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8563b1e8 LL |
1 | /* |
2 | * Copyright © 2016 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
25 | #include "intel_drv.h" | |
26 | ||
82cf435b LL |
27 | #define CTM_COEFF_SIGN (1ULL << 63) |
28 | ||
29 | #define CTM_COEFF_1_0 (1ULL << 32) | |
30 | #define CTM_COEFF_2_0 (CTM_COEFF_1_0 << 1) | |
31 | #define CTM_COEFF_4_0 (CTM_COEFF_2_0 << 1) | |
29dc3739 | 32 | #define CTM_COEFF_8_0 (CTM_COEFF_4_0 << 1) |
82cf435b LL |
33 | #define CTM_COEFF_0_5 (CTM_COEFF_1_0 >> 1) |
34 | #define CTM_COEFF_0_25 (CTM_COEFF_0_5 >> 1) | |
35 | #define CTM_COEFF_0_125 (CTM_COEFF_0_25 >> 1) | |
36 | ||
37 | #define CTM_COEFF_LIMITED_RANGE ((235ULL - 16ULL) * CTM_COEFF_1_0 / 255) | |
38 | ||
39 | #define CTM_COEFF_NEGATIVE(coeff) (((coeff) & CTM_COEFF_SIGN) != 0) | |
40 | #define CTM_COEFF_ABS(coeff) ((coeff) & (CTM_COEFF_SIGN - 1)) | |
41 | ||
42 | #define LEGACY_LUT_LENGTH (sizeof(struct drm_color_lut) * 256) | |
43 | ||
8563b1e8 | 44 | /* |
82cf435b LL |
45 | * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point |
46 | * format). This macro takes the coefficient we want transformed and the | |
47 | * number of fractional bits. | |
8563b1e8 | 48 | * |
82cf435b LL |
49 | * We only have a 9 bits precision window which slides depending on the value |
50 | * of the CTM coefficient and we write the value from bit 3. We also round the | |
51 | * value. | |
8563b1e8 | 52 | */ |
82cf435b LL |
53 | #define I9XX_CSC_COEFF_FP(coeff, fbits) \ |
54 | (clamp_val(((coeff) >> (32 - (fbits) - 3)) + 4, 0, 0xfff) & 0xff8) | |
55 | ||
56 | #define I9XX_CSC_COEFF_LIMITED_RANGE \ | |
57 | I9XX_CSC_COEFF_FP(CTM_COEFF_LIMITED_RANGE, 9) | |
58 | #define I9XX_CSC_COEFF_1_0 \ | |
59 | ((7 << 12) | I9XX_CSC_COEFF_FP(CTM_COEFF_1_0, 8)) | |
60 | ||
61 | static bool crtc_state_is_legacy(struct drm_crtc_state *state) | |
62 | { | |
63 | return !state->degamma_lut && | |
64 | !state->ctm && | |
65 | state->gamma_lut && | |
66 | state->gamma_lut->length == LEGACY_LUT_LENGTH; | |
67 | } | |
68 | ||
69 | /* | |
70 | * When using limited range, multiply the matrix given by userspace by | |
71 | * the matrix that we would use for the limited range. We do the | |
72 | * multiplication in U2.30 format. | |
73 | */ | |
74 | static void ctm_mult_by_limited(uint64_t *result, int64_t *input) | |
75 | { | |
76 | int i; | |
77 | ||
78 | for (i = 0; i < 9; i++) | |
79 | result[i] = 0; | |
80 | ||
81 | for (i = 0; i < 3; i++) { | |
82 | int64_t user_coeff = input[i * 3 + i]; | |
83 | uint64_t limited_coeff = CTM_COEFF_LIMITED_RANGE >> 2; | |
84 | uint64_t abs_coeff = clamp_val(CTM_COEFF_ABS(user_coeff), | |
85 | 0, | |
86 | CTM_COEFF_4_0 - 1) >> 2; | |
87 | ||
88 | result[i * 3 + i] = (limited_coeff * abs_coeff) >> 27; | |
89 | if (CTM_COEFF_NEGATIVE(user_coeff)) | |
90 | result[i * 3 + i] |= CTM_COEFF_SIGN; | |
91 | } | |
92 | } | |
93 | ||
94 | /* Set up the pipe CSC unit. */ | |
b95c5321 | 95 | static void i9xx_load_csc_matrix(struct drm_crtc_state *crtc_state) |
8563b1e8 | 96 | { |
b95c5321 | 97 | struct drm_crtc *crtc = crtc_state->crtc; |
66478475 | 98 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
8563b1e8 | 99 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
82cf435b LL |
100 | int i, pipe = intel_crtc->pipe; |
101 | uint16_t coeffs[9] = { 0, }; | |
1f0017f6 | 102 | struct intel_crtc_state *intel_crtc_state = to_intel_crtc_state(crtc_state); |
82cf435b LL |
103 | |
104 | if (crtc_state->ctm) { | |
105 | struct drm_color_ctm *ctm = | |
106 | (struct drm_color_ctm *)crtc_state->ctm->data; | |
107 | uint64_t input[9] = { 0, }; | |
108 | ||
1f0017f6 | 109 | if (intel_crtc_state->limited_color_range) { |
82cf435b LL |
110 | ctm_mult_by_limited(input, ctm->matrix); |
111 | } else { | |
112 | for (i = 0; i < ARRAY_SIZE(input); i++) | |
113 | input[i] = ctm->matrix[i]; | |
114 | } | |
115 | ||
116 | /* | |
117 | * Convert fixed point S31.32 input to format supported by the | |
118 | * hardware. | |
119 | */ | |
120 | for (i = 0; i < ARRAY_SIZE(coeffs); i++) { | |
121 | uint64_t abs_coeff = ((1ULL << 63) - 1) & input[i]; | |
122 | ||
123 | /* | |
124 | * Clamp input value to min/max supported by | |
125 | * hardware. | |
126 | */ | |
127 | abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_4_0 - 1); | |
128 | ||
129 | /* sign bit */ | |
130 | if (CTM_COEFF_NEGATIVE(input[i])) | |
131 | coeffs[i] |= 1 << 15; | |
132 | ||
133 | if (abs_coeff < CTM_COEFF_0_125) | |
134 | coeffs[i] |= (3 << 12) | | |
135 | I9XX_CSC_COEFF_FP(abs_coeff, 12); | |
136 | else if (abs_coeff < CTM_COEFF_0_25) | |
137 | coeffs[i] |= (2 << 12) | | |
138 | I9XX_CSC_COEFF_FP(abs_coeff, 11); | |
139 | else if (abs_coeff < CTM_COEFF_0_5) | |
140 | coeffs[i] |= (1 << 12) | | |
141 | I9XX_CSC_COEFF_FP(abs_coeff, 10); | |
142 | else if (abs_coeff < CTM_COEFF_1_0) | |
143 | coeffs[i] |= I9XX_CSC_COEFF_FP(abs_coeff, 9); | |
144 | else if (abs_coeff < CTM_COEFF_2_0) | |
145 | coeffs[i] |= (7 << 12) | | |
146 | I9XX_CSC_COEFF_FP(abs_coeff, 8); | |
147 | else | |
148 | coeffs[i] |= (6 << 12) | | |
149 | I9XX_CSC_COEFF_FP(abs_coeff, 7); | |
150 | } | |
151 | } else { | |
152 | /* | |
153 | * Load an identity matrix if no coefficients are provided. | |
154 | * | |
155 | * TODO: Check what kind of values actually come out of the | |
156 | * pipe with these coeff/postoff values and adjust to get the | |
157 | * best accuracy. Perhaps we even need to take the bpc value | |
158 | * into consideration. | |
159 | */ | |
160 | for (i = 0; i < 3; i++) { | |
1f0017f6 | 161 | if (intel_crtc_state->limited_color_range) |
82cf435b LL |
162 | coeffs[i * 3 + i] = |
163 | I9XX_CSC_COEFF_LIMITED_RANGE; | |
164 | else | |
165 | coeffs[i * 3 + i] = I9XX_CSC_COEFF_1_0; | |
166 | } | |
167 | } | |
8563b1e8 | 168 | |
82cf435b LL |
169 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeffs[0] << 16 | coeffs[1]); |
170 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), coeffs[2] << 16); | |
8563b1e8 | 171 | |
82cf435b LL |
172 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeffs[3] << 16 | coeffs[4]); |
173 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), coeffs[5] << 16); | |
8563b1e8 | 174 | |
82cf435b LL |
175 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), coeffs[6] << 16 | coeffs[7]); |
176 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeffs[8] << 16); | |
8563b1e8 LL |
177 | |
178 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
179 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
180 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
181 | ||
66478475 | 182 | if (INTEL_GEN(dev_priv) > 6) { |
8563b1e8 LL |
183 | uint16_t postoff = 0; |
184 | ||
1f0017f6 | 185 | if (intel_crtc_state->limited_color_range) |
8563b1e8 LL |
186 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
187 | ||
188 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
189 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
190 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
191 | ||
192 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
193 | } else { | |
194 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
195 | ||
1f0017f6 | 196 | if (intel_crtc_state->limited_color_range) |
8563b1e8 LL |
197 | mode |= CSC_BLACK_SCREEN_OFFSET; |
198 | ||
199 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
200 | } | |
201 | } | |
202 | ||
29dc3739 LL |
203 | /* |
204 | * Set up the pipe CSC unit on CherryView. | |
205 | */ | |
b95c5321 | 206 | static void cherryview_load_csc_matrix(struct drm_crtc_state *state) |
29dc3739 | 207 | { |
b95c5321 | 208 | struct drm_crtc *crtc = state->crtc; |
29dc3739 | 209 | struct drm_device *dev = crtc->dev; |
fac5e23e | 210 | struct drm_i915_private *dev_priv = to_i915(dev); |
29dc3739 LL |
211 | int pipe = to_intel_crtc(crtc)->pipe; |
212 | uint32_t mode; | |
213 | ||
214 | if (state->ctm) { | |
215 | struct drm_color_ctm *ctm = | |
216 | (struct drm_color_ctm *) state->ctm->data; | |
217 | uint16_t coeffs[9] = { 0, }; | |
218 | int i; | |
219 | ||
220 | for (i = 0; i < ARRAY_SIZE(coeffs); i++) { | |
221 | uint64_t abs_coeff = | |
222 | ((1ULL << 63) - 1) & ctm->matrix[i]; | |
223 | ||
224 | /* Round coefficient. */ | |
225 | abs_coeff += 1 << (32 - 13); | |
226 | /* Clamp to hardware limits. */ | |
227 | abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1); | |
228 | ||
229 | /* Write coefficients in S3.12 format. */ | |
230 | if (ctm->matrix[i] & (1ULL << 63)) | |
231 | coeffs[i] = 1 << 15; | |
232 | coeffs[i] |= ((abs_coeff >> 32) & 7) << 12; | |
233 | coeffs[i] |= (abs_coeff >> 20) & 0xfff; | |
234 | } | |
235 | ||
236 | I915_WRITE(CGM_PIPE_CSC_COEFF01(pipe), | |
237 | coeffs[1] << 16 | coeffs[0]); | |
238 | I915_WRITE(CGM_PIPE_CSC_COEFF23(pipe), | |
239 | coeffs[3] << 16 | coeffs[2]); | |
240 | I915_WRITE(CGM_PIPE_CSC_COEFF45(pipe), | |
241 | coeffs[5] << 16 | coeffs[4]); | |
242 | I915_WRITE(CGM_PIPE_CSC_COEFF67(pipe), | |
243 | coeffs[7] << 16 | coeffs[6]); | |
244 | I915_WRITE(CGM_PIPE_CSC_COEFF8(pipe), coeffs[8]); | |
245 | } | |
246 | ||
247 | mode = (state->ctm ? CGM_PIPE_MODE_CSC : 0); | |
248 | if (!crtc_state_is_legacy(state)) { | |
249 | mode |= (state->degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) | | |
250 | (state->gamma_lut ? CGM_PIPE_MODE_GAMMA : 0); | |
251 | } | |
252 | I915_WRITE(CGM_PIPE_MODE(pipe), mode); | |
253 | } | |
254 | ||
b95c5321 | 255 | void intel_color_set_csc(struct drm_crtc_state *crtc_state) |
8563b1e8 | 256 | { |
b95c5321 | 257 | struct drm_device *dev = crtc_state->crtc->dev; |
fac5e23e | 258 | struct drm_i915_private *dev_priv = to_i915(dev); |
82cf435b LL |
259 | |
260 | if (dev_priv->display.load_csc_matrix) | |
b95c5321 | 261 | dev_priv->display.load_csc_matrix(crtc_state); |
8563b1e8 LL |
262 | } |
263 | ||
82cf435b | 264 | /* Loads the legacy palette/gamma unit for the CRTC. */ |
29dc3739 | 265 | static void i9xx_load_luts_internal(struct drm_crtc *crtc, |
1f0017f6 ML |
266 | struct drm_property_blob *blob, |
267 | struct intel_crtc_state *crtc_state) | |
8563b1e8 LL |
268 | { |
269 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 270 | struct drm_i915_private *dev_priv = to_i915(dev); |
8563b1e8 LL |
271 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
272 | enum pipe pipe = intel_crtc->pipe; | |
273 | int i; | |
274 | ||
49cff963 | 275 | if (HAS_GMCH_DISPLAY(dev_priv)) { |
1f0017f6 | 276 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) |
8563b1e8 LL |
277 | assert_dsi_pll_enabled(dev_priv); |
278 | else | |
279 | assert_pll_enabled(dev_priv, pipe); | |
280 | } | |
281 | ||
29dc3739 LL |
282 | if (blob) { |
283 | struct drm_color_lut *lut = (struct drm_color_lut *) blob->data; | |
82cf435b LL |
284 | for (i = 0; i < 256; i++) { |
285 | uint32_t word = | |
286 | (drm_color_lut_extract(lut[i].red, 8) << 16) | | |
287 | (drm_color_lut_extract(lut[i].green, 8) << 8) | | |
288 | drm_color_lut_extract(lut[i].blue, 8); | |
289 | ||
49cff963 | 290 | if (HAS_GMCH_DISPLAY(dev_priv)) |
82cf435b LL |
291 | I915_WRITE(PALETTE(pipe, i), word); |
292 | else | |
293 | I915_WRITE(LGC_PALETTE(pipe, i), word); | |
294 | } | |
295 | } else { | |
296 | for (i = 0; i < 256; i++) { | |
297 | uint32_t word = (i << 16) | (i << 8) | i; | |
298 | ||
49cff963 | 299 | if (HAS_GMCH_DISPLAY(dev_priv)) |
82cf435b LL |
300 | I915_WRITE(PALETTE(pipe, i), word); |
301 | else | |
302 | I915_WRITE(LGC_PALETTE(pipe, i), word); | |
303 | } | |
8563b1e8 LL |
304 | } |
305 | } | |
306 | ||
b95c5321 | 307 | static void i9xx_load_luts(struct drm_crtc_state *crtc_state) |
29dc3739 | 308 | { |
1f0017f6 ML |
309 | i9xx_load_luts_internal(crtc_state->crtc, crtc_state->gamma_lut, |
310 | to_intel_crtc_state(crtc_state)); | |
29dc3739 LL |
311 | } |
312 | ||
82cf435b | 313 | /* Loads the legacy palette/gamma unit for the CRTC on Haswell. */ |
b95c5321 | 314 | static void haswell_load_luts(struct drm_crtc_state *crtc_state) |
8563b1e8 | 315 | { |
b95c5321 | 316 | struct drm_crtc *crtc = crtc_state->crtc; |
8563b1e8 | 317 | struct drm_device *dev = crtc->dev; |
fac5e23e | 318 | struct drm_i915_private *dev_priv = to_i915(dev); |
8563b1e8 | 319 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
05dc698c | 320 | struct intel_crtc_state *intel_crtc_state = |
b95c5321 | 321 | to_intel_crtc_state(crtc_state); |
8563b1e8 LL |
322 | bool reenable_ips = false; |
323 | ||
324 | /* | |
325 | * Workaround : Do not read or write the pipe palette/gamma data while | |
326 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
327 | */ | |
772c2a51 | 328 | if (IS_HASWELL(dev_priv) && intel_crtc_state->ips_enabled && |
05dc698c | 329 | (intel_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)) { |
8563b1e8 LL |
330 | hsw_disable_ips(intel_crtc); |
331 | reenable_ips = true; | |
332 | } | |
05dc698c LL |
333 | |
334 | intel_crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT; | |
8563b1e8 LL |
335 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); |
336 | ||
b95c5321 | 337 | i9xx_load_luts(crtc_state); |
8563b1e8 LL |
338 | |
339 | if (reenable_ips) | |
340 | hsw_enable_ips(intel_crtc); | |
341 | } | |
342 | ||
2fcb2066 | 343 | static void bdw_load_degamma_lut(struct drm_crtc_state *state) |
82cf435b | 344 | { |
2fcb2066 ACO |
345 | struct drm_i915_private *dev_priv = to_i915(state->crtc->dev); |
346 | enum pipe pipe = to_intel_crtc(state->crtc)->pipe; | |
b7f05d4a | 347 | uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size; |
82cf435b | 348 | |
82cf435b LL |
349 | I915_WRITE(PREC_PAL_INDEX(pipe), |
350 | PAL_PREC_SPLIT_MODE | PAL_PREC_AUTO_INCREMENT); | |
351 | ||
352 | if (state->degamma_lut) { | |
353 | struct drm_color_lut *lut = | |
354 | (struct drm_color_lut *) state->degamma_lut->data; | |
355 | ||
356 | for (i = 0; i < lut_size; i++) { | |
357 | uint32_t word = | |
358 | drm_color_lut_extract(lut[i].red, 10) << 20 | | |
359 | drm_color_lut_extract(lut[i].green, 10) << 10 | | |
360 | drm_color_lut_extract(lut[i].blue, 10); | |
361 | ||
362 | I915_WRITE(PREC_PAL_DATA(pipe), word); | |
363 | } | |
364 | } else { | |
365 | for (i = 0; i < lut_size; i++) { | |
366 | uint32_t v = (i * ((1 << 10) - 1)) / (lut_size - 1); | |
367 | ||
368 | I915_WRITE(PREC_PAL_DATA(pipe), | |
369 | (v << 20) | (v << 10) | v); | |
370 | } | |
371 | } | |
2fcb2066 ACO |
372 | } |
373 | ||
374 | static void bdw_load_gamma_lut(struct drm_crtc_state *state, u32 offset) | |
375 | { | |
376 | struct drm_i915_private *dev_priv = to_i915(state->crtc->dev); | |
377 | enum pipe pipe = to_intel_crtc(state->crtc)->pipe; | |
378 | uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; | |
379 | ||
380 | WARN_ON(offset & ~PAL_PREC_INDEX_VALUE_MASK); | |
381 | ||
382 | I915_WRITE(PREC_PAL_INDEX(pipe), | |
9751bafc ACO |
383 | (offset ? PAL_PREC_SPLIT_MODE : 0) | |
384 | PAL_PREC_AUTO_INCREMENT | | |
385 | offset); | |
82cf435b LL |
386 | |
387 | if (state->gamma_lut) { | |
388 | struct drm_color_lut *lut = | |
389 | (struct drm_color_lut *) state->gamma_lut->data; | |
390 | ||
391 | for (i = 0; i < lut_size; i++) { | |
392 | uint32_t word = | |
393 | (drm_color_lut_extract(lut[i].red, 10) << 20) | | |
394 | (drm_color_lut_extract(lut[i].green, 10) << 10) | | |
395 | drm_color_lut_extract(lut[i].blue, 10); | |
396 | ||
397 | I915_WRITE(PREC_PAL_DATA(pipe), word); | |
398 | } | |
399 | ||
400 | /* Program the max register to clamp values > 1.0. */ | |
401 | I915_WRITE(PREC_PAL_GC_MAX(pipe, 0), | |
402 | drm_color_lut_extract(lut[i].red, 16)); | |
403 | I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), | |
404 | drm_color_lut_extract(lut[i].green, 16)); | |
405 | I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), | |
406 | drm_color_lut_extract(lut[i].blue, 16)); | |
407 | } else { | |
408 | for (i = 0; i < lut_size; i++) { | |
409 | uint32_t v = (i * ((1 << 10) - 1)) / (lut_size - 1); | |
410 | ||
411 | I915_WRITE(PREC_PAL_DATA(pipe), | |
412 | (v << 20) | (v << 10) | v); | |
413 | } | |
414 | ||
415 | I915_WRITE(PREC_PAL_GC_MAX(pipe, 0), (1 << 16) - 1); | |
416 | I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), (1 << 16) - 1); | |
417 | I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), (1 << 16) - 1); | |
418 | } | |
2fcb2066 ACO |
419 | } |
420 | ||
421 | /* Loads the palette/gamma unit for the CRTC on Broadwell+. */ | |
422 | static void broadwell_load_luts(struct drm_crtc_state *state) | |
423 | { | |
424 | struct drm_i915_private *dev_priv = to_i915(state->crtc->dev); | |
425 | struct intel_crtc_state *intel_state = to_intel_crtc_state(state); | |
426 | enum pipe pipe = to_intel_crtc(state->crtc)->pipe; | |
427 | ||
428 | if (crtc_state_is_legacy(state)) { | |
429 | haswell_load_luts(state); | |
430 | return; | |
431 | } | |
432 | ||
433 | bdw_load_degamma_lut(state); | |
434 | bdw_load_gamma_lut(state, | |
435 | INTEL_INFO(dev_priv)->color.degamma_lut_size); | |
82cf435b LL |
436 | |
437 | intel_state->gamma_mode = GAMMA_MODE_MODE_SPLIT; | |
438 | I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_SPLIT); | |
439 | POSTING_READ(GAMMA_MODE(pipe)); | |
440 | ||
441 | /* | |
442 | * Reset the index, otherwise it prevents the legacy palette to be | |
443 | * written properly. | |
444 | */ | |
445 | I915_WRITE(PREC_PAL_INDEX(pipe), 0); | |
446 | } | |
447 | ||
9751bafc ACO |
448 | static void glk_load_degamma_lut(struct drm_crtc_state *state) |
449 | { | |
450 | struct drm_i915_private *dev_priv = to_i915(state->crtc->dev); | |
451 | enum pipe pipe = to_intel_crtc(state->crtc)->pipe; | |
452 | const uint32_t lut_size = 33; | |
453 | uint32_t i; | |
454 | ||
455 | /* | |
456 | * When setting the auto-increment bit, the hardware seems to | |
457 | * ignore the index bits, so we need to reset it to index 0 | |
458 | * separately. | |
459 | */ | |
460 | I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), 0); | |
461 | I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), PRE_CSC_GAMC_AUTO_INCREMENT); | |
462 | ||
463 | /* | |
464 | * FIXME: The pipe degamma table in geminilake doesn't support | |
465 | * different values per channel, so this just loads a linear table. | |
466 | */ | |
467 | for (i = 0; i < lut_size; i++) { | |
3465dbdd | 468 | uint32_t v = (i * (1 << 16)) / (lut_size - 1); |
9751bafc ACO |
469 | |
470 | I915_WRITE(PRE_CSC_GAMC_DATA(pipe), v); | |
471 | } | |
472 | ||
473 | /* Clamp values > 1.0. */ | |
474 | while (i++ < 35) | |
3465dbdd | 475 | I915_WRITE(PRE_CSC_GAMC_DATA(pipe), (1 << 16)); |
9751bafc ACO |
476 | } |
477 | ||
478 | static void glk_load_luts(struct drm_crtc_state *state) | |
479 | { | |
480 | struct drm_crtc *crtc = state->crtc; | |
481 | struct drm_device *dev = crtc->dev; | |
482 | struct drm_i915_private *dev_priv = to_i915(dev); | |
483 | struct intel_crtc_state *intel_state = to_intel_crtc_state(state); | |
484 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
485 | ||
8d371db4 ACO |
486 | glk_load_degamma_lut(state); |
487 | ||
9751bafc ACO |
488 | if (crtc_state_is_legacy(state)) { |
489 | haswell_load_luts(state); | |
490 | return; | |
491 | } | |
492 | ||
9751bafc ACO |
493 | bdw_load_gamma_lut(state, 0); |
494 | ||
495 | intel_state->gamma_mode = GAMMA_MODE_MODE_10BIT; | |
496 | I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_10BIT); | |
497 | POSTING_READ(GAMMA_MODE(pipe)); | |
498 | } | |
499 | ||
29dc3739 | 500 | /* Loads the palette/gamma unit for the CRTC on CherryView. */ |
b95c5321 | 501 | static void cherryview_load_luts(struct drm_crtc_state *state) |
29dc3739 | 502 | { |
b95c5321 | 503 | struct drm_crtc *crtc = state->crtc; |
b7f05d4a | 504 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
29dc3739 LL |
505 | enum pipe pipe = to_intel_crtc(crtc)->pipe; |
506 | struct drm_color_lut *lut; | |
507 | uint32_t i, lut_size; | |
508 | uint32_t word0, word1; | |
509 | ||
510 | if (crtc_state_is_legacy(state)) { | |
511 | /* Turn off degamma/gamma on CGM block. */ | |
512 | I915_WRITE(CGM_PIPE_MODE(pipe), | |
513 | (state->ctm ? CGM_PIPE_MODE_CSC : 0)); | |
1f0017f6 ML |
514 | i9xx_load_luts_internal(crtc, state->gamma_lut, |
515 | to_intel_crtc_state(state)); | |
29dc3739 LL |
516 | return; |
517 | } | |
518 | ||
519 | if (state->degamma_lut) { | |
520 | lut = (struct drm_color_lut *) state->degamma_lut->data; | |
b7f05d4a | 521 | lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size; |
29dc3739 LL |
522 | for (i = 0; i < lut_size; i++) { |
523 | /* Write LUT in U0.14 format. */ | |
524 | word0 = | |
525 | (drm_color_lut_extract(lut[i].green, 14) << 16) | | |
526 | drm_color_lut_extract(lut[i].blue, 14); | |
527 | word1 = drm_color_lut_extract(lut[i].red, 14); | |
528 | ||
529 | I915_WRITE(CGM_PIPE_DEGAMMA(pipe, i, 0), word0); | |
530 | I915_WRITE(CGM_PIPE_DEGAMMA(pipe, i, 1), word1); | |
531 | } | |
532 | } | |
533 | ||
534 | if (state->gamma_lut) { | |
535 | lut = (struct drm_color_lut *) state->gamma_lut->data; | |
b7f05d4a | 536 | lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; |
29dc3739 LL |
537 | for (i = 0; i < lut_size; i++) { |
538 | /* Write LUT in U0.10 format. */ | |
539 | word0 = | |
540 | (drm_color_lut_extract(lut[i].green, 10) << 16) | | |
541 | drm_color_lut_extract(lut[i].blue, 10); | |
542 | word1 = drm_color_lut_extract(lut[i].red, 10); | |
543 | ||
544 | I915_WRITE(CGM_PIPE_GAMMA(pipe, i, 0), word0); | |
545 | I915_WRITE(CGM_PIPE_GAMMA(pipe, i, 1), word1); | |
546 | } | |
547 | } | |
548 | ||
549 | I915_WRITE(CGM_PIPE_MODE(pipe), | |
550 | (state->ctm ? CGM_PIPE_MODE_CSC : 0) | | |
551 | (state->degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) | | |
552 | (state->gamma_lut ? CGM_PIPE_MODE_GAMMA : 0)); | |
553 | ||
554 | /* | |
555 | * Also program a linear LUT in the legacy block (behind the | |
556 | * CGM block). | |
557 | */ | |
1f0017f6 | 558 | i9xx_load_luts_internal(crtc, NULL, to_intel_crtc_state(state)); |
29dc3739 LL |
559 | } |
560 | ||
b95c5321 | 561 | void intel_color_load_luts(struct drm_crtc_state *crtc_state) |
8563b1e8 | 562 | { |
b95c5321 | 563 | struct drm_device *dev = crtc_state->crtc->dev; |
fac5e23e | 564 | struct drm_i915_private *dev_priv = to_i915(dev); |
8563b1e8 | 565 | |
b95c5321 | 566 | dev_priv->display.load_luts(crtc_state); |
8563b1e8 LL |
567 | } |
568 | ||
82cf435b LL |
569 | int intel_color_check(struct drm_crtc *crtc, |
570 | struct drm_crtc_state *crtc_state) | |
8563b1e8 | 571 | { |
b7f05d4a | 572 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
82cf435b | 573 | size_t gamma_length, degamma_length; |
8563b1e8 | 574 | |
b7f05d4a | 575 | degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size * |
82cf435b | 576 | sizeof(struct drm_color_lut); |
b7f05d4a | 577 | gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size * |
82cf435b | 578 | sizeof(struct drm_color_lut); |
8563b1e8 | 579 | |
82cf435b LL |
580 | /* |
581 | * We allow both degamma & gamma luts at the right size or | |
582 | * NULL. | |
583 | */ | |
584 | if ((!crtc_state->degamma_lut || | |
585 | crtc_state->degamma_lut->length == degamma_length) && | |
586 | (!crtc_state->gamma_lut || | |
587 | crtc_state->gamma_lut->length == gamma_length)) | |
588 | return 0; | |
589 | ||
590 | /* | |
591 | * We also allow no degamma lut and a gamma lut at the legacy | |
592 | * size (256 entries). | |
593 | */ | |
594 | if (!crtc_state->degamma_lut && | |
595 | crtc_state->gamma_lut && | |
596 | crtc_state->gamma_lut->length == LEGACY_LUT_LENGTH) | |
597 | return 0; | |
598 | ||
599 | return -EINVAL; | |
8563b1e8 LL |
600 | } |
601 | ||
602 | void intel_color_init(struct drm_crtc *crtc) | |
603 | { | |
b7f05d4a | 604 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
8563b1e8 LL |
605 | |
606 | drm_mode_crtc_set_gamma_size(crtc, 256); | |
8563b1e8 | 607 | |
920a14b2 | 608 | if (IS_CHERRYVIEW(dev_priv)) { |
29dc3739 LL |
609 | dev_priv->display.load_csc_matrix = cherryview_load_csc_matrix; |
610 | dev_priv->display.load_luts = cherryview_load_luts; | |
772c2a51 | 611 | } else if (IS_HASWELL(dev_priv)) { |
82cf435b | 612 | dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix; |
8563b1e8 | 613 | dev_priv->display.load_luts = haswell_load_luts; |
b976dc53 RV |
614 | } else if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv) || |
615 | IS_BROXTON(dev_priv)) { | |
82cf435b LL |
616 | dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix; |
617 | dev_priv->display.load_luts = broadwell_load_luts; | |
6602be0e | 618 | } else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) { |
9751bafc ACO |
619 | dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix; |
620 | dev_priv->display.load_luts = glk_load_luts; | |
8563b1e8 LL |
621 | } else { |
622 | dev_priv->display.load_luts = i9xx_load_luts; | |
623 | } | |
82cf435b LL |
624 | |
625 | /* Enable color management support when we have degamma & gamma LUTs. */ | |
b7f05d4a TU |
626 | if (INTEL_INFO(dev_priv)->color.degamma_lut_size != 0 && |
627 | INTEL_INFO(dev_priv)->color.gamma_lut_size != 0) | |
f8ed34ac | 628 | drm_crtc_enable_color_mgmt(crtc, |
b7f05d4a TU |
629 | INTEL_INFO(dev_priv)->color.degamma_lut_size, |
630 | true, | |
631 | INTEL_INFO(dev_priv)->color.gamma_lut_size); | |
8563b1e8 | 632 | } |