[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_crt.c

/*
 * Copyright © 2006-2007 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *	Eric Anholt <eric@anholt.net>
 */

#include <linux/i2c.h>
#include <linux/slab.h>
#include "drmP.h"
#include "drm.h"
#include "drm_crtc.h"
#include "drm_crtc_helper.h"
#include "intel_drv.h"
#include "i915_drm.h"
#include "i915_drv.h"

/* Here's the desired hotplug mode */
#define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 |		\
			   ADPA_CRT_HOTPLUG_WARMUP_10MS |		\
			   ADPA_CRT_HOTPLUG_SAMPLE_4S |			\
			   ADPA_CRT_HOTPLUG_VOLTAGE_50 |		\
			   ADPA_CRT_HOTPLUG_VOLREF_325MV |		\
			   ADPA_CRT_HOTPLUG_ENABLE)

struct intel_crt {
	struct intel_encoder base;
	bool force_hotplug_required;
};

static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
{
	return container_of(intel_attached_encoder(connector),
			    struct intel_crt, base);
}

static void intel_crt_dpms(struct drm_encoder *encoder, int mode)
{
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 temp, reg;

	if (HAS_PCH_SPLIT(dev))
		reg = PCH_ADPA;
	else
		reg = ADPA;

	temp = I915_READ(reg);
	temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
	temp &= ~ADPA_DAC_ENABLE;

	switch(mode) {
	case DRM_MODE_DPMS_ON:
		temp |= ADPA_DAC_ENABLE;
		break;
	case DRM_MODE_DPMS_STANDBY:
		temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
		break;
	case DRM_MODE_DPMS_SUSPEND:
		temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
		break;
	case DRM_MODE_DPMS_OFF:
		temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
		break;
	}

	I915_WRITE(reg, temp);
}

static int intel_crt_mode_valid(struct drm_connector *connector,
				struct drm_display_mode *mode)
{
	struct drm_device *dev = connector->dev;

	int max_clock = 0;
	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
		return MODE_NO_DBLESCAN;

	if (mode->clock < 25000)
		return MODE_CLOCK_LOW;

	if (IS_GEN2(dev))
		max_clock = 350000;
	else
		max_clock = 400000;
	if (mode->clock > max_clock)
		return MODE_CLOCK_HIGH;

	return MODE_OK;
}

static bool intel_crt_mode_fixup(struct drm_encoder *encoder,
				 struct drm_display_mode *mode,
				 struct drm_display_mode *adjusted_mode)
{
	return true;
}

static void intel_crt_mode_set(struct drm_encoder *encoder,
			       struct drm_display_mode *mode,
			       struct drm_display_mode *adjusted_mode)
{

	struct drm_device *dev = encoder->dev;
	struct drm_crtc *crtc = encoder->crtc;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct drm_i915_private *dev_priv = dev->dev_private;
	int dpll_md_reg;
	u32 adpa, dpll_md;
	u32 adpa_reg;

	if (intel_crtc->pipe == 0)
		dpll_md_reg = DPLL_A_MD;
	else
		dpll_md_reg = DPLL_B_MD;

	if (HAS_PCH_SPLIT(dev))
		adpa_reg = PCH_ADPA;
	else
		adpa_reg = ADPA;

	/*
	 * Disable separate mode multiplier used when cloning SDVO to CRT
	 * XXX this needs to be adjusted when we really are cloning
	 */
	if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
		dpll_md = I915_READ(dpll_md_reg);
		I915_WRITE(dpll_md_reg,
			   dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK);
	}

	adpa = ADPA_HOTPLUG_BITS;
	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
		adpa |= ADPA_HSYNC_ACTIVE_HIGH;
	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
		adpa |= ADPA_VSYNC_ACTIVE_HIGH;

	if (intel_crtc->pipe == 0) {
		if (HAS_PCH_CPT(dev))
			adpa |= PORT_TRANS_A_SEL_CPT;
		else
			adpa |= ADPA_PIPE_A_SELECT;
		if (!HAS_PCH_SPLIT(dev))
			I915_WRITE(BCLRPAT_A, 0);
	} else {
		if (HAS_PCH_CPT(dev))
			adpa |= PORT_TRANS_B_SEL_CPT;
		else
			adpa |= ADPA_PIPE_B_SELECT;
		if (!HAS_PCH_SPLIT(dev))
			I915_WRITE(BCLRPAT_B, 0);
	}

	I915_WRITE(adpa_reg, adpa);
}

static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
{
	struct drm_device *dev = connector->dev;
	struct intel_crt *crt = intel_attached_crt(connector);
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 adpa;
	bool ret;

	/* The first time through, trigger an explicit detection cycle */
	if (crt->force_hotplug_required) {
		bool turn_off_dac = HAS_PCH_SPLIT(dev);
		u32 save_adpa;

		crt->force_hotplug_required = 0;

		save_adpa = adpa = I915_READ(PCH_ADPA);
		DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);

		adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
		if (turn_off_dac)
			adpa &= ~ADPA_DAC_ENABLE;

		I915_WRITE(PCH_ADPA, adpa);

		if (wait_for((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
			     1000))
			DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");

		if (turn_off_dac) {
			I915_WRITE(PCH_ADPA, save_adpa);
			POSTING_READ(PCH_ADPA);
		}
	}

	/* Check the status to see if both blue and green are on now */
	adpa = I915_READ(PCH_ADPA);
	if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
		ret = true;
	else
		ret = false;
	DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);

	return ret;
}

/**
 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
 *
 * Not for i915G/i915GM
 *
 * \return true if CRT is connected.
 * \return false if CRT is disconnected.
 */
static bool intel_crt_detect_hotplug(struct drm_connector *connector)
{
	struct drm_device *dev = connector->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 hotplug_en, orig, stat;
	bool ret = false;
	int i, tries = 0;

	if (HAS_PCH_SPLIT(dev))
		return intel_ironlake_crt_detect_hotplug(connector);

	/*
	 * On 4 series desktop, CRT detect sequence need to be done twice
	 * to get a reliable result.
	 */

	if (IS_G4X(dev) && !IS_GM45(dev))
		tries = 2;
	else
		tries = 1;
	hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN);
	hotplug_en |= CRT_HOTPLUG_FORCE_DETECT;

	for (i = 0; i < tries ; i++) {
		/* turn on the FORCE_DETECT */
		I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
		/* wait for FORCE_DETECT to go off */
		if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
			      CRT_HOTPLUG_FORCE_DETECT) == 0,
			     1000))
			DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
	}

	stat = I915_READ(PORT_HOTPLUG_STAT);
	if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
		ret = true;

	/* clear the interrupt we just generated, if any */
	I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);

	/* and put the bits back */
	I915_WRITE(PORT_HOTPLUG_EN, orig);

	return ret;
}

static bool intel_crt_ddc_probe(struct drm_i915_private *dev_priv, int ddc_bus)
{
	u8 buf;
	struct i2c_msg msgs[] = {
		{
			.addr = 0xA0,
			.flags = 0,
			.len = 1,
			.buf = &buf,
		},
	};
	/* DDC monitor detect: Does it ACK a write to 0xA0? */
	return i2c_transfer(&dev_priv->gmbus[ddc_bus].adapter, msgs, 1) == 1;
}

static bool intel_crt_detect_ddc(struct intel_crt *crt)
{
	struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private;

	/* CRT should always be at 0, but check anyway */
	if (crt->base.type != INTEL_OUTPUT_ANALOG)
		return false;

	if (intel_crt_ddc_probe(dev_priv, dev_priv->crt_ddc_pin)) {
		DRM_DEBUG_KMS("CRT detected via DDC:0xa0\n");
		return true;
	}

	if (intel_ddc_probe(&crt->base, dev_priv->crt_ddc_pin)) {
		DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
		return true;
	}

	return false;
}

static enum drm_connector_status
intel_crt_load_detect(struct drm_crtc *crtc, struct intel_crt *crt)
{
	struct drm_encoder *encoder = &crt->base.base;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	uint32_t pipe = intel_crtc->pipe;
	uint32_t save_bclrpat;
	uint32_t save_vtotal;
	uint32_t vtotal, vactive;
	uint32_t vsample;
	uint32_t vblank, vblank_start, vblank_end;
	uint32_t dsl;
	uint32_t bclrpat_reg;
	uint32_t vtotal_reg;
	uint32_t vblank_reg;
	uint32_t vsync_reg;
	uint32_t pipeconf_reg;
	uint32_t pipe_dsl_reg;
	uint8_t	st00;
	enum drm_connector_status status;

	DRM_DEBUG_KMS("starting load-detect on CRT\n");

	if (pipe == 0) {
		bclrpat_reg = BCLRPAT_A;
		vtotal_reg = VTOTAL_A;
		vblank_reg = VBLANK_A;
		vsync_reg = VSYNC_A;
		pipeconf_reg = PIPEACONF;
		pipe_dsl_reg = PIPEADSL;
	} else {
		bclrpat_reg = BCLRPAT_B;
		vtotal_reg = VTOTAL_B;
		vblank_reg = VBLANK_B;
		vsync_reg = VSYNC_B;
		pipeconf_reg = PIPEBCONF;
		pipe_dsl_reg = PIPEBDSL;
	}

	save_bclrpat = I915_READ(bclrpat_reg);
	save_vtotal = I915_READ(vtotal_reg);
	vblank = I915_READ(vblank_reg);

	vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
	vactive = (save_vtotal & 0x7ff) + 1;

	vblank_start = (vblank & 0xfff) + 1;
	vblank_end = ((vblank >> 16) & 0xfff) + 1;

	/* Set the border color to purple. */
	I915_WRITE(bclrpat_reg, 0x500050);

	if (!IS_GEN2(dev)) {
		uint32_t pipeconf = I915_READ(pipeconf_reg);
		I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
		POSTING_READ(pipeconf_reg);
		/* Wait for next Vblank to substitue
		 * border color for Color info */
		intel_wait_for_vblank(dev, pipe);
		st00 = I915_READ8(VGA_MSR_WRITE);
		status = ((st00 & (1 << 4)) != 0) ?
			connector_status_connected :
			connector_status_disconnected;

		I915_WRITE(pipeconf_reg, pipeconf);
	} else {
		bool restore_vblank = false;
		int count, detect;

		/*
		* If there isn't any border, add some.
		* Yes, this will flicker
		*/
		if (vblank_start <= vactive && vblank_end >= vtotal) {
			uint32_t vsync = I915_READ(vsync_reg);
			uint32_t vsync_start = (vsync & 0xffff) + 1;

			vblank_start = vsync_start;
			I915_WRITE(vblank_reg,
				   (vblank_start - 1) |
				   ((vblank_end - 1) << 16));
			restore_vblank = true;
		}
		/* sample in the vertical border, selecting the larger one */
		if (vblank_start - vactive >= vtotal - vblank_end)
			vsample = (vblank_start + vactive) >> 1;
		else
			vsample = (vtotal + vblank_end) >> 1;

		/*
		 * Wait for the border to be displayed
		 */
		while (I915_READ(pipe_dsl_reg) >= vactive)
			;
		while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
			;
		/*
		 * Watch ST00 for an entire scanline
		 */
		detect = 0;
		count = 0;
		do {
			count++;
			/* Read the ST00 VGA status register */
			st00 = I915_READ8(VGA_MSR_WRITE);
			if (st00 & (1 << 4))
				detect++;
		} while ((I915_READ(pipe_dsl_reg) == dsl));

		/* restore vblank if necessary */
		if (restore_vblank)
			I915_WRITE(vblank_reg, vblank);
		/*
		 * If more than 3/4 of the scanline detected a monitor,
		 * then it is assumed to be present. This works even on i830,
		 * where there isn't any way to force the border color across
		 * the screen
		 */
		status = detect * 4 > count * 3 ?
			 connector_status_connected :
			 connector_status_disconnected;
	}

	/* Restore previous settings */
	I915_WRITE(bclrpat_reg, save_bclrpat);

	return status;
}

static enum drm_connector_status
intel_crt_detect(struct drm_connector *connector, bool force)
{
	struct drm_device *dev = connector->dev;
	struct intel_crt *crt = intel_attached_crt(connector);
	struct drm_crtc *crtc;
	int dpms_mode;
	enum drm_connector_status status;

	if (I915_HAS_HOTPLUG(dev)) {
		if (intel_crt_detect_hotplug(connector)) {
			DRM_DEBUG_KMS("CRT detected via hotplug\n");
			return connector_status_connected;
		} else {
			DRM_DEBUG_KMS("CRT not detected via hotplug\n");
			return connector_status_disconnected;
		}
	}

	if (intel_crt_detect_ddc(crt))
		return connector_status_connected;

	if (!force)
		return connector->status;

	/* for pre-945g platforms use load detect */
	crtc = crt->base.base.crtc;
	if (crtc && crtc->enabled) {
		status = intel_crt_load_detect(crtc, crt);
	} else {
		crtc = intel_get_load_detect_pipe(&crt->base, connector,
						  NULL, &dpms_mode);
		if (crtc) {
			if (intel_crt_detect_ddc(crt))
				status = connector_status_connected;
			else
				status = intel_crt_load_detect(crtc, crt);
			intel_release_load_detect_pipe(&crt->base,
						       connector, dpms_mode);
		} else
			status = connector_status_unknown;
	}

	return status;
}

static void intel_crt_destroy(struct drm_connector *connector)
{
	drm_sysfs_connector_remove(connector);
	drm_connector_cleanup(connector);
	kfree(connector);
}

static int intel_crt_get_modes(struct drm_connector *connector)
{
	struct drm_device *dev = connector->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;

	ret = intel_ddc_get_modes(connector,
				 &dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter);
	if (ret || !IS_G4X(dev))
		return ret;

	/* Try to probe digital port for output in DVI-I -> VGA mode. */
	return intel_ddc_get_modes(connector,
				   &dev_priv->gmbus[GMBUS_PORT_DPB].adapter);
}

static int intel_crt_set_property(struct drm_connector *connector,
				  struct drm_property *property,
				  uint64_t value)
{
	return 0;
}

/*
 * Routines for controlling stuff on the analog port
 */

static const struct drm_encoder_helper_funcs intel_crt_helper_funcs = {
	.dpms = intel_crt_dpms,
	.mode_fixup = intel_crt_mode_fixup,
	.prepare = intel_encoder_prepare,
	.commit = intel_encoder_commit,
	.mode_set = intel_crt_mode_set,
};

static const struct drm_connector_funcs intel_crt_connector_funcs = {
	.dpms = drm_helper_connector_dpms,
	.detect = intel_crt_detect,
	.fill_modes = drm_helper_probe_single_connector_modes,
	.destroy = intel_crt_destroy,
	.set_property = intel_crt_set_property,
};

static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
	.mode_valid = intel_crt_mode_valid,
	.get_modes = intel_crt_get_modes,
	.best_encoder = intel_best_encoder,
};

static const struct drm_encoder_funcs intel_crt_enc_funcs = {
	.destroy = intel_encoder_destroy,
};

void intel_crt_init(struct drm_device *dev)
{
	struct drm_connector *connector;
	struct intel_crt *crt;
	struct intel_connector *intel_connector;
	struct drm_i915_private *dev_priv = dev->dev_private;

	crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
	if (!crt)
		return;

	intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
	if (!intel_connector) {
		kfree(crt);
		return;
	}

	connector = &intel_connector->base;
	drm_connector_init(dev, &intel_connector->base,
			   &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);

	drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs,
			 DRM_MODE_ENCODER_DAC);

	intel_connector_attach_encoder(intel_connector, &crt->base);

	crt->base.type = INTEL_OUTPUT_ANALOG;
	crt->base.clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT |
				1 << INTEL_ANALOG_CLONE_BIT |
				1 << INTEL_SDVO_LVDS_CLONE_BIT);
	crt->base.crtc_mask = (1 << 0) | (1 << 1);
	connector->interlace_allowed = 1;
	connector->doublescan_allowed = 0;

	drm_encoder_helper_add(&crt->base.base, &intel_crt_helper_funcs);
	drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);

	drm_sysfs_connector_add(connector);

	if (I915_HAS_HOTPLUG(dev))
		connector->polled = DRM_CONNECTOR_POLL_HPD;
	else
		connector->polled = DRM_CONNECTOR_POLL_CONNECT;

	/*
	 * Configure the automatic hotplug detection stuff
	 */
	crt->force_hotplug_required = 0;
	if (HAS_PCH_SPLIT(dev)) {
		u32 adpa;

		adpa = I915_READ(PCH_ADPA);
		adpa &= ~ADPA_CRT_HOTPLUG_MASK;
		adpa |= ADPA_HOTPLUG_BITS;
		I915_WRITE(PCH_ADPA, adpa);
		POSTING_READ(PCH_ADPA);

		DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa);
		crt->force_hotplug_required = 1;
	}

	dev_priv->hotplug_supported_mask |= CRT_HOTPLUG_INT_STATUS;
}
Commit	Line	Data
79e53945 JB	1	/*
	2	* Copyright © 2006-2007 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	21	* DEALINGS IN THE SOFTWARE.
	22	*
	23	* Authors:
	24	* Eric Anholt <eric@anholt.net>
	25	*/
	26
	27	#include <linux/i2c.h>
5a0e3ad6	28	#include <linux/slab.h>
79e53945 JB	29	#include "drmP.h"
	30	#include "drm.h"
	31	#include "drm_crtc.h"
	32	#include "drm_crtc_helper.h"
	33	#include "intel_drv.h"
	34	#include "i915_drm.h"
	35	#include "i915_drv.h"
	36
e7dbb2f2 KP	37	/* Here's the desired hotplug mode */
	38	#define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 \| \
	39	ADPA_CRT_HOTPLUG_WARMUP_10MS \| \
	40	ADPA_CRT_HOTPLUG_SAMPLE_4S \| \
	41	ADPA_CRT_HOTPLUG_VOLTAGE_50 \| \
	42	ADPA_CRT_HOTPLUG_VOLREF_325MV \| \
	43	ADPA_CRT_HOTPLUG_ENABLE)
	44
c9a1c4cd CW	45	struct intel_crt {
c9a1c4cd CW	46	struct intel_encoder base;
e7dbb2f2	47	bool force_hotplug_required;
c9a1c4cd CW	48	};
	49
	50	static struct intel_crt intel_attached_crt(struct drm_connector connector)
	51	{
	52	return container_of(intel_attached_encoder(connector),
	53	struct intel_crt, base);
	54	}
	55
79e53945 JB	56	static void intel_crt_dpms(struct drm_encoder *encoder, int mode)
	57	{
	58	struct drm_device *dev = encoder->dev;
	59	struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f	60	u32 temp, reg;
79e53945	61
bad720ff	62	if (HAS_PCH_SPLIT(dev))
2c07245f ZW	63	reg = PCH_ADPA;
	64	else
	65	reg = ADPA;
	66
	67	temp = I915_READ(reg);
79e53945	68	temp &= ~(ADPA_HSYNC_CNTL_DISABLE \| ADPA_VSYNC_CNTL_DISABLE);
febc7694	69	temp &= ~ADPA_DAC_ENABLE;
79e53945 JB	70
	71	switch(mode) {
	72	case DRM_MODE_DPMS_ON:
	73	temp \|= ADPA_DAC_ENABLE;
	74	break;
	75	case DRM_MODE_DPMS_STANDBY:
	76	temp \|= ADPA_DAC_ENABLE \| ADPA_HSYNC_CNTL_DISABLE;
	77	break;
	78	case DRM_MODE_DPMS_SUSPEND:
	79	temp \|= ADPA_DAC_ENABLE \| ADPA_VSYNC_CNTL_DISABLE;
	80	break;
	81	case DRM_MODE_DPMS_OFF:
	82	temp \|= ADPA_HSYNC_CNTL_DISABLE \| ADPA_VSYNC_CNTL_DISABLE;
	83	break;
	84	}
	85
2c07245f	86	I915_WRITE(reg, temp);
79e53945 JB	87	}
	88
	89	static int intel_crt_mode_valid(struct drm_connector *connector,
	90	struct drm_display_mode *mode)
	91	{
6bcdcd9e ZY	92	struct drm_device *dev = connector->dev;
	93
	94	int max_clock = 0;
79e53945 JB	95	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
	96	return MODE_NO_DBLESCAN;
	97
6bcdcd9e ZY	98	if (mode->clock < 25000)
	99	return MODE_CLOCK_LOW;
	100
a6c45cf0	101	if (IS_GEN2(dev))
6bcdcd9e ZY	102	max_clock = 350000;
	103	else
	104	max_clock = 400000;
	105	if (mode->clock > max_clock)
	106	return MODE_CLOCK_HIGH;
79e53945 JB	107
	108	return MODE_OK;
	109	}
	110
	111	static bool intel_crt_mode_fixup(struct drm_encoder *encoder,
	112	struct drm_display_mode *mode,
	113	struct drm_display_mode *adjusted_mode)
	114	{
	115	return true;
	116	}
	117
	118	static void intel_crt_mode_set(struct drm_encoder *encoder,
	119	struct drm_display_mode *mode,
	120	struct drm_display_mode *adjusted_mode)
	121	{
	122
	123	struct drm_device *dev = encoder->dev;
	124	struct drm_crtc *crtc = encoder->crtc;
	125	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	126	struct drm_i915_private *dev_priv = dev->dev_private;
	127	int dpll_md_reg;
	128	u32 adpa, dpll_md;
2c07245f	129	u32 adpa_reg;
79e53945 JB	130
	131	if (intel_crtc->pipe == 0)
	132	dpll_md_reg = DPLL_A_MD;
	133	else
	134	dpll_md_reg = DPLL_B_MD;
	135
bad720ff	136	if (HAS_PCH_SPLIT(dev))
2c07245f ZW	137	adpa_reg = PCH_ADPA;
	138	else
	139	adpa_reg = ADPA;
	140
79e53945 JB	141	/*
	142	* Disable separate mode multiplier used when cloning SDVO to CRT
	143	* XXX this needs to be adjusted when we really are cloning
	144	*/
a6c45cf0	145	if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
79e53945 JB	146	dpll_md = I915_READ(dpll_md_reg);
	147	I915_WRITE(dpll_md_reg,
	148	dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK);
	149	}
	150
e7dbb2f2	151	adpa = ADPA_HOTPLUG_BITS;
79e53945 JB	152	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
	153	adpa \|= ADPA_HSYNC_ACTIVE_HIGH;
	154	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
	155	adpa \|= ADPA_VSYNC_ACTIVE_HIGH;
	156
6bcdcd9e	157	if (intel_crtc->pipe == 0) {
8db9d77b ZW	158	if (HAS_PCH_CPT(dev))
	159	adpa \|= PORT_TRANS_A_SEL_CPT;
	160	else
	161	adpa \|= ADPA_PIPE_A_SELECT;
bad720ff	162	if (!HAS_PCH_SPLIT(dev))
2c07245f	163	I915_WRITE(BCLRPAT_A, 0);
6bcdcd9e	164	} else {
8db9d77b ZW	165	if (HAS_PCH_CPT(dev))
	166	adpa \|= PORT_TRANS_B_SEL_CPT;
	167	else
	168	adpa \|= ADPA_PIPE_B_SELECT;
bad720ff	169	if (!HAS_PCH_SPLIT(dev))
2c07245f	170	I915_WRITE(BCLRPAT_B, 0);
6bcdcd9e	171	}
79e53945	172
2c07245f ZW	173	I915_WRITE(adpa_reg, adpa);
	174	}
	175
f2b115e6	176	static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
2c07245f ZW	177	{
2c07245f ZW	178	struct drm_device *dev = connector->dev;
e7dbb2f2	179	struct intel_crt *crt = intel_attached_crt(connector);
2c07245f	180	struct drm_i915_private *dev_priv = dev->dev_private;
e7dbb2f2	181	u32 adpa;
2c07245f ZW	182	bool ret;
2c07245f ZW	183
e7dbb2f2 KP	184	/* The first time through, trigger an explicit detection cycle */
	185	if (crt->force_hotplug_required) {
	186	bool turn_off_dac = HAS_PCH_SPLIT(dev);
	187	u32 save_adpa;
67941da2	188
e7dbb2f2 KP	189	crt->force_hotplug_required = 0;
	190
	191	save_adpa = adpa = I915_READ(PCH_ADPA);
	192	DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
	193
	194	adpa \|= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
	195	if (turn_off_dac)
	196	adpa &= ~ADPA_DAC_ENABLE;
	197
	198	I915_WRITE(PCH_ADPA, adpa);
	199
	200	if (wait_for((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
	201	1000))
	202	DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
	203
	204	if (turn_off_dac) {
	205	I915_WRITE(PCH_ADPA, save_adpa);
	206	POSTING_READ(PCH_ADPA);
	207	}
a4a6b901 ZW	208	}
a4a6b901 ZW	209
2c07245f ZW	210	/* Check the status to see if both blue and green are on now */
2c07245f ZW	211	adpa = I915_READ(PCH_ADPA);
e7dbb2f2	212	if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
2c07245f ZW	213	ret = true;
	214	else
	215	ret = false;
e7dbb2f2	216	DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
2c07245f	217
2c07245f	218	return ret;
79e53945 JB	219	}
	220
	221	/**
	222	* Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
	223	*
	224	* Not for i915G/i915GM
	225	*
	226	* \return true if CRT is connected.
	227	* \return false if CRT is disconnected.
	228	*/
	229	static bool intel_crt_detect_hotplug(struct drm_connector *connector)
	230	{
	231	struct drm_device *dev = connector->dev;
	232	struct drm_i915_private *dev_priv = dev->dev_private;
7a772c49 AJ	233	u32 hotplug_en, orig, stat;
7a772c49 AJ	234	bool ret = false;
771cb081	235	int i, tries = 0;
2c07245f	236
bad720ff	237	if (HAS_PCH_SPLIT(dev))
f2b115e6	238	return intel_ironlake_crt_detect_hotplug(connector);
2c07245f	239
771cb081 ZY	240	/*
	241	* On 4 series desktop, CRT detect sequence need to be done twice
	242	* to get a reliable result.
	243	*/
79e53945	244
771cb081 ZY	245	if (IS_G4X(dev) && !IS_GM45(dev))
	246	tries = 2;
	247	else
	248	tries = 1;
7a772c49	249	hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN);
771cb081 ZY	250	hotplug_en \|= CRT_HOTPLUG_FORCE_DETECT;
771cb081 ZY	251
771cb081	252	for (i = 0; i < tries ; i++) {
771cb081 ZY	253	/* turn on the FORCE_DETECT */
771cb081 ZY	254	I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
771cb081	255	/* wait for FORCE_DETECT to go off */
913d8d11 CW	256	if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
913d8d11 CW	257	CRT_HOTPLUG_FORCE_DETECT) == 0,
481b6af3	258	1000))
79077319	259	DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
771cb081	260	}
79e53945	261
7a772c49 AJ	262	stat = I915_READ(PORT_HOTPLUG_STAT);
	263	if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
	264	ret = true;
	265
	266	/* clear the interrupt we just generated, if any */
	267	I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
79e53945	268
7a772c49 AJ	269	/* and put the bits back */
	270	I915_WRITE(PORT_HOTPLUG_EN, orig);
	271
	272	return ret;
79e53945 JB	273	}
79e53945 JB	274
6ec3d0c0 CW	275	static bool intel_crt_ddc_probe(struct drm_i915_private *dev_priv, int ddc_bus)
	276	{
	277	u8 buf;
	278	struct i2c_msg msgs[] = {
	279	{
	280	.addr = 0xA0,
	281	.flags = 0,
	282	.len = 1,
	283	.buf = &buf,
	284	},
	285	};
	286	/* DDC monitor detect: Does it ACK a write to 0xA0? */
	287	return i2c_transfer(&dev_priv->gmbus[ddc_bus].adapter, msgs, 1) == 1;
	288	}
	289
c9a1c4cd	290	static bool intel_crt_detect_ddc(struct intel_crt *crt)
79e53945	291	{
c9a1c4cd	292	struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private;
79e53945 JB	293
79e53945 JB	294	/* CRT should always be at 0, but check anyway */
c9a1c4cd	295	if (crt->base.type != INTEL_OUTPUT_ANALOG)
79e53945 JB	296	return false;
79e53945 JB	297
6ec3d0c0 CW	298	if (intel_crt_ddc_probe(dev_priv, dev_priv->crt_ddc_pin)) {
	299	DRM_DEBUG_KMS("CRT detected via DDC:0xa0\n");
	300	return true;
	301	}
	302
c9a1c4cd	303	if (intel_ddc_probe(&crt->base, dev_priv->crt_ddc_pin)) {
6ec3d0c0 CW	304	DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
	305	return true;
	306	}
	307
	308	return false;
79e53945 JB	309	}
79e53945 JB	310
e4a5d54f	311	static enum drm_connector_status
c9a1c4cd	312	intel_crt_load_detect(struct drm_crtc crtc, struct intel_crt crt)
e4a5d54f	313	{
c9a1c4cd	314	struct drm_encoder *encoder = &crt->base.base;
e4a5d54f ML	315	struct drm_device *dev = encoder->dev;
	316	struct drm_i915_private *dev_priv = dev->dev_private;
	317	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	318	uint32_t pipe = intel_crtc->pipe;
	319	uint32_t save_bclrpat;
	320	uint32_t save_vtotal;
	321	uint32_t vtotal, vactive;
	322	uint32_t vsample;
	323	uint32_t vblank, vblank_start, vblank_end;
	324	uint32_t dsl;
	325	uint32_t bclrpat_reg;
	326	uint32_t vtotal_reg;
	327	uint32_t vblank_reg;
	328	uint32_t vsync_reg;
	329	uint32_t pipeconf_reg;
	330	uint32_t pipe_dsl_reg;
	331	uint8_t st00;
	332	enum drm_connector_status status;
	333
6ec3d0c0 CW	334	DRM_DEBUG_KMS("starting load-detect on CRT\n");
6ec3d0c0 CW	335
e4a5d54f ML	336	if (pipe == 0) {
	337	bclrpat_reg = BCLRPAT_A;
	338	vtotal_reg = VTOTAL_A;
	339	vblank_reg = VBLANK_A;
	340	vsync_reg = VSYNC_A;
	341	pipeconf_reg = PIPEACONF;
	342	pipe_dsl_reg = PIPEADSL;
	343	} else {
	344	bclrpat_reg = BCLRPAT_B;
	345	vtotal_reg = VTOTAL_B;
	346	vblank_reg = VBLANK_B;
	347	vsync_reg = VSYNC_B;
	348	pipeconf_reg = PIPEBCONF;
	349	pipe_dsl_reg = PIPEBDSL;
	350	}
	351
	352	save_bclrpat = I915_READ(bclrpat_reg);
	353	save_vtotal = I915_READ(vtotal_reg);
	354	vblank = I915_READ(vblank_reg);
	355
	356	vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
	357	vactive = (save_vtotal & 0x7ff) + 1;
	358
	359	vblank_start = (vblank & 0xfff) + 1;
	360	vblank_end = ((vblank >> 16) & 0xfff) + 1;
	361
	362	/* Set the border color to purple. */
	363	I915_WRITE(bclrpat_reg, 0x500050);
	364
a6c45cf0	365	if (!IS_GEN2(dev)) {
e4a5d54f ML	366	uint32_t pipeconf = I915_READ(pipeconf_reg);
e4a5d54f ML	367	I915_WRITE(pipeconf_reg, pipeconf \| PIPECONF_FORCE_BORDER);
19c55da1	368	POSTING_READ(pipeconf_reg);
e4a5d54f ML	369	/* Wait for next Vblank to substitue
e4a5d54f ML	370	* border color for Color info */
9d0498a2	371	intel_wait_for_vblank(dev, pipe);
e4a5d54f ML	372	st00 = I915_READ8(VGA_MSR_WRITE);
	373	status = ((st00 & (1 << 4)) != 0) ?
	374	connector_status_connected :
	375	connector_status_disconnected;
	376
	377	I915_WRITE(pipeconf_reg, pipeconf);
	378	} else {
	379	bool restore_vblank = false;
	380	int count, detect;
	381
	382	/*
	383	* If there isn't any border, add some.
	384	* Yes, this will flicker
	385	*/
	386	if (vblank_start <= vactive && vblank_end >= vtotal) {
	387	uint32_t vsync = I915_READ(vsync_reg);
	388	uint32_t vsync_start = (vsync & 0xffff) + 1;
	389
	390	vblank_start = vsync_start;
	391	I915_WRITE(vblank_reg,
	392	(vblank_start - 1) \|
	393	((vblank_end - 1) << 16));
	394	restore_vblank = true;
	395	}
	396	/* sample in the vertical border, selecting the larger one */
	397	if (vblank_start - vactive >= vtotal - vblank_end)
	398	vsample = (vblank_start + vactive) >> 1;
	399	else
	400	vsample = (vtotal + vblank_end) >> 1;
	401
	402	/*
	403	* Wait for the border to be displayed
	404	*/
	405	while (I915_READ(pipe_dsl_reg) >= vactive)
	406	;
	407	while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
	408	;
	409	/*
	410	* Watch ST00 for an entire scanline
	411	*/
	412	detect = 0;
	413	count = 0;
	414	do {
	415	count++;
	416	/* Read the ST00 VGA status register */
	417	st00 = I915_READ8(VGA_MSR_WRITE);
	418	if (st00 & (1 << 4))
	419	detect++;
	420	} while ((I915_READ(pipe_dsl_reg) == dsl));
	421
	422	/* restore vblank if necessary */
	423	if (restore_vblank)
	424	I915_WRITE(vblank_reg, vblank);
	425	/*
	426	* If more than 3/4 of the scanline detected a monitor,
	427	* then it is assumed to be present. This works even on i830,
	428	* where there isn't any way to force the border color across
	429	* the screen
	430	*/
	431	status = detect * 4 > count * 3 ?
	432	connector_status_connected :
	433	connector_status_disconnected;
	434	}
	435
436	/* Restore previous settings */
437	I915_WRITE(bclrpat_reg, save_bclrpat);
438
439	return status;
440	}
441
7b334fcb	442	static enum drm_connector_status
930a9e28	443	intel_crt_detect(struct drm_connector *connector, bool force)
79e53945 JB	444	{
79e53945 JB	445	struct drm_device *dev = connector->dev;
c9a1c4cd	446	struct intel_crt *crt = intel_attached_crt(connector);
e4a5d54f ML	447	struct drm_crtc *crtc;
	448	int dpms_mode;
	449	enum drm_connector_status status;
79e53945	450
a6c45cf0	451	if (I915_HAS_HOTPLUG(dev)) {
6ec3d0c0 CW	452	if (intel_crt_detect_hotplug(connector)) {
6ec3d0c0 CW	453	DRM_DEBUG_KMS("CRT detected via hotplug\n");
79e53945	454	return connector_status_connected;
e7dbb2f2 KP	455	} else {
e7dbb2f2 KP	456	DRM_DEBUG_KMS("CRT not detected via hotplug\n");
79e53945	457	return connector_status_disconnected;
e7dbb2f2	458	}
79e53945 JB	459	}
79e53945 JB	460
c9a1c4cd	461	if (intel_crt_detect_ddc(crt))
79e53945 JB	462	return connector_status_connected;
79e53945 JB	463
930a9e28	464	if (!force)
7b334fcb CW	465	return connector->status;
7b334fcb CW	466
e4a5d54f	467	/* for pre-945g platforms use load detect */
c9a1c4cd CW	468	crtc = crt->base.base.crtc;
	469	if (crtc && crtc->enabled) {
	470	status = intel_crt_load_detect(crtc, crt);
e4a5d54f	471	} else {
c9a1c4cd	472	crtc = intel_get_load_detect_pipe(&crt->base, connector,
e4a5d54f ML	473	NULL, &dpms_mode);
e4a5d54f ML	474	if (crtc) {
c9a1c4cd	475	if (intel_crt_detect_ddc(crt))
6ec3d0c0 CW	476	status = connector_status_connected;
6ec3d0c0 CW	477	else
c9a1c4cd CW	478	status = intel_crt_load_detect(crtc, crt);
c9a1c4cd CW	479	intel_release_load_detect_pipe(&crt->base,
c1c43977	480	connector, dpms_mode);
e4a5d54f ML	481	} else
	482	status = connector_status_unknown;
	483	}
	484
	485	return status;
79e53945 JB	486	}
	487
	488	static void intel_crt_destroy(struct drm_connector *connector)
	489	{
79e53945 JB	490	drm_sysfs_connector_remove(connector);
	491	drm_connector_cleanup(connector);
	492	kfree(connector);
	493	}
	494
	495	static int intel_crt_get_modes(struct drm_connector *connector)
	496	{
8e4d36b9	497	struct drm_device *dev = connector->dev;
f899fc64	498	struct drm_i915_private *dev_priv = dev->dev_private;
890f3359	499	int ret;
8e4d36b9	500
f899fc64 CW	501	ret = intel_ddc_get_modes(connector,
f899fc64 CW	502	&dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter);
8e4d36b9	503	if (ret \|\| !IS_G4X(dev))
f899fc64	504	return ret;
8e4d36b9	505
8e4d36b9	506	/* Try to probe digital port for output in DVI-I -> VGA mode. */
f899fc64 CW	507	return intel_ddc_get_modes(connector,
f899fc64 CW	508	&dev_priv->gmbus[GMBUS_PORT_DPB].adapter);
79e53945 JB	509	}
	510
	511	static int intel_crt_set_property(struct drm_connector *connector,
	512	struct drm_property *property,
	513	uint64_t value)
	514	{
79e53945 JB	515	return 0;
	516	}
	517
	518	/*
	519	* Routines for controlling stuff on the analog port
	520	*/
	521
	522	static const struct drm_encoder_helper_funcs intel_crt_helper_funcs = {
	523	.dpms = intel_crt_dpms,
	524	.mode_fixup = intel_crt_mode_fixup,
	525	.prepare = intel_encoder_prepare,
	526	.commit = intel_encoder_commit,
	527	.mode_set = intel_crt_mode_set,
	528	};
	529
	530	static const struct drm_connector_funcs intel_crt_connector_funcs = {
c9fb15f6	531	.dpms = drm_helper_connector_dpms,
79e53945 JB	532	.detect = intel_crt_detect,
	533	.fill_modes = drm_helper_probe_single_connector_modes,
	534	.destroy = intel_crt_destroy,
	535	.set_property = intel_crt_set_property,
	536	};
	537
	538	static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
	539	.mode_valid = intel_crt_mode_valid,
	540	.get_modes = intel_crt_get_modes,
df0e9248	541	.best_encoder = intel_best_encoder,
79e53945 JB	542	};
79e53945 JB	543
79e53945	544	static const struct drm_encoder_funcs intel_crt_enc_funcs = {
ea5b213a	545	.destroy = intel_encoder_destroy,
79e53945 JB	546	};
	547
	548	void intel_crt_init(struct drm_device *dev)
	549	{
	550	struct drm_connector *connector;
c9a1c4cd	551	struct intel_crt *crt;
454c1ca8	552	struct intel_connector *intel_connector;
db545019	553	struct drm_i915_private *dev_priv = dev->dev_private;
79e53945	554
c9a1c4cd CW	555	crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
c9a1c4cd CW	556	if (!crt)
79e53945 JB	557	return;
79e53945 JB	558
454c1ca8 ZW	559	intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
454c1ca8 ZW	560	if (!intel_connector) {
c9a1c4cd	561	kfree(crt);
454c1ca8 ZW	562	return;
	563	}
	564
	565	connector = &intel_connector->base;
	566	drm_connector_init(dev, &intel_connector->base,
79e53945 JB	567	&intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
79e53945 JB	568
c9a1c4cd	569	drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs,
79e53945 JB	570	DRM_MODE_ENCODER_DAC);
79e53945 JB	571
c9a1c4cd	572	intel_connector_attach_encoder(intel_connector, &crt->base);
79e53945	573
c9a1c4cd CW	574	crt->base.type = INTEL_OUTPUT_ANALOG;
	575	crt->base.clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT \|
	576	1 << INTEL_ANALOG_CLONE_BIT \|
	577	1 << INTEL_SDVO_LVDS_CLONE_BIT);
	578	crt->base.crtc_mask = (1 << 0) \| (1 << 1);
734b4157	579	connector->interlace_allowed = 1;
79e53945 JB	580	connector->doublescan_allowed = 0;
79e53945 JB	581
c9a1c4cd	582	drm_encoder_helper_add(&crt->base.base, &intel_crt_helper_funcs);
79e53945 JB	583	drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
	584
	585	drm_sysfs_connector_add(connector);
b01f2c3a	586
eb1f8e4f DA	587	if (I915_HAS_HOTPLUG(dev))
	588	connector->polled = DRM_CONNECTOR_POLL_HPD;
	589	else
	590	connector->polled = DRM_CONNECTOR_POLL_CONNECT;
	591
e7dbb2f2 KP	592	/*
	593	* Configure the automatic hotplug detection stuff
	594	*/
	595	crt->force_hotplug_required = 0;
	596	if (HAS_PCH_SPLIT(dev)) {
	597	u32 adpa;
	598
	599	adpa = I915_READ(PCH_ADPA);
	600	adpa &= ~ADPA_CRT_HOTPLUG_MASK;
	601	adpa \|= ADPA_HOTPLUG_BITS;
	602	I915_WRITE(PCH_ADPA, adpa);
	603	POSTING_READ(PCH_ADPA);
	604
	605	DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa);
	606	crt->force_hotplug_required = 1;
	607	}
	608
b01f2c3a	609	dev_priv->hotplug_supported_mask \|= CRT_HOTPLUG_INT_STATUS;
79e53945	610	}