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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
319c1d42 | 40 | #include <drm/drm_atomic.h> |
c196e1d6 | 41 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
42 | #include <drm/drm_dp_helper.h> |
43 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
44 | #include <drm/drm_plane_helper.h> |
45 | #include <drm/drm_rect.h> | |
c0f372b3 | 46 | #include <linux/dma_remapping.h> |
79e53945 | 47 | |
465c120c MR |
48 | /* Primary plane formats supported by all gen */ |
49 | #define COMMON_PRIMARY_FORMATS \ | |
50 | DRM_FORMAT_C8, \ | |
51 | DRM_FORMAT_RGB565, \ | |
52 | DRM_FORMAT_XRGB8888, \ | |
53 | DRM_FORMAT_ARGB8888 | |
54 | ||
55 | /* Primary plane formats for gen <= 3 */ | |
56 | static const uint32_t intel_primary_formats_gen2[] = { | |
57 | COMMON_PRIMARY_FORMATS, | |
58 | DRM_FORMAT_XRGB1555, | |
59 | DRM_FORMAT_ARGB1555, | |
60 | }; | |
61 | ||
62 | /* Primary plane formats for gen >= 4 */ | |
63 | static const uint32_t intel_primary_formats_gen4[] = { | |
64 | COMMON_PRIMARY_FORMATS, \ | |
65 | DRM_FORMAT_XBGR8888, | |
66 | DRM_FORMAT_ABGR8888, | |
67 | DRM_FORMAT_XRGB2101010, | |
68 | DRM_FORMAT_ARGB2101010, | |
69 | DRM_FORMAT_XBGR2101010, | |
70 | DRM_FORMAT_ABGR2101010, | |
71 | }; | |
72 | ||
3d7d6510 MR |
73 | /* Cursor formats */ |
74 | static const uint32_t intel_cursor_formats[] = { | |
75 | DRM_FORMAT_ARGB8888, | |
76 | }; | |
77 | ||
6b383a7f | 78 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 79 | |
f1f644dc | 80 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 81 | struct intel_crtc_state *pipe_config); |
18442d08 | 82 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 83 | struct intel_crtc_state *pipe_config); |
f1f644dc | 84 | |
e7457a9a | 85 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
83a57153 ACO |
86 | int x, int y, struct drm_framebuffer *old_fb, |
87 | struct drm_atomic_state *state); | |
eb1bfe80 JB |
88 | static int intel_framebuffer_init(struct drm_device *dev, |
89 | struct intel_framebuffer *ifb, | |
90 | struct drm_mode_fb_cmd2 *mode_cmd, | |
91 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
92 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
93 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
29407aab | 94 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
95 | struct intel_link_m_n *m_n, |
96 | struct intel_link_m_n *m2_n2); | |
29407aab | 97 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 DV |
98 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
99 | static void intel_set_pipe_csc(struct drm_crtc *crtc); | |
d288f65f | 100 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 101 | const struct intel_crtc_state *pipe_config); |
d288f65f | 102 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 103 | const struct intel_crtc_state *pipe_config); |
ea2c67bb MR |
104 | static void intel_begin_crtc_commit(struct drm_crtc *crtc); |
105 | static void intel_finish_crtc_commit(struct drm_crtc *crtc); | |
e7457a9a | 106 | |
0e32b39c DA |
107 | static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe) |
108 | { | |
109 | if (!connector->mst_port) | |
110 | return connector->encoder; | |
111 | else | |
112 | return &connector->mst_port->mst_encoders[pipe]->base; | |
113 | } | |
114 | ||
79e53945 | 115 | typedef struct { |
0206e353 | 116 | int min, max; |
79e53945 JB |
117 | } intel_range_t; |
118 | ||
119 | typedef struct { | |
0206e353 AJ |
120 | int dot_limit; |
121 | int p2_slow, p2_fast; | |
79e53945 JB |
122 | } intel_p2_t; |
123 | ||
d4906093 ML |
124 | typedef struct intel_limit intel_limit_t; |
125 | struct intel_limit { | |
0206e353 AJ |
126 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
127 | intel_p2_t p2; | |
d4906093 | 128 | }; |
79e53945 | 129 | |
d2acd215 DV |
130 | int |
131 | intel_pch_rawclk(struct drm_device *dev) | |
132 | { | |
133 | struct drm_i915_private *dev_priv = dev->dev_private; | |
134 | ||
135 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
136 | ||
137 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
138 | } | |
139 | ||
021357ac CW |
140 | static inline u32 /* units of 100MHz */ |
141 | intel_fdi_link_freq(struct drm_device *dev) | |
142 | { | |
8b99e68c CW |
143 | if (IS_GEN5(dev)) { |
144 | struct drm_i915_private *dev_priv = dev->dev_private; | |
145 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
146 | } else | |
147 | return 27; | |
021357ac CW |
148 | } |
149 | ||
5d536e28 | 150 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 151 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 152 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 153 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
154 | .m = { .min = 96, .max = 140 }, |
155 | .m1 = { .min = 18, .max = 26 }, | |
156 | .m2 = { .min = 6, .max = 16 }, | |
157 | .p = { .min = 4, .max = 128 }, | |
158 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
159 | .p2 = { .dot_limit = 165000, |
160 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
161 | }; |
162 | ||
5d536e28 DV |
163 | static const intel_limit_t intel_limits_i8xx_dvo = { |
164 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 165 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 166 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
167 | .m = { .min = 96, .max = 140 }, |
168 | .m1 = { .min = 18, .max = 26 }, | |
169 | .m2 = { .min = 6, .max = 16 }, | |
170 | .p = { .min = 4, .max = 128 }, | |
171 | .p1 = { .min = 2, .max = 33 }, | |
172 | .p2 = { .dot_limit = 165000, | |
173 | .p2_slow = 4, .p2_fast = 4 }, | |
174 | }; | |
175 | ||
e4b36699 | 176 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 177 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 178 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 179 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
180 | .m = { .min = 96, .max = 140 }, |
181 | .m1 = { .min = 18, .max = 26 }, | |
182 | .m2 = { .min = 6, .max = 16 }, | |
183 | .p = { .min = 4, .max = 128 }, | |
184 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
185 | .p2 = { .dot_limit = 165000, |
186 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 187 | }; |
273e27ca | 188 | |
e4b36699 | 189 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
190 | .dot = { .min = 20000, .max = 400000 }, |
191 | .vco = { .min = 1400000, .max = 2800000 }, | |
192 | .n = { .min = 1, .max = 6 }, | |
193 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
194 | .m1 = { .min = 8, .max = 18 }, |
195 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
196 | .p = { .min = 5, .max = 80 }, |
197 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
198 | .p2 = { .dot_limit = 200000, |
199 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
200 | }; |
201 | ||
202 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
203 | .dot = { .min = 20000, .max = 400000 }, |
204 | .vco = { .min = 1400000, .max = 2800000 }, | |
205 | .n = { .min = 1, .max = 6 }, | |
206 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
207 | .m1 = { .min = 8, .max = 18 }, |
208 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
209 | .p = { .min = 7, .max = 98 }, |
210 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
211 | .p2 = { .dot_limit = 112000, |
212 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
213 | }; |
214 | ||
273e27ca | 215 | |
e4b36699 | 216 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
217 | .dot = { .min = 25000, .max = 270000 }, |
218 | .vco = { .min = 1750000, .max = 3500000}, | |
219 | .n = { .min = 1, .max = 4 }, | |
220 | .m = { .min = 104, .max = 138 }, | |
221 | .m1 = { .min = 17, .max = 23 }, | |
222 | .m2 = { .min = 5, .max = 11 }, | |
223 | .p = { .min = 10, .max = 30 }, | |
224 | .p1 = { .min = 1, .max = 3}, | |
225 | .p2 = { .dot_limit = 270000, | |
226 | .p2_slow = 10, | |
227 | .p2_fast = 10 | |
044c7c41 | 228 | }, |
e4b36699 KP |
229 | }; |
230 | ||
231 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
232 | .dot = { .min = 22000, .max = 400000 }, |
233 | .vco = { .min = 1750000, .max = 3500000}, | |
234 | .n = { .min = 1, .max = 4 }, | |
235 | .m = { .min = 104, .max = 138 }, | |
236 | .m1 = { .min = 16, .max = 23 }, | |
237 | .m2 = { .min = 5, .max = 11 }, | |
238 | .p = { .min = 5, .max = 80 }, | |
239 | .p1 = { .min = 1, .max = 8}, | |
240 | .p2 = { .dot_limit = 165000, | |
241 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
242 | }; |
243 | ||
244 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
245 | .dot = { .min = 20000, .max = 115000 }, |
246 | .vco = { .min = 1750000, .max = 3500000 }, | |
247 | .n = { .min = 1, .max = 3 }, | |
248 | .m = { .min = 104, .max = 138 }, | |
249 | .m1 = { .min = 17, .max = 23 }, | |
250 | .m2 = { .min = 5, .max = 11 }, | |
251 | .p = { .min = 28, .max = 112 }, | |
252 | .p1 = { .min = 2, .max = 8 }, | |
253 | .p2 = { .dot_limit = 0, | |
254 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 255 | }, |
e4b36699 KP |
256 | }; |
257 | ||
258 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
259 | .dot = { .min = 80000, .max = 224000 }, |
260 | .vco = { .min = 1750000, .max = 3500000 }, | |
261 | .n = { .min = 1, .max = 3 }, | |
262 | .m = { .min = 104, .max = 138 }, | |
263 | .m1 = { .min = 17, .max = 23 }, | |
264 | .m2 = { .min = 5, .max = 11 }, | |
265 | .p = { .min = 14, .max = 42 }, | |
266 | .p1 = { .min = 2, .max = 6 }, | |
267 | .p2 = { .dot_limit = 0, | |
268 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 269 | }, |
e4b36699 KP |
270 | }; |
271 | ||
f2b115e6 | 272 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
273 | .dot = { .min = 20000, .max = 400000}, |
274 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 275 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
276 | .n = { .min = 3, .max = 6 }, |
277 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 278 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
279 | .m1 = { .min = 0, .max = 0 }, |
280 | .m2 = { .min = 0, .max = 254 }, | |
281 | .p = { .min = 5, .max = 80 }, | |
282 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
283 | .p2 = { .dot_limit = 200000, |
284 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
285 | }; |
286 | ||
f2b115e6 | 287 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
288 | .dot = { .min = 20000, .max = 400000 }, |
289 | .vco = { .min = 1700000, .max = 3500000 }, | |
290 | .n = { .min = 3, .max = 6 }, | |
291 | .m = { .min = 2, .max = 256 }, | |
292 | .m1 = { .min = 0, .max = 0 }, | |
293 | .m2 = { .min = 0, .max = 254 }, | |
294 | .p = { .min = 7, .max = 112 }, | |
295 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
296 | .p2 = { .dot_limit = 112000, |
297 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
298 | }; |
299 | ||
273e27ca EA |
300 | /* Ironlake / Sandybridge |
301 | * | |
302 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
303 | * the range value for them is (actual_value - 2). | |
304 | */ | |
b91ad0ec | 305 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
306 | .dot = { .min = 25000, .max = 350000 }, |
307 | .vco = { .min = 1760000, .max = 3510000 }, | |
308 | .n = { .min = 1, .max = 5 }, | |
309 | .m = { .min = 79, .max = 127 }, | |
310 | .m1 = { .min = 12, .max = 22 }, | |
311 | .m2 = { .min = 5, .max = 9 }, | |
312 | .p = { .min = 5, .max = 80 }, | |
313 | .p1 = { .min = 1, .max = 8 }, | |
314 | .p2 = { .dot_limit = 225000, | |
315 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
316 | }; |
317 | ||
b91ad0ec | 318 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
319 | .dot = { .min = 25000, .max = 350000 }, |
320 | .vco = { .min = 1760000, .max = 3510000 }, | |
321 | .n = { .min = 1, .max = 3 }, | |
322 | .m = { .min = 79, .max = 118 }, | |
323 | .m1 = { .min = 12, .max = 22 }, | |
324 | .m2 = { .min = 5, .max = 9 }, | |
325 | .p = { .min = 28, .max = 112 }, | |
326 | .p1 = { .min = 2, .max = 8 }, | |
327 | .p2 = { .dot_limit = 225000, | |
328 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
329 | }; |
330 | ||
331 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
332 | .dot = { .min = 25000, .max = 350000 }, |
333 | .vco = { .min = 1760000, .max = 3510000 }, | |
334 | .n = { .min = 1, .max = 3 }, | |
335 | .m = { .min = 79, .max = 127 }, | |
336 | .m1 = { .min = 12, .max = 22 }, | |
337 | .m2 = { .min = 5, .max = 9 }, | |
338 | .p = { .min = 14, .max = 56 }, | |
339 | .p1 = { .min = 2, .max = 8 }, | |
340 | .p2 = { .dot_limit = 225000, | |
341 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
342 | }; |
343 | ||
273e27ca | 344 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 345 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
346 | .dot = { .min = 25000, .max = 350000 }, |
347 | .vco = { .min = 1760000, .max = 3510000 }, | |
348 | .n = { .min = 1, .max = 2 }, | |
349 | .m = { .min = 79, .max = 126 }, | |
350 | .m1 = { .min = 12, .max = 22 }, | |
351 | .m2 = { .min = 5, .max = 9 }, | |
352 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 353 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
354 | .p2 = { .dot_limit = 225000, |
355 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
356 | }; |
357 | ||
358 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
359 | .dot = { .min = 25000, .max = 350000 }, |
360 | .vco = { .min = 1760000, .max = 3510000 }, | |
361 | .n = { .min = 1, .max = 3 }, | |
362 | .m = { .min = 79, .max = 126 }, | |
363 | .m1 = { .min = 12, .max = 22 }, | |
364 | .m2 = { .min = 5, .max = 9 }, | |
365 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 366 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
367 | .p2 = { .dot_limit = 225000, |
368 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
369 | }; |
370 | ||
dc730512 | 371 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
372 | /* |
373 | * These are the data rate limits (measured in fast clocks) | |
374 | * since those are the strictest limits we have. The fast | |
375 | * clock and actual rate limits are more relaxed, so checking | |
376 | * them would make no difference. | |
377 | */ | |
378 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 379 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 380 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
381 | .m1 = { .min = 2, .max = 3 }, |
382 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 383 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 384 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
385 | }; |
386 | ||
ef9348c8 CML |
387 | static const intel_limit_t intel_limits_chv = { |
388 | /* | |
389 | * These are the data rate limits (measured in fast clocks) | |
390 | * since those are the strictest limits we have. The fast | |
391 | * clock and actual rate limits are more relaxed, so checking | |
392 | * them would make no difference. | |
393 | */ | |
394 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 395 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
396 | .n = { .min = 1, .max = 1 }, |
397 | .m1 = { .min = 2, .max = 2 }, | |
398 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
399 | .p1 = { .min = 2, .max = 4 }, | |
400 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
401 | }; | |
402 | ||
6b4bf1c4 VS |
403 | static void vlv_clock(int refclk, intel_clock_t *clock) |
404 | { | |
405 | clock->m = clock->m1 * clock->m2; | |
406 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
407 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
408 | return; | |
fb03ac01 VS |
409 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
410 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
6b4bf1c4 VS |
411 | } |
412 | ||
e0638cdf PZ |
413 | /** |
414 | * Returns whether any output on the specified pipe is of the specified type | |
415 | */ | |
4093561b | 416 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) |
e0638cdf | 417 | { |
409ee761 | 418 | struct drm_device *dev = crtc->base.dev; |
e0638cdf PZ |
419 | struct intel_encoder *encoder; |
420 | ||
409ee761 | 421 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
e0638cdf PZ |
422 | if (encoder->type == type) |
423 | return true; | |
424 | ||
425 | return false; | |
426 | } | |
427 | ||
d0737e1d ACO |
428 | /** |
429 | * Returns whether any output on the specified pipe will have the specified | |
430 | * type after a staged modeset is complete, i.e., the same as | |
431 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of | |
432 | * encoder->crtc. | |
433 | */ | |
a93e255f ACO |
434 | static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state, |
435 | int type) | |
d0737e1d | 436 | { |
a93e255f ACO |
437 | struct drm_atomic_state *state = crtc_state->base.state; |
438 | struct drm_connector_state *connector_state; | |
d0737e1d | 439 | struct intel_encoder *encoder; |
a93e255f ACO |
440 | int i, num_connectors = 0; |
441 | ||
442 | for (i = 0; i < state->num_connector; i++) { | |
443 | if (!state->connectors[i]) | |
444 | continue; | |
445 | ||
446 | connector_state = state->connector_states[i]; | |
447 | if (connector_state->crtc != crtc_state->base.crtc) | |
448 | continue; | |
449 | ||
450 | num_connectors++; | |
d0737e1d | 451 | |
a93e255f ACO |
452 | encoder = to_intel_encoder(connector_state->best_encoder); |
453 | if (encoder->type == type) | |
d0737e1d | 454 | return true; |
a93e255f ACO |
455 | } |
456 | ||
457 | WARN_ON(num_connectors == 0); | |
d0737e1d ACO |
458 | |
459 | return false; | |
460 | } | |
461 | ||
a93e255f ACO |
462 | static const intel_limit_t * |
463 | intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk) | |
2c07245f | 464 | { |
a93e255f | 465 | struct drm_device *dev = crtc_state->base.crtc->dev; |
2c07245f | 466 | const intel_limit_t *limit; |
b91ad0ec | 467 | |
a93e255f | 468 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 469 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 470 | if (refclk == 100000) |
b91ad0ec ZW |
471 | limit = &intel_limits_ironlake_dual_lvds_100m; |
472 | else | |
473 | limit = &intel_limits_ironlake_dual_lvds; | |
474 | } else { | |
1b894b59 | 475 | if (refclk == 100000) |
b91ad0ec ZW |
476 | limit = &intel_limits_ironlake_single_lvds_100m; |
477 | else | |
478 | limit = &intel_limits_ironlake_single_lvds; | |
479 | } | |
c6bb3538 | 480 | } else |
b91ad0ec | 481 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
482 | |
483 | return limit; | |
484 | } | |
485 | ||
a93e255f ACO |
486 | static const intel_limit_t * |
487 | intel_g4x_limit(struct intel_crtc_state *crtc_state) | |
044c7c41 | 488 | { |
a93e255f | 489 | struct drm_device *dev = crtc_state->base.crtc->dev; |
044c7c41 ML |
490 | const intel_limit_t *limit; |
491 | ||
a93e255f | 492 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 493 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 494 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 495 | else |
e4b36699 | 496 | limit = &intel_limits_g4x_single_channel_lvds; |
a93e255f ACO |
497 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) || |
498 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 499 | limit = &intel_limits_g4x_hdmi; |
a93e255f | 500 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 501 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 502 | } else /* The option is for other outputs */ |
e4b36699 | 503 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
504 | |
505 | return limit; | |
506 | } | |
507 | ||
a93e255f ACO |
508 | static const intel_limit_t * |
509 | intel_limit(struct intel_crtc_state *crtc_state, int refclk) | |
79e53945 | 510 | { |
a93e255f | 511 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 JB |
512 | const intel_limit_t *limit; |
513 | ||
bad720ff | 514 | if (HAS_PCH_SPLIT(dev)) |
a93e255f | 515 | limit = intel_ironlake_limit(crtc_state, refclk); |
2c07245f | 516 | else if (IS_G4X(dev)) { |
a93e255f | 517 | limit = intel_g4x_limit(crtc_state); |
f2b115e6 | 518 | } else if (IS_PINEVIEW(dev)) { |
a93e255f | 519 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 520 | limit = &intel_limits_pineview_lvds; |
2177832f | 521 | else |
f2b115e6 | 522 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
523 | } else if (IS_CHERRYVIEW(dev)) { |
524 | limit = &intel_limits_chv; | |
a0c4da24 | 525 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 526 | limit = &intel_limits_vlv; |
a6c45cf0 | 527 | } else if (!IS_GEN2(dev)) { |
a93e255f | 528 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a6c45cf0 CW |
529 | limit = &intel_limits_i9xx_lvds; |
530 | else | |
531 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 | 532 | } else { |
a93e255f | 533 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
e4b36699 | 534 | limit = &intel_limits_i8xx_lvds; |
a93e255f | 535 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
e4b36699 | 536 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
537 | else |
538 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
539 | } |
540 | return limit; | |
541 | } | |
542 | ||
f2b115e6 AJ |
543 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
544 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 545 | { |
2177832f SL |
546 | clock->m = clock->m2 + 2; |
547 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
548 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
549 | return; | |
fb03ac01 VS |
550 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
551 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
2177832f SL |
552 | } |
553 | ||
7429e9d4 DV |
554 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
555 | { | |
556 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
557 | } | |
558 | ||
ac58c3f0 | 559 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
2177832f | 560 | { |
7429e9d4 | 561 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 562 | clock->p = clock->p1 * clock->p2; |
ed5ca77e VS |
563 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
564 | return; | |
fb03ac01 VS |
565 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
566 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
79e53945 JB |
567 | } |
568 | ||
ef9348c8 CML |
569 | static void chv_clock(int refclk, intel_clock_t *clock) |
570 | { | |
571 | clock->m = clock->m1 * clock->m2; | |
572 | clock->p = clock->p1 * clock->p2; | |
573 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
574 | return; | |
575 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, | |
576 | clock->n << 22); | |
577 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
578 | } | |
579 | ||
7c04d1d9 | 580 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
581 | /** |
582 | * Returns whether the given set of divisors are valid for a given refclk with | |
583 | * the given connectors. | |
584 | */ | |
585 | ||
1b894b59 CW |
586 | static bool intel_PLL_is_valid(struct drm_device *dev, |
587 | const intel_limit_t *limit, | |
588 | const intel_clock_t *clock) | |
79e53945 | 589 | { |
f01b7962 VS |
590 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
591 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 592 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 593 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 594 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 595 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 596 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 597 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 VS |
598 | |
599 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev)) | |
600 | if (clock->m1 <= clock->m2) | |
601 | INTELPllInvalid("m1 <= m2\n"); | |
602 | ||
603 | if (!IS_VALLEYVIEW(dev)) { | |
604 | if (clock->p < limit->p.min || limit->p.max < clock->p) | |
605 | INTELPllInvalid("p out of range\n"); | |
606 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
607 | INTELPllInvalid("m out of range\n"); | |
608 | } | |
609 | ||
79e53945 | 610 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 611 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
612 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
613 | * connector, etc., rather than just a single range. | |
614 | */ | |
615 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 616 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
617 | |
618 | return true; | |
619 | } | |
620 | ||
d4906093 | 621 | static bool |
a93e255f ACO |
622 | i9xx_find_best_dpll(const intel_limit_t *limit, |
623 | struct intel_crtc_state *crtc_state, | |
cec2f356 SP |
624 | int target, int refclk, intel_clock_t *match_clock, |
625 | intel_clock_t *best_clock) | |
79e53945 | 626 | { |
a93e255f | 627 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 628 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 629 | intel_clock_t clock; |
79e53945 JB |
630 | int err = target; |
631 | ||
a93e255f | 632 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 633 | /* |
a210b028 DV |
634 | * For LVDS just rely on its current settings for dual-channel. |
635 | * We haven't figured out how to reliably set up different | |
636 | * single/dual channel state, if we even can. | |
79e53945 | 637 | */ |
1974cad0 | 638 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
639 | clock.p2 = limit->p2.p2_fast; |
640 | else | |
641 | clock.p2 = limit->p2.p2_slow; | |
642 | } else { | |
643 | if (target < limit->p2.dot_limit) | |
644 | clock.p2 = limit->p2.p2_slow; | |
645 | else | |
646 | clock.p2 = limit->p2.p2_fast; | |
647 | } | |
648 | ||
0206e353 | 649 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 650 | |
42158660 ZY |
651 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
652 | clock.m1++) { | |
653 | for (clock.m2 = limit->m2.min; | |
654 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 655 | if (clock.m2 >= clock.m1) |
42158660 ZY |
656 | break; |
657 | for (clock.n = limit->n.min; | |
658 | clock.n <= limit->n.max; clock.n++) { | |
659 | for (clock.p1 = limit->p1.min; | |
660 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
661 | int this_err; |
662 | ||
ac58c3f0 DV |
663 | i9xx_clock(refclk, &clock); |
664 | if (!intel_PLL_is_valid(dev, limit, | |
665 | &clock)) | |
666 | continue; | |
667 | if (match_clock && | |
668 | clock.p != match_clock->p) | |
669 | continue; | |
670 | ||
671 | this_err = abs(clock.dot - target); | |
672 | if (this_err < err) { | |
673 | *best_clock = clock; | |
674 | err = this_err; | |
675 | } | |
676 | } | |
677 | } | |
678 | } | |
679 | } | |
680 | ||
681 | return (err != target); | |
682 | } | |
683 | ||
684 | static bool | |
a93e255f ACO |
685 | pnv_find_best_dpll(const intel_limit_t *limit, |
686 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
687 | int target, int refclk, intel_clock_t *match_clock, |
688 | intel_clock_t *best_clock) | |
79e53945 | 689 | { |
a93e255f | 690 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 691 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 692 | intel_clock_t clock; |
79e53945 JB |
693 | int err = target; |
694 | ||
a93e255f | 695 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 696 | /* |
a210b028 DV |
697 | * For LVDS just rely on its current settings for dual-channel. |
698 | * We haven't figured out how to reliably set up different | |
699 | * single/dual channel state, if we even can. | |
79e53945 | 700 | */ |
1974cad0 | 701 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
702 | clock.p2 = limit->p2.p2_fast; |
703 | else | |
704 | clock.p2 = limit->p2.p2_slow; | |
705 | } else { | |
706 | if (target < limit->p2.dot_limit) | |
707 | clock.p2 = limit->p2.p2_slow; | |
708 | else | |
709 | clock.p2 = limit->p2.p2_fast; | |
710 | } | |
711 | ||
0206e353 | 712 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 713 | |
42158660 ZY |
714 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
715 | clock.m1++) { | |
716 | for (clock.m2 = limit->m2.min; | |
717 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
718 | for (clock.n = limit->n.min; |
719 | clock.n <= limit->n.max; clock.n++) { | |
720 | for (clock.p1 = limit->p1.min; | |
721 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
722 | int this_err; |
723 | ||
ac58c3f0 | 724 | pineview_clock(refclk, &clock); |
1b894b59 CW |
725 | if (!intel_PLL_is_valid(dev, limit, |
726 | &clock)) | |
79e53945 | 727 | continue; |
cec2f356 SP |
728 | if (match_clock && |
729 | clock.p != match_clock->p) | |
730 | continue; | |
79e53945 JB |
731 | |
732 | this_err = abs(clock.dot - target); | |
733 | if (this_err < err) { | |
734 | *best_clock = clock; | |
735 | err = this_err; | |
736 | } | |
737 | } | |
738 | } | |
739 | } | |
740 | } | |
741 | ||
742 | return (err != target); | |
743 | } | |
744 | ||
d4906093 | 745 | static bool |
a93e255f ACO |
746 | g4x_find_best_dpll(const intel_limit_t *limit, |
747 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
748 | int target, int refclk, intel_clock_t *match_clock, |
749 | intel_clock_t *best_clock) | |
d4906093 | 750 | { |
a93e255f | 751 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 752 | struct drm_device *dev = crtc->base.dev; |
d4906093 ML |
753 | intel_clock_t clock; |
754 | int max_n; | |
755 | bool found; | |
6ba770dc AJ |
756 | /* approximately equals target * 0.00585 */ |
757 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
758 | found = false; |
759 | ||
a93e255f | 760 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 761 | if (intel_is_dual_link_lvds(dev)) |
d4906093 ML |
762 | clock.p2 = limit->p2.p2_fast; |
763 | else | |
764 | clock.p2 = limit->p2.p2_slow; | |
765 | } else { | |
766 | if (target < limit->p2.dot_limit) | |
767 | clock.p2 = limit->p2.p2_slow; | |
768 | else | |
769 | clock.p2 = limit->p2.p2_fast; | |
770 | } | |
771 | ||
772 | memset(best_clock, 0, sizeof(*best_clock)); | |
773 | max_n = limit->n.max; | |
f77f13e2 | 774 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 775 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 776 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
777 | for (clock.m1 = limit->m1.max; |
778 | clock.m1 >= limit->m1.min; clock.m1--) { | |
779 | for (clock.m2 = limit->m2.max; | |
780 | clock.m2 >= limit->m2.min; clock.m2--) { | |
781 | for (clock.p1 = limit->p1.max; | |
782 | clock.p1 >= limit->p1.min; clock.p1--) { | |
783 | int this_err; | |
784 | ||
ac58c3f0 | 785 | i9xx_clock(refclk, &clock); |
1b894b59 CW |
786 | if (!intel_PLL_is_valid(dev, limit, |
787 | &clock)) | |
d4906093 | 788 | continue; |
1b894b59 CW |
789 | |
790 | this_err = abs(clock.dot - target); | |
d4906093 ML |
791 | if (this_err < err_most) { |
792 | *best_clock = clock; | |
793 | err_most = this_err; | |
794 | max_n = clock.n; | |
795 | found = true; | |
796 | } | |
797 | } | |
798 | } | |
799 | } | |
800 | } | |
2c07245f ZW |
801 | return found; |
802 | } | |
803 | ||
d5dd62bd ID |
804 | /* |
805 | * Check if the calculated PLL configuration is more optimal compared to the | |
806 | * best configuration and error found so far. Return the calculated error. | |
807 | */ | |
808 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
809 | const intel_clock_t *calculated_clock, | |
810 | const intel_clock_t *best_clock, | |
811 | unsigned int best_error_ppm, | |
812 | unsigned int *error_ppm) | |
813 | { | |
9ca3ba01 ID |
814 | /* |
815 | * For CHV ignore the error and consider only the P value. | |
816 | * Prefer a bigger P value based on HW requirements. | |
817 | */ | |
818 | if (IS_CHERRYVIEW(dev)) { | |
819 | *error_ppm = 0; | |
820 | ||
821 | return calculated_clock->p > best_clock->p; | |
822 | } | |
823 | ||
24be4e46 ID |
824 | if (WARN_ON_ONCE(!target_freq)) |
825 | return false; | |
826 | ||
d5dd62bd ID |
827 | *error_ppm = div_u64(1000000ULL * |
828 | abs(target_freq - calculated_clock->dot), | |
829 | target_freq); | |
830 | /* | |
831 | * Prefer a better P value over a better (smaller) error if the error | |
832 | * is small. Ensure this preference for future configurations too by | |
833 | * setting the error to 0. | |
834 | */ | |
835 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
836 | *error_ppm = 0; | |
837 | ||
838 | return true; | |
839 | } | |
840 | ||
841 | return *error_ppm + 10 < best_error_ppm; | |
842 | } | |
843 | ||
a0c4da24 | 844 | static bool |
a93e255f ACO |
845 | vlv_find_best_dpll(const intel_limit_t *limit, |
846 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
847 | int target, int refclk, intel_clock_t *match_clock, |
848 | intel_clock_t *best_clock) | |
a0c4da24 | 849 | { |
a93e255f | 850 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 851 | struct drm_device *dev = crtc->base.dev; |
6b4bf1c4 | 852 | intel_clock_t clock; |
69e4f900 | 853 | unsigned int bestppm = 1000000; |
27e639bf VS |
854 | /* min update 19.2 MHz */ |
855 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 856 | bool found = false; |
a0c4da24 | 857 | |
6b4bf1c4 VS |
858 | target *= 5; /* fast clock */ |
859 | ||
860 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
861 | |
862 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 863 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 864 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 865 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 866 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 867 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 868 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 869 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 870 | unsigned int ppm; |
69e4f900 | 871 | |
6b4bf1c4 VS |
872 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
873 | refclk * clock.m1); | |
874 | ||
875 | vlv_clock(refclk, &clock); | |
43b0ac53 | 876 | |
f01b7962 VS |
877 | if (!intel_PLL_is_valid(dev, limit, |
878 | &clock)) | |
43b0ac53 VS |
879 | continue; |
880 | ||
d5dd62bd ID |
881 | if (!vlv_PLL_is_optimal(dev, target, |
882 | &clock, | |
883 | best_clock, | |
884 | bestppm, &ppm)) | |
885 | continue; | |
6b4bf1c4 | 886 | |
d5dd62bd ID |
887 | *best_clock = clock; |
888 | bestppm = ppm; | |
889 | found = true; | |
a0c4da24 JB |
890 | } |
891 | } | |
892 | } | |
893 | } | |
a0c4da24 | 894 | |
49e497ef | 895 | return found; |
a0c4da24 | 896 | } |
a4fc5ed6 | 897 | |
ef9348c8 | 898 | static bool |
a93e255f ACO |
899 | chv_find_best_dpll(const intel_limit_t *limit, |
900 | struct intel_crtc_state *crtc_state, | |
ef9348c8 CML |
901 | int target, int refclk, intel_clock_t *match_clock, |
902 | intel_clock_t *best_clock) | |
903 | { | |
a93e255f | 904 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 905 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 906 | unsigned int best_error_ppm; |
ef9348c8 CML |
907 | intel_clock_t clock; |
908 | uint64_t m2; | |
909 | int found = false; | |
910 | ||
911 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 912 | best_error_ppm = 1000000; |
ef9348c8 CML |
913 | |
914 | /* | |
915 | * Based on hardware doc, the n always set to 1, and m1 always | |
916 | * set to 2. If requires to support 200Mhz refclk, we need to | |
917 | * revisit this because n may not 1 anymore. | |
918 | */ | |
919 | clock.n = 1, clock.m1 = 2; | |
920 | target *= 5; /* fast clock */ | |
921 | ||
922 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
923 | for (clock.p2 = limit->p2.p2_fast; | |
924 | clock.p2 >= limit->p2.p2_slow; | |
925 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 926 | unsigned int error_ppm; |
ef9348c8 CML |
927 | |
928 | clock.p = clock.p1 * clock.p2; | |
929 | ||
930 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
931 | clock.n) << 22, refclk * clock.m1); | |
932 | ||
933 | if (m2 > INT_MAX/clock.m1) | |
934 | continue; | |
935 | ||
936 | clock.m2 = m2; | |
937 | ||
938 | chv_clock(refclk, &clock); | |
939 | ||
940 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
941 | continue; | |
942 | ||
9ca3ba01 ID |
943 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
944 | best_error_ppm, &error_ppm)) | |
945 | continue; | |
946 | ||
947 | *best_clock = clock; | |
948 | best_error_ppm = error_ppm; | |
949 | found = true; | |
ef9348c8 CML |
950 | } |
951 | } | |
952 | ||
953 | return found; | |
954 | } | |
955 | ||
20ddf665 VS |
956 | bool intel_crtc_active(struct drm_crtc *crtc) |
957 | { | |
958 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
959 | ||
960 | /* Be paranoid as we can arrive here with only partial | |
961 | * state retrieved from the hardware during setup. | |
962 | * | |
241bfc38 | 963 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
964 | * as Haswell has gained clock readout/fastboot support. |
965 | * | |
66e514c1 | 966 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 967 | * properly reconstruct framebuffers. |
c3d1f436 MR |
968 | * |
969 | * FIXME: The intel_crtc->active here should be switched to | |
970 | * crtc->state->active once we have proper CRTC states wired up | |
971 | * for atomic. | |
20ddf665 | 972 | */ |
c3d1f436 | 973 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 974 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
975 | } |
976 | ||
a5c961d1 PZ |
977 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
978 | enum pipe pipe) | |
979 | { | |
980 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
981 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
982 | ||
6e3c9717 | 983 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
984 | } |
985 | ||
fbf49ea2 VS |
986 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
987 | { | |
988 | struct drm_i915_private *dev_priv = dev->dev_private; | |
989 | u32 reg = PIPEDSL(pipe); | |
990 | u32 line1, line2; | |
991 | u32 line_mask; | |
992 | ||
993 | if (IS_GEN2(dev)) | |
994 | line_mask = DSL_LINEMASK_GEN2; | |
995 | else | |
996 | line_mask = DSL_LINEMASK_GEN3; | |
997 | ||
998 | line1 = I915_READ(reg) & line_mask; | |
999 | mdelay(5); | |
1000 | line2 = I915_READ(reg) & line_mask; | |
1001 | ||
1002 | return line1 == line2; | |
1003 | } | |
1004 | ||
ab7ad7f6 KP |
1005 | /* |
1006 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1007 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1008 | * |
1009 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1010 | * spinning on the vblank interrupt status bit, since we won't actually | |
1011 | * see an interrupt when the pipe is disabled. | |
1012 | * | |
ab7ad7f6 KP |
1013 | * On Gen4 and above: |
1014 | * wait for the pipe register state bit to turn off | |
1015 | * | |
1016 | * Otherwise: | |
1017 | * wait for the display line value to settle (it usually | |
1018 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1019 | * |
9d0498a2 | 1020 | */ |
575f7ab7 | 1021 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1022 | { |
575f7ab7 | 1023 | struct drm_device *dev = crtc->base.dev; |
9d0498a2 | 1024 | struct drm_i915_private *dev_priv = dev->dev_private; |
6e3c9717 | 1025 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1026 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
1027 | |
1028 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 1029 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1030 | |
1031 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
1032 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1033 | 100)) | |
284637d9 | 1034 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1035 | } else { |
ab7ad7f6 | 1036 | /* Wait for the display line to settle */ |
fbf49ea2 | 1037 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1038 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1039 | } |
79e53945 JB |
1040 | } |
1041 | ||
b0ea7d37 DL |
1042 | /* |
1043 | * ibx_digital_port_connected - is the specified port connected? | |
1044 | * @dev_priv: i915 private structure | |
1045 | * @port: the port to test | |
1046 | * | |
1047 | * Returns true if @port is connected, false otherwise. | |
1048 | */ | |
1049 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, | |
1050 | struct intel_digital_port *port) | |
1051 | { | |
1052 | u32 bit; | |
1053 | ||
c36346e3 | 1054 | if (HAS_PCH_IBX(dev_priv->dev)) { |
eba905b2 | 1055 | switch (port->port) { |
c36346e3 DL |
1056 | case PORT_B: |
1057 | bit = SDE_PORTB_HOTPLUG; | |
1058 | break; | |
1059 | case PORT_C: | |
1060 | bit = SDE_PORTC_HOTPLUG; | |
1061 | break; | |
1062 | case PORT_D: | |
1063 | bit = SDE_PORTD_HOTPLUG; | |
1064 | break; | |
1065 | default: | |
1066 | return true; | |
1067 | } | |
1068 | } else { | |
eba905b2 | 1069 | switch (port->port) { |
c36346e3 DL |
1070 | case PORT_B: |
1071 | bit = SDE_PORTB_HOTPLUG_CPT; | |
1072 | break; | |
1073 | case PORT_C: | |
1074 | bit = SDE_PORTC_HOTPLUG_CPT; | |
1075 | break; | |
1076 | case PORT_D: | |
1077 | bit = SDE_PORTD_HOTPLUG_CPT; | |
1078 | break; | |
1079 | default: | |
1080 | return true; | |
1081 | } | |
b0ea7d37 DL |
1082 | } |
1083 | ||
1084 | return I915_READ(SDEISR) & bit; | |
1085 | } | |
1086 | ||
b24e7179 JB |
1087 | static const char *state_string(bool enabled) |
1088 | { | |
1089 | return enabled ? "on" : "off"; | |
1090 | } | |
1091 | ||
1092 | /* Only for pre-ILK configs */ | |
55607e8a DV |
1093 | void assert_pll(struct drm_i915_private *dev_priv, |
1094 | enum pipe pipe, bool state) | |
b24e7179 JB |
1095 | { |
1096 | int reg; | |
1097 | u32 val; | |
1098 | bool cur_state; | |
1099 | ||
1100 | reg = DPLL(pipe); | |
1101 | val = I915_READ(reg); | |
1102 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
e2c719b7 | 1103 | I915_STATE_WARN(cur_state != state, |
b24e7179 JB |
1104 | "PLL state assertion failure (expected %s, current %s)\n", |
1105 | state_string(state), state_string(cur_state)); | |
1106 | } | |
b24e7179 | 1107 | |
23538ef1 JN |
1108 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1109 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1110 | { | |
1111 | u32 val; | |
1112 | bool cur_state; | |
1113 | ||
1114 | mutex_lock(&dev_priv->dpio_lock); | |
1115 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
1116 | mutex_unlock(&dev_priv->dpio_lock); | |
1117 | ||
1118 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1119 | I915_STATE_WARN(cur_state != state, |
23538ef1 JN |
1120 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
1121 | state_string(state), state_string(cur_state)); | |
1122 | } | |
1123 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1124 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1125 | ||
55607e8a | 1126 | struct intel_shared_dpll * |
e2b78267 DV |
1127 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1128 | { | |
1129 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1130 | ||
6e3c9717 | 1131 | if (crtc->config->shared_dpll < 0) |
e2b78267 DV |
1132 | return NULL; |
1133 | ||
6e3c9717 | 1134 | return &dev_priv->shared_dplls[crtc->config->shared_dpll]; |
e2b78267 DV |
1135 | } |
1136 | ||
040484af | 1137 | /* For ILK+ */ |
55607e8a DV |
1138 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1139 | struct intel_shared_dpll *pll, | |
1140 | bool state) | |
040484af | 1141 | { |
040484af | 1142 | bool cur_state; |
5358901f | 1143 | struct intel_dpll_hw_state hw_state; |
040484af | 1144 | |
92b27b08 | 1145 | if (WARN (!pll, |
46edb027 | 1146 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 1147 | return; |
ee7b9f93 | 1148 | |
5358901f | 1149 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
e2c719b7 | 1150 | I915_STATE_WARN(cur_state != state, |
5358901f DV |
1151 | "%s assertion failure (expected %s, current %s)\n", |
1152 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 1153 | } |
040484af JB |
1154 | |
1155 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1156 | enum pipe pipe, bool state) | |
1157 | { | |
1158 | int reg; | |
1159 | u32 val; | |
1160 | bool cur_state; | |
ad80a810 PZ |
1161 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1162 | pipe); | |
040484af | 1163 | |
affa9354 PZ |
1164 | if (HAS_DDI(dev_priv->dev)) { |
1165 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 1166 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 1167 | val = I915_READ(reg); |
ad80a810 | 1168 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
1169 | } else { |
1170 | reg = FDI_TX_CTL(pipe); | |
1171 | val = I915_READ(reg); | |
1172 | cur_state = !!(val & FDI_TX_ENABLE); | |
1173 | } | |
e2c719b7 | 1174 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1175 | "FDI TX state assertion failure (expected %s, current %s)\n", |
1176 | state_string(state), state_string(cur_state)); | |
1177 | } | |
1178 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1179 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1180 | ||
1181 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1182 | enum pipe pipe, bool state) | |
1183 | { | |
1184 | int reg; | |
1185 | u32 val; | |
1186 | bool cur_state; | |
1187 | ||
d63fa0dc PZ |
1188 | reg = FDI_RX_CTL(pipe); |
1189 | val = I915_READ(reg); | |
1190 | cur_state = !!(val & FDI_RX_ENABLE); | |
e2c719b7 | 1191 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1192 | "FDI RX state assertion failure (expected %s, current %s)\n", |
1193 | state_string(state), state_string(cur_state)); | |
1194 | } | |
1195 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1196 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1197 | ||
1198 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1199 | enum pipe pipe) | |
1200 | { | |
1201 | int reg; | |
1202 | u32 val; | |
1203 | ||
1204 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1205 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1206 | return; |
1207 | ||
bf507ef7 | 1208 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1209 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1210 | return; |
1211 | ||
040484af JB |
1212 | reg = FDI_TX_CTL(pipe); |
1213 | val = I915_READ(reg); | |
e2c719b7 | 1214 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1215 | } |
1216 | ||
55607e8a DV |
1217 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1218 | enum pipe pipe, bool state) | |
040484af JB |
1219 | { |
1220 | int reg; | |
1221 | u32 val; | |
55607e8a | 1222 | bool cur_state; |
040484af JB |
1223 | |
1224 | reg = FDI_RX_CTL(pipe); | |
1225 | val = I915_READ(reg); | |
55607e8a | 1226 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1227 | I915_STATE_WARN(cur_state != state, |
55607e8a DV |
1228 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
1229 | state_string(state), state_string(cur_state)); | |
040484af JB |
1230 | } |
1231 | ||
b680c37a DV |
1232 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1233 | enum pipe pipe) | |
ea0760cf | 1234 | { |
bedd4dba JN |
1235 | struct drm_device *dev = dev_priv->dev; |
1236 | int pp_reg; | |
ea0760cf JB |
1237 | u32 val; |
1238 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1239 | bool locked = true; |
ea0760cf | 1240 | |
bedd4dba JN |
1241 | if (WARN_ON(HAS_DDI(dev))) |
1242 | return; | |
1243 | ||
1244 | if (HAS_PCH_SPLIT(dev)) { | |
1245 | u32 port_sel; | |
1246 | ||
ea0760cf | 1247 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1248 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1249 | ||
1250 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1251 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1252 | panel_pipe = PIPE_B; | |
1253 | /* XXX: else fix for eDP */ | |
1254 | } else if (IS_VALLEYVIEW(dev)) { | |
1255 | /* presumably write lock depends on pipe, not port select */ | |
1256 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1257 | panel_pipe = pipe; | |
ea0760cf JB |
1258 | } else { |
1259 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1260 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1261 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1262 | } |
1263 | ||
1264 | val = I915_READ(pp_reg); | |
1265 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1266 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1267 | locked = false; |
1268 | ||
e2c719b7 | 1269 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1270 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1271 | pipe_name(pipe)); |
ea0760cf JB |
1272 | } |
1273 | ||
93ce0ba6 JN |
1274 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1275 | enum pipe pipe, bool state) | |
1276 | { | |
1277 | struct drm_device *dev = dev_priv->dev; | |
1278 | bool cur_state; | |
1279 | ||
d9d82081 | 1280 | if (IS_845G(dev) || IS_I865G(dev)) |
93ce0ba6 | 1281 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; |
d9d82081 | 1282 | else |
5efb3e28 | 1283 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1284 | |
e2c719b7 | 1285 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 JN |
1286 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
1287 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1288 | } | |
1289 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1290 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1291 | ||
b840d907 JB |
1292 | void assert_pipe(struct drm_i915_private *dev_priv, |
1293 | enum pipe pipe, bool state) | |
b24e7179 JB |
1294 | { |
1295 | int reg; | |
1296 | u32 val; | |
63d7bbe9 | 1297 | bool cur_state; |
702e7a56 PZ |
1298 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1299 | pipe); | |
b24e7179 | 1300 | |
b6b5d049 VS |
1301 | /* if we need the pipe quirk it must be always on */ |
1302 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1303 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1304 | state = true; |
1305 | ||
f458ebbc | 1306 | if (!intel_display_power_is_enabled(dev_priv, |
b97186f0 | 1307 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
69310161 PZ |
1308 | cur_state = false; |
1309 | } else { | |
1310 | reg = PIPECONF(cpu_transcoder); | |
1311 | val = I915_READ(reg); | |
1312 | cur_state = !!(val & PIPECONF_ENABLE); | |
1313 | } | |
1314 | ||
e2c719b7 | 1315 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1316 | "pipe %c assertion failure (expected %s, current %s)\n", |
9db4a9c7 | 1317 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1318 | } |
1319 | ||
931872fc CW |
1320 | static void assert_plane(struct drm_i915_private *dev_priv, |
1321 | enum plane plane, bool state) | |
b24e7179 JB |
1322 | { |
1323 | int reg; | |
1324 | u32 val; | |
931872fc | 1325 | bool cur_state; |
b24e7179 JB |
1326 | |
1327 | reg = DSPCNTR(plane); | |
1328 | val = I915_READ(reg); | |
931872fc | 1329 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1330 | I915_STATE_WARN(cur_state != state, |
931872fc CW |
1331 | "plane %c assertion failure (expected %s, current %s)\n", |
1332 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1333 | } |
1334 | ||
931872fc CW |
1335 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1336 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1337 | ||
b24e7179 JB |
1338 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1339 | enum pipe pipe) | |
1340 | { | |
653e1026 | 1341 | struct drm_device *dev = dev_priv->dev; |
b24e7179 JB |
1342 | int reg, i; |
1343 | u32 val; | |
1344 | int cur_pipe; | |
1345 | ||
653e1026 VS |
1346 | /* Primary planes are fixed to pipes on gen4+ */ |
1347 | if (INTEL_INFO(dev)->gen >= 4) { | |
28c05794 AJ |
1348 | reg = DSPCNTR(pipe); |
1349 | val = I915_READ(reg); | |
e2c719b7 | 1350 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1351 | "plane %c assertion failure, should be disabled but not\n", |
1352 | plane_name(pipe)); | |
19ec1358 | 1353 | return; |
28c05794 | 1354 | } |
19ec1358 | 1355 | |
b24e7179 | 1356 | /* Need to check both planes against the pipe */ |
055e393f | 1357 | for_each_pipe(dev_priv, i) { |
b24e7179 JB |
1358 | reg = DSPCNTR(i); |
1359 | val = I915_READ(reg); | |
1360 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1361 | DISPPLANE_SEL_PIPE_SHIFT; | |
e2c719b7 | 1362 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1363 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1364 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1365 | } |
1366 | } | |
1367 | ||
19332d7a JB |
1368 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1369 | enum pipe pipe) | |
1370 | { | |
20674eef | 1371 | struct drm_device *dev = dev_priv->dev; |
1fe47785 | 1372 | int reg, sprite; |
19332d7a JB |
1373 | u32 val; |
1374 | ||
7feb8b88 | 1375 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1376 | for_each_sprite(dev_priv, pipe, sprite) { |
7feb8b88 | 1377 | val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1378 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1379 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1380 | sprite, pipe_name(pipe)); | |
1381 | } | |
1382 | } else if (IS_VALLEYVIEW(dev)) { | |
3bdcfc0c | 1383 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 1384 | reg = SPCNTR(pipe, sprite); |
20674eef | 1385 | val = I915_READ(reg); |
e2c719b7 | 1386 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1387 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1388 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1389 | } |
1390 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
1391 | reg = SPRCTL(pipe); | |
19332d7a | 1392 | val = I915_READ(reg); |
e2c719b7 | 1393 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1394 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1395 | plane_name(pipe), pipe_name(pipe)); |
1396 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1397 | reg = DVSCNTR(pipe); | |
19332d7a | 1398 | val = I915_READ(reg); |
e2c719b7 | 1399 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1400 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1401 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1402 | } |
1403 | } | |
1404 | ||
08c71e5e VS |
1405 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1406 | { | |
e2c719b7 | 1407 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1408 | drm_crtc_vblank_put(crtc); |
1409 | } | |
1410 | ||
89eff4be | 1411 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1412 | { |
1413 | u32 val; | |
1414 | bool enabled; | |
1415 | ||
e2c719b7 | 1416 | I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1417 | |
92f2584a JB |
1418 | val = I915_READ(PCH_DREF_CONTROL); |
1419 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1420 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
e2c719b7 | 1421 | I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
92f2584a JB |
1422 | } |
1423 | ||
ab9412ba DV |
1424 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1425 | enum pipe pipe) | |
92f2584a JB |
1426 | { |
1427 | int reg; | |
1428 | u32 val; | |
1429 | bool enabled; | |
1430 | ||
ab9412ba | 1431 | reg = PCH_TRANSCONF(pipe); |
92f2584a JB |
1432 | val = I915_READ(reg); |
1433 | enabled = !!(val & TRANS_ENABLE); | |
e2c719b7 | 1434 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1435 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1436 | pipe_name(pipe)); | |
92f2584a JB |
1437 | } |
1438 | ||
4e634389 KP |
1439 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1440 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1441 | { |
1442 | if ((val & DP_PORT_EN) == 0) | |
1443 | return false; | |
1444 | ||
1445 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1446 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1447 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1448 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1449 | return false; | |
44f37d1f CML |
1450 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1451 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1452 | return false; | |
f0575e92 KP |
1453 | } else { |
1454 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1455 | return false; | |
1456 | } | |
1457 | return true; | |
1458 | } | |
1459 | ||
1519b995 KP |
1460 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1461 | enum pipe pipe, u32 val) | |
1462 | { | |
dc0fa718 | 1463 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1464 | return false; |
1465 | ||
1466 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1467 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1468 | return false; |
44f37d1f CML |
1469 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1470 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1471 | return false; | |
1519b995 | 1472 | } else { |
dc0fa718 | 1473 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1474 | return false; |
1475 | } | |
1476 | return true; | |
1477 | } | |
1478 | ||
1479 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1480 | enum pipe pipe, u32 val) | |
1481 | { | |
1482 | if ((val & LVDS_PORT_EN) == 0) | |
1483 | return false; | |
1484 | ||
1485 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1486 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1487 | return false; | |
1488 | } else { | |
1489 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1490 | return false; | |
1491 | } | |
1492 | return true; | |
1493 | } | |
1494 | ||
1495 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1496 | enum pipe pipe, u32 val) | |
1497 | { | |
1498 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1499 | return false; | |
1500 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1501 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1502 | return false; | |
1503 | } else { | |
1504 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1505 | return false; | |
1506 | } | |
1507 | return true; | |
1508 | } | |
1509 | ||
291906f1 | 1510 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1511 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1512 | { |
47a05eca | 1513 | u32 val = I915_READ(reg); |
e2c719b7 | 1514 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1515 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1516 | reg, pipe_name(pipe)); |
de9a35ab | 1517 | |
e2c719b7 | 1518 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1519 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1520 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1521 | } |
1522 | ||
1523 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1524 | enum pipe pipe, int reg) | |
1525 | { | |
47a05eca | 1526 | u32 val = I915_READ(reg); |
e2c719b7 | 1527 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1528 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1529 | reg, pipe_name(pipe)); |
de9a35ab | 1530 | |
e2c719b7 | 1531 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1532 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1533 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1534 | } |
1535 | ||
1536 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1537 | enum pipe pipe) | |
1538 | { | |
1539 | int reg; | |
1540 | u32 val; | |
291906f1 | 1541 | |
f0575e92 KP |
1542 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1543 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1544 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1545 | |
1546 | reg = PCH_ADPA; | |
1547 | val = I915_READ(reg); | |
e2c719b7 | 1548 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1549 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1550 | pipe_name(pipe)); |
291906f1 JB |
1551 | |
1552 | reg = PCH_LVDS; | |
1553 | val = I915_READ(reg); | |
e2c719b7 | 1554 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1555 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1556 | pipe_name(pipe)); |
291906f1 | 1557 | |
e2debe91 PZ |
1558 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1559 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1560 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1561 | } |
1562 | ||
40e9cf64 JB |
1563 | static void intel_init_dpio(struct drm_device *dev) |
1564 | { | |
1565 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1566 | ||
1567 | if (!IS_VALLEYVIEW(dev)) | |
1568 | return; | |
1569 | ||
a09caddd CML |
1570 | /* |
1571 | * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), | |
1572 | * CHV x1 PHY (DP/HDMI D) | |
1573 | * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) | |
1574 | */ | |
1575 | if (IS_CHERRYVIEW(dev)) { | |
1576 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; | |
1577 | DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO; | |
1578 | } else { | |
1579 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; | |
1580 | } | |
5382f5f3 JB |
1581 | } |
1582 | ||
d288f65f | 1583 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1584 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1585 | { |
426115cf DV |
1586 | struct drm_device *dev = crtc->base.dev; |
1587 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1588 | int reg = DPLL(crtc->pipe); | |
d288f65f | 1589 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
87442f73 | 1590 | |
426115cf | 1591 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 DV |
1592 | |
1593 | /* No really, not for ILK+ */ | |
1594 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
1595 | ||
1596 | /* PLL is protected by panel, make sure we can write it */ | |
6a9e7363 | 1597 | if (IS_MOBILE(dev_priv->dev)) |
426115cf | 1598 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1599 | |
426115cf DV |
1600 | I915_WRITE(reg, dpll); |
1601 | POSTING_READ(reg); | |
1602 | udelay(150); | |
1603 | ||
1604 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1605 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1606 | ||
d288f65f | 1607 | I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); |
426115cf | 1608 | POSTING_READ(DPLL_MD(crtc->pipe)); |
87442f73 DV |
1609 | |
1610 | /* We do this three times for luck */ | |
426115cf | 1611 | I915_WRITE(reg, dpll); |
87442f73 DV |
1612 | POSTING_READ(reg); |
1613 | udelay(150); /* wait for warmup */ | |
426115cf | 1614 | I915_WRITE(reg, dpll); |
87442f73 DV |
1615 | POSTING_READ(reg); |
1616 | udelay(150); /* wait for warmup */ | |
426115cf | 1617 | I915_WRITE(reg, dpll); |
87442f73 DV |
1618 | POSTING_READ(reg); |
1619 | udelay(150); /* wait for warmup */ | |
1620 | } | |
1621 | ||
d288f65f | 1622 | static void chv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1623 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
1624 | { |
1625 | struct drm_device *dev = crtc->base.dev; | |
1626 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1627 | int pipe = crtc->pipe; | |
1628 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1629 | u32 tmp; |
1630 | ||
1631 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1632 | ||
1633 | BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); | |
1634 | ||
1635 | mutex_lock(&dev_priv->dpio_lock); | |
1636 | ||
1637 | /* Enable back the 10bit clock to display controller */ | |
1638 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1639 | tmp |= DPIO_DCLKP_EN; | |
1640 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1641 | ||
1642 | /* | |
1643 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1644 | */ | |
1645 | udelay(1); | |
1646 | ||
1647 | /* Enable PLL */ | |
d288f65f | 1648 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1649 | |
1650 | /* Check PLL is locked */ | |
a11b0703 | 1651 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1652 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1653 | ||
a11b0703 | 1654 | /* not sure when this should be written */ |
d288f65f | 1655 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
a11b0703 VS |
1656 | POSTING_READ(DPLL_MD(pipe)); |
1657 | ||
9d556c99 CML |
1658 | mutex_unlock(&dev_priv->dpio_lock); |
1659 | } | |
1660 | ||
1c4e0274 VS |
1661 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1662 | { | |
1663 | struct intel_crtc *crtc; | |
1664 | int count = 0; | |
1665 | ||
1666 | for_each_intel_crtc(dev, crtc) | |
1667 | count += crtc->active && | |
409ee761 | 1668 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
1c4e0274 VS |
1669 | |
1670 | return count; | |
1671 | } | |
1672 | ||
66e3d5c0 | 1673 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1674 | { |
66e3d5c0 DV |
1675 | struct drm_device *dev = crtc->base.dev; |
1676 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1677 | int reg = DPLL(crtc->pipe); | |
6e3c9717 | 1678 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1679 | |
66e3d5c0 | 1680 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1681 | |
63d7bbe9 | 1682 | /* No really, not for ILK+ */ |
3d13ef2e | 1683 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1684 | |
1685 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1686 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1687 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1688 | |
1c4e0274 VS |
1689 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1690 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1691 | /* | |
1692 | * It appears to be important that we don't enable this | |
1693 | * for the current pipe before otherwise configuring the | |
1694 | * PLL. No idea how this should be handled if multiple | |
1695 | * DVO outputs are enabled simultaneosly. | |
1696 | */ | |
1697 | dpll |= DPLL_DVO_2X_MODE; | |
1698 | I915_WRITE(DPLL(!crtc->pipe), | |
1699 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1700 | } | |
66e3d5c0 DV |
1701 | |
1702 | /* Wait for the clocks to stabilize. */ | |
1703 | POSTING_READ(reg); | |
1704 | udelay(150); | |
1705 | ||
1706 | if (INTEL_INFO(dev)->gen >= 4) { | |
1707 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1708 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1709 | } else { |
1710 | /* The pixel multiplier can only be updated once the | |
1711 | * DPLL is enabled and the clocks are stable. | |
1712 | * | |
1713 | * So write it again. | |
1714 | */ | |
1715 | I915_WRITE(reg, dpll); | |
1716 | } | |
63d7bbe9 JB |
1717 | |
1718 | /* We do this three times for luck */ | |
66e3d5c0 | 1719 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1720 | POSTING_READ(reg); |
1721 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1722 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1723 | POSTING_READ(reg); |
1724 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1725 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1726 | POSTING_READ(reg); |
1727 | udelay(150); /* wait for warmup */ | |
1728 | } | |
1729 | ||
1730 | /** | |
50b44a44 | 1731 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1732 | * @dev_priv: i915 private structure |
1733 | * @pipe: pipe PLL to disable | |
1734 | * | |
1735 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1736 | * | |
1737 | * Note! This is for pre-ILK only. | |
1738 | */ | |
1c4e0274 | 1739 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1740 | { |
1c4e0274 VS |
1741 | struct drm_device *dev = crtc->base.dev; |
1742 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1743 | enum pipe pipe = crtc->pipe; | |
1744 | ||
1745 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1746 | if (IS_I830(dev) && | |
409ee761 | 1747 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
1c4e0274 VS |
1748 | intel_num_dvo_pipes(dev) == 1) { |
1749 | I915_WRITE(DPLL(PIPE_B), | |
1750 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1751 | I915_WRITE(DPLL(PIPE_A), | |
1752 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1753 | } | |
1754 | ||
b6b5d049 VS |
1755 | /* Don't disable pipe or pipe PLLs if needed */ |
1756 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1757 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1758 | return; |
1759 | ||
1760 | /* Make sure the pipe isn't still relying on us */ | |
1761 | assert_pipe_disabled(dev_priv, pipe); | |
1762 | ||
50b44a44 DV |
1763 | I915_WRITE(DPLL(pipe), 0); |
1764 | POSTING_READ(DPLL(pipe)); | |
63d7bbe9 JB |
1765 | } |
1766 | ||
f6071166 JB |
1767 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1768 | { | |
1769 | u32 val = 0; | |
1770 | ||
1771 | /* Make sure the pipe isn't still relying on us */ | |
1772 | assert_pipe_disabled(dev_priv, pipe); | |
1773 | ||
e5cbfbfb ID |
1774 | /* |
1775 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1776 | * The latter is needed for VGA hotplug / manual detection. | |
1777 | */ | |
f6071166 | 1778 | if (pipe == PIPE_B) |
e5cbfbfb | 1779 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; |
f6071166 JB |
1780 | I915_WRITE(DPLL(pipe), val); |
1781 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1782 | |
1783 | } | |
1784 | ||
1785 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1786 | { | |
d752048d | 1787 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1788 | u32 val; |
1789 | ||
a11b0703 VS |
1790 | /* Make sure the pipe isn't still relying on us */ |
1791 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1792 | |
a11b0703 | 1793 | /* Set PLL en = 0 */ |
d17ec4ce | 1794 | val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV; |
a11b0703 VS |
1795 | if (pipe != PIPE_A) |
1796 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1797 | I915_WRITE(DPLL(pipe), val); | |
1798 | POSTING_READ(DPLL(pipe)); | |
d752048d VS |
1799 | |
1800 | mutex_lock(&dev_priv->dpio_lock); | |
1801 | ||
1802 | /* Disable 10bit clock to display controller */ | |
1803 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1804 | val &= ~DPIO_DCLKP_EN; | |
1805 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1806 | ||
61407f6d VS |
1807 | /* disable left/right clock distribution */ |
1808 | if (pipe != PIPE_B) { | |
1809 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
1810 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
1811 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
1812 | } else { | |
1813 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
1814 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
1815 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
1816 | } | |
1817 | ||
d752048d | 1818 | mutex_unlock(&dev_priv->dpio_lock); |
f6071166 JB |
1819 | } |
1820 | ||
e4607fcf CML |
1821 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
1822 | struct intel_digital_port *dport) | |
89b667f8 JB |
1823 | { |
1824 | u32 port_mask; | |
00fc31b7 | 1825 | int dpll_reg; |
89b667f8 | 1826 | |
e4607fcf CML |
1827 | switch (dport->port) { |
1828 | case PORT_B: | |
89b667f8 | 1829 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1830 | dpll_reg = DPLL(0); |
e4607fcf CML |
1831 | break; |
1832 | case PORT_C: | |
89b667f8 | 1833 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 CML |
1834 | dpll_reg = DPLL(0); |
1835 | break; | |
1836 | case PORT_D: | |
1837 | port_mask = DPLL_PORTD_READY_MASK; | |
1838 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1839 | break; |
1840 | default: | |
1841 | BUG(); | |
1842 | } | |
89b667f8 | 1843 | |
00fc31b7 | 1844 | if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000)) |
89b667f8 | 1845 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", |
00fc31b7 | 1846 | port_name(dport->port), I915_READ(dpll_reg)); |
89b667f8 JB |
1847 | } |
1848 | ||
b14b1055 DV |
1849 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1850 | { | |
1851 | struct drm_device *dev = crtc->base.dev; | |
1852 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1853 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
1854 | ||
be19f0ff CW |
1855 | if (WARN_ON(pll == NULL)) |
1856 | return; | |
1857 | ||
3e369b76 | 1858 | WARN_ON(!pll->config.crtc_mask); |
b14b1055 DV |
1859 | if (pll->active == 0) { |
1860 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
1861 | WARN_ON(pll->on); | |
1862 | assert_shared_dpll_disabled(dev_priv, pll); | |
1863 | ||
1864 | pll->mode_set(dev_priv, pll); | |
1865 | } | |
1866 | } | |
1867 | ||
92f2584a | 1868 | /** |
85b3894f | 1869 | * intel_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1870 | * @dev_priv: i915 private structure |
1871 | * @pipe: pipe PLL to enable | |
1872 | * | |
1873 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1874 | * drives the transcoder clock. | |
1875 | */ | |
85b3894f | 1876 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1877 | { |
3d13ef2e DL |
1878 | struct drm_device *dev = crtc->base.dev; |
1879 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1880 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1881 | |
87a875bb | 1882 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1883 | return; |
1884 | ||
3e369b76 | 1885 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1886 | return; |
ee7b9f93 | 1887 | |
74dd6928 | 1888 | DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n", |
46edb027 | 1889 | pll->name, pll->active, pll->on, |
e2b78267 | 1890 | crtc->base.base.id); |
92f2584a | 1891 | |
cdbd2316 DV |
1892 | if (pll->active++) { |
1893 | WARN_ON(!pll->on); | |
e9d6944e | 1894 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1895 | return; |
1896 | } | |
f4a091c7 | 1897 | WARN_ON(pll->on); |
ee7b9f93 | 1898 | |
bd2bb1b9 PZ |
1899 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
1900 | ||
46edb027 | 1901 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1902 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1903 | pll->on = true; |
92f2584a JB |
1904 | } |
1905 | ||
f6daaec2 | 1906 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1907 | { |
3d13ef2e DL |
1908 | struct drm_device *dev = crtc->base.dev; |
1909 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1910 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1911 | |
92f2584a | 1912 | /* PCH only available on ILK+ */ |
3d13ef2e | 1913 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
87a875bb | 1914 | if (WARN_ON(pll == NULL)) |
ee7b9f93 | 1915 | return; |
92f2584a | 1916 | |
3e369b76 | 1917 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1918 | return; |
7a419866 | 1919 | |
46edb027 DV |
1920 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1921 | pll->name, pll->active, pll->on, | |
e2b78267 | 1922 | crtc->base.base.id); |
7a419866 | 1923 | |
48da64a8 | 1924 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1925 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1926 | return; |
1927 | } | |
1928 | ||
e9d6944e | 1929 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1930 | WARN_ON(!pll->on); |
cdbd2316 | 1931 | if (--pll->active) |
7a419866 | 1932 | return; |
ee7b9f93 | 1933 | |
46edb027 | 1934 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1935 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1936 | pll->on = false; |
bd2bb1b9 PZ |
1937 | |
1938 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
92f2584a JB |
1939 | } |
1940 | ||
b8a4f404 PZ |
1941 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1942 | enum pipe pipe) | |
040484af | 1943 | { |
23670b32 | 1944 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1945 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1946 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
23670b32 | 1947 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1948 | |
1949 | /* PCH only available on ILK+ */ | |
55522f37 | 1950 | BUG_ON(!HAS_PCH_SPLIT(dev)); |
040484af JB |
1951 | |
1952 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1953 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1954 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1955 | |
1956 | /* FDI must be feeding us bits for PCH ports */ | |
1957 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1958 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1959 | ||
23670b32 DV |
1960 | if (HAS_PCH_CPT(dev)) { |
1961 | /* Workaround: Set the timing override bit before enabling the | |
1962 | * pch transcoder. */ | |
1963 | reg = TRANS_CHICKEN2(pipe); | |
1964 | val = I915_READ(reg); | |
1965 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1966 | I915_WRITE(reg, val); | |
59c859d6 | 1967 | } |
23670b32 | 1968 | |
ab9412ba | 1969 | reg = PCH_TRANSCONF(pipe); |
040484af | 1970 | val = I915_READ(reg); |
5f7f726d | 1971 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1972 | |
1973 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1974 | /* | |
1975 | * make the BPC in transcoder be consistent with | |
1976 | * that in pipeconf reg. | |
1977 | */ | |
dfd07d72 DV |
1978 | val &= ~PIPECONF_BPC_MASK; |
1979 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1980 | } |
5f7f726d PZ |
1981 | |
1982 | val &= ~TRANS_INTERLACE_MASK; | |
1983 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 | 1984 | if (HAS_PCH_IBX(dev_priv->dev) && |
409ee761 | 1985 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
1986 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1987 | else | |
1988 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1989 | else |
1990 | val |= TRANS_PROGRESSIVE; | |
1991 | ||
040484af JB |
1992 | I915_WRITE(reg, val | TRANS_ENABLE); |
1993 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 1994 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1995 | } |
1996 | ||
8fb033d7 | 1997 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1998 | enum transcoder cpu_transcoder) |
040484af | 1999 | { |
8fb033d7 | 2000 | u32 val, pipeconf_val; |
8fb033d7 PZ |
2001 | |
2002 | /* PCH only available on ILK+ */ | |
55522f37 | 2003 | BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev)); |
8fb033d7 | 2004 | |
8fb033d7 | 2005 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 2006 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 2007 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 2008 | |
223a6fdf PZ |
2009 | /* Workaround: set timing override bit. */ |
2010 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 2011 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
2012 | I915_WRITE(_TRANSA_CHICKEN2, val); |
2013 | ||
25f3ef11 | 2014 | val = TRANS_ENABLE; |
937bb610 | 2015 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 2016 | |
9a76b1c6 PZ |
2017 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
2018 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 2019 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
2020 | else |
2021 | val |= TRANS_PROGRESSIVE; | |
2022 | ||
ab9412ba DV |
2023 | I915_WRITE(LPT_TRANSCONF, val); |
2024 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 2025 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
2026 | } |
2027 | ||
b8a4f404 PZ |
2028 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
2029 | enum pipe pipe) | |
040484af | 2030 | { |
23670b32 DV |
2031 | struct drm_device *dev = dev_priv->dev; |
2032 | uint32_t reg, val; | |
040484af JB |
2033 | |
2034 | /* FDI relies on the transcoder */ | |
2035 | assert_fdi_tx_disabled(dev_priv, pipe); | |
2036 | assert_fdi_rx_disabled(dev_priv, pipe); | |
2037 | ||
291906f1 JB |
2038 | /* Ports must be off as well */ |
2039 | assert_pch_ports_disabled(dev_priv, pipe); | |
2040 | ||
ab9412ba | 2041 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
2042 | val = I915_READ(reg); |
2043 | val &= ~TRANS_ENABLE; | |
2044 | I915_WRITE(reg, val); | |
2045 | /* wait for PCH transcoder off, transcoder state */ | |
2046 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 2047 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 DV |
2048 | |
2049 | if (!HAS_PCH_IBX(dev)) { | |
2050 | /* Workaround: Clear the timing override chicken bit again. */ | |
2051 | reg = TRANS_CHICKEN2(pipe); | |
2052 | val = I915_READ(reg); | |
2053 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
2054 | I915_WRITE(reg, val); | |
2055 | } | |
040484af JB |
2056 | } |
2057 | ||
ab4d966c | 2058 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 2059 | { |
8fb033d7 PZ |
2060 | u32 val; |
2061 | ||
ab9412ba | 2062 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 2063 | val &= ~TRANS_ENABLE; |
ab9412ba | 2064 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 2065 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 2066 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 2067 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
2068 | |
2069 | /* Workaround: clear timing override bit. */ | |
2070 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 2071 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 2072 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
2073 | } |
2074 | ||
b24e7179 | 2075 | /** |
309cfea8 | 2076 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 2077 | * @crtc: crtc responsible for the pipe |
b24e7179 | 2078 | * |
0372264a | 2079 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 2080 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 2081 | */ |
e1fdc473 | 2082 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2083 | { |
0372264a PZ |
2084 | struct drm_device *dev = crtc->base.dev; |
2085 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2086 | enum pipe pipe = crtc->pipe; | |
702e7a56 PZ |
2087 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
2088 | pipe); | |
1a240d4d | 2089 | enum pipe pch_transcoder; |
b24e7179 JB |
2090 | int reg; |
2091 | u32 val; | |
2092 | ||
58c6eaa2 | 2093 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 2094 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
2095 | assert_sprites_disabled(dev_priv, pipe); |
2096 | ||
681e5811 | 2097 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
2098 | pch_transcoder = TRANSCODER_A; |
2099 | else | |
2100 | pch_transcoder = pipe; | |
2101 | ||
b24e7179 JB |
2102 | /* |
2103 | * A pipe without a PLL won't actually be able to drive bits from | |
2104 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
2105 | * need the check. | |
2106 | */ | |
2107 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
409ee761 | 2108 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
2109 | assert_dsi_pll_enabled(dev_priv); |
2110 | else | |
2111 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2112 | else { |
6e3c9717 | 2113 | if (crtc->config->has_pch_encoder) { |
040484af | 2114 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2115 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2116 | assert_fdi_tx_pll_enabled(dev_priv, |
2117 | (enum pipe) cpu_transcoder); | |
040484af JB |
2118 | } |
2119 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2120 | } | |
b24e7179 | 2121 | |
702e7a56 | 2122 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2123 | val = I915_READ(reg); |
7ad25d48 | 2124 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
2125 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
2126 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 2127 | return; |
7ad25d48 | 2128 | } |
00d70b15 CW |
2129 | |
2130 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2131 | POSTING_READ(reg); |
b24e7179 JB |
2132 | } |
2133 | ||
2134 | /** | |
309cfea8 | 2135 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2136 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2137 | * |
575f7ab7 VS |
2138 | * Disable the pipe of @crtc, making sure that various hardware |
2139 | * specific requirements are met, if applicable, e.g. plane | |
2140 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2141 | * |
2142 | * Will wait until the pipe has shut down before returning. | |
2143 | */ | |
575f7ab7 | 2144 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2145 | { |
575f7ab7 | 2146 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
6e3c9717 | 2147 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2148 | enum pipe pipe = crtc->pipe; |
b24e7179 JB |
2149 | int reg; |
2150 | u32 val; | |
2151 | ||
2152 | /* | |
2153 | * Make sure planes won't keep trying to pump pixels to us, | |
2154 | * or we might hang the display. | |
2155 | */ | |
2156 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2157 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2158 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2159 | |
702e7a56 | 2160 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2161 | val = I915_READ(reg); |
00d70b15 CW |
2162 | if ((val & PIPECONF_ENABLE) == 0) |
2163 | return; | |
2164 | ||
67adc644 VS |
2165 | /* |
2166 | * Double wide has implications for planes | |
2167 | * so best keep it disabled when not needed. | |
2168 | */ | |
6e3c9717 | 2169 | if (crtc->config->double_wide) |
67adc644 VS |
2170 | val &= ~PIPECONF_DOUBLE_WIDE; |
2171 | ||
2172 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2173 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2174 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2175 | val &= ~PIPECONF_ENABLE; |
2176 | ||
2177 | I915_WRITE(reg, val); | |
2178 | if ((val & PIPECONF_ENABLE) == 0) | |
2179 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2180 | } |
2181 | ||
d74362c9 KP |
2182 | /* |
2183 | * Plane regs are double buffered, going from enabled->disabled needs a | |
2184 | * trigger in order to latch. The display address reg provides this. | |
2185 | */ | |
1dba99f4 VS |
2186 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
2187 | enum plane plane) | |
d74362c9 | 2188 | { |
3d13ef2e DL |
2189 | struct drm_device *dev = dev_priv->dev; |
2190 | u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); | |
1dba99f4 VS |
2191 | |
2192 | I915_WRITE(reg, I915_READ(reg)); | |
2193 | POSTING_READ(reg); | |
d74362c9 KP |
2194 | } |
2195 | ||
b24e7179 | 2196 | /** |
262ca2b0 | 2197 | * intel_enable_primary_hw_plane - enable the primary plane on a given pipe |
fdd508a6 VS |
2198 | * @plane: plane to be enabled |
2199 | * @crtc: crtc for the plane | |
b24e7179 | 2200 | * |
fdd508a6 | 2201 | * Enable @plane on @crtc, making sure that the pipe is running first. |
b24e7179 | 2202 | */ |
fdd508a6 VS |
2203 | static void intel_enable_primary_hw_plane(struct drm_plane *plane, |
2204 | struct drm_crtc *crtc) | |
b24e7179 | 2205 | { |
fdd508a6 VS |
2206 | struct drm_device *dev = plane->dev; |
2207 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2208 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b24e7179 JB |
2209 | |
2210 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
fdd508a6 | 2211 | assert_pipe_enabled(dev_priv, intel_crtc->pipe); |
b24e7179 | 2212 | |
98ec7739 VS |
2213 | if (intel_crtc->primary_enabled) |
2214 | return; | |
0037f71c | 2215 | |
4c445e0e | 2216 | intel_crtc->primary_enabled = true; |
939c2fe8 | 2217 | |
fdd508a6 VS |
2218 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
2219 | crtc->x, crtc->y); | |
33c3b0d1 VS |
2220 | |
2221 | /* | |
2222 | * BDW signals flip done immediately if the plane | |
2223 | * is disabled, even if the plane enable is already | |
2224 | * armed to occur at the next vblank :( | |
2225 | */ | |
2226 | if (IS_BROADWELL(dev)) | |
2227 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
b24e7179 JB |
2228 | } |
2229 | ||
b24e7179 | 2230 | /** |
262ca2b0 | 2231 | * intel_disable_primary_hw_plane - disable the primary hardware plane |
fdd508a6 VS |
2232 | * @plane: plane to be disabled |
2233 | * @crtc: crtc for the plane | |
b24e7179 | 2234 | * |
fdd508a6 | 2235 | * Disable @plane on @crtc, making sure that the pipe is running first. |
b24e7179 | 2236 | */ |
fdd508a6 VS |
2237 | static void intel_disable_primary_hw_plane(struct drm_plane *plane, |
2238 | struct drm_crtc *crtc) | |
b24e7179 | 2239 | { |
fdd508a6 VS |
2240 | struct drm_device *dev = plane->dev; |
2241 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2242 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2243 | ||
32b7eeec MR |
2244 | if (WARN_ON(!intel_crtc->active)) |
2245 | return; | |
b24e7179 | 2246 | |
98ec7739 VS |
2247 | if (!intel_crtc->primary_enabled) |
2248 | return; | |
0037f71c | 2249 | |
4c445e0e | 2250 | intel_crtc->primary_enabled = false; |
939c2fe8 | 2251 | |
fdd508a6 VS |
2252 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
2253 | crtc->x, crtc->y); | |
b24e7179 JB |
2254 | } |
2255 | ||
693db184 CW |
2256 | static bool need_vtd_wa(struct drm_device *dev) |
2257 | { | |
2258 | #ifdef CONFIG_INTEL_IOMMU | |
2259 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2260 | return true; | |
2261 | #endif | |
2262 | return false; | |
2263 | } | |
2264 | ||
50470bb0 | 2265 | unsigned int |
6761dd31 TU |
2266 | intel_tile_height(struct drm_device *dev, uint32_t pixel_format, |
2267 | uint64_t fb_format_modifier) | |
a57ce0b2 | 2268 | { |
6761dd31 TU |
2269 | unsigned int tile_height; |
2270 | uint32_t pixel_bytes; | |
a57ce0b2 | 2271 | |
b5d0e9bf DL |
2272 | switch (fb_format_modifier) { |
2273 | case DRM_FORMAT_MOD_NONE: | |
2274 | tile_height = 1; | |
2275 | break; | |
2276 | case I915_FORMAT_MOD_X_TILED: | |
2277 | tile_height = IS_GEN2(dev) ? 16 : 8; | |
2278 | break; | |
2279 | case I915_FORMAT_MOD_Y_TILED: | |
2280 | tile_height = 32; | |
2281 | break; | |
2282 | case I915_FORMAT_MOD_Yf_TILED: | |
6761dd31 TU |
2283 | pixel_bytes = drm_format_plane_cpp(pixel_format, 0); |
2284 | switch (pixel_bytes) { | |
b5d0e9bf | 2285 | default: |
6761dd31 | 2286 | case 1: |
b5d0e9bf DL |
2287 | tile_height = 64; |
2288 | break; | |
6761dd31 TU |
2289 | case 2: |
2290 | case 4: | |
b5d0e9bf DL |
2291 | tile_height = 32; |
2292 | break; | |
6761dd31 | 2293 | case 8: |
b5d0e9bf DL |
2294 | tile_height = 16; |
2295 | break; | |
6761dd31 | 2296 | case 16: |
b5d0e9bf DL |
2297 | WARN_ONCE(1, |
2298 | "128-bit pixels are not supported for display!"); | |
2299 | tile_height = 16; | |
2300 | break; | |
2301 | } | |
2302 | break; | |
2303 | default: | |
2304 | MISSING_CASE(fb_format_modifier); | |
2305 | tile_height = 1; | |
2306 | break; | |
2307 | } | |
091df6cb | 2308 | |
6761dd31 TU |
2309 | return tile_height; |
2310 | } | |
2311 | ||
2312 | unsigned int | |
2313 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
2314 | uint32_t pixel_format, uint64_t fb_format_modifier) | |
2315 | { | |
2316 | return ALIGN(height, intel_tile_height(dev, pixel_format, | |
2317 | fb_format_modifier)); | |
a57ce0b2 JB |
2318 | } |
2319 | ||
f64b98cd TU |
2320 | static int |
2321 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb, | |
2322 | const struct drm_plane_state *plane_state) | |
2323 | { | |
50470bb0 | 2324 | struct intel_rotation_info *info = &view->rotation_info; |
50470bb0 | 2325 | |
f64b98cd TU |
2326 | *view = i915_ggtt_view_normal; |
2327 | ||
50470bb0 TU |
2328 | if (!plane_state) |
2329 | return 0; | |
2330 | ||
121920fa | 2331 | if (!intel_rotation_90_or_270(plane_state->rotation)) |
50470bb0 TU |
2332 | return 0; |
2333 | ||
9abc4648 | 2334 | *view = i915_ggtt_view_rotated; |
50470bb0 TU |
2335 | |
2336 | info->height = fb->height; | |
2337 | info->pixel_format = fb->pixel_format; | |
2338 | info->pitch = fb->pitches[0]; | |
2339 | info->fb_modifier = fb->modifier[0]; | |
2340 | ||
f64b98cd TU |
2341 | return 0; |
2342 | } | |
2343 | ||
127bd2ac | 2344 | int |
850c4cdc TU |
2345 | intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
2346 | struct drm_framebuffer *fb, | |
82bc3b2d | 2347 | const struct drm_plane_state *plane_state, |
a4872ba6 | 2348 | struct intel_engine_cs *pipelined) |
6b95a207 | 2349 | { |
850c4cdc | 2350 | struct drm_device *dev = fb->dev; |
ce453d81 | 2351 | struct drm_i915_private *dev_priv = dev->dev_private; |
850c4cdc | 2352 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2353 | struct i915_ggtt_view view; |
6b95a207 KH |
2354 | u32 alignment; |
2355 | int ret; | |
2356 | ||
ebcdd39e MR |
2357 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2358 | ||
7b911adc TU |
2359 | switch (fb->modifier[0]) { |
2360 | case DRM_FORMAT_MOD_NONE: | |
1fada4cc DL |
2361 | if (INTEL_INFO(dev)->gen >= 9) |
2362 | alignment = 256 * 1024; | |
2363 | else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) | |
534843da | 2364 | alignment = 128 * 1024; |
a6c45cf0 | 2365 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
2366 | alignment = 4 * 1024; |
2367 | else | |
2368 | alignment = 64 * 1024; | |
6b95a207 | 2369 | break; |
7b911adc | 2370 | case I915_FORMAT_MOD_X_TILED: |
1fada4cc DL |
2371 | if (INTEL_INFO(dev)->gen >= 9) |
2372 | alignment = 256 * 1024; | |
2373 | else { | |
2374 | /* pin() will align the object as required by fence */ | |
2375 | alignment = 0; | |
2376 | } | |
6b95a207 | 2377 | break; |
7b911adc | 2378 | case I915_FORMAT_MOD_Y_TILED: |
1327b9a1 DL |
2379 | case I915_FORMAT_MOD_Yf_TILED: |
2380 | if (WARN_ONCE(INTEL_INFO(dev)->gen < 9, | |
2381 | "Y tiling bo slipped through, driver bug!\n")) | |
2382 | return -EINVAL; | |
2383 | alignment = 1 * 1024 * 1024; | |
2384 | break; | |
6b95a207 | 2385 | default: |
7b911adc TU |
2386 | MISSING_CASE(fb->modifier[0]); |
2387 | return -EINVAL; | |
6b95a207 KH |
2388 | } |
2389 | ||
f64b98cd TU |
2390 | ret = intel_fill_fb_ggtt_view(&view, fb, plane_state); |
2391 | if (ret) | |
2392 | return ret; | |
2393 | ||
693db184 CW |
2394 | /* Note that the w/a also requires 64 PTE of padding following the |
2395 | * bo. We currently fill all unused PTE with the shadow page and so | |
2396 | * we should always have valid PTE following the scanout preventing | |
2397 | * the VT-d warning. | |
2398 | */ | |
2399 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2400 | alignment = 256 * 1024; | |
2401 | ||
d6dd6843 PZ |
2402 | /* |
2403 | * Global gtt pte registers are special registers which actually forward | |
2404 | * writes to a chunk of system memory. Which means that there is no risk | |
2405 | * that the register values disappear as soon as we call | |
2406 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2407 | * pin/unpin/fence and not more. | |
2408 | */ | |
2409 | intel_runtime_pm_get(dev_priv); | |
2410 | ||
ce453d81 | 2411 | dev_priv->mm.interruptible = false; |
e6617330 | 2412 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined, |
f64b98cd | 2413 | &view); |
48b956c5 | 2414 | if (ret) |
ce453d81 | 2415 | goto err_interruptible; |
6b95a207 KH |
2416 | |
2417 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2418 | * fence, whereas 965+ only requires a fence if using | |
2419 | * framebuffer compression. For simplicity, we always install | |
2420 | * a fence as the cost is not that onerous. | |
2421 | */ | |
06d98131 | 2422 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
2423 | if (ret) |
2424 | goto err_unpin; | |
1690e1eb | 2425 | |
9a5a53b3 | 2426 | i915_gem_object_pin_fence(obj); |
6b95a207 | 2427 | |
ce453d81 | 2428 | dev_priv->mm.interruptible = true; |
d6dd6843 | 2429 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2430 | return 0; |
48b956c5 CW |
2431 | |
2432 | err_unpin: | |
f64b98cd | 2433 | i915_gem_object_unpin_from_display_plane(obj, &view); |
ce453d81 CW |
2434 | err_interruptible: |
2435 | dev_priv->mm.interruptible = true; | |
d6dd6843 | 2436 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2437 | return ret; |
6b95a207 KH |
2438 | } |
2439 | ||
82bc3b2d TU |
2440 | static void intel_unpin_fb_obj(struct drm_framebuffer *fb, |
2441 | const struct drm_plane_state *plane_state) | |
1690e1eb | 2442 | { |
82bc3b2d | 2443 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd TU |
2444 | struct i915_ggtt_view view; |
2445 | int ret; | |
82bc3b2d | 2446 | |
ebcdd39e MR |
2447 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2448 | ||
f64b98cd TU |
2449 | ret = intel_fill_fb_ggtt_view(&view, fb, plane_state); |
2450 | WARN_ONCE(ret, "Couldn't get view from plane state!"); | |
2451 | ||
1690e1eb | 2452 | i915_gem_object_unpin_fence(obj); |
f64b98cd | 2453 | i915_gem_object_unpin_from_display_plane(obj, &view); |
1690e1eb CW |
2454 | } |
2455 | ||
c2c75131 DV |
2456 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2457 | * is assumed to be a power-of-two. */ | |
bc752862 CW |
2458 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
2459 | unsigned int tiling_mode, | |
2460 | unsigned int cpp, | |
2461 | unsigned int pitch) | |
c2c75131 | 2462 | { |
bc752862 CW |
2463 | if (tiling_mode != I915_TILING_NONE) { |
2464 | unsigned int tile_rows, tiles; | |
c2c75131 | 2465 | |
bc752862 CW |
2466 | tile_rows = *y / 8; |
2467 | *y %= 8; | |
c2c75131 | 2468 | |
bc752862 CW |
2469 | tiles = *x / (512/cpp); |
2470 | *x %= 512/cpp; | |
2471 | ||
2472 | return tile_rows * pitch * 8 + tiles * 4096; | |
2473 | } else { | |
2474 | unsigned int offset; | |
2475 | ||
2476 | offset = *y * pitch + *x * cpp; | |
2477 | *y = 0; | |
2478 | *x = (offset & 4095) / cpp; | |
2479 | return offset & -4096; | |
2480 | } | |
c2c75131 DV |
2481 | } |
2482 | ||
b35d63fa | 2483 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2484 | { |
2485 | switch (format) { | |
2486 | case DISPPLANE_8BPP: | |
2487 | return DRM_FORMAT_C8; | |
2488 | case DISPPLANE_BGRX555: | |
2489 | return DRM_FORMAT_XRGB1555; | |
2490 | case DISPPLANE_BGRX565: | |
2491 | return DRM_FORMAT_RGB565; | |
2492 | default: | |
2493 | case DISPPLANE_BGRX888: | |
2494 | return DRM_FORMAT_XRGB8888; | |
2495 | case DISPPLANE_RGBX888: | |
2496 | return DRM_FORMAT_XBGR8888; | |
2497 | case DISPPLANE_BGRX101010: | |
2498 | return DRM_FORMAT_XRGB2101010; | |
2499 | case DISPPLANE_RGBX101010: | |
2500 | return DRM_FORMAT_XBGR2101010; | |
2501 | } | |
2502 | } | |
2503 | ||
bc8d7dff DL |
2504 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2505 | { | |
2506 | switch (format) { | |
2507 | case PLANE_CTL_FORMAT_RGB_565: | |
2508 | return DRM_FORMAT_RGB565; | |
2509 | default: | |
2510 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2511 | if (rgb_order) { | |
2512 | if (alpha) | |
2513 | return DRM_FORMAT_ABGR8888; | |
2514 | else | |
2515 | return DRM_FORMAT_XBGR8888; | |
2516 | } else { | |
2517 | if (alpha) | |
2518 | return DRM_FORMAT_ARGB8888; | |
2519 | else | |
2520 | return DRM_FORMAT_XRGB8888; | |
2521 | } | |
2522 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2523 | if (rgb_order) | |
2524 | return DRM_FORMAT_XBGR2101010; | |
2525 | else | |
2526 | return DRM_FORMAT_XRGB2101010; | |
2527 | } | |
2528 | } | |
2529 | ||
5724dbd1 | 2530 | static bool |
f6936e29 DV |
2531 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2532 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2533 | { |
2534 | struct drm_device *dev = crtc->base.dev; | |
2535 | struct drm_i915_gem_object *obj = NULL; | |
2536 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2537 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2538 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2539 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2540 | PAGE_SIZE); | |
2541 | ||
2542 | size_aligned -= base_aligned; | |
46f297fb | 2543 | |
ff2652ea CW |
2544 | if (plane_config->size == 0) |
2545 | return false; | |
2546 | ||
f37b5c2b DV |
2547 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2548 | base_aligned, | |
2549 | base_aligned, | |
2550 | size_aligned); | |
46f297fb | 2551 | if (!obj) |
484b41dd | 2552 | return false; |
46f297fb | 2553 | |
49af449b DL |
2554 | obj->tiling_mode = plane_config->tiling; |
2555 | if (obj->tiling_mode == I915_TILING_X) | |
6bf129df | 2556 | obj->stride = fb->pitches[0]; |
46f297fb | 2557 | |
6bf129df DL |
2558 | mode_cmd.pixel_format = fb->pixel_format; |
2559 | mode_cmd.width = fb->width; | |
2560 | mode_cmd.height = fb->height; | |
2561 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2562 | mode_cmd.modifier[0] = fb->modifier[0]; |
2563 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb JB |
2564 | |
2565 | mutex_lock(&dev->struct_mutex); | |
6bf129df | 2566 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2567 | &mode_cmd, obj)) { |
46f297fb JB |
2568 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2569 | goto out_unref_obj; | |
2570 | } | |
46f297fb | 2571 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2572 | |
f6936e29 | 2573 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2574 | return true; |
46f297fb JB |
2575 | |
2576 | out_unref_obj: | |
2577 | drm_gem_object_unreference(&obj->base); | |
2578 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2579 | return false; |
2580 | } | |
2581 | ||
afd65eb4 MR |
2582 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2583 | static void | |
2584 | update_state_fb(struct drm_plane *plane) | |
2585 | { | |
2586 | if (plane->fb == plane->state->fb) | |
2587 | return; | |
2588 | ||
2589 | if (plane->state->fb) | |
2590 | drm_framebuffer_unreference(plane->state->fb); | |
2591 | plane->state->fb = plane->fb; | |
2592 | if (plane->state->fb) | |
2593 | drm_framebuffer_reference(plane->state->fb); | |
2594 | } | |
2595 | ||
5724dbd1 | 2596 | static void |
f6936e29 DV |
2597 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2598 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2599 | { |
2600 | struct drm_device *dev = intel_crtc->base.dev; | |
d9ceb816 | 2601 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd JB |
2602 | struct drm_crtc *c; |
2603 | struct intel_crtc *i; | |
2ff8fde1 | 2604 | struct drm_i915_gem_object *obj; |
88595ac9 DV |
2605 | struct drm_plane *primary = intel_crtc->base.primary; |
2606 | struct drm_framebuffer *fb; | |
484b41dd | 2607 | |
2d14030b | 2608 | if (!plane_config->fb) |
484b41dd JB |
2609 | return; |
2610 | ||
f6936e29 | 2611 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2612 | fb = &plane_config->fb->base; |
2613 | goto valid_fb; | |
f55548b5 | 2614 | } |
484b41dd | 2615 | |
2d14030b | 2616 | kfree(plane_config->fb); |
484b41dd JB |
2617 | |
2618 | /* | |
2619 | * Failed to alloc the obj, check to see if we should share | |
2620 | * an fb with another CRTC instead | |
2621 | */ | |
70e1e0ec | 2622 | for_each_crtc(dev, c) { |
484b41dd JB |
2623 | i = to_intel_crtc(c); |
2624 | ||
2625 | if (c == &intel_crtc->base) | |
2626 | continue; | |
2627 | ||
2ff8fde1 MR |
2628 | if (!i->active) |
2629 | continue; | |
2630 | ||
88595ac9 DV |
2631 | fb = c->primary->fb; |
2632 | if (!fb) | |
484b41dd JB |
2633 | continue; |
2634 | ||
88595ac9 | 2635 | obj = intel_fb_obj(fb); |
2ff8fde1 | 2636 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
88595ac9 DV |
2637 | drm_framebuffer_reference(fb); |
2638 | goto valid_fb; | |
484b41dd JB |
2639 | } |
2640 | } | |
88595ac9 DV |
2641 | |
2642 | return; | |
2643 | ||
2644 | valid_fb: | |
2645 | obj = intel_fb_obj(fb); | |
2646 | if (obj->tiling_mode != I915_TILING_NONE) | |
2647 | dev_priv->preserve_bios_swizzle = true; | |
2648 | ||
2649 | primary->fb = fb; | |
2650 | primary->state->crtc = &intel_crtc->base; | |
2651 | primary->crtc = &intel_crtc->base; | |
2652 | update_state_fb(primary); | |
2653 | obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); | |
46f297fb JB |
2654 | } |
2655 | ||
29b9bde6 DV |
2656 | static void i9xx_update_primary_plane(struct drm_crtc *crtc, |
2657 | struct drm_framebuffer *fb, | |
2658 | int x, int y) | |
81255565 JB |
2659 | { |
2660 | struct drm_device *dev = crtc->dev; | |
2661 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2662 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
c9ba6fad | 2663 | struct drm_i915_gem_object *obj; |
81255565 | 2664 | int plane = intel_crtc->plane; |
e506a0c6 | 2665 | unsigned long linear_offset; |
81255565 | 2666 | u32 dspcntr; |
f45651ba | 2667 | u32 reg = DSPCNTR(plane); |
48404c1e | 2668 | int pixel_size; |
f45651ba | 2669 | |
fdd508a6 VS |
2670 | if (!intel_crtc->primary_enabled) { |
2671 | I915_WRITE(reg, 0); | |
2672 | if (INTEL_INFO(dev)->gen >= 4) | |
2673 | I915_WRITE(DSPSURF(plane), 0); | |
2674 | else | |
2675 | I915_WRITE(DSPADDR(plane), 0); | |
2676 | POSTING_READ(reg); | |
2677 | return; | |
2678 | } | |
2679 | ||
c9ba6fad VS |
2680 | obj = intel_fb_obj(fb); |
2681 | if (WARN_ON(obj == NULL)) | |
2682 | return; | |
2683 | ||
2684 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2685 | ||
f45651ba VS |
2686 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2687 | ||
fdd508a6 | 2688 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2689 | |
2690 | if (INTEL_INFO(dev)->gen < 4) { | |
2691 | if (intel_crtc->pipe == PIPE_B) | |
2692 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2693 | ||
2694 | /* pipesrc and dspsize control the size that is scaled from, | |
2695 | * which should always be the user's requested size. | |
2696 | */ | |
2697 | I915_WRITE(DSPSIZE(plane), | |
6e3c9717 ACO |
2698 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2699 | (intel_crtc->config->pipe_src_w - 1)); | |
f45651ba | 2700 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
2701 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2702 | I915_WRITE(PRIMSIZE(plane), | |
6e3c9717 ACO |
2703 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2704 | (intel_crtc->config->pipe_src_w - 1)); | |
c14b0485 VS |
2705 | I915_WRITE(PRIMPOS(plane), 0); |
2706 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2707 | } |
81255565 | 2708 | |
57779d06 VS |
2709 | switch (fb->pixel_format) { |
2710 | case DRM_FORMAT_C8: | |
81255565 JB |
2711 | dspcntr |= DISPPLANE_8BPP; |
2712 | break; | |
57779d06 VS |
2713 | case DRM_FORMAT_XRGB1555: |
2714 | case DRM_FORMAT_ARGB1555: | |
2715 | dspcntr |= DISPPLANE_BGRX555; | |
81255565 | 2716 | break; |
57779d06 VS |
2717 | case DRM_FORMAT_RGB565: |
2718 | dspcntr |= DISPPLANE_BGRX565; | |
2719 | break; | |
2720 | case DRM_FORMAT_XRGB8888: | |
2721 | case DRM_FORMAT_ARGB8888: | |
2722 | dspcntr |= DISPPLANE_BGRX888; | |
2723 | break; | |
2724 | case DRM_FORMAT_XBGR8888: | |
2725 | case DRM_FORMAT_ABGR8888: | |
2726 | dspcntr |= DISPPLANE_RGBX888; | |
2727 | break; | |
2728 | case DRM_FORMAT_XRGB2101010: | |
2729 | case DRM_FORMAT_ARGB2101010: | |
2730 | dspcntr |= DISPPLANE_BGRX101010; | |
2731 | break; | |
2732 | case DRM_FORMAT_XBGR2101010: | |
2733 | case DRM_FORMAT_ABGR2101010: | |
2734 | dspcntr |= DISPPLANE_RGBX101010; | |
81255565 JB |
2735 | break; |
2736 | default: | |
baba133a | 2737 | BUG(); |
81255565 | 2738 | } |
57779d06 | 2739 | |
f45651ba VS |
2740 | if (INTEL_INFO(dev)->gen >= 4 && |
2741 | obj->tiling_mode != I915_TILING_NONE) | |
2742 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2743 | |
de1aa629 VS |
2744 | if (IS_G4X(dev)) |
2745 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2746 | ||
b9897127 | 2747 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
81255565 | 2748 | |
c2c75131 DV |
2749 | if (INTEL_INFO(dev)->gen >= 4) { |
2750 | intel_crtc->dspaddr_offset = | |
bc752862 | 2751 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
b9897127 | 2752 | pixel_size, |
bc752862 | 2753 | fb->pitches[0]); |
c2c75131 DV |
2754 | linear_offset -= intel_crtc->dspaddr_offset; |
2755 | } else { | |
e506a0c6 | 2756 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2757 | } |
e506a0c6 | 2758 | |
8e7d688b | 2759 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2760 | dspcntr |= DISPPLANE_ROTATE_180; |
2761 | ||
6e3c9717 ACO |
2762 | x += (intel_crtc->config->pipe_src_w - 1); |
2763 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2764 | |
2765 | /* Finding the last pixel of the last line of the display | |
2766 | data and adding to linear_offset*/ | |
2767 | linear_offset += | |
6e3c9717 ACO |
2768 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2769 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2770 | } |
2771 | ||
2772 | I915_WRITE(reg, dspcntr); | |
2773 | ||
01f2c773 | 2774 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2775 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2776 | I915_WRITE(DSPSURF(plane), |
2777 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2778 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2779 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2780 | } else |
f343c5f6 | 2781 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2782 | POSTING_READ(reg); |
17638cd6 JB |
2783 | } |
2784 | ||
29b9bde6 DV |
2785 | static void ironlake_update_primary_plane(struct drm_crtc *crtc, |
2786 | struct drm_framebuffer *fb, | |
2787 | int x, int y) | |
17638cd6 JB |
2788 | { |
2789 | struct drm_device *dev = crtc->dev; | |
2790 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2791 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
c9ba6fad | 2792 | struct drm_i915_gem_object *obj; |
17638cd6 | 2793 | int plane = intel_crtc->plane; |
e506a0c6 | 2794 | unsigned long linear_offset; |
17638cd6 | 2795 | u32 dspcntr; |
f45651ba | 2796 | u32 reg = DSPCNTR(plane); |
48404c1e | 2797 | int pixel_size; |
f45651ba | 2798 | |
fdd508a6 VS |
2799 | if (!intel_crtc->primary_enabled) { |
2800 | I915_WRITE(reg, 0); | |
2801 | I915_WRITE(DSPSURF(plane), 0); | |
2802 | POSTING_READ(reg); | |
2803 | return; | |
2804 | } | |
2805 | ||
c9ba6fad VS |
2806 | obj = intel_fb_obj(fb); |
2807 | if (WARN_ON(obj == NULL)) | |
2808 | return; | |
2809 | ||
2810 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2811 | ||
f45651ba VS |
2812 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2813 | ||
fdd508a6 | 2814 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2815 | |
2816 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2817 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2818 | |
57779d06 VS |
2819 | switch (fb->pixel_format) { |
2820 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2821 | dspcntr |= DISPPLANE_8BPP; |
2822 | break; | |
57779d06 VS |
2823 | case DRM_FORMAT_RGB565: |
2824 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2825 | break; |
57779d06 VS |
2826 | case DRM_FORMAT_XRGB8888: |
2827 | case DRM_FORMAT_ARGB8888: | |
2828 | dspcntr |= DISPPLANE_BGRX888; | |
2829 | break; | |
2830 | case DRM_FORMAT_XBGR8888: | |
2831 | case DRM_FORMAT_ABGR8888: | |
2832 | dspcntr |= DISPPLANE_RGBX888; | |
2833 | break; | |
2834 | case DRM_FORMAT_XRGB2101010: | |
2835 | case DRM_FORMAT_ARGB2101010: | |
2836 | dspcntr |= DISPPLANE_BGRX101010; | |
2837 | break; | |
2838 | case DRM_FORMAT_XBGR2101010: | |
2839 | case DRM_FORMAT_ABGR2101010: | |
2840 | dspcntr |= DISPPLANE_RGBX101010; | |
17638cd6 JB |
2841 | break; |
2842 | default: | |
baba133a | 2843 | BUG(); |
17638cd6 JB |
2844 | } |
2845 | ||
2846 | if (obj->tiling_mode != I915_TILING_NONE) | |
2847 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2848 | |
f45651ba | 2849 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2850 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2851 | |
b9897127 | 2852 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
c2c75131 | 2853 | intel_crtc->dspaddr_offset = |
bc752862 | 2854 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
b9897127 | 2855 | pixel_size, |
bc752862 | 2856 | fb->pitches[0]); |
c2c75131 | 2857 | linear_offset -= intel_crtc->dspaddr_offset; |
8e7d688b | 2858 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2859 | dspcntr |= DISPPLANE_ROTATE_180; |
2860 | ||
2861 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
6e3c9717 ACO |
2862 | x += (intel_crtc->config->pipe_src_w - 1); |
2863 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2864 | |
2865 | /* Finding the last pixel of the last line of the display | |
2866 | data and adding to linear_offset*/ | |
2867 | linear_offset += | |
6e3c9717 ACO |
2868 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2869 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2870 | } |
2871 | } | |
2872 | ||
2873 | I915_WRITE(reg, dspcntr); | |
17638cd6 | 2874 | |
01f2c773 | 2875 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2876 | I915_WRITE(DSPSURF(plane), |
2877 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2878 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2879 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2880 | } else { | |
2881 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2882 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2883 | } | |
17638cd6 | 2884 | POSTING_READ(reg); |
17638cd6 JB |
2885 | } |
2886 | ||
b321803d DL |
2887 | u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier, |
2888 | uint32_t pixel_format) | |
2889 | { | |
2890 | u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8; | |
2891 | ||
2892 | /* | |
2893 | * The stride is either expressed as a multiple of 64 bytes | |
2894 | * chunks for linear buffers or in number of tiles for tiled | |
2895 | * buffers. | |
2896 | */ | |
2897 | switch (fb_modifier) { | |
2898 | case DRM_FORMAT_MOD_NONE: | |
2899 | return 64; | |
2900 | case I915_FORMAT_MOD_X_TILED: | |
2901 | if (INTEL_INFO(dev)->gen == 2) | |
2902 | return 128; | |
2903 | return 512; | |
2904 | case I915_FORMAT_MOD_Y_TILED: | |
2905 | /* No need to check for old gens and Y tiling since this is | |
2906 | * about the display engine and those will be blocked before | |
2907 | * we get here. | |
2908 | */ | |
2909 | return 128; | |
2910 | case I915_FORMAT_MOD_Yf_TILED: | |
2911 | if (bits_per_pixel == 8) | |
2912 | return 64; | |
2913 | else | |
2914 | return 128; | |
2915 | default: | |
2916 | MISSING_CASE(fb_modifier); | |
2917 | return 64; | |
2918 | } | |
2919 | } | |
2920 | ||
121920fa TU |
2921 | unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane, |
2922 | struct drm_i915_gem_object *obj) | |
2923 | { | |
9abc4648 | 2924 | const struct i915_ggtt_view *view = &i915_ggtt_view_normal; |
121920fa TU |
2925 | |
2926 | if (intel_rotation_90_or_270(intel_plane->base.state->rotation)) | |
9abc4648 | 2927 | view = &i915_ggtt_view_rotated; |
121920fa TU |
2928 | |
2929 | return i915_gem_obj_ggtt_offset_view(obj, view); | |
2930 | } | |
2931 | ||
70d21f0e DL |
2932 | static void skylake_update_primary_plane(struct drm_crtc *crtc, |
2933 | struct drm_framebuffer *fb, | |
2934 | int x, int y) | |
2935 | { | |
2936 | struct drm_device *dev = crtc->dev; | |
2937 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2938 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
70d21f0e DL |
2939 | struct drm_i915_gem_object *obj; |
2940 | int pipe = intel_crtc->pipe; | |
3b7a5119 SJ |
2941 | u32 plane_ctl, stride_div, stride; |
2942 | u32 tile_height, plane_offset, plane_size; | |
2943 | unsigned int rotation; | |
2944 | int x_offset, y_offset; | |
121920fa | 2945 | unsigned long surf_addr; |
3b7a5119 | 2946 | struct drm_plane *plane; |
70d21f0e DL |
2947 | |
2948 | if (!intel_crtc->primary_enabled) { | |
2949 | I915_WRITE(PLANE_CTL(pipe, 0), 0); | |
2950 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
2951 | POSTING_READ(PLANE_CTL(pipe, 0)); | |
2952 | return; | |
2953 | } | |
2954 | ||
2955 | plane_ctl = PLANE_CTL_ENABLE | | |
2956 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
2957 | PLANE_CTL_PIPE_CSC_ENABLE; | |
2958 | ||
2959 | switch (fb->pixel_format) { | |
2960 | case DRM_FORMAT_RGB565: | |
2961 | plane_ctl |= PLANE_CTL_FORMAT_RGB_565; | |
2962 | break; | |
2963 | case DRM_FORMAT_XRGB8888: | |
2964 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; | |
2965 | break; | |
f75fb42a JN |
2966 | case DRM_FORMAT_ARGB8888: |
2967 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; | |
2968 | plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY; | |
2969 | break; | |
70d21f0e DL |
2970 | case DRM_FORMAT_XBGR8888: |
2971 | plane_ctl |= PLANE_CTL_ORDER_RGBX; | |
2972 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; | |
2973 | break; | |
f75fb42a JN |
2974 | case DRM_FORMAT_ABGR8888: |
2975 | plane_ctl |= PLANE_CTL_ORDER_RGBX; | |
2976 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; | |
2977 | plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY; | |
2978 | break; | |
70d21f0e DL |
2979 | case DRM_FORMAT_XRGB2101010: |
2980 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010; | |
2981 | break; | |
2982 | case DRM_FORMAT_XBGR2101010: | |
2983 | plane_ctl |= PLANE_CTL_ORDER_RGBX; | |
2984 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010; | |
2985 | break; | |
2986 | default: | |
2987 | BUG(); | |
2988 | } | |
2989 | ||
30af77c4 DV |
2990 | switch (fb->modifier[0]) { |
2991 | case DRM_FORMAT_MOD_NONE: | |
70d21f0e | 2992 | break; |
30af77c4 | 2993 | case I915_FORMAT_MOD_X_TILED: |
70d21f0e | 2994 | plane_ctl |= PLANE_CTL_TILED_X; |
b321803d DL |
2995 | break; |
2996 | case I915_FORMAT_MOD_Y_TILED: | |
2997 | plane_ctl |= PLANE_CTL_TILED_Y; | |
2998 | break; | |
2999 | case I915_FORMAT_MOD_Yf_TILED: | |
3000 | plane_ctl |= PLANE_CTL_TILED_YF; | |
70d21f0e DL |
3001 | break; |
3002 | default: | |
b321803d | 3003 | MISSING_CASE(fb->modifier[0]); |
70d21f0e DL |
3004 | } |
3005 | ||
3006 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
3b7a5119 SJ |
3007 | |
3008 | plane = crtc->primary; | |
3009 | rotation = plane->state->rotation; | |
3010 | switch (rotation) { | |
3011 | case BIT(DRM_ROTATE_90): | |
3012 | plane_ctl |= PLANE_CTL_ROTATE_90; | |
3013 | break; | |
3014 | ||
3015 | case BIT(DRM_ROTATE_180): | |
1447dde0 | 3016 | plane_ctl |= PLANE_CTL_ROTATE_180; |
3b7a5119 SJ |
3017 | break; |
3018 | ||
3019 | case BIT(DRM_ROTATE_270): | |
3020 | plane_ctl |= PLANE_CTL_ROTATE_270; | |
3021 | break; | |
3022 | } | |
70d21f0e | 3023 | |
b321803d DL |
3024 | obj = intel_fb_obj(fb); |
3025 | stride_div = intel_fb_stride_alignment(dev, fb->modifier[0], | |
3026 | fb->pixel_format); | |
3b7a5119 SJ |
3027 | surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj); |
3028 | ||
3029 | if (intel_rotation_90_or_270(rotation)) { | |
3030 | /* stride = Surface height in tiles */ | |
3031 | tile_height = intel_tile_height(dev, fb->bits_per_pixel, | |
3032 | fb->modifier[0]); | |
3033 | stride = DIV_ROUND_UP(fb->height, tile_height); | |
3034 | x_offset = stride * tile_height - y - (plane->state->src_h >> 16); | |
3035 | y_offset = x; | |
3036 | plane_size = ((plane->state->src_w >> 16) - 1) << 16 | | |
3037 | ((plane->state->src_h >> 16) - 1); | |
3038 | } else { | |
3039 | stride = fb->pitches[0] / stride_div; | |
3040 | x_offset = x; | |
3041 | y_offset = y; | |
3042 | plane_size = ((plane->state->src_h >> 16) - 1) << 16 | | |
3043 | ((plane->state->src_w >> 16) - 1); | |
3044 | } | |
3045 | plane_offset = y_offset << 16 | x_offset; | |
b321803d | 3046 | |
70d21f0e | 3047 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
70d21f0e | 3048 | I915_WRITE(PLANE_POS(pipe, 0), 0); |
3b7a5119 SJ |
3049 | I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); |
3050 | I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); | |
3051 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
121920fa | 3052 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
70d21f0e DL |
3053 | |
3054 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3055 | } | |
3056 | ||
17638cd6 JB |
3057 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3058 | static int | |
3059 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3060 | int x, int y, enum mode_set_atomic state) | |
3061 | { | |
3062 | struct drm_device *dev = crtc->dev; | |
3063 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 3064 | |
6b8e6ed0 CW |
3065 | if (dev_priv->display.disable_fbc) |
3066 | dev_priv->display.disable_fbc(dev); | |
81255565 | 3067 | |
29b9bde6 DV |
3068 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
3069 | ||
3070 | return 0; | |
81255565 JB |
3071 | } |
3072 | ||
7514747d | 3073 | static void intel_complete_page_flips(struct drm_device *dev) |
96a02917 | 3074 | { |
96a02917 VS |
3075 | struct drm_crtc *crtc; |
3076 | ||
70e1e0ec | 3077 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3078 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3079 | enum plane plane = intel_crtc->plane; | |
3080 | ||
3081 | intel_prepare_page_flip(dev, plane); | |
3082 | intel_finish_page_flip_plane(dev, plane); | |
3083 | } | |
7514747d VS |
3084 | } |
3085 | ||
3086 | static void intel_update_primary_planes(struct drm_device *dev) | |
3087 | { | |
3088 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3089 | struct drm_crtc *crtc; | |
96a02917 | 3090 | |
70e1e0ec | 3091 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3092 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3093 | ||
51fd371b | 3094 | drm_modeset_lock(&crtc->mutex, NULL); |
947fdaad CW |
3095 | /* |
3096 | * FIXME: Once we have proper support for primary planes (and | |
3097 | * disabling them without disabling the entire crtc) allow again | |
66e514c1 | 3098 | * a NULL crtc->primary->fb. |
947fdaad | 3099 | */ |
f4510a27 | 3100 | if (intel_crtc->active && crtc->primary->fb) |
262ca2b0 | 3101 | dev_priv->display.update_primary_plane(crtc, |
66e514c1 | 3102 | crtc->primary->fb, |
262ca2b0 MR |
3103 | crtc->x, |
3104 | crtc->y); | |
51fd371b | 3105 | drm_modeset_unlock(&crtc->mutex); |
96a02917 VS |
3106 | } |
3107 | } | |
3108 | ||
7514747d VS |
3109 | void intel_prepare_reset(struct drm_device *dev) |
3110 | { | |
f98ce92f VS |
3111 | struct drm_i915_private *dev_priv = to_i915(dev); |
3112 | struct intel_crtc *crtc; | |
3113 | ||
7514747d VS |
3114 | /* no reset support for gen2 */ |
3115 | if (IS_GEN2(dev)) | |
3116 | return; | |
3117 | ||
3118 | /* reset doesn't touch the display */ | |
3119 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
3120 | return; | |
3121 | ||
3122 | drm_modeset_lock_all(dev); | |
f98ce92f VS |
3123 | |
3124 | /* | |
3125 | * Disabling the crtcs gracefully seems nicer. Also the | |
3126 | * g33 docs say we should at least disable all the planes. | |
3127 | */ | |
3128 | for_each_intel_crtc(dev, crtc) { | |
3129 | if (crtc->active) | |
3130 | dev_priv->display.crtc_disable(&crtc->base); | |
3131 | } | |
7514747d VS |
3132 | } |
3133 | ||
3134 | void intel_finish_reset(struct drm_device *dev) | |
3135 | { | |
3136 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3137 | ||
3138 | /* | |
3139 | * Flips in the rings will be nuked by the reset, | |
3140 | * so complete all pending flips so that user space | |
3141 | * will get its events and not get stuck. | |
3142 | */ | |
3143 | intel_complete_page_flips(dev); | |
3144 | ||
3145 | /* no reset support for gen2 */ | |
3146 | if (IS_GEN2(dev)) | |
3147 | return; | |
3148 | ||
3149 | /* reset doesn't touch the display */ | |
3150 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { | |
3151 | /* | |
3152 | * Flips in the rings have been nuked by the reset, | |
3153 | * so update the base address of all primary | |
3154 | * planes to the the last fb to make sure we're | |
3155 | * showing the correct fb after a reset. | |
3156 | */ | |
3157 | intel_update_primary_planes(dev); | |
3158 | return; | |
3159 | } | |
3160 | ||
3161 | /* | |
3162 | * The display has been reset as well, | |
3163 | * so need a full re-initialization. | |
3164 | */ | |
3165 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3166 | intel_runtime_pm_enable_interrupts(dev_priv); | |
3167 | ||
3168 | intel_modeset_init_hw(dev); | |
3169 | ||
3170 | spin_lock_irq(&dev_priv->irq_lock); | |
3171 | if (dev_priv->display.hpd_irq_setup) | |
3172 | dev_priv->display.hpd_irq_setup(dev); | |
3173 | spin_unlock_irq(&dev_priv->irq_lock); | |
3174 | ||
3175 | intel_modeset_setup_hw_state(dev, true); | |
3176 | ||
3177 | intel_hpd_init(dev_priv); | |
3178 | ||
3179 | drm_modeset_unlock_all(dev); | |
3180 | } | |
3181 | ||
14667a4b CW |
3182 | static int |
3183 | intel_finish_fb(struct drm_framebuffer *old_fb) | |
3184 | { | |
2ff8fde1 | 3185 | struct drm_i915_gem_object *obj = intel_fb_obj(old_fb); |
14667a4b CW |
3186 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
3187 | bool was_interruptible = dev_priv->mm.interruptible; | |
3188 | int ret; | |
3189 | ||
14667a4b CW |
3190 | /* Big Hammer, we also need to ensure that any pending |
3191 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
3192 | * current scanout is retired before unpinning the old | |
3193 | * framebuffer. | |
3194 | * | |
3195 | * This should only fail upon a hung GPU, in which case we | |
3196 | * can safely continue. | |
3197 | */ | |
3198 | dev_priv->mm.interruptible = false; | |
3199 | ret = i915_gem_object_finish_gpu(obj); | |
3200 | dev_priv->mm.interruptible = was_interruptible; | |
3201 | ||
3202 | return ret; | |
3203 | } | |
3204 | ||
7d5e3799 CW |
3205 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3206 | { | |
3207 | struct drm_device *dev = crtc->dev; | |
3208 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3209 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7d5e3799 CW |
3210 | bool pending; |
3211 | ||
3212 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
3213 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
3214 | return false; | |
3215 | ||
5e2d7afc | 3216 | spin_lock_irq(&dev->event_lock); |
7d5e3799 | 3217 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
5e2d7afc | 3218 | spin_unlock_irq(&dev->event_lock); |
7d5e3799 CW |
3219 | |
3220 | return pending; | |
3221 | } | |
3222 | ||
e30e8f75 GP |
3223 | static void intel_update_pipe_size(struct intel_crtc *crtc) |
3224 | { | |
3225 | struct drm_device *dev = crtc->base.dev; | |
3226 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3227 | const struct drm_display_mode *adjusted_mode; | |
3228 | ||
3229 | if (!i915.fastboot) | |
3230 | return; | |
3231 | ||
3232 | /* | |
3233 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3234 | * that in compute_mode_changes we check the native mode (not the pfit | |
3235 | * mode) to see if we can flip rather than do a full mode set. In the | |
3236 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3237 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3238 | * sized surface. | |
3239 | * | |
3240 | * To fix this properly, we need to hoist the checks up into | |
3241 | * compute_mode_changes (or above), check the actual pfit state and | |
3242 | * whether the platform allows pfit disable with pipe active, and only | |
3243 | * then update the pipesrc and pfit state, even on the flip path. | |
3244 | */ | |
3245 | ||
6e3c9717 | 3246 | adjusted_mode = &crtc->config->base.adjusted_mode; |
e30e8f75 GP |
3247 | |
3248 | I915_WRITE(PIPESRC(crtc->pipe), | |
3249 | ((adjusted_mode->crtc_hdisplay - 1) << 16) | | |
3250 | (adjusted_mode->crtc_vdisplay - 1)); | |
6e3c9717 | 3251 | if (!crtc->config->pch_pfit.enabled && |
409ee761 ACO |
3252 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
3253 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
e30e8f75 GP |
3254 | I915_WRITE(PF_CTL(crtc->pipe), 0); |
3255 | I915_WRITE(PF_WIN_POS(crtc->pipe), 0); | |
3256 | I915_WRITE(PF_WIN_SZ(crtc->pipe), 0); | |
3257 | } | |
6e3c9717 ACO |
3258 | crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay; |
3259 | crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay; | |
e30e8f75 GP |
3260 | } |
3261 | ||
5e84e1a4 ZW |
3262 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3263 | { | |
3264 | struct drm_device *dev = crtc->dev; | |
3265 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3266 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3267 | int pipe = intel_crtc->pipe; | |
3268 | u32 reg, temp; | |
3269 | ||
3270 | /* enable normal train */ | |
3271 | reg = FDI_TX_CTL(pipe); | |
3272 | temp = I915_READ(reg); | |
61e499bf | 3273 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3274 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3275 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3276 | } else { |
3277 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3278 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3279 | } |
5e84e1a4 ZW |
3280 | I915_WRITE(reg, temp); |
3281 | ||
3282 | reg = FDI_RX_CTL(pipe); | |
3283 | temp = I915_READ(reg); | |
3284 | if (HAS_PCH_CPT(dev)) { | |
3285 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3286 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3287 | } else { | |
3288 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3289 | temp |= FDI_LINK_TRAIN_NONE; | |
3290 | } | |
3291 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3292 | ||
3293 | /* wait one idle pattern time */ | |
3294 | POSTING_READ(reg); | |
3295 | udelay(1000); | |
357555c0 JB |
3296 | |
3297 | /* IVB wants error correction enabled */ | |
3298 | if (IS_IVYBRIDGE(dev)) | |
3299 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3300 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3301 | } |
3302 | ||
8db9d77b ZW |
3303 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3304 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3305 | { | |
3306 | struct drm_device *dev = crtc->dev; | |
3307 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3308 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3309 | int pipe = intel_crtc->pipe; | |
5eddb70b | 3310 | u32 reg, temp, tries; |
8db9d77b | 3311 | |
1c8562f6 | 3312 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3313 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3314 | |
e1a44743 AJ |
3315 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3316 | for train result */ | |
5eddb70b CW |
3317 | reg = FDI_RX_IMR(pipe); |
3318 | temp = I915_READ(reg); | |
e1a44743 AJ |
3319 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3320 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3321 | I915_WRITE(reg, temp); |
3322 | I915_READ(reg); | |
e1a44743 AJ |
3323 | udelay(150); |
3324 | ||
8db9d77b | 3325 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3326 | reg = FDI_TX_CTL(pipe); |
3327 | temp = I915_READ(reg); | |
627eb5a3 | 3328 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3329 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3330 | temp &= ~FDI_LINK_TRAIN_NONE; |
3331 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3332 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3333 | |
5eddb70b CW |
3334 | reg = FDI_RX_CTL(pipe); |
3335 | temp = I915_READ(reg); | |
8db9d77b ZW |
3336 | temp &= ~FDI_LINK_TRAIN_NONE; |
3337 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3338 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3339 | ||
3340 | POSTING_READ(reg); | |
8db9d77b ZW |
3341 | udelay(150); |
3342 | ||
5b2adf89 | 3343 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3344 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3345 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3346 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3347 | |
5eddb70b | 3348 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3349 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3350 | temp = I915_READ(reg); |
8db9d77b ZW |
3351 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3352 | ||
3353 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3354 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3355 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3356 | break; |
3357 | } | |
8db9d77b | 3358 | } |
e1a44743 | 3359 | if (tries == 5) |
5eddb70b | 3360 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3361 | |
3362 | /* Train 2 */ | |
5eddb70b CW |
3363 | reg = FDI_TX_CTL(pipe); |
3364 | temp = I915_READ(reg); | |
8db9d77b ZW |
3365 | temp &= ~FDI_LINK_TRAIN_NONE; |
3366 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3367 | I915_WRITE(reg, temp); |
8db9d77b | 3368 | |
5eddb70b CW |
3369 | reg = FDI_RX_CTL(pipe); |
3370 | temp = I915_READ(reg); | |
8db9d77b ZW |
3371 | temp &= ~FDI_LINK_TRAIN_NONE; |
3372 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3373 | I915_WRITE(reg, temp); |
8db9d77b | 3374 | |
5eddb70b CW |
3375 | POSTING_READ(reg); |
3376 | udelay(150); | |
8db9d77b | 3377 | |
5eddb70b | 3378 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3379 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3380 | temp = I915_READ(reg); |
8db9d77b ZW |
3381 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3382 | ||
3383 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3384 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3385 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3386 | break; | |
3387 | } | |
8db9d77b | 3388 | } |
e1a44743 | 3389 | if (tries == 5) |
5eddb70b | 3390 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3391 | |
3392 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3393 | |
8db9d77b ZW |
3394 | } |
3395 | ||
0206e353 | 3396 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3397 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3398 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3399 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3400 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3401 | }; | |
3402 | ||
3403 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3404 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3405 | { | |
3406 | struct drm_device *dev = crtc->dev; | |
3407 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3408 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3409 | int pipe = intel_crtc->pipe; | |
fa37d39e | 3410 | u32 reg, temp, i, retry; |
8db9d77b | 3411 | |
e1a44743 AJ |
3412 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3413 | for train result */ | |
5eddb70b CW |
3414 | reg = FDI_RX_IMR(pipe); |
3415 | temp = I915_READ(reg); | |
e1a44743 AJ |
3416 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3417 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3418 | I915_WRITE(reg, temp); |
3419 | ||
3420 | POSTING_READ(reg); | |
e1a44743 AJ |
3421 | udelay(150); |
3422 | ||
8db9d77b | 3423 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3424 | reg = FDI_TX_CTL(pipe); |
3425 | temp = I915_READ(reg); | |
627eb5a3 | 3426 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3427 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3428 | temp &= ~FDI_LINK_TRAIN_NONE; |
3429 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3430 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3431 | /* SNB-B */ | |
3432 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3433 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3434 | |
d74cf324 DV |
3435 | I915_WRITE(FDI_RX_MISC(pipe), |
3436 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3437 | ||
5eddb70b CW |
3438 | reg = FDI_RX_CTL(pipe); |
3439 | temp = I915_READ(reg); | |
8db9d77b ZW |
3440 | if (HAS_PCH_CPT(dev)) { |
3441 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3442 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3443 | } else { | |
3444 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3445 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3446 | } | |
5eddb70b CW |
3447 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3448 | ||
3449 | POSTING_READ(reg); | |
8db9d77b ZW |
3450 | udelay(150); |
3451 | ||
0206e353 | 3452 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3453 | reg = FDI_TX_CTL(pipe); |
3454 | temp = I915_READ(reg); | |
8db9d77b ZW |
3455 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3456 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3457 | I915_WRITE(reg, temp); |
3458 | ||
3459 | POSTING_READ(reg); | |
8db9d77b ZW |
3460 | udelay(500); |
3461 | ||
fa37d39e SP |
3462 | for (retry = 0; retry < 5; retry++) { |
3463 | reg = FDI_RX_IIR(pipe); | |
3464 | temp = I915_READ(reg); | |
3465 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3466 | if (temp & FDI_RX_BIT_LOCK) { | |
3467 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3468 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3469 | break; | |
3470 | } | |
3471 | udelay(50); | |
8db9d77b | 3472 | } |
fa37d39e SP |
3473 | if (retry < 5) |
3474 | break; | |
8db9d77b ZW |
3475 | } |
3476 | if (i == 4) | |
5eddb70b | 3477 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3478 | |
3479 | /* Train 2 */ | |
5eddb70b CW |
3480 | reg = FDI_TX_CTL(pipe); |
3481 | temp = I915_READ(reg); | |
8db9d77b ZW |
3482 | temp &= ~FDI_LINK_TRAIN_NONE; |
3483 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3484 | if (IS_GEN6(dev)) { | |
3485 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3486 | /* SNB-B */ | |
3487 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3488 | } | |
5eddb70b | 3489 | I915_WRITE(reg, temp); |
8db9d77b | 3490 | |
5eddb70b CW |
3491 | reg = FDI_RX_CTL(pipe); |
3492 | temp = I915_READ(reg); | |
8db9d77b ZW |
3493 | if (HAS_PCH_CPT(dev)) { |
3494 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3495 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3496 | } else { | |
3497 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3498 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3499 | } | |
5eddb70b CW |
3500 | I915_WRITE(reg, temp); |
3501 | ||
3502 | POSTING_READ(reg); | |
8db9d77b ZW |
3503 | udelay(150); |
3504 | ||
0206e353 | 3505 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3506 | reg = FDI_TX_CTL(pipe); |
3507 | temp = I915_READ(reg); | |
8db9d77b ZW |
3508 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3509 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3510 | I915_WRITE(reg, temp); |
3511 | ||
3512 | POSTING_READ(reg); | |
8db9d77b ZW |
3513 | udelay(500); |
3514 | ||
fa37d39e SP |
3515 | for (retry = 0; retry < 5; retry++) { |
3516 | reg = FDI_RX_IIR(pipe); | |
3517 | temp = I915_READ(reg); | |
3518 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3519 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3520 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3521 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3522 | break; | |
3523 | } | |
3524 | udelay(50); | |
8db9d77b | 3525 | } |
fa37d39e SP |
3526 | if (retry < 5) |
3527 | break; | |
8db9d77b ZW |
3528 | } |
3529 | if (i == 4) | |
5eddb70b | 3530 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3531 | |
3532 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3533 | } | |
3534 | ||
357555c0 JB |
3535 | /* Manual link training for Ivy Bridge A0 parts */ |
3536 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3537 | { | |
3538 | struct drm_device *dev = crtc->dev; | |
3539 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3540 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3541 | int pipe = intel_crtc->pipe; | |
139ccd3f | 3542 | u32 reg, temp, i, j; |
357555c0 JB |
3543 | |
3544 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3545 | for train result */ | |
3546 | reg = FDI_RX_IMR(pipe); | |
3547 | temp = I915_READ(reg); | |
3548 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3549 | temp &= ~FDI_RX_BIT_LOCK; | |
3550 | I915_WRITE(reg, temp); | |
3551 | ||
3552 | POSTING_READ(reg); | |
3553 | udelay(150); | |
3554 | ||
01a415fd DV |
3555 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3556 | I915_READ(FDI_RX_IIR(pipe))); | |
3557 | ||
139ccd3f JB |
3558 | /* Try each vswing and preemphasis setting twice before moving on */ |
3559 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3560 | /* disable first in case we need to retry */ | |
3561 | reg = FDI_TX_CTL(pipe); | |
3562 | temp = I915_READ(reg); | |
3563 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3564 | temp &= ~FDI_TX_ENABLE; | |
3565 | I915_WRITE(reg, temp); | |
357555c0 | 3566 | |
139ccd3f JB |
3567 | reg = FDI_RX_CTL(pipe); |
3568 | temp = I915_READ(reg); | |
3569 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3570 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3571 | temp &= ~FDI_RX_ENABLE; | |
3572 | I915_WRITE(reg, temp); | |
357555c0 | 3573 | |
139ccd3f | 3574 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3575 | reg = FDI_TX_CTL(pipe); |
3576 | temp = I915_READ(reg); | |
139ccd3f | 3577 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3578 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 3579 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3580 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3581 | temp |= snb_b_fdi_train_param[j/2]; |
3582 | temp |= FDI_COMPOSITE_SYNC; | |
3583 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3584 | |
139ccd3f JB |
3585 | I915_WRITE(FDI_RX_MISC(pipe), |
3586 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3587 | |
139ccd3f | 3588 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3589 | temp = I915_READ(reg); |
139ccd3f JB |
3590 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3591 | temp |= FDI_COMPOSITE_SYNC; | |
3592 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3593 | |
139ccd3f JB |
3594 | POSTING_READ(reg); |
3595 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3596 | |
139ccd3f JB |
3597 | for (i = 0; i < 4; i++) { |
3598 | reg = FDI_RX_IIR(pipe); | |
3599 | temp = I915_READ(reg); | |
3600 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3601 | |
139ccd3f JB |
3602 | if (temp & FDI_RX_BIT_LOCK || |
3603 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3604 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3605 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3606 | i); | |
3607 | break; | |
3608 | } | |
3609 | udelay(1); /* should be 0.5us */ | |
3610 | } | |
3611 | if (i == 4) { | |
3612 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3613 | continue; | |
3614 | } | |
357555c0 | 3615 | |
139ccd3f | 3616 | /* Train 2 */ |
357555c0 JB |
3617 | reg = FDI_TX_CTL(pipe); |
3618 | temp = I915_READ(reg); | |
139ccd3f JB |
3619 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3620 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3621 | I915_WRITE(reg, temp); | |
3622 | ||
3623 | reg = FDI_RX_CTL(pipe); | |
3624 | temp = I915_READ(reg); | |
3625 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3626 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3627 | I915_WRITE(reg, temp); |
3628 | ||
3629 | POSTING_READ(reg); | |
139ccd3f | 3630 | udelay(2); /* should be 1.5us */ |
357555c0 | 3631 | |
139ccd3f JB |
3632 | for (i = 0; i < 4; i++) { |
3633 | reg = FDI_RX_IIR(pipe); | |
3634 | temp = I915_READ(reg); | |
3635 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3636 | |
139ccd3f JB |
3637 | if (temp & FDI_RX_SYMBOL_LOCK || |
3638 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3639 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3640 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3641 | i); | |
3642 | goto train_done; | |
3643 | } | |
3644 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3645 | } |
139ccd3f JB |
3646 | if (i == 4) |
3647 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3648 | } |
357555c0 | 3649 | |
139ccd3f | 3650 | train_done: |
357555c0 JB |
3651 | DRM_DEBUG_KMS("FDI train done.\n"); |
3652 | } | |
3653 | ||
88cefb6c | 3654 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3655 | { |
88cefb6c | 3656 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3657 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3658 | int pipe = intel_crtc->pipe; |
5eddb70b | 3659 | u32 reg, temp; |
79e53945 | 3660 | |
c64e311e | 3661 | |
c98e9dcf | 3662 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3663 | reg = FDI_RX_CTL(pipe); |
3664 | temp = I915_READ(reg); | |
627eb5a3 | 3665 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3666 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3667 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3668 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3669 | ||
3670 | POSTING_READ(reg); | |
c98e9dcf JB |
3671 | udelay(200); |
3672 | ||
3673 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3674 | temp = I915_READ(reg); |
3675 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3676 | ||
3677 | POSTING_READ(reg); | |
c98e9dcf JB |
3678 | udelay(200); |
3679 | ||
20749730 PZ |
3680 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3681 | reg = FDI_TX_CTL(pipe); | |
3682 | temp = I915_READ(reg); | |
3683 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3684 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3685 | |
20749730 PZ |
3686 | POSTING_READ(reg); |
3687 | udelay(100); | |
6be4a607 | 3688 | } |
0e23b99d JB |
3689 | } |
3690 | ||
88cefb6c DV |
3691 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3692 | { | |
3693 | struct drm_device *dev = intel_crtc->base.dev; | |
3694 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3695 | int pipe = intel_crtc->pipe; | |
3696 | u32 reg, temp; | |
3697 | ||
3698 | /* Switch from PCDclk to Rawclk */ | |
3699 | reg = FDI_RX_CTL(pipe); | |
3700 | temp = I915_READ(reg); | |
3701 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3702 | ||
3703 | /* Disable CPU FDI TX PLL */ | |
3704 | reg = FDI_TX_CTL(pipe); | |
3705 | temp = I915_READ(reg); | |
3706 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3707 | ||
3708 | POSTING_READ(reg); | |
3709 | udelay(100); | |
3710 | ||
3711 | reg = FDI_RX_CTL(pipe); | |
3712 | temp = I915_READ(reg); | |
3713 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3714 | ||
3715 | /* Wait for the clocks to turn off. */ | |
3716 | POSTING_READ(reg); | |
3717 | udelay(100); | |
3718 | } | |
3719 | ||
0fc932b8 JB |
3720 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3721 | { | |
3722 | struct drm_device *dev = crtc->dev; | |
3723 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3724 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3725 | int pipe = intel_crtc->pipe; | |
3726 | u32 reg, temp; | |
3727 | ||
3728 | /* disable CPU FDI tx and PCH FDI rx */ | |
3729 | reg = FDI_TX_CTL(pipe); | |
3730 | temp = I915_READ(reg); | |
3731 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3732 | POSTING_READ(reg); | |
3733 | ||
3734 | reg = FDI_RX_CTL(pipe); | |
3735 | temp = I915_READ(reg); | |
3736 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3737 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3738 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3739 | ||
3740 | POSTING_READ(reg); | |
3741 | udelay(100); | |
3742 | ||
3743 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3744 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3745 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3746 | |
3747 | /* still set train pattern 1 */ | |
3748 | reg = FDI_TX_CTL(pipe); | |
3749 | temp = I915_READ(reg); | |
3750 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3751 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3752 | I915_WRITE(reg, temp); | |
3753 | ||
3754 | reg = FDI_RX_CTL(pipe); | |
3755 | temp = I915_READ(reg); | |
3756 | if (HAS_PCH_CPT(dev)) { | |
3757 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3758 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3759 | } else { | |
3760 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3761 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3762 | } | |
3763 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3764 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3765 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3766 | I915_WRITE(reg, temp); |
3767 | ||
3768 | POSTING_READ(reg); | |
3769 | udelay(100); | |
3770 | } | |
3771 | ||
5dce5b93 CW |
3772 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3773 | { | |
3774 | struct intel_crtc *crtc; | |
3775 | ||
3776 | /* Note that we don't need to be called with mode_config.lock here | |
3777 | * as our list of CRTC objects is static for the lifetime of the | |
3778 | * device and so cannot disappear as we iterate. Similarly, we can | |
3779 | * happily treat the predicates as racy, atomic checks as userspace | |
3780 | * cannot claim and pin a new fb without at least acquring the | |
3781 | * struct_mutex and so serialising with us. | |
3782 | */ | |
d3fcc808 | 3783 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3784 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3785 | continue; | |
3786 | ||
3787 | if (crtc->unpin_work) | |
3788 | intel_wait_for_vblank(dev, crtc->pipe); | |
3789 | ||
3790 | return true; | |
3791 | } | |
3792 | ||
3793 | return false; | |
3794 | } | |
3795 | ||
d6bbafa1 CW |
3796 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
3797 | { | |
3798 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
3799 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
3800 | ||
3801 | /* ensure that the unpin work is consistent wrt ->pending. */ | |
3802 | smp_rmb(); | |
3803 | intel_crtc->unpin_work = NULL; | |
3804 | ||
3805 | if (work->event) | |
3806 | drm_send_vblank_event(intel_crtc->base.dev, | |
3807 | intel_crtc->pipe, | |
3808 | work->event); | |
3809 | ||
3810 | drm_crtc_vblank_put(&intel_crtc->base); | |
3811 | ||
3812 | wake_up_all(&dev_priv->pending_flip_queue); | |
3813 | queue_work(dev_priv->wq, &work->work); | |
3814 | ||
3815 | trace_i915_flip_complete(intel_crtc->plane, | |
3816 | work->pending_flip_obj); | |
3817 | } | |
3818 | ||
46a55d30 | 3819 | void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3820 | { |
0f91128d | 3821 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3822 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 | 3823 | |
2c10d571 | 3824 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
9c787942 CW |
3825 | if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue, |
3826 | !intel_crtc_has_pending_flip(crtc), | |
3827 | 60*HZ) == 0)) { | |
3828 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2c10d571 | 3829 | |
5e2d7afc | 3830 | spin_lock_irq(&dev->event_lock); |
9c787942 CW |
3831 | if (intel_crtc->unpin_work) { |
3832 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
3833 | page_flip_completed(intel_crtc); | |
3834 | } | |
5e2d7afc | 3835 | spin_unlock_irq(&dev->event_lock); |
9c787942 | 3836 | } |
5bb61643 | 3837 | |
975d568a CW |
3838 | if (crtc->primary->fb) { |
3839 | mutex_lock(&dev->struct_mutex); | |
3840 | intel_finish_fb(crtc->primary->fb); | |
3841 | mutex_unlock(&dev->struct_mutex); | |
3842 | } | |
e6c3a2a6 CW |
3843 | } |
3844 | ||
e615efe4 ED |
3845 | /* Program iCLKIP clock to the desired frequency */ |
3846 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3847 | { | |
3848 | struct drm_device *dev = crtc->dev; | |
3849 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 3850 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
3851 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3852 | u32 temp; | |
3853 | ||
09153000 DV |
3854 | mutex_lock(&dev_priv->dpio_lock); |
3855 | ||
e615efe4 ED |
3856 | /* It is necessary to ungate the pixclk gate prior to programming |
3857 | * the divisors, and gate it back when it is done. | |
3858 | */ | |
3859 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3860 | ||
3861 | /* Disable SSCCTL */ | |
3862 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
3863 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
3864 | SBI_SSCCTL_DISABLE, | |
3865 | SBI_ICLK); | |
e615efe4 ED |
3866 | |
3867 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3868 | if (clock == 20000) { |
e615efe4 ED |
3869 | auxdiv = 1; |
3870 | divsel = 0x41; | |
3871 | phaseinc = 0x20; | |
3872 | } else { | |
3873 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3874 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3875 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3876 | * convert the virtual clock precision to KHz here for higher |
3877 | * precision. | |
3878 | */ | |
3879 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3880 | u32 iclk_pi_range = 64; | |
3881 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3882 | ||
12d7ceed | 3883 | desired_divisor = (iclk_virtual_root_freq / clock); |
e615efe4 ED |
3884 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3885 | pi_value = desired_divisor % iclk_pi_range; | |
3886 | ||
3887 | auxdiv = 0; | |
3888 | divsel = msb_divisor_value - 2; | |
3889 | phaseinc = pi_value; | |
3890 | } | |
3891 | ||
3892 | /* This should not happen with any sane values */ | |
3893 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3894 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3895 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3896 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3897 | ||
3898 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3899 | clock, |
e615efe4 ED |
3900 | auxdiv, |
3901 | divsel, | |
3902 | phasedir, | |
3903 | phaseinc); | |
3904 | ||
3905 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 3906 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3907 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3908 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3909 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3910 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3911 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3912 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3913 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3914 | |
3915 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3916 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3917 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3918 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3919 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3920 | |
3921 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3922 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3923 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3924 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
3925 | |
3926 | /* Wait for initialization time */ | |
3927 | udelay(24); | |
3928 | ||
3929 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 DV |
3930 | |
3931 | mutex_unlock(&dev_priv->dpio_lock); | |
e615efe4 ED |
3932 | } |
3933 | ||
275f01b2 DV |
3934 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
3935 | enum pipe pch_transcoder) | |
3936 | { | |
3937 | struct drm_device *dev = crtc->base.dev; | |
3938 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 3939 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
3940 | |
3941 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
3942 | I915_READ(HTOTAL(cpu_transcoder))); | |
3943 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
3944 | I915_READ(HBLANK(cpu_transcoder))); | |
3945 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
3946 | I915_READ(HSYNC(cpu_transcoder))); | |
3947 | ||
3948 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
3949 | I915_READ(VTOTAL(cpu_transcoder))); | |
3950 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
3951 | I915_READ(VBLANK(cpu_transcoder))); | |
3952 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
3953 | I915_READ(VSYNC(cpu_transcoder))); | |
3954 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
3955 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
3956 | } | |
3957 | ||
003632d9 | 3958 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 DV |
3959 | { |
3960 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3961 | uint32_t temp; | |
3962 | ||
3963 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 3964 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
3965 | return; |
3966 | ||
3967 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
3968 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
3969 | ||
003632d9 ACO |
3970 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
3971 | if (enable) | |
3972 | temp |= FDI_BC_BIFURCATION_SELECT; | |
3973 | ||
3974 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
3975 | I915_WRITE(SOUTH_CHICKEN1, temp); |
3976 | POSTING_READ(SOUTH_CHICKEN1); | |
3977 | } | |
3978 | ||
3979 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
3980 | { | |
3981 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
3982 | |
3983 | switch (intel_crtc->pipe) { | |
3984 | case PIPE_A: | |
3985 | break; | |
3986 | case PIPE_B: | |
6e3c9717 | 3987 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 3988 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 3989 | else |
003632d9 | 3990 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
3991 | |
3992 | break; | |
3993 | case PIPE_C: | |
003632d9 | 3994 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
3995 | |
3996 | break; | |
3997 | default: | |
3998 | BUG(); | |
3999 | } | |
4000 | } | |
4001 | ||
f67a559d JB |
4002 | /* |
4003 | * Enable PCH resources required for PCH ports: | |
4004 | * - PCH PLLs | |
4005 | * - FDI training & RX/TX | |
4006 | * - update transcoder timings | |
4007 | * - DP transcoding bits | |
4008 | * - transcoder | |
4009 | */ | |
4010 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4011 | { |
4012 | struct drm_device *dev = crtc->dev; | |
4013 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4014 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4015 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 4016 | u32 reg, temp; |
2c07245f | 4017 | |
ab9412ba | 4018 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4019 | |
1fbc0d78 DV |
4020 | if (IS_IVYBRIDGE(dev)) |
4021 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
4022 | ||
cd986abb DV |
4023 | /* Write the TU size bits before fdi link training, so that error |
4024 | * detection works. */ | |
4025 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4026 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4027 | ||
c98e9dcf | 4028 | /* For PCH output, training FDI link */ |
674cf967 | 4029 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4030 | |
3ad8a208 DV |
4031 | /* We need to program the right clock selection before writing the pixel |
4032 | * mutliplier into the DPLL. */ | |
303b81e0 | 4033 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 4034 | u32 sel; |
4b645f14 | 4035 | |
c98e9dcf | 4036 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4037 | temp |= TRANS_DPLL_ENABLE(pipe); |
4038 | sel = TRANS_DPLLB_SEL(pipe); | |
6e3c9717 | 4039 | if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
4040 | temp |= sel; |
4041 | else | |
4042 | temp &= ~sel; | |
c98e9dcf | 4043 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4044 | } |
5eddb70b | 4045 | |
3ad8a208 DV |
4046 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4047 | * transcoder, and we actually should do this to not upset any PCH | |
4048 | * transcoder that already use the clock when we share it. | |
4049 | * | |
4050 | * Note that enable_shared_dpll tries to do the right thing, but | |
4051 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4052 | * the right LVDS enable sequence. */ | |
85b3894f | 4053 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4054 | |
d9b6cb56 JB |
4055 | /* set transcoder timing, panel must allow it */ |
4056 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4057 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4058 | |
303b81e0 | 4059 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4060 | |
c98e9dcf | 4061 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e3c9717 | 4062 | if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { |
dfd07d72 | 4063 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
4064 | reg = TRANS_DP_CTL(pipe); |
4065 | temp = I915_READ(reg); | |
4066 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4067 | TRANS_DP_SYNC_MASK | |
4068 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
4069 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
4070 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 4071 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
4072 | |
4073 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 4074 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 4075 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4076 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4077 | |
4078 | switch (intel_trans_dp_port_sel(crtc)) { | |
4079 | case PCH_DP_B: | |
5eddb70b | 4080 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
4081 | break; |
4082 | case PCH_DP_C: | |
5eddb70b | 4083 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
4084 | break; |
4085 | case PCH_DP_D: | |
5eddb70b | 4086 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4087 | break; |
4088 | default: | |
e95d41e1 | 4089 | BUG(); |
32f9d658 | 4090 | } |
2c07245f | 4091 | |
5eddb70b | 4092 | I915_WRITE(reg, temp); |
6be4a607 | 4093 | } |
b52eb4dc | 4094 | |
b8a4f404 | 4095 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4096 | } |
4097 | ||
1507e5bd PZ |
4098 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4099 | { | |
4100 | struct drm_device *dev = crtc->dev; | |
4101 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4102 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6e3c9717 | 4103 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4104 | |
ab9412ba | 4105 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4106 | |
8c52b5e8 | 4107 | lpt_program_iclkip(crtc); |
1507e5bd | 4108 | |
0540e488 | 4109 | /* Set transcoder timing. */ |
275f01b2 | 4110 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4111 | |
937bb610 | 4112 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4113 | } |
4114 | ||
716c2e55 | 4115 | void intel_put_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 4116 | { |
e2b78267 | 4117 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
ee7b9f93 JB |
4118 | |
4119 | if (pll == NULL) | |
4120 | return; | |
4121 | ||
3e369b76 | 4122 | if (!(pll->config.crtc_mask & (1 << crtc->pipe))) { |
1e6f2ddc | 4123 | WARN(1, "bad %s crtc mask\n", pll->name); |
ee7b9f93 JB |
4124 | return; |
4125 | } | |
4126 | ||
3e369b76 ACO |
4127 | pll->config.crtc_mask &= ~(1 << crtc->pipe); |
4128 | if (pll->config.crtc_mask == 0) { | |
f4a091c7 DV |
4129 | WARN_ON(pll->on); |
4130 | WARN_ON(pll->active); | |
4131 | } | |
4132 | ||
6e3c9717 | 4133 | crtc->config->shared_dpll = DPLL_ID_PRIVATE; |
ee7b9f93 JB |
4134 | } |
4135 | ||
190f68c5 ACO |
4136 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, |
4137 | struct intel_crtc_state *crtc_state) | |
ee7b9f93 | 4138 | { |
e2b78267 | 4139 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
8bd31e67 | 4140 | struct intel_shared_dpll *pll; |
e2b78267 | 4141 | enum intel_dpll_id i; |
ee7b9f93 | 4142 | |
98b6bd99 DV |
4143 | if (HAS_PCH_IBX(dev_priv->dev)) { |
4144 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 4145 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 4146 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 4147 | |
46edb027 DV |
4148 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
4149 | crtc->base.base.id, pll->name); | |
98b6bd99 | 4150 | |
8bd31e67 | 4151 | WARN_ON(pll->new_config->crtc_mask); |
f2a69f44 | 4152 | |
98b6bd99 DV |
4153 | goto found; |
4154 | } | |
4155 | ||
e72f9fbf DV |
4156 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4157 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 JB |
4158 | |
4159 | /* Only want to check enabled timings first */ | |
8bd31e67 | 4160 | if (pll->new_config->crtc_mask == 0) |
ee7b9f93 JB |
4161 | continue; |
4162 | ||
190f68c5 | 4163 | if (memcmp(&crtc_state->dpll_hw_state, |
8bd31e67 ACO |
4164 | &pll->new_config->hw_state, |
4165 | sizeof(pll->new_config->hw_state)) == 0) { | |
4166 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n", | |
1e6f2ddc | 4167 | crtc->base.base.id, pll->name, |
8bd31e67 ACO |
4168 | pll->new_config->crtc_mask, |
4169 | pll->active); | |
ee7b9f93 JB |
4170 | goto found; |
4171 | } | |
4172 | } | |
4173 | ||
4174 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
4175 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4176 | pll = &dev_priv->shared_dplls[i]; | |
8bd31e67 | 4177 | if (pll->new_config->crtc_mask == 0) { |
46edb027 DV |
4178 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
4179 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
4180 | goto found; |
4181 | } | |
4182 | } | |
4183 | ||
4184 | return NULL; | |
4185 | ||
4186 | found: | |
8bd31e67 | 4187 | if (pll->new_config->crtc_mask == 0) |
190f68c5 | 4188 | pll->new_config->hw_state = crtc_state->dpll_hw_state; |
f2a69f44 | 4189 | |
190f68c5 | 4190 | crtc_state->shared_dpll = i; |
46edb027 DV |
4191 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
4192 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 4193 | |
8bd31e67 | 4194 | pll->new_config->crtc_mask |= 1 << crtc->pipe; |
e04c7350 | 4195 | |
ee7b9f93 JB |
4196 | return pll; |
4197 | } | |
4198 | ||
8bd31e67 ACO |
4199 | /** |
4200 | * intel_shared_dpll_start_config - start a new PLL staged config | |
4201 | * @dev_priv: DRM device | |
4202 | * @clear_pipes: mask of pipes that will have their PLLs freed | |
4203 | * | |
4204 | * Starts a new PLL staged config, copying the current config but | |
4205 | * releasing the references of pipes specified in clear_pipes. | |
4206 | */ | |
4207 | static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv, | |
4208 | unsigned clear_pipes) | |
4209 | { | |
4210 | struct intel_shared_dpll *pll; | |
4211 | enum intel_dpll_id i; | |
4212 | ||
4213 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
4214 | pll = &dev_priv->shared_dplls[i]; | |
4215 | ||
4216 | pll->new_config = kmemdup(&pll->config, sizeof pll->config, | |
4217 | GFP_KERNEL); | |
4218 | if (!pll->new_config) | |
4219 | goto cleanup; | |
4220 | ||
4221 | pll->new_config->crtc_mask &= ~clear_pipes; | |
4222 | } | |
4223 | ||
4224 | return 0; | |
4225 | ||
4226 | cleanup: | |
4227 | while (--i >= 0) { | |
4228 | pll = &dev_priv->shared_dplls[i]; | |
f354d733 | 4229 | kfree(pll->new_config); |
8bd31e67 ACO |
4230 | pll->new_config = NULL; |
4231 | } | |
4232 | ||
4233 | return -ENOMEM; | |
4234 | } | |
4235 | ||
4236 | static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv) | |
4237 | { | |
4238 | struct intel_shared_dpll *pll; | |
4239 | enum intel_dpll_id i; | |
4240 | ||
4241 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
4242 | pll = &dev_priv->shared_dplls[i]; | |
4243 | ||
4244 | WARN_ON(pll->new_config == &pll->config); | |
4245 | ||
4246 | pll->config = *pll->new_config; | |
4247 | kfree(pll->new_config); | |
4248 | pll->new_config = NULL; | |
4249 | } | |
4250 | } | |
4251 | ||
4252 | static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv) | |
4253 | { | |
4254 | struct intel_shared_dpll *pll; | |
4255 | enum intel_dpll_id i; | |
4256 | ||
4257 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
4258 | pll = &dev_priv->shared_dplls[i]; | |
4259 | ||
4260 | WARN_ON(pll->new_config == &pll->config); | |
4261 | ||
4262 | kfree(pll->new_config); | |
4263 | pll->new_config = NULL; | |
4264 | } | |
4265 | } | |
4266 | ||
a1520318 | 4267 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
4268 | { |
4269 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 4270 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4271 | u32 temp; |
4272 | ||
4273 | temp = I915_READ(dslreg); | |
4274 | udelay(500); | |
4275 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4276 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4277 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4278 | } |
4279 | } | |
4280 | ||
bd2e244f JB |
4281 | static void skylake_pfit_enable(struct intel_crtc *crtc) |
4282 | { | |
4283 | struct drm_device *dev = crtc->base.dev; | |
4284 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4285 | int pipe = crtc->pipe; | |
4286 | ||
6e3c9717 | 4287 | if (crtc->config->pch_pfit.enabled) { |
bd2e244f | 4288 | I915_WRITE(PS_CTL(pipe), PS_ENABLE); |
6e3c9717 ACO |
4289 | I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4290 | I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
bd2e244f JB |
4291 | } |
4292 | } | |
4293 | ||
b074cec8 JB |
4294 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4295 | { | |
4296 | struct drm_device *dev = crtc->base.dev; | |
4297 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4298 | int pipe = crtc->pipe; | |
4299 | ||
6e3c9717 | 4300 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4301 | /* Force use of hard-coded filter coefficients |
4302 | * as some pre-programmed values are broken, | |
4303 | * e.g. x201. | |
4304 | */ | |
4305 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4306 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4307 | PF_PIPE_SEL_IVB(pipe)); | |
4308 | else | |
4309 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4310 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4311 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4312 | } |
4313 | } | |
4314 | ||
4a3b8769 | 4315 | static void intel_enable_sprite_planes(struct drm_crtc *crtc) |
bb53d4ae VS |
4316 | { |
4317 | struct drm_device *dev = crtc->dev; | |
4318 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 4319 | struct drm_plane *plane; |
bb53d4ae VS |
4320 | struct intel_plane *intel_plane; |
4321 | ||
af2b653b MR |
4322 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
4323 | intel_plane = to_intel_plane(plane); | |
bb53d4ae VS |
4324 | if (intel_plane->pipe == pipe) |
4325 | intel_plane_restore(&intel_plane->base); | |
af2b653b | 4326 | } |
bb53d4ae VS |
4327 | } |
4328 | ||
0d703d4e MR |
4329 | /* |
4330 | * Disable a plane internally without actually modifying the plane's state. | |
4331 | * This will allow us to easily restore the plane later by just reprogramming | |
4332 | * its state. | |
4333 | */ | |
4334 | static void disable_plane_internal(struct drm_plane *plane) | |
4335 | { | |
4336 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
4337 | struct drm_plane_state *state = | |
4338 | plane->funcs->atomic_duplicate_state(plane); | |
4339 | struct intel_plane_state *intel_state = to_intel_plane_state(state); | |
4340 | ||
4341 | intel_state->visible = false; | |
4342 | intel_plane->commit_plane(plane, intel_state); | |
4343 | ||
4344 | intel_plane_destroy_state(plane, state); | |
4345 | } | |
4346 | ||
4a3b8769 | 4347 | static void intel_disable_sprite_planes(struct drm_crtc *crtc) |
bb53d4ae VS |
4348 | { |
4349 | struct drm_device *dev = crtc->dev; | |
4350 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 4351 | struct drm_plane *plane; |
bb53d4ae VS |
4352 | struct intel_plane *intel_plane; |
4353 | ||
af2b653b MR |
4354 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
4355 | intel_plane = to_intel_plane(plane); | |
0d703d4e MR |
4356 | if (plane->fb && intel_plane->pipe == pipe) |
4357 | disable_plane_internal(plane); | |
af2b653b | 4358 | } |
bb53d4ae VS |
4359 | } |
4360 | ||
20bc8673 | 4361 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4362 | { |
cea165c3 VS |
4363 | struct drm_device *dev = crtc->base.dev; |
4364 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 | 4365 | |
6e3c9717 | 4366 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4367 | return; |
4368 | ||
cea165c3 VS |
4369 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
4370 | intel_wait_for_vblank(dev, crtc->pipe); | |
4371 | ||
d77e4531 | 4372 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4373 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4374 | mutex_lock(&dev_priv->rps.hw_lock); |
4375 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4376 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4377 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4378 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4379 | * mailbox." Moreover, the mailbox may return a bogus state, |
4380 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4381 | */ |
4382 | } else { | |
4383 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4384 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4385 | * is essentially intel_wait_for_vblank. If we don't have this | |
4386 | * and don't wait for vblanks until the end of crtc_enable, then | |
4387 | * the HW state readout code will complain that the expected | |
4388 | * IPS_CTL value is not the one we read. */ | |
4389 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
4390 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
4391 | } | |
d77e4531 PZ |
4392 | } |
4393 | ||
20bc8673 | 4394 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4395 | { |
4396 | struct drm_device *dev = crtc->base.dev; | |
4397 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4398 | ||
6e3c9717 | 4399 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4400 | return; |
4401 | ||
4402 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4403 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4404 | mutex_lock(&dev_priv->rps.hw_lock); |
4405 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4406 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
4407 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
4408 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
4409 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 4410 | } else { |
2a114cc1 | 4411 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4412 | POSTING_READ(IPS_CTL); |
4413 | } | |
d77e4531 PZ |
4414 | |
4415 | /* We need to wait for a vblank before we can disable the plane. */ | |
4416 | intel_wait_for_vblank(dev, crtc->pipe); | |
4417 | } | |
4418 | ||
4419 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
4420 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
4421 | { | |
4422 | struct drm_device *dev = crtc->dev; | |
4423 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4424 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4425 | enum pipe pipe = intel_crtc->pipe; | |
4426 | int palreg = PALETTE(pipe); | |
4427 | int i; | |
4428 | bool reenable_ips = false; | |
4429 | ||
4430 | /* The clocks have to be on to load the palette. */ | |
83d65738 | 4431 | if (!crtc->state->enable || !intel_crtc->active) |
d77e4531 PZ |
4432 | return; |
4433 | ||
4434 | if (!HAS_PCH_SPLIT(dev_priv->dev)) { | |
409ee761 | 4435 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) |
d77e4531 PZ |
4436 | assert_dsi_pll_enabled(dev_priv); |
4437 | else | |
4438 | assert_pll_enabled(dev_priv, pipe); | |
4439 | } | |
4440 | ||
4441 | /* use legacy palette for Ironlake */ | |
7a1db49a | 4442 | if (!HAS_GMCH_DISPLAY(dev)) |
d77e4531 PZ |
4443 | palreg = LGC_PALETTE(pipe); |
4444 | ||
4445 | /* Workaround : Do not read or write the pipe palette/gamma data while | |
4446 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
4447 | */ | |
6e3c9717 | 4448 | if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled && |
d77e4531 PZ |
4449 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
4450 | GAMMA_MODE_MODE_SPLIT)) { | |
4451 | hsw_disable_ips(intel_crtc); | |
4452 | reenable_ips = true; | |
4453 | } | |
4454 | ||
4455 | for (i = 0; i < 256; i++) { | |
4456 | I915_WRITE(palreg + 4 * i, | |
4457 | (intel_crtc->lut_r[i] << 16) | | |
4458 | (intel_crtc->lut_g[i] << 8) | | |
4459 | intel_crtc->lut_b[i]); | |
4460 | } | |
4461 | ||
4462 | if (reenable_ips) | |
4463 | hsw_enable_ips(intel_crtc); | |
4464 | } | |
4465 | ||
d3eedb1a VS |
4466 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
4467 | { | |
4468 | if (!enable && intel_crtc->overlay) { | |
4469 | struct drm_device *dev = intel_crtc->base.dev; | |
4470 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4471 | ||
4472 | mutex_lock(&dev->struct_mutex); | |
4473 | dev_priv->mm.interruptible = false; | |
4474 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4475 | dev_priv->mm.interruptible = true; | |
4476 | mutex_unlock(&dev->struct_mutex); | |
4477 | } | |
4478 | ||
4479 | /* Let userspace switch the overlay on again. In most cases userspace | |
4480 | * has to recompute where to put it anyway. | |
4481 | */ | |
4482 | } | |
4483 | ||
d3eedb1a | 4484 | static void intel_crtc_enable_planes(struct drm_crtc *crtc) |
a5c4d7bc VS |
4485 | { |
4486 | struct drm_device *dev = crtc->dev; | |
a5c4d7bc VS |
4487 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4488 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4489 | |
fdd508a6 | 4490 | intel_enable_primary_hw_plane(crtc->primary, crtc); |
4a3b8769 | 4491 | intel_enable_sprite_planes(crtc); |
a5c4d7bc | 4492 | intel_crtc_update_cursor(crtc, true); |
d3eedb1a | 4493 | intel_crtc_dpms_overlay(intel_crtc, true); |
a5c4d7bc VS |
4494 | |
4495 | hsw_enable_ips(intel_crtc); | |
4496 | ||
4497 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 4498 | intel_fbc_update(dev); |
a5c4d7bc | 4499 | mutex_unlock(&dev->struct_mutex); |
f99d7069 DV |
4500 | |
4501 | /* | |
4502 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4503 | * to compute the mask of flip planes precisely. For the time being | |
4504 | * consider this a flip from a NULL plane. | |
4505 | */ | |
4506 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4507 | } |
4508 | ||
d3eedb1a | 4509 | static void intel_crtc_disable_planes(struct drm_crtc *crtc) |
a5c4d7bc VS |
4510 | { |
4511 | struct drm_device *dev = crtc->dev; | |
4512 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4513 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4514 | int pipe = intel_crtc->pipe; | |
a5c4d7bc VS |
4515 | |
4516 | intel_crtc_wait_for_pending_flips(crtc); | |
a5c4d7bc | 4517 | |
e35fef21 | 4518 | if (dev_priv->fbc.crtc == intel_crtc) |
7ff0ebcc | 4519 | intel_fbc_disable(dev); |
a5c4d7bc VS |
4520 | |
4521 | hsw_disable_ips(intel_crtc); | |
4522 | ||
d3eedb1a | 4523 | intel_crtc_dpms_overlay(intel_crtc, false); |
a5c4d7bc | 4524 | intel_crtc_update_cursor(crtc, false); |
4a3b8769 | 4525 | intel_disable_sprite_planes(crtc); |
fdd508a6 | 4526 | intel_disable_primary_hw_plane(crtc->primary, crtc); |
f98551ae | 4527 | |
f99d7069 DV |
4528 | /* |
4529 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4530 | * to compute the mask of flip planes precisely. For the time being | |
4531 | * consider this a flip to a NULL plane. | |
4532 | */ | |
4533 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4534 | } |
4535 | ||
f67a559d JB |
4536 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4537 | { | |
4538 | struct drm_device *dev = crtc->dev; | |
4539 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4540 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4541 | struct intel_encoder *encoder; |
f67a559d | 4542 | int pipe = intel_crtc->pipe; |
f67a559d | 4543 | |
83d65738 | 4544 | WARN_ON(!crtc->state->enable); |
08a48469 | 4545 | |
f67a559d JB |
4546 | if (intel_crtc->active) |
4547 | return; | |
4548 | ||
6e3c9717 | 4549 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
4550 | intel_prepare_shared_dpll(intel_crtc); |
4551 | ||
6e3c9717 | 4552 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4553 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
4554 | |
4555 | intel_set_pipe_timings(intel_crtc); | |
4556 | ||
6e3c9717 | 4557 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 4558 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4559 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
4560 | } |
4561 | ||
4562 | ironlake_set_pipeconf(crtc); | |
4563 | ||
f67a559d | 4564 | intel_crtc->active = true; |
8664281b | 4565 | |
a72e4c9f DV |
4566 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4567 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
8664281b | 4568 | |
f6736a1a | 4569 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4570 | if (encoder->pre_enable) |
4571 | encoder->pre_enable(encoder); | |
f67a559d | 4572 | |
6e3c9717 | 4573 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
4574 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4575 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4576 | * enabling. */ | |
88cefb6c | 4577 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4578 | } else { |
4579 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4580 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4581 | } | |
f67a559d | 4582 | |
b074cec8 | 4583 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4584 | |
9c54c0dd JB |
4585 | /* |
4586 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4587 | * clocks enabled | |
4588 | */ | |
4589 | intel_crtc_load_lut(crtc); | |
4590 | ||
f37fcc2a | 4591 | intel_update_watermarks(crtc); |
e1fdc473 | 4592 | intel_enable_pipe(intel_crtc); |
f67a559d | 4593 | |
6e3c9717 | 4594 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 4595 | ironlake_pch_enable(crtc); |
c98e9dcf | 4596 | |
f9b61ff6 DV |
4597 | assert_vblank_disabled(crtc); |
4598 | drm_crtc_vblank_on(crtc); | |
4599 | ||
fa5c73b1 DV |
4600 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4601 | encoder->enable(encoder); | |
61b77ddd DV |
4602 | |
4603 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4604 | cpt_verify_modeset(dev, intel_crtc->pipe); |
6ce94100 | 4605 | |
d3eedb1a | 4606 | intel_crtc_enable_planes(crtc); |
6be4a607 JB |
4607 | } |
4608 | ||
42db64ef PZ |
4609 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4610 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4611 | { | |
f5adf94e | 4612 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4613 | } |
4614 | ||
e4916946 PZ |
4615 | /* |
4616 | * This implements the workaround described in the "notes" section of the mode | |
4617 | * set sequence documentation. When going from no pipes or single pipe to | |
4618 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
4619 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
4620 | */ | |
4621 | static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) | |
4622 | { | |
4623 | struct drm_device *dev = crtc->base.dev; | |
4624 | struct intel_crtc *crtc_it, *other_active_crtc = NULL; | |
4625 | ||
4626 | /* We want to get the other_active_crtc only if there's only 1 other | |
4627 | * active crtc. */ | |
d3fcc808 | 4628 | for_each_intel_crtc(dev, crtc_it) { |
e4916946 PZ |
4629 | if (!crtc_it->active || crtc_it == crtc) |
4630 | continue; | |
4631 | ||
4632 | if (other_active_crtc) | |
4633 | return; | |
4634 | ||
4635 | other_active_crtc = crtc_it; | |
4636 | } | |
4637 | if (!other_active_crtc) | |
4638 | return; | |
4639 | ||
4640 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4641 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4642 | } | |
4643 | ||
4f771f10 PZ |
4644 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4645 | { | |
4646 | struct drm_device *dev = crtc->dev; | |
4647 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4648 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4649 | struct intel_encoder *encoder; | |
4650 | int pipe = intel_crtc->pipe; | |
4f771f10 | 4651 | |
83d65738 | 4652 | WARN_ON(!crtc->state->enable); |
4f771f10 PZ |
4653 | |
4654 | if (intel_crtc->active) | |
4655 | return; | |
4656 | ||
df8ad70c DV |
4657 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
4658 | intel_enable_shared_dpll(intel_crtc); | |
4659 | ||
6e3c9717 | 4660 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4661 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 DV |
4662 | |
4663 | intel_set_pipe_timings(intel_crtc); | |
4664 | ||
6e3c9717 ACO |
4665 | if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) { |
4666 | I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder), | |
4667 | intel_crtc->config->pixel_multiplier - 1); | |
ebb69c95 CT |
4668 | } |
4669 | ||
6e3c9717 | 4670 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 4671 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4672 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
4673 | } |
4674 | ||
4675 | haswell_set_pipeconf(crtc); | |
4676 | ||
4677 | intel_set_pipe_csc(crtc); | |
4678 | ||
4f771f10 | 4679 | intel_crtc->active = true; |
8664281b | 4680 | |
a72e4c9f | 4681 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4f771f10 PZ |
4682 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4683 | if (encoder->pre_enable) | |
4684 | encoder->pre_enable(encoder); | |
4685 | ||
6e3c9717 | 4686 | if (intel_crtc->config->has_pch_encoder) { |
a72e4c9f DV |
4687 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
4688 | true); | |
4fe9467d ID |
4689 | dev_priv->display.fdi_link_train(crtc); |
4690 | } | |
4691 | ||
1f544388 | 4692 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 4693 | |
bd2e244f JB |
4694 | if (IS_SKYLAKE(dev)) |
4695 | skylake_pfit_enable(intel_crtc); | |
4696 | else | |
4697 | ironlake_pfit_enable(intel_crtc); | |
4f771f10 PZ |
4698 | |
4699 | /* | |
4700 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4701 | * clocks enabled | |
4702 | */ | |
4703 | intel_crtc_load_lut(crtc); | |
4704 | ||
1f544388 | 4705 | intel_ddi_set_pipe_settings(crtc); |
8228c251 | 4706 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 4707 | |
f37fcc2a | 4708 | intel_update_watermarks(crtc); |
e1fdc473 | 4709 | intel_enable_pipe(intel_crtc); |
42db64ef | 4710 | |
6e3c9717 | 4711 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 4712 | lpt_pch_enable(crtc); |
4f771f10 | 4713 | |
6e3c9717 | 4714 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
4715 | intel_ddi_set_vc_payload_alloc(crtc, true); |
4716 | ||
f9b61ff6 DV |
4717 | assert_vblank_disabled(crtc); |
4718 | drm_crtc_vblank_on(crtc); | |
4719 | ||
8807e55b | 4720 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 4721 | encoder->enable(encoder); |
8807e55b JN |
4722 | intel_opregion_notify_encoder(encoder, true); |
4723 | } | |
4f771f10 | 4724 | |
e4916946 PZ |
4725 | /* If we change the relative order between pipe/planes enabling, we need |
4726 | * to change the workaround. */ | |
4727 | haswell_mode_set_planes_workaround(intel_crtc); | |
d3eedb1a | 4728 | intel_crtc_enable_planes(crtc); |
4f771f10 PZ |
4729 | } |
4730 | ||
bd2e244f JB |
4731 | static void skylake_pfit_disable(struct intel_crtc *crtc) |
4732 | { | |
4733 | struct drm_device *dev = crtc->base.dev; | |
4734 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4735 | int pipe = crtc->pipe; | |
4736 | ||
4737 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
4738 | * it's in use. The hw state code will make sure we get this right. */ | |
6e3c9717 | 4739 | if (crtc->config->pch_pfit.enabled) { |
bd2e244f JB |
4740 | I915_WRITE(PS_CTL(pipe), 0); |
4741 | I915_WRITE(PS_WIN_POS(pipe), 0); | |
4742 | I915_WRITE(PS_WIN_SZ(pipe), 0); | |
4743 | } | |
4744 | } | |
4745 | ||
3f8dce3a DV |
4746 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
4747 | { | |
4748 | struct drm_device *dev = crtc->base.dev; | |
4749 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4750 | int pipe = crtc->pipe; | |
4751 | ||
4752 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
4753 | * it's in use. The hw state code will make sure we get this right. */ | |
6e3c9717 | 4754 | if (crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
4755 | I915_WRITE(PF_CTL(pipe), 0); |
4756 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
4757 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
4758 | } | |
4759 | } | |
4760 | ||
6be4a607 JB |
4761 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
4762 | { | |
4763 | struct drm_device *dev = crtc->dev; | |
4764 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4765 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4766 | struct intel_encoder *encoder; |
6be4a607 | 4767 | int pipe = intel_crtc->pipe; |
5eddb70b | 4768 | u32 reg, temp; |
b52eb4dc | 4769 | |
f7abfe8b CW |
4770 | if (!intel_crtc->active) |
4771 | return; | |
4772 | ||
d3eedb1a | 4773 | intel_crtc_disable_planes(crtc); |
a5c4d7bc | 4774 | |
ea9d758d DV |
4775 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4776 | encoder->disable(encoder); | |
4777 | ||
f9b61ff6 DV |
4778 | drm_crtc_vblank_off(crtc); |
4779 | assert_vblank_disabled(crtc); | |
4780 | ||
6e3c9717 | 4781 | if (intel_crtc->config->has_pch_encoder) |
a72e4c9f | 4782 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
d925c59a | 4783 | |
575f7ab7 | 4784 | intel_disable_pipe(intel_crtc); |
32f9d658 | 4785 | |
3f8dce3a | 4786 | ironlake_pfit_disable(intel_crtc); |
2c07245f | 4787 | |
bf49ec8c DV |
4788 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4789 | if (encoder->post_disable) | |
4790 | encoder->post_disable(encoder); | |
2c07245f | 4791 | |
6e3c9717 | 4792 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 4793 | ironlake_fdi_disable(crtc); |
913d8d11 | 4794 | |
d925c59a | 4795 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 4796 | |
d925c59a DV |
4797 | if (HAS_PCH_CPT(dev)) { |
4798 | /* disable TRANS_DP_CTL */ | |
4799 | reg = TRANS_DP_CTL(pipe); | |
4800 | temp = I915_READ(reg); | |
4801 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
4802 | TRANS_DP_PORT_SEL_MASK); | |
4803 | temp |= TRANS_DP_PORT_SEL_NONE; | |
4804 | I915_WRITE(reg, temp); | |
4805 | ||
4806 | /* disable DPLL_SEL */ | |
4807 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 4808 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 4809 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 4810 | } |
e3421a18 | 4811 | |
d925c59a | 4812 | /* disable PCH DPLL */ |
e72f9fbf | 4813 | intel_disable_shared_dpll(intel_crtc); |
8db9d77b | 4814 | |
d925c59a DV |
4815 | ironlake_fdi_pll_disable(intel_crtc); |
4816 | } | |
6b383a7f | 4817 | |
f7abfe8b | 4818 | intel_crtc->active = false; |
46ba614c | 4819 | intel_update_watermarks(crtc); |
d1ebd816 BW |
4820 | |
4821 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 4822 | intel_fbc_update(dev); |
d1ebd816 | 4823 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 4824 | } |
1b3c7a47 | 4825 | |
4f771f10 | 4826 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 4827 | { |
4f771f10 PZ |
4828 | struct drm_device *dev = crtc->dev; |
4829 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 4830 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 4831 | struct intel_encoder *encoder; |
6e3c9717 | 4832 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 4833 | |
4f771f10 PZ |
4834 | if (!intel_crtc->active) |
4835 | return; | |
4836 | ||
d3eedb1a | 4837 | intel_crtc_disable_planes(crtc); |
dda9a66a | 4838 | |
8807e55b JN |
4839 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4840 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 4841 | encoder->disable(encoder); |
8807e55b | 4842 | } |
4f771f10 | 4843 | |
f9b61ff6 DV |
4844 | drm_crtc_vblank_off(crtc); |
4845 | assert_vblank_disabled(crtc); | |
4846 | ||
6e3c9717 | 4847 | if (intel_crtc->config->has_pch_encoder) |
a72e4c9f DV |
4848 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
4849 | false); | |
575f7ab7 | 4850 | intel_disable_pipe(intel_crtc); |
4f771f10 | 4851 | |
6e3c9717 | 4852 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
4853 | intel_ddi_set_vc_payload_alloc(crtc, false); |
4854 | ||
ad80a810 | 4855 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 4856 | |
bd2e244f JB |
4857 | if (IS_SKYLAKE(dev)) |
4858 | skylake_pfit_disable(intel_crtc); | |
4859 | else | |
4860 | ironlake_pfit_disable(intel_crtc); | |
4f771f10 | 4861 | |
1f544388 | 4862 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 4863 | |
6e3c9717 | 4864 | if (intel_crtc->config->has_pch_encoder) { |
ab4d966c | 4865 | lpt_disable_pch_transcoder(dev_priv); |
1ad960f2 | 4866 | intel_ddi_fdi_disable(crtc); |
83616634 | 4867 | } |
4f771f10 | 4868 | |
97b040aa ID |
4869 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4870 | if (encoder->post_disable) | |
4871 | encoder->post_disable(encoder); | |
4872 | ||
4f771f10 | 4873 | intel_crtc->active = false; |
46ba614c | 4874 | intel_update_watermarks(crtc); |
4f771f10 PZ |
4875 | |
4876 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 4877 | intel_fbc_update(dev); |
4f771f10 | 4878 | mutex_unlock(&dev->struct_mutex); |
df8ad70c DV |
4879 | |
4880 | if (intel_crtc_to_shared_dpll(intel_crtc)) | |
4881 | intel_disable_shared_dpll(intel_crtc); | |
4f771f10 PZ |
4882 | } |
4883 | ||
ee7b9f93 JB |
4884 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
4885 | { | |
4886 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e72f9fbf | 4887 | intel_put_shared_dpll(intel_crtc); |
ee7b9f93 JB |
4888 | } |
4889 | ||
6441ab5f | 4890 | |
2dd24552 JB |
4891 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
4892 | { | |
4893 | struct drm_device *dev = crtc->base.dev; | |
4894 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 4895 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 4896 | |
681a8504 | 4897 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
4898 | return; |
4899 | ||
2dd24552 | 4900 | /* |
c0b03411 DV |
4901 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
4902 | * according to register description and PRM. | |
2dd24552 | 4903 | */ |
c0b03411 DV |
4904 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
4905 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 4906 | |
b074cec8 JB |
4907 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
4908 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
4909 | |
4910 | /* Border color in case we don't scale up to the full screen. Black by | |
4911 | * default, change to something else for debugging. */ | |
4912 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
4913 | } |
4914 | ||
d05410f9 DA |
4915 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
4916 | { | |
4917 | switch (port) { | |
4918 | case PORT_A: | |
4919 | return POWER_DOMAIN_PORT_DDI_A_4_LANES; | |
4920 | case PORT_B: | |
4921 | return POWER_DOMAIN_PORT_DDI_B_4_LANES; | |
4922 | case PORT_C: | |
4923 | return POWER_DOMAIN_PORT_DDI_C_4_LANES; | |
4924 | case PORT_D: | |
4925 | return POWER_DOMAIN_PORT_DDI_D_4_LANES; | |
4926 | default: | |
4927 | WARN_ON_ONCE(1); | |
4928 | return POWER_DOMAIN_PORT_OTHER; | |
4929 | } | |
4930 | } | |
4931 | ||
77d22dca ID |
4932 | #define for_each_power_domain(domain, mask) \ |
4933 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
4934 | if ((1 << (domain)) & (mask)) | |
4935 | ||
319be8ae ID |
4936 | enum intel_display_power_domain |
4937 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
4938 | { | |
4939 | struct drm_device *dev = intel_encoder->base.dev; | |
4940 | struct intel_digital_port *intel_dig_port; | |
4941 | ||
4942 | switch (intel_encoder->type) { | |
4943 | case INTEL_OUTPUT_UNKNOWN: | |
4944 | /* Only DDI platforms should ever use this output type */ | |
4945 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
4946 | case INTEL_OUTPUT_DISPLAYPORT: | |
4947 | case INTEL_OUTPUT_HDMI: | |
4948 | case INTEL_OUTPUT_EDP: | |
4949 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 4950 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
4951 | case INTEL_OUTPUT_DP_MST: |
4952 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
4953 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
4954 | case INTEL_OUTPUT_ANALOG: |
4955 | return POWER_DOMAIN_PORT_CRT; | |
4956 | case INTEL_OUTPUT_DSI: | |
4957 | return POWER_DOMAIN_PORT_DSI; | |
4958 | default: | |
4959 | return POWER_DOMAIN_PORT_OTHER; | |
4960 | } | |
4961 | } | |
4962 | ||
4963 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) | |
77d22dca | 4964 | { |
319be8ae ID |
4965 | struct drm_device *dev = crtc->dev; |
4966 | struct intel_encoder *intel_encoder; | |
4967 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4968 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca ID |
4969 | unsigned long mask; |
4970 | enum transcoder transcoder; | |
4971 | ||
4972 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); | |
4973 | ||
4974 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); | |
4975 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
6e3c9717 ACO |
4976 | if (intel_crtc->config->pch_pfit.enabled || |
4977 | intel_crtc->config->pch_pfit.force_thru) | |
77d22dca ID |
4978 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
4979 | ||
319be8ae ID |
4980 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
4981 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); | |
4982 | ||
77d22dca ID |
4983 | return mask; |
4984 | } | |
4985 | ||
679dacd4 | 4986 | static void modeset_update_crtc_power_domains(struct drm_atomic_state *state) |
77d22dca | 4987 | { |
679dacd4 | 4988 | struct drm_device *dev = state->dev; |
77d22dca ID |
4989 | struct drm_i915_private *dev_priv = dev->dev_private; |
4990 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; | |
4991 | struct intel_crtc *crtc; | |
4992 | ||
4993 | /* | |
4994 | * First get all needed power domains, then put all unneeded, to avoid | |
4995 | * any unnecessary toggling of the power wells. | |
4996 | */ | |
d3fcc808 | 4997 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
4998 | enum intel_display_power_domain domain; |
4999 | ||
83d65738 | 5000 | if (!crtc->base.state->enable) |
77d22dca ID |
5001 | continue; |
5002 | ||
319be8ae | 5003 | pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base); |
77d22dca ID |
5004 | |
5005 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) | |
5006 | intel_display_power_get(dev_priv, domain); | |
5007 | } | |
5008 | ||
50f6e502 | 5009 | if (dev_priv->display.modeset_global_resources) |
679dacd4 | 5010 | dev_priv->display.modeset_global_resources(state); |
50f6e502 | 5011 | |
d3fcc808 | 5012 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
5013 | enum intel_display_power_domain domain; |
5014 | ||
5015 | for_each_power_domain(domain, crtc->enabled_power_domains) | |
5016 | intel_display_power_put(dev_priv, domain); | |
5017 | ||
5018 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; | |
5019 | } | |
5020 | ||
5021 | intel_display_set_init_power(dev_priv, false); | |
5022 | } | |
5023 | ||
dfcab17e | 5024 | /* returns HPLL frequency in kHz */ |
f8bf63fd | 5025 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) |
30a970c6 | 5026 | { |
586f49dc | 5027 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
30a970c6 | 5028 | |
586f49dc JB |
5029 | /* Obtain SKU information */ |
5030 | mutex_lock(&dev_priv->dpio_lock); | |
5031 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
5032 | CCK_FUSE_HPLL_FREQ_MASK; | |
5033 | mutex_unlock(&dev_priv->dpio_lock); | |
30a970c6 | 5034 | |
dfcab17e | 5035 | return vco_freq[hpll_freq] * 1000; |
30a970c6 JB |
5036 | } |
5037 | ||
f8bf63fd VS |
5038 | static void vlv_update_cdclk(struct drm_device *dev) |
5039 | { | |
5040 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5041 | ||
5042 | dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
43dc52c3 | 5043 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", |
f8bf63fd VS |
5044 | dev_priv->vlv_cdclk_freq); |
5045 | ||
5046 | /* | |
5047 | * Program the gmbus_freq based on the cdclk frequency. | |
5048 | * BSpec erroneously claims we should aim for 4MHz, but | |
5049 | * in fact 1MHz is the correct frequency. | |
5050 | */ | |
6be1e3d3 | 5051 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000)); |
f8bf63fd VS |
5052 | } |
5053 | ||
30a970c6 JB |
5054 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
5055 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
5056 | { | |
5057 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5058 | u32 val, cmd; | |
5059 | ||
d197b7d3 | 5060 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq); |
d60c4473 | 5061 | |
dfcab17e | 5062 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 5063 | cmd = 2; |
dfcab17e | 5064 | else if (cdclk == 266667) |
30a970c6 JB |
5065 | cmd = 1; |
5066 | else | |
5067 | cmd = 0; | |
5068 | ||
5069 | mutex_lock(&dev_priv->rps.hw_lock); | |
5070 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5071 | val &= ~DSPFREQGUAR_MASK; | |
5072 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
5073 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5074 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5075 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
5076 | 50)) { | |
5077 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5078 | } | |
5079 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5080 | ||
dfcab17e | 5081 | if (cdclk == 400000) { |
6bcda4f0 | 5082 | u32 divider; |
30a970c6 | 5083 | |
6bcda4f0 | 5084 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 JB |
5085 | |
5086 | mutex_lock(&dev_priv->dpio_lock); | |
5087 | /* adjust cdclk divider */ | |
5088 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
9cf33db5 | 5089 | val &= ~DISPLAY_FREQUENCY_VALUES; |
30a970c6 JB |
5090 | val |= divider; |
5091 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
5092 | |
5093 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
5094 | DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
5095 | 50)) | |
5096 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
5097 | mutex_unlock(&dev_priv->dpio_lock); |
5098 | } | |
5099 | ||
5100 | mutex_lock(&dev_priv->dpio_lock); | |
5101 | /* adjust self-refresh exit latency value */ | |
5102 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
5103 | val &= ~0x7f; | |
5104 | ||
5105 | /* | |
5106 | * For high bandwidth configs, we set a higher latency in the bunit | |
5107 | * so that the core display fetch happens in time to avoid underruns. | |
5108 | */ | |
dfcab17e | 5109 | if (cdclk == 400000) |
30a970c6 JB |
5110 | val |= 4500 / 250; /* 4.5 usec */ |
5111 | else | |
5112 | val |= 3000 / 250; /* 3.0 usec */ | |
5113 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
5114 | mutex_unlock(&dev_priv->dpio_lock); | |
5115 | ||
f8bf63fd | 5116 | vlv_update_cdclk(dev); |
30a970c6 JB |
5117 | } |
5118 | ||
383c5a6a VS |
5119 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
5120 | { | |
5121 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5122 | u32 val, cmd; | |
5123 | ||
5124 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq); | |
5125 | ||
5126 | switch (cdclk) { | |
383c5a6a VS |
5127 | case 333333: |
5128 | case 320000: | |
383c5a6a | 5129 | case 266667: |
383c5a6a | 5130 | case 200000: |
383c5a6a VS |
5131 | break; |
5132 | default: | |
5f77eeb0 | 5133 | MISSING_CASE(cdclk); |
383c5a6a VS |
5134 | return; |
5135 | } | |
5136 | ||
9d0d3fda VS |
5137 | /* |
5138 | * Specs are full of misinformation, but testing on actual | |
5139 | * hardware has shown that we just need to write the desired | |
5140 | * CCK divider into the Punit register. | |
5141 | */ | |
5142 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
5143 | ||
383c5a6a VS |
5144 | mutex_lock(&dev_priv->rps.hw_lock); |
5145 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5146 | val &= ~DSPFREQGUAR_MASK_CHV; | |
5147 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
5148 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5149 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5150 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
5151 | 50)) { | |
5152 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5153 | } | |
5154 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5155 | ||
5156 | vlv_update_cdclk(dev); | |
5157 | } | |
5158 | ||
30a970c6 JB |
5159 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
5160 | int max_pixclk) | |
5161 | { | |
6bcda4f0 | 5162 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 5163 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 5164 | |
30a970c6 JB |
5165 | /* |
5166 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
5167 | * 200MHz | |
5168 | * 267MHz | |
29dc7ef3 | 5169 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
5170 | * 400MHz (VLV only) |
5171 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
5172 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
5173 | * |
5174 | * We seem to get an unstable or solid color picture at 200MHz. | |
5175 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
5176 | * are off. | |
30a970c6 | 5177 | */ |
6cca3195 VS |
5178 | if (!IS_CHERRYVIEW(dev_priv) && |
5179 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 5180 | return 400000; |
6cca3195 | 5181 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 5182 | return freq_320; |
e37c67a1 | 5183 | else if (max_pixclk > 0) |
dfcab17e | 5184 | return 266667; |
e37c67a1 VS |
5185 | else |
5186 | return 200000; | |
30a970c6 JB |
5187 | } |
5188 | ||
2f2d7aa1 | 5189 | /* compute the max pixel clock for new configuration */ |
304603f4 | 5190 | static int intel_mode_max_pixclk(struct drm_atomic_state *state) |
30a970c6 | 5191 | { |
304603f4 | 5192 | struct drm_device *dev = state->dev; |
30a970c6 | 5193 | struct intel_crtc *intel_crtc; |
304603f4 | 5194 | struct intel_crtc_state *crtc_state; |
30a970c6 JB |
5195 | int max_pixclk = 0; |
5196 | ||
d3fcc808 | 5197 | for_each_intel_crtc(dev, intel_crtc) { |
304603f4 ACO |
5198 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
5199 | if (IS_ERR(crtc_state)) | |
5200 | return PTR_ERR(crtc_state); | |
5201 | ||
5202 | if (!crtc_state->base.enable) | |
5203 | continue; | |
5204 | ||
5205 | max_pixclk = max(max_pixclk, | |
5206 | crtc_state->base.adjusted_mode.crtc_clock); | |
30a970c6 JB |
5207 | } |
5208 | ||
5209 | return max_pixclk; | |
5210 | } | |
5211 | ||
304603f4 | 5212 | static int valleyview_modeset_global_pipes(struct drm_atomic_state *state, |
2f2d7aa1 | 5213 | unsigned *prepare_pipes) |
30a970c6 | 5214 | { |
304603f4 | 5215 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
30a970c6 | 5216 | struct intel_crtc *intel_crtc; |
304603f4 ACO |
5217 | int max_pixclk = intel_mode_max_pixclk(state); |
5218 | ||
5219 | if (max_pixclk < 0) | |
5220 | return max_pixclk; | |
30a970c6 | 5221 | |
d60c4473 ID |
5222 | if (valleyview_calc_cdclk(dev_priv, max_pixclk) == |
5223 | dev_priv->vlv_cdclk_freq) | |
304603f4 | 5224 | return 0; |
30a970c6 | 5225 | |
2f2d7aa1 | 5226 | /* disable/enable all currently active pipes while we change cdclk */ |
304603f4 | 5227 | for_each_intel_crtc(state->dev, intel_crtc) |
83d65738 | 5228 | if (intel_crtc->base.state->enable) |
30a970c6 | 5229 | *prepare_pipes |= (1 << intel_crtc->pipe); |
304603f4 ACO |
5230 | |
5231 | return 0; | |
30a970c6 JB |
5232 | } |
5233 | ||
1e69cd74 VS |
5234 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
5235 | { | |
5236 | unsigned int credits, default_credits; | |
5237 | ||
5238 | if (IS_CHERRYVIEW(dev_priv)) | |
5239 | default_credits = PFI_CREDIT(12); | |
5240 | else | |
5241 | default_credits = PFI_CREDIT(8); | |
5242 | ||
5243 | if (DIV_ROUND_CLOSEST(dev_priv->vlv_cdclk_freq, 1000) >= dev_priv->rps.cz_freq) { | |
5244 | /* CHV suggested value is 31 or 63 */ | |
5245 | if (IS_CHERRYVIEW(dev_priv)) | |
5246 | credits = PFI_CREDIT_31; | |
5247 | else | |
5248 | credits = PFI_CREDIT(15); | |
5249 | } else { | |
5250 | credits = default_credits; | |
5251 | } | |
5252 | ||
5253 | /* | |
5254 | * WA - write default credits before re-programming | |
5255 | * FIXME: should we also set the resend bit here? | |
5256 | */ | |
5257 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
5258 | default_credits); | |
5259 | ||
5260 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
5261 | credits | PFI_CREDIT_RESEND); | |
5262 | ||
5263 | /* | |
5264 | * FIXME is this guaranteed to clear | |
5265 | * immediately or should we poll for it? | |
5266 | */ | |
5267 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
5268 | } | |
5269 | ||
679dacd4 | 5270 | static void valleyview_modeset_global_resources(struct drm_atomic_state *state) |
30a970c6 | 5271 | { |
679dacd4 | 5272 | struct drm_device *dev = state->dev; |
30a970c6 | 5273 | struct drm_i915_private *dev_priv = dev->dev_private; |
304603f4 ACO |
5274 | int max_pixclk = intel_mode_max_pixclk(state); |
5275 | int req_cdclk; | |
5276 | ||
5277 | /* The only reason this can fail is if we fail to add the crtc_state | |
5278 | * to the atomic state. But that can't happen since the call to | |
5279 | * intel_mode_max_pixclk() in valleyview_modeset_global_pipes() (which | |
5280 | * can't have failed otherwise the mode set would be aborted) added all | |
5281 | * the states already. */ | |
5282 | if (WARN_ON(max_pixclk < 0)) | |
5283 | return; | |
5284 | ||
5285 | req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); | |
30a970c6 | 5286 | |
383c5a6a | 5287 | if (req_cdclk != dev_priv->vlv_cdclk_freq) { |
738c05c0 ID |
5288 | /* |
5289 | * FIXME: We can end up here with all power domains off, yet | |
5290 | * with a CDCLK frequency other than the minimum. To account | |
5291 | * for this take the PIPE-A power domain, which covers the HW | |
5292 | * blocks needed for the following programming. This can be | |
5293 | * removed once it's guaranteed that we get here either with | |
5294 | * the minimum CDCLK set, or the required power domains | |
5295 | * enabled. | |
5296 | */ | |
5297 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
5298 | ||
383c5a6a VS |
5299 | if (IS_CHERRYVIEW(dev)) |
5300 | cherryview_set_cdclk(dev, req_cdclk); | |
5301 | else | |
5302 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 5303 | |
1e69cd74 VS |
5304 | vlv_program_pfi_credits(dev_priv); |
5305 | ||
738c05c0 | 5306 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
383c5a6a | 5307 | } |
30a970c6 JB |
5308 | } |
5309 | ||
89b667f8 JB |
5310 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
5311 | { | |
5312 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 5313 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
5314 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5315 | struct intel_encoder *encoder; | |
5316 | int pipe = intel_crtc->pipe; | |
23538ef1 | 5317 | bool is_dsi; |
89b667f8 | 5318 | |
83d65738 | 5319 | WARN_ON(!crtc->state->enable); |
89b667f8 JB |
5320 | |
5321 | if (intel_crtc->active) | |
5322 | return; | |
5323 | ||
409ee761 | 5324 | is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI); |
8525a235 | 5325 | |
1ae0d137 VS |
5326 | if (!is_dsi) { |
5327 | if (IS_CHERRYVIEW(dev)) | |
6e3c9717 | 5328 | chv_prepare_pll(intel_crtc, intel_crtc->config); |
1ae0d137 | 5329 | else |
6e3c9717 | 5330 | vlv_prepare_pll(intel_crtc, intel_crtc->config); |
1ae0d137 | 5331 | } |
5b18e57c | 5332 | |
6e3c9717 | 5333 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 5334 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
5335 | |
5336 | intel_set_pipe_timings(intel_crtc); | |
5337 | ||
c14b0485 VS |
5338 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
5339 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5340 | ||
5341 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
5342 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
5343 | } | |
5344 | ||
5b18e57c DV |
5345 | i9xx_set_pipeconf(intel_crtc); |
5346 | ||
89b667f8 | 5347 | intel_crtc->active = true; |
89b667f8 | 5348 | |
a72e4c9f | 5349 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 5350 | |
89b667f8 JB |
5351 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5352 | if (encoder->pre_pll_enable) | |
5353 | encoder->pre_pll_enable(encoder); | |
5354 | ||
9d556c99 CML |
5355 | if (!is_dsi) { |
5356 | if (IS_CHERRYVIEW(dev)) | |
6e3c9717 | 5357 | chv_enable_pll(intel_crtc, intel_crtc->config); |
9d556c99 | 5358 | else |
6e3c9717 | 5359 | vlv_enable_pll(intel_crtc, intel_crtc->config); |
9d556c99 | 5360 | } |
89b667f8 JB |
5361 | |
5362 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
5363 | if (encoder->pre_enable) | |
5364 | encoder->pre_enable(encoder); | |
5365 | ||
2dd24552 JB |
5366 | i9xx_pfit_enable(intel_crtc); |
5367 | ||
63cbb074 VS |
5368 | intel_crtc_load_lut(crtc); |
5369 | ||
f37fcc2a | 5370 | intel_update_watermarks(crtc); |
e1fdc473 | 5371 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 5372 | |
4b3a9526 VS |
5373 | assert_vblank_disabled(crtc); |
5374 | drm_crtc_vblank_on(crtc); | |
5375 | ||
f9b61ff6 DV |
5376 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5377 | encoder->enable(encoder); | |
5378 | ||
9ab0460b | 5379 | intel_crtc_enable_planes(crtc); |
d40d9187 | 5380 | |
56b80e1f | 5381 | /* Underruns don't raise interrupts, so check manually. */ |
a72e4c9f | 5382 | i9xx_check_fifo_underruns(dev_priv); |
89b667f8 JB |
5383 | } |
5384 | ||
f13c2ef3 DV |
5385 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
5386 | { | |
5387 | struct drm_device *dev = crtc->base.dev; | |
5388 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5389 | ||
6e3c9717 ACO |
5390 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
5391 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
5392 | } |
5393 | ||
0b8765c6 | 5394 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
5395 | { |
5396 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 5397 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 5398 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 5399 | struct intel_encoder *encoder; |
79e53945 | 5400 | int pipe = intel_crtc->pipe; |
79e53945 | 5401 | |
83d65738 | 5402 | WARN_ON(!crtc->state->enable); |
08a48469 | 5403 | |
f7abfe8b CW |
5404 | if (intel_crtc->active) |
5405 | return; | |
5406 | ||
f13c2ef3 DV |
5407 | i9xx_set_pll_dividers(intel_crtc); |
5408 | ||
6e3c9717 | 5409 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 5410 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
5411 | |
5412 | intel_set_pipe_timings(intel_crtc); | |
5413 | ||
5b18e57c DV |
5414 | i9xx_set_pipeconf(intel_crtc); |
5415 | ||
f7abfe8b | 5416 | intel_crtc->active = true; |
6b383a7f | 5417 | |
4a3436e8 | 5418 | if (!IS_GEN2(dev)) |
a72e4c9f | 5419 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 5420 | |
9d6d9f19 MK |
5421 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5422 | if (encoder->pre_enable) | |
5423 | encoder->pre_enable(encoder); | |
5424 | ||
f6736a1a DV |
5425 | i9xx_enable_pll(intel_crtc); |
5426 | ||
2dd24552 JB |
5427 | i9xx_pfit_enable(intel_crtc); |
5428 | ||
63cbb074 VS |
5429 | intel_crtc_load_lut(crtc); |
5430 | ||
f37fcc2a | 5431 | intel_update_watermarks(crtc); |
e1fdc473 | 5432 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 5433 | |
4b3a9526 VS |
5434 | assert_vblank_disabled(crtc); |
5435 | drm_crtc_vblank_on(crtc); | |
5436 | ||
f9b61ff6 DV |
5437 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5438 | encoder->enable(encoder); | |
5439 | ||
9ab0460b | 5440 | intel_crtc_enable_planes(crtc); |
d40d9187 | 5441 | |
4a3436e8 VS |
5442 | /* |
5443 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
5444 | * So don't enable underrun reporting before at least some planes | |
5445 | * are enabled. | |
5446 | * FIXME: Need to fix the logic to work when we turn off all planes | |
5447 | * but leave the pipe running. | |
5448 | */ | |
5449 | if (IS_GEN2(dev)) | |
a72e4c9f | 5450 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 5451 | |
56b80e1f | 5452 | /* Underruns don't raise interrupts, so check manually. */ |
a72e4c9f | 5453 | i9xx_check_fifo_underruns(dev_priv); |
0b8765c6 | 5454 | } |
79e53945 | 5455 | |
87476d63 DV |
5456 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
5457 | { | |
5458 | struct drm_device *dev = crtc->base.dev; | |
5459 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 5460 | |
6e3c9717 | 5461 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 5462 | return; |
87476d63 | 5463 | |
328d8e82 | 5464 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 5465 | |
328d8e82 DV |
5466 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
5467 | I915_READ(PFIT_CONTROL)); | |
5468 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
5469 | } |
5470 | ||
0b8765c6 JB |
5471 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
5472 | { | |
5473 | struct drm_device *dev = crtc->dev; | |
5474 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5475 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 5476 | struct intel_encoder *encoder; |
0b8765c6 | 5477 | int pipe = intel_crtc->pipe; |
ef9c3aee | 5478 | |
f7abfe8b CW |
5479 | if (!intel_crtc->active) |
5480 | return; | |
5481 | ||
4a3436e8 VS |
5482 | /* |
5483 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
5484 | * So diasble underrun reporting before all the planes get disabled. | |
5485 | * FIXME: Need to fix the logic to work when we turn off all planes | |
5486 | * but leave the pipe running. | |
5487 | */ | |
5488 | if (IS_GEN2(dev)) | |
a72e4c9f | 5489 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
4a3436e8 | 5490 | |
564ed191 ID |
5491 | /* |
5492 | * Vblank time updates from the shadow to live plane control register | |
5493 | * are blocked if the memory self-refresh mode is active at that | |
5494 | * moment. So to make sure the plane gets truly disabled, disable | |
5495 | * first the self-refresh mode. The self-refresh enable bit in turn | |
5496 | * will be checked/applied by the HW only at the next frame start | |
5497 | * event which is after the vblank start event, so we need to have a | |
5498 | * wait-for-vblank between disabling the plane and the pipe. | |
5499 | */ | |
5500 | intel_set_memory_cxsr(dev_priv, false); | |
9ab0460b VS |
5501 | intel_crtc_disable_planes(crtc); |
5502 | ||
6304cd91 VS |
5503 | /* |
5504 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
5505 | * wait for planes to fully turn off before disabling the pipe. | |
564ed191 ID |
5506 | * We also need to wait on all gmch platforms because of the |
5507 | * self-refresh mode constraint explained above. | |
6304cd91 | 5508 | */ |
564ed191 | 5509 | intel_wait_for_vblank(dev, pipe); |
6304cd91 | 5510 | |
4b3a9526 VS |
5511 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5512 | encoder->disable(encoder); | |
5513 | ||
f9b61ff6 DV |
5514 | drm_crtc_vblank_off(crtc); |
5515 | assert_vblank_disabled(crtc); | |
5516 | ||
575f7ab7 | 5517 | intel_disable_pipe(intel_crtc); |
24a1f16d | 5518 | |
87476d63 | 5519 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 5520 | |
89b667f8 JB |
5521 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5522 | if (encoder->post_disable) | |
5523 | encoder->post_disable(encoder); | |
5524 | ||
409ee761 | 5525 | if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) { |
076ed3b2 CML |
5526 | if (IS_CHERRYVIEW(dev)) |
5527 | chv_disable_pll(dev_priv, pipe); | |
5528 | else if (IS_VALLEYVIEW(dev)) | |
5529 | vlv_disable_pll(dev_priv, pipe); | |
5530 | else | |
1c4e0274 | 5531 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 5532 | } |
0b8765c6 | 5533 | |
4a3436e8 | 5534 | if (!IS_GEN2(dev)) |
a72e4c9f | 5535 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
4a3436e8 | 5536 | |
f7abfe8b | 5537 | intel_crtc->active = false; |
46ba614c | 5538 | intel_update_watermarks(crtc); |
f37fcc2a | 5539 | |
efa9624e | 5540 | mutex_lock(&dev->struct_mutex); |
7ff0ebcc | 5541 | intel_fbc_update(dev); |
efa9624e | 5542 | mutex_unlock(&dev->struct_mutex); |
0b8765c6 JB |
5543 | } |
5544 | ||
ee7b9f93 JB |
5545 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
5546 | { | |
5547 | } | |
5548 | ||
b04c5bd6 BF |
5549 | /* Master function to enable/disable CRTC and corresponding power wells */ |
5550 | void intel_crtc_control(struct drm_crtc *crtc, bool enable) | |
976f8a20 DV |
5551 | { |
5552 | struct drm_device *dev = crtc->dev; | |
5553 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0e572fe7 | 5554 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
0e572fe7 DV |
5555 | enum intel_display_power_domain domain; |
5556 | unsigned long domains; | |
976f8a20 | 5557 | |
0e572fe7 DV |
5558 | if (enable) { |
5559 | if (!intel_crtc->active) { | |
e1e9fb84 DV |
5560 | domains = get_crtc_power_domains(crtc); |
5561 | for_each_power_domain(domain, domains) | |
5562 | intel_display_power_get(dev_priv, domain); | |
5563 | intel_crtc->enabled_power_domains = domains; | |
0e572fe7 DV |
5564 | |
5565 | dev_priv->display.crtc_enable(crtc); | |
5566 | } | |
5567 | } else { | |
5568 | if (intel_crtc->active) { | |
5569 | dev_priv->display.crtc_disable(crtc); | |
5570 | ||
e1e9fb84 DV |
5571 | domains = intel_crtc->enabled_power_domains; |
5572 | for_each_power_domain(domain, domains) | |
5573 | intel_display_power_put(dev_priv, domain); | |
5574 | intel_crtc->enabled_power_domains = 0; | |
0e572fe7 DV |
5575 | } |
5576 | } | |
b04c5bd6 BF |
5577 | } |
5578 | ||
5579 | /** | |
5580 | * Sets the power management mode of the pipe and plane. | |
5581 | */ | |
5582 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
5583 | { | |
5584 | struct drm_device *dev = crtc->dev; | |
5585 | struct intel_encoder *intel_encoder; | |
5586 | bool enable = false; | |
5587 | ||
5588 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
5589 | enable |= intel_encoder->connectors_active; | |
5590 | ||
5591 | intel_crtc_control(crtc, enable); | |
976f8a20 DV |
5592 | } |
5593 | ||
cdd59983 CW |
5594 | static void intel_crtc_disable(struct drm_crtc *crtc) |
5595 | { | |
cdd59983 | 5596 | struct drm_device *dev = crtc->dev; |
976f8a20 | 5597 | struct drm_connector *connector; |
ee7b9f93 | 5598 | struct drm_i915_private *dev_priv = dev->dev_private; |
cdd59983 | 5599 | |
976f8a20 | 5600 | /* crtc should still be enabled when we disable it. */ |
83d65738 | 5601 | WARN_ON(!crtc->state->enable); |
976f8a20 DV |
5602 | |
5603 | dev_priv->display.crtc_disable(crtc); | |
ee7b9f93 JB |
5604 | dev_priv->display.off(crtc); |
5605 | ||
70a101f8 | 5606 | drm_plane_helper_disable(crtc->primary); |
976f8a20 DV |
5607 | |
5608 | /* Update computed state. */ | |
5609 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
5610 | if (!connector->encoder || !connector->encoder->crtc) | |
5611 | continue; | |
5612 | ||
5613 | if (connector->encoder->crtc != crtc) | |
5614 | continue; | |
5615 | ||
5616 | connector->dpms = DRM_MODE_DPMS_OFF; | |
5617 | to_intel_encoder(connector->encoder)->connectors_active = false; | |
cdd59983 CW |
5618 | } |
5619 | } | |
5620 | ||
ea5b213a | 5621 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 5622 | { |
4ef69c7a | 5623 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 5624 | |
ea5b213a CW |
5625 | drm_encoder_cleanup(encoder); |
5626 | kfree(intel_encoder); | |
7e7d76c3 JB |
5627 | } |
5628 | ||
9237329d | 5629 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
5ab432ef DV |
5630 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
5631 | * state of the entire output pipe. */ | |
9237329d | 5632 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
7e7d76c3 | 5633 | { |
5ab432ef DV |
5634 | if (mode == DRM_MODE_DPMS_ON) { |
5635 | encoder->connectors_active = true; | |
5636 | ||
b2cabb0e | 5637 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
5638 | } else { |
5639 | encoder->connectors_active = false; | |
5640 | ||
b2cabb0e | 5641 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 5642 | } |
79e53945 JB |
5643 | } |
5644 | ||
0a91ca29 DV |
5645 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
5646 | * internal consistency). */ | |
b980514c | 5647 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 5648 | { |
0a91ca29 DV |
5649 | if (connector->get_hw_state(connector)) { |
5650 | struct intel_encoder *encoder = connector->encoder; | |
5651 | struct drm_crtc *crtc; | |
5652 | bool encoder_enabled; | |
5653 | enum pipe pipe; | |
5654 | ||
5655 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
5656 | connector->base.base.id, | |
c23cc417 | 5657 | connector->base.name); |
0a91ca29 | 5658 | |
0e32b39c DA |
5659 | /* there is no real hw state for MST connectors */ |
5660 | if (connector->mst_port) | |
5661 | return; | |
5662 | ||
e2c719b7 | 5663 | I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, |
0a91ca29 | 5664 | "wrong connector dpms state\n"); |
e2c719b7 | 5665 | I915_STATE_WARN(connector->base.encoder != &encoder->base, |
0a91ca29 | 5666 | "active connector not linked to encoder\n"); |
0a91ca29 | 5667 | |
36cd7444 | 5668 | if (encoder) { |
e2c719b7 | 5669 | I915_STATE_WARN(!encoder->connectors_active, |
36cd7444 DA |
5670 | "encoder->connectors_active not set\n"); |
5671 | ||
5672 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
e2c719b7 RC |
5673 | I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n"); |
5674 | if (I915_STATE_WARN_ON(!encoder->base.crtc)) | |
36cd7444 | 5675 | return; |
0a91ca29 | 5676 | |
36cd7444 | 5677 | crtc = encoder->base.crtc; |
0a91ca29 | 5678 | |
83d65738 MR |
5679 | I915_STATE_WARN(!crtc->state->enable, |
5680 | "crtc not enabled\n"); | |
e2c719b7 RC |
5681 | I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); |
5682 | I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe, | |
36cd7444 DA |
5683 | "encoder active on the wrong pipe\n"); |
5684 | } | |
0a91ca29 | 5685 | } |
79e53945 JB |
5686 | } |
5687 | ||
9bdbd0b9 ACO |
5688 | int intel_connector_init(struct intel_connector *connector) |
5689 | { | |
5690 | struct drm_connector_state *connector_state; | |
5691 | ||
5692 | connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL); | |
5693 | if (!connector_state) | |
5694 | return -ENOMEM; | |
5695 | ||
5696 | connector->base.state = connector_state; | |
5697 | return 0; | |
5698 | } | |
5699 | ||
5700 | struct intel_connector *intel_connector_alloc(void) | |
5701 | { | |
5702 | struct intel_connector *connector; | |
5703 | ||
5704 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
5705 | if (!connector) | |
5706 | return NULL; | |
5707 | ||
5708 | if (intel_connector_init(connector) < 0) { | |
5709 | kfree(connector); | |
5710 | return NULL; | |
5711 | } | |
5712 | ||
5713 | return connector; | |
5714 | } | |
5715 | ||
5ab432ef DV |
5716 | /* Even simpler default implementation, if there's really no special case to |
5717 | * consider. */ | |
5718 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 5719 | { |
5ab432ef DV |
5720 | /* All the simple cases only support two dpms states. */ |
5721 | if (mode != DRM_MODE_DPMS_ON) | |
5722 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 5723 | |
5ab432ef DV |
5724 | if (mode == connector->dpms) |
5725 | return; | |
5726 | ||
5727 | connector->dpms = mode; | |
5728 | ||
5729 | /* Only need to change hw state when actually enabled */ | |
c9976dcf CW |
5730 | if (connector->encoder) |
5731 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); | |
0a91ca29 | 5732 | |
b980514c | 5733 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
5734 | } |
5735 | ||
f0947c37 DV |
5736 | /* Simple connector->get_hw_state implementation for encoders that support only |
5737 | * one connector and no cloning and hence the encoder state determines the state | |
5738 | * of the connector. */ | |
5739 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 5740 | { |
24929352 | 5741 | enum pipe pipe = 0; |
f0947c37 | 5742 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 5743 | |
f0947c37 | 5744 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
5745 | } |
5746 | ||
6d293983 | 5747 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 5748 | { |
6d293983 ACO |
5749 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
5750 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
5751 | |
5752 | return 0; | |
5753 | } | |
5754 | ||
6d293983 | 5755 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 5756 | struct intel_crtc_state *pipe_config) |
1857e1da | 5757 | { |
6d293983 ACO |
5758 | struct drm_atomic_state *state = pipe_config->base.state; |
5759 | struct intel_crtc *other_crtc; | |
5760 | struct intel_crtc_state *other_crtc_state; | |
5761 | ||
1857e1da DV |
5762 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
5763 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5764 | if (pipe_config->fdi_lanes > 4) { | |
5765 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
5766 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 5767 | return -EINVAL; |
1857e1da DV |
5768 | } |
5769 | ||
bafb6553 | 5770 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
5771 | if (pipe_config->fdi_lanes > 2) { |
5772 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
5773 | pipe_config->fdi_lanes); | |
6d293983 | 5774 | return -EINVAL; |
1857e1da | 5775 | } else { |
6d293983 | 5776 | return 0; |
1857e1da DV |
5777 | } |
5778 | } | |
5779 | ||
5780 | if (INTEL_INFO(dev)->num_pipes == 2) | |
6d293983 | 5781 | return 0; |
1857e1da DV |
5782 | |
5783 | /* Ivybridge 3 pipe is really complicated */ | |
5784 | switch (pipe) { | |
5785 | case PIPE_A: | |
6d293983 | 5786 | return 0; |
1857e1da | 5787 | case PIPE_B: |
6d293983 ACO |
5788 | if (pipe_config->fdi_lanes <= 2) |
5789 | return 0; | |
5790 | ||
5791 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); | |
5792 | other_crtc_state = | |
5793 | intel_atomic_get_crtc_state(state, other_crtc); | |
5794 | if (IS_ERR(other_crtc_state)) | |
5795 | return PTR_ERR(other_crtc_state); | |
5796 | ||
5797 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
5798 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
5799 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 5800 | return -EINVAL; |
1857e1da | 5801 | } |
6d293983 | 5802 | return 0; |
1857e1da | 5803 | case PIPE_C: |
251cc67c VS |
5804 | if (pipe_config->fdi_lanes > 2) { |
5805 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
5806 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 5807 | return -EINVAL; |
251cc67c | 5808 | } |
6d293983 ACO |
5809 | |
5810 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); | |
5811 | other_crtc_state = | |
5812 | intel_atomic_get_crtc_state(state, other_crtc); | |
5813 | if (IS_ERR(other_crtc_state)) | |
5814 | return PTR_ERR(other_crtc_state); | |
5815 | ||
5816 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 5817 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 5818 | return -EINVAL; |
1857e1da | 5819 | } |
6d293983 | 5820 | return 0; |
1857e1da DV |
5821 | default: |
5822 | BUG(); | |
5823 | } | |
5824 | } | |
5825 | ||
e29c22c0 DV |
5826 | #define RETRY 1 |
5827 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 5828 | struct intel_crtc_state *pipe_config) |
877d48d5 | 5829 | { |
1857e1da | 5830 | struct drm_device *dev = intel_crtc->base.dev; |
2d112de7 | 5831 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
5832 | int lane, link_bw, fdi_dotclock, ret; |
5833 | bool needs_recompute = false; | |
877d48d5 | 5834 | |
e29c22c0 | 5835 | retry: |
877d48d5 DV |
5836 | /* FDI is a binary signal running at ~2.7GHz, encoding |
5837 | * each output octet as 10 bits. The actual frequency | |
5838 | * is stored as a divider into a 100MHz clock, and the | |
5839 | * mode pixel clock is stored in units of 1KHz. | |
5840 | * Hence the bw of each lane in terms of the mode signal | |
5841 | * is: | |
5842 | */ | |
5843 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
5844 | ||
241bfc38 | 5845 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 5846 | |
2bd89a07 | 5847 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
5848 | pipe_config->pipe_bpp); |
5849 | ||
5850 | pipe_config->fdi_lanes = lane; | |
5851 | ||
2bd89a07 | 5852 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 5853 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 5854 | |
6d293983 ACO |
5855 | ret = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
5856 | intel_crtc->pipe, pipe_config); | |
5857 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { | |
e29c22c0 DV |
5858 | pipe_config->pipe_bpp -= 2*3; |
5859 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
5860 | pipe_config->pipe_bpp); | |
5861 | needs_recompute = true; | |
5862 | pipe_config->bw_constrained = true; | |
5863 | ||
5864 | goto retry; | |
5865 | } | |
5866 | ||
5867 | if (needs_recompute) | |
5868 | return RETRY; | |
5869 | ||
6d293983 | 5870 | return ret; |
877d48d5 DV |
5871 | } |
5872 | ||
42db64ef | 5873 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 5874 | struct intel_crtc_state *pipe_config) |
42db64ef | 5875 | { |
d330a953 | 5876 | pipe_config->ips_enabled = i915.enable_ips && |
3c4ca58c | 5877 | hsw_crtc_supports_ips(crtc) && |
b6dfdc9b | 5878 | pipe_config->pipe_bpp <= 24; |
42db64ef PZ |
5879 | } |
5880 | ||
a43f6e0f | 5881 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 5882 | struct intel_crtc_state *pipe_config) |
79e53945 | 5883 | { |
a43f6e0f | 5884 | struct drm_device *dev = crtc->base.dev; |
8bd31e67 | 5885 | struct drm_i915_private *dev_priv = dev->dev_private; |
2d112de7 | 5886 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
89749350 | 5887 | |
ad3a4479 | 5888 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 | 5889 | if (INTEL_INFO(dev)->gen < 4) { |
cf532bb2 VS |
5890 | int clock_limit = |
5891 | dev_priv->display.get_display_clock_speed(dev); | |
5892 | ||
5893 | /* | |
5894 | * Enable pixel doubling when the dot clock | |
5895 | * is > 90% of the (display) core speed. | |
5896 | * | |
b397c96b VS |
5897 | * GDG double wide on either pipe, |
5898 | * otherwise pipe A only. | |
cf532bb2 | 5899 | */ |
b397c96b | 5900 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
241bfc38 | 5901 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
ad3a4479 | 5902 | clock_limit *= 2; |
cf532bb2 | 5903 | pipe_config->double_wide = true; |
ad3a4479 VS |
5904 | } |
5905 | ||
241bfc38 | 5906 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
e29c22c0 | 5907 | return -EINVAL; |
2c07245f | 5908 | } |
89749350 | 5909 | |
1d1d0e27 VS |
5910 | /* |
5911 | * Pipe horizontal size must be even in: | |
5912 | * - DVO ganged mode | |
5913 | * - LVDS dual channel mode | |
5914 | * - Double wide pipe | |
5915 | */ | |
a93e255f | 5916 | if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
5917 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
5918 | pipe_config->pipe_src_w &= ~1; | |
5919 | ||
8693a824 DL |
5920 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
5921 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
5922 | */ |
5923 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
5924 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
e29c22c0 | 5925 | return -EINVAL; |
44f46b42 | 5926 | |
bd080ee5 | 5927 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { |
5d2d38dd | 5928 | pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ |
bd080ee5 | 5929 | } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { |
5d2d38dd DV |
5930 | /* only a 8bpc pipe, with 6bpc dither through the panel fitter |
5931 | * for lvds. */ | |
5932 | pipe_config->pipe_bpp = 8*3; | |
5933 | } | |
5934 | ||
f5adf94e | 5935 | if (HAS_IPS(dev)) |
a43f6e0f DV |
5936 | hsw_compute_ips_config(crtc, pipe_config); |
5937 | ||
877d48d5 | 5938 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 5939 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 5940 | |
e29c22c0 | 5941 | return 0; |
79e53945 JB |
5942 | } |
5943 | ||
1652d19e VS |
5944 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
5945 | { | |
5946 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5947 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
5948 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
5949 | uint32_t linkrate; | |
5950 | ||
5951 | if (!(lcpll1 & LCPLL_PLL_ENABLE)) { | |
5952 | WARN(1, "LCPLL1 not enabled\n"); | |
5953 | return 24000; /* 24MHz is the cd freq with NSSC ref */ | |
5954 | } | |
5955 | ||
5956 | if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) | |
5957 | return 540000; | |
5958 | ||
5959 | linkrate = (I915_READ(DPLL_CTRL1) & | |
5960 | DPLL_CRTL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; | |
5961 | ||
5962 | if (linkrate == DPLL_CRTL1_LINK_RATE_2160 || | |
5963 | linkrate == DPLL_CRTL1_LINK_RATE_1080) { | |
5964 | /* vco 8640 */ | |
5965 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
5966 | case CDCLK_FREQ_450_432: | |
5967 | return 432000; | |
5968 | case CDCLK_FREQ_337_308: | |
5969 | return 308570; | |
5970 | case CDCLK_FREQ_675_617: | |
5971 | return 617140; | |
5972 | default: | |
5973 | WARN(1, "Unknown cd freq selection\n"); | |
5974 | } | |
5975 | } else { | |
5976 | /* vco 8100 */ | |
5977 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
5978 | case CDCLK_FREQ_450_432: | |
5979 | return 450000; | |
5980 | case CDCLK_FREQ_337_308: | |
5981 | return 337500; | |
5982 | case CDCLK_FREQ_675_617: | |
5983 | return 675000; | |
5984 | default: | |
5985 | WARN(1, "Unknown cd freq selection\n"); | |
5986 | } | |
5987 | } | |
5988 | ||
5989 | /* error case, do as if DPLL0 isn't enabled */ | |
5990 | return 24000; | |
5991 | } | |
5992 | ||
5993 | static int broadwell_get_display_clock_speed(struct drm_device *dev) | |
5994 | { | |
5995 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5996 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
5997 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
5998 | ||
5999 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6000 | return 800000; | |
6001 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6002 | return 450000; | |
6003 | else if (freq == LCPLL_CLK_FREQ_450) | |
6004 | return 450000; | |
6005 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
6006 | return 540000; | |
6007 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
6008 | return 337500; | |
6009 | else | |
6010 | return 675000; | |
6011 | } | |
6012 | ||
6013 | static int haswell_get_display_clock_speed(struct drm_device *dev) | |
6014 | { | |
6015 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6016 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6017 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6018 | ||
6019 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6020 | return 800000; | |
6021 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6022 | return 450000; | |
6023 | else if (freq == LCPLL_CLK_FREQ_450) | |
6024 | return 450000; | |
6025 | else if (IS_HSW_ULT(dev)) | |
6026 | return 337500; | |
6027 | else | |
6028 | return 540000; | |
6029 | } | |
6030 | ||
25eb05fc JB |
6031 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
6032 | { | |
d197b7d3 | 6033 | struct drm_i915_private *dev_priv = dev->dev_private; |
d197b7d3 VS |
6034 | u32 val; |
6035 | int divider; | |
6036 | ||
6bcda4f0 VS |
6037 | if (dev_priv->hpll_freq == 0) |
6038 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
6039 | ||
d197b7d3 VS |
6040 | mutex_lock(&dev_priv->dpio_lock); |
6041 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
6042 | mutex_unlock(&dev_priv->dpio_lock); | |
6043 | ||
6044 | divider = val & DISPLAY_FREQUENCY_VALUES; | |
6045 | ||
7d007f40 VS |
6046 | WARN((val & DISPLAY_FREQUENCY_STATUS) != |
6047 | (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
6048 | "cdclk change in progress\n"); | |
6049 | ||
6bcda4f0 | 6050 | return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); |
25eb05fc JB |
6051 | } |
6052 | ||
b37a6434 VS |
6053 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
6054 | { | |
6055 | return 450000; | |
6056 | } | |
6057 | ||
e70236a8 JB |
6058 | static int i945_get_display_clock_speed(struct drm_device *dev) |
6059 | { | |
6060 | return 400000; | |
6061 | } | |
79e53945 | 6062 | |
e70236a8 | 6063 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 6064 | { |
e907f170 | 6065 | return 333333; |
e70236a8 | 6066 | } |
79e53945 | 6067 | |
e70236a8 JB |
6068 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
6069 | { | |
6070 | return 200000; | |
6071 | } | |
79e53945 | 6072 | |
257a7ffc DV |
6073 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
6074 | { | |
6075 | u16 gcfgc = 0; | |
6076 | ||
6077 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
6078 | ||
6079 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6080 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 6081 | return 266667; |
257a7ffc | 6082 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 6083 | return 333333; |
257a7ffc | 6084 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 6085 | return 444444; |
257a7ffc DV |
6086 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
6087 | return 200000; | |
6088 | default: | |
6089 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
6090 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 6091 | return 133333; |
257a7ffc | 6092 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 6093 | return 166667; |
257a7ffc DV |
6094 | } |
6095 | } | |
6096 | ||
e70236a8 JB |
6097 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
6098 | { | |
6099 | u16 gcfgc = 0; | |
79e53945 | 6100 | |
e70236a8 JB |
6101 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
6102 | ||
6103 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 6104 | return 133333; |
e70236a8 JB |
6105 | else { |
6106 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6107 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 6108 | return 333333; |
e70236a8 JB |
6109 | default: |
6110 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
6111 | return 190000; | |
79e53945 | 6112 | } |
e70236a8 JB |
6113 | } |
6114 | } | |
6115 | ||
6116 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
6117 | { | |
e907f170 | 6118 | return 266667; |
e70236a8 JB |
6119 | } |
6120 | ||
6121 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
6122 | { | |
6123 | u16 hpllcc = 0; | |
6124 | /* Assume that the hardware is in the high speed state. This | |
6125 | * should be the default. | |
6126 | */ | |
6127 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
6128 | case GC_CLOCK_133_200: | |
6129 | case GC_CLOCK_100_200: | |
6130 | return 200000; | |
6131 | case GC_CLOCK_166_250: | |
6132 | return 250000; | |
6133 | case GC_CLOCK_100_133: | |
e907f170 | 6134 | return 133333; |
e70236a8 | 6135 | } |
79e53945 | 6136 | |
e70236a8 JB |
6137 | /* Shouldn't happen */ |
6138 | return 0; | |
6139 | } | |
79e53945 | 6140 | |
e70236a8 JB |
6141 | static int i830_get_display_clock_speed(struct drm_device *dev) |
6142 | { | |
e907f170 | 6143 | return 133333; |
79e53945 JB |
6144 | } |
6145 | ||
2c07245f | 6146 | static void |
a65851af | 6147 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 6148 | { |
a65851af VS |
6149 | while (*num > DATA_LINK_M_N_MASK || |
6150 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
6151 | *num >>= 1; |
6152 | *den >>= 1; | |
6153 | } | |
6154 | } | |
6155 | ||
a65851af VS |
6156 | static void compute_m_n(unsigned int m, unsigned int n, |
6157 | uint32_t *ret_m, uint32_t *ret_n) | |
6158 | { | |
6159 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
6160 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
6161 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
6162 | } | |
6163 | ||
e69d0bc1 DV |
6164 | void |
6165 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
6166 | int pixel_clock, int link_clock, | |
6167 | struct intel_link_m_n *m_n) | |
2c07245f | 6168 | { |
e69d0bc1 | 6169 | m_n->tu = 64; |
a65851af VS |
6170 | |
6171 | compute_m_n(bits_per_pixel * pixel_clock, | |
6172 | link_clock * nlanes * 8, | |
6173 | &m_n->gmch_m, &m_n->gmch_n); | |
6174 | ||
6175 | compute_m_n(pixel_clock, link_clock, | |
6176 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
6177 | } |
6178 | ||
a7615030 CW |
6179 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
6180 | { | |
d330a953 JN |
6181 | if (i915.panel_use_ssc >= 0) |
6182 | return i915.panel_use_ssc != 0; | |
41aa3448 | 6183 | return dev_priv->vbt.lvds_use_ssc |
435793df | 6184 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
6185 | } |
6186 | ||
a93e255f ACO |
6187 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
6188 | int num_connectors) | |
c65d77d8 | 6189 | { |
a93e255f | 6190 | struct drm_device *dev = crtc_state->base.crtc->dev; |
c65d77d8 JB |
6191 | struct drm_i915_private *dev_priv = dev->dev_private; |
6192 | int refclk; | |
6193 | ||
a93e255f ACO |
6194 | WARN_ON(!crtc_state->base.state); |
6195 | ||
a0c4da24 | 6196 | if (IS_VALLEYVIEW(dev)) { |
9a0ea498 | 6197 | refclk = 100000; |
a93e255f | 6198 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 6199 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
6200 | refclk = dev_priv->vbt.lvds_ssc_freq; |
6201 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
6202 | } else if (!IS_GEN2(dev)) { |
6203 | refclk = 96000; | |
6204 | } else { | |
6205 | refclk = 48000; | |
6206 | } | |
6207 | ||
6208 | return refclk; | |
6209 | } | |
6210 | ||
7429e9d4 | 6211 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 6212 | { |
7df00d7a | 6213 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 6214 | } |
f47709a9 | 6215 | |
7429e9d4 DV |
6216 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
6217 | { | |
6218 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
6219 | } |
6220 | ||
f47709a9 | 6221 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 6222 | struct intel_crtc_state *crtc_state, |
a7516a05 JB |
6223 | intel_clock_t *reduced_clock) |
6224 | { | |
f47709a9 | 6225 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
6226 | u32 fp, fp2 = 0; |
6227 | ||
6228 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 6229 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 6230 | if (reduced_clock) |
7429e9d4 | 6231 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 6232 | } else { |
190f68c5 | 6233 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 6234 | if (reduced_clock) |
7429e9d4 | 6235 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
6236 | } |
6237 | ||
190f68c5 | 6238 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 6239 | |
f47709a9 | 6240 | crtc->lowfreq_avail = false; |
a93e255f | 6241 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 6242 | reduced_clock) { |
190f68c5 | 6243 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 6244 | crtc->lowfreq_avail = true; |
a7516a05 | 6245 | } else { |
190f68c5 | 6246 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
6247 | } |
6248 | } | |
6249 | ||
5e69f97f CML |
6250 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
6251 | pipe) | |
89b667f8 JB |
6252 | { |
6253 | u32 reg_val; | |
6254 | ||
6255 | /* | |
6256 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
6257 | * and set it to a reasonable value instead. | |
6258 | */ | |
ab3c759a | 6259 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
6260 | reg_val &= 0xffffff00; |
6261 | reg_val |= 0x00000030; | |
ab3c759a | 6262 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 6263 | |
ab3c759a | 6264 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
6265 | reg_val &= 0x8cffffff; |
6266 | reg_val = 0x8c000000; | |
ab3c759a | 6267 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 6268 | |
ab3c759a | 6269 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 6270 | reg_val &= 0xffffff00; |
ab3c759a | 6271 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 6272 | |
ab3c759a | 6273 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
6274 | reg_val &= 0x00ffffff; |
6275 | reg_val |= 0xb0000000; | |
ab3c759a | 6276 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
6277 | } |
6278 | ||
b551842d DV |
6279 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
6280 | struct intel_link_m_n *m_n) | |
6281 | { | |
6282 | struct drm_device *dev = crtc->base.dev; | |
6283 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6284 | int pipe = crtc->pipe; | |
6285 | ||
e3b95f1e DV |
6286 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6287 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
6288 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
6289 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
6290 | } |
6291 | ||
6292 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
6293 | struct intel_link_m_n *m_n, |
6294 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
6295 | { |
6296 | struct drm_device *dev = crtc->base.dev; | |
6297 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6298 | int pipe = crtc->pipe; | |
6e3c9717 | 6299 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
6300 | |
6301 | if (INTEL_INFO(dev)->gen >= 5) { | |
6302 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
6303 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
6304 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
6305 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
6306 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
6307 | * for gen < 8) and if DRRS is supported (to make sure the | |
6308 | * registers are not unnecessarily accessed). | |
6309 | */ | |
44395bfe | 6310 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 6311 | crtc->config->has_drrs) { |
f769cd24 VK |
6312 | I915_WRITE(PIPE_DATA_M2(transcoder), |
6313 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
6314 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
6315 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
6316 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
6317 | } | |
b551842d | 6318 | } else { |
e3b95f1e DV |
6319 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6320 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
6321 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
6322 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
6323 | } |
6324 | } | |
6325 | ||
fe3cd48d | 6326 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 6327 | { |
fe3cd48d R |
6328 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
6329 | ||
6330 | if (m_n == M1_N1) { | |
6331 | dp_m_n = &crtc->config->dp_m_n; | |
6332 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
6333 | } else if (m_n == M2_N2) { | |
6334 | ||
6335 | /* | |
6336 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
6337 | * needs to be programmed into M1_N1. | |
6338 | */ | |
6339 | dp_m_n = &crtc->config->dp_m2_n2; | |
6340 | } else { | |
6341 | DRM_ERROR("Unsupported divider value\n"); | |
6342 | return; | |
6343 | } | |
6344 | ||
6e3c9717 ACO |
6345 | if (crtc->config->has_pch_encoder) |
6346 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 6347 | else |
fe3cd48d | 6348 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
6349 | } |
6350 | ||
d288f65f | 6351 | static void vlv_update_pll(struct intel_crtc *crtc, |
5cec258b | 6352 | struct intel_crtc_state *pipe_config) |
bdd4b6a6 DV |
6353 | { |
6354 | u32 dpll, dpll_md; | |
6355 | ||
6356 | /* | |
6357 | * Enable DPIO clock input. We should never disable the reference | |
6358 | * clock for pipe B, since VGA hotplug / manual detection depends | |
6359 | * on it. | |
6360 | */ | |
6361 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | | |
6362 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; | |
6363 | /* We should never disable this, set it here for state tracking */ | |
6364 | if (crtc->pipe == PIPE_B) | |
6365 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
6366 | dpll |= DPLL_VCO_ENABLE; | |
d288f65f | 6367 | pipe_config->dpll_hw_state.dpll = dpll; |
bdd4b6a6 | 6368 | |
d288f65f | 6369 | dpll_md = (pipe_config->pixel_multiplier - 1) |
bdd4b6a6 | 6370 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
d288f65f | 6371 | pipe_config->dpll_hw_state.dpll_md = dpll_md; |
bdd4b6a6 DV |
6372 | } |
6373 | ||
d288f65f | 6374 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 6375 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 6376 | { |
f47709a9 | 6377 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 6378 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 6379 | int pipe = crtc->pipe; |
bdd4b6a6 | 6380 | u32 mdiv; |
a0c4da24 | 6381 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 6382 | u32 coreclk, reg_val; |
a0c4da24 | 6383 | |
09153000 DV |
6384 | mutex_lock(&dev_priv->dpio_lock); |
6385 | ||
d288f65f VS |
6386 | bestn = pipe_config->dpll.n; |
6387 | bestm1 = pipe_config->dpll.m1; | |
6388 | bestm2 = pipe_config->dpll.m2; | |
6389 | bestp1 = pipe_config->dpll.p1; | |
6390 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 6391 | |
89b667f8 JB |
6392 | /* See eDP HDMI DPIO driver vbios notes doc */ |
6393 | ||
6394 | /* PLL B needs special handling */ | |
bdd4b6a6 | 6395 | if (pipe == PIPE_B) |
5e69f97f | 6396 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
6397 | |
6398 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 6399 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
6400 | |
6401 | /* Disable target IRef on PLL */ | |
ab3c759a | 6402 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 6403 | reg_val &= 0x00ffffff; |
ab3c759a | 6404 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
6405 | |
6406 | /* Disable fast lock */ | |
ab3c759a | 6407 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
6408 | |
6409 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
6410 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
6411 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
6412 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 6413 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
6414 | |
6415 | /* | |
6416 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
6417 | * but we don't support that). | |
6418 | * Note: don't use the DAC post divider as it seems unstable. | |
6419 | */ | |
6420 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 6421 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6422 | |
a0c4da24 | 6423 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 6424 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6425 | |
89b667f8 | 6426 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 6427 | if (pipe_config->port_clock == 162000 || |
409ee761 ACO |
6428 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || |
6429 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 6430 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 6431 | 0x009f0003); |
89b667f8 | 6432 | else |
ab3c759a | 6433 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
6434 | 0x00d0000f); |
6435 | ||
681a8504 | 6436 | if (pipe_config->has_dp_encoder) { |
89b667f8 | 6437 | /* Use SSC source */ |
bdd4b6a6 | 6438 | if (pipe == PIPE_A) |
ab3c759a | 6439 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6440 | 0x0df40000); |
6441 | else | |
ab3c759a | 6442 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6443 | 0x0df70000); |
6444 | } else { /* HDMI or VGA */ | |
6445 | /* Use bend source */ | |
bdd4b6a6 | 6446 | if (pipe == PIPE_A) |
ab3c759a | 6447 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6448 | 0x0df70000); |
6449 | else | |
ab3c759a | 6450 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6451 | 0x0df40000); |
6452 | } | |
a0c4da24 | 6453 | |
ab3c759a | 6454 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 6455 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
409ee761 ACO |
6456 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
6457 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) | |
89b667f8 | 6458 | coreclk |= 0x01000000; |
ab3c759a | 6459 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 6460 | |
ab3c759a | 6461 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
09153000 | 6462 | mutex_unlock(&dev_priv->dpio_lock); |
a0c4da24 JB |
6463 | } |
6464 | ||
d288f65f | 6465 | static void chv_update_pll(struct intel_crtc *crtc, |
5cec258b | 6466 | struct intel_crtc_state *pipe_config) |
1ae0d137 | 6467 | { |
d288f65f | 6468 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV | |
1ae0d137 VS |
6469 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | |
6470 | DPLL_VCO_ENABLE; | |
6471 | if (crtc->pipe != PIPE_A) | |
d288f65f | 6472 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
1ae0d137 | 6473 | |
d288f65f VS |
6474 | pipe_config->dpll_hw_state.dpll_md = |
6475 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
1ae0d137 VS |
6476 | } |
6477 | ||
d288f65f | 6478 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 6479 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
6480 | { |
6481 | struct drm_device *dev = crtc->base.dev; | |
6482 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6483 | int pipe = crtc->pipe; | |
6484 | int dpll_reg = DPLL(crtc->pipe); | |
6485 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9cbe40c1 | 6486 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 6487 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 6488 | u32 dpio_val; |
9cbe40c1 | 6489 | int vco; |
9d556c99 | 6490 | |
d288f65f VS |
6491 | bestn = pipe_config->dpll.n; |
6492 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
6493 | bestm1 = pipe_config->dpll.m1; | |
6494 | bestm2 = pipe_config->dpll.m2 >> 22; | |
6495 | bestp1 = pipe_config->dpll.p1; | |
6496 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 6497 | vco = pipe_config->dpll.vco; |
a945ce7e | 6498 | dpio_val = 0; |
9cbe40c1 | 6499 | loopfilter = 0; |
9d556c99 CML |
6500 | |
6501 | /* | |
6502 | * Enable Refclk and SSC | |
6503 | */ | |
a11b0703 | 6504 | I915_WRITE(dpll_reg, |
d288f65f | 6505 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
a11b0703 VS |
6506 | |
6507 | mutex_lock(&dev_priv->dpio_lock); | |
9d556c99 | 6508 | |
9d556c99 CML |
6509 | /* p1 and p2 divider */ |
6510 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
6511 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
6512 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
6513 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
6514 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
6515 | ||
6516 | /* Feedback post-divider - m2 */ | |
6517 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
6518 | ||
6519 | /* Feedback refclk divider - n and m1 */ | |
6520 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
6521 | DPIO_CHV_M1_DIV_BY_2 | | |
6522 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
6523 | ||
6524 | /* M2 fraction division */ | |
a945ce7e VP |
6525 | if (bestm2_frac) |
6526 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); | |
9d556c99 CML |
6527 | |
6528 | /* M2 fraction division enable */ | |
a945ce7e VP |
6529 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
6530 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
6531 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
6532 | if (bestm2_frac) | |
6533 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
6534 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 6535 | |
de3a0fde VP |
6536 | /* Program digital lock detect threshold */ |
6537 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
6538 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
6539 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
6540 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
6541 | if (!bestm2_frac) | |
6542 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
6543 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
6544 | ||
9d556c99 | 6545 | /* Loop filter */ |
9cbe40c1 VP |
6546 | if (vco == 5400000) { |
6547 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6548 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
6549 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6550 | tribuf_calcntr = 0x9; | |
6551 | } else if (vco <= 6200000) { | |
6552 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6553 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
6554 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6555 | tribuf_calcntr = 0x9; | |
6556 | } else if (vco <= 6480000) { | |
6557 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6558 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
6559 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6560 | tribuf_calcntr = 0x8; | |
6561 | } else { | |
6562 | /* Not supported. Apply the same limits as in the max case */ | |
6563 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6564 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
6565 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6566 | tribuf_calcntr = 0; | |
6567 | } | |
9d556c99 CML |
6568 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
6569 | ||
968040b2 | 6570 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
6571 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
6572 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
6573 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
6574 | ||
9d556c99 CML |
6575 | /* AFC Recal */ |
6576 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
6577 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
6578 | DPIO_AFC_RECAL); | |
6579 | ||
6580 | mutex_unlock(&dev_priv->dpio_lock); | |
6581 | } | |
6582 | ||
d288f65f VS |
6583 | /** |
6584 | * vlv_force_pll_on - forcibly enable just the PLL | |
6585 | * @dev_priv: i915 private structure | |
6586 | * @pipe: pipe PLL to enable | |
6587 | * @dpll: PLL configuration | |
6588 | * | |
6589 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
6590 | * in cases where we need the PLL enabled even when @pipe is not going to | |
6591 | * be enabled. | |
6592 | */ | |
6593 | void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, | |
6594 | const struct dpll *dpll) | |
6595 | { | |
6596 | struct intel_crtc *crtc = | |
6597 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
5cec258b | 6598 | struct intel_crtc_state pipe_config = { |
a93e255f | 6599 | .base.crtc = &crtc->base, |
d288f65f VS |
6600 | .pixel_multiplier = 1, |
6601 | .dpll = *dpll, | |
6602 | }; | |
6603 | ||
6604 | if (IS_CHERRYVIEW(dev)) { | |
6605 | chv_update_pll(crtc, &pipe_config); | |
6606 | chv_prepare_pll(crtc, &pipe_config); | |
6607 | chv_enable_pll(crtc, &pipe_config); | |
6608 | } else { | |
6609 | vlv_update_pll(crtc, &pipe_config); | |
6610 | vlv_prepare_pll(crtc, &pipe_config); | |
6611 | vlv_enable_pll(crtc, &pipe_config); | |
6612 | } | |
6613 | } | |
6614 | ||
6615 | /** | |
6616 | * vlv_force_pll_off - forcibly disable just the PLL | |
6617 | * @dev_priv: i915 private structure | |
6618 | * @pipe: pipe PLL to disable | |
6619 | * | |
6620 | * Disable the PLL for @pipe. To be used in cases where we need | |
6621 | * the PLL enabled even when @pipe is not going to be enabled. | |
6622 | */ | |
6623 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
6624 | { | |
6625 | if (IS_CHERRYVIEW(dev)) | |
6626 | chv_disable_pll(to_i915(dev), pipe); | |
6627 | else | |
6628 | vlv_disable_pll(to_i915(dev), pipe); | |
6629 | } | |
6630 | ||
f47709a9 | 6631 | static void i9xx_update_pll(struct intel_crtc *crtc, |
190f68c5 | 6632 | struct intel_crtc_state *crtc_state, |
f47709a9 | 6633 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
6634 | int num_connectors) |
6635 | { | |
f47709a9 | 6636 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 6637 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
6638 | u32 dpll; |
6639 | bool is_sdvo; | |
190f68c5 | 6640 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 6641 | |
190f68c5 | 6642 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 6643 | |
a93e255f ACO |
6644 | is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) || |
6645 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
6646 | |
6647 | dpll = DPLL_VGA_MODE_DIS; | |
6648 | ||
a93e255f | 6649 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
6650 | dpll |= DPLLB_MODE_LVDS; |
6651 | else | |
6652 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 6653 | |
ef1b460d | 6654 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 6655 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 6656 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 6657 | } |
198a037f DV |
6658 | |
6659 | if (is_sdvo) | |
4a33e48d | 6660 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 6661 | |
190f68c5 | 6662 | if (crtc_state->has_dp_encoder) |
4a33e48d | 6663 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
6664 | |
6665 | /* compute bitmask from p1 value */ | |
6666 | if (IS_PINEVIEW(dev)) | |
6667 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
6668 | else { | |
6669 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
6670 | if (IS_G4X(dev) && reduced_clock) | |
6671 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
6672 | } | |
6673 | switch (clock->p2) { | |
6674 | case 5: | |
6675 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
6676 | break; | |
6677 | case 7: | |
6678 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
6679 | break; | |
6680 | case 10: | |
6681 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
6682 | break; | |
6683 | case 14: | |
6684 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
6685 | break; | |
6686 | } | |
6687 | if (INTEL_INFO(dev)->gen >= 4) | |
6688 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
6689 | ||
190f68c5 | 6690 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 6691 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
a93e255f | 6692 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
6693 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
6694 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
6695 | else | |
6696 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6697 | ||
6698 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 6699 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 6700 | |
eb1cbe48 | 6701 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 6702 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 6703 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 6704 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
6705 | } |
6706 | } | |
6707 | ||
f47709a9 | 6708 | static void i8xx_update_pll(struct intel_crtc *crtc, |
190f68c5 | 6709 | struct intel_crtc_state *crtc_state, |
f47709a9 | 6710 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
6711 | int num_connectors) |
6712 | { | |
f47709a9 | 6713 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 6714 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 6715 | u32 dpll; |
190f68c5 | 6716 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 6717 | |
190f68c5 | 6718 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 6719 | |
eb1cbe48 DV |
6720 | dpll = DPLL_VGA_MODE_DIS; |
6721 | ||
a93e255f | 6722 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
6723 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
6724 | } else { | |
6725 | if (clock->p1 == 2) | |
6726 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
6727 | else | |
6728 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
6729 | if (clock->p2 == 4) | |
6730 | dpll |= PLL_P2_DIVIDE_BY_4; | |
6731 | } | |
6732 | ||
a93e255f | 6733 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
6734 | dpll |= DPLL_DVO_2X_MODE; |
6735 | ||
a93e255f | 6736 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
6737 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
6738 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
6739 | else | |
6740 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6741 | ||
6742 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 6743 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
6744 | } |
6745 | ||
8a654f3b | 6746 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
6747 | { |
6748 | struct drm_device *dev = intel_crtc->base.dev; | |
6749 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6750 | enum pipe pipe = intel_crtc->pipe; | |
6e3c9717 | 6751 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
8a654f3b | 6752 | struct drm_display_mode *adjusted_mode = |
6e3c9717 | 6753 | &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
6754 | uint32_t crtc_vtotal, crtc_vblank_end; |
6755 | int vsyncshift = 0; | |
4d8a62ea DV |
6756 | |
6757 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
6758 | * the hw state checker will get angry at the mismatch. */ | |
6759 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
6760 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 6761 | |
609aeaca | 6762 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 6763 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
6764 | crtc_vtotal -= 1; |
6765 | crtc_vblank_end -= 1; | |
609aeaca | 6766 | |
409ee761 | 6767 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
6768 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
6769 | else | |
6770 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
6771 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
6772 | if (vsyncshift < 0) |
6773 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
6774 | } |
6775 | ||
6776 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 6777 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 6778 | |
fe2b8f9d | 6779 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
6780 | (adjusted_mode->crtc_hdisplay - 1) | |
6781 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 6782 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
6783 | (adjusted_mode->crtc_hblank_start - 1) | |
6784 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 6785 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
6786 | (adjusted_mode->crtc_hsync_start - 1) | |
6787 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
6788 | ||
fe2b8f9d | 6789 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 6790 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 6791 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 6792 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 6793 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 6794 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 6795 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
6796 | (adjusted_mode->crtc_vsync_start - 1) | |
6797 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
6798 | ||
b5e508d4 PZ |
6799 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
6800 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
6801 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
6802 | * bits. */ | |
6803 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
6804 | (pipe == PIPE_B || pipe == PIPE_C)) | |
6805 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
6806 | ||
b0e77b9c PZ |
6807 | /* pipesrc controls the size that is scaled from, which should |
6808 | * always be the user's requested size. | |
6809 | */ | |
6810 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
6811 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
6812 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
6813 | } |
6814 | ||
1bd1bd80 | 6815 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 6816 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
6817 | { |
6818 | struct drm_device *dev = crtc->base.dev; | |
6819 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6820 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
6821 | uint32_t tmp; | |
6822 | ||
6823 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
6824 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
6825 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6826 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
6827 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
6828 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6829 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
6830 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
6831 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
6832 | |
6833 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
6834 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
6835 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6836 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
6837 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
6838 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6839 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
6840 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
6841 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
6842 | |
6843 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
6844 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
6845 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
6846 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 DV |
6847 | } |
6848 | ||
6849 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
6850 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
6851 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
6852 | ||
2d112de7 ACO |
6853 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
6854 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
6855 | } |
6856 | ||
f6a83288 | 6857 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 6858 | struct intel_crtc_state *pipe_config) |
babea61d | 6859 | { |
2d112de7 ACO |
6860 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
6861 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
6862 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
6863 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 6864 | |
2d112de7 ACO |
6865 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
6866 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
6867 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
6868 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 6869 | |
2d112de7 | 6870 | mode->flags = pipe_config->base.adjusted_mode.flags; |
babea61d | 6871 | |
2d112de7 ACO |
6872 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
6873 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
babea61d JB |
6874 | } |
6875 | ||
84b046f3 DV |
6876 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
6877 | { | |
6878 | struct drm_device *dev = intel_crtc->base.dev; | |
6879 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6880 | uint32_t pipeconf; | |
6881 | ||
9f11a9e4 | 6882 | pipeconf = 0; |
84b046f3 | 6883 | |
b6b5d049 VS |
6884 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
6885 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
6886 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 6887 | |
6e3c9717 | 6888 | if (intel_crtc->config->double_wide) |
cf532bb2 | 6889 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 6890 | |
ff9ce46e DV |
6891 | /* only g4x and later have fancy bpc/dither controls */ |
6892 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
ff9ce46e | 6893 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 6894 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 6895 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 6896 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 6897 | |
6e3c9717 | 6898 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
6899 | case 18: |
6900 | pipeconf |= PIPECONF_6BPC; | |
6901 | break; | |
6902 | case 24: | |
6903 | pipeconf |= PIPECONF_8BPC; | |
6904 | break; | |
6905 | case 30: | |
6906 | pipeconf |= PIPECONF_10BPC; | |
6907 | break; | |
6908 | default: | |
6909 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
6910 | BUG(); | |
84b046f3 DV |
6911 | } |
6912 | } | |
6913 | ||
6914 | if (HAS_PIPE_CXSR(dev)) { | |
6915 | if (intel_crtc->lowfreq_avail) { | |
6916 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
6917 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
6918 | } else { | |
6919 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
6920 | } |
6921 | } | |
6922 | ||
6e3c9717 | 6923 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 6924 | if (INTEL_INFO(dev)->gen < 4 || |
409ee761 | 6925 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
6926 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
6927 | else | |
6928 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
6929 | } else | |
84b046f3 DV |
6930 | pipeconf |= PIPECONF_PROGRESSIVE; |
6931 | ||
6e3c9717 | 6932 | if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range) |
9f11a9e4 | 6933 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 6934 | |
84b046f3 DV |
6935 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
6936 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
6937 | } | |
6938 | ||
190f68c5 ACO |
6939 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
6940 | struct intel_crtc_state *crtc_state) | |
79e53945 | 6941 | { |
c7653199 | 6942 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 6943 | struct drm_i915_private *dev_priv = dev->dev_private; |
c751ce4f | 6944 | int refclk, num_connectors = 0; |
652c393a | 6945 | intel_clock_t clock, reduced_clock; |
a16af721 | 6946 | bool ok, has_reduced_clock = false; |
e9fd1c02 | 6947 | bool is_lvds = false, is_dsi = false; |
5eddb70b | 6948 | struct intel_encoder *encoder; |
d4906093 | 6949 | const intel_limit_t *limit; |
55bb9992 ACO |
6950 | struct drm_atomic_state *state = crtc_state->base.state; |
6951 | struct drm_connector_state *connector_state; | |
6952 | int i; | |
79e53945 | 6953 | |
55bb9992 ACO |
6954 | for (i = 0; i < state->num_connector; i++) { |
6955 | if (!state->connectors[i]) | |
d0737e1d ACO |
6956 | continue; |
6957 | ||
55bb9992 ACO |
6958 | connector_state = state->connector_states[i]; |
6959 | if (connector_state->crtc != &crtc->base) | |
6960 | continue; | |
6961 | ||
6962 | encoder = to_intel_encoder(connector_state->best_encoder); | |
6963 | ||
5eddb70b | 6964 | switch (encoder->type) { |
79e53945 JB |
6965 | case INTEL_OUTPUT_LVDS: |
6966 | is_lvds = true; | |
6967 | break; | |
e9fd1c02 JN |
6968 | case INTEL_OUTPUT_DSI: |
6969 | is_dsi = true; | |
6970 | break; | |
6847d71b PZ |
6971 | default: |
6972 | break; | |
79e53945 | 6973 | } |
43565a06 | 6974 | |
c751ce4f | 6975 | num_connectors++; |
79e53945 JB |
6976 | } |
6977 | ||
f2335330 | 6978 | if (is_dsi) |
5b18e57c | 6979 | return 0; |
f2335330 | 6980 | |
190f68c5 | 6981 | if (!crtc_state->clock_set) { |
a93e255f | 6982 | refclk = i9xx_get_refclk(crtc_state, num_connectors); |
79e53945 | 6983 | |
e9fd1c02 JN |
6984 | /* |
6985 | * Returns a set of divisors for the desired target clock with | |
6986 | * the given refclk, or FALSE. The returned values represent | |
6987 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
6988 | * 2) / p1 / p2. | |
6989 | */ | |
a93e255f ACO |
6990 | limit = intel_limit(crtc_state, refclk); |
6991 | ok = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 6992 | crtc_state->port_clock, |
e9fd1c02 | 6993 | refclk, NULL, &clock); |
f2335330 | 6994 | if (!ok) { |
e9fd1c02 JN |
6995 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
6996 | return -EINVAL; | |
6997 | } | |
79e53945 | 6998 | |
f2335330 JN |
6999 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
7000 | /* | |
7001 | * Ensure we match the reduced clock's P to the target | |
7002 | * clock. If the clocks don't match, we can't switch | |
7003 | * the display clock by using the FP0/FP1. In such case | |
7004 | * we will disable the LVDS downclock feature. | |
7005 | */ | |
7006 | has_reduced_clock = | |
a93e255f | 7007 | dev_priv->display.find_dpll(limit, crtc_state, |
f2335330 JN |
7008 | dev_priv->lvds_downclock, |
7009 | refclk, &clock, | |
7010 | &reduced_clock); | |
7011 | } | |
7012 | /* Compat-code for transition, will disappear. */ | |
190f68c5 ACO |
7013 | crtc_state->dpll.n = clock.n; |
7014 | crtc_state->dpll.m1 = clock.m1; | |
7015 | crtc_state->dpll.m2 = clock.m2; | |
7016 | crtc_state->dpll.p1 = clock.p1; | |
7017 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 7018 | } |
7026d4ac | 7019 | |
e9fd1c02 | 7020 | if (IS_GEN2(dev)) { |
190f68c5 | 7021 | i8xx_update_pll(crtc, crtc_state, |
2a8f64ca VP |
7022 | has_reduced_clock ? &reduced_clock : NULL, |
7023 | num_connectors); | |
9d556c99 | 7024 | } else if (IS_CHERRYVIEW(dev)) { |
190f68c5 | 7025 | chv_update_pll(crtc, crtc_state); |
e9fd1c02 | 7026 | } else if (IS_VALLEYVIEW(dev)) { |
190f68c5 | 7027 | vlv_update_pll(crtc, crtc_state); |
e9fd1c02 | 7028 | } else { |
190f68c5 | 7029 | i9xx_update_pll(crtc, crtc_state, |
eb1cbe48 | 7030 | has_reduced_clock ? &reduced_clock : NULL, |
eba905b2 | 7031 | num_connectors); |
e9fd1c02 | 7032 | } |
79e53945 | 7033 | |
c8f7a0db | 7034 | return 0; |
f564048e EA |
7035 | } |
7036 | ||
2fa2fe9a | 7037 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 7038 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
7039 | { |
7040 | struct drm_device *dev = crtc->base.dev; | |
7041 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7042 | uint32_t tmp; | |
7043 | ||
dc9e7dec VS |
7044 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
7045 | return; | |
7046 | ||
2fa2fe9a | 7047 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
7048 | if (!(tmp & PFIT_ENABLE)) |
7049 | return; | |
2fa2fe9a | 7050 | |
06922821 | 7051 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
7052 | if (INTEL_INFO(dev)->gen < 4) { |
7053 | if (crtc->pipe != PIPE_B) | |
7054 | return; | |
2fa2fe9a DV |
7055 | } else { |
7056 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
7057 | return; | |
7058 | } | |
7059 | ||
06922821 | 7060 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
7061 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
7062 | if (INTEL_INFO(dev)->gen < 5) | |
7063 | pipe_config->gmch_pfit.lvds_border_bits = | |
7064 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
7065 | } | |
7066 | ||
acbec814 | 7067 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7068 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
7069 | { |
7070 | struct drm_device *dev = crtc->base.dev; | |
7071 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7072 | int pipe = pipe_config->cpu_transcoder; | |
7073 | intel_clock_t clock; | |
7074 | u32 mdiv; | |
662c6ecb | 7075 | int refclk = 100000; |
acbec814 | 7076 | |
f573de5a SK |
7077 | /* In case of MIPI DPLL will not even be used */ |
7078 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) | |
7079 | return; | |
7080 | ||
acbec814 | 7081 | mutex_lock(&dev_priv->dpio_lock); |
ab3c759a | 7082 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
acbec814 JB |
7083 | mutex_unlock(&dev_priv->dpio_lock); |
7084 | ||
7085 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
7086 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
7087 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
7088 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
7089 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
7090 | ||
f646628b | 7091 | vlv_clock(refclk, &clock); |
acbec814 | 7092 | |
f646628b VS |
7093 | /* clock.dot is the fast clock */ |
7094 | pipe_config->port_clock = clock.dot / 5; | |
acbec814 JB |
7095 | } |
7096 | ||
5724dbd1 DL |
7097 | static void |
7098 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
7099 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
7100 | { |
7101 | struct drm_device *dev = crtc->base.dev; | |
7102 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7103 | u32 val, base, offset; | |
7104 | int pipe = crtc->pipe, plane = crtc->plane; | |
7105 | int fourcc, pixel_format; | |
6761dd31 | 7106 | unsigned int aligned_height; |
b113d5ee | 7107 | struct drm_framebuffer *fb; |
1b842c89 | 7108 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 7109 | |
42a7b088 DL |
7110 | val = I915_READ(DSPCNTR(plane)); |
7111 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
7112 | return; | |
7113 | ||
d9806c9f | 7114 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 7115 | if (!intel_fb) { |
1ad292b5 JB |
7116 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7117 | return; | |
7118 | } | |
7119 | ||
1b842c89 DL |
7120 | fb = &intel_fb->base; |
7121 | ||
18c5247e DV |
7122 | if (INTEL_INFO(dev)->gen >= 4) { |
7123 | if (val & DISPPLANE_TILED) { | |
49af449b | 7124 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
7125 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
7126 | } | |
7127 | } | |
1ad292b5 JB |
7128 | |
7129 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 7130 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
7131 | fb->pixel_format = fourcc; |
7132 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
7133 | |
7134 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 7135 | if (plane_config->tiling) |
1ad292b5 JB |
7136 | offset = I915_READ(DSPTILEOFF(plane)); |
7137 | else | |
7138 | offset = I915_READ(DSPLINOFF(plane)); | |
7139 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
7140 | } else { | |
7141 | base = I915_READ(DSPADDR(plane)); | |
7142 | } | |
7143 | plane_config->base = base; | |
7144 | ||
7145 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
7146 | fb->width = ((val >> 16) & 0xfff) + 1; |
7147 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
7148 | |
7149 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 7150 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 7151 | |
b113d5ee | 7152 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
7153 | fb->pixel_format, |
7154 | fb->modifier[0]); | |
1ad292b5 | 7155 | |
f37b5c2b | 7156 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 7157 | |
2844a921 DL |
7158 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
7159 | pipe_name(pipe), plane, fb->width, fb->height, | |
7160 | fb->bits_per_pixel, base, fb->pitches[0], | |
7161 | plane_config->size); | |
1ad292b5 | 7162 | |
2d14030b | 7163 | plane_config->fb = intel_fb; |
1ad292b5 JB |
7164 | } |
7165 | ||
70b23a98 | 7166 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7167 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
7168 | { |
7169 | struct drm_device *dev = crtc->base.dev; | |
7170 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7171 | int pipe = pipe_config->cpu_transcoder; | |
7172 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
7173 | intel_clock_t clock; | |
7174 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2; | |
7175 | int refclk = 100000; | |
7176 | ||
7177 | mutex_lock(&dev_priv->dpio_lock); | |
7178 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); | |
7179 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
7180 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
7181 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
7182 | mutex_unlock(&dev_priv->dpio_lock); | |
7183 | ||
7184 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
7185 | clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff); | |
7186 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; | |
7187 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
7188 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
7189 | ||
7190 | chv_clock(refclk, &clock); | |
7191 | ||
7192 | /* clock.dot is the fast clock */ | |
7193 | pipe_config->port_clock = clock.dot / 5; | |
7194 | } | |
7195 | ||
0e8ffe1b | 7196 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 7197 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
7198 | { |
7199 | struct drm_device *dev = crtc->base.dev; | |
7200 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7201 | uint32_t tmp; | |
7202 | ||
f458ebbc DV |
7203 | if (!intel_display_power_is_enabled(dev_priv, |
7204 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
b5482bd0 ID |
7205 | return false; |
7206 | ||
e143a21c | 7207 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 7208 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 7209 | |
0e8ffe1b DV |
7210 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
7211 | if (!(tmp & PIPECONF_ENABLE)) | |
7212 | return false; | |
7213 | ||
42571aef VS |
7214 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
7215 | switch (tmp & PIPECONF_BPC_MASK) { | |
7216 | case PIPECONF_6BPC: | |
7217 | pipe_config->pipe_bpp = 18; | |
7218 | break; | |
7219 | case PIPECONF_8BPC: | |
7220 | pipe_config->pipe_bpp = 24; | |
7221 | break; | |
7222 | case PIPECONF_10BPC: | |
7223 | pipe_config->pipe_bpp = 30; | |
7224 | break; | |
7225 | default: | |
7226 | break; | |
7227 | } | |
7228 | } | |
7229 | ||
b5a9fa09 DV |
7230 | if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
7231 | pipe_config->limited_color_range = true; | |
7232 | ||
282740f7 VS |
7233 | if (INTEL_INFO(dev)->gen < 4) |
7234 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
7235 | ||
1bd1bd80 DV |
7236 | intel_get_pipe_timings(crtc, pipe_config); |
7237 | ||
2fa2fe9a DV |
7238 | i9xx_get_pfit_config(crtc, pipe_config); |
7239 | ||
6c49f241 DV |
7240 | if (INTEL_INFO(dev)->gen >= 4) { |
7241 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
7242 | pipe_config->pixel_multiplier = | |
7243 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
7244 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 7245 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
7246 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
7247 | tmp = I915_READ(DPLL(crtc->pipe)); | |
7248 | pipe_config->pixel_multiplier = | |
7249 | ((tmp & SDVO_MULTIPLIER_MASK) | |
7250 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
7251 | } else { | |
7252 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
7253 | * port and will be fixed up in the encoder->get_config | |
7254 | * function. */ | |
7255 | pipe_config->pixel_multiplier = 1; | |
7256 | } | |
8bcc2795 DV |
7257 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
7258 | if (!IS_VALLEYVIEW(dev)) { | |
1c4e0274 VS |
7259 | /* |
7260 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
7261 | * on 830. Filter it out here so that we don't | |
7262 | * report errors due to that. | |
7263 | */ | |
7264 | if (IS_I830(dev)) | |
7265 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
7266 | ||
8bcc2795 DV |
7267 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
7268 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
7269 | } else { |
7270 | /* Mask out read-only status bits. */ | |
7271 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
7272 | DPLL_PORTC_READY_MASK | | |
7273 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 7274 | } |
6c49f241 | 7275 | |
70b23a98 VS |
7276 | if (IS_CHERRYVIEW(dev)) |
7277 | chv_crtc_clock_get(crtc, pipe_config); | |
7278 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
7279 | vlv_crtc_clock_get(crtc, pipe_config); |
7280 | else | |
7281 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 7282 | |
0e8ffe1b DV |
7283 | return true; |
7284 | } | |
7285 | ||
dde86e2d | 7286 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
7287 | { |
7288 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 7289 | struct intel_encoder *encoder; |
74cfd7ac | 7290 | u32 val, final; |
13d83a67 | 7291 | bool has_lvds = false; |
199e5d79 | 7292 | bool has_cpu_edp = false; |
199e5d79 | 7293 | bool has_panel = false; |
99eb6a01 KP |
7294 | bool has_ck505 = false; |
7295 | bool can_ssc = false; | |
13d83a67 JB |
7296 | |
7297 | /* We need to take the global config into account */ | |
b2784e15 | 7298 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
7299 | switch (encoder->type) { |
7300 | case INTEL_OUTPUT_LVDS: | |
7301 | has_panel = true; | |
7302 | has_lvds = true; | |
7303 | break; | |
7304 | case INTEL_OUTPUT_EDP: | |
7305 | has_panel = true; | |
2de6905f | 7306 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
7307 | has_cpu_edp = true; |
7308 | break; | |
6847d71b PZ |
7309 | default: |
7310 | break; | |
13d83a67 JB |
7311 | } |
7312 | } | |
7313 | ||
99eb6a01 | 7314 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 7315 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
7316 | can_ssc = has_ck505; |
7317 | } else { | |
7318 | has_ck505 = false; | |
7319 | can_ssc = true; | |
7320 | } | |
7321 | ||
2de6905f ID |
7322 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
7323 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
7324 | |
7325 | /* Ironlake: try to setup display ref clock before DPLL | |
7326 | * enabling. This is only under driver's control after | |
7327 | * PCH B stepping, previous chipset stepping should be | |
7328 | * ignoring this setting. | |
7329 | */ | |
74cfd7ac CW |
7330 | val = I915_READ(PCH_DREF_CONTROL); |
7331 | ||
7332 | /* As we must carefully and slowly disable/enable each source in turn, | |
7333 | * compute the final state we want first and check if we need to | |
7334 | * make any changes at all. | |
7335 | */ | |
7336 | final = val; | |
7337 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
7338 | if (has_ck505) | |
7339 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
7340 | else | |
7341 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
7342 | ||
7343 | final &= ~DREF_SSC_SOURCE_MASK; | |
7344 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
7345 | final &= ~DREF_SSC1_ENABLE; | |
7346 | ||
7347 | if (has_panel) { | |
7348 | final |= DREF_SSC_SOURCE_ENABLE; | |
7349 | ||
7350 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
7351 | final |= DREF_SSC1_ENABLE; | |
7352 | ||
7353 | if (has_cpu_edp) { | |
7354 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
7355 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
7356 | else | |
7357 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
7358 | } else | |
7359 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
7360 | } else { | |
7361 | final |= DREF_SSC_SOURCE_DISABLE; | |
7362 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
7363 | } | |
7364 | ||
7365 | if (final == val) | |
7366 | return; | |
7367 | ||
13d83a67 | 7368 | /* Always enable nonspread source */ |
74cfd7ac | 7369 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 7370 | |
99eb6a01 | 7371 | if (has_ck505) |
74cfd7ac | 7372 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 7373 | else |
74cfd7ac | 7374 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 7375 | |
199e5d79 | 7376 | if (has_panel) { |
74cfd7ac CW |
7377 | val &= ~DREF_SSC_SOURCE_MASK; |
7378 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 7379 | |
199e5d79 | 7380 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 7381 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 7382 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 7383 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 7384 | } else |
74cfd7ac | 7385 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
7386 | |
7387 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 7388 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7389 | POSTING_READ(PCH_DREF_CONTROL); |
7390 | udelay(200); | |
7391 | ||
74cfd7ac | 7392 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
7393 | |
7394 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 7395 | if (has_cpu_edp) { |
99eb6a01 | 7396 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 7397 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 7398 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 7399 | } else |
74cfd7ac | 7400 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 7401 | } else |
74cfd7ac | 7402 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7403 | |
74cfd7ac | 7404 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7405 | POSTING_READ(PCH_DREF_CONTROL); |
7406 | udelay(200); | |
7407 | } else { | |
7408 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
7409 | ||
74cfd7ac | 7410 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
7411 | |
7412 | /* Turn off CPU output */ | |
74cfd7ac | 7413 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7414 | |
74cfd7ac | 7415 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7416 | POSTING_READ(PCH_DREF_CONTROL); |
7417 | udelay(200); | |
7418 | ||
7419 | /* Turn off the SSC source */ | |
74cfd7ac CW |
7420 | val &= ~DREF_SSC_SOURCE_MASK; |
7421 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
7422 | |
7423 | /* Turn off SSC1 */ | |
74cfd7ac | 7424 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 7425 | |
74cfd7ac | 7426 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
7427 | POSTING_READ(PCH_DREF_CONTROL); |
7428 | udelay(200); | |
7429 | } | |
74cfd7ac CW |
7430 | |
7431 | BUG_ON(val != final); | |
13d83a67 JB |
7432 | } |
7433 | ||
f31f2d55 | 7434 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 7435 | { |
f31f2d55 | 7436 | uint32_t tmp; |
dde86e2d | 7437 | |
0ff066a9 PZ |
7438 | tmp = I915_READ(SOUTH_CHICKEN2); |
7439 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
7440 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7441 | |
0ff066a9 PZ |
7442 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
7443 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
7444 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 7445 | |
0ff066a9 PZ |
7446 | tmp = I915_READ(SOUTH_CHICKEN2); |
7447 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
7448 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7449 | |
0ff066a9 PZ |
7450 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
7451 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
7452 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
7453 | } |
7454 | ||
7455 | /* WaMPhyProgramming:hsw */ | |
7456 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
7457 | { | |
7458 | uint32_t tmp; | |
dde86e2d PZ |
7459 | |
7460 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
7461 | tmp &= ~(0xFF << 24); | |
7462 | tmp |= (0x12 << 24); | |
7463 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
7464 | ||
dde86e2d PZ |
7465 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
7466 | tmp |= (1 << 11); | |
7467 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
7468 | ||
7469 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
7470 | tmp |= (1 << 11); | |
7471 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
7472 | ||
dde86e2d PZ |
7473 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
7474 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7475 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
7476 | ||
7477 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
7478 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7479 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
7480 | ||
0ff066a9 PZ |
7481 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
7482 | tmp &= ~(7 << 13); | |
7483 | tmp |= (5 << 13); | |
7484 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 7485 | |
0ff066a9 PZ |
7486 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
7487 | tmp &= ~(7 << 13); | |
7488 | tmp |= (5 << 13); | |
7489 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
7490 | |
7491 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
7492 | tmp &= ~0xFF; | |
7493 | tmp |= 0x1C; | |
7494 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
7495 | ||
7496 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
7497 | tmp &= ~0xFF; | |
7498 | tmp |= 0x1C; | |
7499 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
7500 | ||
7501 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
7502 | tmp &= ~(0xFF << 16); | |
7503 | tmp |= (0x1C << 16); | |
7504 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
7505 | ||
7506 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
7507 | tmp &= ~(0xFF << 16); | |
7508 | tmp |= (0x1C << 16); | |
7509 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
7510 | ||
0ff066a9 PZ |
7511 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
7512 | tmp |= (1 << 27); | |
7513 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 7514 | |
0ff066a9 PZ |
7515 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
7516 | tmp |= (1 << 27); | |
7517 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 7518 | |
0ff066a9 PZ |
7519 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
7520 | tmp &= ~(0xF << 28); | |
7521 | tmp |= (4 << 28); | |
7522 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 7523 | |
0ff066a9 PZ |
7524 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
7525 | tmp &= ~(0xF << 28); | |
7526 | tmp |= (4 << 28); | |
7527 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
7528 | } |
7529 | ||
2fa86a1f PZ |
7530 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
7531 | * Programming" based on the parameters passed: | |
7532 | * - Sequence to enable CLKOUT_DP | |
7533 | * - Sequence to enable CLKOUT_DP without spread | |
7534 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
7535 | */ | |
7536 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
7537 | bool with_fdi) | |
f31f2d55 PZ |
7538 | { |
7539 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
7540 | uint32_t reg, tmp; |
7541 | ||
7542 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
7543 | with_spread = true; | |
7544 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && | |
7545 | with_fdi, "LP PCH doesn't have FDI\n")) | |
7546 | with_fdi = false; | |
f31f2d55 PZ |
7547 | |
7548 | mutex_lock(&dev_priv->dpio_lock); | |
7549 | ||
7550 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7551 | tmp &= ~SBI_SSCCTL_DISABLE; | |
7552 | tmp |= SBI_SSCCTL_PATHALT; | |
7553 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7554 | ||
7555 | udelay(24); | |
7556 | ||
2fa86a1f PZ |
7557 | if (with_spread) { |
7558 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7559 | tmp &= ~SBI_SSCCTL_PATHALT; | |
7560 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 7561 | |
2fa86a1f PZ |
7562 | if (with_fdi) { |
7563 | lpt_reset_fdi_mphy(dev_priv); | |
7564 | lpt_program_fdi_mphy(dev_priv); | |
7565 | } | |
7566 | } | |
dde86e2d | 7567 | |
2fa86a1f PZ |
7568 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
7569 | SBI_GEN0 : SBI_DBUFF0; | |
7570 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
7571 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
7572 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 DV |
7573 | |
7574 | mutex_unlock(&dev_priv->dpio_lock); | |
dde86e2d PZ |
7575 | } |
7576 | ||
47701c3b PZ |
7577 | /* Sequence to disable CLKOUT_DP */ |
7578 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
7579 | { | |
7580 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7581 | uint32_t reg, tmp; | |
7582 | ||
7583 | mutex_lock(&dev_priv->dpio_lock); | |
7584 | ||
7585 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? | |
7586 | SBI_GEN0 : SBI_DBUFF0; | |
7587 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
7588 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
7589 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
7590 | ||
7591 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7592 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
7593 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
7594 | tmp |= SBI_SSCCTL_PATHALT; | |
7595 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7596 | udelay(32); | |
7597 | } | |
7598 | tmp |= SBI_SSCCTL_DISABLE; | |
7599 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7600 | } | |
7601 | ||
7602 | mutex_unlock(&dev_priv->dpio_lock); | |
7603 | } | |
7604 | ||
bf8fa3d3 PZ |
7605 | static void lpt_init_pch_refclk(struct drm_device *dev) |
7606 | { | |
bf8fa3d3 PZ |
7607 | struct intel_encoder *encoder; |
7608 | bool has_vga = false; | |
7609 | ||
b2784e15 | 7610 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
7611 | switch (encoder->type) { |
7612 | case INTEL_OUTPUT_ANALOG: | |
7613 | has_vga = true; | |
7614 | break; | |
6847d71b PZ |
7615 | default: |
7616 | break; | |
bf8fa3d3 PZ |
7617 | } |
7618 | } | |
7619 | ||
47701c3b PZ |
7620 | if (has_vga) |
7621 | lpt_enable_clkout_dp(dev, true, true); | |
7622 | else | |
7623 | lpt_disable_clkout_dp(dev); | |
bf8fa3d3 PZ |
7624 | } |
7625 | ||
dde86e2d PZ |
7626 | /* |
7627 | * Initialize reference clocks when the driver loads | |
7628 | */ | |
7629 | void intel_init_pch_refclk(struct drm_device *dev) | |
7630 | { | |
7631 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7632 | ironlake_init_pch_refclk(dev); | |
7633 | else if (HAS_PCH_LPT(dev)) | |
7634 | lpt_init_pch_refclk(dev); | |
7635 | } | |
7636 | ||
55bb9992 | 7637 | static int ironlake_get_refclk(struct intel_crtc_state *crtc_state) |
d9d444cb | 7638 | { |
55bb9992 | 7639 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d9d444cb | 7640 | struct drm_i915_private *dev_priv = dev->dev_private; |
55bb9992 ACO |
7641 | struct drm_atomic_state *state = crtc_state->base.state; |
7642 | struct drm_connector_state *connector_state; | |
d9d444cb | 7643 | struct intel_encoder *encoder; |
55bb9992 | 7644 | int num_connectors = 0, i; |
d9d444cb JB |
7645 | bool is_lvds = false; |
7646 | ||
55bb9992 ACO |
7647 | for (i = 0; i < state->num_connector; i++) { |
7648 | if (!state->connectors[i]) | |
d0737e1d ACO |
7649 | continue; |
7650 | ||
55bb9992 ACO |
7651 | connector_state = state->connector_states[i]; |
7652 | if (connector_state->crtc != crtc_state->base.crtc) | |
7653 | continue; | |
7654 | ||
7655 | encoder = to_intel_encoder(connector_state->best_encoder); | |
7656 | ||
d9d444cb JB |
7657 | switch (encoder->type) { |
7658 | case INTEL_OUTPUT_LVDS: | |
7659 | is_lvds = true; | |
7660 | break; | |
6847d71b PZ |
7661 | default: |
7662 | break; | |
d9d444cb JB |
7663 | } |
7664 | num_connectors++; | |
7665 | } | |
7666 | ||
7667 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 7668 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 7669 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 7670 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
7671 | } |
7672 | ||
7673 | return 120000; | |
7674 | } | |
7675 | ||
6ff93609 | 7676 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 7677 | { |
c8203565 | 7678 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
7679 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7680 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
7681 | uint32_t val; |
7682 | ||
78114071 | 7683 | val = 0; |
c8203565 | 7684 | |
6e3c9717 | 7685 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 7686 | case 18: |
dfd07d72 | 7687 | val |= PIPECONF_6BPC; |
c8203565 PZ |
7688 | break; |
7689 | case 24: | |
dfd07d72 | 7690 | val |= PIPECONF_8BPC; |
c8203565 PZ |
7691 | break; |
7692 | case 30: | |
dfd07d72 | 7693 | val |= PIPECONF_10BPC; |
c8203565 PZ |
7694 | break; |
7695 | case 36: | |
dfd07d72 | 7696 | val |= PIPECONF_12BPC; |
c8203565 PZ |
7697 | break; |
7698 | default: | |
cc769b62 PZ |
7699 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
7700 | BUG(); | |
c8203565 PZ |
7701 | } |
7702 | ||
6e3c9717 | 7703 | if (intel_crtc->config->dither) |
c8203565 PZ |
7704 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
7705 | ||
6e3c9717 | 7706 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
7707 | val |= PIPECONF_INTERLACED_ILK; |
7708 | else | |
7709 | val |= PIPECONF_PROGRESSIVE; | |
7710 | ||
6e3c9717 | 7711 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 7712 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 7713 | |
c8203565 PZ |
7714 | I915_WRITE(PIPECONF(pipe), val); |
7715 | POSTING_READ(PIPECONF(pipe)); | |
7716 | } | |
7717 | ||
86d3efce VS |
7718 | /* |
7719 | * Set up the pipe CSC unit. | |
7720 | * | |
7721 | * Currently only full range RGB to limited range RGB conversion | |
7722 | * is supported, but eventually this should handle various | |
7723 | * RGB<->YCbCr scenarios as well. | |
7724 | */ | |
50f3b016 | 7725 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
7726 | { |
7727 | struct drm_device *dev = crtc->dev; | |
7728 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7729 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7730 | int pipe = intel_crtc->pipe; | |
7731 | uint16_t coeff = 0x7800; /* 1.0 */ | |
7732 | ||
7733 | /* | |
7734 | * TODO: Check what kind of values actually come out of the pipe | |
7735 | * with these coeff/postoff values and adjust to get the best | |
7736 | * accuracy. Perhaps we even need to take the bpc value into | |
7737 | * consideration. | |
7738 | */ | |
7739 | ||
6e3c9717 | 7740 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
7741 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
7742 | ||
7743 | /* | |
7744 | * GY/GU and RY/RU should be the other way around according | |
7745 | * to BSpec, but reality doesn't agree. Just set them up in | |
7746 | * a way that results in the correct picture. | |
7747 | */ | |
7748 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
7749 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
7750 | ||
7751 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
7752 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
7753 | ||
7754 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
7755 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
7756 | ||
7757 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
7758 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
7759 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
7760 | ||
7761 | if (INTEL_INFO(dev)->gen > 6) { | |
7762 | uint16_t postoff = 0; | |
7763 | ||
6e3c9717 | 7764 | if (intel_crtc->config->limited_color_range) |
32cf0cb0 | 7765 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
7766 | |
7767 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
7768 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
7769 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
7770 | ||
7771 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
7772 | } else { | |
7773 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
7774 | ||
6e3c9717 | 7775 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
7776 | mode |= CSC_BLACK_SCREEN_OFFSET; |
7777 | ||
7778 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
7779 | } | |
7780 | } | |
7781 | ||
6ff93609 | 7782 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 7783 | { |
756f85cf PZ |
7784 | struct drm_device *dev = crtc->dev; |
7785 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 7786 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 7787 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 7788 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee2b0b38 PZ |
7789 | uint32_t val; |
7790 | ||
3eff4faa | 7791 | val = 0; |
ee2b0b38 | 7792 | |
6e3c9717 | 7793 | if (IS_HASWELL(dev) && intel_crtc->config->dither) |
ee2b0b38 PZ |
7794 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
7795 | ||
6e3c9717 | 7796 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
7797 | val |= PIPECONF_INTERLACED_ILK; |
7798 | else | |
7799 | val |= PIPECONF_PROGRESSIVE; | |
7800 | ||
702e7a56 PZ |
7801 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
7802 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
7803 | |
7804 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
7805 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf | 7806 | |
3cdf122c | 7807 | if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { |
756f85cf PZ |
7808 | val = 0; |
7809 | ||
6e3c9717 | 7810 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
7811 | case 18: |
7812 | val |= PIPEMISC_DITHER_6_BPC; | |
7813 | break; | |
7814 | case 24: | |
7815 | val |= PIPEMISC_DITHER_8_BPC; | |
7816 | break; | |
7817 | case 30: | |
7818 | val |= PIPEMISC_DITHER_10_BPC; | |
7819 | break; | |
7820 | case 36: | |
7821 | val |= PIPEMISC_DITHER_12_BPC; | |
7822 | break; | |
7823 | default: | |
7824 | /* Case prevented by pipe_config_set_bpp. */ | |
7825 | BUG(); | |
7826 | } | |
7827 | ||
6e3c9717 | 7828 | if (intel_crtc->config->dither) |
756f85cf PZ |
7829 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
7830 | ||
7831 | I915_WRITE(PIPEMISC(pipe), val); | |
7832 | } | |
ee2b0b38 PZ |
7833 | } |
7834 | ||
6591c6e4 | 7835 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
190f68c5 | 7836 | struct intel_crtc_state *crtc_state, |
6591c6e4 PZ |
7837 | intel_clock_t *clock, |
7838 | bool *has_reduced_clock, | |
7839 | intel_clock_t *reduced_clock) | |
7840 | { | |
7841 | struct drm_device *dev = crtc->dev; | |
7842 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6591c6e4 | 7843 | int refclk; |
d4906093 | 7844 | const intel_limit_t *limit; |
a16af721 | 7845 | bool ret, is_lvds = false; |
79e53945 | 7846 | |
a93e255f | 7847 | is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS); |
79e53945 | 7848 | |
55bb9992 | 7849 | refclk = ironlake_get_refclk(crtc_state); |
79e53945 | 7850 | |
d4906093 ML |
7851 | /* |
7852 | * Returns a set of divisors for the desired target clock with the given | |
7853 | * refclk, or FALSE. The returned values represent the clock equation: | |
7854 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
7855 | */ | |
a93e255f ACO |
7856 | limit = intel_limit(crtc_state, refclk); |
7857 | ret = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 7858 | crtc_state->port_clock, |
ee9300bb | 7859 | refclk, NULL, clock); |
6591c6e4 PZ |
7860 | if (!ret) |
7861 | return false; | |
cda4b7d3 | 7862 | |
ddc9003c | 7863 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
7864 | /* |
7865 | * Ensure we match the reduced clock's P to the target clock. | |
7866 | * If the clocks don't match, we can't switch the display clock | |
7867 | * by using the FP0/FP1. In such case we will disable the LVDS | |
7868 | * downclock feature. | |
7869 | */ | |
ee9300bb | 7870 | *has_reduced_clock = |
a93e255f | 7871 | dev_priv->display.find_dpll(limit, crtc_state, |
ee9300bb DV |
7872 | dev_priv->lvds_downclock, |
7873 | refclk, clock, | |
7874 | reduced_clock); | |
652c393a | 7875 | } |
61e9653f | 7876 | |
6591c6e4 PZ |
7877 | return true; |
7878 | } | |
7879 | ||
d4b1931c PZ |
7880 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
7881 | { | |
7882 | /* | |
7883 | * Account for spread spectrum to avoid | |
7884 | * oversubscribing the link. Max center spread | |
7885 | * is 2.5%; use 5% for safety's sake. | |
7886 | */ | |
7887 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 7888 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
7889 | } |
7890 | ||
7429e9d4 | 7891 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 7892 | { |
7429e9d4 | 7893 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
7894 | } |
7895 | ||
de13a2e3 | 7896 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
190f68c5 | 7897 | struct intel_crtc_state *crtc_state, |
7429e9d4 | 7898 | u32 *fp, |
9a7c7890 | 7899 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 7900 | { |
de13a2e3 | 7901 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
7902 | struct drm_device *dev = crtc->dev; |
7903 | struct drm_i915_private *dev_priv = dev->dev_private; | |
55bb9992 ACO |
7904 | struct drm_atomic_state *state = crtc_state->base.state; |
7905 | struct drm_connector_state *connector_state; | |
7906 | struct intel_encoder *encoder; | |
de13a2e3 | 7907 | uint32_t dpll; |
55bb9992 | 7908 | int factor, num_connectors = 0, i; |
09ede541 | 7909 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 7910 | |
55bb9992 ACO |
7911 | for (i = 0; i < state->num_connector; i++) { |
7912 | if (!state->connectors[i]) | |
d0737e1d ACO |
7913 | continue; |
7914 | ||
55bb9992 ACO |
7915 | connector_state = state->connector_states[i]; |
7916 | if (connector_state->crtc != crtc_state->base.crtc) | |
7917 | continue; | |
7918 | ||
7919 | encoder = to_intel_encoder(connector_state->best_encoder); | |
7920 | ||
7921 | switch (encoder->type) { | |
79e53945 JB |
7922 | case INTEL_OUTPUT_LVDS: |
7923 | is_lvds = true; | |
7924 | break; | |
7925 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 7926 | case INTEL_OUTPUT_HDMI: |
79e53945 | 7927 | is_sdvo = true; |
79e53945 | 7928 | break; |
6847d71b PZ |
7929 | default: |
7930 | break; | |
79e53945 | 7931 | } |
43565a06 | 7932 | |
c751ce4f | 7933 | num_connectors++; |
79e53945 | 7934 | } |
79e53945 | 7935 | |
c1858123 | 7936 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
7937 | factor = 21; |
7938 | if (is_lvds) { | |
7939 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 7940 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 7941 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 7942 | factor = 25; |
190f68c5 | 7943 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 7944 | factor = 20; |
c1858123 | 7945 | |
190f68c5 | 7946 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
7d0ac5b7 | 7947 | *fp |= FP_CB_TUNE; |
2c07245f | 7948 | |
9a7c7890 DV |
7949 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
7950 | *fp2 |= FP_CB_TUNE; | |
7951 | ||
5eddb70b | 7952 | dpll = 0; |
2c07245f | 7953 | |
a07d6787 EA |
7954 | if (is_lvds) |
7955 | dpll |= DPLLB_MODE_LVDS; | |
7956 | else | |
7957 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 7958 | |
190f68c5 | 7959 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7960 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f DV |
7961 | |
7962 | if (is_sdvo) | |
4a33e48d | 7963 | dpll |= DPLL_SDVO_HIGH_SPEED; |
190f68c5 | 7964 | if (crtc_state->has_dp_encoder) |
4a33e48d | 7965 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 7966 | |
a07d6787 | 7967 | /* compute bitmask from p1 value */ |
190f68c5 | 7968 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 7969 | /* also FPA1 */ |
190f68c5 | 7970 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 7971 | |
190f68c5 | 7972 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
7973 | case 5: |
7974 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7975 | break; | |
7976 | case 7: | |
7977 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7978 | break; | |
7979 | case 10: | |
7980 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7981 | break; | |
7982 | case 14: | |
7983 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7984 | break; | |
79e53945 JB |
7985 | } |
7986 | ||
b4c09f3b | 7987 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 7988 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
7989 | else |
7990 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7991 | ||
959e16d6 | 7992 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
7993 | } |
7994 | ||
190f68c5 ACO |
7995 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
7996 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 7997 | { |
c7653199 | 7998 | struct drm_device *dev = crtc->base.dev; |
de13a2e3 | 7999 | intel_clock_t clock, reduced_clock; |
cbbab5bd | 8000 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 8001 | bool ok, has_reduced_clock = false; |
8b47047b | 8002 | bool is_lvds = false; |
e2b78267 | 8003 | struct intel_shared_dpll *pll; |
de13a2e3 | 8004 | |
409ee761 | 8005 | is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS); |
79e53945 | 8006 | |
5dc5298b PZ |
8007 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
8008 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 8009 | |
190f68c5 | 8010 | ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock, |
de13a2e3 | 8011 | &has_reduced_clock, &reduced_clock); |
190f68c5 | 8012 | if (!ok && !crtc_state->clock_set) { |
de13a2e3 PZ |
8013 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
8014 | return -EINVAL; | |
79e53945 | 8015 | } |
f47709a9 | 8016 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
8017 | if (!crtc_state->clock_set) { |
8018 | crtc_state->dpll.n = clock.n; | |
8019 | crtc_state->dpll.m1 = clock.m1; | |
8020 | crtc_state->dpll.m2 = clock.m2; | |
8021 | crtc_state->dpll.p1 = clock.p1; | |
8022 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 8023 | } |
79e53945 | 8024 | |
5dc5298b | 8025 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
190f68c5 ACO |
8026 | if (crtc_state->has_pch_encoder) { |
8027 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); | |
cbbab5bd | 8028 | if (has_reduced_clock) |
7429e9d4 | 8029 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 8030 | |
190f68c5 | 8031 | dpll = ironlake_compute_dpll(crtc, crtc_state, |
cbbab5bd DV |
8032 | &fp, &reduced_clock, |
8033 | has_reduced_clock ? &fp2 : NULL); | |
8034 | ||
190f68c5 ACO |
8035 | crtc_state->dpll_hw_state.dpll = dpll; |
8036 | crtc_state->dpll_hw_state.fp0 = fp; | |
66e985c0 | 8037 | if (has_reduced_clock) |
190f68c5 | 8038 | crtc_state->dpll_hw_state.fp1 = fp2; |
66e985c0 | 8039 | else |
190f68c5 | 8040 | crtc_state->dpll_hw_state.fp1 = fp; |
66e985c0 | 8041 | |
190f68c5 | 8042 | pll = intel_get_shared_dpll(crtc, crtc_state); |
ee7b9f93 | 8043 | if (pll == NULL) { |
84f44ce7 | 8044 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
c7653199 | 8045 | pipe_name(crtc->pipe)); |
4b645f14 JB |
8046 | return -EINVAL; |
8047 | } | |
3fb37703 | 8048 | } |
79e53945 | 8049 | |
ab585dea | 8050 | if (is_lvds && has_reduced_clock) |
c7653199 | 8051 | crtc->lowfreq_avail = true; |
bcd644e0 | 8052 | else |
c7653199 | 8053 | crtc->lowfreq_avail = false; |
e2b78267 | 8054 | |
c8f7a0db | 8055 | return 0; |
79e53945 JB |
8056 | } |
8057 | ||
eb14cb74 VS |
8058 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
8059 | struct intel_link_m_n *m_n) | |
8060 | { | |
8061 | struct drm_device *dev = crtc->base.dev; | |
8062 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8063 | enum pipe pipe = crtc->pipe; | |
8064 | ||
8065 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
8066 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
8067 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8068 | & ~TU_SIZE_MASK; | |
8069 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
8070 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8071 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8072 | } | |
8073 | ||
8074 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
8075 | enum transcoder transcoder, | |
b95af8be VK |
8076 | struct intel_link_m_n *m_n, |
8077 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
8078 | { |
8079 | struct drm_device *dev = crtc->base.dev; | |
8080 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 8081 | enum pipe pipe = crtc->pipe; |
72419203 | 8082 | |
eb14cb74 VS |
8083 | if (INTEL_INFO(dev)->gen >= 5) { |
8084 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
8085 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
8086 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
8087 | & ~TU_SIZE_MASK; | |
8088 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
8089 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
8090 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
8091 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
8092 | * gen < 8) and if DRRS is supported (to make sure the | |
8093 | * registers are not unnecessarily read). | |
8094 | */ | |
8095 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 8096 | crtc->config->has_drrs) { |
b95af8be VK |
8097 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
8098 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
8099 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
8100 | & ~TU_SIZE_MASK; | |
8101 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
8102 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
8103 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8104 | } | |
eb14cb74 VS |
8105 | } else { |
8106 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
8107 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
8108 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8109 | & ~TU_SIZE_MASK; | |
8110 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
8111 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8112 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8113 | } | |
8114 | } | |
8115 | ||
8116 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 8117 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 8118 | { |
681a8504 | 8119 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
8120 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
8121 | else | |
8122 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
8123 | &pipe_config->dp_m_n, |
8124 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 8125 | } |
72419203 | 8126 | |
eb14cb74 | 8127 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 8128 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
8129 | { |
8130 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 8131 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
8132 | } |
8133 | ||
bd2e244f | 8134 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8135 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
8136 | { |
8137 | struct drm_device *dev = crtc->base.dev; | |
8138 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8139 | uint32_t tmp; | |
8140 | ||
8141 | tmp = I915_READ(PS_CTL(crtc->pipe)); | |
8142 | ||
8143 | if (tmp & PS_ENABLE) { | |
8144 | pipe_config->pch_pfit.enabled = true; | |
8145 | pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe)); | |
8146 | pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe)); | |
8147 | } | |
8148 | } | |
8149 | ||
5724dbd1 DL |
8150 | static void |
8151 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
8152 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
8153 | { |
8154 | struct drm_device *dev = crtc->base.dev; | |
8155 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40f46283 | 8156 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
8157 | int pipe = crtc->pipe; |
8158 | int fourcc, pixel_format; | |
6761dd31 | 8159 | unsigned int aligned_height; |
bc8d7dff | 8160 | struct drm_framebuffer *fb; |
1b842c89 | 8161 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 8162 | |
d9806c9f | 8163 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8164 | if (!intel_fb) { |
bc8d7dff DL |
8165 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8166 | return; | |
8167 | } | |
8168 | ||
1b842c89 DL |
8169 | fb = &intel_fb->base; |
8170 | ||
bc8d7dff | 8171 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
8172 | if (!(val & PLANE_CTL_ENABLE)) |
8173 | goto error; | |
8174 | ||
bc8d7dff DL |
8175 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
8176 | fourcc = skl_format_to_fourcc(pixel_format, | |
8177 | val & PLANE_CTL_ORDER_RGBX, | |
8178 | val & PLANE_CTL_ALPHA_MASK); | |
8179 | fb->pixel_format = fourcc; | |
8180 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
8181 | ||
40f46283 DL |
8182 | tiling = val & PLANE_CTL_TILED_MASK; |
8183 | switch (tiling) { | |
8184 | case PLANE_CTL_TILED_LINEAR: | |
8185 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
8186 | break; | |
8187 | case PLANE_CTL_TILED_X: | |
8188 | plane_config->tiling = I915_TILING_X; | |
8189 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
8190 | break; | |
8191 | case PLANE_CTL_TILED_Y: | |
8192 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
8193 | break; | |
8194 | case PLANE_CTL_TILED_YF: | |
8195 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
8196 | break; | |
8197 | default: | |
8198 | MISSING_CASE(tiling); | |
8199 | goto error; | |
8200 | } | |
8201 | ||
bc8d7dff DL |
8202 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
8203 | plane_config->base = base; | |
8204 | ||
8205 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
8206 | ||
8207 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
8208 | fb->height = ((val >> 16) & 0xfff) + 1; | |
8209 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
8210 | ||
8211 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
40f46283 DL |
8212 | stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0], |
8213 | fb->pixel_format); | |
bc8d7dff DL |
8214 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
8215 | ||
8216 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
8217 | fb->pixel_format, |
8218 | fb->modifier[0]); | |
bc8d7dff | 8219 | |
f37b5c2b | 8220 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
8221 | |
8222 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
8223 | pipe_name(pipe), fb->width, fb->height, | |
8224 | fb->bits_per_pixel, base, fb->pitches[0], | |
8225 | plane_config->size); | |
8226 | ||
2d14030b | 8227 | plane_config->fb = intel_fb; |
bc8d7dff DL |
8228 | return; |
8229 | ||
8230 | error: | |
8231 | kfree(fb); | |
8232 | } | |
8233 | ||
2fa2fe9a | 8234 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8235 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
8236 | { |
8237 | struct drm_device *dev = crtc->base.dev; | |
8238 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8239 | uint32_t tmp; | |
8240 | ||
8241 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
8242 | ||
8243 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 8244 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
8245 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
8246 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
8247 | |
8248 | /* We currently do not free assignements of panel fitters on | |
8249 | * ivb/hsw (since we don't use the higher upscaling modes which | |
8250 | * differentiates them) so just WARN about this case for now. */ | |
8251 | if (IS_GEN7(dev)) { | |
8252 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
8253 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
8254 | } | |
2fa2fe9a | 8255 | } |
79e53945 JB |
8256 | } |
8257 | ||
5724dbd1 DL |
8258 | static void |
8259 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
8260 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
8261 | { |
8262 | struct drm_device *dev = crtc->base.dev; | |
8263 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8264 | u32 val, base, offset; | |
aeee5a49 | 8265 | int pipe = crtc->pipe; |
4c6baa59 | 8266 | int fourcc, pixel_format; |
6761dd31 | 8267 | unsigned int aligned_height; |
b113d5ee | 8268 | struct drm_framebuffer *fb; |
1b842c89 | 8269 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 8270 | |
42a7b088 DL |
8271 | val = I915_READ(DSPCNTR(pipe)); |
8272 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8273 | return; | |
8274 | ||
d9806c9f | 8275 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8276 | if (!intel_fb) { |
4c6baa59 JB |
8277 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8278 | return; | |
8279 | } | |
8280 | ||
1b842c89 DL |
8281 | fb = &intel_fb->base; |
8282 | ||
18c5247e DV |
8283 | if (INTEL_INFO(dev)->gen >= 4) { |
8284 | if (val & DISPPLANE_TILED) { | |
49af449b | 8285 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
8286 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
8287 | } | |
8288 | } | |
4c6baa59 JB |
8289 | |
8290 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8291 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
8292 | fb->pixel_format = fourcc; |
8293 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 8294 | |
aeee5a49 | 8295 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 8296 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 8297 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 8298 | } else { |
49af449b | 8299 | if (plane_config->tiling) |
aeee5a49 | 8300 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 8301 | else |
aeee5a49 | 8302 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
8303 | } |
8304 | plane_config->base = base; | |
8305 | ||
8306 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8307 | fb->width = ((val >> 16) & 0xfff) + 1; |
8308 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
8309 | |
8310 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8311 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 8312 | |
b113d5ee | 8313 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
8314 | fb->pixel_format, |
8315 | fb->modifier[0]); | |
4c6baa59 | 8316 | |
f37b5c2b | 8317 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 8318 | |
2844a921 DL |
8319 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8320 | pipe_name(pipe), fb->width, fb->height, | |
8321 | fb->bits_per_pixel, base, fb->pitches[0], | |
8322 | plane_config->size); | |
b113d5ee | 8323 | |
2d14030b | 8324 | plane_config->fb = intel_fb; |
4c6baa59 JB |
8325 | } |
8326 | ||
0e8ffe1b | 8327 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8328 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8329 | { |
8330 | struct drm_device *dev = crtc->base.dev; | |
8331 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8332 | uint32_t tmp; | |
8333 | ||
f458ebbc DV |
8334 | if (!intel_display_power_is_enabled(dev_priv, |
8335 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
930e8c9e PZ |
8336 | return false; |
8337 | ||
e143a21c | 8338 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 8339 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 8340 | |
0e8ffe1b DV |
8341 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8342 | if (!(tmp & PIPECONF_ENABLE)) | |
8343 | return false; | |
8344 | ||
42571aef VS |
8345 | switch (tmp & PIPECONF_BPC_MASK) { |
8346 | case PIPECONF_6BPC: | |
8347 | pipe_config->pipe_bpp = 18; | |
8348 | break; | |
8349 | case PIPECONF_8BPC: | |
8350 | pipe_config->pipe_bpp = 24; | |
8351 | break; | |
8352 | case PIPECONF_10BPC: | |
8353 | pipe_config->pipe_bpp = 30; | |
8354 | break; | |
8355 | case PIPECONF_12BPC: | |
8356 | pipe_config->pipe_bpp = 36; | |
8357 | break; | |
8358 | default: | |
8359 | break; | |
8360 | } | |
8361 | ||
b5a9fa09 DV |
8362 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
8363 | pipe_config->limited_color_range = true; | |
8364 | ||
ab9412ba | 8365 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
8366 | struct intel_shared_dpll *pll; |
8367 | ||
88adfff1 DV |
8368 | pipe_config->has_pch_encoder = true; |
8369 | ||
627eb5a3 DV |
8370 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
8371 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
8372 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
8373 | |
8374 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 8375 | |
c0d43d62 | 8376 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
8377 | pipe_config->shared_dpll = |
8378 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
8379 | } else { |
8380 | tmp = I915_READ(PCH_DPLL_SEL); | |
8381 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
8382 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
8383 | else | |
8384 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
8385 | } | |
66e985c0 DV |
8386 | |
8387 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
8388 | ||
8389 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
8390 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
8391 | |
8392 | tmp = pipe_config->dpll_hw_state.dpll; | |
8393 | pipe_config->pixel_multiplier = | |
8394 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
8395 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
8396 | |
8397 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
8398 | } else { |
8399 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
8400 | } |
8401 | ||
1bd1bd80 DV |
8402 | intel_get_pipe_timings(crtc, pipe_config); |
8403 | ||
2fa2fe9a DV |
8404 | ironlake_get_pfit_config(crtc, pipe_config); |
8405 | ||
0e8ffe1b DV |
8406 | return true; |
8407 | } | |
8408 | ||
be256dc7 PZ |
8409 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
8410 | { | |
8411 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 8412 | struct intel_crtc *crtc; |
be256dc7 | 8413 | |
d3fcc808 | 8414 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 8415 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
8416 | pipe_name(crtc->pipe)); |
8417 | ||
e2c719b7 RC |
8418 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
8419 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
8420 | I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); | |
8421 | I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
8422 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); | |
8423 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
be256dc7 | 8424 | "CPU PWM1 enabled\n"); |
c5107b87 | 8425 | if (IS_HASWELL(dev)) |
e2c719b7 | 8426 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 8427 | "CPU PWM2 enabled\n"); |
e2c719b7 | 8428 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 8429 | "PCH PWM1 enabled\n"); |
e2c719b7 | 8430 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 8431 | "Utility pin enabled\n"); |
e2c719b7 | 8432 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 8433 | |
9926ada1 PZ |
8434 | /* |
8435 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
8436 | * interrupts remain enabled. We used to check for that, but since it's | |
8437 | * gen-specific and since we only disable LCPLL after we fully disable | |
8438 | * the interrupts, the check below should be enough. | |
8439 | */ | |
e2c719b7 | 8440 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
8441 | } |
8442 | ||
9ccd5aeb PZ |
8443 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
8444 | { | |
8445 | struct drm_device *dev = dev_priv->dev; | |
8446 | ||
8447 | if (IS_HASWELL(dev)) | |
8448 | return I915_READ(D_COMP_HSW); | |
8449 | else | |
8450 | return I915_READ(D_COMP_BDW); | |
8451 | } | |
8452 | ||
3c4c9b81 PZ |
8453 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
8454 | { | |
8455 | struct drm_device *dev = dev_priv->dev; | |
8456 | ||
8457 | if (IS_HASWELL(dev)) { | |
8458 | mutex_lock(&dev_priv->rps.hw_lock); | |
8459 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
8460 | val)) | |
f475dadf | 8461 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
8462 | mutex_unlock(&dev_priv->rps.hw_lock); |
8463 | } else { | |
9ccd5aeb PZ |
8464 | I915_WRITE(D_COMP_BDW, val); |
8465 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 8466 | } |
be256dc7 PZ |
8467 | } |
8468 | ||
8469 | /* | |
8470 | * This function implements pieces of two sequences from BSpec: | |
8471 | * - Sequence for display software to disable LCPLL | |
8472 | * - Sequence for display software to allow package C8+ | |
8473 | * The steps implemented here are just the steps that actually touch the LCPLL | |
8474 | * register. Callers should take care of disabling all the display engine | |
8475 | * functions, doing the mode unset, fixing interrupts, etc. | |
8476 | */ | |
6ff58d53 PZ |
8477 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
8478 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
8479 | { |
8480 | uint32_t val; | |
8481 | ||
8482 | assert_can_disable_lcpll(dev_priv); | |
8483 | ||
8484 | val = I915_READ(LCPLL_CTL); | |
8485 | ||
8486 | if (switch_to_fclk) { | |
8487 | val |= LCPLL_CD_SOURCE_FCLK; | |
8488 | I915_WRITE(LCPLL_CTL, val); | |
8489 | ||
8490 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
8491 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
8492 | DRM_ERROR("Switching to FCLK failed\n"); | |
8493 | ||
8494 | val = I915_READ(LCPLL_CTL); | |
8495 | } | |
8496 | ||
8497 | val |= LCPLL_PLL_DISABLE; | |
8498 | I915_WRITE(LCPLL_CTL, val); | |
8499 | POSTING_READ(LCPLL_CTL); | |
8500 | ||
8501 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
8502 | DRM_ERROR("LCPLL still locked\n"); | |
8503 | ||
9ccd5aeb | 8504 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 8505 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 8506 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
8507 | ndelay(100); |
8508 | ||
9ccd5aeb PZ |
8509 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
8510 | 1)) | |
be256dc7 PZ |
8511 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
8512 | ||
8513 | if (allow_power_down) { | |
8514 | val = I915_READ(LCPLL_CTL); | |
8515 | val |= LCPLL_POWER_DOWN_ALLOW; | |
8516 | I915_WRITE(LCPLL_CTL, val); | |
8517 | POSTING_READ(LCPLL_CTL); | |
8518 | } | |
8519 | } | |
8520 | ||
8521 | /* | |
8522 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
8523 | * source. | |
8524 | */ | |
6ff58d53 | 8525 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
8526 | { |
8527 | uint32_t val; | |
8528 | ||
8529 | val = I915_READ(LCPLL_CTL); | |
8530 | ||
8531 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
8532 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
8533 | return; | |
8534 | ||
a8a8bd54 PZ |
8535 | /* |
8536 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
8537 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 8538 | */ |
59bad947 | 8539 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 8540 | |
be256dc7 PZ |
8541 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
8542 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
8543 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 8544 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
8545 | } |
8546 | ||
9ccd5aeb | 8547 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
8548 | val |= D_COMP_COMP_FORCE; |
8549 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 8550 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
8551 | |
8552 | val = I915_READ(LCPLL_CTL); | |
8553 | val &= ~LCPLL_PLL_DISABLE; | |
8554 | I915_WRITE(LCPLL_CTL, val); | |
8555 | ||
8556 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
8557 | DRM_ERROR("LCPLL not locked yet\n"); | |
8558 | ||
8559 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
8560 | val = I915_READ(LCPLL_CTL); | |
8561 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
8562 | I915_WRITE(LCPLL_CTL, val); | |
8563 | ||
8564 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
8565 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
8566 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
8567 | } | |
215733fa | 8568 | |
59bad947 | 8569 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
be256dc7 PZ |
8570 | } |
8571 | ||
765dab67 PZ |
8572 | /* |
8573 | * Package states C8 and deeper are really deep PC states that can only be | |
8574 | * reached when all the devices on the system allow it, so even if the graphics | |
8575 | * device allows PC8+, it doesn't mean the system will actually get to these | |
8576 | * states. Our driver only allows PC8+ when going into runtime PM. | |
8577 | * | |
8578 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
8579 | * well is disabled and most interrupts are disabled, and these are also | |
8580 | * requirements for runtime PM. When these conditions are met, we manually do | |
8581 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
8582 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
8583 | * hang the machine. | |
8584 | * | |
8585 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
8586 | * the state of some registers, so when we come back from PC8+ we need to | |
8587 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
8588 | * need to take care of the registers kept by RC6. Notice that this happens even | |
8589 | * if we don't put the device in PCI D3 state (which is what currently happens | |
8590 | * because of the runtime PM support). | |
8591 | * | |
8592 | * For more, read "Display Sequences for Package C8" on the hardware | |
8593 | * documentation. | |
8594 | */ | |
a14cb6fc | 8595 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 8596 | { |
c67a470b PZ |
8597 | struct drm_device *dev = dev_priv->dev; |
8598 | uint32_t val; | |
8599 | ||
c67a470b PZ |
8600 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
8601 | ||
c67a470b PZ |
8602 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
8603 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
8604 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
8605 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
8606 | } | |
8607 | ||
8608 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
8609 | hsw_disable_lcpll(dev_priv, true, true); |
8610 | } | |
8611 | ||
a14cb6fc | 8612 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
8613 | { |
8614 | struct drm_device *dev = dev_priv->dev; | |
8615 | uint32_t val; | |
8616 | ||
c67a470b PZ |
8617 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
8618 | ||
8619 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
8620 | lpt_init_pch_refclk(dev); |
8621 | ||
8622 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
8623 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
8624 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
8625 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
8626 | } | |
8627 | ||
8628 | intel_prepare_ddi(dev); | |
c67a470b PZ |
8629 | } |
8630 | ||
190f68c5 ACO |
8631 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
8632 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 8633 | { |
190f68c5 | 8634 | if (!intel_ddi_pll_select(crtc, crtc_state)) |
6441ab5f | 8635 | return -EINVAL; |
716c2e55 | 8636 | |
c7653199 | 8637 | crtc->lowfreq_avail = false; |
644cef34 | 8638 | |
c8f7a0db | 8639 | return 0; |
79e53945 JB |
8640 | } |
8641 | ||
96b7dfb7 S |
8642 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
8643 | enum port port, | |
5cec258b | 8644 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 8645 | { |
3148ade7 | 8646 | u32 temp, dpll_ctl1; |
96b7dfb7 S |
8647 | |
8648 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
8649 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
8650 | ||
8651 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 DL |
8652 | case SKL_DPLL0: |
8653 | /* | |
8654 | * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part | |
8655 | * of the shared DPLL framework and thus needs to be read out | |
8656 | * separately | |
8657 | */ | |
8658 | dpll_ctl1 = I915_READ(DPLL_CTRL1); | |
8659 | pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f; | |
8660 | break; | |
96b7dfb7 S |
8661 | case SKL_DPLL1: |
8662 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
8663 | break; | |
8664 | case SKL_DPLL2: | |
8665 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
8666 | break; | |
8667 | case SKL_DPLL3: | |
8668 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
8669 | break; | |
96b7dfb7 S |
8670 | } |
8671 | } | |
8672 | ||
7d2c8175 DL |
8673 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
8674 | enum port port, | |
5cec258b | 8675 | struct intel_crtc_state *pipe_config) |
7d2c8175 DL |
8676 | { |
8677 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); | |
8678 | ||
8679 | switch (pipe_config->ddi_pll_sel) { | |
8680 | case PORT_CLK_SEL_WRPLL1: | |
8681 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; | |
8682 | break; | |
8683 | case PORT_CLK_SEL_WRPLL2: | |
8684 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; | |
8685 | break; | |
8686 | } | |
8687 | } | |
8688 | ||
26804afd | 8689 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 8690 | struct intel_crtc_state *pipe_config) |
26804afd DV |
8691 | { |
8692 | struct drm_device *dev = crtc->base.dev; | |
8693 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 8694 | struct intel_shared_dpll *pll; |
26804afd DV |
8695 | enum port port; |
8696 | uint32_t tmp; | |
8697 | ||
8698 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
8699 | ||
8700 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
8701 | ||
96b7dfb7 S |
8702 | if (IS_SKYLAKE(dev)) |
8703 | skylake_get_ddi_pll(dev_priv, port, pipe_config); | |
8704 | else | |
8705 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 8706 | |
d452c5b6 DV |
8707 | if (pipe_config->shared_dpll >= 0) { |
8708 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
8709 | ||
8710 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
8711 | &pipe_config->dpll_hw_state)); | |
8712 | } | |
8713 | ||
26804afd DV |
8714 | /* |
8715 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
8716 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
8717 | * the PCH transcoder is on. | |
8718 | */ | |
ca370455 DL |
8719 | if (INTEL_INFO(dev)->gen < 9 && |
8720 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
8721 | pipe_config->has_pch_encoder = true; |
8722 | ||
8723 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
8724 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
8725 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
8726 | ||
8727 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
8728 | } | |
8729 | } | |
8730 | ||
0e8ffe1b | 8731 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8732 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8733 | { |
8734 | struct drm_device *dev = crtc->base.dev; | |
8735 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 8736 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
8737 | uint32_t tmp; |
8738 | ||
f458ebbc | 8739 | if (!intel_display_power_is_enabled(dev_priv, |
b5482bd0 ID |
8740 | POWER_DOMAIN_PIPE(crtc->pipe))) |
8741 | return false; | |
8742 | ||
e143a21c | 8743 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
8744 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
8745 | ||
eccb140b DV |
8746 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
8747 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
8748 | enum pipe trans_edp_pipe; | |
8749 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
8750 | default: | |
8751 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
8752 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
8753 | case TRANS_DDI_EDP_INPUT_A_ON: | |
8754 | trans_edp_pipe = PIPE_A; | |
8755 | break; | |
8756 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
8757 | trans_edp_pipe = PIPE_B; | |
8758 | break; | |
8759 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
8760 | trans_edp_pipe = PIPE_C; | |
8761 | break; | |
8762 | } | |
8763 | ||
8764 | if (trans_edp_pipe == crtc->pipe) | |
8765 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
8766 | } | |
8767 | ||
f458ebbc | 8768 | if (!intel_display_power_is_enabled(dev_priv, |
eccb140b | 8769 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
8770 | return false; |
8771 | ||
eccb140b | 8772 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
8773 | if (!(tmp & PIPECONF_ENABLE)) |
8774 | return false; | |
8775 | ||
26804afd | 8776 | haswell_get_ddi_port_state(crtc, pipe_config); |
627eb5a3 | 8777 | |
1bd1bd80 DV |
8778 | intel_get_pipe_timings(crtc, pipe_config); |
8779 | ||
2fa2fe9a | 8780 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
bd2e244f JB |
8781 | if (intel_display_power_is_enabled(dev_priv, pfit_domain)) { |
8782 | if (IS_SKYLAKE(dev)) | |
8783 | skylake_get_pfit_config(crtc, pipe_config); | |
8784 | else | |
8785 | ironlake_get_pfit_config(crtc, pipe_config); | |
8786 | } | |
88adfff1 | 8787 | |
e59150dc JB |
8788 | if (IS_HASWELL(dev)) |
8789 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
8790 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 8791 | |
ebb69c95 CT |
8792 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP) { |
8793 | pipe_config->pixel_multiplier = | |
8794 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
8795 | } else { | |
8796 | pipe_config->pixel_multiplier = 1; | |
8797 | } | |
6c49f241 | 8798 | |
0e8ffe1b DV |
8799 | return true; |
8800 | } | |
8801 | ||
560b85bb CW |
8802 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
8803 | { | |
8804 | struct drm_device *dev = crtc->dev; | |
8805 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8806 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 8807 | uint32_t cntl = 0, size = 0; |
560b85bb | 8808 | |
dc41c154 | 8809 | if (base) { |
3dd512fb MR |
8810 | unsigned int width = intel_crtc->base.cursor->state->crtc_w; |
8811 | unsigned int height = intel_crtc->base.cursor->state->crtc_h; | |
dc41c154 VS |
8812 | unsigned int stride = roundup_pow_of_two(width) * 4; |
8813 | ||
8814 | switch (stride) { | |
8815 | default: | |
8816 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
8817 | width, stride); | |
8818 | stride = 256; | |
8819 | /* fallthrough */ | |
8820 | case 256: | |
8821 | case 512: | |
8822 | case 1024: | |
8823 | case 2048: | |
8824 | break; | |
4b0e333e CW |
8825 | } |
8826 | ||
dc41c154 VS |
8827 | cntl |= CURSOR_ENABLE | |
8828 | CURSOR_GAMMA_ENABLE | | |
8829 | CURSOR_FORMAT_ARGB | | |
8830 | CURSOR_STRIDE(stride); | |
8831 | ||
8832 | size = (height << 12) | width; | |
4b0e333e | 8833 | } |
560b85bb | 8834 | |
dc41c154 VS |
8835 | if (intel_crtc->cursor_cntl != 0 && |
8836 | (intel_crtc->cursor_base != base || | |
8837 | intel_crtc->cursor_size != size || | |
8838 | intel_crtc->cursor_cntl != cntl)) { | |
8839 | /* On these chipsets we can only modify the base/size/stride | |
8840 | * whilst the cursor is disabled. | |
8841 | */ | |
8842 | I915_WRITE(_CURACNTR, 0); | |
4b0e333e | 8843 | POSTING_READ(_CURACNTR); |
dc41c154 | 8844 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 8845 | } |
560b85bb | 8846 | |
99d1f387 | 8847 | if (intel_crtc->cursor_base != base) { |
9db4a9c7 | 8848 | I915_WRITE(_CURABASE, base); |
99d1f387 VS |
8849 | intel_crtc->cursor_base = base; |
8850 | } | |
4726e0b0 | 8851 | |
dc41c154 VS |
8852 | if (intel_crtc->cursor_size != size) { |
8853 | I915_WRITE(CURSIZE, size); | |
8854 | intel_crtc->cursor_size = size; | |
4b0e333e | 8855 | } |
560b85bb | 8856 | |
4b0e333e | 8857 | if (intel_crtc->cursor_cntl != cntl) { |
4b0e333e CW |
8858 | I915_WRITE(_CURACNTR, cntl); |
8859 | POSTING_READ(_CURACNTR); | |
4b0e333e | 8860 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 8861 | } |
560b85bb CW |
8862 | } |
8863 | ||
560b85bb | 8864 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
65a21cd6 JB |
8865 | { |
8866 | struct drm_device *dev = crtc->dev; | |
8867 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8868 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8869 | int pipe = intel_crtc->pipe; | |
4b0e333e CW |
8870 | uint32_t cntl; |
8871 | ||
8872 | cntl = 0; | |
8873 | if (base) { | |
8874 | cntl = MCURSOR_GAMMA_ENABLE; | |
3dd512fb | 8875 | switch (intel_crtc->base.cursor->state->crtc_w) { |
4726e0b0 SK |
8876 | case 64: |
8877 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
8878 | break; | |
8879 | case 128: | |
8880 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
8881 | break; | |
8882 | case 256: | |
8883 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
8884 | break; | |
8885 | default: | |
3dd512fb | 8886 | MISSING_CASE(intel_crtc->base.cursor->state->crtc_w); |
4726e0b0 | 8887 | return; |
65a21cd6 | 8888 | } |
4b0e333e | 8889 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 VS |
8890 | |
8891 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
8892 | cntl |= CURSOR_PIPE_CSC_ENABLE; | |
4b0e333e | 8893 | } |
65a21cd6 | 8894 | |
8e7d688b | 8895 | if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) |
4398ad45 VS |
8896 | cntl |= CURSOR_ROTATE_180; |
8897 | ||
4b0e333e CW |
8898 | if (intel_crtc->cursor_cntl != cntl) { |
8899 | I915_WRITE(CURCNTR(pipe), cntl); | |
8900 | POSTING_READ(CURCNTR(pipe)); | |
8901 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 8902 | } |
4b0e333e | 8903 | |
65a21cd6 | 8904 | /* and commit changes on next vblank */ |
5efb3e28 VS |
8905 | I915_WRITE(CURBASE(pipe), base); |
8906 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
8907 | |
8908 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
8909 | } |
8910 | ||
cda4b7d3 | 8911 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
8912 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
8913 | bool on) | |
cda4b7d3 CW |
8914 | { |
8915 | struct drm_device *dev = crtc->dev; | |
8916 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8917 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8918 | int pipe = intel_crtc->pipe; | |
3d7d6510 MR |
8919 | int x = crtc->cursor_x; |
8920 | int y = crtc->cursor_y; | |
d6e4db15 | 8921 | u32 base = 0, pos = 0; |
cda4b7d3 | 8922 | |
d6e4db15 | 8923 | if (on) |
cda4b7d3 | 8924 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 8925 | |
6e3c9717 | 8926 | if (x >= intel_crtc->config->pipe_src_w) |
d6e4db15 VS |
8927 | base = 0; |
8928 | ||
6e3c9717 | 8929 | if (y >= intel_crtc->config->pipe_src_h) |
cda4b7d3 CW |
8930 | base = 0; |
8931 | ||
8932 | if (x < 0) { | |
3dd512fb | 8933 | if (x + intel_crtc->base.cursor->state->crtc_w <= 0) |
cda4b7d3 CW |
8934 | base = 0; |
8935 | ||
8936 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
8937 | x = -x; | |
8938 | } | |
8939 | pos |= x << CURSOR_X_SHIFT; | |
8940 | ||
8941 | if (y < 0) { | |
3dd512fb | 8942 | if (y + intel_crtc->base.cursor->state->crtc_h <= 0) |
cda4b7d3 CW |
8943 | base = 0; |
8944 | ||
8945 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
8946 | y = -y; | |
8947 | } | |
8948 | pos |= y << CURSOR_Y_SHIFT; | |
8949 | ||
4b0e333e | 8950 | if (base == 0 && intel_crtc->cursor_base == 0) |
cda4b7d3 CW |
8951 | return; |
8952 | ||
5efb3e28 VS |
8953 | I915_WRITE(CURPOS(pipe), pos); |
8954 | ||
4398ad45 VS |
8955 | /* ILK+ do this automagically */ |
8956 | if (HAS_GMCH_DISPLAY(dev) && | |
8e7d688b | 8957 | crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) { |
3dd512fb MR |
8958 | base += (intel_crtc->base.cursor->state->crtc_h * |
8959 | intel_crtc->base.cursor->state->crtc_w - 1) * 4; | |
4398ad45 VS |
8960 | } |
8961 | ||
8ac54669 | 8962 | if (IS_845G(dev) || IS_I865G(dev)) |
5efb3e28 VS |
8963 | i845_update_cursor(crtc, base); |
8964 | else | |
8965 | i9xx_update_cursor(crtc, base); | |
cda4b7d3 CW |
8966 | } |
8967 | ||
dc41c154 VS |
8968 | static bool cursor_size_ok(struct drm_device *dev, |
8969 | uint32_t width, uint32_t height) | |
8970 | { | |
8971 | if (width == 0 || height == 0) | |
8972 | return false; | |
8973 | ||
8974 | /* | |
8975 | * 845g/865g are special in that they are only limited by | |
8976 | * the width of their cursors, the height is arbitrary up to | |
8977 | * the precision of the register. Everything else requires | |
8978 | * square cursors, limited to a few power-of-two sizes. | |
8979 | */ | |
8980 | if (IS_845G(dev) || IS_I865G(dev)) { | |
8981 | if ((width & 63) != 0) | |
8982 | return false; | |
8983 | ||
8984 | if (width > (IS_845G(dev) ? 64 : 512)) | |
8985 | return false; | |
8986 | ||
8987 | if (height > 1023) | |
8988 | return false; | |
8989 | } else { | |
8990 | switch (width | height) { | |
8991 | case 256: | |
8992 | case 128: | |
8993 | if (IS_GEN2(dev)) | |
8994 | return false; | |
8995 | case 64: | |
8996 | break; | |
8997 | default: | |
8998 | return false; | |
8999 | } | |
9000 | } | |
9001 | ||
9002 | return true; | |
9003 | } | |
9004 | ||
79e53945 | 9005 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 9006 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 9007 | { |
7203425a | 9008 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 9009 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 9010 | |
7203425a | 9011 | for (i = start; i < end; i++) { |
79e53945 JB |
9012 | intel_crtc->lut_r[i] = red[i] >> 8; |
9013 | intel_crtc->lut_g[i] = green[i] >> 8; | |
9014 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
9015 | } | |
9016 | ||
9017 | intel_crtc_load_lut(crtc); | |
9018 | } | |
9019 | ||
79e53945 JB |
9020 | /* VESA 640x480x72Hz mode to set on the pipe */ |
9021 | static struct drm_display_mode load_detect_mode = { | |
9022 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
9023 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
9024 | }; | |
9025 | ||
a8bb6818 DV |
9026 | struct drm_framebuffer * |
9027 | __intel_framebuffer_create(struct drm_device *dev, | |
9028 | struct drm_mode_fb_cmd2 *mode_cmd, | |
9029 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
9030 | { |
9031 | struct intel_framebuffer *intel_fb; | |
9032 | int ret; | |
9033 | ||
9034 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
9035 | if (!intel_fb) { | |
6ccb81f2 | 9036 | drm_gem_object_unreference(&obj->base); |
d2dff872 CW |
9037 | return ERR_PTR(-ENOMEM); |
9038 | } | |
9039 | ||
9040 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
9041 | if (ret) |
9042 | goto err; | |
d2dff872 CW |
9043 | |
9044 | return &intel_fb->base; | |
dd4916c5 | 9045 | err: |
6ccb81f2 | 9046 | drm_gem_object_unreference(&obj->base); |
dd4916c5 DV |
9047 | kfree(intel_fb); |
9048 | ||
9049 | return ERR_PTR(ret); | |
d2dff872 CW |
9050 | } |
9051 | ||
b5ea642a | 9052 | static struct drm_framebuffer * |
a8bb6818 DV |
9053 | intel_framebuffer_create(struct drm_device *dev, |
9054 | struct drm_mode_fb_cmd2 *mode_cmd, | |
9055 | struct drm_i915_gem_object *obj) | |
9056 | { | |
9057 | struct drm_framebuffer *fb; | |
9058 | int ret; | |
9059 | ||
9060 | ret = i915_mutex_lock_interruptible(dev); | |
9061 | if (ret) | |
9062 | return ERR_PTR(ret); | |
9063 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
9064 | mutex_unlock(&dev->struct_mutex); | |
9065 | ||
9066 | return fb; | |
9067 | } | |
9068 | ||
d2dff872 CW |
9069 | static u32 |
9070 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
9071 | { | |
9072 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
9073 | return ALIGN(pitch, 64); | |
9074 | } | |
9075 | ||
9076 | static u32 | |
9077 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
9078 | { | |
9079 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 9080 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
9081 | } |
9082 | ||
9083 | static struct drm_framebuffer * | |
9084 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
9085 | struct drm_display_mode *mode, | |
9086 | int depth, int bpp) | |
9087 | { | |
9088 | struct drm_i915_gem_object *obj; | |
0fed39bd | 9089 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
9090 | |
9091 | obj = i915_gem_alloc_object(dev, | |
9092 | intel_framebuffer_size_for_mode(mode, bpp)); | |
9093 | if (obj == NULL) | |
9094 | return ERR_PTR(-ENOMEM); | |
9095 | ||
9096 | mode_cmd.width = mode->hdisplay; | |
9097 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
9098 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
9099 | bpp); | |
5ca0c34a | 9100 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
9101 | |
9102 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
9103 | } | |
9104 | ||
9105 | static struct drm_framebuffer * | |
9106 | mode_fits_in_fbdev(struct drm_device *dev, | |
9107 | struct drm_display_mode *mode) | |
9108 | { | |
4520f53a | 9109 | #ifdef CONFIG_DRM_I915_FBDEV |
d2dff872 CW |
9110 | struct drm_i915_private *dev_priv = dev->dev_private; |
9111 | struct drm_i915_gem_object *obj; | |
9112 | struct drm_framebuffer *fb; | |
9113 | ||
4c0e5528 | 9114 | if (!dev_priv->fbdev) |
d2dff872 CW |
9115 | return NULL; |
9116 | ||
4c0e5528 | 9117 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
9118 | return NULL; |
9119 | ||
4c0e5528 DV |
9120 | obj = dev_priv->fbdev->fb->obj; |
9121 | BUG_ON(!obj); | |
9122 | ||
8bcd4553 | 9123 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
9124 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
9125 | fb->bits_per_pixel)) | |
d2dff872 CW |
9126 | return NULL; |
9127 | ||
01f2c773 | 9128 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
9129 | return NULL; |
9130 | ||
9131 | return fb; | |
4520f53a DV |
9132 | #else |
9133 | return NULL; | |
9134 | #endif | |
d2dff872 CW |
9135 | } |
9136 | ||
d2434ab7 | 9137 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 9138 | struct drm_display_mode *mode, |
51fd371b RC |
9139 | struct intel_load_detect_pipe *old, |
9140 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
9141 | { |
9142 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
9143 | struct intel_encoder *intel_encoder = |
9144 | intel_attached_encoder(connector); | |
79e53945 | 9145 | struct drm_crtc *possible_crtc; |
4ef69c7a | 9146 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
9147 | struct drm_crtc *crtc = NULL; |
9148 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 9149 | struct drm_framebuffer *fb; |
51fd371b | 9150 | struct drm_mode_config *config = &dev->mode_config; |
83a57153 | 9151 | struct drm_atomic_state *state = NULL; |
944b0c76 | 9152 | struct drm_connector_state *connector_state; |
51fd371b | 9153 | int ret, i = -1; |
79e53945 | 9154 | |
d2dff872 | 9155 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 9156 | connector->base.id, connector->name, |
8e329a03 | 9157 | encoder->base.id, encoder->name); |
d2dff872 | 9158 | |
51fd371b RC |
9159 | retry: |
9160 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
9161 | if (ret) | |
9162 | goto fail_unlock; | |
6e9f798d | 9163 | |
79e53945 JB |
9164 | /* |
9165 | * Algorithm gets a little messy: | |
7a5e4805 | 9166 | * |
79e53945 JB |
9167 | * - if the connector already has an assigned crtc, use it (but make |
9168 | * sure it's on first) | |
7a5e4805 | 9169 | * |
79e53945 JB |
9170 | * - try to find the first unused crtc that can drive this connector, |
9171 | * and use that if we find one | |
79e53945 JB |
9172 | */ |
9173 | ||
9174 | /* See if we already have a CRTC for this connector */ | |
9175 | if (encoder->crtc) { | |
9176 | crtc = encoder->crtc; | |
8261b191 | 9177 | |
51fd371b | 9178 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de DV |
9179 | if (ret) |
9180 | goto fail_unlock; | |
9181 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); | |
51fd371b RC |
9182 | if (ret) |
9183 | goto fail_unlock; | |
7b24056b | 9184 | |
24218aac | 9185 | old->dpms_mode = connector->dpms; |
8261b191 CW |
9186 | old->load_detect_temp = false; |
9187 | ||
9188 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
9189 | if (connector->dpms != DRM_MODE_DPMS_ON) |
9190 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 9191 | |
7173188d | 9192 | return true; |
79e53945 JB |
9193 | } |
9194 | ||
9195 | /* Find an unused one (if possible) */ | |
70e1e0ec | 9196 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
9197 | i++; |
9198 | if (!(encoder->possible_crtcs & (1 << i))) | |
9199 | continue; | |
83d65738 | 9200 | if (possible_crtc->state->enable) |
a459249c VS |
9201 | continue; |
9202 | /* This can occur when applying the pipe A quirk on resume. */ | |
9203 | if (to_intel_crtc(possible_crtc)->new_enabled) | |
9204 | continue; | |
9205 | ||
9206 | crtc = possible_crtc; | |
9207 | break; | |
79e53945 JB |
9208 | } |
9209 | ||
9210 | /* | |
9211 | * If we didn't find an unused CRTC, don't use any. | |
9212 | */ | |
9213 | if (!crtc) { | |
7173188d | 9214 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
51fd371b | 9215 | goto fail_unlock; |
79e53945 JB |
9216 | } |
9217 | ||
51fd371b RC |
9218 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
9219 | if (ret) | |
4d02e2de DV |
9220 | goto fail_unlock; |
9221 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); | |
9222 | if (ret) | |
51fd371b | 9223 | goto fail_unlock; |
fc303101 DV |
9224 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
9225 | to_intel_connector(connector)->new_encoder = intel_encoder; | |
79e53945 JB |
9226 | |
9227 | intel_crtc = to_intel_crtc(crtc); | |
412b61d8 | 9228 | intel_crtc->new_enabled = true; |
24218aac | 9229 | old->dpms_mode = connector->dpms; |
8261b191 | 9230 | old->load_detect_temp = true; |
d2dff872 | 9231 | old->release_fb = NULL; |
79e53945 | 9232 | |
83a57153 ACO |
9233 | state = drm_atomic_state_alloc(dev); |
9234 | if (!state) | |
9235 | return false; | |
9236 | ||
9237 | state->acquire_ctx = ctx; | |
9238 | ||
944b0c76 ACO |
9239 | connector_state = drm_atomic_get_connector_state(state, connector); |
9240 | if (IS_ERR(connector_state)) { | |
9241 | ret = PTR_ERR(connector_state); | |
9242 | goto fail; | |
9243 | } | |
9244 | ||
9245 | connector_state->crtc = crtc; | |
9246 | connector_state->best_encoder = &intel_encoder->base; | |
9247 | ||
6492711d CW |
9248 | if (!mode) |
9249 | mode = &load_detect_mode; | |
79e53945 | 9250 | |
d2dff872 CW |
9251 | /* We need a framebuffer large enough to accommodate all accesses |
9252 | * that the plane may generate whilst we perform load detection. | |
9253 | * We can not rely on the fbcon either being present (we get called | |
9254 | * during its initialisation to detect all boot displays, or it may | |
9255 | * not even exist) or that it is large enough to satisfy the | |
9256 | * requested mode. | |
9257 | */ | |
94352cf9 DV |
9258 | fb = mode_fits_in_fbdev(dev, mode); |
9259 | if (fb == NULL) { | |
d2dff872 | 9260 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
9261 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
9262 | old->release_fb = fb; | |
d2dff872 CW |
9263 | } else |
9264 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 9265 | if (IS_ERR(fb)) { |
d2dff872 | 9266 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 9267 | goto fail; |
79e53945 | 9268 | } |
79e53945 | 9269 | |
83a57153 | 9270 | if (intel_set_mode(crtc, mode, 0, 0, fb, state)) { |
6492711d | 9271 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
9272 | if (old->release_fb) |
9273 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 9274 | goto fail; |
79e53945 | 9275 | } |
9128b040 | 9276 | crtc->primary->crtc = crtc; |
7173188d | 9277 | |
79e53945 | 9278 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 9279 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 9280 | return true; |
412b61d8 VS |
9281 | |
9282 | fail: | |
83d65738 | 9283 | intel_crtc->new_enabled = crtc->state->enable; |
51fd371b | 9284 | fail_unlock: |
83a57153 ACO |
9285 | if (state) { |
9286 | drm_atomic_state_free(state); | |
9287 | state = NULL; | |
9288 | } | |
9289 | ||
51fd371b RC |
9290 | if (ret == -EDEADLK) { |
9291 | drm_modeset_backoff(ctx); | |
9292 | goto retry; | |
9293 | } | |
9294 | ||
412b61d8 | 9295 | return false; |
79e53945 JB |
9296 | } |
9297 | ||
d2434ab7 | 9298 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
9299 | struct intel_load_detect_pipe *old, |
9300 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 9301 | { |
83a57153 | 9302 | struct drm_device *dev = connector->dev; |
d2434ab7 DV |
9303 | struct intel_encoder *intel_encoder = |
9304 | intel_attached_encoder(connector); | |
4ef69c7a | 9305 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 9306 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 9307 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
83a57153 | 9308 | struct drm_atomic_state *state; |
944b0c76 | 9309 | struct drm_connector_state *connector_state; |
79e53945 | 9310 | |
d2dff872 | 9311 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 9312 | connector->base.id, connector->name, |
8e329a03 | 9313 | encoder->base.id, encoder->name); |
d2dff872 | 9314 | |
8261b191 | 9315 | if (old->load_detect_temp) { |
83a57153 | 9316 | state = drm_atomic_state_alloc(dev); |
944b0c76 ACO |
9317 | if (!state) |
9318 | goto fail; | |
83a57153 ACO |
9319 | |
9320 | state->acquire_ctx = ctx; | |
9321 | ||
944b0c76 ACO |
9322 | connector_state = drm_atomic_get_connector_state(state, connector); |
9323 | if (IS_ERR(connector_state)) | |
9324 | goto fail; | |
9325 | ||
fc303101 DV |
9326 | to_intel_connector(connector)->new_encoder = NULL; |
9327 | intel_encoder->new_crtc = NULL; | |
412b61d8 | 9328 | intel_crtc->new_enabled = false; |
944b0c76 ACO |
9329 | |
9330 | connector_state->best_encoder = NULL; | |
9331 | connector_state->crtc = NULL; | |
9332 | ||
83a57153 ACO |
9333 | intel_set_mode(crtc, NULL, 0, 0, NULL, state); |
9334 | ||
9335 | drm_atomic_state_free(state); | |
d2dff872 | 9336 | |
36206361 DV |
9337 | if (old->release_fb) { |
9338 | drm_framebuffer_unregister_private(old->release_fb); | |
9339 | drm_framebuffer_unreference(old->release_fb); | |
9340 | } | |
d2dff872 | 9341 | |
0622a53c | 9342 | return; |
79e53945 JB |
9343 | } |
9344 | ||
c751ce4f | 9345 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
9346 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
9347 | connector->funcs->dpms(connector, old->dpms_mode); | |
944b0c76 ACO |
9348 | |
9349 | return; | |
9350 | fail: | |
9351 | DRM_DEBUG_KMS("Couldn't release load detect pipe.\n"); | |
9352 | drm_atomic_state_free(state); | |
79e53945 JB |
9353 | } |
9354 | ||
da4a1efa | 9355 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 9356 | const struct intel_crtc_state *pipe_config) |
da4a1efa VS |
9357 | { |
9358 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9359 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
9360 | ||
9361 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 9362 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
9363 | else if (HAS_PCH_SPLIT(dev)) |
9364 | return 120000; | |
9365 | else if (!IS_GEN2(dev)) | |
9366 | return 96000; | |
9367 | else | |
9368 | return 48000; | |
9369 | } | |
9370 | ||
79e53945 | 9371 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 9372 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 9373 | struct intel_crtc_state *pipe_config) |
79e53945 | 9374 | { |
f1f644dc | 9375 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 9376 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 9377 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 9378 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
9379 | u32 fp; |
9380 | intel_clock_t clock; | |
da4a1efa | 9381 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
9382 | |
9383 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 9384 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 9385 | else |
293623f7 | 9386 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
9387 | |
9388 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
9389 | if (IS_PINEVIEW(dev)) { |
9390 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
9391 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
9392 | } else { |
9393 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
9394 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
9395 | } | |
9396 | ||
a6c45cf0 | 9397 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
9398 | if (IS_PINEVIEW(dev)) |
9399 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
9400 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
9401 | else |
9402 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
9403 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
9404 | ||
9405 | switch (dpll & DPLL_MODE_MASK) { | |
9406 | case DPLLB_MODE_DAC_SERIAL: | |
9407 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
9408 | 5 : 10; | |
9409 | break; | |
9410 | case DPLLB_MODE_LVDS: | |
9411 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
9412 | 7 : 14; | |
9413 | break; | |
9414 | default: | |
28c97730 | 9415 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 9416 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 9417 | return; |
79e53945 JB |
9418 | } |
9419 | ||
ac58c3f0 | 9420 | if (IS_PINEVIEW(dev)) |
da4a1efa | 9421 | pineview_clock(refclk, &clock); |
ac58c3f0 | 9422 | else |
da4a1efa | 9423 | i9xx_clock(refclk, &clock); |
79e53945 | 9424 | } else { |
0fb58223 | 9425 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 9426 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
9427 | |
9428 | if (is_lvds) { | |
9429 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
9430 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
9431 | |
9432 | if (lvds & LVDS_CLKB_POWER_UP) | |
9433 | clock.p2 = 7; | |
9434 | else | |
9435 | clock.p2 = 14; | |
79e53945 JB |
9436 | } else { |
9437 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
9438 | clock.p1 = 2; | |
9439 | else { | |
9440 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
9441 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
9442 | } | |
9443 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
9444 | clock.p2 = 4; | |
9445 | else | |
9446 | clock.p2 = 2; | |
79e53945 | 9447 | } |
da4a1efa VS |
9448 | |
9449 | i9xx_clock(refclk, &clock); | |
79e53945 JB |
9450 | } |
9451 | ||
18442d08 VS |
9452 | /* |
9453 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 9454 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
9455 | * encoder's get_config() function. |
9456 | */ | |
9457 | pipe_config->port_clock = clock.dot; | |
f1f644dc JB |
9458 | } |
9459 | ||
6878da05 VS |
9460 | int intel_dotclock_calculate(int link_freq, |
9461 | const struct intel_link_m_n *m_n) | |
f1f644dc | 9462 | { |
f1f644dc JB |
9463 | /* |
9464 | * The calculation for the data clock is: | |
1041a02f | 9465 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 9466 | * But we want to avoid losing precison if possible, so: |
1041a02f | 9467 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
9468 | * |
9469 | * and the link clock is simpler: | |
1041a02f | 9470 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
9471 | */ |
9472 | ||
6878da05 VS |
9473 | if (!m_n->link_n) |
9474 | return 0; | |
f1f644dc | 9475 | |
6878da05 VS |
9476 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
9477 | } | |
f1f644dc | 9478 | |
18442d08 | 9479 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 9480 | struct intel_crtc_state *pipe_config) |
6878da05 VS |
9481 | { |
9482 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 9483 | |
18442d08 VS |
9484 | /* read out port_clock from the DPLL */ |
9485 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 9486 | |
f1f644dc | 9487 | /* |
18442d08 | 9488 | * This value does not include pixel_multiplier. |
241bfc38 | 9489 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
9490 | * agree once we know their relationship in the encoder's |
9491 | * get_config() function. | |
79e53945 | 9492 | */ |
2d112de7 | 9493 | pipe_config->base.adjusted_mode.crtc_clock = |
18442d08 VS |
9494 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
9495 | &pipe_config->fdi_m_n); | |
79e53945 JB |
9496 | } |
9497 | ||
9498 | /** Returns the currently programmed mode of the given pipe. */ | |
9499 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
9500 | struct drm_crtc *crtc) | |
9501 | { | |
548f245b | 9502 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 9503 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 9504 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 9505 | struct drm_display_mode *mode; |
5cec258b | 9506 | struct intel_crtc_state pipe_config; |
fe2b8f9d PZ |
9507 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
9508 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
9509 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
9510 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 9511 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
9512 | |
9513 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
9514 | if (!mode) | |
9515 | return NULL; | |
9516 | ||
f1f644dc JB |
9517 | /* |
9518 | * Construct a pipe_config sufficient for getting the clock info | |
9519 | * back out of crtc_clock_get. | |
9520 | * | |
9521 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
9522 | * to use a real value here instead. | |
9523 | */ | |
293623f7 | 9524 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 9525 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
9526 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
9527 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
9528 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
9529 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
9530 | ||
773ae034 | 9531 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
9532 | mode->hdisplay = (htot & 0xffff) + 1; |
9533 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
9534 | mode->hsync_start = (hsync & 0xffff) + 1; | |
9535 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
9536 | mode->vdisplay = (vtot & 0xffff) + 1; | |
9537 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
9538 | mode->vsync_start = (vsync & 0xffff) + 1; | |
9539 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
9540 | ||
9541 | drm_mode_set_name(mode); | |
79e53945 JB |
9542 | |
9543 | return mode; | |
9544 | } | |
9545 | ||
652c393a JB |
9546 | static void intel_decrease_pllclock(struct drm_crtc *crtc) |
9547 | { | |
9548 | struct drm_device *dev = crtc->dev; | |
fbee40df | 9549 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 9550 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
652c393a | 9551 | |
baff296c | 9552 | if (!HAS_GMCH_DISPLAY(dev)) |
652c393a JB |
9553 | return; |
9554 | ||
9555 | if (!dev_priv->lvds_downclock_avail) | |
9556 | return; | |
9557 | ||
9558 | /* | |
9559 | * Since this is called by a timer, we should never get here in | |
9560 | * the manual case. | |
9561 | */ | |
9562 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
9563 | int pipe = intel_crtc->pipe; |
9564 | int dpll_reg = DPLL(pipe); | |
9565 | int dpll; | |
f6e5b160 | 9566 | |
44d98a61 | 9567 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 9568 | |
8ac5a6d5 | 9569 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 9570 | |
dc257cf1 | 9571 | dpll = I915_READ(dpll_reg); |
652c393a JB |
9572 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
9573 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 9574 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
9575 | dpll = I915_READ(dpll_reg); |
9576 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 9577 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
9578 | } |
9579 | ||
9580 | } | |
9581 | ||
f047e395 CW |
9582 | void intel_mark_busy(struct drm_device *dev) |
9583 | { | |
c67a470b PZ |
9584 | struct drm_i915_private *dev_priv = dev->dev_private; |
9585 | ||
f62a0076 CW |
9586 | if (dev_priv->mm.busy) |
9587 | return; | |
9588 | ||
43694d69 | 9589 | intel_runtime_pm_get(dev_priv); |
c67a470b | 9590 | i915_update_gfx_val(dev_priv); |
43cf3bf0 CW |
9591 | if (INTEL_INFO(dev)->gen >= 6) |
9592 | gen6_rps_busy(dev_priv); | |
f62a0076 | 9593 | dev_priv->mm.busy = true; |
f047e395 CW |
9594 | } |
9595 | ||
9596 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 9597 | { |
c67a470b | 9598 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 9599 | struct drm_crtc *crtc; |
652c393a | 9600 | |
f62a0076 CW |
9601 | if (!dev_priv->mm.busy) |
9602 | return; | |
9603 | ||
9604 | dev_priv->mm.busy = false; | |
9605 | ||
70e1e0ec | 9606 | for_each_crtc(dev, crtc) { |
f4510a27 | 9607 | if (!crtc->primary->fb) |
652c393a JB |
9608 | continue; |
9609 | ||
725a5b54 | 9610 | intel_decrease_pllclock(crtc); |
652c393a | 9611 | } |
b29c19b6 | 9612 | |
3d13ef2e | 9613 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 9614 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 | 9615 | |
43694d69 | 9616 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
9617 | } |
9618 | ||
f5de6e07 ACO |
9619 | static void intel_crtc_set_state(struct intel_crtc *crtc, |
9620 | struct intel_crtc_state *crtc_state) | |
9621 | { | |
9622 | kfree(crtc->config); | |
9623 | crtc->config = crtc_state; | |
16f3f658 | 9624 | crtc->base.state = &crtc_state->base; |
f5de6e07 ACO |
9625 | } |
9626 | ||
79e53945 JB |
9627 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
9628 | { | |
9629 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
9630 | struct drm_device *dev = crtc->dev; |
9631 | struct intel_unpin_work *work; | |
67e77c5a | 9632 | |
5e2d7afc | 9633 | spin_lock_irq(&dev->event_lock); |
67e77c5a DV |
9634 | work = intel_crtc->unpin_work; |
9635 | intel_crtc->unpin_work = NULL; | |
5e2d7afc | 9636 | spin_unlock_irq(&dev->event_lock); |
67e77c5a DV |
9637 | |
9638 | if (work) { | |
9639 | cancel_work_sync(&work->work); | |
9640 | kfree(work); | |
9641 | } | |
79e53945 | 9642 | |
f5de6e07 | 9643 | intel_crtc_set_state(intel_crtc, NULL); |
79e53945 | 9644 | drm_crtc_cleanup(crtc); |
67e77c5a | 9645 | |
79e53945 JB |
9646 | kfree(intel_crtc); |
9647 | } | |
9648 | ||
6b95a207 KH |
9649 | static void intel_unpin_work_fn(struct work_struct *__work) |
9650 | { | |
9651 | struct intel_unpin_work *work = | |
9652 | container_of(__work, struct intel_unpin_work, work); | |
b4a98e57 | 9653 | struct drm_device *dev = work->crtc->dev; |
f99d7069 | 9654 | enum pipe pipe = to_intel_crtc(work->crtc)->pipe; |
6b95a207 | 9655 | |
b4a98e57 | 9656 | mutex_lock(&dev->struct_mutex); |
82bc3b2d | 9657 | intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state); |
05394f39 | 9658 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
d9e86c0e | 9659 | |
7ff0ebcc | 9660 | intel_fbc_update(dev); |
f06cc1b9 JH |
9661 | |
9662 | if (work->flip_queued_req) | |
146d84f0 | 9663 | i915_gem_request_assign(&work->flip_queued_req, NULL); |
b4a98e57 CW |
9664 | mutex_unlock(&dev->struct_mutex); |
9665 | ||
f99d7069 | 9666 | intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
89ed88ba | 9667 | drm_framebuffer_unreference(work->old_fb); |
f99d7069 | 9668 | |
b4a98e57 CW |
9669 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); |
9670 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); | |
9671 | ||
6b95a207 KH |
9672 | kfree(work); |
9673 | } | |
9674 | ||
1afe3e9d | 9675 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 9676 | struct drm_crtc *crtc) |
6b95a207 | 9677 | { |
6b95a207 KH |
9678 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9679 | struct intel_unpin_work *work; | |
6b95a207 KH |
9680 | unsigned long flags; |
9681 | ||
9682 | /* Ignore early vblank irqs */ | |
9683 | if (intel_crtc == NULL) | |
9684 | return; | |
9685 | ||
f326038a DV |
9686 | /* |
9687 | * This is called both by irq handlers and the reset code (to complete | |
9688 | * lost pageflips) so needs the full irqsave spinlocks. | |
9689 | */ | |
6b95a207 KH |
9690 | spin_lock_irqsave(&dev->event_lock, flags); |
9691 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
9692 | |
9693 | /* Ensure we don't miss a work->pending update ... */ | |
9694 | smp_rmb(); | |
9695 | ||
9696 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
9697 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9698 | return; | |
9699 | } | |
9700 | ||
d6bbafa1 | 9701 | page_flip_completed(intel_crtc); |
0af7e4df | 9702 | |
6b95a207 | 9703 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6b95a207 KH |
9704 | } |
9705 | ||
1afe3e9d JB |
9706 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
9707 | { | |
fbee40df | 9708 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
9709 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
9710 | ||
49b14a5c | 9711 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
9712 | } |
9713 | ||
9714 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
9715 | { | |
fbee40df | 9716 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
9717 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
9718 | ||
49b14a5c | 9719 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
9720 | } |
9721 | ||
75f7f3ec VS |
9722 | /* Is 'a' after or equal to 'b'? */ |
9723 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
9724 | { | |
9725 | return !((a - b) & 0x80000000); | |
9726 | } | |
9727 | ||
9728 | static bool page_flip_finished(struct intel_crtc *crtc) | |
9729 | { | |
9730 | struct drm_device *dev = crtc->base.dev; | |
9731 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9732 | ||
bdfa7542 VS |
9733 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
9734 | crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
9735 | return true; | |
9736 | ||
75f7f3ec VS |
9737 | /* |
9738 | * The relevant registers doen't exist on pre-ctg. | |
9739 | * As the flip done interrupt doesn't trigger for mmio | |
9740 | * flips on gmch platforms, a flip count check isn't | |
9741 | * really needed there. But since ctg has the registers, | |
9742 | * include it in the check anyway. | |
9743 | */ | |
9744 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
9745 | return true; | |
9746 | ||
9747 | /* | |
9748 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
9749 | * used the same base address. In that case the mmio flip might | |
9750 | * have completed, but the CS hasn't even executed the flip yet. | |
9751 | * | |
9752 | * A flip count check isn't enough as the CS might have updated | |
9753 | * the base address just after start of vblank, but before we | |
9754 | * managed to process the interrupt. This means we'd complete the | |
9755 | * CS flip too soon. | |
9756 | * | |
9757 | * Combining both checks should get us a good enough result. It may | |
9758 | * still happen that the CS flip has been executed, but has not | |
9759 | * yet actually completed. But in case the base address is the same | |
9760 | * anyway, we don't really care. | |
9761 | */ | |
9762 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
9763 | crtc->unpin_work->gtt_offset && | |
9764 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)), | |
9765 | crtc->unpin_work->flip_count); | |
9766 | } | |
9767 | ||
6b95a207 KH |
9768 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
9769 | { | |
fbee40df | 9770 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
9771 | struct intel_crtc *intel_crtc = |
9772 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
9773 | unsigned long flags; | |
9774 | ||
f326038a DV |
9775 | |
9776 | /* | |
9777 | * This is called both by irq handlers and the reset code (to complete | |
9778 | * lost pageflips) so needs the full irqsave spinlocks. | |
9779 | * | |
9780 | * NB: An MMIO update of the plane base pointer will also | |
e7d841ca CW |
9781 | * generate a page-flip completion irq, i.e. every modeset |
9782 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
9783 | */ | |
6b95a207 | 9784 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 9785 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 9786 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
9787 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9788 | } | |
9789 | ||
eba905b2 | 9790 | static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
e7d841ca CW |
9791 | { |
9792 | /* Ensure that the work item is consistent when activating it ... */ | |
9793 | smp_wmb(); | |
9794 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
9795 | /* and that it is marked active as soon as the irq could fire. */ | |
9796 | smp_wmb(); | |
9797 | } | |
9798 | ||
8c9f3aaf JB |
9799 | static int intel_gen2_queue_flip(struct drm_device *dev, |
9800 | struct drm_crtc *crtc, | |
9801 | struct drm_framebuffer *fb, | |
ed8d1975 | 9802 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9803 | struct intel_engine_cs *ring, |
ed8d1975 | 9804 | uint32_t flags) |
8c9f3aaf | 9805 | { |
8c9f3aaf | 9806 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
9807 | u32 flip_mask; |
9808 | int ret; | |
9809 | ||
6d90c952 | 9810 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 9811 | if (ret) |
4fa62c89 | 9812 | return ret; |
8c9f3aaf JB |
9813 | |
9814 | /* Can't queue multiple flips, so wait for the previous | |
9815 | * one to finish before executing the next. | |
9816 | */ | |
9817 | if (intel_crtc->plane) | |
9818 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
9819 | else | |
9820 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
9821 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
9822 | intel_ring_emit(ring, MI_NOOP); | |
9823 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
9824 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9825 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9826 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 | 9827 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
9828 | |
9829 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9830 | __intel_ring_advance(ring); |
83d4092b | 9831 | return 0; |
8c9f3aaf JB |
9832 | } |
9833 | ||
9834 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
9835 | struct drm_crtc *crtc, | |
9836 | struct drm_framebuffer *fb, | |
ed8d1975 | 9837 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9838 | struct intel_engine_cs *ring, |
ed8d1975 | 9839 | uint32_t flags) |
8c9f3aaf | 9840 | { |
8c9f3aaf | 9841 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
9842 | u32 flip_mask; |
9843 | int ret; | |
9844 | ||
6d90c952 | 9845 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 9846 | if (ret) |
4fa62c89 | 9847 | return ret; |
8c9f3aaf JB |
9848 | |
9849 | if (intel_crtc->plane) | |
9850 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
9851 | else | |
9852 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
9853 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
9854 | intel_ring_emit(ring, MI_NOOP); | |
9855 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
9856 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9857 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9858 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 DV |
9859 | intel_ring_emit(ring, MI_NOOP); |
9860 | ||
e7d841ca | 9861 | intel_mark_page_flip_active(intel_crtc); |
09246732 | 9862 | __intel_ring_advance(ring); |
83d4092b | 9863 | return 0; |
8c9f3aaf JB |
9864 | } |
9865 | ||
9866 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
9867 | struct drm_crtc *crtc, | |
9868 | struct drm_framebuffer *fb, | |
ed8d1975 | 9869 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9870 | struct intel_engine_cs *ring, |
ed8d1975 | 9871 | uint32_t flags) |
8c9f3aaf JB |
9872 | { |
9873 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9874 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9875 | uint32_t pf, pipesrc; | |
9876 | int ret; | |
9877 | ||
6d90c952 | 9878 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 9879 | if (ret) |
4fa62c89 | 9880 | return ret; |
8c9f3aaf JB |
9881 | |
9882 | /* i965+ uses the linear or tiled offsets from the | |
9883 | * Display Registers (which do not change across a page-flip) | |
9884 | * so we need only reprogram the base address. | |
9885 | */ | |
6d90c952 DV |
9886 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
9887 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9888 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9889 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
c2c75131 | 9890 | obj->tiling_mode); |
8c9f3aaf JB |
9891 | |
9892 | /* XXX Enabling the panel-fitter across page-flip is so far | |
9893 | * untested on non-native modes, so ignore it for now. | |
9894 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
9895 | */ | |
9896 | pf = 0; | |
9897 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 9898 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
9899 | |
9900 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9901 | __intel_ring_advance(ring); |
83d4092b | 9902 | return 0; |
8c9f3aaf JB |
9903 | } |
9904 | ||
9905 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
9906 | struct drm_crtc *crtc, | |
9907 | struct drm_framebuffer *fb, | |
ed8d1975 | 9908 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9909 | struct intel_engine_cs *ring, |
ed8d1975 | 9910 | uint32_t flags) |
8c9f3aaf JB |
9911 | { |
9912 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9913 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9914 | uint32_t pf, pipesrc; | |
9915 | int ret; | |
9916 | ||
6d90c952 | 9917 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 9918 | if (ret) |
4fa62c89 | 9919 | return ret; |
8c9f3aaf | 9920 | |
6d90c952 DV |
9921 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
9922 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9923 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
75f7f3ec | 9924 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8c9f3aaf | 9925 | |
dc257cf1 DV |
9926 | /* Contrary to the suggestions in the documentation, |
9927 | * "Enable Panel Fitter" does not seem to be required when page | |
9928 | * flipping with a non-native mode, and worse causes a normal | |
9929 | * modeset to fail. | |
9930 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
9931 | */ | |
9932 | pf = 0; | |
8c9f3aaf | 9933 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 9934 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
9935 | |
9936 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9937 | __intel_ring_advance(ring); |
83d4092b | 9938 | return 0; |
8c9f3aaf JB |
9939 | } |
9940 | ||
7c9017e5 JB |
9941 | static int intel_gen7_queue_flip(struct drm_device *dev, |
9942 | struct drm_crtc *crtc, | |
9943 | struct drm_framebuffer *fb, | |
ed8d1975 | 9944 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9945 | struct intel_engine_cs *ring, |
ed8d1975 | 9946 | uint32_t flags) |
7c9017e5 | 9947 | { |
7c9017e5 | 9948 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 9949 | uint32_t plane_bit = 0; |
ffe74d75 CW |
9950 | int len, ret; |
9951 | ||
eba905b2 | 9952 | switch (intel_crtc->plane) { |
cb05d8de DV |
9953 | case PLANE_A: |
9954 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
9955 | break; | |
9956 | case PLANE_B: | |
9957 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
9958 | break; | |
9959 | case PLANE_C: | |
9960 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
9961 | break; | |
9962 | default: | |
9963 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 9964 | return -ENODEV; |
cb05d8de DV |
9965 | } |
9966 | ||
ffe74d75 | 9967 | len = 4; |
f476828a | 9968 | if (ring->id == RCS) { |
ffe74d75 | 9969 | len += 6; |
f476828a DL |
9970 | /* |
9971 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
9972 | * 48bits addresses, and we need a NOOP for the batch size to | |
9973 | * stay even. | |
9974 | */ | |
9975 | if (IS_GEN8(dev)) | |
9976 | len += 2; | |
9977 | } | |
ffe74d75 | 9978 | |
f66fab8e VS |
9979 | /* |
9980 | * BSpec MI_DISPLAY_FLIP for IVB: | |
9981 | * "The full packet must be contained within the same cache line." | |
9982 | * | |
9983 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
9984 | * cacheline, if we ever start emitting more commands before | |
9985 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
9986 | * then do the cacheline alignment, and finally emit the | |
9987 | * MI_DISPLAY_FLIP. | |
9988 | */ | |
9989 | ret = intel_ring_cacheline_align(ring); | |
9990 | if (ret) | |
4fa62c89 | 9991 | return ret; |
f66fab8e | 9992 | |
ffe74d75 | 9993 | ret = intel_ring_begin(ring, len); |
7c9017e5 | 9994 | if (ret) |
4fa62c89 | 9995 | return ret; |
7c9017e5 | 9996 | |
ffe74d75 CW |
9997 | /* Unmask the flip-done completion message. Note that the bspec says that |
9998 | * we should do this for both the BCS and RCS, and that we must not unmask | |
9999 | * more than one flip event at any time (or ensure that one flip message | |
10000 | * can be sent by waiting for flip-done prior to queueing new flips). | |
10001 | * Experimentation says that BCS works despite DERRMR masking all | |
10002 | * flip-done completion events and that unmasking all planes at once | |
10003 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
10004 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
10005 | */ | |
10006 | if (ring->id == RCS) { | |
10007 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
10008 | intel_ring_emit(ring, DERRMR); | |
10009 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
10010 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
10011 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a DL |
10012 | if (IS_GEN8(dev)) |
10013 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) | | |
10014 | MI_SRM_LRM_GLOBAL_GTT); | |
10015 | else | |
10016 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | | |
10017 | MI_SRM_LRM_GLOBAL_GTT); | |
ffe74d75 CW |
10018 | intel_ring_emit(ring, DERRMR); |
10019 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
f476828a DL |
10020 | if (IS_GEN8(dev)) { |
10021 | intel_ring_emit(ring, 0); | |
10022 | intel_ring_emit(ring, MI_NOOP); | |
10023 | } | |
ffe74d75 CW |
10024 | } |
10025 | ||
cb05d8de | 10026 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 10027 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
75f7f3ec | 10028 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
7c9017e5 | 10029 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
10030 | |
10031 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 10032 | __intel_ring_advance(ring); |
83d4092b | 10033 | return 0; |
7c9017e5 JB |
10034 | } |
10035 | ||
84c33a64 SG |
10036 | static bool use_mmio_flip(struct intel_engine_cs *ring, |
10037 | struct drm_i915_gem_object *obj) | |
10038 | { | |
10039 | /* | |
10040 | * This is not being used for older platforms, because | |
10041 | * non-availability of flip done interrupt forces us to use | |
10042 | * CS flips. Older platforms derive flip done using some clever | |
10043 | * tricks involving the flip_pending status bits and vblank irqs. | |
10044 | * So using MMIO flips there would disrupt this mechanism. | |
10045 | */ | |
10046 | ||
8e09bf83 CW |
10047 | if (ring == NULL) |
10048 | return true; | |
10049 | ||
84c33a64 SG |
10050 | if (INTEL_INFO(ring->dev)->gen < 5) |
10051 | return false; | |
10052 | ||
10053 | if (i915.use_mmio_flip < 0) | |
10054 | return false; | |
10055 | else if (i915.use_mmio_flip > 0) | |
10056 | return true; | |
14bf993e OM |
10057 | else if (i915.enable_execlists) |
10058 | return true; | |
84c33a64 | 10059 | else |
41c52415 | 10060 | return ring != i915_gem_request_get_ring(obj->last_read_req); |
84c33a64 SG |
10061 | } |
10062 | ||
ff944564 DL |
10063 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc) |
10064 | { | |
10065 | struct drm_device *dev = intel_crtc->base.dev; | |
10066 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10067 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; | |
10068 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
10069 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
10070 | const enum pipe pipe = intel_crtc->pipe; | |
10071 | u32 ctl, stride; | |
10072 | ||
10073 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
10074 | ctl &= ~PLANE_CTL_TILED_MASK; | |
10075 | if (obj->tiling_mode == I915_TILING_X) | |
10076 | ctl |= PLANE_CTL_TILED_X; | |
10077 | ||
10078 | /* | |
10079 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
10080 | * linear buffers or in number of tiles for tiled buffers. | |
10081 | */ | |
10082 | stride = fb->pitches[0] >> 6; | |
10083 | if (obj->tiling_mode == I915_TILING_X) | |
10084 | stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */ | |
10085 | ||
10086 | /* | |
10087 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
10088 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
10089 | */ | |
10090 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
10091 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
10092 | ||
10093 | I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset); | |
10094 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
10095 | } | |
10096 | ||
10097 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc) | |
84c33a64 SG |
10098 | { |
10099 | struct drm_device *dev = intel_crtc->base.dev; | |
10100 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10101 | struct intel_framebuffer *intel_fb = | |
10102 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
10103 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
10104 | u32 dspcntr; | |
10105 | u32 reg; | |
10106 | ||
84c33a64 SG |
10107 | reg = DSPCNTR(intel_crtc->plane); |
10108 | dspcntr = I915_READ(reg); | |
10109 | ||
c5d97472 DL |
10110 | if (obj->tiling_mode != I915_TILING_NONE) |
10111 | dspcntr |= DISPPLANE_TILED; | |
10112 | else | |
10113 | dspcntr &= ~DISPPLANE_TILED; | |
10114 | ||
84c33a64 SG |
10115 | I915_WRITE(reg, dspcntr); |
10116 | ||
10117 | I915_WRITE(DSPSURF(intel_crtc->plane), | |
10118 | intel_crtc->unpin_work->gtt_offset); | |
10119 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
84c33a64 | 10120 | |
ff944564 DL |
10121 | } |
10122 | ||
10123 | /* | |
10124 | * XXX: This is the temporary way to update the plane registers until we get | |
10125 | * around to using the usual plane update functions for MMIO flips | |
10126 | */ | |
10127 | static void intel_do_mmio_flip(struct intel_crtc *intel_crtc) | |
10128 | { | |
10129 | struct drm_device *dev = intel_crtc->base.dev; | |
10130 | bool atomic_update; | |
10131 | u32 start_vbl_count; | |
10132 | ||
10133 | intel_mark_page_flip_active(intel_crtc); | |
10134 | ||
10135 | atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count); | |
10136 | ||
10137 | if (INTEL_INFO(dev)->gen >= 9) | |
10138 | skl_do_mmio_flip(intel_crtc); | |
10139 | else | |
10140 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
10141 | ilk_do_mmio_flip(intel_crtc); | |
10142 | ||
9362c7c5 ACO |
10143 | if (atomic_update) |
10144 | intel_pipe_update_end(intel_crtc, start_vbl_count); | |
84c33a64 SG |
10145 | } |
10146 | ||
9362c7c5 | 10147 | static void intel_mmio_flip_work_func(struct work_struct *work) |
84c33a64 | 10148 | { |
cc8c4cc2 | 10149 | struct intel_crtc *crtc = |
9362c7c5 | 10150 | container_of(work, struct intel_crtc, mmio_flip.work); |
cc8c4cc2 | 10151 | struct intel_mmio_flip *mmio_flip; |
84c33a64 | 10152 | |
cc8c4cc2 JH |
10153 | mmio_flip = &crtc->mmio_flip; |
10154 | if (mmio_flip->req) | |
9c654818 JH |
10155 | WARN_ON(__i915_wait_request(mmio_flip->req, |
10156 | crtc->reset_counter, | |
10157 | false, NULL, NULL) != 0); | |
84c33a64 | 10158 | |
cc8c4cc2 JH |
10159 | intel_do_mmio_flip(crtc); |
10160 | if (mmio_flip->req) { | |
10161 | mutex_lock(&crtc->base.dev->struct_mutex); | |
146d84f0 | 10162 | i915_gem_request_assign(&mmio_flip->req, NULL); |
cc8c4cc2 JH |
10163 | mutex_unlock(&crtc->base.dev->struct_mutex); |
10164 | } | |
84c33a64 SG |
10165 | } |
10166 | ||
10167 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
10168 | struct drm_crtc *crtc, | |
10169 | struct drm_framebuffer *fb, | |
10170 | struct drm_i915_gem_object *obj, | |
10171 | struct intel_engine_cs *ring, | |
10172 | uint32_t flags) | |
10173 | { | |
84c33a64 | 10174 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
84c33a64 | 10175 | |
cc8c4cc2 JH |
10176 | i915_gem_request_assign(&intel_crtc->mmio_flip.req, |
10177 | obj->last_write_req); | |
536f5b5e ACO |
10178 | |
10179 | schedule_work(&intel_crtc->mmio_flip.work); | |
84c33a64 | 10180 | |
84c33a64 SG |
10181 | return 0; |
10182 | } | |
10183 | ||
8c9f3aaf JB |
10184 | static int intel_default_queue_flip(struct drm_device *dev, |
10185 | struct drm_crtc *crtc, | |
10186 | struct drm_framebuffer *fb, | |
ed8d1975 | 10187 | struct drm_i915_gem_object *obj, |
a4872ba6 | 10188 | struct intel_engine_cs *ring, |
ed8d1975 | 10189 | uint32_t flags) |
8c9f3aaf JB |
10190 | { |
10191 | return -ENODEV; | |
10192 | } | |
10193 | ||
d6bbafa1 CW |
10194 | static bool __intel_pageflip_stall_check(struct drm_device *dev, |
10195 | struct drm_crtc *crtc) | |
10196 | { | |
10197 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10198 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10199 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
10200 | u32 addr; | |
10201 | ||
10202 | if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) | |
10203 | return true; | |
10204 | ||
10205 | if (!work->enable_stall_check) | |
10206 | return false; | |
10207 | ||
10208 | if (work->flip_ready_vblank == 0) { | |
3a8a946e DV |
10209 | if (work->flip_queued_req && |
10210 | !i915_gem_request_completed(work->flip_queued_req, true)) | |
d6bbafa1 CW |
10211 | return false; |
10212 | ||
1e3feefd | 10213 | work->flip_ready_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 CW |
10214 | } |
10215 | ||
1e3feefd | 10216 | if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) |
d6bbafa1 CW |
10217 | return false; |
10218 | ||
10219 | /* Potential stall - if we see that the flip has happened, | |
10220 | * assume a missed interrupt. */ | |
10221 | if (INTEL_INFO(dev)->gen >= 4) | |
10222 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
10223 | else | |
10224 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
10225 | ||
10226 | /* There is a potential issue here with a false positive after a flip | |
10227 | * to the same address. We could address this by checking for a | |
10228 | * non-incrementing frame counter. | |
10229 | */ | |
10230 | return addr == work->gtt_offset; | |
10231 | } | |
10232 | ||
10233 | void intel_check_page_flip(struct drm_device *dev, int pipe) | |
10234 | { | |
10235 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10236 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
10237 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6ad790c0 | 10238 | struct intel_unpin_work *work; |
f326038a | 10239 | |
6c51d46f | 10240 | WARN_ON(!in_interrupt()); |
d6bbafa1 CW |
10241 | |
10242 | if (crtc == NULL) | |
10243 | return; | |
10244 | ||
f326038a | 10245 | spin_lock(&dev->event_lock); |
6ad790c0 CW |
10246 | work = intel_crtc->unpin_work; |
10247 | if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) { | |
d6bbafa1 | 10248 | WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", |
6ad790c0 | 10249 | work->flip_queued_vblank, drm_vblank_count(dev, pipe)); |
d6bbafa1 | 10250 | page_flip_completed(intel_crtc); |
6ad790c0 | 10251 | work = NULL; |
d6bbafa1 | 10252 | } |
6ad790c0 CW |
10253 | if (work != NULL && |
10254 | drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1) | |
10255 | intel_queue_rps_boost_for_request(dev, work->flip_queued_req); | |
f326038a | 10256 | spin_unlock(&dev->event_lock); |
d6bbafa1 CW |
10257 | } |
10258 | ||
6b95a207 KH |
10259 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
10260 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
10261 | struct drm_pending_vblank_event *event, |
10262 | uint32_t page_flip_flags) | |
6b95a207 KH |
10263 | { |
10264 | struct drm_device *dev = crtc->dev; | |
10265 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 10266 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 10267 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 | 10268 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
455a6808 | 10269 | struct drm_plane *primary = crtc->primary; |
a071fa00 | 10270 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 10271 | struct intel_unpin_work *work; |
a4872ba6 | 10272 | struct intel_engine_cs *ring; |
cf5d8a46 | 10273 | bool mmio_flip; |
52e68630 | 10274 | int ret; |
6b95a207 | 10275 | |
2ff8fde1 MR |
10276 | /* |
10277 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
10278 | * check to be safe. In the future we may enable pageflipping from | |
10279 | * a disabled primary plane. | |
10280 | */ | |
10281 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
10282 | return -EBUSY; | |
10283 | ||
e6a595d2 | 10284 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 10285 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
10286 | return -EINVAL; |
10287 | ||
10288 | /* | |
10289 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
10290 | * Note that pitch changes could also affect these register. | |
10291 | */ | |
10292 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
10293 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
10294 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
10295 | return -EINVAL; |
10296 | ||
f900db47 CW |
10297 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
10298 | goto out_hang; | |
10299 | ||
b14c5679 | 10300 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
10301 | if (work == NULL) |
10302 | return -ENOMEM; | |
10303 | ||
6b95a207 | 10304 | work->event = event; |
b4a98e57 | 10305 | work->crtc = crtc; |
ab8d6675 | 10306 | work->old_fb = old_fb; |
6b95a207 KH |
10307 | INIT_WORK(&work->work, intel_unpin_work_fn); |
10308 | ||
87b6b101 | 10309 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
10310 | if (ret) |
10311 | goto free_work; | |
10312 | ||
6b95a207 | 10313 | /* We borrow the event spin lock for protecting unpin_work */ |
5e2d7afc | 10314 | spin_lock_irq(&dev->event_lock); |
6b95a207 | 10315 | if (intel_crtc->unpin_work) { |
d6bbafa1 CW |
10316 | /* Before declaring the flip queue wedged, check if |
10317 | * the hardware completed the operation behind our backs. | |
10318 | */ | |
10319 | if (__intel_pageflip_stall_check(dev, crtc)) { | |
10320 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
10321 | page_flip_completed(intel_crtc); | |
10322 | } else { | |
10323 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
5e2d7afc | 10324 | spin_unlock_irq(&dev->event_lock); |
468f0b44 | 10325 | |
d6bbafa1 CW |
10326 | drm_crtc_vblank_put(crtc); |
10327 | kfree(work); | |
10328 | return -EBUSY; | |
10329 | } | |
6b95a207 KH |
10330 | } |
10331 | intel_crtc->unpin_work = work; | |
5e2d7afc | 10332 | spin_unlock_irq(&dev->event_lock); |
6b95a207 | 10333 | |
b4a98e57 CW |
10334 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
10335 | flush_workqueue(dev_priv->wq); | |
10336 | ||
75dfca80 | 10337 | /* Reference the objects for the scheduled work. */ |
ab8d6675 | 10338 | drm_framebuffer_reference(work->old_fb); |
05394f39 | 10339 | drm_gem_object_reference(&obj->base); |
6b95a207 | 10340 | |
f4510a27 | 10341 | crtc->primary->fb = fb; |
afd65eb4 | 10342 | update_state_fb(crtc->primary); |
1ed1f968 | 10343 | |
e1f99ce6 | 10344 | work->pending_flip_obj = obj; |
e1f99ce6 | 10345 | |
89ed88ba CW |
10346 | ret = i915_mutex_lock_interruptible(dev); |
10347 | if (ret) | |
10348 | goto cleanup; | |
10349 | ||
b4a98e57 | 10350 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 10351 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 10352 | |
75f7f3ec | 10353 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
a071fa00 | 10354 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1; |
75f7f3ec | 10355 | |
4fa62c89 VS |
10356 | if (IS_VALLEYVIEW(dev)) { |
10357 | ring = &dev_priv->ring[BCS]; | |
ab8d6675 | 10358 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) |
8e09bf83 CW |
10359 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
10360 | ring = NULL; | |
48bf5b2d | 10361 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
2a92d5bc | 10362 | ring = &dev_priv->ring[BCS]; |
4fa62c89 | 10363 | } else if (INTEL_INFO(dev)->gen >= 7) { |
41c52415 | 10364 | ring = i915_gem_request_get_ring(obj->last_read_req); |
4fa62c89 VS |
10365 | if (ring == NULL || ring->id != RCS) |
10366 | ring = &dev_priv->ring[BCS]; | |
10367 | } else { | |
10368 | ring = &dev_priv->ring[RCS]; | |
10369 | } | |
10370 | ||
cf5d8a46 CW |
10371 | mmio_flip = use_mmio_flip(ring, obj); |
10372 | ||
10373 | /* When using CS flips, we want to emit semaphores between rings. | |
10374 | * However, when using mmio flips we will create a task to do the | |
10375 | * synchronisation, so all we want here is to pin the framebuffer | |
10376 | * into the display plane and skip any waits. | |
10377 | */ | |
82bc3b2d | 10378 | ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, |
cf5d8a46 CW |
10379 | crtc->primary->state, |
10380 | mmio_flip ? i915_gem_request_get_ring(obj->last_read_req) : ring); | |
8c9f3aaf JB |
10381 | if (ret) |
10382 | goto cleanup_pending; | |
6b95a207 | 10383 | |
121920fa TU |
10384 | work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj) |
10385 | + intel_crtc->dspaddr_offset; | |
4fa62c89 | 10386 | |
cf5d8a46 | 10387 | if (mmio_flip) { |
84c33a64 SG |
10388 | ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring, |
10389 | page_flip_flags); | |
d6bbafa1 CW |
10390 | if (ret) |
10391 | goto cleanup_unpin; | |
10392 | ||
f06cc1b9 JH |
10393 | i915_gem_request_assign(&work->flip_queued_req, |
10394 | obj->last_write_req); | |
d6bbafa1 | 10395 | } else { |
84c33a64 | 10396 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, |
d6bbafa1 CW |
10397 | page_flip_flags); |
10398 | if (ret) | |
10399 | goto cleanup_unpin; | |
10400 | ||
f06cc1b9 JH |
10401 | i915_gem_request_assign(&work->flip_queued_req, |
10402 | intel_ring_get_request(ring)); | |
d6bbafa1 CW |
10403 | } |
10404 | ||
1e3feefd | 10405 | work->flip_queued_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 | 10406 | work->enable_stall_check = true; |
4fa62c89 | 10407 | |
ab8d6675 | 10408 | i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, |
a071fa00 DV |
10409 | INTEL_FRONTBUFFER_PRIMARY(pipe)); |
10410 | ||
7ff0ebcc | 10411 | intel_fbc_disable(dev); |
f99d7069 | 10412 | intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
6b95a207 KH |
10413 | mutex_unlock(&dev->struct_mutex); |
10414 | ||
e5510fac JB |
10415 | trace_i915_flip_request(intel_crtc->plane, obj); |
10416 | ||
6b95a207 | 10417 | return 0; |
96b099fd | 10418 | |
4fa62c89 | 10419 | cleanup_unpin: |
82bc3b2d | 10420 | intel_unpin_fb_obj(fb, crtc->primary->state); |
8c9f3aaf | 10421 | cleanup_pending: |
b4a98e57 | 10422 | atomic_dec(&intel_crtc->unpin_work_count); |
89ed88ba CW |
10423 | mutex_unlock(&dev->struct_mutex); |
10424 | cleanup: | |
f4510a27 | 10425 | crtc->primary->fb = old_fb; |
afd65eb4 | 10426 | update_state_fb(crtc->primary); |
89ed88ba CW |
10427 | |
10428 | drm_gem_object_unreference_unlocked(&obj->base); | |
ab8d6675 | 10429 | drm_framebuffer_unreference(work->old_fb); |
96b099fd | 10430 | |
5e2d7afc | 10431 | spin_lock_irq(&dev->event_lock); |
96b099fd | 10432 | intel_crtc->unpin_work = NULL; |
5e2d7afc | 10433 | spin_unlock_irq(&dev->event_lock); |
96b099fd | 10434 | |
87b6b101 | 10435 | drm_crtc_vblank_put(crtc); |
7317c75e | 10436 | free_work: |
96b099fd CW |
10437 | kfree(work); |
10438 | ||
f900db47 CW |
10439 | if (ret == -EIO) { |
10440 | out_hang: | |
53a366b9 | 10441 | ret = intel_plane_restore(primary); |
f0d3dad3 | 10442 | if (ret == 0 && event) { |
5e2d7afc | 10443 | spin_lock_irq(&dev->event_lock); |
a071fa00 | 10444 | drm_send_vblank_event(dev, pipe, event); |
5e2d7afc | 10445 | spin_unlock_irq(&dev->event_lock); |
f0d3dad3 | 10446 | } |
f900db47 | 10447 | } |
96b099fd | 10448 | return ret; |
6b95a207 KH |
10449 | } |
10450 | ||
f6e5b160 | 10451 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
10452 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
10453 | .load_lut = intel_crtc_load_lut, | |
ea2c67bb MR |
10454 | .atomic_begin = intel_begin_crtc_commit, |
10455 | .atomic_flush = intel_finish_crtc_commit, | |
f6e5b160 CW |
10456 | }; |
10457 | ||
9a935856 DV |
10458 | /** |
10459 | * intel_modeset_update_staged_output_state | |
10460 | * | |
10461 | * Updates the staged output configuration state, e.g. after we've read out the | |
10462 | * current hw state. | |
10463 | */ | |
10464 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) | |
f6e5b160 | 10465 | { |
7668851f | 10466 | struct intel_crtc *crtc; |
9a935856 DV |
10467 | struct intel_encoder *encoder; |
10468 | struct intel_connector *connector; | |
f6e5b160 | 10469 | |
3a3371ff | 10470 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
10471 | connector->new_encoder = |
10472 | to_intel_encoder(connector->base.encoder); | |
10473 | } | |
f6e5b160 | 10474 | |
b2784e15 | 10475 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
10476 | encoder->new_crtc = |
10477 | to_intel_crtc(encoder->base.crtc); | |
10478 | } | |
7668851f | 10479 | |
d3fcc808 | 10480 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 10481 | crtc->new_enabled = crtc->base.state->enable; |
7668851f | 10482 | } |
f6e5b160 CW |
10483 | } |
10484 | ||
d29b2f9d ACO |
10485 | /* Transitional helper to copy current connector/encoder state to |
10486 | * connector->state. This is needed so that code that is partially | |
10487 | * converted to atomic does the right thing. | |
10488 | */ | |
10489 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) | |
10490 | { | |
10491 | struct intel_connector *connector; | |
10492 | ||
10493 | for_each_intel_connector(dev, connector) { | |
10494 | if (connector->base.encoder) { | |
10495 | connector->base.state->best_encoder = | |
10496 | connector->base.encoder; | |
10497 | connector->base.state->crtc = | |
10498 | connector->base.encoder->crtc; | |
10499 | } else { | |
10500 | connector->base.state->best_encoder = NULL; | |
10501 | connector->base.state->crtc = NULL; | |
10502 | } | |
10503 | } | |
10504 | } | |
10505 | ||
9a935856 DV |
10506 | /** |
10507 | * intel_modeset_commit_output_state | |
10508 | * | |
10509 | * This function copies the stage display pipe configuration to the real one. | |
10510 | */ | |
10511 | static void intel_modeset_commit_output_state(struct drm_device *dev) | |
10512 | { | |
7668851f | 10513 | struct intel_crtc *crtc; |
9a935856 DV |
10514 | struct intel_encoder *encoder; |
10515 | struct intel_connector *connector; | |
f6e5b160 | 10516 | |
3a3371ff | 10517 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
10518 | connector->base.encoder = &connector->new_encoder->base; |
10519 | } | |
f6e5b160 | 10520 | |
b2784e15 | 10521 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
10522 | encoder->base.crtc = &encoder->new_crtc->base; |
10523 | } | |
7668851f | 10524 | |
d3fcc808 | 10525 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 10526 | crtc->base.state->enable = crtc->new_enabled; |
7668851f VS |
10527 | crtc->base.enabled = crtc->new_enabled; |
10528 | } | |
d29b2f9d ACO |
10529 | |
10530 | intel_modeset_update_connector_atomic_state(dev); | |
9a935856 DV |
10531 | } |
10532 | ||
050f7aeb | 10533 | static void |
eba905b2 | 10534 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 10535 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
10536 | { |
10537 | int bpp = pipe_config->pipe_bpp; | |
10538 | ||
10539 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
10540 | connector->base.base.id, | |
c23cc417 | 10541 | connector->base.name); |
050f7aeb DV |
10542 | |
10543 | /* Don't use an invalid EDID bpc value */ | |
10544 | if (connector->base.display_info.bpc && | |
10545 | connector->base.display_info.bpc * 3 < bpp) { | |
10546 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
10547 | bpp, connector->base.display_info.bpc*3); | |
10548 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
10549 | } | |
10550 | ||
10551 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
10552 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
10553 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
10554 | bpp); | |
10555 | pipe_config->pipe_bpp = 24; | |
10556 | } | |
10557 | } | |
10558 | ||
4e53c2e0 | 10559 | static int |
050f7aeb DV |
10560 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
10561 | struct drm_framebuffer *fb, | |
5cec258b | 10562 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 10563 | { |
050f7aeb | 10564 | struct drm_device *dev = crtc->base.dev; |
1486017f | 10565 | struct drm_atomic_state *state; |
050f7aeb | 10566 | struct intel_connector *connector; |
1486017f | 10567 | int bpp, i; |
4e53c2e0 | 10568 | |
d42264b1 DV |
10569 | switch (fb->pixel_format) { |
10570 | case DRM_FORMAT_C8: | |
4e53c2e0 DV |
10571 | bpp = 8*3; /* since we go through a colormap */ |
10572 | break; | |
d42264b1 DV |
10573 | case DRM_FORMAT_XRGB1555: |
10574 | case DRM_FORMAT_ARGB1555: | |
10575 | /* checked in intel_framebuffer_init already */ | |
10576 | if (WARN_ON(INTEL_INFO(dev)->gen > 3)) | |
10577 | return -EINVAL; | |
10578 | case DRM_FORMAT_RGB565: | |
4e53c2e0 DV |
10579 | bpp = 6*3; /* min is 18bpp */ |
10580 | break; | |
d42264b1 DV |
10581 | case DRM_FORMAT_XBGR8888: |
10582 | case DRM_FORMAT_ABGR8888: | |
10583 | /* checked in intel_framebuffer_init already */ | |
10584 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
10585 | return -EINVAL; | |
10586 | case DRM_FORMAT_XRGB8888: | |
10587 | case DRM_FORMAT_ARGB8888: | |
4e53c2e0 DV |
10588 | bpp = 8*3; |
10589 | break; | |
d42264b1 DV |
10590 | case DRM_FORMAT_XRGB2101010: |
10591 | case DRM_FORMAT_ARGB2101010: | |
10592 | case DRM_FORMAT_XBGR2101010: | |
10593 | case DRM_FORMAT_ABGR2101010: | |
10594 | /* checked in intel_framebuffer_init already */ | |
10595 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
baba133a | 10596 | return -EINVAL; |
4e53c2e0 DV |
10597 | bpp = 10*3; |
10598 | break; | |
baba133a | 10599 | /* TODO: gen4+ supports 16 bpc floating point, too. */ |
4e53c2e0 DV |
10600 | default: |
10601 | DRM_DEBUG_KMS("unsupported depth\n"); | |
10602 | return -EINVAL; | |
10603 | } | |
10604 | ||
4e53c2e0 DV |
10605 | pipe_config->pipe_bpp = bpp; |
10606 | ||
1486017f ACO |
10607 | state = pipe_config->base.state; |
10608 | ||
4e53c2e0 | 10609 | /* Clamp display bpp to EDID value */ |
1486017f ACO |
10610 | for (i = 0; i < state->num_connector; i++) { |
10611 | if (!state->connectors[i]) | |
10612 | continue; | |
10613 | ||
10614 | connector = to_intel_connector(state->connectors[i]); | |
10615 | if (state->connector_states[i]->crtc != &crtc->base) | |
4e53c2e0 DV |
10616 | continue; |
10617 | ||
050f7aeb | 10618 | connected_sink_compute_bpp(connector, pipe_config); |
4e53c2e0 DV |
10619 | } |
10620 | ||
10621 | return bpp; | |
10622 | } | |
10623 | ||
644db711 DV |
10624 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
10625 | { | |
10626 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
10627 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 10628 | mode->crtc_clock, |
644db711 DV |
10629 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
10630 | mode->crtc_hsync_end, mode->crtc_htotal, | |
10631 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
10632 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
10633 | } | |
10634 | ||
c0b03411 | 10635 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 10636 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
10637 | const char *context) |
10638 | { | |
10639 | DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id, | |
10640 | context, pipe_name(crtc->pipe)); | |
10641 | ||
10642 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
10643 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
10644 | pipe_config->pipe_bpp, pipe_config->dither); | |
10645 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
10646 | pipe_config->has_pch_encoder, | |
10647 | pipe_config->fdi_lanes, | |
10648 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
10649 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
10650 | pipe_config->fdi_m_n.tu); | |
eb14cb74 VS |
10651 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
10652 | pipe_config->has_dp_encoder, | |
10653 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, | |
10654 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
10655 | pipe_config->dp_m_n.tu); | |
b95af8be VK |
10656 | |
10657 | DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", | |
10658 | pipe_config->has_dp_encoder, | |
10659 | pipe_config->dp_m2_n2.gmch_m, | |
10660 | pipe_config->dp_m2_n2.gmch_n, | |
10661 | pipe_config->dp_m2_n2.link_m, | |
10662 | pipe_config->dp_m2_n2.link_n, | |
10663 | pipe_config->dp_m2_n2.tu); | |
10664 | ||
55072d19 DV |
10665 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
10666 | pipe_config->has_audio, | |
10667 | pipe_config->has_infoframe); | |
10668 | ||
c0b03411 | 10669 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 10670 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 10671 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
10672 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
10673 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 10674 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
10675 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
10676 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
c0b03411 DV |
10677 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
10678 | pipe_config->gmch_pfit.control, | |
10679 | pipe_config->gmch_pfit.pgm_ratios, | |
10680 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 10681 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 10682 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
10683 | pipe_config->pch_pfit.size, |
10684 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 10685 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 10686 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
c0b03411 DV |
10687 | } |
10688 | ||
bc079e8b VS |
10689 | static bool encoders_cloneable(const struct intel_encoder *a, |
10690 | const struct intel_encoder *b) | |
accfc0c5 | 10691 | { |
bc079e8b VS |
10692 | /* masks could be asymmetric, so check both ways */ |
10693 | return a == b || (a->cloneable & (1 << b->type) && | |
10694 | b->cloneable & (1 << a->type)); | |
10695 | } | |
10696 | ||
98a221da ACO |
10697 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, |
10698 | struct intel_crtc *crtc, | |
bc079e8b VS |
10699 | struct intel_encoder *encoder) |
10700 | { | |
bc079e8b | 10701 | struct intel_encoder *source_encoder; |
98a221da ACO |
10702 | struct drm_connector_state *connector_state; |
10703 | int i; | |
10704 | ||
10705 | for (i = 0; i < state->num_connector; i++) { | |
10706 | if (!state->connectors[i]) | |
10707 | continue; | |
bc079e8b | 10708 | |
98a221da ACO |
10709 | connector_state = state->connector_states[i]; |
10710 | if (connector_state->crtc != &crtc->base) | |
bc079e8b VS |
10711 | continue; |
10712 | ||
98a221da ACO |
10713 | source_encoder = |
10714 | to_intel_encoder(connector_state->best_encoder); | |
bc079e8b VS |
10715 | if (!encoders_cloneable(encoder, source_encoder)) |
10716 | return false; | |
10717 | } | |
10718 | ||
10719 | return true; | |
10720 | } | |
10721 | ||
98a221da ACO |
10722 | static bool check_encoder_cloning(struct drm_atomic_state *state, |
10723 | struct intel_crtc *crtc) | |
bc079e8b | 10724 | { |
accfc0c5 | 10725 | struct intel_encoder *encoder; |
98a221da ACO |
10726 | struct drm_connector_state *connector_state; |
10727 | int i; | |
accfc0c5 | 10728 | |
98a221da ACO |
10729 | for (i = 0; i < state->num_connector; i++) { |
10730 | if (!state->connectors[i]) | |
accfc0c5 DV |
10731 | continue; |
10732 | ||
98a221da ACO |
10733 | connector_state = state->connector_states[i]; |
10734 | if (connector_state->crtc != &crtc->base) | |
10735 | continue; | |
10736 | ||
10737 | encoder = to_intel_encoder(connector_state->best_encoder); | |
10738 | if (!check_single_encoder_cloning(state, crtc, encoder)) | |
bc079e8b | 10739 | return false; |
accfc0c5 DV |
10740 | } |
10741 | ||
bc079e8b | 10742 | return true; |
accfc0c5 DV |
10743 | } |
10744 | ||
5448a00d | 10745 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 10746 | { |
5448a00d ACO |
10747 | struct drm_device *dev = state->dev; |
10748 | struct intel_encoder *encoder; | |
10749 | struct drm_connector_state *connector_state; | |
00f0b378 | 10750 | unsigned int used_ports = 0; |
5448a00d | 10751 | int i; |
00f0b378 VS |
10752 | |
10753 | /* | |
10754 | * Walk the connector list instead of the encoder | |
10755 | * list to detect the problem on ddi platforms | |
10756 | * where there's just one encoder per digital port. | |
10757 | */ | |
5448a00d ACO |
10758 | for (i = 0; i < state->num_connector; i++) { |
10759 | if (!state->connectors[i]) | |
10760 | continue; | |
00f0b378 | 10761 | |
5448a00d ACO |
10762 | connector_state = state->connector_states[i]; |
10763 | if (!connector_state->best_encoder) | |
00f0b378 VS |
10764 | continue; |
10765 | ||
5448a00d ACO |
10766 | encoder = to_intel_encoder(connector_state->best_encoder); |
10767 | ||
10768 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
10769 | |
10770 | switch (encoder->type) { | |
10771 | unsigned int port_mask; | |
10772 | case INTEL_OUTPUT_UNKNOWN: | |
10773 | if (WARN_ON(!HAS_DDI(dev))) | |
10774 | break; | |
10775 | case INTEL_OUTPUT_DISPLAYPORT: | |
10776 | case INTEL_OUTPUT_HDMI: | |
10777 | case INTEL_OUTPUT_EDP: | |
10778 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
10779 | ||
10780 | /* the same port mustn't appear more than once */ | |
10781 | if (used_ports & port_mask) | |
10782 | return false; | |
10783 | ||
10784 | used_ports |= port_mask; | |
10785 | default: | |
10786 | break; | |
10787 | } | |
10788 | } | |
10789 | ||
10790 | return true; | |
10791 | } | |
10792 | ||
83a57153 ACO |
10793 | static void |
10794 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
10795 | { | |
10796 | struct drm_crtc_state tmp_state; | |
10797 | ||
10798 | /* Clear only the intel specific part of the crtc state */ | |
10799 | tmp_state = crtc_state->base; | |
10800 | memset(crtc_state, 0, sizeof *crtc_state); | |
10801 | crtc_state->base = tmp_state; | |
10802 | } | |
10803 | ||
5cec258b | 10804 | static struct intel_crtc_state * |
b8cecdf5 | 10805 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
4e53c2e0 | 10806 | struct drm_framebuffer *fb, |
83a57153 ACO |
10807 | struct drm_display_mode *mode, |
10808 | struct drm_atomic_state *state) | |
ee7b9f93 | 10809 | { |
7758a113 | 10810 | struct intel_encoder *encoder; |
0b901879 ACO |
10811 | struct intel_connector *connector; |
10812 | struct drm_connector_state *connector_state; | |
5cec258b | 10813 | struct intel_crtc_state *pipe_config; |
e29c22c0 | 10814 | int plane_bpp, ret = -EINVAL; |
0b901879 | 10815 | int i; |
e29c22c0 | 10816 | bool retry = true; |
ee7b9f93 | 10817 | |
98a221da | 10818 | if (!check_encoder_cloning(state, to_intel_crtc(crtc))) { |
accfc0c5 DV |
10819 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
10820 | return ERR_PTR(-EINVAL); | |
10821 | } | |
10822 | ||
5448a00d | 10823 | if (!check_digital_port_conflicts(state)) { |
00f0b378 VS |
10824 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); |
10825 | return ERR_PTR(-EINVAL); | |
10826 | } | |
10827 | ||
83a57153 ACO |
10828 | pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc)); |
10829 | if (IS_ERR(pipe_config)) | |
10830 | return pipe_config; | |
10831 | ||
10832 | clear_intel_crtc_state(pipe_config); | |
7758a113 | 10833 | |
07878248 | 10834 | pipe_config->base.crtc = crtc; |
2d112de7 ACO |
10835 | drm_mode_copy(&pipe_config->base.adjusted_mode, mode); |
10836 | drm_mode_copy(&pipe_config->base.mode, mode); | |
37327abd | 10837 | |
e143a21c DV |
10838 | pipe_config->cpu_transcoder = |
10839 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
c0d43d62 | 10840 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
b8cecdf5 | 10841 | |
2960bc9c ID |
10842 | /* |
10843 | * Sanitize sync polarity flags based on requested ones. If neither | |
10844 | * positive or negative polarity is requested, treat this as meaning | |
10845 | * negative polarity. | |
10846 | */ | |
2d112de7 | 10847 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 10848 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 10849 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 10850 | |
2d112de7 | 10851 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 10852 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 10853 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 10854 | |
050f7aeb DV |
10855 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
10856 | * plane pixel format and any sink constraints into account. Returns the | |
10857 | * source plane bpp so that dithering can be selected on mismatches | |
10858 | * after encoders and crtc also have had their say. */ | |
10859 | plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), | |
10860 | fb, pipe_config); | |
4e53c2e0 DV |
10861 | if (plane_bpp < 0) |
10862 | goto fail; | |
10863 | ||
e41a56be VS |
10864 | /* |
10865 | * Determine the real pipe dimensions. Note that stereo modes can | |
10866 | * increase the actual pipe size due to the frame doubling and | |
10867 | * insertion of additional space for blanks between the frame. This | |
10868 | * is stored in the crtc timings. We use the requested mode to do this | |
10869 | * computation to clearly distinguish it from the adjusted mode, which | |
10870 | * can be changed by the connectors in the below retry loop. | |
10871 | */ | |
2d112de7 | 10872 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
10873 | &pipe_config->pipe_src_w, |
10874 | &pipe_config->pipe_src_h); | |
e41a56be | 10875 | |
e29c22c0 | 10876 | encoder_retry: |
ef1b460d | 10877 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 10878 | pipe_config->port_clock = 0; |
ef1b460d | 10879 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 10880 | |
135c81b8 | 10881 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
10882 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
10883 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 10884 | |
7758a113 DV |
10885 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
10886 | * adjust it according to limitations or connector properties, and also | |
10887 | * a chance to reject the mode entirely. | |
47f1c6c9 | 10888 | */ |
0b901879 ACO |
10889 | for (i = 0; i < state->num_connector; i++) { |
10890 | connector = to_intel_connector(state->connectors[i]); | |
10891 | if (!connector) | |
10892 | continue; | |
47f1c6c9 | 10893 | |
0b901879 ACO |
10894 | connector_state = state->connector_states[i]; |
10895 | if (connector_state->crtc != crtc) | |
7758a113 | 10896 | continue; |
7ae89233 | 10897 | |
0b901879 ACO |
10898 | encoder = to_intel_encoder(connector_state->best_encoder); |
10899 | ||
efea6e8e DV |
10900 | if (!(encoder->compute_config(encoder, pipe_config))) { |
10901 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
10902 | goto fail; |
10903 | } | |
ee7b9f93 | 10904 | } |
47f1c6c9 | 10905 | |
ff9a6750 DV |
10906 | /* Set default port clock if not overwritten by the encoder. Needs to be |
10907 | * done afterwards in case the encoder adjusts the mode. */ | |
10908 | if (!pipe_config->port_clock) | |
2d112de7 | 10909 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 10910 | * pipe_config->pixel_multiplier; |
ff9a6750 | 10911 | |
a43f6e0f | 10912 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 10913 | if (ret < 0) { |
7758a113 DV |
10914 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
10915 | goto fail; | |
ee7b9f93 | 10916 | } |
e29c22c0 DV |
10917 | |
10918 | if (ret == RETRY) { | |
10919 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
10920 | ret = -EINVAL; | |
10921 | goto fail; | |
10922 | } | |
10923 | ||
10924 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
10925 | retry = false; | |
10926 | goto encoder_retry; | |
10927 | } | |
10928 | ||
4e53c2e0 DV |
10929 | pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; |
10930 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", | |
10931 | plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); | |
10932 | ||
b8cecdf5 | 10933 | return pipe_config; |
7758a113 | 10934 | fail: |
e29c22c0 | 10935 | return ERR_PTR(ret); |
ee7b9f93 | 10936 | } |
47f1c6c9 | 10937 | |
e2e1ed41 DV |
10938 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
10939 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ | |
10940 | static void | |
10941 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, | |
10942 | unsigned *prepare_pipes, unsigned *disable_pipes) | |
79e53945 JB |
10943 | { |
10944 | struct intel_crtc *intel_crtc; | |
e2e1ed41 DV |
10945 | struct drm_device *dev = crtc->dev; |
10946 | struct intel_encoder *encoder; | |
10947 | struct intel_connector *connector; | |
10948 | struct drm_crtc *tmp_crtc; | |
79e53945 | 10949 | |
e2e1ed41 | 10950 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
79e53945 | 10951 | |
e2e1ed41 DV |
10952 | /* Check which crtcs have changed outputs connected to them, these need |
10953 | * to be part of the prepare_pipes mask. We don't (yet) support global | |
10954 | * modeset across multiple crtcs, so modeset_pipes will only have one | |
10955 | * bit set at most. */ | |
3a3371ff | 10956 | for_each_intel_connector(dev, connector) { |
e2e1ed41 DV |
10957 | if (connector->base.encoder == &connector->new_encoder->base) |
10958 | continue; | |
79e53945 | 10959 | |
e2e1ed41 DV |
10960 | if (connector->base.encoder) { |
10961 | tmp_crtc = connector->base.encoder->crtc; | |
10962 | ||
10963 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
10964 | } | |
10965 | ||
10966 | if (connector->new_encoder) | |
10967 | *prepare_pipes |= | |
10968 | 1 << connector->new_encoder->new_crtc->pipe; | |
79e53945 JB |
10969 | } |
10970 | ||
b2784e15 | 10971 | for_each_intel_encoder(dev, encoder) { |
e2e1ed41 DV |
10972 | if (encoder->base.crtc == &encoder->new_crtc->base) |
10973 | continue; | |
10974 | ||
10975 | if (encoder->base.crtc) { | |
10976 | tmp_crtc = encoder->base.crtc; | |
10977 | ||
10978 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
10979 | } | |
10980 | ||
10981 | if (encoder->new_crtc) | |
10982 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; | |
80824003 JB |
10983 | } |
10984 | ||
7668851f | 10985 | /* Check for pipes that will be enabled/disabled ... */ |
d3fcc808 | 10986 | for_each_intel_crtc(dev, intel_crtc) { |
83d65738 | 10987 | if (intel_crtc->base.state->enable == intel_crtc->new_enabled) |
e2e1ed41 | 10988 | continue; |
7e7d76c3 | 10989 | |
7668851f | 10990 | if (!intel_crtc->new_enabled) |
e2e1ed41 | 10991 | *disable_pipes |= 1 << intel_crtc->pipe; |
7668851f VS |
10992 | else |
10993 | *prepare_pipes |= 1 << intel_crtc->pipe; | |
7e7d76c3 JB |
10994 | } |
10995 | ||
e2e1ed41 DV |
10996 | |
10997 | /* set_mode is also used to update properties on life display pipes. */ | |
10998 | intel_crtc = to_intel_crtc(crtc); | |
7668851f | 10999 | if (intel_crtc->new_enabled) |
e2e1ed41 DV |
11000 | *prepare_pipes |= 1 << intel_crtc->pipe; |
11001 | ||
b6c5164d DV |
11002 | /* |
11003 | * For simplicity do a full modeset on any pipe where the output routing | |
11004 | * changed. We could be more clever, but that would require us to be | |
11005 | * more careful with calling the relevant encoder->mode_set functions. | |
11006 | */ | |
e2e1ed41 DV |
11007 | if (*prepare_pipes) |
11008 | *modeset_pipes = *prepare_pipes; | |
11009 | ||
11010 | /* ... and mask these out. */ | |
11011 | *modeset_pipes &= ~(*disable_pipes); | |
11012 | *prepare_pipes &= ~(*disable_pipes); | |
b6c5164d DV |
11013 | |
11014 | /* | |
11015 | * HACK: We don't (yet) fully support global modesets. intel_set_config | |
11016 | * obies this rule, but the modeset restore mode of | |
11017 | * intel_modeset_setup_hw_state does not. | |
11018 | */ | |
11019 | *modeset_pipes &= 1 << intel_crtc->pipe; | |
11020 | *prepare_pipes &= 1 << intel_crtc->pipe; | |
e3641d3f DV |
11021 | |
11022 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", | |
11023 | *modeset_pipes, *prepare_pipes, *disable_pipes); | |
47f1c6c9 | 11024 | } |
79e53945 | 11025 | |
ea9d758d | 11026 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 11027 | { |
ea9d758d | 11028 | struct drm_encoder *encoder; |
f6e5b160 | 11029 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 11030 | |
ea9d758d DV |
11031 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
11032 | if (encoder->crtc == crtc) | |
11033 | return true; | |
11034 | ||
11035 | return false; | |
11036 | } | |
11037 | ||
11038 | static void | |
11039 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) | |
11040 | { | |
ba41c0de | 11041 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea9d758d DV |
11042 | struct intel_encoder *intel_encoder; |
11043 | struct intel_crtc *intel_crtc; | |
11044 | struct drm_connector *connector; | |
11045 | ||
ba41c0de DV |
11046 | intel_shared_dpll_commit(dev_priv); |
11047 | ||
b2784e15 | 11048 | for_each_intel_encoder(dev, intel_encoder) { |
ea9d758d DV |
11049 | if (!intel_encoder->base.crtc) |
11050 | continue; | |
11051 | ||
11052 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
11053 | ||
11054 | if (prepare_pipes & (1 << intel_crtc->pipe)) | |
11055 | intel_encoder->connectors_active = false; | |
11056 | } | |
11057 | ||
11058 | intel_modeset_commit_output_state(dev); | |
11059 | ||
7668851f | 11060 | /* Double check state. */ |
d3fcc808 | 11061 | for_each_intel_crtc(dev, intel_crtc) { |
83d65738 | 11062 | WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base)); |
ea9d758d DV |
11063 | } |
11064 | ||
11065 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
11066 | if (!connector->encoder || !connector->encoder->crtc) | |
11067 | continue; | |
11068 | ||
11069 | intel_crtc = to_intel_crtc(connector->encoder->crtc); | |
11070 | ||
11071 | if (prepare_pipes & (1 << intel_crtc->pipe)) { | |
68d34720 DV |
11072 | struct drm_property *dpms_property = |
11073 | dev->mode_config.dpms_property; | |
11074 | ||
ea9d758d | 11075 | connector->dpms = DRM_MODE_DPMS_ON; |
662595df | 11076 | drm_object_property_set_value(&connector->base, |
68d34720 DV |
11077 | dpms_property, |
11078 | DRM_MODE_DPMS_ON); | |
ea9d758d DV |
11079 | |
11080 | intel_encoder = to_intel_encoder(connector->encoder); | |
11081 | intel_encoder->connectors_active = true; | |
11082 | } | |
11083 | } | |
11084 | ||
11085 | } | |
11086 | ||
3bd26263 | 11087 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 11088 | { |
3bd26263 | 11089 | int diff; |
f1f644dc JB |
11090 | |
11091 | if (clock1 == clock2) | |
11092 | return true; | |
11093 | ||
11094 | if (!clock1 || !clock2) | |
11095 | return false; | |
11096 | ||
11097 | diff = abs(clock1 - clock2); | |
11098 | ||
11099 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
11100 | return true; | |
11101 | ||
11102 | return false; | |
11103 | } | |
11104 | ||
25c5b266 DV |
11105 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
11106 | list_for_each_entry((intel_crtc), \ | |
11107 | &(dev)->mode_config.crtc_list, \ | |
11108 | base.head) \ | |
0973f18f | 11109 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 11110 | |
0e8ffe1b | 11111 | static bool |
2fa2fe9a | 11112 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b ACO |
11113 | struct intel_crtc_state *current_config, |
11114 | struct intel_crtc_state *pipe_config) | |
0e8ffe1b | 11115 | { |
66e985c0 DV |
11116 | #define PIPE_CONF_CHECK_X(name) \ |
11117 | if (current_config->name != pipe_config->name) { \ | |
11118 | DRM_ERROR("mismatch in " #name " " \ | |
11119 | "(expected 0x%08x, found 0x%08x)\n", \ | |
11120 | current_config->name, \ | |
11121 | pipe_config->name); \ | |
11122 | return false; \ | |
11123 | } | |
11124 | ||
08a24034 DV |
11125 | #define PIPE_CONF_CHECK_I(name) \ |
11126 | if (current_config->name != pipe_config->name) { \ | |
11127 | DRM_ERROR("mismatch in " #name " " \ | |
11128 | "(expected %i, found %i)\n", \ | |
11129 | current_config->name, \ | |
11130 | pipe_config->name); \ | |
11131 | return false; \ | |
88adfff1 DV |
11132 | } |
11133 | ||
b95af8be VK |
11134 | /* This is required for BDW+ where there is only one set of registers for |
11135 | * switching between high and low RR. | |
11136 | * This macro can be used whenever a comparison has to be made between one | |
11137 | * hw state and multiple sw state variables. | |
11138 | */ | |
11139 | #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ | |
11140 | if ((current_config->name != pipe_config->name) && \ | |
11141 | (current_config->alt_name != pipe_config->name)) { \ | |
11142 | DRM_ERROR("mismatch in " #name " " \ | |
11143 | "(expected %i or %i, found %i)\n", \ | |
11144 | current_config->name, \ | |
11145 | current_config->alt_name, \ | |
11146 | pipe_config->name); \ | |
11147 | return false; \ | |
11148 | } | |
11149 | ||
1bd1bd80 DV |
11150 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
11151 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
6f02488e | 11152 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
11153 | "(expected %i, found %i)\n", \ |
11154 | current_config->name & (mask), \ | |
11155 | pipe_config->name & (mask)); \ | |
11156 | return false; \ | |
11157 | } | |
11158 | ||
5e550656 VS |
11159 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
11160 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
11161 | DRM_ERROR("mismatch in " #name " " \ | |
11162 | "(expected %i, found %i)\n", \ | |
11163 | current_config->name, \ | |
11164 | pipe_config->name); \ | |
11165 | return false; \ | |
11166 | } | |
11167 | ||
bb760063 DV |
11168 | #define PIPE_CONF_QUIRK(quirk) \ |
11169 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
11170 | ||
eccb140b DV |
11171 | PIPE_CONF_CHECK_I(cpu_transcoder); |
11172 | ||
08a24034 DV |
11173 | PIPE_CONF_CHECK_I(has_pch_encoder); |
11174 | PIPE_CONF_CHECK_I(fdi_lanes); | |
72419203 DV |
11175 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
11176 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); | |
11177 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); | |
11178 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); | |
11179 | PIPE_CONF_CHECK_I(fdi_m_n.tu); | |
08a24034 | 11180 | |
eb14cb74 | 11181 | PIPE_CONF_CHECK_I(has_dp_encoder); |
b95af8be VK |
11182 | |
11183 | if (INTEL_INFO(dev)->gen < 8) { | |
11184 | PIPE_CONF_CHECK_I(dp_m_n.gmch_m); | |
11185 | PIPE_CONF_CHECK_I(dp_m_n.gmch_n); | |
11186 | PIPE_CONF_CHECK_I(dp_m_n.link_m); | |
11187 | PIPE_CONF_CHECK_I(dp_m_n.link_n); | |
11188 | PIPE_CONF_CHECK_I(dp_m_n.tu); | |
11189 | ||
11190 | if (current_config->has_drrs) { | |
11191 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m); | |
11192 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n); | |
11193 | PIPE_CONF_CHECK_I(dp_m2_n2.link_m); | |
11194 | PIPE_CONF_CHECK_I(dp_m2_n2.link_n); | |
11195 | PIPE_CONF_CHECK_I(dp_m2_n2.tu); | |
11196 | } | |
11197 | } else { | |
11198 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m); | |
11199 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n); | |
11200 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m); | |
11201 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n); | |
11202 | PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu); | |
11203 | } | |
eb14cb74 | 11204 | |
2d112de7 ACO |
11205 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
11206 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
11207 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
11208 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
11209 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
11210 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 11211 | |
2d112de7 ACO |
11212 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
11213 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
11214 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
11215 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
11216 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
11217 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 11218 | |
c93f54cf | 11219 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 11220 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 DV |
11221 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
11222 | IS_VALLEYVIEW(dev)) | |
11223 | PIPE_CONF_CHECK_I(limited_color_range); | |
e43823ec | 11224 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 11225 | |
9ed109a7 DV |
11226 | PIPE_CONF_CHECK_I(has_audio); |
11227 | ||
2d112de7 | 11228 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
11229 | DRM_MODE_FLAG_INTERLACE); |
11230 | ||
bb760063 | 11231 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 11232 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11233 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 11234 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11235 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 11236 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11237 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 11238 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
11239 | DRM_MODE_FLAG_NVSYNC); |
11240 | } | |
045ac3b5 | 11241 | |
37327abd VS |
11242 | PIPE_CONF_CHECK_I(pipe_src_w); |
11243 | PIPE_CONF_CHECK_I(pipe_src_h); | |
1bd1bd80 | 11244 | |
9953599b DV |
11245 | /* |
11246 | * FIXME: BIOS likes to set up a cloned config with lvds+external | |
11247 | * screen. Since we don't yet re-compute the pipe config when moving | |
11248 | * just the lvds port away to another pipe the sw tracking won't match. | |
11249 | * | |
11250 | * Proper atomic modesets with recomputed global state will fix this. | |
11251 | * Until then just don't check gmch state for inherited modes. | |
11252 | */ | |
11253 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) { | |
11254 | PIPE_CONF_CHECK_I(gmch_pfit.control); | |
11255 | /* pfit ratios are autocomputed by the hw on gen4+ */ | |
11256 | if (INTEL_INFO(dev)->gen < 4) | |
11257 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
11258 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); | |
11259 | } | |
11260 | ||
fd4daa9c CW |
11261 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
11262 | if (current_config->pch_pfit.enabled) { | |
11263 | PIPE_CONF_CHECK_I(pch_pfit.pos); | |
11264 | PIPE_CONF_CHECK_I(pch_pfit.size); | |
11265 | } | |
2fa2fe9a | 11266 | |
e59150dc JB |
11267 | /* BDW+ don't expose a synchronous way to read the state */ |
11268 | if (IS_HASWELL(dev)) | |
11269 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 11270 | |
282740f7 VS |
11271 | PIPE_CONF_CHECK_I(double_wide); |
11272 | ||
26804afd DV |
11273 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
11274 | ||
c0d43d62 | 11275 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 11276 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 11277 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
11278 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
11279 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 11280 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
3f4cd19f DL |
11281 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
11282 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
11283 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 11284 | |
42571aef VS |
11285 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
11286 | PIPE_CONF_CHECK_I(pipe_bpp); | |
11287 | ||
2d112de7 | 11288 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 11289 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 11290 | |
66e985c0 | 11291 | #undef PIPE_CONF_CHECK_X |
08a24034 | 11292 | #undef PIPE_CONF_CHECK_I |
b95af8be | 11293 | #undef PIPE_CONF_CHECK_I_ALT |
1bd1bd80 | 11294 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 11295 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 11296 | #undef PIPE_CONF_QUIRK |
88adfff1 | 11297 | |
0e8ffe1b DV |
11298 | return true; |
11299 | } | |
11300 | ||
08db6652 DL |
11301 | static void check_wm_state(struct drm_device *dev) |
11302 | { | |
11303 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11304 | struct skl_ddb_allocation hw_ddb, *sw_ddb; | |
11305 | struct intel_crtc *intel_crtc; | |
11306 | int plane; | |
11307 | ||
11308 | if (INTEL_INFO(dev)->gen < 9) | |
11309 | return; | |
11310 | ||
11311 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
11312 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
11313 | ||
11314 | for_each_intel_crtc(dev, intel_crtc) { | |
11315 | struct skl_ddb_entry *hw_entry, *sw_entry; | |
11316 | const enum pipe pipe = intel_crtc->pipe; | |
11317 | ||
11318 | if (!intel_crtc->active) | |
11319 | continue; | |
11320 | ||
11321 | /* planes */ | |
dd740780 | 11322 | for_each_plane(dev_priv, pipe, plane) { |
08db6652 DL |
11323 | hw_entry = &hw_ddb.plane[pipe][plane]; |
11324 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
11325 | ||
11326 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
11327 | continue; | |
11328 | ||
11329 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " | |
11330 | "(expected (%u,%u), found (%u,%u))\n", | |
11331 | pipe_name(pipe), plane + 1, | |
11332 | sw_entry->start, sw_entry->end, | |
11333 | hw_entry->start, hw_entry->end); | |
11334 | } | |
11335 | ||
11336 | /* cursor */ | |
11337 | hw_entry = &hw_ddb.cursor[pipe]; | |
11338 | sw_entry = &sw_ddb->cursor[pipe]; | |
11339 | ||
11340 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
11341 | continue; | |
11342 | ||
11343 | DRM_ERROR("mismatch in DDB state pipe %c cursor " | |
11344 | "(expected (%u,%u), found (%u,%u))\n", | |
11345 | pipe_name(pipe), | |
11346 | sw_entry->start, sw_entry->end, | |
11347 | hw_entry->start, hw_entry->end); | |
11348 | } | |
11349 | } | |
11350 | ||
91d1b4bd DV |
11351 | static void |
11352 | check_connector_state(struct drm_device *dev) | |
8af6cf88 | 11353 | { |
8af6cf88 DV |
11354 | struct intel_connector *connector; |
11355 | ||
3a3371ff | 11356 | for_each_intel_connector(dev, connector) { |
8af6cf88 DV |
11357 | /* This also checks the encoder/connector hw state with the |
11358 | * ->get_hw_state callbacks. */ | |
11359 | intel_connector_check_state(connector); | |
11360 | ||
e2c719b7 | 11361 | I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder, |
8af6cf88 DV |
11362 | "connector's staged encoder doesn't match current encoder\n"); |
11363 | } | |
91d1b4bd DV |
11364 | } |
11365 | ||
11366 | static void | |
11367 | check_encoder_state(struct drm_device *dev) | |
11368 | { | |
11369 | struct intel_encoder *encoder; | |
11370 | struct intel_connector *connector; | |
8af6cf88 | 11371 | |
b2784e15 | 11372 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 DV |
11373 | bool enabled = false; |
11374 | bool active = false; | |
11375 | enum pipe pipe, tracked_pipe; | |
11376 | ||
11377 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
11378 | encoder->base.base.id, | |
8e329a03 | 11379 | encoder->base.name); |
8af6cf88 | 11380 | |
e2c719b7 | 11381 | I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc, |
8af6cf88 | 11382 | "encoder's stage crtc doesn't match current crtc\n"); |
e2c719b7 | 11383 | I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc, |
8af6cf88 DV |
11384 | "encoder's active_connectors set, but no crtc\n"); |
11385 | ||
3a3371ff | 11386 | for_each_intel_connector(dev, connector) { |
8af6cf88 DV |
11387 | if (connector->base.encoder != &encoder->base) |
11388 | continue; | |
11389 | enabled = true; | |
11390 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
11391 | active = true; | |
11392 | } | |
0e32b39c DA |
11393 | /* |
11394 | * for MST connectors if we unplug the connector is gone | |
11395 | * away but the encoder is still connected to a crtc | |
11396 | * until a modeset happens in response to the hotplug. | |
11397 | */ | |
11398 | if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST) | |
11399 | continue; | |
11400 | ||
e2c719b7 | 11401 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
11402 | "encoder's enabled state mismatch " |
11403 | "(expected %i, found %i)\n", | |
11404 | !!encoder->base.crtc, enabled); | |
e2c719b7 | 11405 | I915_STATE_WARN(active && !encoder->base.crtc, |
8af6cf88 DV |
11406 | "active encoder with no crtc\n"); |
11407 | ||
e2c719b7 | 11408 | I915_STATE_WARN(encoder->connectors_active != active, |
8af6cf88 DV |
11409 | "encoder's computed active state doesn't match tracked active state " |
11410 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
11411 | ||
11412 | active = encoder->get_hw_state(encoder, &pipe); | |
e2c719b7 | 11413 | I915_STATE_WARN(active != encoder->connectors_active, |
8af6cf88 DV |
11414 | "encoder's hw state doesn't match sw tracking " |
11415 | "(expected %i, found %i)\n", | |
11416 | encoder->connectors_active, active); | |
11417 | ||
11418 | if (!encoder->base.crtc) | |
11419 | continue; | |
11420 | ||
11421 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
e2c719b7 | 11422 | I915_STATE_WARN(active && pipe != tracked_pipe, |
8af6cf88 DV |
11423 | "active encoder's pipe doesn't match" |
11424 | "(expected %i, found %i)\n", | |
11425 | tracked_pipe, pipe); | |
11426 | ||
11427 | } | |
91d1b4bd DV |
11428 | } |
11429 | ||
11430 | static void | |
11431 | check_crtc_state(struct drm_device *dev) | |
11432 | { | |
fbee40df | 11433 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
11434 | struct intel_crtc *crtc; |
11435 | struct intel_encoder *encoder; | |
5cec258b | 11436 | struct intel_crtc_state pipe_config; |
8af6cf88 | 11437 | |
d3fcc808 | 11438 | for_each_intel_crtc(dev, crtc) { |
8af6cf88 DV |
11439 | bool enabled = false; |
11440 | bool active = false; | |
11441 | ||
045ac3b5 JB |
11442 | memset(&pipe_config, 0, sizeof(pipe_config)); |
11443 | ||
8af6cf88 DV |
11444 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
11445 | crtc->base.base.id); | |
11446 | ||
83d65738 | 11447 | I915_STATE_WARN(crtc->active && !crtc->base.state->enable, |
8af6cf88 DV |
11448 | "active crtc, but not enabled in sw tracking\n"); |
11449 | ||
b2784e15 | 11450 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 DV |
11451 | if (encoder->base.crtc != &crtc->base) |
11452 | continue; | |
11453 | enabled = true; | |
11454 | if (encoder->connectors_active) | |
11455 | active = true; | |
11456 | } | |
6c49f241 | 11457 | |
e2c719b7 | 11458 | I915_STATE_WARN(active != crtc->active, |
8af6cf88 DV |
11459 | "crtc's computed active state doesn't match tracked active state " |
11460 | "(expected %i, found %i)\n", active, crtc->active); | |
83d65738 | 11461 | I915_STATE_WARN(enabled != crtc->base.state->enable, |
8af6cf88 | 11462 | "crtc's computed enabled state doesn't match tracked enabled state " |
83d65738 MR |
11463 | "(expected %i, found %i)\n", enabled, |
11464 | crtc->base.state->enable); | |
8af6cf88 | 11465 | |
0e8ffe1b DV |
11466 | active = dev_priv->display.get_pipe_config(crtc, |
11467 | &pipe_config); | |
d62cf62a | 11468 | |
b6b5d049 VS |
11469 | /* hw state is inconsistent with the pipe quirk */ |
11470 | if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
11471 | (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
d62cf62a DV |
11472 | active = crtc->active; |
11473 | ||
b2784e15 | 11474 | for_each_intel_encoder(dev, encoder) { |
3eaba51c | 11475 | enum pipe pipe; |
6c49f241 DV |
11476 | if (encoder->base.crtc != &crtc->base) |
11477 | continue; | |
1d37b689 | 11478 | if (encoder->get_hw_state(encoder, &pipe)) |
6c49f241 DV |
11479 | encoder->get_config(encoder, &pipe_config); |
11480 | } | |
11481 | ||
e2c719b7 | 11482 | I915_STATE_WARN(crtc->active != active, |
0e8ffe1b DV |
11483 | "crtc active state doesn't match with hw state " |
11484 | "(expected %i, found %i)\n", crtc->active, active); | |
11485 | ||
c0b03411 | 11486 | if (active && |
6e3c9717 | 11487 | !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) { |
e2c719b7 | 11488 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); |
c0b03411 DV |
11489 | intel_dump_pipe_config(crtc, &pipe_config, |
11490 | "[hw state]"); | |
6e3c9717 | 11491 | intel_dump_pipe_config(crtc, crtc->config, |
c0b03411 DV |
11492 | "[sw state]"); |
11493 | } | |
8af6cf88 DV |
11494 | } |
11495 | } | |
11496 | ||
91d1b4bd DV |
11497 | static void |
11498 | check_shared_dpll_state(struct drm_device *dev) | |
11499 | { | |
fbee40df | 11500 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
11501 | struct intel_crtc *crtc; |
11502 | struct intel_dpll_hw_state dpll_hw_state; | |
11503 | int i; | |
5358901f DV |
11504 | |
11505 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
11506 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
11507 | int enabled_crtcs = 0, active_crtcs = 0; | |
11508 | bool active; | |
11509 | ||
11510 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
11511 | ||
11512 | DRM_DEBUG_KMS("%s\n", pll->name); | |
11513 | ||
11514 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
11515 | ||
e2c719b7 | 11516 | I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask), |
5358901f | 11517 | "more active pll users than references: %i vs %i\n", |
3e369b76 | 11518 | pll->active, hweight32(pll->config.crtc_mask)); |
e2c719b7 | 11519 | I915_STATE_WARN(pll->active && !pll->on, |
5358901f | 11520 | "pll in active use but not on in sw tracking\n"); |
e2c719b7 | 11521 | I915_STATE_WARN(pll->on && !pll->active, |
35c95375 | 11522 | "pll in on but not on in use in sw tracking\n"); |
e2c719b7 | 11523 | I915_STATE_WARN(pll->on != active, |
5358901f DV |
11524 | "pll on state mismatch (expected %i, found %i)\n", |
11525 | pll->on, active); | |
11526 | ||
d3fcc808 | 11527 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 11528 | if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll) |
5358901f DV |
11529 | enabled_crtcs++; |
11530 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
11531 | active_crtcs++; | |
11532 | } | |
e2c719b7 | 11533 | I915_STATE_WARN(pll->active != active_crtcs, |
5358901f DV |
11534 | "pll active crtcs mismatch (expected %i, found %i)\n", |
11535 | pll->active, active_crtcs); | |
e2c719b7 | 11536 | I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs, |
5358901f | 11537 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
3e369b76 | 11538 | hweight32(pll->config.crtc_mask), enabled_crtcs); |
66e985c0 | 11539 | |
e2c719b7 | 11540 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state, |
66e985c0 DV |
11541 | sizeof(dpll_hw_state)), |
11542 | "pll hw state mismatch\n"); | |
5358901f | 11543 | } |
8af6cf88 DV |
11544 | } |
11545 | ||
91d1b4bd DV |
11546 | void |
11547 | intel_modeset_check_state(struct drm_device *dev) | |
11548 | { | |
08db6652 | 11549 | check_wm_state(dev); |
91d1b4bd DV |
11550 | check_connector_state(dev); |
11551 | check_encoder_state(dev); | |
11552 | check_crtc_state(dev); | |
11553 | check_shared_dpll_state(dev); | |
11554 | } | |
11555 | ||
5cec258b | 11556 | void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config, |
18442d08 VS |
11557 | int dotclock) |
11558 | { | |
11559 | /* | |
11560 | * FDI already provided one idea for the dotclock. | |
11561 | * Yell if the encoder disagrees. | |
11562 | */ | |
2d112de7 | 11563 | WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock), |
18442d08 | 11564 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
2d112de7 | 11565 | pipe_config->base.adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
11566 | } |
11567 | ||
80715b2f VS |
11568 | static void update_scanline_offset(struct intel_crtc *crtc) |
11569 | { | |
11570 | struct drm_device *dev = crtc->base.dev; | |
11571 | ||
11572 | /* | |
11573 | * The scanline counter increments at the leading edge of hsync. | |
11574 | * | |
11575 | * On most platforms it starts counting from vtotal-1 on the | |
11576 | * first active line. That means the scanline counter value is | |
11577 | * always one less than what we would expect. Ie. just after | |
11578 | * start of vblank, which also occurs at start of hsync (on the | |
11579 | * last active line), the scanline counter will read vblank_start-1. | |
11580 | * | |
11581 | * On gen2 the scanline counter starts counting from 1 instead | |
11582 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
11583 | * to keep the value positive), instead of adding one. | |
11584 | * | |
11585 | * On HSW+ the behaviour of the scanline counter depends on the output | |
11586 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
11587 | * there's an extra 1 line difference. So we need to add two instead of | |
11588 | * one to the value. | |
11589 | */ | |
11590 | if (IS_GEN2(dev)) { | |
6e3c9717 | 11591 | const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
11592 | int vtotal; |
11593 | ||
11594 | vtotal = mode->crtc_vtotal; | |
11595 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
11596 | vtotal /= 2; | |
11597 | ||
11598 | crtc->scanline_offset = vtotal - 1; | |
11599 | } else if (HAS_DDI(dev) && | |
409ee761 | 11600 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
11601 | crtc->scanline_offset = 2; |
11602 | } else | |
11603 | crtc->scanline_offset = 1; | |
11604 | } | |
11605 | ||
5cec258b | 11606 | static struct intel_crtc_state * |
7f27126e JB |
11607 | intel_modeset_compute_config(struct drm_crtc *crtc, |
11608 | struct drm_display_mode *mode, | |
11609 | struct drm_framebuffer *fb, | |
83a57153 | 11610 | struct drm_atomic_state *state, |
7f27126e JB |
11611 | unsigned *modeset_pipes, |
11612 | unsigned *prepare_pipes, | |
11613 | unsigned *disable_pipes) | |
11614 | { | |
db7542dd | 11615 | struct drm_device *dev = crtc->dev; |
5cec258b | 11616 | struct intel_crtc_state *pipe_config = NULL; |
db7542dd | 11617 | struct intel_crtc *intel_crtc; |
0b901879 ACO |
11618 | int ret = 0; |
11619 | ||
11620 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
11621 | if (ret) | |
11622 | return ERR_PTR(ret); | |
7f27126e JB |
11623 | |
11624 | intel_modeset_affected_pipes(crtc, modeset_pipes, | |
11625 | prepare_pipes, disable_pipes); | |
11626 | ||
db7542dd ACO |
11627 | for_each_intel_crtc_masked(dev, *disable_pipes, intel_crtc) { |
11628 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
11629 | if (IS_ERR(pipe_config)) | |
11630 | return pipe_config; | |
11631 | ||
11632 | pipe_config->base.enable = false; | |
11633 | } | |
7f27126e JB |
11634 | |
11635 | /* | |
11636 | * Note this needs changes when we start tracking multiple modes | |
11637 | * and crtcs. At that point we'll need to compute the whole config | |
11638 | * (i.e. one pipe_config for each crtc) rather than just the one | |
11639 | * for this crtc. | |
11640 | */ | |
db7542dd ACO |
11641 | for_each_intel_crtc_masked(dev, *modeset_pipes, intel_crtc) { |
11642 | /* FIXME: For now we still expect modeset_pipes has at most | |
11643 | * one bit set. */ | |
11644 | if (WARN_ON(&intel_crtc->base != crtc)) | |
11645 | continue; | |
83a57153 | 11646 | |
db7542dd ACO |
11647 | pipe_config = intel_modeset_pipe_config(crtc, fb, mode, state); |
11648 | if (IS_ERR(pipe_config)) | |
11649 | return pipe_config; | |
7f27126e | 11650 | |
304603f4 ACO |
11651 | pipe_config->base.enable = true; |
11652 | ||
db7542dd ACO |
11653 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
11654 | "[modeset]"); | |
11655 | } | |
11656 | ||
11657 | return intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));; | |
7f27126e JB |
11658 | } |
11659 | ||
225da59b | 11660 | static int __intel_set_mode_setup_plls(struct drm_atomic_state *state, |
ed6739ef ACO |
11661 | unsigned modeset_pipes, |
11662 | unsigned disable_pipes) | |
11663 | { | |
225da59b | 11664 | struct drm_device *dev = state->dev; |
ed6739ef ACO |
11665 | struct drm_i915_private *dev_priv = to_i915(dev); |
11666 | unsigned clear_pipes = modeset_pipes | disable_pipes; | |
11667 | struct intel_crtc *intel_crtc; | |
11668 | int ret = 0; | |
11669 | ||
11670 | if (!dev_priv->display.crtc_compute_clock) | |
11671 | return 0; | |
11672 | ||
11673 | ret = intel_shared_dpll_start_config(dev_priv, clear_pipes); | |
11674 | if (ret) | |
11675 | goto done; | |
11676 | ||
11677 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { | |
225da59b ACO |
11678 | struct intel_crtc_state *crtc_state = |
11679 | intel_atomic_get_crtc_state(state, intel_crtc); | |
11680 | ||
11681 | /* Modeset pipes should have a new state by now */ | |
11682 | if (WARN_ON(IS_ERR(crtc_state))) | |
11683 | continue; | |
11684 | ||
ed6739ef | 11685 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, |
225da59b | 11686 | crtc_state); |
ed6739ef ACO |
11687 | if (ret) { |
11688 | intel_shared_dpll_abort_config(dev_priv); | |
11689 | goto done; | |
11690 | } | |
11691 | } | |
11692 | ||
11693 | done: | |
11694 | return ret; | |
11695 | } | |
11696 | ||
f30da187 DV |
11697 | static int __intel_set_mode(struct drm_crtc *crtc, |
11698 | struct drm_display_mode *mode, | |
7f27126e | 11699 | int x, int y, struct drm_framebuffer *fb, |
5cec258b | 11700 | struct intel_crtc_state *pipe_config, |
7f27126e JB |
11701 | unsigned modeset_pipes, |
11702 | unsigned prepare_pipes, | |
11703 | unsigned disable_pipes) | |
a6778b3c DV |
11704 | { |
11705 | struct drm_device *dev = crtc->dev; | |
fbee40df | 11706 | struct drm_i915_private *dev_priv = dev->dev_private; |
4b4b9238 | 11707 | struct drm_display_mode *saved_mode; |
304603f4 | 11708 | struct drm_atomic_state *state = pipe_config->base.state; |
83a57153 | 11709 | struct intel_crtc_state *crtc_state_copy = NULL; |
25c5b266 | 11710 | struct intel_crtc *intel_crtc; |
c0c36b94 | 11711 | int ret = 0; |
a6778b3c | 11712 | |
4b4b9238 | 11713 | saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL); |
c0c36b94 CW |
11714 | if (!saved_mode) |
11715 | return -ENOMEM; | |
a6778b3c | 11716 | |
83a57153 ACO |
11717 | crtc_state_copy = kmalloc(sizeof(*crtc_state_copy), GFP_KERNEL); |
11718 | if (!crtc_state_copy) { | |
11719 | ret = -ENOMEM; | |
11720 | goto done; | |
11721 | } | |
11722 | ||
3ac18232 | 11723 | *saved_mode = crtc->mode; |
a6778b3c | 11724 | |
30a970c6 JB |
11725 | /* |
11726 | * See if the config requires any additional preparation, e.g. | |
11727 | * to adjust global state with pipes off. We need to do this | |
11728 | * here so we can get the modeset_pipe updated config for the new | |
11729 | * mode set on this crtc. For other crtcs we need to use the | |
11730 | * adjusted_mode bits in the crtc directly. | |
11731 | */ | |
c164f833 | 11732 | if (IS_VALLEYVIEW(dev)) { |
304603f4 ACO |
11733 | ret = valleyview_modeset_global_pipes(state, &prepare_pipes); |
11734 | if (ret) | |
11735 | goto done; | |
30a970c6 | 11736 | |
c164f833 VS |
11737 | /* may have added more to prepare_pipes than we should */ |
11738 | prepare_pipes &= ~disable_pipes; | |
11739 | } | |
11740 | ||
225da59b | 11741 | ret = __intel_set_mode_setup_plls(state, modeset_pipes, disable_pipes); |
ed6739ef ACO |
11742 | if (ret) |
11743 | goto done; | |
8bd31e67 | 11744 | |
460da916 DV |
11745 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
11746 | intel_crtc_disable(&intel_crtc->base); | |
11747 | ||
ea9d758d | 11748 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
83d65738 | 11749 | if (intel_crtc->base.state->enable) |
ea9d758d DV |
11750 | dev_priv->display.crtc_disable(&intel_crtc->base); |
11751 | } | |
a6778b3c | 11752 | |
6c4c86f5 DV |
11753 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
11754 | * to set it here already despite that we pass it down the callchain. | |
7f27126e JB |
11755 | * |
11756 | * Note we'll need to fix this up when we start tracking multiple | |
11757 | * pipes; here we assume a single modeset_pipe and only track the | |
11758 | * single crtc and mode. | |
f6e5b160 | 11759 | */ |
b8cecdf5 | 11760 | if (modeset_pipes) { |
25c5b266 | 11761 | crtc->mode = *mode; |
b8cecdf5 DV |
11762 | /* mode_set/enable/disable functions rely on a correct pipe |
11763 | * config. */ | |
f5de6e07 | 11764 | intel_crtc_set_state(to_intel_crtc(crtc), pipe_config); |
c326c0a9 VS |
11765 | |
11766 | /* | |
11767 | * Calculate and store various constants which | |
11768 | * are later needed by vblank and swap-completion | |
11769 | * timestamping. They are derived from true hwmode. | |
11770 | */ | |
11771 | drm_calc_timestamping_constants(crtc, | |
2d112de7 | 11772 | &pipe_config->base.adjusted_mode); |
b8cecdf5 | 11773 | } |
7758a113 | 11774 | |
ea9d758d DV |
11775 | /* Only after disabling all output pipelines that will be changed can we |
11776 | * update the the output configuration. */ | |
11777 | intel_modeset_update_state(dev, prepare_pipes); | |
f6e5b160 | 11778 | |
304603f4 | 11779 | modeset_update_crtc_power_domains(state); |
47fab737 | 11780 | |
25c5b266 | 11781 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
455a6808 GP |
11782 | struct drm_plane *primary = intel_crtc->base.primary; |
11783 | int vdisplay, hdisplay; | |
4c10794f | 11784 | |
455a6808 | 11785 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); |
70a101f8 MR |
11786 | ret = drm_plane_helper_update(primary, &intel_crtc->base, |
11787 | fb, 0, 0, | |
11788 | hdisplay, vdisplay, | |
11789 | x << 16, y << 16, | |
11790 | hdisplay << 16, vdisplay << 16); | |
a6778b3c DV |
11791 | } |
11792 | ||
11793 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
80715b2f VS |
11794 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
11795 | update_scanline_offset(intel_crtc); | |
11796 | ||
25c5b266 | 11797 | dev_priv->display.crtc_enable(&intel_crtc->base); |
80715b2f | 11798 | } |
a6778b3c | 11799 | |
a6778b3c DV |
11800 | /* FIXME: add subpixel order */ |
11801 | done: | |
83d65738 | 11802 | if (ret && crtc->state->enable) |
3ac18232 | 11803 | crtc->mode = *saved_mode; |
a6778b3c | 11804 | |
83a57153 ACO |
11805 | if (ret == 0 && pipe_config) { |
11806 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11807 | ||
11808 | /* The pipe_config will be freed with the atomic state, so | |
11809 | * make a copy. */ | |
11810 | memcpy(crtc_state_copy, intel_crtc->config, | |
11811 | sizeof *crtc_state_copy); | |
11812 | intel_crtc->config = crtc_state_copy; | |
11813 | intel_crtc->base.state = &crtc_state_copy->base; | |
83a57153 ACO |
11814 | } else { |
11815 | kfree(crtc_state_copy); | |
11816 | } | |
11817 | ||
3ac18232 | 11818 | kfree(saved_mode); |
a6778b3c | 11819 | return ret; |
f6e5b160 CW |
11820 | } |
11821 | ||
7f27126e JB |
11822 | static int intel_set_mode_pipes(struct drm_crtc *crtc, |
11823 | struct drm_display_mode *mode, | |
11824 | int x, int y, struct drm_framebuffer *fb, | |
5cec258b | 11825 | struct intel_crtc_state *pipe_config, |
7f27126e JB |
11826 | unsigned modeset_pipes, |
11827 | unsigned prepare_pipes, | |
11828 | unsigned disable_pipes) | |
f30da187 DV |
11829 | { |
11830 | int ret; | |
11831 | ||
7f27126e JB |
11832 | ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes, |
11833 | prepare_pipes, disable_pipes); | |
f30da187 DV |
11834 | |
11835 | if (ret == 0) | |
11836 | intel_modeset_check_state(crtc->dev); | |
11837 | ||
11838 | return ret; | |
11839 | } | |
11840 | ||
7f27126e JB |
11841 | static int intel_set_mode(struct drm_crtc *crtc, |
11842 | struct drm_display_mode *mode, | |
83a57153 ACO |
11843 | int x, int y, struct drm_framebuffer *fb, |
11844 | struct drm_atomic_state *state) | |
7f27126e | 11845 | { |
5cec258b | 11846 | struct intel_crtc_state *pipe_config; |
7f27126e | 11847 | unsigned modeset_pipes, prepare_pipes, disable_pipes; |
83a57153 | 11848 | int ret = 0; |
7f27126e | 11849 | |
83a57153 | 11850 | pipe_config = intel_modeset_compute_config(crtc, mode, fb, state, |
7f27126e JB |
11851 | &modeset_pipes, |
11852 | &prepare_pipes, | |
11853 | &disable_pipes); | |
11854 | ||
83a57153 ACO |
11855 | if (IS_ERR(pipe_config)) { |
11856 | ret = PTR_ERR(pipe_config); | |
11857 | goto out; | |
11858 | } | |
11859 | ||
11860 | ret = intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config, | |
11861 | modeset_pipes, prepare_pipes, | |
11862 | disable_pipes); | |
11863 | if (ret) | |
11864 | goto out; | |
7f27126e | 11865 | |
83a57153 ACO |
11866 | out: |
11867 | return ret; | |
7f27126e JB |
11868 | } |
11869 | ||
c0c36b94 CW |
11870 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
11871 | { | |
83a57153 ACO |
11872 | struct drm_device *dev = crtc->dev; |
11873 | struct drm_atomic_state *state; | |
11874 | struct intel_encoder *encoder; | |
11875 | struct intel_connector *connector; | |
11876 | struct drm_connector_state *connector_state; | |
11877 | ||
11878 | state = drm_atomic_state_alloc(dev); | |
11879 | if (!state) { | |
11880 | DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory", | |
11881 | crtc->base.id); | |
11882 | return; | |
11883 | } | |
11884 | ||
11885 | state->acquire_ctx = dev->mode_config.acquire_ctx; | |
11886 | ||
11887 | /* The force restore path in the HW readout code relies on the staged | |
11888 | * config still keeping the user requested config while the actual | |
11889 | * state has been overwritten by the configuration read from HW. We | |
11890 | * need to copy the staged config to the atomic state, otherwise the | |
11891 | * mode set will just reapply the state the HW is already in. */ | |
11892 | for_each_intel_encoder(dev, encoder) { | |
11893 | if (&encoder->new_crtc->base != crtc) | |
11894 | continue; | |
11895 | ||
11896 | for_each_intel_connector(dev, connector) { | |
11897 | if (connector->new_encoder != encoder) | |
11898 | continue; | |
11899 | ||
11900 | connector_state = drm_atomic_get_connector_state(state, &connector->base); | |
11901 | if (IS_ERR(connector_state)) { | |
11902 | DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n", | |
11903 | connector->base.base.id, | |
11904 | connector->base.name, | |
11905 | PTR_ERR(connector_state)); | |
11906 | continue; | |
11907 | } | |
11908 | ||
11909 | connector_state->crtc = crtc; | |
11910 | connector_state->best_encoder = &encoder->base; | |
11911 | } | |
11912 | } | |
11913 | ||
11914 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb, | |
11915 | state); | |
11916 | ||
11917 | drm_atomic_state_free(state); | |
c0c36b94 CW |
11918 | } |
11919 | ||
25c5b266 DV |
11920 | #undef for_each_intel_crtc_masked |
11921 | ||
d9e55608 DV |
11922 | static void intel_set_config_free(struct intel_set_config *config) |
11923 | { | |
11924 | if (!config) | |
11925 | return; | |
11926 | ||
1aa4b628 DV |
11927 | kfree(config->save_connector_encoders); |
11928 | kfree(config->save_encoder_crtcs); | |
7668851f | 11929 | kfree(config->save_crtc_enabled); |
d9e55608 DV |
11930 | kfree(config); |
11931 | } | |
11932 | ||
85f9eb71 DV |
11933 | static int intel_set_config_save_state(struct drm_device *dev, |
11934 | struct intel_set_config *config) | |
11935 | { | |
7668851f | 11936 | struct drm_crtc *crtc; |
85f9eb71 DV |
11937 | struct drm_encoder *encoder; |
11938 | struct drm_connector *connector; | |
11939 | int count; | |
11940 | ||
7668851f VS |
11941 | config->save_crtc_enabled = |
11942 | kcalloc(dev->mode_config.num_crtc, | |
11943 | sizeof(bool), GFP_KERNEL); | |
11944 | if (!config->save_crtc_enabled) | |
11945 | return -ENOMEM; | |
11946 | ||
1aa4b628 DV |
11947 | config->save_encoder_crtcs = |
11948 | kcalloc(dev->mode_config.num_encoder, | |
11949 | sizeof(struct drm_crtc *), GFP_KERNEL); | |
11950 | if (!config->save_encoder_crtcs) | |
85f9eb71 DV |
11951 | return -ENOMEM; |
11952 | ||
1aa4b628 DV |
11953 | config->save_connector_encoders = |
11954 | kcalloc(dev->mode_config.num_connector, | |
11955 | sizeof(struct drm_encoder *), GFP_KERNEL); | |
11956 | if (!config->save_connector_encoders) | |
85f9eb71 DV |
11957 | return -ENOMEM; |
11958 | ||
11959 | /* Copy data. Note that driver private data is not affected. | |
11960 | * Should anything bad happen only the expected state is | |
11961 | * restored, not the drivers personal bookkeeping. | |
11962 | */ | |
7668851f | 11963 | count = 0; |
70e1e0ec | 11964 | for_each_crtc(dev, crtc) { |
83d65738 | 11965 | config->save_crtc_enabled[count++] = crtc->state->enable; |
7668851f VS |
11966 | } |
11967 | ||
85f9eb71 DV |
11968 | count = 0; |
11969 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1aa4b628 | 11970 | config->save_encoder_crtcs[count++] = encoder->crtc; |
85f9eb71 DV |
11971 | } |
11972 | ||
11973 | count = 0; | |
11974 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1aa4b628 | 11975 | config->save_connector_encoders[count++] = connector->encoder; |
85f9eb71 DV |
11976 | } |
11977 | ||
11978 | return 0; | |
11979 | } | |
11980 | ||
11981 | static void intel_set_config_restore_state(struct drm_device *dev, | |
11982 | struct intel_set_config *config) | |
11983 | { | |
7668851f | 11984 | struct intel_crtc *crtc; |
9a935856 DV |
11985 | struct intel_encoder *encoder; |
11986 | struct intel_connector *connector; | |
85f9eb71 DV |
11987 | int count; |
11988 | ||
7668851f | 11989 | count = 0; |
d3fcc808 | 11990 | for_each_intel_crtc(dev, crtc) { |
7668851f VS |
11991 | crtc->new_enabled = config->save_crtc_enabled[count++]; |
11992 | } | |
11993 | ||
85f9eb71 | 11994 | count = 0; |
b2784e15 | 11995 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
11996 | encoder->new_crtc = |
11997 | to_intel_crtc(config->save_encoder_crtcs[count++]); | |
85f9eb71 DV |
11998 | } |
11999 | ||
12000 | count = 0; | |
3a3371ff | 12001 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
12002 | connector->new_encoder = |
12003 | to_intel_encoder(config->save_connector_encoders[count++]); | |
85f9eb71 DV |
12004 | } |
12005 | } | |
12006 | ||
e3de42b6 | 12007 | static bool |
2e57f47d | 12008 | is_crtc_connector_off(struct drm_mode_set *set) |
e3de42b6 ID |
12009 | { |
12010 | int i; | |
12011 | ||
2e57f47d CW |
12012 | if (set->num_connectors == 0) |
12013 | return false; | |
12014 | ||
12015 | if (WARN_ON(set->connectors == NULL)) | |
12016 | return false; | |
12017 | ||
12018 | for (i = 0; i < set->num_connectors; i++) | |
12019 | if (set->connectors[i]->encoder && | |
12020 | set->connectors[i]->encoder->crtc == set->crtc && | |
12021 | set->connectors[i]->dpms != DRM_MODE_DPMS_ON) | |
e3de42b6 ID |
12022 | return true; |
12023 | ||
12024 | return false; | |
12025 | } | |
12026 | ||
5e2b584e DV |
12027 | static void |
12028 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, | |
12029 | struct intel_set_config *config) | |
12030 | { | |
12031 | ||
12032 | /* We should be able to check here if the fb has the same properties | |
12033 | * and then just flip_or_move it */ | |
2e57f47d CW |
12034 | if (is_crtc_connector_off(set)) { |
12035 | config->mode_changed = true; | |
f4510a27 | 12036 | } else if (set->crtc->primary->fb != set->fb) { |
3b150f08 MR |
12037 | /* |
12038 | * If we have no fb, we can only flip as long as the crtc is | |
12039 | * active, otherwise we need a full mode set. The crtc may | |
12040 | * be active if we've only disabled the primary plane, or | |
12041 | * in fastboot situations. | |
12042 | */ | |
f4510a27 | 12043 | if (set->crtc->primary->fb == NULL) { |
319d9827 JB |
12044 | struct intel_crtc *intel_crtc = |
12045 | to_intel_crtc(set->crtc); | |
12046 | ||
3b150f08 | 12047 | if (intel_crtc->active) { |
319d9827 JB |
12048 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); |
12049 | config->fb_changed = true; | |
12050 | } else { | |
12051 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); | |
12052 | config->mode_changed = true; | |
12053 | } | |
5e2b584e DV |
12054 | } else if (set->fb == NULL) { |
12055 | config->mode_changed = true; | |
72f4901e | 12056 | } else if (set->fb->pixel_format != |
f4510a27 | 12057 | set->crtc->primary->fb->pixel_format) { |
5e2b584e | 12058 | config->mode_changed = true; |
e3de42b6 | 12059 | } else { |
5e2b584e | 12060 | config->fb_changed = true; |
e3de42b6 | 12061 | } |
5e2b584e DV |
12062 | } |
12063 | ||
835c5873 | 12064 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
5e2b584e DV |
12065 | config->fb_changed = true; |
12066 | ||
12067 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { | |
12068 | DRM_DEBUG_KMS("modes are different, full mode set\n"); | |
12069 | drm_mode_debug_printmodeline(&set->crtc->mode); | |
12070 | drm_mode_debug_printmodeline(set->mode); | |
12071 | config->mode_changed = true; | |
12072 | } | |
a1d95703 CW |
12073 | |
12074 | DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", | |
12075 | set->crtc->base.id, config->mode_changed, config->fb_changed); | |
5e2b584e DV |
12076 | } |
12077 | ||
2e431051 | 12078 | static int |
9a935856 DV |
12079 | intel_modeset_stage_output_state(struct drm_device *dev, |
12080 | struct drm_mode_set *set, | |
944b0c76 ACO |
12081 | struct intel_set_config *config, |
12082 | struct drm_atomic_state *state) | |
50f56119 | 12083 | { |
9a935856 | 12084 | struct intel_connector *connector; |
944b0c76 | 12085 | struct drm_connector_state *connector_state; |
9a935856 | 12086 | struct intel_encoder *encoder; |
7668851f | 12087 | struct intel_crtc *crtc; |
f3f08572 | 12088 | int ro; |
50f56119 | 12089 | |
9abdda74 | 12090 | /* The upper layers ensure that we either disable a crtc or have a list |
9a935856 DV |
12091 | * of connectors. For paranoia, double-check this. */ |
12092 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
12093 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
12094 | ||
3a3371ff | 12095 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
12096 | /* Otherwise traverse passed in connector list and get encoders |
12097 | * for them. */ | |
50f56119 | 12098 | for (ro = 0; ro < set->num_connectors; ro++) { |
9a935856 | 12099 | if (set->connectors[ro] == &connector->base) { |
0e32b39c | 12100 | connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe); |
50f56119 DV |
12101 | break; |
12102 | } | |
12103 | } | |
12104 | ||
9a935856 DV |
12105 | /* If we disable the crtc, disable all its connectors. Also, if |
12106 | * the connector is on the changing crtc but not on the new | |
12107 | * connector list, disable it. */ | |
12108 | if ((!set->fb || ro == set->num_connectors) && | |
12109 | connector->base.encoder && | |
12110 | connector->base.encoder->crtc == set->crtc) { | |
12111 | connector->new_encoder = NULL; | |
12112 | ||
12113 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
12114 | connector->base.base.id, | |
c23cc417 | 12115 | connector->base.name); |
9a935856 DV |
12116 | } |
12117 | ||
12118 | ||
12119 | if (&connector->new_encoder->base != connector->base.encoder) { | |
10634189 ACO |
12120 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n", |
12121 | connector->base.base.id, | |
12122 | connector->base.name); | |
5e2b584e | 12123 | config->mode_changed = true; |
50f56119 DV |
12124 | } |
12125 | } | |
9a935856 | 12126 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 12127 | |
9a935856 | 12128 | /* Update crtc of enabled connectors. */ |
3a3371ff | 12129 | for_each_intel_connector(dev, connector) { |
7668851f VS |
12130 | struct drm_crtc *new_crtc; |
12131 | ||
9a935856 | 12132 | if (!connector->new_encoder) |
50f56119 DV |
12133 | continue; |
12134 | ||
9a935856 | 12135 | new_crtc = connector->new_encoder->base.crtc; |
50f56119 DV |
12136 | |
12137 | for (ro = 0; ro < set->num_connectors; ro++) { | |
9a935856 | 12138 | if (set->connectors[ro] == &connector->base) |
50f56119 DV |
12139 | new_crtc = set->crtc; |
12140 | } | |
12141 | ||
12142 | /* Make sure the new CRTC will work with the encoder */ | |
14509916 TR |
12143 | if (!drm_encoder_crtc_ok(&connector->new_encoder->base, |
12144 | new_crtc)) { | |
5e2b584e | 12145 | return -EINVAL; |
50f56119 | 12146 | } |
0e32b39c | 12147 | connector->new_encoder->new_crtc = to_intel_crtc(new_crtc); |
9a935856 | 12148 | |
944b0c76 ACO |
12149 | connector_state = |
12150 | drm_atomic_get_connector_state(state, &connector->base); | |
12151 | if (IS_ERR(connector_state)) | |
12152 | return PTR_ERR(connector_state); | |
12153 | ||
12154 | connector_state->crtc = new_crtc; | |
12155 | connector_state->best_encoder = &connector->new_encoder->base; | |
12156 | ||
9a935856 DV |
12157 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", |
12158 | connector->base.base.id, | |
c23cc417 | 12159 | connector->base.name, |
9a935856 DV |
12160 | new_crtc->base.id); |
12161 | } | |
12162 | ||
12163 | /* Check for any encoders that needs to be disabled. */ | |
b2784e15 | 12164 | for_each_intel_encoder(dev, encoder) { |
5a65f358 | 12165 | int num_connectors = 0; |
3a3371ff | 12166 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
12167 | if (connector->new_encoder == encoder) { |
12168 | WARN_ON(!connector->new_encoder->new_crtc); | |
5a65f358 | 12169 | num_connectors++; |
9a935856 DV |
12170 | } |
12171 | } | |
5a65f358 PZ |
12172 | |
12173 | if (num_connectors == 0) | |
12174 | encoder->new_crtc = NULL; | |
12175 | else if (num_connectors > 1) | |
12176 | return -EINVAL; | |
12177 | ||
9a935856 DV |
12178 | /* Only now check for crtc changes so we don't miss encoders |
12179 | * that will be disabled. */ | |
12180 | if (&encoder->new_crtc->base != encoder->base.crtc) { | |
10634189 ACO |
12181 | DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n", |
12182 | encoder->base.base.id, | |
12183 | encoder->base.name); | |
5e2b584e | 12184 | config->mode_changed = true; |
50f56119 DV |
12185 | } |
12186 | } | |
9a935856 | 12187 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
3a3371ff | 12188 | for_each_intel_connector(dev, connector) { |
944b0c76 ACO |
12189 | connector_state = |
12190 | drm_atomic_get_connector_state(state, &connector->base); | |
9d918c15 ACO |
12191 | if (IS_ERR(connector_state)) |
12192 | return PTR_ERR(connector_state); | |
944b0c76 ACO |
12193 | |
12194 | if (connector->new_encoder) { | |
0e32b39c DA |
12195 | if (connector->new_encoder != connector->encoder) |
12196 | connector->encoder = connector->new_encoder; | |
944b0c76 ACO |
12197 | } else { |
12198 | connector_state->crtc = NULL; | |
f61cccf3 | 12199 | connector_state->best_encoder = NULL; |
944b0c76 | 12200 | } |
0e32b39c | 12201 | } |
d3fcc808 | 12202 | for_each_intel_crtc(dev, crtc) { |
7668851f VS |
12203 | crtc->new_enabled = false; |
12204 | ||
b2784e15 | 12205 | for_each_intel_encoder(dev, encoder) { |
7668851f VS |
12206 | if (encoder->new_crtc == crtc) { |
12207 | crtc->new_enabled = true; | |
12208 | break; | |
12209 | } | |
12210 | } | |
12211 | ||
83d65738 | 12212 | if (crtc->new_enabled != crtc->base.state->enable) { |
10634189 ACO |
12213 | DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n", |
12214 | crtc->base.base.id, | |
7668851f VS |
12215 | crtc->new_enabled ? "en" : "dis"); |
12216 | config->mode_changed = true; | |
12217 | } | |
12218 | } | |
12219 | ||
2e431051 DV |
12220 | return 0; |
12221 | } | |
12222 | ||
7d00a1f5 VS |
12223 | static void disable_crtc_nofb(struct intel_crtc *crtc) |
12224 | { | |
12225 | struct drm_device *dev = crtc->base.dev; | |
12226 | struct intel_encoder *encoder; | |
12227 | struct intel_connector *connector; | |
12228 | ||
12229 | DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n", | |
12230 | pipe_name(crtc->pipe)); | |
12231 | ||
3a3371ff | 12232 | for_each_intel_connector(dev, connector) { |
7d00a1f5 VS |
12233 | if (connector->new_encoder && |
12234 | connector->new_encoder->new_crtc == crtc) | |
12235 | connector->new_encoder = NULL; | |
12236 | } | |
12237 | ||
b2784e15 | 12238 | for_each_intel_encoder(dev, encoder) { |
7d00a1f5 VS |
12239 | if (encoder->new_crtc == crtc) |
12240 | encoder->new_crtc = NULL; | |
12241 | } | |
12242 | ||
12243 | crtc->new_enabled = false; | |
12244 | } | |
12245 | ||
2e431051 DV |
12246 | static int intel_crtc_set_config(struct drm_mode_set *set) |
12247 | { | |
12248 | struct drm_device *dev; | |
2e431051 | 12249 | struct drm_mode_set save_set; |
83a57153 | 12250 | struct drm_atomic_state *state = NULL; |
2e431051 | 12251 | struct intel_set_config *config; |
5cec258b | 12252 | struct intel_crtc_state *pipe_config; |
50f52756 | 12253 | unsigned modeset_pipes, prepare_pipes, disable_pipes; |
2e431051 | 12254 | int ret; |
2e431051 | 12255 | |
8d3e375e DV |
12256 | BUG_ON(!set); |
12257 | BUG_ON(!set->crtc); | |
12258 | BUG_ON(!set->crtc->helper_private); | |
2e431051 | 12259 | |
7e53f3a4 DV |
12260 | /* Enforce sane interface api - has been abused by the fb helper. */ |
12261 | BUG_ON(!set->mode && set->fb); | |
12262 | BUG_ON(set->fb && set->num_connectors == 0); | |
431e50f7 | 12263 | |
2e431051 DV |
12264 | if (set->fb) { |
12265 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
12266 | set->crtc->base.id, set->fb->base.id, | |
12267 | (int)set->num_connectors, set->x, set->y); | |
12268 | } else { | |
12269 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
12270 | } |
12271 | ||
12272 | dev = set->crtc->dev; | |
12273 | ||
12274 | ret = -ENOMEM; | |
12275 | config = kzalloc(sizeof(*config), GFP_KERNEL); | |
12276 | if (!config) | |
12277 | goto out_config; | |
12278 | ||
12279 | ret = intel_set_config_save_state(dev, config); | |
12280 | if (ret) | |
12281 | goto out_config; | |
12282 | ||
12283 | save_set.crtc = set->crtc; | |
12284 | save_set.mode = &set->crtc->mode; | |
12285 | save_set.x = set->crtc->x; | |
12286 | save_set.y = set->crtc->y; | |
f4510a27 | 12287 | save_set.fb = set->crtc->primary->fb; |
2e431051 DV |
12288 | |
12289 | /* Compute whether we need a full modeset, only an fb base update or no | |
12290 | * change at all. In the future we might also check whether only the | |
12291 | * mode changed, e.g. for LVDS where we only change the panel fitter in | |
12292 | * such cases. */ | |
12293 | intel_set_config_compute_mode_changes(set, config); | |
12294 | ||
83a57153 ACO |
12295 | state = drm_atomic_state_alloc(dev); |
12296 | if (!state) { | |
12297 | ret = -ENOMEM; | |
12298 | goto out_config; | |
12299 | } | |
12300 | ||
12301 | state->acquire_ctx = dev->mode_config.acquire_ctx; | |
12302 | ||
944b0c76 | 12303 | ret = intel_modeset_stage_output_state(dev, set, config, state); |
2e431051 DV |
12304 | if (ret) |
12305 | goto fail; | |
12306 | ||
50f52756 | 12307 | pipe_config = intel_modeset_compute_config(set->crtc, set->mode, |
83a57153 | 12308 | set->fb, state, |
50f52756 JB |
12309 | &modeset_pipes, |
12310 | &prepare_pipes, | |
12311 | &disable_pipes); | |
20664591 | 12312 | if (IS_ERR(pipe_config)) { |
6ac0483b | 12313 | ret = PTR_ERR(pipe_config); |
50f52756 | 12314 | goto fail; |
20664591 | 12315 | } else if (pipe_config) { |
b9950a13 | 12316 | if (pipe_config->has_audio != |
6e3c9717 | 12317 | to_intel_crtc(set->crtc)->config->has_audio) |
20664591 JB |
12318 | config->mode_changed = true; |
12319 | ||
af15d2ce JB |
12320 | /* |
12321 | * Note we have an issue here with infoframes: current code | |
12322 | * only updates them on the full mode set path per hw | |
12323 | * requirements. So here we should be checking for any | |
12324 | * required changes and forcing a mode set. | |
12325 | */ | |
20664591 | 12326 | } |
50f52756 | 12327 | |
1f9954d0 JB |
12328 | intel_update_pipe_size(to_intel_crtc(set->crtc)); |
12329 | ||
5e2b584e | 12330 | if (config->mode_changed) { |
50f52756 JB |
12331 | ret = intel_set_mode_pipes(set->crtc, set->mode, |
12332 | set->x, set->y, set->fb, pipe_config, | |
12333 | modeset_pipes, prepare_pipes, | |
12334 | disable_pipes); | |
5e2b584e | 12335 | } else if (config->fb_changed) { |
3b150f08 | 12336 | struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc); |
455a6808 GP |
12337 | struct drm_plane *primary = set->crtc->primary; |
12338 | int vdisplay, hdisplay; | |
3b150f08 | 12339 | |
455a6808 | 12340 | drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay); |
70a101f8 MR |
12341 | ret = drm_plane_helper_update(primary, set->crtc, set->fb, |
12342 | 0, 0, hdisplay, vdisplay, | |
12343 | set->x << 16, set->y << 16, | |
12344 | hdisplay << 16, vdisplay << 16); | |
3b150f08 MR |
12345 | |
12346 | /* | |
12347 | * We need to make sure the primary plane is re-enabled if it | |
12348 | * has previously been turned off. | |
12349 | */ | |
12350 | if (!intel_crtc->primary_enabled && ret == 0) { | |
12351 | WARN_ON(!intel_crtc->active); | |
fdd508a6 | 12352 | intel_enable_primary_hw_plane(set->crtc->primary, set->crtc); |
3b150f08 MR |
12353 | } |
12354 | ||
7ca51a3a JB |
12355 | /* |
12356 | * In the fastboot case this may be our only check of the | |
12357 | * state after boot. It would be better to only do it on | |
12358 | * the first update, but we don't have a nice way of doing that | |
12359 | * (and really, set_config isn't used much for high freq page | |
12360 | * flipping, so increasing its cost here shouldn't be a big | |
12361 | * deal). | |
12362 | */ | |
d330a953 | 12363 | if (i915.fastboot && ret == 0) |
7ca51a3a | 12364 | intel_modeset_check_state(set->crtc->dev); |
50f56119 DV |
12365 | } |
12366 | ||
2d05eae1 | 12367 | if (ret) { |
bf67dfeb DV |
12368 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
12369 | set->crtc->base.id, ret); | |
50f56119 | 12370 | fail: |
2d05eae1 | 12371 | intel_set_config_restore_state(dev, config); |
50f56119 | 12372 | |
83a57153 ACO |
12373 | drm_atomic_state_clear(state); |
12374 | ||
7d00a1f5 VS |
12375 | /* |
12376 | * HACK: if the pipe was on, but we didn't have a framebuffer, | |
12377 | * force the pipe off to avoid oopsing in the modeset code | |
12378 | * due to fb==NULL. This should only happen during boot since | |
12379 | * we don't yet reconstruct the FB from the hardware state. | |
12380 | */ | |
12381 | if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb) | |
12382 | disable_crtc_nofb(to_intel_crtc(save_set.crtc)); | |
12383 | ||
2d05eae1 CW |
12384 | /* Try to restore the config */ |
12385 | if (config->mode_changed && | |
12386 | intel_set_mode(save_set.crtc, save_set.mode, | |
83a57153 ACO |
12387 | save_set.x, save_set.y, save_set.fb, |
12388 | state)) | |
2d05eae1 CW |
12389 | DRM_ERROR("failed to restore config after modeset failure\n"); |
12390 | } | |
50f56119 | 12391 | |
d9e55608 | 12392 | out_config: |
83a57153 ACO |
12393 | if (state) |
12394 | drm_atomic_state_free(state); | |
12395 | ||
d9e55608 | 12396 | intel_set_config_free(config); |
50f56119 DV |
12397 | return ret; |
12398 | } | |
f6e5b160 CW |
12399 | |
12400 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 | 12401 | .gamma_set = intel_crtc_gamma_set, |
50f56119 | 12402 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
12403 | .destroy = intel_crtc_destroy, |
12404 | .page_flip = intel_crtc_page_flip, | |
1356837e MR |
12405 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
12406 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
12407 | }; |
12408 | ||
5358901f DV |
12409 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
12410 | struct intel_shared_dpll *pll, | |
12411 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 12412 | { |
5358901f | 12413 | uint32_t val; |
ee7b9f93 | 12414 | |
f458ebbc | 12415 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
bd2bb1b9 PZ |
12416 | return false; |
12417 | ||
5358901f | 12418 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
12419 | hw_state->dpll = val; |
12420 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
12421 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
12422 | |
12423 | return val & DPLL_VCO_ENABLE; | |
12424 | } | |
12425 | ||
15bdd4cf DV |
12426 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
12427 | struct intel_shared_dpll *pll) | |
12428 | { | |
3e369b76 ACO |
12429 | I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0); |
12430 | I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1); | |
15bdd4cf DV |
12431 | } |
12432 | ||
e7b903d2 DV |
12433 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
12434 | struct intel_shared_dpll *pll) | |
12435 | { | |
e7b903d2 | 12436 | /* PCH refclock must be enabled first */ |
89eff4be | 12437 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 12438 | |
3e369b76 | 12439 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf DV |
12440 | |
12441 | /* Wait for the clocks to stabilize. */ | |
12442 | POSTING_READ(PCH_DPLL(pll->id)); | |
12443 | udelay(150); | |
12444 | ||
12445 | /* The pixel multiplier can only be updated once the | |
12446 | * DPLL is enabled and the clocks are stable. | |
12447 | * | |
12448 | * So write it again. | |
12449 | */ | |
3e369b76 | 12450 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf | 12451 | POSTING_READ(PCH_DPLL(pll->id)); |
e7b903d2 DV |
12452 | udelay(200); |
12453 | } | |
12454 | ||
12455 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
12456 | struct intel_shared_dpll *pll) | |
12457 | { | |
12458 | struct drm_device *dev = dev_priv->dev; | |
12459 | struct intel_crtc *crtc; | |
e7b903d2 DV |
12460 | |
12461 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 12462 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
12463 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
12464 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
12465 | } |
12466 | ||
15bdd4cf DV |
12467 | I915_WRITE(PCH_DPLL(pll->id), 0); |
12468 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
12469 | udelay(200); |
12470 | } | |
12471 | ||
46edb027 DV |
12472 | static char *ibx_pch_dpll_names[] = { |
12473 | "PCH DPLL A", | |
12474 | "PCH DPLL B", | |
12475 | }; | |
12476 | ||
7c74ade1 | 12477 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 12478 | { |
e7b903d2 | 12479 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
12480 | int i; |
12481 | ||
7c74ade1 | 12482 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 12483 | |
e72f9fbf | 12484 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
12485 | dev_priv->shared_dplls[i].id = i; |
12486 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 12487 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
12488 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
12489 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
12490 | dev_priv->shared_dplls[i].get_hw_state = |
12491 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
12492 | } |
12493 | } | |
12494 | ||
7c74ade1 DV |
12495 | static void intel_shared_dpll_init(struct drm_device *dev) |
12496 | { | |
e7b903d2 | 12497 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 | 12498 | |
9cd86933 DV |
12499 | if (HAS_DDI(dev)) |
12500 | intel_ddi_pll_init(dev); | |
12501 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7c74ade1 DV |
12502 | ibx_pch_dpll_init(dev); |
12503 | else | |
12504 | dev_priv->num_shared_dpll = 0; | |
12505 | ||
12506 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
12507 | } |
12508 | ||
1fc0a8f7 TU |
12509 | /** |
12510 | * intel_wm_need_update - Check whether watermarks need updating | |
12511 | * @plane: drm plane | |
12512 | * @state: new plane state | |
12513 | * | |
12514 | * Check current plane state versus the new one to determine whether | |
12515 | * watermarks need to be recalculated. | |
12516 | * | |
12517 | * Returns true or false. | |
12518 | */ | |
12519 | bool intel_wm_need_update(struct drm_plane *plane, | |
12520 | struct drm_plane_state *state) | |
12521 | { | |
12522 | /* Update watermarks on tiling changes. */ | |
12523 | if (!plane->state->fb || !state->fb || | |
12524 | plane->state->fb->modifier[0] != state->fb->modifier[0] || | |
12525 | plane->state->rotation != state->rotation) | |
12526 | return true; | |
12527 | ||
12528 | return false; | |
12529 | } | |
12530 | ||
6beb8c23 MR |
12531 | /** |
12532 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
12533 | * @plane: drm plane to prepare for | |
12534 | * @fb: framebuffer to prepare for presentation | |
12535 | * | |
12536 | * Prepares a framebuffer for usage on a display plane. Generally this | |
12537 | * involves pinning the underlying object and updating the frontbuffer tracking | |
12538 | * bits. Some older platforms need special physical address handling for | |
12539 | * cursor planes. | |
12540 | * | |
12541 | * Returns 0 on success, negative error code on failure. | |
12542 | */ | |
12543 | int | |
12544 | intel_prepare_plane_fb(struct drm_plane *plane, | |
d136dfee TU |
12545 | struct drm_framebuffer *fb, |
12546 | const struct drm_plane_state *new_state) | |
465c120c MR |
12547 | { |
12548 | struct drm_device *dev = plane->dev; | |
6beb8c23 MR |
12549 | struct intel_plane *intel_plane = to_intel_plane(plane); |
12550 | enum pipe pipe = intel_plane->pipe; | |
12551 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
12552 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); | |
12553 | unsigned frontbuffer_bits = 0; | |
12554 | int ret = 0; | |
465c120c | 12555 | |
ea2c67bb | 12556 | if (!obj) |
465c120c MR |
12557 | return 0; |
12558 | ||
6beb8c23 MR |
12559 | switch (plane->type) { |
12560 | case DRM_PLANE_TYPE_PRIMARY: | |
12561 | frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe); | |
12562 | break; | |
12563 | case DRM_PLANE_TYPE_CURSOR: | |
12564 | frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe); | |
12565 | break; | |
12566 | case DRM_PLANE_TYPE_OVERLAY: | |
12567 | frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe); | |
12568 | break; | |
12569 | } | |
465c120c | 12570 | |
6beb8c23 | 12571 | mutex_lock(&dev->struct_mutex); |
465c120c | 12572 | |
6beb8c23 MR |
12573 | if (plane->type == DRM_PLANE_TYPE_CURSOR && |
12574 | INTEL_INFO(dev)->cursor_needs_physical) { | |
12575 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
12576 | ret = i915_gem_object_attach_phys(obj, align); | |
12577 | if (ret) | |
12578 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
12579 | } else { | |
82bc3b2d | 12580 | ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL); |
6beb8c23 | 12581 | } |
465c120c | 12582 | |
6beb8c23 MR |
12583 | if (ret == 0) |
12584 | i915_gem_track_fb(old_obj, obj, frontbuffer_bits); | |
fdd508a6 | 12585 | |
4c34574f | 12586 | mutex_unlock(&dev->struct_mutex); |
465c120c | 12587 | |
6beb8c23 MR |
12588 | return ret; |
12589 | } | |
12590 | ||
38f3ce3a MR |
12591 | /** |
12592 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
12593 | * @plane: drm plane to clean up for | |
12594 | * @fb: old framebuffer that was on plane | |
12595 | * | |
12596 | * Cleans up a framebuffer that has just been removed from a plane. | |
12597 | */ | |
12598 | void | |
12599 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
d136dfee TU |
12600 | struct drm_framebuffer *fb, |
12601 | const struct drm_plane_state *old_state) | |
38f3ce3a MR |
12602 | { |
12603 | struct drm_device *dev = plane->dev; | |
12604 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
12605 | ||
12606 | if (WARN_ON(!obj)) | |
12607 | return; | |
12608 | ||
12609 | if (plane->type != DRM_PLANE_TYPE_CURSOR || | |
12610 | !INTEL_INFO(dev)->cursor_needs_physical) { | |
12611 | mutex_lock(&dev->struct_mutex); | |
82bc3b2d | 12612 | intel_unpin_fb_obj(fb, old_state); |
38f3ce3a MR |
12613 | mutex_unlock(&dev->struct_mutex); |
12614 | } | |
465c120c MR |
12615 | } |
12616 | ||
12617 | static int | |
3c692a41 GP |
12618 | intel_check_primary_plane(struct drm_plane *plane, |
12619 | struct intel_plane_state *state) | |
12620 | { | |
32b7eeec MR |
12621 | struct drm_device *dev = plane->dev; |
12622 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2b875c22 | 12623 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb | 12624 | struct intel_crtc *intel_crtc; |
2b875c22 | 12625 | struct drm_framebuffer *fb = state->base.fb; |
3c692a41 GP |
12626 | struct drm_rect *dest = &state->dst; |
12627 | struct drm_rect *src = &state->src; | |
12628 | const struct drm_rect *clip = &state->clip; | |
d8106366 | 12629 | bool can_position = false; |
465c120c MR |
12630 | int ret; |
12631 | ||
ea2c67bb MR |
12632 | crtc = crtc ? crtc : plane->crtc; |
12633 | intel_crtc = to_intel_crtc(crtc); | |
12634 | ||
d8106366 SJ |
12635 | if (INTEL_INFO(dev)->gen >= 9) |
12636 | can_position = true; | |
12637 | ||
c59cb179 MR |
12638 | ret = drm_plane_helper_check_update(plane, crtc, fb, |
12639 | src, dest, clip, | |
12640 | DRM_PLANE_HELPER_NO_SCALING, | |
12641 | DRM_PLANE_HELPER_NO_SCALING, | |
d8106366 SJ |
12642 | can_position, true, |
12643 | &state->visible); | |
c59cb179 MR |
12644 | if (ret) |
12645 | return ret; | |
465c120c | 12646 | |
32b7eeec MR |
12647 | if (intel_crtc->active) { |
12648 | intel_crtc->atomic.wait_for_flips = true; | |
12649 | ||
12650 | /* | |
12651 | * FBC does not work on some platforms for rotated | |
12652 | * planes, so disable it when rotation is not 0 and | |
12653 | * update it when rotation is set back to 0. | |
12654 | * | |
12655 | * FIXME: This is redundant with the fbc update done in | |
12656 | * the primary plane enable function except that that | |
12657 | * one is done too late. We eventually need to unify | |
12658 | * this. | |
12659 | */ | |
12660 | if (intel_crtc->primary_enabled && | |
12661 | INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && | |
e35fef21 | 12662 | dev_priv->fbc.crtc == intel_crtc && |
8e7d688b | 12663 | state->base.rotation != BIT(DRM_ROTATE_0)) { |
32b7eeec MR |
12664 | intel_crtc->atomic.disable_fbc = true; |
12665 | } | |
12666 | ||
12667 | if (state->visible) { | |
12668 | /* | |
12669 | * BDW signals flip done immediately if the plane | |
12670 | * is disabled, even if the plane enable is already | |
12671 | * armed to occur at the next vblank :( | |
12672 | */ | |
12673 | if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled) | |
12674 | intel_crtc->atomic.wait_vblank = true; | |
12675 | } | |
12676 | ||
12677 | intel_crtc->atomic.fb_bits |= | |
12678 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); | |
12679 | ||
12680 | intel_crtc->atomic.update_fbc = true; | |
0fda6568 | 12681 | |
1fc0a8f7 | 12682 | if (intel_wm_need_update(plane, &state->base)) |
0fda6568 | 12683 | intel_crtc->atomic.update_wm = true; |
ccc759dc GP |
12684 | } |
12685 | ||
14af293f GP |
12686 | return 0; |
12687 | } | |
12688 | ||
12689 | static void | |
12690 | intel_commit_primary_plane(struct drm_plane *plane, | |
12691 | struct intel_plane_state *state) | |
12692 | { | |
2b875c22 MR |
12693 | struct drm_crtc *crtc = state->base.crtc; |
12694 | struct drm_framebuffer *fb = state->base.fb; | |
12695 | struct drm_device *dev = plane->dev; | |
14af293f | 12696 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea2c67bb | 12697 | struct intel_crtc *intel_crtc; |
14af293f GP |
12698 | struct drm_rect *src = &state->src; |
12699 | ||
ea2c67bb MR |
12700 | crtc = crtc ? crtc : plane->crtc; |
12701 | intel_crtc = to_intel_crtc(crtc); | |
cf4c7c12 MR |
12702 | |
12703 | plane->fb = fb; | |
9dc806fc MR |
12704 | crtc->x = src->x1 >> 16; |
12705 | crtc->y = src->y1 >> 16; | |
ccc759dc | 12706 | |
ccc759dc | 12707 | if (intel_crtc->active) { |
ccc759dc | 12708 | if (state->visible) { |
ccc759dc GP |
12709 | /* FIXME: kill this fastboot hack */ |
12710 | intel_update_pipe_size(intel_crtc); | |
465c120c | 12711 | |
ccc759dc | 12712 | intel_crtc->primary_enabled = true; |
465c120c | 12713 | |
ccc759dc GP |
12714 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
12715 | crtc->x, crtc->y); | |
ccc759dc GP |
12716 | } else { |
12717 | /* | |
12718 | * If clipping results in a non-visible primary plane, | |
12719 | * we'll disable the primary plane. Note that this is | |
12720 | * a bit different than what happens if userspace | |
12721 | * explicitly disables the plane by passing fb=0 | |
12722 | * because plane->fb still gets set and pinned. | |
12723 | */ | |
12724 | intel_disable_primary_hw_plane(plane, crtc); | |
48404c1e | 12725 | } |
ccc759dc | 12726 | } |
465c120c MR |
12727 | } |
12728 | ||
32b7eeec | 12729 | static void intel_begin_crtc_commit(struct drm_crtc *crtc) |
3c692a41 | 12730 | { |
32b7eeec | 12731 | struct drm_device *dev = crtc->dev; |
140fd38d | 12732 | struct drm_i915_private *dev_priv = dev->dev_private; |
3c692a41 | 12733 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ea2c67bb MR |
12734 | struct intel_plane *intel_plane; |
12735 | struct drm_plane *p; | |
12736 | unsigned fb_bits = 0; | |
12737 | ||
12738 | /* Track fb's for any planes being disabled */ | |
12739 | list_for_each_entry(p, &dev->mode_config.plane_list, head) { | |
12740 | intel_plane = to_intel_plane(p); | |
12741 | ||
12742 | if (intel_crtc->atomic.disabled_planes & | |
12743 | (1 << drm_plane_index(p))) { | |
12744 | switch (p->type) { | |
12745 | case DRM_PLANE_TYPE_PRIMARY: | |
12746 | fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe); | |
12747 | break; | |
12748 | case DRM_PLANE_TYPE_CURSOR: | |
12749 | fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe); | |
12750 | break; | |
12751 | case DRM_PLANE_TYPE_OVERLAY: | |
12752 | fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe); | |
12753 | break; | |
12754 | } | |
3c692a41 | 12755 | |
ea2c67bb MR |
12756 | mutex_lock(&dev->struct_mutex); |
12757 | i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits); | |
12758 | mutex_unlock(&dev->struct_mutex); | |
12759 | } | |
12760 | } | |
3c692a41 | 12761 | |
32b7eeec MR |
12762 | if (intel_crtc->atomic.wait_for_flips) |
12763 | intel_crtc_wait_for_pending_flips(crtc); | |
3c692a41 | 12764 | |
32b7eeec MR |
12765 | if (intel_crtc->atomic.disable_fbc) |
12766 | intel_fbc_disable(dev); | |
3c692a41 | 12767 | |
32b7eeec MR |
12768 | if (intel_crtc->atomic.pre_disable_primary) |
12769 | intel_pre_disable_primary(crtc); | |
3c692a41 | 12770 | |
32b7eeec MR |
12771 | if (intel_crtc->atomic.update_wm) |
12772 | intel_update_watermarks(crtc); | |
3c692a41 | 12773 | |
32b7eeec | 12774 | intel_runtime_pm_get(dev_priv); |
3c692a41 | 12775 | |
c34c9ee4 MR |
12776 | /* Perform vblank evasion around commit operation */ |
12777 | if (intel_crtc->active) | |
12778 | intel_crtc->atomic.evade = | |
12779 | intel_pipe_update_start(intel_crtc, | |
12780 | &intel_crtc->atomic.start_vbl_count); | |
32b7eeec MR |
12781 | } |
12782 | ||
12783 | static void intel_finish_crtc_commit(struct drm_crtc *crtc) | |
12784 | { | |
12785 | struct drm_device *dev = crtc->dev; | |
12786 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12787 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12788 | struct drm_plane *p; | |
12789 | ||
c34c9ee4 MR |
12790 | if (intel_crtc->atomic.evade) |
12791 | intel_pipe_update_end(intel_crtc, | |
12792 | intel_crtc->atomic.start_vbl_count); | |
3c692a41 | 12793 | |
140fd38d | 12794 | intel_runtime_pm_put(dev_priv); |
3c692a41 | 12795 | |
32b7eeec MR |
12796 | if (intel_crtc->atomic.wait_vblank) |
12797 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
12798 | ||
12799 | intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits); | |
12800 | ||
12801 | if (intel_crtc->atomic.update_fbc) { | |
ccc759dc | 12802 | mutex_lock(&dev->struct_mutex); |
7ff0ebcc | 12803 | intel_fbc_update(dev); |
ccc759dc | 12804 | mutex_unlock(&dev->struct_mutex); |
38f3ce3a | 12805 | } |
3c692a41 | 12806 | |
32b7eeec MR |
12807 | if (intel_crtc->atomic.post_enable_primary) |
12808 | intel_post_enable_primary(crtc); | |
3c692a41 | 12809 | |
32b7eeec MR |
12810 | drm_for_each_legacy_plane(p, &dev->mode_config.plane_list) |
12811 | if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p)) | |
12812 | intel_update_sprite_watermarks(p, crtc, 0, 0, 0, | |
12813 | false, false); | |
12814 | ||
12815 | memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic)); | |
3c692a41 GP |
12816 | } |
12817 | ||
cf4c7c12 | 12818 | /** |
4a3b8769 MR |
12819 | * intel_plane_destroy - destroy a plane |
12820 | * @plane: plane to destroy | |
cf4c7c12 | 12821 | * |
4a3b8769 MR |
12822 | * Common destruction function for all types of planes (primary, cursor, |
12823 | * sprite). | |
cf4c7c12 | 12824 | */ |
4a3b8769 | 12825 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c MR |
12826 | { |
12827 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
12828 | drm_plane_cleanup(plane); | |
12829 | kfree(intel_plane); | |
12830 | } | |
12831 | ||
65a3fea0 | 12832 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
12833 | .update_plane = drm_atomic_helper_update_plane, |
12834 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 12835 | .destroy = intel_plane_destroy, |
c196e1d6 | 12836 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
12837 | .atomic_get_property = intel_plane_atomic_get_property, |
12838 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
12839 | .atomic_duplicate_state = intel_plane_duplicate_state, |
12840 | .atomic_destroy_state = intel_plane_destroy_state, | |
12841 | ||
465c120c MR |
12842 | }; |
12843 | ||
12844 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
12845 | int pipe) | |
12846 | { | |
12847 | struct intel_plane *primary; | |
8e7d688b | 12848 | struct intel_plane_state *state; |
465c120c MR |
12849 | const uint32_t *intel_primary_formats; |
12850 | int num_formats; | |
12851 | ||
12852 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
12853 | if (primary == NULL) | |
12854 | return NULL; | |
12855 | ||
8e7d688b MR |
12856 | state = intel_create_plane_state(&primary->base); |
12857 | if (!state) { | |
ea2c67bb MR |
12858 | kfree(primary); |
12859 | return NULL; | |
12860 | } | |
8e7d688b | 12861 | primary->base.state = &state->base; |
ea2c67bb | 12862 | |
465c120c MR |
12863 | primary->can_scale = false; |
12864 | primary->max_downscale = 1; | |
12865 | primary->pipe = pipe; | |
12866 | primary->plane = pipe; | |
c59cb179 MR |
12867 | primary->check_plane = intel_check_primary_plane; |
12868 | primary->commit_plane = intel_commit_primary_plane; | |
08e221fb | 12869 | primary->ckey.flags = I915_SET_COLORKEY_NONE; |
465c120c MR |
12870 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
12871 | primary->plane = !pipe; | |
12872 | ||
12873 | if (INTEL_INFO(dev)->gen <= 3) { | |
12874 | intel_primary_formats = intel_primary_formats_gen2; | |
12875 | num_formats = ARRAY_SIZE(intel_primary_formats_gen2); | |
12876 | } else { | |
12877 | intel_primary_formats = intel_primary_formats_gen4; | |
12878 | num_formats = ARRAY_SIZE(intel_primary_formats_gen4); | |
12879 | } | |
12880 | ||
12881 | drm_universal_plane_init(dev, &primary->base, 0, | |
65a3fea0 | 12882 | &intel_plane_funcs, |
465c120c MR |
12883 | intel_primary_formats, num_formats, |
12884 | DRM_PLANE_TYPE_PRIMARY); | |
48404c1e | 12885 | |
3b7a5119 SJ |
12886 | if (INTEL_INFO(dev)->gen >= 4) |
12887 | intel_create_rotation_property(dev, primary); | |
48404c1e | 12888 | |
ea2c67bb MR |
12889 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
12890 | ||
465c120c MR |
12891 | return &primary->base; |
12892 | } | |
12893 | ||
3b7a5119 SJ |
12894 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
12895 | { | |
12896 | if (!dev->mode_config.rotation_property) { | |
12897 | unsigned long flags = BIT(DRM_ROTATE_0) | | |
12898 | BIT(DRM_ROTATE_180); | |
12899 | ||
12900 | if (INTEL_INFO(dev)->gen >= 9) | |
12901 | flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); | |
12902 | ||
12903 | dev->mode_config.rotation_property = | |
12904 | drm_mode_create_rotation_property(dev, flags); | |
12905 | } | |
12906 | if (dev->mode_config.rotation_property) | |
12907 | drm_object_attach_property(&plane->base.base, | |
12908 | dev->mode_config.rotation_property, | |
12909 | plane->base.state->rotation); | |
12910 | } | |
12911 | ||
3d7d6510 | 12912 | static int |
852e787c GP |
12913 | intel_check_cursor_plane(struct drm_plane *plane, |
12914 | struct intel_plane_state *state) | |
3d7d6510 | 12915 | { |
2b875c22 | 12916 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb | 12917 | struct drm_device *dev = plane->dev; |
2b875c22 | 12918 | struct drm_framebuffer *fb = state->base.fb; |
852e787c GP |
12919 | struct drm_rect *dest = &state->dst; |
12920 | struct drm_rect *src = &state->src; | |
12921 | const struct drm_rect *clip = &state->clip; | |
757f9a3e | 12922 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
ea2c67bb | 12923 | struct intel_crtc *intel_crtc; |
757f9a3e GP |
12924 | unsigned stride; |
12925 | int ret; | |
3d7d6510 | 12926 | |
ea2c67bb MR |
12927 | crtc = crtc ? crtc : plane->crtc; |
12928 | intel_crtc = to_intel_crtc(crtc); | |
12929 | ||
757f9a3e | 12930 | ret = drm_plane_helper_check_update(plane, crtc, fb, |
852e787c | 12931 | src, dest, clip, |
3d7d6510 MR |
12932 | DRM_PLANE_HELPER_NO_SCALING, |
12933 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 12934 | true, true, &state->visible); |
757f9a3e GP |
12935 | if (ret) |
12936 | return ret; | |
12937 | ||
12938 | ||
12939 | /* if we want to turn off the cursor ignore width and height */ | |
12940 | if (!obj) | |
32b7eeec | 12941 | goto finish; |
757f9a3e | 12942 | |
757f9a3e | 12943 | /* Check for which cursor types we support */ |
ea2c67bb MR |
12944 | if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) { |
12945 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", | |
12946 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
12947 | return -EINVAL; |
12948 | } | |
12949 | ||
ea2c67bb MR |
12950 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
12951 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
12952 | DRM_DEBUG_KMS("buffer is too small\n"); |
12953 | return -ENOMEM; | |
12954 | } | |
12955 | ||
3a656b54 | 12956 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e GP |
12957 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
12958 | ret = -EINVAL; | |
12959 | } | |
757f9a3e | 12960 | |
32b7eeec MR |
12961 | finish: |
12962 | if (intel_crtc->active) { | |
3749f463 | 12963 | if (plane->state->crtc_w != state->base.crtc_w) |
32b7eeec MR |
12964 | intel_crtc->atomic.update_wm = true; |
12965 | ||
12966 | intel_crtc->atomic.fb_bits |= | |
12967 | INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe); | |
12968 | } | |
12969 | ||
757f9a3e | 12970 | return ret; |
852e787c | 12971 | } |
3d7d6510 | 12972 | |
f4a2cf29 | 12973 | static void |
852e787c GP |
12974 | intel_commit_cursor_plane(struct drm_plane *plane, |
12975 | struct intel_plane_state *state) | |
12976 | { | |
2b875c22 | 12977 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb MR |
12978 | struct drm_device *dev = plane->dev; |
12979 | struct intel_crtc *intel_crtc; | |
2b875c22 | 12980 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 12981 | uint32_t addr; |
852e787c | 12982 | |
ea2c67bb MR |
12983 | crtc = crtc ? crtc : plane->crtc; |
12984 | intel_crtc = to_intel_crtc(crtc); | |
12985 | ||
2b875c22 | 12986 | plane->fb = state->base.fb; |
ea2c67bb MR |
12987 | crtc->cursor_x = state->base.crtc_x; |
12988 | crtc->cursor_y = state->base.crtc_y; | |
12989 | ||
a912f12f GP |
12990 | if (intel_crtc->cursor_bo == obj) |
12991 | goto update; | |
4ed91096 | 12992 | |
f4a2cf29 | 12993 | if (!obj) |
a912f12f | 12994 | addr = 0; |
f4a2cf29 | 12995 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 12996 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 12997 | else |
a912f12f | 12998 | addr = obj->phys_handle->busaddr; |
852e787c | 12999 | |
a912f12f GP |
13000 | intel_crtc->cursor_addr = addr; |
13001 | intel_crtc->cursor_bo = obj; | |
13002 | update: | |
852e787c | 13003 | |
32b7eeec | 13004 | if (intel_crtc->active) |
a912f12f | 13005 | intel_crtc_update_cursor(crtc, state->visible); |
852e787c GP |
13006 | } |
13007 | ||
3d7d6510 MR |
13008 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
13009 | int pipe) | |
13010 | { | |
13011 | struct intel_plane *cursor; | |
8e7d688b | 13012 | struct intel_plane_state *state; |
3d7d6510 MR |
13013 | |
13014 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
13015 | if (cursor == NULL) | |
13016 | return NULL; | |
13017 | ||
8e7d688b MR |
13018 | state = intel_create_plane_state(&cursor->base); |
13019 | if (!state) { | |
ea2c67bb MR |
13020 | kfree(cursor); |
13021 | return NULL; | |
13022 | } | |
8e7d688b | 13023 | cursor->base.state = &state->base; |
ea2c67bb | 13024 | |
3d7d6510 MR |
13025 | cursor->can_scale = false; |
13026 | cursor->max_downscale = 1; | |
13027 | cursor->pipe = pipe; | |
13028 | cursor->plane = pipe; | |
c59cb179 MR |
13029 | cursor->check_plane = intel_check_cursor_plane; |
13030 | cursor->commit_plane = intel_commit_cursor_plane; | |
3d7d6510 MR |
13031 | |
13032 | drm_universal_plane_init(dev, &cursor->base, 0, | |
65a3fea0 | 13033 | &intel_plane_funcs, |
3d7d6510 MR |
13034 | intel_cursor_formats, |
13035 | ARRAY_SIZE(intel_cursor_formats), | |
13036 | DRM_PLANE_TYPE_CURSOR); | |
4398ad45 VS |
13037 | |
13038 | if (INTEL_INFO(dev)->gen >= 4) { | |
13039 | if (!dev->mode_config.rotation_property) | |
13040 | dev->mode_config.rotation_property = | |
13041 | drm_mode_create_rotation_property(dev, | |
13042 | BIT(DRM_ROTATE_0) | | |
13043 | BIT(DRM_ROTATE_180)); | |
13044 | if (dev->mode_config.rotation_property) | |
13045 | drm_object_attach_property(&cursor->base.base, | |
13046 | dev->mode_config.rotation_property, | |
8e7d688b | 13047 | state->base.rotation); |
4398ad45 VS |
13048 | } |
13049 | ||
ea2c67bb MR |
13050 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
13051 | ||
3d7d6510 MR |
13052 | return &cursor->base; |
13053 | } | |
13054 | ||
b358d0a6 | 13055 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 13056 | { |
fbee40df | 13057 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 13058 | struct intel_crtc *intel_crtc; |
f5de6e07 | 13059 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
13060 | struct drm_plane *primary = NULL; |
13061 | struct drm_plane *cursor = NULL; | |
465c120c | 13062 | int i, ret; |
79e53945 | 13063 | |
955382f3 | 13064 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
13065 | if (intel_crtc == NULL) |
13066 | return; | |
13067 | ||
f5de6e07 ACO |
13068 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
13069 | if (!crtc_state) | |
13070 | goto fail; | |
13071 | intel_crtc_set_state(intel_crtc, crtc_state); | |
07878248 | 13072 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 13073 | |
465c120c | 13074 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
13075 | if (!primary) |
13076 | goto fail; | |
13077 | ||
13078 | cursor = intel_cursor_plane_create(dev, pipe); | |
13079 | if (!cursor) | |
13080 | goto fail; | |
13081 | ||
465c120c | 13082 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
3d7d6510 MR |
13083 | cursor, &intel_crtc_funcs); |
13084 | if (ret) | |
13085 | goto fail; | |
79e53945 JB |
13086 | |
13087 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
13088 | for (i = 0; i < 256; i++) { |
13089 | intel_crtc->lut_r[i] = i; | |
13090 | intel_crtc->lut_g[i] = i; | |
13091 | intel_crtc->lut_b[i] = i; | |
13092 | } | |
13093 | ||
1f1c2e24 VS |
13094 | /* |
13095 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 13096 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 13097 | */ |
80824003 JB |
13098 | intel_crtc->pipe = pipe; |
13099 | intel_crtc->plane = pipe; | |
3a77c4c4 | 13100 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 13101 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 13102 | intel_crtc->plane = !pipe; |
80824003 JB |
13103 | } |
13104 | ||
4b0e333e CW |
13105 | intel_crtc->cursor_base = ~0; |
13106 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 13107 | intel_crtc->cursor_size = ~0; |
8d7849db | 13108 | |
22fd0fab JB |
13109 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
13110 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
13111 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
13112 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
13113 | ||
9362c7c5 ACO |
13114 | INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func); |
13115 | ||
79e53945 | 13116 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 DV |
13117 | |
13118 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); | |
3d7d6510 MR |
13119 | return; |
13120 | ||
13121 | fail: | |
13122 | if (primary) | |
13123 | drm_plane_cleanup(primary); | |
13124 | if (cursor) | |
13125 | drm_plane_cleanup(cursor); | |
f5de6e07 | 13126 | kfree(crtc_state); |
3d7d6510 | 13127 | kfree(intel_crtc); |
79e53945 JB |
13128 | } |
13129 | ||
752aa88a JB |
13130 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
13131 | { | |
13132 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 13133 | struct drm_device *dev = connector->base.dev; |
752aa88a | 13134 | |
51fd371b | 13135 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 13136 | |
d3babd3f | 13137 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
13138 | return INVALID_PIPE; |
13139 | ||
13140 | return to_intel_crtc(encoder->crtc)->pipe; | |
13141 | } | |
13142 | ||
08d7b3d1 | 13143 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 13144 | struct drm_file *file) |
08d7b3d1 | 13145 | { |
08d7b3d1 | 13146 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 13147 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 13148 | struct intel_crtc *crtc; |
08d7b3d1 | 13149 | |
7707e653 | 13150 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 13151 | |
7707e653 | 13152 | if (!drmmode_crtc) { |
08d7b3d1 | 13153 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 13154 | return -ENOENT; |
08d7b3d1 CW |
13155 | } |
13156 | ||
7707e653 | 13157 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 13158 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 13159 | |
c05422d5 | 13160 | return 0; |
08d7b3d1 CW |
13161 | } |
13162 | ||
66a9278e | 13163 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 13164 | { |
66a9278e DV |
13165 | struct drm_device *dev = encoder->base.dev; |
13166 | struct intel_encoder *source_encoder; | |
79e53945 | 13167 | int index_mask = 0; |
79e53945 JB |
13168 | int entry = 0; |
13169 | ||
b2784e15 | 13170 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 13171 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
13172 | index_mask |= (1 << entry); |
13173 | ||
79e53945 JB |
13174 | entry++; |
13175 | } | |
4ef69c7a | 13176 | |
79e53945 JB |
13177 | return index_mask; |
13178 | } | |
13179 | ||
4d302442 CW |
13180 | static bool has_edp_a(struct drm_device *dev) |
13181 | { | |
13182 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13183 | ||
13184 | if (!IS_MOBILE(dev)) | |
13185 | return false; | |
13186 | ||
13187 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
13188 | return false; | |
13189 | ||
e3589908 | 13190 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
13191 | return false; |
13192 | ||
13193 | return true; | |
13194 | } | |
13195 | ||
84b4e042 JB |
13196 | static bool intel_crt_present(struct drm_device *dev) |
13197 | { | |
13198 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13199 | ||
884497ed DL |
13200 | if (INTEL_INFO(dev)->gen >= 9) |
13201 | return false; | |
13202 | ||
cf404ce4 | 13203 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
13204 | return false; |
13205 | ||
13206 | if (IS_CHERRYVIEW(dev)) | |
13207 | return false; | |
13208 | ||
13209 | if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support) | |
13210 | return false; | |
13211 | ||
13212 | return true; | |
13213 | } | |
13214 | ||
79e53945 JB |
13215 | static void intel_setup_outputs(struct drm_device *dev) |
13216 | { | |
725e30ad | 13217 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 13218 | struct intel_encoder *encoder; |
cb0953d7 | 13219 | bool dpd_is_edp = false; |
79e53945 | 13220 | |
c9093354 | 13221 | intel_lvds_init(dev); |
79e53945 | 13222 | |
84b4e042 | 13223 | if (intel_crt_present(dev)) |
79935fca | 13224 | intel_crt_init(dev); |
cb0953d7 | 13225 | |
affa9354 | 13226 | if (HAS_DDI(dev)) { |
0e72a5b5 ED |
13227 | int found; |
13228 | ||
de31facd JB |
13229 | /* |
13230 | * Haswell uses DDI functions to detect digital outputs. | |
13231 | * On SKL pre-D0 the strap isn't connected, so we assume | |
13232 | * it's there. | |
13233 | */ | |
0e72a5b5 | 13234 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; |
de31facd JB |
13235 | /* WaIgnoreDDIAStrap: skl */ |
13236 | if (found || | |
13237 | (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0)) | |
0e72a5b5 ED |
13238 | intel_ddi_init(dev, PORT_A); |
13239 | ||
13240 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
13241 | * register */ | |
13242 | found = I915_READ(SFUSE_STRAP); | |
13243 | ||
13244 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
13245 | intel_ddi_init(dev, PORT_B); | |
13246 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
13247 | intel_ddi_init(dev, PORT_C); | |
13248 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
13249 | intel_ddi_init(dev, PORT_D); | |
13250 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 13251 | int found; |
5d8a7752 | 13252 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
13253 | |
13254 | if (has_edp_a(dev)) | |
13255 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 13256 | |
dc0fa718 | 13257 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 13258 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 13259 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 13260 | if (!found) |
e2debe91 | 13261 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 13262 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 13263 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
13264 | } |
13265 | ||
dc0fa718 | 13266 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 13267 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 13268 | |
dc0fa718 | 13269 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 13270 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 13271 | |
5eb08b69 | 13272 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 13273 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 13274 | |
270b3042 | 13275 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 13276 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 13277 | } else if (IS_VALLEYVIEW(dev)) { |
e17ac6db VS |
13278 | /* |
13279 | * The DP_DETECTED bit is the latched state of the DDC | |
13280 | * SDA pin at boot. However since eDP doesn't require DDC | |
13281 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
13282 | * eDP ports may have been muxed to an alternate function. | |
13283 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
13284 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
13285 | * detect eDP ports. | |
13286 | */ | |
d2182a66 VS |
13287 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED && |
13288 | !intel_dp_is_edp(dev, PORT_B)) | |
585a94b8 AB |
13289 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, |
13290 | PORT_B); | |
e17ac6db VS |
13291 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED || |
13292 | intel_dp_is_edp(dev, PORT_B)) | |
13293 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
585a94b8 | 13294 | |
d2182a66 VS |
13295 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED && |
13296 | !intel_dp_is_edp(dev, PORT_C)) | |
6f6005a5 JB |
13297 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, |
13298 | PORT_C); | |
e17ac6db VS |
13299 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED || |
13300 | intel_dp_is_edp(dev, PORT_C)) | |
13301 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); | |
19c03924 | 13302 | |
9418c1f1 | 13303 | if (IS_CHERRYVIEW(dev)) { |
e17ac6db | 13304 | if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) |
9418c1f1 VS |
13305 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID, |
13306 | PORT_D); | |
e17ac6db VS |
13307 | /* eDP not supported on port D, so don't check VBT */ |
13308 | if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED) | |
13309 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D); | |
9418c1f1 VS |
13310 | } |
13311 | ||
3cfca973 | 13312 | intel_dsi_init(dev); |
103a196f | 13313 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 13314 | bool found = false; |
7d57382e | 13315 | |
e2debe91 | 13316 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 13317 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 13318 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
b01f2c3a JB |
13319 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
13320 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
e2debe91 | 13321 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 13322 | } |
27185ae1 | 13323 | |
e7281eab | 13324 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 13325 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 13326 | } |
13520b05 KH |
13327 | |
13328 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 13329 | |
e2debe91 | 13330 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 13331 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 13332 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 13333 | } |
27185ae1 | 13334 | |
e2debe91 | 13335 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 13336 | |
b01f2c3a JB |
13337 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
13338 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
e2debe91 | 13339 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 13340 | } |
e7281eab | 13341 | if (SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 13342 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 13343 | } |
27185ae1 | 13344 | |
b01f2c3a | 13345 | if (SUPPORTS_INTEGRATED_DP(dev) && |
e7281eab | 13346 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 13347 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 13348 | } else if (IS_GEN2(dev)) |
79e53945 JB |
13349 | intel_dvo_init(dev); |
13350 | ||
103a196f | 13351 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
13352 | intel_tv_init(dev); |
13353 | ||
0bc12bcb | 13354 | intel_psr_init(dev); |
7c8f8a70 | 13355 | |
b2784e15 | 13356 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
13357 | encoder->base.possible_crtcs = encoder->crtc_mask; |
13358 | encoder->base.possible_clones = | |
66a9278e | 13359 | intel_encoder_clones(encoder); |
79e53945 | 13360 | } |
47356eb6 | 13361 | |
dde86e2d | 13362 | intel_init_pch_refclk(dev); |
270b3042 DV |
13363 | |
13364 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
13365 | } |
13366 | ||
13367 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
13368 | { | |
60a5ca01 | 13369 | struct drm_device *dev = fb->dev; |
79e53945 | 13370 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 13371 | |
ef2d633e | 13372 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 13373 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 13374 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
13375 | drm_gem_object_unreference(&intel_fb->obj->base); |
13376 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
13377 | kfree(intel_fb); |
13378 | } | |
13379 | ||
13380 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 13381 | struct drm_file *file, |
79e53945 JB |
13382 | unsigned int *handle) |
13383 | { | |
13384 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 13385 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 13386 | |
05394f39 | 13387 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
13388 | } |
13389 | ||
13390 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
13391 | .destroy = intel_user_framebuffer_destroy, | |
13392 | .create_handle = intel_user_framebuffer_create_handle, | |
13393 | }; | |
13394 | ||
b321803d DL |
13395 | static |
13396 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
13397 | uint32_t pixel_format) | |
13398 | { | |
13399 | u32 gen = INTEL_INFO(dev)->gen; | |
13400 | ||
13401 | if (gen >= 9) { | |
13402 | /* "The stride in bytes must not exceed the of the size of 8K | |
13403 | * pixels and 32K bytes." | |
13404 | */ | |
13405 | return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768); | |
13406 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) { | |
13407 | return 32*1024; | |
13408 | } else if (gen >= 4) { | |
13409 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
13410 | return 16*1024; | |
13411 | else | |
13412 | return 32*1024; | |
13413 | } else if (gen >= 3) { | |
13414 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
13415 | return 8*1024; | |
13416 | else | |
13417 | return 16*1024; | |
13418 | } else { | |
13419 | /* XXX DSPC is limited to 4k tiled */ | |
13420 | return 8*1024; | |
13421 | } | |
13422 | } | |
13423 | ||
b5ea642a DV |
13424 | static int intel_framebuffer_init(struct drm_device *dev, |
13425 | struct intel_framebuffer *intel_fb, | |
13426 | struct drm_mode_fb_cmd2 *mode_cmd, | |
13427 | struct drm_i915_gem_object *obj) | |
79e53945 | 13428 | { |
6761dd31 | 13429 | unsigned int aligned_height; |
79e53945 | 13430 | int ret; |
b321803d | 13431 | u32 pitch_limit, stride_alignment; |
79e53945 | 13432 | |
dd4916c5 DV |
13433 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
13434 | ||
2a80eada DV |
13435 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
13436 | /* Enforce that fb modifier and tiling mode match, but only for | |
13437 | * X-tiled. This is needed for FBC. */ | |
13438 | if (!!(obj->tiling_mode == I915_TILING_X) != | |
13439 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { | |
13440 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
13441 | return -EINVAL; | |
13442 | } | |
13443 | } else { | |
13444 | if (obj->tiling_mode == I915_TILING_X) | |
13445 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
13446 | else if (obj->tiling_mode == I915_TILING_Y) { | |
13447 | DRM_DEBUG("No Y tiling for legacy addfb\n"); | |
13448 | return -EINVAL; | |
13449 | } | |
13450 | } | |
13451 | ||
9a8f0a12 TU |
13452 | /* Passed in modifier sanity checking. */ |
13453 | switch (mode_cmd->modifier[0]) { | |
13454 | case I915_FORMAT_MOD_Y_TILED: | |
13455 | case I915_FORMAT_MOD_Yf_TILED: | |
13456 | if (INTEL_INFO(dev)->gen < 9) { | |
13457 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
13458 | mode_cmd->modifier[0]); | |
13459 | return -EINVAL; | |
13460 | } | |
13461 | case DRM_FORMAT_MOD_NONE: | |
13462 | case I915_FORMAT_MOD_X_TILED: | |
13463 | break; | |
13464 | default: | |
c0f40428 JB |
13465 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
13466 | mode_cmd->modifier[0]); | |
57cd6508 | 13467 | return -EINVAL; |
c16ed4be | 13468 | } |
57cd6508 | 13469 | |
b321803d DL |
13470 | stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0], |
13471 | mode_cmd->pixel_format); | |
13472 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
13473 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
13474 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 13475 | return -EINVAL; |
c16ed4be | 13476 | } |
57cd6508 | 13477 | |
b321803d DL |
13478 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
13479 | mode_cmd->pixel_format); | |
a35cdaa0 | 13480 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
13481 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
13482 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 13483 | "tiled" : "linear", |
a35cdaa0 | 13484 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 13485 | return -EINVAL; |
c16ed4be | 13486 | } |
5d7bd705 | 13487 | |
2a80eada | 13488 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
c16ed4be CW |
13489 | mode_cmd->pitches[0] != obj->stride) { |
13490 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
13491 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 13492 | return -EINVAL; |
c16ed4be | 13493 | } |
5d7bd705 | 13494 | |
57779d06 | 13495 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 13496 | switch (mode_cmd->pixel_format) { |
57779d06 | 13497 | case DRM_FORMAT_C8: |
04b3924d VS |
13498 | case DRM_FORMAT_RGB565: |
13499 | case DRM_FORMAT_XRGB8888: | |
13500 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
13501 | break; |
13502 | case DRM_FORMAT_XRGB1555: | |
13503 | case DRM_FORMAT_ARGB1555: | |
c16ed4be | 13504 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
13505 | DRM_DEBUG("unsupported pixel format: %s\n", |
13506 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 13507 | return -EINVAL; |
c16ed4be | 13508 | } |
57779d06 VS |
13509 | break; |
13510 | case DRM_FORMAT_XBGR8888: | |
13511 | case DRM_FORMAT_ABGR8888: | |
04b3924d VS |
13512 | case DRM_FORMAT_XRGB2101010: |
13513 | case DRM_FORMAT_ARGB2101010: | |
57779d06 VS |
13514 | case DRM_FORMAT_XBGR2101010: |
13515 | case DRM_FORMAT_ABGR2101010: | |
c16ed4be | 13516 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
13517 | DRM_DEBUG("unsupported pixel format: %s\n", |
13518 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 13519 | return -EINVAL; |
c16ed4be | 13520 | } |
b5626747 | 13521 | break; |
04b3924d VS |
13522 | case DRM_FORMAT_YUYV: |
13523 | case DRM_FORMAT_UYVY: | |
13524 | case DRM_FORMAT_YVYU: | |
13525 | case DRM_FORMAT_VYUY: | |
c16ed4be | 13526 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
13527 | DRM_DEBUG("unsupported pixel format: %s\n", |
13528 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 13529 | return -EINVAL; |
c16ed4be | 13530 | } |
57cd6508 CW |
13531 | break; |
13532 | default: | |
4ee62c76 VS |
13533 | DRM_DEBUG("unsupported pixel format: %s\n", |
13534 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
13535 | return -EINVAL; |
13536 | } | |
13537 | ||
90f9a336 VS |
13538 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
13539 | if (mode_cmd->offsets[0] != 0) | |
13540 | return -EINVAL; | |
13541 | ||
ec2c981e | 13542 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
091df6cb DV |
13543 | mode_cmd->pixel_format, |
13544 | mode_cmd->modifier[0]); | |
53155c0a DV |
13545 | /* FIXME drm helper for size checks (especially planar formats)? */ |
13546 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
13547 | return -EINVAL; | |
13548 | ||
c7d73f6a DV |
13549 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
13550 | intel_fb->obj = obj; | |
80075d49 | 13551 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 13552 | |
79e53945 JB |
13553 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
13554 | if (ret) { | |
13555 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
13556 | return ret; | |
13557 | } | |
13558 | ||
79e53945 JB |
13559 | return 0; |
13560 | } | |
13561 | ||
79e53945 JB |
13562 | static struct drm_framebuffer * |
13563 | intel_user_framebuffer_create(struct drm_device *dev, | |
13564 | struct drm_file *filp, | |
308e5bcb | 13565 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 13566 | { |
05394f39 | 13567 | struct drm_i915_gem_object *obj; |
79e53945 | 13568 | |
308e5bcb JB |
13569 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
13570 | mode_cmd->handles[0])); | |
c8725226 | 13571 | if (&obj->base == NULL) |
cce13ff7 | 13572 | return ERR_PTR(-ENOENT); |
79e53945 | 13573 | |
d2dff872 | 13574 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
13575 | } |
13576 | ||
4520f53a | 13577 | #ifndef CONFIG_DRM_I915_FBDEV |
0632fef6 | 13578 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
13579 | { |
13580 | } | |
13581 | #endif | |
13582 | ||
79e53945 | 13583 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 13584 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 13585 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
13586 | .atomic_check = intel_atomic_check, |
13587 | .atomic_commit = intel_atomic_commit, | |
79e53945 JB |
13588 | }; |
13589 | ||
e70236a8 JB |
13590 | /* Set up chip specific display functions */ |
13591 | static void intel_init_display(struct drm_device *dev) | |
13592 | { | |
13593 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13594 | ||
ee9300bb DV |
13595 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
13596 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
13597 | else if (IS_CHERRYVIEW(dev)) |
13598 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
13599 | else if (IS_VALLEYVIEW(dev)) |
13600 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
13601 | else if (IS_PINEVIEW(dev)) | |
13602 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
13603 | else | |
13604 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
13605 | ||
bc8d7dff DL |
13606 | if (INTEL_INFO(dev)->gen >= 9) { |
13607 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; | |
5724dbd1 DL |
13608 | dev_priv->display.get_initial_plane_config = |
13609 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
13610 | dev_priv->display.crtc_compute_clock = |
13611 | haswell_crtc_compute_clock; | |
13612 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
13613 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
13614 | dev_priv->display.off = ironlake_crtc_off; | |
13615 | dev_priv->display.update_primary_plane = | |
13616 | skylake_update_primary_plane; | |
13617 | } else if (HAS_DDI(dev)) { | |
0e8ffe1b | 13618 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
13619 | dev_priv->display.get_initial_plane_config = |
13620 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
13621 | dev_priv->display.crtc_compute_clock = |
13622 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
13623 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
13624 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
df8ad70c | 13625 | dev_priv->display.off = ironlake_crtc_off; |
bc8d7dff DL |
13626 | dev_priv->display.update_primary_plane = |
13627 | ironlake_update_primary_plane; | |
09b4ddf9 | 13628 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 13629 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
13630 | dev_priv->display.get_initial_plane_config = |
13631 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
13632 | dev_priv->display.crtc_compute_clock = |
13633 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
13634 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
13635 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
ee7b9f93 | 13636 | dev_priv->display.off = ironlake_crtc_off; |
262ca2b0 MR |
13637 | dev_priv->display.update_primary_plane = |
13638 | ironlake_update_primary_plane; | |
89b667f8 JB |
13639 | } else if (IS_VALLEYVIEW(dev)) { |
13640 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
5724dbd1 DL |
13641 | dev_priv->display.get_initial_plane_config = |
13642 | i9xx_get_initial_plane_config; | |
d6dfee7a | 13643 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
89b667f8 JB |
13644 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
13645 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
13646 | dev_priv->display.off = i9xx_crtc_off; | |
262ca2b0 MR |
13647 | dev_priv->display.update_primary_plane = |
13648 | i9xx_update_primary_plane; | |
f564048e | 13649 | } else { |
0e8ffe1b | 13650 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
13651 | dev_priv->display.get_initial_plane_config = |
13652 | i9xx_get_initial_plane_config; | |
d6dfee7a | 13653 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
13654 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
13655 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
ee7b9f93 | 13656 | dev_priv->display.off = i9xx_crtc_off; |
262ca2b0 MR |
13657 | dev_priv->display.update_primary_plane = |
13658 | i9xx_update_primary_plane; | |
f564048e | 13659 | } |
e70236a8 | 13660 | |
e70236a8 | 13661 | /* Returns the core display clock speed */ |
1652d19e VS |
13662 | if (IS_SKYLAKE(dev)) |
13663 | dev_priv->display.get_display_clock_speed = | |
13664 | skylake_get_display_clock_speed; | |
13665 | else if (IS_BROADWELL(dev)) | |
13666 | dev_priv->display.get_display_clock_speed = | |
13667 | broadwell_get_display_clock_speed; | |
13668 | else if (IS_HASWELL(dev)) | |
13669 | dev_priv->display.get_display_clock_speed = | |
13670 | haswell_get_display_clock_speed; | |
13671 | else if (IS_VALLEYVIEW(dev)) | |
25eb05fc JB |
13672 | dev_priv->display.get_display_clock_speed = |
13673 | valleyview_get_display_clock_speed; | |
b37a6434 VS |
13674 | else if (IS_GEN5(dev)) |
13675 | dev_priv->display.get_display_clock_speed = | |
13676 | ilk_get_display_clock_speed; | |
a7c66cd8 VS |
13677 | else if (IS_I945G(dev) || IS_BROADWATER(dev) || |
13678 | IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
13679 | dev_priv->display.get_display_clock_speed = |
13680 | i945_get_display_clock_speed; | |
13681 | else if (IS_I915G(dev)) | |
13682 | dev_priv->display.get_display_clock_speed = | |
13683 | i915_get_display_clock_speed; | |
257a7ffc | 13684 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
13685 | dev_priv->display.get_display_clock_speed = |
13686 | i9xx_misc_get_display_clock_speed; | |
257a7ffc DV |
13687 | else if (IS_PINEVIEW(dev)) |
13688 | dev_priv->display.get_display_clock_speed = | |
13689 | pnv_get_display_clock_speed; | |
e70236a8 JB |
13690 | else if (IS_I915GM(dev)) |
13691 | dev_priv->display.get_display_clock_speed = | |
13692 | i915gm_get_display_clock_speed; | |
13693 | else if (IS_I865G(dev)) | |
13694 | dev_priv->display.get_display_clock_speed = | |
13695 | i865_get_display_clock_speed; | |
f0f8a9ce | 13696 | else if (IS_I85X(dev)) |
e70236a8 JB |
13697 | dev_priv->display.get_display_clock_speed = |
13698 | i855_get_display_clock_speed; | |
13699 | else /* 852, 830 */ | |
13700 | dev_priv->display.get_display_clock_speed = | |
13701 | i830_get_display_clock_speed; | |
13702 | ||
7c10a2b5 | 13703 | if (IS_GEN5(dev)) { |
3bb11b53 | 13704 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
3bb11b53 SJ |
13705 | } else if (IS_GEN6(dev)) { |
13706 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; | |
3bb11b53 SJ |
13707 | } else if (IS_IVYBRIDGE(dev)) { |
13708 | /* FIXME: detect B0+ stepping and use auto training */ | |
13709 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
059b2fe9 | 13710 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
3bb11b53 | 13711 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
30a970c6 JB |
13712 | } else if (IS_VALLEYVIEW(dev)) { |
13713 | dev_priv->display.modeset_global_resources = | |
13714 | valleyview_modeset_global_resources; | |
e70236a8 | 13715 | } |
8c9f3aaf | 13716 | |
8c9f3aaf JB |
13717 | switch (INTEL_INFO(dev)->gen) { |
13718 | case 2: | |
13719 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
13720 | break; | |
13721 | ||
13722 | case 3: | |
13723 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
13724 | break; | |
13725 | ||
13726 | case 4: | |
13727 | case 5: | |
13728 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
13729 | break; | |
13730 | ||
13731 | case 6: | |
13732 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
13733 | break; | |
7c9017e5 | 13734 | case 7: |
4e0bbc31 | 13735 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
13736 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
13737 | break; | |
830c81db | 13738 | case 9: |
ba343e02 TU |
13739 | /* Drop through - unsupported since execlist only. */ |
13740 | default: | |
13741 | /* Default just returns -ENODEV to indicate unsupported */ | |
13742 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8c9f3aaf | 13743 | } |
7bd688cd JN |
13744 | |
13745 | intel_panel_init_backlight_funcs(dev); | |
e39b999a VS |
13746 | |
13747 | mutex_init(&dev_priv->pps_mutex); | |
e70236a8 JB |
13748 | } |
13749 | ||
b690e96c JB |
13750 | /* |
13751 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
13752 | * resume, or other times. This quirk makes sure that's the case for | |
13753 | * affected systems. | |
13754 | */ | |
0206e353 | 13755 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
13756 | { |
13757 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13758 | ||
13759 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 13760 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
13761 | } |
13762 | ||
b6b5d049 VS |
13763 | static void quirk_pipeb_force(struct drm_device *dev) |
13764 | { | |
13765 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13766 | ||
13767 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
13768 | DRM_INFO("applying pipe b force quirk\n"); | |
13769 | } | |
13770 | ||
435793df KP |
13771 | /* |
13772 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
13773 | */ | |
13774 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
13775 | { | |
13776 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13777 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 13778 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
13779 | } |
13780 | ||
4dca20ef | 13781 | /* |
5a15ab5b CE |
13782 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
13783 | * brightness value | |
4dca20ef CE |
13784 | */ |
13785 | static void quirk_invert_brightness(struct drm_device *dev) | |
13786 | { | |
13787 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13788 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 13789 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
13790 | } |
13791 | ||
9c72cc6f SD |
13792 | /* Some VBT's incorrectly indicate no backlight is present */ |
13793 | static void quirk_backlight_present(struct drm_device *dev) | |
13794 | { | |
13795 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13796 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
13797 | DRM_INFO("applying backlight present quirk\n"); | |
13798 | } | |
13799 | ||
b690e96c JB |
13800 | struct intel_quirk { |
13801 | int device; | |
13802 | int subsystem_vendor; | |
13803 | int subsystem_device; | |
13804 | void (*hook)(struct drm_device *dev); | |
13805 | }; | |
13806 | ||
5f85f176 EE |
13807 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
13808 | struct intel_dmi_quirk { | |
13809 | void (*hook)(struct drm_device *dev); | |
13810 | const struct dmi_system_id (*dmi_id_list)[]; | |
13811 | }; | |
13812 | ||
13813 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
13814 | { | |
13815 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
13816 | return 1; | |
13817 | } | |
13818 | ||
13819 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
13820 | { | |
13821 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
13822 | { | |
13823 | .callback = intel_dmi_reverse_brightness, | |
13824 | .ident = "NCR Corporation", | |
13825 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
13826 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
13827 | }, | |
13828 | }, | |
13829 | { } /* terminating entry */ | |
13830 | }, | |
13831 | .hook = quirk_invert_brightness, | |
13832 | }, | |
13833 | }; | |
13834 | ||
c43b5634 | 13835 | static struct intel_quirk intel_quirks[] = { |
b690e96c | 13836 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 13837 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c | 13838 | |
b690e96c JB |
13839 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
13840 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
13841 | ||
b690e96c JB |
13842 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
13843 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
13844 | ||
5f080c0f VS |
13845 | /* 830 needs to leave pipe A & dpll A up */ |
13846 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
13847 | ||
b6b5d049 VS |
13848 | /* 830 needs to leave pipe B & dpll B up */ |
13849 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
13850 | ||
435793df KP |
13851 | /* Lenovo U160 cannot use SSC on LVDS */ |
13852 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
13853 | |
13854 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
13855 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 13856 | |
be505f64 AH |
13857 | /* Acer Aspire 5734Z must invert backlight brightness */ |
13858 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
13859 | ||
13860 | /* Acer/eMachines G725 */ | |
13861 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
13862 | ||
13863 | /* Acer/eMachines e725 */ | |
13864 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
13865 | ||
13866 | /* Acer/Packard Bell NCL20 */ | |
13867 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
13868 | ||
13869 | /* Acer Aspire 4736Z */ | |
13870 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
13871 | |
13872 | /* Acer Aspire 5336 */ | |
13873 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
13874 | |
13875 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
13876 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 13877 | |
dfb3d47b SD |
13878 | /* Acer C720 Chromebook (Core i3 4005U) */ |
13879 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
13880 | ||
b2a9601c | 13881 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
13882 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
13883 | ||
d4967d8c SD |
13884 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
13885 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
13886 | |
13887 | /* HP Chromebook 14 (Celeron 2955U) */ | |
13888 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
13889 | |
13890 | /* Dell Chromebook 11 */ | |
13891 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
13892 | }; |
13893 | ||
13894 | static void intel_init_quirks(struct drm_device *dev) | |
13895 | { | |
13896 | struct pci_dev *d = dev->pdev; | |
13897 | int i; | |
13898 | ||
13899 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
13900 | struct intel_quirk *q = &intel_quirks[i]; | |
13901 | ||
13902 | if (d->device == q->device && | |
13903 | (d->subsystem_vendor == q->subsystem_vendor || | |
13904 | q->subsystem_vendor == PCI_ANY_ID) && | |
13905 | (d->subsystem_device == q->subsystem_device || | |
13906 | q->subsystem_device == PCI_ANY_ID)) | |
13907 | q->hook(dev); | |
13908 | } | |
5f85f176 EE |
13909 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
13910 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
13911 | intel_dmi_quirks[i].hook(dev); | |
13912 | } | |
b690e96c JB |
13913 | } |
13914 | ||
9cce37f4 JB |
13915 | /* Disable the VGA plane that we never use */ |
13916 | static void i915_disable_vga(struct drm_device *dev) | |
13917 | { | |
13918 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13919 | u8 sr1; | |
766aa1c4 | 13920 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 13921 | |
2b37c616 | 13922 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 13923 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 13924 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
13925 | sr1 = inb(VGA_SR_DATA); |
13926 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
13927 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
13928 | udelay(300); | |
13929 | ||
01f5a626 | 13930 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
13931 | POSTING_READ(vga_reg); |
13932 | } | |
13933 | ||
f817586c DV |
13934 | void intel_modeset_init_hw(struct drm_device *dev) |
13935 | { | |
a8f78b58 ED |
13936 | intel_prepare_ddi(dev); |
13937 | ||
f8bf63fd VS |
13938 | if (IS_VALLEYVIEW(dev)) |
13939 | vlv_update_cdclk(dev); | |
13940 | ||
f817586c DV |
13941 | intel_init_clock_gating(dev); |
13942 | ||
8090c6b9 | 13943 | intel_enable_gt_powersave(dev); |
f817586c DV |
13944 | } |
13945 | ||
79e53945 JB |
13946 | void intel_modeset_init(struct drm_device *dev) |
13947 | { | |
652c393a | 13948 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 13949 | int sprite, ret; |
8cc87b75 | 13950 | enum pipe pipe; |
46f297fb | 13951 | struct intel_crtc *crtc; |
79e53945 JB |
13952 | |
13953 | drm_mode_config_init(dev); | |
13954 | ||
13955 | dev->mode_config.min_width = 0; | |
13956 | dev->mode_config.min_height = 0; | |
13957 | ||
019d96cb DA |
13958 | dev->mode_config.preferred_depth = 24; |
13959 | dev->mode_config.prefer_shadow = 1; | |
13960 | ||
25bab385 TU |
13961 | dev->mode_config.allow_fb_modifiers = true; |
13962 | ||
e6ecefaa | 13963 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 13964 | |
b690e96c JB |
13965 | intel_init_quirks(dev); |
13966 | ||
1fa61106 ED |
13967 | intel_init_pm(dev); |
13968 | ||
e3c74757 BW |
13969 | if (INTEL_INFO(dev)->num_pipes == 0) |
13970 | return; | |
13971 | ||
e70236a8 | 13972 | intel_init_display(dev); |
7c10a2b5 | 13973 | intel_init_audio(dev); |
e70236a8 | 13974 | |
a6c45cf0 CW |
13975 | if (IS_GEN2(dev)) { |
13976 | dev->mode_config.max_width = 2048; | |
13977 | dev->mode_config.max_height = 2048; | |
13978 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
13979 | dev->mode_config.max_width = 4096; |
13980 | dev->mode_config.max_height = 4096; | |
79e53945 | 13981 | } else { |
a6c45cf0 CW |
13982 | dev->mode_config.max_width = 8192; |
13983 | dev->mode_config.max_height = 8192; | |
79e53945 | 13984 | } |
068be561 | 13985 | |
dc41c154 VS |
13986 | if (IS_845G(dev) || IS_I865G(dev)) { |
13987 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
13988 | dev->mode_config.cursor_height = 1023; | |
13989 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
13990 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
13991 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
13992 | } else { | |
13993 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
13994 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
13995 | } | |
13996 | ||
5d4545ae | 13997 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 13998 | |
28c97730 | 13999 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
14000 | INTEL_INFO(dev)->num_pipes, |
14001 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 14002 | |
055e393f | 14003 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 14004 | intel_crtc_init(dev, pipe); |
3bdcfc0c | 14005 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 14006 | ret = intel_plane_init(dev, pipe, sprite); |
7f1f3851 | 14007 | if (ret) |
06da8da2 | 14008 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 14009 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 14010 | } |
79e53945 JB |
14011 | } |
14012 | ||
f42bb70d JB |
14013 | intel_init_dpio(dev); |
14014 | ||
e72f9fbf | 14015 | intel_shared_dpll_init(dev); |
ee7b9f93 | 14016 | |
9cce37f4 JB |
14017 | /* Just disable it once at startup */ |
14018 | i915_disable_vga(dev); | |
79e53945 | 14019 | intel_setup_outputs(dev); |
11be49eb CW |
14020 | |
14021 | /* Just in case the BIOS is doing something questionable. */ | |
7ff0ebcc | 14022 | intel_fbc_disable(dev); |
fa9fa083 | 14023 | |
6e9f798d | 14024 | drm_modeset_lock_all(dev); |
fa9fa083 | 14025 | intel_modeset_setup_hw_state(dev, false); |
6e9f798d | 14026 | drm_modeset_unlock_all(dev); |
46f297fb | 14027 | |
d3fcc808 | 14028 | for_each_intel_crtc(dev, crtc) { |
46f297fb JB |
14029 | if (!crtc->active) |
14030 | continue; | |
14031 | ||
46f297fb | 14032 | /* |
46f297fb JB |
14033 | * Note that reserving the BIOS fb up front prevents us |
14034 | * from stuffing other stolen allocations like the ring | |
14035 | * on top. This prevents some ugliness at boot time, and | |
14036 | * can even allow for smooth boot transitions if the BIOS | |
14037 | * fb is large enough for the active pipe configuration. | |
14038 | */ | |
5724dbd1 DL |
14039 | if (dev_priv->display.get_initial_plane_config) { |
14040 | dev_priv->display.get_initial_plane_config(crtc, | |
46f297fb JB |
14041 | &crtc->plane_config); |
14042 | /* | |
14043 | * If the fb is shared between multiple heads, we'll | |
14044 | * just get the first one. | |
14045 | */ | |
f6936e29 | 14046 | intel_find_initial_plane_obj(crtc, &crtc->plane_config); |
46f297fb | 14047 | } |
46f297fb | 14048 | } |
2c7111db CW |
14049 | } |
14050 | ||
7fad798e DV |
14051 | static void intel_enable_pipe_a(struct drm_device *dev) |
14052 | { | |
14053 | struct intel_connector *connector; | |
14054 | struct drm_connector *crt = NULL; | |
14055 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 14056 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
14057 | |
14058 | /* We can't just switch on the pipe A, we need to set things up with a | |
14059 | * proper mode and output configuration. As a gross hack, enable pipe A | |
14060 | * by enabling the load detect pipe once. */ | |
3a3371ff | 14061 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
14062 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
14063 | crt = &connector->base; | |
14064 | break; | |
14065 | } | |
14066 | } | |
14067 | ||
14068 | if (!crt) | |
14069 | return; | |
14070 | ||
208bf9fd | 14071 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 14072 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
14073 | } |
14074 | ||
fa555837 DV |
14075 | static bool |
14076 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
14077 | { | |
7eb552ae BW |
14078 | struct drm_device *dev = crtc->base.dev; |
14079 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
14080 | u32 reg, val; |
14081 | ||
7eb552ae | 14082 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
14083 | return true; |
14084 | ||
14085 | reg = DSPCNTR(!crtc->plane); | |
14086 | val = I915_READ(reg); | |
14087 | ||
14088 | if ((val & DISPLAY_PLANE_ENABLE) && | |
14089 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
14090 | return false; | |
14091 | ||
14092 | return true; | |
14093 | } | |
14094 | ||
24929352 DV |
14095 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
14096 | { | |
14097 | struct drm_device *dev = crtc->base.dev; | |
14098 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 14099 | u32 reg; |
24929352 | 14100 | |
24929352 | 14101 | /* Clear any frame start delays used for debugging left by the BIOS */ |
6e3c9717 | 14102 | reg = PIPECONF(crtc->config->cpu_transcoder); |
24929352 DV |
14103 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
14104 | ||
d3eaf884 | 14105 | /* restore vblank interrupts to correct state */ |
9625604c | 14106 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 VS |
14107 | if (crtc->active) { |
14108 | update_scanline_offset(crtc); | |
9625604c DV |
14109 | drm_crtc_vblank_on(&crtc->base); |
14110 | } | |
d3eaf884 | 14111 | |
24929352 | 14112 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
14113 | * disable the crtc (and hence change the state) if it is wrong. Note |
14114 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
14115 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
14116 | struct intel_connector *connector; |
14117 | bool plane; | |
14118 | ||
24929352 DV |
14119 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
14120 | crtc->base.base.id); | |
14121 | ||
14122 | /* Pipe has the wrong plane attached and the plane is active. | |
14123 | * Temporarily change the plane mapping and disable everything | |
14124 | * ... */ | |
14125 | plane = crtc->plane; | |
14126 | crtc->plane = !plane; | |
9c8958bc | 14127 | crtc->primary_enabled = true; |
24929352 DV |
14128 | dev_priv->display.crtc_disable(&crtc->base); |
14129 | crtc->plane = plane; | |
14130 | ||
14131 | /* ... and break all links. */ | |
3a3371ff | 14132 | for_each_intel_connector(dev, connector) { |
24929352 DV |
14133 | if (connector->encoder->base.crtc != &crtc->base) |
14134 | continue; | |
14135 | ||
7f1950fb EE |
14136 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
14137 | connector->base.encoder = NULL; | |
24929352 | 14138 | } |
7f1950fb EE |
14139 | /* multiple connectors may have the same encoder: |
14140 | * handle them and break crtc link separately */ | |
3a3371ff | 14141 | for_each_intel_connector(dev, connector) |
7f1950fb EE |
14142 | if (connector->encoder->base.crtc == &crtc->base) { |
14143 | connector->encoder->base.crtc = NULL; | |
14144 | connector->encoder->connectors_active = false; | |
14145 | } | |
24929352 DV |
14146 | |
14147 | WARN_ON(crtc->active); | |
83d65738 | 14148 | crtc->base.state->enable = false; |
24929352 DV |
14149 | crtc->base.enabled = false; |
14150 | } | |
24929352 | 14151 | |
7fad798e DV |
14152 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
14153 | crtc->pipe == PIPE_A && !crtc->active) { | |
14154 | /* BIOS forgot to enable pipe A, this mostly happens after | |
14155 | * resume. Force-enable the pipe to fix this, the update_dpms | |
14156 | * call below we restore the pipe to the right state, but leave | |
14157 | * the required bits on. */ | |
14158 | intel_enable_pipe_a(dev); | |
14159 | } | |
14160 | ||
24929352 DV |
14161 | /* Adjust the state of the output pipe according to whether we |
14162 | * have active connectors/encoders. */ | |
14163 | intel_crtc_update_dpms(&crtc->base); | |
14164 | ||
83d65738 | 14165 | if (crtc->active != crtc->base.state->enable) { |
24929352 DV |
14166 | struct intel_encoder *encoder; |
14167 | ||
14168 | /* This can happen either due to bugs in the get_hw_state | |
14169 | * functions or because the pipe is force-enabled due to the | |
14170 | * pipe A quirk. */ | |
14171 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
14172 | crtc->base.base.id, | |
83d65738 | 14173 | crtc->base.state->enable ? "enabled" : "disabled", |
24929352 DV |
14174 | crtc->active ? "enabled" : "disabled"); |
14175 | ||
83d65738 | 14176 | crtc->base.state->enable = crtc->active; |
24929352 DV |
14177 | crtc->base.enabled = crtc->active; |
14178 | ||
14179 | /* Because we only establish the connector -> encoder -> | |
14180 | * crtc links if something is active, this means the | |
14181 | * crtc is now deactivated. Break the links. connector | |
14182 | * -> encoder links are only establish when things are | |
14183 | * actually up, hence no need to break them. */ | |
14184 | WARN_ON(crtc->active); | |
14185 | ||
14186 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
14187 | WARN_ON(encoder->connectors_active); | |
14188 | encoder->base.crtc = NULL; | |
14189 | } | |
14190 | } | |
c5ab3bc0 | 14191 | |
a3ed6aad | 14192 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
14193 | /* |
14194 | * We start out with underrun reporting disabled to avoid races. | |
14195 | * For correct bookkeeping mark this on active crtcs. | |
14196 | * | |
c5ab3bc0 DV |
14197 | * Also on gmch platforms we dont have any hardware bits to |
14198 | * disable the underrun reporting. Which means we need to start | |
14199 | * out with underrun reporting disabled also on inactive pipes, | |
14200 | * since otherwise we'll complain about the garbage we read when | |
14201 | * e.g. coming up after runtime pm. | |
14202 | * | |
4cc31489 DV |
14203 | * No protection against concurrent access is required - at |
14204 | * worst a fifo underrun happens which also sets this to false. | |
14205 | */ | |
14206 | crtc->cpu_fifo_underrun_disabled = true; | |
14207 | crtc->pch_fifo_underrun_disabled = true; | |
14208 | } | |
24929352 DV |
14209 | } |
14210 | ||
14211 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
14212 | { | |
14213 | struct intel_connector *connector; | |
14214 | struct drm_device *dev = encoder->base.dev; | |
14215 | ||
14216 | /* We need to check both for a crtc link (meaning that the | |
14217 | * encoder is active and trying to read from a pipe) and the | |
14218 | * pipe itself being active. */ | |
14219 | bool has_active_crtc = encoder->base.crtc && | |
14220 | to_intel_crtc(encoder->base.crtc)->active; | |
14221 | ||
14222 | if (encoder->connectors_active && !has_active_crtc) { | |
14223 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
14224 | encoder->base.base.id, | |
8e329a03 | 14225 | encoder->base.name); |
24929352 DV |
14226 | |
14227 | /* Connector is active, but has no active pipe. This is | |
14228 | * fallout from our resume register restoring. Disable | |
14229 | * the encoder manually again. */ | |
14230 | if (encoder->base.crtc) { | |
14231 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
14232 | encoder->base.base.id, | |
8e329a03 | 14233 | encoder->base.name); |
24929352 | 14234 | encoder->disable(encoder); |
a62d1497 VS |
14235 | if (encoder->post_disable) |
14236 | encoder->post_disable(encoder); | |
24929352 | 14237 | } |
7f1950fb EE |
14238 | encoder->base.crtc = NULL; |
14239 | encoder->connectors_active = false; | |
24929352 DV |
14240 | |
14241 | /* Inconsistent output/port/pipe state happens presumably due to | |
14242 | * a bug in one of the get_hw_state functions. Or someplace else | |
14243 | * in our code, like the register restore mess on resume. Clamp | |
14244 | * things to off as a safer default. */ | |
3a3371ff | 14245 | for_each_intel_connector(dev, connector) { |
24929352 DV |
14246 | if (connector->encoder != encoder) |
14247 | continue; | |
7f1950fb EE |
14248 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
14249 | connector->base.encoder = NULL; | |
24929352 DV |
14250 | } |
14251 | } | |
14252 | /* Enabled encoders without active connectors will be fixed in | |
14253 | * the crtc fixup. */ | |
14254 | } | |
14255 | ||
04098753 | 14256 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
14257 | { |
14258 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 14259 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 14260 | |
04098753 ID |
14261 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
14262 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
14263 | i915_disable_vga(dev); | |
14264 | } | |
14265 | } | |
14266 | ||
14267 | void i915_redisable_vga(struct drm_device *dev) | |
14268 | { | |
14269 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14270 | ||
8dc8a27c PZ |
14271 | /* This function can be called both from intel_modeset_setup_hw_state or |
14272 | * at a very early point in our resume sequence, where the power well | |
14273 | * structures are not yet restored. Since this function is at a very | |
14274 | * paranoid "someone might have enabled VGA while we were not looking" | |
14275 | * level, just check if the power well is enabled instead of trying to | |
14276 | * follow the "don't touch the power well if we don't need it" policy | |
14277 | * the rest of the driver uses. */ | |
f458ebbc | 14278 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
14279 | return; |
14280 | ||
04098753 | 14281 | i915_redisable_vga_power_on(dev); |
0fde901f KM |
14282 | } |
14283 | ||
98ec7739 VS |
14284 | static bool primary_get_hw_state(struct intel_crtc *crtc) |
14285 | { | |
14286 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
14287 | ||
14288 | if (!crtc->active) | |
14289 | return false; | |
14290 | ||
14291 | return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE; | |
14292 | } | |
14293 | ||
30e984df | 14294 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
14295 | { |
14296 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14297 | enum pipe pipe; | |
24929352 DV |
14298 | struct intel_crtc *crtc; |
14299 | struct intel_encoder *encoder; | |
14300 | struct intel_connector *connector; | |
5358901f | 14301 | int i; |
24929352 | 14302 | |
d3fcc808 | 14303 | for_each_intel_crtc(dev, crtc) { |
6e3c9717 | 14304 | memset(crtc->config, 0, sizeof(*crtc->config)); |
3b117c8f | 14305 | |
6e3c9717 | 14306 | crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE; |
9953599b | 14307 | |
0e8ffe1b | 14308 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
6e3c9717 | 14309 | crtc->config); |
24929352 | 14310 | |
83d65738 | 14311 | crtc->base.state->enable = crtc->active; |
24929352 | 14312 | crtc->base.enabled = crtc->active; |
98ec7739 | 14313 | crtc->primary_enabled = primary_get_hw_state(crtc); |
24929352 DV |
14314 | |
14315 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
14316 | crtc->base.base.id, | |
14317 | crtc->active ? "enabled" : "disabled"); | |
14318 | } | |
14319 | ||
5358901f DV |
14320 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
14321 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
14322 | ||
3e369b76 ACO |
14323 | pll->on = pll->get_hw_state(dev_priv, pll, |
14324 | &pll->config.hw_state); | |
5358901f | 14325 | pll->active = 0; |
3e369b76 | 14326 | pll->config.crtc_mask = 0; |
d3fcc808 | 14327 | for_each_intel_crtc(dev, crtc) { |
1e6f2ddc | 14328 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) { |
5358901f | 14329 | pll->active++; |
3e369b76 | 14330 | pll->config.crtc_mask |= 1 << crtc->pipe; |
1e6f2ddc | 14331 | } |
5358901f | 14332 | } |
5358901f | 14333 | |
1e6f2ddc | 14334 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 14335 | pll->name, pll->config.crtc_mask, pll->on); |
bd2bb1b9 | 14336 | |
3e369b76 | 14337 | if (pll->config.crtc_mask) |
bd2bb1b9 | 14338 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
5358901f DV |
14339 | } |
14340 | ||
b2784e15 | 14341 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
14342 | pipe = 0; |
14343 | ||
14344 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
14345 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
14346 | encoder->base.crtc = &crtc->base; | |
6e3c9717 | 14347 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
14348 | } else { |
14349 | encoder->base.crtc = NULL; | |
14350 | } | |
14351 | ||
14352 | encoder->connectors_active = false; | |
6f2bcceb | 14353 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 14354 | encoder->base.base.id, |
8e329a03 | 14355 | encoder->base.name, |
24929352 | 14356 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 14357 | pipe_name(pipe)); |
24929352 DV |
14358 | } |
14359 | ||
3a3371ff | 14360 | for_each_intel_connector(dev, connector) { |
24929352 DV |
14361 | if (connector->get_hw_state(connector)) { |
14362 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
14363 | connector->encoder->connectors_active = true; | |
14364 | connector->base.encoder = &connector->encoder->base; | |
14365 | } else { | |
14366 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
14367 | connector->base.encoder = NULL; | |
14368 | } | |
14369 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
14370 | connector->base.base.id, | |
c23cc417 | 14371 | connector->base.name, |
24929352 DV |
14372 | connector->base.encoder ? "enabled" : "disabled"); |
14373 | } | |
30e984df DV |
14374 | } |
14375 | ||
14376 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm | |
14377 | * and i915 state tracking structures. */ | |
14378 | void intel_modeset_setup_hw_state(struct drm_device *dev, | |
14379 | bool force_restore) | |
14380 | { | |
14381 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14382 | enum pipe pipe; | |
30e984df DV |
14383 | struct intel_crtc *crtc; |
14384 | struct intel_encoder *encoder; | |
35c95375 | 14385 | int i; |
30e984df DV |
14386 | |
14387 | intel_modeset_readout_hw_state(dev); | |
24929352 | 14388 | |
babea61d JB |
14389 | /* |
14390 | * Now that we have the config, copy it to each CRTC struct | |
14391 | * Note that this could go away if we move to using crtc_config | |
14392 | * checking everywhere. | |
14393 | */ | |
d3fcc808 | 14394 | for_each_intel_crtc(dev, crtc) { |
d330a953 | 14395 | if (crtc->active && i915.fastboot) { |
6e3c9717 ACO |
14396 | intel_mode_from_pipe_config(&crtc->base.mode, |
14397 | crtc->config); | |
babea61d JB |
14398 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", |
14399 | crtc->base.base.id); | |
14400 | drm_mode_debug_printmodeline(&crtc->base.mode); | |
14401 | } | |
14402 | } | |
14403 | ||
24929352 | 14404 | /* HW state is read out, now we need to sanitize this mess. */ |
b2784e15 | 14405 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
14406 | intel_sanitize_encoder(encoder); |
14407 | } | |
14408 | ||
055e393f | 14409 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
14410 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
14411 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
14412 | intel_dump_pipe_config(crtc, crtc->config, |
14413 | "[setup_hw_state]"); | |
24929352 | 14414 | } |
9a935856 | 14415 | |
d29b2f9d ACO |
14416 | intel_modeset_update_connector_atomic_state(dev); |
14417 | ||
35c95375 DV |
14418 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
14419 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
14420 | ||
14421 | if (!pll->on || pll->active) | |
14422 | continue; | |
14423 | ||
14424 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
14425 | ||
14426 | pll->disable(dev_priv, pll); | |
14427 | pll->on = false; | |
14428 | } | |
14429 | ||
3078999f PB |
14430 | if (IS_GEN9(dev)) |
14431 | skl_wm_get_hw_state(dev); | |
14432 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 VS |
14433 | ilk_wm_get_hw_state(dev); |
14434 | ||
45e2b5f6 | 14435 | if (force_restore) { |
7d0bc1ea VS |
14436 | i915_redisable_vga(dev); |
14437 | ||
f30da187 DV |
14438 | /* |
14439 | * We need to use raw interfaces for restoring state to avoid | |
14440 | * checking (bogus) intermediate states. | |
14441 | */ | |
055e393f | 14442 | for_each_pipe(dev_priv, pipe) { |
b5644d05 JB |
14443 | struct drm_crtc *crtc = |
14444 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
f30da187 | 14445 | |
83a57153 | 14446 | intel_crtc_restore_mode(crtc); |
45e2b5f6 DV |
14447 | } |
14448 | } else { | |
14449 | intel_modeset_update_staged_output_state(dev); | |
14450 | } | |
8af6cf88 DV |
14451 | |
14452 | intel_modeset_check_state(dev); | |
2c7111db CW |
14453 | } |
14454 | ||
14455 | void intel_modeset_gem_init(struct drm_device *dev) | |
14456 | { | |
92122789 | 14457 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd | 14458 | struct drm_crtc *c; |
2ff8fde1 | 14459 | struct drm_i915_gem_object *obj; |
484b41dd | 14460 | |
ae48434c ID |
14461 | mutex_lock(&dev->struct_mutex); |
14462 | intel_init_gt_powersave(dev); | |
14463 | mutex_unlock(&dev->struct_mutex); | |
14464 | ||
92122789 JB |
14465 | /* |
14466 | * There may be no VBT; and if the BIOS enabled SSC we can | |
14467 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
14468 | * BIOS isn't using it, don't assume it will work even if the VBT | |
14469 | * indicates as much. | |
14470 | */ | |
14471 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
14472 | dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
14473 | DREF_SSC1_ENABLE); | |
14474 | ||
1833b134 | 14475 | intel_modeset_init_hw(dev); |
02e792fb DV |
14476 | |
14477 | intel_setup_overlay(dev); | |
484b41dd JB |
14478 | |
14479 | /* | |
14480 | * Make sure any fbs we allocated at startup are properly | |
14481 | * pinned & fenced. When we do the allocation it's too early | |
14482 | * for this. | |
14483 | */ | |
14484 | mutex_lock(&dev->struct_mutex); | |
70e1e0ec | 14485 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
14486 | obj = intel_fb_obj(c->primary->fb); |
14487 | if (obj == NULL) | |
484b41dd JB |
14488 | continue; |
14489 | ||
850c4cdc TU |
14490 | if (intel_pin_and_fence_fb_obj(c->primary, |
14491 | c->primary->fb, | |
82bc3b2d | 14492 | c->primary->state, |
850c4cdc | 14493 | NULL)) { |
484b41dd JB |
14494 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
14495 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
14496 | drm_framebuffer_unreference(c->primary->fb); |
14497 | c->primary->fb = NULL; | |
afd65eb4 | 14498 | update_state_fb(c->primary); |
484b41dd JB |
14499 | } |
14500 | } | |
14501 | mutex_unlock(&dev->struct_mutex); | |
0962c3c9 VS |
14502 | |
14503 | intel_backlight_register(dev); | |
79e53945 JB |
14504 | } |
14505 | ||
4932e2c3 ID |
14506 | void intel_connector_unregister(struct intel_connector *intel_connector) |
14507 | { | |
14508 | struct drm_connector *connector = &intel_connector->base; | |
14509 | ||
14510 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 14511 | drm_connector_unregister(connector); |
4932e2c3 ID |
14512 | } |
14513 | ||
79e53945 JB |
14514 | void intel_modeset_cleanup(struct drm_device *dev) |
14515 | { | |
652c393a | 14516 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9255d57 | 14517 | struct drm_connector *connector; |
652c393a | 14518 | |
2eb5252e ID |
14519 | intel_disable_gt_powersave(dev); |
14520 | ||
0962c3c9 VS |
14521 | intel_backlight_unregister(dev); |
14522 | ||
fd0c0642 DV |
14523 | /* |
14524 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 14525 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
14526 | * experience fancy races otherwise. |
14527 | */ | |
2aeb7d3a | 14528 | intel_irq_uninstall(dev_priv); |
eb21b92b | 14529 | |
fd0c0642 DV |
14530 | /* |
14531 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
14532 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
14533 | */ | |
f87ea761 | 14534 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 14535 | |
652c393a JB |
14536 | mutex_lock(&dev->struct_mutex); |
14537 | ||
723bfd70 JB |
14538 | intel_unregister_dsm_handler(); |
14539 | ||
7ff0ebcc | 14540 | intel_fbc_disable(dev); |
e70236a8 | 14541 | |
69341a5e KH |
14542 | mutex_unlock(&dev->struct_mutex); |
14543 | ||
1630fe75 CW |
14544 | /* flush any delayed tasks or pending work */ |
14545 | flush_scheduled_work(); | |
14546 | ||
db31af1d JN |
14547 | /* destroy the backlight and sysfs files before encoders/connectors */ |
14548 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4932e2c3 ID |
14549 | struct intel_connector *intel_connector; |
14550 | ||
14551 | intel_connector = to_intel_connector(connector); | |
14552 | intel_connector->unregister(intel_connector); | |
db31af1d | 14553 | } |
d9255d57 | 14554 | |
79e53945 | 14555 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
14556 | |
14557 | intel_cleanup_overlay(dev); | |
ae48434c ID |
14558 | |
14559 | mutex_lock(&dev->struct_mutex); | |
14560 | intel_cleanup_gt_powersave(dev); | |
14561 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
14562 | } |
14563 | ||
f1c79df3 ZW |
14564 | /* |
14565 | * Return which encoder is currently attached for connector. | |
14566 | */ | |
df0e9248 | 14567 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 14568 | { |
df0e9248 CW |
14569 | return &intel_attached_encoder(connector)->base; |
14570 | } | |
f1c79df3 | 14571 | |
df0e9248 CW |
14572 | void intel_connector_attach_encoder(struct intel_connector *connector, |
14573 | struct intel_encoder *encoder) | |
14574 | { | |
14575 | connector->encoder = encoder; | |
14576 | drm_mode_connector_attach_encoder(&connector->base, | |
14577 | &encoder->base); | |
79e53945 | 14578 | } |
28d52043 DA |
14579 | |
14580 | /* | |
14581 | * set vga decode state - true == enable VGA decode | |
14582 | */ | |
14583 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
14584 | { | |
14585 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 14586 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
14587 | u16 gmch_ctrl; |
14588 | ||
75fa041d CW |
14589 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
14590 | DRM_ERROR("failed to read control word\n"); | |
14591 | return -EIO; | |
14592 | } | |
14593 | ||
c0cc8a55 CW |
14594 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
14595 | return 0; | |
14596 | ||
28d52043 DA |
14597 | if (state) |
14598 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
14599 | else | |
14600 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
14601 | |
14602 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
14603 | DRM_ERROR("failed to write control word\n"); | |
14604 | return -EIO; | |
14605 | } | |
14606 | ||
28d52043 DA |
14607 | return 0; |
14608 | } | |
c4a1d9e4 | 14609 | |
c4a1d9e4 | 14610 | struct intel_display_error_state { |
ff57f1b0 PZ |
14611 | |
14612 | u32 power_well_driver; | |
14613 | ||
63b66e5b CW |
14614 | int num_transcoders; |
14615 | ||
c4a1d9e4 CW |
14616 | struct intel_cursor_error_state { |
14617 | u32 control; | |
14618 | u32 position; | |
14619 | u32 base; | |
14620 | u32 size; | |
52331309 | 14621 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
14622 | |
14623 | struct intel_pipe_error_state { | |
ddf9c536 | 14624 | bool power_domain_on; |
c4a1d9e4 | 14625 | u32 source; |
f301b1e1 | 14626 | u32 stat; |
52331309 | 14627 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
14628 | |
14629 | struct intel_plane_error_state { | |
14630 | u32 control; | |
14631 | u32 stride; | |
14632 | u32 size; | |
14633 | u32 pos; | |
14634 | u32 addr; | |
14635 | u32 surface; | |
14636 | u32 tile_offset; | |
52331309 | 14637 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
14638 | |
14639 | struct intel_transcoder_error_state { | |
ddf9c536 | 14640 | bool power_domain_on; |
63b66e5b CW |
14641 | enum transcoder cpu_transcoder; |
14642 | ||
14643 | u32 conf; | |
14644 | ||
14645 | u32 htotal; | |
14646 | u32 hblank; | |
14647 | u32 hsync; | |
14648 | u32 vtotal; | |
14649 | u32 vblank; | |
14650 | u32 vsync; | |
14651 | } transcoder[4]; | |
c4a1d9e4 CW |
14652 | }; |
14653 | ||
14654 | struct intel_display_error_state * | |
14655 | intel_display_capture_error_state(struct drm_device *dev) | |
14656 | { | |
fbee40df | 14657 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 14658 | struct intel_display_error_state *error; |
63b66e5b CW |
14659 | int transcoders[] = { |
14660 | TRANSCODER_A, | |
14661 | TRANSCODER_B, | |
14662 | TRANSCODER_C, | |
14663 | TRANSCODER_EDP, | |
14664 | }; | |
c4a1d9e4 CW |
14665 | int i; |
14666 | ||
63b66e5b CW |
14667 | if (INTEL_INFO(dev)->num_pipes == 0) |
14668 | return NULL; | |
14669 | ||
9d1cb914 | 14670 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
14671 | if (error == NULL) |
14672 | return NULL; | |
14673 | ||
190be112 | 14674 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
14675 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
14676 | ||
055e393f | 14677 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 14678 | error->pipe[i].power_domain_on = |
f458ebbc DV |
14679 | __intel_display_power_is_enabled(dev_priv, |
14680 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 14681 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
14682 | continue; |
14683 | ||
5efb3e28 VS |
14684 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
14685 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
14686 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
14687 | |
14688 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
14689 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 14690 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 14691 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
14692 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
14693 | } | |
ca291363 PZ |
14694 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
14695 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
14696 | if (INTEL_INFO(dev)->gen >= 4) { |
14697 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
14698 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
14699 | } | |
14700 | ||
c4a1d9e4 | 14701 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 14702 | |
3abfce77 | 14703 | if (HAS_GMCH_DISPLAY(dev)) |
f301b1e1 | 14704 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
14705 | } |
14706 | ||
14707 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
14708 | if (HAS_DDI(dev_priv->dev)) | |
14709 | error->num_transcoders++; /* Account for eDP. */ | |
14710 | ||
14711 | for (i = 0; i < error->num_transcoders; i++) { | |
14712 | enum transcoder cpu_transcoder = transcoders[i]; | |
14713 | ||
ddf9c536 | 14714 | error->transcoder[i].power_domain_on = |
f458ebbc | 14715 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 14716 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 14717 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
14718 | continue; |
14719 | ||
63b66e5b CW |
14720 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
14721 | ||
14722 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
14723 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
14724 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
14725 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
14726 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
14727 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
14728 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
14729 | } |
14730 | ||
14731 | return error; | |
14732 | } | |
14733 | ||
edc3d884 MK |
14734 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
14735 | ||
c4a1d9e4 | 14736 | void |
edc3d884 | 14737 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
14738 | struct drm_device *dev, |
14739 | struct intel_display_error_state *error) | |
14740 | { | |
055e393f | 14741 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
14742 | int i; |
14743 | ||
63b66e5b CW |
14744 | if (!error) |
14745 | return; | |
14746 | ||
edc3d884 | 14747 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 14748 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 14749 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 14750 | error->power_well_driver); |
055e393f | 14751 | for_each_pipe(dev_priv, i) { |
edc3d884 | 14752 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 ID |
14753 | err_printf(m, " Power: %s\n", |
14754 | error->pipe[i].power_domain_on ? "on" : "off"); | |
edc3d884 | 14755 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 14756 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
14757 | |
14758 | err_printf(m, "Plane [%d]:\n", i); | |
14759 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
14760 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 14761 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
14762 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
14763 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 14764 | } |
4b71a570 | 14765 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 14766 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 14767 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
14768 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
14769 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
14770 | } |
14771 | ||
edc3d884 MK |
14772 | err_printf(m, "Cursor [%d]:\n", i); |
14773 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
14774 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
14775 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 14776 | } |
63b66e5b CW |
14777 | |
14778 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 14779 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 14780 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 ID |
14781 | err_printf(m, " Power: %s\n", |
14782 | error->transcoder[i].power_domain_on ? "on" : "off"); | |
63b66e5b CW |
14783 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
14784 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
14785 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
14786 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
14787 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
14788 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
14789 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
14790 | } | |
c4a1d9e4 | 14791 | } |
e2fcdaa9 VS |
14792 | |
14793 | void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file) | |
14794 | { | |
14795 | struct intel_crtc *crtc; | |
14796 | ||
14797 | for_each_intel_crtc(dev, crtc) { | |
14798 | struct intel_unpin_work *work; | |
e2fcdaa9 | 14799 | |
5e2d7afc | 14800 | spin_lock_irq(&dev->event_lock); |
e2fcdaa9 VS |
14801 | |
14802 | work = crtc->unpin_work; | |
14803 | ||
14804 | if (work && work->event && | |
14805 | work->event->base.file_priv == file) { | |
14806 | kfree(work->event); | |
14807 | work->event = NULL; | |
14808 | } | |
14809 | ||
5e2d7afc | 14810 | spin_unlock_irq(&dev->event_lock); |
e2fcdaa9 VS |
14811 | } |
14812 | } |