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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
db18b6a6 | 39 | #include "intel_dsi.h" |
e5510fac | 40 | #include "i915_trace.h" |
319c1d42 | 41 | #include <drm/drm_atomic.h> |
c196e1d6 | 42 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
43 | #include <drm/drm_dp_helper.h> |
44 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
45 | #include <drm/drm_plane_helper.h> |
46 | #include <drm/drm_rect.h> | |
c0f372b3 | 47 | #include <linux/dma_remapping.h> |
fd8e058a AG |
48 | #include <linux/reservation.h> |
49 | #include <linux/dma-buf.h> | |
79e53945 | 50 | |
465c120c | 51 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 52 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
53 | DRM_FORMAT_C8, |
54 | DRM_FORMAT_RGB565, | |
465c120c | 55 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 56 | DRM_FORMAT_XRGB8888, |
465c120c MR |
57 | }; |
58 | ||
59 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 60 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
61 | DRM_FORMAT_C8, |
62 | DRM_FORMAT_RGB565, | |
63 | DRM_FORMAT_XRGB8888, | |
64 | DRM_FORMAT_XBGR8888, | |
65 | DRM_FORMAT_XRGB2101010, | |
66 | DRM_FORMAT_XBGR2101010, | |
67 | }; | |
68 | ||
69 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
70 | DRM_FORMAT_C8, |
71 | DRM_FORMAT_RGB565, | |
72 | DRM_FORMAT_XRGB8888, | |
465c120c | 73 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 74 | DRM_FORMAT_ARGB8888, |
465c120c MR |
75 | DRM_FORMAT_ABGR8888, |
76 | DRM_FORMAT_XRGB2101010, | |
465c120c | 77 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
78 | DRM_FORMAT_YUYV, |
79 | DRM_FORMAT_YVYU, | |
80 | DRM_FORMAT_UYVY, | |
81 | DRM_FORMAT_VYUY, | |
465c120c MR |
82 | }; |
83 | ||
3d7d6510 MR |
84 | /* Cursor formats */ |
85 | static const uint32_t intel_cursor_formats[] = { | |
86 | DRM_FORMAT_ARGB8888, | |
87 | }; | |
88 | ||
f1f644dc | 89 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 90 | struct intel_crtc_state *pipe_config); |
18442d08 | 91 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 92 | struct intel_crtc_state *pipe_config); |
f1f644dc | 93 | |
eb1bfe80 JB |
94 | static int intel_framebuffer_init(struct drm_device *dev, |
95 | struct intel_framebuffer *ifb, | |
96 | struct drm_mode_fb_cmd2 *mode_cmd, | |
97 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
98 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
99 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
bc58be60 | 100 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc); |
29407aab | 101 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
102 | struct intel_link_m_n *m_n, |
103 | struct intel_link_m_n *m2_n2); | |
29407aab | 104 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 | 105 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
391bf048 | 106 | static void haswell_set_pipemisc(struct drm_crtc *crtc); |
d288f65f | 107 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 108 | const struct intel_crtc_state *pipe_config); |
d288f65f | 109 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 110 | const struct intel_crtc_state *pipe_config); |
549e2bfb CK |
111 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
112 | struct intel_crtc_state *crtc_state); | |
bfd16b2a ML |
113 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
114 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
115 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
043e9bda | 116 | static void intel_modeset_setup_hw_state(struct drm_device *dev); |
2622a081 | 117 | static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc); |
4e5ca60f | 118 | static int ilk_max_pixel_rate(struct drm_atomic_state *state); |
143f73b3 ML |
119 | static void intel_modeset_verify_crtc(struct drm_crtc *crtc, |
120 | struct drm_crtc_state *old_state, | |
121 | struct drm_crtc_state *new_state); | |
d1b32c32 | 122 | static int broxton_calc_cdclk(int max_pixclk); |
e7457a9a | 123 | |
d4906093 | 124 | struct intel_limit { |
4c5def93 ACO |
125 | struct { |
126 | int min, max; | |
127 | } dot, vco, n, m, m1, m2, p, p1; | |
128 | ||
129 | struct { | |
130 | int dot_limit; | |
131 | int p2_slow, p2_fast; | |
132 | } p2; | |
d4906093 | 133 | }; |
79e53945 | 134 | |
bfa7df01 VS |
135 | /* returns HPLL frequency in kHz */ |
136 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) | |
137 | { | |
138 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
139 | ||
140 | /* Obtain SKU information */ | |
141 | mutex_lock(&dev_priv->sb_lock); | |
142 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
143 | CCK_FUSE_HPLL_FREQ_MASK; | |
144 | mutex_unlock(&dev_priv->sb_lock); | |
145 | ||
146 | return vco_freq[hpll_freq] * 1000; | |
147 | } | |
148 | ||
c30fec65 VS |
149 | int vlv_get_cck_clock(struct drm_i915_private *dev_priv, |
150 | const char *name, u32 reg, int ref_freq) | |
bfa7df01 VS |
151 | { |
152 | u32 val; | |
153 | int divider; | |
154 | ||
bfa7df01 VS |
155 | mutex_lock(&dev_priv->sb_lock); |
156 | val = vlv_cck_read(dev_priv, reg); | |
157 | mutex_unlock(&dev_priv->sb_lock); | |
158 | ||
159 | divider = val & CCK_FREQUENCY_VALUES; | |
160 | ||
161 | WARN((val & CCK_FREQUENCY_STATUS) != | |
162 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
163 | "%s change in progress\n", name); | |
164 | ||
c30fec65 VS |
165 | return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); |
166 | } | |
167 | ||
168 | static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, | |
169 | const char *name, u32 reg) | |
170 | { | |
171 | if (dev_priv->hpll_freq == 0) | |
172 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
173 | ||
174 | return vlv_get_cck_clock(dev_priv, name, reg, | |
175 | dev_priv->hpll_freq); | |
bfa7df01 VS |
176 | } |
177 | ||
e7dc33f3 VS |
178 | static int |
179 | intel_pch_rawclk(struct drm_i915_private *dev_priv) | |
d2acd215 | 180 | { |
e7dc33f3 VS |
181 | return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; |
182 | } | |
d2acd215 | 183 | |
e7dc33f3 VS |
184 | static int |
185 | intel_vlv_hrawclk(struct drm_i915_private *dev_priv) | |
186 | { | |
19ab4ed3 | 187 | /* RAWCLK_FREQ_VLV register updated from power well code */ |
35d38d1f VS |
188 | return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", |
189 | CCK_DISPLAY_REF_CLOCK_CONTROL); | |
d2acd215 DV |
190 | } |
191 | ||
e7dc33f3 VS |
192 | static int |
193 | intel_g4x_hrawclk(struct drm_i915_private *dev_priv) | |
79e50a4f | 194 | { |
79e50a4f JN |
195 | uint32_t clkcfg; |
196 | ||
e7dc33f3 | 197 | /* hrawclock is 1/4 the FSB frequency */ |
79e50a4f JN |
198 | clkcfg = I915_READ(CLKCFG); |
199 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
200 | case CLKCFG_FSB_400: | |
e7dc33f3 | 201 | return 100000; |
79e50a4f | 202 | case CLKCFG_FSB_533: |
e7dc33f3 | 203 | return 133333; |
79e50a4f | 204 | case CLKCFG_FSB_667: |
e7dc33f3 | 205 | return 166667; |
79e50a4f | 206 | case CLKCFG_FSB_800: |
e7dc33f3 | 207 | return 200000; |
79e50a4f | 208 | case CLKCFG_FSB_1067: |
e7dc33f3 | 209 | return 266667; |
79e50a4f | 210 | case CLKCFG_FSB_1333: |
e7dc33f3 | 211 | return 333333; |
79e50a4f JN |
212 | /* these two are just a guess; one of them might be right */ |
213 | case CLKCFG_FSB_1600: | |
214 | case CLKCFG_FSB_1600_ALT: | |
e7dc33f3 | 215 | return 400000; |
79e50a4f | 216 | default: |
e7dc33f3 | 217 | return 133333; |
79e50a4f JN |
218 | } |
219 | } | |
220 | ||
19ab4ed3 | 221 | void intel_update_rawclk(struct drm_i915_private *dev_priv) |
e7dc33f3 VS |
222 | { |
223 | if (HAS_PCH_SPLIT(dev_priv)) | |
224 | dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv); | |
225 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
226 | dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv); | |
227 | else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv)) | |
228 | dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv); | |
229 | else | |
230 | return; /* no rawclk on other platforms, or no need to know it */ | |
231 | ||
232 | DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq); | |
233 | } | |
234 | ||
bfa7df01 VS |
235 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
236 | { | |
666a4537 | 237 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
bfa7df01 VS |
238 | return; |
239 | ||
240 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
241 | CCK_CZ_CLOCK_CONTROL); | |
242 | ||
243 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); | |
244 | } | |
245 | ||
021357ac | 246 | static inline u32 /* units of 100MHz */ |
21a727b3 VS |
247 | intel_fdi_link_freq(struct drm_i915_private *dev_priv, |
248 | const struct intel_crtc_state *pipe_config) | |
021357ac | 249 | { |
21a727b3 VS |
250 | if (HAS_DDI(dev_priv)) |
251 | return pipe_config->port_clock; /* SPLL */ | |
252 | else if (IS_GEN5(dev_priv)) | |
253 | return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000; | |
e3b247da | 254 | else |
21a727b3 | 255 | return 270000; |
021357ac CW |
256 | } |
257 | ||
1b6f4958 | 258 | static const struct intel_limit intel_limits_i8xx_dac = { |
0206e353 | 259 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 260 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 261 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
262 | .m = { .min = 96, .max = 140 }, |
263 | .m1 = { .min = 18, .max = 26 }, | |
264 | .m2 = { .min = 6, .max = 16 }, | |
265 | .p = { .min = 4, .max = 128 }, | |
266 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
267 | .p2 = { .dot_limit = 165000, |
268 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
269 | }; |
270 | ||
1b6f4958 | 271 | static const struct intel_limit intel_limits_i8xx_dvo = { |
5d536e28 | 272 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 273 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 274 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
275 | .m = { .min = 96, .max = 140 }, |
276 | .m1 = { .min = 18, .max = 26 }, | |
277 | .m2 = { .min = 6, .max = 16 }, | |
278 | .p = { .min = 4, .max = 128 }, | |
279 | .p1 = { .min = 2, .max = 33 }, | |
280 | .p2 = { .dot_limit = 165000, | |
281 | .p2_slow = 4, .p2_fast = 4 }, | |
282 | }; | |
283 | ||
1b6f4958 | 284 | static const struct intel_limit intel_limits_i8xx_lvds = { |
0206e353 | 285 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 286 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 287 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
288 | .m = { .min = 96, .max = 140 }, |
289 | .m1 = { .min = 18, .max = 26 }, | |
290 | .m2 = { .min = 6, .max = 16 }, | |
291 | .p = { .min = 4, .max = 128 }, | |
292 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
293 | .p2 = { .dot_limit = 165000, |
294 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 295 | }; |
273e27ca | 296 | |
1b6f4958 | 297 | static const struct intel_limit intel_limits_i9xx_sdvo = { |
0206e353 AJ |
298 | .dot = { .min = 20000, .max = 400000 }, |
299 | .vco = { .min = 1400000, .max = 2800000 }, | |
300 | .n = { .min = 1, .max = 6 }, | |
301 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
302 | .m1 = { .min = 8, .max = 18 }, |
303 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
304 | .p = { .min = 5, .max = 80 }, |
305 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
306 | .p2 = { .dot_limit = 200000, |
307 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
308 | }; |
309 | ||
1b6f4958 | 310 | static const struct intel_limit intel_limits_i9xx_lvds = { |
0206e353 AJ |
311 | .dot = { .min = 20000, .max = 400000 }, |
312 | .vco = { .min = 1400000, .max = 2800000 }, | |
313 | .n = { .min = 1, .max = 6 }, | |
314 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
315 | .m1 = { .min = 8, .max = 18 }, |
316 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
317 | .p = { .min = 7, .max = 98 }, |
318 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
319 | .p2 = { .dot_limit = 112000, |
320 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
321 | }; |
322 | ||
273e27ca | 323 | |
1b6f4958 | 324 | static const struct intel_limit intel_limits_g4x_sdvo = { |
273e27ca EA |
325 | .dot = { .min = 25000, .max = 270000 }, |
326 | .vco = { .min = 1750000, .max = 3500000}, | |
327 | .n = { .min = 1, .max = 4 }, | |
328 | .m = { .min = 104, .max = 138 }, | |
329 | .m1 = { .min = 17, .max = 23 }, | |
330 | .m2 = { .min = 5, .max = 11 }, | |
331 | .p = { .min = 10, .max = 30 }, | |
332 | .p1 = { .min = 1, .max = 3}, | |
333 | .p2 = { .dot_limit = 270000, | |
334 | .p2_slow = 10, | |
335 | .p2_fast = 10 | |
044c7c41 | 336 | }, |
e4b36699 KP |
337 | }; |
338 | ||
1b6f4958 | 339 | static const struct intel_limit intel_limits_g4x_hdmi = { |
273e27ca EA |
340 | .dot = { .min = 22000, .max = 400000 }, |
341 | .vco = { .min = 1750000, .max = 3500000}, | |
342 | .n = { .min = 1, .max = 4 }, | |
343 | .m = { .min = 104, .max = 138 }, | |
344 | .m1 = { .min = 16, .max = 23 }, | |
345 | .m2 = { .min = 5, .max = 11 }, | |
346 | .p = { .min = 5, .max = 80 }, | |
347 | .p1 = { .min = 1, .max = 8}, | |
348 | .p2 = { .dot_limit = 165000, | |
349 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
350 | }; |
351 | ||
1b6f4958 | 352 | static const struct intel_limit intel_limits_g4x_single_channel_lvds = { |
273e27ca EA |
353 | .dot = { .min = 20000, .max = 115000 }, |
354 | .vco = { .min = 1750000, .max = 3500000 }, | |
355 | .n = { .min = 1, .max = 3 }, | |
356 | .m = { .min = 104, .max = 138 }, | |
357 | .m1 = { .min = 17, .max = 23 }, | |
358 | .m2 = { .min = 5, .max = 11 }, | |
359 | .p = { .min = 28, .max = 112 }, | |
360 | .p1 = { .min = 2, .max = 8 }, | |
361 | .p2 = { .dot_limit = 0, | |
362 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 363 | }, |
e4b36699 KP |
364 | }; |
365 | ||
1b6f4958 | 366 | static const struct intel_limit intel_limits_g4x_dual_channel_lvds = { |
273e27ca EA |
367 | .dot = { .min = 80000, .max = 224000 }, |
368 | .vco = { .min = 1750000, .max = 3500000 }, | |
369 | .n = { .min = 1, .max = 3 }, | |
370 | .m = { .min = 104, .max = 138 }, | |
371 | .m1 = { .min = 17, .max = 23 }, | |
372 | .m2 = { .min = 5, .max = 11 }, | |
373 | .p = { .min = 14, .max = 42 }, | |
374 | .p1 = { .min = 2, .max = 6 }, | |
375 | .p2 = { .dot_limit = 0, | |
376 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 377 | }, |
e4b36699 KP |
378 | }; |
379 | ||
1b6f4958 | 380 | static const struct intel_limit intel_limits_pineview_sdvo = { |
0206e353 AJ |
381 | .dot = { .min = 20000, .max = 400000}, |
382 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 383 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
384 | .n = { .min = 3, .max = 6 }, |
385 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 386 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
387 | .m1 = { .min = 0, .max = 0 }, |
388 | .m2 = { .min = 0, .max = 254 }, | |
389 | .p = { .min = 5, .max = 80 }, | |
390 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
391 | .p2 = { .dot_limit = 200000, |
392 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
393 | }; |
394 | ||
1b6f4958 | 395 | static const struct intel_limit intel_limits_pineview_lvds = { |
0206e353 AJ |
396 | .dot = { .min = 20000, .max = 400000 }, |
397 | .vco = { .min = 1700000, .max = 3500000 }, | |
398 | .n = { .min = 3, .max = 6 }, | |
399 | .m = { .min = 2, .max = 256 }, | |
400 | .m1 = { .min = 0, .max = 0 }, | |
401 | .m2 = { .min = 0, .max = 254 }, | |
402 | .p = { .min = 7, .max = 112 }, | |
403 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
404 | .p2 = { .dot_limit = 112000, |
405 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
406 | }; |
407 | ||
273e27ca EA |
408 | /* Ironlake / Sandybridge |
409 | * | |
410 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
411 | * the range value for them is (actual_value - 2). | |
412 | */ | |
1b6f4958 | 413 | static const struct intel_limit intel_limits_ironlake_dac = { |
273e27ca EA |
414 | .dot = { .min = 25000, .max = 350000 }, |
415 | .vco = { .min = 1760000, .max = 3510000 }, | |
416 | .n = { .min = 1, .max = 5 }, | |
417 | .m = { .min = 79, .max = 127 }, | |
418 | .m1 = { .min = 12, .max = 22 }, | |
419 | .m2 = { .min = 5, .max = 9 }, | |
420 | .p = { .min = 5, .max = 80 }, | |
421 | .p1 = { .min = 1, .max = 8 }, | |
422 | .p2 = { .dot_limit = 225000, | |
423 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
424 | }; |
425 | ||
1b6f4958 | 426 | static const struct intel_limit intel_limits_ironlake_single_lvds = { |
273e27ca EA |
427 | .dot = { .min = 25000, .max = 350000 }, |
428 | .vco = { .min = 1760000, .max = 3510000 }, | |
429 | .n = { .min = 1, .max = 3 }, | |
430 | .m = { .min = 79, .max = 118 }, | |
431 | .m1 = { .min = 12, .max = 22 }, | |
432 | .m2 = { .min = 5, .max = 9 }, | |
433 | .p = { .min = 28, .max = 112 }, | |
434 | .p1 = { .min = 2, .max = 8 }, | |
435 | .p2 = { .dot_limit = 225000, | |
436 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
437 | }; |
438 | ||
1b6f4958 | 439 | static const struct intel_limit intel_limits_ironlake_dual_lvds = { |
273e27ca EA |
440 | .dot = { .min = 25000, .max = 350000 }, |
441 | .vco = { .min = 1760000, .max = 3510000 }, | |
442 | .n = { .min = 1, .max = 3 }, | |
443 | .m = { .min = 79, .max = 127 }, | |
444 | .m1 = { .min = 12, .max = 22 }, | |
445 | .m2 = { .min = 5, .max = 9 }, | |
446 | .p = { .min = 14, .max = 56 }, | |
447 | .p1 = { .min = 2, .max = 8 }, | |
448 | .p2 = { .dot_limit = 225000, | |
449 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
450 | }; |
451 | ||
273e27ca | 452 | /* LVDS 100mhz refclk limits. */ |
1b6f4958 | 453 | static const struct intel_limit intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
454 | .dot = { .min = 25000, .max = 350000 }, |
455 | .vco = { .min = 1760000, .max = 3510000 }, | |
456 | .n = { .min = 1, .max = 2 }, | |
457 | .m = { .min = 79, .max = 126 }, | |
458 | .m1 = { .min = 12, .max = 22 }, | |
459 | .m2 = { .min = 5, .max = 9 }, | |
460 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 461 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
462 | .p2 = { .dot_limit = 225000, |
463 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
464 | }; |
465 | ||
1b6f4958 | 466 | static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = { |
273e27ca EA |
467 | .dot = { .min = 25000, .max = 350000 }, |
468 | .vco = { .min = 1760000, .max = 3510000 }, | |
469 | .n = { .min = 1, .max = 3 }, | |
470 | .m = { .min = 79, .max = 126 }, | |
471 | .m1 = { .min = 12, .max = 22 }, | |
472 | .m2 = { .min = 5, .max = 9 }, | |
473 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 474 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
475 | .p2 = { .dot_limit = 225000, |
476 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
477 | }; |
478 | ||
1b6f4958 | 479 | static const struct intel_limit intel_limits_vlv = { |
f01b7962 VS |
480 | /* |
481 | * These are the data rate limits (measured in fast clocks) | |
482 | * since those are the strictest limits we have. The fast | |
483 | * clock and actual rate limits are more relaxed, so checking | |
484 | * them would make no difference. | |
485 | */ | |
486 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 487 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 488 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
489 | .m1 = { .min = 2, .max = 3 }, |
490 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 491 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 492 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
493 | }; |
494 | ||
1b6f4958 | 495 | static const struct intel_limit intel_limits_chv = { |
ef9348c8 CML |
496 | /* |
497 | * These are the data rate limits (measured in fast clocks) | |
498 | * since those are the strictest limits we have. The fast | |
499 | * clock and actual rate limits are more relaxed, so checking | |
500 | * them would make no difference. | |
501 | */ | |
502 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 503 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
504 | .n = { .min = 1, .max = 1 }, |
505 | .m1 = { .min = 2, .max = 2 }, | |
506 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
507 | .p1 = { .min = 2, .max = 4 }, | |
508 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
509 | }; | |
510 | ||
1b6f4958 | 511 | static const struct intel_limit intel_limits_bxt = { |
5ab7b0b7 ID |
512 | /* FIXME: find real dot limits */ |
513 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 514 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
515 | .n = { .min = 1, .max = 1 }, |
516 | .m1 = { .min = 2, .max = 2 }, | |
517 | /* FIXME: find real m2 limits */ | |
518 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
519 | .p1 = { .min = 2, .max = 4 }, | |
520 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
521 | }; | |
522 | ||
cdba954e ACO |
523 | static bool |
524 | needs_modeset(struct drm_crtc_state *state) | |
525 | { | |
fc596660 | 526 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
527 | } |
528 | ||
e0638cdf PZ |
529 | /** |
530 | * Returns whether any output on the specified pipe is of the specified type | |
531 | */ | |
4093561b | 532 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) |
e0638cdf | 533 | { |
409ee761 | 534 | struct drm_device *dev = crtc->base.dev; |
e0638cdf PZ |
535 | struct intel_encoder *encoder; |
536 | ||
409ee761 | 537 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
e0638cdf PZ |
538 | if (encoder->type == type) |
539 | return true; | |
540 | ||
541 | return false; | |
542 | } | |
543 | ||
d0737e1d ACO |
544 | /** |
545 | * Returns whether any output on the specified pipe will have the specified | |
546 | * type after a staged modeset is complete, i.e., the same as | |
547 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of | |
548 | * encoder->crtc. | |
549 | */ | |
a93e255f ACO |
550 | static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state, |
551 | int type) | |
d0737e1d | 552 | { |
a93e255f | 553 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 554 | struct drm_connector *connector; |
a93e255f | 555 | struct drm_connector_state *connector_state; |
d0737e1d | 556 | struct intel_encoder *encoder; |
a93e255f ACO |
557 | int i, num_connectors = 0; |
558 | ||
da3ced29 | 559 | for_each_connector_in_state(state, connector, connector_state, i) { |
a93e255f ACO |
560 | if (connector_state->crtc != crtc_state->base.crtc) |
561 | continue; | |
562 | ||
563 | num_connectors++; | |
d0737e1d | 564 | |
a93e255f ACO |
565 | encoder = to_intel_encoder(connector_state->best_encoder); |
566 | if (encoder->type == type) | |
d0737e1d | 567 | return true; |
a93e255f ACO |
568 | } |
569 | ||
570 | WARN_ON(num_connectors == 0); | |
d0737e1d ACO |
571 | |
572 | return false; | |
573 | } | |
574 | ||
dccbea3b ID |
575 | /* |
576 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
577 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
578 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
579 | * The helpers' return value is the rate of the clock that is fed to the | |
580 | * display engine's pipe which can be the above fast dot clock rate or a | |
581 | * divided-down version of it. | |
582 | */ | |
f2b115e6 | 583 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
9e2c8475 | 584 | static int pnv_calc_dpll_params(int refclk, struct dpll *clock) |
79e53945 | 585 | { |
2177832f SL |
586 | clock->m = clock->m2 + 2; |
587 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 588 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 589 | return 0; |
fb03ac01 VS |
590 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
591 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
592 | |
593 | return clock->dot; | |
2177832f SL |
594 | } |
595 | ||
7429e9d4 DV |
596 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
597 | { | |
598 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
599 | } | |
600 | ||
9e2c8475 | 601 | static int i9xx_calc_dpll_params(int refclk, struct dpll *clock) |
2177832f | 602 | { |
7429e9d4 | 603 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 604 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 605 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 606 | return 0; |
fb03ac01 VS |
607 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
608 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
609 | |
610 | return clock->dot; | |
79e53945 JB |
611 | } |
612 | ||
9e2c8475 | 613 | static int vlv_calc_dpll_params(int refclk, struct dpll *clock) |
589eca67 ID |
614 | { |
615 | clock->m = clock->m1 * clock->m2; | |
616 | clock->p = clock->p1 * clock->p2; | |
617 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 618 | return 0; |
589eca67 ID |
619 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
620 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
621 | |
622 | return clock->dot / 5; | |
589eca67 ID |
623 | } |
624 | ||
9e2c8475 | 625 | int chv_calc_dpll_params(int refclk, struct dpll *clock) |
ef9348c8 CML |
626 | { |
627 | clock->m = clock->m1 * clock->m2; | |
628 | clock->p = clock->p1 * clock->p2; | |
629 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 630 | return 0; |
ef9348c8 CML |
631 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
632 | clock->n << 22); | |
633 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
634 | |
635 | return clock->dot / 5; | |
ef9348c8 CML |
636 | } |
637 | ||
7c04d1d9 | 638 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
639 | /** |
640 | * Returns whether the given set of divisors are valid for a given refclk with | |
641 | * the given connectors. | |
642 | */ | |
643 | ||
1b894b59 | 644 | static bool intel_PLL_is_valid(struct drm_device *dev, |
1b6f4958 | 645 | const struct intel_limit *limit, |
9e2c8475 | 646 | const struct dpll *clock) |
79e53945 | 647 | { |
f01b7962 VS |
648 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
649 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 650 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 651 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 652 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 653 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 654 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 655 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 656 | |
666a4537 WB |
657 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && |
658 | !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) | |
f01b7962 VS |
659 | if (clock->m1 <= clock->m2) |
660 | INTELPllInvalid("m1 <= m2\n"); | |
661 | ||
666a4537 | 662 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) { |
f01b7962 VS |
663 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
664 | INTELPllInvalid("p out of range\n"); | |
665 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
666 | INTELPllInvalid("m out of range\n"); | |
667 | } | |
668 | ||
79e53945 | 669 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 670 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
671 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
672 | * connector, etc., rather than just a single range. | |
673 | */ | |
674 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 675 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
676 | |
677 | return true; | |
678 | } | |
679 | ||
3b1429d9 | 680 | static int |
1b6f4958 | 681 | i9xx_select_p2_div(const struct intel_limit *limit, |
3b1429d9 VS |
682 | const struct intel_crtc_state *crtc_state, |
683 | int target) | |
79e53945 | 684 | { |
3b1429d9 | 685 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 686 | |
a93e255f | 687 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 688 | /* |
a210b028 DV |
689 | * For LVDS just rely on its current settings for dual-channel. |
690 | * We haven't figured out how to reliably set up different | |
691 | * single/dual channel state, if we even can. | |
79e53945 | 692 | */ |
1974cad0 | 693 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 694 | return limit->p2.p2_fast; |
79e53945 | 695 | else |
3b1429d9 | 696 | return limit->p2.p2_slow; |
79e53945 JB |
697 | } else { |
698 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 699 | return limit->p2.p2_slow; |
79e53945 | 700 | else |
3b1429d9 | 701 | return limit->p2.p2_fast; |
79e53945 | 702 | } |
3b1429d9 VS |
703 | } |
704 | ||
70e8aa21 ACO |
705 | /* |
706 | * Returns a set of divisors for the desired target clock with the given | |
707 | * refclk, or FALSE. The returned values represent the clock equation: | |
708 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
709 | * | |
710 | * Target and reference clocks are specified in kHz. | |
711 | * | |
712 | * If match_clock is provided, then best_clock P divider must match the P | |
713 | * divider from @match_clock used for LVDS downclocking. | |
714 | */ | |
3b1429d9 | 715 | static bool |
1b6f4958 | 716 | i9xx_find_best_dpll(const struct intel_limit *limit, |
3b1429d9 | 717 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
718 | int target, int refclk, struct dpll *match_clock, |
719 | struct dpll *best_clock) | |
3b1429d9 VS |
720 | { |
721 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
9e2c8475 | 722 | struct dpll clock; |
3b1429d9 | 723 | int err = target; |
79e53945 | 724 | |
0206e353 | 725 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 726 | |
3b1429d9 VS |
727 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
728 | ||
42158660 ZY |
729 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
730 | clock.m1++) { | |
731 | for (clock.m2 = limit->m2.min; | |
732 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 733 | if (clock.m2 >= clock.m1) |
42158660 ZY |
734 | break; |
735 | for (clock.n = limit->n.min; | |
736 | clock.n <= limit->n.max; clock.n++) { | |
737 | for (clock.p1 = limit->p1.min; | |
738 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
739 | int this_err; |
740 | ||
dccbea3b | 741 | i9xx_calc_dpll_params(refclk, &clock); |
ac58c3f0 DV |
742 | if (!intel_PLL_is_valid(dev, limit, |
743 | &clock)) | |
744 | continue; | |
745 | if (match_clock && | |
746 | clock.p != match_clock->p) | |
747 | continue; | |
748 | ||
749 | this_err = abs(clock.dot - target); | |
750 | if (this_err < err) { | |
751 | *best_clock = clock; | |
752 | err = this_err; | |
753 | } | |
754 | } | |
755 | } | |
756 | } | |
757 | } | |
758 | ||
759 | return (err != target); | |
760 | } | |
761 | ||
70e8aa21 ACO |
762 | /* |
763 | * Returns a set of divisors for the desired target clock with the given | |
764 | * refclk, or FALSE. The returned values represent the clock equation: | |
765 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
766 | * | |
767 | * Target and reference clocks are specified in kHz. | |
768 | * | |
769 | * If match_clock is provided, then best_clock P divider must match the P | |
770 | * divider from @match_clock used for LVDS downclocking. | |
771 | */ | |
ac58c3f0 | 772 | static bool |
1b6f4958 | 773 | pnv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 774 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
775 | int target, int refclk, struct dpll *match_clock, |
776 | struct dpll *best_clock) | |
79e53945 | 777 | { |
3b1429d9 | 778 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 779 | struct dpll clock; |
79e53945 JB |
780 | int err = target; |
781 | ||
0206e353 | 782 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 783 | |
3b1429d9 VS |
784 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
785 | ||
42158660 ZY |
786 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
787 | clock.m1++) { | |
788 | for (clock.m2 = limit->m2.min; | |
789 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
790 | for (clock.n = limit->n.min; |
791 | clock.n <= limit->n.max; clock.n++) { | |
792 | for (clock.p1 = limit->p1.min; | |
793 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
794 | int this_err; |
795 | ||
dccbea3b | 796 | pnv_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
797 | if (!intel_PLL_is_valid(dev, limit, |
798 | &clock)) | |
79e53945 | 799 | continue; |
cec2f356 SP |
800 | if (match_clock && |
801 | clock.p != match_clock->p) | |
802 | continue; | |
79e53945 JB |
803 | |
804 | this_err = abs(clock.dot - target); | |
805 | if (this_err < err) { | |
806 | *best_clock = clock; | |
807 | err = this_err; | |
808 | } | |
809 | } | |
810 | } | |
811 | } | |
812 | } | |
813 | ||
814 | return (err != target); | |
815 | } | |
816 | ||
997c030c ACO |
817 | /* |
818 | * Returns a set of divisors for the desired target clock with the given | |
819 | * refclk, or FALSE. The returned values represent the clock equation: | |
820 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
70e8aa21 ACO |
821 | * |
822 | * Target and reference clocks are specified in kHz. | |
823 | * | |
824 | * If match_clock is provided, then best_clock P divider must match the P | |
825 | * divider from @match_clock used for LVDS downclocking. | |
997c030c | 826 | */ |
d4906093 | 827 | static bool |
1b6f4958 | 828 | g4x_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 829 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
830 | int target, int refclk, struct dpll *match_clock, |
831 | struct dpll *best_clock) | |
d4906093 | 832 | { |
3b1429d9 | 833 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 834 | struct dpll clock; |
d4906093 | 835 | int max_n; |
3b1429d9 | 836 | bool found = false; |
6ba770dc AJ |
837 | /* approximately equals target * 0.00585 */ |
838 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
839 | |
840 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
841 | |
842 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
843 | ||
d4906093 | 844 | max_n = limit->n.max; |
f77f13e2 | 845 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 846 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 847 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
848 | for (clock.m1 = limit->m1.max; |
849 | clock.m1 >= limit->m1.min; clock.m1--) { | |
850 | for (clock.m2 = limit->m2.max; | |
851 | clock.m2 >= limit->m2.min; clock.m2--) { | |
852 | for (clock.p1 = limit->p1.max; | |
853 | clock.p1 >= limit->p1.min; clock.p1--) { | |
854 | int this_err; | |
855 | ||
dccbea3b | 856 | i9xx_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
857 | if (!intel_PLL_is_valid(dev, limit, |
858 | &clock)) | |
d4906093 | 859 | continue; |
1b894b59 CW |
860 | |
861 | this_err = abs(clock.dot - target); | |
d4906093 ML |
862 | if (this_err < err_most) { |
863 | *best_clock = clock; | |
864 | err_most = this_err; | |
865 | max_n = clock.n; | |
866 | found = true; | |
867 | } | |
868 | } | |
869 | } | |
870 | } | |
871 | } | |
2c07245f ZW |
872 | return found; |
873 | } | |
874 | ||
d5dd62bd ID |
875 | /* |
876 | * Check if the calculated PLL configuration is more optimal compared to the | |
877 | * best configuration and error found so far. Return the calculated error. | |
878 | */ | |
879 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
9e2c8475 ACO |
880 | const struct dpll *calculated_clock, |
881 | const struct dpll *best_clock, | |
d5dd62bd ID |
882 | unsigned int best_error_ppm, |
883 | unsigned int *error_ppm) | |
884 | { | |
9ca3ba01 ID |
885 | /* |
886 | * For CHV ignore the error and consider only the P value. | |
887 | * Prefer a bigger P value based on HW requirements. | |
888 | */ | |
889 | if (IS_CHERRYVIEW(dev)) { | |
890 | *error_ppm = 0; | |
891 | ||
892 | return calculated_clock->p > best_clock->p; | |
893 | } | |
894 | ||
24be4e46 ID |
895 | if (WARN_ON_ONCE(!target_freq)) |
896 | return false; | |
897 | ||
d5dd62bd ID |
898 | *error_ppm = div_u64(1000000ULL * |
899 | abs(target_freq - calculated_clock->dot), | |
900 | target_freq); | |
901 | /* | |
902 | * Prefer a better P value over a better (smaller) error if the error | |
903 | * is small. Ensure this preference for future configurations too by | |
904 | * setting the error to 0. | |
905 | */ | |
906 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
907 | *error_ppm = 0; | |
908 | ||
909 | return true; | |
910 | } | |
911 | ||
912 | return *error_ppm + 10 < best_error_ppm; | |
913 | } | |
914 | ||
65b3d6a9 ACO |
915 | /* |
916 | * Returns a set of divisors for the desired target clock with the given | |
917 | * refclk, or FALSE. The returned values represent the clock equation: | |
918 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
919 | */ | |
a0c4da24 | 920 | static bool |
1b6f4958 | 921 | vlv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 922 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
923 | int target, int refclk, struct dpll *match_clock, |
924 | struct dpll *best_clock) | |
a0c4da24 | 925 | { |
a93e255f | 926 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 927 | struct drm_device *dev = crtc->base.dev; |
9e2c8475 | 928 | struct dpll clock; |
69e4f900 | 929 | unsigned int bestppm = 1000000; |
27e639bf VS |
930 | /* min update 19.2 MHz */ |
931 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 932 | bool found = false; |
a0c4da24 | 933 | |
6b4bf1c4 VS |
934 | target *= 5; /* fast clock */ |
935 | ||
936 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
937 | |
938 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 939 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 940 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 941 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 942 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 943 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 944 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 945 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 946 | unsigned int ppm; |
69e4f900 | 947 | |
6b4bf1c4 VS |
948 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
949 | refclk * clock.m1); | |
950 | ||
dccbea3b | 951 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 952 | |
f01b7962 VS |
953 | if (!intel_PLL_is_valid(dev, limit, |
954 | &clock)) | |
43b0ac53 VS |
955 | continue; |
956 | ||
d5dd62bd ID |
957 | if (!vlv_PLL_is_optimal(dev, target, |
958 | &clock, | |
959 | best_clock, | |
960 | bestppm, &ppm)) | |
961 | continue; | |
6b4bf1c4 | 962 | |
d5dd62bd ID |
963 | *best_clock = clock; |
964 | bestppm = ppm; | |
965 | found = true; | |
a0c4da24 JB |
966 | } |
967 | } | |
968 | } | |
969 | } | |
a0c4da24 | 970 | |
49e497ef | 971 | return found; |
a0c4da24 | 972 | } |
a4fc5ed6 | 973 | |
65b3d6a9 ACO |
974 | /* |
975 | * Returns a set of divisors for the desired target clock with the given | |
976 | * refclk, or FALSE. The returned values represent the clock equation: | |
977 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
978 | */ | |
ef9348c8 | 979 | static bool |
1b6f4958 | 980 | chv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 981 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
982 | int target, int refclk, struct dpll *match_clock, |
983 | struct dpll *best_clock) | |
ef9348c8 | 984 | { |
a93e255f | 985 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 986 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 987 | unsigned int best_error_ppm; |
9e2c8475 | 988 | struct dpll clock; |
ef9348c8 CML |
989 | uint64_t m2; |
990 | int found = false; | |
991 | ||
992 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 993 | best_error_ppm = 1000000; |
ef9348c8 CML |
994 | |
995 | /* | |
996 | * Based on hardware doc, the n always set to 1, and m1 always | |
997 | * set to 2. If requires to support 200Mhz refclk, we need to | |
998 | * revisit this because n may not 1 anymore. | |
999 | */ | |
1000 | clock.n = 1, clock.m1 = 2; | |
1001 | target *= 5; /* fast clock */ | |
1002 | ||
1003 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
1004 | for (clock.p2 = limit->p2.p2_fast; | |
1005 | clock.p2 >= limit->p2.p2_slow; | |
1006 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 1007 | unsigned int error_ppm; |
ef9348c8 CML |
1008 | |
1009 | clock.p = clock.p1 * clock.p2; | |
1010 | ||
1011 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
1012 | clock.n) << 22, refclk * clock.m1); | |
1013 | ||
1014 | if (m2 > INT_MAX/clock.m1) | |
1015 | continue; | |
1016 | ||
1017 | clock.m2 = m2; | |
1018 | ||
dccbea3b | 1019 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 CML |
1020 | |
1021 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
1022 | continue; | |
1023 | ||
9ca3ba01 ID |
1024 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
1025 | best_error_ppm, &error_ppm)) | |
1026 | continue; | |
1027 | ||
1028 | *best_clock = clock; | |
1029 | best_error_ppm = error_ppm; | |
1030 | found = true; | |
ef9348c8 CML |
1031 | } |
1032 | } | |
1033 | ||
1034 | return found; | |
1035 | } | |
1036 | ||
5ab7b0b7 | 1037 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
9e2c8475 | 1038 | struct dpll *best_clock) |
5ab7b0b7 | 1039 | { |
65b3d6a9 | 1040 | int refclk = 100000; |
1b6f4958 | 1041 | const struct intel_limit *limit = &intel_limits_bxt; |
5ab7b0b7 | 1042 | |
65b3d6a9 | 1043 | return chv_find_best_dpll(limit, crtc_state, |
5ab7b0b7 ID |
1044 | target_clock, refclk, NULL, best_clock); |
1045 | } | |
1046 | ||
20ddf665 VS |
1047 | bool intel_crtc_active(struct drm_crtc *crtc) |
1048 | { | |
1049 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1050 | ||
1051 | /* Be paranoid as we can arrive here with only partial | |
1052 | * state retrieved from the hardware during setup. | |
1053 | * | |
241bfc38 | 1054 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
1055 | * as Haswell has gained clock readout/fastboot support. |
1056 | * | |
66e514c1 | 1057 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 1058 | * properly reconstruct framebuffers. |
c3d1f436 MR |
1059 | * |
1060 | * FIXME: The intel_crtc->active here should be switched to | |
1061 | * crtc->state->active once we have proper CRTC states wired up | |
1062 | * for atomic. | |
20ddf665 | 1063 | */ |
c3d1f436 | 1064 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 1065 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
1066 | } |
1067 | ||
a5c961d1 PZ |
1068 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1069 | enum pipe pipe) | |
1070 | { | |
1071 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1072 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1073 | ||
6e3c9717 | 1074 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1075 | } |
1076 | ||
fbf49ea2 VS |
1077 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
1078 | { | |
1079 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1080 | i915_reg_t reg = PIPEDSL(pipe); |
fbf49ea2 VS |
1081 | u32 line1, line2; |
1082 | u32 line_mask; | |
1083 | ||
1084 | if (IS_GEN2(dev)) | |
1085 | line_mask = DSL_LINEMASK_GEN2; | |
1086 | else | |
1087 | line_mask = DSL_LINEMASK_GEN3; | |
1088 | ||
1089 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 1090 | msleep(5); |
fbf49ea2 VS |
1091 | line2 = I915_READ(reg) & line_mask; |
1092 | ||
1093 | return line1 == line2; | |
1094 | } | |
1095 | ||
ab7ad7f6 KP |
1096 | /* |
1097 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1098 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1099 | * |
1100 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1101 | * spinning on the vblank interrupt status bit, since we won't actually | |
1102 | * see an interrupt when the pipe is disabled. | |
1103 | * | |
ab7ad7f6 KP |
1104 | * On Gen4 and above: |
1105 | * wait for the pipe register state bit to turn off | |
1106 | * | |
1107 | * Otherwise: | |
1108 | * wait for the display line value to settle (it usually | |
1109 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1110 | * |
9d0498a2 | 1111 | */ |
575f7ab7 | 1112 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1113 | { |
575f7ab7 | 1114 | struct drm_device *dev = crtc->base.dev; |
9d0498a2 | 1115 | struct drm_i915_private *dev_priv = dev->dev_private; |
6e3c9717 | 1116 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1117 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
1118 | |
1119 | if (INTEL_INFO(dev)->gen >= 4) { | |
f0f59a00 | 1120 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1121 | |
1122 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
1123 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1124 | 100)) | |
284637d9 | 1125 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1126 | } else { |
ab7ad7f6 | 1127 | /* Wait for the display line to settle */ |
fbf49ea2 | 1128 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1129 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1130 | } |
79e53945 JB |
1131 | } |
1132 | ||
b24e7179 | 1133 | /* Only for pre-ILK configs */ |
55607e8a DV |
1134 | void assert_pll(struct drm_i915_private *dev_priv, |
1135 | enum pipe pipe, bool state) | |
b24e7179 | 1136 | { |
b24e7179 JB |
1137 | u32 val; |
1138 | bool cur_state; | |
1139 | ||
649636ef | 1140 | val = I915_READ(DPLL(pipe)); |
b24e7179 | 1141 | cur_state = !!(val & DPLL_VCO_ENABLE); |
e2c719b7 | 1142 | I915_STATE_WARN(cur_state != state, |
b24e7179 | 1143 | "PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1144 | onoff(state), onoff(cur_state)); |
b24e7179 | 1145 | } |
b24e7179 | 1146 | |
23538ef1 | 1147 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
8563b1e8 | 1148 | void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) |
23538ef1 JN |
1149 | { |
1150 | u32 val; | |
1151 | bool cur_state; | |
1152 | ||
a580516d | 1153 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1154 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1155 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1156 | |
1157 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1158 | I915_STATE_WARN(cur_state != state, |
23538ef1 | 1159 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1160 | onoff(state), onoff(cur_state)); |
23538ef1 | 1161 | } |
23538ef1 | 1162 | |
040484af JB |
1163 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
1164 | enum pipe pipe, bool state) | |
1165 | { | |
040484af | 1166 | bool cur_state; |
ad80a810 PZ |
1167 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1168 | pipe); | |
040484af | 1169 | |
2d1fe073 | 1170 | if (HAS_DDI(dev_priv)) { |
affa9354 | 1171 | /* DDI does not have a specific FDI_TX register */ |
649636ef | 1172 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
ad80a810 | 1173 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 | 1174 | } else { |
649636ef | 1175 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
bf507ef7 ED |
1176 | cur_state = !!(val & FDI_TX_ENABLE); |
1177 | } | |
e2c719b7 | 1178 | I915_STATE_WARN(cur_state != state, |
040484af | 1179 | "FDI TX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1180 | onoff(state), onoff(cur_state)); |
040484af JB |
1181 | } |
1182 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1183 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1184 | ||
1185 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1186 | enum pipe pipe, bool state) | |
1187 | { | |
040484af JB |
1188 | u32 val; |
1189 | bool cur_state; | |
1190 | ||
649636ef | 1191 | val = I915_READ(FDI_RX_CTL(pipe)); |
d63fa0dc | 1192 | cur_state = !!(val & FDI_RX_ENABLE); |
e2c719b7 | 1193 | I915_STATE_WARN(cur_state != state, |
040484af | 1194 | "FDI RX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1195 | onoff(state), onoff(cur_state)); |
040484af JB |
1196 | } |
1197 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1198 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1199 | ||
1200 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1201 | enum pipe pipe) | |
1202 | { | |
040484af JB |
1203 | u32 val; |
1204 | ||
1205 | /* ILK FDI PLL is always enabled */ | |
7e22dbbb | 1206 | if (IS_GEN5(dev_priv)) |
040484af JB |
1207 | return; |
1208 | ||
bf507ef7 | 1209 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
2d1fe073 | 1210 | if (HAS_DDI(dev_priv)) |
bf507ef7 ED |
1211 | return; |
1212 | ||
649636ef | 1213 | val = I915_READ(FDI_TX_CTL(pipe)); |
e2c719b7 | 1214 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1215 | } |
1216 | ||
55607e8a DV |
1217 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1218 | enum pipe pipe, bool state) | |
040484af | 1219 | { |
040484af | 1220 | u32 val; |
55607e8a | 1221 | bool cur_state; |
040484af | 1222 | |
649636ef | 1223 | val = I915_READ(FDI_RX_CTL(pipe)); |
55607e8a | 1224 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1225 | I915_STATE_WARN(cur_state != state, |
55607e8a | 1226 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
87ad3212 | 1227 | onoff(state), onoff(cur_state)); |
040484af JB |
1228 | } |
1229 | ||
b680c37a DV |
1230 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1231 | enum pipe pipe) | |
ea0760cf | 1232 | { |
bedd4dba | 1233 | struct drm_device *dev = dev_priv->dev; |
f0f59a00 | 1234 | i915_reg_t pp_reg; |
ea0760cf JB |
1235 | u32 val; |
1236 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1237 | bool locked = true; |
ea0760cf | 1238 | |
bedd4dba JN |
1239 | if (WARN_ON(HAS_DDI(dev))) |
1240 | return; | |
1241 | ||
1242 | if (HAS_PCH_SPLIT(dev)) { | |
1243 | u32 port_sel; | |
1244 | ||
ea0760cf | 1245 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1246 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1247 | ||
1248 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1249 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1250 | panel_pipe = PIPE_B; | |
1251 | /* XXX: else fix for eDP */ | |
666a4537 | 1252 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
bedd4dba JN |
1253 | /* presumably write lock depends on pipe, not port select */ |
1254 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1255 | panel_pipe = pipe; | |
ea0760cf JB |
1256 | } else { |
1257 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1258 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1259 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1260 | } |
1261 | ||
1262 | val = I915_READ(pp_reg); | |
1263 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1264 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1265 | locked = false; |
1266 | ||
e2c719b7 | 1267 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1268 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1269 | pipe_name(pipe)); |
ea0760cf JB |
1270 | } |
1271 | ||
93ce0ba6 JN |
1272 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1273 | enum pipe pipe, bool state) | |
1274 | { | |
1275 | struct drm_device *dev = dev_priv->dev; | |
1276 | bool cur_state; | |
1277 | ||
d9d82081 | 1278 | if (IS_845G(dev) || IS_I865G(dev)) |
0b87c24e | 1279 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
d9d82081 | 1280 | else |
5efb3e28 | 1281 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1282 | |
e2c719b7 | 1283 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 | 1284 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1285 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
93ce0ba6 JN |
1286 | } |
1287 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1288 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1289 | ||
b840d907 JB |
1290 | void assert_pipe(struct drm_i915_private *dev_priv, |
1291 | enum pipe pipe, bool state) | |
b24e7179 | 1292 | { |
63d7bbe9 | 1293 | bool cur_state; |
702e7a56 PZ |
1294 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1295 | pipe); | |
4feed0eb | 1296 | enum intel_display_power_domain power_domain; |
b24e7179 | 1297 | |
b6b5d049 VS |
1298 | /* if we need the pipe quirk it must be always on */ |
1299 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1300 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1301 | state = true; |
1302 | ||
4feed0eb ID |
1303 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); |
1304 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
649636ef | 1305 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
69310161 | 1306 | cur_state = !!(val & PIPECONF_ENABLE); |
4feed0eb ID |
1307 | |
1308 | intel_display_power_put(dev_priv, power_domain); | |
1309 | } else { | |
1310 | cur_state = false; | |
69310161 PZ |
1311 | } |
1312 | ||
e2c719b7 | 1313 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1314 | "pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1315 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1316 | } |
1317 | ||
931872fc CW |
1318 | static void assert_plane(struct drm_i915_private *dev_priv, |
1319 | enum plane plane, bool state) | |
b24e7179 | 1320 | { |
b24e7179 | 1321 | u32 val; |
931872fc | 1322 | bool cur_state; |
b24e7179 | 1323 | |
649636ef | 1324 | val = I915_READ(DSPCNTR(plane)); |
931872fc | 1325 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1326 | I915_STATE_WARN(cur_state != state, |
931872fc | 1327 | "plane %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1328 | plane_name(plane), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1329 | } |
1330 | ||
931872fc CW |
1331 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1332 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1333 | ||
b24e7179 JB |
1334 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1335 | enum pipe pipe) | |
1336 | { | |
653e1026 | 1337 | struct drm_device *dev = dev_priv->dev; |
649636ef | 1338 | int i; |
b24e7179 | 1339 | |
653e1026 VS |
1340 | /* Primary planes are fixed to pipes on gen4+ */ |
1341 | if (INTEL_INFO(dev)->gen >= 4) { | |
649636ef | 1342 | u32 val = I915_READ(DSPCNTR(pipe)); |
e2c719b7 | 1343 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1344 | "plane %c assertion failure, should be disabled but not\n", |
1345 | plane_name(pipe)); | |
19ec1358 | 1346 | return; |
28c05794 | 1347 | } |
19ec1358 | 1348 | |
b24e7179 | 1349 | /* Need to check both planes against the pipe */ |
055e393f | 1350 | for_each_pipe(dev_priv, i) { |
649636ef VS |
1351 | u32 val = I915_READ(DSPCNTR(i)); |
1352 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
b24e7179 | 1353 | DISPPLANE_SEL_PIPE_SHIFT; |
e2c719b7 | 1354 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1355 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1356 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1357 | } |
1358 | } | |
1359 | ||
19332d7a JB |
1360 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1361 | enum pipe pipe) | |
1362 | { | |
20674eef | 1363 | struct drm_device *dev = dev_priv->dev; |
649636ef | 1364 | int sprite; |
19332d7a | 1365 | |
7feb8b88 | 1366 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1367 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1368 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1369 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1370 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1371 | sprite, pipe_name(pipe)); | |
1372 | } | |
666a4537 | 1373 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
3bdcfc0c | 1374 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1375 | u32 val = I915_READ(SPCNTR(pipe, sprite)); |
e2c719b7 | 1376 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1377 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1378 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1379 | } |
1380 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
649636ef | 1381 | u32 val = I915_READ(SPRCTL(pipe)); |
e2c719b7 | 1382 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1383 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1384 | plane_name(pipe), pipe_name(pipe)); |
1385 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
649636ef | 1386 | u32 val = I915_READ(DVSCNTR(pipe)); |
e2c719b7 | 1387 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1388 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1389 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1390 | } |
1391 | } | |
1392 | ||
08c71e5e VS |
1393 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1394 | { | |
e2c719b7 | 1395 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1396 | drm_crtc_vblank_put(crtc); |
1397 | } | |
1398 | ||
7abd4b35 ACO |
1399 | void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1400 | enum pipe pipe) | |
92f2584a | 1401 | { |
92f2584a JB |
1402 | u32 val; |
1403 | bool enabled; | |
1404 | ||
649636ef | 1405 | val = I915_READ(PCH_TRANSCONF(pipe)); |
92f2584a | 1406 | enabled = !!(val & TRANS_ENABLE); |
e2c719b7 | 1407 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1408 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1409 | pipe_name(pipe)); | |
92f2584a JB |
1410 | } |
1411 | ||
4e634389 KP |
1412 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1413 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1414 | { |
1415 | if ((val & DP_PORT_EN) == 0) | |
1416 | return false; | |
1417 | ||
2d1fe073 | 1418 | if (HAS_PCH_CPT(dev_priv)) { |
f0f59a00 | 1419 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
f0575e92 KP |
1420 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1421 | return false; | |
2d1fe073 | 1422 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1423 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) |
1424 | return false; | |
f0575e92 KP |
1425 | } else { |
1426 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1427 | return false; | |
1428 | } | |
1429 | return true; | |
1430 | } | |
1431 | ||
1519b995 KP |
1432 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1433 | enum pipe pipe, u32 val) | |
1434 | { | |
dc0fa718 | 1435 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1436 | return false; |
1437 | ||
2d1fe073 | 1438 | if (HAS_PCH_CPT(dev_priv)) { |
dc0fa718 | 1439 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1440 | return false; |
2d1fe073 | 1441 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1442 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) |
1443 | return false; | |
1519b995 | 1444 | } else { |
dc0fa718 | 1445 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1446 | return false; |
1447 | } | |
1448 | return true; | |
1449 | } | |
1450 | ||
1451 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1452 | enum pipe pipe, u32 val) | |
1453 | { | |
1454 | if ((val & LVDS_PORT_EN) == 0) | |
1455 | return false; | |
1456 | ||
2d1fe073 | 1457 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1458 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1459 | return false; | |
1460 | } else { | |
1461 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1462 | return false; | |
1463 | } | |
1464 | return true; | |
1465 | } | |
1466 | ||
1467 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1468 | enum pipe pipe, u32 val) | |
1469 | { | |
1470 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1471 | return false; | |
2d1fe073 | 1472 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1473 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1474 | return false; | |
1475 | } else { | |
1476 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1477 | return false; | |
1478 | } | |
1479 | return true; | |
1480 | } | |
1481 | ||
291906f1 | 1482 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
1483 | enum pipe pipe, i915_reg_t reg, |
1484 | u32 port_sel) | |
291906f1 | 1485 | { |
47a05eca | 1486 | u32 val = I915_READ(reg); |
e2c719b7 | 1487 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1488 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1489 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1490 | |
2d1fe073 | 1491 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1492 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1493 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1494 | } |
1495 | ||
1496 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
f0f59a00 | 1497 | enum pipe pipe, i915_reg_t reg) |
291906f1 | 1498 | { |
47a05eca | 1499 | u32 val = I915_READ(reg); |
e2c719b7 | 1500 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1501 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1502 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1503 | |
2d1fe073 | 1504 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1505 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1506 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1507 | } |
1508 | ||
1509 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1510 | enum pipe pipe) | |
1511 | { | |
291906f1 | 1512 | u32 val; |
291906f1 | 1513 | |
f0575e92 KP |
1514 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1515 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1516 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 | 1517 | |
649636ef | 1518 | val = I915_READ(PCH_ADPA); |
e2c719b7 | 1519 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1520 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1521 | pipe_name(pipe)); |
291906f1 | 1522 | |
649636ef | 1523 | val = I915_READ(PCH_LVDS); |
e2c719b7 | 1524 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1525 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1526 | pipe_name(pipe)); |
291906f1 | 1527 | |
e2debe91 PZ |
1528 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1529 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1530 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1531 | } |
1532 | ||
cd2d34d9 VS |
1533 | static void _vlv_enable_pll(struct intel_crtc *crtc, |
1534 | const struct intel_crtc_state *pipe_config) | |
1535 | { | |
1536 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1537 | enum pipe pipe = crtc->pipe; | |
1538 | ||
1539 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); | |
1540 | POSTING_READ(DPLL(pipe)); | |
1541 | udelay(150); | |
1542 | ||
1543 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1544 | DRM_ERROR("DPLL %d failed to lock\n", pipe); | |
1545 | } | |
1546 | ||
d288f65f | 1547 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1548 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1549 | { |
cd2d34d9 | 1550 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1551 | enum pipe pipe = crtc->pipe; |
87442f73 | 1552 | |
8bd3f301 | 1553 | assert_pipe_disabled(dev_priv, pipe); |
87442f73 | 1554 | |
87442f73 | 1555 | /* PLL is protected by panel, make sure we can write it */ |
7d1a83cb | 1556 | assert_panel_unlocked(dev_priv, pipe); |
87442f73 | 1557 | |
cd2d34d9 VS |
1558 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) |
1559 | _vlv_enable_pll(crtc, pipe_config); | |
426115cf | 1560 | |
8bd3f301 VS |
1561 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
1562 | POSTING_READ(DPLL_MD(pipe)); | |
87442f73 DV |
1563 | } |
1564 | ||
cd2d34d9 VS |
1565 | |
1566 | static void _chv_enable_pll(struct intel_crtc *crtc, | |
1567 | const struct intel_crtc_state *pipe_config) | |
9d556c99 | 1568 | { |
cd2d34d9 | 1569 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1570 | enum pipe pipe = crtc->pipe; |
9d556c99 | 1571 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9d556c99 CML |
1572 | u32 tmp; |
1573 | ||
a580516d | 1574 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1575 | |
1576 | /* Enable back the 10bit clock to display controller */ | |
1577 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1578 | tmp |= DPIO_DCLKP_EN; | |
1579 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1580 | ||
54433e91 VS |
1581 | mutex_unlock(&dev_priv->sb_lock); |
1582 | ||
9d556c99 CML |
1583 | /* |
1584 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1585 | */ | |
1586 | udelay(1); | |
1587 | ||
1588 | /* Enable PLL */ | |
d288f65f | 1589 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1590 | |
1591 | /* Check PLL is locked */ | |
a11b0703 | 1592 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 | 1593 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
cd2d34d9 VS |
1594 | } |
1595 | ||
1596 | static void chv_enable_pll(struct intel_crtc *crtc, | |
1597 | const struct intel_crtc_state *pipe_config) | |
1598 | { | |
1599 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1600 | enum pipe pipe = crtc->pipe; | |
1601 | ||
1602 | assert_pipe_disabled(dev_priv, pipe); | |
1603 | ||
1604 | /* PLL is protected by panel, make sure we can write it */ | |
1605 | assert_panel_unlocked(dev_priv, pipe); | |
1606 | ||
1607 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) | |
1608 | _chv_enable_pll(crtc, pipe_config); | |
9d556c99 | 1609 | |
c231775c VS |
1610 | if (pipe != PIPE_A) { |
1611 | /* | |
1612 | * WaPixelRepeatModeFixForC0:chv | |
1613 | * | |
1614 | * DPLLCMD is AWOL. Use chicken bits to propagate | |
1615 | * the value from DPLLBMD to either pipe B or C. | |
1616 | */ | |
1617 | I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C); | |
1618 | I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md); | |
1619 | I915_WRITE(CBR4_VLV, 0); | |
1620 | dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; | |
1621 | ||
1622 | /* | |
1623 | * DPLLB VGA mode also seems to cause problems. | |
1624 | * We should always have it disabled. | |
1625 | */ | |
1626 | WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); | |
1627 | } else { | |
1628 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); | |
1629 | POSTING_READ(DPLL_MD(pipe)); | |
1630 | } | |
9d556c99 CML |
1631 | } |
1632 | ||
1c4e0274 VS |
1633 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1634 | { | |
1635 | struct intel_crtc *crtc; | |
1636 | int count = 0; | |
1637 | ||
1638 | for_each_intel_crtc(dev, crtc) | |
3538b9df | 1639 | count += crtc->base.state->active && |
409ee761 | 1640 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
1c4e0274 VS |
1641 | |
1642 | return count; | |
1643 | } | |
1644 | ||
66e3d5c0 | 1645 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1646 | { |
66e3d5c0 DV |
1647 | struct drm_device *dev = crtc->base.dev; |
1648 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1649 | i915_reg_t reg = DPLL(crtc->pipe); |
6e3c9717 | 1650 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1651 | |
66e3d5c0 | 1652 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1653 | |
63d7bbe9 | 1654 | /* PLL is protected by panel, make sure we can write it */ |
66e3d5c0 DV |
1655 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1656 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1657 | |
1c4e0274 VS |
1658 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1659 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1660 | /* | |
1661 | * It appears to be important that we don't enable this | |
1662 | * for the current pipe before otherwise configuring the | |
1663 | * PLL. No idea how this should be handled if multiple | |
1664 | * DVO outputs are enabled simultaneosly. | |
1665 | */ | |
1666 | dpll |= DPLL_DVO_2X_MODE; | |
1667 | I915_WRITE(DPLL(!crtc->pipe), | |
1668 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1669 | } | |
66e3d5c0 | 1670 | |
c2b63374 VS |
1671 | /* |
1672 | * Apparently we need to have VGA mode enabled prior to changing | |
1673 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1674 | * dividers, even though the register value does change. | |
1675 | */ | |
1676 | I915_WRITE(reg, 0); | |
1677 | ||
8e7a65aa VS |
1678 | I915_WRITE(reg, dpll); |
1679 | ||
66e3d5c0 DV |
1680 | /* Wait for the clocks to stabilize. */ |
1681 | POSTING_READ(reg); | |
1682 | udelay(150); | |
1683 | ||
1684 | if (INTEL_INFO(dev)->gen >= 4) { | |
1685 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1686 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1687 | } else { |
1688 | /* The pixel multiplier can only be updated once the | |
1689 | * DPLL is enabled and the clocks are stable. | |
1690 | * | |
1691 | * So write it again. | |
1692 | */ | |
1693 | I915_WRITE(reg, dpll); | |
1694 | } | |
63d7bbe9 JB |
1695 | |
1696 | /* We do this three times for luck */ | |
66e3d5c0 | 1697 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1698 | POSTING_READ(reg); |
1699 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1700 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1701 | POSTING_READ(reg); |
1702 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1703 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1704 | POSTING_READ(reg); |
1705 | udelay(150); /* wait for warmup */ | |
1706 | } | |
1707 | ||
1708 | /** | |
50b44a44 | 1709 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1710 | * @dev_priv: i915 private structure |
1711 | * @pipe: pipe PLL to disable | |
1712 | * | |
1713 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1714 | * | |
1715 | * Note! This is for pre-ILK only. | |
1716 | */ | |
1c4e0274 | 1717 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1718 | { |
1c4e0274 VS |
1719 | struct drm_device *dev = crtc->base.dev; |
1720 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1721 | enum pipe pipe = crtc->pipe; | |
1722 | ||
1723 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1724 | if (IS_I830(dev) && | |
409ee761 | 1725 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
3538b9df | 1726 | !intel_num_dvo_pipes(dev)) { |
1c4e0274 VS |
1727 | I915_WRITE(DPLL(PIPE_B), |
1728 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1729 | I915_WRITE(DPLL(PIPE_A), | |
1730 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1731 | } | |
1732 | ||
b6b5d049 VS |
1733 | /* Don't disable pipe or pipe PLLs if needed */ |
1734 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1735 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1736 | return; |
1737 | ||
1738 | /* Make sure the pipe isn't still relying on us */ | |
1739 | assert_pipe_disabled(dev_priv, pipe); | |
1740 | ||
b8afb911 | 1741 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1742 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1743 | } |
1744 | ||
f6071166 JB |
1745 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1746 | { | |
b8afb911 | 1747 | u32 val; |
f6071166 JB |
1748 | |
1749 | /* Make sure the pipe isn't still relying on us */ | |
1750 | assert_pipe_disabled(dev_priv, pipe); | |
1751 | ||
03ed5cbf VS |
1752 | val = DPLL_INTEGRATED_REF_CLK_VLV | |
1753 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
1754 | if (pipe != PIPE_A) | |
1755 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1756 | ||
f6071166 JB |
1757 | I915_WRITE(DPLL(pipe), val); |
1758 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1759 | } |
1760 | ||
1761 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1762 | { | |
d752048d | 1763 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1764 | u32 val; |
1765 | ||
a11b0703 VS |
1766 | /* Make sure the pipe isn't still relying on us */ |
1767 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1768 | |
60bfe44f VS |
1769 | val = DPLL_SSC_REF_CLK_CHV | |
1770 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1771 | if (pipe != PIPE_A) |
1772 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
03ed5cbf | 1773 | |
a11b0703 VS |
1774 | I915_WRITE(DPLL(pipe), val); |
1775 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1776 | |
a580516d | 1777 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1778 | |
1779 | /* Disable 10bit clock to display controller */ | |
1780 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1781 | val &= ~DPIO_DCLKP_EN; | |
1782 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1783 | ||
a580516d | 1784 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1785 | } |
1786 | ||
e4607fcf | 1787 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1788 | struct intel_digital_port *dport, |
1789 | unsigned int expected_mask) | |
89b667f8 JB |
1790 | { |
1791 | u32 port_mask; | |
f0f59a00 | 1792 | i915_reg_t dpll_reg; |
89b667f8 | 1793 | |
e4607fcf CML |
1794 | switch (dport->port) { |
1795 | case PORT_B: | |
89b667f8 | 1796 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1797 | dpll_reg = DPLL(0); |
e4607fcf CML |
1798 | break; |
1799 | case PORT_C: | |
89b667f8 | 1800 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1801 | dpll_reg = DPLL(0); |
9b6de0a1 | 1802 | expected_mask <<= 4; |
00fc31b7 CML |
1803 | break; |
1804 | case PORT_D: | |
1805 | port_mask = DPLL_PORTD_READY_MASK; | |
1806 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1807 | break; |
1808 | default: | |
1809 | BUG(); | |
1810 | } | |
89b667f8 | 1811 | |
9b6de0a1 VS |
1812 | if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000)) |
1813 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", | |
1814 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1815 | } |
1816 | ||
b8a4f404 PZ |
1817 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1818 | enum pipe pipe) | |
040484af | 1819 | { |
23670b32 | 1820 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1821 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1822 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
f0f59a00 VS |
1823 | i915_reg_t reg; |
1824 | uint32_t val, pipeconf_val; | |
040484af | 1825 | |
040484af | 1826 | /* Make sure PCH DPLL is enabled */ |
8106ddbd | 1827 | assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll); |
040484af JB |
1828 | |
1829 | /* FDI must be feeding us bits for PCH ports */ | |
1830 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1831 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1832 | ||
23670b32 DV |
1833 | if (HAS_PCH_CPT(dev)) { |
1834 | /* Workaround: Set the timing override bit before enabling the | |
1835 | * pch transcoder. */ | |
1836 | reg = TRANS_CHICKEN2(pipe); | |
1837 | val = I915_READ(reg); | |
1838 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1839 | I915_WRITE(reg, val); | |
59c859d6 | 1840 | } |
23670b32 | 1841 | |
ab9412ba | 1842 | reg = PCH_TRANSCONF(pipe); |
040484af | 1843 | val = I915_READ(reg); |
5f7f726d | 1844 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c | 1845 | |
2d1fe073 | 1846 | if (HAS_PCH_IBX(dev_priv)) { |
e9bcff5c | 1847 | /* |
c5de7c6f VS |
1848 | * Make the BPC in transcoder be consistent with |
1849 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1850 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1851 | */ |
dfd07d72 | 1852 | val &= ~PIPECONF_BPC_MASK; |
c5de7c6f VS |
1853 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI)) |
1854 | val |= PIPECONF_8BPC; | |
1855 | else | |
1856 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1857 | } |
5f7f726d PZ |
1858 | |
1859 | val &= ~TRANS_INTERLACE_MASK; | |
1860 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
2d1fe073 | 1861 | if (HAS_PCH_IBX(dev_priv) && |
409ee761 | 1862 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
1863 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1864 | else | |
1865 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1866 | else |
1867 | val |= TRANS_PROGRESSIVE; | |
1868 | ||
040484af JB |
1869 | I915_WRITE(reg, val | TRANS_ENABLE); |
1870 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 1871 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1872 | } |
1873 | ||
8fb033d7 | 1874 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1875 | enum transcoder cpu_transcoder) |
040484af | 1876 | { |
8fb033d7 | 1877 | u32 val, pipeconf_val; |
8fb033d7 | 1878 | |
8fb033d7 | 1879 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1880 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1881 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1882 | |
223a6fdf | 1883 | /* Workaround: set timing override bit. */ |
36c0d0cf | 1884 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1885 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1886 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 1887 | |
25f3ef11 | 1888 | val = TRANS_ENABLE; |
937bb610 | 1889 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1890 | |
9a76b1c6 PZ |
1891 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1892 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1893 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1894 | else |
1895 | val |= TRANS_PROGRESSIVE; | |
1896 | ||
ab9412ba DV |
1897 | I915_WRITE(LPT_TRANSCONF, val); |
1898 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 1899 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1900 | } |
1901 | ||
b8a4f404 PZ |
1902 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1903 | enum pipe pipe) | |
040484af | 1904 | { |
23670b32 | 1905 | struct drm_device *dev = dev_priv->dev; |
f0f59a00 VS |
1906 | i915_reg_t reg; |
1907 | uint32_t val; | |
040484af JB |
1908 | |
1909 | /* FDI relies on the transcoder */ | |
1910 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1911 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1912 | ||
291906f1 JB |
1913 | /* Ports must be off as well */ |
1914 | assert_pch_ports_disabled(dev_priv, pipe); | |
1915 | ||
ab9412ba | 1916 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1917 | val = I915_READ(reg); |
1918 | val &= ~TRANS_ENABLE; | |
1919 | I915_WRITE(reg, val); | |
1920 | /* wait for PCH transcoder off, transcoder state */ | |
1921 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 1922 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 | 1923 | |
c465613b | 1924 | if (HAS_PCH_CPT(dev)) { |
23670b32 DV |
1925 | /* Workaround: Clear the timing override chicken bit again. */ |
1926 | reg = TRANS_CHICKEN2(pipe); | |
1927 | val = I915_READ(reg); | |
1928 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1929 | I915_WRITE(reg, val); | |
1930 | } | |
040484af JB |
1931 | } |
1932 | ||
ab4d966c | 1933 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1934 | { |
8fb033d7 PZ |
1935 | u32 val; |
1936 | ||
ab9412ba | 1937 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1938 | val &= ~TRANS_ENABLE; |
ab9412ba | 1939 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1940 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 1941 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 1942 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1943 | |
1944 | /* Workaround: clear timing override bit. */ | |
36c0d0cf | 1945 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1946 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1947 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
1948 | } |
1949 | ||
b24e7179 | 1950 | /** |
309cfea8 | 1951 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 1952 | * @crtc: crtc responsible for the pipe |
b24e7179 | 1953 | * |
0372264a | 1954 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 1955 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 1956 | */ |
e1fdc473 | 1957 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1958 | { |
0372264a PZ |
1959 | struct drm_device *dev = crtc->base.dev; |
1960 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1961 | enum pipe pipe = crtc->pipe; | |
1a70a728 | 1962 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
1a240d4d | 1963 | enum pipe pch_transcoder; |
f0f59a00 | 1964 | i915_reg_t reg; |
b24e7179 JB |
1965 | u32 val; |
1966 | ||
9e2ee2dd VS |
1967 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
1968 | ||
58c6eaa2 | 1969 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 1970 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
1971 | assert_sprites_disabled(dev_priv, pipe); |
1972 | ||
2d1fe073 | 1973 | if (HAS_PCH_LPT(dev_priv)) |
cc391bbb PZ |
1974 | pch_transcoder = TRANSCODER_A; |
1975 | else | |
1976 | pch_transcoder = pipe; | |
1977 | ||
b24e7179 JB |
1978 | /* |
1979 | * A pipe without a PLL won't actually be able to drive bits from | |
1980 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1981 | * need the check. | |
1982 | */ | |
2d1fe073 | 1983 | if (HAS_GMCH_DISPLAY(dev_priv)) |
a65347ba | 1984 | if (crtc->config->has_dsi_encoder) |
23538ef1 JN |
1985 | assert_dsi_pll_enabled(dev_priv); |
1986 | else | |
1987 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 1988 | else { |
6e3c9717 | 1989 | if (crtc->config->has_pch_encoder) { |
040484af | 1990 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 1991 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
1992 | assert_fdi_tx_pll_enabled(dev_priv, |
1993 | (enum pipe) cpu_transcoder); | |
040484af JB |
1994 | } |
1995 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1996 | } | |
b24e7179 | 1997 | |
702e7a56 | 1998 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1999 | val = I915_READ(reg); |
7ad25d48 | 2000 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
2001 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
2002 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 2003 | return; |
7ad25d48 | 2004 | } |
00d70b15 CW |
2005 | |
2006 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2007 | POSTING_READ(reg); |
b7792d8b VS |
2008 | |
2009 | /* | |
2010 | * Until the pipe starts DSL will read as 0, which would cause | |
2011 | * an apparent vblank timestamp jump, which messes up also the | |
2012 | * frame count when it's derived from the timestamps. So let's | |
2013 | * wait for the pipe to start properly before we call | |
2014 | * drm_crtc_vblank_on() | |
2015 | */ | |
2016 | if (dev->max_vblank_count == 0 && | |
2017 | wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50)) | |
2018 | DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe)); | |
b24e7179 JB |
2019 | } |
2020 | ||
2021 | /** | |
309cfea8 | 2022 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2023 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2024 | * |
575f7ab7 VS |
2025 | * Disable the pipe of @crtc, making sure that various hardware |
2026 | * specific requirements are met, if applicable, e.g. plane | |
2027 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2028 | * |
2029 | * Will wait until the pipe has shut down before returning. | |
2030 | */ | |
575f7ab7 | 2031 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2032 | { |
575f7ab7 | 2033 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
6e3c9717 | 2034 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2035 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 2036 | i915_reg_t reg; |
b24e7179 JB |
2037 | u32 val; |
2038 | ||
9e2ee2dd VS |
2039 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
2040 | ||
b24e7179 JB |
2041 | /* |
2042 | * Make sure planes won't keep trying to pump pixels to us, | |
2043 | * or we might hang the display. | |
2044 | */ | |
2045 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2046 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2047 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2048 | |
702e7a56 | 2049 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2050 | val = I915_READ(reg); |
00d70b15 CW |
2051 | if ((val & PIPECONF_ENABLE) == 0) |
2052 | return; | |
2053 | ||
67adc644 VS |
2054 | /* |
2055 | * Double wide has implications for planes | |
2056 | * so best keep it disabled when not needed. | |
2057 | */ | |
6e3c9717 | 2058 | if (crtc->config->double_wide) |
67adc644 VS |
2059 | val &= ~PIPECONF_DOUBLE_WIDE; |
2060 | ||
2061 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2062 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2063 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2064 | val &= ~PIPECONF_ENABLE; |
2065 | ||
2066 | I915_WRITE(reg, val); | |
2067 | if ((val & PIPECONF_ENABLE) == 0) | |
2068 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2069 | } |
2070 | ||
693db184 CW |
2071 | static bool need_vtd_wa(struct drm_device *dev) |
2072 | { | |
2073 | #ifdef CONFIG_INTEL_IOMMU | |
2074 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2075 | return true; | |
2076 | #endif | |
2077 | return false; | |
2078 | } | |
2079 | ||
832be82f VS |
2080 | static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) |
2081 | { | |
2082 | return IS_GEN2(dev_priv) ? 2048 : 4096; | |
2083 | } | |
2084 | ||
27ba3910 VS |
2085 | static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv, |
2086 | uint64_t fb_modifier, unsigned int cpp) | |
7b49f948 VS |
2087 | { |
2088 | switch (fb_modifier) { | |
2089 | case DRM_FORMAT_MOD_NONE: | |
2090 | return cpp; | |
2091 | case I915_FORMAT_MOD_X_TILED: | |
2092 | if (IS_GEN2(dev_priv)) | |
2093 | return 128; | |
2094 | else | |
2095 | return 512; | |
2096 | case I915_FORMAT_MOD_Y_TILED: | |
2097 | if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) | |
2098 | return 128; | |
2099 | else | |
2100 | return 512; | |
2101 | case I915_FORMAT_MOD_Yf_TILED: | |
2102 | switch (cpp) { | |
2103 | case 1: | |
2104 | return 64; | |
2105 | case 2: | |
2106 | case 4: | |
2107 | return 128; | |
2108 | case 8: | |
2109 | case 16: | |
2110 | return 256; | |
2111 | default: | |
2112 | MISSING_CASE(cpp); | |
2113 | return cpp; | |
2114 | } | |
2115 | break; | |
2116 | default: | |
2117 | MISSING_CASE(fb_modifier); | |
2118 | return cpp; | |
2119 | } | |
2120 | } | |
2121 | ||
832be82f VS |
2122 | unsigned int intel_tile_height(const struct drm_i915_private *dev_priv, |
2123 | uint64_t fb_modifier, unsigned int cpp) | |
a57ce0b2 | 2124 | { |
832be82f VS |
2125 | if (fb_modifier == DRM_FORMAT_MOD_NONE) |
2126 | return 1; | |
2127 | else | |
2128 | return intel_tile_size(dev_priv) / | |
27ba3910 | 2129 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
6761dd31 TU |
2130 | } |
2131 | ||
8d0deca8 VS |
2132 | /* Return the tile dimensions in pixel units */ |
2133 | static void intel_tile_dims(const struct drm_i915_private *dev_priv, | |
2134 | unsigned int *tile_width, | |
2135 | unsigned int *tile_height, | |
2136 | uint64_t fb_modifier, | |
2137 | unsigned int cpp) | |
2138 | { | |
2139 | unsigned int tile_width_bytes = | |
2140 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); | |
2141 | ||
2142 | *tile_width = tile_width_bytes / cpp; | |
2143 | *tile_height = intel_tile_size(dev_priv) / tile_width_bytes; | |
2144 | } | |
2145 | ||
6761dd31 TU |
2146 | unsigned int |
2147 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
832be82f | 2148 | uint32_t pixel_format, uint64_t fb_modifier) |
6761dd31 | 2149 | { |
832be82f VS |
2150 | unsigned int cpp = drm_format_plane_cpp(pixel_format, 0); |
2151 | unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp); | |
2152 | ||
2153 | return ALIGN(height, tile_height); | |
a57ce0b2 JB |
2154 | } |
2155 | ||
1663b9d6 VS |
2156 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) |
2157 | { | |
2158 | unsigned int size = 0; | |
2159 | int i; | |
2160 | ||
2161 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) | |
2162 | size += rot_info->plane[i].width * rot_info->plane[i].height; | |
2163 | ||
2164 | return size; | |
2165 | } | |
2166 | ||
75c82a53 | 2167 | static void |
3465c580 VS |
2168 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, |
2169 | const struct drm_framebuffer *fb, | |
2170 | unsigned int rotation) | |
f64b98cd | 2171 | { |
2d7a215f VS |
2172 | if (intel_rotation_90_or_270(rotation)) { |
2173 | *view = i915_ggtt_view_rotated; | |
2174 | view->params.rotated = to_intel_framebuffer(fb)->rot_info; | |
2175 | } else { | |
2176 | *view = i915_ggtt_view_normal; | |
2177 | } | |
2178 | } | |
50470bb0 | 2179 | |
2d7a215f VS |
2180 | static void |
2181 | intel_fill_fb_info(struct drm_i915_private *dev_priv, | |
2182 | struct drm_framebuffer *fb) | |
2183 | { | |
2184 | struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info; | |
2185 | unsigned int tile_size, tile_width, tile_height, cpp; | |
50470bb0 | 2186 | |
d9b3288e VS |
2187 | tile_size = intel_tile_size(dev_priv); |
2188 | ||
2189 | cpp = drm_format_plane_cpp(fb->pixel_format, 0); | |
8d0deca8 VS |
2190 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2191 | fb->modifier[0], cpp); | |
d9b3288e | 2192 | |
1663b9d6 VS |
2193 | info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp); |
2194 | info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height); | |
84fe03f7 | 2195 | |
89e3e142 | 2196 | if (info->pixel_format == DRM_FORMAT_NV12) { |
832be82f | 2197 | cpp = drm_format_plane_cpp(fb->pixel_format, 1); |
8d0deca8 VS |
2198 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2199 | fb->modifier[1], cpp); | |
d9b3288e | 2200 | |
2d7a215f | 2201 | info->uv_offset = fb->offsets[1]; |
1663b9d6 VS |
2202 | info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp); |
2203 | info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height); | |
89e3e142 | 2204 | } |
f64b98cd TU |
2205 | } |
2206 | ||
603525d7 | 2207 | static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) |
4e9a86b6 VS |
2208 | { |
2209 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2210 | return 256 * 1024; | |
985b8bb4 | 2211 | else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || |
666a4537 | 2212 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
4e9a86b6 VS |
2213 | return 128 * 1024; |
2214 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2215 | return 4 * 1024; | |
2216 | else | |
44c5905e | 2217 | return 0; |
4e9a86b6 VS |
2218 | } |
2219 | ||
603525d7 VS |
2220 | static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv, |
2221 | uint64_t fb_modifier) | |
2222 | { | |
2223 | switch (fb_modifier) { | |
2224 | case DRM_FORMAT_MOD_NONE: | |
2225 | return intel_linear_alignment(dev_priv); | |
2226 | case I915_FORMAT_MOD_X_TILED: | |
2227 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2228 | return 256 * 1024; | |
2229 | return 0; | |
2230 | case I915_FORMAT_MOD_Y_TILED: | |
2231 | case I915_FORMAT_MOD_Yf_TILED: | |
2232 | return 1 * 1024 * 1024; | |
2233 | default: | |
2234 | MISSING_CASE(fb_modifier); | |
2235 | return 0; | |
2236 | } | |
2237 | } | |
2238 | ||
127bd2ac | 2239 | int |
3465c580 VS |
2240 | intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, |
2241 | unsigned int rotation) | |
6b95a207 | 2242 | { |
850c4cdc | 2243 | struct drm_device *dev = fb->dev; |
ce453d81 | 2244 | struct drm_i915_private *dev_priv = dev->dev_private; |
850c4cdc | 2245 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2246 | struct i915_ggtt_view view; |
6b95a207 KH |
2247 | u32 alignment; |
2248 | int ret; | |
2249 | ||
ebcdd39e MR |
2250 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2251 | ||
603525d7 | 2252 | alignment = intel_surf_alignment(dev_priv, fb->modifier[0]); |
6b95a207 | 2253 | |
3465c580 | 2254 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2255 | |
693db184 CW |
2256 | /* Note that the w/a also requires 64 PTE of padding following the |
2257 | * bo. We currently fill all unused PTE with the shadow page and so | |
2258 | * we should always have valid PTE following the scanout preventing | |
2259 | * the VT-d warning. | |
2260 | */ | |
2261 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2262 | alignment = 256 * 1024; | |
2263 | ||
d6dd6843 PZ |
2264 | /* |
2265 | * Global gtt pte registers are special registers which actually forward | |
2266 | * writes to a chunk of system memory. Which means that there is no risk | |
2267 | * that the register values disappear as soon as we call | |
2268 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2269 | * pin/unpin/fence and not more. | |
2270 | */ | |
2271 | intel_runtime_pm_get(dev_priv); | |
2272 | ||
7580d774 ML |
2273 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, |
2274 | &view); | |
48b956c5 | 2275 | if (ret) |
b26a6b35 | 2276 | goto err_pm; |
6b95a207 KH |
2277 | |
2278 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2279 | * fence, whereas 965+ only requires a fence if using | |
2280 | * framebuffer compression. For simplicity, we always install | |
2281 | * a fence as the cost is not that onerous. | |
2282 | */ | |
9807216f VK |
2283 | if (view.type == I915_GGTT_VIEW_NORMAL) { |
2284 | ret = i915_gem_object_get_fence(obj); | |
2285 | if (ret == -EDEADLK) { | |
2286 | /* | |
2287 | * -EDEADLK means there are no free fences | |
2288 | * no pending flips. | |
2289 | * | |
2290 | * This is propagated to atomic, but it uses | |
2291 | * -EDEADLK to force a locking recovery, so | |
2292 | * change the returned error to -EBUSY. | |
2293 | */ | |
2294 | ret = -EBUSY; | |
2295 | goto err_unpin; | |
2296 | } else if (ret) | |
2297 | goto err_unpin; | |
1690e1eb | 2298 | |
9807216f VK |
2299 | i915_gem_object_pin_fence(obj); |
2300 | } | |
6b95a207 | 2301 | |
d6dd6843 | 2302 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2303 | return 0; |
48b956c5 CW |
2304 | |
2305 | err_unpin: | |
f64b98cd | 2306 | i915_gem_object_unpin_from_display_plane(obj, &view); |
b26a6b35 | 2307 | err_pm: |
d6dd6843 | 2308 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2309 | return ret; |
6b95a207 KH |
2310 | } |
2311 | ||
fb4b8ce1 | 2312 | void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) |
1690e1eb | 2313 | { |
82bc3b2d | 2314 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2315 | struct i915_ggtt_view view; |
82bc3b2d | 2316 | |
ebcdd39e MR |
2317 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2318 | ||
3465c580 | 2319 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2320 | |
9807216f VK |
2321 | if (view.type == I915_GGTT_VIEW_NORMAL) |
2322 | i915_gem_object_unpin_fence(obj); | |
2323 | ||
f64b98cd | 2324 | i915_gem_object_unpin_from_display_plane(obj, &view); |
1690e1eb CW |
2325 | } |
2326 | ||
29cf9491 VS |
2327 | /* |
2328 | * Adjust the tile offset by moving the difference into | |
2329 | * the x/y offsets. | |
2330 | * | |
2331 | * Input tile dimensions and pitch must already be | |
2332 | * rotated to match x and y, and in pixel units. | |
2333 | */ | |
2334 | static u32 intel_adjust_tile_offset(int *x, int *y, | |
2335 | unsigned int tile_width, | |
2336 | unsigned int tile_height, | |
2337 | unsigned int tile_size, | |
2338 | unsigned int pitch_tiles, | |
2339 | u32 old_offset, | |
2340 | u32 new_offset) | |
2341 | { | |
2342 | unsigned int tiles; | |
2343 | ||
2344 | WARN_ON(old_offset & (tile_size - 1)); | |
2345 | WARN_ON(new_offset & (tile_size - 1)); | |
2346 | WARN_ON(new_offset > old_offset); | |
2347 | ||
2348 | tiles = (old_offset - new_offset) / tile_size; | |
2349 | ||
2350 | *y += tiles / pitch_tiles * tile_height; | |
2351 | *x += tiles % pitch_tiles * tile_width; | |
2352 | ||
2353 | return new_offset; | |
2354 | } | |
2355 | ||
8d0deca8 VS |
2356 | /* |
2357 | * Computes the linear offset to the base tile and adjusts | |
2358 | * x, y. bytes per pixel is assumed to be a power-of-two. | |
2359 | * | |
2360 | * In the 90/270 rotated case, x and y are assumed | |
2361 | * to be already rotated to match the rotated GTT view, and | |
2362 | * pitch is the tile_height aligned framebuffer height. | |
2363 | */ | |
4f2d9934 VS |
2364 | u32 intel_compute_tile_offset(int *x, int *y, |
2365 | const struct drm_framebuffer *fb, int plane, | |
8d0deca8 VS |
2366 | unsigned int pitch, |
2367 | unsigned int rotation) | |
c2c75131 | 2368 | { |
4f2d9934 VS |
2369 | const struct drm_i915_private *dev_priv = to_i915(fb->dev); |
2370 | uint64_t fb_modifier = fb->modifier[plane]; | |
2371 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); | |
29cf9491 VS |
2372 | u32 offset, offset_aligned, alignment; |
2373 | ||
2374 | alignment = intel_surf_alignment(dev_priv, fb_modifier); | |
2375 | if (alignment) | |
2376 | alignment--; | |
2377 | ||
b5c65338 | 2378 | if (fb_modifier != DRM_FORMAT_MOD_NONE) { |
8d0deca8 VS |
2379 | unsigned int tile_size, tile_width, tile_height; |
2380 | unsigned int tile_rows, tiles, pitch_tiles; | |
c2c75131 | 2381 | |
d843310d | 2382 | tile_size = intel_tile_size(dev_priv); |
8d0deca8 VS |
2383 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2384 | fb_modifier, cpp); | |
2385 | ||
2386 | if (intel_rotation_90_or_270(rotation)) { | |
2387 | pitch_tiles = pitch / tile_height; | |
2388 | swap(tile_width, tile_height); | |
2389 | } else { | |
2390 | pitch_tiles = pitch / (tile_width * cpp); | |
2391 | } | |
d843310d VS |
2392 | |
2393 | tile_rows = *y / tile_height; | |
2394 | *y %= tile_height; | |
c2c75131 | 2395 | |
8d0deca8 VS |
2396 | tiles = *x / tile_width; |
2397 | *x %= tile_width; | |
bc752862 | 2398 | |
29cf9491 VS |
2399 | offset = (tile_rows * pitch_tiles + tiles) * tile_size; |
2400 | offset_aligned = offset & ~alignment; | |
bc752862 | 2401 | |
29cf9491 VS |
2402 | intel_adjust_tile_offset(x, y, tile_width, tile_height, |
2403 | tile_size, pitch_tiles, | |
2404 | offset, offset_aligned); | |
2405 | } else { | |
bc752862 | 2406 | offset = *y * pitch + *x * cpp; |
29cf9491 VS |
2407 | offset_aligned = offset & ~alignment; |
2408 | ||
4e9a86b6 VS |
2409 | *y = (offset & alignment) / pitch; |
2410 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
bc752862 | 2411 | } |
29cf9491 VS |
2412 | |
2413 | return offset_aligned; | |
c2c75131 DV |
2414 | } |
2415 | ||
b35d63fa | 2416 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2417 | { |
2418 | switch (format) { | |
2419 | case DISPPLANE_8BPP: | |
2420 | return DRM_FORMAT_C8; | |
2421 | case DISPPLANE_BGRX555: | |
2422 | return DRM_FORMAT_XRGB1555; | |
2423 | case DISPPLANE_BGRX565: | |
2424 | return DRM_FORMAT_RGB565; | |
2425 | default: | |
2426 | case DISPPLANE_BGRX888: | |
2427 | return DRM_FORMAT_XRGB8888; | |
2428 | case DISPPLANE_RGBX888: | |
2429 | return DRM_FORMAT_XBGR8888; | |
2430 | case DISPPLANE_BGRX101010: | |
2431 | return DRM_FORMAT_XRGB2101010; | |
2432 | case DISPPLANE_RGBX101010: | |
2433 | return DRM_FORMAT_XBGR2101010; | |
2434 | } | |
2435 | } | |
2436 | ||
bc8d7dff DL |
2437 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2438 | { | |
2439 | switch (format) { | |
2440 | case PLANE_CTL_FORMAT_RGB_565: | |
2441 | return DRM_FORMAT_RGB565; | |
2442 | default: | |
2443 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2444 | if (rgb_order) { | |
2445 | if (alpha) | |
2446 | return DRM_FORMAT_ABGR8888; | |
2447 | else | |
2448 | return DRM_FORMAT_XBGR8888; | |
2449 | } else { | |
2450 | if (alpha) | |
2451 | return DRM_FORMAT_ARGB8888; | |
2452 | else | |
2453 | return DRM_FORMAT_XRGB8888; | |
2454 | } | |
2455 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2456 | if (rgb_order) | |
2457 | return DRM_FORMAT_XBGR2101010; | |
2458 | else | |
2459 | return DRM_FORMAT_XRGB2101010; | |
2460 | } | |
2461 | } | |
2462 | ||
5724dbd1 | 2463 | static bool |
f6936e29 DV |
2464 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2465 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2466 | { |
2467 | struct drm_device *dev = crtc->base.dev; | |
3badb49f | 2468 | struct drm_i915_private *dev_priv = to_i915(dev); |
72e96d64 | 2469 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
46f297fb JB |
2470 | struct drm_i915_gem_object *obj = NULL; |
2471 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2472 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2473 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2474 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2475 | PAGE_SIZE); | |
2476 | ||
2477 | size_aligned -= base_aligned; | |
46f297fb | 2478 | |
ff2652ea CW |
2479 | if (plane_config->size == 0) |
2480 | return false; | |
2481 | ||
3badb49f PZ |
2482 | /* If the FB is too big, just don't use it since fbdev is not very |
2483 | * important and we should probably use that space with FBC or other | |
2484 | * features. */ | |
72e96d64 | 2485 | if (size_aligned * 2 > ggtt->stolen_usable_size) |
3badb49f PZ |
2486 | return false; |
2487 | ||
12c83d99 TU |
2488 | mutex_lock(&dev->struct_mutex); |
2489 | ||
f37b5c2b DV |
2490 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2491 | base_aligned, | |
2492 | base_aligned, | |
2493 | size_aligned); | |
12c83d99 TU |
2494 | if (!obj) { |
2495 | mutex_unlock(&dev->struct_mutex); | |
484b41dd | 2496 | return false; |
12c83d99 | 2497 | } |
46f297fb | 2498 | |
49af449b DL |
2499 | obj->tiling_mode = plane_config->tiling; |
2500 | if (obj->tiling_mode == I915_TILING_X) | |
6bf129df | 2501 | obj->stride = fb->pitches[0]; |
46f297fb | 2502 | |
6bf129df DL |
2503 | mode_cmd.pixel_format = fb->pixel_format; |
2504 | mode_cmd.width = fb->width; | |
2505 | mode_cmd.height = fb->height; | |
2506 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2507 | mode_cmd.modifier[0] = fb->modifier[0]; |
2508 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb | 2509 | |
6bf129df | 2510 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2511 | &mode_cmd, obj)) { |
46f297fb JB |
2512 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2513 | goto out_unref_obj; | |
2514 | } | |
12c83d99 | 2515 | |
46f297fb | 2516 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2517 | |
f6936e29 | 2518 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2519 | return true; |
46f297fb JB |
2520 | |
2521 | out_unref_obj: | |
2522 | drm_gem_object_unreference(&obj->base); | |
2523 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2524 | return false; |
2525 | } | |
2526 | ||
5724dbd1 | 2527 | static void |
f6936e29 DV |
2528 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2529 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2530 | { |
2531 | struct drm_device *dev = intel_crtc->base.dev; | |
d9ceb816 | 2532 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd JB |
2533 | struct drm_crtc *c; |
2534 | struct intel_crtc *i; | |
2ff8fde1 | 2535 | struct drm_i915_gem_object *obj; |
88595ac9 | 2536 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2537 | struct drm_plane_state *plane_state = primary->state; |
200757f5 MR |
2538 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
2539 | struct intel_plane *intel_plane = to_intel_plane(primary); | |
0a8d8a86 MR |
2540 | struct intel_plane_state *intel_state = |
2541 | to_intel_plane_state(plane_state); | |
88595ac9 | 2542 | struct drm_framebuffer *fb; |
484b41dd | 2543 | |
2d14030b | 2544 | if (!plane_config->fb) |
484b41dd JB |
2545 | return; |
2546 | ||
f6936e29 | 2547 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2548 | fb = &plane_config->fb->base; |
2549 | goto valid_fb; | |
f55548b5 | 2550 | } |
484b41dd | 2551 | |
2d14030b | 2552 | kfree(plane_config->fb); |
484b41dd JB |
2553 | |
2554 | /* | |
2555 | * Failed to alloc the obj, check to see if we should share | |
2556 | * an fb with another CRTC instead | |
2557 | */ | |
70e1e0ec | 2558 | for_each_crtc(dev, c) { |
484b41dd JB |
2559 | i = to_intel_crtc(c); |
2560 | ||
2561 | if (c == &intel_crtc->base) | |
2562 | continue; | |
2563 | ||
2ff8fde1 MR |
2564 | if (!i->active) |
2565 | continue; | |
2566 | ||
88595ac9 DV |
2567 | fb = c->primary->fb; |
2568 | if (!fb) | |
484b41dd JB |
2569 | continue; |
2570 | ||
88595ac9 | 2571 | obj = intel_fb_obj(fb); |
2ff8fde1 | 2572 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
88595ac9 DV |
2573 | drm_framebuffer_reference(fb); |
2574 | goto valid_fb; | |
484b41dd JB |
2575 | } |
2576 | } | |
88595ac9 | 2577 | |
200757f5 MR |
2578 | /* |
2579 | * We've failed to reconstruct the BIOS FB. Current display state | |
2580 | * indicates that the primary plane is visible, but has a NULL FB, | |
2581 | * which will lead to problems later if we don't fix it up. The | |
2582 | * simplest solution is to just disable the primary plane now and | |
2583 | * pretend the BIOS never had it enabled. | |
2584 | */ | |
2585 | to_intel_plane_state(plane_state)->visible = false; | |
2586 | crtc_state->plane_mask &= ~(1 << drm_plane_index(primary)); | |
2622a081 | 2587 | intel_pre_disable_primary_noatomic(&intel_crtc->base); |
200757f5 MR |
2588 | intel_plane->disable_plane(primary, &intel_crtc->base); |
2589 | ||
88595ac9 DV |
2590 | return; |
2591 | ||
2592 | valid_fb: | |
f44e2659 VS |
2593 | plane_state->src_x = 0; |
2594 | plane_state->src_y = 0; | |
be5651f2 ML |
2595 | plane_state->src_w = fb->width << 16; |
2596 | plane_state->src_h = fb->height << 16; | |
2597 | ||
f44e2659 VS |
2598 | plane_state->crtc_x = 0; |
2599 | plane_state->crtc_y = 0; | |
be5651f2 ML |
2600 | plane_state->crtc_w = fb->width; |
2601 | plane_state->crtc_h = fb->height; | |
2602 | ||
0a8d8a86 MR |
2603 | intel_state->src.x1 = plane_state->src_x; |
2604 | intel_state->src.y1 = plane_state->src_y; | |
2605 | intel_state->src.x2 = plane_state->src_x + plane_state->src_w; | |
2606 | intel_state->src.y2 = plane_state->src_y + plane_state->src_h; | |
2607 | intel_state->dst.x1 = plane_state->crtc_x; | |
2608 | intel_state->dst.y1 = plane_state->crtc_y; | |
2609 | intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w; | |
2610 | intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h; | |
2611 | ||
88595ac9 DV |
2612 | obj = intel_fb_obj(fb); |
2613 | if (obj->tiling_mode != I915_TILING_NONE) | |
2614 | dev_priv->preserve_bios_swizzle = true; | |
2615 | ||
be5651f2 ML |
2616 | drm_framebuffer_reference(fb); |
2617 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2618 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
36750f28 | 2619 | intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); |
a9ff8714 | 2620 | obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit; |
46f297fb JB |
2621 | } |
2622 | ||
a8d201af ML |
2623 | static void i9xx_update_primary_plane(struct drm_plane *primary, |
2624 | const struct intel_crtc_state *crtc_state, | |
2625 | const struct intel_plane_state *plane_state) | |
81255565 | 2626 | { |
a8d201af | 2627 | struct drm_device *dev = primary->dev; |
81255565 | 2628 | struct drm_i915_private *dev_priv = dev->dev_private; |
a8d201af ML |
2629 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
2630 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2631 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
81255565 | 2632 | int plane = intel_crtc->plane; |
54ea9da8 | 2633 | u32 linear_offset; |
81255565 | 2634 | u32 dspcntr; |
f0f59a00 | 2635 | i915_reg_t reg = DSPCNTR(plane); |
8d0deca8 | 2636 | unsigned int rotation = plane_state->base.rotation; |
ac484963 | 2637 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
54ea9da8 VS |
2638 | int x = plane_state->src.x1 >> 16; |
2639 | int y = plane_state->src.y1 >> 16; | |
c9ba6fad | 2640 | |
f45651ba VS |
2641 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2642 | ||
fdd508a6 | 2643 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2644 | |
2645 | if (INTEL_INFO(dev)->gen < 4) { | |
2646 | if (intel_crtc->pipe == PIPE_B) | |
2647 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2648 | ||
2649 | /* pipesrc and dspsize control the size that is scaled from, | |
2650 | * which should always be the user's requested size. | |
2651 | */ | |
2652 | I915_WRITE(DSPSIZE(plane), | |
a8d201af ML |
2653 | ((crtc_state->pipe_src_h - 1) << 16) | |
2654 | (crtc_state->pipe_src_w - 1)); | |
f45651ba | 2655 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
2656 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2657 | I915_WRITE(PRIMSIZE(plane), | |
a8d201af ML |
2658 | ((crtc_state->pipe_src_h - 1) << 16) | |
2659 | (crtc_state->pipe_src_w - 1)); | |
c14b0485 VS |
2660 | I915_WRITE(PRIMPOS(plane), 0); |
2661 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2662 | } |
81255565 | 2663 | |
57779d06 VS |
2664 | switch (fb->pixel_format) { |
2665 | case DRM_FORMAT_C8: | |
81255565 JB |
2666 | dspcntr |= DISPPLANE_8BPP; |
2667 | break; | |
57779d06 | 2668 | case DRM_FORMAT_XRGB1555: |
57779d06 | 2669 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 2670 | break; |
57779d06 VS |
2671 | case DRM_FORMAT_RGB565: |
2672 | dspcntr |= DISPPLANE_BGRX565; | |
2673 | break; | |
2674 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
2675 | dspcntr |= DISPPLANE_BGRX888; |
2676 | break; | |
2677 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2678 | dspcntr |= DISPPLANE_RGBX888; |
2679 | break; | |
2680 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2681 | dspcntr |= DISPPLANE_BGRX101010; |
2682 | break; | |
2683 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2684 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
2685 | break; |
2686 | default: | |
baba133a | 2687 | BUG(); |
81255565 | 2688 | } |
57779d06 | 2689 | |
f45651ba VS |
2690 | if (INTEL_INFO(dev)->gen >= 4 && |
2691 | obj->tiling_mode != I915_TILING_NONE) | |
2692 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2693 | |
de1aa629 VS |
2694 | if (IS_G4X(dev)) |
2695 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2696 | ||
ac484963 | 2697 | linear_offset = y * fb->pitches[0] + x * cpp; |
81255565 | 2698 | |
c2c75131 DV |
2699 | if (INTEL_INFO(dev)->gen >= 4) { |
2700 | intel_crtc->dspaddr_offset = | |
4f2d9934 | 2701 | intel_compute_tile_offset(&x, &y, fb, 0, |
8d0deca8 | 2702 | fb->pitches[0], rotation); |
c2c75131 DV |
2703 | linear_offset -= intel_crtc->dspaddr_offset; |
2704 | } else { | |
e506a0c6 | 2705 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2706 | } |
e506a0c6 | 2707 | |
8d0deca8 | 2708 | if (rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2709 | dspcntr |= DISPPLANE_ROTATE_180; |
2710 | ||
a8d201af ML |
2711 | x += (crtc_state->pipe_src_w - 1); |
2712 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
2713 | |
2714 | /* Finding the last pixel of the last line of the display | |
2715 | data and adding to linear_offset*/ | |
2716 | linear_offset += | |
a8d201af | 2717 | (crtc_state->pipe_src_h - 1) * fb->pitches[0] + |
ac484963 | 2718 | (crtc_state->pipe_src_w - 1) * cpp; |
48404c1e SJ |
2719 | } |
2720 | ||
2db3366b PZ |
2721 | intel_crtc->adjusted_x = x; |
2722 | intel_crtc->adjusted_y = y; | |
2723 | ||
48404c1e SJ |
2724 | I915_WRITE(reg, dspcntr); |
2725 | ||
01f2c773 | 2726 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2727 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2728 | I915_WRITE(DSPSURF(plane), |
2729 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2730 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2731 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2732 | } else |
f343c5f6 | 2733 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2734 | POSTING_READ(reg); |
17638cd6 JB |
2735 | } |
2736 | ||
a8d201af ML |
2737 | static void i9xx_disable_primary_plane(struct drm_plane *primary, |
2738 | struct drm_crtc *crtc) | |
17638cd6 JB |
2739 | { |
2740 | struct drm_device *dev = crtc->dev; | |
2741 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2742 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
17638cd6 | 2743 | int plane = intel_crtc->plane; |
f45651ba | 2744 | |
a8d201af ML |
2745 | I915_WRITE(DSPCNTR(plane), 0); |
2746 | if (INTEL_INFO(dev_priv)->gen >= 4) | |
fdd508a6 | 2747 | I915_WRITE(DSPSURF(plane), 0); |
a8d201af ML |
2748 | else |
2749 | I915_WRITE(DSPADDR(plane), 0); | |
2750 | POSTING_READ(DSPCNTR(plane)); | |
2751 | } | |
c9ba6fad | 2752 | |
a8d201af ML |
2753 | static void ironlake_update_primary_plane(struct drm_plane *primary, |
2754 | const struct intel_crtc_state *crtc_state, | |
2755 | const struct intel_plane_state *plane_state) | |
2756 | { | |
2757 | struct drm_device *dev = primary->dev; | |
2758 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2759 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
2760 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2761 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
2762 | int plane = intel_crtc->plane; | |
54ea9da8 | 2763 | u32 linear_offset; |
a8d201af ML |
2764 | u32 dspcntr; |
2765 | i915_reg_t reg = DSPCNTR(plane); | |
8d0deca8 | 2766 | unsigned int rotation = plane_state->base.rotation; |
ac484963 | 2767 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
a8d201af ML |
2768 | int x = plane_state->src.x1 >> 16; |
2769 | int y = plane_state->src.y1 >> 16; | |
c9ba6fad | 2770 | |
f45651ba | 2771 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
fdd508a6 | 2772 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2773 | |
2774 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2775 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2776 | |
57779d06 VS |
2777 | switch (fb->pixel_format) { |
2778 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2779 | dspcntr |= DISPPLANE_8BPP; |
2780 | break; | |
57779d06 VS |
2781 | case DRM_FORMAT_RGB565: |
2782 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2783 | break; |
57779d06 | 2784 | case DRM_FORMAT_XRGB8888: |
57779d06 VS |
2785 | dspcntr |= DISPPLANE_BGRX888; |
2786 | break; | |
2787 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2788 | dspcntr |= DISPPLANE_RGBX888; |
2789 | break; | |
2790 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2791 | dspcntr |= DISPPLANE_BGRX101010; |
2792 | break; | |
2793 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2794 | dspcntr |= DISPPLANE_RGBX101010; |
17638cd6 JB |
2795 | break; |
2796 | default: | |
baba133a | 2797 | BUG(); |
17638cd6 JB |
2798 | } |
2799 | ||
2800 | if (obj->tiling_mode != I915_TILING_NONE) | |
2801 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2802 | |
f45651ba | 2803 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2804 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2805 | |
ac484963 | 2806 | linear_offset = y * fb->pitches[0] + x * cpp; |
c2c75131 | 2807 | intel_crtc->dspaddr_offset = |
4f2d9934 | 2808 | intel_compute_tile_offset(&x, &y, fb, 0, |
8d0deca8 | 2809 | fb->pitches[0], rotation); |
c2c75131 | 2810 | linear_offset -= intel_crtc->dspaddr_offset; |
8d0deca8 | 2811 | if (rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2812 | dspcntr |= DISPPLANE_ROTATE_180; |
2813 | ||
2814 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
a8d201af ML |
2815 | x += (crtc_state->pipe_src_w - 1); |
2816 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
2817 | |
2818 | /* Finding the last pixel of the last line of the display | |
2819 | data and adding to linear_offset*/ | |
2820 | linear_offset += | |
a8d201af | 2821 | (crtc_state->pipe_src_h - 1) * fb->pitches[0] + |
ac484963 | 2822 | (crtc_state->pipe_src_w - 1) * cpp; |
48404c1e SJ |
2823 | } |
2824 | } | |
2825 | ||
2db3366b PZ |
2826 | intel_crtc->adjusted_x = x; |
2827 | intel_crtc->adjusted_y = y; | |
2828 | ||
48404c1e | 2829 | I915_WRITE(reg, dspcntr); |
17638cd6 | 2830 | |
01f2c773 | 2831 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2832 | I915_WRITE(DSPSURF(plane), |
2833 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2834 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2835 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2836 | } else { | |
2837 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2838 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2839 | } | |
17638cd6 | 2840 | POSTING_READ(reg); |
17638cd6 JB |
2841 | } |
2842 | ||
7b49f948 VS |
2843 | u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv, |
2844 | uint64_t fb_modifier, uint32_t pixel_format) | |
b321803d | 2845 | { |
7b49f948 | 2846 | if (fb_modifier == DRM_FORMAT_MOD_NONE) { |
b321803d | 2847 | return 64; |
7b49f948 VS |
2848 | } else { |
2849 | int cpp = drm_format_plane_cpp(pixel_format, 0); | |
2850 | ||
27ba3910 | 2851 | return intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
b321803d DL |
2852 | } |
2853 | } | |
2854 | ||
44eb0cb9 MK |
2855 | u32 intel_plane_obj_offset(struct intel_plane *intel_plane, |
2856 | struct drm_i915_gem_object *obj, | |
2857 | unsigned int plane) | |
121920fa | 2858 | { |
ce7f1728 | 2859 | struct i915_ggtt_view view; |
dedf278c | 2860 | struct i915_vma *vma; |
44eb0cb9 | 2861 | u64 offset; |
121920fa | 2862 | |
e7941294 | 2863 | intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb, |
3465c580 | 2864 | intel_plane->base.state->rotation); |
121920fa | 2865 | |
ce7f1728 | 2866 | vma = i915_gem_obj_to_ggtt_view(obj, &view); |
dedf278c | 2867 | if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n", |
ce7f1728 | 2868 | view.type)) |
dedf278c TU |
2869 | return -1; |
2870 | ||
44eb0cb9 | 2871 | offset = vma->node.start; |
dedf278c TU |
2872 | |
2873 | if (plane == 1) { | |
7723f47d | 2874 | offset += vma->ggtt_view.params.rotated.uv_start_page * |
dedf278c TU |
2875 | PAGE_SIZE; |
2876 | } | |
2877 | ||
44eb0cb9 MK |
2878 | WARN_ON(upper_32_bits(offset)); |
2879 | ||
2880 | return lower_32_bits(offset); | |
121920fa TU |
2881 | } |
2882 | ||
e435d6e5 ML |
2883 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
2884 | { | |
2885 | struct drm_device *dev = intel_crtc->base.dev; | |
2886 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2887 | ||
2888 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
2889 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
2890 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
2891 | } |
2892 | ||
a1b2278e CK |
2893 | /* |
2894 | * This function detaches (aka. unbinds) unused scalers in hardware | |
2895 | */ | |
0583236e | 2896 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 2897 | { |
a1b2278e CK |
2898 | struct intel_crtc_scaler_state *scaler_state; |
2899 | int i; | |
2900 | ||
a1b2278e CK |
2901 | scaler_state = &intel_crtc->config->scaler_state; |
2902 | ||
2903 | /* loop through and disable scalers that aren't in use */ | |
2904 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
2905 | if (!scaler_state->scalers[i].in_use) |
2906 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
2907 | } |
2908 | } | |
2909 | ||
6156a456 | 2910 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 2911 | { |
6156a456 | 2912 | switch (pixel_format) { |
d161cf7a | 2913 | case DRM_FORMAT_C8: |
c34ce3d1 | 2914 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 2915 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 2916 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 2917 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 2918 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 2919 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 2920 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
2921 | /* |
2922 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
2923 | * to be already pre-multiplied. We need to add a knob (or a different | |
2924 | * DRM_FORMAT) for user-space to configure that. | |
2925 | */ | |
f75fb42a | 2926 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 2927 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 2928 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 2929 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 2930 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 2931 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 2932 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 2933 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 2934 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 2935 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 2936 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 2937 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 2938 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 2939 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 2940 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 2941 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 2942 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 2943 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 2944 | default: |
4249eeef | 2945 | MISSING_CASE(pixel_format); |
70d21f0e | 2946 | } |
8cfcba41 | 2947 | |
c34ce3d1 | 2948 | return 0; |
6156a456 | 2949 | } |
70d21f0e | 2950 | |
6156a456 CK |
2951 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
2952 | { | |
6156a456 | 2953 | switch (fb_modifier) { |
30af77c4 | 2954 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 2955 | break; |
30af77c4 | 2956 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 2957 | return PLANE_CTL_TILED_X; |
b321803d | 2958 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 2959 | return PLANE_CTL_TILED_Y; |
b321803d | 2960 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 2961 | return PLANE_CTL_TILED_YF; |
70d21f0e | 2962 | default: |
6156a456 | 2963 | MISSING_CASE(fb_modifier); |
70d21f0e | 2964 | } |
8cfcba41 | 2965 | |
c34ce3d1 | 2966 | return 0; |
6156a456 | 2967 | } |
70d21f0e | 2968 | |
6156a456 CK |
2969 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
2970 | { | |
3b7a5119 | 2971 | switch (rotation) { |
6156a456 CK |
2972 | case BIT(DRM_ROTATE_0): |
2973 | break; | |
1e8df167 SJ |
2974 | /* |
2975 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
2976 | * while i915 HW rotation is clockwise, thats why this swapping. | |
2977 | */ | |
3b7a5119 | 2978 | case BIT(DRM_ROTATE_90): |
1e8df167 | 2979 | return PLANE_CTL_ROTATE_270; |
3b7a5119 | 2980 | case BIT(DRM_ROTATE_180): |
c34ce3d1 | 2981 | return PLANE_CTL_ROTATE_180; |
3b7a5119 | 2982 | case BIT(DRM_ROTATE_270): |
1e8df167 | 2983 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
2984 | default: |
2985 | MISSING_CASE(rotation); | |
2986 | } | |
2987 | ||
c34ce3d1 | 2988 | return 0; |
6156a456 CK |
2989 | } |
2990 | ||
a8d201af ML |
2991 | static void skylake_update_primary_plane(struct drm_plane *plane, |
2992 | const struct intel_crtc_state *crtc_state, | |
2993 | const struct intel_plane_state *plane_state) | |
6156a456 | 2994 | { |
a8d201af | 2995 | struct drm_device *dev = plane->dev; |
6156a456 | 2996 | struct drm_i915_private *dev_priv = dev->dev_private; |
a8d201af ML |
2997 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
2998 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2999 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
6156a456 CK |
3000 | int pipe = intel_crtc->pipe; |
3001 | u32 plane_ctl, stride_div, stride; | |
3002 | u32 tile_height, plane_offset, plane_size; | |
a8d201af | 3003 | unsigned int rotation = plane_state->base.rotation; |
6156a456 | 3004 | int x_offset, y_offset; |
44eb0cb9 | 3005 | u32 surf_addr; |
a8d201af ML |
3006 | int scaler_id = plane_state->scaler_id; |
3007 | int src_x = plane_state->src.x1 >> 16; | |
3008 | int src_y = plane_state->src.y1 >> 16; | |
3009 | int src_w = drm_rect_width(&plane_state->src) >> 16; | |
3010 | int src_h = drm_rect_height(&plane_state->src) >> 16; | |
3011 | int dst_x = plane_state->dst.x1; | |
3012 | int dst_y = plane_state->dst.y1; | |
3013 | int dst_w = drm_rect_width(&plane_state->dst); | |
3014 | int dst_h = drm_rect_height(&plane_state->dst); | |
70d21f0e | 3015 | |
6156a456 CK |
3016 | plane_ctl = PLANE_CTL_ENABLE | |
3017 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3018 | PLANE_CTL_PIPE_CSC_ENABLE; | |
3019 | ||
3020 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); | |
3021 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
3022 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
6156a456 CK |
3023 | plane_ctl |= skl_plane_ctl_rotation(rotation); |
3024 | ||
7b49f948 | 3025 | stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
b321803d | 3026 | fb->pixel_format); |
dedf278c | 3027 | surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0); |
3b7a5119 | 3028 | |
a42e5a23 PZ |
3029 | WARN_ON(drm_rect_width(&plane_state->src) == 0); |
3030 | ||
3b7a5119 | 3031 | if (intel_rotation_90_or_270(rotation)) { |
832be82f VS |
3032 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
3033 | ||
3b7a5119 | 3034 | /* stride = Surface height in tiles */ |
832be82f | 3035 | tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp); |
3b7a5119 | 3036 | stride = DIV_ROUND_UP(fb->height, tile_height); |
a8d201af ML |
3037 | x_offset = stride * tile_height - src_y - src_h; |
3038 | y_offset = src_x; | |
6156a456 | 3039 | plane_size = (src_w - 1) << 16 | (src_h - 1); |
3b7a5119 SJ |
3040 | } else { |
3041 | stride = fb->pitches[0] / stride_div; | |
a8d201af ML |
3042 | x_offset = src_x; |
3043 | y_offset = src_y; | |
6156a456 | 3044 | plane_size = (src_h - 1) << 16 | (src_w - 1); |
3b7a5119 SJ |
3045 | } |
3046 | plane_offset = y_offset << 16 | x_offset; | |
b321803d | 3047 | |
2db3366b PZ |
3048 | intel_crtc->adjusted_x = x_offset; |
3049 | intel_crtc->adjusted_y = y_offset; | |
3050 | ||
70d21f0e | 3051 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
3b7a5119 SJ |
3052 | I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); |
3053 | I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); | |
3054 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
6156a456 CK |
3055 | |
3056 | if (scaler_id >= 0) { | |
3057 | uint32_t ps_ctrl = 0; | |
3058 | ||
3059 | WARN_ON(!dst_w || !dst_h); | |
3060 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | | |
3061 | crtc_state->scaler_state.scalers[scaler_id].mode; | |
3062 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3063 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3064 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3065 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3066 | I915_WRITE(PLANE_POS(pipe, 0), 0); | |
3067 | } else { | |
3068 | I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); | |
3069 | } | |
3070 | ||
121920fa | 3071 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
70d21f0e DL |
3072 | |
3073 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3074 | } | |
3075 | ||
a8d201af ML |
3076 | static void skylake_disable_primary_plane(struct drm_plane *primary, |
3077 | struct drm_crtc *crtc) | |
17638cd6 JB |
3078 | { |
3079 | struct drm_device *dev = crtc->dev; | |
3080 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a8d201af | 3081 | int pipe = to_intel_crtc(crtc)->pipe; |
17638cd6 | 3082 | |
a8d201af ML |
3083 | I915_WRITE(PLANE_CTL(pipe, 0), 0); |
3084 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
3085 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3086 | } | |
29b9bde6 | 3087 | |
a8d201af ML |
3088 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3089 | static int | |
3090 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3091 | int x, int y, enum mode_set_atomic state) | |
3092 | { | |
3093 | /* Support for kgdboc is disabled, this needs a major rework. */ | |
3094 | DRM_ERROR("legacy panic handler not supported any more.\n"); | |
3095 | ||
3096 | return -ENODEV; | |
81255565 JB |
3097 | } |
3098 | ||
7514747d VS |
3099 | static void intel_update_primary_planes(struct drm_device *dev) |
3100 | { | |
7514747d | 3101 | struct drm_crtc *crtc; |
96a02917 | 3102 | |
70e1e0ec | 3103 | for_each_crtc(dev, crtc) { |
11c22da6 ML |
3104 | struct intel_plane *plane = to_intel_plane(crtc->primary); |
3105 | struct intel_plane_state *plane_state; | |
96a02917 | 3106 | |
11c22da6 | 3107 | drm_modeset_lock_crtc(crtc, &plane->base); |
11c22da6 ML |
3108 | plane_state = to_intel_plane_state(plane->base.state); |
3109 | ||
a8d201af ML |
3110 | if (plane_state->visible) |
3111 | plane->update_plane(&plane->base, | |
3112 | to_intel_crtc_state(crtc->state), | |
3113 | plane_state); | |
11c22da6 ML |
3114 | |
3115 | drm_modeset_unlock_crtc(crtc); | |
96a02917 VS |
3116 | } |
3117 | } | |
3118 | ||
c033666a | 3119 | void intel_prepare_reset(struct drm_i915_private *dev_priv) |
7514747d VS |
3120 | { |
3121 | /* no reset support for gen2 */ | |
c033666a | 3122 | if (IS_GEN2(dev_priv)) |
7514747d VS |
3123 | return; |
3124 | ||
3125 | /* reset doesn't touch the display */ | |
c033666a | 3126 | if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) |
7514747d VS |
3127 | return; |
3128 | ||
c033666a | 3129 | drm_modeset_lock_all(dev_priv->dev); |
f98ce92f VS |
3130 | /* |
3131 | * Disabling the crtcs gracefully seems nicer. Also the | |
3132 | * g33 docs say we should at least disable all the planes. | |
3133 | */ | |
c033666a | 3134 | intel_display_suspend(dev_priv->dev); |
7514747d VS |
3135 | } |
3136 | ||
c033666a | 3137 | void intel_finish_reset(struct drm_i915_private *dev_priv) |
7514747d | 3138 | { |
7514747d | 3139 | /* no reset support for gen2 */ |
c033666a | 3140 | if (IS_GEN2(dev_priv)) |
7514747d VS |
3141 | return; |
3142 | ||
3143 | /* reset doesn't touch the display */ | |
c033666a | 3144 | if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) { |
7514747d VS |
3145 | /* |
3146 | * Flips in the rings have been nuked by the reset, | |
3147 | * so update the base address of all primary | |
3148 | * planes to the the last fb to make sure we're | |
3149 | * showing the correct fb after a reset. | |
11c22da6 ML |
3150 | * |
3151 | * FIXME: Atomic will make this obsolete since we won't schedule | |
3152 | * CS-based flips (which might get lost in gpu resets) any more. | |
7514747d | 3153 | */ |
c033666a | 3154 | intel_update_primary_planes(dev_priv->dev); |
7514747d VS |
3155 | return; |
3156 | } | |
3157 | ||
3158 | /* | |
3159 | * The display has been reset as well, | |
3160 | * so need a full re-initialization. | |
3161 | */ | |
3162 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3163 | intel_runtime_pm_enable_interrupts(dev_priv); | |
3164 | ||
c033666a | 3165 | intel_modeset_init_hw(dev_priv->dev); |
7514747d VS |
3166 | |
3167 | spin_lock_irq(&dev_priv->irq_lock); | |
3168 | if (dev_priv->display.hpd_irq_setup) | |
91d14251 | 3169 | dev_priv->display.hpd_irq_setup(dev_priv); |
7514747d VS |
3170 | spin_unlock_irq(&dev_priv->irq_lock); |
3171 | ||
c033666a | 3172 | intel_display_resume(dev_priv->dev); |
7514747d VS |
3173 | |
3174 | intel_hpd_init(dev_priv); | |
3175 | ||
c033666a | 3176 | drm_modeset_unlock_all(dev_priv->dev); |
7514747d VS |
3177 | } |
3178 | ||
7d5e3799 CW |
3179 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3180 | { | |
6885843a | 3181 | return !list_empty_careful(&to_intel_crtc(crtc)->flip_work); |
7d5e3799 CW |
3182 | } |
3183 | ||
bfd16b2a ML |
3184 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
3185 | struct intel_crtc_state *old_crtc_state) | |
e30e8f75 GP |
3186 | { |
3187 | struct drm_device *dev = crtc->base.dev; | |
3188 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bfd16b2a ML |
3189 | struct intel_crtc_state *pipe_config = |
3190 | to_intel_crtc_state(crtc->base.state); | |
e30e8f75 | 3191 | |
bfd16b2a ML |
3192 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
3193 | crtc->base.mode = crtc->base.state->mode; | |
3194 | ||
3195 | DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n", | |
3196 | old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h, | |
3197 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
e30e8f75 GP |
3198 | |
3199 | /* | |
3200 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3201 | * that in compute_mode_changes we check the native mode (not the pfit | |
3202 | * mode) to see if we can flip rather than do a full mode set. In the | |
3203 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3204 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3205 | * sized surface. | |
e30e8f75 GP |
3206 | */ |
3207 | ||
e30e8f75 | 3208 | I915_WRITE(PIPESRC(crtc->pipe), |
bfd16b2a ML |
3209 | ((pipe_config->pipe_src_w - 1) << 16) | |
3210 | (pipe_config->pipe_src_h - 1)); | |
3211 | ||
3212 | /* on skylake this is done by detaching scalers */ | |
3213 | if (INTEL_INFO(dev)->gen >= 9) { | |
3214 | skl_detach_scalers(crtc); | |
3215 | ||
3216 | if (pipe_config->pch_pfit.enabled) | |
3217 | skylake_pfit_enable(crtc); | |
3218 | } else if (HAS_PCH_SPLIT(dev)) { | |
3219 | if (pipe_config->pch_pfit.enabled) | |
3220 | ironlake_pfit_enable(crtc); | |
3221 | else if (old_crtc_state->pch_pfit.enabled) | |
3222 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3223 | } |
e30e8f75 GP |
3224 | } |
3225 | ||
5e84e1a4 ZW |
3226 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3227 | { | |
3228 | struct drm_device *dev = crtc->dev; | |
3229 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3230 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3231 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3232 | i915_reg_t reg; |
3233 | u32 temp; | |
5e84e1a4 ZW |
3234 | |
3235 | /* enable normal train */ | |
3236 | reg = FDI_TX_CTL(pipe); | |
3237 | temp = I915_READ(reg); | |
61e499bf | 3238 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3239 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3240 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3241 | } else { |
3242 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3243 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3244 | } |
5e84e1a4 ZW |
3245 | I915_WRITE(reg, temp); |
3246 | ||
3247 | reg = FDI_RX_CTL(pipe); | |
3248 | temp = I915_READ(reg); | |
3249 | if (HAS_PCH_CPT(dev)) { | |
3250 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3251 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3252 | } else { | |
3253 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3254 | temp |= FDI_LINK_TRAIN_NONE; | |
3255 | } | |
3256 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3257 | ||
3258 | /* wait one idle pattern time */ | |
3259 | POSTING_READ(reg); | |
3260 | udelay(1000); | |
357555c0 JB |
3261 | |
3262 | /* IVB wants error correction enabled */ | |
3263 | if (IS_IVYBRIDGE(dev)) | |
3264 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3265 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3266 | } |
3267 | ||
8db9d77b ZW |
3268 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3269 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3270 | { | |
3271 | struct drm_device *dev = crtc->dev; | |
3272 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3273 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3274 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3275 | i915_reg_t reg; |
3276 | u32 temp, tries; | |
8db9d77b | 3277 | |
1c8562f6 | 3278 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3279 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3280 | |
e1a44743 AJ |
3281 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3282 | for train result */ | |
5eddb70b CW |
3283 | reg = FDI_RX_IMR(pipe); |
3284 | temp = I915_READ(reg); | |
e1a44743 AJ |
3285 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3286 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3287 | I915_WRITE(reg, temp); |
3288 | I915_READ(reg); | |
e1a44743 AJ |
3289 | udelay(150); |
3290 | ||
8db9d77b | 3291 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3292 | reg = FDI_TX_CTL(pipe); |
3293 | temp = I915_READ(reg); | |
627eb5a3 | 3294 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3295 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3296 | temp &= ~FDI_LINK_TRAIN_NONE; |
3297 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3298 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3299 | |
5eddb70b CW |
3300 | reg = FDI_RX_CTL(pipe); |
3301 | temp = I915_READ(reg); | |
8db9d77b ZW |
3302 | temp &= ~FDI_LINK_TRAIN_NONE; |
3303 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3304 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3305 | ||
3306 | POSTING_READ(reg); | |
8db9d77b ZW |
3307 | udelay(150); |
3308 | ||
5b2adf89 | 3309 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3310 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3311 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3312 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3313 | |
5eddb70b | 3314 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3315 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3316 | temp = I915_READ(reg); |
8db9d77b ZW |
3317 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3318 | ||
3319 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3320 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3321 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3322 | break; |
3323 | } | |
8db9d77b | 3324 | } |
e1a44743 | 3325 | if (tries == 5) |
5eddb70b | 3326 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3327 | |
3328 | /* Train 2 */ | |
5eddb70b CW |
3329 | reg = FDI_TX_CTL(pipe); |
3330 | temp = I915_READ(reg); | |
8db9d77b ZW |
3331 | temp &= ~FDI_LINK_TRAIN_NONE; |
3332 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3333 | I915_WRITE(reg, temp); |
8db9d77b | 3334 | |
5eddb70b CW |
3335 | reg = FDI_RX_CTL(pipe); |
3336 | temp = I915_READ(reg); | |
8db9d77b ZW |
3337 | temp &= ~FDI_LINK_TRAIN_NONE; |
3338 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3339 | I915_WRITE(reg, temp); |
8db9d77b | 3340 | |
5eddb70b CW |
3341 | POSTING_READ(reg); |
3342 | udelay(150); | |
8db9d77b | 3343 | |
5eddb70b | 3344 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3345 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3346 | temp = I915_READ(reg); |
8db9d77b ZW |
3347 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3348 | ||
3349 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3350 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3351 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3352 | break; | |
3353 | } | |
8db9d77b | 3354 | } |
e1a44743 | 3355 | if (tries == 5) |
5eddb70b | 3356 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3357 | |
3358 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3359 | |
8db9d77b ZW |
3360 | } |
3361 | ||
0206e353 | 3362 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3363 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3364 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3365 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3366 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3367 | }; | |
3368 | ||
3369 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3370 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3371 | { | |
3372 | struct drm_device *dev = crtc->dev; | |
3373 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3374 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3375 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3376 | i915_reg_t reg; |
3377 | u32 temp, i, retry; | |
8db9d77b | 3378 | |
e1a44743 AJ |
3379 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3380 | for train result */ | |
5eddb70b CW |
3381 | reg = FDI_RX_IMR(pipe); |
3382 | temp = I915_READ(reg); | |
e1a44743 AJ |
3383 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3384 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3385 | I915_WRITE(reg, temp); |
3386 | ||
3387 | POSTING_READ(reg); | |
e1a44743 AJ |
3388 | udelay(150); |
3389 | ||
8db9d77b | 3390 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3391 | reg = FDI_TX_CTL(pipe); |
3392 | temp = I915_READ(reg); | |
627eb5a3 | 3393 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3394 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3395 | temp &= ~FDI_LINK_TRAIN_NONE; |
3396 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3397 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3398 | /* SNB-B */ | |
3399 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3400 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3401 | |
d74cf324 DV |
3402 | I915_WRITE(FDI_RX_MISC(pipe), |
3403 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3404 | ||
5eddb70b CW |
3405 | reg = FDI_RX_CTL(pipe); |
3406 | temp = I915_READ(reg); | |
8db9d77b ZW |
3407 | if (HAS_PCH_CPT(dev)) { |
3408 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3409 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3410 | } else { | |
3411 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3412 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3413 | } | |
5eddb70b CW |
3414 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3415 | ||
3416 | POSTING_READ(reg); | |
8db9d77b ZW |
3417 | udelay(150); |
3418 | ||
0206e353 | 3419 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3420 | reg = FDI_TX_CTL(pipe); |
3421 | temp = I915_READ(reg); | |
8db9d77b ZW |
3422 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3423 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3424 | I915_WRITE(reg, temp); |
3425 | ||
3426 | POSTING_READ(reg); | |
8db9d77b ZW |
3427 | udelay(500); |
3428 | ||
fa37d39e SP |
3429 | for (retry = 0; retry < 5; retry++) { |
3430 | reg = FDI_RX_IIR(pipe); | |
3431 | temp = I915_READ(reg); | |
3432 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3433 | if (temp & FDI_RX_BIT_LOCK) { | |
3434 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3435 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3436 | break; | |
3437 | } | |
3438 | udelay(50); | |
8db9d77b | 3439 | } |
fa37d39e SP |
3440 | if (retry < 5) |
3441 | break; | |
8db9d77b ZW |
3442 | } |
3443 | if (i == 4) | |
5eddb70b | 3444 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3445 | |
3446 | /* Train 2 */ | |
5eddb70b CW |
3447 | reg = FDI_TX_CTL(pipe); |
3448 | temp = I915_READ(reg); | |
8db9d77b ZW |
3449 | temp &= ~FDI_LINK_TRAIN_NONE; |
3450 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3451 | if (IS_GEN6(dev)) { | |
3452 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3453 | /* SNB-B */ | |
3454 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3455 | } | |
5eddb70b | 3456 | I915_WRITE(reg, temp); |
8db9d77b | 3457 | |
5eddb70b CW |
3458 | reg = FDI_RX_CTL(pipe); |
3459 | temp = I915_READ(reg); | |
8db9d77b ZW |
3460 | if (HAS_PCH_CPT(dev)) { |
3461 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3462 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3463 | } else { | |
3464 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3465 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3466 | } | |
5eddb70b CW |
3467 | I915_WRITE(reg, temp); |
3468 | ||
3469 | POSTING_READ(reg); | |
8db9d77b ZW |
3470 | udelay(150); |
3471 | ||
0206e353 | 3472 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3473 | reg = FDI_TX_CTL(pipe); |
3474 | temp = I915_READ(reg); | |
8db9d77b ZW |
3475 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3476 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3477 | I915_WRITE(reg, temp); |
3478 | ||
3479 | POSTING_READ(reg); | |
8db9d77b ZW |
3480 | udelay(500); |
3481 | ||
fa37d39e SP |
3482 | for (retry = 0; retry < 5; retry++) { |
3483 | reg = FDI_RX_IIR(pipe); | |
3484 | temp = I915_READ(reg); | |
3485 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3486 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3487 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3488 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3489 | break; | |
3490 | } | |
3491 | udelay(50); | |
8db9d77b | 3492 | } |
fa37d39e SP |
3493 | if (retry < 5) |
3494 | break; | |
8db9d77b ZW |
3495 | } |
3496 | if (i == 4) | |
5eddb70b | 3497 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3498 | |
3499 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3500 | } | |
3501 | ||
357555c0 JB |
3502 | /* Manual link training for Ivy Bridge A0 parts */ |
3503 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3504 | { | |
3505 | struct drm_device *dev = crtc->dev; | |
3506 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3507 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3508 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3509 | i915_reg_t reg; |
3510 | u32 temp, i, j; | |
357555c0 JB |
3511 | |
3512 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3513 | for train result */ | |
3514 | reg = FDI_RX_IMR(pipe); | |
3515 | temp = I915_READ(reg); | |
3516 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3517 | temp &= ~FDI_RX_BIT_LOCK; | |
3518 | I915_WRITE(reg, temp); | |
3519 | ||
3520 | POSTING_READ(reg); | |
3521 | udelay(150); | |
3522 | ||
01a415fd DV |
3523 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3524 | I915_READ(FDI_RX_IIR(pipe))); | |
3525 | ||
139ccd3f JB |
3526 | /* Try each vswing and preemphasis setting twice before moving on */ |
3527 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3528 | /* disable first in case we need to retry */ | |
3529 | reg = FDI_TX_CTL(pipe); | |
3530 | temp = I915_READ(reg); | |
3531 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3532 | temp &= ~FDI_TX_ENABLE; | |
3533 | I915_WRITE(reg, temp); | |
357555c0 | 3534 | |
139ccd3f JB |
3535 | reg = FDI_RX_CTL(pipe); |
3536 | temp = I915_READ(reg); | |
3537 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3538 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3539 | temp &= ~FDI_RX_ENABLE; | |
3540 | I915_WRITE(reg, temp); | |
357555c0 | 3541 | |
139ccd3f | 3542 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3543 | reg = FDI_TX_CTL(pipe); |
3544 | temp = I915_READ(reg); | |
139ccd3f | 3545 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3546 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 3547 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3548 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3549 | temp |= snb_b_fdi_train_param[j/2]; |
3550 | temp |= FDI_COMPOSITE_SYNC; | |
3551 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3552 | |
139ccd3f JB |
3553 | I915_WRITE(FDI_RX_MISC(pipe), |
3554 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3555 | |
139ccd3f | 3556 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3557 | temp = I915_READ(reg); |
139ccd3f JB |
3558 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3559 | temp |= FDI_COMPOSITE_SYNC; | |
3560 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3561 | |
139ccd3f JB |
3562 | POSTING_READ(reg); |
3563 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3564 | |
139ccd3f JB |
3565 | for (i = 0; i < 4; i++) { |
3566 | reg = FDI_RX_IIR(pipe); | |
3567 | temp = I915_READ(reg); | |
3568 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3569 | |
139ccd3f JB |
3570 | if (temp & FDI_RX_BIT_LOCK || |
3571 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3572 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3573 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3574 | i); | |
3575 | break; | |
3576 | } | |
3577 | udelay(1); /* should be 0.5us */ | |
3578 | } | |
3579 | if (i == 4) { | |
3580 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3581 | continue; | |
3582 | } | |
357555c0 | 3583 | |
139ccd3f | 3584 | /* Train 2 */ |
357555c0 JB |
3585 | reg = FDI_TX_CTL(pipe); |
3586 | temp = I915_READ(reg); | |
139ccd3f JB |
3587 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3588 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3589 | I915_WRITE(reg, temp); | |
3590 | ||
3591 | reg = FDI_RX_CTL(pipe); | |
3592 | temp = I915_READ(reg); | |
3593 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3594 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3595 | I915_WRITE(reg, temp); |
3596 | ||
3597 | POSTING_READ(reg); | |
139ccd3f | 3598 | udelay(2); /* should be 1.5us */ |
357555c0 | 3599 | |
139ccd3f JB |
3600 | for (i = 0; i < 4; i++) { |
3601 | reg = FDI_RX_IIR(pipe); | |
3602 | temp = I915_READ(reg); | |
3603 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3604 | |
139ccd3f JB |
3605 | if (temp & FDI_RX_SYMBOL_LOCK || |
3606 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3607 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3608 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3609 | i); | |
3610 | goto train_done; | |
3611 | } | |
3612 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3613 | } |
139ccd3f JB |
3614 | if (i == 4) |
3615 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3616 | } |
357555c0 | 3617 | |
139ccd3f | 3618 | train_done: |
357555c0 JB |
3619 | DRM_DEBUG_KMS("FDI train done.\n"); |
3620 | } | |
3621 | ||
88cefb6c | 3622 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3623 | { |
88cefb6c | 3624 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3625 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3626 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
3627 | i915_reg_t reg; |
3628 | u32 temp; | |
c64e311e | 3629 | |
c98e9dcf | 3630 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3631 | reg = FDI_RX_CTL(pipe); |
3632 | temp = I915_READ(reg); | |
627eb5a3 | 3633 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3634 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3635 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3636 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3637 | ||
3638 | POSTING_READ(reg); | |
c98e9dcf JB |
3639 | udelay(200); |
3640 | ||
3641 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3642 | temp = I915_READ(reg); |
3643 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3644 | ||
3645 | POSTING_READ(reg); | |
c98e9dcf JB |
3646 | udelay(200); |
3647 | ||
20749730 PZ |
3648 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3649 | reg = FDI_TX_CTL(pipe); | |
3650 | temp = I915_READ(reg); | |
3651 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3652 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3653 | |
20749730 PZ |
3654 | POSTING_READ(reg); |
3655 | udelay(100); | |
6be4a607 | 3656 | } |
0e23b99d JB |
3657 | } |
3658 | ||
88cefb6c DV |
3659 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3660 | { | |
3661 | struct drm_device *dev = intel_crtc->base.dev; | |
3662 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3663 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3664 | i915_reg_t reg; |
3665 | u32 temp; | |
88cefb6c DV |
3666 | |
3667 | /* Switch from PCDclk to Rawclk */ | |
3668 | reg = FDI_RX_CTL(pipe); | |
3669 | temp = I915_READ(reg); | |
3670 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3671 | ||
3672 | /* Disable CPU FDI TX PLL */ | |
3673 | reg = FDI_TX_CTL(pipe); | |
3674 | temp = I915_READ(reg); | |
3675 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3676 | ||
3677 | POSTING_READ(reg); | |
3678 | udelay(100); | |
3679 | ||
3680 | reg = FDI_RX_CTL(pipe); | |
3681 | temp = I915_READ(reg); | |
3682 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3683 | ||
3684 | /* Wait for the clocks to turn off. */ | |
3685 | POSTING_READ(reg); | |
3686 | udelay(100); | |
3687 | } | |
3688 | ||
0fc932b8 JB |
3689 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3690 | { | |
3691 | struct drm_device *dev = crtc->dev; | |
3692 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3693 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3694 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3695 | i915_reg_t reg; |
3696 | u32 temp; | |
0fc932b8 JB |
3697 | |
3698 | /* disable CPU FDI tx and PCH FDI rx */ | |
3699 | reg = FDI_TX_CTL(pipe); | |
3700 | temp = I915_READ(reg); | |
3701 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3702 | POSTING_READ(reg); | |
3703 | ||
3704 | reg = FDI_RX_CTL(pipe); | |
3705 | temp = I915_READ(reg); | |
3706 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3707 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3708 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3709 | ||
3710 | POSTING_READ(reg); | |
3711 | udelay(100); | |
3712 | ||
3713 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3714 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3715 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3716 | |
3717 | /* still set train pattern 1 */ | |
3718 | reg = FDI_TX_CTL(pipe); | |
3719 | temp = I915_READ(reg); | |
3720 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3721 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3722 | I915_WRITE(reg, temp); | |
3723 | ||
3724 | reg = FDI_RX_CTL(pipe); | |
3725 | temp = I915_READ(reg); | |
3726 | if (HAS_PCH_CPT(dev)) { | |
3727 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3728 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3729 | } else { | |
3730 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3731 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3732 | } | |
3733 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3734 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3735 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3736 | I915_WRITE(reg, temp); |
3737 | ||
3738 | POSTING_READ(reg); | |
3739 | udelay(100); | |
3740 | } | |
3741 | ||
5dce5b93 CW |
3742 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3743 | { | |
3744 | struct intel_crtc *crtc; | |
3745 | ||
3746 | /* Note that we don't need to be called with mode_config.lock here | |
3747 | * as our list of CRTC objects is static for the lifetime of the | |
3748 | * device and so cannot disappear as we iterate. Similarly, we can | |
3749 | * happily treat the predicates as racy, atomic checks as userspace | |
3750 | * cannot claim and pin a new fb without at least acquring the | |
3751 | * struct_mutex and so serialising with us. | |
3752 | */ | |
d3fcc808 | 3753 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3754 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3755 | continue; | |
3756 | ||
6885843a | 3757 | if (!list_empty_careful(&crtc->flip_work)) |
5dce5b93 CW |
3758 | intel_wait_for_vblank(dev, crtc->pipe); |
3759 | ||
3760 | return true; | |
3761 | } | |
3762 | ||
3763 | return false; | |
3764 | } | |
3765 | ||
6885843a | 3766 | static void page_flip_completed(struct intel_crtc *intel_crtc, struct intel_flip_work *work) |
d6bbafa1 CW |
3767 | { |
3768 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
143f73b3 ML |
3769 | struct drm_plane_state *new_plane_state; |
3770 | struct drm_plane *primary = intel_crtc->base.primary; | |
d6bbafa1 CW |
3771 | |
3772 | if (work->event) | |
560ce1dc | 3773 | drm_crtc_send_vblank_event(&intel_crtc->base, work->event); |
d6bbafa1 CW |
3774 | |
3775 | drm_crtc_vblank_put(&intel_crtc->base); | |
3776 | ||
143f73b3 ML |
3777 | new_plane_state = &work->old_plane_state[0]->base; |
3778 | if (work->num_planes >= 1 && | |
3779 | new_plane_state->plane == primary && | |
3780 | new_plane_state->fb) | |
3781 | trace_i915_flip_complete(intel_crtc->plane, | |
3782 | intel_fb_obj(new_plane_state->fb)); | |
d6bbafa1 | 3783 | |
143f73b3 ML |
3784 | if (work->can_async_unpin) { |
3785 | list_del_init(&work->head); | |
3786 | wake_up_all(&dev_priv->pending_flip_queue); | |
3787 | } | |
3788 | ||
3789 | queue_work(dev_priv->wq, &work->unpin_work); | |
d6bbafa1 CW |
3790 | } |
3791 | ||
5008e874 | 3792 | static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3793 | { |
0f91128d | 3794 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3795 | struct drm_i915_private *dev_priv = dev->dev_private; |
5008e874 | 3796 | long ret; |
e6c3a2a6 | 3797 | |
2c10d571 | 3798 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
5008e874 ML |
3799 | |
3800 | ret = wait_event_interruptible_timeout( | |
3801 | dev_priv->pending_flip_queue, | |
3802 | !intel_crtc_has_pending_flip(crtc), | |
3803 | 60*HZ); | |
3804 | ||
3805 | if (ret < 0) | |
3806 | return ret; | |
3807 | ||
8dd634d9 | 3808 | WARN(ret == 0, "Stuck page flip\n"); |
5bb61643 | 3809 | |
5008e874 | 3810 | return 0; |
e6c3a2a6 CW |
3811 | } |
3812 | ||
060f02d8 VS |
3813 | static void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
3814 | { | |
3815 | u32 temp; | |
3816 | ||
3817 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3818 | ||
3819 | mutex_lock(&dev_priv->sb_lock); | |
3820 | ||
3821 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
3822 | temp |= SBI_SSCCTL_DISABLE; | |
3823 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
3824 | ||
3825 | mutex_unlock(&dev_priv->sb_lock); | |
3826 | } | |
3827 | ||
e615efe4 ED |
3828 | /* Program iCLKIP clock to the desired frequency */ |
3829 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3830 | { | |
64b46a06 | 3831 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
6e3c9717 | 3832 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
3833 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3834 | u32 temp; | |
3835 | ||
060f02d8 | 3836 | lpt_disable_iclkip(dev_priv); |
e615efe4 | 3837 | |
64b46a06 VS |
3838 | /* The iCLK virtual clock root frequency is in MHz, |
3839 | * but the adjusted_mode->crtc_clock in in KHz. To get the | |
3840 | * divisors, it is necessary to divide one by another, so we | |
3841 | * convert the virtual clock precision to KHz here for higher | |
3842 | * precision. | |
3843 | */ | |
3844 | for (auxdiv = 0; auxdiv < 2; auxdiv++) { | |
e615efe4 ED |
3845 | u32 iclk_virtual_root_freq = 172800 * 1000; |
3846 | u32 iclk_pi_range = 64; | |
64b46a06 | 3847 | u32 desired_divisor; |
e615efe4 | 3848 | |
64b46a06 VS |
3849 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, |
3850 | clock << auxdiv); | |
3851 | divsel = (desired_divisor / iclk_pi_range) - 2; | |
3852 | phaseinc = desired_divisor % iclk_pi_range; | |
e615efe4 | 3853 | |
64b46a06 VS |
3854 | /* |
3855 | * Near 20MHz is a corner case which is | |
3856 | * out of range for the 7-bit divisor | |
3857 | */ | |
3858 | if (divsel <= 0x7f) | |
3859 | break; | |
e615efe4 ED |
3860 | } |
3861 | ||
3862 | /* This should not happen with any sane values */ | |
3863 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3864 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3865 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3866 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3867 | ||
3868 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3869 | clock, |
e615efe4 ED |
3870 | auxdiv, |
3871 | divsel, | |
3872 | phasedir, | |
3873 | phaseinc); | |
3874 | ||
060f02d8 VS |
3875 | mutex_lock(&dev_priv->sb_lock); |
3876 | ||
e615efe4 | 3877 | /* Program SSCDIVINTPHASE6 */ |
988d6ee8 | 3878 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3879 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3880 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3881 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3882 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3883 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3884 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3885 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3886 | |
3887 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3888 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3889 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3890 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3891 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3892 | |
3893 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3894 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3895 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3896 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 | 3897 | |
060f02d8 VS |
3898 | mutex_unlock(&dev_priv->sb_lock); |
3899 | ||
e615efe4 ED |
3900 | /* Wait for initialization time */ |
3901 | udelay(24); | |
3902 | ||
3903 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
3904 | } | |
3905 | ||
8802e5b6 VS |
3906 | int lpt_get_iclkip(struct drm_i915_private *dev_priv) |
3907 | { | |
3908 | u32 divsel, phaseinc, auxdiv; | |
3909 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3910 | u32 iclk_pi_range = 64; | |
3911 | u32 desired_divisor; | |
3912 | u32 temp; | |
3913 | ||
3914 | if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) | |
3915 | return 0; | |
3916 | ||
3917 | mutex_lock(&dev_priv->sb_lock); | |
3918 | ||
3919 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
3920 | if (temp & SBI_SSCCTL_DISABLE) { | |
3921 | mutex_unlock(&dev_priv->sb_lock); | |
3922 | return 0; | |
3923 | } | |
3924 | ||
3925 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); | |
3926 | divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >> | |
3927 | SBI_SSCDIVINTPHASE_DIVSEL_SHIFT; | |
3928 | phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >> | |
3929 | SBI_SSCDIVINTPHASE_INCVAL_SHIFT; | |
3930 | ||
3931 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); | |
3932 | auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >> | |
3933 | SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT; | |
3934 | ||
3935 | mutex_unlock(&dev_priv->sb_lock); | |
3936 | ||
3937 | desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc; | |
3938 | ||
3939 | return DIV_ROUND_CLOSEST(iclk_virtual_root_freq, | |
3940 | desired_divisor << auxdiv); | |
3941 | } | |
3942 | ||
275f01b2 DV |
3943 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
3944 | enum pipe pch_transcoder) | |
3945 | { | |
3946 | struct drm_device *dev = crtc->base.dev; | |
3947 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 3948 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
3949 | |
3950 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
3951 | I915_READ(HTOTAL(cpu_transcoder))); | |
3952 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
3953 | I915_READ(HBLANK(cpu_transcoder))); | |
3954 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
3955 | I915_READ(HSYNC(cpu_transcoder))); | |
3956 | ||
3957 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
3958 | I915_READ(VTOTAL(cpu_transcoder))); | |
3959 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
3960 | I915_READ(VBLANK(cpu_transcoder))); | |
3961 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
3962 | I915_READ(VSYNC(cpu_transcoder))); | |
3963 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
3964 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
3965 | } | |
3966 | ||
003632d9 | 3967 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 DV |
3968 | { |
3969 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3970 | uint32_t temp; | |
3971 | ||
3972 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 3973 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
3974 | return; |
3975 | ||
3976 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
3977 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
3978 | ||
003632d9 ACO |
3979 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
3980 | if (enable) | |
3981 | temp |= FDI_BC_BIFURCATION_SELECT; | |
3982 | ||
3983 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
3984 | I915_WRITE(SOUTH_CHICKEN1, temp); |
3985 | POSTING_READ(SOUTH_CHICKEN1); | |
3986 | } | |
3987 | ||
3988 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
3989 | { | |
3990 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
3991 | |
3992 | switch (intel_crtc->pipe) { | |
3993 | case PIPE_A: | |
3994 | break; | |
3995 | case PIPE_B: | |
6e3c9717 | 3996 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 3997 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 3998 | else |
003632d9 | 3999 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4000 | |
4001 | break; | |
4002 | case PIPE_C: | |
003632d9 | 4003 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4004 | |
4005 | break; | |
4006 | default: | |
4007 | BUG(); | |
4008 | } | |
4009 | } | |
4010 | ||
c48b5305 VS |
4011 | /* Return which DP Port should be selected for Transcoder DP control */ |
4012 | static enum port | |
4013 | intel_trans_dp_port_sel(struct drm_crtc *crtc) | |
4014 | { | |
4015 | struct drm_device *dev = crtc->dev; | |
4016 | struct intel_encoder *encoder; | |
4017 | ||
4018 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
4019 | if (encoder->type == INTEL_OUTPUT_DISPLAYPORT || | |
4020 | encoder->type == INTEL_OUTPUT_EDP) | |
4021 | return enc_to_dig_port(&encoder->base)->port; | |
4022 | } | |
4023 | ||
4024 | return -1; | |
4025 | } | |
4026 | ||
f67a559d JB |
4027 | /* |
4028 | * Enable PCH resources required for PCH ports: | |
4029 | * - PCH PLLs | |
4030 | * - FDI training & RX/TX | |
4031 | * - update transcoder timings | |
4032 | * - DP transcoding bits | |
4033 | * - transcoder | |
4034 | */ | |
4035 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4036 | { |
4037 | struct drm_device *dev = crtc->dev; | |
4038 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4039 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4040 | int pipe = intel_crtc->pipe; | |
f0f59a00 | 4041 | u32 temp; |
2c07245f | 4042 | |
ab9412ba | 4043 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4044 | |
1fbc0d78 DV |
4045 | if (IS_IVYBRIDGE(dev)) |
4046 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
4047 | ||
cd986abb DV |
4048 | /* Write the TU size bits before fdi link training, so that error |
4049 | * detection works. */ | |
4050 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4051 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4052 | ||
c98e9dcf | 4053 | /* For PCH output, training FDI link */ |
674cf967 | 4054 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4055 | |
3ad8a208 DV |
4056 | /* We need to program the right clock selection before writing the pixel |
4057 | * mutliplier into the DPLL. */ | |
303b81e0 | 4058 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 4059 | u32 sel; |
4b645f14 | 4060 | |
c98e9dcf | 4061 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4062 | temp |= TRANS_DPLL_ENABLE(pipe); |
4063 | sel = TRANS_DPLLB_SEL(pipe); | |
8106ddbd ACO |
4064 | if (intel_crtc->config->shared_dpll == |
4065 | intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B)) | |
ee7b9f93 JB |
4066 | temp |= sel; |
4067 | else | |
4068 | temp &= ~sel; | |
c98e9dcf | 4069 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4070 | } |
5eddb70b | 4071 | |
3ad8a208 DV |
4072 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4073 | * transcoder, and we actually should do this to not upset any PCH | |
4074 | * transcoder that already use the clock when we share it. | |
4075 | * | |
4076 | * Note that enable_shared_dpll tries to do the right thing, but | |
4077 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4078 | * the right LVDS enable sequence. */ | |
85b3894f | 4079 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4080 | |
d9b6cb56 JB |
4081 | /* set transcoder timing, panel must allow it */ |
4082 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4083 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4084 | |
303b81e0 | 4085 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4086 | |
c98e9dcf | 4087 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e3c9717 | 4088 | if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { |
9c4edaee VS |
4089 | const struct drm_display_mode *adjusted_mode = |
4090 | &intel_crtc->config->base.adjusted_mode; | |
dfd07d72 | 4091 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
f0f59a00 | 4092 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
5eddb70b CW |
4093 | temp = I915_READ(reg); |
4094 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4095 | TRANS_DP_SYNC_MASK | |
4096 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4097 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4098 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf | 4099 | |
9c4edaee | 4100 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
5eddb70b | 4101 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
9c4edaee | 4102 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4103 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4104 | |
4105 | switch (intel_trans_dp_port_sel(crtc)) { | |
c48b5305 | 4106 | case PORT_B: |
5eddb70b | 4107 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 4108 | break; |
c48b5305 | 4109 | case PORT_C: |
5eddb70b | 4110 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf | 4111 | break; |
c48b5305 | 4112 | case PORT_D: |
5eddb70b | 4113 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4114 | break; |
4115 | default: | |
e95d41e1 | 4116 | BUG(); |
32f9d658 | 4117 | } |
2c07245f | 4118 | |
5eddb70b | 4119 | I915_WRITE(reg, temp); |
6be4a607 | 4120 | } |
b52eb4dc | 4121 | |
b8a4f404 | 4122 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4123 | } |
4124 | ||
1507e5bd PZ |
4125 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4126 | { | |
4127 | struct drm_device *dev = crtc->dev; | |
4128 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4129 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6e3c9717 | 4130 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4131 | |
ab9412ba | 4132 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4133 | |
8c52b5e8 | 4134 | lpt_program_iclkip(crtc); |
1507e5bd | 4135 | |
0540e488 | 4136 | /* Set transcoder timing. */ |
275f01b2 | 4137 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4138 | |
937bb610 | 4139 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4140 | } |
4141 | ||
a1520318 | 4142 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
4143 | { |
4144 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 4145 | i915_reg_t dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4146 | u32 temp; |
4147 | ||
4148 | temp = I915_READ(dslreg); | |
4149 | udelay(500); | |
4150 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4151 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4152 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4153 | } |
4154 | } | |
4155 | ||
86adf9d7 ML |
4156 | static int |
4157 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
4158 | unsigned scaler_user, int *scaler_id, unsigned int rotation, | |
4159 | int src_w, int src_h, int dst_w, int dst_h) | |
a1b2278e | 4160 | { |
86adf9d7 ML |
4161 | struct intel_crtc_scaler_state *scaler_state = |
4162 | &crtc_state->scaler_state; | |
4163 | struct intel_crtc *intel_crtc = | |
4164 | to_intel_crtc(crtc_state->base.crtc); | |
a1b2278e | 4165 | int need_scaling; |
6156a456 CK |
4166 | |
4167 | need_scaling = intel_rotation_90_or_270(rotation) ? | |
4168 | (src_h != dst_w || src_w != dst_h): | |
4169 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4170 | |
4171 | /* | |
4172 | * if plane is being disabled or scaler is no more required or force detach | |
4173 | * - free scaler binded to this plane/crtc | |
4174 | * - in order to do this, update crtc->scaler_usage | |
4175 | * | |
4176 | * Here scaler state in crtc_state is set free so that | |
4177 | * scaler can be assigned to other user. Actual register | |
4178 | * update to free the scaler is done in plane/panel-fit programming. | |
4179 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4180 | */ | |
86adf9d7 | 4181 | if (force_detach || !need_scaling) { |
a1b2278e | 4182 | if (*scaler_id >= 0) { |
86adf9d7 | 4183 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4184 | scaler_state->scalers[*scaler_id].in_use = 0; |
4185 | ||
86adf9d7 ML |
4186 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4187 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4188 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4189 | scaler_state->scaler_users); |
4190 | *scaler_id = -1; | |
4191 | } | |
4192 | return 0; | |
4193 | } | |
4194 | ||
4195 | /* range checks */ | |
4196 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4197 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4198 | ||
4199 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4200 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4201 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4202 | "size is out of scaler range\n", |
86adf9d7 | 4203 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4204 | return -EINVAL; |
4205 | } | |
4206 | ||
86adf9d7 ML |
4207 | /* mark this plane as a scaler user in crtc_state */ |
4208 | scaler_state->scaler_users |= (1 << scaler_user); | |
4209 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4210 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4211 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4212 | scaler_state->scaler_users); | |
4213 | ||
4214 | return 0; | |
4215 | } | |
4216 | ||
4217 | /** | |
4218 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4219 | * | |
4220 | * @state: crtc's scaler state | |
86adf9d7 ML |
4221 | * |
4222 | * Return | |
4223 | * 0 - scaler_usage updated successfully | |
4224 | * error - requested scaling cannot be supported or other error condition | |
4225 | */ | |
e435d6e5 | 4226 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 ML |
4227 | { |
4228 | struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); | |
7c5f93b0 | 4229 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
86adf9d7 ML |
4230 | |
4231 | DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n", | |
4232 | intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX); | |
4233 | ||
e435d6e5 | 4234 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
fa5a7970 | 4235 | &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0), |
86adf9d7 | 4236 | state->pipe_src_w, state->pipe_src_h, |
aad941d5 | 4237 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
86adf9d7 ML |
4238 | } |
4239 | ||
4240 | /** | |
4241 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4242 | * | |
4243 | * @state: crtc's scaler state | |
86adf9d7 ML |
4244 | * @plane_state: atomic plane state to update |
4245 | * | |
4246 | * Return | |
4247 | * 0 - scaler_usage updated successfully | |
4248 | * error - requested scaling cannot be supported or other error condition | |
4249 | */ | |
da20eabd ML |
4250 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4251 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4252 | { |
4253 | ||
4254 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
da20eabd ML |
4255 | struct intel_plane *intel_plane = |
4256 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4257 | struct drm_framebuffer *fb = plane_state->base.fb; |
4258 | int ret; | |
4259 | ||
4260 | bool force_detach = !fb || !plane_state->visible; | |
4261 | ||
4262 | DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n", | |
4263 | intel_plane->base.base.id, intel_crtc->pipe, | |
4264 | drm_plane_index(&intel_plane->base)); | |
4265 | ||
4266 | ret = skl_update_scaler(crtc_state, force_detach, | |
4267 | drm_plane_index(&intel_plane->base), | |
4268 | &plane_state->scaler_id, | |
4269 | plane_state->base.rotation, | |
4270 | drm_rect_width(&plane_state->src) >> 16, | |
4271 | drm_rect_height(&plane_state->src) >> 16, | |
4272 | drm_rect_width(&plane_state->dst), | |
4273 | drm_rect_height(&plane_state->dst)); | |
4274 | ||
4275 | if (ret || plane_state->scaler_id < 0) | |
4276 | return ret; | |
4277 | ||
a1b2278e | 4278 | /* check colorkey */ |
818ed961 | 4279 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
86adf9d7 | 4280 | DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed", |
818ed961 | 4281 | intel_plane->base.base.id); |
a1b2278e CK |
4282 | return -EINVAL; |
4283 | } | |
4284 | ||
4285 | /* Check src format */ | |
86adf9d7 ML |
4286 | switch (fb->pixel_format) { |
4287 | case DRM_FORMAT_RGB565: | |
4288 | case DRM_FORMAT_XBGR8888: | |
4289 | case DRM_FORMAT_XRGB8888: | |
4290 | case DRM_FORMAT_ABGR8888: | |
4291 | case DRM_FORMAT_ARGB8888: | |
4292 | case DRM_FORMAT_XRGB2101010: | |
4293 | case DRM_FORMAT_XBGR2101010: | |
4294 | case DRM_FORMAT_YUYV: | |
4295 | case DRM_FORMAT_YVYU: | |
4296 | case DRM_FORMAT_UYVY: | |
4297 | case DRM_FORMAT_VYUY: | |
4298 | break; | |
4299 | default: | |
4300 | DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n", | |
4301 | intel_plane->base.base.id, fb->base.id, fb->pixel_format); | |
4302 | return -EINVAL; | |
a1b2278e CK |
4303 | } |
4304 | ||
a1b2278e CK |
4305 | return 0; |
4306 | } | |
4307 | ||
e435d6e5 ML |
4308 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4309 | { | |
4310 | int i; | |
4311 | ||
4312 | for (i = 0; i < crtc->num_scalers; i++) | |
4313 | skl_detach_scaler(crtc, i); | |
4314 | } | |
4315 | ||
4316 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4317 | { |
4318 | struct drm_device *dev = crtc->base.dev; | |
4319 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4320 | int pipe = crtc->pipe; | |
a1b2278e CK |
4321 | struct intel_crtc_scaler_state *scaler_state = |
4322 | &crtc->config->scaler_state; | |
4323 | ||
4324 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4325 | ||
6e3c9717 | 4326 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4327 | int id; |
4328 | ||
4329 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4330 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4331 | return; | |
4332 | } | |
4333 | ||
4334 | id = scaler_state->scaler_id; | |
4335 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4336 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4337 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4338 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4339 | ||
4340 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4341 | } |
4342 | } | |
4343 | ||
b074cec8 JB |
4344 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4345 | { | |
4346 | struct drm_device *dev = crtc->base.dev; | |
4347 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4348 | int pipe = crtc->pipe; | |
4349 | ||
6e3c9717 | 4350 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4351 | /* Force use of hard-coded filter coefficients |
4352 | * as some pre-programmed values are broken, | |
4353 | * e.g. x201. | |
4354 | */ | |
4355 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4356 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4357 | PF_PIPE_SEL_IVB(pipe)); | |
4358 | else | |
4359 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4360 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4361 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4362 | } |
4363 | } | |
4364 | ||
20bc8673 | 4365 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4366 | { |
cea165c3 VS |
4367 | struct drm_device *dev = crtc->base.dev; |
4368 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 | 4369 | |
6e3c9717 | 4370 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4371 | return; |
4372 | ||
307e4498 ML |
4373 | /* |
4374 | * We can only enable IPS after we enable a plane and wait for a vblank | |
4375 | * This function is called from post_plane_update, which is run after | |
4376 | * a vblank wait. | |
4377 | */ | |
cea165c3 | 4378 | |
d77e4531 | 4379 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4380 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4381 | mutex_lock(&dev_priv->rps.hw_lock); |
4382 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4383 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4384 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4385 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4386 | * mailbox." Moreover, the mailbox may return a bogus state, |
4387 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4388 | */ |
4389 | } else { | |
4390 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4391 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4392 | * is essentially intel_wait_for_vblank. If we don't have this | |
4393 | * and don't wait for vblanks until the end of crtc_enable, then | |
4394 | * the HW state readout code will complain that the expected | |
4395 | * IPS_CTL value is not the one we read. */ | |
4396 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
4397 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
4398 | } | |
d77e4531 PZ |
4399 | } |
4400 | ||
20bc8673 | 4401 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4402 | { |
4403 | struct drm_device *dev = crtc->base.dev; | |
4404 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4405 | ||
6e3c9717 | 4406 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4407 | return; |
4408 | ||
4409 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4410 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4411 | mutex_lock(&dev_priv->rps.hw_lock); |
4412 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4413 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
4414 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
4415 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
4416 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 4417 | } else { |
2a114cc1 | 4418 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4419 | POSTING_READ(IPS_CTL); |
4420 | } | |
d77e4531 PZ |
4421 | |
4422 | /* We need to wait for a vblank before we can disable the plane. */ | |
4423 | intel_wait_for_vblank(dev, crtc->pipe); | |
4424 | } | |
4425 | ||
7cac945f | 4426 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4427 | { |
7cac945f | 4428 | if (intel_crtc->overlay) { |
d3eedb1a VS |
4429 | struct drm_device *dev = intel_crtc->base.dev; |
4430 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4431 | ||
4432 | mutex_lock(&dev->struct_mutex); | |
4433 | dev_priv->mm.interruptible = false; | |
4434 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4435 | dev_priv->mm.interruptible = true; | |
4436 | mutex_unlock(&dev->struct_mutex); | |
4437 | } | |
4438 | ||
4439 | /* Let userspace switch the overlay on again. In most cases userspace | |
4440 | * has to recompute where to put it anyway. | |
4441 | */ | |
4442 | } | |
4443 | ||
87d4300a ML |
4444 | /** |
4445 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4446 | * @crtc: the CRTC whose primary plane was just enabled | |
4447 | * | |
4448 | * Performs potentially sleeping operations that must be done after the primary | |
4449 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4450 | * called due to an explicit primary plane update, or due to an implicit | |
4451 | * re-enable that is caused when a sprite plane is updated to no longer | |
4452 | * completely hide the primary plane. | |
4453 | */ | |
4454 | static void | |
4455 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4456 | { |
4457 | struct drm_device *dev = crtc->dev; | |
87d4300a | 4458 | struct drm_i915_private *dev_priv = dev->dev_private; |
a5c4d7bc VS |
4459 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4460 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4461 | |
87d4300a ML |
4462 | /* |
4463 | * FIXME IPS should be fine as long as one plane is | |
4464 | * enabled, but in practice it seems to have problems | |
4465 | * when going from primary only to sprite only and vice | |
4466 | * versa. | |
4467 | */ | |
a5c4d7bc VS |
4468 | hsw_enable_ips(intel_crtc); |
4469 | ||
f99d7069 | 4470 | /* |
87d4300a ML |
4471 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4472 | * So don't enable underrun reporting before at least some planes | |
4473 | * are enabled. | |
4474 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4475 | * but leave the pipe running. | |
f99d7069 | 4476 | */ |
87d4300a ML |
4477 | if (IS_GEN2(dev)) |
4478 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4479 | ||
aca7b684 VS |
4480 | /* Underruns don't always raise interrupts, so check manually. */ |
4481 | intel_check_cpu_fifo_underruns(dev_priv); | |
4482 | intel_check_pch_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4483 | } |
4484 | ||
2622a081 | 4485 | /* FIXME move all this to pre_plane_update() with proper state tracking */ |
87d4300a ML |
4486 | static void |
4487 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4488 | { |
4489 | struct drm_device *dev = crtc->dev; | |
4490 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4491 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4492 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4493 | |
87d4300a ML |
4494 | /* |
4495 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4496 | * So diasble underrun reporting before all the planes get disabled. | |
4497 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4498 | * but leave the pipe running. | |
4499 | */ | |
4500 | if (IS_GEN2(dev)) | |
4501 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
a5c4d7bc | 4502 | |
2622a081 VS |
4503 | /* |
4504 | * FIXME IPS should be fine as long as one plane is | |
4505 | * enabled, but in practice it seems to have problems | |
4506 | * when going from primary only to sprite only and vice | |
4507 | * versa. | |
4508 | */ | |
4509 | hsw_disable_ips(intel_crtc); | |
4510 | } | |
4511 | ||
4512 | /* FIXME get rid of this and use pre_plane_update */ | |
4513 | static void | |
4514 | intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) | |
4515 | { | |
4516 | struct drm_device *dev = crtc->dev; | |
4517 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4518 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4519 | int pipe = intel_crtc->pipe; | |
4520 | ||
4521 | intel_pre_disable_primary(crtc); | |
4522 | ||
87d4300a ML |
4523 | /* |
4524 | * Vblank time updates from the shadow to live plane control register | |
4525 | * are blocked if the memory self-refresh mode is active at that | |
4526 | * moment. So to make sure the plane gets truly disabled, disable | |
4527 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4528 | * will be checked/applied by the HW only at the next frame start | |
4529 | * event which is after the vblank start event, so we need to have a | |
4530 | * wait-for-vblank between disabling the plane and the pipe. | |
4531 | */ | |
262cd2e1 | 4532 | if (HAS_GMCH_DISPLAY(dev)) { |
87d4300a | 4533 | intel_set_memory_cxsr(dev_priv, false); |
262cd2e1 VS |
4534 | dev_priv->wm.vlv.cxsr = false; |
4535 | intel_wait_for_vblank(dev, pipe); | |
4536 | } | |
87d4300a ML |
4537 | } |
4538 | ||
5c74cd73 | 4539 | static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state) |
ac21b225 | 4540 | { |
5c74cd73 | 4541 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
ac21b225 | 4542 | struct drm_device *dev = crtc->base.dev; |
eddfcbcd | 4543 | struct drm_i915_private *dev_priv = dev->dev_private; |
ab1d3a0e ML |
4544 | struct intel_crtc_state *pipe_config = |
4545 | to_intel_crtc_state(crtc->base.state); | |
5c74cd73 ML |
4546 | struct drm_atomic_state *old_state = old_crtc_state->base.state; |
4547 | struct drm_plane *primary = crtc->base.primary; | |
4548 | struct drm_plane_state *old_pri_state = | |
4549 | drm_atomic_get_existing_plane_state(old_state, primary); | |
4550 | bool modeset = needs_modeset(&pipe_config->base); | |
ac21b225 | 4551 | |
5c74cd73 ML |
4552 | if (old_pri_state) { |
4553 | struct intel_plane_state *primary_state = | |
4554 | to_intel_plane_state(primary->state); | |
4555 | struct intel_plane_state *old_primary_state = | |
4556 | to_intel_plane_state(old_pri_state); | |
4557 | ||
2099deff | 4558 | intel_fbc_pre_update(crtc, pipe_config, primary_state); |
31ae71fc | 4559 | |
5c74cd73 ML |
4560 | if (old_primary_state->visible && |
4561 | (modeset || !primary_state->visible)) | |
4562 | intel_pre_disable_primary(&crtc->base); | |
4563 | } | |
852eb00d | 4564 | |
ab1d3a0e | 4565 | if (pipe_config->disable_cxsr) { |
852eb00d | 4566 | crtc->wm.cxsr_allowed = false; |
2dfd178d | 4567 | |
2622a081 VS |
4568 | /* |
4569 | * Vblank time updates from the shadow to live plane control register | |
4570 | * are blocked if the memory self-refresh mode is active at that | |
4571 | * moment. So to make sure the plane gets truly disabled, disable | |
4572 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4573 | * will be checked/applied by the HW only at the next frame start | |
4574 | * event which is after the vblank start event, so we need to have a | |
4575 | * wait-for-vblank between disabling the plane and the pipe. | |
4576 | */ | |
4577 | if (old_crtc_state->base.active) { | |
2dfd178d | 4578 | intel_set_memory_cxsr(dev_priv, false); |
2622a081 VS |
4579 | dev_priv->wm.vlv.cxsr = false; |
4580 | intel_wait_for_vblank(dev, crtc->pipe); | |
4581 | } | |
852eb00d | 4582 | } |
92826fcd | 4583 | |
ed4a6a7c MR |
4584 | /* |
4585 | * IVB workaround: must disable low power watermarks for at least | |
4586 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
4587 | * when scaling is disabled. | |
4588 | * | |
4589 | * WaCxSRDisabledForSpriteScaling:ivb | |
4590 | */ | |
4591 | if (pipe_config->disable_lp_wm) { | |
4592 | ilk_disable_lp_wm(dev); | |
4593 | intel_wait_for_vblank(dev, crtc->pipe); | |
4594 | } | |
4595 | ||
4596 | /* | |
4597 | * If we're doing a modeset, we're done. No need to do any pre-vblank | |
4598 | * watermark programming here. | |
4599 | */ | |
4600 | if (needs_modeset(&pipe_config->base)) | |
4601 | return; | |
4602 | ||
4603 | /* | |
4604 | * For platforms that support atomic watermarks, program the | |
4605 | * 'intermediate' watermarks immediately. On pre-gen9 platforms, these | |
4606 | * will be the intermediate values that are safe for both pre- and | |
4607 | * post- vblank; when vblank happens, the 'active' values will be set | |
4608 | * to the final 'target' values and we'll do this again to get the | |
4609 | * optimal watermarks. For gen9+ platforms, the values we program here | |
4610 | * will be the final target values which will get automatically latched | |
4611 | * at vblank time; no further programming will be necessary. | |
4612 | * | |
4613 | * If a platform hasn't been transitioned to atomic watermarks yet, | |
4614 | * we'll continue to update watermarks the old way, if flags tell | |
4615 | * us to. | |
4616 | */ | |
4617 | if (dev_priv->display.initial_watermarks != NULL) | |
4618 | dev_priv->display.initial_watermarks(pipe_config); | |
caed361d | 4619 | else if (pipe_config->update_wm_pre) |
92826fcd | 4620 | intel_update_watermarks(&crtc->base); |
ac21b225 ML |
4621 | } |
4622 | ||
d032ffa0 | 4623 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
4624 | { |
4625 | struct drm_device *dev = crtc->dev; | |
4626 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 4627 | struct drm_plane *p; |
87d4300a ML |
4628 | int pipe = intel_crtc->pipe; |
4629 | ||
7cac945f | 4630 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 4631 | |
d032ffa0 ML |
4632 | drm_for_each_plane_mask(p, dev, plane_mask) |
4633 | to_intel_plane(p)->disable_plane(p, crtc); | |
f98551ae | 4634 | |
f99d7069 DV |
4635 | /* |
4636 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4637 | * to compute the mask of flip planes precisely. For the time being | |
4638 | * consider this a flip to a NULL plane. | |
4639 | */ | |
4640 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4641 | } |
4642 | ||
f67a559d JB |
4643 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4644 | { | |
4645 | struct drm_device *dev = crtc->dev; | |
4646 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4647 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4648 | struct intel_encoder *encoder; |
f67a559d | 4649 | int pipe = intel_crtc->pipe; |
b95c5321 ML |
4650 | struct intel_crtc_state *pipe_config = |
4651 | to_intel_crtc_state(crtc->state); | |
f67a559d | 4652 | |
53d9f4e9 | 4653 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
4654 | return; |
4655 | ||
b2c0593a VS |
4656 | /* |
4657 | * Sometimes spurious CPU pipe underruns happen during FDI | |
4658 | * training, at least with VGA+HDMI cloning. Suppress them. | |
4659 | * | |
4660 | * On ILK we get an occasional spurious CPU pipe underruns | |
4661 | * between eDP port A enable and vdd enable. Also PCH port | |
4662 | * enable seems to result in the occasional CPU pipe underrun. | |
4663 | * | |
4664 | * Spurious PCH underruns also occur during PCH enabling. | |
4665 | */ | |
4666 | if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv)) | |
4667 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
81b088ca VS |
4668 | if (intel_crtc->config->has_pch_encoder) |
4669 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
4670 | ||
6e3c9717 | 4671 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
4672 | intel_prepare_shared_dpll(intel_crtc); |
4673 | ||
6e3c9717 | 4674 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4675 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
4676 | |
4677 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 4678 | intel_set_pipe_src_size(intel_crtc); |
29407aab | 4679 | |
6e3c9717 | 4680 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 4681 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4682 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
4683 | } |
4684 | ||
4685 | ironlake_set_pipeconf(crtc); | |
4686 | ||
f67a559d | 4687 | intel_crtc->active = true; |
8664281b | 4688 | |
f6736a1a | 4689 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4690 | if (encoder->pre_enable) |
4691 | encoder->pre_enable(encoder); | |
f67a559d | 4692 | |
6e3c9717 | 4693 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
4694 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4695 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4696 | * enabling. */ | |
88cefb6c | 4697 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4698 | } else { |
4699 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4700 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4701 | } | |
f67a559d | 4702 | |
b074cec8 | 4703 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4704 | |
9c54c0dd JB |
4705 | /* |
4706 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4707 | * clocks enabled | |
4708 | */ | |
b95c5321 | 4709 | intel_color_load_luts(&pipe_config->base); |
9c54c0dd | 4710 | |
1d5bf5d9 ID |
4711 | if (dev_priv->display.initial_watermarks != NULL) |
4712 | dev_priv->display.initial_watermarks(intel_crtc->config); | |
e1fdc473 | 4713 | intel_enable_pipe(intel_crtc); |
f67a559d | 4714 | |
6e3c9717 | 4715 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 4716 | ironlake_pch_enable(crtc); |
c98e9dcf | 4717 | |
f9b61ff6 DV |
4718 | assert_vblank_disabled(crtc); |
4719 | drm_crtc_vblank_on(crtc); | |
4720 | ||
fa5c73b1 DV |
4721 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4722 | encoder->enable(encoder); | |
61b77ddd DV |
4723 | |
4724 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4725 | cpt_verify_modeset(dev, intel_crtc->pipe); |
37ca8d4c VS |
4726 | |
4727 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ | |
4728 | if (intel_crtc->config->has_pch_encoder) | |
4729 | intel_wait_for_vblank(dev, pipe); | |
b2c0593a | 4730 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
37ca8d4c | 4731 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 JB |
4732 | } |
4733 | ||
42db64ef PZ |
4734 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4735 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4736 | { | |
f5adf94e | 4737 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4738 | } |
4739 | ||
4f771f10 PZ |
4740 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4741 | { | |
4742 | struct drm_device *dev = crtc->dev; | |
4743 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4744 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4745 | struct intel_encoder *encoder; | |
99d736a2 | 4746 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4d1de975 | 4747 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
99d736a2 ML |
4748 | struct intel_crtc_state *pipe_config = |
4749 | to_intel_crtc_state(crtc->state); | |
4f771f10 | 4750 | |
53d9f4e9 | 4751 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
4752 | return; |
4753 | ||
81b088ca VS |
4754 | if (intel_crtc->config->has_pch_encoder) |
4755 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
4756 | false); | |
4757 | ||
8106ddbd | 4758 | if (intel_crtc->config->shared_dpll) |
df8ad70c DV |
4759 | intel_enable_shared_dpll(intel_crtc); |
4760 | ||
6e3c9717 | 4761 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4762 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 | 4763 | |
4d1de975 JN |
4764 | if (!intel_crtc->config->has_dsi_encoder) |
4765 | intel_set_pipe_timings(intel_crtc); | |
4766 | ||
bc58be60 | 4767 | intel_set_pipe_src_size(intel_crtc); |
229fca97 | 4768 | |
4d1de975 JN |
4769 | if (cpu_transcoder != TRANSCODER_EDP && |
4770 | !transcoder_is_dsi(cpu_transcoder)) { | |
4771 | I915_WRITE(PIPE_MULT(cpu_transcoder), | |
6e3c9717 | 4772 | intel_crtc->config->pixel_multiplier - 1); |
ebb69c95 CT |
4773 | } |
4774 | ||
6e3c9717 | 4775 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 4776 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4777 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
4778 | } |
4779 | ||
4d1de975 JN |
4780 | if (!intel_crtc->config->has_dsi_encoder) |
4781 | haswell_set_pipeconf(crtc); | |
4782 | ||
391bf048 | 4783 | haswell_set_pipemisc(crtc); |
229fca97 | 4784 | |
b95c5321 | 4785 | intel_color_set_csc(&pipe_config->base); |
229fca97 | 4786 | |
4f771f10 | 4787 | intel_crtc->active = true; |
8664281b | 4788 | |
6b698516 DV |
4789 | if (intel_crtc->config->has_pch_encoder) |
4790 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
4791 | else | |
4792 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4793 | ||
7d4aefd0 | 4794 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 PZ |
4795 | if (encoder->pre_enable) |
4796 | encoder->pre_enable(encoder); | |
7d4aefd0 | 4797 | } |
4f771f10 | 4798 | |
d2d65408 | 4799 | if (intel_crtc->config->has_pch_encoder) |
4fe9467d | 4800 | dev_priv->display.fdi_link_train(crtc); |
4fe9467d | 4801 | |
a65347ba | 4802 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 4803 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 4804 | |
1c132b44 | 4805 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 4806 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 4807 | else |
1c132b44 | 4808 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
4809 | |
4810 | /* | |
4811 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4812 | * clocks enabled | |
4813 | */ | |
b95c5321 | 4814 | intel_color_load_luts(&pipe_config->base); |
4f771f10 | 4815 | |
1f544388 | 4816 | intel_ddi_set_pipe_settings(crtc); |
a65347ba | 4817 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 4818 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 4819 | |
1d5bf5d9 ID |
4820 | if (dev_priv->display.initial_watermarks != NULL) |
4821 | dev_priv->display.initial_watermarks(pipe_config); | |
4822 | else | |
4823 | intel_update_watermarks(crtc); | |
4d1de975 JN |
4824 | |
4825 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ | |
4826 | if (!intel_crtc->config->has_dsi_encoder) | |
4827 | intel_enable_pipe(intel_crtc); | |
42db64ef | 4828 | |
6e3c9717 | 4829 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 4830 | lpt_pch_enable(crtc); |
4f771f10 | 4831 | |
a65347ba | 4832 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
4833 | intel_ddi_set_vc_payload_alloc(crtc, true); |
4834 | ||
f9b61ff6 DV |
4835 | assert_vblank_disabled(crtc); |
4836 | drm_crtc_vblank_on(crtc); | |
4837 | ||
8807e55b | 4838 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 4839 | encoder->enable(encoder); |
8807e55b JN |
4840 | intel_opregion_notify_encoder(encoder, true); |
4841 | } | |
4f771f10 | 4842 | |
6b698516 DV |
4843 | if (intel_crtc->config->has_pch_encoder) { |
4844 | intel_wait_for_vblank(dev, pipe); | |
4845 | intel_wait_for_vblank(dev, pipe); | |
4846 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
d2d65408 VS |
4847 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
4848 | true); | |
6b698516 | 4849 | } |
d2d65408 | 4850 | |
e4916946 PZ |
4851 | /* If we change the relative order between pipe/planes enabling, we need |
4852 | * to change the workaround. */ | |
99d736a2 ML |
4853 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
4854 | if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) { | |
4855 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
4856 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
4857 | } | |
4f771f10 PZ |
4858 | } |
4859 | ||
bfd16b2a | 4860 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
4861 | { |
4862 | struct drm_device *dev = crtc->base.dev; | |
4863 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4864 | int pipe = crtc->pipe; | |
4865 | ||
4866 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
4867 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 4868 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
4869 | I915_WRITE(PF_CTL(pipe), 0); |
4870 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
4871 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
4872 | } | |
4873 | } | |
4874 | ||
6be4a607 JB |
4875 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
4876 | { | |
4877 | struct drm_device *dev = crtc->dev; | |
4878 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4879 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4880 | struct intel_encoder *encoder; |
6be4a607 | 4881 | int pipe = intel_crtc->pipe; |
b52eb4dc | 4882 | |
b2c0593a VS |
4883 | /* |
4884 | * Sometimes spurious CPU pipe underruns happen when the | |
4885 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
4886 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
4887 | */ | |
4888 | if (intel_crtc->config->has_pch_encoder) { | |
4889 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
37ca8d4c | 4890 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
b2c0593a | 4891 | } |
37ca8d4c | 4892 | |
ea9d758d DV |
4893 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4894 | encoder->disable(encoder); | |
4895 | ||
f9b61ff6 DV |
4896 | drm_crtc_vblank_off(crtc); |
4897 | assert_vblank_disabled(crtc); | |
4898 | ||
575f7ab7 | 4899 | intel_disable_pipe(intel_crtc); |
32f9d658 | 4900 | |
bfd16b2a | 4901 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 4902 | |
b2c0593a | 4903 | if (intel_crtc->config->has_pch_encoder) |
5a74f70a VS |
4904 | ironlake_fdi_disable(crtc); |
4905 | ||
bf49ec8c DV |
4906 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4907 | if (encoder->post_disable) | |
4908 | encoder->post_disable(encoder); | |
2c07245f | 4909 | |
6e3c9717 | 4910 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 4911 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 4912 | |
d925c59a | 4913 | if (HAS_PCH_CPT(dev)) { |
f0f59a00 VS |
4914 | i915_reg_t reg; |
4915 | u32 temp; | |
4916 | ||
d925c59a DV |
4917 | /* disable TRANS_DP_CTL */ |
4918 | reg = TRANS_DP_CTL(pipe); | |
4919 | temp = I915_READ(reg); | |
4920 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
4921 | TRANS_DP_PORT_SEL_MASK); | |
4922 | temp |= TRANS_DP_PORT_SEL_NONE; | |
4923 | I915_WRITE(reg, temp); | |
4924 | ||
4925 | /* disable DPLL_SEL */ | |
4926 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 4927 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 4928 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 4929 | } |
e3421a18 | 4930 | |
d925c59a DV |
4931 | ironlake_fdi_pll_disable(intel_crtc); |
4932 | } | |
81b088ca | 4933 | |
b2c0593a | 4934 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
81b088ca | 4935 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 | 4936 | } |
1b3c7a47 | 4937 | |
4f771f10 | 4938 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 4939 | { |
4f771f10 PZ |
4940 | struct drm_device *dev = crtc->dev; |
4941 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 4942 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 4943 | struct intel_encoder *encoder; |
6e3c9717 | 4944 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 4945 | |
d2d65408 VS |
4946 | if (intel_crtc->config->has_pch_encoder) |
4947 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
4948 | false); | |
4949 | ||
8807e55b JN |
4950 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4951 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 4952 | encoder->disable(encoder); |
8807e55b | 4953 | } |
4f771f10 | 4954 | |
f9b61ff6 DV |
4955 | drm_crtc_vblank_off(crtc); |
4956 | assert_vblank_disabled(crtc); | |
4957 | ||
4d1de975 JN |
4958 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ |
4959 | if (!intel_crtc->config->has_dsi_encoder) | |
4960 | intel_disable_pipe(intel_crtc); | |
4f771f10 | 4961 | |
6e3c9717 | 4962 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
4963 | intel_ddi_set_vc_payload_alloc(crtc, false); |
4964 | ||
a65347ba | 4965 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 4966 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 4967 | |
1c132b44 | 4968 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 4969 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 4970 | else |
bfd16b2a | 4971 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 4972 | |
a65347ba | 4973 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 4974 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 4975 | |
97b040aa ID |
4976 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4977 | if (encoder->post_disable) | |
4978 | encoder->post_disable(encoder); | |
81b088ca | 4979 | |
92966a37 VS |
4980 | if (intel_crtc->config->has_pch_encoder) { |
4981 | lpt_disable_pch_transcoder(dev_priv); | |
503a74e9 | 4982 | lpt_disable_iclkip(dev_priv); |
92966a37 VS |
4983 | intel_ddi_fdi_disable(crtc); |
4984 | ||
81b088ca VS |
4985 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
4986 | true); | |
92966a37 | 4987 | } |
4f771f10 PZ |
4988 | } |
4989 | ||
2dd24552 JB |
4990 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
4991 | { | |
4992 | struct drm_device *dev = crtc->base.dev; | |
4993 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 4994 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 4995 | |
681a8504 | 4996 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
4997 | return; |
4998 | ||
2dd24552 | 4999 | /* |
c0b03411 DV |
5000 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5001 | * according to register description and PRM. | |
2dd24552 | 5002 | */ |
c0b03411 DV |
5003 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5004 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5005 | |
b074cec8 JB |
5006 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5007 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5008 | |
5009 | /* Border color in case we don't scale up to the full screen. Black by | |
5010 | * default, change to something else for debugging. */ | |
5011 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5012 | } |
5013 | ||
d05410f9 DA |
5014 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5015 | { | |
5016 | switch (port) { | |
5017 | case PORT_A: | |
6331a704 | 5018 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
d05410f9 | 5019 | case PORT_B: |
6331a704 | 5020 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
d05410f9 | 5021 | case PORT_C: |
6331a704 | 5022 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
d05410f9 | 5023 | case PORT_D: |
6331a704 | 5024 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
d8e19f99 | 5025 | case PORT_E: |
6331a704 | 5026 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
d05410f9 | 5027 | default: |
b9fec167 | 5028 | MISSING_CASE(port); |
d05410f9 DA |
5029 | return POWER_DOMAIN_PORT_OTHER; |
5030 | } | |
5031 | } | |
5032 | ||
25f78f58 VS |
5033 | static enum intel_display_power_domain port_to_aux_power_domain(enum port port) |
5034 | { | |
5035 | switch (port) { | |
5036 | case PORT_A: | |
5037 | return POWER_DOMAIN_AUX_A; | |
5038 | case PORT_B: | |
5039 | return POWER_DOMAIN_AUX_B; | |
5040 | case PORT_C: | |
5041 | return POWER_DOMAIN_AUX_C; | |
5042 | case PORT_D: | |
5043 | return POWER_DOMAIN_AUX_D; | |
5044 | case PORT_E: | |
5045 | /* FIXME: Check VBT for actual wiring of PORT E */ | |
5046 | return POWER_DOMAIN_AUX_D; | |
5047 | default: | |
b9fec167 | 5048 | MISSING_CASE(port); |
25f78f58 VS |
5049 | return POWER_DOMAIN_AUX_A; |
5050 | } | |
5051 | } | |
5052 | ||
319be8ae ID |
5053 | enum intel_display_power_domain |
5054 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5055 | { | |
5056 | struct drm_device *dev = intel_encoder->base.dev; | |
5057 | struct intel_digital_port *intel_dig_port; | |
5058 | ||
5059 | switch (intel_encoder->type) { | |
5060 | case INTEL_OUTPUT_UNKNOWN: | |
5061 | /* Only DDI platforms should ever use this output type */ | |
5062 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
5063 | case INTEL_OUTPUT_DISPLAYPORT: | |
5064 | case INTEL_OUTPUT_HDMI: | |
5065 | case INTEL_OUTPUT_EDP: | |
5066 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 5067 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
5068 | case INTEL_OUTPUT_DP_MST: |
5069 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5070 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
5071 | case INTEL_OUTPUT_ANALOG: |
5072 | return POWER_DOMAIN_PORT_CRT; | |
5073 | case INTEL_OUTPUT_DSI: | |
5074 | return POWER_DOMAIN_PORT_DSI; | |
5075 | default: | |
5076 | return POWER_DOMAIN_PORT_OTHER; | |
5077 | } | |
5078 | } | |
5079 | ||
25f78f58 VS |
5080 | enum intel_display_power_domain |
5081 | intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder) | |
5082 | { | |
5083 | struct drm_device *dev = intel_encoder->base.dev; | |
5084 | struct intel_digital_port *intel_dig_port; | |
5085 | ||
5086 | switch (intel_encoder->type) { | |
5087 | case INTEL_OUTPUT_UNKNOWN: | |
651174a4 ID |
5088 | case INTEL_OUTPUT_HDMI: |
5089 | /* | |
5090 | * Only DDI platforms should ever use these output types. | |
5091 | * We can get here after the HDMI detect code has already set | |
5092 | * the type of the shared encoder. Since we can't be sure | |
5093 | * what's the status of the given connectors, play safe and | |
5094 | * run the DP detection too. | |
5095 | */ | |
25f78f58 VS |
5096 | WARN_ON_ONCE(!HAS_DDI(dev)); |
5097 | case INTEL_OUTPUT_DISPLAYPORT: | |
5098 | case INTEL_OUTPUT_EDP: | |
5099 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
5100 | return port_to_aux_power_domain(intel_dig_port->port); | |
5101 | case INTEL_OUTPUT_DP_MST: | |
5102 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5103 | return port_to_aux_power_domain(intel_dig_port->port); | |
5104 | default: | |
b9fec167 | 5105 | MISSING_CASE(intel_encoder->type); |
25f78f58 VS |
5106 | return POWER_DOMAIN_AUX_A; |
5107 | } | |
5108 | } | |
5109 | ||
74bff5f9 ML |
5110 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc, |
5111 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5112 | { |
319be8ae | 5113 | struct drm_device *dev = crtc->dev; |
74bff5f9 | 5114 | struct drm_encoder *encoder; |
319be8ae ID |
5115 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5116 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca | 5117 | unsigned long mask; |
74bff5f9 | 5118 | enum transcoder transcoder = crtc_state->cpu_transcoder; |
77d22dca | 5119 | |
74bff5f9 | 5120 | if (!crtc_state->base.active) |
292b990e ML |
5121 | return 0; |
5122 | ||
77d22dca ID |
5123 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5124 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
74bff5f9 ML |
5125 | if (crtc_state->pch_pfit.enabled || |
5126 | crtc_state->pch_pfit.force_thru) | |
77d22dca ID |
5127 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5128 | ||
74bff5f9 ML |
5129 | drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) { |
5130 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
5131 | ||
319be8ae | 5132 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); |
74bff5f9 | 5133 | } |
319be8ae | 5134 | |
15e7ec29 ML |
5135 | if (crtc_state->shared_dpll) |
5136 | mask |= BIT(POWER_DOMAIN_PLLS); | |
5137 | ||
77d22dca ID |
5138 | return mask; |
5139 | } | |
5140 | ||
74bff5f9 ML |
5141 | static unsigned long |
5142 | modeset_get_crtc_power_domains(struct drm_crtc *crtc, | |
5143 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5144 | { |
292b990e ML |
5145 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
5146 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5147 | enum intel_display_power_domain domain; | |
a6747b73 | 5148 | unsigned long domains, new_domains, old_domains, ms_domain = 0; |
77d22dca | 5149 | |
292b990e | 5150 | old_domains = intel_crtc->enabled_power_domains; |
74bff5f9 ML |
5151 | intel_crtc->enabled_power_domains = new_domains = |
5152 | get_crtc_power_domains(crtc, crtc_state); | |
77d22dca | 5153 | |
a6747b73 ML |
5154 | if (needs_modeset(&crtc_state->base)) |
5155 | ms_domain = BIT(POWER_DOMAIN_MODESET); | |
5156 | ||
5157 | domains = (new_domains & ~old_domains) | ms_domain; | |
292b990e ML |
5158 | |
5159 | for_each_power_domain(domain, domains) | |
5160 | intel_display_power_get(dev_priv, domain); | |
5161 | ||
a6747b73 | 5162 | return (old_domains & ~new_domains) | ms_domain; |
292b990e ML |
5163 | } |
5164 | ||
5165 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
5166 | unsigned long domains) | |
5167 | { | |
5168 | enum intel_display_power_domain domain; | |
5169 | ||
5170 | for_each_power_domain(domain, domains) | |
5171 | intel_display_power_put(dev_priv, domain); | |
5172 | } | |
77d22dca | 5173 | |
adafdc6f MK |
5174 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
5175 | { | |
5176 | int max_cdclk_freq = dev_priv->max_cdclk_freq; | |
5177 | ||
5178 | if (INTEL_INFO(dev_priv)->gen >= 9 || | |
5179 | IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
5180 | return max_cdclk_freq; | |
5181 | else if (IS_CHERRYVIEW(dev_priv)) | |
5182 | return max_cdclk_freq*95/100; | |
5183 | else if (INTEL_INFO(dev_priv)->gen < 4) | |
5184 | return 2*max_cdclk_freq*90/100; | |
5185 | else | |
5186 | return max_cdclk_freq*90/100; | |
5187 | } | |
5188 | ||
b2045352 VS |
5189 | static int skl_calc_cdclk(int max_pixclk, int vco); |
5190 | ||
560a7ae4 DL |
5191 | static void intel_update_max_cdclk(struct drm_device *dev) |
5192 | { | |
5193 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5194 | ||
ef11bdb3 | 5195 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
560a7ae4 | 5196 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; |
b2045352 VS |
5197 | int max_cdclk, vco; |
5198 | ||
5199 | vco = dev_priv->skl_preferred_vco_freq; | |
63911d72 | 5200 | WARN_ON(vco != 8100000 && vco != 8640000); |
560a7ae4 | 5201 | |
b2045352 VS |
5202 | /* |
5203 | * Use the lower (vco 8640) cdclk values as a | |
5204 | * first guess. skl_calc_cdclk() will correct it | |
5205 | * if the preferred vco is 8100 instead. | |
5206 | */ | |
560a7ae4 | 5207 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) |
487ed2e4 | 5208 | max_cdclk = 617143; |
560a7ae4 | 5209 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) |
b2045352 | 5210 | max_cdclk = 540000; |
560a7ae4 | 5211 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) |
b2045352 | 5212 | max_cdclk = 432000; |
560a7ae4 | 5213 | else |
487ed2e4 | 5214 | max_cdclk = 308571; |
b2045352 VS |
5215 | |
5216 | dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); | |
281c114f MR |
5217 | } else if (IS_BROXTON(dev)) { |
5218 | dev_priv->max_cdclk_freq = 624000; | |
560a7ae4 DL |
5219 | } else if (IS_BROADWELL(dev)) { |
5220 | /* | |
5221 | * FIXME with extra cooling we can allow | |
5222 | * 540 MHz for ULX and 675 Mhz for ULT. | |
5223 | * How can we know if extra cooling is | |
5224 | * available? PCI ID, VTB, something else? | |
5225 | */ | |
5226 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
5227 | dev_priv->max_cdclk_freq = 450000; | |
5228 | else if (IS_BDW_ULX(dev)) | |
5229 | dev_priv->max_cdclk_freq = 450000; | |
5230 | else if (IS_BDW_ULT(dev)) | |
5231 | dev_priv->max_cdclk_freq = 540000; | |
5232 | else | |
5233 | dev_priv->max_cdclk_freq = 675000; | |
0904deaf MK |
5234 | } else if (IS_CHERRYVIEW(dev)) { |
5235 | dev_priv->max_cdclk_freq = 320000; | |
560a7ae4 DL |
5236 | } else if (IS_VALLEYVIEW(dev)) { |
5237 | dev_priv->max_cdclk_freq = 400000; | |
5238 | } else { | |
5239 | /* otherwise assume cdclk is fixed */ | |
5240 | dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; | |
5241 | } | |
5242 | ||
adafdc6f MK |
5243 | dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); |
5244 | ||
560a7ae4 DL |
5245 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", |
5246 | dev_priv->max_cdclk_freq); | |
adafdc6f MK |
5247 | |
5248 | DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", | |
5249 | dev_priv->max_dotclk_freq); | |
560a7ae4 DL |
5250 | } |
5251 | ||
5252 | static void intel_update_cdclk(struct drm_device *dev) | |
5253 | { | |
5254 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5255 | ||
5256 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
2f2a121a | 5257 | |
83d7c81f | 5258 | if (INTEL_GEN(dev_priv) >= 9) |
709e05c3 VS |
5259 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n", |
5260 | dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco, | |
5261 | dev_priv->cdclk_pll.ref); | |
2f2a121a VS |
5262 | else |
5263 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", | |
5264 | dev_priv->cdclk_freq); | |
560a7ae4 DL |
5265 | |
5266 | /* | |
b5d99ff9 VS |
5267 | * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): |
5268 | * Programmng [sic] note: bit[9:2] should be programmed to the number | |
5269 | * of cdclk that generates 4MHz reference clock freq which is used to | |
5270 | * generate GMBus clock. This will vary with the cdclk freq. | |
560a7ae4 | 5271 | */ |
b5d99ff9 | 5272 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
560a7ae4 | 5273 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); |
560a7ae4 DL |
5274 | } |
5275 | ||
92891e45 VS |
5276 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ |
5277 | static int skl_cdclk_decimal(int cdclk) | |
5278 | { | |
5279 | return DIV_ROUND_CLOSEST(cdclk - 1000, 500); | |
5280 | } | |
5281 | ||
5f199dfa VS |
5282 | static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk) |
5283 | { | |
5284 | int ratio; | |
5285 | ||
5286 | if (cdclk == dev_priv->cdclk_pll.ref) | |
5287 | return 0; | |
5288 | ||
5289 | switch (cdclk) { | |
5290 | default: | |
5291 | MISSING_CASE(cdclk); | |
5292 | case 144000: | |
5293 | case 288000: | |
5294 | case 384000: | |
5295 | case 576000: | |
5296 | ratio = 60; | |
5297 | break; | |
5298 | case 624000: | |
5299 | ratio = 65; | |
5300 | break; | |
5301 | } | |
5302 | ||
5303 | return dev_priv->cdclk_pll.ref * ratio; | |
5304 | } | |
5305 | ||
2b73001e VS |
5306 | static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) |
5307 | { | |
5308 | I915_WRITE(BXT_DE_PLL_ENABLE, 0); | |
5309 | ||
5310 | /* Timeout 200us */ | |
5311 | if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1)) | |
5312 | DRM_ERROR("timeout waiting for DE PLL unlock\n"); | |
83d7c81f VS |
5313 | |
5314 | dev_priv->cdclk_pll.vco = 0; | |
2b73001e VS |
5315 | } |
5316 | ||
5f199dfa | 5317 | static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) |
2b73001e | 5318 | { |
5f199dfa | 5319 | int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref); |
2b73001e VS |
5320 | u32 val; |
5321 | ||
5322 | val = I915_READ(BXT_DE_PLL_CTL); | |
5323 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5f199dfa | 5324 | val |= BXT_DE_PLL_RATIO(ratio); |
2b73001e VS |
5325 | I915_WRITE(BXT_DE_PLL_CTL, val); |
5326 | ||
5327 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5328 | ||
5329 | /* Timeout 200us */ | |
5330 | if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1)) | |
5331 | DRM_ERROR("timeout waiting for DE PLL lock\n"); | |
83d7c81f | 5332 | |
5f199dfa | 5333 | dev_priv->cdclk_pll.vco = vco; |
2b73001e VS |
5334 | } |
5335 | ||
9ef56154 | 5336 | static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int cdclk) |
f8437dd1 | 5337 | { |
5f199dfa VS |
5338 | u32 val, divider; |
5339 | int vco, ret; | |
f8437dd1 | 5340 | |
5f199dfa VS |
5341 | vco = bxt_de_pll_vco(dev_priv, cdclk); |
5342 | ||
5343 | DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco); | |
5344 | ||
5345 | /* cdclk = vco / 2 / div{1,1.5,2,4} */ | |
5346 | switch (DIV_ROUND_CLOSEST(vco, cdclk)) { | |
5347 | case 8: | |
f8437dd1 | 5348 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; |
f8437dd1 | 5349 | break; |
5f199dfa | 5350 | case 4: |
f8437dd1 | 5351 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; |
f8437dd1 | 5352 | break; |
5f199dfa | 5353 | case 3: |
f8437dd1 | 5354 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; |
f8437dd1 | 5355 | break; |
5f199dfa | 5356 | case 2: |
f8437dd1 | 5357 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; |
f8437dd1 VK |
5358 | break; |
5359 | default: | |
5f199dfa VS |
5360 | WARN_ON(cdclk != dev_priv->cdclk_pll.ref); |
5361 | WARN_ON(vco != 0); | |
f8437dd1 | 5362 | |
5f199dfa VS |
5363 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; |
5364 | break; | |
f8437dd1 VK |
5365 | } |
5366 | ||
f8437dd1 | 5367 | /* Inform power controller of upcoming frequency change */ |
5f199dfa | 5368 | mutex_lock(&dev_priv->rps.hw_lock); |
f8437dd1 VK |
5369 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, |
5370 | 0x80000000); | |
5371 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5372 | ||
5373 | if (ret) { | |
5374 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
9ef56154 | 5375 | ret, cdclk); |
f8437dd1 VK |
5376 | return; |
5377 | } | |
5378 | ||
5f199dfa VS |
5379 | if (dev_priv->cdclk_pll.vco != 0 && |
5380 | dev_priv->cdclk_pll.vco != vco) | |
2b73001e | 5381 | bxt_de_pll_disable(dev_priv); |
f8437dd1 | 5382 | |
5f199dfa VS |
5383 | if (dev_priv->cdclk_pll.vco != vco) |
5384 | bxt_de_pll_enable(dev_priv, vco); | |
f8437dd1 | 5385 | |
5f199dfa VS |
5386 | val = divider | skl_cdclk_decimal(cdclk); |
5387 | /* | |
5388 | * FIXME if only the cd2x divider needs changing, it could be done | |
5389 | * without shutting off the pipe (if only one pipe is active). | |
5390 | */ | |
5391 | val |= BXT_CDCLK_CD2X_PIPE_NONE; | |
5392 | /* | |
5393 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5394 | * enable otherwise. | |
5395 | */ | |
5396 | if (cdclk >= 500000) | |
5397 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5398 | I915_WRITE(CDCLK_CTL, val); | |
f8437dd1 VK |
5399 | |
5400 | mutex_lock(&dev_priv->rps.hw_lock); | |
5401 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
9ef56154 | 5402 | DIV_ROUND_UP(cdclk, 25000)); |
f8437dd1 VK |
5403 | mutex_unlock(&dev_priv->rps.hw_lock); |
5404 | ||
5405 | if (ret) { | |
5406 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
9ef56154 | 5407 | ret, cdclk); |
f8437dd1 VK |
5408 | return; |
5409 | } | |
5410 | ||
c6c4696f | 5411 | intel_update_cdclk(dev_priv->dev); |
f8437dd1 VK |
5412 | } |
5413 | ||
c6c4696f | 5414 | void broxton_init_cdclk(struct drm_i915_private *dev_priv) |
f8437dd1 | 5415 | { |
089c6fd5 | 5416 | intel_update_cdclk(dev_priv->dev); |
f8437dd1 | 5417 | |
089c6fd5 VS |
5418 | if (dev_priv->cdclk_pll.vco != 0) |
5419 | return; | |
c2e001ef | 5420 | |
f8437dd1 VK |
5421 | /* |
5422 | * FIXME: | |
5423 | * - The initial CDCLK needs to be read from VBT. | |
5424 | * Need to make this change after VBT has changes for BXT. | |
f8437dd1 | 5425 | */ |
d1b32c32 | 5426 | broxton_set_cdclk(dev_priv, broxton_calc_cdclk(0)); |
f8437dd1 VK |
5427 | } |
5428 | ||
c6c4696f | 5429 | void broxton_uninit_cdclk(struct drm_i915_private *dev_priv) |
f8437dd1 | 5430 | { |
5f199dfa | 5431 | broxton_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref); |
f8437dd1 VK |
5432 | } |
5433 | ||
a8ca4934 VS |
5434 | static int skl_calc_cdclk(int max_pixclk, int vco) |
5435 | { | |
63911d72 | 5436 | if (vco == 8640000) { |
a8ca4934 | 5437 | if (max_pixclk > 540000) |
487ed2e4 | 5438 | return 617143; |
a8ca4934 VS |
5439 | else if (max_pixclk > 432000) |
5440 | return 540000; | |
487ed2e4 | 5441 | else if (max_pixclk > 308571) |
a8ca4934 VS |
5442 | return 432000; |
5443 | else | |
487ed2e4 | 5444 | return 308571; |
a8ca4934 | 5445 | } else { |
a8ca4934 VS |
5446 | if (max_pixclk > 540000) |
5447 | return 675000; | |
5448 | else if (max_pixclk > 450000) | |
5449 | return 540000; | |
5450 | else if (max_pixclk > 337500) | |
5451 | return 450000; | |
5452 | else | |
5453 | return 337500; | |
5454 | } | |
5455 | } | |
5456 | ||
ea61791e VS |
5457 | static void |
5458 | skl_dpll0_update(struct drm_i915_private *dev_priv) | |
5d96d8af | 5459 | { |
ea61791e | 5460 | u32 val; |
5d96d8af | 5461 | |
709e05c3 VS |
5462 | dev_priv->cdclk_pll.ref = 24000; |
5463 | ||
ea61791e VS |
5464 | val = I915_READ(LCPLL1_CTL); |
5465 | if ((val & LCPLL_PLL_ENABLE) == 0) { | |
63911d72 | 5466 | dev_priv->cdclk_pll.vco = 0; |
ea61791e | 5467 | return; |
5d96d8af DL |
5468 | } |
5469 | ||
9f7eb31a VS |
5470 | WARN_ON((val & LCPLL_PLL_LOCK) == 0); |
5471 | ||
ea61791e VS |
5472 | val = I915_READ(DPLL_CTRL1); |
5473 | ||
9f7eb31a VS |
5474 | WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | |
5475 | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
5476 | DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != | |
5477 | DPLL_CTRL1_OVERRIDE(SKL_DPLL0)); | |
5478 | ||
ea61791e VS |
5479 | switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { |
5480 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): | |
5481 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): | |
5482 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): | |
5483 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): | |
63911d72 | 5484 | dev_priv->cdclk_pll.vco = 8100000; |
ea61791e VS |
5485 | break; |
5486 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): | |
5487 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): | |
63911d72 | 5488 | dev_priv->cdclk_pll.vco = 8640000; |
ea61791e VS |
5489 | break; |
5490 | default: | |
5491 | MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
63911d72 | 5492 | dev_priv->cdclk_pll.vco = 0; |
ea61791e VS |
5493 | break; |
5494 | } | |
5d96d8af DL |
5495 | } |
5496 | ||
b2045352 VS |
5497 | void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco) |
5498 | { | |
5499 | bool changed = dev_priv->skl_preferred_vco_freq != vco; | |
5500 | ||
5501 | dev_priv->skl_preferred_vco_freq = vco; | |
5502 | ||
5503 | if (changed) | |
5504 | intel_update_max_cdclk(dev_priv->dev); | |
5505 | } | |
5506 | ||
5d96d8af | 5507 | static void |
3861fc60 | 5508 | skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) |
5d96d8af | 5509 | { |
a8ca4934 | 5510 | int min_cdclk = skl_calc_cdclk(0, vco); |
5d96d8af DL |
5511 | u32 val; |
5512 | ||
63911d72 | 5513 | WARN_ON(vco != 8100000 && vco != 8640000); |
b2045352 | 5514 | |
5d96d8af | 5515 | /* select the minimum CDCLK before enabling DPLL 0 */ |
9ef56154 | 5516 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk); |
5d96d8af DL |
5517 | I915_WRITE(CDCLK_CTL, val); |
5518 | POSTING_READ(CDCLK_CTL); | |
5519 | ||
5520 | /* | |
5521 | * We always enable DPLL0 with the lowest link rate possible, but still | |
5522 | * taking into account the VCO required to operate the eDP panel at the | |
5523 | * desired frequency. The usual DP link rates operate with a VCO of | |
5524 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. | |
5525 | * The modeset code is responsible for the selection of the exact link | |
5526 | * rate later on, with the constraint of choosing a frequency that | |
a8ca4934 | 5527 | * works with vco. |
5d96d8af DL |
5528 | */ |
5529 | val = I915_READ(DPLL_CTRL1); | |
5530 | ||
5531 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
5532 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
5533 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
63911d72 | 5534 | if (vco == 8640000) |
5d96d8af DL |
5535 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, |
5536 | SKL_DPLL0); | |
5537 | else | |
5538 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, | |
5539 | SKL_DPLL0); | |
5540 | ||
5541 | I915_WRITE(DPLL_CTRL1, val); | |
5542 | POSTING_READ(DPLL_CTRL1); | |
5543 | ||
5544 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); | |
5545 | ||
5546 | if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5)) | |
5547 | DRM_ERROR("DPLL0 not locked\n"); | |
1cd593e0 | 5548 | |
63911d72 | 5549 | dev_priv->cdclk_pll.vco = vco; |
b2045352 VS |
5550 | |
5551 | /* We'll want to keep using the current vco from now on. */ | |
5552 | skl_set_preferred_cdclk_vco(dev_priv, vco); | |
5d96d8af DL |
5553 | } |
5554 | ||
430e05de VS |
5555 | static void |
5556 | skl_dpll0_disable(struct drm_i915_private *dev_priv) | |
5557 | { | |
5558 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); | |
5559 | if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) | |
5560 | DRM_ERROR("Couldn't disable DPLL0\n"); | |
1cd593e0 | 5561 | |
63911d72 | 5562 | dev_priv->cdclk_pll.vco = 0; |
430e05de VS |
5563 | } |
5564 | ||
5d96d8af DL |
5565 | static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) |
5566 | { | |
5567 | int ret; | |
5568 | u32 val; | |
5569 | ||
5570 | /* inform PCU we want to change CDCLK */ | |
5571 | val = SKL_CDCLK_PREPARE_FOR_CHANGE; | |
5572 | mutex_lock(&dev_priv->rps.hw_lock); | |
5573 | ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); | |
5574 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5575 | ||
5576 | return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE); | |
5577 | } | |
5578 | ||
5579 | static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) | |
5580 | { | |
5581 | unsigned int i; | |
5582 | ||
5583 | for (i = 0; i < 15; i++) { | |
5584 | if (skl_cdclk_pcu_ready(dev_priv)) | |
5585 | return true; | |
5586 | udelay(10); | |
5587 | } | |
5588 | ||
5589 | return false; | |
5590 | } | |
5591 | ||
1cd593e0 | 5592 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco) |
5d96d8af | 5593 | { |
560a7ae4 | 5594 | struct drm_device *dev = dev_priv->dev; |
5d96d8af DL |
5595 | u32 freq_select, pcu_ack; |
5596 | ||
1cd593e0 VS |
5597 | WARN_ON((cdclk == 24000) != (vco == 0)); |
5598 | ||
63911d72 | 5599 | DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco); |
5d96d8af DL |
5600 | |
5601 | if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { | |
5602 | DRM_ERROR("failed to inform PCU about cdclk change\n"); | |
5603 | return; | |
5604 | } | |
5605 | ||
5606 | /* set CDCLK_CTL */ | |
9ef56154 | 5607 | switch (cdclk) { |
5d96d8af DL |
5608 | case 450000: |
5609 | case 432000: | |
5610 | freq_select = CDCLK_FREQ_450_432; | |
5611 | pcu_ack = 1; | |
5612 | break; | |
5613 | case 540000: | |
5614 | freq_select = CDCLK_FREQ_540; | |
5615 | pcu_ack = 2; | |
5616 | break; | |
487ed2e4 | 5617 | case 308571: |
5d96d8af DL |
5618 | case 337500: |
5619 | default: | |
5620 | freq_select = CDCLK_FREQ_337_308; | |
5621 | pcu_ack = 0; | |
5622 | break; | |
487ed2e4 | 5623 | case 617143: |
5d96d8af DL |
5624 | case 675000: |
5625 | freq_select = CDCLK_FREQ_675_617; | |
5626 | pcu_ack = 3; | |
5627 | break; | |
5628 | } | |
5629 | ||
63911d72 VS |
5630 | if (dev_priv->cdclk_pll.vco != 0 && |
5631 | dev_priv->cdclk_pll.vco != vco) | |
1cd593e0 VS |
5632 | skl_dpll0_disable(dev_priv); |
5633 | ||
63911d72 | 5634 | if (dev_priv->cdclk_pll.vco != vco) |
1cd593e0 VS |
5635 | skl_dpll0_enable(dev_priv, vco); |
5636 | ||
9ef56154 | 5637 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk)); |
5d96d8af DL |
5638 | POSTING_READ(CDCLK_CTL); |
5639 | ||
5640 | /* inform PCU of the change */ | |
5641 | mutex_lock(&dev_priv->rps.hw_lock); | |
5642 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); | |
5643 | mutex_unlock(&dev_priv->rps.hw_lock); | |
560a7ae4 DL |
5644 | |
5645 | intel_update_cdclk(dev); | |
5d96d8af DL |
5646 | } |
5647 | ||
9f7eb31a VS |
5648 | static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv); |
5649 | ||
5d96d8af DL |
5650 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) |
5651 | { | |
709e05c3 | 5652 | skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0); |
5d96d8af DL |
5653 | } |
5654 | ||
5655 | void skl_init_cdclk(struct drm_i915_private *dev_priv) | |
5656 | { | |
9f7eb31a VS |
5657 | int cdclk, vco; |
5658 | ||
5659 | skl_sanitize_cdclk(dev_priv); | |
5d96d8af | 5660 | |
63911d72 | 5661 | if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) { |
9f7eb31a VS |
5662 | /* |
5663 | * Use the current vco as our initial | |
5664 | * guess as to what the preferred vco is. | |
5665 | */ | |
5666 | if (dev_priv->skl_preferred_vco_freq == 0) | |
5667 | skl_set_preferred_cdclk_vco(dev_priv, | |
63911d72 | 5668 | dev_priv->cdclk_pll.vco); |
70c2c184 | 5669 | return; |
1cd593e0 | 5670 | } |
5d96d8af | 5671 | |
70c2c184 VS |
5672 | vco = dev_priv->skl_preferred_vco_freq; |
5673 | if (vco == 0) | |
63911d72 | 5674 | vco = 8100000; |
70c2c184 | 5675 | cdclk = skl_calc_cdclk(0, vco); |
5d96d8af | 5676 | |
70c2c184 | 5677 | skl_set_cdclk(dev_priv, cdclk, vco); |
5d96d8af DL |
5678 | } |
5679 | ||
9f7eb31a | 5680 | static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) |
c73666f3 | 5681 | { |
09492498 | 5682 | uint32_t cdctl, expected; |
c73666f3 | 5683 | |
f1b391a5 SK |
5684 | /* |
5685 | * check if the pre-os intialized the display | |
5686 | * There is SWF18 scratchpad register defined which is set by the | |
5687 | * pre-os which can be used by the OS drivers to check the status | |
5688 | */ | |
5689 | if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) | |
5690 | goto sanitize; | |
5691 | ||
c73666f3 | 5692 | /* Is PLL enabled and locked ? */ |
09492498 VS |
5693 | if ((I915_READ(LCPLL1_CTL) & (LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK)) != |
5694 | (LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK)) | |
5695 | goto sanitize; | |
5696 | ||
5697 | if ((I915_READ(DPLL_CTRL1) & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | | |
5698 | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
5699 | DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != | |
5700 | DPLL_CTRL1_OVERRIDE(SKL_DPLL0)) | |
c73666f3 SK |
5701 | goto sanitize; |
5702 | ||
9f7eb31a VS |
5703 | intel_update_cdclk(dev_priv->dev); |
5704 | ||
c73666f3 SK |
5705 | /* DPLL okay; verify the cdclock |
5706 | * | |
5707 | * Noticed in some instances that the freq selection is correct but | |
5708 | * decimal part is programmed wrong from BIOS where pre-os does not | |
5709 | * enable display. Verify the same as well. | |
5710 | */ | |
09492498 VS |
5711 | cdctl = I915_READ(CDCLK_CTL); |
5712 | expected = (cdctl & CDCLK_FREQ_SEL_MASK) | | |
5713 | skl_cdclk_decimal(dev_priv->cdclk_freq); | |
5714 | if (cdctl == expected) | |
c73666f3 | 5715 | /* All well; nothing to sanitize */ |
9f7eb31a | 5716 | return; |
c89e39f3 | 5717 | |
9f7eb31a VS |
5718 | sanitize: |
5719 | DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); | |
c73666f3 | 5720 | |
9f7eb31a VS |
5721 | /* force cdclk programming */ |
5722 | dev_priv->cdclk_freq = 0; | |
5723 | /* force full PLL disable + enable */ | |
63911d72 | 5724 | dev_priv->cdclk_pll.vco = -1; |
c73666f3 SK |
5725 | } |
5726 | ||
30a970c6 JB |
5727 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
5728 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
5729 | { | |
5730 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5731 | u32 val, cmd; | |
5732 | ||
164dfd28 VK |
5733 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5734 | != dev_priv->cdclk_freq); | |
d60c4473 | 5735 | |
dfcab17e | 5736 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 5737 | cmd = 2; |
dfcab17e | 5738 | else if (cdclk == 266667) |
30a970c6 JB |
5739 | cmd = 1; |
5740 | else | |
5741 | cmd = 0; | |
5742 | ||
5743 | mutex_lock(&dev_priv->rps.hw_lock); | |
5744 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5745 | val &= ~DSPFREQGUAR_MASK; | |
5746 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
5747 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5748 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5749 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
5750 | 50)) { | |
5751 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5752 | } | |
5753 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5754 | ||
54433e91 VS |
5755 | mutex_lock(&dev_priv->sb_lock); |
5756 | ||
dfcab17e | 5757 | if (cdclk == 400000) { |
6bcda4f0 | 5758 | u32 divider; |
30a970c6 | 5759 | |
6bcda4f0 | 5760 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 | 5761 | |
30a970c6 JB |
5762 | /* adjust cdclk divider */ |
5763 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
87d5d259 | 5764 | val &= ~CCK_FREQUENCY_VALUES; |
30a970c6 JB |
5765 | val |= divider; |
5766 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
5767 | |
5768 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
87d5d259 | 5769 | CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), |
a877e801 VS |
5770 | 50)) |
5771 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
5772 | } |
5773 | ||
30a970c6 JB |
5774 | /* adjust self-refresh exit latency value */ |
5775 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
5776 | val &= ~0x7f; | |
5777 | ||
5778 | /* | |
5779 | * For high bandwidth configs, we set a higher latency in the bunit | |
5780 | * so that the core display fetch happens in time to avoid underruns. | |
5781 | */ | |
dfcab17e | 5782 | if (cdclk == 400000) |
30a970c6 JB |
5783 | val |= 4500 / 250; /* 4.5 usec */ |
5784 | else | |
5785 | val |= 3000 / 250; /* 3.0 usec */ | |
5786 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
54433e91 | 5787 | |
a580516d | 5788 | mutex_unlock(&dev_priv->sb_lock); |
30a970c6 | 5789 | |
b6283055 | 5790 | intel_update_cdclk(dev); |
30a970c6 JB |
5791 | } |
5792 | ||
383c5a6a VS |
5793 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
5794 | { | |
5795 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5796 | u32 val, cmd; | |
5797 | ||
164dfd28 VK |
5798 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5799 | != dev_priv->cdclk_freq); | |
383c5a6a VS |
5800 | |
5801 | switch (cdclk) { | |
383c5a6a VS |
5802 | case 333333: |
5803 | case 320000: | |
383c5a6a | 5804 | case 266667: |
383c5a6a | 5805 | case 200000: |
383c5a6a VS |
5806 | break; |
5807 | default: | |
5f77eeb0 | 5808 | MISSING_CASE(cdclk); |
383c5a6a VS |
5809 | return; |
5810 | } | |
5811 | ||
9d0d3fda VS |
5812 | /* |
5813 | * Specs are full of misinformation, but testing on actual | |
5814 | * hardware has shown that we just need to write the desired | |
5815 | * CCK divider into the Punit register. | |
5816 | */ | |
5817 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
5818 | ||
383c5a6a VS |
5819 | mutex_lock(&dev_priv->rps.hw_lock); |
5820 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5821 | val &= ~DSPFREQGUAR_MASK_CHV; | |
5822 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
5823 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5824 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5825 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
5826 | 50)) { | |
5827 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5828 | } | |
5829 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5830 | ||
b6283055 | 5831 | intel_update_cdclk(dev); |
383c5a6a VS |
5832 | } |
5833 | ||
30a970c6 JB |
5834 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
5835 | int max_pixclk) | |
5836 | { | |
6bcda4f0 | 5837 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 5838 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 5839 | |
30a970c6 JB |
5840 | /* |
5841 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
5842 | * 200MHz | |
5843 | * 267MHz | |
29dc7ef3 | 5844 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
5845 | * 400MHz (VLV only) |
5846 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
5847 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
5848 | * |
5849 | * We seem to get an unstable or solid color picture at 200MHz. | |
5850 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
5851 | * are off. | |
30a970c6 | 5852 | */ |
6cca3195 VS |
5853 | if (!IS_CHERRYVIEW(dev_priv) && |
5854 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 5855 | return 400000; |
6cca3195 | 5856 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 5857 | return freq_320; |
e37c67a1 | 5858 | else if (max_pixclk > 0) |
dfcab17e | 5859 | return 266667; |
e37c67a1 VS |
5860 | else |
5861 | return 200000; | |
30a970c6 JB |
5862 | } |
5863 | ||
c44deb6c | 5864 | static int broxton_calc_cdclk(int max_pixclk) |
f8437dd1 | 5865 | { |
760e1477 | 5866 | if (max_pixclk > 576000) |
f8437dd1 | 5867 | return 624000; |
760e1477 | 5868 | else if (max_pixclk > 384000) |
f8437dd1 | 5869 | return 576000; |
760e1477 | 5870 | else if (max_pixclk > 288000) |
f8437dd1 | 5871 | return 384000; |
760e1477 | 5872 | else if (max_pixclk > 144000) |
f8437dd1 VK |
5873 | return 288000; |
5874 | else | |
5875 | return 144000; | |
5876 | } | |
5877 | ||
e8788cbc | 5878 | /* Compute the max pixel clock for new configuration. */ |
a821fc46 ACO |
5879 | static int intel_mode_max_pixclk(struct drm_device *dev, |
5880 | struct drm_atomic_state *state) | |
30a970c6 | 5881 | { |
565602d7 ML |
5882 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
5883 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5884 | struct drm_crtc *crtc; | |
5885 | struct drm_crtc_state *crtc_state; | |
5886 | unsigned max_pixclk = 0, i; | |
5887 | enum pipe pipe; | |
30a970c6 | 5888 | |
565602d7 ML |
5889 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
5890 | sizeof(intel_state->min_pixclk)); | |
304603f4 | 5891 | |
565602d7 ML |
5892 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
5893 | int pixclk = 0; | |
5894 | ||
5895 | if (crtc_state->enable) | |
5896 | pixclk = crtc_state->adjusted_mode.crtc_clock; | |
304603f4 | 5897 | |
565602d7 | 5898 | intel_state->min_pixclk[i] = pixclk; |
30a970c6 JB |
5899 | } |
5900 | ||
565602d7 ML |
5901 | for_each_pipe(dev_priv, pipe) |
5902 | max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk); | |
5903 | ||
30a970c6 JB |
5904 | return max_pixclk; |
5905 | } | |
5906 | ||
27c329ed | 5907 | static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) |
30a970c6 | 5908 | { |
27c329ed ML |
5909 | struct drm_device *dev = state->dev; |
5910 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5911 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
1a617b77 ML |
5912 | struct intel_atomic_state *intel_state = |
5913 | to_intel_atomic_state(state); | |
30a970c6 | 5914 | |
1a617b77 | 5915 | intel_state->cdclk = intel_state->dev_cdclk = |
27c329ed | 5916 | valleyview_calc_cdclk(dev_priv, max_pixclk); |
0a9ab303 | 5917 | |
1a617b77 ML |
5918 | if (!intel_state->active_crtcs) |
5919 | intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0); | |
5920 | ||
27c329ed ML |
5921 | return 0; |
5922 | } | |
304603f4 | 5923 | |
27c329ed ML |
5924 | static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state) |
5925 | { | |
4e5ca60f | 5926 | int max_pixclk = ilk_max_pixel_rate(state); |
1a617b77 ML |
5927 | struct intel_atomic_state *intel_state = |
5928 | to_intel_atomic_state(state); | |
85a96e7a | 5929 | |
1a617b77 | 5930 | intel_state->cdclk = intel_state->dev_cdclk = |
c44deb6c | 5931 | broxton_calc_cdclk(max_pixclk); |
85a96e7a | 5932 | |
1a617b77 | 5933 | if (!intel_state->active_crtcs) |
c44deb6c | 5934 | intel_state->dev_cdclk = broxton_calc_cdclk(0); |
1a617b77 | 5935 | |
27c329ed | 5936 | return 0; |
30a970c6 JB |
5937 | } |
5938 | ||
1e69cd74 VS |
5939 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
5940 | { | |
5941 | unsigned int credits, default_credits; | |
5942 | ||
5943 | if (IS_CHERRYVIEW(dev_priv)) | |
5944 | default_credits = PFI_CREDIT(12); | |
5945 | else | |
5946 | default_credits = PFI_CREDIT(8); | |
5947 | ||
bfa7df01 | 5948 | if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) { |
1e69cd74 VS |
5949 | /* CHV suggested value is 31 or 63 */ |
5950 | if (IS_CHERRYVIEW(dev_priv)) | |
fcc0008f | 5951 | credits = PFI_CREDIT_63; |
1e69cd74 VS |
5952 | else |
5953 | credits = PFI_CREDIT(15); | |
5954 | } else { | |
5955 | credits = default_credits; | |
5956 | } | |
5957 | ||
5958 | /* | |
5959 | * WA - write default credits before re-programming | |
5960 | * FIXME: should we also set the resend bit here? | |
5961 | */ | |
5962 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
5963 | default_credits); | |
5964 | ||
5965 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
5966 | credits | PFI_CREDIT_RESEND); | |
5967 | ||
5968 | /* | |
5969 | * FIXME is this guaranteed to clear | |
5970 | * immediately or should we poll for it? | |
5971 | */ | |
5972 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
5973 | } | |
5974 | ||
27c329ed | 5975 | static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
30a970c6 | 5976 | { |
a821fc46 | 5977 | struct drm_device *dev = old_state->dev; |
30a970c6 | 5978 | struct drm_i915_private *dev_priv = dev->dev_private; |
1a617b77 ML |
5979 | struct intel_atomic_state *old_intel_state = |
5980 | to_intel_atomic_state(old_state); | |
5981 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
30a970c6 | 5982 | |
27c329ed ML |
5983 | /* |
5984 | * FIXME: We can end up here with all power domains off, yet | |
5985 | * with a CDCLK frequency other than the minimum. To account | |
5986 | * for this take the PIPE-A power domain, which covers the HW | |
5987 | * blocks needed for the following programming. This can be | |
5988 | * removed once it's guaranteed that we get here either with | |
5989 | * the minimum CDCLK set, or the required power domains | |
5990 | * enabled. | |
5991 | */ | |
5992 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
738c05c0 | 5993 | |
27c329ed ML |
5994 | if (IS_CHERRYVIEW(dev)) |
5995 | cherryview_set_cdclk(dev, req_cdclk); | |
5996 | else | |
5997 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 5998 | |
27c329ed | 5999 | vlv_program_pfi_credits(dev_priv); |
1e69cd74 | 6000 | |
27c329ed | 6001 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
30a970c6 JB |
6002 | } |
6003 | ||
89b667f8 JB |
6004 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
6005 | { | |
6006 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6007 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
6008 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6009 | struct intel_encoder *encoder; | |
b95c5321 ML |
6010 | struct intel_crtc_state *pipe_config = |
6011 | to_intel_crtc_state(crtc->state); | |
89b667f8 | 6012 | int pipe = intel_crtc->pipe; |
89b667f8 | 6013 | |
53d9f4e9 | 6014 | if (WARN_ON(intel_crtc->active)) |
89b667f8 JB |
6015 | return; |
6016 | ||
6e3c9717 | 6017 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6018 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6019 | |
6020 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 6021 | intel_set_pipe_src_size(intel_crtc); |
5b18e57c | 6022 | |
c14b0485 VS |
6023 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
6024 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6025 | ||
6026 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
6027 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
6028 | } | |
6029 | ||
5b18e57c DV |
6030 | i9xx_set_pipeconf(intel_crtc); |
6031 | ||
89b667f8 | 6032 | intel_crtc->active = true; |
89b667f8 | 6033 | |
a72e4c9f | 6034 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6035 | |
89b667f8 JB |
6036 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6037 | if (encoder->pre_pll_enable) | |
6038 | encoder->pre_pll_enable(encoder); | |
6039 | ||
cd2d34d9 VS |
6040 | if (IS_CHERRYVIEW(dev)) { |
6041 | chv_prepare_pll(intel_crtc, intel_crtc->config); | |
6042 | chv_enable_pll(intel_crtc, intel_crtc->config); | |
6043 | } else { | |
6044 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
6045 | vlv_enable_pll(intel_crtc, intel_crtc->config); | |
9d556c99 | 6046 | } |
89b667f8 JB |
6047 | |
6048 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
6049 | if (encoder->pre_enable) | |
6050 | encoder->pre_enable(encoder); | |
6051 | ||
2dd24552 JB |
6052 | i9xx_pfit_enable(intel_crtc); |
6053 | ||
b95c5321 | 6054 | intel_color_load_luts(&pipe_config->base); |
63cbb074 | 6055 | |
caed361d | 6056 | intel_update_watermarks(crtc); |
e1fdc473 | 6057 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6058 | |
4b3a9526 VS |
6059 | assert_vblank_disabled(crtc); |
6060 | drm_crtc_vblank_on(crtc); | |
6061 | ||
f9b61ff6 DV |
6062 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6063 | encoder->enable(encoder); | |
89b667f8 JB |
6064 | } |
6065 | ||
f13c2ef3 DV |
6066 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
6067 | { | |
6068 | struct drm_device *dev = crtc->base.dev; | |
6069 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6070 | ||
6e3c9717 ACO |
6071 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
6072 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
6073 | } |
6074 | ||
0b8765c6 | 6075 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
6076 | { |
6077 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6078 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 6079 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 6080 | struct intel_encoder *encoder; |
b95c5321 ML |
6081 | struct intel_crtc_state *pipe_config = |
6082 | to_intel_crtc_state(crtc->state); | |
cd2d34d9 | 6083 | enum pipe pipe = intel_crtc->pipe; |
79e53945 | 6084 | |
53d9f4e9 | 6085 | if (WARN_ON(intel_crtc->active)) |
f7abfe8b CW |
6086 | return; |
6087 | ||
f13c2ef3 DV |
6088 | i9xx_set_pll_dividers(intel_crtc); |
6089 | ||
6e3c9717 | 6090 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6091 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6092 | |
6093 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 6094 | intel_set_pipe_src_size(intel_crtc); |
5b18e57c | 6095 | |
5b18e57c DV |
6096 | i9xx_set_pipeconf(intel_crtc); |
6097 | ||
f7abfe8b | 6098 | intel_crtc->active = true; |
6b383a7f | 6099 | |
4a3436e8 | 6100 | if (!IS_GEN2(dev)) |
a72e4c9f | 6101 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6102 | |
9d6d9f19 MK |
6103 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6104 | if (encoder->pre_enable) | |
6105 | encoder->pre_enable(encoder); | |
6106 | ||
f6736a1a DV |
6107 | i9xx_enable_pll(intel_crtc); |
6108 | ||
2dd24552 JB |
6109 | i9xx_pfit_enable(intel_crtc); |
6110 | ||
b95c5321 | 6111 | intel_color_load_luts(&pipe_config->base); |
63cbb074 | 6112 | |
f37fcc2a | 6113 | intel_update_watermarks(crtc); |
e1fdc473 | 6114 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6115 | |
4b3a9526 VS |
6116 | assert_vblank_disabled(crtc); |
6117 | drm_crtc_vblank_on(crtc); | |
6118 | ||
f9b61ff6 DV |
6119 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6120 | encoder->enable(encoder); | |
0b8765c6 | 6121 | } |
79e53945 | 6122 | |
87476d63 DV |
6123 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
6124 | { | |
6125 | struct drm_device *dev = crtc->base.dev; | |
6126 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 6127 | |
6e3c9717 | 6128 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 6129 | return; |
87476d63 | 6130 | |
328d8e82 | 6131 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 6132 | |
328d8e82 DV |
6133 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
6134 | I915_READ(PFIT_CONTROL)); | |
6135 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
6136 | } |
6137 | ||
0b8765c6 JB |
6138 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
6139 | { | |
6140 | struct drm_device *dev = crtc->dev; | |
6141 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6142 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 6143 | struct intel_encoder *encoder; |
0b8765c6 | 6144 | int pipe = intel_crtc->pipe; |
ef9c3aee | 6145 | |
6304cd91 VS |
6146 | /* |
6147 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
6148 | * wait for planes to fully turn off before disabling the pipe. | |
6149 | */ | |
90e83e53 ACO |
6150 | if (IS_GEN2(dev)) |
6151 | intel_wait_for_vblank(dev, pipe); | |
6304cd91 | 6152 | |
4b3a9526 VS |
6153 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6154 | encoder->disable(encoder); | |
6155 | ||
f9b61ff6 DV |
6156 | drm_crtc_vblank_off(crtc); |
6157 | assert_vblank_disabled(crtc); | |
6158 | ||
575f7ab7 | 6159 | intel_disable_pipe(intel_crtc); |
24a1f16d | 6160 | |
87476d63 | 6161 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 6162 | |
89b667f8 JB |
6163 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6164 | if (encoder->post_disable) | |
6165 | encoder->post_disable(encoder); | |
6166 | ||
a65347ba | 6167 | if (!intel_crtc->config->has_dsi_encoder) { |
076ed3b2 CML |
6168 | if (IS_CHERRYVIEW(dev)) |
6169 | chv_disable_pll(dev_priv, pipe); | |
6170 | else if (IS_VALLEYVIEW(dev)) | |
6171 | vlv_disable_pll(dev_priv, pipe); | |
6172 | else | |
1c4e0274 | 6173 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 6174 | } |
0b8765c6 | 6175 | |
d6db995f VS |
6176 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6177 | if (encoder->post_pll_disable) | |
6178 | encoder->post_pll_disable(encoder); | |
6179 | ||
4a3436e8 | 6180 | if (!IS_GEN2(dev)) |
a72e4c9f | 6181 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
0b8765c6 JB |
6182 | } |
6183 | ||
b17d48e2 ML |
6184 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
6185 | { | |
842e0307 | 6186 | struct intel_encoder *encoder; |
b17d48e2 ML |
6187 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6188 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
6189 | enum intel_display_power_domain domain; | |
6190 | unsigned long domains; | |
6191 | ||
6192 | if (!intel_crtc->active) | |
6193 | return; | |
6194 | ||
a539205a | 6195 | if (to_intel_plane_state(crtc->primary->state)->visible) { |
6885843a | 6196 | WARN_ON(list_empty(&intel_crtc->flip_work)); |
fc32b1fd | 6197 | |
2622a081 | 6198 | intel_pre_disable_primary_noatomic(crtc); |
54a41961 ML |
6199 | |
6200 | intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); | |
6201 | to_intel_plane_state(crtc->primary->state)->visible = false; | |
a539205a ML |
6202 | } |
6203 | ||
b17d48e2 | 6204 | dev_priv->display.crtc_disable(crtc); |
842e0307 ML |
6205 | |
6206 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was enabled, now disabled\n", | |
6207 | crtc->base.id); | |
6208 | ||
6209 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0); | |
6210 | crtc->state->active = false; | |
37d9078b | 6211 | intel_crtc->active = false; |
842e0307 ML |
6212 | crtc->enabled = false; |
6213 | crtc->state->connector_mask = 0; | |
6214 | crtc->state->encoder_mask = 0; | |
6215 | ||
6216 | for_each_encoder_on_crtc(crtc->dev, crtc, encoder) | |
6217 | encoder->base.crtc = NULL; | |
6218 | ||
58f9c0bc | 6219 | intel_fbc_disable(intel_crtc); |
37d9078b | 6220 | intel_update_watermarks(crtc); |
1f7457b1 | 6221 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
6222 | |
6223 | domains = intel_crtc->enabled_power_domains; | |
6224 | for_each_power_domain(domain, domains) | |
6225 | intel_display_power_put(dev_priv, domain); | |
6226 | intel_crtc->enabled_power_domains = 0; | |
565602d7 ML |
6227 | |
6228 | dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); | |
6229 | dev_priv->min_pixclk[intel_crtc->pipe] = 0; | |
b17d48e2 ML |
6230 | } |
6231 | ||
6b72d486 ML |
6232 | /* |
6233 | * turn all crtc's off, but do not adjust state | |
6234 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
6235 | */ | |
70e0bd74 | 6236 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 6237 | { |
e2c8b870 | 6238 | struct drm_i915_private *dev_priv = to_i915(dev); |
70e0bd74 | 6239 | struct drm_atomic_state *state; |
e2c8b870 | 6240 | int ret; |
70e0bd74 | 6241 | |
e2c8b870 ML |
6242 | state = drm_atomic_helper_suspend(dev); |
6243 | ret = PTR_ERR_OR_ZERO(state); | |
70e0bd74 ML |
6244 | if (ret) |
6245 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
e2c8b870 ML |
6246 | else |
6247 | dev_priv->modeset_restore_state = state; | |
a6747b73 ML |
6248 | |
6249 | /* | |
6250 | * Make sure all unpin_work completes before returning. | |
6251 | */ | |
6252 | flush_workqueue(dev_priv->wq); | |
6253 | ||
70e0bd74 | 6254 | return ret; |
ee7b9f93 JB |
6255 | } |
6256 | ||
ea5b213a | 6257 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6258 | { |
4ef69c7a | 6259 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6260 | |
ea5b213a CW |
6261 | drm_encoder_cleanup(encoder); |
6262 | kfree(intel_encoder); | |
7e7d76c3 JB |
6263 | } |
6264 | ||
0a91ca29 DV |
6265 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6266 | * internal consistency). */ | |
03f476e1 ML |
6267 | static void intel_connector_verify_state(struct intel_connector *connector, |
6268 | struct drm_connector_state *conn_state) | |
79e53945 | 6269 | { |
03f476e1 | 6270 | struct drm_crtc *crtc = conn_state->crtc; |
35dd3c64 ML |
6271 | |
6272 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6273 | connector->base.base.id, | |
6274 | connector->base.name); | |
6275 | ||
0a91ca29 | 6276 | if (connector->get_hw_state(connector)) { |
e85376cb | 6277 | struct intel_encoder *encoder = connector->encoder; |
0a91ca29 | 6278 | |
35dd3c64 ML |
6279 | I915_STATE_WARN(!crtc, |
6280 | "connector enabled without attached crtc\n"); | |
0a91ca29 | 6281 | |
35dd3c64 ML |
6282 | if (!crtc) |
6283 | return; | |
6284 | ||
6285 | I915_STATE_WARN(!crtc->state->active, | |
6286 | "connector is active, but attached crtc isn't\n"); | |
6287 | ||
e85376cb | 6288 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
6289 | return; |
6290 | ||
e85376cb | 6291 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
6292 | "atomic encoder doesn't match attached encoder\n"); |
6293 | ||
e85376cb | 6294 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
6295 | "attached encoder crtc differs from connector crtc\n"); |
6296 | } else { | |
4d688a2a ML |
6297 | I915_STATE_WARN(crtc && crtc->state->active, |
6298 | "attached crtc is active, but connector isn't\n"); | |
03f476e1 | 6299 | I915_STATE_WARN(!crtc && conn_state->best_encoder, |
35dd3c64 | 6300 | "best encoder set without crtc!\n"); |
0a91ca29 | 6301 | } |
79e53945 JB |
6302 | } |
6303 | ||
08d9bc92 ACO |
6304 | int intel_connector_init(struct intel_connector *connector) |
6305 | { | |
5350a031 | 6306 | drm_atomic_helper_connector_reset(&connector->base); |
08d9bc92 | 6307 | |
5350a031 | 6308 | if (!connector->base.state) |
08d9bc92 ACO |
6309 | return -ENOMEM; |
6310 | ||
08d9bc92 ACO |
6311 | return 0; |
6312 | } | |
6313 | ||
6314 | struct intel_connector *intel_connector_alloc(void) | |
6315 | { | |
6316 | struct intel_connector *connector; | |
6317 | ||
6318 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6319 | if (!connector) | |
6320 | return NULL; | |
6321 | ||
6322 | if (intel_connector_init(connector) < 0) { | |
6323 | kfree(connector); | |
6324 | return NULL; | |
6325 | } | |
6326 | ||
6327 | return connector; | |
6328 | } | |
6329 | ||
f0947c37 DV |
6330 | /* Simple connector->get_hw_state implementation for encoders that support only |
6331 | * one connector and no cloning and hence the encoder state determines the state | |
6332 | * of the connector. */ | |
6333 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6334 | { |
24929352 | 6335 | enum pipe pipe = 0; |
f0947c37 | 6336 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6337 | |
f0947c37 | 6338 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6339 | } |
6340 | ||
6d293983 | 6341 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6342 | { |
6d293983 ACO |
6343 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6344 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6345 | |
6346 | return 0; | |
6347 | } | |
6348 | ||
6d293983 | 6349 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6350 | struct intel_crtc_state *pipe_config) |
1857e1da | 6351 | { |
6d293983 ACO |
6352 | struct drm_atomic_state *state = pipe_config->base.state; |
6353 | struct intel_crtc *other_crtc; | |
6354 | struct intel_crtc_state *other_crtc_state; | |
6355 | ||
1857e1da DV |
6356 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6357 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6358 | if (pipe_config->fdi_lanes > 4) { | |
6359 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6360 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6361 | return -EINVAL; |
1857e1da DV |
6362 | } |
6363 | ||
bafb6553 | 6364 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
6365 | if (pipe_config->fdi_lanes > 2) { |
6366 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6367 | pipe_config->fdi_lanes); | |
6d293983 | 6368 | return -EINVAL; |
1857e1da | 6369 | } else { |
6d293983 | 6370 | return 0; |
1857e1da DV |
6371 | } |
6372 | } | |
6373 | ||
6374 | if (INTEL_INFO(dev)->num_pipes == 2) | |
6d293983 | 6375 | return 0; |
1857e1da DV |
6376 | |
6377 | /* Ivybridge 3 pipe is really complicated */ | |
6378 | switch (pipe) { | |
6379 | case PIPE_A: | |
6d293983 | 6380 | return 0; |
1857e1da | 6381 | case PIPE_B: |
6d293983 ACO |
6382 | if (pipe_config->fdi_lanes <= 2) |
6383 | return 0; | |
6384 | ||
6385 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); | |
6386 | other_crtc_state = | |
6387 | intel_atomic_get_crtc_state(state, other_crtc); | |
6388 | if (IS_ERR(other_crtc_state)) | |
6389 | return PTR_ERR(other_crtc_state); | |
6390 | ||
6391 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6392 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6393 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6394 | return -EINVAL; |
1857e1da | 6395 | } |
6d293983 | 6396 | return 0; |
1857e1da | 6397 | case PIPE_C: |
251cc67c VS |
6398 | if (pipe_config->fdi_lanes > 2) { |
6399 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6400 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6401 | return -EINVAL; |
251cc67c | 6402 | } |
6d293983 ACO |
6403 | |
6404 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); | |
6405 | other_crtc_state = | |
6406 | intel_atomic_get_crtc_state(state, other_crtc); | |
6407 | if (IS_ERR(other_crtc_state)) | |
6408 | return PTR_ERR(other_crtc_state); | |
6409 | ||
6410 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6411 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6412 | return -EINVAL; |
1857e1da | 6413 | } |
6d293983 | 6414 | return 0; |
1857e1da DV |
6415 | default: |
6416 | BUG(); | |
6417 | } | |
6418 | } | |
6419 | ||
e29c22c0 DV |
6420 | #define RETRY 1 |
6421 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6422 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6423 | { |
1857e1da | 6424 | struct drm_device *dev = intel_crtc->base.dev; |
7c5f93b0 | 6425 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6426 | int lane, link_bw, fdi_dotclock, ret; |
6427 | bool needs_recompute = false; | |
877d48d5 | 6428 | |
e29c22c0 | 6429 | retry: |
877d48d5 DV |
6430 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6431 | * each output octet as 10 bits. The actual frequency | |
6432 | * is stored as a divider into a 100MHz clock, and the | |
6433 | * mode pixel clock is stored in units of 1KHz. | |
6434 | * Hence the bw of each lane in terms of the mode signal | |
6435 | * is: | |
6436 | */ | |
21a727b3 | 6437 | link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config); |
877d48d5 | 6438 | |
241bfc38 | 6439 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6440 | |
2bd89a07 | 6441 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6442 | pipe_config->pipe_bpp); |
6443 | ||
6444 | pipe_config->fdi_lanes = lane; | |
6445 | ||
2bd89a07 | 6446 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 6447 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 6448 | |
e3b247da | 6449 | ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); |
6d293983 | 6450 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { |
e29c22c0 DV |
6451 | pipe_config->pipe_bpp -= 2*3; |
6452 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
6453 | pipe_config->pipe_bpp); | |
6454 | needs_recompute = true; | |
6455 | pipe_config->bw_constrained = true; | |
6456 | ||
6457 | goto retry; | |
6458 | } | |
6459 | ||
6460 | if (needs_recompute) | |
6461 | return RETRY; | |
6462 | ||
6d293983 | 6463 | return ret; |
877d48d5 DV |
6464 | } |
6465 | ||
8cfb3407 VS |
6466 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
6467 | struct intel_crtc_state *pipe_config) | |
6468 | { | |
6469 | if (pipe_config->pipe_bpp > 24) | |
6470 | return false; | |
6471 | ||
6472 | /* HSW can handle pixel rate up to cdclk? */ | |
2d1fe073 | 6473 | if (IS_HASWELL(dev_priv)) |
8cfb3407 VS |
6474 | return true; |
6475 | ||
6476 | /* | |
b432e5cf VS |
6477 | * We compare against max which means we must take |
6478 | * the increased cdclk requirement into account when | |
6479 | * calculating the new cdclk. | |
6480 | * | |
6481 | * Should measure whether using a lower cdclk w/o IPS | |
8cfb3407 VS |
6482 | */ |
6483 | return ilk_pipe_pixel_rate(pipe_config) <= | |
6484 | dev_priv->max_cdclk_freq * 95 / 100; | |
6485 | } | |
6486 | ||
42db64ef | 6487 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 6488 | struct intel_crtc_state *pipe_config) |
42db64ef | 6489 | { |
8cfb3407 VS |
6490 | struct drm_device *dev = crtc->base.dev; |
6491 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6492 | ||
d330a953 | 6493 | pipe_config->ips_enabled = i915.enable_ips && |
8cfb3407 VS |
6494 | hsw_crtc_supports_ips(crtc) && |
6495 | pipe_config_supports_ips(dev_priv, pipe_config); | |
42db64ef PZ |
6496 | } |
6497 | ||
39acb4aa VS |
6498 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
6499 | { | |
6500 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
6501 | ||
6502 | /* GDG double wide on either pipe, otherwise pipe A only */ | |
6503 | return INTEL_INFO(dev_priv)->gen < 4 && | |
6504 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); | |
6505 | } | |
6506 | ||
a43f6e0f | 6507 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 6508 | struct intel_crtc_state *pipe_config) |
79e53945 | 6509 | { |
a43f6e0f | 6510 | struct drm_device *dev = crtc->base.dev; |
8bd31e67 | 6511 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c5f93b0 | 6512 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
89749350 | 6513 | |
ad3a4479 | 6514 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 | 6515 | if (INTEL_INFO(dev)->gen < 4) { |
39acb4aa | 6516 | int clock_limit = dev_priv->max_cdclk_freq * 9 / 10; |
cf532bb2 VS |
6517 | |
6518 | /* | |
39acb4aa | 6519 | * Enable double wide mode when the dot clock |
cf532bb2 | 6520 | * is > 90% of the (display) core speed. |
cf532bb2 | 6521 | */ |
39acb4aa VS |
6522 | if (intel_crtc_supports_double_wide(crtc) && |
6523 | adjusted_mode->crtc_clock > clock_limit) { | |
ad3a4479 | 6524 | clock_limit *= 2; |
cf532bb2 | 6525 | pipe_config->double_wide = true; |
ad3a4479 VS |
6526 | } |
6527 | ||
39acb4aa VS |
6528 | if (adjusted_mode->crtc_clock > clock_limit) { |
6529 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
6530 | adjusted_mode->crtc_clock, clock_limit, | |
6531 | yesno(pipe_config->double_wide)); | |
e29c22c0 | 6532 | return -EINVAL; |
39acb4aa | 6533 | } |
2c07245f | 6534 | } |
89749350 | 6535 | |
1d1d0e27 VS |
6536 | /* |
6537 | * Pipe horizontal size must be even in: | |
6538 | * - DVO ganged mode | |
6539 | * - LVDS dual channel mode | |
6540 | * - Double wide pipe | |
6541 | */ | |
a93e255f | 6542 | if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
6543 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
6544 | pipe_config->pipe_src_w &= ~1; | |
6545 | ||
8693a824 DL |
6546 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6547 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
6548 | */ |
6549 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
aad941d5 | 6550 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) |
e29c22c0 | 6551 | return -EINVAL; |
44f46b42 | 6552 | |
f5adf94e | 6553 | if (HAS_IPS(dev)) |
a43f6e0f DV |
6554 | hsw_compute_ips_config(crtc, pipe_config); |
6555 | ||
877d48d5 | 6556 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 6557 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 6558 | |
cf5a15be | 6559 | return 0; |
79e53945 JB |
6560 | } |
6561 | ||
1652d19e VS |
6562 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
6563 | { | |
6564 | struct drm_i915_private *dev_priv = to_i915(dev); | |
ea61791e | 6565 | uint32_t cdctl; |
1652d19e | 6566 | |
ea61791e | 6567 | skl_dpll0_update(dev_priv); |
1652d19e | 6568 | |
63911d72 | 6569 | if (dev_priv->cdclk_pll.vco == 0) |
709e05c3 | 6570 | return dev_priv->cdclk_pll.ref; |
1652d19e | 6571 | |
ea61791e | 6572 | cdctl = I915_READ(CDCLK_CTL); |
1652d19e | 6573 | |
63911d72 | 6574 | if (dev_priv->cdclk_pll.vco == 8640000) { |
1652d19e VS |
6575 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { |
6576 | case CDCLK_FREQ_450_432: | |
6577 | return 432000; | |
6578 | case CDCLK_FREQ_337_308: | |
487ed2e4 | 6579 | return 308571; |
ea61791e VS |
6580 | case CDCLK_FREQ_540: |
6581 | return 540000; | |
1652d19e | 6582 | case CDCLK_FREQ_675_617: |
487ed2e4 | 6583 | return 617143; |
1652d19e | 6584 | default: |
ea61791e | 6585 | MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); |
1652d19e VS |
6586 | } |
6587 | } else { | |
1652d19e VS |
6588 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { |
6589 | case CDCLK_FREQ_450_432: | |
6590 | return 450000; | |
6591 | case CDCLK_FREQ_337_308: | |
6592 | return 337500; | |
ea61791e VS |
6593 | case CDCLK_FREQ_540: |
6594 | return 540000; | |
1652d19e VS |
6595 | case CDCLK_FREQ_675_617: |
6596 | return 675000; | |
6597 | default: | |
ea61791e | 6598 | MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); |
1652d19e VS |
6599 | } |
6600 | } | |
6601 | ||
709e05c3 | 6602 | return dev_priv->cdclk_pll.ref; |
1652d19e VS |
6603 | } |
6604 | ||
83d7c81f VS |
6605 | static void bxt_de_pll_update(struct drm_i915_private *dev_priv) |
6606 | { | |
6607 | u32 val; | |
6608 | ||
6609 | dev_priv->cdclk_pll.ref = 19200; | |
6610 | ||
6611 | val = I915_READ(BXT_DE_PLL_ENABLE); | |
6612 | if ((val & BXT_DE_PLL_PLL_ENABLE) == 0) { | |
6613 | dev_priv->cdclk_pll.vco = 0; | |
6614 | return; | |
6615 | } | |
6616 | ||
6617 | WARN_ON((val & BXT_DE_PLL_LOCK) == 0); | |
6618 | ||
6619 | val = I915_READ(BXT_DE_PLL_CTL); | |
6620 | dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) * | |
6621 | dev_priv->cdclk_pll.ref; | |
6622 | } | |
6623 | ||
acd3f3d3 BP |
6624 | static int broxton_get_display_clock_speed(struct drm_device *dev) |
6625 | { | |
6626 | struct drm_i915_private *dev_priv = to_i915(dev); | |
f5986242 VS |
6627 | u32 divider; |
6628 | int div, vco; | |
acd3f3d3 | 6629 | |
83d7c81f VS |
6630 | bxt_de_pll_update(dev_priv); |
6631 | ||
f5986242 VS |
6632 | vco = dev_priv->cdclk_pll.vco; |
6633 | if (vco == 0) | |
6634 | return dev_priv->cdclk_pll.ref; | |
acd3f3d3 | 6635 | |
f5986242 | 6636 | divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; |
acd3f3d3 | 6637 | |
f5986242 | 6638 | switch (divider) { |
acd3f3d3 | 6639 | case BXT_CDCLK_CD2X_DIV_SEL_1: |
f5986242 VS |
6640 | div = 2; |
6641 | break; | |
acd3f3d3 | 6642 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: |
f5986242 VS |
6643 | div = 3; |
6644 | break; | |
acd3f3d3 | 6645 | case BXT_CDCLK_CD2X_DIV_SEL_2: |
f5986242 VS |
6646 | div = 4; |
6647 | break; | |
acd3f3d3 | 6648 | case BXT_CDCLK_CD2X_DIV_SEL_4: |
f5986242 VS |
6649 | div = 8; |
6650 | break; | |
6651 | default: | |
6652 | MISSING_CASE(divider); | |
6653 | return dev_priv->cdclk_pll.ref; | |
acd3f3d3 BP |
6654 | } |
6655 | ||
f5986242 | 6656 | return DIV_ROUND_CLOSEST(vco, div); |
acd3f3d3 BP |
6657 | } |
6658 | ||
1652d19e VS |
6659 | static int broadwell_get_display_clock_speed(struct drm_device *dev) |
6660 | { | |
6661 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6662 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6663 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6664 | ||
6665 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6666 | return 800000; | |
6667 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6668 | return 450000; | |
6669 | else if (freq == LCPLL_CLK_FREQ_450) | |
6670 | return 450000; | |
6671 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
6672 | return 540000; | |
6673 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
6674 | return 337500; | |
6675 | else | |
6676 | return 675000; | |
6677 | } | |
6678 | ||
6679 | static int haswell_get_display_clock_speed(struct drm_device *dev) | |
6680 | { | |
6681 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6682 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6683 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6684 | ||
6685 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6686 | return 800000; | |
6687 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6688 | return 450000; | |
6689 | else if (freq == LCPLL_CLK_FREQ_450) | |
6690 | return 450000; | |
6691 | else if (IS_HSW_ULT(dev)) | |
6692 | return 337500; | |
6693 | else | |
6694 | return 540000; | |
79e53945 JB |
6695 | } |
6696 | ||
25eb05fc JB |
6697 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
6698 | { | |
bfa7df01 VS |
6699 | return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk", |
6700 | CCK_DISPLAY_CLOCK_CONTROL); | |
25eb05fc JB |
6701 | } |
6702 | ||
b37a6434 VS |
6703 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
6704 | { | |
6705 | return 450000; | |
6706 | } | |
6707 | ||
e70236a8 JB |
6708 | static int i945_get_display_clock_speed(struct drm_device *dev) |
6709 | { | |
6710 | return 400000; | |
6711 | } | |
79e53945 | 6712 | |
e70236a8 | 6713 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 6714 | { |
e907f170 | 6715 | return 333333; |
e70236a8 | 6716 | } |
79e53945 | 6717 | |
e70236a8 JB |
6718 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
6719 | { | |
6720 | return 200000; | |
6721 | } | |
79e53945 | 6722 | |
257a7ffc DV |
6723 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
6724 | { | |
6725 | u16 gcfgc = 0; | |
6726 | ||
6727 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
6728 | ||
6729 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6730 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 6731 | return 266667; |
257a7ffc | 6732 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 6733 | return 333333; |
257a7ffc | 6734 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 6735 | return 444444; |
257a7ffc DV |
6736 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
6737 | return 200000; | |
6738 | default: | |
6739 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
6740 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 6741 | return 133333; |
257a7ffc | 6742 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 6743 | return 166667; |
257a7ffc DV |
6744 | } |
6745 | } | |
6746 | ||
e70236a8 JB |
6747 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
6748 | { | |
6749 | u16 gcfgc = 0; | |
79e53945 | 6750 | |
e70236a8 JB |
6751 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
6752 | ||
6753 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 6754 | return 133333; |
e70236a8 JB |
6755 | else { |
6756 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6757 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 6758 | return 333333; |
e70236a8 JB |
6759 | default: |
6760 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
6761 | return 190000; | |
79e53945 | 6762 | } |
e70236a8 JB |
6763 | } |
6764 | } | |
6765 | ||
6766 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
6767 | { | |
e907f170 | 6768 | return 266667; |
e70236a8 JB |
6769 | } |
6770 | ||
1b1d2716 | 6771 | static int i85x_get_display_clock_speed(struct drm_device *dev) |
e70236a8 JB |
6772 | { |
6773 | u16 hpllcc = 0; | |
1b1d2716 | 6774 | |
65cd2b3f VS |
6775 | /* |
6776 | * 852GM/852GMV only supports 133 MHz and the HPLLCC | |
6777 | * encoding is different :( | |
6778 | * FIXME is this the right way to detect 852GM/852GMV? | |
6779 | */ | |
6780 | if (dev->pdev->revision == 0x1) | |
6781 | return 133333; | |
6782 | ||
1b1d2716 VS |
6783 | pci_bus_read_config_word(dev->pdev->bus, |
6784 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); | |
6785 | ||
e70236a8 JB |
6786 | /* Assume that the hardware is in the high speed state. This |
6787 | * should be the default. | |
6788 | */ | |
6789 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
6790 | case GC_CLOCK_133_200: | |
1b1d2716 | 6791 | case GC_CLOCK_133_200_2: |
e70236a8 JB |
6792 | case GC_CLOCK_100_200: |
6793 | return 200000; | |
6794 | case GC_CLOCK_166_250: | |
6795 | return 250000; | |
6796 | case GC_CLOCK_100_133: | |
e907f170 | 6797 | return 133333; |
1b1d2716 VS |
6798 | case GC_CLOCK_133_266: |
6799 | case GC_CLOCK_133_266_2: | |
6800 | case GC_CLOCK_166_266: | |
6801 | return 266667; | |
e70236a8 | 6802 | } |
79e53945 | 6803 | |
e70236a8 JB |
6804 | /* Shouldn't happen */ |
6805 | return 0; | |
6806 | } | |
79e53945 | 6807 | |
e70236a8 JB |
6808 | static int i830_get_display_clock_speed(struct drm_device *dev) |
6809 | { | |
e907f170 | 6810 | return 133333; |
79e53945 JB |
6811 | } |
6812 | ||
34edce2f VS |
6813 | static unsigned int intel_hpll_vco(struct drm_device *dev) |
6814 | { | |
6815 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6816 | static const unsigned int blb_vco[8] = { | |
6817 | [0] = 3200000, | |
6818 | [1] = 4000000, | |
6819 | [2] = 5333333, | |
6820 | [3] = 4800000, | |
6821 | [4] = 6400000, | |
6822 | }; | |
6823 | static const unsigned int pnv_vco[8] = { | |
6824 | [0] = 3200000, | |
6825 | [1] = 4000000, | |
6826 | [2] = 5333333, | |
6827 | [3] = 4800000, | |
6828 | [4] = 2666667, | |
6829 | }; | |
6830 | static const unsigned int cl_vco[8] = { | |
6831 | [0] = 3200000, | |
6832 | [1] = 4000000, | |
6833 | [2] = 5333333, | |
6834 | [3] = 6400000, | |
6835 | [4] = 3333333, | |
6836 | [5] = 3566667, | |
6837 | [6] = 4266667, | |
6838 | }; | |
6839 | static const unsigned int elk_vco[8] = { | |
6840 | [0] = 3200000, | |
6841 | [1] = 4000000, | |
6842 | [2] = 5333333, | |
6843 | [3] = 4800000, | |
6844 | }; | |
6845 | static const unsigned int ctg_vco[8] = { | |
6846 | [0] = 3200000, | |
6847 | [1] = 4000000, | |
6848 | [2] = 5333333, | |
6849 | [3] = 6400000, | |
6850 | [4] = 2666667, | |
6851 | [5] = 4266667, | |
6852 | }; | |
6853 | const unsigned int *vco_table; | |
6854 | unsigned int vco; | |
6855 | uint8_t tmp = 0; | |
6856 | ||
6857 | /* FIXME other chipsets? */ | |
6858 | if (IS_GM45(dev)) | |
6859 | vco_table = ctg_vco; | |
6860 | else if (IS_G4X(dev)) | |
6861 | vco_table = elk_vco; | |
6862 | else if (IS_CRESTLINE(dev)) | |
6863 | vco_table = cl_vco; | |
6864 | else if (IS_PINEVIEW(dev)) | |
6865 | vco_table = pnv_vco; | |
6866 | else if (IS_G33(dev)) | |
6867 | vco_table = blb_vco; | |
6868 | else | |
6869 | return 0; | |
6870 | ||
6871 | tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO); | |
6872 | ||
6873 | vco = vco_table[tmp & 0x7]; | |
6874 | if (vco == 0) | |
6875 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); | |
6876 | else | |
6877 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); | |
6878 | ||
6879 | return vco; | |
6880 | } | |
6881 | ||
6882 | static int gm45_get_display_clock_speed(struct drm_device *dev) | |
6883 | { | |
6884 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
6885 | uint16_t tmp = 0; | |
6886 | ||
6887 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
6888 | ||
6889 | cdclk_sel = (tmp >> 12) & 0x1; | |
6890 | ||
6891 | switch (vco) { | |
6892 | case 2666667: | |
6893 | case 4000000: | |
6894 | case 5333333: | |
6895 | return cdclk_sel ? 333333 : 222222; | |
6896 | case 3200000: | |
6897 | return cdclk_sel ? 320000 : 228571; | |
6898 | default: | |
6899 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); | |
6900 | return 222222; | |
6901 | } | |
6902 | } | |
6903 | ||
6904 | static int i965gm_get_display_clock_speed(struct drm_device *dev) | |
6905 | { | |
6906 | static const uint8_t div_3200[] = { 16, 10, 8 }; | |
6907 | static const uint8_t div_4000[] = { 20, 12, 10 }; | |
6908 | static const uint8_t div_5333[] = { 24, 16, 14 }; | |
6909 | const uint8_t *div_table; | |
6910 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
6911 | uint16_t tmp = 0; | |
6912 | ||
6913 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
6914 | ||
6915 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; | |
6916 | ||
6917 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
6918 | goto fail; | |
6919 | ||
6920 | switch (vco) { | |
6921 | case 3200000: | |
6922 | div_table = div_3200; | |
6923 | break; | |
6924 | case 4000000: | |
6925 | div_table = div_4000; | |
6926 | break; | |
6927 | case 5333333: | |
6928 | div_table = div_5333; | |
6929 | break; | |
6930 | default: | |
6931 | goto fail; | |
6932 | } | |
6933 | ||
6934 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
6935 | ||
caf4e252 | 6936 | fail: |
34edce2f VS |
6937 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); |
6938 | return 200000; | |
6939 | } | |
6940 | ||
6941 | static int g33_get_display_clock_speed(struct drm_device *dev) | |
6942 | { | |
6943 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; | |
6944 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; | |
6945 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; | |
6946 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; | |
6947 | const uint8_t *div_table; | |
6948 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
6949 | uint16_t tmp = 0; | |
6950 | ||
6951 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
6952 | ||
6953 | cdclk_sel = (tmp >> 4) & 0x7; | |
6954 | ||
6955 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
6956 | goto fail; | |
6957 | ||
6958 | switch (vco) { | |
6959 | case 3200000: | |
6960 | div_table = div_3200; | |
6961 | break; | |
6962 | case 4000000: | |
6963 | div_table = div_4000; | |
6964 | break; | |
6965 | case 4800000: | |
6966 | div_table = div_4800; | |
6967 | break; | |
6968 | case 5333333: | |
6969 | div_table = div_5333; | |
6970 | break; | |
6971 | default: | |
6972 | goto fail; | |
6973 | } | |
6974 | ||
6975 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
6976 | ||
caf4e252 | 6977 | fail: |
34edce2f VS |
6978 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); |
6979 | return 190476; | |
6980 | } | |
6981 | ||
2c07245f | 6982 | static void |
a65851af | 6983 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 6984 | { |
a65851af VS |
6985 | while (*num > DATA_LINK_M_N_MASK || |
6986 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
6987 | *num >>= 1; |
6988 | *den >>= 1; | |
6989 | } | |
6990 | } | |
6991 | ||
a65851af VS |
6992 | static void compute_m_n(unsigned int m, unsigned int n, |
6993 | uint32_t *ret_m, uint32_t *ret_n) | |
6994 | { | |
6995 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
6996 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
6997 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
6998 | } | |
6999 | ||
e69d0bc1 DV |
7000 | void |
7001 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
7002 | int pixel_clock, int link_clock, | |
7003 | struct intel_link_m_n *m_n) | |
2c07245f | 7004 | { |
e69d0bc1 | 7005 | m_n->tu = 64; |
a65851af VS |
7006 | |
7007 | compute_m_n(bits_per_pixel * pixel_clock, | |
7008 | link_clock * nlanes * 8, | |
7009 | &m_n->gmch_m, &m_n->gmch_n); | |
7010 | ||
7011 | compute_m_n(pixel_clock, link_clock, | |
7012 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
7013 | } |
7014 | ||
a7615030 CW |
7015 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
7016 | { | |
d330a953 JN |
7017 | if (i915.panel_use_ssc >= 0) |
7018 | return i915.panel_use_ssc != 0; | |
41aa3448 | 7019 | return dev_priv->vbt.lvds_use_ssc |
435793df | 7020 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
7021 | } |
7022 | ||
7429e9d4 | 7023 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 7024 | { |
7df00d7a | 7025 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 7026 | } |
f47709a9 | 7027 | |
7429e9d4 DV |
7028 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
7029 | { | |
7030 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
7031 | } |
7032 | ||
f47709a9 | 7033 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 7034 | struct intel_crtc_state *crtc_state, |
9e2c8475 | 7035 | struct dpll *reduced_clock) |
a7516a05 | 7036 | { |
f47709a9 | 7037 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
7038 | u32 fp, fp2 = 0; |
7039 | ||
7040 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 7041 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7042 | if (reduced_clock) |
7429e9d4 | 7043 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 7044 | } else { |
190f68c5 | 7045 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7046 | if (reduced_clock) |
7429e9d4 | 7047 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
7048 | } |
7049 | ||
190f68c5 | 7050 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 7051 | |
f47709a9 | 7052 | crtc->lowfreq_avail = false; |
a93e255f | 7053 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 7054 | reduced_clock) { |
190f68c5 | 7055 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 7056 | crtc->lowfreq_avail = true; |
a7516a05 | 7057 | } else { |
190f68c5 | 7058 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
7059 | } |
7060 | } | |
7061 | ||
5e69f97f CML |
7062 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
7063 | pipe) | |
89b667f8 JB |
7064 | { |
7065 | u32 reg_val; | |
7066 | ||
7067 | /* | |
7068 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
7069 | * and set it to a reasonable value instead. | |
7070 | */ | |
ab3c759a | 7071 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
7072 | reg_val &= 0xffffff00; |
7073 | reg_val |= 0x00000030; | |
ab3c759a | 7074 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7075 | |
ab3c759a | 7076 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7077 | reg_val &= 0x8cffffff; |
7078 | reg_val = 0x8c000000; | |
ab3c759a | 7079 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 7080 | |
ab3c759a | 7081 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 7082 | reg_val &= 0xffffff00; |
ab3c759a | 7083 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7084 | |
ab3c759a | 7085 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7086 | reg_val &= 0x00ffffff; |
7087 | reg_val |= 0xb0000000; | |
ab3c759a | 7088 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
7089 | } |
7090 | ||
b551842d DV |
7091 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
7092 | struct intel_link_m_n *m_n) | |
7093 | { | |
7094 | struct drm_device *dev = crtc->base.dev; | |
7095 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7096 | int pipe = crtc->pipe; | |
7097 | ||
e3b95f1e DV |
7098 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7099 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
7100 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
7101 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
7102 | } |
7103 | ||
7104 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
7105 | struct intel_link_m_n *m_n, |
7106 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
7107 | { |
7108 | struct drm_device *dev = crtc->base.dev; | |
7109 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7110 | int pipe = crtc->pipe; | |
6e3c9717 | 7111 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
7112 | |
7113 | if (INTEL_INFO(dev)->gen >= 5) { | |
7114 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
7115 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
7116 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
7117 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
7118 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
7119 | * for gen < 8) and if DRRS is supported (to make sure the | |
7120 | * registers are not unnecessarily accessed). | |
7121 | */ | |
44395bfe | 7122 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 7123 | crtc->config->has_drrs) { |
f769cd24 VK |
7124 | I915_WRITE(PIPE_DATA_M2(transcoder), |
7125 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
7126 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
7127 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
7128 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
7129 | } | |
b551842d | 7130 | } else { |
e3b95f1e DV |
7131 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7132 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
7133 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
7134 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
7135 | } |
7136 | } | |
7137 | ||
fe3cd48d | 7138 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 7139 | { |
fe3cd48d R |
7140 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
7141 | ||
7142 | if (m_n == M1_N1) { | |
7143 | dp_m_n = &crtc->config->dp_m_n; | |
7144 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
7145 | } else if (m_n == M2_N2) { | |
7146 | ||
7147 | /* | |
7148 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
7149 | * needs to be programmed into M1_N1. | |
7150 | */ | |
7151 | dp_m_n = &crtc->config->dp_m2_n2; | |
7152 | } else { | |
7153 | DRM_ERROR("Unsupported divider value\n"); | |
7154 | return; | |
7155 | } | |
7156 | ||
6e3c9717 ACO |
7157 | if (crtc->config->has_pch_encoder) |
7158 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 7159 | else |
fe3cd48d | 7160 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
7161 | } |
7162 | ||
251ac862 DV |
7163 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
7164 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 | 7165 | { |
03ed5cbf | 7166 | pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | |
cd2d34d9 | 7167 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
7168 | if (crtc->pipe != PIPE_A) |
7169 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
bdd4b6a6 | 7170 | |
cd2d34d9 | 7171 | /* DPLL not used with DSI, but still need the rest set up */ |
187a1c07 | 7172 | if (!pipe_config->has_dsi_encoder) |
cd2d34d9 VS |
7173 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | |
7174 | DPLL_EXT_BUFFER_ENABLE_VLV; | |
7175 | ||
03ed5cbf VS |
7176 | pipe_config->dpll_hw_state.dpll_md = |
7177 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
7178 | } | |
bdd4b6a6 | 7179 | |
03ed5cbf VS |
7180 | static void chv_compute_dpll(struct intel_crtc *crtc, |
7181 | struct intel_crtc_state *pipe_config) | |
7182 | { | |
7183 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | | |
cd2d34d9 | 7184 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
7185 | if (crtc->pipe != PIPE_A) |
7186 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
7187 | ||
cd2d34d9 | 7188 | /* DPLL not used with DSI, but still need the rest set up */ |
187a1c07 | 7189 | if (!pipe_config->has_dsi_encoder) |
cd2d34d9 VS |
7190 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; |
7191 | ||
03ed5cbf VS |
7192 | pipe_config->dpll_hw_state.dpll_md = |
7193 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
bdd4b6a6 DV |
7194 | } |
7195 | ||
d288f65f | 7196 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7197 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 7198 | { |
f47709a9 | 7199 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 7200 | struct drm_i915_private *dev_priv = dev->dev_private; |
cd2d34d9 | 7201 | enum pipe pipe = crtc->pipe; |
bdd4b6a6 | 7202 | u32 mdiv; |
a0c4da24 | 7203 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 7204 | u32 coreclk, reg_val; |
a0c4da24 | 7205 | |
cd2d34d9 VS |
7206 | /* Enable Refclk */ |
7207 | I915_WRITE(DPLL(pipe), | |
7208 | pipe_config->dpll_hw_state.dpll & | |
7209 | ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); | |
7210 | ||
7211 | /* No need to actually set up the DPLL with DSI */ | |
7212 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
7213 | return; | |
7214 | ||
a580516d | 7215 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 7216 | |
d288f65f VS |
7217 | bestn = pipe_config->dpll.n; |
7218 | bestm1 = pipe_config->dpll.m1; | |
7219 | bestm2 = pipe_config->dpll.m2; | |
7220 | bestp1 = pipe_config->dpll.p1; | |
7221 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 7222 | |
89b667f8 JB |
7223 | /* See eDP HDMI DPIO driver vbios notes doc */ |
7224 | ||
7225 | /* PLL B needs special handling */ | |
bdd4b6a6 | 7226 | if (pipe == PIPE_B) |
5e69f97f | 7227 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
7228 | |
7229 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 7230 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
7231 | |
7232 | /* Disable target IRef on PLL */ | |
ab3c759a | 7233 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 7234 | reg_val &= 0x00ffffff; |
ab3c759a | 7235 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
7236 | |
7237 | /* Disable fast lock */ | |
ab3c759a | 7238 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
7239 | |
7240 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
7241 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
7242 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
7243 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 7244 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
7245 | |
7246 | /* | |
7247 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
7248 | * but we don't support that). | |
7249 | * Note: don't use the DAC post divider as it seems unstable. | |
7250 | */ | |
7251 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 7252 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7253 | |
a0c4da24 | 7254 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 7255 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7256 | |
89b667f8 | 7257 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 7258 | if (pipe_config->port_clock == 162000 || |
409ee761 ACO |
7259 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || |
7260 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 7261 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 7262 | 0x009f0003); |
89b667f8 | 7263 | else |
ab3c759a | 7264 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
7265 | 0x00d0000f); |
7266 | ||
681a8504 | 7267 | if (pipe_config->has_dp_encoder) { |
89b667f8 | 7268 | /* Use SSC source */ |
bdd4b6a6 | 7269 | if (pipe == PIPE_A) |
ab3c759a | 7270 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7271 | 0x0df40000); |
7272 | else | |
ab3c759a | 7273 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7274 | 0x0df70000); |
7275 | } else { /* HDMI or VGA */ | |
7276 | /* Use bend source */ | |
bdd4b6a6 | 7277 | if (pipe == PIPE_A) |
ab3c759a | 7278 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7279 | 0x0df70000); |
7280 | else | |
ab3c759a | 7281 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7282 | 0x0df40000); |
7283 | } | |
a0c4da24 | 7284 | |
ab3c759a | 7285 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 7286 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
409ee761 ACO |
7287 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
7288 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) | |
89b667f8 | 7289 | coreclk |= 0x01000000; |
ab3c759a | 7290 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 7291 | |
ab3c759a | 7292 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 7293 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
7294 | } |
7295 | ||
d288f65f | 7296 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7297 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
7298 | { |
7299 | struct drm_device *dev = crtc->base.dev; | |
7300 | struct drm_i915_private *dev_priv = dev->dev_private; | |
cd2d34d9 | 7301 | enum pipe pipe = crtc->pipe; |
9d556c99 | 7302 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9cbe40c1 | 7303 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 7304 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 7305 | u32 dpio_val; |
9cbe40c1 | 7306 | int vco; |
9d556c99 | 7307 | |
cd2d34d9 VS |
7308 | /* Enable Refclk and SSC */ |
7309 | I915_WRITE(DPLL(pipe), | |
7310 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); | |
7311 | ||
7312 | /* No need to actually set up the DPLL with DSI */ | |
7313 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
7314 | return; | |
7315 | ||
d288f65f VS |
7316 | bestn = pipe_config->dpll.n; |
7317 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
7318 | bestm1 = pipe_config->dpll.m1; | |
7319 | bestm2 = pipe_config->dpll.m2 >> 22; | |
7320 | bestp1 = pipe_config->dpll.p1; | |
7321 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 7322 | vco = pipe_config->dpll.vco; |
a945ce7e | 7323 | dpio_val = 0; |
9cbe40c1 | 7324 | loopfilter = 0; |
9d556c99 | 7325 | |
a580516d | 7326 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 7327 | |
9d556c99 CML |
7328 | /* p1 and p2 divider */ |
7329 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
7330 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
7331 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
7332 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
7333 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
7334 | ||
7335 | /* Feedback post-divider - m2 */ | |
7336 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
7337 | ||
7338 | /* Feedback refclk divider - n and m1 */ | |
7339 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
7340 | DPIO_CHV_M1_DIV_BY_2 | | |
7341 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
7342 | ||
7343 | /* M2 fraction division */ | |
25a25dfc | 7344 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
7345 | |
7346 | /* M2 fraction division enable */ | |
a945ce7e VP |
7347 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
7348 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
7349 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
7350 | if (bestm2_frac) | |
7351 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
7352 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 7353 | |
de3a0fde VP |
7354 | /* Program digital lock detect threshold */ |
7355 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
7356 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
7357 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
7358 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
7359 | if (!bestm2_frac) | |
7360 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
7361 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
7362 | ||
9d556c99 | 7363 | /* Loop filter */ |
9cbe40c1 VP |
7364 | if (vco == 5400000) { |
7365 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7366 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
7367 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7368 | tribuf_calcntr = 0x9; | |
7369 | } else if (vco <= 6200000) { | |
7370 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7371 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
7372 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7373 | tribuf_calcntr = 0x9; | |
7374 | } else if (vco <= 6480000) { | |
7375 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7376 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7377 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7378 | tribuf_calcntr = 0x8; | |
7379 | } else { | |
7380 | /* Not supported. Apply the same limits as in the max case */ | |
7381 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7382 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7383 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7384 | tribuf_calcntr = 0; | |
7385 | } | |
9d556c99 CML |
7386 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
7387 | ||
968040b2 | 7388 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
7389 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
7390 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
7391 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
7392 | ||
9d556c99 CML |
7393 | /* AFC Recal */ |
7394 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
7395 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
7396 | DPIO_AFC_RECAL); | |
7397 | ||
a580516d | 7398 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
7399 | } |
7400 | ||
d288f65f VS |
7401 | /** |
7402 | * vlv_force_pll_on - forcibly enable just the PLL | |
7403 | * @dev_priv: i915 private structure | |
7404 | * @pipe: pipe PLL to enable | |
7405 | * @dpll: PLL configuration | |
7406 | * | |
7407 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
7408 | * in cases where we need the PLL enabled even when @pipe is not going to | |
7409 | * be enabled. | |
7410 | */ | |
3f36b937 TU |
7411 | int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, |
7412 | const struct dpll *dpll) | |
d288f65f VS |
7413 | { |
7414 | struct intel_crtc *crtc = | |
7415 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
3f36b937 TU |
7416 | struct intel_crtc_state *pipe_config; |
7417 | ||
7418 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); | |
7419 | if (!pipe_config) | |
7420 | return -ENOMEM; | |
7421 | ||
7422 | pipe_config->base.crtc = &crtc->base; | |
7423 | pipe_config->pixel_multiplier = 1; | |
7424 | pipe_config->dpll = *dpll; | |
d288f65f VS |
7425 | |
7426 | if (IS_CHERRYVIEW(dev)) { | |
3f36b937 TU |
7427 | chv_compute_dpll(crtc, pipe_config); |
7428 | chv_prepare_pll(crtc, pipe_config); | |
7429 | chv_enable_pll(crtc, pipe_config); | |
d288f65f | 7430 | } else { |
3f36b937 TU |
7431 | vlv_compute_dpll(crtc, pipe_config); |
7432 | vlv_prepare_pll(crtc, pipe_config); | |
7433 | vlv_enable_pll(crtc, pipe_config); | |
d288f65f | 7434 | } |
3f36b937 TU |
7435 | |
7436 | kfree(pipe_config); | |
7437 | ||
7438 | return 0; | |
d288f65f VS |
7439 | } |
7440 | ||
7441 | /** | |
7442 | * vlv_force_pll_off - forcibly disable just the PLL | |
7443 | * @dev_priv: i915 private structure | |
7444 | * @pipe: pipe PLL to disable | |
7445 | * | |
7446 | * Disable the PLL for @pipe. To be used in cases where we need | |
7447 | * the PLL enabled even when @pipe is not going to be enabled. | |
7448 | */ | |
7449 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
7450 | { | |
7451 | if (IS_CHERRYVIEW(dev)) | |
7452 | chv_disable_pll(to_i915(dev), pipe); | |
7453 | else | |
7454 | vlv_disable_pll(to_i915(dev), pipe); | |
7455 | } | |
7456 | ||
251ac862 DV |
7457 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
7458 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 7459 | struct dpll *reduced_clock) |
eb1cbe48 | 7460 | { |
f47709a9 | 7461 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7462 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
7463 | u32 dpll; |
7464 | bool is_sdvo; | |
190f68c5 | 7465 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7466 | |
190f68c5 | 7467 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7468 | |
a93e255f ACO |
7469 | is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) || |
7470 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
7471 | |
7472 | dpll = DPLL_VGA_MODE_DIS; | |
7473 | ||
a93e255f | 7474 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
7475 | dpll |= DPLLB_MODE_LVDS; |
7476 | else | |
7477 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 7478 | |
ef1b460d | 7479 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 7480 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 7481 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 7482 | } |
198a037f DV |
7483 | |
7484 | if (is_sdvo) | |
4a33e48d | 7485 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 7486 | |
190f68c5 | 7487 | if (crtc_state->has_dp_encoder) |
4a33e48d | 7488 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
7489 | |
7490 | /* compute bitmask from p1 value */ | |
7491 | if (IS_PINEVIEW(dev)) | |
7492 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
7493 | else { | |
7494 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7495 | if (IS_G4X(dev) && reduced_clock) | |
7496 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
7497 | } | |
7498 | switch (clock->p2) { | |
7499 | case 5: | |
7500 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7501 | break; | |
7502 | case 7: | |
7503 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7504 | break; | |
7505 | case 10: | |
7506 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7507 | break; | |
7508 | case 14: | |
7509 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7510 | break; | |
7511 | } | |
7512 | if (INTEL_INFO(dev)->gen >= 4) | |
7513 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
7514 | ||
190f68c5 | 7515 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 7516 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
a93e255f | 7517 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 7518 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
7519 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
7520 | else | |
7521 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7522 | ||
7523 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7524 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 7525 | |
eb1cbe48 | 7526 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 7527 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7528 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 7529 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
7530 | } |
7531 | } | |
7532 | ||
251ac862 DV |
7533 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
7534 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 7535 | struct dpll *reduced_clock) |
eb1cbe48 | 7536 | { |
f47709a9 | 7537 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7538 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 7539 | u32 dpll; |
190f68c5 | 7540 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7541 | |
190f68c5 | 7542 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7543 | |
eb1cbe48 DV |
7544 | dpll = DPLL_VGA_MODE_DIS; |
7545 | ||
a93e255f | 7546 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
7547 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
7548 | } else { | |
7549 | if (clock->p1 == 2) | |
7550 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
7551 | else | |
7552 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7553 | if (clock->p2 == 4) | |
7554 | dpll |= PLL_P2_DIVIDE_BY_4; | |
7555 | } | |
7556 | ||
a93e255f | 7557 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
7558 | dpll |= DPLL_DVO_2X_MODE; |
7559 | ||
a93e255f | 7560 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 7561 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
7562 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
7563 | else | |
7564 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7565 | ||
7566 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7567 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
7568 | } |
7569 | ||
8a654f3b | 7570 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
7571 | { |
7572 | struct drm_device *dev = intel_crtc->base.dev; | |
7573 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7574 | enum pipe pipe = intel_crtc->pipe; | |
6e3c9717 | 7575 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
7c5f93b0 | 7576 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
7577 | uint32_t crtc_vtotal, crtc_vblank_end; |
7578 | int vsyncshift = 0; | |
4d8a62ea DV |
7579 | |
7580 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
7581 | * the hw state checker will get angry at the mismatch. */ | |
7582 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
7583 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 7584 | |
609aeaca | 7585 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 7586 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
7587 | crtc_vtotal -= 1; |
7588 | crtc_vblank_end -= 1; | |
609aeaca | 7589 | |
409ee761 | 7590 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
7591 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
7592 | else | |
7593 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
7594 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
7595 | if (vsyncshift < 0) |
7596 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
7597 | } |
7598 | ||
7599 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 7600 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 7601 | |
fe2b8f9d | 7602 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
7603 | (adjusted_mode->crtc_hdisplay - 1) | |
7604 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 7605 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
7606 | (adjusted_mode->crtc_hblank_start - 1) | |
7607 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 7608 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
7609 | (adjusted_mode->crtc_hsync_start - 1) | |
7610 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
7611 | ||
fe2b8f9d | 7612 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 7613 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 7614 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 7615 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 7616 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 7617 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 7618 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
7619 | (adjusted_mode->crtc_vsync_start - 1) | |
7620 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
7621 | ||
b5e508d4 PZ |
7622 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
7623 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
7624 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
7625 | * bits. */ | |
7626 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
7627 | (pipe == PIPE_B || pipe == PIPE_C)) | |
7628 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
7629 | ||
bc58be60 JN |
7630 | } |
7631 | ||
7632 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc) | |
7633 | { | |
7634 | struct drm_device *dev = intel_crtc->base.dev; | |
7635 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7636 | enum pipe pipe = intel_crtc->pipe; | |
7637 | ||
b0e77b9c PZ |
7638 | /* pipesrc controls the size that is scaled from, which should |
7639 | * always be the user's requested size. | |
7640 | */ | |
7641 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
7642 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
7643 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
7644 | } |
7645 | ||
1bd1bd80 | 7646 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 7647 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
7648 | { |
7649 | struct drm_device *dev = crtc->base.dev; | |
7650 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7651 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
7652 | uint32_t tmp; | |
7653 | ||
7654 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7655 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
7656 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7657 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
7658 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
7659 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7660 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
7661 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
7662 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7663 | |
7664 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7665 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
7666 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7667 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
7668 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
7669 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7670 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
7671 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
7672 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7673 | |
7674 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
7675 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
7676 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
7677 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 | 7678 | } |
bc58be60 JN |
7679 | } |
7680 | ||
7681 | static void intel_get_pipe_src_size(struct intel_crtc *crtc, | |
7682 | struct intel_crtc_state *pipe_config) | |
7683 | { | |
7684 | struct drm_device *dev = crtc->base.dev; | |
7685 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7686 | u32 tmp; | |
1bd1bd80 DV |
7687 | |
7688 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
7689 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
7690 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
7691 | ||
2d112de7 ACO |
7692 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
7693 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
7694 | } |
7695 | ||
f6a83288 | 7696 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 7697 | struct intel_crtc_state *pipe_config) |
babea61d | 7698 | { |
2d112de7 ACO |
7699 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
7700 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
7701 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
7702 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 7703 | |
2d112de7 ACO |
7704 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
7705 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
7706 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7707 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 7708 | |
2d112de7 | 7709 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 7710 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 7711 | |
2d112de7 ACO |
7712 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
7713 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
cd13f5ab ML |
7714 | |
7715 | mode->hsync = drm_mode_hsync(mode); | |
7716 | mode->vrefresh = drm_mode_vrefresh(mode); | |
7717 | drm_mode_set_name(mode); | |
babea61d JB |
7718 | } |
7719 | ||
84b046f3 DV |
7720 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7721 | { | |
7722 | struct drm_device *dev = intel_crtc->base.dev; | |
7723 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7724 | uint32_t pipeconf; | |
7725 | ||
9f11a9e4 | 7726 | pipeconf = 0; |
84b046f3 | 7727 | |
b6b5d049 VS |
7728 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
7729 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
7730 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 7731 | |
6e3c9717 | 7732 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7733 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7734 | |
ff9ce46e | 7735 | /* only g4x and later have fancy bpc/dither controls */ |
666a4537 | 7736 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
ff9ce46e | 7737 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 7738 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 7739 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 7740 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 7741 | |
6e3c9717 | 7742 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
7743 | case 18: |
7744 | pipeconf |= PIPECONF_6BPC; | |
7745 | break; | |
7746 | case 24: | |
7747 | pipeconf |= PIPECONF_8BPC; | |
7748 | break; | |
7749 | case 30: | |
7750 | pipeconf |= PIPECONF_10BPC; | |
7751 | break; | |
7752 | default: | |
7753 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7754 | BUG(); | |
84b046f3 DV |
7755 | } |
7756 | } | |
7757 | ||
7758 | if (HAS_PIPE_CXSR(dev)) { | |
7759 | if (intel_crtc->lowfreq_avail) { | |
7760 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
7761 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
7762 | } else { | |
7763 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
7764 | } |
7765 | } | |
7766 | ||
6e3c9717 | 7767 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 7768 | if (INTEL_INFO(dev)->gen < 4 || |
409ee761 | 7769 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
7770 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
7771 | else | |
7772 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7773 | } else | |
84b046f3 DV |
7774 | pipeconf |= PIPECONF_PROGRESSIVE; |
7775 | ||
666a4537 WB |
7776 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
7777 | intel_crtc->config->limited_color_range) | |
9f11a9e4 | 7778 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 7779 | |
84b046f3 DV |
7780 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7781 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7782 | } | |
7783 | ||
81c97f52 ACO |
7784 | static int i8xx_crtc_compute_clock(struct intel_crtc *crtc, |
7785 | struct intel_crtc_state *crtc_state) | |
7786 | { | |
7787 | struct drm_device *dev = crtc->base.dev; | |
7788 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1b6f4958 | 7789 | const struct intel_limit *limit; |
81c97f52 ACO |
7790 | int refclk = 48000; |
7791 | ||
7792 | memset(&crtc_state->dpll_hw_state, 0, | |
7793 | sizeof(crtc_state->dpll_hw_state)); | |
7794 | ||
7795 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { | |
7796 | if (intel_panel_use_ssc(dev_priv)) { | |
7797 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7798 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7799 | } | |
7800 | ||
7801 | limit = &intel_limits_i8xx_lvds; | |
7802 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) { | |
7803 | limit = &intel_limits_i8xx_dvo; | |
7804 | } else { | |
7805 | limit = &intel_limits_i8xx_dac; | |
7806 | } | |
7807 | ||
7808 | if (!crtc_state->clock_set && | |
7809 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7810 | refclk, NULL, &crtc_state->dpll)) { | |
7811 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7812 | return -EINVAL; | |
7813 | } | |
7814 | ||
7815 | i8xx_compute_dpll(crtc, crtc_state, NULL); | |
7816 | ||
7817 | return 0; | |
7818 | } | |
7819 | ||
19ec6693 ACO |
7820 | static int g4x_crtc_compute_clock(struct intel_crtc *crtc, |
7821 | struct intel_crtc_state *crtc_state) | |
7822 | { | |
7823 | struct drm_device *dev = crtc->base.dev; | |
7824 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1b6f4958 | 7825 | const struct intel_limit *limit; |
19ec6693 ACO |
7826 | int refclk = 96000; |
7827 | ||
7828 | memset(&crtc_state->dpll_hw_state, 0, | |
7829 | sizeof(crtc_state->dpll_hw_state)); | |
7830 | ||
7831 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { | |
7832 | if (intel_panel_use_ssc(dev_priv)) { | |
7833 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7834 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7835 | } | |
7836 | ||
7837 | if (intel_is_dual_link_lvds(dev)) | |
7838 | limit = &intel_limits_g4x_dual_channel_lvds; | |
7839 | else | |
7840 | limit = &intel_limits_g4x_single_channel_lvds; | |
7841 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) || | |
7842 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
7843 | limit = &intel_limits_g4x_hdmi; | |
7844 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) { | |
7845 | limit = &intel_limits_g4x_sdvo; | |
7846 | } else { | |
7847 | /* The option is for other outputs */ | |
7848 | limit = &intel_limits_i9xx_sdvo; | |
7849 | } | |
7850 | ||
7851 | if (!crtc_state->clock_set && | |
7852 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7853 | refclk, NULL, &crtc_state->dpll)) { | |
7854 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7855 | return -EINVAL; | |
7856 | } | |
7857 | ||
7858 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
7859 | ||
7860 | return 0; | |
7861 | } | |
7862 | ||
70e8aa21 ACO |
7863 | static int pnv_crtc_compute_clock(struct intel_crtc *crtc, |
7864 | struct intel_crtc_state *crtc_state) | |
7865 | { | |
7866 | struct drm_device *dev = crtc->base.dev; | |
7867 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1b6f4958 | 7868 | const struct intel_limit *limit; |
70e8aa21 ACO |
7869 | int refclk = 96000; |
7870 | ||
7871 | memset(&crtc_state->dpll_hw_state, 0, | |
7872 | sizeof(crtc_state->dpll_hw_state)); | |
7873 | ||
7874 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { | |
7875 | if (intel_panel_use_ssc(dev_priv)) { | |
7876 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7877 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7878 | } | |
7879 | ||
7880 | limit = &intel_limits_pineview_lvds; | |
7881 | } else { | |
7882 | limit = &intel_limits_pineview_sdvo; | |
7883 | } | |
7884 | ||
7885 | if (!crtc_state->clock_set && | |
7886 | !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7887 | refclk, NULL, &crtc_state->dpll)) { | |
7888 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7889 | return -EINVAL; | |
7890 | } | |
7891 | ||
7892 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
7893 | ||
7894 | return 0; | |
7895 | } | |
7896 | ||
190f68c5 ACO |
7897 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
7898 | struct intel_crtc_state *crtc_state) | |
79e53945 | 7899 | { |
c7653199 | 7900 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 7901 | struct drm_i915_private *dev_priv = dev->dev_private; |
1b6f4958 | 7902 | const struct intel_limit *limit; |
81c97f52 | 7903 | int refclk = 96000; |
79e53945 | 7904 | |
dd3cd74a ACO |
7905 | memset(&crtc_state->dpll_hw_state, 0, |
7906 | sizeof(crtc_state->dpll_hw_state)); | |
7907 | ||
70e8aa21 ACO |
7908 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
7909 | if (intel_panel_use_ssc(dev_priv)) { | |
7910 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7911 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7912 | } | |
43565a06 | 7913 | |
70e8aa21 ACO |
7914 | limit = &intel_limits_i9xx_lvds; |
7915 | } else { | |
7916 | limit = &intel_limits_i9xx_sdvo; | |
81c97f52 | 7917 | } |
79e53945 | 7918 | |
70e8aa21 ACO |
7919 | if (!crtc_state->clock_set && |
7920 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7921 | refclk, NULL, &crtc_state->dpll)) { | |
7922 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7923 | return -EINVAL; | |
f47709a9 | 7924 | } |
7026d4ac | 7925 | |
81c97f52 | 7926 | i9xx_compute_dpll(crtc, crtc_state, NULL); |
79e53945 | 7927 | |
c8f7a0db | 7928 | return 0; |
f564048e EA |
7929 | } |
7930 | ||
65b3d6a9 ACO |
7931 | static int chv_crtc_compute_clock(struct intel_crtc *crtc, |
7932 | struct intel_crtc_state *crtc_state) | |
7933 | { | |
7934 | int refclk = 100000; | |
1b6f4958 | 7935 | const struct intel_limit *limit = &intel_limits_chv; |
65b3d6a9 ACO |
7936 | |
7937 | memset(&crtc_state->dpll_hw_state, 0, | |
7938 | sizeof(crtc_state->dpll_hw_state)); | |
7939 | ||
65b3d6a9 ACO |
7940 | if (!crtc_state->clock_set && |
7941 | !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7942 | refclk, NULL, &crtc_state->dpll)) { | |
7943 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7944 | return -EINVAL; | |
7945 | } | |
7946 | ||
7947 | chv_compute_dpll(crtc, crtc_state); | |
7948 | ||
7949 | return 0; | |
7950 | } | |
7951 | ||
7952 | static int vlv_crtc_compute_clock(struct intel_crtc *crtc, | |
7953 | struct intel_crtc_state *crtc_state) | |
7954 | { | |
7955 | int refclk = 100000; | |
1b6f4958 | 7956 | const struct intel_limit *limit = &intel_limits_vlv; |
65b3d6a9 ACO |
7957 | |
7958 | memset(&crtc_state->dpll_hw_state, 0, | |
7959 | sizeof(crtc_state->dpll_hw_state)); | |
7960 | ||
65b3d6a9 ACO |
7961 | if (!crtc_state->clock_set && |
7962 | !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7963 | refclk, NULL, &crtc_state->dpll)) { | |
7964 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7965 | return -EINVAL; | |
7966 | } | |
7967 | ||
7968 | vlv_compute_dpll(crtc, crtc_state); | |
7969 | ||
7970 | return 0; | |
7971 | } | |
7972 | ||
2fa2fe9a | 7973 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 7974 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
7975 | { |
7976 | struct drm_device *dev = crtc->base.dev; | |
7977 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7978 | uint32_t tmp; | |
7979 | ||
dc9e7dec VS |
7980 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
7981 | return; | |
7982 | ||
2fa2fe9a | 7983 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
7984 | if (!(tmp & PFIT_ENABLE)) |
7985 | return; | |
2fa2fe9a | 7986 | |
06922821 | 7987 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
7988 | if (INTEL_INFO(dev)->gen < 4) { |
7989 | if (crtc->pipe != PIPE_B) | |
7990 | return; | |
2fa2fe9a DV |
7991 | } else { |
7992 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
7993 | return; | |
7994 | } | |
7995 | ||
06922821 | 7996 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a | 7997 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
2fa2fe9a DV |
7998 | } |
7999 | ||
acbec814 | 8000 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8001 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
8002 | { |
8003 | struct drm_device *dev = crtc->base.dev; | |
8004 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8005 | int pipe = pipe_config->cpu_transcoder; | |
9e2c8475 | 8006 | struct dpll clock; |
acbec814 | 8007 | u32 mdiv; |
662c6ecb | 8008 | int refclk = 100000; |
acbec814 | 8009 | |
b521973b VS |
8010 | /* In case of DSI, DPLL will not be used */ |
8011 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
f573de5a SK |
8012 | return; |
8013 | ||
a580516d | 8014 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 8015 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 8016 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
8017 | |
8018 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
8019 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
8020 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
8021 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
8022 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
8023 | ||
dccbea3b | 8024 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
8025 | } |
8026 | ||
5724dbd1 DL |
8027 | static void |
8028 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
8029 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
8030 | { |
8031 | struct drm_device *dev = crtc->base.dev; | |
8032 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8033 | u32 val, base, offset; | |
8034 | int pipe = crtc->pipe, plane = crtc->plane; | |
8035 | int fourcc, pixel_format; | |
6761dd31 | 8036 | unsigned int aligned_height; |
b113d5ee | 8037 | struct drm_framebuffer *fb; |
1b842c89 | 8038 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 8039 | |
42a7b088 DL |
8040 | val = I915_READ(DSPCNTR(plane)); |
8041 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8042 | return; | |
8043 | ||
d9806c9f | 8044 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8045 | if (!intel_fb) { |
1ad292b5 JB |
8046 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8047 | return; | |
8048 | } | |
8049 | ||
1b842c89 DL |
8050 | fb = &intel_fb->base; |
8051 | ||
18c5247e DV |
8052 | if (INTEL_INFO(dev)->gen >= 4) { |
8053 | if (val & DISPPLANE_TILED) { | |
49af449b | 8054 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
8055 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
8056 | } | |
8057 | } | |
1ad292b5 JB |
8058 | |
8059 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8060 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
8061 | fb->pixel_format = fourcc; |
8062 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
8063 | |
8064 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 8065 | if (plane_config->tiling) |
1ad292b5 JB |
8066 | offset = I915_READ(DSPTILEOFF(plane)); |
8067 | else | |
8068 | offset = I915_READ(DSPLINOFF(plane)); | |
8069 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
8070 | } else { | |
8071 | base = I915_READ(DSPADDR(plane)); | |
8072 | } | |
8073 | plane_config->base = base; | |
8074 | ||
8075 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8076 | fb->width = ((val >> 16) & 0xfff) + 1; |
8077 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
8078 | |
8079 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8080 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 8081 | |
b113d5ee | 8082 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
8083 | fb->pixel_format, |
8084 | fb->modifier[0]); | |
1ad292b5 | 8085 | |
f37b5c2b | 8086 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 8087 | |
2844a921 DL |
8088 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8089 | pipe_name(pipe), plane, fb->width, fb->height, | |
8090 | fb->bits_per_pixel, base, fb->pitches[0], | |
8091 | plane_config->size); | |
1ad292b5 | 8092 | |
2d14030b | 8093 | plane_config->fb = intel_fb; |
1ad292b5 JB |
8094 | } |
8095 | ||
70b23a98 | 8096 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8097 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
8098 | { |
8099 | struct drm_device *dev = crtc->base.dev; | |
8100 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8101 | int pipe = pipe_config->cpu_transcoder; | |
8102 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9e2c8475 | 8103 | struct dpll clock; |
0d7b6b11 | 8104 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
8105 | int refclk = 100000; |
8106 | ||
b521973b VS |
8107 | /* In case of DSI, DPLL will not be used */ |
8108 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
8109 | return; | |
8110 | ||
a580516d | 8111 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
8112 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
8113 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
8114 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
8115 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 8116 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 8117 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
8118 | |
8119 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
8120 | clock.m2 = (pll_dw0 & 0xff) << 22; |
8121 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
8122 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
8123 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
8124 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
8125 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
8126 | ||
dccbea3b | 8127 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
8128 | } |
8129 | ||
0e8ffe1b | 8130 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8131 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8132 | { |
8133 | struct drm_device *dev = crtc->base.dev; | |
8134 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1729050e | 8135 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 8136 | uint32_t tmp; |
1729050e | 8137 | bool ret; |
0e8ffe1b | 8138 | |
1729050e ID |
8139 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
8140 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 ID |
8141 | return false; |
8142 | ||
e143a21c | 8143 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 8144 | pipe_config->shared_dpll = NULL; |
eccb140b | 8145 | |
1729050e ID |
8146 | ret = false; |
8147 | ||
0e8ffe1b DV |
8148 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8149 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 8150 | goto out; |
0e8ffe1b | 8151 | |
666a4537 | 8152 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
42571aef VS |
8153 | switch (tmp & PIPECONF_BPC_MASK) { |
8154 | case PIPECONF_6BPC: | |
8155 | pipe_config->pipe_bpp = 18; | |
8156 | break; | |
8157 | case PIPECONF_8BPC: | |
8158 | pipe_config->pipe_bpp = 24; | |
8159 | break; | |
8160 | case PIPECONF_10BPC: | |
8161 | pipe_config->pipe_bpp = 30; | |
8162 | break; | |
8163 | default: | |
8164 | break; | |
8165 | } | |
8166 | } | |
8167 | ||
666a4537 WB |
8168 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
8169 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) | |
b5a9fa09 DV |
8170 | pipe_config->limited_color_range = true; |
8171 | ||
282740f7 VS |
8172 | if (INTEL_INFO(dev)->gen < 4) |
8173 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
8174 | ||
1bd1bd80 | 8175 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 8176 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 8177 | |
2fa2fe9a DV |
8178 | i9xx_get_pfit_config(crtc, pipe_config); |
8179 | ||
6c49f241 | 8180 | if (INTEL_INFO(dev)->gen >= 4) { |
c231775c VS |
8181 | /* No way to read it out on pipes B and C */ |
8182 | if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A) | |
8183 | tmp = dev_priv->chv_dpll_md[crtc->pipe]; | |
8184 | else | |
8185 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
6c49f241 DV |
8186 | pipe_config->pixel_multiplier = |
8187 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
8188 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 8189 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
8190 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
8191 | tmp = I915_READ(DPLL(crtc->pipe)); | |
8192 | pipe_config->pixel_multiplier = | |
8193 | ((tmp & SDVO_MULTIPLIER_MASK) | |
8194 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
8195 | } else { | |
8196 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
8197 | * port and will be fixed up in the encoder->get_config | |
8198 | * function. */ | |
8199 | pipe_config->pixel_multiplier = 1; | |
8200 | } | |
8bcc2795 | 8201 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
666a4537 | 8202 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
1c4e0274 VS |
8203 | /* |
8204 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
8205 | * on 830. Filter it out here so that we don't | |
8206 | * report errors due to that. | |
8207 | */ | |
8208 | if (IS_I830(dev)) | |
8209 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
8210 | ||
8bcc2795 DV |
8211 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
8212 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
8213 | } else { |
8214 | /* Mask out read-only status bits. */ | |
8215 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
8216 | DPLL_PORTC_READY_MASK | | |
8217 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 8218 | } |
6c49f241 | 8219 | |
70b23a98 VS |
8220 | if (IS_CHERRYVIEW(dev)) |
8221 | chv_crtc_clock_get(crtc, pipe_config); | |
8222 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
8223 | vlv_crtc_clock_get(crtc, pipe_config); |
8224 | else | |
8225 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 8226 | |
0f64614d VS |
8227 | /* |
8228 | * Normally the dotclock is filled in by the encoder .get_config() | |
8229 | * but in case the pipe is enabled w/o any ports we need a sane | |
8230 | * default. | |
8231 | */ | |
8232 | pipe_config->base.adjusted_mode.crtc_clock = | |
8233 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
8234 | ||
1729050e ID |
8235 | ret = true; |
8236 | ||
8237 | out: | |
8238 | intel_display_power_put(dev_priv, power_domain); | |
8239 | ||
8240 | return ret; | |
0e8ffe1b DV |
8241 | } |
8242 | ||
dde86e2d | 8243 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
8244 | { |
8245 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 8246 | struct intel_encoder *encoder; |
74cfd7ac | 8247 | u32 val, final; |
13d83a67 | 8248 | bool has_lvds = false; |
199e5d79 | 8249 | bool has_cpu_edp = false; |
199e5d79 | 8250 | bool has_panel = false; |
99eb6a01 KP |
8251 | bool has_ck505 = false; |
8252 | bool can_ssc = false; | |
13d83a67 JB |
8253 | |
8254 | /* We need to take the global config into account */ | |
b2784e15 | 8255 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
8256 | switch (encoder->type) { |
8257 | case INTEL_OUTPUT_LVDS: | |
8258 | has_panel = true; | |
8259 | has_lvds = true; | |
8260 | break; | |
8261 | case INTEL_OUTPUT_EDP: | |
8262 | has_panel = true; | |
2de6905f | 8263 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
8264 | has_cpu_edp = true; |
8265 | break; | |
6847d71b PZ |
8266 | default: |
8267 | break; | |
13d83a67 JB |
8268 | } |
8269 | } | |
8270 | ||
99eb6a01 | 8271 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 8272 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
8273 | can_ssc = has_ck505; |
8274 | } else { | |
8275 | has_ck505 = false; | |
8276 | can_ssc = true; | |
8277 | } | |
8278 | ||
2de6905f ID |
8279 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
8280 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
8281 | |
8282 | /* Ironlake: try to setup display ref clock before DPLL | |
8283 | * enabling. This is only under driver's control after | |
8284 | * PCH B stepping, previous chipset stepping should be | |
8285 | * ignoring this setting. | |
8286 | */ | |
74cfd7ac CW |
8287 | val = I915_READ(PCH_DREF_CONTROL); |
8288 | ||
8289 | /* As we must carefully and slowly disable/enable each source in turn, | |
8290 | * compute the final state we want first and check if we need to | |
8291 | * make any changes at all. | |
8292 | */ | |
8293 | final = val; | |
8294 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
8295 | if (has_ck505) | |
8296 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
8297 | else | |
8298 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
8299 | ||
8300 | final &= ~DREF_SSC_SOURCE_MASK; | |
8301 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
8302 | final &= ~DREF_SSC1_ENABLE; | |
8303 | ||
8304 | if (has_panel) { | |
8305 | final |= DREF_SSC_SOURCE_ENABLE; | |
8306 | ||
8307 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8308 | final |= DREF_SSC1_ENABLE; | |
8309 | ||
8310 | if (has_cpu_edp) { | |
8311 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8312 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
8313 | else | |
8314 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
8315 | } else | |
8316 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8317 | } else { | |
8318 | final |= DREF_SSC_SOURCE_DISABLE; | |
8319 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8320 | } | |
8321 | ||
8322 | if (final == val) | |
8323 | return; | |
8324 | ||
13d83a67 | 8325 | /* Always enable nonspread source */ |
74cfd7ac | 8326 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 8327 | |
99eb6a01 | 8328 | if (has_ck505) |
74cfd7ac | 8329 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 8330 | else |
74cfd7ac | 8331 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 8332 | |
199e5d79 | 8333 | if (has_panel) { |
74cfd7ac CW |
8334 | val &= ~DREF_SSC_SOURCE_MASK; |
8335 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 8336 | |
199e5d79 | 8337 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 8338 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8339 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 8340 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 8341 | } else |
74cfd7ac | 8342 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
8343 | |
8344 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 8345 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8346 | POSTING_READ(PCH_DREF_CONTROL); |
8347 | udelay(200); | |
8348 | ||
74cfd7ac | 8349 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
8350 | |
8351 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 8352 | if (has_cpu_edp) { |
99eb6a01 | 8353 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8354 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 8355 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 8356 | } else |
74cfd7ac | 8357 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 8358 | } else |
74cfd7ac | 8359 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8360 | |
74cfd7ac | 8361 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8362 | POSTING_READ(PCH_DREF_CONTROL); |
8363 | udelay(200); | |
8364 | } else { | |
8365 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
8366 | ||
74cfd7ac | 8367 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
8368 | |
8369 | /* Turn off CPU output */ | |
74cfd7ac | 8370 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8371 | |
74cfd7ac | 8372 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8373 | POSTING_READ(PCH_DREF_CONTROL); |
8374 | udelay(200); | |
8375 | ||
8376 | /* Turn off the SSC source */ | |
74cfd7ac CW |
8377 | val &= ~DREF_SSC_SOURCE_MASK; |
8378 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
8379 | |
8380 | /* Turn off SSC1 */ | |
74cfd7ac | 8381 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 8382 | |
74cfd7ac | 8383 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
8384 | POSTING_READ(PCH_DREF_CONTROL); |
8385 | udelay(200); | |
8386 | } | |
74cfd7ac CW |
8387 | |
8388 | BUG_ON(val != final); | |
13d83a67 JB |
8389 | } |
8390 | ||
f31f2d55 | 8391 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 8392 | { |
f31f2d55 | 8393 | uint32_t tmp; |
dde86e2d | 8394 | |
0ff066a9 PZ |
8395 | tmp = I915_READ(SOUTH_CHICKEN2); |
8396 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
8397 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8398 | |
0ff066a9 PZ |
8399 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
8400 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
8401 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 8402 | |
0ff066a9 PZ |
8403 | tmp = I915_READ(SOUTH_CHICKEN2); |
8404 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
8405 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8406 | |
0ff066a9 PZ |
8407 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
8408 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
8409 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
8410 | } |
8411 | ||
8412 | /* WaMPhyProgramming:hsw */ | |
8413 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
8414 | { | |
8415 | uint32_t tmp; | |
dde86e2d PZ |
8416 | |
8417 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
8418 | tmp &= ~(0xFF << 24); | |
8419 | tmp |= (0x12 << 24); | |
8420 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
8421 | ||
dde86e2d PZ |
8422 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
8423 | tmp |= (1 << 11); | |
8424 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
8425 | ||
8426 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
8427 | tmp |= (1 << 11); | |
8428 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
8429 | ||
dde86e2d PZ |
8430 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
8431 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8432 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
8433 | ||
8434 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
8435 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8436 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
8437 | ||
0ff066a9 PZ |
8438 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
8439 | tmp &= ~(7 << 13); | |
8440 | tmp |= (5 << 13); | |
8441 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 8442 | |
0ff066a9 PZ |
8443 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
8444 | tmp &= ~(7 << 13); | |
8445 | tmp |= (5 << 13); | |
8446 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
8447 | |
8448 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
8449 | tmp &= ~0xFF; | |
8450 | tmp |= 0x1C; | |
8451 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
8452 | ||
8453 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
8454 | tmp &= ~0xFF; | |
8455 | tmp |= 0x1C; | |
8456 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
8457 | ||
8458 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
8459 | tmp &= ~(0xFF << 16); | |
8460 | tmp |= (0x1C << 16); | |
8461 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
8462 | ||
8463 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
8464 | tmp &= ~(0xFF << 16); | |
8465 | tmp |= (0x1C << 16); | |
8466 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
8467 | ||
0ff066a9 PZ |
8468 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
8469 | tmp |= (1 << 27); | |
8470 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 8471 | |
0ff066a9 PZ |
8472 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
8473 | tmp |= (1 << 27); | |
8474 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 8475 | |
0ff066a9 PZ |
8476 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
8477 | tmp &= ~(0xF << 28); | |
8478 | tmp |= (4 << 28); | |
8479 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 8480 | |
0ff066a9 PZ |
8481 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
8482 | tmp &= ~(0xF << 28); | |
8483 | tmp |= (4 << 28); | |
8484 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
8485 | } |
8486 | ||
2fa86a1f PZ |
8487 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
8488 | * Programming" based on the parameters passed: | |
8489 | * - Sequence to enable CLKOUT_DP | |
8490 | * - Sequence to enable CLKOUT_DP without spread | |
8491 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
8492 | */ | |
8493 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
8494 | bool with_fdi) | |
f31f2d55 PZ |
8495 | { |
8496 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
8497 | uint32_t reg, tmp; |
8498 | ||
8499 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
8500 | with_spread = true; | |
c2699524 | 8501 | if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n")) |
2fa86a1f | 8502 | with_fdi = false; |
f31f2d55 | 8503 | |
a580516d | 8504 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
8505 | |
8506 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8507 | tmp &= ~SBI_SSCCTL_DISABLE; | |
8508 | tmp |= SBI_SSCCTL_PATHALT; | |
8509 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8510 | ||
8511 | udelay(24); | |
8512 | ||
2fa86a1f PZ |
8513 | if (with_spread) { |
8514 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8515 | tmp &= ~SBI_SSCCTL_PATHALT; | |
8516 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 8517 | |
2fa86a1f PZ |
8518 | if (with_fdi) { |
8519 | lpt_reset_fdi_mphy(dev_priv); | |
8520 | lpt_program_fdi_mphy(dev_priv); | |
8521 | } | |
8522 | } | |
dde86e2d | 8523 | |
c2699524 | 8524 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
8525 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8526 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8527 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 8528 | |
a580516d | 8529 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
8530 | } |
8531 | ||
47701c3b PZ |
8532 | /* Sequence to disable CLKOUT_DP */ |
8533 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
8534 | { | |
8535 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8536 | uint32_t reg, tmp; | |
8537 | ||
a580516d | 8538 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 8539 | |
c2699524 | 8540 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
8541 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8542 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8543 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
8544 | ||
8545 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8546 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
8547 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
8548 | tmp |= SBI_SSCCTL_PATHALT; | |
8549 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8550 | udelay(32); | |
8551 | } | |
8552 | tmp |= SBI_SSCCTL_DISABLE; | |
8553 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8554 | } | |
8555 | ||
a580516d | 8556 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
8557 | } |
8558 | ||
f7be2c21 VS |
8559 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
8560 | ||
8561 | static const uint16_t sscdivintphase[] = { | |
8562 | [BEND_IDX( 50)] = 0x3B23, | |
8563 | [BEND_IDX( 45)] = 0x3B23, | |
8564 | [BEND_IDX( 40)] = 0x3C23, | |
8565 | [BEND_IDX( 35)] = 0x3C23, | |
8566 | [BEND_IDX( 30)] = 0x3D23, | |
8567 | [BEND_IDX( 25)] = 0x3D23, | |
8568 | [BEND_IDX( 20)] = 0x3E23, | |
8569 | [BEND_IDX( 15)] = 0x3E23, | |
8570 | [BEND_IDX( 10)] = 0x3F23, | |
8571 | [BEND_IDX( 5)] = 0x3F23, | |
8572 | [BEND_IDX( 0)] = 0x0025, | |
8573 | [BEND_IDX( -5)] = 0x0025, | |
8574 | [BEND_IDX(-10)] = 0x0125, | |
8575 | [BEND_IDX(-15)] = 0x0125, | |
8576 | [BEND_IDX(-20)] = 0x0225, | |
8577 | [BEND_IDX(-25)] = 0x0225, | |
8578 | [BEND_IDX(-30)] = 0x0325, | |
8579 | [BEND_IDX(-35)] = 0x0325, | |
8580 | [BEND_IDX(-40)] = 0x0425, | |
8581 | [BEND_IDX(-45)] = 0x0425, | |
8582 | [BEND_IDX(-50)] = 0x0525, | |
8583 | }; | |
8584 | ||
8585 | /* | |
8586 | * Bend CLKOUT_DP | |
8587 | * steps -50 to 50 inclusive, in steps of 5 | |
8588 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) | |
8589 | * change in clock period = -(steps / 10) * 5.787 ps | |
8590 | */ | |
8591 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) | |
8592 | { | |
8593 | uint32_t tmp; | |
8594 | int idx = BEND_IDX(steps); | |
8595 | ||
8596 | if (WARN_ON(steps % 5 != 0)) | |
8597 | return; | |
8598 | ||
8599 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) | |
8600 | return; | |
8601 | ||
8602 | mutex_lock(&dev_priv->sb_lock); | |
8603 | ||
8604 | if (steps % 10 != 0) | |
8605 | tmp = 0xAAAAAAAB; | |
8606 | else | |
8607 | tmp = 0x00000000; | |
8608 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); | |
8609 | ||
8610 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); | |
8611 | tmp &= 0xffff0000; | |
8612 | tmp |= sscdivintphase[idx]; | |
8613 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); | |
8614 | ||
8615 | mutex_unlock(&dev_priv->sb_lock); | |
8616 | } | |
8617 | ||
8618 | #undef BEND_IDX | |
8619 | ||
bf8fa3d3 PZ |
8620 | static void lpt_init_pch_refclk(struct drm_device *dev) |
8621 | { | |
bf8fa3d3 PZ |
8622 | struct intel_encoder *encoder; |
8623 | bool has_vga = false; | |
8624 | ||
b2784e15 | 8625 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
8626 | switch (encoder->type) { |
8627 | case INTEL_OUTPUT_ANALOG: | |
8628 | has_vga = true; | |
8629 | break; | |
6847d71b PZ |
8630 | default: |
8631 | break; | |
bf8fa3d3 PZ |
8632 | } |
8633 | } | |
8634 | ||
f7be2c21 VS |
8635 | if (has_vga) { |
8636 | lpt_bend_clkout_dp(to_i915(dev), 0); | |
47701c3b | 8637 | lpt_enable_clkout_dp(dev, true, true); |
f7be2c21 | 8638 | } else { |
47701c3b | 8639 | lpt_disable_clkout_dp(dev); |
f7be2c21 | 8640 | } |
bf8fa3d3 PZ |
8641 | } |
8642 | ||
dde86e2d PZ |
8643 | /* |
8644 | * Initialize reference clocks when the driver loads | |
8645 | */ | |
8646 | void intel_init_pch_refclk(struct drm_device *dev) | |
8647 | { | |
8648 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
8649 | ironlake_init_pch_refclk(dev); | |
8650 | else if (HAS_PCH_LPT(dev)) | |
8651 | lpt_init_pch_refclk(dev); | |
8652 | } | |
8653 | ||
6ff93609 | 8654 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 8655 | { |
c8203565 | 8656 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
8657 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8658 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
8659 | uint32_t val; |
8660 | ||
78114071 | 8661 | val = 0; |
c8203565 | 8662 | |
6e3c9717 | 8663 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 8664 | case 18: |
dfd07d72 | 8665 | val |= PIPECONF_6BPC; |
c8203565 PZ |
8666 | break; |
8667 | case 24: | |
dfd07d72 | 8668 | val |= PIPECONF_8BPC; |
c8203565 PZ |
8669 | break; |
8670 | case 30: | |
dfd07d72 | 8671 | val |= PIPECONF_10BPC; |
c8203565 PZ |
8672 | break; |
8673 | case 36: | |
dfd07d72 | 8674 | val |= PIPECONF_12BPC; |
c8203565 PZ |
8675 | break; |
8676 | default: | |
cc769b62 PZ |
8677 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
8678 | BUG(); | |
c8203565 PZ |
8679 | } |
8680 | ||
6e3c9717 | 8681 | if (intel_crtc->config->dither) |
c8203565 PZ |
8682 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8683 | ||
6e3c9717 | 8684 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
8685 | val |= PIPECONF_INTERLACED_ILK; |
8686 | else | |
8687 | val |= PIPECONF_PROGRESSIVE; | |
8688 | ||
6e3c9717 | 8689 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 8690 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 8691 | |
c8203565 PZ |
8692 | I915_WRITE(PIPECONF(pipe), val); |
8693 | POSTING_READ(PIPECONF(pipe)); | |
8694 | } | |
8695 | ||
6ff93609 | 8696 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8697 | { |
391bf048 | 8698 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
ee2b0b38 | 8699 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 8700 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
391bf048 | 8701 | u32 val = 0; |
ee2b0b38 | 8702 | |
391bf048 | 8703 | if (IS_HASWELL(dev_priv) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8704 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8705 | ||
6e3c9717 | 8706 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8707 | val |= PIPECONF_INTERLACED_ILK; |
8708 | else | |
8709 | val |= PIPECONF_PROGRESSIVE; | |
8710 | ||
702e7a56 PZ |
8711 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8712 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
391bf048 JN |
8713 | } |
8714 | ||
391bf048 JN |
8715 | static void haswell_set_pipemisc(struct drm_crtc *crtc) |
8716 | { | |
8717 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
8718 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
756f85cf | 8719 | |
391bf048 JN |
8720 | if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) { |
8721 | u32 val = 0; | |
756f85cf | 8722 | |
6e3c9717 | 8723 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8724 | case 18: |
8725 | val |= PIPEMISC_DITHER_6_BPC; | |
8726 | break; | |
8727 | case 24: | |
8728 | val |= PIPEMISC_DITHER_8_BPC; | |
8729 | break; | |
8730 | case 30: | |
8731 | val |= PIPEMISC_DITHER_10_BPC; | |
8732 | break; | |
8733 | case 36: | |
8734 | val |= PIPEMISC_DITHER_12_BPC; | |
8735 | break; | |
8736 | default: | |
8737 | /* Case prevented by pipe_config_set_bpp. */ | |
8738 | BUG(); | |
8739 | } | |
8740 | ||
6e3c9717 | 8741 | if (intel_crtc->config->dither) |
756f85cf PZ |
8742 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8743 | ||
391bf048 | 8744 | I915_WRITE(PIPEMISC(intel_crtc->pipe), val); |
756f85cf | 8745 | } |
ee2b0b38 PZ |
8746 | } |
8747 | ||
d4b1931c PZ |
8748 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
8749 | { | |
8750 | /* | |
8751 | * Account for spread spectrum to avoid | |
8752 | * oversubscribing the link. Max center spread | |
8753 | * is 2.5%; use 5% for safety's sake. | |
8754 | */ | |
8755 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 8756 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
8757 | } |
8758 | ||
7429e9d4 | 8759 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 8760 | { |
7429e9d4 | 8761 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
8762 | } |
8763 | ||
b75ca6f6 ACO |
8764 | static void ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
8765 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 8766 | struct dpll *reduced_clock) |
79e53945 | 8767 | { |
de13a2e3 | 8768 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
8769 | struct drm_device *dev = crtc->dev; |
8770 | struct drm_i915_private *dev_priv = dev->dev_private; | |
55bb9992 | 8771 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8772 | struct drm_connector *connector; |
55bb9992 ACO |
8773 | struct drm_connector_state *connector_state; |
8774 | struct intel_encoder *encoder; | |
b75ca6f6 | 8775 | u32 dpll, fp, fp2; |
ceb41007 | 8776 | int factor, i; |
09ede541 | 8777 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 8778 | |
da3ced29 | 8779 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8780 | if (connector_state->crtc != crtc_state->base.crtc) |
8781 | continue; | |
8782 | ||
8783 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8784 | ||
8785 | switch (encoder->type) { | |
79e53945 JB |
8786 | case INTEL_OUTPUT_LVDS: |
8787 | is_lvds = true; | |
8788 | break; | |
8789 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 8790 | case INTEL_OUTPUT_HDMI: |
79e53945 | 8791 | is_sdvo = true; |
79e53945 | 8792 | break; |
6847d71b PZ |
8793 | default: |
8794 | break; | |
79e53945 JB |
8795 | } |
8796 | } | |
79e53945 | 8797 | |
c1858123 | 8798 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
8799 | factor = 21; |
8800 | if (is_lvds) { | |
8801 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 8802 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 8803 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 8804 | factor = 25; |
190f68c5 | 8805 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 8806 | factor = 20; |
c1858123 | 8807 | |
b75ca6f6 ACO |
8808 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
8809 | ||
190f68c5 | 8810 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
b75ca6f6 ACO |
8811 | fp |= FP_CB_TUNE; |
8812 | ||
8813 | if (reduced_clock) { | |
8814 | fp2 = i9xx_dpll_compute_fp(reduced_clock); | |
2c07245f | 8815 | |
b75ca6f6 ACO |
8816 | if (reduced_clock->m < factor * reduced_clock->n) |
8817 | fp2 |= FP_CB_TUNE; | |
8818 | } else { | |
8819 | fp2 = fp; | |
8820 | } | |
9a7c7890 | 8821 | |
5eddb70b | 8822 | dpll = 0; |
2c07245f | 8823 | |
a07d6787 EA |
8824 | if (is_lvds) |
8825 | dpll |= DPLLB_MODE_LVDS; | |
8826 | else | |
8827 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 8828 | |
190f68c5 | 8829 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8830 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f DV |
8831 | |
8832 | if (is_sdvo) | |
4a33e48d | 8833 | dpll |= DPLL_SDVO_HIGH_SPEED; |
190f68c5 | 8834 | if (crtc_state->has_dp_encoder) |
4a33e48d | 8835 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 8836 | |
a07d6787 | 8837 | /* compute bitmask from p1 value */ |
190f68c5 | 8838 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 8839 | /* also FPA1 */ |
190f68c5 | 8840 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 8841 | |
190f68c5 | 8842 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
8843 | case 5: |
8844 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8845 | break; | |
8846 | case 7: | |
8847 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8848 | break; | |
8849 | case 10: | |
8850 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8851 | break; | |
8852 | case 14: | |
8853 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8854 | break; | |
79e53945 JB |
8855 | } |
8856 | ||
ceb41007 | 8857 | if (is_lvds && intel_panel_use_ssc(dev_priv)) |
43565a06 | 8858 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
8859 | else |
8860 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8861 | ||
b75ca6f6 ACO |
8862 | dpll |= DPLL_VCO_ENABLE; |
8863 | ||
8864 | crtc_state->dpll_hw_state.dpll = dpll; | |
8865 | crtc_state->dpll_hw_state.fp0 = fp; | |
8866 | crtc_state->dpll_hw_state.fp1 = fp2; | |
de13a2e3 PZ |
8867 | } |
8868 | ||
190f68c5 ACO |
8869 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
8870 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 8871 | { |
997c030c ACO |
8872 | struct drm_device *dev = crtc->base.dev; |
8873 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9e2c8475 | 8874 | struct dpll reduced_clock; |
7ed9f894 | 8875 | bool has_reduced_clock = false; |
e2b78267 | 8876 | struct intel_shared_dpll *pll; |
1b6f4958 | 8877 | const struct intel_limit *limit; |
997c030c | 8878 | int refclk = 120000; |
de13a2e3 | 8879 | |
dd3cd74a ACO |
8880 | memset(&crtc_state->dpll_hw_state, 0, |
8881 | sizeof(crtc_state->dpll_hw_state)); | |
8882 | ||
ded220e2 ACO |
8883 | crtc->lowfreq_avail = false; |
8884 | ||
8885 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ | |
8886 | if (!crtc_state->has_pch_encoder) | |
8887 | return 0; | |
79e53945 | 8888 | |
997c030c ACO |
8889 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
8890 | if (intel_panel_use_ssc(dev_priv)) { | |
8891 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", | |
8892 | dev_priv->vbt.lvds_ssc_freq); | |
8893 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8894 | } | |
8895 | ||
8896 | if (intel_is_dual_link_lvds(dev)) { | |
8897 | if (refclk == 100000) | |
8898 | limit = &intel_limits_ironlake_dual_lvds_100m; | |
8899 | else | |
8900 | limit = &intel_limits_ironlake_dual_lvds; | |
8901 | } else { | |
8902 | if (refclk == 100000) | |
8903 | limit = &intel_limits_ironlake_single_lvds_100m; | |
8904 | else | |
8905 | limit = &intel_limits_ironlake_single_lvds; | |
8906 | } | |
8907 | } else { | |
8908 | limit = &intel_limits_ironlake_dac; | |
8909 | } | |
8910 | ||
364ee29d | 8911 | if (!crtc_state->clock_set && |
997c030c ACO |
8912 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
8913 | refclk, NULL, &crtc_state->dpll)) { | |
364ee29d ACO |
8914 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
8915 | return -EINVAL; | |
f47709a9 | 8916 | } |
79e53945 | 8917 | |
b75ca6f6 ACO |
8918 | ironlake_compute_dpll(crtc, crtc_state, |
8919 | has_reduced_clock ? &reduced_clock : NULL); | |
66e985c0 | 8920 | |
ded220e2 ACO |
8921 | pll = intel_get_shared_dpll(crtc, crtc_state, NULL); |
8922 | if (pll == NULL) { | |
8923 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
8924 | pipe_name(crtc->pipe)); | |
8925 | return -EINVAL; | |
3fb37703 | 8926 | } |
79e53945 | 8927 | |
ded220e2 ACO |
8928 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
8929 | has_reduced_clock) | |
c7653199 | 8930 | crtc->lowfreq_avail = true; |
e2b78267 | 8931 | |
c8f7a0db | 8932 | return 0; |
79e53945 JB |
8933 | } |
8934 | ||
eb14cb74 VS |
8935 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
8936 | struct intel_link_m_n *m_n) | |
8937 | { | |
8938 | struct drm_device *dev = crtc->base.dev; | |
8939 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8940 | enum pipe pipe = crtc->pipe; | |
8941 | ||
8942 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
8943 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
8944 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8945 | & ~TU_SIZE_MASK; | |
8946 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
8947 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8948 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8949 | } | |
8950 | ||
8951 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
8952 | enum transcoder transcoder, | |
b95af8be VK |
8953 | struct intel_link_m_n *m_n, |
8954 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
8955 | { |
8956 | struct drm_device *dev = crtc->base.dev; | |
8957 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 8958 | enum pipe pipe = crtc->pipe; |
72419203 | 8959 | |
eb14cb74 VS |
8960 | if (INTEL_INFO(dev)->gen >= 5) { |
8961 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
8962 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
8963 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
8964 | & ~TU_SIZE_MASK; | |
8965 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
8966 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
8967 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
8968 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
8969 | * gen < 8) and if DRRS is supported (to make sure the | |
8970 | * registers are not unnecessarily read). | |
8971 | */ | |
8972 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 8973 | crtc->config->has_drrs) { |
b95af8be VK |
8974 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
8975 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
8976 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
8977 | & ~TU_SIZE_MASK; | |
8978 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
8979 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
8980 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8981 | } | |
eb14cb74 VS |
8982 | } else { |
8983 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
8984 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
8985 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8986 | & ~TU_SIZE_MASK; | |
8987 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
8988 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8989 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8990 | } | |
8991 | } | |
8992 | ||
8993 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 8994 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 8995 | { |
681a8504 | 8996 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
8997 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
8998 | else | |
8999 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
9000 | &pipe_config->dp_m_n, |
9001 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 9002 | } |
72419203 | 9003 | |
eb14cb74 | 9004 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 9005 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
9006 | { |
9007 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 9008 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
9009 | } |
9010 | ||
bd2e244f | 9011 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9012 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
9013 | { |
9014 | struct drm_device *dev = crtc->base.dev; | |
9015 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a1b2278e CK |
9016 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
9017 | uint32_t ps_ctrl = 0; | |
9018 | int id = -1; | |
9019 | int i; | |
bd2e244f | 9020 | |
a1b2278e CK |
9021 | /* find scaler attached to this pipe */ |
9022 | for (i = 0; i < crtc->num_scalers; i++) { | |
9023 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
9024 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
9025 | id = i; | |
9026 | pipe_config->pch_pfit.enabled = true; | |
9027 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
9028 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
9029 | break; | |
9030 | } | |
9031 | } | |
bd2e244f | 9032 | |
a1b2278e CK |
9033 | scaler_state->scaler_id = id; |
9034 | if (id >= 0) { | |
9035 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
9036 | } else { | |
9037 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
9038 | } |
9039 | } | |
9040 | ||
5724dbd1 DL |
9041 | static void |
9042 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
9043 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
9044 | { |
9045 | struct drm_device *dev = crtc->base.dev; | |
9046 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40f46283 | 9047 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
9048 | int pipe = crtc->pipe; |
9049 | int fourcc, pixel_format; | |
6761dd31 | 9050 | unsigned int aligned_height; |
bc8d7dff | 9051 | struct drm_framebuffer *fb; |
1b842c89 | 9052 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 9053 | |
d9806c9f | 9054 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9055 | if (!intel_fb) { |
bc8d7dff DL |
9056 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9057 | return; | |
9058 | } | |
9059 | ||
1b842c89 DL |
9060 | fb = &intel_fb->base; |
9061 | ||
bc8d7dff | 9062 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
9063 | if (!(val & PLANE_CTL_ENABLE)) |
9064 | goto error; | |
9065 | ||
bc8d7dff DL |
9066 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
9067 | fourcc = skl_format_to_fourcc(pixel_format, | |
9068 | val & PLANE_CTL_ORDER_RGBX, | |
9069 | val & PLANE_CTL_ALPHA_MASK); | |
9070 | fb->pixel_format = fourcc; | |
9071 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
9072 | ||
40f46283 DL |
9073 | tiling = val & PLANE_CTL_TILED_MASK; |
9074 | switch (tiling) { | |
9075 | case PLANE_CTL_TILED_LINEAR: | |
9076 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
9077 | break; | |
9078 | case PLANE_CTL_TILED_X: | |
9079 | plane_config->tiling = I915_TILING_X; | |
9080 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
9081 | break; | |
9082 | case PLANE_CTL_TILED_Y: | |
9083 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
9084 | break; | |
9085 | case PLANE_CTL_TILED_YF: | |
9086 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
9087 | break; | |
9088 | default: | |
9089 | MISSING_CASE(tiling); | |
9090 | goto error; | |
9091 | } | |
9092 | ||
bc8d7dff DL |
9093 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
9094 | plane_config->base = base; | |
9095 | ||
9096 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
9097 | ||
9098 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
9099 | fb->height = ((val >> 16) & 0xfff) + 1; | |
9100 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
9101 | ||
9102 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
7b49f948 | 9103 | stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
40f46283 | 9104 | fb->pixel_format); |
bc8d7dff DL |
9105 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
9106 | ||
9107 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
9108 | fb->pixel_format, |
9109 | fb->modifier[0]); | |
bc8d7dff | 9110 | |
f37b5c2b | 9111 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
9112 | |
9113 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
9114 | pipe_name(pipe), fb->width, fb->height, | |
9115 | fb->bits_per_pixel, base, fb->pitches[0], | |
9116 | plane_config->size); | |
9117 | ||
2d14030b | 9118 | plane_config->fb = intel_fb; |
bc8d7dff DL |
9119 | return; |
9120 | ||
9121 | error: | |
9122 | kfree(fb); | |
9123 | } | |
9124 | ||
2fa2fe9a | 9125 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9126 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
9127 | { |
9128 | struct drm_device *dev = crtc->base.dev; | |
9129 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9130 | uint32_t tmp; | |
9131 | ||
9132 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
9133 | ||
9134 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 9135 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
9136 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
9137 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
9138 | |
9139 | /* We currently do not free assignements of panel fitters on | |
9140 | * ivb/hsw (since we don't use the higher upscaling modes which | |
9141 | * differentiates them) so just WARN about this case for now. */ | |
9142 | if (IS_GEN7(dev)) { | |
9143 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
9144 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
9145 | } | |
2fa2fe9a | 9146 | } |
79e53945 JB |
9147 | } |
9148 | ||
5724dbd1 DL |
9149 | static void |
9150 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
9151 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
9152 | { |
9153 | struct drm_device *dev = crtc->base.dev; | |
9154 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9155 | u32 val, base, offset; | |
aeee5a49 | 9156 | int pipe = crtc->pipe; |
4c6baa59 | 9157 | int fourcc, pixel_format; |
6761dd31 | 9158 | unsigned int aligned_height; |
b113d5ee | 9159 | struct drm_framebuffer *fb; |
1b842c89 | 9160 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 9161 | |
42a7b088 DL |
9162 | val = I915_READ(DSPCNTR(pipe)); |
9163 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
9164 | return; | |
9165 | ||
d9806c9f | 9166 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9167 | if (!intel_fb) { |
4c6baa59 JB |
9168 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9169 | return; | |
9170 | } | |
9171 | ||
1b842c89 DL |
9172 | fb = &intel_fb->base; |
9173 | ||
18c5247e DV |
9174 | if (INTEL_INFO(dev)->gen >= 4) { |
9175 | if (val & DISPPLANE_TILED) { | |
49af449b | 9176 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
9177 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
9178 | } | |
9179 | } | |
4c6baa59 JB |
9180 | |
9181 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 9182 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
9183 | fb->pixel_format = fourcc; |
9184 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 9185 | |
aeee5a49 | 9186 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 9187 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 9188 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 9189 | } else { |
49af449b | 9190 | if (plane_config->tiling) |
aeee5a49 | 9191 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 9192 | else |
aeee5a49 | 9193 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
9194 | } |
9195 | plane_config->base = base; | |
9196 | ||
9197 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
9198 | fb->width = ((val >> 16) & 0xfff) + 1; |
9199 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
9200 | |
9201 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 9202 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 9203 | |
b113d5ee | 9204 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
9205 | fb->pixel_format, |
9206 | fb->modifier[0]); | |
4c6baa59 | 9207 | |
f37b5c2b | 9208 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 9209 | |
2844a921 DL |
9210 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
9211 | pipe_name(pipe), fb->width, fb->height, | |
9212 | fb->bits_per_pixel, base, fb->pitches[0], | |
9213 | plane_config->size); | |
b113d5ee | 9214 | |
2d14030b | 9215 | plane_config->fb = intel_fb; |
4c6baa59 JB |
9216 | } |
9217 | ||
0e8ffe1b | 9218 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9219 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9220 | { |
9221 | struct drm_device *dev = crtc->base.dev; | |
9222 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1729050e | 9223 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 9224 | uint32_t tmp; |
1729050e | 9225 | bool ret; |
0e8ffe1b | 9226 | |
1729050e ID |
9227 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
9228 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
930e8c9e PZ |
9229 | return false; |
9230 | ||
e143a21c | 9231 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 9232 | pipe_config->shared_dpll = NULL; |
eccb140b | 9233 | |
1729050e | 9234 | ret = false; |
0e8ffe1b DV |
9235 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
9236 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 9237 | goto out; |
0e8ffe1b | 9238 | |
42571aef VS |
9239 | switch (tmp & PIPECONF_BPC_MASK) { |
9240 | case PIPECONF_6BPC: | |
9241 | pipe_config->pipe_bpp = 18; | |
9242 | break; | |
9243 | case PIPECONF_8BPC: | |
9244 | pipe_config->pipe_bpp = 24; | |
9245 | break; | |
9246 | case PIPECONF_10BPC: | |
9247 | pipe_config->pipe_bpp = 30; | |
9248 | break; | |
9249 | case PIPECONF_12BPC: | |
9250 | pipe_config->pipe_bpp = 36; | |
9251 | break; | |
9252 | default: | |
9253 | break; | |
9254 | } | |
9255 | ||
b5a9fa09 DV |
9256 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
9257 | pipe_config->limited_color_range = true; | |
9258 | ||
ab9412ba | 9259 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 | 9260 | struct intel_shared_dpll *pll; |
8106ddbd | 9261 | enum intel_dpll_id pll_id; |
66e985c0 | 9262 | |
88adfff1 DV |
9263 | pipe_config->has_pch_encoder = true; |
9264 | ||
627eb5a3 DV |
9265 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
9266 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9267 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
9268 | |
9269 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 9270 | |
2d1fe073 | 9271 | if (HAS_PCH_IBX(dev_priv)) { |
d9a7bc67 ID |
9272 | /* |
9273 | * The pipe->pch transcoder and pch transcoder->pll | |
9274 | * mapping is fixed. | |
9275 | */ | |
8106ddbd | 9276 | pll_id = (enum intel_dpll_id) crtc->pipe; |
c0d43d62 DV |
9277 | } else { |
9278 | tmp = I915_READ(PCH_DPLL_SEL); | |
9279 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
8106ddbd | 9280 | pll_id = DPLL_ID_PCH_PLL_B; |
c0d43d62 | 9281 | else |
8106ddbd | 9282 | pll_id= DPLL_ID_PCH_PLL_A; |
c0d43d62 | 9283 | } |
66e985c0 | 9284 | |
8106ddbd ACO |
9285 | pipe_config->shared_dpll = |
9286 | intel_get_shared_dpll_by_id(dev_priv, pll_id); | |
9287 | pll = pipe_config->shared_dpll; | |
66e985c0 | 9288 | |
2edd6443 ACO |
9289 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
9290 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
9291 | |
9292 | tmp = pipe_config->dpll_hw_state.dpll; | |
9293 | pipe_config->pixel_multiplier = | |
9294 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
9295 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
9296 | |
9297 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
9298 | } else { |
9299 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
9300 | } |
9301 | ||
1bd1bd80 | 9302 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 9303 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 9304 | |
2fa2fe9a DV |
9305 | ironlake_get_pfit_config(crtc, pipe_config); |
9306 | ||
1729050e ID |
9307 | ret = true; |
9308 | ||
9309 | out: | |
9310 | intel_display_power_put(dev_priv, power_domain); | |
9311 | ||
9312 | return ret; | |
0e8ffe1b DV |
9313 | } |
9314 | ||
be256dc7 PZ |
9315 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
9316 | { | |
9317 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 9318 | struct intel_crtc *crtc; |
be256dc7 | 9319 | |
d3fcc808 | 9320 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 9321 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
9322 | pipe_name(crtc->pipe)); |
9323 | ||
e2c719b7 RC |
9324 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
9325 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
01403de3 VS |
9326 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
9327 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
e2c719b7 RC |
9328 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
9329 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
be256dc7 | 9330 | "CPU PWM1 enabled\n"); |
c5107b87 | 9331 | if (IS_HASWELL(dev)) |
e2c719b7 | 9332 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 9333 | "CPU PWM2 enabled\n"); |
e2c719b7 | 9334 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 9335 | "PCH PWM1 enabled\n"); |
e2c719b7 | 9336 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 9337 | "Utility pin enabled\n"); |
e2c719b7 | 9338 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 9339 | |
9926ada1 PZ |
9340 | /* |
9341 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
9342 | * interrupts remain enabled. We used to check for that, but since it's | |
9343 | * gen-specific and since we only disable LCPLL after we fully disable | |
9344 | * the interrupts, the check below should be enough. | |
9345 | */ | |
e2c719b7 | 9346 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
9347 | } |
9348 | ||
9ccd5aeb PZ |
9349 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
9350 | { | |
9351 | struct drm_device *dev = dev_priv->dev; | |
9352 | ||
9353 | if (IS_HASWELL(dev)) | |
9354 | return I915_READ(D_COMP_HSW); | |
9355 | else | |
9356 | return I915_READ(D_COMP_BDW); | |
9357 | } | |
9358 | ||
3c4c9b81 PZ |
9359 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
9360 | { | |
9361 | struct drm_device *dev = dev_priv->dev; | |
9362 | ||
9363 | if (IS_HASWELL(dev)) { | |
9364 | mutex_lock(&dev_priv->rps.hw_lock); | |
9365 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
9366 | val)) | |
f475dadf | 9367 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
9368 | mutex_unlock(&dev_priv->rps.hw_lock); |
9369 | } else { | |
9ccd5aeb PZ |
9370 | I915_WRITE(D_COMP_BDW, val); |
9371 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 9372 | } |
be256dc7 PZ |
9373 | } |
9374 | ||
9375 | /* | |
9376 | * This function implements pieces of two sequences from BSpec: | |
9377 | * - Sequence for display software to disable LCPLL | |
9378 | * - Sequence for display software to allow package C8+ | |
9379 | * The steps implemented here are just the steps that actually touch the LCPLL | |
9380 | * register. Callers should take care of disabling all the display engine | |
9381 | * functions, doing the mode unset, fixing interrupts, etc. | |
9382 | */ | |
6ff58d53 PZ |
9383 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
9384 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
9385 | { |
9386 | uint32_t val; | |
9387 | ||
9388 | assert_can_disable_lcpll(dev_priv); | |
9389 | ||
9390 | val = I915_READ(LCPLL_CTL); | |
9391 | ||
9392 | if (switch_to_fclk) { | |
9393 | val |= LCPLL_CD_SOURCE_FCLK; | |
9394 | I915_WRITE(LCPLL_CTL, val); | |
9395 | ||
9396 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9397 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9398 | DRM_ERROR("Switching to FCLK failed\n"); | |
9399 | ||
9400 | val = I915_READ(LCPLL_CTL); | |
9401 | } | |
9402 | ||
9403 | val |= LCPLL_PLL_DISABLE; | |
9404 | I915_WRITE(LCPLL_CTL, val); | |
9405 | POSTING_READ(LCPLL_CTL); | |
9406 | ||
9407 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
9408 | DRM_ERROR("LCPLL still locked\n"); | |
9409 | ||
9ccd5aeb | 9410 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 9411 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 9412 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9413 | ndelay(100); |
9414 | ||
9ccd5aeb PZ |
9415 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
9416 | 1)) | |
be256dc7 PZ |
9417 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
9418 | ||
9419 | if (allow_power_down) { | |
9420 | val = I915_READ(LCPLL_CTL); | |
9421 | val |= LCPLL_POWER_DOWN_ALLOW; | |
9422 | I915_WRITE(LCPLL_CTL, val); | |
9423 | POSTING_READ(LCPLL_CTL); | |
9424 | } | |
9425 | } | |
9426 | ||
9427 | /* | |
9428 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
9429 | * source. | |
9430 | */ | |
6ff58d53 | 9431 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
9432 | { |
9433 | uint32_t val; | |
9434 | ||
9435 | val = I915_READ(LCPLL_CTL); | |
9436 | ||
9437 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
9438 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
9439 | return; | |
9440 | ||
a8a8bd54 PZ |
9441 | /* |
9442 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
9443 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 9444 | */ |
59bad947 | 9445 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 9446 | |
be256dc7 PZ |
9447 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
9448 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
9449 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 9450 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
9451 | } |
9452 | ||
9ccd5aeb | 9453 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
9454 | val |= D_COMP_COMP_FORCE; |
9455 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 9456 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9457 | |
9458 | val = I915_READ(LCPLL_CTL); | |
9459 | val &= ~LCPLL_PLL_DISABLE; | |
9460 | I915_WRITE(LCPLL_CTL, val); | |
9461 | ||
9462 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
9463 | DRM_ERROR("LCPLL not locked yet\n"); | |
9464 | ||
9465 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
9466 | val = I915_READ(LCPLL_CTL); | |
9467 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9468 | I915_WRITE(LCPLL_CTL, val); | |
9469 | ||
9470 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9471 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9472 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9473 | } | |
215733fa | 9474 | |
59bad947 | 9475 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b6283055 | 9476 | intel_update_cdclk(dev_priv->dev); |
be256dc7 PZ |
9477 | } |
9478 | ||
765dab67 PZ |
9479 | /* |
9480 | * Package states C8 and deeper are really deep PC states that can only be | |
9481 | * reached when all the devices on the system allow it, so even if the graphics | |
9482 | * device allows PC8+, it doesn't mean the system will actually get to these | |
9483 | * states. Our driver only allows PC8+ when going into runtime PM. | |
9484 | * | |
9485 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
9486 | * well is disabled and most interrupts are disabled, and these are also | |
9487 | * requirements for runtime PM. When these conditions are met, we manually do | |
9488 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
9489 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
9490 | * hang the machine. | |
9491 | * | |
9492 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
9493 | * the state of some registers, so when we come back from PC8+ we need to | |
9494 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
9495 | * need to take care of the registers kept by RC6. Notice that this happens even | |
9496 | * if we don't put the device in PCI D3 state (which is what currently happens | |
9497 | * because of the runtime PM support). | |
9498 | * | |
9499 | * For more, read "Display Sequences for Package C8" on the hardware | |
9500 | * documentation. | |
9501 | */ | |
a14cb6fc | 9502 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 9503 | { |
c67a470b PZ |
9504 | struct drm_device *dev = dev_priv->dev; |
9505 | uint32_t val; | |
9506 | ||
c67a470b PZ |
9507 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
9508 | ||
c2699524 | 9509 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9510 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9511 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
9512 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9513 | } | |
9514 | ||
9515 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
9516 | hsw_disable_lcpll(dev_priv, true, true); |
9517 | } | |
9518 | ||
a14cb6fc | 9519 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
9520 | { |
9521 | struct drm_device *dev = dev_priv->dev; | |
9522 | uint32_t val; | |
9523 | ||
c67a470b PZ |
9524 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
9525 | ||
9526 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
9527 | lpt_init_pch_refclk(dev); |
9528 | ||
c2699524 | 9529 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9530 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9531 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
9532 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9533 | } | |
c67a470b PZ |
9534 | } |
9535 | ||
27c329ed | 9536 | static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
f8437dd1 | 9537 | { |
a821fc46 | 9538 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
9539 | struct intel_atomic_state *old_intel_state = |
9540 | to_intel_atomic_state(old_state); | |
9541 | unsigned int req_cdclk = old_intel_state->dev_cdclk; | |
f8437dd1 | 9542 | |
c6c4696f | 9543 | broxton_set_cdclk(to_i915(dev), req_cdclk); |
f8437dd1 VK |
9544 | } |
9545 | ||
b432e5cf | 9546 | /* compute the max rate for new configuration */ |
27c329ed | 9547 | static int ilk_max_pixel_rate(struct drm_atomic_state *state) |
b432e5cf | 9548 | { |
565602d7 ML |
9549 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
9550 | struct drm_i915_private *dev_priv = state->dev->dev_private; | |
9551 | struct drm_crtc *crtc; | |
9552 | struct drm_crtc_state *cstate; | |
27c329ed | 9553 | struct intel_crtc_state *crtc_state; |
565602d7 ML |
9554 | unsigned max_pixel_rate = 0, i; |
9555 | enum pipe pipe; | |
b432e5cf | 9556 | |
565602d7 ML |
9557 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
9558 | sizeof(intel_state->min_pixclk)); | |
27c329ed | 9559 | |
565602d7 ML |
9560 | for_each_crtc_in_state(state, crtc, cstate, i) { |
9561 | int pixel_rate; | |
27c329ed | 9562 | |
565602d7 ML |
9563 | crtc_state = to_intel_crtc_state(cstate); |
9564 | if (!crtc_state->base.enable) { | |
9565 | intel_state->min_pixclk[i] = 0; | |
b432e5cf | 9566 | continue; |
565602d7 | 9567 | } |
b432e5cf | 9568 | |
27c329ed | 9569 | pixel_rate = ilk_pipe_pixel_rate(crtc_state); |
b432e5cf VS |
9570 | |
9571 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
565602d7 | 9572 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) |
b432e5cf VS |
9573 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); |
9574 | ||
565602d7 | 9575 | intel_state->min_pixclk[i] = pixel_rate; |
b432e5cf VS |
9576 | } |
9577 | ||
565602d7 ML |
9578 | for_each_pipe(dev_priv, pipe) |
9579 | max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate); | |
9580 | ||
b432e5cf VS |
9581 | return max_pixel_rate; |
9582 | } | |
9583 | ||
9584 | static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) | |
9585 | { | |
9586 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9587 | uint32_t val, data; | |
9588 | int ret; | |
9589 | ||
9590 | if (WARN((I915_READ(LCPLL_CTL) & | |
9591 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | | |
9592 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | | |
9593 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | | |
9594 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, | |
9595 | "trying to change cdclk frequency with cdclk not enabled\n")) | |
9596 | return; | |
9597 | ||
9598 | mutex_lock(&dev_priv->rps.hw_lock); | |
9599 | ret = sandybridge_pcode_write(dev_priv, | |
9600 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); | |
9601 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9602 | if (ret) { | |
9603 | DRM_ERROR("failed to inform pcode about cdclk change\n"); | |
9604 | return; | |
9605 | } | |
9606 | ||
9607 | val = I915_READ(LCPLL_CTL); | |
9608 | val |= LCPLL_CD_SOURCE_FCLK; | |
9609 | I915_WRITE(LCPLL_CTL, val); | |
9610 | ||
5ba00178 TU |
9611 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
9612 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
b432e5cf VS |
9613 | DRM_ERROR("Switching to FCLK failed\n"); |
9614 | ||
9615 | val = I915_READ(LCPLL_CTL); | |
9616 | val &= ~LCPLL_CLK_FREQ_MASK; | |
9617 | ||
9618 | switch (cdclk) { | |
9619 | case 450000: | |
9620 | val |= LCPLL_CLK_FREQ_450; | |
9621 | data = 0; | |
9622 | break; | |
9623 | case 540000: | |
9624 | val |= LCPLL_CLK_FREQ_54O_BDW; | |
9625 | data = 1; | |
9626 | break; | |
9627 | case 337500: | |
9628 | val |= LCPLL_CLK_FREQ_337_5_BDW; | |
9629 | data = 2; | |
9630 | break; | |
9631 | case 675000: | |
9632 | val |= LCPLL_CLK_FREQ_675_BDW; | |
9633 | data = 3; | |
9634 | break; | |
9635 | default: | |
9636 | WARN(1, "invalid cdclk frequency\n"); | |
9637 | return; | |
9638 | } | |
9639 | ||
9640 | I915_WRITE(LCPLL_CTL, val); | |
9641 | ||
9642 | val = I915_READ(LCPLL_CTL); | |
9643 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9644 | I915_WRITE(LCPLL_CTL, val); | |
9645 | ||
5ba00178 TU |
9646 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
9647 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
b432e5cf VS |
9648 | DRM_ERROR("Switching back to LCPLL failed\n"); |
9649 | ||
9650 | mutex_lock(&dev_priv->rps.hw_lock); | |
9651 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); | |
9652 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9653 | ||
7f1052a8 VS |
9654 | I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1); |
9655 | ||
b432e5cf VS |
9656 | intel_update_cdclk(dev); |
9657 | ||
9658 | WARN(cdclk != dev_priv->cdclk_freq, | |
9659 | "cdclk requested %d kHz but got %d kHz\n", | |
9660 | cdclk, dev_priv->cdclk_freq); | |
9661 | } | |
9662 | ||
587c7914 VS |
9663 | static int broadwell_calc_cdclk(int max_pixclk) |
9664 | { | |
9665 | if (max_pixclk > 540000) | |
9666 | return 675000; | |
9667 | else if (max_pixclk > 450000) | |
9668 | return 540000; | |
9669 | else if (max_pixclk > 337500) | |
9670 | return 450000; | |
9671 | else | |
9672 | return 337500; | |
9673 | } | |
9674 | ||
27c329ed | 9675 | static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state) |
b432e5cf | 9676 | { |
27c329ed | 9677 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
1a617b77 | 9678 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
27c329ed | 9679 | int max_pixclk = ilk_max_pixel_rate(state); |
b432e5cf VS |
9680 | int cdclk; |
9681 | ||
9682 | /* | |
9683 | * FIXME should also account for plane ratio | |
9684 | * once 64bpp pixel formats are supported. | |
9685 | */ | |
587c7914 | 9686 | cdclk = broadwell_calc_cdclk(max_pixclk); |
b432e5cf | 9687 | |
b432e5cf | 9688 | if (cdclk > dev_priv->max_cdclk_freq) { |
63ba534e ML |
9689 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", |
9690 | cdclk, dev_priv->max_cdclk_freq); | |
9691 | return -EINVAL; | |
b432e5cf VS |
9692 | } |
9693 | ||
1a617b77 ML |
9694 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; |
9695 | if (!intel_state->active_crtcs) | |
587c7914 | 9696 | intel_state->dev_cdclk = broadwell_calc_cdclk(0); |
b432e5cf VS |
9697 | |
9698 | return 0; | |
9699 | } | |
9700 | ||
27c329ed | 9701 | static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
b432e5cf | 9702 | { |
27c329ed | 9703 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
9704 | struct intel_atomic_state *old_intel_state = |
9705 | to_intel_atomic_state(old_state); | |
9706 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
b432e5cf | 9707 | |
27c329ed | 9708 | broadwell_set_cdclk(dev, req_cdclk); |
b432e5cf VS |
9709 | } |
9710 | ||
c89e39f3 CT |
9711 | static int skl_modeset_calc_cdclk(struct drm_atomic_state *state) |
9712 | { | |
9713 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
9714 | struct drm_i915_private *dev_priv = to_i915(state->dev); | |
9715 | const int max_pixclk = ilk_max_pixel_rate(state); | |
a8ca4934 | 9716 | int vco = intel_state->cdclk_pll_vco; |
c89e39f3 CT |
9717 | int cdclk; |
9718 | ||
9719 | /* | |
9720 | * FIXME should also account for plane ratio | |
9721 | * once 64bpp pixel formats are supported. | |
9722 | */ | |
a8ca4934 | 9723 | cdclk = skl_calc_cdclk(max_pixclk, vco); |
c89e39f3 CT |
9724 | |
9725 | /* | |
9726 | * FIXME move the cdclk caclulation to | |
9727 | * compute_config() so we can fail gracegully. | |
9728 | */ | |
9729 | if (cdclk > dev_priv->max_cdclk_freq) { | |
9730 | DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n", | |
9731 | cdclk, dev_priv->max_cdclk_freq); | |
9732 | cdclk = dev_priv->max_cdclk_freq; | |
9733 | } | |
9734 | ||
9735 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; | |
9736 | if (!intel_state->active_crtcs) | |
a8ca4934 | 9737 | intel_state->dev_cdclk = skl_calc_cdclk(0, vco); |
c89e39f3 CT |
9738 | |
9739 | return 0; | |
9740 | } | |
9741 | ||
9742 | static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state) | |
9743 | { | |
1cd593e0 VS |
9744 | struct drm_i915_private *dev_priv = to_i915(old_state->dev); |
9745 | struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state); | |
9746 | unsigned int req_cdclk = intel_state->dev_cdclk; | |
9747 | unsigned int req_vco = intel_state->cdclk_pll_vco; | |
c89e39f3 | 9748 | |
1cd593e0 | 9749 | skl_set_cdclk(dev_priv, req_cdclk, req_vco); |
c89e39f3 CT |
9750 | } |
9751 | ||
190f68c5 ACO |
9752 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
9753 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 9754 | { |
af3997b5 MK |
9755 | struct intel_encoder *intel_encoder = |
9756 | intel_ddi_get_crtc_new_encoder(crtc_state); | |
9757 | ||
9758 | if (intel_encoder->type != INTEL_OUTPUT_DSI) { | |
9759 | if (!intel_ddi_pll_select(crtc, crtc_state)) | |
9760 | return -EINVAL; | |
9761 | } | |
716c2e55 | 9762 | |
c7653199 | 9763 | crtc->lowfreq_avail = false; |
644cef34 | 9764 | |
c8f7a0db | 9765 | return 0; |
79e53945 JB |
9766 | } |
9767 | ||
3760b59c S |
9768 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
9769 | enum port port, | |
9770 | struct intel_crtc_state *pipe_config) | |
9771 | { | |
8106ddbd ACO |
9772 | enum intel_dpll_id id; |
9773 | ||
3760b59c S |
9774 | switch (port) { |
9775 | case PORT_A: | |
9776 | pipe_config->ddi_pll_sel = SKL_DPLL0; | |
08250c4b | 9777 | id = DPLL_ID_SKL_DPLL0; |
3760b59c S |
9778 | break; |
9779 | case PORT_B: | |
9780 | pipe_config->ddi_pll_sel = SKL_DPLL1; | |
08250c4b | 9781 | id = DPLL_ID_SKL_DPLL1; |
3760b59c S |
9782 | break; |
9783 | case PORT_C: | |
9784 | pipe_config->ddi_pll_sel = SKL_DPLL2; | |
08250c4b | 9785 | id = DPLL_ID_SKL_DPLL2; |
3760b59c S |
9786 | break; |
9787 | default: | |
9788 | DRM_ERROR("Incorrect port type\n"); | |
8106ddbd | 9789 | return; |
3760b59c | 9790 | } |
8106ddbd ACO |
9791 | |
9792 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
3760b59c S |
9793 | } |
9794 | ||
96b7dfb7 S |
9795 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
9796 | enum port port, | |
5cec258b | 9797 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 9798 | { |
8106ddbd | 9799 | enum intel_dpll_id id; |
a3c988ea | 9800 | u32 temp; |
96b7dfb7 S |
9801 | |
9802 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
9803 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
9804 | ||
9805 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 | 9806 | case SKL_DPLL0: |
a3c988ea ACO |
9807 | id = DPLL_ID_SKL_DPLL0; |
9808 | break; | |
96b7dfb7 | 9809 | case SKL_DPLL1: |
8106ddbd | 9810 | id = DPLL_ID_SKL_DPLL1; |
96b7dfb7 S |
9811 | break; |
9812 | case SKL_DPLL2: | |
8106ddbd | 9813 | id = DPLL_ID_SKL_DPLL2; |
96b7dfb7 S |
9814 | break; |
9815 | case SKL_DPLL3: | |
8106ddbd | 9816 | id = DPLL_ID_SKL_DPLL3; |
96b7dfb7 | 9817 | break; |
8106ddbd ACO |
9818 | default: |
9819 | MISSING_CASE(pipe_config->ddi_pll_sel); | |
9820 | return; | |
96b7dfb7 | 9821 | } |
8106ddbd ACO |
9822 | |
9823 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
96b7dfb7 S |
9824 | } |
9825 | ||
7d2c8175 DL |
9826 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
9827 | enum port port, | |
5cec258b | 9828 | struct intel_crtc_state *pipe_config) |
7d2c8175 | 9829 | { |
8106ddbd ACO |
9830 | enum intel_dpll_id id; |
9831 | ||
7d2c8175 DL |
9832 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); |
9833 | ||
9834 | switch (pipe_config->ddi_pll_sel) { | |
9835 | case PORT_CLK_SEL_WRPLL1: | |
8106ddbd | 9836 | id = DPLL_ID_WRPLL1; |
7d2c8175 DL |
9837 | break; |
9838 | case PORT_CLK_SEL_WRPLL2: | |
8106ddbd | 9839 | id = DPLL_ID_WRPLL2; |
7d2c8175 | 9840 | break; |
00490c22 | 9841 | case PORT_CLK_SEL_SPLL: |
8106ddbd | 9842 | id = DPLL_ID_SPLL; |
79bd23da | 9843 | break; |
9d16da65 ACO |
9844 | case PORT_CLK_SEL_LCPLL_810: |
9845 | id = DPLL_ID_LCPLL_810; | |
9846 | break; | |
9847 | case PORT_CLK_SEL_LCPLL_1350: | |
9848 | id = DPLL_ID_LCPLL_1350; | |
9849 | break; | |
9850 | case PORT_CLK_SEL_LCPLL_2700: | |
9851 | id = DPLL_ID_LCPLL_2700; | |
9852 | break; | |
8106ddbd ACO |
9853 | default: |
9854 | MISSING_CASE(pipe_config->ddi_pll_sel); | |
9855 | /* fall through */ | |
9856 | case PORT_CLK_SEL_NONE: | |
8106ddbd | 9857 | return; |
7d2c8175 | 9858 | } |
8106ddbd ACO |
9859 | |
9860 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
7d2c8175 DL |
9861 | } |
9862 | ||
cf30429e JN |
9863 | static bool hsw_get_transcoder_state(struct intel_crtc *crtc, |
9864 | struct intel_crtc_state *pipe_config, | |
9865 | unsigned long *power_domain_mask) | |
9866 | { | |
9867 | struct drm_device *dev = crtc->base.dev; | |
9868 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9869 | enum intel_display_power_domain power_domain; | |
9870 | u32 tmp; | |
9871 | ||
d9a7bc67 ID |
9872 | /* |
9873 | * The pipe->transcoder mapping is fixed with the exception of the eDP | |
9874 | * transcoder handled below. | |
9875 | */ | |
cf30429e JN |
9876 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
9877 | ||
9878 | /* | |
9879 | * XXX: Do intel_display_power_get_if_enabled before reading this (for | |
9880 | * consistency and less surprising code; it's in always on power). | |
9881 | */ | |
9882 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
9883 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
9884 | enum pipe trans_edp_pipe; | |
9885 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
9886 | default: | |
9887 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
9888 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
9889 | case TRANS_DDI_EDP_INPUT_A_ON: | |
9890 | trans_edp_pipe = PIPE_A; | |
9891 | break; | |
9892 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
9893 | trans_edp_pipe = PIPE_B; | |
9894 | break; | |
9895 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
9896 | trans_edp_pipe = PIPE_C; | |
9897 | break; | |
9898 | } | |
9899 | ||
9900 | if (trans_edp_pipe == crtc->pipe) | |
9901 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
9902 | } | |
9903 | ||
9904 | power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); | |
9905 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
9906 | return false; | |
9907 | *power_domain_mask |= BIT(power_domain); | |
9908 | ||
9909 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); | |
9910 | ||
9911 | return tmp & PIPECONF_ENABLE; | |
9912 | } | |
9913 | ||
4d1de975 JN |
9914 | static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, |
9915 | struct intel_crtc_state *pipe_config, | |
9916 | unsigned long *power_domain_mask) | |
9917 | { | |
9918 | struct drm_device *dev = crtc->base.dev; | |
9919 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9920 | enum intel_display_power_domain power_domain; | |
9921 | enum port port; | |
9922 | enum transcoder cpu_transcoder; | |
9923 | u32 tmp; | |
9924 | ||
9925 | pipe_config->has_dsi_encoder = false; | |
9926 | ||
9927 | for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { | |
9928 | if (port == PORT_A) | |
9929 | cpu_transcoder = TRANSCODER_DSI_A; | |
9930 | else | |
9931 | cpu_transcoder = TRANSCODER_DSI_C; | |
9932 | ||
9933 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
9934 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
9935 | continue; | |
9936 | *power_domain_mask |= BIT(power_domain); | |
9937 | ||
db18b6a6 ID |
9938 | /* |
9939 | * The PLL needs to be enabled with a valid divider | |
9940 | * configuration, otherwise accessing DSI registers will hang | |
9941 | * the machine. See BSpec North Display Engine | |
9942 | * registers/MIPI[BXT]. We can break out here early, since we | |
9943 | * need the same DSI PLL to be enabled for both DSI ports. | |
9944 | */ | |
9945 | if (!intel_dsi_pll_is_enabled(dev_priv)) | |
9946 | break; | |
9947 | ||
4d1de975 JN |
9948 | /* XXX: this works for video mode only */ |
9949 | tmp = I915_READ(BXT_MIPI_PORT_CTRL(port)); | |
9950 | if (!(tmp & DPI_ENABLE)) | |
9951 | continue; | |
9952 | ||
9953 | tmp = I915_READ(MIPI_CTRL(port)); | |
9954 | if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) | |
9955 | continue; | |
9956 | ||
9957 | pipe_config->cpu_transcoder = cpu_transcoder; | |
9958 | pipe_config->has_dsi_encoder = true; | |
9959 | break; | |
9960 | } | |
9961 | ||
9962 | return pipe_config->has_dsi_encoder; | |
9963 | } | |
9964 | ||
26804afd | 9965 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 9966 | struct intel_crtc_state *pipe_config) |
26804afd DV |
9967 | { |
9968 | struct drm_device *dev = crtc->base.dev; | |
9969 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 9970 | struct intel_shared_dpll *pll; |
26804afd DV |
9971 | enum port port; |
9972 | uint32_t tmp; | |
9973 | ||
9974 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
9975 | ||
9976 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
9977 | ||
ef11bdb3 | 9978 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
96b7dfb7 | 9979 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
3760b59c S |
9980 | else if (IS_BROXTON(dev)) |
9981 | bxt_get_ddi_pll(dev_priv, port, pipe_config); | |
96b7dfb7 S |
9982 | else |
9983 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 9984 | |
8106ddbd ACO |
9985 | pll = pipe_config->shared_dpll; |
9986 | if (pll) { | |
2edd6443 ACO |
9987 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
9988 | &pipe_config->dpll_hw_state)); | |
d452c5b6 DV |
9989 | } |
9990 | ||
26804afd DV |
9991 | /* |
9992 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
9993 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
9994 | * the PCH transcoder is on. | |
9995 | */ | |
ca370455 DL |
9996 | if (INTEL_INFO(dev)->gen < 9 && |
9997 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
9998 | pipe_config->has_pch_encoder = true; |
9999 | ||
10000 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
10001 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
10002 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
10003 | ||
10004 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
10005 | } | |
10006 | } | |
10007 | ||
0e8ffe1b | 10008 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 10009 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
10010 | { |
10011 | struct drm_device *dev = crtc->base.dev; | |
10012 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1729050e ID |
10013 | enum intel_display_power_domain power_domain; |
10014 | unsigned long power_domain_mask; | |
cf30429e | 10015 | bool active; |
0e8ffe1b | 10016 | |
1729050e ID |
10017 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
10018 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 | 10019 | return false; |
1729050e ID |
10020 | power_domain_mask = BIT(power_domain); |
10021 | ||
8106ddbd | 10022 | pipe_config->shared_dpll = NULL; |
c0d43d62 | 10023 | |
cf30429e | 10024 | active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask); |
eccb140b | 10025 | |
4d1de975 JN |
10026 | if (IS_BROXTON(dev_priv)) { |
10027 | bxt_get_dsi_transcoder_state(crtc, pipe_config, | |
10028 | &power_domain_mask); | |
10029 | WARN_ON(active && pipe_config->has_dsi_encoder); | |
10030 | if (pipe_config->has_dsi_encoder) | |
10031 | active = true; | |
10032 | } | |
10033 | ||
cf30429e | 10034 | if (!active) |
1729050e | 10035 | goto out; |
0e8ffe1b | 10036 | |
4d1de975 JN |
10037 | if (!pipe_config->has_dsi_encoder) { |
10038 | haswell_get_ddi_port_state(crtc, pipe_config); | |
10039 | intel_get_pipe_timings(crtc, pipe_config); | |
10040 | } | |
627eb5a3 | 10041 | |
bc58be60 | 10042 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 10043 | |
05dc698c LL |
10044 | pipe_config->gamma_mode = |
10045 | I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; | |
10046 | ||
a1b2278e CK |
10047 | if (INTEL_INFO(dev)->gen >= 9) { |
10048 | skl_init_scalers(dev, crtc, pipe_config); | |
10049 | } | |
10050 | ||
af99ceda CK |
10051 | if (INTEL_INFO(dev)->gen >= 9) { |
10052 | pipe_config->scaler_state.scaler_id = -1; | |
10053 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
10054 | } | |
10055 | ||
1729050e ID |
10056 | power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
10057 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
10058 | power_domain_mask |= BIT(power_domain); | |
1c132b44 | 10059 | if (INTEL_INFO(dev)->gen >= 9) |
bd2e244f | 10060 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 10061 | else |
1c132b44 | 10062 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 10063 | } |
88adfff1 | 10064 | |
e59150dc JB |
10065 | if (IS_HASWELL(dev)) |
10066 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
10067 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 10068 | |
4d1de975 JN |
10069 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP && |
10070 | !transcoder_is_dsi(pipe_config->cpu_transcoder)) { | |
ebb69c95 CT |
10071 | pipe_config->pixel_multiplier = |
10072 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
10073 | } else { | |
10074 | pipe_config->pixel_multiplier = 1; | |
10075 | } | |
6c49f241 | 10076 | |
1729050e ID |
10077 | out: |
10078 | for_each_power_domain(power_domain, power_domain_mask) | |
10079 | intel_display_power_put(dev_priv, power_domain); | |
10080 | ||
cf30429e | 10081 | return active; |
0e8ffe1b DV |
10082 | } |
10083 | ||
55a08b3f ML |
10084 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base, |
10085 | const struct intel_plane_state *plane_state) | |
560b85bb CW |
10086 | { |
10087 | struct drm_device *dev = crtc->dev; | |
10088 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10089 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 10090 | uint32_t cntl = 0, size = 0; |
560b85bb | 10091 | |
55a08b3f ML |
10092 | if (plane_state && plane_state->visible) { |
10093 | unsigned int width = plane_state->base.crtc_w; | |
10094 | unsigned int height = plane_state->base.crtc_h; | |
dc41c154 VS |
10095 | unsigned int stride = roundup_pow_of_two(width) * 4; |
10096 | ||
10097 | switch (stride) { | |
10098 | default: | |
10099 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
10100 | width, stride); | |
10101 | stride = 256; | |
10102 | /* fallthrough */ | |
10103 | case 256: | |
10104 | case 512: | |
10105 | case 1024: | |
10106 | case 2048: | |
10107 | break; | |
4b0e333e CW |
10108 | } |
10109 | ||
dc41c154 VS |
10110 | cntl |= CURSOR_ENABLE | |
10111 | CURSOR_GAMMA_ENABLE | | |
10112 | CURSOR_FORMAT_ARGB | | |
10113 | CURSOR_STRIDE(stride); | |
10114 | ||
10115 | size = (height << 12) | width; | |
4b0e333e | 10116 | } |
560b85bb | 10117 | |
dc41c154 VS |
10118 | if (intel_crtc->cursor_cntl != 0 && |
10119 | (intel_crtc->cursor_base != base || | |
10120 | intel_crtc->cursor_size != size || | |
10121 | intel_crtc->cursor_cntl != cntl)) { | |
10122 | /* On these chipsets we can only modify the base/size/stride | |
10123 | * whilst the cursor is disabled. | |
10124 | */ | |
0b87c24e VS |
10125 | I915_WRITE(CURCNTR(PIPE_A), 0); |
10126 | POSTING_READ(CURCNTR(PIPE_A)); | |
dc41c154 | 10127 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 10128 | } |
560b85bb | 10129 | |
99d1f387 | 10130 | if (intel_crtc->cursor_base != base) { |
0b87c24e | 10131 | I915_WRITE(CURBASE(PIPE_A), base); |
99d1f387 VS |
10132 | intel_crtc->cursor_base = base; |
10133 | } | |
4726e0b0 | 10134 | |
dc41c154 VS |
10135 | if (intel_crtc->cursor_size != size) { |
10136 | I915_WRITE(CURSIZE, size); | |
10137 | intel_crtc->cursor_size = size; | |
4b0e333e | 10138 | } |
560b85bb | 10139 | |
4b0e333e | 10140 | if (intel_crtc->cursor_cntl != cntl) { |
0b87c24e VS |
10141 | I915_WRITE(CURCNTR(PIPE_A), cntl); |
10142 | POSTING_READ(CURCNTR(PIPE_A)); | |
4b0e333e | 10143 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 10144 | } |
560b85bb CW |
10145 | } |
10146 | ||
55a08b3f ML |
10147 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, |
10148 | const struct intel_plane_state *plane_state) | |
65a21cd6 JB |
10149 | { |
10150 | struct drm_device *dev = crtc->dev; | |
10151 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10152 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10153 | int pipe = intel_crtc->pipe; | |
663f3122 | 10154 | uint32_t cntl = 0; |
4b0e333e | 10155 | |
55a08b3f | 10156 | if (plane_state && plane_state->visible) { |
4b0e333e | 10157 | cntl = MCURSOR_GAMMA_ENABLE; |
55a08b3f | 10158 | switch (plane_state->base.crtc_w) { |
4726e0b0 SK |
10159 | case 64: |
10160 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
10161 | break; | |
10162 | case 128: | |
10163 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
10164 | break; | |
10165 | case 256: | |
10166 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
10167 | break; | |
10168 | default: | |
55a08b3f | 10169 | MISSING_CASE(plane_state->base.crtc_w); |
4726e0b0 | 10170 | return; |
65a21cd6 | 10171 | } |
4b0e333e | 10172 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 | 10173 | |
fc6f93bc | 10174 | if (HAS_DDI(dev)) |
47bf17a7 | 10175 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
65a21cd6 | 10176 | |
55a08b3f ML |
10177 | if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) |
10178 | cntl |= CURSOR_ROTATE_180; | |
10179 | } | |
4398ad45 | 10180 | |
4b0e333e CW |
10181 | if (intel_crtc->cursor_cntl != cntl) { |
10182 | I915_WRITE(CURCNTR(pipe), cntl); | |
10183 | POSTING_READ(CURCNTR(pipe)); | |
10184 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 10185 | } |
4b0e333e | 10186 | |
65a21cd6 | 10187 | /* and commit changes on next vblank */ |
5efb3e28 VS |
10188 | I915_WRITE(CURBASE(pipe), base); |
10189 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
10190 | |
10191 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
10192 | } |
10193 | ||
cda4b7d3 | 10194 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f | 10195 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
55a08b3f | 10196 | const struct intel_plane_state *plane_state) |
cda4b7d3 CW |
10197 | { |
10198 | struct drm_device *dev = crtc->dev; | |
10199 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10200 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10201 | int pipe = intel_crtc->pipe; | |
55a08b3f ML |
10202 | u32 base = intel_crtc->cursor_addr; |
10203 | u32 pos = 0; | |
cda4b7d3 | 10204 | |
55a08b3f ML |
10205 | if (plane_state) { |
10206 | int x = plane_state->base.crtc_x; | |
10207 | int y = plane_state->base.crtc_y; | |
cda4b7d3 | 10208 | |
55a08b3f ML |
10209 | if (x < 0) { |
10210 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
10211 | x = -x; | |
10212 | } | |
10213 | pos |= x << CURSOR_X_SHIFT; | |
cda4b7d3 | 10214 | |
55a08b3f ML |
10215 | if (y < 0) { |
10216 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
10217 | y = -y; | |
10218 | } | |
10219 | pos |= y << CURSOR_Y_SHIFT; | |
10220 | ||
10221 | /* ILK+ do this automagically */ | |
10222 | if (HAS_GMCH_DISPLAY(dev) && | |
10223 | plane_state->base.rotation == BIT(DRM_ROTATE_180)) { | |
10224 | base += (plane_state->base.crtc_h * | |
10225 | plane_state->base.crtc_w - 1) * 4; | |
10226 | } | |
cda4b7d3 | 10227 | } |
cda4b7d3 | 10228 | |
5efb3e28 VS |
10229 | I915_WRITE(CURPOS(pipe), pos); |
10230 | ||
8ac54669 | 10231 | if (IS_845G(dev) || IS_I865G(dev)) |
55a08b3f | 10232 | i845_update_cursor(crtc, base, plane_state); |
5efb3e28 | 10233 | else |
55a08b3f | 10234 | i9xx_update_cursor(crtc, base, plane_state); |
cda4b7d3 CW |
10235 | } |
10236 | ||
dc41c154 VS |
10237 | static bool cursor_size_ok(struct drm_device *dev, |
10238 | uint32_t width, uint32_t height) | |
10239 | { | |
10240 | if (width == 0 || height == 0) | |
10241 | return false; | |
10242 | ||
10243 | /* | |
10244 | * 845g/865g are special in that they are only limited by | |
10245 | * the width of their cursors, the height is arbitrary up to | |
10246 | * the precision of the register. Everything else requires | |
10247 | * square cursors, limited to a few power-of-two sizes. | |
10248 | */ | |
10249 | if (IS_845G(dev) || IS_I865G(dev)) { | |
10250 | if ((width & 63) != 0) | |
10251 | return false; | |
10252 | ||
10253 | if (width > (IS_845G(dev) ? 64 : 512)) | |
10254 | return false; | |
10255 | ||
10256 | if (height > 1023) | |
10257 | return false; | |
10258 | } else { | |
10259 | switch (width | height) { | |
10260 | case 256: | |
10261 | case 128: | |
10262 | if (IS_GEN2(dev)) | |
10263 | return false; | |
10264 | case 64: | |
10265 | break; | |
10266 | default: | |
10267 | return false; | |
10268 | } | |
10269 | } | |
10270 | ||
10271 | return true; | |
10272 | } | |
10273 | ||
79e53945 JB |
10274 | /* VESA 640x480x72Hz mode to set on the pipe */ |
10275 | static struct drm_display_mode load_detect_mode = { | |
10276 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
10277 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
10278 | }; | |
10279 | ||
a8bb6818 DV |
10280 | struct drm_framebuffer * |
10281 | __intel_framebuffer_create(struct drm_device *dev, | |
10282 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10283 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
10284 | { |
10285 | struct intel_framebuffer *intel_fb; | |
10286 | int ret; | |
10287 | ||
10288 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
dcb1394e | 10289 | if (!intel_fb) |
d2dff872 | 10290 | return ERR_PTR(-ENOMEM); |
d2dff872 CW |
10291 | |
10292 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
10293 | if (ret) |
10294 | goto err; | |
d2dff872 CW |
10295 | |
10296 | return &intel_fb->base; | |
dcb1394e | 10297 | |
dd4916c5 | 10298 | err: |
dd4916c5 | 10299 | kfree(intel_fb); |
dd4916c5 | 10300 | return ERR_PTR(ret); |
d2dff872 CW |
10301 | } |
10302 | ||
b5ea642a | 10303 | static struct drm_framebuffer * |
a8bb6818 DV |
10304 | intel_framebuffer_create(struct drm_device *dev, |
10305 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10306 | struct drm_i915_gem_object *obj) | |
10307 | { | |
10308 | struct drm_framebuffer *fb; | |
10309 | int ret; | |
10310 | ||
10311 | ret = i915_mutex_lock_interruptible(dev); | |
10312 | if (ret) | |
10313 | return ERR_PTR(ret); | |
10314 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
10315 | mutex_unlock(&dev->struct_mutex); | |
10316 | ||
10317 | return fb; | |
10318 | } | |
10319 | ||
d2dff872 CW |
10320 | static u32 |
10321 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
10322 | { | |
10323 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
10324 | return ALIGN(pitch, 64); | |
10325 | } | |
10326 | ||
10327 | static u32 | |
10328 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
10329 | { | |
10330 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 10331 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
10332 | } |
10333 | ||
10334 | static struct drm_framebuffer * | |
10335 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
10336 | struct drm_display_mode *mode, | |
10337 | int depth, int bpp) | |
10338 | { | |
dcb1394e | 10339 | struct drm_framebuffer *fb; |
d2dff872 | 10340 | struct drm_i915_gem_object *obj; |
0fed39bd | 10341 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 | 10342 | |
d37cd8a8 | 10343 | obj = i915_gem_object_create(dev, |
d2dff872 | 10344 | intel_framebuffer_size_for_mode(mode, bpp)); |
fe3db79b CW |
10345 | if (IS_ERR(obj)) |
10346 | return ERR_CAST(obj); | |
d2dff872 CW |
10347 | |
10348 | mode_cmd.width = mode->hdisplay; | |
10349 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
10350 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
10351 | bpp); | |
5ca0c34a | 10352 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 | 10353 | |
dcb1394e LW |
10354 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
10355 | if (IS_ERR(fb)) | |
10356 | drm_gem_object_unreference_unlocked(&obj->base); | |
10357 | ||
10358 | return fb; | |
d2dff872 CW |
10359 | } |
10360 | ||
10361 | static struct drm_framebuffer * | |
10362 | mode_fits_in_fbdev(struct drm_device *dev, | |
10363 | struct drm_display_mode *mode) | |
10364 | { | |
0695726e | 10365 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
d2dff872 CW |
10366 | struct drm_i915_private *dev_priv = dev->dev_private; |
10367 | struct drm_i915_gem_object *obj; | |
10368 | struct drm_framebuffer *fb; | |
10369 | ||
4c0e5528 | 10370 | if (!dev_priv->fbdev) |
d2dff872 CW |
10371 | return NULL; |
10372 | ||
4c0e5528 | 10373 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
10374 | return NULL; |
10375 | ||
4c0e5528 DV |
10376 | obj = dev_priv->fbdev->fb->obj; |
10377 | BUG_ON(!obj); | |
10378 | ||
8bcd4553 | 10379 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
10380 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
10381 | fb->bits_per_pixel)) | |
d2dff872 CW |
10382 | return NULL; |
10383 | ||
01f2c773 | 10384 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
10385 | return NULL; |
10386 | ||
edde3617 | 10387 | drm_framebuffer_reference(fb); |
d2dff872 | 10388 | return fb; |
4520f53a DV |
10389 | #else |
10390 | return NULL; | |
10391 | #endif | |
d2dff872 CW |
10392 | } |
10393 | ||
d3a40d1b ACO |
10394 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
10395 | struct drm_crtc *crtc, | |
10396 | struct drm_display_mode *mode, | |
10397 | struct drm_framebuffer *fb, | |
10398 | int x, int y) | |
10399 | { | |
10400 | struct drm_plane_state *plane_state; | |
10401 | int hdisplay, vdisplay; | |
10402 | int ret; | |
10403 | ||
10404 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
10405 | if (IS_ERR(plane_state)) | |
10406 | return PTR_ERR(plane_state); | |
10407 | ||
10408 | if (mode) | |
10409 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); | |
10410 | else | |
10411 | hdisplay = vdisplay = 0; | |
10412 | ||
10413 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
10414 | if (ret) | |
10415 | return ret; | |
10416 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
10417 | plane_state->crtc_x = 0; | |
10418 | plane_state->crtc_y = 0; | |
10419 | plane_state->crtc_w = hdisplay; | |
10420 | plane_state->crtc_h = vdisplay; | |
10421 | plane_state->src_x = x << 16; | |
10422 | plane_state->src_y = y << 16; | |
10423 | plane_state->src_w = hdisplay << 16; | |
10424 | plane_state->src_h = vdisplay << 16; | |
10425 | ||
10426 | return 0; | |
10427 | } | |
10428 | ||
d2434ab7 | 10429 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 10430 | struct drm_display_mode *mode, |
51fd371b RC |
10431 | struct intel_load_detect_pipe *old, |
10432 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
10433 | { |
10434 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
10435 | struct intel_encoder *intel_encoder = |
10436 | intel_attached_encoder(connector); | |
79e53945 | 10437 | struct drm_crtc *possible_crtc; |
4ef69c7a | 10438 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
10439 | struct drm_crtc *crtc = NULL; |
10440 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 10441 | struct drm_framebuffer *fb; |
51fd371b | 10442 | struct drm_mode_config *config = &dev->mode_config; |
edde3617 | 10443 | struct drm_atomic_state *state = NULL, *restore_state = NULL; |
944b0c76 | 10444 | struct drm_connector_state *connector_state; |
4be07317 | 10445 | struct intel_crtc_state *crtc_state; |
51fd371b | 10446 | int ret, i = -1; |
79e53945 | 10447 | |
d2dff872 | 10448 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10449 | connector->base.id, connector->name, |
8e329a03 | 10450 | encoder->base.id, encoder->name); |
d2dff872 | 10451 | |
edde3617 ML |
10452 | old->restore_state = NULL; |
10453 | ||
51fd371b RC |
10454 | retry: |
10455 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
10456 | if (ret) | |
ad3c558f | 10457 | goto fail; |
6e9f798d | 10458 | |
79e53945 JB |
10459 | /* |
10460 | * Algorithm gets a little messy: | |
7a5e4805 | 10461 | * |
79e53945 JB |
10462 | * - if the connector already has an assigned crtc, use it (but make |
10463 | * sure it's on first) | |
7a5e4805 | 10464 | * |
79e53945 JB |
10465 | * - try to find the first unused crtc that can drive this connector, |
10466 | * and use that if we find one | |
79e53945 JB |
10467 | */ |
10468 | ||
10469 | /* See if we already have a CRTC for this connector */ | |
edde3617 ML |
10470 | if (connector->state->crtc) { |
10471 | crtc = connector->state->crtc; | |
8261b191 | 10472 | |
51fd371b | 10473 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 10474 | if (ret) |
ad3c558f | 10475 | goto fail; |
8261b191 CW |
10476 | |
10477 | /* Make sure the crtc and connector are running */ | |
edde3617 | 10478 | goto found; |
79e53945 JB |
10479 | } |
10480 | ||
10481 | /* Find an unused one (if possible) */ | |
70e1e0ec | 10482 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
10483 | i++; |
10484 | if (!(encoder->possible_crtcs & (1 << i))) | |
10485 | continue; | |
edde3617 ML |
10486 | |
10487 | ret = drm_modeset_lock(&possible_crtc->mutex, ctx); | |
10488 | if (ret) | |
10489 | goto fail; | |
10490 | ||
10491 | if (possible_crtc->state->enable) { | |
10492 | drm_modeset_unlock(&possible_crtc->mutex); | |
a459249c | 10493 | continue; |
edde3617 | 10494 | } |
a459249c VS |
10495 | |
10496 | crtc = possible_crtc; | |
10497 | break; | |
79e53945 JB |
10498 | } |
10499 | ||
10500 | /* | |
10501 | * If we didn't find an unused CRTC, don't use any. | |
10502 | */ | |
10503 | if (!crtc) { | |
7173188d | 10504 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
ad3c558f | 10505 | goto fail; |
79e53945 JB |
10506 | } |
10507 | ||
edde3617 ML |
10508 | found: |
10509 | intel_crtc = to_intel_crtc(crtc); | |
10510 | ||
4d02e2de DV |
10511 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
10512 | if (ret) | |
ad3c558f | 10513 | goto fail; |
79e53945 | 10514 | |
83a57153 | 10515 | state = drm_atomic_state_alloc(dev); |
edde3617 ML |
10516 | restore_state = drm_atomic_state_alloc(dev); |
10517 | if (!state || !restore_state) { | |
10518 | ret = -ENOMEM; | |
10519 | goto fail; | |
10520 | } | |
83a57153 ACO |
10521 | |
10522 | state->acquire_ctx = ctx; | |
edde3617 | 10523 | restore_state->acquire_ctx = ctx; |
83a57153 | 10524 | |
944b0c76 ACO |
10525 | connector_state = drm_atomic_get_connector_state(state, connector); |
10526 | if (IS_ERR(connector_state)) { | |
10527 | ret = PTR_ERR(connector_state); | |
10528 | goto fail; | |
10529 | } | |
10530 | ||
edde3617 ML |
10531 | ret = drm_atomic_set_crtc_for_connector(connector_state, crtc); |
10532 | if (ret) | |
10533 | goto fail; | |
944b0c76 | 10534 | |
4be07317 ACO |
10535 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10536 | if (IS_ERR(crtc_state)) { | |
10537 | ret = PTR_ERR(crtc_state); | |
10538 | goto fail; | |
10539 | } | |
10540 | ||
49d6fa21 | 10541 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 10542 | |
6492711d CW |
10543 | if (!mode) |
10544 | mode = &load_detect_mode; | |
79e53945 | 10545 | |
d2dff872 CW |
10546 | /* We need a framebuffer large enough to accommodate all accesses |
10547 | * that the plane may generate whilst we perform load detection. | |
10548 | * We can not rely on the fbcon either being present (we get called | |
10549 | * during its initialisation to detect all boot displays, or it may | |
10550 | * not even exist) or that it is large enough to satisfy the | |
10551 | * requested mode. | |
10552 | */ | |
94352cf9 DV |
10553 | fb = mode_fits_in_fbdev(dev, mode); |
10554 | if (fb == NULL) { | |
d2dff872 | 10555 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 | 10556 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
d2dff872 CW |
10557 | } else |
10558 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 10559 | if (IS_ERR(fb)) { |
d2dff872 | 10560 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 10561 | goto fail; |
79e53945 | 10562 | } |
79e53945 | 10563 | |
d3a40d1b ACO |
10564 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
10565 | if (ret) | |
10566 | goto fail; | |
10567 | ||
edde3617 ML |
10568 | drm_framebuffer_unreference(fb); |
10569 | ||
10570 | ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode); | |
10571 | if (ret) | |
10572 | goto fail; | |
10573 | ||
10574 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); | |
10575 | if (!ret) | |
10576 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc)); | |
10577 | if (!ret) | |
10578 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary)); | |
10579 | if (ret) { | |
10580 | DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret); | |
10581 | goto fail; | |
10582 | } | |
8c7b5ccb | 10583 | |
3ba86073 ML |
10584 | ret = drm_atomic_commit(state); |
10585 | if (ret) { | |
6492711d | 10586 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
412b61d8 | 10587 | goto fail; |
79e53945 | 10588 | } |
edde3617 ML |
10589 | |
10590 | old->restore_state = restore_state; | |
7173188d | 10591 | |
79e53945 | 10592 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 10593 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 10594 | return true; |
412b61d8 | 10595 | |
ad3c558f | 10596 | fail: |
e5d958ef | 10597 | drm_atomic_state_free(state); |
edde3617 ML |
10598 | drm_atomic_state_free(restore_state); |
10599 | restore_state = state = NULL; | |
83a57153 | 10600 | |
51fd371b RC |
10601 | if (ret == -EDEADLK) { |
10602 | drm_modeset_backoff(ctx); | |
10603 | goto retry; | |
10604 | } | |
10605 | ||
412b61d8 | 10606 | return false; |
79e53945 JB |
10607 | } |
10608 | ||
d2434ab7 | 10609 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
10610 | struct intel_load_detect_pipe *old, |
10611 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 10612 | { |
d2434ab7 DV |
10613 | struct intel_encoder *intel_encoder = |
10614 | intel_attached_encoder(connector); | |
4ef69c7a | 10615 | struct drm_encoder *encoder = &intel_encoder->base; |
edde3617 | 10616 | struct drm_atomic_state *state = old->restore_state; |
d3a40d1b | 10617 | int ret; |
79e53945 | 10618 | |
d2dff872 | 10619 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10620 | connector->base.id, connector->name, |
8e329a03 | 10621 | encoder->base.id, encoder->name); |
d2dff872 | 10622 | |
edde3617 | 10623 | if (!state) |
0622a53c | 10624 | return; |
79e53945 | 10625 | |
edde3617 ML |
10626 | ret = drm_atomic_commit(state); |
10627 | if (ret) { | |
10628 | DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret); | |
10629 | drm_atomic_state_free(state); | |
10630 | } | |
79e53945 JB |
10631 | } |
10632 | ||
da4a1efa | 10633 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 10634 | const struct intel_crtc_state *pipe_config) |
da4a1efa VS |
10635 | { |
10636 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10637 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
10638 | ||
10639 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 10640 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
10641 | else if (HAS_PCH_SPLIT(dev)) |
10642 | return 120000; | |
10643 | else if (!IS_GEN2(dev)) | |
10644 | return 96000; | |
10645 | else | |
10646 | return 48000; | |
10647 | } | |
10648 | ||
79e53945 | 10649 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 10650 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 10651 | struct intel_crtc_state *pipe_config) |
79e53945 | 10652 | { |
f1f644dc | 10653 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 10654 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 10655 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 10656 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 | 10657 | u32 fp; |
9e2c8475 | 10658 | struct dpll clock; |
dccbea3b | 10659 | int port_clock; |
da4a1efa | 10660 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
10661 | |
10662 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 10663 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 10664 | else |
293623f7 | 10665 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
10666 | |
10667 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
10668 | if (IS_PINEVIEW(dev)) { |
10669 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
10670 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
10671 | } else { |
10672 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
10673 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
10674 | } | |
10675 | ||
a6c45cf0 | 10676 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
10677 | if (IS_PINEVIEW(dev)) |
10678 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
10679 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
10680 | else |
10681 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
10682 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
10683 | ||
10684 | switch (dpll & DPLL_MODE_MASK) { | |
10685 | case DPLLB_MODE_DAC_SERIAL: | |
10686 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
10687 | 5 : 10; | |
10688 | break; | |
10689 | case DPLLB_MODE_LVDS: | |
10690 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
10691 | 7 : 14; | |
10692 | break; | |
10693 | default: | |
28c97730 | 10694 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 10695 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 10696 | return; |
79e53945 JB |
10697 | } |
10698 | ||
ac58c3f0 | 10699 | if (IS_PINEVIEW(dev)) |
dccbea3b | 10700 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 10701 | else |
dccbea3b | 10702 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 10703 | } else { |
0fb58223 | 10704 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 10705 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
10706 | |
10707 | if (is_lvds) { | |
10708 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
10709 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
10710 | |
10711 | if (lvds & LVDS_CLKB_POWER_UP) | |
10712 | clock.p2 = 7; | |
10713 | else | |
10714 | clock.p2 = 14; | |
79e53945 JB |
10715 | } else { |
10716 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
10717 | clock.p1 = 2; | |
10718 | else { | |
10719 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
10720 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
10721 | } | |
10722 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
10723 | clock.p2 = 4; | |
10724 | else | |
10725 | clock.p2 = 2; | |
79e53945 | 10726 | } |
da4a1efa | 10727 | |
dccbea3b | 10728 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
10729 | } |
10730 | ||
18442d08 VS |
10731 | /* |
10732 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 10733 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
10734 | * encoder's get_config() function. |
10735 | */ | |
dccbea3b | 10736 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
10737 | } |
10738 | ||
6878da05 VS |
10739 | int intel_dotclock_calculate(int link_freq, |
10740 | const struct intel_link_m_n *m_n) | |
f1f644dc | 10741 | { |
f1f644dc JB |
10742 | /* |
10743 | * The calculation for the data clock is: | |
1041a02f | 10744 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 10745 | * But we want to avoid losing precison if possible, so: |
1041a02f | 10746 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
10747 | * |
10748 | * and the link clock is simpler: | |
1041a02f | 10749 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
10750 | */ |
10751 | ||
6878da05 VS |
10752 | if (!m_n->link_n) |
10753 | return 0; | |
f1f644dc | 10754 | |
6878da05 VS |
10755 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
10756 | } | |
f1f644dc | 10757 | |
18442d08 | 10758 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 10759 | struct intel_crtc_state *pipe_config) |
6878da05 | 10760 | { |
e3b247da | 10761 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
79e53945 | 10762 | |
18442d08 VS |
10763 | /* read out port_clock from the DPLL */ |
10764 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 10765 | |
f1f644dc | 10766 | /* |
e3b247da VS |
10767 | * In case there is an active pipe without active ports, |
10768 | * we may need some idea for the dotclock anyway. | |
10769 | * Calculate one based on the FDI configuration. | |
79e53945 | 10770 | */ |
2d112de7 | 10771 | pipe_config->base.adjusted_mode.crtc_clock = |
21a727b3 | 10772 | intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
18442d08 | 10773 | &pipe_config->fdi_m_n); |
79e53945 JB |
10774 | } |
10775 | ||
10776 | /** Returns the currently programmed mode of the given pipe. */ | |
10777 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
10778 | struct drm_crtc *crtc) | |
10779 | { | |
548f245b | 10780 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 10781 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 10782 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 10783 | struct drm_display_mode *mode; |
3f36b937 | 10784 | struct intel_crtc_state *pipe_config; |
fe2b8f9d PZ |
10785 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
10786 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
10787 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
10788 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 10789 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
10790 | |
10791 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
10792 | if (!mode) | |
10793 | return NULL; | |
10794 | ||
3f36b937 TU |
10795 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
10796 | if (!pipe_config) { | |
10797 | kfree(mode); | |
10798 | return NULL; | |
10799 | } | |
10800 | ||
f1f644dc JB |
10801 | /* |
10802 | * Construct a pipe_config sufficient for getting the clock info | |
10803 | * back out of crtc_clock_get. | |
10804 | * | |
10805 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
10806 | * to use a real value here instead. | |
10807 | */ | |
3f36b937 TU |
10808 | pipe_config->cpu_transcoder = (enum transcoder) pipe; |
10809 | pipe_config->pixel_multiplier = 1; | |
10810 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe)); | |
10811 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
10812 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
10813 | i9xx_crtc_clock_get(intel_crtc, pipe_config); | |
10814 | ||
10815 | mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier; | |
79e53945 JB |
10816 | mode->hdisplay = (htot & 0xffff) + 1; |
10817 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
10818 | mode->hsync_start = (hsync & 0xffff) + 1; | |
10819 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
10820 | mode->vdisplay = (vtot & 0xffff) + 1; | |
10821 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
10822 | mode->vsync_start = (vsync & 0xffff) + 1; | |
10823 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
10824 | ||
10825 | drm_mode_set_name(mode); | |
79e53945 | 10826 | |
3f36b937 TU |
10827 | kfree(pipe_config); |
10828 | ||
79e53945 JB |
10829 | return mode; |
10830 | } | |
10831 | ||
7d993739 | 10832 | void intel_mark_busy(struct drm_i915_private *dev_priv) |
f047e395 | 10833 | { |
f62a0076 CW |
10834 | if (dev_priv->mm.busy) |
10835 | return; | |
10836 | ||
43694d69 | 10837 | intel_runtime_pm_get(dev_priv); |
c67a470b | 10838 | i915_update_gfx_val(dev_priv); |
7d993739 | 10839 | if (INTEL_GEN(dev_priv) >= 6) |
43cf3bf0 | 10840 | gen6_rps_busy(dev_priv); |
f62a0076 | 10841 | dev_priv->mm.busy = true; |
f047e395 CW |
10842 | } |
10843 | ||
7d993739 | 10844 | void intel_mark_idle(struct drm_i915_private *dev_priv) |
652c393a | 10845 | { |
f62a0076 CW |
10846 | if (!dev_priv->mm.busy) |
10847 | return; | |
10848 | ||
10849 | dev_priv->mm.busy = false; | |
10850 | ||
7d993739 TU |
10851 | if (INTEL_GEN(dev_priv) >= 6) |
10852 | gen6_rps_idle(dev_priv); | |
bb4cdd53 | 10853 | |
43694d69 | 10854 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
10855 | } |
10856 | ||
a6747b73 | 10857 | void intel_free_flip_work(struct intel_flip_work *work) |
03f476e1 ML |
10858 | { |
10859 | kfree(work->old_connector_state); | |
10860 | kfree(work->new_connector_state); | |
10861 | kfree(work); | |
10862 | } | |
10863 | ||
79e53945 JB |
10864 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
10865 | { | |
10866 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a | 10867 | struct drm_device *dev = crtc->dev; |
51cbaf01 | 10868 | struct intel_flip_work *work; |
67e77c5a | 10869 | |
5e2d7afc | 10870 | spin_lock_irq(&dev->event_lock); |
6885843a ML |
10871 | while (!list_empty(&intel_crtc->flip_work)) { |
10872 | work = list_first_entry(&intel_crtc->flip_work, | |
10873 | struct intel_flip_work, head); | |
10874 | list_del_init(&work->head); | |
10875 | spin_unlock_irq(&dev->event_lock); | |
67e77c5a | 10876 | |
51cbaf01 ML |
10877 | cancel_work_sync(&work->mmio_work); |
10878 | cancel_work_sync(&work->unpin_work); | |
03f476e1 | 10879 | intel_free_flip_work(work); |
6885843a ML |
10880 | |
10881 | spin_lock_irq(&dev->event_lock); | |
67e77c5a | 10882 | } |
6885843a | 10883 | spin_unlock_irq(&dev->event_lock); |
79e53945 JB |
10884 | |
10885 | drm_crtc_cleanup(crtc); | |
67e77c5a | 10886 | |
79e53945 JB |
10887 | kfree(intel_crtc); |
10888 | } | |
10889 | ||
143f73b3 ML |
10890 | static void intel_crtc_post_flip_update(struct intel_flip_work *work, |
10891 | struct drm_crtc *crtc) | |
10892 | { | |
10893 | struct intel_crtc_state *crtc_state = work->new_crtc_state; | |
10894 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10895 | ||
10896 | if (crtc_state->disable_cxsr) | |
10897 | intel_crtc->wm.cxsr_allowed = true; | |
10898 | ||
10899 | if (crtc_state->update_wm_post && crtc_state->base.active) | |
10900 | intel_update_watermarks(crtc); | |
10901 | ||
10902 | if (work->num_planes > 0 && | |
10903 | work->old_plane_state[0]->base.plane == crtc->primary) { | |
10904 | struct intel_plane_state *plane_state = | |
10905 | work->new_plane_state[0]; | |
10906 | ||
10907 | if (plane_state->visible && | |
10908 | (needs_modeset(&crtc_state->base) || | |
10909 | !work->old_plane_state[0]->visible)) | |
10910 | intel_post_enable_primary(crtc); | |
10911 | } | |
10912 | } | |
10913 | ||
6b95a207 KH |
10914 | static void intel_unpin_work_fn(struct work_struct *__work) |
10915 | { | |
51cbaf01 ML |
10916 | struct intel_flip_work *work = |
10917 | container_of(__work, struct intel_flip_work, unpin_work); | |
143f73b3 ML |
10918 | struct drm_crtc *crtc = work->old_crtc_state->base.crtc; |
10919 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10920 | struct drm_device *dev = crtc->dev; | |
10921 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10922 | int i; | |
6b95a207 | 10923 | |
143f73b3 ML |
10924 | if (work->fb_bits) |
10925 | intel_frontbuffer_flip_complete(dev, work->fb_bits); | |
51cbaf01 | 10926 | |
143f73b3 ML |
10927 | /* |
10928 | * Unless work->can_async_unpin is false, there's no way to ensure | |
10929 | * that work->new_crtc_state contains valid memory during unpin | |
10930 | * because intel_atomic_commit may free it before this runs. | |
10931 | */ | |
a6747b73 | 10932 | if (!work->can_async_unpin) { |
143f73b3 ML |
10933 | intel_crtc_post_flip_update(work, crtc); |
10934 | ||
a6747b73 ML |
10935 | if (dev_priv->display.optimize_watermarks) |
10936 | dev_priv->display.optimize_watermarks(work->new_crtc_state); | |
10937 | } | |
10938 | ||
143f73b3 ML |
10939 | if (work->fb_bits & to_intel_plane(crtc->primary)->frontbuffer_bit) |
10940 | intel_fbc_post_update(intel_crtc); | |
10941 | ||
10942 | if (work->put_power_domains) | |
10943 | modeset_put_power_domains(dev_priv, work->put_power_domains); | |
10944 | ||
10945 | /* Make sure mmio work is completely finished before freeing all state here. */ | |
10946 | flush_work(&work->mmio_work); | |
10947 | ||
03f476e1 ML |
10948 | if (!work->can_async_unpin && |
10949 | (work->new_crtc_state->update_pipe || | |
10950 | needs_modeset(&work->new_crtc_state->base))) { | |
143f73b3 ML |
10951 | /* This must be called before work is unpinned for serialization. */ |
10952 | intel_modeset_verify_crtc(crtc, &work->old_crtc_state->base, | |
10953 | &work->new_crtc_state->base); | |
10954 | ||
03f476e1 ML |
10955 | for (i = 0; i < work->num_new_connectors; i++) { |
10956 | struct drm_connector_state *conn_state = | |
10957 | work->new_connector_state[i]; | |
10958 | struct drm_connector *con = conn_state->connector; | |
10959 | ||
a6747b73 ML |
10960 | WARN_ON(!con); |
10961 | ||
03f476e1 ML |
10962 | intel_connector_verify_state(to_intel_connector(con), |
10963 | conn_state); | |
10964 | } | |
10965 | } | |
10966 | ||
10967 | for (i = 0; i < work->num_old_connectors; i++) { | |
10968 | struct drm_connector_state *old_con_state = | |
10969 | work->old_connector_state[i]; | |
10970 | struct drm_connector *con = | |
10971 | old_con_state->connector; | |
10972 | ||
10973 | con->funcs->atomic_destroy_state(con, old_con_state); | |
10974 | } | |
10975 | ||
143f73b3 ML |
10976 | if (!work->can_async_unpin || !list_empty(&work->head)) { |
10977 | spin_lock_irq(&dev->event_lock); | |
10978 | WARN(list_empty(&work->head) != work->can_async_unpin, | |
10979 | "[CRTC:%i] Pin work %p async %i with %i planes, active %i -> %i ms %i\n", | |
10980 | crtc->base.id, work, work->can_async_unpin, work->num_planes, | |
10981 | work->old_crtc_state->base.active, work->new_crtc_state->base.active, | |
10982 | needs_modeset(&work->new_crtc_state->base)); | |
10983 | ||
10984 | if (!list_empty(&work->head)) | |
10985 | list_del(&work->head); | |
10986 | ||
10987 | wake_up_all(&dev_priv->pending_flip_queue); | |
10988 | spin_unlock_irq(&dev->event_lock); | |
10989 | } | |
10990 | ||
a6747b73 ML |
10991 | /* New crtc_state freed? */ |
10992 | if (work->free_new_crtc_state) | |
10993 | intel_crtc_destroy_state(crtc, &work->new_crtc_state->base); | |
10994 | ||
143f73b3 | 10995 | intel_crtc_destroy_state(crtc, &work->old_crtc_state->base); |
d9e86c0e | 10996 | |
143f73b3 ML |
10997 | for (i = 0; i < work->num_planes; i++) { |
10998 | struct intel_plane_state *old_plane_state = | |
10999 | work->old_plane_state[i]; | |
11000 | struct drm_framebuffer *old_fb = old_plane_state->base.fb; | |
11001 | struct drm_plane *plane = old_plane_state->base.plane; | |
11002 | struct drm_i915_gem_request *req; | |
11003 | ||
11004 | req = old_plane_state->wait_req; | |
11005 | old_plane_state->wait_req = NULL; | |
a6747b73 ML |
11006 | if (req) |
11007 | i915_gem_request_unreference(req); | |
143f73b3 ML |
11008 | |
11009 | fence_put(old_plane_state->base.fence); | |
11010 | old_plane_state->base.fence = NULL; | |
11011 | ||
11012 | if (old_fb && | |
11013 | (plane->type != DRM_PLANE_TYPE_CURSOR || | |
11014 | !INTEL_INFO(dev_priv)->cursor_needs_physical)) { | |
11015 | mutex_lock(&dev->struct_mutex); | |
11016 | intel_unpin_fb_obj(old_fb, old_plane_state->base.rotation); | |
11017 | mutex_unlock(&dev->struct_mutex); | |
11018 | } | |
b4a98e57 | 11019 | |
143f73b3 ML |
11020 | intel_plane_destroy_state(plane, &old_plane_state->base); |
11021 | } | |
f99d7069 | 11022 | |
143f73b3 ML |
11023 | if (!WARN_ON(atomic_read(&intel_crtc->unpin_work_count) == 0)) |
11024 | atomic_dec(&intel_crtc->unpin_work_count); | |
b4a98e57 | 11025 | |
03f476e1 | 11026 | intel_free_flip_work(work); |
6b95a207 KH |
11027 | } |
11028 | ||
51cbaf01 ML |
11029 | |
11030 | static bool pageflip_finished(struct intel_crtc *crtc, | |
11031 | struct intel_flip_work *work) | |
11032 | { | |
11033 | if (!atomic_read(&work->pending)) | |
11034 | return false; | |
11035 | ||
11036 | smp_rmb(); | |
11037 | ||
51cbaf01 | 11038 | /* |
8dd634d9 ML |
11039 | * MMIO work completes when vblank is different from |
11040 | * flip_queued_vblank. | |
51cbaf01 | 11041 | */ |
8dd634d9 | 11042 | return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank; |
75f7f3ec VS |
11043 | } |
11044 | ||
51cbaf01 | 11045 | void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe) |
6b95a207 | 11046 | { |
91d14251 | 11047 | struct drm_device *dev = dev_priv->dev; |
5251f04e ML |
11048 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
11049 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
51cbaf01 | 11050 | struct intel_flip_work *work; |
6b95a207 KH |
11051 | unsigned long flags; |
11052 | ||
5251f04e ML |
11053 | /* Ignore early vblank irqs */ |
11054 | if (!crtc) | |
11055 | return; | |
f326038a DV |
11056 | |
11057 | /* | |
11058 | * This is called both by irq handlers and the reset code (to complete | |
11059 | * lost pageflips) so needs the full irqsave spinlocks. | |
e7d841ca | 11060 | */ |
6b95a207 | 11061 | spin_lock_irqsave(&dev->event_lock, flags); |
6885843a ML |
11062 | while (!list_empty(&intel_crtc->flip_work)) { |
11063 | work = list_first_entry(&intel_crtc->flip_work, | |
11064 | struct intel_flip_work, | |
11065 | head); | |
5251f04e | 11066 | |
143f73b3 ML |
11067 | if (!pageflip_finished(intel_crtc, work) || |
11068 | work_busy(&work->unpin_work)) | |
6885843a | 11069 | break; |
5251f04e | 11070 | |
6885843a ML |
11071 | page_flip_completed(intel_crtc, work); |
11072 | } | |
6b95a207 KH |
11073 | spin_unlock_irqrestore(&dev->event_lock, flags); |
11074 | } | |
11075 | ||
51cbaf01 | 11076 | static void intel_mmio_flip_work_func(struct work_struct *w) |
84c33a64 | 11077 | { |
51cbaf01 ML |
11078 | struct intel_flip_work *work = |
11079 | container_of(w, struct intel_flip_work, mmio_work); | |
143f73b3 ML |
11080 | struct drm_crtc *crtc = work->old_crtc_state->base.crtc; |
11081 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11082 | struct intel_crtc_state *crtc_state = work->new_crtc_state; | |
11083 | struct drm_device *dev = crtc->dev; | |
aa420ddd | 11084 | struct drm_i915_private *dev_priv = dev->dev_private; |
143f73b3 | 11085 | struct drm_i915_gem_request *req; |
d55dbd06 | 11086 | int i, ret; |
84c33a64 | 11087 | |
a6747b73 ML |
11088 | if (!needs_modeset(&crtc_state->base) && crtc_state->update_pipe) { |
11089 | work->put_power_domains = | |
11090 | modeset_get_crtc_power_domains(crtc, crtc_state); | |
11091 | } | |
11092 | ||
143f73b3 ML |
11093 | for (i = 0; i < work->num_planes; i++) { |
11094 | struct intel_plane_state *old_plane_state = work->old_plane_state[i]; | |
11095 | ||
11096 | /* For framebuffer backed by dmabuf, wait for fence */ | |
11097 | if (old_plane_state->base.fence) | |
11098 | WARN_ON(fence_wait(old_plane_state->base.fence, false) < 0); | |
11099 | ||
11100 | req = old_plane_state->wait_req; | |
11101 | if (!req) | |
11102 | continue; | |
11103 | ||
11104 | WARN_ON(__i915_wait_request(req, false, NULL, | |
51cbaf01 | 11105 | &dev_priv->rps.mmioflips)); |
143f73b3 | 11106 | } |
84c33a64 | 11107 | |
d55dbd06 ML |
11108 | ret = drm_crtc_vblank_get(crtc); |
11109 | I915_STATE_WARN(ret < 0, "enabling vblank failed with %i\n", ret); | |
11110 | ||
11111 | if (work->num_planes && | |
11112 | work->old_plane_state[0]->base.plane == crtc->primary) | |
11113 | intel_fbc_enable(intel_crtc, work->new_crtc_state, work->new_plane_state[0]); | |
11114 | ||
11115 | intel_frontbuffer_flip_prepare(dev, work->fb_bits); | |
fd8e058a | 11116 | |
143f73b3 ML |
11117 | intel_pipe_update_start(intel_crtc); |
11118 | if (!needs_modeset(&crtc_state->base)) { | |
11119 | if (crtc_state->base.color_mgmt_changed || crtc_state->update_pipe) { | |
11120 | intel_color_set_csc(&crtc_state->base); | |
11121 | intel_color_load_luts(&crtc_state->base); | |
11122 | } | |
84c33a64 | 11123 | |
143f73b3 ML |
11124 | if (crtc_state->update_pipe) |
11125 | intel_update_pipe_config(intel_crtc, work->old_crtc_state); | |
11126 | else if (INTEL_INFO(dev)->gen >= 9) | |
11127 | skl_detach_scalers(intel_crtc); | |
11128 | } | |
11129 | ||
11130 | for (i = 0; i < work->num_planes; i++) { | |
11131 | struct intel_plane_state *new_plane_state = work->new_plane_state[i]; | |
11132 | struct intel_plane *plane = to_intel_plane(new_plane_state->base.plane); | |
11133 | ||
d55dbd06 ML |
11134 | if (new_plane_state->visible) |
11135 | plane->update_plane(&plane->base, crtc_state, new_plane_state); | |
11136 | else | |
11137 | plane->disable_plane(&plane->base, crtc); | |
143f73b3 ML |
11138 | } |
11139 | ||
11140 | intel_pipe_update_end(intel_crtc, work); | |
8c9f3aaf JB |
11141 | } |
11142 | ||
da20eabd ML |
11143 | /** |
11144 | * intel_wm_need_update - Check whether watermarks need updating | |
11145 | * @plane: drm plane | |
11146 | * @state: new plane state | |
11147 | * | |
11148 | * Check current plane state versus the new one to determine whether | |
11149 | * watermarks need to be recalculated. | |
11150 | * | |
11151 | * Returns true or false. | |
11152 | */ | |
11153 | static bool intel_wm_need_update(struct drm_plane *plane, | |
11154 | struct drm_plane_state *state) | |
11155 | { | |
d21fbe87 MR |
11156 | struct intel_plane_state *new = to_intel_plane_state(state); |
11157 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); | |
11158 | ||
11159 | /* Update watermarks on tiling or size changes. */ | |
92826fcd ML |
11160 | if (new->visible != cur->visible) |
11161 | return true; | |
11162 | ||
11163 | if (!cur->base.fb || !new->base.fb) | |
11164 | return false; | |
11165 | ||
11166 | if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] || | |
11167 | cur->base.rotation != new->base.rotation || | |
d21fbe87 MR |
11168 | drm_rect_width(&new->src) != drm_rect_width(&cur->src) || |
11169 | drm_rect_height(&new->src) != drm_rect_height(&cur->src) || | |
11170 | drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) || | |
11171 | drm_rect_height(&new->dst) != drm_rect_height(&cur->dst)) | |
2791a16c | 11172 | return true; |
7809e5ae | 11173 | |
2791a16c | 11174 | return false; |
7809e5ae MR |
11175 | } |
11176 | ||
d21fbe87 MR |
11177 | static bool needs_scaling(struct intel_plane_state *state) |
11178 | { | |
11179 | int src_w = drm_rect_width(&state->src) >> 16; | |
11180 | int src_h = drm_rect_height(&state->src) >> 16; | |
11181 | int dst_w = drm_rect_width(&state->dst); | |
11182 | int dst_h = drm_rect_height(&state->dst); | |
11183 | ||
11184 | return (src_w != dst_w || src_h != dst_h); | |
11185 | } | |
11186 | ||
da20eabd ML |
11187 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
11188 | struct drm_plane_state *plane_state) | |
11189 | { | |
ab1d3a0e | 11190 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
da20eabd ML |
11191 | struct drm_crtc *crtc = crtc_state->crtc; |
11192 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11193 | struct drm_plane *plane = plane_state->plane; | |
11194 | struct drm_device *dev = crtc->dev; | |
ed4a6a7c | 11195 | struct drm_i915_private *dev_priv = to_i915(dev); |
da20eabd ML |
11196 | struct intel_plane_state *old_plane_state = |
11197 | to_intel_plane_state(plane->state); | |
11198 | int idx = intel_crtc->base.base.id, ret; | |
da20eabd ML |
11199 | bool mode_changed = needs_modeset(crtc_state); |
11200 | bool was_crtc_enabled = crtc->state->active; | |
11201 | bool is_crtc_enabled = crtc_state->active; | |
da20eabd ML |
11202 | bool turn_off, turn_on, visible, was_visible; |
11203 | struct drm_framebuffer *fb = plane_state->fb; | |
11204 | ||
11205 | if (crtc_state && INTEL_INFO(dev)->gen >= 9 && | |
11206 | plane->type != DRM_PLANE_TYPE_CURSOR) { | |
11207 | ret = skl_update_scaler_plane( | |
11208 | to_intel_crtc_state(crtc_state), | |
11209 | to_intel_plane_state(plane_state)); | |
11210 | if (ret) | |
11211 | return ret; | |
11212 | } | |
11213 | ||
da20eabd ML |
11214 | was_visible = old_plane_state->visible; |
11215 | visible = to_intel_plane_state(plane_state)->visible; | |
11216 | ||
11217 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
11218 | was_visible = false; | |
11219 | ||
35c08f43 ML |
11220 | /* |
11221 | * Visibility is calculated as if the crtc was on, but | |
11222 | * after scaler setup everything depends on it being off | |
11223 | * when the crtc isn't active. | |
f818ffea VS |
11224 | * |
11225 | * FIXME this is wrong for watermarks. Watermarks should also | |
11226 | * be computed as if the pipe would be active. Perhaps move | |
11227 | * per-plane wm computation to the .check_plane() hook, and | |
11228 | * only combine the results from all planes in the current place? | |
35c08f43 ML |
11229 | */ |
11230 | if (!is_crtc_enabled) | |
11231 | to_intel_plane_state(plane_state)->visible = visible = false; | |
da20eabd ML |
11232 | |
11233 | if (!was_visible && !visible) | |
11234 | return 0; | |
11235 | ||
e8861675 ML |
11236 | if (fb != old_plane_state->base.fb) |
11237 | pipe_config->fb_changed = true; | |
11238 | ||
da20eabd ML |
11239 | turn_off = was_visible && (!visible || mode_changed); |
11240 | turn_on = visible && (!was_visible || mode_changed); | |
11241 | ||
11242 | DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx, | |
11243 | plane->base.id, fb ? fb->base.id : -1); | |
11244 | ||
11245 | DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n", | |
11246 | plane->base.id, was_visible, visible, | |
11247 | turn_off, turn_on, mode_changed); | |
11248 | ||
caed361d VS |
11249 | if (turn_on) { |
11250 | pipe_config->update_wm_pre = true; | |
11251 | ||
11252 | /* must disable cxsr around plane enable/disable */ | |
11253 | if (plane->type != DRM_PLANE_TYPE_CURSOR) | |
11254 | pipe_config->disable_cxsr = true; | |
11255 | } else if (turn_off) { | |
11256 | pipe_config->update_wm_post = true; | |
92826fcd | 11257 | |
852eb00d | 11258 | /* must disable cxsr around plane enable/disable */ |
e8861675 | 11259 | if (plane->type != DRM_PLANE_TYPE_CURSOR) |
ab1d3a0e | 11260 | pipe_config->disable_cxsr = true; |
852eb00d | 11261 | } else if (intel_wm_need_update(plane, plane_state)) { |
caed361d VS |
11262 | /* FIXME bollocks */ |
11263 | pipe_config->update_wm_pre = true; | |
11264 | pipe_config->update_wm_post = true; | |
852eb00d | 11265 | } |
da20eabd | 11266 | |
ed4a6a7c | 11267 | /* Pre-gen9 platforms need two-step watermark updates */ |
caed361d VS |
11268 | if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) && |
11269 | INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks) | |
ed4a6a7c MR |
11270 | to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true; |
11271 | ||
8be6ca85 | 11272 | if (visible || was_visible) |
cd202f69 | 11273 | pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit; |
a9ff8714 | 11274 | |
31ae71fc ML |
11275 | /* |
11276 | * WaCxSRDisabledForSpriteScaling:ivb | |
11277 | * | |
11278 | * cstate->update_wm was already set above, so this flag will | |
11279 | * take effect when we commit and program watermarks. | |
11280 | */ | |
11281 | if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) && | |
11282 | needs_scaling(to_intel_plane_state(plane_state)) && | |
11283 | !needs_scaling(old_plane_state)) | |
11284 | pipe_config->disable_lp_wm = true; | |
d21fbe87 | 11285 | |
da20eabd ML |
11286 | return 0; |
11287 | } | |
11288 | ||
6d3a1ce7 ML |
11289 | static bool encoders_cloneable(const struct intel_encoder *a, |
11290 | const struct intel_encoder *b) | |
11291 | { | |
11292 | /* masks could be asymmetric, so check both ways */ | |
11293 | return a == b || (a->cloneable & (1 << b->type) && | |
11294 | b->cloneable & (1 << a->type)); | |
11295 | } | |
11296 | ||
11297 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
11298 | struct intel_crtc *crtc, | |
11299 | struct intel_encoder *encoder) | |
11300 | { | |
11301 | struct intel_encoder *source_encoder; | |
11302 | struct drm_connector *connector; | |
11303 | struct drm_connector_state *connector_state; | |
11304 | int i; | |
11305 | ||
11306 | for_each_connector_in_state(state, connector, connector_state, i) { | |
11307 | if (connector_state->crtc != &crtc->base) | |
11308 | continue; | |
11309 | ||
11310 | source_encoder = | |
11311 | to_intel_encoder(connector_state->best_encoder); | |
11312 | if (!encoders_cloneable(encoder, source_encoder)) | |
11313 | return false; | |
11314 | } | |
11315 | ||
11316 | return true; | |
11317 | } | |
11318 | ||
11319 | static bool check_encoder_cloning(struct drm_atomic_state *state, | |
11320 | struct intel_crtc *crtc) | |
11321 | { | |
11322 | struct intel_encoder *encoder; | |
11323 | struct drm_connector *connector; | |
11324 | struct drm_connector_state *connector_state; | |
11325 | int i; | |
11326 | ||
11327 | for_each_connector_in_state(state, connector, connector_state, i) { | |
11328 | if (connector_state->crtc != &crtc->base) | |
11329 | continue; | |
11330 | ||
11331 | encoder = to_intel_encoder(connector_state->best_encoder); | |
11332 | if (!check_single_encoder_cloning(state, crtc, encoder)) | |
11333 | return false; | |
11334 | } | |
11335 | ||
11336 | return true; | |
11337 | } | |
11338 | ||
11339 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, | |
11340 | struct drm_crtc_state *crtc_state) | |
11341 | { | |
cf5a15be | 11342 | struct drm_device *dev = crtc->dev; |
ad421372 | 11343 | struct drm_i915_private *dev_priv = dev->dev_private; |
6d3a1ce7 | 11344 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
11345 | struct intel_crtc_state *pipe_config = |
11346 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 11347 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 11348 | int ret; |
6d3a1ce7 ML |
11349 | bool mode_changed = needs_modeset(crtc_state); |
11350 | ||
11351 | if (mode_changed && !check_encoder_cloning(state, intel_crtc)) { | |
11352 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
11353 | return -EINVAL; | |
11354 | } | |
11355 | ||
852eb00d | 11356 | if (mode_changed && !crtc_state->active) |
caed361d | 11357 | pipe_config->update_wm_post = true; |
eddfcbcd | 11358 | |
ad421372 ML |
11359 | if (mode_changed && crtc_state->enable && |
11360 | dev_priv->display.crtc_compute_clock && | |
8106ddbd | 11361 | !WARN_ON(pipe_config->shared_dpll)) { |
ad421372 ML |
11362 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, |
11363 | pipe_config); | |
11364 | if (ret) | |
11365 | return ret; | |
11366 | } | |
11367 | ||
82cf435b LL |
11368 | if (crtc_state->color_mgmt_changed) { |
11369 | ret = intel_color_check(crtc, crtc_state); | |
11370 | if (ret) | |
11371 | return ret; | |
11372 | } | |
11373 | ||
e435d6e5 | 11374 | ret = 0; |
86c8bbbe | 11375 | if (dev_priv->display.compute_pipe_wm) { |
e3bddded | 11376 | ret = dev_priv->display.compute_pipe_wm(pipe_config); |
ed4a6a7c MR |
11377 | if (ret) { |
11378 | DRM_DEBUG_KMS("Target pipe watermarks are invalid\n"); | |
11379 | return ret; | |
11380 | } | |
11381 | } | |
11382 | ||
11383 | if (dev_priv->display.compute_intermediate_wm && | |
11384 | !to_intel_atomic_state(state)->skip_intermediate_wm) { | |
11385 | if (WARN_ON(!dev_priv->display.compute_pipe_wm)) | |
11386 | return 0; | |
11387 | ||
11388 | /* | |
11389 | * Calculate 'intermediate' watermarks that satisfy both the | |
11390 | * old state and the new state. We can program these | |
11391 | * immediately. | |
11392 | */ | |
11393 | ret = dev_priv->display.compute_intermediate_wm(crtc->dev, | |
11394 | intel_crtc, | |
11395 | pipe_config); | |
11396 | if (ret) { | |
11397 | DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n"); | |
86c8bbbe | 11398 | return ret; |
ed4a6a7c | 11399 | } |
e3d5457c VS |
11400 | } else if (dev_priv->display.compute_intermediate_wm) { |
11401 | if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9) | |
11402 | pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal; | |
86c8bbbe MR |
11403 | } |
11404 | ||
e435d6e5 ML |
11405 | if (INTEL_INFO(dev)->gen >= 9) { |
11406 | if (mode_changed) | |
11407 | ret = skl_update_scaler_crtc(pipe_config); | |
11408 | ||
11409 | if (!ret) | |
11410 | ret = intel_atomic_setup_scalers(dev, intel_crtc, | |
11411 | pipe_config); | |
11412 | } | |
11413 | ||
11414 | return ret; | |
6d3a1ce7 ML |
11415 | } |
11416 | ||
65b38e0d | 11417 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 | 11418 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
6d3a1ce7 | 11419 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
11420 | }; |
11421 | ||
d29b2f9d ACO |
11422 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
11423 | { | |
11424 | struct intel_connector *connector; | |
11425 | ||
11426 | for_each_intel_connector(dev, connector) { | |
8863dc7f DV |
11427 | if (connector->base.state->crtc) |
11428 | drm_connector_unreference(&connector->base); | |
11429 | ||
d29b2f9d ACO |
11430 | if (connector->base.encoder) { |
11431 | connector->base.state->best_encoder = | |
11432 | connector->base.encoder; | |
11433 | connector->base.state->crtc = | |
11434 | connector->base.encoder->crtc; | |
8863dc7f DV |
11435 | |
11436 | drm_connector_reference(&connector->base); | |
d29b2f9d ACO |
11437 | } else { |
11438 | connector->base.state->best_encoder = NULL; | |
11439 | connector->base.state->crtc = NULL; | |
11440 | } | |
11441 | } | |
11442 | } | |
11443 | ||
050f7aeb | 11444 | static void |
eba905b2 | 11445 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 11446 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
11447 | { |
11448 | int bpp = pipe_config->pipe_bpp; | |
11449 | ||
11450 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
11451 | connector->base.base.id, | |
c23cc417 | 11452 | connector->base.name); |
050f7aeb DV |
11453 | |
11454 | /* Don't use an invalid EDID bpc value */ | |
11455 | if (connector->base.display_info.bpc && | |
11456 | connector->base.display_info.bpc * 3 < bpp) { | |
11457 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
11458 | bpp, connector->base.display_info.bpc*3); | |
11459 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
11460 | } | |
11461 | ||
013dd9e0 JN |
11462 | /* Clamp bpp to default limit on screens without EDID 1.4 */ |
11463 | if (connector->base.display_info.bpc == 0) { | |
11464 | int type = connector->base.connector_type; | |
11465 | int clamp_bpp = 24; | |
11466 | ||
11467 | /* Fall back to 18 bpp when DP sink capability is unknown. */ | |
11468 | if (type == DRM_MODE_CONNECTOR_DisplayPort || | |
11469 | type == DRM_MODE_CONNECTOR_eDP) | |
11470 | clamp_bpp = 18; | |
11471 | ||
11472 | if (bpp > clamp_bpp) { | |
11473 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n", | |
11474 | bpp, clamp_bpp); | |
11475 | pipe_config->pipe_bpp = clamp_bpp; | |
11476 | } | |
050f7aeb DV |
11477 | } |
11478 | } | |
11479 | ||
4e53c2e0 | 11480 | static int |
050f7aeb | 11481 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 11482 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 11483 | { |
050f7aeb | 11484 | struct drm_device *dev = crtc->base.dev; |
1486017f | 11485 | struct drm_atomic_state *state; |
da3ced29 ACO |
11486 | struct drm_connector *connector; |
11487 | struct drm_connector_state *connector_state; | |
1486017f | 11488 | int bpp, i; |
4e53c2e0 | 11489 | |
666a4537 | 11490 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) |
4e53c2e0 | 11491 | bpp = 10*3; |
d328c9d7 DV |
11492 | else if (INTEL_INFO(dev)->gen >= 5) |
11493 | bpp = 12*3; | |
11494 | else | |
11495 | bpp = 8*3; | |
11496 | ||
4e53c2e0 | 11497 | |
4e53c2e0 DV |
11498 | pipe_config->pipe_bpp = bpp; |
11499 | ||
1486017f ACO |
11500 | state = pipe_config->base.state; |
11501 | ||
4e53c2e0 | 11502 | /* Clamp display bpp to EDID value */ |
da3ced29 ACO |
11503 | for_each_connector_in_state(state, connector, connector_state, i) { |
11504 | if (connector_state->crtc != &crtc->base) | |
4e53c2e0 DV |
11505 | continue; |
11506 | ||
da3ced29 ACO |
11507 | connected_sink_compute_bpp(to_intel_connector(connector), |
11508 | pipe_config); | |
4e53c2e0 DV |
11509 | } |
11510 | ||
11511 | return bpp; | |
11512 | } | |
11513 | ||
644db711 DV |
11514 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
11515 | { | |
11516 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
11517 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 11518 | mode->crtc_clock, |
644db711 DV |
11519 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
11520 | mode->crtc_hsync_end, mode->crtc_htotal, | |
11521 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
11522 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
11523 | } | |
11524 | ||
c0b03411 | 11525 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 11526 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
11527 | const char *context) |
11528 | { | |
6a60cd87 CK |
11529 | struct drm_device *dev = crtc->base.dev; |
11530 | struct drm_plane *plane; | |
11531 | struct intel_plane *intel_plane; | |
11532 | struct intel_plane_state *state; | |
11533 | struct drm_framebuffer *fb; | |
11534 | ||
11535 | DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id, | |
11536 | context, pipe_config, pipe_name(crtc->pipe)); | |
c0b03411 | 11537 | |
da205630 | 11538 | DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder)); |
c0b03411 DV |
11539 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", |
11540 | pipe_config->pipe_bpp, pipe_config->dither); | |
11541 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
11542 | pipe_config->has_pch_encoder, | |
11543 | pipe_config->fdi_lanes, | |
11544 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
11545 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
11546 | pipe_config->fdi_m_n.tu); | |
90a6b7b0 | 11547 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
eb14cb74 | 11548 | pipe_config->has_dp_encoder, |
90a6b7b0 | 11549 | pipe_config->lane_count, |
eb14cb74 VS |
11550 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, |
11551 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
11552 | pipe_config->dp_m_n.tu); | |
b95af8be | 11553 | |
90a6b7b0 | 11554 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", |
b95af8be | 11555 | pipe_config->has_dp_encoder, |
90a6b7b0 | 11556 | pipe_config->lane_count, |
b95af8be VK |
11557 | pipe_config->dp_m2_n2.gmch_m, |
11558 | pipe_config->dp_m2_n2.gmch_n, | |
11559 | pipe_config->dp_m2_n2.link_m, | |
11560 | pipe_config->dp_m2_n2.link_n, | |
11561 | pipe_config->dp_m2_n2.tu); | |
11562 | ||
55072d19 DV |
11563 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
11564 | pipe_config->has_audio, | |
11565 | pipe_config->has_infoframe); | |
11566 | ||
c0b03411 | 11567 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 11568 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 11569 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
11570 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
11571 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 11572 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
11573 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
11574 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
0ec463d3 TU |
11575 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", |
11576 | crtc->num_scalers, | |
11577 | pipe_config->scaler_state.scaler_users, | |
11578 | pipe_config->scaler_state.scaler_id); | |
c0b03411 DV |
11579 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
11580 | pipe_config->gmch_pfit.control, | |
11581 | pipe_config->gmch_pfit.pgm_ratios, | |
11582 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 11583 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 11584 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
11585 | pipe_config->pch_pfit.size, |
11586 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 11587 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 11588 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
6a60cd87 | 11589 | |
415ff0f6 | 11590 | if (IS_BROXTON(dev)) { |
05712c15 | 11591 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," |
415ff0f6 | 11592 | "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " |
c8453338 | 11593 | "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", |
415ff0f6 TU |
11594 | pipe_config->ddi_pll_sel, |
11595 | pipe_config->dpll_hw_state.ebb0, | |
05712c15 | 11596 | pipe_config->dpll_hw_state.ebb4, |
415ff0f6 TU |
11597 | pipe_config->dpll_hw_state.pll0, |
11598 | pipe_config->dpll_hw_state.pll1, | |
11599 | pipe_config->dpll_hw_state.pll2, | |
11600 | pipe_config->dpll_hw_state.pll3, | |
11601 | pipe_config->dpll_hw_state.pll6, | |
11602 | pipe_config->dpll_hw_state.pll8, | |
05712c15 | 11603 | pipe_config->dpll_hw_state.pll9, |
c8453338 | 11604 | pipe_config->dpll_hw_state.pll10, |
415ff0f6 | 11605 | pipe_config->dpll_hw_state.pcsdw12); |
ef11bdb3 | 11606 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
415ff0f6 TU |
11607 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " |
11608 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", | |
11609 | pipe_config->ddi_pll_sel, | |
11610 | pipe_config->dpll_hw_state.ctrl1, | |
11611 | pipe_config->dpll_hw_state.cfgcr1, | |
11612 | pipe_config->dpll_hw_state.cfgcr2); | |
11613 | } else if (HAS_DDI(dev)) { | |
1260f07e | 11614 | DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", |
415ff0f6 | 11615 | pipe_config->ddi_pll_sel, |
00490c22 ML |
11616 | pipe_config->dpll_hw_state.wrpll, |
11617 | pipe_config->dpll_hw_state.spll); | |
415ff0f6 TU |
11618 | } else { |
11619 | DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " | |
11620 | "fp0: 0x%x, fp1: 0x%x\n", | |
11621 | pipe_config->dpll_hw_state.dpll, | |
11622 | pipe_config->dpll_hw_state.dpll_md, | |
11623 | pipe_config->dpll_hw_state.fp0, | |
11624 | pipe_config->dpll_hw_state.fp1); | |
11625 | } | |
11626 | ||
6a60cd87 CK |
11627 | DRM_DEBUG_KMS("planes on this crtc\n"); |
11628 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
11629 | intel_plane = to_intel_plane(plane); | |
11630 | if (intel_plane->pipe != crtc->pipe) | |
11631 | continue; | |
11632 | ||
11633 | state = to_intel_plane_state(plane->state); | |
11634 | fb = state->base.fb; | |
11635 | if (!fb) { | |
11636 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d " | |
11637 | "disabled, scaler_id = %d\n", | |
11638 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
11639 | plane->base.id, intel_plane->pipe, | |
11640 | (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1, | |
11641 | drm_plane_index(plane), state->scaler_id); | |
11642 | continue; | |
11643 | } | |
11644 | ||
11645 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled", | |
11646 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
11647 | plane->base.id, intel_plane->pipe, | |
11648 | crtc->base.primary == plane ? 0 : intel_plane->plane + 1, | |
11649 | drm_plane_index(plane)); | |
11650 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x", | |
11651 | fb->base.id, fb->width, fb->height, fb->pixel_format); | |
11652 | DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n", | |
11653 | state->scaler_id, | |
11654 | state->src.x1 >> 16, state->src.y1 >> 16, | |
11655 | drm_rect_width(&state->src) >> 16, | |
11656 | drm_rect_height(&state->src) >> 16, | |
11657 | state->dst.x1, state->dst.y1, | |
11658 | drm_rect_width(&state->dst), drm_rect_height(&state->dst)); | |
11659 | } | |
c0b03411 DV |
11660 | } |
11661 | ||
5448a00d | 11662 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 11663 | { |
5448a00d | 11664 | struct drm_device *dev = state->dev; |
da3ced29 | 11665 | struct drm_connector *connector; |
00f0b378 VS |
11666 | unsigned int used_ports = 0; |
11667 | ||
11668 | /* | |
11669 | * Walk the connector list instead of the encoder | |
11670 | * list to detect the problem on ddi platforms | |
11671 | * where there's just one encoder per digital port. | |
11672 | */ | |
0bff4858 VS |
11673 | drm_for_each_connector(connector, dev) { |
11674 | struct drm_connector_state *connector_state; | |
11675 | struct intel_encoder *encoder; | |
11676 | ||
11677 | connector_state = drm_atomic_get_existing_connector_state(state, connector); | |
11678 | if (!connector_state) | |
11679 | connector_state = connector->state; | |
11680 | ||
5448a00d | 11681 | if (!connector_state->best_encoder) |
00f0b378 VS |
11682 | continue; |
11683 | ||
5448a00d ACO |
11684 | encoder = to_intel_encoder(connector_state->best_encoder); |
11685 | ||
11686 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
11687 | |
11688 | switch (encoder->type) { | |
11689 | unsigned int port_mask; | |
11690 | case INTEL_OUTPUT_UNKNOWN: | |
11691 | if (WARN_ON(!HAS_DDI(dev))) | |
11692 | break; | |
11693 | case INTEL_OUTPUT_DISPLAYPORT: | |
11694 | case INTEL_OUTPUT_HDMI: | |
11695 | case INTEL_OUTPUT_EDP: | |
11696 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
11697 | ||
11698 | /* the same port mustn't appear more than once */ | |
11699 | if (used_ports & port_mask) | |
11700 | return false; | |
11701 | ||
11702 | used_ports |= port_mask; | |
11703 | default: | |
11704 | break; | |
11705 | } | |
11706 | } | |
11707 | ||
11708 | return true; | |
11709 | } | |
11710 | ||
83a57153 ACO |
11711 | static void |
11712 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
11713 | { | |
11714 | struct drm_crtc_state tmp_state; | |
663a3640 | 11715 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 | 11716 | struct intel_dpll_hw_state dpll_hw_state; |
8106ddbd | 11717 | struct intel_shared_dpll *shared_dpll; |
8504c74c | 11718 | uint32_t ddi_pll_sel; |
c4e2d043 | 11719 | bool force_thru; |
83a57153 | 11720 | |
7546a384 ACO |
11721 | /* FIXME: before the switch to atomic started, a new pipe_config was |
11722 | * kzalloc'd. Code that depends on any field being zero should be | |
11723 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
11724 | * only fields that are know to not cause problems are preserved. */ | |
11725 | ||
83a57153 | 11726 | tmp_state = crtc_state->base; |
663a3640 | 11727 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
11728 | shared_dpll = crtc_state->shared_dpll; |
11729 | dpll_hw_state = crtc_state->dpll_hw_state; | |
8504c74c | 11730 | ddi_pll_sel = crtc_state->ddi_pll_sel; |
c4e2d043 | 11731 | force_thru = crtc_state->pch_pfit.force_thru; |
4978cc93 | 11732 | |
83a57153 | 11733 | memset(crtc_state, 0, sizeof *crtc_state); |
4978cc93 | 11734 | |
83a57153 | 11735 | crtc_state->base = tmp_state; |
663a3640 | 11736 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
11737 | crtc_state->shared_dpll = shared_dpll; |
11738 | crtc_state->dpll_hw_state = dpll_hw_state; | |
8504c74c | 11739 | crtc_state->ddi_pll_sel = ddi_pll_sel; |
c4e2d043 | 11740 | crtc_state->pch_pfit.force_thru = force_thru; |
83a57153 ACO |
11741 | } |
11742 | ||
548ee15b | 11743 | static int |
b8cecdf5 | 11744 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 11745 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 11746 | { |
b359283a | 11747 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 11748 | struct intel_encoder *encoder; |
da3ced29 | 11749 | struct drm_connector *connector; |
0b901879 | 11750 | struct drm_connector_state *connector_state; |
d328c9d7 | 11751 | int base_bpp, ret = -EINVAL; |
0b901879 | 11752 | int i; |
e29c22c0 | 11753 | bool retry = true; |
ee7b9f93 | 11754 | |
83a57153 | 11755 | clear_intel_crtc_state(pipe_config); |
7758a113 | 11756 | |
e143a21c DV |
11757 | pipe_config->cpu_transcoder = |
11758 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 11759 | |
2960bc9c ID |
11760 | /* |
11761 | * Sanitize sync polarity flags based on requested ones. If neither | |
11762 | * positive or negative polarity is requested, treat this as meaning | |
11763 | * negative polarity. | |
11764 | */ | |
2d112de7 | 11765 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 11766 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 11767 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 11768 | |
2d112de7 | 11769 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 11770 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 11771 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 11772 | |
d328c9d7 DV |
11773 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
11774 | pipe_config); | |
11775 | if (base_bpp < 0) | |
4e53c2e0 DV |
11776 | goto fail; |
11777 | ||
e41a56be VS |
11778 | /* |
11779 | * Determine the real pipe dimensions. Note that stereo modes can | |
11780 | * increase the actual pipe size due to the frame doubling and | |
11781 | * insertion of additional space for blanks between the frame. This | |
11782 | * is stored in the crtc timings. We use the requested mode to do this | |
11783 | * computation to clearly distinguish it from the adjusted mode, which | |
11784 | * can be changed by the connectors in the below retry loop. | |
11785 | */ | |
2d112de7 | 11786 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
11787 | &pipe_config->pipe_src_w, |
11788 | &pipe_config->pipe_src_h); | |
e41a56be | 11789 | |
e29c22c0 | 11790 | encoder_retry: |
ef1b460d | 11791 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 11792 | pipe_config->port_clock = 0; |
ef1b460d | 11793 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 11794 | |
135c81b8 | 11795 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
11796 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
11797 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 11798 | |
7758a113 DV |
11799 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
11800 | * adjust it according to limitations or connector properties, and also | |
11801 | * a chance to reject the mode entirely. | |
47f1c6c9 | 11802 | */ |
da3ced29 | 11803 | for_each_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 11804 | if (connector_state->crtc != crtc) |
7758a113 | 11805 | continue; |
7ae89233 | 11806 | |
0b901879 ACO |
11807 | encoder = to_intel_encoder(connector_state->best_encoder); |
11808 | ||
efea6e8e DV |
11809 | if (!(encoder->compute_config(encoder, pipe_config))) { |
11810 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
11811 | goto fail; |
11812 | } | |
ee7b9f93 | 11813 | } |
47f1c6c9 | 11814 | |
ff9a6750 DV |
11815 | /* Set default port clock if not overwritten by the encoder. Needs to be |
11816 | * done afterwards in case the encoder adjusts the mode. */ | |
11817 | if (!pipe_config->port_clock) | |
2d112de7 | 11818 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 11819 | * pipe_config->pixel_multiplier; |
ff9a6750 | 11820 | |
a43f6e0f | 11821 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 11822 | if (ret < 0) { |
7758a113 DV |
11823 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
11824 | goto fail; | |
ee7b9f93 | 11825 | } |
e29c22c0 DV |
11826 | |
11827 | if (ret == RETRY) { | |
11828 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
11829 | ret = -EINVAL; | |
11830 | goto fail; | |
11831 | } | |
11832 | ||
11833 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
11834 | retry = false; | |
11835 | goto encoder_retry; | |
11836 | } | |
11837 | ||
e8fa4270 DV |
11838 | /* Dithering seems to not pass-through bits correctly when it should, so |
11839 | * only enable it on 6bpc panels. */ | |
11840 | pipe_config->dither = pipe_config->pipe_bpp == 6*3; | |
62f0ace5 | 11841 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 11842 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 11843 | |
7758a113 | 11844 | fail: |
548ee15b | 11845 | return ret; |
ee7b9f93 | 11846 | } |
47f1c6c9 | 11847 | |
ea9d758d | 11848 | static void |
4740b0f2 | 11849 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 11850 | { |
0a9ab303 ACO |
11851 | struct drm_crtc *crtc; |
11852 | struct drm_crtc_state *crtc_state; | |
8a75d157 | 11853 | int i; |
ea9d758d | 11854 | |
7668851f | 11855 | /* Double check state. */ |
8a75d157 | 11856 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
3cb480bc | 11857 | to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); |
fc467a22 ML |
11858 | |
11859 | /* Update hwmode for vblank functions */ | |
11860 | if (crtc->state->active) | |
11861 | crtc->hwmode = crtc->state->adjusted_mode; | |
11862 | else | |
11863 | crtc->hwmode.crtc_clock = 0; | |
61067a5e ML |
11864 | |
11865 | /* | |
11866 | * Update legacy state to satisfy fbc code. This can | |
11867 | * be removed when fbc uses the atomic state. | |
11868 | */ | |
11869 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
11870 | struct drm_plane_state *plane_state = crtc->primary->state; | |
11871 | ||
11872 | crtc->primary->fb = plane_state->fb; | |
11873 | crtc->x = plane_state->src_x >> 16; | |
11874 | crtc->y = plane_state->src_y >> 16; | |
11875 | } | |
ea9d758d | 11876 | } |
ea9d758d DV |
11877 | } |
11878 | ||
3bd26263 | 11879 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 11880 | { |
3bd26263 | 11881 | int diff; |
f1f644dc JB |
11882 | |
11883 | if (clock1 == clock2) | |
11884 | return true; | |
11885 | ||
11886 | if (!clock1 || !clock2) | |
11887 | return false; | |
11888 | ||
11889 | diff = abs(clock1 - clock2); | |
11890 | ||
11891 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
11892 | return true; | |
11893 | ||
11894 | return false; | |
11895 | } | |
11896 | ||
25c5b266 DV |
11897 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
11898 | list_for_each_entry((intel_crtc), \ | |
11899 | &(dev)->mode_config.crtc_list, \ | |
11900 | base.head) \ | |
95150bdf | 11901 | for_each_if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 11902 | |
cfb23ed6 ML |
11903 | static bool |
11904 | intel_compare_m_n(unsigned int m, unsigned int n, | |
11905 | unsigned int m2, unsigned int n2, | |
11906 | bool exact) | |
11907 | { | |
11908 | if (m == m2 && n == n2) | |
11909 | return true; | |
11910 | ||
11911 | if (exact || !m || !n || !m2 || !n2) | |
11912 | return false; | |
11913 | ||
11914 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
11915 | ||
31d10b57 ML |
11916 | if (n > n2) { |
11917 | while (n > n2) { | |
cfb23ed6 ML |
11918 | m2 <<= 1; |
11919 | n2 <<= 1; | |
11920 | } | |
31d10b57 ML |
11921 | } else if (n < n2) { |
11922 | while (n < n2) { | |
cfb23ed6 ML |
11923 | m <<= 1; |
11924 | n <<= 1; | |
11925 | } | |
11926 | } | |
11927 | ||
31d10b57 ML |
11928 | if (n != n2) |
11929 | return false; | |
11930 | ||
11931 | return intel_fuzzy_clock_check(m, m2); | |
cfb23ed6 ML |
11932 | } |
11933 | ||
11934 | static bool | |
11935 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
11936 | struct intel_link_m_n *m2_n2, | |
11937 | bool adjust) | |
11938 | { | |
11939 | if (m_n->tu == m2_n2->tu && | |
11940 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
11941 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
11942 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
11943 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
11944 | if (adjust) | |
11945 | *m2_n2 = *m_n; | |
11946 | ||
11947 | return true; | |
11948 | } | |
11949 | ||
11950 | return false; | |
11951 | } | |
11952 | ||
0e8ffe1b | 11953 | static bool |
2fa2fe9a | 11954 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b | 11955 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
11956 | struct intel_crtc_state *pipe_config, |
11957 | bool adjust) | |
0e8ffe1b | 11958 | { |
cfb23ed6 ML |
11959 | bool ret = true; |
11960 | ||
11961 | #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \ | |
11962 | do { \ | |
11963 | if (!adjust) \ | |
11964 | DRM_ERROR(fmt, ##__VA_ARGS__); \ | |
11965 | else \ | |
11966 | DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \ | |
11967 | } while (0) | |
11968 | ||
66e985c0 DV |
11969 | #define PIPE_CONF_CHECK_X(name) \ |
11970 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 11971 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
66e985c0 DV |
11972 | "(expected 0x%08x, found 0x%08x)\n", \ |
11973 | current_config->name, \ | |
11974 | pipe_config->name); \ | |
cfb23ed6 | 11975 | ret = false; \ |
66e985c0 DV |
11976 | } |
11977 | ||
08a24034 DV |
11978 | #define PIPE_CONF_CHECK_I(name) \ |
11979 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 11980 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
08a24034 DV |
11981 | "(expected %i, found %i)\n", \ |
11982 | current_config->name, \ | |
11983 | pipe_config->name); \ | |
cfb23ed6 ML |
11984 | ret = false; \ |
11985 | } | |
11986 | ||
8106ddbd ACO |
11987 | #define PIPE_CONF_CHECK_P(name) \ |
11988 | if (current_config->name != pipe_config->name) { \ | |
11989 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
11990 | "(expected %p, found %p)\n", \ | |
11991 | current_config->name, \ | |
11992 | pipe_config->name); \ | |
11993 | ret = false; \ | |
11994 | } | |
11995 | ||
cfb23ed6 ML |
11996 | #define PIPE_CONF_CHECK_M_N(name) \ |
11997 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
11998 | &pipe_config->name,\ | |
11999 | adjust)) { \ | |
12000 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12001 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12002 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12003 | current_config->name.tu, \ | |
12004 | current_config->name.gmch_m, \ | |
12005 | current_config->name.gmch_n, \ | |
12006 | current_config->name.link_m, \ | |
12007 | current_config->name.link_n, \ | |
12008 | pipe_config->name.tu, \ | |
12009 | pipe_config->name.gmch_m, \ | |
12010 | pipe_config->name.gmch_n, \ | |
12011 | pipe_config->name.link_m, \ | |
12012 | pipe_config->name.link_n); \ | |
12013 | ret = false; \ | |
12014 | } | |
12015 | ||
55c561a7 DV |
12016 | /* This is required for BDW+ where there is only one set of registers for |
12017 | * switching between high and low RR. | |
12018 | * This macro can be used whenever a comparison has to be made between one | |
12019 | * hw state and multiple sw state variables. | |
12020 | */ | |
cfb23ed6 ML |
12021 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ |
12022 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12023 | &pipe_config->name, adjust) && \ | |
12024 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
12025 | &pipe_config->name, adjust)) { \ | |
12026 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12027 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12028 | "or tu %i gmch %i/%i link %i/%i, " \ | |
12029 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12030 | current_config->name.tu, \ | |
12031 | current_config->name.gmch_m, \ | |
12032 | current_config->name.gmch_n, \ | |
12033 | current_config->name.link_m, \ | |
12034 | current_config->name.link_n, \ | |
12035 | current_config->alt_name.tu, \ | |
12036 | current_config->alt_name.gmch_m, \ | |
12037 | current_config->alt_name.gmch_n, \ | |
12038 | current_config->alt_name.link_m, \ | |
12039 | current_config->alt_name.link_n, \ | |
12040 | pipe_config->name.tu, \ | |
12041 | pipe_config->name.gmch_m, \ | |
12042 | pipe_config->name.gmch_n, \ | |
12043 | pipe_config->name.link_m, \ | |
12044 | pipe_config->name.link_n); \ | |
12045 | ret = false; \ | |
88adfff1 DV |
12046 | } |
12047 | ||
1bd1bd80 DV |
12048 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
12049 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
cfb23ed6 | 12050 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
12051 | "(expected %i, found %i)\n", \ |
12052 | current_config->name & (mask), \ | |
12053 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 12054 | ret = false; \ |
1bd1bd80 DV |
12055 | } |
12056 | ||
5e550656 VS |
12057 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
12058 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
cfb23ed6 | 12059 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
5e550656 VS |
12060 | "(expected %i, found %i)\n", \ |
12061 | current_config->name, \ | |
12062 | pipe_config->name); \ | |
cfb23ed6 | 12063 | ret = false; \ |
5e550656 VS |
12064 | } |
12065 | ||
bb760063 DV |
12066 | #define PIPE_CONF_QUIRK(quirk) \ |
12067 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
12068 | ||
eccb140b DV |
12069 | PIPE_CONF_CHECK_I(cpu_transcoder); |
12070 | ||
08a24034 DV |
12071 | PIPE_CONF_CHECK_I(has_pch_encoder); |
12072 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 12073 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 12074 | |
eb14cb74 | 12075 | PIPE_CONF_CHECK_I(has_dp_encoder); |
90a6b7b0 | 12076 | PIPE_CONF_CHECK_I(lane_count); |
b95af8be VK |
12077 | |
12078 | if (INTEL_INFO(dev)->gen < 8) { | |
cfb23ed6 ML |
12079 | PIPE_CONF_CHECK_M_N(dp_m_n); |
12080 | ||
cfb23ed6 ML |
12081 | if (current_config->has_drrs) |
12082 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
12083 | } else | |
12084 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 12085 | |
a65347ba JN |
12086 | PIPE_CONF_CHECK_I(has_dsi_encoder); |
12087 | ||
2d112de7 ACO |
12088 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
12089 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
12090 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
12091 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
12092 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
12093 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 12094 | |
2d112de7 ACO |
12095 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
12096 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
12097 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
12098 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
12099 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
12100 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 12101 | |
c93f54cf | 12102 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 12103 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 | 12104 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
666a4537 | 12105 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
b5a9fa09 | 12106 | PIPE_CONF_CHECK_I(limited_color_range); |
e43823ec | 12107 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 12108 | |
9ed109a7 DV |
12109 | PIPE_CONF_CHECK_I(has_audio); |
12110 | ||
2d112de7 | 12111 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
12112 | DRM_MODE_FLAG_INTERLACE); |
12113 | ||
bb760063 | 12114 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 12115 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12116 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 12117 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12118 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 12119 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12120 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 12121 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
12122 | DRM_MODE_FLAG_NVSYNC); |
12123 | } | |
045ac3b5 | 12124 | |
333b8ca8 | 12125 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a DV |
12126 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
12127 | if (INTEL_INFO(dev)->gen < 4) | |
7f7d8dd6 | 12128 | PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); |
333b8ca8 | 12129 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 12130 | |
bfd16b2a ML |
12131 | if (!adjust) { |
12132 | PIPE_CONF_CHECK_I(pipe_src_w); | |
12133 | PIPE_CONF_CHECK_I(pipe_src_h); | |
12134 | ||
12135 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
12136 | if (current_config->pch_pfit.enabled) { | |
12137 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
12138 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
12139 | } | |
2fa2fe9a | 12140 | |
7aefe2b5 ML |
12141 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
12142 | } | |
a1b2278e | 12143 | |
e59150dc JB |
12144 | /* BDW+ don't expose a synchronous way to read the state */ |
12145 | if (IS_HASWELL(dev)) | |
12146 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 12147 | |
282740f7 VS |
12148 | PIPE_CONF_CHECK_I(double_wide); |
12149 | ||
26804afd DV |
12150 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
12151 | ||
8106ddbd | 12152 | PIPE_CONF_CHECK_P(shared_dpll); |
66e985c0 | 12153 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 12154 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
12155 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
12156 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 12157 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
00490c22 | 12158 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
3f4cd19f DL |
12159 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
12160 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
12161 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 12162 | |
47eacbab VS |
12163 | PIPE_CONF_CHECK_X(dsi_pll.ctrl); |
12164 | PIPE_CONF_CHECK_X(dsi_pll.div); | |
12165 | ||
42571aef VS |
12166 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
12167 | PIPE_CONF_CHECK_I(pipe_bpp); | |
12168 | ||
2d112de7 | 12169 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 12170 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 12171 | |
66e985c0 | 12172 | #undef PIPE_CONF_CHECK_X |
08a24034 | 12173 | #undef PIPE_CONF_CHECK_I |
8106ddbd | 12174 | #undef PIPE_CONF_CHECK_P |
1bd1bd80 | 12175 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 12176 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 12177 | #undef PIPE_CONF_QUIRK |
cfb23ed6 | 12178 | #undef INTEL_ERR_OR_DBG_KMS |
88adfff1 | 12179 | |
cfb23ed6 | 12180 | return ret; |
0e8ffe1b DV |
12181 | } |
12182 | ||
e3b247da VS |
12183 | static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, |
12184 | const struct intel_crtc_state *pipe_config) | |
12185 | { | |
12186 | if (pipe_config->has_pch_encoder) { | |
21a727b3 | 12187 | int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
e3b247da VS |
12188 | &pipe_config->fdi_m_n); |
12189 | int dotclock = pipe_config->base.adjusted_mode.crtc_clock; | |
12190 | ||
12191 | /* | |
12192 | * FDI already provided one idea for the dotclock. | |
12193 | * Yell if the encoder disagrees. | |
12194 | */ | |
12195 | WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock), | |
12196 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", | |
12197 | fdi_dotclock, dotclock); | |
12198 | } | |
12199 | } | |
12200 | ||
c0ead703 ML |
12201 | static void verify_wm_state(struct drm_crtc *crtc, |
12202 | struct drm_crtc_state *new_state) | |
08db6652 | 12203 | { |
e7c84544 | 12204 | struct drm_device *dev = crtc->dev; |
08db6652 DL |
12205 | struct drm_i915_private *dev_priv = dev->dev_private; |
12206 | struct skl_ddb_allocation hw_ddb, *sw_ddb; | |
e7c84544 ML |
12207 | struct skl_ddb_entry *hw_entry, *sw_entry; |
12208 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12209 | const enum pipe pipe = intel_crtc->pipe; | |
08db6652 DL |
12210 | int plane; |
12211 | ||
e7c84544 | 12212 | if (INTEL_INFO(dev)->gen < 9 || !new_state->active) |
08db6652 DL |
12213 | return; |
12214 | ||
12215 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
12216 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
12217 | ||
e7c84544 ML |
12218 | /* planes */ |
12219 | for_each_plane(dev_priv, pipe, plane) { | |
12220 | hw_entry = &hw_ddb.plane[pipe][plane]; | |
12221 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
08db6652 | 12222 | |
e7c84544 | 12223 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) |
08db6652 DL |
12224 | continue; |
12225 | ||
e7c84544 ML |
12226 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " |
12227 | "(expected (%u,%u), found (%u,%u))\n", | |
12228 | pipe_name(pipe), plane + 1, | |
12229 | sw_entry->start, sw_entry->end, | |
12230 | hw_entry->start, hw_entry->end); | |
12231 | } | |
08db6652 | 12232 | |
e7c84544 ML |
12233 | /* cursor */ |
12234 | hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; | |
12235 | sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; | |
08db6652 | 12236 | |
e7c84544 | 12237 | if (!skl_ddb_entry_equal(hw_entry, sw_entry)) { |
08db6652 DL |
12238 | DRM_ERROR("mismatch in DDB state pipe %c cursor " |
12239 | "(expected (%u,%u), found (%u,%u))\n", | |
12240 | pipe_name(pipe), | |
12241 | sw_entry->start, sw_entry->end, | |
12242 | hw_entry->start, hw_entry->end); | |
12243 | } | |
12244 | } | |
12245 | ||
91d1b4bd | 12246 | static void |
c0ead703 | 12247 | verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc) |
8af6cf88 | 12248 | { |
35dd3c64 | 12249 | struct drm_connector *connector; |
8af6cf88 | 12250 | |
e7c84544 | 12251 | drm_for_each_connector(connector, dev) { |
35dd3c64 ML |
12252 | struct drm_encoder *encoder = connector->encoder; |
12253 | struct drm_connector_state *state = connector->state; | |
ad3c558f | 12254 | |
e7c84544 ML |
12255 | if (state->crtc != crtc) |
12256 | continue; | |
12257 | ||
03f476e1 ML |
12258 | intel_connector_verify_state(to_intel_connector(connector), |
12259 | connector->state); | |
8af6cf88 | 12260 | |
ad3c558f | 12261 | I915_STATE_WARN(state->best_encoder != encoder, |
35dd3c64 | 12262 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 12263 | } |
91d1b4bd DV |
12264 | } |
12265 | ||
12266 | static void | |
c0ead703 | 12267 | verify_encoder_state(struct drm_device *dev) |
91d1b4bd DV |
12268 | { |
12269 | struct intel_encoder *encoder; | |
12270 | struct intel_connector *connector; | |
8af6cf88 | 12271 | |
b2784e15 | 12272 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 | 12273 | bool enabled = false; |
4d20cd86 | 12274 | enum pipe pipe; |
8af6cf88 DV |
12275 | |
12276 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
12277 | encoder->base.base.id, | |
8e329a03 | 12278 | encoder->base.name); |
8af6cf88 | 12279 | |
3a3371ff | 12280 | for_each_intel_connector(dev, connector) { |
4d20cd86 | 12281 | if (connector->base.state->best_encoder != &encoder->base) |
8af6cf88 DV |
12282 | continue; |
12283 | enabled = true; | |
ad3c558f ML |
12284 | |
12285 | I915_STATE_WARN(connector->base.state->crtc != | |
12286 | encoder->base.crtc, | |
12287 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 12288 | } |
0e32b39c | 12289 | |
e2c719b7 | 12290 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
12291 | "encoder's enabled state mismatch " |
12292 | "(expected %i, found %i)\n", | |
12293 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
12294 | |
12295 | if (!encoder->base.crtc) { | |
4d20cd86 | 12296 | bool active; |
7c60d198 | 12297 | |
4d20cd86 ML |
12298 | active = encoder->get_hw_state(encoder, &pipe); |
12299 | I915_STATE_WARN(active, | |
12300 | "encoder detached but still enabled on pipe %c.\n", | |
12301 | pipe_name(pipe)); | |
7c60d198 | 12302 | } |
8af6cf88 | 12303 | } |
91d1b4bd DV |
12304 | } |
12305 | ||
12306 | static void | |
c0ead703 ML |
12307 | verify_crtc_state(struct drm_crtc *crtc, |
12308 | struct drm_crtc_state *old_crtc_state, | |
12309 | struct drm_crtc_state *new_crtc_state) | |
91d1b4bd | 12310 | { |
e7c84544 | 12311 | struct drm_device *dev = crtc->dev; |
fbee40df | 12312 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd | 12313 | struct intel_encoder *encoder; |
e7c84544 ML |
12314 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
12315 | struct intel_crtc_state *pipe_config, *sw_config; | |
12316 | struct drm_atomic_state *old_state; | |
12317 | bool active; | |
045ac3b5 | 12318 | |
e7c84544 ML |
12319 | old_state = old_crtc_state->state; |
12320 | __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state); | |
12321 | pipe_config = to_intel_crtc_state(old_crtc_state); | |
12322 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
12323 | pipe_config->base.crtc = crtc; | |
12324 | pipe_config->base.state = old_state; | |
8af6cf88 | 12325 | |
e7c84544 | 12326 | DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id); |
8af6cf88 | 12327 | |
e7c84544 | 12328 | active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config); |
d62cf62a | 12329 | |
e7c84544 ML |
12330 | /* hw state is inconsistent with the pipe quirk */ |
12331 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
12332 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
12333 | active = new_crtc_state->active; | |
6c49f241 | 12334 | |
e7c84544 ML |
12335 | I915_STATE_WARN(new_crtc_state->active != active, |
12336 | "crtc active state doesn't match with hw state " | |
12337 | "(expected %i, found %i)\n", new_crtc_state->active, active); | |
0e8ffe1b | 12338 | |
e7c84544 ML |
12339 | I915_STATE_WARN(intel_crtc->active != new_crtc_state->active, |
12340 | "transitional active state does not match atomic hw state " | |
12341 | "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active); | |
4d20cd86 | 12342 | |
e7c84544 ML |
12343 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
12344 | enum pipe pipe; | |
4d20cd86 | 12345 | |
e7c84544 ML |
12346 | active = encoder->get_hw_state(encoder, &pipe); |
12347 | I915_STATE_WARN(active != new_crtc_state->active, | |
12348 | "[ENCODER:%i] active %i with crtc active %i\n", | |
12349 | encoder->base.base.id, active, new_crtc_state->active); | |
4d20cd86 | 12350 | |
e7c84544 ML |
12351 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, |
12352 | "Encoder connected to wrong pipe %c\n", | |
12353 | pipe_name(pipe)); | |
4d20cd86 | 12354 | |
e7c84544 ML |
12355 | if (active) |
12356 | encoder->get_config(encoder, pipe_config); | |
12357 | } | |
53d9f4e9 | 12358 | |
e7c84544 ML |
12359 | if (!new_crtc_state->active) |
12360 | return; | |
cfb23ed6 | 12361 | |
e7c84544 | 12362 | intel_pipe_config_sanity_check(dev_priv, pipe_config); |
e3b247da | 12363 | |
e7c84544 ML |
12364 | sw_config = to_intel_crtc_state(crtc->state); |
12365 | if (!intel_pipe_config_compare(dev, sw_config, | |
12366 | pipe_config, false)) { | |
12367 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); | |
12368 | intel_dump_pipe_config(intel_crtc, pipe_config, | |
12369 | "[hw state]"); | |
12370 | intel_dump_pipe_config(intel_crtc, sw_config, | |
12371 | "[sw state]"); | |
8af6cf88 DV |
12372 | } |
12373 | } | |
12374 | ||
91d1b4bd | 12375 | static void |
c0ead703 ML |
12376 | verify_single_dpll_state(struct drm_i915_private *dev_priv, |
12377 | struct intel_shared_dpll *pll, | |
12378 | struct drm_crtc *crtc, | |
12379 | struct drm_crtc_state *new_state) | |
91d1b4bd | 12380 | { |
91d1b4bd | 12381 | struct intel_dpll_hw_state dpll_hw_state; |
e7c84544 ML |
12382 | unsigned crtc_mask; |
12383 | bool active; | |
5358901f | 12384 | |
e7c84544 | 12385 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); |
5358901f | 12386 | |
e7c84544 | 12387 | DRM_DEBUG_KMS("%s\n", pll->name); |
5358901f | 12388 | |
e7c84544 | 12389 | active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state); |
5358901f | 12390 | |
e7c84544 ML |
12391 | if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) { |
12392 | I915_STATE_WARN(!pll->on && pll->active_mask, | |
12393 | "pll in active use but not on in sw tracking\n"); | |
12394 | I915_STATE_WARN(pll->on && !pll->active_mask, | |
12395 | "pll is on but not used by any active crtc\n"); | |
12396 | I915_STATE_WARN(pll->on != active, | |
12397 | "pll on state mismatch (expected %i, found %i)\n", | |
12398 | pll->on, active); | |
12399 | } | |
5358901f | 12400 | |
e7c84544 | 12401 | if (!crtc) { |
2dd66ebd | 12402 | I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask, |
e7c84544 ML |
12403 | "more active pll users than references: %x vs %x\n", |
12404 | pll->active_mask, pll->config.crtc_mask); | |
5358901f | 12405 | |
e7c84544 ML |
12406 | return; |
12407 | } | |
12408 | ||
12409 | crtc_mask = 1 << drm_crtc_index(crtc); | |
12410 | ||
12411 | if (new_state->active) | |
12412 | I915_STATE_WARN(!(pll->active_mask & crtc_mask), | |
12413 | "pll active mismatch (expected pipe %c in active mask 0x%02x)\n", | |
12414 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
12415 | else | |
12416 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
12417 | "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n", | |
12418 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
2dd66ebd | 12419 | |
e7c84544 ML |
12420 | I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask), |
12421 | "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n", | |
12422 | crtc_mask, pll->config.crtc_mask); | |
66e985c0 | 12423 | |
e7c84544 ML |
12424 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, |
12425 | &dpll_hw_state, | |
12426 | sizeof(dpll_hw_state)), | |
12427 | "pll hw state mismatch\n"); | |
12428 | } | |
12429 | ||
12430 | static void | |
c0ead703 ML |
12431 | verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc, |
12432 | struct drm_crtc_state *old_crtc_state, | |
12433 | struct drm_crtc_state *new_crtc_state) | |
e7c84544 ML |
12434 | { |
12435 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12436 | struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state); | |
12437 | struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state); | |
12438 | ||
12439 | if (new_state->shared_dpll) | |
c0ead703 | 12440 | verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state); |
e7c84544 ML |
12441 | |
12442 | if (old_state->shared_dpll && | |
12443 | old_state->shared_dpll != new_state->shared_dpll) { | |
12444 | unsigned crtc_mask = 1 << drm_crtc_index(crtc); | |
12445 | struct intel_shared_dpll *pll = old_state->shared_dpll; | |
12446 | ||
12447 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
12448 | "pll active mismatch (didn't expect pipe %c in active mask)\n", | |
12449 | pipe_name(drm_crtc_index(crtc))); | |
12450 | I915_STATE_WARN(pll->config.crtc_mask & crtc_mask, | |
12451 | "pll enabled crtcs mismatch (found %x in enabled mask)\n", | |
12452 | pipe_name(drm_crtc_index(crtc))); | |
5358901f | 12453 | } |
8af6cf88 DV |
12454 | } |
12455 | ||
e7c84544 | 12456 | static void |
c0ead703 | 12457 | intel_modeset_verify_crtc(struct drm_crtc *crtc, |
e7c84544 ML |
12458 | struct drm_crtc_state *old_state, |
12459 | struct drm_crtc_state *new_state) | |
12460 | { | |
c0ead703 | 12461 | verify_wm_state(crtc, new_state); |
c0ead703 ML |
12462 | verify_crtc_state(crtc, old_state, new_state); |
12463 | verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state); | |
e7c84544 ML |
12464 | } |
12465 | ||
12466 | static void | |
c0ead703 | 12467 | verify_disabled_dpll_state(struct drm_device *dev) |
e7c84544 ML |
12468 | { |
12469 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12470 | int i; | |
12471 | ||
12472 | for (i = 0; i < dev_priv->num_shared_dpll; i++) | |
c0ead703 | 12473 | verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL); |
e7c84544 ML |
12474 | } |
12475 | ||
12476 | static void | |
c0ead703 | 12477 | intel_modeset_verify_disabled(struct drm_device *dev) |
e7c84544 | 12478 | { |
c0ead703 ML |
12479 | verify_encoder_state(dev); |
12480 | verify_connector_state(dev, NULL); | |
12481 | verify_disabled_dpll_state(dev); | |
e7c84544 ML |
12482 | } |
12483 | ||
80715b2f VS |
12484 | static void update_scanline_offset(struct intel_crtc *crtc) |
12485 | { | |
12486 | struct drm_device *dev = crtc->base.dev; | |
12487 | ||
12488 | /* | |
12489 | * The scanline counter increments at the leading edge of hsync. | |
12490 | * | |
12491 | * On most platforms it starts counting from vtotal-1 on the | |
12492 | * first active line. That means the scanline counter value is | |
12493 | * always one less than what we would expect. Ie. just after | |
12494 | * start of vblank, which also occurs at start of hsync (on the | |
12495 | * last active line), the scanline counter will read vblank_start-1. | |
12496 | * | |
12497 | * On gen2 the scanline counter starts counting from 1 instead | |
12498 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
12499 | * to keep the value positive), instead of adding one. | |
12500 | * | |
12501 | * On HSW+ the behaviour of the scanline counter depends on the output | |
12502 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
12503 | * there's an extra 1 line difference. So we need to add two instead of | |
12504 | * one to the value. | |
12505 | */ | |
12506 | if (IS_GEN2(dev)) { | |
124abe07 | 12507 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
12508 | int vtotal; |
12509 | ||
124abe07 VS |
12510 | vtotal = adjusted_mode->crtc_vtotal; |
12511 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
12512 | vtotal /= 2; |
12513 | ||
12514 | crtc->scanline_offset = vtotal - 1; | |
12515 | } else if (HAS_DDI(dev) && | |
409ee761 | 12516 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
12517 | crtc->scanline_offset = 2; |
12518 | } else | |
12519 | crtc->scanline_offset = 1; | |
12520 | } | |
12521 | ||
ad421372 | 12522 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 12523 | { |
225da59b | 12524 | struct drm_device *dev = state->dev; |
ed6739ef | 12525 | struct drm_i915_private *dev_priv = to_i915(dev); |
ad421372 | 12526 | struct intel_shared_dpll_config *shared_dpll = NULL; |
0a9ab303 ACO |
12527 | struct drm_crtc *crtc; |
12528 | struct drm_crtc_state *crtc_state; | |
0a9ab303 | 12529 | int i; |
ed6739ef ACO |
12530 | |
12531 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 12532 | return; |
ed6739ef | 12533 | |
0a9ab303 | 12534 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
fb1a38a9 | 12535 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8106ddbd ACO |
12536 | struct intel_shared_dpll *old_dpll = |
12537 | to_intel_crtc_state(crtc->state)->shared_dpll; | |
0a9ab303 | 12538 | |
fb1a38a9 | 12539 | if (!needs_modeset(crtc_state)) |
225da59b ACO |
12540 | continue; |
12541 | ||
8106ddbd | 12542 | to_intel_crtc_state(crtc_state)->shared_dpll = NULL; |
fb1a38a9 | 12543 | |
8106ddbd | 12544 | if (!old_dpll) |
fb1a38a9 | 12545 | continue; |
0a9ab303 | 12546 | |
ad421372 ML |
12547 | if (!shared_dpll) |
12548 | shared_dpll = intel_atomic_get_shared_dpll_state(state); | |
ed6739ef | 12549 | |
8106ddbd | 12550 | intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc); |
ad421372 | 12551 | } |
ed6739ef ACO |
12552 | } |
12553 | ||
99d736a2 ML |
12554 | /* |
12555 | * This implements the workaround described in the "notes" section of the mode | |
12556 | * set sequence documentation. When going from no pipes or single pipe to | |
12557 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
12558 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
12559 | */ | |
12560 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
12561 | { | |
12562 | struct drm_crtc_state *crtc_state; | |
12563 | struct intel_crtc *intel_crtc; | |
12564 | struct drm_crtc *crtc; | |
12565 | struct intel_crtc_state *first_crtc_state = NULL; | |
12566 | struct intel_crtc_state *other_crtc_state = NULL; | |
12567 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
12568 | int i; | |
12569 | ||
12570 | /* look at all crtc's that are going to be enabled in during modeset */ | |
12571 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
12572 | intel_crtc = to_intel_crtc(crtc); | |
12573 | ||
12574 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
12575 | continue; | |
12576 | ||
12577 | if (first_crtc_state) { | |
12578 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
12579 | break; | |
12580 | } else { | |
12581 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
12582 | first_pipe = intel_crtc->pipe; | |
12583 | } | |
12584 | } | |
12585 | ||
12586 | /* No workaround needed? */ | |
12587 | if (!first_crtc_state) | |
12588 | return 0; | |
12589 | ||
12590 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
12591 | for_each_intel_crtc(state->dev, intel_crtc) { | |
12592 | struct intel_crtc_state *pipe_config; | |
12593 | ||
12594 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
12595 | if (IS_ERR(pipe_config)) | |
12596 | return PTR_ERR(pipe_config); | |
12597 | ||
12598 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
12599 | ||
12600 | if (!pipe_config->base.active || | |
12601 | needs_modeset(&pipe_config->base)) | |
12602 | continue; | |
12603 | ||
12604 | /* 2 or more enabled crtcs means no need for w/a */ | |
12605 | if (enabled_pipe != INVALID_PIPE) | |
12606 | return 0; | |
12607 | ||
12608 | enabled_pipe = intel_crtc->pipe; | |
12609 | } | |
12610 | ||
12611 | if (enabled_pipe != INVALID_PIPE) | |
12612 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
12613 | else if (other_crtc_state) | |
12614 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
12615 | ||
12616 | return 0; | |
12617 | } | |
12618 | ||
27c329ed ML |
12619 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
12620 | { | |
12621 | struct drm_crtc *crtc; | |
12622 | struct drm_crtc_state *crtc_state; | |
12623 | int ret = 0; | |
12624 | ||
12625 | /* add all active pipes to the state */ | |
12626 | for_each_crtc(state->dev, crtc) { | |
12627 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
12628 | if (IS_ERR(crtc_state)) | |
12629 | return PTR_ERR(crtc_state); | |
12630 | ||
12631 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
12632 | continue; | |
12633 | ||
12634 | crtc_state->mode_changed = true; | |
12635 | ||
12636 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
12637 | if (ret) | |
12638 | break; | |
12639 | ||
12640 | ret = drm_atomic_add_affected_planes(state, crtc); | |
12641 | if (ret) | |
12642 | break; | |
12643 | } | |
12644 | ||
12645 | return ret; | |
12646 | } | |
12647 | ||
c347a676 | 12648 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd | 12649 | { |
565602d7 ML |
12650 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
12651 | struct drm_i915_private *dev_priv = state->dev->dev_private; | |
12652 | struct drm_crtc *crtc; | |
12653 | struct drm_crtc_state *crtc_state; | |
12654 | int ret = 0, i; | |
054518dd | 12655 | |
b359283a ML |
12656 | if (!check_digital_port_conflicts(state)) { |
12657 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
12658 | return -EINVAL; | |
12659 | } | |
12660 | ||
565602d7 ML |
12661 | intel_state->modeset = true; |
12662 | intel_state->active_crtcs = dev_priv->active_crtcs; | |
12663 | ||
12664 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
12665 | if (crtc_state->active) | |
12666 | intel_state->active_crtcs |= 1 << i; | |
12667 | else | |
12668 | intel_state->active_crtcs &= ~(1 << i); | |
8b4a7d05 MR |
12669 | |
12670 | if (crtc_state->active != crtc->state->active) | |
12671 | intel_state->active_pipe_changes |= drm_crtc_mask(crtc); | |
565602d7 ML |
12672 | } |
12673 | ||
054518dd ACO |
12674 | /* |
12675 | * See if the config requires any additional preparation, e.g. | |
12676 | * to adjust global state with pipes off. We need to do this | |
12677 | * here so we can get the modeset_pipe updated config for the new | |
12678 | * mode set on this crtc. For other crtcs we need to use the | |
12679 | * adjusted_mode bits in the crtc directly. | |
12680 | */ | |
27c329ed | 12681 | if (dev_priv->display.modeset_calc_cdclk) { |
c89e39f3 | 12682 | if (!intel_state->cdclk_pll_vco) |
63911d72 | 12683 | intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco; |
b2045352 VS |
12684 | if (!intel_state->cdclk_pll_vco) |
12685 | intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq; | |
c89e39f3 | 12686 | |
27c329ed | 12687 | ret = dev_priv->display.modeset_calc_cdclk(state); |
c89e39f3 CT |
12688 | if (ret < 0) |
12689 | return ret; | |
27c329ed | 12690 | |
c89e39f3 | 12691 | if (intel_state->dev_cdclk != dev_priv->cdclk_freq || |
63911d72 | 12692 | intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco) |
27c329ed ML |
12693 | ret = intel_modeset_all_pipes(state); |
12694 | ||
12695 | if (ret < 0) | |
054518dd | 12696 | return ret; |
e8788cbc ML |
12697 | |
12698 | DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n", | |
12699 | intel_state->cdclk, intel_state->dev_cdclk); | |
27c329ed | 12700 | } else |
1a617b77 | 12701 | to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq; |
054518dd | 12702 | |
ad421372 | 12703 | intel_modeset_clear_plls(state); |
054518dd | 12704 | |
565602d7 | 12705 | if (IS_HASWELL(dev_priv)) |
ad421372 | 12706 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 12707 | |
ad421372 | 12708 | return 0; |
c347a676 ACO |
12709 | } |
12710 | ||
aa363136 MR |
12711 | /* |
12712 | * Handle calculation of various watermark data at the end of the atomic check | |
12713 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
12714 | * handlers to ensure that all derived state has been updated. | |
12715 | */ | |
55994c2c | 12716 | static int calc_watermark_data(struct drm_atomic_state *state) |
aa363136 MR |
12717 | { |
12718 | struct drm_device *dev = state->dev; | |
98d39494 | 12719 | struct drm_i915_private *dev_priv = to_i915(dev); |
98d39494 MR |
12720 | |
12721 | /* Is there platform-specific watermark information to calculate? */ | |
12722 | if (dev_priv->display.compute_global_watermarks) | |
55994c2c MR |
12723 | return dev_priv->display.compute_global_watermarks(state); |
12724 | ||
12725 | return 0; | |
aa363136 MR |
12726 | } |
12727 | ||
74c090b1 ML |
12728 | /** |
12729 | * intel_atomic_check - validate state object | |
12730 | * @dev: drm device | |
12731 | * @state: state to validate | |
12732 | */ | |
12733 | static int intel_atomic_check(struct drm_device *dev, | |
12734 | struct drm_atomic_state *state) | |
c347a676 | 12735 | { |
dd8b3bdb | 12736 | struct drm_i915_private *dev_priv = to_i915(dev); |
aa363136 | 12737 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
c347a676 ACO |
12738 | struct drm_crtc *crtc; |
12739 | struct drm_crtc_state *crtc_state; | |
12740 | int ret, i; | |
61333b60 | 12741 | bool any_ms = false; |
c347a676 | 12742 | |
74c090b1 | 12743 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
12744 | if (ret) |
12745 | return ret; | |
12746 | ||
c347a676 | 12747 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
cfb23ed6 ML |
12748 | struct intel_crtc_state *pipe_config = |
12749 | to_intel_crtc_state(crtc_state); | |
1ed51de9 DV |
12750 | |
12751 | /* Catch I915_MODE_FLAG_INHERITED */ | |
12752 | if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) | |
12753 | crtc_state->mode_changed = true; | |
cfb23ed6 | 12754 | |
af4a879e | 12755 | if (!needs_modeset(crtc_state)) |
c347a676 ACO |
12756 | continue; |
12757 | ||
af4a879e DV |
12758 | if (!crtc_state->enable) { |
12759 | any_ms = true; | |
cfb23ed6 | 12760 | continue; |
af4a879e | 12761 | } |
cfb23ed6 | 12762 | |
26495481 DV |
12763 | /* FIXME: For only active_changed we shouldn't need to do any |
12764 | * state recomputation at all. */ | |
12765 | ||
1ed51de9 DV |
12766 | ret = drm_atomic_add_affected_connectors(state, crtc); |
12767 | if (ret) | |
12768 | return ret; | |
b359283a | 12769 | |
cfb23ed6 | 12770 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
25aa1c39 ML |
12771 | if (ret) { |
12772 | intel_dump_pipe_config(to_intel_crtc(crtc), | |
12773 | pipe_config, "[failed]"); | |
c347a676 | 12774 | return ret; |
25aa1c39 | 12775 | } |
c347a676 | 12776 | |
73831236 | 12777 | if (i915.fastboot && |
dd8b3bdb | 12778 | intel_pipe_config_compare(dev, |
cfb23ed6 | 12779 | to_intel_crtc_state(crtc->state), |
1ed51de9 | 12780 | pipe_config, true)) { |
26495481 | 12781 | crtc_state->mode_changed = false; |
bfd16b2a | 12782 | to_intel_crtc_state(crtc_state)->update_pipe = true; |
26495481 DV |
12783 | } |
12784 | ||
af4a879e | 12785 | if (needs_modeset(crtc_state)) |
26495481 | 12786 | any_ms = true; |
cfb23ed6 | 12787 | |
af4a879e DV |
12788 | ret = drm_atomic_add_affected_planes(state, crtc); |
12789 | if (ret) | |
12790 | return ret; | |
61333b60 | 12791 | |
26495481 DV |
12792 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
12793 | needs_modeset(crtc_state) ? | |
12794 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
12795 | } |
12796 | ||
61333b60 ML |
12797 | if (any_ms) { |
12798 | ret = intel_modeset_checks(state); | |
12799 | ||
12800 | if (ret) | |
12801 | return ret; | |
27c329ed | 12802 | } else |
dd8b3bdb | 12803 | intel_state->cdclk = dev_priv->cdclk_freq; |
76305b1a | 12804 | |
dd8b3bdb | 12805 | ret = drm_atomic_helper_check_planes(dev, state); |
aa363136 MR |
12806 | if (ret) |
12807 | return ret; | |
12808 | ||
f51be2e0 | 12809 | intel_fbc_choose_crtc(dev_priv, state); |
55994c2c | 12810 | return calc_watermark_data(state); |
054518dd ACO |
12811 | } |
12812 | ||
a6747b73 ML |
12813 | static bool needs_work(struct drm_crtc_state *crtc_state) |
12814 | { | |
12815 | /* hw state checker needs to run */ | |
12816 | if (needs_modeset(crtc_state)) | |
12817 | return true; | |
12818 | ||
12819 | /* unpin old fb's, possibly vblank update */ | |
12820 | if (crtc_state->planes_changed) | |
12821 | return true; | |
12822 | ||
12823 | /* pipe parameters need to be updated, and hw state checker */ | |
12824 | if (to_intel_crtc_state(crtc_state)->update_pipe) | |
12825 | return true; | |
12826 | ||
12827 | /* vblank event requested? */ | |
12828 | if (crtc_state->event) | |
12829 | return true; | |
12830 | ||
12831 | return false; | |
12832 | } | |
12833 | ||
5008e874 ML |
12834 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
12835 | struct drm_atomic_state *state, | |
81072bfd | 12836 | bool nonblock) |
5008e874 | 12837 | { |
7580d774 | 12838 | struct drm_i915_private *dev_priv = dev->dev_private; |
a6747b73 | 12839 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
7580d774 | 12840 | struct drm_plane_state *plane_state; |
5008e874 | 12841 | struct drm_crtc_state *crtc_state; |
7580d774 | 12842 | struct drm_plane *plane; |
5008e874 ML |
12843 | struct drm_crtc *crtc; |
12844 | int i, ret; | |
12845 | ||
5008e874 | 12846 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
a6747b73 ML |
12847 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
12848 | struct intel_flip_work *work; | |
12849 | ||
95c2ccdc ML |
12850 | if (!state->legacy_cursor_update) { |
12851 | ret = intel_crtc_wait_for_pending_flips(crtc); | |
12852 | if (ret) | |
12853 | return ret; | |
7580d774 | 12854 | |
95c2ccdc ML |
12855 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
12856 | flush_workqueue(dev_priv->wq); | |
12857 | } | |
a6747b73 ML |
12858 | |
12859 | /* test if we need to update something */ | |
12860 | if (!needs_work(crtc_state)) | |
12861 | continue; | |
12862 | ||
12863 | intel_state->work[i] = work = | |
12864 | kzalloc(sizeof(**intel_state->work), GFP_KERNEL); | |
12865 | ||
12866 | if (!work) | |
12867 | return -ENOMEM; | |
12868 | ||
12869 | if (needs_modeset(crtc_state) || | |
12870 | to_intel_crtc_state(crtc_state)->update_pipe) { | |
12871 | work->num_old_connectors = hweight32(crtc->state->connector_mask); | |
12872 | ||
12873 | work->old_connector_state = kcalloc(work->num_old_connectors, | |
12874 | sizeof(*work->old_connector_state), | |
12875 | GFP_KERNEL); | |
12876 | ||
12877 | work->num_new_connectors = hweight32(crtc_state->connector_mask); | |
12878 | work->new_connector_state = kcalloc(work->num_new_connectors, | |
12879 | sizeof(*work->new_connector_state), | |
12880 | GFP_KERNEL); | |
12881 | ||
12882 | if (!work->old_connector_state || !work->new_connector_state) | |
12883 | return -ENOMEM; | |
12884 | } | |
5008e874 ML |
12885 | } |
12886 | ||
d55dbd06 ML |
12887 | if (intel_state->modeset && nonblock) { |
12888 | DRM_DEBUG_ATOMIC("Nonblock modesets are not yet supported!\n"); | |
12889 | return -EINVAL; | |
12890 | } | |
12891 | ||
f935675f ML |
12892 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
12893 | if (ret) | |
12894 | return ret; | |
12895 | ||
5008e874 | 12896 | ret = drm_atomic_helper_prepare_planes(dev, state); |
f7e5838b | 12897 | mutex_unlock(&dev->struct_mutex); |
7580d774 | 12898 | |
21daaeee | 12899 | if (!ret && !nonblock) { |
7580d774 ML |
12900 | for_each_plane_in_state(state, plane, plane_state, i) { |
12901 | struct intel_plane_state *intel_plane_state = | |
12902 | to_intel_plane_state(plane_state); | |
12903 | ||
84fc494b ML |
12904 | if (plane_state->fence) { |
12905 | long lret = fence_wait(plane_state->fence, true); | |
12906 | ||
12907 | if (lret < 0) { | |
12908 | ret = lret; | |
12909 | break; | |
12910 | } | |
12911 | } | |
12912 | ||
7580d774 ML |
12913 | if (!intel_plane_state->wait_req) |
12914 | continue; | |
12915 | ||
12916 | ret = __i915_wait_request(intel_plane_state->wait_req, | |
299259a3 | 12917 | true, NULL, NULL); |
f7e5838b | 12918 | if (ret) { |
f4457ae7 CW |
12919 | /* Any hang should be swallowed by the wait */ |
12920 | WARN_ON(ret == -EIO); | |
f7e5838b CW |
12921 | mutex_lock(&dev->struct_mutex); |
12922 | drm_atomic_helper_cleanup_planes(dev, state); | |
12923 | mutex_unlock(&dev->struct_mutex); | |
7580d774 | 12924 | break; |
f7e5838b | 12925 | } |
7580d774 | 12926 | } |
7580d774 | 12927 | } |
5008e874 ML |
12928 | |
12929 | return ret; | |
12930 | } | |
12931 | ||
a2991414 ML |
12932 | u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc) |
12933 | { | |
12934 | struct drm_device *dev = crtc->base.dev; | |
12935 | ||
12936 | if (!dev->max_vblank_count) | |
12937 | return drm_accurate_vblank_count(&crtc->base); | |
12938 | ||
12939 | return dev->driver->get_vblank_counter(dev, crtc->pipe); | |
12940 | } | |
12941 | ||
a6747b73 ML |
12942 | static void intel_prepare_work(struct drm_crtc *crtc, |
12943 | struct intel_flip_work *work, | |
12944 | struct drm_atomic_state *state, | |
12945 | struct drm_crtc_state *old_crtc_state) | |
e8861675 | 12946 | { |
a6747b73 ML |
12947 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
12948 | struct drm_plane_state *old_plane_state; | |
12949 | struct drm_plane *plane; | |
12950 | int i, j = 0; | |
e8861675 | 12951 | |
a6747b73 ML |
12952 | INIT_WORK(&work->unpin_work, intel_unpin_work_fn); |
12953 | INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func); | |
12954 | atomic_inc(&intel_crtc->unpin_work_count); | |
e8861675 | 12955 | |
a6747b73 ML |
12956 | for_each_plane_in_state(state, plane, old_plane_state, i) { |
12957 | struct intel_plane_state *old_state = to_intel_plane_state(old_plane_state); | |
12958 | struct intel_plane_state *new_state = to_intel_plane_state(plane->state); | |
e8861675 | 12959 | |
a6747b73 ML |
12960 | if (old_state->base.crtc != crtc && |
12961 | new_state->base.crtc != crtc) | |
e8861675 ML |
12962 | continue; |
12963 | ||
a6747b73 ML |
12964 | if (plane->type == DRM_PLANE_TYPE_PRIMARY) { |
12965 | plane->fb = new_state->base.fb; | |
12966 | crtc->x = new_state->base.src_x >> 16; | |
12967 | crtc->y = new_state->base.src_y >> 16; | |
e8861675 ML |
12968 | } |
12969 | ||
a6747b73 ML |
12970 | old_state->wait_req = new_state->wait_req; |
12971 | new_state->wait_req = NULL; | |
12972 | ||
12973 | old_state->base.fence = new_state->base.fence; | |
12974 | new_state->base.fence = NULL; | |
12975 | ||
12976 | /* remove plane state from the atomic state and move it to work */ | |
12977 | old_plane_state->state = NULL; | |
12978 | state->planes[i] = NULL; | |
12979 | state->plane_states[i] = NULL; | |
12980 | ||
12981 | work->old_plane_state[j] = old_state; | |
12982 | work->new_plane_state[j++] = new_state; | |
e8861675 ML |
12983 | } |
12984 | ||
a6747b73 ML |
12985 | old_crtc_state->state = NULL; |
12986 | state->crtcs[drm_crtc_index(crtc)] = NULL; | |
12987 | state->crtc_states[drm_crtc_index(crtc)] = NULL; | |
e8861675 | 12988 | |
a6747b73 ML |
12989 | work->old_crtc_state = to_intel_crtc_state(old_crtc_state); |
12990 | work->new_crtc_state = to_intel_crtc_state(crtc->state); | |
12991 | work->num_planes = j; | |
e8861675 | 12992 | |
a6747b73 ML |
12993 | work->event = crtc->state->event; |
12994 | crtc->state->event = NULL; | |
e8861675 | 12995 | |
a6747b73 ML |
12996 | if (needs_modeset(crtc->state) || work->new_crtc_state->update_pipe) { |
12997 | struct drm_connector *conn; | |
12998 | struct drm_connector_state *old_conn_state; | |
12999 | int k = 0; | |
e8861675 | 13000 | |
a6747b73 ML |
13001 | j = 0; |
13002 | ||
13003 | /* | |
13004 | * intel_unpin_work_fn cannot depend on the connector list | |
13005 | * because it may be freed from underneath it, so add | |
13006 | * them all to the work struct while we're holding locks. | |
13007 | */ | |
13008 | for_each_connector_in_state(state, conn, old_conn_state, i) { | |
13009 | if (old_conn_state->crtc == crtc) { | |
13010 | work->old_connector_state[j++] = old_conn_state; | |
13011 | ||
13012 | state->connectors[i] = NULL; | |
13013 | state->connector_states[i] = NULL; | |
13014 | } | |
13015 | } | |
13016 | ||
13017 | /* If another crtc has stolen the connector from state, | |
13018 | * then for_each_connector_in_state is no longer reliable, | |
13019 | * so use drm_for_each_connector here. | |
13020 | */ | |
13021 | drm_for_each_connector(conn, state->dev) | |
13022 | if (conn->state->crtc == crtc) | |
13023 | work->new_connector_state[k++] = conn->state; | |
13024 | ||
13025 | WARN(j != work->num_old_connectors, "j = %i, expected %i\n", j, work->num_old_connectors); | |
13026 | WARN(k != work->num_new_connectors, "k = %i, expected %i\n", k, work->num_new_connectors); | |
13027 | } else if (!work->new_crtc_state->update_wm_post) | |
13028 | work->can_async_unpin = true; | |
13029 | ||
13030 | work->fb_bits = work->new_crtc_state->fb_bits; | |
e8861675 ML |
13031 | } |
13032 | ||
a6747b73 ML |
13033 | static void intel_schedule_unpin(struct drm_crtc *crtc, |
13034 | struct intel_atomic_state *state, | |
13035 | struct intel_flip_work *work) | |
e8861675 | 13036 | { |
a6747b73 ML |
13037 | struct drm_device *dev = crtc->dev; |
13038 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e8861675 | 13039 | |
a6747b73 | 13040 | to_intel_crtc(crtc)->config = work->new_crtc_state; |
e8861675 | 13041 | |
a6747b73 ML |
13042 | queue_work(dev_priv->wq, &work->unpin_work); |
13043 | } | |
e8861675 | 13044 | |
d55dbd06 ML |
13045 | static void intel_schedule_flip(struct drm_crtc *crtc, |
13046 | struct intel_atomic_state *state, | |
13047 | struct intel_flip_work *work, | |
13048 | bool nonblock) | |
13049 | { | |
13050 | struct intel_crtc_state *crtc_state = work->new_crtc_state; | |
13051 | ||
13052 | if (crtc_state->base.planes_changed || | |
13053 | needs_modeset(&crtc_state->base) || | |
13054 | crtc_state->update_pipe) { | |
13055 | if (nonblock) | |
13056 | schedule_work(&work->mmio_work); | |
13057 | else | |
13058 | intel_mmio_flip_work_func(&work->mmio_work); | |
13059 | } else { | |
13060 | int ret; | |
13061 | ||
13062 | ret = drm_crtc_vblank_get(crtc); | |
13063 | I915_STATE_WARN(ret < 0, "enabling vblank failed with %i\n", ret); | |
13064 | ||
13065 | work->flip_queued_vblank = intel_crtc_get_vblank_counter(to_intel_crtc(crtc)); | |
13066 | smp_mb__before_atomic(); | |
13067 | atomic_set(&work->pending, 1); | |
13068 | } | |
13069 | } | |
13070 | ||
a6747b73 ML |
13071 | static void intel_schedule_update(struct drm_crtc *crtc, |
13072 | struct intel_atomic_state *state, | |
d55dbd06 ML |
13073 | struct intel_flip_work *work, |
13074 | bool nonblock) | |
a6747b73 ML |
13075 | { |
13076 | struct drm_device *dev = crtc->dev; | |
d55dbd06 | 13077 | struct intel_crtc_state *pipe_config = work->new_crtc_state; |
a6747b73 | 13078 | |
d55dbd06 | 13079 | if (!pipe_config->base.active && work->can_async_unpin) { |
a6747b73 ML |
13080 | INIT_LIST_HEAD(&work->head); |
13081 | intel_schedule_unpin(crtc, state, work); | |
13082 | return; | |
13083 | } | |
13084 | ||
13085 | spin_lock_irq(&dev->event_lock); | |
13086 | list_add_tail(&work->head, &to_intel_crtc(crtc)->flip_work); | |
13087 | spin_unlock_irq(&dev->event_lock); | |
13088 | ||
d55dbd06 ML |
13089 | if (!pipe_config->base.active) |
13090 | intel_schedule_unpin(crtc, state, work); | |
13091 | else | |
13092 | intel_schedule_flip(crtc, state, work, nonblock); | |
e8861675 ML |
13093 | } |
13094 | ||
74c090b1 ML |
13095 | /** |
13096 | * intel_atomic_commit - commit validated state object | |
13097 | * @dev: DRM device | |
13098 | * @state: the top-level driver state object | |
81072bfd | 13099 | * @nonblock: nonblocking commit |
74c090b1 ML |
13100 | * |
13101 | * This function commits a top-level state object that has been validated | |
13102 | * with drm_atomic_helper_check(). | |
13103 | * | |
13104 | * FIXME: Atomic modeset support for i915 is not yet complete. At the moment | |
13105 | * we can only handle plane-related operations and do not yet support | |
81072bfd | 13106 | * nonblocking commit. |
74c090b1 ML |
13107 | * |
13108 | * RETURNS | |
13109 | * Zero for success or -errno. | |
13110 | */ | |
13111 | static int intel_atomic_commit(struct drm_device *dev, | |
13112 | struct drm_atomic_state *state, | |
81072bfd | 13113 | bool nonblock) |
a6778b3c | 13114 | { |
565602d7 | 13115 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fbee40df | 13116 | struct drm_i915_private *dev_priv = dev->dev_private; |
29ceb0e6 | 13117 | struct drm_crtc_state *old_crtc_state; |
7580d774 | 13118 | struct drm_crtc *crtc; |
565602d7 | 13119 | int ret = 0, i; |
a6778b3c | 13120 | |
81072bfd | 13121 | ret = intel_atomic_prepare_commit(dev, state, nonblock); |
7580d774 ML |
13122 | if (ret) { |
13123 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); | |
d4afb8cc | 13124 | return ret; |
7580d774 | 13125 | } |
d4afb8cc | 13126 | |
1c5e19f8 | 13127 | drm_atomic_helper_swap_state(dev, state); |
279e99d7 | 13128 | dev_priv->wm.distrust_bios_wm = false; |
734fa01f | 13129 | dev_priv->wm.skl_results = intel_state->wm_results; |
a1475e77 | 13130 | intel_shared_dpll_commit(state); |
1c5e19f8 | 13131 | |
565602d7 ML |
13132 | if (intel_state->modeset) { |
13133 | memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, | |
13134 | sizeof(intel_state->min_pixclk)); | |
13135 | dev_priv->active_crtcs = intel_state->active_crtcs; | |
1a617b77 | 13136 | dev_priv->atomic_cdclk_freq = intel_state->cdclk; |
565602d7 ML |
13137 | } |
13138 | ||
29ceb0e6 | 13139 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
a539205a ML |
13140 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13141 | ||
61333b60 ML |
13142 | if (!needs_modeset(crtc->state)) |
13143 | continue; | |
13144 | ||
29ceb0e6 | 13145 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); |
460da916 | 13146 | |
a6747b73 ML |
13147 | intel_state->work[i]->put_power_domains = |
13148 | modeset_get_crtc_power_domains(crtc, | |
13149 | to_intel_crtc_state(crtc->state)); | |
13150 | ||
29ceb0e6 VS |
13151 | if (old_crtc_state->active) { |
13152 | intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask); | |
a539205a | 13153 | dev_priv->display.crtc_disable(crtc); |
eddfcbcd | 13154 | intel_crtc->active = false; |
58f9c0bc | 13155 | intel_fbc_disable(intel_crtc); |
eddfcbcd | 13156 | intel_disable_shared_dpll(intel_crtc); |
9bbc8258 VS |
13157 | |
13158 | /* | |
13159 | * Underruns don't always raise | |
13160 | * interrupts, so check manually. | |
13161 | */ | |
13162 | intel_check_cpu_fifo_underruns(dev_priv); | |
13163 | intel_check_pch_fifo_underruns(dev_priv); | |
b9001114 ML |
13164 | |
13165 | if (!crtc->state->active) | |
13166 | intel_update_watermarks(crtc); | |
a539205a | 13167 | } |
b8cecdf5 | 13168 | } |
7758a113 | 13169 | |
ea9d758d DV |
13170 | /* Only after disabling all output pipelines that will be changed can we |
13171 | * update the the output configuration. */ | |
4740b0f2 | 13172 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 13173 | |
565602d7 | 13174 | if (intel_state->modeset) { |
4740b0f2 | 13175 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); |
33c8df89 ML |
13176 | |
13177 | if (dev_priv->display.modeset_commit_cdclk && | |
c89e39f3 | 13178 | (intel_state->dev_cdclk != dev_priv->cdclk_freq || |
63911d72 | 13179 | intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)) |
33c8df89 | 13180 | dev_priv->display.modeset_commit_cdclk(state); |
f6d1973d | 13181 | |
c0ead703 | 13182 | intel_modeset_verify_disabled(dev); |
4740b0f2 | 13183 | } |
47fab737 | 13184 | |
a6778b3c | 13185 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
29ceb0e6 | 13186 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
d55dbd06 | 13187 | struct intel_flip_work *work = intel_state->work[i]; |
f6ac4b2a ML |
13188 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13189 | bool modeset = needs_modeset(crtc->state); | |
9f836f90 | 13190 | |
f6ac4b2a | 13191 | if (modeset && crtc->state->active) { |
a539205a ML |
13192 | update_scanline_offset(to_intel_crtc(crtc)); |
13193 | dev_priv->display.crtc_enable(crtc); | |
13194 | } | |
80715b2f | 13195 | |
f6ac4b2a | 13196 | if (!modeset) |
29ceb0e6 | 13197 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); |
f6ac4b2a | 13198 | |
a6747b73 ML |
13199 | if (!work) { |
13200 | if (!list_empty_careful(&intel_crtc->flip_work)) { | |
13201 | spin_lock_irq(&dev->event_lock); | |
13202 | if (!list_empty(&intel_crtc->flip_work)) | |
13203 | work = list_last_entry(&intel_crtc->flip_work, | |
13204 | struct intel_flip_work, head); | |
13205 | ||
13206 | if (work && work->new_crtc_state == to_intel_crtc_state(old_crtc_state)) { | |
13207 | work->free_new_crtc_state = true; | |
13208 | state->crtc_states[i] = NULL; | |
13209 | state->crtcs[i] = NULL; | |
13210 | } | |
13211 | spin_unlock_irq(&dev->event_lock); | |
13212 | } | |
13213 | continue; | |
13214 | } | |
f6d1973d | 13215 | |
a6747b73 ML |
13216 | intel_state->work[i] = NULL; |
13217 | intel_prepare_work(crtc, work, state, old_crtc_state); | |
d55dbd06 | 13218 | intel_schedule_update(crtc, intel_state, work, nonblock); |
177246a8 MR |
13219 | } |
13220 | ||
d55dbd06 ML |
13221 | /* FIXME: add subpixel order */ |
13222 | ||
ee165b1a | 13223 | drm_atomic_state_free(state); |
f30da187 | 13224 | |
75714940 MK |
13225 | /* As one of the primary mmio accessors, KMS has a high likelihood |
13226 | * of triggering bugs in unclaimed access. After we finish | |
13227 | * modesetting, see if an error has been flagged, and if so | |
13228 | * enable debugging for the next modeset - and hope we catch | |
13229 | * the culprit. | |
13230 | * | |
13231 | * XXX note that we assume display power is on at this point. | |
13232 | * This might hold true now but we need to add pm helper to check | |
13233 | * unclaimed only when the hardware is on, as atomic commits | |
13234 | * can happen also when the device is completely off. | |
13235 | */ | |
13236 | intel_uncore_arm_unclaimed_mmio_detection(dev_priv); | |
13237 | ||
74c090b1 | 13238 | return 0; |
7f27126e JB |
13239 | } |
13240 | ||
c0c36b94 CW |
13241 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
13242 | { | |
83a57153 ACO |
13243 | struct drm_device *dev = crtc->dev; |
13244 | struct drm_atomic_state *state; | |
e694eb02 | 13245 | struct drm_crtc_state *crtc_state; |
2bfb4627 | 13246 | int ret; |
83a57153 ACO |
13247 | |
13248 | state = drm_atomic_state_alloc(dev); | |
13249 | if (!state) { | |
e694eb02 | 13250 | DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory", |
83a57153 ACO |
13251 | crtc->base.id); |
13252 | return; | |
13253 | } | |
13254 | ||
e694eb02 | 13255 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
83a57153 | 13256 | |
e694eb02 ML |
13257 | retry: |
13258 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13259 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
13260 | if (!ret) { | |
13261 | if (!crtc_state->active) | |
13262 | goto out; | |
83a57153 | 13263 | |
e694eb02 | 13264 | crtc_state->mode_changed = true; |
74c090b1 | 13265 | ret = drm_atomic_commit(state); |
83a57153 ACO |
13266 | } |
13267 | ||
e694eb02 ML |
13268 | if (ret == -EDEADLK) { |
13269 | drm_atomic_state_clear(state); | |
13270 | drm_modeset_backoff(state->acquire_ctx); | |
13271 | goto retry; | |
4ed9fb37 | 13272 | } |
4be07317 | 13273 | |
2bfb4627 | 13274 | if (ret) |
e694eb02 | 13275 | out: |
2bfb4627 | 13276 | drm_atomic_state_free(state); |
c0c36b94 CW |
13277 | } |
13278 | ||
25c5b266 DV |
13279 | #undef for_each_intel_crtc_masked |
13280 | ||
f6e5b160 | 13281 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
82cf435b | 13282 | .gamma_set = drm_atomic_helper_legacy_gamma_set, |
74c090b1 | 13283 | .set_config = drm_atomic_helper_set_config, |
82cf435b | 13284 | .set_property = drm_atomic_helper_crtc_set_property, |
f6e5b160 | 13285 | .destroy = intel_crtc_destroy, |
d55dbd06 | 13286 | .page_flip = drm_atomic_helper_page_flip, |
1356837e MR |
13287 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
13288 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
13289 | }; |
13290 | ||
d55dbd06 ML |
13291 | static struct fence *intel_get_excl_fence(struct drm_i915_gem_object *obj) |
13292 | { | |
13293 | struct reservation_object *resv; | |
13294 | ||
13295 | ||
13296 | if (!obj->base.dma_buf) | |
13297 | return NULL; | |
13298 | ||
13299 | resv = obj->base.dma_buf->resv; | |
13300 | ||
13301 | /* For framebuffer backed by dmabuf, wait for fence */ | |
13302 | while (1) { | |
13303 | struct fence *fence_excl, *ret = NULL; | |
13304 | ||
13305 | rcu_read_lock(); | |
13306 | ||
13307 | fence_excl = rcu_dereference(resv->fence_excl); | |
13308 | if (fence_excl) | |
13309 | ret = fence_get_rcu(fence_excl); | |
13310 | ||
13311 | rcu_read_unlock(); | |
13312 | ||
13313 | if (ret == fence_excl) | |
13314 | return ret; | |
13315 | } | |
13316 | } | |
13317 | ||
6beb8c23 MR |
13318 | /** |
13319 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
13320 | * @plane: drm plane to prepare for | |
13321 | * @fb: framebuffer to prepare for presentation | |
13322 | * | |
13323 | * Prepares a framebuffer for usage on a display plane. Generally this | |
13324 | * involves pinning the underlying object and updating the frontbuffer tracking | |
13325 | * bits. Some older platforms need special physical address handling for | |
13326 | * cursor planes. | |
13327 | * | |
f935675f ML |
13328 | * Must be called with struct_mutex held. |
13329 | * | |
6beb8c23 MR |
13330 | * Returns 0 on success, negative error code on failure. |
13331 | */ | |
13332 | int | |
13333 | intel_prepare_plane_fb(struct drm_plane *plane, | |
d136dfee | 13334 | const struct drm_plane_state *new_state) |
465c120c MR |
13335 | { |
13336 | struct drm_device *dev = plane->dev; | |
844f9111 | 13337 | struct drm_framebuffer *fb = new_state->fb; |
6beb8c23 | 13338 | struct intel_plane *intel_plane = to_intel_plane(plane); |
6beb8c23 | 13339 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1ee49399 | 13340 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
15c86bdb | 13341 | struct drm_crtc *crtc = new_state->crtc ?: plane->state->crtc; |
6beb8c23 | 13342 | int ret = 0; |
465c120c | 13343 | |
1ee49399 | 13344 | if (!obj && !old_obj) |
465c120c MR |
13345 | return 0; |
13346 | ||
15c86bdb ML |
13347 | if (WARN_ON(!new_state->state) || WARN_ON(!crtc) || |
13348 | WARN_ON(!to_intel_atomic_state(new_state->state)->work[to_intel_crtc(crtc)->pipe])) { | |
13349 | if (WARN_ON(old_obj != obj)) | |
13350 | return -EINVAL; | |
13351 | ||
13352 | return 0; | |
13353 | } | |
13354 | ||
5008e874 ML |
13355 | if (old_obj) { |
13356 | struct drm_crtc_state *crtc_state = | |
13357 | drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc); | |
13358 | ||
13359 | /* Big Hammer, we also need to ensure that any pending | |
13360 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
13361 | * current scanout is retired before unpinning the old | |
13362 | * framebuffer. Note that we rely on userspace rendering | |
13363 | * into the buffer attached to the pipe they are waiting | |
13364 | * on. If not, userspace generates a GPU hang with IPEHR | |
13365 | * point to the MI_WAIT_FOR_EVENT. | |
13366 | * | |
13367 | * This should only fail upon a hung GPU, in which case we | |
13368 | * can safely continue. | |
13369 | */ | |
13370 | if (needs_modeset(crtc_state)) | |
13371 | ret = i915_gem_object_wait_rendering(old_obj, true); | |
f4457ae7 CW |
13372 | if (ret) { |
13373 | /* GPU hangs should have been swallowed by the wait */ | |
13374 | WARN_ON(ret == -EIO); | |
f935675f | 13375 | return ret; |
f4457ae7 | 13376 | } |
5008e874 ML |
13377 | } |
13378 | ||
1ee49399 ML |
13379 | if (!obj) { |
13380 | ret = 0; | |
13381 | } else if (plane->type == DRM_PLANE_TYPE_CURSOR && | |
6beb8c23 MR |
13382 | INTEL_INFO(dev)->cursor_needs_physical) { |
13383 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
13384 | ret = i915_gem_object_attach_phys(obj, align); | |
13385 | if (ret) | |
13386 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
13387 | } else { | |
3465c580 | 13388 | ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation); |
6beb8c23 | 13389 | } |
465c120c | 13390 | |
7580d774 ML |
13391 | if (ret == 0) { |
13392 | if (obj) { | |
13393 | struct intel_plane_state *plane_state = | |
13394 | to_intel_plane_state(new_state); | |
13395 | ||
13396 | i915_gem_request_assign(&plane_state->wait_req, | |
13397 | obj->last_write_req); | |
84fc494b ML |
13398 | |
13399 | plane_state->base.fence = intel_get_excl_fence(obj); | |
7580d774 ML |
13400 | } |
13401 | ||
a9ff8714 | 13402 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); |
7580d774 | 13403 | } |
fdd508a6 | 13404 | |
6beb8c23 MR |
13405 | return ret; |
13406 | } | |
13407 | ||
38f3ce3a MR |
13408 | /** |
13409 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
13410 | * @plane: drm plane to clean up for | |
13411 | * @fb: old framebuffer that was on plane | |
13412 | * | |
13413 | * Cleans up a framebuffer that has just been removed from a plane. | |
f935675f ML |
13414 | * |
13415 | * Must be called with struct_mutex held. | |
38f3ce3a MR |
13416 | */ |
13417 | void | |
13418 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
d136dfee | 13419 | const struct drm_plane_state *old_state) |
38f3ce3a MR |
13420 | { |
13421 | struct drm_device *dev = plane->dev; | |
1ee49399 | 13422 | struct intel_plane *intel_plane = to_intel_plane(plane); |
7580d774 | 13423 | struct intel_plane_state *old_intel_state; |
1ee49399 ML |
13424 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb); |
13425 | struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb); | |
38f3ce3a | 13426 | |
7580d774 ML |
13427 | old_intel_state = to_intel_plane_state(old_state); |
13428 | ||
1ee49399 | 13429 | if (!obj && !old_obj) |
38f3ce3a MR |
13430 | return; |
13431 | ||
1ee49399 ML |
13432 | if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR || |
13433 | !INTEL_INFO(dev)->cursor_needs_physical)) | |
3465c580 | 13434 | intel_unpin_fb_obj(old_state->fb, old_state->rotation); |
1ee49399 ML |
13435 | |
13436 | /* prepare_fb aborted? */ | |
13437 | if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) || | |
13438 | (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit))) | |
13439 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); | |
7580d774 ML |
13440 | |
13441 | i915_gem_request_assign(&old_intel_state->wait_req, NULL); | |
84fc494b ML |
13442 | |
13443 | fence_put(old_intel_state->base.fence); | |
13444 | old_intel_state->base.fence = NULL; | |
465c120c MR |
13445 | } |
13446 | ||
6156a456 CK |
13447 | int |
13448 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
13449 | { | |
13450 | int max_scale; | |
13451 | struct drm_device *dev; | |
13452 | struct drm_i915_private *dev_priv; | |
13453 | int crtc_clock, cdclk; | |
13454 | ||
bf8a0af0 | 13455 | if (!intel_crtc || !crtc_state->base.enable) |
6156a456 CK |
13456 | return DRM_PLANE_HELPER_NO_SCALING; |
13457 | ||
13458 | dev = intel_crtc->base.dev; | |
13459 | dev_priv = dev->dev_private; | |
13460 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; | |
27c329ed | 13461 | cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; |
6156a456 | 13462 | |
54bf1ce6 | 13463 | if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)) |
6156a456 CK |
13464 | return DRM_PLANE_HELPER_NO_SCALING; |
13465 | ||
13466 | /* | |
13467 | * skl max scale is lower of: | |
13468 | * close to 3 but not 3, -1 is for that purpose | |
13469 | * or | |
13470 | * cdclk/crtc_clock | |
13471 | */ | |
13472 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); | |
13473 | ||
13474 | return max_scale; | |
13475 | } | |
13476 | ||
465c120c | 13477 | static int |
3c692a41 | 13478 | intel_check_primary_plane(struct drm_plane *plane, |
061e4b8d | 13479 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
13480 | struct intel_plane_state *state) |
13481 | { | |
2b875c22 MR |
13482 | struct drm_crtc *crtc = state->base.crtc; |
13483 | struct drm_framebuffer *fb = state->base.fb; | |
6156a456 | 13484 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
13485 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
13486 | bool can_position = false; | |
465c120c | 13487 | |
693bdc28 VS |
13488 | if (INTEL_INFO(plane->dev)->gen >= 9) { |
13489 | /* use scaler when colorkey is not required */ | |
13490 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { | |
13491 | min_scale = 1; | |
13492 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
13493 | } | |
d8106366 | 13494 | can_position = true; |
6156a456 | 13495 | } |
d8106366 | 13496 | |
061e4b8d ML |
13497 | return drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
13498 | &state->dst, &state->clip, | |
da20eabd ML |
13499 | min_scale, max_scale, |
13500 | can_position, true, | |
13501 | &state->visible); | |
14af293f GP |
13502 | } |
13503 | ||
cf4c7c12 | 13504 | /** |
4a3b8769 MR |
13505 | * intel_plane_destroy - destroy a plane |
13506 | * @plane: plane to destroy | |
cf4c7c12 | 13507 | * |
4a3b8769 MR |
13508 | * Common destruction function for all types of planes (primary, cursor, |
13509 | * sprite). | |
cf4c7c12 | 13510 | */ |
4a3b8769 | 13511 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c MR |
13512 | { |
13513 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
13514 | drm_plane_cleanup(plane); | |
13515 | kfree(intel_plane); | |
13516 | } | |
13517 | ||
65a3fea0 | 13518 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
13519 | .update_plane = drm_atomic_helper_update_plane, |
13520 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 13521 | .destroy = intel_plane_destroy, |
c196e1d6 | 13522 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
13523 | .atomic_get_property = intel_plane_atomic_get_property, |
13524 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
13525 | .atomic_duplicate_state = intel_plane_duplicate_state, |
13526 | .atomic_destroy_state = intel_plane_destroy_state, | |
13527 | ||
465c120c MR |
13528 | }; |
13529 | ||
13530 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
13531 | int pipe) | |
13532 | { | |
fca0ce2a VS |
13533 | struct intel_plane *primary = NULL; |
13534 | struct intel_plane_state *state = NULL; | |
465c120c | 13535 | const uint32_t *intel_primary_formats; |
45e3743a | 13536 | unsigned int num_formats; |
fca0ce2a | 13537 | int ret; |
465c120c MR |
13538 | |
13539 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
fca0ce2a VS |
13540 | if (!primary) |
13541 | goto fail; | |
465c120c | 13542 | |
8e7d688b | 13543 | state = intel_create_plane_state(&primary->base); |
fca0ce2a VS |
13544 | if (!state) |
13545 | goto fail; | |
8e7d688b | 13546 | primary->base.state = &state->base; |
ea2c67bb | 13547 | |
465c120c MR |
13548 | primary->can_scale = false; |
13549 | primary->max_downscale = 1; | |
6156a456 CK |
13550 | if (INTEL_INFO(dev)->gen >= 9) { |
13551 | primary->can_scale = true; | |
af99ceda | 13552 | state->scaler_id = -1; |
6156a456 | 13553 | } |
465c120c MR |
13554 | primary->pipe = pipe; |
13555 | primary->plane = pipe; | |
a9ff8714 | 13556 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 | 13557 | primary->check_plane = intel_check_primary_plane; |
465c120c MR |
13558 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
13559 | primary->plane = !pipe; | |
13560 | ||
6c0fd451 DL |
13561 | if (INTEL_INFO(dev)->gen >= 9) { |
13562 | intel_primary_formats = skl_primary_formats; | |
13563 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
a8d201af ML |
13564 | |
13565 | primary->update_plane = skylake_update_primary_plane; | |
13566 | primary->disable_plane = skylake_disable_primary_plane; | |
13567 | } else if (HAS_PCH_SPLIT(dev)) { | |
13568 | intel_primary_formats = i965_primary_formats; | |
13569 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
13570 | ||
13571 | primary->update_plane = ironlake_update_primary_plane; | |
13572 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 | 13573 | } else if (INTEL_INFO(dev)->gen >= 4) { |
568db4f2 DL |
13574 | intel_primary_formats = i965_primary_formats; |
13575 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
a8d201af ML |
13576 | |
13577 | primary->update_plane = i9xx_update_primary_plane; | |
13578 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 DL |
13579 | } else { |
13580 | intel_primary_formats = i8xx_primary_formats; | |
13581 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
a8d201af ML |
13582 | |
13583 | primary->update_plane = i9xx_update_primary_plane; | |
13584 | primary->disable_plane = i9xx_disable_primary_plane; | |
465c120c MR |
13585 | } |
13586 | ||
fca0ce2a VS |
13587 | ret = drm_universal_plane_init(dev, &primary->base, 0, |
13588 | &intel_plane_funcs, | |
13589 | intel_primary_formats, num_formats, | |
13590 | DRM_PLANE_TYPE_PRIMARY, NULL); | |
13591 | if (ret) | |
13592 | goto fail; | |
48404c1e | 13593 | |
3b7a5119 SJ |
13594 | if (INTEL_INFO(dev)->gen >= 4) |
13595 | intel_create_rotation_property(dev, primary); | |
48404c1e | 13596 | |
ea2c67bb MR |
13597 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
13598 | ||
465c120c | 13599 | return &primary->base; |
fca0ce2a VS |
13600 | |
13601 | fail: | |
13602 | kfree(state); | |
13603 | kfree(primary); | |
13604 | ||
13605 | return NULL; | |
465c120c MR |
13606 | } |
13607 | ||
3b7a5119 SJ |
13608 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
13609 | { | |
13610 | if (!dev->mode_config.rotation_property) { | |
13611 | unsigned long flags = BIT(DRM_ROTATE_0) | | |
13612 | BIT(DRM_ROTATE_180); | |
13613 | ||
13614 | if (INTEL_INFO(dev)->gen >= 9) | |
13615 | flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); | |
13616 | ||
13617 | dev->mode_config.rotation_property = | |
13618 | drm_mode_create_rotation_property(dev, flags); | |
13619 | } | |
13620 | if (dev->mode_config.rotation_property) | |
13621 | drm_object_attach_property(&plane->base.base, | |
13622 | dev->mode_config.rotation_property, | |
13623 | plane->base.state->rotation); | |
13624 | } | |
13625 | ||
3d7d6510 | 13626 | static int |
852e787c | 13627 | intel_check_cursor_plane(struct drm_plane *plane, |
061e4b8d | 13628 | struct intel_crtc_state *crtc_state, |
852e787c | 13629 | struct intel_plane_state *state) |
3d7d6510 | 13630 | { |
061e4b8d | 13631 | struct drm_crtc *crtc = crtc_state->base.crtc; |
2b875c22 | 13632 | struct drm_framebuffer *fb = state->base.fb; |
757f9a3e | 13633 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
b29ec92c | 13634 | enum pipe pipe = to_intel_plane(plane)->pipe; |
757f9a3e GP |
13635 | unsigned stride; |
13636 | int ret; | |
3d7d6510 | 13637 | |
061e4b8d ML |
13638 | ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
13639 | &state->dst, &state->clip, | |
3d7d6510 MR |
13640 | DRM_PLANE_HELPER_NO_SCALING, |
13641 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 13642 | true, true, &state->visible); |
757f9a3e GP |
13643 | if (ret) |
13644 | return ret; | |
13645 | ||
757f9a3e GP |
13646 | /* if we want to turn off the cursor ignore width and height */ |
13647 | if (!obj) | |
da20eabd | 13648 | return 0; |
757f9a3e | 13649 | |
757f9a3e | 13650 | /* Check for which cursor types we support */ |
061e4b8d | 13651 | if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) { |
ea2c67bb MR |
13652 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", |
13653 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
13654 | return -EINVAL; |
13655 | } | |
13656 | ||
ea2c67bb MR |
13657 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
13658 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
13659 | DRM_DEBUG_KMS("buffer is too small\n"); |
13660 | return -ENOMEM; | |
13661 | } | |
13662 | ||
3a656b54 | 13663 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e | 13664 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
da20eabd | 13665 | return -EINVAL; |
32b7eeec MR |
13666 | } |
13667 | ||
b29ec92c VS |
13668 | /* |
13669 | * There's something wrong with the cursor on CHV pipe C. | |
13670 | * If it straddles the left edge of the screen then | |
13671 | * moving it away from the edge or disabling it often | |
13672 | * results in a pipe underrun, and often that can lead to | |
13673 | * dead pipe (constant underrun reported, and it scans | |
13674 | * out just a solid color). To recover from that, the | |
13675 | * display power well must be turned off and on again. | |
13676 | * Refuse the put the cursor into that compromised position. | |
13677 | */ | |
13678 | if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C && | |
13679 | state->visible && state->base.crtc_x < 0) { | |
13680 | DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); | |
13681 | return -EINVAL; | |
13682 | } | |
13683 | ||
da20eabd | 13684 | return 0; |
852e787c | 13685 | } |
3d7d6510 | 13686 | |
a8ad0d8e ML |
13687 | static void |
13688 | intel_disable_cursor_plane(struct drm_plane *plane, | |
7fabf5ef | 13689 | struct drm_crtc *crtc) |
a8ad0d8e | 13690 | { |
f2858021 ML |
13691 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13692 | ||
13693 | intel_crtc->cursor_addr = 0; | |
55a08b3f | 13694 | intel_crtc_update_cursor(crtc, NULL); |
a8ad0d8e ML |
13695 | } |
13696 | ||
f4a2cf29 | 13697 | static void |
55a08b3f ML |
13698 | intel_update_cursor_plane(struct drm_plane *plane, |
13699 | const struct intel_crtc_state *crtc_state, | |
13700 | const struct intel_plane_state *state) | |
852e787c | 13701 | { |
55a08b3f ML |
13702 | struct drm_crtc *crtc = crtc_state->base.crtc; |
13703 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ea2c67bb | 13704 | struct drm_device *dev = plane->dev; |
2b875c22 | 13705 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 13706 | uint32_t addr; |
852e787c | 13707 | |
f4a2cf29 | 13708 | if (!obj) |
a912f12f | 13709 | addr = 0; |
f4a2cf29 | 13710 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 13711 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 13712 | else |
a912f12f | 13713 | addr = obj->phys_handle->busaddr; |
852e787c | 13714 | |
a912f12f | 13715 | intel_crtc->cursor_addr = addr; |
55a08b3f | 13716 | intel_crtc_update_cursor(crtc, state); |
852e787c GP |
13717 | } |
13718 | ||
3d7d6510 MR |
13719 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
13720 | int pipe) | |
13721 | { | |
fca0ce2a VS |
13722 | struct intel_plane *cursor = NULL; |
13723 | struct intel_plane_state *state = NULL; | |
13724 | int ret; | |
3d7d6510 MR |
13725 | |
13726 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
fca0ce2a VS |
13727 | if (!cursor) |
13728 | goto fail; | |
3d7d6510 | 13729 | |
8e7d688b | 13730 | state = intel_create_plane_state(&cursor->base); |
fca0ce2a VS |
13731 | if (!state) |
13732 | goto fail; | |
8e7d688b | 13733 | cursor->base.state = &state->base; |
ea2c67bb | 13734 | |
3d7d6510 MR |
13735 | cursor->can_scale = false; |
13736 | cursor->max_downscale = 1; | |
13737 | cursor->pipe = pipe; | |
13738 | cursor->plane = pipe; | |
a9ff8714 | 13739 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
c59cb179 | 13740 | cursor->check_plane = intel_check_cursor_plane; |
55a08b3f | 13741 | cursor->update_plane = intel_update_cursor_plane; |
a8ad0d8e | 13742 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 | 13743 | |
fca0ce2a VS |
13744 | ret = drm_universal_plane_init(dev, &cursor->base, 0, |
13745 | &intel_plane_funcs, | |
13746 | intel_cursor_formats, | |
13747 | ARRAY_SIZE(intel_cursor_formats), | |
13748 | DRM_PLANE_TYPE_CURSOR, NULL); | |
13749 | if (ret) | |
13750 | goto fail; | |
4398ad45 VS |
13751 | |
13752 | if (INTEL_INFO(dev)->gen >= 4) { | |
13753 | if (!dev->mode_config.rotation_property) | |
13754 | dev->mode_config.rotation_property = | |
13755 | drm_mode_create_rotation_property(dev, | |
13756 | BIT(DRM_ROTATE_0) | | |
13757 | BIT(DRM_ROTATE_180)); | |
13758 | if (dev->mode_config.rotation_property) | |
13759 | drm_object_attach_property(&cursor->base.base, | |
13760 | dev->mode_config.rotation_property, | |
8e7d688b | 13761 | state->base.rotation); |
4398ad45 VS |
13762 | } |
13763 | ||
af99ceda CK |
13764 | if (INTEL_INFO(dev)->gen >=9) |
13765 | state->scaler_id = -1; | |
13766 | ||
ea2c67bb MR |
13767 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
13768 | ||
3d7d6510 | 13769 | return &cursor->base; |
fca0ce2a VS |
13770 | |
13771 | fail: | |
13772 | kfree(state); | |
13773 | kfree(cursor); | |
13774 | ||
13775 | return NULL; | |
3d7d6510 MR |
13776 | } |
13777 | ||
549e2bfb CK |
13778 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
13779 | struct intel_crtc_state *crtc_state) | |
13780 | { | |
13781 | int i; | |
13782 | struct intel_scaler *intel_scaler; | |
13783 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; | |
13784 | ||
13785 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
13786 | intel_scaler = &scaler_state->scalers[i]; | |
13787 | intel_scaler->in_use = 0; | |
549e2bfb CK |
13788 | intel_scaler->mode = PS_SCALER_MODE_DYN; |
13789 | } | |
13790 | ||
13791 | scaler_state->scaler_id = -1; | |
13792 | } | |
13793 | ||
b358d0a6 | 13794 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 13795 | { |
fbee40df | 13796 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 13797 | struct intel_crtc *intel_crtc; |
f5de6e07 | 13798 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
13799 | struct drm_plane *primary = NULL; |
13800 | struct drm_plane *cursor = NULL; | |
8563b1e8 | 13801 | int ret; |
79e53945 | 13802 | |
955382f3 | 13803 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
13804 | if (intel_crtc == NULL) |
13805 | return; | |
13806 | ||
f5de6e07 ACO |
13807 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
13808 | if (!crtc_state) | |
13809 | goto fail; | |
550acefd ACO |
13810 | intel_crtc->config = crtc_state; |
13811 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 13812 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 13813 | |
6885843a ML |
13814 | INIT_LIST_HEAD(&intel_crtc->flip_work); |
13815 | ||
549e2bfb CK |
13816 | /* initialize shared scalers */ |
13817 | if (INTEL_INFO(dev)->gen >= 9) { | |
13818 | if (pipe == PIPE_C) | |
13819 | intel_crtc->num_scalers = 1; | |
13820 | else | |
13821 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
13822 | ||
13823 | skl_init_scalers(dev, intel_crtc, crtc_state); | |
13824 | } | |
13825 | ||
465c120c | 13826 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
13827 | if (!primary) |
13828 | goto fail; | |
13829 | ||
13830 | cursor = intel_cursor_plane_create(dev, pipe); | |
13831 | if (!cursor) | |
13832 | goto fail; | |
13833 | ||
465c120c | 13834 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
f9882876 | 13835 | cursor, &intel_crtc_funcs, NULL); |
3d7d6510 MR |
13836 | if (ret) |
13837 | goto fail; | |
79e53945 | 13838 | |
1f1c2e24 VS |
13839 | /* |
13840 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 13841 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 13842 | */ |
80824003 JB |
13843 | intel_crtc->pipe = pipe; |
13844 | intel_crtc->plane = pipe; | |
3a77c4c4 | 13845 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 13846 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 13847 | intel_crtc->plane = !pipe; |
80824003 JB |
13848 | } |
13849 | ||
4b0e333e CW |
13850 | intel_crtc->cursor_base = ~0; |
13851 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 13852 | intel_crtc->cursor_size = ~0; |
8d7849db | 13853 | |
852eb00d VS |
13854 | intel_crtc->wm.cxsr_allowed = true; |
13855 | ||
22fd0fab JB |
13856 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
13857 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
13858 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
13859 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
13860 | ||
79e53945 | 13861 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 | 13862 | |
8563b1e8 LL |
13863 | intel_color_init(&intel_crtc->base); |
13864 | ||
87b6b101 | 13865 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); |
3d7d6510 MR |
13866 | return; |
13867 | ||
13868 | fail: | |
13869 | if (primary) | |
13870 | drm_plane_cleanup(primary); | |
13871 | if (cursor) | |
13872 | drm_plane_cleanup(cursor); | |
f5de6e07 | 13873 | kfree(crtc_state); |
3d7d6510 | 13874 | kfree(intel_crtc); |
79e53945 JB |
13875 | } |
13876 | ||
752aa88a JB |
13877 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
13878 | { | |
13879 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 13880 | struct drm_device *dev = connector->base.dev; |
752aa88a | 13881 | |
51fd371b | 13882 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 13883 | |
d3babd3f | 13884 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
13885 | return INVALID_PIPE; |
13886 | ||
13887 | return to_intel_crtc(encoder->crtc)->pipe; | |
13888 | } | |
13889 | ||
08d7b3d1 | 13890 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 13891 | struct drm_file *file) |
08d7b3d1 | 13892 | { |
08d7b3d1 | 13893 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 13894 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 13895 | struct intel_crtc *crtc; |
08d7b3d1 | 13896 | |
7707e653 | 13897 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 13898 | |
7707e653 | 13899 | if (!drmmode_crtc) { |
08d7b3d1 | 13900 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 13901 | return -ENOENT; |
08d7b3d1 CW |
13902 | } |
13903 | ||
7707e653 | 13904 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 13905 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 13906 | |
c05422d5 | 13907 | return 0; |
08d7b3d1 CW |
13908 | } |
13909 | ||
66a9278e | 13910 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 13911 | { |
66a9278e DV |
13912 | struct drm_device *dev = encoder->base.dev; |
13913 | struct intel_encoder *source_encoder; | |
79e53945 | 13914 | int index_mask = 0; |
79e53945 JB |
13915 | int entry = 0; |
13916 | ||
b2784e15 | 13917 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 13918 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
13919 | index_mask |= (1 << entry); |
13920 | ||
79e53945 JB |
13921 | entry++; |
13922 | } | |
4ef69c7a | 13923 | |
79e53945 JB |
13924 | return index_mask; |
13925 | } | |
13926 | ||
4d302442 CW |
13927 | static bool has_edp_a(struct drm_device *dev) |
13928 | { | |
13929 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13930 | ||
13931 | if (!IS_MOBILE(dev)) | |
13932 | return false; | |
13933 | ||
13934 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
13935 | return false; | |
13936 | ||
e3589908 | 13937 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
13938 | return false; |
13939 | ||
13940 | return true; | |
13941 | } | |
13942 | ||
84b4e042 JB |
13943 | static bool intel_crt_present(struct drm_device *dev) |
13944 | { | |
13945 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13946 | ||
884497ed DL |
13947 | if (INTEL_INFO(dev)->gen >= 9) |
13948 | return false; | |
13949 | ||
cf404ce4 | 13950 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
13951 | return false; |
13952 | ||
13953 | if (IS_CHERRYVIEW(dev)) | |
13954 | return false; | |
13955 | ||
65e472e4 VS |
13956 | if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) |
13957 | return false; | |
13958 | ||
70ac54d0 VS |
13959 | /* DDI E can't be used if DDI A requires 4 lanes */ |
13960 | if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) | |
13961 | return false; | |
13962 | ||
e4abb733 | 13963 | if (!dev_priv->vbt.int_crt_support) |
84b4e042 JB |
13964 | return false; |
13965 | ||
13966 | return true; | |
13967 | } | |
13968 | ||
79e53945 JB |
13969 | static void intel_setup_outputs(struct drm_device *dev) |
13970 | { | |
725e30ad | 13971 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 13972 | struct intel_encoder *encoder; |
cb0953d7 | 13973 | bool dpd_is_edp = false; |
79e53945 | 13974 | |
c9093354 | 13975 | intel_lvds_init(dev); |
79e53945 | 13976 | |
84b4e042 | 13977 | if (intel_crt_present(dev)) |
79935fca | 13978 | intel_crt_init(dev); |
cb0953d7 | 13979 | |
c776eb2e VK |
13980 | if (IS_BROXTON(dev)) { |
13981 | /* | |
13982 | * FIXME: Broxton doesn't support port detection via the | |
13983 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
13984 | * detect the ports. | |
13985 | */ | |
13986 | intel_ddi_init(dev, PORT_A); | |
13987 | intel_ddi_init(dev, PORT_B); | |
13988 | intel_ddi_init(dev, PORT_C); | |
c6c794a2 SS |
13989 | |
13990 | intel_dsi_init(dev); | |
c776eb2e | 13991 | } else if (HAS_DDI(dev)) { |
0e72a5b5 ED |
13992 | int found; |
13993 | ||
de31facd JB |
13994 | /* |
13995 | * Haswell uses DDI functions to detect digital outputs. | |
13996 | * On SKL pre-D0 the strap isn't connected, so we assume | |
13997 | * it's there. | |
13998 | */ | |
77179400 | 13999 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 14000 | /* WaIgnoreDDIAStrap: skl */ |
ef11bdb3 | 14001 | if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
0e72a5b5 ED |
14002 | intel_ddi_init(dev, PORT_A); |
14003 | ||
14004 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
14005 | * register */ | |
14006 | found = I915_READ(SFUSE_STRAP); | |
14007 | ||
14008 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
14009 | intel_ddi_init(dev, PORT_B); | |
14010 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
14011 | intel_ddi_init(dev, PORT_C); | |
14012 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
14013 | intel_ddi_init(dev, PORT_D); | |
2800e4c2 RV |
14014 | /* |
14015 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
14016 | */ | |
ef11bdb3 | 14017 | if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && |
2800e4c2 RV |
14018 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
14019 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
14020 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
14021 | intel_ddi_init(dev, PORT_E); | |
14022 | ||
0e72a5b5 | 14023 | } else if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 14024 | int found; |
5d8a7752 | 14025 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
14026 | |
14027 | if (has_edp_a(dev)) | |
14028 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 14029 | |
dc0fa718 | 14030 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 14031 | /* PCH SDVOB multiplex with HDMIB */ |
2a5c0832 | 14032 | found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B); |
30ad48b7 | 14033 | if (!found) |
e2debe91 | 14034 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 14035 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 14036 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
14037 | } |
14038 | ||
dc0fa718 | 14039 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 14040 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 14041 | |
dc0fa718 | 14042 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 14043 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 14044 | |
5eb08b69 | 14045 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 14046 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 14047 | |
270b3042 | 14048 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 14049 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
666a4537 | 14050 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
e17ac6db VS |
14051 | /* |
14052 | * The DP_DETECTED bit is the latched state of the DDC | |
14053 | * SDA pin at boot. However since eDP doesn't require DDC | |
14054 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
14055 | * eDP ports may have been muxed to an alternate function. | |
14056 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
14057 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
14058 | * detect eDP ports. | |
14059 | */ | |
e66eb81d | 14060 | if (I915_READ(VLV_HDMIB) & SDVO_DETECTED && |
d2182a66 | 14061 | !intel_dp_is_edp(dev, PORT_B)) |
e66eb81d VS |
14062 | intel_hdmi_init(dev, VLV_HDMIB, PORT_B); |
14063 | if (I915_READ(VLV_DP_B) & DP_DETECTED || | |
e17ac6db | 14064 | intel_dp_is_edp(dev, PORT_B)) |
e66eb81d | 14065 | intel_dp_init(dev, VLV_DP_B, PORT_B); |
585a94b8 | 14066 | |
e66eb81d | 14067 | if (I915_READ(VLV_HDMIC) & SDVO_DETECTED && |
d2182a66 | 14068 | !intel_dp_is_edp(dev, PORT_C)) |
e66eb81d VS |
14069 | intel_hdmi_init(dev, VLV_HDMIC, PORT_C); |
14070 | if (I915_READ(VLV_DP_C) & DP_DETECTED || | |
e17ac6db | 14071 | intel_dp_is_edp(dev, PORT_C)) |
e66eb81d | 14072 | intel_dp_init(dev, VLV_DP_C, PORT_C); |
19c03924 | 14073 | |
9418c1f1 | 14074 | if (IS_CHERRYVIEW(dev)) { |
e17ac6db | 14075 | /* eDP not supported on port D, so don't check VBT */ |
e66eb81d VS |
14076 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED) |
14077 | intel_hdmi_init(dev, CHV_HDMID, PORT_D); | |
14078 | if (I915_READ(CHV_DP_D) & DP_DETECTED) | |
14079 | intel_dp_init(dev, CHV_DP_D, PORT_D); | |
9418c1f1 VS |
14080 | } |
14081 | ||
3cfca973 | 14082 | intel_dsi_init(dev); |
09da55dc | 14083 | } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) { |
27185ae1 | 14084 | bool found = false; |
7d57382e | 14085 | |
e2debe91 | 14086 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14087 | DRM_DEBUG_KMS("probing SDVOB\n"); |
2a5c0832 | 14088 | found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B); |
3fec3d2f | 14089 | if (!found && IS_G4X(dev)) { |
b01f2c3a | 14090 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
e2debe91 | 14091 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 14092 | } |
27185ae1 | 14093 | |
3fec3d2f | 14094 | if (!found && IS_G4X(dev)) |
ab9d7c30 | 14095 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 14096 | } |
13520b05 KH |
14097 | |
14098 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 14099 | |
e2debe91 | 14100 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14101 | DRM_DEBUG_KMS("probing SDVOC\n"); |
2a5c0832 | 14102 | found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C); |
b01f2c3a | 14103 | } |
27185ae1 | 14104 | |
e2debe91 | 14105 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 14106 | |
3fec3d2f | 14107 | if (IS_G4X(dev)) { |
b01f2c3a | 14108 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
e2debe91 | 14109 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 14110 | } |
3fec3d2f | 14111 | if (IS_G4X(dev)) |
ab9d7c30 | 14112 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 14113 | } |
27185ae1 | 14114 | |
3fec3d2f | 14115 | if (IS_G4X(dev) && |
e7281eab | 14116 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 14117 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 14118 | } else if (IS_GEN2(dev)) |
79e53945 JB |
14119 | intel_dvo_init(dev); |
14120 | ||
103a196f | 14121 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
14122 | intel_tv_init(dev); |
14123 | ||
0bc12bcb | 14124 | intel_psr_init(dev); |
7c8f8a70 | 14125 | |
b2784e15 | 14126 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
14127 | encoder->base.possible_crtcs = encoder->crtc_mask; |
14128 | encoder->base.possible_clones = | |
66a9278e | 14129 | intel_encoder_clones(encoder); |
79e53945 | 14130 | } |
47356eb6 | 14131 | |
dde86e2d | 14132 | intel_init_pch_refclk(dev); |
270b3042 DV |
14133 | |
14134 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
14135 | } |
14136 | ||
14137 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
14138 | { | |
60a5ca01 | 14139 | struct drm_device *dev = fb->dev; |
79e53945 | 14140 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 14141 | |
ef2d633e | 14142 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 14143 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 14144 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
14145 | drm_gem_object_unreference(&intel_fb->obj->base); |
14146 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
14147 | kfree(intel_fb); |
14148 | } | |
14149 | ||
14150 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 14151 | struct drm_file *file, |
79e53945 JB |
14152 | unsigned int *handle) |
14153 | { | |
14154 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 14155 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 14156 | |
cc917ab4 CW |
14157 | if (obj->userptr.mm) { |
14158 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); | |
14159 | return -EINVAL; | |
14160 | } | |
14161 | ||
05394f39 | 14162 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
14163 | } |
14164 | ||
86c98588 RV |
14165 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
14166 | struct drm_file *file, | |
14167 | unsigned flags, unsigned color, | |
14168 | struct drm_clip_rect *clips, | |
14169 | unsigned num_clips) | |
14170 | { | |
14171 | struct drm_device *dev = fb->dev; | |
14172 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
14173 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
14174 | ||
14175 | mutex_lock(&dev->struct_mutex); | |
74b4ea1e | 14176 | intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); |
86c98588 RV |
14177 | mutex_unlock(&dev->struct_mutex); |
14178 | ||
14179 | return 0; | |
14180 | } | |
14181 | ||
79e53945 JB |
14182 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
14183 | .destroy = intel_user_framebuffer_destroy, | |
14184 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 14185 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
14186 | }; |
14187 | ||
b321803d DL |
14188 | static |
14189 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
14190 | uint32_t pixel_format) | |
14191 | { | |
14192 | u32 gen = INTEL_INFO(dev)->gen; | |
14193 | ||
14194 | if (gen >= 9) { | |
ac484963 VS |
14195 | int cpp = drm_format_plane_cpp(pixel_format, 0); |
14196 | ||
b321803d DL |
14197 | /* "The stride in bytes must not exceed the of the size of 8K |
14198 | * pixels and 32K bytes." | |
14199 | */ | |
ac484963 | 14200 | return min(8192 * cpp, 32768); |
666a4537 | 14201 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
b321803d DL |
14202 | return 32*1024; |
14203 | } else if (gen >= 4) { | |
14204 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14205 | return 16*1024; | |
14206 | else | |
14207 | return 32*1024; | |
14208 | } else if (gen >= 3) { | |
14209 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14210 | return 8*1024; | |
14211 | else | |
14212 | return 16*1024; | |
14213 | } else { | |
14214 | /* XXX DSPC is limited to 4k tiled */ | |
14215 | return 8*1024; | |
14216 | } | |
14217 | } | |
14218 | ||
b5ea642a DV |
14219 | static int intel_framebuffer_init(struct drm_device *dev, |
14220 | struct intel_framebuffer *intel_fb, | |
14221 | struct drm_mode_fb_cmd2 *mode_cmd, | |
14222 | struct drm_i915_gem_object *obj) | |
79e53945 | 14223 | { |
7b49f948 | 14224 | struct drm_i915_private *dev_priv = to_i915(dev); |
6761dd31 | 14225 | unsigned int aligned_height; |
79e53945 | 14226 | int ret; |
b321803d | 14227 | u32 pitch_limit, stride_alignment; |
79e53945 | 14228 | |
dd4916c5 DV |
14229 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
14230 | ||
2a80eada DV |
14231 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
14232 | /* Enforce that fb modifier and tiling mode match, but only for | |
14233 | * X-tiled. This is needed for FBC. */ | |
14234 | if (!!(obj->tiling_mode == I915_TILING_X) != | |
14235 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { | |
14236 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
14237 | return -EINVAL; | |
14238 | } | |
14239 | } else { | |
14240 | if (obj->tiling_mode == I915_TILING_X) | |
14241 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
14242 | else if (obj->tiling_mode == I915_TILING_Y) { | |
14243 | DRM_DEBUG("No Y tiling for legacy addfb\n"); | |
14244 | return -EINVAL; | |
14245 | } | |
14246 | } | |
14247 | ||
9a8f0a12 TU |
14248 | /* Passed in modifier sanity checking. */ |
14249 | switch (mode_cmd->modifier[0]) { | |
14250 | case I915_FORMAT_MOD_Y_TILED: | |
14251 | case I915_FORMAT_MOD_Yf_TILED: | |
14252 | if (INTEL_INFO(dev)->gen < 9) { | |
14253 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
14254 | mode_cmd->modifier[0]); | |
14255 | return -EINVAL; | |
14256 | } | |
14257 | case DRM_FORMAT_MOD_NONE: | |
14258 | case I915_FORMAT_MOD_X_TILED: | |
14259 | break; | |
14260 | default: | |
c0f40428 JB |
14261 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
14262 | mode_cmd->modifier[0]); | |
57cd6508 | 14263 | return -EINVAL; |
c16ed4be | 14264 | } |
57cd6508 | 14265 | |
7b49f948 VS |
14266 | stride_alignment = intel_fb_stride_alignment(dev_priv, |
14267 | mode_cmd->modifier[0], | |
b321803d DL |
14268 | mode_cmd->pixel_format); |
14269 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
14270 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
14271 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 14272 | return -EINVAL; |
c16ed4be | 14273 | } |
57cd6508 | 14274 | |
b321803d DL |
14275 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
14276 | mode_cmd->pixel_format); | |
a35cdaa0 | 14277 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
14278 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
14279 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 14280 | "tiled" : "linear", |
a35cdaa0 | 14281 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 14282 | return -EINVAL; |
c16ed4be | 14283 | } |
5d7bd705 | 14284 | |
2a80eada | 14285 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
c16ed4be CW |
14286 | mode_cmd->pitches[0] != obj->stride) { |
14287 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
14288 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 14289 | return -EINVAL; |
c16ed4be | 14290 | } |
5d7bd705 | 14291 | |
57779d06 | 14292 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 14293 | switch (mode_cmd->pixel_format) { |
57779d06 | 14294 | case DRM_FORMAT_C8: |
04b3924d VS |
14295 | case DRM_FORMAT_RGB565: |
14296 | case DRM_FORMAT_XRGB8888: | |
14297 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
14298 | break; |
14299 | case DRM_FORMAT_XRGB1555: | |
c16ed4be | 14300 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
14301 | DRM_DEBUG("unsupported pixel format: %s\n", |
14302 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14303 | return -EINVAL; |
c16ed4be | 14304 | } |
57779d06 | 14305 | break; |
57779d06 | 14306 | case DRM_FORMAT_ABGR8888: |
666a4537 WB |
14307 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
14308 | INTEL_INFO(dev)->gen < 9) { | |
6c0fd451 DL |
14309 | DRM_DEBUG("unsupported pixel format: %s\n", |
14310 | drm_get_format_name(mode_cmd->pixel_format)); | |
14311 | return -EINVAL; | |
14312 | } | |
14313 | break; | |
14314 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 14315 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 14316 | case DRM_FORMAT_XBGR2101010: |
c16ed4be | 14317 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
14318 | DRM_DEBUG("unsupported pixel format: %s\n", |
14319 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14320 | return -EINVAL; |
c16ed4be | 14321 | } |
b5626747 | 14322 | break; |
7531208b | 14323 | case DRM_FORMAT_ABGR2101010: |
666a4537 | 14324 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
7531208b DL |
14325 | DRM_DEBUG("unsupported pixel format: %s\n", |
14326 | drm_get_format_name(mode_cmd->pixel_format)); | |
14327 | return -EINVAL; | |
14328 | } | |
14329 | break; | |
04b3924d VS |
14330 | case DRM_FORMAT_YUYV: |
14331 | case DRM_FORMAT_UYVY: | |
14332 | case DRM_FORMAT_YVYU: | |
14333 | case DRM_FORMAT_VYUY: | |
c16ed4be | 14334 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
14335 | DRM_DEBUG("unsupported pixel format: %s\n", |
14336 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14337 | return -EINVAL; |
c16ed4be | 14338 | } |
57cd6508 CW |
14339 | break; |
14340 | default: | |
4ee62c76 VS |
14341 | DRM_DEBUG("unsupported pixel format: %s\n", |
14342 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
14343 | return -EINVAL; |
14344 | } | |
14345 | ||
90f9a336 VS |
14346 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
14347 | if (mode_cmd->offsets[0] != 0) | |
14348 | return -EINVAL; | |
14349 | ||
ec2c981e | 14350 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
091df6cb DV |
14351 | mode_cmd->pixel_format, |
14352 | mode_cmd->modifier[0]); | |
53155c0a DV |
14353 | /* FIXME drm helper for size checks (especially planar formats)? */ |
14354 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
14355 | return -EINVAL; | |
14356 | ||
c7d73f6a DV |
14357 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
14358 | intel_fb->obj = obj; | |
14359 | ||
2d7a215f VS |
14360 | intel_fill_fb_info(dev_priv, &intel_fb->base); |
14361 | ||
79e53945 JB |
14362 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
14363 | if (ret) { | |
14364 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
14365 | return ret; | |
14366 | } | |
14367 | ||
0b05e1e0 VS |
14368 | intel_fb->obj->framebuffer_references++; |
14369 | ||
79e53945 JB |
14370 | return 0; |
14371 | } | |
14372 | ||
79e53945 JB |
14373 | static struct drm_framebuffer * |
14374 | intel_user_framebuffer_create(struct drm_device *dev, | |
14375 | struct drm_file *filp, | |
1eb83451 | 14376 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
79e53945 | 14377 | { |
dcb1394e | 14378 | struct drm_framebuffer *fb; |
05394f39 | 14379 | struct drm_i915_gem_object *obj; |
76dc3769 | 14380 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
79e53945 | 14381 | |
308e5bcb | 14382 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
76dc3769 | 14383 | mode_cmd.handles[0])); |
c8725226 | 14384 | if (&obj->base == NULL) |
cce13ff7 | 14385 | return ERR_PTR(-ENOENT); |
79e53945 | 14386 | |
92907cbb | 14387 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
dcb1394e LW |
14388 | if (IS_ERR(fb)) |
14389 | drm_gem_object_unreference_unlocked(&obj->base); | |
14390 | ||
14391 | return fb; | |
79e53945 JB |
14392 | } |
14393 | ||
0695726e | 14394 | #ifndef CONFIG_DRM_FBDEV_EMULATION |
0632fef6 | 14395 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
14396 | { |
14397 | } | |
14398 | #endif | |
14399 | ||
79e53945 | 14400 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 14401 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 14402 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
14403 | .atomic_check = intel_atomic_check, |
14404 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
14405 | .atomic_state_alloc = intel_atomic_state_alloc, |
14406 | .atomic_state_clear = intel_atomic_state_clear, | |
79e53945 JB |
14407 | }; |
14408 | ||
88212941 ID |
14409 | /** |
14410 | * intel_init_display_hooks - initialize the display modesetting hooks | |
14411 | * @dev_priv: device private | |
14412 | */ | |
14413 | void intel_init_display_hooks(struct drm_i915_private *dev_priv) | |
e70236a8 | 14414 | { |
88212941 | 14415 | if (INTEL_INFO(dev_priv)->gen >= 9) { |
bc8d7dff | 14416 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14417 | dev_priv->display.get_initial_plane_config = |
14418 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
14419 | dev_priv->display.crtc_compute_clock = |
14420 | haswell_crtc_compute_clock; | |
14421 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
14422 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 14423 | } else if (HAS_DDI(dev_priv)) { |
0e8ffe1b | 14424 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14425 | dev_priv->display.get_initial_plane_config = |
14426 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
14427 | dev_priv->display.crtc_compute_clock = |
14428 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
14429 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
14430 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 14431 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
0e8ffe1b | 14432 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
14433 | dev_priv->display.get_initial_plane_config = |
14434 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
14435 | dev_priv->display.crtc_compute_clock = |
14436 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
14437 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
14438 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
65b3d6a9 | 14439 | } else if (IS_CHERRYVIEW(dev_priv)) { |
89b667f8 | 14440 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14441 | dev_priv->display.get_initial_plane_config = |
14442 | i9xx_get_initial_plane_config; | |
65b3d6a9 ACO |
14443 | dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock; |
14444 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
14445 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
14446 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
14447 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14448 | dev_priv->display.get_initial_plane_config = | |
14449 | i9xx_get_initial_plane_config; | |
14450 | dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock; | |
89b667f8 JB |
14451 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
14452 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
19ec6693 ACO |
14453 | } else if (IS_G4X(dev_priv)) { |
14454 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14455 | dev_priv->display.get_initial_plane_config = | |
14456 | i9xx_get_initial_plane_config; | |
14457 | dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock; | |
14458 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
14459 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
70e8aa21 ACO |
14460 | } else if (IS_PINEVIEW(dev_priv)) { |
14461 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14462 | dev_priv->display.get_initial_plane_config = | |
14463 | i9xx_get_initial_plane_config; | |
14464 | dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock; | |
14465 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
14466 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 | 14467 | } else if (!IS_GEN2(dev_priv)) { |
0e8ffe1b | 14468 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14469 | dev_priv->display.get_initial_plane_config = |
14470 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14471 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
14472 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
14473 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 ACO |
14474 | } else { |
14475 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14476 | dev_priv->display.get_initial_plane_config = | |
14477 | i9xx_get_initial_plane_config; | |
14478 | dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock; | |
14479 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
14480 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 14481 | } |
e70236a8 | 14482 | |
e70236a8 | 14483 | /* Returns the core display clock speed */ |
88212941 | 14484 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
1652d19e VS |
14485 | dev_priv->display.get_display_clock_speed = |
14486 | skylake_get_display_clock_speed; | |
88212941 | 14487 | else if (IS_BROXTON(dev_priv)) |
acd3f3d3 BP |
14488 | dev_priv->display.get_display_clock_speed = |
14489 | broxton_get_display_clock_speed; | |
88212941 | 14490 | else if (IS_BROADWELL(dev_priv)) |
1652d19e VS |
14491 | dev_priv->display.get_display_clock_speed = |
14492 | broadwell_get_display_clock_speed; | |
88212941 | 14493 | else if (IS_HASWELL(dev_priv)) |
1652d19e VS |
14494 | dev_priv->display.get_display_clock_speed = |
14495 | haswell_get_display_clock_speed; | |
88212941 | 14496 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
25eb05fc JB |
14497 | dev_priv->display.get_display_clock_speed = |
14498 | valleyview_get_display_clock_speed; | |
88212941 | 14499 | else if (IS_GEN5(dev_priv)) |
b37a6434 VS |
14500 | dev_priv->display.get_display_clock_speed = |
14501 | ilk_get_display_clock_speed; | |
88212941 ID |
14502 | else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) || |
14503 | IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) | |
e70236a8 JB |
14504 | dev_priv->display.get_display_clock_speed = |
14505 | i945_get_display_clock_speed; | |
88212941 | 14506 | else if (IS_GM45(dev_priv)) |
34edce2f VS |
14507 | dev_priv->display.get_display_clock_speed = |
14508 | gm45_get_display_clock_speed; | |
88212941 | 14509 | else if (IS_CRESTLINE(dev_priv)) |
34edce2f VS |
14510 | dev_priv->display.get_display_clock_speed = |
14511 | i965gm_get_display_clock_speed; | |
88212941 | 14512 | else if (IS_PINEVIEW(dev_priv)) |
34edce2f VS |
14513 | dev_priv->display.get_display_clock_speed = |
14514 | pnv_get_display_clock_speed; | |
88212941 | 14515 | else if (IS_G33(dev_priv) || IS_G4X(dev_priv)) |
34edce2f VS |
14516 | dev_priv->display.get_display_clock_speed = |
14517 | g33_get_display_clock_speed; | |
88212941 | 14518 | else if (IS_I915G(dev_priv)) |
e70236a8 JB |
14519 | dev_priv->display.get_display_clock_speed = |
14520 | i915_get_display_clock_speed; | |
88212941 | 14521 | else if (IS_I945GM(dev_priv) || IS_845G(dev_priv)) |
e70236a8 JB |
14522 | dev_priv->display.get_display_clock_speed = |
14523 | i9xx_misc_get_display_clock_speed; | |
88212941 | 14524 | else if (IS_I915GM(dev_priv)) |
e70236a8 JB |
14525 | dev_priv->display.get_display_clock_speed = |
14526 | i915gm_get_display_clock_speed; | |
88212941 | 14527 | else if (IS_I865G(dev_priv)) |
e70236a8 JB |
14528 | dev_priv->display.get_display_clock_speed = |
14529 | i865_get_display_clock_speed; | |
88212941 | 14530 | else if (IS_I85X(dev_priv)) |
e70236a8 | 14531 | dev_priv->display.get_display_clock_speed = |
1b1d2716 | 14532 | i85x_get_display_clock_speed; |
623e01e5 | 14533 | else { /* 830 */ |
88212941 | 14534 | WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n"); |
e70236a8 JB |
14535 | dev_priv->display.get_display_clock_speed = |
14536 | i830_get_display_clock_speed; | |
623e01e5 | 14537 | } |
e70236a8 | 14538 | |
88212941 | 14539 | if (IS_GEN5(dev_priv)) { |
3bb11b53 | 14540 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
88212941 | 14541 | } else if (IS_GEN6(dev_priv)) { |
3bb11b53 | 14542 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
88212941 | 14543 | } else if (IS_IVYBRIDGE(dev_priv)) { |
3bb11b53 SJ |
14544 | /* FIXME: detect B0+ stepping and use auto training */ |
14545 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
88212941 | 14546 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
3bb11b53 | 14547 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
445e780b VS |
14548 | } |
14549 | ||
14550 | if (IS_BROADWELL(dev_priv)) { | |
14551 | dev_priv->display.modeset_commit_cdclk = | |
14552 | broadwell_modeset_commit_cdclk; | |
14553 | dev_priv->display.modeset_calc_cdclk = | |
14554 | broadwell_modeset_calc_cdclk; | |
88212941 | 14555 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
27c329ed ML |
14556 | dev_priv->display.modeset_commit_cdclk = |
14557 | valleyview_modeset_commit_cdclk; | |
14558 | dev_priv->display.modeset_calc_cdclk = | |
14559 | valleyview_modeset_calc_cdclk; | |
88212941 | 14560 | } else if (IS_BROXTON(dev_priv)) { |
27c329ed ML |
14561 | dev_priv->display.modeset_commit_cdclk = |
14562 | broxton_modeset_commit_cdclk; | |
14563 | dev_priv->display.modeset_calc_cdclk = | |
14564 | broxton_modeset_calc_cdclk; | |
c89e39f3 CT |
14565 | } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { |
14566 | dev_priv->display.modeset_commit_cdclk = | |
14567 | skl_modeset_commit_cdclk; | |
14568 | dev_priv->display.modeset_calc_cdclk = | |
14569 | skl_modeset_calc_cdclk; | |
e70236a8 JB |
14570 | } |
14571 | } | |
14572 | ||
b690e96c JB |
14573 | /* |
14574 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
14575 | * resume, or other times. This quirk makes sure that's the case for | |
14576 | * affected systems. | |
14577 | */ | |
0206e353 | 14578 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
14579 | { |
14580 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14581 | ||
14582 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 14583 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
14584 | } |
14585 | ||
b6b5d049 VS |
14586 | static void quirk_pipeb_force(struct drm_device *dev) |
14587 | { | |
14588 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14589 | ||
14590 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
14591 | DRM_INFO("applying pipe b force quirk\n"); | |
14592 | } | |
14593 | ||
435793df KP |
14594 | /* |
14595 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
14596 | */ | |
14597 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
14598 | { | |
14599 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14600 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 14601 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
14602 | } |
14603 | ||
4dca20ef | 14604 | /* |
5a15ab5b CE |
14605 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
14606 | * brightness value | |
4dca20ef CE |
14607 | */ |
14608 | static void quirk_invert_brightness(struct drm_device *dev) | |
14609 | { | |
14610 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14611 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 14612 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
14613 | } |
14614 | ||
9c72cc6f SD |
14615 | /* Some VBT's incorrectly indicate no backlight is present */ |
14616 | static void quirk_backlight_present(struct drm_device *dev) | |
14617 | { | |
14618 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14619 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
14620 | DRM_INFO("applying backlight present quirk\n"); | |
14621 | } | |
14622 | ||
b690e96c JB |
14623 | struct intel_quirk { |
14624 | int device; | |
14625 | int subsystem_vendor; | |
14626 | int subsystem_device; | |
14627 | void (*hook)(struct drm_device *dev); | |
14628 | }; | |
14629 | ||
5f85f176 EE |
14630 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
14631 | struct intel_dmi_quirk { | |
14632 | void (*hook)(struct drm_device *dev); | |
14633 | const struct dmi_system_id (*dmi_id_list)[]; | |
14634 | }; | |
14635 | ||
14636 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
14637 | { | |
14638 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
14639 | return 1; | |
14640 | } | |
14641 | ||
14642 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
14643 | { | |
14644 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
14645 | { | |
14646 | .callback = intel_dmi_reverse_brightness, | |
14647 | .ident = "NCR Corporation", | |
14648 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
14649 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
14650 | }, | |
14651 | }, | |
14652 | { } /* terminating entry */ | |
14653 | }, | |
14654 | .hook = quirk_invert_brightness, | |
14655 | }, | |
14656 | }; | |
14657 | ||
c43b5634 | 14658 | static struct intel_quirk intel_quirks[] = { |
b690e96c JB |
14659 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
14660 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
14661 | ||
b690e96c JB |
14662 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
14663 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
14664 | ||
5f080c0f VS |
14665 | /* 830 needs to leave pipe A & dpll A up */ |
14666 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
14667 | ||
b6b5d049 VS |
14668 | /* 830 needs to leave pipe B & dpll B up */ |
14669 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
14670 | ||
435793df KP |
14671 | /* Lenovo U160 cannot use SSC on LVDS */ |
14672 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
14673 | |
14674 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
14675 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 14676 | |
be505f64 AH |
14677 | /* Acer Aspire 5734Z must invert backlight brightness */ |
14678 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
14679 | ||
14680 | /* Acer/eMachines G725 */ | |
14681 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
14682 | ||
14683 | /* Acer/eMachines e725 */ | |
14684 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
14685 | ||
14686 | /* Acer/Packard Bell NCL20 */ | |
14687 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
14688 | ||
14689 | /* Acer Aspire 4736Z */ | |
14690 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
14691 | |
14692 | /* Acer Aspire 5336 */ | |
14693 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
14694 | |
14695 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
14696 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 14697 | |
dfb3d47b SD |
14698 | /* Acer C720 Chromebook (Core i3 4005U) */ |
14699 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
14700 | ||
b2a9601c | 14701 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
14702 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
14703 | ||
1b9448b0 JN |
14704 | /* Apple Macbook 4,1 */ |
14705 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, | |
14706 | ||
d4967d8c SD |
14707 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
14708 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
14709 | |
14710 | /* HP Chromebook 14 (Celeron 2955U) */ | |
14711 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
14712 | |
14713 | /* Dell Chromebook 11 */ | |
14714 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
9be64eee JN |
14715 | |
14716 | /* Dell Chromebook 11 (2015 version) */ | |
14717 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
14718 | }; |
14719 | ||
14720 | static void intel_init_quirks(struct drm_device *dev) | |
14721 | { | |
14722 | struct pci_dev *d = dev->pdev; | |
14723 | int i; | |
14724 | ||
14725 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
14726 | struct intel_quirk *q = &intel_quirks[i]; | |
14727 | ||
14728 | if (d->device == q->device && | |
14729 | (d->subsystem_vendor == q->subsystem_vendor || | |
14730 | q->subsystem_vendor == PCI_ANY_ID) && | |
14731 | (d->subsystem_device == q->subsystem_device || | |
14732 | q->subsystem_device == PCI_ANY_ID)) | |
14733 | q->hook(dev); | |
14734 | } | |
5f85f176 EE |
14735 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
14736 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
14737 | intel_dmi_quirks[i].hook(dev); | |
14738 | } | |
b690e96c JB |
14739 | } |
14740 | ||
9cce37f4 JB |
14741 | /* Disable the VGA plane that we never use */ |
14742 | static void i915_disable_vga(struct drm_device *dev) | |
14743 | { | |
14744 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14745 | u8 sr1; | |
f0f59a00 | 14746 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 14747 | |
2b37c616 | 14748 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 14749 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 14750 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
14751 | sr1 = inb(VGA_SR_DATA); |
14752 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
14753 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
14754 | udelay(300); | |
14755 | ||
01f5a626 | 14756 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
14757 | POSTING_READ(vga_reg); |
14758 | } | |
14759 | ||
f817586c DV |
14760 | void intel_modeset_init_hw(struct drm_device *dev) |
14761 | { | |
1a617b77 ML |
14762 | struct drm_i915_private *dev_priv = dev->dev_private; |
14763 | ||
b6283055 | 14764 | intel_update_cdclk(dev); |
1a617b77 ML |
14765 | |
14766 | dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq; | |
14767 | ||
f817586c | 14768 | intel_init_clock_gating(dev); |
dc97997a | 14769 | intel_enable_gt_powersave(dev_priv); |
f817586c DV |
14770 | } |
14771 | ||
d93c0372 MR |
14772 | /* |
14773 | * Calculate what we think the watermarks should be for the state we've read | |
14774 | * out of the hardware and then immediately program those watermarks so that | |
14775 | * we ensure the hardware settings match our internal state. | |
14776 | * | |
14777 | * We can calculate what we think WM's should be by creating a duplicate of the | |
14778 | * current state (which was constructed during hardware readout) and running it | |
14779 | * through the atomic check code to calculate new watermark values in the | |
14780 | * state object. | |
14781 | */ | |
14782 | static void sanitize_watermarks(struct drm_device *dev) | |
14783 | { | |
14784 | struct drm_i915_private *dev_priv = to_i915(dev); | |
14785 | struct drm_atomic_state *state; | |
14786 | struct drm_crtc *crtc; | |
14787 | struct drm_crtc_state *cstate; | |
14788 | struct drm_modeset_acquire_ctx ctx; | |
14789 | int ret; | |
14790 | int i; | |
14791 | ||
14792 | /* Only supported on platforms that use atomic watermark design */ | |
ed4a6a7c | 14793 | if (!dev_priv->display.optimize_watermarks) |
d93c0372 MR |
14794 | return; |
14795 | ||
14796 | /* | |
14797 | * We need to hold connection_mutex before calling duplicate_state so | |
14798 | * that the connector loop is protected. | |
14799 | */ | |
14800 | drm_modeset_acquire_init(&ctx, 0); | |
14801 | retry: | |
0cd1262d | 14802 | ret = drm_modeset_lock_all_ctx(dev, &ctx); |
d93c0372 MR |
14803 | if (ret == -EDEADLK) { |
14804 | drm_modeset_backoff(&ctx); | |
14805 | goto retry; | |
14806 | } else if (WARN_ON(ret)) { | |
0cd1262d | 14807 | goto fail; |
d93c0372 MR |
14808 | } |
14809 | ||
14810 | state = drm_atomic_helper_duplicate_state(dev, &ctx); | |
14811 | if (WARN_ON(IS_ERR(state))) | |
0cd1262d | 14812 | goto fail; |
d93c0372 | 14813 | |
ed4a6a7c MR |
14814 | /* |
14815 | * Hardware readout is the only time we don't want to calculate | |
14816 | * intermediate watermarks (since we don't trust the current | |
14817 | * watermarks). | |
14818 | */ | |
14819 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
14820 | ||
d93c0372 MR |
14821 | ret = intel_atomic_check(dev, state); |
14822 | if (ret) { | |
14823 | /* | |
14824 | * If we fail here, it means that the hardware appears to be | |
14825 | * programmed in a way that shouldn't be possible, given our | |
14826 | * understanding of watermark requirements. This might mean a | |
14827 | * mistake in the hardware readout code or a mistake in the | |
14828 | * watermark calculations for a given platform. Raise a WARN | |
14829 | * so that this is noticeable. | |
14830 | * | |
14831 | * If this actually happens, we'll have to just leave the | |
14832 | * BIOS-programmed watermarks untouched and hope for the best. | |
14833 | */ | |
14834 | WARN(true, "Could not determine valid watermarks for inherited state\n"); | |
0cd1262d | 14835 | goto fail; |
d93c0372 MR |
14836 | } |
14837 | ||
14838 | /* Write calculated watermark values back */ | |
d93c0372 MR |
14839 | for_each_crtc_in_state(state, crtc, cstate, i) { |
14840 | struct intel_crtc_state *cs = to_intel_crtc_state(cstate); | |
14841 | ||
ed4a6a7c MR |
14842 | cs->wm.need_postvbl_update = true; |
14843 | dev_priv->display.optimize_watermarks(cs); | |
d93c0372 MR |
14844 | } |
14845 | ||
14846 | drm_atomic_state_free(state); | |
0cd1262d | 14847 | fail: |
d93c0372 MR |
14848 | drm_modeset_drop_locks(&ctx); |
14849 | drm_modeset_acquire_fini(&ctx); | |
14850 | } | |
14851 | ||
79e53945 JB |
14852 | void intel_modeset_init(struct drm_device *dev) |
14853 | { | |
72e96d64 JL |
14854 | struct drm_i915_private *dev_priv = to_i915(dev); |
14855 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
1fe47785 | 14856 | int sprite, ret; |
8cc87b75 | 14857 | enum pipe pipe; |
46f297fb | 14858 | struct intel_crtc *crtc; |
79e53945 JB |
14859 | |
14860 | drm_mode_config_init(dev); | |
14861 | ||
14862 | dev->mode_config.min_width = 0; | |
14863 | dev->mode_config.min_height = 0; | |
14864 | ||
019d96cb DA |
14865 | dev->mode_config.preferred_depth = 24; |
14866 | dev->mode_config.prefer_shadow = 1; | |
14867 | ||
25bab385 TU |
14868 | dev->mode_config.allow_fb_modifiers = true; |
14869 | ||
e6ecefaa | 14870 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 14871 | |
b690e96c JB |
14872 | intel_init_quirks(dev); |
14873 | ||
1fa61106 ED |
14874 | intel_init_pm(dev); |
14875 | ||
e3c74757 BW |
14876 | if (INTEL_INFO(dev)->num_pipes == 0) |
14877 | return; | |
14878 | ||
69f92f67 LW |
14879 | /* |
14880 | * There may be no VBT; and if the BIOS enabled SSC we can | |
14881 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
14882 | * BIOS isn't using it, don't assume it will work even if the VBT | |
14883 | * indicates as much. | |
14884 | */ | |
14885 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { | |
14886 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
14887 | DREF_SSC1_ENABLE); | |
14888 | ||
14889 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
14890 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
14891 | bios_lvds_use_ssc ? "en" : "dis", | |
14892 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
14893 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
14894 | } | |
14895 | } | |
14896 | ||
a6c45cf0 CW |
14897 | if (IS_GEN2(dev)) { |
14898 | dev->mode_config.max_width = 2048; | |
14899 | dev->mode_config.max_height = 2048; | |
14900 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
14901 | dev->mode_config.max_width = 4096; |
14902 | dev->mode_config.max_height = 4096; | |
79e53945 | 14903 | } else { |
a6c45cf0 CW |
14904 | dev->mode_config.max_width = 8192; |
14905 | dev->mode_config.max_height = 8192; | |
79e53945 | 14906 | } |
068be561 | 14907 | |
dc41c154 VS |
14908 | if (IS_845G(dev) || IS_I865G(dev)) { |
14909 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
14910 | dev->mode_config.cursor_height = 1023; | |
14911 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
14912 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
14913 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
14914 | } else { | |
14915 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
14916 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
14917 | } | |
14918 | ||
72e96d64 | 14919 | dev->mode_config.fb_base = ggtt->mappable_base; |
79e53945 | 14920 | |
28c97730 | 14921 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
14922 | INTEL_INFO(dev)->num_pipes, |
14923 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 14924 | |
055e393f | 14925 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 14926 | intel_crtc_init(dev, pipe); |
3bdcfc0c | 14927 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 14928 | ret = intel_plane_init(dev, pipe, sprite); |
7f1f3851 | 14929 | if (ret) |
06da8da2 | 14930 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 14931 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 14932 | } |
79e53945 JB |
14933 | } |
14934 | ||
bfa7df01 VS |
14935 | intel_update_czclk(dev_priv); |
14936 | intel_update_cdclk(dev); | |
14937 | ||
e72f9fbf | 14938 | intel_shared_dpll_init(dev); |
ee7b9f93 | 14939 | |
b2045352 VS |
14940 | if (dev_priv->max_cdclk_freq == 0) |
14941 | intel_update_max_cdclk(dev); | |
14942 | ||
9cce37f4 JB |
14943 | /* Just disable it once at startup */ |
14944 | i915_disable_vga(dev); | |
79e53945 | 14945 | intel_setup_outputs(dev); |
11be49eb | 14946 | |
6e9f798d | 14947 | drm_modeset_lock_all(dev); |
043e9bda | 14948 | intel_modeset_setup_hw_state(dev); |
6e9f798d | 14949 | drm_modeset_unlock_all(dev); |
46f297fb | 14950 | |
d3fcc808 | 14951 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
14952 | struct intel_initial_plane_config plane_config = {}; |
14953 | ||
46f297fb JB |
14954 | if (!crtc->active) |
14955 | continue; | |
14956 | ||
46f297fb | 14957 | /* |
46f297fb JB |
14958 | * Note that reserving the BIOS fb up front prevents us |
14959 | * from stuffing other stolen allocations like the ring | |
14960 | * on top. This prevents some ugliness at boot time, and | |
14961 | * can even allow for smooth boot transitions if the BIOS | |
14962 | * fb is large enough for the active pipe configuration. | |
14963 | */ | |
eeebeac5 ML |
14964 | dev_priv->display.get_initial_plane_config(crtc, |
14965 | &plane_config); | |
14966 | ||
14967 | /* | |
14968 | * If the fb is shared between multiple heads, we'll | |
14969 | * just get the first one. | |
14970 | */ | |
14971 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 14972 | } |
d93c0372 MR |
14973 | |
14974 | /* | |
14975 | * Make sure hardware watermarks really match the state we read out. | |
14976 | * Note that we need to do this after reconstructing the BIOS fb's | |
14977 | * since the watermark calculation done here will use pstate->fb. | |
14978 | */ | |
14979 | sanitize_watermarks(dev); | |
2c7111db CW |
14980 | } |
14981 | ||
7fad798e DV |
14982 | static void intel_enable_pipe_a(struct drm_device *dev) |
14983 | { | |
14984 | struct intel_connector *connector; | |
14985 | struct drm_connector *crt = NULL; | |
14986 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 14987 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
14988 | |
14989 | /* We can't just switch on the pipe A, we need to set things up with a | |
14990 | * proper mode and output configuration. As a gross hack, enable pipe A | |
14991 | * by enabling the load detect pipe once. */ | |
3a3371ff | 14992 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
14993 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
14994 | crt = &connector->base; | |
14995 | break; | |
14996 | } | |
14997 | } | |
14998 | ||
14999 | if (!crt) | |
15000 | return; | |
15001 | ||
208bf9fd | 15002 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 15003 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
15004 | } |
15005 | ||
fa555837 DV |
15006 | static bool |
15007 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
15008 | { | |
7eb552ae BW |
15009 | struct drm_device *dev = crtc->base.dev; |
15010 | struct drm_i915_private *dev_priv = dev->dev_private; | |
649636ef | 15011 | u32 val; |
fa555837 | 15012 | |
7eb552ae | 15013 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
15014 | return true; |
15015 | ||
649636ef | 15016 | val = I915_READ(DSPCNTR(!crtc->plane)); |
fa555837 DV |
15017 | |
15018 | if ((val & DISPLAY_PLANE_ENABLE) && | |
15019 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
15020 | return false; | |
15021 | ||
15022 | return true; | |
15023 | } | |
15024 | ||
02e93c35 VS |
15025 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
15026 | { | |
15027 | struct drm_device *dev = crtc->base.dev; | |
15028 | struct intel_encoder *encoder; | |
15029 | ||
15030 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
15031 | return true; | |
15032 | ||
15033 | return false; | |
15034 | } | |
15035 | ||
dd756198 VS |
15036 | static bool intel_encoder_has_connectors(struct intel_encoder *encoder) |
15037 | { | |
15038 | struct drm_device *dev = encoder->base.dev; | |
15039 | struct intel_connector *connector; | |
15040 | ||
15041 | for_each_connector_on_encoder(dev, &encoder->base, connector) | |
15042 | return true; | |
15043 | ||
15044 | return false; | |
15045 | } | |
15046 | ||
24929352 DV |
15047 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
15048 | { | |
15049 | struct drm_device *dev = crtc->base.dev; | |
15050 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4d1de975 | 15051 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
24929352 | 15052 | |
24929352 | 15053 | /* Clear any frame start delays used for debugging left by the BIOS */ |
4d1de975 JN |
15054 | if (!transcoder_is_dsi(cpu_transcoder)) { |
15055 | i915_reg_t reg = PIPECONF(cpu_transcoder); | |
15056 | ||
15057 | I915_WRITE(reg, | |
15058 | I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); | |
15059 | } | |
24929352 | 15060 | |
d3eaf884 | 15061 | /* restore vblank interrupts to correct state */ |
9625604c | 15062 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 15063 | if (crtc->active) { |
f9cd7b88 VS |
15064 | struct intel_plane *plane; |
15065 | ||
9625604c | 15066 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
15067 | |
15068 | /* Disable everything but the primary plane */ | |
15069 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
15070 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
15071 | continue; | |
15072 | ||
15073 | plane->disable_plane(&plane->base, &crtc->base); | |
15074 | } | |
9625604c | 15075 | } |
d3eaf884 | 15076 | |
24929352 | 15077 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
15078 | * disable the crtc (and hence change the state) if it is wrong. Note |
15079 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
15080 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
15081 | bool plane; |
15082 | ||
24929352 DV |
15083 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
15084 | crtc->base.base.id); | |
15085 | ||
15086 | /* Pipe has the wrong plane attached and the plane is active. | |
15087 | * Temporarily change the plane mapping and disable everything | |
15088 | * ... */ | |
15089 | plane = crtc->plane; | |
b70709a6 | 15090 | to_intel_plane_state(crtc->base.primary->state)->visible = true; |
24929352 | 15091 | crtc->plane = !plane; |
b17d48e2 | 15092 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15093 | crtc->plane = plane; |
24929352 | 15094 | } |
24929352 | 15095 | |
7fad798e DV |
15096 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
15097 | crtc->pipe == PIPE_A && !crtc->active) { | |
15098 | /* BIOS forgot to enable pipe A, this mostly happens after | |
15099 | * resume. Force-enable the pipe to fix this, the update_dpms | |
15100 | * call below we restore the pipe to the right state, but leave | |
15101 | * the required bits on. */ | |
15102 | intel_enable_pipe_a(dev); | |
15103 | } | |
15104 | ||
24929352 DV |
15105 | /* Adjust the state of the output pipe according to whether we |
15106 | * have active connectors/encoders. */ | |
842e0307 | 15107 | if (crtc->active && !intel_crtc_has_encoders(crtc)) |
b17d48e2 | 15108 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15109 | |
a3ed6aad | 15110 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
15111 | /* |
15112 | * We start out with underrun reporting disabled to avoid races. | |
15113 | * For correct bookkeeping mark this on active crtcs. | |
15114 | * | |
c5ab3bc0 DV |
15115 | * Also on gmch platforms we dont have any hardware bits to |
15116 | * disable the underrun reporting. Which means we need to start | |
15117 | * out with underrun reporting disabled also on inactive pipes, | |
15118 | * since otherwise we'll complain about the garbage we read when | |
15119 | * e.g. coming up after runtime pm. | |
15120 | * | |
4cc31489 DV |
15121 | * No protection against concurrent access is required - at |
15122 | * worst a fifo underrun happens which also sets this to false. | |
15123 | */ | |
15124 | crtc->cpu_fifo_underrun_disabled = true; | |
15125 | crtc->pch_fifo_underrun_disabled = true; | |
15126 | } | |
24929352 DV |
15127 | } |
15128 | ||
15129 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
15130 | { | |
15131 | struct intel_connector *connector; | |
15132 | struct drm_device *dev = encoder->base.dev; | |
15133 | ||
15134 | /* We need to check both for a crtc link (meaning that the | |
15135 | * encoder is active and trying to read from a pipe) and the | |
15136 | * pipe itself being active. */ | |
15137 | bool has_active_crtc = encoder->base.crtc && | |
15138 | to_intel_crtc(encoder->base.crtc)->active; | |
15139 | ||
dd756198 | 15140 | if (intel_encoder_has_connectors(encoder) && !has_active_crtc) { |
24929352 DV |
15141 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
15142 | encoder->base.base.id, | |
8e329a03 | 15143 | encoder->base.name); |
24929352 DV |
15144 | |
15145 | /* Connector is active, but has no active pipe. This is | |
15146 | * fallout from our resume register restoring. Disable | |
15147 | * the encoder manually again. */ | |
15148 | if (encoder->base.crtc) { | |
15149 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
15150 | encoder->base.base.id, | |
8e329a03 | 15151 | encoder->base.name); |
24929352 | 15152 | encoder->disable(encoder); |
a62d1497 VS |
15153 | if (encoder->post_disable) |
15154 | encoder->post_disable(encoder); | |
24929352 | 15155 | } |
7f1950fb | 15156 | encoder->base.crtc = NULL; |
24929352 DV |
15157 | |
15158 | /* Inconsistent output/port/pipe state happens presumably due to | |
15159 | * a bug in one of the get_hw_state functions. Or someplace else | |
15160 | * in our code, like the register restore mess on resume. Clamp | |
15161 | * things to off as a safer default. */ | |
3a3371ff | 15162 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15163 | if (connector->encoder != encoder) |
15164 | continue; | |
7f1950fb EE |
15165 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
15166 | connector->base.encoder = NULL; | |
24929352 DV |
15167 | } |
15168 | } | |
15169 | /* Enabled encoders without active connectors will be fixed in | |
15170 | * the crtc fixup. */ | |
15171 | } | |
15172 | ||
04098753 | 15173 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
15174 | { |
15175 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 15176 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 15177 | |
04098753 ID |
15178 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
15179 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
15180 | i915_disable_vga(dev); | |
15181 | } | |
15182 | } | |
15183 | ||
15184 | void i915_redisable_vga(struct drm_device *dev) | |
15185 | { | |
15186 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15187 | ||
8dc8a27c PZ |
15188 | /* This function can be called both from intel_modeset_setup_hw_state or |
15189 | * at a very early point in our resume sequence, where the power well | |
15190 | * structures are not yet restored. Since this function is at a very | |
15191 | * paranoid "someone might have enabled VGA while we were not looking" | |
15192 | * level, just check if the power well is enabled instead of trying to | |
15193 | * follow the "don't touch the power well if we don't need it" policy | |
15194 | * the rest of the driver uses. */ | |
6392f847 | 15195 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
15196 | return; |
15197 | ||
04098753 | 15198 | i915_redisable_vga_power_on(dev); |
6392f847 ID |
15199 | |
15200 | intel_display_power_put(dev_priv, POWER_DOMAIN_VGA); | |
0fde901f KM |
15201 | } |
15202 | ||
f9cd7b88 | 15203 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 15204 | { |
f9cd7b88 | 15205 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 15206 | |
f9cd7b88 | 15207 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
15208 | } |
15209 | ||
f9cd7b88 VS |
15210 | /* FIXME read out full plane state for all planes */ |
15211 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 15212 | { |
b26d3ea3 | 15213 | struct drm_plane *primary = crtc->base.primary; |
f9cd7b88 | 15214 | struct intel_plane_state *plane_state = |
b26d3ea3 | 15215 | to_intel_plane_state(primary->state); |
d032ffa0 | 15216 | |
19b8d387 | 15217 | plane_state->visible = crtc->active && |
b26d3ea3 ML |
15218 | primary_get_hw_state(to_intel_plane(primary)); |
15219 | ||
15220 | if (plane_state->visible) | |
15221 | crtc->base.state->plane_mask |= 1 << drm_plane_index(primary); | |
98ec7739 VS |
15222 | } |
15223 | ||
30e984df | 15224 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
15225 | { |
15226 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15227 | enum pipe pipe; | |
24929352 DV |
15228 | struct intel_crtc *crtc; |
15229 | struct intel_encoder *encoder; | |
15230 | struct intel_connector *connector; | |
5358901f | 15231 | int i; |
24929352 | 15232 | |
565602d7 ML |
15233 | dev_priv->active_crtcs = 0; |
15234 | ||
d3fcc808 | 15235 | for_each_intel_crtc(dev, crtc) { |
565602d7 ML |
15236 | struct intel_crtc_state *crtc_state = crtc->config; |
15237 | int pixclk = 0; | |
3b117c8f | 15238 | |
565602d7 ML |
15239 | __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base); |
15240 | memset(crtc_state, 0, sizeof(*crtc_state)); | |
15241 | crtc_state->base.crtc = &crtc->base; | |
24929352 | 15242 | |
565602d7 ML |
15243 | crtc_state->base.active = crtc_state->base.enable = |
15244 | dev_priv->display.get_pipe_config(crtc, crtc_state); | |
15245 | ||
15246 | crtc->base.enabled = crtc_state->base.enable; | |
15247 | crtc->active = crtc_state->base.active; | |
15248 | ||
15249 | if (crtc_state->base.active) { | |
15250 | dev_priv->active_crtcs |= 1 << crtc->pipe; | |
15251 | ||
c89e39f3 | 15252 | if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) |
565602d7 | 15253 | pixclk = ilk_pipe_pixel_rate(crtc_state); |
9558d15d | 15254 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
565602d7 ML |
15255 | pixclk = crtc_state->base.adjusted_mode.crtc_clock; |
15256 | else | |
15257 | WARN_ON(dev_priv->display.modeset_calc_cdclk); | |
9558d15d VS |
15258 | |
15259 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
15260 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) | |
15261 | pixclk = DIV_ROUND_UP(pixclk * 100, 95); | |
565602d7 ML |
15262 | } |
15263 | ||
15264 | dev_priv->min_pixclk[crtc->pipe] = pixclk; | |
b70709a6 | 15265 | |
f9cd7b88 | 15266 | readout_plane_state(crtc); |
24929352 DV |
15267 | |
15268 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
15269 | crtc->base.base.id, | |
15270 | crtc->active ? "enabled" : "disabled"); | |
15271 | } | |
15272 | ||
5358901f DV |
15273 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15274 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15275 | ||
2edd6443 ACO |
15276 | pll->on = pll->funcs.get_hw_state(dev_priv, pll, |
15277 | &pll->config.hw_state); | |
3e369b76 | 15278 | pll->config.crtc_mask = 0; |
d3fcc808 | 15279 | for_each_intel_crtc(dev, crtc) { |
2dd66ebd | 15280 | if (crtc->active && crtc->config->shared_dpll == pll) |
3e369b76 | 15281 | pll->config.crtc_mask |= 1 << crtc->pipe; |
5358901f | 15282 | } |
2dd66ebd | 15283 | pll->active_mask = pll->config.crtc_mask; |
5358901f | 15284 | |
1e6f2ddc | 15285 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 15286 | pll->name, pll->config.crtc_mask, pll->on); |
5358901f DV |
15287 | } |
15288 | ||
b2784e15 | 15289 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15290 | pipe = 0; |
15291 | ||
15292 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
15293 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15294 | encoder->base.crtc = &crtc->base; | |
6e3c9717 | 15295 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
15296 | } else { |
15297 | encoder->base.crtc = NULL; | |
15298 | } | |
15299 | ||
6f2bcceb | 15300 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 15301 | encoder->base.base.id, |
8e329a03 | 15302 | encoder->base.name, |
24929352 | 15303 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 15304 | pipe_name(pipe)); |
24929352 DV |
15305 | } |
15306 | ||
3a3371ff | 15307 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15308 | if (connector->get_hw_state(connector)) { |
15309 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
2aa974c9 ML |
15310 | |
15311 | encoder = connector->encoder; | |
15312 | connector->base.encoder = &encoder->base; | |
15313 | ||
15314 | if (encoder->base.crtc && | |
15315 | encoder->base.crtc->state->active) { | |
15316 | /* | |
15317 | * This has to be done during hardware readout | |
15318 | * because anything calling .crtc_disable may | |
15319 | * rely on the connector_mask being accurate. | |
15320 | */ | |
15321 | encoder->base.crtc->state->connector_mask |= | |
15322 | 1 << drm_connector_index(&connector->base); | |
e87a52b3 ML |
15323 | encoder->base.crtc->state->encoder_mask |= |
15324 | 1 << drm_encoder_index(&encoder->base); | |
2aa974c9 ML |
15325 | } |
15326 | ||
24929352 DV |
15327 | } else { |
15328 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
15329 | connector->base.encoder = NULL; | |
15330 | } | |
15331 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
15332 | connector->base.base.id, | |
c23cc417 | 15333 | connector->base.name, |
24929352 DV |
15334 | connector->base.encoder ? "enabled" : "disabled"); |
15335 | } | |
7f4c6284 VS |
15336 | |
15337 | for_each_intel_crtc(dev, crtc) { | |
15338 | crtc->base.hwmode = crtc->config->base.adjusted_mode; | |
15339 | ||
15340 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); | |
15341 | if (crtc->base.state->active) { | |
15342 | intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); | |
15343 | intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config); | |
15344 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); | |
15345 | ||
15346 | /* | |
15347 | * The initial mode needs to be set in order to keep | |
15348 | * the atomic core happy. It wants a valid mode if the | |
15349 | * crtc's enabled, so we do the above call. | |
15350 | * | |
15351 | * At this point some state updated by the connectors | |
15352 | * in their ->detect() callback has not run yet, so | |
15353 | * no recalculation can be done yet. | |
15354 | * | |
15355 | * Even if we could do a recalculation and modeset | |
15356 | * right now it would cause a double modeset if | |
15357 | * fbdev or userspace chooses a different initial mode. | |
15358 | * | |
15359 | * If that happens, someone indicated they wanted a | |
15360 | * mode change, which means it's safe to do a full | |
15361 | * recalculation. | |
15362 | */ | |
15363 | crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED; | |
9eca6832 VS |
15364 | |
15365 | drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); | |
15366 | update_scanline_offset(crtc); | |
7f4c6284 | 15367 | } |
e3b247da VS |
15368 | |
15369 | intel_pipe_config_sanity_check(dev_priv, crtc->config); | |
7f4c6284 | 15370 | } |
30e984df DV |
15371 | } |
15372 | ||
043e9bda ML |
15373 | /* Scan out the current hw modeset state, |
15374 | * and sanitizes it to the current state | |
15375 | */ | |
15376 | static void | |
15377 | intel_modeset_setup_hw_state(struct drm_device *dev) | |
30e984df DV |
15378 | { |
15379 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15380 | enum pipe pipe; | |
30e984df DV |
15381 | struct intel_crtc *crtc; |
15382 | struct intel_encoder *encoder; | |
35c95375 | 15383 | int i; |
30e984df DV |
15384 | |
15385 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
15386 | |
15387 | /* HW state is read out, now we need to sanitize this mess. */ | |
b2784e15 | 15388 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15389 | intel_sanitize_encoder(encoder); |
15390 | } | |
15391 | ||
055e393f | 15392 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
15393 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15394 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
15395 | intel_dump_pipe_config(crtc, crtc->config, |
15396 | "[setup_hw_state]"); | |
24929352 | 15397 | } |
9a935856 | 15398 | |
d29b2f9d ACO |
15399 | intel_modeset_update_connector_atomic_state(dev); |
15400 | ||
35c95375 DV |
15401 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15402 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15403 | ||
2dd66ebd | 15404 | if (!pll->on || pll->active_mask) |
35c95375 DV |
15405 | continue; |
15406 | ||
15407 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
15408 | ||
2edd6443 | 15409 | pll->funcs.disable(dev_priv, pll); |
35c95375 DV |
15410 | pll->on = false; |
15411 | } | |
15412 | ||
666a4537 | 15413 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
6eb1a681 VS |
15414 | vlv_wm_get_hw_state(dev); |
15415 | else if (IS_GEN9(dev)) | |
3078999f PB |
15416 | skl_wm_get_hw_state(dev); |
15417 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 | 15418 | ilk_wm_get_hw_state(dev); |
292b990e ML |
15419 | |
15420 | for_each_intel_crtc(dev, crtc) { | |
15421 | unsigned long put_domains; | |
15422 | ||
74bff5f9 | 15423 | put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config); |
292b990e ML |
15424 | if (WARN_ON(put_domains)) |
15425 | modeset_put_power_domains(dev_priv, put_domains); | |
15426 | } | |
15427 | intel_display_set_init_power(dev_priv, false); | |
010cf73d PZ |
15428 | |
15429 | intel_fbc_init_pipe_state(dev_priv); | |
043e9bda | 15430 | } |
7d0bc1ea | 15431 | |
043e9bda ML |
15432 | void intel_display_resume(struct drm_device *dev) |
15433 | { | |
e2c8b870 ML |
15434 | struct drm_i915_private *dev_priv = to_i915(dev); |
15435 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
15436 | struct drm_modeset_acquire_ctx ctx; | |
043e9bda | 15437 | int ret; |
e2c8b870 | 15438 | bool setup = false; |
f30da187 | 15439 | |
e2c8b870 | 15440 | dev_priv->modeset_restore_state = NULL; |
043e9bda | 15441 | |
ea49c9ac ML |
15442 | /* |
15443 | * This is a cludge because with real atomic modeset mode_config.mutex | |
15444 | * won't be taken. Unfortunately some probed state like | |
15445 | * audio_codec_enable is still protected by mode_config.mutex, so lock | |
15446 | * it here for now. | |
15447 | */ | |
15448 | mutex_lock(&dev->mode_config.mutex); | |
e2c8b870 | 15449 | drm_modeset_acquire_init(&ctx, 0); |
043e9bda | 15450 | |
e2c8b870 ML |
15451 | retry: |
15452 | ret = drm_modeset_lock_all_ctx(dev, &ctx); | |
043e9bda | 15453 | |
e2c8b870 ML |
15454 | if (ret == 0 && !setup) { |
15455 | setup = true; | |
043e9bda | 15456 | |
e2c8b870 ML |
15457 | intel_modeset_setup_hw_state(dev); |
15458 | i915_redisable_vga(dev); | |
45e2b5f6 | 15459 | } |
8af6cf88 | 15460 | |
e2c8b870 ML |
15461 | if (ret == 0 && state) { |
15462 | struct drm_crtc_state *crtc_state; | |
15463 | struct drm_crtc *crtc; | |
15464 | int i; | |
043e9bda | 15465 | |
e2c8b870 ML |
15466 | state->acquire_ctx = &ctx; |
15467 | ||
e3d5457c VS |
15468 | /* ignore any reset values/BIOS leftovers in the WM registers */ |
15469 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
15470 | ||
e2c8b870 ML |
15471 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
15472 | /* | |
15473 | * Force recalculation even if we restore | |
15474 | * current state. With fast modeset this may not result | |
15475 | * in a modeset when the state is compatible. | |
15476 | */ | |
15477 | crtc_state->mode_changed = true; | |
15478 | } | |
15479 | ||
15480 | ret = drm_atomic_commit(state); | |
043e9bda ML |
15481 | } |
15482 | ||
e2c8b870 ML |
15483 | if (ret == -EDEADLK) { |
15484 | drm_modeset_backoff(&ctx); | |
15485 | goto retry; | |
15486 | } | |
043e9bda | 15487 | |
e2c8b870 ML |
15488 | drm_modeset_drop_locks(&ctx); |
15489 | drm_modeset_acquire_fini(&ctx); | |
ea49c9ac | 15490 | mutex_unlock(&dev->mode_config.mutex); |
043e9bda | 15491 | |
e2c8b870 ML |
15492 | if (ret) { |
15493 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
15494 | drm_atomic_state_free(state); | |
15495 | } | |
2c7111db CW |
15496 | } |
15497 | ||
15498 | void intel_modeset_gem_init(struct drm_device *dev) | |
15499 | { | |
dc97997a | 15500 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd | 15501 | struct drm_crtc *c; |
2ff8fde1 | 15502 | struct drm_i915_gem_object *obj; |
e0d6149b | 15503 | int ret; |
484b41dd | 15504 | |
dc97997a | 15505 | intel_init_gt_powersave(dev_priv); |
ae48434c | 15506 | |
1833b134 | 15507 | intel_modeset_init_hw(dev); |
02e792fb | 15508 | |
1ee8da6d | 15509 | intel_setup_overlay(dev_priv); |
484b41dd JB |
15510 | |
15511 | /* | |
15512 | * Make sure any fbs we allocated at startup are properly | |
15513 | * pinned & fenced. When we do the allocation it's too early | |
15514 | * for this. | |
15515 | */ | |
70e1e0ec | 15516 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
15517 | obj = intel_fb_obj(c->primary->fb); |
15518 | if (obj == NULL) | |
484b41dd JB |
15519 | continue; |
15520 | ||
e0d6149b | 15521 | mutex_lock(&dev->struct_mutex); |
3465c580 VS |
15522 | ret = intel_pin_and_fence_fb_obj(c->primary->fb, |
15523 | c->primary->state->rotation); | |
e0d6149b TU |
15524 | mutex_unlock(&dev->struct_mutex); |
15525 | if (ret) { | |
484b41dd JB |
15526 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
15527 | to_intel_crtc(c)->pipe); | |
66e514c1 | 15528 | drm_framebuffer_unreference(c->primary->fb); |
143f73b3 ML |
15529 | drm_framebuffer_unreference(c->primary->state->fb); |
15530 | c->primary->fb = c->primary->state->fb = NULL; | |
36750f28 | 15531 | c->primary->crtc = c->primary->state->crtc = NULL; |
36750f28 | 15532 | c->state->plane_mask &= ~(1 << drm_plane_index(c->primary)); |
484b41dd JB |
15533 | } |
15534 | } | |
0962c3c9 VS |
15535 | |
15536 | intel_backlight_register(dev); | |
79e53945 JB |
15537 | } |
15538 | ||
4932e2c3 ID |
15539 | void intel_connector_unregister(struct intel_connector *intel_connector) |
15540 | { | |
15541 | struct drm_connector *connector = &intel_connector->base; | |
15542 | ||
15543 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 15544 | drm_connector_unregister(connector); |
4932e2c3 ID |
15545 | } |
15546 | ||
79e53945 JB |
15547 | void intel_modeset_cleanup(struct drm_device *dev) |
15548 | { | |
652c393a | 15549 | struct drm_i915_private *dev_priv = dev->dev_private; |
19c8054c | 15550 | struct intel_connector *connector; |
652c393a | 15551 | |
dc97997a | 15552 | intel_disable_gt_powersave(dev_priv); |
2eb5252e | 15553 | |
0962c3c9 VS |
15554 | intel_backlight_unregister(dev); |
15555 | ||
fd0c0642 DV |
15556 | /* |
15557 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 15558 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
15559 | * experience fancy races otherwise. |
15560 | */ | |
2aeb7d3a | 15561 | intel_irq_uninstall(dev_priv); |
eb21b92b | 15562 | |
fd0c0642 DV |
15563 | /* |
15564 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
15565 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
15566 | */ | |
f87ea761 | 15567 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 15568 | |
723bfd70 JB |
15569 | intel_unregister_dsm_handler(); |
15570 | ||
c937ab3e | 15571 | intel_fbc_global_disable(dev_priv); |
69341a5e | 15572 | |
1630fe75 CW |
15573 | /* flush any delayed tasks or pending work */ |
15574 | flush_scheduled_work(); | |
15575 | ||
db31af1d | 15576 | /* destroy the backlight and sysfs files before encoders/connectors */ |
19c8054c JN |
15577 | for_each_intel_connector(dev, connector) |
15578 | connector->unregister(connector); | |
d9255d57 | 15579 | |
79e53945 | 15580 | drm_mode_config_cleanup(dev); |
4d7bb011 | 15581 | |
1ee8da6d | 15582 | intel_cleanup_overlay(dev_priv); |
ae48434c | 15583 | |
dc97997a | 15584 | intel_cleanup_gt_powersave(dev_priv); |
f5949141 DV |
15585 | |
15586 | intel_teardown_gmbus(dev); | |
79e53945 JB |
15587 | } |
15588 | ||
f1c79df3 ZW |
15589 | /* |
15590 | * Return which encoder is currently attached for connector. | |
15591 | */ | |
df0e9248 | 15592 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 15593 | { |
df0e9248 CW |
15594 | return &intel_attached_encoder(connector)->base; |
15595 | } | |
f1c79df3 | 15596 | |
df0e9248 CW |
15597 | void intel_connector_attach_encoder(struct intel_connector *connector, |
15598 | struct intel_encoder *encoder) | |
15599 | { | |
15600 | connector->encoder = encoder; | |
15601 | drm_mode_connector_attach_encoder(&connector->base, | |
15602 | &encoder->base); | |
79e53945 | 15603 | } |
28d52043 DA |
15604 | |
15605 | /* | |
15606 | * set vga decode state - true == enable VGA decode | |
15607 | */ | |
15608 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
15609 | { | |
15610 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 15611 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
15612 | u16 gmch_ctrl; |
15613 | ||
75fa041d CW |
15614 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
15615 | DRM_ERROR("failed to read control word\n"); | |
15616 | return -EIO; | |
15617 | } | |
15618 | ||
c0cc8a55 CW |
15619 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
15620 | return 0; | |
15621 | ||
28d52043 DA |
15622 | if (state) |
15623 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
15624 | else | |
15625 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
15626 | |
15627 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
15628 | DRM_ERROR("failed to write control word\n"); | |
15629 | return -EIO; | |
15630 | } | |
15631 | ||
28d52043 DA |
15632 | return 0; |
15633 | } | |
c4a1d9e4 | 15634 | |
c4a1d9e4 | 15635 | struct intel_display_error_state { |
ff57f1b0 PZ |
15636 | |
15637 | u32 power_well_driver; | |
15638 | ||
63b66e5b CW |
15639 | int num_transcoders; |
15640 | ||
c4a1d9e4 CW |
15641 | struct intel_cursor_error_state { |
15642 | u32 control; | |
15643 | u32 position; | |
15644 | u32 base; | |
15645 | u32 size; | |
52331309 | 15646 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15647 | |
15648 | struct intel_pipe_error_state { | |
ddf9c536 | 15649 | bool power_domain_on; |
c4a1d9e4 | 15650 | u32 source; |
f301b1e1 | 15651 | u32 stat; |
52331309 | 15652 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15653 | |
15654 | struct intel_plane_error_state { | |
15655 | u32 control; | |
15656 | u32 stride; | |
15657 | u32 size; | |
15658 | u32 pos; | |
15659 | u32 addr; | |
15660 | u32 surface; | |
15661 | u32 tile_offset; | |
52331309 | 15662 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
15663 | |
15664 | struct intel_transcoder_error_state { | |
ddf9c536 | 15665 | bool power_domain_on; |
63b66e5b CW |
15666 | enum transcoder cpu_transcoder; |
15667 | ||
15668 | u32 conf; | |
15669 | ||
15670 | u32 htotal; | |
15671 | u32 hblank; | |
15672 | u32 hsync; | |
15673 | u32 vtotal; | |
15674 | u32 vblank; | |
15675 | u32 vsync; | |
15676 | } transcoder[4]; | |
c4a1d9e4 CW |
15677 | }; |
15678 | ||
15679 | struct intel_display_error_state * | |
c033666a | 15680 | intel_display_capture_error_state(struct drm_i915_private *dev_priv) |
c4a1d9e4 | 15681 | { |
c4a1d9e4 | 15682 | struct intel_display_error_state *error; |
63b66e5b CW |
15683 | int transcoders[] = { |
15684 | TRANSCODER_A, | |
15685 | TRANSCODER_B, | |
15686 | TRANSCODER_C, | |
15687 | TRANSCODER_EDP, | |
15688 | }; | |
c4a1d9e4 CW |
15689 | int i; |
15690 | ||
c033666a | 15691 | if (INTEL_INFO(dev_priv)->num_pipes == 0) |
63b66e5b CW |
15692 | return NULL; |
15693 | ||
9d1cb914 | 15694 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
15695 | if (error == NULL) |
15696 | return NULL; | |
15697 | ||
c033666a | 15698 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
ff57f1b0 PZ |
15699 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
15700 | ||
055e393f | 15701 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 15702 | error->pipe[i].power_domain_on = |
f458ebbc DV |
15703 | __intel_display_power_is_enabled(dev_priv, |
15704 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 15705 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
15706 | continue; |
15707 | ||
5efb3e28 VS |
15708 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
15709 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
15710 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
15711 | |
15712 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
15713 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
c033666a | 15714 | if (INTEL_GEN(dev_priv) <= 3) { |
51889b35 | 15715 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
15716 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
15717 | } | |
c033666a | 15718 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
ca291363 | 15719 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
c033666a | 15720 | if (INTEL_GEN(dev_priv) >= 4) { |
c4a1d9e4 CW |
15721 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
15722 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
15723 | } | |
15724 | ||
c4a1d9e4 | 15725 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 15726 | |
c033666a | 15727 | if (HAS_GMCH_DISPLAY(dev_priv)) |
f301b1e1 | 15728 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
15729 | } |
15730 | ||
4d1de975 | 15731 | /* Note: this does not include DSI transcoders. */ |
c033666a | 15732 | error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes; |
2d1fe073 | 15733 | if (HAS_DDI(dev_priv)) |
63b66e5b CW |
15734 | error->num_transcoders++; /* Account for eDP. */ |
15735 | ||
15736 | for (i = 0; i < error->num_transcoders; i++) { | |
15737 | enum transcoder cpu_transcoder = transcoders[i]; | |
15738 | ||
ddf9c536 | 15739 | error->transcoder[i].power_domain_on = |
f458ebbc | 15740 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 15741 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 15742 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
15743 | continue; |
15744 | ||
63b66e5b CW |
15745 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
15746 | ||
15747 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
15748 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
15749 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
15750 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
15751 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
15752 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
15753 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
15754 | } |
15755 | ||
15756 | return error; | |
15757 | } | |
15758 | ||
edc3d884 MK |
15759 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
15760 | ||
c4a1d9e4 | 15761 | void |
edc3d884 | 15762 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
15763 | struct drm_device *dev, |
15764 | struct intel_display_error_state *error) | |
15765 | { | |
055e393f | 15766 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
15767 | int i; |
15768 | ||
63b66e5b CW |
15769 | if (!error) |
15770 | return; | |
15771 | ||
edc3d884 | 15772 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 15773 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 15774 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 15775 | error->power_well_driver); |
055e393f | 15776 | for_each_pipe(dev_priv, i) { |
edc3d884 | 15777 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 | 15778 | err_printf(m, " Power: %s\n", |
87ad3212 | 15779 | onoff(error->pipe[i].power_domain_on)); |
edc3d884 | 15780 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 15781 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
15782 | |
15783 | err_printf(m, "Plane [%d]:\n", i); | |
15784 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
15785 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 15786 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
15787 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
15788 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 15789 | } |
4b71a570 | 15790 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 15791 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 15792 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
15793 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
15794 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
15795 | } |
15796 | ||
edc3d884 MK |
15797 | err_printf(m, "Cursor [%d]:\n", i); |
15798 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
15799 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
15800 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 15801 | } |
63b66e5b CW |
15802 | |
15803 | for (i = 0; i < error->num_transcoders; i++) { | |
da205630 | 15804 | err_printf(m, "CPU transcoder: %s\n", |
63b66e5b | 15805 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 | 15806 | err_printf(m, " Power: %s\n", |
87ad3212 | 15807 | onoff(error->transcoder[i].power_domain_on)); |
63b66e5b CW |
15808 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
15809 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
15810 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
15811 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
15812 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
15813 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
15814 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
15815 | } | |
c4a1d9e4 | 15816 | } |