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drm/i915: don't assert_pch_pll_enabled on lpt_enable_pch_transcoder
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 47static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 48static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 49
50typedef struct {
0206e353
AJ		 51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
79e53945
JB		 60} intel_clock_t;
61
62typedef struct {
0206e353 63 int min, max;
79e53945
JB		 64} intel_range_t;
65
66typedef struct {
0206e353
AJ		 67 int dot_limit;
68 int p2_slow, p2_fast;
79e53945
JB		 69} intel_p2_t;
70
71#define INTEL_P2_NUM 2
d4906093
ML		 72typedef struct intel_limit intel_limit_t;
73struct intel_limit {
0206e353
AJ		 74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 77 int, int, intel_clock_t *, intel_clock_t *);
d4906093 78};
79e53945 79
2377b741
JB		 80/* FDI */
81#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
d2acd215
DV		 83int
84intel_pch_rawclk(struct drm_device *dev)
85{
86 struct drm_i915_private *dev_priv = dev->dev_private;
87
88 WARN_ON(!HAS_PCH_SPLIT(dev));
89
90 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
91}
92
d4906093
ML		 93static bool
94intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 95 int target, int refclk, intel_clock_t *match_clock,
96 intel_clock_t *best_clock);
d4906093
ML		 97static bool
98intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 99 int target, int refclk, intel_clock_t *match_clock,
100 intel_clock_t *best_clock);
79e53945 101
a4fc5ed6
KP		 102static bool
103intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 104 int target, int refclk, intel_clock_t *match_clock,
105 intel_clock_t *best_clock);
5eb08b69 106static bool
f2b115e6 107intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 108 int target, int refclk, intel_clock_t *match_clock,
109 intel_clock_t *best_clock);
a4fc5ed6 110
a0c4da24
JB		 111static bool
112intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
113 int target, int refclk, intel_clock_t *match_clock,
114 intel_clock_t *best_clock);
115
021357ac
CW		 116static inline u32 /* units of 100MHz */
117intel_fdi_link_freq(struct drm_device *dev)
118{
8b99e68c
CW		 119 if (IS_GEN5(dev)) {
120 struct drm_i915_private *dev_priv = dev->dev_private;
121 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
122 } else
123 return 27;
021357ac
CW		 124}
125
e4b36699 126static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 127 .dot = { .min = 25000, .max = 350000 },
128 .vco = { .min = 930000, .max = 1400000 },
129 .n = { .min = 3, .max = 16 },
130 .m = { .min = 96, .max = 140 },
131 .m1 = { .min = 18, .max = 26 },
132 .m2 = { .min = 6, .max = 16 },
133 .p = { .min = 4, .max = 128 },
134 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 135 .p2 = { .dot_limit = 165000,
136 .p2_slow = 4, .p2_fast = 2 },
d4906093 137 .find_pll = intel_find_best_PLL,
e4b36699
KP		 138};
139
140static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 141 .dot = { .min = 25000, .max = 350000 },
142 .vco = { .min = 930000, .max = 1400000 },
143 .n = { .min = 3, .max = 16 },
144 .m = { .min = 96, .max = 140 },
145 .m1 = { .min = 18, .max = 26 },
146 .m2 = { .min = 6, .max = 16 },
147 .p = { .min = 4, .max = 128 },
148 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 149 .p2 = { .dot_limit = 165000,
150 .p2_slow = 14, .p2_fast = 7 },
d4906093 151 .find_pll = intel_find_best_PLL,
e4b36699 152};
273e27ca 153
e4b36699 154static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 155 .dot = { .min = 20000, .max = 400000 },
156 .vco = { .min = 1400000, .max = 2800000 },
157 .n = { .min = 1, .max = 6 },
158 .m = { .min = 70, .max = 120 },
159 .m1 = { .min = 10, .max = 22 },
160 .m2 = { .min = 5, .max = 9 },
161 .p = { .min = 5, .max = 80 },
162 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 163 .p2 = { .dot_limit = 200000,
164 .p2_slow = 10, .p2_fast = 5 },
d4906093 165 .find_pll = intel_find_best_PLL,
e4b36699
KP		 166};
167
168static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 169 .dot = { .min = 20000, .max = 400000 },
170 .vco = { .min = 1400000, .max = 2800000 },
171 .n = { .min = 1, .max = 6 },
172 .m = { .min = 70, .max = 120 },
173 .m1 = { .min = 10, .max = 22 },
174 .m2 = { .min = 5, .max = 9 },
175 .p = { .min = 7, .max = 98 },
176 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 177 .p2 = { .dot_limit = 112000,
178 .p2_slow = 14, .p2_fast = 7 },
d4906093 179 .find_pll = intel_find_best_PLL,
e4b36699
KP		 180};
181
273e27ca 182
e4b36699 183static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 184 .dot = { .min = 25000, .max = 270000 },
185 .vco = { .min = 1750000, .max = 3500000},
186 .n = { .min = 1, .max = 4 },
187 .m = { .min = 104, .max = 138 },
188 .m1 = { .min = 17, .max = 23 },
189 .m2 = { .min = 5, .max = 11 },
190 .p = { .min = 10, .max = 30 },
191 .p1 = { .min = 1, .max = 3},
192 .p2 = { .dot_limit = 270000,
193 .p2_slow = 10,
194 .p2_fast = 10
044c7c41 195 },
d4906093 196 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 197};
198
199static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 200 .dot = { .min = 22000, .max = 400000 },
201 .vco = { .min = 1750000, .max = 3500000},
202 .n = { .min = 1, .max = 4 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 16, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 5, .max = 80 },
207 .p1 = { .min = 1, .max = 8},
208 .p2 = { .dot_limit = 165000,
209 .p2_slow = 10, .p2_fast = 5 },
d4906093 210 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 211};
212
213static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 214 .dot = { .min = 20000, .max = 115000 },
215 .vco = { .min = 1750000, .max = 3500000 },
216 .n = { .min = 1, .max = 3 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 17, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 28, .max = 112 },
221 .p1 = { .min = 2, .max = 8 },
222 .p2 = { .dot_limit = 0,
223 .p2_slow = 14, .p2_fast = 14
044c7c41 224 },
d4906093 225 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 226};
227
228static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 229 .dot = { .min = 80000, .max = 224000 },
230 .vco = { .min = 1750000, .max = 3500000 },
231 .n = { .min = 1, .max = 3 },
232 .m = { .min = 104, .max = 138 },
233 .m1 = { .min = 17, .max = 23 },
234 .m2 = { .min = 5, .max = 11 },
235 .p = { .min = 14, .max = 42 },
236 .p1 = { .min = 2, .max = 6 },
237 .p2 = { .dot_limit = 0,
238 .p2_slow = 7, .p2_fast = 7
044c7c41 239 },
d4906093 240 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 241};
242
243static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 244 .dot = { .min = 161670, .max = 227000 },
245 .vco = { .min = 1750000, .max = 3500000},
246 .n = { .min = 1, .max = 2 },
247 .m = { .min = 97, .max = 108 },
248 .m1 = { .min = 0x10, .max = 0x12 },
249 .m2 = { .min = 0x05, .max = 0x06 },
250 .p = { .min = 10, .max = 20 },
251 .p1 = { .min = 1, .max = 2},
252 .p2 = { .dot_limit = 0,
273e27ca 253 .p2_slow = 10, .p2_fast = 10 },
0206e353 254 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 255};
256
f2b115e6 257static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 258 .dot = { .min = 20000, .max = 400000},
259 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 260 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 261 .n = { .min = 3, .max = 6 },
262 .m = { .min = 2, .max = 256 },
273e27ca 263 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 264 .m1 = { .min = 0, .max = 0 },
265 .m2 = { .min = 0, .max = 254 },
266 .p = { .min = 5, .max = 80 },
267 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 268 .p2 = { .dot_limit = 200000,
269 .p2_slow = 10, .p2_fast = 5 },
6115707b 270 .find_pll = intel_find_best_PLL,
e4b36699
KP		 271};
272
f2b115e6 273static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 274 .dot = { .min = 20000, .max = 400000 },
275 .vco = { .min = 1700000, .max = 3500000 },
276 .n = { .min = 3, .max = 6 },
277 .m = { .min = 2, .max = 256 },
278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 7, .max = 112 },
281 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 282 .p2 = { .dot_limit = 112000,
283 .p2_slow = 14, .p2_fast = 14 },
6115707b 284 .find_pll = intel_find_best_PLL,
e4b36699
KP		 285};
286
273e27ca
EA		 287/* Ironlake / Sandybridge
288 *
289 * We calculate clock using (register_value + 2) for N/M1/M2, so here
290 * the range value for them is (actual_value - 2).
291 */
b91ad0ec 292static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 293 .dot = { .min = 25000, .max = 350000 },
294 .vco = { .min = 1760000, .max = 3510000 },
295 .n = { .min = 1, .max = 5 },
296 .m = { .min = 79, .max = 127 },
297 .m1 = { .min = 12, .max = 22 },
298 .m2 = { .min = 5, .max = 9 },
299 .p = { .min = 5, .max = 80 },
300 .p1 = { .min = 1, .max = 8 },
301 .p2 = { .dot_limit = 225000,
302 .p2_slow = 10, .p2_fast = 5 },
4547668a 303 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 304};
305
b91ad0ec 306static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 3 },
310 .m = { .min = 79, .max = 118 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 28, .max = 112 },
314 .p1 = { .min = 2, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 317 .find_pll = intel_g4x_find_best_PLL,
318};
319
320static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 127 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 14, .max = 56 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 331 .find_pll = intel_g4x_find_best_PLL,
332};
333
273e27ca 334/* LVDS 100mhz refclk limits. */
b91ad0ec 335static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 336 .dot = { .min = 25000, .max = 350000 },
337 .vco = { .min = 1760000, .max = 3510000 },
338 .n = { .min = 1, .max = 2 },
339 .m = { .min = 79, .max = 126 },
340 .m1 = { .min = 12, .max = 22 },
341 .m2 = { .min = 5, .max = 9 },
342 .p = { .min = 28, .max = 112 },
0206e353 343 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 344 .p2 = { .dot_limit = 225000,
345 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 346 .find_pll = intel_g4x_find_best_PLL,
347};
348
349static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000 },
352 .n = { .min = 1, .max = 3 },
353 .m = { .min = 79, .max = 126 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 14, .max = 42 },
0206e353 357 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 358 .p2 = { .dot_limit = 225000,
359 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 360 .find_pll = intel_g4x_find_best_PLL,
361};
362
363static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000},
366 .n = { .min = 1, .max = 2 },
367 .m = { .min = 81, .max = 90 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 10, .max = 20 },
371 .p1 = { .min = 1, .max = 2},
372 .p2 = { .dot_limit = 0,
273e27ca 373 .p2_slow = 10, .p2_fast = 10 },
0206e353 374 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 375};
376
a0c4da24
JB		 377static const intel_limit_t intel_limits_vlv_dac = {
378 .dot = { .min = 25000, .max = 270000 },
379 .vco = { .min = 4000000, .max = 6000000 },
380 .n = { .min = 1, .max = 7 },
381 .m = { .min = 22, .max = 450 }, /* guess */
382 .m1 = { .min = 2, .max = 3 },
383 .m2 = { .min = 11, .max = 156 },
384 .p = { .min = 10, .max = 30 },
385 .p1 = { .min = 2, .max = 3 },
386 .p2 = { .dot_limit = 270000,
387 .p2_slow = 2, .p2_fast = 20 },
388 .find_pll = intel_vlv_find_best_pll,
389};
390
391static const intel_limit_t intel_limits_vlv_hdmi = {
392 .dot = { .min = 20000, .max = 165000 },
17dc9257 393 .vco = { .min = 4000000, .max = 5994000},
a0c4da24
JB		 394 .n = { .min = 1, .max = 7 },
395 .m = { .min = 60, .max = 300 }, /* guess */
396 .m1 = { .min = 2, .max = 3 },
397 .m2 = { .min = 11, .max = 156 },
398 .p = { .min = 10, .max = 30 },
399 .p1 = { .min = 2, .max = 3 },
400 .p2 = { .dot_limit = 270000,
401 .p2_slow = 2, .p2_fast = 20 },
402 .find_pll = intel_vlv_find_best_pll,
403};
404
405static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 406 .dot = { .min = 25000, .max = 270000 },
407 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 408 .n = { .min = 1, .max = 7 },
74a4dd2e 409 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 410 .m1 = { .min = 2, .max = 3 },
411 .m2 = { .min = 11, .max = 156 },
412 .p = { .min = 10, .max = 30 },
413 .p1 = { .min = 2, .max = 3 },
414 .p2 = { .dot_limit = 270000,
415 .p2_slow = 2, .p2_fast = 20 },
416 .find_pll = intel_vlv_find_best_pll,
417};
418
57f350b6
JB		 419u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
420{
421 unsigned long flags;
422 u32 val = 0;
423
424 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
425 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
426 DRM_ERROR("DPIO idle wait timed out\n");
427 goto out_unlock;
428 }
429
430 I915_WRITE(DPIO_REG, reg);
431 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
432 DPIO_BYTE);
433 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
434 DRM_ERROR("DPIO read wait timed out\n");
435 goto out_unlock;
436 }
437 val = I915_READ(DPIO_DATA);
438
439out_unlock:
440 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
441 return val;
442}
443
a0c4da24
JB		 444static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
445 u32 val)
446{
447 unsigned long flags;
448
449 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
450 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
451 DRM_ERROR("DPIO idle wait timed out\n");
452 goto out_unlock;
453 }
454
455 I915_WRITE(DPIO_DATA, val);
456 I915_WRITE(DPIO_REG, reg);
457 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
458 DPIO_BYTE);
459 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
460 DRM_ERROR("DPIO write wait timed out\n");
461
462out_unlock:
463 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
464}
465
57f350b6
JB		 466static void vlv_init_dpio(struct drm_device *dev)
467{
468 struct drm_i915_private *dev_priv = dev->dev_private;
469
470 /* Reset the DPIO config */
471 I915_WRITE(DPIO_CTL, 0);
472 POSTING_READ(DPIO_CTL);
473 I915_WRITE(DPIO_CTL, 1);
474 POSTING_READ(DPIO_CTL);
475}
476
618563e3
DV		 477static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
478{
479 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
480 return 1;
481}
482
483static const struct dmi_system_id intel_dual_link_lvds[] = {
484 {
485 .callback = intel_dual_link_lvds_callback,
486 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
487 .matches = {
488 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
489 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
490 },
491 },
492 { } /* terminating entry */
493};
494
b0354385
TI		 495static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
496 unsigned int reg)
497{
498 unsigned int val;
499
121d527a
TI		 500 /* use the module option value if specified */
501 if (i915_lvds_channel_mode > 0)
502 return i915_lvds_channel_mode == 2;
503
618563e3
DV		 504 if (dmi_check_system(intel_dual_link_lvds))
505 return true;
506
b0354385
TI		 507 if (dev_priv->lvds_val)
508 val = dev_priv->lvds_val;
509 else {
510 /* BIOS should set the proper LVDS register value at boot, but
511 * in reality, it doesn't set the value when the lid is closed;
512 * we need to check "the value to be set" in VBT when LVDS
513 * register is uninitialized.
514 */
515 val = I915_READ(reg);
14d94a3d 516 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
b0354385
TI		 517 val = dev_priv->bios_lvds_val;
518 dev_priv->lvds_val = val;
519 }
520 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
521}
522
1b894b59
CW		 523static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
524 int refclk)
2c07245f 525{
b91ad0ec
ZW		 526 struct drm_device *dev = crtc->dev;
527 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 528 const intel_limit_t *limit;
b91ad0ec
ZW		 529
530 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 531 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
b91ad0ec 532 /* LVDS dual channel */
1b894b59 533 if (refclk == 100000)
b91ad0ec
ZW		 534 limit = &intel_limits_ironlake_dual_lvds_100m;
535 else
536 limit = &intel_limits_ironlake_dual_lvds;
537 } else {
1b894b59 538 if (refclk == 100000)
b91ad0ec
ZW		 539 limit = &intel_limits_ironlake_single_lvds_100m;
540 else
541 limit = &intel_limits_ironlake_single_lvds;
542 }
543 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 544 HAS_eDP)
545 limit = &intel_limits_ironlake_display_port;
2c07245f 546 else
b91ad0ec 547 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 548
549 return limit;
550}
551
044c7c41
ML		 552static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
553{
554 struct drm_device *dev = crtc->dev;
555 struct drm_i915_private *dev_priv = dev->dev_private;
556 const intel_limit_t *limit;
557
558 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 559 if (is_dual_link_lvds(dev_priv, LVDS))
044c7c41 560 /* LVDS with dual channel */
e4b36699 561 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 562 else
563 /* LVDS with dual channel */
e4b36699 564 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 565 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
566 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 567 limit = &intel_limits_g4x_hdmi;
044c7c41 568 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 569 limit = &intel_limits_g4x_sdvo;
0206e353 570 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 571 limit = &intel_limits_g4x_display_port;
044c7c41 572 } else /* The option is for other outputs */
e4b36699 573 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 574
575 return limit;
576}
577
1b894b59 578static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 579{
580 struct drm_device *dev = crtc->dev;
581 const intel_limit_t *limit;
582
bad720ff 583 if (HAS_PCH_SPLIT(dev))
1b894b59 584 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 585 else if (IS_G4X(dev)) {
044c7c41 586 limit = intel_g4x_limit(crtc);
f2b115e6 587 } else if (IS_PINEVIEW(dev)) {
2177832f 588 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 589 limit = &intel_limits_pineview_lvds;
2177832f 590 else
f2b115e6 591 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 592 } else if (IS_VALLEYVIEW(dev)) {
593 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
594 limit = &intel_limits_vlv_dac;
595 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
596 limit = &intel_limits_vlv_hdmi;
597 else
598 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 599 } else if (!IS_GEN2(dev)) {
600 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
601 limit = &intel_limits_i9xx_lvds;
602 else
603 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 604 } else {
605 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 606 limit = &intel_limits_i8xx_lvds;
79e53945 607 else
e4b36699 608 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 609 }
610 return limit;
611}
612
f2b115e6
AJ		 613/* m1 is reserved as 0 in Pineview, n is a ring counter */
614static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 615{
2177832f
SL		 616 clock->m = clock->m2 + 2;
617 clock->p = clock->p1 * clock->p2;
618 clock->vco = refclk * clock->m / clock->n;
619 clock->dot = clock->vco / clock->p;
620}
621
622static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
623{
f2b115e6
AJ		 624 if (IS_PINEVIEW(dev)) {
625 pineview_clock(refclk, clock);
2177832f
SL		 626 return;
627 }
79e53945
JB		 628 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
629 clock->p = clock->p1 * clock->p2;
630 clock->vco = refclk * clock->m / (clock->n + 2);
631 clock->dot = clock->vco / clock->p;
632}
633
79e53945
JB		 634/**
635 * Returns whether any output on the specified pipe is of the specified type
636 */
4ef69c7a 637bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 638{
4ef69c7a 639 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 640 struct intel_encoder *encoder;
641
6c2b7c12
DV		 642 for_each_encoder_on_crtc(dev, crtc, encoder)
643 if (encoder->type == type)
4ef69c7a
CW		 644 return true;
645
646 return false;
79e53945
JB		 647}
648
7c04d1d9 649#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 650/**
651 * Returns whether the given set of divisors are valid for a given refclk with
652 * the given connectors.
653 */
654
1b894b59
CW		 655static bool intel_PLL_is_valid(struct drm_device *dev,
656 const intel_limit_t *limit,
657 const intel_clock_t *clock)
79e53945 658{
79e53945 659 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 660 INTELPllInvalid("p1 out of range\n");
79e53945 661 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 662 INTELPllInvalid("p out of range\n");
79e53945 663 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 664 INTELPllInvalid("m2 out of range\n");
79e53945 665 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 666 INTELPllInvalid("m1 out of range\n");
f2b115e6 667 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 668 INTELPllInvalid("m1 <= m2\n");
79e53945 669 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 670 INTELPllInvalid("m out of range\n");
79e53945 671 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 672 INTELPllInvalid("n out of range\n");
79e53945 673 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 674 INTELPllInvalid("vco out of range\n");
79e53945
JB		 675 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
676 * connector, etc., rather than just a single range.
677 */
678 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 679 INTELPllInvalid("dot out of range\n");
79e53945
JB		 680
681 return true;
682}
683
d4906093
ML		 684static bool
685intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 686 int target, int refclk, intel_clock_t *match_clock,
687 intel_clock_t *best_clock)
d4906093 688
79e53945
JB		 689{
690 struct drm_device *dev = crtc->dev;
691 struct drm_i915_private *dev_priv = dev->dev_private;
692 intel_clock_t clock;
79e53945
JB		 693 int err = target;
694
bc5e5718 695 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 696 (I915_READ(LVDS)) != 0) {
79e53945
JB		 697 /*
698 * For LVDS, if the panel is on, just rely on its current
699 * settings for dual-channel. We haven't figured out how to
700 * reliably set up different single/dual channel state, if we
701 * even can.
702 */
b0354385 703 if (is_dual_link_lvds(dev_priv, LVDS))
79e53945
JB		 704 clock.p2 = limit->p2.p2_fast;
705 else
706 clock.p2 = limit->p2.p2_slow;
707 } else {
708 if (target < limit->p2.dot_limit)
709 clock.p2 = limit->p2.p2_slow;
710 else
711 clock.p2 = limit->p2.p2_fast;
712 }
713
0206e353 714 memset(best_clock, 0, sizeof(*best_clock));
79e53945 715
42158660
ZY		 716 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
717 clock.m1++) {
718 for (clock.m2 = limit->m2.min;
719 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 720 /* m1 is always 0 in Pineview */
721 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 722 break;
723 for (clock.n = limit->n.min;
724 clock.n <= limit->n.max; clock.n++) {
725 for (clock.p1 = limit->p1.min;
726 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 727 int this_err;
728
2177832f 729 intel_clock(dev, refclk, &clock);
1b894b59
CW		 730 if (!intel_PLL_is_valid(dev, limit,
731 &clock))
79e53945 732 continue;
cec2f356
SP		 733 if (match_clock &&
734 clock.p != match_clock->p)
735 continue;
79e53945
JB		 736
737 this_err = abs(clock.dot - target);
738 if (this_err < err) {
739 *best_clock = clock;
740 err = this_err;
741 }
742 }
743 }
744 }
745 }
746
747 return (err != target);
748}
749
d4906093
ML		 750static bool
751intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 752 int target, int refclk, intel_clock_t *match_clock,
753 intel_clock_t *best_clock)
d4906093
ML		 754{
755 struct drm_device *dev = crtc->dev;
756 struct drm_i915_private *dev_priv = dev->dev_private;
757 intel_clock_t clock;
758 int max_n;
759 bool found;
6ba770dc
AJ		 760 /* approximately equals target * 0.00585 */
761 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 762 found = false;
763
764 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 765 int lvds_reg;
766
c619eed4 767 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 768 lvds_reg = PCH_LVDS;
769 else
770 lvds_reg = LVDS;
771 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 772 LVDS_CLKB_POWER_UP)
773 clock.p2 = limit->p2.p2_fast;
774 else
775 clock.p2 = limit->p2.p2_slow;
776 } else {
777 if (target < limit->p2.dot_limit)
778 clock.p2 = limit->p2.p2_slow;
779 else
780 clock.p2 = limit->p2.p2_fast;
781 }
782
783 memset(best_clock, 0, sizeof(*best_clock));
784 max_n = limit->n.max;
f77f13e2 785 /* based on hardware requirement, prefer smaller n to precision */
d4906093 786 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 787 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 788 for (clock.m1 = limit->m1.max;
789 clock.m1 >= limit->m1.min; clock.m1--) {
790 for (clock.m2 = limit->m2.max;
791 clock.m2 >= limit->m2.min; clock.m2--) {
792 for (clock.p1 = limit->p1.max;
793 clock.p1 >= limit->p1.min; clock.p1--) {
794 int this_err;
795
2177832f 796 intel_clock(dev, refclk, &clock);
1b894b59
CW		 797 if (!intel_PLL_is_valid(dev, limit,
798 &clock))
d4906093 799 continue;
cec2f356
SP		 800 if (match_clock &&
801 clock.p != match_clock->p)
802 continue;
1b894b59
CW		 803
804 this_err = abs(clock.dot - target);
d4906093
ML		 805 if (this_err < err_most) {
806 *best_clock = clock;
807 err_most = this_err;
808 max_n = clock.n;
809 found = true;
810 }
811 }
812 }
813 }
814 }
2c07245f
ZW		 815 return found;
816}
817
5eb08b69 818static bool
f2b115e6 819intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 820 int target, int refclk, intel_clock_t *match_clock,
821 intel_clock_t *best_clock)
5eb08b69
ZW		 822{
823 struct drm_device *dev = crtc->dev;
824 intel_clock_t clock;
4547668a 825
5eb08b69
ZW		 826 if (target < 200000) {
827 clock.n = 1;
828 clock.p1 = 2;
829 clock.p2 = 10;
830 clock.m1 = 12;
831 clock.m2 = 9;
832 } else {
833 clock.n = 2;
834 clock.p1 = 1;
835 clock.p2 = 10;
836 clock.m1 = 14;
837 clock.m2 = 8;
838 }
839 intel_clock(dev, refclk, &clock);
840 memcpy(best_clock, &clock, sizeof(intel_clock_t));
841 return true;
842}
843
a4fc5ed6
KP		 844/* DisplayPort has only two frequencies, 162MHz and 270MHz */
845static bool
846intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 847 int target, int refclk, intel_clock_t *match_clock,
848 intel_clock_t *best_clock)
a4fc5ed6 849{
5eddb70b
CW		 850 intel_clock_t clock;
851 if (target < 200000) {
852 clock.p1 = 2;
853 clock.p2 = 10;
854 clock.n = 2;
855 clock.m1 = 23;
856 clock.m2 = 8;
857 } else {
858 clock.p1 = 1;
859 clock.p2 = 10;
860 clock.n = 1;
861 clock.m1 = 14;
862 clock.m2 = 2;
863 }
864 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
865 clock.p = (clock.p1 * clock.p2);
866 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
867 clock.vco = 0;
868 memcpy(best_clock, &clock, sizeof(intel_clock_t));
869 return true;
a4fc5ed6 870}
a0c4da24
JB		 871static bool
872intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
873 int target, int refclk, intel_clock_t *match_clock,
874 intel_clock_t *best_clock)
875{
876 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
877 u32 m, n, fastclk;
878 u32 updrate, minupdate, fracbits, p;
879 unsigned long bestppm, ppm, absppm;
880 int dotclk, flag;
881
af447bd3 882 flag = 0;
a0c4da24
JB		 883 dotclk = target * 1000;
884 bestppm = 1000000;
885 ppm = absppm = 0;
886 fastclk = dotclk / (2*100);
887 updrate = 0;
888 minupdate = 19200;
889 fracbits = 1;
890 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
891 bestm1 = bestm2 = bestp1 = bestp2 = 0;
892
893 /* based on hardware requirement, prefer smaller n to precision */
894 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
895 updrate = refclk / n;
896 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
897 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
898 if (p2 > 10)
899 p2 = p2 - 1;
900 p = p1 * p2;
901 /* based on hardware requirement, prefer bigger m1,m2 values */
902 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
903 m2 = (((2*(fastclk * p * n / m1 )) +
904 refclk) / (2*refclk));
905 m = m1 * m2;
906 vco = updrate * m;
907 if (vco >= limit->vco.min && vco < limit->vco.max) {
908 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
909 absppm = (ppm > 0) ? ppm : (-ppm);
910 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
911 bestppm = 0;
912 flag = 1;
913 }
914 if (absppm < bestppm - 10) {
915 bestppm = absppm;
916 flag = 1;
917 }
918 if (flag) {
919 bestn = n;
920 bestm1 = m1;
921 bestm2 = m2;
922 bestp1 = p1;
923 bestp2 = p2;
924 flag = 0;
925 }
926 }
927 }
928 }
929 }
930 }
931 best_clock->n = bestn;
932 best_clock->m1 = bestm1;
933 best_clock->m2 = bestm2;
934 best_clock->p1 = bestp1;
935 best_clock->p2 = bestp2;
936
937 return true;
938}
a4fc5ed6 939
a5c961d1
PZ		 940enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
941 enum pipe pipe)
942{
943 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
945
946 return intel_crtc->cpu_transcoder;
947}
948
a928d536
PZ		 949static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
950{
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 u32 frame, frame_reg = PIPEFRAME(pipe);
953
954 frame = I915_READ(frame_reg);
955
956 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
957 DRM_DEBUG_KMS("vblank wait timed out\n");
958}
959
9d0498a2
JB		 960/**
961 * intel_wait_for_vblank - wait for vblank on a given pipe
962 * @dev: drm device
963 * @pipe: pipe to wait for
964 *
965 * Wait for vblank to occur on a given pipe. Needed for various bits of
966 * mode setting code.
967 */
968void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 969{
9d0498a2 970 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 971 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 972
a928d536
PZ		 973 if (INTEL_INFO(dev)->gen >= 5) {
974 ironlake_wait_for_vblank(dev, pipe);
975 return;
976 }
977
300387c0
CW		 978 /* Clear existing vblank status. Note this will clear any other
979 * sticky status fields as well.
980 *
981 * This races with i915_driver_irq_handler() with the result
982 * that either function could miss a vblank event. Here it is not
983 * fatal, as we will either wait upon the next vblank interrupt or
984 * timeout. Generally speaking intel_wait_for_vblank() is only
985 * called during modeset at which time the GPU should be idle and
986 * should *not* be performing page flips and thus not waiting on
987 * vblanks...
988 * Currently, the result of us stealing a vblank from the irq
989 * handler is that a single frame will be skipped during swapbuffers.
990 */
991 I915_WRITE(pipestat_reg,
992 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
993
9d0498a2 994 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 995 if (wait_for(I915_READ(pipestat_reg) &
996 PIPE_VBLANK_INTERRUPT_STATUS,
997 50))
9d0498a2
JB		 998 DRM_DEBUG_KMS("vblank wait timed out\n");
999}
1000
ab7ad7f6
KP		 1001/*
1002 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 1003 * @dev: drm device
1004 * @pipe: pipe to wait for
1005 *
1006 * After disabling a pipe, we can't wait for vblank in the usual way,
1007 * spinning on the vblank interrupt status bit, since we won't actually
1008 * see an interrupt when the pipe is disabled.
1009 *
ab7ad7f6
KP		 1010 * On Gen4 and above:
1011 * wait for the pipe register state bit to turn off
1012 *
1013 * Otherwise:
1014 * wait for the display line value to settle (it usually
1015 * ends up stopping at the start of the next frame).
58e10eb9 1016 *
9d0498a2 1017 */
58e10eb9 1018void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 1019{
1020 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 1021 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1022 pipe);
ab7ad7f6
KP		 1023
1024 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1025 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1026
1027 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1028 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1029 100))
284637d9 1030 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1031 } else {
837ba00f 1032 u32 last_line, line_mask;
58e10eb9 1033 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 1034 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1035
837ba00f
PZ		 1036 if (IS_GEN2(dev))
1037 line_mask = DSL_LINEMASK_GEN2;
1038 else
1039 line_mask = DSL_LINEMASK_GEN3;
1040
ab7ad7f6
KP		 1041 /* Wait for the display line to settle */
1042 do {
837ba00f 1043 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 1044 mdelay(5);
837ba00f 1045 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 1046 time_after(timeout, jiffies));
1047 if (time_after(jiffies, timeout))
284637d9 1048 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1049 }
79e53945
JB		 1050}
1051
b24e7179
JB		 1052static const char *state_string(bool enabled)
1053{
1054 return enabled ? "on" : "off";
1055}
1056
1057/* Only for pre-ILK configs */
1058static void assert_pll(struct drm_i915_private *dev_priv,
1059 enum pipe pipe, bool state)
1060{
1061 int reg;
1062 u32 val;
1063 bool cur_state;
1064
1065 reg = DPLL(pipe);
1066 val = I915_READ(reg);
1067 cur_state = !!(val & DPLL_VCO_ENABLE);
1068 WARN(cur_state != state,
1069 "PLL state assertion failure (expected %s, current %s)\n",
1070 state_string(state), state_string(cur_state));
1071}
1072#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1073#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1074
040484af
JB		 1075/* For ILK+ */
1076static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1077 struct intel_pch_pll *pll,
1078 struct intel_crtc *crtc,
1079 bool state)
040484af 1080{
040484af
JB		 1081 u32 val;
1082 bool cur_state;
1083
9d82aa17
ED		 1084 if (HAS_PCH_LPT(dev_priv->dev)) {
1085 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1086 return;
1087 }
1088
92b27b08
CW		 1089 if (WARN (!pll,
1090 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1091 return;
ee7b9f93 1092
92b27b08
CW		 1093 val = I915_READ(pll->pll_reg);
1094 cur_state = !!(val & DPLL_VCO_ENABLE);
1095 WARN(cur_state != state,
1096 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1097 pll->pll_reg, state_string(state), state_string(cur_state), val);
1098
1099 /* Make sure the selected PLL is correctly attached to the transcoder */
1100 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1101 u32 pch_dpll;
1102
1103 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1104 cur_state = pll->pll_reg == _PCH_DPLL_B;
1105 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1106 "PLL[%d] not attached to this transcoder %d: %08x\n",
1107 cur_state, crtc->pipe, pch_dpll)) {
1108 cur_state = !!(val >> (4*crtc->pipe + 3));
1109 WARN(cur_state != state,
1110 "PLL[%d] not %s on this transcoder %d: %08x\n",
1111 pll->pll_reg == _PCH_DPLL_B,
1112 state_string(state),
1113 crtc->pipe,
1114 val);
1115 }
d3ccbe86 1116 }
040484af 1117}
92b27b08
CW		 1118#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1119#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1120
1121static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1122 enum pipe pipe, bool state)
1123{
1124 int reg;
1125 u32 val;
1126 bool cur_state;
ad80a810
PZ		 1127 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128 pipe);
040484af 1129
bf507ef7
ED		 1130 if (IS_HASWELL(dev_priv->dev)) {
1131 /* On Haswell, DDI is used instead of FDI_TX_CTL */
ad80a810 1132 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1133 val = I915_READ(reg);
ad80a810 1134 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1135 } else {
1136 reg = FDI_TX_CTL(pipe);
1137 val = I915_READ(reg);
1138 cur_state = !!(val & FDI_TX_ENABLE);
1139 }
040484af
JB		 1140 WARN(cur_state != state,
1141 "FDI TX state assertion failure (expected %s, current %s)\n",
1142 state_string(state), state_string(cur_state));
1143}
1144#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1145#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1146
1147static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1148 enum pipe pipe, bool state)
1149{
1150 int reg;
1151 u32 val;
1152 bool cur_state;
1153
59c859d6
ED		 1154 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1155 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1156 return;
1157 } else {
1158 reg = FDI_RX_CTL(pipe);
1159 val = I915_READ(reg);
1160 cur_state = !!(val & FDI_RX_ENABLE);
1161 }
040484af
JB		 1162 WARN(cur_state != state,
1163 "FDI RX state assertion failure (expected %s, current %s)\n",
1164 state_string(state), state_string(cur_state));
1165}
1166#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1167#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1168
1169static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1170 enum pipe pipe)
1171{
1172 int reg;
1173 u32 val;
1174
1175 /* ILK FDI PLL is always enabled */
1176 if (dev_priv->info->gen == 5)
1177 return;
1178
bf507ef7
ED		 1179 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1180 if (IS_HASWELL(dev_priv->dev))
1181 return;
1182
040484af
JB		 1183 reg = FDI_TX_CTL(pipe);
1184 val = I915_READ(reg);
1185 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1186}
1187
1188static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1189 enum pipe pipe)
1190{
1191 int reg;
1192 u32 val;
1193
59c859d6
ED		 1194 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1195 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1196 return;
1197 }
040484af
JB		 1198 reg = FDI_RX_CTL(pipe);
1199 val = I915_READ(reg);
1200 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1201}
1202
ea0760cf
JB		 1203static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1204 enum pipe pipe)
1205{
1206 int pp_reg, lvds_reg;
1207 u32 val;
1208 enum pipe panel_pipe = PIPE_A;
0de3b485 1209 bool locked = true;
ea0760cf
JB		 1210
1211 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1212 pp_reg = PCH_PP_CONTROL;
1213 lvds_reg = PCH_LVDS;
1214 } else {
1215 pp_reg = PP_CONTROL;
1216 lvds_reg = LVDS;
1217 }
1218
1219 val = I915_READ(pp_reg);
1220 if (!(val & PANEL_POWER_ON) ||
1221 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1222 locked = false;
1223
1224 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1225 panel_pipe = PIPE_B;
1226
1227 WARN(panel_pipe == pipe && locked,
1228 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1229 pipe_name(pipe));
ea0760cf
JB		 1230}
1231
b840d907
JB		 1232void assert_pipe(struct drm_i915_private *dev_priv,
1233 enum pipe pipe, bool state)
b24e7179
JB		 1234{
1235 int reg;
1236 u32 val;
63d7bbe9 1237 bool cur_state;
702e7a56
PZ		 1238 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1239 pipe);
b24e7179 1240
8e636784
DV		 1241 /* if we need the pipe A quirk it must be always on */
1242 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1243 state = true;
1244
702e7a56 1245 reg = PIPECONF(cpu_transcoder);
b24e7179 1246 val = I915_READ(reg);
63d7bbe9
JB		 1247 cur_state = !!(val & PIPECONF_ENABLE);
1248 WARN(cur_state != state,
1249 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1250 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1251}
1252
931872fc
CW		 1253static void assert_plane(struct drm_i915_private *dev_priv,
1254 enum plane plane, bool state)
b24e7179
JB		 1255{
1256 int reg;
1257 u32 val;
931872fc 1258 bool cur_state;
b24e7179
JB		 1259
1260 reg = DSPCNTR(plane);
1261 val = I915_READ(reg);
931872fc
CW		 1262 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1263 WARN(cur_state != state,
1264 "plane %c assertion failure (expected %s, current %s)\n",
1265 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1266}
1267
931872fc
CW		 1268#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1269#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1270
b24e7179
JB		 1271static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1272 enum pipe pipe)
1273{
1274 int reg, i;
1275 u32 val;
1276 int cur_pipe;
1277
19ec1358 1278 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1279 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1280 reg = DSPCNTR(pipe);
1281 val = I915_READ(reg);
1282 WARN((val & DISPLAY_PLANE_ENABLE),
1283 "plane %c assertion failure, should be disabled but not\n",
1284 plane_name(pipe));
19ec1358 1285 return;
28c05794 1286 }
19ec1358 1287
b24e7179
JB		 1288 /* Need to check both planes against the pipe */
1289 for (i = 0; i < 2; i++) {
1290 reg = DSPCNTR(i);
1291 val = I915_READ(reg);
1292 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1293 DISPPLANE_SEL_PIPE_SHIFT;
1294 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1295 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1296 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1297 }
1298}
1299
92f2584a
JB		 1300static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1301{
1302 u32 val;
1303 bool enabled;
1304
9d82aa17
ED		 1305 if (HAS_PCH_LPT(dev_priv->dev)) {
1306 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1307 return;
1308 }
1309
92f2584a
JB		 1310 val = I915_READ(PCH_DREF_CONTROL);
1311 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1312 DREF_SUPERSPREAD_SOURCE_MASK));
1313 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1314}
1315
1316static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1317 enum pipe pipe)
1318{
1319 int reg;
1320 u32 val;
1321 bool enabled;
1322
1323 reg = TRANSCONF(pipe);
1324 val = I915_READ(reg);
1325 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1326 WARN(enabled,
1327 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1328 pipe_name(pipe));
92f2584a
JB		 1329}
1330
4e634389
KP		 1331static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1332 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1333{
1334 if ((val & DP_PORT_EN) == 0)
1335 return false;
1336
1337 if (HAS_PCH_CPT(dev_priv->dev)) {
1338 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1339 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1340 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1341 return false;
1342 } else {
1343 if ((val & DP_PIPE_MASK) != (pipe << 30))
1344 return false;
1345 }
1346 return true;
1347}
1348
1519b995
KP		 1349static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1350 enum pipe pipe, u32 val)
1351{
1352 if ((val & PORT_ENABLE) == 0)
1353 return false;
1354
1355 if (HAS_PCH_CPT(dev_priv->dev)) {
1356 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1357 return false;
1358 } else {
1359 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1360 return false;
1361 }
1362 return true;
1363}
1364
1365static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1366 enum pipe pipe, u32 val)
1367{
1368 if ((val & LVDS_PORT_EN) == 0)
1369 return false;
1370
1371 if (HAS_PCH_CPT(dev_priv->dev)) {
1372 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1373 return false;
1374 } else {
1375 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1376 return false;
1377 }
1378 return true;
1379}
1380
1381static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1382 enum pipe pipe, u32 val)
1383{
1384 if ((val & ADPA_DAC_ENABLE) == 0)
1385 return false;
1386 if (HAS_PCH_CPT(dev_priv->dev)) {
1387 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1388 return false;
1389 } else {
1390 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1391 return false;
1392 }
1393 return true;
1394}
1395
291906f1 1396static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1397 enum pipe pipe, int reg, u32 port_sel)
291906f1 1398{
47a05eca 1399 u32 val = I915_READ(reg);
4e634389 1400 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1401 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1402 reg, pipe_name(pipe));
de9a35ab 1403
75c5da27
DV		 1404 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1405 && (val & DP_PIPEB_SELECT),
de9a35ab 1406 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1407}
1408
1409static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1410 enum pipe pipe, int reg)
1411{
47a05eca 1412 u32 val = I915_READ(reg);
e9a851ed 1413 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1414 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1415 reg, pipe_name(pipe));
de9a35ab 1416
75c5da27
DV		 1417 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1418 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1419 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1420}
1421
1422static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1423 enum pipe pipe)
1424{
1425 int reg;
1426 u32 val;
291906f1 1427
f0575e92
KP		 1428 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1429 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1430 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1431
1432 reg = PCH_ADPA;
1433 val = I915_READ(reg);
e9a851ed 1434 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1435 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1436 pipe_name(pipe));
291906f1
JB		 1437
1438 reg = PCH_LVDS;
1439 val = I915_READ(reg);
e9a851ed 1440 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1441 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1442 pipe_name(pipe));
291906f1
JB		 1443
1444 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1445 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1446 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1447}
1448
63d7bbe9
JB		 1449/**
1450 * intel_enable_pll - enable a PLL
1451 * @dev_priv: i915 private structure
1452 * @pipe: pipe PLL to enable
1453 *
1454 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1455 * make sure the PLL reg is writable first though, since the panel write
1456 * protect mechanism may be enabled.
1457 *
1458 * Note! This is for pre-ILK only.
7434a255
TR		 1459 *
1460 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9 1461 */
a37b9b34 1462static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9
JB		 1463{
1464 int reg;
1465 u32 val;
1466
1467 /* No really, not for ILK+ */
a0c4da24 1468 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1469
1470 /* PLL is protected by panel, make sure we can write it */
1471 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1472 assert_panel_unlocked(dev_priv, pipe);
1473
1474 reg = DPLL(pipe);
1475 val = I915_READ(reg);
1476 val |= DPLL_VCO_ENABLE;
1477
1478 /* We do this three times for luck */
1479 I915_WRITE(reg, val);
1480 POSTING_READ(reg);
1481 udelay(150); /* wait for warmup */
1482 I915_WRITE(reg, val);
1483 POSTING_READ(reg);
1484 udelay(150); /* wait for warmup */
1485 I915_WRITE(reg, val);
1486 POSTING_READ(reg);
1487 udelay(150); /* wait for warmup */
1488}
1489
1490/**
1491 * intel_disable_pll - disable a PLL
1492 * @dev_priv: i915 private structure
1493 * @pipe: pipe PLL to disable
1494 *
1495 * Disable the PLL for @pipe, making sure the pipe is off first.
1496 *
1497 * Note! This is for pre-ILK only.
1498 */
1499static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1500{
1501 int reg;
1502 u32 val;
1503
1504 /* Don't disable pipe A or pipe A PLLs if needed */
1505 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1506 return;
1507
1508 /* Make sure the pipe isn't still relying on us */
1509 assert_pipe_disabled(dev_priv, pipe);
1510
1511 reg = DPLL(pipe);
1512 val = I915_READ(reg);
1513 val &= ~DPLL_VCO_ENABLE;
1514 I915_WRITE(reg, val);
1515 POSTING_READ(reg);
1516}
1517
a416edef
ED		 1518/* SBI access */
1519static void
1520intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1521{
1522 unsigned long flags;
1523
1524 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1525 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1526 100)) {
1527 DRM_ERROR("timeout waiting for SBI to become ready\n");
1528 goto out_unlock;
1529 }
1530
1531 I915_WRITE(SBI_ADDR,
1532 (reg << 16));
1533 I915_WRITE(SBI_DATA,
1534 value);
1535 I915_WRITE(SBI_CTL_STAT,
1536 SBI_BUSY |
1537 SBI_CTL_OP_CRWR);
1538
39fb50f6 1539 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1540 100)) {
1541 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1542 goto out_unlock;
1543 }
1544
1545out_unlock:
1546 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1547}
1548
1549static u32
1550intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1551{
1552 unsigned long flags;
39fb50f6 1553 u32 value = 0;
a416edef
ED		 1554
1555 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1556 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1557 100)) {
1558 DRM_ERROR("timeout waiting for SBI to become ready\n");
1559 goto out_unlock;
1560 }
1561
1562 I915_WRITE(SBI_ADDR,
1563 (reg << 16));
1564 I915_WRITE(SBI_CTL_STAT,
1565 SBI_BUSY |
1566 SBI_CTL_OP_CRRD);
1567
39fb50f6 1568 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1569 100)) {
1570 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1571 goto out_unlock;
1572 }
1573
1574 value = I915_READ(SBI_DATA);
1575
1576out_unlock:
1577 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1578 return value;
1579}
1580
92f2584a 1581/**
b6b4e185 1582 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1583 * @dev_priv: i915 private structure
1584 * @pipe: pipe PLL to enable
1585 *
1586 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1587 * drives the transcoder clock.
1588 */
b6b4e185 1589static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1590{
ee7b9f93 1591 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1592 struct intel_pch_pll *pll;
92f2584a
JB		 1593 int reg;
1594 u32 val;
1595
48da64a8 1596 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1597 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1598 pll = intel_crtc->pch_pll;
1599 if (pll == NULL)
1600 return;
1601
1602 if (WARN_ON(pll->refcount == 0))
1603 return;
ee7b9f93
JB		 1604
1605 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1606 pll->pll_reg, pll->active, pll->on,
1607 intel_crtc->base.base.id);
92f2584a
JB		 1608
1609 /* PCH refclock must be enabled first */
1610 assert_pch_refclk_enabled(dev_priv);
1611
ee7b9f93 1612 if (pll->active++ && pll->on) {
92b27b08 1613 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1614 return;
1615 }
1616
1617 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1618
1619 reg = pll->pll_reg;
92f2584a
JB		 1620 val = I915_READ(reg);
1621 val |= DPLL_VCO_ENABLE;
1622 I915_WRITE(reg, val);
1623 POSTING_READ(reg);
1624 udelay(200);
ee7b9f93
JB		 1625
1626 pll->on = true;
92f2584a
JB		 1627}
1628
ee7b9f93 1629static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1630{
ee7b9f93
JB		 1631 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1632 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1633 int reg;
ee7b9f93 1634 u32 val;
4c609cb8 1635
92f2584a
JB		 1636 /* PCH only available on ILK+ */
1637 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1638 if (pll == NULL)
1639 return;
92f2584a 1640
48da64a8
CW		 1641 if (WARN_ON(pll->refcount == 0))
1642 return;
7a419866 1643
ee7b9f93
JB		 1644 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1645 pll->pll_reg, pll->active, pll->on,
1646 intel_crtc->base.base.id);
7a419866 1647
48da64a8 1648 if (WARN_ON(pll->active == 0)) {
92b27b08 1649 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1650 return;
1651 }
1652
ee7b9f93 1653 if (--pll->active) {
92b27b08 1654 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1655 return;
ee7b9f93
JB		 1656 }
1657
1658 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1659
1660 /* Make sure transcoder isn't still depending on us */
1661 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1662
ee7b9f93 1663 reg = pll->pll_reg;
92f2584a
JB		 1664 val = I915_READ(reg);
1665 val &= ~DPLL_VCO_ENABLE;
1666 I915_WRITE(reg, val);
1667 POSTING_READ(reg);
1668 udelay(200);
ee7b9f93
JB		 1669
1670 pll->on = false;
92f2584a
JB		 1671}
1672
b8a4f404
PZ		 1673static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1674 enum pipe pipe)
040484af
JB		 1675{
1676 int reg;
5f7f726d 1677 u32 val, pipeconf_val;
7c26e5c6 1678 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
040484af
JB		 1679
1680 /* PCH only available on ILK+ */
1681 BUG_ON(dev_priv->info->gen < 5);
1682
1683 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1684 assert_pch_pll_enabled(dev_priv,
1685 to_intel_crtc(crtc)->pch_pll,
1686 to_intel_crtc(crtc));
040484af
JB		 1687
1688 /* FDI must be feeding us bits for PCH ports */
1689 assert_fdi_tx_enabled(dev_priv, pipe);
1690 assert_fdi_rx_enabled(dev_priv, pipe);
1691
1692 reg = TRANSCONF(pipe);
1693 val = I915_READ(reg);
5f7f726d 1694 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1695
1696 if (HAS_PCH_IBX(dev_priv->dev)) {
1697 /*
1698 * make the BPC in transcoder be consistent with
1699 * that in pipeconf reg.
1700 */
1701 val &= ~PIPE_BPC_MASK;
5f7f726d 1702 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1703 }
5f7f726d
PZ		 1704
1705 val &= ~TRANS_INTERLACE_MASK;
1706 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1707 if (HAS_PCH_IBX(dev_priv->dev) &&
1708 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1709 val |= TRANS_LEGACY_INTERLACED_ILK;
1710 else
1711 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1712 else
1713 val |= TRANS_PROGRESSIVE;
1714
040484af
JB		 1715 I915_WRITE(reg, val | TRANS_ENABLE);
1716 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1717 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1718}
1719
8fb033d7
PZ		 1720static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1721 enum pipe pipe)
1722{
1723 int reg;
1724 u32 val, pipeconf_val;
8fb033d7
PZ		 1725
1726 /* PCH only available on ILK+ */
1727 BUG_ON(dev_priv->info->gen < 5);
1728
8fb033d7
PZ		 1729 /* FDI must be feeding us bits for PCH ports */
1730 assert_fdi_tx_enabled(dev_priv, pipe);
1731 assert_fdi_rx_enabled(dev_priv, pipe);
1732
1733 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1734 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1735 return;
1736 }
1737 reg = TRANSCONF(pipe);
1738 val = I915_READ(reg);
1739 pipeconf_val = I915_READ(PIPECONF(pipe));
1740
8fb033d7
PZ		 1741 val &= ~TRANS_INTERLACE_MASK;
1742 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
a35f2679 1743 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1744 else
1745 val |= TRANS_PROGRESSIVE;
1746
1747 I915_WRITE(reg, val | TRANS_ENABLE);
1748 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1749 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1750}
1751
b8a4f404
PZ		 1752static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1753 enum pipe pipe)
040484af
JB		 1754{
1755 int reg;
1756 u32 val;
1757
1758 /* FDI relies on the transcoder */
1759 assert_fdi_tx_disabled(dev_priv, pipe);
1760 assert_fdi_rx_disabled(dev_priv, pipe);
1761
291906f1
JB		 1762 /* Ports must be off as well */
1763 assert_pch_ports_disabled(dev_priv, pipe);
1764
040484af
JB		 1765 reg = TRANSCONF(pipe);
1766 val = I915_READ(reg);
1767 val &= ~TRANS_ENABLE;
1768 I915_WRITE(reg, val);
1769 /* wait for PCH transcoder off, transcoder state */
1770 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1771 DRM_ERROR("failed to disable transcoder %d\n", pipe);
040484af
JB		 1772}
1773
8fb033d7
PZ		 1774static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1775 enum pipe pipe)
1776{
1777 int reg;
1778 u32 val;
1779
1780 /* FDI relies on the transcoder */
1781 assert_fdi_tx_disabled(dev_priv, pipe);
1782 assert_fdi_rx_disabled(dev_priv, pipe);
1783
1784 /* Ports must be off as well */
1785 assert_pch_ports_disabled(dev_priv, pipe);
1786
1787 reg = TRANSCONF(pipe);
1788 val = I915_READ(reg);
1789 val &= ~TRANS_ENABLE;
1790 I915_WRITE(reg, val);
1791 /* wait for PCH transcoder off, transcoder state */
1792 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1793 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1794}
1795
b24e7179 1796/**
309cfea8 1797 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1798 * @dev_priv: i915 private structure
1799 * @pipe: pipe to enable
040484af 1800 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1801 *
1802 * Enable @pipe, making sure that various hardware specific requirements
1803 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1804 *
1805 * @pipe should be %PIPE_A or %PIPE_B.
1806 *
1807 * Will wait until the pipe is actually running (i.e. first vblank) before
1808 * returning.
1809 */
040484af
JB		 1810static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1811 bool pch_port)
b24e7179 1812{
702e7a56
PZ		 1813 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1814 pipe);
b24e7179
JB		 1815 int reg;
1816 u32 val;
1817
1818 /*
1819 * A pipe without a PLL won't actually be able to drive bits from
1820 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1821 * need the check.
1822 */
1823 if (!HAS_PCH_SPLIT(dev_priv->dev))
1824 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1825 else {
1826 if (pch_port) {
1827 /* if driving the PCH, we need FDI enabled */
1828 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1829 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1830 }
1831 /* FIXME: assert CPU port conditions for SNB+ */
1832 }
b24e7179 1833
702e7a56 1834 reg = PIPECONF(cpu_transcoder);
b24e7179 1835 val = I915_READ(reg);
00d70b15
CW		 1836 if (val & PIPECONF_ENABLE)
1837 return;
1838
1839 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1840 intel_wait_for_vblank(dev_priv->dev, pipe);
1841}
1842
1843/**
309cfea8 1844 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1845 * @dev_priv: i915 private structure
1846 * @pipe: pipe to disable
1847 *
1848 * Disable @pipe, making sure that various hardware specific requirements
1849 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1850 *
1851 * @pipe should be %PIPE_A or %PIPE_B.
1852 *
1853 * Will wait until the pipe has shut down before returning.
1854 */
1855static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1856 enum pipe pipe)
1857{
702e7a56
PZ		 1858 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1859 pipe);
b24e7179
JB		 1860 int reg;
1861 u32 val;
1862
1863 /*
1864 * Make sure planes won't keep trying to pump pixels to us,
1865 * or we might hang the display.
1866 */
1867 assert_planes_disabled(dev_priv, pipe);
1868
1869 /* Don't disable pipe A or pipe A PLLs if needed */
1870 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1871 return;
1872
702e7a56 1873 reg = PIPECONF(cpu_transcoder);
b24e7179 1874 val = I915_READ(reg);
00d70b15
CW		 1875 if ((val & PIPECONF_ENABLE) == 0)
1876 return;
1877
1878 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1879 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1880}
1881
d74362c9
KP		 1882/*
1883 * Plane regs are double buffered, going from enabled->disabled needs a
1884 * trigger in order to latch. The display address reg provides this.
1885 */
6f1d69b0 1886void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1887 enum plane plane)
1888{
14f86147
DL		 1889 if (dev_priv->info->gen >= 4)
1890 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1891 else
1892 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1893}
1894
b24e7179
JB		 1895/**
1896 * intel_enable_plane - enable a display plane on a given pipe
1897 * @dev_priv: i915 private structure
1898 * @plane: plane to enable
1899 * @pipe: pipe being fed
1900 *
1901 * Enable @plane on @pipe, making sure that @pipe is running first.
1902 */
1903static void intel_enable_plane(struct drm_i915_private *dev_priv,
1904 enum plane plane, enum pipe pipe)
1905{
1906 int reg;
1907 u32 val;
1908
1909 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1910 assert_pipe_enabled(dev_priv, pipe);
1911
1912 reg = DSPCNTR(plane);
1913 val = I915_READ(reg);
00d70b15
CW		 1914 if (val & DISPLAY_PLANE_ENABLE)
1915 return;
1916
1917 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1918 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1919 intel_wait_for_vblank(dev_priv->dev, pipe);
1920}
1921
b24e7179
JB		 1922/**
1923 * intel_disable_plane - disable a display plane
1924 * @dev_priv: i915 private structure
1925 * @plane: plane to disable
1926 * @pipe: pipe consuming the data
1927 *
1928 * Disable @plane; should be an independent operation.
1929 */
1930static void intel_disable_plane(struct drm_i915_private *dev_priv,
1931 enum plane plane, enum pipe pipe)
1932{
1933 int reg;
1934 u32 val;
1935
1936 reg = DSPCNTR(plane);
1937 val = I915_READ(reg);
00d70b15
CW		 1938 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1939 return;
1940
1941 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1942 intel_flush_display_plane(dev_priv, plane);
1943 intel_wait_for_vblank(dev_priv->dev, pipe);
1944}
1945
127bd2ac 1946int
48b956c5 1947intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1948 struct drm_i915_gem_object *obj,
919926ae 1949 struct intel_ring_buffer *pipelined)
6b95a207 1950{
ce453d81 1951 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1952 u32 alignment;
1953 int ret;
1954
05394f39 1955 switch (obj->tiling_mode) {
6b95a207 1956 case I915_TILING_NONE:
534843da
CW		 1957 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1958 alignment = 128 * 1024;
a6c45cf0 1959 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1960 alignment = 4 * 1024;
1961 else
1962 alignment = 64 * 1024;
6b95a207
KH		 1963 break;
1964 case I915_TILING_X:
1965 /* pin() will align the object as required by fence */
1966 alignment = 0;
1967 break;
1968 case I915_TILING_Y:
1969 /* FIXME: Is this true? */
1970 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1971 return -EINVAL;
1972 default:
1973 BUG();
1974 }
1975
ce453d81 1976 dev_priv->mm.interruptible = false;
2da3b9b9 1977 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1978 if (ret)
ce453d81 1979 goto err_interruptible;
6b95a207
KH		 1980
1981 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1982 * fence, whereas 965+ only requires a fence if using
1983 * framebuffer compression. For simplicity, we always install
1984 * a fence as the cost is not that onerous.
1985 */
06d98131 1986 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1987 if (ret)
1988 goto err_unpin;
1690e1eb 1989
9a5a53b3 1990 i915_gem_object_pin_fence(obj);
6b95a207 1991
ce453d81 1992 dev_priv->mm.interruptible = true;
6b95a207 1993 return 0;
48b956c5
CW		 1994
1995err_unpin:
1996 i915_gem_object_unpin(obj);
ce453d81
CW		 1997err_interruptible:
1998 dev_priv->mm.interruptible = true;
48b956c5 1999 return ret;
6b95a207
KH		 2000}
2001
1690e1eb
CW		 2002void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2003{
2004 i915_gem_object_unpin_fence(obj);
2005 i915_gem_object_unpin(obj);
2006}
2007
c2c75131
DV		 2008/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2009 * is assumed to be a power-of-two. */
5a35e99e
DL		 2010unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
2011 unsigned int bpp,
2012 unsigned int pitch)
c2c75131
DV		 2013{
2014 int tile_rows, tiles;
2015
2016 tile_rows = *y / 8;
2017 *y %= 8;
2018 tiles = *x / (512/bpp);
2019 *x %= 512/bpp;
2020
2021 return tile_rows * pitch * 8 + tiles * 4096;
2022}
2023
17638cd6
JB		 2024static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2025 int x, int y)
81255565
JB		 2026{
2027 struct drm_device *dev = crtc->dev;
2028 struct drm_i915_private *dev_priv = dev->dev_private;
2029 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2030 struct intel_framebuffer *intel_fb;
05394f39 2031 struct drm_i915_gem_object *obj;
81255565 2032 int plane = intel_crtc->plane;
e506a0c6 2033 unsigned long linear_offset;
81255565 2034 u32 dspcntr;
5eddb70b 2035 u32 reg;
81255565
JB		 2036
2037 switch (plane) {
2038 case 0:
2039 case 1:
2040 break;
2041 default:
2042 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2043 return -EINVAL;
2044 }
2045
2046 intel_fb = to_intel_framebuffer(fb);
2047 obj = intel_fb->obj;
81255565 2048
5eddb70b
CW		 2049 reg = DSPCNTR(plane);
2050 dspcntr = I915_READ(reg);
81255565
JB		 2051 /* Mask out pixel format bits in case we change it */
2052 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2053 switch (fb->pixel_format) {
2054 case DRM_FORMAT_C8:
81255565
JB		 2055 dspcntr |= DISPPLANE_8BPP;
2056 break;
57779d06
VS		 2057 case DRM_FORMAT_XRGB1555:
2058 case DRM_FORMAT_ARGB1555:
2059 dspcntr |= DISPPLANE_BGRX555;
81255565 2060 break;
57779d06
VS		 2061 case DRM_FORMAT_RGB565:
2062 dspcntr |= DISPPLANE_BGRX565;
2063 break;
2064 case DRM_FORMAT_XRGB8888:
2065 case DRM_FORMAT_ARGB8888:
2066 dspcntr |= DISPPLANE_BGRX888;
2067 break;
2068 case DRM_FORMAT_XBGR8888:
2069 case DRM_FORMAT_ABGR8888:
2070 dspcntr |= DISPPLANE_RGBX888;
2071 break;
2072 case DRM_FORMAT_XRGB2101010:
2073 case DRM_FORMAT_ARGB2101010:
2074 dspcntr |= DISPPLANE_BGRX101010;
2075 break;
2076 case DRM_FORMAT_XBGR2101010:
2077 case DRM_FORMAT_ABGR2101010:
2078 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2079 break;
2080 default:
57779d06 2081 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
81255565
JB		 2082 return -EINVAL;
2083 }
57779d06 2084
a6c45cf0 2085 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2086 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2087 dspcntr |= DISPPLANE_TILED;
2088 else
2089 dspcntr &= ~DISPPLANE_TILED;
2090 }
2091
5eddb70b 2092 I915_WRITE(reg, dspcntr);
81255565 2093
e506a0c6 2094 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2095
c2c75131
DV		 2096 if (INTEL_INFO(dev)->gen >= 4) {
2097 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2098 intel_gen4_compute_offset_xtiled(&x, &y,
2099 fb->bits_per_pixel / 8,
2100 fb->pitches[0]);
c2c75131
DV		 2101 linear_offset -= intel_crtc->dspaddr_offset;
2102 } else {
e506a0c6 2103 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2104 }
e506a0c6
DV		 2105
2106 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2107 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2108 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2109 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2110 I915_MODIFY_DISPBASE(DSPSURF(plane),
2111 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2112 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2113 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2114 } else
e506a0c6 2115 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2116 POSTING_READ(reg);
81255565 2117
17638cd6
JB		 2118 return 0;
2119}
2120
2121static int ironlake_update_plane(struct drm_crtc *crtc,
2122 struct drm_framebuffer *fb, int x, int y)
2123{
2124 struct drm_device *dev = crtc->dev;
2125 struct drm_i915_private *dev_priv = dev->dev_private;
2126 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2127 struct intel_framebuffer *intel_fb;
2128 struct drm_i915_gem_object *obj;
2129 int plane = intel_crtc->plane;
e506a0c6 2130 unsigned long linear_offset;
17638cd6
JB		 2131 u32 dspcntr;
2132 u32 reg;
2133
2134 switch (plane) {
2135 case 0:
2136 case 1:
27f8227b 2137 case 2:
17638cd6
JB		 2138 break;
2139 default:
2140 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2141 return -EINVAL;
2142 }
2143
2144 intel_fb = to_intel_framebuffer(fb);
2145 obj = intel_fb->obj;
2146
2147 reg = DSPCNTR(plane);
2148 dspcntr = I915_READ(reg);
2149 /* Mask out pixel format bits in case we change it */
2150 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2151 switch (fb->pixel_format) {
2152 case DRM_FORMAT_C8:
17638cd6
JB		 2153 dspcntr |= DISPPLANE_8BPP;
2154 break;
57779d06
VS		 2155 case DRM_FORMAT_RGB565:
2156 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2157 break;
57779d06
VS		 2158 case DRM_FORMAT_XRGB8888:
2159 case DRM_FORMAT_ARGB8888:
2160 dspcntr |= DISPPLANE_BGRX888;
2161 break;
2162 case DRM_FORMAT_XBGR8888:
2163 case DRM_FORMAT_ABGR8888:
2164 dspcntr |= DISPPLANE_RGBX888;
2165 break;
2166 case DRM_FORMAT_XRGB2101010:
2167 case DRM_FORMAT_ARGB2101010:
2168 dspcntr |= DISPPLANE_BGRX101010;
2169 break;
2170 case DRM_FORMAT_XBGR2101010:
2171 case DRM_FORMAT_ABGR2101010:
2172 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2173 break;
2174 default:
57779d06 2175 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
17638cd6
JB		 2176 return -EINVAL;
2177 }
2178
2179 if (obj->tiling_mode != I915_TILING_NONE)
2180 dspcntr |= DISPPLANE_TILED;
2181 else
2182 dspcntr &= ~DISPPLANE_TILED;
2183
2184 /* must disable */
2185 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2186
2187 I915_WRITE(reg, dspcntr);
2188
e506a0c6 2189 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2190 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2191 intel_gen4_compute_offset_xtiled(&x, &y,
2192 fb->bits_per_pixel / 8,
2193 fb->pitches[0]);
c2c75131 2194 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2195
e506a0c6
DV		 2196 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2197 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2198 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2199 I915_MODIFY_DISPBASE(DSPSURF(plane),
2200 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2201 if (IS_HASWELL(dev)) {
2202 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2203 } else {
2204 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2205 I915_WRITE(DSPLINOFF(plane), linear_offset);
2206 }
17638cd6
JB		 2207 POSTING_READ(reg);
2208
2209 return 0;
2210}
2211
2212/* Assume fb object is pinned & idle & fenced and just update base pointers */
2213static int
2214intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2215 int x, int y, enum mode_set_atomic state)
2216{
2217 struct drm_device *dev = crtc->dev;
2218 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2219
6b8e6ed0
CW		 2220 if (dev_priv->display.disable_fbc)
2221 dev_priv->display.disable_fbc(dev);
3dec0095 2222 intel_increase_pllclock(crtc);
81255565 2223
6b8e6ed0 2224 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2225}
2226
14667a4b
CW		 2227static int
2228intel_finish_fb(struct drm_framebuffer *old_fb)
2229{
2230 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2231 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2232 bool was_interruptible = dev_priv->mm.interruptible;
2233 int ret;
2234
2235 wait_event(dev_priv->pending_flip_queue,
2236 atomic_read(&dev_priv->mm.wedged) ||
2237 atomic_read(&obj->pending_flip) == 0);
2238
2239 /* Big Hammer, we also need to ensure that any pending
2240 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2241 * current scanout is retired before unpinning the old
2242 * framebuffer.
2243 *
2244 * This should only fail upon a hung GPU, in which case we
2245 * can safely continue.
2246 */
2247 dev_priv->mm.interruptible = false;
2248 ret = i915_gem_object_finish_gpu(obj);
2249 dev_priv->mm.interruptible = was_interruptible;
2250
2251 return ret;
2252}
2253
198598d0
VS		 2254static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2255{
2256 struct drm_device *dev = crtc->dev;
2257 struct drm_i915_master_private *master_priv;
2258 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2259
2260 if (!dev->primary->master)
2261 return;
2262
2263 master_priv = dev->primary->master->driver_priv;
2264 if (!master_priv->sarea_priv)
2265 return;
2266
2267 switch (intel_crtc->pipe) {
2268 case 0:
2269 master_priv->sarea_priv->pipeA_x = x;
2270 master_priv->sarea_priv->pipeA_y = y;
2271 break;
2272 case 1:
2273 master_priv->sarea_priv->pipeB_x = x;
2274 master_priv->sarea_priv->pipeB_y = y;
2275 break;
2276 default:
2277 break;
2278 }
2279}
2280
5c3b82e2 2281static int
3c4fdcfb 2282intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2283 struct drm_framebuffer *fb)
79e53945
JB		 2284{
2285 struct drm_device *dev = crtc->dev;
6b8e6ed0 2286 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2287 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2288 struct drm_framebuffer *old_fb;
5c3b82e2 2289 int ret;
79e53945
JB		 2290
2291 /* no fb bound */
94352cf9 2292 if (!fb) {
a5071c2f 2293 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2294 return 0;
2295 }
2296
5826eca5
ED		 2297 if(intel_crtc->plane > dev_priv->num_pipe) {
2298 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2299 intel_crtc->plane,
2300 dev_priv->num_pipe);
5c3b82e2 2301 return -EINVAL;
79e53945
JB		 2302 }
2303
5c3b82e2 2304 mutex_lock(&dev->struct_mutex);
265db958 2305 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2306 to_intel_framebuffer(fb)->obj,
919926ae 2307 NULL);
5c3b82e2
CW		 2308 if (ret != 0) {
2309 mutex_unlock(&dev->struct_mutex);
a5071c2f 2310 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2311 return ret;
2312 }
79e53945 2313
94352cf9
DV		 2314 if (crtc->fb)
2315 intel_finish_fb(crtc->fb);
265db958 2316
94352cf9 2317 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2318 if (ret) {
94352cf9 2319 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2320 mutex_unlock(&dev->struct_mutex);
a5071c2f 2321 DRM_ERROR("failed to update base address\n");
4e6cfefc 2322 return ret;
79e53945 2323 }
3c4fdcfb 2324
94352cf9
DV		 2325 old_fb = crtc->fb;
2326 crtc->fb = fb;
6c4c86f5
DV		 2327 crtc->x = x;
2328 crtc->y = y;
94352cf9 2329
b7f1de28
CW		 2330 if (old_fb) {
2331 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2332 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2333 }
652c393a 2334
6b8e6ed0 2335 intel_update_fbc(dev);
5c3b82e2 2336 mutex_unlock(&dev->struct_mutex);
79e53945 2337
198598d0 2338 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2339
2340 return 0;
79e53945
JB		 2341}
2342
5eddb70b 2343static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2344{
2345 struct drm_device *dev = crtc->dev;
2346 struct drm_i915_private *dev_priv = dev->dev_private;
2347 u32 dpa_ctl;
2348
28c97730 2349 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2350 dpa_ctl = I915_READ(DP_A);
2351 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2352
2353 if (clock < 200000) {
2354 u32 temp;
2355 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2356 /* workaround for 160Mhz:
2357 1) program 0x4600c bits 15:0 = 0x8124
2358 2) program 0x46010 bit 0 = 1
2359 3) program 0x46034 bit 24 = 1
2360 4) program 0x64000 bit 14 = 1
2361 */
2362 temp = I915_READ(0x4600c);
2363 temp &= 0xffff0000;
2364 I915_WRITE(0x4600c, temp | 0x8124);
2365
2366 temp = I915_READ(0x46010);
2367 I915_WRITE(0x46010, temp | 1);
2368
2369 temp = I915_READ(0x46034);
2370 I915_WRITE(0x46034, temp | (1 << 24));
2371 } else {
2372 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2373 }
2374 I915_WRITE(DP_A, dpa_ctl);
2375
5eddb70b 2376 POSTING_READ(DP_A);
32f9d658
ZW		 2377 udelay(500);
2378}
2379
5e84e1a4
ZW		 2380static void intel_fdi_normal_train(struct drm_crtc *crtc)
2381{
2382 struct drm_device *dev = crtc->dev;
2383 struct drm_i915_private *dev_priv = dev->dev_private;
2384 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2385 int pipe = intel_crtc->pipe;
2386 u32 reg, temp;
2387
2388 /* enable normal train */
2389 reg = FDI_TX_CTL(pipe);
2390 temp = I915_READ(reg);
61e499bf 2391 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2392 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2393 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2394 } else {
2395 temp &= ~FDI_LINK_TRAIN_NONE;
2396 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2397 }
5e84e1a4
ZW		 2398 I915_WRITE(reg, temp);
2399
2400 reg = FDI_RX_CTL(pipe);
2401 temp = I915_READ(reg);
2402 if (HAS_PCH_CPT(dev)) {
2403 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2404 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2405 } else {
2406 temp &= ~FDI_LINK_TRAIN_NONE;
2407 temp |= FDI_LINK_TRAIN_NONE;
2408 }
2409 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2410
2411 /* wait one idle pattern time */
2412 POSTING_READ(reg);
2413 udelay(1000);
357555c0
JB		 2414
2415 /* IVB wants error correction enabled */
2416 if (IS_IVYBRIDGE(dev))
2417 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2418 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2419}
2420
291427f5
JB		 2421static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2422{
2423 struct drm_i915_private *dev_priv = dev->dev_private;
2424 u32 flags = I915_READ(SOUTH_CHICKEN1);
2425
2426 flags |= FDI_PHASE_SYNC_OVR(pipe);
2427 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2428 flags |= FDI_PHASE_SYNC_EN(pipe);
2429 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2430 POSTING_READ(SOUTH_CHICKEN1);
2431}
2432
01a415fd
DV		 2433static void ivb_modeset_global_resources(struct drm_device *dev)
2434{
2435 struct drm_i915_private *dev_priv = dev->dev_private;
2436 struct intel_crtc *pipe_B_crtc =
2437 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2438 struct intel_crtc *pipe_C_crtc =
2439 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2440 uint32_t temp;
2441
2442 /* When everything is off disable fdi C so that we could enable fdi B
2443 * with all lanes. XXX: This misses the case where a pipe is not using
2444 * any pch resources and so doesn't need any fdi lanes. */
2445 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2446 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2447 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2448
2449 temp = I915_READ(SOUTH_CHICKEN1);
2450 temp &= ~FDI_BC_BIFURCATION_SELECT;
2451 DRM_DEBUG_KMS("disabling fdi C rx\n");
2452 I915_WRITE(SOUTH_CHICKEN1, temp);
2453 }
2454}
2455
8db9d77b
ZW		 2456/* The FDI link training functions for ILK/Ibexpeak. */
2457static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2458{
2459 struct drm_device *dev = crtc->dev;
2460 struct drm_i915_private *dev_priv = dev->dev_private;
2461 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2462 int pipe = intel_crtc->pipe;
0fc932b8 2463 int plane = intel_crtc->plane;
5eddb70b 2464 u32 reg, temp, tries;
8db9d77b 2465
0fc932b8
JB		 2466 /* FDI needs bits from pipe & plane first */
2467 assert_pipe_enabled(dev_priv, pipe);
2468 assert_plane_enabled(dev_priv, plane);
2469
e1a44743
AJ		 2470 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2471 for train result */
5eddb70b
CW		 2472 reg = FDI_RX_IMR(pipe);
2473 temp = I915_READ(reg);
e1a44743
AJ		 2474 temp &= ~FDI_RX_SYMBOL_LOCK;
2475 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2476 I915_WRITE(reg, temp);
2477 I915_READ(reg);
e1a44743
AJ		 2478 udelay(150);
2479
8db9d77b 2480 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2481 reg = FDI_TX_CTL(pipe);
2482 temp = I915_READ(reg);
77ffb597
AJ		 2483 temp &= ~(7 << 19);
2484 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2485 temp &= ~FDI_LINK_TRAIN_NONE;
2486 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2487 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2488
5eddb70b
CW		 2489 reg = FDI_RX_CTL(pipe);
2490 temp = I915_READ(reg);
8db9d77b
ZW		 2491 temp &= ~FDI_LINK_TRAIN_NONE;
2492 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2493 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2494
2495 POSTING_READ(reg);
8db9d77b
ZW		 2496 udelay(150);
2497
5b2adf89 2498 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2499 if (HAS_PCH_IBX(dev)) {
2500 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2501 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2502 FDI_RX_PHASE_SYNC_POINTER_EN);
2503 }
5b2adf89 2504
5eddb70b 2505 reg = FDI_RX_IIR(pipe);
e1a44743 2506 for (tries = 0; tries < 5; tries++) {
5eddb70b 2507 temp = I915_READ(reg);
8db9d77b
ZW		 2508 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2509
2510 if ((temp & FDI_RX_BIT_LOCK)) {
2511 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2512 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2513 break;
2514 }
8db9d77b 2515 }
e1a44743 2516 if (tries == 5)
5eddb70b 2517 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2518
2519 /* Train 2 */
5eddb70b
CW		 2520 reg = FDI_TX_CTL(pipe);
2521 temp = I915_READ(reg);
8db9d77b
ZW		 2522 temp &= ~FDI_LINK_TRAIN_NONE;
2523 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2524 I915_WRITE(reg, temp);
8db9d77b 2525
5eddb70b
CW		 2526 reg = FDI_RX_CTL(pipe);
2527 temp = I915_READ(reg);
8db9d77b
ZW		 2528 temp &= ~FDI_LINK_TRAIN_NONE;
2529 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2530 I915_WRITE(reg, temp);
8db9d77b 2531
5eddb70b
CW		 2532 POSTING_READ(reg);
2533 udelay(150);
8db9d77b 2534
5eddb70b 2535 reg = FDI_RX_IIR(pipe);
e1a44743 2536 for (tries = 0; tries < 5; tries++) {
5eddb70b 2537 temp = I915_READ(reg);
8db9d77b
ZW		 2538 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2539
2540 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2541 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2542 DRM_DEBUG_KMS("FDI train 2 done.\n");
2543 break;
2544 }
8db9d77b 2545 }
e1a44743 2546 if (tries == 5)
5eddb70b 2547 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2548
2549 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2550
8db9d77b
ZW		 2551}
2552
0206e353 2553static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2554 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2555 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2556 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2557 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2558};
2559
2560/* The FDI link training functions for SNB/Cougarpoint. */
2561static void gen6_fdi_link_train(struct drm_crtc *crtc)
2562{
2563 struct drm_device *dev = crtc->dev;
2564 struct drm_i915_private *dev_priv = dev->dev_private;
2565 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2566 int pipe = intel_crtc->pipe;
fa37d39e 2567 u32 reg, temp, i, retry;
8db9d77b 2568
e1a44743
AJ		 2569 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2570 for train result */
5eddb70b
CW		 2571 reg = FDI_RX_IMR(pipe);
2572 temp = I915_READ(reg);
e1a44743
AJ		 2573 temp &= ~FDI_RX_SYMBOL_LOCK;
2574 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2575 I915_WRITE(reg, temp);
2576
2577 POSTING_READ(reg);
e1a44743
AJ		 2578 udelay(150);
2579
8db9d77b 2580 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2581 reg = FDI_TX_CTL(pipe);
2582 temp = I915_READ(reg);
77ffb597
AJ		 2583 temp &= ~(7 << 19);
2584 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2585 temp &= ~FDI_LINK_TRAIN_NONE;
2586 temp |= FDI_LINK_TRAIN_PATTERN_1;
2587 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2588 /* SNB-B */
2589 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2590 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2591
d74cf324
DV		 2592 I915_WRITE(FDI_RX_MISC(pipe),
2593 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2594
5eddb70b
CW		 2595 reg = FDI_RX_CTL(pipe);
2596 temp = I915_READ(reg);
8db9d77b
ZW		 2597 if (HAS_PCH_CPT(dev)) {
2598 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2599 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2600 } else {
2601 temp &= ~FDI_LINK_TRAIN_NONE;
2602 temp |= FDI_LINK_TRAIN_PATTERN_1;
2603 }
5eddb70b
CW		 2604 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2605
2606 POSTING_READ(reg);
8db9d77b
ZW		 2607 udelay(150);
2608
291427f5
JB		 2609 if (HAS_PCH_CPT(dev))
2610 cpt_phase_pointer_enable(dev, pipe);
2611
0206e353 2612 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2613 reg = FDI_TX_CTL(pipe);
2614 temp = I915_READ(reg);
8db9d77b
ZW		 2615 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2616 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2617 I915_WRITE(reg, temp);
2618
2619 POSTING_READ(reg);
8db9d77b
ZW		 2620 udelay(500);
2621
fa37d39e
SP		 2622 for (retry = 0; retry < 5; retry++) {
2623 reg = FDI_RX_IIR(pipe);
2624 temp = I915_READ(reg);
2625 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2626 if (temp & FDI_RX_BIT_LOCK) {
2627 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2628 DRM_DEBUG_KMS("FDI train 1 done.\n");
2629 break;
2630 }
2631 udelay(50);
8db9d77b 2632 }
fa37d39e
SP		 2633 if (retry < 5)
2634 break;
8db9d77b
ZW		 2635 }
2636 if (i == 4)
5eddb70b 2637 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2638
2639 /* Train 2 */
5eddb70b
CW		 2640 reg = FDI_TX_CTL(pipe);
2641 temp = I915_READ(reg);
8db9d77b
ZW		 2642 temp &= ~FDI_LINK_TRAIN_NONE;
2643 temp |= FDI_LINK_TRAIN_PATTERN_2;
2644 if (IS_GEN6(dev)) {
2645 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2646 /* SNB-B */
2647 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2648 }
5eddb70b 2649 I915_WRITE(reg, temp);
8db9d77b 2650
5eddb70b
CW		 2651 reg = FDI_RX_CTL(pipe);
2652 temp = I915_READ(reg);
8db9d77b
ZW		 2653 if (HAS_PCH_CPT(dev)) {
2654 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2655 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2656 } else {
2657 temp &= ~FDI_LINK_TRAIN_NONE;
2658 temp |= FDI_LINK_TRAIN_PATTERN_2;
2659 }
5eddb70b
CW		 2660 I915_WRITE(reg, temp);
2661
2662 POSTING_READ(reg);
8db9d77b
ZW		 2663 udelay(150);
2664
0206e353 2665 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2666 reg = FDI_TX_CTL(pipe);
2667 temp = I915_READ(reg);
8db9d77b
ZW		 2668 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2669 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2670 I915_WRITE(reg, temp);
2671
2672 POSTING_READ(reg);
8db9d77b
ZW		 2673 udelay(500);
2674
fa37d39e
SP		 2675 for (retry = 0; retry < 5; retry++) {
2676 reg = FDI_RX_IIR(pipe);
2677 temp = I915_READ(reg);
2678 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2679 if (temp & FDI_RX_SYMBOL_LOCK) {
2680 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2681 DRM_DEBUG_KMS("FDI train 2 done.\n");
2682 break;
2683 }
2684 udelay(50);
8db9d77b 2685 }
fa37d39e
SP		 2686 if (retry < 5)
2687 break;
8db9d77b
ZW		 2688 }
2689 if (i == 4)
5eddb70b 2690 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2691
2692 DRM_DEBUG_KMS("FDI train done.\n");
2693}
2694
357555c0
JB		 2695/* Manual link training for Ivy Bridge A0 parts */
2696static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2697{
2698 struct drm_device *dev = crtc->dev;
2699 struct drm_i915_private *dev_priv = dev->dev_private;
2700 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2701 int pipe = intel_crtc->pipe;
2702 u32 reg, temp, i;
2703
2704 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2705 for train result */
2706 reg = FDI_RX_IMR(pipe);
2707 temp = I915_READ(reg);
2708 temp &= ~FDI_RX_SYMBOL_LOCK;
2709 temp &= ~FDI_RX_BIT_LOCK;
2710 I915_WRITE(reg, temp);
2711
2712 POSTING_READ(reg);
2713 udelay(150);
2714
01a415fd
DV		 2715 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2716 I915_READ(FDI_RX_IIR(pipe)));
2717
357555c0
JB		 2718 /* enable CPU FDI TX and PCH FDI RX */
2719 reg = FDI_TX_CTL(pipe);
2720 temp = I915_READ(reg);
2721 temp &= ~(7 << 19);
2722 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2723 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2724 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2725 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2726 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2727 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2728 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2729
d74cf324
DV		 2730 I915_WRITE(FDI_RX_MISC(pipe),
2731 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2732
357555c0
JB		 2733 reg = FDI_RX_CTL(pipe);
2734 temp = I915_READ(reg);
2735 temp &= ~FDI_LINK_TRAIN_AUTO;
2736 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2737 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2738 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2739 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2740
2741 POSTING_READ(reg);
2742 udelay(150);
2743
291427f5
JB		 2744 if (HAS_PCH_CPT(dev))
2745 cpt_phase_pointer_enable(dev, pipe);
2746
0206e353 2747 for (i = 0; i < 4; i++) {
357555c0
JB		 2748 reg = FDI_TX_CTL(pipe);
2749 temp = I915_READ(reg);
2750 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2751 temp |= snb_b_fdi_train_param[i];
2752 I915_WRITE(reg, temp);
2753
2754 POSTING_READ(reg);
2755 udelay(500);
2756
2757 reg = FDI_RX_IIR(pipe);
2758 temp = I915_READ(reg);
2759 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2760
2761 if (temp & FDI_RX_BIT_LOCK ||
2762 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2763 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2764 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2765 break;
2766 }
2767 }
2768 if (i == 4)
2769 DRM_ERROR("FDI train 1 fail!\n");
2770
2771 /* Train 2 */
2772 reg = FDI_TX_CTL(pipe);
2773 temp = I915_READ(reg);
2774 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2775 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2776 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2777 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2778 I915_WRITE(reg, temp);
2779
2780 reg = FDI_RX_CTL(pipe);
2781 temp = I915_READ(reg);
2782 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2783 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2784 I915_WRITE(reg, temp);
2785
2786 POSTING_READ(reg);
2787 udelay(150);
2788
0206e353 2789 for (i = 0; i < 4; i++) {
357555c0
JB		 2790 reg = FDI_TX_CTL(pipe);
2791 temp = I915_READ(reg);
2792 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2793 temp |= snb_b_fdi_train_param[i];
2794 I915_WRITE(reg, temp);
2795
2796 POSTING_READ(reg);
2797 udelay(500);
2798
2799 reg = FDI_RX_IIR(pipe);
2800 temp = I915_READ(reg);
2801 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2802
2803 if (temp & FDI_RX_SYMBOL_LOCK) {
2804 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2805 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2806 break;
2807 }
2808 }
2809 if (i == 4)
2810 DRM_ERROR("FDI train 2 fail!\n");
2811
2812 DRM_DEBUG_KMS("FDI train done.\n");
2813}
2814
88cefb6c 2815static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2816{
88cefb6c 2817 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2818 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2819 int pipe = intel_crtc->pipe;
5eddb70b 2820 u32 reg, temp;
79e53945 2821
c64e311e 2822
c98e9dcf 2823 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2824 reg = FDI_RX_CTL(pipe);
2825 temp = I915_READ(reg);
2826 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2827 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2828 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2829 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2830
2831 POSTING_READ(reg);
c98e9dcf
JB		 2832 udelay(200);
2833
2834 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2835 temp = I915_READ(reg);
2836 I915_WRITE(reg, temp | FDI_PCDCLK);
2837
2838 POSTING_READ(reg);
c98e9dcf
JB		 2839 udelay(200);
2840
bf507ef7
ED		 2841 /* On Haswell, the PLL configuration for ports and pipes is handled
2842 * separately, as part of DDI setup */
2843 if (!IS_HASWELL(dev)) {
2844 /* Enable CPU FDI TX PLL, always on for Ironlake */
2845 reg = FDI_TX_CTL(pipe);
2846 temp = I915_READ(reg);
2847 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2848 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2849
bf507ef7
ED		 2850 POSTING_READ(reg);
2851 udelay(100);
2852 }
6be4a607 2853 }
0e23b99d
JB		 2854}
2855
88cefb6c
DV		 2856static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2857{
2858 struct drm_device *dev = intel_crtc->base.dev;
2859 struct drm_i915_private *dev_priv = dev->dev_private;
2860 int pipe = intel_crtc->pipe;
2861 u32 reg, temp;
2862
2863 /* Switch from PCDclk to Rawclk */
2864 reg = FDI_RX_CTL(pipe);
2865 temp = I915_READ(reg);
2866 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2867
2868 /* Disable CPU FDI TX PLL */
2869 reg = FDI_TX_CTL(pipe);
2870 temp = I915_READ(reg);
2871 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2872
2873 POSTING_READ(reg);
2874 udelay(100);
2875
2876 reg = FDI_RX_CTL(pipe);
2877 temp = I915_READ(reg);
2878 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2879
2880 /* Wait for the clocks to turn off. */
2881 POSTING_READ(reg);
2882 udelay(100);
2883}
2884
291427f5
JB		 2885static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2886{
2887 struct drm_i915_private *dev_priv = dev->dev_private;
2888 u32 flags = I915_READ(SOUTH_CHICKEN1);
2889
2890 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2891 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2892 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2893 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2894 POSTING_READ(SOUTH_CHICKEN1);
2895}
0fc932b8
JB		 2896static void ironlake_fdi_disable(struct drm_crtc *crtc)
2897{
2898 struct drm_device *dev = crtc->dev;
2899 struct drm_i915_private *dev_priv = dev->dev_private;
2900 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2901 int pipe = intel_crtc->pipe;
2902 u32 reg, temp;
2903
2904 /* disable CPU FDI tx and PCH FDI rx */
2905 reg = FDI_TX_CTL(pipe);
2906 temp = I915_READ(reg);
2907 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2908 POSTING_READ(reg);
2909
2910 reg = FDI_RX_CTL(pipe);
2911 temp = I915_READ(reg);
2912 temp &= ~(0x7 << 16);
2913 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2914 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2915
2916 POSTING_READ(reg);
2917 udelay(100);
2918
2919 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2920 if (HAS_PCH_IBX(dev)) {
2921 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2922 I915_WRITE(FDI_RX_CHICKEN(pipe),
2923 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2924 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2925 } else if (HAS_PCH_CPT(dev)) {
2926 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2927 }
0fc932b8
JB		 2928
2929 /* still set train pattern 1 */
2930 reg = FDI_TX_CTL(pipe);
2931 temp = I915_READ(reg);
2932 temp &= ~FDI_LINK_TRAIN_NONE;
2933 temp |= FDI_LINK_TRAIN_PATTERN_1;
2934 I915_WRITE(reg, temp);
2935
2936 reg = FDI_RX_CTL(pipe);
2937 temp = I915_READ(reg);
2938 if (HAS_PCH_CPT(dev)) {
2939 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2940 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2941 } else {
2942 temp &= ~FDI_LINK_TRAIN_NONE;
2943 temp |= FDI_LINK_TRAIN_PATTERN_1;
2944 }
2945 /* BPC in FDI rx is consistent with that in PIPECONF */
2946 temp &= ~(0x07 << 16);
2947 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2948 I915_WRITE(reg, temp);
2949
2950 POSTING_READ(reg);
2951 udelay(100);
2952}
2953
5bb61643
CW		 2954static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2955{
2956 struct drm_device *dev = crtc->dev;
2957 struct drm_i915_private *dev_priv = dev->dev_private;
2958 unsigned long flags;
2959 bool pending;
2960
2961 if (atomic_read(&dev_priv->mm.wedged))
2962 return false;
2963
2964 spin_lock_irqsave(&dev->event_lock, flags);
2965 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2966 spin_unlock_irqrestore(&dev->event_lock, flags);
2967
2968 return pending;
2969}
2970
e6c3a2a6
CW		 2971static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2972{
0f91128d 2973 struct drm_device *dev = crtc->dev;
5bb61643 2974 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2975
2976 if (crtc->fb == NULL)
2977 return;
2978
5bb61643
CW		 2979 wait_event(dev_priv->pending_flip_queue,
2980 !intel_crtc_has_pending_flip(crtc));
2981
0f91128d
CW		 2982 mutex_lock(&dev->struct_mutex);
2983 intel_finish_fb(crtc->fb);
2984 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2985}
2986
fc316cbe 2987static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
040484af
JB		 2988{
2989 struct drm_device *dev = crtc->dev;
228d3e36 2990 struct intel_encoder *intel_encoder;
040484af
JB		 2991
2992 /*
2993 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2994 * must be driven by its own crtc; no sharing is possible.
2995 */
228d3e36 2996 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
228d3e36 2997 switch (intel_encoder->type) {
040484af 2998 case INTEL_OUTPUT_EDP:
228d3e36 2999 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
040484af
JB		 3000 return false;
3001 continue;
3002 }
3003 }
3004
3005 return true;
3006}
3007
fc316cbe
PZ		 3008static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
3009{
3010 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
3011}
3012
e615efe4
ED		 3013/* Program iCLKIP clock to the desired frequency */
3014static void lpt_program_iclkip(struct drm_crtc *crtc)
3015{
3016 struct drm_device *dev = crtc->dev;
3017 struct drm_i915_private *dev_priv = dev->dev_private;
3018 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3019 u32 temp;
3020
3021 /* It is necessary to ungate the pixclk gate prior to programming
3022 * the divisors, and gate it back when it is done.
3023 */
3024 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3025
3026 /* Disable SSCCTL */
3027 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3028 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
3029 SBI_SSCCTL_DISABLE);
3030
3031 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3032 if (crtc->mode.clock == 20000) {
3033 auxdiv = 1;
3034 divsel = 0x41;
3035 phaseinc = 0x20;
3036 } else {
3037 /* The iCLK virtual clock root frequency is in MHz,
3038 * but the crtc->mode.clock in in KHz. To get the divisors,
3039 * it is necessary to divide one by another, so we
3040 * convert the virtual clock precision to KHz here for higher
3041 * precision.
3042 */
3043 u32 iclk_virtual_root_freq = 172800 * 1000;
3044 u32 iclk_pi_range = 64;
3045 u32 desired_divisor, msb_divisor_value, pi_value;
3046
3047 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3048 msb_divisor_value = desired_divisor / iclk_pi_range;
3049 pi_value = desired_divisor % iclk_pi_range;
3050
3051 auxdiv = 0;
3052 divsel = msb_divisor_value - 2;
3053 phaseinc = pi_value;
3054 }
3055
3056 /* This should not happen with any sane values */
3057 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3058 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3059 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3060 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3061
3062 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3063 crtc->mode.clock,
3064 auxdiv,
3065 divsel,
3066 phasedir,
3067 phaseinc);
3068
3069 /* Program SSCDIVINTPHASE6 */
3070 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
3071 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3072 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3073 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3074 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3075 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3076 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3077
3078 intel_sbi_write(dev_priv,
3079 SBI_SSCDIVINTPHASE6,
3080 temp);
3081
3082 /* Program SSCAUXDIV */
3083 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
3084 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3085 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3086 intel_sbi_write(dev_priv,
3087 SBI_SSCAUXDIV6,
3088 temp);
3089
3090
3091 /* Enable modulator and associated divider */
3092 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
3093 temp &= ~SBI_SSCCTL_DISABLE;
3094 intel_sbi_write(dev_priv,
3095 SBI_SSCCTL6,
3096 temp);
3097
3098 /* Wait for initialization time */
3099 udelay(24);
3100
3101 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3102}
3103
f67a559d
JB		 3104/*
3105 * Enable PCH resources required for PCH ports:
3106 * - PCH PLLs
3107 * - FDI training & RX/TX
3108 * - update transcoder timings
3109 * - DP transcoding bits
3110 * - transcoder
3111 */
3112static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3113{
3114 struct drm_device *dev = crtc->dev;
3115 struct drm_i915_private *dev_priv = dev->dev_private;
3116 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3117 int pipe = intel_crtc->pipe;
ee7b9f93 3118 u32 reg, temp;
2c07245f 3119
e7e164db
CW		 3120 assert_transcoder_disabled(dev_priv, pipe);
3121
cd986abb
DV		 3122 /* Write the TU size bits before fdi link training, so that error
3123 * detection works. */
3124 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3125 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3126
c98e9dcf 3127 /* For PCH output, training FDI link */
674cf967 3128 dev_priv->display.fdi_link_train(crtc);
2c07245f 3129
572deb37
DV		 3130 /* XXX: pch pll's can be enabled any time before we enable the PCH
3131 * transcoder, and we actually should do this to not upset any PCH
3132 * transcoder that already use the clock when we share it.
3133 *
3134 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3135 * unconditionally resets the pll - we need that to have the right LVDS
3136 * enable sequence. */
b6b4e185 3137 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3138
303b81e0 3139 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3140 u32 sel;
4b645f14 3141
c98e9dcf 3142 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3143 switch (pipe) {
3144 default:
3145 case 0:
3146 temp |= TRANSA_DPLL_ENABLE;
3147 sel = TRANSA_DPLLB_SEL;
3148 break;
3149 case 1:
3150 temp |= TRANSB_DPLL_ENABLE;
3151 sel = TRANSB_DPLLB_SEL;
3152 break;
3153 case 2:
3154 temp |= TRANSC_DPLL_ENABLE;
3155 sel = TRANSC_DPLLB_SEL;
3156 break;
d64311ab 3157 }
ee7b9f93
JB		 3158 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3159 temp |= sel;
3160 else
3161 temp &= ~sel;
c98e9dcf 3162 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3163 }
5eddb70b 3164
d9b6cb56
JB		 3165 /* set transcoder timing, panel must allow it */
3166 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3167 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3168 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3169 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3170
5eddb70b
CW		 3171 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3172 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3173 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3174 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3175
303b81e0 3176 intel_fdi_normal_train(crtc);
5e84e1a4 3177
c98e9dcf
JB		 3178 /* For PCH DP, enable TRANS_DP_CTL */
3179 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3180 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3181 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 3182 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 3183 reg = TRANS_DP_CTL(pipe);
3184 temp = I915_READ(reg);
3185 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3186 TRANS_DP_SYNC_MASK |
3187 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3188 temp |= (TRANS_DP_OUTPUT_ENABLE |
3189 TRANS_DP_ENH_FRAMING);
9325c9f0 3190 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3191
3192 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3193 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3194 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3195 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3196
3197 switch (intel_trans_dp_port_sel(crtc)) {
3198 case PCH_DP_B:
5eddb70b 3199 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3200 break;
3201 case PCH_DP_C:
5eddb70b 3202 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3203 break;
3204 case PCH_DP_D:
5eddb70b 3205 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3206 break;
3207 default:
e95d41e1 3208 BUG();
32f9d658 3209 }
2c07245f 3210
5eddb70b 3211 I915_WRITE(reg, temp);
6be4a607 3212 }
b52eb4dc 3213
b8a4f404 3214 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3215}
3216
1507e5bd
PZ		 3217static void lpt_pch_enable(struct drm_crtc *crtc)
3218{
3219 struct drm_device *dev = crtc->dev;
3220 struct drm_i915_private *dev_priv = dev->dev_private;
3221 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3222 int pipe = intel_crtc->pipe;
daed2dbb 3223 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
1507e5bd 3224
daed2dbb 3225 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd
PZ		 3226
3227 /* Write the TU size bits before fdi link training, so that error
3228 * detection works. */
3229 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3230 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3231
3232 /* For PCH output, training FDI link */
3233 dev_priv->display.fdi_link_train(crtc);
3234
8c52b5e8 3235 lpt_program_iclkip(crtc);
1507e5bd 3236
0540e488 3237 /* Set transcoder timing. */
daed2dbb
PZ		 3238 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3239 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3240 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
1507e5bd 3241
daed2dbb
PZ		 3242 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3243 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3244 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3245 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
1507e5bd 3246
8fb033d7 3247 lpt_enable_pch_transcoder(dev_priv, intel_crtc->pipe);
1507e5bd
PZ		 3248}
3249
ee7b9f93
JB		 3250static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3251{
3252 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3253
3254 if (pll == NULL)
3255 return;
3256
3257 if (pll->refcount == 0) {
3258 WARN(1, "bad PCH PLL refcount\n");
3259 return;
3260 }
3261
3262 --pll->refcount;
3263 intel_crtc->pch_pll = NULL;
3264}
3265
3266static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3267{
3268 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3269 struct intel_pch_pll *pll;
3270 int i;
3271
3272 pll = intel_crtc->pch_pll;
3273 if (pll) {
3274 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3275 intel_crtc->base.base.id, pll->pll_reg);
3276 goto prepare;
3277 }
3278
98b6bd99
DV		 3279 if (HAS_PCH_IBX(dev_priv->dev)) {
3280 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3281 i = intel_crtc->pipe;
3282 pll = &dev_priv->pch_plls[i];
3283
3284 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3285 intel_crtc->base.base.id, pll->pll_reg);
3286
3287 goto found;
3288 }
3289
ee7b9f93
JB		 3290 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3291 pll = &dev_priv->pch_plls[i];
3292
3293 /* Only want to check enabled timings first */
3294 if (pll->refcount == 0)
3295 continue;
3296
3297 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3298 fp == I915_READ(pll->fp0_reg)) {
3299 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3300 intel_crtc->base.base.id,
3301 pll->pll_reg, pll->refcount, pll->active);
3302
3303 goto found;
3304 }
3305 }
3306
3307 /* Ok no matching timings, maybe there's a free one? */
3308 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3309 pll = &dev_priv->pch_plls[i];
3310 if (pll->refcount == 0) {
3311 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3312 intel_crtc->base.base.id, pll->pll_reg);
3313 goto found;
3314 }
3315 }
3316
3317 return NULL;
3318
3319found:
3320 intel_crtc->pch_pll = pll;
3321 pll->refcount++;
3322 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3323prepare: /* separate function? */
3324 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3325
e04c7350
CW		 3326 /* Wait for the clocks to stabilize before rewriting the regs */
3327 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3328 POSTING_READ(pll->pll_reg);
3329 udelay(150);
e04c7350
CW		 3330
3331 I915_WRITE(pll->fp0_reg, fp);
3332 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3333 pll->on = false;
3334 return pll;
3335}
3336
d4270e57
JB		 3337void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3338{
3339 struct drm_i915_private *dev_priv = dev->dev_private;
3340 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3341 u32 temp;
3342
3343 temp = I915_READ(dslreg);
3344 udelay(500);
3345 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3346 /* Without this, mode sets may fail silently on FDI */
3347 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3348 udelay(250);
3349 I915_WRITE(tc2reg, 0);
3350 if (wait_for(I915_READ(dslreg) != temp, 5))
3351 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3352 }
3353}
3354
f67a559d
JB		 3355static void ironlake_crtc_enable(struct drm_crtc *crtc)
3356{
3357 struct drm_device *dev = crtc->dev;
3358 struct drm_i915_private *dev_priv = dev->dev_private;
3359 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3360 struct intel_encoder *encoder;
f67a559d
JB		 3361 int pipe = intel_crtc->pipe;
3362 int plane = intel_crtc->plane;
3363 u32 temp;
3364 bool is_pch_port;
3365
08a48469
DV		 3366 WARN_ON(!crtc->enabled);
3367
f67a559d
JB		 3368 if (intel_crtc->active)
3369 return;
3370
3371 intel_crtc->active = true;
3372 intel_update_watermarks(dev);
3373
3374 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3375 temp = I915_READ(PCH_LVDS);
3376 if ((temp & LVDS_PORT_EN) == 0)
3377 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3378 }
3379
fc316cbe 3380 is_pch_port = ironlake_crtc_driving_pch(crtc);
f67a559d 3381
46b6f814 3382 if (is_pch_port) {
fff367c7
DV		 3383 /* Note: FDI PLL enabling _must_ be done before we enable the
3384 * cpu pipes, hence this is separate from all the other fdi/pch
3385 * enabling. */
88cefb6c 3386 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3387 } else {
3388 assert_fdi_tx_disabled(dev_priv, pipe);
3389 assert_fdi_rx_disabled(dev_priv, pipe);
3390 }
f67a559d 3391
bf49ec8c
DV		 3392 for_each_encoder_on_crtc(dev, crtc, encoder)
3393 if (encoder->pre_enable)
3394 encoder->pre_enable(encoder);
3395
f67a559d
JB		 3396 /* Enable panel fitting for LVDS */
3397 if (dev_priv->pch_pf_size &&
3398 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3399 /* Force use of hard-coded filter coefficients
3400 * as some pre-programmed values are broken,
3401 * e.g. x201.
3402 */
9db4a9c7
JB		 3403 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3404 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3405 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3406 }
3407
9c54c0dd
JB		 3408 /*
3409 * On ILK+ LUT must be loaded before the pipe is running but with
3410 * clocks enabled
3411 */
3412 intel_crtc_load_lut(crtc);
3413
f67a559d
JB		 3414 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3415 intel_enable_plane(dev_priv, plane, pipe);
3416
3417 if (is_pch_port)
3418 ironlake_pch_enable(crtc);
c98e9dcf 3419
d1ebd816 3420 mutex_lock(&dev->struct_mutex);
bed4a673 3421 intel_update_fbc(dev);
d1ebd816
BW		 3422 mutex_unlock(&dev->struct_mutex);
3423
6b383a7f 3424 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3425
fa5c73b1
DV		 3426 for_each_encoder_on_crtc(dev, crtc, encoder)
3427 encoder->enable(encoder);
61b77ddd
DV		 3428
3429 if (HAS_PCH_CPT(dev))
3430 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3431
3432 /*
3433 * There seems to be a race in PCH platform hw (at least on some
3434 * outputs) where an enabled pipe still completes any pageflip right
3435 * away (as if the pipe is off) instead of waiting for vblank. As soon
3436 * as the first vblank happend, everything works as expected. Hence just
3437 * wait for one vblank before returning to avoid strange things
3438 * happening.
3439 */
3440 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3441}
3442
4f771f10
PZ		 3443static void haswell_crtc_enable(struct drm_crtc *crtc)
3444{
3445 struct drm_device *dev = crtc->dev;
3446 struct drm_i915_private *dev_priv = dev->dev_private;
3447 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3448 struct intel_encoder *encoder;
3449 int pipe = intel_crtc->pipe;
3450 int plane = intel_crtc->plane;
4f771f10
PZ		 3451 bool is_pch_port;
3452
3453 WARN_ON(!crtc->enabled);
3454
3455 if (intel_crtc->active)
3456 return;
3457
3458 intel_crtc->active = true;
3459 intel_update_watermarks(dev);
3460
fc316cbe 3461 is_pch_port = haswell_crtc_driving_pch(crtc);
4f771f10 3462
83616634 3463 if (is_pch_port)
4f771f10 3464 ironlake_fdi_pll_enable(intel_crtc);
4f771f10
PZ		 3465
3466 for_each_encoder_on_crtc(dev, crtc, encoder)
3467 if (encoder->pre_enable)
3468 encoder->pre_enable(encoder);
3469
1f544388 3470 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3471
1f544388
PZ		 3472 /* Enable panel fitting for eDP */
3473 if (dev_priv->pch_pf_size && HAS_eDP) {
4f771f10
PZ		 3474 /* Force use of hard-coded filter coefficients
3475 * as some pre-programmed values are broken,
3476 * e.g. x201.
3477 */
3478 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3479 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3480 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3481 }
3482
3483 /*
3484 * On ILK+ LUT must be loaded before the pipe is running but with
3485 * clocks enabled
3486 */
3487 intel_crtc_load_lut(crtc);
3488
1f544388
PZ		 3489 intel_ddi_set_pipe_settings(crtc);
3490 intel_ddi_enable_pipe_func(crtc);
4f771f10
PZ		 3491
3492 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3493 intel_enable_plane(dev_priv, plane, pipe);
3494
3495 if (is_pch_port)
1507e5bd 3496 lpt_pch_enable(crtc);
4f771f10
PZ		 3497
3498 mutex_lock(&dev->struct_mutex);
3499 intel_update_fbc(dev);
3500 mutex_unlock(&dev->struct_mutex);
3501
3502 intel_crtc_update_cursor(crtc, true);
3503
3504 for_each_encoder_on_crtc(dev, crtc, encoder)
3505 encoder->enable(encoder);
3506
4f771f10
PZ		 3507 /*
3508 * There seems to be a race in PCH platform hw (at least on some
3509 * outputs) where an enabled pipe still completes any pageflip right
3510 * away (as if the pipe is off) instead of waiting for vblank. As soon
3511 * as the first vblank happend, everything works as expected. Hence just
3512 * wait for one vblank before returning to avoid strange things
3513 * happening.
3514 */
3515 intel_wait_for_vblank(dev, intel_crtc->pipe);
3516}
3517
6be4a607
JB		 3518static void ironlake_crtc_disable(struct drm_crtc *crtc)
3519{
3520 struct drm_device *dev = crtc->dev;
3521 struct drm_i915_private *dev_priv = dev->dev_private;
3522 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3523 struct intel_encoder *encoder;
6be4a607
JB		 3524 int pipe = intel_crtc->pipe;
3525 int plane = intel_crtc->plane;
5eddb70b 3526 u32 reg, temp;
b52eb4dc 3527
ef9c3aee 3528
f7abfe8b
CW		 3529 if (!intel_crtc->active)
3530 return;
3531
ea9d758d
DV		 3532 for_each_encoder_on_crtc(dev, crtc, encoder)
3533 encoder->disable(encoder);
3534
e6c3a2a6 3535 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3536 drm_vblank_off(dev, pipe);
6b383a7f 3537 intel_crtc_update_cursor(crtc, false);
5eddb70b 3538
b24e7179 3539 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3540
973d04f9
CW		 3541 if (dev_priv->cfb_plane == plane)
3542 intel_disable_fbc(dev);
2c07245f 3543
b24e7179 3544 intel_disable_pipe(dev_priv, pipe);
32f9d658 3545
6be4a607 3546 /* Disable PF */
9db4a9c7
JB		 3547 I915_WRITE(PF_CTL(pipe), 0);
3548 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3549
bf49ec8c
DV		 3550 for_each_encoder_on_crtc(dev, crtc, encoder)
3551 if (encoder->post_disable)
3552 encoder->post_disable(encoder);
3553
0fc932b8 3554 ironlake_fdi_disable(crtc);
2c07245f 3555
b8a4f404 3556 ironlake_disable_pch_transcoder(dev_priv, pipe);
913d8d11 3557
6be4a607
JB		 3558 if (HAS_PCH_CPT(dev)) {
3559 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3560 reg = TRANS_DP_CTL(pipe);
3561 temp = I915_READ(reg);
3562 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3563 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3564 I915_WRITE(reg, temp);
6be4a607
JB		 3565
3566 /* disable DPLL_SEL */
3567 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3568 switch (pipe) {
3569 case 0:
d64311ab 3570 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3571 break;
3572 case 1:
6be4a607 3573 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3574 break;
3575 case 2:
4b645f14 3576 /* C shares PLL A or B */
d64311ab 3577 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3578 break;
3579 default:
3580 BUG(); /* wtf */
3581 }
6be4a607 3582 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3583 }
e3421a18 3584
6be4a607 3585 /* disable PCH DPLL */
ee7b9f93 3586 intel_disable_pch_pll(intel_crtc);
8db9d77b 3587
88cefb6c 3588 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3589
f7abfe8b 3590 intel_crtc->active = false;
6b383a7f 3591 intel_update_watermarks(dev);
d1ebd816
BW		 3592
3593 mutex_lock(&dev->struct_mutex);
6b383a7f 3594 intel_update_fbc(dev);
d1ebd816 3595 mutex_unlock(&dev->struct_mutex);
6be4a607 3596}
1b3c7a47 3597
4f771f10
PZ		 3598static void haswell_crtc_disable(struct drm_crtc *crtc)
3599{
3600 struct drm_device *dev = crtc->dev;
3601 struct drm_i915_private *dev_priv = dev->dev_private;
3602 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3603 struct intel_encoder *encoder;
3604 int pipe = intel_crtc->pipe;
3605 int plane = intel_crtc->plane;
ad80a810 3606 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
83616634 3607 bool is_pch_port;
4f771f10
PZ		 3608
3609 if (!intel_crtc->active)
3610 return;
3611
83616634
PZ		 3612 is_pch_port = haswell_crtc_driving_pch(crtc);
3613
4f771f10
PZ		 3614 for_each_encoder_on_crtc(dev, crtc, encoder)
3615 encoder->disable(encoder);
3616
3617 intel_crtc_wait_for_pending_flips(crtc);
3618 drm_vblank_off(dev, pipe);
3619 intel_crtc_update_cursor(crtc, false);
3620
3621 intel_disable_plane(dev_priv, plane, pipe);
3622
3623 if (dev_priv->cfb_plane == plane)
3624 intel_disable_fbc(dev);
3625
3626 intel_disable_pipe(dev_priv, pipe);
3627
ad80a810 3628 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10
PZ		 3629
3630 /* Disable PF */
3631 I915_WRITE(PF_CTL(pipe), 0);
3632 I915_WRITE(PF_WIN_SZ(pipe), 0);
3633
1f544388 3634 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3635
3636 for_each_encoder_on_crtc(dev, crtc, encoder)
3637 if (encoder->post_disable)
3638 encoder->post_disable(encoder);
3639
83616634
PZ		 3640 if (is_pch_port) {
3641 ironlake_fdi_disable(crtc);
8fb033d7 3642 lpt_disable_pch_transcoder(dev_priv, pipe);
83616634
PZ		 3643 intel_disable_pch_pll(intel_crtc);
3644 ironlake_fdi_pll_disable(intel_crtc);
3645 }
4f771f10
PZ		 3646
3647 intel_crtc->active = false;
3648 intel_update_watermarks(dev);
3649
3650 mutex_lock(&dev->struct_mutex);
3651 intel_update_fbc(dev);
3652 mutex_unlock(&dev->struct_mutex);
3653}
3654
ee7b9f93
JB		 3655static void ironlake_crtc_off(struct drm_crtc *crtc)
3656{
3657 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3658 intel_put_pch_pll(intel_crtc);
3659}
3660
6441ab5f
PZ		 3661static void haswell_crtc_off(struct drm_crtc *crtc)
3662{
a5c961d1
PZ		 3663 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3664
3665 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3666 * start using it. */
3667 intel_crtc->cpu_transcoder = intel_crtc->pipe;
3668
6441ab5f
PZ		 3669 intel_ddi_put_crtc_pll(crtc);
3670}
3671
02e792fb
DV		 3672static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3673{
02e792fb 3674 if (!enable && intel_crtc->overlay) {
23f09ce3 3675 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3676 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3677
23f09ce3 3678 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3679 dev_priv->mm.interruptible = false;
3680 (void) intel_overlay_switch_off(intel_crtc->overlay);
3681 dev_priv->mm.interruptible = true;
23f09ce3 3682 mutex_unlock(&dev->struct_mutex);
02e792fb 3683 }
02e792fb 3684
5dcdbcb0
CW		 3685 /* Let userspace switch the overlay on again. In most cases userspace
3686 * has to recompute where to put it anyway.
3687 */
02e792fb
DV		 3688}
3689
0b8765c6 3690static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3691{
3692 struct drm_device *dev = crtc->dev;
79e53945
JB		 3693 struct drm_i915_private *dev_priv = dev->dev_private;
3694 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3695 struct intel_encoder *encoder;
79e53945 3696 int pipe = intel_crtc->pipe;
80824003 3697 int plane = intel_crtc->plane;
79e53945 3698
08a48469
DV		 3699 WARN_ON(!crtc->enabled);
3700
f7abfe8b
CW		 3701 if (intel_crtc->active)
3702 return;
3703
3704 intel_crtc->active = true;
6b383a7f
CW		 3705 intel_update_watermarks(dev);
3706
63d7bbe9 3707 intel_enable_pll(dev_priv, pipe);
040484af 3708 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3709 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3710
0b8765c6 3711 intel_crtc_load_lut(crtc);
bed4a673 3712 intel_update_fbc(dev);
79e53945 3713
0b8765c6
JB		 3714 /* Give the overlay scaler a chance to enable if it's on this pipe */
3715 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3716 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3717
fa5c73b1
DV		 3718 for_each_encoder_on_crtc(dev, crtc, encoder)
3719 encoder->enable(encoder);
0b8765c6 3720}
79e53945 3721
0b8765c6
JB		 3722static void i9xx_crtc_disable(struct drm_crtc *crtc)
3723{
3724 struct drm_device *dev = crtc->dev;
3725 struct drm_i915_private *dev_priv = dev->dev_private;
3726 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3727 struct intel_encoder *encoder;
0b8765c6
JB		 3728 int pipe = intel_crtc->pipe;
3729 int plane = intel_crtc->plane;
b690e96c 3730
ef9c3aee 3731
f7abfe8b
CW		 3732 if (!intel_crtc->active)
3733 return;
3734
ea9d758d
DV		 3735 for_each_encoder_on_crtc(dev, crtc, encoder)
3736 encoder->disable(encoder);
3737
0b8765c6 3738 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3739 intel_crtc_wait_for_pending_flips(crtc);
3740 drm_vblank_off(dev, pipe);
0b8765c6 3741 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3742 intel_crtc_update_cursor(crtc, false);
0b8765c6 3743
973d04f9
CW		 3744 if (dev_priv->cfb_plane == plane)
3745 intel_disable_fbc(dev);
79e53945 3746
b24e7179 3747 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3748 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3749 intel_disable_pll(dev_priv, pipe);
0b8765c6 3750
f7abfe8b 3751 intel_crtc->active = false;
6b383a7f
CW		 3752 intel_update_fbc(dev);
3753 intel_update_watermarks(dev);
0b8765c6
JB		 3754}
3755
ee7b9f93
JB		 3756static void i9xx_crtc_off(struct drm_crtc *crtc)
3757{
3758}
3759
976f8a20
DV		 3760static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3761 bool enabled)
2c07245f
ZW		 3762{
3763 struct drm_device *dev = crtc->dev;
3764 struct drm_i915_master_private *master_priv;
3765 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3766 int pipe = intel_crtc->pipe;
79e53945
JB		 3767
3768 if (!dev->primary->master)
3769 return;
3770
3771 master_priv = dev->primary->master->driver_priv;
3772 if (!master_priv->sarea_priv)
3773 return;
3774
79e53945
JB		 3775 switch (pipe) {
3776 case 0:
3777 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3778 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3779 break;
3780 case 1:
3781 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3782 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3783 break;
3784 default:
9db4a9c7 3785 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3786 break;
3787 }
79e53945
JB		 3788}
3789
976f8a20
DV		 3790/**
3791 * Sets the power management mode of the pipe and plane.
3792 */
3793void intel_crtc_update_dpms(struct drm_crtc *crtc)
3794{
3795 struct drm_device *dev = crtc->dev;
3796 struct drm_i915_private *dev_priv = dev->dev_private;
3797 struct intel_encoder *intel_encoder;
3798 bool enable = false;
3799
3800 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3801 enable |= intel_encoder->connectors_active;
3802
3803 if (enable)
3804 dev_priv->display.crtc_enable(crtc);
3805 else
3806 dev_priv->display.crtc_disable(crtc);
3807
3808 intel_crtc_update_sarea(crtc, enable);
3809}
3810
3811static void intel_crtc_noop(struct drm_crtc *crtc)
3812{
3813}
3814
cdd59983
CW		 3815static void intel_crtc_disable(struct drm_crtc *crtc)
3816{
cdd59983 3817 struct drm_device *dev = crtc->dev;
976f8a20 3818 struct drm_connector *connector;
ee7b9f93 3819 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 3820
976f8a20
DV		 3821 /* crtc should still be enabled when we disable it. */
3822 WARN_ON(!crtc->enabled);
3823
3824 dev_priv->display.crtc_disable(crtc);
3825 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3826 dev_priv->display.off(crtc);
3827
931872fc
CW		 3828 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3829 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3830
3831 if (crtc->fb) {
3832 mutex_lock(&dev->struct_mutex);
1690e1eb 3833 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3834 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3835 crtc->fb = NULL;
3836 }
3837
3838 /* Update computed state. */
3839 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3840 if (!connector->encoder || !connector->encoder->crtc)
3841 continue;
3842
3843 if (connector->encoder->crtc != crtc)
3844 continue;
3845
3846 connector->dpms = DRM_MODE_DPMS_OFF;
3847 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3848 }
3849}
3850
a261b246 3851void intel_modeset_disable(struct drm_device *dev)
79e53945 3852{
a261b246
DV		 3853 struct drm_crtc *crtc;
3854
3855 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3856 if (crtc->enabled)
3857 intel_crtc_disable(crtc);
3858 }
79e53945
JB		 3859}
3860
1f703855 3861void intel_encoder_noop(struct drm_encoder *encoder)
79e53945 3862{
7e7d76c3
JB		 3863}
3864
ea5b213a 3865void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3866{
4ef69c7a 3867 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3868
ea5b213a
CW		 3869 drm_encoder_cleanup(encoder);
3870 kfree(intel_encoder);
7e7d76c3
JB		 3871}
3872
5ab432ef
DV		 3873/* Simple dpms helper for encodres with just one connector, no cloning and only
3874 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3875 * state of the entire output pipe. */
3876void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3877{
5ab432ef
DV		 3878 if (mode == DRM_MODE_DPMS_ON) {
3879 encoder->connectors_active = true;
3880
b2cabb0e 3881 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3882 } else {
3883 encoder->connectors_active = false;
3884
b2cabb0e 3885 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3886 }
79e53945
JB		 3887}
3888
0a91ca29
DV		 3889/* Cross check the actual hw state with our own modeset state tracking (and it's
3890 * internal consistency). */
b980514c 3891static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3892{
0a91ca29
DV		 3893 if (connector->get_hw_state(connector)) {
3894 struct intel_encoder *encoder = connector->encoder;
3895 struct drm_crtc *crtc;
3896 bool encoder_enabled;
3897 enum pipe pipe;
3898
3899 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3900 connector->base.base.id,
3901 drm_get_connector_name(&connector->base));
3902
3903 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3904 "wrong connector dpms state\n");
3905 WARN(connector->base.encoder != &encoder->base,
3906 "active connector not linked to encoder\n");
3907 WARN(!encoder->connectors_active,
3908 "encoder->connectors_active not set\n");
3909
3910 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3911 WARN(!encoder_enabled, "encoder not enabled\n");
3912 if (WARN_ON(!encoder->base.crtc))
3913 return;
3914
3915 crtc = encoder->base.crtc;
3916
3917 WARN(!crtc->enabled, "crtc not enabled\n");
3918 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3919 WARN(pipe != to_intel_crtc(crtc)->pipe,
3920 "encoder active on the wrong pipe\n");
3921 }
79e53945
JB		 3922}
3923
5ab432ef
DV		 3924/* Even simpler default implementation, if there's really no special case to
3925 * consider. */
3926void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3927{
5ab432ef 3928 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3929
5ab432ef
DV		 3930 /* All the simple cases only support two dpms states. */
3931 if (mode != DRM_MODE_DPMS_ON)
3932 mode = DRM_MODE_DPMS_OFF;
d4270e57 3933
5ab432ef
DV		 3934 if (mode == connector->dpms)
3935 return;
3936
3937 connector->dpms = mode;
3938
3939 /* Only need to change hw state when actually enabled */
3940 if (encoder->base.crtc)
3941 intel_encoder_dpms(encoder, mode);
3942 else
8af6cf88 3943 WARN_ON(encoder->connectors_active != false);
0a91ca29 3944
b980514c 3945 intel_modeset_check_state(connector->dev);
79e53945
JB		 3946}
3947
f0947c37
DV		 3948/* Simple connector->get_hw_state implementation for encoders that support only
3949 * one connector and no cloning and hence the encoder state determines the state
3950 * of the connector. */
3951bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3952{
24929352 3953 enum pipe pipe = 0;
f0947c37 3954 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3955
f0947c37 3956 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3957}
3958
79e53945 3959static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
35313cde 3960 const struct drm_display_mode *mode,
79e53945
JB		 3961 struct drm_display_mode *adjusted_mode)
3962{
2c07245f 3963 struct drm_device *dev = crtc->dev;
89749350 3964
bad720ff 3965 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3966 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3967 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3968 return false;
2c07245f 3969 }
89749350 3970
f9bef081
DV		 3971 /* All interlaced capable intel hw wants timings in frames. Note though
3972 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3973 * timings, so we need to be careful not to clobber these.*/
3974 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3975 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3976
44f46b42
CW		 3977 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3978 * with a hsync front porch of 0.
3979 */
3980 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3981 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3982 return false;
3983
79e53945
JB		 3984 return true;
3985}
3986
25eb05fc
JB		 3987static int valleyview_get_display_clock_speed(struct drm_device *dev)
3988{
3989 return 400000; /* FIXME */
3990}
3991
e70236a8
JB		 3992static int i945_get_display_clock_speed(struct drm_device *dev)
3993{
3994 return 400000;
3995}
79e53945 3996
e70236a8 3997static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3998{
e70236a8
JB		 3999 return 333000;
4000}
79e53945 4001
e70236a8
JB		 4002static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4003{
4004 return 200000;
4005}
79e53945 4006
e70236a8
JB		 4007static int i915gm_get_display_clock_speed(struct drm_device *dev)
4008{
4009 u16 gcfgc = 0;
79e53945 4010
e70236a8
JB		 4011 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4012
4013 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4014 return 133000;
4015 else {
4016 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4017 case GC_DISPLAY_CLOCK_333_MHZ:
4018 return 333000;
4019 default:
4020 case GC_DISPLAY_CLOCK_190_200_MHZ:
4021 return 190000;
79e53945 4022 }
e70236a8
JB		 4023 }
4024}
4025
4026static int i865_get_display_clock_speed(struct drm_device *dev)
4027{
4028 return 266000;
4029}
4030
4031static int i855_get_display_clock_speed(struct drm_device *dev)
4032{
4033 u16 hpllcc = 0;
4034 /* Assume that the hardware is in the high speed state. This
4035 * should be the default.
4036 */
4037 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4038 case GC_CLOCK_133_200:
4039 case GC_CLOCK_100_200:
4040 return 200000;
4041 case GC_CLOCK_166_250:
4042 return 250000;
4043 case GC_CLOCK_100_133:
79e53945 4044 return 133000;
e70236a8 4045 }
79e53945 4046
e70236a8
JB		 4047 /* Shouldn't happen */
4048 return 0;
4049}
79e53945 4050
e70236a8
JB		 4051static int i830_get_display_clock_speed(struct drm_device *dev)
4052{
4053 return 133000;
79e53945
JB		 4054}
4055
2c07245f
ZW		 4056struct fdi_m_n {
4057 u32 tu;
4058 u32 gmch_m;
4059 u32 gmch_n;
4060 u32 link_m;
4061 u32 link_n;
4062};
4063
4064static void
4065fdi_reduce_ratio(u32 *num, u32 *den)
4066{
4067 while (*num > 0xffffff || *den > 0xffffff) {
4068 *num >>= 1;
4069 *den >>= 1;
4070 }
4071}
4072
2c07245f 4073static void
f2b115e6
AJ		 4074ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
4075 int link_clock, struct fdi_m_n *m_n)
2c07245f 4076{
2c07245f
ZW		 4077 m_n->tu = 64; /* default size */
4078
22ed1113
CW		 4079 /* BUG_ON(pixel_clock > INT_MAX / 36); */
4080 m_n->gmch_m = bits_per_pixel * pixel_clock;
4081 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 4082 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4083
22ed1113
CW		 4084 m_n->link_m = pixel_clock;
4085 m_n->link_n = link_clock;
2c07245f
ZW		 4086 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
4087}
4088
a7615030
CW		 4089static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4090{
72bbe58c
KP		 4091 if (i915_panel_use_ssc >= 0)
4092 return i915_panel_use_ssc != 0;
4093 return dev_priv->lvds_use_ssc
435793df 4094 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4095}
4096
5a354204
JB		 4097/**
4098 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4099 * @crtc: CRTC structure
3b5c78a3 4100 * @mode: requested mode
5a354204
JB		 4101 *
4102 * A pipe may be connected to one or more outputs. Based on the depth of the
4103 * attached framebuffer, choose a good color depth to use on the pipe.
4104 *
4105 * If possible, match the pipe depth to the fb depth. In some cases, this
4106 * isn't ideal, because the connected output supports a lesser or restricted
4107 * set of depths. Resolve that here:
4108 * LVDS typically supports only 6bpc, so clamp down in that case
4109 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4110 * Displays may support a restricted set as well, check EDID and clamp as
4111 * appropriate.
3b5c78a3 4112 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 4113 *
4114 * RETURNS:
4115 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4116 * true if they don't match).
4117 */
4118static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
94352cf9 4119 struct drm_framebuffer *fb,
3b5c78a3
AJ		 4120 unsigned int *pipe_bpp,
4121 struct drm_display_mode *mode)
5a354204
JB		 4122{
4123 struct drm_device *dev = crtc->dev;
4124 struct drm_i915_private *dev_priv = dev->dev_private;
5a354204 4125 struct drm_connector *connector;
6c2b7c12 4126 struct intel_encoder *intel_encoder;
5a354204
JB		 4127 unsigned int display_bpc = UINT_MAX, bpc;
4128
4129 /* Walk the encoders & connectors on this crtc, get min bpc */
6c2b7c12 4130 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5a354204
JB		 4131
4132 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4133 unsigned int lvds_bpc;
4134
4135 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4136 LVDS_A3_POWER_UP)
4137 lvds_bpc = 8;
4138 else
4139 lvds_bpc = 6;
4140
4141 if (lvds_bpc < display_bpc) {
82820490 4142 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 4143 display_bpc = lvds_bpc;
4144 }
4145 continue;
4146 }
4147
5a354204
JB		 4148 /* Not one of the known troublemakers, check the EDID */
4149 list_for_each_entry(connector, &dev->mode_config.connector_list,
4150 head) {
6c2b7c12 4151 if (connector->encoder != &intel_encoder->base)
5a354204
JB		 4152 continue;
4153
62ac41a6
JB		 4154 /* Don't use an invalid EDID bpc value */
4155 if (connector->display_info.bpc &&
4156 connector->display_info.bpc < display_bpc) {
82820490 4157 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 4158 display_bpc = connector->display_info.bpc;
4159 }
4160 }
4161
4162 /*
4163 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4164 * through, clamp it down. (Note: >12bpc will be caught below.)
4165 */
4166 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4167 if (display_bpc > 8 && display_bpc < 12) {
82820490 4168 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 4169 display_bpc = 12;
4170 } else {
82820490 4171 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 4172 display_bpc = 8;
4173 }
4174 }
4175 }
4176
3b5c78a3
AJ		 4177 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4178 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4179 display_bpc = 6;
4180 }
4181
5a354204
JB		 4182 /*
4183 * We could just drive the pipe at the highest bpc all the time and
4184 * enable dithering as needed, but that costs bandwidth. So choose
4185 * the minimum value that expresses the full color range of the fb but
4186 * also stays within the max display bpc discovered above.
4187 */
4188
94352cf9 4189 switch (fb->depth) {
5a354204
JB		 4190 case 8:
4191 bpc = 8; /* since we go through a colormap */
4192 break;
4193 case 15:
4194 case 16:
4195 bpc = 6; /* min is 18bpp */
4196 break;
4197 case 24:
578393cd 4198 bpc = 8;
5a354204
JB		 4199 break;
4200 case 30:
578393cd 4201 bpc = 10;
5a354204
JB		 4202 break;
4203 case 48:
578393cd 4204 bpc = 12;
5a354204
JB		 4205 break;
4206 default:
4207 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4208 bpc = min((unsigned int)8, display_bpc);
4209 break;
4210 }
4211
578393cd
KP		 4212 display_bpc = min(display_bpc, bpc);
4213
82820490
AJ		 4214 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4215 bpc, display_bpc);
5a354204 4216
578393cd 4217 *pipe_bpp = display_bpc * 3;
5a354204
JB		 4218
4219 return display_bpc != bpc;
4220}
4221
a0c4da24
JB		 4222static int vlv_get_refclk(struct drm_crtc *crtc)
4223{
4224 struct drm_device *dev = crtc->dev;
4225 struct drm_i915_private *dev_priv = dev->dev_private;
4226 int refclk = 27000; /* for DP & HDMI */
4227
4228 return 100000; /* only one validated so far */
4229
4230 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4231 refclk = 96000;
4232 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4233 if (intel_panel_use_ssc(dev_priv))
4234 refclk = 100000;
4235 else
4236 refclk = 96000;
4237 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4238 refclk = 100000;
4239 }
4240
4241 return refclk;
4242}
4243
c65d77d8
JB		 4244static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4245{
4246 struct drm_device *dev = crtc->dev;
4247 struct drm_i915_private *dev_priv = dev->dev_private;
4248 int refclk;
4249
a0c4da24
JB		 4250 if (IS_VALLEYVIEW(dev)) {
4251 refclk = vlv_get_refclk(crtc);
4252 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4253 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4254 refclk = dev_priv->lvds_ssc_freq * 1000;
4255 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4256 refclk / 1000);
4257 } else if (!IS_GEN2(dev)) {
4258 refclk = 96000;
4259 } else {
4260 refclk = 48000;
4261 }
4262
4263 return refclk;
4264}
4265
4266static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4267 intel_clock_t *clock)
4268{
4269 /* SDVO TV has fixed PLL values depend on its clock range,
4270 this mirrors vbios setting. */
4271 if (adjusted_mode->clock >= 100000
4272 && adjusted_mode->clock < 140500) {
4273 clock->p1 = 2;
4274 clock->p2 = 10;
4275 clock->n = 3;
4276 clock->m1 = 16;
4277 clock->m2 = 8;
4278 } else if (adjusted_mode->clock >= 140500
4279 && adjusted_mode->clock <= 200000) {
4280 clock->p1 = 1;
4281 clock->p2 = 10;
4282 clock->n = 6;
4283 clock->m1 = 12;
4284 clock->m2 = 8;
4285 }
4286}
4287
a7516a05
JB		 4288static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4289 intel_clock_t *clock,
4290 intel_clock_t *reduced_clock)
4291{
4292 struct drm_device *dev = crtc->dev;
4293 struct drm_i915_private *dev_priv = dev->dev_private;
4294 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4295 int pipe = intel_crtc->pipe;
4296 u32 fp, fp2 = 0;
4297
4298 if (IS_PINEVIEW(dev)) {
4299 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4300 if (reduced_clock)
4301 fp2 = (1 << reduced_clock->n) << 16 |
4302 reduced_clock->m1 << 8 | reduced_clock->m2;
4303 } else {
4304 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4305 if (reduced_clock)
4306 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4307 reduced_clock->m2;
4308 }
4309
4310 I915_WRITE(FP0(pipe), fp);
4311
4312 intel_crtc->lowfreq_avail = false;
4313 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4314 reduced_clock && i915_powersave) {
4315 I915_WRITE(FP1(pipe), fp2);
4316 intel_crtc->lowfreq_avail = true;
4317 } else {
4318 I915_WRITE(FP1(pipe), fp);
4319 }
4320}
4321
93e537a1
DV		 4322static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4323 struct drm_display_mode *adjusted_mode)
4324{
4325 struct drm_device *dev = crtc->dev;
4326 struct drm_i915_private *dev_priv = dev->dev_private;
4327 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4328 int pipe = intel_crtc->pipe;
284d5df5 4329 u32 temp;
93e537a1
DV		 4330
4331 temp = I915_READ(LVDS);
4332 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4333 if (pipe == 1) {
4334 temp |= LVDS_PIPEB_SELECT;
4335 } else {
4336 temp &= ~LVDS_PIPEB_SELECT;
4337 }
4338 /* set the corresponsding LVDS_BORDER bit */
4339 temp |= dev_priv->lvds_border_bits;
4340 /* Set the B0-B3 data pairs corresponding to whether we're going to
4341 * set the DPLLs for dual-channel mode or not.
4342 */
4343 if (clock->p2 == 7)
4344 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4345 else
4346 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4347
4348 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4349 * appropriately here, but we need to look more thoroughly into how
4350 * panels behave in the two modes.
4351 */
4352 /* set the dithering flag on LVDS as needed */
4353 if (INTEL_INFO(dev)->gen >= 4) {
4354 if (dev_priv->lvds_dither)
4355 temp |= LVDS_ENABLE_DITHER;
4356 else
4357 temp &= ~LVDS_ENABLE_DITHER;
4358 }
284d5df5 4359 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
93e537a1 4360 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 4361 temp |= LVDS_HSYNC_POLARITY;
93e537a1 4362 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 4363 temp |= LVDS_VSYNC_POLARITY;
93e537a1
DV		 4364 I915_WRITE(LVDS, temp);
4365}
4366
a0c4da24
JB		 4367static void vlv_update_pll(struct drm_crtc *crtc,
4368 struct drm_display_mode *mode,
4369 struct drm_display_mode *adjusted_mode,
4370 intel_clock_t *clock, intel_clock_t *reduced_clock,
2a8f64ca 4371 int num_connectors)
a0c4da24
JB		 4372{
4373 struct drm_device *dev = crtc->dev;
4374 struct drm_i915_private *dev_priv = dev->dev_private;
4375 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4376 int pipe = intel_crtc->pipe;
4377 u32 dpll, mdiv, pdiv;
4378 u32 bestn, bestm1, bestm2, bestp1, bestp2;
2a8f64ca
VP		 4379 bool is_sdvo;
4380 u32 temp;
4381
4382 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4383 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
a0c4da24 4384
2a8f64ca
VP		 4385 dpll = DPLL_VGA_MODE_DIS;
4386 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4387 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4388 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4389
4390 I915_WRITE(DPLL(pipe), dpll);
4391 POSTING_READ(DPLL(pipe));
a0c4da24
JB		 4392
4393 bestn = clock->n;
4394 bestm1 = clock->m1;
4395 bestm2 = clock->m2;
4396 bestp1 = clock->p1;
4397 bestp2 = clock->p2;
4398
2a8f64ca
VP		 4399 /*
4400 * In Valleyview PLL and program lane counter registers are exposed
4401 * through DPIO interface
4402 */
a0c4da24
JB		 4403 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4404 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4405 mdiv |= ((bestn << DPIO_N_SHIFT));
4406 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4407 mdiv |= (1 << DPIO_K_SHIFT);
4408 mdiv |= DPIO_ENABLE_CALIBRATION;
4409 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4410
4411 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4412
2a8f64ca 4413 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
a0c4da24 4414 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
2a8f64ca
VP		 4415 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4416 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
a0c4da24
JB		 4417 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4418
2a8f64ca 4419 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
a0c4da24
JB		 4420
4421 dpll |= DPLL_VCO_ENABLE;
4422 I915_WRITE(DPLL(pipe), dpll);
4423 POSTING_READ(DPLL(pipe));
4424 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4425 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4426
2a8f64ca
VP		 4427 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4428
4429 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4430 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4431
4432 I915_WRITE(DPLL(pipe), dpll);
4433
4434 /* Wait for the clocks to stabilize. */
4435 POSTING_READ(DPLL(pipe));
4436 udelay(150);
a0c4da24 4437
2a8f64ca
VP		 4438 temp = 0;
4439 if (is_sdvo) {
4440 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
a0c4da24
JB		 4441 if (temp > 1)
4442 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4443 else
4444 temp = 0;
a0c4da24 4445 }
2a8f64ca
VP		 4446 I915_WRITE(DPLL_MD(pipe), temp);
4447 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4448
2a8f64ca
VP		 4449 /* Now program lane control registers */
4450 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4451 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4452 {
4453 temp = 0x1000C4;
4454 if(pipe == 1)
4455 temp |= (1 << 21);
4456 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4457 }
4458 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4459 {
4460 temp = 0x1000C4;
4461 if(pipe == 1)
4462 temp |= (1 << 21);
4463 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4464 }
a0c4da24
JB		 4465}
4466
eb1cbe48
DV		 4467static void i9xx_update_pll(struct drm_crtc *crtc,
4468 struct drm_display_mode *mode,
4469 struct drm_display_mode *adjusted_mode,
4470 intel_clock_t *clock, intel_clock_t *reduced_clock,
4471 int num_connectors)
4472{
4473 struct drm_device *dev = crtc->dev;
4474 struct drm_i915_private *dev_priv = dev->dev_private;
4475 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4476 int pipe = intel_crtc->pipe;
4477 u32 dpll;
4478 bool is_sdvo;
4479
2a8f64ca
VP		 4480 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4481
eb1cbe48
DV		 4482 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4483 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4484
4485 dpll = DPLL_VGA_MODE_DIS;
4486
4487 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4488 dpll |= DPLLB_MODE_LVDS;
4489 else
4490 dpll |= DPLLB_MODE_DAC_SERIAL;
4491 if (is_sdvo) {
4492 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4493 if (pixel_multiplier > 1) {
4494 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4495 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4496 }
4497 dpll |= DPLL_DVO_HIGH_SPEED;
4498 }
4499 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4500 dpll |= DPLL_DVO_HIGH_SPEED;
4501
4502 /* compute bitmask from p1 value */
4503 if (IS_PINEVIEW(dev))
4504 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4505 else {
4506 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4507 if (IS_G4X(dev) && reduced_clock)
4508 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4509 }
4510 switch (clock->p2) {
4511 case 5:
4512 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4513 break;
4514 case 7:
4515 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4516 break;
4517 case 10:
4518 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4519 break;
4520 case 14:
4521 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4522 break;
4523 }
4524 if (INTEL_INFO(dev)->gen >= 4)
4525 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4526
4527 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4528 dpll |= PLL_REF_INPUT_TVCLKINBC;
4529 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4530 /* XXX: just matching BIOS for now */
4531 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4532 dpll |= 3;
4533 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4534 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4535 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4536 else
4537 dpll |= PLL_REF_INPUT_DREFCLK;
4538
4539 dpll |= DPLL_VCO_ENABLE;
4540 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4541 POSTING_READ(DPLL(pipe));
4542 udelay(150);
4543
4544 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4545 * This is an exception to the general rule that mode_set doesn't turn
4546 * things on.
4547 */
4548 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4549 intel_update_lvds(crtc, clock, adjusted_mode);
4550
4551 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4552 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4553
4554 I915_WRITE(DPLL(pipe), dpll);
4555
4556 /* Wait for the clocks to stabilize. */
4557 POSTING_READ(DPLL(pipe));
4558 udelay(150);
4559
4560 if (INTEL_INFO(dev)->gen >= 4) {
4561 u32 temp = 0;
4562 if (is_sdvo) {
4563 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4564 if (temp > 1)
4565 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4566 else
4567 temp = 0;
4568 }
4569 I915_WRITE(DPLL_MD(pipe), temp);
4570 } else {
4571 /* The pixel multiplier can only be updated once the
4572 * DPLL is enabled and the clocks are stable.
4573 *
4574 * So write it again.
4575 */
4576 I915_WRITE(DPLL(pipe), dpll);
4577 }
4578}
4579
4580static void i8xx_update_pll(struct drm_crtc *crtc,
4581 struct drm_display_mode *adjusted_mode,
2a8f64ca 4582 intel_clock_t *clock, intel_clock_t *reduced_clock,
eb1cbe48
DV		 4583 int num_connectors)
4584{
4585 struct drm_device *dev = crtc->dev;
4586 struct drm_i915_private *dev_priv = dev->dev_private;
4587 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4588 int pipe = intel_crtc->pipe;
4589 u32 dpll;
4590
2a8f64ca
VP		 4591 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4592
eb1cbe48
DV		 4593 dpll = DPLL_VGA_MODE_DIS;
4594
4595 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4596 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4597 } else {
4598 if (clock->p1 == 2)
4599 dpll |= PLL_P1_DIVIDE_BY_TWO;
4600 else
4601 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4602 if (clock->p2 == 4)
4603 dpll |= PLL_P2_DIVIDE_BY_4;
4604 }
4605
4606 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4607 /* XXX: just matching BIOS for now */
4608 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4609 dpll |= 3;
4610 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4611 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4612 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4613 else
4614 dpll |= PLL_REF_INPUT_DREFCLK;
4615
4616 dpll |= DPLL_VCO_ENABLE;
4617 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4618 POSTING_READ(DPLL(pipe));
4619 udelay(150);
4620
eb1cbe48
DV		 4621 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4622 * This is an exception to the general rule that mode_set doesn't turn
4623 * things on.
4624 */
4625 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4626 intel_update_lvds(crtc, clock, adjusted_mode);
4627
5b5896e4
DV		 4628 I915_WRITE(DPLL(pipe), dpll);
4629
4630 /* Wait for the clocks to stabilize. */
4631 POSTING_READ(DPLL(pipe));
4632 udelay(150);
4633
eb1cbe48
DV		 4634 /* The pixel multiplier can only be updated once the
4635 * DPLL is enabled and the clocks are stable.
4636 *
4637 * So write it again.
4638 */
4639 I915_WRITE(DPLL(pipe), dpll);
4640}
4641
b0e77b9c
PZ		 4642static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4643 struct drm_display_mode *mode,
4644 struct drm_display_mode *adjusted_mode)
4645{
4646 struct drm_device *dev = intel_crtc->base.dev;
4647 struct drm_i915_private *dev_priv = dev->dev_private;
4648 enum pipe pipe = intel_crtc->pipe;
fe2b8f9d 4649 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
b0e77b9c
PZ		 4650 uint32_t vsyncshift;
4651
4652 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4653 /* the chip adds 2 halflines automatically */
4654 adjusted_mode->crtc_vtotal -= 1;
4655 adjusted_mode->crtc_vblank_end -= 1;
4656 vsyncshift = adjusted_mode->crtc_hsync_start
4657 - adjusted_mode->crtc_htotal / 2;
4658 } else {
4659 vsyncshift = 0;
4660 }
4661
4662 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4663 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4664
fe2b8f9d 4665 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4666 (adjusted_mode->crtc_hdisplay - 1) |
4667 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4668 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4669 (adjusted_mode->crtc_hblank_start - 1) |
4670 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4671 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4672 (adjusted_mode->crtc_hsync_start - 1) |
4673 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4674
fe2b8f9d 4675 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4676 (adjusted_mode->crtc_vdisplay - 1) |
4677 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4678 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4679 (adjusted_mode->crtc_vblank_start - 1) |
4680 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4681 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4682 (adjusted_mode->crtc_vsync_start - 1) |
4683 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4684
b5e508d4
PZ		 4685 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4686 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4687 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4688 * bits. */
4689 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4690 (pipe == PIPE_B || pipe == PIPE_C))
4691 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4692
b0e77b9c
PZ		 4693 /* pipesrc controls the size that is scaled from, which should
4694 * always be the user's requested size.
4695 */
4696 I915_WRITE(PIPESRC(pipe),
4697 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4698}
4699
f564048e
EA		 4700static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4701 struct drm_display_mode *mode,
4702 struct drm_display_mode *adjusted_mode,
4703 int x, int y,
94352cf9 4704 struct drm_framebuffer *fb)
79e53945
JB		 4705{
4706 struct drm_device *dev = crtc->dev;
4707 struct drm_i915_private *dev_priv = dev->dev_private;
4708 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4709 int pipe = intel_crtc->pipe;
80824003 4710 int plane = intel_crtc->plane;
c751ce4f 4711 int refclk, num_connectors = 0;
652c393a 4712 intel_clock_t clock, reduced_clock;
b0e77b9c 4713 u32 dspcntr, pipeconf;
eb1cbe48
DV		 4714 bool ok, has_reduced_clock = false, is_sdvo = false;
4715 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4716 struct intel_encoder *encoder;
d4906093 4717 const intel_limit_t *limit;
5c3b82e2 4718 int ret;
79e53945 4719
6c2b7c12 4720 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4721 switch (encoder->type) {
79e53945
JB		 4722 case INTEL_OUTPUT_LVDS:
4723 is_lvds = true;
4724 break;
4725 case INTEL_OUTPUT_SDVO:
7d57382e 4726 case INTEL_OUTPUT_HDMI:
79e53945 4727 is_sdvo = true;
5eddb70b 4728 if (encoder->needs_tv_clock)
e2f0ba97 4729 is_tv = true;
79e53945 4730 break;
79e53945
JB		 4731 case INTEL_OUTPUT_TVOUT:
4732 is_tv = true;
4733 break;
a4fc5ed6
KP		 4734 case INTEL_OUTPUT_DISPLAYPORT:
4735 is_dp = true;
4736 break;
79e53945 4737 }
43565a06 4738
c751ce4f 4739 num_connectors++;
79e53945
JB		 4740 }
4741
c65d77d8 4742 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4743
d4906093
ML		 4744 /*
4745 * Returns a set of divisors for the desired target clock with the given
4746 * refclk, or FALSE. The returned values represent the clock equation:
4747 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4748 */
1b894b59 4749 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4750 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4751 &clock);
79e53945
JB		 4752 if (!ok) {
4753 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4754 return -EINVAL;
79e53945
JB		 4755 }
4756
cda4b7d3 4757 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4758 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4759
ddc9003c 4760 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4761 /*
4762 * Ensure we match the reduced clock's P to the target clock.
4763 * If the clocks don't match, we can't switch the display clock
4764 * by using the FP0/FP1. In such case we will disable the LVDS
4765 * downclock feature.
4766 */
ddc9003c 4767 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4768 dev_priv->lvds_downclock,
4769 refclk,
cec2f356 4770 &clock,
5eddb70b 4771 &reduced_clock);
7026d4ac
ZW		 4772 }
4773
c65d77d8
JB		 4774 if (is_sdvo && is_tv)
4775 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4776
eb1cbe48 4777 if (IS_GEN2(dev))
2a8f64ca
VP		 4778 i8xx_update_pll(crtc, adjusted_mode, &clock,
4779 has_reduced_clock ? &reduced_clock : NULL,
4780 num_connectors);
a0c4da24 4781 else if (IS_VALLEYVIEW(dev))
2a8f64ca
VP		 4782 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4783 has_reduced_clock ? &reduced_clock : NULL,
4784 num_connectors);
79e53945 4785 else
eb1cbe48
DV		 4786 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4787 has_reduced_clock ? &reduced_clock : NULL,
4788 num_connectors);
79e53945
JB		 4789
4790 /* setup pipeconf */
5eddb70b 4791 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4792
4793 /* Set up the display plane register */
4794 dspcntr = DISPPLANE_GAMMA_ENABLE;
4795
929c77fb
EA		 4796 if (pipe == 0)
4797 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4798 else
4799 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4800
a6c45cf0 4801 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4802 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4803 * core speed.
4804 *
4805 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4806 * pipe == 0 check?
4807 */
e70236a8
JB		 4808 if (mode->clock >
4809 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4810 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4811 else
5eddb70b 4812 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4813 }
4814
3b5c78a3
AJ		 4815 /* default to 8bpc */
4816 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4817 if (is_dp) {
0c96c65b 4818 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3b5c78a3
AJ		 4819 pipeconf |= PIPECONF_BPP_6 |
4820 PIPECONF_DITHER_EN |
4821 PIPECONF_DITHER_TYPE_SP;
4822 }
4823 }
4824
19c03924
GB		 4825 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4826 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4827 pipeconf |= PIPECONF_BPP_6 |
4828 PIPECONF_ENABLE |
4829 I965_PIPECONF_ACTIVE;
4830 }
4831 }
4832
28c97730 4833 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4834 drm_mode_debug_printmodeline(mode);
4835
a7516a05
JB		 4836 if (HAS_PIPE_CXSR(dev)) {
4837 if (intel_crtc->lowfreq_avail) {
28c97730 4838 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4839 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4840 } else {
28c97730 4841 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4842 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4843 }
4844 }
4845
617cf884 4846 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575 4847 if (!IS_GEN2(dev) &&
b0e77b9c 4848 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
734b4157 4849 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
b0e77b9c 4850 else
617cf884 4851 pipeconf |= PIPECONF_PROGRESSIVE;
734b4157 4852
b0e77b9c 4853 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4854
4855 /* pipesrc and dspsize control the size that is scaled from,
4856 * which should always be the user's requested size.
79e53945 4857 */
929c77fb
EA		 4858 I915_WRITE(DSPSIZE(plane),
4859 ((mode->vdisplay - 1) << 16) |
4860 (mode->hdisplay - 1));
4861 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4862
f564048e
EA		 4863 I915_WRITE(PIPECONF(pipe), pipeconf);
4864 POSTING_READ(PIPECONF(pipe));
929c77fb 4865 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4866
4867 intel_wait_for_vblank(dev, pipe);
4868
f564048e
EA		 4869 I915_WRITE(DSPCNTR(plane), dspcntr);
4870 POSTING_READ(DSPCNTR(plane));
4871
94352cf9 4872 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4873
4874 intel_update_watermarks(dev);
4875
f564048e
EA		 4876 return ret;
4877}
4878
9fb526db
KP		 4879/*
4880 * Initialize reference clocks when the driver loads
4881 */
4882void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4883{
4884 struct drm_i915_private *dev_priv = dev->dev_private;
4885 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4886 struct intel_encoder *encoder;
13d83a67
JB		 4887 u32 temp;
4888 bool has_lvds = false;
199e5d79
KP		 4889 bool has_cpu_edp = false;
4890 bool has_pch_edp = false;
4891 bool has_panel = false;
99eb6a01
KP		 4892 bool has_ck505 = false;
4893 bool can_ssc = false;
13d83a67
JB		 4894
4895 /* We need to take the global config into account */
199e5d79
KP		 4896 list_for_each_entry(encoder, &mode_config->encoder_list,
4897 base.head) {
4898 switch (encoder->type) {
4899 case INTEL_OUTPUT_LVDS:
4900 has_panel = true;
4901 has_lvds = true;
4902 break;
4903 case INTEL_OUTPUT_EDP:
4904 has_panel = true;
4905 if (intel_encoder_is_pch_edp(&encoder->base))
4906 has_pch_edp = true;
4907 else
4908 has_cpu_edp = true;
4909 break;
13d83a67
JB		 4910 }
4911 }
4912
99eb6a01
KP		 4913 if (HAS_PCH_IBX(dev)) {
4914 has_ck505 = dev_priv->display_clock_mode;
4915 can_ssc = has_ck505;
4916 } else {
4917 has_ck505 = false;
4918 can_ssc = true;
4919 }
4920
4921 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4922 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4923 has_ck505);
13d83a67
JB		 4924
4925 /* Ironlake: try to setup display ref clock before DPLL
4926 * enabling. This is only under driver's control after
4927 * PCH B stepping, previous chipset stepping should be
4928 * ignoring this setting.
4929 */
4930 temp = I915_READ(PCH_DREF_CONTROL);
4931 /* Always enable nonspread source */
4932 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4933
99eb6a01
KP		 4934 if (has_ck505)
4935 temp |= DREF_NONSPREAD_CK505_ENABLE;
4936 else
4937 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4938
199e5d79
KP		 4939 if (has_panel) {
4940 temp &= ~DREF_SSC_SOURCE_MASK;
4941 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4942
199e5d79 4943 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4944 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4945 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4946 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4947 } else
4948 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4949
4950 /* Get SSC going before enabling the outputs */
4951 I915_WRITE(PCH_DREF_CONTROL, temp);
4952 POSTING_READ(PCH_DREF_CONTROL);
4953 udelay(200);
4954
13d83a67
JB		 4955 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4956
4957 /* Enable CPU source on CPU attached eDP */
199e5d79 4958 if (has_cpu_edp) {
99eb6a01 4959 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4960 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4961 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4962 }
13d83a67
JB		 4963 else
4964 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4965 } else
4966 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4967
4968 I915_WRITE(PCH_DREF_CONTROL, temp);
4969 POSTING_READ(PCH_DREF_CONTROL);
4970 udelay(200);
4971 } else {
4972 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4973
4974 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4975
4976 /* Turn off CPU output */
4977 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4978
4979 I915_WRITE(PCH_DREF_CONTROL, temp);
4980 POSTING_READ(PCH_DREF_CONTROL);
4981 udelay(200);
4982
4983 /* Turn off the SSC source */
4984 temp &= ~DREF_SSC_SOURCE_MASK;
4985 temp |= DREF_SSC_SOURCE_DISABLE;
4986
4987 /* Turn off SSC1 */
4988 temp &= ~ DREF_SSC1_ENABLE;
4989
13d83a67
JB		 4990 I915_WRITE(PCH_DREF_CONTROL, temp);
4991 POSTING_READ(PCH_DREF_CONTROL);
4992 udelay(200);
4993 }
4994}
4995
d9d444cb
JB		 4996static int ironlake_get_refclk(struct drm_crtc *crtc)
4997{
4998 struct drm_device *dev = crtc->dev;
4999 struct drm_i915_private *dev_priv = dev->dev_private;
5000 struct intel_encoder *encoder;
d9d444cb
JB		 5001 struct intel_encoder *edp_encoder = NULL;
5002 int num_connectors = 0;
5003 bool is_lvds = false;
5004
6c2b7c12 5005 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5006 switch (encoder->type) {
5007 case INTEL_OUTPUT_LVDS:
5008 is_lvds = true;
5009 break;
5010 case INTEL_OUTPUT_EDP:
5011 edp_encoder = encoder;
5012 break;
5013 }
5014 num_connectors++;
5015 }
5016
5017 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5018 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5019 dev_priv->lvds_ssc_freq);
5020 return dev_priv->lvds_ssc_freq * 1000;
5021 }
5022
5023 return 120000;
5024}
5025
c8203565
PZ		 5026static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5027 struct drm_display_mode *adjusted_mode,
5028 bool dither)
5029{
5030 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5031 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5032 int pipe = intel_crtc->pipe;
5033 uint32_t val;
5034
5035 val = I915_READ(PIPECONF(pipe));
5036
5037 val &= ~PIPE_BPC_MASK;
5038 switch (intel_crtc->bpp) {
5039 case 18:
5040 val |= PIPE_6BPC;
5041 break;
5042 case 24:
5043 val |= PIPE_8BPC;
5044 break;
5045 case 30:
5046 val |= PIPE_10BPC;
5047 break;
5048 case 36:
5049 val |= PIPE_12BPC;
5050 break;
5051 default:
cc769b62
PZ		 5052 /* Case prevented by intel_choose_pipe_bpp_dither. */
5053 BUG();
c8203565
PZ		 5054 }
5055
5056 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5057 if (dither)
5058 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5059
5060 val &= ~PIPECONF_INTERLACE_MASK;
5061 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5062 val |= PIPECONF_INTERLACED_ILK;
5063 else
5064 val |= PIPECONF_PROGRESSIVE;
5065
5066 I915_WRITE(PIPECONF(pipe), val);
5067 POSTING_READ(PIPECONF(pipe));
5068}
5069
ee2b0b38
PZ		 5070static void haswell_set_pipeconf(struct drm_crtc *crtc,
5071 struct drm_display_mode *adjusted_mode,
5072 bool dither)
5073{
5074 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5075 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
702e7a56 5076 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
ee2b0b38
PZ		 5077 uint32_t val;
5078
702e7a56 5079 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5080
5081 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5082 if (dither)
5083 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5084
5085 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5086 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5087 val |= PIPECONF_INTERLACED_ILK;
5088 else
5089 val |= PIPECONF_PROGRESSIVE;
5090
702e7a56
PZ		 5091 I915_WRITE(PIPECONF(cpu_transcoder), val);
5092 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5093}
5094
6591c6e4
PZ		 5095static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5096 struct drm_display_mode *adjusted_mode,
5097 intel_clock_t *clock,
5098 bool *has_reduced_clock,
5099 intel_clock_t *reduced_clock)
5100{
5101 struct drm_device *dev = crtc->dev;
5102 struct drm_i915_private *dev_priv = dev->dev_private;
5103 struct intel_encoder *intel_encoder;
5104 int refclk;
5105 const intel_limit_t *limit;
5106 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5107
5108 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5109 switch (intel_encoder->type) {
5110 case INTEL_OUTPUT_LVDS:
5111 is_lvds = true;
5112 break;
5113 case INTEL_OUTPUT_SDVO:
5114 case INTEL_OUTPUT_HDMI:
5115 is_sdvo = true;
5116 if (intel_encoder->needs_tv_clock)
5117 is_tv = true;
5118 break;
5119 case INTEL_OUTPUT_TVOUT:
5120 is_tv = true;
5121 break;
5122 }
5123 }
5124
5125 refclk = ironlake_get_refclk(crtc);
5126
5127 /*
5128 * Returns a set of divisors for the desired target clock with the given
5129 * refclk, or FALSE. The returned values represent the clock equation:
5130 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5131 */
5132 limit = intel_limit(crtc, refclk);
5133 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5134 clock);
5135 if (!ret)
5136 return false;
5137
5138 if (is_lvds && dev_priv->lvds_downclock_avail) {
5139 /*
5140 * Ensure we match the reduced clock's P to the target clock.
5141 * If the clocks don't match, we can't switch the display clock
5142 * by using the FP0/FP1. In such case we will disable the LVDS
5143 * downclock feature.
5144 */
5145 *has_reduced_clock = limit->find_pll(limit, crtc,
5146 dev_priv->lvds_downclock,
5147 refclk,
5148 clock,
5149 reduced_clock);
5150 }
5151
5152 if (is_sdvo && is_tv)
5153 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5154
5155 return true;
5156}
5157
01a415fd
DV		 5158static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5159{
5160 struct drm_i915_private *dev_priv = dev->dev_private;
5161 uint32_t temp;
5162
5163 temp = I915_READ(SOUTH_CHICKEN1);
5164 if (temp & FDI_BC_BIFURCATION_SELECT)
5165 return;
5166
5167 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5168 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5169
5170 temp |= FDI_BC_BIFURCATION_SELECT;
5171 DRM_DEBUG_KMS("enabling fdi C rx\n");
5172 I915_WRITE(SOUTH_CHICKEN1, temp);
5173 POSTING_READ(SOUTH_CHICKEN1);
5174}
5175
5176static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5177{
5178 struct drm_device *dev = intel_crtc->base.dev;
5179 struct drm_i915_private *dev_priv = dev->dev_private;
5180 struct intel_crtc *pipe_B_crtc =
5181 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5182
5183 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5184 intel_crtc->pipe, intel_crtc->fdi_lanes);
5185 if (intel_crtc->fdi_lanes > 4) {
5186 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5187 intel_crtc->pipe, intel_crtc->fdi_lanes);
5188 /* Clamp lanes to avoid programming the hw with bogus values. */
5189 intel_crtc->fdi_lanes = 4;
5190
5191 return false;
5192 }
5193
5194 if (dev_priv->num_pipe == 2)
5195 return true;
5196
5197 switch (intel_crtc->pipe) {
5198 case PIPE_A:
5199 return true;
5200 case PIPE_B:
5201 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5202 intel_crtc->fdi_lanes > 2) {
5203 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5204 intel_crtc->pipe, intel_crtc->fdi_lanes);
5205 /* Clamp lanes to avoid programming the hw with bogus values. */
5206 intel_crtc->fdi_lanes = 2;
5207
5208 return false;
5209 }
5210
5211 if (intel_crtc->fdi_lanes > 2)
5212 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5213 else
5214 cpt_enable_fdi_bc_bifurcation(dev);
5215
5216 return true;
5217 case PIPE_C:
5218 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5219 if (intel_crtc->fdi_lanes > 2) {
5220 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5221 intel_crtc->pipe, intel_crtc->fdi_lanes);
5222 /* Clamp lanes to avoid programming the hw with bogus values. */
5223 intel_crtc->fdi_lanes = 2;
5224
5225 return false;
5226 }
5227 } else {
5228 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5229 return false;
5230 }
5231
5232 cpt_enable_fdi_bc_bifurcation(dev);
5233
5234 return true;
5235 default:
5236 BUG();
5237 }
5238}
5239
f48d8f23
PZ		 5240static void ironlake_set_m_n(struct drm_crtc *crtc,
5241 struct drm_display_mode *mode,
5242 struct drm_display_mode *adjusted_mode)
5243{
5244 struct drm_device *dev = crtc->dev;
5245 struct drm_i915_private *dev_priv = dev->dev_private;
5246 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
afe2fcf5 5247 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
f48d8f23
PZ		 5248 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5249 struct fdi_m_n m_n = {0};
5250 int target_clock, pixel_multiplier, lane, link_bw;
5251 bool is_dp = false, is_cpu_edp = false;
5252
5253 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5254 switch (intel_encoder->type) {
5255 case INTEL_OUTPUT_DISPLAYPORT:
5256 is_dp = true;
5257 break;
5258 case INTEL_OUTPUT_EDP:
5259 is_dp = true;
5260 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5261 is_cpu_edp = true;
5262 edp_encoder = intel_encoder;
5263 break;
5264 }
5265 }
5266
5267 /* FDI link */
5268 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5269 lane = 0;
5270 /* CPU eDP doesn't require FDI link, so just set DP M/N
5271 according to current link config */
5272 if (is_cpu_edp) {
5273 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5274 } else {
5275 /* FDI is a binary signal running at ~2.7GHz, encoding
5276 * each output octet as 10 bits. The actual frequency
5277 * is stored as a divider into a 100MHz clock, and the
5278 * mode pixel clock is stored in units of 1KHz.
5279 * Hence the bw of each lane in terms of the mode signal
5280 * is:
5281 */
5282 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5283 }
5284
5285 /* [e]DP over FDI requires target mode clock instead of link clock. */
5286 if (edp_encoder)
5287 target_clock = intel_edp_target_clock(edp_encoder, mode);
5288 else if (is_dp)
5289 target_clock = mode->clock;
5290 else
5291 target_clock = adjusted_mode->clock;
5292
5293 if (!lane) {
5294 /*
5295 * Account for spread spectrum to avoid
5296 * oversubscribing the link. Max center spread
5297 * is 2.5%; use 5% for safety's sake.
5298 */
5299 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5300 lane = bps / (link_bw * 8) + 1;
5301 }
5302
5303 intel_crtc->fdi_lanes = lane;
5304
5305 if (pixel_multiplier > 1)
5306 link_bw *= pixel_multiplier;
5307 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5308 &m_n);
5309
afe2fcf5
PZ		 5310 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5311 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5312 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5313 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
f48d8f23
PZ		 5314}
5315
de13a2e3
PZ		 5316static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5317 struct drm_display_mode *adjusted_mode,
5318 intel_clock_t *clock, u32 fp)
79e53945 5319{
de13a2e3 5320 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5321 struct drm_device *dev = crtc->dev;
5322 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5323 struct intel_encoder *intel_encoder;
5324 uint32_t dpll;
5325 int factor, pixel_multiplier, num_connectors = 0;
5326 bool is_lvds = false, is_sdvo = false, is_tv = false;
5327 bool is_dp = false, is_cpu_edp = false;
79e53945 5328
de13a2e3
PZ		 5329 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5330 switch (intel_encoder->type) {
79e53945
JB		 5331 case INTEL_OUTPUT_LVDS:
5332 is_lvds = true;
5333 break;
5334 case INTEL_OUTPUT_SDVO:
7d57382e 5335 case INTEL_OUTPUT_HDMI:
79e53945 5336 is_sdvo = true;
de13a2e3 5337 if (intel_encoder->needs_tv_clock)
e2f0ba97 5338 is_tv = true;
79e53945 5339 break;
79e53945
JB		 5340 case INTEL_OUTPUT_TVOUT:
5341 is_tv = true;
5342 break;
a4fc5ed6
KP		 5343 case INTEL_OUTPUT_DISPLAYPORT:
5344 is_dp = true;
5345 break;
32f9d658 5346 case INTEL_OUTPUT_EDP:
e3aef172 5347 is_dp = true;
de13a2e3 5348 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5349 is_cpu_edp = true;
32f9d658 5350 break;
79e53945 5351 }
43565a06 5352
c751ce4f 5353 num_connectors++;
79e53945
JB		 5354 }
5355
c1858123 5356 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5357 factor = 21;
5358 if (is_lvds) {
5359 if ((intel_panel_use_ssc(dev_priv) &&
5360 dev_priv->lvds_ssc_freq == 100) ||
5361 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5362 factor = 25;
5363 } else if (is_sdvo && is_tv)
5364 factor = 20;
c1858123 5365
de13a2e3 5366 if (clock->m < factor * clock->n)
8febb297 5367 fp |= FP_CB_TUNE;
2c07245f 5368
5eddb70b 5369 dpll = 0;
2c07245f 5370
a07d6787
EA		 5371 if (is_lvds)
5372 dpll |= DPLLB_MODE_LVDS;
5373 else
5374 dpll |= DPLLB_MODE_DAC_SERIAL;
5375 if (is_sdvo) {
de13a2e3 5376 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
a07d6787
EA		 5377 if (pixel_multiplier > 1) {
5378 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5379 }
a07d6787
EA		 5380 dpll |= DPLL_DVO_HIGH_SPEED;
5381 }
e3aef172 5382 if (is_dp && !is_cpu_edp)
a07d6787 5383 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5384
a07d6787 5385 /* compute bitmask from p1 value */
de13a2e3 5386 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5387 /* also FPA1 */
de13a2e3 5388 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5389
de13a2e3 5390 switch (clock->p2) {
a07d6787
EA		 5391 case 5:
5392 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5393 break;
5394 case 7:
5395 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5396 break;
5397 case 10:
5398 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5399 break;
5400 case 14:
5401 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5402 break;
79e53945
JB		 5403 }
5404
43565a06
KH		 5405 if (is_sdvo && is_tv)
5406 dpll |= PLL_REF_INPUT_TVCLKINBC;
5407 else if (is_tv)
79e53945 5408 /* XXX: just matching BIOS for now */
43565a06 5409 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5410 dpll |= 3;
a7615030 5411 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5412 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5413 else
5414 dpll |= PLL_REF_INPUT_DREFCLK;
5415
de13a2e3
PZ		 5416 return dpll;
5417}
5418
5419static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5420 struct drm_display_mode *mode,
5421 struct drm_display_mode *adjusted_mode,
5422 int x, int y,
5423 struct drm_framebuffer *fb)
5424{
5425 struct drm_device *dev = crtc->dev;
5426 struct drm_i915_private *dev_priv = dev->dev_private;
5427 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5428 int pipe = intel_crtc->pipe;
5429 int plane = intel_crtc->plane;
5430 int num_connectors = 0;
5431 intel_clock_t clock, reduced_clock;
5432 u32 dpll, fp = 0, fp2 = 0;
e2f12b07
PZ		 5433 bool ok, has_reduced_clock = false;
5434 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
de13a2e3
PZ		 5435 struct intel_encoder *encoder;
5436 u32 temp;
5437 int ret;
01a415fd 5438 bool dither, fdi_config_ok;
de13a2e3
PZ		 5439
5440 for_each_encoder_on_crtc(dev, crtc, encoder) {
5441 switch (encoder->type) {
5442 case INTEL_OUTPUT_LVDS:
5443 is_lvds = true;
5444 break;
de13a2e3
PZ		 5445 case INTEL_OUTPUT_DISPLAYPORT:
5446 is_dp = true;
5447 break;
5448 case INTEL_OUTPUT_EDP:
5449 is_dp = true;
e2f12b07 5450 if (!intel_encoder_is_pch_edp(&encoder->base))
de13a2e3
PZ		 5451 is_cpu_edp = true;
5452 break;
5453 }
5454
5455 num_connectors++;
5456 }
5457
5dc5298b
PZ		 5458 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5459 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5460
de13a2e3
PZ		 5461 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5462 &has_reduced_clock, &reduced_clock);
5463 if (!ok) {
5464 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5465 return -EINVAL;
5466 }
5467
5468 /* Ensure that the cursor is valid for the new mode before changing... */
5469 intel_crtc_update_cursor(crtc, true);
5470
5471 /* determine panel color depth */
c8241969
JN		 5472 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5473 adjusted_mode);
de13a2e3
PZ		 5474 if (is_lvds && dev_priv->lvds_dither)
5475 dither = true;
5476
5477 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5478 if (has_reduced_clock)
5479 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5480 reduced_clock.m2;
5481
5482 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5483
f7cb34d4 5484 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5485 drm_mode_debug_printmodeline(mode);
5486
5dc5298b
PZ		 5487 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5488 if (!is_cpu_edp) {
ee7b9f93 5489 struct intel_pch_pll *pll;
4b645f14 5490
ee7b9f93
JB		 5491 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5492 if (pll == NULL) {
5493 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5494 pipe);
4b645f14
JB		 5495 return -EINVAL;
5496 }
ee7b9f93
JB		 5497 } else
5498 intel_put_pch_pll(intel_crtc);
79e53945
JB		 5499
5500 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5501 * This is an exception to the general rule that mode_set doesn't turn
5502 * things on.
5503 */
5504 if (is_lvds) {
fae14981 5505 temp = I915_READ(PCH_LVDS);
5eddb70b 5506 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 5507 if (HAS_PCH_CPT(dev)) {
5508 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 5509 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 5510 } else {
5511 if (pipe == 1)
5512 temp |= LVDS_PIPEB_SELECT;
5513 else
5514 temp &= ~LVDS_PIPEB_SELECT;
5515 }
4b645f14 5516
a3e17eb8 5517 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5518 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5519 /* Set the B0-B3 data pairs corresponding to whether we're going to
5520 * set the DPLLs for dual-channel mode or not.
5521 */
5522 if (clock.p2 == 7)
5eddb70b 5523 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5524 else
5eddb70b 5525 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5526
5527 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5528 * appropriately here, but we need to look more thoroughly into how
5529 * panels behave in the two modes.
5530 */
284d5df5 5531 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
aa9b500d 5532 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 5533 temp |= LVDS_HSYNC_POLARITY;
aa9b500d 5534 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 5535 temp |= LVDS_VSYNC_POLARITY;
fae14981 5536 I915_WRITE(PCH_LVDS, temp);
79e53945 5537 }
434ed097 5538
e3aef172 5539 if (is_dp && !is_cpu_edp) {
a4fc5ed6 5540 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 5541 } else {
8db9d77b 5542 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 5543 I915_WRITE(TRANSDATA_M1(pipe), 0);
5544 I915_WRITE(TRANSDATA_N1(pipe), 0);
5545 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5546 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 5547 }
79e53945 5548
ee7b9f93
JB		 5549 if (intel_crtc->pch_pll) {
5550 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5551
32f9d658 5552 /* Wait for the clocks to stabilize. */
ee7b9f93 5553 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5554 udelay(150);
5555
8febb297
EA		 5556 /* The pixel multiplier can only be updated once the
5557 * DPLL is enabled and the clocks are stable.
5558 *
5559 * So write it again.
5560 */
ee7b9f93 5561 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5562 }
79e53945 5563
5eddb70b 5564 intel_crtc->lowfreq_avail = false;
ee7b9f93 5565 if (intel_crtc->pch_pll) {
4b645f14 5566 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5567 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5568 intel_crtc->lowfreq_avail = true;
4b645f14 5569 } else {
ee7b9f93 5570 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5571 }
5572 }
5573
b0e77b9c 5574 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
2c07245f 5575
01a415fd
DV		 5576 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5577 * ironlake_check_fdi_lanes. */
f48d8f23 5578 ironlake_set_m_n(crtc, mode, adjusted_mode);
2c07245f 5579
01a415fd
DV		 5580 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5581
e3aef172 5582 if (is_cpu_edp)
8febb297 5583 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f 5584
c8203565 5585 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5586
9d0498a2 5587 intel_wait_for_vblank(dev, pipe);
79e53945 5588
a1f9e77e
PZ		 5589 /* Set up the display plane register */
5590 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5591 POSTING_READ(DSPCNTR(plane));
79e53945 5592
94352cf9 5593 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5594
5595 intel_update_watermarks(dev);
5596
1f8eeabf
ED		 5597 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5598
01a415fd 5599 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5600}
5601
09b4ddf9
PZ		 5602static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5603 struct drm_display_mode *mode,
5604 struct drm_display_mode *adjusted_mode,
5605 int x, int y,
5606 struct drm_framebuffer *fb)
5607{
5608 struct drm_device *dev = crtc->dev;
5609 struct drm_i915_private *dev_priv = dev->dev_private;
5610 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5611 int pipe = intel_crtc->pipe;
5612 int plane = intel_crtc->plane;
5613 int num_connectors = 0;
5614 intel_clock_t clock, reduced_clock;
5dc5298b 5615 u32 dpll = 0, fp = 0, fp2 = 0;
09b4ddf9
PZ		 5616 bool ok, has_reduced_clock = false;
5617 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5618 struct intel_encoder *encoder;
5619 u32 temp;
5620 int ret;
5621 bool dither;
5622
5623 for_each_encoder_on_crtc(dev, crtc, encoder) {
5624 switch (encoder->type) {
5625 case INTEL_OUTPUT_LVDS:
5626 is_lvds = true;
5627 break;
5628 case INTEL_OUTPUT_DISPLAYPORT:
5629 is_dp = true;
5630 break;
5631 case INTEL_OUTPUT_EDP:
5632 is_dp = true;
5633 if (!intel_encoder_is_pch_edp(&encoder->base))
5634 is_cpu_edp = true;
5635 break;
5636 }
5637
5638 num_connectors++;
5639 }
5640
a5c961d1
PZ		 5641 if (is_cpu_edp)
5642 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5643 else
5644 intel_crtc->cpu_transcoder = pipe;
5645
5dc5298b
PZ		 5646 /* We are not sure yet this won't happen. */
5647 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5648 INTEL_PCH_TYPE(dev));
5649
5650 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5651 num_connectors, pipe_name(pipe));
5652
702e7a56 5653 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
1ce42920
PZ		 5654 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5655
5656 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5657
6441ab5f
PZ		 5658 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5659 return -EINVAL;
5660
5dc5298b
PZ		 5661 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5662 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5663 &has_reduced_clock,
5664 &reduced_clock);
5665 if (!ok) {
5666 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5667 return -EINVAL;
5668 }
09b4ddf9
PZ		 5669 }
5670
5671 /* Ensure that the cursor is valid for the new mode before changing... */
5672 intel_crtc_update_cursor(crtc, true);
5673
5674 /* determine panel color depth */
c8241969
JN		 5675 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5676 adjusted_mode);
09b4ddf9
PZ		 5677 if (is_lvds && dev_priv->lvds_dither)
5678 dither = true;
5679
09b4ddf9
PZ		 5680 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5681 drm_mode_debug_printmodeline(mode);
5682
5dc5298b
PZ		 5683 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5684 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5685 if (has_reduced_clock)
5686 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5687 reduced_clock.m2;
5688
5689 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5690 fp);
5691
5692 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5693 * own on pre-Haswell/LPT generation */
5694 if (!is_cpu_edp) {
5695 struct intel_pch_pll *pll;
5696
5697 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5698 if (pll == NULL) {
5699 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5700 pipe);
5701 return -EINVAL;
5702 }
5703 } else
5704 intel_put_pch_pll(intel_crtc);
09b4ddf9 5705
5dc5298b
PZ		 5706 /* The LVDS pin pair needs to be on before the DPLLs are
5707 * enabled. This is an exception to the general rule that
5708 * mode_set doesn't turn things on.
5709 */
5710 if (is_lvds) {
5711 temp = I915_READ(PCH_LVDS);
5712 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5713 if (HAS_PCH_CPT(dev)) {
5714 temp &= ~PORT_TRANS_SEL_MASK;
5715 temp |= PORT_TRANS_SEL_CPT(pipe);
5716 } else {
5717 if (pipe == 1)
5718 temp |= LVDS_PIPEB_SELECT;
5719 else
5720 temp &= ~LVDS_PIPEB_SELECT;
5721 }
09b4ddf9 5722
5dc5298b
PZ		 5723 /* set the corresponsding LVDS_BORDER bit */
5724 temp |= dev_priv->lvds_border_bits;
5725 /* Set the B0-B3 data pairs corresponding to whether
5726 * we're going to set the DPLLs for dual-channel mode or
5727 * not.
5728 */
5729 if (clock.p2 == 7)
5730 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
09b4ddf9 5731 else
5dc5298b
PZ		 5732 temp &= ~(LVDS_B0B3_POWER_UP |
5733 LVDS_CLKB_POWER_UP);
5734
5735 /* It would be nice to set 24 vs 18-bit mode
5736 * (LVDS_A3_POWER_UP) appropriately here, but we need to
5737 * look more thoroughly into how panels behave in the
5738 * two modes.
5739 */
5740 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5741 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5742 temp |= LVDS_HSYNC_POLARITY;
5743 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5744 temp |= LVDS_VSYNC_POLARITY;
5745 I915_WRITE(PCH_LVDS, temp);
09b4ddf9 5746 }
09b4ddf9
PZ		 5747 }
5748
5749 if (is_dp && !is_cpu_edp) {
5750 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5751 } else {
5dc5298b
PZ		 5752 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5753 /* For non-DP output, clear any trans DP clock recovery
5754 * setting.*/
5755 I915_WRITE(TRANSDATA_M1(pipe), 0);
5756 I915_WRITE(TRANSDATA_N1(pipe), 0);
5757 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5758 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5759 }
09b4ddf9
PZ		 5760 }
5761
5762 intel_crtc->lowfreq_avail = false;
5dc5298b
PZ		 5763 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5764 if (intel_crtc->pch_pll) {
5765 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5766
5767 /* Wait for the clocks to stabilize. */
5768 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5769 udelay(150);
5770
5771 /* The pixel multiplier can only be updated once the
5772 * DPLL is enabled and the clocks are stable.
5773 *
5774 * So write it again.
5775 */
5776 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5777 }
5778
5779 if (intel_crtc->pch_pll) {
5780 if (is_lvds && has_reduced_clock && i915_powersave) {
5781 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5782 intel_crtc->lowfreq_avail = true;
5783 } else {
5784 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5785 }
09b4ddf9
PZ		 5786 }
5787 }
5788
5789 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5790
1eb8dfec
PZ		 5791 if (!is_dp || is_cpu_edp)
5792 ironlake_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9 5793
5dc5298b
PZ		 5794 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5795 if (is_cpu_edp)
5796 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
09b4ddf9 5797
ee2b0b38 5798 haswell_set_pipeconf(crtc, adjusted_mode, dither);
09b4ddf9 5799
09b4ddf9
PZ		 5800 /* Set up the display plane register */
5801 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5802 POSTING_READ(DSPCNTR(plane));
5803
5804 ret = intel_pipe_set_base(crtc, x, y, fb);
5805
5806 intel_update_watermarks(dev);
5807
5808 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5809
5810 return ret;
5811}
5812
f564048e
EA		 5813static int intel_crtc_mode_set(struct drm_crtc *crtc,
5814 struct drm_display_mode *mode,
5815 struct drm_display_mode *adjusted_mode,
5816 int x, int y,
94352cf9 5817 struct drm_framebuffer *fb)
f564048e
EA		 5818{
5819 struct drm_device *dev = crtc->dev;
5820 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5821 struct drm_encoder_helper_funcs *encoder_funcs;
5822 struct intel_encoder *encoder;
0b701d27
EA		 5823 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5824 int pipe = intel_crtc->pipe;
f564048e
EA		 5825 int ret;
5826
0b701d27 5827 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5828
f564048e 5829 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
94352cf9 5830 x, y, fb);
79e53945 5831 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5832
9256aa19
DV		 5833 if (ret != 0)
5834 return ret;
5835
5836 for_each_encoder_on_crtc(dev, crtc, encoder) {
5837 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5838 encoder->base.base.id,
5839 drm_get_encoder_name(&encoder->base),
5840 mode->base.id, mode->name);
5841 encoder_funcs = encoder->base.helper_private;
5842 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5843 }
5844
5845 return 0;
79e53945
JB		 5846}
5847
3a9627f4
WF		 5848static bool intel_eld_uptodate(struct drm_connector *connector,
5849 int reg_eldv, uint32_t bits_eldv,
5850 int reg_elda, uint32_t bits_elda,
5851 int reg_edid)
5852{
5853 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5854 uint8_t *eld = connector->eld;
5855 uint32_t i;
5856
5857 i = I915_READ(reg_eldv);
5858 i &= bits_eldv;
5859
5860 if (!eld[0])
5861 return !i;
5862
5863 if (!i)
5864 return false;
5865
5866 i = I915_READ(reg_elda);
5867 i &= ~bits_elda;
5868 I915_WRITE(reg_elda, i);
5869
5870 for (i = 0; i < eld[2]; i++)
5871 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5872 return false;
5873
5874 return true;
5875}
5876
e0dac65e
WF		 5877static void g4x_write_eld(struct drm_connector *connector,
5878 struct drm_crtc *crtc)
5879{
5880 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5881 uint8_t *eld = connector->eld;
5882 uint32_t eldv;
5883 uint32_t len;
5884 uint32_t i;
5885
5886 i = I915_READ(G4X_AUD_VID_DID);
5887
5888 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5889 eldv = G4X_ELDV_DEVCL_DEVBLC;
5890 else
5891 eldv = G4X_ELDV_DEVCTG;
5892
3a9627f4
WF		 5893 if (intel_eld_uptodate(connector,
5894 G4X_AUD_CNTL_ST, eldv,
5895 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5896 G4X_HDMIW_HDMIEDID))
5897 return;
5898
e0dac65e
WF		 5899 i = I915_READ(G4X_AUD_CNTL_ST);
5900 i &= ~(eldv | G4X_ELD_ADDR);
5901 len = (i >> 9) & 0x1f; /* ELD buffer size */
5902 I915_WRITE(G4X_AUD_CNTL_ST, i);
5903
5904 if (!eld[0])
5905 return;
5906
5907 len = min_t(uint8_t, eld[2], len);
5908 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5909 for (i = 0; i < len; i++)
5910 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5911
5912 i = I915_READ(G4X_AUD_CNTL_ST);
5913 i |= eldv;
5914 I915_WRITE(G4X_AUD_CNTL_ST, i);
5915}
5916
83358c85
WX		 5917static void haswell_write_eld(struct drm_connector *connector,
5918 struct drm_crtc *crtc)
5919{
5920 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5921 uint8_t *eld = connector->eld;
5922 struct drm_device *dev = crtc->dev;
5923 uint32_t eldv;
5924 uint32_t i;
5925 int len;
5926 int pipe = to_intel_crtc(crtc)->pipe;
5927 int tmp;
5928
5929 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5930 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5931 int aud_config = HSW_AUD_CFG(pipe);
5932 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5933
5934
5935 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5936
5937 /* Audio output enable */
5938 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5939 tmp = I915_READ(aud_cntrl_st2);
5940 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5941 I915_WRITE(aud_cntrl_st2, tmp);
5942
5943 /* Wait for 1 vertical blank */
5944 intel_wait_for_vblank(dev, pipe);
5945
5946 /* Set ELD valid state */
5947 tmp = I915_READ(aud_cntrl_st2);
5948 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5949 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5950 I915_WRITE(aud_cntrl_st2, tmp);
5951 tmp = I915_READ(aud_cntrl_st2);
5952 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5953
5954 /* Enable HDMI mode */
5955 tmp = I915_READ(aud_config);
5956 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5957 /* clear N_programing_enable and N_value_index */
5958 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5959 I915_WRITE(aud_config, tmp);
5960
5961 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5962
5963 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5964
5965 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5966 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5967 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5968 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5969 } else
5970 I915_WRITE(aud_config, 0);
5971
5972 if (intel_eld_uptodate(connector,
5973 aud_cntrl_st2, eldv,
5974 aud_cntl_st, IBX_ELD_ADDRESS,
5975 hdmiw_hdmiedid))
5976 return;
5977
5978 i = I915_READ(aud_cntrl_st2);
5979 i &= ~eldv;
5980 I915_WRITE(aud_cntrl_st2, i);
5981
5982 if (!eld[0])
5983 return;
5984
5985 i = I915_READ(aud_cntl_st);
5986 i &= ~IBX_ELD_ADDRESS;
5987 I915_WRITE(aud_cntl_st, i);
5988 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5989 DRM_DEBUG_DRIVER("port num:%d\n", i);
5990
5991 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5992 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5993 for (i = 0; i < len; i++)
5994 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5995
5996 i = I915_READ(aud_cntrl_st2);
5997 i |= eldv;
5998 I915_WRITE(aud_cntrl_st2, i);
5999
6000}
6001
e0dac65e
WF		 6002static void ironlake_write_eld(struct drm_connector *connector,
6003 struct drm_crtc *crtc)
6004{
6005 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6006 uint8_t *eld = connector->eld;
6007 uint32_t eldv;
6008 uint32_t i;
6009 int len;
6010 int hdmiw_hdmiedid;
b6daa025 6011 int aud_config;
e0dac65e
WF		 6012 int aud_cntl_st;
6013 int aud_cntrl_st2;
9b138a83 6014 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6015
b3f33cbf 6016 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6017 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6018 aud_config = IBX_AUD_CFG(pipe);
6019 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6020 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6021 } else {
9b138a83
WX		 6022 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6023 aud_config = CPT_AUD_CFG(pipe);
6024 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6025 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6026 }
6027
9b138a83 6028 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6029
6030 i = I915_READ(aud_cntl_st);
9b138a83 6031 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6032 if (!i) {
6033 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6034 /* operate blindly on all ports */
1202b4c6
WF		 6035 eldv = IBX_ELD_VALIDB;
6036 eldv |= IBX_ELD_VALIDB << 4;
6037 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 6038 } else {
6039 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 6040 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6041 }
6042
3a9627f4
WF		 6043 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6044 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6045 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6046 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6047 } else
6048 I915_WRITE(aud_config, 0);
e0dac65e 6049
3a9627f4
WF		 6050 if (intel_eld_uptodate(connector,
6051 aud_cntrl_st2, eldv,
6052 aud_cntl_st, IBX_ELD_ADDRESS,
6053 hdmiw_hdmiedid))
6054 return;
6055
e0dac65e
WF		 6056 i = I915_READ(aud_cntrl_st2);
6057 i &= ~eldv;
6058 I915_WRITE(aud_cntrl_st2, i);
6059
6060 if (!eld[0])
6061 return;
6062
e0dac65e 6063 i = I915_READ(aud_cntl_st);
1202b4c6 6064 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6065 I915_WRITE(aud_cntl_st, i);
6066
6067 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6068 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6069 for (i = 0; i < len; i++)
6070 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6071
6072 i = I915_READ(aud_cntrl_st2);
6073 i |= eldv;
6074 I915_WRITE(aud_cntrl_st2, i);
6075}
6076
6077void intel_write_eld(struct drm_encoder *encoder,
6078 struct drm_display_mode *mode)
6079{
6080 struct drm_crtc *crtc = encoder->crtc;
6081 struct drm_connector *connector;
6082 struct drm_device *dev = encoder->dev;
6083 struct drm_i915_private *dev_priv = dev->dev_private;
6084
6085 connector = drm_select_eld(encoder, mode);
6086 if (!connector)
6087 return;
6088
6089 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6090 connector->base.id,
6091 drm_get_connector_name(connector),
6092 connector->encoder->base.id,
6093 drm_get_encoder_name(connector->encoder));
6094
6095 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6096
6097 if (dev_priv->display.write_eld)
6098 dev_priv->display.write_eld(connector, crtc);
6099}
6100
79e53945
JB		 6101/** Loads the palette/gamma unit for the CRTC with the prepared values */
6102void intel_crtc_load_lut(struct drm_crtc *crtc)
6103{
6104 struct drm_device *dev = crtc->dev;
6105 struct drm_i915_private *dev_priv = dev->dev_private;
6106 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6107 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6108 int i;
6109
6110 /* The clocks have to be on to load the palette. */
aed3f09d 6111 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6112 return;
6113
f2b115e6 6114 /* use legacy palette for Ironlake */
bad720ff 6115 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6116 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6117
79e53945
JB		 6118 for (i = 0; i < 256; i++) {
6119 I915_WRITE(palreg + 4 * i,
6120 (intel_crtc->lut_r[i] << 16) |
6121 (intel_crtc->lut_g[i] << 8) |
6122 intel_crtc->lut_b[i]);
6123 }
6124}
6125
560b85bb
CW		 6126static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6127{
6128 struct drm_device *dev = crtc->dev;
6129 struct drm_i915_private *dev_priv = dev->dev_private;
6130 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6131 bool visible = base != 0;
6132 u32 cntl;
6133
6134 if (intel_crtc->cursor_visible == visible)
6135 return;
6136
9db4a9c7 6137 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6138 if (visible) {
6139 /* On these chipsets we can only modify the base whilst
6140 * the cursor is disabled.
6141 */
9db4a9c7 6142 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6143
6144 cntl &= ~(CURSOR_FORMAT_MASK);
6145 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6146 cntl |= CURSOR_ENABLE |
6147 CURSOR_GAMMA_ENABLE |
6148 CURSOR_FORMAT_ARGB;
6149 } else
6150 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6151 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6152
6153 intel_crtc->cursor_visible = visible;
6154}
6155
6156static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6157{
6158 struct drm_device *dev = crtc->dev;
6159 struct drm_i915_private *dev_priv = dev->dev_private;
6160 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6161 int pipe = intel_crtc->pipe;
6162 bool visible = base != 0;
6163
6164 if (intel_crtc->cursor_visible != visible) {
548f245b 6165 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6166 if (base) {
6167 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6168 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6169 cntl |= pipe << 28; /* Connect to correct pipe */
6170 } else {
6171 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6172 cntl |= CURSOR_MODE_DISABLE;
6173 }
9db4a9c7 6174 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6175
6176 intel_crtc->cursor_visible = visible;
6177 }
6178 /* and commit changes on next vblank */
9db4a9c7 6179 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6180}
6181
65a21cd6
JB		 6182static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6183{
6184 struct drm_device *dev = crtc->dev;
6185 struct drm_i915_private *dev_priv = dev->dev_private;
6186 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6187 int pipe = intel_crtc->pipe;
6188 bool visible = base != 0;
6189
6190 if (intel_crtc->cursor_visible != visible) {
6191 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6192 if (base) {
6193 cntl &= ~CURSOR_MODE;
6194 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6195 } else {
6196 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6197 cntl |= CURSOR_MODE_DISABLE;
6198 }
6199 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6200
6201 intel_crtc->cursor_visible = visible;
6202 }
6203 /* and commit changes on next vblank */
6204 I915_WRITE(CURBASE_IVB(pipe), base);
6205}
6206
cda4b7d3 6207/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6208static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6209 bool on)
cda4b7d3
CW		 6210{
6211 struct drm_device *dev = crtc->dev;
6212 struct drm_i915_private *dev_priv = dev->dev_private;
6213 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6214 int pipe = intel_crtc->pipe;
6215 int x = intel_crtc->cursor_x;
6216 int y = intel_crtc->cursor_y;
560b85bb 6217 u32 base, pos;
cda4b7d3
CW		 6218 bool visible;
6219
6220 pos = 0;
6221
6b383a7f 6222 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6223 base = intel_crtc->cursor_addr;
6224 if (x > (int) crtc->fb->width)
6225 base = 0;
6226
6227 if (y > (int) crtc->fb->height)
6228 base = 0;
6229 } else
6230 base = 0;
6231
6232 if (x < 0) {
6233 if (x + intel_crtc->cursor_width < 0)
6234 base = 0;
6235
6236 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6237 x = -x;
6238 }
6239 pos |= x << CURSOR_X_SHIFT;
6240
6241 if (y < 0) {
6242 if (y + intel_crtc->cursor_height < 0)
6243 base = 0;
6244
6245 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6246 y = -y;
6247 }
6248 pos |= y << CURSOR_Y_SHIFT;
6249
6250 visible = base != 0;
560b85bb 6251 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6252 return;
6253
0cd83aa9 6254 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6255 I915_WRITE(CURPOS_IVB(pipe), pos);
6256 ivb_update_cursor(crtc, base);
6257 } else {
6258 I915_WRITE(CURPOS(pipe), pos);
6259 if (IS_845G(dev) || IS_I865G(dev))
6260 i845_update_cursor(crtc, base);
6261 else
6262 i9xx_update_cursor(crtc, base);
6263 }
cda4b7d3
CW		 6264}
6265
79e53945 6266static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6267 struct drm_file *file,
79e53945
JB		 6268 uint32_t handle,
6269 uint32_t width, uint32_t height)
6270{
6271 struct drm_device *dev = crtc->dev;
6272 struct drm_i915_private *dev_priv = dev->dev_private;
6273 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6274 struct drm_i915_gem_object *obj;
cda4b7d3 6275 uint32_t addr;
3f8bc370 6276 int ret;
79e53945 6277
79e53945
JB		 6278 /* if we want to turn off the cursor ignore width and height */
6279 if (!handle) {
28c97730 6280 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6281 addr = 0;
05394f39 6282 obj = NULL;
5004417d 6283 mutex_lock(&dev->struct_mutex);
3f8bc370 6284 goto finish;
79e53945
JB		 6285 }
6286
6287 /* Currently we only support 64x64 cursors */
6288 if (width != 64 || height != 64) {
6289 DRM_ERROR("we currently only support 64x64 cursors\n");
6290 return -EINVAL;
6291 }
6292
05394f39 6293 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6294 if (&obj->base == NULL)
79e53945
JB		 6295 return -ENOENT;
6296
05394f39 6297 if (obj->base.size < width * height * 4) {
79e53945 6298 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6299 ret = -ENOMEM;
6300 goto fail;
79e53945
JB		 6301 }
6302
71acb5eb 6303 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6304 mutex_lock(&dev->struct_mutex);
b295d1b6 6305 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 6306 if (obj->tiling_mode) {
6307 DRM_ERROR("cursor cannot be tiled\n");
6308 ret = -EINVAL;
6309 goto fail_locked;
6310 }
6311
2da3b9b9 6312 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 6313 if (ret) {
6314 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6315 goto fail_locked;
e7b526bb
CW		 6316 }
6317
d9e86c0e
CW		 6318 ret = i915_gem_object_put_fence(obj);
6319 if (ret) {
2da3b9b9 6320 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6321 goto fail_unpin;
6322 }
6323
05394f39 6324 addr = obj->gtt_offset;
71acb5eb 6325 } else {
6eeefaf3 6326 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6327 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6328 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6329 align);
71acb5eb
DA		 6330 if (ret) {
6331 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6332 goto fail_locked;
71acb5eb 6333 }
05394f39 6334 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6335 }
6336
a6c45cf0 6337 if (IS_GEN2(dev))
14b60391
JB		 6338 I915_WRITE(CURSIZE, (height << 12) | width);
6339
3f8bc370 6340 finish:
3f8bc370 6341 if (intel_crtc->cursor_bo) {
b295d1b6 6342 if (dev_priv->info->cursor_needs_physical) {
05394f39 6343 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6344 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6345 } else
6346 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6347 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6348 }
80824003 6349
7f9872e0 6350 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6351
6352 intel_crtc->cursor_addr = addr;
05394f39 6353 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6354 intel_crtc->cursor_width = width;
6355 intel_crtc->cursor_height = height;
6356
6b383a7f 6357 intel_crtc_update_cursor(crtc, true);
3f8bc370 6358
79e53945 6359 return 0;
e7b526bb 6360fail_unpin:
05394f39 6361 i915_gem_object_unpin(obj);
7f9872e0 6362fail_locked:
34b8686e 6363 mutex_unlock(&dev->struct_mutex);
bc9025bd 6364fail:
05394f39 6365 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6366 return ret;
79e53945
JB		 6367}
6368
6369static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6370{
79e53945 6371 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6372
cda4b7d3
CW		 6373 intel_crtc->cursor_x = x;
6374 intel_crtc->cursor_y = y;
652c393a 6375
6b383a7f 6376 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6377
6378 return 0;
6379}
6380
6381/** Sets the color ramps on behalf of RandR */
6382void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6383 u16 blue, int regno)
6384{
6385 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6386
6387 intel_crtc->lut_r[regno] = red >> 8;
6388 intel_crtc->lut_g[regno] = green >> 8;
6389 intel_crtc->lut_b[regno] = blue >> 8;
6390}
6391
b8c00ac5
DA		 6392void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6393 u16 *blue, int regno)
6394{
6395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6396
6397 *red = intel_crtc->lut_r[regno] << 8;
6398 *green = intel_crtc->lut_g[regno] << 8;
6399 *blue = intel_crtc->lut_b[regno] << 8;
6400}
6401
79e53945 6402static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6403 u16 *blue, uint32_t start, uint32_t size)
79e53945 6404{
7203425a 6405 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6406 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6407
7203425a 6408 for (i = start; i < end; i++) {
79e53945
JB		 6409 intel_crtc->lut_r[i] = red[i] >> 8;
6410 intel_crtc->lut_g[i] = green[i] >> 8;
6411 intel_crtc->lut_b[i] = blue[i] >> 8;
6412 }
6413
6414 intel_crtc_load_lut(crtc);
6415}
6416
6417/**
6418 * Get a pipe with a simple mode set on it for doing load-based monitor
6419 * detection.
6420 *
6421 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 6422 * its requirements. The pipe will be connected to no other encoders.
79e53945 6423 *
c751ce4f 6424 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 6425 * configured for it. In the future, it could choose to temporarily disable
6426 * some outputs to free up a pipe for its use.
6427 *
6428 * \return crtc, or NULL if no pipes are available.
6429 */
6430
6431/* VESA 640x480x72Hz mode to set on the pipe */
6432static struct drm_display_mode load_detect_mode = {
6433 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6434 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6435};
6436
d2dff872
CW		 6437static struct drm_framebuffer *
6438intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6439 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6440 struct drm_i915_gem_object *obj)
6441{
6442 struct intel_framebuffer *intel_fb;
6443 int ret;
6444
6445 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6446 if (!intel_fb) {
6447 drm_gem_object_unreference_unlocked(&obj->base);
6448 return ERR_PTR(-ENOMEM);
6449 }
6450
6451 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6452 if (ret) {
6453 drm_gem_object_unreference_unlocked(&obj->base);
6454 kfree(intel_fb);
6455 return ERR_PTR(ret);
6456 }
6457
6458 return &intel_fb->base;
6459}
6460
6461static u32
6462intel_framebuffer_pitch_for_width(int width, int bpp)
6463{
6464 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6465 return ALIGN(pitch, 64);
6466}
6467
6468static u32
6469intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6470{
6471 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6472 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6473}
6474
6475static struct drm_framebuffer *
6476intel_framebuffer_create_for_mode(struct drm_device *dev,
6477 struct drm_display_mode *mode,
6478 int depth, int bpp)
6479{
6480 struct drm_i915_gem_object *obj;
308e5bcb 6481 struct drm_mode_fb_cmd2 mode_cmd;
d2dff872
CW		 6482
6483 obj = i915_gem_alloc_object(dev,
6484 intel_framebuffer_size_for_mode(mode, bpp));
6485 if (obj == NULL)
6486 return ERR_PTR(-ENOMEM);
6487
6488 mode_cmd.width = mode->hdisplay;
6489 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6490 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6491 bpp);
5ca0c34a 6492 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6493
6494 return intel_framebuffer_create(dev, &mode_cmd, obj);
6495}
6496
6497static struct drm_framebuffer *
6498mode_fits_in_fbdev(struct drm_device *dev,
6499 struct drm_display_mode *mode)
6500{
6501 struct drm_i915_private *dev_priv = dev->dev_private;
6502 struct drm_i915_gem_object *obj;
6503 struct drm_framebuffer *fb;
6504
6505 if (dev_priv->fbdev == NULL)
6506 return NULL;
6507
6508 obj = dev_priv->fbdev->ifb.obj;
6509 if (obj == NULL)
6510 return NULL;
6511
6512 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6513 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6514 fb->bits_per_pixel))
d2dff872
CW		 6515 return NULL;
6516
01f2c773 6517 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6518 return NULL;
6519
6520 return fb;
6521}
6522
d2434ab7 6523bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6524 struct drm_display_mode *mode,
8261b191 6525 struct intel_load_detect_pipe *old)
79e53945
JB		 6526{
6527 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6528 struct intel_encoder *intel_encoder =
6529 intel_attached_encoder(connector);
79e53945 6530 struct drm_crtc *possible_crtc;
4ef69c7a 6531 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6532 struct drm_crtc *crtc = NULL;
6533 struct drm_device *dev = encoder->dev;
94352cf9 6534 struct drm_framebuffer *fb;
79e53945
JB		 6535 int i = -1;
6536
d2dff872
CW		 6537 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6538 connector->base.id, drm_get_connector_name(connector),
6539 encoder->base.id, drm_get_encoder_name(encoder));
6540
79e53945
JB		 6541 /*
6542 * Algorithm gets a little messy:
7a5e4805 6543 *
79e53945
JB		 6544 * - if the connector already has an assigned crtc, use it (but make
6545 * sure it's on first)
7a5e4805 6546 *
79e53945
JB		 6547 * - try to find the first unused crtc that can drive this connector,
6548 * and use that if we find one
79e53945
JB		 6549 */
6550
6551 /* See if we already have a CRTC for this connector */
6552 if (encoder->crtc) {
6553 crtc = encoder->crtc;
8261b191 6554
24218aac 6555 old->dpms_mode = connector->dpms;
8261b191
CW		 6556 old->load_detect_temp = false;
6557
6558 /* Make sure the crtc and connector are running */
24218aac
DV		 6559 if (connector->dpms != DRM_MODE_DPMS_ON)
6560 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6561
7173188d 6562 return true;
79e53945
JB		 6563 }
6564
6565 /* Find an unused one (if possible) */
6566 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6567 i++;
6568 if (!(encoder->possible_crtcs & (1 << i)))
6569 continue;
6570 if (!possible_crtc->enabled) {
6571 crtc = possible_crtc;
6572 break;
6573 }
79e53945
JB		 6574 }
6575
6576 /*
6577 * If we didn't find an unused CRTC, don't use any.
6578 */
6579 if (!crtc) {
7173188d
CW		 6580 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6581 return false;
79e53945
JB		 6582 }
6583
fc303101
DV		 6584 intel_encoder->new_crtc = to_intel_crtc(crtc);
6585 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6586
6587 intel_crtc = to_intel_crtc(crtc);
24218aac 6588 old->dpms_mode = connector->dpms;
8261b191 6589 old->load_detect_temp = true;
d2dff872 6590 old->release_fb = NULL;
79e53945 6591
6492711d
CW		 6592 if (!mode)
6593 mode = &load_detect_mode;
79e53945 6594
d2dff872
CW		 6595 /* We need a framebuffer large enough to accommodate all accesses
6596 * that the plane may generate whilst we perform load detection.
6597 * We can not rely on the fbcon either being present (we get called
6598 * during its initialisation to detect all boot displays, or it may
6599 * not even exist) or that it is large enough to satisfy the
6600 * requested mode.
6601 */
94352cf9
DV		 6602 fb = mode_fits_in_fbdev(dev, mode);
6603 if (fb == NULL) {
d2dff872 6604 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6605 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6606 old->release_fb = fb;
d2dff872
CW		 6607 } else
6608 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6609 if (IS_ERR(fb)) {
d2dff872 6610 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
24218aac 6611 goto fail;
79e53945 6612 }
79e53945 6613
94352cf9 6614 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6615 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6616 if (old->release_fb)
6617 old->release_fb->funcs->destroy(old->release_fb);
24218aac 6618 goto fail;
79e53945 6619 }
7173188d 6620
79e53945 6621 /* let the connector get through one full cycle before testing */
9d0498a2 6622 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 6623
7173188d 6624 return true;
24218aac
DV		 6625fail:
6626 connector->encoder = NULL;
6627 encoder->crtc = NULL;
24218aac 6628 return false;
79e53945
JB		 6629}
6630
d2434ab7 6631void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6632 struct intel_load_detect_pipe *old)
79e53945 6633{
d2434ab7
DV		 6634 struct intel_encoder *intel_encoder =
6635 intel_attached_encoder(connector);
4ef69c7a 6636 struct drm_encoder *encoder = &intel_encoder->base;
79e53945 6637
d2dff872
CW		 6638 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6639 connector->base.id, drm_get_connector_name(connector),
6640 encoder->base.id, drm_get_encoder_name(encoder));
6641
8261b191 6642 if (old->load_detect_temp) {
fc303101
DV		 6643 struct drm_crtc *crtc = encoder->crtc;
6644
6645 to_intel_connector(connector)->new_encoder = NULL;
6646 intel_encoder->new_crtc = NULL;
6647 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872
CW		 6648
6649 if (old->release_fb)
6650 old->release_fb->funcs->destroy(old->release_fb);
6651
0622a53c 6652 return;
79e53945
JB		 6653 }
6654
c751ce4f 6655 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6656 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6657 connector->funcs->dpms(connector, old->dpms_mode);
79e53945
JB		 6658}
6659
6660/* Returns the clock of the currently programmed mode of the given pipe. */
6661static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6662{
6663 struct drm_i915_private *dev_priv = dev->dev_private;
6664 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6665 int pipe = intel_crtc->pipe;
548f245b 6666 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6667 u32 fp;
6668 intel_clock_t clock;
6669
6670 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6671 fp = I915_READ(FP0(pipe));
79e53945 6672 else
39adb7a5 6673 fp = I915_READ(FP1(pipe));
79e53945
JB		 6674
6675 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6676 if (IS_PINEVIEW(dev)) {
6677 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6678 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6679 } else {
6680 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6681 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6682 }
6683
a6c45cf0 6684 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6685 if (IS_PINEVIEW(dev))
6686 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6687 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6688 else
6689 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6690 DPLL_FPA01_P1_POST_DIV_SHIFT);
6691
6692 switch (dpll & DPLL_MODE_MASK) {
6693 case DPLLB_MODE_DAC_SERIAL:
6694 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6695 5 : 10;
6696 break;
6697 case DPLLB_MODE_LVDS:
6698 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6699 7 : 14;
6700 break;
6701 default:
28c97730 6702 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6703 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6704 return 0;
6705 }
6706
6707 /* XXX: Handle the 100Mhz refclk */
2177832f 6708 intel_clock(dev, 96000, &clock);
79e53945
JB		 6709 } else {
6710 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6711
6712 if (is_lvds) {
6713 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6714 DPLL_FPA01_P1_POST_DIV_SHIFT);
6715 clock.p2 = 14;
6716
6717 if ((dpll & PLL_REF_INPUT_MASK) ==
6718 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6719 /* XXX: might not be 66MHz */
2177832f 6720 intel_clock(dev, 66000, &clock);
79e53945 6721 } else
2177832f 6722 intel_clock(dev, 48000, &clock);
79e53945
JB		 6723 } else {
6724 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6725 clock.p1 = 2;
6726 else {
6727 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6728 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6729 }
6730 if (dpll & PLL_P2_DIVIDE_BY_4)
6731 clock.p2 = 4;
6732 else
6733 clock.p2 = 2;
6734
2177832f 6735 intel_clock(dev, 48000, &clock);
79e53945
JB		 6736 }
6737 }
6738
6739 /* XXX: It would be nice to validate the clocks, but we can't reuse
6740 * i830PllIsValid() because it relies on the xf86_config connector
6741 * configuration being accurate, which it isn't necessarily.
6742 */
6743
6744 return clock.dot;
6745}
6746
6747/** Returns the currently programmed mode of the given pipe. */
6748struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6749 struct drm_crtc *crtc)
6750{
548f245b 6751 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6752 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fe2b8f9d 6753 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
79e53945 6754 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6755 int htot = I915_READ(HTOTAL(cpu_transcoder));
6756 int hsync = I915_READ(HSYNC(cpu_transcoder));
6757 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6758 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6759
6760 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6761 if (!mode)
6762 return NULL;
6763
6764 mode->clock = intel_crtc_clock_get(dev, crtc);
6765 mode->hdisplay = (htot & 0xffff) + 1;
6766 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6767 mode->hsync_start = (hsync & 0xffff) + 1;
6768 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6769 mode->vdisplay = (vtot & 0xffff) + 1;
6770 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6771 mode->vsync_start = (vsync & 0xffff) + 1;
6772 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6773
6774 drm_mode_set_name(mode);
79e53945
JB		 6775
6776 return mode;
6777}
6778
3dec0095 6779static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6780{
6781 struct drm_device *dev = crtc->dev;
6782 drm_i915_private_t *dev_priv = dev->dev_private;
6783 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6784 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6785 int dpll_reg = DPLL(pipe);
6786 int dpll;
652c393a 6787
bad720ff 6788 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6789 return;
6790
6791 if (!dev_priv->lvds_downclock_avail)
6792 return;
6793
dbdc6479 6794 dpll = I915_READ(dpll_reg);
652c393a 6795 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6796 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6797
8ac5a6d5 6798 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6799
6800 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6801 I915_WRITE(dpll_reg, dpll);
9d0498a2 6802 intel_wait_for_vblank(dev, pipe);
dbdc6479 6803
652c393a
JB		 6804 dpll = I915_READ(dpll_reg);
6805 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6806 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6807 }
652c393a
JB		 6808}
6809
6810static void intel_decrease_pllclock(struct drm_crtc *crtc)
6811{
6812 struct drm_device *dev = crtc->dev;
6813 drm_i915_private_t *dev_priv = dev->dev_private;
6814 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6815
bad720ff 6816 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6817 return;
6818
6819 if (!dev_priv->lvds_downclock_avail)
6820 return;
6821
6822 /*
6823 * Since this is called by a timer, we should never get here in
6824 * the manual case.
6825 */
6826 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6827 int pipe = intel_crtc->pipe;
6828 int dpll_reg = DPLL(pipe);
6829 int dpll;
f6e5b160 6830
44d98a61 6831 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6832
8ac5a6d5 6833 assert_panel_unlocked(dev_priv, pipe);
652c393a 6834
dc257cf1 6835 dpll = I915_READ(dpll_reg);
652c393a
JB		 6836 dpll |= DISPLAY_RATE_SELECT_FPA1;
6837 I915_WRITE(dpll_reg, dpll);
9d0498a2 6838 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6839 dpll = I915_READ(dpll_reg);
6840 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6841 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6842 }
6843
6844}
6845
f047e395
CW		 6846void intel_mark_busy(struct drm_device *dev)
6847{
f047e395
CW		 6848 i915_update_gfx_val(dev->dev_private);
6849}
6850
6851void intel_mark_idle(struct drm_device *dev)
652c393a 6852{
f047e395
CW		 6853}
6854
6855void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6856{
6857 struct drm_device *dev = obj->base.dev;
652c393a 6858 struct drm_crtc *crtc;
652c393a
JB		 6859
6860 if (!i915_powersave)
6861 return;
6862
652c393a 6863 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6864 if (!crtc->fb)
6865 continue;
6866
f047e395
CW		 6867 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6868 intel_increase_pllclock(crtc);
652c393a 6869 }
652c393a
JB		 6870}
6871
f047e395 6872void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
652c393a 6873{
f047e395
CW		 6874 struct drm_device *dev = obj->base.dev;
6875 struct drm_crtc *crtc;
652c393a 6876
f047e395 6877 if (!i915_powersave)
acb87dfb
CW		 6878 return;
6879
652c393a
JB		 6880 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6881 if (!crtc->fb)
6882 continue;
6883
f047e395
CW		 6884 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6885 intel_decrease_pllclock(crtc);
652c393a
JB		 6886 }
6887}
6888
79e53945
JB		 6889static void intel_crtc_destroy(struct drm_crtc *crtc)
6890{
6891 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6892 struct drm_device *dev = crtc->dev;
6893 struct intel_unpin_work *work;
6894 unsigned long flags;
6895
6896 spin_lock_irqsave(&dev->event_lock, flags);
6897 work = intel_crtc->unpin_work;
6898 intel_crtc->unpin_work = NULL;
6899 spin_unlock_irqrestore(&dev->event_lock, flags);
6900
6901 if (work) {
6902 cancel_work_sync(&work->work);
6903 kfree(work);
6904 }
79e53945
JB		 6905
6906 drm_crtc_cleanup(crtc);
67e77c5a 6907
79e53945
JB		 6908 kfree(intel_crtc);
6909}
6910
6b95a207
KH		 6911static void intel_unpin_work_fn(struct work_struct *__work)
6912{
6913 struct intel_unpin_work *work =
6914 container_of(__work, struct intel_unpin_work, work);
6915
6916 mutex_lock(&work->dev->struct_mutex);
1690e1eb 6917 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6918 drm_gem_object_unreference(&work->pending_flip_obj->base);
6919 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6920
7782de3b 6921 intel_update_fbc(work->dev);
6b95a207
KH		 6922 mutex_unlock(&work->dev->struct_mutex);
6923 kfree(work);
6924}
6925
1afe3e9d 6926static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6927 struct drm_crtc *crtc)
6b95a207
KH		 6928{
6929 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6930 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6931 struct intel_unpin_work *work;
05394f39 6932 struct drm_i915_gem_object *obj;
6b95a207 6933 struct drm_pending_vblank_event *e;
95cb1b02 6934 struct timeval tvbl;
6b95a207
KH		 6935 unsigned long flags;
6936
6937 /* Ignore early vblank irqs */
6938 if (intel_crtc == NULL)
6939 return;
6940
6941 spin_lock_irqsave(&dev->event_lock, flags);
6942 work = intel_crtc->unpin_work;
6943 if (work == NULL || !work->pending) {
6944 spin_unlock_irqrestore(&dev->event_lock, flags);
6945 return;
6946 }
6947
6948 intel_crtc->unpin_work = NULL;
6b95a207
KH		 6949
6950 if (work->event) {
6951 e = work->event;
49b14a5c 6952 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df 6953
49b14a5c
MK		 6954 e->event.tv_sec = tvbl.tv_sec;
6955 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 6956
6b95a207
KH		 6957 list_add_tail(&e->base.link,
6958 &e->base.file_priv->event_list);
6959 wake_up_interruptible(&e->base.file_priv->event_wait);
6960 }
6961
0af7e4df
MK		 6962 drm_vblank_put(dev, intel_crtc->pipe);
6963
6b95a207
KH		 6964 spin_unlock_irqrestore(&dev->event_lock, flags);
6965
05394f39 6966 obj = work->old_fb_obj;
d9e86c0e 6967
e59f2bac 6968 atomic_clear_mask(1 << intel_crtc->plane,
05394f39 6969 &obj->pending_flip.counter);
d9e86c0e 6970
5bb61643 6971 wake_up(&dev_priv->pending_flip_queue);
6b95a207 6972 schedule_work(&work->work);
e5510fac
JB		 6973
6974 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6975}
6976
1afe3e9d
JB		 6977void intel_finish_page_flip(struct drm_device *dev, int pipe)
6978{
6979 drm_i915_private_t *dev_priv = dev->dev_private;
6980 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6981
49b14a5c 6982 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6983}
6984
6985void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6986{
6987 drm_i915_private_t *dev_priv = dev->dev_private;
6988 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6989
49b14a5c 6990 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6991}
6992
6b95a207
KH		 6993void intel_prepare_page_flip(struct drm_device *dev, int plane)
6994{
6995 drm_i915_private_t *dev_priv = dev->dev_private;
6996 struct intel_crtc *intel_crtc =
6997 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6998 unsigned long flags;
6999
7000 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 7001 if (intel_crtc->unpin_work) {
4e5359cd
SF		 7002 if ((++intel_crtc->unpin_work->pending) > 1)
7003 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 7004 } else {
7005 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
7006 }
6b95a207
KH		 7007 spin_unlock_irqrestore(&dev->event_lock, flags);
7008}
7009
8c9f3aaf
JB		 7010static int intel_gen2_queue_flip(struct drm_device *dev,
7011 struct drm_crtc *crtc,
7012 struct drm_framebuffer *fb,
7013 struct drm_i915_gem_object *obj)
7014{
7015 struct drm_i915_private *dev_priv = dev->dev_private;
7016 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7017 u32 flip_mask;
6d90c952 7018 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7019 int ret;
7020
6d90c952 7021 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7022 if (ret)
83d4092b 7023 goto err;
8c9f3aaf 7024
6d90c952 7025 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7026 if (ret)
83d4092b 7027 goto err_unpin;
8c9f3aaf
JB		 7028
7029 /* Can't queue multiple flips, so wait for the previous
7030 * one to finish before executing the next.
7031 */
7032 if (intel_crtc->plane)
7033 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7034 else
7035 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7036 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7037 intel_ring_emit(ring, MI_NOOP);
7038 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7039 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7040 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7041 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7042 intel_ring_emit(ring, 0); /* aux display base address, unused */
7043 intel_ring_advance(ring);
83d4092b
CW		 7044 return 0;
7045
7046err_unpin:
7047 intel_unpin_fb_obj(obj);
7048err:
8c9f3aaf
JB		 7049 return ret;
7050}
7051
7052static int intel_gen3_queue_flip(struct drm_device *dev,
7053 struct drm_crtc *crtc,
7054 struct drm_framebuffer *fb,
7055 struct drm_i915_gem_object *obj)
7056{
7057 struct drm_i915_private *dev_priv = dev->dev_private;
7058 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7059 u32 flip_mask;
6d90c952 7060 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7061 int ret;
7062
6d90c952 7063 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7064 if (ret)
83d4092b 7065 goto err;
8c9f3aaf 7066
6d90c952 7067 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7068 if (ret)
83d4092b 7069 goto err_unpin;
8c9f3aaf
JB		 7070
7071 if (intel_crtc->plane)
7072 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7073 else
7074 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7075 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7076 intel_ring_emit(ring, MI_NOOP);
7077 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7078 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7079 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7080 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7081 intel_ring_emit(ring, MI_NOOP);
7082
7083 intel_ring_advance(ring);
83d4092b
CW		 7084 return 0;
7085
7086err_unpin:
7087 intel_unpin_fb_obj(obj);
7088err:
8c9f3aaf
JB		 7089 return ret;
7090}
7091
7092static int intel_gen4_queue_flip(struct drm_device *dev,
7093 struct drm_crtc *crtc,
7094 struct drm_framebuffer *fb,
7095 struct drm_i915_gem_object *obj)
7096{
7097 struct drm_i915_private *dev_priv = dev->dev_private;
7098 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7099 uint32_t pf, pipesrc;
6d90c952 7100 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7101 int ret;
7102
6d90c952 7103 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7104 if (ret)
83d4092b 7105 goto err;
8c9f3aaf 7106
6d90c952 7107 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7108 if (ret)
83d4092b 7109 goto err_unpin;
8c9f3aaf
JB		 7110
7111 /* i965+ uses the linear or tiled offsets from the
7112 * Display Registers (which do not change across a page-flip)
7113 * so we need only reprogram the base address.
7114 */
6d90c952
DV		 7115 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7116 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7117 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7118 intel_ring_emit(ring,
7119 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7120 obj->tiling_mode);
8c9f3aaf
JB		 7121
7122 /* XXX Enabling the panel-fitter across page-flip is so far
7123 * untested on non-native modes, so ignore it for now.
7124 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7125 */
7126 pf = 0;
7127 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 7128 intel_ring_emit(ring, pf | pipesrc);
7129 intel_ring_advance(ring);
83d4092b
CW		 7130 return 0;
7131
7132err_unpin:
7133 intel_unpin_fb_obj(obj);
7134err:
8c9f3aaf
JB		 7135 return ret;
7136}
7137
7138static int intel_gen6_queue_flip(struct drm_device *dev,
7139 struct drm_crtc *crtc,
7140 struct drm_framebuffer *fb,
7141 struct drm_i915_gem_object *obj)
7142{
7143 struct drm_i915_private *dev_priv = dev->dev_private;
7144 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7145 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7146 uint32_t pf, pipesrc;
7147 int ret;
7148
6d90c952 7149 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7150 if (ret)
83d4092b 7151 goto err;
8c9f3aaf 7152
6d90c952 7153 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7154 if (ret)
83d4092b 7155 goto err_unpin;
8c9f3aaf 7156
6d90c952
DV		 7157 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7158 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7159 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7160 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7161
dc257cf1
DV		 7162 /* Contrary to the suggestions in the documentation,
7163 * "Enable Panel Fitter" does not seem to be required when page
7164 * flipping with a non-native mode, and worse causes a normal
7165 * modeset to fail.
7166 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7167 */
7168 pf = 0;
8c9f3aaf 7169 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 7170 intel_ring_emit(ring, pf | pipesrc);
7171 intel_ring_advance(ring);
83d4092b
CW		 7172 return 0;
7173
7174err_unpin:
7175 intel_unpin_fb_obj(obj);
7176err:
8c9f3aaf
JB		 7177 return ret;
7178}
7179
7c9017e5
JB		 7180/*
7181 * On gen7 we currently use the blit ring because (in early silicon at least)
7182 * the render ring doesn't give us interrpts for page flip completion, which
7183 * means clients will hang after the first flip is queued. Fortunately the
7184 * blit ring generates interrupts properly, so use it instead.
7185 */
7186static int intel_gen7_queue_flip(struct drm_device *dev,
7187 struct drm_crtc *crtc,
7188 struct drm_framebuffer *fb,
7189 struct drm_i915_gem_object *obj)
7190{
7191 struct drm_i915_private *dev_priv = dev->dev_private;
7192 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7193 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7194 uint32_t plane_bit = 0;
7c9017e5
JB		 7195 int ret;
7196
7197 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7198 if (ret)
83d4092b 7199 goto err;
7c9017e5 7200
cb05d8de
DV		 7201 switch(intel_crtc->plane) {
7202 case PLANE_A:
7203 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7204 break;
7205 case PLANE_B:
7206 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7207 break;
7208 case PLANE_C:
7209 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7210 break;
7211 default:
7212 WARN_ONCE(1, "unknown plane in flip command\n");
7213 ret = -ENODEV;
ab3951eb 7214 goto err_unpin;
cb05d8de
DV		 7215 }
7216
7c9017e5
JB		 7217 ret = intel_ring_begin(ring, 4);
7218 if (ret)
83d4092b 7219 goto err_unpin;
7c9017e5 7220
cb05d8de 7221 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7222 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7223 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5
JB		 7224 intel_ring_emit(ring, (MI_NOOP));
7225 intel_ring_advance(ring);
83d4092b
CW		 7226 return 0;
7227
7228err_unpin:
7229 intel_unpin_fb_obj(obj);
7230err:
7c9017e5
JB		 7231 return ret;
7232}
7233
8c9f3aaf
JB		 7234static int intel_default_queue_flip(struct drm_device *dev,
7235 struct drm_crtc *crtc,
7236 struct drm_framebuffer *fb,
7237 struct drm_i915_gem_object *obj)
7238{
7239 return -ENODEV;
7240}
7241
6b95a207
KH		 7242static int intel_crtc_page_flip(struct drm_crtc *crtc,
7243 struct drm_framebuffer *fb,
7244 struct drm_pending_vblank_event *event)
7245{
7246 struct drm_device *dev = crtc->dev;
7247 struct drm_i915_private *dev_priv = dev->dev_private;
7248 struct intel_framebuffer *intel_fb;
05394f39 7249 struct drm_i915_gem_object *obj;
6b95a207
KH		 7250 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7251 struct intel_unpin_work *work;
8c9f3aaf 7252 unsigned long flags;
52e68630 7253 int ret;
6b95a207 7254
e6a595d2
VS		 7255 /* Can't change pixel format via MI display flips. */
7256 if (fb->pixel_format != crtc->fb->pixel_format)
7257 return -EINVAL;
7258
7259 /*
7260 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7261 * Note that pitch changes could also affect these register.
7262 */
7263 if (INTEL_INFO(dev)->gen > 3 &&
7264 (fb->offsets[0] != crtc->fb->offsets[0] ||
7265 fb->pitches[0] != crtc->fb->pitches[0]))
7266 return -EINVAL;
7267
6b95a207
KH		 7268 work = kzalloc(sizeof *work, GFP_KERNEL);
7269 if (work == NULL)
7270 return -ENOMEM;
7271
6b95a207
KH		 7272 work->event = event;
7273 work->dev = crtc->dev;
7274 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 7275 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 7276 INIT_WORK(&work->work, intel_unpin_work_fn);
7277
7317c75e
JB		 7278 ret = drm_vblank_get(dev, intel_crtc->pipe);
7279 if (ret)
7280 goto free_work;
7281
6b95a207
KH		 7282 /* We borrow the event spin lock for protecting unpin_work */
7283 spin_lock_irqsave(&dev->event_lock, flags);
7284 if (intel_crtc->unpin_work) {
7285 spin_unlock_irqrestore(&dev->event_lock, flags);
7286 kfree(work);
7317c75e 7287 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7288
7289 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7290 return -EBUSY;
7291 }
7292 intel_crtc->unpin_work = work;
7293 spin_unlock_irqrestore(&dev->event_lock, flags);
7294
7295 intel_fb = to_intel_framebuffer(fb);
7296 obj = intel_fb->obj;
7297
79158103
CW		 7298 ret = i915_mutex_lock_interruptible(dev);
7299 if (ret)
7300 goto cleanup;
6b95a207 7301
75dfca80 7302 /* Reference the objects for the scheduled work. */
05394f39
CW		 7303 drm_gem_object_reference(&work->old_fb_obj->base);
7304 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7305
7306 crtc->fb = fb;
96b099fd 7307
e1f99ce6 7308 work->pending_flip_obj = obj;
e1f99ce6 7309
4e5359cd
SF		 7310 work->enable_stall_check = true;
7311
e1f99ce6
CW		 7312 /* Block clients from rendering to the new back buffer until
7313 * the flip occurs and the object is no longer visible.
7314 */
05394f39 7315 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 7316
8c9f3aaf
JB		 7317 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7318 if (ret)
7319 goto cleanup_pending;
6b95a207 7320
7782de3b 7321 intel_disable_fbc(dev);
f047e395 7322 intel_mark_fb_busy(obj);
6b95a207
KH		 7323 mutex_unlock(&dev->struct_mutex);
7324
e5510fac
JB		 7325 trace_i915_flip_request(intel_crtc->plane, obj);
7326
6b95a207 7327 return 0;
96b099fd 7328
8c9f3aaf
JB		 7329cleanup_pending:
7330 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 7331 drm_gem_object_unreference(&work->old_fb_obj->base);
7332 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7333 mutex_unlock(&dev->struct_mutex);
7334
79158103 7335cleanup:
96b099fd
CW		 7336 spin_lock_irqsave(&dev->event_lock, flags);
7337 intel_crtc->unpin_work = NULL;
7338 spin_unlock_irqrestore(&dev->event_lock, flags);
7339
7317c75e
JB		 7340 drm_vblank_put(dev, intel_crtc->pipe);
7341free_work:
96b099fd
CW		 7342 kfree(work);
7343
7344 return ret;
6b95a207
KH		 7345}
7346
f6e5b160 7347static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7348 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7349 .load_lut = intel_crtc_load_lut,
976f8a20 7350 .disable = intel_crtc_noop,
f6e5b160
CW		 7351};
7352
6ed0f796 7353bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7354{
6ed0f796
DV		 7355 struct intel_encoder *other_encoder;
7356 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7357
6ed0f796
DV		 7358 if (WARN_ON(!crtc))
7359 return false;
7360
7361 list_for_each_entry(other_encoder,
7362 &crtc->dev->mode_config.encoder_list,
7363 base.head) {
7364
7365 if (&other_encoder->new_crtc->base != crtc ||
7366 encoder == other_encoder)
7367 continue;
7368 else
7369 return true;
f47166d2
CW		 7370 }
7371
6ed0f796
DV		 7372 return false;
7373}
47f1c6c9 7374
50f56119
DV		 7375static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7376 struct drm_crtc *crtc)
7377{
7378 struct drm_device *dev;
7379 struct drm_crtc *tmp;
7380 int crtc_mask = 1;
47f1c6c9 7381
50f56119 7382 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7383
50f56119 7384 dev = crtc->dev;
47f1c6c9 7385
50f56119
DV		 7386 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7387 if (tmp == crtc)
7388 break;
7389 crtc_mask <<= 1;
7390 }
47f1c6c9 7391
50f56119
DV		 7392 if (encoder->possible_crtcs & crtc_mask)
7393 return true;
7394 return false;
47f1c6c9 7395}
79e53945 7396
9a935856
DV		 7397/**
7398 * intel_modeset_update_staged_output_state
7399 *
7400 * Updates the staged output configuration state, e.g. after we've read out the
7401 * current hw state.
7402 */
7403static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7404{
9a935856
DV		 7405 struct intel_encoder *encoder;
7406 struct intel_connector *connector;
f6e5b160 7407
9a935856
DV		 7408 list_for_each_entry(connector, &dev->mode_config.connector_list,
7409 base.head) {
7410 connector->new_encoder =
7411 to_intel_encoder(connector->base.encoder);
7412 }
f6e5b160 7413
9a935856
DV		 7414 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7415 base.head) {
7416 encoder->new_crtc =
7417 to_intel_crtc(encoder->base.crtc);
7418 }
f6e5b160
CW		 7419}
7420
9a935856
DV		 7421/**
7422 * intel_modeset_commit_output_state
7423 *
7424 * This function copies the stage display pipe configuration to the real one.
7425 */
7426static void intel_modeset_commit_output_state(struct drm_device *dev)
7427{
7428 struct intel_encoder *encoder;
7429 struct intel_connector *connector;
f6e5b160 7430
9a935856
DV		 7431 list_for_each_entry(connector, &dev->mode_config.connector_list,
7432 base.head) {
7433 connector->base.encoder = &connector->new_encoder->base;
7434 }
f6e5b160 7435
9a935856
DV		 7436 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7437 base.head) {
7438 encoder->base.crtc = &encoder->new_crtc->base;
7439 }
7440}
7441
7758a113
DV		 7442static struct drm_display_mode *
7443intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7444 struct drm_display_mode *mode)
ee7b9f93 7445{
7758a113
DV		 7446 struct drm_device *dev = crtc->dev;
7447 struct drm_display_mode *adjusted_mode;
7448 struct drm_encoder_helper_funcs *encoder_funcs;
7449 struct intel_encoder *encoder;
ee7b9f93 7450
7758a113
DV		 7451 adjusted_mode = drm_mode_duplicate(dev, mode);
7452 if (!adjusted_mode)
7453 return ERR_PTR(-ENOMEM);
7454
7455 /* Pass our mode to the connectors and the CRTC to give them a chance to
7456 * adjust it according to limitations or connector properties, and also
7457 * a chance to reject the mode entirely.
7458 */
7459 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7460 base.head) {
7461
7462 if (&encoder->new_crtc->base != crtc)
7463 continue;
7464 encoder_funcs = encoder->base.helper_private;
7465 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7466 adjusted_mode))) {
7467 DRM_DEBUG_KMS("Encoder fixup failed\n");
7468 goto fail;
7469 }
ee7b9f93
JB		 7470 }
7471
7758a113
DV		 7472 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7473 DRM_DEBUG_KMS("CRTC fixup failed\n");
7474 goto fail;
ee7b9f93 7475 }
7758a113
DV		 7476 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7477
7478 return adjusted_mode;
7479fail:
7480 drm_mode_destroy(dev, adjusted_mode);
7481 return ERR_PTR(-EINVAL);
ee7b9f93
JB		 7482}
7483
e2e1ed41
DV		 7484/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7485 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7486static void
7487intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7488 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7489{
7490 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7491 struct drm_device *dev = crtc->dev;
7492 struct intel_encoder *encoder;
7493 struct intel_connector *connector;
7494 struct drm_crtc *tmp_crtc;
79e53945 7495
e2e1ed41 7496 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7497
e2e1ed41
DV		 7498 /* Check which crtcs have changed outputs connected to them, these need
7499 * to be part of the prepare_pipes mask. We don't (yet) support global
7500 * modeset across multiple crtcs, so modeset_pipes will only have one
7501 * bit set at most. */
7502 list_for_each_entry(connector, &dev->mode_config.connector_list,
7503 base.head) {
7504 if (connector->base.encoder == &connector->new_encoder->base)
7505 continue;
79e53945 7506
e2e1ed41
DV		 7507 if (connector->base.encoder) {
7508 tmp_crtc = connector->base.encoder->crtc;
7509
7510 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7511 }
7512
7513 if (connector->new_encoder)
7514 *prepare_pipes |=
7515 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7516 }
7517
e2e1ed41
DV		 7518 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7519 base.head) {
7520 if (encoder->base.crtc == &encoder->new_crtc->base)
7521 continue;
7522
7523 if (encoder->base.crtc) {
7524 tmp_crtc = encoder->base.crtc;
7525
7526 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7527 }
7528
7529 if (encoder->new_crtc)
7530 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7531 }
7532
e2e1ed41
DV		 7533 /* Check for any pipes that will be fully disabled ... */
7534 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7535 base.head) {
7536 bool used = false;
22fd0fab 7537
e2e1ed41
DV		 7538 /* Don't try to disable disabled crtcs. */
7539 if (!intel_crtc->base.enabled)
7540 continue;
7e7d76c3 7541
e2e1ed41
DV		 7542 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7543 base.head) {
7544 if (encoder->new_crtc == intel_crtc)
7545 used = true;
7546 }
7547
7548 if (!used)
7549 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7550 }
7551
e2e1ed41
DV		 7552
7553 /* set_mode is also used to update properties on life display pipes. */
7554 intel_crtc = to_intel_crtc(crtc);
7555 if (crtc->enabled)
7556 *prepare_pipes |= 1 << intel_crtc->pipe;
7557
7558 /* We only support modeset on one single crtc, hence we need to do that
7559 * only for the passed in crtc iff we change anything else than just
7560 * disable crtcs.
7561 *
7562 * This is actually not true, to be fully compatible with the old crtc
7563 * helper we automatically disable _any_ output (i.e. doesn't need to be
7564 * connected to the crtc we're modesetting on) if it's disconnected.
7565 * Which is a rather nutty api (since changed the output configuration
7566 * without userspace's explicit request can lead to confusion), but
7567 * alas. Hence we currently need to modeset on all pipes we prepare. */
7568 if (*prepare_pipes)
7569 *modeset_pipes = *prepare_pipes;
7570
7571 /* ... and mask these out. */
7572 *modeset_pipes &= ~(*disable_pipes);
7573 *prepare_pipes &= ~(*disable_pipes);
7574}
7575
ea9d758d
DV		 7576static bool intel_crtc_in_use(struct drm_crtc *crtc)
7577{
7578 struct drm_encoder *encoder;
7579 struct drm_device *dev = crtc->dev;
7580
7581 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7582 if (encoder->crtc == crtc)
7583 return true;
7584
7585 return false;
7586}
7587
7588static void
7589intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7590{
7591 struct intel_encoder *intel_encoder;
7592 struct intel_crtc *intel_crtc;
7593 struct drm_connector *connector;
7594
7595 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7596 base.head) {
7597 if (!intel_encoder->base.crtc)
7598 continue;
7599
7600 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7601
7602 if (prepare_pipes & (1 << intel_crtc->pipe))
7603 intel_encoder->connectors_active = false;
7604 }
7605
7606 intel_modeset_commit_output_state(dev);
7607
7608 /* Update computed state. */
7609 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7610 base.head) {
7611 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7612 }
7613
7614 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7615 if (!connector->encoder || !connector->encoder->crtc)
7616 continue;
7617
7618 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7619
7620 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7621 struct drm_property *dpms_property =
7622 dev->mode_config.dpms_property;
7623
ea9d758d 7624 connector->dpms = DRM_MODE_DPMS_ON;
68d34720
DV		 7625 drm_connector_property_set_value(connector,
7626 dpms_property,
7627 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7628
7629 intel_encoder = to_intel_encoder(connector->encoder);
7630 intel_encoder->connectors_active = true;
7631 }
7632 }
7633
7634}
7635
25c5b266
DV		 7636#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7637 list_for_each_entry((intel_crtc), \
7638 &(dev)->mode_config.crtc_list, \
7639 base.head) \
7640 if (mask & (1 <<(intel_crtc)->pipe)) \
7641
b980514c 7642void
8af6cf88
DV		 7643intel_modeset_check_state(struct drm_device *dev)
7644{
7645 struct intel_crtc *crtc;
7646 struct intel_encoder *encoder;
7647 struct intel_connector *connector;
7648
7649 list_for_each_entry(connector, &dev->mode_config.connector_list,
7650 base.head) {
7651 /* This also checks the encoder/connector hw state with the
7652 * ->get_hw_state callbacks. */
7653 intel_connector_check_state(connector);
7654
7655 WARN(&connector->new_encoder->base != connector->base.encoder,
7656 "connector's staged encoder doesn't match current encoder\n");
7657 }
7658
7659 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7660 base.head) {
7661 bool enabled = false;
7662 bool active = false;
7663 enum pipe pipe, tracked_pipe;
7664
7665 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7666 encoder->base.base.id,
7667 drm_get_encoder_name(&encoder->base));
7668
7669 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7670 "encoder's stage crtc doesn't match current crtc\n");
7671 WARN(encoder->connectors_active && !encoder->base.crtc,
7672 "encoder's active_connectors set, but no crtc\n");
7673
7674 list_for_each_entry(connector, &dev->mode_config.connector_list,
7675 base.head) {
7676 if (connector->base.encoder != &encoder->base)
7677 continue;
7678 enabled = true;
7679 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7680 active = true;
7681 }
7682 WARN(!!encoder->base.crtc != enabled,
7683 "encoder's enabled state mismatch "
7684 "(expected %i, found %i)\n",
7685 !!encoder->base.crtc, enabled);
7686 WARN(active && !encoder->base.crtc,
7687 "active encoder with no crtc\n");
7688
7689 WARN(encoder->connectors_active != active,
7690 "encoder's computed active state doesn't match tracked active state "
7691 "(expected %i, found %i)\n", active, encoder->connectors_active);
7692
7693 active = encoder->get_hw_state(encoder, &pipe);
7694 WARN(active != encoder->connectors_active,
7695 "encoder's hw state doesn't match sw tracking "
7696 "(expected %i, found %i)\n",
7697 encoder->connectors_active, active);
7698
7699 if (!encoder->base.crtc)
7700 continue;
7701
7702 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7703 WARN(active && pipe != tracked_pipe,
7704 "active encoder's pipe doesn't match"
7705 "(expected %i, found %i)\n",
7706 tracked_pipe, pipe);
7707
7708 }
7709
7710 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7711 base.head) {
7712 bool enabled = false;
7713 bool active = false;
7714
7715 DRM_DEBUG_KMS("[CRTC:%d]\n",
7716 crtc->base.base.id);
7717
7718 WARN(crtc->active && !crtc->base.enabled,
7719 "active crtc, but not enabled in sw tracking\n");
7720
7721 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7722 base.head) {
7723 if (encoder->base.crtc != &crtc->base)
7724 continue;
7725 enabled = true;
7726 if (encoder->connectors_active)
7727 active = true;
7728 }
7729 WARN(active != crtc->active,
7730 "crtc's computed active state doesn't match tracked active state "
7731 "(expected %i, found %i)\n", active, crtc->active);
7732 WARN(enabled != crtc->base.enabled,
7733 "crtc's computed enabled state doesn't match tracked enabled state "
7734 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7735
7736 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7737 }
7738}
7739
a6778b3c
DV		 7740bool intel_set_mode(struct drm_crtc *crtc,
7741 struct drm_display_mode *mode,
94352cf9 7742 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7743{
7744 struct drm_device *dev = crtc->dev;
dbf2b54e 7745 drm_i915_private_t *dev_priv = dev->dev_private;
a6778b3c 7746 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
25c5b266
DV		 7747 struct intel_crtc *intel_crtc;
7748 unsigned disable_pipes, prepare_pipes, modeset_pipes;
a6778b3c
DV		 7749 bool ret = true;
7750
e2e1ed41 7751 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 7752 &prepare_pipes, &disable_pipes);
7753
7754 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7755 modeset_pipes, prepare_pipes, disable_pipes);
e2e1ed41 7756
976f8a20
DV		 7757 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7758 intel_crtc_disable(&intel_crtc->base);
87f1faa6 7759
a6778b3c
DV		 7760 saved_hwmode = crtc->hwmode;
7761 saved_mode = crtc->mode;
a6778b3c 7762
25c5b266
DV		 7763 /* Hack: Because we don't (yet) support global modeset on multiple
7764 * crtcs, we don't keep track of the new mode for more than one crtc.
7765 * Hence simply check whether any bit is set in modeset_pipes in all the
7766 * pieces of code that are not yet converted to deal with mutliple crtcs
7767 * changing their mode at the same time. */
7768 adjusted_mode = NULL;
7769 if (modeset_pipes) {
7770 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7771 if (IS_ERR(adjusted_mode)) {
7772 return false;
7773 }
25c5b266 7774 }
a6778b3c 7775
ea9d758d
DV		 7776 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7777 if (intel_crtc->base.enabled)
7778 dev_priv->display.crtc_disable(&intel_crtc->base);
7779 }
a6778b3c 7780
6c4c86f5
DV		 7781 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7782 * to set it here already despite that we pass it down the callchain.
7783 */
7784 if (modeset_pipes)
25c5b266 7785 crtc->mode = *mode;
7758a113 7786
ea9d758d
DV		 7787 /* Only after disabling all output pipelines that will be changed can we
7788 * update the the output configuration. */
7789 intel_modeset_update_state(dev, prepare_pipes);
7790
47fab737
DV		 7791 if (dev_priv->display.modeset_global_resources)
7792 dev_priv->display.modeset_global_resources(dev);
7793
a6778b3c
DV		 7794 /* Set up the DPLL and any encoders state that needs to adjust or depend
7795 * on the DPLL.
7796 */
25c5b266
DV		 7797 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7798 ret = !intel_crtc_mode_set(&intel_crtc->base,
7799 mode, adjusted_mode,
7800 x, y, fb);
7801 if (!ret)
7802 goto done;
a6778b3c
DV		 7803 }
7804
7805 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 7806 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7807 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 7808
25c5b266
DV		 7809 if (modeset_pipes) {
7810 /* Store real post-adjustment hardware mode. */
7811 crtc->hwmode = *adjusted_mode;
a6778b3c 7812
25c5b266
DV		 7813 /* Calculate and store various constants which
7814 * are later needed by vblank and swap-completion
7815 * timestamping. They are derived from true hwmode.
7816 */
7817 drm_calc_timestamping_constants(crtc);
7818 }
a6778b3c
DV		 7819
7820 /* FIXME: add subpixel order */
7821done:
7822 drm_mode_destroy(dev, adjusted_mode);
25c5b266 7823 if (!ret && crtc->enabled) {
a6778b3c
DV		 7824 crtc->hwmode = saved_hwmode;
7825 crtc->mode = saved_mode;
8af6cf88
DV		 7826 } else {
7827 intel_modeset_check_state(dev);
a6778b3c
DV		 7828 }
7829
7830 return ret;
7831}
7832
25c5b266
DV		 7833#undef for_each_intel_crtc_masked
7834
d9e55608
DV		 7835static void intel_set_config_free(struct intel_set_config *config)
7836{
7837 if (!config)
7838 return;
7839
1aa4b628
DV		 7840 kfree(config->save_connector_encoders);
7841 kfree(config->save_encoder_crtcs);
d9e55608
DV		 7842 kfree(config);
7843}
7844
85f9eb71
DV		 7845static int intel_set_config_save_state(struct drm_device *dev,
7846 struct intel_set_config *config)
7847{
85f9eb71
DV		 7848 struct drm_encoder *encoder;
7849 struct drm_connector *connector;
7850 int count;
7851
1aa4b628
DV		 7852 config->save_encoder_crtcs =
7853 kcalloc(dev->mode_config.num_encoder,
7854 sizeof(struct drm_crtc *), GFP_KERNEL);
7855 if (!config->save_encoder_crtcs)
85f9eb71
DV		 7856 return -ENOMEM;
7857
1aa4b628
DV		 7858 config->save_connector_encoders =
7859 kcalloc(dev->mode_config.num_connector,
7860 sizeof(struct drm_encoder *), GFP_KERNEL);
7861 if (!config->save_connector_encoders)
85f9eb71
DV		 7862 return -ENOMEM;
7863
7864 /* Copy data. Note that driver private data is not affected.
7865 * Should anything bad happen only the expected state is
7866 * restored, not the drivers personal bookkeeping.
7867 */
85f9eb71
DV		 7868 count = 0;
7869 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 7870 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 7871 }
7872
7873 count = 0;
7874 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 7875 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 7876 }
7877
7878 return 0;
7879}
7880
7881static void intel_set_config_restore_state(struct drm_device *dev,
7882 struct intel_set_config *config)
7883{
9a935856
DV		 7884 struct intel_encoder *encoder;
7885 struct intel_connector *connector;
85f9eb71
DV		 7886 int count;
7887
85f9eb71 7888 count = 0;
9a935856
DV		 7889 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7890 encoder->new_crtc =
7891 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 7892 }
7893
7894 count = 0;
9a935856
DV		 7895 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7896 connector->new_encoder =
7897 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 7898 }
7899}
7900
5e2b584e
DV		 7901static void
7902intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7903 struct intel_set_config *config)
7904{
7905
7906 /* We should be able to check here if the fb has the same properties
7907 * and then just flip_or_move it */
7908 if (set->crtc->fb != set->fb) {
7909 /* If we have no fb then treat it as a full mode set */
7910 if (set->crtc->fb == NULL) {
7911 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7912 config->mode_changed = true;
7913 } else if (set->fb == NULL) {
7914 config->mode_changed = true;
7915 } else if (set->fb->depth != set->crtc->fb->depth) {
7916 config->mode_changed = true;
7917 } else if (set->fb->bits_per_pixel !=
7918 set->crtc->fb->bits_per_pixel) {
7919 config->mode_changed = true;
7920 } else
7921 config->fb_changed = true;
7922 }
7923
835c5873 7924 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 7925 config->fb_changed = true;
7926
7927 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7928 DRM_DEBUG_KMS("modes are different, full mode set\n");
7929 drm_mode_debug_printmodeline(&set->crtc->mode);
7930 drm_mode_debug_printmodeline(set->mode);
7931 config->mode_changed = true;
7932 }
7933}
7934
2e431051 7935static int
9a935856
DV		 7936intel_modeset_stage_output_state(struct drm_device *dev,
7937 struct drm_mode_set *set,
7938 struct intel_set_config *config)
50f56119 7939{
85f9eb71 7940 struct drm_crtc *new_crtc;
9a935856
DV		 7941 struct intel_connector *connector;
7942 struct intel_encoder *encoder;
2e431051 7943 int count, ro;
50f56119 7944
9a935856
DV		 7945 /* The upper layers ensure that we either disabl a crtc or have a list
7946 * of connectors. For paranoia, double-check this. */
7947 WARN_ON(!set->fb && (set->num_connectors != 0));
7948 WARN_ON(set->fb && (set->num_connectors == 0));
7949
50f56119 7950 count = 0;
9a935856
DV		 7951 list_for_each_entry(connector, &dev->mode_config.connector_list,
7952 base.head) {
7953 /* Otherwise traverse passed in connector list and get encoders
7954 * for them. */
50f56119 7955 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 7956 if (set->connectors[ro] == &connector->base) {
7957 connector->new_encoder = connector->encoder;
50f56119
DV		 7958 break;
7959 }
7960 }
7961
9a935856
DV		 7962 /* If we disable the crtc, disable all its connectors. Also, if
7963 * the connector is on the changing crtc but not on the new
7964 * connector list, disable it. */
7965 if ((!set->fb || ro == set->num_connectors) &&
7966 connector->base.encoder &&
7967 connector->base.encoder->crtc == set->crtc) {
7968 connector->new_encoder = NULL;
7969
7970 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7971 connector->base.base.id,
7972 drm_get_connector_name(&connector->base));
7973 }
7974
7975
7976 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 7977 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 7978 config->mode_changed = true;
50f56119 7979 }
9a935856
DV		 7980
7981 /* Disable all disconnected encoders. */
7982 if (connector->base.status == connector_status_disconnected)
7983 connector->new_encoder = NULL;
50f56119 7984 }
9a935856 7985 /* connector->new_encoder is now updated for all connectors. */
50f56119 7986
9a935856 7987 /* Update crtc of enabled connectors. */
50f56119 7988 count = 0;
9a935856
DV		 7989 list_for_each_entry(connector, &dev->mode_config.connector_list,
7990 base.head) {
7991 if (!connector->new_encoder)
50f56119
DV		 7992 continue;
7993
9a935856 7994 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 7995
7996 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 7997 if (set->connectors[ro] == &connector->base)
50f56119
DV		 7998 new_crtc = set->crtc;
7999 }
8000
8001 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8002 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8003 new_crtc)) {
5e2b584e 8004 return -EINVAL;
50f56119 8005 }
9a935856
DV		 8006 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8007
8008 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8009 connector->base.base.id,
8010 drm_get_connector_name(&connector->base),
8011 new_crtc->base.id);
8012 }
8013
8014 /* Check for any encoders that needs to be disabled. */
8015 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8016 base.head) {
8017 list_for_each_entry(connector,
8018 &dev->mode_config.connector_list,
8019 base.head) {
8020 if (connector->new_encoder == encoder) {
8021 WARN_ON(!connector->new_encoder->new_crtc);
8022
8023 goto next_encoder;
8024 }
8025 }
8026 encoder->new_crtc = NULL;
8027next_encoder:
8028 /* Only now check for crtc changes so we don't miss encoders
8029 * that will be disabled. */
8030 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8031 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8032 config->mode_changed = true;
50f56119
DV		 8033 }
8034 }
9a935856 8035 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8036
2e431051
DV		 8037 return 0;
8038}
8039
8040static int intel_crtc_set_config(struct drm_mode_set *set)
8041{
8042 struct drm_device *dev;
2e431051
DV		 8043 struct drm_mode_set save_set;
8044 struct intel_set_config *config;
8045 int ret;
2e431051 8046
8d3e375e
DV		 8047 BUG_ON(!set);
8048 BUG_ON(!set->crtc);
8049 BUG_ON(!set->crtc->helper_private);
2e431051
DV		 8050
8051 if (!set->mode)
8052 set->fb = NULL;
8053
431e50f7
DV		 8054 /* The fb helper likes to play gross jokes with ->mode_set_config.
8055 * Unfortunately the crtc helper doesn't do much at all for this case,
8056 * so we have to cope with this madness until the fb helper is fixed up. */
8057 if (set->fb && set->num_connectors == 0)
8058 return 0;
8059
2e431051
DV		 8060 if (set->fb) {
8061 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8062 set->crtc->base.id, set->fb->base.id,
8063 (int)set->num_connectors, set->x, set->y);
8064 } else {
8065 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8066 }
8067
8068 dev = set->crtc->dev;
8069
8070 ret = -ENOMEM;
8071 config = kzalloc(sizeof(*config), GFP_KERNEL);
8072 if (!config)
8073 goto out_config;
8074
8075 ret = intel_set_config_save_state(dev, config);
8076 if (ret)
8077 goto out_config;
8078
8079 save_set.crtc = set->crtc;
8080 save_set.mode = &set->crtc->mode;
8081 save_set.x = set->crtc->x;
8082 save_set.y = set->crtc->y;
8083 save_set.fb = set->crtc->fb;
8084
8085 /* Compute whether we need a full modeset, only an fb base update or no
8086 * change at all. In the future we might also check whether only the
8087 * mode changed, e.g. for LVDS where we only change the panel fitter in
8088 * such cases. */
8089 intel_set_config_compute_mode_changes(set, config);
8090
9a935856 8091 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8092 if (ret)
8093 goto fail;
8094
5e2b584e 8095 if (config->mode_changed) {
87f1faa6 8096 if (set->mode) {
50f56119
DV		 8097 DRM_DEBUG_KMS("attempting to set mode from"
8098 " userspace\n");
8099 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 8100 }
8101
8102 if (!intel_set_mode(set->crtc, set->mode,
8103 set->x, set->y, set->fb)) {
8104 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
8105 set->crtc->base.id);
8106 ret = -EINVAL;
8107 goto fail;
8108 }
5e2b584e 8109 } else if (config->fb_changed) {
4f660f49 8110 ret = intel_pipe_set_base(set->crtc,
94352cf9 8111 set->x, set->y, set->fb);
50f56119
DV		 8112 }
8113
d9e55608
DV		 8114 intel_set_config_free(config);
8115
50f56119
DV		 8116 return 0;
8117
8118fail:
85f9eb71 8119 intel_set_config_restore_state(dev, config);
50f56119
DV		 8120
8121 /* Try to restore the config */
5e2b584e 8122 if (config->mode_changed &&
a6778b3c
DV		 8123 !intel_set_mode(save_set.crtc, save_set.mode,
8124 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8125 DRM_ERROR("failed to restore config after modeset failure\n");
8126
d9e55608
DV		 8127out_config:
8128 intel_set_config_free(config);
50f56119
DV		 8129 return ret;
8130}
8131
f6e5b160 8132static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8133 .cursor_set = intel_crtc_cursor_set,
8134 .cursor_move = intel_crtc_cursor_move,
8135 .gamma_set = intel_crtc_gamma_set,
50f56119 8136 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8137 .destroy = intel_crtc_destroy,
8138 .page_flip = intel_crtc_page_flip,
8139};
8140
79f689aa
PZ		 8141static void intel_cpu_pll_init(struct drm_device *dev)
8142{
8143 if (IS_HASWELL(dev))
8144 intel_ddi_pll_init(dev);
8145}
8146
ee7b9f93
JB		 8147static void intel_pch_pll_init(struct drm_device *dev)
8148{
8149 drm_i915_private_t *dev_priv = dev->dev_private;
8150 int i;
8151
8152 if (dev_priv->num_pch_pll == 0) {
8153 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8154 return;
8155 }
8156
8157 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8158 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8159 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8160 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8161 }
8162}
8163
b358d0a6 8164static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8165{
22fd0fab 8166 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8167 struct intel_crtc *intel_crtc;
8168 int i;
8169
8170 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8171 if (intel_crtc == NULL)
8172 return;
8173
8174 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8175
8176 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8177 for (i = 0; i < 256; i++) {
8178 intel_crtc->lut_r[i] = i;
8179 intel_crtc->lut_g[i] = i;
8180 intel_crtc->lut_b[i] = i;
8181 }
8182
80824003
JB		 8183 /* Swap pipes & planes for FBC on pre-965 */
8184 intel_crtc->pipe = pipe;
8185 intel_crtc->plane = pipe;
a5c961d1 8186 intel_crtc->cpu_transcoder = pipe;
e2e767ab 8187 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8188 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8189 intel_crtc->plane = !pipe;
80824003
JB		 8190 }
8191
22fd0fab
JB		 8192 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8193 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8194 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8195 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8196
5a354204 8197 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3 8198
79e53945 8199 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8200}
8201
08d7b3d1 8202int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8203 struct drm_file *file)
08d7b3d1 8204{
08d7b3d1 8205 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8206 struct drm_mode_object *drmmode_obj;
8207 struct intel_crtc *crtc;
08d7b3d1 8208
1cff8f6b
DV		 8209 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8210 return -ENODEV;
08d7b3d1 8211
c05422d5
DV		 8212 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8213 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8214
c05422d5 8215 if (!drmmode_obj) {
08d7b3d1
CW		 8216 DRM_ERROR("no such CRTC id\n");
8217 return -EINVAL;
8218 }
8219
c05422d5
DV		 8220 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8221 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8222
c05422d5 8223 return 0;
08d7b3d1
CW		 8224}
8225
66a9278e 8226static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8227{
66a9278e
DV		 8228 struct drm_device *dev = encoder->base.dev;
8229 struct intel_encoder *source_encoder;
79e53945 8230 int index_mask = 0;
79e53945
JB		 8231 int entry = 0;
8232
66a9278e
DV		 8233 list_for_each_entry(source_encoder,
8234 &dev->mode_config.encoder_list, base.head) {
8235
8236 if (encoder == source_encoder)
79e53945 8237 index_mask |= (1 << entry);
66a9278e
DV		 8238
8239 /* Intel hw has only one MUX where enocoders could be cloned. */
8240 if (encoder->cloneable && source_encoder->cloneable)
8241 index_mask |= (1 << entry);
8242
79e53945
JB		 8243 entry++;
8244 }
4ef69c7a 8245
79e53945
JB		 8246 return index_mask;
8247}
8248
4d302442
CW		 8249static bool has_edp_a(struct drm_device *dev)
8250{
8251 struct drm_i915_private *dev_priv = dev->dev_private;
8252
8253 if (!IS_MOBILE(dev))
8254 return false;
8255
8256 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8257 return false;
8258
8259 if (IS_GEN5(dev) &&
8260 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8261 return false;
8262
8263 return true;
8264}
8265
79e53945
JB		 8266static void intel_setup_outputs(struct drm_device *dev)
8267{
725e30ad 8268 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8269 struct intel_encoder *encoder;
cb0953d7 8270 bool dpd_is_edp = false;
f3cfcba6 8271 bool has_lvds;
79e53945 8272
f3cfcba6 8273 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8274 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8275 /* disable the panel fitter on everything but LVDS */
8276 I915_WRITE(PFIT_CONTROL, 0);
8277 }
79e53945 8278
bad720ff 8279 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8280 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 8281
4d302442 8282 if (has_edp_a(dev))
ab9d7c30 8283 intel_dp_init(dev, DP_A, PORT_A);
32f9d658 8284
cb0953d7 8285 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
ab9d7c30 8286 intel_dp_init(dev, PCH_DP_D, PORT_D);
cb0953d7
AJ		 8287 }
8288
8289 intel_crt_init(dev);
8290
0e72a5b5
ED		 8291 if (IS_HASWELL(dev)) {
8292 int found;
8293
8294 /* Haswell uses DDI functions to detect digital outputs */
8295 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8296 /* DDI A only supports eDP */
8297 if (found)
8298 intel_ddi_init(dev, PORT_A);
8299
8300 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8301 * register */
8302 found = I915_READ(SFUSE_STRAP);
8303
8304 if (found & SFUSE_STRAP_DDIB_DETECTED)
8305 intel_ddi_init(dev, PORT_B);
8306 if (found & SFUSE_STRAP_DDIC_DETECTED)
8307 intel_ddi_init(dev, PORT_C);
8308 if (found & SFUSE_STRAP_DDID_DETECTED)
8309 intel_ddi_init(dev, PORT_D);
8310 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7
AJ		 8311 int found;
8312
30ad48b7 8313 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 8314 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8315 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8316 if (!found)
08d644ad 8317 intel_hdmi_init(dev, HDMIB, PORT_B);
5eb08b69 8318 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8319 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8320 }
8321
8322 if (I915_READ(HDMIC) & PORT_DETECTED)
08d644ad 8323 intel_hdmi_init(dev, HDMIC, PORT_C);
30ad48b7 8324
b708a1d5 8325 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
08d644ad 8326 intel_hdmi_init(dev, HDMID, PORT_D);
30ad48b7 8327
5eb08b69 8328 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8329 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8330
cb0953d7 8331 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
ab9d7c30 8332 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d
JB		 8333 } else if (IS_VALLEYVIEW(dev)) {
8334 int found;
8335
19c03924
GB		 8336 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8337 if (I915_READ(DP_C) & DP_DETECTED)
8338 intel_dp_init(dev, DP_C, PORT_C);
8339
4a87d65d
JB		 8340 if (I915_READ(SDVOB) & PORT_DETECTED) {
8341 /* SDVOB multiplex with HDMIB */
8342 found = intel_sdvo_init(dev, SDVOB, true);
8343 if (!found)
08d644ad 8344 intel_hdmi_init(dev, SDVOB, PORT_B);
4a87d65d 8345 if (!found && (I915_READ(DP_B) & DP_DETECTED))
ab9d7c30 8346 intel_dp_init(dev, DP_B, PORT_B);
4a87d65d
JB		 8347 }
8348
8349 if (I915_READ(SDVOC) & PORT_DETECTED)
08d644ad 8350 intel_hdmi_init(dev, SDVOC, PORT_C);
5eb08b69 8351
103a196f 8352 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8353 bool found = false;
7d57382e 8354
725e30ad 8355 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 8356 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 8357 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 8358 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8359 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
08d644ad 8360 intel_hdmi_init(dev, SDVOB, PORT_B);
b01f2c3a 8361 }
27185ae1 8362
b01f2c3a
JB		 8363 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8364 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8365 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8366 }
725e30ad 8367 }
13520b05
KH		 8368
8369 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8370
b01f2c3a
JB		 8371 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8372 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 8373 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 8374 }
27185ae1
ML		 8375
8376 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8377
b01f2c3a
JB		 8378 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8379 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
08d644ad 8380 intel_hdmi_init(dev, SDVOC, PORT_C);
b01f2c3a
JB		 8381 }
8382 if (SUPPORTS_INTEGRATED_DP(dev)) {
8383 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8384 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8385 }
725e30ad 8386 }
27185ae1 8387
b01f2c3a
JB		 8388 if (SUPPORTS_INTEGRATED_DP(dev) &&
8389 (I915_READ(DP_D) & DP_DETECTED)) {
8390 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8391 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8392 }
bad720ff 8393 } else if (IS_GEN2(dev))
79e53945
JB		 8394 intel_dvo_init(dev);
8395
103a196f 8396 if (SUPPORTS_TV(dev))
79e53945
JB		 8397 intel_tv_init(dev);
8398
4ef69c7a
CW		 8399 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8400 encoder->base.possible_crtcs = encoder->crtc_mask;
8401 encoder->base.possible_clones =
66a9278e 8402 intel_encoder_clones(encoder);
79e53945 8403 }
47356eb6 8404
40579abe 8405 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9fb526db 8406 ironlake_init_pch_refclk(dev);
79e53945
JB		 8407}
8408
8409static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8410{
8411 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8412
8413 drm_framebuffer_cleanup(fb);
05394f39 8414 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8415
8416 kfree(intel_fb);
8417}
8418
8419static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8420 struct drm_file *file,
79e53945
JB		 8421 unsigned int *handle)
8422{
8423 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8424 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8425
05394f39 8426 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8427}
8428
8429static const struct drm_framebuffer_funcs intel_fb_funcs = {
8430 .destroy = intel_user_framebuffer_destroy,
8431 .create_handle = intel_user_framebuffer_create_handle,
8432};
8433
38651674
DA		 8434int intel_framebuffer_init(struct drm_device *dev,
8435 struct intel_framebuffer *intel_fb,
308e5bcb 8436 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8437 struct drm_i915_gem_object *obj)
79e53945 8438{
79e53945
JB		 8439 int ret;
8440
05394f39 8441 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 8442 return -EINVAL;
8443
308e5bcb 8444 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 8445 return -EINVAL;
8446
5d7bd705
VS		 8447 /* FIXME <= Gen4 stride limits are bit unclear */
8448 if (mode_cmd->pitches[0] > 32768)
8449 return -EINVAL;
8450
8451 if (obj->tiling_mode != I915_TILING_NONE &&
8452 mode_cmd->pitches[0] != obj->stride)
8453 return -EINVAL;
8454
57779d06 8455 /* Reject formats not supported by any plane early. */
308e5bcb 8456 switch (mode_cmd->pixel_format) {
57779d06 8457 case DRM_FORMAT_C8:
04b3924d
VS		 8458 case DRM_FORMAT_RGB565:
8459 case DRM_FORMAT_XRGB8888:
8460 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8461 break;
8462 case DRM_FORMAT_XRGB1555:
8463 case DRM_FORMAT_ARGB1555:
8464 if (INTEL_INFO(dev)->gen > 3)
8465 return -EINVAL;
8466 break;
8467 case DRM_FORMAT_XBGR8888:
8468 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8469 case DRM_FORMAT_XRGB2101010:
8470 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8471 case DRM_FORMAT_XBGR2101010:
8472 case DRM_FORMAT_ABGR2101010:
8473 if (INTEL_INFO(dev)->gen < 4)
8474 return -EINVAL;
b5626747 8475 break;
04b3924d
VS		 8476 case DRM_FORMAT_YUYV:
8477 case DRM_FORMAT_UYVY:
8478 case DRM_FORMAT_YVYU:
8479 case DRM_FORMAT_VYUY:
57779d06
VS		 8480 if (INTEL_INFO(dev)->gen < 6)
8481 return -EINVAL;
57cd6508
CW		 8482 break;
8483 default:
57779d06 8484 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8485 return -EINVAL;
8486 }
8487
90f9a336
VS		 8488 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8489 if (mode_cmd->offsets[0] != 0)
8490 return -EINVAL;
8491
79e53945
JB		 8492 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8493 if (ret) {
8494 DRM_ERROR("framebuffer init failed %d\n", ret);
8495 return ret;
8496 }
8497
8498 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 8499 intel_fb->obj = obj;
79e53945
JB		 8500 return 0;
8501}
8502
79e53945
JB		 8503static struct drm_framebuffer *
8504intel_user_framebuffer_create(struct drm_device *dev,
8505 struct drm_file *filp,
308e5bcb 8506 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8507{
05394f39 8508 struct drm_i915_gem_object *obj;
79e53945 8509
308e5bcb
JB		 8510 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8511 mode_cmd->handles[0]));
c8725226 8512 if (&obj->base == NULL)
cce13ff7 8513 return ERR_PTR(-ENOENT);
79e53945 8514
d2dff872 8515 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8516}
8517
79e53945 8518static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8519 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8520 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8521};
8522
e70236a8
JB		 8523/* Set up chip specific display functions */
8524static void intel_init_display(struct drm_device *dev)
8525{
8526 struct drm_i915_private *dev_priv = dev->dev_private;
8527
8528 /* We always want a DPMS function */
09b4ddf9
PZ		 8529 if (IS_HASWELL(dev)) {
8530 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8531 dev_priv->display.crtc_enable = haswell_crtc_enable;
8532 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8533 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8534 dev_priv->display.update_plane = ironlake_update_plane;
8535 } else if (HAS_PCH_SPLIT(dev)) {
f564048e 8536 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8537 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8538 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8539 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8540 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8541 } else {
f564048e 8542 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8543 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8544 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8545 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8546 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8547 }
e70236a8 8548
e70236a8 8549 /* Returns the core display clock speed */
25eb05fc
JB		 8550 if (IS_VALLEYVIEW(dev))
8551 dev_priv->display.get_display_clock_speed =
8552 valleyview_get_display_clock_speed;
8553 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8554 dev_priv->display.get_display_clock_speed =
8555 i945_get_display_clock_speed;
8556 else if (IS_I915G(dev))
8557 dev_priv->display.get_display_clock_speed =
8558 i915_get_display_clock_speed;
f2b115e6 8559 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8560 dev_priv->display.get_display_clock_speed =
8561 i9xx_misc_get_display_clock_speed;
8562 else if (IS_I915GM(dev))
8563 dev_priv->display.get_display_clock_speed =
8564 i915gm_get_display_clock_speed;
8565 else if (IS_I865G(dev))
8566 dev_priv->display.get_display_clock_speed =
8567 i865_get_display_clock_speed;
f0f8a9ce 8568 else if (IS_I85X(dev))
e70236a8
JB		 8569 dev_priv->display.get_display_clock_speed =
8570 i855_get_display_clock_speed;
8571 else /* 852, 830 */
8572 dev_priv->display.get_display_clock_speed =
8573 i830_get_display_clock_speed;
8574
7f8a8569 8575 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8576 if (IS_GEN5(dev)) {
674cf967 8577 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8578 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8579 } else if (IS_GEN6(dev)) {
674cf967 8580 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8581 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8582 } else if (IS_IVYBRIDGE(dev)) {
8583 /* FIXME: detect B0+ stepping and use auto training */
8584 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8585 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8586 dev_priv->display.modeset_global_resources =
8587 ivb_modeset_global_resources;
c82e4d26
ED		 8588 } else if (IS_HASWELL(dev)) {
8589 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8590 dev_priv->display.write_eld = haswell_write_eld;
7f8a8569
ZW		 8591 } else
8592 dev_priv->display.update_wm = NULL;
6067aaea 8593 } else if (IS_G4X(dev)) {
e0dac65e 8594 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8595 }
8c9f3aaf
JB		 8596
8597 /* Default just returns -ENODEV to indicate unsupported */
8598 dev_priv->display.queue_flip = intel_default_queue_flip;
8599
8600 switch (INTEL_INFO(dev)->gen) {
8601 case 2:
8602 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8603 break;
8604
8605 case 3:
8606 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8607 break;
8608
8609 case 4:
8610 case 5:
8611 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8612 break;
8613
8614 case 6:
8615 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8616 break;
7c9017e5
JB		 8617 case 7:
8618 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8619 break;
8c9f3aaf 8620 }
e70236a8
JB		 8621}
8622
b690e96c
JB		 8623/*
8624 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8625 * resume, or other times. This quirk makes sure that's the case for
8626 * affected systems.
8627 */
0206e353 8628static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8629{
8630 struct drm_i915_private *dev_priv = dev->dev_private;
8631
8632 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8633 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8634}
8635
435793df
KP		 8636/*
8637 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8638 */
8639static void quirk_ssc_force_disable(struct drm_device *dev)
8640{
8641 struct drm_i915_private *dev_priv = dev->dev_private;
8642 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8643 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8644}
8645
4dca20ef 8646/*
5a15ab5b
CE		 8647 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8648 * brightness value
4dca20ef
CE		 8649 */
8650static void quirk_invert_brightness(struct drm_device *dev)
8651{
8652 struct drm_i915_private *dev_priv = dev->dev_private;
8653 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8654 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8655}
8656
b690e96c
JB		 8657struct intel_quirk {
8658 int device;
8659 int subsystem_vendor;
8660 int subsystem_device;
8661 void (*hook)(struct drm_device *dev);
8662};
8663
c43b5634 8664static struct intel_quirk intel_quirks[] = {
b690e96c 8665 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8666 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8667
b690e96c
JB		 8668 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8669 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8670
b690e96c
JB		 8671 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8672 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8673
ccd0d36e 8674 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 8675 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 8676 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8677
8678 /* Lenovo U160 cannot use SSC on LVDS */
8679 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8680
8681 /* Sony Vaio Y cannot use SSC on LVDS */
8682 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 8683
8684 /* Acer Aspire 5734Z must invert backlight brightness */
8685 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
b690e96c
JB		 8686};
8687
8688static void intel_init_quirks(struct drm_device *dev)
8689{
8690 struct pci_dev *d = dev->pdev;
8691 int i;
8692
8693 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8694 struct intel_quirk *q = &intel_quirks[i];
8695
8696 if (d->device == q->device &&
8697 (d->subsystem_vendor == q->subsystem_vendor ||
8698 q->subsystem_vendor == PCI_ANY_ID) &&
8699 (d->subsystem_device == q->subsystem_device ||
8700 q->subsystem_device == PCI_ANY_ID))
8701 q->hook(dev);
8702 }
8703}
8704
9cce37f4
JB		 8705/* Disable the VGA plane that we never use */
8706static void i915_disable_vga(struct drm_device *dev)
8707{
8708 struct drm_i915_private *dev_priv = dev->dev_private;
8709 u8 sr1;
8710 u32 vga_reg;
8711
8712 if (HAS_PCH_SPLIT(dev))
8713 vga_reg = CPU_VGACNTRL;
8714 else
8715 vga_reg = VGACNTRL;
8716
8717 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 8718 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 8719 sr1 = inb(VGA_SR_DATA);
8720 outb(sr1 | 1<<5, VGA_SR_DATA);
8721 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8722 udelay(300);
8723
8724 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8725 POSTING_READ(vga_reg);
8726}
8727
f817586c
DV		 8728void intel_modeset_init_hw(struct drm_device *dev)
8729{
0232e927
ED		 8730 /* We attempt to init the necessary power wells early in the initialization
8731 * time, so the subsystems that expect power to be enabled can work.
8732 */
8733 intel_init_power_wells(dev);
8734
a8f78b58
ED		 8735 intel_prepare_ddi(dev);
8736
f817586c
DV		 8737 intel_init_clock_gating(dev);
8738
79f5b2c7 8739 mutex_lock(&dev->struct_mutex);
8090c6b9 8740 intel_enable_gt_powersave(dev);
79f5b2c7 8741 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 8742}
8743
79e53945
JB		 8744void intel_modeset_init(struct drm_device *dev)
8745{
652c393a 8746 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 8747 int i, ret;
79e53945
JB		 8748
8749 drm_mode_config_init(dev);
8750
8751 dev->mode_config.min_width = 0;
8752 dev->mode_config.min_height = 0;
8753
019d96cb
DA		 8754 dev->mode_config.preferred_depth = 24;
8755 dev->mode_config.prefer_shadow = 1;
8756
e6ecefaa 8757 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 8758
b690e96c
JB		 8759 intel_init_quirks(dev);
8760
1fa61106
ED		 8761 intel_init_pm(dev);
8762
e70236a8
JB		 8763 intel_init_display(dev);
8764
a6c45cf0
CW		 8765 if (IS_GEN2(dev)) {
8766 dev->mode_config.max_width = 2048;
8767 dev->mode_config.max_height = 2048;
8768 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8769 dev->mode_config.max_width = 4096;
8770 dev->mode_config.max_height = 4096;
79e53945 8771 } else {
a6c45cf0
CW		 8772 dev->mode_config.max_width = 8192;
8773 dev->mode_config.max_height = 8192;
79e53945 8774 }
dd2757f8 8775 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
79e53945 8776
28c97730 8777 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 8778 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 8779
a3524f1b 8780 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 8781 intel_crtc_init(dev, i);
00c2064b
JB		 8782 ret = intel_plane_init(dev, i);
8783 if (ret)
8784 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 8785 }
8786
79f689aa 8787 intel_cpu_pll_init(dev);
ee7b9f93
JB		 8788 intel_pch_pll_init(dev);
8789
9cce37f4
JB		 8790 /* Just disable it once at startup */
8791 i915_disable_vga(dev);
79e53945 8792 intel_setup_outputs(dev);
2c7111db
CW		 8793}
8794
24929352
DV		 8795static void
8796intel_connector_break_all_links(struct intel_connector *connector)
8797{
8798 connector->base.dpms = DRM_MODE_DPMS_OFF;
8799 connector->base.encoder = NULL;
8800 connector->encoder->connectors_active = false;
8801 connector->encoder->base.crtc = NULL;
8802}
8803
7fad798e
DV		 8804static void intel_enable_pipe_a(struct drm_device *dev)
8805{
8806 struct intel_connector *connector;
8807 struct drm_connector *crt = NULL;
8808 struct intel_load_detect_pipe load_detect_temp;
8809
8810 /* We can't just switch on the pipe A, we need to set things up with a
8811 * proper mode and output configuration. As a gross hack, enable pipe A
8812 * by enabling the load detect pipe once. */
8813 list_for_each_entry(connector,
8814 &dev->mode_config.connector_list,
8815 base.head) {
8816 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8817 crt = &connector->base;
8818 break;
8819 }
8820 }
8821
8822 if (!crt)
8823 return;
8824
8825 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8826 intel_release_load_detect_pipe(crt, &load_detect_temp);
8827
8828
8829}
8830
fa555837
DV		 8831static bool
8832intel_check_plane_mapping(struct intel_crtc *crtc)
8833{
8834 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8835 u32 reg, val;
8836
8837 if (dev_priv->num_pipe == 1)
8838 return true;
8839
8840 reg = DSPCNTR(!crtc->plane);
8841 val = I915_READ(reg);
8842
8843 if ((val & DISPLAY_PLANE_ENABLE) &&
8844 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8845 return false;
8846
8847 return true;
8848}
8849
24929352
DV		 8850static void intel_sanitize_crtc(struct intel_crtc *crtc)
8851{
8852 struct drm_device *dev = crtc->base.dev;
8853 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 8854 u32 reg;
24929352 8855
24929352 8856 /* Clear any frame start delays used for debugging left by the BIOS */
702e7a56 8857 reg = PIPECONF(crtc->cpu_transcoder);
24929352
DV		 8858 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8859
8860 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 8861 * disable the crtc (and hence change the state) if it is wrong. Note
8862 * that gen4+ has a fixed plane -> pipe mapping. */
8863 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 8864 struct intel_connector *connector;
8865 bool plane;
8866
24929352
DV		 8867 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8868 crtc->base.base.id);
8869
8870 /* Pipe has the wrong plane attached and the plane is active.
8871 * Temporarily change the plane mapping and disable everything
8872 * ... */
8873 plane = crtc->plane;
8874 crtc->plane = !plane;
8875 dev_priv->display.crtc_disable(&crtc->base);
8876 crtc->plane = plane;
8877
8878 /* ... and break all links. */
8879 list_for_each_entry(connector, &dev->mode_config.connector_list,
8880 base.head) {
8881 if (connector->encoder->base.crtc != &crtc->base)
8882 continue;
8883
8884 intel_connector_break_all_links(connector);
8885 }
8886
8887 WARN_ON(crtc->active);
8888 crtc->base.enabled = false;
8889 }
24929352 8890
7fad798e
DV		 8891 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8892 crtc->pipe == PIPE_A && !crtc->active) {
8893 /* BIOS forgot to enable pipe A, this mostly happens after
8894 * resume. Force-enable the pipe to fix this, the update_dpms
8895 * call below we restore the pipe to the right state, but leave
8896 * the required bits on. */
8897 intel_enable_pipe_a(dev);
8898 }
8899
24929352
DV		 8900 /* Adjust the state of the output pipe according to whether we
8901 * have active connectors/encoders. */
8902 intel_crtc_update_dpms(&crtc->base);
8903
8904 if (crtc->active != crtc->base.enabled) {
8905 struct intel_encoder *encoder;
8906
8907 /* This can happen either due to bugs in the get_hw_state
8908 * functions or because the pipe is force-enabled due to the
8909 * pipe A quirk. */
8910 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8911 crtc->base.base.id,
8912 crtc->base.enabled ? "enabled" : "disabled",
8913 crtc->active ? "enabled" : "disabled");
8914
8915 crtc->base.enabled = crtc->active;
8916
8917 /* Because we only establish the connector -> encoder ->
8918 * crtc links if something is active, this means the
8919 * crtc is now deactivated. Break the links. connector
8920 * -> encoder links are only establish when things are
8921 * actually up, hence no need to break them. */
8922 WARN_ON(crtc->active);
8923
8924 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8925 WARN_ON(encoder->connectors_active);
8926 encoder->base.crtc = NULL;
8927 }
8928 }
8929}
8930
8931static void intel_sanitize_encoder(struct intel_encoder *encoder)
8932{
8933 struct intel_connector *connector;
8934 struct drm_device *dev = encoder->base.dev;
8935
8936 /* We need to check both for a crtc link (meaning that the
8937 * encoder is active and trying to read from a pipe) and the
8938 * pipe itself being active. */
8939 bool has_active_crtc = encoder->base.crtc &&
8940 to_intel_crtc(encoder->base.crtc)->active;
8941
8942 if (encoder->connectors_active && !has_active_crtc) {
8943 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8944 encoder->base.base.id,
8945 drm_get_encoder_name(&encoder->base));
8946
8947 /* Connector is active, but has no active pipe. This is
8948 * fallout from our resume register restoring. Disable
8949 * the encoder manually again. */
8950 if (encoder->base.crtc) {
8951 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8952 encoder->base.base.id,
8953 drm_get_encoder_name(&encoder->base));
8954 encoder->disable(encoder);
8955 }
8956
8957 /* Inconsistent output/port/pipe state happens presumably due to
8958 * a bug in one of the get_hw_state functions. Or someplace else
8959 * in our code, like the register restore mess on resume. Clamp
8960 * things to off as a safer default. */
8961 list_for_each_entry(connector,
8962 &dev->mode_config.connector_list,
8963 base.head) {
8964 if (connector->encoder != encoder)
8965 continue;
8966
8967 intel_connector_break_all_links(connector);
8968 }
8969 }
8970 /* Enabled encoders without active connectors will be fixed in
8971 * the crtc fixup. */
8972}
8973
8974/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8975 * and i915 state tracking structures. */
8976void intel_modeset_setup_hw_state(struct drm_device *dev)
8977{
8978 struct drm_i915_private *dev_priv = dev->dev_private;
8979 enum pipe pipe;
8980 u32 tmp;
8981 struct intel_crtc *crtc;
8982 struct intel_encoder *encoder;
8983 struct intel_connector *connector;
8984
e28d54cb
PZ		 8985 if (IS_HASWELL(dev)) {
8986 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8987
8988 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8989 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8990 case TRANS_DDI_EDP_INPUT_A_ON:
8991 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8992 pipe = PIPE_A;
8993 break;
8994 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8995 pipe = PIPE_B;
8996 break;
8997 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8998 pipe = PIPE_C;
8999 break;
9000 }
9001
9002 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9003 crtc->cpu_transcoder = TRANSCODER_EDP;
9004
9005 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9006 pipe_name(pipe));
9007 }
9008 }
9009
24929352
DV		 9010 for_each_pipe(pipe) {
9011 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9012
702e7a56 9013 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
24929352
DV		 9014 if (tmp & PIPECONF_ENABLE)
9015 crtc->active = true;
9016 else
9017 crtc->active = false;
9018
9019 crtc->base.enabled = crtc->active;
9020
9021 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9022 crtc->base.base.id,
9023 crtc->active ? "enabled" : "disabled");
9024 }
9025
6441ab5f
PZ		 9026 if (IS_HASWELL(dev))
9027 intel_ddi_setup_hw_pll_state(dev);
9028
24929352
DV		 9029 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9030 base.head) {
9031 pipe = 0;
9032
9033 if (encoder->get_hw_state(encoder, &pipe)) {
9034 encoder->base.crtc =
9035 dev_priv->pipe_to_crtc_mapping[pipe];
9036 } else {
9037 encoder->base.crtc = NULL;
9038 }
9039
9040 encoder->connectors_active = false;
9041 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9042 encoder->base.base.id,
9043 drm_get_encoder_name(&encoder->base),
9044 encoder->base.crtc ? "enabled" : "disabled",
9045 pipe);
9046 }
9047
9048 list_for_each_entry(connector, &dev->mode_config.connector_list,
9049 base.head) {
9050 if (connector->get_hw_state(connector)) {
9051 connector->base.dpms = DRM_MODE_DPMS_ON;
9052 connector->encoder->connectors_active = true;
9053 connector->base.encoder = &connector->encoder->base;
9054 } else {
9055 connector->base.dpms = DRM_MODE_DPMS_OFF;
9056 connector->base.encoder = NULL;
9057 }
9058 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9059 connector->base.base.id,
9060 drm_get_connector_name(&connector->base),
9061 connector->base.encoder ? "enabled" : "disabled");
9062 }
9063
9064 /* HW state is read out, now we need to sanitize this mess. */
9065 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9066 base.head) {
9067 intel_sanitize_encoder(encoder);
9068 }
9069
9070 for_each_pipe(pipe) {
9071 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9072 intel_sanitize_crtc(crtc);
9073 }
9a935856
DV		 9074
9075 intel_modeset_update_staged_output_state(dev);
8af6cf88
DV		 9076
9077 intel_modeset_check_state(dev);
2e938892
DV		 9078
9079 drm_mode_config_reset(dev);
24929352
DV		 9080}
9081
2c7111db
CW		 9082void intel_modeset_gem_init(struct drm_device *dev)
9083{
1833b134 9084 intel_modeset_init_hw(dev);
02e792fb
DV		 9085
9086 intel_setup_overlay(dev);
24929352
DV		 9087
9088 intel_modeset_setup_hw_state(dev);
79e53945
JB		 9089}
9090
9091void intel_modeset_cleanup(struct drm_device *dev)
9092{
652c393a
JB		 9093 struct drm_i915_private *dev_priv = dev->dev_private;
9094 struct drm_crtc *crtc;
9095 struct intel_crtc *intel_crtc;
9096
f87ea761 9097 drm_kms_helper_poll_fini(dev);
652c393a
JB		 9098 mutex_lock(&dev->struct_mutex);
9099
723bfd70
JB		 9100 intel_unregister_dsm_handler();
9101
9102
652c393a
JB		 9103 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9104 /* Skip inactive CRTCs */
9105 if (!crtc->fb)
9106 continue;
9107
9108 intel_crtc = to_intel_crtc(crtc);
3dec0095 9109 intel_increase_pllclock(crtc);
652c393a
JB		 9110 }
9111
973d04f9 9112 intel_disable_fbc(dev);
e70236a8 9113
8090c6b9 9114 intel_disable_gt_powersave(dev);
0cdab21f 9115
930ebb46
DV		 9116 ironlake_teardown_rc6(dev);
9117
57f350b6
JB		 9118 if (IS_VALLEYVIEW(dev))
9119 vlv_init_dpio(dev);
9120
69341a5e
KH		 9121 mutex_unlock(&dev->struct_mutex);
9122
6c0d9350
DV		 9123 /* Disable the irq before mode object teardown, for the irq might
9124 * enqueue unpin/hotplug work. */
9125 drm_irq_uninstall(dev);
9126 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 9127 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 9128
1630fe75
CW		 9129 /* flush any delayed tasks or pending work */
9130 flush_scheduled_work();
9131
79e53945
JB		 9132 drm_mode_config_cleanup(dev);
9133}
9134
f1c79df3
ZW		 9135/*
9136 * Return which encoder is currently attached for connector.
9137 */
df0e9248 9138struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9139{
df0e9248
CW		 9140 return &intel_attached_encoder(connector)->base;
9141}
f1c79df3 9142
df0e9248
CW		 9143void intel_connector_attach_encoder(struct intel_connector *connector,
9144 struct intel_encoder *encoder)
9145{
9146 connector->encoder = encoder;
9147 drm_mode_connector_attach_encoder(&connector->base,
9148 &encoder->base);
79e53945 9149}
28d52043
DA		 9150
9151/*
9152 * set vga decode state - true == enable VGA decode
9153 */
9154int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9155{
9156 struct drm_i915_private *dev_priv = dev->dev_private;
9157 u16 gmch_ctrl;
9158
9159 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9160 if (state)
9161 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9162 else
9163 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9164 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9165 return 0;
9166}
c4a1d9e4
CW		 9167
9168#ifdef CONFIG_DEBUG_FS
9169#include <linux/seq_file.h>
9170
9171struct intel_display_error_state {
9172 struct intel_cursor_error_state {
9173 u32 control;
9174 u32 position;
9175 u32 base;
9176 u32 size;
52331309 9177 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9178
9179 struct intel_pipe_error_state {
9180 u32 conf;
9181 u32 source;
9182
9183 u32 htotal;
9184 u32 hblank;
9185 u32 hsync;
9186 u32 vtotal;
9187 u32 vblank;
9188 u32 vsync;
52331309 9189 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9190
9191 struct intel_plane_error_state {
9192 u32 control;
9193 u32 stride;
9194 u32 size;
9195 u32 pos;
9196 u32 addr;
9197 u32 surface;
9198 u32 tile_offset;
52331309 9199 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9200};
9201
9202struct intel_display_error_state *
9203intel_display_capture_error_state(struct drm_device *dev)
9204{
0206e353 9205 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9206 struct intel_display_error_state *error;
702e7a56 9207 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9208 int i;
9209
9210 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9211 if (error == NULL)
9212 return NULL;
9213
52331309 9214 for_each_pipe(i) {
702e7a56
PZ		 9215 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9216
c4a1d9e4
CW		 9217 error->cursor[i].control = I915_READ(CURCNTR(i));
9218 error->cursor[i].position = I915_READ(CURPOS(i));
9219 error->cursor[i].base = I915_READ(CURBASE(i));
9220
9221 error->plane[i].control = I915_READ(DSPCNTR(i));
9222 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9223 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 9224 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 9225 error->plane[i].addr = I915_READ(DSPADDR(i));
9226 if (INTEL_INFO(dev)->gen >= 4) {
9227 error->plane[i].surface = I915_READ(DSPSURF(i));
9228 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9229 }
9230
702e7a56 9231 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9232 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9233 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9234 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9235 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9236 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9237 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9238 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9239 }
9240
9241 return error;
9242}
9243
9244void
9245intel_display_print_error_state(struct seq_file *m,
9246 struct drm_device *dev,
9247 struct intel_display_error_state *error)
9248{
52331309 9249 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 9250 int i;
9251
52331309
DL		 9252 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9253 for_each_pipe(i) {
c4a1d9e4
CW		 9254 seq_printf(m, "Pipe [%d]:\n", i);
9255 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9256 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9257 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9258 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9259 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9260 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9261 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9262 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9263
9264 seq_printf(m, "Plane [%d]:\n", i);
9265 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9266 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9267 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9268 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9269 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9270 if (INTEL_INFO(dev)->gen >= 4) {
9271 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9272 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9273 }
9274
9275 seq_printf(m, "Cursor [%d]:\n", i);
9276 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9277 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9278 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9279 }
9280}
9281#endif
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