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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
5d723d7a | 37 | #include "intel_frontbuffer.h" |
760285e7 | 38 | #include <drm/i915_drm.h> |
79e53945 | 39 | #include "i915_drv.h" |
db18b6a6 | 40 | #include "intel_dsi.h" |
e5510fac | 41 | #include "i915_trace.h" |
319c1d42 | 42 | #include <drm/drm_atomic.h> |
c196e1d6 | 43 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
44 | #include <drm/drm_dp_helper.h> |
45 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
46 | #include <drm/drm_plane_helper.h> |
47 | #include <drm/drm_rect.h> | |
c0f372b3 | 48 | #include <linux/dma_remapping.h> |
fd8e058a | 49 | #include <linux/reservation.h> |
79e53945 | 50 | |
5a21b665 DV |
51 | static bool is_mmio_work(struct intel_flip_work *work) |
52 | { | |
53 | return work->mmio_work.func; | |
54 | } | |
55 | ||
465c120c | 56 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 57 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
58 | DRM_FORMAT_C8, |
59 | DRM_FORMAT_RGB565, | |
465c120c | 60 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 61 | DRM_FORMAT_XRGB8888, |
465c120c MR |
62 | }; |
63 | ||
64 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 65 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
66 | DRM_FORMAT_C8, |
67 | DRM_FORMAT_RGB565, | |
68 | DRM_FORMAT_XRGB8888, | |
69 | DRM_FORMAT_XBGR8888, | |
70 | DRM_FORMAT_XRGB2101010, | |
71 | DRM_FORMAT_XBGR2101010, | |
72 | }; | |
73 | ||
74 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
75 | DRM_FORMAT_C8, |
76 | DRM_FORMAT_RGB565, | |
77 | DRM_FORMAT_XRGB8888, | |
465c120c | 78 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 79 | DRM_FORMAT_ARGB8888, |
465c120c MR |
80 | DRM_FORMAT_ABGR8888, |
81 | DRM_FORMAT_XRGB2101010, | |
465c120c | 82 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
83 | DRM_FORMAT_YUYV, |
84 | DRM_FORMAT_YVYU, | |
85 | DRM_FORMAT_UYVY, | |
86 | DRM_FORMAT_VYUY, | |
465c120c MR |
87 | }; |
88 | ||
3d7d6510 MR |
89 | /* Cursor formats */ |
90 | static const uint32_t intel_cursor_formats[] = { | |
91 | DRM_FORMAT_ARGB8888, | |
92 | }; | |
93 | ||
f1f644dc | 94 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 95 | struct intel_crtc_state *pipe_config); |
18442d08 | 96 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 97 | struct intel_crtc_state *pipe_config); |
f1f644dc | 98 | |
eb1bfe80 JB |
99 | static int intel_framebuffer_init(struct drm_device *dev, |
100 | struct intel_framebuffer *ifb, | |
101 | struct drm_mode_fb_cmd2 *mode_cmd, | |
102 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
103 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
104 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
bc58be60 | 105 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc); |
29407aab | 106 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
107 | struct intel_link_m_n *m_n, |
108 | struct intel_link_m_n *m2_n2); | |
29407aab | 109 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 | 110 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
391bf048 | 111 | static void haswell_set_pipemisc(struct drm_crtc *crtc); |
d288f65f | 112 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 113 | const struct intel_crtc_state *pipe_config); |
d288f65f | 114 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 115 | const struct intel_crtc_state *pipe_config); |
5a21b665 DV |
116 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
117 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
65edccce VS |
118 | static void skl_init_scalers(struct drm_i915_private *dev_priv, |
119 | struct intel_crtc *crtc, | |
120 | struct intel_crtc_state *crtc_state); | |
bfd16b2a ML |
121 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
122 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
123 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
043e9bda | 124 | static void intel_modeset_setup_hw_state(struct drm_device *dev); |
2622a081 | 125 | static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc); |
4e5ca60f | 126 | static int ilk_max_pixel_rate(struct drm_atomic_state *state); |
89b3c3c7 | 127 | static int glk_calc_cdclk(int max_pixclk); |
324513c0 | 128 | static int bxt_calc_cdclk(int max_pixclk); |
e7457a9a | 129 | |
d4906093 | 130 | struct intel_limit { |
4c5def93 ACO |
131 | struct { |
132 | int min, max; | |
133 | } dot, vco, n, m, m1, m2, p, p1; | |
134 | ||
135 | struct { | |
136 | int dot_limit; | |
137 | int p2_slow, p2_fast; | |
138 | } p2; | |
d4906093 | 139 | }; |
79e53945 | 140 | |
bfa7df01 VS |
141 | /* returns HPLL frequency in kHz */ |
142 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) | |
143 | { | |
144 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
145 | ||
146 | /* Obtain SKU information */ | |
147 | mutex_lock(&dev_priv->sb_lock); | |
148 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
149 | CCK_FUSE_HPLL_FREQ_MASK; | |
150 | mutex_unlock(&dev_priv->sb_lock); | |
151 | ||
152 | return vco_freq[hpll_freq] * 1000; | |
153 | } | |
154 | ||
c30fec65 VS |
155 | int vlv_get_cck_clock(struct drm_i915_private *dev_priv, |
156 | const char *name, u32 reg, int ref_freq) | |
bfa7df01 VS |
157 | { |
158 | u32 val; | |
159 | int divider; | |
160 | ||
bfa7df01 VS |
161 | mutex_lock(&dev_priv->sb_lock); |
162 | val = vlv_cck_read(dev_priv, reg); | |
163 | mutex_unlock(&dev_priv->sb_lock); | |
164 | ||
165 | divider = val & CCK_FREQUENCY_VALUES; | |
166 | ||
167 | WARN((val & CCK_FREQUENCY_STATUS) != | |
168 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
169 | "%s change in progress\n", name); | |
170 | ||
c30fec65 VS |
171 | return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); |
172 | } | |
173 | ||
174 | static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, | |
175 | const char *name, u32 reg) | |
176 | { | |
177 | if (dev_priv->hpll_freq == 0) | |
178 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
179 | ||
180 | return vlv_get_cck_clock(dev_priv, name, reg, | |
181 | dev_priv->hpll_freq); | |
bfa7df01 VS |
182 | } |
183 | ||
e7dc33f3 VS |
184 | static int |
185 | intel_pch_rawclk(struct drm_i915_private *dev_priv) | |
d2acd215 | 186 | { |
e7dc33f3 VS |
187 | return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; |
188 | } | |
d2acd215 | 189 | |
e7dc33f3 VS |
190 | static int |
191 | intel_vlv_hrawclk(struct drm_i915_private *dev_priv) | |
192 | { | |
19ab4ed3 | 193 | /* RAWCLK_FREQ_VLV register updated from power well code */ |
35d38d1f VS |
194 | return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", |
195 | CCK_DISPLAY_REF_CLOCK_CONTROL); | |
d2acd215 DV |
196 | } |
197 | ||
e7dc33f3 VS |
198 | static int |
199 | intel_g4x_hrawclk(struct drm_i915_private *dev_priv) | |
79e50a4f | 200 | { |
79e50a4f JN |
201 | uint32_t clkcfg; |
202 | ||
e7dc33f3 | 203 | /* hrawclock is 1/4 the FSB frequency */ |
79e50a4f JN |
204 | clkcfg = I915_READ(CLKCFG); |
205 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
206 | case CLKCFG_FSB_400: | |
e7dc33f3 | 207 | return 100000; |
79e50a4f | 208 | case CLKCFG_FSB_533: |
e7dc33f3 | 209 | return 133333; |
79e50a4f | 210 | case CLKCFG_FSB_667: |
e7dc33f3 | 211 | return 166667; |
79e50a4f | 212 | case CLKCFG_FSB_800: |
e7dc33f3 | 213 | return 200000; |
79e50a4f | 214 | case CLKCFG_FSB_1067: |
e7dc33f3 | 215 | return 266667; |
79e50a4f | 216 | case CLKCFG_FSB_1333: |
e7dc33f3 | 217 | return 333333; |
79e50a4f JN |
218 | /* these two are just a guess; one of them might be right */ |
219 | case CLKCFG_FSB_1600: | |
220 | case CLKCFG_FSB_1600_ALT: | |
e7dc33f3 | 221 | return 400000; |
79e50a4f | 222 | default: |
e7dc33f3 | 223 | return 133333; |
79e50a4f JN |
224 | } |
225 | } | |
226 | ||
19ab4ed3 | 227 | void intel_update_rawclk(struct drm_i915_private *dev_priv) |
e7dc33f3 VS |
228 | { |
229 | if (HAS_PCH_SPLIT(dev_priv)) | |
230 | dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv); | |
231 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
232 | dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv); | |
233 | else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv)) | |
234 | dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv); | |
235 | else | |
236 | return; /* no rawclk on other platforms, or no need to know it */ | |
237 | ||
238 | DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq); | |
239 | } | |
240 | ||
bfa7df01 VS |
241 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
242 | { | |
666a4537 | 243 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
bfa7df01 VS |
244 | return; |
245 | ||
246 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
247 | CCK_CZ_CLOCK_CONTROL); | |
248 | ||
249 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); | |
250 | } | |
251 | ||
021357ac | 252 | static inline u32 /* units of 100MHz */ |
21a727b3 VS |
253 | intel_fdi_link_freq(struct drm_i915_private *dev_priv, |
254 | const struct intel_crtc_state *pipe_config) | |
021357ac | 255 | { |
21a727b3 VS |
256 | if (HAS_DDI(dev_priv)) |
257 | return pipe_config->port_clock; /* SPLL */ | |
258 | else if (IS_GEN5(dev_priv)) | |
259 | return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000; | |
e3b247da | 260 | else |
21a727b3 | 261 | return 270000; |
021357ac CW |
262 | } |
263 | ||
1b6f4958 | 264 | static const struct intel_limit intel_limits_i8xx_dac = { |
0206e353 | 265 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 266 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 267 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
268 | .m = { .min = 96, .max = 140 }, |
269 | .m1 = { .min = 18, .max = 26 }, | |
270 | .m2 = { .min = 6, .max = 16 }, | |
271 | .p = { .min = 4, .max = 128 }, | |
272 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
273 | .p2 = { .dot_limit = 165000, |
274 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
275 | }; |
276 | ||
1b6f4958 | 277 | static const struct intel_limit intel_limits_i8xx_dvo = { |
5d536e28 | 278 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 279 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 280 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
281 | .m = { .min = 96, .max = 140 }, |
282 | .m1 = { .min = 18, .max = 26 }, | |
283 | .m2 = { .min = 6, .max = 16 }, | |
284 | .p = { .min = 4, .max = 128 }, | |
285 | .p1 = { .min = 2, .max = 33 }, | |
286 | .p2 = { .dot_limit = 165000, | |
287 | .p2_slow = 4, .p2_fast = 4 }, | |
288 | }; | |
289 | ||
1b6f4958 | 290 | static const struct intel_limit intel_limits_i8xx_lvds = { |
0206e353 | 291 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 292 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 293 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
294 | .m = { .min = 96, .max = 140 }, |
295 | .m1 = { .min = 18, .max = 26 }, | |
296 | .m2 = { .min = 6, .max = 16 }, | |
297 | .p = { .min = 4, .max = 128 }, | |
298 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
299 | .p2 = { .dot_limit = 165000, |
300 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 301 | }; |
273e27ca | 302 | |
1b6f4958 | 303 | static const struct intel_limit intel_limits_i9xx_sdvo = { |
0206e353 AJ |
304 | .dot = { .min = 20000, .max = 400000 }, |
305 | .vco = { .min = 1400000, .max = 2800000 }, | |
306 | .n = { .min = 1, .max = 6 }, | |
307 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
308 | .m1 = { .min = 8, .max = 18 }, |
309 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
310 | .p = { .min = 5, .max = 80 }, |
311 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
312 | .p2 = { .dot_limit = 200000, |
313 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
314 | }; |
315 | ||
1b6f4958 | 316 | static const struct intel_limit intel_limits_i9xx_lvds = { |
0206e353 AJ |
317 | .dot = { .min = 20000, .max = 400000 }, |
318 | .vco = { .min = 1400000, .max = 2800000 }, | |
319 | .n = { .min = 1, .max = 6 }, | |
320 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
321 | .m1 = { .min = 8, .max = 18 }, |
322 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
323 | .p = { .min = 7, .max = 98 }, |
324 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
325 | .p2 = { .dot_limit = 112000, |
326 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
327 | }; |
328 | ||
273e27ca | 329 | |
1b6f4958 | 330 | static const struct intel_limit intel_limits_g4x_sdvo = { |
273e27ca EA |
331 | .dot = { .min = 25000, .max = 270000 }, |
332 | .vco = { .min = 1750000, .max = 3500000}, | |
333 | .n = { .min = 1, .max = 4 }, | |
334 | .m = { .min = 104, .max = 138 }, | |
335 | .m1 = { .min = 17, .max = 23 }, | |
336 | .m2 = { .min = 5, .max = 11 }, | |
337 | .p = { .min = 10, .max = 30 }, | |
338 | .p1 = { .min = 1, .max = 3}, | |
339 | .p2 = { .dot_limit = 270000, | |
340 | .p2_slow = 10, | |
341 | .p2_fast = 10 | |
044c7c41 | 342 | }, |
e4b36699 KP |
343 | }; |
344 | ||
1b6f4958 | 345 | static const struct intel_limit intel_limits_g4x_hdmi = { |
273e27ca EA |
346 | .dot = { .min = 22000, .max = 400000 }, |
347 | .vco = { .min = 1750000, .max = 3500000}, | |
348 | .n = { .min = 1, .max = 4 }, | |
349 | .m = { .min = 104, .max = 138 }, | |
350 | .m1 = { .min = 16, .max = 23 }, | |
351 | .m2 = { .min = 5, .max = 11 }, | |
352 | .p = { .min = 5, .max = 80 }, | |
353 | .p1 = { .min = 1, .max = 8}, | |
354 | .p2 = { .dot_limit = 165000, | |
355 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
356 | }; |
357 | ||
1b6f4958 | 358 | static const struct intel_limit intel_limits_g4x_single_channel_lvds = { |
273e27ca EA |
359 | .dot = { .min = 20000, .max = 115000 }, |
360 | .vco = { .min = 1750000, .max = 3500000 }, | |
361 | .n = { .min = 1, .max = 3 }, | |
362 | .m = { .min = 104, .max = 138 }, | |
363 | .m1 = { .min = 17, .max = 23 }, | |
364 | .m2 = { .min = 5, .max = 11 }, | |
365 | .p = { .min = 28, .max = 112 }, | |
366 | .p1 = { .min = 2, .max = 8 }, | |
367 | .p2 = { .dot_limit = 0, | |
368 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 369 | }, |
e4b36699 KP |
370 | }; |
371 | ||
1b6f4958 | 372 | static const struct intel_limit intel_limits_g4x_dual_channel_lvds = { |
273e27ca EA |
373 | .dot = { .min = 80000, .max = 224000 }, |
374 | .vco = { .min = 1750000, .max = 3500000 }, | |
375 | .n = { .min = 1, .max = 3 }, | |
376 | .m = { .min = 104, .max = 138 }, | |
377 | .m1 = { .min = 17, .max = 23 }, | |
378 | .m2 = { .min = 5, .max = 11 }, | |
379 | .p = { .min = 14, .max = 42 }, | |
380 | .p1 = { .min = 2, .max = 6 }, | |
381 | .p2 = { .dot_limit = 0, | |
382 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 383 | }, |
e4b36699 KP |
384 | }; |
385 | ||
1b6f4958 | 386 | static const struct intel_limit intel_limits_pineview_sdvo = { |
0206e353 AJ |
387 | .dot = { .min = 20000, .max = 400000}, |
388 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 389 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
390 | .n = { .min = 3, .max = 6 }, |
391 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 392 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
393 | .m1 = { .min = 0, .max = 0 }, |
394 | .m2 = { .min = 0, .max = 254 }, | |
395 | .p = { .min = 5, .max = 80 }, | |
396 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
397 | .p2 = { .dot_limit = 200000, |
398 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
399 | }; |
400 | ||
1b6f4958 | 401 | static const struct intel_limit intel_limits_pineview_lvds = { |
0206e353 AJ |
402 | .dot = { .min = 20000, .max = 400000 }, |
403 | .vco = { .min = 1700000, .max = 3500000 }, | |
404 | .n = { .min = 3, .max = 6 }, | |
405 | .m = { .min = 2, .max = 256 }, | |
406 | .m1 = { .min = 0, .max = 0 }, | |
407 | .m2 = { .min = 0, .max = 254 }, | |
408 | .p = { .min = 7, .max = 112 }, | |
409 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
410 | .p2 = { .dot_limit = 112000, |
411 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
412 | }; |
413 | ||
273e27ca EA |
414 | /* Ironlake / Sandybridge |
415 | * | |
416 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
417 | * the range value for them is (actual_value - 2). | |
418 | */ | |
1b6f4958 | 419 | static const struct intel_limit intel_limits_ironlake_dac = { |
273e27ca EA |
420 | .dot = { .min = 25000, .max = 350000 }, |
421 | .vco = { .min = 1760000, .max = 3510000 }, | |
422 | .n = { .min = 1, .max = 5 }, | |
423 | .m = { .min = 79, .max = 127 }, | |
424 | .m1 = { .min = 12, .max = 22 }, | |
425 | .m2 = { .min = 5, .max = 9 }, | |
426 | .p = { .min = 5, .max = 80 }, | |
427 | .p1 = { .min = 1, .max = 8 }, | |
428 | .p2 = { .dot_limit = 225000, | |
429 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
430 | }; |
431 | ||
1b6f4958 | 432 | static const struct intel_limit intel_limits_ironlake_single_lvds = { |
273e27ca EA |
433 | .dot = { .min = 25000, .max = 350000 }, |
434 | .vco = { .min = 1760000, .max = 3510000 }, | |
435 | .n = { .min = 1, .max = 3 }, | |
436 | .m = { .min = 79, .max = 118 }, | |
437 | .m1 = { .min = 12, .max = 22 }, | |
438 | .m2 = { .min = 5, .max = 9 }, | |
439 | .p = { .min = 28, .max = 112 }, | |
440 | .p1 = { .min = 2, .max = 8 }, | |
441 | .p2 = { .dot_limit = 225000, | |
442 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
443 | }; |
444 | ||
1b6f4958 | 445 | static const struct intel_limit intel_limits_ironlake_dual_lvds = { |
273e27ca EA |
446 | .dot = { .min = 25000, .max = 350000 }, |
447 | .vco = { .min = 1760000, .max = 3510000 }, | |
448 | .n = { .min = 1, .max = 3 }, | |
449 | .m = { .min = 79, .max = 127 }, | |
450 | .m1 = { .min = 12, .max = 22 }, | |
451 | .m2 = { .min = 5, .max = 9 }, | |
452 | .p = { .min = 14, .max = 56 }, | |
453 | .p1 = { .min = 2, .max = 8 }, | |
454 | .p2 = { .dot_limit = 225000, | |
455 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
456 | }; |
457 | ||
273e27ca | 458 | /* LVDS 100mhz refclk limits. */ |
1b6f4958 | 459 | static const struct intel_limit intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
460 | .dot = { .min = 25000, .max = 350000 }, |
461 | .vco = { .min = 1760000, .max = 3510000 }, | |
462 | .n = { .min = 1, .max = 2 }, | |
463 | .m = { .min = 79, .max = 126 }, | |
464 | .m1 = { .min = 12, .max = 22 }, | |
465 | .m2 = { .min = 5, .max = 9 }, | |
466 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 467 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
468 | .p2 = { .dot_limit = 225000, |
469 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
470 | }; |
471 | ||
1b6f4958 | 472 | static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = { |
273e27ca EA |
473 | .dot = { .min = 25000, .max = 350000 }, |
474 | .vco = { .min = 1760000, .max = 3510000 }, | |
475 | .n = { .min = 1, .max = 3 }, | |
476 | .m = { .min = 79, .max = 126 }, | |
477 | .m1 = { .min = 12, .max = 22 }, | |
478 | .m2 = { .min = 5, .max = 9 }, | |
479 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 480 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
481 | .p2 = { .dot_limit = 225000, |
482 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
483 | }; |
484 | ||
1b6f4958 | 485 | static const struct intel_limit intel_limits_vlv = { |
f01b7962 VS |
486 | /* |
487 | * These are the data rate limits (measured in fast clocks) | |
488 | * since those are the strictest limits we have. The fast | |
489 | * clock and actual rate limits are more relaxed, so checking | |
490 | * them would make no difference. | |
491 | */ | |
492 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 493 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 494 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
495 | .m1 = { .min = 2, .max = 3 }, |
496 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 497 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 498 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
499 | }; |
500 | ||
1b6f4958 | 501 | static const struct intel_limit intel_limits_chv = { |
ef9348c8 CML |
502 | /* |
503 | * These are the data rate limits (measured in fast clocks) | |
504 | * since those are the strictest limits we have. The fast | |
505 | * clock and actual rate limits are more relaxed, so checking | |
506 | * them would make no difference. | |
507 | */ | |
508 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 509 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
510 | .n = { .min = 1, .max = 1 }, |
511 | .m1 = { .min = 2, .max = 2 }, | |
512 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
513 | .p1 = { .min = 2, .max = 4 }, | |
514 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
515 | }; | |
516 | ||
1b6f4958 | 517 | static const struct intel_limit intel_limits_bxt = { |
5ab7b0b7 ID |
518 | /* FIXME: find real dot limits */ |
519 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 520 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
521 | .n = { .min = 1, .max = 1 }, |
522 | .m1 = { .min = 2, .max = 2 }, | |
523 | /* FIXME: find real m2 limits */ | |
524 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
525 | .p1 = { .min = 2, .max = 4 }, | |
526 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
527 | }; | |
528 | ||
cdba954e ACO |
529 | static bool |
530 | needs_modeset(struct drm_crtc_state *state) | |
531 | { | |
fc596660 | 532 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
533 | } |
534 | ||
dccbea3b ID |
535 | /* |
536 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
537 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
538 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
539 | * The helpers' return value is the rate of the clock that is fed to the | |
540 | * display engine's pipe which can be the above fast dot clock rate or a | |
541 | * divided-down version of it. | |
542 | */ | |
f2b115e6 | 543 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
9e2c8475 | 544 | static int pnv_calc_dpll_params(int refclk, struct dpll *clock) |
79e53945 | 545 | { |
2177832f SL |
546 | clock->m = clock->m2 + 2; |
547 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 548 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 549 | return 0; |
fb03ac01 VS |
550 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
551 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
552 | |
553 | return clock->dot; | |
2177832f SL |
554 | } |
555 | ||
7429e9d4 DV |
556 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
557 | { | |
558 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
559 | } | |
560 | ||
9e2c8475 | 561 | static int i9xx_calc_dpll_params(int refclk, struct dpll *clock) |
2177832f | 562 | { |
7429e9d4 | 563 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 564 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 565 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 566 | return 0; |
fb03ac01 VS |
567 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
568 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
569 | |
570 | return clock->dot; | |
79e53945 JB |
571 | } |
572 | ||
9e2c8475 | 573 | static int vlv_calc_dpll_params(int refclk, struct dpll *clock) |
589eca67 ID |
574 | { |
575 | clock->m = clock->m1 * clock->m2; | |
576 | clock->p = clock->p1 * clock->p2; | |
577 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 578 | return 0; |
589eca67 ID |
579 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
580 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
581 | |
582 | return clock->dot / 5; | |
589eca67 ID |
583 | } |
584 | ||
9e2c8475 | 585 | int chv_calc_dpll_params(int refclk, struct dpll *clock) |
ef9348c8 CML |
586 | { |
587 | clock->m = clock->m1 * clock->m2; | |
588 | clock->p = clock->p1 * clock->p2; | |
589 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 590 | return 0; |
ef9348c8 CML |
591 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
592 | clock->n << 22); | |
593 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
594 | |
595 | return clock->dot / 5; | |
ef9348c8 CML |
596 | } |
597 | ||
7c04d1d9 | 598 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
599 | /** |
600 | * Returns whether the given set of divisors are valid for a given refclk with | |
601 | * the given connectors. | |
602 | */ | |
603 | ||
e2d214ae | 604 | static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv, |
1b6f4958 | 605 | const struct intel_limit *limit, |
9e2c8475 | 606 | const struct dpll *clock) |
79e53945 | 607 | { |
f01b7962 VS |
608 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
609 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 610 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 611 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 612 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 613 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 614 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 615 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 616 | |
e2d214ae | 617 | if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) && |
cc3f90f0 | 618 | !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv)) |
f01b7962 VS |
619 | if (clock->m1 <= clock->m2) |
620 | INTELPllInvalid("m1 <= m2\n"); | |
621 | ||
e2d214ae | 622 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
cc3f90f0 | 623 | !IS_GEN9_LP(dev_priv)) { |
f01b7962 VS |
624 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
625 | INTELPllInvalid("p out of range\n"); | |
626 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
627 | INTELPllInvalid("m out of range\n"); | |
628 | } | |
629 | ||
79e53945 | 630 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 631 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
632 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
633 | * connector, etc., rather than just a single range. | |
634 | */ | |
635 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 636 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
637 | |
638 | return true; | |
639 | } | |
640 | ||
3b1429d9 | 641 | static int |
1b6f4958 | 642 | i9xx_select_p2_div(const struct intel_limit *limit, |
3b1429d9 VS |
643 | const struct intel_crtc_state *crtc_state, |
644 | int target) | |
79e53945 | 645 | { |
3b1429d9 | 646 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 647 | |
2d84d2b3 | 648 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 649 | /* |
a210b028 DV |
650 | * For LVDS just rely on its current settings for dual-channel. |
651 | * We haven't figured out how to reliably set up different | |
652 | * single/dual channel state, if we even can. | |
79e53945 | 653 | */ |
1974cad0 | 654 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 655 | return limit->p2.p2_fast; |
79e53945 | 656 | else |
3b1429d9 | 657 | return limit->p2.p2_slow; |
79e53945 JB |
658 | } else { |
659 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 660 | return limit->p2.p2_slow; |
79e53945 | 661 | else |
3b1429d9 | 662 | return limit->p2.p2_fast; |
79e53945 | 663 | } |
3b1429d9 VS |
664 | } |
665 | ||
70e8aa21 ACO |
666 | /* |
667 | * Returns a set of divisors for the desired target clock with the given | |
668 | * refclk, or FALSE. The returned values represent the clock equation: | |
669 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
670 | * | |
671 | * Target and reference clocks are specified in kHz. | |
672 | * | |
673 | * If match_clock is provided, then best_clock P divider must match the P | |
674 | * divider from @match_clock used for LVDS downclocking. | |
675 | */ | |
3b1429d9 | 676 | static bool |
1b6f4958 | 677 | i9xx_find_best_dpll(const struct intel_limit *limit, |
3b1429d9 | 678 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
679 | int target, int refclk, struct dpll *match_clock, |
680 | struct dpll *best_clock) | |
3b1429d9 VS |
681 | { |
682 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
9e2c8475 | 683 | struct dpll clock; |
3b1429d9 | 684 | int err = target; |
79e53945 | 685 | |
0206e353 | 686 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 687 | |
3b1429d9 VS |
688 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
689 | ||
42158660 ZY |
690 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
691 | clock.m1++) { | |
692 | for (clock.m2 = limit->m2.min; | |
693 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 694 | if (clock.m2 >= clock.m1) |
42158660 ZY |
695 | break; |
696 | for (clock.n = limit->n.min; | |
697 | clock.n <= limit->n.max; clock.n++) { | |
698 | for (clock.p1 = limit->p1.min; | |
699 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
700 | int this_err; |
701 | ||
dccbea3b | 702 | i9xx_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
703 | if (!intel_PLL_is_valid(to_i915(dev), |
704 | limit, | |
ac58c3f0 DV |
705 | &clock)) |
706 | continue; | |
707 | if (match_clock && | |
708 | clock.p != match_clock->p) | |
709 | continue; | |
710 | ||
711 | this_err = abs(clock.dot - target); | |
712 | if (this_err < err) { | |
713 | *best_clock = clock; | |
714 | err = this_err; | |
715 | } | |
716 | } | |
717 | } | |
718 | } | |
719 | } | |
720 | ||
721 | return (err != target); | |
722 | } | |
723 | ||
70e8aa21 ACO |
724 | /* |
725 | * Returns a set of divisors for the desired target clock with the given | |
726 | * refclk, or FALSE. The returned values represent the clock equation: | |
727 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
728 | * | |
729 | * Target and reference clocks are specified in kHz. | |
730 | * | |
731 | * If match_clock is provided, then best_clock P divider must match the P | |
732 | * divider from @match_clock used for LVDS downclocking. | |
733 | */ | |
ac58c3f0 | 734 | static bool |
1b6f4958 | 735 | pnv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 736 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
737 | int target, int refclk, struct dpll *match_clock, |
738 | struct dpll *best_clock) | |
79e53945 | 739 | { |
3b1429d9 | 740 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 741 | struct dpll clock; |
79e53945 JB |
742 | int err = target; |
743 | ||
0206e353 | 744 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 745 | |
3b1429d9 VS |
746 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
747 | ||
42158660 ZY |
748 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
749 | clock.m1++) { | |
750 | for (clock.m2 = limit->m2.min; | |
751 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
752 | for (clock.n = limit->n.min; |
753 | clock.n <= limit->n.max; clock.n++) { | |
754 | for (clock.p1 = limit->p1.min; | |
755 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
756 | int this_err; |
757 | ||
dccbea3b | 758 | pnv_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
759 | if (!intel_PLL_is_valid(to_i915(dev), |
760 | limit, | |
1b894b59 | 761 | &clock)) |
79e53945 | 762 | continue; |
cec2f356 SP |
763 | if (match_clock && |
764 | clock.p != match_clock->p) | |
765 | continue; | |
79e53945 JB |
766 | |
767 | this_err = abs(clock.dot - target); | |
768 | if (this_err < err) { | |
769 | *best_clock = clock; | |
770 | err = this_err; | |
771 | } | |
772 | } | |
773 | } | |
774 | } | |
775 | } | |
776 | ||
777 | return (err != target); | |
778 | } | |
779 | ||
997c030c ACO |
780 | /* |
781 | * Returns a set of divisors for the desired target clock with the given | |
782 | * refclk, or FALSE. The returned values represent the clock equation: | |
783 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
70e8aa21 ACO |
784 | * |
785 | * Target and reference clocks are specified in kHz. | |
786 | * | |
787 | * If match_clock is provided, then best_clock P divider must match the P | |
788 | * divider from @match_clock used for LVDS downclocking. | |
997c030c | 789 | */ |
d4906093 | 790 | static bool |
1b6f4958 | 791 | g4x_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 792 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
793 | int target, int refclk, struct dpll *match_clock, |
794 | struct dpll *best_clock) | |
d4906093 | 795 | { |
3b1429d9 | 796 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 797 | struct dpll clock; |
d4906093 | 798 | int max_n; |
3b1429d9 | 799 | bool found = false; |
6ba770dc AJ |
800 | /* approximately equals target * 0.00585 */ |
801 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
802 | |
803 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
804 | |
805 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
806 | ||
d4906093 | 807 | max_n = limit->n.max; |
f77f13e2 | 808 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 809 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 810 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
811 | for (clock.m1 = limit->m1.max; |
812 | clock.m1 >= limit->m1.min; clock.m1--) { | |
813 | for (clock.m2 = limit->m2.max; | |
814 | clock.m2 >= limit->m2.min; clock.m2--) { | |
815 | for (clock.p1 = limit->p1.max; | |
816 | clock.p1 >= limit->p1.min; clock.p1--) { | |
817 | int this_err; | |
818 | ||
dccbea3b | 819 | i9xx_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
820 | if (!intel_PLL_is_valid(to_i915(dev), |
821 | limit, | |
1b894b59 | 822 | &clock)) |
d4906093 | 823 | continue; |
1b894b59 CW |
824 | |
825 | this_err = abs(clock.dot - target); | |
d4906093 ML |
826 | if (this_err < err_most) { |
827 | *best_clock = clock; | |
828 | err_most = this_err; | |
829 | max_n = clock.n; | |
830 | found = true; | |
831 | } | |
832 | } | |
833 | } | |
834 | } | |
835 | } | |
2c07245f ZW |
836 | return found; |
837 | } | |
838 | ||
d5dd62bd ID |
839 | /* |
840 | * Check if the calculated PLL configuration is more optimal compared to the | |
841 | * best configuration and error found so far. Return the calculated error. | |
842 | */ | |
843 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
9e2c8475 ACO |
844 | const struct dpll *calculated_clock, |
845 | const struct dpll *best_clock, | |
d5dd62bd ID |
846 | unsigned int best_error_ppm, |
847 | unsigned int *error_ppm) | |
848 | { | |
9ca3ba01 ID |
849 | /* |
850 | * For CHV ignore the error and consider only the P value. | |
851 | * Prefer a bigger P value based on HW requirements. | |
852 | */ | |
920a14b2 | 853 | if (IS_CHERRYVIEW(to_i915(dev))) { |
9ca3ba01 ID |
854 | *error_ppm = 0; |
855 | ||
856 | return calculated_clock->p > best_clock->p; | |
857 | } | |
858 | ||
24be4e46 ID |
859 | if (WARN_ON_ONCE(!target_freq)) |
860 | return false; | |
861 | ||
d5dd62bd ID |
862 | *error_ppm = div_u64(1000000ULL * |
863 | abs(target_freq - calculated_clock->dot), | |
864 | target_freq); | |
865 | /* | |
866 | * Prefer a better P value over a better (smaller) error if the error | |
867 | * is small. Ensure this preference for future configurations too by | |
868 | * setting the error to 0. | |
869 | */ | |
870 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
871 | *error_ppm = 0; | |
872 | ||
873 | return true; | |
874 | } | |
875 | ||
876 | return *error_ppm + 10 < best_error_ppm; | |
877 | } | |
878 | ||
65b3d6a9 ACO |
879 | /* |
880 | * Returns a set of divisors for the desired target clock with the given | |
881 | * refclk, or FALSE. The returned values represent the clock equation: | |
882 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
883 | */ | |
a0c4da24 | 884 | static bool |
1b6f4958 | 885 | vlv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 886 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
887 | int target, int refclk, struct dpll *match_clock, |
888 | struct dpll *best_clock) | |
a0c4da24 | 889 | { |
a93e255f | 890 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 891 | struct drm_device *dev = crtc->base.dev; |
9e2c8475 | 892 | struct dpll clock; |
69e4f900 | 893 | unsigned int bestppm = 1000000; |
27e639bf VS |
894 | /* min update 19.2 MHz */ |
895 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 896 | bool found = false; |
a0c4da24 | 897 | |
6b4bf1c4 VS |
898 | target *= 5; /* fast clock */ |
899 | ||
900 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
901 | |
902 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 903 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 904 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 905 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 906 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 907 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 908 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 909 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 910 | unsigned int ppm; |
69e4f900 | 911 | |
6b4bf1c4 VS |
912 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
913 | refclk * clock.m1); | |
914 | ||
dccbea3b | 915 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 916 | |
e2d214ae TU |
917 | if (!intel_PLL_is_valid(to_i915(dev), |
918 | limit, | |
f01b7962 | 919 | &clock)) |
43b0ac53 VS |
920 | continue; |
921 | ||
d5dd62bd ID |
922 | if (!vlv_PLL_is_optimal(dev, target, |
923 | &clock, | |
924 | best_clock, | |
925 | bestppm, &ppm)) | |
926 | continue; | |
6b4bf1c4 | 927 | |
d5dd62bd ID |
928 | *best_clock = clock; |
929 | bestppm = ppm; | |
930 | found = true; | |
a0c4da24 JB |
931 | } |
932 | } | |
933 | } | |
934 | } | |
a0c4da24 | 935 | |
49e497ef | 936 | return found; |
a0c4da24 | 937 | } |
a4fc5ed6 | 938 | |
65b3d6a9 ACO |
939 | /* |
940 | * Returns a set of divisors for the desired target clock with the given | |
941 | * refclk, or FALSE. The returned values represent the clock equation: | |
942 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
943 | */ | |
ef9348c8 | 944 | static bool |
1b6f4958 | 945 | chv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 946 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
947 | int target, int refclk, struct dpll *match_clock, |
948 | struct dpll *best_clock) | |
ef9348c8 | 949 | { |
a93e255f | 950 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 951 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 952 | unsigned int best_error_ppm; |
9e2c8475 | 953 | struct dpll clock; |
ef9348c8 CML |
954 | uint64_t m2; |
955 | int found = false; | |
956 | ||
957 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 958 | best_error_ppm = 1000000; |
ef9348c8 CML |
959 | |
960 | /* | |
961 | * Based on hardware doc, the n always set to 1, and m1 always | |
962 | * set to 2. If requires to support 200Mhz refclk, we need to | |
963 | * revisit this because n may not 1 anymore. | |
964 | */ | |
965 | clock.n = 1, clock.m1 = 2; | |
966 | target *= 5; /* fast clock */ | |
967 | ||
968 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
969 | for (clock.p2 = limit->p2.p2_fast; | |
970 | clock.p2 >= limit->p2.p2_slow; | |
971 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 972 | unsigned int error_ppm; |
ef9348c8 CML |
973 | |
974 | clock.p = clock.p1 * clock.p2; | |
975 | ||
976 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
977 | clock.n) << 22, refclk * clock.m1); | |
978 | ||
979 | if (m2 > INT_MAX/clock.m1) | |
980 | continue; | |
981 | ||
982 | clock.m2 = m2; | |
983 | ||
dccbea3b | 984 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 | 985 | |
e2d214ae | 986 | if (!intel_PLL_is_valid(to_i915(dev), limit, &clock)) |
ef9348c8 CML |
987 | continue; |
988 | ||
9ca3ba01 ID |
989 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
990 | best_error_ppm, &error_ppm)) | |
991 | continue; | |
992 | ||
993 | *best_clock = clock; | |
994 | best_error_ppm = error_ppm; | |
995 | found = true; | |
ef9348c8 CML |
996 | } |
997 | } | |
998 | ||
999 | return found; | |
1000 | } | |
1001 | ||
5ab7b0b7 | 1002 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
9e2c8475 | 1003 | struct dpll *best_clock) |
5ab7b0b7 | 1004 | { |
65b3d6a9 | 1005 | int refclk = 100000; |
1b6f4958 | 1006 | const struct intel_limit *limit = &intel_limits_bxt; |
5ab7b0b7 | 1007 | |
65b3d6a9 | 1008 | return chv_find_best_dpll(limit, crtc_state, |
5ab7b0b7 ID |
1009 | target_clock, refclk, NULL, best_clock); |
1010 | } | |
1011 | ||
525b9311 | 1012 | bool intel_crtc_active(struct intel_crtc *crtc) |
20ddf665 | 1013 | { |
20ddf665 VS |
1014 | /* Be paranoid as we can arrive here with only partial |
1015 | * state retrieved from the hardware during setup. | |
1016 | * | |
241bfc38 | 1017 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
1018 | * as Haswell has gained clock readout/fastboot support. |
1019 | * | |
66e514c1 | 1020 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 1021 | * properly reconstruct framebuffers. |
c3d1f436 MR |
1022 | * |
1023 | * FIXME: The intel_crtc->active here should be switched to | |
1024 | * crtc->state->active once we have proper CRTC states wired up | |
1025 | * for atomic. | |
20ddf665 | 1026 | */ |
525b9311 VS |
1027 | return crtc->active && crtc->base.primary->state->fb && |
1028 | crtc->config->base.adjusted_mode.crtc_clock; | |
20ddf665 VS |
1029 | } |
1030 | ||
a5c961d1 PZ |
1031 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1032 | enum pipe pipe) | |
1033 | { | |
98187836 | 1034 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
a5c961d1 | 1035 | |
e2af48c6 | 1036 | return crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1037 | } |
1038 | ||
6315b5d3 | 1039 | static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe) |
fbf49ea2 | 1040 | { |
f0f59a00 | 1041 | i915_reg_t reg = PIPEDSL(pipe); |
fbf49ea2 VS |
1042 | u32 line1, line2; |
1043 | u32 line_mask; | |
1044 | ||
5db94019 | 1045 | if (IS_GEN2(dev_priv)) |
fbf49ea2 VS |
1046 | line_mask = DSL_LINEMASK_GEN2; |
1047 | else | |
1048 | line_mask = DSL_LINEMASK_GEN3; | |
1049 | ||
1050 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 1051 | msleep(5); |
fbf49ea2 VS |
1052 | line2 = I915_READ(reg) & line_mask; |
1053 | ||
1054 | return line1 == line2; | |
1055 | } | |
1056 | ||
ab7ad7f6 KP |
1057 | /* |
1058 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1059 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1060 | * |
1061 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1062 | * spinning on the vblank interrupt status bit, since we won't actually | |
1063 | * see an interrupt when the pipe is disabled. | |
1064 | * | |
ab7ad7f6 KP |
1065 | * On Gen4 and above: |
1066 | * wait for the pipe register state bit to turn off | |
1067 | * | |
1068 | * Otherwise: | |
1069 | * wait for the display line value to settle (it usually | |
1070 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1071 | * |
9d0498a2 | 1072 | */ |
575f7ab7 | 1073 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1074 | { |
6315b5d3 | 1075 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6e3c9717 | 1076 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1077 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 | 1078 | |
6315b5d3 | 1079 | if (INTEL_GEN(dev_priv) >= 4) { |
f0f59a00 | 1080 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1081 | |
1082 | /* Wait for the Pipe State to go off */ | |
b8511f53 CW |
1083 | if (intel_wait_for_register(dev_priv, |
1084 | reg, I965_PIPECONF_ACTIVE, 0, | |
1085 | 100)) | |
284637d9 | 1086 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1087 | } else { |
ab7ad7f6 | 1088 | /* Wait for the display line to settle */ |
6315b5d3 | 1089 | if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100)) |
284637d9 | 1090 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1091 | } |
79e53945 JB |
1092 | } |
1093 | ||
b24e7179 | 1094 | /* Only for pre-ILK configs */ |
55607e8a DV |
1095 | void assert_pll(struct drm_i915_private *dev_priv, |
1096 | enum pipe pipe, bool state) | |
b24e7179 | 1097 | { |
b24e7179 JB |
1098 | u32 val; |
1099 | bool cur_state; | |
1100 | ||
649636ef | 1101 | val = I915_READ(DPLL(pipe)); |
b24e7179 | 1102 | cur_state = !!(val & DPLL_VCO_ENABLE); |
e2c719b7 | 1103 | I915_STATE_WARN(cur_state != state, |
b24e7179 | 1104 | "PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1105 | onoff(state), onoff(cur_state)); |
b24e7179 | 1106 | } |
b24e7179 | 1107 | |
23538ef1 | 1108 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
8563b1e8 | 1109 | void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) |
23538ef1 JN |
1110 | { |
1111 | u32 val; | |
1112 | bool cur_state; | |
1113 | ||
a580516d | 1114 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1115 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1116 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1117 | |
1118 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1119 | I915_STATE_WARN(cur_state != state, |
23538ef1 | 1120 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1121 | onoff(state), onoff(cur_state)); |
23538ef1 | 1122 | } |
23538ef1 | 1123 | |
040484af JB |
1124 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
1125 | enum pipe pipe, bool state) | |
1126 | { | |
040484af | 1127 | bool cur_state; |
ad80a810 PZ |
1128 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1129 | pipe); | |
040484af | 1130 | |
2d1fe073 | 1131 | if (HAS_DDI(dev_priv)) { |
affa9354 | 1132 | /* DDI does not have a specific FDI_TX register */ |
649636ef | 1133 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
ad80a810 | 1134 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 | 1135 | } else { |
649636ef | 1136 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
bf507ef7 ED |
1137 | cur_state = !!(val & FDI_TX_ENABLE); |
1138 | } | |
e2c719b7 | 1139 | I915_STATE_WARN(cur_state != state, |
040484af | 1140 | "FDI TX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1141 | onoff(state), onoff(cur_state)); |
040484af JB |
1142 | } |
1143 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1144 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1145 | ||
1146 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1147 | enum pipe pipe, bool state) | |
1148 | { | |
040484af JB |
1149 | u32 val; |
1150 | bool cur_state; | |
1151 | ||
649636ef | 1152 | val = I915_READ(FDI_RX_CTL(pipe)); |
d63fa0dc | 1153 | cur_state = !!(val & FDI_RX_ENABLE); |
e2c719b7 | 1154 | I915_STATE_WARN(cur_state != state, |
040484af | 1155 | "FDI RX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1156 | onoff(state), onoff(cur_state)); |
040484af JB |
1157 | } |
1158 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1159 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1160 | ||
1161 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1162 | enum pipe pipe) | |
1163 | { | |
040484af JB |
1164 | u32 val; |
1165 | ||
1166 | /* ILK FDI PLL is always enabled */ | |
7e22dbbb | 1167 | if (IS_GEN5(dev_priv)) |
040484af JB |
1168 | return; |
1169 | ||
bf507ef7 | 1170 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
2d1fe073 | 1171 | if (HAS_DDI(dev_priv)) |
bf507ef7 ED |
1172 | return; |
1173 | ||
649636ef | 1174 | val = I915_READ(FDI_TX_CTL(pipe)); |
e2c719b7 | 1175 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1176 | } |
1177 | ||
55607e8a DV |
1178 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1179 | enum pipe pipe, bool state) | |
040484af | 1180 | { |
040484af | 1181 | u32 val; |
55607e8a | 1182 | bool cur_state; |
040484af | 1183 | |
649636ef | 1184 | val = I915_READ(FDI_RX_CTL(pipe)); |
55607e8a | 1185 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1186 | I915_STATE_WARN(cur_state != state, |
55607e8a | 1187 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
87ad3212 | 1188 | onoff(state), onoff(cur_state)); |
040484af JB |
1189 | } |
1190 | ||
4f8036a2 | 1191 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe) |
ea0760cf | 1192 | { |
f0f59a00 | 1193 | i915_reg_t pp_reg; |
ea0760cf JB |
1194 | u32 val; |
1195 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1196 | bool locked = true; |
ea0760cf | 1197 | |
4f8036a2 | 1198 | if (WARN_ON(HAS_DDI(dev_priv))) |
bedd4dba JN |
1199 | return; |
1200 | ||
4f8036a2 | 1201 | if (HAS_PCH_SPLIT(dev_priv)) { |
bedd4dba JN |
1202 | u32 port_sel; |
1203 | ||
44cb734c ID |
1204 | pp_reg = PP_CONTROL(0); |
1205 | port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; | |
bedd4dba JN |
1206 | |
1207 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1208 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1209 | panel_pipe = PIPE_B; | |
1210 | /* XXX: else fix for eDP */ | |
4f8036a2 | 1211 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
bedd4dba | 1212 | /* presumably write lock depends on pipe, not port select */ |
44cb734c | 1213 | pp_reg = PP_CONTROL(pipe); |
bedd4dba | 1214 | panel_pipe = pipe; |
ea0760cf | 1215 | } else { |
44cb734c | 1216 | pp_reg = PP_CONTROL(0); |
bedd4dba JN |
1217 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1218 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1219 | } |
1220 | ||
1221 | val = I915_READ(pp_reg); | |
1222 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1223 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1224 | locked = false; |
1225 | ||
e2c719b7 | 1226 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1227 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1228 | pipe_name(pipe)); |
ea0760cf JB |
1229 | } |
1230 | ||
93ce0ba6 JN |
1231 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1232 | enum pipe pipe, bool state) | |
1233 | { | |
93ce0ba6 JN |
1234 | bool cur_state; |
1235 | ||
2a307c2e | 1236 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) |
0b87c24e | 1237 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
d9d82081 | 1238 | else |
5efb3e28 | 1239 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1240 | |
e2c719b7 | 1241 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 | 1242 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1243 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
93ce0ba6 JN |
1244 | } |
1245 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1246 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1247 | ||
b840d907 JB |
1248 | void assert_pipe(struct drm_i915_private *dev_priv, |
1249 | enum pipe pipe, bool state) | |
b24e7179 | 1250 | { |
63d7bbe9 | 1251 | bool cur_state; |
702e7a56 PZ |
1252 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1253 | pipe); | |
4feed0eb | 1254 | enum intel_display_power_domain power_domain; |
b24e7179 | 1255 | |
b6b5d049 VS |
1256 | /* if we need the pipe quirk it must be always on */ |
1257 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1258 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1259 | state = true; |
1260 | ||
4feed0eb ID |
1261 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); |
1262 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
649636ef | 1263 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
69310161 | 1264 | cur_state = !!(val & PIPECONF_ENABLE); |
4feed0eb ID |
1265 | |
1266 | intel_display_power_put(dev_priv, power_domain); | |
1267 | } else { | |
1268 | cur_state = false; | |
69310161 PZ |
1269 | } |
1270 | ||
e2c719b7 | 1271 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1272 | "pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1273 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1274 | } |
1275 | ||
931872fc CW |
1276 | static void assert_plane(struct drm_i915_private *dev_priv, |
1277 | enum plane plane, bool state) | |
b24e7179 | 1278 | { |
b24e7179 | 1279 | u32 val; |
931872fc | 1280 | bool cur_state; |
b24e7179 | 1281 | |
649636ef | 1282 | val = I915_READ(DSPCNTR(plane)); |
931872fc | 1283 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1284 | I915_STATE_WARN(cur_state != state, |
931872fc | 1285 | "plane %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1286 | plane_name(plane), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1287 | } |
1288 | ||
931872fc CW |
1289 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1290 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1291 | ||
b24e7179 JB |
1292 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1293 | enum pipe pipe) | |
1294 | { | |
649636ef | 1295 | int i; |
b24e7179 | 1296 | |
653e1026 | 1297 | /* Primary planes are fixed to pipes on gen4+ */ |
6315b5d3 | 1298 | if (INTEL_GEN(dev_priv) >= 4) { |
649636ef | 1299 | u32 val = I915_READ(DSPCNTR(pipe)); |
e2c719b7 | 1300 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1301 | "plane %c assertion failure, should be disabled but not\n", |
1302 | plane_name(pipe)); | |
19ec1358 | 1303 | return; |
28c05794 | 1304 | } |
19ec1358 | 1305 | |
b24e7179 | 1306 | /* Need to check both planes against the pipe */ |
055e393f | 1307 | for_each_pipe(dev_priv, i) { |
649636ef VS |
1308 | u32 val = I915_READ(DSPCNTR(i)); |
1309 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
b24e7179 | 1310 | DISPPLANE_SEL_PIPE_SHIFT; |
e2c719b7 | 1311 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1312 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1313 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1314 | } |
1315 | } | |
1316 | ||
19332d7a JB |
1317 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1318 | enum pipe pipe) | |
1319 | { | |
649636ef | 1320 | int sprite; |
19332d7a | 1321 | |
6315b5d3 | 1322 | if (INTEL_GEN(dev_priv) >= 9) { |
3bdcfc0c | 1323 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1324 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1325 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1326 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1327 | sprite, pipe_name(pipe)); | |
1328 | } | |
920a14b2 | 1329 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
3bdcfc0c | 1330 | for_each_sprite(dev_priv, pipe, sprite) { |
83c04a62 | 1331 | u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite)); |
e2c719b7 | 1332 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1333 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1334 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef | 1335 | } |
6315b5d3 | 1336 | } else if (INTEL_GEN(dev_priv) >= 7) { |
649636ef | 1337 | u32 val = I915_READ(SPRCTL(pipe)); |
e2c719b7 | 1338 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1339 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1340 | plane_name(pipe), pipe_name(pipe)); |
6315b5d3 | 1341 | } else if (INTEL_GEN(dev_priv) >= 5) { |
649636ef | 1342 | u32 val = I915_READ(DVSCNTR(pipe)); |
e2c719b7 | 1343 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1344 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1345 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1346 | } |
1347 | } | |
1348 | ||
08c71e5e VS |
1349 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1350 | { | |
e2c719b7 | 1351 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1352 | drm_crtc_vblank_put(crtc); |
1353 | } | |
1354 | ||
7abd4b35 ACO |
1355 | void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1356 | enum pipe pipe) | |
92f2584a | 1357 | { |
92f2584a JB |
1358 | u32 val; |
1359 | bool enabled; | |
1360 | ||
649636ef | 1361 | val = I915_READ(PCH_TRANSCONF(pipe)); |
92f2584a | 1362 | enabled = !!(val & TRANS_ENABLE); |
e2c719b7 | 1363 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1364 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1365 | pipe_name(pipe)); | |
92f2584a JB |
1366 | } |
1367 | ||
4e634389 KP |
1368 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1369 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1370 | { |
1371 | if ((val & DP_PORT_EN) == 0) | |
1372 | return false; | |
1373 | ||
2d1fe073 | 1374 | if (HAS_PCH_CPT(dev_priv)) { |
f0f59a00 | 1375 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
f0575e92 KP |
1376 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1377 | return false; | |
2d1fe073 | 1378 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1379 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) |
1380 | return false; | |
f0575e92 KP |
1381 | } else { |
1382 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1383 | return false; | |
1384 | } | |
1385 | return true; | |
1386 | } | |
1387 | ||
1519b995 KP |
1388 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1389 | enum pipe pipe, u32 val) | |
1390 | { | |
dc0fa718 | 1391 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1392 | return false; |
1393 | ||
2d1fe073 | 1394 | if (HAS_PCH_CPT(dev_priv)) { |
dc0fa718 | 1395 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1396 | return false; |
2d1fe073 | 1397 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1398 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) |
1399 | return false; | |
1519b995 | 1400 | } else { |
dc0fa718 | 1401 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1402 | return false; |
1403 | } | |
1404 | return true; | |
1405 | } | |
1406 | ||
1407 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1408 | enum pipe pipe, u32 val) | |
1409 | { | |
1410 | if ((val & LVDS_PORT_EN) == 0) | |
1411 | return false; | |
1412 | ||
2d1fe073 | 1413 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1414 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1415 | return false; | |
1416 | } else { | |
1417 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1418 | return false; | |
1419 | } | |
1420 | return true; | |
1421 | } | |
1422 | ||
1423 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1424 | enum pipe pipe, u32 val) | |
1425 | { | |
1426 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1427 | return false; | |
2d1fe073 | 1428 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1429 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1430 | return false; | |
1431 | } else { | |
1432 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1433 | return false; | |
1434 | } | |
1435 | return true; | |
1436 | } | |
1437 | ||
291906f1 | 1438 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
1439 | enum pipe pipe, i915_reg_t reg, |
1440 | u32 port_sel) | |
291906f1 | 1441 | { |
47a05eca | 1442 | u32 val = I915_READ(reg); |
e2c719b7 | 1443 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1444 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1445 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1446 | |
2d1fe073 | 1447 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1448 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1449 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1450 | } |
1451 | ||
1452 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
f0f59a00 | 1453 | enum pipe pipe, i915_reg_t reg) |
291906f1 | 1454 | { |
47a05eca | 1455 | u32 val = I915_READ(reg); |
e2c719b7 | 1456 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1457 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1458 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1459 | |
2d1fe073 | 1460 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1461 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1462 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1463 | } |
1464 | ||
1465 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1466 | enum pipe pipe) | |
1467 | { | |
291906f1 | 1468 | u32 val; |
291906f1 | 1469 | |
f0575e92 KP |
1470 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1471 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1472 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 | 1473 | |
649636ef | 1474 | val = I915_READ(PCH_ADPA); |
e2c719b7 | 1475 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1476 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1477 | pipe_name(pipe)); |
291906f1 | 1478 | |
649636ef | 1479 | val = I915_READ(PCH_LVDS); |
e2c719b7 | 1480 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1481 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1482 | pipe_name(pipe)); |
291906f1 | 1483 | |
e2debe91 PZ |
1484 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1485 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1486 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1487 | } |
1488 | ||
cd2d34d9 VS |
1489 | static void _vlv_enable_pll(struct intel_crtc *crtc, |
1490 | const struct intel_crtc_state *pipe_config) | |
1491 | { | |
1492 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1493 | enum pipe pipe = crtc->pipe; | |
1494 | ||
1495 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); | |
1496 | POSTING_READ(DPLL(pipe)); | |
1497 | udelay(150); | |
1498 | ||
2c30b43b CW |
1499 | if (intel_wait_for_register(dev_priv, |
1500 | DPLL(pipe), | |
1501 | DPLL_LOCK_VLV, | |
1502 | DPLL_LOCK_VLV, | |
1503 | 1)) | |
cd2d34d9 VS |
1504 | DRM_ERROR("DPLL %d failed to lock\n", pipe); |
1505 | } | |
1506 | ||
d288f65f | 1507 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1508 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1509 | { |
cd2d34d9 | 1510 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1511 | enum pipe pipe = crtc->pipe; |
87442f73 | 1512 | |
8bd3f301 | 1513 | assert_pipe_disabled(dev_priv, pipe); |
87442f73 | 1514 | |
87442f73 | 1515 | /* PLL is protected by panel, make sure we can write it */ |
7d1a83cb | 1516 | assert_panel_unlocked(dev_priv, pipe); |
87442f73 | 1517 | |
cd2d34d9 VS |
1518 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) |
1519 | _vlv_enable_pll(crtc, pipe_config); | |
426115cf | 1520 | |
8bd3f301 VS |
1521 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
1522 | POSTING_READ(DPLL_MD(pipe)); | |
87442f73 DV |
1523 | } |
1524 | ||
cd2d34d9 VS |
1525 | |
1526 | static void _chv_enable_pll(struct intel_crtc *crtc, | |
1527 | const struct intel_crtc_state *pipe_config) | |
9d556c99 | 1528 | { |
cd2d34d9 | 1529 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1530 | enum pipe pipe = crtc->pipe; |
9d556c99 | 1531 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9d556c99 CML |
1532 | u32 tmp; |
1533 | ||
a580516d | 1534 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1535 | |
1536 | /* Enable back the 10bit clock to display controller */ | |
1537 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1538 | tmp |= DPIO_DCLKP_EN; | |
1539 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1540 | ||
54433e91 VS |
1541 | mutex_unlock(&dev_priv->sb_lock); |
1542 | ||
9d556c99 CML |
1543 | /* |
1544 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1545 | */ | |
1546 | udelay(1); | |
1547 | ||
1548 | /* Enable PLL */ | |
d288f65f | 1549 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1550 | |
1551 | /* Check PLL is locked */ | |
6b18826a CW |
1552 | if (intel_wait_for_register(dev_priv, |
1553 | DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV, | |
1554 | 1)) | |
9d556c99 | 1555 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
cd2d34d9 VS |
1556 | } |
1557 | ||
1558 | static void chv_enable_pll(struct intel_crtc *crtc, | |
1559 | const struct intel_crtc_state *pipe_config) | |
1560 | { | |
1561 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1562 | enum pipe pipe = crtc->pipe; | |
1563 | ||
1564 | assert_pipe_disabled(dev_priv, pipe); | |
1565 | ||
1566 | /* PLL is protected by panel, make sure we can write it */ | |
1567 | assert_panel_unlocked(dev_priv, pipe); | |
1568 | ||
1569 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) | |
1570 | _chv_enable_pll(crtc, pipe_config); | |
9d556c99 | 1571 | |
c231775c VS |
1572 | if (pipe != PIPE_A) { |
1573 | /* | |
1574 | * WaPixelRepeatModeFixForC0:chv | |
1575 | * | |
1576 | * DPLLCMD is AWOL. Use chicken bits to propagate | |
1577 | * the value from DPLLBMD to either pipe B or C. | |
1578 | */ | |
1579 | I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C); | |
1580 | I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md); | |
1581 | I915_WRITE(CBR4_VLV, 0); | |
1582 | dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; | |
1583 | ||
1584 | /* | |
1585 | * DPLLB VGA mode also seems to cause problems. | |
1586 | * We should always have it disabled. | |
1587 | */ | |
1588 | WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); | |
1589 | } else { | |
1590 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); | |
1591 | POSTING_READ(DPLL_MD(pipe)); | |
1592 | } | |
9d556c99 CML |
1593 | } |
1594 | ||
6315b5d3 | 1595 | static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv) |
1c4e0274 VS |
1596 | { |
1597 | struct intel_crtc *crtc; | |
1598 | int count = 0; | |
1599 | ||
6315b5d3 | 1600 | for_each_intel_crtc(&dev_priv->drm, crtc) { |
3538b9df | 1601 | count += crtc->base.state->active && |
2d84d2b3 VS |
1602 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO); |
1603 | } | |
1c4e0274 VS |
1604 | |
1605 | return count; | |
1606 | } | |
1607 | ||
66e3d5c0 | 1608 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1609 | { |
6315b5d3 | 1610 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
f0f59a00 | 1611 | i915_reg_t reg = DPLL(crtc->pipe); |
6e3c9717 | 1612 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1613 | |
66e3d5c0 | 1614 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1615 | |
63d7bbe9 | 1616 | /* PLL is protected by panel, make sure we can write it */ |
50a0bc90 | 1617 | if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv)) |
66e3d5c0 | 1618 | assert_panel_unlocked(dev_priv, crtc->pipe); |
63d7bbe9 | 1619 | |
1c4e0274 | 1620 | /* Enable DVO 2x clock on both PLLs if necessary */ |
6315b5d3 | 1621 | if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) { |
1c4e0274 VS |
1622 | /* |
1623 | * It appears to be important that we don't enable this | |
1624 | * for the current pipe before otherwise configuring the | |
1625 | * PLL. No idea how this should be handled if multiple | |
1626 | * DVO outputs are enabled simultaneosly. | |
1627 | */ | |
1628 | dpll |= DPLL_DVO_2X_MODE; | |
1629 | I915_WRITE(DPLL(!crtc->pipe), | |
1630 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1631 | } | |
66e3d5c0 | 1632 | |
c2b63374 VS |
1633 | /* |
1634 | * Apparently we need to have VGA mode enabled prior to changing | |
1635 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1636 | * dividers, even though the register value does change. | |
1637 | */ | |
1638 | I915_WRITE(reg, 0); | |
1639 | ||
8e7a65aa VS |
1640 | I915_WRITE(reg, dpll); |
1641 | ||
66e3d5c0 DV |
1642 | /* Wait for the clocks to stabilize. */ |
1643 | POSTING_READ(reg); | |
1644 | udelay(150); | |
1645 | ||
6315b5d3 | 1646 | if (INTEL_GEN(dev_priv) >= 4) { |
66e3d5c0 | 1647 | I915_WRITE(DPLL_MD(crtc->pipe), |
6e3c9717 | 1648 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1649 | } else { |
1650 | /* The pixel multiplier can only be updated once the | |
1651 | * DPLL is enabled and the clocks are stable. | |
1652 | * | |
1653 | * So write it again. | |
1654 | */ | |
1655 | I915_WRITE(reg, dpll); | |
1656 | } | |
63d7bbe9 JB |
1657 | |
1658 | /* We do this three times for luck */ | |
66e3d5c0 | 1659 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1660 | POSTING_READ(reg); |
1661 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1662 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1663 | POSTING_READ(reg); |
1664 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1665 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1666 | POSTING_READ(reg); |
1667 | udelay(150); /* wait for warmup */ | |
1668 | } | |
1669 | ||
1670 | /** | |
50b44a44 | 1671 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1672 | * @dev_priv: i915 private structure |
1673 | * @pipe: pipe PLL to disable | |
1674 | * | |
1675 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1676 | * | |
1677 | * Note! This is for pre-ILK only. | |
1678 | */ | |
1c4e0274 | 1679 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1680 | { |
6315b5d3 | 1681 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1c4e0274 VS |
1682 | enum pipe pipe = crtc->pipe; |
1683 | ||
1684 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
50a0bc90 | 1685 | if (IS_I830(dev_priv) && |
2d84d2b3 | 1686 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) && |
6315b5d3 | 1687 | !intel_num_dvo_pipes(dev_priv)) { |
1c4e0274 VS |
1688 | I915_WRITE(DPLL(PIPE_B), |
1689 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1690 | I915_WRITE(DPLL(PIPE_A), | |
1691 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1692 | } | |
1693 | ||
b6b5d049 VS |
1694 | /* Don't disable pipe or pipe PLLs if needed */ |
1695 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1696 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1697 | return; |
1698 | ||
1699 | /* Make sure the pipe isn't still relying on us */ | |
1700 | assert_pipe_disabled(dev_priv, pipe); | |
1701 | ||
b8afb911 | 1702 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1703 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1704 | } |
1705 | ||
f6071166 JB |
1706 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1707 | { | |
b8afb911 | 1708 | u32 val; |
f6071166 JB |
1709 | |
1710 | /* Make sure the pipe isn't still relying on us */ | |
1711 | assert_pipe_disabled(dev_priv, pipe); | |
1712 | ||
03ed5cbf VS |
1713 | val = DPLL_INTEGRATED_REF_CLK_VLV | |
1714 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
1715 | if (pipe != PIPE_A) | |
1716 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1717 | ||
f6071166 JB |
1718 | I915_WRITE(DPLL(pipe), val); |
1719 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1720 | } |
1721 | ||
1722 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1723 | { | |
d752048d | 1724 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1725 | u32 val; |
1726 | ||
a11b0703 VS |
1727 | /* Make sure the pipe isn't still relying on us */ |
1728 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1729 | |
60bfe44f VS |
1730 | val = DPLL_SSC_REF_CLK_CHV | |
1731 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1732 | if (pipe != PIPE_A) |
1733 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
03ed5cbf | 1734 | |
a11b0703 VS |
1735 | I915_WRITE(DPLL(pipe), val); |
1736 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1737 | |
a580516d | 1738 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1739 | |
1740 | /* Disable 10bit clock to display controller */ | |
1741 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1742 | val &= ~DPIO_DCLKP_EN; | |
1743 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1744 | ||
a580516d | 1745 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1746 | } |
1747 | ||
e4607fcf | 1748 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1749 | struct intel_digital_port *dport, |
1750 | unsigned int expected_mask) | |
89b667f8 JB |
1751 | { |
1752 | u32 port_mask; | |
f0f59a00 | 1753 | i915_reg_t dpll_reg; |
89b667f8 | 1754 | |
e4607fcf CML |
1755 | switch (dport->port) { |
1756 | case PORT_B: | |
89b667f8 | 1757 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1758 | dpll_reg = DPLL(0); |
e4607fcf CML |
1759 | break; |
1760 | case PORT_C: | |
89b667f8 | 1761 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1762 | dpll_reg = DPLL(0); |
9b6de0a1 | 1763 | expected_mask <<= 4; |
00fc31b7 CML |
1764 | break; |
1765 | case PORT_D: | |
1766 | port_mask = DPLL_PORTD_READY_MASK; | |
1767 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1768 | break; |
1769 | default: | |
1770 | BUG(); | |
1771 | } | |
89b667f8 | 1772 | |
370004d3 CW |
1773 | if (intel_wait_for_register(dev_priv, |
1774 | dpll_reg, port_mask, expected_mask, | |
1775 | 1000)) | |
9b6de0a1 VS |
1776 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", |
1777 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1778 | } |
1779 | ||
b8a4f404 PZ |
1780 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1781 | enum pipe pipe) | |
040484af | 1782 | { |
98187836 VS |
1783 | struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv, |
1784 | pipe); | |
f0f59a00 VS |
1785 | i915_reg_t reg; |
1786 | uint32_t val, pipeconf_val; | |
040484af | 1787 | |
040484af | 1788 | /* Make sure PCH DPLL is enabled */ |
8106ddbd | 1789 | assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll); |
040484af JB |
1790 | |
1791 | /* FDI must be feeding us bits for PCH ports */ | |
1792 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1793 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1794 | ||
6e266956 | 1795 | if (HAS_PCH_CPT(dev_priv)) { |
23670b32 DV |
1796 | /* Workaround: Set the timing override bit before enabling the |
1797 | * pch transcoder. */ | |
1798 | reg = TRANS_CHICKEN2(pipe); | |
1799 | val = I915_READ(reg); | |
1800 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1801 | I915_WRITE(reg, val); | |
59c859d6 | 1802 | } |
23670b32 | 1803 | |
ab9412ba | 1804 | reg = PCH_TRANSCONF(pipe); |
040484af | 1805 | val = I915_READ(reg); |
5f7f726d | 1806 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c | 1807 | |
2d1fe073 | 1808 | if (HAS_PCH_IBX(dev_priv)) { |
e9bcff5c | 1809 | /* |
c5de7c6f VS |
1810 | * Make the BPC in transcoder be consistent with |
1811 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1812 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1813 | */ |
dfd07d72 | 1814 | val &= ~PIPECONF_BPC_MASK; |
2d84d2b3 | 1815 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI)) |
c5de7c6f VS |
1816 | val |= PIPECONF_8BPC; |
1817 | else | |
1818 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1819 | } |
5f7f726d PZ |
1820 | |
1821 | val &= ~TRANS_INTERLACE_MASK; | |
1822 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
2d1fe073 | 1823 | if (HAS_PCH_IBX(dev_priv) && |
2d84d2b3 | 1824 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
1825 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1826 | else | |
1827 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1828 | else |
1829 | val |= TRANS_PROGRESSIVE; | |
1830 | ||
040484af | 1831 | I915_WRITE(reg, val | TRANS_ENABLE); |
650fbd84 CW |
1832 | if (intel_wait_for_register(dev_priv, |
1833 | reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE, | |
1834 | 100)) | |
4bb6f1f3 | 1835 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1836 | } |
1837 | ||
8fb033d7 | 1838 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1839 | enum transcoder cpu_transcoder) |
040484af | 1840 | { |
8fb033d7 | 1841 | u32 val, pipeconf_val; |
8fb033d7 | 1842 | |
8fb033d7 | 1843 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1844 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1845 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1846 | |
223a6fdf | 1847 | /* Workaround: set timing override bit. */ |
36c0d0cf | 1848 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1849 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1850 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 1851 | |
25f3ef11 | 1852 | val = TRANS_ENABLE; |
937bb610 | 1853 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1854 | |
9a76b1c6 PZ |
1855 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1856 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1857 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1858 | else |
1859 | val |= TRANS_PROGRESSIVE; | |
1860 | ||
ab9412ba | 1861 | I915_WRITE(LPT_TRANSCONF, val); |
d9f96244 CW |
1862 | if (intel_wait_for_register(dev_priv, |
1863 | LPT_TRANSCONF, | |
1864 | TRANS_STATE_ENABLE, | |
1865 | TRANS_STATE_ENABLE, | |
1866 | 100)) | |
937bb610 | 1867 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1868 | } |
1869 | ||
b8a4f404 PZ |
1870 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1871 | enum pipe pipe) | |
040484af | 1872 | { |
f0f59a00 VS |
1873 | i915_reg_t reg; |
1874 | uint32_t val; | |
040484af JB |
1875 | |
1876 | /* FDI relies on the transcoder */ | |
1877 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1878 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1879 | ||
291906f1 JB |
1880 | /* Ports must be off as well */ |
1881 | assert_pch_ports_disabled(dev_priv, pipe); | |
1882 | ||
ab9412ba | 1883 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1884 | val = I915_READ(reg); |
1885 | val &= ~TRANS_ENABLE; | |
1886 | I915_WRITE(reg, val); | |
1887 | /* wait for PCH transcoder off, transcoder state */ | |
a7d04662 CW |
1888 | if (intel_wait_for_register(dev_priv, |
1889 | reg, TRANS_STATE_ENABLE, 0, | |
1890 | 50)) | |
4bb6f1f3 | 1891 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 | 1892 | |
6e266956 | 1893 | if (HAS_PCH_CPT(dev_priv)) { |
23670b32 DV |
1894 | /* Workaround: Clear the timing override chicken bit again. */ |
1895 | reg = TRANS_CHICKEN2(pipe); | |
1896 | val = I915_READ(reg); | |
1897 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1898 | I915_WRITE(reg, val); | |
1899 | } | |
040484af JB |
1900 | } |
1901 | ||
b7076546 | 1902 | void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1903 | { |
8fb033d7 PZ |
1904 | u32 val; |
1905 | ||
ab9412ba | 1906 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1907 | val &= ~TRANS_ENABLE; |
ab9412ba | 1908 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1909 | /* wait for PCH transcoder off, transcoder state */ |
dfdb4749 CW |
1910 | if (intel_wait_for_register(dev_priv, |
1911 | LPT_TRANSCONF, TRANS_STATE_ENABLE, 0, | |
1912 | 50)) | |
8a52fd9f | 1913 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1914 | |
1915 | /* Workaround: clear timing override bit. */ | |
36c0d0cf | 1916 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1917 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1918 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
1919 | } |
1920 | ||
65f2130c VS |
1921 | enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc) |
1922 | { | |
1923 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1924 | ||
1925 | WARN_ON(!crtc->config->has_pch_encoder); | |
1926 | ||
1927 | if (HAS_PCH_LPT(dev_priv)) | |
1928 | return TRANSCODER_A; | |
1929 | else | |
1930 | return (enum transcoder) crtc->pipe; | |
1931 | } | |
1932 | ||
b24e7179 | 1933 | /** |
309cfea8 | 1934 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 1935 | * @crtc: crtc responsible for the pipe |
b24e7179 | 1936 | * |
0372264a | 1937 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 1938 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 1939 | */ |
e1fdc473 | 1940 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1941 | { |
0372264a | 1942 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1943 | struct drm_i915_private *dev_priv = to_i915(dev); |
0372264a | 1944 | enum pipe pipe = crtc->pipe; |
1a70a728 | 1945 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
f0f59a00 | 1946 | i915_reg_t reg; |
b24e7179 JB |
1947 | u32 val; |
1948 | ||
9e2ee2dd VS |
1949 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
1950 | ||
58c6eaa2 | 1951 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 1952 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
1953 | assert_sprites_disabled(dev_priv, pipe); |
1954 | ||
b24e7179 JB |
1955 | /* |
1956 | * A pipe without a PLL won't actually be able to drive bits from | |
1957 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1958 | * need the check. | |
1959 | */ | |
09fa8bb9 | 1960 | if (HAS_GMCH_DISPLAY(dev_priv)) { |
d7edc4e5 | 1961 | if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
1962 | assert_dsi_pll_enabled(dev_priv); |
1963 | else | |
1964 | assert_pll_enabled(dev_priv, pipe); | |
09fa8bb9 | 1965 | } else { |
6e3c9717 | 1966 | if (crtc->config->has_pch_encoder) { |
040484af | 1967 | /* if driving the PCH, we need FDI enabled */ |
65f2130c VS |
1968 | assert_fdi_rx_pll_enabled(dev_priv, |
1969 | (enum pipe) intel_crtc_pch_transcoder(crtc)); | |
1a240d4d DV |
1970 | assert_fdi_tx_pll_enabled(dev_priv, |
1971 | (enum pipe) cpu_transcoder); | |
040484af JB |
1972 | } |
1973 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1974 | } | |
b24e7179 | 1975 | |
702e7a56 | 1976 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1977 | val = I915_READ(reg); |
7ad25d48 | 1978 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
1979 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
1980 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 1981 | return; |
7ad25d48 | 1982 | } |
00d70b15 CW |
1983 | |
1984 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 1985 | POSTING_READ(reg); |
b7792d8b VS |
1986 | |
1987 | /* | |
1988 | * Until the pipe starts DSL will read as 0, which would cause | |
1989 | * an apparent vblank timestamp jump, which messes up also the | |
1990 | * frame count when it's derived from the timestamps. So let's | |
1991 | * wait for the pipe to start properly before we call | |
1992 | * drm_crtc_vblank_on() | |
1993 | */ | |
1994 | if (dev->max_vblank_count == 0 && | |
1995 | wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50)) | |
1996 | DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe)); | |
b24e7179 JB |
1997 | } |
1998 | ||
1999 | /** | |
309cfea8 | 2000 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2001 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2002 | * |
575f7ab7 VS |
2003 | * Disable the pipe of @crtc, making sure that various hardware |
2004 | * specific requirements are met, if applicable, e.g. plane | |
2005 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2006 | * |
2007 | * Will wait until the pipe has shut down before returning. | |
2008 | */ | |
575f7ab7 | 2009 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2010 | { |
fac5e23e | 2011 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6e3c9717 | 2012 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2013 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 2014 | i915_reg_t reg; |
b24e7179 JB |
2015 | u32 val; |
2016 | ||
9e2ee2dd VS |
2017 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
2018 | ||
b24e7179 JB |
2019 | /* |
2020 | * Make sure planes won't keep trying to pump pixels to us, | |
2021 | * or we might hang the display. | |
2022 | */ | |
2023 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2024 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2025 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2026 | |
702e7a56 | 2027 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2028 | val = I915_READ(reg); |
00d70b15 CW |
2029 | if ((val & PIPECONF_ENABLE) == 0) |
2030 | return; | |
2031 | ||
67adc644 VS |
2032 | /* |
2033 | * Double wide has implications for planes | |
2034 | * so best keep it disabled when not needed. | |
2035 | */ | |
6e3c9717 | 2036 | if (crtc->config->double_wide) |
67adc644 VS |
2037 | val &= ~PIPECONF_DOUBLE_WIDE; |
2038 | ||
2039 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2040 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2041 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2042 | val &= ~PIPECONF_ENABLE; |
2043 | ||
2044 | I915_WRITE(reg, val); | |
2045 | if ((val & PIPECONF_ENABLE) == 0) | |
2046 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2047 | } |
2048 | ||
832be82f VS |
2049 | static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) |
2050 | { | |
2051 | return IS_GEN2(dev_priv) ? 2048 : 4096; | |
2052 | } | |
2053 | ||
27ba3910 VS |
2054 | static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv, |
2055 | uint64_t fb_modifier, unsigned int cpp) | |
7b49f948 VS |
2056 | { |
2057 | switch (fb_modifier) { | |
2058 | case DRM_FORMAT_MOD_NONE: | |
2059 | return cpp; | |
2060 | case I915_FORMAT_MOD_X_TILED: | |
2061 | if (IS_GEN2(dev_priv)) | |
2062 | return 128; | |
2063 | else | |
2064 | return 512; | |
2065 | case I915_FORMAT_MOD_Y_TILED: | |
2066 | if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) | |
2067 | return 128; | |
2068 | else | |
2069 | return 512; | |
2070 | case I915_FORMAT_MOD_Yf_TILED: | |
2071 | switch (cpp) { | |
2072 | case 1: | |
2073 | return 64; | |
2074 | case 2: | |
2075 | case 4: | |
2076 | return 128; | |
2077 | case 8: | |
2078 | case 16: | |
2079 | return 256; | |
2080 | default: | |
2081 | MISSING_CASE(cpp); | |
2082 | return cpp; | |
2083 | } | |
2084 | break; | |
2085 | default: | |
2086 | MISSING_CASE(fb_modifier); | |
2087 | return cpp; | |
2088 | } | |
2089 | } | |
2090 | ||
832be82f VS |
2091 | unsigned int intel_tile_height(const struct drm_i915_private *dev_priv, |
2092 | uint64_t fb_modifier, unsigned int cpp) | |
a57ce0b2 | 2093 | { |
832be82f VS |
2094 | if (fb_modifier == DRM_FORMAT_MOD_NONE) |
2095 | return 1; | |
2096 | else | |
2097 | return intel_tile_size(dev_priv) / | |
27ba3910 | 2098 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
6761dd31 TU |
2099 | } |
2100 | ||
8d0deca8 VS |
2101 | /* Return the tile dimensions in pixel units */ |
2102 | static void intel_tile_dims(const struct drm_i915_private *dev_priv, | |
2103 | unsigned int *tile_width, | |
2104 | unsigned int *tile_height, | |
2105 | uint64_t fb_modifier, | |
2106 | unsigned int cpp) | |
2107 | { | |
2108 | unsigned int tile_width_bytes = | |
2109 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); | |
2110 | ||
2111 | *tile_width = tile_width_bytes / cpp; | |
2112 | *tile_height = intel_tile_size(dev_priv) / tile_width_bytes; | |
2113 | } | |
2114 | ||
6761dd31 TU |
2115 | unsigned int |
2116 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
832be82f | 2117 | uint32_t pixel_format, uint64_t fb_modifier) |
6761dd31 | 2118 | { |
832be82f VS |
2119 | unsigned int cpp = drm_format_plane_cpp(pixel_format, 0); |
2120 | unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp); | |
2121 | ||
2122 | return ALIGN(height, tile_height); | |
a57ce0b2 JB |
2123 | } |
2124 | ||
1663b9d6 VS |
2125 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) |
2126 | { | |
2127 | unsigned int size = 0; | |
2128 | int i; | |
2129 | ||
2130 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) | |
2131 | size += rot_info->plane[i].width * rot_info->plane[i].height; | |
2132 | ||
2133 | return size; | |
2134 | } | |
2135 | ||
75c82a53 | 2136 | static void |
3465c580 VS |
2137 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, |
2138 | const struct drm_framebuffer *fb, | |
2139 | unsigned int rotation) | |
f64b98cd | 2140 | { |
bd2ef25d | 2141 | if (drm_rotation_90_or_270(rotation)) { |
2d7a215f VS |
2142 | *view = i915_ggtt_view_rotated; |
2143 | view->params.rotated = to_intel_framebuffer(fb)->rot_info; | |
2144 | } else { | |
2145 | *view = i915_ggtt_view_normal; | |
2146 | } | |
2147 | } | |
50470bb0 | 2148 | |
603525d7 | 2149 | static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) |
4e9a86b6 VS |
2150 | { |
2151 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2152 | return 256 * 1024; | |
c0f86832 | 2153 | else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) || |
666a4537 | 2154 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
4e9a86b6 VS |
2155 | return 128 * 1024; |
2156 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2157 | return 4 * 1024; | |
2158 | else | |
44c5905e | 2159 | return 0; |
4e9a86b6 VS |
2160 | } |
2161 | ||
603525d7 VS |
2162 | static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv, |
2163 | uint64_t fb_modifier) | |
2164 | { | |
2165 | switch (fb_modifier) { | |
2166 | case DRM_FORMAT_MOD_NONE: | |
2167 | return intel_linear_alignment(dev_priv); | |
2168 | case I915_FORMAT_MOD_X_TILED: | |
2169 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2170 | return 256 * 1024; | |
2171 | return 0; | |
2172 | case I915_FORMAT_MOD_Y_TILED: | |
2173 | case I915_FORMAT_MOD_Yf_TILED: | |
2174 | return 1 * 1024 * 1024; | |
2175 | default: | |
2176 | MISSING_CASE(fb_modifier); | |
2177 | return 0; | |
2178 | } | |
2179 | } | |
2180 | ||
058d88c4 CW |
2181 | struct i915_vma * |
2182 | intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) | |
6b95a207 | 2183 | { |
850c4cdc | 2184 | struct drm_device *dev = fb->dev; |
fac5e23e | 2185 | struct drm_i915_private *dev_priv = to_i915(dev); |
850c4cdc | 2186 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2187 | struct i915_ggtt_view view; |
058d88c4 | 2188 | struct i915_vma *vma; |
6b95a207 | 2189 | u32 alignment; |
6b95a207 | 2190 | |
ebcdd39e MR |
2191 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2192 | ||
bae781b2 | 2193 | alignment = intel_surf_alignment(dev_priv, fb->modifier); |
6b95a207 | 2194 | |
3465c580 | 2195 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2196 | |
693db184 CW |
2197 | /* Note that the w/a also requires 64 PTE of padding following the |
2198 | * bo. We currently fill all unused PTE with the shadow page and so | |
2199 | * we should always have valid PTE following the scanout preventing | |
2200 | * the VT-d warning. | |
2201 | */ | |
48f112fe | 2202 | if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024) |
693db184 CW |
2203 | alignment = 256 * 1024; |
2204 | ||
d6dd6843 PZ |
2205 | /* |
2206 | * Global gtt pte registers are special registers which actually forward | |
2207 | * writes to a chunk of system memory. Which means that there is no risk | |
2208 | * that the register values disappear as soon as we call | |
2209 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2210 | * pin/unpin/fence and not more. | |
2211 | */ | |
2212 | intel_runtime_pm_get(dev_priv); | |
2213 | ||
058d88c4 | 2214 | vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view); |
49ef5294 CW |
2215 | if (IS_ERR(vma)) |
2216 | goto err; | |
6b95a207 | 2217 | |
05a20d09 | 2218 | if (i915_vma_is_map_and_fenceable(vma)) { |
49ef5294 CW |
2219 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
2220 | * fence, whereas 965+ only requires a fence if using | |
2221 | * framebuffer compression. For simplicity, we always, when | |
2222 | * possible, install a fence as the cost is not that onerous. | |
2223 | * | |
2224 | * If we fail to fence the tiled scanout, then either the | |
2225 | * modeset will reject the change (which is highly unlikely as | |
2226 | * the affected systems, all but one, do not have unmappable | |
2227 | * space) or we will not be able to enable full powersaving | |
2228 | * techniques (also likely not to apply due to various limits | |
2229 | * FBC and the like impose on the size of the buffer, which | |
2230 | * presumably we violated anyway with this unmappable buffer). | |
2231 | * Anyway, it is presumably better to stumble onwards with | |
2232 | * something and try to run the system in a "less than optimal" | |
2233 | * mode that matches the user configuration. | |
2234 | */ | |
2235 | if (i915_vma_get_fence(vma) == 0) | |
2236 | i915_vma_pin_fence(vma); | |
9807216f | 2237 | } |
6b95a207 | 2238 | |
49ef5294 | 2239 | err: |
d6dd6843 | 2240 | intel_runtime_pm_put(dev_priv); |
058d88c4 | 2241 | return vma; |
6b95a207 KH |
2242 | } |
2243 | ||
fb4b8ce1 | 2244 | void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) |
1690e1eb | 2245 | { |
82bc3b2d | 2246 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2247 | struct i915_ggtt_view view; |
058d88c4 | 2248 | struct i915_vma *vma; |
82bc3b2d | 2249 | |
ebcdd39e MR |
2250 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2251 | ||
3465c580 | 2252 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
05a20d09 | 2253 | vma = i915_gem_object_to_ggtt(obj, &view); |
f64b98cd | 2254 | |
49ef5294 | 2255 | i915_vma_unpin_fence(vma); |
058d88c4 | 2256 | i915_gem_object_unpin_from_display_plane(vma); |
1690e1eb CW |
2257 | } |
2258 | ||
ef78ec94 VS |
2259 | static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane, |
2260 | unsigned int rotation) | |
2261 | { | |
bd2ef25d | 2262 | if (drm_rotation_90_or_270(rotation)) |
ef78ec94 VS |
2263 | return to_intel_framebuffer(fb)->rotated[plane].pitch; |
2264 | else | |
2265 | return fb->pitches[plane]; | |
2266 | } | |
2267 | ||
6687c906 VS |
2268 | /* |
2269 | * Convert the x/y offsets into a linear offset. | |
2270 | * Only valid with 0/180 degree rotation, which is fine since linear | |
2271 | * offset is only used with linear buffers on pre-hsw and tiled buffers | |
2272 | * with gen2/3, and 90/270 degree rotations isn't supported on any of them. | |
2273 | */ | |
2274 | u32 intel_fb_xy_to_linear(int x, int y, | |
2949056c VS |
2275 | const struct intel_plane_state *state, |
2276 | int plane) | |
6687c906 | 2277 | { |
2949056c | 2278 | const struct drm_framebuffer *fb = state->base.fb; |
6687c906 VS |
2279 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); |
2280 | unsigned int pitch = fb->pitches[plane]; | |
2281 | ||
2282 | return y * pitch + x * cpp; | |
2283 | } | |
2284 | ||
2285 | /* | |
2286 | * Add the x/y offsets derived from fb->offsets[] to the user | |
2287 | * specified plane src x/y offsets. The resulting x/y offsets | |
2288 | * specify the start of scanout from the beginning of the gtt mapping. | |
2289 | */ | |
2290 | void intel_add_fb_offsets(int *x, int *y, | |
2949056c VS |
2291 | const struct intel_plane_state *state, |
2292 | int plane) | |
6687c906 VS |
2293 | |
2294 | { | |
2949056c VS |
2295 | const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb); |
2296 | unsigned int rotation = state->base.rotation; | |
6687c906 | 2297 | |
bd2ef25d | 2298 | if (drm_rotation_90_or_270(rotation)) { |
6687c906 VS |
2299 | *x += intel_fb->rotated[plane].x; |
2300 | *y += intel_fb->rotated[plane].y; | |
2301 | } else { | |
2302 | *x += intel_fb->normal[plane].x; | |
2303 | *y += intel_fb->normal[plane].y; | |
2304 | } | |
2305 | } | |
2306 | ||
29cf9491 | 2307 | /* |
29cf9491 VS |
2308 | * Input tile dimensions and pitch must already be |
2309 | * rotated to match x and y, and in pixel units. | |
2310 | */ | |
66a2d927 VS |
2311 | static u32 _intel_adjust_tile_offset(int *x, int *y, |
2312 | unsigned int tile_width, | |
2313 | unsigned int tile_height, | |
2314 | unsigned int tile_size, | |
2315 | unsigned int pitch_tiles, | |
2316 | u32 old_offset, | |
2317 | u32 new_offset) | |
29cf9491 | 2318 | { |
b9b24038 | 2319 | unsigned int pitch_pixels = pitch_tiles * tile_width; |
29cf9491 VS |
2320 | unsigned int tiles; |
2321 | ||
2322 | WARN_ON(old_offset & (tile_size - 1)); | |
2323 | WARN_ON(new_offset & (tile_size - 1)); | |
2324 | WARN_ON(new_offset > old_offset); | |
2325 | ||
2326 | tiles = (old_offset - new_offset) / tile_size; | |
2327 | ||
2328 | *y += tiles / pitch_tiles * tile_height; | |
2329 | *x += tiles % pitch_tiles * tile_width; | |
2330 | ||
b9b24038 VS |
2331 | /* minimize x in case it got needlessly big */ |
2332 | *y += *x / pitch_pixels * tile_height; | |
2333 | *x %= pitch_pixels; | |
2334 | ||
29cf9491 VS |
2335 | return new_offset; |
2336 | } | |
2337 | ||
66a2d927 VS |
2338 | /* |
2339 | * Adjust the tile offset by moving the difference into | |
2340 | * the x/y offsets. | |
2341 | */ | |
2342 | static u32 intel_adjust_tile_offset(int *x, int *y, | |
2343 | const struct intel_plane_state *state, int plane, | |
2344 | u32 old_offset, u32 new_offset) | |
2345 | { | |
2346 | const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev); | |
2347 | const struct drm_framebuffer *fb = state->base.fb; | |
2348 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); | |
2349 | unsigned int rotation = state->base.rotation; | |
2350 | unsigned int pitch = intel_fb_pitch(fb, plane, rotation); | |
2351 | ||
2352 | WARN_ON(new_offset > old_offset); | |
2353 | ||
bae781b2 | 2354 | if (fb->modifier != DRM_FORMAT_MOD_NONE) { |
66a2d927 VS |
2355 | unsigned int tile_size, tile_width, tile_height; |
2356 | unsigned int pitch_tiles; | |
2357 | ||
2358 | tile_size = intel_tile_size(dev_priv); | |
2359 | intel_tile_dims(dev_priv, &tile_width, &tile_height, | |
bae781b2 | 2360 | fb->modifier, cpp); |
66a2d927 | 2361 | |
bd2ef25d | 2362 | if (drm_rotation_90_or_270(rotation)) { |
66a2d927 VS |
2363 | pitch_tiles = pitch / tile_height; |
2364 | swap(tile_width, tile_height); | |
2365 | } else { | |
2366 | pitch_tiles = pitch / (tile_width * cpp); | |
2367 | } | |
2368 | ||
2369 | _intel_adjust_tile_offset(x, y, tile_width, tile_height, | |
2370 | tile_size, pitch_tiles, | |
2371 | old_offset, new_offset); | |
2372 | } else { | |
2373 | old_offset += *y * pitch + *x * cpp; | |
2374 | ||
2375 | *y = (old_offset - new_offset) / pitch; | |
2376 | *x = ((old_offset - new_offset) - *y * pitch) / cpp; | |
2377 | } | |
2378 | ||
2379 | return new_offset; | |
2380 | } | |
2381 | ||
8d0deca8 VS |
2382 | /* |
2383 | * Computes the linear offset to the base tile and adjusts | |
2384 | * x, y. bytes per pixel is assumed to be a power-of-two. | |
2385 | * | |
2386 | * In the 90/270 rotated case, x and y are assumed | |
2387 | * to be already rotated to match the rotated GTT view, and | |
2388 | * pitch is the tile_height aligned framebuffer height. | |
6687c906 VS |
2389 | * |
2390 | * This function is used when computing the derived information | |
2391 | * under intel_framebuffer, so using any of that information | |
2392 | * here is not allowed. Anything under drm_framebuffer can be | |
2393 | * used. This is why the user has to pass in the pitch since it | |
2394 | * is specified in the rotated orientation. | |
8d0deca8 | 2395 | */ |
6687c906 VS |
2396 | static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv, |
2397 | int *x, int *y, | |
2398 | const struct drm_framebuffer *fb, int plane, | |
2399 | unsigned int pitch, | |
2400 | unsigned int rotation, | |
2401 | u32 alignment) | |
c2c75131 | 2402 | { |
bae781b2 | 2403 | uint64_t fb_modifier = fb->modifier; |
4f2d9934 | 2404 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); |
6687c906 | 2405 | u32 offset, offset_aligned; |
29cf9491 | 2406 | |
29cf9491 VS |
2407 | if (alignment) |
2408 | alignment--; | |
2409 | ||
b5c65338 | 2410 | if (fb_modifier != DRM_FORMAT_MOD_NONE) { |
8d0deca8 VS |
2411 | unsigned int tile_size, tile_width, tile_height; |
2412 | unsigned int tile_rows, tiles, pitch_tiles; | |
c2c75131 | 2413 | |
d843310d | 2414 | tile_size = intel_tile_size(dev_priv); |
8d0deca8 VS |
2415 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2416 | fb_modifier, cpp); | |
2417 | ||
bd2ef25d | 2418 | if (drm_rotation_90_or_270(rotation)) { |
8d0deca8 VS |
2419 | pitch_tiles = pitch / tile_height; |
2420 | swap(tile_width, tile_height); | |
2421 | } else { | |
2422 | pitch_tiles = pitch / (tile_width * cpp); | |
2423 | } | |
d843310d VS |
2424 | |
2425 | tile_rows = *y / tile_height; | |
2426 | *y %= tile_height; | |
c2c75131 | 2427 | |
8d0deca8 VS |
2428 | tiles = *x / tile_width; |
2429 | *x %= tile_width; | |
bc752862 | 2430 | |
29cf9491 VS |
2431 | offset = (tile_rows * pitch_tiles + tiles) * tile_size; |
2432 | offset_aligned = offset & ~alignment; | |
bc752862 | 2433 | |
66a2d927 VS |
2434 | _intel_adjust_tile_offset(x, y, tile_width, tile_height, |
2435 | tile_size, pitch_tiles, | |
2436 | offset, offset_aligned); | |
29cf9491 | 2437 | } else { |
bc752862 | 2438 | offset = *y * pitch + *x * cpp; |
29cf9491 VS |
2439 | offset_aligned = offset & ~alignment; |
2440 | ||
4e9a86b6 VS |
2441 | *y = (offset & alignment) / pitch; |
2442 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
bc752862 | 2443 | } |
29cf9491 VS |
2444 | |
2445 | return offset_aligned; | |
c2c75131 DV |
2446 | } |
2447 | ||
6687c906 | 2448 | u32 intel_compute_tile_offset(int *x, int *y, |
2949056c VS |
2449 | const struct intel_plane_state *state, |
2450 | int plane) | |
6687c906 | 2451 | { |
2949056c VS |
2452 | const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev); |
2453 | const struct drm_framebuffer *fb = state->base.fb; | |
2454 | unsigned int rotation = state->base.rotation; | |
ef78ec94 | 2455 | int pitch = intel_fb_pitch(fb, plane, rotation); |
8d970654 VS |
2456 | u32 alignment; |
2457 | ||
2458 | /* AUX_DIST needs only 4K alignment */ | |
2459 | if (fb->pixel_format == DRM_FORMAT_NV12 && plane == 1) | |
2460 | alignment = 4096; | |
2461 | else | |
bae781b2 | 2462 | alignment = intel_surf_alignment(dev_priv, fb->modifier); |
6687c906 VS |
2463 | |
2464 | return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch, | |
2465 | rotation, alignment); | |
2466 | } | |
2467 | ||
2468 | /* Convert the fb->offset[] linear offset into x/y offsets */ | |
2469 | static void intel_fb_offset_to_xy(int *x, int *y, | |
2470 | const struct drm_framebuffer *fb, int plane) | |
2471 | { | |
2472 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); | |
2473 | unsigned int pitch = fb->pitches[plane]; | |
2474 | u32 linear_offset = fb->offsets[plane]; | |
2475 | ||
2476 | *y = linear_offset / pitch; | |
2477 | *x = linear_offset % pitch / cpp; | |
2478 | } | |
2479 | ||
72618ebf VS |
2480 | static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier) |
2481 | { | |
2482 | switch (fb_modifier) { | |
2483 | case I915_FORMAT_MOD_X_TILED: | |
2484 | return I915_TILING_X; | |
2485 | case I915_FORMAT_MOD_Y_TILED: | |
2486 | return I915_TILING_Y; | |
2487 | default: | |
2488 | return I915_TILING_NONE; | |
2489 | } | |
2490 | } | |
2491 | ||
6687c906 VS |
2492 | static int |
2493 | intel_fill_fb_info(struct drm_i915_private *dev_priv, | |
2494 | struct drm_framebuffer *fb) | |
2495 | { | |
2496 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
2497 | struct intel_rotation_info *rot_info = &intel_fb->rot_info; | |
2498 | u32 gtt_offset_rotated = 0; | |
2499 | unsigned int max_size = 0; | |
2500 | uint32_t format = fb->pixel_format; | |
2501 | int i, num_planes = drm_format_num_planes(format); | |
2502 | unsigned int tile_size = intel_tile_size(dev_priv); | |
2503 | ||
2504 | for (i = 0; i < num_planes; i++) { | |
2505 | unsigned int width, height; | |
2506 | unsigned int cpp, size; | |
2507 | u32 offset; | |
2508 | int x, y; | |
2509 | ||
2510 | cpp = drm_format_plane_cpp(format, i); | |
2511 | width = drm_format_plane_width(fb->width, format, i); | |
2512 | height = drm_format_plane_height(fb->height, format, i); | |
2513 | ||
2514 | intel_fb_offset_to_xy(&x, &y, fb, i); | |
2515 | ||
60d5f2a4 VS |
2516 | /* |
2517 | * The fence (if used) is aligned to the start of the object | |
2518 | * so having the framebuffer wrap around across the edge of the | |
2519 | * fenced region doesn't really work. We have no API to configure | |
2520 | * the fence start offset within the object (nor could we probably | |
2521 | * on gen2/3). So it's just easier if we just require that the | |
2522 | * fb layout agrees with the fence layout. We already check that the | |
2523 | * fb stride matches the fence stride elsewhere. | |
2524 | */ | |
2525 | if (i915_gem_object_is_tiled(intel_fb->obj) && | |
2526 | (x + width) * cpp > fb->pitches[i]) { | |
2527 | DRM_DEBUG("bad fb plane %d offset: 0x%x\n", | |
2528 | i, fb->offsets[i]); | |
2529 | return -EINVAL; | |
2530 | } | |
2531 | ||
6687c906 VS |
2532 | /* |
2533 | * First pixel of the framebuffer from | |
2534 | * the start of the normal gtt mapping. | |
2535 | */ | |
2536 | intel_fb->normal[i].x = x; | |
2537 | intel_fb->normal[i].y = y; | |
2538 | ||
2539 | offset = _intel_compute_tile_offset(dev_priv, &x, &y, | |
2540 | fb, 0, fb->pitches[i], | |
cc926387 | 2541 | DRM_ROTATE_0, tile_size); |
6687c906 VS |
2542 | offset /= tile_size; |
2543 | ||
bae781b2 | 2544 | if (fb->modifier != DRM_FORMAT_MOD_NONE) { |
6687c906 VS |
2545 | unsigned int tile_width, tile_height; |
2546 | unsigned int pitch_tiles; | |
2547 | struct drm_rect r; | |
2548 | ||
2549 | intel_tile_dims(dev_priv, &tile_width, &tile_height, | |
bae781b2 | 2550 | fb->modifier, cpp); |
6687c906 VS |
2551 | |
2552 | rot_info->plane[i].offset = offset; | |
2553 | rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp); | |
2554 | rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width); | |
2555 | rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height); | |
2556 | ||
2557 | intel_fb->rotated[i].pitch = | |
2558 | rot_info->plane[i].height * tile_height; | |
2559 | ||
2560 | /* how many tiles does this plane need */ | |
2561 | size = rot_info->plane[i].stride * rot_info->plane[i].height; | |
2562 | /* | |
2563 | * If the plane isn't horizontally tile aligned, | |
2564 | * we need one more tile. | |
2565 | */ | |
2566 | if (x != 0) | |
2567 | size++; | |
2568 | ||
2569 | /* rotate the x/y offsets to match the GTT view */ | |
2570 | r.x1 = x; | |
2571 | r.y1 = y; | |
2572 | r.x2 = x + width; | |
2573 | r.y2 = y + height; | |
2574 | drm_rect_rotate(&r, | |
2575 | rot_info->plane[i].width * tile_width, | |
2576 | rot_info->plane[i].height * tile_height, | |
cc926387 | 2577 | DRM_ROTATE_270); |
6687c906 VS |
2578 | x = r.x1; |
2579 | y = r.y1; | |
2580 | ||
2581 | /* rotate the tile dimensions to match the GTT view */ | |
2582 | pitch_tiles = intel_fb->rotated[i].pitch / tile_height; | |
2583 | swap(tile_width, tile_height); | |
2584 | ||
2585 | /* | |
2586 | * We only keep the x/y offsets, so push all of the | |
2587 | * gtt offset into the x/y offsets. | |
2588 | */ | |
66a2d927 VS |
2589 | _intel_adjust_tile_offset(&x, &y, tile_size, |
2590 | tile_width, tile_height, pitch_tiles, | |
2591 | gtt_offset_rotated * tile_size, 0); | |
6687c906 VS |
2592 | |
2593 | gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height; | |
2594 | ||
2595 | /* | |
2596 | * First pixel of the framebuffer from | |
2597 | * the start of the rotated gtt mapping. | |
2598 | */ | |
2599 | intel_fb->rotated[i].x = x; | |
2600 | intel_fb->rotated[i].y = y; | |
2601 | } else { | |
2602 | size = DIV_ROUND_UP((y + height) * fb->pitches[i] + | |
2603 | x * cpp, tile_size); | |
2604 | } | |
2605 | ||
2606 | /* how many tiles in total needed in the bo */ | |
2607 | max_size = max(max_size, offset + size); | |
2608 | } | |
2609 | ||
2610 | if (max_size * tile_size > to_intel_framebuffer(fb)->obj->base.size) { | |
2611 | DRM_DEBUG("fb too big for bo (need %u bytes, have %zu bytes)\n", | |
2612 | max_size * tile_size, to_intel_framebuffer(fb)->obj->base.size); | |
2613 | return -EINVAL; | |
2614 | } | |
2615 | ||
2616 | return 0; | |
2617 | } | |
2618 | ||
b35d63fa | 2619 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2620 | { |
2621 | switch (format) { | |
2622 | case DISPPLANE_8BPP: | |
2623 | return DRM_FORMAT_C8; | |
2624 | case DISPPLANE_BGRX555: | |
2625 | return DRM_FORMAT_XRGB1555; | |
2626 | case DISPPLANE_BGRX565: | |
2627 | return DRM_FORMAT_RGB565; | |
2628 | default: | |
2629 | case DISPPLANE_BGRX888: | |
2630 | return DRM_FORMAT_XRGB8888; | |
2631 | case DISPPLANE_RGBX888: | |
2632 | return DRM_FORMAT_XBGR8888; | |
2633 | case DISPPLANE_BGRX101010: | |
2634 | return DRM_FORMAT_XRGB2101010; | |
2635 | case DISPPLANE_RGBX101010: | |
2636 | return DRM_FORMAT_XBGR2101010; | |
2637 | } | |
2638 | } | |
2639 | ||
bc8d7dff DL |
2640 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2641 | { | |
2642 | switch (format) { | |
2643 | case PLANE_CTL_FORMAT_RGB_565: | |
2644 | return DRM_FORMAT_RGB565; | |
2645 | default: | |
2646 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2647 | if (rgb_order) { | |
2648 | if (alpha) | |
2649 | return DRM_FORMAT_ABGR8888; | |
2650 | else | |
2651 | return DRM_FORMAT_XBGR8888; | |
2652 | } else { | |
2653 | if (alpha) | |
2654 | return DRM_FORMAT_ARGB8888; | |
2655 | else | |
2656 | return DRM_FORMAT_XRGB8888; | |
2657 | } | |
2658 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2659 | if (rgb_order) | |
2660 | return DRM_FORMAT_XBGR2101010; | |
2661 | else | |
2662 | return DRM_FORMAT_XRGB2101010; | |
2663 | } | |
2664 | } | |
2665 | ||
5724dbd1 | 2666 | static bool |
f6936e29 DV |
2667 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2668 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2669 | { |
2670 | struct drm_device *dev = crtc->base.dev; | |
3badb49f | 2671 | struct drm_i915_private *dev_priv = to_i915(dev); |
72e96d64 | 2672 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
46f297fb JB |
2673 | struct drm_i915_gem_object *obj = NULL; |
2674 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2675 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2676 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2677 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2678 | PAGE_SIZE); | |
2679 | ||
2680 | size_aligned -= base_aligned; | |
46f297fb | 2681 | |
ff2652ea CW |
2682 | if (plane_config->size == 0) |
2683 | return false; | |
2684 | ||
3badb49f PZ |
2685 | /* If the FB is too big, just don't use it since fbdev is not very |
2686 | * important and we should probably use that space with FBC or other | |
2687 | * features. */ | |
72e96d64 | 2688 | if (size_aligned * 2 > ggtt->stolen_usable_size) |
3badb49f PZ |
2689 | return false; |
2690 | ||
12c83d99 TU |
2691 | mutex_lock(&dev->struct_mutex); |
2692 | ||
187685cb | 2693 | obj = i915_gem_object_create_stolen_for_preallocated(dev_priv, |
f37b5c2b DV |
2694 | base_aligned, |
2695 | base_aligned, | |
2696 | size_aligned); | |
12c83d99 TU |
2697 | if (!obj) { |
2698 | mutex_unlock(&dev->struct_mutex); | |
484b41dd | 2699 | return false; |
12c83d99 | 2700 | } |
46f297fb | 2701 | |
3e510a8e CW |
2702 | if (plane_config->tiling == I915_TILING_X) |
2703 | obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X; | |
46f297fb | 2704 | |
6bf129df DL |
2705 | mode_cmd.pixel_format = fb->pixel_format; |
2706 | mode_cmd.width = fb->width; | |
2707 | mode_cmd.height = fb->height; | |
2708 | mode_cmd.pitches[0] = fb->pitches[0]; | |
bae781b2 | 2709 | mode_cmd.modifier[0] = fb->modifier; |
18c5247e | 2710 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; |
46f297fb | 2711 | |
6bf129df | 2712 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2713 | &mode_cmd, obj)) { |
46f297fb JB |
2714 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2715 | goto out_unref_obj; | |
2716 | } | |
12c83d99 | 2717 | |
46f297fb | 2718 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2719 | |
f6936e29 | 2720 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2721 | return true; |
46f297fb JB |
2722 | |
2723 | out_unref_obj: | |
f8c417cd | 2724 | i915_gem_object_put(obj); |
46f297fb | 2725 | mutex_unlock(&dev->struct_mutex); |
484b41dd JB |
2726 | return false; |
2727 | } | |
2728 | ||
5a21b665 DV |
2729 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2730 | static void | |
2731 | update_state_fb(struct drm_plane *plane) | |
2732 | { | |
2733 | if (plane->fb == plane->state->fb) | |
2734 | return; | |
2735 | ||
2736 | if (plane->state->fb) | |
2737 | drm_framebuffer_unreference(plane->state->fb); | |
2738 | plane->state->fb = plane->fb; | |
2739 | if (plane->state->fb) | |
2740 | drm_framebuffer_reference(plane->state->fb); | |
2741 | } | |
2742 | ||
5724dbd1 | 2743 | static void |
f6936e29 DV |
2744 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2745 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2746 | { |
2747 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 2748 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd JB |
2749 | struct drm_crtc *c; |
2750 | struct intel_crtc *i; | |
2ff8fde1 | 2751 | struct drm_i915_gem_object *obj; |
88595ac9 | 2752 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2753 | struct drm_plane_state *plane_state = primary->state; |
200757f5 MR |
2754 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
2755 | struct intel_plane *intel_plane = to_intel_plane(primary); | |
0a8d8a86 MR |
2756 | struct intel_plane_state *intel_state = |
2757 | to_intel_plane_state(plane_state); | |
88595ac9 | 2758 | struct drm_framebuffer *fb; |
484b41dd | 2759 | |
2d14030b | 2760 | if (!plane_config->fb) |
484b41dd JB |
2761 | return; |
2762 | ||
f6936e29 | 2763 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2764 | fb = &plane_config->fb->base; |
2765 | goto valid_fb; | |
f55548b5 | 2766 | } |
484b41dd | 2767 | |
2d14030b | 2768 | kfree(plane_config->fb); |
484b41dd JB |
2769 | |
2770 | /* | |
2771 | * Failed to alloc the obj, check to see if we should share | |
2772 | * an fb with another CRTC instead | |
2773 | */ | |
70e1e0ec | 2774 | for_each_crtc(dev, c) { |
484b41dd JB |
2775 | i = to_intel_crtc(c); |
2776 | ||
2777 | if (c == &intel_crtc->base) | |
2778 | continue; | |
2779 | ||
2ff8fde1 MR |
2780 | if (!i->active) |
2781 | continue; | |
2782 | ||
88595ac9 DV |
2783 | fb = c->primary->fb; |
2784 | if (!fb) | |
484b41dd JB |
2785 | continue; |
2786 | ||
88595ac9 | 2787 | obj = intel_fb_obj(fb); |
058d88c4 | 2788 | if (i915_gem_object_ggtt_offset(obj, NULL) == plane_config->base) { |
88595ac9 DV |
2789 | drm_framebuffer_reference(fb); |
2790 | goto valid_fb; | |
484b41dd JB |
2791 | } |
2792 | } | |
88595ac9 | 2793 | |
200757f5 MR |
2794 | /* |
2795 | * We've failed to reconstruct the BIOS FB. Current display state | |
2796 | * indicates that the primary plane is visible, but has a NULL FB, | |
2797 | * which will lead to problems later if we don't fix it up. The | |
2798 | * simplest solution is to just disable the primary plane now and | |
2799 | * pretend the BIOS never had it enabled. | |
2800 | */ | |
936e71e3 | 2801 | to_intel_plane_state(plane_state)->base.visible = false; |
200757f5 | 2802 | crtc_state->plane_mask &= ~(1 << drm_plane_index(primary)); |
2622a081 | 2803 | intel_pre_disable_primary_noatomic(&intel_crtc->base); |
200757f5 MR |
2804 | intel_plane->disable_plane(primary, &intel_crtc->base); |
2805 | ||
88595ac9 DV |
2806 | return; |
2807 | ||
2808 | valid_fb: | |
f44e2659 VS |
2809 | plane_state->src_x = 0; |
2810 | plane_state->src_y = 0; | |
be5651f2 ML |
2811 | plane_state->src_w = fb->width << 16; |
2812 | plane_state->src_h = fb->height << 16; | |
2813 | ||
f44e2659 VS |
2814 | plane_state->crtc_x = 0; |
2815 | plane_state->crtc_y = 0; | |
be5651f2 ML |
2816 | plane_state->crtc_w = fb->width; |
2817 | plane_state->crtc_h = fb->height; | |
2818 | ||
1638d30c RC |
2819 | intel_state->base.src = drm_plane_state_src(plane_state); |
2820 | intel_state->base.dst = drm_plane_state_dest(plane_state); | |
0a8d8a86 | 2821 | |
88595ac9 | 2822 | obj = intel_fb_obj(fb); |
3e510a8e | 2823 | if (i915_gem_object_is_tiled(obj)) |
88595ac9 DV |
2824 | dev_priv->preserve_bios_swizzle = true; |
2825 | ||
be5651f2 ML |
2826 | drm_framebuffer_reference(fb); |
2827 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2828 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
36750f28 | 2829 | intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); |
faf5bf0a CW |
2830 | atomic_or(to_intel_plane(primary)->frontbuffer_bit, |
2831 | &obj->frontbuffer_bits); | |
46f297fb JB |
2832 | } |
2833 | ||
b63a16f6 VS |
2834 | static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane, |
2835 | unsigned int rotation) | |
2836 | { | |
2837 | int cpp = drm_format_plane_cpp(fb->pixel_format, plane); | |
2838 | ||
bae781b2 | 2839 | switch (fb->modifier) { |
b63a16f6 VS |
2840 | case DRM_FORMAT_MOD_NONE: |
2841 | case I915_FORMAT_MOD_X_TILED: | |
2842 | switch (cpp) { | |
2843 | case 8: | |
2844 | return 4096; | |
2845 | case 4: | |
2846 | case 2: | |
2847 | case 1: | |
2848 | return 8192; | |
2849 | default: | |
2850 | MISSING_CASE(cpp); | |
2851 | break; | |
2852 | } | |
2853 | break; | |
2854 | case I915_FORMAT_MOD_Y_TILED: | |
2855 | case I915_FORMAT_MOD_Yf_TILED: | |
2856 | switch (cpp) { | |
2857 | case 8: | |
2858 | return 2048; | |
2859 | case 4: | |
2860 | return 4096; | |
2861 | case 2: | |
2862 | case 1: | |
2863 | return 8192; | |
2864 | default: | |
2865 | MISSING_CASE(cpp); | |
2866 | break; | |
2867 | } | |
2868 | break; | |
2869 | default: | |
bae781b2 | 2870 | MISSING_CASE(fb->modifier); |
b63a16f6 VS |
2871 | } |
2872 | ||
2873 | return 2048; | |
2874 | } | |
2875 | ||
2876 | static int skl_check_main_surface(struct intel_plane_state *plane_state) | |
2877 | { | |
2878 | const struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev); | |
2879 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
2880 | unsigned int rotation = plane_state->base.rotation; | |
cc926387 DV |
2881 | int x = plane_state->base.src.x1 >> 16; |
2882 | int y = plane_state->base.src.y1 >> 16; | |
2883 | int w = drm_rect_width(&plane_state->base.src) >> 16; | |
2884 | int h = drm_rect_height(&plane_state->base.src) >> 16; | |
b63a16f6 VS |
2885 | int max_width = skl_max_plane_width(fb, 0, rotation); |
2886 | int max_height = 4096; | |
8d970654 | 2887 | u32 alignment, offset, aux_offset = plane_state->aux.offset; |
b63a16f6 VS |
2888 | |
2889 | if (w > max_width || h > max_height) { | |
2890 | DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n", | |
2891 | w, h, max_width, max_height); | |
2892 | return -EINVAL; | |
2893 | } | |
2894 | ||
2895 | intel_add_fb_offsets(&x, &y, plane_state, 0); | |
2896 | offset = intel_compute_tile_offset(&x, &y, plane_state, 0); | |
2897 | ||
bae781b2 | 2898 | alignment = intel_surf_alignment(dev_priv, fb->modifier); |
b63a16f6 | 2899 | |
8d970654 VS |
2900 | /* |
2901 | * AUX surface offset is specified as the distance from the | |
2902 | * main surface offset, and it must be non-negative. Make | |
2903 | * sure that is what we will get. | |
2904 | */ | |
2905 | if (offset > aux_offset) | |
2906 | offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, | |
2907 | offset, aux_offset & ~(alignment - 1)); | |
2908 | ||
b63a16f6 VS |
2909 | /* |
2910 | * When using an X-tiled surface, the plane blows up | |
2911 | * if the x offset + width exceed the stride. | |
2912 | * | |
2913 | * TODO: linear and Y-tiled seem fine, Yf untested, | |
2914 | */ | |
bae781b2 | 2915 | if (fb->modifier == I915_FORMAT_MOD_X_TILED) { |
b63a16f6 VS |
2916 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
2917 | ||
2918 | while ((x + w) * cpp > fb->pitches[0]) { | |
2919 | if (offset == 0) { | |
2920 | DRM_DEBUG_KMS("Unable to find suitable display surface offset\n"); | |
2921 | return -EINVAL; | |
2922 | } | |
2923 | ||
2924 | offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, | |
2925 | offset, offset - alignment); | |
2926 | } | |
2927 | } | |
2928 | ||
2929 | plane_state->main.offset = offset; | |
2930 | plane_state->main.x = x; | |
2931 | plane_state->main.y = y; | |
2932 | ||
2933 | return 0; | |
2934 | } | |
2935 | ||
8d970654 VS |
2936 | static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) |
2937 | { | |
2938 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
2939 | unsigned int rotation = plane_state->base.rotation; | |
2940 | int max_width = skl_max_plane_width(fb, 1, rotation); | |
2941 | int max_height = 4096; | |
cc926387 DV |
2942 | int x = plane_state->base.src.x1 >> 17; |
2943 | int y = plane_state->base.src.y1 >> 17; | |
2944 | int w = drm_rect_width(&plane_state->base.src) >> 17; | |
2945 | int h = drm_rect_height(&plane_state->base.src) >> 17; | |
8d970654 VS |
2946 | u32 offset; |
2947 | ||
2948 | intel_add_fb_offsets(&x, &y, plane_state, 1); | |
2949 | offset = intel_compute_tile_offset(&x, &y, plane_state, 1); | |
2950 | ||
2951 | /* FIXME not quite sure how/if these apply to the chroma plane */ | |
2952 | if (w > max_width || h > max_height) { | |
2953 | DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n", | |
2954 | w, h, max_width, max_height); | |
2955 | return -EINVAL; | |
2956 | } | |
2957 | ||
2958 | plane_state->aux.offset = offset; | |
2959 | plane_state->aux.x = x; | |
2960 | plane_state->aux.y = y; | |
2961 | ||
2962 | return 0; | |
2963 | } | |
2964 | ||
b63a16f6 VS |
2965 | int skl_check_plane_surface(struct intel_plane_state *plane_state) |
2966 | { | |
2967 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
2968 | unsigned int rotation = plane_state->base.rotation; | |
2969 | int ret; | |
2970 | ||
2971 | /* Rotate src coordinates to match rotated GTT view */ | |
bd2ef25d | 2972 | if (drm_rotation_90_or_270(rotation)) |
cc926387 | 2973 | drm_rect_rotate(&plane_state->base.src, |
da064b47 VS |
2974 | fb->width << 16, fb->height << 16, |
2975 | DRM_ROTATE_270); | |
b63a16f6 | 2976 | |
8d970654 VS |
2977 | /* |
2978 | * Handle the AUX surface first since | |
2979 | * the main surface setup depends on it. | |
2980 | */ | |
2981 | if (fb->pixel_format == DRM_FORMAT_NV12) { | |
2982 | ret = skl_check_nv12_aux_surface(plane_state); | |
2983 | if (ret) | |
2984 | return ret; | |
2985 | } else { | |
2986 | plane_state->aux.offset = ~0xfff; | |
2987 | plane_state->aux.x = 0; | |
2988 | plane_state->aux.y = 0; | |
2989 | } | |
2990 | ||
b63a16f6 VS |
2991 | ret = skl_check_main_surface(plane_state); |
2992 | if (ret) | |
2993 | return ret; | |
2994 | ||
2995 | return 0; | |
2996 | } | |
2997 | ||
a8d201af ML |
2998 | static void i9xx_update_primary_plane(struct drm_plane *primary, |
2999 | const struct intel_crtc_state *crtc_state, | |
3000 | const struct intel_plane_state *plane_state) | |
81255565 | 3001 | { |
6315b5d3 | 3002 | struct drm_i915_private *dev_priv = to_i915(primary->dev); |
a8d201af ML |
3003 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
3004 | struct drm_framebuffer *fb = plane_state->base.fb; | |
81255565 | 3005 | int plane = intel_crtc->plane; |
54ea9da8 | 3006 | u32 linear_offset; |
81255565 | 3007 | u32 dspcntr; |
f0f59a00 | 3008 | i915_reg_t reg = DSPCNTR(plane); |
8d0deca8 | 3009 | unsigned int rotation = plane_state->base.rotation; |
936e71e3 VS |
3010 | int x = plane_state->base.src.x1 >> 16; |
3011 | int y = plane_state->base.src.y1 >> 16; | |
c9ba6fad | 3012 | |
f45651ba VS |
3013 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
3014 | ||
fdd508a6 | 3015 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba | 3016 | |
6315b5d3 | 3017 | if (INTEL_GEN(dev_priv) < 4) { |
f45651ba VS |
3018 | if (intel_crtc->pipe == PIPE_B) |
3019 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
3020 | ||
3021 | /* pipesrc and dspsize control the size that is scaled from, | |
3022 | * which should always be the user's requested size. | |
3023 | */ | |
3024 | I915_WRITE(DSPSIZE(plane), | |
a8d201af ML |
3025 | ((crtc_state->pipe_src_h - 1) << 16) | |
3026 | (crtc_state->pipe_src_w - 1)); | |
f45651ba | 3027 | I915_WRITE(DSPPOS(plane), 0); |
920a14b2 | 3028 | } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) { |
c14b0485 | 3029 | I915_WRITE(PRIMSIZE(plane), |
a8d201af ML |
3030 | ((crtc_state->pipe_src_h - 1) << 16) | |
3031 | (crtc_state->pipe_src_w - 1)); | |
c14b0485 VS |
3032 | I915_WRITE(PRIMPOS(plane), 0); |
3033 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 3034 | } |
81255565 | 3035 | |
57779d06 VS |
3036 | switch (fb->pixel_format) { |
3037 | case DRM_FORMAT_C8: | |
81255565 JB |
3038 | dspcntr |= DISPPLANE_8BPP; |
3039 | break; | |
57779d06 | 3040 | case DRM_FORMAT_XRGB1555: |
57779d06 | 3041 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 3042 | break; |
57779d06 VS |
3043 | case DRM_FORMAT_RGB565: |
3044 | dspcntr |= DISPPLANE_BGRX565; | |
3045 | break; | |
3046 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
3047 | dspcntr |= DISPPLANE_BGRX888; |
3048 | break; | |
3049 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
3050 | dspcntr |= DISPPLANE_RGBX888; |
3051 | break; | |
3052 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
3053 | dspcntr |= DISPPLANE_BGRX101010; |
3054 | break; | |
3055 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 3056 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
3057 | break; |
3058 | default: | |
baba133a | 3059 | BUG(); |
81255565 | 3060 | } |
57779d06 | 3061 | |
72618ebf | 3062 | if (INTEL_GEN(dev_priv) >= 4 && |
bae781b2 | 3063 | fb->modifier == I915_FORMAT_MOD_X_TILED) |
f45651ba | 3064 | dspcntr |= DISPPLANE_TILED; |
81255565 | 3065 | |
df0cd455 VS |
3066 | if (rotation & DRM_ROTATE_180) |
3067 | dspcntr |= DISPPLANE_ROTATE_180; | |
3068 | ||
4ea7be2b VS |
3069 | if (rotation & DRM_REFLECT_X) |
3070 | dspcntr |= DISPPLANE_MIRROR; | |
3071 | ||
9beb5fea | 3072 | if (IS_G4X(dev_priv)) |
de1aa629 VS |
3073 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
3074 | ||
2949056c | 3075 | intel_add_fb_offsets(&x, &y, plane_state, 0); |
81255565 | 3076 | |
6315b5d3 | 3077 | if (INTEL_GEN(dev_priv) >= 4) |
c2c75131 | 3078 | intel_crtc->dspaddr_offset = |
2949056c | 3079 | intel_compute_tile_offset(&x, &y, plane_state, 0); |
e506a0c6 | 3080 | |
f22aa143 | 3081 | if (rotation & DRM_ROTATE_180) { |
df0cd455 VS |
3082 | x += crtc_state->pipe_src_w - 1; |
3083 | y += crtc_state->pipe_src_h - 1; | |
4ea7be2b VS |
3084 | } else if (rotation & DRM_REFLECT_X) { |
3085 | x += crtc_state->pipe_src_w - 1; | |
48404c1e SJ |
3086 | } |
3087 | ||
2949056c | 3088 | linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); |
6687c906 | 3089 | |
6315b5d3 | 3090 | if (INTEL_GEN(dev_priv) < 4) |
6687c906 VS |
3091 | intel_crtc->dspaddr_offset = linear_offset; |
3092 | ||
2db3366b PZ |
3093 | intel_crtc->adjusted_x = x; |
3094 | intel_crtc->adjusted_y = y; | |
3095 | ||
48404c1e SJ |
3096 | I915_WRITE(reg, dspcntr); |
3097 | ||
01f2c773 | 3098 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
6315b5d3 | 3099 | if (INTEL_GEN(dev_priv) >= 4) { |
85ba7b7d | 3100 | I915_WRITE(DSPSURF(plane), |
6687c906 VS |
3101 | intel_fb_gtt_offset(fb, rotation) + |
3102 | intel_crtc->dspaddr_offset); | |
5eddb70b | 3103 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 3104 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
bfb81049 VS |
3105 | } else { |
3106 | I915_WRITE(DSPADDR(plane), | |
3107 | intel_fb_gtt_offset(fb, rotation) + | |
3108 | intel_crtc->dspaddr_offset); | |
3109 | } | |
5eddb70b | 3110 | POSTING_READ(reg); |
17638cd6 JB |
3111 | } |
3112 | ||
a8d201af ML |
3113 | static void i9xx_disable_primary_plane(struct drm_plane *primary, |
3114 | struct drm_crtc *crtc) | |
17638cd6 JB |
3115 | { |
3116 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3117 | struct drm_i915_private *dev_priv = to_i915(dev); |
17638cd6 | 3118 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
17638cd6 | 3119 | int plane = intel_crtc->plane; |
f45651ba | 3120 | |
a8d201af ML |
3121 | I915_WRITE(DSPCNTR(plane), 0); |
3122 | if (INTEL_INFO(dev_priv)->gen >= 4) | |
fdd508a6 | 3123 | I915_WRITE(DSPSURF(plane), 0); |
a8d201af ML |
3124 | else |
3125 | I915_WRITE(DSPADDR(plane), 0); | |
3126 | POSTING_READ(DSPCNTR(plane)); | |
3127 | } | |
c9ba6fad | 3128 | |
a8d201af ML |
3129 | static void ironlake_update_primary_plane(struct drm_plane *primary, |
3130 | const struct intel_crtc_state *crtc_state, | |
3131 | const struct intel_plane_state *plane_state) | |
3132 | { | |
3133 | struct drm_device *dev = primary->dev; | |
fac5e23e | 3134 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8d201af ML |
3135 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
3136 | struct drm_framebuffer *fb = plane_state->base.fb; | |
a8d201af | 3137 | int plane = intel_crtc->plane; |
54ea9da8 | 3138 | u32 linear_offset; |
a8d201af ML |
3139 | u32 dspcntr; |
3140 | i915_reg_t reg = DSPCNTR(plane); | |
8d0deca8 | 3141 | unsigned int rotation = plane_state->base.rotation; |
936e71e3 VS |
3142 | int x = plane_state->base.src.x1 >> 16; |
3143 | int y = plane_state->base.src.y1 >> 16; | |
c9ba6fad | 3144 | |
f45651ba | 3145 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
fdd508a6 | 3146 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba | 3147 | |
8652744b | 3148 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
f45651ba | 3149 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; |
17638cd6 | 3150 | |
57779d06 VS |
3151 | switch (fb->pixel_format) { |
3152 | case DRM_FORMAT_C8: | |
17638cd6 JB |
3153 | dspcntr |= DISPPLANE_8BPP; |
3154 | break; | |
57779d06 VS |
3155 | case DRM_FORMAT_RGB565: |
3156 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 3157 | break; |
57779d06 | 3158 | case DRM_FORMAT_XRGB8888: |
57779d06 VS |
3159 | dspcntr |= DISPPLANE_BGRX888; |
3160 | break; | |
3161 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
3162 | dspcntr |= DISPPLANE_RGBX888; |
3163 | break; | |
3164 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
3165 | dspcntr |= DISPPLANE_BGRX101010; |
3166 | break; | |
3167 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 3168 | dspcntr |= DISPPLANE_RGBX101010; |
17638cd6 JB |
3169 | break; |
3170 | default: | |
baba133a | 3171 | BUG(); |
17638cd6 JB |
3172 | } |
3173 | ||
bae781b2 | 3174 | if (fb->modifier == I915_FORMAT_MOD_X_TILED) |
17638cd6 | 3175 | dspcntr |= DISPPLANE_TILED; |
17638cd6 | 3176 | |
df0cd455 VS |
3177 | if (rotation & DRM_ROTATE_180) |
3178 | dspcntr |= DISPPLANE_ROTATE_180; | |
3179 | ||
8652744b | 3180 | if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) |
1f5d76db | 3181 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 3182 | |
2949056c | 3183 | intel_add_fb_offsets(&x, &y, plane_state, 0); |
6687c906 | 3184 | |
c2c75131 | 3185 | intel_crtc->dspaddr_offset = |
2949056c | 3186 | intel_compute_tile_offset(&x, &y, plane_state, 0); |
6687c906 | 3187 | |
df0cd455 VS |
3188 | /* HSW+ does this automagically in hardware */ |
3189 | if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv) && | |
3190 | rotation & DRM_ROTATE_180) { | |
3191 | x += crtc_state->pipe_src_w - 1; | |
3192 | y += crtc_state->pipe_src_h - 1; | |
48404c1e SJ |
3193 | } |
3194 | ||
2949056c | 3195 | linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); |
6687c906 | 3196 | |
2db3366b PZ |
3197 | intel_crtc->adjusted_x = x; |
3198 | intel_crtc->adjusted_y = y; | |
3199 | ||
48404c1e | 3200 | I915_WRITE(reg, dspcntr); |
17638cd6 | 3201 | |
01f2c773 | 3202 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d | 3203 | I915_WRITE(DSPSURF(plane), |
6687c906 VS |
3204 | intel_fb_gtt_offset(fb, rotation) + |
3205 | intel_crtc->dspaddr_offset); | |
8652744b | 3206 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
bc1c91eb DL |
3207 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
3208 | } else { | |
3209 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
3210 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
3211 | } | |
17638cd6 | 3212 | POSTING_READ(reg); |
17638cd6 JB |
3213 | } |
3214 | ||
7b49f948 VS |
3215 | u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv, |
3216 | uint64_t fb_modifier, uint32_t pixel_format) | |
b321803d | 3217 | { |
7b49f948 | 3218 | if (fb_modifier == DRM_FORMAT_MOD_NONE) { |
b321803d | 3219 | return 64; |
7b49f948 VS |
3220 | } else { |
3221 | int cpp = drm_format_plane_cpp(pixel_format, 0); | |
3222 | ||
27ba3910 | 3223 | return intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
b321803d DL |
3224 | } |
3225 | } | |
3226 | ||
6687c906 VS |
3227 | u32 intel_fb_gtt_offset(struct drm_framebuffer *fb, |
3228 | unsigned int rotation) | |
121920fa | 3229 | { |
6687c906 | 3230 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
ce7f1728 | 3231 | struct i915_ggtt_view view; |
058d88c4 | 3232 | struct i915_vma *vma; |
121920fa | 3233 | |
6687c906 | 3234 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
dedf278c | 3235 | |
058d88c4 CW |
3236 | vma = i915_gem_object_to_ggtt(obj, &view); |
3237 | if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n", | |
3238 | view.type)) | |
3239 | return -1; | |
3240 | ||
bde13ebd | 3241 | return i915_ggtt_offset(vma); |
121920fa TU |
3242 | } |
3243 | ||
e435d6e5 ML |
3244 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
3245 | { | |
3246 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 3247 | struct drm_i915_private *dev_priv = to_i915(dev); |
e435d6e5 ML |
3248 | |
3249 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
3250 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
3251 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
3252 | } |
3253 | ||
a1b2278e CK |
3254 | /* |
3255 | * This function detaches (aka. unbinds) unused scalers in hardware | |
3256 | */ | |
0583236e | 3257 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 3258 | { |
a1b2278e CK |
3259 | struct intel_crtc_scaler_state *scaler_state; |
3260 | int i; | |
3261 | ||
a1b2278e CK |
3262 | scaler_state = &intel_crtc->config->scaler_state; |
3263 | ||
3264 | /* loop through and disable scalers that aren't in use */ | |
3265 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
3266 | if (!scaler_state->scalers[i].in_use) |
3267 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
3268 | } |
3269 | } | |
3270 | ||
d2196774 VS |
3271 | u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane, |
3272 | unsigned int rotation) | |
3273 | { | |
3274 | const struct drm_i915_private *dev_priv = to_i915(fb->dev); | |
3275 | u32 stride = intel_fb_pitch(fb, plane, rotation); | |
3276 | ||
3277 | /* | |
3278 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
3279 | * linear buffers or in number of tiles for tiled buffers. | |
3280 | */ | |
bd2ef25d | 3281 | if (drm_rotation_90_or_270(rotation)) { |
d2196774 VS |
3282 | int cpp = drm_format_plane_cpp(fb->pixel_format, plane); |
3283 | ||
bae781b2 | 3284 | stride /= intel_tile_height(dev_priv, fb->modifier, cpp); |
d2196774 | 3285 | } else { |
bae781b2 | 3286 | stride /= intel_fb_stride_alignment(dev_priv, fb->modifier, |
d2196774 VS |
3287 | fb->pixel_format); |
3288 | } | |
3289 | ||
3290 | return stride; | |
3291 | } | |
3292 | ||
6156a456 | 3293 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 3294 | { |
6156a456 | 3295 | switch (pixel_format) { |
d161cf7a | 3296 | case DRM_FORMAT_C8: |
c34ce3d1 | 3297 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 3298 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 3299 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 3300 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 3301 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 3302 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 3303 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
3304 | /* |
3305 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
3306 | * to be already pre-multiplied. We need to add a knob (or a different | |
3307 | * DRM_FORMAT) for user-space to configure that. | |
3308 | */ | |
f75fb42a | 3309 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 3310 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 3311 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 3312 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 3313 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 3314 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 3315 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 3316 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 3317 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 3318 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 3319 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 3320 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 3321 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 3322 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 3323 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 3324 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 3325 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 3326 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 3327 | default: |
4249eeef | 3328 | MISSING_CASE(pixel_format); |
70d21f0e | 3329 | } |
8cfcba41 | 3330 | |
c34ce3d1 | 3331 | return 0; |
6156a456 | 3332 | } |
70d21f0e | 3333 | |
6156a456 CK |
3334 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
3335 | { | |
6156a456 | 3336 | switch (fb_modifier) { |
30af77c4 | 3337 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 3338 | break; |
30af77c4 | 3339 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 3340 | return PLANE_CTL_TILED_X; |
b321803d | 3341 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 3342 | return PLANE_CTL_TILED_Y; |
b321803d | 3343 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 3344 | return PLANE_CTL_TILED_YF; |
70d21f0e | 3345 | default: |
6156a456 | 3346 | MISSING_CASE(fb_modifier); |
70d21f0e | 3347 | } |
8cfcba41 | 3348 | |
c34ce3d1 | 3349 | return 0; |
6156a456 | 3350 | } |
70d21f0e | 3351 | |
6156a456 CK |
3352 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
3353 | { | |
3b7a5119 | 3354 | switch (rotation) { |
31ad61e4 | 3355 | case DRM_ROTATE_0: |
6156a456 | 3356 | break; |
1e8df167 SJ |
3357 | /* |
3358 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
3359 | * while i915 HW rotation is clockwise, thats why this swapping. | |
3360 | */ | |
31ad61e4 | 3361 | case DRM_ROTATE_90: |
1e8df167 | 3362 | return PLANE_CTL_ROTATE_270; |
31ad61e4 | 3363 | case DRM_ROTATE_180: |
c34ce3d1 | 3364 | return PLANE_CTL_ROTATE_180; |
31ad61e4 | 3365 | case DRM_ROTATE_270: |
1e8df167 | 3366 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
3367 | default: |
3368 | MISSING_CASE(rotation); | |
3369 | } | |
3370 | ||
c34ce3d1 | 3371 | return 0; |
6156a456 CK |
3372 | } |
3373 | ||
a8d201af ML |
3374 | static void skylake_update_primary_plane(struct drm_plane *plane, |
3375 | const struct intel_crtc_state *crtc_state, | |
3376 | const struct intel_plane_state *plane_state) | |
6156a456 | 3377 | { |
a8d201af | 3378 | struct drm_device *dev = plane->dev; |
fac5e23e | 3379 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8d201af ML |
3380 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
3381 | struct drm_framebuffer *fb = plane_state->base.fb; | |
8e816bb4 VS |
3382 | enum plane_id plane_id = to_intel_plane(plane)->id; |
3383 | enum pipe pipe = to_intel_plane(plane)->pipe; | |
d2196774 | 3384 | u32 plane_ctl; |
a8d201af | 3385 | unsigned int rotation = plane_state->base.rotation; |
d2196774 | 3386 | u32 stride = skl_plane_stride(fb, 0, rotation); |
b63a16f6 | 3387 | u32 surf_addr = plane_state->main.offset; |
a8d201af | 3388 | int scaler_id = plane_state->scaler_id; |
b63a16f6 VS |
3389 | int src_x = plane_state->main.x; |
3390 | int src_y = plane_state->main.y; | |
936e71e3 VS |
3391 | int src_w = drm_rect_width(&plane_state->base.src) >> 16; |
3392 | int src_h = drm_rect_height(&plane_state->base.src) >> 16; | |
3393 | int dst_x = plane_state->base.dst.x1; | |
3394 | int dst_y = plane_state->base.dst.y1; | |
3395 | int dst_w = drm_rect_width(&plane_state->base.dst); | |
3396 | int dst_h = drm_rect_height(&plane_state->base.dst); | |
70d21f0e | 3397 | |
6156a456 CK |
3398 | plane_ctl = PLANE_CTL_ENABLE | |
3399 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3400 | PLANE_CTL_PIPE_CSC_ENABLE; | |
3401 | ||
3402 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); | |
bae781b2 | 3403 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier); |
6156a456 | 3404 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; |
6156a456 CK |
3405 | plane_ctl |= skl_plane_ctl_rotation(rotation); |
3406 | ||
6687c906 VS |
3407 | /* Sizes are 0 based */ |
3408 | src_w--; | |
3409 | src_h--; | |
3410 | dst_w--; | |
3411 | dst_h--; | |
3412 | ||
4c0b8a8b PZ |
3413 | intel_crtc->dspaddr_offset = surf_addr; |
3414 | ||
6687c906 VS |
3415 | intel_crtc->adjusted_x = src_x; |
3416 | intel_crtc->adjusted_y = src_y; | |
2db3366b | 3417 | |
8e816bb4 VS |
3418 | I915_WRITE(PLANE_CTL(pipe, plane_id), plane_ctl); |
3419 | I915_WRITE(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x); | |
3420 | I915_WRITE(PLANE_STRIDE(pipe, plane_id), stride); | |
3421 | I915_WRITE(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w); | |
6156a456 CK |
3422 | |
3423 | if (scaler_id >= 0) { | |
3424 | uint32_t ps_ctrl = 0; | |
3425 | ||
3426 | WARN_ON(!dst_w || !dst_h); | |
8e816bb4 | 3427 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) | |
6156a456 CK |
3428 | crtc_state->scaler_state.scalers[scaler_id].mode; |
3429 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3430 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3431 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3432 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
8e816bb4 | 3433 | I915_WRITE(PLANE_POS(pipe, plane_id), 0); |
6156a456 | 3434 | } else { |
8e816bb4 | 3435 | I915_WRITE(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x); |
6156a456 CK |
3436 | } |
3437 | ||
8e816bb4 | 3438 | I915_WRITE(PLANE_SURF(pipe, plane_id), |
6687c906 | 3439 | intel_fb_gtt_offset(fb, rotation) + surf_addr); |
70d21f0e | 3440 | |
8e816bb4 | 3441 | POSTING_READ(PLANE_SURF(pipe, plane_id)); |
70d21f0e DL |
3442 | } |
3443 | ||
a8d201af ML |
3444 | static void skylake_disable_primary_plane(struct drm_plane *primary, |
3445 | struct drm_crtc *crtc) | |
17638cd6 JB |
3446 | { |
3447 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3448 | struct drm_i915_private *dev_priv = to_i915(dev); |
8e816bb4 VS |
3449 | enum plane_id plane_id = to_intel_plane(primary)->id; |
3450 | enum pipe pipe = to_intel_plane(primary)->pipe; | |
62e0fb88 | 3451 | |
8e816bb4 VS |
3452 | I915_WRITE(PLANE_CTL(pipe, plane_id), 0); |
3453 | I915_WRITE(PLANE_SURF(pipe, plane_id), 0); | |
3454 | POSTING_READ(PLANE_SURF(pipe, plane_id)); | |
a8d201af | 3455 | } |
29b9bde6 | 3456 | |
a8d201af ML |
3457 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3458 | static int | |
3459 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3460 | int x, int y, enum mode_set_atomic state) | |
3461 | { | |
3462 | /* Support for kgdboc is disabled, this needs a major rework. */ | |
3463 | DRM_ERROR("legacy panic handler not supported any more.\n"); | |
3464 | ||
3465 | return -ENODEV; | |
81255565 JB |
3466 | } |
3467 | ||
5a21b665 DV |
3468 | static void intel_complete_page_flips(struct drm_i915_private *dev_priv) |
3469 | { | |
3470 | struct intel_crtc *crtc; | |
3471 | ||
91c8a326 | 3472 | for_each_intel_crtc(&dev_priv->drm, crtc) |
5a21b665 DV |
3473 | intel_finish_page_flip_cs(dev_priv, crtc->pipe); |
3474 | } | |
3475 | ||
7514747d VS |
3476 | static void intel_update_primary_planes(struct drm_device *dev) |
3477 | { | |
7514747d | 3478 | struct drm_crtc *crtc; |
96a02917 | 3479 | |
70e1e0ec | 3480 | for_each_crtc(dev, crtc) { |
11c22da6 | 3481 | struct intel_plane *plane = to_intel_plane(crtc->primary); |
73974893 ML |
3482 | struct intel_plane_state *plane_state = |
3483 | to_intel_plane_state(plane->base.state); | |
11c22da6 | 3484 | |
936e71e3 | 3485 | if (plane_state->base.visible) |
a8d201af ML |
3486 | plane->update_plane(&plane->base, |
3487 | to_intel_crtc_state(crtc->state), | |
3488 | plane_state); | |
73974893 ML |
3489 | } |
3490 | } | |
3491 | ||
3492 | static int | |
3493 | __intel_display_resume(struct drm_device *dev, | |
3494 | struct drm_atomic_state *state) | |
3495 | { | |
3496 | struct drm_crtc_state *crtc_state; | |
3497 | struct drm_crtc *crtc; | |
3498 | int i, ret; | |
11c22da6 | 3499 | |
73974893 | 3500 | intel_modeset_setup_hw_state(dev); |
29b74b7f | 3501 | i915_redisable_vga(to_i915(dev)); |
73974893 ML |
3502 | |
3503 | if (!state) | |
3504 | return 0; | |
3505 | ||
3506 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
3507 | /* | |
3508 | * Force recalculation even if we restore | |
3509 | * current state. With fast modeset this may not result | |
3510 | * in a modeset when the state is compatible. | |
3511 | */ | |
3512 | crtc_state->mode_changed = true; | |
96a02917 | 3513 | } |
73974893 ML |
3514 | |
3515 | /* ignore any reset values/BIOS leftovers in the WM registers */ | |
3516 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
3517 | ||
3518 | ret = drm_atomic_commit(state); | |
3519 | ||
3520 | WARN_ON(ret == -EDEADLK); | |
3521 | return ret; | |
96a02917 VS |
3522 | } |
3523 | ||
4ac2ba2f VS |
3524 | static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv) |
3525 | { | |
ae98104b VS |
3526 | return intel_has_gpu_reset(dev_priv) && |
3527 | INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv); | |
4ac2ba2f VS |
3528 | } |
3529 | ||
c033666a | 3530 | void intel_prepare_reset(struct drm_i915_private *dev_priv) |
7514747d | 3531 | { |
73974893 ML |
3532 | struct drm_device *dev = &dev_priv->drm; |
3533 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; | |
3534 | struct drm_atomic_state *state; | |
3535 | int ret; | |
3536 | ||
73974893 ML |
3537 | /* |
3538 | * Need mode_config.mutex so that we don't | |
3539 | * trample ongoing ->detect() and whatnot. | |
3540 | */ | |
3541 | mutex_lock(&dev->mode_config.mutex); | |
3542 | drm_modeset_acquire_init(ctx, 0); | |
3543 | while (1) { | |
3544 | ret = drm_modeset_lock_all_ctx(dev, ctx); | |
3545 | if (ret != -EDEADLK) | |
3546 | break; | |
3547 | ||
3548 | drm_modeset_backoff(ctx); | |
3549 | } | |
3550 | ||
3551 | /* reset doesn't touch the display, but flips might get nuked anyway, */ | |
522a63de | 3552 | if (!i915.force_reset_modeset_test && |
4ac2ba2f | 3553 | !gpu_reset_clobbers_display(dev_priv)) |
7514747d VS |
3554 | return; |
3555 | ||
f98ce92f VS |
3556 | /* |
3557 | * Disabling the crtcs gracefully seems nicer. Also the | |
3558 | * g33 docs say we should at least disable all the planes. | |
3559 | */ | |
73974893 ML |
3560 | state = drm_atomic_helper_duplicate_state(dev, ctx); |
3561 | if (IS_ERR(state)) { | |
3562 | ret = PTR_ERR(state); | |
3563 | state = NULL; | |
3564 | DRM_ERROR("Duplicating state failed with %i\n", ret); | |
3565 | goto err; | |
3566 | } | |
3567 | ||
3568 | ret = drm_atomic_helper_disable_all(dev, ctx); | |
3569 | if (ret) { | |
3570 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
3571 | goto err; | |
3572 | } | |
3573 | ||
3574 | dev_priv->modeset_restore_state = state; | |
3575 | state->acquire_ctx = ctx; | |
3576 | return; | |
3577 | ||
3578 | err: | |
0853695c | 3579 | drm_atomic_state_put(state); |
7514747d VS |
3580 | } |
3581 | ||
c033666a | 3582 | void intel_finish_reset(struct drm_i915_private *dev_priv) |
7514747d | 3583 | { |
73974893 ML |
3584 | struct drm_device *dev = &dev_priv->drm; |
3585 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; | |
3586 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
3587 | int ret; | |
3588 | ||
5a21b665 DV |
3589 | /* |
3590 | * Flips in the rings will be nuked by the reset, | |
3591 | * so complete all pending flips so that user space | |
3592 | * will get its events and not get stuck. | |
3593 | */ | |
3594 | intel_complete_page_flips(dev_priv); | |
3595 | ||
73974893 ML |
3596 | dev_priv->modeset_restore_state = NULL; |
3597 | ||
7514747d | 3598 | /* reset doesn't touch the display */ |
4ac2ba2f | 3599 | if (!gpu_reset_clobbers_display(dev_priv)) { |
522a63de ML |
3600 | if (!state) { |
3601 | /* | |
3602 | * Flips in the rings have been nuked by the reset, | |
3603 | * so update the base address of all primary | |
3604 | * planes to the the last fb to make sure we're | |
3605 | * showing the correct fb after a reset. | |
3606 | * | |
3607 | * FIXME: Atomic will make this obsolete since we won't schedule | |
3608 | * CS-based flips (which might get lost in gpu resets) any more. | |
3609 | */ | |
3610 | intel_update_primary_planes(dev); | |
3611 | } else { | |
3612 | ret = __intel_display_resume(dev, state); | |
3613 | if (ret) | |
3614 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
3615 | } | |
73974893 ML |
3616 | } else { |
3617 | /* | |
3618 | * The display has been reset as well, | |
3619 | * so need a full re-initialization. | |
3620 | */ | |
3621 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3622 | intel_runtime_pm_enable_interrupts(dev_priv); | |
7514747d | 3623 | |
51f59205 | 3624 | intel_pps_unlock_regs_wa(dev_priv); |
73974893 | 3625 | intel_modeset_init_hw(dev); |
7514747d | 3626 | |
73974893 ML |
3627 | spin_lock_irq(&dev_priv->irq_lock); |
3628 | if (dev_priv->display.hpd_irq_setup) | |
3629 | dev_priv->display.hpd_irq_setup(dev_priv); | |
3630 | spin_unlock_irq(&dev_priv->irq_lock); | |
7514747d | 3631 | |
73974893 ML |
3632 | ret = __intel_display_resume(dev, state); |
3633 | if (ret) | |
3634 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
7514747d | 3635 | |
73974893 ML |
3636 | intel_hpd_init(dev_priv); |
3637 | } | |
7514747d | 3638 | |
0853695c CW |
3639 | if (state) |
3640 | drm_atomic_state_put(state); | |
73974893 ML |
3641 | drm_modeset_drop_locks(ctx); |
3642 | drm_modeset_acquire_fini(ctx); | |
3643 | mutex_unlock(&dev->mode_config.mutex); | |
7514747d VS |
3644 | } |
3645 | ||
8af29b0c CW |
3646 | static bool abort_flip_on_reset(struct intel_crtc *crtc) |
3647 | { | |
3648 | struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error; | |
3649 | ||
3650 | if (i915_reset_in_progress(error)) | |
3651 | return true; | |
3652 | ||
3653 | if (crtc->reset_count != i915_reset_count(error)) | |
3654 | return true; | |
3655 | ||
3656 | return false; | |
3657 | } | |
3658 | ||
7d5e3799 CW |
3659 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3660 | { | |
5a21b665 DV |
3661 | struct drm_device *dev = crtc->dev; |
3662 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5a21b665 DV |
3663 | bool pending; |
3664 | ||
8af29b0c | 3665 | if (abort_flip_on_reset(intel_crtc)) |
5a21b665 DV |
3666 | return false; |
3667 | ||
3668 | spin_lock_irq(&dev->event_lock); | |
3669 | pending = to_intel_crtc(crtc)->flip_work != NULL; | |
3670 | spin_unlock_irq(&dev->event_lock); | |
3671 | ||
3672 | return pending; | |
7d5e3799 CW |
3673 | } |
3674 | ||
bfd16b2a ML |
3675 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
3676 | struct intel_crtc_state *old_crtc_state) | |
e30e8f75 | 3677 | { |
6315b5d3 | 3678 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
bfd16b2a ML |
3679 | struct intel_crtc_state *pipe_config = |
3680 | to_intel_crtc_state(crtc->base.state); | |
e30e8f75 | 3681 | |
bfd16b2a ML |
3682 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
3683 | crtc->base.mode = crtc->base.state->mode; | |
3684 | ||
3685 | DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n", | |
3686 | old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h, | |
3687 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
e30e8f75 GP |
3688 | |
3689 | /* | |
3690 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3691 | * that in compute_mode_changes we check the native mode (not the pfit | |
3692 | * mode) to see if we can flip rather than do a full mode set. In the | |
3693 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3694 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3695 | * sized surface. | |
e30e8f75 GP |
3696 | */ |
3697 | ||
e30e8f75 | 3698 | I915_WRITE(PIPESRC(crtc->pipe), |
bfd16b2a ML |
3699 | ((pipe_config->pipe_src_w - 1) << 16) | |
3700 | (pipe_config->pipe_src_h - 1)); | |
3701 | ||
3702 | /* on skylake this is done by detaching scalers */ | |
6315b5d3 | 3703 | if (INTEL_GEN(dev_priv) >= 9) { |
bfd16b2a ML |
3704 | skl_detach_scalers(crtc); |
3705 | ||
3706 | if (pipe_config->pch_pfit.enabled) | |
3707 | skylake_pfit_enable(crtc); | |
6e266956 | 3708 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
bfd16b2a ML |
3709 | if (pipe_config->pch_pfit.enabled) |
3710 | ironlake_pfit_enable(crtc); | |
3711 | else if (old_crtc_state->pch_pfit.enabled) | |
3712 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3713 | } |
e30e8f75 GP |
3714 | } |
3715 | ||
5e84e1a4 ZW |
3716 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3717 | { | |
3718 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3719 | struct drm_i915_private *dev_priv = to_i915(dev); |
5e84e1a4 ZW |
3720 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3721 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3722 | i915_reg_t reg; |
3723 | u32 temp; | |
5e84e1a4 ZW |
3724 | |
3725 | /* enable normal train */ | |
3726 | reg = FDI_TX_CTL(pipe); | |
3727 | temp = I915_READ(reg); | |
fd6b8f43 | 3728 | if (IS_IVYBRIDGE(dev_priv)) { |
357555c0 JB |
3729 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3730 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3731 | } else { |
3732 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3733 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3734 | } |
5e84e1a4 ZW |
3735 | I915_WRITE(reg, temp); |
3736 | ||
3737 | reg = FDI_RX_CTL(pipe); | |
3738 | temp = I915_READ(reg); | |
6e266956 | 3739 | if (HAS_PCH_CPT(dev_priv)) { |
5e84e1a4 ZW |
3740 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3741 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3742 | } else { | |
3743 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3744 | temp |= FDI_LINK_TRAIN_NONE; | |
3745 | } | |
3746 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3747 | ||
3748 | /* wait one idle pattern time */ | |
3749 | POSTING_READ(reg); | |
3750 | udelay(1000); | |
357555c0 JB |
3751 | |
3752 | /* IVB wants error correction enabled */ | |
fd6b8f43 | 3753 | if (IS_IVYBRIDGE(dev_priv)) |
357555c0 JB |
3754 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | |
3755 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3756 | } |
3757 | ||
8db9d77b ZW |
3758 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3759 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3760 | { | |
3761 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3762 | struct drm_i915_private *dev_priv = to_i915(dev); |
8db9d77b ZW |
3763 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3764 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3765 | i915_reg_t reg; |
3766 | u32 temp, tries; | |
8db9d77b | 3767 | |
1c8562f6 | 3768 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3769 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3770 | |
e1a44743 AJ |
3771 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3772 | for train result */ | |
5eddb70b CW |
3773 | reg = FDI_RX_IMR(pipe); |
3774 | temp = I915_READ(reg); | |
e1a44743 AJ |
3775 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3776 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3777 | I915_WRITE(reg, temp); |
3778 | I915_READ(reg); | |
e1a44743 AJ |
3779 | udelay(150); |
3780 | ||
8db9d77b | 3781 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3782 | reg = FDI_TX_CTL(pipe); |
3783 | temp = I915_READ(reg); | |
627eb5a3 | 3784 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3785 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3786 | temp &= ~FDI_LINK_TRAIN_NONE; |
3787 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3788 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3789 | |
5eddb70b CW |
3790 | reg = FDI_RX_CTL(pipe); |
3791 | temp = I915_READ(reg); | |
8db9d77b ZW |
3792 | temp &= ~FDI_LINK_TRAIN_NONE; |
3793 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3794 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3795 | ||
3796 | POSTING_READ(reg); | |
8db9d77b ZW |
3797 | udelay(150); |
3798 | ||
5b2adf89 | 3799 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3800 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3801 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3802 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3803 | |
5eddb70b | 3804 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3805 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3806 | temp = I915_READ(reg); |
8db9d77b ZW |
3807 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3808 | ||
3809 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3810 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3811 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3812 | break; |
3813 | } | |
8db9d77b | 3814 | } |
e1a44743 | 3815 | if (tries == 5) |
5eddb70b | 3816 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3817 | |
3818 | /* Train 2 */ | |
5eddb70b CW |
3819 | reg = FDI_TX_CTL(pipe); |
3820 | temp = I915_READ(reg); | |
8db9d77b ZW |
3821 | temp &= ~FDI_LINK_TRAIN_NONE; |
3822 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3823 | I915_WRITE(reg, temp); |
8db9d77b | 3824 | |
5eddb70b CW |
3825 | reg = FDI_RX_CTL(pipe); |
3826 | temp = I915_READ(reg); | |
8db9d77b ZW |
3827 | temp &= ~FDI_LINK_TRAIN_NONE; |
3828 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3829 | I915_WRITE(reg, temp); |
8db9d77b | 3830 | |
5eddb70b CW |
3831 | POSTING_READ(reg); |
3832 | udelay(150); | |
8db9d77b | 3833 | |
5eddb70b | 3834 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3835 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3836 | temp = I915_READ(reg); |
8db9d77b ZW |
3837 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3838 | ||
3839 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3840 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3841 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3842 | break; | |
3843 | } | |
8db9d77b | 3844 | } |
e1a44743 | 3845 | if (tries == 5) |
5eddb70b | 3846 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3847 | |
3848 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3849 | |
8db9d77b ZW |
3850 | } |
3851 | ||
0206e353 | 3852 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3853 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3854 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3855 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3856 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3857 | }; | |
3858 | ||
3859 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3860 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3861 | { | |
3862 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3863 | struct drm_i915_private *dev_priv = to_i915(dev); |
8db9d77b ZW |
3864 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3865 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3866 | i915_reg_t reg; |
3867 | u32 temp, i, retry; | |
8db9d77b | 3868 | |
e1a44743 AJ |
3869 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3870 | for train result */ | |
5eddb70b CW |
3871 | reg = FDI_RX_IMR(pipe); |
3872 | temp = I915_READ(reg); | |
e1a44743 AJ |
3873 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3874 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3875 | I915_WRITE(reg, temp); |
3876 | ||
3877 | POSTING_READ(reg); | |
e1a44743 AJ |
3878 | udelay(150); |
3879 | ||
8db9d77b | 3880 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3881 | reg = FDI_TX_CTL(pipe); |
3882 | temp = I915_READ(reg); | |
627eb5a3 | 3883 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3884 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3885 | temp &= ~FDI_LINK_TRAIN_NONE; |
3886 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3887 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3888 | /* SNB-B */ | |
3889 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3890 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3891 | |
d74cf324 DV |
3892 | I915_WRITE(FDI_RX_MISC(pipe), |
3893 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3894 | ||
5eddb70b CW |
3895 | reg = FDI_RX_CTL(pipe); |
3896 | temp = I915_READ(reg); | |
6e266956 | 3897 | if (HAS_PCH_CPT(dev_priv)) { |
8db9d77b ZW |
3898 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3899 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3900 | } else { | |
3901 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3902 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3903 | } | |
5eddb70b CW |
3904 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3905 | ||
3906 | POSTING_READ(reg); | |
8db9d77b ZW |
3907 | udelay(150); |
3908 | ||
0206e353 | 3909 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3910 | reg = FDI_TX_CTL(pipe); |
3911 | temp = I915_READ(reg); | |
8db9d77b ZW |
3912 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3913 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3914 | I915_WRITE(reg, temp); |
3915 | ||
3916 | POSTING_READ(reg); | |
8db9d77b ZW |
3917 | udelay(500); |
3918 | ||
fa37d39e SP |
3919 | for (retry = 0; retry < 5; retry++) { |
3920 | reg = FDI_RX_IIR(pipe); | |
3921 | temp = I915_READ(reg); | |
3922 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3923 | if (temp & FDI_RX_BIT_LOCK) { | |
3924 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3925 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3926 | break; | |
3927 | } | |
3928 | udelay(50); | |
8db9d77b | 3929 | } |
fa37d39e SP |
3930 | if (retry < 5) |
3931 | break; | |
8db9d77b ZW |
3932 | } |
3933 | if (i == 4) | |
5eddb70b | 3934 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3935 | |
3936 | /* Train 2 */ | |
5eddb70b CW |
3937 | reg = FDI_TX_CTL(pipe); |
3938 | temp = I915_READ(reg); | |
8db9d77b ZW |
3939 | temp &= ~FDI_LINK_TRAIN_NONE; |
3940 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5db94019 | 3941 | if (IS_GEN6(dev_priv)) { |
8db9d77b ZW |
3942 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3943 | /* SNB-B */ | |
3944 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3945 | } | |
5eddb70b | 3946 | I915_WRITE(reg, temp); |
8db9d77b | 3947 | |
5eddb70b CW |
3948 | reg = FDI_RX_CTL(pipe); |
3949 | temp = I915_READ(reg); | |
6e266956 | 3950 | if (HAS_PCH_CPT(dev_priv)) { |
8db9d77b ZW |
3951 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3952 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3953 | } else { | |
3954 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3955 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3956 | } | |
5eddb70b CW |
3957 | I915_WRITE(reg, temp); |
3958 | ||
3959 | POSTING_READ(reg); | |
8db9d77b ZW |
3960 | udelay(150); |
3961 | ||
0206e353 | 3962 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3963 | reg = FDI_TX_CTL(pipe); |
3964 | temp = I915_READ(reg); | |
8db9d77b ZW |
3965 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3966 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3967 | I915_WRITE(reg, temp); |
3968 | ||
3969 | POSTING_READ(reg); | |
8db9d77b ZW |
3970 | udelay(500); |
3971 | ||
fa37d39e SP |
3972 | for (retry = 0; retry < 5; retry++) { |
3973 | reg = FDI_RX_IIR(pipe); | |
3974 | temp = I915_READ(reg); | |
3975 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3976 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3977 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3978 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3979 | break; | |
3980 | } | |
3981 | udelay(50); | |
8db9d77b | 3982 | } |
fa37d39e SP |
3983 | if (retry < 5) |
3984 | break; | |
8db9d77b ZW |
3985 | } |
3986 | if (i == 4) | |
5eddb70b | 3987 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3988 | |
3989 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3990 | } | |
3991 | ||
357555c0 JB |
3992 | /* Manual link training for Ivy Bridge A0 parts */ |
3993 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3994 | { | |
3995 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3996 | struct drm_i915_private *dev_priv = to_i915(dev); |
357555c0 JB |
3997 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3998 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3999 | i915_reg_t reg; |
4000 | u32 temp, i, j; | |
357555c0 JB |
4001 | |
4002 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
4003 | for train result */ | |
4004 | reg = FDI_RX_IMR(pipe); | |
4005 | temp = I915_READ(reg); | |
4006 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
4007 | temp &= ~FDI_RX_BIT_LOCK; | |
4008 | I915_WRITE(reg, temp); | |
4009 | ||
4010 | POSTING_READ(reg); | |
4011 | udelay(150); | |
4012 | ||
01a415fd DV |
4013 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
4014 | I915_READ(FDI_RX_IIR(pipe))); | |
4015 | ||
139ccd3f JB |
4016 | /* Try each vswing and preemphasis setting twice before moving on */ |
4017 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
4018 | /* disable first in case we need to retry */ | |
4019 | reg = FDI_TX_CTL(pipe); | |
4020 | temp = I915_READ(reg); | |
4021 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
4022 | temp &= ~FDI_TX_ENABLE; | |
4023 | I915_WRITE(reg, temp); | |
357555c0 | 4024 | |
139ccd3f JB |
4025 | reg = FDI_RX_CTL(pipe); |
4026 | temp = I915_READ(reg); | |
4027 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
4028 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
4029 | temp &= ~FDI_RX_ENABLE; | |
4030 | I915_WRITE(reg, temp); | |
357555c0 | 4031 | |
139ccd3f | 4032 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
4033 | reg = FDI_TX_CTL(pipe); |
4034 | temp = I915_READ(reg); | |
139ccd3f | 4035 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 4036 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 4037 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 4038 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
4039 | temp |= snb_b_fdi_train_param[j/2]; |
4040 | temp |= FDI_COMPOSITE_SYNC; | |
4041 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 4042 | |
139ccd3f JB |
4043 | I915_WRITE(FDI_RX_MISC(pipe), |
4044 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 4045 | |
139ccd3f | 4046 | reg = FDI_RX_CTL(pipe); |
357555c0 | 4047 | temp = I915_READ(reg); |
139ccd3f JB |
4048 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
4049 | temp |= FDI_COMPOSITE_SYNC; | |
4050 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 4051 | |
139ccd3f JB |
4052 | POSTING_READ(reg); |
4053 | udelay(1); /* should be 0.5us */ | |
357555c0 | 4054 | |
139ccd3f JB |
4055 | for (i = 0; i < 4; i++) { |
4056 | reg = FDI_RX_IIR(pipe); | |
4057 | temp = I915_READ(reg); | |
4058 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 4059 | |
139ccd3f JB |
4060 | if (temp & FDI_RX_BIT_LOCK || |
4061 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
4062 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
4063 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
4064 | i); | |
4065 | break; | |
4066 | } | |
4067 | udelay(1); /* should be 0.5us */ | |
4068 | } | |
4069 | if (i == 4) { | |
4070 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
4071 | continue; | |
4072 | } | |
357555c0 | 4073 | |
139ccd3f | 4074 | /* Train 2 */ |
357555c0 JB |
4075 | reg = FDI_TX_CTL(pipe); |
4076 | temp = I915_READ(reg); | |
139ccd3f JB |
4077 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
4078 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
4079 | I915_WRITE(reg, temp); | |
4080 | ||
4081 | reg = FDI_RX_CTL(pipe); | |
4082 | temp = I915_READ(reg); | |
4083 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
4084 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
4085 | I915_WRITE(reg, temp); |
4086 | ||
4087 | POSTING_READ(reg); | |
139ccd3f | 4088 | udelay(2); /* should be 1.5us */ |
357555c0 | 4089 | |
139ccd3f JB |
4090 | for (i = 0; i < 4; i++) { |
4091 | reg = FDI_RX_IIR(pipe); | |
4092 | temp = I915_READ(reg); | |
4093 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 4094 | |
139ccd3f JB |
4095 | if (temp & FDI_RX_SYMBOL_LOCK || |
4096 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
4097 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
4098 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
4099 | i); | |
4100 | goto train_done; | |
4101 | } | |
4102 | udelay(2); /* should be 1.5us */ | |
357555c0 | 4103 | } |
139ccd3f JB |
4104 | if (i == 4) |
4105 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 4106 | } |
357555c0 | 4107 | |
139ccd3f | 4108 | train_done: |
357555c0 JB |
4109 | DRM_DEBUG_KMS("FDI train done.\n"); |
4110 | } | |
4111 | ||
88cefb6c | 4112 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 4113 | { |
88cefb6c | 4114 | struct drm_device *dev = intel_crtc->base.dev; |
fac5e23e | 4115 | struct drm_i915_private *dev_priv = to_i915(dev); |
2c07245f | 4116 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
4117 | i915_reg_t reg; |
4118 | u32 temp; | |
c64e311e | 4119 | |
c98e9dcf | 4120 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
4121 | reg = FDI_RX_CTL(pipe); |
4122 | temp = I915_READ(reg); | |
627eb5a3 | 4123 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 4124 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 4125 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
4126 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
4127 | ||
4128 | POSTING_READ(reg); | |
c98e9dcf JB |
4129 | udelay(200); |
4130 | ||
4131 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
4132 | temp = I915_READ(reg); |
4133 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
4134 | ||
4135 | POSTING_READ(reg); | |
c98e9dcf JB |
4136 | udelay(200); |
4137 | ||
20749730 PZ |
4138 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
4139 | reg = FDI_TX_CTL(pipe); | |
4140 | temp = I915_READ(reg); | |
4141 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
4142 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 4143 | |
20749730 PZ |
4144 | POSTING_READ(reg); |
4145 | udelay(100); | |
6be4a607 | 4146 | } |
0e23b99d JB |
4147 | } |
4148 | ||
88cefb6c DV |
4149 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
4150 | { | |
4151 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 4152 | struct drm_i915_private *dev_priv = to_i915(dev); |
88cefb6c | 4153 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
4154 | i915_reg_t reg; |
4155 | u32 temp; | |
88cefb6c DV |
4156 | |
4157 | /* Switch from PCDclk to Rawclk */ | |
4158 | reg = FDI_RX_CTL(pipe); | |
4159 | temp = I915_READ(reg); | |
4160 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
4161 | ||
4162 | /* Disable CPU FDI TX PLL */ | |
4163 | reg = FDI_TX_CTL(pipe); | |
4164 | temp = I915_READ(reg); | |
4165 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
4166 | ||
4167 | POSTING_READ(reg); | |
4168 | udelay(100); | |
4169 | ||
4170 | reg = FDI_RX_CTL(pipe); | |
4171 | temp = I915_READ(reg); | |
4172 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
4173 | ||
4174 | /* Wait for the clocks to turn off. */ | |
4175 | POSTING_READ(reg); | |
4176 | udelay(100); | |
4177 | } | |
4178 | ||
0fc932b8 JB |
4179 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
4180 | { | |
4181 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4182 | struct drm_i915_private *dev_priv = to_i915(dev); |
0fc932b8 JB |
4183 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4184 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
4185 | i915_reg_t reg; |
4186 | u32 temp; | |
0fc932b8 JB |
4187 | |
4188 | /* disable CPU FDI tx and PCH FDI rx */ | |
4189 | reg = FDI_TX_CTL(pipe); | |
4190 | temp = I915_READ(reg); | |
4191 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
4192 | POSTING_READ(reg); | |
4193 | ||
4194 | reg = FDI_RX_CTL(pipe); | |
4195 | temp = I915_READ(reg); | |
4196 | temp &= ~(0x7 << 16); | |
dfd07d72 | 4197 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
4198 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
4199 | ||
4200 | POSTING_READ(reg); | |
4201 | udelay(100); | |
4202 | ||
4203 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
6e266956 | 4204 | if (HAS_PCH_IBX(dev_priv)) |
6f06ce18 | 4205 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
4206 | |
4207 | /* still set train pattern 1 */ | |
4208 | reg = FDI_TX_CTL(pipe); | |
4209 | temp = I915_READ(reg); | |
4210 | temp &= ~FDI_LINK_TRAIN_NONE; | |
4211 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
4212 | I915_WRITE(reg, temp); | |
4213 | ||
4214 | reg = FDI_RX_CTL(pipe); | |
4215 | temp = I915_READ(reg); | |
6e266956 | 4216 | if (HAS_PCH_CPT(dev_priv)) { |
0fc932b8 JB |
4217 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
4218 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
4219 | } else { | |
4220 | temp &= ~FDI_LINK_TRAIN_NONE; | |
4221 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
4222 | } | |
4223 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
4224 | temp &= ~(0x07 << 16); | |
dfd07d72 | 4225 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
4226 | I915_WRITE(reg, temp); |
4227 | ||
4228 | POSTING_READ(reg); | |
4229 | udelay(100); | |
4230 | } | |
4231 | ||
49d73912 | 4232 | bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) |
5dce5b93 CW |
4233 | { |
4234 | struct intel_crtc *crtc; | |
4235 | ||
4236 | /* Note that we don't need to be called with mode_config.lock here | |
4237 | * as our list of CRTC objects is static for the lifetime of the | |
4238 | * device and so cannot disappear as we iterate. Similarly, we can | |
4239 | * happily treat the predicates as racy, atomic checks as userspace | |
4240 | * cannot claim and pin a new fb without at least acquring the | |
4241 | * struct_mutex and so serialising with us. | |
4242 | */ | |
49d73912 | 4243 | for_each_intel_crtc(&dev_priv->drm, crtc) { |
5dce5b93 CW |
4244 | if (atomic_read(&crtc->unpin_work_count) == 0) |
4245 | continue; | |
4246 | ||
5a21b665 | 4247 | if (crtc->flip_work) |
0f0f74bc | 4248 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
5dce5b93 CW |
4249 | |
4250 | return true; | |
4251 | } | |
4252 | ||
4253 | return false; | |
4254 | } | |
4255 | ||
5a21b665 | 4256 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
d6bbafa1 CW |
4257 | { |
4258 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
5a21b665 DV |
4259 | struct intel_flip_work *work = intel_crtc->flip_work; |
4260 | ||
4261 | intel_crtc->flip_work = NULL; | |
d6bbafa1 CW |
4262 | |
4263 | if (work->event) | |
560ce1dc | 4264 | drm_crtc_send_vblank_event(&intel_crtc->base, work->event); |
d6bbafa1 CW |
4265 | |
4266 | drm_crtc_vblank_put(&intel_crtc->base); | |
4267 | ||
5a21b665 | 4268 | wake_up_all(&dev_priv->pending_flip_queue); |
143f73b3 | 4269 | queue_work(dev_priv->wq, &work->unpin_work); |
5a21b665 DV |
4270 | |
4271 | trace_i915_flip_complete(intel_crtc->plane, | |
4272 | work->pending_flip_obj); | |
d6bbafa1 CW |
4273 | } |
4274 | ||
5008e874 | 4275 | static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 4276 | { |
0f91128d | 4277 | struct drm_device *dev = crtc->dev; |
fac5e23e | 4278 | struct drm_i915_private *dev_priv = to_i915(dev); |
5008e874 | 4279 | long ret; |
e6c3a2a6 | 4280 | |
2c10d571 | 4281 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
5008e874 ML |
4282 | |
4283 | ret = wait_event_interruptible_timeout( | |
4284 | dev_priv->pending_flip_queue, | |
4285 | !intel_crtc_has_pending_flip(crtc), | |
4286 | 60*HZ); | |
4287 | ||
4288 | if (ret < 0) | |
4289 | return ret; | |
4290 | ||
5a21b665 DV |
4291 | if (ret == 0) { |
4292 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4293 | struct intel_flip_work *work; | |
4294 | ||
4295 | spin_lock_irq(&dev->event_lock); | |
4296 | work = intel_crtc->flip_work; | |
4297 | if (work && !is_mmio_work(work)) { | |
4298 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
4299 | page_flip_completed(intel_crtc); | |
4300 | } | |
4301 | spin_unlock_irq(&dev->event_lock); | |
4302 | } | |
5bb61643 | 4303 | |
5008e874 | 4304 | return 0; |
e6c3a2a6 CW |
4305 | } |
4306 | ||
b7076546 | 4307 | void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
060f02d8 VS |
4308 | { |
4309 | u32 temp; | |
4310 | ||
4311 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
4312 | ||
4313 | mutex_lock(&dev_priv->sb_lock); | |
4314 | ||
4315 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
4316 | temp |= SBI_SSCCTL_DISABLE; | |
4317 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
4318 | ||
4319 | mutex_unlock(&dev_priv->sb_lock); | |
4320 | } | |
4321 | ||
e615efe4 ED |
4322 | /* Program iCLKIP clock to the desired frequency */ |
4323 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
4324 | { | |
64b46a06 | 4325 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
6e3c9717 | 4326 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
4327 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
4328 | u32 temp; | |
4329 | ||
060f02d8 | 4330 | lpt_disable_iclkip(dev_priv); |
e615efe4 | 4331 | |
64b46a06 VS |
4332 | /* The iCLK virtual clock root frequency is in MHz, |
4333 | * but the adjusted_mode->crtc_clock in in KHz. To get the | |
4334 | * divisors, it is necessary to divide one by another, so we | |
4335 | * convert the virtual clock precision to KHz here for higher | |
4336 | * precision. | |
4337 | */ | |
4338 | for (auxdiv = 0; auxdiv < 2; auxdiv++) { | |
e615efe4 ED |
4339 | u32 iclk_virtual_root_freq = 172800 * 1000; |
4340 | u32 iclk_pi_range = 64; | |
64b46a06 | 4341 | u32 desired_divisor; |
e615efe4 | 4342 | |
64b46a06 VS |
4343 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, |
4344 | clock << auxdiv); | |
4345 | divsel = (desired_divisor / iclk_pi_range) - 2; | |
4346 | phaseinc = desired_divisor % iclk_pi_range; | |
e615efe4 | 4347 | |
64b46a06 VS |
4348 | /* |
4349 | * Near 20MHz is a corner case which is | |
4350 | * out of range for the 7-bit divisor | |
4351 | */ | |
4352 | if (divsel <= 0x7f) | |
4353 | break; | |
e615efe4 ED |
4354 | } |
4355 | ||
4356 | /* This should not happen with any sane values */ | |
4357 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
4358 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
4359 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
4360 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
4361 | ||
4362 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 4363 | clock, |
e615efe4 ED |
4364 | auxdiv, |
4365 | divsel, | |
4366 | phasedir, | |
4367 | phaseinc); | |
4368 | ||
060f02d8 VS |
4369 | mutex_lock(&dev_priv->sb_lock); |
4370 | ||
e615efe4 | 4371 | /* Program SSCDIVINTPHASE6 */ |
988d6ee8 | 4372 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
4373 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
4374 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
4375 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
4376 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
4377 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
4378 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 4379 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
4380 | |
4381 | /* Program SSCAUXDIV */ | |
988d6ee8 | 4382 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
4383 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
4384 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 4385 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
4386 | |
4387 | /* Enable modulator and associated divider */ | |
988d6ee8 | 4388 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 4389 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 4390 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 | 4391 | |
060f02d8 VS |
4392 | mutex_unlock(&dev_priv->sb_lock); |
4393 | ||
e615efe4 ED |
4394 | /* Wait for initialization time */ |
4395 | udelay(24); | |
4396 | ||
4397 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
4398 | } | |
4399 | ||
8802e5b6 VS |
4400 | int lpt_get_iclkip(struct drm_i915_private *dev_priv) |
4401 | { | |
4402 | u32 divsel, phaseinc, auxdiv; | |
4403 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
4404 | u32 iclk_pi_range = 64; | |
4405 | u32 desired_divisor; | |
4406 | u32 temp; | |
4407 | ||
4408 | if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) | |
4409 | return 0; | |
4410 | ||
4411 | mutex_lock(&dev_priv->sb_lock); | |
4412 | ||
4413 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
4414 | if (temp & SBI_SSCCTL_DISABLE) { | |
4415 | mutex_unlock(&dev_priv->sb_lock); | |
4416 | return 0; | |
4417 | } | |
4418 | ||
4419 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); | |
4420 | divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >> | |
4421 | SBI_SSCDIVINTPHASE_DIVSEL_SHIFT; | |
4422 | phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >> | |
4423 | SBI_SSCDIVINTPHASE_INCVAL_SHIFT; | |
4424 | ||
4425 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); | |
4426 | auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >> | |
4427 | SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT; | |
4428 | ||
4429 | mutex_unlock(&dev_priv->sb_lock); | |
4430 | ||
4431 | desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc; | |
4432 | ||
4433 | return DIV_ROUND_CLOSEST(iclk_virtual_root_freq, | |
4434 | desired_divisor << auxdiv); | |
4435 | } | |
4436 | ||
275f01b2 DV |
4437 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4438 | enum pipe pch_transcoder) | |
4439 | { | |
4440 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4441 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 4442 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4443 | |
4444 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4445 | I915_READ(HTOTAL(cpu_transcoder))); | |
4446 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4447 | I915_READ(HBLANK(cpu_transcoder))); | |
4448 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4449 | I915_READ(HSYNC(cpu_transcoder))); | |
4450 | ||
4451 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4452 | I915_READ(VTOTAL(cpu_transcoder))); | |
4453 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4454 | I915_READ(VBLANK(cpu_transcoder))); | |
4455 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4456 | I915_READ(VSYNC(cpu_transcoder))); | |
4457 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4458 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4459 | } | |
4460 | ||
003632d9 | 4461 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 | 4462 | { |
fac5e23e | 4463 | struct drm_i915_private *dev_priv = to_i915(dev); |
1fbc0d78 DV |
4464 | uint32_t temp; |
4465 | ||
4466 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4467 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4468 | return; |
4469 | ||
4470 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4471 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4472 | ||
003632d9 ACO |
4473 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4474 | if (enable) | |
4475 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4476 | ||
4477 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4478 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4479 | POSTING_READ(SOUTH_CHICKEN1); | |
4480 | } | |
4481 | ||
4482 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4483 | { | |
4484 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4485 | |
4486 | switch (intel_crtc->pipe) { | |
4487 | case PIPE_A: | |
4488 | break; | |
4489 | case PIPE_B: | |
6e3c9717 | 4490 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4491 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4492 | else |
003632d9 | 4493 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4494 | |
4495 | break; | |
4496 | case PIPE_C: | |
003632d9 | 4497 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4498 | |
4499 | break; | |
4500 | default: | |
4501 | BUG(); | |
4502 | } | |
4503 | } | |
4504 | ||
c48b5305 VS |
4505 | /* Return which DP Port should be selected for Transcoder DP control */ |
4506 | static enum port | |
4507 | intel_trans_dp_port_sel(struct drm_crtc *crtc) | |
4508 | { | |
4509 | struct drm_device *dev = crtc->dev; | |
4510 | struct intel_encoder *encoder; | |
4511 | ||
4512 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
cca0502b | 4513 | if (encoder->type == INTEL_OUTPUT_DP || |
c48b5305 VS |
4514 | encoder->type == INTEL_OUTPUT_EDP) |
4515 | return enc_to_dig_port(&encoder->base)->port; | |
4516 | } | |
4517 | ||
4518 | return -1; | |
4519 | } | |
4520 | ||
f67a559d JB |
4521 | /* |
4522 | * Enable PCH resources required for PCH ports: | |
4523 | * - PCH PLLs | |
4524 | * - FDI training & RX/TX | |
4525 | * - update transcoder timings | |
4526 | * - DP transcoding bits | |
4527 | * - transcoder | |
4528 | */ | |
4529 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4530 | { |
4531 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4532 | struct drm_i915_private *dev_priv = to_i915(dev); |
0e23b99d JB |
4533 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4534 | int pipe = intel_crtc->pipe; | |
f0f59a00 | 4535 | u32 temp; |
2c07245f | 4536 | |
ab9412ba | 4537 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4538 | |
fd6b8f43 | 4539 | if (IS_IVYBRIDGE(dev_priv)) |
1fbc0d78 DV |
4540 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); |
4541 | ||
cd986abb DV |
4542 | /* Write the TU size bits before fdi link training, so that error |
4543 | * detection works. */ | |
4544 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4545 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4546 | ||
c98e9dcf | 4547 | /* For PCH output, training FDI link */ |
674cf967 | 4548 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4549 | |
3ad8a208 DV |
4550 | /* We need to program the right clock selection before writing the pixel |
4551 | * mutliplier into the DPLL. */ | |
6e266956 | 4552 | if (HAS_PCH_CPT(dev_priv)) { |
ee7b9f93 | 4553 | u32 sel; |
4b645f14 | 4554 | |
c98e9dcf | 4555 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4556 | temp |= TRANS_DPLL_ENABLE(pipe); |
4557 | sel = TRANS_DPLLB_SEL(pipe); | |
8106ddbd ACO |
4558 | if (intel_crtc->config->shared_dpll == |
4559 | intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B)) | |
ee7b9f93 JB |
4560 | temp |= sel; |
4561 | else | |
4562 | temp &= ~sel; | |
c98e9dcf | 4563 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4564 | } |
5eddb70b | 4565 | |
3ad8a208 DV |
4566 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4567 | * transcoder, and we actually should do this to not upset any PCH | |
4568 | * transcoder that already use the clock when we share it. | |
4569 | * | |
4570 | * Note that enable_shared_dpll tries to do the right thing, but | |
4571 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4572 | * the right LVDS enable sequence. */ | |
85b3894f | 4573 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4574 | |
d9b6cb56 JB |
4575 | /* set transcoder timing, panel must allow it */ |
4576 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4577 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4578 | |
303b81e0 | 4579 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4580 | |
c98e9dcf | 4581 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e266956 TU |
4582 | if (HAS_PCH_CPT(dev_priv) && |
4583 | intel_crtc_has_dp_encoder(intel_crtc->config)) { | |
9c4edaee VS |
4584 | const struct drm_display_mode *adjusted_mode = |
4585 | &intel_crtc->config->base.adjusted_mode; | |
dfd07d72 | 4586 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
f0f59a00 | 4587 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
5eddb70b CW |
4588 | temp = I915_READ(reg); |
4589 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4590 | TRANS_DP_SYNC_MASK | |
4591 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4592 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4593 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf | 4594 | |
9c4edaee | 4595 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
5eddb70b | 4596 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
9c4edaee | 4597 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4598 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4599 | |
4600 | switch (intel_trans_dp_port_sel(crtc)) { | |
c48b5305 | 4601 | case PORT_B: |
5eddb70b | 4602 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 4603 | break; |
c48b5305 | 4604 | case PORT_C: |
5eddb70b | 4605 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf | 4606 | break; |
c48b5305 | 4607 | case PORT_D: |
5eddb70b | 4608 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4609 | break; |
4610 | default: | |
e95d41e1 | 4611 | BUG(); |
32f9d658 | 4612 | } |
2c07245f | 4613 | |
5eddb70b | 4614 | I915_WRITE(reg, temp); |
6be4a607 | 4615 | } |
b52eb4dc | 4616 | |
b8a4f404 | 4617 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4618 | } |
4619 | ||
1507e5bd PZ |
4620 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4621 | { | |
4622 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4623 | struct drm_i915_private *dev_priv = to_i915(dev); |
1507e5bd | 4624 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 4625 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4626 | |
ab9412ba | 4627 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4628 | |
8c52b5e8 | 4629 | lpt_program_iclkip(crtc); |
1507e5bd | 4630 | |
0540e488 | 4631 | /* Set transcoder timing. */ |
275f01b2 | 4632 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4633 | |
937bb610 | 4634 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4635 | } |
4636 | ||
a1520318 | 4637 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 | 4638 | { |
fac5e23e | 4639 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 4640 | i915_reg_t dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4641 | u32 temp; |
4642 | ||
4643 | temp = I915_READ(dslreg); | |
4644 | udelay(500); | |
4645 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4646 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4647 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4648 | } |
4649 | } | |
4650 | ||
86adf9d7 ML |
4651 | static int |
4652 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
4653 | unsigned scaler_user, int *scaler_id, unsigned int rotation, | |
4654 | int src_w, int src_h, int dst_w, int dst_h) | |
a1b2278e | 4655 | { |
86adf9d7 ML |
4656 | struct intel_crtc_scaler_state *scaler_state = |
4657 | &crtc_state->scaler_state; | |
4658 | struct intel_crtc *intel_crtc = | |
4659 | to_intel_crtc(crtc_state->base.crtc); | |
a1b2278e | 4660 | int need_scaling; |
6156a456 | 4661 | |
bd2ef25d | 4662 | need_scaling = drm_rotation_90_or_270(rotation) ? |
6156a456 CK |
4663 | (src_h != dst_w || src_w != dst_h): |
4664 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4665 | |
4666 | /* | |
4667 | * if plane is being disabled or scaler is no more required or force detach | |
4668 | * - free scaler binded to this plane/crtc | |
4669 | * - in order to do this, update crtc->scaler_usage | |
4670 | * | |
4671 | * Here scaler state in crtc_state is set free so that | |
4672 | * scaler can be assigned to other user. Actual register | |
4673 | * update to free the scaler is done in plane/panel-fit programming. | |
4674 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4675 | */ | |
86adf9d7 | 4676 | if (force_detach || !need_scaling) { |
a1b2278e | 4677 | if (*scaler_id >= 0) { |
86adf9d7 | 4678 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4679 | scaler_state->scalers[*scaler_id].in_use = 0; |
4680 | ||
86adf9d7 ML |
4681 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4682 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4683 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4684 | scaler_state->scaler_users); |
4685 | *scaler_id = -1; | |
4686 | } | |
4687 | return 0; | |
4688 | } | |
4689 | ||
4690 | /* range checks */ | |
4691 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4692 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4693 | ||
4694 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4695 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4696 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4697 | "size is out of scaler range\n", |
86adf9d7 | 4698 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4699 | return -EINVAL; |
4700 | } | |
4701 | ||
86adf9d7 ML |
4702 | /* mark this plane as a scaler user in crtc_state */ |
4703 | scaler_state->scaler_users |= (1 << scaler_user); | |
4704 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4705 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4706 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4707 | scaler_state->scaler_users); | |
4708 | ||
4709 | return 0; | |
4710 | } | |
4711 | ||
4712 | /** | |
4713 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4714 | * | |
4715 | * @state: crtc's scaler state | |
86adf9d7 ML |
4716 | * |
4717 | * Return | |
4718 | * 0 - scaler_usage updated successfully | |
4719 | * error - requested scaling cannot be supported or other error condition | |
4720 | */ | |
e435d6e5 | 4721 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 | 4722 | { |
7c5f93b0 | 4723 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
86adf9d7 | 4724 | |
e435d6e5 | 4725 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
31ad61e4 | 4726 | &state->scaler_state.scaler_id, DRM_ROTATE_0, |
86adf9d7 | 4727 | state->pipe_src_w, state->pipe_src_h, |
aad941d5 | 4728 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
86adf9d7 ML |
4729 | } |
4730 | ||
4731 | /** | |
4732 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4733 | * | |
4734 | * @state: crtc's scaler state | |
86adf9d7 ML |
4735 | * @plane_state: atomic plane state to update |
4736 | * | |
4737 | * Return | |
4738 | * 0 - scaler_usage updated successfully | |
4739 | * error - requested scaling cannot be supported or other error condition | |
4740 | */ | |
da20eabd ML |
4741 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4742 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4743 | { |
4744 | ||
da20eabd ML |
4745 | struct intel_plane *intel_plane = |
4746 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4747 | struct drm_framebuffer *fb = plane_state->base.fb; |
4748 | int ret; | |
4749 | ||
936e71e3 | 4750 | bool force_detach = !fb || !plane_state->base.visible; |
86adf9d7 | 4751 | |
86adf9d7 ML |
4752 | ret = skl_update_scaler(crtc_state, force_detach, |
4753 | drm_plane_index(&intel_plane->base), | |
4754 | &plane_state->scaler_id, | |
4755 | plane_state->base.rotation, | |
936e71e3 VS |
4756 | drm_rect_width(&plane_state->base.src) >> 16, |
4757 | drm_rect_height(&plane_state->base.src) >> 16, | |
4758 | drm_rect_width(&plane_state->base.dst), | |
4759 | drm_rect_height(&plane_state->base.dst)); | |
86adf9d7 ML |
4760 | |
4761 | if (ret || plane_state->scaler_id < 0) | |
4762 | return ret; | |
4763 | ||
a1b2278e | 4764 | /* check colorkey */ |
818ed961 | 4765 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
72660ce0 VS |
4766 | DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed", |
4767 | intel_plane->base.base.id, | |
4768 | intel_plane->base.name); | |
a1b2278e CK |
4769 | return -EINVAL; |
4770 | } | |
4771 | ||
4772 | /* Check src format */ | |
86adf9d7 ML |
4773 | switch (fb->pixel_format) { |
4774 | case DRM_FORMAT_RGB565: | |
4775 | case DRM_FORMAT_XBGR8888: | |
4776 | case DRM_FORMAT_XRGB8888: | |
4777 | case DRM_FORMAT_ABGR8888: | |
4778 | case DRM_FORMAT_ARGB8888: | |
4779 | case DRM_FORMAT_XRGB2101010: | |
4780 | case DRM_FORMAT_XBGR2101010: | |
4781 | case DRM_FORMAT_YUYV: | |
4782 | case DRM_FORMAT_YVYU: | |
4783 | case DRM_FORMAT_UYVY: | |
4784 | case DRM_FORMAT_VYUY: | |
4785 | break; | |
4786 | default: | |
72660ce0 VS |
4787 | DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n", |
4788 | intel_plane->base.base.id, intel_plane->base.name, | |
4789 | fb->base.id, fb->pixel_format); | |
86adf9d7 | 4790 | return -EINVAL; |
a1b2278e CK |
4791 | } |
4792 | ||
a1b2278e CK |
4793 | return 0; |
4794 | } | |
4795 | ||
e435d6e5 ML |
4796 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4797 | { | |
4798 | int i; | |
4799 | ||
4800 | for (i = 0; i < crtc->num_scalers; i++) | |
4801 | skl_detach_scaler(crtc, i); | |
4802 | } | |
4803 | ||
4804 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4805 | { |
4806 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4807 | struct drm_i915_private *dev_priv = to_i915(dev); |
bd2e244f | 4808 | int pipe = crtc->pipe; |
a1b2278e CK |
4809 | struct intel_crtc_scaler_state *scaler_state = |
4810 | &crtc->config->scaler_state; | |
4811 | ||
4812 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4813 | ||
6e3c9717 | 4814 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4815 | int id; |
4816 | ||
4817 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4818 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4819 | return; | |
4820 | } | |
4821 | ||
4822 | id = scaler_state->scaler_id; | |
4823 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4824 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4825 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4826 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4827 | ||
4828 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4829 | } |
4830 | } | |
4831 | ||
b074cec8 JB |
4832 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4833 | { | |
4834 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4835 | struct drm_i915_private *dev_priv = to_i915(dev); |
b074cec8 JB |
4836 | int pipe = crtc->pipe; |
4837 | ||
6e3c9717 | 4838 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4839 | /* Force use of hard-coded filter coefficients |
4840 | * as some pre-programmed values are broken, | |
4841 | * e.g. x201. | |
4842 | */ | |
fd6b8f43 | 4843 | if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) |
b074cec8 JB |
4844 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | |
4845 | PF_PIPE_SEL_IVB(pipe)); | |
4846 | else | |
4847 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4848 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4849 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4850 | } |
4851 | } | |
4852 | ||
20bc8673 | 4853 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4854 | { |
cea165c3 | 4855 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4856 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 4857 | |
6e3c9717 | 4858 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4859 | return; |
4860 | ||
307e4498 ML |
4861 | /* |
4862 | * We can only enable IPS after we enable a plane and wait for a vblank | |
4863 | * This function is called from post_plane_update, which is run after | |
4864 | * a vblank wait. | |
4865 | */ | |
cea165c3 | 4866 | |
d77e4531 | 4867 | assert_plane_enabled(dev_priv, crtc->plane); |
8652744b | 4868 | if (IS_BROADWELL(dev_priv)) { |
2a114cc1 BW |
4869 | mutex_lock(&dev_priv->rps.hw_lock); |
4870 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4871 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4872 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4873 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4874 | * mailbox." Moreover, the mailbox may return a bogus state, |
4875 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4876 | */ |
4877 | } else { | |
4878 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4879 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4880 | * is essentially intel_wait_for_vblank. If we don't have this | |
4881 | * and don't wait for vblanks until the end of crtc_enable, then | |
4882 | * the HW state readout code will complain that the expected | |
4883 | * IPS_CTL value is not the one we read. */ | |
2ec9ba3c CW |
4884 | if (intel_wait_for_register(dev_priv, |
4885 | IPS_CTL, IPS_ENABLE, IPS_ENABLE, | |
4886 | 50)) | |
2a114cc1 BW |
4887 | DRM_ERROR("Timed out waiting for IPS enable\n"); |
4888 | } | |
d77e4531 PZ |
4889 | } |
4890 | ||
20bc8673 | 4891 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4892 | { |
4893 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4894 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 4895 | |
6e3c9717 | 4896 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4897 | return; |
4898 | ||
4899 | assert_plane_enabled(dev_priv, crtc->plane); | |
8652744b | 4900 | if (IS_BROADWELL(dev_priv)) { |
2a114cc1 BW |
4901 | mutex_lock(&dev_priv->rps.hw_lock); |
4902 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4903 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 | 4904 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
b85c1ecf CW |
4905 | if (intel_wait_for_register(dev_priv, |
4906 | IPS_CTL, IPS_ENABLE, 0, | |
4907 | 42)) | |
23d0b130 | 4908 | DRM_ERROR("Timed out waiting for IPS disable\n"); |
e59150dc | 4909 | } else { |
2a114cc1 | 4910 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4911 | POSTING_READ(IPS_CTL); |
4912 | } | |
d77e4531 PZ |
4913 | |
4914 | /* We need to wait for a vblank before we can disable the plane. */ | |
0f0f74bc | 4915 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
d77e4531 PZ |
4916 | } |
4917 | ||
7cac945f | 4918 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4919 | { |
7cac945f | 4920 | if (intel_crtc->overlay) { |
d3eedb1a | 4921 | struct drm_device *dev = intel_crtc->base.dev; |
fac5e23e | 4922 | struct drm_i915_private *dev_priv = to_i915(dev); |
d3eedb1a VS |
4923 | |
4924 | mutex_lock(&dev->struct_mutex); | |
4925 | dev_priv->mm.interruptible = false; | |
4926 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4927 | dev_priv->mm.interruptible = true; | |
4928 | mutex_unlock(&dev->struct_mutex); | |
4929 | } | |
4930 | ||
4931 | /* Let userspace switch the overlay on again. In most cases userspace | |
4932 | * has to recompute where to put it anyway. | |
4933 | */ | |
4934 | } | |
4935 | ||
87d4300a ML |
4936 | /** |
4937 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4938 | * @crtc: the CRTC whose primary plane was just enabled | |
4939 | * | |
4940 | * Performs potentially sleeping operations that must be done after the primary | |
4941 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4942 | * called due to an explicit primary plane update, or due to an implicit | |
4943 | * re-enable that is caused when a sprite plane is updated to no longer | |
4944 | * completely hide the primary plane. | |
4945 | */ | |
4946 | static void | |
4947 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4948 | { |
4949 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4950 | struct drm_i915_private *dev_priv = to_i915(dev); |
a5c4d7bc VS |
4951 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4952 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4953 | |
87d4300a ML |
4954 | /* |
4955 | * FIXME IPS should be fine as long as one plane is | |
4956 | * enabled, but in practice it seems to have problems | |
4957 | * when going from primary only to sprite only and vice | |
4958 | * versa. | |
4959 | */ | |
a5c4d7bc VS |
4960 | hsw_enable_ips(intel_crtc); |
4961 | ||
f99d7069 | 4962 | /* |
87d4300a ML |
4963 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4964 | * So don't enable underrun reporting before at least some planes | |
4965 | * are enabled. | |
4966 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4967 | * but leave the pipe running. | |
f99d7069 | 4968 | */ |
5db94019 | 4969 | if (IS_GEN2(dev_priv)) |
87d4300a ML |
4970 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4971 | ||
aca7b684 VS |
4972 | /* Underruns don't always raise interrupts, so check manually. */ |
4973 | intel_check_cpu_fifo_underruns(dev_priv); | |
4974 | intel_check_pch_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4975 | } |
4976 | ||
2622a081 | 4977 | /* FIXME move all this to pre_plane_update() with proper state tracking */ |
87d4300a ML |
4978 | static void |
4979 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4980 | { |
4981 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4982 | struct drm_i915_private *dev_priv = to_i915(dev); |
a5c4d7bc VS |
4983 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4984 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4985 | |
87d4300a ML |
4986 | /* |
4987 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4988 | * So diasble underrun reporting before all the planes get disabled. | |
4989 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4990 | * but leave the pipe running. | |
4991 | */ | |
5db94019 | 4992 | if (IS_GEN2(dev_priv)) |
87d4300a | 4993 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
a5c4d7bc | 4994 | |
2622a081 VS |
4995 | /* |
4996 | * FIXME IPS should be fine as long as one plane is | |
4997 | * enabled, but in practice it seems to have problems | |
4998 | * when going from primary only to sprite only and vice | |
4999 | * versa. | |
5000 | */ | |
5001 | hsw_disable_ips(intel_crtc); | |
5002 | } | |
5003 | ||
5004 | /* FIXME get rid of this and use pre_plane_update */ | |
5005 | static void | |
5006 | intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) | |
5007 | { | |
5008 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 5009 | struct drm_i915_private *dev_priv = to_i915(dev); |
2622a081 VS |
5010 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5011 | int pipe = intel_crtc->pipe; | |
5012 | ||
5013 | intel_pre_disable_primary(crtc); | |
5014 | ||
87d4300a ML |
5015 | /* |
5016 | * Vblank time updates from the shadow to live plane control register | |
5017 | * are blocked if the memory self-refresh mode is active at that | |
5018 | * moment. So to make sure the plane gets truly disabled, disable | |
5019 | * first the self-refresh mode. The self-refresh enable bit in turn | |
5020 | * will be checked/applied by the HW only at the next frame start | |
5021 | * event which is after the vblank start event, so we need to have a | |
5022 | * wait-for-vblank between disabling the plane and the pipe. | |
5023 | */ | |
11a85d6a VS |
5024 | if (HAS_GMCH_DISPLAY(dev_priv) && |
5025 | intel_set_memory_cxsr(dev_priv, false)) | |
0f0f74bc | 5026 | intel_wait_for_vblank(dev_priv, pipe); |
87d4300a ML |
5027 | } |
5028 | ||
5a21b665 DV |
5029 | static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) |
5030 | { | |
5031 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); | |
5032 | struct drm_atomic_state *old_state = old_crtc_state->base.state; | |
5033 | struct intel_crtc_state *pipe_config = | |
5034 | to_intel_crtc_state(crtc->base.state); | |
5a21b665 DV |
5035 | struct drm_plane *primary = crtc->base.primary; |
5036 | struct drm_plane_state *old_pri_state = | |
5037 | drm_atomic_get_existing_plane_state(old_state, primary); | |
5038 | ||
5748b6a1 | 5039 | intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits); |
5a21b665 DV |
5040 | |
5041 | crtc->wm.cxsr_allowed = true; | |
5042 | ||
5043 | if (pipe_config->update_wm_post && pipe_config->base.active) | |
432081bc | 5044 | intel_update_watermarks(crtc); |
5a21b665 DV |
5045 | |
5046 | if (old_pri_state) { | |
5047 | struct intel_plane_state *primary_state = | |
5048 | to_intel_plane_state(primary->state); | |
5049 | struct intel_plane_state *old_primary_state = | |
5050 | to_intel_plane_state(old_pri_state); | |
5051 | ||
5052 | intel_fbc_post_update(crtc); | |
5053 | ||
936e71e3 | 5054 | if (primary_state->base.visible && |
5a21b665 | 5055 | (needs_modeset(&pipe_config->base) || |
936e71e3 | 5056 | !old_primary_state->base.visible)) |
5a21b665 DV |
5057 | intel_post_enable_primary(&crtc->base); |
5058 | } | |
5059 | } | |
5060 | ||
5c74cd73 | 5061 | static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state) |
ac21b225 | 5062 | { |
5c74cd73 | 5063 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
ac21b225 | 5064 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 5065 | struct drm_i915_private *dev_priv = to_i915(dev); |
ab1d3a0e ML |
5066 | struct intel_crtc_state *pipe_config = |
5067 | to_intel_crtc_state(crtc->base.state); | |
5c74cd73 ML |
5068 | struct drm_atomic_state *old_state = old_crtc_state->base.state; |
5069 | struct drm_plane *primary = crtc->base.primary; | |
5070 | struct drm_plane_state *old_pri_state = | |
5071 | drm_atomic_get_existing_plane_state(old_state, primary); | |
5072 | bool modeset = needs_modeset(&pipe_config->base); | |
ccf010fb ML |
5073 | struct intel_atomic_state *old_intel_state = |
5074 | to_intel_atomic_state(old_state); | |
ac21b225 | 5075 | |
5c74cd73 ML |
5076 | if (old_pri_state) { |
5077 | struct intel_plane_state *primary_state = | |
5078 | to_intel_plane_state(primary->state); | |
5079 | struct intel_plane_state *old_primary_state = | |
5080 | to_intel_plane_state(old_pri_state); | |
5081 | ||
faf68d92 | 5082 | intel_fbc_pre_update(crtc, pipe_config, primary_state); |
31ae71fc | 5083 | |
936e71e3 VS |
5084 | if (old_primary_state->base.visible && |
5085 | (modeset || !primary_state->base.visible)) | |
5c74cd73 ML |
5086 | intel_pre_disable_primary(&crtc->base); |
5087 | } | |
852eb00d | 5088 | |
49cff963 | 5089 | if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev_priv)) { |
852eb00d | 5090 | crtc->wm.cxsr_allowed = false; |
2dfd178d | 5091 | |
2622a081 VS |
5092 | /* |
5093 | * Vblank time updates from the shadow to live plane control register | |
5094 | * are blocked if the memory self-refresh mode is active at that | |
5095 | * moment. So to make sure the plane gets truly disabled, disable | |
5096 | * first the self-refresh mode. The self-refresh enable bit in turn | |
5097 | * will be checked/applied by the HW only at the next frame start | |
5098 | * event which is after the vblank start event, so we need to have a | |
5099 | * wait-for-vblank between disabling the plane and the pipe. | |
5100 | */ | |
11a85d6a VS |
5101 | if (old_crtc_state->base.active && |
5102 | intel_set_memory_cxsr(dev_priv, false)) | |
0f0f74bc | 5103 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
852eb00d | 5104 | } |
92826fcd | 5105 | |
ed4a6a7c MR |
5106 | /* |
5107 | * IVB workaround: must disable low power watermarks for at least | |
5108 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
5109 | * when scaling is disabled. | |
5110 | * | |
5111 | * WaCxSRDisabledForSpriteScaling:ivb | |
5112 | */ | |
ddd2b792 | 5113 | if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev)) |
0f0f74bc | 5114 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
ed4a6a7c MR |
5115 | |
5116 | /* | |
5117 | * If we're doing a modeset, we're done. No need to do any pre-vblank | |
5118 | * watermark programming here. | |
5119 | */ | |
5120 | if (needs_modeset(&pipe_config->base)) | |
5121 | return; | |
5122 | ||
5123 | /* | |
5124 | * For platforms that support atomic watermarks, program the | |
5125 | * 'intermediate' watermarks immediately. On pre-gen9 platforms, these | |
5126 | * will be the intermediate values that are safe for both pre- and | |
5127 | * post- vblank; when vblank happens, the 'active' values will be set | |
5128 | * to the final 'target' values and we'll do this again to get the | |
5129 | * optimal watermarks. For gen9+ platforms, the values we program here | |
5130 | * will be the final target values which will get automatically latched | |
5131 | * at vblank time; no further programming will be necessary. | |
5132 | * | |
5133 | * If a platform hasn't been transitioned to atomic watermarks yet, | |
5134 | * we'll continue to update watermarks the old way, if flags tell | |
5135 | * us to. | |
5136 | */ | |
5137 | if (dev_priv->display.initial_watermarks != NULL) | |
ccf010fb ML |
5138 | dev_priv->display.initial_watermarks(old_intel_state, |
5139 | pipe_config); | |
caed361d | 5140 | else if (pipe_config->update_wm_pre) |
432081bc | 5141 | intel_update_watermarks(crtc); |
ac21b225 ML |
5142 | } |
5143 | ||
d032ffa0 | 5144 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
5145 | { |
5146 | struct drm_device *dev = crtc->dev; | |
5147 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 5148 | struct drm_plane *p; |
87d4300a ML |
5149 | int pipe = intel_crtc->pipe; |
5150 | ||
7cac945f | 5151 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 5152 | |
d032ffa0 ML |
5153 | drm_for_each_plane_mask(p, dev, plane_mask) |
5154 | to_intel_plane(p)->disable_plane(p, crtc); | |
f98551ae | 5155 | |
f99d7069 DV |
5156 | /* |
5157 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
5158 | * to compute the mask of flip planes precisely. For the time being | |
5159 | * consider this a flip to a NULL plane. | |
5160 | */ | |
5748b6a1 | 5161 | intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe)); |
a5c4d7bc VS |
5162 | } |
5163 | ||
fb1c98b1 | 5164 | static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc, |
fd6bbda9 | 5165 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5166 | struct drm_atomic_state *old_state) |
5167 | { | |
5168 | struct drm_connector_state *old_conn_state; | |
5169 | struct drm_connector *conn; | |
5170 | int i; | |
5171 | ||
5172 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5173 | struct drm_connector_state *conn_state = conn->state; | |
5174 | struct intel_encoder *encoder = | |
5175 | to_intel_encoder(conn_state->best_encoder); | |
5176 | ||
5177 | if (conn_state->crtc != crtc) | |
5178 | continue; | |
5179 | ||
5180 | if (encoder->pre_pll_enable) | |
fd6bbda9 | 5181 | encoder->pre_pll_enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5182 | } |
5183 | } | |
5184 | ||
5185 | static void intel_encoders_pre_enable(struct drm_crtc *crtc, | |
fd6bbda9 | 5186 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5187 | struct drm_atomic_state *old_state) |
5188 | { | |
5189 | struct drm_connector_state *old_conn_state; | |
5190 | struct drm_connector *conn; | |
5191 | int i; | |
5192 | ||
5193 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5194 | struct drm_connector_state *conn_state = conn->state; | |
5195 | struct intel_encoder *encoder = | |
5196 | to_intel_encoder(conn_state->best_encoder); | |
5197 | ||
5198 | if (conn_state->crtc != crtc) | |
5199 | continue; | |
5200 | ||
5201 | if (encoder->pre_enable) | |
fd6bbda9 | 5202 | encoder->pre_enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5203 | } |
5204 | } | |
5205 | ||
5206 | static void intel_encoders_enable(struct drm_crtc *crtc, | |
fd6bbda9 | 5207 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5208 | struct drm_atomic_state *old_state) |
5209 | { | |
5210 | struct drm_connector_state *old_conn_state; | |
5211 | struct drm_connector *conn; | |
5212 | int i; | |
5213 | ||
5214 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5215 | struct drm_connector_state *conn_state = conn->state; | |
5216 | struct intel_encoder *encoder = | |
5217 | to_intel_encoder(conn_state->best_encoder); | |
5218 | ||
5219 | if (conn_state->crtc != crtc) | |
5220 | continue; | |
5221 | ||
fd6bbda9 | 5222 | encoder->enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5223 | intel_opregion_notify_encoder(encoder, true); |
5224 | } | |
5225 | } | |
5226 | ||
5227 | static void intel_encoders_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5228 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5229 | struct drm_atomic_state *old_state) |
5230 | { | |
5231 | struct drm_connector_state *old_conn_state; | |
5232 | struct drm_connector *conn; | |
5233 | int i; | |
5234 | ||
5235 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5236 | struct intel_encoder *encoder = | |
5237 | to_intel_encoder(old_conn_state->best_encoder); | |
5238 | ||
5239 | if (old_conn_state->crtc != crtc) | |
5240 | continue; | |
5241 | ||
5242 | intel_opregion_notify_encoder(encoder, false); | |
fd6bbda9 | 5243 | encoder->disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5244 | } |
5245 | } | |
5246 | ||
5247 | static void intel_encoders_post_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5248 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5249 | struct drm_atomic_state *old_state) |
5250 | { | |
5251 | struct drm_connector_state *old_conn_state; | |
5252 | struct drm_connector *conn; | |
5253 | int i; | |
5254 | ||
5255 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5256 | struct intel_encoder *encoder = | |
5257 | to_intel_encoder(old_conn_state->best_encoder); | |
5258 | ||
5259 | if (old_conn_state->crtc != crtc) | |
5260 | continue; | |
5261 | ||
5262 | if (encoder->post_disable) | |
fd6bbda9 | 5263 | encoder->post_disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5264 | } |
5265 | } | |
5266 | ||
5267 | static void intel_encoders_post_pll_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5268 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5269 | struct drm_atomic_state *old_state) |
5270 | { | |
5271 | struct drm_connector_state *old_conn_state; | |
5272 | struct drm_connector *conn; | |
5273 | int i; | |
5274 | ||
5275 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5276 | struct intel_encoder *encoder = | |
5277 | to_intel_encoder(old_conn_state->best_encoder); | |
5278 | ||
5279 | if (old_conn_state->crtc != crtc) | |
5280 | continue; | |
5281 | ||
5282 | if (encoder->post_pll_disable) | |
fd6bbda9 | 5283 | encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5284 | } |
5285 | } | |
5286 | ||
4a806558 ML |
5287 | static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config, |
5288 | struct drm_atomic_state *old_state) | |
f67a559d | 5289 | { |
4a806558 | 5290 | struct drm_crtc *crtc = pipe_config->base.crtc; |
f67a559d | 5291 | struct drm_device *dev = crtc->dev; |
fac5e23e | 5292 | struct drm_i915_private *dev_priv = to_i915(dev); |
f67a559d JB |
5293 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5294 | int pipe = intel_crtc->pipe; | |
ccf010fb ML |
5295 | struct intel_atomic_state *old_intel_state = |
5296 | to_intel_atomic_state(old_state); | |
f67a559d | 5297 | |
53d9f4e9 | 5298 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
5299 | return; |
5300 | ||
b2c0593a VS |
5301 | /* |
5302 | * Sometimes spurious CPU pipe underruns happen during FDI | |
5303 | * training, at least with VGA+HDMI cloning. Suppress them. | |
5304 | * | |
5305 | * On ILK we get an occasional spurious CPU pipe underruns | |
5306 | * between eDP port A enable and vdd enable. Also PCH port | |
5307 | * enable seems to result in the occasional CPU pipe underrun. | |
5308 | * | |
5309 | * Spurious PCH underruns also occur during PCH enabling. | |
5310 | */ | |
5311 | if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv)) | |
5312 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
81b088ca VS |
5313 | if (intel_crtc->config->has_pch_encoder) |
5314 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
5315 | ||
6e3c9717 | 5316 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
5317 | intel_prepare_shared_dpll(intel_crtc); |
5318 | ||
37a5650b | 5319 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 5320 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
5321 | |
5322 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 5323 | intel_set_pipe_src_size(intel_crtc); |
29407aab | 5324 | |
6e3c9717 | 5325 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 5326 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5327 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
5328 | } |
5329 | ||
5330 | ironlake_set_pipeconf(crtc); | |
5331 | ||
f67a559d | 5332 | intel_crtc->active = true; |
8664281b | 5333 | |
fd6bbda9 | 5334 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
f67a559d | 5335 | |
6e3c9717 | 5336 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
5337 | /* Note: FDI PLL enabling _must_ be done before we enable the |
5338 | * cpu pipes, hence this is separate from all the other fdi/pch | |
5339 | * enabling. */ | |
88cefb6c | 5340 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
5341 | } else { |
5342 | assert_fdi_tx_disabled(dev_priv, pipe); | |
5343 | assert_fdi_rx_disabled(dev_priv, pipe); | |
5344 | } | |
f67a559d | 5345 | |
b074cec8 | 5346 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 5347 | |
9c54c0dd JB |
5348 | /* |
5349 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5350 | * clocks enabled | |
5351 | */ | |
b95c5321 | 5352 | intel_color_load_luts(&pipe_config->base); |
9c54c0dd | 5353 | |
1d5bf5d9 | 5354 | if (dev_priv->display.initial_watermarks != NULL) |
ccf010fb | 5355 | dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config); |
e1fdc473 | 5356 | intel_enable_pipe(intel_crtc); |
f67a559d | 5357 | |
6e3c9717 | 5358 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 5359 | ironlake_pch_enable(crtc); |
c98e9dcf | 5360 | |
f9b61ff6 DV |
5361 | assert_vblank_disabled(crtc); |
5362 | drm_crtc_vblank_on(crtc); | |
5363 | ||
fd6bbda9 | 5364 | intel_encoders_enable(crtc, pipe_config, old_state); |
61b77ddd | 5365 | |
6e266956 | 5366 | if (HAS_PCH_CPT(dev_priv)) |
a1520318 | 5367 | cpt_verify_modeset(dev, intel_crtc->pipe); |
37ca8d4c VS |
5368 | |
5369 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ | |
5370 | if (intel_crtc->config->has_pch_encoder) | |
0f0f74bc | 5371 | intel_wait_for_vblank(dev_priv, pipe); |
b2c0593a | 5372 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
37ca8d4c | 5373 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 JB |
5374 | } |
5375 | ||
42db64ef PZ |
5376 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
5377 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
5378 | { | |
50a0bc90 | 5379 | return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A; |
42db64ef PZ |
5380 | } |
5381 | ||
4a806558 ML |
5382 | static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, |
5383 | struct drm_atomic_state *old_state) | |
4f771f10 | 5384 | { |
4a806558 | 5385 | struct drm_crtc *crtc = pipe_config->base.crtc; |
6315b5d3 | 5386 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
4f771f10 | 5387 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
99d736a2 | 5388 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4d1de975 | 5389 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ccf010fb ML |
5390 | struct intel_atomic_state *old_intel_state = |
5391 | to_intel_atomic_state(old_state); | |
4f771f10 | 5392 | |
53d9f4e9 | 5393 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
5394 | return; |
5395 | ||
81b088ca VS |
5396 | if (intel_crtc->config->has_pch_encoder) |
5397 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5398 | false); | |
5399 | ||
fd6bbda9 | 5400 | intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); |
95a7a2ae | 5401 | |
8106ddbd | 5402 | if (intel_crtc->config->shared_dpll) |
df8ad70c DV |
5403 | intel_enable_shared_dpll(intel_crtc); |
5404 | ||
37a5650b | 5405 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 5406 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 | 5407 | |
d7edc4e5 | 5408 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 JN |
5409 | intel_set_pipe_timings(intel_crtc); |
5410 | ||
bc58be60 | 5411 | intel_set_pipe_src_size(intel_crtc); |
229fca97 | 5412 | |
4d1de975 JN |
5413 | if (cpu_transcoder != TRANSCODER_EDP && |
5414 | !transcoder_is_dsi(cpu_transcoder)) { | |
5415 | I915_WRITE(PIPE_MULT(cpu_transcoder), | |
6e3c9717 | 5416 | intel_crtc->config->pixel_multiplier - 1); |
ebb69c95 CT |
5417 | } |
5418 | ||
6e3c9717 | 5419 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 5420 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5421 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
5422 | } |
5423 | ||
d7edc4e5 | 5424 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 JN |
5425 | haswell_set_pipeconf(crtc); |
5426 | ||
391bf048 | 5427 | haswell_set_pipemisc(crtc); |
229fca97 | 5428 | |
b95c5321 | 5429 | intel_color_set_csc(&pipe_config->base); |
229fca97 | 5430 | |
4f771f10 | 5431 | intel_crtc->active = true; |
8664281b | 5432 | |
6b698516 DV |
5433 | if (intel_crtc->config->has_pch_encoder) |
5434 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
5435 | else | |
5436 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
5437 | ||
fd6bbda9 | 5438 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
4f771f10 | 5439 | |
d2d65408 | 5440 | if (intel_crtc->config->has_pch_encoder) |
4fe9467d | 5441 | dev_priv->display.fdi_link_train(crtc); |
4fe9467d | 5442 | |
d7edc4e5 | 5443 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5444 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 5445 | |
6315b5d3 | 5446 | if (INTEL_GEN(dev_priv) >= 9) |
e435d6e5 | 5447 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 5448 | else |
1c132b44 | 5449 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
5450 | |
5451 | /* | |
5452 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5453 | * clocks enabled | |
5454 | */ | |
b95c5321 | 5455 | intel_color_load_luts(&pipe_config->base); |
4f771f10 | 5456 | |
1f544388 | 5457 | intel_ddi_set_pipe_settings(crtc); |
d7edc4e5 | 5458 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5459 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 5460 | |
1d5bf5d9 | 5461 | if (dev_priv->display.initial_watermarks != NULL) |
3125d39f | 5462 | dev_priv->display.initial_watermarks(old_intel_state, pipe_config); |
4d1de975 JN |
5463 | |
5464 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ | |
d7edc4e5 | 5465 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 | 5466 | intel_enable_pipe(intel_crtc); |
42db64ef | 5467 | |
6e3c9717 | 5468 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 5469 | lpt_pch_enable(crtc); |
4f771f10 | 5470 | |
0037071d | 5471 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST)) |
0e32b39c DA |
5472 | intel_ddi_set_vc_payload_alloc(crtc, true); |
5473 | ||
f9b61ff6 DV |
5474 | assert_vblank_disabled(crtc); |
5475 | drm_crtc_vblank_on(crtc); | |
5476 | ||
fd6bbda9 | 5477 | intel_encoders_enable(crtc, pipe_config, old_state); |
4f771f10 | 5478 | |
6b698516 | 5479 | if (intel_crtc->config->has_pch_encoder) { |
0f0f74bc VS |
5480 | intel_wait_for_vblank(dev_priv, pipe); |
5481 | intel_wait_for_vblank(dev_priv, pipe); | |
6b698516 | 5482 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
d2d65408 VS |
5483 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5484 | true); | |
6b698516 | 5485 | } |
d2d65408 | 5486 | |
e4916946 PZ |
5487 | /* If we change the relative order between pipe/planes enabling, we need |
5488 | * to change the workaround. */ | |
99d736a2 | 5489 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
772c2a51 | 5490 | if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { |
0f0f74bc VS |
5491 | intel_wait_for_vblank(dev_priv, hsw_workaround_pipe); |
5492 | intel_wait_for_vblank(dev_priv, hsw_workaround_pipe); | |
99d736a2 | 5493 | } |
4f771f10 PZ |
5494 | } |
5495 | ||
bfd16b2a | 5496 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
5497 | { |
5498 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 5499 | struct drm_i915_private *dev_priv = to_i915(dev); |
3f8dce3a DV |
5500 | int pipe = crtc->pipe; |
5501 | ||
5502 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
5503 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 5504 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
5505 | I915_WRITE(PF_CTL(pipe), 0); |
5506 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
5507 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
5508 | } | |
5509 | } | |
5510 | ||
4a806558 ML |
5511 | static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state, |
5512 | struct drm_atomic_state *old_state) | |
6be4a607 | 5513 | { |
4a806558 | 5514 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
6be4a607 | 5515 | struct drm_device *dev = crtc->dev; |
fac5e23e | 5516 | struct drm_i915_private *dev_priv = to_i915(dev); |
6be4a607 JB |
5517 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5518 | int pipe = intel_crtc->pipe; | |
b52eb4dc | 5519 | |
b2c0593a VS |
5520 | /* |
5521 | * Sometimes spurious CPU pipe underruns happen when the | |
5522 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
5523 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
5524 | */ | |
5525 | if (intel_crtc->config->has_pch_encoder) { | |
5526 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
37ca8d4c | 5527 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
b2c0593a | 5528 | } |
37ca8d4c | 5529 | |
fd6bbda9 | 5530 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
ea9d758d | 5531 | |
f9b61ff6 DV |
5532 | drm_crtc_vblank_off(crtc); |
5533 | assert_vblank_disabled(crtc); | |
5534 | ||
575f7ab7 | 5535 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5536 | |
bfd16b2a | 5537 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 5538 | |
b2c0593a | 5539 | if (intel_crtc->config->has_pch_encoder) |
5a74f70a VS |
5540 | ironlake_fdi_disable(crtc); |
5541 | ||
fd6bbda9 | 5542 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
2c07245f | 5543 | |
6e3c9717 | 5544 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5545 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5546 | |
6e266956 | 5547 | if (HAS_PCH_CPT(dev_priv)) { |
f0f59a00 VS |
5548 | i915_reg_t reg; |
5549 | u32 temp; | |
5550 | ||
d925c59a DV |
5551 | /* disable TRANS_DP_CTL */ |
5552 | reg = TRANS_DP_CTL(pipe); | |
5553 | temp = I915_READ(reg); | |
5554 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5555 | TRANS_DP_PORT_SEL_MASK); | |
5556 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5557 | I915_WRITE(reg, temp); | |
5558 | ||
5559 | /* disable DPLL_SEL */ | |
5560 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5561 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5562 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5563 | } |
e3421a18 | 5564 | |
d925c59a DV |
5565 | ironlake_fdi_pll_disable(intel_crtc); |
5566 | } | |
81b088ca | 5567 | |
b2c0593a | 5568 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
81b088ca | 5569 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 | 5570 | } |
1b3c7a47 | 5571 | |
4a806558 ML |
5572 | static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state, |
5573 | struct drm_atomic_state *old_state) | |
ee7b9f93 | 5574 | { |
4a806558 | 5575 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
6315b5d3 | 5576 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
ee7b9f93 | 5577 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 5578 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5579 | |
d2d65408 VS |
5580 | if (intel_crtc->config->has_pch_encoder) |
5581 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5582 | false); | |
5583 | ||
fd6bbda9 | 5584 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
4f771f10 | 5585 | |
f9b61ff6 DV |
5586 | drm_crtc_vblank_off(crtc); |
5587 | assert_vblank_disabled(crtc); | |
5588 | ||
4d1de975 | 5589 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ |
d7edc4e5 | 5590 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 | 5591 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5592 | |
0037071d | 5593 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST)) |
a4bf214f VS |
5594 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5595 | ||
d7edc4e5 | 5596 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5597 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5598 | |
6315b5d3 | 5599 | if (INTEL_GEN(dev_priv) >= 9) |
e435d6e5 | 5600 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5601 | else |
bfd16b2a | 5602 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 5603 | |
d7edc4e5 | 5604 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5605 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 5606 | |
fd6bbda9 | 5607 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
81b088ca | 5608 | |
b7076546 | 5609 | if (old_crtc_state->has_pch_encoder) |
81b088ca VS |
5610 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5611 | true); | |
4f771f10 PZ |
5612 | } |
5613 | ||
2dd24552 JB |
5614 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5615 | { | |
5616 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 5617 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 5618 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5619 | |
681a8504 | 5620 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5621 | return; |
5622 | ||
2dd24552 | 5623 | /* |
c0b03411 DV |
5624 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5625 | * according to register description and PRM. | |
2dd24552 | 5626 | */ |
c0b03411 DV |
5627 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5628 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5629 | |
b074cec8 JB |
5630 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5631 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5632 | |
5633 | /* Border color in case we don't scale up to the full screen. Black by | |
5634 | * default, change to something else for debugging. */ | |
5635 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5636 | } |
5637 | ||
d05410f9 DA |
5638 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5639 | { | |
5640 | switch (port) { | |
5641 | case PORT_A: | |
6331a704 | 5642 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
d05410f9 | 5643 | case PORT_B: |
6331a704 | 5644 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
d05410f9 | 5645 | case PORT_C: |
6331a704 | 5646 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
d05410f9 | 5647 | case PORT_D: |
6331a704 | 5648 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
d8e19f99 | 5649 | case PORT_E: |
6331a704 | 5650 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
d05410f9 | 5651 | default: |
b9fec167 | 5652 | MISSING_CASE(port); |
d05410f9 DA |
5653 | return POWER_DOMAIN_PORT_OTHER; |
5654 | } | |
5655 | } | |
5656 | ||
25f78f58 VS |
5657 | static enum intel_display_power_domain port_to_aux_power_domain(enum port port) |
5658 | { | |
5659 | switch (port) { | |
5660 | case PORT_A: | |
5661 | return POWER_DOMAIN_AUX_A; | |
5662 | case PORT_B: | |
5663 | return POWER_DOMAIN_AUX_B; | |
5664 | case PORT_C: | |
5665 | return POWER_DOMAIN_AUX_C; | |
5666 | case PORT_D: | |
5667 | return POWER_DOMAIN_AUX_D; | |
5668 | case PORT_E: | |
5669 | /* FIXME: Check VBT for actual wiring of PORT E */ | |
5670 | return POWER_DOMAIN_AUX_D; | |
5671 | default: | |
b9fec167 | 5672 | MISSING_CASE(port); |
25f78f58 VS |
5673 | return POWER_DOMAIN_AUX_A; |
5674 | } | |
5675 | } | |
5676 | ||
319be8ae ID |
5677 | enum intel_display_power_domain |
5678 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5679 | { | |
4f8036a2 | 5680 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); |
319be8ae ID |
5681 | struct intel_digital_port *intel_dig_port; |
5682 | ||
5683 | switch (intel_encoder->type) { | |
5684 | case INTEL_OUTPUT_UNKNOWN: | |
5685 | /* Only DDI platforms should ever use this output type */ | |
4f8036a2 | 5686 | WARN_ON_ONCE(!HAS_DDI(dev_priv)); |
cca0502b | 5687 | case INTEL_OUTPUT_DP: |
319be8ae ID |
5688 | case INTEL_OUTPUT_HDMI: |
5689 | case INTEL_OUTPUT_EDP: | |
5690 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 5691 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
5692 | case INTEL_OUTPUT_DP_MST: |
5693 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5694 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
5695 | case INTEL_OUTPUT_ANALOG: |
5696 | return POWER_DOMAIN_PORT_CRT; | |
5697 | case INTEL_OUTPUT_DSI: | |
5698 | return POWER_DOMAIN_PORT_DSI; | |
5699 | default: | |
5700 | return POWER_DOMAIN_PORT_OTHER; | |
5701 | } | |
5702 | } | |
5703 | ||
25f78f58 VS |
5704 | enum intel_display_power_domain |
5705 | intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder) | |
5706 | { | |
4f8036a2 | 5707 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); |
25f78f58 VS |
5708 | struct intel_digital_port *intel_dig_port; |
5709 | ||
5710 | switch (intel_encoder->type) { | |
5711 | case INTEL_OUTPUT_UNKNOWN: | |
651174a4 ID |
5712 | case INTEL_OUTPUT_HDMI: |
5713 | /* | |
5714 | * Only DDI platforms should ever use these output types. | |
5715 | * We can get here after the HDMI detect code has already set | |
5716 | * the type of the shared encoder. Since we can't be sure | |
5717 | * what's the status of the given connectors, play safe and | |
5718 | * run the DP detection too. | |
5719 | */ | |
4f8036a2 | 5720 | WARN_ON_ONCE(!HAS_DDI(dev_priv)); |
cca0502b | 5721 | case INTEL_OUTPUT_DP: |
25f78f58 VS |
5722 | case INTEL_OUTPUT_EDP: |
5723 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
5724 | return port_to_aux_power_domain(intel_dig_port->port); | |
5725 | case INTEL_OUTPUT_DP_MST: | |
5726 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5727 | return port_to_aux_power_domain(intel_dig_port->port); | |
5728 | default: | |
b9fec167 | 5729 | MISSING_CASE(intel_encoder->type); |
25f78f58 VS |
5730 | return POWER_DOMAIN_AUX_A; |
5731 | } | |
5732 | } | |
5733 | ||
74bff5f9 ML |
5734 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc, |
5735 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5736 | { |
319be8ae | 5737 | struct drm_device *dev = crtc->dev; |
74bff5f9 | 5738 | struct drm_encoder *encoder; |
319be8ae ID |
5739 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5740 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca | 5741 | unsigned long mask; |
74bff5f9 | 5742 | enum transcoder transcoder = crtc_state->cpu_transcoder; |
77d22dca | 5743 | |
74bff5f9 | 5744 | if (!crtc_state->base.active) |
292b990e ML |
5745 | return 0; |
5746 | ||
77d22dca ID |
5747 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5748 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
74bff5f9 ML |
5749 | if (crtc_state->pch_pfit.enabled || |
5750 | crtc_state->pch_pfit.force_thru) | |
77d22dca ID |
5751 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5752 | ||
74bff5f9 ML |
5753 | drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) { |
5754 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
5755 | ||
319be8ae | 5756 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); |
74bff5f9 | 5757 | } |
319be8ae | 5758 | |
15e7ec29 ML |
5759 | if (crtc_state->shared_dpll) |
5760 | mask |= BIT(POWER_DOMAIN_PLLS); | |
5761 | ||
77d22dca ID |
5762 | return mask; |
5763 | } | |
5764 | ||
74bff5f9 ML |
5765 | static unsigned long |
5766 | modeset_get_crtc_power_domains(struct drm_crtc *crtc, | |
5767 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5768 | { |
fac5e23e | 5769 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
292b990e ML |
5770 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5771 | enum intel_display_power_domain domain; | |
5a21b665 | 5772 | unsigned long domains, new_domains, old_domains; |
77d22dca | 5773 | |
292b990e | 5774 | old_domains = intel_crtc->enabled_power_domains; |
74bff5f9 ML |
5775 | intel_crtc->enabled_power_domains = new_domains = |
5776 | get_crtc_power_domains(crtc, crtc_state); | |
77d22dca | 5777 | |
5a21b665 | 5778 | domains = new_domains & ~old_domains; |
292b990e ML |
5779 | |
5780 | for_each_power_domain(domain, domains) | |
5781 | intel_display_power_get(dev_priv, domain); | |
5782 | ||
5a21b665 | 5783 | return old_domains & ~new_domains; |
292b990e ML |
5784 | } |
5785 | ||
5786 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
5787 | unsigned long domains) | |
5788 | { | |
5789 | enum intel_display_power_domain domain; | |
5790 | ||
5791 | for_each_power_domain(domain, domains) | |
5792 | intel_display_power_put(dev_priv, domain); | |
5793 | } | |
77d22dca | 5794 | |
adafdc6f MK |
5795 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
5796 | { | |
5797 | int max_cdclk_freq = dev_priv->max_cdclk_freq; | |
5798 | ||
09d09386 ACO |
5799 | if (IS_GEMINILAKE(dev_priv)) |
5800 | return 2 * max_cdclk_freq; | |
5801 | else if (INTEL_INFO(dev_priv)->gen >= 9 || | |
5802 | IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
adafdc6f MK |
5803 | return max_cdclk_freq; |
5804 | else if (IS_CHERRYVIEW(dev_priv)) | |
5805 | return max_cdclk_freq*95/100; | |
5806 | else if (INTEL_INFO(dev_priv)->gen < 4) | |
5807 | return 2*max_cdclk_freq*90/100; | |
5808 | else | |
5809 | return max_cdclk_freq*90/100; | |
5810 | } | |
5811 | ||
b2045352 VS |
5812 | static int skl_calc_cdclk(int max_pixclk, int vco); |
5813 | ||
4c75b940 | 5814 | static void intel_update_max_cdclk(struct drm_i915_private *dev_priv) |
560a7ae4 | 5815 | { |
0853723b | 5816 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { |
560a7ae4 | 5817 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; |
b2045352 VS |
5818 | int max_cdclk, vco; |
5819 | ||
5820 | vco = dev_priv->skl_preferred_vco_freq; | |
63911d72 | 5821 | WARN_ON(vco != 8100000 && vco != 8640000); |
560a7ae4 | 5822 | |
b2045352 VS |
5823 | /* |
5824 | * Use the lower (vco 8640) cdclk values as a | |
5825 | * first guess. skl_calc_cdclk() will correct it | |
5826 | * if the preferred vco is 8100 instead. | |
5827 | */ | |
560a7ae4 | 5828 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) |
487ed2e4 | 5829 | max_cdclk = 617143; |
560a7ae4 | 5830 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) |
b2045352 | 5831 | max_cdclk = 540000; |
560a7ae4 | 5832 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) |
b2045352 | 5833 | max_cdclk = 432000; |
560a7ae4 | 5834 | else |
487ed2e4 | 5835 | max_cdclk = 308571; |
b2045352 VS |
5836 | |
5837 | dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); | |
89b3c3c7 ACO |
5838 | } else if (IS_GEMINILAKE(dev_priv)) { |
5839 | dev_priv->max_cdclk_freq = 316800; | |
e2d214ae | 5840 | } else if (IS_BROXTON(dev_priv)) { |
281c114f | 5841 | dev_priv->max_cdclk_freq = 624000; |
8652744b | 5842 | } else if (IS_BROADWELL(dev_priv)) { |
560a7ae4 DL |
5843 | /* |
5844 | * FIXME with extra cooling we can allow | |
5845 | * 540 MHz for ULX and 675 Mhz for ULT. | |
5846 | * How can we know if extra cooling is | |
5847 | * available? PCI ID, VTB, something else? | |
5848 | */ | |
5849 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
5850 | dev_priv->max_cdclk_freq = 450000; | |
50a0bc90 | 5851 | else if (IS_BDW_ULX(dev_priv)) |
560a7ae4 | 5852 | dev_priv->max_cdclk_freq = 450000; |
50a0bc90 | 5853 | else if (IS_BDW_ULT(dev_priv)) |
560a7ae4 DL |
5854 | dev_priv->max_cdclk_freq = 540000; |
5855 | else | |
5856 | dev_priv->max_cdclk_freq = 675000; | |
920a14b2 | 5857 | } else if (IS_CHERRYVIEW(dev_priv)) { |
0904deaf | 5858 | dev_priv->max_cdclk_freq = 320000; |
11a914c2 | 5859 | } else if (IS_VALLEYVIEW(dev_priv)) { |
560a7ae4 DL |
5860 | dev_priv->max_cdclk_freq = 400000; |
5861 | } else { | |
5862 | /* otherwise assume cdclk is fixed */ | |
5863 | dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; | |
5864 | } | |
5865 | ||
adafdc6f MK |
5866 | dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); |
5867 | ||
560a7ae4 DL |
5868 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", |
5869 | dev_priv->max_cdclk_freq); | |
adafdc6f MK |
5870 | |
5871 | DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", | |
5872 | dev_priv->max_dotclk_freq); | |
560a7ae4 DL |
5873 | } |
5874 | ||
4c75b940 | 5875 | static void intel_update_cdclk(struct drm_i915_private *dev_priv) |
560a7ae4 | 5876 | { |
1353c4fb | 5877 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev_priv); |
2f2a121a | 5878 | |
83d7c81f | 5879 | if (INTEL_GEN(dev_priv) >= 9) |
709e05c3 VS |
5880 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n", |
5881 | dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco, | |
5882 | dev_priv->cdclk_pll.ref); | |
2f2a121a VS |
5883 | else |
5884 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", | |
5885 | dev_priv->cdclk_freq); | |
560a7ae4 DL |
5886 | |
5887 | /* | |
b5d99ff9 VS |
5888 | * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): |
5889 | * Programmng [sic] note: bit[9:2] should be programmed to the number | |
5890 | * of cdclk that generates 4MHz reference clock freq which is used to | |
5891 | * generate GMBus clock. This will vary with the cdclk freq. | |
560a7ae4 | 5892 | */ |
b5d99ff9 | 5893 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
560a7ae4 | 5894 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); |
560a7ae4 DL |
5895 | } |
5896 | ||
92891e45 VS |
5897 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ |
5898 | static int skl_cdclk_decimal(int cdclk) | |
5899 | { | |
5900 | return DIV_ROUND_CLOSEST(cdclk - 1000, 500); | |
5901 | } | |
5902 | ||
5f199dfa VS |
5903 | static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk) |
5904 | { | |
5905 | int ratio; | |
5906 | ||
5907 | if (cdclk == dev_priv->cdclk_pll.ref) | |
5908 | return 0; | |
5909 | ||
5910 | switch (cdclk) { | |
5911 | default: | |
5912 | MISSING_CASE(cdclk); | |
5913 | case 144000: | |
5914 | case 288000: | |
5915 | case 384000: | |
5916 | case 576000: | |
5917 | ratio = 60; | |
5918 | break; | |
5919 | case 624000: | |
5920 | ratio = 65; | |
5921 | break; | |
5922 | } | |
5923 | ||
5924 | return dev_priv->cdclk_pll.ref * ratio; | |
5925 | } | |
5926 | ||
89b3c3c7 ACO |
5927 | static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk) |
5928 | { | |
5929 | int ratio; | |
5930 | ||
5931 | if (cdclk == dev_priv->cdclk_pll.ref) | |
5932 | return 0; | |
5933 | ||
5934 | switch (cdclk) { | |
5935 | default: | |
5936 | MISSING_CASE(cdclk); | |
5937 | case 79200: | |
5938 | case 158400: | |
5939 | case 316800: | |
5940 | ratio = 33; | |
5941 | break; | |
5942 | } | |
5943 | ||
5944 | return dev_priv->cdclk_pll.ref * ratio; | |
5945 | } | |
5946 | ||
2b73001e VS |
5947 | static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) |
5948 | { | |
5949 | I915_WRITE(BXT_DE_PLL_ENABLE, 0); | |
5950 | ||
5951 | /* Timeout 200us */ | |
95cac283 CW |
5952 | if (intel_wait_for_register(dev_priv, |
5953 | BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0, | |
5954 | 1)) | |
2b73001e | 5955 | DRM_ERROR("timeout waiting for DE PLL unlock\n"); |
83d7c81f VS |
5956 | |
5957 | dev_priv->cdclk_pll.vco = 0; | |
2b73001e VS |
5958 | } |
5959 | ||
5f199dfa | 5960 | static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) |
2b73001e | 5961 | { |
5f199dfa | 5962 | int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref); |
2b73001e VS |
5963 | u32 val; |
5964 | ||
5965 | val = I915_READ(BXT_DE_PLL_CTL); | |
5966 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5f199dfa | 5967 | val |= BXT_DE_PLL_RATIO(ratio); |
2b73001e VS |
5968 | I915_WRITE(BXT_DE_PLL_CTL, val); |
5969 | ||
5970 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5971 | ||
5972 | /* Timeout 200us */ | |
e084e1b9 CW |
5973 | if (intel_wait_for_register(dev_priv, |
5974 | BXT_DE_PLL_ENABLE, | |
5975 | BXT_DE_PLL_LOCK, | |
5976 | BXT_DE_PLL_LOCK, | |
5977 | 1)) | |
2b73001e | 5978 | DRM_ERROR("timeout waiting for DE PLL lock\n"); |
83d7c81f | 5979 | |
5f199dfa | 5980 | dev_priv->cdclk_pll.vco = vco; |
2b73001e VS |
5981 | } |
5982 | ||
324513c0 | 5983 | static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk) |
f8437dd1 | 5984 | { |
5f199dfa VS |
5985 | u32 val, divider; |
5986 | int vco, ret; | |
f8437dd1 | 5987 | |
89b3c3c7 ACO |
5988 | if (IS_GEMINILAKE(dev_priv)) |
5989 | vco = glk_de_pll_vco(dev_priv, cdclk); | |
5990 | else | |
5991 | vco = bxt_de_pll_vco(dev_priv, cdclk); | |
5f199dfa VS |
5992 | |
5993 | DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco); | |
5994 | ||
5995 | /* cdclk = vco / 2 / div{1,1.5,2,4} */ | |
5996 | switch (DIV_ROUND_CLOSEST(vco, cdclk)) { | |
5997 | case 8: | |
f8437dd1 | 5998 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; |
f8437dd1 | 5999 | break; |
5f199dfa | 6000 | case 4: |
f8437dd1 | 6001 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; |
f8437dd1 | 6002 | break; |
5f199dfa | 6003 | case 3: |
89b3c3c7 | 6004 | WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n"); |
f8437dd1 | 6005 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; |
f8437dd1 | 6006 | break; |
5f199dfa | 6007 | case 2: |
f8437dd1 | 6008 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; |
f8437dd1 VK |
6009 | break; |
6010 | default: | |
5f199dfa VS |
6011 | WARN_ON(cdclk != dev_priv->cdclk_pll.ref); |
6012 | WARN_ON(vco != 0); | |
f8437dd1 | 6013 | |
5f199dfa VS |
6014 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; |
6015 | break; | |
f8437dd1 VK |
6016 | } |
6017 | ||
f8437dd1 | 6018 | /* Inform power controller of upcoming frequency change */ |
5f199dfa | 6019 | mutex_lock(&dev_priv->rps.hw_lock); |
f8437dd1 VK |
6020 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, |
6021 | 0x80000000); | |
6022 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6023 | ||
6024 | if (ret) { | |
6025 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
9ef56154 | 6026 | ret, cdclk); |
f8437dd1 VK |
6027 | return; |
6028 | } | |
6029 | ||
5f199dfa VS |
6030 | if (dev_priv->cdclk_pll.vco != 0 && |
6031 | dev_priv->cdclk_pll.vco != vco) | |
2b73001e | 6032 | bxt_de_pll_disable(dev_priv); |
f8437dd1 | 6033 | |
5f199dfa VS |
6034 | if (dev_priv->cdclk_pll.vco != vco) |
6035 | bxt_de_pll_enable(dev_priv, vco); | |
f8437dd1 | 6036 | |
5f199dfa VS |
6037 | val = divider | skl_cdclk_decimal(cdclk); |
6038 | /* | |
6039 | * FIXME if only the cd2x divider needs changing, it could be done | |
6040 | * without shutting off the pipe (if only one pipe is active). | |
6041 | */ | |
6042 | val |= BXT_CDCLK_CD2X_PIPE_NONE; | |
6043 | /* | |
6044 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
6045 | * enable otherwise. | |
6046 | */ | |
6047 | if (cdclk >= 500000) | |
6048 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
6049 | I915_WRITE(CDCLK_CTL, val); | |
f8437dd1 VK |
6050 | |
6051 | mutex_lock(&dev_priv->rps.hw_lock); | |
6052 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
9ef56154 | 6053 | DIV_ROUND_UP(cdclk, 25000)); |
f8437dd1 VK |
6054 | mutex_unlock(&dev_priv->rps.hw_lock); |
6055 | ||
6056 | if (ret) { | |
6057 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
9ef56154 | 6058 | ret, cdclk); |
f8437dd1 VK |
6059 | return; |
6060 | } | |
6061 | ||
4c75b940 | 6062 | intel_update_cdclk(dev_priv); |
f8437dd1 VK |
6063 | } |
6064 | ||
d66a2194 | 6065 | static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) |
f8437dd1 | 6066 | { |
d66a2194 ID |
6067 | u32 cdctl, expected; |
6068 | ||
4c75b940 | 6069 | intel_update_cdclk(dev_priv); |
f8437dd1 | 6070 | |
d66a2194 ID |
6071 | if (dev_priv->cdclk_pll.vco == 0 || |
6072 | dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref) | |
6073 | goto sanitize; | |
6074 | ||
6075 | /* DPLL okay; verify the cdclock | |
6076 | * | |
6077 | * Some BIOS versions leave an incorrect decimal frequency value and | |
6078 | * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, | |
6079 | * so sanitize this register. | |
6080 | */ | |
6081 | cdctl = I915_READ(CDCLK_CTL); | |
6082 | /* | |
6083 | * Let's ignore the pipe field, since BIOS could have configured the | |
6084 | * dividers both synching to an active pipe, or asynchronously | |
6085 | * (PIPE_NONE). | |
6086 | */ | |
6087 | cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE; | |
6088 | ||
6089 | expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) | | |
6090 | skl_cdclk_decimal(dev_priv->cdclk_freq); | |
6091 | /* | |
6092 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
6093 | * enable otherwise. | |
6094 | */ | |
6095 | if (dev_priv->cdclk_freq >= 500000) | |
6096 | expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
6097 | ||
6098 | if (cdctl == expected) | |
6099 | /* All well; nothing to sanitize */ | |
6100 | return; | |
6101 | ||
6102 | sanitize: | |
6103 | DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); | |
6104 | ||
6105 | /* force cdclk programming */ | |
6106 | dev_priv->cdclk_freq = 0; | |
6107 | ||
6108 | /* force full PLL disable + enable */ | |
6109 | dev_priv->cdclk_pll.vco = -1; | |
6110 | } | |
6111 | ||
324513c0 | 6112 | void bxt_init_cdclk(struct drm_i915_private *dev_priv) |
d66a2194 | 6113 | { |
89b3c3c7 ACO |
6114 | int cdclk; |
6115 | ||
d66a2194 ID |
6116 | bxt_sanitize_cdclk(dev_priv); |
6117 | ||
6118 | if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) | |
089c6fd5 | 6119 | return; |
c2e001ef | 6120 | |
f8437dd1 VK |
6121 | /* |
6122 | * FIXME: | |
6123 | * - The initial CDCLK needs to be read from VBT. | |
6124 | * Need to make this change after VBT has changes for BXT. | |
f8437dd1 | 6125 | */ |
89b3c3c7 ACO |
6126 | if (IS_GEMINILAKE(dev_priv)) |
6127 | cdclk = glk_calc_cdclk(0); | |
6128 | else | |
6129 | cdclk = bxt_calc_cdclk(0); | |
6130 | ||
6131 | bxt_set_cdclk(dev_priv, cdclk); | |
f8437dd1 VK |
6132 | } |
6133 | ||
324513c0 | 6134 | void bxt_uninit_cdclk(struct drm_i915_private *dev_priv) |
f8437dd1 | 6135 | { |
324513c0 | 6136 | bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref); |
f8437dd1 VK |
6137 | } |
6138 | ||
a8ca4934 VS |
6139 | static int skl_calc_cdclk(int max_pixclk, int vco) |
6140 | { | |
63911d72 | 6141 | if (vco == 8640000) { |
a8ca4934 | 6142 | if (max_pixclk > 540000) |
487ed2e4 | 6143 | return 617143; |
a8ca4934 VS |
6144 | else if (max_pixclk > 432000) |
6145 | return 540000; | |
487ed2e4 | 6146 | else if (max_pixclk > 308571) |
a8ca4934 VS |
6147 | return 432000; |
6148 | else | |
487ed2e4 | 6149 | return 308571; |
a8ca4934 | 6150 | } else { |
a8ca4934 VS |
6151 | if (max_pixclk > 540000) |
6152 | return 675000; | |
6153 | else if (max_pixclk > 450000) | |
6154 | return 540000; | |
6155 | else if (max_pixclk > 337500) | |
6156 | return 450000; | |
6157 | else | |
6158 | return 337500; | |
6159 | } | |
6160 | } | |
6161 | ||
ea61791e VS |
6162 | static void |
6163 | skl_dpll0_update(struct drm_i915_private *dev_priv) | |
5d96d8af | 6164 | { |
ea61791e | 6165 | u32 val; |
5d96d8af | 6166 | |
709e05c3 | 6167 | dev_priv->cdclk_pll.ref = 24000; |
1c3f7700 | 6168 | dev_priv->cdclk_pll.vco = 0; |
709e05c3 | 6169 | |
ea61791e | 6170 | val = I915_READ(LCPLL1_CTL); |
1c3f7700 | 6171 | if ((val & LCPLL_PLL_ENABLE) == 0) |
ea61791e | 6172 | return; |
5d96d8af | 6173 | |
1c3f7700 ID |
6174 | if (WARN_ON((val & LCPLL_PLL_LOCK) == 0)) |
6175 | return; | |
9f7eb31a | 6176 | |
ea61791e VS |
6177 | val = I915_READ(DPLL_CTRL1); |
6178 | ||
1c3f7700 ID |
6179 | if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | |
6180 | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
6181 | DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != | |
6182 | DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) | |
6183 | return; | |
9f7eb31a | 6184 | |
ea61791e VS |
6185 | switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { |
6186 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): | |
6187 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): | |
6188 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): | |
6189 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): | |
63911d72 | 6190 | dev_priv->cdclk_pll.vco = 8100000; |
ea61791e VS |
6191 | break; |
6192 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): | |
6193 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): | |
63911d72 | 6194 | dev_priv->cdclk_pll.vco = 8640000; |
ea61791e VS |
6195 | break; |
6196 | default: | |
6197 | MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
ea61791e VS |
6198 | break; |
6199 | } | |
5d96d8af DL |
6200 | } |
6201 | ||
b2045352 VS |
6202 | void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco) |
6203 | { | |
6204 | bool changed = dev_priv->skl_preferred_vco_freq != vco; | |
6205 | ||
6206 | dev_priv->skl_preferred_vco_freq = vco; | |
6207 | ||
6208 | if (changed) | |
4c75b940 | 6209 | intel_update_max_cdclk(dev_priv); |
b2045352 VS |
6210 | } |
6211 | ||
5d96d8af | 6212 | static void |
3861fc60 | 6213 | skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) |
5d96d8af | 6214 | { |
a8ca4934 | 6215 | int min_cdclk = skl_calc_cdclk(0, vco); |
5d96d8af DL |
6216 | u32 val; |
6217 | ||
63911d72 | 6218 | WARN_ON(vco != 8100000 && vco != 8640000); |
b2045352 | 6219 | |
5d96d8af | 6220 | /* select the minimum CDCLK before enabling DPLL 0 */ |
9ef56154 | 6221 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk); |
5d96d8af DL |
6222 | I915_WRITE(CDCLK_CTL, val); |
6223 | POSTING_READ(CDCLK_CTL); | |
6224 | ||
6225 | /* | |
6226 | * We always enable DPLL0 with the lowest link rate possible, but still | |
6227 | * taking into account the VCO required to operate the eDP panel at the | |
6228 | * desired frequency. The usual DP link rates operate with a VCO of | |
6229 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. | |
6230 | * The modeset code is responsible for the selection of the exact link | |
6231 | * rate later on, with the constraint of choosing a frequency that | |
a8ca4934 | 6232 | * works with vco. |
5d96d8af DL |
6233 | */ |
6234 | val = I915_READ(DPLL_CTRL1); | |
6235 | ||
6236 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
6237 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
6238 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
63911d72 | 6239 | if (vco == 8640000) |
5d96d8af DL |
6240 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, |
6241 | SKL_DPLL0); | |
6242 | else | |
6243 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, | |
6244 | SKL_DPLL0); | |
6245 | ||
6246 | I915_WRITE(DPLL_CTRL1, val); | |
6247 | POSTING_READ(DPLL_CTRL1); | |
6248 | ||
6249 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); | |
6250 | ||
e24ca054 CW |
6251 | if (intel_wait_for_register(dev_priv, |
6252 | LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, | |
6253 | 5)) | |
5d96d8af | 6254 | DRM_ERROR("DPLL0 not locked\n"); |
1cd593e0 | 6255 | |
63911d72 | 6256 | dev_priv->cdclk_pll.vco = vco; |
b2045352 VS |
6257 | |
6258 | /* We'll want to keep using the current vco from now on. */ | |
6259 | skl_set_preferred_cdclk_vco(dev_priv, vco); | |
5d96d8af DL |
6260 | } |
6261 | ||
430e05de VS |
6262 | static void |
6263 | skl_dpll0_disable(struct drm_i915_private *dev_priv) | |
6264 | { | |
6265 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); | |
8ad32a05 CW |
6266 | if (intel_wait_for_register(dev_priv, |
6267 | LCPLL1_CTL, LCPLL_PLL_LOCK, 0, | |
6268 | 1)) | |
430e05de | 6269 | DRM_ERROR("Couldn't disable DPLL0\n"); |
1cd593e0 | 6270 | |
63911d72 | 6271 | dev_priv->cdclk_pll.vco = 0; |
430e05de VS |
6272 | } |
6273 | ||
5d96d8af DL |
6274 | static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) |
6275 | { | |
6276 | int ret; | |
6277 | u32 val; | |
6278 | ||
6279 | /* inform PCU we want to change CDCLK */ | |
6280 | val = SKL_CDCLK_PREPARE_FOR_CHANGE; | |
6281 | mutex_lock(&dev_priv->rps.hw_lock); | |
6282 | ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); | |
6283 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6284 | ||
6285 | return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE); | |
6286 | } | |
6287 | ||
6288 | static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) | |
6289 | { | |
848496e5 | 6290 | return _wait_for(skl_cdclk_pcu_ready(dev_priv), 3000, 10) == 0; |
5d96d8af DL |
6291 | } |
6292 | ||
1cd593e0 | 6293 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco) |
5d96d8af DL |
6294 | { |
6295 | u32 freq_select, pcu_ack; | |
6296 | ||
1cd593e0 VS |
6297 | WARN_ON((cdclk == 24000) != (vco == 0)); |
6298 | ||
63911d72 | 6299 | DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco); |
5d96d8af DL |
6300 | |
6301 | if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { | |
6302 | DRM_ERROR("failed to inform PCU about cdclk change\n"); | |
6303 | return; | |
6304 | } | |
6305 | ||
6306 | /* set CDCLK_CTL */ | |
9ef56154 | 6307 | switch (cdclk) { |
5d96d8af DL |
6308 | case 450000: |
6309 | case 432000: | |
6310 | freq_select = CDCLK_FREQ_450_432; | |
6311 | pcu_ack = 1; | |
6312 | break; | |
6313 | case 540000: | |
6314 | freq_select = CDCLK_FREQ_540; | |
6315 | pcu_ack = 2; | |
6316 | break; | |
487ed2e4 | 6317 | case 308571: |
5d96d8af DL |
6318 | case 337500: |
6319 | default: | |
6320 | freq_select = CDCLK_FREQ_337_308; | |
6321 | pcu_ack = 0; | |
6322 | break; | |
487ed2e4 | 6323 | case 617143: |
5d96d8af DL |
6324 | case 675000: |
6325 | freq_select = CDCLK_FREQ_675_617; | |
6326 | pcu_ack = 3; | |
6327 | break; | |
6328 | } | |
6329 | ||
63911d72 VS |
6330 | if (dev_priv->cdclk_pll.vco != 0 && |
6331 | dev_priv->cdclk_pll.vco != vco) | |
1cd593e0 VS |
6332 | skl_dpll0_disable(dev_priv); |
6333 | ||
63911d72 | 6334 | if (dev_priv->cdclk_pll.vco != vco) |
1cd593e0 VS |
6335 | skl_dpll0_enable(dev_priv, vco); |
6336 | ||
9ef56154 | 6337 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk)); |
5d96d8af DL |
6338 | POSTING_READ(CDCLK_CTL); |
6339 | ||
6340 | /* inform PCU of the change */ | |
6341 | mutex_lock(&dev_priv->rps.hw_lock); | |
6342 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); | |
6343 | mutex_unlock(&dev_priv->rps.hw_lock); | |
560a7ae4 | 6344 | |
4c75b940 | 6345 | intel_update_cdclk(dev_priv); |
5d96d8af DL |
6346 | } |
6347 | ||
9f7eb31a VS |
6348 | static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv); |
6349 | ||
5d96d8af DL |
6350 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) |
6351 | { | |
709e05c3 | 6352 | skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0); |
5d96d8af DL |
6353 | } |
6354 | ||
6355 | void skl_init_cdclk(struct drm_i915_private *dev_priv) | |
6356 | { | |
9f7eb31a VS |
6357 | int cdclk, vco; |
6358 | ||
6359 | skl_sanitize_cdclk(dev_priv); | |
5d96d8af | 6360 | |
63911d72 | 6361 | if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) { |
9f7eb31a VS |
6362 | /* |
6363 | * Use the current vco as our initial | |
6364 | * guess as to what the preferred vco is. | |
6365 | */ | |
6366 | if (dev_priv->skl_preferred_vco_freq == 0) | |
6367 | skl_set_preferred_cdclk_vco(dev_priv, | |
63911d72 | 6368 | dev_priv->cdclk_pll.vco); |
70c2c184 | 6369 | return; |
1cd593e0 | 6370 | } |
5d96d8af | 6371 | |
70c2c184 VS |
6372 | vco = dev_priv->skl_preferred_vco_freq; |
6373 | if (vco == 0) | |
63911d72 | 6374 | vco = 8100000; |
70c2c184 | 6375 | cdclk = skl_calc_cdclk(0, vco); |
5d96d8af | 6376 | |
70c2c184 | 6377 | skl_set_cdclk(dev_priv, cdclk, vco); |
5d96d8af DL |
6378 | } |
6379 | ||
9f7eb31a | 6380 | static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) |
c73666f3 | 6381 | { |
09492498 | 6382 | uint32_t cdctl, expected; |
c73666f3 | 6383 | |
f1b391a5 SK |
6384 | /* |
6385 | * check if the pre-os intialized the display | |
6386 | * There is SWF18 scratchpad register defined which is set by the | |
6387 | * pre-os which can be used by the OS drivers to check the status | |
6388 | */ | |
6389 | if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) | |
6390 | goto sanitize; | |
6391 | ||
4c75b940 | 6392 | intel_update_cdclk(dev_priv); |
c73666f3 | 6393 | /* Is PLL enabled and locked ? */ |
1c3f7700 ID |
6394 | if (dev_priv->cdclk_pll.vco == 0 || |
6395 | dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref) | |
c73666f3 SK |
6396 | goto sanitize; |
6397 | ||
6398 | /* DPLL okay; verify the cdclock | |
6399 | * | |
6400 | * Noticed in some instances that the freq selection is correct but | |
6401 | * decimal part is programmed wrong from BIOS where pre-os does not | |
6402 | * enable display. Verify the same as well. | |
6403 | */ | |
09492498 VS |
6404 | cdctl = I915_READ(CDCLK_CTL); |
6405 | expected = (cdctl & CDCLK_FREQ_SEL_MASK) | | |
6406 | skl_cdclk_decimal(dev_priv->cdclk_freq); | |
6407 | if (cdctl == expected) | |
c73666f3 | 6408 | /* All well; nothing to sanitize */ |
9f7eb31a | 6409 | return; |
c89e39f3 | 6410 | |
9f7eb31a VS |
6411 | sanitize: |
6412 | DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); | |
c73666f3 | 6413 | |
9f7eb31a VS |
6414 | /* force cdclk programming */ |
6415 | dev_priv->cdclk_freq = 0; | |
6416 | /* force full PLL disable + enable */ | |
63911d72 | 6417 | dev_priv->cdclk_pll.vco = -1; |
c73666f3 SK |
6418 | } |
6419 | ||
30a970c6 JB |
6420 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
6421 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
6422 | { | |
fac5e23e | 6423 | struct drm_i915_private *dev_priv = to_i915(dev); |
30a970c6 JB |
6424 | u32 val, cmd; |
6425 | ||
1353c4fb | 6426 | WARN_ON(dev_priv->display.get_display_clock_speed(dev_priv) |
164dfd28 | 6427 | != dev_priv->cdclk_freq); |
d60c4473 | 6428 | |
dfcab17e | 6429 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 6430 | cmd = 2; |
dfcab17e | 6431 | else if (cdclk == 266667) |
30a970c6 JB |
6432 | cmd = 1; |
6433 | else | |
6434 | cmd = 0; | |
6435 | ||
6436 | mutex_lock(&dev_priv->rps.hw_lock); | |
6437 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
6438 | val &= ~DSPFREQGUAR_MASK; | |
6439 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
6440 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
6441 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
6442 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
6443 | 50)) { | |
6444 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
6445 | } | |
6446 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6447 | ||
54433e91 VS |
6448 | mutex_lock(&dev_priv->sb_lock); |
6449 | ||
dfcab17e | 6450 | if (cdclk == 400000) { |
6bcda4f0 | 6451 | u32 divider; |
30a970c6 | 6452 | |
6bcda4f0 | 6453 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 | 6454 | |
30a970c6 JB |
6455 | /* adjust cdclk divider */ |
6456 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
87d5d259 | 6457 | val &= ~CCK_FREQUENCY_VALUES; |
30a970c6 JB |
6458 | val |= divider; |
6459 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
6460 | |
6461 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
87d5d259 | 6462 | CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), |
a877e801 VS |
6463 | 50)) |
6464 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
6465 | } |
6466 | ||
30a970c6 JB |
6467 | /* adjust self-refresh exit latency value */ |
6468 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
6469 | val &= ~0x7f; | |
6470 | ||
6471 | /* | |
6472 | * For high bandwidth configs, we set a higher latency in the bunit | |
6473 | * so that the core display fetch happens in time to avoid underruns. | |
6474 | */ | |
dfcab17e | 6475 | if (cdclk == 400000) |
30a970c6 JB |
6476 | val |= 4500 / 250; /* 4.5 usec */ |
6477 | else | |
6478 | val |= 3000 / 250; /* 3.0 usec */ | |
6479 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
54433e91 | 6480 | |
a580516d | 6481 | mutex_unlock(&dev_priv->sb_lock); |
30a970c6 | 6482 | |
4c75b940 | 6483 | intel_update_cdclk(dev_priv); |
30a970c6 JB |
6484 | } |
6485 | ||
383c5a6a VS |
6486 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
6487 | { | |
fac5e23e | 6488 | struct drm_i915_private *dev_priv = to_i915(dev); |
383c5a6a VS |
6489 | u32 val, cmd; |
6490 | ||
1353c4fb | 6491 | WARN_ON(dev_priv->display.get_display_clock_speed(dev_priv) |
164dfd28 | 6492 | != dev_priv->cdclk_freq); |
383c5a6a VS |
6493 | |
6494 | switch (cdclk) { | |
383c5a6a VS |
6495 | case 333333: |
6496 | case 320000: | |
383c5a6a | 6497 | case 266667: |
383c5a6a | 6498 | case 200000: |
383c5a6a VS |
6499 | break; |
6500 | default: | |
5f77eeb0 | 6501 | MISSING_CASE(cdclk); |
383c5a6a VS |
6502 | return; |
6503 | } | |
6504 | ||
9d0d3fda VS |
6505 | /* |
6506 | * Specs are full of misinformation, but testing on actual | |
6507 | * hardware has shown that we just need to write the desired | |
6508 | * CCK divider into the Punit register. | |
6509 | */ | |
6510 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
6511 | ||
383c5a6a VS |
6512 | mutex_lock(&dev_priv->rps.hw_lock); |
6513 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
6514 | val &= ~DSPFREQGUAR_MASK_CHV; | |
6515 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
6516 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
6517 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
6518 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
6519 | 50)) { | |
6520 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
6521 | } | |
6522 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6523 | ||
4c75b940 | 6524 | intel_update_cdclk(dev_priv); |
383c5a6a VS |
6525 | } |
6526 | ||
30a970c6 JB |
6527 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
6528 | int max_pixclk) | |
6529 | { | |
6bcda4f0 | 6530 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 6531 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 6532 | |
30a970c6 JB |
6533 | /* |
6534 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
6535 | * 200MHz | |
6536 | * 267MHz | |
29dc7ef3 | 6537 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
6538 | * 400MHz (VLV only) |
6539 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
6540 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
6541 | * |
6542 | * We seem to get an unstable or solid color picture at 200MHz. | |
6543 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
6544 | * are off. | |
30a970c6 | 6545 | */ |
6cca3195 VS |
6546 | if (!IS_CHERRYVIEW(dev_priv) && |
6547 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 6548 | return 400000; |
6cca3195 | 6549 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 6550 | return freq_320; |
e37c67a1 | 6551 | else if (max_pixclk > 0) |
dfcab17e | 6552 | return 266667; |
e37c67a1 VS |
6553 | else |
6554 | return 200000; | |
30a970c6 JB |
6555 | } |
6556 | ||
89b3c3c7 ACO |
6557 | static int glk_calc_cdclk(int max_pixclk) |
6558 | { | |
09d09386 | 6559 | if (max_pixclk > 2 * 158400) |
89b3c3c7 | 6560 | return 316800; |
09d09386 | 6561 | else if (max_pixclk > 2 * 79200) |
89b3c3c7 ACO |
6562 | return 158400; |
6563 | else | |
6564 | return 79200; | |
6565 | } | |
6566 | ||
324513c0 | 6567 | static int bxt_calc_cdclk(int max_pixclk) |
f8437dd1 | 6568 | { |
760e1477 | 6569 | if (max_pixclk > 576000) |
f8437dd1 | 6570 | return 624000; |
760e1477 | 6571 | else if (max_pixclk > 384000) |
f8437dd1 | 6572 | return 576000; |
760e1477 | 6573 | else if (max_pixclk > 288000) |
f8437dd1 | 6574 | return 384000; |
760e1477 | 6575 | else if (max_pixclk > 144000) |
f8437dd1 VK |
6576 | return 288000; |
6577 | else | |
6578 | return 144000; | |
6579 | } | |
6580 | ||
e8788cbc | 6581 | /* Compute the max pixel clock for new configuration. */ |
a821fc46 ACO |
6582 | static int intel_mode_max_pixclk(struct drm_device *dev, |
6583 | struct drm_atomic_state *state) | |
30a970c6 | 6584 | { |
565602d7 | 6585 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 6586 | struct drm_i915_private *dev_priv = to_i915(dev); |
565602d7 ML |
6587 | struct drm_crtc *crtc; |
6588 | struct drm_crtc_state *crtc_state; | |
6589 | unsigned max_pixclk = 0, i; | |
6590 | enum pipe pipe; | |
30a970c6 | 6591 | |
565602d7 ML |
6592 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
6593 | sizeof(intel_state->min_pixclk)); | |
304603f4 | 6594 | |
565602d7 ML |
6595 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
6596 | int pixclk = 0; | |
6597 | ||
6598 | if (crtc_state->enable) | |
6599 | pixclk = crtc_state->adjusted_mode.crtc_clock; | |
304603f4 | 6600 | |
565602d7 | 6601 | intel_state->min_pixclk[i] = pixclk; |
30a970c6 JB |
6602 | } |
6603 | ||
565602d7 ML |
6604 | for_each_pipe(dev_priv, pipe) |
6605 | max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk); | |
6606 | ||
30a970c6 JB |
6607 | return max_pixclk; |
6608 | } | |
6609 | ||
27c329ed | 6610 | static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) |
30a970c6 | 6611 | { |
27c329ed | 6612 | struct drm_device *dev = state->dev; |
fac5e23e | 6613 | struct drm_i915_private *dev_priv = to_i915(dev); |
27c329ed | 6614 | int max_pixclk = intel_mode_max_pixclk(dev, state); |
1a617b77 ML |
6615 | struct intel_atomic_state *intel_state = |
6616 | to_intel_atomic_state(state); | |
30a970c6 | 6617 | |
1a617b77 | 6618 | intel_state->cdclk = intel_state->dev_cdclk = |
27c329ed | 6619 | valleyview_calc_cdclk(dev_priv, max_pixclk); |
0a9ab303 | 6620 | |
1a617b77 ML |
6621 | if (!intel_state->active_crtcs) |
6622 | intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0); | |
6623 | ||
27c329ed ML |
6624 | return 0; |
6625 | } | |
304603f4 | 6626 | |
324513c0 | 6627 | static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state) |
27c329ed | 6628 | { |
89b3c3c7 | 6629 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
4e5ca60f | 6630 | int max_pixclk = ilk_max_pixel_rate(state); |
1a617b77 ML |
6631 | struct intel_atomic_state *intel_state = |
6632 | to_intel_atomic_state(state); | |
89b3c3c7 | 6633 | int cdclk; |
85a96e7a | 6634 | |
89b3c3c7 ACO |
6635 | if (IS_GEMINILAKE(dev_priv)) |
6636 | cdclk = glk_calc_cdclk(max_pixclk); | |
6637 | else | |
6638 | cdclk = bxt_calc_cdclk(max_pixclk); | |
85a96e7a | 6639 | |
89b3c3c7 ACO |
6640 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; |
6641 | ||
6642 | if (!intel_state->active_crtcs) { | |
6643 | if (IS_GEMINILAKE(dev_priv)) | |
6644 | cdclk = glk_calc_cdclk(0); | |
6645 | else | |
6646 | cdclk = bxt_calc_cdclk(0); | |
6647 | ||
6648 | intel_state->dev_cdclk = cdclk; | |
6649 | } | |
1a617b77 | 6650 | |
27c329ed | 6651 | return 0; |
30a970c6 JB |
6652 | } |
6653 | ||
1e69cd74 VS |
6654 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
6655 | { | |
6656 | unsigned int credits, default_credits; | |
6657 | ||
6658 | if (IS_CHERRYVIEW(dev_priv)) | |
6659 | default_credits = PFI_CREDIT(12); | |
6660 | else | |
6661 | default_credits = PFI_CREDIT(8); | |
6662 | ||
bfa7df01 | 6663 | if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) { |
1e69cd74 VS |
6664 | /* CHV suggested value is 31 or 63 */ |
6665 | if (IS_CHERRYVIEW(dev_priv)) | |
fcc0008f | 6666 | credits = PFI_CREDIT_63; |
1e69cd74 VS |
6667 | else |
6668 | credits = PFI_CREDIT(15); | |
6669 | } else { | |
6670 | credits = default_credits; | |
6671 | } | |
6672 | ||
6673 | /* | |
6674 | * WA - write default credits before re-programming | |
6675 | * FIXME: should we also set the resend bit here? | |
6676 | */ | |
6677 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6678 | default_credits); | |
6679 | ||
6680 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6681 | credits | PFI_CREDIT_RESEND); | |
6682 | ||
6683 | /* | |
6684 | * FIXME is this guaranteed to clear | |
6685 | * immediately or should we poll for it? | |
6686 | */ | |
6687 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
6688 | } | |
6689 | ||
27c329ed | 6690 | static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
30a970c6 | 6691 | { |
a821fc46 | 6692 | struct drm_device *dev = old_state->dev; |
fac5e23e | 6693 | struct drm_i915_private *dev_priv = to_i915(dev); |
1a617b77 ML |
6694 | struct intel_atomic_state *old_intel_state = |
6695 | to_intel_atomic_state(old_state); | |
6696 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
30a970c6 | 6697 | |
27c329ed ML |
6698 | /* |
6699 | * FIXME: We can end up here with all power domains off, yet | |
6700 | * with a CDCLK frequency other than the minimum. To account | |
6701 | * for this take the PIPE-A power domain, which covers the HW | |
6702 | * blocks needed for the following programming. This can be | |
6703 | * removed once it's guaranteed that we get here either with | |
6704 | * the minimum CDCLK set, or the required power domains | |
6705 | * enabled. | |
6706 | */ | |
6707 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
738c05c0 | 6708 | |
920a14b2 | 6709 | if (IS_CHERRYVIEW(dev_priv)) |
27c329ed ML |
6710 | cherryview_set_cdclk(dev, req_cdclk); |
6711 | else | |
6712 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 6713 | |
27c329ed | 6714 | vlv_program_pfi_credits(dev_priv); |
1e69cd74 | 6715 | |
27c329ed | 6716 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
30a970c6 JB |
6717 | } |
6718 | ||
4a806558 ML |
6719 | static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config, |
6720 | struct drm_atomic_state *old_state) | |
89b667f8 | 6721 | { |
4a806558 | 6722 | struct drm_crtc *crtc = pipe_config->base.crtc; |
89b667f8 | 6723 | struct drm_device *dev = crtc->dev; |
a72e4c9f | 6724 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 | 6725 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
89b667f8 | 6726 | int pipe = intel_crtc->pipe; |
89b667f8 | 6727 | |
53d9f4e9 | 6728 | if (WARN_ON(intel_crtc->active)) |
89b667f8 JB |
6729 | return; |
6730 | ||
37a5650b | 6731 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 6732 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6733 | |
6734 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 6735 | intel_set_pipe_src_size(intel_crtc); |
5b18e57c | 6736 | |
920a14b2 | 6737 | if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { |
fac5e23e | 6738 | struct drm_i915_private *dev_priv = to_i915(dev); |
c14b0485 VS |
6739 | |
6740 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
6741 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
6742 | } | |
6743 | ||
5b18e57c DV |
6744 | i9xx_set_pipeconf(intel_crtc); |
6745 | ||
89b667f8 | 6746 | intel_crtc->active = true; |
89b667f8 | 6747 | |
a72e4c9f | 6748 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6749 | |
fd6bbda9 | 6750 | intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); |
89b667f8 | 6751 | |
920a14b2 | 6752 | if (IS_CHERRYVIEW(dev_priv)) { |
cd2d34d9 VS |
6753 | chv_prepare_pll(intel_crtc, intel_crtc->config); |
6754 | chv_enable_pll(intel_crtc, intel_crtc->config); | |
6755 | } else { | |
6756 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
6757 | vlv_enable_pll(intel_crtc, intel_crtc->config); | |
9d556c99 | 6758 | } |
89b667f8 | 6759 | |
fd6bbda9 | 6760 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
89b667f8 | 6761 | |
2dd24552 JB |
6762 | i9xx_pfit_enable(intel_crtc); |
6763 | ||
b95c5321 | 6764 | intel_color_load_luts(&pipe_config->base); |
63cbb074 | 6765 | |
432081bc | 6766 | intel_update_watermarks(intel_crtc); |
e1fdc473 | 6767 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6768 | |
4b3a9526 VS |
6769 | assert_vblank_disabled(crtc); |
6770 | drm_crtc_vblank_on(crtc); | |
6771 | ||
fd6bbda9 | 6772 | intel_encoders_enable(crtc, pipe_config, old_state); |
89b667f8 JB |
6773 | } |
6774 | ||
f13c2ef3 DV |
6775 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
6776 | { | |
6777 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6778 | struct drm_i915_private *dev_priv = to_i915(dev); |
f13c2ef3 | 6779 | |
6e3c9717 ACO |
6780 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
6781 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
6782 | } |
6783 | ||
4a806558 ML |
6784 | static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config, |
6785 | struct drm_atomic_state *old_state) | |
79e53945 | 6786 | { |
4a806558 | 6787 | struct drm_crtc *crtc = pipe_config->base.crtc; |
79e53945 | 6788 | struct drm_device *dev = crtc->dev; |
a72e4c9f | 6789 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 6790 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cd2d34d9 | 6791 | enum pipe pipe = intel_crtc->pipe; |
79e53945 | 6792 | |
53d9f4e9 | 6793 | if (WARN_ON(intel_crtc->active)) |
f7abfe8b CW |
6794 | return; |
6795 | ||
f13c2ef3 DV |
6796 | i9xx_set_pll_dividers(intel_crtc); |
6797 | ||
37a5650b | 6798 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 6799 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6800 | |
6801 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 6802 | intel_set_pipe_src_size(intel_crtc); |
5b18e57c | 6803 | |
5b18e57c DV |
6804 | i9xx_set_pipeconf(intel_crtc); |
6805 | ||
f7abfe8b | 6806 | intel_crtc->active = true; |
6b383a7f | 6807 | |
5db94019 | 6808 | if (!IS_GEN2(dev_priv)) |
a72e4c9f | 6809 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6810 | |
fd6bbda9 | 6811 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
9d6d9f19 | 6812 | |
f6736a1a DV |
6813 | i9xx_enable_pll(intel_crtc); |
6814 | ||
2dd24552 JB |
6815 | i9xx_pfit_enable(intel_crtc); |
6816 | ||
b95c5321 | 6817 | intel_color_load_luts(&pipe_config->base); |
63cbb074 | 6818 | |
432081bc | 6819 | intel_update_watermarks(intel_crtc); |
e1fdc473 | 6820 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6821 | |
4b3a9526 VS |
6822 | assert_vblank_disabled(crtc); |
6823 | drm_crtc_vblank_on(crtc); | |
6824 | ||
fd6bbda9 | 6825 | intel_encoders_enable(crtc, pipe_config, old_state); |
0b8765c6 | 6826 | } |
79e53945 | 6827 | |
87476d63 DV |
6828 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
6829 | { | |
6830 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6831 | struct drm_i915_private *dev_priv = to_i915(dev); |
87476d63 | 6832 | |
6e3c9717 | 6833 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 6834 | return; |
87476d63 | 6835 | |
328d8e82 | 6836 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 6837 | |
328d8e82 DV |
6838 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
6839 | I915_READ(PFIT_CONTROL)); | |
6840 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
6841 | } |
6842 | ||
4a806558 ML |
6843 | static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state, |
6844 | struct drm_atomic_state *old_state) | |
0b8765c6 | 6845 | { |
4a806558 | 6846 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
0b8765c6 | 6847 | struct drm_device *dev = crtc->dev; |
fac5e23e | 6848 | struct drm_i915_private *dev_priv = to_i915(dev); |
0b8765c6 JB |
6849 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6850 | int pipe = intel_crtc->pipe; | |
ef9c3aee | 6851 | |
6304cd91 VS |
6852 | /* |
6853 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
6854 | * wait for planes to fully turn off before disabling the pipe. | |
6855 | */ | |
5db94019 | 6856 | if (IS_GEN2(dev_priv)) |
0f0f74bc | 6857 | intel_wait_for_vblank(dev_priv, pipe); |
6304cd91 | 6858 | |
fd6bbda9 | 6859 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
4b3a9526 | 6860 | |
f9b61ff6 DV |
6861 | drm_crtc_vblank_off(crtc); |
6862 | assert_vblank_disabled(crtc); | |
6863 | ||
575f7ab7 | 6864 | intel_disable_pipe(intel_crtc); |
24a1f16d | 6865 | |
87476d63 | 6866 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 6867 | |
fd6bbda9 | 6868 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
89b667f8 | 6869 | |
d7edc4e5 | 6870 | if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) { |
920a14b2 | 6871 | if (IS_CHERRYVIEW(dev_priv)) |
076ed3b2 | 6872 | chv_disable_pll(dev_priv, pipe); |
11a914c2 | 6873 | else if (IS_VALLEYVIEW(dev_priv)) |
076ed3b2 CML |
6874 | vlv_disable_pll(dev_priv, pipe); |
6875 | else | |
1c4e0274 | 6876 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 6877 | } |
0b8765c6 | 6878 | |
fd6bbda9 | 6879 | intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state); |
d6db995f | 6880 | |
5db94019 | 6881 | if (!IS_GEN2(dev_priv)) |
a72e4c9f | 6882 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
0b8765c6 JB |
6883 | } |
6884 | ||
b17d48e2 ML |
6885 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
6886 | { | |
842e0307 | 6887 | struct intel_encoder *encoder; |
b17d48e2 ML |
6888 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6889 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
6890 | enum intel_display_power_domain domain; | |
6891 | unsigned long domains; | |
4a806558 ML |
6892 | struct drm_atomic_state *state; |
6893 | struct intel_crtc_state *crtc_state; | |
6894 | int ret; | |
b17d48e2 ML |
6895 | |
6896 | if (!intel_crtc->active) | |
6897 | return; | |
6898 | ||
936e71e3 | 6899 | if (to_intel_plane_state(crtc->primary->state)->base.visible) { |
5a21b665 | 6900 | WARN_ON(intel_crtc->flip_work); |
fc32b1fd | 6901 | |
2622a081 | 6902 | intel_pre_disable_primary_noatomic(crtc); |
54a41961 ML |
6903 | |
6904 | intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); | |
936e71e3 | 6905 | to_intel_plane_state(crtc->primary->state)->base.visible = false; |
a539205a ML |
6906 | } |
6907 | ||
4a806558 ML |
6908 | state = drm_atomic_state_alloc(crtc->dev); |
6909 | state->acquire_ctx = crtc->dev->mode_config.acquire_ctx; | |
6910 | ||
6911 | /* Everything's already locked, -EDEADLK can't happen. */ | |
6912 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); | |
6913 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
6914 | ||
6915 | WARN_ON(IS_ERR(crtc_state) || ret); | |
6916 | ||
6917 | dev_priv->display.crtc_disable(crtc_state, state); | |
6918 | ||
0853695c | 6919 | drm_atomic_state_put(state); |
842e0307 | 6920 | |
78108b7c VS |
6921 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", |
6922 | crtc->base.id, crtc->name); | |
842e0307 ML |
6923 | |
6924 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0); | |
6925 | crtc->state->active = false; | |
37d9078b | 6926 | intel_crtc->active = false; |
842e0307 ML |
6927 | crtc->enabled = false; |
6928 | crtc->state->connector_mask = 0; | |
6929 | crtc->state->encoder_mask = 0; | |
6930 | ||
6931 | for_each_encoder_on_crtc(crtc->dev, crtc, encoder) | |
6932 | encoder->base.crtc = NULL; | |
6933 | ||
58f9c0bc | 6934 | intel_fbc_disable(intel_crtc); |
432081bc | 6935 | intel_update_watermarks(intel_crtc); |
1f7457b1 | 6936 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
6937 | |
6938 | domains = intel_crtc->enabled_power_domains; | |
6939 | for_each_power_domain(domain, domains) | |
6940 | intel_display_power_put(dev_priv, domain); | |
6941 | intel_crtc->enabled_power_domains = 0; | |
565602d7 ML |
6942 | |
6943 | dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); | |
6944 | dev_priv->min_pixclk[intel_crtc->pipe] = 0; | |
b17d48e2 ML |
6945 | } |
6946 | ||
6b72d486 ML |
6947 | /* |
6948 | * turn all crtc's off, but do not adjust state | |
6949 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
6950 | */ | |
70e0bd74 | 6951 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 6952 | { |
e2c8b870 | 6953 | struct drm_i915_private *dev_priv = to_i915(dev); |
70e0bd74 | 6954 | struct drm_atomic_state *state; |
e2c8b870 | 6955 | int ret; |
70e0bd74 | 6956 | |
e2c8b870 ML |
6957 | state = drm_atomic_helper_suspend(dev); |
6958 | ret = PTR_ERR_OR_ZERO(state); | |
70e0bd74 ML |
6959 | if (ret) |
6960 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
e2c8b870 ML |
6961 | else |
6962 | dev_priv->modeset_restore_state = state; | |
70e0bd74 | 6963 | return ret; |
ee7b9f93 JB |
6964 | } |
6965 | ||
ea5b213a | 6966 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6967 | { |
4ef69c7a | 6968 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6969 | |
ea5b213a CW |
6970 | drm_encoder_cleanup(encoder); |
6971 | kfree(intel_encoder); | |
7e7d76c3 JB |
6972 | } |
6973 | ||
0a91ca29 DV |
6974 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6975 | * internal consistency). */ | |
5a21b665 | 6976 | static void intel_connector_verify_state(struct intel_connector *connector) |
79e53945 | 6977 | { |
5a21b665 | 6978 | struct drm_crtc *crtc = connector->base.state->crtc; |
35dd3c64 ML |
6979 | |
6980 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6981 | connector->base.base.id, | |
6982 | connector->base.name); | |
6983 | ||
0a91ca29 | 6984 | if (connector->get_hw_state(connector)) { |
e85376cb | 6985 | struct intel_encoder *encoder = connector->encoder; |
5a21b665 | 6986 | struct drm_connector_state *conn_state = connector->base.state; |
0a91ca29 | 6987 | |
35dd3c64 ML |
6988 | I915_STATE_WARN(!crtc, |
6989 | "connector enabled without attached crtc\n"); | |
0a91ca29 | 6990 | |
35dd3c64 ML |
6991 | if (!crtc) |
6992 | return; | |
6993 | ||
6994 | I915_STATE_WARN(!crtc->state->active, | |
6995 | "connector is active, but attached crtc isn't\n"); | |
6996 | ||
e85376cb | 6997 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
6998 | return; |
6999 | ||
e85376cb | 7000 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
7001 | "atomic encoder doesn't match attached encoder\n"); |
7002 | ||
e85376cb | 7003 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
7004 | "attached encoder crtc differs from connector crtc\n"); |
7005 | } else { | |
4d688a2a ML |
7006 | I915_STATE_WARN(crtc && crtc->state->active, |
7007 | "attached crtc is active, but connector isn't\n"); | |
5a21b665 | 7008 | I915_STATE_WARN(!crtc && connector->base.state->best_encoder, |
35dd3c64 | 7009 | "best encoder set without crtc!\n"); |
0a91ca29 | 7010 | } |
79e53945 JB |
7011 | } |
7012 | ||
08d9bc92 ACO |
7013 | int intel_connector_init(struct intel_connector *connector) |
7014 | { | |
5350a031 | 7015 | drm_atomic_helper_connector_reset(&connector->base); |
08d9bc92 | 7016 | |
5350a031 | 7017 | if (!connector->base.state) |
08d9bc92 ACO |
7018 | return -ENOMEM; |
7019 | ||
08d9bc92 ACO |
7020 | return 0; |
7021 | } | |
7022 | ||
7023 | struct intel_connector *intel_connector_alloc(void) | |
7024 | { | |
7025 | struct intel_connector *connector; | |
7026 | ||
7027 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
7028 | if (!connector) | |
7029 | return NULL; | |
7030 | ||
7031 | if (intel_connector_init(connector) < 0) { | |
7032 | kfree(connector); | |
7033 | return NULL; | |
7034 | } | |
7035 | ||
7036 | return connector; | |
7037 | } | |
7038 | ||
f0947c37 DV |
7039 | /* Simple connector->get_hw_state implementation for encoders that support only |
7040 | * one connector and no cloning and hence the encoder state determines the state | |
7041 | * of the connector. */ | |
7042 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 7043 | { |
24929352 | 7044 | enum pipe pipe = 0; |
f0947c37 | 7045 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 7046 | |
f0947c37 | 7047 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
7048 | } |
7049 | ||
6d293983 | 7050 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 7051 | { |
6d293983 ACO |
7052 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
7053 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
7054 | |
7055 | return 0; | |
7056 | } | |
7057 | ||
6d293983 | 7058 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 7059 | struct intel_crtc_state *pipe_config) |
1857e1da | 7060 | { |
8652744b | 7061 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d293983 ACO |
7062 | struct drm_atomic_state *state = pipe_config->base.state; |
7063 | struct intel_crtc *other_crtc; | |
7064 | struct intel_crtc_state *other_crtc_state; | |
7065 | ||
1857e1da DV |
7066 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
7067 | pipe_name(pipe), pipe_config->fdi_lanes); | |
7068 | if (pipe_config->fdi_lanes > 4) { | |
7069 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
7070 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 7071 | return -EINVAL; |
1857e1da DV |
7072 | } |
7073 | ||
8652744b | 7074 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
1857e1da DV |
7075 | if (pipe_config->fdi_lanes > 2) { |
7076 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
7077 | pipe_config->fdi_lanes); | |
6d293983 | 7078 | return -EINVAL; |
1857e1da | 7079 | } else { |
6d293983 | 7080 | return 0; |
1857e1da DV |
7081 | } |
7082 | } | |
7083 | ||
b7f05d4a | 7084 | if (INTEL_INFO(dev_priv)->num_pipes == 2) |
6d293983 | 7085 | return 0; |
1857e1da DV |
7086 | |
7087 | /* Ivybridge 3 pipe is really complicated */ | |
7088 | switch (pipe) { | |
7089 | case PIPE_A: | |
6d293983 | 7090 | return 0; |
1857e1da | 7091 | case PIPE_B: |
6d293983 ACO |
7092 | if (pipe_config->fdi_lanes <= 2) |
7093 | return 0; | |
7094 | ||
b91eb5cc | 7095 | other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C); |
6d293983 ACO |
7096 | other_crtc_state = |
7097 | intel_atomic_get_crtc_state(state, other_crtc); | |
7098 | if (IS_ERR(other_crtc_state)) | |
7099 | return PTR_ERR(other_crtc_state); | |
7100 | ||
7101 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
7102 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
7103 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 7104 | return -EINVAL; |
1857e1da | 7105 | } |
6d293983 | 7106 | return 0; |
1857e1da | 7107 | case PIPE_C: |
251cc67c VS |
7108 | if (pipe_config->fdi_lanes > 2) { |
7109 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
7110 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 7111 | return -EINVAL; |
251cc67c | 7112 | } |
6d293983 | 7113 | |
b91eb5cc | 7114 | other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B); |
6d293983 ACO |
7115 | other_crtc_state = |
7116 | intel_atomic_get_crtc_state(state, other_crtc); | |
7117 | if (IS_ERR(other_crtc_state)) | |
7118 | return PTR_ERR(other_crtc_state); | |
7119 | ||
7120 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 7121 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 7122 | return -EINVAL; |
1857e1da | 7123 | } |
6d293983 | 7124 | return 0; |
1857e1da DV |
7125 | default: |
7126 | BUG(); | |
7127 | } | |
7128 | } | |
7129 | ||
e29c22c0 DV |
7130 | #define RETRY 1 |
7131 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 7132 | struct intel_crtc_state *pipe_config) |
877d48d5 | 7133 | { |
1857e1da | 7134 | struct drm_device *dev = intel_crtc->base.dev; |
7c5f93b0 | 7135 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
7136 | int lane, link_bw, fdi_dotclock, ret; |
7137 | bool needs_recompute = false; | |
877d48d5 | 7138 | |
e29c22c0 | 7139 | retry: |
877d48d5 DV |
7140 | /* FDI is a binary signal running at ~2.7GHz, encoding |
7141 | * each output octet as 10 bits. The actual frequency | |
7142 | * is stored as a divider into a 100MHz clock, and the | |
7143 | * mode pixel clock is stored in units of 1KHz. | |
7144 | * Hence the bw of each lane in terms of the mode signal | |
7145 | * is: | |
7146 | */ | |
21a727b3 | 7147 | link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config); |
877d48d5 | 7148 | |
241bfc38 | 7149 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 7150 | |
2bd89a07 | 7151 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
7152 | pipe_config->pipe_bpp); |
7153 | ||
7154 | pipe_config->fdi_lanes = lane; | |
7155 | ||
2bd89a07 | 7156 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 7157 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 7158 | |
e3b247da | 7159 | ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); |
6d293983 | 7160 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { |
e29c22c0 DV |
7161 | pipe_config->pipe_bpp -= 2*3; |
7162 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
7163 | pipe_config->pipe_bpp); | |
7164 | needs_recompute = true; | |
7165 | pipe_config->bw_constrained = true; | |
7166 | ||
7167 | goto retry; | |
7168 | } | |
7169 | ||
7170 | if (needs_recompute) | |
7171 | return RETRY; | |
7172 | ||
6d293983 | 7173 | return ret; |
877d48d5 DV |
7174 | } |
7175 | ||
8cfb3407 VS |
7176 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
7177 | struct intel_crtc_state *pipe_config) | |
7178 | { | |
7179 | if (pipe_config->pipe_bpp > 24) | |
7180 | return false; | |
7181 | ||
7182 | /* HSW can handle pixel rate up to cdclk? */ | |
2d1fe073 | 7183 | if (IS_HASWELL(dev_priv)) |
8cfb3407 VS |
7184 | return true; |
7185 | ||
7186 | /* | |
b432e5cf VS |
7187 | * We compare against max which means we must take |
7188 | * the increased cdclk requirement into account when | |
7189 | * calculating the new cdclk. | |
7190 | * | |
7191 | * Should measure whether using a lower cdclk w/o IPS | |
8cfb3407 VS |
7192 | */ |
7193 | return ilk_pipe_pixel_rate(pipe_config) <= | |
7194 | dev_priv->max_cdclk_freq * 95 / 100; | |
7195 | } | |
7196 | ||
42db64ef | 7197 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 7198 | struct intel_crtc_state *pipe_config) |
42db64ef | 7199 | { |
8cfb3407 | 7200 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7201 | struct drm_i915_private *dev_priv = to_i915(dev); |
8cfb3407 | 7202 | |
d330a953 | 7203 | pipe_config->ips_enabled = i915.enable_ips && |
8cfb3407 VS |
7204 | hsw_crtc_supports_ips(crtc) && |
7205 | pipe_config_supports_ips(dev_priv, pipe_config); | |
42db64ef PZ |
7206 | } |
7207 | ||
39acb4aa VS |
7208 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
7209 | { | |
7210 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
7211 | ||
7212 | /* GDG double wide on either pipe, otherwise pipe A only */ | |
7213 | return INTEL_INFO(dev_priv)->gen < 4 && | |
7214 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); | |
7215 | } | |
7216 | ||
a43f6e0f | 7217 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 7218 | struct intel_crtc_state *pipe_config) |
79e53945 | 7219 | { |
a43f6e0f | 7220 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7221 | struct drm_i915_private *dev_priv = to_i915(dev); |
7c5f93b0 | 7222 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
f3261156 | 7223 | int clock_limit = dev_priv->max_dotclk_freq; |
89749350 | 7224 | |
6315b5d3 | 7225 | if (INTEL_GEN(dev_priv) < 4) { |
f3261156 | 7226 | clock_limit = dev_priv->max_cdclk_freq * 9 / 10; |
cf532bb2 VS |
7227 | |
7228 | /* | |
39acb4aa | 7229 | * Enable double wide mode when the dot clock |
cf532bb2 | 7230 | * is > 90% of the (display) core speed. |
cf532bb2 | 7231 | */ |
39acb4aa VS |
7232 | if (intel_crtc_supports_double_wide(crtc) && |
7233 | adjusted_mode->crtc_clock > clock_limit) { | |
f3261156 | 7234 | clock_limit = dev_priv->max_dotclk_freq; |
cf532bb2 | 7235 | pipe_config->double_wide = true; |
ad3a4479 | 7236 | } |
f3261156 | 7237 | } |
ad3a4479 | 7238 | |
f3261156 VS |
7239 | if (adjusted_mode->crtc_clock > clock_limit) { |
7240 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
7241 | adjusted_mode->crtc_clock, clock_limit, | |
7242 | yesno(pipe_config->double_wide)); | |
7243 | return -EINVAL; | |
2c07245f | 7244 | } |
89749350 | 7245 | |
1d1d0e27 VS |
7246 | /* |
7247 | * Pipe horizontal size must be even in: | |
7248 | * - DVO ganged mode | |
7249 | * - LVDS dual channel mode | |
7250 | * - Double wide pipe | |
7251 | */ | |
2d84d2b3 | 7252 | if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
7253 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
7254 | pipe_config->pipe_src_w &= ~1; | |
7255 | ||
8693a824 DL |
7256 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
7257 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 | 7258 | */ |
9beb5fea | 7259 | if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) && |
aad941d5 | 7260 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) |
e29c22c0 | 7261 | return -EINVAL; |
44f46b42 | 7262 | |
50a0bc90 | 7263 | if (HAS_IPS(dev_priv)) |
a43f6e0f DV |
7264 | hsw_compute_ips_config(crtc, pipe_config); |
7265 | ||
877d48d5 | 7266 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 7267 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 7268 | |
cf5a15be | 7269 | return 0; |
79e53945 JB |
7270 | } |
7271 | ||
1353c4fb | 7272 | static int skylake_get_display_clock_speed(struct drm_i915_private *dev_priv) |
1652d19e | 7273 | { |
1353c4fb | 7274 | u32 cdctl; |
1652d19e | 7275 | |
ea61791e | 7276 | skl_dpll0_update(dev_priv); |
1652d19e | 7277 | |
63911d72 | 7278 | if (dev_priv->cdclk_pll.vco == 0) |
709e05c3 | 7279 | return dev_priv->cdclk_pll.ref; |
1652d19e | 7280 | |
ea61791e | 7281 | cdctl = I915_READ(CDCLK_CTL); |
1652d19e | 7282 | |
63911d72 | 7283 | if (dev_priv->cdclk_pll.vco == 8640000) { |
1652d19e VS |
7284 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { |
7285 | case CDCLK_FREQ_450_432: | |
7286 | return 432000; | |
7287 | case CDCLK_FREQ_337_308: | |
487ed2e4 | 7288 | return 308571; |
ea61791e VS |
7289 | case CDCLK_FREQ_540: |
7290 | return 540000; | |
1652d19e | 7291 | case CDCLK_FREQ_675_617: |
487ed2e4 | 7292 | return 617143; |
1652d19e | 7293 | default: |
ea61791e | 7294 | MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); |
1652d19e VS |
7295 | } |
7296 | } else { | |
1652d19e VS |
7297 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { |
7298 | case CDCLK_FREQ_450_432: | |
7299 | return 450000; | |
7300 | case CDCLK_FREQ_337_308: | |
7301 | return 337500; | |
ea61791e VS |
7302 | case CDCLK_FREQ_540: |
7303 | return 540000; | |
1652d19e VS |
7304 | case CDCLK_FREQ_675_617: |
7305 | return 675000; | |
7306 | default: | |
ea61791e | 7307 | MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); |
1652d19e VS |
7308 | } |
7309 | } | |
7310 | ||
709e05c3 | 7311 | return dev_priv->cdclk_pll.ref; |
1652d19e VS |
7312 | } |
7313 | ||
83d7c81f VS |
7314 | static void bxt_de_pll_update(struct drm_i915_private *dev_priv) |
7315 | { | |
7316 | u32 val; | |
7317 | ||
7318 | dev_priv->cdclk_pll.ref = 19200; | |
1c3f7700 | 7319 | dev_priv->cdclk_pll.vco = 0; |
83d7c81f VS |
7320 | |
7321 | val = I915_READ(BXT_DE_PLL_ENABLE); | |
1c3f7700 | 7322 | if ((val & BXT_DE_PLL_PLL_ENABLE) == 0) |
83d7c81f | 7323 | return; |
83d7c81f | 7324 | |
1c3f7700 ID |
7325 | if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0)) |
7326 | return; | |
83d7c81f VS |
7327 | |
7328 | val = I915_READ(BXT_DE_PLL_CTL); | |
7329 | dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) * | |
7330 | dev_priv->cdclk_pll.ref; | |
7331 | } | |
7332 | ||
1353c4fb | 7333 | static int broxton_get_display_clock_speed(struct drm_i915_private *dev_priv) |
acd3f3d3 | 7334 | { |
f5986242 VS |
7335 | u32 divider; |
7336 | int div, vco; | |
acd3f3d3 | 7337 | |
83d7c81f VS |
7338 | bxt_de_pll_update(dev_priv); |
7339 | ||
f5986242 VS |
7340 | vco = dev_priv->cdclk_pll.vco; |
7341 | if (vco == 0) | |
7342 | return dev_priv->cdclk_pll.ref; | |
acd3f3d3 | 7343 | |
f5986242 | 7344 | divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; |
acd3f3d3 | 7345 | |
f5986242 | 7346 | switch (divider) { |
acd3f3d3 | 7347 | case BXT_CDCLK_CD2X_DIV_SEL_1: |
f5986242 VS |
7348 | div = 2; |
7349 | break; | |
acd3f3d3 | 7350 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: |
89b3c3c7 | 7351 | WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n"); |
f5986242 VS |
7352 | div = 3; |
7353 | break; | |
acd3f3d3 | 7354 | case BXT_CDCLK_CD2X_DIV_SEL_2: |
f5986242 VS |
7355 | div = 4; |
7356 | break; | |
acd3f3d3 | 7357 | case BXT_CDCLK_CD2X_DIV_SEL_4: |
f5986242 VS |
7358 | div = 8; |
7359 | break; | |
7360 | default: | |
7361 | MISSING_CASE(divider); | |
7362 | return dev_priv->cdclk_pll.ref; | |
acd3f3d3 BP |
7363 | } |
7364 | ||
f5986242 | 7365 | return DIV_ROUND_CLOSEST(vco, div); |
acd3f3d3 BP |
7366 | } |
7367 | ||
1353c4fb | 7368 | static int broadwell_get_display_clock_speed(struct drm_i915_private *dev_priv) |
1652d19e | 7369 | { |
1652d19e VS |
7370 | uint32_t lcpll = I915_READ(LCPLL_CTL); |
7371 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
7372 | ||
7373 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
7374 | return 800000; | |
7375 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
7376 | return 450000; | |
7377 | else if (freq == LCPLL_CLK_FREQ_450) | |
7378 | return 450000; | |
7379 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
7380 | return 540000; | |
7381 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
7382 | return 337500; | |
7383 | else | |
7384 | return 675000; | |
7385 | } | |
7386 | ||
1353c4fb | 7387 | static int haswell_get_display_clock_speed(struct drm_i915_private *dev_priv) |
1652d19e | 7388 | { |
1652d19e VS |
7389 | uint32_t lcpll = I915_READ(LCPLL_CTL); |
7390 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
7391 | ||
7392 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
7393 | return 800000; | |
7394 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
7395 | return 450000; | |
7396 | else if (freq == LCPLL_CLK_FREQ_450) | |
7397 | return 450000; | |
50a0bc90 | 7398 | else if (IS_HSW_ULT(dev_priv)) |
1652d19e VS |
7399 | return 337500; |
7400 | else | |
7401 | return 540000; | |
79e53945 JB |
7402 | } |
7403 | ||
1353c4fb | 7404 | static int valleyview_get_display_clock_speed(struct drm_i915_private *dev_priv) |
25eb05fc | 7405 | { |
1353c4fb | 7406 | return vlv_get_cck_clock_hpll(dev_priv, "cdclk", |
bfa7df01 | 7407 | CCK_DISPLAY_CLOCK_CONTROL); |
25eb05fc JB |
7408 | } |
7409 | ||
1353c4fb | 7410 | static int ilk_get_display_clock_speed(struct drm_i915_private *dev_priv) |
b37a6434 VS |
7411 | { |
7412 | return 450000; | |
7413 | } | |
7414 | ||
1353c4fb | 7415 | static int i945_get_display_clock_speed(struct drm_i915_private *dev_priv) |
e70236a8 JB |
7416 | { |
7417 | return 400000; | |
7418 | } | |
79e53945 | 7419 | |
1353c4fb | 7420 | static int i915_get_display_clock_speed(struct drm_i915_private *dev_priv) |
79e53945 | 7421 | { |
e907f170 | 7422 | return 333333; |
e70236a8 | 7423 | } |
79e53945 | 7424 | |
1353c4fb | 7425 | static int i9xx_misc_get_display_clock_speed(struct drm_i915_private *dev_priv) |
e70236a8 JB |
7426 | { |
7427 | return 200000; | |
7428 | } | |
79e53945 | 7429 | |
1353c4fb | 7430 | static int pnv_get_display_clock_speed(struct drm_i915_private *dev_priv) |
257a7ffc | 7431 | { |
1353c4fb | 7432 | struct pci_dev *pdev = dev_priv->drm.pdev; |
257a7ffc DV |
7433 | u16 gcfgc = 0; |
7434 | ||
52a05c30 | 7435 | pci_read_config_word(pdev, GCFGC, &gcfgc); |
257a7ffc DV |
7436 | |
7437 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
7438 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 7439 | return 266667; |
257a7ffc | 7440 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 7441 | return 333333; |
257a7ffc | 7442 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 7443 | return 444444; |
257a7ffc DV |
7444 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
7445 | return 200000; | |
7446 | default: | |
7447 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
7448 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 7449 | return 133333; |
257a7ffc | 7450 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 7451 | return 166667; |
257a7ffc DV |
7452 | } |
7453 | } | |
7454 | ||
1353c4fb | 7455 | static int i915gm_get_display_clock_speed(struct drm_i915_private *dev_priv) |
e70236a8 | 7456 | { |
1353c4fb | 7457 | struct pci_dev *pdev = dev_priv->drm.pdev; |
e70236a8 | 7458 | u16 gcfgc = 0; |
79e53945 | 7459 | |
52a05c30 | 7460 | pci_read_config_word(pdev, GCFGC, &gcfgc); |
e70236a8 JB |
7461 | |
7462 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 7463 | return 133333; |
e70236a8 JB |
7464 | else { |
7465 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
7466 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 7467 | return 333333; |
e70236a8 JB |
7468 | default: |
7469 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
7470 | return 190000; | |
79e53945 | 7471 | } |
e70236a8 JB |
7472 | } |
7473 | } | |
7474 | ||
1353c4fb | 7475 | static int i865_get_display_clock_speed(struct drm_i915_private *dev_priv) |
e70236a8 | 7476 | { |
e907f170 | 7477 | return 266667; |
e70236a8 JB |
7478 | } |
7479 | ||
1353c4fb | 7480 | static int i85x_get_display_clock_speed(struct drm_i915_private *dev_priv) |
e70236a8 | 7481 | { |
1353c4fb | 7482 | struct pci_dev *pdev = dev_priv->drm.pdev; |
e70236a8 | 7483 | u16 hpllcc = 0; |
1b1d2716 | 7484 | |
65cd2b3f VS |
7485 | /* |
7486 | * 852GM/852GMV only supports 133 MHz and the HPLLCC | |
7487 | * encoding is different :( | |
7488 | * FIXME is this the right way to detect 852GM/852GMV? | |
7489 | */ | |
52a05c30 | 7490 | if (pdev->revision == 0x1) |
65cd2b3f VS |
7491 | return 133333; |
7492 | ||
52a05c30 | 7493 | pci_bus_read_config_word(pdev->bus, |
1b1d2716 VS |
7494 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); |
7495 | ||
e70236a8 JB |
7496 | /* Assume that the hardware is in the high speed state. This |
7497 | * should be the default. | |
7498 | */ | |
7499 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
7500 | case GC_CLOCK_133_200: | |
1b1d2716 | 7501 | case GC_CLOCK_133_200_2: |
e70236a8 JB |
7502 | case GC_CLOCK_100_200: |
7503 | return 200000; | |
7504 | case GC_CLOCK_166_250: | |
7505 | return 250000; | |
7506 | case GC_CLOCK_100_133: | |
e907f170 | 7507 | return 133333; |
1b1d2716 VS |
7508 | case GC_CLOCK_133_266: |
7509 | case GC_CLOCK_133_266_2: | |
7510 | case GC_CLOCK_166_266: | |
7511 | return 266667; | |
e70236a8 | 7512 | } |
79e53945 | 7513 | |
e70236a8 JB |
7514 | /* Shouldn't happen */ |
7515 | return 0; | |
7516 | } | |
79e53945 | 7517 | |
1353c4fb | 7518 | static int i830_get_display_clock_speed(struct drm_i915_private *dev_priv) |
e70236a8 | 7519 | { |
e907f170 | 7520 | return 133333; |
79e53945 JB |
7521 | } |
7522 | ||
1353c4fb | 7523 | static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv) |
34edce2f | 7524 | { |
34edce2f VS |
7525 | static const unsigned int blb_vco[8] = { |
7526 | [0] = 3200000, | |
7527 | [1] = 4000000, | |
7528 | [2] = 5333333, | |
7529 | [3] = 4800000, | |
7530 | [4] = 6400000, | |
7531 | }; | |
7532 | static const unsigned int pnv_vco[8] = { | |
7533 | [0] = 3200000, | |
7534 | [1] = 4000000, | |
7535 | [2] = 5333333, | |
7536 | [3] = 4800000, | |
7537 | [4] = 2666667, | |
7538 | }; | |
7539 | static const unsigned int cl_vco[8] = { | |
7540 | [0] = 3200000, | |
7541 | [1] = 4000000, | |
7542 | [2] = 5333333, | |
7543 | [3] = 6400000, | |
7544 | [4] = 3333333, | |
7545 | [5] = 3566667, | |
7546 | [6] = 4266667, | |
7547 | }; | |
7548 | static const unsigned int elk_vco[8] = { | |
7549 | [0] = 3200000, | |
7550 | [1] = 4000000, | |
7551 | [2] = 5333333, | |
7552 | [3] = 4800000, | |
7553 | }; | |
7554 | static const unsigned int ctg_vco[8] = { | |
7555 | [0] = 3200000, | |
7556 | [1] = 4000000, | |
7557 | [2] = 5333333, | |
7558 | [3] = 6400000, | |
7559 | [4] = 2666667, | |
7560 | [5] = 4266667, | |
7561 | }; | |
7562 | const unsigned int *vco_table; | |
7563 | unsigned int vco; | |
7564 | uint8_t tmp = 0; | |
7565 | ||
7566 | /* FIXME other chipsets? */ | |
50a0bc90 | 7567 | if (IS_GM45(dev_priv)) |
34edce2f | 7568 | vco_table = ctg_vco; |
9beb5fea | 7569 | else if (IS_G4X(dev_priv)) |
34edce2f | 7570 | vco_table = elk_vco; |
c0f86832 | 7571 | else if (IS_I965GM(dev_priv)) |
34edce2f | 7572 | vco_table = cl_vco; |
1353c4fb | 7573 | else if (IS_PINEVIEW(dev_priv)) |
34edce2f | 7574 | vco_table = pnv_vco; |
1353c4fb | 7575 | else if (IS_G33(dev_priv)) |
34edce2f VS |
7576 | vco_table = blb_vco; |
7577 | else | |
7578 | return 0; | |
7579 | ||
1353c4fb | 7580 | tmp = I915_READ(IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO); |
34edce2f VS |
7581 | |
7582 | vco = vco_table[tmp & 0x7]; | |
7583 | if (vco == 0) | |
7584 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); | |
7585 | else | |
7586 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); | |
7587 | ||
7588 | return vco; | |
7589 | } | |
7590 | ||
1353c4fb | 7591 | static int gm45_get_display_clock_speed(struct drm_i915_private *dev_priv) |
34edce2f | 7592 | { |
1353c4fb VS |
7593 | struct pci_dev *pdev = dev_priv->drm.pdev; |
7594 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv); | |
34edce2f VS |
7595 | uint16_t tmp = 0; |
7596 | ||
52a05c30 | 7597 | pci_read_config_word(pdev, GCFGC, &tmp); |
34edce2f VS |
7598 | |
7599 | cdclk_sel = (tmp >> 12) & 0x1; | |
7600 | ||
7601 | switch (vco) { | |
7602 | case 2666667: | |
7603 | case 4000000: | |
7604 | case 5333333: | |
7605 | return cdclk_sel ? 333333 : 222222; | |
7606 | case 3200000: | |
7607 | return cdclk_sel ? 320000 : 228571; | |
7608 | default: | |
7609 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); | |
7610 | return 222222; | |
7611 | } | |
7612 | } | |
7613 | ||
1353c4fb | 7614 | static int i965gm_get_display_clock_speed(struct drm_i915_private *dev_priv) |
34edce2f | 7615 | { |
1353c4fb | 7616 | struct pci_dev *pdev = dev_priv->drm.pdev; |
34edce2f VS |
7617 | static const uint8_t div_3200[] = { 16, 10, 8 }; |
7618 | static const uint8_t div_4000[] = { 20, 12, 10 }; | |
7619 | static const uint8_t div_5333[] = { 24, 16, 14 }; | |
7620 | const uint8_t *div_table; | |
1353c4fb | 7621 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv); |
34edce2f VS |
7622 | uint16_t tmp = 0; |
7623 | ||
52a05c30 | 7624 | pci_read_config_word(pdev, GCFGC, &tmp); |
34edce2f VS |
7625 | |
7626 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; | |
7627 | ||
7628 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7629 | goto fail; | |
7630 | ||
7631 | switch (vco) { | |
7632 | case 3200000: | |
7633 | div_table = div_3200; | |
7634 | break; | |
7635 | case 4000000: | |
7636 | div_table = div_4000; | |
7637 | break; | |
7638 | case 5333333: | |
7639 | div_table = div_5333; | |
7640 | break; | |
7641 | default: | |
7642 | goto fail; | |
7643 | } | |
7644 | ||
7645 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7646 | ||
caf4e252 | 7647 | fail: |
34edce2f VS |
7648 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); |
7649 | return 200000; | |
7650 | } | |
7651 | ||
1353c4fb | 7652 | static int g33_get_display_clock_speed(struct drm_i915_private *dev_priv) |
34edce2f | 7653 | { |
1353c4fb | 7654 | struct pci_dev *pdev = dev_priv->drm.pdev; |
34edce2f VS |
7655 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; |
7656 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; | |
7657 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; | |
7658 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; | |
7659 | const uint8_t *div_table; | |
1353c4fb | 7660 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv); |
34edce2f VS |
7661 | uint16_t tmp = 0; |
7662 | ||
52a05c30 | 7663 | pci_read_config_word(pdev, GCFGC, &tmp); |
34edce2f VS |
7664 | |
7665 | cdclk_sel = (tmp >> 4) & 0x7; | |
7666 | ||
7667 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7668 | goto fail; | |
7669 | ||
7670 | switch (vco) { | |
7671 | case 3200000: | |
7672 | div_table = div_3200; | |
7673 | break; | |
7674 | case 4000000: | |
7675 | div_table = div_4000; | |
7676 | break; | |
7677 | case 4800000: | |
7678 | div_table = div_4800; | |
7679 | break; | |
7680 | case 5333333: | |
7681 | div_table = div_5333; | |
7682 | break; | |
7683 | default: | |
7684 | goto fail; | |
7685 | } | |
7686 | ||
7687 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7688 | ||
caf4e252 | 7689 | fail: |
34edce2f VS |
7690 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); |
7691 | return 190476; | |
7692 | } | |
7693 | ||
2c07245f | 7694 | static void |
a65851af | 7695 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 7696 | { |
a65851af VS |
7697 | while (*num > DATA_LINK_M_N_MASK || |
7698 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
7699 | *num >>= 1; |
7700 | *den >>= 1; | |
7701 | } | |
7702 | } | |
7703 | ||
a65851af VS |
7704 | static void compute_m_n(unsigned int m, unsigned int n, |
7705 | uint32_t *ret_m, uint32_t *ret_n) | |
7706 | { | |
7707 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
7708 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
7709 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
7710 | } | |
7711 | ||
e69d0bc1 DV |
7712 | void |
7713 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
7714 | int pixel_clock, int link_clock, | |
7715 | struct intel_link_m_n *m_n) | |
2c07245f | 7716 | { |
e69d0bc1 | 7717 | m_n->tu = 64; |
a65851af VS |
7718 | |
7719 | compute_m_n(bits_per_pixel * pixel_clock, | |
7720 | link_clock * nlanes * 8, | |
7721 | &m_n->gmch_m, &m_n->gmch_n); | |
7722 | ||
7723 | compute_m_n(pixel_clock, link_clock, | |
7724 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
7725 | } |
7726 | ||
a7615030 CW |
7727 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
7728 | { | |
d330a953 JN |
7729 | if (i915.panel_use_ssc >= 0) |
7730 | return i915.panel_use_ssc != 0; | |
41aa3448 | 7731 | return dev_priv->vbt.lvds_use_ssc |
435793df | 7732 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
7733 | } |
7734 | ||
7429e9d4 | 7735 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 7736 | { |
7df00d7a | 7737 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 7738 | } |
f47709a9 | 7739 | |
7429e9d4 DV |
7740 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
7741 | { | |
7742 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
7743 | } |
7744 | ||
f47709a9 | 7745 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 7746 | struct intel_crtc_state *crtc_state, |
9e2c8475 | 7747 | struct dpll *reduced_clock) |
a7516a05 | 7748 | { |
9b1e14f4 | 7749 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
a7516a05 JB |
7750 | u32 fp, fp2 = 0; |
7751 | ||
9b1e14f4 | 7752 | if (IS_PINEVIEW(dev_priv)) { |
190f68c5 | 7753 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7754 | if (reduced_clock) |
7429e9d4 | 7755 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 7756 | } else { |
190f68c5 | 7757 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7758 | if (reduced_clock) |
7429e9d4 | 7759 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
7760 | } |
7761 | ||
190f68c5 | 7762 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 7763 | |
f47709a9 | 7764 | crtc->lowfreq_avail = false; |
2d84d2b3 | 7765 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 7766 | reduced_clock) { |
190f68c5 | 7767 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 7768 | crtc->lowfreq_avail = true; |
a7516a05 | 7769 | } else { |
190f68c5 | 7770 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
7771 | } |
7772 | } | |
7773 | ||
5e69f97f CML |
7774 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
7775 | pipe) | |
89b667f8 JB |
7776 | { |
7777 | u32 reg_val; | |
7778 | ||
7779 | /* | |
7780 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
7781 | * and set it to a reasonable value instead. | |
7782 | */ | |
ab3c759a | 7783 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
7784 | reg_val &= 0xffffff00; |
7785 | reg_val |= 0x00000030; | |
ab3c759a | 7786 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7787 | |
ab3c759a | 7788 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7789 | reg_val &= 0x8cffffff; |
7790 | reg_val = 0x8c000000; | |
ab3c759a | 7791 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 7792 | |
ab3c759a | 7793 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 7794 | reg_val &= 0xffffff00; |
ab3c759a | 7795 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7796 | |
ab3c759a | 7797 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7798 | reg_val &= 0x00ffffff; |
7799 | reg_val |= 0xb0000000; | |
ab3c759a | 7800 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
7801 | } |
7802 | ||
b551842d DV |
7803 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
7804 | struct intel_link_m_n *m_n) | |
7805 | { | |
7806 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7807 | struct drm_i915_private *dev_priv = to_i915(dev); |
b551842d DV |
7808 | int pipe = crtc->pipe; |
7809 | ||
e3b95f1e DV |
7810 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7811 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
7812 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
7813 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
7814 | } |
7815 | ||
7816 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
7817 | struct intel_link_m_n *m_n, |
7818 | struct intel_link_m_n *m2_n2) | |
b551842d | 7819 | { |
6315b5d3 | 7820 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
b551842d | 7821 | int pipe = crtc->pipe; |
6e3c9717 | 7822 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d | 7823 | |
6315b5d3 | 7824 | if (INTEL_GEN(dev_priv) >= 5) { |
b551842d DV |
7825 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7826 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
7827 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
7828 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
7829 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
7830 | * for gen < 8) and if DRRS is supported (to make sure the | |
7831 | * registers are not unnecessarily accessed). | |
7832 | */ | |
920a14b2 TU |
7833 | if (m2_n2 && (IS_CHERRYVIEW(dev_priv) || |
7834 | INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) { | |
f769cd24 VK |
7835 | I915_WRITE(PIPE_DATA_M2(transcoder), |
7836 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
7837 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
7838 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
7839 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
7840 | } | |
b551842d | 7841 | } else { |
e3b95f1e DV |
7842 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7843 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
7844 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
7845 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
7846 | } |
7847 | } | |
7848 | ||
fe3cd48d | 7849 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 7850 | { |
fe3cd48d R |
7851 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
7852 | ||
7853 | if (m_n == M1_N1) { | |
7854 | dp_m_n = &crtc->config->dp_m_n; | |
7855 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
7856 | } else if (m_n == M2_N2) { | |
7857 | ||
7858 | /* | |
7859 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
7860 | * needs to be programmed into M1_N1. | |
7861 | */ | |
7862 | dp_m_n = &crtc->config->dp_m2_n2; | |
7863 | } else { | |
7864 | DRM_ERROR("Unsupported divider value\n"); | |
7865 | return; | |
7866 | } | |
7867 | ||
6e3c9717 ACO |
7868 | if (crtc->config->has_pch_encoder) |
7869 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 7870 | else |
fe3cd48d | 7871 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
7872 | } |
7873 | ||
251ac862 DV |
7874 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
7875 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 | 7876 | { |
03ed5cbf | 7877 | pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | |
cd2d34d9 | 7878 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
7879 | if (crtc->pipe != PIPE_A) |
7880 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
bdd4b6a6 | 7881 | |
cd2d34d9 | 7882 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 7883 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
7884 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | |
7885 | DPLL_EXT_BUFFER_ENABLE_VLV; | |
7886 | ||
03ed5cbf VS |
7887 | pipe_config->dpll_hw_state.dpll_md = |
7888 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
7889 | } | |
bdd4b6a6 | 7890 | |
03ed5cbf VS |
7891 | static void chv_compute_dpll(struct intel_crtc *crtc, |
7892 | struct intel_crtc_state *pipe_config) | |
7893 | { | |
7894 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | | |
cd2d34d9 | 7895 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
7896 | if (crtc->pipe != PIPE_A) |
7897 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
7898 | ||
cd2d34d9 | 7899 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 7900 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
7901 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; |
7902 | ||
03ed5cbf VS |
7903 | pipe_config->dpll_hw_state.dpll_md = |
7904 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
bdd4b6a6 DV |
7905 | } |
7906 | ||
d288f65f | 7907 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7908 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 7909 | { |
f47709a9 | 7910 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7911 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 7912 | enum pipe pipe = crtc->pipe; |
bdd4b6a6 | 7913 | u32 mdiv; |
a0c4da24 | 7914 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 7915 | u32 coreclk, reg_val; |
a0c4da24 | 7916 | |
cd2d34d9 VS |
7917 | /* Enable Refclk */ |
7918 | I915_WRITE(DPLL(pipe), | |
7919 | pipe_config->dpll_hw_state.dpll & | |
7920 | ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); | |
7921 | ||
7922 | /* No need to actually set up the DPLL with DSI */ | |
7923 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
7924 | return; | |
7925 | ||
a580516d | 7926 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 7927 | |
d288f65f VS |
7928 | bestn = pipe_config->dpll.n; |
7929 | bestm1 = pipe_config->dpll.m1; | |
7930 | bestm2 = pipe_config->dpll.m2; | |
7931 | bestp1 = pipe_config->dpll.p1; | |
7932 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 7933 | |
89b667f8 JB |
7934 | /* See eDP HDMI DPIO driver vbios notes doc */ |
7935 | ||
7936 | /* PLL B needs special handling */ | |
bdd4b6a6 | 7937 | if (pipe == PIPE_B) |
5e69f97f | 7938 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
7939 | |
7940 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 7941 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
7942 | |
7943 | /* Disable target IRef on PLL */ | |
ab3c759a | 7944 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 7945 | reg_val &= 0x00ffffff; |
ab3c759a | 7946 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
7947 | |
7948 | /* Disable fast lock */ | |
ab3c759a | 7949 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
7950 | |
7951 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
7952 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
7953 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
7954 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 7955 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
7956 | |
7957 | /* | |
7958 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
7959 | * but we don't support that). | |
7960 | * Note: don't use the DAC post divider as it seems unstable. | |
7961 | */ | |
7962 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 7963 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7964 | |
a0c4da24 | 7965 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 7966 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7967 | |
89b667f8 | 7968 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 7969 | if (pipe_config->port_clock == 162000 || |
2d84d2b3 VS |
7970 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) || |
7971 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 7972 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 7973 | 0x009f0003); |
89b667f8 | 7974 | else |
ab3c759a | 7975 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
7976 | 0x00d0000f); |
7977 | ||
37a5650b | 7978 | if (intel_crtc_has_dp_encoder(pipe_config)) { |
89b667f8 | 7979 | /* Use SSC source */ |
bdd4b6a6 | 7980 | if (pipe == PIPE_A) |
ab3c759a | 7981 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7982 | 0x0df40000); |
7983 | else | |
ab3c759a | 7984 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7985 | 0x0df70000); |
7986 | } else { /* HDMI or VGA */ | |
7987 | /* Use bend source */ | |
bdd4b6a6 | 7988 | if (pipe == PIPE_A) |
ab3c759a | 7989 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7990 | 0x0df70000); |
7991 | else | |
ab3c759a | 7992 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7993 | 0x0df40000); |
7994 | } | |
a0c4da24 | 7995 | |
ab3c759a | 7996 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 7997 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
2210ce7f | 7998 | if (intel_crtc_has_dp_encoder(crtc->config)) |
89b667f8 | 7999 | coreclk |= 0x01000000; |
ab3c759a | 8000 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 8001 | |
ab3c759a | 8002 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 8003 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
8004 | } |
8005 | ||
d288f65f | 8006 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 8007 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
8008 | { |
8009 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8010 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 8011 | enum pipe pipe = crtc->pipe; |
9d556c99 | 8012 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9cbe40c1 | 8013 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 8014 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 8015 | u32 dpio_val; |
9cbe40c1 | 8016 | int vco; |
9d556c99 | 8017 | |
cd2d34d9 VS |
8018 | /* Enable Refclk and SSC */ |
8019 | I915_WRITE(DPLL(pipe), | |
8020 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); | |
8021 | ||
8022 | /* No need to actually set up the DPLL with DSI */ | |
8023 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
8024 | return; | |
8025 | ||
d288f65f VS |
8026 | bestn = pipe_config->dpll.n; |
8027 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
8028 | bestm1 = pipe_config->dpll.m1; | |
8029 | bestm2 = pipe_config->dpll.m2 >> 22; | |
8030 | bestp1 = pipe_config->dpll.p1; | |
8031 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 8032 | vco = pipe_config->dpll.vco; |
a945ce7e | 8033 | dpio_val = 0; |
9cbe40c1 | 8034 | loopfilter = 0; |
9d556c99 | 8035 | |
a580516d | 8036 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 8037 | |
9d556c99 CML |
8038 | /* p1 and p2 divider */ |
8039 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
8040 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
8041 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
8042 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
8043 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
8044 | ||
8045 | /* Feedback post-divider - m2 */ | |
8046 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
8047 | ||
8048 | /* Feedback refclk divider - n and m1 */ | |
8049 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
8050 | DPIO_CHV_M1_DIV_BY_2 | | |
8051 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
8052 | ||
8053 | /* M2 fraction division */ | |
25a25dfc | 8054 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
8055 | |
8056 | /* M2 fraction division enable */ | |
a945ce7e VP |
8057 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
8058 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
8059 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
8060 | if (bestm2_frac) | |
8061 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
8062 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 8063 | |
de3a0fde VP |
8064 | /* Program digital lock detect threshold */ |
8065 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
8066 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
8067 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
8068 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
8069 | if (!bestm2_frac) | |
8070 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
8071 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
8072 | ||
9d556c99 | 8073 | /* Loop filter */ |
9cbe40c1 VP |
8074 | if (vco == 5400000) { |
8075 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
8076 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
8077 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
8078 | tribuf_calcntr = 0x9; | |
8079 | } else if (vco <= 6200000) { | |
8080 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
8081 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
8082 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
8083 | tribuf_calcntr = 0x9; | |
8084 | } else if (vco <= 6480000) { | |
8085 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
8086 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
8087 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
8088 | tribuf_calcntr = 0x8; | |
8089 | } else { | |
8090 | /* Not supported. Apply the same limits as in the max case */ | |
8091 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
8092 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
8093 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
8094 | tribuf_calcntr = 0; | |
8095 | } | |
9d556c99 CML |
8096 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
8097 | ||
968040b2 | 8098 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
8099 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
8100 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
8101 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
8102 | ||
9d556c99 CML |
8103 | /* AFC Recal */ |
8104 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
8105 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
8106 | DPIO_AFC_RECAL); | |
8107 | ||
a580516d | 8108 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
8109 | } |
8110 | ||
d288f65f VS |
8111 | /** |
8112 | * vlv_force_pll_on - forcibly enable just the PLL | |
8113 | * @dev_priv: i915 private structure | |
8114 | * @pipe: pipe PLL to enable | |
8115 | * @dpll: PLL configuration | |
8116 | * | |
8117 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
8118 | * in cases where we need the PLL enabled even when @pipe is not going to | |
8119 | * be enabled. | |
8120 | */ | |
30ad9814 | 8121 | int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, |
3f36b937 | 8122 | const struct dpll *dpll) |
d288f65f | 8123 | { |
b91eb5cc | 8124 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
3f36b937 TU |
8125 | struct intel_crtc_state *pipe_config; |
8126 | ||
8127 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); | |
8128 | if (!pipe_config) | |
8129 | return -ENOMEM; | |
8130 | ||
8131 | pipe_config->base.crtc = &crtc->base; | |
8132 | pipe_config->pixel_multiplier = 1; | |
8133 | pipe_config->dpll = *dpll; | |
d288f65f | 8134 | |
30ad9814 | 8135 | if (IS_CHERRYVIEW(dev_priv)) { |
3f36b937 TU |
8136 | chv_compute_dpll(crtc, pipe_config); |
8137 | chv_prepare_pll(crtc, pipe_config); | |
8138 | chv_enable_pll(crtc, pipe_config); | |
d288f65f | 8139 | } else { |
3f36b937 TU |
8140 | vlv_compute_dpll(crtc, pipe_config); |
8141 | vlv_prepare_pll(crtc, pipe_config); | |
8142 | vlv_enable_pll(crtc, pipe_config); | |
d288f65f | 8143 | } |
3f36b937 TU |
8144 | |
8145 | kfree(pipe_config); | |
8146 | ||
8147 | return 0; | |
d288f65f VS |
8148 | } |
8149 | ||
8150 | /** | |
8151 | * vlv_force_pll_off - forcibly disable just the PLL | |
8152 | * @dev_priv: i915 private structure | |
8153 | * @pipe: pipe PLL to disable | |
8154 | * | |
8155 | * Disable the PLL for @pipe. To be used in cases where we need | |
8156 | * the PLL enabled even when @pipe is not going to be enabled. | |
8157 | */ | |
30ad9814 | 8158 | void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe) |
d288f65f | 8159 | { |
30ad9814 VS |
8160 | if (IS_CHERRYVIEW(dev_priv)) |
8161 | chv_disable_pll(dev_priv, pipe); | |
d288f65f | 8162 | else |
30ad9814 | 8163 | vlv_disable_pll(dev_priv, pipe); |
d288f65f VS |
8164 | } |
8165 | ||
251ac862 DV |
8166 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
8167 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 8168 | struct dpll *reduced_clock) |
eb1cbe48 | 8169 | { |
9b1e14f4 | 8170 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
eb1cbe48 | 8171 | u32 dpll; |
190f68c5 | 8172 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 8173 | |
190f68c5 | 8174 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 8175 | |
eb1cbe48 DV |
8176 | dpll = DPLL_VGA_MODE_DIS; |
8177 | ||
2d84d2b3 | 8178 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
8179 | dpll |= DPLLB_MODE_LVDS; |
8180 | else | |
8181 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 8182 | |
50a0bc90 | 8183 | if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || IS_G33(dev_priv)) { |
190f68c5 | 8184 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 8185 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 8186 | } |
198a037f | 8187 | |
3d6e9ee0 VS |
8188 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
8189 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 8190 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 8191 | |
37a5650b | 8192 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 8193 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
8194 | |
8195 | /* compute bitmask from p1 value */ | |
9b1e14f4 | 8196 | if (IS_PINEVIEW(dev_priv)) |
eb1cbe48 DV |
8197 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; |
8198 | else { | |
8199 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
9beb5fea | 8200 | if (IS_G4X(dev_priv) && reduced_clock) |
eb1cbe48 DV |
8201 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
8202 | } | |
8203 | switch (clock->p2) { | |
8204 | case 5: | |
8205 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8206 | break; | |
8207 | case 7: | |
8208 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8209 | break; | |
8210 | case 10: | |
8211 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8212 | break; | |
8213 | case 14: | |
8214 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8215 | break; | |
8216 | } | |
9b1e14f4 | 8217 | if (INTEL_GEN(dev_priv) >= 4) |
eb1cbe48 DV |
8218 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
8219 | ||
190f68c5 | 8220 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 8221 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
2d84d2b3 | 8222 | else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 8223 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
8224 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
8225 | else | |
8226 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8227 | ||
8228 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 8229 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 8230 | |
9b1e14f4 | 8231 | if (INTEL_GEN(dev_priv) >= 4) { |
190f68c5 | 8232 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8233 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 8234 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
8235 | } |
8236 | } | |
8237 | ||
251ac862 DV |
8238 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
8239 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 8240 | struct dpll *reduced_clock) |
eb1cbe48 | 8241 | { |
f47709a9 | 8242 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 8243 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb1cbe48 | 8244 | u32 dpll; |
190f68c5 | 8245 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 8246 | |
190f68c5 | 8247 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 8248 | |
eb1cbe48 DV |
8249 | dpll = DPLL_VGA_MODE_DIS; |
8250 | ||
2d84d2b3 | 8251 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
8252 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
8253 | } else { | |
8254 | if (clock->p1 == 2) | |
8255 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
8256 | else | |
8257 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
8258 | if (clock->p2 == 4) | |
8259 | dpll |= PLL_P2_DIVIDE_BY_4; | |
8260 | } | |
8261 | ||
50a0bc90 TU |
8262 | if (!IS_I830(dev_priv) && |
8263 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) | |
4a33e48d DV |
8264 | dpll |= DPLL_DVO_2X_MODE; |
8265 | ||
2d84d2b3 | 8266 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 8267 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
8268 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
8269 | else | |
8270 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8271 | ||
8272 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 8273 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
8274 | } |
8275 | ||
8a654f3b | 8276 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c | 8277 | { |
6315b5d3 | 8278 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
b0e77b9c | 8279 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 8280 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
7c5f93b0 | 8281 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
8282 | uint32_t crtc_vtotal, crtc_vblank_end; |
8283 | int vsyncshift = 0; | |
4d8a62ea DV |
8284 | |
8285 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
8286 | * the hw state checker will get angry at the mismatch. */ | |
8287 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
8288 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 8289 | |
609aeaca | 8290 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 8291 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
8292 | crtc_vtotal -= 1; |
8293 | crtc_vblank_end -= 1; | |
609aeaca | 8294 | |
2d84d2b3 | 8295 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
8296 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
8297 | else | |
8298 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
8299 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
8300 | if (vsyncshift < 0) |
8301 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
8302 | } |
8303 | ||
6315b5d3 | 8304 | if (INTEL_GEN(dev_priv) > 3) |
fe2b8f9d | 8305 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 8306 | |
fe2b8f9d | 8307 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
8308 | (adjusted_mode->crtc_hdisplay - 1) | |
8309 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 8310 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
8311 | (adjusted_mode->crtc_hblank_start - 1) | |
8312 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 8313 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
8314 | (adjusted_mode->crtc_hsync_start - 1) | |
8315 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
8316 | ||
fe2b8f9d | 8317 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 8318 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 8319 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 8320 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 8321 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 8322 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 8323 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
8324 | (adjusted_mode->crtc_vsync_start - 1) | |
8325 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
8326 | ||
b5e508d4 PZ |
8327 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
8328 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
8329 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
8330 | * bits. */ | |
772c2a51 | 8331 | if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && |
b5e508d4 PZ |
8332 | (pipe == PIPE_B || pipe == PIPE_C)) |
8333 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
8334 | ||
bc58be60 JN |
8335 | } |
8336 | ||
8337 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc) | |
8338 | { | |
8339 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 8340 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 JN |
8341 | enum pipe pipe = intel_crtc->pipe; |
8342 | ||
b0e77b9c PZ |
8343 | /* pipesrc controls the size that is scaled from, which should |
8344 | * always be the user's requested size. | |
8345 | */ | |
8346 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
8347 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
8348 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
8349 | } |
8350 | ||
1bd1bd80 | 8351 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 8352 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
8353 | { |
8354 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8355 | struct drm_i915_private *dev_priv = to_i915(dev); |
1bd1bd80 DV |
8356 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
8357 | uint32_t tmp; | |
8358 | ||
8359 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
8360 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
8361 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 8362 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
8363 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
8364 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 8365 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
8366 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
8367 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
8368 | |
8369 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
8370 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
8371 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 8372 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
8373 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
8374 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 8375 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
8376 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
8377 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
8378 | |
8379 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
8380 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
8381 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
8382 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 | 8383 | } |
bc58be60 JN |
8384 | } |
8385 | ||
8386 | static void intel_get_pipe_src_size(struct intel_crtc *crtc, | |
8387 | struct intel_crtc_state *pipe_config) | |
8388 | { | |
8389 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8390 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 | 8391 | u32 tmp; |
1bd1bd80 DV |
8392 | |
8393 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
8394 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
8395 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
8396 | ||
2d112de7 ACO |
8397 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
8398 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
8399 | } |
8400 | ||
f6a83288 | 8401 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 8402 | struct intel_crtc_state *pipe_config) |
babea61d | 8403 | { |
2d112de7 ACO |
8404 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
8405 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
8406 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
8407 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 8408 | |
2d112de7 ACO |
8409 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
8410 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
8411 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
8412 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 8413 | |
2d112de7 | 8414 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 8415 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 8416 | |
2d112de7 ACO |
8417 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
8418 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
cd13f5ab ML |
8419 | |
8420 | mode->hsync = drm_mode_hsync(mode); | |
8421 | mode->vrefresh = drm_mode_vrefresh(mode); | |
8422 | drm_mode_set_name(mode); | |
babea61d JB |
8423 | } |
8424 | ||
84b046f3 DV |
8425 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
8426 | { | |
6315b5d3 | 8427 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
84b046f3 DV |
8428 | uint32_t pipeconf; |
8429 | ||
9f11a9e4 | 8430 | pipeconf = 0; |
84b046f3 | 8431 | |
b6b5d049 VS |
8432 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
8433 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8434 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 8435 | |
6e3c9717 | 8436 | if (intel_crtc->config->double_wide) |
cf532bb2 | 8437 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 8438 | |
ff9ce46e | 8439 | /* only g4x and later have fancy bpc/dither controls */ |
9beb5fea TU |
8440 | if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
8441 | IS_CHERRYVIEW(dev_priv)) { | |
ff9ce46e | 8442 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 8443 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 8444 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 8445 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 8446 | |
6e3c9717 | 8447 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
8448 | case 18: |
8449 | pipeconf |= PIPECONF_6BPC; | |
8450 | break; | |
8451 | case 24: | |
8452 | pipeconf |= PIPECONF_8BPC; | |
8453 | break; | |
8454 | case 30: | |
8455 | pipeconf |= PIPECONF_10BPC; | |
8456 | break; | |
8457 | default: | |
8458 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
8459 | BUG(); | |
84b046f3 DV |
8460 | } |
8461 | } | |
8462 | ||
56b857a5 | 8463 | if (HAS_PIPE_CXSR(dev_priv)) { |
84b046f3 DV |
8464 | if (intel_crtc->lowfreq_avail) { |
8465 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
8466 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
8467 | } else { | |
8468 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
8469 | } |
8470 | } | |
8471 | ||
6e3c9717 | 8472 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
6315b5d3 | 8473 | if (INTEL_GEN(dev_priv) < 4 || |
2d84d2b3 | 8474 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
8475 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
8476 | else | |
8477 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
8478 | } else | |
84b046f3 DV |
8479 | pipeconf |= PIPECONF_PROGRESSIVE; |
8480 | ||
920a14b2 | 8481 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
666a4537 | 8482 | intel_crtc->config->limited_color_range) |
9f11a9e4 | 8483 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 8484 | |
84b046f3 DV |
8485 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
8486 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
8487 | } | |
8488 | ||
81c97f52 ACO |
8489 | static int i8xx_crtc_compute_clock(struct intel_crtc *crtc, |
8490 | struct intel_crtc_state *crtc_state) | |
8491 | { | |
8492 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8493 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 8494 | const struct intel_limit *limit; |
81c97f52 ACO |
8495 | int refclk = 48000; |
8496 | ||
8497 | memset(&crtc_state->dpll_hw_state, 0, | |
8498 | sizeof(crtc_state->dpll_hw_state)); | |
8499 | ||
2d84d2b3 | 8500 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
81c97f52 ACO |
8501 | if (intel_panel_use_ssc(dev_priv)) { |
8502 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8503 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
8504 | } | |
8505 | ||
8506 | limit = &intel_limits_i8xx_lvds; | |
2d84d2b3 | 8507 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) { |
81c97f52 ACO |
8508 | limit = &intel_limits_i8xx_dvo; |
8509 | } else { | |
8510 | limit = &intel_limits_i8xx_dac; | |
8511 | } | |
8512 | ||
8513 | if (!crtc_state->clock_set && | |
8514 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8515 | refclk, NULL, &crtc_state->dpll)) { | |
8516 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8517 | return -EINVAL; | |
8518 | } | |
8519 | ||
8520 | i8xx_compute_dpll(crtc, crtc_state, NULL); | |
8521 | ||
8522 | return 0; | |
8523 | } | |
8524 | ||
19ec6693 ACO |
8525 | static int g4x_crtc_compute_clock(struct intel_crtc *crtc, |
8526 | struct intel_crtc_state *crtc_state) | |
8527 | { | |
8528 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8529 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 8530 | const struct intel_limit *limit; |
19ec6693 ACO |
8531 | int refclk = 96000; |
8532 | ||
8533 | memset(&crtc_state->dpll_hw_state, 0, | |
8534 | sizeof(crtc_state->dpll_hw_state)); | |
8535 | ||
2d84d2b3 | 8536 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
19ec6693 ACO |
8537 | if (intel_panel_use_ssc(dev_priv)) { |
8538 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8539 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
8540 | } | |
8541 | ||
8542 | if (intel_is_dual_link_lvds(dev)) | |
8543 | limit = &intel_limits_g4x_dual_channel_lvds; | |
8544 | else | |
8545 | limit = &intel_limits_g4x_single_channel_lvds; | |
2d84d2b3 VS |
8546 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) || |
8547 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
19ec6693 | 8548 | limit = &intel_limits_g4x_hdmi; |
2d84d2b3 | 8549 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
19ec6693 ACO |
8550 | limit = &intel_limits_g4x_sdvo; |
8551 | } else { | |
8552 | /* The option is for other outputs */ | |
8553 | limit = &intel_limits_i9xx_sdvo; | |
8554 | } | |
8555 | ||
8556 | if (!crtc_state->clock_set && | |
8557 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8558 | refclk, NULL, &crtc_state->dpll)) { | |
8559 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8560 | return -EINVAL; | |
8561 | } | |
8562 | ||
8563 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
8564 | ||
8565 | return 0; | |
8566 | } | |
8567 | ||
70e8aa21 ACO |
8568 | static int pnv_crtc_compute_clock(struct intel_crtc *crtc, |
8569 | struct intel_crtc_state *crtc_state) | |
8570 | { | |
8571 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8572 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 8573 | const struct intel_limit *limit; |
70e8aa21 ACO |
8574 | int refclk = 96000; |
8575 | ||
8576 | memset(&crtc_state->dpll_hw_state, 0, | |
8577 | sizeof(crtc_state->dpll_hw_state)); | |
8578 | ||
2d84d2b3 | 8579 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
8580 | if (intel_panel_use_ssc(dev_priv)) { |
8581 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8582 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
8583 | } | |
8584 | ||
8585 | limit = &intel_limits_pineview_lvds; | |
8586 | } else { | |
8587 | limit = &intel_limits_pineview_sdvo; | |
8588 | } | |
8589 | ||
8590 | if (!crtc_state->clock_set && | |
8591 | !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8592 | refclk, NULL, &crtc_state->dpll)) { | |
8593 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8594 | return -EINVAL; | |
8595 | } | |
8596 | ||
8597 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
8598 | ||
8599 | return 0; | |
8600 | } | |
8601 | ||
190f68c5 ACO |
8602 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
8603 | struct intel_crtc_state *crtc_state) | |
79e53945 | 8604 | { |
c7653199 | 8605 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 8606 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 8607 | const struct intel_limit *limit; |
81c97f52 | 8608 | int refclk = 96000; |
79e53945 | 8609 | |
dd3cd74a ACO |
8610 | memset(&crtc_state->dpll_hw_state, 0, |
8611 | sizeof(crtc_state->dpll_hw_state)); | |
8612 | ||
2d84d2b3 | 8613 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
8614 | if (intel_panel_use_ssc(dev_priv)) { |
8615 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8616 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
8617 | } | |
43565a06 | 8618 | |
70e8aa21 ACO |
8619 | limit = &intel_limits_i9xx_lvds; |
8620 | } else { | |
8621 | limit = &intel_limits_i9xx_sdvo; | |
81c97f52 | 8622 | } |
79e53945 | 8623 | |
70e8aa21 ACO |
8624 | if (!crtc_state->clock_set && |
8625 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8626 | refclk, NULL, &crtc_state->dpll)) { | |
8627 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8628 | return -EINVAL; | |
f47709a9 | 8629 | } |
7026d4ac | 8630 | |
81c97f52 | 8631 | i9xx_compute_dpll(crtc, crtc_state, NULL); |
79e53945 | 8632 | |
c8f7a0db | 8633 | return 0; |
f564048e EA |
8634 | } |
8635 | ||
65b3d6a9 ACO |
8636 | static int chv_crtc_compute_clock(struct intel_crtc *crtc, |
8637 | struct intel_crtc_state *crtc_state) | |
8638 | { | |
8639 | int refclk = 100000; | |
1b6f4958 | 8640 | const struct intel_limit *limit = &intel_limits_chv; |
65b3d6a9 ACO |
8641 | |
8642 | memset(&crtc_state->dpll_hw_state, 0, | |
8643 | sizeof(crtc_state->dpll_hw_state)); | |
8644 | ||
65b3d6a9 ACO |
8645 | if (!crtc_state->clock_set && |
8646 | !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8647 | refclk, NULL, &crtc_state->dpll)) { | |
8648 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8649 | return -EINVAL; | |
8650 | } | |
8651 | ||
8652 | chv_compute_dpll(crtc, crtc_state); | |
8653 | ||
8654 | return 0; | |
8655 | } | |
8656 | ||
8657 | static int vlv_crtc_compute_clock(struct intel_crtc *crtc, | |
8658 | struct intel_crtc_state *crtc_state) | |
8659 | { | |
8660 | int refclk = 100000; | |
1b6f4958 | 8661 | const struct intel_limit *limit = &intel_limits_vlv; |
65b3d6a9 ACO |
8662 | |
8663 | memset(&crtc_state->dpll_hw_state, 0, | |
8664 | sizeof(crtc_state->dpll_hw_state)); | |
8665 | ||
65b3d6a9 ACO |
8666 | if (!crtc_state->clock_set && |
8667 | !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8668 | refclk, NULL, &crtc_state->dpll)) { | |
8669 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8670 | return -EINVAL; | |
8671 | } | |
8672 | ||
8673 | vlv_compute_dpll(crtc, crtc_state); | |
8674 | ||
8675 | return 0; | |
8676 | } | |
8677 | ||
2fa2fe9a | 8678 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8679 | struct intel_crtc_state *pipe_config) |
2fa2fe9a | 8680 | { |
6315b5d3 | 8681 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
2fa2fe9a DV |
8682 | uint32_t tmp; |
8683 | ||
50a0bc90 TU |
8684 | if (INTEL_GEN(dev_priv) <= 3 && |
8685 | (IS_I830(dev_priv) || !IS_MOBILE(dev_priv))) | |
dc9e7dec VS |
8686 | return; |
8687 | ||
2fa2fe9a | 8688 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
8689 | if (!(tmp & PFIT_ENABLE)) |
8690 | return; | |
2fa2fe9a | 8691 | |
06922821 | 8692 | /* Check whether the pfit is attached to our pipe. */ |
6315b5d3 | 8693 | if (INTEL_GEN(dev_priv) < 4) { |
2fa2fe9a DV |
8694 | if (crtc->pipe != PIPE_B) |
8695 | return; | |
2fa2fe9a DV |
8696 | } else { |
8697 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
8698 | return; | |
8699 | } | |
8700 | ||
06922821 | 8701 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a | 8702 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
2fa2fe9a DV |
8703 | } |
8704 | ||
acbec814 | 8705 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8706 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
8707 | { |
8708 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8709 | struct drm_i915_private *dev_priv = to_i915(dev); |
acbec814 | 8710 | int pipe = pipe_config->cpu_transcoder; |
9e2c8475 | 8711 | struct dpll clock; |
acbec814 | 8712 | u32 mdiv; |
662c6ecb | 8713 | int refclk = 100000; |
acbec814 | 8714 | |
b521973b VS |
8715 | /* In case of DSI, DPLL will not be used */ |
8716 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
f573de5a SK |
8717 | return; |
8718 | ||
a580516d | 8719 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 8720 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 8721 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
8722 | |
8723 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
8724 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
8725 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
8726 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
8727 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
8728 | ||
dccbea3b | 8729 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
8730 | } |
8731 | ||
5724dbd1 DL |
8732 | static void |
8733 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
8734 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
8735 | { |
8736 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8737 | struct drm_i915_private *dev_priv = to_i915(dev); |
1ad292b5 JB |
8738 | u32 val, base, offset; |
8739 | int pipe = crtc->pipe, plane = crtc->plane; | |
8740 | int fourcc, pixel_format; | |
6761dd31 | 8741 | unsigned int aligned_height; |
b113d5ee | 8742 | struct drm_framebuffer *fb; |
1b842c89 | 8743 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 8744 | |
42a7b088 DL |
8745 | val = I915_READ(DSPCNTR(plane)); |
8746 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8747 | return; | |
8748 | ||
d9806c9f | 8749 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8750 | if (!intel_fb) { |
1ad292b5 JB |
8751 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8752 | return; | |
8753 | } | |
8754 | ||
1b842c89 DL |
8755 | fb = &intel_fb->base; |
8756 | ||
6315b5d3 | 8757 | if (INTEL_GEN(dev_priv) >= 4) { |
18c5247e | 8758 | if (val & DISPPLANE_TILED) { |
49af449b | 8759 | plane_config->tiling = I915_TILING_X; |
bae781b2 | 8760 | fb->modifier = I915_FORMAT_MOD_X_TILED; |
18c5247e DV |
8761 | } |
8762 | } | |
1ad292b5 JB |
8763 | |
8764 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8765 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
8766 | fb->pixel_format = fourcc; |
8767 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 | 8768 | |
6315b5d3 | 8769 | if (INTEL_GEN(dev_priv) >= 4) { |
49af449b | 8770 | if (plane_config->tiling) |
1ad292b5 JB |
8771 | offset = I915_READ(DSPTILEOFF(plane)); |
8772 | else | |
8773 | offset = I915_READ(DSPLINOFF(plane)); | |
8774 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
8775 | } else { | |
8776 | base = I915_READ(DSPADDR(plane)); | |
8777 | } | |
8778 | plane_config->base = base; | |
8779 | ||
8780 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8781 | fb->width = ((val >> 16) & 0xfff) + 1; |
8782 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
8783 | |
8784 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8785 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 8786 | |
b113d5ee | 8787 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb | 8788 | fb->pixel_format, |
bae781b2 | 8789 | fb->modifier); |
1ad292b5 | 8790 | |
f37b5c2b | 8791 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 8792 | |
2844a921 DL |
8793 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8794 | pipe_name(pipe), plane, fb->width, fb->height, | |
8795 | fb->bits_per_pixel, base, fb->pitches[0], | |
8796 | plane_config->size); | |
1ad292b5 | 8797 | |
2d14030b | 8798 | plane_config->fb = intel_fb; |
1ad292b5 JB |
8799 | } |
8800 | ||
70b23a98 | 8801 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8802 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
8803 | { |
8804 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8805 | struct drm_i915_private *dev_priv = to_i915(dev); |
70b23a98 VS |
8806 | int pipe = pipe_config->cpu_transcoder; |
8807 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9e2c8475 | 8808 | struct dpll clock; |
0d7b6b11 | 8809 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
8810 | int refclk = 100000; |
8811 | ||
b521973b VS |
8812 | /* In case of DSI, DPLL will not be used */ |
8813 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
8814 | return; | |
8815 | ||
a580516d | 8816 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
8817 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
8818 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
8819 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
8820 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 8821 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 8822 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
8823 | |
8824 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
8825 | clock.m2 = (pll_dw0 & 0xff) << 22; |
8826 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
8827 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
8828 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
8829 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
8830 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
8831 | ||
dccbea3b | 8832 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
8833 | } |
8834 | ||
0e8ffe1b | 8835 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8836 | struct intel_crtc_state *pipe_config) |
0e8ffe1b | 8837 | { |
6315b5d3 | 8838 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1729050e | 8839 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 8840 | uint32_t tmp; |
1729050e | 8841 | bool ret; |
0e8ffe1b | 8842 | |
1729050e ID |
8843 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
8844 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 ID |
8845 | return false; |
8846 | ||
e143a21c | 8847 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 8848 | pipe_config->shared_dpll = NULL; |
eccb140b | 8849 | |
1729050e ID |
8850 | ret = false; |
8851 | ||
0e8ffe1b DV |
8852 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8853 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 8854 | goto out; |
0e8ffe1b | 8855 | |
9beb5fea TU |
8856 | if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
8857 | IS_CHERRYVIEW(dev_priv)) { | |
42571aef VS |
8858 | switch (tmp & PIPECONF_BPC_MASK) { |
8859 | case PIPECONF_6BPC: | |
8860 | pipe_config->pipe_bpp = 18; | |
8861 | break; | |
8862 | case PIPECONF_8BPC: | |
8863 | pipe_config->pipe_bpp = 24; | |
8864 | break; | |
8865 | case PIPECONF_10BPC: | |
8866 | pipe_config->pipe_bpp = 30; | |
8867 | break; | |
8868 | default: | |
8869 | break; | |
8870 | } | |
8871 | } | |
8872 | ||
920a14b2 | 8873 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
666a4537 | 8874 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
b5a9fa09 DV |
8875 | pipe_config->limited_color_range = true; |
8876 | ||
6315b5d3 | 8877 | if (INTEL_GEN(dev_priv) < 4) |
282740f7 VS |
8878 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; |
8879 | ||
1bd1bd80 | 8880 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 8881 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 8882 | |
2fa2fe9a DV |
8883 | i9xx_get_pfit_config(crtc, pipe_config); |
8884 | ||
6315b5d3 | 8885 | if (INTEL_GEN(dev_priv) >= 4) { |
c231775c | 8886 | /* No way to read it out on pipes B and C */ |
920a14b2 | 8887 | if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) |
c231775c VS |
8888 | tmp = dev_priv->chv_dpll_md[crtc->pipe]; |
8889 | else | |
8890 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
6c49f241 DV |
8891 | pipe_config->pixel_multiplier = |
8892 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
8893 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 8894 | pipe_config->dpll_hw_state.dpll_md = tmp; |
50a0bc90 TU |
8895 | } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || |
8896 | IS_G33(dev_priv)) { | |
6c49f241 DV |
8897 | tmp = I915_READ(DPLL(crtc->pipe)); |
8898 | pipe_config->pixel_multiplier = | |
8899 | ((tmp & SDVO_MULTIPLIER_MASK) | |
8900 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
8901 | } else { | |
8902 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
8903 | * port and will be fixed up in the encoder->get_config | |
8904 | * function. */ | |
8905 | pipe_config->pixel_multiplier = 1; | |
8906 | } | |
8bcc2795 | 8907 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
920a14b2 | 8908 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { |
1c4e0274 VS |
8909 | /* |
8910 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
8911 | * on 830. Filter it out here so that we don't | |
8912 | * report errors due to that. | |
8913 | */ | |
50a0bc90 | 8914 | if (IS_I830(dev_priv)) |
1c4e0274 VS |
8915 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; |
8916 | ||
8bcc2795 DV |
8917 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
8918 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
8919 | } else { |
8920 | /* Mask out read-only status bits. */ | |
8921 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
8922 | DPLL_PORTC_READY_MASK | | |
8923 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 8924 | } |
6c49f241 | 8925 | |
920a14b2 | 8926 | if (IS_CHERRYVIEW(dev_priv)) |
70b23a98 | 8927 | chv_crtc_clock_get(crtc, pipe_config); |
11a914c2 | 8928 | else if (IS_VALLEYVIEW(dev_priv)) |
acbec814 JB |
8929 | vlv_crtc_clock_get(crtc, pipe_config); |
8930 | else | |
8931 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 8932 | |
0f64614d VS |
8933 | /* |
8934 | * Normally the dotclock is filled in by the encoder .get_config() | |
8935 | * but in case the pipe is enabled w/o any ports we need a sane | |
8936 | * default. | |
8937 | */ | |
8938 | pipe_config->base.adjusted_mode.crtc_clock = | |
8939 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
8940 | ||
1729050e ID |
8941 | ret = true; |
8942 | ||
8943 | out: | |
8944 | intel_display_power_put(dev_priv, power_domain); | |
8945 | ||
8946 | return ret; | |
0e8ffe1b DV |
8947 | } |
8948 | ||
c39055b0 | 8949 | static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv) |
13d83a67 | 8950 | { |
13d83a67 | 8951 | struct intel_encoder *encoder; |
1c1a24d2 | 8952 | int i; |
74cfd7ac | 8953 | u32 val, final; |
13d83a67 | 8954 | bool has_lvds = false; |
199e5d79 | 8955 | bool has_cpu_edp = false; |
199e5d79 | 8956 | bool has_panel = false; |
99eb6a01 KP |
8957 | bool has_ck505 = false; |
8958 | bool can_ssc = false; | |
1c1a24d2 | 8959 | bool using_ssc_source = false; |
13d83a67 JB |
8960 | |
8961 | /* We need to take the global config into account */ | |
c39055b0 | 8962 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
199e5d79 KP |
8963 | switch (encoder->type) { |
8964 | case INTEL_OUTPUT_LVDS: | |
8965 | has_panel = true; | |
8966 | has_lvds = true; | |
8967 | break; | |
8968 | case INTEL_OUTPUT_EDP: | |
8969 | has_panel = true; | |
2de6905f | 8970 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
8971 | has_cpu_edp = true; |
8972 | break; | |
6847d71b PZ |
8973 | default: |
8974 | break; | |
13d83a67 JB |
8975 | } |
8976 | } | |
8977 | ||
6e266956 | 8978 | if (HAS_PCH_IBX(dev_priv)) { |
41aa3448 | 8979 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
8980 | can_ssc = has_ck505; |
8981 | } else { | |
8982 | has_ck505 = false; | |
8983 | can_ssc = true; | |
8984 | } | |
8985 | ||
1c1a24d2 L |
8986 | /* Check if any DPLLs are using the SSC source */ |
8987 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
8988 | u32 temp = I915_READ(PCH_DPLL(i)); | |
8989 | ||
8990 | if (!(temp & DPLL_VCO_ENABLE)) | |
8991 | continue; | |
8992 | ||
8993 | if ((temp & PLL_REF_INPUT_MASK) == | |
8994 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
8995 | using_ssc_source = true; | |
8996 | break; | |
8997 | } | |
8998 | } | |
8999 | ||
9000 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n", | |
9001 | has_panel, has_lvds, has_ck505, using_ssc_source); | |
13d83a67 JB |
9002 | |
9003 | /* Ironlake: try to setup display ref clock before DPLL | |
9004 | * enabling. This is only under driver's control after | |
9005 | * PCH B stepping, previous chipset stepping should be | |
9006 | * ignoring this setting. | |
9007 | */ | |
74cfd7ac CW |
9008 | val = I915_READ(PCH_DREF_CONTROL); |
9009 | ||
9010 | /* As we must carefully and slowly disable/enable each source in turn, | |
9011 | * compute the final state we want first and check if we need to | |
9012 | * make any changes at all. | |
9013 | */ | |
9014 | final = val; | |
9015 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
9016 | if (has_ck505) | |
9017 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
9018 | else | |
9019 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
9020 | ||
8c07eb68 | 9021 | final &= ~DREF_SSC_SOURCE_MASK; |
74cfd7ac | 9022 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
8c07eb68 | 9023 | final &= ~DREF_SSC1_ENABLE; |
74cfd7ac CW |
9024 | |
9025 | if (has_panel) { | |
9026 | final |= DREF_SSC_SOURCE_ENABLE; | |
9027 | ||
9028 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
9029 | final |= DREF_SSC1_ENABLE; | |
9030 | ||
9031 | if (has_cpu_edp) { | |
9032 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
9033 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
9034 | else | |
9035 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
9036 | } else | |
9037 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
1c1a24d2 L |
9038 | } else if (using_ssc_source) { |
9039 | final |= DREF_SSC_SOURCE_ENABLE; | |
9040 | final |= DREF_SSC1_ENABLE; | |
74cfd7ac CW |
9041 | } |
9042 | ||
9043 | if (final == val) | |
9044 | return; | |
9045 | ||
13d83a67 | 9046 | /* Always enable nonspread source */ |
74cfd7ac | 9047 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 9048 | |
99eb6a01 | 9049 | if (has_ck505) |
74cfd7ac | 9050 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 9051 | else |
74cfd7ac | 9052 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 9053 | |
199e5d79 | 9054 | if (has_panel) { |
74cfd7ac CW |
9055 | val &= ~DREF_SSC_SOURCE_MASK; |
9056 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 9057 | |
199e5d79 | 9058 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 9059 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 9060 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 9061 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 9062 | } else |
74cfd7ac | 9063 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
9064 | |
9065 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 9066 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
9067 | POSTING_READ(PCH_DREF_CONTROL); |
9068 | udelay(200); | |
9069 | ||
74cfd7ac | 9070 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
9071 | |
9072 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 9073 | if (has_cpu_edp) { |
99eb6a01 | 9074 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 9075 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 9076 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 9077 | } else |
74cfd7ac | 9078 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 9079 | } else |
74cfd7ac | 9080 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 9081 | |
74cfd7ac | 9082 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
9083 | POSTING_READ(PCH_DREF_CONTROL); |
9084 | udelay(200); | |
9085 | } else { | |
1c1a24d2 | 9086 | DRM_DEBUG_KMS("Disabling CPU source output\n"); |
199e5d79 | 9087 | |
74cfd7ac | 9088 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
9089 | |
9090 | /* Turn off CPU output */ | |
74cfd7ac | 9091 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 9092 | |
74cfd7ac | 9093 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
9094 | POSTING_READ(PCH_DREF_CONTROL); |
9095 | udelay(200); | |
9096 | ||
1c1a24d2 L |
9097 | if (!using_ssc_source) { |
9098 | DRM_DEBUG_KMS("Disabling SSC source\n"); | |
199e5d79 | 9099 | |
1c1a24d2 L |
9100 | /* Turn off the SSC source */ |
9101 | val &= ~DREF_SSC_SOURCE_MASK; | |
9102 | val |= DREF_SSC_SOURCE_DISABLE; | |
f165d283 | 9103 | |
1c1a24d2 L |
9104 | /* Turn off SSC1 */ |
9105 | val &= ~DREF_SSC1_ENABLE; | |
9106 | ||
9107 | I915_WRITE(PCH_DREF_CONTROL, val); | |
9108 | POSTING_READ(PCH_DREF_CONTROL); | |
9109 | udelay(200); | |
9110 | } | |
13d83a67 | 9111 | } |
74cfd7ac CW |
9112 | |
9113 | BUG_ON(val != final); | |
13d83a67 JB |
9114 | } |
9115 | ||
f31f2d55 | 9116 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 9117 | { |
f31f2d55 | 9118 | uint32_t tmp; |
dde86e2d | 9119 | |
0ff066a9 PZ |
9120 | tmp = I915_READ(SOUTH_CHICKEN2); |
9121 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
9122 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 9123 | |
cf3598c2 ID |
9124 | if (wait_for_us(I915_READ(SOUTH_CHICKEN2) & |
9125 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
0ff066a9 | 9126 | DRM_ERROR("FDI mPHY reset assert timeout\n"); |
dde86e2d | 9127 | |
0ff066a9 PZ |
9128 | tmp = I915_READ(SOUTH_CHICKEN2); |
9129 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
9130 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 9131 | |
cf3598c2 ID |
9132 | if (wait_for_us((I915_READ(SOUTH_CHICKEN2) & |
9133 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
0ff066a9 | 9134 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); |
f31f2d55 PZ |
9135 | } |
9136 | ||
9137 | /* WaMPhyProgramming:hsw */ | |
9138 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
9139 | { | |
9140 | uint32_t tmp; | |
dde86e2d PZ |
9141 | |
9142 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
9143 | tmp &= ~(0xFF << 24); | |
9144 | tmp |= (0x12 << 24); | |
9145 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
9146 | ||
dde86e2d PZ |
9147 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
9148 | tmp |= (1 << 11); | |
9149 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
9150 | ||
9151 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
9152 | tmp |= (1 << 11); | |
9153 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
9154 | ||
dde86e2d PZ |
9155 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
9156 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
9157 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
9158 | ||
9159 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
9160 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
9161 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
9162 | ||
0ff066a9 PZ |
9163 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
9164 | tmp &= ~(7 << 13); | |
9165 | tmp |= (5 << 13); | |
9166 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 9167 | |
0ff066a9 PZ |
9168 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
9169 | tmp &= ~(7 << 13); | |
9170 | tmp |= (5 << 13); | |
9171 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
9172 | |
9173 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
9174 | tmp &= ~0xFF; | |
9175 | tmp |= 0x1C; | |
9176 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
9177 | ||
9178 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
9179 | tmp &= ~0xFF; | |
9180 | tmp |= 0x1C; | |
9181 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
9182 | ||
9183 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
9184 | tmp &= ~(0xFF << 16); | |
9185 | tmp |= (0x1C << 16); | |
9186 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
9187 | ||
9188 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
9189 | tmp &= ~(0xFF << 16); | |
9190 | tmp |= (0x1C << 16); | |
9191 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
9192 | ||
0ff066a9 PZ |
9193 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
9194 | tmp |= (1 << 27); | |
9195 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 9196 | |
0ff066a9 PZ |
9197 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
9198 | tmp |= (1 << 27); | |
9199 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 9200 | |
0ff066a9 PZ |
9201 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
9202 | tmp &= ~(0xF << 28); | |
9203 | tmp |= (4 << 28); | |
9204 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 9205 | |
0ff066a9 PZ |
9206 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
9207 | tmp &= ~(0xF << 28); | |
9208 | tmp |= (4 << 28); | |
9209 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
9210 | } |
9211 | ||
2fa86a1f PZ |
9212 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
9213 | * Programming" based on the parameters passed: | |
9214 | * - Sequence to enable CLKOUT_DP | |
9215 | * - Sequence to enable CLKOUT_DP without spread | |
9216 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
9217 | */ | |
c39055b0 ACO |
9218 | static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv, |
9219 | bool with_spread, bool with_fdi) | |
f31f2d55 | 9220 | { |
2fa86a1f PZ |
9221 | uint32_t reg, tmp; |
9222 | ||
9223 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
9224 | with_spread = true; | |
4f8036a2 TU |
9225 | if (WARN(HAS_PCH_LPT_LP(dev_priv) && |
9226 | with_fdi, "LP PCH doesn't have FDI\n")) | |
2fa86a1f | 9227 | with_fdi = false; |
f31f2d55 | 9228 | |
a580516d | 9229 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
9230 | |
9231 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
9232 | tmp &= ~SBI_SSCCTL_DISABLE; | |
9233 | tmp |= SBI_SSCCTL_PATHALT; | |
9234 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
9235 | ||
9236 | udelay(24); | |
9237 | ||
2fa86a1f PZ |
9238 | if (with_spread) { |
9239 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
9240 | tmp &= ~SBI_SSCCTL_PATHALT; | |
9241 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 9242 | |
2fa86a1f PZ |
9243 | if (with_fdi) { |
9244 | lpt_reset_fdi_mphy(dev_priv); | |
9245 | lpt_program_fdi_mphy(dev_priv); | |
9246 | } | |
9247 | } | |
dde86e2d | 9248 | |
4f8036a2 | 9249 | reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
9250 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
9251 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
9252 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 9253 | |
a580516d | 9254 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
9255 | } |
9256 | ||
47701c3b | 9257 | /* Sequence to disable CLKOUT_DP */ |
c39055b0 | 9258 | static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv) |
47701c3b | 9259 | { |
47701c3b PZ |
9260 | uint32_t reg, tmp; |
9261 | ||
a580516d | 9262 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 9263 | |
4f8036a2 | 9264 | reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
9265 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
9266 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
9267 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
9268 | ||
9269 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
9270 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
9271 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
9272 | tmp |= SBI_SSCCTL_PATHALT; | |
9273 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
9274 | udelay(32); | |
9275 | } | |
9276 | tmp |= SBI_SSCCTL_DISABLE; | |
9277 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
9278 | } | |
9279 | ||
a580516d | 9280 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
9281 | } |
9282 | ||
f7be2c21 VS |
9283 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
9284 | ||
9285 | static const uint16_t sscdivintphase[] = { | |
9286 | [BEND_IDX( 50)] = 0x3B23, | |
9287 | [BEND_IDX( 45)] = 0x3B23, | |
9288 | [BEND_IDX( 40)] = 0x3C23, | |
9289 | [BEND_IDX( 35)] = 0x3C23, | |
9290 | [BEND_IDX( 30)] = 0x3D23, | |
9291 | [BEND_IDX( 25)] = 0x3D23, | |
9292 | [BEND_IDX( 20)] = 0x3E23, | |
9293 | [BEND_IDX( 15)] = 0x3E23, | |
9294 | [BEND_IDX( 10)] = 0x3F23, | |
9295 | [BEND_IDX( 5)] = 0x3F23, | |
9296 | [BEND_IDX( 0)] = 0x0025, | |
9297 | [BEND_IDX( -5)] = 0x0025, | |
9298 | [BEND_IDX(-10)] = 0x0125, | |
9299 | [BEND_IDX(-15)] = 0x0125, | |
9300 | [BEND_IDX(-20)] = 0x0225, | |
9301 | [BEND_IDX(-25)] = 0x0225, | |
9302 | [BEND_IDX(-30)] = 0x0325, | |
9303 | [BEND_IDX(-35)] = 0x0325, | |
9304 | [BEND_IDX(-40)] = 0x0425, | |
9305 | [BEND_IDX(-45)] = 0x0425, | |
9306 | [BEND_IDX(-50)] = 0x0525, | |
9307 | }; | |
9308 | ||
9309 | /* | |
9310 | * Bend CLKOUT_DP | |
9311 | * steps -50 to 50 inclusive, in steps of 5 | |
9312 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) | |
9313 | * change in clock period = -(steps / 10) * 5.787 ps | |
9314 | */ | |
9315 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) | |
9316 | { | |
9317 | uint32_t tmp; | |
9318 | int idx = BEND_IDX(steps); | |
9319 | ||
9320 | if (WARN_ON(steps % 5 != 0)) | |
9321 | return; | |
9322 | ||
9323 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) | |
9324 | return; | |
9325 | ||
9326 | mutex_lock(&dev_priv->sb_lock); | |
9327 | ||
9328 | if (steps % 10 != 0) | |
9329 | tmp = 0xAAAAAAAB; | |
9330 | else | |
9331 | tmp = 0x00000000; | |
9332 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); | |
9333 | ||
9334 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); | |
9335 | tmp &= 0xffff0000; | |
9336 | tmp |= sscdivintphase[idx]; | |
9337 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); | |
9338 | ||
9339 | mutex_unlock(&dev_priv->sb_lock); | |
9340 | } | |
9341 | ||
9342 | #undef BEND_IDX | |
9343 | ||
c39055b0 | 9344 | static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv) |
bf8fa3d3 | 9345 | { |
bf8fa3d3 PZ |
9346 | struct intel_encoder *encoder; |
9347 | bool has_vga = false; | |
9348 | ||
c39055b0 | 9349 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
bf8fa3d3 PZ |
9350 | switch (encoder->type) { |
9351 | case INTEL_OUTPUT_ANALOG: | |
9352 | has_vga = true; | |
9353 | break; | |
6847d71b PZ |
9354 | default: |
9355 | break; | |
bf8fa3d3 PZ |
9356 | } |
9357 | } | |
9358 | ||
f7be2c21 | 9359 | if (has_vga) { |
c39055b0 ACO |
9360 | lpt_bend_clkout_dp(dev_priv, 0); |
9361 | lpt_enable_clkout_dp(dev_priv, true, true); | |
f7be2c21 | 9362 | } else { |
c39055b0 | 9363 | lpt_disable_clkout_dp(dev_priv); |
f7be2c21 | 9364 | } |
bf8fa3d3 PZ |
9365 | } |
9366 | ||
dde86e2d PZ |
9367 | /* |
9368 | * Initialize reference clocks when the driver loads | |
9369 | */ | |
c39055b0 | 9370 | void intel_init_pch_refclk(struct drm_i915_private *dev_priv) |
dde86e2d | 9371 | { |
6e266956 | 9372 | if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) |
c39055b0 | 9373 | ironlake_init_pch_refclk(dev_priv); |
6e266956 | 9374 | else if (HAS_PCH_LPT(dev_priv)) |
c39055b0 | 9375 | lpt_init_pch_refclk(dev_priv); |
dde86e2d PZ |
9376 | } |
9377 | ||
6ff93609 | 9378 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 9379 | { |
fac5e23e | 9380 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
79e53945 JB |
9381 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9382 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
9383 | uint32_t val; |
9384 | ||
78114071 | 9385 | val = 0; |
c8203565 | 9386 | |
6e3c9717 | 9387 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 9388 | case 18: |
dfd07d72 | 9389 | val |= PIPECONF_6BPC; |
c8203565 PZ |
9390 | break; |
9391 | case 24: | |
dfd07d72 | 9392 | val |= PIPECONF_8BPC; |
c8203565 PZ |
9393 | break; |
9394 | case 30: | |
dfd07d72 | 9395 | val |= PIPECONF_10BPC; |
c8203565 PZ |
9396 | break; |
9397 | case 36: | |
dfd07d72 | 9398 | val |= PIPECONF_12BPC; |
c8203565 PZ |
9399 | break; |
9400 | default: | |
cc769b62 PZ |
9401 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
9402 | BUG(); | |
c8203565 PZ |
9403 | } |
9404 | ||
6e3c9717 | 9405 | if (intel_crtc->config->dither) |
c8203565 PZ |
9406 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
9407 | ||
6e3c9717 | 9408 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
9409 | val |= PIPECONF_INTERLACED_ILK; |
9410 | else | |
9411 | val |= PIPECONF_PROGRESSIVE; | |
9412 | ||
6e3c9717 | 9413 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 9414 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 9415 | |
c8203565 PZ |
9416 | I915_WRITE(PIPECONF(pipe), val); |
9417 | POSTING_READ(PIPECONF(pipe)); | |
9418 | } | |
9419 | ||
6ff93609 | 9420 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 9421 | { |
fac5e23e | 9422 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
ee2b0b38 | 9423 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 9424 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
391bf048 | 9425 | u32 val = 0; |
ee2b0b38 | 9426 | |
391bf048 | 9427 | if (IS_HASWELL(dev_priv) && intel_crtc->config->dither) |
ee2b0b38 PZ |
9428 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
9429 | ||
6e3c9717 | 9430 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
9431 | val |= PIPECONF_INTERLACED_ILK; |
9432 | else | |
9433 | val |= PIPECONF_PROGRESSIVE; | |
9434 | ||
702e7a56 PZ |
9435 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
9436 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
391bf048 JN |
9437 | } |
9438 | ||
391bf048 JN |
9439 | static void haswell_set_pipemisc(struct drm_crtc *crtc) |
9440 | { | |
fac5e23e | 9441 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
391bf048 | 9442 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 9443 | |
391bf048 JN |
9444 | if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) { |
9445 | u32 val = 0; | |
756f85cf | 9446 | |
6e3c9717 | 9447 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
9448 | case 18: |
9449 | val |= PIPEMISC_DITHER_6_BPC; | |
9450 | break; | |
9451 | case 24: | |
9452 | val |= PIPEMISC_DITHER_8_BPC; | |
9453 | break; | |
9454 | case 30: | |
9455 | val |= PIPEMISC_DITHER_10_BPC; | |
9456 | break; | |
9457 | case 36: | |
9458 | val |= PIPEMISC_DITHER_12_BPC; | |
9459 | break; | |
9460 | default: | |
9461 | /* Case prevented by pipe_config_set_bpp. */ | |
9462 | BUG(); | |
9463 | } | |
9464 | ||
6e3c9717 | 9465 | if (intel_crtc->config->dither) |
756f85cf PZ |
9466 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
9467 | ||
391bf048 | 9468 | I915_WRITE(PIPEMISC(intel_crtc->pipe), val); |
756f85cf | 9469 | } |
ee2b0b38 PZ |
9470 | } |
9471 | ||
d4b1931c PZ |
9472 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
9473 | { | |
9474 | /* | |
9475 | * Account for spread spectrum to avoid | |
9476 | * oversubscribing the link. Max center spread | |
9477 | * is 2.5%; use 5% for safety's sake. | |
9478 | */ | |
9479 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 9480 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
9481 | } |
9482 | ||
7429e9d4 | 9483 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 9484 | { |
7429e9d4 | 9485 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
9486 | } |
9487 | ||
b75ca6f6 ACO |
9488 | static void ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
9489 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 9490 | struct dpll *reduced_clock) |
79e53945 | 9491 | { |
de13a2e3 | 9492 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 | 9493 | struct drm_device *dev = crtc->dev; |
fac5e23e | 9494 | struct drm_i915_private *dev_priv = to_i915(dev); |
b75ca6f6 | 9495 | u32 dpll, fp, fp2; |
3d6e9ee0 | 9496 | int factor; |
79e53945 | 9497 | |
c1858123 | 9498 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 | 9499 | factor = 21; |
3d6e9ee0 | 9500 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
8febb297 | 9501 | if ((intel_panel_use_ssc(dev_priv) && |
e91e941b | 9502 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
6e266956 | 9503 | (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev))) |
8febb297 | 9504 | factor = 25; |
190f68c5 | 9505 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 9506 | factor = 20; |
c1858123 | 9507 | |
b75ca6f6 ACO |
9508 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
9509 | ||
190f68c5 | 9510 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
b75ca6f6 ACO |
9511 | fp |= FP_CB_TUNE; |
9512 | ||
9513 | if (reduced_clock) { | |
9514 | fp2 = i9xx_dpll_compute_fp(reduced_clock); | |
2c07245f | 9515 | |
b75ca6f6 ACO |
9516 | if (reduced_clock->m < factor * reduced_clock->n) |
9517 | fp2 |= FP_CB_TUNE; | |
9518 | } else { | |
9519 | fp2 = fp; | |
9520 | } | |
9a7c7890 | 9521 | |
5eddb70b | 9522 | dpll = 0; |
2c07245f | 9523 | |
3d6e9ee0 | 9524 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a07d6787 EA |
9525 | dpll |= DPLLB_MODE_LVDS; |
9526 | else | |
9527 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 9528 | |
190f68c5 | 9529 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 9530 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f | 9531 | |
3d6e9ee0 VS |
9532 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
9533 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 9534 | dpll |= DPLL_SDVO_HIGH_SPEED; |
3d6e9ee0 | 9535 | |
37a5650b | 9536 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 9537 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 9538 | |
7d7f8633 VS |
9539 | /* |
9540 | * The high speed IO clock is only really required for | |
9541 | * SDVO/HDMI/DP, but we also enable it for CRT to make it | |
9542 | * possible to share the DPLL between CRT and HDMI. Enabling | |
9543 | * the clock needlessly does no real harm, except use up a | |
9544 | * bit of power potentially. | |
9545 | * | |
9546 | * We'll limit this to IVB with 3 pipes, since it has only two | |
9547 | * DPLLs and so DPLL sharing is the only way to get three pipes | |
9548 | * driving PCH ports at the same time. On SNB we could do this, | |
9549 | * and potentially avoid enabling the second DPLL, but it's not | |
9550 | * clear if it''s a win or loss power wise. No point in doing | |
9551 | * this on ILK at all since it has a fixed DPLL<->pipe mapping. | |
9552 | */ | |
9553 | if (INTEL_INFO(dev_priv)->num_pipes == 3 && | |
9554 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) | |
9555 | dpll |= DPLL_SDVO_HIGH_SPEED; | |
9556 | ||
a07d6787 | 9557 | /* compute bitmask from p1 value */ |
190f68c5 | 9558 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 9559 | /* also FPA1 */ |
190f68c5 | 9560 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 9561 | |
190f68c5 | 9562 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
9563 | case 5: |
9564 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
9565 | break; | |
9566 | case 7: | |
9567 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
9568 | break; | |
9569 | case 10: | |
9570 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
9571 | break; | |
9572 | case 14: | |
9573 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
9574 | break; | |
79e53945 JB |
9575 | } |
9576 | ||
3d6e9ee0 VS |
9577 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
9578 | intel_panel_use_ssc(dev_priv)) | |
43565a06 | 9579 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
9580 | else |
9581 | dpll |= PLL_REF_INPUT_DREFCLK; | |
9582 | ||
b75ca6f6 ACO |
9583 | dpll |= DPLL_VCO_ENABLE; |
9584 | ||
9585 | crtc_state->dpll_hw_state.dpll = dpll; | |
9586 | crtc_state->dpll_hw_state.fp0 = fp; | |
9587 | crtc_state->dpll_hw_state.fp1 = fp2; | |
de13a2e3 PZ |
9588 | } |
9589 | ||
190f68c5 ACO |
9590 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
9591 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 9592 | { |
997c030c | 9593 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 9594 | struct drm_i915_private *dev_priv = to_i915(dev); |
9e2c8475 | 9595 | struct dpll reduced_clock; |
7ed9f894 | 9596 | bool has_reduced_clock = false; |
e2b78267 | 9597 | struct intel_shared_dpll *pll; |
1b6f4958 | 9598 | const struct intel_limit *limit; |
997c030c | 9599 | int refclk = 120000; |
de13a2e3 | 9600 | |
dd3cd74a ACO |
9601 | memset(&crtc_state->dpll_hw_state, 0, |
9602 | sizeof(crtc_state->dpll_hw_state)); | |
9603 | ||
ded220e2 ACO |
9604 | crtc->lowfreq_avail = false; |
9605 | ||
9606 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ | |
9607 | if (!crtc_state->has_pch_encoder) | |
9608 | return 0; | |
79e53945 | 9609 | |
2d84d2b3 | 9610 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
997c030c ACO |
9611 | if (intel_panel_use_ssc(dev_priv)) { |
9612 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", | |
9613 | dev_priv->vbt.lvds_ssc_freq); | |
9614 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
9615 | } | |
9616 | ||
9617 | if (intel_is_dual_link_lvds(dev)) { | |
9618 | if (refclk == 100000) | |
9619 | limit = &intel_limits_ironlake_dual_lvds_100m; | |
9620 | else | |
9621 | limit = &intel_limits_ironlake_dual_lvds; | |
9622 | } else { | |
9623 | if (refclk == 100000) | |
9624 | limit = &intel_limits_ironlake_single_lvds_100m; | |
9625 | else | |
9626 | limit = &intel_limits_ironlake_single_lvds; | |
9627 | } | |
9628 | } else { | |
9629 | limit = &intel_limits_ironlake_dac; | |
9630 | } | |
9631 | ||
364ee29d | 9632 | if (!crtc_state->clock_set && |
997c030c ACO |
9633 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
9634 | refclk, NULL, &crtc_state->dpll)) { | |
364ee29d ACO |
9635 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
9636 | return -EINVAL; | |
f47709a9 | 9637 | } |
79e53945 | 9638 | |
b75ca6f6 ACO |
9639 | ironlake_compute_dpll(crtc, crtc_state, |
9640 | has_reduced_clock ? &reduced_clock : NULL); | |
66e985c0 | 9641 | |
ded220e2 ACO |
9642 | pll = intel_get_shared_dpll(crtc, crtc_state, NULL); |
9643 | if (pll == NULL) { | |
9644 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
9645 | pipe_name(crtc->pipe)); | |
9646 | return -EINVAL; | |
3fb37703 | 9647 | } |
79e53945 | 9648 | |
2d84d2b3 | 9649 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ded220e2 | 9650 | has_reduced_clock) |
c7653199 | 9651 | crtc->lowfreq_avail = true; |
e2b78267 | 9652 | |
c8f7a0db | 9653 | return 0; |
79e53945 JB |
9654 | } |
9655 | ||
eb14cb74 VS |
9656 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
9657 | struct intel_link_m_n *m_n) | |
9658 | { | |
9659 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9660 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb14cb74 VS |
9661 | enum pipe pipe = crtc->pipe; |
9662 | ||
9663 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
9664 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
9665 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9666 | & ~TU_SIZE_MASK; | |
9667 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
9668 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9669 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9670 | } | |
9671 | ||
9672 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
9673 | enum transcoder transcoder, | |
b95af8be VK |
9674 | struct intel_link_m_n *m_n, |
9675 | struct intel_link_m_n *m2_n2) | |
72419203 | 9676 | { |
6315b5d3 | 9677 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
eb14cb74 | 9678 | enum pipe pipe = crtc->pipe; |
72419203 | 9679 | |
6315b5d3 | 9680 | if (INTEL_GEN(dev_priv) >= 5) { |
eb14cb74 VS |
9681 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); |
9682 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
9683 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
9684 | & ~TU_SIZE_MASK; | |
9685 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
9686 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
9687 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
9688 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
9689 | * gen < 8) and if DRRS is supported (to make sure the | |
9690 | * registers are not unnecessarily read). | |
9691 | */ | |
6315b5d3 | 9692 | if (m2_n2 && INTEL_GEN(dev_priv) < 8 && |
6e3c9717 | 9693 | crtc->config->has_drrs) { |
b95af8be VK |
9694 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
9695 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
9696 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
9697 | & ~TU_SIZE_MASK; | |
9698 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
9699 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
9700 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9701 | } | |
eb14cb74 VS |
9702 | } else { |
9703 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
9704 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
9705 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9706 | & ~TU_SIZE_MASK; | |
9707 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
9708 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9709 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9710 | } | |
9711 | } | |
9712 | ||
9713 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 9714 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 9715 | { |
681a8504 | 9716 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
9717 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
9718 | else | |
9719 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
9720 | &pipe_config->dp_m_n, |
9721 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 9722 | } |
72419203 | 9723 | |
eb14cb74 | 9724 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 9725 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
9726 | { |
9727 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 9728 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
9729 | } |
9730 | ||
bd2e244f | 9731 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9732 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
9733 | { |
9734 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9735 | struct drm_i915_private *dev_priv = to_i915(dev); |
a1b2278e CK |
9736 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
9737 | uint32_t ps_ctrl = 0; | |
9738 | int id = -1; | |
9739 | int i; | |
bd2e244f | 9740 | |
a1b2278e CK |
9741 | /* find scaler attached to this pipe */ |
9742 | for (i = 0; i < crtc->num_scalers; i++) { | |
9743 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
9744 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
9745 | id = i; | |
9746 | pipe_config->pch_pfit.enabled = true; | |
9747 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
9748 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
9749 | break; | |
9750 | } | |
9751 | } | |
bd2e244f | 9752 | |
a1b2278e CK |
9753 | scaler_state->scaler_id = id; |
9754 | if (id >= 0) { | |
9755 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
9756 | } else { | |
9757 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
9758 | } |
9759 | } | |
9760 | ||
5724dbd1 DL |
9761 | static void |
9762 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
9763 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
9764 | { |
9765 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9766 | struct drm_i915_private *dev_priv = to_i915(dev); |
40f46283 | 9767 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
9768 | int pipe = crtc->pipe; |
9769 | int fourcc, pixel_format; | |
6761dd31 | 9770 | unsigned int aligned_height; |
bc8d7dff | 9771 | struct drm_framebuffer *fb; |
1b842c89 | 9772 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 9773 | |
d9806c9f | 9774 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9775 | if (!intel_fb) { |
bc8d7dff DL |
9776 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9777 | return; | |
9778 | } | |
9779 | ||
1b842c89 DL |
9780 | fb = &intel_fb->base; |
9781 | ||
bc8d7dff | 9782 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
9783 | if (!(val & PLANE_CTL_ENABLE)) |
9784 | goto error; | |
9785 | ||
bc8d7dff DL |
9786 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
9787 | fourcc = skl_format_to_fourcc(pixel_format, | |
9788 | val & PLANE_CTL_ORDER_RGBX, | |
9789 | val & PLANE_CTL_ALPHA_MASK); | |
9790 | fb->pixel_format = fourcc; | |
9791 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
9792 | ||
40f46283 DL |
9793 | tiling = val & PLANE_CTL_TILED_MASK; |
9794 | switch (tiling) { | |
9795 | case PLANE_CTL_TILED_LINEAR: | |
bae781b2 | 9796 | fb->modifier = DRM_FORMAT_MOD_NONE; |
40f46283 DL |
9797 | break; |
9798 | case PLANE_CTL_TILED_X: | |
9799 | plane_config->tiling = I915_TILING_X; | |
bae781b2 | 9800 | fb->modifier = I915_FORMAT_MOD_X_TILED; |
40f46283 DL |
9801 | break; |
9802 | case PLANE_CTL_TILED_Y: | |
bae781b2 | 9803 | fb->modifier = I915_FORMAT_MOD_Y_TILED; |
40f46283 DL |
9804 | break; |
9805 | case PLANE_CTL_TILED_YF: | |
bae781b2 | 9806 | fb->modifier = I915_FORMAT_MOD_Yf_TILED; |
40f46283 DL |
9807 | break; |
9808 | default: | |
9809 | MISSING_CASE(tiling); | |
9810 | goto error; | |
9811 | } | |
9812 | ||
bc8d7dff DL |
9813 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
9814 | plane_config->base = base; | |
9815 | ||
9816 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
9817 | ||
9818 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
9819 | fb->height = ((val >> 16) & 0xfff) + 1; | |
9820 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
9821 | ||
9822 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
bae781b2 | 9823 | stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier, |
40f46283 | 9824 | fb->pixel_format); |
bc8d7dff DL |
9825 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
9826 | ||
9827 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb | 9828 | fb->pixel_format, |
bae781b2 | 9829 | fb->modifier); |
bc8d7dff | 9830 | |
f37b5c2b | 9831 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
9832 | |
9833 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
9834 | pipe_name(pipe), fb->width, fb->height, | |
9835 | fb->bits_per_pixel, base, fb->pitches[0], | |
9836 | plane_config->size); | |
9837 | ||
2d14030b | 9838 | plane_config->fb = intel_fb; |
bc8d7dff DL |
9839 | return; |
9840 | ||
9841 | error: | |
d1a3a036 | 9842 | kfree(intel_fb); |
bc8d7dff DL |
9843 | } |
9844 | ||
2fa2fe9a | 9845 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9846 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
9847 | { |
9848 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9849 | struct drm_i915_private *dev_priv = to_i915(dev); |
2fa2fe9a DV |
9850 | uint32_t tmp; |
9851 | ||
9852 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
9853 | ||
9854 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 9855 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
9856 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
9857 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
9858 | |
9859 | /* We currently do not free assignements of panel fitters on | |
9860 | * ivb/hsw (since we don't use the higher upscaling modes which | |
9861 | * differentiates them) so just WARN about this case for now. */ | |
5db94019 | 9862 | if (IS_GEN7(dev_priv)) { |
cb8b2a30 DV |
9863 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != |
9864 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
9865 | } | |
2fa2fe9a | 9866 | } |
79e53945 JB |
9867 | } |
9868 | ||
5724dbd1 DL |
9869 | static void |
9870 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
9871 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
9872 | { |
9873 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9874 | struct drm_i915_private *dev_priv = to_i915(dev); |
4c6baa59 | 9875 | u32 val, base, offset; |
aeee5a49 | 9876 | int pipe = crtc->pipe; |
4c6baa59 | 9877 | int fourcc, pixel_format; |
6761dd31 | 9878 | unsigned int aligned_height; |
b113d5ee | 9879 | struct drm_framebuffer *fb; |
1b842c89 | 9880 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 9881 | |
42a7b088 DL |
9882 | val = I915_READ(DSPCNTR(pipe)); |
9883 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
9884 | return; | |
9885 | ||
d9806c9f | 9886 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9887 | if (!intel_fb) { |
4c6baa59 JB |
9888 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9889 | return; | |
9890 | } | |
9891 | ||
1b842c89 DL |
9892 | fb = &intel_fb->base; |
9893 | ||
6315b5d3 | 9894 | if (INTEL_GEN(dev_priv) >= 4) { |
18c5247e | 9895 | if (val & DISPPLANE_TILED) { |
49af449b | 9896 | plane_config->tiling = I915_TILING_X; |
bae781b2 | 9897 | fb->modifier = I915_FORMAT_MOD_X_TILED; |
18c5247e DV |
9898 | } |
9899 | } | |
4c6baa59 JB |
9900 | |
9901 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 9902 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
9903 | fb->pixel_format = fourcc; |
9904 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 9905 | |
aeee5a49 | 9906 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
8652744b | 9907 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
aeee5a49 | 9908 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 9909 | } else { |
49af449b | 9910 | if (plane_config->tiling) |
aeee5a49 | 9911 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 9912 | else |
aeee5a49 | 9913 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
9914 | } |
9915 | plane_config->base = base; | |
9916 | ||
9917 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
9918 | fb->width = ((val >> 16) & 0xfff) + 1; |
9919 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
9920 | |
9921 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 9922 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 9923 | |
b113d5ee | 9924 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb | 9925 | fb->pixel_format, |
bae781b2 | 9926 | fb->modifier); |
4c6baa59 | 9927 | |
f37b5c2b | 9928 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 9929 | |
2844a921 DL |
9930 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
9931 | pipe_name(pipe), fb->width, fb->height, | |
9932 | fb->bits_per_pixel, base, fb->pitches[0], | |
9933 | plane_config->size); | |
b113d5ee | 9934 | |
2d14030b | 9935 | plane_config->fb = intel_fb; |
4c6baa59 JB |
9936 | } |
9937 | ||
0e8ffe1b | 9938 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9939 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9940 | { |
9941 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9942 | struct drm_i915_private *dev_priv = to_i915(dev); |
1729050e | 9943 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 9944 | uint32_t tmp; |
1729050e | 9945 | bool ret; |
0e8ffe1b | 9946 | |
1729050e ID |
9947 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
9948 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
930e8c9e PZ |
9949 | return false; |
9950 | ||
e143a21c | 9951 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 9952 | pipe_config->shared_dpll = NULL; |
eccb140b | 9953 | |
1729050e | 9954 | ret = false; |
0e8ffe1b DV |
9955 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
9956 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 9957 | goto out; |
0e8ffe1b | 9958 | |
42571aef VS |
9959 | switch (tmp & PIPECONF_BPC_MASK) { |
9960 | case PIPECONF_6BPC: | |
9961 | pipe_config->pipe_bpp = 18; | |
9962 | break; | |
9963 | case PIPECONF_8BPC: | |
9964 | pipe_config->pipe_bpp = 24; | |
9965 | break; | |
9966 | case PIPECONF_10BPC: | |
9967 | pipe_config->pipe_bpp = 30; | |
9968 | break; | |
9969 | case PIPECONF_12BPC: | |
9970 | pipe_config->pipe_bpp = 36; | |
9971 | break; | |
9972 | default: | |
9973 | break; | |
9974 | } | |
9975 | ||
b5a9fa09 DV |
9976 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
9977 | pipe_config->limited_color_range = true; | |
9978 | ||
ab9412ba | 9979 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 | 9980 | struct intel_shared_dpll *pll; |
8106ddbd | 9981 | enum intel_dpll_id pll_id; |
66e985c0 | 9982 | |
88adfff1 DV |
9983 | pipe_config->has_pch_encoder = true; |
9984 | ||
627eb5a3 DV |
9985 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
9986 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9987 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
9988 | |
9989 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 9990 | |
2d1fe073 | 9991 | if (HAS_PCH_IBX(dev_priv)) { |
d9a7bc67 ID |
9992 | /* |
9993 | * The pipe->pch transcoder and pch transcoder->pll | |
9994 | * mapping is fixed. | |
9995 | */ | |
8106ddbd | 9996 | pll_id = (enum intel_dpll_id) crtc->pipe; |
c0d43d62 DV |
9997 | } else { |
9998 | tmp = I915_READ(PCH_DPLL_SEL); | |
9999 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
8106ddbd | 10000 | pll_id = DPLL_ID_PCH_PLL_B; |
c0d43d62 | 10001 | else |
8106ddbd | 10002 | pll_id= DPLL_ID_PCH_PLL_A; |
c0d43d62 | 10003 | } |
66e985c0 | 10004 | |
8106ddbd ACO |
10005 | pipe_config->shared_dpll = |
10006 | intel_get_shared_dpll_by_id(dev_priv, pll_id); | |
10007 | pll = pipe_config->shared_dpll; | |
66e985c0 | 10008 | |
2edd6443 ACO |
10009 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
10010 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
10011 | |
10012 | tmp = pipe_config->dpll_hw_state.dpll; | |
10013 | pipe_config->pixel_multiplier = | |
10014 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
10015 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
10016 | |
10017 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
10018 | } else { |
10019 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
10020 | } |
10021 | ||
1bd1bd80 | 10022 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 10023 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 10024 | |
2fa2fe9a DV |
10025 | ironlake_get_pfit_config(crtc, pipe_config); |
10026 | ||
1729050e ID |
10027 | ret = true; |
10028 | ||
10029 | out: | |
10030 | intel_display_power_put(dev_priv, power_domain); | |
10031 | ||
10032 | return ret; | |
0e8ffe1b DV |
10033 | } |
10034 | ||
be256dc7 PZ |
10035 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
10036 | { | |
91c8a326 | 10037 | struct drm_device *dev = &dev_priv->drm; |
be256dc7 | 10038 | struct intel_crtc *crtc; |
be256dc7 | 10039 | |
d3fcc808 | 10040 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 10041 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
10042 | pipe_name(crtc->pipe)); |
10043 | ||
e2c719b7 RC |
10044 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
10045 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
01403de3 VS |
10046 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
10047 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
44cb734c | 10048 | I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n"); |
e2c719b7 | 10049 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, |
be256dc7 | 10050 | "CPU PWM1 enabled\n"); |
772c2a51 | 10051 | if (IS_HASWELL(dev_priv)) |
e2c719b7 | 10052 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 10053 | "CPU PWM2 enabled\n"); |
e2c719b7 | 10054 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 10055 | "PCH PWM1 enabled\n"); |
e2c719b7 | 10056 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 10057 | "Utility pin enabled\n"); |
e2c719b7 | 10058 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 10059 | |
9926ada1 PZ |
10060 | /* |
10061 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
10062 | * interrupts remain enabled. We used to check for that, but since it's | |
10063 | * gen-specific and since we only disable LCPLL after we fully disable | |
10064 | * the interrupts, the check below should be enough. | |
10065 | */ | |
e2c719b7 | 10066 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
10067 | } |
10068 | ||
9ccd5aeb PZ |
10069 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
10070 | { | |
772c2a51 | 10071 | if (IS_HASWELL(dev_priv)) |
9ccd5aeb PZ |
10072 | return I915_READ(D_COMP_HSW); |
10073 | else | |
10074 | return I915_READ(D_COMP_BDW); | |
10075 | } | |
10076 | ||
3c4c9b81 PZ |
10077 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
10078 | { | |
772c2a51 | 10079 | if (IS_HASWELL(dev_priv)) { |
3c4c9b81 PZ |
10080 | mutex_lock(&dev_priv->rps.hw_lock); |
10081 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
10082 | val)) | |
79cf219a | 10083 | DRM_DEBUG_KMS("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
10084 | mutex_unlock(&dev_priv->rps.hw_lock); |
10085 | } else { | |
9ccd5aeb PZ |
10086 | I915_WRITE(D_COMP_BDW, val); |
10087 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 10088 | } |
be256dc7 PZ |
10089 | } |
10090 | ||
10091 | /* | |
10092 | * This function implements pieces of two sequences from BSpec: | |
10093 | * - Sequence for display software to disable LCPLL | |
10094 | * - Sequence for display software to allow package C8+ | |
10095 | * The steps implemented here are just the steps that actually touch the LCPLL | |
10096 | * register. Callers should take care of disabling all the display engine | |
10097 | * functions, doing the mode unset, fixing interrupts, etc. | |
10098 | */ | |
6ff58d53 PZ |
10099 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
10100 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
10101 | { |
10102 | uint32_t val; | |
10103 | ||
10104 | assert_can_disable_lcpll(dev_priv); | |
10105 | ||
10106 | val = I915_READ(LCPLL_CTL); | |
10107 | ||
10108 | if (switch_to_fclk) { | |
10109 | val |= LCPLL_CD_SOURCE_FCLK; | |
10110 | I915_WRITE(LCPLL_CTL, val); | |
10111 | ||
f53dd63f ID |
10112 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
10113 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
be256dc7 PZ |
10114 | DRM_ERROR("Switching to FCLK failed\n"); |
10115 | ||
10116 | val = I915_READ(LCPLL_CTL); | |
10117 | } | |
10118 | ||
10119 | val |= LCPLL_PLL_DISABLE; | |
10120 | I915_WRITE(LCPLL_CTL, val); | |
10121 | POSTING_READ(LCPLL_CTL); | |
10122 | ||
24d8441d | 10123 | if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1)) |
be256dc7 PZ |
10124 | DRM_ERROR("LCPLL still locked\n"); |
10125 | ||
9ccd5aeb | 10126 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 10127 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 10128 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
10129 | ndelay(100); |
10130 | ||
9ccd5aeb PZ |
10131 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
10132 | 1)) | |
be256dc7 PZ |
10133 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
10134 | ||
10135 | if (allow_power_down) { | |
10136 | val = I915_READ(LCPLL_CTL); | |
10137 | val |= LCPLL_POWER_DOWN_ALLOW; | |
10138 | I915_WRITE(LCPLL_CTL, val); | |
10139 | POSTING_READ(LCPLL_CTL); | |
10140 | } | |
10141 | } | |
10142 | ||
10143 | /* | |
10144 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
10145 | * source. | |
10146 | */ | |
6ff58d53 | 10147 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
10148 | { |
10149 | uint32_t val; | |
10150 | ||
10151 | val = I915_READ(LCPLL_CTL); | |
10152 | ||
10153 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
10154 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
10155 | return; | |
10156 | ||
a8a8bd54 PZ |
10157 | /* |
10158 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
10159 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 10160 | */ |
59bad947 | 10161 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 10162 | |
be256dc7 PZ |
10163 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
10164 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
10165 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 10166 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
10167 | } |
10168 | ||
9ccd5aeb | 10169 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
10170 | val |= D_COMP_COMP_FORCE; |
10171 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 10172 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
10173 | |
10174 | val = I915_READ(LCPLL_CTL); | |
10175 | val &= ~LCPLL_PLL_DISABLE; | |
10176 | I915_WRITE(LCPLL_CTL, val); | |
10177 | ||
93220c08 CW |
10178 | if (intel_wait_for_register(dev_priv, |
10179 | LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, | |
10180 | 5)) | |
be256dc7 PZ |
10181 | DRM_ERROR("LCPLL not locked yet\n"); |
10182 | ||
10183 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
10184 | val = I915_READ(LCPLL_CTL); | |
10185 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
10186 | I915_WRITE(LCPLL_CTL, val); | |
10187 | ||
f53dd63f ID |
10188 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
10189 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
be256dc7 PZ |
10190 | DRM_ERROR("Switching back to LCPLL failed\n"); |
10191 | } | |
215733fa | 10192 | |
59bad947 | 10193 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
4c75b940 | 10194 | intel_update_cdclk(dev_priv); |
be256dc7 PZ |
10195 | } |
10196 | ||
765dab67 PZ |
10197 | /* |
10198 | * Package states C8 and deeper are really deep PC states that can only be | |
10199 | * reached when all the devices on the system allow it, so even if the graphics | |
10200 | * device allows PC8+, it doesn't mean the system will actually get to these | |
10201 | * states. Our driver only allows PC8+ when going into runtime PM. | |
10202 | * | |
10203 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
10204 | * well is disabled and most interrupts are disabled, and these are also | |
10205 | * requirements for runtime PM. When these conditions are met, we manually do | |
10206 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
10207 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
10208 | * hang the machine. | |
10209 | * | |
10210 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
10211 | * the state of some registers, so when we come back from PC8+ we need to | |
10212 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
10213 | * need to take care of the registers kept by RC6. Notice that this happens even | |
10214 | * if we don't put the device in PCI D3 state (which is what currently happens | |
10215 | * because of the runtime PM support). | |
10216 | * | |
10217 | * For more, read "Display Sequences for Package C8" on the hardware | |
10218 | * documentation. | |
10219 | */ | |
a14cb6fc | 10220 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 10221 | { |
c67a470b PZ |
10222 | uint32_t val; |
10223 | ||
c67a470b PZ |
10224 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
10225 | ||
4f8036a2 | 10226 | if (HAS_PCH_LPT_LP(dev_priv)) { |
c67a470b PZ |
10227 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
10228 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
10229 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
10230 | } | |
10231 | ||
c39055b0 | 10232 | lpt_disable_clkout_dp(dev_priv); |
c67a470b PZ |
10233 | hsw_disable_lcpll(dev_priv, true, true); |
10234 | } | |
10235 | ||
a14cb6fc | 10236 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 10237 | { |
c67a470b PZ |
10238 | uint32_t val; |
10239 | ||
c67a470b PZ |
10240 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
10241 | ||
10242 | hsw_restore_lcpll(dev_priv); | |
c39055b0 | 10243 | lpt_init_pch_refclk(dev_priv); |
c67a470b | 10244 | |
4f8036a2 | 10245 | if (HAS_PCH_LPT_LP(dev_priv)) { |
c67a470b PZ |
10246 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
10247 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
10248 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
10249 | } | |
c67a470b PZ |
10250 | } |
10251 | ||
324513c0 | 10252 | static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
f8437dd1 | 10253 | { |
a821fc46 | 10254 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
10255 | struct intel_atomic_state *old_intel_state = |
10256 | to_intel_atomic_state(old_state); | |
10257 | unsigned int req_cdclk = old_intel_state->dev_cdclk; | |
f8437dd1 | 10258 | |
324513c0 | 10259 | bxt_set_cdclk(to_i915(dev), req_cdclk); |
f8437dd1 VK |
10260 | } |
10261 | ||
b30ce9e0 DP |
10262 | static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state, |
10263 | int pixel_rate) | |
10264 | { | |
9c754024 DP |
10265 | struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); |
10266 | ||
b30ce9e0 | 10267 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ |
9c754024 | 10268 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) |
b30ce9e0 DP |
10269 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); |
10270 | ||
10271 | /* BSpec says "Do not use DisplayPort with CDCLK less than | |
10272 | * 432 MHz, audio enabled, port width x4, and link rate | |
10273 | * HBR2 (5.4 GHz), or else there may be audio corruption or | |
10274 | * screen corruption." | |
10275 | */ | |
10276 | if (intel_crtc_has_dp_encoder(crtc_state) && | |
10277 | crtc_state->has_audio && | |
10278 | crtc_state->port_clock >= 540000 && | |
10279 | crtc_state->lane_count == 4) | |
10280 | pixel_rate = max(432000, pixel_rate); | |
10281 | ||
10282 | return pixel_rate; | |
10283 | } | |
10284 | ||
b432e5cf | 10285 | /* compute the max rate for new configuration */ |
27c329ed | 10286 | static int ilk_max_pixel_rate(struct drm_atomic_state *state) |
b432e5cf | 10287 | { |
565602d7 | 10288 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 10289 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
565602d7 ML |
10290 | struct drm_crtc *crtc; |
10291 | struct drm_crtc_state *cstate; | |
27c329ed | 10292 | struct intel_crtc_state *crtc_state; |
565602d7 ML |
10293 | unsigned max_pixel_rate = 0, i; |
10294 | enum pipe pipe; | |
b432e5cf | 10295 | |
565602d7 ML |
10296 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
10297 | sizeof(intel_state->min_pixclk)); | |
27c329ed | 10298 | |
565602d7 ML |
10299 | for_each_crtc_in_state(state, crtc, cstate, i) { |
10300 | int pixel_rate; | |
27c329ed | 10301 | |
565602d7 ML |
10302 | crtc_state = to_intel_crtc_state(cstate); |
10303 | if (!crtc_state->base.enable) { | |
10304 | intel_state->min_pixclk[i] = 0; | |
b432e5cf | 10305 | continue; |
565602d7 | 10306 | } |
b432e5cf | 10307 | |
27c329ed | 10308 | pixel_rate = ilk_pipe_pixel_rate(crtc_state); |
b432e5cf | 10309 | |
9c754024 | 10310 | if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv)) |
b30ce9e0 DP |
10311 | pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state, |
10312 | pixel_rate); | |
b432e5cf | 10313 | |
565602d7 | 10314 | intel_state->min_pixclk[i] = pixel_rate; |
b432e5cf VS |
10315 | } |
10316 | ||
565602d7 ML |
10317 | for_each_pipe(dev_priv, pipe) |
10318 | max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate); | |
10319 | ||
b432e5cf VS |
10320 | return max_pixel_rate; |
10321 | } | |
10322 | ||
10323 | static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) | |
10324 | { | |
fac5e23e | 10325 | struct drm_i915_private *dev_priv = to_i915(dev); |
b432e5cf VS |
10326 | uint32_t val, data; |
10327 | int ret; | |
10328 | ||
10329 | if (WARN((I915_READ(LCPLL_CTL) & | |
10330 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | | |
10331 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | | |
10332 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | | |
10333 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, | |
10334 | "trying to change cdclk frequency with cdclk not enabled\n")) | |
10335 | return; | |
10336 | ||
10337 | mutex_lock(&dev_priv->rps.hw_lock); | |
10338 | ret = sandybridge_pcode_write(dev_priv, | |
10339 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); | |
10340 | mutex_unlock(&dev_priv->rps.hw_lock); | |
10341 | if (ret) { | |
10342 | DRM_ERROR("failed to inform pcode about cdclk change\n"); | |
10343 | return; | |
10344 | } | |
10345 | ||
10346 | val = I915_READ(LCPLL_CTL); | |
10347 | val |= LCPLL_CD_SOURCE_FCLK; | |
10348 | I915_WRITE(LCPLL_CTL, val); | |
10349 | ||
5ba00178 TU |
10350 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
10351 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
b432e5cf VS |
10352 | DRM_ERROR("Switching to FCLK failed\n"); |
10353 | ||
10354 | val = I915_READ(LCPLL_CTL); | |
10355 | val &= ~LCPLL_CLK_FREQ_MASK; | |
10356 | ||
10357 | switch (cdclk) { | |
10358 | case 450000: | |
10359 | val |= LCPLL_CLK_FREQ_450; | |
10360 | data = 0; | |
10361 | break; | |
10362 | case 540000: | |
10363 | val |= LCPLL_CLK_FREQ_54O_BDW; | |
10364 | data = 1; | |
10365 | break; | |
10366 | case 337500: | |
10367 | val |= LCPLL_CLK_FREQ_337_5_BDW; | |
10368 | data = 2; | |
10369 | break; | |
10370 | case 675000: | |
10371 | val |= LCPLL_CLK_FREQ_675_BDW; | |
10372 | data = 3; | |
10373 | break; | |
10374 | default: | |
10375 | WARN(1, "invalid cdclk frequency\n"); | |
10376 | return; | |
10377 | } | |
10378 | ||
10379 | I915_WRITE(LCPLL_CTL, val); | |
10380 | ||
10381 | val = I915_READ(LCPLL_CTL); | |
10382 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
10383 | I915_WRITE(LCPLL_CTL, val); | |
10384 | ||
5ba00178 TU |
10385 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
10386 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
b432e5cf VS |
10387 | DRM_ERROR("Switching back to LCPLL failed\n"); |
10388 | ||
10389 | mutex_lock(&dev_priv->rps.hw_lock); | |
10390 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); | |
10391 | mutex_unlock(&dev_priv->rps.hw_lock); | |
10392 | ||
7f1052a8 VS |
10393 | I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1); |
10394 | ||
4c75b940 | 10395 | intel_update_cdclk(dev_priv); |
b432e5cf VS |
10396 | |
10397 | WARN(cdclk != dev_priv->cdclk_freq, | |
10398 | "cdclk requested %d kHz but got %d kHz\n", | |
10399 | cdclk, dev_priv->cdclk_freq); | |
10400 | } | |
10401 | ||
587c7914 VS |
10402 | static int broadwell_calc_cdclk(int max_pixclk) |
10403 | { | |
10404 | if (max_pixclk > 540000) | |
10405 | return 675000; | |
10406 | else if (max_pixclk > 450000) | |
10407 | return 540000; | |
10408 | else if (max_pixclk > 337500) | |
10409 | return 450000; | |
10410 | else | |
10411 | return 337500; | |
10412 | } | |
10413 | ||
27c329ed | 10414 | static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state) |
b432e5cf | 10415 | { |
27c329ed | 10416 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
1a617b77 | 10417 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
27c329ed | 10418 | int max_pixclk = ilk_max_pixel_rate(state); |
b432e5cf VS |
10419 | int cdclk; |
10420 | ||
10421 | /* | |
10422 | * FIXME should also account for plane ratio | |
10423 | * once 64bpp pixel formats are supported. | |
10424 | */ | |
587c7914 | 10425 | cdclk = broadwell_calc_cdclk(max_pixclk); |
b432e5cf | 10426 | |
b432e5cf | 10427 | if (cdclk > dev_priv->max_cdclk_freq) { |
63ba534e ML |
10428 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", |
10429 | cdclk, dev_priv->max_cdclk_freq); | |
10430 | return -EINVAL; | |
b432e5cf VS |
10431 | } |
10432 | ||
1a617b77 ML |
10433 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; |
10434 | if (!intel_state->active_crtcs) | |
587c7914 | 10435 | intel_state->dev_cdclk = broadwell_calc_cdclk(0); |
b432e5cf VS |
10436 | |
10437 | return 0; | |
10438 | } | |
10439 | ||
27c329ed | 10440 | static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
b432e5cf | 10441 | { |
27c329ed | 10442 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
10443 | struct intel_atomic_state *old_intel_state = |
10444 | to_intel_atomic_state(old_state); | |
10445 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
b432e5cf | 10446 | |
27c329ed | 10447 | broadwell_set_cdclk(dev, req_cdclk); |
b432e5cf VS |
10448 | } |
10449 | ||
c89e39f3 CT |
10450 | static int skl_modeset_calc_cdclk(struct drm_atomic_state *state) |
10451 | { | |
10452 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
10453 | struct drm_i915_private *dev_priv = to_i915(state->dev); | |
10454 | const int max_pixclk = ilk_max_pixel_rate(state); | |
a8ca4934 | 10455 | int vco = intel_state->cdclk_pll_vco; |
c89e39f3 CT |
10456 | int cdclk; |
10457 | ||
10458 | /* | |
10459 | * FIXME should also account for plane ratio | |
10460 | * once 64bpp pixel formats are supported. | |
10461 | */ | |
a8ca4934 | 10462 | cdclk = skl_calc_cdclk(max_pixclk, vco); |
c89e39f3 CT |
10463 | |
10464 | /* | |
10465 | * FIXME move the cdclk caclulation to | |
10466 | * compute_config() so we can fail gracegully. | |
10467 | */ | |
10468 | if (cdclk > dev_priv->max_cdclk_freq) { | |
10469 | DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n", | |
10470 | cdclk, dev_priv->max_cdclk_freq); | |
10471 | cdclk = dev_priv->max_cdclk_freq; | |
10472 | } | |
10473 | ||
10474 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; | |
10475 | if (!intel_state->active_crtcs) | |
a8ca4934 | 10476 | intel_state->dev_cdclk = skl_calc_cdclk(0, vco); |
c89e39f3 CT |
10477 | |
10478 | return 0; | |
10479 | } | |
10480 | ||
10481 | static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state) | |
10482 | { | |
1cd593e0 VS |
10483 | struct drm_i915_private *dev_priv = to_i915(old_state->dev); |
10484 | struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state); | |
10485 | unsigned int req_cdclk = intel_state->dev_cdclk; | |
10486 | unsigned int req_vco = intel_state->cdclk_pll_vco; | |
c89e39f3 | 10487 | |
1cd593e0 | 10488 | skl_set_cdclk(dev_priv, req_cdclk, req_vco); |
c89e39f3 CT |
10489 | } |
10490 | ||
190f68c5 ACO |
10491 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
10492 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 10493 | { |
d7edc4e5 | 10494 | if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) { |
af3997b5 MK |
10495 | if (!intel_ddi_pll_select(crtc, crtc_state)) |
10496 | return -EINVAL; | |
10497 | } | |
716c2e55 | 10498 | |
c7653199 | 10499 | crtc->lowfreq_avail = false; |
644cef34 | 10500 | |
c8f7a0db | 10501 | return 0; |
79e53945 JB |
10502 | } |
10503 | ||
3760b59c S |
10504 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
10505 | enum port port, | |
10506 | struct intel_crtc_state *pipe_config) | |
10507 | { | |
8106ddbd ACO |
10508 | enum intel_dpll_id id; |
10509 | ||
3760b59c S |
10510 | switch (port) { |
10511 | case PORT_A: | |
08250c4b | 10512 | id = DPLL_ID_SKL_DPLL0; |
3760b59c S |
10513 | break; |
10514 | case PORT_B: | |
08250c4b | 10515 | id = DPLL_ID_SKL_DPLL1; |
3760b59c S |
10516 | break; |
10517 | case PORT_C: | |
08250c4b | 10518 | id = DPLL_ID_SKL_DPLL2; |
3760b59c S |
10519 | break; |
10520 | default: | |
10521 | DRM_ERROR("Incorrect port type\n"); | |
8106ddbd | 10522 | return; |
3760b59c | 10523 | } |
8106ddbd ACO |
10524 | |
10525 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
3760b59c S |
10526 | } |
10527 | ||
96b7dfb7 S |
10528 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
10529 | enum port port, | |
5cec258b | 10530 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 10531 | { |
8106ddbd | 10532 | enum intel_dpll_id id; |
a3c988ea | 10533 | u32 temp; |
96b7dfb7 S |
10534 | |
10535 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
c856052a | 10536 | id = temp >> (port * 3 + 1); |
96b7dfb7 | 10537 | |
c856052a | 10538 | if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3)) |
8106ddbd | 10539 | return; |
8106ddbd ACO |
10540 | |
10541 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
96b7dfb7 S |
10542 | } |
10543 | ||
7d2c8175 DL |
10544 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
10545 | enum port port, | |
5cec258b | 10546 | struct intel_crtc_state *pipe_config) |
7d2c8175 | 10547 | { |
8106ddbd | 10548 | enum intel_dpll_id id; |
c856052a | 10549 | uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); |
8106ddbd | 10550 | |
c856052a | 10551 | switch (ddi_pll_sel) { |
7d2c8175 | 10552 | case PORT_CLK_SEL_WRPLL1: |
8106ddbd | 10553 | id = DPLL_ID_WRPLL1; |
7d2c8175 DL |
10554 | break; |
10555 | case PORT_CLK_SEL_WRPLL2: | |
8106ddbd | 10556 | id = DPLL_ID_WRPLL2; |
7d2c8175 | 10557 | break; |
00490c22 | 10558 | case PORT_CLK_SEL_SPLL: |
8106ddbd | 10559 | id = DPLL_ID_SPLL; |
79bd23da | 10560 | break; |
9d16da65 ACO |
10561 | case PORT_CLK_SEL_LCPLL_810: |
10562 | id = DPLL_ID_LCPLL_810; | |
10563 | break; | |
10564 | case PORT_CLK_SEL_LCPLL_1350: | |
10565 | id = DPLL_ID_LCPLL_1350; | |
10566 | break; | |
10567 | case PORT_CLK_SEL_LCPLL_2700: | |
10568 | id = DPLL_ID_LCPLL_2700; | |
10569 | break; | |
8106ddbd | 10570 | default: |
c856052a | 10571 | MISSING_CASE(ddi_pll_sel); |
8106ddbd ACO |
10572 | /* fall through */ |
10573 | case PORT_CLK_SEL_NONE: | |
8106ddbd | 10574 | return; |
7d2c8175 | 10575 | } |
8106ddbd ACO |
10576 | |
10577 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
7d2c8175 DL |
10578 | } |
10579 | ||
cf30429e JN |
10580 | static bool hsw_get_transcoder_state(struct intel_crtc *crtc, |
10581 | struct intel_crtc_state *pipe_config, | |
10582 | unsigned long *power_domain_mask) | |
10583 | { | |
10584 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10585 | struct drm_i915_private *dev_priv = to_i915(dev); |
cf30429e JN |
10586 | enum intel_display_power_domain power_domain; |
10587 | u32 tmp; | |
10588 | ||
d9a7bc67 ID |
10589 | /* |
10590 | * The pipe->transcoder mapping is fixed with the exception of the eDP | |
10591 | * transcoder handled below. | |
10592 | */ | |
cf30429e JN |
10593 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
10594 | ||
10595 | /* | |
10596 | * XXX: Do intel_display_power_get_if_enabled before reading this (for | |
10597 | * consistency and less surprising code; it's in always on power). | |
10598 | */ | |
10599 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
10600 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
10601 | enum pipe trans_edp_pipe; | |
10602 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
10603 | default: | |
10604 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
10605 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
10606 | case TRANS_DDI_EDP_INPUT_A_ON: | |
10607 | trans_edp_pipe = PIPE_A; | |
10608 | break; | |
10609 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
10610 | trans_edp_pipe = PIPE_B; | |
10611 | break; | |
10612 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
10613 | trans_edp_pipe = PIPE_C; | |
10614 | break; | |
10615 | } | |
10616 | ||
10617 | if (trans_edp_pipe == crtc->pipe) | |
10618 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
10619 | } | |
10620 | ||
10621 | power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); | |
10622 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
10623 | return false; | |
10624 | *power_domain_mask |= BIT(power_domain); | |
10625 | ||
10626 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); | |
10627 | ||
10628 | return tmp & PIPECONF_ENABLE; | |
10629 | } | |
10630 | ||
4d1de975 JN |
10631 | static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, |
10632 | struct intel_crtc_state *pipe_config, | |
10633 | unsigned long *power_domain_mask) | |
10634 | { | |
10635 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10636 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 JN |
10637 | enum intel_display_power_domain power_domain; |
10638 | enum port port; | |
10639 | enum transcoder cpu_transcoder; | |
10640 | u32 tmp; | |
10641 | ||
4d1de975 JN |
10642 | for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { |
10643 | if (port == PORT_A) | |
10644 | cpu_transcoder = TRANSCODER_DSI_A; | |
10645 | else | |
10646 | cpu_transcoder = TRANSCODER_DSI_C; | |
10647 | ||
10648 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
10649 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
10650 | continue; | |
10651 | *power_domain_mask |= BIT(power_domain); | |
10652 | ||
db18b6a6 ID |
10653 | /* |
10654 | * The PLL needs to be enabled with a valid divider | |
10655 | * configuration, otherwise accessing DSI registers will hang | |
10656 | * the machine. See BSpec North Display Engine | |
10657 | * registers/MIPI[BXT]. We can break out here early, since we | |
10658 | * need the same DSI PLL to be enabled for both DSI ports. | |
10659 | */ | |
10660 | if (!intel_dsi_pll_is_enabled(dev_priv)) | |
10661 | break; | |
10662 | ||
4d1de975 JN |
10663 | /* XXX: this works for video mode only */ |
10664 | tmp = I915_READ(BXT_MIPI_PORT_CTRL(port)); | |
10665 | if (!(tmp & DPI_ENABLE)) | |
10666 | continue; | |
10667 | ||
10668 | tmp = I915_READ(MIPI_CTRL(port)); | |
10669 | if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) | |
10670 | continue; | |
10671 | ||
10672 | pipe_config->cpu_transcoder = cpu_transcoder; | |
4d1de975 JN |
10673 | break; |
10674 | } | |
10675 | ||
d7edc4e5 | 10676 | return transcoder_is_dsi(pipe_config->cpu_transcoder); |
4d1de975 JN |
10677 | } |
10678 | ||
26804afd | 10679 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 10680 | struct intel_crtc_state *pipe_config) |
26804afd | 10681 | { |
6315b5d3 | 10682 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
d452c5b6 | 10683 | struct intel_shared_dpll *pll; |
26804afd DV |
10684 | enum port port; |
10685 | uint32_t tmp; | |
10686 | ||
10687 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
10688 | ||
10689 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
10690 | ||
0853723b | 10691 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
96b7dfb7 | 10692 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
cc3f90f0 | 10693 | else if (IS_GEN9_LP(dev_priv)) |
3760b59c | 10694 | bxt_get_ddi_pll(dev_priv, port, pipe_config); |
96b7dfb7 S |
10695 | else |
10696 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 10697 | |
8106ddbd ACO |
10698 | pll = pipe_config->shared_dpll; |
10699 | if (pll) { | |
2edd6443 ACO |
10700 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
10701 | &pipe_config->dpll_hw_state)); | |
d452c5b6 DV |
10702 | } |
10703 | ||
26804afd DV |
10704 | /* |
10705 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
10706 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
10707 | * the PCH transcoder is on. | |
10708 | */ | |
6315b5d3 | 10709 | if (INTEL_GEN(dev_priv) < 9 && |
ca370455 | 10710 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
26804afd DV |
10711 | pipe_config->has_pch_encoder = true; |
10712 | ||
10713 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
10714 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
10715 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
10716 | ||
10717 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
10718 | } | |
10719 | } | |
10720 | ||
0e8ffe1b | 10721 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 10722 | struct intel_crtc_state *pipe_config) |
0e8ffe1b | 10723 | { |
6315b5d3 | 10724 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1729050e ID |
10725 | enum intel_display_power_domain power_domain; |
10726 | unsigned long power_domain_mask; | |
cf30429e | 10727 | bool active; |
0e8ffe1b | 10728 | |
1729050e ID |
10729 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
10730 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 | 10731 | return false; |
1729050e ID |
10732 | power_domain_mask = BIT(power_domain); |
10733 | ||
8106ddbd | 10734 | pipe_config->shared_dpll = NULL; |
c0d43d62 | 10735 | |
cf30429e | 10736 | active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask); |
eccb140b | 10737 | |
cc3f90f0 | 10738 | if (IS_GEN9_LP(dev_priv) && |
d7edc4e5 VS |
10739 | bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) { |
10740 | WARN_ON(active); | |
10741 | active = true; | |
4d1de975 JN |
10742 | } |
10743 | ||
cf30429e | 10744 | if (!active) |
1729050e | 10745 | goto out; |
0e8ffe1b | 10746 | |
d7edc4e5 | 10747 | if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { |
4d1de975 JN |
10748 | haswell_get_ddi_port_state(crtc, pipe_config); |
10749 | intel_get_pipe_timings(crtc, pipe_config); | |
10750 | } | |
627eb5a3 | 10751 | |
bc58be60 | 10752 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 10753 | |
05dc698c LL |
10754 | pipe_config->gamma_mode = |
10755 | I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; | |
10756 | ||
6315b5d3 | 10757 | if (INTEL_GEN(dev_priv) >= 9) { |
65edccce | 10758 | skl_init_scalers(dev_priv, crtc, pipe_config); |
a1b2278e | 10759 | |
af99ceda CK |
10760 | pipe_config->scaler_state.scaler_id = -1; |
10761 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
10762 | } | |
10763 | ||
1729050e ID |
10764 | power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
10765 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
10766 | power_domain_mask |= BIT(power_domain); | |
6315b5d3 | 10767 | if (INTEL_GEN(dev_priv) >= 9) |
bd2e244f | 10768 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 10769 | else |
1c132b44 | 10770 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 10771 | } |
88adfff1 | 10772 | |
772c2a51 | 10773 | if (IS_HASWELL(dev_priv)) |
e59150dc JB |
10774 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && |
10775 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 10776 | |
4d1de975 JN |
10777 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP && |
10778 | !transcoder_is_dsi(pipe_config->cpu_transcoder)) { | |
ebb69c95 CT |
10779 | pipe_config->pixel_multiplier = |
10780 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
10781 | } else { | |
10782 | pipe_config->pixel_multiplier = 1; | |
10783 | } | |
6c49f241 | 10784 | |
1729050e ID |
10785 | out: |
10786 | for_each_power_domain(power_domain, power_domain_mask) | |
10787 | intel_display_power_put(dev_priv, power_domain); | |
10788 | ||
cf30429e | 10789 | return active; |
0e8ffe1b DV |
10790 | } |
10791 | ||
55a08b3f ML |
10792 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base, |
10793 | const struct intel_plane_state *plane_state) | |
560b85bb CW |
10794 | { |
10795 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 10796 | struct drm_i915_private *dev_priv = to_i915(dev); |
560b85bb | 10797 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
dc41c154 | 10798 | uint32_t cntl = 0, size = 0; |
560b85bb | 10799 | |
936e71e3 | 10800 | if (plane_state && plane_state->base.visible) { |
55a08b3f ML |
10801 | unsigned int width = plane_state->base.crtc_w; |
10802 | unsigned int height = plane_state->base.crtc_h; | |
dc41c154 VS |
10803 | unsigned int stride = roundup_pow_of_two(width) * 4; |
10804 | ||
10805 | switch (stride) { | |
10806 | default: | |
10807 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
10808 | width, stride); | |
10809 | stride = 256; | |
10810 | /* fallthrough */ | |
10811 | case 256: | |
10812 | case 512: | |
10813 | case 1024: | |
10814 | case 2048: | |
10815 | break; | |
4b0e333e CW |
10816 | } |
10817 | ||
dc41c154 VS |
10818 | cntl |= CURSOR_ENABLE | |
10819 | CURSOR_GAMMA_ENABLE | | |
10820 | CURSOR_FORMAT_ARGB | | |
10821 | CURSOR_STRIDE(stride); | |
10822 | ||
10823 | size = (height << 12) | width; | |
4b0e333e | 10824 | } |
560b85bb | 10825 | |
dc41c154 VS |
10826 | if (intel_crtc->cursor_cntl != 0 && |
10827 | (intel_crtc->cursor_base != base || | |
10828 | intel_crtc->cursor_size != size || | |
10829 | intel_crtc->cursor_cntl != cntl)) { | |
10830 | /* On these chipsets we can only modify the base/size/stride | |
10831 | * whilst the cursor is disabled. | |
10832 | */ | |
0b87c24e VS |
10833 | I915_WRITE(CURCNTR(PIPE_A), 0); |
10834 | POSTING_READ(CURCNTR(PIPE_A)); | |
dc41c154 | 10835 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 10836 | } |
560b85bb | 10837 | |
99d1f387 | 10838 | if (intel_crtc->cursor_base != base) { |
0b87c24e | 10839 | I915_WRITE(CURBASE(PIPE_A), base); |
99d1f387 VS |
10840 | intel_crtc->cursor_base = base; |
10841 | } | |
4726e0b0 | 10842 | |
dc41c154 VS |
10843 | if (intel_crtc->cursor_size != size) { |
10844 | I915_WRITE(CURSIZE, size); | |
10845 | intel_crtc->cursor_size = size; | |
4b0e333e | 10846 | } |
560b85bb | 10847 | |
4b0e333e | 10848 | if (intel_crtc->cursor_cntl != cntl) { |
0b87c24e VS |
10849 | I915_WRITE(CURCNTR(PIPE_A), cntl); |
10850 | POSTING_READ(CURCNTR(PIPE_A)); | |
4b0e333e | 10851 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 10852 | } |
560b85bb CW |
10853 | } |
10854 | ||
55a08b3f ML |
10855 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, |
10856 | const struct intel_plane_state *plane_state) | |
65a21cd6 JB |
10857 | { |
10858 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 10859 | struct drm_i915_private *dev_priv = to_i915(dev); |
65a21cd6 JB |
10860 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10861 | int pipe = intel_crtc->pipe; | |
663f3122 | 10862 | uint32_t cntl = 0; |
4b0e333e | 10863 | |
936e71e3 | 10864 | if (plane_state && plane_state->base.visible) { |
4b0e333e | 10865 | cntl = MCURSOR_GAMMA_ENABLE; |
55a08b3f | 10866 | switch (plane_state->base.crtc_w) { |
4726e0b0 SK |
10867 | case 64: |
10868 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
10869 | break; | |
10870 | case 128: | |
10871 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
10872 | break; | |
10873 | case 256: | |
10874 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
10875 | break; | |
10876 | default: | |
55a08b3f | 10877 | MISSING_CASE(plane_state->base.crtc_w); |
4726e0b0 | 10878 | return; |
65a21cd6 | 10879 | } |
4b0e333e | 10880 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 | 10881 | |
4f8036a2 | 10882 | if (HAS_DDI(dev_priv)) |
47bf17a7 | 10883 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
65a21cd6 | 10884 | |
f22aa143 | 10885 | if (plane_state->base.rotation & DRM_ROTATE_180) |
55a08b3f ML |
10886 | cntl |= CURSOR_ROTATE_180; |
10887 | } | |
4398ad45 | 10888 | |
4b0e333e CW |
10889 | if (intel_crtc->cursor_cntl != cntl) { |
10890 | I915_WRITE(CURCNTR(pipe), cntl); | |
10891 | POSTING_READ(CURCNTR(pipe)); | |
10892 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 10893 | } |
4b0e333e | 10894 | |
65a21cd6 | 10895 | /* and commit changes on next vblank */ |
5efb3e28 VS |
10896 | I915_WRITE(CURBASE(pipe), base); |
10897 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
10898 | |
10899 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
10900 | } |
10901 | ||
cda4b7d3 | 10902 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f | 10903 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
55a08b3f | 10904 | const struct intel_plane_state *plane_state) |
cda4b7d3 CW |
10905 | { |
10906 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 10907 | struct drm_i915_private *dev_priv = to_i915(dev); |
cda4b7d3 CW |
10908 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10909 | int pipe = intel_crtc->pipe; | |
55a08b3f ML |
10910 | u32 base = intel_crtc->cursor_addr; |
10911 | u32 pos = 0; | |
cda4b7d3 | 10912 | |
55a08b3f ML |
10913 | if (plane_state) { |
10914 | int x = plane_state->base.crtc_x; | |
10915 | int y = plane_state->base.crtc_y; | |
cda4b7d3 | 10916 | |
55a08b3f ML |
10917 | if (x < 0) { |
10918 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
10919 | x = -x; | |
10920 | } | |
10921 | pos |= x << CURSOR_X_SHIFT; | |
cda4b7d3 | 10922 | |
55a08b3f ML |
10923 | if (y < 0) { |
10924 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
10925 | y = -y; | |
10926 | } | |
10927 | pos |= y << CURSOR_Y_SHIFT; | |
10928 | ||
10929 | /* ILK+ do this automagically */ | |
49cff963 | 10930 | if (HAS_GMCH_DISPLAY(dev_priv) && |
f22aa143 | 10931 | plane_state->base.rotation & DRM_ROTATE_180) { |
55a08b3f ML |
10932 | base += (plane_state->base.crtc_h * |
10933 | plane_state->base.crtc_w - 1) * 4; | |
10934 | } | |
cda4b7d3 | 10935 | } |
cda4b7d3 | 10936 | |
5efb3e28 VS |
10937 | I915_WRITE(CURPOS(pipe), pos); |
10938 | ||
2a307c2e | 10939 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) |
55a08b3f | 10940 | i845_update_cursor(crtc, base, plane_state); |
5efb3e28 | 10941 | else |
55a08b3f | 10942 | i9xx_update_cursor(crtc, base, plane_state); |
cda4b7d3 CW |
10943 | } |
10944 | ||
50a0bc90 | 10945 | static bool cursor_size_ok(struct drm_i915_private *dev_priv, |
dc41c154 VS |
10946 | uint32_t width, uint32_t height) |
10947 | { | |
10948 | if (width == 0 || height == 0) | |
10949 | return false; | |
10950 | ||
10951 | /* | |
10952 | * 845g/865g are special in that they are only limited by | |
10953 | * the width of their cursors, the height is arbitrary up to | |
10954 | * the precision of the register. Everything else requires | |
10955 | * square cursors, limited to a few power-of-two sizes. | |
10956 | */ | |
2a307c2e | 10957 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { |
dc41c154 VS |
10958 | if ((width & 63) != 0) |
10959 | return false; | |
10960 | ||
2a307c2e | 10961 | if (width > (IS_I845G(dev_priv) ? 64 : 512)) |
dc41c154 VS |
10962 | return false; |
10963 | ||
10964 | if (height > 1023) | |
10965 | return false; | |
10966 | } else { | |
10967 | switch (width | height) { | |
10968 | case 256: | |
10969 | case 128: | |
50a0bc90 | 10970 | if (IS_GEN2(dev_priv)) |
dc41c154 VS |
10971 | return false; |
10972 | case 64: | |
10973 | break; | |
10974 | default: | |
10975 | return false; | |
10976 | } | |
10977 | } | |
10978 | ||
10979 | return true; | |
10980 | } | |
10981 | ||
79e53945 JB |
10982 | /* VESA 640x480x72Hz mode to set on the pipe */ |
10983 | static struct drm_display_mode load_detect_mode = { | |
10984 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
10985 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
10986 | }; | |
10987 | ||
a8bb6818 DV |
10988 | struct drm_framebuffer * |
10989 | __intel_framebuffer_create(struct drm_device *dev, | |
10990 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10991 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
10992 | { |
10993 | struct intel_framebuffer *intel_fb; | |
10994 | int ret; | |
10995 | ||
10996 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
dcb1394e | 10997 | if (!intel_fb) |
d2dff872 | 10998 | return ERR_PTR(-ENOMEM); |
d2dff872 CW |
10999 | |
11000 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
11001 | if (ret) |
11002 | goto err; | |
d2dff872 CW |
11003 | |
11004 | return &intel_fb->base; | |
dcb1394e | 11005 | |
dd4916c5 | 11006 | err: |
dd4916c5 | 11007 | kfree(intel_fb); |
dd4916c5 | 11008 | return ERR_PTR(ret); |
d2dff872 CW |
11009 | } |
11010 | ||
b5ea642a | 11011 | static struct drm_framebuffer * |
a8bb6818 DV |
11012 | intel_framebuffer_create(struct drm_device *dev, |
11013 | struct drm_mode_fb_cmd2 *mode_cmd, | |
11014 | struct drm_i915_gem_object *obj) | |
11015 | { | |
11016 | struct drm_framebuffer *fb; | |
11017 | int ret; | |
11018 | ||
11019 | ret = i915_mutex_lock_interruptible(dev); | |
11020 | if (ret) | |
11021 | return ERR_PTR(ret); | |
11022 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
11023 | mutex_unlock(&dev->struct_mutex); | |
11024 | ||
11025 | return fb; | |
11026 | } | |
11027 | ||
d2dff872 CW |
11028 | static u32 |
11029 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
11030 | { | |
11031 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
11032 | return ALIGN(pitch, 64); | |
11033 | } | |
11034 | ||
11035 | static u32 | |
11036 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
11037 | { | |
11038 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 11039 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
11040 | } |
11041 | ||
11042 | static struct drm_framebuffer * | |
11043 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
11044 | struct drm_display_mode *mode, | |
11045 | int depth, int bpp) | |
11046 | { | |
dcb1394e | 11047 | struct drm_framebuffer *fb; |
d2dff872 | 11048 | struct drm_i915_gem_object *obj; |
0fed39bd | 11049 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 | 11050 | |
12d79d78 | 11051 | obj = i915_gem_object_create(to_i915(dev), |
d2dff872 | 11052 | intel_framebuffer_size_for_mode(mode, bpp)); |
fe3db79b CW |
11053 | if (IS_ERR(obj)) |
11054 | return ERR_CAST(obj); | |
d2dff872 CW |
11055 | |
11056 | mode_cmd.width = mode->hdisplay; | |
11057 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
11058 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
11059 | bpp); | |
5ca0c34a | 11060 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 | 11061 | |
dcb1394e LW |
11062 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
11063 | if (IS_ERR(fb)) | |
f0cd5182 | 11064 | i915_gem_object_put(obj); |
dcb1394e LW |
11065 | |
11066 | return fb; | |
d2dff872 CW |
11067 | } |
11068 | ||
11069 | static struct drm_framebuffer * | |
11070 | mode_fits_in_fbdev(struct drm_device *dev, | |
11071 | struct drm_display_mode *mode) | |
11072 | { | |
0695726e | 11073 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
fac5e23e | 11074 | struct drm_i915_private *dev_priv = to_i915(dev); |
d2dff872 CW |
11075 | struct drm_i915_gem_object *obj; |
11076 | struct drm_framebuffer *fb; | |
11077 | ||
4c0e5528 | 11078 | if (!dev_priv->fbdev) |
d2dff872 CW |
11079 | return NULL; |
11080 | ||
4c0e5528 | 11081 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
11082 | return NULL; |
11083 | ||
4c0e5528 DV |
11084 | obj = dev_priv->fbdev->fb->obj; |
11085 | BUG_ON(!obj); | |
11086 | ||
8bcd4553 | 11087 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
11088 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
11089 | fb->bits_per_pixel)) | |
d2dff872 CW |
11090 | return NULL; |
11091 | ||
01f2c773 | 11092 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
11093 | return NULL; |
11094 | ||
edde3617 | 11095 | drm_framebuffer_reference(fb); |
d2dff872 | 11096 | return fb; |
4520f53a DV |
11097 | #else |
11098 | return NULL; | |
11099 | #endif | |
d2dff872 CW |
11100 | } |
11101 | ||
d3a40d1b ACO |
11102 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
11103 | struct drm_crtc *crtc, | |
11104 | struct drm_display_mode *mode, | |
11105 | struct drm_framebuffer *fb, | |
11106 | int x, int y) | |
11107 | { | |
11108 | struct drm_plane_state *plane_state; | |
11109 | int hdisplay, vdisplay; | |
11110 | int ret; | |
11111 | ||
11112 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
11113 | if (IS_ERR(plane_state)) | |
11114 | return PTR_ERR(plane_state); | |
11115 | ||
11116 | if (mode) | |
11117 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); | |
11118 | else | |
11119 | hdisplay = vdisplay = 0; | |
11120 | ||
11121 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
11122 | if (ret) | |
11123 | return ret; | |
11124 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
11125 | plane_state->crtc_x = 0; | |
11126 | plane_state->crtc_y = 0; | |
11127 | plane_state->crtc_w = hdisplay; | |
11128 | plane_state->crtc_h = vdisplay; | |
11129 | plane_state->src_x = x << 16; | |
11130 | plane_state->src_y = y << 16; | |
11131 | plane_state->src_w = hdisplay << 16; | |
11132 | plane_state->src_h = vdisplay << 16; | |
11133 | ||
11134 | return 0; | |
11135 | } | |
11136 | ||
d2434ab7 | 11137 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 11138 | struct drm_display_mode *mode, |
51fd371b RC |
11139 | struct intel_load_detect_pipe *old, |
11140 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
11141 | { |
11142 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
11143 | struct intel_encoder *intel_encoder = |
11144 | intel_attached_encoder(connector); | |
79e53945 | 11145 | struct drm_crtc *possible_crtc; |
4ef69c7a | 11146 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
11147 | struct drm_crtc *crtc = NULL; |
11148 | struct drm_device *dev = encoder->dev; | |
0f0f74bc | 11149 | struct drm_i915_private *dev_priv = to_i915(dev); |
94352cf9 | 11150 | struct drm_framebuffer *fb; |
51fd371b | 11151 | struct drm_mode_config *config = &dev->mode_config; |
edde3617 | 11152 | struct drm_atomic_state *state = NULL, *restore_state = NULL; |
944b0c76 | 11153 | struct drm_connector_state *connector_state; |
4be07317 | 11154 | struct intel_crtc_state *crtc_state; |
51fd371b | 11155 | int ret, i = -1; |
79e53945 | 11156 | |
d2dff872 | 11157 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 11158 | connector->base.id, connector->name, |
8e329a03 | 11159 | encoder->base.id, encoder->name); |
d2dff872 | 11160 | |
edde3617 ML |
11161 | old->restore_state = NULL; |
11162 | ||
51fd371b RC |
11163 | retry: |
11164 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
11165 | if (ret) | |
ad3c558f | 11166 | goto fail; |
6e9f798d | 11167 | |
79e53945 JB |
11168 | /* |
11169 | * Algorithm gets a little messy: | |
7a5e4805 | 11170 | * |
79e53945 JB |
11171 | * - if the connector already has an assigned crtc, use it (but make |
11172 | * sure it's on first) | |
7a5e4805 | 11173 | * |
79e53945 JB |
11174 | * - try to find the first unused crtc that can drive this connector, |
11175 | * and use that if we find one | |
79e53945 JB |
11176 | */ |
11177 | ||
11178 | /* See if we already have a CRTC for this connector */ | |
edde3617 ML |
11179 | if (connector->state->crtc) { |
11180 | crtc = connector->state->crtc; | |
8261b191 | 11181 | |
51fd371b | 11182 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 11183 | if (ret) |
ad3c558f | 11184 | goto fail; |
8261b191 CW |
11185 | |
11186 | /* Make sure the crtc and connector are running */ | |
edde3617 | 11187 | goto found; |
79e53945 JB |
11188 | } |
11189 | ||
11190 | /* Find an unused one (if possible) */ | |
70e1e0ec | 11191 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
11192 | i++; |
11193 | if (!(encoder->possible_crtcs & (1 << i))) | |
11194 | continue; | |
edde3617 ML |
11195 | |
11196 | ret = drm_modeset_lock(&possible_crtc->mutex, ctx); | |
11197 | if (ret) | |
11198 | goto fail; | |
11199 | ||
11200 | if (possible_crtc->state->enable) { | |
11201 | drm_modeset_unlock(&possible_crtc->mutex); | |
a459249c | 11202 | continue; |
edde3617 | 11203 | } |
a459249c VS |
11204 | |
11205 | crtc = possible_crtc; | |
11206 | break; | |
79e53945 JB |
11207 | } |
11208 | ||
11209 | /* | |
11210 | * If we didn't find an unused CRTC, don't use any. | |
11211 | */ | |
11212 | if (!crtc) { | |
7173188d | 11213 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
ad3c558f | 11214 | goto fail; |
79e53945 JB |
11215 | } |
11216 | ||
edde3617 ML |
11217 | found: |
11218 | intel_crtc = to_intel_crtc(crtc); | |
11219 | ||
4d02e2de DV |
11220 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
11221 | if (ret) | |
ad3c558f | 11222 | goto fail; |
79e53945 | 11223 | |
83a57153 | 11224 | state = drm_atomic_state_alloc(dev); |
edde3617 ML |
11225 | restore_state = drm_atomic_state_alloc(dev); |
11226 | if (!state || !restore_state) { | |
11227 | ret = -ENOMEM; | |
11228 | goto fail; | |
11229 | } | |
83a57153 ACO |
11230 | |
11231 | state->acquire_ctx = ctx; | |
edde3617 | 11232 | restore_state->acquire_ctx = ctx; |
83a57153 | 11233 | |
944b0c76 ACO |
11234 | connector_state = drm_atomic_get_connector_state(state, connector); |
11235 | if (IS_ERR(connector_state)) { | |
11236 | ret = PTR_ERR(connector_state); | |
11237 | goto fail; | |
11238 | } | |
11239 | ||
edde3617 ML |
11240 | ret = drm_atomic_set_crtc_for_connector(connector_state, crtc); |
11241 | if (ret) | |
11242 | goto fail; | |
944b0c76 | 11243 | |
4be07317 ACO |
11244 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
11245 | if (IS_ERR(crtc_state)) { | |
11246 | ret = PTR_ERR(crtc_state); | |
11247 | goto fail; | |
11248 | } | |
11249 | ||
49d6fa21 | 11250 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 11251 | |
6492711d CW |
11252 | if (!mode) |
11253 | mode = &load_detect_mode; | |
79e53945 | 11254 | |
d2dff872 CW |
11255 | /* We need a framebuffer large enough to accommodate all accesses |
11256 | * that the plane may generate whilst we perform load detection. | |
11257 | * We can not rely on the fbcon either being present (we get called | |
11258 | * during its initialisation to detect all boot displays, or it may | |
11259 | * not even exist) or that it is large enough to satisfy the | |
11260 | * requested mode. | |
11261 | */ | |
94352cf9 DV |
11262 | fb = mode_fits_in_fbdev(dev, mode); |
11263 | if (fb == NULL) { | |
d2dff872 | 11264 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 | 11265 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
d2dff872 CW |
11266 | } else |
11267 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 11268 | if (IS_ERR(fb)) { |
d2dff872 | 11269 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 11270 | goto fail; |
79e53945 | 11271 | } |
79e53945 | 11272 | |
d3a40d1b ACO |
11273 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
11274 | if (ret) | |
11275 | goto fail; | |
11276 | ||
edde3617 ML |
11277 | drm_framebuffer_unreference(fb); |
11278 | ||
11279 | ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode); | |
11280 | if (ret) | |
11281 | goto fail; | |
11282 | ||
11283 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); | |
11284 | if (!ret) | |
11285 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc)); | |
11286 | if (!ret) | |
11287 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary)); | |
11288 | if (ret) { | |
11289 | DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret); | |
11290 | goto fail; | |
11291 | } | |
8c7b5ccb | 11292 | |
3ba86073 ML |
11293 | ret = drm_atomic_commit(state); |
11294 | if (ret) { | |
6492711d | 11295 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
412b61d8 | 11296 | goto fail; |
79e53945 | 11297 | } |
edde3617 ML |
11298 | |
11299 | old->restore_state = restore_state; | |
7173188d | 11300 | |
79e53945 | 11301 | /* let the connector get through one full cycle before testing */ |
0f0f74bc | 11302 | intel_wait_for_vblank(dev_priv, intel_crtc->pipe); |
7173188d | 11303 | return true; |
412b61d8 | 11304 | |
ad3c558f | 11305 | fail: |
7fb71c8f CW |
11306 | if (state) { |
11307 | drm_atomic_state_put(state); | |
11308 | state = NULL; | |
11309 | } | |
11310 | if (restore_state) { | |
11311 | drm_atomic_state_put(restore_state); | |
11312 | restore_state = NULL; | |
11313 | } | |
83a57153 | 11314 | |
51fd371b RC |
11315 | if (ret == -EDEADLK) { |
11316 | drm_modeset_backoff(ctx); | |
11317 | goto retry; | |
11318 | } | |
11319 | ||
412b61d8 | 11320 | return false; |
79e53945 JB |
11321 | } |
11322 | ||
d2434ab7 | 11323 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
11324 | struct intel_load_detect_pipe *old, |
11325 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 11326 | { |
d2434ab7 DV |
11327 | struct intel_encoder *intel_encoder = |
11328 | intel_attached_encoder(connector); | |
4ef69c7a | 11329 | struct drm_encoder *encoder = &intel_encoder->base; |
edde3617 | 11330 | struct drm_atomic_state *state = old->restore_state; |
d3a40d1b | 11331 | int ret; |
79e53945 | 11332 | |
d2dff872 | 11333 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 11334 | connector->base.id, connector->name, |
8e329a03 | 11335 | encoder->base.id, encoder->name); |
d2dff872 | 11336 | |
edde3617 | 11337 | if (!state) |
0622a53c | 11338 | return; |
79e53945 | 11339 | |
edde3617 | 11340 | ret = drm_atomic_commit(state); |
0853695c | 11341 | if (ret) |
edde3617 | 11342 | DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret); |
0853695c | 11343 | drm_atomic_state_put(state); |
79e53945 JB |
11344 | } |
11345 | ||
da4a1efa | 11346 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 11347 | const struct intel_crtc_state *pipe_config) |
da4a1efa | 11348 | { |
fac5e23e | 11349 | struct drm_i915_private *dev_priv = to_i915(dev); |
da4a1efa VS |
11350 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
11351 | ||
11352 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 11353 | return dev_priv->vbt.lvds_ssc_freq; |
6e266956 | 11354 | else if (HAS_PCH_SPLIT(dev_priv)) |
da4a1efa | 11355 | return 120000; |
5db94019 | 11356 | else if (!IS_GEN2(dev_priv)) |
da4a1efa VS |
11357 | return 96000; |
11358 | else | |
11359 | return 48000; | |
11360 | } | |
11361 | ||
79e53945 | 11362 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 11363 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 11364 | struct intel_crtc_state *pipe_config) |
79e53945 | 11365 | { |
f1f644dc | 11366 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 11367 | struct drm_i915_private *dev_priv = to_i915(dev); |
f1f644dc | 11368 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 11369 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 | 11370 | u32 fp; |
9e2c8475 | 11371 | struct dpll clock; |
dccbea3b | 11372 | int port_clock; |
da4a1efa | 11373 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
11374 | |
11375 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 11376 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 11377 | else |
293623f7 | 11378 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
11379 | |
11380 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
9b1e14f4 | 11381 | if (IS_PINEVIEW(dev_priv)) { |
f2b115e6 AJ |
11382 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; |
11383 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
11384 | } else { |
11385 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
11386 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
11387 | } | |
11388 | ||
5db94019 | 11389 | if (!IS_GEN2(dev_priv)) { |
9b1e14f4 | 11390 | if (IS_PINEVIEW(dev_priv)) |
f2b115e6 AJ |
11391 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> |
11392 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
11393 | else |
11394 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
11395 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
11396 | ||
11397 | switch (dpll & DPLL_MODE_MASK) { | |
11398 | case DPLLB_MODE_DAC_SERIAL: | |
11399 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
11400 | 5 : 10; | |
11401 | break; | |
11402 | case DPLLB_MODE_LVDS: | |
11403 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
11404 | 7 : 14; | |
11405 | break; | |
11406 | default: | |
28c97730 | 11407 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 11408 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 11409 | return; |
79e53945 JB |
11410 | } |
11411 | ||
9b1e14f4 | 11412 | if (IS_PINEVIEW(dev_priv)) |
dccbea3b | 11413 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 11414 | else |
dccbea3b | 11415 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 11416 | } else { |
50a0bc90 | 11417 | u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS); |
b1c560d1 | 11418 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
11419 | |
11420 | if (is_lvds) { | |
11421 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
11422 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
11423 | |
11424 | if (lvds & LVDS_CLKB_POWER_UP) | |
11425 | clock.p2 = 7; | |
11426 | else | |
11427 | clock.p2 = 14; | |
79e53945 JB |
11428 | } else { |
11429 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
11430 | clock.p1 = 2; | |
11431 | else { | |
11432 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
11433 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
11434 | } | |
11435 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
11436 | clock.p2 = 4; | |
11437 | else | |
11438 | clock.p2 = 2; | |
79e53945 | 11439 | } |
da4a1efa | 11440 | |
dccbea3b | 11441 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
11442 | } |
11443 | ||
18442d08 VS |
11444 | /* |
11445 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 11446 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
11447 | * encoder's get_config() function. |
11448 | */ | |
dccbea3b | 11449 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
11450 | } |
11451 | ||
6878da05 VS |
11452 | int intel_dotclock_calculate(int link_freq, |
11453 | const struct intel_link_m_n *m_n) | |
f1f644dc | 11454 | { |
f1f644dc JB |
11455 | /* |
11456 | * The calculation for the data clock is: | |
1041a02f | 11457 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 11458 | * But we want to avoid losing precison if possible, so: |
1041a02f | 11459 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
11460 | * |
11461 | * and the link clock is simpler: | |
1041a02f | 11462 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
11463 | */ |
11464 | ||
6878da05 VS |
11465 | if (!m_n->link_n) |
11466 | return 0; | |
f1f644dc | 11467 | |
6878da05 VS |
11468 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
11469 | } | |
f1f644dc | 11470 | |
18442d08 | 11471 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 11472 | struct intel_crtc_state *pipe_config) |
6878da05 | 11473 | { |
e3b247da | 11474 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
79e53945 | 11475 | |
18442d08 VS |
11476 | /* read out port_clock from the DPLL */ |
11477 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 11478 | |
f1f644dc | 11479 | /* |
e3b247da VS |
11480 | * In case there is an active pipe without active ports, |
11481 | * we may need some idea for the dotclock anyway. | |
11482 | * Calculate one based on the FDI configuration. | |
79e53945 | 11483 | */ |
2d112de7 | 11484 | pipe_config->base.adjusted_mode.crtc_clock = |
21a727b3 | 11485 | intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
18442d08 | 11486 | &pipe_config->fdi_m_n); |
79e53945 JB |
11487 | } |
11488 | ||
11489 | /** Returns the currently programmed mode of the given pipe. */ | |
11490 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
11491 | struct drm_crtc *crtc) | |
11492 | { | |
fac5e23e | 11493 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 11494 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 11495 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 11496 | struct drm_display_mode *mode; |
3f36b937 | 11497 | struct intel_crtc_state *pipe_config; |
fe2b8f9d PZ |
11498 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
11499 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
11500 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
11501 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 11502 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
11503 | |
11504 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
11505 | if (!mode) | |
11506 | return NULL; | |
11507 | ||
3f36b937 TU |
11508 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
11509 | if (!pipe_config) { | |
11510 | kfree(mode); | |
11511 | return NULL; | |
11512 | } | |
11513 | ||
f1f644dc JB |
11514 | /* |
11515 | * Construct a pipe_config sufficient for getting the clock info | |
11516 | * back out of crtc_clock_get. | |
11517 | * | |
11518 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
11519 | * to use a real value here instead. | |
11520 | */ | |
3f36b937 TU |
11521 | pipe_config->cpu_transcoder = (enum transcoder) pipe; |
11522 | pipe_config->pixel_multiplier = 1; | |
11523 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe)); | |
11524 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
11525 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
11526 | i9xx_crtc_clock_get(intel_crtc, pipe_config); | |
11527 | ||
11528 | mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier; | |
79e53945 JB |
11529 | mode->hdisplay = (htot & 0xffff) + 1; |
11530 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
11531 | mode->hsync_start = (hsync & 0xffff) + 1; | |
11532 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
11533 | mode->vdisplay = (vtot & 0xffff) + 1; | |
11534 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
11535 | mode->vsync_start = (vsync & 0xffff) + 1; | |
11536 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
11537 | ||
11538 | drm_mode_set_name(mode); | |
79e53945 | 11539 | |
3f36b937 TU |
11540 | kfree(pipe_config); |
11541 | ||
79e53945 JB |
11542 | return mode; |
11543 | } | |
11544 | ||
11545 | static void intel_crtc_destroy(struct drm_crtc *crtc) | |
11546 | { | |
11547 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a | 11548 | struct drm_device *dev = crtc->dev; |
51cbaf01 | 11549 | struct intel_flip_work *work; |
67e77c5a | 11550 | |
5e2d7afc | 11551 | spin_lock_irq(&dev->event_lock); |
5a21b665 DV |
11552 | work = intel_crtc->flip_work; |
11553 | intel_crtc->flip_work = NULL; | |
11554 | spin_unlock_irq(&dev->event_lock); | |
67e77c5a | 11555 | |
5a21b665 | 11556 | if (work) { |
51cbaf01 ML |
11557 | cancel_work_sync(&work->mmio_work); |
11558 | cancel_work_sync(&work->unpin_work); | |
5a21b665 | 11559 | kfree(work); |
67e77c5a | 11560 | } |
79e53945 JB |
11561 | |
11562 | drm_crtc_cleanup(crtc); | |
67e77c5a | 11563 | |
79e53945 JB |
11564 | kfree(intel_crtc); |
11565 | } | |
11566 | ||
6b95a207 KH |
11567 | static void intel_unpin_work_fn(struct work_struct *__work) |
11568 | { | |
51cbaf01 ML |
11569 | struct intel_flip_work *work = |
11570 | container_of(__work, struct intel_flip_work, unpin_work); | |
5a21b665 DV |
11571 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); |
11572 | struct drm_device *dev = crtc->base.dev; | |
11573 | struct drm_plane *primary = crtc->base.primary; | |
03f476e1 | 11574 | |
5a21b665 DV |
11575 | if (is_mmio_work(work)) |
11576 | flush_work(&work->mmio_work); | |
03f476e1 | 11577 | |
5a21b665 DV |
11578 | mutex_lock(&dev->struct_mutex); |
11579 | intel_unpin_fb_obj(work->old_fb, primary->state->rotation); | |
f8c417cd | 11580 | i915_gem_object_put(work->pending_flip_obj); |
5a21b665 | 11581 | mutex_unlock(&dev->struct_mutex); |
143f73b3 | 11582 | |
e8a261ea CW |
11583 | i915_gem_request_put(work->flip_queued_req); |
11584 | ||
5748b6a1 CW |
11585 | intel_frontbuffer_flip_complete(to_i915(dev), |
11586 | to_intel_plane(primary)->frontbuffer_bit); | |
5a21b665 DV |
11587 | intel_fbc_post_update(crtc); |
11588 | drm_framebuffer_unreference(work->old_fb); | |
143f73b3 | 11589 | |
5a21b665 DV |
11590 | BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); |
11591 | atomic_dec(&crtc->unpin_work_count); | |
a6747b73 | 11592 | |
5a21b665 DV |
11593 | kfree(work); |
11594 | } | |
d9e86c0e | 11595 | |
5a21b665 DV |
11596 | /* Is 'a' after or equal to 'b'? */ |
11597 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
11598 | { | |
11599 | return !((a - b) & 0x80000000); | |
11600 | } | |
143f73b3 | 11601 | |
5a21b665 DV |
11602 | static bool __pageflip_finished_cs(struct intel_crtc *crtc, |
11603 | struct intel_flip_work *work) | |
11604 | { | |
11605 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 11606 | struct drm_i915_private *dev_priv = to_i915(dev); |
143f73b3 | 11607 | |
8af29b0c | 11608 | if (abort_flip_on_reset(crtc)) |
5a21b665 | 11609 | return true; |
143f73b3 | 11610 | |
5a21b665 DV |
11611 | /* |
11612 | * The relevant registers doen't exist on pre-ctg. | |
11613 | * As the flip done interrupt doesn't trigger for mmio | |
11614 | * flips on gmch platforms, a flip count check isn't | |
11615 | * really needed there. But since ctg has the registers, | |
11616 | * include it in the check anyway. | |
11617 | */ | |
9beb5fea | 11618 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) |
5a21b665 | 11619 | return true; |
b4a98e57 | 11620 | |
5a21b665 DV |
11621 | /* |
11622 | * BDW signals flip done immediately if the plane | |
11623 | * is disabled, even if the plane enable is already | |
11624 | * armed to occur at the next vblank :( | |
11625 | */ | |
f99d7069 | 11626 | |
5a21b665 DV |
11627 | /* |
11628 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
11629 | * used the same base address. In that case the mmio flip might | |
11630 | * have completed, but the CS hasn't even executed the flip yet. | |
11631 | * | |
11632 | * A flip count check isn't enough as the CS might have updated | |
11633 | * the base address just after start of vblank, but before we | |
11634 | * managed to process the interrupt. This means we'd complete the | |
11635 | * CS flip too soon. | |
11636 | * | |
11637 | * Combining both checks should get us a good enough result. It may | |
11638 | * still happen that the CS flip has been executed, but has not | |
11639 | * yet actually completed. But in case the base address is the same | |
11640 | * anyway, we don't really care. | |
11641 | */ | |
11642 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
11643 | crtc->flip_work->gtt_offset && | |
11644 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), | |
11645 | crtc->flip_work->flip_count); | |
11646 | } | |
b4a98e57 | 11647 | |
5a21b665 DV |
11648 | static bool |
11649 | __pageflip_finished_mmio(struct intel_crtc *crtc, | |
11650 | struct intel_flip_work *work) | |
11651 | { | |
11652 | /* | |
11653 | * MMIO work completes when vblank is different from | |
11654 | * flip_queued_vblank. | |
11655 | * | |
11656 | * Reset counter value doesn't matter, this is handled by | |
11657 | * i915_wait_request finishing early, so no need to handle | |
11658 | * reset here. | |
11659 | */ | |
11660 | return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank; | |
6b95a207 KH |
11661 | } |
11662 | ||
51cbaf01 ML |
11663 | |
11664 | static bool pageflip_finished(struct intel_crtc *crtc, | |
11665 | struct intel_flip_work *work) | |
11666 | { | |
11667 | if (!atomic_read(&work->pending)) | |
11668 | return false; | |
11669 | ||
11670 | smp_rmb(); | |
11671 | ||
5a21b665 DV |
11672 | if (is_mmio_work(work)) |
11673 | return __pageflip_finished_mmio(crtc, work); | |
11674 | else | |
11675 | return __pageflip_finished_cs(crtc, work); | |
11676 | } | |
11677 | ||
11678 | void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe) | |
11679 | { | |
91c8a326 | 11680 | struct drm_device *dev = &dev_priv->drm; |
98187836 | 11681 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
5a21b665 DV |
11682 | struct intel_flip_work *work; |
11683 | unsigned long flags; | |
11684 | ||
11685 | /* Ignore early vblank irqs */ | |
11686 | if (!crtc) | |
11687 | return; | |
11688 | ||
51cbaf01 | 11689 | /* |
5a21b665 DV |
11690 | * This is called both by irq handlers and the reset code (to complete |
11691 | * lost pageflips) so needs the full irqsave spinlocks. | |
51cbaf01 | 11692 | */ |
5a21b665 | 11693 | spin_lock_irqsave(&dev->event_lock, flags); |
e2af48c6 | 11694 | work = crtc->flip_work; |
5a21b665 DV |
11695 | |
11696 | if (work != NULL && | |
11697 | !is_mmio_work(work) && | |
e2af48c6 VS |
11698 | pageflip_finished(crtc, work)) |
11699 | page_flip_completed(crtc); | |
5a21b665 DV |
11700 | |
11701 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
75f7f3ec VS |
11702 | } |
11703 | ||
51cbaf01 | 11704 | void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe) |
6b95a207 | 11705 | { |
91c8a326 | 11706 | struct drm_device *dev = &dev_priv->drm; |
98187836 | 11707 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
51cbaf01 | 11708 | struct intel_flip_work *work; |
6b95a207 KH |
11709 | unsigned long flags; |
11710 | ||
5251f04e ML |
11711 | /* Ignore early vblank irqs */ |
11712 | if (!crtc) | |
11713 | return; | |
f326038a DV |
11714 | |
11715 | /* | |
11716 | * This is called both by irq handlers and the reset code (to complete | |
11717 | * lost pageflips) so needs the full irqsave spinlocks. | |
e7d841ca | 11718 | */ |
6b95a207 | 11719 | spin_lock_irqsave(&dev->event_lock, flags); |
e2af48c6 | 11720 | work = crtc->flip_work; |
5251f04e | 11721 | |
5a21b665 DV |
11722 | if (work != NULL && |
11723 | is_mmio_work(work) && | |
e2af48c6 VS |
11724 | pageflip_finished(crtc, work)) |
11725 | page_flip_completed(crtc); | |
5251f04e | 11726 | |
6b95a207 KH |
11727 | spin_unlock_irqrestore(&dev->event_lock, flags); |
11728 | } | |
11729 | ||
5a21b665 DV |
11730 | static inline void intel_mark_page_flip_active(struct intel_crtc *crtc, |
11731 | struct intel_flip_work *work) | |
84c33a64 | 11732 | { |
5a21b665 | 11733 | work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc); |
84c33a64 | 11734 | |
5a21b665 DV |
11735 | /* Ensure that the work item is consistent when activating it ... */ |
11736 | smp_mb__before_atomic(); | |
11737 | atomic_set(&work->pending, 1); | |
11738 | } | |
a6747b73 | 11739 | |
5a21b665 DV |
11740 | static int intel_gen2_queue_flip(struct drm_device *dev, |
11741 | struct drm_crtc *crtc, | |
11742 | struct drm_framebuffer *fb, | |
11743 | struct drm_i915_gem_object *obj, | |
11744 | struct drm_i915_gem_request *req, | |
11745 | uint32_t flags) | |
11746 | { | |
7e37f889 | 11747 | struct intel_ring *ring = req->ring; |
5a21b665 DV |
11748 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11749 | u32 flip_mask; | |
11750 | int ret; | |
143f73b3 | 11751 | |
5a21b665 DV |
11752 | ret = intel_ring_begin(req, 6); |
11753 | if (ret) | |
11754 | return ret; | |
143f73b3 | 11755 | |
5a21b665 DV |
11756 | /* Can't queue multiple flips, so wait for the previous |
11757 | * one to finish before executing the next. | |
11758 | */ | |
11759 | if (intel_crtc->plane) | |
11760 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11761 | else | |
11762 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
b5321f30 CW |
11763 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
11764 | intel_ring_emit(ring, MI_NOOP); | |
11765 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
5a21b665 | 11766 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
b5321f30 CW |
11767 | intel_ring_emit(ring, fb->pitches[0]); |
11768 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset); | |
11769 | intel_ring_emit(ring, 0); /* aux display base address, unused */ | |
143f73b3 | 11770 | |
5a21b665 DV |
11771 | return 0; |
11772 | } | |
84c33a64 | 11773 | |
5a21b665 DV |
11774 | static int intel_gen3_queue_flip(struct drm_device *dev, |
11775 | struct drm_crtc *crtc, | |
11776 | struct drm_framebuffer *fb, | |
11777 | struct drm_i915_gem_object *obj, | |
11778 | struct drm_i915_gem_request *req, | |
11779 | uint32_t flags) | |
11780 | { | |
7e37f889 | 11781 | struct intel_ring *ring = req->ring; |
5a21b665 DV |
11782 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11783 | u32 flip_mask; | |
11784 | int ret; | |
d55dbd06 | 11785 | |
5a21b665 DV |
11786 | ret = intel_ring_begin(req, 6); |
11787 | if (ret) | |
11788 | return ret; | |
d55dbd06 | 11789 | |
5a21b665 DV |
11790 | if (intel_crtc->plane) |
11791 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11792 | else | |
11793 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
b5321f30 CW |
11794 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
11795 | intel_ring_emit(ring, MI_NOOP); | |
11796 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
5a21b665 | 11797 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
b5321f30 CW |
11798 | intel_ring_emit(ring, fb->pitches[0]); |
11799 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset); | |
11800 | intel_ring_emit(ring, MI_NOOP); | |
fd8e058a | 11801 | |
5a21b665 DV |
11802 | return 0; |
11803 | } | |
84c33a64 | 11804 | |
5a21b665 DV |
11805 | static int intel_gen4_queue_flip(struct drm_device *dev, |
11806 | struct drm_crtc *crtc, | |
11807 | struct drm_framebuffer *fb, | |
11808 | struct drm_i915_gem_object *obj, | |
11809 | struct drm_i915_gem_request *req, | |
11810 | uint32_t flags) | |
11811 | { | |
7e37f889 | 11812 | struct intel_ring *ring = req->ring; |
fac5e23e | 11813 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
11814 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11815 | uint32_t pf, pipesrc; | |
11816 | int ret; | |
143f73b3 | 11817 | |
5a21b665 DV |
11818 | ret = intel_ring_begin(req, 4); |
11819 | if (ret) | |
11820 | return ret; | |
143f73b3 | 11821 | |
5a21b665 DV |
11822 | /* i965+ uses the linear or tiled offsets from the |
11823 | * Display Registers (which do not change across a page-flip) | |
11824 | * so we need only reprogram the base address. | |
11825 | */ | |
b5321f30 | 11826 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
5a21b665 | 11827 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
b5321f30 CW |
11828 | intel_ring_emit(ring, fb->pitches[0]); |
11829 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset | | |
bae781b2 | 11830 | intel_fb_modifier_to_tiling(fb->modifier)); |
5a21b665 DV |
11831 | |
11832 | /* XXX Enabling the panel-fitter across page-flip is so far | |
11833 | * untested on non-native modes, so ignore it for now. | |
11834 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
11835 | */ | |
11836 | pf = 0; | |
11837 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
b5321f30 | 11838 | intel_ring_emit(ring, pf | pipesrc); |
143f73b3 | 11839 | |
5a21b665 | 11840 | return 0; |
8c9f3aaf JB |
11841 | } |
11842 | ||
5a21b665 DV |
11843 | static int intel_gen6_queue_flip(struct drm_device *dev, |
11844 | struct drm_crtc *crtc, | |
11845 | struct drm_framebuffer *fb, | |
11846 | struct drm_i915_gem_object *obj, | |
11847 | struct drm_i915_gem_request *req, | |
11848 | uint32_t flags) | |
da20eabd | 11849 | { |
7e37f889 | 11850 | struct intel_ring *ring = req->ring; |
fac5e23e | 11851 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
11852 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11853 | uint32_t pf, pipesrc; | |
11854 | int ret; | |
d21fbe87 | 11855 | |
5a21b665 DV |
11856 | ret = intel_ring_begin(req, 4); |
11857 | if (ret) | |
11858 | return ret; | |
92826fcd | 11859 | |
b5321f30 | 11860 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
5a21b665 | 11861 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
72618ebf | 11862 | intel_ring_emit(ring, fb->pitches[0] | |
bae781b2 | 11863 | intel_fb_modifier_to_tiling(fb->modifier)); |
b5321f30 | 11864 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset); |
92826fcd | 11865 | |
5a21b665 DV |
11866 | /* Contrary to the suggestions in the documentation, |
11867 | * "Enable Panel Fitter" does not seem to be required when page | |
11868 | * flipping with a non-native mode, and worse causes a normal | |
11869 | * modeset to fail. | |
11870 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
11871 | */ | |
11872 | pf = 0; | |
11873 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
b5321f30 | 11874 | intel_ring_emit(ring, pf | pipesrc); |
7809e5ae | 11875 | |
5a21b665 | 11876 | return 0; |
7809e5ae MR |
11877 | } |
11878 | ||
5a21b665 DV |
11879 | static int intel_gen7_queue_flip(struct drm_device *dev, |
11880 | struct drm_crtc *crtc, | |
11881 | struct drm_framebuffer *fb, | |
11882 | struct drm_i915_gem_object *obj, | |
11883 | struct drm_i915_gem_request *req, | |
11884 | uint32_t flags) | |
d21fbe87 | 11885 | { |
5db94019 | 11886 | struct drm_i915_private *dev_priv = to_i915(dev); |
7e37f889 | 11887 | struct intel_ring *ring = req->ring; |
5a21b665 DV |
11888 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11889 | uint32_t plane_bit = 0; | |
11890 | int len, ret; | |
d21fbe87 | 11891 | |
5a21b665 DV |
11892 | switch (intel_crtc->plane) { |
11893 | case PLANE_A: | |
11894 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
11895 | break; | |
11896 | case PLANE_B: | |
11897 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
11898 | break; | |
11899 | case PLANE_C: | |
11900 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
11901 | break; | |
11902 | default: | |
11903 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
11904 | return -ENODEV; | |
11905 | } | |
11906 | ||
11907 | len = 4; | |
b5321f30 | 11908 | if (req->engine->id == RCS) { |
5a21b665 DV |
11909 | len += 6; |
11910 | /* | |
11911 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
11912 | * 48bits addresses, and we need a NOOP for the batch size to | |
11913 | * stay even. | |
11914 | */ | |
5db94019 | 11915 | if (IS_GEN8(dev_priv)) |
5a21b665 DV |
11916 | len += 2; |
11917 | } | |
11918 | ||
11919 | /* | |
11920 | * BSpec MI_DISPLAY_FLIP for IVB: | |
11921 | * "The full packet must be contained within the same cache line." | |
11922 | * | |
11923 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
11924 | * cacheline, if we ever start emitting more commands before | |
11925 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
11926 | * then do the cacheline alignment, and finally emit the | |
11927 | * MI_DISPLAY_FLIP. | |
11928 | */ | |
11929 | ret = intel_ring_cacheline_align(req); | |
11930 | if (ret) | |
11931 | return ret; | |
11932 | ||
11933 | ret = intel_ring_begin(req, len); | |
11934 | if (ret) | |
11935 | return ret; | |
11936 | ||
11937 | /* Unmask the flip-done completion message. Note that the bspec says that | |
11938 | * we should do this for both the BCS and RCS, and that we must not unmask | |
11939 | * more than one flip event at any time (or ensure that one flip message | |
11940 | * can be sent by waiting for flip-done prior to queueing new flips). | |
11941 | * Experimentation says that BCS works despite DERRMR masking all | |
11942 | * flip-done completion events and that unmasking all planes at once | |
11943 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
11944 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
11945 | */ | |
b5321f30 CW |
11946 | if (req->engine->id == RCS) { |
11947 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
11948 | intel_ring_emit_reg(ring, DERRMR); | |
11949 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
5a21b665 DV |
11950 | DERRMR_PIPEB_PRI_FLIP_DONE | |
11951 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
5db94019 | 11952 | if (IS_GEN8(dev_priv)) |
b5321f30 | 11953 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 | |
5a21b665 DV |
11954 | MI_SRM_LRM_GLOBAL_GTT); |
11955 | else | |
b5321f30 | 11956 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM | |
5a21b665 | 11957 | MI_SRM_LRM_GLOBAL_GTT); |
b5321f30 | 11958 | intel_ring_emit_reg(ring, DERRMR); |
bde13ebd CW |
11959 | intel_ring_emit(ring, |
11960 | i915_ggtt_offset(req->engine->scratch) + 256); | |
5db94019 | 11961 | if (IS_GEN8(dev_priv)) { |
b5321f30 CW |
11962 | intel_ring_emit(ring, 0); |
11963 | intel_ring_emit(ring, MI_NOOP); | |
5a21b665 DV |
11964 | } |
11965 | } | |
11966 | ||
b5321f30 | 11967 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
72618ebf | 11968 | intel_ring_emit(ring, fb->pitches[0] | |
bae781b2 | 11969 | intel_fb_modifier_to_tiling(fb->modifier)); |
b5321f30 CW |
11970 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset); |
11971 | intel_ring_emit(ring, (MI_NOOP)); | |
5a21b665 DV |
11972 | |
11973 | return 0; | |
11974 | } | |
11975 | ||
11976 | static bool use_mmio_flip(struct intel_engine_cs *engine, | |
11977 | struct drm_i915_gem_object *obj) | |
11978 | { | |
11979 | /* | |
11980 | * This is not being used for older platforms, because | |
11981 | * non-availability of flip done interrupt forces us to use | |
11982 | * CS flips. Older platforms derive flip done using some clever | |
11983 | * tricks involving the flip_pending status bits and vblank irqs. | |
11984 | * So using MMIO flips there would disrupt this mechanism. | |
11985 | */ | |
11986 | ||
11987 | if (engine == NULL) | |
11988 | return true; | |
11989 | ||
11990 | if (INTEL_GEN(engine->i915) < 5) | |
11991 | return false; | |
11992 | ||
11993 | if (i915.use_mmio_flip < 0) | |
11994 | return false; | |
11995 | else if (i915.use_mmio_flip > 0) | |
11996 | return true; | |
11997 | else if (i915.enable_execlists) | |
11998 | return true; | |
c37efb99 | 11999 | |
d07f0e59 | 12000 | return engine != i915_gem_object_last_write_engine(obj); |
5a21b665 DV |
12001 | } |
12002 | ||
12003 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, | |
12004 | unsigned int rotation, | |
12005 | struct intel_flip_work *work) | |
12006 | { | |
12007 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 12008 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
12009 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; |
12010 | const enum pipe pipe = intel_crtc->pipe; | |
d2196774 | 12011 | u32 ctl, stride = skl_plane_stride(fb, 0, rotation); |
5a21b665 DV |
12012 | |
12013 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
12014 | ctl &= ~PLANE_CTL_TILED_MASK; | |
bae781b2 | 12015 | switch (fb->modifier) { |
5a21b665 DV |
12016 | case DRM_FORMAT_MOD_NONE: |
12017 | break; | |
12018 | case I915_FORMAT_MOD_X_TILED: | |
12019 | ctl |= PLANE_CTL_TILED_X; | |
12020 | break; | |
12021 | case I915_FORMAT_MOD_Y_TILED: | |
12022 | ctl |= PLANE_CTL_TILED_Y; | |
12023 | break; | |
12024 | case I915_FORMAT_MOD_Yf_TILED: | |
12025 | ctl |= PLANE_CTL_TILED_YF; | |
12026 | break; | |
12027 | default: | |
bae781b2 | 12028 | MISSING_CASE(fb->modifier); |
5a21b665 DV |
12029 | } |
12030 | ||
5a21b665 DV |
12031 | /* |
12032 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
12033 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
12034 | */ | |
12035 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
12036 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
12037 | ||
12038 | I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); | |
12039 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
12040 | } | |
12041 | ||
12042 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, | |
12043 | struct intel_flip_work *work) | |
12044 | { | |
12045 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 12046 | struct drm_i915_private *dev_priv = to_i915(dev); |
72618ebf | 12047 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; |
5a21b665 DV |
12048 | i915_reg_t reg = DSPCNTR(intel_crtc->plane); |
12049 | u32 dspcntr; | |
12050 | ||
12051 | dspcntr = I915_READ(reg); | |
12052 | ||
bae781b2 | 12053 | if (fb->modifier == I915_FORMAT_MOD_X_TILED) |
5a21b665 DV |
12054 | dspcntr |= DISPPLANE_TILED; |
12055 | else | |
12056 | dspcntr &= ~DISPPLANE_TILED; | |
12057 | ||
12058 | I915_WRITE(reg, dspcntr); | |
12059 | ||
12060 | I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); | |
12061 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
12062 | } | |
12063 | ||
12064 | static void intel_mmio_flip_work_func(struct work_struct *w) | |
12065 | { | |
12066 | struct intel_flip_work *work = | |
12067 | container_of(w, struct intel_flip_work, mmio_work); | |
12068 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); | |
12069 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
12070 | struct intel_framebuffer *intel_fb = | |
12071 | to_intel_framebuffer(crtc->base.primary->fb); | |
12072 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
12073 | ||
d07f0e59 | 12074 | WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0); |
5a21b665 DV |
12075 | |
12076 | intel_pipe_update_start(crtc); | |
12077 | ||
12078 | if (INTEL_GEN(dev_priv) >= 9) | |
12079 | skl_do_mmio_flip(crtc, work->rotation, work); | |
12080 | else | |
12081 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
12082 | ilk_do_mmio_flip(crtc, work); | |
12083 | ||
12084 | intel_pipe_update_end(crtc, work); | |
12085 | } | |
12086 | ||
12087 | static int intel_default_queue_flip(struct drm_device *dev, | |
12088 | struct drm_crtc *crtc, | |
12089 | struct drm_framebuffer *fb, | |
12090 | struct drm_i915_gem_object *obj, | |
12091 | struct drm_i915_gem_request *req, | |
12092 | uint32_t flags) | |
12093 | { | |
12094 | return -ENODEV; | |
12095 | } | |
12096 | ||
12097 | static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv, | |
12098 | struct intel_crtc *intel_crtc, | |
12099 | struct intel_flip_work *work) | |
12100 | { | |
12101 | u32 addr, vblank; | |
12102 | ||
12103 | if (!atomic_read(&work->pending)) | |
12104 | return false; | |
12105 | ||
12106 | smp_rmb(); | |
12107 | ||
12108 | vblank = intel_crtc_get_vblank_counter(intel_crtc); | |
12109 | if (work->flip_ready_vblank == 0) { | |
12110 | if (work->flip_queued_req && | |
f69a02c9 | 12111 | !i915_gem_request_completed(work->flip_queued_req)) |
5a21b665 DV |
12112 | return false; |
12113 | ||
12114 | work->flip_ready_vblank = vblank; | |
12115 | } | |
12116 | ||
12117 | if (vblank - work->flip_ready_vblank < 3) | |
12118 | return false; | |
12119 | ||
12120 | /* Potential stall - if we see that the flip has happened, | |
12121 | * assume a missed interrupt. */ | |
12122 | if (INTEL_GEN(dev_priv) >= 4) | |
12123 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
12124 | else | |
12125 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
12126 | ||
12127 | /* There is a potential issue here with a false positive after a flip | |
12128 | * to the same address. We could address this by checking for a | |
12129 | * non-incrementing frame counter. | |
12130 | */ | |
12131 | return addr == work->gtt_offset; | |
12132 | } | |
12133 | ||
12134 | void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe) | |
12135 | { | |
91c8a326 | 12136 | struct drm_device *dev = &dev_priv->drm; |
98187836 | 12137 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
5a21b665 DV |
12138 | struct intel_flip_work *work; |
12139 | ||
12140 | WARN_ON(!in_interrupt()); | |
12141 | ||
12142 | if (crtc == NULL) | |
12143 | return; | |
12144 | ||
12145 | spin_lock(&dev->event_lock); | |
e2af48c6 | 12146 | work = crtc->flip_work; |
5a21b665 DV |
12147 | |
12148 | if (work != NULL && !is_mmio_work(work) && | |
e2af48c6 | 12149 | __pageflip_stall_check_cs(dev_priv, crtc, work)) { |
5a21b665 DV |
12150 | WARN_ONCE(1, |
12151 | "Kicking stuck page flip: queued at %d, now %d\n", | |
e2af48c6 VS |
12152 | work->flip_queued_vblank, intel_crtc_get_vblank_counter(crtc)); |
12153 | page_flip_completed(crtc); | |
5a21b665 DV |
12154 | work = NULL; |
12155 | } | |
12156 | ||
12157 | if (work != NULL && !is_mmio_work(work) && | |
e2af48c6 | 12158 | intel_crtc_get_vblank_counter(crtc) - work->flip_queued_vblank > 1) |
5a21b665 DV |
12159 | intel_queue_rps_boost_for_request(work->flip_queued_req); |
12160 | spin_unlock(&dev->event_lock); | |
12161 | } | |
12162 | ||
12163 | static int intel_crtc_page_flip(struct drm_crtc *crtc, | |
12164 | struct drm_framebuffer *fb, | |
12165 | struct drm_pending_vblank_event *event, | |
12166 | uint32_t page_flip_flags) | |
12167 | { | |
12168 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 12169 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
12170 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
12171 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
12172 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12173 | struct drm_plane *primary = crtc->primary; | |
12174 | enum pipe pipe = intel_crtc->pipe; | |
12175 | struct intel_flip_work *work; | |
12176 | struct intel_engine_cs *engine; | |
12177 | bool mmio_flip; | |
8e637178 | 12178 | struct drm_i915_gem_request *request; |
058d88c4 | 12179 | struct i915_vma *vma; |
5a21b665 DV |
12180 | int ret; |
12181 | ||
12182 | /* | |
12183 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
12184 | * check to be safe. In the future we may enable pageflipping from | |
12185 | * a disabled primary plane. | |
12186 | */ | |
12187 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
12188 | return -EBUSY; | |
12189 | ||
12190 | /* Can't change pixel format via MI display flips. */ | |
12191 | if (fb->pixel_format != crtc->primary->fb->pixel_format) | |
12192 | return -EINVAL; | |
12193 | ||
12194 | /* | |
12195 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
12196 | * Note that pitch changes could also affect these register. | |
12197 | */ | |
6315b5d3 | 12198 | if (INTEL_GEN(dev_priv) > 3 && |
5a21b665 DV |
12199 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
12200 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
12201 | return -EINVAL; | |
12202 | ||
12203 | if (i915_terminally_wedged(&dev_priv->gpu_error)) | |
12204 | goto out_hang; | |
12205 | ||
12206 | work = kzalloc(sizeof(*work), GFP_KERNEL); | |
12207 | if (work == NULL) | |
12208 | return -ENOMEM; | |
12209 | ||
12210 | work->event = event; | |
12211 | work->crtc = crtc; | |
12212 | work->old_fb = old_fb; | |
12213 | INIT_WORK(&work->unpin_work, intel_unpin_work_fn); | |
12214 | ||
12215 | ret = drm_crtc_vblank_get(crtc); | |
12216 | if (ret) | |
12217 | goto free_work; | |
12218 | ||
12219 | /* We borrow the event spin lock for protecting flip_work */ | |
12220 | spin_lock_irq(&dev->event_lock); | |
12221 | if (intel_crtc->flip_work) { | |
12222 | /* Before declaring the flip queue wedged, check if | |
12223 | * the hardware completed the operation behind our backs. | |
12224 | */ | |
12225 | if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) { | |
12226 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
12227 | page_flip_completed(intel_crtc); | |
12228 | } else { | |
12229 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
12230 | spin_unlock_irq(&dev->event_lock); | |
12231 | ||
12232 | drm_crtc_vblank_put(crtc); | |
12233 | kfree(work); | |
12234 | return -EBUSY; | |
12235 | } | |
12236 | } | |
12237 | intel_crtc->flip_work = work; | |
12238 | spin_unlock_irq(&dev->event_lock); | |
12239 | ||
12240 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) | |
12241 | flush_workqueue(dev_priv->wq); | |
12242 | ||
12243 | /* Reference the objects for the scheduled work. */ | |
12244 | drm_framebuffer_reference(work->old_fb); | |
5a21b665 DV |
12245 | |
12246 | crtc->primary->fb = fb; | |
12247 | update_state_fb(crtc->primary); | |
faf68d92 | 12248 | |
25dc556a | 12249 | work->pending_flip_obj = i915_gem_object_get(obj); |
5a21b665 DV |
12250 | |
12251 | ret = i915_mutex_lock_interruptible(dev); | |
12252 | if (ret) | |
12253 | goto cleanup; | |
12254 | ||
8af29b0c CW |
12255 | intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error); |
12256 | if (i915_reset_in_progress_or_wedged(&dev_priv->gpu_error)) { | |
5a21b665 | 12257 | ret = -EIO; |
ddbb271a | 12258 | goto unlock; |
5a21b665 DV |
12259 | } |
12260 | ||
12261 | atomic_inc(&intel_crtc->unpin_work_count); | |
12262 | ||
9beb5fea | 12263 | if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) |
5a21b665 DV |
12264 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; |
12265 | ||
920a14b2 | 12266 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
3b3f1650 | 12267 | engine = dev_priv->engine[BCS]; |
bae781b2 | 12268 | if (fb->modifier != old_fb->modifier) |
5a21b665 DV |
12269 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
12270 | engine = NULL; | |
fd6b8f43 | 12271 | } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) { |
3b3f1650 | 12272 | engine = dev_priv->engine[BCS]; |
6315b5d3 | 12273 | } else if (INTEL_GEN(dev_priv) >= 7) { |
d07f0e59 | 12274 | engine = i915_gem_object_last_write_engine(obj); |
5a21b665 | 12275 | if (engine == NULL || engine->id != RCS) |
3b3f1650 | 12276 | engine = dev_priv->engine[BCS]; |
5a21b665 | 12277 | } else { |
3b3f1650 | 12278 | engine = dev_priv->engine[RCS]; |
5a21b665 DV |
12279 | } |
12280 | ||
12281 | mmio_flip = use_mmio_flip(engine, obj); | |
12282 | ||
058d88c4 CW |
12283 | vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation); |
12284 | if (IS_ERR(vma)) { | |
12285 | ret = PTR_ERR(vma); | |
5a21b665 | 12286 | goto cleanup_pending; |
058d88c4 | 12287 | } |
5a21b665 | 12288 | |
6687c906 | 12289 | work->gtt_offset = intel_fb_gtt_offset(fb, primary->state->rotation); |
5a21b665 DV |
12290 | work->gtt_offset += intel_crtc->dspaddr_offset; |
12291 | work->rotation = crtc->primary->state->rotation; | |
12292 | ||
1f061316 PZ |
12293 | /* |
12294 | * There's the potential that the next frame will not be compatible with | |
12295 | * FBC, so we want to call pre_update() before the actual page flip. | |
12296 | * The problem is that pre_update() caches some information about the fb | |
12297 | * object, so we want to do this only after the object is pinned. Let's | |
12298 | * be on the safe side and do this immediately before scheduling the | |
12299 | * flip. | |
12300 | */ | |
12301 | intel_fbc_pre_update(intel_crtc, intel_crtc->config, | |
12302 | to_intel_plane_state(primary->state)); | |
12303 | ||
5a21b665 DV |
12304 | if (mmio_flip) { |
12305 | INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func); | |
6277c8d0 | 12306 | queue_work(system_unbound_wq, &work->mmio_work); |
5a21b665 | 12307 | } else { |
8e637178 CW |
12308 | request = i915_gem_request_alloc(engine, engine->last_context); |
12309 | if (IS_ERR(request)) { | |
12310 | ret = PTR_ERR(request); | |
12311 | goto cleanup_unpin; | |
12312 | } | |
12313 | ||
a2bc4695 | 12314 | ret = i915_gem_request_await_object(request, obj, false); |
8e637178 CW |
12315 | if (ret) |
12316 | goto cleanup_request; | |
12317 | ||
5a21b665 DV |
12318 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, |
12319 | page_flip_flags); | |
12320 | if (ret) | |
8e637178 | 12321 | goto cleanup_request; |
5a21b665 DV |
12322 | |
12323 | intel_mark_page_flip_active(intel_crtc, work); | |
12324 | ||
8e637178 | 12325 | work->flip_queued_req = i915_gem_request_get(request); |
5a21b665 DV |
12326 | i915_add_request_no_flush(request); |
12327 | } | |
12328 | ||
92117f0b | 12329 | i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY); |
5a21b665 DV |
12330 | i915_gem_track_fb(intel_fb_obj(old_fb), obj, |
12331 | to_intel_plane(primary)->frontbuffer_bit); | |
12332 | mutex_unlock(&dev->struct_mutex); | |
12333 | ||
5748b6a1 | 12334 | intel_frontbuffer_flip_prepare(to_i915(dev), |
5a21b665 DV |
12335 | to_intel_plane(primary)->frontbuffer_bit); |
12336 | ||
12337 | trace_i915_flip_request(intel_crtc->plane, obj); | |
12338 | ||
12339 | return 0; | |
12340 | ||
8e637178 CW |
12341 | cleanup_request: |
12342 | i915_add_request_no_flush(request); | |
5a21b665 DV |
12343 | cleanup_unpin: |
12344 | intel_unpin_fb_obj(fb, crtc->primary->state->rotation); | |
12345 | cleanup_pending: | |
5a21b665 | 12346 | atomic_dec(&intel_crtc->unpin_work_count); |
ddbb271a | 12347 | unlock: |
5a21b665 DV |
12348 | mutex_unlock(&dev->struct_mutex); |
12349 | cleanup: | |
12350 | crtc->primary->fb = old_fb; | |
12351 | update_state_fb(crtc->primary); | |
12352 | ||
f0cd5182 | 12353 | i915_gem_object_put(obj); |
5a21b665 DV |
12354 | drm_framebuffer_unreference(work->old_fb); |
12355 | ||
12356 | spin_lock_irq(&dev->event_lock); | |
12357 | intel_crtc->flip_work = NULL; | |
12358 | spin_unlock_irq(&dev->event_lock); | |
12359 | ||
12360 | drm_crtc_vblank_put(crtc); | |
12361 | free_work: | |
12362 | kfree(work); | |
12363 | ||
12364 | if (ret == -EIO) { | |
12365 | struct drm_atomic_state *state; | |
12366 | struct drm_plane_state *plane_state; | |
12367 | ||
12368 | out_hang: | |
12369 | state = drm_atomic_state_alloc(dev); | |
12370 | if (!state) | |
12371 | return -ENOMEM; | |
12372 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); | |
12373 | ||
12374 | retry: | |
12375 | plane_state = drm_atomic_get_plane_state(state, primary); | |
12376 | ret = PTR_ERR_OR_ZERO(plane_state); | |
12377 | if (!ret) { | |
12378 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
12379 | ||
12380 | ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); | |
12381 | if (!ret) | |
12382 | ret = drm_atomic_commit(state); | |
12383 | } | |
12384 | ||
12385 | if (ret == -EDEADLK) { | |
12386 | drm_modeset_backoff(state->acquire_ctx); | |
12387 | drm_atomic_state_clear(state); | |
12388 | goto retry; | |
12389 | } | |
12390 | ||
0853695c | 12391 | drm_atomic_state_put(state); |
5a21b665 DV |
12392 | |
12393 | if (ret == 0 && event) { | |
12394 | spin_lock_irq(&dev->event_lock); | |
12395 | drm_crtc_send_vblank_event(crtc, event); | |
12396 | spin_unlock_irq(&dev->event_lock); | |
12397 | } | |
12398 | } | |
12399 | return ret; | |
12400 | } | |
12401 | ||
12402 | ||
12403 | /** | |
12404 | * intel_wm_need_update - Check whether watermarks need updating | |
12405 | * @plane: drm plane | |
12406 | * @state: new plane state | |
12407 | * | |
12408 | * Check current plane state versus the new one to determine whether | |
12409 | * watermarks need to be recalculated. | |
12410 | * | |
12411 | * Returns true or false. | |
12412 | */ | |
12413 | static bool intel_wm_need_update(struct drm_plane *plane, | |
12414 | struct drm_plane_state *state) | |
12415 | { | |
12416 | struct intel_plane_state *new = to_intel_plane_state(state); | |
12417 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); | |
12418 | ||
12419 | /* Update watermarks on tiling or size changes. */ | |
936e71e3 | 12420 | if (new->base.visible != cur->base.visible) |
5a21b665 DV |
12421 | return true; |
12422 | ||
12423 | if (!cur->base.fb || !new->base.fb) | |
12424 | return false; | |
12425 | ||
bae781b2 | 12426 | if (cur->base.fb->modifier != new->base.fb->modifier || |
5a21b665 | 12427 | cur->base.rotation != new->base.rotation || |
936e71e3 VS |
12428 | drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) || |
12429 | drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) || | |
12430 | drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) || | |
12431 | drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst)) | |
5a21b665 DV |
12432 | return true; |
12433 | ||
12434 | return false; | |
12435 | } | |
12436 | ||
12437 | static bool needs_scaling(struct intel_plane_state *state) | |
12438 | { | |
936e71e3 VS |
12439 | int src_w = drm_rect_width(&state->base.src) >> 16; |
12440 | int src_h = drm_rect_height(&state->base.src) >> 16; | |
12441 | int dst_w = drm_rect_width(&state->base.dst); | |
12442 | int dst_h = drm_rect_height(&state->base.dst); | |
5a21b665 DV |
12443 | |
12444 | return (src_w != dst_w || src_h != dst_h); | |
12445 | } | |
d21fbe87 | 12446 | |
da20eabd ML |
12447 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
12448 | struct drm_plane_state *plane_state) | |
12449 | { | |
ab1d3a0e | 12450 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
da20eabd ML |
12451 | struct drm_crtc *crtc = crtc_state->crtc; |
12452 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12453 | struct drm_plane *plane = plane_state->plane; | |
12454 | struct drm_device *dev = crtc->dev; | |
ed4a6a7c | 12455 | struct drm_i915_private *dev_priv = to_i915(dev); |
da20eabd ML |
12456 | struct intel_plane_state *old_plane_state = |
12457 | to_intel_plane_state(plane->state); | |
da20eabd ML |
12458 | bool mode_changed = needs_modeset(crtc_state); |
12459 | bool was_crtc_enabled = crtc->state->active; | |
12460 | bool is_crtc_enabled = crtc_state->active; | |
da20eabd ML |
12461 | bool turn_off, turn_on, visible, was_visible; |
12462 | struct drm_framebuffer *fb = plane_state->fb; | |
78108b7c | 12463 | int ret; |
da20eabd | 12464 | |
55b8f2a7 | 12465 | if (INTEL_GEN(dev_priv) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) { |
da20eabd ML |
12466 | ret = skl_update_scaler_plane( |
12467 | to_intel_crtc_state(crtc_state), | |
12468 | to_intel_plane_state(plane_state)); | |
12469 | if (ret) | |
12470 | return ret; | |
12471 | } | |
12472 | ||
936e71e3 VS |
12473 | was_visible = old_plane_state->base.visible; |
12474 | visible = to_intel_plane_state(plane_state)->base.visible; | |
da20eabd ML |
12475 | |
12476 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
12477 | was_visible = false; | |
12478 | ||
35c08f43 ML |
12479 | /* |
12480 | * Visibility is calculated as if the crtc was on, but | |
12481 | * after scaler setup everything depends on it being off | |
12482 | * when the crtc isn't active. | |
f818ffea VS |
12483 | * |
12484 | * FIXME this is wrong for watermarks. Watermarks should also | |
12485 | * be computed as if the pipe would be active. Perhaps move | |
12486 | * per-plane wm computation to the .check_plane() hook, and | |
12487 | * only combine the results from all planes in the current place? | |
35c08f43 ML |
12488 | */ |
12489 | if (!is_crtc_enabled) | |
936e71e3 | 12490 | to_intel_plane_state(plane_state)->base.visible = visible = false; |
da20eabd ML |
12491 | |
12492 | if (!was_visible && !visible) | |
12493 | return 0; | |
12494 | ||
e8861675 ML |
12495 | if (fb != old_plane_state->base.fb) |
12496 | pipe_config->fb_changed = true; | |
12497 | ||
da20eabd ML |
12498 | turn_off = was_visible && (!visible || mode_changed); |
12499 | turn_on = visible && (!was_visible || mode_changed); | |
12500 | ||
72660ce0 | 12501 | DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n", |
78108b7c VS |
12502 | intel_crtc->base.base.id, |
12503 | intel_crtc->base.name, | |
72660ce0 VS |
12504 | plane->base.id, plane->name, |
12505 | fb ? fb->base.id : -1); | |
da20eabd | 12506 | |
72660ce0 VS |
12507 | DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n", |
12508 | plane->base.id, plane->name, | |
12509 | was_visible, visible, | |
da20eabd ML |
12510 | turn_off, turn_on, mode_changed); |
12511 | ||
caed361d VS |
12512 | if (turn_on) { |
12513 | pipe_config->update_wm_pre = true; | |
12514 | ||
12515 | /* must disable cxsr around plane enable/disable */ | |
12516 | if (plane->type != DRM_PLANE_TYPE_CURSOR) | |
12517 | pipe_config->disable_cxsr = true; | |
12518 | } else if (turn_off) { | |
12519 | pipe_config->update_wm_post = true; | |
92826fcd | 12520 | |
852eb00d | 12521 | /* must disable cxsr around plane enable/disable */ |
e8861675 | 12522 | if (plane->type != DRM_PLANE_TYPE_CURSOR) |
ab1d3a0e | 12523 | pipe_config->disable_cxsr = true; |
852eb00d | 12524 | } else if (intel_wm_need_update(plane, plane_state)) { |
caed361d VS |
12525 | /* FIXME bollocks */ |
12526 | pipe_config->update_wm_pre = true; | |
12527 | pipe_config->update_wm_post = true; | |
852eb00d | 12528 | } |
da20eabd | 12529 | |
ed4a6a7c | 12530 | /* Pre-gen9 platforms need two-step watermark updates */ |
caed361d | 12531 | if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) && |
6315b5d3 | 12532 | INTEL_GEN(dev_priv) < 9 && dev_priv->display.optimize_watermarks) |
ed4a6a7c MR |
12533 | to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true; |
12534 | ||
8be6ca85 | 12535 | if (visible || was_visible) |
cd202f69 | 12536 | pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit; |
a9ff8714 | 12537 | |
31ae71fc ML |
12538 | /* |
12539 | * WaCxSRDisabledForSpriteScaling:ivb | |
12540 | * | |
12541 | * cstate->update_wm was already set above, so this flag will | |
12542 | * take effect when we commit and program watermarks. | |
12543 | */ | |
fd6b8f43 | 12544 | if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev_priv) && |
31ae71fc ML |
12545 | needs_scaling(to_intel_plane_state(plane_state)) && |
12546 | !needs_scaling(old_plane_state)) | |
12547 | pipe_config->disable_lp_wm = true; | |
d21fbe87 | 12548 | |
da20eabd ML |
12549 | return 0; |
12550 | } | |
12551 | ||
6d3a1ce7 ML |
12552 | static bool encoders_cloneable(const struct intel_encoder *a, |
12553 | const struct intel_encoder *b) | |
12554 | { | |
12555 | /* masks could be asymmetric, so check both ways */ | |
12556 | return a == b || (a->cloneable & (1 << b->type) && | |
12557 | b->cloneable & (1 << a->type)); | |
12558 | } | |
12559 | ||
12560 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
12561 | struct intel_crtc *crtc, | |
12562 | struct intel_encoder *encoder) | |
12563 | { | |
12564 | struct intel_encoder *source_encoder; | |
12565 | struct drm_connector *connector; | |
12566 | struct drm_connector_state *connector_state; | |
12567 | int i; | |
12568 | ||
12569 | for_each_connector_in_state(state, connector, connector_state, i) { | |
12570 | if (connector_state->crtc != &crtc->base) | |
12571 | continue; | |
12572 | ||
12573 | source_encoder = | |
12574 | to_intel_encoder(connector_state->best_encoder); | |
12575 | if (!encoders_cloneable(encoder, source_encoder)) | |
12576 | return false; | |
12577 | } | |
12578 | ||
12579 | return true; | |
12580 | } | |
12581 | ||
6d3a1ce7 ML |
12582 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, |
12583 | struct drm_crtc_state *crtc_state) | |
12584 | { | |
cf5a15be | 12585 | struct drm_device *dev = crtc->dev; |
fac5e23e | 12586 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d3a1ce7 | 12587 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
12588 | struct intel_crtc_state *pipe_config = |
12589 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 12590 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 12591 | int ret; |
6d3a1ce7 ML |
12592 | bool mode_changed = needs_modeset(crtc_state); |
12593 | ||
852eb00d | 12594 | if (mode_changed && !crtc_state->active) |
caed361d | 12595 | pipe_config->update_wm_post = true; |
eddfcbcd | 12596 | |
ad421372 ML |
12597 | if (mode_changed && crtc_state->enable && |
12598 | dev_priv->display.crtc_compute_clock && | |
8106ddbd | 12599 | !WARN_ON(pipe_config->shared_dpll)) { |
ad421372 ML |
12600 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, |
12601 | pipe_config); | |
12602 | if (ret) | |
12603 | return ret; | |
12604 | } | |
12605 | ||
82cf435b LL |
12606 | if (crtc_state->color_mgmt_changed) { |
12607 | ret = intel_color_check(crtc, crtc_state); | |
12608 | if (ret) | |
12609 | return ret; | |
e7852a4b LL |
12610 | |
12611 | /* | |
12612 | * Changing color management on Intel hardware is | |
12613 | * handled as part of planes update. | |
12614 | */ | |
12615 | crtc_state->planes_changed = true; | |
82cf435b LL |
12616 | } |
12617 | ||
e435d6e5 | 12618 | ret = 0; |
86c8bbbe | 12619 | if (dev_priv->display.compute_pipe_wm) { |
e3bddded | 12620 | ret = dev_priv->display.compute_pipe_wm(pipe_config); |
ed4a6a7c MR |
12621 | if (ret) { |
12622 | DRM_DEBUG_KMS("Target pipe watermarks are invalid\n"); | |
12623 | return ret; | |
12624 | } | |
12625 | } | |
12626 | ||
12627 | if (dev_priv->display.compute_intermediate_wm && | |
12628 | !to_intel_atomic_state(state)->skip_intermediate_wm) { | |
12629 | if (WARN_ON(!dev_priv->display.compute_pipe_wm)) | |
12630 | return 0; | |
12631 | ||
12632 | /* | |
12633 | * Calculate 'intermediate' watermarks that satisfy both the | |
12634 | * old state and the new state. We can program these | |
12635 | * immediately. | |
12636 | */ | |
6315b5d3 | 12637 | ret = dev_priv->display.compute_intermediate_wm(dev, |
ed4a6a7c MR |
12638 | intel_crtc, |
12639 | pipe_config); | |
12640 | if (ret) { | |
12641 | DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n"); | |
86c8bbbe | 12642 | return ret; |
ed4a6a7c | 12643 | } |
e3d5457c VS |
12644 | } else if (dev_priv->display.compute_intermediate_wm) { |
12645 | if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9) | |
12646 | pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal; | |
86c8bbbe MR |
12647 | } |
12648 | ||
6315b5d3 | 12649 | if (INTEL_GEN(dev_priv) >= 9) { |
e435d6e5 ML |
12650 | if (mode_changed) |
12651 | ret = skl_update_scaler_crtc(pipe_config); | |
12652 | ||
12653 | if (!ret) | |
12654 | ret = intel_atomic_setup_scalers(dev, intel_crtc, | |
12655 | pipe_config); | |
12656 | } | |
12657 | ||
12658 | return ret; | |
6d3a1ce7 ML |
12659 | } |
12660 | ||
65b38e0d | 12661 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 | 12662 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
5a21b665 DV |
12663 | .atomic_begin = intel_begin_crtc_commit, |
12664 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 12665 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
12666 | }; |
12667 | ||
d29b2f9d ACO |
12668 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
12669 | { | |
12670 | struct intel_connector *connector; | |
12671 | ||
12672 | for_each_intel_connector(dev, connector) { | |
8863dc7f DV |
12673 | if (connector->base.state->crtc) |
12674 | drm_connector_unreference(&connector->base); | |
12675 | ||
d29b2f9d ACO |
12676 | if (connector->base.encoder) { |
12677 | connector->base.state->best_encoder = | |
12678 | connector->base.encoder; | |
12679 | connector->base.state->crtc = | |
12680 | connector->base.encoder->crtc; | |
8863dc7f DV |
12681 | |
12682 | drm_connector_reference(&connector->base); | |
d29b2f9d ACO |
12683 | } else { |
12684 | connector->base.state->best_encoder = NULL; | |
12685 | connector->base.state->crtc = NULL; | |
12686 | } | |
12687 | } | |
12688 | } | |
12689 | ||
050f7aeb | 12690 | static void |
eba905b2 | 12691 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 12692 | struct intel_crtc_state *pipe_config) |
050f7aeb | 12693 | { |
6a2a5c5d | 12694 | const struct drm_display_info *info = &connector->base.display_info; |
050f7aeb DV |
12695 | int bpp = pipe_config->pipe_bpp; |
12696 | ||
12697 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
6a2a5c5d VS |
12698 | connector->base.base.id, |
12699 | connector->base.name); | |
050f7aeb DV |
12700 | |
12701 | /* Don't use an invalid EDID bpc value */ | |
6a2a5c5d | 12702 | if (info->bpc != 0 && info->bpc * 3 < bpp) { |
050f7aeb | 12703 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", |
6a2a5c5d VS |
12704 | bpp, info->bpc * 3); |
12705 | pipe_config->pipe_bpp = info->bpc * 3; | |
050f7aeb DV |
12706 | } |
12707 | ||
196f954e | 12708 | /* Clamp bpp to 8 on screens without EDID 1.4 */ |
6a2a5c5d | 12709 | if (info->bpc == 0 && bpp > 24) { |
196f954e MK |
12710 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", |
12711 | bpp); | |
12712 | pipe_config->pipe_bpp = 24; | |
050f7aeb DV |
12713 | } |
12714 | } | |
12715 | ||
4e53c2e0 | 12716 | static int |
050f7aeb | 12717 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 12718 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 12719 | { |
9beb5fea | 12720 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1486017f | 12721 | struct drm_atomic_state *state; |
da3ced29 ACO |
12722 | struct drm_connector *connector; |
12723 | struct drm_connector_state *connector_state; | |
1486017f | 12724 | int bpp, i; |
4e53c2e0 | 12725 | |
9beb5fea TU |
12726 | if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
12727 | IS_CHERRYVIEW(dev_priv))) | |
4e53c2e0 | 12728 | bpp = 10*3; |
9beb5fea | 12729 | else if (INTEL_GEN(dev_priv) >= 5) |
d328c9d7 DV |
12730 | bpp = 12*3; |
12731 | else | |
12732 | bpp = 8*3; | |
12733 | ||
4e53c2e0 | 12734 | |
4e53c2e0 DV |
12735 | pipe_config->pipe_bpp = bpp; |
12736 | ||
1486017f ACO |
12737 | state = pipe_config->base.state; |
12738 | ||
4e53c2e0 | 12739 | /* Clamp display bpp to EDID value */ |
da3ced29 ACO |
12740 | for_each_connector_in_state(state, connector, connector_state, i) { |
12741 | if (connector_state->crtc != &crtc->base) | |
4e53c2e0 DV |
12742 | continue; |
12743 | ||
da3ced29 ACO |
12744 | connected_sink_compute_bpp(to_intel_connector(connector), |
12745 | pipe_config); | |
4e53c2e0 DV |
12746 | } |
12747 | ||
12748 | return bpp; | |
12749 | } | |
12750 | ||
644db711 DV |
12751 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
12752 | { | |
12753 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
12754 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 12755 | mode->crtc_clock, |
644db711 DV |
12756 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
12757 | mode->crtc_hsync_end, mode->crtc_htotal, | |
12758 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
12759 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
12760 | } | |
12761 | ||
f6982332 TU |
12762 | static inline void |
12763 | intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id, | |
a4309657 | 12764 | unsigned int lane_count, struct intel_link_m_n *m_n) |
f6982332 | 12765 | { |
a4309657 TU |
12766 | DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
12767 | id, lane_count, | |
f6982332 TU |
12768 | m_n->gmch_m, m_n->gmch_n, |
12769 | m_n->link_m, m_n->link_n, m_n->tu); | |
12770 | } | |
12771 | ||
c0b03411 | 12772 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 12773 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
12774 | const char *context) |
12775 | { | |
6a60cd87 | 12776 | struct drm_device *dev = crtc->base.dev; |
4f8036a2 | 12777 | struct drm_i915_private *dev_priv = to_i915(dev); |
6a60cd87 CK |
12778 | struct drm_plane *plane; |
12779 | struct intel_plane *intel_plane; | |
12780 | struct intel_plane_state *state; | |
12781 | struct drm_framebuffer *fb; | |
12782 | ||
66766e4f TU |
12783 | DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n", |
12784 | crtc->base.base.id, crtc->base.name, context); | |
c0b03411 | 12785 | |
2c89429e TU |
12786 | DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n", |
12787 | transcoder_name(pipe_config->cpu_transcoder), | |
c0b03411 | 12788 | pipe_config->pipe_bpp, pipe_config->dither); |
a4309657 TU |
12789 | |
12790 | if (pipe_config->has_pch_encoder) | |
12791 | intel_dump_m_n_config(pipe_config, "fdi", | |
12792 | pipe_config->fdi_lanes, | |
12793 | &pipe_config->fdi_m_n); | |
f6982332 TU |
12794 | |
12795 | if (intel_crtc_has_dp_encoder(pipe_config)) { | |
a4309657 TU |
12796 | intel_dump_m_n_config(pipe_config, "dp m_n", |
12797 | pipe_config->lane_count, &pipe_config->dp_m_n); | |
d806e682 TU |
12798 | if (pipe_config->has_drrs) |
12799 | intel_dump_m_n_config(pipe_config, "dp m2_n2", | |
12800 | pipe_config->lane_count, | |
12801 | &pipe_config->dp_m2_n2); | |
f6982332 | 12802 | } |
b95af8be | 12803 | |
55072d19 | 12804 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
2c89429e | 12805 | pipe_config->has_audio, pipe_config->has_infoframe); |
55072d19 | 12806 | |
c0b03411 | 12807 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 12808 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 12809 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
12810 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
12811 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
2c89429e TU |
12812 | DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d\n", |
12813 | pipe_config->port_clock, | |
37327abd | 12814 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); |
dd2f616d TU |
12815 | |
12816 | if (INTEL_GEN(dev_priv) >= 9) | |
12817 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", | |
12818 | crtc->num_scalers, | |
12819 | pipe_config->scaler_state.scaler_users, | |
12820 | pipe_config->scaler_state.scaler_id); | |
a74f8375 TU |
12821 | |
12822 | if (HAS_GMCH_DISPLAY(dev_priv)) | |
12823 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", | |
12824 | pipe_config->gmch_pfit.control, | |
12825 | pipe_config->gmch_pfit.pgm_ratios, | |
12826 | pipe_config->gmch_pfit.lvds_border_bits); | |
12827 | else | |
12828 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", | |
12829 | pipe_config->pch_pfit.pos, | |
12830 | pipe_config->pch_pfit.size, | |
08c4d7fc | 12831 | enableddisabled(pipe_config->pch_pfit.enabled)); |
a74f8375 | 12832 | |
2c89429e TU |
12833 | DRM_DEBUG_KMS("ips: %i, double wide: %i\n", |
12834 | pipe_config->ips_enabled, pipe_config->double_wide); | |
6a60cd87 | 12835 | |
cc3f90f0 | 12836 | if (IS_GEN9_LP(dev_priv)) { |
c856052a | 12837 | DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," |
415ff0f6 | 12838 | "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " |
c8453338 | 12839 | "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", |
415ff0f6 | 12840 | pipe_config->dpll_hw_state.ebb0, |
05712c15 | 12841 | pipe_config->dpll_hw_state.ebb4, |
415ff0f6 TU |
12842 | pipe_config->dpll_hw_state.pll0, |
12843 | pipe_config->dpll_hw_state.pll1, | |
12844 | pipe_config->dpll_hw_state.pll2, | |
12845 | pipe_config->dpll_hw_state.pll3, | |
12846 | pipe_config->dpll_hw_state.pll6, | |
12847 | pipe_config->dpll_hw_state.pll8, | |
05712c15 | 12848 | pipe_config->dpll_hw_state.pll9, |
c8453338 | 12849 | pipe_config->dpll_hw_state.pll10, |
415ff0f6 | 12850 | pipe_config->dpll_hw_state.pcsdw12); |
0853723b | 12851 | } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { |
c856052a | 12852 | DRM_DEBUG_KMS("dpll_hw_state: " |
415ff0f6 | 12853 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", |
415ff0f6 TU |
12854 | pipe_config->dpll_hw_state.ctrl1, |
12855 | pipe_config->dpll_hw_state.cfgcr1, | |
12856 | pipe_config->dpll_hw_state.cfgcr2); | |
4f8036a2 | 12857 | } else if (HAS_DDI(dev_priv)) { |
c856052a | 12858 | DRM_DEBUG_KMS("dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", |
00490c22 ML |
12859 | pipe_config->dpll_hw_state.wrpll, |
12860 | pipe_config->dpll_hw_state.spll); | |
415ff0f6 TU |
12861 | } else { |
12862 | DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " | |
12863 | "fp0: 0x%x, fp1: 0x%x\n", | |
12864 | pipe_config->dpll_hw_state.dpll, | |
12865 | pipe_config->dpll_hw_state.dpll_md, | |
12866 | pipe_config->dpll_hw_state.fp0, | |
12867 | pipe_config->dpll_hw_state.fp1); | |
12868 | } | |
12869 | ||
6a60cd87 CK |
12870 | DRM_DEBUG_KMS("planes on this crtc\n"); |
12871 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
b3c11ac2 | 12872 | struct drm_format_name_buf format_name; |
6a60cd87 CK |
12873 | intel_plane = to_intel_plane(plane); |
12874 | if (intel_plane->pipe != crtc->pipe) | |
12875 | continue; | |
12876 | ||
12877 | state = to_intel_plane_state(plane->state); | |
12878 | fb = state->base.fb; | |
12879 | if (!fb) { | |
1d577e02 VS |
12880 | DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n", |
12881 | plane->base.id, plane->name, state->scaler_id); | |
6a60cd87 CK |
12882 | continue; |
12883 | } | |
12884 | ||
dd2f616d TU |
12885 | DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n", |
12886 | plane->base.id, plane->name, | |
b3c11ac2 EE |
12887 | fb->base.id, fb->width, fb->height, |
12888 | drm_get_format_name(fb->pixel_format, &format_name)); | |
dd2f616d TU |
12889 | if (INTEL_GEN(dev_priv) >= 9) |
12890 | DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n", | |
12891 | state->scaler_id, | |
12892 | state->base.src.x1 >> 16, | |
12893 | state->base.src.y1 >> 16, | |
12894 | drm_rect_width(&state->base.src) >> 16, | |
12895 | drm_rect_height(&state->base.src) >> 16, | |
12896 | state->base.dst.x1, state->base.dst.y1, | |
12897 | drm_rect_width(&state->base.dst), | |
12898 | drm_rect_height(&state->base.dst)); | |
6a60cd87 | 12899 | } |
c0b03411 DV |
12900 | } |
12901 | ||
5448a00d | 12902 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 12903 | { |
5448a00d | 12904 | struct drm_device *dev = state->dev; |
da3ced29 | 12905 | struct drm_connector *connector; |
00f0b378 | 12906 | unsigned int used_ports = 0; |
477321e0 | 12907 | unsigned int used_mst_ports = 0; |
00f0b378 VS |
12908 | |
12909 | /* | |
12910 | * Walk the connector list instead of the encoder | |
12911 | * list to detect the problem on ddi platforms | |
12912 | * where there's just one encoder per digital port. | |
12913 | */ | |
0bff4858 VS |
12914 | drm_for_each_connector(connector, dev) { |
12915 | struct drm_connector_state *connector_state; | |
12916 | struct intel_encoder *encoder; | |
12917 | ||
12918 | connector_state = drm_atomic_get_existing_connector_state(state, connector); | |
12919 | if (!connector_state) | |
12920 | connector_state = connector->state; | |
12921 | ||
5448a00d | 12922 | if (!connector_state->best_encoder) |
00f0b378 VS |
12923 | continue; |
12924 | ||
5448a00d ACO |
12925 | encoder = to_intel_encoder(connector_state->best_encoder); |
12926 | ||
12927 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
12928 | |
12929 | switch (encoder->type) { | |
12930 | unsigned int port_mask; | |
12931 | case INTEL_OUTPUT_UNKNOWN: | |
4f8036a2 | 12932 | if (WARN_ON(!HAS_DDI(to_i915(dev)))) |
00f0b378 | 12933 | break; |
cca0502b | 12934 | case INTEL_OUTPUT_DP: |
00f0b378 VS |
12935 | case INTEL_OUTPUT_HDMI: |
12936 | case INTEL_OUTPUT_EDP: | |
12937 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
12938 | ||
12939 | /* the same port mustn't appear more than once */ | |
12940 | if (used_ports & port_mask) | |
12941 | return false; | |
12942 | ||
12943 | used_ports |= port_mask; | |
477321e0 VS |
12944 | break; |
12945 | case INTEL_OUTPUT_DP_MST: | |
12946 | used_mst_ports |= | |
12947 | 1 << enc_to_mst(&encoder->base)->primary->port; | |
12948 | break; | |
00f0b378 VS |
12949 | default: |
12950 | break; | |
12951 | } | |
12952 | } | |
12953 | ||
477321e0 VS |
12954 | /* can't mix MST and SST/HDMI on the same port */ |
12955 | if (used_ports & used_mst_ports) | |
12956 | return false; | |
12957 | ||
00f0b378 VS |
12958 | return true; |
12959 | } | |
12960 | ||
83a57153 ACO |
12961 | static void |
12962 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
12963 | { | |
12964 | struct drm_crtc_state tmp_state; | |
663a3640 | 12965 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 | 12966 | struct intel_dpll_hw_state dpll_hw_state; |
8106ddbd | 12967 | struct intel_shared_dpll *shared_dpll; |
c4e2d043 | 12968 | bool force_thru; |
83a57153 | 12969 | |
7546a384 ACO |
12970 | /* FIXME: before the switch to atomic started, a new pipe_config was |
12971 | * kzalloc'd. Code that depends on any field being zero should be | |
12972 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
12973 | * only fields that are know to not cause problems are preserved. */ | |
12974 | ||
83a57153 | 12975 | tmp_state = crtc_state->base; |
663a3640 | 12976 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
12977 | shared_dpll = crtc_state->shared_dpll; |
12978 | dpll_hw_state = crtc_state->dpll_hw_state; | |
c4e2d043 | 12979 | force_thru = crtc_state->pch_pfit.force_thru; |
4978cc93 | 12980 | |
83a57153 | 12981 | memset(crtc_state, 0, sizeof *crtc_state); |
4978cc93 | 12982 | |
83a57153 | 12983 | crtc_state->base = tmp_state; |
663a3640 | 12984 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
12985 | crtc_state->shared_dpll = shared_dpll; |
12986 | crtc_state->dpll_hw_state = dpll_hw_state; | |
c4e2d043 | 12987 | crtc_state->pch_pfit.force_thru = force_thru; |
83a57153 ACO |
12988 | } |
12989 | ||
548ee15b | 12990 | static int |
b8cecdf5 | 12991 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 12992 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 12993 | { |
b359283a | 12994 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 12995 | struct intel_encoder *encoder; |
da3ced29 | 12996 | struct drm_connector *connector; |
0b901879 | 12997 | struct drm_connector_state *connector_state; |
d328c9d7 | 12998 | int base_bpp, ret = -EINVAL; |
0b901879 | 12999 | int i; |
e29c22c0 | 13000 | bool retry = true; |
ee7b9f93 | 13001 | |
83a57153 | 13002 | clear_intel_crtc_state(pipe_config); |
7758a113 | 13003 | |
e143a21c DV |
13004 | pipe_config->cpu_transcoder = |
13005 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 13006 | |
2960bc9c ID |
13007 | /* |
13008 | * Sanitize sync polarity flags based on requested ones. If neither | |
13009 | * positive or negative polarity is requested, treat this as meaning | |
13010 | * negative polarity. | |
13011 | */ | |
2d112de7 | 13012 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 13013 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 13014 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 13015 | |
2d112de7 | 13016 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 13017 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 13018 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 13019 | |
d328c9d7 DV |
13020 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
13021 | pipe_config); | |
13022 | if (base_bpp < 0) | |
4e53c2e0 DV |
13023 | goto fail; |
13024 | ||
e41a56be VS |
13025 | /* |
13026 | * Determine the real pipe dimensions. Note that stereo modes can | |
13027 | * increase the actual pipe size due to the frame doubling and | |
13028 | * insertion of additional space for blanks between the frame. This | |
13029 | * is stored in the crtc timings. We use the requested mode to do this | |
13030 | * computation to clearly distinguish it from the adjusted mode, which | |
13031 | * can be changed by the connectors in the below retry loop. | |
13032 | */ | |
2d112de7 | 13033 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
13034 | &pipe_config->pipe_src_w, |
13035 | &pipe_config->pipe_src_h); | |
e41a56be | 13036 | |
253c84c8 VS |
13037 | for_each_connector_in_state(state, connector, connector_state, i) { |
13038 | if (connector_state->crtc != crtc) | |
13039 | continue; | |
13040 | ||
13041 | encoder = to_intel_encoder(connector_state->best_encoder); | |
13042 | ||
e25148d0 VS |
13043 | if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) { |
13044 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
13045 | goto fail; | |
13046 | } | |
13047 | ||
253c84c8 VS |
13048 | /* |
13049 | * Determine output_types before calling the .compute_config() | |
13050 | * hooks so that the hooks can use this information safely. | |
13051 | */ | |
13052 | pipe_config->output_types |= 1 << encoder->type; | |
13053 | } | |
13054 | ||
e29c22c0 | 13055 | encoder_retry: |
ef1b460d | 13056 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 13057 | pipe_config->port_clock = 0; |
ef1b460d | 13058 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 13059 | |
135c81b8 | 13060 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
13061 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
13062 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 13063 | |
7758a113 DV |
13064 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
13065 | * adjust it according to limitations or connector properties, and also | |
13066 | * a chance to reject the mode entirely. | |
47f1c6c9 | 13067 | */ |
da3ced29 | 13068 | for_each_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 13069 | if (connector_state->crtc != crtc) |
7758a113 | 13070 | continue; |
7ae89233 | 13071 | |
0b901879 ACO |
13072 | encoder = to_intel_encoder(connector_state->best_encoder); |
13073 | ||
0a478c27 | 13074 | if (!(encoder->compute_config(encoder, pipe_config, connector_state))) { |
efea6e8e | 13075 | DRM_DEBUG_KMS("Encoder config failure\n"); |
7758a113 DV |
13076 | goto fail; |
13077 | } | |
ee7b9f93 | 13078 | } |
47f1c6c9 | 13079 | |
ff9a6750 DV |
13080 | /* Set default port clock if not overwritten by the encoder. Needs to be |
13081 | * done afterwards in case the encoder adjusts the mode. */ | |
13082 | if (!pipe_config->port_clock) | |
2d112de7 | 13083 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 13084 | * pipe_config->pixel_multiplier; |
ff9a6750 | 13085 | |
a43f6e0f | 13086 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 13087 | if (ret < 0) { |
7758a113 DV |
13088 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
13089 | goto fail; | |
ee7b9f93 | 13090 | } |
e29c22c0 DV |
13091 | |
13092 | if (ret == RETRY) { | |
13093 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
13094 | ret = -EINVAL; | |
13095 | goto fail; | |
13096 | } | |
13097 | ||
13098 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
13099 | retry = false; | |
13100 | goto encoder_retry; | |
13101 | } | |
13102 | ||
e8fa4270 DV |
13103 | /* Dithering seems to not pass-through bits correctly when it should, so |
13104 | * only enable it on 6bpc panels. */ | |
13105 | pipe_config->dither = pipe_config->pipe_bpp == 6*3; | |
62f0ace5 | 13106 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 13107 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 13108 | |
7758a113 | 13109 | fail: |
548ee15b | 13110 | return ret; |
ee7b9f93 | 13111 | } |
47f1c6c9 | 13112 | |
ea9d758d | 13113 | static void |
4740b0f2 | 13114 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 13115 | { |
0a9ab303 ACO |
13116 | struct drm_crtc *crtc; |
13117 | struct drm_crtc_state *crtc_state; | |
8a75d157 | 13118 | int i; |
ea9d758d | 13119 | |
7668851f | 13120 | /* Double check state. */ |
8a75d157 | 13121 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
3cb480bc | 13122 | to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); |
fc467a22 ML |
13123 | |
13124 | /* Update hwmode for vblank functions */ | |
13125 | if (crtc->state->active) | |
13126 | crtc->hwmode = crtc->state->adjusted_mode; | |
13127 | else | |
13128 | crtc->hwmode.crtc_clock = 0; | |
61067a5e ML |
13129 | |
13130 | /* | |
13131 | * Update legacy state to satisfy fbc code. This can | |
13132 | * be removed when fbc uses the atomic state. | |
13133 | */ | |
13134 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
13135 | struct drm_plane_state *plane_state = crtc->primary->state; | |
13136 | ||
13137 | crtc->primary->fb = plane_state->fb; | |
13138 | crtc->x = plane_state->src_x >> 16; | |
13139 | crtc->y = plane_state->src_y >> 16; | |
13140 | } | |
ea9d758d | 13141 | } |
ea9d758d DV |
13142 | } |
13143 | ||
3bd26263 | 13144 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 13145 | { |
3bd26263 | 13146 | int diff; |
f1f644dc JB |
13147 | |
13148 | if (clock1 == clock2) | |
13149 | return true; | |
13150 | ||
13151 | if (!clock1 || !clock2) | |
13152 | return false; | |
13153 | ||
13154 | diff = abs(clock1 - clock2); | |
13155 | ||
13156 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
13157 | return true; | |
13158 | ||
13159 | return false; | |
13160 | } | |
13161 | ||
cfb23ed6 ML |
13162 | static bool |
13163 | intel_compare_m_n(unsigned int m, unsigned int n, | |
13164 | unsigned int m2, unsigned int n2, | |
13165 | bool exact) | |
13166 | { | |
13167 | if (m == m2 && n == n2) | |
13168 | return true; | |
13169 | ||
13170 | if (exact || !m || !n || !m2 || !n2) | |
13171 | return false; | |
13172 | ||
13173 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
13174 | ||
31d10b57 ML |
13175 | if (n > n2) { |
13176 | while (n > n2) { | |
cfb23ed6 ML |
13177 | m2 <<= 1; |
13178 | n2 <<= 1; | |
13179 | } | |
31d10b57 ML |
13180 | } else if (n < n2) { |
13181 | while (n < n2) { | |
cfb23ed6 ML |
13182 | m <<= 1; |
13183 | n <<= 1; | |
13184 | } | |
13185 | } | |
13186 | ||
31d10b57 ML |
13187 | if (n != n2) |
13188 | return false; | |
13189 | ||
13190 | return intel_fuzzy_clock_check(m, m2); | |
cfb23ed6 ML |
13191 | } |
13192 | ||
13193 | static bool | |
13194 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
13195 | struct intel_link_m_n *m2_n2, | |
13196 | bool adjust) | |
13197 | { | |
13198 | if (m_n->tu == m2_n2->tu && | |
13199 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
13200 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
13201 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
13202 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
13203 | if (adjust) | |
13204 | *m2_n2 = *m_n; | |
13205 | ||
13206 | return true; | |
13207 | } | |
13208 | ||
13209 | return false; | |
13210 | } | |
13211 | ||
0e8ffe1b | 13212 | static bool |
6315b5d3 | 13213 | intel_pipe_config_compare(struct drm_i915_private *dev_priv, |
5cec258b | 13214 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
13215 | struct intel_crtc_state *pipe_config, |
13216 | bool adjust) | |
0e8ffe1b | 13217 | { |
cfb23ed6 ML |
13218 | bool ret = true; |
13219 | ||
13220 | #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \ | |
13221 | do { \ | |
13222 | if (!adjust) \ | |
13223 | DRM_ERROR(fmt, ##__VA_ARGS__); \ | |
13224 | else \ | |
13225 | DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \ | |
13226 | } while (0) | |
13227 | ||
66e985c0 DV |
13228 | #define PIPE_CONF_CHECK_X(name) \ |
13229 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 13230 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
66e985c0 DV |
13231 | "(expected 0x%08x, found 0x%08x)\n", \ |
13232 | current_config->name, \ | |
13233 | pipe_config->name); \ | |
cfb23ed6 | 13234 | ret = false; \ |
66e985c0 DV |
13235 | } |
13236 | ||
08a24034 DV |
13237 | #define PIPE_CONF_CHECK_I(name) \ |
13238 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 13239 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
08a24034 DV |
13240 | "(expected %i, found %i)\n", \ |
13241 | current_config->name, \ | |
13242 | pipe_config->name); \ | |
cfb23ed6 ML |
13243 | ret = false; \ |
13244 | } | |
13245 | ||
8106ddbd ACO |
13246 | #define PIPE_CONF_CHECK_P(name) \ |
13247 | if (current_config->name != pipe_config->name) { \ | |
13248 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
13249 | "(expected %p, found %p)\n", \ | |
13250 | current_config->name, \ | |
13251 | pipe_config->name); \ | |
13252 | ret = false; \ | |
13253 | } | |
13254 | ||
cfb23ed6 ML |
13255 | #define PIPE_CONF_CHECK_M_N(name) \ |
13256 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
13257 | &pipe_config->name,\ | |
13258 | adjust)) { \ | |
13259 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
13260 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
13261 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
13262 | current_config->name.tu, \ | |
13263 | current_config->name.gmch_m, \ | |
13264 | current_config->name.gmch_n, \ | |
13265 | current_config->name.link_m, \ | |
13266 | current_config->name.link_n, \ | |
13267 | pipe_config->name.tu, \ | |
13268 | pipe_config->name.gmch_m, \ | |
13269 | pipe_config->name.gmch_n, \ | |
13270 | pipe_config->name.link_m, \ | |
13271 | pipe_config->name.link_n); \ | |
13272 | ret = false; \ | |
13273 | } | |
13274 | ||
55c561a7 DV |
13275 | /* This is required for BDW+ where there is only one set of registers for |
13276 | * switching between high and low RR. | |
13277 | * This macro can be used whenever a comparison has to be made between one | |
13278 | * hw state and multiple sw state variables. | |
13279 | */ | |
cfb23ed6 ML |
13280 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ |
13281 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
13282 | &pipe_config->name, adjust) && \ | |
13283 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
13284 | &pipe_config->name, adjust)) { \ | |
13285 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
13286 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
13287 | "or tu %i gmch %i/%i link %i/%i, " \ | |
13288 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
13289 | current_config->name.tu, \ | |
13290 | current_config->name.gmch_m, \ | |
13291 | current_config->name.gmch_n, \ | |
13292 | current_config->name.link_m, \ | |
13293 | current_config->name.link_n, \ | |
13294 | current_config->alt_name.tu, \ | |
13295 | current_config->alt_name.gmch_m, \ | |
13296 | current_config->alt_name.gmch_n, \ | |
13297 | current_config->alt_name.link_m, \ | |
13298 | current_config->alt_name.link_n, \ | |
13299 | pipe_config->name.tu, \ | |
13300 | pipe_config->name.gmch_m, \ | |
13301 | pipe_config->name.gmch_n, \ | |
13302 | pipe_config->name.link_m, \ | |
13303 | pipe_config->name.link_n); \ | |
13304 | ret = false; \ | |
88adfff1 DV |
13305 | } |
13306 | ||
1bd1bd80 DV |
13307 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
13308 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
cfb23ed6 | 13309 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
13310 | "(expected %i, found %i)\n", \ |
13311 | current_config->name & (mask), \ | |
13312 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 13313 | ret = false; \ |
1bd1bd80 DV |
13314 | } |
13315 | ||
5e550656 VS |
13316 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
13317 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
cfb23ed6 | 13318 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
5e550656 VS |
13319 | "(expected %i, found %i)\n", \ |
13320 | current_config->name, \ | |
13321 | pipe_config->name); \ | |
cfb23ed6 | 13322 | ret = false; \ |
5e550656 VS |
13323 | } |
13324 | ||
bb760063 DV |
13325 | #define PIPE_CONF_QUIRK(quirk) \ |
13326 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
13327 | ||
eccb140b DV |
13328 | PIPE_CONF_CHECK_I(cpu_transcoder); |
13329 | ||
08a24034 DV |
13330 | PIPE_CONF_CHECK_I(has_pch_encoder); |
13331 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 13332 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 13333 | |
90a6b7b0 | 13334 | PIPE_CONF_CHECK_I(lane_count); |
95a7a2ae | 13335 | PIPE_CONF_CHECK_X(lane_lat_optim_mask); |
b95af8be | 13336 | |
6315b5d3 | 13337 | if (INTEL_GEN(dev_priv) < 8) { |
cfb23ed6 ML |
13338 | PIPE_CONF_CHECK_M_N(dp_m_n); |
13339 | ||
cfb23ed6 ML |
13340 | if (current_config->has_drrs) |
13341 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
13342 | } else | |
13343 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 13344 | |
253c84c8 | 13345 | PIPE_CONF_CHECK_X(output_types); |
a65347ba | 13346 | |
2d112de7 ACO |
13347 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
13348 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
13349 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
13350 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
13351 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
13352 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 13353 | |
2d112de7 ACO |
13354 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
13355 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
13356 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
13357 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
13358 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
13359 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 13360 | |
c93f54cf | 13361 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 13362 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
772c2a51 | 13363 | if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || |
920a14b2 | 13364 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
b5a9fa09 | 13365 | PIPE_CONF_CHECK_I(limited_color_range); |
e43823ec | 13366 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 13367 | |
9ed109a7 DV |
13368 | PIPE_CONF_CHECK_I(has_audio); |
13369 | ||
2d112de7 | 13370 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
13371 | DRM_MODE_FLAG_INTERLACE); |
13372 | ||
bb760063 | 13373 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 13374 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 13375 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 13376 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 13377 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 13378 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 13379 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 13380 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
13381 | DRM_MODE_FLAG_NVSYNC); |
13382 | } | |
045ac3b5 | 13383 | |
333b8ca8 | 13384 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a | 13385 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
6315b5d3 | 13386 | if (INTEL_GEN(dev_priv) < 4) |
7f7d8dd6 | 13387 | PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); |
333b8ca8 | 13388 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 13389 | |
bfd16b2a ML |
13390 | if (!adjust) { |
13391 | PIPE_CONF_CHECK_I(pipe_src_w); | |
13392 | PIPE_CONF_CHECK_I(pipe_src_h); | |
13393 | ||
13394 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
13395 | if (current_config->pch_pfit.enabled) { | |
13396 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
13397 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
13398 | } | |
2fa2fe9a | 13399 | |
7aefe2b5 ML |
13400 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
13401 | } | |
a1b2278e | 13402 | |
e59150dc | 13403 | /* BDW+ don't expose a synchronous way to read the state */ |
772c2a51 | 13404 | if (IS_HASWELL(dev_priv)) |
e59150dc | 13405 | PIPE_CONF_CHECK_I(ips_enabled); |
42db64ef | 13406 | |
282740f7 VS |
13407 | PIPE_CONF_CHECK_I(double_wide); |
13408 | ||
8106ddbd | 13409 | PIPE_CONF_CHECK_P(shared_dpll); |
66e985c0 | 13410 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 13411 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
13412 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
13413 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 13414 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
00490c22 | 13415 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
3f4cd19f DL |
13416 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
13417 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
13418 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 13419 | |
47eacbab VS |
13420 | PIPE_CONF_CHECK_X(dsi_pll.ctrl); |
13421 | PIPE_CONF_CHECK_X(dsi_pll.div); | |
13422 | ||
9beb5fea | 13423 | if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) |
42571aef VS |
13424 | PIPE_CONF_CHECK_I(pipe_bpp); |
13425 | ||
2d112de7 | 13426 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 13427 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 13428 | |
66e985c0 | 13429 | #undef PIPE_CONF_CHECK_X |
08a24034 | 13430 | #undef PIPE_CONF_CHECK_I |
8106ddbd | 13431 | #undef PIPE_CONF_CHECK_P |
1bd1bd80 | 13432 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 13433 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 13434 | #undef PIPE_CONF_QUIRK |
cfb23ed6 | 13435 | #undef INTEL_ERR_OR_DBG_KMS |
88adfff1 | 13436 | |
cfb23ed6 | 13437 | return ret; |
0e8ffe1b DV |
13438 | } |
13439 | ||
e3b247da VS |
13440 | static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, |
13441 | const struct intel_crtc_state *pipe_config) | |
13442 | { | |
13443 | if (pipe_config->has_pch_encoder) { | |
21a727b3 | 13444 | int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
e3b247da VS |
13445 | &pipe_config->fdi_m_n); |
13446 | int dotclock = pipe_config->base.adjusted_mode.crtc_clock; | |
13447 | ||
13448 | /* | |
13449 | * FDI already provided one idea for the dotclock. | |
13450 | * Yell if the encoder disagrees. | |
13451 | */ | |
13452 | WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock), | |
13453 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", | |
13454 | fdi_dotclock, dotclock); | |
13455 | } | |
13456 | } | |
13457 | ||
c0ead703 ML |
13458 | static void verify_wm_state(struct drm_crtc *crtc, |
13459 | struct drm_crtc_state *new_state) | |
08db6652 | 13460 | { |
6315b5d3 | 13461 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
08db6652 | 13462 | struct skl_ddb_allocation hw_ddb, *sw_ddb; |
3de8a14c | 13463 | struct skl_pipe_wm hw_wm, *sw_wm; |
13464 | struct skl_plane_wm *hw_plane_wm, *sw_plane_wm; | |
13465 | struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry; | |
e7c84544 ML |
13466 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13467 | const enum pipe pipe = intel_crtc->pipe; | |
3de8a14c | 13468 | int plane, level, max_level = ilk_wm_max_level(dev_priv); |
08db6652 | 13469 | |
6315b5d3 | 13470 | if (INTEL_GEN(dev_priv) < 9 || !new_state->active) |
08db6652 DL |
13471 | return; |
13472 | ||
3de8a14c | 13473 | skl_pipe_wm_get_hw_state(crtc, &hw_wm); |
03af79e0 | 13474 | sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal; |
3de8a14c | 13475 | |
08db6652 DL |
13476 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); |
13477 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
13478 | ||
e7c84544 | 13479 | /* planes */ |
8b364b41 | 13480 | for_each_universal_plane(dev_priv, pipe, plane) { |
3de8a14c | 13481 | hw_plane_wm = &hw_wm.planes[plane]; |
13482 | sw_plane_wm = &sw_wm->planes[plane]; | |
08db6652 | 13483 | |
3de8a14c | 13484 | /* Watermarks */ |
13485 | for (level = 0; level <= max_level; level++) { | |
13486 | if (skl_wm_level_equals(&hw_plane_wm->wm[level], | |
13487 | &sw_plane_wm->wm[level])) | |
13488 | continue; | |
13489 | ||
13490 | DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
13491 | pipe_name(pipe), plane + 1, level, | |
13492 | sw_plane_wm->wm[level].plane_en, | |
13493 | sw_plane_wm->wm[level].plane_res_b, | |
13494 | sw_plane_wm->wm[level].plane_res_l, | |
13495 | hw_plane_wm->wm[level].plane_en, | |
13496 | hw_plane_wm->wm[level].plane_res_b, | |
13497 | hw_plane_wm->wm[level].plane_res_l); | |
13498 | } | |
08db6652 | 13499 | |
3de8a14c | 13500 | if (!skl_wm_level_equals(&hw_plane_wm->trans_wm, |
13501 | &sw_plane_wm->trans_wm)) { | |
13502 | DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
13503 | pipe_name(pipe), plane + 1, | |
13504 | sw_plane_wm->trans_wm.plane_en, | |
13505 | sw_plane_wm->trans_wm.plane_res_b, | |
13506 | sw_plane_wm->trans_wm.plane_res_l, | |
13507 | hw_plane_wm->trans_wm.plane_en, | |
13508 | hw_plane_wm->trans_wm.plane_res_b, | |
13509 | hw_plane_wm->trans_wm.plane_res_l); | |
13510 | } | |
13511 | ||
13512 | /* DDB */ | |
13513 | hw_ddb_entry = &hw_ddb.plane[pipe][plane]; | |
13514 | sw_ddb_entry = &sw_ddb->plane[pipe][plane]; | |
13515 | ||
13516 | if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { | |
faccd994 | 13517 | DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n", |
3de8a14c | 13518 | pipe_name(pipe), plane + 1, |
13519 | sw_ddb_entry->start, sw_ddb_entry->end, | |
13520 | hw_ddb_entry->start, hw_ddb_entry->end); | |
13521 | } | |
e7c84544 | 13522 | } |
08db6652 | 13523 | |
27082493 L |
13524 | /* |
13525 | * cursor | |
13526 | * If the cursor plane isn't active, we may not have updated it's ddb | |
13527 | * allocation. In that case since the ddb allocation will be updated | |
13528 | * once the plane becomes visible, we can skip this check | |
13529 | */ | |
13530 | if (intel_crtc->cursor_addr) { | |
3de8a14c | 13531 | hw_plane_wm = &hw_wm.planes[PLANE_CURSOR]; |
13532 | sw_plane_wm = &sw_wm->planes[PLANE_CURSOR]; | |
13533 | ||
13534 | /* Watermarks */ | |
13535 | for (level = 0; level <= max_level; level++) { | |
13536 | if (skl_wm_level_equals(&hw_plane_wm->wm[level], | |
13537 | &sw_plane_wm->wm[level])) | |
13538 | continue; | |
13539 | ||
13540 | DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
13541 | pipe_name(pipe), level, | |
13542 | sw_plane_wm->wm[level].plane_en, | |
13543 | sw_plane_wm->wm[level].plane_res_b, | |
13544 | sw_plane_wm->wm[level].plane_res_l, | |
13545 | hw_plane_wm->wm[level].plane_en, | |
13546 | hw_plane_wm->wm[level].plane_res_b, | |
13547 | hw_plane_wm->wm[level].plane_res_l); | |
13548 | } | |
13549 | ||
13550 | if (!skl_wm_level_equals(&hw_plane_wm->trans_wm, | |
13551 | &sw_plane_wm->trans_wm)) { | |
13552 | DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
13553 | pipe_name(pipe), | |
13554 | sw_plane_wm->trans_wm.plane_en, | |
13555 | sw_plane_wm->trans_wm.plane_res_b, | |
13556 | sw_plane_wm->trans_wm.plane_res_l, | |
13557 | hw_plane_wm->trans_wm.plane_en, | |
13558 | hw_plane_wm->trans_wm.plane_res_b, | |
13559 | hw_plane_wm->trans_wm.plane_res_l); | |
13560 | } | |
13561 | ||
13562 | /* DDB */ | |
13563 | hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; | |
13564 | sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; | |
27082493 | 13565 | |
3de8a14c | 13566 | if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { |
faccd994 | 13567 | DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n", |
27082493 | 13568 | pipe_name(pipe), |
3de8a14c | 13569 | sw_ddb_entry->start, sw_ddb_entry->end, |
13570 | hw_ddb_entry->start, hw_ddb_entry->end); | |
27082493 | 13571 | } |
08db6652 DL |
13572 | } |
13573 | } | |
13574 | ||
91d1b4bd | 13575 | static void |
677100ce ML |
13576 | verify_connector_state(struct drm_device *dev, |
13577 | struct drm_atomic_state *state, | |
13578 | struct drm_crtc *crtc) | |
8af6cf88 | 13579 | { |
35dd3c64 | 13580 | struct drm_connector *connector; |
677100ce ML |
13581 | struct drm_connector_state *old_conn_state; |
13582 | int i; | |
8af6cf88 | 13583 | |
677100ce | 13584 | for_each_connector_in_state(state, connector, old_conn_state, i) { |
35dd3c64 ML |
13585 | struct drm_encoder *encoder = connector->encoder; |
13586 | struct drm_connector_state *state = connector->state; | |
ad3c558f | 13587 | |
e7c84544 ML |
13588 | if (state->crtc != crtc) |
13589 | continue; | |
13590 | ||
5a21b665 | 13591 | intel_connector_verify_state(to_intel_connector(connector)); |
8af6cf88 | 13592 | |
ad3c558f | 13593 | I915_STATE_WARN(state->best_encoder != encoder, |
35dd3c64 | 13594 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 13595 | } |
91d1b4bd DV |
13596 | } |
13597 | ||
13598 | static void | |
c0ead703 | 13599 | verify_encoder_state(struct drm_device *dev) |
91d1b4bd DV |
13600 | { |
13601 | struct intel_encoder *encoder; | |
13602 | struct intel_connector *connector; | |
8af6cf88 | 13603 | |
b2784e15 | 13604 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 | 13605 | bool enabled = false; |
4d20cd86 | 13606 | enum pipe pipe; |
8af6cf88 DV |
13607 | |
13608 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
13609 | encoder->base.base.id, | |
8e329a03 | 13610 | encoder->base.name); |
8af6cf88 | 13611 | |
3a3371ff | 13612 | for_each_intel_connector(dev, connector) { |
4d20cd86 | 13613 | if (connector->base.state->best_encoder != &encoder->base) |
8af6cf88 DV |
13614 | continue; |
13615 | enabled = true; | |
ad3c558f ML |
13616 | |
13617 | I915_STATE_WARN(connector->base.state->crtc != | |
13618 | encoder->base.crtc, | |
13619 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 13620 | } |
0e32b39c | 13621 | |
e2c719b7 | 13622 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
13623 | "encoder's enabled state mismatch " |
13624 | "(expected %i, found %i)\n", | |
13625 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
13626 | |
13627 | if (!encoder->base.crtc) { | |
4d20cd86 | 13628 | bool active; |
7c60d198 | 13629 | |
4d20cd86 ML |
13630 | active = encoder->get_hw_state(encoder, &pipe); |
13631 | I915_STATE_WARN(active, | |
13632 | "encoder detached but still enabled on pipe %c.\n", | |
13633 | pipe_name(pipe)); | |
7c60d198 | 13634 | } |
8af6cf88 | 13635 | } |
91d1b4bd DV |
13636 | } |
13637 | ||
13638 | static void | |
c0ead703 ML |
13639 | verify_crtc_state(struct drm_crtc *crtc, |
13640 | struct drm_crtc_state *old_crtc_state, | |
13641 | struct drm_crtc_state *new_crtc_state) | |
91d1b4bd | 13642 | { |
e7c84544 | 13643 | struct drm_device *dev = crtc->dev; |
fac5e23e | 13644 | struct drm_i915_private *dev_priv = to_i915(dev); |
91d1b4bd | 13645 | struct intel_encoder *encoder; |
e7c84544 ML |
13646 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13647 | struct intel_crtc_state *pipe_config, *sw_config; | |
13648 | struct drm_atomic_state *old_state; | |
13649 | bool active; | |
045ac3b5 | 13650 | |
e7c84544 | 13651 | old_state = old_crtc_state->state; |
ec2dc6a0 | 13652 | __drm_atomic_helper_crtc_destroy_state(old_crtc_state); |
e7c84544 ML |
13653 | pipe_config = to_intel_crtc_state(old_crtc_state); |
13654 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
13655 | pipe_config->base.crtc = crtc; | |
13656 | pipe_config->base.state = old_state; | |
8af6cf88 | 13657 | |
78108b7c | 13658 | DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name); |
8af6cf88 | 13659 | |
e7c84544 | 13660 | active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config); |
d62cf62a | 13661 | |
e7c84544 ML |
13662 | /* hw state is inconsistent with the pipe quirk */ |
13663 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
13664 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
13665 | active = new_crtc_state->active; | |
6c49f241 | 13666 | |
e7c84544 ML |
13667 | I915_STATE_WARN(new_crtc_state->active != active, |
13668 | "crtc active state doesn't match with hw state " | |
13669 | "(expected %i, found %i)\n", new_crtc_state->active, active); | |
0e8ffe1b | 13670 | |
e7c84544 ML |
13671 | I915_STATE_WARN(intel_crtc->active != new_crtc_state->active, |
13672 | "transitional active state does not match atomic hw state " | |
13673 | "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active); | |
4d20cd86 | 13674 | |
e7c84544 ML |
13675 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
13676 | enum pipe pipe; | |
4d20cd86 | 13677 | |
e7c84544 ML |
13678 | active = encoder->get_hw_state(encoder, &pipe); |
13679 | I915_STATE_WARN(active != new_crtc_state->active, | |
13680 | "[ENCODER:%i] active %i with crtc active %i\n", | |
13681 | encoder->base.base.id, active, new_crtc_state->active); | |
4d20cd86 | 13682 | |
e7c84544 ML |
13683 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, |
13684 | "Encoder connected to wrong pipe %c\n", | |
13685 | pipe_name(pipe)); | |
4d20cd86 | 13686 | |
253c84c8 VS |
13687 | if (active) { |
13688 | pipe_config->output_types |= 1 << encoder->type; | |
e7c84544 | 13689 | encoder->get_config(encoder, pipe_config); |
253c84c8 | 13690 | } |
e7c84544 | 13691 | } |
53d9f4e9 | 13692 | |
e7c84544 ML |
13693 | if (!new_crtc_state->active) |
13694 | return; | |
cfb23ed6 | 13695 | |
e7c84544 | 13696 | intel_pipe_config_sanity_check(dev_priv, pipe_config); |
e3b247da | 13697 | |
e7c84544 | 13698 | sw_config = to_intel_crtc_state(crtc->state); |
6315b5d3 | 13699 | if (!intel_pipe_config_compare(dev_priv, sw_config, |
e7c84544 ML |
13700 | pipe_config, false)) { |
13701 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); | |
13702 | intel_dump_pipe_config(intel_crtc, pipe_config, | |
13703 | "[hw state]"); | |
13704 | intel_dump_pipe_config(intel_crtc, sw_config, | |
13705 | "[sw state]"); | |
8af6cf88 DV |
13706 | } |
13707 | } | |
13708 | ||
91d1b4bd | 13709 | static void |
c0ead703 ML |
13710 | verify_single_dpll_state(struct drm_i915_private *dev_priv, |
13711 | struct intel_shared_dpll *pll, | |
13712 | struct drm_crtc *crtc, | |
13713 | struct drm_crtc_state *new_state) | |
91d1b4bd | 13714 | { |
91d1b4bd | 13715 | struct intel_dpll_hw_state dpll_hw_state; |
e7c84544 ML |
13716 | unsigned crtc_mask; |
13717 | bool active; | |
5358901f | 13718 | |
e7c84544 | 13719 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); |
5358901f | 13720 | |
e7c84544 | 13721 | DRM_DEBUG_KMS("%s\n", pll->name); |
5358901f | 13722 | |
e7c84544 | 13723 | active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state); |
5358901f | 13724 | |
e7c84544 ML |
13725 | if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) { |
13726 | I915_STATE_WARN(!pll->on && pll->active_mask, | |
13727 | "pll in active use but not on in sw tracking\n"); | |
13728 | I915_STATE_WARN(pll->on && !pll->active_mask, | |
13729 | "pll is on but not used by any active crtc\n"); | |
13730 | I915_STATE_WARN(pll->on != active, | |
13731 | "pll on state mismatch (expected %i, found %i)\n", | |
13732 | pll->on, active); | |
13733 | } | |
5358901f | 13734 | |
e7c84544 | 13735 | if (!crtc) { |
2dd66ebd | 13736 | I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask, |
e7c84544 ML |
13737 | "more active pll users than references: %x vs %x\n", |
13738 | pll->active_mask, pll->config.crtc_mask); | |
5358901f | 13739 | |
e7c84544 ML |
13740 | return; |
13741 | } | |
13742 | ||
13743 | crtc_mask = 1 << drm_crtc_index(crtc); | |
13744 | ||
13745 | if (new_state->active) | |
13746 | I915_STATE_WARN(!(pll->active_mask & crtc_mask), | |
13747 | "pll active mismatch (expected pipe %c in active mask 0x%02x)\n", | |
13748 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
13749 | else | |
13750 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
13751 | "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n", | |
13752 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
2dd66ebd | 13753 | |
e7c84544 ML |
13754 | I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask), |
13755 | "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n", | |
13756 | crtc_mask, pll->config.crtc_mask); | |
66e985c0 | 13757 | |
e7c84544 ML |
13758 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, |
13759 | &dpll_hw_state, | |
13760 | sizeof(dpll_hw_state)), | |
13761 | "pll hw state mismatch\n"); | |
13762 | } | |
13763 | ||
13764 | static void | |
c0ead703 ML |
13765 | verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc, |
13766 | struct drm_crtc_state *old_crtc_state, | |
13767 | struct drm_crtc_state *new_crtc_state) | |
e7c84544 | 13768 | { |
fac5e23e | 13769 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7c84544 ML |
13770 | struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state); |
13771 | struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state); | |
13772 | ||
13773 | if (new_state->shared_dpll) | |
c0ead703 | 13774 | verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state); |
e7c84544 ML |
13775 | |
13776 | if (old_state->shared_dpll && | |
13777 | old_state->shared_dpll != new_state->shared_dpll) { | |
13778 | unsigned crtc_mask = 1 << drm_crtc_index(crtc); | |
13779 | struct intel_shared_dpll *pll = old_state->shared_dpll; | |
13780 | ||
13781 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
13782 | "pll active mismatch (didn't expect pipe %c in active mask)\n", | |
13783 | pipe_name(drm_crtc_index(crtc))); | |
13784 | I915_STATE_WARN(pll->config.crtc_mask & crtc_mask, | |
13785 | "pll enabled crtcs mismatch (found %x in enabled mask)\n", | |
13786 | pipe_name(drm_crtc_index(crtc))); | |
5358901f | 13787 | } |
8af6cf88 DV |
13788 | } |
13789 | ||
e7c84544 | 13790 | static void |
c0ead703 | 13791 | intel_modeset_verify_crtc(struct drm_crtc *crtc, |
677100ce ML |
13792 | struct drm_atomic_state *state, |
13793 | struct drm_crtc_state *old_state, | |
13794 | struct drm_crtc_state *new_state) | |
e7c84544 | 13795 | { |
5a21b665 DV |
13796 | if (!needs_modeset(new_state) && |
13797 | !to_intel_crtc_state(new_state)->update_pipe) | |
13798 | return; | |
13799 | ||
c0ead703 | 13800 | verify_wm_state(crtc, new_state); |
677100ce | 13801 | verify_connector_state(crtc->dev, state, crtc); |
c0ead703 ML |
13802 | verify_crtc_state(crtc, old_state, new_state); |
13803 | verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state); | |
e7c84544 ML |
13804 | } |
13805 | ||
13806 | static void | |
c0ead703 | 13807 | verify_disabled_dpll_state(struct drm_device *dev) |
e7c84544 | 13808 | { |
fac5e23e | 13809 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7c84544 ML |
13810 | int i; |
13811 | ||
13812 | for (i = 0; i < dev_priv->num_shared_dpll; i++) | |
c0ead703 | 13813 | verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL); |
e7c84544 ML |
13814 | } |
13815 | ||
13816 | static void | |
677100ce ML |
13817 | intel_modeset_verify_disabled(struct drm_device *dev, |
13818 | struct drm_atomic_state *state) | |
e7c84544 | 13819 | { |
c0ead703 | 13820 | verify_encoder_state(dev); |
677100ce | 13821 | verify_connector_state(dev, state, NULL); |
c0ead703 | 13822 | verify_disabled_dpll_state(dev); |
e7c84544 ML |
13823 | } |
13824 | ||
80715b2f VS |
13825 | static void update_scanline_offset(struct intel_crtc *crtc) |
13826 | { | |
4f8036a2 | 13827 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
80715b2f VS |
13828 | |
13829 | /* | |
13830 | * The scanline counter increments at the leading edge of hsync. | |
13831 | * | |
13832 | * On most platforms it starts counting from vtotal-1 on the | |
13833 | * first active line. That means the scanline counter value is | |
13834 | * always one less than what we would expect. Ie. just after | |
13835 | * start of vblank, which also occurs at start of hsync (on the | |
13836 | * last active line), the scanline counter will read vblank_start-1. | |
13837 | * | |
13838 | * On gen2 the scanline counter starts counting from 1 instead | |
13839 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
13840 | * to keep the value positive), instead of adding one. | |
13841 | * | |
13842 | * On HSW+ the behaviour of the scanline counter depends on the output | |
13843 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
13844 | * there's an extra 1 line difference. So we need to add two instead of | |
13845 | * one to the value. | |
13846 | */ | |
4f8036a2 | 13847 | if (IS_GEN2(dev_priv)) { |
124abe07 | 13848 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
13849 | int vtotal; |
13850 | ||
124abe07 VS |
13851 | vtotal = adjusted_mode->crtc_vtotal; |
13852 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
13853 | vtotal /= 2; |
13854 | ||
13855 | crtc->scanline_offset = vtotal - 1; | |
4f8036a2 | 13856 | } else if (HAS_DDI(dev_priv) && |
2d84d2b3 | 13857 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
13858 | crtc->scanline_offset = 2; |
13859 | } else | |
13860 | crtc->scanline_offset = 1; | |
13861 | } | |
13862 | ||
ad421372 | 13863 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 13864 | { |
225da59b | 13865 | struct drm_device *dev = state->dev; |
ed6739ef | 13866 | struct drm_i915_private *dev_priv = to_i915(dev); |
ad421372 | 13867 | struct intel_shared_dpll_config *shared_dpll = NULL; |
0a9ab303 ACO |
13868 | struct drm_crtc *crtc; |
13869 | struct drm_crtc_state *crtc_state; | |
0a9ab303 | 13870 | int i; |
ed6739ef ACO |
13871 | |
13872 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 13873 | return; |
ed6739ef | 13874 | |
0a9ab303 | 13875 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
fb1a38a9 | 13876 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8106ddbd ACO |
13877 | struct intel_shared_dpll *old_dpll = |
13878 | to_intel_crtc_state(crtc->state)->shared_dpll; | |
0a9ab303 | 13879 | |
fb1a38a9 | 13880 | if (!needs_modeset(crtc_state)) |
225da59b ACO |
13881 | continue; |
13882 | ||
8106ddbd | 13883 | to_intel_crtc_state(crtc_state)->shared_dpll = NULL; |
fb1a38a9 | 13884 | |
8106ddbd | 13885 | if (!old_dpll) |
fb1a38a9 | 13886 | continue; |
0a9ab303 | 13887 | |
ad421372 ML |
13888 | if (!shared_dpll) |
13889 | shared_dpll = intel_atomic_get_shared_dpll_state(state); | |
ed6739ef | 13890 | |
8106ddbd | 13891 | intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc); |
ad421372 | 13892 | } |
ed6739ef ACO |
13893 | } |
13894 | ||
99d736a2 ML |
13895 | /* |
13896 | * This implements the workaround described in the "notes" section of the mode | |
13897 | * set sequence documentation. When going from no pipes or single pipe to | |
13898 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
13899 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
13900 | */ | |
13901 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
13902 | { | |
13903 | struct drm_crtc_state *crtc_state; | |
13904 | struct intel_crtc *intel_crtc; | |
13905 | struct drm_crtc *crtc; | |
13906 | struct intel_crtc_state *first_crtc_state = NULL; | |
13907 | struct intel_crtc_state *other_crtc_state = NULL; | |
13908 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
13909 | int i; | |
13910 | ||
13911 | /* look at all crtc's that are going to be enabled in during modeset */ | |
13912 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13913 | intel_crtc = to_intel_crtc(crtc); | |
13914 | ||
13915 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
13916 | continue; | |
13917 | ||
13918 | if (first_crtc_state) { | |
13919 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
13920 | break; | |
13921 | } else { | |
13922 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
13923 | first_pipe = intel_crtc->pipe; | |
13924 | } | |
13925 | } | |
13926 | ||
13927 | /* No workaround needed? */ | |
13928 | if (!first_crtc_state) | |
13929 | return 0; | |
13930 | ||
13931 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
13932 | for_each_intel_crtc(state->dev, intel_crtc) { | |
13933 | struct intel_crtc_state *pipe_config; | |
13934 | ||
13935 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
13936 | if (IS_ERR(pipe_config)) | |
13937 | return PTR_ERR(pipe_config); | |
13938 | ||
13939 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
13940 | ||
13941 | if (!pipe_config->base.active || | |
13942 | needs_modeset(&pipe_config->base)) | |
13943 | continue; | |
13944 | ||
13945 | /* 2 or more enabled crtcs means no need for w/a */ | |
13946 | if (enabled_pipe != INVALID_PIPE) | |
13947 | return 0; | |
13948 | ||
13949 | enabled_pipe = intel_crtc->pipe; | |
13950 | } | |
13951 | ||
13952 | if (enabled_pipe != INVALID_PIPE) | |
13953 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
13954 | else if (other_crtc_state) | |
13955 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
13956 | ||
13957 | return 0; | |
13958 | } | |
13959 | ||
8d96561a VS |
13960 | static int intel_lock_all_pipes(struct drm_atomic_state *state) |
13961 | { | |
13962 | struct drm_crtc *crtc; | |
13963 | ||
13964 | /* Add all pipes to the state */ | |
13965 | for_each_crtc(state->dev, crtc) { | |
13966 | struct drm_crtc_state *crtc_state; | |
13967 | ||
13968 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13969 | if (IS_ERR(crtc_state)) | |
13970 | return PTR_ERR(crtc_state); | |
13971 | } | |
13972 | ||
13973 | return 0; | |
13974 | } | |
13975 | ||
27c329ed ML |
13976 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
13977 | { | |
13978 | struct drm_crtc *crtc; | |
27c329ed | 13979 | |
8d96561a VS |
13980 | /* |
13981 | * Add all pipes to the state, and force | |
13982 | * a modeset on all the active ones. | |
13983 | */ | |
27c329ed | 13984 | for_each_crtc(state->dev, crtc) { |
9780aad5 VS |
13985 | struct drm_crtc_state *crtc_state; |
13986 | int ret; | |
13987 | ||
27c329ed ML |
13988 | crtc_state = drm_atomic_get_crtc_state(state, crtc); |
13989 | if (IS_ERR(crtc_state)) | |
13990 | return PTR_ERR(crtc_state); | |
13991 | ||
13992 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
13993 | continue; | |
13994 | ||
13995 | crtc_state->mode_changed = true; | |
13996 | ||
13997 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
13998 | if (ret) | |
9780aad5 | 13999 | return ret; |
27c329ed ML |
14000 | |
14001 | ret = drm_atomic_add_affected_planes(state, crtc); | |
14002 | if (ret) | |
9780aad5 | 14003 | return ret; |
27c329ed ML |
14004 | } |
14005 | ||
9780aad5 | 14006 | return 0; |
27c329ed ML |
14007 | } |
14008 | ||
c347a676 | 14009 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd | 14010 | { |
565602d7 | 14011 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 14012 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
565602d7 ML |
14013 | struct drm_crtc *crtc; |
14014 | struct drm_crtc_state *crtc_state; | |
14015 | int ret = 0, i; | |
054518dd | 14016 | |
b359283a ML |
14017 | if (!check_digital_port_conflicts(state)) { |
14018 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
14019 | return -EINVAL; | |
14020 | } | |
14021 | ||
565602d7 ML |
14022 | intel_state->modeset = true; |
14023 | intel_state->active_crtcs = dev_priv->active_crtcs; | |
14024 | ||
14025 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
14026 | if (crtc_state->active) | |
14027 | intel_state->active_crtcs |= 1 << i; | |
14028 | else | |
14029 | intel_state->active_crtcs &= ~(1 << i); | |
8b4a7d05 MR |
14030 | |
14031 | if (crtc_state->active != crtc->state->active) | |
14032 | intel_state->active_pipe_changes |= drm_crtc_mask(crtc); | |
565602d7 ML |
14033 | } |
14034 | ||
054518dd ACO |
14035 | /* |
14036 | * See if the config requires any additional preparation, e.g. | |
14037 | * to adjust global state with pipes off. We need to do this | |
14038 | * here so we can get the modeset_pipe updated config for the new | |
14039 | * mode set on this crtc. For other crtcs we need to use the | |
14040 | * adjusted_mode bits in the crtc directly. | |
14041 | */ | |
27c329ed | 14042 | if (dev_priv->display.modeset_calc_cdclk) { |
c89e39f3 | 14043 | if (!intel_state->cdclk_pll_vco) |
63911d72 | 14044 | intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco; |
b2045352 VS |
14045 | if (!intel_state->cdclk_pll_vco) |
14046 | intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq; | |
c89e39f3 | 14047 | |
27c329ed | 14048 | ret = dev_priv->display.modeset_calc_cdclk(state); |
c89e39f3 CT |
14049 | if (ret < 0) |
14050 | return ret; | |
27c329ed | 14051 | |
8d96561a VS |
14052 | /* |
14053 | * Writes to dev_priv->atomic_cdclk_freq must protected by | |
14054 | * holding all the crtc locks, even if we don't end up | |
14055 | * touching the hardware | |
14056 | */ | |
14057 | if (intel_state->cdclk != dev_priv->atomic_cdclk_freq) { | |
14058 | ret = intel_lock_all_pipes(state); | |
14059 | if (ret < 0) | |
14060 | return ret; | |
14061 | } | |
14062 | ||
14063 | /* All pipes must be switched off while we change the cdclk. */ | |
c89e39f3 | 14064 | if (intel_state->dev_cdclk != dev_priv->cdclk_freq || |
8d96561a | 14065 | intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco) { |
27c329ed | 14066 | ret = intel_modeset_all_pipes(state); |
8d96561a VS |
14067 | if (ret < 0) |
14068 | return ret; | |
14069 | } | |
e8788cbc ML |
14070 | |
14071 | DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n", | |
14072 | intel_state->cdclk, intel_state->dev_cdclk); | |
e0ca7a6b | 14073 | } else { |
1a617b77 | 14074 | to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq; |
e0ca7a6b | 14075 | } |
054518dd | 14076 | |
ad421372 | 14077 | intel_modeset_clear_plls(state); |
054518dd | 14078 | |
565602d7 | 14079 | if (IS_HASWELL(dev_priv)) |
ad421372 | 14080 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 14081 | |
ad421372 | 14082 | return 0; |
c347a676 ACO |
14083 | } |
14084 | ||
aa363136 MR |
14085 | /* |
14086 | * Handle calculation of various watermark data at the end of the atomic check | |
14087 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
14088 | * handlers to ensure that all derived state has been updated. | |
14089 | */ | |
55994c2c | 14090 | static int calc_watermark_data(struct drm_atomic_state *state) |
aa363136 MR |
14091 | { |
14092 | struct drm_device *dev = state->dev; | |
98d39494 | 14093 | struct drm_i915_private *dev_priv = to_i915(dev); |
98d39494 MR |
14094 | |
14095 | /* Is there platform-specific watermark information to calculate? */ | |
14096 | if (dev_priv->display.compute_global_watermarks) | |
55994c2c MR |
14097 | return dev_priv->display.compute_global_watermarks(state); |
14098 | ||
14099 | return 0; | |
aa363136 MR |
14100 | } |
14101 | ||
74c090b1 ML |
14102 | /** |
14103 | * intel_atomic_check - validate state object | |
14104 | * @dev: drm device | |
14105 | * @state: state to validate | |
14106 | */ | |
14107 | static int intel_atomic_check(struct drm_device *dev, | |
14108 | struct drm_atomic_state *state) | |
c347a676 | 14109 | { |
dd8b3bdb | 14110 | struct drm_i915_private *dev_priv = to_i915(dev); |
aa363136 | 14111 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
c347a676 ACO |
14112 | struct drm_crtc *crtc; |
14113 | struct drm_crtc_state *crtc_state; | |
14114 | int ret, i; | |
61333b60 | 14115 | bool any_ms = false; |
c347a676 | 14116 | |
74c090b1 | 14117 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
14118 | if (ret) |
14119 | return ret; | |
14120 | ||
c347a676 | 14121 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
cfb23ed6 ML |
14122 | struct intel_crtc_state *pipe_config = |
14123 | to_intel_crtc_state(crtc_state); | |
1ed51de9 DV |
14124 | |
14125 | /* Catch I915_MODE_FLAG_INHERITED */ | |
14126 | if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) | |
14127 | crtc_state->mode_changed = true; | |
cfb23ed6 | 14128 | |
af4a879e | 14129 | if (!needs_modeset(crtc_state)) |
c347a676 ACO |
14130 | continue; |
14131 | ||
af4a879e DV |
14132 | if (!crtc_state->enable) { |
14133 | any_ms = true; | |
cfb23ed6 | 14134 | continue; |
af4a879e | 14135 | } |
cfb23ed6 | 14136 | |
26495481 DV |
14137 | /* FIXME: For only active_changed we shouldn't need to do any |
14138 | * state recomputation at all. */ | |
14139 | ||
1ed51de9 DV |
14140 | ret = drm_atomic_add_affected_connectors(state, crtc); |
14141 | if (ret) | |
14142 | return ret; | |
b359283a | 14143 | |
cfb23ed6 | 14144 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
25aa1c39 ML |
14145 | if (ret) { |
14146 | intel_dump_pipe_config(to_intel_crtc(crtc), | |
14147 | pipe_config, "[failed]"); | |
c347a676 | 14148 | return ret; |
25aa1c39 | 14149 | } |
c347a676 | 14150 | |
73831236 | 14151 | if (i915.fastboot && |
6315b5d3 | 14152 | intel_pipe_config_compare(dev_priv, |
cfb23ed6 | 14153 | to_intel_crtc_state(crtc->state), |
1ed51de9 | 14154 | pipe_config, true)) { |
26495481 | 14155 | crtc_state->mode_changed = false; |
bfd16b2a | 14156 | to_intel_crtc_state(crtc_state)->update_pipe = true; |
26495481 DV |
14157 | } |
14158 | ||
af4a879e | 14159 | if (needs_modeset(crtc_state)) |
26495481 | 14160 | any_ms = true; |
cfb23ed6 | 14161 | |
af4a879e DV |
14162 | ret = drm_atomic_add_affected_planes(state, crtc); |
14163 | if (ret) | |
14164 | return ret; | |
61333b60 | 14165 | |
26495481 DV |
14166 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
14167 | needs_modeset(crtc_state) ? | |
14168 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
14169 | } |
14170 | ||
61333b60 ML |
14171 | if (any_ms) { |
14172 | ret = intel_modeset_checks(state); | |
14173 | ||
14174 | if (ret) | |
14175 | return ret; | |
e0ca7a6b VS |
14176 | } else { |
14177 | intel_state->cdclk = dev_priv->atomic_cdclk_freq; | |
14178 | } | |
76305b1a | 14179 | |
dd8b3bdb | 14180 | ret = drm_atomic_helper_check_planes(dev, state); |
aa363136 MR |
14181 | if (ret) |
14182 | return ret; | |
14183 | ||
f51be2e0 | 14184 | intel_fbc_choose_crtc(dev_priv, state); |
55994c2c | 14185 | return calc_watermark_data(state); |
054518dd ACO |
14186 | } |
14187 | ||
5008e874 | 14188 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
d07f0e59 | 14189 | struct drm_atomic_state *state) |
5008e874 | 14190 | { |
fac5e23e | 14191 | struct drm_i915_private *dev_priv = to_i915(dev); |
5008e874 ML |
14192 | struct drm_crtc_state *crtc_state; |
14193 | struct drm_crtc *crtc; | |
14194 | int i, ret; | |
14195 | ||
5a21b665 DV |
14196 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
14197 | if (state->legacy_cursor_update) | |
a6747b73 ML |
14198 | continue; |
14199 | ||
5a21b665 DV |
14200 | ret = intel_crtc_wait_for_pending_flips(crtc); |
14201 | if (ret) | |
14202 | return ret; | |
5008e874 | 14203 | |
5a21b665 DV |
14204 | if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) |
14205 | flush_workqueue(dev_priv->wq); | |
d55dbd06 ML |
14206 | } |
14207 | ||
f935675f ML |
14208 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
14209 | if (ret) | |
14210 | return ret; | |
14211 | ||
5008e874 | 14212 | ret = drm_atomic_helper_prepare_planes(dev, state); |
f7e5838b | 14213 | mutex_unlock(&dev->struct_mutex); |
7580d774 | 14214 | |
5008e874 ML |
14215 | return ret; |
14216 | } | |
14217 | ||
a2991414 ML |
14218 | u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc) |
14219 | { | |
14220 | struct drm_device *dev = crtc->base.dev; | |
14221 | ||
14222 | if (!dev->max_vblank_count) | |
14223 | return drm_accurate_vblank_count(&crtc->base); | |
14224 | ||
14225 | return dev->driver->get_vblank_counter(dev, crtc->pipe); | |
14226 | } | |
14227 | ||
5a21b665 DV |
14228 | static void intel_atomic_wait_for_vblanks(struct drm_device *dev, |
14229 | struct drm_i915_private *dev_priv, | |
14230 | unsigned crtc_mask) | |
e8861675 | 14231 | { |
5a21b665 DV |
14232 | unsigned last_vblank_count[I915_MAX_PIPES]; |
14233 | enum pipe pipe; | |
14234 | int ret; | |
e8861675 | 14235 | |
5a21b665 DV |
14236 | if (!crtc_mask) |
14237 | return; | |
e8861675 | 14238 | |
5a21b665 | 14239 | for_each_pipe(dev_priv, pipe) { |
98187836 VS |
14240 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, |
14241 | pipe); | |
e8861675 | 14242 | |
5a21b665 | 14243 | if (!((1 << pipe) & crtc_mask)) |
e8861675 ML |
14244 | continue; |
14245 | ||
e2af48c6 | 14246 | ret = drm_crtc_vblank_get(&crtc->base); |
5a21b665 DV |
14247 | if (WARN_ON(ret != 0)) { |
14248 | crtc_mask &= ~(1 << pipe); | |
14249 | continue; | |
e8861675 ML |
14250 | } |
14251 | ||
e2af48c6 | 14252 | last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base); |
e8861675 ML |
14253 | } |
14254 | ||
5a21b665 | 14255 | for_each_pipe(dev_priv, pipe) { |
98187836 VS |
14256 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, |
14257 | pipe); | |
5a21b665 | 14258 | long lret; |
e8861675 | 14259 | |
5a21b665 DV |
14260 | if (!((1 << pipe) & crtc_mask)) |
14261 | continue; | |
d55dbd06 | 14262 | |
5a21b665 DV |
14263 | lret = wait_event_timeout(dev->vblank[pipe].queue, |
14264 | last_vblank_count[pipe] != | |
e2af48c6 | 14265 | drm_crtc_vblank_count(&crtc->base), |
5a21b665 | 14266 | msecs_to_jiffies(50)); |
d55dbd06 | 14267 | |
5a21b665 | 14268 | WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe)); |
d55dbd06 | 14269 | |
e2af48c6 | 14270 | drm_crtc_vblank_put(&crtc->base); |
d55dbd06 ML |
14271 | } |
14272 | } | |
14273 | ||
5a21b665 | 14274 | static bool needs_vblank_wait(struct intel_crtc_state *crtc_state) |
a6747b73 | 14275 | { |
5a21b665 DV |
14276 | /* fb updated, need to unpin old fb */ |
14277 | if (crtc_state->fb_changed) | |
14278 | return true; | |
a6747b73 | 14279 | |
5a21b665 DV |
14280 | /* wm changes, need vblank before final wm's */ |
14281 | if (crtc_state->update_wm_post) | |
14282 | return true; | |
a6747b73 | 14283 | |
5a21b665 DV |
14284 | /* |
14285 | * cxsr is re-enabled after vblank. | |
14286 | * This is already handled by crtc_state->update_wm_post, | |
14287 | * but added for clarity. | |
14288 | */ | |
14289 | if (crtc_state->disable_cxsr) | |
14290 | return true; | |
a6747b73 | 14291 | |
5a21b665 | 14292 | return false; |
e8861675 ML |
14293 | } |
14294 | ||
896e5bb0 L |
14295 | static void intel_update_crtc(struct drm_crtc *crtc, |
14296 | struct drm_atomic_state *state, | |
14297 | struct drm_crtc_state *old_crtc_state, | |
14298 | unsigned int *crtc_vblank_mask) | |
14299 | { | |
14300 | struct drm_device *dev = crtc->dev; | |
14301 | struct drm_i915_private *dev_priv = to_i915(dev); | |
14302 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
14303 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc->state); | |
14304 | bool modeset = needs_modeset(crtc->state); | |
14305 | ||
14306 | if (modeset) { | |
14307 | update_scanline_offset(intel_crtc); | |
14308 | dev_priv->display.crtc_enable(pipe_config, state); | |
14309 | } else { | |
14310 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); | |
14311 | } | |
14312 | ||
14313 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
14314 | intel_fbc_enable( | |
14315 | intel_crtc, pipe_config, | |
14316 | to_intel_plane_state(crtc->primary->state)); | |
14317 | } | |
14318 | ||
14319 | drm_atomic_helper_commit_planes_on_crtc(old_crtc_state); | |
14320 | ||
14321 | if (needs_vblank_wait(pipe_config)) | |
14322 | *crtc_vblank_mask |= drm_crtc_mask(crtc); | |
14323 | } | |
14324 | ||
14325 | static void intel_update_crtcs(struct drm_atomic_state *state, | |
14326 | unsigned int *crtc_vblank_mask) | |
14327 | { | |
14328 | struct drm_crtc *crtc; | |
14329 | struct drm_crtc_state *old_crtc_state; | |
14330 | int i; | |
14331 | ||
14332 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
14333 | if (!crtc->state->active) | |
14334 | continue; | |
14335 | ||
14336 | intel_update_crtc(crtc, state, old_crtc_state, | |
14337 | crtc_vblank_mask); | |
14338 | } | |
14339 | } | |
14340 | ||
27082493 L |
14341 | static void skl_update_crtcs(struct drm_atomic_state *state, |
14342 | unsigned int *crtc_vblank_mask) | |
14343 | { | |
0f0f74bc | 14344 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
27082493 L |
14345 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
14346 | struct drm_crtc *crtc; | |
ce0ba283 | 14347 | struct intel_crtc *intel_crtc; |
27082493 | 14348 | struct drm_crtc_state *old_crtc_state; |
ce0ba283 | 14349 | struct intel_crtc_state *cstate; |
27082493 L |
14350 | unsigned int updated = 0; |
14351 | bool progress; | |
14352 | enum pipe pipe; | |
5eff503b ML |
14353 | int i; |
14354 | ||
14355 | const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {}; | |
14356 | ||
14357 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) | |
14358 | /* ignore allocations for crtc's that have been turned off. */ | |
14359 | if (crtc->state->active) | |
14360 | entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb; | |
27082493 L |
14361 | |
14362 | /* | |
14363 | * Whenever the number of active pipes changes, we need to make sure we | |
14364 | * update the pipes in the right order so that their ddb allocations | |
14365 | * never overlap with eachother inbetween CRTC updates. Otherwise we'll | |
14366 | * cause pipe underruns and other bad stuff. | |
14367 | */ | |
14368 | do { | |
27082493 L |
14369 | progress = false; |
14370 | ||
14371 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
14372 | bool vbl_wait = false; | |
14373 | unsigned int cmask = drm_crtc_mask(crtc); | |
ce0ba283 L |
14374 | |
14375 | intel_crtc = to_intel_crtc(crtc); | |
14376 | cstate = to_intel_crtc_state(crtc->state); | |
14377 | pipe = intel_crtc->pipe; | |
27082493 | 14378 | |
5eff503b | 14379 | if (updated & cmask || !cstate->base.active) |
27082493 | 14380 | continue; |
5eff503b ML |
14381 | |
14382 | if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i)) | |
27082493 L |
14383 | continue; |
14384 | ||
14385 | updated |= cmask; | |
5eff503b | 14386 | entries[i] = &cstate->wm.skl.ddb; |
27082493 L |
14387 | |
14388 | /* | |
14389 | * If this is an already active pipe, it's DDB changed, | |
14390 | * and this isn't the last pipe that needs updating | |
14391 | * then we need to wait for a vblank to pass for the | |
14392 | * new ddb allocation to take effect. | |
14393 | */ | |
ce0ba283 | 14394 | if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb, |
512b5527 | 14395 | &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) && |
27082493 L |
14396 | !crtc->state->active_changed && |
14397 | intel_state->wm_results.dirty_pipes != updated) | |
14398 | vbl_wait = true; | |
14399 | ||
14400 | intel_update_crtc(crtc, state, old_crtc_state, | |
14401 | crtc_vblank_mask); | |
14402 | ||
14403 | if (vbl_wait) | |
0f0f74bc | 14404 | intel_wait_for_vblank(dev_priv, pipe); |
27082493 L |
14405 | |
14406 | progress = true; | |
14407 | } | |
14408 | } while (progress); | |
14409 | } | |
14410 | ||
94f05024 | 14411 | static void intel_atomic_commit_tail(struct drm_atomic_state *state) |
a6778b3c | 14412 | { |
94f05024 | 14413 | struct drm_device *dev = state->dev; |
565602d7 | 14414 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 14415 | struct drm_i915_private *dev_priv = to_i915(dev); |
29ceb0e6 | 14416 | struct drm_crtc_state *old_crtc_state; |
7580d774 | 14417 | struct drm_crtc *crtc; |
5a21b665 | 14418 | struct intel_crtc_state *intel_cstate; |
5a21b665 DV |
14419 | bool hw_check = intel_state->modeset; |
14420 | unsigned long put_domains[I915_MAX_PIPES] = {}; | |
14421 | unsigned crtc_vblank_mask = 0; | |
e95433c7 | 14422 | int i; |
a6778b3c | 14423 | |
ea0000f0 DV |
14424 | drm_atomic_helper_wait_for_dependencies(state); |
14425 | ||
c3b32658 | 14426 | if (intel_state->modeset) |
5a21b665 | 14427 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); |
565602d7 | 14428 | |
29ceb0e6 | 14429 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
a539205a ML |
14430 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
14431 | ||
5a21b665 DV |
14432 | if (needs_modeset(crtc->state) || |
14433 | to_intel_crtc_state(crtc->state)->update_pipe) { | |
14434 | hw_check = true; | |
14435 | ||
14436 | put_domains[to_intel_crtc(crtc)->pipe] = | |
14437 | modeset_get_crtc_power_domains(crtc, | |
14438 | to_intel_crtc_state(crtc->state)); | |
14439 | } | |
14440 | ||
61333b60 ML |
14441 | if (!needs_modeset(crtc->state)) |
14442 | continue; | |
14443 | ||
29ceb0e6 | 14444 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); |
460da916 | 14445 | |
29ceb0e6 VS |
14446 | if (old_crtc_state->active) { |
14447 | intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask); | |
4a806558 | 14448 | dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state); |
eddfcbcd | 14449 | intel_crtc->active = false; |
58f9c0bc | 14450 | intel_fbc_disable(intel_crtc); |
eddfcbcd | 14451 | intel_disable_shared_dpll(intel_crtc); |
9bbc8258 VS |
14452 | |
14453 | /* | |
14454 | * Underruns don't always raise | |
14455 | * interrupts, so check manually. | |
14456 | */ | |
14457 | intel_check_cpu_fifo_underruns(dev_priv); | |
14458 | intel_check_pch_fifo_underruns(dev_priv); | |
b9001114 | 14459 | |
e62929b3 ML |
14460 | if (!crtc->state->active) { |
14461 | /* | |
14462 | * Make sure we don't call initial_watermarks | |
14463 | * for ILK-style watermark updates. | |
14464 | */ | |
14465 | if (dev_priv->display.atomic_update_watermarks) | |
14466 | dev_priv->display.initial_watermarks(intel_state, | |
14467 | to_intel_crtc_state(crtc->state)); | |
14468 | else | |
14469 | intel_update_watermarks(intel_crtc); | |
14470 | } | |
a539205a | 14471 | } |
b8cecdf5 | 14472 | } |
7758a113 | 14473 | |
ea9d758d DV |
14474 | /* Only after disabling all output pipelines that will be changed can we |
14475 | * update the the output configuration. */ | |
4740b0f2 | 14476 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 14477 | |
565602d7 | 14478 | if (intel_state->modeset) { |
4740b0f2 | 14479 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); |
33c8df89 ML |
14480 | |
14481 | if (dev_priv->display.modeset_commit_cdclk && | |
c89e39f3 | 14482 | (intel_state->dev_cdclk != dev_priv->cdclk_freq || |
63911d72 | 14483 | intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)) |
33c8df89 | 14484 | dev_priv->display.modeset_commit_cdclk(state); |
f6d1973d | 14485 | |
656d1b89 L |
14486 | /* |
14487 | * SKL workaround: bspec recommends we disable the SAGV when we | |
14488 | * have more then one pipe enabled | |
14489 | */ | |
56feca91 | 14490 | if (!intel_can_enable_sagv(state)) |
16dcdc4e | 14491 | intel_disable_sagv(dev_priv); |
656d1b89 | 14492 | |
677100ce | 14493 | intel_modeset_verify_disabled(dev, state); |
4740b0f2 | 14494 | } |
47fab737 | 14495 | |
896e5bb0 | 14496 | /* Complete the events for pipes that have now been disabled */ |
29ceb0e6 | 14497 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
f6ac4b2a | 14498 | bool modeset = needs_modeset(crtc->state); |
80715b2f | 14499 | |
1f7528c4 DV |
14500 | /* Complete events for now disable pipes here. */ |
14501 | if (modeset && !crtc->state->active && crtc->state->event) { | |
14502 | spin_lock_irq(&dev->event_lock); | |
14503 | drm_crtc_send_vblank_event(crtc, crtc->state->event); | |
14504 | spin_unlock_irq(&dev->event_lock); | |
14505 | ||
14506 | crtc->state->event = NULL; | |
14507 | } | |
177246a8 MR |
14508 | } |
14509 | ||
896e5bb0 L |
14510 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
14511 | dev_priv->display.update_crtcs(state, &crtc_vblank_mask); | |
14512 | ||
94f05024 DV |
14513 | /* FIXME: We should call drm_atomic_helper_commit_hw_done() here |
14514 | * already, but still need the state for the delayed optimization. To | |
14515 | * fix this: | |
14516 | * - wrap the optimization/post_plane_update stuff into a per-crtc work. | |
14517 | * - schedule that vblank worker _before_ calling hw_done | |
14518 | * - at the start of commit_tail, cancel it _synchrously | |
14519 | * - switch over to the vblank wait helper in the core after that since | |
14520 | * we don't need out special handling any more. | |
14521 | */ | |
5a21b665 DV |
14522 | if (!state->legacy_cursor_update) |
14523 | intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask); | |
14524 | ||
14525 | /* | |
14526 | * Now that the vblank has passed, we can go ahead and program the | |
14527 | * optimal watermarks on platforms that need two-step watermark | |
14528 | * programming. | |
14529 | * | |
14530 | * TODO: Move this (and other cleanup) to an async worker eventually. | |
14531 | */ | |
14532 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
14533 | intel_cstate = to_intel_crtc_state(crtc->state); | |
14534 | ||
14535 | if (dev_priv->display.optimize_watermarks) | |
ccf010fb ML |
14536 | dev_priv->display.optimize_watermarks(intel_state, |
14537 | intel_cstate); | |
5a21b665 DV |
14538 | } |
14539 | ||
14540 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
14541 | intel_post_plane_update(to_intel_crtc_state(old_crtc_state)); | |
14542 | ||
14543 | if (put_domains[i]) | |
14544 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
14545 | ||
677100ce | 14546 | intel_modeset_verify_crtc(crtc, state, old_crtc_state, crtc->state); |
5a21b665 DV |
14547 | } |
14548 | ||
56feca91 | 14549 | if (intel_state->modeset && intel_can_enable_sagv(state)) |
16dcdc4e | 14550 | intel_enable_sagv(dev_priv); |
656d1b89 | 14551 | |
94f05024 DV |
14552 | drm_atomic_helper_commit_hw_done(state); |
14553 | ||
5a21b665 DV |
14554 | if (intel_state->modeset) |
14555 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); | |
14556 | ||
14557 | mutex_lock(&dev->struct_mutex); | |
14558 | drm_atomic_helper_cleanup_planes(dev, state); | |
14559 | mutex_unlock(&dev->struct_mutex); | |
14560 | ||
ea0000f0 DV |
14561 | drm_atomic_helper_commit_cleanup_done(state); |
14562 | ||
0853695c | 14563 | drm_atomic_state_put(state); |
f30da187 | 14564 | |
75714940 MK |
14565 | /* As one of the primary mmio accessors, KMS has a high likelihood |
14566 | * of triggering bugs in unclaimed access. After we finish | |
14567 | * modesetting, see if an error has been flagged, and if so | |
14568 | * enable debugging for the next modeset - and hope we catch | |
14569 | * the culprit. | |
14570 | * | |
14571 | * XXX note that we assume display power is on at this point. | |
14572 | * This might hold true now but we need to add pm helper to check | |
14573 | * unclaimed only when the hardware is on, as atomic commits | |
14574 | * can happen also when the device is completely off. | |
14575 | */ | |
14576 | intel_uncore_arm_unclaimed_mmio_detection(dev_priv); | |
94f05024 DV |
14577 | } |
14578 | ||
14579 | static void intel_atomic_commit_work(struct work_struct *work) | |
14580 | { | |
c004a90b CW |
14581 | struct drm_atomic_state *state = |
14582 | container_of(work, struct drm_atomic_state, commit_work); | |
14583 | ||
94f05024 DV |
14584 | intel_atomic_commit_tail(state); |
14585 | } | |
14586 | ||
c004a90b CW |
14587 | static int __i915_sw_fence_call |
14588 | intel_atomic_commit_ready(struct i915_sw_fence *fence, | |
14589 | enum i915_sw_fence_notify notify) | |
14590 | { | |
14591 | struct intel_atomic_state *state = | |
14592 | container_of(fence, struct intel_atomic_state, commit_ready); | |
14593 | ||
14594 | switch (notify) { | |
14595 | case FENCE_COMPLETE: | |
14596 | if (state->base.commit_work.func) | |
14597 | queue_work(system_unbound_wq, &state->base.commit_work); | |
14598 | break; | |
14599 | ||
14600 | case FENCE_FREE: | |
14601 | drm_atomic_state_put(&state->base); | |
14602 | break; | |
14603 | } | |
14604 | ||
14605 | return NOTIFY_DONE; | |
14606 | } | |
14607 | ||
6c9c1b38 DV |
14608 | static void intel_atomic_track_fbs(struct drm_atomic_state *state) |
14609 | { | |
14610 | struct drm_plane_state *old_plane_state; | |
14611 | struct drm_plane *plane; | |
6c9c1b38 DV |
14612 | int i; |
14613 | ||
faf5bf0a CW |
14614 | for_each_plane_in_state(state, plane, old_plane_state, i) |
14615 | i915_gem_track_fb(intel_fb_obj(old_plane_state->fb), | |
14616 | intel_fb_obj(plane->state->fb), | |
14617 | to_intel_plane(plane)->frontbuffer_bit); | |
6c9c1b38 DV |
14618 | } |
14619 | ||
94f05024 DV |
14620 | /** |
14621 | * intel_atomic_commit - commit validated state object | |
14622 | * @dev: DRM device | |
14623 | * @state: the top-level driver state object | |
14624 | * @nonblock: nonblocking commit | |
14625 | * | |
14626 | * This function commits a top-level state object that has been validated | |
14627 | * with drm_atomic_helper_check(). | |
14628 | * | |
94f05024 DV |
14629 | * RETURNS |
14630 | * Zero for success or -errno. | |
14631 | */ | |
14632 | static int intel_atomic_commit(struct drm_device *dev, | |
14633 | struct drm_atomic_state *state, | |
14634 | bool nonblock) | |
14635 | { | |
14636 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
fac5e23e | 14637 | struct drm_i915_private *dev_priv = to_i915(dev); |
94f05024 DV |
14638 | int ret = 0; |
14639 | ||
94f05024 DV |
14640 | ret = drm_atomic_helper_setup_commit(state, nonblock); |
14641 | if (ret) | |
14642 | return ret; | |
14643 | ||
c004a90b CW |
14644 | drm_atomic_state_get(state); |
14645 | i915_sw_fence_init(&intel_state->commit_ready, | |
14646 | intel_atomic_commit_ready); | |
94f05024 | 14647 | |
d07f0e59 | 14648 | ret = intel_atomic_prepare_commit(dev, state); |
94f05024 DV |
14649 | if (ret) { |
14650 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); | |
c004a90b | 14651 | i915_sw_fence_commit(&intel_state->commit_ready); |
94f05024 DV |
14652 | return ret; |
14653 | } | |
14654 | ||
14655 | drm_atomic_helper_swap_state(state, true); | |
14656 | dev_priv->wm.distrust_bios_wm = false; | |
94f05024 | 14657 | intel_shared_dpll_commit(state); |
6c9c1b38 | 14658 | intel_atomic_track_fbs(state); |
94f05024 | 14659 | |
c3b32658 ML |
14660 | if (intel_state->modeset) { |
14661 | memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, | |
14662 | sizeof(intel_state->min_pixclk)); | |
14663 | dev_priv->active_crtcs = intel_state->active_crtcs; | |
14664 | dev_priv->atomic_cdclk_freq = intel_state->cdclk; | |
14665 | } | |
14666 | ||
0853695c | 14667 | drm_atomic_state_get(state); |
c004a90b CW |
14668 | INIT_WORK(&state->commit_work, |
14669 | nonblock ? intel_atomic_commit_work : NULL); | |
14670 | ||
14671 | i915_sw_fence_commit(&intel_state->commit_ready); | |
14672 | if (!nonblock) { | |
14673 | i915_sw_fence_wait(&intel_state->commit_ready); | |
94f05024 | 14674 | intel_atomic_commit_tail(state); |
c004a90b | 14675 | } |
75714940 | 14676 | |
74c090b1 | 14677 | return 0; |
7f27126e JB |
14678 | } |
14679 | ||
c0c36b94 CW |
14680 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
14681 | { | |
83a57153 ACO |
14682 | struct drm_device *dev = crtc->dev; |
14683 | struct drm_atomic_state *state; | |
e694eb02 | 14684 | struct drm_crtc_state *crtc_state; |
2bfb4627 | 14685 | int ret; |
83a57153 ACO |
14686 | |
14687 | state = drm_atomic_state_alloc(dev); | |
14688 | if (!state) { | |
78108b7c VS |
14689 | DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory", |
14690 | crtc->base.id, crtc->name); | |
83a57153 ACO |
14691 | return; |
14692 | } | |
14693 | ||
e694eb02 | 14694 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
83a57153 | 14695 | |
e694eb02 ML |
14696 | retry: |
14697 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
14698 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
14699 | if (!ret) { | |
14700 | if (!crtc_state->active) | |
14701 | goto out; | |
83a57153 | 14702 | |
e694eb02 | 14703 | crtc_state->mode_changed = true; |
74c090b1 | 14704 | ret = drm_atomic_commit(state); |
83a57153 ACO |
14705 | } |
14706 | ||
e694eb02 ML |
14707 | if (ret == -EDEADLK) { |
14708 | drm_atomic_state_clear(state); | |
14709 | drm_modeset_backoff(state->acquire_ctx); | |
14710 | goto retry; | |
4ed9fb37 | 14711 | } |
4be07317 | 14712 | |
e694eb02 | 14713 | out: |
0853695c | 14714 | drm_atomic_state_put(state); |
c0c36b94 CW |
14715 | } |
14716 | ||
a8784875 BP |
14717 | /* |
14718 | * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling | |
14719 | * drm_atomic_helper_legacy_gamma_set() directly. | |
14720 | */ | |
14721 | static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc, | |
14722 | u16 *red, u16 *green, u16 *blue, | |
14723 | uint32_t size) | |
14724 | { | |
14725 | struct drm_device *dev = crtc->dev; | |
14726 | struct drm_mode_config *config = &dev->mode_config; | |
14727 | struct drm_crtc_state *state; | |
14728 | int ret; | |
14729 | ||
14730 | ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size); | |
14731 | if (ret) | |
14732 | return ret; | |
14733 | ||
14734 | /* | |
14735 | * Make sure we update the legacy properties so this works when | |
14736 | * atomic is not enabled. | |
14737 | */ | |
14738 | ||
14739 | state = crtc->state; | |
14740 | ||
14741 | drm_object_property_set_value(&crtc->base, | |
14742 | config->degamma_lut_property, | |
14743 | (state->degamma_lut) ? | |
14744 | state->degamma_lut->base.id : 0); | |
14745 | ||
14746 | drm_object_property_set_value(&crtc->base, | |
14747 | config->ctm_property, | |
14748 | (state->ctm) ? | |
14749 | state->ctm->base.id : 0); | |
14750 | ||
14751 | drm_object_property_set_value(&crtc->base, | |
14752 | config->gamma_lut_property, | |
14753 | (state->gamma_lut) ? | |
14754 | state->gamma_lut->base.id : 0); | |
14755 | ||
14756 | return 0; | |
14757 | } | |
14758 | ||
f6e5b160 | 14759 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
a8784875 | 14760 | .gamma_set = intel_atomic_legacy_gamma_set, |
74c090b1 | 14761 | .set_config = drm_atomic_helper_set_config, |
82cf435b | 14762 | .set_property = drm_atomic_helper_crtc_set_property, |
f6e5b160 | 14763 | .destroy = intel_crtc_destroy, |
527b6abe | 14764 | .page_flip = intel_crtc_page_flip, |
1356837e MR |
14765 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
14766 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
14767 | }; |
14768 | ||
6beb8c23 MR |
14769 | /** |
14770 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
14771 | * @plane: drm plane to prepare for | |
14772 | * @fb: framebuffer to prepare for presentation | |
14773 | * | |
14774 | * Prepares a framebuffer for usage on a display plane. Generally this | |
14775 | * involves pinning the underlying object and updating the frontbuffer tracking | |
14776 | * bits. Some older platforms need special physical address handling for | |
14777 | * cursor planes. | |
14778 | * | |
f935675f ML |
14779 | * Must be called with struct_mutex held. |
14780 | * | |
6beb8c23 MR |
14781 | * Returns 0 on success, negative error code on failure. |
14782 | */ | |
14783 | int | |
14784 | intel_prepare_plane_fb(struct drm_plane *plane, | |
1832040d | 14785 | struct drm_plane_state *new_state) |
465c120c | 14786 | { |
c004a90b CW |
14787 | struct intel_atomic_state *intel_state = |
14788 | to_intel_atomic_state(new_state->state); | |
b7f05d4a | 14789 | struct drm_i915_private *dev_priv = to_i915(plane->dev); |
844f9111 | 14790 | struct drm_framebuffer *fb = new_state->fb; |
6beb8c23 | 14791 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1ee49399 | 14792 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
c004a90b | 14793 | int ret; |
465c120c | 14794 | |
1ee49399 | 14795 | if (!obj && !old_obj) |
465c120c MR |
14796 | return 0; |
14797 | ||
5008e874 ML |
14798 | if (old_obj) { |
14799 | struct drm_crtc_state *crtc_state = | |
c004a90b CW |
14800 | drm_atomic_get_existing_crtc_state(new_state->state, |
14801 | plane->state->crtc); | |
5008e874 ML |
14802 | |
14803 | /* Big Hammer, we also need to ensure that any pending | |
14804 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
14805 | * current scanout is retired before unpinning the old | |
14806 | * framebuffer. Note that we rely on userspace rendering | |
14807 | * into the buffer attached to the pipe they are waiting | |
14808 | * on. If not, userspace generates a GPU hang with IPEHR | |
14809 | * point to the MI_WAIT_FOR_EVENT. | |
14810 | * | |
14811 | * This should only fail upon a hung GPU, in which case we | |
14812 | * can safely continue. | |
14813 | */ | |
c004a90b CW |
14814 | if (needs_modeset(crtc_state)) { |
14815 | ret = i915_sw_fence_await_reservation(&intel_state->commit_ready, | |
14816 | old_obj->resv, NULL, | |
14817 | false, 0, | |
14818 | GFP_KERNEL); | |
14819 | if (ret < 0) | |
14820 | return ret; | |
f4457ae7 | 14821 | } |
5008e874 ML |
14822 | } |
14823 | ||
c004a90b CW |
14824 | if (new_state->fence) { /* explicit fencing */ |
14825 | ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready, | |
14826 | new_state->fence, | |
14827 | I915_FENCE_TIMEOUT, | |
14828 | GFP_KERNEL); | |
14829 | if (ret < 0) | |
14830 | return ret; | |
14831 | } | |
14832 | ||
c37efb99 CW |
14833 | if (!obj) |
14834 | return 0; | |
14835 | ||
c004a90b CW |
14836 | if (!new_state->fence) { /* implicit fencing */ |
14837 | ret = i915_sw_fence_await_reservation(&intel_state->commit_ready, | |
14838 | obj->resv, NULL, | |
14839 | false, I915_FENCE_TIMEOUT, | |
14840 | GFP_KERNEL); | |
14841 | if (ret < 0) | |
14842 | return ret; | |
6b5e90f5 CW |
14843 | |
14844 | i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY); | |
c004a90b | 14845 | } |
5a21b665 | 14846 | |
c37efb99 | 14847 | if (plane->type == DRM_PLANE_TYPE_CURSOR && |
b7f05d4a | 14848 | INTEL_INFO(dev_priv)->cursor_needs_physical) { |
50a0bc90 | 14849 | int align = IS_I830(dev_priv) ? 16 * 1024 : 256; |
6beb8c23 | 14850 | ret = i915_gem_object_attach_phys(obj, align); |
d07f0e59 | 14851 | if (ret) { |
6beb8c23 | 14852 | DRM_DEBUG_KMS("failed to attach phys object\n"); |
d07f0e59 CW |
14853 | return ret; |
14854 | } | |
6beb8c23 | 14855 | } else { |
058d88c4 CW |
14856 | struct i915_vma *vma; |
14857 | ||
14858 | vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation); | |
d07f0e59 CW |
14859 | if (IS_ERR(vma)) { |
14860 | DRM_DEBUG_KMS("failed to pin object\n"); | |
14861 | return PTR_ERR(vma); | |
14862 | } | |
7580d774 | 14863 | } |
fdd508a6 | 14864 | |
d07f0e59 | 14865 | return 0; |
6beb8c23 MR |
14866 | } |
14867 | ||
38f3ce3a MR |
14868 | /** |
14869 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
14870 | * @plane: drm plane to clean up for | |
14871 | * @fb: old framebuffer that was on plane | |
14872 | * | |
14873 | * Cleans up a framebuffer that has just been removed from a plane. | |
f935675f ML |
14874 | * |
14875 | * Must be called with struct_mutex held. | |
38f3ce3a MR |
14876 | */ |
14877 | void | |
14878 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
1832040d | 14879 | struct drm_plane_state *old_state) |
38f3ce3a | 14880 | { |
b7f05d4a | 14881 | struct drm_i915_private *dev_priv = to_i915(plane->dev); |
7580d774 | 14882 | struct intel_plane_state *old_intel_state; |
1ee49399 ML |
14883 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb); |
14884 | struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb); | |
38f3ce3a | 14885 | |
7580d774 ML |
14886 | old_intel_state = to_intel_plane_state(old_state); |
14887 | ||
1ee49399 | 14888 | if (!obj && !old_obj) |
38f3ce3a MR |
14889 | return; |
14890 | ||
1ee49399 | 14891 | if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR || |
b7f05d4a | 14892 | !INTEL_INFO(dev_priv)->cursor_needs_physical)) |
3465c580 | 14893 | intel_unpin_fb_obj(old_state->fb, old_state->rotation); |
465c120c MR |
14894 | } |
14895 | ||
6156a456 CK |
14896 | int |
14897 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
14898 | { | |
14899 | int max_scale; | |
6156a456 CK |
14900 | int crtc_clock, cdclk; |
14901 | ||
bf8a0af0 | 14902 | if (!intel_crtc || !crtc_state->base.enable) |
6156a456 CK |
14903 | return DRM_PLANE_HELPER_NO_SCALING; |
14904 | ||
6156a456 | 14905 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; |
27c329ed | 14906 | cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; |
6156a456 | 14907 | |
54bf1ce6 | 14908 | if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)) |
6156a456 CK |
14909 | return DRM_PLANE_HELPER_NO_SCALING; |
14910 | ||
14911 | /* | |
14912 | * skl max scale is lower of: | |
14913 | * close to 3 but not 3, -1 is for that purpose | |
14914 | * or | |
14915 | * cdclk/crtc_clock | |
14916 | */ | |
14917 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); | |
14918 | ||
14919 | return max_scale; | |
14920 | } | |
14921 | ||
465c120c | 14922 | static int |
3c692a41 | 14923 | intel_check_primary_plane(struct drm_plane *plane, |
061e4b8d | 14924 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
14925 | struct intel_plane_state *state) |
14926 | { | |
b63a16f6 | 14927 | struct drm_i915_private *dev_priv = to_i915(plane->dev); |
2b875c22 | 14928 | struct drm_crtc *crtc = state->base.crtc; |
6156a456 | 14929 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
14930 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
14931 | bool can_position = false; | |
b63a16f6 | 14932 | int ret; |
465c120c | 14933 | |
b63a16f6 | 14934 | if (INTEL_GEN(dev_priv) >= 9) { |
693bdc28 VS |
14935 | /* use scaler when colorkey is not required */ |
14936 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { | |
14937 | min_scale = 1; | |
14938 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
14939 | } | |
d8106366 | 14940 | can_position = true; |
6156a456 | 14941 | } |
d8106366 | 14942 | |
cc926387 DV |
14943 | ret = drm_plane_helper_check_state(&state->base, |
14944 | &state->clip, | |
14945 | min_scale, max_scale, | |
14946 | can_position, true); | |
b63a16f6 VS |
14947 | if (ret) |
14948 | return ret; | |
14949 | ||
cc926387 | 14950 | if (!state->base.fb) |
b63a16f6 VS |
14951 | return 0; |
14952 | ||
14953 | if (INTEL_GEN(dev_priv) >= 9) { | |
14954 | ret = skl_check_plane_surface(state); | |
14955 | if (ret) | |
14956 | return ret; | |
14957 | } | |
14958 | ||
14959 | return 0; | |
14af293f GP |
14960 | } |
14961 | ||
5a21b665 DV |
14962 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
14963 | struct drm_crtc_state *old_crtc_state) | |
14964 | { | |
14965 | struct drm_device *dev = crtc->dev; | |
62e0fb88 | 14966 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 | 14967 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
b707aa50 L |
14968 | struct intel_crtc_state *intel_cstate = |
14969 | to_intel_crtc_state(crtc->state); | |
ccf010fb | 14970 | struct intel_crtc_state *old_intel_cstate = |
5a21b665 | 14971 | to_intel_crtc_state(old_crtc_state); |
ccf010fb ML |
14972 | struct intel_atomic_state *old_intel_state = |
14973 | to_intel_atomic_state(old_crtc_state->state); | |
5a21b665 DV |
14974 | bool modeset = needs_modeset(crtc->state); |
14975 | ||
14976 | /* Perform vblank evasion around commit operation */ | |
14977 | intel_pipe_update_start(intel_crtc); | |
14978 | ||
14979 | if (modeset) | |
e62929b3 | 14980 | goto out; |
5a21b665 DV |
14981 | |
14982 | if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) { | |
14983 | intel_color_set_csc(crtc->state); | |
14984 | intel_color_load_luts(crtc->state); | |
14985 | } | |
14986 | ||
ccf010fb ML |
14987 | if (intel_cstate->update_pipe) |
14988 | intel_update_pipe_config(intel_crtc, old_intel_cstate); | |
14989 | else if (INTEL_GEN(dev_priv) >= 9) | |
5a21b665 | 14990 | skl_detach_scalers(intel_crtc); |
62e0fb88 | 14991 | |
e62929b3 | 14992 | out: |
ccf010fb ML |
14993 | if (dev_priv->display.atomic_update_watermarks) |
14994 | dev_priv->display.atomic_update_watermarks(old_intel_state, | |
14995 | intel_cstate); | |
5a21b665 DV |
14996 | } |
14997 | ||
14998 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, | |
14999 | struct drm_crtc_state *old_crtc_state) | |
15000 | { | |
15001 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
15002 | ||
15003 | intel_pipe_update_end(intel_crtc, NULL); | |
15004 | } | |
15005 | ||
cf4c7c12 | 15006 | /** |
4a3b8769 MR |
15007 | * intel_plane_destroy - destroy a plane |
15008 | * @plane: plane to destroy | |
cf4c7c12 | 15009 | * |
4a3b8769 MR |
15010 | * Common destruction function for all types of planes (primary, cursor, |
15011 | * sprite). | |
cf4c7c12 | 15012 | */ |
4a3b8769 | 15013 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c | 15014 | { |
465c120c | 15015 | drm_plane_cleanup(plane); |
69ae561f | 15016 | kfree(to_intel_plane(plane)); |
465c120c MR |
15017 | } |
15018 | ||
65a3fea0 | 15019 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
15020 | .update_plane = drm_atomic_helper_update_plane, |
15021 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 15022 | .destroy = intel_plane_destroy, |
c196e1d6 | 15023 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
15024 | .atomic_get_property = intel_plane_atomic_get_property, |
15025 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
15026 | .atomic_duplicate_state = intel_plane_duplicate_state, |
15027 | .atomic_destroy_state = intel_plane_destroy_state, | |
465c120c MR |
15028 | }; |
15029 | ||
b079bd17 | 15030 | static struct intel_plane * |
580503c7 | 15031 | intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) |
465c120c | 15032 | { |
fca0ce2a VS |
15033 | struct intel_plane *primary = NULL; |
15034 | struct intel_plane_state *state = NULL; | |
465c120c | 15035 | const uint32_t *intel_primary_formats; |
93ca7e00 | 15036 | unsigned int supported_rotations; |
45e3743a | 15037 | unsigned int num_formats; |
fca0ce2a | 15038 | int ret; |
465c120c MR |
15039 | |
15040 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
b079bd17 VS |
15041 | if (!primary) { |
15042 | ret = -ENOMEM; | |
fca0ce2a | 15043 | goto fail; |
b079bd17 | 15044 | } |
465c120c | 15045 | |
8e7d688b | 15046 | state = intel_create_plane_state(&primary->base); |
b079bd17 VS |
15047 | if (!state) { |
15048 | ret = -ENOMEM; | |
fca0ce2a | 15049 | goto fail; |
b079bd17 VS |
15050 | } |
15051 | ||
8e7d688b | 15052 | primary->base.state = &state->base; |
ea2c67bb | 15053 | |
465c120c MR |
15054 | primary->can_scale = false; |
15055 | primary->max_downscale = 1; | |
580503c7 | 15056 | if (INTEL_GEN(dev_priv) >= 9) { |
6156a456 | 15057 | primary->can_scale = true; |
af99ceda | 15058 | state->scaler_id = -1; |
6156a456 | 15059 | } |
465c120c | 15060 | primary->pipe = pipe; |
e3c566df VS |
15061 | /* |
15062 | * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS | |
15063 | * port is hooked to pipe B. Hence we want plane A feeding pipe B. | |
15064 | */ | |
15065 | if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4) | |
15066 | primary->plane = (enum plane) !pipe; | |
15067 | else | |
15068 | primary->plane = (enum plane) pipe; | |
b14e5848 | 15069 | primary->id = PLANE_PRIMARY; |
a9ff8714 | 15070 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 | 15071 | primary->check_plane = intel_check_primary_plane; |
465c120c | 15072 | |
580503c7 | 15073 | if (INTEL_GEN(dev_priv) >= 9) { |
6c0fd451 DL |
15074 | intel_primary_formats = skl_primary_formats; |
15075 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
a8d201af ML |
15076 | |
15077 | primary->update_plane = skylake_update_primary_plane; | |
15078 | primary->disable_plane = skylake_disable_primary_plane; | |
6e266956 | 15079 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
a8d201af ML |
15080 | intel_primary_formats = i965_primary_formats; |
15081 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
15082 | ||
15083 | primary->update_plane = ironlake_update_primary_plane; | |
15084 | primary->disable_plane = i9xx_disable_primary_plane; | |
580503c7 | 15085 | } else if (INTEL_GEN(dev_priv) >= 4) { |
568db4f2 DL |
15086 | intel_primary_formats = i965_primary_formats; |
15087 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
a8d201af ML |
15088 | |
15089 | primary->update_plane = i9xx_update_primary_plane; | |
15090 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 DL |
15091 | } else { |
15092 | intel_primary_formats = i8xx_primary_formats; | |
15093 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
a8d201af ML |
15094 | |
15095 | primary->update_plane = i9xx_update_primary_plane; | |
15096 | primary->disable_plane = i9xx_disable_primary_plane; | |
465c120c MR |
15097 | } |
15098 | ||
580503c7 VS |
15099 | if (INTEL_GEN(dev_priv) >= 9) |
15100 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, | |
15101 | 0, &intel_plane_funcs, | |
38573dc1 VS |
15102 | intel_primary_formats, num_formats, |
15103 | DRM_PLANE_TYPE_PRIMARY, | |
15104 | "plane 1%c", pipe_name(pipe)); | |
9beb5fea | 15105 | else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) |
580503c7 VS |
15106 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, |
15107 | 0, &intel_plane_funcs, | |
38573dc1 VS |
15108 | intel_primary_formats, num_formats, |
15109 | DRM_PLANE_TYPE_PRIMARY, | |
15110 | "primary %c", pipe_name(pipe)); | |
15111 | else | |
580503c7 VS |
15112 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, |
15113 | 0, &intel_plane_funcs, | |
38573dc1 VS |
15114 | intel_primary_formats, num_formats, |
15115 | DRM_PLANE_TYPE_PRIMARY, | |
15116 | "plane %c", plane_name(primary->plane)); | |
fca0ce2a VS |
15117 | if (ret) |
15118 | goto fail; | |
48404c1e | 15119 | |
5481e27f | 15120 | if (INTEL_GEN(dev_priv) >= 9) { |
93ca7e00 VS |
15121 | supported_rotations = |
15122 | DRM_ROTATE_0 | DRM_ROTATE_90 | | |
15123 | DRM_ROTATE_180 | DRM_ROTATE_270; | |
4ea7be2b VS |
15124 | } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { |
15125 | supported_rotations = | |
15126 | DRM_ROTATE_0 | DRM_ROTATE_180 | | |
15127 | DRM_REFLECT_X; | |
5481e27f | 15128 | } else if (INTEL_GEN(dev_priv) >= 4) { |
93ca7e00 VS |
15129 | supported_rotations = |
15130 | DRM_ROTATE_0 | DRM_ROTATE_180; | |
15131 | } else { | |
15132 | supported_rotations = DRM_ROTATE_0; | |
15133 | } | |
15134 | ||
5481e27f | 15135 | if (INTEL_GEN(dev_priv) >= 4) |
93ca7e00 VS |
15136 | drm_plane_create_rotation_property(&primary->base, |
15137 | DRM_ROTATE_0, | |
15138 | supported_rotations); | |
48404c1e | 15139 | |
ea2c67bb MR |
15140 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
15141 | ||
b079bd17 | 15142 | return primary; |
fca0ce2a VS |
15143 | |
15144 | fail: | |
15145 | kfree(state); | |
15146 | kfree(primary); | |
15147 | ||
b079bd17 | 15148 | return ERR_PTR(ret); |
465c120c MR |
15149 | } |
15150 | ||
3d7d6510 | 15151 | static int |
852e787c | 15152 | intel_check_cursor_plane(struct drm_plane *plane, |
061e4b8d | 15153 | struct intel_crtc_state *crtc_state, |
852e787c | 15154 | struct intel_plane_state *state) |
3d7d6510 | 15155 | { |
2b875c22 | 15156 | struct drm_framebuffer *fb = state->base.fb; |
757f9a3e | 15157 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
b29ec92c | 15158 | enum pipe pipe = to_intel_plane(plane)->pipe; |
757f9a3e GP |
15159 | unsigned stride; |
15160 | int ret; | |
3d7d6510 | 15161 | |
f8856a44 VS |
15162 | ret = drm_plane_helper_check_state(&state->base, |
15163 | &state->clip, | |
15164 | DRM_PLANE_HELPER_NO_SCALING, | |
15165 | DRM_PLANE_HELPER_NO_SCALING, | |
15166 | true, true); | |
757f9a3e GP |
15167 | if (ret) |
15168 | return ret; | |
15169 | ||
757f9a3e GP |
15170 | /* if we want to turn off the cursor ignore width and height */ |
15171 | if (!obj) | |
da20eabd | 15172 | return 0; |
757f9a3e | 15173 | |
757f9a3e | 15174 | /* Check for which cursor types we support */ |
50a0bc90 TU |
15175 | if (!cursor_size_ok(to_i915(plane->dev), state->base.crtc_w, |
15176 | state->base.crtc_h)) { | |
ea2c67bb MR |
15177 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", |
15178 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
15179 | return -EINVAL; |
15180 | } | |
15181 | ||
ea2c67bb MR |
15182 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
15183 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
15184 | DRM_DEBUG_KMS("buffer is too small\n"); |
15185 | return -ENOMEM; | |
15186 | } | |
15187 | ||
bae781b2 | 15188 | if (fb->modifier != DRM_FORMAT_MOD_NONE) { |
757f9a3e | 15189 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
da20eabd | 15190 | return -EINVAL; |
32b7eeec MR |
15191 | } |
15192 | ||
b29ec92c VS |
15193 | /* |
15194 | * There's something wrong with the cursor on CHV pipe C. | |
15195 | * If it straddles the left edge of the screen then | |
15196 | * moving it away from the edge or disabling it often | |
15197 | * results in a pipe underrun, and often that can lead to | |
15198 | * dead pipe (constant underrun reported, and it scans | |
15199 | * out just a solid color). To recover from that, the | |
15200 | * display power well must be turned off and on again. | |
15201 | * Refuse the put the cursor into that compromised position. | |
15202 | */ | |
920a14b2 | 15203 | if (IS_CHERRYVIEW(to_i915(plane->dev)) && pipe == PIPE_C && |
936e71e3 | 15204 | state->base.visible && state->base.crtc_x < 0) { |
b29ec92c VS |
15205 | DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); |
15206 | return -EINVAL; | |
15207 | } | |
15208 | ||
da20eabd | 15209 | return 0; |
852e787c | 15210 | } |
3d7d6510 | 15211 | |
a8ad0d8e ML |
15212 | static void |
15213 | intel_disable_cursor_plane(struct drm_plane *plane, | |
7fabf5ef | 15214 | struct drm_crtc *crtc) |
a8ad0d8e | 15215 | { |
f2858021 ML |
15216 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
15217 | ||
15218 | intel_crtc->cursor_addr = 0; | |
55a08b3f | 15219 | intel_crtc_update_cursor(crtc, NULL); |
a8ad0d8e ML |
15220 | } |
15221 | ||
f4a2cf29 | 15222 | static void |
55a08b3f ML |
15223 | intel_update_cursor_plane(struct drm_plane *plane, |
15224 | const struct intel_crtc_state *crtc_state, | |
15225 | const struct intel_plane_state *state) | |
852e787c | 15226 | { |
55a08b3f ML |
15227 | struct drm_crtc *crtc = crtc_state->base.crtc; |
15228 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b7f05d4a | 15229 | struct drm_i915_private *dev_priv = to_i915(plane->dev); |
2b875c22 | 15230 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 15231 | uint32_t addr; |
852e787c | 15232 | |
f4a2cf29 | 15233 | if (!obj) |
a912f12f | 15234 | addr = 0; |
b7f05d4a | 15235 | else if (!INTEL_INFO(dev_priv)->cursor_needs_physical) |
058d88c4 | 15236 | addr = i915_gem_object_ggtt_offset(obj, NULL); |
f4a2cf29 | 15237 | else |
a912f12f | 15238 | addr = obj->phys_handle->busaddr; |
852e787c | 15239 | |
a912f12f | 15240 | intel_crtc->cursor_addr = addr; |
55a08b3f | 15241 | intel_crtc_update_cursor(crtc, state); |
852e787c GP |
15242 | } |
15243 | ||
b079bd17 | 15244 | static struct intel_plane * |
580503c7 | 15245 | intel_cursor_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) |
3d7d6510 | 15246 | { |
fca0ce2a VS |
15247 | struct intel_plane *cursor = NULL; |
15248 | struct intel_plane_state *state = NULL; | |
15249 | int ret; | |
3d7d6510 MR |
15250 | |
15251 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
b079bd17 VS |
15252 | if (!cursor) { |
15253 | ret = -ENOMEM; | |
fca0ce2a | 15254 | goto fail; |
b079bd17 | 15255 | } |
3d7d6510 | 15256 | |
8e7d688b | 15257 | state = intel_create_plane_state(&cursor->base); |
b079bd17 VS |
15258 | if (!state) { |
15259 | ret = -ENOMEM; | |
fca0ce2a | 15260 | goto fail; |
b079bd17 VS |
15261 | } |
15262 | ||
8e7d688b | 15263 | cursor->base.state = &state->base; |
ea2c67bb | 15264 | |
3d7d6510 MR |
15265 | cursor->can_scale = false; |
15266 | cursor->max_downscale = 1; | |
15267 | cursor->pipe = pipe; | |
15268 | cursor->plane = pipe; | |
b14e5848 | 15269 | cursor->id = PLANE_CURSOR; |
a9ff8714 | 15270 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
c59cb179 | 15271 | cursor->check_plane = intel_check_cursor_plane; |
55a08b3f | 15272 | cursor->update_plane = intel_update_cursor_plane; |
a8ad0d8e | 15273 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 | 15274 | |
580503c7 VS |
15275 | ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base, |
15276 | 0, &intel_plane_funcs, | |
fca0ce2a VS |
15277 | intel_cursor_formats, |
15278 | ARRAY_SIZE(intel_cursor_formats), | |
38573dc1 VS |
15279 | DRM_PLANE_TYPE_CURSOR, |
15280 | "cursor %c", pipe_name(pipe)); | |
fca0ce2a VS |
15281 | if (ret) |
15282 | goto fail; | |
4398ad45 | 15283 | |
5481e27f | 15284 | if (INTEL_GEN(dev_priv) >= 4) |
93ca7e00 VS |
15285 | drm_plane_create_rotation_property(&cursor->base, |
15286 | DRM_ROTATE_0, | |
15287 | DRM_ROTATE_0 | | |
15288 | DRM_ROTATE_180); | |
4398ad45 | 15289 | |
580503c7 | 15290 | if (INTEL_GEN(dev_priv) >= 9) |
af99ceda CK |
15291 | state->scaler_id = -1; |
15292 | ||
ea2c67bb MR |
15293 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
15294 | ||
b079bd17 | 15295 | return cursor; |
fca0ce2a VS |
15296 | |
15297 | fail: | |
15298 | kfree(state); | |
15299 | kfree(cursor); | |
15300 | ||
b079bd17 | 15301 | return ERR_PTR(ret); |
3d7d6510 MR |
15302 | } |
15303 | ||
65edccce VS |
15304 | static void skl_init_scalers(struct drm_i915_private *dev_priv, |
15305 | struct intel_crtc *crtc, | |
15306 | struct intel_crtc_state *crtc_state) | |
549e2bfb | 15307 | { |
65edccce VS |
15308 | struct intel_crtc_scaler_state *scaler_state = |
15309 | &crtc_state->scaler_state; | |
549e2bfb | 15310 | int i; |
549e2bfb | 15311 | |
65edccce VS |
15312 | for (i = 0; i < crtc->num_scalers; i++) { |
15313 | struct intel_scaler *scaler = &scaler_state->scalers[i]; | |
15314 | ||
15315 | scaler->in_use = 0; | |
15316 | scaler->mode = PS_SCALER_MODE_DYN; | |
549e2bfb CK |
15317 | } |
15318 | ||
15319 | scaler_state->scaler_id = -1; | |
15320 | } | |
15321 | ||
5ab0d85b | 15322 | static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) |
79e53945 JB |
15323 | { |
15324 | struct intel_crtc *intel_crtc; | |
f5de6e07 | 15325 | struct intel_crtc_state *crtc_state = NULL; |
b079bd17 VS |
15326 | struct intel_plane *primary = NULL; |
15327 | struct intel_plane *cursor = NULL; | |
a81d6fa0 | 15328 | int sprite, ret; |
79e53945 | 15329 | |
955382f3 | 15330 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
b079bd17 VS |
15331 | if (!intel_crtc) |
15332 | return -ENOMEM; | |
79e53945 | 15333 | |
f5de6e07 | 15334 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
b079bd17 VS |
15335 | if (!crtc_state) { |
15336 | ret = -ENOMEM; | |
f5de6e07 | 15337 | goto fail; |
b079bd17 | 15338 | } |
550acefd ACO |
15339 | intel_crtc->config = crtc_state; |
15340 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 15341 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 15342 | |
549e2bfb | 15343 | /* initialize shared scalers */ |
5ab0d85b | 15344 | if (INTEL_GEN(dev_priv) >= 9) { |
549e2bfb CK |
15345 | if (pipe == PIPE_C) |
15346 | intel_crtc->num_scalers = 1; | |
15347 | else | |
15348 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
15349 | ||
65edccce | 15350 | skl_init_scalers(dev_priv, intel_crtc, crtc_state); |
549e2bfb CK |
15351 | } |
15352 | ||
580503c7 | 15353 | primary = intel_primary_plane_create(dev_priv, pipe); |
b079bd17 VS |
15354 | if (IS_ERR(primary)) { |
15355 | ret = PTR_ERR(primary); | |
3d7d6510 | 15356 | goto fail; |
b079bd17 | 15357 | } |
d97d7b48 | 15358 | intel_crtc->plane_ids_mask |= BIT(primary->id); |
3d7d6510 | 15359 | |
a81d6fa0 | 15360 | for_each_sprite(dev_priv, pipe, sprite) { |
b079bd17 VS |
15361 | struct intel_plane *plane; |
15362 | ||
580503c7 | 15363 | plane = intel_sprite_plane_create(dev_priv, pipe, sprite); |
d2b2cbce | 15364 | if (IS_ERR(plane)) { |
b079bd17 VS |
15365 | ret = PTR_ERR(plane); |
15366 | goto fail; | |
15367 | } | |
d97d7b48 | 15368 | intel_crtc->plane_ids_mask |= BIT(plane->id); |
a81d6fa0 VS |
15369 | } |
15370 | ||
580503c7 | 15371 | cursor = intel_cursor_plane_create(dev_priv, pipe); |
d2b2cbce | 15372 | if (IS_ERR(cursor)) { |
b079bd17 | 15373 | ret = PTR_ERR(cursor); |
3d7d6510 | 15374 | goto fail; |
b079bd17 | 15375 | } |
d97d7b48 | 15376 | intel_crtc->plane_ids_mask |= BIT(cursor->id); |
3d7d6510 | 15377 | |
5ab0d85b | 15378 | ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base, |
b079bd17 VS |
15379 | &primary->base, &cursor->base, |
15380 | &intel_crtc_funcs, | |
4d5d72b7 | 15381 | "pipe %c", pipe_name(pipe)); |
3d7d6510 MR |
15382 | if (ret) |
15383 | goto fail; | |
79e53945 | 15384 | |
80824003 | 15385 | intel_crtc->pipe = pipe; |
e3c566df | 15386 | intel_crtc->plane = primary->plane; |
80824003 | 15387 | |
4b0e333e CW |
15388 | intel_crtc->cursor_base = ~0; |
15389 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 15390 | intel_crtc->cursor_size = ~0; |
8d7849db | 15391 | |
852eb00d VS |
15392 | intel_crtc->wm.cxsr_allowed = true; |
15393 | ||
22fd0fab JB |
15394 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
15395 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
e2af48c6 VS |
15396 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc; |
15397 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc; | |
22fd0fab | 15398 | |
79e53945 | 15399 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 | 15400 | |
8563b1e8 LL |
15401 | intel_color_init(&intel_crtc->base); |
15402 | ||
87b6b101 | 15403 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); |
b079bd17 VS |
15404 | |
15405 | return 0; | |
3d7d6510 MR |
15406 | |
15407 | fail: | |
b079bd17 VS |
15408 | /* |
15409 | * drm_mode_config_cleanup() will free up any | |
15410 | * crtcs/planes already initialized. | |
15411 | */ | |
f5de6e07 | 15412 | kfree(crtc_state); |
3d7d6510 | 15413 | kfree(intel_crtc); |
b079bd17 VS |
15414 | |
15415 | return ret; | |
79e53945 JB |
15416 | } |
15417 | ||
752aa88a JB |
15418 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
15419 | { | |
15420 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 15421 | struct drm_device *dev = connector->base.dev; |
752aa88a | 15422 | |
51fd371b | 15423 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 15424 | |
d3babd3f | 15425 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
15426 | return INVALID_PIPE; |
15427 | ||
15428 | return to_intel_crtc(encoder->crtc)->pipe; | |
15429 | } | |
15430 | ||
08d7b3d1 | 15431 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 15432 | struct drm_file *file) |
08d7b3d1 | 15433 | { |
08d7b3d1 | 15434 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 15435 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 15436 | struct intel_crtc *crtc; |
08d7b3d1 | 15437 | |
7707e653 | 15438 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
71240ed2 | 15439 | if (!drmmode_crtc) |
3f2c2057 | 15440 | return -ENOENT; |
08d7b3d1 | 15441 | |
7707e653 | 15442 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 15443 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 15444 | |
c05422d5 | 15445 | return 0; |
08d7b3d1 CW |
15446 | } |
15447 | ||
66a9278e | 15448 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 15449 | { |
66a9278e DV |
15450 | struct drm_device *dev = encoder->base.dev; |
15451 | struct intel_encoder *source_encoder; | |
79e53945 | 15452 | int index_mask = 0; |
79e53945 JB |
15453 | int entry = 0; |
15454 | ||
b2784e15 | 15455 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 15456 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
15457 | index_mask |= (1 << entry); |
15458 | ||
79e53945 JB |
15459 | entry++; |
15460 | } | |
4ef69c7a | 15461 | |
79e53945 JB |
15462 | return index_mask; |
15463 | } | |
15464 | ||
646d5772 | 15465 | static bool has_edp_a(struct drm_i915_private *dev_priv) |
4d302442 | 15466 | { |
646d5772 | 15467 | if (!IS_MOBILE(dev_priv)) |
4d302442 CW |
15468 | return false; |
15469 | ||
15470 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
15471 | return false; | |
15472 | ||
5db94019 | 15473 | if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
15474 | return false; |
15475 | ||
15476 | return true; | |
15477 | } | |
15478 | ||
6315b5d3 | 15479 | static bool intel_crt_present(struct drm_i915_private *dev_priv) |
84b4e042 | 15480 | { |
6315b5d3 | 15481 | if (INTEL_GEN(dev_priv) >= 9) |
884497ed DL |
15482 | return false; |
15483 | ||
50a0bc90 | 15484 | if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) |
84b4e042 JB |
15485 | return false; |
15486 | ||
920a14b2 | 15487 | if (IS_CHERRYVIEW(dev_priv)) |
84b4e042 JB |
15488 | return false; |
15489 | ||
4f8036a2 TU |
15490 | if (HAS_PCH_LPT_H(dev_priv) && |
15491 | I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) | |
65e472e4 VS |
15492 | return false; |
15493 | ||
70ac54d0 | 15494 | /* DDI E can't be used if DDI A requires 4 lanes */ |
4f8036a2 | 15495 | if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) |
70ac54d0 VS |
15496 | return false; |
15497 | ||
e4abb733 | 15498 | if (!dev_priv->vbt.int_crt_support) |
84b4e042 JB |
15499 | return false; |
15500 | ||
15501 | return true; | |
15502 | } | |
15503 | ||
8090ba8c ID |
15504 | void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv) |
15505 | { | |
15506 | int pps_num; | |
15507 | int pps_idx; | |
15508 | ||
15509 | if (HAS_DDI(dev_priv)) | |
15510 | return; | |
15511 | /* | |
15512 | * This w/a is needed at least on CPT/PPT, but to be sure apply it | |
15513 | * everywhere where registers can be write protected. | |
15514 | */ | |
15515 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
15516 | pps_num = 2; | |
15517 | else | |
15518 | pps_num = 1; | |
15519 | ||
15520 | for (pps_idx = 0; pps_idx < pps_num; pps_idx++) { | |
15521 | u32 val = I915_READ(PP_CONTROL(pps_idx)); | |
15522 | ||
15523 | val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS; | |
15524 | I915_WRITE(PP_CONTROL(pps_idx), val); | |
15525 | } | |
15526 | } | |
15527 | ||
44cb734c ID |
15528 | static void intel_pps_init(struct drm_i915_private *dev_priv) |
15529 | { | |
cc3f90f0 | 15530 | if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv)) |
44cb734c ID |
15531 | dev_priv->pps_mmio_base = PCH_PPS_BASE; |
15532 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
15533 | dev_priv->pps_mmio_base = VLV_PPS_BASE; | |
15534 | else | |
15535 | dev_priv->pps_mmio_base = PPS_BASE; | |
8090ba8c ID |
15536 | |
15537 | intel_pps_unlock_regs_wa(dev_priv); | |
44cb734c ID |
15538 | } |
15539 | ||
c39055b0 | 15540 | static void intel_setup_outputs(struct drm_i915_private *dev_priv) |
79e53945 | 15541 | { |
4ef69c7a | 15542 | struct intel_encoder *encoder; |
cb0953d7 | 15543 | bool dpd_is_edp = false; |
79e53945 | 15544 | |
44cb734c ID |
15545 | intel_pps_init(dev_priv); |
15546 | ||
97a824e1 ID |
15547 | /* |
15548 | * intel_edp_init_connector() depends on this completing first, to | |
15549 | * prevent the registeration of both eDP and LVDS and the incorrect | |
15550 | * sharing of the PPS. | |
15551 | */ | |
c39055b0 | 15552 | intel_lvds_init(dev_priv); |
79e53945 | 15553 | |
6315b5d3 | 15554 | if (intel_crt_present(dev_priv)) |
c39055b0 | 15555 | intel_crt_init(dev_priv); |
cb0953d7 | 15556 | |
cc3f90f0 | 15557 | if (IS_GEN9_LP(dev_priv)) { |
c776eb2e VK |
15558 | /* |
15559 | * FIXME: Broxton doesn't support port detection via the | |
15560 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
15561 | * detect the ports. | |
15562 | */ | |
c39055b0 ACO |
15563 | intel_ddi_init(dev_priv, PORT_A); |
15564 | intel_ddi_init(dev_priv, PORT_B); | |
15565 | intel_ddi_init(dev_priv, PORT_C); | |
c6c794a2 | 15566 | |
c39055b0 | 15567 | intel_dsi_init(dev_priv); |
4f8036a2 | 15568 | } else if (HAS_DDI(dev_priv)) { |
0e72a5b5 ED |
15569 | int found; |
15570 | ||
de31facd JB |
15571 | /* |
15572 | * Haswell uses DDI functions to detect digital outputs. | |
15573 | * On SKL pre-D0 the strap isn't connected, so we assume | |
15574 | * it's there. | |
15575 | */ | |
77179400 | 15576 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 15577 | /* WaIgnoreDDIAStrap: skl */ |
0853723b | 15578 | if (found || IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
c39055b0 | 15579 | intel_ddi_init(dev_priv, PORT_A); |
0e72a5b5 ED |
15580 | |
15581 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
15582 | * register */ | |
15583 | found = I915_READ(SFUSE_STRAP); | |
15584 | ||
15585 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
c39055b0 | 15586 | intel_ddi_init(dev_priv, PORT_B); |
0e72a5b5 | 15587 | if (found & SFUSE_STRAP_DDIC_DETECTED) |
c39055b0 | 15588 | intel_ddi_init(dev_priv, PORT_C); |
0e72a5b5 | 15589 | if (found & SFUSE_STRAP_DDID_DETECTED) |
c39055b0 | 15590 | intel_ddi_init(dev_priv, PORT_D); |
2800e4c2 RV |
15591 | /* |
15592 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
15593 | */ | |
0853723b | 15594 | if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) && |
2800e4c2 RV |
15595 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
15596 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
15597 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
c39055b0 | 15598 | intel_ddi_init(dev_priv, PORT_E); |
2800e4c2 | 15599 | |
6e266956 | 15600 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
cb0953d7 | 15601 | int found; |
dd11bc10 | 15602 | dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D); |
270b3042 | 15603 | |
646d5772 | 15604 | if (has_edp_a(dev_priv)) |
c39055b0 | 15605 | intel_dp_init(dev_priv, DP_A, PORT_A); |
cb0953d7 | 15606 | |
dc0fa718 | 15607 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 15608 | /* PCH SDVOB multiplex with HDMIB */ |
c39055b0 | 15609 | found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B); |
30ad48b7 | 15610 | if (!found) |
c39055b0 | 15611 | intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B); |
5eb08b69 | 15612 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
c39055b0 | 15613 | intel_dp_init(dev_priv, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
15614 | } |
15615 | ||
dc0fa718 | 15616 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
c39055b0 | 15617 | intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C); |
30ad48b7 | 15618 | |
dc0fa718 | 15619 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
c39055b0 | 15620 | intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D); |
30ad48b7 | 15621 | |
5eb08b69 | 15622 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
c39055b0 | 15623 | intel_dp_init(dev_priv, PCH_DP_C, PORT_C); |
5eb08b69 | 15624 | |
270b3042 | 15625 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
c39055b0 | 15626 | intel_dp_init(dev_priv, PCH_DP_D, PORT_D); |
920a14b2 | 15627 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
22f35042 | 15628 | bool has_edp, has_port; |
457c52d8 | 15629 | |
e17ac6db VS |
15630 | /* |
15631 | * The DP_DETECTED bit is the latched state of the DDC | |
15632 | * SDA pin at boot. However since eDP doesn't require DDC | |
15633 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
15634 | * eDP ports may have been muxed to an alternate function. | |
15635 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
15636 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
15637 | * detect eDP ports. | |
22f35042 VS |
15638 | * |
15639 | * Sadly the straps seem to be missing sometimes even for HDMI | |
15640 | * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap | |
15641 | * and VBT for the presence of the port. Additionally we can't | |
15642 | * trust the port type the VBT declares as we've seen at least | |
15643 | * HDMI ports that the VBT claim are DP or eDP. | |
e17ac6db | 15644 | */ |
dd11bc10 | 15645 | has_edp = intel_dp_is_edp(dev_priv, PORT_B); |
22f35042 VS |
15646 | has_port = intel_bios_is_port_present(dev_priv, PORT_B); |
15647 | if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port) | |
c39055b0 | 15648 | has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B); |
22f35042 | 15649 | if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) |
c39055b0 | 15650 | intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); |
585a94b8 | 15651 | |
dd11bc10 | 15652 | has_edp = intel_dp_is_edp(dev_priv, PORT_C); |
22f35042 VS |
15653 | has_port = intel_bios_is_port_present(dev_priv, PORT_C); |
15654 | if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port) | |
c39055b0 | 15655 | has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C); |
22f35042 | 15656 | if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) |
c39055b0 | 15657 | intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C); |
19c03924 | 15658 | |
920a14b2 | 15659 | if (IS_CHERRYVIEW(dev_priv)) { |
22f35042 VS |
15660 | /* |
15661 | * eDP not supported on port D, | |
15662 | * so no need to worry about it | |
15663 | */ | |
15664 | has_port = intel_bios_is_port_present(dev_priv, PORT_D); | |
15665 | if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port) | |
c39055b0 | 15666 | intel_dp_init(dev_priv, CHV_DP_D, PORT_D); |
22f35042 | 15667 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port) |
c39055b0 | 15668 | intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D); |
9418c1f1 VS |
15669 | } |
15670 | ||
c39055b0 | 15671 | intel_dsi_init(dev_priv); |
5db94019 | 15672 | } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) { |
27185ae1 | 15673 | bool found = false; |
7d57382e | 15674 | |
e2debe91 | 15675 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 15676 | DRM_DEBUG_KMS("probing SDVOB\n"); |
c39055b0 | 15677 | found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B); |
9beb5fea | 15678 | if (!found && IS_G4X(dev_priv)) { |
b01f2c3a | 15679 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
c39055b0 | 15680 | intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B); |
b01f2c3a | 15681 | } |
27185ae1 | 15682 | |
9beb5fea | 15683 | if (!found && IS_G4X(dev_priv)) |
c39055b0 | 15684 | intel_dp_init(dev_priv, DP_B, PORT_B); |
725e30ad | 15685 | } |
13520b05 KH |
15686 | |
15687 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 15688 | |
e2debe91 | 15689 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 15690 | DRM_DEBUG_KMS("probing SDVOC\n"); |
c39055b0 | 15691 | found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C); |
b01f2c3a | 15692 | } |
27185ae1 | 15693 | |
e2debe91 | 15694 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 15695 | |
9beb5fea | 15696 | if (IS_G4X(dev_priv)) { |
b01f2c3a | 15697 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
c39055b0 | 15698 | intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C); |
b01f2c3a | 15699 | } |
9beb5fea | 15700 | if (IS_G4X(dev_priv)) |
c39055b0 | 15701 | intel_dp_init(dev_priv, DP_C, PORT_C); |
725e30ad | 15702 | } |
27185ae1 | 15703 | |
9beb5fea | 15704 | if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED)) |
c39055b0 | 15705 | intel_dp_init(dev_priv, DP_D, PORT_D); |
5db94019 | 15706 | } else if (IS_GEN2(dev_priv)) |
c39055b0 | 15707 | intel_dvo_init(dev_priv); |
79e53945 | 15708 | |
56b857a5 | 15709 | if (SUPPORTS_TV(dev_priv)) |
c39055b0 | 15710 | intel_tv_init(dev_priv); |
79e53945 | 15711 | |
c39055b0 | 15712 | intel_psr_init(dev_priv); |
7c8f8a70 | 15713 | |
c39055b0 | 15714 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
4ef69c7a CW |
15715 | encoder->base.possible_crtcs = encoder->crtc_mask; |
15716 | encoder->base.possible_clones = | |
66a9278e | 15717 | intel_encoder_clones(encoder); |
79e53945 | 15718 | } |
47356eb6 | 15719 | |
c39055b0 | 15720 | intel_init_pch_refclk(dev_priv); |
270b3042 | 15721 | |
c39055b0 | 15722 | drm_helper_move_panel_connectors_to_head(&dev_priv->drm); |
79e53945 JB |
15723 | } |
15724 | ||
15725 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
15726 | { | |
60a5ca01 | 15727 | struct drm_device *dev = fb->dev; |
79e53945 | 15728 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 15729 | |
ef2d633e | 15730 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 15731 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 15732 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
f8c417cd | 15733 | i915_gem_object_put(intel_fb->obj); |
60a5ca01 | 15734 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
15735 | kfree(intel_fb); |
15736 | } | |
15737 | ||
15738 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 15739 | struct drm_file *file, |
79e53945 JB |
15740 | unsigned int *handle) |
15741 | { | |
15742 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 15743 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 15744 | |
cc917ab4 CW |
15745 | if (obj->userptr.mm) { |
15746 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); | |
15747 | return -EINVAL; | |
15748 | } | |
15749 | ||
05394f39 | 15750 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
15751 | } |
15752 | ||
86c98588 RV |
15753 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
15754 | struct drm_file *file, | |
15755 | unsigned flags, unsigned color, | |
15756 | struct drm_clip_rect *clips, | |
15757 | unsigned num_clips) | |
15758 | { | |
15759 | struct drm_device *dev = fb->dev; | |
15760 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
15761 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
15762 | ||
15763 | mutex_lock(&dev->struct_mutex); | |
a6a7cc4b CW |
15764 | if (obj->pin_display && obj->cache_dirty) |
15765 | i915_gem_clflush_object(obj, true); | |
74b4ea1e | 15766 | intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); |
86c98588 RV |
15767 | mutex_unlock(&dev->struct_mutex); |
15768 | ||
15769 | return 0; | |
15770 | } | |
15771 | ||
79e53945 JB |
15772 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
15773 | .destroy = intel_user_framebuffer_destroy, | |
15774 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 15775 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
15776 | }; |
15777 | ||
b321803d | 15778 | static |
920a14b2 TU |
15779 | u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv, |
15780 | uint64_t fb_modifier, uint32_t pixel_format) | |
b321803d | 15781 | { |
920a14b2 | 15782 | u32 gen = INTEL_INFO(dev_priv)->gen; |
b321803d DL |
15783 | |
15784 | if (gen >= 9) { | |
ac484963 VS |
15785 | int cpp = drm_format_plane_cpp(pixel_format, 0); |
15786 | ||
b321803d DL |
15787 | /* "The stride in bytes must not exceed the of the size of 8K |
15788 | * pixels and 32K bytes." | |
15789 | */ | |
ac484963 | 15790 | return min(8192 * cpp, 32768); |
920a14b2 TU |
15791 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev_priv) && |
15792 | !IS_CHERRYVIEW(dev_priv)) { | |
b321803d DL |
15793 | return 32*1024; |
15794 | } else if (gen >= 4) { | |
15795 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
15796 | return 16*1024; | |
15797 | else | |
15798 | return 32*1024; | |
15799 | } else if (gen >= 3) { | |
15800 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
15801 | return 8*1024; | |
15802 | else | |
15803 | return 16*1024; | |
15804 | } else { | |
15805 | /* XXX DSPC is limited to 4k tiled */ | |
15806 | return 8*1024; | |
15807 | } | |
15808 | } | |
15809 | ||
b5ea642a DV |
15810 | static int intel_framebuffer_init(struct drm_device *dev, |
15811 | struct intel_framebuffer *intel_fb, | |
15812 | struct drm_mode_fb_cmd2 *mode_cmd, | |
15813 | struct drm_i915_gem_object *obj) | |
79e53945 | 15814 | { |
7b49f948 | 15815 | struct drm_i915_private *dev_priv = to_i915(dev); |
c2ff7370 | 15816 | unsigned int tiling = i915_gem_object_get_tiling(obj); |
79e53945 | 15817 | int ret; |
b321803d | 15818 | u32 pitch_limit, stride_alignment; |
b3c11ac2 | 15819 | struct drm_format_name_buf format_name; |
79e53945 | 15820 | |
dd4916c5 DV |
15821 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
15822 | ||
2a80eada | 15823 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
c2ff7370 VS |
15824 | /* |
15825 | * If there's a fence, enforce that | |
15826 | * the fb modifier and tiling mode match. | |
15827 | */ | |
15828 | if (tiling != I915_TILING_NONE && | |
15829 | tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { | |
2a80eada DV |
15830 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); |
15831 | return -EINVAL; | |
15832 | } | |
15833 | } else { | |
c2ff7370 | 15834 | if (tiling == I915_TILING_X) { |
2a80eada | 15835 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; |
c2ff7370 | 15836 | } else if (tiling == I915_TILING_Y) { |
2a80eada DV |
15837 | DRM_DEBUG("No Y tiling for legacy addfb\n"); |
15838 | return -EINVAL; | |
15839 | } | |
15840 | } | |
15841 | ||
9a8f0a12 TU |
15842 | /* Passed in modifier sanity checking. */ |
15843 | switch (mode_cmd->modifier[0]) { | |
15844 | case I915_FORMAT_MOD_Y_TILED: | |
15845 | case I915_FORMAT_MOD_Yf_TILED: | |
6315b5d3 | 15846 | if (INTEL_GEN(dev_priv) < 9) { |
9a8f0a12 TU |
15847 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", |
15848 | mode_cmd->modifier[0]); | |
15849 | return -EINVAL; | |
15850 | } | |
15851 | case DRM_FORMAT_MOD_NONE: | |
15852 | case I915_FORMAT_MOD_X_TILED: | |
15853 | break; | |
15854 | default: | |
c0f40428 JB |
15855 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
15856 | mode_cmd->modifier[0]); | |
57cd6508 | 15857 | return -EINVAL; |
c16ed4be | 15858 | } |
57cd6508 | 15859 | |
c2ff7370 VS |
15860 | /* |
15861 | * gen2/3 display engine uses the fence if present, | |
15862 | * so the tiling mode must match the fb modifier exactly. | |
15863 | */ | |
15864 | if (INTEL_INFO(dev_priv)->gen < 4 && | |
15865 | tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { | |
15866 | DRM_DEBUG("tiling_mode must match fb modifier exactly on gen2/3\n"); | |
15867 | return -EINVAL; | |
15868 | } | |
15869 | ||
7b49f948 VS |
15870 | stride_alignment = intel_fb_stride_alignment(dev_priv, |
15871 | mode_cmd->modifier[0], | |
b321803d DL |
15872 | mode_cmd->pixel_format); |
15873 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
15874 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
15875 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 15876 | return -EINVAL; |
c16ed4be | 15877 | } |
57cd6508 | 15878 | |
920a14b2 | 15879 | pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0], |
b321803d | 15880 | mode_cmd->pixel_format); |
a35cdaa0 | 15881 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
15882 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
15883 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 15884 | "tiled" : "linear", |
a35cdaa0 | 15885 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 15886 | return -EINVAL; |
c16ed4be | 15887 | } |
5d7bd705 | 15888 | |
c2ff7370 VS |
15889 | /* |
15890 | * If there's a fence, enforce that | |
15891 | * the fb pitch and fence stride match. | |
15892 | */ | |
15893 | if (tiling != I915_TILING_NONE && | |
3e510a8e | 15894 | mode_cmd->pitches[0] != i915_gem_object_get_stride(obj)) { |
c16ed4be | 15895 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", |
3e510a8e CW |
15896 | mode_cmd->pitches[0], |
15897 | i915_gem_object_get_stride(obj)); | |
5d7bd705 | 15898 | return -EINVAL; |
c16ed4be | 15899 | } |
5d7bd705 | 15900 | |
57779d06 | 15901 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 15902 | switch (mode_cmd->pixel_format) { |
57779d06 | 15903 | case DRM_FORMAT_C8: |
04b3924d VS |
15904 | case DRM_FORMAT_RGB565: |
15905 | case DRM_FORMAT_XRGB8888: | |
15906 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
15907 | break; |
15908 | case DRM_FORMAT_XRGB1555: | |
6315b5d3 | 15909 | if (INTEL_GEN(dev_priv) > 3) { |
b3c11ac2 EE |
15910 | DRM_DEBUG("unsupported pixel format: %s\n", |
15911 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
57779d06 | 15912 | return -EINVAL; |
c16ed4be | 15913 | } |
57779d06 | 15914 | break; |
57779d06 | 15915 | case DRM_FORMAT_ABGR8888: |
920a14b2 | 15916 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
6315b5d3 | 15917 | INTEL_GEN(dev_priv) < 9) { |
b3c11ac2 EE |
15918 | DRM_DEBUG("unsupported pixel format: %s\n", |
15919 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
6c0fd451 DL |
15920 | return -EINVAL; |
15921 | } | |
15922 | break; | |
15923 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 15924 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 15925 | case DRM_FORMAT_XBGR2101010: |
6315b5d3 | 15926 | if (INTEL_GEN(dev_priv) < 4) { |
b3c11ac2 EE |
15927 | DRM_DEBUG("unsupported pixel format: %s\n", |
15928 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
57779d06 | 15929 | return -EINVAL; |
c16ed4be | 15930 | } |
b5626747 | 15931 | break; |
7531208b | 15932 | case DRM_FORMAT_ABGR2101010: |
920a14b2 | 15933 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { |
b3c11ac2 EE |
15934 | DRM_DEBUG("unsupported pixel format: %s\n", |
15935 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
7531208b DL |
15936 | return -EINVAL; |
15937 | } | |
15938 | break; | |
04b3924d VS |
15939 | case DRM_FORMAT_YUYV: |
15940 | case DRM_FORMAT_UYVY: | |
15941 | case DRM_FORMAT_YVYU: | |
15942 | case DRM_FORMAT_VYUY: | |
6315b5d3 | 15943 | if (INTEL_GEN(dev_priv) < 5) { |
b3c11ac2 EE |
15944 | DRM_DEBUG("unsupported pixel format: %s\n", |
15945 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
57779d06 | 15946 | return -EINVAL; |
c16ed4be | 15947 | } |
57cd6508 CW |
15948 | break; |
15949 | default: | |
b3c11ac2 EE |
15950 | DRM_DEBUG("unsupported pixel format: %s\n", |
15951 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
57cd6508 CW |
15952 | return -EINVAL; |
15953 | } | |
15954 | ||
90f9a336 VS |
15955 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
15956 | if (mode_cmd->offsets[0] != 0) | |
15957 | return -EINVAL; | |
15958 | ||
c7d73f6a DV |
15959 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
15960 | intel_fb->obj = obj; | |
15961 | ||
6687c906 VS |
15962 | ret = intel_fill_fb_info(dev_priv, &intel_fb->base); |
15963 | if (ret) | |
15964 | return ret; | |
2d7a215f | 15965 | |
79e53945 JB |
15966 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
15967 | if (ret) { | |
15968 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
15969 | return ret; | |
15970 | } | |
15971 | ||
0b05e1e0 VS |
15972 | intel_fb->obj->framebuffer_references++; |
15973 | ||
79e53945 JB |
15974 | return 0; |
15975 | } | |
15976 | ||
79e53945 JB |
15977 | static struct drm_framebuffer * |
15978 | intel_user_framebuffer_create(struct drm_device *dev, | |
15979 | struct drm_file *filp, | |
1eb83451 | 15980 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
79e53945 | 15981 | { |
dcb1394e | 15982 | struct drm_framebuffer *fb; |
05394f39 | 15983 | struct drm_i915_gem_object *obj; |
76dc3769 | 15984 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
79e53945 | 15985 | |
03ac0642 CW |
15986 | obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]); |
15987 | if (!obj) | |
cce13ff7 | 15988 | return ERR_PTR(-ENOENT); |
79e53945 | 15989 | |
92907cbb | 15990 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
dcb1394e | 15991 | if (IS_ERR(fb)) |
f0cd5182 | 15992 | i915_gem_object_put(obj); |
dcb1394e LW |
15993 | |
15994 | return fb; | |
79e53945 JB |
15995 | } |
15996 | ||
778e23a9 CW |
15997 | static void intel_atomic_state_free(struct drm_atomic_state *state) |
15998 | { | |
15999 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
16000 | ||
16001 | drm_atomic_state_default_release(state); | |
16002 | ||
16003 | i915_sw_fence_fini(&intel_state->commit_ready); | |
16004 | ||
16005 | kfree(state); | |
16006 | } | |
16007 | ||
79e53945 | 16008 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 16009 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 16010 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
16011 | .atomic_check = intel_atomic_check, |
16012 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
16013 | .atomic_state_alloc = intel_atomic_state_alloc, |
16014 | .atomic_state_clear = intel_atomic_state_clear, | |
778e23a9 | 16015 | .atomic_state_free = intel_atomic_state_free, |
79e53945 JB |
16016 | }; |
16017 | ||
88212941 ID |
16018 | /** |
16019 | * intel_init_display_hooks - initialize the display modesetting hooks | |
16020 | * @dev_priv: device private | |
16021 | */ | |
16022 | void intel_init_display_hooks(struct drm_i915_private *dev_priv) | |
e70236a8 | 16023 | { |
88212941 | 16024 | if (INTEL_INFO(dev_priv)->gen >= 9) { |
bc8d7dff | 16025 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
16026 | dev_priv->display.get_initial_plane_config = |
16027 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
16028 | dev_priv->display.crtc_compute_clock = |
16029 | haswell_crtc_compute_clock; | |
16030 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
16031 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 16032 | } else if (HAS_DDI(dev_priv)) { |
0e8ffe1b | 16033 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
16034 | dev_priv->display.get_initial_plane_config = |
16035 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
16036 | dev_priv->display.crtc_compute_clock = |
16037 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
16038 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
16039 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 16040 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
0e8ffe1b | 16041 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
16042 | dev_priv->display.get_initial_plane_config = |
16043 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
16044 | dev_priv->display.crtc_compute_clock = |
16045 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
16046 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
16047 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
65b3d6a9 | 16048 | } else if (IS_CHERRYVIEW(dev_priv)) { |
89b667f8 | 16049 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
16050 | dev_priv->display.get_initial_plane_config = |
16051 | i9xx_get_initial_plane_config; | |
65b3d6a9 ACO |
16052 | dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock; |
16053 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
16054 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
16055 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
16056 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
16057 | dev_priv->display.get_initial_plane_config = | |
16058 | i9xx_get_initial_plane_config; | |
16059 | dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock; | |
89b667f8 JB |
16060 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
16061 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
19ec6693 ACO |
16062 | } else if (IS_G4X(dev_priv)) { |
16063 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
16064 | dev_priv->display.get_initial_plane_config = | |
16065 | i9xx_get_initial_plane_config; | |
16066 | dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock; | |
16067 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
16068 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
70e8aa21 ACO |
16069 | } else if (IS_PINEVIEW(dev_priv)) { |
16070 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
16071 | dev_priv->display.get_initial_plane_config = | |
16072 | i9xx_get_initial_plane_config; | |
16073 | dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock; | |
16074 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
16075 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 | 16076 | } else if (!IS_GEN2(dev_priv)) { |
0e8ffe1b | 16077 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
16078 | dev_priv->display.get_initial_plane_config = |
16079 | i9xx_get_initial_plane_config; | |
d6dfee7a | 16080 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
16081 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
16082 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 ACO |
16083 | } else { |
16084 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
16085 | dev_priv->display.get_initial_plane_config = | |
16086 | i9xx_get_initial_plane_config; | |
16087 | dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock; | |
16088 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
16089 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 16090 | } |
e70236a8 | 16091 | |
e70236a8 | 16092 | /* Returns the core display clock speed */ |
88212941 | 16093 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
1652d19e VS |
16094 | dev_priv->display.get_display_clock_speed = |
16095 | skylake_get_display_clock_speed; | |
89b3c3c7 | 16096 | else if (IS_GEN9_LP(dev_priv)) |
acd3f3d3 BP |
16097 | dev_priv->display.get_display_clock_speed = |
16098 | broxton_get_display_clock_speed; | |
88212941 | 16099 | else if (IS_BROADWELL(dev_priv)) |
1652d19e VS |
16100 | dev_priv->display.get_display_clock_speed = |
16101 | broadwell_get_display_clock_speed; | |
88212941 | 16102 | else if (IS_HASWELL(dev_priv)) |
1652d19e VS |
16103 | dev_priv->display.get_display_clock_speed = |
16104 | haswell_get_display_clock_speed; | |
88212941 | 16105 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
25eb05fc JB |
16106 | dev_priv->display.get_display_clock_speed = |
16107 | valleyview_get_display_clock_speed; | |
88212941 | 16108 | else if (IS_GEN5(dev_priv)) |
b37a6434 VS |
16109 | dev_priv->display.get_display_clock_speed = |
16110 | ilk_get_display_clock_speed; | |
c0f86832 | 16111 | else if (IS_I945G(dev_priv) || IS_I965G(dev_priv) || |
88212941 | 16112 | IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) |
e70236a8 JB |
16113 | dev_priv->display.get_display_clock_speed = |
16114 | i945_get_display_clock_speed; | |
88212941 | 16115 | else if (IS_GM45(dev_priv)) |
34edce2f VS |
16116 | dev_priv->display.get_display_clock_speed = |
16117 | gm45_get_display_clock_speed; | |
c0f86832 | 16118 | else if (IS_I965GM(dev_priv)) |
34edce2f VS |
16119 | dev_priv->display.get_display_clock_speed = |
16120 | i965gm_get_display_clock_speed; | |
88212941 | 16121 | else if (IS_PINEVIEW(dev_priv)) |
34edce2f VS |
16122 | dev_priv->display.get_display_clock_speed = |
16123 | pnv_get_display_clock_speed; | |
88212941 | 16124 | else if (IS_G33(dev_priv) || IS_G4X(dev_priv)) |
34edce2f VS |
16125 | dev_priv->display.get_display_clock_speed = |
16126 | g33_get_display_clock_speed; | |
88212941 | 16127 | else if (IS_I915G(dev_priv)) |
e70236a8 JB |
16128 | dev_priv->display.get_display_clock_speed = |
16129 | i915_get_display_clock_speed; | |
2a307c2e | 16130 | else if (IS_I945GM(dev_priv) || IS_I845G(dev_priv)) |
e70236a8 JB |
16131 | dev_priv->display.get_display_clock_speed = |
16132 | i9xx_misc_get_display_clock_speed; | |
88212941 | 16133 | else if (IS_I915GM(dev_priv)) |
e70236a8 JB |
16134 | dev_priv->display.get_display_clock_speed = |
16135 | i915gm_get_display_clock_speed; | |
88212941 | 16136 | else if (IS_I865G(dev_priv)) |
e70236a8 JB |
16137 | dev_priv->display.get_display_clock_speed = |
16138 | i865_get_display_clock_speed; | |
88212941 | 16139 | else if (IS_I85X(dev_priv)) |
e70236a8 | 16140 | dev_priv->display.get_display_clock_speed = |
1b1d2716 | 16141 | i85x_get_display_clock_speed; |
623e01e5 | 16142 | else { /* 830 */ |
88212941 | 16143 | WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n"); |
e70236a8 JB |
16144 | dev_priv->display.get_display_clock_speed = |
16145 | i830_get_display_clock_speed; | |
623e01e5 | 16146 | } |
e70236a8 | 16147 | |
88212941 | 16148 | if (IS_GEN5(dev_priv)) { |
3bb11b53 | 16149 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
88212941 | 16150 | } else if (IS_GEN6(dev_priv)) { |
3bb11b53 | 16151 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
88212941 | 16152 | } else if (IS_IVYBRIDGE(dev_priv)) { |
3bb11b53 SJ |
16153 | /* FIXME: detect B0+ stepping and use auto training */ |
16154 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
88212941 | 16155 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
3bb11b53 | 16156 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
445e780b VS |
16157 | } |
16158 | ||
16159 | if (IS_BROADWELL(dev_priv)) { | |
16160 | dev_priv->display.modeset_commit_cdclk = | |
16161 | broadwell_modeset_commit_cdclk; | |
16162 | dev_priv->display.modeset_calc_cdclk = | |
16163 | broadwell_modeset_calc_cdclk; | |
88212941 | 16164 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
27c329ed ML |
16165 | dev_priv->display.modeset_commit_cdclk = |
16166 | valleyview_modeset_commit_cdclk; | |
16167 | dev_priv->display.modeset_calc_cdclk = | |
16168 | valleyview_modeset_calc_cdclk; | |
89b3c3c7 | 16169 | } else if (IS_GEN9_LP(dev_priv)) { |
27c329ed | 16170 | dev_priv->display.modeset_commit_cdclk = |
324513c0 | 16171 | bxt_modeset_commit_cdclk; |
27c329ed | 16172 | dev_priv->display.modeset_calc_cdclk = |
324513c0 | 16173 | bxt_modeset_calc_cdclk; |
c89e39f3 CT |
16174 | } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { |
16175 | dev_priv->display.modeset_commit_cdclk = | |
16176 | skl_modeset_commit_cdclk; | |
16177 | dev_priv->display.modeset_calc_cdclk = | |
16178 | skl_modeset_calc_cdclk; | |
e70236a8 | 16179 | } |
5a21b665 | 16180 | |
27082493 L |
16181 | if (dev_priv->info.gen >= 9) |
16182 | dev_priv->display.update_crtcs = skl_update_crtcs; | |
16183 | else | |
16184 | dev_priv->display.update_crtcs = intel_update_crtcs; | |
16185 | ||
5a21b665 DV |
16186 | switch (INTEL_INFO(dev_priv)->gen) { |
16187 | case 2: | |
16188 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
16189 | break; | |
16190 | ||
16191 | case 3: | |
16192 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
16193 | break; | |
16194 | ||
16195 | case 4: | |
16196 | case 5: | |
16197 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
16198 | break; | |
16199 | ||
16200 | case 6: | |
16201 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
16202 | break; | |
16203 | case 7: | |
16204 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ | |
16205 | dev_priv->display.queue_flip = intel_gen7_queue_flip; | |
16206 | break; | |
16207 | case 9: | |
16208 | /* Drop through - unsupported since execlist only. */ | |
16209 | default: | |
16210 | /* Default just returns -ENODEV to indicate unsupported */ | |
16211 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
16212 | } | |
e70236a8 JB |
16213 | } |
16214 | ||
b690e96c JB |
16215 | /* |
16216 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
16217 | * resume, or other times. This quirk makes sure that's the case for | |
16218 | * affected systems. | |
16219 | */ | |
0206e353 | 16220 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c | 16221 | { |
fac5e23e | 16222 | struct drm_i915_private *dev_priv = to_i915(dev); |
b690e96c JB |
16223 | |
16224 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 16225 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
16226 | } |
16227 | ||
b6b5d049 VS |
16228 | static void quirk_pipeb_force(struct drm_device *dev) |
16229 | { | |
fac5e23e | 16230 | struct drm_i915_private *dev_priv = to_i915(dev); |
b6b5d049 VS |
16231 | |
16232 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
16233 | DRM_INFO("applying pipe b force quirk\n"); | |
16234 | } | |
16235 | ||
435793df KP |
16236 | /* |
16237 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
16238 | */ | |
16239 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
16240 | { | |
fac5e23e | 16241 | struct drm_i915_private *dev_priv = to_i915(dev); |
435793df | 16242 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; |
bc0daf48 | 16243 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
16244 | } |
16245 | ||
4dca20ef | 16246 | /* |
5a15ab5b CE |
16247 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
16248 | * brightness value | |
4dca20ef CE |
16249 | */ |
16250 | static void quirk_invert_brightness(struct drm_device *dev) | |
16251 | { | |
fac5e23e | 16252 | struct drm_i915_private *dev_priv = to_i915(dev); |
4dca20ef | 16253 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; |
bc0daf48 | 16254 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
16255 | } |
16256 | ||
9c72cc6f SD |
16257 | /* Some VBT's incorrectly indicate no backlight is present */ |
16258 | static void quirk_backlight_present(struct drm_device *dev) | |
16259 | { | |
fac5e23e | 16260 | struct drm_i915_private *dev_priv = to_i915(dev); |
9c72cc6f SD |
16261 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; |
16262 | DRM_INFO("applying backlight present quirk\n"); | |
16263 | } | |
16264 | ||
b690e96c JB |
16265 | struct intel_quirk { |
16266 | int device; | |
16267 | int subsystem_vendor; | |
16268 | int subsystem_device; | |
16269 | void (*hook)(struct drm_device *dev); | |
16270 | }; | |
16271 | ||
5f85f176 EE |
16272 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
16273 | struct intel_dmi_quirk { | |
16274 | void (*hook)(struct drm_device *dev); | |
16275 | const struct dmi_system_id (*dmi_id_list)[]; | |
16276 | }; | |
16277 | ||
16278 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
16279 | { | |
16280 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
16281 | return 1; | |
16282 | } | |
16283 | ||
16284 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
16285 | { | |
16286 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
16287 | { | |
16288 | .callback = intel_dmi_reverse_brightness, | |
16289 | .ident = "NCR Corporation", | |
16290 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
16291 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
16292 | }, | |
16293 | }, | |
16294 | { } /* terminating entry */ | |
16295 | }, | |
16296 | .hook = quirk_invert_brightness, | |
16297 | }, | |
16298 | }; | |
16299 | ||
c43b5634 | 16300 | static struct intel_quirk intel_quirks[] = { |
b690e96c JB |
16301 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
16302 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
16303 | ||
b690e96c JB |
16304 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
16305 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
16306 | ||
5f080c0f VS |
16307 | /* 830 needs to leave pipe A & dpll A up */ |
16308 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
16309 | ||
b6b5d049 VS |
16310 | /* 830 needs to leave pipe B & dpll B up */ |
16311 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
16312 | ||
435793df KP |
16313 | /* Lenovo U160 cannot use SSC on LVDS */ |
16314 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
16315 | |
16316 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
16317 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 16318 | |
be505f64 AH |
16319 | /* Acer Aspire 5734Z must invert backlight brightness */ |
16320 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
16321 | ||
16322 | /* Acer/eMachines G725 */ | |
16323 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
16324 | ||
16325 | /* Acer/eMachines e725 */ | |
16326 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
16327 | ||
16328 | /* Acer/Packard Bell NCL20 */ | |
16329 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
16330 | ||
16331 | /* Acer Aspire 4736Z */ | |
16332 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
16333 | |
16334 | /* Acer Aspire 5336 */ | |
16335 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
16336 | |
16337 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
16338 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 16339 | |
dfb3d47b SD |
16340 | /* Acer C720 Chromebook (Core i3 4005U) */ |
16341 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
16342 | ||
b2a9601c | 16343 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
16344 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
16345 | ||
1b9448b0 JN |
16346 | /* Apple Macbook 4,1 */ |
16347 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, | |
16348 | ||
d4967d8c SD |
16349 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
16350 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
16351 | |
16352 | /* HP Chromebook 14 (Celeron 2955U) */ | |
16353 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
16354 | |
16355 | /* Dell Chromebook 11 */ | |
16356 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
9be64eee JN |
16357 | |
16358 | /* Dell Chromebook 11 (2015 version) */ | |
16359 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
16360 | }; |
16361 | ||
16362 | static void intel_init_quirks(struct drm_device *dev) | |
16363 | { | |
16364 | struct pci_dev *d = dev->pdev; | |
16365 | int i; | |
16366 | ||
16367 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
16368 | struct intel_quirk *q = &intel_quirks[i]; | |
16369 | ||
16370 | if (d->device == q->device && | |
16371 | (d->subsystem_vendor == q->subsystem_vendor || | |
16372 | q->subsystem_vendor == PCI_ANY_ID) && | |
16373 | (d->subsystem_device == q->subsystem_device || | |
16374 | q->subsystem_device == PCI_ANY_ID)) | |
16375 | q->hook(dev); | |
16376 | } | |
5f85f176 EE |
16377 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
16378 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
16379 | intel_dmi_quirks[i].hook(dev); | |
16380 | } | |
b690e96c JB |
16381 | } |
16382 | ||
9cce37f4 | 16383 | /* Disable the VGA plane that we never use */ |
29b74b7f | 16384 | static void i915_disable_vga(struct drm_i915_private *dev_priv) |
9cce37f4 | 16385 | { |
52a05c30 | 16386 | struct pci_dev *pdev = dev_priv->drm.pdev; |
9cce37f4 | 16387 | u8 sr1; |
920a14b2 | 16388 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv); |
9cce37f4 | 16389 | |
2b37c616 | 16390 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
52a05c30 | 16391 | vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 16392 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
16393 | sr1 = inb(VGA_SR_DATA); |
16394 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
52a05c30 | 16395 | vga_put(pdev, VGA_RSRC_LEGACY_IO); |
9cce37f4 JB |
16396 | udelay(300); |
16397 | ||
01f5a626 | 16398 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
16399 | POSTING_READ(vga_reg); |
16400 | } | |
16401 | ||
f817586c DV |
16402 | void intel_modeset_init_hw(struct drm_device *dev) |
16403 | { | |
fac5e23e | 16404 | struct drm_i915_private *dev_priv = to_i915(dev); |
1a617b77 | 16405 | |
4c75b940 | 16406 | intel_update_cdclk(dev_priv); |
1a617b77 ML |
16407 | |
16408 | dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq; | |
16409 | ||
46f16e63 | 16410 | intel_init_clock_gating(dev_priv); |
f817586c DV |
16411 | } |
16412 | ||
d93c0372 MR |
16413 | /* |
16414 | * Calculate what we think the watermarks should be for the state we've read | |
16415 | * out of the hardware and then immediately program those watermarks so that | |
16416 | * we ensure the hardware settings match our internal state. | |
16417 | * | |
16418 | * We can calculate what we think WM's should be by creating a duplicate of the | |
16419 | * current state (which was constructed during hardware readout) and running it | |
16420 | * through the atomic check code to calculate new watermark values in the | |
16421 | * state object. | |
16422 | */ | |
16423 | static void sanitize_watermarks(struct drm_device *dev) | |
16424 | { | |
16425 | struct drm_i915_private *dev_priv = to_i915(dev); | |
16426 | struct drm_atomic_state *state; | |
ccf010fb | 16427 | struct intel_atomic_state *intel_state; |
d93c0372 MR |
16428 | struct drm_crtc *crtc; |
16429 | struct drm_crtc_state *cstate; | |
16430 | struct drm_modeset_acquire_ctx ctx; | |
16431 | int ret; | |
16432 | int i; | |
16433 | ||
16434 | /* Only supported on platforms that use atomic watermark design */ | |
ed4a6a7c | 16435 | if (!dev_priv->display.optimize_watermarks) |
d93c0372 MR |
16436 | return; |
16437 | ||
16438 | /* | |
16439 | * We need to hold connection_mutex before calling duplicate_state so | |
16440 | * that the connector loop is protected. | |
16441 | */ | |
16442 | drm_modeset_acquire_init(&ctx, 0); | |
16443 | retry: | |
0cd1262d | 16444 | ret = drm_modeset_lock_all_ctx(dev, &ctx); |
d93c0372 MR |
16445 | if (ret == -EDEADLK) { |
16446 | drm_modeset_backoff(&ctx); | |
16447 | goto retry; | |
16448 | } else if (WARN_ON(ret)) { | |
0cd1262d | 16449 | goto fail; |
d93c0372 MR |
16450 | } |
16451 | ||
16452 | state = drm_atomic_helper_duplicate_state(dev, &ctx); | |
16453 | if (WARN_ON(IS_ERR(state))) | |
0cd1262d | 16454 | goto fail; |
d93c0372 | 16455 | |
ccf010fb ML |
16456 | intel_state = to_intel_atomic_state(state); |
16457 | ||
ed4a6a7c MR |
16458 | /* |
16459 | * Hardware readout is the only time we don't want to calculate | |
16460 | * intermediate watermarks (since we don't trust the current | |
16461 | * watermarks). | |
16462 | */ | |
ccf010fb | 16463 | intel_state->skip_intermediate_wm = true; |
ed4a6a7c | 16464 | |
d93c0372 MR |
16465 | ret = intel_atomic_check(dev, state); |
16466 | if (ret) { | |
16467 | /* | |
16468 | * If we fail here, it means that the hardware appears to be | |
16469 | * programmed in a way that shouldn't be possible, given our | |
16470 | * understanding of watermark requirements. This might mean a | |
16471 | * mistake in the hardware readout code or a mistake in the | |
16472 | * watermark calculations for a given platform. Raise a WARN | |
16473 | * so that this is noticeable. | |
16474 | * | |
16475 | * If this actually happens, we'll have to just leave the | |
16476 | * BIOS-programmed watermarks untouched and hope for the best. | |
16477 | */ | |
16478 | WARN(true, "Could not determine valid watermarks for inherited state\n"); | |
b9a1b717 | 16479 | goto put_state; |
d93c0372 MR |
16480 | } |
16481 | ||
16482 | /* Write calculated watermark values back */ | |
d93c0372 MR |
16483 | for_each_crtc_in_state(state, crtc, cstate, i) { |
16484 | struct intel_crtc_state *cs = to_intel_crtc_state(cstate); | |
16485 | ||
ed4a6a7c | 16486 | cs->wm.need_postvbl_update = true; |
ccf010fb | 16487 | dev_priv->display.optimize_watermarks(intel_state, cs); |
d93c0372 MR |
16488 | } |
16489 | ||
b9a1b717 | 16490 | put_state: |
0853695c | 16491 | drm_atomic_state_put(state); |
0cd1262d | 16492 | fail: |
d93c0372 MR |
16493 | drm_modeset_drop_locks(&ctx); |
16494 | drm_modeset_acquire_fini(&ctx); | |
16495 | } | |
16496 | ||
b079bd17 | 16497 | int intel_modeset_init(struct drm_device *dev) |
79e53945 | 16498 | { |
72e96d64 JL |
16499 | struct drm_i915_private *dev_priv = to_i915(dev); |
16500 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
8cc87b75 | 16501 | enum pipe pipe; |
46f297fb | 16502 | struct intel_crtc *crtc; |
79e53945 JB |
16503 | |
16504 | drm_mode_config_init(dev); | |
16505 | ||
16506 | dev->mode_config.min_width = 0; | |
16507 | dev->mode_config.min_height = 0; | |
16508 | ||
019d96cb DA |
16509 | dev->mode_config.preferred_depth = 24; |
16510 | dev->mode_config.prefer_shadow = 1; | |
16511 | ||
25bab385 TU |
16512 | dev->mode_config.allow_fb_modifiers = true; |
16513 | ||
e6ecefaa | 16514 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 16515 | |
b690e96c JB |
16516 | intel_init_quirks(dev); |
16517 | ||
62d75df7 | 16518 | intel_init_pm(dev_priv); |
1fa61106 | 16519 | |
b7f05d4a | 16520 | if (INTEL_INFO(dev_priv)->num_pipes == 0) |
b079bd17 | 16521 | return 0; |
e3c74757 | 16522 | |
69f92f67 LW |
16523 | /* |
16524 | * There may be no VBT; and if the BIOS enabled SSC we can | |
16525 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
16526 | * BIOS isn't using it, don't assume it will work even if the VBT | |
16527 | * indicates as much. | |
16528 | */ | |
6e266956 | 16529 | if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { |
69f92f67 LW |
16530 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & |
16531 | DREF_SSC1_ENABLE); | |
16532 | ||
16533 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
16534 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
16535 | bios_lvds_use_ssc ? "en" : "dis", | |
16536 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
16537 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
16538 | } | |
16539 | } | |
16540 | ||
5db94019 | 16541 | if (IS_GEN2(dev_priv)) { |
a6c45cf0 CW |
16542 | dev->mode_config.max_width = 2048; |
16543 | dev->mode_config.max_height = 2048; | |
5db94019 | 16544 | } else if (IS_GEN3(dev_priv)) { |
5e4d6fa7 KP |
16545 | dev->mode_config.max_width = 4096; |
16546 | dev->mode_config.max_height = 4096; | |
79e53945 | 16547 | } else { |
a6c45cf0 CW |
16548 | dev->mode_config.max_width = 8192; |
16549 | dev->mode_config.max_height = 8192; | |
79e53945 | 16550 | } |
068be561 | 16551 | |
2a307c2e JN |
16552 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { |
16553 | dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512; | |
dc41c154 | 16554 | dev->mode_config.cursor_height = 1023; |
5db94019 | 16555 | } else if (IS_GEN2(dev_priv)) { |
068be561 DL |
16556 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
16557 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
16558 | } else { | |
16559 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
16560 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
16561 | } | |
16562 | ||
72e96d64 | 16563 | dev->mode_config.fb_base = ggtt->mappable_base; |
79e53945 | 16564 | |
28c97730 | 16565 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
b7f05d4a TU |
16566 | INTEL_INFO(dev_priv)->num_pipes, |
16567 | INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 16568 | |
055e393f | 16569 | for_each_pipe(dev_priv, pipe) { |
b079bd17 VS |
16570 | int ret; |
16571 | ||
5ab0d85b | 16572 | ret = intel_crtc_init(dev_priv, pipe); |
b079bd17 VS |
16573 | if (ret) { |
16574 | drm_mode_config_cleanup(dev); | |
16575 | return ret; | |
16576 | } | |
79e53945 JB |
16577 | } |
16578 | ||
bfa7df01 | 16579 | intel_update_czclk(dev_priv); |
4c75b940 | 16580 | intel_update_cdclk(dev_priv); |
6a259b1f | 16581 | dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq; |
bfa7df01 | 16582 | |
e72f9fbf | 16583 | intel_shared_dpll_init(dev); |
ee7b9f93 | 16584 | |
b2045352 | 16585 | if (dev_priv->max_cdclk_freq == 0) |
4c75b940 | 16586 | intel_update_max_cdclk(dev_priv); |
b2045352 | 16587 | |
9cce37f4 | 16588 | /* Just disable it once at startup */ |
29b74b7f | 16589 | i915_disable_vga(dev_priv); |
c39055b0 | 16590 | intel_setup_outputs(dev_priv); |
11be49eb | 16591 | |
6e9f798d | 16592 | drm_modeset_lock_all(dev); |
043e9bda | 16593 | intel_modeset_setup_hw_state(dev); |
6e9f798d | 16594 | drm_modeset_unlock_all(dev); |
46f297fb | 16595 | |
d3fcc808 | 16596 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
16597 | struct intel_initial_plane_config plane_config = {}; |
16598 | ||
46f297fb JB |
16599 | if (!crtc->active) |
16600 | continue; | |
16601 | ||
46f297fb | 16602 | /* |
46f297fb JB |
16603 | * Note that reserving the BIOS fb up front prevents us |
16604 | * from stuffing other stolen allocations like the ring | |
16605 | * on top. This prevents some ugliness at boot time, and | |
16606 | * can even allow for smooth boot transitions if the BIOS | |
16607 | * fb is large enough for the active pipe configuration. | |
16608 | */ | |
eeebeac5 ML |
16609 | dev_priv->display.get_initial_plane_config(crtc, |
16610 | &plane_config); | |
16611 | ||
16612 | /* | |
16613 | * If the fb is shared between multiple heads, we'll | |
16614 | * just get the first one. | |
16615 | */ | |
16616 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 16617 | } |
d93c0372 MR |
16618 | |
16619 | /* | |
16620 | * Make sure hardware watermarks really match the state we read out. | |
16621 | * Note that we need to do this after reconstructing the BIOS fb's | |
16622 | * since the watermark calculation done here will use pstate->fb. | |
16623 | */ | |
16624 | sanitize_watermarks(dev); | |
b079bd17 VS |
16625 | |
16626 | return 0; | |
2c7111db CW |
16627 | } |
16628 | ||
7fad798e DV |
16629 | static void intel_enable_pipe_a(struct drm_device *dev) |
16630 | { | |
16631 | struct intel_connector *connector; | |
16632 | struct drm_connector *crt = NULL; | |
16633 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 16634 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
16635 | |
16636 | /* We can't just switch on the pipe A, we need to set things up with a | |
16637 | * proper mode and output configuration. As a gross hack, enable pipe A | |
16638 | * by enabling the load detect pipe once. */ | |
3a3371ff | 16639 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
16640 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
16641 | crt = &connector->base; | |
16642 | break; | |
16643 | } | |
16644 | } | |
16645 | ||
16646 | if (!crt) | |
16647 | return; | |
16648 | ||
208bf9fd | 16649 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 16650 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
16651 | } |
16652 | ||
fa555837 DV |
16653 | static bool |
16654 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
16655 | { | |
b7f05d4a | 16656 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
649636ef | 16657 | u32 val; |
fa555837 | 16658 | |
b7f05d4a | 16659 | if (INTEL_INFO(dev_priv)->num_pipes == 1) |
fa555837 DV |
16660 | return true; |
16661 | ||
649636ef | 16662 | val = I915_READ(DSPCNTR(!crtc->plane)); |
fa555837 DV |
16663 | |
16664 | if ((val & DISPLAY_PLANE_ENABLE) && | |
16665 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
16666 | return false; | |
16667 | ||
16668 | return true; | |
16669 | } | |
16670 | ||
02e93c35 VS |
16671 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
16672 | { | |
16673 | struct drm_device *dev = crtc->base.dev; | |
16674 | struct intel_encoder *encoder; | |
16675 | ||
16676 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
16677 | return true; | |
16678 | ||
16679 | return false; | |
16680 | } | |
16681 | ||
496b0fc3 ML |
16682 | static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder) |
16683 | { | |
16684 | struct drm_device *dev = encoder->base.dev; | |
16685 | struct intel_connector *connector; | |
16686 | ||
16687 | for_each_connector_on_encoder(dev, &encoder->base, connector) | |
16688 | return connector; | |
16689 | ||
16690 | return NULL; | |
16691 | } | |
16692 | ||
a168f5b3 VS |
16693 | static bool has_pch_trancoder(struct drm_i915_private *dev_priv, |
16694 | enum transcoder pch_transcoder) | |
16695 | { | |
16696 | return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) || | |
16697 | (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A); | |
16698 | } | |
16699 | ||
24929352 DV |
16700 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
16701 | { | |
16702 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 16703 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 | 16704 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
24929352 | 16705 | |
24929352 | 16706 | /* Clear any frame start delays used for debugging left by the BIOS */ |
4d1de975 JN |
16707 | if (!transcoder_is_dsi(cpu_transcoder)) { |
16708 | i915_reg_t reg = PIPECONF(cpu_transcoder); | |
16709 | ||
16710 | I915_WRITE(reg, | |
16711 | I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); | |
16712 | } | |
24929352 | 16713 | |
d3eaf884 | 16714 | /* restore vblank interrupts to correct state */ |
9625604c | 16715 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 16716 | if (crtc->active) { |
f9cd7b88 VS |
16717 | struct intel_plane *plane; |
16718 | ||
9625604c | 16719 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
16720 | |
16721 | /* Disable everything but the primary plane */ | |
16722 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
16723 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
16724 | continue; | |
16725 | ||
16726 | plane->disable_plane(&plane->base, &crtc->base); | |
16727 | } | |
9625604c | 16728 | } |
d3eaf884 | 16729 | |
24929352 | 16730 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
16731 | * disable the crtc (and hence change the state) if it is wrong. Note |
16732 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
6315b5d3 | 16733 | if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) { |
24929352 DV |
16734 | bool plane; |
16735 | ||
78108b7c VS |
16736 | DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n", |
16737 | crtc->base.base.id, crtc->base.name); | |
24929352 DV |
16738 | |
16739 | /* Pipe has the wrong plane attached and the plane is active. | |
16740 | * Temporarily change the plane mapping and disable everything | |
16741 | * ... */ | |
16742 | plane = crtc->plane; | |
936e71e3 | 16743 | to_intel_plane_state(crtc->base.primary->state)->base.visible = true; |
24929352 | 16744 | crtc->plane = !plane; |
b17d48e2 | 16745 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 16746 | crtc->plane = plane; |
24929352 | 16747 | } |
24929352 | 16748 | |
7fad798e DV |
16749 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
16750 | crtc->pipe == PIPE_A && !crtc->active) { | |
16751 | /* BIOS forgot to enable pipe A, this mostly happens after | |
16752 | * resume. Force-enable the pipe to fix this, the update_dpms | |
16753 | * call below we restore the pipe to the right state, but leave | |
16754 | * the required bits on. */ | |
16755 | intel_enable_pipe_a(dev); | |
16756 | } | |
16757 | ||
24929352 DV |
16758 | /* Adjust the state of the output pipe according to whether we |
16759 | * have active connectors/encoders. */ | |
842e0307 | 16760 | if (crtc->active && !intel_crtc_has_encoders(crtc)) |
b17d48e2 | 16761 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 16762 | |
49cff963 | 16763 | if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) { |
4cc31489 DV |
16764 | /* |
16765 | * We start out with underrun reporting disabled to avoid races. | |
16766 | * For correct bookkeeping mark this on active crtcs. | |
16767 | * | |
c5ab3bc0 DV |
16768 | * Also on gmch platforms we dont have any hardware bits to |
16769 | * disable the underrun reporting. Which means we need to start | |
16770 | * out with underrun reporting disabled also on inactive pipes, | |
16771 | * since otherwise we'll complain about the garbage we read when | |
16772 | * e.g. coming up after runtime pm. | |
16773 | * | |
4cc31489 DV |
16774 | * No protection against concurrent access is required - at |
16775 | * worst a fifo underrun happens which also sets this to false. | |
16776 | */ | |
16777 | crtc->cpu_fifo_underrun_disabled = true; | |
a168f5b3 VS |
16778 | /* |
16779 | * We track the PCH trancoder underrun reporting state | |
16780 | * within the crtc. With crtc for pipe A housing the underrun | |
16781 | * reporting state for PCH transcoder A, crtc for pipe B housing | |
16782 | * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A, | |
16783 | * and marking underrun reporting as disabled for the non-existing | |
16784 | * PCH transcoders B and C would prevent enabling the south | |
16785 | * error interrupt (see cpt_can_enable_serr_int()). | |
16786 | */ | |
16787 | if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe)) | |
16788 | crtc->pch_fifo_underrun_disabled = true; | |
4cc31489 | 16789 | } |
24929352 DV |
16790 | } |
16791 | ||
16792 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
16793 | { | |
16794 | struct intel_connector *connector; | |
24929352 DV |
16795 | |
16796 | /* We need to check both for a crtc link (meaning that the | |
16797 | * encoder is active and trying to read from a pipe) and the | |
16798 | * pipe itself being active. */ | |
16799 | bool has_active_crtc = encoder->base.crtc && | |
16800 | to_intel_crtc(encoder->base.crtc)->active; | |
16801 | ||
496b0fc3 ML |
16802 | connector = intel_encoder_find_connector(encoder); |
16803 | if (connector && !has_active_crtc) { | |
24929352 DV |
16804 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
16805 | encoder->base.base.id, | |
8e329a03 | 16806 | encoder->base.name); |
24929352 DV |
16807 | |
16808 | /* Connector is active, but has no active pipe. This is | |
16809 | * fallout from our resume register restoring. Disable | |
16810 | * the encoder manually again. */ | |
16811 | if (encoder->base.crtc) { | |
fd6bbda9 ML |
16812 | struct drm_crtc_state *crtc_state = encoder->base.crtc->state; |
16813 | ||
24929352 DV |
16814 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", |
16815 | encoder->base.base.id, | |
8e329a03 | 16816 | encoder->base.name); |
fd6bbda9 | 16817 | encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state); |
a62d1497 | 16818 | if (encoder->post_disable) |
fd6bbda9 | 16819 | encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state); |
24929352 | 16820 | } |
7f1950fb | 16821 | encoder->base.crtc = NULL; |
24929352 DV |
16822 | |
16823 | /* Inconsistent output/port/pipe state happens presumably due to | |
16824 | * a bug in one of the get_hw_state functions. Or someplace else | |
16825 | * in our code, like the register restore mess on resume. Clamp | |
16826 | * things to off as a safer default. */ | |
fd6bbda9 ML |
16827 | |
16828 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
16829 | connector->base.encoder = NULL; | |
24929352 DV |
16830 | } |
16831 | /* Enabled encoders without active connectors will be fixed in | |
16832 | * the crtc fixup. */ | |
16833 | } | |
16834 | ||
29b74b7f | 16835 | void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv) |
0fde901f | 16836 | { |
920a14b2 | 16837 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv); |
0fde901f | 16838 | |
04098753 ID |
16839 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
16840 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
29b74b7f | 16841 | i915_disable_vga(dev_priv); |
04098753 ID |
16842 | } |
16843 | } | |
16844 | ||
29b74b7f | 16845 | void i915_redisable_vga(struct drm_i915_private *dev_priv) |
04098753 | 16846 | { |
8dc8a27c PZ |
16847 | /* This function can be called both from intel_modeset_setup_hw_state or |
16848 | * at a very early point in our resume sequence, where the power well | |
16849 | * structures are not yet restored. Since this function is at a very | |
16850 | * paranoid "someone might have enabled VGA while we were not looking" | |
16851 | * level, just check if the power well is enabled instead of trying to | |
16852 | * follow the "don't touch the power well if we don't need it" policy | |
16853 | * the rest of the driver uses. */ | |
6392f847 | 16854 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
16855 | return; |
16856 | ||
29b74b7f | 16857 | i915_redisable_vga_power_on(dev_priv); |
6392f847 ID |
16858 | |
16859 | intel_display_power_put(dev_priv, POWER_DOMAIN_VGA); | |
0fde901f KM |
16860 | } |
16861 | ||
f9cd7b88 | 16862 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 16863 | { |
f9cd7b88 | 16864 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 16865 | |
f9cd7b88 | 16866 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
16867 | } |
16868 | ||
f9cd7b88 VS |
16869 | /* FIXME read out full plane state for all planes */ |
16870 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 16871 | { |
b26d3ea3 | 16872 | struct drm_plane *primary = crtc->base.primary; |
f9cd7b88 | 16873 | struct intel_plane_state *plane_state = |
b26d3ea3 | 16874 | to_intel_plane_state(primary->state); |
d032ffa0 | 16875 | |
936e71e3 | 16876 | plane_state->base.visible = crtc->active && |
b26d3ea3 ML |
16877 | primary_get_hw_state(to_intel_plane(primary)); |
16878 | ||
936e71e3 | 16879 | if (plane_state->base.visible) |
b26d3ea3 | 16880 | crtc->base.state->plane_mask |= 1 << drm_plane_index(primary); |
98ec7739 VS |
16881 | } |
16882 | ||
30e984df | 16883 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 | 16884 | { |
fac5e23e | 16885 | struct drm_i915_private *dev_priv = to_i915(dev); |
24929352 | 16886 | enum pipe pipe; |
24929352 DV |
16887 | struct intel_crtc *crtc; |
16888 | struct intel_encoder *encoder; | |
16889 | struct intel_connector *connector; | |
5358901f | 16890 | int i; |
24929352 | 16891 | |
565602d7 ML |
16892 | dev_priv->active_crtcs = 0; |
16893 | ||
d3fcc808 | 16894 | for_each_intel_crtc(dev, crtc) { |
565602d7 ML |
16895 | struct intel_crtc_state *crtc_state = crtc->config; |
16896 | int pixclk = 0; | |
3b117c8f | 16897 | |
ec2dc6a0 | 16898 | __drm_atomic_helper_crtc_destroy_state(&crtc_state->base); |
565602d7 ML |
16899 | memset(crtc_state, 0, sizeof(*crtc_state)); |
16900 | crtc_state->base.crtc = &crtc->base; | |
24929352 | 16901 | |
565602d7 ML |
16902 | crtc_state->base.active = crtc_state->base.enable = |
16903 | dev_priv->display.get_pipe_config(crtc, crtc_state); | |
16904 | ||
16905 | crtc->base.enabled = crtc_state->base.enable; | |
16906 | crtc->active = crtc_state->base.active; | |
16907 | ||
16908 | if (crtc_state->base.active) { | |
16909 | dev_priv->active_crtcs |= 1 << crtc->pipe; | |
16910 | ||
c89e39f3 | 16911 | if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) |
565602d7 | 16912 | pixclk = ilk_pipe_pixel_rate(crtc_state); |
9558d15d | 16913 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
565602d7 ML |
16914 | pixclk = crtc_state->base.adjusted_mode.crtc_clock; |
16915 | else | |
16916 | WARN_ON(dev_priv->display.modeset_calc_cdclk); | |
9558d15d VS |
16917 | |
16918 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
16919 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) | |
16920 | pixclk = DIV_ROUND_UP(pixclk * 100, 95); | |
565602d7 ML |
16921 | } |
16922 | ||
16923 | dev_priv->min_pixclk[crtc->pipe] = pixclk; | |
b70709a6 | 16924 | |
f9cd7b88 | 16925 | readout_plane_state(crtc); |
24929352 | 16926 | |
78108b7c VS |
16927 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n", |
16928 | crtc->base.base.id, crtc->base.name, | |
08c4d7fc | 16929 | enableddisabled(crtc->active)); |
24929352 DV |
16930 | } |
16931 | ||
5358901f DV |
16932 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
16933 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
16934 | ||
2edd6443 ACO |
16935 | pll->on = pll->funcs.get_hw_state(dev_priv, pll, |
16936 | &pll->config.hw_state); | |
3e369b76 | 16937 | pll->config.crtc_mask = 0; |
d3fcc808 | 16938 | for_each_intel_crtc(dev, crtc) { |
2dd66ebd | 16939 | if (crtc->active && crtc->config->shared_dpll == pll) |
3e369b76 | 16940 | pll->config.crtc_mask |= 1 << crtc->pipe; |
5358901f | 16941 | } |
2dd66ebd | 16942 | pll->active_mask = pll->config.crtc_mask; |
5358901f | 16943 | |
1e6f2ddc | 16944 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 16945 | pll->name, pll->config.crtc_mask, pll->on); |
5358901f DV |
16946 | } |
16947 | ||
b2784e15 | 16948 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
16949 | pipe = 0; |
16950 | ||
16951 | if (encoder->get_hw_state(encoder, &pipe)) { | |
98187836 | 16952 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
e2af48c6 | 16953 | |
045ac3b5 | 16954 | encoder->base.crtc = &crtc->base; |
253c84c8 | 16955 | crtc->config->output_types |= 1 << encoder->type; |
6e3c9717 | 16956 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
16957 | } else { |
16958 | encoder->base.crtc = NULL; | |
16959 | } | |
16960 | ||
6f2bcceb | 16961 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
08c4d7fc TU |
16962 | encoder->base.base.id, encoder->base.name, |
16963 | enableddisabled(encoder->base.crtc), | |
6f2bcceb | 16964 | pipe_name(pipe)); |
24929352 DV |
16965 | } |
16966 | ||
3a3371ff | 16967 | for_each_intel_connector(dev, connector) { |
24929352 DV |
16968 | if (connector->get_hw_state(connector)) { |
16969 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
2aa974c9 ML |
16970 | |
16971 | encoder = connector->encoder; | |
16972 | connector->base.encoder = &encoder->base; | |
16973 | ||
16974 | if (encoder->base.crtc && | |
16975 | encoder->base.crtc->state->active) { | |
16976 | /* | |
16977 | * This has to be done during hardware readout | |
16978 | * because anything calling .crtc_disable may | |
16979 | * rely on the connector_mask being accurate. | |
16980 | */ | |
16981 | encoder->base.crtc->state->connector_mask |= | |
16982 | 1 << drm_connector_index(&connector->base); | |
e87a52b3 ML |
16983 | encoder->base.crtc->state->encoder_mask |= |
16984 | 1 << drm_encoder_index(&encoder->base); | |
2aa974c9 ML |
16985 | } |
16986 | ||
24929352 DV |
16987 | } else { |
16988 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
16989 | connector->base.encoder = NULL; | |
16990 | } | |
16991 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
08c4d7fc TU |
16992 | connector->base.base.id, connector->base.name, |
16993 | enableddisabled(connector->base.encoder)); | |
24929352 | 16994 | } |
7f4c6284 VS |
16995 | |
16996 | for_each_intel_crtc(dev, crtc) { | |
16997 | crtc->base.hwmode = crtc->config->base.adjusted_mode; | |
16998 | ||
16999 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); | |
17000 | if (crtc->base.state->active) { | |
17001 | intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); | |
17002 | intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config); | |
17003 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); | |
17004 | ||
17005 | /* | |
17006 | * The initial mode needs to be set in order to keep | |
17007 | * the atomic core happy. It wants a valid mode if the | |
17008 | * crtc's enabled, so we do the above call. | |
17009 | * | |
17010 | * At this point some state updated by the connectors | |
17011 | * in their ->detect() callback has not run yet, so | |
17012 | * no recalculation can be done yet. | |
17013 | * | |
17014 | * Even if we could do a recalculation and modeset | |
17015 | * right now it would cause a double modeset if | |
17016 | * fbdev or userspace chooses a different initial mode. | |
17017 | * | |
17018 | * If that happens, someone indicated they wanted a | |
17019 | * mode change, which means it's safe to do a full | |
17020 | * recalculation. | |
17021 | */ | |
17022 | crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED; | |
9eca6832 VS |
17023 | |
17024 | drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); | |
17025 | update_scanline_offset(crtc); | |
7f4c6284 | 17026 | } |
e3b247da VS |
17027 | |
17028 | intel_pipe_config_sanity_check(dev_priv, crtc->config); | |
7f4c6284 | 17029 | } |
30e984df DV |
17030 | } |
17031 | ||
043e9bda ML |
17032 | /* Scan out the current hw modeset state, |
17033 | * and sanitizes it to the current state | |
17034 | */ | |
17035 | static void | |
17036 | intel_modeset_setup_hw_state(struct drm_device *dev) | |
30e984df | 17037 | { |
fac5e23e | 17038 | struct drm_i915_private *dev_priv = to_i915(dev); |
30e984df | 17039 | enum pipe pipe; |
30e984df DV |
17040 | struct intel_crtc *crtc; |
17041 | struct intel_encoder *encoder; | |
35c95375 | 17042 | int i; |
30e984df DV |
17043 | |
17044 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
17045 | |
17046 | /* HW state is read out, now we need to sanitize this mess. */ | |
b2784e15 | 17047 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
17048 | intel_sanitize_encoder(encoder); |
17049 | } | |
17050 | ||
055e393f | 17051 | for_each_pipe(dev_priv, pipe) { |
98187836 | 17052 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
e2af48c6 | 17053 | |
24929352 | 17054 | intel_sanitize_crtc(crtc); |
6e3c9717 ACO |
17055 | intel_dump_pipe_config(crtc, crtc->config, |
17056 | "[setup_hw_state]"); | |
24929352 | 17057 | } |
9a935856 | 17058 | |
d29b2f9d ACO |
17059 | intel_modeset_update_connector_atomic_state(dev); |
17060 | ||
35c95375 DV |
17061 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
17062 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
17063 | ||
2dd66ebd | 17064 | if (!pll->on || pll->active_mask) |
35c95375 DV |
17065 | continue; |
17066 | ||
17067 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
17068 | ||
2edd6443 | 17069 | pll->funcs.disable(dev_priv, pll); |
35c95375 DV |
17070 | pll->on = false; |
17071 | } | |
17072 | ||
920a14b2 | 17073 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
6eb1a681 | 17074 | vlv_wm_get_hw_state(dev); |
5db94019 | 17075 | else if (IS_GEN9(dev_priv)) |
3078999f | 17076 | skl_wm_get_hw_state(dev); |
6e266956 | 17077 | else if (HAS_PCH_SPLIT(dev_priv)) |
243e6a44 | 17078 | ilk_wm_get_hw_state(dev); |
292b990e ML |
17079 | |
17080 | for_each_intel_crtc(dev, crtc) { | |
17081 | unsigned long put_domains; | |
17082 | ||
74bff5f9 | 17083 | put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config); |
292b990e ML |
17084 | if (WARN_ON(put_domains)) |
17085 | modeset_put_power_domains(dev_priv, put_domains); | |
17086 | } | |
17087 | intel_display_set_init_power(dev_priv, false); | |
010cf73d PZ |
17088 | |
17089 | intel_fbc_init_pipe_state(dev_priv); | |
043e9bda | 17090 | } |
7d0bc1ea | 17091 | |
043e9bda ML |
17092 | void intel_display_resume(struct drm_device *dev) |
17093 | { | |
e2c8b870 ML |
17094 | struct drm_i915_private *dev_priv = to_i915(dev); |
17095 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
17096 | struct drm_modeset_acquire_ctx ctx; | |
043e9bda | 17097 | int ret; |
f30da187 | 17098 | |
e2c8b870 | 17099 | dev_priv->modeset_restore_state = NULL; |
73974893 ML |
17100 | if (state) |
17101 | state->acquire_ctx = &ctx; | |
043e9bda | 17102 | |
ea49c9ac ML |
17103 | /* |
17104 | * This is a cludge because with real atomic modeset mode_config.mutex | |
17105 | * won't be taken. Unfortunately some probed state like | |
17106 | * audio_codec_enable is still protected by mode_config.mutex, so lock | |
17107 | * it here for now. | |
17108 | */ | |
17109 | mutex_lock(&dev->mode_config.mutex); | |
e2c8b870 | 17110 | drm_modeset_acquire_init(&ctx, 0); |
043e9bda | 17111 | |
73974893 ML |
17112 | while (1) { |
17113 | ret = drm_modeset_lock_all_ctx(dev, &ctx); | |
17114 | if (ret != -EDEADLK) | |
17115 | break; | |
043e9bda | 17116 | |
e2c8b870 | 17117 | drm_modeset_backoff(&ctx); |
e2c8b870 | 17118 | } |
043e9bda | 17119 | |
73974893 ML |
17120 | if (!ret) |
17121 | ret = __intel_display_resume(dev, state); | |
17122 | ||
e2c8b870 ML |
17123 | drm_modeset_drop_locks(&ctx); |
17124 | drm_modeset_acquire_fini(&ctx); | |
ea49c9ac | 17125 | mutex_unlock(&dev->mode_config.mutex); |
043e9bda | 17126 | |
0853695c | 17127 | if (ret) |
e2c8b870 | 17128 | DRM_ERROR("Restoring old state failed with %i\n", ret); |
0853695c | 17129 | drm_atomic_state_put(state); |
2c7111db CW |
17130 | } |
17131 | ||
17132 | void intel_modeset_gem_init(struct drm_device *dev) | |
17133 | { | |
dc97997a | 17134 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd | 17135 | struct drm_crtc *c; |
2ff8fde1 | 17136 | struct drm_i915_gem_object *obj; |
484b41dd | 17137 | |
dc97997a | 17138 | intel_init_gt_powersave(dev_priv); |
ae48434c | 17139 | |
1833b134 | 17140 | intel_modeset_init_hw(dev); |
02e792fb | 17141 | |
1ee8da6d | 17142 | intel_setup_overlay(dev_priv); |
484b41dd JB |
17143 | |
17144 | /* | |
17145 | * Make sure any fbs we allocated at startup are properly | |
17146 | * pinned & fenced. When we do the allocation it's too early | |
17147 | * for this. | |
17148 | */ | |
70e1e0ec | 17149 | for_each_crtc(dev, c) { |
058d88c4 CW |
17150 | struct i915_vma *vma; |
17151 | ||
2ff8fde1 MR |
17152 | obj = intel_fb_obj(c->primary->fb); |
17153 | if (obj == NULL) | |
484b41dd JB |
17154 | continue; |
17155 | ||
e0d6149b | 17156 | mutex_lock(&dev->struct_mutex); |
058d88c4 | 17157 | vma = intel_pin_and_fence_fb_obj(c->primary->fb, |
3465c580 | 17158 | c->primary->state->rotation); |
e0d6149b | 17159 | mutex_unlock(&dev->struct_mutex); |
058d88c4 | 17160 | if (IS_ERR(vma)) { |
484b41dd JB |
17161 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
17162 | to_intel_crtc(c)->pipe); | |
66e514c1 | 17163 | drm_framebuffer_unreference(c->primary->fb); |
5a21b665 | 17164 | c->primary->fb = NULL; |
36750f28 | 17165 | c->primary->crtc = c->primary->state->crtc = NULL; |
5a21b665 | 17166 | update_state_fb(c->primary); |
36750f28 | 17167 | c->state->plane_mask &= ~(1 << drm_plane_index(c->primary)); |
484b41dd JB |
17168 | } |
17169 | } | |
1ebaa0b9 CW |
17170 | } |
17171 | ||
17172 | int intel_connector_register(struct drm_connector *connector) | |
17173 | { | |
17174 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
17175 | int ret; | |
17176 | ||
17177 | ret = intel_backlight_device_register(intel_connector); | |
17178 | if (ret) | |
17179 | goto err; | |
17180 | ||
17181 | return 0; | |
0962c3c9 | 17182 | |
1ebaa0b9 CW |
17183 | err: |
17184 | return ret; | |
79e53945 JB |
17185 | } |
17186 | ||
c191eca1 | 17187 | void intel_connector_unregister(struct drm_connector *connector) |
4932e2c3 | 17188 | { |
e63d87c0 | 17189 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4932e2c3 | 17190 | |
e63d87c0 | 17191 | intel_backlight_device_unregister(intel_connector); |
4932e2c3 | 17192 | intel_panel_destroy_backlight(connector); |
4932e2c3 ID |
17193 | } |
17194 | ||
79e53945 JB |
17195 | void intel_modeset_cleanup(struct drm_device *dev) |
17196 | { | |
fac5e23e | 17197 | struct drm_i915_private *dev_priv = to_i915(dev); |
652c393a | 17198 | |
dc97997a | 17199 | intel_disable_gt_powersave(dev_priv); |
2eb5252e | 17200 | |
fd0c0642 DV |
17201 | /* |
17202 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 17203 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
17204 | * experience fancy races otherwise. |
17205 | */ | |
2aeb7d3a | 17206 | intel_irq_uninstall(dev_priv); |
eb21b92b | 17207 | |
fd0c0642 DV |
17208 | /* |
17209 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
17210 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
17211 | */ | |
f87ea761 | 17212 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 17213 | |
723bfd70 JB |
17214 | intel_unregister_dsm_handler(); |
17215 | ||
c937ab3e | 17216 | intel_fbc_global_disable(dev_priv); |
69341a5e | 17217 | |
1630fe75 CW |
17218 | /* flush any delayed tasks or pending work */ |
17219 | flush_scheduled_work(); | |
17220 | ||
79e53945 | 17221 | drm_mode_config_cleanup(dev); |
4d7bb011 | 17222 | |
1ee8da6d | 17223 | intel_cleanup_overlay(dev_priv); |
ae48434c | 17224 | |
dc97997a | 17225 | intel_cleanup_gt_powersave(dev_priv); |
f5949141 | 17226 | |
40196446 | 17227 | intel_teardown_gmbus(dev_priv); |
79e53945 JB |
17228 | } |
17229 | ||
df0e9248 CW |
17230 | void intel_connector_attach_encoder(struct intel_connector *connector, |
17231 | struct intel_encoder *encoder) | |
17232 | { | |
17233 | connector->encoder = encoder; | |
17234 | drm_mode_connector_attach_encoder(&connector->base, | |
17235 | &encoder->base); | |
79e53945 | 17236 | } |
28d52043 DA |
17237 | |
17238 | /* | |
17239 | * set vga decode state - true == enable VGA decode | |
17240 | */ | |
6315b5d3 | 17241 | int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state) |
28d52043 | 17242 | { |
6315b5d3 | 17243 | unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
17244 | u16 gmch_ctrl; |
17245 | ||
75fa041d CW |
17246 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
17247 | DRM_ERROR("failed to read control word\n"); | |
17248 | return -EIO; | |
17249 | } | |
17250 | ||
c0cc8a55 CW |
17251 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
17252 | return 0; | |
17253 | ||
28d52043 DA |
17254 | if (state) |
17255 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
17256 | else | |
17257 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
17258 | |
17259 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
17260 | DRM_ERROR("failed to write control word\n"); | |
17261 | return -EIO; | |
17262 | } | |
17263 | ||
28d52043 DA |
17264 | return 0; |
17265 | } | |
c4a1d9e4 | 17266 | |
98a2f411 CW |
17267 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
17268 | ||
c4a1d9e4 | 17269 | struct intel_display_error_state { |
ff57f1b0 PZ |
17270 | |
17271 | u32 power_well_driver; | |
17272 | ||
63b66e5b CW |
17273 | int num_transcoders; |
17274 | ||
c4a1d9e4 CW |
17275 | struct intel_cursor_error_state { |
17276 | u32 control; | |
17277 | u32 position; | |
17278 | u32 base; | |
17279 | u32 size; | |
52331309 | 17280 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
17281 | |
17282 | struct intel_pipe_error_state { | |
ddf9c536 | 17283 | bool power_domain_on; |
c4a1d9e4 | 17284 | u32 source; |
f301b1e1 | 17285 | u32 stat; |
52331309 | 17286 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
17287 | |
17288 | struct intel_plane_error_state { | |
17289 | u32 control; | |
17290 | u32 stride; | |
17291 | u32 size; | |
17292 | u32 pos; | |
17293 | u32 addr; | |
17294 | u32 surface; | |
17295 | u32 tile_offset; | |
52331309 | 17296 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
17297 | |
17298 | struct intel_transcoder_error_state { | |
ddf9c536 | 17299 | bool power_domain_on; |
63b66e5b CW |
17300 | enum transcoder cpu_transcoder; |
17301 | ||
17302 | u32 conf; | |
17303 | ||
17304 | u32 htotal; | |
17305 | u32 hblank; | |
17306 | u32 hsync; | |
17307 | u32 vtotal; | |
17308 | u32 vblank; | |
17309 | u32 vsync; | |
17310 | } transcoder[4]; | |
c4a1d9e4 CW |
17311 | }; |
17312 | ||
17313 | struct intel_display_error_state * | |
c033666a | 17314 | intel_display_capture_error_state(struct drm_i915_private *dev_priv) |
c4a1d9e4 | 17315 | { |
c4a1d9e4 | 17316 | struct intel_display_error_state *error; |
63b66e5b CW |
17317 | int transcoders[] = { |
17318 | TRANSCODER_A, | |
17319 | TRANSCODER_B, | |
17320 | TRANSCODER_C, | |
17321 | TRANSCODER_EDP, | |
17322 | }; | |
c4a1d9e4 CW |
17323 | int i; |
17324 | ||
c033666a | 17325 | if (INTEL_INFO(dev_priv)->num_pipes == 0) |
63b66e5b CW |
17326 | return NULL; |
17327 | ||
9d1cb914 | 17328 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
17329 | if (error == NULL) |
17330 | return NULL; | |
17331 | ||
c033666a | 17332 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
ff57f1b0 PZ |
17333 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
17334 | ||
055e393f | 17335 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 17336 | error->pipe[i].power_domain_on = |
f458ebbc DV |
17337 | __intel_display_power_is_enabled(dev_priv, |
17338 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 17339 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
17340 | continue; |
17341 | ||
5efb3e28 VS |
17342 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
17343 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
17344 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
17345 | |
17346 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
17347 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
c033666a | 17348 | if (INTEL_GEN(dev_priv) <= 3) { |
51889b35 | 17349 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
17350 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
17351 | } | |
c033666a | 17352 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
ca291363 | 17353 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
c033666a | 17354 | if (INTEL_GEN(dev_priv) >= 4) { |
c4a1d9e4 CW |
17355 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
17356 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
17357 | } | |
17358 | ||
c4a1d9e4 | 17359 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 17360 | |
c033666a | 17361 | if (HAS_GMCH_DISPLAY(dev_priv)) |
f301b1e1 | 17362 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
17363 | } |
17364 | ||
4d1de975 | 17365 | /* Note: this does not include DSI transcoders. */ |
c033666a | 17366 | error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes; |
2d1fe073 | 17367 | if (HAS_DDI(dev_priv)) |
63b66e5b CW |
17368 | error->num_transcoders++; /* Account for eDP. */ |
17369 | ||
17370 | for (i = 0; i < error->num_transcoders; i++) { | |
17371 | enum transcoder cpu_transcoder = transcoders[i]; | |
17372 | ||
ddf9c536 | 17373 | error->transcoder[i].power_domain_on = |
f458ebbc | 17374 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 17375 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 17376 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
17377 | continue; |
17378 | ||
63b66e5b CW |
17379 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
17380 | ||
17381 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
17382 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
17383 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
17384 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
17385 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
17386 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
17387 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
17388 | } |
17389 | ||
17390 | return error; | |
17391 | } | |
17392 | ||
edc3d884 MK |
17393 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
17394 | ||
c4a1d9e4 | 17395 | void |
edc3d884 | 17396 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
5f56d5f9 | 17397 | struct drm_i915_private *dev_priv, |
c4a1d9e4 CW |
17398 | struct intel_display_error_state *error) |
17399 | { | |
17400 | int i; | |
17401 | ||
63b66e5b CW |
17402 | if (!error) |
17403 | return; | |
17404 | ||
b7f05d4a | 17405 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes); |
8652744b | 17406 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
edc3d884 | 17407 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 17408 | error->power_well_driver); |
055e393f | 17409 | for_each_pipe(dev_priv, i) { |
edc3d884 | 17410 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 | 17411 | err_printf(m, " Power: %s\n", |
87ad3212 | 17412 | onoff(error->pipe[i].power_domain_on)); |
edc3d884 | 17413 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 17414 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
17415 | |
17416 | err_printf(m, "Plane [%d]:\n", i); | |
17417 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
17418 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
5f56d5f9 | 17419 | if (INTEL_GEN(dev_priv) <= 3) { |
edc3d884 MK |
17420 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
17421 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 17422 | } |
772c2a51 | 17423 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
edc3d884 | 17424 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
5f56d5f9 | 17425 | if (INTEL_GEN(dev_priv) >= 4) { |
edc3d884 MK |
17426 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
17427 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
17428 | } |
17429 | ||
edc3d884 MK |
17430 | err_printf(m, "Cursor [%d]:\n", i); |
17431 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
17432 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
17433 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 17434 | } |
63b66e5b CW |
17435 | |
17436 | for (i = 0; i < error->num_transcoders; i++) { | |
da205630 | 17437 | err_printf(m, "CPU transcoder: %s\n", |
63b66e5b | 17438 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 | 17439 | err_printf(m, " Power: %s\n", |
87ad3212 | 17440 | onoff(error->transcoder[i].power_domain_on)); |
63b66e5b CW |
17441 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
17442 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
17443 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
17444 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
17445 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
17446 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
17447 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
17448 | } | |
c4a1d9e4 | 17449 | } |
98a2f411 CW |
17450 | |
17451 | #endif |