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drm/i915: Don't set a MBZ bit in gen2/3 MI_FLUSH
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
23b2f8bb 28#include <linux/cpufreq.h>
c1c7af60
JB		 29#include <linux/module.h>
30#include <linux/input.h>
79e53945 31#include <linux/i2c.h>
7662c8bd 32#include <linux/kernel.h>
5a0e3ad6 33#include <linux/slab.h>
9cce37f4 34#include <linux/vgaarb.h>
e0dac65e 35#include <drm/drm_edid.h>
79e53945
JB		 36#include "drmP.h"
37#include "intel_drv.h"
38#include "i915_drm.h"
39#include "i915_drv.h"
e5510fac 40#include "i915_trace.h"
ab2c0672 41#include "drm_dp_helper.h"
79e53945 42#include "drm_crtc_helper.h"
c0f372b3 43#include <linux/dma_remapping.h>
79e53945 44
32f9d658
ZW		 45#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
46
0206e353 47bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 48static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 49static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 50
51typedef struct {
0206e353
AJ		 52 /* given values */
53 int n;
54 int m1, m2;
55 int p1, p2;
56 /* derived values */
57 int dot;
58 int vco;
59 int m;
60 int p;
79e53945
JB		 61} intel_clock_t;
62
63typedef struct {
0206e353 64 int min, max;
79e53945
JB		 65} intel_range_t;
66
67typedef struct {
0206e353
AJ		 68 int dot_limit;
69 int p2_slow, p2_fast;
79e53945
JB		 70} intel_p2_t;
71
72#define INTEL_P2_NUM 2
d4906093
ML		 73typedef struct intel_limit intel_limit_t;
74struct intel_limit {
0206e353
AJ		 75 intel_range_t dot, vco, n, m, m1, m2, p, p1;
76 intel_p2_t p2;
77 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 78 int, int, intel_clock_t *, intel_clock_t *);
d4906093 79};
79e53945 80
2377b741
JB		 81/* FDI */
82#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
83
d4906093
ML		 84static bool
85intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 86 int target, int refclk, intel_clock_t *match_clock,
87 intel_clock_t *best_clock);
d4906093
ML		 88static bool
89intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 90 int target, int refclk, intel_clock_t *match_clock,
91 intel_clock_t *best_clock);
79e53945 92
a4fc5ed6
KP		 93static bool
94intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 95 int target, int refclk, intel_clock_t *match_clock,
96 intel_clock_t *best_clock);
5eb08b69 97static bool
f2b115e6 98intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 99 int target, int refclk, intel_clock_t *match_clock,
100 intel_clock_t *best_clock);
a4fc5ed6 101
021357ac
CW		 102static inline u32 /* units of 100MHz */
103intel_fdi_link_freq(struct drm_device *dev)
104{
8b99e68c
CW		 105 if (IS_GEN5(dev)) {
106 struct drm_i915_private *dev_priv = dev->dev_private;
107 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
108 } else
109 return 27;
021357ac
CW		 110}
111
e4b36699 112static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 113 .dot = { .min = 25000, .max = 350000 },
114 .vco = { .min = 930000, .max = 1400000 },
115 .n = { .min = 3, .max = 16 },
116 .m = { .min = 96, .max = 140 },
117 .m1 = { .min = 18, .max = 26 },
118 .m2 = { .min = 6, .max = 16 },
119 .p = { .min = 4, .max = 128 },
120 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 121 .p2 = { .dot_limit = 165000,
122 .p2_slow = 4, .p2_fast = 2 },
d4906093 123 .find_pll = intel_find_best_PLL,
e4b36699
KP		 124};
125
126static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 127 .dot = { .min = 25000, .max = 350000 },
128 .vco = { .min = 930000, .max = 1400000 },
129 .n = { .min = 3, .max = 16 },
130 .m = { .min = 96, .max = 140 },
131 .m1 = { .min = 18, .max = 26 },
132 .m2 = { .min = 6, .max = 16 },
133 .p = { .min = 4, .max = 128 },
134 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 135 .p2 = { .dot_limit = 165000,
136 .p2_slow = 14, .p2_fast = 7 },
d4906093 137 .find_pll = intel_find_best_PLL,
e4b36699 138};
273e27ca 139
e4b36699 140static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 141 .dot = { .min = 20000, .max = 400000 },
142 .vco = { .min = 1400000, .max = 2800000 },
143 .n = { .min = 1, .max = 6 },
144 .m = { .min = 70, .max = 120 },
145 .m1 = { .min = 10, .max = 22 },
146 .m2 = { .min = 5, .max = 9 },
147 .p = { .min = 5, .max = 80 },
148 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 149 .p2 = { .dot_limit = 200000,
150 .p2_slow = 10, .p2_fast = 5 },
d4906093 151 .find_pll = intel_find_best_PLL,
e4b36699
KP		 152};
153
154static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 155 .dot = { .min = 20000, .max = 400000 },
156 .vco = { .min = 1400000, .max = 2800000 },
157 .n = { .min = 1, .max = 6 },
158 .m = { .min = 70, .max = 120 },
159 .m1 = { .min = 10, .max = 22 },
160 .m2 = { .min = 5, .max = 9 },
161 .p = { .min = 7, .max = 98 },
162 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 163 .p2 = { .dot_limit = 112000,
164 .p2_slow = 14, .p2_fast = 7 },
d4906093 165 .find_pll = intel_find_best_PLL,
e4b36699
KP		 166};
167
273e27ca 168
e4b36699 169static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 170 .dot = { .min = 25000, .max = 270000 },
171 .vco = { .min = 1750000, .max = 3500000},
172 .n = { .min = 1, .max = 4 },
173 .m = { .min = 104, .max = 138 },
174 .m1 = { .min = 17, .max = 23 },
175 .m2 = { .min = 5, .max = 11 },
176 .p = { .min = 10, .max = 30 },
177 .p1 = { .min = 1, .max = 3},
178 .p2 = { .dot_limit = 270000,
179 .p2_slow = 10,
180 .p2_fast = 10
044c7c41 181 },
d4906093 182 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 183};
184
185static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 186 .dot = { .min = 22000, .max = 400000 },
187 .vco = { .min = 1750000, .max = 3500000},
188 .n = { .min = 1, .max = 4 },
189 .m = { .min = 104, .max = 138 },
190 .m1 = { .min = 16, .max = 23 },
191 .m2 = { .min = 5, .max = 11 },
192 .p = { .min = 5, .max = 80 },
193 .p1 = { .min = 1, .max = 8},
194 .p2 = { .dot_limit = 165000,
195 .p2_slow = 10, .p2_fast = 5 },
d4906093 196 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 197};
198
199static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 200 .dot = { .min = 20000, .max = 115000 },
201 .vco = { .min = 1750000, .max = 3500000 },
202 .n = { .min = 1, .max = 3 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 17, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 28, .max = 112 },
207 .p1 = { .min = 2, .max = 8 },
208 .p2 = { .dot_limit = 0,
209 .p2_slow = 14, .p2_fast = 14
044c7c41 210 },
d4906093 211 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 212};
213
214static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 215 .dot = { .min = 80000, .max = 224000 },
216 .vco = { .min = 1750000, .max = 3500000 },
217 .n = { .min = 1, .max = 3 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 14, .max = 42 },
222 .p1 = { .min = 2, .max = 6 },
223 .p2 = { .dot_limit = 0,
224 .p2_slow = 7, .p2_fast = 7
044c7c41 225 },
d4906093 226 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 227};
228
229static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 230 .dot = { .min = 161670, .max = 227000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 2 },
233 .m = { .min = 97, .max = 108 },
234 .m1 = { .min = 0x10, .max = 0x12 },
235 .m2 = { .min = 0x05, .max = 0x06 },
236 .p = { .min = 10, .max = 20 },
237 .p1 = { .min = 1, .max = 2},
238 .p2 = { .dot_limit = 0,
273e27ca 239 .p2_slow = 10, .p2_fast = 10 },
0206e353 240 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 241};
242
f2b115e6 243static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 244 .dot = { .min = 20000, .max = 400000},
245 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 246 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 247 .n = { .min = 3, .max = 6 },
248 .m = { .min = 2, .max = 256 },
273e27ca 249 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 250 .m1 = { .min = 0, .max = 0 },
251 .m2 = { .min = 0, .max = 254 },
252 .p = { .min = 5, .max = 80 },
253 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 254 .p2 = { .dot_limit = 200000,
255 .p2_slow = 10, .p2_fast = 5 },
6115707b 256 .find_pll = intel_find_best_PLL,
e4b36699
KP		 257};
258
f2b115e6 259static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 260 .dot = { .min = 20000, .max = 400000 },
261 .vco = { .min = 1700000, .max = 3500000 },
262 .n = { .min = 3, .max = 6 },
263 .m = { .min = 2, .max = 256 },
264 .m1 = { .min = 0, .max = 0 },
265 .m2 = { .min = 0, .max = 254 },
266 .p = { .min = 7, .max = 112 },
267 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 268 .p2 = { .dot_limit = 112000,
269 .p2_slow = 14, .p2_fast = 14 },
6115707b 270 .find_pll = intel_find_best_PLL,
e4b36699
KP		 271};
272
273e27ca
EA		 273/* Ironlake / Sandybridge
274 *
275 * We calculate clock using (register_value + 2) for N/M1/M2, so here
276 * the range value for them is (actual_value - 2).
277 */
b91ad0ec 278static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 279 .dot = { .min = 25000, .max = 350000 },
280 .vco = { .min = 1760000, .max = 3510000 },
281 .n = { .min = 1, .max = 5 },
282 .m = { .min = 79, .max = 127 },
283 .m1 = { .min = 12, .max = 22 },
284 .m2 = { .min = 5, .max = 9 },
285 .p = { .min = 5, .max = 80 },
286 .p1 = { .min = 1, .max = 8 },
287 .p2 = { .dot_limit = 225000,
288 .p2_slow = 10, .p2_fast = 5 },
4547668a 289 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 290};
291
b91ad0ec 292static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 293 .dot = { .min = 25000, .max = 350000 },
294 .vco = { .min = 1760000, .max = 3510000 },
295 .n = { .min = 1, .max = 3 },
296 .m = { .min = 79, .max = 118 },
297 .m1 = { .min = 12, .max = 22 },
298 .m2 = { .min = 5, .max = 9 },
299 .p = { .min = 28, .max = 112 },
300 .p1 = { .min = 2, .max = 8 },
301 .p2 = { .dot_limit = 225000,
302 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 303 .find_pll = intel_g4x_find_best_PLL,
304};
305
306static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 3 },
310 .m = { .min = 79, .max = 127 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 14, .max = 56 },
314 .p1 = { .min = 2, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 317 .find_pll = intel_g4x_find_best_PLL,
318};
319
273e27ca 320/* LVDS 100mhz refclk limits. */
b91ad0ec 321static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 322 .dot = { .min = 25000, .max = 350000 },
323 .vco = { .min = 1760000, .max = 3510000 },
324 .n = { .min = 1, .max = 2 },
325 .m = { .min = 79, .max = 126 },
326 .m1 = { .min = 12, .max = 22 },
327 .m2 = { .min = 5, .max = 9 },
328 .p = { .min = 28, .max = 112 },
0206e353 329 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 330 .p2 = { .dot_limit = 225000,
331 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 332 .find_pll = intel_g4x_find_best_PLL,
333};
334
335static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 336 .dot = { .min = 25000, .max = 350000 },
337 .vco = { .min = 1760000, .max = 3510000 },
338 .n = { .min = 1, .max = 3 },
339 .m = { .min = 79, .max = 126 },
340 .m1 = { .min = 12, .max = 22 },
341 .m2 = { .min = 5, .max = 9 },
342 .p = { .min = 14, .max = 42 },
0206e353 343 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 344 .p2 = { .dot_limit = 225000,
345 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 346 .find_pll = intel_g4x_find_best_PLL,
347};
348
349static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000},
352 .n = { .min = 1, .max = 2 },
353 .m = { .min = 81, .max = 90 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 10, .max = 20 },
357 .p1 = { .min = 1, .max = 2},
358 .p2 = { .dot_limit = 0,
273e27ca 359 .p2_slow = 10, .p2_fast = 10 },
0206e353 360 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 361};
362
57f350b6
JB		 363u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
364{
365 unsigned long flags;
366 u32 val = 0;
367
368 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
369 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
370 DRM_ERROR("DPIO idle wait timed out\n");
371 goto out_unlock;
372 }
373
374 I915_WRITE(DPIO_REG, reg);
375 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
376 DPIO_BYTE);
377 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
378 DRM_ERROR("DPIO read wait timed out\n");
379 goto out_unlock;
380 }
381 val = I915_READ(DPIO_DATA);
382
383out_unlock:
384 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
385 return val;
386}
387
388static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
389 u32 val)
390{
391 unsigned long flags;
392
393 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
394 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
395 DRM_ERROR("DPIO idle wait timed out\n");
396 goto out_unlock;
397 }
398
399 I915_WRITE(DPIO_DATA, val);
400 I915_WRITE(DPIO_REG, reg);
401 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
402 DPIO_BYTE);
403 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
404 DRM_ERROR("DPIO write wait timed out\n");
405
406out_unlock:
407 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
408}
409
410static void vlv_init_dpio(struct drm_device *dev)
411{
412 struct drm_i915_private *dev_priv = dev->dev_private;
413
414 /* Reset the DPIO config */
415 I915_WRITE(DPIO_CTL, 0);
416 POSTING_READ(DPIO_CTL);
417 I915_WRITE(DPIO_CTL, 1);
418 POSTING_READ(DPIO_CTL);
419}
420
618563e3
DV		 421static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
422{
423 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
424 return 1;
425}
426
427static const struct dmi_system_id intel_dual_link_lvds[] = {
428 {
429 .callback = intel_dual_link_lvds_callback,
430 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
431 .matches = {
432 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
433 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
434 },
435 },
436 { } /* terminating entry */
437};
438
b0354385
TI		 439static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
440 unsigned int reg)
441{
442 unsigned int val;
443
121d527a
TI		 444 /* use the module option value if specified */
445 if (i915_lvds_channel_mode > 0)
446 return i915_lvds_channel_mode == 2;
447
618563e3
DV		 448 if (dmi_check_system(intel_dual_link_lvds))
449 return true;
450
b0354385
TI		 451 if (dev_priv->lvds_val)
452 val = dev_priv->lvds_val;
453 else {
454 /* BIOS should set the proper LVDS register value at boot, but
455 * in reality, it doesn't set the value when the lid is closed;
456 * we need to check "the value to be set" in VBT when LVDS
457 * register is uninitialized.
458 */
459 val = I915_READ(reg);
460 if (!(val & ~LVDS_DETECTED))
461 val = dev_priv->bios_lvds_val;
462 dev_priv->lvds_val = val;
463 }
464 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
465}
466
1b894b59
CW		 467static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
468 int refclk)
2c07245f 469{
b91ad0ec
ZW		 470 struct drm_device *dev = crtc->dev;
471 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 472 const intel_limit_t *limit;
b91ad0ec
ZW		 473
474 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 475 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
b91ad0ec 476 /* LVDS dual channel */
1b894b59 477 if (refclk == 100000)
b91ad0ec
ZW		 478 limit = &intel_limits_ironlake_dual_lvds_100m;
479 else
480 limit = &intel_limits_ironlake_dual_lvds;
481 } else {
1b894b59 482 if (refclk == 100000)
b91ad0ec
ZW		 483 limit = &intel_limits_ironlake_single_lvds_100m;
484 else
485 limit = &intel_limits_ironlake_single_lvds;
486 }
487 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 488 HAS_eDP)
489 limit = &intel_limits_ironlake_display_port;
2c07245f 490 else
b91ad0ec 491 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 492
493 return limit;
494}
495
044c7c41
ML		 496static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
497{
498 struct drm_device *dev = crtc->dev;
499 struct drm_i915_private *dev_priv = dev->dev_private;
500 const intel_limit_t *limit;
501
502 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 503 if (is_dual_link_lvds(dev_priv, LVDS))
044c7c41 504 /* LVDS with dual channel */
e4b36699 505 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 506 else
507 /* LVDS with dual channel */
e4b36699 508 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 509 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
510 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 511 limit = &intel_limits_g4x_hdmi;
044c7c41 512 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 513 limit = &intel_limits_g4x_sdvo;
0206e353 514 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 515 limit = &intel_limits_g4x_display_port;
044c7c41 516 } else /* The option is for other outputs */
e4b36699 517 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 518
519 return limit;
520}
521
1b894b59 522static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 523{
524 struct drm_device *dev = crtc->dev;
525 const intel_limit_t *limit;
526
bad720ff 527 if (HAS_PCH_SPLIT(dev))
1b894b59 528 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 529 else if (IS_G4X(dev)) {
044c7c41 530 limit = intel_g4x_limit(crtc);
f2b115e6 531 } else if (IS_PINEVIEW(dev)) {
2177832f 532 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 533 limit = &intel_limits_pineview_lvds;
2177832f 534 else
f2b115e6 535 limit = &intel_limits_pineview_sdvo;
a6c45cf0
CW		 536 } else if (!IS_GEN2(dev)) {
537 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
538 limit = &intel_limits_i9xx_lvds;
539 else
540 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 541 } else {
542 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 543 limit = &intel_limits_i8xx_lvds;
79e53945 544 else
e4b36699 545 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 546 }
547 return limit;
548}
549
f2b115e6
AJ		 550/* m1 is reserved as 0 in Pineview, n is a ring counter */
551static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 552{
2177832f
SL		 553 clock->m = clock->m2 + 2;
554 clock->p = clock->p1 * clock->p2;
555 clock->vco = refclk * clock->m / clock->n;
556 clock->dot = clock->vco / clock->p;
557}
558
559static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
560{
f2b115e6
AJ		 561 if (IS_PINEVIEW(dev)) {
562 pineview_clock(refclk, clock);
2177832f
SL		 563 return;
564 }
79e53945
JB		 565 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
566 clock->p = clock->p1 * clock->p2;
567 clock->vco = refclk * clock->m / (clock->n + 2);
568 clock->dot = clock->vco / clock->p;
569}
570
79e53945
JB		 571/**
572 * Returns whether any output on the specified pipe is of the specified type
573 */
4ef69c7a 574bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 575{
4ef69c7a
CW		 576 struct drm_device *dev = crtc->dev;
577 struct drm_mode_config *mode_config = &dev->mode_config;
578 struct intel_encoder *encoder;
579
580 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
581 if (encoder->base.crtc == crtc && encoder->type == type)
582 return true;
583
584 return false;
79e53945
JB		 585}
586
7c04d1d9 587#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 588/**
589 * Returns whether the given set of divisors are valid for a given refclk with
590 * the given connectors.
591 */
592
1b894b59
CW		 593static bool intel_PLL_is_valid(struct drm_device *dev,
594 const intel_limit_t *limit,
595 const intel_clock_t *clock)
79e53945 596{
79e53945 597 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 598 INTELPllInvalid("p1 out of range\n");
79e53945 599 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 600 INTELPllInvalid("p out of range\n");
79e53945 601 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 602 INTELPllInvalid("m2 out of range\n");
79e53945 603 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 604 INTELPllInvalid("m1 out of range\n");
f2b115e6 605 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 606 INTELPllInvalid("m1 <= m2\n");
79e53945 607 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 608 INTELPllInvalid("m out of range\n");
79e53945 609 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 610 INTELPllInvalid("n out of range\n");
79e53945 611 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 612 INTELPllInvalid("vco out of range\n");
79e53945
JB		 613 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
614 * connector, etc., rather than just a single range.
615 */
616 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 617 INTELPllInvalid("dot out of range\n");
79e53945
JB		 618
619 return true;
620}
621
d4906093
ML		 622static bool
623intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 624 int target, int refclk, intel_clock_t *match_clock,
625 intel_clock_t *best_clock)
d4906093 626
79e53945
JB		 627{
628 struct drm_device *dev = crtc->dev;
629 struct drm_i915_private *dev_priv = dev->dev_private;
630 intel_clock_t clock;
79e53945
JB		 631 int err = target;
632
bc5e5718 633 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 634 (I915_READ(LVDS)) != 0) {
79e53945
JB		 635 /*
636 * For LVDS, if the panel is on, just rely on its current
637 * settings for dual-channel. We haven't figured out how to
638 * reliably set up different single/dual channel state, if we
639 * even can.
640 */
b0354385 641 if (is_dual_link_lvds(dev_priv, LVDS))
79e53945
JB		 642 clock.p2 = limit->p2.p2_fast;
643 else
644 clock.p2 = limit->p2.p2_slow;
645 } else {
646 if (target < limit->p2.dot_limit)
647 clock.p2 = limit->p2.p2_slow;
648 else
649 clock.p2 = limit->p2.p2_fast;
650 }
651
0206e353 652 memset(best_clock, 0, sizeof(*best_clock));
79e53945 653
42158660
ZY		 654 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
655 clock.m1++) {
656 for (clock.m2 = limit->m2.min;
657 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 658 /* m1 is always 0 in Pineview */
659 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 660 break;
661 for (clock.n = limit->n.min;
662 clock.n <= limit->n.max; clock.n++) {
663 for (clock.p1 = limit->p1.min;
664 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 665 int this_err;
666
2177832f 667 intel_clock(dev, refclk, &clock);
1b894b59
CW		 668 if (!intel_PLL_is_valid(dev, limit,
669 &clock))
79e53945 670 continue;
cec2f356
SP		 671 if (match_clock &&
672 clock.p != match_clock->p)
673 continue;
79e53945
JB		 674
675 this_err = abs(clock.dot - target);
676 if (this_err < err) {
677 *best_clock = clock;
678 err = this_err;
679 }
680 }
681 }
682 }
683 }
684
685 return (err != target);
686}
687
d4906093
ML		 688static bool
689intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 690 int target, int refclk, intel_clock_t *match_clock,
691 intel_clock_t *best_clock)
d4906093
ML		 692{
693 struct drm_device *dev = crtc->dev;
694 struct drm_i915_private *dev_priv = dev->dev_private;
695 intel_clock_t clock;
696 int max_n;
697 bool found;
6ba770dc
AJ		 698 /* approximately equals target * 0.00585 */
699 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 700 found = false;
701
702 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 703 int lvds_reg;
704
c619eed4 705 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 706 lvds_reg = PCH_LVDS;
707 else
708 lvds_reg = LVDS;
709 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 710 LVDS_CLKB_POWER_UP)
711 clock.p2 = limit->p2.p2_fast;
712 else
713 clock.p2 = limit->p2.p2_slow;
714 } else {
715 if (target < limit->p2.dot_limit)
716 clock.p2 = limit->p2.p2_slow;
717 else
718 clock.p2 = limit->p2.p2_fast;
719 }
720
721 memset(best_clock, 0, sizeof(*best_clock));
722 max_n = limit->n.max;
f77f13e2 723 /* based on hardware requirement, prefer smaller n to precision */
d4906093 724 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 725 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 726 for (clock.m1 = limit->m1.max;
727 clock.m1 >= limit->m1.min; clock.m1--) {
728 for (clock.m2 = limit->m2.max;
729 clock.m2 >= limit->m2.min; clock.m2--) {
730 for (clock.p1 = limit->p1.max;
731 clock.p1 >= limit->p1.min; clock.p1--) {
732 int this_err;
733
2177832f 734 intel_clock(dev, refclk, &clock);
1b894b59
CW		 735 if (!intel_PLL_is_valid(dev, limit,
736 &clock))
d4906093 737 continue;
cec2f356
SP		 738 if (match_clock &&
739 clock.p != match_clock->p)
740 continue;
1b894b59
CW		 741
742 this_err = abs(clock.dot - target);
d4906093
ML		 743 if (this_err < err_most) {
744 *best_clock = clock;
745 err_most = this_err;
746 max_n = clock.n;
747 found = true;
748 }
749 }
750 }
751 }
752 }
2c07245f
ZW		 753 return found;
754}
755
5eb08b69 756static bool
f2b115e6 757intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 758 int target, int refclk, intel_clock_t *match_clock,
759 intel_clock_t *best_clock)
5eb08b69
ZW		 760{
761 struct drm_device *dev = crtc->dev;
762 intel_clock_t clock;
4547668a 763
5eb08b69
ZW		 764 if (target < 200000) {
765 clock.n = 1;
766 clock.p1 = 2;
767 clock.p2 = 10;
768 clock.m1 = 12;
769 clock.m2 = 9;
770 } else {
771 clock.n = 2;
772 clock.p1 = 1;
773 clock.p2 = 10;
774 clock.m1 = 14;
775 clock.m2 = 8;
776 }
777 intel_clock(dev, refclk, &clock);
778 memcpy(best_clock, &clock, sizeof(intel_clock_t));
779 return true;
780}
781
a4fc5ed6
KP		 782/* DisplayPort has only two frequencies, 162MHz and 270MHz */
783static bool
784intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 785 int target, int refclk, intel_clock_t *match_clock,
786 intel_clock_t *best_clock)
a4fc5ed6 787{
5eddb70b
CW		 788 intel_clock_t clock;
789 if (target < 200000) {
790 clock.p1 = 2;
791 clock.p2 = 10;
792 clock.n = 2;
793 clock.m1 = 23;
794 clock.m2 = 8;
795 } else {
796 clock.p1 = 1;
797 clock.p2 = 10;
798 clock.n = 1;
799 clock.m1 = 14;
800 clock.m2 = 2;
801 }
802 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
803 clock.p = (clock.p1 * clock.p2);
804 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
805 clock.vco = 0;
806 memcpy(best_clock, &clock, sizeof(intel_clock_t));
807 return true;
a4fc5ed6
KP		 808}
809
9d0498a2
JB		 810/**
811 * intel_wait_for_vblank - wait for vblank on a given pipe
812 * @dev: drm device
813 * @pipe: pipe to wait for
814 *
815 * Wait for vblank to occur on a given pipe. Needed for various bits of
816 * mode setting code.
817 */
818void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 819{
9d0498a2 820 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 821 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 822
300387c0
CW		 823 /* Clear existing vblank status. Note this will clear any other
824 * sticky status fields as well.
825 *
826 * This races with i915_driver_irq_handler() with the result
827 * that either function could miss a vblank event. Here it is not
828 * fatal, as we will either wait upon the next vblank interrupt or
829 * timeout. Generally speaking intel_wait_for_vblank() is only
830 * called during modeset at which time the GPU should be idle and
831 * should *not* be performing page flips and thus not waiting on
832 * vblanks...
833 * Currently, the result of us stealing a vblank from the irq
834 * handler is that a single frame will be skipped during swapbuffers.
835 */
836 I915_WRITE(pipestat_reg,
837 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
838
9d0498a2 839 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 840 if (wait_for(I915_READ(pipestat_reg) &
841 PIPE_VBLANK_INTERRUPT_STATUS,
842 50))
9d0498a2
JB		 843 DRM_DEBUG_KMS("vblank wait timed out\n");
844}
845
ab7ad7f6
KP		 846/*
847 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 848 * @dev: drm device
849 * @pipe: pipe to wait for
850 *
851 * After disabling a pipe, we can't wait for vblank in the usual way,
852 * spinning on the vblank interrupt status bit, since we won't actually
853 * see an interrupt when the pipe is disabled.
854 *
ab7ad7f6
KP		 855 * On Gen4 and above:
856 * wait for the pipe register state bit to turn off
857 *
858 * Otherwise:
859 * wait for the display line value to settle (it usually
860 * ends up stopping at the start of the next frame).
58e10eb9 861 *
9d0498a2 862 */
58e10eb9 863void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 864{
865 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 866
867 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 868 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 869
870 /* Wait for the Pipe State to go off */
58e10eb9
CW		 871 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
872 100))
ab7ad7f6
KP		 873 DRM_DEBUG_KMS("pipe_off wait timed out\n");
874 } else {
875 u32 last_line;
58e10eb9 876 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 877 unsigned long timeout = jiffies + msecs_to_jiffies(100);
878
879 /* Wait for the display line to settle */
880 do {
58e10eb9 881 last_line = I915_READ(reg) & DSL_LINEMASK;
ab7ad7f6 882 mdelay(5);
58e10eb9 883 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
ab7ad7f6
KP		 884 time_after(timeout, jiffies));
885 if (time_after(jiffies, timeout))
886 DRM_DEBUG_KMS("pipe_off wait timed out\n");
887 }
79e53945
JB		 888}
889
b24e7179
JB		 890static const char *state_string(bool enabled)
891{
892 return enabled ? "on" : "off";
893}
894
895/* Only for pre-ILK configs */
896static void assert_pll(struct drm_i915_private *dev_priv,
897 enum pipe pipe, bool state)
898{
899 int reg;
900 u32 val;
901 bool cur_state;
902
903 reg = DPLL(pipe);
904 val = I915_READ(reg);
905 cur_state = !!(val & DPLL_VCO_ENABLE);
906 WARN(cur_state != state,
907 "PLL state assertion failure (expected %s, current %s)\n",
908 state_string(state), state_string(cur_state));
909}
910#define assert_pll_enabled(d, p) assert_pll(d, p, true)
911#define assert_pll_disabled(d, p) assert_pll(d, p, false)
912
040484af
JB		 913/* For ILK+ */
914static void assert_pch_pll(struct drm_i915_private *dev_priv,
915 enum pipe pipe, bool state)
916{
917 int reg;
918 u32 val;
919 bool cur_state;
920
d3ccbe86
JB		 921 if (HAS_PCH_CPT(dev_priv->dev)) {
922 u32 pch_dpll;
923
924 pch_dpll = I915_READ(PCH_DPLL_SEL);
925
926 /* Make sure the selected PLL is enabled to the transcoder */
927 WARN(!((pch_dpll >> (4 * pipe)) & 8),
928 "transcoder %d PLL not enabled\n", pipe);
929
930 /* Convert the transcoder pipe number to a pll pipe number */
931 pipe = (pch_dpll >> (4 * pipe)) & 1;
932 }
933
040484af
JB		 934 reg = PCH_DPLL(pipe);
935 val = I915_READ(reg);
936 cur_state = !!(val & DPLL_VCO_ENABLE);
937 WARN(cur_state != state,
938 "PCH PLL state assertion failure (expected %s, current %s)\n",
939 state_string(state), state_string(cur_state));
940}
941#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
942#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
943
944static void assert_fdi_tx(struct drm_i915_private *dev_priv,
945 enum pipe pipe, bool state)
946{
947 int reg;
948 u32 val;
949 bool cur_state;
950
951 reg = FDI_TX_CTL(pipe);
952 val = I915_READ(reg);
953 cur_state = !!(val & FDI_TX_ENABLE);
954 WARN(cur_state != state,
955 "FDI TX state assertion failure (expected %s, current %s)\n",
956 state_string(state), state_string(cur_state));
957}
958#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
959#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
960
961static void assert_fdi_rx(struct drm_i915_private *dev_priv,
962 enum pipe pipe, bool state)
963{
964 int reg;
965 u32 val;
966 bool cur_state;
967
968 reg = FDI_RX_CTL(pipe);
969 val = I915_READ(reg);
970 cur_state = !!(val & FDI_RX_ENABLE);
971 WARN(cur_state != state,
972 "FDI RX state assertion failure (expected %s, current %s)\n",
973 state_string(state), state_string(cur_state));
974}
975#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
976#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
977
978static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
979 enum pipe pipe)
980{
981 int reg;
982 u32 val;
983
984 /* ILK FDI PLL is always enabled */
985 if (dev_priv->info->gen == 5)
986 return;
987
988 reg = FDI_TX_CTL(pipe);
989 val = I915_READ(reg);
990 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
991}
992
993static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
994 enum pipe pipe)
995{
996 int reg;
997 u32 val;
998
999 reg = FDI_RX_CTL(pipe);
1000 val = I915_READ(reg);
1001 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1002}
1003
ea0760cf
JB		 1004static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1005 enum pipe pipe)
1006{
1007 int pp_reg, lvds_reg;
1008 u32 val;
1009 enum pipe panel_pipe = PIPE_A;
0de3b485 1010 bool locked = true;
ea0760cf
JB		 1011
1012 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1013 pp_reg = PCH_PP_CONTROL;
1014 lvds_reg = PCH_LVDS;
1015 } else {
1016 pp_reg = PP_CONTROL;
1017 lvds_reg = LVDS;
1018 }
1019
1020 val = I915_READ(pp_reg);
1021 if (!(val & PANEL_POWER_ON) ||
1022 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1023 locked = false;
1024
1025 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1026 panel_pipe = PIPE_B;
1027
1028 WARN(panel_pipe == pipe && locked,
1029 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1030 pipe_name(pipe));
ea0760cf
JB		 1031}
1032
b840d907
JB		 1033void assert_pipe(struct drm_i915_private *dev_priv,
1034 enum pipe pipe, bool state)
b24e7179
JB		 1035{
1036 int reg;
1037 u32 val;
63d7bbe9 1038 bool cur_state;
b24e7179 1039
8e636784
DV		 1040 /* if we need the pipe A quirk it must be always on */
1041 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1042 state = true;
1043
b24e7179
JB		 1044 reg = PIPECONF(pipe);
1045 val = I915_READ(reg);
63d7bbe9
JB		 1046 cur_state = !!(val & PIPECONF_ENABLE);
1047 WARN(cur_state != state,
1048 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1049 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1050}
1051
931872fc
CW		 1052static void assert_plane(struct drm_i915_private *dev_priv,
1053 enum plane plane, bool state)
b24e7179
JB		 1054{
1055 int reg;
1056 u32 val;
931872fc 1057 bool cur_state;
b24e7179
JB		 1058
1059 reg = DSPCNTR(plane);
1060 val = I915_READ(reg);
931872fc
CW		 1061 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1062 WARN(cur_state != state,
1063 "plane %c assertion failure (expected %s, current %s)\n",
1064 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1065}
1066
931872fc
CW		 1067#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1068#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1069
b24e7179
JB		 1070static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1071 enum pipe pipe)
1072{
1073 int reg, i;
1074 u32 val;
1075 int cur_pipe;
1076
19ec1358 1077 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1078 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1079 reg = DSPCNTR(pipe);
1080 val = I915_READ(reg);
1081 WARN((val & DISPLAY_PLANE_ENABLE),
1082 "plane %c assertion failure, should be disabled but not\n",
1083 plane_name(pipe));
19ec1358 1084 return;
28c05794 1085 }
19ec1358 1086
b24e7179
JB		 1087 /* Need to check both planes against the pipe */
1088 for (i = 0; i < 2; i++) {
1089 reg = DSPCNTR(i);
1090 val = I915_READ(reg);
1091 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1092 DISPPLANE_SEL_PIPE_SHIFT;
1093 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1094 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1095 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1096 }
1097}
1098
92f2584a
JB		 1099static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1100{
1101 u32 val;
1102 bool enabled;
1103
1104 val = I915_READ(PCH_DREF_CONTROL);
1105 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1106 DREF_SUPERSPREAD_SOURCE_MASK));
1107 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1108}
1109
1110static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1111 enum pipe pipe)
1112{
1113 int reg;
1114 u32 val;
1115 bool enabled;
1116
1117 reg = TRANSCONF(pipe);
1118 val = I915_READ(reg);
1119 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1120 WARN(enabled,
1121 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1122 pipe_name(pipe));
92f2584a
JB		 1123}
1124
4e634389
KP		 1125static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1126 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1127{
1128 if ((val & DP_PORT_EN) == 0)
1129 return false;
1130
1131 if (HAS_PCH_CPT(dev_priv->dev)) {
1132 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1133 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1134 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1135 return false;
1136 } else {
1137 if ((val & DP_PIPE_MASK) != (pipe << 30))
1138 return false;
1139 }
1140 return true;
1141}
1142
1519b995
KP		 1143static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1144 enum pipe pipe, u32 val)
1145{
1146 if ((val & PORT_ENABLE) == 0)
1147 return false;
1148
1149 if (HAS_PCH_CPT(dev_priv->dev)) {
1150 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1151 return false;
1152 } else {
1153 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1154 return false;
1155 }
1156 return true;
1157}
1158
1159static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1160 enum pipe pipe, u32 val)
1161{
1162 if ((val & LVDS_PORT_EN) == 0)
1163 return false;
1164
1165 if (HAS_PCH_CPT(dev_priv->dev)) {
1166 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1167 return false;
1168 } else {
1169 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1170 return false;
1171 }
1172 return true;
1173}
1174
1175static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1176 enum pipe pipe, u32 val)
1177{
1178 if ((val & ADPA_DAC_ENABLE) == 0)
1179 return false;
1180 if (HAS_PCH_CPT(dev_priv->dev)) {
1181 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1182 return false;
1183 } else {
1184 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1185 return false;
1186 }
1187 return true;
1188}
1189
291906f1 1190static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1191 enum pipe pipe, int reg, u32 port_sel)
291906f1 1192{
47a05eca 1193 u32 val = I915_READ(reg);
4e634389 1194 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1195 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1196 reg, pipe_name(pipe));
291906f1
JB		 1197}
1198
1199static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1200 enum pipe pipe, int reg)
1201{
47a05eca 1202 u32 val = I915_READ(reg);
1519b995 1203 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
23c99e77 1204 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1205 reg, pipe_name(pipe));
291906f1
JB		 1206}
1207
1208static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1209 enum pipe pipe)
1210{
1211 int reg;
1212 u32 val;
291906f1 1213
f0575e92
KP		 1214 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1215 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1216 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1217
1218 reg = PCH_ADPA;
1219 val = I915_READ(reg);
1519b995 1220 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
291906f1 1221 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1222 pipe_name(pipe));
291906f1
JB		 1223
1224 reg = PCH_LVDS;
1225 val = I915_READ(reg);
1519b995 1226 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
291906f1 1227 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1228 pipe_name(pipe));
291906f1
JB		 1229
1230 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1231 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1232 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1233}
1234
63d7bbe9
JB		 1235/**
1236 * intel_enable_pll - enable a PLL
1237 * @dev_priv: i915 private structure
1238 * @pipe: pipe PLL to enable
1239 *
1240 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1241 * make sure the PLL reg is writable first though, since the panel write
1242 * protect mechanism may be enabled.
1243 *
1244 * Note! This is for pre-ILK only.
1245 */
1246static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1247{
1248 int reg;
1249 u32 val;
1250
1251 /* No really, not for ILK+ */
1252 BUG_ON(dev_priv->info->gen >= 5);
1253
1254 /* PLL is protected by panel, make sure we can write it */
1255 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1256 assert_panel_unlocked(dev_priv, pipe);
1257
1258 reg = DPLL(pipe);
1259 val = I915_READ(reg);
1260 val |= DPLL_VCO_ENABLE;
1261
1262 /* We do this three times for luck */
1263 I915_WRITE(reg, val);
1264 POSTING_READ(reg);
1265 udelay(150); /* wait for warmup */
1266 I915_WRITE(reg, val);
1267 POSTING_READ(reg);
1268 udelay(150); /* wait for warmup */
1269 I915_WRITE(reg, val);
1270 POSTING_READ(reg);
1271 udelay(150); /* wait for warmup */
1272}
1273
1274/**
1275 * intel_disable_pll - disable a PLL
1276 * @dev_priv: i915 private structure
1277 * @pipe: pipe PLL to disable
1278 *
1279 * Disable the PLL for @pipe, making sure the pipe is off first.
1280 *
1281 * Note! This is for pre-ILK only.
1282 */
1283static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1284{
1285 int reg;
1286 u32 val;
1287
1288 /* Don't disable pipe A or pipe A PLLs if needed */
1289 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1290 return;
1291
1292 /* Make sure the pipe isn't still relying on us */
1293 assert_pipe_disabled(dev_priv, pipe);
1294
1295 reg = DPLL(pipe);
1296 val = I915_READ(reg);
1297 val &= ~DPLL_VCO_ENABLE;
1298 I915_WRITE(reg, val);
1299 POSTING_READ(reg);
1300}
1301
92f2584a
JB		 1302/**
1303 * intel_enable_pch_pll - enable PCH PLL
1304 * @dev_priv: i915 private structure
1305 * @pipe: pipe PLL to enable
1306 *
1307 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1308 * drives the transcoder clock.
1309 */
1310static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1311 enum pipe pipe)
1312{
1313 int reg;
1314 u32 val;
1315
4c609cb8
JB		 1316 if (pipe > 1)
1317 return;
1318
92f2584a
JB		 1319 /* PCH only available on ILK+ */
1320 BUG_ON(dev_priv->info->gen < 5);
1321
1322 /* PCH refclock must be enabled first */
1323 assert_pch_refclk_enabled(dev_priv);
1324
1325 reg = PCH_DPLL(pipe);
1326 val = I915_READ(reg);
1327 val |= DPLL_VCO_ENABLE;
1328 I915_WRITE(reg, val);
1329 POSTING_READ(reg);
1330 udelay(200);
1331}
1332
1333static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1334 enum pipe pipe)
1335{
1336 int reg;
7a419866
JB		 1337 u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL,
1338 pll_sel = TRANSC_DPLL_ENABLE;
92f2584a 1339
4c609cb8
JB		 1340 if (pipe > 1)
1341 return;
1342
92f2584a
JB		 1343 /* PCH only available on ILK+ */
1344 BUG_ON(dev_priv->info->gen < 5);
1345
1346 /* Make sure transcoder isn't still depending on us */
1347 assert_transcoder_disabled(dev_priv, pipe);
1348
7a419866
JB		 1349 if (pipe == 0)
1350 pll_sel |= TRANSC_DPLLA_SEL;
1351 else if (pipe == 1)
1352 pll_sel |= TRANSC_DPLLB_SEL;
1353
1354
1355 if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel)
1356 return;
1357
92f2584a
JB		 1358 reg = PCH_DPLL(pipe);
1359 val = I915_READ(reg);
1360 val &= ~DPLL_VCO_ENABLE;
1361 I915_WRITE(reg, val);
1362 POSTING_READ(reg);
1363 udelay(200);
1364}
1365
040484af
JB		 1366static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1367 enum pipe pipe)
1368{
1369 int reg;
5f7f726d 1370 u32 val, pipeconf_val;
7c26e5c6 1371 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
040484af
JB		 1372
1373 /* PCH only available on ILK+ */
1374 BUG_ON(dev_priv->info->gen < 5);
1375
1376 /* Make sure PCH DPLL is enabled */
1377 assert_pch_pll_enabled(dev_priv, pipe);
1378
1379 /* FDI must be feeding us bits for PCH ports */
1380 assert_fdi_tx_enabled(dev_priv, pipe);
1381 assert_fdi_rx_enabled(dev_priv, pipe);
1382
1383 reg = TRANSCONF(pipe);
1384 val = I915_READ(reg);
5f7f726d 1385 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1386
1387 if (HAS_PCH_IBX(dev_priv->dev)) {
1388 /*
1389 * make the BPC in transcoder be consistent with
1390 * that in pipeconf reg.
1391 */
1392 val &= ~PIPE_BPC_MASK;
5f7f726d 1393 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1394 }
5f7f726d
PZ		 1395
1396 val &= ~TRANS_INTERLACE_MASK;
1397 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1398 if (HAS_PCH_IBX(dev_priv->dev) &&
1399 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1400 val |= TRANS_LEGACY_INTERLACED_ILK;
1401 else
1402 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1403 else
1404 val |= TRANS_PROGRESSIVE;
1405
040484af
JB		 1406 I915_WRITE(reg, val | TRANS_ENABLE);
1407 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1408 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1409}
1410
1411static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1412 enum pipe pipe)
1413{
1414 int reg;
1415 u32 val;
1416
1417 /* FDI relies on the transcoder */
1418 assert_fdi_tx_disabled(dev_priv, pipe);
1419 assert_fdi_rx_disabled(dev_priv, pipe);
1420
291906f1
JB		 1421 /* Ports must be off as well */
1422 assert_pch_ports_disabled(dev_priv, pipe);
1423
040484af
JB		 1424 reg = TRANSCONF(pipe);
1425 val = I915_READ(reg);
1426 val &= ~TRANS_ENABLE;
1427 I915_WRITE(reg, val);
1428 /* wait for PCH transcoder off, transcoder state */
1429 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1430 DRM_ERROR("failed to disable transcoder %d\n", pipe);
040484af
JB		 1431}
1432
b24e7179 1433/**
309cfea8 1434 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1435 * @dev_priv: i915 private structure
1436 * @pipe: pipe to enable
040484af 1437 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1438 *
1439 * Enable @pipe, making sure that various hardware specific requirements
1440 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1441 *
1442 * @pipe should be %PIPE_A or %PIPE_B.
1443 *
1444 * Will wait until the pipe is actually running (i.e. first vblank) before
1445 * returning.
1446 */
040484af
JB		 1447static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1448 bool pch_port)
b24e7179
JB		 1449{
1450 int reg;
1451 u32 val;
1452
1453 /*
1454 * A pipe without a PLL won't actually be able to drive bits from
1455 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1456 * need the check.
1457 */
1458 if (!HAS_PCH_SPLIT(dev_priv->dev))
1459 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1460 else {
1461 if (pch_port) {
1462 /* if driving the PCH, we need FDI enabled */
1463 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1464 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1465 }
1466 /* FIXME: assert CPU port conditions for SNB+ */
1467 }
b24e7179
JB		 1468
1469 reg = PIPECONF(pipe);
1470 val = I915_READ(reg);
00d70b15
CW		 1471 if (val & PIPECONF_ENABLE)
1472 return;
1473
1474 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1475 intel_wait_for_vblank(dev_priv->dev, pipe);
1476}
1477
1478/**
309cfea8 1479 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1480 * @dev_priv: i915 private structure
1481 * @pipe: pipe to disable
1482 *
1483 * Disable @pipe, making sure that various hardware specific requirements
1484 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1485 *
1486 * @pipe should be %PIPE_A or %PIPE_B.
1487 *
1488 * Will wait until the pipe has shut down before returning.
1489 */
1490static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1491 enum pipe pipe)
1492{
1493 int reg;
1494 u32 val;
1495
1496 /*
1497 * Make sure planes won't keep trying to pump pixels to us,
1498 * or we might hang the display.
1499 */
1500 assert_planes_disabled(dev_priv, pipe);
1501
1502 /* Don't disable pipe A or pipe A PLLs if needed */
1503 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1504 return;
1505
1506 reg = PIPECONF(pipe);
1507 val = I915_READ(reg);
00d70b15
CW		 1508 if ((val & PIPECONF_ENABLE) == 0)
1509 return;
1510
1511 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1512 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1513}
1514
d74362c9
KP		 1515/*
1516 * Plane regs are double buffered, going from enabled->disabled needs a
1517 * trigger in order to latch. The display address reg provides this.
1518 */
1519static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1520 enum plane plane)
1521{
1522 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1523 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1524}
1525
b24e7179
JB		 1526/**
1527 * intel_enable_plane - enable a display plane on a given pipe
1528 * @dev_priv: i915 private structure
1529 * @plane: plane to enable
1530 * @pipe: pipe being fed
1531 *
1532 * Enable @plane on @pipe, making sure that @pipe is running first.
1533 */
1534static void intel_enable_plane(struct drm_i915_private *dev_priv,
1535 enum plane plane, enum pipe pipe)
1536{
1537 int reg;
1538 u32 val;
1539
1540 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1541 assert_pipe_enabled(dev_priv, pipe);
1542
1543 reg = DSPCNTR(plane);
1544 val = I915_READ(reg);
00d70b15
CW		 1545 if (val & DISPLAY_PLANE_ENABLE)
1546 return;
1547
1548 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1549 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1550 intel_wait_for_vblank(dev_priv->dev, pipe);
1551}
1552
b24e7179
JB		 1553/**
1554 * intel_disable_plane - disable a display plane
1555 * @dev_priv: i915 private structure
1556 * @plane: plane to disable
1557 * @pipe: pipe consuming the data
1558 *
1559 * Disable @plane; should be an independent operation.
1560 */
1561static void intel_disable_plane(struct drm_i915_private *dev_priv,
1562 enum plane plane, enum pipe pipe)
1563{
1564 int reg;
1565 u32 val;
1566
1567 reg = DSPCNTR(plane);
1568 val = I915_READ(reg);
00d70b15
CW		 1569 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1570 return;
1571
1572 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1573 intel_flush_display_plane(dev_priv, plane);
1574 intel_wait_for_vblank(dev_priv->dev, pipe);
1575}
1576
47a05eca 1577static void disable_pch_dp(struct drm_i915_private *dev_priv,
f0575e92 1578 enum pipe pipe, int reg, u32 port_sel)
47a05eca
JB		 1579{
1580 u32 val = I915_READ(reg);
4e634389 1581 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
f0575e92 1582 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
47a05eca 1583 I915_WRITE(reg, val & ~DP_PORT_EN);
f0575e92 1584 }
47a05eca
JB		 1585}
1586
1587static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1588 enum pipe pipe, int reg)
1589{
1590 u32 val = I915_READ(reg);
1519b995 1591 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
f0575e92
KP		 1592 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1593 reg, pipe);
47a05eca 1594 I915_WRITE(reg, val & ~PORT_ENABLE);
f0575e92 1595 }
47a05eca
JB		 1596}
1597
1598/* Disable any ports connected to this transcoder */
1599static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1600 enum pipe pipe)
1601{
1602 u32 reg, val;
1603
1604 val = I915_READ(PCH_PP_CONTROL);
1605 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1606
f0575e92
KP		 1607 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1608 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1609 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
47a05eca
JB		 1610
1611 reg = PCH_ADPA;
1612 val = I915_READ(reg);
1519b995 1613 if (adpa_pipe_enabled(dev_priv, val, pipe))
47a05eca
JB		 1614 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1615
1616 reg = PCH_LVDS;
1617 val = I915_READ(reg);
1519b995
KP		 1618 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1619 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
47a05eca
JB		 1620 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1621 POSTING_READ(reg);
1622 udelay(100);
1623 }
1624
1625 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1626 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1627 disable_pch_hdmi(dev_priv, pipe, HDMID);
1628}
1629
43a9539f
CW		 1630static void i8xx_disable_fbc(struct drm_device *dev)
1631{
1632 struct drm_i915_private *dev_priv = dev->dev_private;
1633 u32 fbc_ctl;
1634
1635 /* Disable compression */
1636 fbc_ctl = I915_READ(FBC_CONTROL);
1637 if ((fbc_ctl & FBC_CTL_EN) == 0)
1638 return;
1639
1640 fbc_ctl &= ~FBC_CTL_EN;
1641 I915_WRITE(FBC_CONTROL, fbc_ctl);
1642
1643 /* Wait for compressing bit to clear */
1644 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1645 DRM_DEBUG_KMS("FBC idle timed out\n");
1646 return;
1647 }
1648
1649 DRM_DEBUG_KMS("disabled FBC\n");
1650}
1651
80824003
JB		 1652static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1653{
1654 struct drm_device *dev = crtc->dev;
1655 struct drm_i915_private *dev_priv = dev->dev_private;
1656 struct drm_framebuffer *fb = crtc->fb;
1657 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1658 struct drm_i915_gem_object *obj = intel_fb->obj;
80824003 1659 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
016b9b61 1660 int cfb_pitch;
80824003
JB		 1661 int plane, i;
1662 u32 fbc_ctl, fbc_ctl2;
1663
016b9b61 1664 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
01f2c773
VS		 1665 if (fb->pitches[0] < cfb_pitch)
1666 cfb_pitch = fb->pitches[0];
80824003
JB		 1667
1668 /* FBC_CTL wants 64B units */
016b9b61
CW		 1669 cfb_pitch = (cfb_pitch / 64) - 1;
1670 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
80824003
JB		 1671
1672 /* Clear old tags */
1673 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1674 I915_WRITE(FBC_TAG + (i * 4), 0);
1675
1676 /* Set it up... */
de568510
CW		 1677 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1678 fbc_ctl2 |= plane;
80824003
JB		 1679 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1680 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1681
1682 /* enable it... */
1683 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
ee25df2b 1684 if (IS_I945GM(dev))
49677901 1685 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
016b9b61 1686 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
80824003 1687 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
016b9b61 1688 fbc_ctl |= obj->fence_reg;
80824003
JB		 1689 I915_WRITE(FBC_CONTROL, fbc_ctl);
1690
016b9b61
CW		 1691 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1692 cfb_pitch, crtc->y, intel_crtc->plane);
80824003
JB		 1693}
1694
ee5382ae 1695static bool i8xx_fbc_enabled(struct drm_device *dev)
80824003 1696{
80824003
JB		 1697 struct drm_i915_private *dev_priv = dev->dev_private;
1698
1699 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1700}
1701
74dff282
JB		 1702static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1703{
1704 struct drm_device *dev = crtc->dev;
1705 struct drm_i915_private *dev_priv = dev->dev_private;
1706 struct drm_framebuffer *fb = crtc->fb;
1707 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1708 struct drm_i915_gem_object *obj = intel_fb->obj;
74dff282 1709 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1710 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
74dff282
JB		 1711 unsigned long stall_watermark = 200;
1712 u32 dpfc_ctl;
1713
74dff282 1714 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
016b9b61 1715 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
de568510 1716 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
74dff282 1717
74dff282
JB		 1718 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1719 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1720 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1721 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1722
1723 /* enable it... */
1724 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1725
28c97730 1726 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
74dff282
JB		 1727}
1728
43a9539f 1729static void g4x_disable_fbc(struct drm_device *dev)
74dff282
JB		 1730{
1731 struct drm_i915_private *dev_priv = dev->dev_private;
1732 u32 dpfc_ctl;
1733
1734 /* Disable compression */
1735 dpfc_ctl = I915_READ(DPFC_CONTROL);
bed4a673
CW		 1736 if (dpfc_ctl & DPFC_CTL_EN) {
1737 dpfc_ctl &= ~DPFC_CTL_EN;
1738 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
74dff282 1739
bed4a673
CW		 1740 DRM_DEBUG_KMS("disabled FBC\n");
1741 }
74dff282
JB		 1742}
1743
ee5382ae 1744static bool g4x_fbc_enabled(struct drm_device *dev)
74dff282 1745{
74dff282
JB		 1746 struct drm_i915_private *dev_priv = dev->dev_private;
1747
1748 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1749}
1750
4efe0708
JB		 1751static void sandybridge_blit_fbc_update(struct drm_device *dev)
1752{
1753 struct drm_i915_private *dev_priv = dev->dev_private;
1754 u32 blt_ecoskpd;
1755
1756 /* Make sure blitter notifies FBC of writes */
fcca7926 1757 gen6_gt_force_wake_get(dev_priv);
4efe0708
JB		 1758 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1759 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1760 GEN6_BLITTER_LOCK_SHIFT;
1761 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1762 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1763 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1764 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1765 GEN6_BLITTER_LOCK_SHIFT);
1766 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1767 POSTING_READ(GEN6_BLITTER_ECOSKPD);
fcca7926 1768 gen6_gt_force_wake_put(dev_priv);
4efe0708
JB		 1769}
1770
b52eb4dc
ZY		 1771static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1772{
1773 struct drm_device *dev = crtc->dev;
1774 struct drm_i915_private *dev_priv = dev->dev_private;
1775 struct drm_framebuffer *fb = crtc->fb;
1776 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1777 struct drm_i915_gem_object *obj = intel_fb->obj;
b52eb4dc 1778 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1779 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
b52eb4dc
ZY		 1780 unsigned long stall_watermark = 200;
1781 u32 dpfc_ctl;
1782
bed4a673 1783 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
b52eb4dc
ZY		 1784 dpfc_ctl &= DPFC_RESERVED;
1785 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
9ce9d069
CW		 1786 /* Set persistent mode for front-buffer rendering, ala X. */
1787 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
016b9b61 1788 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
de568510 1789 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
b52eb4dc 1790
b52eb4dc
ZY		 1791 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1792 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1793 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1794 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
05394f39 1795 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
b52eb4dc 1796 /* enable it... */
bed4a673 1797 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
b52eb4dc 1798
9c04f015
YL		 1799 if (IS_GEN6(dev)) {
1800 I915_WRITE(SNB_DPFC_CTL_SA,
016b9b61 1801 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
9c04f015 1802 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
4efe0708 1803 sandybridge_blit_fbc_update(dev);
9c04f015
YL		 1804 }
1805
b52eb4dc
ZY		 1806 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1807}
1808
43a9539f 1809static void ironlake_disable_fbc(struct drm_device *dev)
b52eb4dc
ZY		 1810{
1811 struct drm_i915_private *dev_priv = dev->dev_private;
1812 u32 dpfc_ctl;
1813
1814 /* Disable compression */
1815 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
bed4a673
CW		 1816 if (dpfc_ctl & DPFC_CTL_EN) {
1817 dpfc_ctl &= ~DPFC_CTL_EN;
1818 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
b52eb4dc 1819
bed4a673
CW		 1820 DRM_DEBUG_KMS("disabled FBC\n");
1821 }
b52eb4dc
ZY		 1822}
1823
1824static bool ironlake_fbc_enabled(struct drm_device *dev)
1825{
1826 struct drm_i915_private *dev_priv = dev->dev_private;
1827
1828 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1829}
1830
ee5382ae
AJ		 1831bool intel_fbc_enabled(struct drm_device *dev)
1832{
1833 struct drm_i915_private *dev_priv = dev->dev_private;
1834
1835 if (!dev_priv->display.fbc_enabled)
1836 return false;
1837
1838 return dev_priv->display.fbc_enabled(dev);
1839}
1840
1630fe75
CW		 1841static void intel_fbc_work_fn(struct work_struct *__work)
1842{
1843 struct intel_fbc_work *work =
1844 container_of(to_delayed_work(__work),
1845 struct intel_fbc_work, work);
1846 struct drm_device *dev = work->crtc->dev;
1847 struct drm_i915_private *dev_priv = dev->dev_private;
1848
1849 mutex_lock(&dev->struct_mutex);
1850 if (work == dev_priv->fbc_work) {
1851 /* Double check that we haven't switched fb without cancelling
1852 * the prior work.
1853 */
016b9b61 1854 if (work->crtc->fb == work->fb) {
1630fe75
CW		 1855 dev_priv->display.enable_fbc(work->crtc,
1856 work->interval);
1857
016b9b61
CW		 1858 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1859 dev_priv->cfb_fb = work->crtc->fb->base.id;
1860 dev_priv->cfb_y = work->crtc->y;
1861 }
1862
1630fe75
CW		 1863 dev_priv->fbc_work = NULL;
1864 }
1865 mutex_unlock(&dev->struct_mutex);
1866
1867 kfree(work);
1868}
1869
1870static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1871{
1872 if (dev_priv->fbc_work == NULL)
1873 return;
1874
1875 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1876
1877 /* Synchronisation is provided by struct_mutex and checking of
1878 * dev_priv->fbc_work, so we can perform the cancellation
1879 * entirely asynchronously.
1880 */
1881 if (cancel_delayed_work(&dev_priv->fbc_work->work))
1882 /* tasklet was killed before being run, clean up */
1883 kfree(dev_priv->fbc_work);
1884
1885 /* Mark the work as no longer wanted so that if it does
1886 * wake-up (because the work was already running and waiting
1887 * for our mutex), it will discover that is no longer
1888 * necessary to run.
1889 */
1890 dev_priv->fbc_work = NULL;
1891}
1892
43a9539f 1893static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
ee5382ae 1894{
1630fe75
CW		 1895 struct intel_fbc_work *work;
1896 struct drm_device *dev = crtc->dev;
1897 struct drm_i915_private *dev_priv = dev->dev_private;
ee5382ae
AJ		 1898
1899 if (!dev_priv->display.enable_fbc)
1900 return;
1901
1630fe75
CW		 1902 intel_cancel_fbc_work(dev_priv);
1903
1904 work = kzalloc(sizeof *work, GFP_KERNEL);
1905 if (work == NULL) {
1906 dev_priv->display.enable_fbc(crtc, interval);
1907 return;
1908 }
1909
1910 work->crtc = crtc;
1911 work->fb = crtc->fb;
1912 work->interval = interval;
1913 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1914
1915 dev_priv->fbc_work = work;
1916
1917 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1918
1919 /* Delay the actual enabling to let pageflipping cease and the
016b9b61
CW		 1920 * display to settle before starting the compression. Note that
1921 * this delay also serves a second purpose: it allows for a
1922 * vblank to pass after disabling the FBC before we attempt
1923 * to modify the control registers.
1630fe75
CW		 1924 *
1925 * A more complicated solution would involve tracking vblanks
1926 * following the termination of the page-flipping sequence
1927 * and indeed performing the enable as a co-routine and not
1928 * waiting synchronously upon the vblank.
1929 */
1930 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
ee5382ae
AJ		 1931}
1932
1933void intel_disable_fbc(struct drm_device *dev)
1934{
1935 struct drm_i915_private *dev_priv = dev->dev_private;
1936
1630fe75
CW		 1937 intel_cancel_fbc_work(dev_priv);
1938
ee5382ae
AJ		 1939 if (!dev_priv->display.disable_fbc)
1940 return;
1941
1942 dev_priv->display.disable_fbc(dev);
016b9b61 1943 dev_priv->cfb_plane = -1;
ee5382ae
AJ		 1944}
1945
80824003
JB		 1946/**
1947 * intel_update_fbc - enable/disable FBC as needed
bed4a673 1948 * @dev: the drm_device
80824003
JB		 1949 *
1950 * Set up the framebuffer compression hardware at mode set time. We
1951 * enable it if possible:
1952 * - plane A only (on pre-965)
1953 * - no pixel mulitply/line duplication
1954 * - no alpha buffer discard
1955 * - no dual wide
1956 * - framebuffer <= 2048 in width, 1536 in height
1957 *
1958 * We can't assume that any compression will take place (worst case),
1959 * so the compressed buffer has to be the same size as the uncompressed
1960 * one. It also must reside (along with the line length buffer) in
1961 * stolen memory.
1962 *
1963 * We need to enable/disable FBC on a global basis.
1964 */
bed4a673 1965static void intel_update_fbc(struct drm_device *dev)
80824003 1966{
80824003 1967 struct drm_i915_private *dev_priv = dev->dev_private;
bed4a673
CW		 1968 struct drm_crtc *crtc = NULL, *tmp_crtc;
1969 struct intel_crtc *intel_crtc;
1970 struct drm_framebuffer *fb;
80824003 1971 struct intel_framebuffer *intel_fb;
05394f39 1972 struct drm_i915_gem_object *obj;
cd0de039 1973 int enable_fbc;
9c928d16
JB		 1974
1975 DRM_DEBUG_KMS("\n");
80824003
JB		 1976
1977 if (!i915_powersave)
1978 return;
1979
ee5382ae 1980 if (!I915_HAS_FBC(dev))
e70236a8
JB		 1981 return;
1982
80824003
JB		 1983 /*
1984 * If FBC is already on, we just have to verify that we can
1985 * keep it that way...
1986 * Need to disable if:
9c928d16 1987 * - more than one pipe is active
80824003
JB		 1988 * - changing FBC params (stride, fence, mode)
1989 * - new fb is too large to fit in compressed buffer
1990 * - going to an unsupported config (interlace, pixel multiply, etc.)
1991 */
9c928d16 1992 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
d210246a 1993 if (tmp_crtc->enabled && tmp_crtc->fb) {
bed4a673
CW		 1994 if (crtc) {
1995 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1996 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1997 goto out_disable;
1998 }
1999 crtc = tmp_crtc;
2000 }
9c928d16 2001 }
bed4a673
CW		 2002
2003 if (!crtc || crtc->fb == NULL) {
2004 DRM_DEBUG_KMS("no output, disabling\n");
2005 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
9c928d16
JB		 2006 goto out_disable;
2007 }
bed4a673
CW		 2008
2009 intel_crtc = to_intel_crtc(crtc);
2010 fb = crtc->fb;
2011 intel_fb = to_intel_framebuffer(fb);
05394f39 2012 obj = intel_fb->obj;
bed4a673 2013
cd0de039
KP		 2014 enable_fbc = i915_enable_fbc;
2015 if (enable_fbc < 0) {
2016 DRM_DEBUG_KMS("fbc set to per-chip default\n");
2017 enable_fbc = 1;
d56d8b28 2018 if (INTEL_INFO(dev)->gen <= 6)
cd0de039
KP		 2019 enable_fbc = 0;
2020 }
2021 if (!enable_fbc) {
2022 DRM_DEBUG_KMS("fbc disabled per module param\n");
c1a9f047
JB		 2023 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
2024 goto out_disable;
2025 }
05394f39 2026 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
28c97730 2027 DRM_DEBUG_KMS("framebuffer too large, disabling "
5eddb70b 2028 "compression\n");
b5e50c3f 2029 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
80824003
JB		 2030 goto out_disable;
2031 }
bed4a673
CW		 2032 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
2033 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
28c97730 2034 DRM_DEBUG_KMS("mode incompatible with compression, "
5eddb70b 2035 "disabling\n");
b5e50c3f 2036 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
80824003
JB		 2037 goto out_disable;
2038 }
bed4a673
CW		 2039 if ((crtc->mode.hdisplay > 2048) ||
2040 (crtc->mode.vdisplay > 1536)) {
28c97730 2041 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
b5e50c3f 2042 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
80824003
JB		 2043 goto out_disable;
2044 }
bed4a673 2045 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
28c97730 2046 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
b5e50c3f 2047 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
80824003
JB		 2048 goto out_disable;
2049 }
de568510
CW		 2050
2051 /* The use of a CPU fence is mandatory in order to detect writes
2052 * by the CPU to the scanout and trigger updates to the FBC.
2053 */
2054 if (obj->tiling_mode != I915_TILING_X ||
2055 obj->fence_reg == I915_FENCE_REG_NONE) {
2056 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
b5e50c3f 2057 dev_priv->no_fbc_reason = FBC_NOT_TILED;
80824003
JB		 2058 goto out_disable;
2059 }
2060
c924b934
JW		 2061 /* If the kernel debugger is active, always disable compression */
2062 if (in_dbg_master())
2063 goto out_disable;
2064
016b9b61
CW		 2065 /* If the scanout has not changed, don't modify the FBC settings.
2066 * Note that we make the fundamental assumption that the fb->obj
2067 * cannot be unpinned (and have its GTT offset and fence revoked)
2068 * without first being decoupled from the scanout and FBC disabled.
2069 */
2070 if (dev_priv->cfb_plane == intel_crtc->plane &&
2071 dev_priv->cfb_fb == fb->base.id &&
2072 dev_priv->cfb_y == crtc->y)
2073 return;
2074
2075 if (intel_fbc_enabled(dev)) {
2076 /* We update FBC along two paths, after changing fb/crtc
2077 * configuration (modeswitching) and after page-flipping
2078 * finishes. For the latter, we know that not only did
2079 * we disable the FBC at the start of the page-flip
2080 * sequence, but also more than one vblank has passed.
2081 *
2082 * For the former case of modeswitching, it is possible
2083 * to switch between two FBC valid configurations
2084 * instantaneously so we do need to disable the FBC
2085 * before we can modify its control registers. We also
2086 * have to wait for the next vblank for that to take
2087 * effect. However, since we delay enabling FBC we can
2088 * assume that a vblank has passed since disabling and
2089 * that we can safely alter the registers in the deferred
2090 * callback.
2091 *
2092 * In the scenario that we go from a valid to invalid
2093 * and then back to valid FBC configuration we have
2094 * no strict enforcement that a vblank occurred since
2095 * disabling the FBC. However, along all current pipe
2096 * disabling paths we do need to wait for a vblank at
2097 * some point. And we wait before enabling FBC anyway.
2098 */
2099 DRM_DEBUG_KMS("disabling active FBC for update\n");
2100 intel_disable_fbc(dev);
2101 }
2102
bed4a673 2103 intel_enable_fbc(crtc, 500);
80824003
JB		 2104 return;
2105
2106out_disable:
80824003 2107 /* Multiple disables should be harmless */
a939406f
CW		 2108 if (intel_fbc_enabled(dev)) {
2109 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
ee5382ae 2110 intel_disable_fbc(dev);
a939406f 2111 }
80824003
JB		 2112}
2113
127bd2ac 2114int
48b956c5 2115intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 2116 struct drm_i915_gem_object *obj,
919926ae 2117 struct intel_ring_buffer *pipelined)
6b95a207 2118{
ce453d81 2119 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 2120 u32 alignment;
2121 int ret;
2122
05394f39 2123 switch (obj->tiling_mode) {
6b95a207 2124 case I915_TILING_NONE:
534843da
CW		 2125 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2126 alignment = 128 * 1024;
a6c45cf0 2127 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 2128 alignment = 4 * 1024;
2129 else
2130 alignment = 64 * 1024;
6b95a207
KH		 2131 break;
2132 case I915_TILING_X:
2133 /* pin() will align the object as required by fence */
2134 alignment = 0;
2135 break;
2136 case I915_TILING_Y:
2137 /* FIXME: Is this true? */
2138 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2139 return -EINVAL;
2140 default:
2141 BUG();
2142 }
2143
ce453d81 2144 dev_priv->mm.interruptible = false;
2da3b9b9 2145 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 2146 if (ret)
ce453d81 2147 goto err_interruptible;
6b95a207
KH		 2148
2149 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2150 * fence, whereas 965+ only requires a fence if using
2151 * framebuffer compression. For simplicity, we always install
2152 * a fence as the cost is not that onerous.
2153 */
9a5a53b3
CW		 2154 ret = i915_gem_object_get_fence(obj, pipelined);
2155 if (ret)
2156 goto err_unpin;
1690e1eb 2157
9a5a53b3 2158 i915_gem_object_pin_fence(obj);
6b95a207 2159
ce453d81 2160 dev_priv->mm.interruptible = true;
6b95a207 2161 return 0;
48b956c5
CW		 2162
2163err_unpin:
2164 i915_gem_object_unpin(obj);
ce453d81
CW		 2165err_interruptible:
2166 dev_priv->mm.interruptible = true;
48b956c5 2167 return ret;
6b95a207
KH		 2168}
2169
1690e1eb
CW		 2170void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2171{
2172 i915_gem_object_unpin_fence(obj);
2173 i915_gem_object_unpin(obj);
2174}
2175
17638cd6
JB		 2176static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2177 int x, int y)
81255565
JB		 2178{
2179 struct drm_device *dev = crtc->dev;
2180 struct drm_i915_private *dev_priv = dev->dev_private;
2181 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2182 struct intel_framebuffer *intel_fb;
05394f39 2183 struct drm_i915_gem_object *obj;
81255565
JB		 2184 int plane = intel_crtc->plane;
2185 unsigned long Start, Offset;
81255565 2186 u32 dspcntr;
5eddb70b 2187 u32 reg;
81255565
JB		 2188
2189 switch (plane) {
2190 case 0:
2191 case 1:
2192 break;
2193 default:
2194 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2195 return -EINVAL;
2196 }
2197
2198 intel_fb = to_intel_framebuffer(fb);
2199 obj = intel_fb->obj;
81255565 2200
5eddb70b
CW		 2201 reg = DSPCNTR(plane);
2202 dspcntr = I915_READ(reg);
81255565
JB		 2203 /* Mask out pixel format bits in case we change it */
2204 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2205 switch (fb->bits_per_pixel) {
2206 case 8:
2207 dspcntr |= DISPPLANE_8BPP;
2208 break;
2209 case 16:
2210 if (fb->depth == 15)
2211 dspcntr |= DISPPLANE_15_16BPP;
2212 else
2213 dspcntr |= DISPPLANE_16BPP;
2214 break;
2215 case 24:
2216 case 32:
2217 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2218 break;
2219 default:
17638cd6 2220 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
81255565
JB		 2221 return -EINVAL;
2222 }
a6c45cf0 2223 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2224 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2225 dspcntr |= DISPPLANE_TILED;
2226 else
2227 dspcntr &= ~DISPPLANE_TILED;
2228 }
2229
5eddb70b 2230 I915_WRITE(reg, dspcntr);
81255565 2231
05394f39 2232 Start = obj->gtt_offset;
01f2c773 2233 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2234
4e6cfefc 2235 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
01f2c773
VS		 2236 Start, Offset, x, y, fb->pitches[0]);
2237 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2238 if (INTEL_INFO(dev)->gen >= 4) {
446f2545 2239 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
5eddb70b
CW		 2240 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2241 I915_WRITE(DSPADDR(plane), Offset);
2242 } else
2243 I915_WRITE(DSPADDR(plane), Start + Offset);
2244 POSTING_READ(reg);
81255565 2245
17638cd6
JB		 2246 return 0;
2247}
2248
2249static int ironlake_update_plane(struct drm_crtc *crtc,
2250 struct drm_framebuffer *fb, int x, int y)
2251{
2252 struct drm_device *dev = crtc->dev;
2253 struct drm_i915_private *dev_priv = dev->dev_private;
2254 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2255 struct intel_framebuffer *intel_fb;
2256 struct drm_i915_gem_object *obj;
2257 int plane = intel_crtc->plane;
2258 unsigned long Start, Offset;
2259 u32 dspcntr;
2260 u32 reg;
2261
2262 switch (plane) {
2263 case 0:
2264 case 1:
27f8227b 2265 case 2:
17638cd6
JB		 2266 break;
2267 default:
2268 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2269 return -EINVAL;
2270 }
2271
2272 intel_fb = to_intel_framebuffer(fb);
2273 obj = intel_fb->obj;
2274
2275 reg = DSPCNTR(plane);
2276 dspcntr = I915_READ(reg);
2277 /* Mask out pixel format bits in case we change it */
2278 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2279 switch (fb->bits_per_pixel) {
2280 case 8:
2281 dspcntr |= DISPPLANE_8BPP;
2282 break;
2283 case 16:
2284 if (fb->depth != 16)
2285 return -EINVAL;
2286
2287 dspcntr |= DISPPLANE_16BPP;
2288 break;
2289 case 24:
2290 case 32:
2291 if (fb->depth == 24)
2292 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2293 else if (fb->depth == 30)
2294 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2295 else
2296 return -EINVAL;
2297 break;
2298 default:
2299 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2300 return -EINVAL;
2301 }
2302
2303 if (obj->tiling_mode != I915_TILING_NONE)
2304 dspcntr |= DISPPLANE_TILED;
2305 else
2306 dspcntr &= ~DISPPLANE_TILED;
2307
2308 /* must disable */
2309 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2310
2311 I915_WRITE(reg, dspcntr);
2312
2313 Start = obj->gtt_offset;
01f2c773 2314 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
17638cd6
JB		 2315
2316 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
01f2c773
VS		 2317 Start, Offset, x, y, fb->pitches[0]);
2318 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
446f2545 2319 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
17638cd6
JB		 2320 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2321 I915_WRITE(DSPADDR(plane), Offset);
2322 POSTING_READ(reg);
2323
2324 return 0;
2325}
2326
2327/* Assume fb object is pinned & idle & fenced and just update base pointers */
2328static int
2329intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2330 int x, int y, enum mode_set_atomic state)
2331{
2332 struct drm_device *dev = crtc->dev;
2333 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2334
6b8e6ed0
CW		 2335 if (dev_priv->display.disable_fbc)
2336 dev_priv->display.disable_fbc(dev);
3dec0095 2337 intel_increase_pllclock(crtc);
81255565 2338
6b8e6ed0 2339 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2340}
2341
14667a4b
CW		 2342static int
2343intel_finish_fb(struct drm_framebuffer *old_fb)
2344{
2345 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2346 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2347 bool was_interruptible = dev_priv->mm.interruptible;
2348 int ret;
2349
2350 wait_event(dev_priv->pending_flip_queue,
2351 atomic_read(&dev_priv->mm.wedged) ||
2352 atomic_read(&obj->pending_flip) == 0);
2353
2354 /* Big Hammer, we also need to ensure that any pending
2355 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2356 * current scanout is retired before unpinning the old
2357 * framebuffer.
2358 *
2359 * This should only fail upon a hung GPU, in which case we
2360 * can safely continue.
2361 */
2362 dev_priv->mm.interruptible = false;
2363 ret = i915_gem_object_finish_gpu(obj);
2364 dev_priv->mm.interruptible = was_interruptible;
2365
2366 return ret;
2367}
2368
5c3b82e2 2369static int
3c4fdcfb
KH		 2370intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2371 struct drm_framebuffer *old_fb)
79e53945
JB		 2372{
2373 struct drm_device *dev = crtc->dev;
6b8e6ed0 2374 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 2375 struct drm_i915_master_private *master_priv;
2376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5c3b82e2 2377 int ret;
79e53945
JB		 2378
2379 /* no fb bound */
2380 if (!crtc->fb) {
a5071c2f 2381 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2382 return 0;
2383 }
2384
265db958 2385 switch (intel_crtc->plane) {
5c3b82e2
CW		 2386 case 0:
2387 case 1:
2388 break;
27f8227b
JB		 2389 case 2:
2390 if (IS_IVYBRIDGE(dev))
2391 break;
2392 /* fall through otherwise */
5c3b82e2 2393 default:
a5071c2f 2394 DRM_ERROR("no plane for crtc\n");
5c3b82e2 2395 return -EINVAL;
79e53945
JB		 2396 }
2397
5c3b82e2 2398 mutex_lock(&dev->struct_mutex);
265db958
CW		 2399 ret = intel_pin_and_fence_fb_obj(dev,
2400 to_intel_framebuffer(crtc->fb)->obj,
919926ae 2401 NULL);
5c3b82e2
CW		 2402 if (ret != 0) {
2403 mutex_unlock(&dev->struct_mutex);
a5071c2f 2404 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2405 return ret;
2406 }
79e53945 2407
14667a4b
CW		 2408 if (old_fb)
2409 intel_finish_fb(old_fb);
265db958 2410
6b8e6ed0 2411 ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y);
4e6cfefc 2412 if (ret) {
1690e1eb 2413 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
5c3b82e2 2414 mutex_unlock(&dev->struct_mutex);
a5071c2f 2415 DRM_ERROR("failed to update base address\n");
4e6cfefc 2416 return ret;
79e53945 2417 }
3c4fdcfb 2418
b7f1de28
CW		 2419 if (old_fb) {
2420 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2421 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2422 }
652c393a 2423
6b8e6ed0 2424 intel_update_fbc(dev);
5c3b82e2 2425 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 2426
2427 if (!dev->primary->master)
5c3b82e2 2428 return 0;
79e53945
JB		 2429
2430 master_priv = dev->primary->master->driver_priv;
2431 if (!master_priv->sarea_priv)
5c3b82e2 2432 return 0;
79e53945 2433
265db958 2434 if (intel_crtc->pipe) {
79e53945
JB		 2435 master_priv->sarea_priv->pipeB_x = x;
2436 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2437 } else {
2438 master_priv->sarea_priv->pipeA_x = x;
2439 master_priv->sarea_priv->pipeA_y = y;
79e53945 2440 }
5c3b82e2
CW		 2441
2442 return 0;
79e53945
JB		 2443}
2444
5eddb70b 2445static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2446{
2447 struct drm_device *dev = crtc->dev;
2448 struct drm_i915_private *dev_priv = dev->dev_private;
2449 u32 dpa_ctl;
2450
28c97730 2451 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2452 dpa_ctl = I915_READ(DP_A);
2453 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2454
2455 if (clock < 200000) {
2456 u32 temp;
2457 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2458 /* workaround for 160Mhz:
2459 1) program 0x4600c bits 15:0 = 0x8124
2460 2) program 0x46010 bit 0 = 1
2461 3) program 0x46034 bit 24 = 1
2462 4) program 0x64000 bit 14 = 1
2463 */
2464 temp = I915_READ(0x4600c);
2465 temp &= 0xffff0000;
2466 I915_WRITE(0x4600c, temp | 0x8124);
2467
2468 temp = I915_READ(0x46010);
2469 I915_WRITE(0x46010, temp | 1);
2470
2471 temp = I915_READ(0x46034);
2472 I915_WRITE(0x46034, temp | (1 << 24));
2473 } else {
2474 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2475 }
2476 I915_WRITE(DP_A, dpa_ctl);
2477
5eddb70b 2478 POSTING_READ(DP_A);
32f9d658
ZW		 2479 udelay(500);
2480}
2481
5e84e1a4
ZW		 2482static void intel_fdi_normal_train(struct drm_crtc *crtc)
2483{
2484 struct drm_device *dev = crtc->dev;
2485 struct drm_i915_private *dev_priv = dev->dev_private;
2486 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2487 int pipe = intel_crtc->pipe;
2488 u32 reg, temp;
2489
2490 /* enable normal train */
2491 reg = FDI_TX_CTL(pipe);
2492 temp = I915_READ(reg);
61e499bf 2493 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2494 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2495 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2496 } else {
2497 temp &= ~FDI_LINK_TRAIN_NONE;
2498 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2499 }
5e84e1a4
ZW		 2500 I915_WRITE(reg, temp);
2501
2502 reg = FDI_RX_CTL(pipe);
2503 temp = I915_READ(reg);
2504 if (HAS_PCH_CPT(dev)) {
2505 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2506 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2507 } else {
2508 temp &= ~FDI_LINK_TRAIN_NONE;
2509 temp |= FDI_LINK_TRAIN_NONE;
2510 }
2511 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2512
2513 /* wait one idle pattern time */
2514 POSTING_READ(reg);
2515 udelay(1000);
357555c0
JB		 2516
2517 /* IVB wants error correction enabled */
2518 if (IS_IVYBRIDGE(dev))
2519 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2520 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2521}
2522
291427f5
JB		 2523static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2524{
2525 struct drm_i915_private *dev_priv = dev->dev_private;
2526 u32 flags = I915_READ(SOUTH_CHICKEN1);
2527
2528 flags |= FDI_PHASE_SYNC_OVR(pipe);
2529 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2530 flags |= FDI_PHASE_SYNC_EN(pipe);
2531 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2532 POSTING_READ(SOUTH_CHICKEN1);
2533}
2534
8db9d77b
ZW		 2535/* The FDI link training functions for ILK/Ibexpeak. */
2536static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2537{
2538 struct drm_device *dev = crtc->dev;
2539 struct drm_i915_private *dev_priv = dev->dev_private;
2540 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2541 int pipe = intel_crtc->pipe;
0fc932b8 2542 int plane = intel_crtc->plane;
5eddb70b 2543 u32 reg, temp, tries;
8db9d77b 2544
0fc932b8
JB		 2545 /* FDI needs bits from pipe & plane first */
2546 assert_pipe_enabled(dev_priv, pipe);
2547 assert_plane_enabled(dev_priv, plane);
2548
e1a44743
AJ		 2549 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2550 for train result */
5eddb70b
CW		 2551 reg = FDI_RX_IMR(pipe);
2552 temp = I915_READ(reg);
e1a44743
AJ		 2553 temp &= ~FDI_RX_SYMBOL_LOCK;
2554 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2555 I915_WRITE(reg, temp);
2556 I915_READ(reg);
e1a44743
AJ		 2557 udelay(150);
2558
8db9d77b 2559 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2560 reg = FDI_TX_CTL(pipe);
2561 temp = I915_READ(reg);
77ffb597
AJ		 2562 temp &= ~(7 << 19);
2563 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2564 temp &= ~FDI_LINK_TRAIN_NONE;
2565 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2566 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2567
5eddb70b
CW		 2568 reg = FDI_RX_CTL(pipe);
2569 temp = I915_READ(reg);
8db9d77b
ZW		 2570 temp &= ~FDI_LINK_TRAIN_NONE;
2571 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2572 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2573
2574 POSTING_READ(reg);
8db9d77b
ZW		 2575 udelay(150);
2576
5b2adf89 2577 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2578 if (HAS_PCH_IBX(dev)) {
2579 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2580 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2581 FDI_RX_PHASE_SYNC_POINTER_EN);
2582 }
5b2adf89 2583
5eddb70b 2584 reg = FDI_RX_IIR(pipe);
e1a44743 2585 for (tries = 0; tries < 5; tries++) {
5eddb70b 2586 temp = I915_READ(reg);
8db9d77b
ZW		 2587 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2588
2589 if ((temp & FDI_RX_BIT_LOCK)) {
2590 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2591 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2592 break;
2593 }
8db9d77b 2594 }
e1a44743 2595 if (tries == 5)
5eddb70b 2596 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2597
2598 /* Train 2 */
5eddb70b
CW		 2599 reg = FDI_TX_CTL(pipe);
2600 temp = I915_READ(reg);
8db9d77b
ZW		 2601 temp &= ~FDI_LINK_TRAIN_NONE;
2602 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2603 I915_WRITE(reg, temp);
8db9d77b 2604
5eddb70b
CW		 2605 reg = FDI_RX_CTL(pipe);
2606 temp = I915_READ(reg);
8db9d77b
ZW		 2607 temp &= ~FDI_LINK_TRAIN_NONE;
2608 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2609 I915_WRITE(reg, temp);
8db9d77b 2610
5eddb70b
CW		 2611 POSTING_READ(reg);
2612 udelay(150);
8db9d77b 2613
5eddb70b 2614 reg = FDI_RX_IIR(pipe);
e1a44743 2615 for (tries = 0; tries < 5; tries++) {
5eddb70b 2616 temp = I915_READ(reg);
8db9d77b
ZW		 2617 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2618
2619 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2620 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2621 DRM_DEBUG_KMS("FDI train 2 done.\n");
2622 break;
2623 }
8db9d77b 2624 }
e1a44743 2625 if (tries == 5)
5eddb70b 2626 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2627
2628 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2629
8db9d77b
ZW		 2630}
2631
0206e353 2632static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2633 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2634 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2635 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2636 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2637};
2638
2639/* The FDI link training functions for SNB/Cougarpoint. */
2640static void gen6_fdi_link_train(struct drm_crtc *crtc)
2641{
2642 struct drm_device *dev = crtc->dev;
2643 struct drm_i915_private *dev_priv = dev->dev_private;
2644 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2645 int pipe = intel_crtc->pipe;
fa37d39e 2646 u32 reg, temp, i, retry;
8db9d77b 2647
e1a44743
AJ		 2648 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2649 for train result */
5eddb70b
CW		 2650 reg = FDI_RX_IMR(pipe);
2651 temp = I915_READ(reg);
e1a44743
AJ		 2652 temp &= ~FDI_RX_SYMBOL_LOCK;
2653 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2654 I915_WRITE(reg, temp);
2655
2656 POSTING_READ(reg);
e1a44743
AJ		 2657 udelay(150);
2658
8db9d77b 2659 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2660 reg = FDI_TX_CTL(pipe);
2661 temp = I915_READ(reg);
77ffb597
AJ		 2662 temp &= ~(7 << 19);
2663 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2664 temp &= ~FDI_LINK_TRAIN_NONE;
2665 temp |= FDI_LINK_TRAIN_PATTERN_1;
2666 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2667 /* SNB-B */
2668 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2669 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2670
5eddb70b
CW		 2671 reg = FDI_RX_CTL(pipe);
2672 temp = I915_READ(reg);
8db9d77b
ZW		 2673 if (HAS_PCH_CPT(dev)) {
2674 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2675 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2676 } else {
2677 temp &= ~FDI_LINK_TRAIN_NONE;
2678 temp |= FDI_LINK_TRAIN_PATTERN_1;
2679 }
5eddb70b
CW		 2680 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2681
2682 POSTING_READ(reg);
8db9d77b
ZW		 2683 udelay(150);
2684
291427f5
JB		 2685 if (HAS_PCH_CPT(dev))
2686 cpt_phase_pointer_enable(dev, pipe);
2687
0206e353 2688 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2689 reg = FDI_TX_CTL(pipe);
2690 temp = I915_READ(reg);
8db9d77b
ZW		 2691 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2692 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2693 I915_WRITE(reg, temp);
2694
2695 POSTING_READ(reg);
8db9d77b
ZW		 2696 udelay(500);
2697
fa37d39e
SP		 2698 for (retry = 0; retry < 5; retry++) {
2699 reg = FDI_RX_IIR(pipe);
2700 temp = I915_READ(reg);
2701 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2702 if (temp & FDI_RX_BIT_LOCK) {
2703 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2704 DRM_DEBUG_KMS("FDI train 1 done.\n");
2705 break;
2706 }
2707 udelay(50);
8db9d77b 2708 }
fa37d39e
SP		 2709 if (retry < 5)
2710 break;
8db9d77b
ZW		 2711 }
2712 if (i == 4)
5eddb70b 2713 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2714
2715 /* Train 2 */
5eddb70b
CW		 2716 reg = FDI_TX_CTL(pipe);
2717 temp = I915_READ(reg);
8db9d77b
ZW		 2718 temp &= ~FDI_LINK_TRAIN_NONE;
2719 temp |= FDI_LINK_TRAIN_PATTERN_2;
2720 if (IS_GEN6(dev)) {
2721 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2722 /* SNB-B */
2723 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2724 }
5eddb70b 2725 I915_WRITE(reg, temp);
8db9d77b 2726
5eddb70b
CW		 2727 reg = FDI_RX_CTL(pipe);
2728 temp = I915_READ(reg);
8db9d77b
ZW		 2729 if (HAS_PCH_CPT(dev)) {
2730 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2731 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2732 } else {
2733 temp &= ~FDI_LINK_TRAIN_NONE;
2734 temp |= FDI_LINK_TRAIN_PATTERN_2;
2735 }
5eddb70b
CW		 2736 I915_WRITE(reg, temp);
2737
2738 POSTING_READ(reg);
8db9d77b
ZW		 2739 udelay(150);
2740
0206e353 2741 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2742 reg = FDI_TX_CTL(pipe);
2743 temp = I915_READ(reg);
8db9d77b
ZW		 2744 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2745 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2746 I915_WRITE(reg, temp);
2747
2748 POSTING_READ(reg);
8db9d77b
ZW		 2749 udelay(500);
2750
fa37d39e
SP		 2751 for (retry = 0; retry < 5; retry++) {
2752 reg = FDI_RX_IIR(pipe);
2753 temp = I915_READ(reg);
2754 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2755 if (temp & FDI_RX_SYMBOL_LOCK) {
2756 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2757 DRM_DEBUG_KMS("FDI train 2 done.\n");
2758 break;
2759 }
2760 udelay(50);
8db9d77b 2761 }
fa37d39e
SP		 2762 if (retry < 5)
2763 break;
8db9d77b
ZW		 2764 }
2765 if (i == 4)
5eddb70b 2766 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2767
2768 DRM_DEBUG_KMS("FDI train done.\n");
2769}
2770
357555c0
JB		 2771/* Manual link training for Ivy Bridge A0 parts */
2772static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2773{
2774 struct drm_device *dev = crtc->dev;
2775 struct drm_i915_private *dev_priv = dev->dev_private;
2776 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2777 int pipe = intel_crtc->pipe;
2778 u32 reg, temp, i;
2779
2780 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2781 for train result */
2782 reg = FDI_RX_IMR(pipe);
2783 temp = I915_READ(reg);
2784 temp &= ~FDI_RX_SYMBOL_LOCK;
2785 temp &= ~FDI_RX_BIT_LOCK;
2786 I915_WRITE(reg, temp);
2787
2788 POSTING_READ(reg);
2789 udelay(150);
2790
2791 /* enable CPU FDI TX and PCH FDI RX */
2792 reg = FDI_TX_CTL(pipe);
2793 temp = I915_READ(reg);
2794 temp &= ~(7 << 19);
2795 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2796 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2797 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2798 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2799 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2800 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2801 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2802
2803 reg = FDI_RX_CTL(pipe);
2804 temp = I915_READ(reg);
2805 temp &= ~FDI_LINK_TRAIN_AUTO;
2806 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2807 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2808 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2809 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2810
2811 POSTING_READ(reg);
2812 udelay(150);
2813
291427f5
JB		 2814 if (HAS_PCH_CPT(dev))
2815 cpt_phase_pointer_enable(dev, pipe);
2816
0206e353 2817 for (i = 0; i < 4; i++) {
357555c0
JB		 2818 reg = FDI_TX_CTL(pipe);
2819 temp = I915_READ(reg);
2820 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2821 temp |= snb_b_fdi_train_param[i];
2822 I915_WRITE(reg, temp);
2823
2824 POSTING_READ(reg);
2825 udelay(500);
2826
2827 reg = FDI_RX_IIR(pipe);
2828 temp = I915_READ(reg);
2829 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2830
2831 if (temp & FDI_RX_BIT_LOCK ||
2832 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2833 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2834 DRM_DEBUG_KMS("FDI train 1 done.\n");
2835 break;
2836 }
2837 }
2838 if (i == 4)
2839 DRM_ERROR("FDI train 1 fail!\n");
2840
2841 /* Train 2 */
2842 reg = FDI_TX_CTL(pipe);
2843 temp = I915_READ(reg);
2844 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2845 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2846 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2847 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2848 I915_WRITE(reg, temp);
2849
2850 reg = FDI_RX_CTL(pipe);
2851 temp = I915_READ(reg);
2852 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2853 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2854 I915_WRITE(reg, temp);
2855
2856 POSTING_READ(reg);
2857 udelay(150);
2858
0206e353 2859 for (i = 0; i < 4; i++) {
357555c0
JB		 2860 reg = FDI_TX_CTL(pipe);
2861 temp = I915_READ(reg);
2862 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2863 temp |= snb_b_fdi_train_param[i];
2864 I915_WRITE(reg, temp);
2865
2866 POSTING_READ(reg);
2867 udelay(500);
2868
2869 reg = FDI_RX_IIR(pipe);
2870 temp = I915_READ(reg);
2871 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2872
2873 if (temp & FDI_RX_SYMBOL_LOCK) {
2874 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2875 DRM_DEBUG_KMS("FDI train 2 done.\n");
2876 break;
2877 }
2878 }
2879 if (i == 4)
2880 DRM_ERROR("FDI train 2 fail!\n");
2881
2882 DRM_DEBUG_KMS("FDI train done.\n");
2883}
2884
2885static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2c07245f
ZW		 2886{
2887 struct drm_device *dev = crtc->dev;
2888 struct drm_i915_private *dev_priv = dev->dev_private;
2889 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2890 int pipe = intel_crtc->pipe;
5eddb70b 2891 u32 reg, temp;
79e53945 2892
c64e311e 2893 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2894 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2895 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2896
c98e9dcf 2897 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2898 reg = FDI_RX_CTL(pipe);
2899 temp = I915_READ(reg);
2900 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2901 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2902 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2903 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2904
2905 POSTING_READ(reg);
c98e9dcf
JB		 2906 udelay(200);
2907
2908 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2909 temp = I915_READ(reg);
2910 I915_WRITE(reg, temp | FDI_PCDCLK);
2911
2912 POSTING_READ(reg);
c98e9dcf
JB		 2913 udelay(200);
2914
2915 /* Enable CPU FDI TX PLL, always on for Ironlake */
5eddb70b
CW		 2916 reg = FDI_TX_CTL(pipe);
2917 temp = I915_READ(reg);
c98e9dcf 2918 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5eddb70b
CW		 2919 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2920
2921 POSTING_READ(reg);
c98e9dcf 2922 udelay(100);
6be4a607 2923 }
0e23b99d
JB		 2924}
2925
291427f5
JB		 2926static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2927{
2928 struct drm_i915_private *dev_priv = dev->dev_private;
2929 u32 flags = I915_READ(SOUTH_CHICKEN1);
2930
2931 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2932 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2933 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2934 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2935 POSTING_READ(SOUTH_CHICKEN1);
2936}
0fc932b8
JB		 2937static void ironlake_fdi_disable(struct drm_crtc *crtc)
2938{
2939 struct drm_device *dev = crtc->dev;
2940 struct drm_i915_private *dev_priv = dev->dev_private;
2941 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2942 int pipe = intel_crtc->pipe;
2943 u32 reg, temp;
2944
2945 /* disable CPU FDI tx and PCH FDI rx */
2946 reg = FDI_TX_CTL(pipe);
2947 temp = I915_READ(reg);
2948 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2949 POSTING_READ(reg);
2950
2951 reg = FDI_RX_CTL(pipe);
2952 temp = I915_READ(reg);
2953 temp &= ~(0x7 << 16);
2954 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2955 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2956
2957 POSTING_READ(reg);
2958 udelay(100);
2959
2960 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2961 if (HAS_PCH_IBX(dev)) {
2962 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2963 I915_WRITE(FDI_RX_CHICKEN(pipe),
2964 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2965 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2966 } else if (HAS_PCH_CPT(dev)) {
2967 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2968 }
0fc932b8
JB		 2969
2970 /* still set train pattern 1 */
2971 reg = FDI_TX_CTL(pipe);
2972 temp = I915_READ(reg);
2973 temp &= ~FDI_LINK_TRAIN_NONE;
2974 temp |= FDI_LINK_TRAIN_PATTERN_1;
2975 I915_WRITE(reg, temp);
2976
2977 reg = FDI_RX_CTL(pipe);
2978 temp = I915_READ(reg);
2979 if (HAS_PCH_CPT(dev)) {
2980 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2981 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2982 } else {
2983 temp &= ~FDI_LINK_TRAIN_NONE;
2984 temp |= FDI_LINK_TRAIN_PATTERN_1;
2985 }
2986 /* BPC in FDI rx is consistent with that in PIPECONF */
2987 temp &= ~(0x07 << 16);
2988 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2989 I915_WRITE(reg, temp);
2990
2991 POSTING_READ(reg);
2992 udelay(100);
2993}
2994
6b383a7f
CW		 2995/*
2996 * When we disable a pipe, we need to clear any pending scanline wait events
2997 * to avoid hanging the ring, which we assume we are waiting on.
2998 */
2999static void intel_clear_scanline_wait(struct drm_device *dev)
3000{
3001 struct drm_i915_private *dev_priv = dev->dev_private;
8168bd48 3002 struct intel_ring_buffer *ring;
6b383a7f
CW		 3003 u32 tmp;
3004
3005 if (IS_GEN2(dev))
3006 /* Can't break the hang on i8xx */
3007 return;
3008
1ec14ad3 3009 ring = LP_RING(dev_priv);
8168bd48
CW		 3010 tmp = I915_READ_CTL(ring);
3011 if (tmp & RING_WAIT)
3012 I915_WRITE_CTL(ring, tmp);
6b383a7f
CW		 3013}
3014
e6c3a2a6
CW		 3015static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3016{
05394f39 3017 struct drm_i915_gem_object *obj;
e6c3a2a6
CW		 3018 struct drm_i915_private *dev_priv;
3019
3020 if (crtc->fb == NULL)
3021 return;
3022
05394f39 3023 obj = to_intel_framebuffer(crtc->fb)->obj;
e6c3a2a6
CW		 3024 dev_priv = crtc->dev->dev_private;
3025 wait_event(dev_priv->pending_flip_queue,
05394f39 3026 atomic_read(&obj->pending_flip) == 0);
e6c3a2a6
CW		 3027}
3028
040484af
JB		 3029static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
3030{
3031 struct drm_device *dev = crtc->dev;
3032 struct drm_mode_config *mode_config = &dev->mode_config;
3033 struct intel_encoder *encoder;
3034
3035 /*
3036 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
3037 * must be driven by its own crtc; no sharing is possible.
3038 */
3039 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3040 if (encoder->base.crtc != crtc)
3041 continue;
3042
3043 switch (encoder->type) {
3044 case INTEL_OUTPUT_EDP:
3045 if (!intel_encoder_is_pch_edp(&encoder->base))
3046 return false;
3047 continue;
3048 }
3049 }
3050
3051 return true;
3052}
3053
f67a559d
JB		 3054/*
3055 * Enable PCH resources required for PCH ports:
3056 * - PCH PLLs
3057 * - FDI training & RX/TX
3058 * - update transcoder timings
3059 * - DP transcoding bits
3060 * - transcoder
3061 */
3062static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3063{
3064 struct drm_device *dev = crtc->dev;
3065 struct drm_i915_private *dev_priv = dev->dev_private;
3066 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3067 int pipe = intel_crtc->pipe;
4b645f14 3068 u32 reg, temp, transc_sel;
2c07245f 3069
c98e9dcf 3070 /* For PCH output, training FDI link */
674cf967 3071 dev_priv->display.fdi_link_train(crtc);
2c07245f 3072
92f2584a 3073 intel_enable_pch_pll(dev_priv, pipe);
8db9d77b 3074
c98e9dcf 3075 if (HAS_PCH_CPT(dev)) {
4b645f14
JB		 3076 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
3077 TRANSC_DPLLB_SEL;
3078
c98e9dcf
JB		 3079 /* Be sure PCH DPLL SEL is set */
3080 temp = I915_READ(PCH_DPLL_SEL);
d64311ab
JB		 3081 if (pipe == 0) {
3082 temp &= ~(TRANSA_DPLLB_SEL);
c98e9dcf 3083 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
d64311ab
JB		 3084 } else if (pipe == 1) {
3085 temp &= ~(TRANSB_DPLLB_SEL);
c98e9dcf 3086 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
d64311ab
JB		 3087 } else if (pipe == 2) {
3088 temp &= ~(TRANSC_DPLLB_SEL);
4b645f14 3089 temp |= (TRANSC_DPLL_ENABLE | transc_sel);
d64311ab 3090 }
c98e9dcf 3091 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3092 }
5eddb70b 3093
d9b6cb56
JB		 3094 /* set transcoder timing, panel must allow it */
3095 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3096 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3097 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3098 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3099
5eddb70b
CW		 3100 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3101 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3102 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3103 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3104
5e84e1a4
ZW		 3105 intel_fdi_normal_train(crtc);
3106
c98e9dcf
JB		 3107 /* For PCH DP, enable TRANS_DP_CTL */
3108 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3109 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3110 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 3111 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 3112 reg = TRANS_DP_CTL(pipe);
3113 temp = I915_READ(reg);
3114 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3115 TRANS_DP_SYNC_MASK |
3116 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3117 temp |= (TRANS_DP_OUTPUT_ENABLE |
3118 TRANS_DP_ENH_FRAMING);
9325c9f0 3119 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3120
3121 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3122 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3123 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3124 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3125
3126 switch (intel_trans_dp_port_sel(crtc)) {
3127 case PCH_DP_B:
5eddb70b 3128 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3129 break;
3130 case PCH_DP_C:
5eddb70b 3131 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3132 break;
3133 case PCH_DP_D:
5eddb70b 3134 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3135 break;
3136 default:
3137 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 3138 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 3139 break;
32f9d658 3140 }
2c07245f 3141
5eddb70b 3142 I915_WRITE(reg, temp);
6be4a607 3143 }
b52eb4dc 3144
040484af 3145 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 3146}
3147
d4270e57
JB		 3148void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3149{
3150 struct drm_i915_private *dev_priv = dev->dev_private;
3151 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3152 u32 temp;
3153
3154 temp = I915_READ(dslreg);
3155 udelay(500);
3156 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3157 /* Without this, mode sets may fail silently on FDI */
3158 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3159 udelay(250);
3160 I915_WRITE(tc2reg, 0);
3161 if (wait_for(I915_READ(dslreg) != temp, 5))
3162 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3163 }
3164}
3165
f67a559d
JB		 3166static void ironlake_crtc_enable(struct drm_crtc *crtc)
3167{
3168 struct drm_device *dev = crtc->dev;
3169 struct drm_i915_private *dev_priv = dev->dev_private;
3170 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3171 int pipe = intel_crtc->pipe;
3172 int plane = intel_crtc->plane;
3173 u32 temp;
3174 bool is_pch_port;
3175
3176 if (intel_crtc->active)
3177 return;
3178
3179 intel_crtc->active = true;
3180 intel_update_watermarks(dev);
3181
3182 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3183 temp = I915_READ(PCH_LVDS);
3184 if ((temp & LVDS_PORT_EN) == 0)
3185 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3186 }
3187
3188 is_pch_port = intel_crtc_driving_pch(crtc);
3189
3190 if (is_pch_port)
357555c0 3191 ironlake_fdi_pll_enable(crtc);
f67a559d
JB		 3192 else
3193 ironlake_fdi_disable(crtc);
3194
3195 /* Enable panel fitting for LVDS */
3196 if (dev_priv->pch_pf_size &&
3197 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3198 /* Force use of hard-coded filter coefficients
3199 * as some pre-programmed values are broken,
3200 * e.g. x201.
3201 */
9db4a9c7
JB		 3202 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3203 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3204 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3205 }
3206
9c54c0dd
JB		 3207 /*
3208 * On ILK+ LUT must be loaded before the pipe is running but with
3209 * clocks enabled
3210 */
3211 intel_crtc_load_lut(crtc);
3212
f67a559d
JB		 3213 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3214 intel_enable_plane(dev_priv, plane, pipe);
3215
3216 if (is_pch_port)
3217 ironlake_pch_enable(crtc);
c98e9dcf 3218
d1ebd816 3219 mutex_lock(&dev->struct_mutex);
bed4a673 3220 intel_update_fbc(dev);
d1ebd816
BW		 3221 mutex_unlock(&dev->struct_mutex);
3222
6b383a7f 3223 intel_crtc_update_cursor(crtc, true);
6be4a607
JB		 3224}
3225
3226static void ironlake_crtc_disable(struct drm_crtc *crtc)
3227{
3228 struct drm_device *dev = crtc->dev;
3229 struct drm_i915_private *dev_priv = dev->dev_private;
3230 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3231 int pipe = intel_crtc->pipe;
3232 int plane = intel_crtc->plane;
5eddb70b 3233 u32 reg, temp;
b52eb4dc 3234
f7abfe8b
CW		 3235 if (!intel_crtc->active)
3236 return;
3237
e6c3a2a6 3238 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3239 drm_vblank_off(dev, pipe);
6b383a7f 3240 intel_crtc_update_cursor(crtc, false);
5eddb70b 3241
b24e7179 3242 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3243
973d04f9
CW		 3244 if (dev_priv->cfb_plane == plane)
3245 intel_disable_fbc(dev);
2c07245f 3246
b24e7179 3247 intel_disable_pipe(dev_priv, pipe);
32f9d658 3248
6be4a607 3249 /* Disable PF */
9db4a9c7
JB		 3250 I915_WRITE(PF_CTL(pipe), 0);
3251 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3252
0fc932b8 3253 ironlake_fdi_disable(crtc);
2c07245f 3254
47a05eca
JB		 3255 /* This is a horrible layering violation; we should be doing this in
3256 * the connector/encoder ->prepare instead, but we don't always have
3257 * enough information there about the config to know whether it will
3258 * actually be necessary or just cause undesired flicker.
3259 */
3260 intel_disable_pch_ports(dev_priv, pipe);
249c0e64 3261
040484af 3262 intel_disable_transcoder(dev_priv, pipe);
913d8d11 3263
6be4a607
JB		 3264 if (HAS_PCH_CPT(dev)) {
3265 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3266 reg = TRANS_DP_CTL(pipe);
3267 temp = I915_READ(reg);
3268 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3269 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3270 I915_WRITE(reg, temp);
6be4a607
JB		 3271
3272 /* disable DPLL_SEL */
3273 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3274 switch (pipe) {
3275 case 0:
d64311ab 3276 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3277 break;
3278 case 1:
6be4a607 3279 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3280 break;
3281 case 2:
4b645f14 3282 /* C shares PLL A or B */
d64311ab 3283 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3284 break;
3285 default:
3286 BUG(); /* wtf */
3287 }
6be4a607 3288 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3289 }
e3421a18 3290
6be4a607 3291 /* disable PCH DPLL */
4b645f14
JB		 3292 if (!intel_crtc->no_pll)
3293 intel_disable_pch_pll(dev_priv, pipe);
8db9d77b 3294
6be4a607 3295 /* Switch from PCDclk to Rawclk */
5eddb70b
CW		 3296 reg = FDI_RX_CTL(pipe);
3297 temp = I915_READ(reg);
3298 I915_WRITE(reg, temp & ~FDI_PCDCLK);
8db9d77b 3299
6be4a607 3300 /* Disable CPU FDI TX PLL */
5eddb70b
CW		 3301 reg = FDI_TX_CTL(pipe);
3302 temp = I915_READ(reg);
3303 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3304
3305 POSTING_READ(reg);
6be4a607 3306 udelay(100);
8db9d77b 3307
5eddb70b
CW		 3308 reg = FDI_RX_CTL(pipe);
3309 temp = I915_READ(reg);
3310 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2c07245f 3311
6be4a607 3312 /* Wait for the clocks to turn off. */
5eddb70b 3313 POSTING_READ(reg);
6be4a607 3314 udelay(100);
6b383a7f 3315
f7abfe8b 3316 intel_crtc->active = false;
6b383a7f 3317 intel_update_watermarks(dev);
d1ebd816
BW		 3318
3319 mutex_lock(&dev->struct_mutex);
6b383a7f
CW		 3320 intel_update_fbc(dev);
3321 intel_clear_scanline_wait(dev);
d1ebd816 3322 mutex_unlock(&dev->struct_mutex);
6be4a607 3323}
1b3c7a47 3324
6be4a607
JB		 3325static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3326{
3327 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3328 int pipe = intel_crtc->pipe;
3329 int plane = intel_crtc->plane;
8db9d77b 3330
6be4a607
JB		 3331 /* XXX: When our outputs are all unaware of DPMS modes other than off
3332 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3333 */
3334 switch (mode) {
3335 case DRM_MODE_DPMS_ON:
3336 case DRM_MODE_DPMS_STANDBY:
3337 case DRM_MODE_DPMS_SUSPEND:
3338 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3339 ironlake_crtc_enable(crtc);
3340 break;
1b3c7a47 3341
6be4a607
JB		 3342 case DRM_MODE_DPMS_OFF:
3343 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3344 ironlake_crtc_disable(crtc);
2c07245f
ZW		 3345 break;
3346 }
3347}
3348
02e792fb
DV		 3349static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3350{
02e792fb 3351 if (!enable && intel_crtc->overlay) {
23f09ce3 3352 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3353 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3354
23f09ce3 3355 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3356 dev_priv->mm.interruptible = false;
3357 (void) intel_overlay_switch_off(intel_crtc->overlay);
3358 dev_priv->mm.interruptible = true;
23f09ce3 3359 mutex_unlock(&dev->struct_mutex);
02e792fb 3360 }
02e792fb 3361
5dcdbcb0
CW		 3362 /* Let userspace switch the overlay on again. In most cases userspace
3363 * has to recompute where to put it anyway.
3364 */
02e792fb
DV		 3365}
3366
0b8765c6 3367static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3368{
3369 struct drm_device *dev = crtc->dev;
79e53945
JB		 3370 struct drm_i915_private *dev_priv = dev->dev_private;
3371 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3372 int pipe = intel_crtc->pipe;
80824003 3373 int plane = intel_crtc->plane;
79e53945 3374
f7abfe8b
CW		 3375 if (intel_crtc->active)
3376 return;
3377
3378 intel_crtc->active = true;
6b383a7f
CW		 3379 intel_update_watermarks(dev);
3380
63d7bbe9 3381 intel_enable_pll(dev_priv, pipe);
040484af 3382 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3383 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3384
0b8765c6 3385 intel_crtc_load_lut(crtc);
bed4a673 3386 intel_update_fbc(dev);
79e53945 3387
0b8765c6
JB		 3388 /* Give the overlay scaler a chance to enable if it's on this pipe */
3389 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3390 intel_crtc_update_cursor(crtc, true);
0b8765c6 3391}
79e53945 3392
0b8765c6
JB		 3393static void i9xx_crtc_disable(struct drm_crtc *crtc)
3394{
3395 struct drm_device *dev = crtc->dev;
3396 struct drm_i915_private *dev_priv = dev->dev_private;
3397 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3398 int pipe = intel_crtc->pipe;
3399 int plane = intel_crtc->plane;
b690e96c 3400
f7abfe8b
CW		 3401 if (!intel_crtc->active)
3402 return;
3403
0b8765c6 3404 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3405 intel_crtc_wait_for_pending_flips(crtc);
3406 drm_vblank_off(dev, pipe);
0b8765c6 3407 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3408 intel_crtc_update_cursor(crtc, false);
0b8765c6 3409
973d04f9
CW		 3410 if (dev_priv->cfb_plane == plane)
3411 intel_disable_fbc(dev);
79e53945 3412
b24e7179 3413 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3414 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3415 intel_disable_pll(dev_priv, pipe);
0b8765c6 3416
f7abfe8b 3417 intel_crtc->active = false;
6b383a7f
CW		 3418 intel_update_fbc(dev);
3419 intel_update_watermarks(dev);
3420 intel_clear_scanline_wait(dev);
0b8765c6
JB		 3421}
3422
3423static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3424{
3425 /* XXX: When our outputs are all unaware of DPMS modes other than off
3426 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3427 */
3428 switch (mode) {
3429 case DRM_MODE_DPMS_ON:
3430 case DRM_MODE_DPMS_STANDBY:
3431 case DRM_MODE_DPMS_SUSPEND:
3432 i9xx_crtc_enable(crtc);
3433 break;
3434 case DRM_MODE_DPMS_OFF:
3435 i9xx_crtc_disable(crtc);
79e53945
JB		 3436 break;
3437 }
2c07245f
ZW		 3438}
3439
3440/**
3441 * Sets the power management mode of the pipe and plane.
2c07245f
ZW		 3442 */
3443static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3444{
3445 struct drm_device *dev = crtc->dev;
e70236a8 3446 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f
ZW		 3447 struct drm_i915_master_private *master_priv;
3448 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3449 int pipe = intel_crtc->pipe;
3450 bool enabled;
3451
032d2a0d
CW		 3452 if (intel_crtc->dpms_mode == mode)
3453 return;
3454
65655d4a 3455 intel_crtc->dpms_mode = mode;
debcaddc 3456
e70236a8 3457 dev_priv->display.dpms(crtc, mode);
79e53945
JB		 3458
3459 if (!dev->primary->master)
3460 return;
3461
3462 master_priv = dev->primary->master->driver_priv;
3463 if (!master_priv->sarea_priv)
3464 return;
3465
3466 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3467
3468 switch (pipe) {
3469 case 0:
3470 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3471 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3472 break;
3473 case 1:
3474 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3475 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3476 break;
3477 default:
9db4a9c7 3478 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3479 break;
3480 }
79e53945
JB		 3481}
3482
cdd59983
CW		 3483static void intel_crtc_disable(struct drm_crtc *crtc)
3484{
3485 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3486 struct drm_device *dev = crtc->dev;
3487
14667a4b
CW		 3488 /* Flush any pending WAITs before we disable the pipe. Note that
3489 * we need to drop the struct_mutex in order to acquire it again
3490 * during the lowlevel dpms routines around a couple of the
3491 * operations. It does not look trivial nor desirable to move
3492 * that locking higher. So instead we leave a window for the
3493 * submission of further commands on the fb before we can actually
3494 * disable it. This race with userspace exists anyway, and we can
3495 * only rely on the pipe being disabled by userspace after it
3496 * receives the hotplug notification and has flushed any pending
3497 * batches.
3498 */
3499 if (crtc->fb) {
3500 mutex_lock(&dev->struct_mutex);
3501 intel_finish_fb(crtc->fb);
3502 mutex_unlock(&dev->struct_mutex);
3503 }
3504
cdd59983 3505 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
931872fc
CW		 3506 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3507 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3508
3509 if (crtc->fb) {
3510 mutex_lock(&dev->struct_mutex);
1690e1eb 3511 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983
CW		 3512 mutex_unlock(&dev->struct_mutex);
3513 }
3514}
3515
7e7d76c3
JB		 3516/* Prepare for a mode set.
3517 *
3518 * Note we could be a lot smarter here. We need to figure out which outputs
3519 * will be enabled, which disabled (in short, how the config will changes)
3520 * and perform the minimum necessary steps to accomplish that, e.g. updating
3521 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3522 * panel fitting is in the proper state, etc.
3523 */
3524static void i9xx_crtc_prepare(struct drm_crtc *crtc)
79e53945 3525{
7e7d76c3 3526 i9xx_crtc_disable(crtc);
79e53945
JB		 3527}
3528
7e7d76c3 3529static void i9xx_crtc_commit(struct drm_crtc *crtc)
79e53945 3530{
7e7d76c3 3531 i9xx_crtc_enable(crtc);
7e7d76c3
JB		 3532}
3533
3534static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3535{
7e7d76c3 3536 ironlake_crtc_disable(crtc);
7e7d76c3
JB		 3537}
3538
3539static void ironlake_crtc_commit(struct drm_crtc *crtc)
3540{
7e7d76c3 3541 ironlake_crtc_enable(crtc);
79e53945
JB		 3542}
3543
0206e353 3544void intel_encoder_prepare(struct drm_encoder *encoder)
79e53945
JB		 3545{
3546 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3547 /* lvds has its own version of prepare see intel_lvds_prepare */
3548 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3549}
3550
0206e353 3551void intel_encoder_commit(struct drm_encoder *encoder)
79e53945
JB		 3552{
3553 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
d4270e57
JB		 3554 struct drm_device *dev = encoder->dev;
3555 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3556 struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3557
79e53945
JB		 3558 /* lvds has its own version of commit see intel_lvds_commit */
3559 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
d4270e57
JB		 3560
3561 if (HAS_PCH_CPT(dev))
3562 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
79e53945
JB		 3563}
3564
ea5b213a
CW		 3565void intel_encoder_destroy(struct drm_encoder *encoder)
3566{
4ef69c7a 3567 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3568
ea5b213a
CW		 3569 drm_encoder_cleanup(encoder);
3570 kfree(intel_encoder);
3571}
3572
79e53945
JB		 3573static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3574 struct drm_display_mode *mode,
3575 struct drm_display_mode *adjusted_mode)
3576{
2c07245f 3577 struct drm_device *dev = crtc->dev;
89749350 3578
bad720ff 3579 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3580 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3581 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3582 return false;
2c07245f 3583 }
89749350 3584
ca9bfa7e
DV		 3585 /* All interlaced capable intel hw wants timings in frames. */
3586 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3587
79e53945
JB		 3588 return true;
3589}
3590
25eb05fc
JB		 3591static int valleyview_get_display_clock_speed(struct drm_device *dev)
3592{
3593 return 400000; /* FIXME */
3594}
3595
e70236a8
JB		 3596static int i945_get_display_clock_speed(struct drm_device *dev)
3597{
3598 return 400000;
3599}
79e53945 3600
e70236a8 3601static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3602{
e70236a8
JB		 3603 return 333000;
3604}
79e53945 3605
e70236a8
JB		 3606static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3607{
3608 return 200000;
3609}
79e53945 3610
e70236a8
JB		 3611static int i915gm_get_display_clock_speed(struct drm_device *dev)
3612{
3613 u16 gcfgc = 0;
79e53945 3614
e70236a8
JB		 3615 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3616
3617 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3618 return 133000;
3619 else {
3620 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3621 case GC_DISPLAY_CLOCK_333_MHZ:
3622 return 333000;
3623 default:
3624 case GC_DISPLAY_CLOCK_190_200_MHZ:
3625 return 190000;
79e53945 3626 }
e70236a8
JB		 3627 }
3628}
3629
3630static int i865_get_display_clock_speed(struct drm_device *dev)
3631{
3632 return 266000;
3633}
3634
3635static int i855_get_display_clock_speed(struct drm_device *dev)
3636{
3637 u16 hpllcc = 0;
3638 /* Assume that the hardware is in the high speed state. This
3639 * should be the default.
3640 */
3641 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3642 case GC_CLOCK_133_200:
3643 case GC_CLOCK_100_200:
3644 return 200000;
3645 case GC_CLOCK_166_250:
3646 return 250000;
3647 case GC_CLOCK_100_133:
79e53945 3648 return 133000;
e70236a8 3649 }
79e53945 3650
e70236a8
JB		 3651 /* Shouldn't happen */
3652 return 0;
3653}
79e53945 3654
e70236a8
JB		 3655static int i830_get_display_clock_speed(struct drm_device *dev)
3656{
3657 return 133000;
79e53945
JB		 3658}
3659
2c07245f
ZW		 3660struct fdi_m_n {
3661 u32 tu;
3662 u32 gmch_m;
3663 u32 gmch_n;
3664 u32 link_m;
3665 u32 link_n;
3666};
3667
3668static void
3669fdi_reduce_ratio(u32 *num, u32 *den)
3670{
3671 while (*num > 0xffffff || *den > 0xffffff) {
3672 *num >>= 1;
3673 *den >>= 1;
3674 }
3675}
3676
2c07245f 3677static void
f2b115e6
AJ		 3678ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3679 int link_clock, struct fdi_m_n *m_n)
2c07245f 3680{
2c07245f
ZW		 3681 m_n->tu = 64; /* default size */
3682
22ed1113
CW		 3683 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3684 m_n->gmch_m = bits_per_pixel * pixel_clock;
3685 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3686 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3687
22ed1113
CW		 3688 m_n->link_m = pixel_clock;
3689 m_n->link_n = link_clock;
2c07245f
ZW		 3690 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3691}
3692
3693
7662c8bd
SL		 3694struct intel_watermark_params {
3695 unsigned long fifo_size;
3696 unsigned long max_wm;
3697 unsigned long default_wm;
3698 unsigned long guard_size;
3699 unsigned long cacheline_size;
3700};
3701
f2b115e6 3702/* Pineview has different values for various configs */
d210246a 3703static const struct intel_watermark_params pineview_display_wm = {
f2b115e6
AJ		 3704 PINEVIEW_DISPLAY_FIFO,
3705 PINEVIEW_MAX_WM,
3706 PINEVIEW_DFT_WM,
3707 PINEVIEW_GUARD_WM,
3708 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3709};
d210246a 3710static const struct intel_watermark_params pineview_display_hplloff_wm = {
f2b115e6
AJ		 3711 PINEVIEW_DISPLAY_FIFO,
3712 PINEVIEW_MAX_WM,
3713 PINEVIEW_DFT_HPLLOFF_WM,
3714 PINEVIEW_GUARD_WM,
3715 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3716};
d210246a 3717static const struct intel_watermark_params pineview_cursor_wm = {
f2b115e6
AJ		 3718 PINEVIEW_CURSOR_FIFO,
3719 PINEVIEW_CURSOR_MAX_WM,
3720 PINEVIEW_CURSOR_DFT_WM,
3721 PINEVIEW_CURSOR_GUARD_WM,
3722 PINEVIEW_FIFO_LINE_SIZE,
7662c8bd 3723};
d210246a 3724static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
f2b115e6
AJ		 3725 PINEVIEW_CURSOR_FIFO,
3726 PINEVIEW_CURSOR_MAX_WM,
3727 PINEVIEW_CURSOR_DFT_WM,
3728 PINEVIEW_CURSOR_GUARD_WM,
3729 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3730};
d210246a 3731static const struct intel_watermark_params g4x_wm_info = {
0e442c60
JB		 3732 G4X_FIFO_SIZE,
3733 G4X_MAX_WM,
3734 G4X_MAX_WM,
3735 2,
3736 G4X_FIFO_LINE_SIZE,
3737};
d210246a 3738static const struct intel_watermark_params g4x_cursor_wm_info = {
4fe5e611
ZY		 3739 I965_CURSOR_FIFO,
3740 I965_CURSOR_MAX_WM,
3741 I965_CURSOR_DFT_WM,
3742 2,
3743 G4X_FIFO_LINE_SIZE,
3744};
ceb04246
JB		 3745static const struct intel_watermark_params valleyview_wm_info = {
3746 VALLEYVIEW_FIFO_SIZE,
3747 VALLEYVIEW_MAX_WM,
3748 VALLEYVIEW_MAX_WM,
3749 2,
3750 G4X_FIFO_LINE_SIZE,
3751};
3752static const struct intel_watermark_params valleyview_cursor_wm_info = {
3753 I965_CURSOR_FIFO,
3754 VALLEYVIEW_CURSOR_MAX_WM,
3755 I965_CURSOR_DFT_WM,
3756 2,
3757 G4X_FIFO_LINE_SIZE,
3758};
d210246a 3759static const struct intel_watermark_params i965_cursor_wm_info = {
4fe5e611
ZY		 3760 I965_CURSOR_FIFO,
3761 I965_CURSOR_MAX_WM,
3762 I965_CURSOR_DFT_WM,
3763 2,
3764 I915_FIFO_LINE_SIZE,
3765};
d210246a 3766static const struct intel_watermark_params i945_wm_info = {
dff33cfc 3767 I945_FIFO_SIZE,
7662c8bd
SL		 3768 I915_MAX_WM,
3769 1,
dff33cfc
JB		 3770 2,
3771 I915_FIFO_LINE_SIZE
7662c8bd 3772};
d210246a 3773static const struct intel_watermark_params i915_wm_info = {
dff33cfc 3774 I915_FIFO_SIZE,
7662c8bd
SL		 3775 I915_MAX_WM,
3776 1,
dff33cfc 3777 2,
7662c8bd
SL		 3778 I915_FIFO_LINE_SIZE
3779};
d210246a 3780static const struct intel_watermark_params i855_wm_info = {
7662c8bd
SL		 3781 I855GM_FIFO_SIZE,
3782 I915_MAX_WM,
3783 1,
dff33cfc 3784 2,
7662c8bd
SL		 3785 I830_FIFO_LINE_SIZE
3786};
d210246a 3787static const struct intel_watermark_params i830_wm_info = {
7662c8bd
SL		 3788 I830_FIFO_SIZE,
3789 I915_MAX_WM,
3790 1,
dff33cfc 3791 2,
7662c8bd
SL		 3792 I830_FIFO_LINE_SIZE
3793};
3794
d210246a 3795static const struct intel_watermark_params ironlake_display_wm_info = {
7f8a8569
ZW		 3796 ILK_DISPLAY_FIFO,
3797 ILK_DISPLAY_MAXWM,
3798 ILK_DISPLAY_DFTWM,
3799 2,
3800 ILK_FIFO_LINE_SIZE
3801};
d210246a 3802static const struct intel_watermark_params ironlake_cursor_wm_info = {
c936f44d
ZY		 3803 ILK_CURSOR_FIFO,
3804 ILK_CURSOR_MAXWM,
3805 ILK_CURSOR_DFTWM,
3806 2,
3807 ILK_FIFO_LINE_SIZE
3808};
d210246a 3809static const struct intel_watermark_params ironlake_display_srwm_info = {
7f8a8569
ZW		 3810 ILK_DISPLAY_SR_FIFO,
3811 ILK_DISPLAY_MAX_SRWM,
3812 ILK_DISPLAY_DFT_SRWM,
3813 2,
3814 ILK_FIFO_LINE_SIZE
3815};
d210246a 3816static const struct intel_watermark_params ironlake_cursor_srwm_info = {
7f8a8569
ZW		 3817 ILK_CURSOR_SR_FIFO,
3818 ILK_CURSOR_MAX_SRWM,
3819 ILK_CURSOR_DFT_SRWM,
3820 2,
3821 ILK_FIFO_LINE_SIZE
3822};
3823
d210246a 3824static const struct intel_watermark_params sandybridge_display_wm_info = {
1398261a
YL		 3825 SNB_DISPLAY_FIFO,
3826 SNB_DISPLAY_MAXWM,
3827 SNB_DISPLAY_DFTWM,
3828 2,
3829 SNB_FIFO_LINE_SIZE
3830};
d210246a 3831static const struct intel_watermark_params sandybridge_cursor_wm_info = {
1398261a
YL		 3832 SNB_CURSOR_FIFO,
3833 SNB_CURSOR_MAXWM,
3834 SNB_CURSOR_DFTWM,
3835 2,
3836 SNB_FIFO_LINE_SIZE
3837};
d210246a 3838static const struct intel_watermark_params sandybridge_display_srwm_info = {
1398261a
YL		 3839 SNB_DISPLAY_SR_FIFO,
3840 SNB_DISPLAY_MAX_SRWM,
3841 SNB_DISPLAY_DFT_SRWM,
3842 2,
3843 SNB_FIFO_LINE_SIZE
3844};
d210246a 3845static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1398261a
YL		 3846 SNB_CURSOR_SR_FIFO,
3847 SNB_CURSOR_MAX_SRWM,
3848 SNB_CURSOR_DFT_SRWM,
3849 2,
3850 SNB_FIFO_LINE_SIZE
3851};
3852
3853
dff33cfc
JB		 3854/**
3855 * intel_calculate_wm - calculate watermark level
3856 * @clock_in_khz: pixel clock
3857 * @wm: chip FIFO params
3858 * @pixel_size: display pixel size
3859 * @latency_ns: memory latency for the platform
3860 *
3861 * Calculate the watermark level (the level at which the display plane will
3862 * start fetching from memory again). Each chip has a different display
3863 * FIFO size and allocation, so the caller needs to figure that out and pass
3864 * in the correct intel_watermark_params structure.
3865 *
3866 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3867 * on the pixel size. When it reaches the watermark level, it'll start
3868 * fetching FIFO line sized based chunks from memory until the FIFO fills
3869 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3870 * will occur, and a display engine hang could result.
3871 */
7662c8bd 3872static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
d210246a
CW		 3873 const struct intel_watermark_params *wm,
3874 int fifo_size,
7662c8bd
SL		 3875 int pixel_size,
3876 unsigned long latency_ns)
3877{
390c4dd4 3878 long entries_required, wm_size;
dff33cfc 3879
d660467c
JB		 3880 /*
3881 * Note: we need to make sure we don't overflow for various clock &
3882 * latency values.
3883 * clocks go from a few thousand to several hundred thousand.
3884 * latency is usually a few thousand
3885 */
3886 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3887 1000;
8de9b311 3888 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
7662c8bd 3889
bbb0aef5 3890 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
dff33cfc 3891
d210246a 3892 wm_size = fifo_size - (entries_required + wm->guard_size);
dff33cfc 3893
bbb0aef5 3894 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
7662c8bd 3895
390c4dd4
JB		 3896 /* Don't promote wm_size to unsigned... */
3897 if (wm_size > (long)wm->max_wm)
7662c8bd 3898 wm_size = wm->max_wm;
c3add4b6 3899 if (wm_size <= 0)
7662c8bd
SL		 3900 wm_size = wm->default_wm;
3901 return wm_size;
3902}
3903
3904struct cxsr_latency {
3905 int is_desktop;
95534263 3906 int is_ddr3;
7662c8bd
SL		 3907 unsigned long fsb_freq;
3908 unsigned long mem_freq;
3909 unsigned long display_sr;
3910 unsigned long display_hpll_disable;
3911 unsigned long cursor_sr;
3912 unsigned long cursor_hpll_disable;
3913};
3914
403c89ff 3915static const struct cxsr_latency cxsr_latency_table[] = {
95534263
LP		 3916 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3917 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3918 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3919 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3920 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3921
3922 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3923 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3924 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3925 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3926 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3927
3928 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3929 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3930 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3931 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3932 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3933
3934 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3935 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3936 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3937 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3938 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3939
3940 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3941 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3942 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3943 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3944 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3945
3946 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3947 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3948 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3949 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3950 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
7662c8bd
SL		 3951};
3952
403c89ff
CW		 3953static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3954 int is_ddr3,
3955 int fsb,
3956 int mem)
7662c8bd 3957{
403c89ff 3958 const struct cxsr_latency *latency;
7662c8bd 3959 int i;
7662c8bd
SL		 3960
3961 if (fsb == 0 || mem == 0)
3962 return NULL;
3963
3964 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3965 latency = &cxsr_latency_table[i];
3966 if (is_desktop == latency->is_desktop &&
95534263 3967 is_ddr3 == latency->is_ddr3 &&
decbbcda
JSR		 3968 fsb == latency->fsb_freq && mem == latency->mem_freq)
3969 return latency;
7662c8bd 3970 }
decbbcda 3971
28c97730 3972 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
decbbcda
JSR		 3973
3974 return NULL;
7662c8bd
SL		 3975}
3976
f2b115e6 3977static void pineview_disable_cxsr(struct drm_device *dev)
7662c8bd
SL		 3978{
3979 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd
SL		 3980
3981 /* deactivate cxsr */
3e33d94d 3982 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
7662c8bd
SL		 3983}
3984
bcc24fb4
JB		 3985/*
3986 * Latency for FIFO fetches is dependent on several factors:
3987 * - memory configuration (speed, channels)
3988 * - chipset
3989 * - current MCH state
3990 * It can be fairly high in some situations, so here we assume a fairly
3991 * pessimal value. It's a tradeoff between extra memory fetches (if we
3992 * set this value too high, the FIFO will fetch frequently to stay full)
3993 * and power consumption (set it too low to save power and we might see
3994 * FIFO underruns and display "flicker").
3995 *
3996 * A value of 5us seems to be a good balance; safe for very low end
3997 * platforms but not overly aggressive on lower latency configs.
3998 */
69e302a9 3999static const int latency_ns = 5000;
7662c8bd 4000
e70236a8 4001static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
dff33cfc
JB		 4002{
4003 struct drm_i915_private *dev_priv = dev->dev_private;
4004 uint32_t dsparb = I915_READ(DSPARB);
4005 int size;
4006
8de9b311
CW		 4007 size = dsparb & 0x7f;
4008 if (plane)
4009 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
dff33cfc 4010
28c97730 4011 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 4012 plane ? "B" : "A", size);
dff33cfc
JB		 4013
4014 return size;
4015}
7662c8bd 4016
e70236a8
JB		 4017static int i85x_get_fifo_size(struct drm_device *dev, int plane)
4018{
4019 struct drm_i915_private *dev_priv = dev->dev_private;
4020 uint32_t dsparb = I915_READ(DSPARB);
4021 int size;
4022
8de9b311
CW		 4023 size = dsparb & 0x1ff;
4024 if (plane)
4025 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
e70236a8 4026 size >>= 1; /* Convert to cachelines */
dff33cfc 4027
28c97730 4028 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 4029 plane ? "B" : "A", size);
dff33cfc
JB		 4030
4031 return size;
4032}
7662c8bd 4033
e70236a8
JB		 4034static int i845_get_fifo_size(struct drm_device *dev, int plane)
4035{
4036 struct drm_i915_private *dev_priv = dev->dev_private;
4037 uint32_t dsparb = I915_READ(DSPARB);
4038 int size;
4039
4040 size = dsparb & 0x7f;
4041 size >>= 2; /* Convert to cachelines */
4042
28c97730 4043 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b
CW		 4044 plane ? "B" : "A",
4045 size);
e70236a8
JB		 4046
4047 return size;
4048}
4049
4050static int i830_get_fifo_size(struct drm_device *dev, int plane)
4051{
4052 struct drm_i915_private *dev_priv = dev->dev_private;
4053 uint32_t dsparb = I915_READ(DSPARB);
4054 int size;
4055
4056 size = dsparb & 0x7f;
4057 size >>= 1; /* Convert to cachelines */
4058
28c97730 4059 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 4060 plane ? "B" : "A", size);
e70236a8
JB		 4061
4062 return size;
4063}
4064
d210246a
CW		 4065static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
4066{
4067 struct drm_crtc *crtc, *enabled = NULL;
4068
4069 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4070 if (crtc->enabled && crtc->fb) {
4071 if (enabled)
4072 return NULL;
4073 enabled = crtc;
4074 }
4075 }
4076
4077 return enabled;
4078}
4079
4080static void pineview_update_wm(struct drm_device *dev)
d4294342
ZY		 4081{
4082 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 4083 struct drm_crtc *crtc;
403c89ff 4084 const struct cxsr_latency *latency;
d4294342
ZY		 4085 u32 reg;
4086 unsigned long wm;
d4294342 4087
403c89ff 4088 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
95534263 4089 dev_priv->fsb_freq, dev_priv->mem_freq);
d4294342
ZY		 4090 if (!latency) {
4091 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
4092 pineview_disable_cxsr(dev);
4093 return;
4094 }
4095
d210246a
CW		 4096 crtc = single_enabled_crtc(dev);
4097 if (crtc) {
4098 int clock = crtc->mode.clock;
4099 int pixel_size = crtc->fb->bits_per_pixel / 8;
d4294342
ZY		 4100
4101 /* Display SR */
d210246a
CW		 4102 wm = intel_calculate_wm(clock, &pineview_display_wm,
4103 pineview_display_wm.fifo_size,
d4294342
ZY		 4104 pixel_size, latency->display_sr);
4105 reg = I915_READ(DSPFW1);
4106 reg &= ~DSPFW_SR_MASK;
4107 reg |= wm << DSPFW_SR_SHIFT;
4108 I915_WRITE(DSPFW1, reg);
4109 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
4110
4111 /* cursor SR */
d210246a
CW		 4112 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
4113 pineview_display_wm.fifo_size,
d4294342
ZY		 4114 pixel_size, latency->cursor_sr);
4115 reg = I915_READ(DSPFW3);
4116 reg &= ~DSPFW_CURSOR_SR_MASK;
4117 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
4118 I915_WRITE(DSPFW3, reg);
4119
4120 /* Display HPLL off SR */
d210246a
CW		 4121 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
4122 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 4123 pixel_size, latency->display_hpll_disable);
4124 reg = I915_READ(DSPFW3);
4125 reg &= ~DSPFW_HPLL_SR_MASK;
4126 reg |= wm & DSPFW_HPLL_SR_MASK;
4127 I915_WRITE(DSPFW3, reg);
4128
4129 /* cursor HPLL off SR */
d210246a
CW		 4130 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
4131 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 4132 pixel_size, latency->cursor_hpll_disable);
4133 reg = I915_READ(DSPFW3);
4134 reg &= ~DSPFW_HPLL_CURSOR_MASK;
4135 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
4136 I915_WRITE(DSPFW3, reg);
4137 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
4138
4139 /* activate cxsr */
3e33d94d
CW		 4140 I915_WRITE(DSPFW3,
4141 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
d4294342
ZY		 4142 DRM_DEBUG_KMS("Self-refresh is enabled\n");
4143 } else {
4144 pineview_disable_cxsr(dev);
4145 DRM_DEBUG_KMS("Self-refresh is disabled\n");
4146 }
4147}
4148
417ae147
CW		 4149static bool g4x_compute_wm0(struct drm_device *dev,
4150 int plane,
4151 const struct intel_watermark_params *display,
4152 int display_latency_ns,
4153 const struct intel_watermark_params *cursor,
4154 int cursor_latency_ns,
4155 int *plane_wm,
4156 int *cursor_wm)
4157{
4158 struct drm_crtc *crtc;
4159 int htotal, hdisplay, clock, pixel_size;
4160 int line_time_us, line_count;
4161 int entries, tlb_miss;
4162
4163 crtc = intel_get_crtc_for_plane(dev, plane);
5c72d064
CW		 4164 if (crtc->fb == NULL || !crtc->enabled) {
4165 *cursor_wm = cursor->guard_size;
4166 *plane_wm = display->guard_size;
417ae147 4167 return false;
5c72d064 4168 }
417ae147
CW		 4169
4170 htotal = crtc->mode.htotal;
4171 hdisplay = crtc->mode.hdisplay;
4172 clock = crtc->mode.clock;
4173 pixel_size = crtc->fb->bits_per_pixel / 8;
4174
4175 /* Use the small buffer method to calculate plane watermark */
4176 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4177 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
4178 if (tlb_miss > 0)
4179 entries += tlb_miss;
4180 entries = DIV_ROUND_UP(entries, display->cacheline_size);
4181 *plane_wm = entries + display->guard_size;
4182 if (*plane_wm > (int)display->max_wm)
4183 *plane_wm = display->max_wm;
4184
4185 /* Use the large buffer method to calculate cursor watermark */
4186 line_time_us = ((htotal * 1000) / clock);
4187 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
4188 entries = line_count * 64 * pixel_size;
4189 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
4190 if (tlb_miss > 0)
4191 entries += tlb_miss;
4192 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4193 *cursor_wm = entries + cursor->guard_size;
4194 if (*cursor_wm > (int)cursor->max_wm)
4195 *cursor_wm = (int)cursor->max_wm;
4196
4197 return true;
4198}
4199
4200/*
4201 * Check the wm result.
4202 *
4203 * If any calculated watermark values is larger than the maximum value that
4204 * can be programmed into the associated watermark register, that watermark
4205 * must be disabled.
4206 */
4207static bool g4x_check_srwm(struct drm_device *dev,
4208 int display_wm, int cursor_wm,
4209 const struct intel_watermark_params *display,
4210 const struct intel_watermark_params *cursor)
652c393a 4211{
417ae147
CW		 4212 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4213 display_wm, cursor_wm);
652c393a 4214
417ae147 4215 if (display_wm > display->max_wm) {
bbb0aef5 4216 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 4217 display_wm, display->max_wm);
4218 return false;
4219 }
0e442c60 4220
417ae147 4221 if (cursor_wm > cursor->max_wm) {
bbb0aef5 4222 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 4223 cursor_wm, cursor->max_wm);
4224 return false;
4225 }
0e442c60 4226
417ae147
CW		 4227 if (!(display_wm || cursor_wm)) {
4228 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4229 return false;
4230 }
0e442c60 4231
417ae147
CW		 4232 return true;
4233}
0e442c60 4234
417ae147 4235static bool g4x_compute_srwm(struct drm_device *dev,
d210246a
CW		 4236 int plane,
4237 int latency_ns,
417ae147
CW		 4238 const struct intel_watermark_params *display,
4239 const struct intel_watermark_params *cursor,
4240 int *display_wm, int *cursor_wm)
4241{
d210246a
CW		 4242 struct drm_crtc *crtc;
4243 int hdisplay, htotal, pixel_size, clock;
417ae147
CW		 4244 unsigned long line_time_us;
4245 int line_count, line_size;
4246 int small, large;
4247 int entries;
0e442c60 4248
417ae147
CW		 4249 if (!latency_ns) {
4250 *display_wm = *cursor_wm = 0;
4251 return false;
4252 }
0e442c60 4253
d210246a
CW		 4254 crtc = intel_get_crtc_for_plane(dev, plane);
4255 hdisplay = crtc->mode.hdisplay;
4256 htotal = crtc->mode.htotal;
4257 clock = crtc->mode.clock;
4258 pixel_size = crtc->fb->bits_per_pixel / 8;
4259
417ae147
CW		 4260 line_time_us = (htotal * 1000) / clock;
4261 line_count = (latency_ns / line_time_us + 1000) / 1000;
4262 line_size = hdisplay * pixel_size;
0e442c60 4263
417ae147
CW		 4264 /* Use the minimum of the small and large buffer method for primary */
4265 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4266 large = line_count * line_size;
0e442c60 4267
417ae147
CW		 4268 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4269 *display_wm = entries + display->guard_size;
4fe5e611 4270
417ae147
CW		 4271 /* calculate the self-refresh watermark for display cursor */
4272 entries = line_count * pixel_size * 64;
4273 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4274 *cursor_wm = entries + cursor->guard_size;
4fe5e611 4275
417ae147
CW		 4276 return g4x_check_srwm(dev,
4277 *display_wm, *cursor_wm,
4278 display, cursor);
4279}
4fe5e611 4280
12a3c055
GB		 4281static bool vlv_compute_drain_latency(struct drm_device *dev,
4282 int plane,
4283 int *plane_prec_mult,
4284 int *plane_dl,
4285 int *cursor_prec_mult,
4286 int *cursor_dl)
4287{
4288 struct drm_crtc *crtc;
4289 int clock, pixel_size;
4290 int entries;
4291
4292 crtc = intel_get_crtc_for_plane(dev, plane);
4293 if (crtc->fb == NULL || !crtc->enabled)
4294 return false;
4295
4296 clock = crtc->mode.clock; /* VESA DOT Clock */
4297 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
4298
4299 entries = (clock / 1000) * pixel_size;
4300 *plane_prec_mult = (entries > 256) ?
4301 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
4302 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
4303 pixel_size);
4304
4305 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
4306 *cursor_prec_mult = (entries > 256) ?
4307 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
4308 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
4309
4310 return true;
4311}
4312
4313/*
4314 * Update drain latency registers of memory arbiter
4315 *
4316 * Valleyview SoC has a new memory arbiter and needs drain latency registers
4317 * to be programmed. Each plane has a drain latency multiplier and a drain
4318 * latency value.
4319 */
4320
4321static void vlv_update_drain_latency(struct drm_device *dev)
4322{
4323 struct drm_i915_private *dev_priv = dev->dev_private;
4324 int planea_prec, planea_dl, planeb_prec, planeb_dl;
4325 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
4326 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
4327 either 16 or 32 */
4328
4329 /* For plane A, Cursor A */
4330 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
4331 &cursor_prec_mult, &cursora_dl)) {
4332 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
4333 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
4334 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
4335 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
4336
4337 I915_WRITE(VLV_DDL1, cursora_prec |
4338 (cursora_dl << DDL_CURSORA_SHIFT) |
4339 planea_prec | planea_dl);
4340 }
4341
4342 /* For plane B, Cursor B */
4343 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
4344 &cursor_prec_mult, &cursorb_dl)) {
4345 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
4346 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
4347 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
4348 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
4349
4350 I915_WRITE(VLV_DDL2, cursorb_prec |
4351 (cursorb_dl << DDL_CURSORB_SHIFT) |
4352 planeb_prec | planeb_dl);
4353 }
4354}
4355
7ccb4a53 4356#define single_plane_enabled(mask) is_power_of_2(mask)
d210246a 4357
ceb04246
JB		 4358static void valleyview_update_wm(struct drm_device *dev)
4359{
4360 static const int sr_latency_ns = 12000;
4361 struct drm_i915_private *dev_priv = dev->dev_private;
4362 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4363 int plane_sr, cursor_sr;
4364 unsigned int enabled = 0;
4365
12a3c055
GB		 4366 vlv_update_drain_latency(dev);
4367
ceb04246
JB		 4368 if (g4x_compute_wm0(dev, 0,
4369 &valleyview_wm_info, latency_ns,
4370 &valleyview_cursor_wm_info, latency_ns,
4371 &planea_wm, &cursora_wm))
4372 enabled |= 1;
4373
4374 if (g4x_compute_wm0(dev, 1,
4375 &valleyview_wm_info, latency_ns,
4376 &valleyview_cursor_wm_info, latency_ns,
4377 &planeb_wm, &cursorb_wm))
4378 enabled |= 2;
4379
4380 plane_sr = cursor_sr = 0;
4381 if (single_plane_enabled(enabled) &&
4382 g4x_compute_srwm(dev, ffs(enabled) - 1,
4383 sr_latency_ns,
4384 &valleyview_wm_info,
4385 &valleyview_cursor_wm_info,
4386 &plane_sr, &cursor_sr))
4387 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
4388 else
4389 I915_WRITE(FW_BLC_SELF_VLV,
4390 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
4391
4392 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4393 planea_wm, cursora_wm,
4394 planeb_wm, cursorb_wm,
4395 plane_sr, cursor_sr);
4396
4397 I915_WRITE(DSPFW1,
4398 (plane_sr << DSPFW_SR_SHIFT) |
4399 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4400 (planeb_wm << DSPFW_PLANEB_SHIFT) |
4401 planea_wm);
4402 I915_WRITE(DSPFW2,
4403 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4404 (cursora_wm << DSPFW_CURSORA_SHIFT));
4405 I915_WRITE(DSPFW3,
4406 (I915_READ(DSPFW3) | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)));
4407}
4408
d210246a 4409static void g4x_update_wm(struct drm_device *dev)
417ae147
CW		 4410{
4411 static const int sr_latency_ns = 12000;
4412 struct drm_i915_private *dev_priv = dev->dev_private;
4413 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
d210246a
CW		 4414 int plane_sr, cursor_sr;
4415 unsigned int enabled = 0;
417ae147
CW		 4416
4417 if (g4x_compute_wm0(dev, 0,
4418 &g4x_wm_info, latency_ns,
4419 &g4x_cursor_wm_info, latency_ns,
4420 &planea_wm, &cursora_wm))
d210246a 4421 enabled |= 1;
417ae147
CW		 4422
4423 if (g4x_compute_wm0(dev, 1,
4424 &g4x_wm_info, latency_ns,
4425 &g4x_cursor_wm_info, latency_ns,
4426 &planeb_wm, &cursorb_wm))
d210246a 4427 enabled |= 2;
417ae147
CW		 4428
4429 plane_sr = cursor_sr = 0;
d210246a
CW		 4430 if (single_plane_enabled(enabled) &&
4431 g4x_compute_srwm(dev, ffs(enabled) - 1,
4432 sr_latency_ns,
417ae147
CW		 4433 &g4x_wm_info,
4434 &g4x_cursor_wm_info,
4435 &plane_sr, &cursor_sr))
0e442c60 4436 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
417ae147
CW		 4437 else
4438 I915_WRITE(FW_BLC_SELF,
4439 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
0e442c60 4440
308977ac
CW		 4441 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4442 planea_wm, cursora_wm,
4443 planeb_wm, cursorb_wm,
4444 plane_sr, cursor_sr);
0e442c60 4445
417ae147
CW		 4446 I915_WRITE(DSPFW1,
4447 (plane_sr << DSPFW_SR_SHIFT) |
0e442c60 4448 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
417ae147
CW		 4449 (planeb_wm << DSPFW_PLANEB_SHIFT) |
4450 planea_wm);
4451 I915_WRITE(DSPFW2,
4452 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
0e442c60
JB		 4453 (cursora_wm << DSPFW_CURSORA_SHIFT));
4454 /* HPLL off in SR has some issues on G4x... disable it */
417ae147
CW		 4455 I915_WRITE(DSPFW3,
4456 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
0e442c60 4457 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
652c393a
JB		 4458}
4459
d210246a 4460static void i965_update_wm(struct drm_device *dev)
7662c8bd
SL		 4461{
4462 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4463 struct drm_crtc *crtc;
4464 int srwm = 1;
4fe5e611 4465 int cursor_sr = 16;
1dc7546d
JB		 4466
4467 /* Calc sr entries for one plane configs */
d210246a
CW		 4468 crtc = single_enabled_crtc(dev);
4469 if (crtc) {
1dc7546d 4470 /* self-refresh has much higher latency */
69e302a9 4471 static const int sr_latency_ns = 12000;
d210246a
CW		 4472 int clock = crtc->mode.clock;
4473 int htotal = crtc->mode.htotal;
4474 int hdisplay = crtc->mode.hdisplay;
4475 int pixel_size = crtc->fb->bits_per_pixel / 8;
4476 unsigned long line_time_us;
4477 int entries;
1dc7546d 4478
d210246a 4479 line_time_us = ((htotal * 1000) / clock);
1dc7546d
JB		 4480
4481 /* Use ns/us then divide to preserve precision */
d210246a
CW		 4482 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4483 pixel_size * hdisplay;
4484 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
d210246a 4485 srwm = I965_FIFO_SIZE - entries;
1dc7546d
JB		 4486 if (srwm < 0)
4487 srwm = 1;
1b07e04e 4488 srwm &= 0x1ff;
308977ac
CW		 4489 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4490 entries, srwm);
4fe5e611 4491
d210246a 4492 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
5eddb70b 4493 pixel_size * 64;
d210246a 4494 entries = DIV_ROUND_UP(entries,
8de9b311 4495 i965_cursor_wm_info.cacheline_size);
4fe5e611 4496 cursor_sr = i965_cursor_wm_info.fifo_size -
d210246a 4497 (entries + i965_cursor_wm_info.guard_size);
4fe5e611
ZY		 4498
4499 if (cursor_sr > i965_cursor_wm_info.max_wm)
4500 cursor_sr = i965_cursor_wm_info.max_wm;
4501
4502 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4503 "cursor %d\n", srwm, cursor_sr);
4504
a6c45cf0 4505 if (IS_CRESTLINE(dev))
adcdbc66 4506 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
33c5fd12
DJ		 4507 } else {
4508 /* Turn off self refresh if both pipes are enabled */
a6c45cf0 4509 if (IS_CRESTLINE(dev))
adcdbc66
JB		 4510 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4511 & ~FW_BLC_SELF_EN);
1dc7546d 4512 }
7662c8bd 4513
1dc7546d
JB		 4514 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4515 srwm);
7662c8bd
SL		 4516
4517 /* 965 has limitations... */
417ae147
CW		 4518 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4519 (8 << 16) | (8 << 8) | (8 << 0));
7662c8bd 4520 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4fe5e611
ZY		 4521 /* update cursor SR watermark */
4522 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
7662c8bd
SL		 4523}
4524
d210246a 4525static void i9xx_update_wm(struct drm_device *dev)
7662c8bd
SL		 4526{
4527 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 4528 const struct intel_watermark_params *wm_info;
dff33cfc
JB		 4529 uint32_t fwater_lo;
4530 uint32_t fwater_hi;
d210246a
CW		 4531 int cwm, srwm = 1;
4532 int fifo_size;
dff33cfc 4533 int planea_wm, planeb_wm;
d210246a 4534 struct drm_crtc *crtc, *enabled = NULL;
7662c8bd 4535
72557b4f 4536 if (IS_I945GM(dev))
d210246a 4537 wm_info = &i945_wm_info;
a6c45cf0 4538 else if (!IS_GEN2(dev))
d210246a 4539 wm_info = &i915_wm_info;
7662c8bd 4540 else
d210246a
CW		 4541 wm_info = &i855_wm_info;
4542
4543 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4544 crtc = intel_get_crtc_for_plane(dev, 0);
4545 if (crtc->enabled && crtc->fb) {
4546 planea_wm = intel_calculate_wm(crtc->mode.clock,
4547 wm_info, fifo_size,
4548 crtc->fb->bits_per_pixel / 8,
4549 latency_ns);
4550 enabled = crtc;
4551 } else
4552 planea_wm = fifo_size - wm_info->guard_size;
4553
4554 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4555 crtc = intel_get_crtc_for_plane(dev, 1);
4556 if (crtc->enabled && crtc->fb) {
4557 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4558 wm_info, fifo_size,
4559 crtc->fb->bits_per_pixel / 8,
4560 latency_ns);
4561 if (enabled == NULL)
4562 enabled = crtc;
4563 else
4564 enabled = NULL;
4565 } else
4566 planeb_wm = fifo_size - wm_info->guard_size;
7662c8bd 4567
28c97730 4568 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
7662c8bd
SL		 4569
4570 /*
4571 * Overlay gets an aggressive default since video jitter is bad.
4572 */
4573 cwm = 2;
4574
18b2190c
AL		 4575 /* Play safe and disable self-refresh before adjusting watermarks. */
4576 if (IS_I945G(dev) || IS_I945GM(dev))
4577 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4578 else if (IS_I915GM(dev))
4579 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4580
dff33cfc 4581 /* Calc sr entries for one plane configs */
d210246a 4582 if (HAS_FW_BLC(dev) && enabled) {
dff33cfc 4583 /* self-refresh has much higher latency */
69e302a9 4584 static const int sr_latency_ns = 6000;
d210246a
CW		 4585 int clock = enabled->mode.clock;
4586 int htotal = enabled->mode.htotal;
4587 int hdisplay = enabled->mode.hdisplay;
4588 int pixel_size = enabled->fb->bits_per_pixel / 8;
4589 unsigned long line_time_us;
4590 int entries;
dff33cfc 4591
d210246a 4592 line_time_us = (htotal * 1000) / clock;
dff33cfc
JB		 4593
4594 /* Use ns/us then divide to preserve precision */
d210246a
CW		 4595 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4596 pixel_size * hdisplay;
4597 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4598 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4599 srwm = wm_info->fifo_size - entries;
dff33cfc
JB		 4600 if (srwm < 0)
4601 srwm = 1;
ee980b80
LP		 4602
4603 if (IS_I945G(dev) || IS_I945GM(dev))
18b2190c
AL		 4604 I915_WRITE(FW_BLC_SELF,
4605 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4606 else if (IS_I915GM(dev))
ee980b80 4607 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
7662c8bd
SL		 4608 }
4609
28c97730 4610 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
5eddb70b 4611 planea_wm, planeb_wm, cwm, srwm);
7662c8bd 4612
dff33cfc
JB		 4613 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4614 fwater_hi = (cwm & 0x1f);
4615
4616 /* Set request length to 8 cachelines per fetch */
4617 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4618 fwater_hi = fwater_hi | (1 << 8);
7662c8bd
SL		 4619
4620 I915_WRITE(FW_BLC, fwater_lo);
4621 I915_WRITE(FW_BLC2, fwater_hi);
18b2190c 4622
d210246a
CW		 4623 if (HAS_FW_BLC(dev)) {
4624 if (enabled) {
4625 if (IS_I945G(dev) || IS_I945GM(dev))
4626 I915_WRITE(FW_BLC_SELF,
4627 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4628 else if (IS_I915GM(dev))
4629 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4630 DRM_DEBUG_KMS("memory self refresh enabled\n");
4631 } else
4632 DRM_DEBUG_KMS("memory self refresh disabled\n");
4633 }
7662c8bd
SL		 4634}
4635
d210246a 4636static void i830_update_wm(struct drm_device *dev)
7662c8bd
SL		 4637{
4638 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4639 struct drm_crtc *crtc;
4640 uint32_t fwater_lo;
dff33cfc 4641 int planea_wm;
7662c8bd 4642
d210246a
CW		 4643 crtc = single_enabled_crtc(dev);
4644 if (crtc == NULL)
4645 return;
7662c8bd 4646
d210246a
CW		 4647 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4648 dev_priv->display.get_fifo_size(dev, 0),
4649 crtc->fb->bits_per_pixel / 8,
4650 latency_ns);
4651 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
f3601326
JB		 4652 fwater_lo |= (3<<8) | planea_wm;
4653
28c97730 4654 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
7662c8bd
SL		 4655
4656 I915_WRITE(FW_BLC, fwater_lo);
4657}
4658
7f8a8569 4659#define ILK_LP0_PLANE_LATENCY 700
c936f44d 4660#define ILK_LP0_CURSOR_LATENCY 1300
7f8a8569 4661
1398261a
YL		 4662/*
4663 * Check the wm result.
4664 *
4665 * If any calculated watermark values is larger than the maximum value that
4666 * can be programmed into the associated watermark register, that watermark
4667 * must be disabled.
1398261a 4668 */
b79d4990
JB		 4669static bool ironlake_check_srwm(struct drm_device *dev, int level,
4670 int fbc_wm, int display_wm, int cursor_wm,
4671 const struct intel_watermark_params *display,
4672 const struct intel_watermark_params *cursor)
1398261a
YL		 4673{
4674 struct drm_i915_private *dev_priv = dev->dev_private;
4675
4676 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4677 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4678
4679 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4680 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4681 fbc_wm, SNB_FBC_MAX_SRWM, level);
1398261a
YL		 4682
4683 /* fbc has it's own way to disable FBC WM */
4684 I915_WRITE(DISP_ARB_CTL,
4685 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4686 return false;
4687 }
4688
b79d4990 4689 if (display_wm > display->max_wm) {
1398261a 4690 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4691 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1398261a
YL		 4692 return false;
4693 }
4694
b79d4990 4695 if (cursor_wm > cursor->max_wm) {
1398261a 4696 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4697 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1398261a
YL		 4698 return false;
4699 }
4700
4701 if (!(fbc_wm || display_wm || cursor_wm)) {
4702 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4703 return false;
4704 }
4705
4706 return true;
4707}
4708
4709/*
4710 * Compute watermark values of WM[1-3],
4711 */
d210246a
CW		 4712static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4713 int latency_ns,
b79d4990
JB		 4714 const struct intel_watermark_params *display,
4715 const struct intel_watermark_params *cursor,
4716 int *fbc_wm, int *display_wm, int *cursor_wm)
1398261a 4717{
d210246a 4718 struct drm_crtc *crtc;
1398261a 4719 unsigned long line_time_us;
d210246a 4720 int hdisplay, htotal, pixel_size, clock;
b79d4990 4721 int line_count, line_size;
1398261a
YL		 4722 int small, large;
4723 int entries;
1398261a
YL		 4724
4725 if (!latency_ns) {
4726 *fbc_wm = *display_wm = *cursor_wm = 0;
4727 return false;
4728 }
4729
d210246a
CW		 4730 crtc = intel_get_crtc_for_plane(dev, plane);
4731 hdisplay = crtc->mode.hdisplay;
4732 htotal = crtc->mode.htotal;
4733 clock = crtc->mode.clock;
4734 pixel_size = crtc->fb->bits_per_pixel / 8;
4735
1398261a
YL		 4736 line_time_us = (htotal * 1000) / clock;
4737 line_count = (latency_ns / line_time_us + 1000) / 1000;
4738 line_size = hdisplay * pixel_size;
4739
4740 /* Use the minimum of the small and large buffer method for primary */
4741 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4742 large = line_count * line_size;
4743
b79d4990
JB		 4744 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4745 *display_wm = entries + display->guard_size;
1398261a
YL		 4746
4747 /*
b79d4990 4748 * Spec says:
1398261a
YL		 4749 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4750 */
4751 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4752
4753 /* calculate the self-refresh watermark for display cursor */
4754 entries = line_count * pixel_size * 64;
b79d4990
JB		 4755 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4756 *cursor_wm = entries + cursor->guard_size;
1398261a 4757
b79d4990
JB		 4758 return ironlake_check_srwm(dev, level,
4759 *fbc_wm, *display_wm, *cursor_wm,
4760 display, cursor);
4761}
4762
d210246a 4763static void ironlake_update_wm(struct drm_device *dev)
b79d4990
JB		 4764{
4765 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4766 int fbc_wm, plane_wm, cursor_wm;
4767 unsigned int enabled;
b79d4990
JB		 4768
4769 enabled = 0;
9f405100
CW		 4770 if (g4x_compute_wm0(dev, 0,
4771 &ironlake_display_wm_info,
4772 ILK_LP0_PLANE_LATENCY,
4773 &ironlake_cursor_wm_info,
4774 ILK_LP0_CURSOR_LATENCY,
4775 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4776 I915_WRITE(WM0_PIPEA_ILK,
4777 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4778 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4779 " plane %d, " "cursor: %d\n",
4780 plane_wm, cursor_wm);
d210246a 4781 enabled |= 1;
b79d4990
JB		 4782 }
4783
9f405100
CW		 4784 if (g4x_compute_wm0(dev, 1,
4785 &ironlake_display_wm_info,
4786 ILK_LP0_PLANE_LATENCY,
4787 &ironlake_cursor_wm_info,
4788 ILK_LP0_CURSOR_LATENCY,
4789 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4790 I915_WRITE(WM0_PIPEB_ILK,
4791 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4792 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4793 " plane %d, cursor: %d\n",
4794 plane_wm, cursor_wm);
d210246a 4795 enabled |= 2;
b79d4990
JB		 4796 }
4797
4798 /*
4799 * Calculate and update the self-refresh watermark only when one
4800 * display plane is used.
4801 */
4802 I915_WRITE(WM3_LP_ILK, 0);
4803 I915_WRITE(WM2_LP_ILK, 0);
4804 I915_WRITE(WM1_LP_ILK, 0);
4805
d210246a 4806 if (!single_plane_enabled(enabled))
b79d4990 4807 return;
d210246a 4808 enabled = ffs(enabled) - 1;
b79d4990
JB		 4809
4810 /* WM1 */
d210246a
CW		 4811 if (!ironlake_compute_srwm(dev, 1, enabled,
4812 ILK_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4813 &ironlake_display_srwm_info,
4814 &ironlake_cursor_srwm_info,
4815 &fbc_wm, &plane_wm, &cursor_wm))
4816 return;
4817
4818 I915_WRITE(WM1_LP_ILK,
4819 WM1_LP_SR_EN |
4820 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4821 (fbc_wm << WM1_LP_FBC_SHIFT) |
4822 (plane_wm << WM1_LP_SR_SHIFT) |
4823 cursor_wm);
4824
4825 /* WM2 */
d210246a
CW		 4826 if (!ironlake_compute_srwm(dev, 2, enabled,
4827 ILK_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4828 &ironlake_display_srwm_info,
4829 &ironlake_cursor_srwm_info,
4830 &fbc_wm, &plane_wm, &cursor_wm))
4831 return;
4832
4833 I915_WRITE(WM2_LP_ILK,
4834 WM2_LP_EN |
4835 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4836 (fbc_wm << WM1_LP_FBC_SHIFT) |
4837 (plane_wm << WM1_LP_SR_SHIFT) |
4838 cursor_wm);
4839
4840 /*
4841 * WM3 is unsupported on ILK, probably because we don't have latency
4842 * data for that power state
4843 */
1398261a
YL		 4844}
4845
f681fa23 4846static void sandybridge_update_wm(struct drm_device *dev)
1398261a
YL		 4847{
4848 struct drm_i915_private *dev_priv = dev->dev_private;
a0fa62d3 4849 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
47842649 4850 u32 val;
d210246a
CW		 4851 int fbc_wm, plane_wm, cursor_wm;
4852 unsigned int enabled;
1398261a
YL		 4853
4854 enabled = 0;
9f405100
CW		 4855 if (g4x_compute_wm0(dev, 0,
4856 &sandybridge_display_wm_info, latency,
4857 &sandybridge_cursor_wm_info, latency,
4858 &plane_wm, &cursor_wm)) {
47842649
JB		 4859 val = I915_READ(WM0_PIPEA_ILK);
4860 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4861 I915_WRITE(WM0_PIPEA_ILK, val |
4862 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1398261a
YL		 4863 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4864 " plane %d, " "cursor: %d\n",
4865 plane_wm, cursor_wm);
d210246a 4866 enabled |= 1;
1398261a
YL		 4867 }
4868
9f405100
CW		 4869 if (g4x_compute_wm0(dev, 1,
4870 &sandybridge_display_wm_info, latency,
4871 &sandybridge_cursor_wm_info, latency,
4872 &plane_wm, &cursor_wm)) {
47842649
JB		 4873 val = I915_READ(WM0_PIPEB_ILK);
4874 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4875 I915_WRITE(WM0_PIPEB_ILK, val |
4876 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1398261a
YL		 4877 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4878 " plane %d, cursor: %d\n",
4879 plane_wm, cursor_wm);
d210246a 4880 enabled |= 2;
1398261a
YL		 4881 }
4882
d6c892df
JB		 4883 /* IVB has 3 pipes */
4884 if (IS_IVYBRIDGE(dev) &&
4885 g4x_compute_wm0(dev, 2,
4886 &sandybridge_display_wm_info, latency,
4887 &sandybridge_cursor_wm_info, latency,
4888 &plane_wm, &cursor_wm)) {
47842649
JB		 4889 val = I915_READ(WM0_PIPEC_IVB);
4890 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4891 I915_WRITE(WM0_PIPEC_IVB, val |
4892 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
d6c892df
JB		 4893 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4894 " plane %d, cursor: %d\n",
4895 plane_wm, cursor_wm);
4896 enabled |= 3;
4897 }
4898
1398261a
YL		 4899 /*
4900 * Calculate and update the self-refresh watermark only when one
4901 * display plane is used.
4902 *
4903 * SNB support 3 levels of watermark.
4904 *
4905 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4906 * and disabled in the descending order
4907 *
4908 */
4909 I915_WRITE(WM3_LP_ILK, 0);
4910 I915_WRITE(WM2_LP_ILK, 0);
4911 I915_WRITE(WM1_LP_ILK, 0);
4912
b840d907
JB		 4913 if (!single_plane_enabled(enabled) ||
4914 dev_priv->sprite_scaling_enabled)
1398261a 4915 return;
d210246a 4916 enabled = ffs(enabled) - 1;
1398261a
YL		 4917
4918 /* WM1 */
d210246a
CW		 4919 if (!ironlake_compute_srwm(dev, 1, enabled,
4920 SNB_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4921 &sandybridge_display_srwm_info,
4922 &sandybridge_cursor_srwm_info,
4923 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4924 return;
4925
4926 I915_WRITE(WM1_LP_ILK,
4927 WM1_LP_SR_EN |
4928 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4929 (fbc_wm << WM1_LP_FBC_SHIFT) |
4930 (plane_wm << WM1_LP_SR_SHIFT) |
4931 cursor_wm);
4932
4933 /* WM2 */
d210246a
CW		 4934 if (!ironlake_compute_srwm(dev, 2, enabled,
4935 SNB_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4936 &sandybridge_display_srwm_info,
4937 &sandybridge_cursor_srwm_info,
4938 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4939 return;
4940
4941 I915_WRITE(WM2_LP_ILK,
4942 WM2_LP_EN |
4943 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4944 (fbc_wm << WM1_LP_FBC_SHIFT) |
4945 (plane_wm << WM1_LP_SR_SHIFT) |
4946 cursor_wm);
4947
4948 /* WM3 */
d210246a
CW		 4949 if (!ironlake_compute_srwm(dev, 3, enabled,
4950 SNB_READ_WM3_LATENCY() * 500,
b79d4990
JB		 4951 &sandybridge_display_srwm_info,
4952 &sandybridge_cursor_srwm_info,
4953 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4954 return;
4955
4956 I915_WRITE(WM3_LP_ILK,
4957 WM3_LP_EN |
4958 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4959 (fbc_wm << WM1_LP_FBC_SHIFT) |
4960 (plane_wm << WM1_LP_SR_SHIFT) |
4961 cursor_wm);
4962}
4963
b840d907
JB		 4964static bool
4965sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
4966 uint32_t sprite_width, int pixel_size,
4967 const struct intel_watermark_params *display,
4968 int display_latency_ns, int *sprite_wm)
4969{
4970 struct drm_crtc *crtc;
4971 int clock;
4972 int entries, tlb_miss;
4973
4974 crtc = intel_get_crtc_for_plane(dev, plane);
4975 if (crtc->fb == NULL || !crtc->enabled) {
4976 *sprite_wm = display->guard_size;
4977 return false;
4978 }
4979
4980 clock = crtc->mode.clock;
4981
4982 /* Use the small buffer method to calculate the sprite watermark */
4983 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4984 tlb_miss = display->fifo_size*display->cacheline_size -
4985 sprite_width * 8;
4986 if (tlb_miss > 0)
4987 entries += tlb_miss;
4988 entries = DIV_ROUND_UP(entries, display->cacheline_size);
4989 *sprite_wm = entries + display->guard_size;
4990 if (*sprite_wm > (int)display->max_wm)
4991 *sprite_wm = display->max_wm;
4992
4993 return true;
4994}
4995
4996static bool
4997sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
4998 uint32_t sprite_width, int pixel_size,
4999 const struct intel_watermark_params *display,
5000 int latency_ns, int *sprite_wm)
5001{
5002 struct drm_crtc *crtc;
5003 unsigned long line_time_us;
5004 int clock;
5005 int line_count, line_size;
5006 int small, large;
5007 int entries;
5008
5009 if (!latency_ns) {
5010 *sprite_wm = 0;
5011 return false;
5012 }
5013
5014 crtc = intel_get_crtc_for_plane(dev, plane);
5015 clock = crtc->mode.clock;
4e9bb47b
HL		 5016 if (!clock) {
5017 *sprite_wm = 0;
5018 return false;
5019 }
b840d907
JB		 5020
5021 line_time_us = (sprite_width * 1000) / clock;
4e9bb47b
HL		 5022 if (!line_time_us) {
5023 *sprite_wm = 0;
5024 return false;
5025 }
5026
b840d907
JB		 5027 line_count = (latency_ns / line_time_us + 1000) / 1000;
5028 line_size = sprite_width * pixel_size;
5029
5030 /* Use the minimum of the small and large buffer method for primary */
5031 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
5032 large = line_count * line_size;
5033
5034 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
5035 *sprite_wm = entries + display->guard_size;
5036
5037 return *sprite_wm > 0x3ff ? false : true;
5038}
5039
5040static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
5041 uint32_t sprite_width, int pixel_size)
5042{
5043 struct drm_i915_private *dev_priv = dev->dev_private;
5044 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
47842649 5045 u32 val;
b840d907
JB		 5046 int sprite_wm, reg;
5047 int ret;
5048
5049 switch (pipe) {
5050 case 0:
5051 reg = WM0_PIPEA_ILK;
5052 break;
5053 case 1:
5054 reg = WM0_PIPEB_ILK;
5055 break;
5056 case 2:
5057 reg = WM0_PIPEC_IVB;
5058 break;
5059 default:
5060 return; /* bad pipe */
5061 }
5062
5063 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
5064 &sandybridge_display_wm_info,
5065 latency, &sprite_wm);
5066 if (!ret) {
5067 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
5068 pipe);
5069 return;
5070 }
5071
47842649
JB		 5072 val = I915_READ(reg);
5073 val &= ~WM0_PIPE_SPRITE_MASK;
5074 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
b840d907
JB		 5075 DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
5076
5077
5078 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
5079 pixel_size,
5080 &sandybridge_display_srwm_info,
5081 SNB_READ_WM1_LATENCY() * 500,
5082 &sprite_wm);
5083 if (!ret) {
5084 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
5085 pipe);
5086 return;
5087 }
5088 I915_WRITE(WM1S_LP_ILK, sprite_wm);
5089
5090 /* Only IVB has two more LP watermarks for sprite */
5091 if (!IS_IVYBRIDGE(dev))
5092 return;
5093
5094 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
5095 pixel_size,
5096 &sandybridge_display_srwm_info,
5097 SNB_READ_WM2_LATENCY() * 500,
5098 &sprite_wm);
5099 if (!ret) {
5100 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
5101 pipe);
5102 return;
5103 }
5104 I915_WRITE(WM2S_LP_IVB, sprite_wm);
5105
5106 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
5107 pixel_size,
5108 &sandybridge_display_srwm_info,
5109 SNB_READ_WM3_LATENCY() * 500,
5110 &sprite_wm);
5111 if (!ret) {
5112 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
5113 pipe);
5114 return;
5115 }
5116 I915_WRITE(WM3S_LP_IVB, sprite_wm);
5117}
5118
7662c8bd
SL		 5119/**
5120 * intel_update_watermarks - update FIFO watermark values based on current modes
5121 *
5122 * Calculate watermark values for the various WM regs based on current mode
5123 * and plane configuration.
5124 *
5125 * There are several cases to deal with here:
5126 * - normal (i.e. non-self-refresh)
5127 * - self-refresh (SR) mode
5128 * - lines are large relative to FIFO size (buffer can hold up to 2)
5129 * - lines are small relative to FIFO size (buffer can hold more than 2
5130 * lines), so need to account for TLB latency
5131 *
5132 * The normal calculation is:
5133 * watermark = dotclock * bytes per pixel * latency
5134 * where latency is platform & configuration dependent (we assume pessimal
5135 * values here).
5136 *
5137 * The SR calculation is:
5138 * watermark = (trunc(latency/line time)+1) * surface width *
5139 * bytes per pixel
5140 * where
5141 * line time = htotal / dotclock
fa143215 5142 * surface width = hdisplay for normal plane and 64 for cursor
7662c8bd
SL		 5143 * and latency is assumed to be high, as above.
5144 *
5145 * The final value programmed to the register should always be rounded up,
5146 * and include an extra 2 entries to account for clock crossings.
5147 *
5148 * We don't use the sprite, so we can ignore that. And on Crestline we have
5149 * to set the non-SR watermarks to 8.
5eddb70b 5150 */
f681fa23 5151void intel_update_watermarks(struct drm_device *dev)
7662c8bd 5152{
e70236a8 5153 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd 5154
d210246a
CW		 5155 if (dev_priv->display.update_wm)
5156 dev_priv->display.update_wm(dev);
7662c8bd
SL		 5157}
5158
b840d907
JB		 5159void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
5160 uint32_t sprite_width, int pixel_size)
5161{
5162 struct drm_i915_private *dev_priv = dev->dev_private;
5163
5164 if (dev_priv->display.update_sprite_wm)
5165 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
5166 pixel_size);
5167}
5168
a7615030
CW		 5169static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5170{
72bbe58c
KP		 5171 if (i915_panel_use_ssc >= 0)
5172 return i915_panel_use_ssc != 0;
5173 return dev_priv->lvds_use_ssc
435793df 5174 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 5175}
5176
5a354204
JB		 5177/**
5178 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
5179 * @crtc: CRTC structure
3b5c78a3 5180 * @mode: requested mode
5a354204
JB		 5181 *
5182 * A pipe may be connected to one or more outputs. Based on the depth of the
5183 * attached framebuffer, choose a good color depth to use on the pipe.
5184 *
5185 * If possible, match the pipe depth to the fb depth. In some cases, this
5186 * isn't ideal, because the connected output supports a lesser or restricted
5187 * set of depths. Resolve that here:
5188 * LVDS typically supports only 6bpc, so clamp down in that case
5189 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
5190 * Displays may support a restricted set as well, check EDID and clamp as
5191 * appropriate.
3b5c78a3 5192 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 5193 *
5194 * RETURNS:
5195 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
5196 * true if they don't match).
5197 */
5198static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3b5c78a3
AJ		 5199 unsigned int *pipe_bpp,
5200 struct drm_display_mode *mode)
5a354204
JB		 5201{
5202 struct drm_device *dev = crtc->dev;
5203 struct drm_i915_private *dev_priv = dev->dev_private;
5204 struct drm_encoder *encoder;
5205 struct drm_connector *connector;
5206 unsigned int display_bpc = UINT_MAX, bpc;
5207
5208 /* Walk the encoders & connectors on this crtc, get min bpc */
5209 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5210 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5211
5212 if (encoder->crtc != crtc)
5213 continue;
5214
5215 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
5216 unsigned int lvds_bpc;
5217
5218 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
5219 LVDS_A3_POWER_UP)
5220 lvds_bpc = 8;
5221 else
5222 lvds_bpc = 6;
5223
5224 if (lvds_bpc < display_bpc) {
82820490 5225 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 5226 display_bpc = lvds_bpc;
5227 }
5228 continue;
5229 }
5230
5231 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
5232 /* Use VBT settings if we have an eDP panel */
5233 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
5234
5235 if (edp_bpc < display_bpc) {
82820490 5236 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
5a354204
JB		 5237 display_bpc = edp_bpc;
5238 }
5239 continue;
5240 }
5241
5242 /* Not one of the known troublemakers, check the EDID */
5243 list_for_each_entry(connector, &dev->mode_config.connector_list,
5244 head) {
5245 if (connector->encoder != encoder)
5246 continue;
5247
62ac41a6
JB		 5248 /* Don't use an invalid EDID bpc value */
5249 if (connector->display_info.bpc &&
5250 connector->display_info.bpc < display_bpc) {
82820490 5251 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 5252 display_bpc = connector->display_info.bpc;
5253 }
5254 }
5255
5256 /*
5257 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
5258 * through, clamp it down. (Note: >12bpc will be caught below.)
5259 */
5260 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
5261 if (display_bpc > 8 && display_bpc < 12) {
82820490 5262 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 5263 display_bpc = 12;
5264 } else {
82820490 5265 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 5266 display_bpc = 8;
5267 }
5268 }
5269 }
5270
3b5c78a3
AJ		 5271 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5272 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
5273 display_bpc = 6;
5274 }
5275
5a354204
JB		 5276 /*
5277 * We could just drive the pipe at the highest bpc all the time and
5278 * enable dithering as needed, but that costs bandwidth. So choose
5279 * the minimum value that expresses the full color range of the fb but
5280 * also stays within the max display bpc discovered above.
5281 */
5282
5283 switch (crtc->fb->depth) {
5284 case 8:
5285 bpc = 8; /* since we go through a colormap */
5286 break;
5287 case 15:
5288 case 16:
5289 bpc = 6; /* min is 18bpp */
5290 break;
5291 case 24:
578393cd 5292 bpc = 8;
5a354204
JB		 5293 break;
5294 case 30:
578393cd 5295 bpc = 10;
5a354204
JB		 5296 break;
5297 case 48:
578393cd 5298 bpc = 12;
5a354204
JB		 5299 break;
5300 default:
5301 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
5302 bpc = min((unsigned int)8, display_bpc);
5303 break;
5304 }
5305
578393cd
KP		 5306 display_bpc = min(display_bpc, bpc);
5307
82820490
AJ		 5308 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
5309 bpc, display_bpc);
5a354204 5310
578393cd 5311 *pipe_bpp = display_bpc * 3;
5a354204
JB		 5312
5313 return display_bpc != bpc;
5314}
5315
c65d77d8
JB		 5316static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5317{
5318 struct drm_device *dev = crtc->dev;
5319 struct drm_i915_private *dev_priv = dev->dev_private;
5320 int refclk;
5321
5322 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5323 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5324 refclk = dev_priv->lvds_ssc_freq * 1000;
5325 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5326 refclk / 1000);
5327 } else if (!IS_GEN2(dev)) {
5328 refclk = 96000;
5329 } else {
5330 refclk = 48000;
5331 }
5332
5333 return refclk;
5334}
5335
5336static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
5337 intel_clock_t *clock)
5338{
5339 /* SDVO TV has fixed PLL values depend on its clock range,
5340 this mirrors vbios setting. */
5341 if (adjusted_mode->clock >= 100000
5342 && adjusted_mode->clock < 140500) {
5343 clock->p1 = 2;
5344 clock->p2 = 10;
5345 clock->n = 3;
5346 clock->m1 = 16;
5347 clock->m2 = 8;
5348 } else if (adjusted_mode->clock >= 140500
5349 && adjusted_mode->clock <= 200000) {
5350 clock->p1 = 1;
5351 clock->p2 = 10;
5352 clock->n = 6;
5353 clock->m1 = 12;
5354 clock->m2 = 8;
5355 }
5356}
5357
a7516a05
JB		 5358static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
5359 intel_clock_t *clock,
5360 intel_clock_t *reduced_clock)
5361{
5362 struct drm_device *dev = crtc->dev;
5363 struct drm_i915_private *dev_priv = dev->dev_private;
5364 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5365 int pipe = intel_crtc->pipe;
5366 u32 fp, fp2 = 0;
5367
5368 if (IS_PINEVIEW(dev)) {
5369 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
5370 if (reduced_clock)
5371 fp2 = (1 << reduced_clock->n) << 16 |
5372 reduced_clock->m1 << 8 | reduced_clock->m2;
5373 } else {
5374 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
5375 if (reduced_clock)
5376 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
5377 reduced_clock->m2;
5378 }
5379
5380 I915_WRITE(FP0(pipe), fp);
5381
5382 intel_crtc->lowfreq_avail = false;
5383 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5384 reduced_clock && i915_powersave) {
5385 I915_WRITE(FP1(pipe), fp2);
5386 intel_crtc->lowfreq_avail = true;
5387 } else {
5388 I915_WRITE(FP1(pipe), fp);
5389 }
5390}
5391
93e537a1
DV		 5392static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
5393 struct drm_display_mode *adjusted_mode)
5394{
5395 struct drm_device *dev = crtc->dev;
5396 struct drm_i915_private *dev_priv = dev->dev_private;
5397 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5398 int pipe = intel_crtc->pipe;
5399 u32 temp, lvds_sync = 0;
5400
5401 temp = I915_READ(LVDS);
5402 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5403 if (pipe == 1) {
5404 temp |= LVDS_PIPEB_SELECT;
5405 } else {
5406 temp &= ~LVDS_PIPEB_SELECT;
5407 }
5408 /* set the corresponsding LVDS_BORDER bit */
5409 temp |= dev_priv->lvds_border_bits;
5410 /* Set the B0-B3 data pairs corresponding to whether we're going to
5411 * set the DPLLs for dual-channel mode or not.
5412 */
5413 if (clock->p2 == 7)
5414 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5415 else
5416 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5417
5418 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5419 * appropriately here, but we need to look more thoroughly into how
5420 * panels behave in the two modes.
5421 */
5422 /* set the dithering flag on LVDS as needed */
5423 if (INTEL_INFO(dev)->gen >= 4) {
5424 if (dev_priv->lvds_dither)
5425 temp |= LVDS_ENABLE_DITHER;
5426 else
5427 temp &= ~LVDS_ENABLE_DITHER;
5428 }
5429 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5430 lvds_sync |= LVDS_HSYNC_POLARITY;
5431 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5432 lvds_sync |= LVDS_VSYNC_POLARITY;
5433 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5434 != lvds_sync) {
5435 char flags[2] = "-+";
5436 DRM_INFO("Changing LVDS panel from "
5437 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5438 flags[!(temp & LVDS_HSYNC_POLARITY)],
5439 flags[!(temp & LVDS_VSYNC_POLARITY)],
5440 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5441 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5442 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5443 temp |= lvds_sync;
5444 }
5445 I915_WRITE(LVDS, temp);
5446}
5447
eb1cbe48
DV		 5448static void i9xx_update_pll(struct drm_crtc *crtc,
5449 struct drm_display_mode *mode,
5450 struct drm_display_mode *adjusted_mode,
5451 intel_clock_t *clock, intel_clock_t *reduced_clock,
5452 int num_connectors)
5453{
5454 struct drm_device *dev = crtc->dev;
5455 struct drm_i915_private *dev_priv = dev->dev_private;
5456 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5457 int pipe = intel_crtc->pipe;
5458 u32 dpll;
5459 bool is_sdvo;
5460
5461 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
5462 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
5463
5464 dpll = DPLL_VGA_MODE_DIS;
5465
5466 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
5467 dpll |= DPLLB_MODE_LVDS;
5468 else
5469 dpll |= DPLLB_MODE_DAC_SERIAL;
5470 if (is_sdvo) {
5471 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5472 if (pixel_multiplier > 1) {
5473 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5474 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
5475 }
5476 dpll |= DPLL_DVO_HIGH_SPEED;
5477 }
5478 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
5479 dpll |= DPLL_DVO_HIGH_SPEED;
5480
5481 /* compute bitmask from p1 value */
5482 if (IS_PINEVIEW(dev))
5483 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5484 else {
5485 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5486 if (IS_G4X(dev) && reduced_clock)
5487 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5488 }
5489 switch (clock->p2) {
5490 case 5:
5491 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5492 break;
5493 case 7:
5494 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5495 break;
5496 case 10:
5497 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5498 break;
5499 case 14:
5500 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5501 break;
5502 }
5503 if (INTEL_INFO(dev)->gen >= 4)
5504 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5505
5506 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
5507 dpll |= PLL_REF_INPUT_TVCLKINBC;
5508 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
5509 /* XXX: just matching BIOS for now */
5510 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5511 dpll |= 3;
5512 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5513 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5514 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5515 else
5516 dpll |= PLL_REF_INPUT_DREFCLK;
5517
5518 dpll |= DPLL_VCO_ENABLE;
5519 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5520 POSTING_READ(DPLL(pipe));
5521 udelay(150);
5522
5523 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5524 * This is an exception to the general rule that mode_set doesn't turn
5525 * things on.
5526 */
5527 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
5528 intel_update_lvds(crtc, clock, adjusted_mode);
5529
5530 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
5531 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5532
5533 I915_WRITE(DPLL(pipe), dpll);
5534
5535 /* Wait for the clocks to stabilize. */
5536 POSTING_READ(DPLL(pipe));
5537 udelay(150);
5538
5539 if (INTEL_INFO(dev)->gen >= 4) {
5540 u32 temp = 0;
5541 if (is_sdvo) {
5542 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5543 if (temp > 1)
5544 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5545 else
5546 temp = 0;
5547 }
5548 I915_WRITE(DPLL_MD(pipe), temp);
5549 } else {
5550 /* The pixel multiplier can only be updated once the
5551 * DPLL is enabled and the clocks are stable.
5552 *
5553 * So write it again.
5554 */
5555 I915_WRITE(DPLL(pipe), dpll);
5556 }
5557}
5558
5559static void i8xx_update_pll(struct drm_crtc *crtc,
5560 struct drm_display_mode *adjusted_mode,
5561 intel_clock_t *clock,
5562 int num_connectors)
5563{
5564 struct drm_device *dev = crtc->dev;
5565 struct drm_i915_private *dev_priv = dev->dev_private;
5566 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5567 int pipe = intel_crtc->pipe;
5568 u32 dpll;
5569
5570 dpll = DPLL_VGA_MODE_DIS;
5571
5572 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
5573 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5574 } else {
5575 if (clock->p1 == 2)
5576 dpll |= PLL_P1_DIVIDE_BY_TWO;
5577 else
5578 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5579 if (clock->p2 == 4)
5580 dpll |= PLL_P2_DIVIDE_BY_4;
5581 }
5582
5583 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
5584 /* XXX: just matching BIOS for now */
5585 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5586 dpll |= 3;
5587 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5588 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5589 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5590 else
5591 dpll |= PLL_REF_INPUT_DREFCLK;
5592
5593 dpll |= DPLL_VCO_ENABLE;
5594 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5595 POSTING_READ(DPLL(pipe));
5596 udelay(150);
5597
5598 I915_WRITE(DPLL(pipe), dpll);
5599
5600 /* Wait for the clocks to stabilize. */
5601 POSTING_READ(DPLL(pipe));
5602 udelay(150);
5603
5604 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5605 * This is an exception to the general rule that mode_set doesn't turn
5606 * things on.
5607 */
5608 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
5609 intel_update_lvds(crtc, clock, adjusted_mode);
5610
5611 /* The pixel multiplier can only be updated once the
5612 * DPLL is enabled and the clocks are stable.
5613 *
5614 * So write it again.
5615 */
5616 I915_WRITE(DPLL(pipe), dpll);
5617}
5618
f564048e
EA		 5619static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5620 struct drm_display_mode *mode,
5621 struct drm_display_mode *adjusted_mode,
5622 int x, int y,
5623 struct drm_framebuffer *old_fb)
79e53945
JB		 5624{
5625 struct drm_device *dev = crtc->dev;
5626 struct drm_i915_private *dev_priv = dev->dev_private;
5627 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5628 int pipe = intel_crtc->pipe;
80824003 5629 int plane = intel_crtc->plane;
c751ce4f 5630 int refclk, num_connectors = 0;
652c393a 5631 intel_clock_t clock, reduced_clock;
eb1cbe48
DV		 5632 u32 dspcntr, pipeconf, vsyncshift;
5633 bool ok, has_reduced_clock = false, is_sdvo = false;
5634 bool is_lvds = false, is_tv = false, is_dp = false;
79e53945 5635 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 5636 struct intel_encoder *encoder;
d4906093 5637 const intel_limit_t *limit;
5c3b82e2 5638 int ret;
79e53945 5639
5eddb70b
CW		 5640 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5641 if (encoder->base.crtc != crtc)
79e53945
JB		 5642 continue;
5643
5eddb70b 5644 switch (encoder->type) {
79e53945
JB		 5645 case INTEL_OUTPUT_LVDS:
5646 is_lvds = true;
5647 break;
5648 case INTEL_OUTPUT_SDVO:
7d57382e 5649 case INTEL_OUTPUT_HDMI:
79e53945 5650 is_sdvo = true;
5eddb70b 5651 if (encoder->needs_tv_clock)
e2f0ba97 5652 is_tv = true;
79e53945 5653 break;
79e53945
JB		 5654 case INTEL_OUTPUT_TVOUT:
5655 is_tv = true;
5656 break;
a4fc5ed6
KP		 5657 case INTEL_OUTPUT_DISPLAYPORT:
5658 is_dp = true;
5659 break;
79e53945 5660 }
43565a06 5661
c751ce4f 5662 num_connectors++;
79e53945
JB		 5663 }
5664
c65d77d8 5665 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 5666
d4906093
ML		 5667 /*
5668 * Returns a set of divisors for the desired target clock with the given
5669 * refclk, or FALSE. The returned values represent the clock equation:
5670 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5671 */
1b894b59 5672 limit = intel_limit(crtc, refclk);
cec2f356
SP		 5673 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5674 &clock);
79e53945
JB		 5675 if (!ok) {
5676 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 5677 return -EINVAL;
79e53945
JB		 5678 }
5679
cda4b7d3 5680 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 5681 intel_crtc_update_cursor(crtc, true);
cda4b7d3 5682
ddc9003c 5683 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5684 /*
5685 * Ensure we match the reduced clock's P to the target clock.
5686 * If the clocks don't match, we can't switch the display clock
5687 * by using the FP0/FP1. In such case we will disable the LVDS
5688 * downclock feature.
5689 */
ddc9003c 5690 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 5691 dev_priv->lvds_downclock,
5692 refclk,
cec2f356 5693 &clock,
5eddb70b 5694 &reduced_clock);
7026d4ac
ZW		 5695 }
5696
c65d77d8
JB		 5697 if (is_sdvo && is_tv)
5698 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 5699
a7516a05
JB		 5700 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
5701 &reduced_clock : NULL);
79e53945 5702
eb1cbe48
DV		 5703 if (IS_GEN2(dev))
5704 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
79e53945 5705 else
eb1cbe48
DV		 5706 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
5707 has_reduced_clock ? &reduced_clock : NULL,
5708 num_connectors);
79e53945
JB		 5709
5710 /* setup pipeconf */
5eddb70b 5711 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 5712
5713 /* Set up the display plane register */
5714 dspcntr = DISPPLANE_GAMMA_ENABLE;
5715
929c77fb
EA		 5716 if (pipe == 0)
5717 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5718 else
5719 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 5720
a6c45cf0 5721 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 5722 /* Enable pixel doubling when the dot clock is > 90% of the (display)
5723 * core speed.
5724 *
5725 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5726 * pipe == 0 check?
5727 */
e70236a8
JB		 5728 if (mode->clock >
5729 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 5730 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 5731 else
5eddb70b 5732 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 5733 }
5734
3b5c78a3
AJ		 5735 /* default to 8bpc */
5736 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
5737 if (is_dp) {
5738 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5739 pipeconf |= PIPECONF_BPP_6 |
5740 PIPECONF_DITHER_EN |
5741 PIPECONF_DITHER_TYPE_SP;
5742 }
5743 }
5744
28c97730 5745 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 5746 drm_mode_debug_printmodeline(mode);
5747
a7516a05
JB		 5748 if (HAS_PIPE_CXSR(dev)) {
5749 if (intel_crtc->lowfreq_avail) {
28c97730 5750 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 5751 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 5752 } else {
28c97730 5753 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 5754 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5755 }
5756 }
5757
617cf884 5758 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575
DV		 5759 if (!IS_GEN2(dev) &&
5760 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
734b4157
KH		 5761 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5762 /* the chip adds 2 halflines automatically */
734b4157 5763 adjusted_mode->crtc_vtotal -= 1;
734b4157 5764 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 5765 vsyncshift = adjusted_mode->crtc_hsync_start
5766 - adjusted_mode->crtc_htotal/2;
5767 } else {
617cf884 5768 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 5769 vsyncshift = 0;
5770 }
5771
5772 if (!IS_GEN3(dev))
5773 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
734b4157 5774
5eddb70b
CW		 5775 I915_WRITE(HTOTAL(pipe),
5776 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 5777 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 5778 I915_WRITE(HBLANK(pipe),
5779 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 5780 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 5781 I915_WRITE(HSYNC(pipe),
5782 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 5783 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 5784
5785 I915_WRITE(VTOTAL(pipe),
5786 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 5787 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 5788 I915_WRITE(VBLANK(pipe),
5789 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 5790 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 5791 I915_WRITE(VSYNC(pipe),
5792 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 5793 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b
CW		 5794
5795 /* pipesrc and dspsize control the size that is scaled from,
5796 * which should always be the user's requested size.
79e53945 5797 */
929c77fb
EA		 5798 I915_WRITE(DSPSIZE(plane),
5799 ((mode->vdisplay - 1) << 16) |
5800 (mode->hdisplay - 1));
5801 I915_WRITE(DSPPOS(plane), 0);
5eddb70b
CW		 5802 I915_WRITE(PIPESRC(pipe),
5803 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 5804
f564048e
EA		 5805 I915_WRITE(PIPECONF(pipe), pipeconf);
5806 POSTING_READ(PIPECONF(pipe));
929c77fb 5807 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 5808
5809 intel_wait_for_vblank(dev, pipe);
5810
f564048e
EA		 5811 I915_WRITE(DSPCNTR(plane), dspcntr);
5812 POSTING_READ(DSPCNTR(plane));
284d9529 5813 intel_enable_plane(dev_priv, plane, pipe);
f564048e
EA		 5814
5815 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5816
5817 intel_update_watermarks(dev);
5818
f564048e
EA		 5819 return ret;
5820}
5821
9fb526db
KP		 5822/*
5823 * Initialize reference clocks when the driver loads
5824 */
5825void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5826{
5827 struct drm_i915_private *dev_priv = dev->dev_private;
5828 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5829 struct intel_encoder *encoder;
13d83a67
JB		 5830 u32 temp;
5831 bool has_lvds = false;
199e5d79
KP		 5832 bool has_cpu_edp = false;
5833 bool has_pch_edp = false;
5834 bool has_panel = false;
99eb6a01
KP		 5835 bool has_ck505 = false;
5836 bool can_ssc = false;
13d83a67
JB		 5837
5838 /* We need to take the global config into account */
199e5d79
KP		 5839 list_for_each_entry(encoder, &mode_config->encoder_list,
5840 base.head) {
5841 switch (encoder->type) {
5842 case INTEL_OUTPUT_LVDS:
5843 has_panel = true;
5844 has_lvds = true;
5845 break;
5846 case INTEL_OUTPUT_EDP:
5847 has_panel = true;
5848 if (intel_encoder_is_pch_edp(&encoder->base))
5849 has_pch_edp = true;
5850 else
5851 has_cpu_edp = true;
5852 break;
13d83a67
JB		 5853 }
5854 }
5855
99eb6a01
KP		 5856 if (HAS_PCH_IBX(dev)) {
5857 has_ck505 = dev_priv->display_clock_mode;
5858 can_ssc = has_ck505;
5859 } else {
5860 has_ck505 = false;
5861 can_ssc = true;
5862 }
5863
5864 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5865 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5866 has_ck505);
13d83a67
JB		 5867
5868 /* Ironlake: try to setup display ref clock before DPLL
5869 * enabling. This is only under driver's control after
5870 * PCH B stepping, previous chipset stepping should be
5871 * ignoring this setting.
5872 */
5873 temp = I915_READ(PCH_DREF_CONTROL);
5874 /* Always enable nonspread source */
5875 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5876
99eb6a01
KP		 5877 if (has_ck505)
5878 temp |= DREF_NONSPREAD_CK505_ENABLE;
5879 else
5880 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5881
199e5d79
KP		 5882 if (has_panel) {
5883 temp &= ~DREF_SSC_SOURCE_MASK;
5884 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5885
199e5d79 5886 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5887 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5888 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 5889 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 5890 } else
5891 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5892
5893 /* Get SSC going before enabling the outputs */
5894 I915_WRITE(PCH_DREF_CONTROL, temp);
5895 POSTING_READ(PCH_DREF_CONTROL);
5896 udelay(200);
5897
13d83a67
JB		 5898 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5899
5900 /* Enable CPU source on CPU attached eDP */
199e5d79 5901 if (has_cpu_edp) {
99eb6a01 5902 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5903 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 5904 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5905 }
13d83a67
JB		 5906 else
5907 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 5908 } else
5909 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5910
5911 I915_WRITE(PCH_DREF_CONTROL, temp);
5912 POSTING_READ(PCH_DREF_CONTROL);
5913 udelay(200);
5914 } else {
5915 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5916
5917 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5918
5919 /* Turn off CPU output */
5920 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5921
5922 I915_WRITE(PCH_DREF_CONTROL, temp);
5923 POSTING_READ(PCH_DREF_CONTROL);
5924 udelay(200);
5925
5926 /* Turn off the SSC source */
5927 temp &= ~DREF_SSC_SOURCE_MASK;
5928 temp |= DREF_SSC_SOURCE_DISABLE;
5929
5930 /* Turn off SSC1 */
5931 temp &= ~ DREF_SSC1_ENABLE;
5932
13d83a67
JB		 5933 I915_WRITE(PCH_DREF_CONTROL, temp);
5934 POSTING_READ(PCH_DREF_CONTROL);
5935 udelay(200);
5936 }
5937}
5938
d9d444cb
JB		 5939static int ironlake_get_refclk(struct drm_crtc *crtc)
5940{
5941 struct drm_device *dev = crtc->dev;
5942 struct drm_i915_private *dev_priv = dev->dev_private;
5943 struct intel_encoder *encoder;
5944 struct drm_mode_config *mode_config = &dev->mode_config;
5945 struct intel_encoder *edp_encoder = NULL;
5946 int num_connectors = 0;
5947 bool is_lvds = false;
5948
5949 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5950 if (encoder->base.crtc != crtc)
5951 continue;
5952
5953 switch (encoder->type) {
5954 case INTEL_OUTPUT_LVDS:
5955 is_lvds = true;
5956 break;
5957 case INTEL_OUTPUT_EDP:
5958 edp_encoder = encoder;
5959 break;
5960 }
5961 num_connectors++;
5962 }
5963
5964 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5965 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5966 dev_priv->lvds_ssc_freq);
5967 return dev_priv->lvds_ssc_freq * 1000;
5968 }
5969
5970 return 120000;
5971}
5972
f564048e
EA		 5973static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5974 struct drm_display_mode *mode,
5975 struct drm_display_mode *adjusted_mode,
5976 int x, int y,
5977 struct drm_framebuffer *old_fb)
79e53945
JB		 5978{
5979 struct drm_device *dev = crtc->dev;
5980 struct drm_i915_private *dev_priv = dev->dev_private;
5981 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5982 int pipe = intel_crtc->pipe;
80824003 5983 int plane = intel_crtc->plane;
c751ce4f 5984 int refclk, num_connectors = 0;
652c393a 5985 intel_clock_t clock, reduced_clock;
5eddb70b 5986 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
a07d6787 5987 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 5988 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
79e53945 5989 struct drm_mode_config *mode_config = &dev->mode_config;
e3aef172 5990 struct intel_encoder *encoder, *edp_encoder = NULL;
d4906093 5991 const intel_limit_t *limit;
5c3b82e2 5992 int ret;
2c07245f 5993 struct fdi_m_n m_n = {0};
fae14981 5994 u32 temp;
aa9b500d 5995 u32 lvds_sync = 0;
5a354204
JB		 5996 int target_clock, pixel_multiplier, lane, link_bw, factor;
5997 unsigned int pipe_bpp;
5998 bool dither;
e3aef172 5999 bool is_cpu_edp = false, is_pch_edp = false;
79e53945 6000
5eddb70b
CW		 6001 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6002 if (encoder->base.crtc != crtc)
79e53945
JB		 6003 continue;
6004
5eddb70b 6005 switch (encoder->type) {
79e53945
JB		 6006 case INTEL_OUTPUT_LVDS:
6007 is_lvds = true;
6008 break;
6009 case INTEL_OUTPUT_SDVO:
7d57382e 6010 case INTEL_OUTPUT_HDMI:
79e53945 6011 is_sdvo = true;
5eddb70b 6012 if (encoder->needs_tv_clock)
e2f0ba97 6013 is_tv = true;
79e53945 6014 break;
79e53945
JB		 6015 case INTEL_OUTPUT_TVOUT:
6016 is_tv = true;
6017 break;
6018 case INTEL_OUTPUT_ANALOG:
6019 is_crt = true;
6020 break;
a4fc5ed6
KP		 6021 case INTEL_OUTPUT_DISPLAYPORT:
6022 is_dp = true;
6023 break;
32f9d658 6024 case INTEL_OUTPUT_EDP:
e3aef172
JB		 6025 is_dp = true;
6026 if (intel_encoder_is_pch_edp(&encoder->base))
6027 is_pch_edp = true;
6028 else
6029 is_cpu_edp = true;
6030 edp_encoder = encoder;
32f9d658 6031 break;
79e53945 6032 }
43565a06 6033
c751ce4f 6034 num_connectors++;
79e53945
JB		 6035 }
6036
d9d444cb 6037 refclk = ironlake_get_refclk(crtc);
79e53945 6038
d4906093
ML		 6039 /*
6040 * Returns a set of divisors for the desired target clock with the given
6041 * refclk, or FALSE. The returned values represent the clock equation:
6042 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6043 */
1b894b59 6044 limit = intel_limit(crtc, refclk);
cec2f356
SP		 6045 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
6046 &clock);
79e53945
JB		 6047 if (!ok) {
6048 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 6049 return -EINVAL;
79e53945
JB		 6050 }
6051
cda4b7d3 6052 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 6053 intel_crtc_update_cursor(crtc, true);
cda4b7d3 6054
ddc9003c 6055 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 6056 /*
6057 * Ensure we match the reduced clock's P to the target clock.
6058 * If the clocks don't match, we can't switch the display clock
6059 * by using the FP0/FP1. In such case we will disable the LVDS
6060 * downclock feature.
6061 */
ddc9003c 6062 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 6063 dev_priv->lvds_downclock,
6064 refclk,
cec2f356 6065 &clock,
5eddb70b 6066 &reduced_clock);
652c393a 6067 }
7026d4ac
ZW		 6068 /* SDVO TV has fixed PLL values depend on its clock range,
6069 this mirrors vbios setting. */
6070 if (is_sdvo && is_tv) {
6071 if (adjusted_mode->clock >= 100000
5eddb70b 6072 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 6073 clock.p1 = 2;
6074 clock.p2 = 10;
6075 clock.n = 3;
6076 clock.m1 = 16;
6077 clock.m2 = 8;
6078 } else if (adjusted_mode->clock >= 140500
5eddb70b 6079 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 6080 clock.p1 = 1;
6081 clock.p2 = 10;
6082 clock.n = 6;
6083 clock.m1 = 12;
6084 clock.m2 = 8;
6085 }
6086 }
6087
2c07245f 6088 /* FDI link */
8febb297
EA		 6089 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
6090 lane = 0;
6091 /* CPU eDP doesn't require FDI link, so just set DP M/N
6092 according to current link config */
e3aef172 6093 if (is_cpu_edp) {
8febb297 6094 target_clock = mode->clock;
e3aef172 6095 intel_edp_link_config(edp_encoder, &lane, &link_bw);
8febb297
EA		 6096 } else {
6097 /* [e]DP over FDI requires target mode clock
6098 instead of link clock */
e3aef172 6099 if (is_dp)
5eb08b69 6100 target_clock = mode->clock;
8febb297
EA		 6101 else
6102 target_clock = adjusted_mode->clock;
6103
6104 /* FDI is a binary signal running at ~2.7GHz, encoding
6105 * each output octet as 10 bits. The actual frequency
6106 * is stored as a divider into a 100MHz clock, and the
6107 * mode pixel clock is stored in units of 1KHz.
6108 * Hence the bw of each lane in terms of the mode signal
6109 * is:
6110 */
6111 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6112 }
58a27471 6113
8febb297
EA		 6114 /* determine panel color depth */
6115 temp = I915_READ(PIPECONF(pipe));
6116 temp &= ~PIPE_BPC_MASK;
3b5c78a3 6117 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5a354204
JB		 6118 switch (pipe_bpp) {
6119 case 18:
6120 temp |= PIPE_6BPC;
8febb297 6121 break;
5a354204
JB		 6122 case 24:
6123 temp |= PIPE_8BPC;
8febb297 6124 break;
5a354204
JB		 6125 case 30:
6126 temp |= PIPE_10BPC;
8febb297 6127 break;
5a354204
JB		 6128 case 36:
6129 temp |= PIPE_12BPC;
8febb297
EA		 6130 break;
6131 default:
62ac41a6
JB		 6132 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
6133 pipe_bpp);
5a354204
JB		 6134 temp |= PIPE_8BPC;
6135 pipe_bpp = 24;
6136 break;
8febb297 6137 }
77ffb597 6138
5a354204
JB		 6139 intel_crtc->bpp = pipe_bpp;
6140 I915_WRITE(PIPECONF(pipe), temp);
6141
8febb297
EA		 6142 if (!lane) {
6143 /*
6144 * Account for spread spectrum to avoid
6145 * oversubscribing the link. Max center spread
6146 * is 2.5%; use 5% for safety's sake.
6147 */
5a354204 6148 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
8febb297 6149 lane = bps / (link_bw * 8) + 1;
5eb08b69 6150 }
2c07245f 6151
8febb297
EA		 6152 intel_crtc->fdi_lanes = lane;
6153
6154 if (pixel_multiplier > 1)
6155 link_bw *= pixel_multiplier;
5a354204
JB		 6156 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
6157 &m_n);
8febb297 6158
a07d6787
EA		 6159 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
6160 if (has_reduced_clock)
6161 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
6162 reduced_clock.m2;
79e53945 6163
c1858123 6164 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 6165 factor = 21;
6166 if (is_lvds) {
6167 if ((intel_panel_use_ssc(dev_priv) &&
6168 dev_priv->lvds_ssc_freq == 100) ||
6169 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
6170 factor = 25;
6171 } else if (is_sdvo && is_tv)
6172 factor = 20;
c1858123 6173
cb0e0931 6174 if (clock.m < factor * clock.n)
8febb297 6175 fp |= FP_CB_TUNE;
2c07245f 6176
5eddb70b 6177 dpll = 0;
2c07245f 6178
a07d6787
EA		 6179 if (is_lvds)
6180 dpll |= DPLLB_MODE_LVDS;
6181 else
6182 dpll |= DPLLB_MODE_DAC_SERIAL;
6183 if (is_sdvo) {
6184 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
6185 if (pixel_multiplier > 1) {
6186 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 6187 }
a07d6787
EA		 6188 dpll |= DPLL_DVO_HIGH_SPEED;
6189 }
e3aef172 6190 if (is_dp && !is_cpu_edp)
a07d6787 6191 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 6192
a07d6787
EA		 6193 /* compute bitmask from p1 value */
6194 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6195 /* also FPA1 */
6196 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6197
6198 switch (clock.p2) {
6199 case 5:
6200 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6201 break;
6202 case 7:
6203 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6204 break;
6205 case 10:
6206 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6207 break;
6208 case 14:
6209 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6210 break;
79e53945
JB		 6211 }
6212
43565a06
KH		 6213 if (is_sdvo && is_tv)
6214 dpll |= PLL_REF_INPUT_TVCLKINBC;
6215 else if (is_tv)
79e53945 6216 /* XXX: just matching BIOS for now */
43565a06 6217 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 6218 dpll |= 3;
a7615030 6219 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 6220 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 6221 else
6222 dpll |= PLL_REF_INPUT_DREFCLK;
6223
6224 /* setup pipeconf */
5eddb70b 6225 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 6226
6227 /* Set up the display plane register */
6228 dspcntr = DISPPLANE_GAMMA_ENABLE;
6229
f7cb34d4 6230 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 6231 drm_mode_debug_printmodeline(mode);
6232
5c5313c8 6233 /* PCH eDP needs FDI, but CPU eDP does not */
4b645f14 6234 if (!intel_crtc->no_pll) {
e3aef172 6235 if (!is_cpu_edp) {
4b645f14
JB		 6236 I915_WRITE(PCH_FP0(pipe), fp);
6237 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
6238
6239 POSTING_READ(PCH_DPLL(pipe));
6240 udelay(150);
6241 }
6242 } else {
6243 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
6244 fp == I915_READ(PCH_FP0(0))) {
6245 intel_crtc->use_pll_a = true;
6246 DRM_DEBUG_KMS("using pipe a dpll\n");
6247 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
6248 fp == I915_READ(PCH_FP0(1))) {
6249 intel_crtc->use_pll_a = false;
6250 DRM_DEBUG_KMS("using pipe b dpll\n");
6251 } else {
6252 DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
6253 return -EINVAL;
6254 }
79e53945
JB		 6255 }
6256
6257 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
6258 * This is an exception to the general rule that mode_set doesn't turn
6259 * things on.
6260 */
6261 if (is_lvds) {
fae14981 6262 temp = I915_READ(PCH_LVDS);
5eddb70b 6263 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 6264 if (HAS_PCH_CPT(dev)) {
6265 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 6266 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 6267 } else {
6268 if (pipe == 1)
6269 temp |= LVDS_PIPEB_SELECT;
6270 else
6271 temp &= ~LVDS_PIPEB_SELECT;
6272 }
4b645f14 6273
a3e17eb8 6274 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 6275 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 6276 /* Set the B0-B3 data pairs corresponding to whether we're going to
6277 * set the DPLLs for dual-channel mode or not.
6278 */
6279 if (clock.p2 == 7)
5eddb70b 6280 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 6281 else
5eddb70b 6282 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 6283
6284 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
6285 * appropriately here, but we need to look more thoroughly into how
6286 * panels behave in the two modes.
6287 */
aa9b500d
BF		 6288 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
6289 lvds_sync |= LVDS_HSYNC_POLARITY;
6290 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
6291 lvds_sync |= LVDS_VSYNC_POLARITY;
6292 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
6293 != lvds_sync) {
6294 char flags[2] = "-+";
6295 DRM_INFO("Changing LVDS panel from "
6296 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
6297 flags[!(temp & LVDS_HSYNC_POLARITY)],
6298 flags[!(temp & LVDS_VSYNC_POLARITY)],
6299 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
6300 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
6301 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
6302 temp |= lvds_sync;
6303 }
fae14981 6304 I915_WRITE(PCH_LVDS, temp);
79e53945 6305 }
434ed097 6306
8febb297
EA		 6307 pipeconf &= ~PIPECONF_DITHER_EN;
6308 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5a354204 6309 if ((is_lvds && dev_priv->lvds_dither) || dither) {
8febb297 6310 pipeconf |= PIPECONF_DITHER_EN;
f74974c7 6311 pipeconf |= PIPECONF_DITHER_TYPE_SP;
434ed097 6312 }
e3aef172 6313 if (is_dp && !is_cpu_edp) {
a4fc5ed6 6314 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 6315 } else {
8db9d77b 6316 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 6317 I915_WRITE(TRANSDATA_M1(pipe), 0);
6318 I915_WRITE(TRANSDATA_N1(pipe), 0);
6319 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
6320 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 6321 }
79e53945 6322
e3aef172 6323 if (!intel_crtc->no_pll && (!edp_encoder || is_pch_edp)) {
fae14981 6324 I915_WRITE(PCH_DPLL(pipe), dpll);
5eddb70b 6325
32f9d658 6326 /* Wait for the clocks to stabilize. */
fae14981 6327 POSTING_READ(PCH_DPLL(pipe));
32f9d658
ZW		 6328 udelay(150);
6329
8febb297
EA		 6330 /* The pixel multiplier can only be updated once the
6331 * DPLL is enabled and the clocks are stable.
6332 *
6333 * So write it again.
6334 */
fae14981 6335 I915_WRITE(PCH_DPLL(pipe), dpll);
79e53945 6336 }
79e53945 6337
5eddb70b 6338 intel_crtc->lowfreq_avail = false;
4b645f14
JB		 6339 if (!intel_crtc->no_pll) {
6340 if (is_lvds && has_reduced_clock && i915_powersave) {
6341 I915_WRITE(PCH_FP1(pipe), fp2);
6342 intel_crtc->lowfreq_avail = true;
6343 if (HAS_PIPE_CXSR(dev)) {
6344 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6345 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6346 }
6347 } else {
6348 I915_WRITE(PCH_FP1(pipe), fp);
6349 if (HAS_PIPE_CXSR(dev)) {
6350 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6351 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
6352 }
652c393a
JB		 6353 }
6354 }
6355
617cf884 6356 pipeconf &= ~PIPECONF_INTERLACE_MASK;
734b4157 6357 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5def474e 6358 pipeconf |= PIPECONF_INTERLACED_ILK;
734b4157 6359 /* the chip adds 2 halflines automatically */
734b4157 6360 adjusted_mode->crtc_vtotal -= 1;
734b4157 6361 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 6362 I915_WRITE(VSYNCSHIFT(pipe),
6363 adjusted_mode->crtc_hsync_start
6364 - adjusted_mode->crtc_htotal/2);
6365 } else {
617cf884 6366 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 6367 I915_WRITE(VSYNCSHIFT(pipe), 0);
6368 }
734b4157 6369
5eddb70b
CW		 6370 I915_WRITE(HTOTAL(pipe),
6371 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 6372 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 6373 I915_WRITE(HBLANK(pipe),
6374 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 6375 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 6376 I915_WRITE(HSYNC(pipe),
6377 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 6378 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 6379
6380 I915_WRITE(VTOTAL(pipe),
6381 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 6382 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 6383 I915_WRITE(VBLANK(pipe),
6384 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 6385 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 6386 I915_WRITE(VSYNC(pipe),
6387 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 6388 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 6389
8febb297
EA		 6390 /* pipesrc controls the size that is scaled from, which should
6391 * always be the user's requested size.
79e53945 6392 */
5eddb70b
CW		 6393 I915_WRITE(PIPESRC(pipe),
6394 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 6395
8febb297
EA		 6396 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
6397 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
6398 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
6399 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 6400
e3aef172 6401 if (is_cpu_edp)
8febb297 6402 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f 6403
5eddb70b
CW		 6404 I915_WRITE(PIPECONF(pipe), pipeconf);
6405 POSTING_READ(PIPECONF(pipe));
79e53945 6406
9d0498a2 6407 intel_wait_for_vblank(dev, pipe);
79e53945 6408
5eddb70b 6409 I915_WRITE(DSPCNTR(plane), dspcntr);
b24e7179 6410 POSTING_READ(DSPCNTR(plane));
79e53945 6411
5c3b82e2 6412 ret = intel_pipe_set_base(crtc, x, y, old_fb);
7662c8bd
SL		 6413
6414 intel_update_watermarks(dev);
6415
1f803ee5 6416 return ret;
79e53945
JB		 6417}
6418
f564048e
EA		 6419static int intel_crtc_mode_set(struct drm_crtc *crtc,
6420 struct drm_display_mode *mode,
6421 struct drm_display_mode *adjusted_mode,
6422 int x, int y,
6423 struct drm_framebuffer *old_fb)
6424{
6425 struct drm_device *dev = crtc->dev;
6426 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 6427 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6428 int pipe = intel_crtc->pipe;
f564048e
EA		 6429 int ret;
6430
0b701d27 6431 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6432
f564048e
EA		 6433 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
6434 x, y, old_fb);
79e53945 6435 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6436
d8e70a25
JB		 6437 if (ret)
6438 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
6439 else
6440 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
120eced9 6441
1f803ee5 6442 return ret;
79e53945
JB		 6443}
6444
3a9627f4
WF		 6445static bool intel_eld_uptodate(struct drm_connector *connector,
6446 int reg_eldv, uint32_t bits_eldv,
6447 int reg_elda, uint32_t bits_elda,
6448 int reg_edid)
6449{
6450 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6451 uint8_t *eld = connector->eld;
6452 uint32_t i;
6453
6454 i = I915_READ(reg_eldv);
6455 i &= bits_eldv;
6456
6457 if (!eld[0])
6458 return !i;
6459
6460 if (!i)
6461 return false;
6462
6463 i = I915_READ(reg_elda);
6464 i &= ~bits_elda;
6465 I915_WRITE(reg_elda, i);
6466
6467 for (i = 0; i < eld[2]; i++)
6468 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6469 return false;
6470
6471 return true;
6472}
6473
e0dac65e
WF		 6474static void g4x_write_eld(struct drm_connector *connector,
6475 struct drm_crtc *crtc)
6476{
6477 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6478 uint8_t *eld = connector->eld;
6479 uint32_t eldv;
6480 uint32_t len;
6481 uint32_t i;
6482
6483 i = I915_READ(G4X_AUD_VID_DID);
6484
6485 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6486 eldv = G4X_ELDV_DEVCL_DEVBLC;
6487 else
6488 eldv = G4X_ELDV_DEVCTG;
6489
3a9627f4
WF		 6490 if (intel_eld_uptodate(connector,
6491 G4X_AUD_CNTL_ST, eldv,
6492 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6493 G4X_HDMIW_HDMIEDID))
6494 return;
6495
e0dac65e
WF		 6496 i = I915_READ(G4X_AUD_CNTL_ST);
6497 i &= ~(eldv | G4X_ELD_ADDR);
6498 len = (i >> 9) & 0x1f; /* ELD buffer size */
6499 I915_WRITE(G4X_AUD_CNTL_ST, i);
6500
6501 if (!eld[0])
6502 return;
6503
6504 len = min_t(uint8_t, eld[2], len);
6505 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6506 for (i = 0; i < len; i++)
6507 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6508
6509 i = I915_READ(G4X_AUD_CNTL_ST);
6510 i |= eldv;
6511 I915_WRITE(G4X_AUD_CNTL_ST, i);
6512}
6513
6514static void ironlake_write_eld(struct drm_connector *connector,
6515 struct drm_crtc *crtc)
6516{
6517 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6518 uint8_t *eld = connector->eld;
6519 uint32_t eldv;
6520 uint32_t i;
6521 int len;
6522 int hdmiw_hdmiedid;
b6daa025 6523 int aud_config;
e0dac65e
WF		 6524 int aud_cntl_st;
6525 int aud_cntrl_st2;
6526
b3f33cbf 6527 if (HAS_PCH_IBX(connector->dev)) {
1202b4c6 6528 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
b6daa025 6529 aud_config = IBX_AUD_CONFIG_A;
1202b4c6
WF		 6530 aud_cntl_st = IBX_AUD_CNTL_ST_A;
6531 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6532 } else {
1202b4c6 6533 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
b6daa025 6534 aud_config = CPT_AUD_CONFIG_A;
1202b4c6
WF		 6535 aud_cntl_st = CPT_AUD_CNTL_ST_A;
6536 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6537 }
6538
6539 i = to_intel_crtc(crtc)->pipe;
6540 hdmiw_hdmiedid += i * 0x100;
6541 aud_cntl_st += i * 0x100;
b6daa025 6542 aud_config += i * 0x100;
e0dac65e
WF		 6543
6544 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
6545
6546 i = I915_READ(aud_cntl_st);
6547 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
6548 if (!i) {
6549 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6550 /* operate blindly on all ports */
1202b4c6
WF		 6551 eldv = IBX_ELD_VALIDB;
6552 eldv |= IBX_ELD_VALIDB << 4;
6553 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 6554 } else {
6555 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 6556 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6557 }
6558
3a9627f4
WF		 6559 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6560 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6561 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6562 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6563 } else
6564 I915_WRITE(aud_config, 0);
e0dac65e 6565
3a9627f4
WF		 6566 if (intel_eld_uptodate(connector,
6567 aud_cntrl_st2, eldv,
6568 aud_cntl_st, IBX_ELD_ADDRESS,
6569 hdmiw_hdmiedid))
6570 return;
6571
e0dac65e
WF		 6572 i = I915_READ(aud_cntrl_st2);
6573 i &= ~eldv;
6574 I915_WRITE(aud_cntrl_st2, i);
6575
6576 if (!eld[0])
6577 return;
6578
e0dac65e 6579 i = I915_READ(aud_cntl_st);
1202b4c6 6580 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6581 I915_WRITE(aud_cntl_st, i);
6582
6583 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6584 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6585 for (i = 0; i < len; i++)
6586 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6587
6588 i = I915_READ(aud_cntrl_st2);
6589 i |= eldv;
6590 I915_WRITE(aud_cntrl_st2, i);
6591}
6592
6593void intel_write_eld(struct drm_encoder *encoder,
6594 struct drm_display_mode *mode)
6595{
6596 struct drm_crtc *crtc = encoder->crtc;
6597 struct drm_connector *connector;
6598 struct drm_device *dev = encoder->dev;
6599 struct drm_i915_private *dev_priv = dev->dev_private;
6600
6601 connector = drm_select_eld(encoder, mode);
6602 if (!connector)
6603 return;
6604
6605 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6606 connector->base.id,
6607 drm_get_connector_name(connector),
6608 connector->encoder->base.id,
6609 drm_get_encoder_name(connector->encoder));
6610
6611 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6612
6613 if (dev_priv->display.write_eld)
6614 dev_priv->display.write_eld(connector, crtc);
6615}
6616
79e53945
JB		 6617/** Loads the palette/gamma unit for the CRTC with the prepared values */
6618void intel_crtc_load_lut(struct drm_crtc *crtc)
6619{
6620 struct drm_device *dev = crtc->dev;
6621 struct drm_i915_private *dev_priv = dev->dev_private;
6622 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6623 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6624 int i;
6625
6626 /* The clocks have to be on to load the palette. */
aed3f09d 6627 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6628 return;
6629
f2b115e6 6630 /* use legacy palette for Ironlake */
bad720ff 6631 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6632 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6633
79e53945
JB		 6634 for (i = 0; i < 256; i++) {
6635 I915_WRITE(palreg + 4 * i,
6636 (intel_crtc->lut_r[i] << 16) |
6637 (intel_crtc->lut_g[i] << 8) |
6638 intel_crtc->lut_b[i]);
6639 }
6640}
6641
560b85bb
CW		 6642static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6643{
6644 struct drm_device *dev = crtc->dev;
6645 struct drm_i915_private *dev_priv = dev->dev_private;
6646 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6647 bool visible = base != 0;
6648 u32 cntl;
6649
6650 if (intel_crtc->cursor_visible == visible)
6651 return;
6652
9db4a9c7 6653 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6654 if (visible) {
6655 /* On these chipsets we can only modify the base whilst
6656 * the cursor is disabled.
6657 */
9db4a9c7 6658 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6659
6660 cntl &= ~(CURSOR_FORMAT_MASK);
6661 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6662 cntl |= CURSOR_ENABLE |
6663 CURSOR_GAMMA_ENABLE |
6664 CURSOR_FORMAT_ARGB;
6665 } else
6666 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6667 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6668
6669 intel_crtc->cursor_visible = visible;
6670}
6671
6672static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6673{
6674 struct drm_device *dev = crtc->dev;
6675 struct drm_i915_private *dev_priv = dev->dev_private;
6676 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6677 int pipe = intel_crtc->pipe;
6678 bool visible = base != 0;
6679
6680 if (intel_crtc->cursor_visible != visible) {
548f245b 6681 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6682 if (base) {
6683 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6684 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6685 cntl |= pipe << 28; /* Connect to correct pipe */
6686 } else {
6687 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6688 cntl |= CURSOR_MODE_DISABLE;
6689 }
9db4a9c7 6690 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6691
6692 intel_crtc->cursor_visible = visible;
6693 }
6694 /* and commit changes on next vblank */
9db4a9c7 6695 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6696}
6697
65a21cd6
JB		 6698static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6699{
6700 struct drm_device *dev = crtc->dev;
6701 struct drm_i915_private *dev_priv = dev->dev_private;
6702 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6703 int pipe = intel_crtc->pipe;
6704 bool visible = base != 0;
6705
6706 if (intel_crtc->cursor_visible != visible) {
6707 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6708 if (base) {
6709 cntl &= ~CURSOR_MODE;
6710 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6711 } else {
6712 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6713 cntl |= CURSOR_MODE_DISABLE;
6714 }
6715 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6716
6717 intel_crtc->cursor_visible = visible;
6718 }
6719 /* and commit changes on next vblank */
6720 I915_WRITE(CURBASE_IVB(pipe), base);
6721}
6722
cda4b7d3 6723/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6724static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6725 bool on)
cda4b7d3
CW		 6726{
6727 struct drm_device *dev = crtc->dev;
6728 struct drm_i915_private *dev_priv = dev->dev_private;
6729 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6730 int pipe = intel_crtc->pipe;
6731 int x = intel_crtc->cursor_x;
6732 int y = intel_crtc->cursor_y;
560b85bb 6733 u32 base, pos;
cda4b7d3
CW		 6734 bool visible;
6735
6736 pos = 0;
6737
6b383a7f 6738 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6739 base = intel_crtc->cursor_addr;
6740 if (x > (int) crtc->fb->width)
6741 base = 0;
6742
6743 if (y > (int) crtc->fb->height)
6744 base = 0;
6745 } else
6746 base = 0;
6747
6748 if (x < 0) {
6749 if (x + intel_crtc->cursor_width < 0)
6750 base = 0;
6751
6752 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6753 x = -x;
6754 }
6755 pos |= x << CURSOR_X_SHIFT;
6756
6757 if (y < 0) {
6758 if (y + intel_crtc->cursor_height < 0)
6759 base = 0;
6760
6761 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6762 y = -y;
6763 }
6764 pos |= y << CURSOR_Y_SHIFT;
6765
6766 visible = base != 0;
560b85bb 6767 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6768 return;
6769
0cd83aa9 6770 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6771 I915_WRITE(CURPOS_IVB(pipe), pos);
6772 ivb_update_cursor(crtc, base);
6773 } else {
6774 I915_WRITE(CURPOS(pipe), pos);
6775 if (IS_845G(dev) || IS_I865G(dev))
6776 i845_update_cursor(crtc, base);
6777 else
6778 i9xx_update_cursor(crtc, base);
6779 }
cda4b7d3
CW		 6780
6781 if (visible)
6782 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
6783}
6784
79e53945 6785static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6786 struct drm_file *file,
79e53945
JB		 6787 uint32_t handle,
6788 uint32_t width, uint32_t height)
6789{
6790 struct drm_device *dev = crtc->dev;
6791 struct drm_i915_private *dev_priv = dev->dev_private;
6792 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6793 struct drm_i915_gem_object *obj;
cda4b7d3 6794 uint32_t addr;
3f8bc370 6795 int ret;
79e53945 6796
28c97730 6797 DRM_DEBUG_KMS("\n");
79e53945
JB		 6798
6799 /* if we want to turn off the cursor ignore width and height */
6800 if (!handle) {
28c97730 6801 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6802 addr = 0;
05394f39 6803 obj = NULL;
5004417d 6804 mutex_lock(&dev->struct_mutex);
3f8bc370 6805 goto finish;
79e53945
JB		 6806 }
6807
6808 /* Currently we only support 64x64 cursors */
6809 if (width != 64 || height != 64) {
6810 DRM_ERROR("we currently only support 64x64 cursors\n");
6811 return -EINVAL;
6812 }
6813
05394f39 6814 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6815 if (&obj->base == NULL)
79e53945
JB		 6816 return -ENOENT;
6817
05394f39 6818 if (obj->base.size < width * height * 4) {
79e53945 6819 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6820 ret = -ENOMEM;
6821 goto fail;
79e53945
JB		 6822 }
6823
71acb5eb 6824 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6825 mutex_lock(&dev->struct_mutex);
b295d1b6 6826 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 6827 if (obj->tiling_mode) {
6828 DRM_ERROR("cursor cannot be tiled\n");
6829 ret = -EINVAL;
6830 goto fail_locked;
6831 }
6832
2da3b9b9 6833 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 6834 if (ret) {
6835 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6836 goto fail_locked;
e7b526bb
CW		 6837 }
6838
d9e86c0e
CW		 6839 ret = i915_gem_object_put_fence(obj);
6840 if (ret) {
2da3b9b9 6841 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6842 goto fail_unpin;
6843 }
6844
05394f39 6845 addr = obj->gtt_offset;
71acb5eb 6846 } else {
6eeefaf3 6847 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6848 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6849 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6850 align);
71acb5eb
DA		 6851 if (ret) {
6852 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6853 goto fail_locked;
71acb5eb 6854 }
05394f39 6855 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6856 }
6857
a6c45cf0 6858 if (IS_GEN2(dev))
14b60391
JB		 6859 I915_WRITE(CURSIZE, (height << 12) | width);
6860
3f8bc370 6861 finish:
3f8bc370 6862 if (intel_crtc->cursor_bo) {
b295d1b6 6863 if (dev_priv->info->cursor_needs_physical) {
05394f39 6864 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6865 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6866 } else
6867 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6868 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6869 }
80824003 6870
7f9872e0 6871 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6872
6873 intel_crtc->cursor_addr = addr;
05394f39 6874 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6875 intel_crtc->cursor_width = width;
6876 intel_crtc->cursor_height = height;
6877
6b383a7f 6878 intel_crtc_update_cursor(crtc, true);
3f8bc370 6879
79e53945 6880 return 0;
e7b526bb 6881fail_unpin:
05394f39 6882 i915_gem_object_unpin(obj);
7f9872e0 6883fail_locked:
34b8686e 6884 mutex_unlock(&dev->struct_mutex);
bc9025bd 6885fail:
05394f39 6886 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6887 return ret;
79e53945
JB		 6888}
6889
6890static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6891{
79e53945 6892 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6893
cda4b7d3
CW		 6894 intel_crtc->cursor_x = x;
6895 intel_crtc->cursor_y = y;
652c393a 6896
6b383a7f 6897 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6898
6899 return 0;
6900}
6901
6902/** Sets the color ramps on behalf of RandR */
6903void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6904 u16 blue, int regno)
6905{
6906 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6907
6908 intel_crtc->lut_r[regno] = red >> 8;
6909 intel_crtc->lut_g[regno] = green >> 8;
6910 intel_crtc->lut_b[regno] = blue >> 8;
6911}
6912
b8c00ac5
DA		 6913void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6914 u16 *blue, int regno)
6915{
6916 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6917
6918 *red = intel_crtc->lut_r[regno] << 8;
6919 *green = intel_crtc->lut_g[regno] << 8;
6920 *blue = intel_crtc->lut_b[regno] << 8;
6921}
6922
79e53945 6923static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6924 u16 *blue, uint32_t start, uint32_t size)
79e53945 6925{
7203425a 6926 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6927 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6928
7203425a 6929 for (i = start; i < end; i++) {
79e53945
JB		 6930 intel_crtc->lut_r[i] = red[i] >> 8;
6931 intel_crtc->lut_g[i] = green[i] >> 8;
6932 intel_crtc->lut_b[i] = blue[i] >> 8;
6933 }
6934
6935 intel_crtc_load_lut(crtc);
6936}
6937
6938/**
6939 * Get a pipe with a simple mode set on it for doing load-based monitor
6940 * detection.
6941 *
6942 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 6943 * its requirements. The pipe will be connected to no other encoders.
79e53945 6944 *
c751ce4f 6945 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 6946 * configured for it. In the future, it could choose to temporarily disable
6947 * some outputs to free up a pipe for its use.
6948 *
6949 * \return crtc, or NULL if no pipes are available.
6950 */
6951
6952/* VESA 640x480x72Hz mode to set on the pipe */
6953static struct drm_display_mode load_detect_mode = {
6954 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6955 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6956};
6957
d2dff872
CW		 6958static struct drm_framebuffer *
6959intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6960 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6961 struct drm_i915_gem_object *obj)
6962{
6963 struct intel_framebuffer *intel_fb;
6964 int ret;
6965
6966 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6967 if (!intel_fb) {
6968 drm_gem_object_unreference_unlocked(&obj->base);
6969 return ERR_PTR(-ENOMEM);
6970 }
6971
6972 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6973 if (ret) {
6974 drm_gem_object_unreference_unlocked(&obj->base);
6975 kfree(intel_fb);
6976 return ERR_PTR(ret);
6977 }
6978
6979 return &intel_fb->base;
6980}
6981
6982static u32
6983intel_framebuffer_pitch_for_width(int width, int bpp)
6984{
6985 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6986 return ALIGN(pitch, 64);
6987}
6988
6989static u32
6990intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6991{
6992 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6993 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6994}
6995
6996static struct drm_framebuffer *
6997intel_framebuffer_create_for_mode(struct drm_device *dev,
6998 struct drm_display_mode *mode,
6999 int depth, int bpp)
7000{
7001 struct drm_i915_gem_object *obj;
308e5bcb 7002 struct drm_mode_fb_cmd2 mode_cmd;
d2dff872
CW		 7003
7004 obj = i915_gem_alloc_object(dev,
7005 intel_framebuffer_size_for_mode(mode, bpp));
7006 if (obj == NULL)
7007 return ERR_PTR(-ENOMEM);
7008
7009 mode_cmd.width = mode->hdisplay;
7010 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 7011 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7012 bpp);
5ca0c34a 7013 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 7014
7015 return intel_framebuffer_create(dev, &mode_cmd, obj);
7016}
7017
7018static struct drm_framebuffer *
7019mode_fits_in_fbdev(struct drm_device *dev,
7020 struct drm_display_mode *mode)
7021{
7022 struct drm_i915_private *dev_priv = dev->dev_private;
7023 struct drm_i915_gem_object *obj;
7024 struct drm_framebuffer *fb;
7025
7026 if (dev_priv->fbdev == NULL)
7027 return NULL;
7028
7029 obj = dev_priv->fbdev->ifb.obj;
7030 if (obj == NULL)
7031 return NULL;
7032
7033 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 7034 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7035 fb->bits_per_pixel))
d2dff872
CW		 7036 return NULL;
7037
01f2c773 7038 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 7039 return NULL;
7040
7041 return fb;
7042}
7043
7173188d
CW		 7044bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
7045 struct drm_connector *connector,
7046 struct drm_display_mode *mode,
8261b191 7047 struct intel_load_detect_pipe *old)
79e53945
JB		 7048{
7049 struct intel_crtc *intel_crtc;
7050 struct drm_crtc *possible_crtc;
4ef69c7a 7051 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 7052 struct drm_crtc *crtc = NULL;
7053 struct drm_device *dev = encoder->dev;
d2dff872 7054 struct drm_framebuffer *old_fb;
79e53945
JB		 7055 int i = -1;
7056
d2dff872
CW		 7057 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7058 connector->base.id, drm_get_connector_name(connector),
7059 encoder->base.id, drm_get_encoder_name(encoder));
7060
79e53945
JB		 7061 /*
7062 * Algorithm gets a little messy:
7a5e4805 7063 *
79e53945
JB		 7064 * - if the connector already has an assigned crtc, use it (but make
7065 * sure it's on first)
7a5e4805 7066 *
79e53945
JB		 7067 * - try to find the first unused crtc that can drive this connector,
7068 * and use that if we find one
79e53945
JB		 7069 */
7070
7071 /* See if we already have a CRTC for this connector */
7072 if (encoder->crtc) {
7073 crtc = encoder->crtc;
8261b191 7074
79e53945 7075 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 7076 old->dpms_mode = intel_crtc->dpms_mode;
7077 old->load_detect_temp = false;
7078
7079 /* Make sure the crtc and connector are running */
79e53945 7080 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6492711d
CW		 7081 struct drm_encoder_helper_funcs *encoder_funcs;
7082 struct drm_crtc_helper_funcs *crtc_funcs;
7083
79e53945
JB		 7084 crtc_funcs = crtc->helper_private;
7085 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6492711d
CW		 7086
7087 encoder_funcs = encoder->helper_private;
79e53945
JB		 7088 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
7089 }
8261b191 7090
7173188d 7091 return true;
79e53945
JB		 7092 }
7093
7094 /* Find an unused one (if possible) */
7095 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7096 i++;
7097 if (!(encoder->possible_crtcs & (1 << i)))
7098 continue;
7099 if (!possible_crtc->enabled) {
7100 crtc = possible_crtc;
7101 break;
7102 }
79e53945
JB		 7103 }
7104
7105 /*
7106 * If we didn't find an unused CRTC, don't use any.
7107 */
7108 if (!crtc) {
7173188d
CW		 7109 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7110 return false;
79e53945
JB		 7111 }
7112
7113 encoder->crtc = crtc;
c1c43977 7114 connector->encoder = encoder;
79e53945
JB		 7115
7116 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 7117 old->dpms_mode = intel_crtc->dpms_mode;
7118 old->load_detect_temp = true;
d2dff872 7119 old->release_fb = NULL;
79e53945 7120
6492711d
CW		 7121 if (!mode)
7122 mode = &load_detect_mode;
79e53945 7123
d2dff872
CW		 7124 old_fb = crtc->fb;
7125
7126 /* We need a framebuffer large enough to accommodate all accesses
7127 * that the plane may generate whilst we perform load detection.
7128 * We can not rely on the fbcon either being present (we get called
7129 * during its initialisation to detect all boot displays, or it may
7130 * not even exist) or that it is large enough to satisfy the
7131 * requested mode.
7132 */
7133 crtc->fb = mode_fits_in_fbdev(dev, mode);
7134 if (crtc->fb == NULL) {
7135 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7136 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7137 old->release_fb = crtc->fb;
7138 } else
7139 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7140 if (IS_ERR(crtc->fb)) {
7141 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7142 crtc->fb = old_fb;
7143 return false;
79e53945 7144 }
79e53945 7145
d2dff872 7146 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6492711d 7147 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 7148 if (old->release_fb)
7149 old->release_fb->funcs->destroy(old->release_fb);
7150 crtc->fb = old_fb;
6492711d 7151 return false;
79e53945 7152 }
7173188d 7153
79e53945 7154 /* let the connector get through one full cycle before testing */
9d0498a2 7155 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 7156
7173188d 7157 return true;
79e53945
JB		 7158}
7159
c1c43977 7160void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
8261b191
CW		 7161 struct drm_connector *connector,
7162 struct intel_load_detect_pipe *old)
79e53945 7163{
4ef69c7a 7164 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 7165 struct drm_device *dev = encoder->dev;
7166 struct drm_crtc *crtc = encoder->crtc;
7167 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
7168 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
7169
d2dff872
CW		 7170 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7171 connector->base.id, drm_get_connector_name(connector),
7172 encoder->base.id, drm_get_encoder_name(encoder));
7173
8261b191 7174 if (old->load_detect_temp) {
c1c43977 7175 connector->encoder = NULL;
79e53945 7176 drm_helper_disable_unused_functions(dev);
d2dff872
CW		 7177
7178 if (old->release_fb)
7179 old->release_fb->funcs->destroy(old->release_fb);
7180
0622a53c 7181 return;
79e53945
JB		 7182 }
7183
c751ce4f 7184 /* Switch crtc and encoder back off if necessary */
0622a53c
CW		 7185 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
7186 encoder_funcs->dpms(encoder, old->dpms_mode);
8261b191 7187 crtc_funcs->dpms(crtc, old->dpms_mode);
79e53945
JB		 7188 }
7189}
7190
7191/* Returns the clock of the currently programmed mode of the given pipe. */
7192static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
7193{
7194 struct drm_i915_private *dev_priv = dev->dev_private;
7195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7196 int pipe = intel_crtc->pipe;
548f245b 7197 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 7198 u32 fp;
7199 intel_clock_t clock;
7200
7201 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 7202 fp = I915_READ(FP0(pipe));
79e53945 7203 else
39adb7a5 7204 fp = I915_READ(FP1(pipe));
79e53945
JB		 7205
7206 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 7207 if (IS_PINEVIEW(dev)) {
7208 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7209 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 7210 } else {
7211 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7212 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7213 }
7214
a6c45cf0 7215 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 7216 if (IS_PINEVIEW(dev))
7217 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7218 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 7219 else
7220 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 7221 DPLL_FPA01_P1_POST_DIV_SHIFT);
7222
7223 switch (dpll & DPLL_MODE_MASK) {
7224 case DPLLB_MODE_DAC_SERIAL:
7225 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7226 5 : 10;
7227 break;
7228 case DPLLB_MODE_LVDS:
7229 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7230 7 : 14;
7231 break;
7232 default:
28c97730 7233 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 7234 "mode\n", (int)(dpll & DPLL_MODE_MASK));
7235 return 0;
7236 }
7237
7238 /* XXX: Handle the 100Mhz refclk */
2177832f 7239 intel_clock(dev, 96000, &clock);
79e53945
JB		 7240 } else {
7241 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7242
7243 if (is_lvds) {
7244 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7245 DPLL_FPA01_P1_POST_DIV_SHIFT);
7246 clock.p2 = 14;
7247
7248 if ((dpll & PLL_REF_INPUT_MASK) ==
7249 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7250 /* XXX: might not be 66MHz */
2177832f 7251 intel_clock(dev, 66000, &clock);
79e53945 7252 } else
2177832f 7253 intel_clock(dev, 48000, &clock);
79e53945
JB		 7254 } else {
7255 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7256 clock.p1 = 2;
7257 else {
7258 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7259 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7260 }
7261 if (dpll & PLL_P2_DIVIDE_BY_4)
7262 clock.p2 = 4;
7263 else
7264 clock.p2 = 2;
7265
2177832f 7266 intel_clock(dev, 48000, &clock);
79e53945
JB		 7267 }
7268 }
7269
7270 /* XXX: It would be nice to validate the clocks, but we can't reuse
7271 * i830PllIsValid() because it relies on the xf86_config connector
7272 * configuration being accurate, which it isn't necessarily.
7273 */
7274
7275 return clock.dot;
7276}
7277
7278/** Returns the currently programmed mode of the given pipe. */
7279struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7280 struct drm_crtc *crtc)
7281{
548f245b 7282 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 7283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7284 int pipe = intel_crtc->pipe;
7285 struct drm_display_mode *mode;
548f245b
JB		 7286 int htot = I915_READ(HTOTAL(pipe));
7287 int hsync = I915_READ(HSYNC(pipe));
7288 int vtot = I915_READ(VTOTAL(pipe));
7289 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 7290
7291 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7292 if (!mode)
7293 return NULL;
7294
7295 mode->clock = intel_crtc_clock_get(dev, crtc);
7296 mode->hdisplay = (htot & 0xffff) + 1;
7297 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7298 mode->hsync_start = (hsync & 0xffff) + 1;
7299 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7300 mode->vdisplay = (vtot & 0xffff) + 1;
7301 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7302 mode->vsync_start = (vsync & 0xffff) + 1;
7303 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7304
7305 drm_mode_set_name(mode);
7306 drm_mode_set_crtcinfo(mode, 0);
7307
7308 return mode;
7309}
7310
652c393a
JB		 7311#define GPU_IDLE_TIMEOUT 500 /* ms */
7312
7313/* When this timer fires, we've been idle for awhile */
7314static void intel_gpu_idle_timer(unsigned long arg)
7315{
7316 struct drm_device *dev = (struct drm_device *)arg;
7317 drm_i915_private_t *dev_priv = dev->dev_private;
7318
ff7ea4c0
CW		 7319 if (!list_empty(&dev_priv->mm.active_list)) {
7320 /* Still processing requests, so just re-arm the timer. */
7321 mod_timer(&dev_priv->idle_timer, jiffies +
7322 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
7323 return;
7324 }
652c393a 7325
ff7ea4c0 7326 dev_priv->busy = false;
01dfba93 7327 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 7328}
7329
652c393a
JB		 7330#define CRTC_IDLE_TIMEOUT 1000 /* ms */
7331
7332static void intel_crtc_idle_timer(unsigned long arg)
7333{
7334 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
7335 struct drm_crtc *crtc = &intel_crtc->base;
7336 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
ff7ea4c0 7337 struct intel_framebuffer *intel_fb;
652c393a 7338
ff7ea4c0
CW		 7339 intel_fb = to_intel_framebuffer(crtc->fb);
7340 if (intel_fb && intel_fb->obj->active) {
7341 /* The framebuffer is still being accessed by the GPU. */
7342 mod_timer(&intel_crtc->idle_timer, jiffies +
7343 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7344 return;
7345 }
652c393a 7346
ff7ea4c0 7347 intel_crtc->busy = false;
01dfba93 7348 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 7349}
7350
3dec0095 7351static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7352{
7353 struct drm_device *dev = crtc->dev;
7354 drm_i915_private_t *dev_priv = dev->dev_private;
7355 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7356 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7357 int dpll_reg = DPLL(pipe);
7358 int dpll;
652c393a 7359
bad720ff 7360 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7361 return;
7362
7363 if (!dev_priv->lvds_downclock_avail)
7364 return;
7365
dbdc6479 7366 dpll = I915_READ(dpll_reg);
652c393a 7367 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7368 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7369
8ac5a6d5 7370 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7371
7372 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7373 I915_WRITE(dpll_reg, dpll);
9d0498a2 7374 intel_wait_for_vblank(dev, pipe);
dbdc6479 7375
652c393a
JB		 7376 dpll = I915_READ(dpll_reg);
7377 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7378 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a
JB		 7379 }
7380
7381 /* Schedule downclock */
3dec0095
DV		 7382 mod_timer(&intel_crtc->idle_timer, jiffies +
7383 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
652c393a
JB		 7384}
7385
7386static void intel_decrease_pllclock(struct drm_crtc *crtc)
7387{
7388 struct drm_device *dev = crtc->dev;
7389 drm_i915_private_t *dev_priv = dev->dev_private;
7390 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7391 int pipe = intel_crtc->pipe;
9db4a9c7 7392 int dpll_reg = DPLL(pipe);
652c393a
JB		 7393 int dpll = I915_READ(dpll_reg);
7394
bad720ff 7395 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7396 return;
7397
7398 if (!dev_priv->lvds_downclock_avail)
7399 return;
7400
7401 /*
7402 * Since this is called by a timer, we should never get here in
7403 * the manual case.
7404 */
7405 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
44d98a61 7406 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7407
8ac5a6d5 7408 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7409
7410 dpll |= DISPLAY_RATE_SELECT_FPA1;
7411 I915_WRITE(dpll_reg, dpll);
9d0498a2 7412 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7413 dpll = I915_READ(dpll_reg);
7414 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7415 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7416 }
7417
7418}
7419
7420/**
7421 * intel_idle_update - adjust clocks for idleness
7422 * @work: work struct
7423 *
7424 * Either the GPU or display (or both) went idle. Check the busy status
7425 * here and adjust the CRTC and GPU clocks as necessary.
7426 */
7427static void intel_idle_update(struct work_struct *work)
7428{
7429 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
7430 idle_work);
7431 struct drm_device *dev = dev_priv->dev;
7432 struct drm_crtc *crtc;
7433 struct intel_crtc *intel_crtc;
7434
7435 if (!i915_powersave)
7436 return;
7437
7438 mutex_lock(&dev->struct_mutex);
7439
7648fa99
JB		 7440 i915_update_gfx_val(dev_priv);
7441
652c393a
JB		 7442 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7443 /* Skip inactive CRTCs */
7444 if (!crtc->fb)
7445 continue;
7446
7447 intel_crtc = to_intel_crtc(crtc);
7448 if (!intel_crtc->busy)
7449 intel_decrease_pllclock(crtc);
7450 }
7451
45ac22c8 7452
652c393a
JB		 7453 mutex_unlock(&dev->struct_mutex);
7454}
7455
7456/**
7457 * intel_mark_busy - mark the GPU and possibly the display busy
7458 * @dev: drm device
7459 * @obj: object we're operating on
7460 *
7461 * Callers can use this function to indicate that the GPU is busy processing
7462 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
7463 * buffer), we'll also mark the display as busy, so we know to increase its
7464 * clock frequency.
7465 */
05394f39 7466void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
652c393a
JB		 7467{
7468 drm_i915_private_t *dev_priv = dev->dev_private;
7469 struct drm_crtc *crtc = NULL;
7470 struct intel_framebuffer *intel_fb;
7471 struct intel_crtc *intel_crtc;
7472
5e17ee74
ZW		 7473 if (!drm_core_check_feature(dev, DRIVER_MODESET))
7474 return;
7475
18b2190c 7476 if (!dev_priv->busy)
28cf798f 7477 dev_priv->busy = true;
18b2190c 7478 else
28cf798f
CW		 7479 mod_timer(&dev_priv->idle_timer, jiffies +
7480 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
652c393a
JB		 7481
7482 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7483 if (!crtc->fb)
7484 continue;
7485
7486 intel_crtc = to_intel_crtc(crtc);
7487 intel_fb = to_intel_framebuffer(crtc->fb);
7488 if (intel_fb->obj == obj) {
7489 if (!intel_crtc->busy) {
7490 /* Non-busy -> busy, upclock */
3dec0095 7491 intel_increase_pllclock(crtc);
652c393a
JB		 7492 intel_crtc->busy = true;
7493 } else {
7494 /* Busy -> busy, put off timer */
7495 mod_timer(&intel_crtc->idle_timer, jiffies +
7496 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7497 }
7498 }
7499 }
7500}
7501
79e53945
JB		 7502static void intel_crtc_destroy(struct drm_crtc *crtc)
7503{
7504 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7505 struct drm_device *dev = crtc->dev;
7506 struct intel_unpin_work *work;
7507 unsigned long flags;
7508
7509 spin_lock_irqsave(&dev->event_lock, flags);
7510 work = intel_crtc->unpin_work;
7511 intel_crtc->unpin_work = NULL;
7512 spin_unlock_irqrestore(&dev->event_lock, flags);
7513
7514 if (work) {
7515 cancel_work_sync(&work->work);
7516 kfree(work);
7517 }
79e53945
JB		 7518
7519 drm_crtc_cleanup(crtc);
67e77c5a 7520
79e53945
JB		 7521 kfree(intel_crtc);
7522}
7523
6b95a207
KH		 7524static void intel_unpin_work_fn(struct work_struct *__work)
7525{
7526 struct intel_unpin_work *work =
7527 container_of(__work, struct intel_unpin_work, work);
7528
7529 mutex_lock(&work->dev->struct_mutex);
1690e1eb 7530 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7531 drm_gem_object_unreference(&work->pending_flip_obj->base);
7532 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7533
7782de3b 7534 intel_update_fbc(work->dev);
6b95a207
KH		 7535 mutex_unlock(&work->dev->struct_mutex);
7536 kfree(work);
7537}
7538
1afe3e9d 7539static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7540 struct drm_crtc *crtc)
6b95a207
KH		 7541{
7542 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7543 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7544 struct intel_unpin_work *work;
05394f39 7545 struct drm_i915_gem_object *obj;
6b95a207 7546 struct drm_pending_vblank_event *e;
49b14a5c 7547 struct timeval tnow, tvbl;
6b95a207
KH		 7548 unsigned long flags;
7549
7550 /* Ignore early vblank irqs */
7551 if (intel_crtc == NULL)
7552 return;
7553
49b14a5c
MK		 7554 do_gettimeofday(&tnow);
7555
6b95a207
KH		 7556 spin_lock_irqsave(&dev->event_lock, flags);
7557 work = intel_crtc->unpin_work;
7558 if (work == NULL || !work->pending) {
7559 spin_unlock_irqrestore(&dev->event_lock, flags);
7560 return;
7561 }
7562
7563 intel_crtc->unpin_work = NULL;
6b95a207
KH		 7564
7565 if (work->event) {
7566 e = work->event;
49b14a5c 7567 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 7568
7569 /* Called before vblank count and timestamps have
7570 * been updated for the vblank interval of flip
7571 * completion? Need to increment vblank count and
7572 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 7573 * to account for this. We assume this happened if we
7574 * get called over 0.9 frame durations after the last
7575 * timestamped vblank.
7576 *
7577 * This calculation can not be used with vrefresh rates
7578 * below 5Hz (10Hz to be on the safe side) without
7579 * promoting to 64 integers.
0af7e4df 7580 */
49b14a5c
MK		 7581 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
7582 9 * crtc->framedur_ns) {
0af7e4df 7583 e->event.sequence++;
49b14a5c
MK		 7584 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
7585 crtc->framedur_ns);
0af7e4df
MK		 7586 }
7587
49b14a5c
MK		 7588 e->event.tv_sec = tvbl.tv_sec;
7589 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 7590
6b95a207
KH		 7591 list_add_tail(&e->base.link,
7592 &e->base.file_priv->event_list);
7593 wake_up_interruptible(&e->base.file_priv->event_wait);
7594 }
7595
0af7e4df
MK		 7596 drm_vblank_put(dev, intel_crtc->pipe);
7597
6b95a207
KH		 7598 spin_unlock_irqrestore(&dev->event_lock, flags);
7599
05394f39 7600 obj = work->old_fb_obj;
d9e86c0e 7601
e59f2bac 7602 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 7603 &obj->pending_flip.counter);
7604 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 7605 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 7606
6b95a207 7607 schedule_work(&work->work);
e5510fac
JB		 7608
7609 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7610}
7611
1afe3e9d
JB		 7612void intel_finish_page_flip(struct drm_device *dev, int pipe)
7613{
7614 drm_i915_private_t *dev_priv = dev->dev_private;
7615 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7616
49b14a5c 7617 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7618}
7619
7620void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7621{
7622 drm_i915_private_t *dev_priv = dev->dev_private;
7623 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7624
49b14a5c 7625 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7626}
7627
6b95a207
KH		 7628void intel_prepare_page_flip(struct drm_device *dev, int plane)
7629{
7630 drm_i915_private_t *dev_priv = dev->dev_private;
7631 struct intel_crtc *intel_crtc =
7632 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7633 unsigned long flags;
7634
7635 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 7636 if (intel_crtc->unpin_work) {
4e5359cd
SF		 7637 if ((++intel_crtc->unpin_work->pending) > 1)
7638 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 7639 } else {
7640 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
7641 }
6b95a207
KH		 7642 spin_unlock_irqrestore(&dev->event_lock, flags);
7643}
7644
8c9f3aaf
JB		 7645static int intel_gen2_queue_flip(struct drm_device *dev,
7646 struct drm_crtc *crtc,
7647 struct drm_framebuffer *fb,
7648 struct drm_i915_gem_object *obj)
7649{
7650 struct drm_i915_private *dev_priv = dev->dev_private;
7651 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7652 unsigned long offset;
7653 u32 flip_mask;
7654 int ret;
7655
7656 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7657 if (ret)
83d4092b 7658 goto err;
8c9f3aaf
JB		 7659
7660 /* Offset into the new buffer for cases of shared fbs between CRTCs */
01f2c773 7661 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
8c9f3aaf
JB		 7662
7663 ret = BEGIN_LP_RING(6);
7664 if (ret)
83d4092b 7665 goto err_unpin;
8c9f3aaf
JB		 7666
7667 /* Can't queue multiple flips, so wait for the previous
7668 * one to finish before executing the next.
7669 */
7670 if (intel_crtc->plane)
7671 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7672 else
7673 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7674 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7675 OUT_RING(MI_NOOP);
7676 OUT_RING(MI_DISPLAY_FLIP |
7677 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
01f2c773 7678 OUT_RING(fb->pitches[0]);
8c9f3aaf 7679 OUT_RING(obj->gtt_offset + offset);
c6a32fcb 7680 OUT_RING(0); /* aux display base address, unused */
8c9f3aaf 7681 ADVANCE_LP_RING();
83d4092b
CW		 7682 return 0;
7683
7684err_unpin:
7685 intel_unpin_fb_obj(obj);
7686err:
8c9f3aaf
JB		 7687 return ret;
7688}
7689
7690static int intel_gen3_queue_flip(struct drm_device *dev,
7691 struct drm_crtc *crtc,
7692 struct drm_framebuffer *fb,
7693 struct drm_i915_gem_object *obj)
7694{
7695 struct drm_i915_private *dev_priv = dev->dev_private;
7696 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7697 unsigned long offset;
7698 u32 flip_mask;
7699 int ret;
7700
7701 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7702 if (ret)
83d4092b 7703 goto err;
8c9f3aaf
JB		 7704
7705 /* Offset into the new buffer for cases of shared fbs between CRTCs */
01f2c773 7706 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
8c9f3aaf
JB		 7707
7708 ret = BEGIN_LP_RING(6);
7709 if (ret)
83d4092b 7710 goto err_unpin;
8c9f3aaf
JB		 7711
7712 if (intel_crtc->plane)
7713 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7714 else
7715 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7716 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7717 OUT_RING(MI_NOOP);
7718 OUT_RING(MI_DISPLAY_FLIP_I915 |
7719 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
01f2c773 7720 OUT_RING(fb->pitches[0]);
8c9f3aaf
JB		 7721 OUT_RING(obj->gtt_offset + offset);
7722 OUT_RING(MI_NOOP);
7723
7724 ADVANCE_LP_RING();
83d4092b
CW		 7725 return 0;
7726
7727err_unpin:
7728 intel_unpin_fb_obj(obj);
7729err:
8c9f3aaf
JB		 7730 return ret;
7731}
7732
7733static int intel_gen4_queue_flip(struct drm_device *dev,
7734 struct drm_crtc *crtc,
7735 struct drm_framebuffer *fb,
7736 struct drm_i915_gem_object *obj)
7737{
7738 struct drm_i915_private *dev_priv = dev->dev_private;
7739 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7740 uint32_t pf, pipesrc;
7741 int ret;
7742
7743 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7744 if (ret)
83d4092b 7745 goto err;
8c9f3aaf
JB		 7746
7747 ret = BEGIN_LP_RING(4);
7748 if (ret)
83d4092b 7749 goto err_unpin;
8c9f3aaf
JB		 7750
7751 /* i965+ uses the linear or tiled offsets from the
7752 * Display Registers (which do not change across a page-flip)
7753 * so we need only reprogram the base address.
7754 */
7755 OUT_RING(MI_DISPLAY_FLIP |
7756 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
01f2c773 7757 OUT_RING(fb->pitches[0]);
8c9f3aaf
JB		 7758 OUT_RING(obj->gtt_offset | obj->tiling_mode);
7759
7760 /* XXX Enabling the panel-fitter across page-flip is so far
7761 * untested on non-native modes, so ignore it for now.
7762 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7763 */
7764 pf = 0;
7765 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7766 OUT_RING(pf | pipesrc);
7767 ADVANCE_LP_RING();
83d4092b
CW		 7768 return 0;
7769
7770err_unpin:
7771 intel_unpin_fb_obj(obj);
7772err:
8c9f3aaf
JB		 7773 return ret;
7774}
7775
7776static int intel_gen6_queue_flip(struct drm_device *dev,
7777 struct drm_crtc *crtc,
7778 struct drm_framebuffer *fb,
7779 struct drm_i915_gem_object *obj)
7780{
7781 struct drm_i915_private *dev_priv = dev->dev_private;
7782 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7783 uint32_t pf, pipesrc;
7784 int ret;
7785
7786 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7787 if (ret)
83d4092b 7788 goto err;
8c9f3aaf
JB		 7789
7790 ret = BEGIN_LP_RING(4);
7791 if (ret)
83d4092b 7792 goto err_unpin;
8c9f3aaf
JB		 7793
7794 OUT_RING(MI_DISPLAY_FLIP |
7795 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
01f2c773 7796 OUT_RING(fb->pitches[0] | obj->tiling_mode);
8c9f3aaf
JB		 7797 OUT_RING(obj->gtt_offset);
7798
7799 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7800 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7801 OUT_RING(pf | pipesrc);
7802 ADVANCE_LP_RING();
83d4092b
CW		 7803 return 0;
7804
7805err_unpin:
7806 intel_unpin_fb_obj(obj);
7807err:
8c9f3aaf
JB		 7808 return ret;
7809}
7810
7c9017e5
JB		 7811/*
7812 * On gen7 we currently use the blit ring because (in early silicon at least)
7813 * the render ring doesn't give us interrpts for page flip completion, which
7814 * means clients will hang after the first flip is queued. Fortunately the
7815 * blit ring generates interrupts properly, so use it instead.
7816 */
7817static int intel_gen7_queue_flip(struct drm_device *dev,
7818 struct drm_crtc *crtc,
7819 struct drm_framebuffer *fb,
7820 struct drm_i915_gem_object *obj)
7821{
7822 struct drm_i915_private *dev_priv = dev->dev_private;
7823 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7824 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7825 int ret;
7826
7827 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7828 if (ret)
83d4092b 7829 goto err;
7c9017e5
JB		 7830
7831 ret = intel_ring_begin(ring, 4);
7832 if (ret)
83d4092b 7833 goto err_unpin;
7c9017e5
JB		 7834
7835 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
01f2c773 7836 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7c9017e5
JB		 7837 intel_ring_emit(ring, (obj->gtt_offset));
7838 intel_ring_emit(ring, (MI_NOOP));
7839 intel_ring_advance(ring);
83d4092b
CW		 7840 return 0;
7841
7842err_unpin:
7843 intel_unpin_fb_obj(obj);
7844err:
7c9017e5
JB		 7845 return ret;
7846}
7847
8c9f3aaf
JB		 7848static int intel_default_queue_flip(struct drm_device *dev,
7849 struct drm_crtc *crtc,
7850 struct drm_framebuffer *fb,
7851 struct drm_i915_gem_object *obj)
7852{
7853 return -ENODEV;
7854}
7855
6b95a207
KH		 7856static int intel_crtc_page_flip(struct drm_crtc *crtc,
7857 struct drm_framebuffer *fb,
7858 struct drm_pending_vblank_event *event)
7859{
7860 struct drm_device *dev = crtc->dev;
7861 struct drm_i915_private *dev_priv = dev->dev_private;
7862 struct intel_framebuffer *intel_fb;
05394f39 7863 struct drm_i915_gem_object *obj;
6b95a207
KH		 7864 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7865 struct intel_unpin_work *work;
8c9f3aaf 7866 unsigned long flags;
52e68630 7867 int ret;
6b95a207
KH		 7868
7869 work = kzalloc(sizeof *work, GFP_KERNEL);
7870 if (work == NULL)
7871 return -ENOMEM;
7872
6b95a207
KH		 7873 work->event = event;
7874 work->dev = crtc->dev;
7875 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 7876 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 7877 INIT_WORK(&work->work, intel_unpin_work_fn);
7878
7317c75e
JB		 7879 ret = drm_vblank_get(dev, intel_crtc->pipe);
7880 if (ret)
7881 goto free_work;
7882
6b95a207
KH		 7883 /* We borrow the event spin lock for protecting unpin_work */
7884 spin_lock_irqsave(&dev->event_lock, flags);
7885 if (intel_crtc->unpin_work) {
7886 spin_unlock_irqrestore(&dev->event_lock, flags);
7887 kfree(work);
7317c75e 7888 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7889
7890 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7891 return -EBUSY;
7892 }
7893 intel_crtc->unpin_work = work;
7894 spin_unlock_irqrestore(&dev->event_lock, flags);
7895
7896 intel_fb = to_intel_framebuffer(fb);
7897 obj = intel_fb->obj;
7898
468f0b44 7899 mutex_lock(&dev->struct_mutex);
6b95a207 7900
75dfca80 7901 /* Reference the objects for the scheduled work. */
05394f39
CW		 7902 drm_gem_object_reference(&work->old_fb_obj->base);
7903 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7904
7905 crtc->fb = fb;
96b099fd 7906
e1f99ce6 7907 work->pending_flip_obj = obj;
e1f99ce6 7908
4e5359cd
SF		 7909 work->enable_stall_check = true;
7910
e1f99ce6
CW		 7911 /* Block clients from rendering to the new back buffer until
7912 * the flip occurs and the object is no longer visible.
7913 */
05394f39 7914 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 7915
8c9f3aaf
JB		 7916 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7917 if (ret)
7918 goto cleanup_pending;
6b95a207 7919
7782de3b 7920 intel_disable_fbc(dev);
6b95a207
KH		 7921 mutex_unlock(&dev->struct_mutex);
7922
e5510fac
JB		 7923 trace_i915_flip_request(intel_crtc->plane, obj);
7924
6b95a207 7925 return 0;
96b099fd 7926
8c9f3aaf
JB		 7927cleanup_pending:
7928 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 7929 drm_gem_object_unreference(&work->old_fb_obj->base);
7930 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7931 mutex_unlock(&dev->struct_mutex);
7932
7933 spin_lock_irqsave(&dev->event_lock, flags);
7934 intel_crtc->unpin_work = NULL;
7935 spin_unlock_irqrestore(&dev->event_lock, flags);
7936
7317c75e
JB		 7937 drm_vblank_put(dev, intel_crtc->pipe);
7938free_work:
96b099fd
CW		 7939 kfree(work);
7940
7941 return ret;
6b95a207
KH		 7942}
7943
47f1c6c9
CW		 7944static void intel_sanitize_modesetting(struct drm_device *dev,
7945 int pipe, int plane)
7946{
7947 struct drm_i915_private *dev_priv = dev->dev_private;
7948 u32 reg, val;
7949
f47166d2
CW		 7950 /* Clear any frame start delays used for debugging left by the BIOS */
7951 for_each_pipe(pipe) {
7952 reg = PIPECONF(pipe);
7953 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
7954 }
7955
47f1c6c9
CW		 7956 if (HAS_PCH_SPLIT(dev))
7957 return;
7958
7959 /* Who knows what state these registers were left in by the BIOS or
7960 * grub?
7961 *
7962 * If we leave the registers in a conflicting state (e.g. with the
7963 * display plane reading from the other pipe than the one we intend
7964 * to use) then when we attempt to teardown the active mode, we will
7965 * not disable the pipes and planes in the correct order -- leaving
7966 * a plane reading from a disabled pipe and possibly leading to
7967 * undefined behaviour.
7968 */
7969
7970 reg = DSPCNTR(plane);
7971 val = I915_READ(reg);
7972
7973 if ((val & DISPLAY_PLANE_ENABLE) == 0)
7974 return;
7975 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7976 return;
7977
7978 /* This display plane is active and attached to the other CPU pipe. */
7979 pipe = !pipe;
7980
7981 /* Disable the plane and wait for it to stop reading from the pipe. */
b24e7179
JB		 7982 intel_disable_plane(dev_priv, plane, pipe);
7983 intel_disable_pipe(dev_priv, pipe);
47f1c6c9 7984}
79e53945 7985
f6e5b160
CW		 7986static void intel_crtc_reset(struct drm_crtc *crtc)
7987{
7988 struct drm_device *dev = crtc->dev;
7989 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7990
7991 /* Reset flags back to the 'unknown' status so that they
7992 * will be correctly set on the initial modeset.
7993 */
7994 intel_crtc->dpms_mode = -1;
7995
7996 /* We need to fix up any BIOS configuration that conflicts with
7997 * our expectations.
7998 */
7999 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
8000}
8001
8002static struct drm_crtc_helper_funcs intel_helper_funcs = {
8003 .dpms = intel_crtc_dpms,
8004 .mode_fixup = intel_crtc_mode_fixup,
8005 .mode_set = intel_crtc_mode_set,
8006 .mode_set_base = intel_pipe_set_base,
8007 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8008 .load_lut = intel_crtc_load_lut,
8009 .disable = intel_crtc_disable,
8010};
8011
8012static const struct drm_crtc_funcs intel_crtc_funcs = {
8013 .reset = intel_crtc_reset,
8014 .cursor_set = intel_crtc_cursor_set,
8015 .cursor_move = intel_crtc_cursor_move,
8016 .gamma_set = intel_crtc_gamma_set,
8017 .set_config = drm_crtc_helper_set_config,
8018 .destroy = intel_crtc_destroy,
8019 .page_flip = intel_crtc_page_flip,
8020};
8021
b358d0a6 8022static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8023{
22fd0fab 8024 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8025 struct intel_crtc *intel_crtc;
8026 int i;
8027
8028 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8029 if (intel_crtc == NULL)
8030 return;
8031
8032 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8033
8034 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8035 for (i = 0; i < 256; i++) {
8036 intel_crtc->lut_r[i] = i;
8037 intel_crtc->lut_g[i] = i;
8038 intel_crtc->lut_b[i] = i;
8039 }
8040
80824003
JB		 8041 /* Swap pipes & planes for FBC on pre-965 */
8042 intel_crtc->pipe = pipe;
8043 intel_crtc->plane = pipe;
e2e767ab 8044 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8045 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8046 intel_crtc->plane = !pipe;
80824003
JB		 8047 }
8048
22fd0fab
JB		 8049 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8050 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8051 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8052 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8053
5d1d0cc8 8054 intel_crtc_reset(&intel_crtc->base);
04dbff52 8055 intel_crtc->active = true; /* force the pipe off on setup_init_config */
5a354204 8056 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3
JB		 8057
8058 if (HAS_PCH_SPLIT(dev)) {
4b645f14
JB		 8059 if (pipe == 2 && IS_IVYBRIDGE(dev))
8060 intel_crtc->no_pll = true;
7e7d76c3
JB		 8061 intel_helper_funcs.prepare = ironlake_crtc_prepare;
8062 intel_helper_funcs.commit = ironlake_crtc_commit;
8063 } else {
8064 intel_helper_funcs.prepare = i9xx_crtc_prepare;
8065 intel_helper_funcs.commit = i9xx_crtc_commit;
8066 }
8067
79e53945
JB		 8068 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8069
652c393a
JB		 8070 intel_crtc->busy = false;
8071
8072 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
8073 (unsigned long)intel_crtc);
79e53945
JB		 8074}
8075
08d7b3d1 8076int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8077 struct drm_file *file)
08d7b3d1
CW		 8078{
8079 drm_i915_private_t *dev_priv = dev->dev_private;
8080 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8081 struct drm_mode_object *drmmode_obj;
8082 struct intel_crtc *crtc;
08d7b3d1
CW		 8083
8084 if (!dev_priv) {
8085 DRM_ERROR("called with no initialization\n");
8086 return -EINVAL;
8087 }
8088
c05422d5
DV		 8089 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8090 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8091
c05422d5 8092 if (!drmmode_obj) {
08d7b3d1
CW		 8093 DRM_ERROR("no such CRTC id\n");
8094 return -EINVAL;
8095 }
8096
c05422d5
DV		 8097 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8098 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8099
c05422d5 8100 return 0;
08d7b3d1
CW		 8101}
8102
c5e4df33 8103static int intel_encoder_clones(struct drm_device *dev, int type_mask)
79e53945 8104{
4ef69c7a 8105 struct intel_encoder *encoder;
79e53945 8106 int index_mask = 0;
79e53945
JB		 8107 int entry = 0;
8108
4ef69c7a
CW		 8109 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8110 if (type_mask & encoder->clone_mask)
79e53945
JB		 8111 index_mask |= (1 << entry);
8112 entry++;
8113 }
4ef69c7a 8114
79e53945
JB		 8115 return index_mask;
8116}
8117
4d302442
CW		 8118static bool has_edp_a(struct drm_device *dev)
8119{
8120 struct drm_i915_private *dev_priv = dev->dev_private;
8121
8122 if (!IS_MOBILE(dev))
8123 return false;
8124
8125 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8126 return false;
8127
8128 if (IS_GEN5(dev) &&
8129 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8130 return false;
8131
8132 return true;
8133}
8134
79e53945
JB		 8135static void intel_setup_outputs(struct drm_device *dev)
8136{
725e30ad 8137 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8138 struct intel_encoder *encoder;
cb0953d7 8139 bool dpd_is_edp = false;
f3cfcba6 8140 bool has_lvds;
79e53945 8141
f3cfcba6 8142 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8143 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8144 /* disable the panel fitter on everything but LVDS */
8145 I915_WRITE(PFIT_CONTROL, 0);
8146 }
79e53945 8147
bad720ff 8148 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8149 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 8150
4d302442 8151 if (has_edp_a(dev))
32f9d658
ZW		 8152 intel_dp_init(dev, DP_A);
8153
cb0953d7
AJ		 8154 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
8155 intel_dp_init(dev, PCH_DP_D);
8156 }
8157
8158 intel_crt_init(dev);
8159
8160 if (HAS_PCH_SPLIT(dev)) {
8161 int found;
8162
30ad48b7 8163 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 8164 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8165 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7
ZW		 8166 if (!found)
8167 intel_hdmi_init(dev, HDMIB);
5eb08b69
ZW		 8168 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8169 intel_dp_init(dev, PCH_DP_B);
30ad48b7
ZW		 8170 }
8171
8172 if (I915_READ(HDMIC) & PORT_DETECTED)
8173 intel_hdmi_init(dev, HDMIC);
8174
8175 if (I915_READ(HDMID) & PORT_DETECTED)
8176 intel_hdmi_init(dev, HDMID);
8177
5eb08b69
ZW		 8178 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8179 intel_dp_init(dev, PCH_DP_C);
8180
cb0953d7 8181 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5eb08b69
ZW		 8182 intel_dp_init(dev, PCH_DP_D);
8183
103a196f 8184 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8185 bool found = false;
7d57382e 8186
725e30ad 8187 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 8188 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 8189 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 8190 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8191 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
725e30ad 8192 intel_hdmi_init(dev, SDVOB);
b01f2c3a 8193 }
27185ae1 8194
b01f2c3a
JB		 8195 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8196 DRM_DEBUG_KMS("probing DP_B\n");
a4fc5ed6 8197 intel_dp_init(dev, DP_B);
b01f2c3a 8198 }
725e30ad 8199 }
13520b05
KH		 8200
8201 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8202
b01f2c3a
JB		 8203 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8204 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 8205 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 8206 }
27185ae1
ML		 8207
8208 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8209
b01f2c3a
JB		 8210 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8211 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
725e30ad 8212 intel_hdmi_init(dev, SDVOC);
b01f2c3a
JB		 8213 }
8214 if (SUPPORTS_INTEGRATED_DP(dev)) {
8215 DRM_DEBUG_KMS("probing DP_C\n");
a4fc5ed6 8216 intel_dp_init(dev, DP_C);
b01f2c3a 8217 }
725e30ad 8218 }
27185ae1 8219
b01f2c3a
JB		 8220 if (SUPPORTS_INTEGRATED_DP(dev) &&
8221 (I915_READ(DP_D) & DP_DETECTED)) {
8222 DRM_DEBUG_KMS("probing DP_D\n");
a4fc5ed6 8223 intel_dp_init(dev, DP_D);
b01f2c3a 8224 }
bad720ff 8225 } else if (IS_GEN2(dev))
79e53945
JB		 8226 intel_dvo_init(dev);
8227
103a196f 8228 if (SUPPORTS_TV(dev))
79e53945
JB		 8229 intel_tv_init(dev);
8230
4ef69c7a
CW		 8231 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8232 encoder->base.possible_crtcs = encoder->crtc_mask;
8233 encoder->base.possible_clones =
8234 intel_encoder_clones(dev, encoder->clone_mask);
79e53945 8235 }
47356eb6 8236
2c7111db
CW		 8237 /* disable all the possible outputs/crtcs before entering KMS mode */
8238 drm_helper_disable_unused_functions(dev);
9fb526db
KP		 8239
8240 if (HAS_PCH_SPLIT(dev))
8241 ironlake_init_pch_refclk(dev);
79e53945
JB		 8242}
8243
8244static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8245{
8246 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8247
8248 drm_framebuffer_cleanup(fb);
05394f39 8249 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8250
8251 kfree(intel_fb);
8252}
8253
8254static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8255 struct drm_file *file,
79e53945
JB		 8256 unsigned int *handle)
8257{
8258 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8259 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8260
05394f39 8261 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8262}
8263
8264static const struct drm_framebuffer_funcs intel_fb_funcs = {
8265 .destroy = intel_user_framebuffer_destroy,
8266 .create_handle = intel_user_framebuffer_create_handle,
8267};
8268
38651674
DA		 8269int intel_framebuffer_init(struct drm_device *dev,
8270 struct intel_framebuffer *intel_fb,
308e5bcb 8271 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8272 struct drm_i915_gem_object *obj)
79e53945 8273{
79e53945
JB		 8274 int ret;
8275
05394f39 8276 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 8277 return -EINVAL;
8278
308e5bcb 8279 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 8280 return -EINVAL;
8281
308e5bcb 8282 switch (mode_cmd->pixel_format) {
04b3924d
VS		 8283 case DRM_FORMAT_RGB332:
8284 case DRM_FORMAT_RGB565:
8285 case DRM_FORMAT_XRGB8888:
b250da79 8286 case DRM_FORMAT_XBGR8888:
04b3924d
VS		 8287 case DRM_FORMAT_ARGB8888:
8288 case DRM_FORMAT_XRGB2101010:
8289 case DRM_FORMAT_ARGB2101010:
308e5bcb 8290 /* RGB formats are common across chipsets */
b5626747 8291 break;
04b3924d
VS		 8292 case DRM_FORMAT_YUYV:
8293 case DRM_FORMAT_UYVY:
8294 case DRM_FORMAT_YVYU:
8295 case DRM_FORMAT_VYUY:
57cd6508
CW		 8296 break;
8297 default:
aca25848
ED		 8298 DRM_DEBUG_KMS("unsupported pixel format %u\n",
8299 mode_cmd->pixel_format);
57cd6508
CW		 8300 return -EINVAL;
8301 }
8302
79e53945
JB		 8303 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8304 if (ret) {
8305 DRM_ERROR("framebuffer init failed %d\n", ret);
8306 return ret;
8307 }
8308
8309 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 8310 intel_fb->obj = obj;
79e53945
JB		 8311 return 0;
8312}
8313
79e53945
JB		 8314static struct drm_framebuffer *
8315intel_user_framebuffer_create(struct drm_device *dev,
8316 struct drm_file *filp,
308e5bcb 8317 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8318{
05394f39 8319 struct drm_i915_gem_object *obj;
79e53945 8320
308e5bcb
JB		 8321 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8322 mode_cmd->handles[0]));
c8725226 8323 if (&obj->base == NULL)
cce13ff7 8324 return ERR_PTR(-ENOENT);
79e53945 8325
d2dff872 8326 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8327}
8328
79e53945 8329static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8330 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8331 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8332};
8333
05394f39 8334static struct drm_i915_gem_object *
aa40d6bb 8335intel_alloc_context_page(struct drm_device *dev)
9ea8d059 8336{
05394f39 8337 struct drm_i915_gem_object *ctx;
9ea8d059
CW		 8338 int ret;
8339
2c34b850
BW		 8340 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
8341
aa40d6bb
ZN		 8342 ctx = i915_gem_alloc_object(dev, 4096);
8343 if (!ctx) {
9ea8d059
CW		 8344 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
8345 return NULL;
8346 }
8347
75e9e915 8348 ret = i915_gem_object_pin(ctx, 4096, true);
9ea8d059
CW		 8349 if (ret) {
8350 DRM_ERROR("failed to pin power context: %d\n", ret);
8351 goto err_unref;
8352 }
8353
aa40d6bb 8354 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
9ea8d059
CW		 8355 if (ret) {
8356 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
8357 goto err_unpin;
8358 }
9ea8d059 8359
aa40d6bb 8360 return ctx;
9ea8d059
CW		 8361
8362err_unpin:
aa40d6bb 8363 i915_gem_object_unpin(ctx);
9ea8d059 8364err_unref:
05394f39 8365 drm_gem_object_unreference(&ctx->base);
9ea8d059
CW		 8366 mutex_unlock(&dev->struct_mutex);
8367 return NULL;
8368}
8369
7648fa99
JB		 8370bool ironlake_set_drps(struct drm_device *dev, u8 val)
8371{
8372 struct drm_i915_private *dev_priv = dev->dev_private;
8373 u16 rgvswctl;
8374
8375 rgvswctl = I915_READ16(MEMSWCTL);
8376 if (rgvswctl & MEMCTL_CMD_STS) {
8377 DRM_DEBUG("gpu busy, RCS change rejected\n");
8378 return false; /* still busy with another command */
8379 }
8380
8381 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
8382 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
8383 I915_WRITE16(MEMSWCTL, rgvswctl);
8384 POSTING_READ16(MEMSWCTL);
8385
8386 rgvswctl |= MEMCTL_CMD_STS;
8387 I915_WRITE16(MEMSWCTL, rgvswctl);
8388
8389 return true;
8390}
8391
f97108d1
JB		 8392void ironlake_enable_drps(struct drm_device *dev)
8393{
8394 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 8395 u32 rgvmodectl = I915_READ(MEMMODECTL);
f97108d1 8396 u8 fmax, fmin, fstart, vstart;
f97108d1 8397
ea056c14
JB		 8398 /* Enable temp reporting */
8399 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
8400 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
8401
f97108d1
JB		 8402 /* 100ms RC evaluation intervals */
8403 I915_WRITE(RCUPEI, 100000);
8404 I915_WRITE(RCDNEI, 100000);
8405
8406 /* Set max/min thresholds to 90ms and 80ms respectively */
8407 I915_WRITE(RCBMAXAVG, 90000);
8408 I915_WRITE(RCBMINAVG, 80000);
8409
8410 I915_WRITE(MEMIHYST, 1);
8411
8412 /* Set up min, max, and cur for interrupt handling */
8413 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
8414 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
8415 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
8416 MEMMODE_FSTART_SHIFT;
7648fa99 8417
f97108d1
JB		 8418 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
8419 PXVFREQ_PX_SHIFT;
8420
80dbf4b7 8421 dev_priv->fmax = fmax; /* IPS callback will increase this */
7648fa99
JB		 8422 dev_priv->fstart = fstart;
8423
80dbf4b7 8424 dev_priv->max_delay = fstart;
f97108d1
JB		 8425 dev_priv->min_delay = fmin;
8426 dev_priv->cur_delay = fstart;
8427
80dbf4b7
JB		 8428 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
8429 fmax, fmin, fstart);
7648fa99 8430
f97108d1
JB		 8431 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
8432
8433 /*
8434 * Interrupts will be enabled in ironlake_irq_postinstall
8435 */
8436
8437 I915_WRITE(VIDSTART, vstart);
8438 POSTING_READ(VIDSTART);
8439
8440 rgvmodectl |= MEMMODE_SWMODE_EN;
8441 I915_WRITE(MEMMODECTL, rgvmodectl);
8442
481b6af3 8443 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
913d8d11 8444 DRM_ERROR("stuck trying to change perf mode\n");
f97108d1
JB		 8445 msleep(1);
8446
7648fa99 8447 ironlake_set_drps(dev, fstart);
f97108d1 8448
7648fa99
JB		 8449 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
8450 I915_READ(0x112e0);
8451 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
8452 dev_priv->last_count2 = I915_READ(0x112f4);
8453 getrawmonotonic(&dev_priv->last_time2);
f97108d1
JB		 8454}
8455
8456void ironlake_disable_drps(struct drm_device *dev)
8457{
8458 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 8459 u16 rgvswctl = I915_READ16(MEMSWCTL);
f97108d1
JB		 8460
8461 /* Ack interrupts, disable EFC interrupt */
8462 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
8463 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
8464 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
8465 I915_WRITE(DEIIR, DE_PCU_EVENT);
8466 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
8467
8468 /* Go back to the starting frequency */
7648fa99 8469 ironlake_set_drps(dev, dev_priv->fstart);
f97108d1
JB		 8470 msleep(1);
8471 rgvswctl |= MEMCTL_CMD_STS;
8472 I915_WRITE(MEMSWCTL, rgvswctl);
8473 msleep(1);
8474
8475}
8476
3b8d8d91
JB		 8477void gen6_set_rps(struct drm_device *dev, u8 val)
8478{
8479 struct drm_i915_private *dev_priv = dev->dev_private;
8480 u32 swreq;
8481
8482 swreq = (val & 0x3ff) << 25;
8483 I915_WRITE(GEN6_RPNSWREQ, swreq);
8484}
8485
8486void gen6_disable_rps(struct drm_device *dev)
8487{
8488 struct drm_i915_private *dev_priv = dev->dev_private;
8489
8490 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
8491 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
8492 I915_WRITE(GEN6_PMIER, 0);
6fdd4d98
DV		 8493 /* Complete PM interrupt masking here doesn't race with the rps work
8494 * item again unmasking PM interrupts because that is using a different
8495 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
8496 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
4912d041
BW		 8497
8498 spin_lock_irq(&dev_priv->rps_lock);
8499 dev_priv->pm_iir = 0;
8500 spin_unlock_irq(&dev_priv->rps_lock);
8501
3b8d8d91
JB		 8502 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
8503}
8504
7648fa99
JB		 8505static unsigned long intel_pxfreq(u32 vidfreq)
8506{
8507 unsigned long freq;
8508 int div = (vidfreq & 0x3f0000) >> 16;
8509 int post = (vidfreq & 0x3000) >> 12;
8510 int pre = (vidfreq & 0x7);
8511
8512 if (!pre)
8513 return 0;
8514
8515 freq = ((div * 133333) / ((1<<post) * pre));
8516
8517 return freq;
8518}
8519
8520void intel_init_emon(struct drm_device *dev)
8521{
8522 struct drm_i915_private *dev_priv = dev->dev_private;
8523 u32 lcfuse;
8524 u8 pxw[16];
8525 int i;
8526
8527 /* Disable to program */
8528 I915_WRITE(ECR, 0);
8529 POSTING_READ(ECR);
8530
8531 /* Program energy weights for various events */
8532 I915_WRITE(SDEW, 0x15040d00);
8533 I915_WRITE(CSIEW0, 0x007f0000);
8534 I915_WRITE(CSIEW1, 0x1e220004);
8535 I915_WRITE(CSIEW2, 0x04000004);
8536
8537 for (i = 0; i < 5; i++)
8538 I915_WRITE(PEW + (i * 4), 0);
8539 for (i = 0; i < 3; i++)
8540 I915_WRITE(DEW + (i * 4), 0);
8541
8542 /* Program P-state weights to account for frequency power adjustment */
8543 for (i = 0; i < 16; i++) {
8544 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
8545 unsigned long freq = intel_pxfreq(pxvidfreq);
8546 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
8547 PXVFREQ_PX_SHIFT;
8548 unsigned long val;
8549
8550 val = vid * vid;
8551 val *= (freq / 1000);
8552 val *= 255;
8553 val /= (127*127*900);
8554 if (val > 0xff)
8555 DRM_ERROR("bad pxval: %ld\n", val);
8556 pxw[i] = val;
8557 }
8558 /* Render standby states get 0 weight */
8559 pxw[14] = 0;
8560 pxw[15] = 0;
8561
8562 for (i = 0; i < 4; i++) {
8563 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
8564 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
8565 I915_WRITE(PXW + (i * 4), val);
8566 }
8567
8568 /* Adjust magic regs to magic values (more experimental results) */
8569 I915_WRITE(OGW0, 0);
8570 I915_WRITE(OGW1, 0);
8571 I915_WRITE(EG0, 0x00007f00);
8572 I915_WRITE(EG1, 0x0000000e);
8573 I915_WRITE(EG2, 0x000e0000);
8574 I915_WRITE(EG3, 0x68000300);
8575 I915_WRITE(EG4, 0x42000000);
8576 I915_WRITE(EG5, 0x00140031);
8577 I915_WRITE(EG6, 0);
8578 I915_WRITE(EG7, 0);
8579
8580 for (i = 0; i < 8; i++)
8581 I915_WRITE(PXWL + (i * 4), 0);
8582
8583 /* Enable PMON + select events */
8584 I915_WRITE(ECR, 0x80000019);
8585
8586 lcfuse = I915_READ(LCFUSE02);
8587
8588 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
8589}
8590
0136db58 8591int intel_enable_rc6(const struct drm_device *dev)
c0f372b3
KP		 8592{
8593 /*
8594 * Respect the kernel parameter if it is set
8595 */
8596 if (i915_enable_rc6 >= 0)
8597 return i915_enable_rc6;
8598
8599 /*
8600 * Disable RC6 on Ironlake
8601 */
8602 if (INTEL_INFO(dev)->gen == 5)
8603 return 0;
8604
83de97c8
ED		 8605 /* Sorry Haswell, no RC6 for you for now. */
8606 if (IS_HASWELL(dev))
8607 return 0;
8608
c0f372b3 8609 /*
371de6e4 8610 * Disable rc6 on Sandybridge
c0f372b3
KP		 8611 */
8612 if (INTEL_INFO(dev)->gen == 6) {
aa464191
ED		 8613 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
8614 return INTEL_RC6_ENABLE;
c0f372b3 8615 }
aa464191
ED		 8616 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
8617 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
c0f372b3
KP		 8618}
8619
3b8d8d91 8620void gen6_enable_rps(struct drm_i915_private *dev_priv)
8fd26859 8621{
a6044e23
JB		 8622 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
8623 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7df8721b 8624 u32 pcu_mbox, rc6_mask = 0;
dd202c6d 8625 u32 gtfifodbg;
a6044e23 8626 int cur_freq, min_freq, max_freq;
83b7f9ac 8627 int rc6_mode;
8fd26859
CW		 8628 int i;
8629
8630 /* Here begins a magic sequence of register writes to enable
8631 * auto-downclocking.
8632 *
8633 * Perhaps there might be some value in exposing these to
8634 * userspace...
8635 */
8636 I915_WRITE(GEN6_RC_STATE, 0);
d1ebd816 8637 mutex_lock(&dev_priv->dev->struct_mutex);
dd202c6d
BW		 8638
8639 /* Clear the DBG now so we don't confuse earlier errors */
8640 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
8641 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
8642 I915_WRITE(GTFIFODBG, gtfifodbg);
8643 }
8644
fcca7926 8645 gen6_gt_force_wake_get(dev_priv);
8fd26859 8646
3b8d8d91 8647 /* disable the counters and set deterministic thresholds */
8fd26859
CW		 8648 I915_WRITE(GEN6_RC_CONTROL, 0);
8649
8650 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
8651 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
8652 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
8653 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
8654 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
8655
8656 for (i = 0; i < I915_NUM_RINGS; i++)
8657 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
8658
8659 I915_WRITE(GEN6_RC_SLEEP, 0);
8660 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
8661 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
8662 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
8663 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
8664
83b7f9ac
ED		 8665 rc6_mode = intel_enable_rc6(dev_priv->dev);
8666 if (rc6_mode & INTEL_RC6_ENABLE)
8667 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
8668
8669 if (rc6_mode & INTEL_RC6p_ENABLE)
8670 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
8671
8672 if (rc6_mode & INTEL_RC6pp_ENABLE)
8673 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
8674
8675 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
8676 (rc6_mode & INTEL_RC6_ENABLE) ? "on" : "off",
8677 (rc6_mode & INTEL_RC6p_ENABLE) ? "on" : "off",
8678 (rc6_mode & INTEL_RC6pp_ENABLE) ? "on" : "off");
7df8721b 8679
8fd26859 8680 I915_WRITE(GEN6_RC_CONTROL,
7df8721b 8681 rc6_mask |
9c3d2f7f 8682 GEN6_RC_CTL_EI_MODE(1) |
8fd26859
CW		 8683 GEN6_RC_CTL_HW_ENABLE);
8684
3b8d8d91 8685 I915_WRITE(GEN6_RPNSWREQ,
8fd26859
CW		 8686 GEN6_FREQUENCY(10) |
8687 GEN6_OFFSET(0) |
8688 GEN6_AGGRESSIVE_TURBO);
8689 I915_WRITE(GEN6_RC_VIDEO_FREQ,
8690 GEN6_FREQUENCY(12));
8691
8692 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
8693 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
8694 18 << 24 |
8695 6 << 16);
ccab5c82
JB		 8696 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
8697 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8fd26859 8698 I915_WRITE(GEN6_RP_UP_EI, 100000);
ccab5c82 8699 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8fd26859
CW		 8700 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
8701 I915_WRITE(GEN6_RP_CONTROL,
8702 GEN6_RP_MEDIA_TURBO |
6ed55ee7 8703 GEN6_RP_MEDIA_HW_MODE |
8fd26859
CW		 8704 GEN6_RP_MEDIA_IS_GFX |
8705 GEN6_RP_ENABLE |
ccab5c82
JB		 8706 GEN6_RP_UP_BUSY_AVG |
8707 GEN6_RP_DOWN_IDLE_CONT);
8fd26859
CW		 8708
8709 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8710 500))
8711 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8712
8713 I915_WRITE(GEN6_PCODE_DATA, 0);
8714 I915_WRITE(GEN6_PCODE_MAILBOX,
8715 GEN6_PCODE_READY |
8716 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8717 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8718 500))
8719 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8720
a6044e23
JB		 8721 min_freq = (rp_state_cap & 0xff0000) >> 16;
8722 max_freq = rp_state_cap & 0xff;
8723 cur_freq = (gt_perf_status & 0xff00) >> 8;
8724
8725 /* Check for overclock support */
8726 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8727 500))
8728 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8729 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
8730 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
8731 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8732 500))
8733 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8734 if (pcu_mbox & (1<<31)) { /* OC supported */
8735 max_freq = pcu_mbox & 0xff;
e281fcaa 8736 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
a6044e23
JB		 8737 }
8738
8739 /* In units of 100MHz */
8740 dev_priv->max_delay = max_freq;
8741 dev_priv->min_delay = min_freq;
8742 dev_priv->cur_delay = cur_freq;
8743
8fd26859
CW		 8744 /* requires MSI enabled */
8745 I915_WRITE(GEN6_PMIER,
8746 GEN6_PM_MBOX_EVENT |
8747 GEN6_PM_THERMAL_EVENT |
8748 GEN6_PM_RP_DOWN_TIMEOUT |
8749 GEN6_PM_RP_UP_THRESHOLD |
8750 GEN6_PM_RP_DOWN_THRESHOLD |
8751 GEN6_PM_RP_UP_EI_EXPIRED |
8752 GEN6_PM_RP_DOWN_EI_EXPIRED);
4912d041
BW		 8753 spin_lock_irq(&dev_priv->rps_lock);
8754 WARN_ON(dev_priv->pm_iir != 0);
3b8d8d91 8755 I915_WRITE(GEN6_PMIMR, 0);
4912d041 8756 spin_unlock_irq(&dev_priv->rps_lock);
3b8d8d91
JB		 8757 /* enable all PM interrupts */
8758 I915_WRITE(GEN6_PMINTRMSK, 0);
8fd26859 8759
fcca7926 8760 gen6_gt_force_wake_put(dev_priv);
d1ebd816 8761 mutex_unlock(&dev_priv->dev->struct_mutex);
8fd26859
CW		 8762}
8763
23b2f8bb
JB		 8764void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
8765{
8766 int min_freq = 15;
8767 int gpu_freq, ia_freq, max_ia_freq;
8768 int scaling_factor = 180;
8769
8770 max_ia_freq = cpufreq_quick_get_max(0);
8771 /*
8772 * Default to measured freq if none found, PCU will ensure we don't go
8773 * over
8774 */
8775 if (!max_ia_freq)
8776 max_ia_freq = tsc_khz;
8777
8778 /* Convert from kHz to MHz */
8779 max_ia_freq /= 1000;
8780
8781 mutex_lock(&dev_priv->dev->struct_mutex);
8782
8783 /*
8784 * For each potential GPU frequency, load a ring frequency we'd like
8785 * to use for memory access. We do this by specifying the IA frequency
8786 * the PCU should use as a reference to determine the ring frequency.
8787 */
8788 for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
8789 gpu_freq--) {
8790 int diff = dev_priv->max_delay - gpu_freq;
8791
8792 /*
8793 * For GPU frequencies less than 750MHz, just use the lowest
8794 * ring freq.
8795 */
8796 if (gpu_freq < min_freq)
8797 ia_freq = 800;
8798 else
8799 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
8800 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
8801
8802 I915_WRITE(GEN6_PCODE_DATA,
8803 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
8804 gpu_freq);
8805 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
8806 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8807 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
8808 GEN6_PCODE_READY) == 0, 10)) {
8809 DRM_ERROR("pcode write of freq table timed out\n");
8810 continue;
8811 }
8812 }
8813
8814 mutex_unlock(&dev_priv->dev->struct_mutex);
8815}
8816
6067aaea
JB		 8817static void ironlake_init_clock_gating(struct drm_device *dev)
8818{
8819 struct drm_i915_private *dev_priv = dev->dev_private;
8820 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8821
8822 /* Required for FBC */
8823 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
8824 DPFCRUNIT_CLOCK_GATE_DISABLE |
8825 DPFDUNIT_CLOCK_GATE_DISABLE;
8826 /* Required for CxSR */
8827 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
8828
8829 I915_WRITE(PCH_3DCGDIS0,
8830 MARIUNIT_CLOCK_GATE_DISABLE |
8831 SVSMUNIT_CLOCK_GATE_DISABLE);
8832 I915_WRITE(PCH_3DCGDIS1,
8833 VFMUNIT_CLOCK_GATE_DISABLE);
8834
8835 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8836
6067aaea
JB		 8837 /*
8838 * According to the spec the following bits should be set in
8839 * order to enable memory self-refresh
8840 * The bit 22/21 of 0x42004
8841 * The bit 5 of 0x42020
8842 * The bit 15 of 0x45000
8843 */
8844 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8845 (I915_READ(ILK_DISPLAY_CHICKEN2) |
8846 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8847 I915_WRITE(ILK_DSPCLK_GATE,
8848 (I915_READ(ILK_DSPCLK_GATE) |
8849 ILK_DPARB_CLK_GATE));
8850 I915_WRITE(DISP_ARB_CTL,
8851 (I915_READ(DISP_ARB_CTL) |
8852 DISP_FBC_WM_DIS));
8853 I915_WRITE(WM3_LP_ILK, 0);
8854 I915_WRITE(WM2_LP_ILK, 0);
8855 I915_WRITE(WM1_LP_ILK, 0);
8856
8857 /*
8858 * Based on the document from hardware guys the following bits
8859 * should be set unconditionally in order to enable FBC.
8860 * The bit 22 of 0x42000
8861 * The bit 22 of 0x42004
8862 * The bit 7,8,9 of 0x42020.
8863 */
8864 if (IS_IRONLAKE_M(dev)) {
8865 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8866 I915_READ(ILK_DISPLAY_CHICKEN1) |
8867 ILK_FBCQ_DIS);
8868 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8869 I915_READ(ILK_DISPLAY_CHICKEN2) |
8870 ILK_DPARB_GATE);
8871 I915_WRITE(ILK_DSPCLK_GATE,
8872 I915_READ(ILK_DSPCLK_GATE) |
8873 ILK_DPFC_DIS1 |
8874 ILK_DPFC_DIS2 |
8875 ILK_CLK_FBC);
8876 }
8877
8878 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8879 I915_READ(ILK_DISPLAY_CHICKEN2) |
8880 ILK_ELPIN_409_SELECT);
8881 I915_WRITE(_3D_CHICKEN2,
8882 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8883 _3D_CHICKEN2_WM_READ_PIPELINED);
8fd26859
CW		 8884}
8885
6067aaea 8886static void gen6_init_clock_gating(struct drm_device *dev)
652c393a
JB		 8887{
8888 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 8889 int pipe;
6067aaea
JB		 8890 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8891
8892 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
652c393a 8893
6067aaea
JB		 8894 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8895 I915_READ(ILK_DISPLAY_CHICKEN2) |
8896 ILK_ELPIN_409_SELECT);
8956c8bb 8897
6067aaea
JB		 8898 I915_WRITE(WM3_LP_ILK, 0);
8899 I915_WRITE(WM2_LP_ILK, 0);
8900 I915_WRITE(WM1_LP_ILK, 0);
652c393a 8901
009be664
DV		 8902 /* clear masked bit */
8903 I915_WRITE(CACHE_MODE_0,
8904 CM0_STC_EVICT_DISABLE_LRA_SNB << CM0_MASK_SHIFT);
8905
80e829fa
DV		 8906 I915_WRITE(GEN6_UCGCTL1,
8907 I915_READ(GEN6_UCGCTL1) |
de4a8bd1
DV		 8908 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
8909 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
80e829fa 8910
406478dc
EA		 8911 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8912 * gating disable must be set. Failure to set it results in
8913 * flickering pixels due to Z write ordering failures after
8914 * some amount of runtime in the Mesa "fire" demo, and Unigine
8915 * Sanctuary and Tropics, and apparently anything else with
8916 * alpha test or pixel discard.
9ca1d10d
EA		 8917 *
8918 * According to the spec, bit 11 (RCCUNIT) must also be set,
8919 * but we didn't debug actual testcases to find it out.
406478dc 8920 */
9ca1d10d
EA		 8921 I915_WRITE(GEN6_UCGCTL2,
8922 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8923 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
406478dc 8924
bf97b276
DV		 8925 /* Bspec says we need to always set all mask bits. */
8926 I915_WRITE(_3D_CHICKEN, (0xFFFF << 16) |
8927 _3D_CHICKEN_SF_DISABLE_FASTCLIP_CULL);
8928
652c393a 8929 /*
6067aaea
JB		 8930 * According to the spec the following bits should be
8931 * set in order to enable memory self-refresh and fbc:
8932 * The bit21 and bit22 of 0x42000
8933 * The bit21 and bit22 of 0x42004
8934 * The bit5 and bit7 of 0x42020
8935 * The bit14 of 0x70180
8936 * The bit14 of 0x71180
652c393a 8937 */
6067aaea
JB		 8938 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8939 I915_READ(ILK_DISPLAY_CHICKEN1) |
8940 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8941 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8942 I915_READ(ILK_DISPLAY_CHICKEN2) |
8943 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8944 I915_WRITE(ILK_DSPCLK_GATE,
8945 I915_READ(ILK_DSPCLK_GATE) |
8946 ILK_DPARB_CLK_GATE |
8947 ILK_DPFD_CLK_GATE);
8956c8bb 8948
d74362c9 8949 for_each_pipe(pipe) {
6067aaea
JB		 8950 I915_WRITE(DSPCNTR(pipe),
8951 I915_READ(DSPCNTR(pipe)) |
8952 DISPPLANE_TRICKLE_FEED_DISABLE);
d74362c9
KP		 8953 intel_flush_display_plane(dev_priv, pipe);
8954 }
6067aaea 8955}
8956c8bb 8956
a1e969e0
BW		 8957static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
8958{
8959 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
8960
8961 reg &= ~GEN7_FF_SCHED_MASK;
8962 reg |= GEN7_FF_TS_SCHED_HW;
8963 reg |= GEN7_FF_VS_SCHED_HW;
8964 reg |= GEN7_FF_DS_SCHED_HW;
8965
8966 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
8967}
8968
28963a3e
JB		 8969static void ivybridge_init_clock_gating(struct drm_device *dev)
8970{
8971 struct drm_i915_private *dev_priv = dev->dev_private;
8972 int pipe;
8973 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7f8a8569 8974
28963a3e 8975 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
382b0936 8976
28963a3e
JB		 8977 I915_WRITE(WM3_LP_ILK, 0);
8978 I915_WRITE(WM2_LP_ILK, 0);
8979 I915_WRITE(WM1_LP_ILK, 0);
de6e2eaf 8980
eae66b50
ED		 8981 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
8982 * This implements the WaDisableRCZUnitClockGating workaround.
8983 */
8984 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
8985
28963a3e 8986 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
67e92af0 8987
116ac8d2
EA		 8988 I915_WRITE(IVB_CHICKEN3,
8989 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8990 CHICKEN3_DGMG_DONE_FIX_DISABLE);
8991
d71de14d
KG		 8992 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
8993 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
8994 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
8995
e4e0c058
ED		 8996 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
8997 I915_WRITE(GEN7_L3CNTLREG1,
8998 GEN7_WA_FOR_GEN7_L3_CONTROL);
8999 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
9000 GEN7_WA_L3_CHICKEN_MODE);
9001
db099c8f
ED		 9002 /* This is required by WaCatErrorRejectionIssue */
9003 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
9004 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
9005 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
9006
d74362c9 9007 for_each_pipe(pipe) {
28963a3e
JB		 9008 I915_WRITE(DSPCNTR(pipe),
9009 I915_READ(DSPCNTR(pipe)) |
9010 DISPPLANE_TRICKLE_FEED_DISABLE);
d74362c9
KP		 9011 intel_flush_display_plane(dev_priv, pipe);
9012 }
a1e969e0
BW		 9013
9014 gen7_setup_fixed_func_scheduler(dev_priv);
28963a3e
JB		 9015}
9016
fb046853
JB		 9017static void valleyview_init_clock_gating(struct drm_device *dev)
9018{
9019 struct drm_i915_private *dev_priv = dev->dev_private;
9020 int pipe;
9021 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
9022
9023 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
9024
9025 I915_WRITE(WM3_LP_ILK, 0);
9026 I915_WRITE(WM2_LP_ILK, 0);
9027 I915_WRITE(WM1_LP_ILK, 0);
9028
9029 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
9030 * This implements the WaDisableRCZUnitClockGating workaround.
9031 */
9032 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
9033
9034 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
9035
9036 I915_WRITE(IVB_CHICKEN3,
9037 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
9038 CHICKEN3_DGMG_DONE_FIX_DISABLE);
9039
9040 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
9041 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
9042 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
9043
9044 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
9045 I915_WRITE(GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL);
9046 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
9047
9048 /* This is required by WaCatErrorRejectionIssue */
9049 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
9050 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
9051 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
9052
9053 for_each_pipe(pipe) {
9054 I915_WRITE(DSPCNTR(pipe),
9055 I915_READ(DSPCNTR(pipe)) |
9056 DISPPLANE_TRICKLE_FEED_DISABLE);
9057 intel_flush_display_plane(dev_priv, pipe);
9058 }
9059
9060 I915_WRITE(CACHE_MODE_1, I915_READ(CACHE_MODE_1) |
9061 (PIXEL_SUBSPAN_COLLECT_OPT_DISABLE << 16) |
9062 PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
9063}
9064
6067aaea
JB		 9065static void g4x_init_clock_gating(struct drm_device *dev)
9066{
9067 struct drm_i915_private *dev_priv = dev->dev_private;
9068 uint32_t dspclk_gate;
8fd26859 9069
6067aaea
JB		 9070 I915_WRITE(RENCLK_GATE_D1, 0);
9071 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
9072 GS_UNIT_CLOCK_GATE_DISABLE |
9073 CL_UNIT_CLOCK_GATE_DISABLE);
9074 I915_WRITE(RAMCLK_GATE_D, 0);
9075 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
9076 OVRUNIT_CLOCK_GATE_DISABLE |
9077 OVCUNIT_CLOCK_GATE_DISABLE;
9078 if (IS_GM45(dev))
9079 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
9080 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
9081}
1398261a 9082
6067aaea
JB		 9083static void crestline_init_clock_gating(struct drm_device *dev)
9084{
9085 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 9086
6067aaea
JB		 9087 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
9088 I915_WRITE(RENCLK_GATE_D2, 0);
9089 I915_WRITE(DSPCLK_GATE_D, 0);
9090 I915_WRITE(RAMCLK_GATE_D, 0);
9091 I915_WRITE16(DEUC, 0);
9092}
652c393a 9093
6067aaea
JB		 9094static void broadwater_init_clock_gating(struct drm_device *dev)
9095{
9096 struct drm_i915_private *dev_priv = dev->dev_private;
9097
9098 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
9099 I965_RCC_CLOCK_GATE_DISABLE |
9100 I965_RCPB_CLOCK_GATE_DISABLE |
9101 I965_ISC_CLOCK_GATE_DISABLE |
9102 I965_FBC_CLOCK_GATE_DISABLE);
9103 I915_WRITE(RENCLK_GATE_D2, 0);
9104}
9105
9106static void gen3_init_clock_gating(struct drm_device *dev)
9107{
9108 struct drm_i915_private *dev_priv = dev->dev_private;
9109 u32 dstate = I915_READ(D_STATE);
9110
9111 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
9112 DSTATE_DOT_CLOCK_GATING;
9113 I915_WRITE(D_STATE, dstate);
9114}
9115
9116static void i85x_init_clock_gating(struct drm_device *dev)
9117{
9118 struct drm_i915_private *dev_priv = dev->dev_private;
9119
9120 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
9121}
9122
9123static void i830_init_clock_gating(struct drm_device *dev)
9124{
9125 struct drm_i915_private *dev_priv = dev->dev_private;
9126
9127 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
652c393a
JB		 9128}
9129
645c62a5
JB		 9130static void ibx_init_clock_gating(struct drm_device *dev)
9131{
9132 struct drm_i915_private *dev_priv = dev->dev_private;
9133
9134 /*
9135 * On Ibex Peak and Cougar Point, we need to disable clock
9136 * gating for the panel power sequencer or it will fail to
9137 * start up when no ports are active.
9138 */
9139 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
9140}
9141
9142static void cpt_init_clock_gating(struct drm_device *dev)
9143{
9144 struct drm_i915_private *dev_priv = dev->dev_private;
3bcf603f 9145 int pipe;
645c62a5
JB		 9146
9147 /*
9148 * On Ibex Peak and Cougar Point, we need to disable clock
9149 * gating for the panel power sequencer or it will fail to
9150 * start up when no ports are active.
9151 */
9152 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
9153 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
9154 DPLS_EDP_PPS_FIX_DIS);
3bcf603f
JB		 9155 /* Without this, mode sets may fail silently on FDI */
9156 for_each_pipe(pipe)
9157 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
652c393a
JB		 9158}
9159
ac668088 9160static void ironlake_teardown_rc6(struct drm_device *dev)
0cdab21f
CW		 9161{
9162 struct drm_i915_private *dev_priv = dev->dev_private;
9163
9164 if (dev_priv->renderctx) {
ac668088
CW		 9165 i915_gem_object_unpin(dev_priv->renderctx);
9166 drm_gem_object_unreference(&dev_priv->renderctx->base);
0cdab21f
CW		 9167 dev_priv->renderctx = NULL;
9168 }
9169
9170 if (dev_priv->pwrctx) {
ac668088
CW		 9171 i915_gem_object_unpin(dev_priv->pwrctx);
9172 drm_gem_object_unreference(&dev_priv->pwrctx->base);
9173 dev_priv->pwrctx = NULL;
9174 }
9175}
9176
9177static void ironlake_disable_rc6(struct drm_device *dev)
9178{
9179 struct drm_i915_private *dev_priv = dev->dev_private;
9180
9181 if (I915_READ(PWRCTXA)) {
9182 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
9183 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
9184 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
9185 50);
0cdab21f
CW		 9186
9187 I915_WRITE(PWRCTXA, 0);
9188 POSTING_READ(PWRCTXA);
9189
ac668088
CW		 9190 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
9191 POSTING_READ(RSTDBYCTL);
0cdab21f 9192 }
ac668088 9193
99507307 9194 ironlake_teardown_rc6(dev);
0cdab21f
CW		 9195}
9196
ac668088 9197static int ironlake_setup_rc6(struct drm_device *dev)
d5bb081b
JB		 9198{
9199 struct drm_i915_private *dev_priv = dev->dev_private;
9200
ac668088
CW		 9201 if (dev_priv->renderctx == NULL)
9202 dev_priv->renderctx = intel_alloc_context_page(dev);
9203 if (!dev_priv->renderctx)
9204 return -ENOMEM;
9205
9206 if (dev_priv->pwrctx == NULL)
9207 dev_priv->pwrctx = intel_alloc_context_page(dev);
9208 if (!dev_priv->pwrctx) {
9209 ironlake_teardown_rc6(dev);
9210 return -ENOMEM;
9211 }
9212
9213 return 0;
d5bb081b
JB		 9214}
9215
9216void ironlake_enable_rc6(struct drm_device *dev)
9217{
9218 struct drm_i915_private *dev_priv = dev->dev_private;
9219 int ret;
9220
ac668088
CW		 9221 /* rc6 disabled by default due to repeated reports of hanging during
9222 * boot and resume.
9223 */
c0f372b3 9224 if (!intel_enable_rc6(dev))
ac668088
CW		 9225 return;
9226
2c34b850 9227 mutex_lock(&dev->struct_mutex);
ac668088 9228 ret = ironlake_setup_rc6(dev);
2c34b850
BW		 9229 if (ret) {
9230 mutex_unlock(&dev->struct_mutex);
ac668088 9231 return;
2c34b850 9232 }
ac668088 9233
d5bb081b
JB		 9234 /*
9235 * GPU can automatically power down the render unit if given a page
9236 * to save state.
9237 */
9238 ret = BEGIN_LP_RING(6);
9239 if (ret) {
ac668088 9240 ironlake_teardown_rc6(dev);
2c34b850 9241 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 9242 return;
9243 }
ac668088 9244
d5bb081b
JB		 9245 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
9246 OUT_RING(MI_SET_CONTEXT);
9247 OUT_RING(dev_priv->renderctx->gtt_offset |
9248 MI_MM_SPACE_GTT |
9249 MI_SAVE_EXT_STATE_EN |
9250 MI_RESTORE_EXT_STATE_EN |
9251 MI_RESTORE_INHIBIT);
9252 OUT_RING(MI_SUSPEND_FLUSH);
9253 OUT_RING(MI_NOOP);
9254 OUT_RING(MI_FLUSH);
9255 ADVANCE_LP_RING();
9256
4a246cfc
BW		 9257 /*
9258 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
9259 * does an implicit flush, combined with MI_FLUSH above, it should be
9260 * safe to assume that renderctx is valid
9261 */
9262 ret = intel_wait_ring_idle(LP_RING(dev_priv));
9263 if (ret) {
9264 DRM_ERROR("failed to enable ironlake power power savings\n");
9265 ironlake_teardown_rc6(dev);
9266 mutex_unlock(&dev->struct_mutex);
9267 return;
9268 }
9269
d5bb081b
JB		 9270 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
9271 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2c34b850 9272 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 9273}
9274
645c62a5
JB		 9275void intel_init_clock_gating(struct drm_device *dev)
9276{
9277 struct drm_i915_private *dev_priv = dev->dev_private;
9278
9279 dev_priv->display.init_clock_gating(dev);
9280
9281 if (dev_priv->display.init_pch_clock_gating)
9282 dev_priv->display.init_pch_clock_gating(dev);
9283}
ac668088 9284
e70236a8
JB		 9285/* Set up chip specific display functions */
9286static void intel_init_display(struct drm_device *dev)
9287{
9288 struct drm_i915_private *dev_priv = dev->dev_private;
9289
9290 /* We always want a DPMS function */
f564048e 9291 if (HAS_PCH_SPLIT(dev)) {
f2b115e6 9292 dev_priv->display.dpms = ironlake_crtc_dpms;
f564048e 9293 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
17638cd6 9294 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 9295 } else {
e70236a8 9296 dev_priv->display.dpms = i9xx_crtc_dpms;
f564048e 9297 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
17638cd6 9298 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9299 }
e70236a8 9300
ee5382ae 9301 if (I915_HAS_FBC(dev)) {
9c04f015 9302 if (HAS_PCH_SPLIT(dev)) {
b52eb4dc
ZY		 9303 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
9304 dev_priv->display.enable_fbc = ironlake_enable_fbc;
9305 dev_priv->display.disable_fbc = ironlake_disable_fbc;
9306 } else if (IS_GM45(dev)) {
74dff282
JB		 9307 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
9308 dev_priv->display.enable_fbc = g4x_enable_fbc;
9309 dev_priv->display.disable_fbc = g4x_disable_fbc;
a6c45cf0 9310 } else if (IS_CRESTLINE(dev)) {
e70236a8
JB		 9311 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
9312 dev_priv->display.enable_fbc = i8xx_enable_fbc;
9313 dev_priv->display.disable_fbc = i8xx_disable_fbc;
9314 }
74dff282 9315 /* 855GM needs testing */
e70236a8
JB		 9316 }
9317
9318 /* Returns the core display clock speed */
25eb05fc
JB		 9319 if (IS_VALLEYVIEW(dev))
9320 dev_priv->display.get_display_clock_speed =
9321 valleyview_get_display_clock_speed;
9322 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 9323 dev_priv->display.get_display_clock_speed =
9324 i945_get_display_clock_speed;
9325 else if (IS_I915G(dev))
9326 dev_priv->display.get_display_clock_speed =
9327 i915_get_display_clock_speed;
f2b115e6 9328 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 9329 dev_priv->display.get_display_clock_speed =
9330 i9xx_misc_get_display_clock_speed;
9331 else if (IS_I915GM(dev))
9332 dev_priv->display.get_display_clock_speed =
9333 i915gm_get_display_clock_speed;
9334 else if (IS_I865G(dev))
9335 dev_priv->display.get_display_clock_speed =
9336 i865_get_display_clock_speed;
f0f8a9ce 9337 else if (IS_I85X(dev))
e70236a8
JB		 9338 dev_priv->display.get_display_clock_speed =
9339 i855_get_display_clock_speed;
9340 else /* 852, 830 */
9341 dev_priv->display.get_display_clock_speed =
9342 i830_get_display_clock_speed;
9343
9344 /* For FIFO watermark updates */
7f8a8569 9345 if (HAS_PCH_SPLIT(dev)) {
8d715f00
KP		 9346 dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
9347 dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
9348
9349 /* IVB configs may use multi-threaded forcewake */
246bdbeb 9350 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
8d715f00
KP		 9351 u32 ecobus;
9352
c7dffff7
KP		 9353 /* A small trick here - if the bios hasn't configured MT forcewake,
9354 * and if the device is in RC6, then force_wake_mt_get will not wake
9355 * the device and the ECOBUS read will return zero. Which will be
9356 * (correctly) interpreted by the test below as MT forcewake being
9357 * disabled.
9358 */
8d715f00
KP		 9359 mutex_lock(&dev->struct_mutex);
9360 __gen6_gt_force_wake_mt_get(dev_priv);
c7dffff7 9361 ecobus = I915_READ_NOTRACE(ECOBUS);
8d715f00
KP		 9362 __gen6_gt_force_wake_mt_put(dev_priv);
9363 mutex_unlock(&dev->struct_mutex);
9364
9365 if (ecobus & FORCEWAKE_MT_ENABLE) {
9366 DRM_DEBUG_KMS("Using MT version of forcewake\n");
9367 dev_priv->display.force_wake_get =
9368 __gen6_gt_force_wake_mt_get;
9369 dev_priv->display.force_wake_put =
9370 __gen6_gt_force_wake_mt_put;
9371 }
9372 }
9373
645c62a5
JB		 9374 if (HAS_PCH_IBX(dev))
9375 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
9376 else if (HAS_PCH_CPT(dev))
9377 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
9378
f00a3ddf 9379 if (IS_GEN5(dev)) {
7f8a8569
ZW		 9380 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
9381 dev_priv->display.update_wm = ironlake_update_wm;
9382 else {
9383 DRM_DEBUG_KMS("Failed to get proper latency. "
9384 "Disable CxSR\n");
9385 dev_priv->display.update_wm = NULL;
1398261a 9386 }
674cf967 9387 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
6067aaea 9388 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
e0dac65e 9389 dev_priv->display.write_eld = ironlake_write_eld;
1398261a
YL		 9390 } else if (IS_GEN6(dev)) {
9391 if (SNB_READ_WM0_LATENCY()) {
9392 dev_priv->display.update_wm = sandybridge_update_wm;
b840d907 9393 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
1398261a
YL		 9394 } else {
9395 DRM_DEBUG_KMS("Failed to read display plane latency. "
9396 "Disable CxSR\n");
9397 dev_priv->display.update_wm = NULL;
7f8a8569 9398 }
674cf967 9399 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
6067aaea 9400 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
e0dac65e 9401 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 9402 } else if (IS_IVYBRIDGE(dev)) {
9403 /* FIXME: detect B0+ stepping and use auto training */
9404 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
fe100d4d
JB		 9405 if (SNB_READ_WM0_LATENCY()) {
9406 dev_priv->display.update_wm = sandybridge_update_wm;
b840d907 9407 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
fe100d4d
JB		 9408 } else {
9409 DRM_DEBUG_KMS("Failed to read display plane latency. "
9410 "Disable CxSR\n");
9411 dev_priv->display.update_wm = NULL;
9412 }
28963a3e 9413 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
e0dac65e 9414 dev_priv->display.write_eld = ironlake_write_eld;
7f8a8569
ZW		 9415 } else
9416 dev_priv->display.update_wm = NULL;
ceb04246
JB		 9417 } else if (IS_VALLEYVIEW(dev)) {
9418 dev_priv->display.update_wm = valleyview_update_wm;
fb046853
JB		 9419 dev_priv->display.init_clock_gating =
9420 valleyview_init_clock_gating;
575155a9
JB		 9421 dev_priv->display.force_wake_get = vlv_force_wake_get;
9422 dev_priv->display.force_wake_put = vlv_force_wake_put;
7f8a8569 9423 } else if (IS_PINEVIEW(dev)) {
d4294342 9424 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
95534263 9425 dev_priv->is_ddr3,
d4294342
ZY		 9426 dev_priv->fsb_freq,
9427 dev_priv->mem_freq)) {
9428 DRM_INFO("failed to find known CxSR latency "
95534263 9429 "(found ddr%s fsb freq %d, mem freq %d), "
d4294342 9430 "disabling CxSR\n",
0206e353 9431 (dev_priv->is_ddr3 == 1) ? "3" : "2",
d4294342
ZY		 9432 dev_priv->fsb_freq, dev_priv->mem_freq);
9433 /* Disable CxSR and never update its watermark again */
9434 pineview_disable_cxsr(dev);
9435 dev_priv->display.update_wm = NULL;
9436 } else
9437 dev_priv->display.update_wm = pineview_update_wm;
95e0ee92 9438 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6067aaea 9439 } else if (IS_G4X(dev)) {
e0dac65e 9440 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 9441 dev_priv->display.update_wm = g4x_update_wm;
6067aaea
JB		 9442 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
9443 } else if (IS_GEN4(dev)) {
e70236a8 9444 dev_priv->display.update_wm = i965_update_wm;
6067aaea
JB		 9445 if (IS_CRESTLINE(dev))
9446 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
9447 else if (IS_BROADWATER(dev))
9448 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
9449 } else if (IS_GEN3(dev)) {
e70236a8
JB		 9450 dev_priv->display.update_wm = i9xx_update_wm;
9451 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6067aaea
JB		 9452 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
9453 } else if (IS_I865G(dev)) {
9454 dev_priv->display.update_wm = i830_update_wm;
9455 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
9456 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8f4695ed
AJ		 9457 } else if (IS_I85X(dev)) {
9458 dev_priv->display.update_wm = i9xx_update_wm;
9459 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6067aaea 9460 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
e70236a8 9461 } else {
8f4695ed 9462 dev_priv->display.update_wm = i830_update_wm;
6067aaea 9463 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8f4695ed 9464 if (IS_845G(dev))
e70236a8
JB		 9465 dev_priv->display.get_fifo_size = i845_get_fifo_size;
9466 else
9467 dev_priv->display.get_fifo_size = i830_get_fifo_size;
e70236a8 9468 }
8c9f3aaf
JB		 9469
9470 /* Default just returns -ENODEV to indicate unsupported */
9471 dev_priv->display.queue_flip = intel_default_queue_flip;
9472
9473 switch (INTEL_INFO(dev)->gen) {
9474 case 2:
9475 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9476 break;
9477
9478 case 3:
9479 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9480 break;
9481
9482 case 4:
9483 case 5:
9484 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9485 break;
9486
9487 case 6:
9488 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9489 break;
7c9017e5
JB		 9490 case 7:
9491 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9492 break;
8c9f3aaf 9493 }
e70236a8
JB		 9494}
9495
b690e96c
JB		 9496/*
9497 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9498 * resume, or other times. This quirk makes sure that's the case for
9499 * affected systems.
9500 */
0206e353 9501static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 9502{
9503 struct drm_i915_private *dev_priv = dev->dev_private;
9504
9505 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 9506 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 9507}
9508
435793df
KP		 9509/*
9510 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9511 */
9512static void quirk_ssc_force_disable(struct drm_device *dev)
9513{
9514 struct drm_i915_private *dev_priv = dev->dev_private;
9515 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 9516 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 9517}
9518
4dca20ef 9519/*
5a15ab5b
CE		 9520 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9521 * brightness value
4dca20ef
CE		 9522 */
9523static void quirk_invert_brightness(struct drm_device *dev)
9524{
9525 struct drm_i915_private *dev_priv = dev->dev_private;
9526 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 9527 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 9528}
9529
b690e96c
JB		 9530struct intel_quirk {
9531 int device;
9532 int subsystem_vendor;
9533 int subsystem_device;
9534 void (*hook)(struct drm_device *dev);
9535};
9536
c43b5634 9537static struct intel_quirk intel_quirks[] = {
b690e96c 9538 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 9539 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c
JB		 9540
9541 /* Thinkpad R31 needs pipe A force quirk */
9542 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
9543 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9544 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9545
9546 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
9547 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
9548 /* ThinkPad X40 needs pipe A force quirk */
9549
9550 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9551 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9552
9553 /* 855 & before need to leave pipe A & dpll A up */
9554 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9555 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9556
9557 /* Lenovo U160 cannot use SSC on LVDS */
9558 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9559
9560 /* Sony Vaio Y cannot use SSC on LVDS */
9561 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 9562
9563 /* Acer Aspire 5734Z must invert backlight brightness */
9564 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
b690e96c
JB		 9565};
9566
9567static void intel_init_quirks(struct drm_device *dev)
9568{
9569 struct pci_dev *d = dev->pdev;
9570 int i;
9571
9572 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9573 struct intel_quirk *q = &intel_quirks[i];
9574
9575 if (d->device == q->device &&
9576 (d->subsystem_vendor == q->subsystem_vendor ||
9577 q->subsystem_vendor == PCI_ANY_ID) &&
9578 (d->subsystem_device == q->subsystem_device ||
9579 q->subsystem_device == PCI_ANY_ID))
9580 q->hook(dev);
9581 }
9582}
9583
9cce37f4
JB		 9584/* Disable the VGA plane that we never use */
9585static void i915_disable_vga(struct drm_device *dev)
9586{
9587 struct drm_i915_private *dev_priv = dev->dev_private;
9588 u8 sr1;
9589 u32 vga_reg;
9590
9591 if (HAS_PCH_SPLIT(dev))
9592 vga_reg = CPU_VGACNTRL;
9593 else
9594 vga_reg = VGACNTRL;
9595
9596 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 9597 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 9598 sr1 = inb(VGA_SR_DATA);
9599 outb(sr1 | 1<<5, VGA_SR_DATA);
9600 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9601 udelay(300);
9602
9603 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9604 POSTING_READ(vga_reg);
9605}
9606
f82cfb6b
JB		 9607static void ivb_pch_pwm_override(struct drm_device *dev)
9608{
9609 struct drm_i915_private *dev_priv = dev->dev_private;
9610
9611 /*
9612 * IVB has CPU eDP backlight regs too, set things up to let the
9613 * PCH regs control the backlight
9614 */
9615 I915_WRITE(BLC_PWM_CPU_CTL2, PWM_ENABLE);
9616 I915_WRITE(BLC_PWM_CPU_CTL, 0);
9617 I915_WRITE(BLC_PWM_PCH_CTL1, PWM_ENABLE | (1<<30));
9618}
9619
f817586c
DV		 9620void intel_modeset_init_hw(struct drm_device *dev)
9621{
9622 struct drm_i915_private *dev_priv = dev->dev_private;
9623
9624 intel_init_clock_gating(dev);
9625
9626 if (IS_IRONLAKE_M(dev)) {
9627 ironlake_enable_drps(dev);
9628 intel_init_emon(dev);
9629 }
9630
b6834bd6 9631 if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
f817586c
DV		 9632 gen6_enable_rps(dev_priv);
9633 gen6_update_ring_freq(dev_priv);
9634 }
f82cfb6b
JB		 9635
9636 if (IS_IVYBRIDGE(dev))
9637 ivb_pch_pwm_override(dev);
f817586c
DV		 9638}
9639
79e53945
JB		 9640void intel_modeset_init(struct drm_device *dev)
9641{
652c393a 9642 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 9643 int i, ret;
79e53945
JB		 9644
9645 drm_mode_config_init(dev);
9646
9647 dev->mode_config.min_width = 0;
9648 dev->mode_config.min_height = 0;
9649
019d96cb
DA		 9650 dev->mode_config.preferred_depth = 24;
9651 dev->mode_config.prefer_shadow = 1;
9652
79e53945
JB		 9653 dev->mode_config.funcs = (void *)&intel_mode_funcs;
9654
b690e96c
JB		 9655 intel_init_quirks(dev);
9656
e70236a8
JB		 9657 intel_init_display(dev);
9658
a6c45cf0
CW		 9659 if (IS_GEN2(dev)) {
9660 dev->mode_config.max_width = 2048;
9661 dev->mode_config.max_height = 2048;
9662 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9663 dev->mode_config.max_width = 4096;
9664 dev->mode_config.max_height = 4096;
79e53945 9665 } else {
a6c45cf0
CW		 9666 dev->mode_config.max_width = 8192;
9667 dev->mode_config.max_height = 8192;
79e53945 9668 }
35c3047a 9669 dev->mode_config.fb_base = dev->agp->base;
79e53945 9670
28c97730 9671 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 9672 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 9673
a3524f1b 9674 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 9675 intel_crtc_init(dev, i);
00c2064b
JB		 9676 ret = intel_plane_init(dev, i);
9677 if (ret)
9678 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 9679 }
9680
9cce37f4
JB		 9681 /* Just disable it once at startup */
9682 i915_disable_vga(dev);
79e53945 9683 intel_setup_outputs(dev);
652c393a 9684
f817586c 9685 intel_modeset_init_hw(dev);
3b8d8d91 9686
652c393a
JB		 9687 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
9688 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
9689 (unsigned long)dev);
2c7111db
CW		 9690}
9691
9692void intel_modeset_gem_init(struct drm_device *dev)
9693{
9694 if (IS_IRONLAKE_M(dev))
9695 ironlake_enable_rc6(dev);
02e792fb
DV		 9696
9697 intel_setup_overlay(dev);
79e53945
JB		 9698}
9699
9700void intel_modeset_cleanup(struct drm_device *dev)
9701{
652c393a
JB		 9702 struct drm_i915_private *dev_priv = dev->dev_private;
9703 struct drm_crtc *crtc;
9704 struct intel_crtc *intel_crtc;
9705
f87ea761 9706 drm_kms_helper_poll_fini(dev);
652c393a
JB		 9707 mutex_lock(&dev->struct_mutex);
9708
723bfd70
JB		 9709 intel_unregister_dsm_handler();
9710
9711
652c393a
JB		 9712 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9713 /* Skip inactive CRTCs */
9714 if (!crtc->fb)
9715 continue;
9716
9717 intel_crtc = to_intel_crtc(crtc);
3dec0095 9718 intel_increase_pllclock(crtc);
652c393a
JB		 9719 }
9720
973d04f9 9721 intel_disable_fbc(dev);
e70236a8 9722
f97108d1
JB		 9723 if (IS_IRONLAKE_M(dev))
9724 ironlake_disable_drps(dev);
b6834bd6 9725 if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev))
3b8d8d91 9726 gen6_disable_rps(dev);
f97108d1 9727
d5bb081b
JB		 9728 if (IS_IRONLAKE_M(dev))
9729 ironlake_disable_rc6(dev);
0cdab21f 9730
57f350b6
JB		 9731 if (IS_VALLEYVIEW(dev))
9732 vlv_init_dpio(dev);
9733
69341a5e
KH		 9734 mutex_unlock(&dev->struct_mutex);
9735
6c0d9350
DV		 9736 /* Disable the irq before mode object teardown, for the irq might
9737 * enqueue unpin/hotplug work. */
9738 drm_irq_uninstall(dev);
9739 cancel_work_sync(&dev_priv->hotplug_work);
6fdd4d98 9740 cancel_work_sync(&dev_priv->rps_work);
6c0d9350 9741
1630fe75
CW		 9742 /* flush any delayed tasks or pending work */
9743 flush_scheduled_work();
9744
3dec0095
DV		 9745 /* Shut off idle work before the crtcs get freed. */
9746 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9747 intel_crtc = to_intel_crtc(crtc);
9748 del_timer_sync(&intel_crtc->idle_timer);
9749 }
9750 del_timer_sync(&dev_priv->idle_timer);
9751 cancel_work_sync(&dev_priv->idle_work);
9752
79e53945
JB		 9753 drm_mode_config_cleanup(dev);
9754}
9755
f1c79df3
ZW		 9756/*
9757 * Return which encoder is currently attached for connector.
9758 */
df0e9248 9759struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9760{
df0e9248
CW		 9761 return &intel_attached_encoder(connector)->base;
9762}
f1c79df3 9763
df0e9248
CW		 9764void intel_connector_attach_encoder(struct intel_connector *connector,
9765 struct intel_encoder *encoder)
9766{
9767 connector->encoder = encoder;
9768 drm_mode_connector_attach_encoder(&connector->base,
9769 &encoder->base);
79e53945 9770}
28d52043
DA		 9771
9772/*
9773 * set vga decode state - true == enable VGA decode
9774 */
9775int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9776{
9777 struct drm_i915_private *dev_priv = dev->dev_private;
9778 u16 gmch_ctrl;
9779
9780 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9781 if (state)
9782 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9783 else
9784 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9785 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9786 return 0;
9787}
c4a1d9e4
CW		 9788
9789#ifdef CONFIG_DEBUG_FS
9790#include <linux/seq_file.h>
9791
9792struct intel_display_error_state {
9793 struct intel_cursor_error_state {
9794 u32 control;
9795 u32 position;
9796 u32 base;
9797 u32 size;
9798 } cursor[2];
9799
9800 struct intel_pipe_error_state {
9801 u32 conf;
9802 u32 source;
9803
9804 u32 htotal;
9805 u32 hblank;
9806 u32 hsync;
9807 u32 vtotal;
9808 u32 vblank;
9809 u32 vsync;
9810 } pipe[2];
9811
9812 struct intel_plane_error_state {
9813 u32 control;
9814 u32 stride;
9815 u32 size;
9816 u32 pos;
9817 u32 addr;
9818 u32 surface;
9819 u32 tile_offset;
9820 } plane[2];
9821};
9822
9823struct intel_display_error_state *
9824intel_display_capture_error_state(struct drm_device *dev)
9825{
0206e353 9826 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 9827 struct intel_display_error_state *error;
9828 int i;
9829
9830 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9831 if (error == NULL)
9832 return NULL;
9833
9834 for (i = 0; i < 2; i++) {
9835 error->cursor[i].control = I915_READ(CURCNTR(i));
9836 error->cursor[i].position = I915_READ(CURPOS(i));
9837 error->cursor[i].base = I915_READ(CURBASE(i));
9838
9839 error->plane[i].control = I915_READ(DSPCNTR(i));
9840 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9841 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 9842 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 9843 error->plane[i].addr = I915_READ(DSPADDR(i));
9844 if (INTEL_INFO(dev)->gen >= 4) {
9845 error->plane[i].surface = I915_READ(DSPSURF(i));
9846 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9847 }
9848
9849 error->pipe[i].conf = I915_READ(PIPECONF(i));
9850 error->pipe[i].source = I915_READ(PIPESRC(i));
9851 error->pipe[i].htotal = I915_READ(HTOTAL(i));
9852 error->pipe[i].hblank = I915_READ(HBLANK(i));
9853 error->pipe[i].hsync = I915_READ(HSYNC(i));
9854 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
9855 error->pipe[i].vblank = I915_READ(VBLANK(i));
9856 error->pipe[i].vsync = I915_READ(VSYNC(i));
9857 }
9858
9859 return error;
9860}
9861
9862void
9863intel_display_print_error_state(struct seq_file *m,
9864 struct drm_device *dev,
9865 struct intel_display_error_state *error)
9866{
9867 int i;
9868
9869 for (i = 0; i < 2; i++) {
9870 seq_printf(m, "Pipe [%d]:\n", i);
9871 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9872 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9873 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9874 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9875 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9876 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9877 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9878 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9879
9880 seq_printf(m, "Plane [%d]:\n", i);
9881 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9882 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9883 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9884 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9885 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9886 if (INTEL_INFO(dev)->gen >= 4) {
9887 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9888 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9889 }
9890
9891 seq_printf(m, "Cursor [%d]:\n", i);
9892 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9893 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9894 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9895 }
9896}
9897#endif
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