]>
Commit | Line | Data |
---|---|---|
79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
c1c7af60 JB |
27 | #include <linux/module.h> |
28 | #include <linux/input.h> | |
79e53945 | 29 | #include <linux/i2c.h> |
7662c8bd | 30 | #include <linux/kernel.h> |
5a0e3ad6 | 31 | #include <linux/slab.h> |
9cce37f4 | 32 | #include <linux/vgaarb.h> |
79e53945 JB |
33 | #include "drmP.h" |
34 | #include "intel_drv.h" | |
35 | #include "i915_drm.h" | |
36 | #include "i915_drv.h" | |
e5510fac | 37 | #include "i915_trace.h" |
ab2c0672 | 38 | #include "drm_dp_helper.h" |
79e53945 JB |
39 | |
40 | #include "drm_crtc_helper.h" | |
41 | ||
32f9d658 ZW |
42 | #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) |
43 | ||
79e53945 | 44 | bool intel_pipe_has_type (struct drm_crtc *crtc, int type); |
7662c8bd | 45 | static void intel_update_watermarks(struct drm_device *dev); |
3dec0095 | 46 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
cda4b7d3 | 47 | static void intel_crtc_update_cursor(struct drm_crtc *crtc); |
79e53945 JB |
48 | |
49 | typedef struct { | |
50 | /* given values */ | |
51 | int n; | |
52 | int m1, m2; | |
53 | int p1, p2; | |
54 | /* derived values */ | |
55 | int dot; | |
56 | int vco; | |
57 | int m; | |
58 | int p; | |
59 | } intel_clock_t; | |
60 | ||
61 | typedef struct { | |
62 | int min, max; | |
63 | } intel_range_t; | |
64 | ||
65 | typedef struct { | |
66 | int dot_limit; | |
67 | int p2_slow, p2_fast; | |
68 | } intel_p2_t; | |
69 | ||
70 | #define INTEL_P2_NUM 2 | |
d4906093 ML |
71 | typedef struct intel_limit intel_limit_t; |
72 | struct intel_limit { | |
79e53945 JB |
73 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
74 | intel_p2_t p2; | |
d4906093 ML |
75 | bool (* find_pll)(const intel_limit_t *, struct drm_crtc *, |
76 | int, int, intel_clock_t *); | |
77 | }; | |
79e53945 JB |
78 | |
79 | #define I8XX_DOT_MIN 25000 | |
80 | #define I8XX_DOT_MAX 350000 | |
81 | #define I8XX_VCO_MIN 930000 | |
82 | #define I8XX_VCO_MAX 1400000 | |
83 | #define I8XX_N_MIN 3 | |
84 | #define I8XX_N_MAX 16 | |
85 | #define I8XX_M_MIN 96 | |
86 | #define I8XX_M_MAX 140 | |
87 | #define I8XX_M1_MIN 18 | |
88 | #define I8XX_M1_MAX 26 | |
89 | #define I8XX_M2_MIN 6 | |
90 | #define I8XX_M2_MAX 16 | |
91 | #define I8XX_P_MIN 4 | |
92 | #define I8XX_P_MAX 128 | |
93 | #define I8XX_P1_MIN 2 | |
94 | #define I8XX_P1_MAX 33 | |
95 | #define I8XX_P1_LVDS_MIN 1 | |
96 | #define I8XX_P1_LVDS_MAX 6 | |
97 | #define I8XX_P2_SLOW 4 | |
98 | #define I8XX_P2_FAST 2 | |
99 | #define I8XX_P2_LVDS_SLOW 14 | |
0c2e3952 | 100 | #define I8XX_P2_LVDS_FAST 7 |
79e53945 JB |
101 | #define I8XX_P2_SLOW_LIMIT 165000 |
102 | ||
103 | #define I9XX_DOT_MIN 20000 | |
104 | #define I9XX_DOT_MAX 400000 | |
105 | #define I9XX_VCO_MIN 1400000 | |
106 | #define I9XX_VCO_MAX 2800000 | |
f2b115e6 AJ |
107 | #define PINEVIEW_VCO_MIN 1700000 |
108 | #define PINEVIEW_VCO_MAX 3500000 | |
f3cade5c KH |
109 | #define I9XX_N_MIN 1 |
110 | #define I9XX_N_MAX 6 | |
f2b115e6 AJ |
111 | /* Pineview's Ncounter is a ring counter */ |
112 | #define PINEVIEW_N_MIN 3 | |
113 | #define PINEVIEW_N_MAX 6 | |
79e53945 JB |
114 | #define I9XX_M_MIN 70 |
115 | #define I9XX_M_MAX 120 | |
f2b115e6 AJ |
116 | #define PINEVIEW_M_MIN 2 |
117 | #define PINEVIEW_M_MAX 256 | |
79e53945 | 118 | #define I9XX_M1_MIN 10 |
f3cade5c | 119 | #define I9XX_M1_MAX 22 |
79e53945 JB |
120 | #define I9XX_M2_MIN 5 |
121 | #define I9XX_M2_MAX 9 | |
f2b115e6 AJ |
122 | /* Pineview M1 is reserved, and must be 0 */ |
123 | #define PINEVIEW_M1_MIN 0 | |
124 | #define PINEVIEW_M1_MAX 0 | |
125 | #define PINEVIEW_M2_MIN 0 | |
126 | #define PINEVIEW_M2_MAX 254 | |
79e53945 JB |
127 | #define I9XX_P_SDVO_DAC_MIN 5 |
128 | #define I9XX_P_SDVO_DAC_MAX 80 | |
129 | #define I9XX_P_LVDS_MIN 7 | |
130 | #define I9XX_P_LVDS_MAX 98 | |
f2b115e6 AJ |
131 | #define PINEVIEW_P_LVDS_MIN 7 |
132 | #define PINEVIEW_P_LVDS_MAX 112 | |
79e53945 JB |
133 | #define I9XX_P1_MIN 1 |
134 | #define I9XX_P1_MAX 8 | |
135 | #define I9XX_P2_SDVO_DAC_SLOW 10 | |
136 | #define I9XX_P2_SDVO_DAC_FAST 5 | |
137 | #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000 | |
138 | #define I9XX_P2_LVDS_SLOW 14 | |
139 | #define I9XX_P2_LVDS_FAST 7 | |
140 | #define I9XX_P2_LVDS_SLOW_LIMIT 112000 | |
141 | ||
044c7c41 ML |
142 | /*The parameter is for SDVO on G4x platform*/ |
143 | #define G4X_DOT_SDVO_MIN 25000 | |
144 | #define G4X_DOT_SDVO_MAX 270000 | |
145 | #define G4X_VCO_MIN 1750000 | |
146 | #define G4X_VCO_MAX 3500000 | |
147 | #define G4X_N_SDVO_MIN 1 | |
148 | #define G4X_N_SDVO_MAX 4 | |
149 | #define G4X_M_SDVO_MIN 104 | |
150 | #define G4X_M_SDVO_MAX 138 | |
151 | #define G4X_M1_SDVO_MIN 17 | |
152 | #define G4X_M1_SDVO_MAX 23 | |
153 | #define G4X_M2_SDVO_MIN 5 | |
154 | #define G4X_M2_SDVO_MAX 11 | |
155 | #define G4X_P_SDVO_MIN 10 | |
156 | #define G4X_P_SDVO_MAX 30 | |
157 | #define G4X_P1_SDVO_MIN 1 | |
158 | #define G4X_P1_SDVO_MAX 3 | |
159 | #define G4X_P2_SDVO_SLOW 10 | |
160 | #define G4X_P2_SDVO_FAST 10 | |
161 | #define G4X_P2_SDVO_LIMIT 270000 | |
162 | ||
163 | /*The parameter is for HDMI_DAC on G4x platform*/ | |
164 | #define G4X_DOT_HDMI_DAC_MIN 22000 | |
165 | #define G4X_DOT_HDMI_DAC_MAX 400000 | |
166 | #define G4X_N_HDMI_DAC_MIN 1 | |
167 | #define G4X_N_HDMI_DAC_MAX 4 | |
168 | #define G4X_M_HDMI_DAC_MIN 104 | |
169 | #define G4X_M_HDMI_DAC_MAX 138 | |
170 | #define G4X_M1_HDMI_DAC_MIN 16 | |
171 | #define G4X_M1_HDMI_DAC_MAX 23 | |
172 | #define G4X_M2_HDMI_DAC_MIN 5 | |
173 | #define G4X_M2_HDMI_DAC_MAX 11 | |
174 | #define G4X_P_HDMI_DAC_MIN 5 | |
175 | #define G4X_P_HDMI_DAC_MAX 80 | |
176 | #define G4X_P1_HDMI_DAC_MIN 1 | |
177 | #define G4X_P1_HDMI_DAC_MAX 8 | |
178 | #define G4X_P2_HDMI_DAC_SLOW 10 | |
179 | #define G4X_P2_HDMI_DAC_FAST 5 | |
180 | #define G4X_P2_HDMI_DAC_LIMIT 165000 | |
181 | ||
182 | /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/ | |
183 | #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000 | |
184 | #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000 | |
185 | #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1 | |
186 | #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3 | |
187 | #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104 | |
188 | #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138 | |
189 | #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17 | |
190 | #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23 | |
191 | #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5 | |
192 | #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11 | |
193 | #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28 | |
194 | #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112 | |
195 | #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2 | |
196 | #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8 | |
197 | #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14 | |
198 | #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14 | |
199 | #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0 | |
200 | ||
201 | /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/ | |
202 | #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000 | |
203 | #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000 | |
204 | #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1 | |
205 | #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3 | |
206 | #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104 | |
207 | #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138 | |
208 | #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17 | |
209 | #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23 | |
210 | #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5 | |
211 | #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11 | |
212 | #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14 | |
213 | #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42 | |
214 | #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2 | |
215 | #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6 | |
216 | #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7 | |
217 | #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7 | |
218 | #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0 | |
219 | ||
a4fc5ed6 KP |
220 | /*The parameter is for DISPLAY PORT on G4x platform*/ |
221 | #define G4X_DOT_DISPLAY_PORT_MIN 161670 | |
222 | #define G4X_DOT_DISPLAY_PORT_MAX 227000 | |
223 | #define G4X_N_DISPLAY_PORT_MIN 1 | |
224 | #define G4X_N_DISPLAY_PORT_MAX 2 | |
225 | #define G4X_M_DISPLAY_PORT_MIN 97 | |
226 | #define G4X_M_DISPLAY_PORT_MAX 108 | |
227 | #define G4X_M1_DISPLAY_PORT_MIN 0x10 | |
228 | #define G4X_M1_DISPLAY_PORT_MAX 0x12 | |
229 | #define G4X_M2_DISPLAY_PORT_MIN 0x05 | |
230 | #define G4X_M2_DISPLAY_PORT_MAX 0x06 | |
231 | #define G4X_P_DISPLAY_PORT_MIN 10 | |
232 | #define G4X_P_DISPLAY_PORT_MAX 20 | |
233 | #define G4X_P1_DISPLAY_PORT_MIN 1 | |
234 | #define G4X_P1_DISPLAY_PORT_MAX 2 | |
235 | #define G4X_P2_DISPLAY_PORT_SLOW 10 | |
236 | #define G4X_P2_DISPLAY_PORT_FAST 10 | |
237 | #define G4X_P2_DISPLAY_PORT_LIMIT 0 | |
238 | ||
bad720ff | 239 | /* Ironlake / Sandybridge */ |
2c07245f ZW |
240 | /* as we calculate clock using (register_value + 2) for |
241 | N/M1/M2, so here the range value for them is (actual_value-2). | |
242 | */ | |
f2b115e6 AJ |
243 | #define IRONLAKE_DOT_MIN 25000 |
244 | #define IRONLAKE_DOT_MAX 350000 | |
245 | #define IRONLAKE_VCO_MIN 1760000 | |
246 | #define IRONLAKE_VCO_MAX 3510000 | |
f2b115e6 | 247 | #define IRONLAKE_M1_MIN 12 |
a59e385e | 248 | #define IRONLAKE_M1_MAX 22 |
f2b115e6 AJ |
249 | #define IRONLAKE_M2_MIN 5 |
250 | #define IRONLAKE_M2_MAX 9 | |
f2b115e6 | 251 | #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */ |
2c07245f | 252 | |
b91ad0ec ZW |
253 | /* We have parameter ranges for different type of outputs. */ |
254 | ||
255 | /* DAC & HDMI Refclk 120Mhz */ | |
256 | #define IRONLAKE_DAC_N_MIN 1 | |
257 | #define IRONLAKE_DAC_N_MAX 5 | |
258 | #define IRONLAKE_DAC_M_MIN 79 | |
259 | #define IRONLAKE_DAC_M_MAX 127 | |
260 | #define IRONLAKE_DAC_P_MIN 5 | |
261 | #define IRONLAKE_DAC_P_MAX 80 | |
262 | #define IRONLAKE_DAC_P1_MIN 1 | |
263 | #define IRONLAKE_DAC_P1_MAX 8 | |
264 | #define IRONLAKE_DAC_P2_SLOW 10 | |
265 | #define IRONLAKE_DAC_P2_FAST 5 | |
266 | ||
267 | /* LVDS single-channel 120Mhz refclk */ | |
268 | #define IRONLAKE_LVDS_S_N_MIN 1 | |
269 | #define IRONLAKE_LVDS_S_N_MAX 3 | |
270 | #define IRONLAKE_LVDS_S_M_MIN 79 | |
271 | #define IRONLAKE_LVDS_S_M_MAX 118 | |
272 | #define IRONLAKE_LVDS_S_P_MIN 28 | |
273 | #define IRONLAKE_LVDS_S_P_MAX 112 | |
274 | #define IRONLAKE_LVDS_S_P1_MIN 2 | |
275 | #define IRONLAKE_LVDS_S_P1_MAX 8 | |
276 | #define IRONLAKE_LVDS_S_P2_SLOW 14 | |
277 | #define IRONLAKE_LVDS_S_P2_FAST 14 | |
278 | ||
279 | /* LVDS dual-channel 120Mhz refclk */ | |
280 | #define IRONLAKE_LVDS_D_N_MIN 1 | |
281 | #define IRONLAKE_LVDS_D_N_MAX 3 | |
282 | #define IRONLAKE_LVDS_D_M_MIN 79 | |
283 | #define IRONLAKE_LVDS_D_M_MAX 127 | |
284 | #define IRONLAKE_LVDS_D_P_MIN 14 | |
285 | #define IRONLAKE_LVDS_D_P_MAX 56 | |
286 | #define IRONLAKE_LVDS_D_P1_MIN 2 | |
287 | #define IRONLAKE_LVDS_D_P1_MAX 8 | |
288 | #define IRONLAKE_LVDS_D_P2_SLOW 7 | |
289 | #define IRONLAKE_LVDS_D_P2_FAST 7 | |
290 | ||
291 | /* LVDS single-channel 100Mhz refclk */ | |
292 | #define IRONLAKE_LVDS_S_SSC_N_MIN 1 | |
293 | #define IRONLAKE_LVDS_S_SSC_N_MAX 2 | |
294 | #define IRONLAKE_LVDS_S_SSC_M_MIN 79 | |
295 | #define IRONLAKE_LVDS_S_SSC_M_MAX 126 | |
296 | #define IRONLAKE_LVDS_S_SSC_P_MIN 28 | |
297 | #define IRONLAKE_LVDS_S_SSC_P_MAX 112 | |
298 | #define IRONLAKE_LVDS_S_SSC_P1_MIN 2 | |
299 | #define IRONLAKE_LVDS_S_SSC_P1_MAX 8 | |
300 | #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14 | |
301 | #define IRONLAKE_LVDS_S_SSC_P2_FAST 14 | |
302 | ||
303 | /* LVDS dual-channel 100Mhz refclk */ | |
304 | #define IRONLAKE_LVDS_D_SSC_N_MIN 1 | |
305 | #define IRONLAKE_LVDS_D_SSC_N_MAX 3 | |
306 | #define IRONLAKE_LVDS_D_SSC_M_MIN 79 | |
307 | #define IRONLAKE_LVDS_D_SSC_M_MAX 126 | |
308 | #define IRONLAKE_LVDS_D_SSC_P_MIN 14 | |
309 | #define IRONLAKE_LVDS_D_SSC_P_MAX 42 | |
310 | #define IRONLAKE_LVDS_D_SSC_P1_MIN 2 | |
311 | #define IRONLAKE_LVDS_D_SSC_P1_MAX 6 | |
312 | #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7 | |
313 | #define IRONLAKE_LVDS_D_SSC_P2_FAST 7 | |
314 | ||
315 | /* DisplayPort */ | |
316 | #define IRONLAKE_DP_N_MIN 1 | |
317 | #define IRONLAKE_DP_N_MAX 2 | |
318 | #define IRONLAKE_DP_M_MIN 81 | |
319 | #define IRONLAKE_DP_M_MAX 90 | |
320 | #define IRONLAKE_DP_P_MIN 10 | |
321 | #define IRONLAKE_DP_P_MAX 20 | |
322 | #define IRONLAKE_DP_P2_FAST 10 | |
323 | #define IRONLAKE_DP_P2_SLOW 10 | |
324 | #define IRONLAKE_DP_P2_LIMIT 0 | |
325 | #define IRONLAKE_DP_P1_MIN 1 | |
326 | #define IRONLAKE_DP_P1_MAX 2 | |
4547668a | 327 | |
2377b741 JB |
328 | /* FDI */ |
329 | #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */ | |
330 | ||
d4906093 ML |
331 | static bool |
332 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
333 | int target, int refclk, intel_clock_t *best_clock); | |
334 | static bool | |
335 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
336 | int target, int refclk, intel_clock_t *best_clock); | |
79e53945 | 337 | |
a4fc5ed6 KP |
338 | static bool |
339 | intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc, | |
340 | int target, int refclk, intel_clock_t *best_clock); | |
5eb08b69 | 341 | static bool |
f2b115e6 AJ |
342 | intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc, |
343 | int target, int refclk, intel_clock_t *best_clock); | |
a4fc5ed6 | 344 | |
e4b36699 | 345 | static const intel_limit_t intel_limits_i8xx_dvo = { |
79e53945 JB |
346 | .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX }, |
347 | .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX }, | |
348 | .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX }, | |
349 | .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX }, | |
350 | .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX }, | |
351 | .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX }, | |
352 | .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX }, | |
353 | .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX }, | |
354 | .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, | |
355 | .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST }, | |
d4906093 | 356 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
357 | }; |
358 | ||
359 | static const intel_limit_t intel_limits_i8xx_lvds = { | |
79e53945 JB |
360 | .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX }, |
361 | .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX }, | |
362 | .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX }, | |
363 | .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX }, | |
364 | .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX }, | |
365 | .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX }, | |
366 | .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX }, | |
367 | .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX }, | |
368 | .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, | |
369 | .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST }, | |
d4906093 | 370 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
371 | }; |
372 | ||
373 | static const intel_limit_t intel_limits_i9xx_sdvo = { | |
79e53945 JB |
374 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, |
375 | .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX }, | |
376 | .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX }, | |
377 | .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX }, | |
378 | .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX }, | |
379 | .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX }, | |
380 | .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX }, | |
381 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, | |
382 | .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, | |
383 | .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, | |
d4906093 | 384 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
385 | }; |
386 | ||
387 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
79e53945 JB |
388 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, |
389 | .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX }, | |
390 | .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX }, | |
391 | .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX }, | |
392 | .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX }, | |
393 | .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX }, | |
394 | .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX }, | |
395 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, | |
396 | /* The single-channel range is 25-112Mhz, and dual-channel | |
397 | * is 80-224Mhz. Prefer single channel as much as possible. | |
398 | */ | |
399 | .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, | |
400 | .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST }, | |
d4906093 | 401 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
402 | }; |
403 | ||
044c7c41 | 404 | /* below parameter and function is for G4X Chipset Family*/ |
e4b36699 | 405 | static const intel_limit_t intel_limits_g4x_sdvo = { |
044c7c41 ML |
406 | .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX }, |
407 | .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX}, | |
408 | .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX }, | |
409 | .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX }, | |
410 | .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX }, | |
411 | .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX }, | |
412 | .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX }, | |
413 | .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX}, | |
414 | .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT, | |
415 | .p2_slow = G4X_P2_SDVO_SLOW, | |
416 | .p2_fast = G4X_P2_SDVO_FAST | |
417 | }, | |
d4906093 | 418 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
419 | }; |
420 | ||
421 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
044c7c41 ML |
422 | .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX }, |
423 | .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX}, | |
424 | .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX }, | |
425 | .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX }, | |
426 | .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX }, | |
427 | .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX }, | |
428 | .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX }, | |
429 | .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX}, | |
430 | .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT, | |
431 | .p2_slow = G4X_P2_HDMI_DAC_SLOW, | |
432 | .p2_fast = G4X_P2_HDMI_DAC_FAST | |
433 | }, | |
d4906093 | 434 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
435 | }; |
436 | ||
437 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
044c7c41 ML |
438 | .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN, |
439 | .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX }, | |
440 | .vco = { .min = G4X_VCO_MIN, | |
441 | .max = G4X_VCO_MAX }, | |
442 | .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN, | |
443 | .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX }, | |
444 | .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN, | |
445 | .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX }, | |
446 | .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN, | |
447 | .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX }, | |
448 | .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN, | |
449 | .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX }, | |
450 | .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN, | |
451 | .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX }, | |
452 | .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN, | |
453 | .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX }, | |
454 | .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT, | |
455 | .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW, | |
456 | .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST | |
457 | }, | |
d4906093 | 458 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
459 | }; |
460 | ||
461 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
044c7c41 ML |
462 | .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN, |
463 | .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX }, | |
464 | .vco = { .min = G4X_VCO_MIN, | |
465 | .max = G4X_VCO_MAX }, | |
466 | .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN, | |
467 | .max = G4X_N_DUAL_CHANNEL_LVDS_MAX }, | |
468 | .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN, | |
469 | .max = G4X_M_DUAL_CHANNEL_LVDS_MAX }, | |
470 | .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN, | |
471 | .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX }, | |
472 | .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN, | |
473 | .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX }, | |
474 | .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN, | |
475 | .max = G4X_P_DUAL_CHANNEL_LVDS_MAX }, | |
476 | .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN, | |
477 | .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX }, | |
478 | .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT, | |
479 | .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW, | |
480 | .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST | |
481 | }, | |
d4906093 | 482 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
483 | }; |
484 | ||
485 | static const intel_limit_t intel_limits_g4x_display_port = { | |
a4fc5ed6 KP |
486 | .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN, |
487 | .max = G4X_DOT_DISPLAY_PORT_MAX }, | |
488 | .vco = { .min = G4X_VCO_MIN, | |
489 | .max = G4X_VCO_MAX}, | |
490 | .n = { .min = G4X_N_DISPLAY_PORT_MIN, | |
491 | .max = G4X_N_DISPLAY_PORT_MAX }, | |
492 | .m = { .min = G4X_M_DISPLAY_PORT_MIN, | |
493 | .max = G4X_M_DISPLAY_PORT_MAX }, | |
494 | .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN, | |
495 | .max = G4X_M1_DISPLAY_PORT_MAX }, | |
496 | .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN, | |
497 | .max = G4X_M2_DISPLAY_PORT_MAX }, | |
498 | .p = { .min = G4X_P_DISPLAY_PORT_MIN, | |
499 | .max = G4X_P_DISPLAY_PORT_MAX }, | |
500 | .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN, | |
501 | .max = G4X_P1_DISPLAY_PORT_MAX}, | |
502 | .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT, | |
503 | .p2_slow = G4X_P2_DISPLAY_PORT_SLOW, | |
504 | .p2_fast = G4X_P2_DISPLAY_PORT_FAST }, | |
505 | .find_pll = intel_find_pll_g4x_dp, | |
e4b36699 KP |
506 | }; |
507 | ||
f2b115e6 | 508 | static const intel_limit_t intel_limits_pineview_sdvo = { |
2177832f | 509 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX}, |
f2b115e6 AJ |
510 | .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX }, |
511 | .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX }, | |
512 | .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX }, | |
513 | .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX }, | |
514 | .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX }, | |
2177832f SL |
515 | .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX }, |
516 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, | |
517 | .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, | |
518 | .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, | |
6115707b | 519 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
520 | }; |
521 | ||
f2b115e6 | 522 | static const intel_limit_t intel_limits_pineview_lvds = { |
2177832f | 523 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, |
f2b115e6 AJ |
524 | .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX }, |
525 | .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX }, | |
526 | .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX }, | |
527 | .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX }, | |
528 | .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX }, | |
529 | .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX }, | |
2177832f | 530 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, |
f2b115e6 | 531 | /* Pineview only supports single-channel mode. */ |
2177832f SL |
532 | .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, |
533 | .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW }, | |
6115707b | 534 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
535 | }; |
536 | ||
b91ad0ec | 537 | static const intel_limit_t intel_limits_ironlake_dac = { |
f2b115e6 AJ |
538 | .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, |
539 | .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, | |
b91ad0ec ZW |
540 | .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX }, |
541 | .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX }, | |
f2b115e6 AJ |
542 | .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, |
543 | .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, | |
b91ad0ec ZW |
544 | .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX }, |
545 | .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX }, | |
f2b115e6 | 546 | .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, |
b91ad0ec ZW |
547 | .p2_slow = IRONLAKE_DAC_P2_SLOW, |
548 | .p2_fast = IRONLAKE_DAC_P2_FAST }, | |
4547668a | 549 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
550 | }; |
551 | ||
b91ad0ec | 552 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
f2b115e6 AJ |
553 | .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, |
554 | .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, | |
b91ad0ec ZW |
555 | .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX }, |
556 | .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX }, | |
f2b115e6 AJ |
557 | .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, |
558 | .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, | |
b91ad0ec ZW |
559 | .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX }, |
560 | .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX }, | |
f2b115e6 | 561 | .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, |
b91ad0ec ZW |
562 | .p2_slow = IRONLAKE_LVDS_S_P2_SLOW, |
563 | .p2_fast = IRONLAKE_LVDS_S_P2_FAST }, | |
564 | .find_pll = intel_g4x_find_best_PLL, | |
565 | }; | |
566 | ||
567 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
568 | .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, | |
569 | .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, | |
570 | .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX }, | |
571 | .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX }, | |
572 | .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, | |
573 | .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, | |
574 | .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX }, | |
575 | .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX }, | |
576 | .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, | |
577 | .p2_slow = IRONLAKE_LVDS_D_P2_SLOW, | |
578 | .p2_fast = IRONLAKE_LVDS_D_P2_FAST }, | |
579 | .find_pll = intel_g4x_find_best_PLL, | |
580 | }; | |
581 | ||
582 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { | |
583 | .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, | |
584 | .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, | |
585 | .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX }, | |
586 | .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX }, | |
587 | .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, | |
588 | .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, | |
589 | .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX }, | |
590 | .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX }, | |
591 | .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, | |
592 | .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW, | |
593 | .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST }, | |
594 | .find_pll = intel_g4x_find_best_PLL, | |
595 | }; | |
596 | ||
597 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
598 | .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, | |
599 | .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, | |
600 | .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX }, | |
601 | .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX }, | |
602 | .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, | |
603 | .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, | |
604 | .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX }, | |
605 | .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX }, | |
606 | .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, | |
607 | .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW, | |
608 | .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST }, | |
4547668a ZY |
609 | .find_pll = intel_g4x_find_best_PLL, |
610 | }; | |
611 | ||
612 | static const intel_limit_t intel_limits_ironlake_display_port = { | |
613 | .dot = { .min = IRONLAKE_DOT_MIN, | |
614 | .max = IRONLAKE_DOT_MAX }, | |
615 | .vco = { .min = IRONLAKE_VCO_MIN, | |
616 | .max = IRONLAKE_VCO_MAX}, | |
b91ad0ec ZW |
617 | .n = { .min = IRONLAKE_DP_N_MIN, |
618 | .max = IRONLAKE_DP_N_MAX }, | |
619 | .m = { .min = IRONLAKE_DP_M_MIN, | |
620 | .max = IRONLAKE_DP_M_MAX }, | |
4547668a ZY |
621 | .m1 = { .min = IRONLAKE_M1_MIN, |
622 | .max = IRONLAKE_M1_MAX }, | |
623 | .m2 = { .min = IRONLAKE_M2_MIN, | |
624 | .max = IRONLAKE_M2_MAX }, | |
b91ad0ec ZW |
625 | .p = { .min = IRONLAKE_DP_P_MIN, |
626 | .max = IRONLAKE_DP_P_MAX }, | |
627 | .p1 = { .min = IRONLAKE_DP_P1_MIN, | |
628 | .max = IRONLAKE_DP_P1_MAX}, | |
629 | .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT, | |
630 | .p2_slow = IRONLAKE_DP_P2_SLOW, | |
631 | .p2_fast = IRONLAKE_DP_P2_FAST }, | |
4547668a | 632 | .find_pll = intel_find_pll_ironlake_dp, |
79e53945 JB |
633 | }; |
634 | ||
f2b115e6 | 635 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc) |
2c07245f | 636 | { |
b91ad0ec ZW |
637 | struct drm_device *dev = crtc->dev; |
638 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2c07245f | 639 | const intel_limit_t *limit; |
b91ad0ec ZW |
640 | int refclk = 120; |
641 | ||
642 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
643 | if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100) | |
644 | refclk = 100; | |
645 | ||
646 | if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == | |
647 | LVDS_CLKB_POWER_UP) { | |
648 | /* LVDS dual channel */ | |
649 | if (refclk == 100) | |
650 | limit = &intel_limits_ironlake_dual_lvds_100m; | |
651 | else | |
652 | limit = &intel_limits_ironlake_dual_lvds; | |
653 | } else { | |
654 | if (refclk == 100) | |
655 | limit = &intel_limits_ironlake_single_lvds_100m; | |
656 | else | |
657 | limit = &intel_limits_ironlake_single_lvds; | |
658 | } | |
659 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || | |
4547668a ZY |
660 | HAS_eDP) |
661 | limit = &intel_limits_ironlake_display_port; | |
2c07245f | 662 | else |
b91ad0ec | 663 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
664 | |
665 | return limit; | |
666 | } | |
667 | ||
044c7c41 ML |
668 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
669 | { | |
670 | struct drm_device *dev = crtc->dev; | |
671 | struct drm_i915_private *dev_priv = dev->dev_private; | |
672 | const intel_limit_t *limit; | |
673 | ||
674 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
675 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == | |
676 | LVDS_CLKB_POWER_UP) | |
677 | /* LVDS with dual channel */ | |
e4b36699 | 678 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 ML |
679 | else |
680 | /* LVDS with dual channel */ | |
e4b36699 | 681 | limit = &intel_limits_g4x_single_channel_lvds; |
044c7c41 ML |
682 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
683 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 684 | limit = &intel_limits_g4x_hdmi; |
044c7c41 | 685 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 686 | limit = &intel_limits_g4x_sdvo; |
a4fc5ed6 | 687 | } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
e4b36699 | 688 | limit = &intel_limits_g4x_display_port; |
044c7c41 | 689 | } else /* The option is for other outputs */ |
e4b36699 | 690 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
691 | |
692 | return limit; | |
693 | } | |
694 | ||
79e53945 JB |
695 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc) |
696 | { | |
697 | struct drm_device *dev = crtc->dev; | |
698 | const intel_limit_t *limit; | |
699 | ||
bad720ff | 700 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 701 | limit = intel_ironlake_limit(crtc); |
2c07245f | 702 | else if (IS_G4X(dev)) { |
044c7c41 | 703 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 704 | } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) { |
79e53945 | 705 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
e4b36699 | 706 | limit = &intel_limits_i9xx_lvds; |
79e53945 | 707 | else |
e4b36699 | 708 | limit = &intel_limits_i9xx_sdvo; |
f2b115e6 | 709 | } else if (IS_PINEVIEW(dev)) { |
2177832f | 710 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 711 | limit = &intel_limits_pineview_lvds; |
2177832f | 712 | else |
f2b115e6 | 713 | limit = &intel_limits_pineview_sdvo; |
79e53945 JB |
714 | } else { |
715 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 716 | limit = &intel_limits_i8xx_lvds; |
79e53945 | 717 | else |
e4b36699 | 718 | limit = &intel_limits_i8xx_dvo; |
79e53945 JB |
719 | } |
720 | return limit; | |
721 | } | |
722 | ||
f2b115e6 AJ |
723 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
724 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 725 | { |
2177832f SL |
726 | clock->m = clock->m2 + 2; |
727 | clock->p = clock->p1 * clock->p2; | |
728 | clock->vco = refclk * clock->m / clock->n; | |
729 | clock->dot = clock->vco / clock->p; | |
730 | } | |
731 | ||
732 | static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock) | |
733 | { | |
f2b115e6 AJ |
734 | if (IS_PINEVIEW(dev)) { |
735 | pineview_clock(refclk, clock); | |
2177832f SL |
736 | return; |
737 | } | |
79e53945 JB |
738 | clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); |
739 | clock->p = clock->p1 * clock->p2; | |
740 | clock->vco = refclk * clock->m / (clock->n + 2); | |
741 | clock->dot = clock->vco / clock->p; | |
742 | } | |
743 | ||
79e53945 JB |
744 | /** |
745 | * Returns whether any output on the specified pipe is of the specified type | |
746 | */ | |
4ef69c7a | 747 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type) |
79e53945 | 748 | { |
4ef69c7a CW |
749 | struct drm_device *dev = crtc->dev; |
750 | struct drm_mode_config *mode_config = &dev->mode_config; | |
751 | struct intel_encoder *encoder; | |
752 | ||
753 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) | |
754 | if (encoder->base.crtc == crtc && encoder->type == type) | |
755 | return true; | |
756 | ||
757 | return false; | |
79e53945 JB |
758 | } |
759 | ||
7c04d1d9 | 760 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
761 | /** |
762 | * Returns whether the given set of divisors are valid for a given refclk with | |
763 | * the given connectors. | |
764 | */ | |
765 | ||
766 | static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock) | |
767 | { | |
768 | const intel_limit_t *limit = intel_limit (crtc); | |
2177832f | 769 | struct drm_device *dev = crtc->dev; |
79e53945 JB |
770 | |
771 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) | |
772 | INTELPllInvalid ("p1 out of range\n"); | |
773 | if (clock->p < limit->p.min || limit->p.max < clock->p) | |
774 | INTELPllInvalid ("p out of range\n"); | |
775 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) | |
776 | INTELPllInvalid ("m2 out of range\n"); | |
777 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) | |
778 | INTELPllInvalid ("m1 out of range\n"); | |
f2b115e6 | 779 | if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev)) |
79e53945 JB |
780 | INTELPllInvalid ("m1 <= m2\n"); |
781 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
782 | INTELPllInvalid ("m out of range\n"); | |
783 | if (clock->n < limit->n.min || limit->n.max < clock->n) | |
784 | INTELPllInvalid ("n out of range\n"); | |
785 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) | |
786 | INTELPllInvalid ("vco out of range\n"); | |
787 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, | |
788 | * connector, etc., rather than just a single range. | |
789 | */ | |
790 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
791 | INTELPllInvalid ("dot out of range\n"); | |
792 | ||
793 | return true; | |
794 | } | |
795 | ||
d4906093 ML |
796 | static bool |
797 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
798 | int target, int refclk, intel_clock_t *best_clock) | |
799 | ||
79e53945 JB |
800 | { |
801 | struct drm_device *dev = crtc->dev; | |
802 | struct drm_i915_private *dev_priv = dev->dev_private; | |
803 | intel_clock_t clock; | |
79e53945 JB |
804 | int err = target; |
805 | ||
bc5e5718 | 806 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
832cc28d | 807 | (I915_READ(LVDS)) != 0) { |
79e53945 JB |
808 | /* |
809 | * For LVDS, if the panel is on, just rely on its current | |
810 | * settings for dual-channel. We haven't figured out how to | |
811 | * reliably set up different single/dual channel state, if we | |
812 | * even can. | |
813 | */ | |
814 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == | |
815 | LVDS_CLKB_POWER_UP) | |
816 | clock.p2 = limit->p2.p2_fast; | |
817 | else | |
818 | clock.p2 = limit->p2.p2_slow; | |
819 | } else { | |
820 | if (target < limit->p2.dot_limit) | |
821 | clock.p2 = limit->p2.p2_slow; | |
822 | else | |
823 | clock.p2 = limit->p2.p2_fast; | |
824 | } | |
825 | ||
826 | memset (best_clock, 0, sizeof (*best_clock)); | |
827 | ||
42158660 ZY |
828 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
829 | clock.m1++) { | |
830 | for (clock.m2 = limit->m2.min; | |
831 | clock.m2 <= limit->m2.max; clock.m2++) { | |
f2b115e6 AJ |
832 | /* m1 is always 0 in Pineview */ |
833 | if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev)) | |
42158660 ZY |
834 | break; |
835 | for (clock.n = limit->n.min; | |
836 | clock.n <= limit->n.max; clock.n++) { | |
837 | for (clock.p1 = limit->p1.min; | |
838 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
839 | int this_err; |
840 | ||
2177832f | 841 | intel_clock(dev, refclk, &clock); |
79e53945 JB |
842 | |
843 | if (!intel_PLL_is_valid(crtc, &clock)) | |
844 | continue; | |
845 | ||
846 | this_err = abs(clock.dot - target); | |
847 | if (this_err < err) { | |
848 | *best_clock = clock; | |
849 | err = this_err; | |
850 | } | |
851 | } | |
852 | } | |
853 | } | |
854 | } | |
855 | ||
856 | return (err != target); | |
857 | } | |
858 | ||
d4906093 ML |
859 | static bool |
860 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
861 | int target, int refclk, intel_clock_t *best_clock) | |
862 | { | |
863 | struct drm_device *dev = crtc->dev; | |
864 | struct drm_i915_private *dev_priv = dev->dev_private; | |
865 | intel_clock_t clock; | |
866 | int max_n; | |
867 | bool found; | |
6ba770dc AJ |
868 | /* approximately equals target * 0.00585 */ |
869 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
870 | found = false; |
871 | ||
872 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
4547668a ZY |
873 | int lvds_reg; |
874 | ||
c619eed4 | 875 | if (HAS_PCH_SPLIT(dev)) |
4547668a ZY |
876 | lvds_reg = PCH_LVDS; |
877 | else | |
878 | lvds_reg = LVDS; | |
879 | if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) == | |
d4906093 ML |
880 | LVDS_CLKB_POWER_UP) |
881 | clock.p2 = limit->p2.p2_fast; | |
882 | else | |
883 | clock.p2 = limit->p2.p2_slow; | |
884 | } else { | |
885 | if (target < limit->p2.dot_limit) | |
886 | clock.p2 = limit->p2.p2_slow; | |
887 | else | |
888 | clock.p2 = limit->p2.p2_fast; | |
889 | } | |
890 | ||
891 | memset(best_clock, 0, sizeof(*best_clock)); | |
892 | max_n = limit->n.max; | |
f77f13e2 | 893 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 894 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 895 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
896 | for (clock.m1 = limit->m1.max; |
897 | clock.m1 >= limit->m1.min; clock.m1--) { | |
898 | for (clock.m2 = limit->m2.max; | |
899 | clock.m2 >= limit->m2.min; clock.m2--) { | |
900 | for (clock.p1 = limit->p1.max; | |
901 | clock.p1 >= limit->p1.min; clock.p1--) { | |
902 | int this_err; | |
903 | ||
2177832f | 904 | intel_clock(dev, refclk, &clock); |
d4906093 ML |
905 | if (!intel_PLL_is_valid(crtc, &clock)) |
906 | continue; | |
907 | this_err = abs(clock.dot - target) ; | |
908 | if (this_err < err_most) { | |
909 | *best_clock = clock; | |
910 | err_most = this_err; | |
911 | max_n = clock.n; | |
912 | found = true; | |
913 | } | |
914 | } | |
915 | } | |
916 | } | |
917 | } | |
2c07245f ZW |
918 | return found; |
919 | } | |
920 | ||
5eb08b69 | 921 | static bool |
f2b115e6 AJ |
922 | intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc, |
923 | int target, int refclk, intel_clock_t *best_clock) | |
5eb08b69 ZW |
924 | { |
925 | struct drm_device *dev = crtc->dev; | |
926 | intel_clock_t clock; | |
4547668a ZY |
927 | |
928 | /* return directly when it is eDP */ | |
929 | if (HAS_eDP) | |
930 | return true; | |
931 | ||
5eb08b69 ZW |
932 | if (target < 200000) { |
933 | clock.n = 1; | |
934 | clock.p1 = 2; | |
935 | clock.p2 = 10; | |
936 | clock.m1 = 12; | |
937 | clock.m2 = 9; | |
938 | } else { | |
939 | clock.n = 2; | |
940 | clock.p1 = 1; | |
941 | clock.p2 = 10; | |
942 | clock.m1 = 14; | |
943 | clock.m2 = 8; | |
944 | } | |
945 | intel_clock(dev, refclk, &clock); | |
946 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); | |
947 | return true; | |
948 | } | |
949 | ||
a4fc5ed6 KP |
950 | /* DisplayPort has only two frequencies, 162MHz and 270MHz */ |
951 | static bool | |
952 | intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc, | |
953 | int target, int refclk, intel_clock_t *best_clock) | |
954 | { | |
955 | intel_clock_t clock; | |
956 | if (target < 200000) { | |
a4fc5ed6 KP |
957 | clock.p1 = 2; |
958 | clock.p2 = 10; | |
b3d25495 KP |
959 | clock.n = 2; |
960 | clock.m1 = 23; | |
961 | clock.m2 = 8; | |
a4fc5ed6 | 962 | } else { |
a4fc5ed6 KP |
963 | clock.p1 = 1; |
964 | clock.p2 = 10; | |
b3d25495 KP |
965 | clock.n = 1; |
966 | clock.m1 = 14; | |
967 | clock.m2 = 2; | |
a4fc5ed6 | 968 | } |
b3d25495 KP |
969 | clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2); |
970 | clock.p = (clock.p1 * clock.p2); | |
971 | clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p; | |
fe798b97 | 972 | clock.vco = 0; |
a4fc5ed6 KP |
973 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); |
974 | return true; | |
975 | } | |
976 | ||
9d0498a2 JB |
977 | /** |
978 | * intel_wait_for_vblank - wait for vblank on a given pipe | |
979 | * @dev: drm device | |
980 | * @pipe: pipe to wait for | |
981 | * | |
982 | * Wait for vblank to occur on a given pipe. Needed for various bits of | |
983 | * mode setting code. | |
984 | */ | |
985 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
79e53945 | 986 | { |
9d0498a2 JB |
987 | struct drm_i915_private *dev_priv = dev->dev_private; |
988 | int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT); | |
989 | ||
300387c0 CW |
990 | /* Clear existing vblank status. Note this will clear any other |
991 | * sticky status fields as well. | |
992 | * | |
993 | * This races with i915_driver_irq_handler() with the result | |
994 | * that either function could miss a vblank event. Here it is not | |
995 | * fatal, as we will either wait upon the next vblank interrupt or | |
996 | * timeout. Generally speaking intel_wait_for_vblank() is only | |
997 | * called during modeset at which time the GPU should be idle and | |
998 | * should *not* be performing page flips and thus not waiting on | |
999 | * vblanks... | |
1000 | * Currently, the result of us stealing a vblank from the irq | |
1001 | * handler is that a single frame will be skipped during swapbuffers. | |
1002 | */ | |
1003 | I915_WRITE(pipestat_reg, | |
1004 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); | |
1005 | ||
9d0498a2 | 1006 | /* Wait for vblank interrupt bit to set */ |
481b6af3 CW |
1007 | if (wait_for(I915_READ(pipestat_reg) & |
1008 | PIPE_VBLANK_INTERRUPT_STATUS, | |
1009 | 50)) | |
9d0498a2 JB |
1010 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
1011 | } | |
1012 | ||
1013 | /** | |
1014 | * intel_wait_for_vblank_off - wait for vblank after disabling a pipe | |
1015 | * @dev: drm device | |
1016 | * @pipe: pipe to wait for | |
1017 | * | |
1018 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1019 | * spinning on the vblank interrupt status bit, since we won't actually | |
1020 | * see an interrupt when the pipe is disabled. | |
1021 | * | |
1022 | * So this function waits for the display line value to settle (it | |
1023 | * usually ends up stopping at the start of the next frame). | |
1024 | */ | |
1025 | void intel_wait_for_vblank_off(struct drm_device *dev, int pipe) | |
1026 | { | |
1027 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1028 | int pipedsl_reg = (pipe == 0 ? PIPEADSL : PIPEBDSL); | |
1029 | unsigned long timeout = jiffies + msecs_to_jiffies(100); | |
1030 | u32 last_line; | |
1031 | ||
1032 | /* Wait for the display line to settle */ | |
1033 | do { | |
1034 | last_line = I915_READ(pipedsl_reg) & DSL_LINEMASK; | |
1035 | mdelay(5); | |
1036 | } while (((I915_READ(pipedsl_reg) & DSL_LINEMASK) != last_line) && | |
1037 | time_after(timeout, jiffies)); | |
1038 | ||
1039 | if (time_after(jiffies, timeout)) | |
1040 | DRM_DEBUG_KMS("vblank wait timed out\n"); | |
79e53945 JB |
1041 | } |
1042 | ||
80824003 JB |
1043 | /* Parameters have changed, update FBC info */ |
1044 | static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval) | |
1045 | { | |
1046 | struct drm_device *dev = crtc->dev; | |
1047 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1048 | struct drm_framebuffer *fb = crtc->fb; | |
1049 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
23010e43 | 1050 | struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj); |
80824003 JB |
1051 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1052 | int plane, i; | |
1053 | u32 fbc_ctl, fbc_ctl2; | |
1054 | ||
1055 | dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE; | |
1056 | ||
1057 | if (fb->pitch < dev_priv->cfb_pitch) | |
1058 | dev_priv->cfb_pitch = fb->pitch; | |
1059 | ||
1060 | /* FBC_CTL wants 64B units */ | |
1061 | dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1; | |
1062 | dev_priv->cfb_fence = obj_priv->fence_reg; | |
1063 | dev_priv->cfb_plane = intel_crtc->plane; | |
1064 | plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB; | |
1065 | ||
1066 | /* Clear old tags */ | |
1067 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) | |
1068 | I915_WRITE(FBC_TAG + (i * 4), 0); | |
1069 | ||
1070 | /* Set it up... */ | |
1071 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane; | |
1072 | if (obj_priv->tiling_mode != I915_TILING_NONE) | |
1073 | fbc_ctl2 |= FBC_CTL_CPU_FENCE; | |
1074 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); | |
1075 | I915_WRITE(FBC_FENCE_OFF, crtc->y); | |
1076 | ||
1077 | /* enable it... */ | |
1078 | fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC; | |
ee25df2b | 1079 | if (IS_I945GM(dev)) |
49677901 | 1080 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ |
80824003 JB |
1081 | fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; |
1082 | fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT; | |
1083 | if (obj_priv->tiling_mode != I915_TILING_NONE) | |
1084 | fbc_ctl |= dev_priv->cfb_fence; | |
1085 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
1086 | ||
28c97730 | 1087 | DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ", |
80824003 JB |
1088 | dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane); |
1089 | } | |
1090 | ||
1091 | void i8xx_disable_fbc(struct drm_device *dev) | |
1092 | { | |
1093 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1094 | u32 fbc_ctl; | |
1095 | ||
c1a1cdc1 JB |
1096 | if (!I915_HAS_FBC(dev)) |
1097 | return; | |
1098 | ||
9517a92f JB |
1099 | if (!(I915_READ(FBC_CONTROL) & FBC_CTL_EN)) |
1100 | return; /* Already off, just return */ | |
1101 | ||
80824003 JB |
1102 | /* Disable compression */ |
1103 | fbc_ctl = I915_READ(FBC_CONTROL); | |
1104 | fbc_ctl &= ~FBC_CTL_EN; | |
1105 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
1106 | ||
1107 | /* Wait for compressing bit to clear */ | |
481b6af3 | 1108 | if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { |
913d8d11 CW |
1109 | DRM_DEBUG_KMS("FBC idle timed out\n"); |
1110 | return; | |
9517a92f | 1111 | } |
80824003 | 1112 | |
28c97730 | 1113 | DRM_DEBUG_KMS("disabled FBC\n"); |
80824003 JB |
1114 | } |
1115 | ||
ee5382ae | 1116 | static bool i8xx_fbc_enabled(struct drm_device *dev) |
80824003 | 1117 | { |
80824003 JB |
1118 | struct drm_i915_private *dev_priv = dev->dev_private; |
1119 | ||
1120 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; | |
1121 | } | |
1122 | ||
74dff282 JB |
1123 | static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
1124 | { | |
1125 | struct drm_device *dev = crtc->dev; | |
1126 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1127 | struct drm_framebuffer *fb = crtc->fb; | |
1128 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
23010e43 | 1129 | struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj); |
74dff282 JB |
1130 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1131 | int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : | |
1132 | DPFC_CTL_PLANEB); | |
1133 | unsigned long stall_watermark = 200; | |
1134 | u32 dpfc_ctl; | |
1135 | ||
1136 | dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1; | |
1137 | dev_priv->cfb_fence = obj_priv->fence_reg; | |
1138 | dev_priv->cfb_plane = intel_crtc->plane; | |
1139 | ||
1140 | dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X; | |
1141 | if (obj_priv->tiling_mode != I915_TILING_NONE) { | |
1142 | dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence; | |
1143 | I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY); | |
1144 | } else { | |
1145 | I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY); | |
1146 | } | |
1147 | ||
1148 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); | |
1149 | I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | | |
1150 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | | |
1151 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); | |
1152 | I915_WRITE(DPFC_FENCE_YOFF, crtc->y); | |
1153 | ||
1154 | /* enable it... */ | |
1155 | I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN); | |
1156 | ||
28c97730 | 1157 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); |
74dff282 JB |
1158 | } |
1159 | ||
1160 | void g4x_disable_fbc(struct drm_device *dev) | |
1161 | { | |
1162 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1163 | u32 dpfc_ctl; | |
1164 | ||
1165 | /* Disable compression */ | |
1166 | dpfc_ctl = I915_READ(DPFC_CONTROL); | |
1167 | dpfc_ctl &= ~DPFC_CTL_EN; | |
1168 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); | |
74dff282 | 1169 | |
28c97730 | 1170 | DRM_DEBUG_KMS("disabled FBC\n"); |
74dff282 JB |
1171 | } |
1172 | ||
ee5382ae | 1173 | static bool g4x_fbc_enabled(struct drm_device *dev) |
74dff282 | 1174 | { |
74dff282 JB |
1175 | struct drm_i915_private *dev_priv = dev->dev_private; |
1176 | ||
1177 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; | |
1178 | } | |
1179 | ||
b52eb4dc ZY |
1180 | static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
1181 | { | |
1182 | struct drm_device *dev = crtc->dev; | |
1183 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1184 | struct drm_framebuffer *fb = crtc->fb; | |
1185 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
1186 | struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj); | |
1187 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1188 | int plane = (intel_crtc->plane == 0) ? DPFC_CTL_PLANEA : | |
1189 | DPFC_CTL_PLANEB; | |
1190 | unsigned long stall_watermark = 200; | |
1191 | u32 dpfc_ctl; | |
1192 | ||
1193 | dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1; | |
1194 | dev_priv->cfb_fence = obj_priv->fence_reg; | |
1195 | dev_priv->cfb_plane = intel_crtc->plane; | |
1196 | ||
1197 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); | |
1198 | dpfc_ctl &= DPFC_RESERVED; | |
1199 | dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X); | |
1200 | if (obj_priv->tiling_mode != I915_TILING_NONE) { | |
1201 | dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence); | |
1202 | I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY); | |
1203 | } else { | |
1204 | I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY); | |
1205 | } | |
1206 | ||
1207 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); | |
1208 | I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | | |
1209 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | | |
1210 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); | |
1211 | I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y); | |
1212 | I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID); | |
1213 | /* enable it... */ | |
1214 | I915_WRITE(ILK_DPFC_CONTROL, I915_READ(ILK_DPFC_CONTROL) | | |
1215 | DPFC_CTL_EN); | |
1216 | ||
1217 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); | |
1218 | } | |
1219 | ||
1220 | void ironlake_disable_fbc(struct drm_device *dev) | |
1221 | { | |
1222 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1223 | u32 dpfc_ctl; | |
1224 | ||
1225 | /* Disable compression */ | |
1226 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); | |
1227 | dpfc_ctl &= ~DPFC_CTL_EN; | |
1228 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); | |
b52eb4dc ZY |
1229 | |
1230 | DRM_DEBUG_KMS("disabled FBC\n"); | |
1231 | } | |
1232 | ||
1233 | static bool ironlake_fbc_enabled(struct drm_device *dev) | |
1234 | { | |
1235 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1236 | ||
1237 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; | |
1238 | } | |
1239 | ||
ee5382ae AJ |
1240 | bool intel_fbc_enabled(struct drm_device *dev) |
1241 | { | |
1242 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1243 | ||
1244 | if (!dev_priv->display.fbc_enabled) | |
1245 | return false; | |
1246 | ||
1247 | return dev_priv->display.fbc_enabled(dev); | |
1248 | } | |
1249 | ||
1250 | void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval) | |
1251 | { | |
1252 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
1253 | ||
1254 | if (!dev_priv->display.enable_fbc) | |
1255 | return; | |
1256 | ||
1257 | dev_priv->display.enable_fbc(crtc, interval); | |
1258 | } | |
1259 | ||
1260 | void intel_disable_fbc(struct drm_device *dev) | |
1261 | { | |
1262 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1263 | ||
1264 | if (!dev_priv->display.disable_fbc) | |
1265 | return; | |
1266 | ||
1267 | dev_priv->display.disable_fbc(dev); | |
1268 | } | |
1269 | ||
80824003 JB |
1270 | /** |
1271 | * intel_update_fbc - enable/disable FBC as needed | |
1272 | * @crtc: CRTC to point the compressor at | |
1273 | * @mode: mode in use | |
1274 | * | |
1275 | * Set up the framebuffer compression hardware at mode set time. We | |
1276 | * enable it if possible: | |
1277 | * - plane A only (on pre-965) | |
1278 | * - no pixel mulitply/line duplication | |
1279 | * - no alpha buffer discard | |
1280 | * - no dual wide | |
1281 | * - framebuffer <= 2048 in width, 1536 in height | |
1282 | * | |
1283 | * We can't assume that any compression will take place (worst case), | |
1284 | * so the compressed buffer has to be the same size as the uncompressed | |
1285 | * one. It also must reside (along with the line length buffer) in | |
1286 | * stolen memory. | |
1287 | * | |
1288 | * We need to enable/disable FBC on a global basis. | |
1289 | */ | |
1290 | static void intel_update_fbc(struct drm_crtc *crtc, | |
1291 | struct drm_display_mode *mode) | |
1292 | { | |
1293 | struct drm_device *dev = crtc->dev; | |
1294 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1295 | struct drm_framebuffer *fb = crtc->fb; | |
1296 | struct intel_framebuffer *intel_fb; | |
1297 | struct drm_i915_gem_object *obj_priv; | |
9c928d16 | 1298 | struct drm_crtc *tmp_crtc; |
80824003 JB |
1299 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1300 | int plane = intel_crtc->plane; | |
9c928d16 JB |
1301 | int crtcs_enabled = 0; |
1302 | ||
1303 | DRM_DEBUG_KMS("\n"); | |
80824003 JB |
1304 | |
1305 | if (!i915_powersave) | |
1306 | return; | |
1307 | ||
ee5382ae | 1308 | if (!I915_HAS_FBC(dev)) |
e70236a8 JB |
1309 | return; |
1310 | ||
80824003 JB |
1311 | if (!crtc->fb) |
1312 | return; | |
1313 | ||
1314 | intel_fb = to_intel_framebuffer(fb); | |
23010e43 | 1315 | obj_priv = to_intel_bo(intel_fb->obj); |
80824003 JB |
1316 | |
1317 | /* | |
1318 | * If FBC is already on, we just have to verify that we can | |
1319 | * keep it that way... | |
1320 | * Need to disable if: | |
9c928d16 | 1321 | * - more than one pipe is active |
80824003 JB |
1322 | * - changing FBC params (stride, fence, mode) |
1323 | * - new fb is too large to fit in compressed buffer | |
1324 | * - going to an unsupported config (interlace, pixel multiply, etc.) | |
1325 | */ | |
9c928d16 JB |
1326 | list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) { |
1327 | if (tmp_crtc->enabled) | |
1328 | crtcs_enabled++; | |
1329 | } | |
1330 | DRM_DEBUG_KMS("%d pipes active\n", crtcs_enabled); | |
1331 | if (crtcs_enabled > 1) { | |
1332 | DRM_DEBUG_KMS("more than one pipe active, disabling compression\n"); | |
1333 | dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES; | |
1334 | goto out_disable; | |
1335 | } | |
80824003 | 1336 | if (intel_fb->obj->size > dev_priv->cfb_size) { |
28c97730 ZY |
1337 | DRM_DEBUG_KMS("framebuffer too large, disabling " |
1338 | "compression\n"); | |
b5e50c3f | 1339 | dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; |
80824003 JB |
1340 | goto out_disable; |
1341 | } | |
1342 | if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || | |
1343 | (mode->flags & DRM_MODE_FLAG_DBLSCAN)) { | |
28c97730 ZY |
1344 | DRM_DEBUG_KMS("mode incompatible with compression, " |
1345 | "disabling\n"); | |
b5e50c3f | 1346 | dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE; |
80824003 JB |
1347 | goto out_disable; |
1348 | } | |
1349 | if ((mode->hdisplay > 2048) || | |
1350 | (mode->vdisplay > 1536)) { | |
28c97730 | 1351 | DRM_DEBUG_KMS("mode too large for compression, disabling\n"); |
b5e50c3f | 1352 | dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE; |
80824003 JB |
1353 | goto out_disable; |
1354 | } | |
74dff282 | 1355 | if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) { |
28c97730 | 1356 | DRM_DEBUG_KMS("plane not 0, disabling compression\n"); |
b5e50c3f | 1357 | dev_priv->no_fbc_reason = FBC_BAD_PLANE; |
80824003 JB |
1358 | goto out_disable; |
1359 | } | |
1360 | if (obj_priv->tiling_mode != I915_TILING_X) { | |
28c97730 | 1361 | DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n"); |
b5e50c3f | 1362 | dev_priv->no_fbc_reason = FBC_NOT_TILED; |
80824003 JB |
1363 | goto out_disable; |
1364 | } | |
1365 | ||
c924b934 JW |
1366 | /* If the kernel debugger is active, always disable compression */ |
1367 | if (in_dbg_master()) | |
1368 | goto out_disable; | |
1369 | ||
ee5382ae | 1370 | if (intel_fbc_enabled(dev)) { |
80824003 | 1371 | /* We can re-enable it in this case, but need to update pitch */ |
ee5382ae AJ |
1372 | if ((fb->pitch > dev_priv->cfb_pitch) || |
1373 | (obj_priv->fence_reg != dev_priv->cfb_fence) || | |
1374 | (plane != dev_priv->cfb_plane)) | |
1375 | intel_disable_fbc(dev); | |
80824003 JB |
1376 | } |
1377 | ||
ee5382ae AJ |
1378 | /* Now try to turn it back on if possible */ |
1379 | if (!intel_fbc_enabled(dev)) | |
1380 | intel_enable_fbc(crtc, 500); | |
80824003 JB |
1381 | |
1382 | return; | |
1383 | ||
1384 | out_disable: | |
80824003 | 1385 | /* Multiple disables should be harmless */ |
a939406f CW |
1386 | if (intel_fbc_enabled(dev)) { |
1387 | DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); | |
ee5382ae | 1388 | intel_disable_fbc(dev); |
a939406f | 1389 | } |
80824003 JB |
1390 | } |
1391 | ||
127bd2ac | 1392 | int |
6b95a207 KH |
1393 | intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj) |
1394 | { | |
23010e43 | 1395 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
6b95a207 KH |
1396 | u32 alignment; |
1397 | int ret; | |
1398 | ||
1399 | switch (obj_priv->tiling_mode) { | |
1400 | case I915_TILING_NONE: | |
534843da CW |
1401 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
1402 | alignment = 128 * 1024; | |
1403 | else if (IS_I965G(dev)) | |
1404 | alignment = 4 * 1024; | |
1405 | else | |
1406 | alignment = 64 * 1024; | |
6b95a207 KH |
1407 | break; |
1408 | case I915_TILING_X: | |
1409 | /* pin() will align the object as required by fence */ | |
1410 | alignment = 0; | |
1411 | break; | |
1412 | case I915_TILING_Y: | |
1413 | /* FIXME: Is this true? */ | |
1414 | DRM_ERROR("Y tiled not allowed for scan out buffers\n"); | |
1415 | return -EINVAL; | |
1416 | default: | |
1417 | BUG(); | |
1418 | } | |
1419 | ||
6b95a207 KH |
1420 | ret = i915_gem_object_pin(obj, alignment); |
1421 | if (ret != 0) | |
1422 | return ret; | |
1423 | ||
1424 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
1425 | * fence, whereas 965+ only requires a fence if using | |
1426 | * framebuffer compression. For simplicity, we always install | |
1427 | * a fence as the cost is not that onerous. | |
1428 | */ | |
1429 | if (obj_priv->fence_reg == I915_FENCE_REG_NONE && | |
1430 | obj_priv->tiling_mode != I915_TILING_NONE) { | |
1431 | ret = i915_gem_object_get_fence_reg(obj); | |
1432 | if (ret != 0) { | |
1433 | i915_gem_object_unpin(obj); | |
1434 | return ret; | |
1435 | } | |
1436 | } | |
1437 | ||
1438 | return 0; | |
1439 | } | |
1440 | ||
81255565 JB |
1441 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
1442 | static int | |
1443 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
1444 | int x, int y) | |
1445 | { | |
1446 | struct drm_device *dev = crtc->dev; | |
1447 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1448 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1449 | struct intel_framebuffer *intel_fb; | |
1450 | struct drm_i915_gem_object *obj_priv; | |
1451 | struct drm_gem_object *obj; | |
1452 | int plane = intel_crtc->plane; | |
1453 | unsigned long Start, Offset; | |
1454 | int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR); | |
1455 | int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF); | |
1456 | int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE; | |
1457 | int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF); | |
1458 | int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR; | |
1459 | u32 dspcntr; | |
1460 | ||
1461 | switch (plane) { | |
1462 | case 0: | |
1463 | case 1: | |
1464 | break; | |
1465 | default: | |
1466 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); | |
1467 | return -EINVAL; | |
1468 | } | |
1469 | ||
1470 | intel_fb = to_intel_framebuffer(fb); | |
1471 | obj = intel_fb->obj; | |
1472 | obj_priv = to_intel_bo(obj); | |
1473 | ||
1474 | dspcntr = I915_READ(dspcntr_reg); | |
1475 | /* Mask out pixel format bits in case we change it */ | |
1476 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
1477 | switch (fb->bits_per_pixel) { | |
1478 | case 8: | |
1479 | dspcntr |= DISPPLANE_8BPP; | |
1480 | break; | |
1481 | case 16: | |
1482 | if (fb->depth == 15) | |
1483 | dspcntr |= DISPPLANE_15_16BPP; | |
1484 | else | |
1485 | dspcntr |= DISPPLANE_16BPP; | |
1486 | break; | |
1487 | case 24: | |
1488 | case 32: | |
1489 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; | |
1490 | break; | |
1491 | default: | |
1492 | DRM_ERROR("Unknown color depth\n"); | |
1493 | return -EINVAL; | |
1494 | } | |
1495 | if (IS_I965G(dev)) { | |
1496 | if (obj_priv->tiling_mode != I915_TILING_NONE) | |
1497 | dspcntr |= DISPPLANE_TILED; | |
1498 | else | |
1499 | dspcntr &= ~DISPPLANE_TILED; | |
1500 | } | |
1501 | ||
4e6cfefc | 1502 | if (HAS_PCH_SPLIT(dev)) |
81255565 JB |
1503 | /* must disable */ |
1504 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
1505 | ||
1506 | I915_WRITE(dspcntr_reg, dspcntr); | |
1507 | ||
1508 | Start = obj_priv->gtt_offset; | |
1509 | Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8); | |
1510 | ||
4e6cfefc CW |
1511 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
1512 | Start, Offset, x, y, fb->pitch); | |
81255565 JB |
1513 | I915_WRITE(dspstride, fb->pitch); |
1514 | if (IS_I965G(dev)) { | |
81255565 | 1515 | I915_WRITE(dspsurf, Start); |
81255565 | 1516 | I915_WRITE(dsptileoff, (y << 16) | x); |
4e6cfefc | 1517 | I915_WRITE(dspbase, Offset); |
81255565 JB |
1518 | } else { |
1519 | I915_WRITE(dspbase, Start + Offset); | |
81255565 | 1520 | } |
4e6cfefc | 1521 | POSTING_READ(dspbase); |
81255565 | 1522 | |
4e6cfefc | 1523 | if (IS_I965G(dev) || plane == 0) |
81255565 JB |
1524 | intel_update_fbc(crtc, &crtc->mode); |
1525 | ||
9d0498a2 | 1526 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
3dec0095 | 1527 | intel_increase_pllclock(crtc); |
81255565 JB |
1528 | |
1529 | return 0; | |
1530 | } | |
1531 | ||
5c3b82e2 | 1532 | static int |
3c4fdcfb KH |
1533 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
1534 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
1535 | { |
1536 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
1537 | struct drm_i915_master_private *master_priv; |
1538 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1539 | struct intel_framebuffer *intel_fb; | |
1540 | struct drm_i915_gem_object *obj_priv; | |
1541 | struct drm_gem_object *obj; | |
1542 | int pipe = intel_crtc->pipe; | |
80824003 | 1543 | int plane = intel_crtc->plane; |
5c3b82e2 | 1544 | int ret; |
79e53945 JB |
1545 | |
1546 | /* no fb bound */ | |
1547 | if (!crtc->fb) { | |
28c97730 | 1548 | DRM_DEBUG_KMS("No FB bound\n"); |
5c3b82e2 CW |
1549 | return 0; |
1550 | } | |
1551 | ||
80824003 | 1552 | switch (plane) { |
5c3b82e2 CW |
1553 | case 0: |
1554 | case 1: | |
1555 | break; | |
1556 | default: | |
80824003 | 1557 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); |
5c3b82e2 | 1558 | return -EINVAL; |
79e53945 JB |
1559 | } |
1560 | ||
1561 | intel_fb = to_intel_framebuffer(crtc->fb); | |
79e53945 | 1562 | obj = intel_fb->obj; |
23010e43 | 1563 | obj_priv = to_intel_bo(obj); |
79e53945 | 1564 | |
5c3b82e2 | 1565 | mutex_lock(&dev->struct_mutex); |
6b95a207 | 1566 | ret = intel_pin_and_fence_fb_obj(dev, obj); |
5c3b82e2 CW |
1567 | if (ret != 0) { |
1568 | mutex_unlock(&dev->struct_mutex); | |
1569 | return ret; | |
1570 | } | |
79e53945 | 1571 | |
b9241ea3 | 1572 | ret = i915_gem_object_set_to_display_plane(obj); |
5c3b82e2 | 1573 | if (ret != 0) { |
8c4b8c3f | 1574 | i915_gem_object_unpin(obj); |
5c3b82e2 CW |
1575 | mutex_unlock(&dev->struct_mutex); |
1576 | return ret; | |
1577 | } | |
79e53945 | 1578 | |
4e6cfefc CW |
1579 | ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y); |
1580 | if (ret) { | |
8c4b8c3f | 1581 | i915_gem_object_unpin(obj); |
5c3b82e2 | 1582 | mutex_unlock(&dev->struct_mutex); |
4e6cfefc | 1583 | return ret; |
79e53945 | 1584 | } |
3c4fdcfb KH |
1585 | |
1586 | if (old_fb) { | |
1587 | intel_fb = to_intel_framebuffer(old_fb); | |
23010e43 | 1588 | obj_priv = to_intel_bo(intel_fb->obj); |
3c4fdcfb KH |
1589 | i915_gem_object_unpin(intel_fb->obj); |
1590 | } | |
652c393a | 1591 | |
5c3b82e2 | 1592 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
1593 | |
1594 | if (!dev->primary->master) | |
5c3b82e2 | 1595 | return 0; |
79e53945 JB |
1596 | |
1597 | master_priv = dev->primary->master->driver_priv; | |
1598 | if (!master_priv->sarea_priv) | |
5c3b82e2 | 1599 | return 0; |
79e53945 | 1600 | |
5c3b82e2 | 1601 | if (pipe) { |
79e53945 JB |
1602 | master_priv->sarea_priv->pipeB_x = x; |
1603 | master_priv->sarea_priv->pipeB_y = y; | |
5c3b82e2 CW |
1604 | } else { |
1605 | master_priv->sarea_priv->pipeA_x = x; | |
1606 | master_priv->sarea_priv->pipeA_y = y; | |
79e53945 | 1607 | } |
5c3b82e2 CW |
1608 | |
1609 | return 0; | |
79e53945 JB |
1610 | } |
1611 | ||
f2b115e6 | 1612 | static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock) |
32f9d658 ZW |
1613 | { |
1614 | struct drm_device *dev = crtc->dev; | |
1615 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1616 | u32 dpa_ctl; | |
1617 | ||
28c97730 | 1618 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock); |
32f9d658 ZW |
1619 | dpa_ctl = I915_READ(DP_A); |
1620 | dpa_ctl &= ~DP_PLL_FREQ_MASK; | |
1621 | ||
1622 | if (clock < 200000) { | |
1623 | u32 temp; | |
1624 | dpa_ctl |= DP_PLL_FREQ_160MHZ; | |
1625 | /* workaround for 160Mhz: | |
1626 | 1) program 0x4600c bits 15:0 = 0x8124 | |
1627 | 2) program 0x46010 bit 0 = 1 | |
1628 | 3) program 0x46034 bit 24 = 1 | |
1629 | 4) program 0x64000 bit 14 = 1 | |
1630 | */ | |
1631 | temp = I915_READ(0x4600c); | |
1632 | temp &= 0xffff0000; | |
1633 | I915_WRITE(0x4600c, temp | 0x8124); | |
1634 | ||
1635 | temp = I915_READ(0x46010); | |
1636 | I915_WRITE(0x46010, temp | 1); | |
1637 | ||
1638 | temp = I915_READ(0x46034); | |
1639 | I915_WRITE(0x46034, temp | (1 << 24)); | |
1640 | } else { | |
1641 | dpa_ctl |= DP_PLL_FREQ_270MHZ; | |
1642 | } | |
1643 | I915_WRITE(DP_A, dpa_ctl); | |
1644 | ||
1645 | udelay(500); | |
1646 | } | |
1647 | ||
8db9d77b ZW |
1648 | /* The FDI link training functions for ILK/Ibexpeak. */ |
1649 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
1650 | { | |
1651 | struct drm_device *dev = crtc->dev; | |
1652 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1653 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1654 | int pipe = intel_crtc->pipe; | |
1655 | int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL; | |
1656 | int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL; | |
1657 | int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR; | |
1658 | int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR; | |
1659 | u32 temp, tries = 0; | |
1660 | ||
e1a44743 AJ |
1661 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
1662 | for train result */ | |
1663 | temp = I915_READ(fdi_rx_imr_reg); | |
1664 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
1665 | temp &= ~FDI_RX_BIT_LOCK; | |
1666 | I915_WRITE(fdi_rx_imr_reg, temp); | |
1667 | I915_READ(fdi_rx_imr_reg); | |
1668 | udelay(150); | |
1669 | ||
8db9d77b ZW |
1670 | /* enable CPU FDI TX and PCH FDI RX */ |
1671 | temp = I915_READ(fdi_tx_reg); | |
1672 | temp |= FDI_TX_ENABLE; | |
77ffb597 AJ |
1673 | temp &= ~(7 << 19); |
1674 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
8db9d77b ZW |
1675 | temp &= ~FDI_LINK_TRAIN_NONE; |
1676 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
1677 | I915_WRITE(fdi_tx_reg, temp); | |
1678 | I915_READ(fdi_tx_reg); | |
1679 | ||
1680 | temp = I915_READ(fdi_rx_reg); | |
1681 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1682 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
1683 | I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE); | |
1684 | I915_READ(fdi_rx_reg); | |
1685 | udelay(150); | |
1686 | ||
e1a44743 | 1687 | for (tries = 0; tries < 5; tries++) { |
8db9d77b ZW |
1688 | temp = I915_READ(fdi_rx_iir_reg); |
1689 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
1690 | ||
1691 | if ((temp & FDI_RX_BIT_LOCK)) { | |
1692 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
1693 | I915_WRITE(fdi_rx_iir_reg, | |
1694 | temp | FDI_RX_BIT_LOCK); | |
1695 | break; | |
1696 | } | |
8db9d77b | 1697 | } |
e1a44743 AJ |
1698 | if (tries == 5) |
1699 | DRM_DEBUG_KMS("FDI train 1 fail!\n"); | |
8db9d77b ZW |
1700 | |
1701 | /* Train 2 */ | |
1702 | temp = I915_READ(fdi_tx_reg); | |
1703 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1704 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
1705 | I915_WRITE(fdi_tx_reg, temp); | |
1706 | ||
1707 | temp = I915_READ(fdi_rx_reg); | |
1708 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1709 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
1710 | I915_WRITE(fdi_rx_reg, temp); | |
1711 | udelay(150); | |
1712 | ||
1713 | tries = 0; | |
1714 | ||
e1a44743 | 1715 | for (tries = 0; tries < 5; tries++) { |
8db9d77b ZW |
1716 | temp = I915_READ(fdi_rx_iir_reg); |
1717 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
1718 | ||
1719 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
1720 | I915_WRITE(fdi_rx_iir_reg, | |
1721 | temp | FDI_RX_SYMBOL_LOCK); | |
1722 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
1723 | break; | |
1724 | } | |
8db9d77b | 1725 | } |
e1a44743 AJ |
1726 | if (tries == 5) |
1727 | DRM_DEBUG_KMS("FDI train 2 fail!\n"); | |
8db9d77b ZW |
1728 | |
1729 | DRM_DEBUG_KMS("FDI train done\n"); | |
1730 | } | |
1731 | ||
1732 | static int snb_b_fdi_train_param [] = { | |
1733 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, | |
1734 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
1735 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
1736 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
1737 | }; | |
1738 | ||
1739 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
1740 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
1741 | { | |
1742 | struct drm_device *dev = crtc->dev; | |
1743 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1744 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1745 | int pipe = intel_crtc->pipe; | |
1746 | int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL; | |
1747 | int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL; | |
1748 | int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR; | |
1749 | int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR; | |
1750 | u32 temp, i; | |
1751 | ||
e1a44743 AJ |
1752 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
1753 | for train result */ | |
1754 | temp = I915_READ(fdi_rx_imr_reg); | |
1755 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
1756 | temp &= ~FDI_RX_BIT_LOCK; | |
1757 | I915_WRITE(fdi_rx_imr_reg, temp); | |
1758 | I915_READ(fdi_rx_imr_reg); | |
1759 | udelay(150); | |
1760 | ||
8db9d77b ZW |
1761 | /* enable CPU FDI TX and PCH FDI RX */ |
1762 | temp = I915_READ(fdi_tx_reg); | |
1763 | temp |= FDI_TX_ENABLE; | |
77ffb597 AJ |
1764 | temp &= ~(7 << 19); |
1765 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
8db9d77b ZW |
1766 | temp &= ~FDI_LINK_TRAIN_NONE; |
1767 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
1768 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
1769 | /* SNB-B */ | |
1770 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
1771 | I915_WRITE(fdi_tx_reg, temp); | |
1772 | I915_READ(fdi_tx_reg); | |
1773 | ||
1774 | temp = I915_READ(fdi_rx_reg); | |
1775 | if (HAS_PCH_CPT(dev)) { | |
1776 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
1777 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
1778 | } else { | |
1779 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1780 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
1781 | } | |
1782 | I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE); | |
1783 | I915_READ(fdi_rx_reg); | |
1784 | udelay(150); | |
1785 | ||
8db9d77b ZW |
1786 | for (i = 0; i < 4; i++ ) { |
1787 | temp = I915_READ(fdi_tx_reg); | |
1788 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
1789 | temp |= snb_b_fdi_train_param[i]; | |
1790 | I915_WRITE(fdi_tx_reg, temp); | |
1791 | udelay(500); | |
1792 | ||
1793 | temp = I915_READ(fdi_rx_iir_reg); | |
1794 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
1795 | ||
1796 | if (temp & FDI_RX_BIT_LOCK) { | |
1797 | I915_WRITE(fdi_rx_iir_reg, | |
1798 | temp | FDI_RX_BIT_LOCK); | |
1799 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
1800 | break; | |
1801 | } | |
1802 | } | |
1803 | if (i == 4) | |
1804 | DRM_DEBUG_KMS("FDI train 1 fail!\n"); | |
1805 | ||
1806 | /* Train 2 */ | |
1807 | temp = I915_READ(fdi_tx_reg); | |
1808 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1809 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
1810 | if (IS_GEN6(dev)) { | |
1811 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
1812 | /* SNB-B */ | |
1813 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
1814 | } | |
1815 | I915_WRITE(fdi_tx_reg, temp); | |
1816 | ||
1817 | temp = I915_READ(fdi_rx_reg); | |
1818 | if (HAS_PCH_CPT(dev)) { | |
1819 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
1820 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
1821 | } else { | |
1822 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1823 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
1824 | } | |
1825 | I915_WRITE(fdi_rx_reg, temp); | |
1826 | udelay(150); | |
1827 | ||
1828 | for (i = 0; i < 4; i++ ) { | |
1829 | temp = I915_READ(fdi_tx_reg); | |
1830 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
1831 | temp |= snb_b_fdi_train_param[i]; | |
1832 | I915_WRITE(fdi_tx_reg, temp); | |
1833 | udelay(500); | |
1834 | ||
1835 | temp = I915_READ(fdi_rx_iir_reg); | |
1836 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
1837 | ||
1838 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
1839 | I915_WRITE(fdi_rx_iir_reg, | |
1840 | temp | FDI_RX_SYMBOL_LOCK); | |
1841 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
1842 | break; | |
1843 | } | |
1844 | } | |
1845 | if (i == 4) | |
1846 | DRM_DEBUG_KMS("FDI train 2 fail!\n"); | |
1847 | ||
1848 | DRM_DEBUG_KMS("FDI train done.\n"); | |
1849 | } | |
1850 | ||
6be4a607 | 1851 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
2c07245f ZW |
1852 | { |
1853 | struct drm_device *dev = crtc->dev; | |
1854 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1855 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1856 | int pipe = intel_crtc->pipe; | |
7662c8bd | 1857 | int plane = intel_crtc->plane; |
2c07245f ZW |
1858 | int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B; |
1859 | int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; | |
1860 | int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR; | |
1861 | int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR; | |
1862 | int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL; | |
1863 | int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL; | |
2c07245f | 1864 | int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF; |
2c07245f ZW |
1865 | int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B; |
1866 | int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B; | |
1867 | int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B; | |
1868 | int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B; | |
1869 | int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B; | |
1870 | int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B; | |
1871 | int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B; | |
1872 | int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B; | |
1873 | int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B; | |
1874 | int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B; | |
1875 | int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B; | |
1876 | int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B; | |
8db9d77b | 1877 | int trans_dpll_sel = (pipe == 0) ? 0 : 1; |
2c07245f | 1878 | u32 temp; |
8faf3b31 ZY |
1879 | u32 pipe_bpc; |
1880 | ||
1881 | temp = I915_READ(pipeconf_reg); | |
1882 | pipe_bpc = temp & PIPE_BPC_MASK; | |
79e53945 | 1883 | |
6be4a607 JB |
1884 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
1885 | temp = I915_READ(PCH_LVDS); | |
1886 | if ((temp & LVDS_PORT_EN) == 0) { | |
1887 | I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN); | |
1888 | POSTING_READ(PCH_LVDS); | |
1b3c7a47 | 1889 | } |
6be4a607 | 1890 | } |
1b3c7a47 | 1891 | |
6be4a607 JB |
1892 | if (!HAS_eDP) { |
1893 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ | |
1894 | temp = I915_READ(fdi_rx_reg); | |
1895 | /* | |
1896 | * make the BPC in FDI Rx be consistent with that in | |
1897 | * pipeconf reg. | |
1898 | */ | |
1899 | temp &= ~(0x7 << 16); | |
1900 | temp |= (pipe_bpc << 11); | |
1901 | temp &= ~(7 << 19); | |
1902 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
1903 | I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE); | |
1904 | I915_READ(fdi_rx_reg); | |
1905 | udelay(200); | |
2c07245f | 1906 | |
6be4a607 JB |
1907 | /* Switch from Rawclk to PCDclk */ |
1908 | temp = I915_READ(fdi_rx_reg); | |
1909 | I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK); | |
1910 | I915_READ(fdi_rx_reg); | |
1911 | udelay(200); | |
8dd81a38 | 1912 | |
6be4a607 JB |
1913 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
1914 | temp = I915_READ(fdi_tx_reg); | |
1915 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
1916 | I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE); | |
1917 | I915_READ(fdi_tx_reg); | |
2c07245f ZW |
1918 | udelay(100); |
1919 | } | |
6be4a607 | 1920 | } |
2c07245f | 1921 | |
6be4a607 JB |
1922 | /* Enable panel fitting for LVDS */ |
1923 | if (dev_priv->pch_pf_size && | |
1924 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) | |
1925 | || HAS_eDP || intel_pch_has_edp(crtc))) { | |
1926 | /* Force use of hard-coded filter coefficients | |
1927 | * as some pre-programmed values are broken, | |
1928 | * e.g. x201. | |
1929 | */ | |
1930 | I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, | |
1931 | PF_ENABLE | PF_FILTER_MED_3x3); | |
1932 | I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS, | |
1933 | dev_priv->pch_pf_pos); | |
1934 | I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, | |
1935 | dev_priv->pch_pf_size); | |
1936 | } | |
2c07245f | 1937 | |
6be4a607 JB |
1938 | /* Enable CPU pipe */ |
1939 | temp = I915_READ(pipeconf_reg); | |
1940 | if ((temp & PIPEACONF_ENABLE) == 0) { | |
1941 | I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE); | |
1942 | I915_READ(pipeconf_reg); | |
1943 | udelay(100); | |
1944 | } | |
2c07245f | 1945 | |
6be4a607 JB |
1946 | /* configure and enable CPU plane */ |
1947 | temp = I915_READ(dspcntr_reg); | |
1948 | if ((temp & DISPLAY_PLANE_ENABLE) == 0) { | |
1949 | I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE); | |
1950 | /* Flush the plane changes */ | |
1951 | I915_WRITE(dspbase_reg, I915_READ(dspbase_reg)); | |
1952 | } | |
2c07245f | 1953 | |
6be4a607 JB |
1954 | if (!HAS_eDP) { |
1955 | /* For PCH output, training FDI link */ | |
1956 | if (IS_GEN6(dev)) | |
1957 | gen6_fdi_link_train(crtc); | |
1958 | else | |
1959 | ironlake_fdi_link_train(crtc); | |
2c07245f | 1960 | |
6be4a607 JB |
1961 | /* enable PCH DPLL */ |
1962 | temp = I915_READ(pch_dpll_reg); | |
1963 | if ((temp & DPLL_VCO_ENABLE) == 0) { | |
1964 | I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE); | |
1965 | I915_READ(pch_dpll_reg); | |
1966 | } | |
1967 | udelay(200); | |
2c07245f | 1968 | |
6be4a607 JB |
1969 | if (HAS_PCH_CPT(dev)) { |
1970 | /* Be sure PCH DPLL SEL is set */ | |
1971 | temp = I915_READ(PCH_DPLL_SEL); | |
1972 | if (trans_dpll_sel == 0 && | |
1973 | (temp & TRANSA_DPLL_ENABLE) == 0) | |
1974 | temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL); | |
1975 | else if (trans_dpll_sel == 1 && | |
1976 | (temp & TRANSB_DPLL_ENABLE) == 0) | |
1977 | temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); | |
1978 | I915_WRITE(PCH_DPLL_SEL, temp); | |
1979 | I915_READ(PCH_DPLL_SEL); | |
1980 | } | |
1981 | /* set transcoder timing */ | |
1982 | I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg)); | |
1983 | I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg)); | |
1984 | I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg)); | |
8db9d77b | 1985 | |
6be4a607 JB |
1986 | I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg)); |
1987 | I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg)); | |
1988 | I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg)); | |
8db9d77b | 1989 | |
6be4a607 JB |
1990 | /* enable normal train */ |
1991 | temp = I915_READ(fdi_tx_reg); | |
1992 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1993 | I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE | | |
1994 | FDI_TX_ENHANCE_FRAME_ENABLE); | |
1995 | I915_READ(fdi_tx_reg); | |
8db9d77b | 1996 | |
6be4a607 JB |
1997 | temp = I915_READ(fdi_rx_reg); |
1998 | if (HAS_PCH_CPT(dev)) { | |
1999 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2000 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
2001 | } else { | |
2002 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2003 | temp |= FDI_LINK_TRAIN_NONE; | |
2004 | } | |
2005 | I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
2006 | I915_READ(fdi_rx_reg); | |
2007 | ||
2008 | /* wait one idle pattern time */ | |
2009 | udelay(100); | |
e3421a18 | 2010 | |
6be4a607 JB |
2011 | /* For PCH DP, enable TRANS_DP_CTL */ |
2012 | if (HAS_PCH_CPT(dev) && | |
2013 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { | |
2014 | int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B; | |
2015 | int reg; | |
2016 | ||
2017 | reg = I915_READ(trans_dp_ctl); | |
2018 | reg &= ~(TRANS_DP_PORT_SEL_MASK | | |
2019 | TRANS_DP_SYNC_MASK); | |
2020 | reg |= (TRANS_DP_OUTPUT_ENABLE | | |
2021 | TRANS_DP_ENH_FRAMING); | |
2022 | ||
2023 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
2024 | reg |= TRANS_DP_HSYNC_ACTIVE_HIGH; | |
2025 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) | |
2026 | reg |= TRANS_DP_VSYNC_ACTIVE_HIGH; | |
2027 | ||
2028 | switch (intel_trans_dp_port_sel(crtc)) { | |
2029 | case PCH_DP_B: | |
2030 | reg |= TRANS_DP_PORT_SEL_B; | |
2031 | break; | |
2032 | case PCH_DP_C: | |
2033 | reg |= TRANS_DP_PORT_SEL_C; | |
2034 | break; | |
2035 | case PCH_DP_D: | |
2036 | reg |= TRANS_DP_PORT_SEL_D; | |
2037 | break; | |
2038 | default: | |
2039 | DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n"); | |
2040 | reg |= TRANS_DP_PORT_SEL_B; | |
2041 | break; | |
e3421a18 ZW |
2042 | } |
2043 | ||
6be4a607 JB |
2044 | I915_WRITE(trans_dp_ctl, reg); |
2045 | POSTING_READ(trans_dp_ctl); | |
32f9d658 | 2046 | } |
2c07245f | 2047 | |
6be4a607 JB |
2048 | /* enable PCH transcoder */ |
2049 | temp = I915_READ(transconf_reg); | |
2050 | /* | |
2051 | * make the BPC in transcoder be consistent with | |
2052 | * that in pipeconf reg. | |
2053 | */ | |
2054 | temp &= ~PIPE_BPC_MASK; | |
2055 | temp |= pipe_bpc; | |
2056 | I915_WRITE(transconf_reg, temp | TRANS_ENABLE); | |
2057 | I915_READ(transconf_reg); | |
2c07245f | 2058 | |
6be4a607 JB |
2059 | if (wait_for(I915_READ(transconf_reg) & TRANS_STATE_ENABLE, 100)) |
2060 | DRM_ERROR("failed to enable transcoder\n"); | |
2061 | } | |
b52eb4dc | 2062 | |
6be4a607 | 2063 | intel_crtc_load_lut(crtc); |
2c07245f | 2064 | |
6be4a607 JB |
2065 | intel_update_fbc(crtc, &crtc->mode); |
2066 | } | |
2067 | ||
2068 | static void ironlake_crtc_disable(struct drm_crtc *crtc) | |
2069 | { | |
2070 | struct drm_device *dev = crtc->dev; | |
2071 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2072 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2073 | int pipe = intel_crtc->pipe; | |
2074 | int plane = intel_crtc->plane; | |
2075 | int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B; | |
2076 | int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; | |
2077 | int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR; | |
2078 | int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR; | |
2079 | int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL; | |
2080 | int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL; | |
2081 | int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF; | |
2082 | int trans_dpll_sel = (pipe == 0) ? 0 : 1; | |
2083 | u32 temp; | |
2084 | u32 pipe_bpc; | |
2c07245f | 2085 | |
6be4a607 JB |
2086 | temp = I915_READ(pipeconf_reg); |
2087 | pipe_bpc = temp & PIPE_BPC_MASK; | |
b52eb4dc | 2088 | |
6be4a607 JB |
2089 | drm_vblank_off(dev, pipe); |
2090 | /* Disable display plane */ | |
2091 | temp = I915_READ(dspcntr_reg); | |
2092 | if ((temp & DISPLAY_PLANE_ENABLE) != 0) { | |
2093 | I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE); | |
2094 | /* Flush the plane changes */ | |
2095 | I915_WRITE(dspbase_reg, I915_READ(dspbase_reg)); | |
2096 | I915_READ(dspbase_reg); | |
2097 | } | |
913d8d11 | 2098 | |
6be4a607 JB |
2099 | if (dev_priv->cfb_plane == plane && |
2100 | dev_priv->display.disable_fbc) | |
2101 | dev_priv->display.disable_fbc(dev); | |
2c07245f | 2102 | |
6be4a607 JB |
2103 | /* disable cpu pipe, disable after all planes disabled */ |
2104 | temp = I915_READ(pipeconf_reg); | |
2105 | if ((temp & PIPEACONF_ENABLE) != 0) { | |
2106 | I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE); | |
1b3c7a47 | 2107 | |
6be4a607 JB |
2108 | /* wait for cpu pipe off, pipe state */ |
2109 | if (wait_for((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) == 0, 50)) | |
2110 | DRM_ERROR("failed to turn off cpu pipe\n"); | |
2111 | } else | |
2112 | DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); | |
32f9d658 | 2113 | |
6be4a607 | 2114 | udelay(100); |
2c07245f | 2115 | |
6be4a607 JB |
2116 | /* Disable PF */ |
2117 | I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0); | |
2118 | I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0); | |
2c07245f | 2119 | |
6be4a607 JB |
2120 | /* disable CPU FDI tx and PCH FDI rx */ |
2121 | temp = I915_READ(fdi_tx_reg); | |
2122 | I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE); | |
2123 | I915_READ(fdi_tx_reg); | |
249c0e64 | 2124 | |
6be4a607 JB |
2125 | temp = I915_READ(fdi_rx_reg); |
2126 | /* BPC in FDI rx is consistent with that in pipeconf */ | |
2127 | temp &= ~(0x07 << 16); | |
2128 | temp |= (pipe_bpc << 11); | |
2129 | I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE); | |
2130 | I915_READ(fdi_rx_reg); | |
2131 | ||
2132 | udelay(100); | |
2133 | ||
2134 | /* still set train pattern 1 */ | |
2135 | temp = I915_READ(fdi_tx_reg); | |
2136 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2137 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2138 | I915_WRITE(fdi_tx_reg, temp); | |
2139 | POSTING_READ(fdi_tx_reg); | |
2140 | ||
2141 | temp = I915_READ(fdi_rx_reg); | |
2142 | if (HAS_PCH_CPT(dev)) { | |
2143 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2144 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2145 | } else { | |
2c07245f ZW |
2146 | temp &= ~FDI_LINK_TRAIN_NONE; |
2147 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
6be4a607 JB |
2148 | } |
2149 | I915_WRITE(fdi_rx_reg, temp); | |
2150 | POSTING_READ(fdi_rx_reg); | |
2c07245f | 2151 | |
6be4a607 | 2152 | udelay(100); |
2c07245f | 2153 | |
6be4a607 JB |
2154 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
2155 | temp = I915_READ(PCH_LVDS); | |
2156 | I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN); | |
2157 | I915_READ(PCH_LVDS); | |
249c0e64 | 2158 | udelay(100); |
6be4a607 | 2159 | } |
249c0e64 | 2160 | |
6be4a607 JB |
2161 | /* disable PCH transcoder */ |
2162 | temp = I915_READ(transconf_reg); | |
2163 | if ((temp & TRANS_ENABLE) != 0) { | |
2164 | I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE); | |
1b3c7a47 | 2165 | |
6be4a607 JB |
2166 | /* wait for PCH transcoder off, transcoder state */ |
2167 | if (wait_for((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
2168 | DRM_ERROR("failed to disable transcoder\n"); | |
2169 | } | |
913d8d11 | 2170 | |
6be4a607 JB |
2171 | temp = I915_READ(transconf_reg); |
2172 | /* BPC in transcoder is consistent with that in pipeconf */ | |
2173 | temp &= ~PIPE_BPC_MASK; | |
2174 | temp |= pipe_bpc; | |
2175 | I915_WRITE(transconf_reg, temp); | |
2176 | I915_READ(transconf_reg); | |
2177 | udelay(100); | |
8db9d77b | 2178 | |
6be4a607 JB |
2179 | if (HAS_PCH_CPT(dev)) { |
2180 | /* disable TRANS_DP_CTL */ | |
2181 | int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B; | |
2182 | int reg; | |
2183 | ||
2184 | reg = I915_READ(trans_dp_ctl); | |
2185 | reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK); | |
2186 | I915_WRITE(trans_dp_ctl, reg); | |
2187 | POSTING_READ(trans_dp_ctl); | |
2188 | ||
2189 | /* disable DPLL_SEL */ | |
2190 | temp = I915_READ(PCH_DPLL_SEL); | |
2191 | if (trans_dpll_sel == 0) | |
2192 | temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL); | |
2193 | else | |
2194 | temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); | |
2195 | I915_WRITE(PCH_DPLL_SEL, temp); | |
2196 | I915_READ(PCH_DPLL_SEL); | |
1b3c7a47 | 2197 | |
6be4a607 | 2198 | } |
e3421a18 | 2199 | |
6be4a607 JB |
2200 | /* disable PCH DPLL */ |
2201 | temp = I915_READ(pch_dpll_reg); | |
2202 | I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE); | |
2203 | I915_READ(pch_dpll_reg); | |
8db9d77b | 2204 | |
6be4a607 JB |
2205 | /* Switch from PCDclk to Rawclk */ |
2206 | temp = I915_READ(fdi_rx_reg); | |
2207 | temp &= ~FDI_SEL_PCDCLK; | |
2208 | I915_WRITE(fdi_rx_reg, temp); | |
2209 | I915_READ(fdi_rx_reg); | |
8db9d77b | 2210 | |
6be4a607 JB |
2211 | /* Disable CPU FDI TX PLL */ |
2212 | temp = I915_READ(fdi_tx_reg); | |
2213 | I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE); | |
2214 | I915_READ(fdi_tx_reg); | |
2215 | udelay(100); | |
8db9d77b | 2216 | |
6be4a607 JB |
2217 | temp = I915_READ(fdi_rx_reg); |
2218 | temp &= ~FDI_RX_PLL_ENABLE; | |
2219 | I915_WRITE(fdi_rx_reg, temp); | |
2220 | I915_READ(fdi_rx_reg); | |
2c07245f | 2221 | |
6be4a607 JB |
2222 | /* Wait for the clocks to turn off. */ |
2223 | udelay(100); | |
2224 | } | |
1b3c7a47 | 2225 | |
6be4a607 JB |
2226 | static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode) |
2227 | { | |
2228 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2229 | int pipe = intel_crtc->pipe; | |
2230 | int plane = intel_crtc->plane; | |
8db9d77b | 2231 | |
6be4a607 JB |
2232 | /* XXX: When our outputs are all unaware of DPMS modes other than off |
2233 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. | |
2234 | */ | |
2235 | switch (mode) { | |
2236 | case DRM_MODE_DPMS_ON: | |
2237 | case DRM_MODE_DPMS_STANDBY: | |
2238 | case DRM_MODE_DPMS_SUSPEND: | |
2239 | DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane); | |
2240 | ironlake_crtc_enable(crtc); | |
2241 | break; | |
1b3c7a47 | 2242 | |
6be4a607 JB |
2243 | case DRM_MODE_DPMS_OFF: |
2244 | DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane); | |
2245 | ironlake_crtc_disable(crtc); | |
2c07245f ZW |
2246 | break; |
2247 | } | |
2248 | } | |
2249 | ||
02e792fb DV |
2250 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
2251 | { | |
02e792fb | 2252 | if (!enable && intel_crtc->overlay) { |
23f09ce3 | 2253 | struct drm_device *dev = intel_crtc->base.dev; |
03f77ea5 | 2254 | |
23f09ce3 CW |
2255 | mutex_lock(&dev->struct_mutex); |
2256 | (void) intel_overlay_switch_off(intel_crtc->overlay, false); | |
2257 | mutex_unlock(&dev->struct_mutex); | |
02e792fb | 2258 | } |
02e792fb | 2259 | |
5dcdbcb0 CW |
2260 | /* Let userspace switch the overlay on again. In most cases userspace |
2261 | * has to recompute where to put it anyway. | |
2262 | */ | |
02e792fb DV |
2263 | } |
2264 | ||
0b8765c6 | 2265 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
2266 | { |
2267 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
2268 | struct drm_i915_private *dev_priv = dev->dev_private; |
2269 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2270 | int pipe = intel_crtc->pipe; | |
80824003 | 2271 | int plane = intel_crtc->plane; |
79e53945 | 2272 | int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; |
80824003 JB |
2273 | int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR; |
2274 | int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR; | |
79e53945 JB |
2275 | int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; |
2276 | u32 temp; | |
79e53945 | 2277 | |
0b8765c6 JB |
2278 | /* Enable the DPLL */ |
2279 | temp = I915_READ(dpll_reg); | |
2280 | if ((temp & DPLL_VCO_ENABLE) == 0) { | |
2281 | I915_WRITE(dpll_reg, temp); | |
2282 | I915_READ(dpll_reg); | |
2283 | /* Wait for the clocks to stabilize. */ | |
2284 | udelay(150); | |
2285 | I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE); | |
2286 | I915_READ(dpll_reg); | |
2287 | /* Wait for the clocks to stabilize. */ | |
2288 | udelay(150); | |
2289 | I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE); | |
2290 | I915_READ(dpll_reg); | |
2291 | /* Wait for the clocks to stabilize. */ | |
2292 | udelay(150); | |
2293 | } | |
79e53945 | 2294 | |
0b8765c6 JB |
2295 | /* Enable the pipe */ |
2296 | temp = I915_READ(pipeconf_reg); | |
2297 | if ((temp & PIPEACONF_ENABLE) == 0) | |
2298 | I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE); | |
79e53945 | 2299 | |
0b8765c6 JB |
2300 | /* Enable the plane */ |
2301 | temp = I915_READ(dspcntr_reg); | |
2302 | if ((temp & DISPLAY_PLANE_ENABLE) == 0) { | |
2303 | I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE); | |
2304 | /* Flush the plane changes */ | |
2305 | I915_WRITE(dspbase_reg, I915_READ(dspbase_reg)); | |
2306 | } | |
79e53945 | 2307 | |
0b8765c6 | 2308 | intel_crtc_load_lut(crtc); |
80824003 | 2309 | |
0b8765c6 JB |
2310 | if ((IS_I965G(dev) || plane == 0)) |
2311 | intel_update_fbc(crtc, &crtc->mode); | |
79e53945 | 2312 | |
0b8765c6 JB |
2313 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
2314 | intel_crtc_dpms_overlay(intel_crtc, true); | |
2315 | } | |
79e53945 | 2316 | |
0b8765c6 JB |
2317 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
2318 | { | |
2319 | struct drm_device *dev = crtc->dev; | |
2320 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2321 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2322 | int pipe = intel_crtc->pipe; | |
2323 | int plane = intel_crtc->plane; | |
2324 | int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; | |
2325 | int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR; | |
2326 | int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR; | |
2327 | int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; | |
2328 | u32 temp; | |
b690e96c | 2329 | |
0b8765c6 JB |
2330 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
2331 | intel_crtc_dpms_overlay(intel_crtc, false); | |
2332 | drm_vblank_off(dev, pipe); | |
2333 | ||
2334 | if (dev_priv->cfb_plane == plane && | |
2335 | dev_priv->display.disable_fbc) | |
2336 | dev_priv->display.disable_fbc(dev); | |
79e53945 | 2337 | |
0b8765c6 JB |
2338 | /* Disable display plane */ |
2339 | temp = I915_READ(dspcntr_reg); | |
2340 | if ((temp & DISPLAY_PLANE_ENABLE) != 0) { | |
2341 | I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE); | |
2342 | /* Flush the plane changes */ | |
2343 | I915_WRITE(dspbase_reg, I915_READ(dspbase_reg)); | |
2344 | I915_READ(dspbase_reg); | |
2345 | } | |
2346 | ||
2347 | if (!IS_I9XX(dev)) { | |
2348 | /* Wait for vblank for the disable to take effect */ | |
9d0498a2 | 2349 | intel_wait_for_vblank_off(dev, pipe); |
0b8765c6 | 2350 | } |
79e53945 | 2351 | |
0b8765c6 JB |
2352 | /* Don't disable pipe A or pipe A PLLs if needed */ |
2353 | if (pipeconf_reg == PIPEACONF && | |
2354 | (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
2355 | goto skip_pipe_off; | |
2356 | ||
2357 | /* Next, disable display pipes */ | |
2358 | temp = I915_READ(pipeconf_reg); | |
2359 | if ((temp & PIPEACONF_ENABLE) != 0) { | |
2360 | I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE); | |
2361 | I915_READ(pipeconf_reg); | |
2362 | } | |
2363 | ||
2364 | /* Wait for vblank for the disable to take effect. */ | |
2365 | intel_wait_for_vblank_off(dev, pipe); | |
2366 | ||
2367 | temp = I915_READ(dpll_reg); | |
2368 | if ((temp & DPLL_VCO_ENABLE) != 0) { | |
2369 | I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE); | |
2370 | I915_READ(dpll_reg); | |
2371 | } | |
2372 | skip_pipe_off: | |
2373 | /* Wait for the clocks to turn off. */ | |
2374 | udelay(150); | |
2375 | } | |
2376 | ||
2377 | static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode) | |
2378 | { | |
2379 | /* XXX: When our outputs are all unaware of DPMS modes other than off | |
2380 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. | |
2381 | */ | |
2382 | switch (mode) { | |
2383 | case DRM_MODE_DPMS_ON: | |
2384 | case DRM_MODE_DPMS_STANDBY: | |
2385 | case DRM_MODE_DPMS_SUSPEND: | |
2386 | i9xx_crtc_enable(crtc); | |
2387 | break; | |
2388 | case DRM_MODE_DPMS_OFF: | |
2389 | i9xx_crtc_disable(crtc); | |
79e53945 JB |
2390 | break; |
2391 | } | |
2c07245f ZW |
2392 | } |
2393 | ||
4b60e5cb CW |
2394 | /* |
2395 | * When we disable a pipe, we need to clear any pending scanline wait events | |
2396 | * to avoid hanging the ring, which we assume we are waiting on. | |
2397 | */ | |
2398 | static void intel_clear_scanline_wait(struct drm_device *dev) | |
2399 | { | |
2400 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2401 | u32 tmp; | |
2402 | ||
2403 | if (IS_GEN2(dev)) | |
2404 | /* Can't break the hang on i8xx */ | |
2405 | return; | |
2406 | ||
2407 | tmp = I915_READ(PRB0_CTL); | |
2408 | if (tmp & RING_WAIT) { | |
2409 | I915_WRITE(PRB0_CTL, tmp); | |
2410 | POSTING_READ(PRB0_CTL); | |
2411 | } | |
2412 | } | |
2413 | ||
2c07245f ZW |
2414 | /** |
2415 | * Sets the power management mode of the pipe and plane. | |
2c07245f ZW |
2416 | */ |
2417 | static void intel_crtc_dpms(struct drm_crtc *crtc, int mode) | |
2418 | { | |
2419 | struct drm_device *dev = crtc->dev; | |
e70236a8 | 2420 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f ZW |
2421 | struct drm_i915_master_private *master_priv; |
2422 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2423 | int pipe = intel_crtc->pipe; | |
2424 | bool enabled; | |
2425 | ||
032d2a0d CW |
2426 | if (intel_crtc->dpms_mode == mode) |
2427 | return; | |
2428 | ||
65655d4a | 2429 | intel_crtc->dpms_mode = mode; |
87f8ebf3 | 2430 | intel_crtc->cursor_on = mode == DRM_MODE_DPMS_ON; |
debcaddc CW |
2431 | |
2432 | /* When switching on the display, ensure that SR is disabled | |
2433 | * with multiple pipes prior to enabling to new pipe. | |
2434 | * | |
2435 | * When switching off the display, make sure the cursor is | |
4b60e5cb CW |
2436 | * properly hidden and there are no pending waits prior to |
2437 | * disabling the pipe. | |
debcaddc CW |
2438 | */ |
2439 | if (mode == DRM_MODE_DPMS_ON) | |
2440 | intel_update_watermarks(dev); | |
2441 | else | |
2442 | intel_crtc_update_cursor(crtc); | |
2443 | ||
e70236a8 | 2444 | dev_priv->display.dpms(crtc, mode); |
79e53945 | 2445 | |
debcaddc CW |
2446 | if (mode == DRM_MODE_DPMS_ON) |
2447 | intel_crtc_update_cursor(crtc); | |
4b60e5cb CW |
2448 | else { |
2449 | /* XXX Note that this is not a complete solution, but a hack | |
2450 | * to avoid the most frequently hit hang. | |
2451 | */ | |
2452 | intel_clear_scanline_wait(dev); | |
2453 | ||
debcaddc | 2454 | intel_update_watermarks(dev); |
4b60e5cb | 2455 | } |
65655d4a | 2456 | |
79e53945 JB |
2457 | if (!dev->primary->master) |
2458 | return; | |
2459 | ||
2460 | master_priv = dev->primary->master->driver_priv; | |
2461 | if (!master_priv->sarea_priv) | |
2462 | return; | |
2463 | ||
2464 | enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF; | |
2465 | ||
2466 | switch (pipe) { | |
2467 | case 0: | |
2468 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
2469 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
2470 | break; | |
2471 | case 1: | |
2472 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
2473 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
2474 | break; | |
2475 | default: | |
2476 | DRM_ERROR("Can't update pipe %d in SAREA\n", pipe); | |
2477 | break; | |
2478 | } | |
79e53945 JB |
2479 | } |
2480 | ||
2481 | static void intel_crtc_prepare (struct drm_crtc *crtc) | |
2482 | { | |
2483 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
2484 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); | |
2485 | } | |
2486 | ||
2487 | static void intel_crtc_commit (struct drm_crtc *crtc) | |
2488 | { | |
2489 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
2490 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | |
2491 | } | |
2492 | ||
2493 | void intel_encoder_prepare (struct drm_encoder *encoder) | |
2494 | { | |
2495 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
2496 | /* lvds has its own version of prepare see intel_lvds_prepare */ | |
2497 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); | |
2498 | } | |
2499 | ||
2500 | void intel_encoder_commit (struct drm_encoder *encoder) | |
2501 | { | |
2502 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
2503 | /* lvds has its own version of commit see intel_lvds_commit */ | |
2504 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); | |
2505 | } | |
2506 | ||
ea5b213a CW |
2507 | void intel_encoder_destroy(struct drm_encoder *encoder) |
2508 | { | |
4ef69c7a | 2509 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a CW |
2510 | |
2511 | if (intel_encoder->ddc_bus) | |
2512 | intel_i2c_destroy(intel_encoder->ddc_bus); | |
2513 | ||
2514 | if (intel_encoder->i2c_bus) | |
2515 | intel_i2c_destroy(intel_encoder->i2c_bus); | |
2516 | ||
2517 | drm_encoder_cleanup(encoder); | |
2518 | kfree(intel_encoder); | |
2519 | } | |
2520 | ||
79e53945 JB |
2521 | static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, |
2522 | struct drm_display_mode *mode, | |
2523 | struct drm_display_mode *adjusted_mode) | |
2524 | { | |
2c07245f | 2525 | struct drm_device *dev = crtc->dev; |
bad720ff | 2526 | if (HAS_PCH_SPLIT(dev)) { |
2c07245f | 2527 | /* FDI link clock is fixed at 2.7G */ |
2377b741 JB |
2528 | if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4) |
2529 | return false; | |
2c07245f | 2530 | } |
79e53945 JB |
2531 | return true; |
2532 | } | |
2533 | ||
e70236a8 JB |
2534 | static int i945_get_display_clock_speed(struct drm_device *dev) |
2535 | { | |
2536 | return 400000; | |
2537 | } | |
79e53945 | 2538 | |
e70236a8 | 2539 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 2540 | { |
e70236a8 JB |
2541 | return 333000; |
2542 | } | |
79e53945 | 2543 | |
e70236a8 JB |
2544 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
2545 | { | |
2546 | return 200000; | |
2547 | } | |
79e53945 | 2548 | |
e70236a8 JB |
2549 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
2550 | { | |
2551 | u16 gcfgc = 0; | |
79e53945 | 2552 | |
e70236a8 JB |
2553 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
2554 | ||
2555 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
2556 | return 133000; | |
2557 | else { | |
2558 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
2559 | case GC_DISPLAY_CLOCK_333_MHZ: | |
2560 | return 333000; | |
2561 | default: | |
2562 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
2563 | return 190000; | |
79e53945 | 2564 | } |
e70236a8 JB |
2565 | } |
2566 | } | |
2567 | ||
2568 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
2569 | { | |
2570 | return 266000; | |
2571 | } | |
2572 | ||
2573 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
2574 | { | |
2575 | u16 hpllcc = 0; | |
2576 | /* Assume that the hardware is in the high speed state. This | |
2577 | * should be the default. | |
2578 | */ | |
2579 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
2580 | case GC_CLOCK_133_200: | |
2581 | case GC_CLOCK_100_200: | |
2582 | return 200000; | |
2583 | case GC_CLOCK_166_250: | |
2584 | return 250000; | |
2585 | case GC_CLOCK_100_133: | |
79e53945 | 2586 | return 133000; |
e70236a8 | 2587 | } |
79e53945 | 2588 | |
e70236a8 JB |
2589 | /* Shouldn't happen */ |
2590 | return 0; | |
2591 | } | |
79e53945 | 2592 | |
e70236a8 JB |
2593 | static int i830_get_display_clock_speed(struct drm_device *dev) |
2594 | { | |
2595 | return 133000; | |
79e53945 JB |
2596 | } |
2597 | ||
79e53945 JB |
2598 | /** |
2599 | * Return the pipe currently connected to the panel fitter, | |
2600 | * or -1 if the panel fitter is not present or not in use | |
2601 | */ | |
02e792fb | 2602 | int intel_panel_fitter_pipe (struct drm_device *dev) |
79e53945 JB |
2603 | { |
2604 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2605 | u32 pfit_control; | |
2606 | ||
2607 | /* i830 doesn't have a panel fitter */ | |
2608 | if (IS_I830(dev)) | |
2609 | return -1; | |
2610 | ||
2611 | pfit_control = I915_READ(PFIT_CONTROL); | |
2612 | ||
2613 | /* See if the panel fitter is in use */ | |
2614 | if ((pfit_control & PFIT_ENABLE) == 0) | |
2615 | return -1; | |
2616 | ||
2617 | /* 965 can place panel fitter on either pipe */ | |
2618 | if (IS_I965G(dev)) | |
2619 | return (pfit_control >> 29) & 0x3; | |
2620 | ||
2621 | /* older chips can only use pipe 1 */ | |
2622 | return 1; | |
2623 | } | |
2624 | ||
2c07245f ZW |
2625 | struct fdi_m_n { |
2626 | u32 tu; | |
2627 | u32 gmch_m; | |
2628 | u32 gmch_n; | |
2629 | u32 link_m; | |
2630 | u32 link_n; | |
2631 | }; | |
2632 | ||
2633 | static void | |
2634 | fdi_reduce_ratio(u32 *num, u32 *den) | |
2635 | { | |
2636 | while (*num > 0xffffff || *den > 0xffffff) { | |
2637 | *num >>= 1; | |
2638 | *den >>= 1; | |
2639 | } | |
2640 | } | |
2641 | ||
2642 | #define DATA_N 0x800000 | |
2643 | #define LINK_N 0x80000 | |
2644 | ||
2645 | static void | |
f2b115e6 AJ |
2646 | ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock, |
2647 | int link_clock, struct fdi_m_n *m_n) | |
2c07245f ZW |
2648 | { |
2649 | u64 temp; | |
2650 | ||
2651 | m_n->tu = 64; /* default size */ | |
2652 | ||
2653 | temp = (u64) DATA_N * pixel_clock; | |
2654 | temp = div_u64(temp, link_clock); | |
58a27471 ZW |
2655 | m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes); |
2656 | m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */ | |
2c07245f ZW |
2657 | m_n->gmch_n = DATA_N; |
2658 | fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); | |
2659 | ||
2660 | temp = (u64) LINK_N * pixel_clock; | |
2661 | m_n->link_m = div_u64(temp, link_clock); | |
2662 | m_n->link_n = LINK_N; | |
2663 | fdi_reduce_ratio(&m_n->link_m, &m_n->link_n); | |
2664 | } | |
2665 | ||
2666 | ||
7662c8bd SL |
2667 | struct intel_watermark_params { |
2668 | unsigned long fifo_size; | |
2669 | unsigned long max_wm; | |
2670 | unsigned long default_wm; | |
2671 | unsigned long guard_size; | |
2672 | unsigned long cacheline_size; | |
2673 | }; | |
2674 | ||
f2b115e6 AJ |
2675 | /* Pineview has different values for various configs */ |
2676 | static struct intel_watermark_params pineview_display_wm = { | |
2677 | PINEVIEW_DISPLAY_FIFO, | |
2678 | PINEVIEW_MAX_WM, | |
2679 | PINEVIEW_DFT_WM, | |
2680 | PINEVIEW_GUARD_WM, | |
2681 | PINEVIEW_FIFO_LINE_SIZE | |
7662c8bd | 2682 | }; |
f2b115e6 AJ |
2683 | static struct intel_watermark_params pineview_display_hplloff_wm = { |
2684 | PINEVIEW_DISPLAY_FIFO, | |
2685 | PINEVIEW_MAX_WM, | |
2686 | PINEVIEW_DFT_HPLLOFF_WM, | |
2687 | PINEVIEW_GUARD_WM, | |
2688 | PINEVIEW_FIFO_LINE_SIZE | |
7662c8bd | 2689 | }; |
f2b115e6 AJ |
2690 | static struct intel_watermark_params pineview_cursor_wm = { |
2691 | PINEVIEW_CURSOR_FIFO, | |
2692 | PINEVIEW_CURSOR_MAX_WM, | |
2693 | PINEVIEW_CURSOR_DFT_WM, | |
2694 | PINEVIEW_CURSOR_GUARD_WM, | |
2695 | PINEVIEW_FIFO_LINE_SIZE, | |
7662c8bd | 2696 | }; |
f2b115e6 AJ |
2697 | static struct intel_watermark_params pineview_cursor_hplloff_wm = { |
2698 | PINEVIEW_CURSOR_FIFO, | |
2699 | PINEVIEW_CURSOR_MAX_WM, | |
2700 | PINEVIEW_CURSOR_DFT_WM, | |
2701 | PINEVIEW_CURSOR_GUARD_WM, | |
2702 | PINEVIEW_FIFO_LINE_SIZE | |
7662c8bd | 2703 | }; |
0e442c60 JB |
2704 | static struct intel_watermark_params g4x_wm_info = { |
2705 | G4X_FIFO_SIZE, | |
2706 | G4X_MAX_WM, | |
2707 | G4X_MAX_WM, | |
2708 | 2, | |
2709 | G4X_FIFO_LINE_SIZE, | |
2710 | }; | |
4fe5e611 ZY |
2711 | static struct intel_watermark_params g4x_cursor_wm_info = { |
2712 | I965_CURSOR_FIFO, | |
2713 | I965_CURSOR_MAX_WM, | |
2714 | I965_CURSOR_DFT_WM, | |
2715 | 2, | |
2716 | G4X_FIFO_LINE_SIZE, | |
2717 | }; | |
2718 | static struct intel_watermark_params i965_cursor_wm_info = { | |
2719 | I965_CURSOR_FIFO, | |
2720 | I965_CURSOR_MAX_WM, | |
2721 | I965_CURSOR_DFT_WM, | |
2722 | 2, | |
2723 | I915_FIFO_LINE_SIZE, | |
2724 | }; | |
7662c8bd | 2725 | static struct intel_watermark_params i945_wm_info = { |
dff33cfc | 2726 | I945_FIFO_SIZE, |
7662c8bd SL |
2727 | I915_MAX_WM, |
2728 | 1, | |
dff33cfc JB |
2729 | 2, |
2730 | I915_FIFO_LINE_SIZE | |
7662c8bd SL |
2731 | }; |
2732 | static struct intel_watermark_params i915_wm_info = { | |
dff33cfc | 2733 | I915_FIFO_SIZE, |
7662c8bd SL |
2734 | I915_MAX_WM, |
2735 | 1, | |
dff33cfc | 2736 | 2, |
7662c8bd SL |
2737 | I915_FIFO_LINE_SIZE |
2738 | }; | |
2739 | static struct intel_watermark_params i855_wm_info = { | |
2740 | I855GM_FIFO_SIZE, | |
2741 | I915_MAX_WM, | |
2742 | 1, | |
dff33cfc | 2743 | 2, |
7662c8bd SL |
2744 | I830_FIFO_LINE_SIZE |
2745 | }; | |
2746 | static struct intel_watermark_params i830_wm_info = { | |
2747 | I830_FIFO_SIZE, | |
2748 | I915_MAX_WM, | |
2749 | 1, | |
dff33cfc | 2750 | 2, |
7662c8bd SL |
2751 | I830_FIFO_LINE_SIZE |
2752 | }; | |
2753 | ||
7f8a8569 ZW |
2754 | static struct intel_watermark_params ironlake_display_wm_info = { |
2755 | ILK_DISPLAY_FIFO, | |
2756 | ILK_DISPLAY_MAXWM, | |
2757 | ILK_DISPLAY_DFTWM, | |
2758 | 2, | |
2759 | ILK_FIFO_LINE_SIZE | |
2760 | }; | |
2761 | ||
c936f44d ZY |
2762 | static struct intel_watermark_params ironlake_cursor_wm_info = { |
2763 | ILK_CURSOR_FIFO, | |
2764 | ILK_CURSOR_MAXWM, | |
2765 | ILK_CURSOR_DFTWM, | |
2766 | 2, | |
2767 | ILK_FIFO_LINE_SIZE | |
2768 | }; | |
2769 | ||
7f8a8569 ZW |
2770 | static struct intel_watermark_params ironlake_display_srwm_info = { |
2771 | ILK_DISPLAY_SR_FIFO, | |
2772 | ILK_DISPLAY_MAX_SRWM, | |
2773 | ILK_DISPLAY_DFT_SRWM, | |
2774 | 2, | |
2775 | ILK_FIFO_LINE_SIZE | |
2776 | }; | |
2777 | ||
2778 | static struct intel_watermark_params ironlake_cursor_srwm_info = { | |
2779 | ILK_CURSOR_SR_FIFO, | |
2780 | ILK_CURSOR_MAX_SRWM, | |
2781 | ILK_CURSOR_DFT_SRWM, | |
2782 | 2, | |
2783 | ILK_FIFO_LINE_SIZE | |
2784 | }; | |
2785 | ||
dff33cfc JB |
2786 | /** |
2787 | * intel_calculate_wm - calculate watermark level | |
2788 | * @clock_in_khz: pixel clock | |
2789 | * @wm: chip FIFO params | |
2790 | * @pixel_size: display pixel size | |
2791 | * @latency_ns: memory latency for the platform | |
2792 | * | |
2793 | * Calculate the watermark level (the level at which the display plane will | |
2794 | * start fetching from memory again). Each chip has a different display | |
2795 | * FIFO size and allocation, so the caller needs to figure that out and pass | |
2796 | * in the correct intel_watermark_params structure. | |
2797 | * | |
2798 | * As the pixel clock runs, the FIFO will be drained at a rate that depends | |
2799 | * on the pixel size. When it reaches the watermark level, it'll start | |
2800 | * fetching FIFO line sized based chunks from memory until the FIFO fills | |
2801 | * past the watermark point. If the FIFO drains completely, a FIFO underrun | |
2802 | * will occur, and a display engine hang could result. | |
2803 | */ | |
7662c8bd SL |
2804 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, |
2805 | struct intel_watermark_params *wm, | |
2806 | int pixel_size, | |
2807 | unsigned long latency_ns) | |
2808 | { | |
390c4dd4 | 2809 | long entries_required, wm_size; |
dff33cfc | 2810 | |
d660467c JB |
2811 | /* |
2812 | * Note: we need to make sure we don't overflow for various clock & | |
2813 | * latency values. | |
2814 | * clocks go from a few thousand to several hundred thousand. | |
2815 | * latency is usually a few thousand | |
2816 | */ | |
2817 | entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / | |
2818 | 1000; | |
8de9b311 | 2819 | entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); |
7662c8bd | 2820 | |
28c97730 | 2821 | DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required); |
dff33cfc JB |
2822 | |
2823 | wm_size = wm->fifo_size - (entries_required + wm->guard_size); | |
2824 | ||
28c97730 | 2825 | DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size); |
7662c8bd | 2826 | |
390c4dd4 JB |
2827 | /* Don't promote wm_size to unsigned... */ |
2828 | if (wm_size > (long)wm->max_wm) | |
7662c8bd | 2829 | wm_size = wm->max_wm; |
c3add4b6 | 2830 | if (wm_size <= 0) |
7662c8bd SL |
2831 | wm_size = wm->default_wm; |
2832 | return wm_size; | |
2833 | } | |
2834 | ||
2835 | struct cxsr_latency { | |
2836 | int is_desktop; | |
95534263 | 2837 | int is_ddr3; |
7662c8bd SL |
2838 | unsigned long fsb_freq; |
2839 | unsigned long mem_freq; | |
2840 | unsigned long display_sr; | |
2841 | unsigned long display_hpll_disable; | |
2842 | unsigned long cursor_sr; | |
2843 | unsigned long cursor_hpll_disable; | |
2844 | }; | |
2845 | ||
403c89ff | 2846 | static const struct cxsr_latency cxsr_latency_table[] = { |
95534263 LP |
2847 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ |
2848 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ | |
2849 | {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ | |
2850 | {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ | |
2851 | {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ | |
2852 | ||
2853 | {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ | |
2854 | {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ | |
2855 | {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ | |
2856 | {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ | |
2857 | {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ | |
2858 | ||
2859 | {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ | |
2860 | {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ | |
2861 | {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ | |
2862 | {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ | |
2863 | {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ | |
2864 | ||
2865 | {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ | |
2866 | {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ | |
2867 | {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ | |
2868 | {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ | |
2869 | {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ | |
2870 | ||
2871 | {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ | |
2872 | {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ | |
2873 | {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ | |
2874 | {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ | |
2875 | {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ | |
2876 | ||
2877 | {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ | |
2878 | {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ | |
2879 | {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ | |
2880 | {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ | |
2881 | {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ | |
7662c8bd SL |
2882 | }; |
2883 | ||
403c89ff CW |
2884 | static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, |
2885 | int is_ddr3, | |
2886 | int fsb, | |
2887 | int mem) | |
7662c8bd | 2888 | { |
403c89ff | 2889 | const struct cxsr_latency *latency; |
7662c8bd | 2890 | int i; |
7662c8bd SL |
2891 | |
2892 | if (fsb == 0 || mem == 0) | |
2893 | return NULL; | |
2894 | ||
2895 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { | |
2896 | latency = &cxsr_latency_table[i]; | |
2897 | if (is_desktop == latency->is_desktop && | |
95534263 | 2898 | is_ddr3 == latency->is_ddr3 && |
decbbcda JSR |
2899 | fsb == latency->fsb_freq && mem == latency->mem_freq) |
2900 | return latency; | |
7662c8bd | 2901 | } |
decbbcda | 2902 | |
28c97730 | 2903 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); |
decbbcda JSR |
2904 | |
2905 | return NULL; | |
7662c8bd SL |
2906 | } |
2907 | ||
f2b115e6 | 2908 | static void pineview_disable_cxsr(struct drm_device *dev) |
7662c8bd SL |
2909 | { |
2910 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7662c8bd SL |
2911 | |
2912 | /* deactivate cxsr */ | |
3e33d94d | 2913 | I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN); |
7662c8bd SL |
2914 | } |
2915 | ||
bcc24fb4 JB |
2916 | /* |
2917 | * Latency for FIFO fetches is dependent on several factors: | |
2918 | * - memory configuration (speed, channels) | |
2919 | * - chipset | |
2920 | * - current MCH state | |
2921 | * It can be fairly high in some situations, so here we assume a fairly | |
2922 | * pessimal value. It's a tradeoff between extra memory fetches (if we | |
2923 | * set this value too high, the FIFO will fetch frequently to stay full) | |
2924 | * and power consumption (set it too low to save power and we might see | |
2925 | * FIFO underruns and display "flicker"). | |
2926 | * | |
2927 | * A value of 5us seems to be a good balance; safe for very low end | |
2928 | * platforms but not overly aggressive on lower latency configs. | |
2929 | */ | |
69e302a9 | 2930 | static const int latency_ns = 5000; |
7662c8bd | 2931 | |
e70236a8 | 2932 | static int i9xx_get_fifo_size(struct drm_device *dev, int plane) |
dff33cfc JB |
2933 | { |
2934 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2935 | uint32_t dsparb = I915_READ(DSPARB); | |
2936 | int size; | |
2937 | ||
8de9b311 CW |
2938 | size = dsparb & 0x7f; |
2939 | if (plane) | |
2940 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; | |
dff33cfc | 2941 | |
28c97730 ZY |
2942 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
2943 | plane ? "B" : "A", size); | |
dff33cfc JB |
2944 | |
2945 | return size; | |
2946 | } | |
7662c8bd | 2947 | |
e70236a8 JB |
2948 | static int i85x_get_fifo_size(struct drm_device *dev, int plane) |
2949 | { | |
2950 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2951 | uint32_t dsparb = I915_READ(DSPARB); | |
2952 | int size; | |
2953 | ||
8de9b311 CW |
2954 | size = dsparb & 0x1ff; |
2955 | if (plane) | |
2956 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; | |
e70236a8 | 2957 | size >>= 1; /* Convert to cachelines */ |
dff33cfc | 2958 | |
28c97730 ZY |
2959 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
2960 | plane ? "B" : "A", size); | |
dff33cfc JB |
2961 | |
2962 | return size; | |
2963 | } | |
7662c8bd | 2964 | |
e70236a8 JB |
2965 | static int i845_get_fifo_size(struct drm_device *dev, int plane) |
2966 | { | |
2967 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2968 | uint32_t dsparb = I915_READ(DSPARB); | |
2969 | int size; | |
2970 | ||
2971 | size = dsparb & 0x7f; | |
2972 | size >>= 2; /* Convert to cachelines */ | |
2973 | ||
28c97730 ZY |
2974 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
2975 | plane ? "B" : "A", | |
e70236a8 JB |
2976 | size); |
2977 | ||
2978 | return size; | |
2979 | } | |
2980 | ||
2981 | static int i830_get_fifo_size(struct drm_device *dev, int plane) | |
2982 | { | |
2983 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2984 | uint32_t dsparb = I915_READ(DSPARB); | |
2985 | int size; | |
2986 | ||
2987 | size = dsparb & 0x7f; | |
2988 | size >>= 1; /* Convert to cachelines */ | |
2989 | ||
28c97730 ZY |
2990 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
2991 | plane ? "B" : "A", size); | |
e70236a8 JB |
2992 | |
2993 | return size; | |
2994 | } | |
2995 | ||
d4294342 | 2996 | static void pineview_update_wm(struct drm_device *dev, int planea_clock, |
fa143215 ZY |
2997 | int planeb_clock, int sr_hdisplay, int unused, |
2998 | int pixel_size) | |
d4294342 ZY |
2999 | { |
3000 | struct drm_i915_private *dev_priv = dev->dev_private; | |
403c89ff | 3001 | const struct cxsr_latency *latency; |
d4294342 ZY |
3002 | u32 reg; |
3003 | unsigned long wm; | |
d4294342 ZY |
3004 | int sr_clock; |
3005 | ||
403c89ff | 3006 | latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, |
95534263 | 3007 | dev_priv->fsb_freq, dev_priv->mem_freq); |
d4294342 ZY |
3008 | if (!latency) { |
3009 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); | |
3010 | pineview_disable_cxsr(dev); | |
3011 | return; | |
3012 | } | |
3013 | ||
3014 | if (!planea_clock || !planeb_clock) { | |
3015 | sr_clock = planea_clock ? planea_clock : planeb_clock; | |
3016 | ||
3017 | /* Display SR */ | |
3018 | wm = intel_calculate_wm(sr_clock, &pineview_display_wm, | |
3019 | pixel_size, latency->display_sr); | |
3020 | reg = I915_READ(DSPFW1); | |
3021 | reg &= ~DSPFW_SR_MASK; | |
3022 | reg |= wm << DSPFW_SR_SHIFT; | |
3023 | I915_WRITE(DSPFW1, reg); | |
3024 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); | |
3025 | ||
3026 | /* cursor SR */ | |
3027 | wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm, | |
3028 | pixel_size, latency->cursor_sr); | |
3029 | reg = I915_READ(DSPFW3); | |
3030 | reg &= ~DSPFW_CURSOR_SR_MASK; | |
3031 | reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT; | |
3032 | I915_WRITE(DSPFW3, reg); | |
3033 | ||
3034 | /* Display HPLL off SR */ | |
3035 | wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm, | |
3036 | pixel_size, latency->display_hpll_disable); | |
3037 | reg = I915_READ(DSPFW3); | |
3038 | reg &= ~DSPFW_HPLL_SR_MASK; | |
3039 | reg |= wm & DSPFW_HPLL_SR_MASK; | |
3040 | I915_WRITE(DSPFW3, reg); | |
3041 | ||
3042 | /* cursor HPLL off SR */ | |
3043 | wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm, | |
3044 | pixel_size, latency->cursor_hpll_disable); | |
3045 | reg = I915_READ(DSPFW3); | |
3046 | reg &= ~DSPFW_HPLL_CURSOR_MASK; | |
3047 | reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT; | |
3048 | I915_WRITE(DSPFW3, reg); | |
3049 | DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); | |
3050 | ||
3051 | /* activate cxsr */ | |
3e33d94d CW |
3052 | I915_WRITE(DSPFW3, |
3053 | I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN); | |
d4294342 ZY |
3054 | DRM_DEBUG_KMS("Self-refresh is enabled\n"); |
3055 | } else { | |
3056 | pineview_disable_cxsr(dev); | |
3057 | DRM_DEBUG_KMS("Self-refresh is disabled\n"); | |
3058 | } | |
3059 | } | |
3060 | ||
0e442c60 | 3061 | static void g4x_update_wm(struct drm_device *dev, int planea_clock, |
fa143215 ZY |
3062 | int planeb_clock, int sr_hdisplay, int sr_htotal, |
3063 | int pixel_size) | |
652c393a JB |
3064 | { |
3065 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0e442c60 JB |
3066 | int total_size, cacheline_size; |
3067 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr; | |
3068 | struct intel_watermark_params planea_params, planeb_params; | |
3069 | unsigned long line_time_us; | |
3070 | int sr_clock, sr_entries = 0, entries_required; | |
652c393a | 3071 | |
0e442c60 JB |
3072 | /* Create copies of the base settings for each pipe */ |
3073 | planea_params = planeb_params = g4x_wm_info; | |
3074 | ||
3075 | /* Grab a couple of global values before we overwrite them */ | |
3076 | total_size = planea_params.fifo_size; | |
3077 | cacheline_size = planea_params.cacheline_size; | |
3078 | ||
3079 | /* | |
3080 | * Note: we need to make sure we don't overflow for various clock & | |
3081 | * latency values. | |
3082 | * clocks go from a few thousand to several hundred thousand. | |
3083 | * latency is usually a few thousand | |
3084 | */ | |
3085 | entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) / | |
3086 | 1000; | |
8de9b311 | 3087 | entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE); |
0e442c60 JB |
3088 | planea_wm = entries_required + planea_params.guard_size; |
3089 | ||
3090 | entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) / | |
3091 | 1000; | |
8de9b311 | 3092 | entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE); |
0e442c60 JB |
3093 | planeb_wm = entries_required + planeb_params.guard_size; |
3094 | ||
3095 | cursora_wm = cursorb_wm = 16; | |
3096 | cursor_sr = 32; | |
3097 | ||
3098 | DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); | |
3099 | ||
3100 | /* Calc sr entries for one plane configs */ | |
3101 | if (sr_hdisplay && (!planea_clock || !planeb_clock)) { | |
3102 | /* self-refresh has much higher latency */ | |
69e302a9 | 3103 | static const int sr_latency_ns = 12000; |
0e442c60 JB |
3104 | |
3105 | sr_clock = planea_clock ? planea_clock : planeb_clock; | |
fa143215 | 3106 | line_time_us = ((sr_htotal * 1000) / sr_clock); |
0e442c60 JB |
3107 | |
3108 | /* Use ns/us then divide to preserve precision */ | |
fa143215 ZY |
3109 | sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
3110 | pixel_size * sr_hdisplay; | |
8de9b311 | 3111 | sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size); |
4fe5e611 ZY |
3112 | |
3113 | entries_required = (((sr_latency_ns / line_time_us) + | |
3114 | 1000) / 1000) * pixel_size * 64; | |
8de9b311 CW |
3115 | entries_required = DIV_ROUND_UP(entries_required, |
3116 | g4x_cursor_wm_info.cacheline_size); | |
4fe5e611 ZY |
3117 | cursor_sr = entries_required + g4x_cursor_wm_info.guard_size; |
3118 | ||
3119 | if (cursor_sr > g4x_cursor_wm_info.max_wm) | |
3120 | cursor_sr = g4x_cursor_wm_info.max_wm; | |
3121 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " | |
3122 | "cursor %d\n", sr_entries, cursor_sr); | |
3123 | ||
0e442c60 | 3124 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
33c5fd12 DJ |
3125 | } else { |
3126 | /* Turn off self refresh if both pipes are enabled */ | |
3127 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) | |
3128 | & ~FW_BLC_SELF_EN); | |
0e442c60 JB |
3129 | } |
3130 | ||
3131 | DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n", | |
3132 | planea_wm, planeb_wm, sr_entries); | |
3133 | ||
3134 | planea_wm &= 0x3f; | |
3135 | planeb_wm &= 0x3f; | |
3136 | ||
3137 | I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) | | |
3138 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | | |
3139 | (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm); | |
3140 | I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) | | |
3141 | (cursora_wm << DSPFW_CURSORA_SHIFT)); | |
3142 | /* HPLL off in SR has some issues on G4x... disable it */ | |
3143 | I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) | | |
3144 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); | |
652c393a JB |
3145 | } |
3146 | ||
1dc7546d | 3147 | static void i965_update_wm(struct drm_device *dev, int planea_clock, |
fa143215 ZY |
3148 | int planeb_clock, int sr_hdisplay, int sr_htotal, |
3149 | int pixel_size) | |
7662c8bd SL |
3150 | { |
3151 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1dc7546d JB |
3152 | unsigned long line_time_us; |
3153 | int sr_clock, sr_entries, srwm = 1; | |
4fe5e611 | 3154 | int cursor_sr = 16; |
1dc7546d JB |
3155 | |
3156 | /* Calc sr entries for one plane configs */ | |
3157 | if (sr_hdisplay && (!planea_clock || !planeb_clock)) { | |
3158 | /* self-refresh has much higher latency */ | |
69e302a9 | 3159 | static const int sr_latency_ns = 12000; |
1dc7546d JB |
3160 | |
3161 | sr_clock = planea_clock ? planea_clock : planeb_clock; | |
fa143215 | 3162 | line_time_us = ((sr_htotal * 1000) / sr_clock); |
1dc7546d JB |
3163 | |
3164 | /* Use ns/us then divide to preserve precision */ | |
fa143215 ZY |
3165 | sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
3166 | pixel_size * sr_hdisplay; | |
8de9b311 | 3167 | sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE); |
1dc7546d | 3168 | DRM_DEBUG("self-refresh entries: %d\n", sr_entries); |
1b07e04e | 3169 | srwm = I965_FIFO_SIZE - sr_entries; |
1dc7546d JB |
3170 | if (srwm < 0) |
3171 | srwm = 1; | |
1b07e04e | 3172 | srwm &= 0x1ff; |
4fe5e611 ZY |
3173 | |
3174 | sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
3175 | pixel_size * 64; | |
8de9b311 CW |
3176 | sr_entries = DIV_ROUND_UP(sr_entries, |
3177 | i965_cursor_wm_info.cacheline_size); | |
4fe5e611 ZY |
3178 | cursor_sr = i965_cursor_wm_info.fifo_size - |
3179 | (sr_entries + i965_cursor_wm_info.guard_size); | |
3180 | ||
3181 | if (cursor_sr > i965_cursor_wm_info.max_wm) | |
3182 | cursor_sr = i965_cursor_wm_info.max_wm; | |
3183 | ||
3184 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " | |
3185 | "cursor %d\n", srwm, cursor_sr); | |
3186 | ||
adcdbc66 JB |
3187 | if (IS_I965GM(dev)) |
3188 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); | |
33c5fd12 DJ |
3189 | } else { |
3190 | /* Turn off self refresh if both pipes are enabled */ | |
adcdbc66 JB |
3191 | if (IS_I965GM(dev)) |
3192 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) | |
3193 | & ~FW_BLC_SELF_EN); | |
1dc7546d | 3194 | } |
7662c8bd | 3195 | |
1dc7546d JB |
3196 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", |
3197 | srwm); | |
7662c8bd SL |
3198 | |
3199 | /* 965 has limitations... */ | |
1dc7546d JB |
3200 | I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) | |
3201 | (8 << 0)); | |
7662c8bd | 3202 | I915_WRITE(DSPFW2, (8 << 8) | (8 << 0)); |
4fe5e611 ZY |
3203 | /* update cursor SR watermark */ |
3204 | I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); | |
7662c8bd SL |
3205 | } |
3206 | ||
3207 | static void i9xx_update_wm(struct drm_device *dev, int planea_clock, | |
fa143215 ZY |
3208 | int planeb_clock, int sr_hdisplay, int sr_htotal, |
3209 | int pixel_size) | |
7662c8bd SL |
3210 | { |
3211 | struct drm_i915_private *dev_priv = dev->dev_private; | |
dff33cfc JB |
3212 | uint32_t fwater_lo; |
3213 | uint32_t fwater_hi; | |
3214 | int total_size, cacheline_size, cwm, srwm = 1; | |
3215 | int planea_wm, planeb_wm; | |
3216 | struct intel_watermark_params planea_params, planeb_params; | |
7662c8bd SL |
3217 | unsigned long line_time_us; |
3218 | int sr_clock, sr_entries = 0; | |
3219 | ||
dff33cfc | 3220 | /* Create copies of the base settings for each pipe */ |
7662c8bd | 3221 | if (IS_I965GM(dev) || IS_I945GM(dev)) |
dff33cfc | 3222 | planea_params = planeb_params = i945_wm_info; |
7662c8bd | 3223 | else if (IS_I9XX(dev)) |
dff33cfc | 3224 | planea_params = planeb_params = i915_wm_info; |
7662c8bd | 3225 | else |
dff33cfc | 3226 | planea_params = planeb_params = i855_wm_info; |
7662c8bd | 3227 | |
dff33cfc JB |
3228 | /* Grab a couple of global values before we overwrite them */ |
3229 | total_size = planea_params.fifo_size; | |
3230 | cacheline_size = planea_params.cacheline_size; | |
7662c8bd | 3231 | |
dff33cfc | 3232 | /* Update per-plane FIFO sizes */ |
e70236a8 JB |
3233 | planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0); |
3234 | planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1); | |
7662c8bd | 3235 | |
dff33cfc JB |
3236 | planea_wm = intel_calculate_wm(planea_clock, &planea_params, |
3237 | pixel_size, latency_ns); | |
3238 | planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params, | |
3239 | pixel_size, latency_ns); | |
28c97730 | 3240 | DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); |
7662c8bd SL |
3241 | |
3242 | /* | |
3243 | * Overlay gets an aggressive default since video jitter is bad. | |
3244 | */ | |
3245 | cwm = 2; | |
3246 | ||
dff33cfc | 3247 | /* Calc sr entries for one plane configs */ |
652c393a JB |
3248 | if (HAS_FW_BLC(dev) && sr_hdisplay && |
3249 | (!planea_clock || !planeb_clock)) { | |
dff33cfc | 3250 | /* self-refresh has much higher latency */ |
69e302a9 | 3251 | static const int sr_latency_ns = 6000; |
dff33cfc | 3252 | |
7662c8bd | 3253 | sr_clock = planea_clock ? planea_clock : planeb_clock; |
fa143215 | 3254 | line_time_us = ((sr_htotal * 1000) / sr_clock); |
dff33cfc JB |
3255 | |
3256 | /* Use ns/us then divide to preserve precision */ | |
fa143215 ZY |
3257 | sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
3258 | pixel_size * sr_hdisplay; | |
8de9b311 | 3259 | sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size); |
28c97730 | 3260 | DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries); |
dff33cfc JB |
3261 | srwm = total_size - sr_entries; |
3262 | if (srwm < 0) | |
3263 | srwm = 1; | |
ee980b80 LP |
3264 | |
3265 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
3266 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); | |
3267 | else if (IS_I915GM(dev)) { | |
3268 | /* 915M has a smaller SRWM field */ | |
3269 | I915_WRITE(FW_BLC_SELF, srwm & 0x3f); | |
3270 | I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN); | |
3271 | } | |
33c5fd12 DJ |
3272 | } else { |
3273 | /* Turn off self refresh if both pipes are enabled */ | |
ee980b80 LP |
3274 | if (IS_I945G(dev) || IS_I945GM(dev)) { |
3275 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) | |
3276 | & ~FW_BLC_SELF_EN); | |
3277 | } else if (IS_I915GM(dev)) { | |
3278 | I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN); | |
3279 | } | |
7662c8bd SL |
3280 | } |
3281 | ||
28c97730 | 3282 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", |
dff33cfc | 3283 | planea_wm, planeb_wm, cwm, srwm); |
7662c8bd | 3284 | |
dff33cfc JB |
3285 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); |
3286 | fwater_hi = (cwm & 0x1f); | |
3287 | ||
3288 | /* Set request length to 8 cachelines per fetch */ | |
3289 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); | |
3290 | fwater_hi = fwater_hi | (1 << 8); | |
7662c8bd SL |
3291 | |
3292 | I915_WRITE(FW_BLC, fwater_lo); | |
3293 | I915_WRITE(FW_BLC2, fwater_hi); | |
7662c8bd SL |
3294 | } |
3295 | ||
e70236a8 | 3296 | static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused, |
fa143215 | 3297 | int unused2, int unused3, int pixel_size) |
7662c8bd SL |
3298 | { |
3299 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f3601326 | 3300 | uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff; |
dff33cfc | 3301 | int planea_wm; |
7662c8bd | 3302 | |
e70236a8 | 3303 | i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0); |
7662c8bd | 3304 | |
dff33cfc JB |
3305 | planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info, |
3306 | pixel_size, latency_ns); | |
f3601326 JB |
3307 | fwater_lo |= (3<<8) | planea_wm; |
3308 | ||
28c97730 | 3309 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); |
7662c8bd SL |
3310 | |
3311 | I915_WRITE(FW_BLC, fwater_lo); | |
3312 | } | |
3313 | ||
7f8a8569 | 3314 | #define ILK_LP0_PLANE_LATENCY 700 |
c936f44d | 3315 | #define ILK_LP0_CURSOR_LATENCY 1300 |
7f8a8569 ZW |
3316 | |
3317 | static void ironlake_update_wm(struct drm_device *dev, int planea_clock, | |
fa143215 ZY |
3318 | int planeb_clock, int sr_hdisplay, int sr_htotal, |
3319 | int pixel_size) | |
7f8a8569 ZW |
3320 | { |
3321 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3322 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; | |
3323 | int sr_wm, cursor_wm; | |
3324 | unsigned long line_time_us; | |
3325 | int sr_clock, entries_required; | |
3326 | u32 reg_value; | |
c936f44d ZY |
3327 | int line_count; |
3328 | int planea_htotal = 0, planeb_htotal = 0; | |
3329 | struct drm_crtc *crtc; | |
c936f44d ZY |
3330 | |
3331 | /* Need htotal for all active display plane */ | |
3332 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
debcaddc CW |
3333 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3334 | if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) { | |
c936f44d ZY |
3335 | if (intel_crtc->plane == 0) |
3336 | planea_htotal = crtc->mode.htotal; | |
3337 | else | |
3338 | planeb_htotal = crtc->mode.htotal; | |
3339 | } | |
3340 | } | |
7f8a8569 ZW |
3341 | |
3342 | /* Calculate and update the watermark for plane A */ | |
3343 | if (planea_clock) { | |
3344 | entries_required = ((planea_clock / 1000) * pixel_size * | |
3345 | ILK_LP0_PLANE_LATENCY) / 1000; | |
3346 | entries_required = DIV_ROUND_UP(entries_required, | |
8de9b311 | 3347 | ironlake_display_wm_info.cacheline_size); |
7f8a8569 ZW |
3348 | planea_wm = entries_required + |
3349 | ironlake_display_wm_info.guard_size; | |
3350 | ||
3351 | if (planea_wm > (int)ironlake_display_wm_info.max_wm) | |
3352 | planea_wm = ironlake_display_wm_info.max_wm; | |
3353 | ||
c936f44d ZY |
3354 | /* Use the large buffer method to calculate cursor watermark */ |
3355 | line_time_us = (planea_htotal * 1000) / planea_clock; | |
3356 | ||
3357 | /* Use ns/us then divide to preserve precision */ | |
3358 | line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000; | |
3359 | ||
3360 | /* calculate the cursor watermark for cursor A */ | |
3361 | entries_required = line_count * 64 * pixel_size; | |
3362 | entries_required = DIV_ROUND_UP(entries_required, | |
3363 | ironlake_cursor_wm_info.cacheline_size); | |
3364 | cursora_wm = entries_required + ironlake_cursor_wm_info.guard_size; | |
3365 | if (cursora_wm > ironlake_cursor_wm_info.max_wm) | |
3366 | cursora_wm = ironlake_cursor_wm_info.max_wm; | |
3367 | ||
7f8a8569 ZW |
3368 | reg_value = I915_READ(WM0_PIPEA_ILK); |
3369 | reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); | |
3370 | reg_value |= (planea_wm << WM0_PIPE_PLANE_SHIFT) | | |
3371 | (cursora_wm & WM0_PIPE_CURSOR_MASK); | |
3372 | I915_WRITE(WM0_PIPEA_ILK, reg_value); | |
3373 | DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, " | |
3374 | "cursor: %d\n", planea_wm, cursora_wm); | |
3375 | } | |
3376 | /* Calculate and update the watermark for plane B */ | |
3377 | if (planeb_clock) { | |
3378 | entries_required = ((planeb_clock / 1000) * pixel_size * | |
3379 | ILK_LP0_PLANE_LATENCY) / 1000; | |
3380 | entries_required = DIV_ROUND_UP(entries_required, | |
8de9b311 | 3381 | ironlake_display_wm_info.cacheline_size); |
7f8a8569 ZW |
3382 | planeb_wm = entries_required + |
3383 | ironlake_display_wm_info.guard_size; | |
3384 | ||
3385 | if (planeb_wm > (int)ironlake_display_wm_info.max_wm) | |
3386 | planeb_wm = ironlake_display_wm_info.max_wm; | |
3387 | ||
c936f44d ZY |
3388 | /* Use the large buffer method to calculate cursor watermark */ |
3389 | line_time_us = (planeb_htotal * 1000) / planeb_clock; | |
3390 | ||
3391 | /* Use ns/us then divide to preserve precision */ | |
3392 | line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000; | |
3393 | ||
3394 | /* calculate the cursor watermark for cursor B */ | |
3395 | entries_required = line_count * 64 * pixel_size; | |
3396 | entries_required = DIV_ROUND_UP(entries_required, | |
3397 | ironlake_cursor_wm_info.cacheline_size); | |
3398 | cursorb_wm = entries_required + ironlake_cursor_wm_info.guard_size; | |
3399 | if (cursorb_wm > ironlake_cursor_wm_info.max_wm) | |
3400 | cursorb_wm = ironlake_cursor_wm_info.max_wm; | |
3401 | ||
7f8a8569 ZW |
3402 | reg_value = I915_READ(WM0_PIPEB_ILK); |
3403 | reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); | |
3404 | reg_value |= (planeb_wm << WM0_PIPE_PLANE_SHIFT) | | |
3405 | (cursorb_wm & WM0_PIPE_CURSOR_MASK); | |
3406 | I915_WRITE(WM0_PIPEB_ILK, reg_value); | |
3407 | DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, " | |
3408 | "cursor: %d\n", planeb_wm, cursorb_wm); | |
3409 | } | |
3410 | ||
3411 | /* | |
3412 | * Calculate and update the self-refresh watermark only when one | |
3413 | * display plane is used. | |
3414 | */ | |
3415 | if (!planea_clock || !planeb_clock) { | |
c936f44d | 3416 | |
7f8a8569 ZW |
3417 | /* Read the self-refresh latency. The unit is 0.5us */ |
3418 | int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK; | |
3419 | ||
3420 | sr_clock = planea_clock ? planea_clock : planeb_clock; | |
fa143215 | 3421 | line_time_us = ((sr_htotal * 1000) / sr_clock); |
7f8a8569 ZW |
3422 | |
3423 | /* Use ns/us then divide to preserve precision */ | |
3424 | line_count = ((ilk_sr_latency * 500) / line_time_us + 1000) | |
3425 | / 1000; | |
3426 | ||
3427 | /* calculate the self-refresh watermark for display plane */ | |
3428 | entries_required = line_count * sr_hdisplay * pixel_size; | |
3429 | entries_required = DIV_ROUND_UP(entries_required, | |
8de9b311 | 3430 | ironlake_display_srwm_info.cacheline_size); |
7f8a8569 ZW |
3431 | sr_wm = entries_required + |
3432 | ironlake_display_srwm_info.guard_size; | |
3433 | ||
3434 | /* calculate the self-refresh watermark for display cursor */ | |
3435 | entries_required = line_count * pixel_size * 64; | |
3436 | entries_required = DIV_ROUND_UP(entries_required, | |
8de9b311 | 3437 | ironlake_cursor_srwm_info.cacheline_size); |
7f8a8569 ZW |
3438 | cursor_wm = entries_required + |
3439 | ironlake_cursor_srwm_info.guard_size; | |
3440 | ||
3441 | /* configure watermark and enable self-refresh */ | |
3442 | reg_value = I915_READ(WM1_LP_ILK); | |
3443 | reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK | | |
3444 | WM1_LP_CURSOR_MASK); | |
3445 | reg_value |= WM1_LP_SR_EN | | |
3446 | (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) | | |
3447 | (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm; | |
3448 | ||
3449 | I915_WRITE(WM1_LP_ILK, reg_value); | |
3450 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " | |
3451 | "cursor %d\n", sr_wm, cursor_wm); | |
3452 | ||
3453 | } else { | |
3454 | /* Turn off self refresh if both pipes are enabled */ | |
3455 | I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN); | |
3456 | } | |
3457 | } | |
7662c8bd SL |
3458 | /** |
3459 | * intel_update_watermarks - update FIFO watermark values based on current modes | |
3460 | * | |
3461 | * Calculate watermark values for the various WM regs based on current mode | |
3462 | * and plane configuration. | |
3463 | * | |
3464 | * There are several cases to deal with here: | |
3465 | * - normal (i.e. non-self-refresh) | |
3466 | * - self-refresh (SR) mode | |
3467 | * - lines are large relative to FIFO size (buffer can hold up to 2) | |
3468 | * - lines are small relative to FIFO size (buffer can hold more than 2 | |
3469 | * lines), so need to account for TLB latency | |
3470 | * | |
3471 | * The normal calculation is: | |
3472 | * watermark = dotclock * bytes per pixel * latency | |
3473 | * where latency is platform & configuration dependent (we assume pessimal | |
3474 | * values here). | |
3475 | * | |
3476 | * The SR calculation is: | |
3477 | * watermark = (trunc(latency/line time)+1) * surface width * | |
3478 | * bytes per pixel | |
3479 | * where | |
3480 | * line time = htotal / dotclock | |
fa143215 | 3481 | * surface width = hdisplay for normal plane and 64 for cursor |
7662c8bd SL |
3482 | * and latency is assumed to be high, as above. |
3483 | * | |
3484 | * The final value programmed to the register should always be rounded up, | |
3485 | * and include an extra 2 entries to account for clock crossings. | |
3486 | * | |
3487 | * We don't use the sprite, so we can ignore that. And on Crestline we have | |
3488 | * to set the non-SR watermarks to 8. | |
3489 | */ | |
3490 | static void intel_update_watermarks(struct drm_device *dev) | |
3491 | { | |
e70236a8 | 3492 | struct drm_i915_private *dev_priv = dev->dev_private; |
7662c8bd | 3493 | struct drm_crtc *crtc; |
7662c8bd SL |
3494 | int sr_hdisplay = 0; |
3495 | unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0; | |
3496 | int enabled = 0, pixel_size = 0; | |
fa143215 | 3497 | int sr_htotal = 0; |
7662c8bd | 3498 | |
c03342fa ZW |
3499 | if (!dev_priv->display.update_wm) |
3500 | return; | |
3501 | ||
7662c8bd SL |
3502 | /* Get the clock config from both planes */ |
3503 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
debcaddc CW |
3504 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3505 | if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) { | |
7662c8bd SL |
3506 | enabled++; |
3507 | if (intel_crtc->plane == 0) { | |
28c97730 | 3508 | DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n", |
7662c8bd SL |
3509 | intel_crtc->pipe, crtc->mode.clock); |
3510 | planea_clock = crtc->mode.clock; | |
3511 | } else { | |
28c97730 | 3512 | DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n", |
7662c8bd SL |
3513 | intel_crtc->pipe, crtc->mode.clock); |
3514 | planeb_clock = crtc->mode.clock; | |
3515 | } | |
3516 | sr_hdisplay = crtc->mode.hdisplay; | |
3517 | sr_clock = crtc->mode.clock; | |
fa143215 | 3518 | sr_htotal = crtc->mode.htotal; |
7662c8bd SL |
3519 | if (crtc->fb) |
3520 | pixel_size = crtc->fb->bits_per_pixel / 8; | |
3521 | else | |
3522 | pixel_size = 4; /* by default */ | |
3523 | } | |
3524 | } | |
3525 | ||
3526 | if (enabled <= 0) | |
3527 | return; | |
3528 | ||
e70236a8 | 3529 | dev_priv->display.update_wm(dev, planea_clock, planeb_clock, |
fa143215 | 3530 | sr_hdisplay, sr_htotal, pixel_size); |
7662c8bd SL |
3531 | } |
3532 | ||
5c3b82e2 CW |
3533 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
3534 | struct drm_display_mode *mode, | |
3535 | struct drm_display_mode *adjusted_mode, | |
3536 | int x, int y, | |
3537 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
3538 | { |
3539 | struct drm_device *dev = crtc->dev; | |
3540 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3541 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3542 | int pipe = intel_crtc->pipe; | |
80824003 | 3543 | int plane = intel_crtc->plane; |
79e53945 JB |
3544 | int fp_reg = (pipe == 0) ? FPA0 : FPB0; |
3545 | int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; | |
3546 | int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD; | |
80824003 | 3547 | int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR; |
79e53945 JB |
3548 | int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; |
3549 | int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B; | |
3550 | int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B; | |
3551 | int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B; | |
3552 | int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B; | |
3553 | int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B; | |
3554 | int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B; | |
80824003 JB |
3555 | int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE; |
3556 | int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS; | |
79e53945 | 3557 | int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC; |
c751ce4f | 3558 | int refclk, num_connectors = 0; |
652c393a JB |
3559 | intel_clock_t clock, reduced_clock; |
3560 | u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf; | |
3561 | bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false; | |
a4fc5ed6 | 3562 | bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; |
8e647a27 | 3563 | struct intel_encoder *has_edp_encoder = NULL; |
79e53945 | 3564 | struct drm_mode_config *mode_config = &dev->mode_config; |
c5e4df33 | 3565 | struct drm_encoder *encoder; |
d4906093 | 3566 | const intel_limit_t *limit; |
5c3b82e2 | 3567 | int ret; |
2c07245f ZW |
3568 | struct fdi_m_n m_n = {0}; |
3569 | int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1; | |
3570 | int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1; | |
3571 | int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1; | |
3572 | int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1; | |
3573 | int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0; | |
3574 | int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B; | |
3575 | int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL; | |
8db9d77b ZW |
3576 | int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL; |
3577 | int trans_dpll_sel = (pipe == 0) ? 0 : 1; | |
541998a1 | 3578 | int lvds_reg = LVDS; |
2c07245f | 3579 | u32 temp; |
5eb08b69 | 3580 | int target_clock; |
79e53945 JB |
3581 | |
3582 | drm_vblank_pre_modeset(dev, pipe); | |
3583 | ||
c5e4df33 | 3584 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { |
8e647a27 | 3585 | struct intel_encoder *intel_encoder; |
79e53945 | 3586 | |
8e647a27 | 3587 | if (encoder->crtc != crtc) |
79e53945 JB |
3588 | continue; |
3589 | ||
4ef69c7a | 3590 | intel_encoder = to_intel_encoder(encoder); |
21d40d37 | 3591 | switch (intel_encoder->type) { |
79e53945 JB |
3592 | case INTEL_OUTPUT_LVDS: |
3593 | is_lvds = true; | |
3594 | break; | |
3595 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 3596 | case INTEL_OUTPUT_HDMI: |
79e53945 | 3597 | is_sdvo = true; |
21d40d37 | 3598 | if (intel_encoder->needs_tv_clock) |
e2f0ba97 | 3599 | is_tv = true; |
79e53945 JB |
3600 | break; |
3601 | case INTEL_OUTPUT_DVO: | |
3602 | is_dvo = true; | |
3603 | break; | |
3604 | case INTEL_OUTPUT_TVOUT: | |
3605 | is_tv = true; | |
3606 | break; | |
3607 | case INTEL_OUTPUT_ANALOG: | |
3608 | is_crt = true; | |
3609 | break; | |
a4fc5ed6 KP |
3610 | case INTEL_OUTPUT_DISPLAYPORT: |
3611 | is_dp = true; | |
3612 | break; | |
32f9d658 | 3613 | case INTEL_OUTPUT_EDP: |
8e647a27 | 3614 | has_edp_encoder = intel_encoder; |
32f9d658 | 3615 | break; |
79e53945 | 3616 | } |
43565a06 | 3617 | |
c751ce4f | 3618 | num_connectors++; |
79e53945 JB |
3619 | } |
3620 | ||
c751ce4f | 3621 | if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) { |
43565a06 | 3622 | refclk = dev_priv->lvds_ssc_freq * 1000; |
28c97730 ZY |
3623 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", |
3624 | refclk / 1000); | |
43565a06 | 3625 | } else if (IS_I9XX(dev)) { |
79e53945 | 3626 | refclk = 96000; |
bad720ff | 3627 | if (HAS_PCH_SPLIT(dev)) |
2c07245f | 3628 | refclk = 120000; /* 120Mhz refclk */ |
79e53945 JB |
3629 | } else { |
3630 | refclk = 48000; | |
3631 | } | |
a4fc5ed6 | 3632 | |
79e53945 | 3633 | |
d4906093 ML |
3634 | /* |
3635 | * Returns a set of divisors for the desired target clock with the given | |
3636 | * refclk, or FALSE. The returned values represent the clock equation: | |
3637 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
3638 | */ | |
3639 | limit = intel_limit(crtc); | |
3640 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock); | |
79e53945 JB |
3641 | if (!ok) { |
3642 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
1f803ee5 | 3643 | drm_vblank_post_modeset(dev, pipe); |
5c3b82e2 | 3644 | return -EINVAL; |
79e53945 JB |
3645 | } |
3646 | ||
cda4b7d3 CW |
3647 | /* Ensure that the cursor is valid for the new mode before changing... */ |
3648 | intel_crtc_update_cursor(crtc); | |
3649 | ||
ddc9003c ZY |
3650 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
3651 | has_reduced_clock = limit->find_pll(limit, crtc, | |
18f9ed12 | 3652 | dev_priv->lvds_downclock, |
652c393a JB |
3653 | refclk, |
3654 | &reduced_clock); | |
18f9ed12 ZY |
3655 | if (has_reduced_clock && (clock.p != reduced_clock.p)) { |
3656 | /* | |
3657 | * If the different P is found, it means that we can't | |
3658 | * switch the display clock by using the FP0/FP1. | |
3659 | * In such case we will disable the LVDS downclock | |
3660 | * feature. | |
3661 | */ | |
3662 | DRM_DEBUG_KMS("Different P is found for " | |
3663 | "LVDS clock/downclock\n"); | |
3664 | has_reduced_clock = 0; | |
3665 | } | |
652c393a | 3666 | } |
7026d4ac ZW |
3667 | /* SDVO TV has fixed PLL values depend on its clock range, |
3668 | this mirrors vbios setting. */ | |
3669 | if (is_sdvo && is_tv) { | |
3670 | if (adjusted_mode->clock >= 100000 | |
3671 | && adjusted_mode->clock < 140500) { | |
3672 | clock.p1 = 2; | |
3673 | clock.p2 = 10; | |
3674 | clock.n = 3; | |
3675 | clock.m1 = 16; | |
3676 | clock.m2 = 8; | |
3677 | } else if (adjusted_mode->clock >= 140500 | |
3678 | && adjusted_mode->clock <= 200000) { | |
3679 | clock.p1 = 1; | |
3680 | clock.p2 = 10; | |
3681 | clock.n = 6; | |
3682 | clock.m1 = 12; | |
3683 | clock.m2 = 8; | |
3684 | } | |
3685 | } | |
3686 | ||
2c07245f | 3687 | /* FDI link */ |
bad720ff | 3688 | if (HAS_PCH_SPLIT(dev)) { |
77ffb597 | 3689 | int lane = 0, link_bw, bpp; |
32f9d658 ZW |
3690 | /* eDP doesn't require FDI link, so just set DP M/N |
3691 | according to current link config */ | |
8e647a27 | 3692 | if (has_edp_encoder) { |
5eb08b69 | 3693 | target_clock = mode->clock; |
8e647a27 CW |
3694 | intel_edp_link_config(has_edp_encoder, |
3695 | &lane, &link_bw); | |
32f9d658 ZW |
3696 | } else { |
3697 | /* DP over FDI requires target mode clock | |
3698 | instead of link clock */ | |
3699 | if (is_dp) | |
3700 | target_clock = mode->clock; | |
3701 | else | |
3702 | target_clock = adjusted_mode->clock; | |
32f9d658 ZW |
3703 | link_bw = 270000; |
3704 | } | |
58a27471 ZW |
3705 | |
3706 | /* determine panel color depth */ | |
3707 | temp = I915_READ(pipeconf_reg); | |
e5a95eb7 ZY |
3708 | temp &= ~PIPE_BPC_MASK; |
3709 | if (is_lvds) { | |
3710 | int lvds_reg = I915_READ(PCH_LVDS); | |
3711 | /* the BPC will be 6 if it is 18-bit LVDS panel */ | |
3712 | if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP) | |
3713 | temp |= PIPE_8BPC; | |
3714 | else | |
3715 | temp |= PIPE_6BPC; | |
8e647a27 | 3716 | } else if (has_edp_encoder || (is_dp && intel_pch_has_edp(crtc))) { |
885a5fb5 ZW |
3717 | switch (dev_priv->edp_bpp/3) { |
3718 | case 8: | |
3719 | temp |= PIPE_8BPC; | |
3720 | break; | |
3721 | case 10: | |
3722 | temp |= PIPE_10BPC; | |
3723 | break; | |
3724 | case 6: | |
3725 | temp |= PIPE_6BPC; | |
3726 | break; | |
3727 | case 12: | |
3728 | temp |= PIPE_12BPC; | |
3729 | break; | |
3730 | } | |
e5a95eb7 ZY |
3731 | } else |
3732 | temp |= PIPE_8BPC; | |
3733 | I915_WRITE(pipeconf_reg, temp); | |
3734 | I915_READ(pipeconf_reg); | |
58a27471 ZW |
3735 | |
3736 | switch (temp & PIPE_BPC_MASK) { | |
3737 | case PIPE_8BPC: | |
3738 | bpp = 24; | |
3739 | break; | |
3740 | case PIPE_10BPC: | |
3741 | bpp = 30; | |
3742 | break; | |
3743 | case PIPE_6BPC: | |
3744 | bpp = 18; | |
3745 | break; | |
3746 | case PIPE_12BPC: | |
3747 | bpp = 36; | |
3748 | break; | |
3749 | default: | |
3750 | DRM_ERROR("unknown pipe bpc value\n"); | |
3751 | bpp = 24; | |
3752 | } | |
3753 | ||
77ffb597 AJ |
3754 | if (!lane) { |
3755 | /* | |
3756 | * Account for spread spectrum to avoid | |
3757 | * oversubscribing the link. Max center spread | |
3758 | * is 2.5%; use 5% for safety's sake. | |
3759 | */ | |
3760 | u32 bps = target_clock * bpp * 21 / 20; | |
3761 | lane = bps / (link_bw * 8) + 1; | |
3762 | } | |
3763 | ||
3764 | intel_crtc->fdi_lanes = lane; | |
3765 | ||
f2b115e6 | 3766 | ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n); |
5eb08b69 | 3767 | } |
2c07245f | 3768 | |
c038e51e ZW |
3769 | /* Ironlake: try to setup display ref clock before DPLL |
3770 | * enabling. This is only under driver's control after | |
3771 | * PCH B stepping, previous chipset stepping should be | |
3772 | * ignoring this setting. | |
3773 | */ | |
bad720ff | 3774 | if (HAS_PCH_SPLIT(dev)) { |
c038e51e ZW |
3775 | temp = I915_READ(PCH_DREF_CONTROL); |
3776 | /* Always enable nonspread source */ | |
3777 | temp &= ~DREF_NONSPREAD_SOURCE_MASK; | |
3778 | temp |= DREF_NONSPREAD_SOURCE_ENABLE; | |
3779 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
3780 | POSTING_READ(PCH_DREF_CONTROL); | |
3781 | ||
3782 | temp &= ~DREF_SSC_SOURCE_MASK; | |
3783 | temp |= DREF_SSC_SOURCE_ENABLE; | |
3784 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
3785 | POSTING_READ(PCH_DREF_CONTROL); | |
3786 | ||
3787 | udelay(200); | |
3788 | ||
8e647a27 | 3789 | if (has_edp_encoder) { |
c038e51e ZW |
3790 | if (dev_priv->lvds_use_ssc) { |
3791 | temp |= DREF_SSC1_ENABLE; | |
3792 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
3793 | POSTING_READ(PCH_DREF_CONTROL); | |
3794 | ||
3795 | udelay(200); | |
3796 | ||
3797 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
3798 | temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
3799 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
3800 | POSTING_READ(PCH_DREF_CONTROL); | |
3801 | } else { | |
3802 | temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
3803 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
3804 | POSTING_READ(PCH_DREF_CONTROL); | |
3805 | } | |
3806 | } | |
3807 | } | |
3808 | ||
f2b115e6 | 3809 | if (IS_PINEVIEW(dev)) { |
2177832f | 3810 | fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2; |
652c393a JB |
3811 | if (has_reduced_clock) |
3812 | fp2 = (1 << reduced_clock.n) << 16 | | |
3813 | reduced_clock.m1 << 8 | reduced_clock.m2; | |
3814 | } else { | |
2177832f | 3815 | fp = clock.n << 16 | clock.m1 << 8 | clock.m2; |
652c393a JB |
3816 | if (has_reduced_clock) |
3817 | fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 | | |
3818 | reduced_clock.m2; | |
3819 | } | |
79e53945 | 3820 | |
bad720ff | 3821 | if (!HAS_PCH_SPLIT(dev)) |
2c07245f ZW |
3822 | dpll = DPLL_VGA_MODE_DIS; |
3823 | ||
79e53945 JB |
3824 | if (IS_I9XX(dev)) { |
3825 | if (is_lvds) | |
3826 | dpll |= DPLLB_MODE_LVDS; | |
3827 | else | |
3828 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
3829 | if (is_sdvo) { | |
6c9547ff CW |
3830 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
3831 | if (pixel_multiplier > 1) { | |
3832 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
3833 | dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; | |
3834 | else if (HAS_PCH_SPLIT(dev)) | |
3835 | dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
3836 | } | |
79e53945 | 3837 | dpll |= DPLL_DVO_HIGH_SPEED; |
79e53945 | 3838 | } |
a4fc5ed6 KP |
3839 | if (is_dp) |
3840 | dpll |= DPLL_DVO_HIGH_SPEED; | |
79e53945 JB |
3841 | |
3842 | /* compute bitmask from p1 value */ | |
f2b115e6 AJ |
3843 | if (IS_PINEVIEW(dev)) |
3844 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
2c07245f | 3845 | else { |
2177832f | 3846 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
2c07245f | 3847 | /* also FPA1 */ |
bad720ff | 3848 | if (HAS_PCH_SPLIT(dev)) |
2c07245f | 3849 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
652c393a JB |
3850 | if (IS_G4X(dev) && has_reduced_clock) |
3851 | dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
2c07245f | 3852 | } |
79e53945 JB |
3853 | switch (clock.p2) { |
3854 | case 5: | |
3855 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
3856 | break; | |
3857 | case 7: | |
3858 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
3859 | break; | |
3860 | case 10: | |
3861 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
3862 | break; | |
3863 | case 14: | |
3864 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
3865 | break; | |
3866 | } | |
bad720ff | 3867 | if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) |
79e53945 JB |
3868 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
3869 | } else { | |
3870 | if (is_lvds) { | |
3871 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
3872 | } else { | |
3873 | if (clock.p1 == 2) | |
3874 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
3875 | else | |
3876 | dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
3877 | if (clock.p2 == 4) | |
3878 | dpll |= PLL_P2_DIVIDE_BY_4; | |
3879 | } | |
3880 | } | |
3881 | ||
43565a06 KH |
3882 | if (is_sdvo && is_tv) |
3883 | dpll |= PLL_REF_INPUT_TVCLKINBC; | |
3884 | else if (is_tv) | |
79e53945 | 3885 | /* XXX: just matching BIOS for now */ |
43565a06 | 3886 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
79e53945 | 3887 | dpll |= 3; |
c751ce4f | 3888 | else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) |
43565a06 | 3889 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
3890 | else |
3891 | dpll |= PLL_REF_INPUT_DREFCLK; | |
3892 | ||
3893 | /* setup pipeconf */ | |
3894 | pipeconf = I915_READ(pipeconf_reg); | |
3895 | ||
3896 | /* Set up the display plane register */ | |
3897 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
3898 | ||
f2b115e6 | 3899 | /* Ironlake's plane is forced to pipe, bit 24 is to |
2c07245f | 3900 | enable color space conversion */ |
bad720ff | 3901 | if (!HAS_PCH_SPLIT(dev)) { |
2c07245f | 3902 | if (pipe == 0) |
80824003 | 3903 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; |
2c07245f ZW |
3904 | else |
3905 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
3906 | } | |
79e53945 JB |
3907 | |
3908 | if (pipe == 0 && !IS_I965G(dev)) { | |
3909 | /* Enable pixel doubling when the dot clock is > 90% of the (display) | |
3910 | * core speed. | |
3911 | * | |
3912 | * XXX: No double-wide on 915GM pipe B. Is that the only reason for the | |
3913 | * pipe == 0 check? | |
3914 | */ | |
e70236a8 JB |
3915 | if (mode->clock > |
3916 | dev_priv->display.get_display_clock_speed(dev) * 9 / 10) | |
79e53945 JB |
3917 | pipeconf |= PIPEACONF_DOUBLE_WIDE; |
3918 | else | |
3919 | pipeconf &= ~PIPEACONF_DOUBLE_WIDE; | |
3920 | } | |
3921 | ||
8d86dc6a LT |
3922 | dspcntr |= DISPLAY_PLANE_ENABLE; |
3923 | pipeconf |= PIPEACONF_ENABLE; | |
3924 | dpll |= DPLL_VCO_ENABLE; | |
3925 | ||
3926 | ||
79e53945 | 3927 | /* Disable the panel fitter if it was on our pipe */ |
bad720ff | 3928 | if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe) |
79e53945 JB |
3929 | I915_WRITE(PFIT_CONTROL, 0); |
3930 | ||
28c97730 | 3931 | DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); |
79e53945 JB |
3932 | drm_mode_debug_printmodeline(mode); |
3933 | ||
f2b115e6 | 3934 | /* assign to Ironlake registers */ |
bad720ff | 3935 | if (HAS_PCH_SPLIT(dev)) { |
2c07245f ZW |
3936 | fp_reg = pch_fp_reg; |
3937 | dpll_reg = pch_dpll_reg; | |
3938 | } | |
79e53945 | 3939 | |
8e647a27 | 3940 | if (!has_edp_encoder) { |
79e53945 JB |
3941 | I915_WRITE(fp_reg, fp); |
3942 | I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE); | |
3943 | I915_READ(dpll_reg); | |
3944 | udelay(150); | |
3945 | } | |
3946 | ||
8db9d77b ZW |
3947 | /* enable transcoder DPLL */ |
3948 | if (HAS_PCH_CPT(dev)) { | |
3949 | temp = I915_READ(PCH_DPLL_SEL); | |
3950 | if (trans_dpll_sel == 0) | |
3951 | temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL); | |
3952 | else | |
3953 | temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); | |
3954 | I915_WRITE(PCH_DPLL_SEL, temp); | |
3955 | I915_READ(PCH_DPLL_SEL); | |
3956 | udelay(150); | |
3957 | } | |
3958 | ||
79e53945 JB |
3959 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. |
3960 | * This is an exception to the general rule that mode_set doesn't turn | |
3961 | * things on. | |
3962 | */ | |
3963 | if (is_lvds) { | |
541998a1 | 3964 | u32 lvds; |
79e53945 | 3965 | |
bad720ff | 3966 | if (HAS_PCH_SPLIT(dev)) |
541998a1 ZW |
3967 | lvds_reg = PCH_LVDS; |
3968 | ||
3969 | lvds = I915_READ(lvds_reg); | |
0f3ee801 | 3970 | lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; |
b3b095b3 ZW |
3971 | if (pipe == 1) { |
3972 | if (HAS_PCH_CPT(dev)) | |
3973 | lvds |= PORT_TRANS_B_SEL_CPT; | |
3974 | else | |
3975 | lvds |= LVDS_PIPEB_SELECT; | |
3976 | } else { | |
3977 | if (HAS_PCH_CPT(dev)) | |
3978 | lvds &= ~PORT_TRANS_SEL_MASK; | |
3979 | else | |
3980 | lvds &= ~LVDS_PIPEB_SELECT; | |
3981 | } | |
a3e17eb8 ZY |
3982 | /* set the corresponsding LVDS_BORDER bit */ |
3983 | lvds |= dev_priv->lvds_border_bits; | |
79e53945 JB |
3984 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
3985 | * set the DPLLs for dual-channel mode or not. | |
3986 | */ | |
3987 | if (clock.p2 == 7) | |
3988 | lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; | |
3989 | else | |
3990 | lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); | |
3991 | ||
3992 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
3993 | * appropriately here, but we need to look more thoroughly into how | |
3994 | * panels behave in the two modes. | |
3995 | */ | |
434ed097 JB |
3996 | /* set the dithering flag on non-PCH LVDS as needed */ |
3997 | if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) { | |
3998 | if (dev_priv->lvds_dither) | |
3999 | lvds |= LVDS_ENABLE_DITHER; | |
4000 | else | |
4001 | lvds &= ~LVDS_ENABLE_DITHER; | |
898822ce | 4002 | } |
541998a1 ZW |
4003 | I915_WRITE(lvds_reg, lvds); |
4004 | I915_READ(lvds_reg); | |
79e53945 | 4005 | } |
434ed097 JB |
4006 | |
4007 | /* set the dithering flag and clear for anything other than a panel. */ | |
4008 | if (HAS_PCH_SPLIT(dev)) { | |
4009 | pipeconf &= ~PIPECONF_DITHER_EN; | |
4010 | pipeconf &= ~PIPECONF_DITHER_TYPE_MASK; | |
4011 | if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) { | |
4012 | pipeconf |= PIPECONF_DITHER_EN; | |
4013 | pipeconf |= PIPECONF_DITHER_TYPE_ST1; | |
4014 | } | |
4015 | } | |
4016 | ||
a4fc5ed6 KP |
4017 | if (is_dp) |
4018 | intel_dp_set_m_n(crtc, mode, adjusted_mode); | |
8db9d77b ZW |
4019 | else if (HAS_PCH_SPLIT(dev)) { |
4020 | /* For non-DP output, clear any trans DP clock recovery setting.*/ | |
4021 | if (pipe == 0) { | |
4022 | I915_WRITE(TRANSA_DATA_M1, 0); | |
4023 | I915_WRITE(TRANSA_DATA_N1, 0); | |
4024 | I915_WRITE(TRANSA_DP_LINK_M1, 0); | |
4025 | I915_WRITE(TRANSA_DP_LINK_N1, 0); | |
4026 | } else { | |
4027 | I915_WRITE(TRANSB_DATA_M1, 0); | |
4028 | I915_WRITE(TRANSB_DATA_N1, 0); | |
4029 | I915_WRITE(TRANSB_DP_LINK_M1, 0); | |
4030 | I915_WRITE(TRANSB_DP_LINK_N1, 0); | |
4031 | } | |
4032 | } | |
79e53945 | 4033 | |
8e647a27 | 4034 | if (!has_edp_encoder) { |
32f9d658 | 4035 | I915_WRITE(fp_reg, fp); |
79e53945 | 4036 | I915_WRITE(dpll_reg, dpll); |
32f9d658 ZW |
4037 | I915_READ(dpll_reg); |
4038 | /* Wait for the clocks to stabilize. */ | |
4039 | udelay(150); | |
4040 | ||
bad720ff | 4041 | if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) { |
bb66c512 | 4042 | if (is_sdvo) { |
6c9547ff CW |
4043 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
4044 | if (pixel_multiplier > 1) | |
4045 | pixel_multiplier = (pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
4046 | else | |
4047 | pixel_multiplier = 0; | |
4048 | ||
4049 | I915_WRITE(dpll_md_reg, | |
4050 | (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | | |
4051 | pixel_multiplier); | |
bb66c512 ZY |
4052 | } else |
4053 | I915_WRITE(dpll_md_reg, 0); | |
32f9d658 ZW |
4054 | } else { |
4055 | /* write it again -- the BIOS does, after all */ | |
4056 | I915_WRITE(dpll_reg, dpll); | |
4057 | } | |
4058 | I915_READ(dpll_reg); | |
4059 | /* Wait for the clocks to stabilize. */ | |
4060 | udelay(150); | |
79e53945 | 4061 | } |
79e53945 | 4062 | |
652c393a JB |
4063 | if (is_lvds && has_reduced_clock && i915_powersave) { |
4064 | I915_WRITE(fp_reg + 4, fp2); | |
4065 | intel_crtc->lowfreq_avail = true; | |
4066 | if (HAS_PIPE_CXSR(dev)) { | |
28c97730 | 4067 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); |
652c393a JB |
4068 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; |
4069 | } | |
4070 | } else { | |
4071 | I915_WRITE(fp_reg + 4, fp); | |
4072 | intel_crtc->lowfreq_avail = false; | |
4073 | if (HAS_PIPE_CXSR(dev)) { | |
28c97730 | 4074 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
652c393a JB |
4075 | pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; |
4076 | } | |
4077 | } | |
4078 | ||
734b4157 KH |
4079 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
4080 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; | |
4081 | /* the chip adds 2 halflines automatically */ | |
4082 | adjusted_mode->crtc_vdisplay -= 1; | |
4083 | adjusted_mode->crtc_vtotal -= 1; | |
4084 | adjusted_mode->crtc_vblank_start -= 1; | |
4085 | adjusted_mode->crtc_vblank_end -= 1; | |
4086 | adjusted_mode->crtc_vsync_end -= 1; | |
4087 | adjusted_mode->crtc_vsync_start -= 1; | |
4088 | } else | |
4089 | pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */ | |
4090 | ||
79e53945 JB |
4091 | I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) | |
4092 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
4093 | I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) | | |
4094 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
4095 | I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) | | |
4096 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
4097 | I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) | | |
4098 | ((adjusted_mode->crtc_vtotal - 1) << 16)); | |
4099 | I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) | | |
4100 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); | |
4101 | I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) | | |
4102 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
4103 | /* pipesrc and dspsize control the size that is scaled from, which should | |
4104 | * always be the user's requested size. | |
4105 | */ | |
bad720ff | 4106 | if (!HAS_PCH_SPLIT(dev)) { |
2c07245f ZW |
4107 | I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) | |
4108 | (mode->hdisplay - 1)); | |
4109 | I915_WRITE(dsppos_reg, 0); | |
4110 | } | |
79e53945 | 4111 | I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); |
2c07245f | 4112 | |
bad720ff | 4113 | if (HAS_PCH_SPLIT(dev)) { |
2c07245f ZW |
4114 | I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m); |
4115 | I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n); | |
4116 | I915_WRITE(link_m1_reg, m_n.link_m); | |
4117 | I915_WRITE(link_n1_reg, m_n.link_n); | |
4118 | ||
8e647a27 | 4119 | if (has_edp_encoder) { |
f2b115e6 | 4120 | ironlake_set_pll_edp(crtc, adjusted_mode->clock); |
32f9d658 ZW |
4121 | } else { |
4122 | /* enable FDI RX PLL too */ | |
4123 | temp = I915_READ(fdi_rx_reg); | |
4124 | I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE); | |
8db9d77b ZW |
4125 | I915_READ(fdi_rx_reg); |
4126 | udelay(200); | |
4127 | ||
4128 | /* enable FDI TX PLL too */ | |
4129 | temp = I915_READ(fdi_tx_reg); | |
4130 | I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE); | |
4131 | I915_READ(fdi_tx_reg); | |
4132 | ||
4133 | /* enable FDI RX PCDCLK */ | |
4134 | temp = I915_READ(fdi_rx_reg); | |
4135 | I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK); | |
4136 | I915_READ(fdi_rx_reg); | |
32f9d658 ZW |
4137 | udelay(200); |
4138 | } | |
2c07245f ZW |
4139 | } |
4140 | ||
79e53945 JB |
4141 | I915_WRITE(pipeconf_reg, pipeconf); |
4142 | I915_READ(pipeconf_reg); | |
4143 | ||
9d0498a2 | 4144 | intel_wait_for_vblank(dev, pipe); |
79e53945 | 4145 | |
c2416fc6 | 4146 | if (IS_IRONLAKE(dev)) { |
553bd149 ZW |
4147 | /* enable address swizzle for tiling buffer */ |
4148 | temp = I915_READ(DISP_ARB_CTL); | |
4149 | I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING); | |
4150 | } | |
4151 | ||
79e53945 JB |
4152 | I915_WRITE(dspcntr_reg, dspcntr); |
4153 | ||
4154 | /* Flush the plane changes */ | |
5c3b82e2 | 4155 | ret = intel_pipe_set_base(crtc, x, y, old_fb); |
7662c8bd SL |
4156 | |
4157 | intel_update_watermarks(dev); | |
4158 | ||
79e53945 | 4159 | drm_vblank_post_modeset(dev, pipe); |
5c3b82e2 | 4160 | |
1f803ee5 | 4161 | return ret; |
79e53945 JB |
4162 | } |
4163 | ||
4164 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
4165 | void intel_crtc_load_lut(struct drm_crtc *crtc) | |
4166 | { | |
4167 | struct drm_device *dev = crtc->dev; | |
4168 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4169 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4170 | int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B; | |
4171 | int i; | |
4172 | ||
4173 | /* The clocks have to be on to load the palette. */ | |
4174 | if (!crtc->enabled) | |
4175 | return; | |
4176 | ||
f2b115e6 | 4177 | /* use legacy palette for Ironlake */ |
bad720ff | 4178 | if (HAS_PCH_SPLIT(dev)) |
2c07245f ZW |
4179 | palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A : |
4180 | LGC_PALETTE_B; | |
4181 | ||
79e53945 JB |
4182 | for (i = 0; i < 256; i++) { |
4183 | I915_WRITE(palreg + 4 * i, | |
4184 | (intel_crtc->lut_r[i] << 16) | | |
4185 | (intel_crtc->lut_g[i] << 8) | | |
4186 | intel_crtc->lut_b[i]); | |
4187 | } | |
4188 | } | |
4189 | ||
560b85bb CW |
4190 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
4191 | { | |
4192 | struct drm_device *dev = crtc->dev; | |
4193 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4194 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4195 | bool visible = base != 0; | |
4196 | u32 cntl; | |
4197 | ||
4198 | if (intel_crtc->cursor_visible == visible) | |
4199 | return; | |
4200 | ||
4201 | cntl = I915_READ(CURACNTR); | |
4202 | if (visible) { | |
4203 | /* On these chipsets we can only modify the base whilst | |
4204 | * the cursor is disabled. | |
4205 | */ | |
4206 | I915_WRITE(CURABASE, base); | |
4207 | ||
4208 | cntl &= ~(CURSOR_FORMAT_MASK); | |
4209 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ | |
4210 | cntl |= CURSOR_ENABLE | | |
4211 | CURSOR_GAMMA_ENABLE | | |
4212 | CURSOR_FORMAT_ARGB; | |
4213 | } else | |
4214 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); | |
4215 | I915_WRITE(CURACNTR, cntl); | |
4216 | ||
4217 | intel_crtc->cursor_visible = visible; | |
4218 | } | |
4219 | ||
4220 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) | |
4221 | { | |
4222 | struct drm_device *dev = crtc->dev; | |
4223 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4224 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4225 | int pipe = intel_crtc->pipe; | |
4226 | bool visible = base != 0; | |
4227 | ||
4228 | if (intel_crtc->cursor_visible != visible) { | |
4229 | uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR); | |
4230 | if (base) { | |
4231 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); | |
4232 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
4233 | cntl |= pipe << 28; /* Connect to correct pipe */ | |
4234 | } else { | |
4235 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
4236 | cntl |= CURSOR_MODE_DISABLE; | |
4237 | } | |
4238 | I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl); | |
4239 | ||
4240 | intel_crtc->cursor_visible = visible; | |
4241 | } | |
4242 | /* and commit changes on next vblank */ | |
4243 | I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base); | |
4244 | } | |
4245 | ||
cda4b7d3 CW |
4246 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
4247 | static void intel_crtc_update_cursor(struct drm_crtc *crtc) | |
4248 | { | |
4249 | struct drm_device *dev = crtc->dev; | |
4250 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4251 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4252 | int pipe = intel_crtc->pipe; | |
4253 | int x = intel_crtc->cursor_x; | |
4254 | int y = intel_crtc->cursor_y; | |
560b85bb | 4255 | u32 base, pos; |
cda4b7d3 CW |
4256 | bool visible; |
4257 | ||
4258 | pos = 0; | |
4259 | ||
87f8ebf3 | 4260 | if (intel_crtc->cursor_on && crtc->fb) { |
cda4b7d3 CW |
4261 | base = intel_crtc->cursor_addr; |
4262 | if (x > (int) crtc->fb->width) | |
4263 | base = 0; | |
4264 | ||
4265 | if (y > (int) crtc->fb->height) | |
4266 | base = 0; | |
4267 | } else | |
4268 | base = 0; | |
4269 | ||
4270 | if (x < 0) { | |
4271 | if (x + intel_crtc->cursor_width < 0) | |
4272 | base = 0; | |
4273 | ||
4274 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
4275 | x = -x; | |
4276 | } | |
4277 | pos |= x << CURSOR_X_SHIFT; | |
4278 | ||
4279 | if (y < 0) { | |
4280 | if (y + intel_crtc->cursor_height < 0) | |
4281 | base = 0; | |
4282 | ||
4283 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
4284 | y = -y; | |
4285 | } | |
4286 | pos |= y << CURSOR_Y_SHIFT; | |
4287 | ||
4288 | visible = base != 0; | |
560b85bb | 4289 | if (!visible && !intel_crtc->cursor_visible) |
cda4b7d3 CW |
4290 | return; |
4291 | ||
4292 | I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos); | |
560b85bb CW |
4293 | if (IS_845G(dev) || IS_I865G(dev)) |
4294 | i845_update_cursor(crtc, base); | |
4295 | else | |
4296 | i9xx_update_cursor(crtc, base); | |
cda4b7d3 CW |
4297 | |
4298 | if (visible) | |
4299 | intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj); | |
4300 | } | |
4301 | ||
79e53945 JB |
4302 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
4303 | struct drm_file *file_priv, | |
4304 | uint32_t handle, | |
4305 | uint32_t width, uint32_t height) | |
4306 | { | |
4307 | struct drm_device *dev = crtc->dev; | |
4308 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4309 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4310 | struct drm_gem_object *bo; | |
4311 | struct drm_i915_gem_object *obj_priv; | |
cda4b7d3 | 4312 | uint32_t addr; |
3f8bc370 | 4313 | int ret; |
79e53945 | 4314 | |
28c97730 | 4315 | DRM_DEBUG_KMS("\n"); |
79e53945 JB |
4316 | |
4317 | /* if we want to turn off the cursor ignore width and height */ | |
4318 | if (!handle) { | |
28c97730 | 4319 | DRM_DEBUG_KMS("cursor off\n"); |
3f8bc370 KH |
4320 | addr = 0; |
4321 | bo = NULL; | |
5004417d | 4322 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 4323 | goto finish; |
79e53945 JB |
4324 | } |
4325 | ||
4326 | /* Currently we only support 64x64 cursors */ | |
4327 | if (width != 64 || height != 64) { | |
4328 | DRM_ERROR("we currently only support 64x64 cursors\n"); | |
4329 | return -EINVAL; | |
4330 | } | |
4331 | ||
4332 | bo = drm_gem_object_lookup(dev, file_priv, handle); | |
4333 | if (!bo) | |
4334 | return -ENOENT; | |
4335 | ||
23010e43 | 4336 | obj_priv = to_intel_bo(bo); |
79e53945 JB |
4337 | |
4338 | if (bo->size < width * height * 4) { | |
4339 | DRM_ERROR("buffer is to small\n"); | |
34b8686e DA |
4340 | ret = -ENOMEM; |
4341 | goto fail; | |
79e53945 JB |
4342 | } |
4343 | ||
71acb5eb | 4344 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 4345 | mutex_lock(&dev->struct_mutex); |
b295d1b6 | 4346 | if (!dev_priv->info->cursor_needs_physical) { |
71acb5eb DA |
4347 | ret = i915_gem_object_pin(bo, PAGE_SIZE); |
4348 | if (ret) { | |
4349 | DRM_ERROR("failed to pin cursor bo\n"); | |
7f9872e0 | 4350 | goto fail_locked; |
71acb5eb | 4351 | } |
e7b526bb CW |
4352 | |
4353 | ret = i915_gem_object_set_to_gtt_domain(bo, 0); | |
4354 | if (ret) { | |
4355 | DRM_ERROR("failed to move cursor bo into the GTT\n"); | |
4356 | goto fail_unpin; | |
4357 | } | |
4358 | ||
79e53945 | 4359 | addr = obj_priv->gtt_offset; |
71acb5eb | 4360 | } else { |
6eeefaf3 | 4361 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
cda4b7d3 | 4362 | ret = i915_gem_attach_phys_object(dev, bo, |
6eeefaf3 CW |
4363 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
4364 | align); | |
71acb5eb DA |
4365 | if (ret) { |
4366 | DRM_ERROR("failed to attach phys object\n"); | |
7f9872e0 | 4367 | goto fail_locked; |
71acb5eb DA |
4368 | } |
4369 | addr = obj_priv->phys_obj->handle->busaddr; | |
3f8bc370 KH |
4370 | } |
4371 | ||
14b60391 JB |
4372 | if (!IS_I9XX(dev)) |
4373 | I915_WRITE(CURSIZE, (height << 12) | width); | |
4374 | ||
3f8bc370 | 4375 | finish: |
3f8bc370 | 4376 | if (intel_crtc->cursor_bo) { |
b295d1b6 | 4377 | if (dev_priv->info->cursor_needs_physical) { |
71acb5eb DA |
4378 | if (intel_crtc->cursor_bo != bo) |
4379 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); | |
4380 | } else | |
4381 | i915_gem_object_unpin(intel_crtc->cursor_bo); | |
3f8bc370 KH |
4382 | drm_gem_object_unreference(intel_crtc->cursor_bo); |
4383 | } | |
80824003 | 4384 | |
7f9872e0 | 4385 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 KH |
4386 | |
4387 | intel_crtc->cursor_addr = addr; | |
4388 | intel_crtc->cursor_bo = bo; | |
cda4b7d3 CW |
4389 | intel_crtc->cursor_width = width; |
4390 | intel_crtc->cursor_height = height; | |
4391 | ||
4392 | intel_crtc_update_cursor(crtc); | |
3f8bc370 | 4393 | |
79e53945 | 4394 | return 0; |
e7b526bb CW |
4395 | fail_unpin: |
4396 | i915_gem_object_unpin(bo); | |
7f9872e0 | 4397 | fail_locked: |
34b8686e | 4398 | mutex_unlock(&dev->struct_mutex); |
bc9025bd LB |
4399 | fail: |
4400 | drm_gem_object_unreference_unlocked(bo); | |
34b8686e | 4401 | return ret; |
79e53945 JB |
4402 | } |
4403 | ||
4404 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
4405 | { | |
79e53945 | 4406 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 4407 | |
cda4b7d3 CW |
4408 | intel_crtc->cursor_x = x; |
4409 | intel_crtc->cursor_y = y; | |
652c393a | 4410 | |
cda4b7d3 | 4411 | intel_crtc_update_cursor(crtc); |
79e53945 JB |
4412 | |
4413 | return 0; | |
4414 | } | |
4415 | ||
4416 | /** Sets the color ramps on behalf of RandR */ | |
4417 | void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, | |
4418 | u16 blue, int regno) | |
4419 | { | |
4420 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4421 | ||
4422 | intel_crtc->lut_r[regno] = red >> 8; | |
4423 | intel_crtc->lut_g[regno] = green >> 8; | |
4424 | intel_crtc->lut_b[regno] = blue >> 8; | |
4425 | } | |
4426 | ||
b8c00ac5 DA |
4427 | void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
4428 | u16 *blue, int regno) | |
4429 | { | |
4430 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4431 | ||
4432 | *red = intel_crtc->lut_r[regno] << 8; | |
4433 | *green = intel_crtc->lut_g[regno] << 8; | |
4434 | *blue = intel_crtc->lut_b[regno] << 8; | |
4435 | } | |
4436 | ||
79e53945 | 4437 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 4438 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 4439 | { |
7203425a | 4440 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 4441 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 4442 | |
7203425a | 4443 | for (i = start; i < end; i++) { |
79e53945 JB |
4444 | intel_crtc->lut_r[i] = red[i] >> 8; |
4445 | intel_crtc->lut_g[i] = green[i] >> 8; | |
4446 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
4447 | } | |
4448 | ||
4449 | intel_crtc_load_lut(crtc); | |
4450 | } | |
4451 | ||
4452 | /** | |
4453 | * Get a pipe with a simple mode set on it for doing load-based monitor | |
4454 | * detection. | |
4455 | * | |
4456 | * It will be up to the load-detect code to adjust the pipe as appropriate for | |
c751ce4f | 4457 | * its requirements. The pipe will be connected to no other encoders. |
79e53945 | 4458 | * |
c751ce4f | 4459 | * Currently this code will only succeed if there is a pipe with no encoders |
79e53945 JB |
4460 | * configured for it. In the future, it could choose to temporarily disable |
4461 | * some outputs to free up a pipe for its use. | |
4462 | * | |
4463 | * \return crtc, or NULL if no pipes are available. | |
4464 | */ | |
4465 | ||
4466 | /* VESA 640x480x72Hz mode to set on the pipe */ | |
4467 | static struct drm_display_mode load_detect_mode = { | |
4468 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
4469 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
4470 | }; | |
4471 | ||
21d40d37 | 4472 | struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder, |
c1c43977 | 4473 | struct drm_connector *connector, |
79e53945 JB |
4474 | struct drm_display_mode *mode, |
4475 | int *dpms_mode) | |
4476 | { | |
4477 | struct intel_crtc *intel_crtc; | |
4478 | struct drm_crtc *possible_crtc; | |
4479 | struct drm_crtc *supported_crtc =NULL; | |
4ef69c7a | 4480 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
4481 | struct drm_crtc *crtc = NULL; |
4482 | struct drm_device *dev = encoder->dev; | |
4483 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
4484 | struct drm_crtc_helper_funcs *crtc_funcs; | |
4485 | int i = -1; | |
4486 | ||
4487 | /* | |
4488 | * Algorithm gets a little messy: | |
4489 | * - if the connector already has an assigned crtc, use it (but make | |
4490 | * sure it's on first) | |
4491 | * - try to find the first unused crtc that can drive this connector, | |
4492 | * and use that if we find one | |
4493 | * - if there are no unused crtcs available, try to use the first | |
4494 | * one we found that supports the connector | |
4495 | */ | |
4496 | ||
4497 | /* See if we already have a CRTC for this connector */ | |
4498 | if (encoder->crtc) { | |
4499 | crtc = encoder->crtc; | |
4500 | /* Make sure the crtc and connector are running */ | |
4501 | intel_crtc = to_intel_crtc(crtc); | |
4502 | *dpms_mode = intel_crtc->dpms_mode; | |
4503 | if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { | |
4504 | crtc_funcs = crtc->helper_private; | |
4505 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | |
4506 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); | |
4507 | } | |
4508 | return crtc; | |
4509 | } | |
4510 | ||
4511 | /* Find an unused one (if possible) */ | |
4512 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { | |
4513 | i++; | |
4514 | if (!(encoder->possible_crtcs & (1 << i))) | |
4515 | continue; | |
4516 | if (!possible_crtc->enabled) { | |
4517 | crtc = possible_crtc; | |
4518 | break; | |
4519 | } | |
4520 | if (!supported_crtc) | |
4521 | supported_crtc = possible_crtc; | |
4522 | } | |
4523 | ||
4524 | /* | |
4525 | * If we didn't find an unused CRTC, don't use any. | |
4526 | */ | |
4527 | if (!crtc) { | |
4528 | return NULL; | |
4529 | } | |
4530 | ||
4531 | encoder->crtc = crtc; | |
c1c43977 | 4532 | connector->encoder = encoder; |
21d40d37 | 4533 | intel_encoder->load_detect_temp = true; |
79e53945 JB |
4534 | |
4535 | intel_crtc = to_intel_crtc(crtc); | |
4536 | *dpms_mode = intel_crtc->dpms_mode; | |
4537 | ||
4538 | if (!crtc->enabled) { | |
4539 | if (!mode) | |
4540 | mode = &load_detect_mode; | |
3c4fdcfb | 4541 | drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb); |
79e53945 JB |
4542 | } else { |
4543 | if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { | |
4544 | crtc_funcs = crtc->helper_private; | |
4545 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | |
4546 | } | |
4547 | ||
4548 | /* Add this connector to the crtc */ | |
4549 | encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode); | |
4550 | encoder_funcs->commit(encoder); | |
4551 | } | |
4552 | /* let the connector get through one full cycle before testing */ | |
9d0498a2 | 4553 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
79e53945 JB |
4554 | |
4555 | return crtc; | |
4556 | } | |
4557 | ||
c1c43977 ZW |
4558 | void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder, |
4559 | struct drm_connector *connector, int dpms_mode) | |
79e53945 | 4560 | { |
4ef69c7a | 4561 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
4562 | struct drm_device *dev = encoder->dev; |
4563 | struct drm_crtc *crtc = encoder->crtc; | |
4564 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
4565 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
4566 | ||
21d40d37 | 4567 | if (intel_encoder->load_detect_temp) { |
79e53945 | 4568 | encoder->crtc = NULL; |
c1c43977 | 4569 | connector->encoder = NULL; |
21d40d37 | 4570 | intel_encoder->load_detect_temp = false; |
79e53945 JB |
4571 | crtc->enabled = drm_helper_crtc_in_use(crtc); |
4572 | drm_helper_disable_unused_functions(dev); | |
4573 | } | |
4574 | ||
c751ce4f | 4575 | /* Switch crtc and encoder back off if necessary */ |
79e53945 JB |
4576 | if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) { |
4577 | if (encoder->crtc == crtc) | |
4578 | encoder_funcs->dpms(encoder, dpms_mode); | |
4579 | crtc_funcs->dpms(crtc, dpms_mode); | |
4580 | } | |
4581 | } | |
4582 | ||
4583 | /* Returns the clock of the currently programmed mode of the given pipe. */ | |
4584 | static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc) | |
4585 | { | |
4586 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4587 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4588 | int pipe = intel_crtc->pipe; | |
4589 | u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B); | |
4590 | u32 fp; | |
4591 | intel_clock_t clock; | |
4592 | ||
4593 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
4594 | fp = I915_READ((pipe == 0) ? FPA0 : FPB0); | |
4595 | else | |
4596 | fp = I915_READ((pipe == 0) ? FPA1 : FPB1); | |
4597 | ||
4598 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
4599 | if (IS_PINEVIEW(dev)) { |
4600 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
4601 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
4602 | } else { |
4603 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
4604 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
4605 | } | |
4606 | ||
79e53945 | 4607 | if (IS_I9XX(dev)) { |
f2b115e6 AJ |
4608 | if (IS_PINEVIEW(dev)) |
4609 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
4610 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
4611 | else |
4612 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
4613 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
4614 | ||
4615 | switch (dpll & DPLL_MODE_MASK) { | |
4616 | case DPLLB_MODE_DAC_SERIAL: | |
4617 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
4618 | 5 : 10; | |
4619 | break; | |
4620 | case DPLLB_MODE_LVDS: | |
4621 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
4622 | 7 : 14; | |
4623 | break; | |
4624 | default: | |
28c97730 | 4625 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 JB |
4626 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
4627 | return 0; | |
4628 | } | |
4629 | ||
4630 | /* XXX: Handle the 100Mhz refclk */ | |
2177832f | 4631 | intel_clock(dev, 96000, &clock); |
79e53945 JB |
4632 | } else { |
4633 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); | |
4634 | ||
4635 | if (is_lvds) { | |
4636 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
4637 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
4638 | clock.p2 = 14; | |
4639 | ||
4640 | if ((dpll & PLL_REF_INPUT_MASK) == | |
4641 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
4642 | /* XXX: might not be 66MHz */ | |
2177832f | 4643 | intel_clock(dev, 66000, &clock); |
79e53945 | 4644 | } else |
2177832f | 4645 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
4646 | } else { |
4647 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
4648 | clock.p1 = 2; | |
4649 | else { | |
4650 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
4651 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
4652 | } | |
4653 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
4654 | clock.p2 = 4; | |
4655 | else | |
4656 | clock.p2 = 2; | |
4657 | ||
2177832f | 4658 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
4659 | } |
4660 | } | |
4661 | ||
4662 | /* XXX: It would be nice to validate the clocks, but we can't reuse | |
4663 | * i830PllIsValid() because it relies on the xf86_config connector | |
4664 | * configuration being accurate, which it isn't necessarily. | |
4665 | */ | |
4666 | ||
4667 | return clock.dot; | |
4668 | } | |
4669 | ||
4670 | /** Returns the currently programmed mode of the given pipe. */ | |
4671 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
4672 | struct drm_crtc *crtc) | |
4673 | { | |
4674 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4675 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4676 | int pipe = intel_crtc->pipe; | |
4677 | struct drm_display_mode *mode; | |
4678 | int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B); | |
4679 | int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B); | |
4680 | int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B); | |
4681 | int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B); | |
4682 | ||
4683 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
4684 | if (!mode) | |
4685 | return NULL; | |
4686 | ||
4687 | mode->clock = intel_crtc_clock_get(dev, crtc); | |
4688 | mode->hdisplay = (htot & 0xffff) + 1; | |
4689 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
4690 | mode->hsync_start = (hsync & 0xffff) + 1; | |
4691 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
4692 | mode->vdisplay = (vtot & 0xffff) + 1; | |
4693 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
4694 | mode->vsync_start = (vsync & 0xffff) + 1; | |
4695 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
4696 | ||
4697 | drm_mode_set_name(mode); | |
4698 | drm_mode_set_crtcinfo(mode, 0); | |
4699 | ||
4700 | return mode; | |
4701 | } | |
4702 | ||
652c393a JB |
4703 | #define GPU_IDLE_TIMEOUT 500 /* ms */ |
4704 | ||
4705 | /* When this timer fires, we've been idle for awhile */ | |
4706 | static void intel_gpu_idle_timer(unsigned long arg) | |
4707 | { | |
4708 | struct drm_device *dev = (struct drm_device *)arg; | |
4709 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4710 | ||
44d98a61 | 4711 | DRM_DEBUG_DRIVER("idle timer fired, downclocking\n"); |
652c393a JB |
4712 | |
4713 | dev_priv->busy = false; | |
4714 | ||
01dfba93 | 4715 | queue_work(dev_priv->wq, &dev_priv->idle_work); |
652c393a JB |
4716 | } |
4717 | ||
652c393a JB |
4718 | #define CRTC_IDLE_TIMEOUT 1000 /* ms */ |
4719 | ||
4720 | static void intel_crtc_idle_timer(unsigned long arg) | |
4721 | { | |
4722 | struct intel_crtc *intel_crtc = (struct intel_crtc *)arg; | |
4723 | struct drm_crtc *crtc = &intel_crtc->base; | |
4724 | drm_i915_private_t *dev_priv = crtc->dev->dev_private; | |
4725 | ||
44d98a61 | 4726 | DRM_DEBUG_DRIVER("idle timer fired, downclocking\n"); |
652c393a JB |
4727 | |
4728 | intel_crtc->busy = false; | |
4729 | ||
01dfba93 | 4730 | queue_work(dev_priv->wq, &dev_priv->idle_work); |
652c393a JB |
4731 | } |
4732 | ||
3dec0095 | 4733 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
652c393a JB |
4734 | { |
4735 | struct drm_device *dev = crtc->dev; | |
4736 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4737 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4738 | int pipe = intel_crtc->pipe; | |
4739 | int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; | |
4740 | int dpll = I915_READ(dpll_reg); | |
4741 | ||
bad720ff | 4742 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
4743 | return; |
4744 | ||
4745 | if (!dev_priv->lvds_downclock_avail) | |
4746 | return; | |
4747 | ||
4748 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { | |
44d98a61 | 4749 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
652c393a JB |
4750 | |
4751 | /* Unlock panel regs */ | |
4a655f04 JB |
4752 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | |
4753 | PANEL_UNLOCK_REGS); | |
652c393a JB |
4754 | |
4755 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; | |
4756 | I915_WRITE(dpll_reg, dpll); | |
4757 | dpll = I915_READ(dpll_reg); | |
9d0498a2 | 4758 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
4759 | dpll = I915_READ(dpll_reg); |
4760 | if (dpll & DISPLAY_RATE_SELECT_FPA1) | |
44d98a61 | 4761 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
652c393a JB |
4762 | |
4763 | /* ...and lock them again */ | |
4764 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3); | |
4765 | } | |
4766 | ||
4767 | /* Schedule downclock */ | |
3dec0095 DV |
4768 | mod_timer(&intel_crtc->idle_timer, jiffies + |
4769 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); | |
652c393a JB |
4770 | } |
4771 | ||
4772 | static void intel_decrease_pllclock(struct drm_crtc *crtc) | |
4773 | { | |
4774 | struct drm_device *dev = crtc->dev; | |
4775 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4776 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4777 | int pipe = intel_crtc->pipe; | |
4778 | int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; | |
4779 | int dpll = I915_READ(dpll_reg); | |
4780 | ||
bad720ff | 4781 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
4782 | return; |
4783 | ||
4784 | if (!dev_priv->lvds_downclock_avail) | |
4785 | return; | |
4786 | ||
4787 | /* | |
4788 | * Since this is called by a timer, we should never get here in | |
4789 | * the manual case. | |
4790 | */ | |
4791 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
44d98a61 | 4792 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a JB |
4793 | |
4794 | /* Unlock panel regs */ | |
4a655f04 JB |
4795 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | |
4796 | PANEL_UNLOCK_REGS); | |
652c393a JB |
4797 | |
4798 | dpll |= DISPLAY_RATE_SELECT_FPA1; | |
4799 | I915_WRITE(dpll_reg, dpll); | |
4800 | dpll = I915_READ(dpll_reg); | |
9d0498a2 | 4801 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
4802 | dpll = I915_READ(dpll_reg); |
4803 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 4804 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
4805 | |
4806 | /* ...and lock them again */ | |
4807 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3); | |
4808 | } | |
4809 | ||
4810 | } | |
4811 | ||
4812 | /** | |
4813 | * intel_idle_update - adjust clocks for idleness | |
4814 | * @work: work struct | |
4815 | * | |
4816 | * Either the GPU or display (or both) went idle. Check the busy status | |
4817 | * here and adjust the CRTC and GPU clocks as necessary. | |
4818 | */ | |
4819 | static void intel_idle_update(struct work_struct *work) | |
4820 | { | |
4821 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
4822 | idle_work); | |
4823 | struct drm_device *dev = dev_priv->dev; | |
4824 | struct drm_crtc *crtc; | |
4825 | struct intel_crtc *intel_crtc; | |
45ac22c8 | 4826 | int enabled = 0; |
652c393a JB |
4827 | |
4828 | if (!i915_powersave) | |
4829 | return; | |
4830 | ||
4831 | mutex_lock(&dev->struct_mutex); | |
4832 | ||
7648fa99 JB |
4833 | i915_update_gfx_val(dev_priv); |
4834 | ||
652c393a JB |
4835 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
4836 | /* Skip inactive CRTCs */ | |
4837 | if (!crtc->fb) | |
4838 | continue; | |
4839 | ||
45ac22c8 | 4840 | enabled++; |
652c393a JB |
4841 | intel_crtc = to_intel_crtc(crtc); |
4842 | if (!intel_crtc->busy) | |
4843 | intel_decrease_pllclock(crtc); | |
4844 | } | |
4845 | ||
45ac22c8 LP |
4846 | if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) { |
4847 | DRM_DEBUG_DRIVER("enable memory self refresh on 945\n"); | |
4848 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN); | |
4849 | } | |
4850 | ||
652c393a JB |
4851 | mutex_unlock(&dev->struct_mutex); |
4852 | } | |
4853 | ||
4854 | /** | |
4855 | * intel_mark_busy - mark the GPU and possibly the display busy | |
4856 | * @dev: drm device | |
4857 | * @obj: object we're operating on | |
4858 | * | |
4859 | * Callers can use this function to indicate that the GPU is busy processing | |
4860 | * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout | |
4861 | * buffer), we'll also mark the display as busy, so we know to increase its | |
4862 | * clock frequency. | |
4863 | */ | |
4864 | void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj) | |
4865 | { | |
4866 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4867 | struct drm_crtc *crtc = NULL; | |
4868 | struct intel_framebuffer *intel_fb; | |
4869 | struct intel_crtc *intel_crtc; | |
4870 | ||
5e17ee74 ZW |
4871 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4872 | return; | |
4873 | ||
060e645a LP |
4874 | if (!dev_priv->busy) { |
4875 | if (IS_I945G(dev) || IS_I945GM(dev)) { | |
4876 | u32 fw_blc_self; | |
ee980b80 | 4877 | |
060e645a LP |
4878 | DRM_DEBUG_DRIVER("disable memory self refresh on 945\n"); |
4879 | fw_blc_self = I915_READ(FW_BLC_SELF); | |
4880 | fw_blc_self &= ~FW_BLC_SELF_EN; | |
4881 | I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK); | |
4882 | } | |
28cf798f | 4883 | dev_priv->busy = true; |
060e645a | 4884 | } else |
28cf798f CW |
4885 | mod_timer(&dev_priv->idle_timer, jiffies + |
4886 | msecs_to_jiffies(GPU_IDLE_TIMEOUT)); | |
652c393a JB |
4887 | |
4888 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
4889 | if (!crtc->fb) | |
4890 | continue; | |
4891 | ||
4892 | intel_crtc = to_intel_crtc(crtc); | |
4893 | intel_fb = to_intel_framebuffer(crtc->fb); | |
4894 | if (intel_fb->obj == obj) { | |
4895 | if (!intel_crtc->busy) { | |
060e645a LP |
4896 | if (IS_I945G(dev) || IS_I945GM(dev)) { |
4897 | u32 fw_blc_self; | |
4898 | ||
4899 | DRM_DEBUG_DRIVER("disable memory self refresh on 945\n"); | |
4900 | fw_blc_self = I915_READ(FW_BLC_SELF); | |
4901 | fw_blc_self &= ~FW_BLC_SELF_EN; | |
4902 | I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK); | |
4903 | } | |
652c393a | 4904 | /* Non-busy -> busy, upclock */ |
3dec0095 | 4905 | intel_increase_pllclock(crtc); |
652c393a JB |
4906 | intel_crtc->busy = true; |
4907 | } else { | |
4908 | /* Busy -> busy, put off timer */ | |
4909 | mod_timer(&intel_crtc->idle_timer, jiffies + | |
4910 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); | |
4911 | } | |
4912 | } | |
4913 | } | |
4914 | } | |
4915 | ||
79e53945 JB |
4916 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
4917 | { | |
4918 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
4919 | struct drm_device *dev = crtc->dev; |
4920 | struct intel_unpin_work *work; | |
4921 | unsigned long flags; | |
4922 | ||
4923 | spin_lock_irqsave(&dev->event_lock, flags); | |
4924 | work = intel_crtc->unpin_work; | |
4925 | intel_crtc->unpin_work = NULL; | |
4926 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
4927 | ||
4928 | if (work) { | |
4929 | cancel_work_sync(&work->work); | |
4930 | kfree(work); | |
4931 | } | |
79e53945 JB |
4932 | |
4933 | drm_crtc_cleanup(crtc); | |
67e77c5a | 4934 | |
79e53945 JB |
4935 | kfree(intel_crtc); |
4936 | } | |
4937 | ||
6b95a207 KH |
4938 | static void intel_unpin_work_fn(struct work_struct *__work) |
4939 | { | |
4940 | struct intel_unpin_work *work = | |
4941 | container_of(__work, struct intel_unpin_work, work); | |
4942 | ||
4943 | mutex_lock(&work->dev->struct_mutex); | |
b1b87f6b | 4944 | i915_gem_object_unpin(work->old_fb_obj); |
75dfca80 | 4945 | drm_gem_object_unreference(work->pending_flip_obj); |
b1b87f6b | 4946 | drm_gem_object_unreference(work->old_fb_obj); |
6b95a207 KH |
4947 | mutex_unlock(&work->dev->struct_mutex); |
4948 | kfree(work); | |
4949 | } | |
4950 | ||
1afe3e9d JB |
4951 | static void do_intel_finish_page_flip(struct drm_device *dev, |
4952 | struct drm_crtc *crtc) | |
6b95a207 KH |
4953 | { |
4954 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6b95a207 KH |
4955 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4956 | struct intel_unpin_work *work; | |
4957 | struct drm_i915_gem_object *obj_priv; | |
4958 | struct drm_pending_vblank_event *e; | |
4959 | struct timeval now; | |
4960 | unsigned long flags; | |
4961 | ||
4962 | /* Ignore early vblank irqs */ | |
4963 | if (intel_crtc == NULL) | |
4964 | return; | |
4965 | ||
4966 | spin_lock_irqsave(&dev->event_lock, flags); | |
4967 | work = intel_crtc->unpin_work; | |
4968 | if (work == NULL || !work->pending) { | |
4969 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
4970 | return; | |
4971 | } | |
4972 | ||
4973 | intel_crtc->unpin_work = NULL; | |
4974 | drm_vblank_put(dev, intel_crtc->pipe); | |
4975 | ||
4976 | if (work->event) { | |
4977 | e = work->event; | |
4978 | do_gettimeofday(&now); | |
4979 | e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe); | |
4980 | e->event.tv_sec = now.tv_sec; | |
4981 | e->event.tv_usec = now.tv_usec; | |
4982 | list_add_tail(&e->base.link, | |
4983 | &e->base.file_priv->event_list); | |
4984 | wake_up_interruptible(&e->base.file_priv->event_wait); | |
4985 | } | |
4986 | ||
4987 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
4988 | ||
23010e43 | 4989 | obj_priv = to_intel_bo(work->pending_flip_obj); |
de3f440f JB |
4990 | |
4991 | /* Initial scanout buffer will have a 0 pending flip count */ | |
4992 | if ((atomic_read(&obj_priv->pending_flip) == 0) || | |
4993 | atomic_dec_and_test(&obj_priv->pending_flip)) | |
6b95a207 KH |
4994 | DRM_WAKEUP(&dev_priv->pending_flip_queue); |
4995 | schedule_work(&work->work); | |
e5510fac JB |
4996 | |
4997 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); | |
6b95a207 KH |
4998 | } |
4999 | ||
1afe3e9d JB |
5000 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
5001 | { | |
5002 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5003 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
5004 | ||
5005 | do_intel_finish_page_flip(dev, crtc); | |
5006 | } | |
5007 | ||
5008 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
5009 | { | |
5010 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5011 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; | |
5012 | ||
5013 | do_intel_finish_page_flip(dev, crtc); | |
5014 | } | |
5015 | ||
6b95a207 KH |
5016 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
5017 | { | |
5018 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5019 | struct intel_crtc *intel_crtc = | |
5020 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
5021 | unsigned long flags; | |
5022 | ||
5023 | spin_lock_irqsave(&dev->event_lock, flags); | |
de3f440f | 5024 | if (intel_crtc->unpin_work) { |
4e5359cd SF |
5025 | if ((++intel_crtc->unpin_work->pending) > 1) |
5026 | DRM_ERROR("Prepared flip multiple times\n"); | |
de3f440f JB |
5027 | } else { |
5028 | DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n"); | |
5029 | } | |
6b95a207 KH |
5030 | spin_unlock_irqrestore(&dev->event_lock, flags); |
5031 | } | |
5032 | ||
5033 | static int intel_crtc_page_flip(struct drm_crtc *crtc, | |
5034 | struct drm_framebuffer *fb, | |
5035 | struct drm_pending_vblank_event *event) | |
5036 | { | |
5037 | struct drm_device *dev = crtc->dev; | |
5038 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5039 | struct intel_framebuffer *intel_fb; | |
5040 | struct drm_i915_gem_object *obj_priv; | |
5041 | struct drm_gem_object *obj; | |
5042 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5043 | struct intel_unpin_work *work; | |
be9a3dbf | 5044 | unsigned long flags, offset; |
52e68630 CW |
5045 | int pipe = intel_crtc->pipe; |
5046 | u32 pf, pipesrc; | |
5047 | int ret; | |
6b95a207 KH |
5048 | |
5049 | work = kzalloc(sizeof *work, GFP_KERNEL); | |
5050 | if (work == NULL) | |
5051 | return -ENOMEM; | |
5052 | ||
6b95a207 KH |
5053 | work->event = event; |
5054 | work->dev = crtc->dev; | |
5055 | intel_fb = to_intel_framebuffer(crtc->fb); | |
b1b87f6b | 5056 | work->old_fb_obj = intel_fb->obj; |
6b95a207 KH |
5057 | INIT_WORK(&work->work, intel_unpin_work_fn); |
5058 | ||
5059 | /* We borrow the event spin lock for protecting unpin_work */ | |
5060 | spin_lock_irqsave(&dev->event_lock, flags); | |
5061 | if (intel_crtc->unpin_work) { | |
5062 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
5063 | kfree(work); | |
468f0b44 CW |
5064 | |
5065 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
6b95a207 KH |
5066 | return -EBUSY; |
5067 | } | |
5068 | intel_crtc->unpin_work = work; | |
5069 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
5070 | ||
5071 | intel_fb = to_intel_framebuffer(fb); | |
5072 | obj = intel_fb->obj; | |
5073 | ||
468f0b44 | 5074 | mutex_lock(&dev->struct_mutex); |
6b95a207 | 5075 | ret = intel_pin_and_fence_fb_obj(dev, obj); |
96b099fd CW |
5076 | if (ret) |
5077 | goto cleanup_work; | |
6b95a207 | 5078 | |
75dfca80 | 5079 | /* Reference the objects for the scheduled work. */ |
b1b87f6b | 5080 | drm_gem_object_reference(work->old_fb_obj); |
75dfca80 | 5081 | drm_gem_object_reference(obj); |
6b95a207 KH |
5082 | |
5083 | crtc->fb = fb; | |
2dafb1e0 CW |
5084 | ret = i915_gem_object_flush_write_domain(obj); |
5085 | if (ret) | |
5086 | goto cleanup_objs; | |
96b099fd CW |
5087 | |
5088 | ret = drm_vblank_get(dev, intel_crtc->pipe); | |
5089 | if (ret) | |
5090 | goto cleanup_objs; | |
5091 | ||
23010e43 | 5092 | obj_priv = to_intel_bo(obj); |
6b95a207 | 5093 | atomic_inc(&obj_priv->pending_flip); |
b1b87f6b | 5094 | work->pending_flip_obj = obj; |
6b95a207 | 5095 | |
6146b3d6 | 5096 | if (IS_GEN3(dev) || IS_GEN2(dev)) { |
52e68630 CW |
5097 | u32 flip_mask; |
5098 | ||
5099 | if (intel_crtc->plane) | |
5100 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
5101 | else | |
5102 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
5103 | ||
6146b3d6 DV |
5104 | BEGIN_LP_RING(2); |
5105 | OUT_RING(MI_WAIT_FOR_EVENT | flip_mask); | |
5106 | OUT_RING(0); | |
5107 | ADVANCE_LP_RING(); | |
5108 | } | |
83f7fd05 | 5109 | |
4e5359cd SF |
5110 | work->enable_stall_check = true; |
5111 | ||
be9a3dbf | 5112 | /* Offset into the new buffer for cases of shared fbs between CRTCs */ |
52e68630 | 5113 | offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8; |
be9a3dbf | 5114 | |
6b95a207 | 5115 | BEGIN_LP_RING(4); |
52e68630 CW |
5116 | switch(INTEL_INFO(dev)->gen) { |
5117 | case 2: | |
1afe3e9d JB |
5118 | OUT_RING(MI_DISPLAY_FLIP | |
5119 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
5120 | OUT_RING(fb->pitch); | |
52e68630 CW |
5121 | OUT_RING(obj_priv->gtt_offset + offset); |
5122 | OUT_RING(MI_NOOP); | |
5123 | break; | |
5124 | ||
5125 | case 3: | |
1afe3e9d JB |
5126 | OUT_RING(MI_DISPLAY_FLIP_I915 | |
5127 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
5128 | OUT_RING(fb->pitch); | |
52e68630 | 5129 | OUT_RING(obj_priv->gtt_offset + offset); |
22fd0fab | 5130 | OUT_RING(MI_NOOP); |
52e68630 CW |
5131 | break; |
5132 | ||
5133 | case 4: | |
5134 | case 5: | |
5135 | /* i965+ uses the linear or tiled offsets from the | |
5136 | * Display Registers (which do not change across a page-flip) | |
5137 | * so we need only reprogram the base address. | |
5138 | */ | |
69d0b96c DV |
5139 | OUT_RING(MI_DISPLAY_FLIP | |
5140 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
5141 | OUT_RING(fb->pitch); | |
52e68630 CW |
5142 | OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode); |
5143 | ||
5144 | /* XXX Enabling the panel-fitter across page-flip is so far | |
5145 | * untested on non-native modes, so ignore it for now. | |
5146 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
5147 | */ | |
5148 | pf = 0; | |
5149 | pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff; | |
5150 | OUT_RING(pf | pipesrc); | |
5151 | break; | |
5152 | ||
5153 | case 6: | |
5154 | OUT_RING(MI_DISPLAY_FLIP | | |
5155 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
5156 | OUT_RING(fb->pitch | obj_priv->tiling_mode); | |
5157 | OUT_RING(obj_priv->gtt_offset); | |
5158 | ||
5159 | pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
5160 | pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff; | |
5161 | OUT_RING(pf | pipesrc); | |
5162 | break; | |
22fd0fab | 5163 | } |
6b95a207 KH |
5164 | ADVANCE_LP_RING(); |
5165 | ||
5166 | mutex_unlock(&dev->struct_mutex); | |
5167 | ||
e5510fac JB |
5168 | trace_i915_flip_request(intel_crtc->plane, obj); |
5169 | ||
6b95a207 | 5170 | return 0; |
96b099fd CW |
5171 | |
5172 | cleanup_objs: | |
5173 | drm_gem_object_unreference(work->old_fb_obj); | |
5174 | drm_gem_object_unreference(obj); | |
5175 | cleanup_work: | |
5176 | mutex_unlock(&dev->struct_mutex); | |
5177 | ||
5178 | spin_lock_irqsave(&dev->event_lock, flags); | |
5179 | intel_crtc->unpin_work = NULL; | |
5180 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
5181 | ||
5182 | kfree(work); | |
5183 | ||
5184 | return ret; | |
6b95a207 KH |
5185 | } |
5186 | ||
79e53945 JB |
5187 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
5188 | .dpms = intel_crtc_dpms, | |
5189 | .mode_fixup = intel_crtc_mode_fixup, | |
5190 | .mode_set = intel_crtc_mode_set, | |
5191 | .mode_set_base = intel_pipe_set_base, | |
81255565 | 5192 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
79e53945 JB |
5193 | .prepare = intel_crtc_prepare, |
5194 | .commit = intel_crtc_commit, | |
068143d3 | 5195 | .load_lut = intel_crtc_load_lut, |
79e53945 JB |
5196 | }; |
5197 | ||
5198 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
5199 | .cursor_set = intel_crtc_cursor_set, | |
5200 | .cursor_move = intel_crtc_cursor_move, | |
5201 | .gamma_set = intel_crtc_gamma_set, | |
5202 | .set_config = drm_crtc_helper_set_config, | |
5203 | .destroy = intel_crtc_destroy, | |
6b95a207 | 5204 | .page_flip = intel_crtc_page_flip, |
79e53945 JB |
5205 | }; |
5206 | ||
5207 | ||
b358d0a6 | 5208 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 5209 | { |
22fd0fab | 5210 | drm_i915_private_t *dev_priv = dev->dev_private; |
79e53945 JB |
5211 | struct intel_crtc *intel_crtc; |
5212 | int i; | |
5213 | ||
5214 | intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); | |
5215 | if (intel_crtc == NULL) | |
5216 | return; | |
5217 | ||
5218 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); | |
5219 | ||
5220 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
5221 | intel_crtc->pipe = pipe; | |
7662c8bd | 5222 | intel_crtc->plane = pipe; |
79e53945 JB |
5223 | for (i = 0; i < 256; i++) { |
5224 | intel_crtc->lut_r[i] = i; | |
5225 | intel_crtc->lut_g[i] = i; | |
5226 | intel_crtc->lut_b[i] = i; | |
5227 | } | |
5228 | ||
80824003 JB |
5229 | /* Swap pipes & planes for FBC on pre-965 */ |
5230 | intel_crtc->pipe = pipe; | |
5231 | intel_crtc->plane = pipe; | |
5232 | if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) { | |
28c97730 | 5233 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
80824003 JB |
5234 | intel_crtc->plane = ((pipe == 0) ? 1 : 0); |
5235 | } | |
5236 | ||
22fd0fab JB |
5237 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
5238 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
5239 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
5240 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
5241 | ||
79e53945 | 5242 | intel_crtc->cursor_addr = 0; |
032d2a0d | 5243 | intel_crtc->dpms_mode = -1; |
79e53945 JB |
5244 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
5245 | ||
652c393a JB |
5246 | intel_crtc->busy = false; |
5247 | ||
5248 | setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer, | |
5249 | (unsigned long)intel_crtc); | |
79e53945 JB |
5250 | } |
5251 | ||
08d7b3d1 CW |
5252 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
5253 | struct drm_file *file_priv) | |
5254 | { | |
5255 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5256 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; | |
c05422d5 DV |
5257 | struct drm_mode_object *drmmode_obj; |
5258 | struct intel_crtc *crtc; | |
08d7b3d1 CW |
5259 | |
5260 | if (!dev_priv) { | |
5261 | DRM_ERROR("called with no initialization\n"); | |
5262 | return -EINVAL; | |
5263 | } | |
5264 | ||
c05422d5 DV |
5265 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
5266 | DRM_MODE_OBJECT_CRTC); | |
08d7b3d1 | 5267 | |
c05422d5 | 5268 | if (!drmmode_obj) { |
08d7b3d1 CW |
5269 | DRM_ERROR("no such CRTC id\n"); |
5270 | return -EINVAL; | |
5271 | } | |
5272 | ||
c05422d5 DV |
5273 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
5274 | pipe_from_crtc_id->pipe = crtc->pipe; | |
08d7b3d1 | 5275 | |
c05422d5 | 5276 | return 0; |
08d7b3d1 CW |
5277 | } |
5278 | ||
c5e4df33 | 5279 | static int intel_encoder_clones(struct drm_device *dev, int type_mask) |
79e53945 | 5280 | { |
4ef69c7a | 5281 | struct intel_encoder *encoder; |
79e53945 | 5282 | int index_mask = 0; |
79e53945 JB |
5283 | int entry = 0; |
5284 | ||
4ef69c7a CW |
5285 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
5286 | if (type_mask & encoder->clone_mask) | |
79e53945 JB |
5287 | index_mask |= (1 << entry); |
5288 | entry++; | |
5289 | } | |
4ef69c7a | 5290 | |
79e53945 JB |
5291 | return index_mask; |
5292 | } | |
5293 | ||
79e53945 JB |
5294 | static void intel_setup_outputs(struct drm_device *dev) |
5295 | { | |
725e30ad | 5296 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 5297 | struct intel_encoder *encoder; |
cb0953d7 | 5298 | bool dpd_is_edp = false; |
79e53945 | 5299 | |
541998a1 | 5300 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
79e53945 JB |
5301 | intel_lvds_init(dev); |
5302 | ||
bad720ff | 5303 | if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 5304 | dpd_is_edp = intel_dpd_is_edp(dev); |
30ad48b7 | 5305 | |
32f9d658 ZW |
5306 | if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED)) |
5307 | intel_dp_init(dev, DP_A); | |
5308 | ||
cb0953d7 AJ |
5309 | if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) |
5310 | intel_dp_init(dev, PCH_DP_D); | |
5311 | } | |
5312 | ||
5313 | intel_crt_init(dev); | |
5314 | ||
5315 | if (HAS_PCH_SPLIT(dev)) { | |
5316 | int found; | |
5317 | ||
30ad48b7 | 5318 | if (I915_READ(HDMIB) & PORT_DETECTED) { |
461ed3ca ZY |
5319 | /* PCH SDVOB multiplex with HDMIB */ |
5320 | found = intel_sdvo_init(dev, PCH_SDVOB); | |
30ad48b7 ZW |
5321 | if (!found) |
5322 | intel_hdmi_init(dev, HDMIB); | |
5eb08b69 ZW |
5323 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
5324 | intel_dp_init(dev, PCH_DP_B); | |
30ad48b7 ZW |
5325 | } |
5326 | ||
5327 | if (I915_READ(HDMIC) & PORT_DETECTED) | |
5328 | intel_hdmi_init(dev, HDMIC); | |
5329 | ||
5330 | if (I915_READ(HDMID) & PORT_DETECTED) | |
5331 | intel_hdmi_init(dev, HDMID); | |
5332 | ||
5eb08b69 ZW |
5333 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
5334 | intel_dp_init(dev, PCH_DP_C); | |
5335 | ||
cb0953d7 | 5336 | if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) |
5eb08b69 ZW |
5337 | intel_dp_init(dev, PCH_DP_D); |
5338 | ||
103a196f | 5339 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 5340 | bool found = false; |
7d57382e | 5341 | |
725e30ad | 5342 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 5343 | DRM_DEBUG_KMS("probing SDVOB\n"); |
725e30ad | 5344 | found = intel_sdvo_init(dev, SDVOB); |
b01f2c3a JB |
5345 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
5346 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
725e30ad | 5347 | intel_hdmi_init(dev, SDVOB); |
b01f2c3a | 5348 | } |
27185ae1 | 5349 | |
b01f2c3a JB |
5350 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) { |
5351 | DRM_DEBUG_KMS("probing DP_B\n"); | |
a4fc5ed6 | 5352 | intel_dp_init(dev, DP_B); |
b01f2c3a | 5353 | } |
725e30ad | 5354 | } |
13520b05 KH |
5355 | |
5356 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 5357 | |
b01f2c3a JB |
5358 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
5359 | DRM_DEBUG_KMS("probing SDVOC\n"); | |
725e30ad | 5360 | found = intel_sdvo_init(dev, SDVOC); |
b01f2c3a | 5361 | } |
27185ae1 ML |
5362 | |
5363 | if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) { | |
5364 | ||
b01f2c3a JB |
5365 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
5366 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
725e30ad | 5367 | intel_hdmi_init(dev, SDVOC); |
b01f2c3a JB |
5368 | } |
5369 | if (SUPPORTS_INTEGRATED_DP(dev)) { | |
5370 | DRM_DEBUG_KMS("probing DP_C\n"); | |
a4fc5ed6 | 5371 | intel_dp_init(dev, DP_C); |
b01f2c3a | 5372 | } |
725e30ad | 5373 | } |
27185ae1 | 5374 | |
b01f2c3a JB |
5375 | if (SUPPORTS_INTEGRATED_DP(dev) && |
5376 | (I915_READ(DP_D) & DP_DETECTED)) { | |
5377 | DRM_DEBUG_KMS("probing DP_D\n"); | |
a4fc5ed6 | 5378 | intel_dp_init(dev, DP_D); |
b01f2c3a | 5379 | } |
bad720ff | 5380 | } else if (IS_GEN2(dev)) |
79e53945 JB |
5381 | intel_dvo_init(dev); |
5382 | ||
103a196f | 5383 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
5384 | intel_tv_init(dev); |
5385 | ||
4ef69c7a CW |
5386 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
5387 | encoder->base.possible_crtcs = encoder->crtc_mask; | |
5388 | encoder->base.possible_clones = | |
5389 | intel_encoder_clones(dev, encoder->clone_mask); | |
79e53945 JB |
5390 | } |
5391 | } | |
5392 | ||
5393 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
5394 | { | |
5395 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 JB |
5396 | |
5397 | drm_framebuffer_cleanup(fb); | |
bc9025bd | 5398 | drm_gem_object_unreference_unlocked(intel_fb->obj); |
79e53945 JB |
5399 | |
5400 | kfree(intel_fb); | |
5401 | } | |
5402 | ||
5403 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
5404 | struct drm_file *file_priv, | |
5405 | unsigned int *handle) | |
5406 | { | |
5407 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
5408 | struct drm_gem_object *object = intel_fb->obj; | |
5409 | ||
5410 | return drm_gem_handle_create(file_priv, object, handle); | |
5411 | } | |
5412 | ||
5413 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
5414 | .destroy = intel_user_framebuffer_destroy, | |
5415 | .create_handle = intel_user_framebuffer_create_handle, | |
5416 | }; | |
5417 | ||
38651674 DA |
5418 | int intel_framebuffer_init(struct drm_device *dev, |
5419 | struct intel_framebuffer *intel_fb, | |
5420 | struct drm_mode_fb_cmd *mode_cmd, | |
5421 | struct drm_gem_object *obj) | |
79e53945 | 5422 | { |
57cd6508 | 5423 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
79e53945 JB |
5424 | int ret; |
5425 | ||
57cd6508 CW |
5426 | if (obj_priv->tiling_mode == I915_TILING_Y) |
5427 | return -EINVAL; | |
5428 | ||
5429 | if (mode_cmd->pitch & 63) | |
5430 | return -EINVAL; | |
5431 | ||
5432 | switch (mode_cmd->bpp) { | |
5433 | case 8: | |
5434 | case 16: | |
5435 | case 24: | |
5436 | case 32: | |
5437 | break; | |
5438 | default: | |
5439 | return -EINVAL; | |
5440 | } | |
5441 | ||
79e53945 JB |
5442 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
5443 | if (ret) { | |
5444 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
5445 | return ret; | |
5446 | } | |
5447 | ||
5448 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); | |
79e53945 | 5449 | intel_fb->obj = obj; |
79e53945 JB |
5450 | return 0; |
5451 | } | |
5452 | ||
79e53945 JB |
5453 | static struct drm_framebuffer * |
5454 | intel_user_framebuffer_create(struct drm_device *dev, | |
5455 | struct drm_file *filp, | |
5456 | struct drm_mode_fb_cmd *mode_cmd) | |
5457 | { | |
5458 | struct drm_gem_object *obj; | |
38651674 | 5459 | struct intel_framebuffer *intel_fb; |
79e53945 JB |
5460 | int ret; |
5461 | ||
5462 | obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle); | |
5463 | if (!obj) | |
cce13ff7 | 5464 | return ERR_PTR(-ENOENT); |
79e53945 | 5465 | |
38651674 DA |
5466 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
5467 | if (!intel_fb) | |
cce13ff7 | 5468 | return ERR_PTR(-ENOMEM); |
38651674 DA |
5469 | |
5470 | ret = intel_framebuffer_init(dev, intel_fb, | |
5471 | mode_cmd, obj); | |
79e53945 | 5472 | if (ret) { |
bc9025bd | 5473 | drm_gem_object_unreference_unlocked(obj); |
38651674 | 5474 | kfree(intel_fb); |
cce13ff7 | 5475 | return ERR_PTR(ret); |
79e53945 JB |
5476 | } |
5477 | ||
38651674 | 5478 | return &intel_fb->base; |
79e53945 JB |
5479 | } |
5480 | ||
79e53945 | 5481 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 5482 | .fb_create = intel_user_framebuffer_create, |
eb1f8e4f | 5483 | .output_poll_changed = intel_fb_output_poll_changed, |
79e53945 JB |
5484 | }; |
5485 | ||
9ea8d059 | 5486 | static struct drm_gem_object * |
aa40d6bb | 5487 | intel_alloc_context_page(struct drm_device *dev) |
9ea8d059 | 5488 | { |
aa40d6bb | 5489 | struct drm_gem_object *ctx; |
9ea8d059 CW |
5490 | int ret; |
5491 | ||
aa40d6bb ZN |
5492 | ctx = i915_gem_alloc_object(dev, 4096); |
5493 | if (!ctx) { | |
9ea8d059 CW |
5494 | DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); |
5495 | return NULL; | |
5496 | } | |
5497 | ||
5498 | mutex_lock(&dev->struct_mutex); | |
aa40d6bb | 5499 | ret = i915_gem_object_pin(ctx, 4096); |
9ea8d059 CW |
5500 | if (ret) { |
5501 | DRM_ERROR("failed to pin power context: %d\n", ret); | |
5502 | goto err_unref; | |
5503 | } | |
5504 | ||
aa40d6bb | 5505 | ret = i915_gem_object_set_to_gtt_domain(ctx, 1); |
9ea8d059 CW |
5506 | if (ret) { |
5507 | DRM_ERROR("failed to set-domain on power context: %d\n", ret); | |
5508 | goto err_unpin; | |
5509 | } | |
5510 | mutex_unlock(&dev->struct_mutex); | |
5511 | ||
aa40d6bb | 5512 | return ctx; |
9ea8d059 CW |
5513 | |
5514 | err_unpin: | |
aa40d6bb | 5515 | i915_gem_object_unpin(ctx); |
9ea8d059 | 5516 | err_unref: |
aa40d6bb | 5517 | drm_gem_object_unreference(ctx); |
9ea8d059 CW |
5518 | mutex_unlock(&dev->struct_mutex); |
5519 | return NULL; | |
5520 | } | |
5521 | ||
7648fa99 JB |
5522 | bool ironlake_set_drps(struct drm_device *dev, u8 val) |
5523 | { | |
5524 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5525 | u16 rgvswctl; | |
5526 | ||
5527 | rgvswctl = I915_READ16(MEMSWCTL); | |
5528 | if (rgvswctl & MEMCTL_CMD_STS) { | |
5529 | DRM_DEBUG("gpu busy, RCS change rejected\n"); | |
5530 | return false; /* still busy with another command */ | |
5531 | } | |
5532 | ||
5533 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | | |
5534 | (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; | |
5535 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
5536 | POSTING_READ16(MEMSWCTL); | |
5537 | ||
5538 | rgvswctl |= MEMCTL_CMD_STS; | |
5539 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
5540 | ||
5541 | return true; | |
5542 | } | |
5543 | ||
f97108d1 JB |
5544 | void ironlake_enable_drps(struct drm_device *dev) |
5545 | { | |
5546 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7648fa99 | 5547 | u32 rgvmodectl = I915_READ(MEMMODECTL); |
f97108d1 | 5548 | u8 fmax, fmin, fstart, vstart; |
f97108d1 JB |
5549 | |
5550 | /* 100ms RC evaluation intervals */ | |
5551 | I915_WRITE(RCUPEI, 100000); | |
5552 | I915_WRITE(RCDNEI, 100000); | |
5553 | ||
5554 | /* Set max/min thresholds to 90ms and 80ms respectively */ | |
5555 | I915_WRITE(RCBMAXAVG, 90000); | |
5556 | I915_WRITE(RCBMINAVG, 80000); | |
5557 | ||
5558 | I915_WRITE(MEMIHYST, 1); | |
5559 | ||
5560 | /* Set up min, max, and cur for interrupt handling */ | |
5561 | fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; | |
5562 | fmin = (rgvmodectl & MEMMODE_FMIN_MASK); | |
5563 | fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> | |
5564 | MEMMODE_FSTART_SHIFT; | |
7648fa99 JB |
5565 | fstart = fmax; |
5566 | ||
f97108d1 JB |
5567 | vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >> |
5568 | PXVFREQ_PX_SHIFT; | |
5569 | ||
7648fa99 JB |
5570 | dev_priv->fmax = fstart; /* IPS callback will increase this */ |
5571 | dev_priv->fstart = fstart; | |
5572 | ||
5573 | dev_priv->max_delay = fmax; | |
f97108d1 JB |
5574 | dev_priv->min_delay = fmin; |
5575 | dev_priv->cur_delay = fstart; | |
5576 | ||
7648fa99 JB |
5577 | DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin, |
5578 | fstart); | |
5579 | ||
f97108d1 JB |
5580 | I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); |
5581 | ||
5582 | /* | |
5583 | * Interrupts will be enabled in ironlake_irq_postinstall | |
5584 | */ | |
5585 | ||
5586 | I915_WRITE(VIDSTART, vstart); | |
5587 | POSTING_READ(VIDSTART); | |
5588 | ||
5589 | rgvmodectl |= MEMMODE_SWMODE_EN; | |
5590 | I915_WRITE(MEMMODECTL, rgvmodectl); | |
5591 | ||
481b6af3 | 5592 | if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) |
913d8d11 | 5593 | DRM_ERROR("stuck trying to change perf mode\n"); |
f97108d1 JB |
5594 | msleep(1); |
5595 | ||
7648fa99 | 5596 | ironlake_set_drps(dev, fstart); |
f97108d1 | 5597 | |
7648fa99 JB |
5598 | dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + |
5599 | I915_READ(0x112e0); | |
5600 | dev_priv->last_time1 = jiffies_to_msecs(jiffies); | |
5601 | dev_priv->last_count2 = I915_READ(0x112f4); | |
5602 | getrawmonotonic(&dev_priv->last_time2); | |
f97108d1 JB |
5603 | } |
5604 | ||
5605 | void ironlake_disable_drps(struct drm_device *dev) | |
5606 | { | |
5607 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7648fa99 | 5608 | u16 rgvswctl = I915_READ16(MEMSWCTL); |
f97108d1 JB |
5609 | |
5610 | /* Ack interrupts, disable EFC interrupt */ | |
5611 | I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); | |
5612 | I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); | |
5613 | I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); | |
5614 | I915_WRITE(DEIIR, DE_PCU_EVENT); | |
5615 | I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); | |
5616 | ||
5617 | /* Go back to the starting frequency */ | |
7648fa99 | 5618 | ironlake_set_drps(dev, dev_priv->fstart); |
f97108d1 JB |
5619 | msleep(1); |
5620 | rgvswctl |= MEMCTL_CMD_STS; | |
5621 | I915_WRITE(MEMSWCTL, rgvswctl); | |
5622 | msleep(1); | |
5623 | ||
5624 | } | |
5625 | ||
7648fa99 JB |
5626 | static unsigned long intel_pxfreq(u32 vidfreq) |
5627 | { | |
5628 | unsigned long freq; | |
5629 | int div = (vidfreq & 0x3f0000) >> 16; | |
5630 | int post = (vidfreq & 0x3000) >> 12; | |
5631 | int pre = (vidfreq & 0x7); | |
5632 | ||
5633 | if (!pre) | |
5634 | return 0; | |
5635 | ||
5636 | freq = ((div * 133333) / ((1<<post) * pre)); | |
5637 | ||
5638 | return freq; | |
5639 | } | |
5640 | ||
5641 | void intel_init_emon(struct drm_device *dev) | |
5642 | { | |
5643 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5644 | u32 lcfuse; | |
5645 | u8 pxw[16]; | |
5646 | int i; | |
5647 | ||
5648 | /* Disable to program */ | |
5649 | I915_WRITE(ECR, 0); | |
5650 | POSTING_READ(ECR); | |
5651 | ||
5652 | /* Program energy weights for various events */ | |
5653 | I915_WRITE(SDEW, 0x15040d00); | |
5654 | I915_WRITE(CSIEW0, 0x007f0000); | |
5655 | I915_WRITE(CSIEW1, 0x1e220004); | |
5656 | I915_WRITE(CSIEW2, 0x04000004); | |
5657 | ||
5658 | for (i = 0; i < 5; i++) | |
5659 | I915_WRITE(PEW + (i * 4), 0); | |
5660 | for (i = 0; i < 3; i++) | |
5661 | I915_WRITE(DEW + (i * 4), 0); | |
5662 | ||
5663 | /* Program P-state weights to account for frequency power adjustment */ | |
5664 | for (i = 0; i < 16; i++) { | |
5665 | u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4)); | |
5666 | unsigned long freq = intel_pxfreq(pxvidfreq); | |
5667 | unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> | |
5668 | PXVFREQ_PX_SHIFT; | |
5669 | unsigned long val; | |
5670 | ||
5671 | val = vid * vid; | |
5672 | val *= (freq / 1000); | |
5673 | val *= 255; | |
5674 | val /= (127*127*900); | |
5675 | if (val > 0xff) | |
5676 | DRM_ERROR("bad pxval: %ld\n", val); | |
5677 | pxw[i] = val; | |
5678 | } | |
5679 | /* Render standby states get 0 weight */ | |
5680 | pxw[14] = 0; | |
5681 | pxw[15] = 0; | |
5682 | ||
5683 | for (i = 0; i < 4; i++) { | |
5684 | u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | | |
5685 | (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); | |
5686 | I915_WRITE(PXW + (i * 4), val); | |
5687 | } | |
5688 | ||
5689 | /* Adjust magic regs to magic values (more experimental results) */ | |
5690 | I915_WRITE(OGW0, 0); | |
5691 | I915_WRITE(OGW1, 0); | |
5692 | I915_WRITE(EG0, 0x00007f00); | |
5693 | I915_WRITE(EG1, 0x0000000e); | |
5694 | I915_WRITE(EG2, 0x000e0000); | |
5695 | I915_WRITE(EG3, 0x68000300); | |
5696 | I915_WRITE(EG4, 0x42000000); | |
5697 | I915_WRITE(EG5, 0x00140031); | |
5698 | I915_WRITE(EG6, 0); | |
5699 | I915_WRITE(EG7, 0); | |
5700 | ||
5701 | for (i = 0; i < 8; i++) | |
5702 | I915_WRITE(PXWL + (i * 4), 0); | |
5703 | ||
5704 | /* Enable PMON + select events */ | |
5705 | I915_WRITE(ECR, 0x80000019); | |
5706 | ||
5707 | lcfuse = I915_READ(LCFUSE02); | |
5708 | ||
5709 | dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK); | |
5710 | } | |
5711 | ||
652c393a JB |
5712 | void intel_init_clock_gating(struct drm_device *dev) |
5713 | { | |
5714 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5715 | ||
5716 | /* | |
5717 | * Disable clock gating reported to work incorrectly according to the | |
5718 | * specs, but enable as much else as we can. | |
5719 | */ | |
bad720ff | 5720 | if (HAS_PCH_SPLIT(dev)) { |
8956c8bb EA |
5721 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; |
5722 | ||
5723 | if (IS_IRONLAKE(dev)) { | |
5724 | /* Required for FBC */ | |
5725 | dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE; | |
5726 | /* Required for CxSR */ | |
5727 | dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE; | |
5728 | ||
5729 | I915_WRITE(PCH_3DCGDIS0, | |
5730 | MARIUNIT_CLOCK_GATE_DISABLE | | |
5731 | SVSMUNIT_CLOCK_GATE_DISABLE); | |
5732 | } | |
5733 | ||
5734 | I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); | |
7f8a8569 ZW |
5735 | |
5736 | /* | |
5737 | * According to the spec the following bits should be set in | |
5738 | * order to enable memory self-refresh | |
5739 | * The bit 22/21 of 0x42004 | |
5740 | * The bit 5 of 0x42020 | |
5741 | * The bit 15 of 0x45000 | |
5742 | */ | |
5743 | if (IS_IRONLAKE(dev)) { | |
5744 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
5745 | (I915_READ(ILK_DISPLAY_CHICKEN2) | | |
5746 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); | |
5747 | I915_WRITE(ILK_DSPCLK_GATE, | |
5748 | (I915_READ(ILK_DSPCLK_GATE) | | |
5749 | ILK_DPARB_CLK_GATE)); | |
5750 | I915_WRITE(DISP_ARB_CTL, | |
5751 | (I915_READ(DISP_ARB_CTL) | | |
5752 | DISP_FBC_WM_DIS)); | |
5753 | } | |
b52eb4dc ZY |
5754 | /* |
5755 | * Based on the document from hardware guys the following bits | |
5756 | * should be set unconditionally in order to enable FBC. | |
5757 | * The bit 22 of 0x42000 | |
5758 | * The bit 22 of 0x42004 | |
5759 | * The bit 7,8,9 of 0x42020. | |
5760 | */ | |
5761 | if (IS_IRONLAKE_M(dev)) { | |
5762 | I915_WRITE(ILK_DISPLAY_CHICKEN1, | |
5763 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
5764 | ILK_FBCQ_DIS); | |
5765 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
5766 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
5767 | ILK_DPARB_GATE); | |
5768 | I915_WRITE(ILK_DSPCLK_GATE, | |
5769 | I915_READ(ILK_DSPCLK_GATE) | | |
5770 | ILK_DPFC_DIS1 | | |
5771 | ILK_DPFC_DIS2 | | |
5772 | ILK_CLK_FBC); | |
5773 | } | |
bc41606a | 5774 | return; |
c03342fa | 5775 | } else if (IS_G4X(dev)) { |
652c393a JB |
5776 | uint32_t dspclk_gate; |
5777 | I915_WRITE(RENCLK_GATE_D1, 0); | |
5778 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | | |
5779 | GS_UNIT_CLOCK_GATE_DISABLE | | |
5780 | CL_UNIT_CLOCK_GATE_DISABLE); | |
5781 | I915_WRITE(RAMCLK_GATE_D, 0); | |
5782 | dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | | |
5783 | OVRUNIT_CLOCK_GATE_DISABLE | | |
5784 | OVCUNIT_CLOCK_GATE_DISABLE; | |
5785 | if (IS_GM45(dev)) | |
5786 | dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; | |
5787 | I915_WRITE(DSPCLK_GATE_D, dspclk_gate); | |
5788 | } else if (IS_I965GM(dev)) { | |
5789 | I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); | |
5790 | I915_WRITE(RENCLK_GATE_D2, 0); | |
5791 | I915_WRITE(DSPCLK_GATE_D, 0); | |
5792 | I915_WRITE(RAMCLK_GATE_D, 0); | |
5793 | I915_WRITE16(DEUC, 0); | |
5794 | } else if (IS_I965G(dev)) { | |
5795 | I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | | |
5796 | I965_RCC_CLOCK_GATE_DISABLE | | |
5797 | I965_RCPB_CLOCK_GATE_DISABLE | | |
5798 | I965_ISC_CLOCK_GATE_DISABLE | | |
5799 | I965_FBC_CLOCK_GATE_DISABLE); | |
5800 | I915_WRITE(RENCLK_GATE_D2, 0); | |
5801 | } else if (IS_I9XX(dev)) { | |
5802 | u32 dstate = I915_READ(D_STATE); | |
5803 | ||
5804 | dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | | |
5805 | DSTATE_DOT_CLOCK_GATING; | |
5806 | I915_WRITE(D_STATE, dstate); | |
f0f8a9ce | 5807 | } else if (IS_I85X(dev) || IS_I865G(dev)) { |
652c393a JB |
5808 | I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); |
5809 | } else if (IS_I830(dev)) { | |
5810 | I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); | |
5811 | } | |
97f5ab66 JB |
5812 | |
5813 | /* | |
5814 | * GPU can automatically power down the render unit if given a page | |
5815 | * to save state. | |
5816 | */ | |
aa40d6bb ZN |
5817 | if (IS_IRONLAKE_M(dev)) { |
5818 | if (dev_priv->renderctx == NULL) | |
5819 | dev_priv->renderctx = intel_alloc_context_page(dev); | |
5820 | if (dev_priv->renderctx) { | |
5821 | struct drm_i915_gem_object *obj_priv; | |
5822 | obj_priv = to_intel_bo(dev_priv->renderctx); | |
5823 | if (obj_priv) { | |
5824 | BEGIN_LP_RING(4); | |
5825 | OUT_RING(MI_SET_CONTEXT); | |
5826 | OUT_RING(obj_priv->gtt_offset | | |
5827 | MI_MM_SPACE_GTT | | |
5828 | MI_SAVE_EXT_STATE_EN | | |
5829 | MI_RESTORE_EXT_STATE_EN | | |
5830 | MI_RESTORE_INHIBIT); | |
5831 | OUT_RING(MI_NOOP); | |
5832 | OUT_RING(MI_FLUSH); | |
5833 | ADVANCE_LP_RING(); | |
5834 | } | |
bc41606a | 5835 | } else |
aa40d6bb | 5836 | DRM_DEBUG_KMS("Failed to allocate render context." |
bc41606a | 5837 | "Disable RC6\n"); |
aa40d6bb ZN |
5838 | } |
5839 | ||
1d3c36ad | 5840 | if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) { |
9ea8d059 | 5841 | struct drm_i915_gem_object *obj_priv = NULL; |
97f5ab66 | 5842 | |
7e8b60fa | 5843 | if (dev_priv->pwrctx) { |
23010e43 | 5844 | obj_priv = to_intel_bo(dev_priv->pwrctx); |
7e8b60fa | 5845 | } else { |
9ea8d059 | 5846 | struct drm_gem_object *pwrctx; |
97f5ab66 | 5847 | |
aa40d6bb | 5848 | pwrctx = intel_alloc_context_page(dev); |
9ea8d059 CW |
5849 | if (pwrctx) { |
5850 | dev_priv->pwrctx = pwrctx; | |
23010e43 | 5851 | obj_priv = to_intel_bo(pwrctx); |
7e8b60fa | 5852 | } |
7e8b60fa | 5853 | } |
97f5ab66 | 5854 | |
9ea8d059 CW |
5855 | if (obj_priv) { |
5856 | I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN); | |
5857 | I915_WRITE(MCHBAR_RENDER_STANDBY, | |
5858 | I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT); | |
5859 | } | |
97f5ab66 | 5860 | } |
652c393a JB |
5861 | } |
5862 | ||
e70236a8 JB |
5863 | /* Set up chip specific display functions */ |
5864 | static void intel_init_display(struct drm_device *dev) | |
5865 | { | |
5866 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5867 | ||
5868 | /* We always want a DPMS function */ | |
bad720ff | 5869 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 5870 | dev_priv->display.dpms = ironlake_crtc_dpms; |
e70236a8 JB |
5871 | else |
5872 | dev_priv->display.dpms = i9xx_crtc_dpms; | |
5873 | ||
ee5382ae | 5874 | if (I915_HAS_FBC(dev)) { |
b52eb4dc ZY |
5875 | if (IS_IRONLAKE_M(dev)) { |
5876 | dev_priv->display.fbc_enabled = ironlake_fbc_enabled; | |
5877 | dev_priv->display.enable_fbc = ironlake_enable_fbc; | |
5878 | dev_priv->display.disable_fbc = ironlake_disable_fbc; | |
5879 | } else if (IS_GM45(dev)) { | |
74dff282 JB |
5880 | dev_priv->display.fbc_enabled = g4x_fbc_enabled; |
5881 | dev_priv->display.enable_fbc = g4x_enable_fbc; | |
5882 | dev_priv->display.disable_fbc = g4x_disable_fbc; | |
8d06a1e1 | 5883 | } else if (IS_I965GM(dev)) { |
e70236a8 JB |
5884 | dev_priv->display.fbc_enabled = i8xx_fbc_enabled; |
5885 | dev_priv->display.enable_fbc = i8xx_enable_fbc; | |
5886 | dev_priv->display.disable_fbc = i8xx_disable_fbc; | |
5887 | } | |
74dff282 | 5888 | /* 855GM needs testing */ |
e70236a8 JB |
5889 | } |
5890 | ||
5891 | /* Returns the core display clock speed */ | |
f2b115e6 | 5892 | if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev))) |
e70236a8 JB |
5893 | dev_priv->display.get_display_clock_speed = |
5894 | i945_get_display_clock_speed; | |
5895 | else if (IS_I915G(dev)) | |
5896 | dev_priv->display.get_display_clock_speed = | |
5897 | i915_get_display_clock_speed; | |
f2b115e6 | 5898 | else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev)) |
e70236a8 JB |
5899 | dev_priv->display.get_display_clock_speed = |
5900 | i9xx_misc_get_display_clock_speed; | |
5901 | else if (IS_I915GM(dev)) | |
5902 | dev_priv->display.get_display_clock_speed = | |
5903 | i915gm_get_display_clock_speed; | |
5904 | else if (IS_I865G(dev)) | |
5905 | dev_priv->display.get_display_clock_speed = | |
5906 | i865_get_display_clock_speed; | |
f0f8a9ce | 5907 | else if (IS_I85X(dev)) |
e70236a8 JB |
5908 | dev_priv->display.get_display_clock_speed = |
5909 | i855_get_display_clock_speed; | |
5910 | else /* 852, 830 */ | |
5911 | dev_priv->display.get_display_clock_speed = | |
5912 | i830_get_display_clock_speed; | |
5913 | ||
5914 | /* For FIFO watermark updates */ | |
7f8a8569 ZW |
5915 | if (HAS_PCH_SPLIT(dev)) { |
5916 | if (IS_IRONLAKE(dev)) { | |
5917 | if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK) | |
5918 | dev_priv->display.update_wm = ironlake_update_wm; | |
5919 | else { | |
5920 | DRM_DEBUG_KMS("Failed to get proper latency. " | |
5921 | "Disable CxSR\n"); | |
5922 | dev_priv->display.update_wm = NULL; | |
5923 | } | |
5924 | } else | |
5925 | dev_priv->display.update_wm = NULL; | |
5926 | } else if (IS_PINEVIEW(dev)) { | |
d4294342 | 5927 | if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), |
95534263 | 5928 | dev_priv->is_ddr3, |
d4294342 ZY |
5929 | dev_priv->fsb_freq, |
5930 | dev_priv->mem_freq)) { | |
5931 | DRM_INFO("failed to find known CxSR latency " | |
95534263 | 5932 | "(found ddr%s fsb freq %d, mem freq %d), " |
d4294342 | 5933 | "disabling CxSR\n", |
95534263 | 5934 | (dev_priv->is_ddr3 == 1) ? "3": "2", |
d4294342 ZY |
5935 | dev_priv->fsb_freq, dev_priv->mem_freq); |
5936 | /* Disable CxSR and never update its watermark again */ | |
5937 | pineview_disable_cxsr(dev); | |
5938 | dev_priv->display.update_wm = NULL; | |
5939 | } else | |
5940 | dev_priv->display.update_wm = pineview_update_wm; | |
5941 | } else if (IS_G4X(dev)) | |
e70236a8 JB |
5942 | dev_priv->display.update_wm = g4x_update_wm; |
5943 | else if (IS_I965G(dev)) | |
5944 | dev_priv->display.update_wm = i965_update_wm; | |
8f4695ed | 5945 | else if (IS_I9XX(dev)) { |
e70236a8 JB |
5946 | dev_priv->display.update_wm = i9xx_update_wm; |
5947 | dev_priv->display.get_fifo_size = i9xx_get_fifo_size; | |
8f4695ed AJ |
5948 | } else if (IS_I85X(dev)) { |
5949 | dev_priv->display.update_wm = i9xx_update_wm; | |
5950 | dev_priv->display.get_fifo_size = i85x_get_fifo_size; | |
e70236a8 | 5951 | } else { |
8f4695ed AJ |
5952 | dev_priv->display.update_wm = i830_update_wm; |
5953 | if (IS_845G(dev)) | |
e70236a8 JB |
5954 | dev_priv->display.get_fifo_size = i845_get_fifo_size; |
5955 | else | |
5956 | dev_priv->display.get_fifo_size = i830_get_fifo_size; | |
e70236a8 JB |
5957 | } |
5958 | } | |
5959 | ||
b690e96c JB |
5960 | /* |
5961 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
5962 | * resume, or other times. This quirk makes sure that's the case for | |
5963 | * affected systems. | |
5964 | */ | |
5965 | static void quirk_pipea_force (struct drm_device *dev) | |
5966 | { | |
5967 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5968 | ||
5969 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
5970 | DRM_DEBUG_DRIVER("applying pipe a force quirk\n"); | |
5971 | } | |
5972 | ||
5973 | struct intel_quirk { | |
5974 | int device; | |
5975 | int subsystem_vendor; | |
5976 | int subsystem_device; | |
5977 | void (*hook)(struct drm_device *dev); | |
5978 | }; | |
5979 | ||
5980 | struct intel_quirk intel_quirks[] = { | |
5981 | /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */ | |
5982 | { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force }, | |
5983 | /* HP Mini needs pipe A force quirk (LP: #322104) */ | |
5984 | { 0x27ae,0x103c, 0x361a, quirk_pipea_force }, | |
5985 | ||
5986 | /* Thinkpad R31 needs pipe A force quirk */ | |
5987 | { 0x3577, 0x1014, 0x0505, quirk_pipea_force }, | |
5988 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ | |
5989 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
5990 | ||
5991 | /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */ | |
5992 | { 0x3577, 0x1014, 0x0513, quirk_pipea_force }, | |
5993 | /* ThinkPad X40 needs pipe A force quirk */ | |
5994 | ||
5995 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ | |
5996 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
5997 | ||
5998 | /* 855 & before need to leave pipe A & dpll A up */ | |
5999 | { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
6000 | { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
6001 | }; | |
6002 | ||
6003 | static void intel_init_quirks(struct drm_device *dev) | |
6004 | { | |
6005 | struct pci_dev *d = dev->pdev; | |
6006 | int i; | |
6007 | ||
6008 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
6009 | struct intel_quirk *q = &intel_quirks[i]; | |
6010 | ||
6011 | if (d->device == q->device && | |
6012 | (d->subsystem_vendor == q->subsystem_vendor || | |
6013 | q->subsystem_vendor == PCI_ANY_ID) && | |
6014 | (d->subsystem_device == q->subsystem_device || | |
6015 | q->subsystem_device == PCI_ANY_ID)) | |
6016 | q->hook(dev); | |
6017 | } | |
6018 | } | |
6019 | ||
9cce37f4 JB |
6020 | /* Disable the VGA plane that we never use */ |
6021 | static void i915_disable_vga(struct drm_device *dev) | |
6022 | { | |
6023 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6024 | u8 sr1; | |
6025 | u32 vga_reg; | |
6026 | ||
6027 | if (HAS_PCH_SPLIT(dev)) | |
6028 | vga_reg = CPU_VGACNTRL; | |
6029 | else | |
6030 | vga_reg = VGACNTRL; | |
6031 | ||
6032 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
6033 | outb(1, VGA_SR_INDEX); | |
6034 | sr1 = inb(VGA_SR_DATA); | |
6035 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
6036 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
6037 | udelay(300); | |
6038 | ||
6039 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); | |
6040 | POSTING_READ(vga_reg); | |
6041 | } | |
6042 | ||
79e53945 JB |
6043 | void intel_modeset_init(struct drm_device *dev) |
6044 | { | |
652c393a | 6045 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 JB |
6046 | int i; |
6047 | ||
6048 | drm_mode_config_init(dev); | |
6049 | ||
6050 | dev->mode_config.min_width = 0; | |
6051 | dev->mode_config.min_height = 0; | |
6052 | ||
6053 | dev->mode_config.funcs = (void *)&intel_mode_funcs; | |
6054 | ||
b690e96c JB |
6055 | intel_init_quirks(dev); |
6056 | ||
e70236a8 JB |
6057 | intel_init_display(dev); |
6058 | ||
79e53945 JB |
6059 | if (IS_I965G(dev)) { |
6060 | dev->mode_config.max_width = 8192; | |
6061 | dev->mode_config.max_height = 8192; | |
5e4d6fa7 KP |
6062 | } else if (IS_I9XX(dev)) { |
6063 | dev->mode_config.max_width = 4096; | |
6064 | dev->mode_config.max_height = 4096; | |
79e53945 JB |
6065 | } else { |
6066 | dev->mode_config.max_width = 2048; | |
6067 | dev->mode_config.max_height = 2048; | |
6068 | } | |
6069 | ||
6070 | /* set memory base */ | |
6071 | if (IS_I9XX(dev)) | |
6072 | dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2); | |
6073 | else | |
6074 | dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0); | |
6075 | ||
6076 | if (IS_MOBILE(dev) || IS_I9XX(dev)) | |
a3524f1b | 6077 | dev_priv->num_pipe = 2; |
79e53945 | 6078 | else |
a3524f1b | 6079 | dev_priv->num_pipe = 1; |
28c97730 | 6080 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
a3524f1b | 6081 | dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : ""); |
79e53945 | 6082 | |
a3524f1b | 6083 | for (i = 0; i < dev_priv->num_pipe; i++) { |
79e53945 JB |
6084 | intel_crtc_init(dev, i); |
6085 | } | |
6086 | ||
6087 | intel_setup_outputs(dev); | |
652c393a JB |
6088 | |
6089 | intel_init_clock_gating(dev); | |
6090 | ||
9cce37f4 JB |
6091 | /* Just disable it once at startup */ |
6092 | i915_disable_vga(dev); | |
6093 | ||
7648fa99 | 6094 | if (IS_IRONLAKE_M(dev)) { |
f97108d1 | 6095 | ironlake_enable_drps(dev); |
7648fa99 JB |
6096 | intel_init_emon(dev); |
6097 | } | |
f97108d1 | 6098 | |
652c393a JB |
6099 | INIT_WORK(&dev_priv->idle_work, intel_idle_update); |
6100 | setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer, | |
6101 | (unsigned long)dev); | |
02e792fb DV |
6102 | |
6103 | intel_setup_overlay(dev); | |
79e53945 JB |
6104 | } |
6105 | ||
6106 | void intel_modeset_cleanup(struct drm_device *dev) | |
6107 | { | |
652c393a JB |
6108 | struct drm_i915_private *dev_priv = dev->dev_private; |
6109 | struct drm_crtc *crtc; | |
6110 | struct intel_crtc *intel_crtc; | |
6111 | ||
6112 | mutex_lock(&dev->struct_mutex); | |
6113 | ||
eb1f8e4f | 6114 | drm_kms_helper_poll_fini(dev); |
38651674 DA |
6115 | intel_fbdev_fini(dev); |
6116 | ||
652c393a JB |
6117 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
6118 | /* Skip inactive CRTCs */ | |
6119 | if (!crtc->fb) | |
6120 | continue; | |
6121 | ||
6122 | intel_crtc = to_intel_crtc(crtc); | |
3dec0095 | 6123 | intel_increase_pllclock(crtc); |
652c393a JB |
6124 | } |
6125 | ||
e70236a8 JB |
6126 | if (dev_priv->display.disable_fbc) |
6127 | dev_priv->display.disable_fbc(dev); | |
6128 | ||
aa40d6bb ZN |
6129 | if (dev_priv->renderctx) { |
6130 | struct drm_i915_gem_object *obj_priv; | |
6131 | ||
6132 | obj_priv = to_intel_bo(dev_priv->renderctx); | |
6133 | I915_WRITE(CCID, obj_priv->gtt_offset &~ CCID_EN); | |
6134 | I915_READ(CCID); | |
6135 | i915_gem_object_unpin(dev_priv->renderctx); | |
6136 | drm_gem_object_unreference(dev_priv->renderctx); | |
6137 | } | |
6138 | ||
97f5ab66 | 6139 | if (dev_priv->pwrctx) { |
c1b5dea0 KH |
6140 | struct drm_i915_gem_object *obj_priv; |
6141 | ||
23010e43 | 6142 | obj_priv = to_intel_bo(dev_priv->pwrctx); |
c1b5dea0 KH |
6143 | I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN); |
6144 | I915_READ(PWRCTXA); | |
97f5ab66 JB |
6145 | i915_gem_object_unpin(dev_priv->pwrctx); |
6146 | drm_gem_object_unreference(dev_priv->pwrctx); | |
6147 | } | |
6148 | ||
f97108d1 JB |
6149 | if (IS_IRONLAKE_M(dev)) |
6150 | ironlake_disable_drps(dev); | |
6151 | ||
69341a5e KH |
6152 | mutex_unlock(&dev->struct_mutex); |
6153 | ||
6c0d9350 DV |
6154 | /* Disable the irq before mode object teardown, for the irq might |
6155 | * enqueue unpin/hotplug work. */ | |
6156 | drm_irq_uninstall(dev); | |
6157 | cancel_work_sync(&dev_priv->hotplug_work); | |
6158 | ||
3dec0095 DV |
6159 | /* Shut off idle work before the crtcs get freed. */ |
6160 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
6161 | intel_crtc = to_intel_crtc(crtc); | |
6162 | del_timer_sync(&intel_crtc->idle_timer); | |
6163 | } | |
6164 | del_timer_sync(&dev_priv->idle_timer); | |
6165 | cancel_work_sync(&dev_priv->idle_work); | |
6166 | ||
79e53945 JB |
6167 | drm_mode_config_cleanup(dev); |
6168 | } | |
6169 | ||
f1c79df3 ZW |
6170 | /* |
6171 | * Return which encoder is currently attached for connector. | |
6172 | */ | |
df0e9248 | 6173 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 6174 | { |
df0e9248 CW |
6175 | return &intel_attached_encoder(connector)->base; |
6176 | } | |
f1c79df3 | 6177 | |
df0e9248 CW |
6178 | void intel_connector_attach_encoder(struct intel_connector *connector, |
6179 | struct intel_encoder *encoder) | |
6180 | { | |
6181 | connector->encoder = encoder; | |
6182 | drm_mode_connector_attach_encoder(&connector->base, | |
6183 | &encoder->base); | |
79e53945 | 6184 | } |
28d52043 DA |
6185 | |
6186 | /* | |
6187 | * set vga decode state - true == enable VGA decode | |
6188 | */ | |
6189 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
6190 | { | |
6191 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6192 | u16 gmch_ctrl; | |
6193 | ||
6194 | pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl); | |
6195 | if (state) | |
6196 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
6197 | else | |
6198 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
6199 | pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl); | |
6200 | return 0; | |
6201 | } |