]>
Commit | Line | Data |
---|---|---|
79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
5d723d7a | 37 | #include "intel_frontbuffer.h" |
760285e7 | 38 | #include <drm/i915_drm.h> |
79e53945 | 39 | #include "i915_drv.h" |
db18b6a6 | 40 | #include "intel_dsi.h" |
e5510fac | 41 | #include "i915_trace.h" |
319c1d42 | 42 | #include <drm/drm_atomic.h> |
c196e1d6 | 43 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
44 | #include <drm/drm_dp_helper.h> |
45 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
46 | #include <drm/drm_plane_helper.h> |
47 | #include <drm/drm_rect.h> | |
c0f372b3 | 48 | #include <linux/dma_remapping.h> |
fd8e058a | 49 | #include <linux/reservation.h> |
79e53945 | 50 | |
5a21b665 DV |
51 | static bool is_mmio_work(struct intel_flip_work *work) |
52 | { | |
53 | return work->mmio_work.func; | |
54 | } | |
55 | ||
465c120c | 56 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 57 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
58 | DRM_FORMAT_C8, |
59 | DRM_FORMAT_RGB565, | |
465c120c | 60 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 61 | DRM_FORMAT_XRGB8888, |
465c120c MR |
62 | }; |
63 | ||
64 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 65 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
66 | DRM_FORMAT_C8, |
67 | DRM_FORMAT_RGB565, | |
68 | DRM_FORMAT_XRGB8888, | |
69 | DRM_FORMAT_XBGR8888, | |
70 | DRM_FORMAT_XRGB2101010, | |
71 | DRM_FORMAT_XBGR2101010, | |
72 | }; | |
73 | ||
74 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
75 | DRM_FORMAT_C8, |
76 | DRM_FORMAT_RGB565, | |
77 | DRM_FORMAT_XRGB8888, | |
465c120c | 78 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 79 | DRM_FORMAT_ARGB8888, |
465c120c MR |
80 | DRM_FORMAT_ABGR8888, |
81 | DRM_FORMAT_XRGB2101010, | |
465c120c | 82 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
83 | DRM_FORMAT_YUYV, |
84 | DRM_FORMAT_YVYU, | |
85 | DRM_FORMAT_UYVY, | |
86 | DRM_FORMAT_VYUY, | |
465c120c MR |
87 | }; |
88 | ||
3d7d6510 MR |
89 | /* Cursor formats */ |
90 | static const uint32_t intel_cursor_formats[] = { | |
91 | DRM_FORMAT_ARGB8888, | |
92 | }; | |
93 | ||
f1f644dc | 94 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 95 | struct intel_crtc_state *pipe_config); |
18442d08 | 96 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 97 | struct intel_crtc_state *pipe_config); |
f1f644dc | 98 | |
eb1bfe80 JB |
99 | static int intel_framebuffer_init(struct drm_device *dev, |
100 | struct intel_framebuffer *ifb, | |
101 | struct drm_mode_fb_cmd2 *mode_cmd, | |
102 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
103 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
104 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
bc58be60 | 105 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc); |
29407aab | 106 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
107 | struct intel_link_m_n *m_n, |
108 | struct intel_link_m_n *m2_n2); | |
29407aab | 109 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 | 110 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
391bf048 | 111 | static void haswell_set_pipemisc(struct drm_crtc *crtc); |
d288f65f | 112 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 113 | const struct intel_crtc_state *pipe_config); |
d288f65f | 114 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 115 | const struct intel_crtc_state *pipe_config); |
5a21b665 DV |
116 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
117 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
549e2bfb CK |
118 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
119 | struct intel_crtc_state *crtc_state); | |
bfd16b2a ML |
120 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
121 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
122 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
043e9bda | 123 | static void intel_modeset_setup_hw_state(struct drm_device *dev); |
2622a081 | 124 | static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc); |
4e5ca60f | 125 | static int ilk_max_pixel_rate(struct drm_atomic_state *state); |
324513c0 | 126 | static int bxt_calc_cdclk(int max_pixclk); |
e7457a9a | 127 | |
d4906093 | 128 | struct intel_limit { |
4c5def93 ACO |
129 | struct { |
130 | int min, max; | |
131 | } dot, vco, n, m, m1, m2, p, p1; | |
132 | ||
133 | struct { | |
134 | int dot_limit; | |
135 | int p2_slow, p2_fast; | |
136 | } p2; | |
d4906093 | 137 | }; |
79e53945 | 138 | |
bfa7df01 VS |
139 | /* returns HPLL frequency in kHz */ |
140 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) | |
141 | { | |
142 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
143 | ||
144 | /* Obtain SKU information */ | |
145 | mutex_lock(&dev_priv->sb_lock); | |
146 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
147 | CCK_FUSE_HPLL_FREQ_MASK; | |
148 | mutex_unlock(&dev_priv->sb_lock); | |
149 | ||
150 | return vco_freq[hpll_freq] * 1000; | |
151 | } | |
152 | ||
c30fec65 VS |
153 | int vlv_get_cck_clock(struct drm_i915_private *dev_priv, |
154 | const char *name, u32 reg, int ref_freq) | |
bfa7df01 VS |
155 | { |
156 | u32 val; | |
157 | int divider; | |
158 | ||
bfa7df01 VS |
159 | mutex_lock(&dev_priv->sb_lock); |
160 | val = vlv_cck_read(dev_priv, reg); | |
161 | mutex_unlock(&dev_priv->sb_lock); | |
162 | ||
163 | divider = val & CCK_FREQUENCY_VALUES; | |
164 | ||
165 | WARN((val & CCK_FREQUENCY_STATUS) != | |
166 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
167 | "%s change in progress\n", name); | |
168 | ||
c30fec65 VS |
169 | return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); |
170 | } | |
171 | ||
172 | static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, | |
173 | const char *name, u32 reg) | |
174 | { | |
175 | if (dev_priv->hpll_freq == 0) | |
176 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
177 | ||
178 | return vlv_get_cck_clock(dev_priv, name, reg, | |
179 | dev_priv->hpll_freq); | |
bfa7df01 VS |
180 | } |
181 | ||
e7dc33f3 VS |
182 | static int |
183 | intel_pch_rawclk(struct drm_i915_private *dev_priv) | |
d2acd215 | 184 | { |
e7dc33f3 VS |
185 | return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; |
186 | } | |
d2acd215 | 187 | |
e7dc33f3 VS |
188 | static int |
189 | intel_vlv_hrawclk(struct drm_i915_private *dev_priv) | |
190 | { | |
19ab4ed3 | 191 | /* RAWCLK_FREQ_VLV register updated from power well code */ |
35d38d1f VS |
192 | return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", |
193 | CCK_DISPLAY_REF_CLOCK_CONTROL); | |
d2acd215 DV |
194 | } |
195 | ||
e7dc33f3 VS |
196 | static int |
197 | intel_g4x_hrawclk(struct drm_i915_private *dev_priv) | |
79e50a4f | 198 | { |
79e50a4f JN |
199 | uint32_t clkcfg; |
200 | ||
e7dc33f3 | 201 | /* hrawclock is 1/4 the FSB frequency */ |
79e50a4f JN |
202 | clkcfg = I915_READ(CLKCFG); |
203 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
204 | case CLKCFG_FSB_400: | |
e7dc33f3 | 205 | return 100000; |
79e50a4f | 206 | case CLKCFG_FSB_533: |
e7dc33f3 | 207 | return 133333; |
79e50a4f | 208 | case CLKCFG_FSB_667: |
e7dc33f3 | 209 | return 166667; |
79e50a4f | 210 | case CLKCFG_FSB_800: |
e7dc33f3 | 211 | return 200000; |
79e50a4f | 212 | case CLKCFG_FSB_1067: |
e7dc33f3 | 213 | return 266667; |
79e50a4f | 214 | case CLKCFG_FSB_1333: |
e7dc33f3 | 215 | return 333333; |
79e50a4f JN |
216 | /* these two are just a guess; one of them might be right */ |
217 | case CLKCFG_FSB_1600: | |
218 | case CLKCFG_FSB_1600_ALT: | |
e7dc33f3 | 219 | return 400000; |
79e50a4f | 220 | default: |
e7dc33f3 | 221 | return 133333; |
79e50a4f JN |
222 | } |
223 | } | |
224 | ||
19ab4ed3 | 225 | void intel_update_rawclk(struct drm_i915_private *dev_priv) |
e7dc33f3 VS |
226 | { |
227 | if (HAS_PCH_SPLIT(dev_priv)) | |
228 | dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv); | |
229 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
230 | dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv); | |
231 | else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv)) | |
232 | dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv); | |
233 | else | |
234 | return; /* no rawclk on other platforms, or no need to know it */ | |
235 | ||
236 | DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq); | |
237 | } | |
238 | ||
bfa7df01 VS |
239 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
240 | { | |
666a4537 | 241 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
bfa7df01 VS |
242 | return; |
243 | ||
244 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
245 | CCK_CZ_CLOCK_CONTROL); | |
246 | ||
247 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); | |
248 | } | |
249 | ||
021357ac | 250 | static inline u32 /* units of 100MHz */ |
21a727b3 VS |
251 | intel_fdi_link_freq(struct drm_i915_private *dev_priv, |
252 | const struct intel_crtc_state *pipe_config) | |
021357ac | 253 | { |
21a727b3 VS |
254 | if (HAS_DDI(dev_priv)) |
255 | return pipe_config->port_clock; /* SPLL */ | |
256 | else if (IS_GEN5(dev_priv)) | |
257 | return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000; | |
e3b247da | 258 | else |
21a727b3 | 259 | return 270000; |
021357ac CW |
260 | } |
261 | ||
1b6f4958 | 262 | static const struct intel_limit intel_limits_i8xx_dac = { |
0206e353 | 263 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 264 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 265 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
266 | .m = { .min = 96, .max = 140 }, |
267 | .m1 = { .min = 18, .max = 26 }, | |
268 | .m2 = { .min = 6, .max = 16 }, | |
269 | .p = { .min = 4, .max = 128 }, | |
270 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
271 | .p2 = { .dot_limit = 165000, |
272 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
273 | }; |
274 | ||
1b6f4958 | 275 | static const struct intel_limit intel_limits_i8xx_dvo = { |
5d536e28 | 276 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 277 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 278 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
279 | .m = { .min = 96, .max = 140 }, |
280 | .m1 = { .min = 18, .max = 26 }, | |
281 | .m2 = { .min = 6, .max = 16 }, | |
282 | .p = { .min = 4, .max = 128 }, | |
283 | .p1 = { .min = 2, .max = 33 }, | |
284 | .p2 = { .dot_limit = 165000, | |
285 | .p2_slow = 4, .p2_fast = 4 }, | |
286 | }; | |
287 | ||
1b6f4958 | 288 | static const struct intel_limit intel_limits_i8xx_lvds = { |
0206e353 | 289 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 290 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 291 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
292 | .m = { .min = 96, .max = 140 }, |
293 | .m1 = { .min = 18, .max = 26 }, | |
294 | .m2 = { .min = 6, .max = 16 }, | |
295 | .p = { .min = 4, .max = 128 }, | |
296 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
297 | .p2 = { .dot_limit = 165000, |
298 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 299 | }; |
273e27ca | 300 | |
1b6f4958 | 301 | static const struct intel_limit intel_limits_i9xx_sdvo = { |
0206e353 AJ |
302 | .dot = { .min = 20000, .max = 400000 }, |
303 | .vco = { .min = 1400000, .max = 2800000 }, | |
304 | .n = { .min = 1, .max = 6 }, | |
305 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
306 | .m1 = { .min = 8, .max = 18 }, |
307 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
308 | .p = { .min = 5, .max = 80 }, |
309 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
310 | .p2 = { .dot_limit = 200000, |
311 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
312 | }; |
313 | ||
1b6f4958 | 314 | static const struct intel_limit intel_limits_i9xx_lvds = { |
0206e353 AJ |
315 | .dot = { .min = 20000, .max = 400000 }, |
316 | .vco = { .min = 1400000, .max = 2800000 }, | |
317 | .n = { .min = 1, .max = 6 }, | |
318 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
319 | .m1 = { .min = 8, .max = 18 }, |
320 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
321 | .p = { .min = 7, .max = 98 }, |
322 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
323 | .p2 = { .dot_limit = 112000, |
324 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
325 | }; |
326 | ||
273e27ca | 327 | |
1b6f4958 | 328 | static const struct intel_limit intel_limits_g4x_sdvo = { |
273e27ca EA |
329 | .dot = { .min = 25000, .max = 270000 }, |
330 | .vco = { .min = 1750000, .max = 3500000}, | |
331 | .n = { .min = 1, .max = 4 }, | |
332 | .m = { .min = 104, .max = 138 }, | |
333 | .m1 = { .min = 17, .max = 23 }, | |
334 | .m2 = { .min = 5, .max = 11 }, | |
335 | .p = { .min = 10, .max = 30 }, | |
336 | .p1 = { .min = 1, .max = 3}, | |
337 | .p2 = { .dot_limit = 270000, | |
338 | .p2_slow = 10, | |
339 | .p2_fast = 10 | |
044c7c41 | 340 | }, |
e4b36699 KP |
341 | }; |
342 | ||
1b6f4958 | 343 | static const struct intel_limit intel_limits_g4x_hdmi = { |
273e27ca EA |
344 | .dot = { .min = 22000, .max = 400000 }, |
345 | .vco = { .min = 1750000, .max = 3500000}, | |
346 | .n = { .min = 1, .max = 4 }, | |
347 | .m = { .min = 104, .max = 138 }, | |
348 | .m1 = { .min = 16, .max = 23 }, | |
349 | .m2 = { .min = 5, .max = 11 }, | |
350 | .p = { .min = 5, .max = 80 }, | |
351 | .p1 = { .min = 1, .max = 8}, | |
352 | .p2 = { .dot_limit = 165000, | |
353 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
354 | }; |
355 | ||
1b6f4958 | 356 | static const struct intel_limit intel_limits_g4x_single_channel_lvds = { |
273e27ca EA |
357 | .dot = { .min = 20000, .max = 115000 }, |
358 | .vco = { .min = 1750000, .max = 3500000 }, | |
359 | .n = { .min = 1, .max = 3 }, | |
360 | .m = { .min = 104, .max = 138 }, | |
361 | .m1 = { .min = 17, .max = 23 }, | |
362 | .m2 = { .min = 5, .max = 11 }, | |
363 | .p = { .min = 28, .max = 112 }, | |
364 | .p1 = { .min = 2, .max = 8 }, | |
365 | .p2 = { .dot_limit = 0, | |
366 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 367 | }, |
e4b36699 KP |
368 | }; |
369 | ||
1b6f4958 | 370 | static const struct intel_limit intel_limits_g4x_dual_channel_lvds = { |
273e27ca EA |
371 | .dot = { .min = 80000, .max = 224000 }, |
372 | .vco = { .min = 1750000, .max = 3500000 }, | |
373 | .n = { .min = 1, .max = 3 }, | |
374 | .m = { .min = 104, .max = 138 }, | |
375 | .m1 = { .min = 17, .max = 23 }, | |
376 | .m2 = { .min = 5, .max = 11 }, | |
377 | .p = { .min = 14, .max = 42 }, | |
378 | .p1 = { .min = 2, .max = 6 }, | |
379 | .p2 = { .dot_limit = 0, | |
380 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 381 | }, |
e4b36699 KP |
382 | }; |
383 | ||
1b6f4958 | 384 | static const struct intel_limit intel_limits_pineview_sdvo = { |
0206e353 AJ |
385 | .dot = { .min = 20000, .max = 400000}, |
386 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 387 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
388 | .n = { .min = 3, .max = 6 }, |
389 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 390 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
391 | .m1 = { .min = 0, .max = 0 }, |
392 | .m2 = { .min = 0, .max = 254 }, | |
393 | .p = { .min = 5, .max = 80 }, | |
394 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
395 | .p2 = { .dot_limit = 200000, |
396 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
397 | }; |
398 | ||
1b6f4958 | 399 | static const struct intel_limit intel_limits_pineview_lvds = { |
0206e353 AJ |
400 | .dot = { .min = 20000, .max = 400000 }, |
401 | .vco = { .min = 1700000, .max = 3500000 }, | |
402 | .n = { .min = 3, .max = 6 }, | |
403 | .m = { .min = 2, .max = 256 }, | |
404 | .m1 = { .min = 0, .max = 0 }, | |
405 | .m2 = { .min = 0, .max = 254 }, | |
406 | .p = { .min = 7, .max = 112 }, | |
407 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
408 | .p2 = { .dot_limit = 112000, |
409 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
410 | }; |
411 | ||
273e27ca EA |
412 | /* Ironlake / Sandybridge |
413 | * | |
414 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
415 | * the range value for them is (actual_value - 2). | |
416 | */ | |
1b6f4958 | 417 | static const struct intel_limit intel_limits_ironlake_dac = { |
273e27ca EA |
418 | .dot = { .min = 25000, .max = 350000 }, |
419 | .vco = { .min = 1760000, .max = 3510000 }, | |
420 | .n = { .min = 1, .max = 5 }, | |
421 | .m = { .min = 79, .max = 127 }, | |
422 | .m1 = { .min = 12, .max = 22 }, | |
423 | .m2 = { .min = 5, .max = 9 }, | |
424 | .p = { .min = 5, .max = 80 }, | |
425 | .p1 = { .min = 1, .max = 8 }, | |
426 | .p2 = { .dot_limit = 225000, | |
427 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
428 | }; |
429 | ||
1b6f4958 | 430 | static const struct intel_limit intel_limits_ironlake_single_lvds = { |
273e27ca EA |
431 | .dot = { .min = 25000, .max = 350000 }, |
432 | .vco = { .min = 1760000, .max = 3510000 }, | |
433 | .n = { .min = 1, .max = 3 }, | |
434 | .m = { .min = 79, .max = 118 }, | |
435 | .m1 = { .min = 12, .max = 22 }, | |
436 | .m2 = { .min = 5, .max = 9 }, | |
437 | .p = { .min = 28, .max = 112 }, | |
438 | .p1 = { .min = 2, .max = 8 }, | |
439 | .p2 = { .dot_limit = 225000, | |
440 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
441 | }; |
442 | ||
1b6f4958 | 443 | static const struct intel_limit intel_limits_ironlake_dual_lvds = { |
273e27ca EA |
444 | .dot = { .min = 25000, .max = 350000 }, |
445 | .vco = { .min = 1760000, .max = 3510000 }, | |
446 | .n = { .min = 1, .max = 3 }, | |
447 | .m = { .min = 79, .max = 127 }, | |
448 | .m1 = { .min = 12, .max = 22 }, | |
449 | .m2 = { .min = 5, .max = 9 }, | |
450 | .p = { .min = 14, .max = 56 }, | |
451 | .p1 = { .min = 2, .max = 8 }, | |
452 | .p2 = { .dot_limit = 225000, | |
453 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
454 | }; |
455 | ||
273e27ca | 456 | /* LVDS 100mhz refclk limits. */ |
1b6f4958 | 457 | static const struct intel_limit intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
458 | .dot = { .min = 25000, .max = 350000 }, |
459 | .vco = { .min = 1760000, .max = 3510000 }, | |
460 | .n = { .min = 1, .max = 2 }, | |
461 | .m = { .min = 79, .max = 126 }, | |
462 | .m1 = { .min = 12, .max = 22 }, | |
463 | .m2 = { .min = 5, .max = 9 }, | |
464 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 465 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
466 | .p2 = { .dot_limit = 225000, |
467 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
468 | }; |
469 | ||
1b6f4958 | 470 | static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = { |
273e27ca EA |
471 | .dot = { .min = 25000, .max = 350000 }, |
472 | .vco = { .min = 1760000, .max = 3510000 }, | |
473 | .n = { .min = 1, .max = 3 }, | |
474 | .m = { .min = 79, .max = 126 }, | |
475 | .m1 = { .min = 12, .max = 22 }, | |
476 | .m2 = { .min = 5, .max = 9 }, | |
477 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 478 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
479 | .p2 = { .dot_limit = 225000, |
480 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
481 | }; |
482 | ||
1b6f4958 | 483 | static const struct intel_limit intel_limits_vlv = { |
f01b7962 VS |
484 | /* |
485 | * These are the data rate limits (measured in fast clocks) | |
486 | * since those are the strictest limits we have. The fast | |
487 | * clock and actual rate limits are more relaxed, so checking | |
488 | * them would make no difference. | |
489 | */ | |
490 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 491 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 492 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
493 | .m1 = { .min = 2, .max = 3 }, |
494 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 495 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 496 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
497 | }; |
498 | ||
1b6f4958 | 499 | static const struct intel_limit intel_limits_chv = { |
ef9348c8 CML |
500 | /* |
501 | * These are the data rate limits (measured in fast clocks) | |
502 | * since those are the strictest limits we have. The fast | |
503 | * clock and actual rate limits are more relaxed, so checking | |
504 | * them would make no difference. | |
505 | */ | |
506 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 507 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
508 | .n = { .min = 1, .max = 1 }, |
509 | .m1 = { .min = 2, .max = 2 }, | |
510 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
511 | .p1 = { .min = 2, .max = 4 }, | |
512 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
513 | }; | |
514 | ||
1b6f4958 | 515 | static const struct intel_limit intel_limits_bxt = { |
5ab7b0b7 ID |
516 | /* FIXME: find real dot limits */ |
517 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 518 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
519 | .n = { .min = 1, .max = 1 }, |
520 | .m1 = { .min = 2, .max = 2 }, | |
521 | /* FIXME: find real m2 limits */ | |
522 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
523 | .p1 = { .min = 2, .max = 4 }, | |
524 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
525 | }; | |
526 | ||
cdba954e ACO |
527 | static bool |
528 | needs_modeset(struct drm_crtc_state *state) | |
529 | { | |
fc596660 | 530 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
531 | } |
532 | ||
dccbea3b ID |
533 | /* |
534 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
535 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
536 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
537 | * The helpers' return value is the rate of the clock that is fed to the | |
538 | * display engine's pipe which can be the above fast dot clock rate or a | |
539 | * divided-down version of it. | |
540 | */ | |
f2b115e6 | 541 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
9e2c8475 | 542 | static int pnv_calc_dpll_params(int refclk, struct dpll *clock) |
79e53945 | 543 | { |
2177832f SL |
544 | clock->m = clock->m2 + 2; |
545 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 546 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 547 | return 0; |
fb03ac01 VS |
548 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
549 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
550 | |
551 | return clock->dot; | |
2177832f SL |
552 | } |
553 | ||
7429e9d4 DV |
554 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
555 | { | |
556 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
557 | } | |
558 | ||
9e2c8475 | 559 | static int i9xx_calc_dpll_params(int refclk, struct dpll *clock) |
2177832f | 560 | { |
7429e9d4 | 561 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 562 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 563 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 564 | return 0; |
fb03ac01 VS |
565 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
566 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
567 | |
568 | return clock->dot; | |
79e53945 JB |
569 | } |
570 | ||
9e2c8475 | 571 | static int vlv_calc_dpll_params(int refclk, struct dpll *clock) |
589eca67 ID |
572 | { |
573 | clock->m = clock->m1 * clock->m2; | |
574 | clock->p = clock->p1 * clock->p2; | |
575 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 576 | return 0; |
589eca67 ID |
577 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
578 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
579 | |
580 | return clock->dot / 5; | |
589eca67 ID |
581 | } |
582 | ||
9e2c8475 | 583 | int chv_calc_dpll_params(int refclk, struct dpll *clock) |
ef9348c8 CML |
584 | { |
585 | clock->m = clock->m1 * clock->m2; | |
586 | clock->p = clock->p1 * clock->p2; | |
587 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 588 | return 0; |
ef9348c8 CML |
589 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
590 | clock->n << 22); | |
591 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
592 | |
593 | return clock->dot / 5; | |
ef9348c8 CML |
594 | } |
595 | ||
7c04d1d9 | 596 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
597 | /** |
598 | * Returns whether the given set of divisors are valid for a given refclk with | |
599 | * the given connectors. | |
600 | */ | |
601 | ||
e2d214ae | 602 | static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv, |
1b6f4958 | 603 | const struct intel_limit *limit, |
9e2c8475 | 604 | const struct dpll *clock) |
79e53945 | 605 | { |
f01b7962 VS |
606 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
607 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 608 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 609 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 610 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 611 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 612 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 613 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 614 | |
e2d214ae TU |
615 | if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) && |
616 | !IS_CHERRYVIEW(dev_priv) && !IS_BROXTON(dev_priv)) | |
f01b7962 VS |
617 | if (clock->m1 <= clock->m2) |
618 | INTELPllInvalid("m1 <= m2\n"); | |
619 | ||
e2d214ae TU |
620 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
621 | !IS_BROXTON(dev_priv)) { | |
f01b7962 VS |
622 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
623 | INTELPllInvalid("p out of range\n"); | |
624 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
625 | INTELPllInvalid("m out of range\n"); | |
626 | } | |
627 | ||
79e53945 | 628 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 629 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
630 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
631 | * connector, etc., rather than just a single range. | |
632 | */ | |
633 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 634 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
635 | |
636 | return true; | |
637 | } | |
638 | ||
3b1429d9 | 639 | static int |
1b6f4958 | 640 | i9xx_select_p2_div(const struct intel_limit *limit, |
3b1429d9 VS |
641 | const struct intel_crtc_state *crtc_state, |
642 | int target) | |
79e53945 | 643 | { |
3b1429d9 | 644 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 645 | |
2d84d2b3 | 646 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 647 | /* |
a210b028 DV |
648 | * For LVDS just rely on its current settings for dual-channel. |
649 | * We haven't figured out how to reliably set up different | |
650 | * single/dual channel state, if we even can. | |
79e53945 | 651 | */ |
1974cad0 | 652 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 653 | return limit->p2.p2_fast; |
79e53945 | 654 | else |
3b1429d9 | 655 | return limit->p2.p2_slow; |
79e53945 JB |
656 | } else { |
657 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 658 | return limit->p2.p2_slow; |
79e53945 | 659 | else |
3b1429d9 | 660 | return limit->p2.p2_fast; |
79e53945 | 661 | } |
3b1429d9 VS |
662 | } |
663 | ||
70e8aa21 ACO |
664 | /* |
665 | * Returns a set of divisors for the desired target clock with the given | |
666 | * refclk, or FALSE. The returned values represent the clock equation: | |
667 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
668 | * | |
669 | * Target and reference clocks are specified in kHz. | |
670 | * | |
671 | * If match_clock is provided, then best_clock P divider must match the P | |
672 | * divider from @match_clock used for LVDS downclocking. | |
673 | */ | |
3b1429d9 | 674 | static bool |
1b6f4958 | 675 | i9xx_find_best_dpll(const struct intel_limit *limit, |
3b1429d9 | 676 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
677 | int target, int refclk, struct dpll *match_clock, |
678 | struct dpll *best_clock) | |
3b1429d9 VS |
679 | { |
680 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
9e2c8475 | 681 | struct dpll clock; |
3b1429d9 | 682 | int err = target; |
79e53945 | 683 | |
0206e353 | 684 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 685 | |
3b1429d9 VS |
686 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
687 | ||
42158660 ZY |
688 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
689 | clock.m1++) { | |
690 | for (clock.m2 = limit->m2.min; | |
691 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 692 | if (clock.m2 >= clock.m1) |
42158660 ZY |
693 | break; |
694 | for (clock.n = limit->n.min; | |
695 | clock.n <= limit->n.max; clock.n++) { | |
696 | for (clock.p1 = limit->p1.min; | |
697 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
698 | int this_err; |
699 | ||
dccbea3b | 700 | i9xx_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
701 | if (!intel_PLL_is_valid(to_i915(dev), |
702 | limit, | |
ac58c3f0 DV |
703 | &clock)) |
704 | continue; | |
705 | if (match_clock && | |
706 | clock.p != match_clock->p) | |
707 | continue; | |
708 | ||
709 | this_err = abs(clock.dot - target); | |
710 | if (this_err < err) { | |
711 | *best_clock = clock; | |
712 | err = this_err; | |
713 | } | |
714 | } | |
715 | } | |
716 | } | |
717 | } | |
718 | ||
719 | return (err != target); | |
720 | } | |
721 | ||
70e8aa21 ACO |
722 | /* |
723 | * Returns a set of divisors for the desired target clock with the given | |
724 | * refclk, or FALSE. The returned values represent the clock equation: | |
725 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
726 | * | |
727 | * Target and reference clocks are specified in kHz. | |
728 | * | |
729 | * If match_clock is provided, then best_clock P divider must match the P | |
730 | * divider from @match_clock used for LVDS downclocking. | |
731 | */ | |
ac58c3f0 | 732 | static bool |
1b6f4958 | 733 | pnv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 734 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
735 | int target, int refclk, struct dpll *match_clock, |
736 | struct dpll *best_clock) | |
79e53945 | 737 | { |
3b1429d9 | 738 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 739 | struct dpll clock; |
79e53945 JB |
740 | int err = target; |
741 | ||
0206e353 | 742 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 743 | |
3b1429d9 VS |
744 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
745 | ||
42158660 ZY |
746 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
747 | clock.m1++) { | |
748 | for (clock.m2 = limit->m2.min; | |
749 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
750 | for (clock.n = limit->n.min; |
751 | clock.n <= limit->n.max; clock.n++) { | |
752 | for (clock.p1 = limit->p1.min; | |
753 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
754 | int this_err; |
755 | ||
dccbea3b | 756 | pnv_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
757 | if (!intel_PLL_is_valid(to_i915(dev), |
758 | limit, | |
1b894b59 | 759 | &clock)) |
79e53945 | 760 | continue; |
cec2f356 SP |
761 | if (match_clock && |
762 | clock.p != match_clock->p) | |
763 | continue; | |
79e53945 JB |
764 | |
765 | this_err = abs(clock.dot - target); | |
766 | if (this_err < err) { | |
767 | *best_clock = clock; | |
768 | err = this_err; | |
769 | } | |
770 | } | |
771 | } | |
772 | } | |
773 | } | |
774 | ||
775 | return (err != target); | |
776 | } | |
777 | ||
997c030c ACO |
778 | /* |
779 | * Returns a set of divisors for the desired target clock with the given | |
780 | * refclk, or FALSE. The returned values represent the clock equation: | |
781 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
70e8aa21 ACO |
782 | * |
783 | * Target and reference clocks are specified in kHz. | |
784 | * | |
785 | * If match_clock is provided, then best_clock P divider must match the P | |
786 | * divider from @match_clock used for LVDS downclocking. | |
997c030c | 787 | */ |
d4906093 | 788 | static bool |
1b6f4958 | 789 | g4x_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 790 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
791 | int target, int refclk, struct dpll *match_clock, |
792 | struct dpll *best_clock) | |
d4906093 | 793 | { |
3b1429d9 | 794 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 795 | struct dpll clock; |
d4906093 | 796 | int max_n; |
3b1429d9 | 797 | bool found = false; |
6ba770dc AJ |
798 | /* approximately equals target * 0.00585 */ |
799 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
800 | |
801 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
802 | |
803 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
804 | ||
d4906093 | 805 | max_n = limit->n.max; |
f77f13e2 | 806 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 807 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 808 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
809 | for (clock.m1 = limit->m1.max; |
810 | clock.m1 >= limit->m1.min; clock.m1--) { | |
811 | for (clock.m2 = limit->m2.max; | |
812 | clock.m2 >= limit->m2.min; clock.m2--) { | |
813 | for (clock.p1 = limit->p1.max; | |
814 | clock.p1 >= limit->p1.min; clock.p1--) { | |
815 | int this_err; | |
816 | ||
dccbea3b | 817 | i9xx_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
818 | if (!intel_PLL_is_valid(to_i915(dev), |
819 | limit, | |
1b894b59 | 820 | &clock)) |
d4906093 | 821 | continue; |
1b894b59 CW |
822 | |
823 | this_err = abs(clock.dot - target); | |
d4906093 ML |
824 | if (this_err < err_most) { |
825 | *best_clock = clock; | |
826 | err_most = this_err; | |
827 | max_n = clock.n; | |
828 | found = true; | |
829 | } | |
830 | } | |
831 | } | |
832 | } | |
833 | } | |
2c07245f ZW |
834 | return found; |
835 | } | |
836 | ||
d5dd62bd ID |
837 | /* |
838 | * Check if the calculated PLL configuration is more optimal compared to the | |
839 | * best configuration and error found so far. Return the calculated error. | |
840 | */ | |
841 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
9e2c8475 ACO |
842 | const struct dpll *calculated_clock, |
843 | const struct dpll *best_clock, | |
d5dd62bd ID |
844 | unsigned int best_error_ppm, |
845 | unsigned int *error_ppm) | |
846 | { | |
9ca3ba01 ID |
847 | /* |
848 | * For CHV ignore the error and consider only the P value. | |
849 | * Prefer a bigger P value based on HW requirements. | |
850 | */ | |
920a14b2 | 851 | if (IS_CHERRYVIEW(to_i915(dev))) { |
9ca3ba01 ID |
852 | *error_ppm = 0; |
853 | ||
854 | return calculated_clock->p > best_clock->p; | |
855 | } | |
856 | ||
24be4e46 ID |
857 | if (WARN_ON_ONCE(!target_freq)) |
858 | return false; | |
859 | ||
d5dd62bd ID |
860 | *error_ppm = div_u64(1000000ULL * |
861 | abs(target_freq - calculated_clock->dot), | |
862 | target_freq); | |
863 | /* | |
864 | * Prefer a better P value over a better (smaller) error if the error | |
865 | * is small. Ensure this preference for future configurations too by | |
866 | * setting the error to 0. | |
867 | */ | |
868 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
869 | *error_ppm = 0; | |
870 | ||
871 | return true; | |
872 | } | |
873 | ||
874 | return *error_ppm + 10 < best_error_ppm; | |
875 | } | |
876 | ||
65b3d6a9 ACO |
877 | /* |
878 | * Returns a set of divisors for the desired target clock with the given | |
879 | * refclk, or FALSE. The returned values represent the clock equation: | |
880 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
881 | */ | |
a0c4da24 | 882 | static bool |
1b6f4958 | 883 | vlv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 884 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
885 | int target, int refclk, struct dpll *match_clock, |
886 | struct dpll *best_clock) | |
a0c4da24 | 887 | { |
a93e255f | 888 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 889 | struct drm_device *dev = crtc->base.dev; |
9e2c8475 | 890 | struct dpll clock; |
69e4f900 | 891 | unsigned int bestppm = 1000000; |
27e639bf VS |
892 | /* min update 19.2 MHz */ |
893 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 894 | bool found = false; |
a0c4da24 | 895 | |
6b4bf1c4 VS |
896 | target *= 5; /* fast clock */ |
897 | ||
898 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
899 | |
900 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 901 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 902 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 903 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 904 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 905 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 906 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 907 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 908 | unsigned int ppm; |
69e4f900 | 909 | |
6b4bf1c4 VS |
910 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
911 | refclk * clock.m1); | |
912 | ||
dccbea3b | 913 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 914 | |
e2d214ae TU |
915 | if (!intel_PLL_is_valid(to_i915(dev), |
916 | limit, | |
f01b7962 | 917 | &clock)) |
43b0ac53 VS |
918 | continue; |
919 | ||
d5dd62bd ID |
920 | if (!vlv_PLL_is_optimal(dev, target, |
921 | &clock, | |
922 | best_clock, | |
923 | bestppm, &ppm)) | |
924 | continue; | |
6b4bf1c4 | 925 | |
d5dd62bd ID |
926 | *best_clock = clock; |
927 | bestppm = ppm; | |
928 | found = true; | |
a0c4da24 JB |
929 | } |
930 | } | |
931 | } | |
932 | } | |
a0c4da24 | 933 | |
49e497ef | 934 | return found; |
a0c4da24 | 935 | } |
a4fc5ed6 | 936 | |
65b3d6a9 ACO |
937 | /* |
938 | * Returns a set of divisors for the desired target clock with the given | |
939 | * refclk, or FALSE. The returned values represent the clock equation: | |
940 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
941 | */ | |
ef9348c8 | 942 | static bool |
1b6f4958 | 943 | chv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 944 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
945 | int target, int refclk, struct dpll *match_clock, |
946 | struct dpll *best_clock) | |
ef9348c8 | 947 | { |
a93e255f | 948 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 949 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 950 | unsigned int best_error_ppm; |
9e2c8475 | 951 | struct dpll clock; |
ef9348c8 CML |
952 | uint64_t m2; |
953 | int found = false; | |
954 | ||
955 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 956 | best_error_ppm = 1000000; |
ef9348c8 CML |
957 | |
958 | /* | |
959 | * Based on hardware doc, the n always set to 1, and m1 always | |
960 | * set to 2. If requires to support 200Mhz refclk, we need to | |
961 | * revisit this because n may not 1 anymore. | |
962 | */ | |
963 | clock.n = 1, clock.m1 = 2; | |
964 | target *= 5; /* fast clock */ | |
965 | ||
966 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
967 | for (clock.p2 = limit->p2.p2_fast; | |
968 | clock.p2 >= limit->p2.p2_slow; | |
969 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 970 | unsigned int error_ppm; |
ef9348c8 CML |
971 | |
972 | clock.p = clock.p1 * clock.p2; | |
973 | ||
974 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
975 | clock.n) << 22, refclk * clock.m1); | |
976 | ||
977 | if (m2 > INT_MAX/clock.m1) | |
978 | continue; | |
979 | ||
980 | clock.m2 = m2; | |
981 | ||
dccbea3b | 982 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 | 983 | |
e2d214ae | 984 | if (!intel_PLL_is_valid(to_i915(dev), limit, &clock)) |
ef9348c8 CML |
985 | continue; |
986 | ||
9ca3ba01 ID |
987 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
988 | best_error_ppm, &error_ppm)) | |
989 | continue; | |
990 | ||
991 | *best_clock = clock; | |
992 | best_error_ppm = error_ppm; | |
993 | found = true; | |
ef9348c8 CML |
994 | } |
995 | } | |
996 | ||
997 | return found; | |
998 | } | |
999 | ||
5ab7b0b7 | 1000 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
9e2c8475 | 1001 | struct dpll *best_clock) |
5ab7b0b7 | 1002 | { |
65b3d6a9 | 1003 | int refclk = 100000; |
1b6f4958 | 1004 | const struct intel_limit *limit = &intel_limits_bxt; |
5ab7b0b7 | 1005 | |
65b3d6a9 | 1006 | return chv_find_best_dpll(limit, crtc_state, |
5ab7b0b7 ID |
1007 | target_clock, refclk, NULL, best_clock); |
1008 | } | |
1009 | ||
20ddf665 VS |
1010 | bool intel_crtc_active(struct drm_crtc *crtc) |
1011 | { | |
1012 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1013 | ||
1014 | /* Be paranoid as we can arrive here with only partial | |
1015 | * state retrieved from the hardware during setup. | |
1016 | * | |
241bfc38 | 1017 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
1018 | * as Haswell has gained clock readout/fastboot support. |
1019 | * | |
66e514c1 | 1020 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 1021 | * properly reconstruct framebuffers. |
c3d1f436 MR |
1022 | * |
1023 | * FIXME: The intel_crtc->active here should be switched to | |
1024 | * crtc->state->active once we have proper CRTC states wired up | |
1025 | * for atomic. | |
20ddf665 | 1026 | */ |
c3d1f436 | 1027 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 1028 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
1029 | } |
1030 | ||
a5c961d1 PZ |
1031 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1032 | enum pipe pipe) | |
1033 | { | |
1034 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1035 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1036 | ||
6e3c9717 | 1037 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1038 | } |
1039 | ||
fbf49ea2 VS |
1040 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
1041 | { | |
fac5e23e | 1042 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 1043 | i915_reg_t reg = PIPEDSL(pipe); |
fbf49ea2 VS |
1044 | u32 line1, line2; |
1045 | u32 line_mask; | |
1046 | ||
5db94019 | 1047 | if (IS_GEN2(dev_priv)) |
fbf49ea2 VS |
1048 | line_mask = DSL_LINEMASK_GEN2; |
1049 | else | |
1050 | line_mask = DSL_LINEMASK_GEN3; | |
1051 | ||
1052 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 1053 | msleep(5); |
fbf49ea2 VS |
1054 | line2 = I915_READ(reg) & line_mask; |
1055 | ||
1056 | return line1 == line2; | |
1057 | } | |
1058 | ||
ab7ad7f6 KP |
1059 | /* |
1060 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1061 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1062 | * |
1063 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1064 | * spinning on the vblank interrupt status bit, since we won't actually | |
1065 | * see an interrupt when the pipe is disabled. | |
1066 | * | |
ab7ad7f6 KP |
1067 | * On Gen4 and above: |
1068 | * wait for the pipe register state bit to turn off | |
1069 | * | |
1070 | * Otherwise: | |
1071 | * wait for the display line value to settle (it usually | |
1072 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1073 | * |
9d0498a2 | 1074 | */ |
575f7ab7 | 1075 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1076 | { |
575f7ab7 | 1077 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1078 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 1079 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1080 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
1081 | |
1082 | if (INTEL_INFO(dev)->gen >= 4) { | |
f0f59a00 | 1083 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1084 | |
1085 | /* Wait for the Pipe State to go off */ | |
b8511f53 CW |
1086 | if (intel_wait_for_register(dev_priv, |
1087 | reg, I965_PIPECONF_ACTIVE, 0, | |
1088 | 100)) | |
284637d9 | 1089 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1090 | } else { |
ab7ad7f6 | 1091 | /* Wait for the display line to settle */ |
fbf49ea2 | 1092 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1093 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1094 | } |
79e53945 JB |
1095 | } |
1096 | ||
b24e7179 | 1097 | /* Only for pre-ILK configs */ |
55607e8a DV |
1098 | void assert_pll(struct drm_i915_private *dev_priv, |
1099 | enum pipe pipe, bool state) | |
b24e7179 | 1100 | { |
b24e7179 JB |
1101 | u32 val; |
1102 | bool cur_state; | |
1103 | ||
649636ef | 1104 | val = I915_READ(DPLL(pipe)); |
b24e7179 | 1105 | cur_state = !!(val & DPLL_VCO_ENABLE); |
e2c719b7 | 1106 | I915_STATE_WARN(cur_state != state, |
b24e7179 | 1107 | "PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1108 | onoff(state), onoff(cur_state)); |
b24e7179 | 1109 | } |
b24e7179 | 1110 | |
23538ef1 | 1111 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
8563b1e8 | 1112 | void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) |
23538ef1 JN |
1113 | { |
1114 | u32 val; | |
1115 | bool cur_state; | |
1116 | ||
a580516d | 1117 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1118 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1119 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1120 | |
1121 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1122 | I915_STATE_WARN(cur_state != state, |
23538ef1 | 1123 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1124 | onoff(state), onoff(cur_state)); |
23538ef1 | 1125 | } |
23538ef1 | 1126 | |
040484af JB |
1127 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
1128 | enum pipe pipe, bool state) | |
1129 | { | |
040484af | 1130 | bool cur_state; |
ad80a810 PZ |
1131 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1132 | pipe); | |
040484af | 1133 | |
2d1fe073 | 1134 | if (HAS_DDI(dev_priv)) { |
affa9354 | 1135 | /* DDI does not have a specific FDI_TX register */ |
649636ef | 1136 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
ad80a810 | 1137 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 | 1138 | } else { |
649636ef | 1139 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
bf507ef7 ED |
1140 | cur_state = !!(val & FDI_TX_ENABLE); |
1141 | } | |
e2c719b7 | 1142 | I915_STATE_WARN(cur_state != state, |
040484af | 1143 | "FDI TX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1144 | onoff(state), onoff(cur_state)); |
040484af JB |
1145 | } |
1146 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1147 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1148 | ||
1149 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1150 | enum pipe pipe, bool state) | |
1151 | { | |
040484af JB |
1152 | u32 val; |
1153 | bool cur_state; | |
1154 | ||
649636ef | 1155 | val = I915_READ(FDI_RX_CTL(pipe)); |
d63fa0dc | 1156 | cur_state = !!(val & FDI_RX_ENABLE); |
e2c719b7 | 1157 | I915_STATE_WARN(cur_state != state, |
040484af | 1158 | "FDI RX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1159 | onoff(state), onoff(cur_state)); |
040484af JB |
1160 | } |
1161 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1162 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1163 | ||
1164 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1165 | enum pipe pipe) | |
1166 | { | |
040484af JB |
1167 | u32 val; |
1168 | ||
1169 | /* ILK FDI PLL is always enabled */ | |
7e22dbbb | 1170 | if (IS_GEN5(dev_priv)) |
040484af JB |
1171 | return; |
1172 | ||
bf507ef7 | 1173 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
2d1fe073 | 1174 | if (HAS_DDI(dev_priv)) |
bf507ef7 ED |
1175 | return; |
1176 | ||
649636ef | 1177 | val = I915_READ(FDI_TX_CTL(pipe)); |
e2c719b7 | 1178 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1179 | } |
1180 | ||
55607e8a DV |
1181 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1182 | enum pipe pipe, bool state) | |
040484af | 1183 | { |
040484af | 1184 | u32 val; |
55607e8a | 1185 | bool cur_state; |
040484af | 1186 | |
649636ef | 1187 | val = I915_READ(FDI_RX_CTL(pipe)); |
55607e8a | 1188 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1189 | I915_STATE_WARN(cur_state != state, |
55607e8a | 1190 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
87ad3212 | 1191 | onoff(state), onoff(cur_state)); |
040484af JB |
1192 | } |
1193 | ||
4f8036a2 | 1194 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe) |
ea0760cf | 1195 | { |
f0f59a00 | 1196 | i915_reg_t pp_reg; |
ea0760cf JB |
1197 | u32 val; |
1198 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1199 | bool locked = true; |
ea0760cf | 1200 | |
4f8036a2 | 1201 | if (WARN_ON(HAS_DDI(dev_priv))) |
bedd4dba JN |
1202 | return; |
1203 | ||
4f8036a2 | 1204 | if (HAS_PCH_SPLIT(dev_priv)) { |
bedd4dba JN |
1205 | u32 port_sel; |
1206 | ||
44cb734c ID |
1207 | pp_reg = PP_CONTROL(0); |
1208 | port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; | |
bedd4dba JN |
1209 | |
1210 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1211 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1212 | panel_pipe = PIPE_B; | |
1213 | /* XXX: else fix for eDP */ | |
4f8036a2 | 1214 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
bedd4dba | 1215 | /* presumably write lock depends on pipe, not port select */ |
44cb734c | 1216 | pp_reg = PP_CONTROL(pipe); |
bedd4dba | 1217 | panel_pipe = pipe; |
ea0760cf | 1218 | } else { |
44cb734c | 1219 | pp_reg = PP_CONTROL(0); |
bedd4dba JN |
1220 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1221 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1222 | } |
1223 | ||
1224 | val = I915_READ(pp_reg); | |
1225 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1226 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1227 | locked = false; |
1228 | ||
e2c719b7 | 1229 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1230 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1231 | pipe_name(pipe)); |
ea0760cf JB |
1232 | } |
1233 | ||
93ce0ba6 JN |
1234 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1235 | enum pipe pipe, bool state) | |
1236 | { | |
93ce0ba6 JN |
1237 | bool cur_state; |
1238 | ||
50a0bc90 | 1239 | if (IS_845G(dev_priv) || IS_I865G(dev_priv)) |
0b87c24e | 1240 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
d9d82081 | 1241 | else |
5efb3e28 | 1242 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1243 | |
e2c719b7 | 1244 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 | 1245 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1246 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
93ce0ba6 JN |
1247 | } |
1248 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1249 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1250 | ||
b840d907 JB |
1251 | void assert_pipe(struct drm_i915_private *dev_priv, |
1252 | enum pipe pipe, bool state) | |
b24e7179 | 1253 | { |
63d7bbe9 | 1254 | bool cur_state; |
702e7a56 PZ |
1255 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1256 | pipe); | |
4feed0eb | 1257 | enum intel_display_power_domain power_domain; |
b24e7179 | 1258 | |
b6b5d049 VS |
1259 | /* if we need the pipe quirk it must be always on */ |
1260 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1261 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1262 | state = true; |
1263 | ||
4feed0eb ID |
1264 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); |
1265 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
649636ef | 1266 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
69310161 | 1267 | cur_state = !!(val & PIPECONF_ENABLE); |
4feed0eb ID |
1268 | |
1269 | intel_display_power_put(dev_priv, power_domain); | |
1270 | } else { | |
1271 | cur_state = false; | |
69310161 PZ |
1272 | } |
1273 | ||
e2c719b7 | 1274 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1275 | "pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1276 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1277 | } |
1278 | ||
931872fc CW |
1279 | static void assert_plane(struct drm_i915_private *dev_priv, |
1280 | enum plane plane, bool state) | |
b24e7179 | 1281 | { |
b24e7179 | 1282 | u32 val; |
931872fc | 1283 | bool cur_state; |
b24e7179 | 1284 | |
649636ef | 1285 | val = I915_READ(DSPCNTR(plane)); |
931872fc | 1286 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1287 | I915_STATE_WARN(cur_state != state, |
931872fc | 1288 | "plane %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1289 | plane_name(plane), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1290 | } |
1291 | ||
931872fc CW |
1292 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1293 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1294 | ||
b24e7179 JB |
1295 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1296 | enum pipe pipe) | |
1297 | { | |
91c8a326 | 1298 | struct drm_device *dev = &dev_priv->drm; |
649636ef | 1299 | int i; |
b24e7179 | 1300 | |
653e1026 VS |
1301 | /* Primary planes are fixed to pipes on gen4+ */ |
1302 | if (INTEL_INFO(dev)->gen >= 4) { | |
649636ef | 1303 | u32 val = I915_READ(DSPCNTR(pipe)); |
e2c719b7 | 1304 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1305 | "plane %c assertion failure, should be disabled but not\n", |
1306 | plane_name(pipe)); | |
19ec1358 | 1307 | return; |
28c05794 | 1308 | } |
19ec1358 | 1309 | |
b24e7179 | 1310 | /* Need to check both planes against the pipe */ |
055e393f | 1311 | for_each_pipe(dev_priv, i) { |
649636ef VS |
1312 | u32 val = I915_READ(DSPCNTR(i)); |
1313 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
b24e7179 | 1314 | DISPPLANE_SEL_PIPE_SHIFT; |
e2c719b7 | 1315 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1316 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1317 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1318 | } |
1319 | } | |
1320 | ||
19332d7a JB |
1321 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1322 | enum pipe pipe) | |
1323 | { | |
91c8a326 | 1324 | struct drm_device *dev = &dev_priv->drm; |
649636ef | 1325 | int sprite; |
19332d7a | 1326 | |
7feb8b88 | 1327 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1328 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1329 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1330 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1331 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1332 | sprite, pipe_name(pipe)); | |
1333 | } | |
920a14b2 | 1334 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
3bdcfc0c | 1335 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1336 | u32 val = I915_READ(SPCNTR(pipe, sprite)); |
e2c719b7 | 1337 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1338 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1339 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1340 | } |
1341 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
649636ef | 1342 | u32 val = I915_READ(SPRCTL(pipe)); |
e2c719b7 | 1343 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1344 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1345 | plane_name(pipe), pipe_name(pipe)); |
1346 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
649636ef | 1347 | u32 val = I915_READ(DVSCNTR(pipe)); |
e2c719b7 | 1348 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1349 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1350 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1351 | } |
1352 | } | |
1353 | ||
08c71e5e VS |
1354 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1355 | { | |
e2c719b7 | 1356 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1357 | drm_crtc_vblank_put(crtc); |
1358 | } | |
1359 | ||
7abd4b35 ACO |
1360 | void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1361 | enum pipe pipe) | |
92f2584a | 1362 | { |
92f2584a JB |
1363 | u32 val; |
1364 | bool enabled; | |
1365 | ||
649636ef | 1366 | val = I915_READ(PCH_TRANSCONF(pipe)); |
92f2584a | 1367 | enabled = !!(val & TRANS_ENABLE); |
e2c719b7 | 1368 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1369 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1370 | pipe_name(pipe)); | |
92f2584a JB |
1371 | } |
1372 | ||
4e634389 KP |
1373 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1374 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1375 | { |
1376 | if ((val & DP_PORT_EN) == 0) | |
1377 | return false; | |
1378 | ||
2d1fe073 | 1379 | if (HAS_PCH_CPT(dev_priv)) { |
f0f59a00 | 1380 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
f0575e92 KP |
1381 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1382 | return false; | |
2d1fe073 | 1383 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1384 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) |
1385 | return false; | |
f0575e92 KP |
1386 | } else { |
1387 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1388 | return false; | |
1389 | } | |
1390 | return true; | |
1391 | } | |
1392 | ||
1519b995 KP |
1393 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1394 | enum pipe pipe, u32 val) | |
1395 | { | |
dc0fa718 | 1396 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1397 | return false; |
1398 | ||
2d1fe073 | 1399 | if (HAS_PCH_CPT(dev_priv)) { |
dc0fa718 | 1400 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1401 | return false; |
2d1fe073 | 1402 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1403 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) |
1404 | return false; | |
1519b995 | 1405 | } else { |
dc0fa718 | 1406 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1407 | return false; |
1408 | } | |
1409 | return true; | |
1410 | } | |
1411 | ||
1412 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1413 | enum pipe pipe, u32 val) | |
1414 | { | |
1415 | if ((val & LVDS_PORT_EN) == 0) | |
1416 | return false; | |
1417 | ||
2d1fe073 | 1418 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1419 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1420 | return false; | |
1421 | } else { | |
1422 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1423 | return false; | |
1424 | } | |
1425 | return true; | |
1426 | } | |
1427 | ||
1428 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1429 | enum pipe pipe, u32 val) | |
1430 | { | |
1431 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1432 | return false; | |
2d1fe073 | 1433 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1434 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1435 | return false; | |
1436 | } else { | |
1437 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1438 | return false; | |
1439 | } | |
1440 | return true; | |
1441 | } | |
1442 | ||
291906f1 | 1443 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
1444 | enum pipe pipe, i915_reg_t reg, |
1445 | u32 port_sel) | |
291906f1 | 1446 | { |
47a05eca | 1447 | u32 val = I915_READ(reg); |
e2c719b7 | 1448 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1449 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1450 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1451 | |
2d1fe073 | 1452 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1453 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1454 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1455 | } |
1456 | ||
1457 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
f0f59a00 | 1458 | enum pipe pipe, i915_reg_t reg) |
291906f1 | 1459 | { |
47a05eca | 1460 | u32 val = I915_READ(reg); |
e2c719b7 | 1461 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1462 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1463 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1464 | |
2d1fe073 | 1465 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1466 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1467 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1468 | } |
1469 | ||
1470 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1471 | enum pipe pipe) | |
1472 | { | |
291906f1 | 1473 | u32 val; |
291906f1 | 1474 | |
f0575e92 KP |
1475 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1476 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1477 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 | 1478 | |
649636ef | 1479 | val = I915_READ(PCH_ADPA); |
e2c719b7 | 1480 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1481 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1482 | pipe_name(pipe)); |
291906f1 | 1483 | |
649636ef | 1484 | val = I915_READ(PCH_LVDS); |
e2c719b7 | 1485 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1486 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1487 | pipe_name(pipe)); |
291906f1 | 1488 | |
e2debe91 PZ |
1489 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1490 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1491 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1492 | } |
1493 | ||
cd2d34d9 VS |
1494 | static void _vlv_enable_pll(struct intel_crtc *crtc, |
1495 | const struct intel_crtc_state *pipe_config) | |
1496 | { | |
1497 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1498 | enum pipe pipe = crtc->pipe; | |
1499 | ||
1500 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); | |
1501 | POSTING_READ(DPLL(pipe)); | |
1502 | udelay(150); | |
1503 | ||
2c30b43b CW |
1504 | if (intel_wait_for_register(dev_priv, |
1505 | DPLL(pipe), | |
1506 | DPLL_LOCK_VLV, | |
1507 | DPLL_LOCK_VLV, | |
1508 | 1)) | |
cd2d34d9 VS |
1509 | DRM_ERROR("DPLL %d failed to lock\n", pipe); |
1510 | } | |
1511 | ||
d288f65f | 1512 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1513 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1514 | { |
cd2d34d9 | 1515 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1516 | enum pipe pipe = crtc->pipe; |
87442f73 | 1517 | |
8bd3f301 | 1518 | assert_pipe_disabled(dev_priv, pipe); |
87442f73 | 1519 | |
87442f73 | 1520 | /* PLL is protected by panel, make sure we can write it */ |
7d1a83cb | 1521 | assert_panel_unlocked(dev_priv, pipe); |
87442f73 | 1522 | |
cd2d34d9 VS |
1523 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) |
1524 | _vlv_enable_pll(crtc, pipe_config); | |
426115cf | 1525 | |
8bd3f301 VS |
1526 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
1527 | POSTING_READ(DPLL_MD(pipe)); | |
87442f73 DV |
1528 | } |
1529 | ||
cd2d34d9 VS |
1530 | |
1531 | static void _chv_enable_pll(struct intel_crtc *crtc, | |
1532 | const struct intel_crtc_state *pipe_config) | |
9d556c99 | 1533 | { |
cd2d34d9 | 1534 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1535 | enum pipe pipe = crtc->pipe; |
9d556c99 | 1536 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9d556c99 CML |
1537 | u32 tmp; |
1538 | ||
a580516d | 1539 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1540 | |
1541 | /* Enable back the 10bit clock to display controller */ | |
1542 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1543 | tmp |= DPIO_DCLKP_EN; | |
1544 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1545 | ||
54433e91 VS |
1546 | mutex_unlock(&dev_priv->sb_lock); |
1547 | ||
9d556c99 CML |
1548 | /* |
1549 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1550 | */ | |
1551 | udelay(1); | |
1552 | ||
1553 | /* Enable PLL */ | |
d288f65f | 1554 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1555 | |
1556 | /* Check PLL is locked */ | |
6b18826a CW |
1557 | if (intel_wait_for_register(dev_priv, |
1558 | DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV, | |
1559 | 1)) | |
9d556c99 | 1560 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
cd2d34d9 VS |
1561 | } |
1562 | ||
1563 | static void chv_enable_pll(struct intel_crtc *crtc, | |
1564 | const struct intel_crtc_state *pipe_config) | |
1565 | { | |
1566 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1567 | enum pipe pipe = crtc->pipe; | |
1568 | ||
1569 | assert_pipe_disabled(dev_priv, pipe); | |
1570 | ||
1571 | /* PLL is protected by panel, make sure we can write it */ | |
1572 | assert_panel_unlocked(dev_priv, pipe); | |
1573 | ||
1574 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) | |
1575 | _chv_enable_pll(crtc, pipe_config); | |
9d556c99 | 1576 | |
c231775c VS |
1577 | if (pipe != PIPE_A) { |
1578 | /* | |
1579 | * WaPixelRepeatModeFixForC0:chv | |
1580 | * | |
1581 | * DPLLCMD is AWOL. Use chicken bits to propagate | |
1582 | * the value from DPLLBMD to either pipe B or C. | |
1583 | */ | |
1584 | I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C); | |
1585 | I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md); | |
1586 | I915_WRITE(CBR4_VLV, 0); | |
1587 | dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; | |
1588 | ||
1589 | /* | |
1590 | * DPLLB VGA mode also seems to cause problems. | |
1591 | * We should always have it disabled. | |
1592 | */ | |
1593 | WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); | |
1594 | } else { | |
1595 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); | |
1596 | POSTING_READ(DPLL_MD(pipe)); | |
1597 | } | |
9d556c99 CML |
1598 | } |
1599 | ||
1c4e0274 VS |
1600 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1601 | { | |
1602 | struct intel_crtc *crtc; | |
1603 | int count = 0; | |
1604 | ||
2d84d2b3 | 1605 | for_each_intel_crtc(dev, crtc) { |
3538b9df | 1606 | count += crtc->base.state->active && |
2d84d2b3 VS |
1607 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO); |
1608 | } | |
1c4e0274 VS |
1609 | |
1610 | return count; | |
1611 | } | |
1612 | ||
66e3d5c0 | 1613 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1614 | { |
66e3d5c0 | 1615 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1616 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 1617 | i915_reg_t reg = DPLL(crtc->pipe); |
6e3c9717 | 1618 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1619 | |
66e3d5c0 | 1620 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1621 | |
63d7bbe9 | 1622 | /* PLL is protected by panel, make sure we can write it */ |
50a0bc90 | 1623 | if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv)) |
66e3d5c0 | 1624 | assert_panel_unlocked(dev_priv, crtc->pipe); |
63d7bbe9 | 1625 | |
1c4e0274 | 1626 | /* Enable DVO 2x clock on both PLLs if necessary */ |
50a0bc90 | 1627 | if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev) > 0) { |
1c4e0274 VS |
1628 | /* |
1629 | * It appears to be important that we don't enable this | |
1630 | * for the current pipe before otherwise configuring the | |
1631 | * PLL. No idea how this should be handled if multiple | |
1632 | * DVO outputs are enabled simultaneosly. | |
1633 | */ | |
1634 | dpll |= DPLL_DVO_2X_MODE; | |
1635 | I915_WRITE(DPLL(!crtc->pipe), | |
1636 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1637 | } | |
66e3d5c0 | 1638 | |
c2b63374 VS |
1639 | /* |
1640 | * Apparently we need to have VGA mode enabled prior to changing | |
1641 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1642 | * dividers, even though the register value does change. | |
1643 | */ | |
1644 | I915_WRITE(reg, 0); | |
1645 | ||
8e7a65aa VS |
1646 | I915_WRITE(reg, dpll); |
1647 | ||
66e3d5c0 DV |
1648 | /* Wait for the clocks to stabilize. */ |
1649 | POSTING_READ(reg); | |
1650 | udelay(150); | |
1651 | ||
1652 | if (INTEL_INFO(dev)->gen >= 4) { | |
1653 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1654 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1655 | } else { |
1656 | /* The pixel multiplier can only be updated once the | |
1657 | * DPLL is enabled and the clocks are stable. | |
1658 | * | |
1659 | * So write it again. | |
1660 | */ | |
1661 | I915_WRITE(reg, dpll); | |
1662 | } | |
63d7bbe9 JB |
1663 | |
1664 | /* We do this three times for luck */ | |
66e3d5c0 | 1665 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1666 | POSTING_READ(reg); |
1667 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1668 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1669 | POSTING_READ(reg); |
1670 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1671 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1672 | POSTING_READ(reg); |
1673 | udelay(150); /* wait for warmup */ | |
1674 | } | |
1675 | ||
1676 | /** | |
50b44a44 | 1677 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1678 | * @dev_priv: i915 private structure |
1679 | * @pipe: pipe PLL to disable | |
1680 | * | |
1681 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1682 | * | |
1683 | * Note! This is for pre-ILK only. | |
1684 | */ | |
1c4e0274 | 1685 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1686 | { |
1c4e0274 | 1687 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1688 | struct drm_i915_private *dev_priv = to_i915(dev); |
1c4e0274 VS |
1689 | enum pipe pipe = crtc->pipe; |
1690 | ||
1691 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
50a0bc90 | 1692 | if (IS_I830(dev_priv) && |
2d84d2b3 | 1693 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) && |
3538b9df | 1694 | !intel_num_dvo_pipes(dev)) { |
1c4e0274 VS |
1695 | I915_WRITE(DPLL(PIPE_B), |
1696 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1697 | I915_WRITE(DPLL(PIPE_A), | |
1698 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1699 | } | |
1700 | ||
b6b5d049 VS |
1701 | /* Don't disable pipe or pipe PLLs if needed */ |
1702 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1703 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1704 | return; |
1705 | ||
1706 | /* Make sure the pipe isn't still relying on us */ | |
1707 | assert_pipe_disabled(dev_priv, pipe); | |
1708 | ||
b8afb911 | 1709 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1710 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1711 | } |
1712 | ||
f6071166 JB |
1713 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1714 | { | |
b8afb911 | 1715 | u32 val; |
f6071166 JB |
1716 | |
1717 | /* Make sure the pipe isn't still relying on us */ | |
1718 | assert_pipe_disabled(dev_priv, pipe); | |
1719 | ||
03ed5cbf VS |
1720 | val = DPLL_INTEGRATED_REF_CLK_VLV | |
1721 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
1722 | if (pipe != PIPE_A) | |
1723 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1724 | ||
f6071166 JB |
1725 | I915_WRITE(DPLL(pipe), val); |
1726 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1727 | } |
1728 | ||
1729 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1730 | { | |
d752048d | 1731 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1732 | u32 val; |
1733 | ||
a11b0703 VS |
1734 | /* Make sure the pipe isn't still relying on us */ |
1735 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1736 | |
60bfe44f VS |
1737 | val = DPLL_SSC_REF_CLK_CHV | |
1738 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1739 | if (pipe != PIPE_A) |
1740 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
03ed5cbf | 1741 | |
a11b0703 VS |
1742 | I915_WRITE(DPLL(pipe), val); |
1743 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1744 | |
a580516d | 1745 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1746 | |
1747 | /* Disable 10bit clock to display controller */ | |
1748 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1749 | val &= ~DPIO_DCLKP_EN; | |
1750 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1751 | ||
a580516d | 1752 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1753 | } |
1754 | ||
e4607fcf | 1755 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1756 | struct intel_digital_port *dport, |
1757 | unsigned int expected_mask) | |
89b667f8 JB |
1758 | { |
1759 | u32 port_mask; | |
f0f59a00 | 1760 | i915_reg_t dpll_reg; |
89b667f8 | 1761 | |
e4607fcf CML |
1762 | switch (dport->port) { |
1763 | case PORT_B: | |
89b667f8 | 1764 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1765 | dpll_reg = DPLL(0); |
e4607fcf CML |
1766 | break; |
1767 | case PORT_C: | |
89b667f8 | 1768 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1769 | dpll_reg = DPLL(0); |
9b6de0a1 | 1770 | expected_mask <<= 4; |
00fc31b7 CML |
1771 | break; |
1772 | case PORT_D: | |
1773 | port_mask = DPLL_PORTD_READY_MASK; | |
1774 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1775 | break; |
1776 | default: | |
1777 | BUG(); | |
1778 | } | |
89b667f8 | 1779 | |
370004d3 CW |
1780 | if (intel_wait_for_register(dev_priv, |
1781 | dpll_reg, port_mask, expected_mask, | |
1782 | 1000)) | |
9b6de0a1 VS |
1783 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", |
1784 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1785 | } |
1786 | ||
b8a4f404 PZ |
1787 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1788 | enum pipe pipe) | |
040484af | 1789 | { |
7c26e5c6 | 1790 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1791 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
f0f59a00 VS |
1792 | i915_reg_t reg; |
1793 | uint32_t val, pipeconf_val; | |
040484af | 1794 | |
040484af | 1795 | /* Make sure PCH DPLL is enabled */ |
8106ddbd | 1796 | assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll); |
040484af JB |
1797 | |
1798 | /* FDI must be feeding us bits for PCH ports */ | |
1799 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1800 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1801 | ||
6e266956 | 1802 | if (HAS_PCH_CPT(dev_priv)) { |
23670b32 DV |
1803 | /* Workaround: Set the timing override bit before enabling the |
1804 | * pch transcoder. */ | |
1805 | reg = TRANS_CHICKEN2(pipe); | |
1806 | val = I915_READ(reg); | |
1807 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1808 | I915_WRITE(reg, val); | |
59c859d6 | 1809 | } |
23670b32 | 1810 | |
ab9412ba | 1811 | reg = PCH_TRANSCONF(pipe); |
040484af | 1812 | val = I915_READ(reg); |
5f7f726d | 1813 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c | 1814 | |
2d1fe073 | 1815 | if (HAS_PCH_IBX(dev_priv)) { |
e9bcff5c | 1816 | /* |
c5de7c6f VS |
1817 | * Make the BPC in transcoder be consistent with |
1818 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1819 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1820 | */ |
dfd07d72 | 1821 | val &= ~PIPECONF_BPC_MASK; |
2d84d2b3 | 1822 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI)) |
c5de7c6f VS |
1823 | val |= PIPECONF_8BPC; |
1824 | else | |
1825 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1826 | } |
5f7f726d PZ |
1827 | |
1828 | val &= ~TRANS_INTERLACE_MASK; | |
1829 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
2d1fe073 | 1830 | if (HAS_PCH_IBX(dev_priv) && |
2d84d2b3 | 1831 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
1832 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1833 | else | |
1834 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1835 | else |
1836 | val |= TRANS_PROGRESSIVE; | |
1837 | ||
040484af | 1838 | I915_WRITE(reg, val | TRANS_ENABLE); |
650fbd84 CW |
1839 | if (intel_wait_for_register(dev_priv, |
1840 | reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE, | |
1841 | 100)) | |
4bb6f1f3 | 1842 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1843 | } |
1844 | ||
8fb033d7 | 1845 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1846 | enum transcoder cpu_transcoder) |
040484af | 1847 | { |
8fb033d7 | 1848 | u32 val, pipeconf_val; |
8fb033d7 | 1849 | |
8fb033d7 | 1850 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1851 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1852 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1853 | |
223a6fdf | 1854 | /* Workaround: set timing override bit. */ |
36c0d0cf | 1855 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1856 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1857 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 1858 | |
25f3ef11 | 1859 | val = TRANS_ENABLE; |
937bb610 | 1860 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1861 | |
9a76b1c6 PZ |
1862 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1863 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1864 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1865 | else |
1866 | val |= TRANS_PROGRESSIVE; | |
1867 | ||
ab9412ba | 1868 | I915_WRITE(LPT_TRANSCONF, val); |
d9f96244 CW |
1869 | if (intel_wait_for_register(dev_priv, |
1870 | LPT_TRANSCONF, | |
1871 | TRANS_STATE_ENABLE, | |
1872 | TRANS_STATE_ENABLE, | |
1873 | 100)) | |
937bb610 | 1874 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1875 | } |
1876 | ||
b8a4f404 PZ |
1877 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1878 | enum pipe pipe) | |
040484af | 1879 | { |
f0f59a00 VS |
1880 | i915_reg_t reg; |
1881 | uint32_t val; | |
040484af JB |
1882 | |
1883 | /* FDI relies on the transcoder */ | |
1884 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1885 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1886 | ||
291906f1 JB |
1887 | /* Ports must be off as well */ |
1888 | assert_pch_ports_disabled(dev_priv, pipe); | |
1889 | ||
ab9412ba | 1890 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1891 | val = I915_READ(reg); |
1892 | val &= ~TRANS_ENABLE; | |
1893 | I915_WRITE(reg, val); | |
1894 | /* wait for PCH transcoder off, transcoder state */ | |
a7d04662 CW |
1895 | if (intel_wait_for_register(dev_priv, |
1896 | reg, TRANS_STATE_ENABLE, 0, | |
1897 | 50)) | |
4bb6f1f3 | 1898 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 | 1899 | |
6e266956 | 1900 | if (HAS_PCH_CPT(dev_priv)) { |
23670b32 DV |
1901 | /* Workaround: Clear the timing override chicken bit again. */ |
1902 | reg = TRANS_CHICKEN2(pipe); | |
1903 | val = I915_READ(reg); | |
1904 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1905 | I915_WRITE(reg, val); | |
1906 | } | |
040484af JB |
1907 | } |
1908 | ||
b7076546 | 1909 | void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1910 | { |
8fb033d7 PZ |
1911 | u32 val; |
1912 | ||
ab9412ba | 1913 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1914 | val &= ~TRANS_ENABLE; |
ab9412ba | 1915 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1916 | /* wait for PCH transcoder off, transcoder state */ |
dfdb4749 CW |
1917 | if (intel_wait_for_register(dev_priv, |
1918 | LPT_TRANSCONF, TRANS_STATE_ENABLE, 0, | |
1919 | 50)) | |
8a52fd9f | 1920 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1921 | |
1922 | /* Workaround: clear timing override bit. */ | |
36c0d0cf | 1923 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1924 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1925 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
1926 | } |
1927 | ||
65f2130c VS |
1928 | enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc) |
1929 | { | |
1930 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1931 | ||
1932 | WARN_ON(!crtc->config->has_pch_encoder); | |
1933 | ||
1934 | if (HAS_PCH_LPT(dev_priv)) | |
1935 | return TRANSCODER_A; | |
1936 | else | |
1937 | return (enum transcoder) crtc->pipe; | |
1938 | } | |
1939 | ||
b24e7179 | 1940 | /** |
309cfea8 | 1941 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 1942 | * @crtc: crtc responsible for the pipe |
b24e7179 | 1943 | * |
0372264a | 1944 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 1945 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 1946 | */ |
e1fdc473 | 1947 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1948 | { |
0372264a | 1949 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1950 | struct drm_i915_private *dev_priv = to_i915(dev); |
0372264a | 1951 | enum pipe pipe = crtc->pipe; |
1a70a728 | 1952 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
f0f59a00 | 1953 | i915_reg_t reg; |
b24e7179 JB |
1954 | u32 val; |
1955 | ||
9e2ee2dd VS |
1956 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
1957 | ||
58c6eaa2 | 1958 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 1959 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
1960 | assert_sprites_disabled(dev_priv, pipe); |
1961 | ||
b24e7179 JB |
1962 | /* |
1963 | * A pipe without a PLL won't actually be able to drive bits from | |
1964 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1965 | * need the check. | |
1966 | */ | |
09fa8bb9 | 1967 | if (HAS_GMCH_DISPLAY(dev_priv)) { |
d7edc4e5 | 1968 | if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
1969 | assert_dsi_pll_enabled(dev_priv); |
1970 | else | |
1971 | assert_pll_enabled(dev_priv, pipe); | |
09fa8bb9 | 1972 | } else { |
6e3c9717 | 1973 | if (crtc->config->has_pch_encoder) { |
040484af | 1974 | /* if driving the PCH, we need FDI enabled */ |
65f2130c VS |
1975 | assert_fdi_rx_pll_enabled(dev_priv, |
1976 | (enum pipe) intel_crtc_pch_transcoder(crtc)); | |
1a240d4d DV |
1977 | assert_fdi_tx_pll_enabled(dev_priv, |
1978 | (enum pipe) cpu_transcoder); | |
040484af JB |
1979 | } |
1980 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1981 | } | |
b24e7179 | 1982 | |
702e7a56 | 1983 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1984 | val = I915_READ(reg); |
7ad25d48 | 1985 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
1986 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
1987 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 1988 | return; |
7ad25d48 | 1989 | } |
00d70b15 CW |
1990 | |
1991 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 1992 | POSTING_READ(reg); |
b7792d8b VS |
1993 | |
1994 | /* | |
1995 | * Until the pipe starts DSL will read as 0, which would cause | |
1996 | * an apparent vblank timestamp jump, which messes up also the | |
1997 | * frame count when it's derived from the timestamps. So let's | |
1998 | * wait for the pipe to start properly before we call | |
1999 | * drm_crtc_vblank_on() | |
2000 | */ | |
2001 | if (dev->max_vblank_count == 0 && | |
2002 | wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50)) | |
2003 | DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe)); | |
b24e7179 JB |
2004 | } |
2005 | ||
2006 | /** | |
309cfea8 | 2007 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2008 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2009 | * |
575f7ab7 VS |
2010 | * Disable the pipe of @crtc, making sure that various hardware |
2011 | * specific requirements are met, if applicable, e.g. plane | |
2012 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2013 | * |
2014 | * Will wait until the pipe has shut down before returning. | |
2015 | */ | |
575f7ab7 | 2016 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2017 | { |
fac5e23e | 2018 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6e3c9717 | 2019 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2020 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 2021 | i915_reg_t reg; |
b24e7179 JB |
2022 | u32 val; |
2023 | ||
9e2ee2dd VS |
2024 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
2025 | ||
b24e7179 JB |
2026 | /* |
2027 | * Make sure planes won't keep trying to pump pixels to us, | |
2028 | * or we might hang the display. | |
2029 | */ | |
2030 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2031 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2032 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2033 | |
702e7a56 | 2034 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2035 | val = I915_READ(reg); |
00d70b15 CW |
2036 | if ((val & PIPECONF_ENABLE) == 0) |
2037 | return; | |
2038 | ||
67adc644 VS |
2039 | /* |
2040 | * Double wide has implications for planes | |
2041 | * so best keep it disabled when not needed. | |
2042 | */ | |
6e3c9717 | 2043 | if (crtc->config->double_wide) |
67adc644 VS |
2044 | val &= ~PIPECONF_DOUBLE_WIDE; |
2045 | ||
2046 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2047 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2048 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2049 | val &= ~PIPECONF_ENABLE; |
2050 | ||
2051 | I915_WRITE(reg, val); | |
2052 | if ((val & PIPECONF_ENABLE) == 0) | |
2053 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2054 | } |
2055 | ||
832be82f VS |
2056 | static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) |
2057 | { | |
2058 | return IS_GEN2(dev_priv) ? 2048 : 4096; | |
2059 | } | |
2060 | ||
27ba3910 VS |
2061 | static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv, |
2062 | uint64_t fb_modifier, unsigned int cpp) | |
7b49f948 VS |
2063 | { |
2064 | switch (fb_modifier) { | |
2065 | case DRM_FORMAT_MOD_NONE: | |
2066 | return cpp; | |
2067 | case I915_FORMAT_MOD_X_TILED: | |
2068 | if (IS_GEN2(dev_priv)) | |
2069 | return 128; | |
2070 | else | |
2071 | return 512; | |
2072 | case I915_FORMAT_MOD_Y_TILED: | |
2073 | if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) | |
2074 | return 128; | |
2075 | else | |
2076 | return 512; | |
2077 | case I915_FORMAT_MOD_Yf_TILED: | |
2078 | switch (cpp) { | |
2079 | case 1: | |
2080 | return 64; | |
2081 | case 2: | |
2082 | case 4: | |
2083 | return 128; | |
2084 | case 8: | |
2085 | case 16: | |
2086 | return 256; | |
2087 | default: | |
2088 | MISSING_CASE(cpp); | |
2089 | return cpp; | |
2090 | } | |
2091 | break; | |
2092 | default: | |
2093 | MISSING_CASE(fb_modifier); | |
2094 | return cpp; | |
2095 | } | |
2096 | } | |
2097 | ||
832be82f VS |
2098 | unsigned int intel_tile_height(const struct drm_i915_private *dev_priv, |
2099 | uint64_t fb_modifier, unsigned int cpp) | |
a57ce0b2 | 2100 | { |
832be82f VS |
2101 | if (fb_modifier == DRM_FORMAT_MOD_NONE) |
2102 | return 1; | |
2103 | else | |
2104 | return intel_tile_size(dev_priv) / | |
27ba3910 | 2105 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
6761dd31 TU |
2106 | } |
2107 | ||
8d0deca8 VS |
2108 | /* Return the tile dimensions in pixel units */ |
2109 | static void intel_tile_dims(const struct drm_i915_private *dev_priv, | |
2110 | unsigned int *tile_width, | |
2111 | unsigned int *tile_height, | |
2112 | uint64_t fb_modifier, | |
2113 | unsigned int cpp) | |
2114 | { | |
2115 | unsigned int tile_width_bytes = | |
2116 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); | |
2117 | ||
2118 | *tile_width = tile_width_bytes / cpp; | |
2119 | *tile_height = intel_tile_size(dev_priv) / tile_width_bytes; | |
2120 | } | |
2121 | ||
6761dd31 TU |
2122 | unsigned int |
2123 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
832be82f | 2124 | uint32_t pixel_format, uint64_t fb_modifier) |
6761dd31 | 2125 | { |
832be82f VS |
2126 | unsigned int cpp = drm_format_plane_cpp(pixel_format, 0); |
2127 | unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp); | |
2128 | ||
2129 | return ALIGN(height, tile_height); | |
a57ce0b2 JB |
2130 | } |
2131 | ||
1663b9d6 VS |
2132 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) |
2133 | { | |
2134 | unsigned int size = 0; | |
2135 | int i; | |
2136 | ||
2137 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) | |
2138 | size += rot_info->plane[i].width * rot_info->plane[i].height; | |
2139 | ||
2140 | return size; | |
2141 | } | |
2142 | ||
75c82a53 | 2143 | static void |
3465c580 VS |
2144 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, |
2145 | const struct drm_framebuffer *fb, | |
2146 | unsigned int rotation) | |
f64b98cd | 2147 | { |
bd2ef25d | 2148 | if (drm_rotation_90_or_270(rotation)) { |
2d7a215f VS |
2149 | *view = i915_ggtt_view_rotated; |
2150 | view->params.rotated = to_intel_framebuffer(fb)->rot_info; | |
2151 | } else { | |
2152 | *view = i915_ggtt_view_normal; | |
2153 | } | |
2154 | } | |
50470bb0 | 2155 | |
603525d7 | 2156 | static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) |
4e9a86b6 VS |
2157 | { |
2158 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2159 | return 256 * 1024; | |
985b8bb4 | 2160 | else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || |
666a4537 | 2161 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
4e9a86b6 VS |
2162 | return 128 * 1024; |
2163 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2164 | return 4 * 1024; | |
2165 | else | |
44c5905e | 2166 | return 0; |
4e9a86b6 VS |
2167 | } |
2168 | ||
603525d7 VS |
2169 | static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv, |
2170 | uint64_t fb_modifier) | |
2171 | { | |
2172 | switch (fb_modifier) { | |
2173 | case DRM_FORMAT_MOD_NONE: | |
2174 | return intel_linear_alignment(dev_priv); | |
2175 | case I915_FORMAT_MOD_X_TILED: | |
2176 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2177 | return 256 * 1024; | |
2178 | return 0; | |
2179 | case I915_FORMAT_MOD_Y_TILED: | |
2180 | case I915_FORMAT_MOD_Yf_TILED: | |
2181 | return 1 * 1024 * 1024; | |
2182 | default: | |
2183 | MISSING_CASE(fb_modifier); | |
2184 | return 0; | |
2185 | } | |
2186 | } | |
2187 | ||
058d88c4 CW |
2188 | struct i915_vma * |
2189 | intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) | |
6b95a207 | 2190 | { |
850c4cdc | 2191 | struct drm_device *dev = fb->dev; |
fac5e23e | 2192 | struct drm_i915_private *dev_priv = to_i915(dev); |
850c4cdc | 2193 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2194 | struct i915_ggtt_view view; |
058d88c4 | 2195 | struct i915_vma *vma; |
6b95a207 | 2196 | u32 alignment; |
6b95a207 | 2197 | |
ebcdd39e MR |
2198 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2199 | ||
603525d7 | 2200 | alignment = intel_surf_alignment(dev_priv, fb->modifier[0]); |
6b95a207 | 2201 | |
3465c580 | 2202 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2203 | |
693db184 CW |
2204 | /* Note that the w/a also requires 64 PTE of padding following the |
2205 | * bo. We currently fill all unused PTE with the shadow page and so | |
2206 | * we should always have valid PTE following the scanout preventing | |
2207 | * the VT-d warning. | |
2208 | */ | |
48f112fe | 2209 | if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024) |
693db184 CW |
2210 | alignment = 256 * 1024; |
2211 | ||
d6dd6843 PZ |
2212 | /* |
2213 | * Global gtt pte registers are special registers which actually forward | |
2214 | * writes to a chunk of system memory. Which means that there is no risk | |
2215 | * that the register values disappear as soon as we call | |
2216 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2217 | * pin/unpin/fence and not more. | |
2218 | */ | |
2219 | intel_runtime_pm_get(dev_priv); | |
2220 | ||
058d88c4 | 2221 | vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view); |
49ef5294 CW |
2222 | if (IS_ERR(vma)) |
2223 | goto err; | |
6b95a207 | 2224 | |
05a20d09 | 2225 | if (i915_vma_is_map_and_fenceable(vma)) { |
49ef5294 CW |
2226 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
2227 | * fence, whereas 965+ only requires a fence if using | |
2228 | * framebuffer compression. For simplicity, we always, when | |
2229 | * possible, install a fence as the cost is not that onerous. | |
2230 | * | |
2231 | * If we fail to fence the tiled scanout, then either the | |
2232 | * modeset will reject the change (which is highly unlikely as | |
2233 | * the affected systems, all but one, do not have unmappable | |
2234 | * space) or we will not be able to enable full powersaving | |
2235 | * techniques (also likely not to apply due to various limits | |
2236 | * FBC and the like impose on the size of the buffer, which | |
2237 | * presumably we violated anyway with this unmappable buffer). | |
2238 | * Anyway, it is presumably better to stumble onwards with | |
2239 | * something and try to run the system in a "less than optimal" | |
2240 | * mode that matches the user configuration. | |
2241 | */ | |
2242 | if (i915_vma_get_fence(vma) == 0) | |
2243 | i915_vma_pin_fence(vma); | |
9807216f | 2244 | } |
6b95a207 | 2245 | |
49ef5294 | 2246 | err: |
d6dd6843 | 2247 | intel_runtime_pm_put(dev_priv); |
058d88c4 | 2248 | return vma; |
6b95a207 KH |
2249 | } |
2250 | ||
fb4b8ce1 | 2251 | void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) |
1690e1eb | 2252 | { |
82bc3b2d | 2253 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2254 | struct i915_ggtt_view view; |
058d88c4 | 2255 | struct i915_vma *vma; |
82bc3b2d | 2256 | |
ebcdd39e MR |
2257 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2258 | ||
3465c580 | 2259 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
05a20d09 | 2260 | vma = i915_gem_object_to_ggtt(obj, &view); |
f64b98cd | 2261 | |
49ef5294 | 2262 | i915_vma_unpin_fence(vma); |
058d88c4 | 2263 | i915_gem_object_unpin_from_display_plane(vma); |
1690e1eb CW |
2264 | } |
2265 | ||
ef78ec94 VS |
2266 | static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane, |
2267 | unsigned int rotation) | |
2268 | { | |
bd2ef25d | 2269 | if (drm_rotation_90_or_270(rotation)) |
ef78ec94 VS |
2270 | return to_intel_framebuffer(fb)->rotated[plane].pitch; |
2271 | else | |
2272 | return fb->pitches[plane]; | |
2273 | } | |
2274 | ||
6687c906 VS |
2275 | /* |
2276 | * Convert the x/y offsets into a linear offset. | |
2277 | * Only valid with 0/180 degree rotation, which is fine since linear | |
2278 | * offset is only used with linear buffers on pre-hsw and tiled buffers | |
2279 | * with gen2/3, and 90/270 degree rotations isn't supported on any of them. | |
2280 | */ | |
2281 | u32 intel_fb_xy_to_linear(int x, int y, | |
2949056c VS |
2282 | const struct intel_plane_state *state, |
2283 | int plane) | |
6687c906 | 2284 | { |
2949056c | 2285 | const struct drm_framebuffer *fb = state->base.fb; |
6687c906 VS |
2286 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); |
2287 | unsigned int pitch = fb->pitches[plane]; | |
2288 | ||
2289 | return y * pitch + x * cpp; | |
2290 | } | |
2291 | ||
2292 | /* | |
2293 | * Add the x/y offsets derived from fb->offsets[] to the user | |
2294 | * specified plane src x/y offsets. The resulting x/y offsets | |
2295 | * specify the start of scanout from the beginning of the gtt mapping. | |
2296 | */ | |
2297 | void intel_add_fb_offsets(int *x, int *y, | |
2949056c VS |
2298 | const struct intel_plane_state *state, |
2299 | int plane) | |
6687c906 VS |
2300 | |
2301 | { | |
2949056c VS |
2302 | const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb); |
2303 | unsigned int rotation = state->base.rotation; | |
6687c906 | 2304 | |
bd2ef25d | 2305 | if (drm_rotation_90_or_270(rotation)) { |
6687c906 VS |
2306 | *x += intel_fb->rotated[plane].x; |
2307 | *y += intel_fb->rotated[plane].y; | |
2308 | } else { | |
2309 | *x += intel_fb->normal[plane].x; | |
2310 | *y += intel_fb->normal[plane].y; | |
2311 | } | |
2312 | } | |
2313 | ||
29cf9491 | 2314 | /* |
29cf9491 VS |
2315 | * Input tile dimensions and pitch must already be |
2316 | * rotated to match x and y, and in pixel units. | |
2317 | */ | |
66a2d927 VS |
2318 | static u32 _intel_adjust_tile_offset(int *x, int *y, |
2319 | unsigned int tile_width, | |
2320 | unsigned int tile_height, | |
2321 | unsigned int tile_size, | |
2322 | unsigned int pitch_tiles, | |
2323 | u32 old_offset, | |
2324 | u32 new_offset) | |
29cf9491 | 2325 | { |
b9b24038 | 2326 | unsigned int pitch_pixels = pitch_tiles * tile_width; |
29cf9491 VS |
2327 | unsigned int tiles; |
2328 | ||
2329 | WARN_ON(old_offset & (tile_size - 1)); | |
2330 | WARN_ON(new_offset & (tile_size - 1)); | |
2331 | WARN_ON(new_offset > old_offset); | |
2332 | ||
2333 | tiles = (old_offset - new_offset) / tile_size; | |
2334 | ||
2335 | *y += tiles / pitch_tiles * tile_height; | |
2336 | *x += tiles % pitch_tiles * tile_width; | |
2337 | ||
b9b24038 VS |
2338 | /* minimize x in case it got needlessly big */ |
2339 | *y += *x / pitch_pixels * tile_height; | |
2340 | *x %= pitch_pixels; | |
2341 | ||
29cf9491 VS |
2342 | return new_offset; |
2343 | } | |
2344 | ||
66a2d927 VS |
2345 | /* |
2346 | * Adjust the tile offset by moving the difference into | |
2347 | * the x/y offsets. | |
2348 | */ | |
2349 | static u32 intel_adjust_tile_offset(int *x, int *y, | |
2350 | const struct intel_plane_state *state, int plane, | |
2351 | u32 old_offset, u32 new_offset) | |
2352 | { | |
2353 | const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev); | |
2354 | const struct drm_framebuffer *fb = state->base.fb; | |
2355 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); | |
2356 | unsigned int rotation = state->base.rotation; | |
2357 | unsigned int pitch = intel_fb_pitch(fb, plane, rotation); | |
2358 | ||
2359 | WARN_ON(new_offset > old_offset); | |
2360 | ||
2361 | if (fb->modifier[plane] != DRM_FORMAT_MOD_NONE) { | |
2362 | unsigned int tile_size, tile_width, tile_height; | |
2363 | unsigned int pitch_tiles; | |
2364 | ||
2365 | tile_size = intel_tile_size(dev_priv); | |
2366 | intel_tile_dims(dev_priv, &tile_width, &tile_height, | |
2367 | fb->modifier[plane], cpp); | |
2368 | ||
bd2ef25d | 2369 | if (drm_rotation_90_or_270(rotation)) { |
66a2d927 VS |
2370 | pitch_tiles = pitch / tile_height; |
2371 | swap(tile_width, tile_height); | |
2372 | } else { | |
2373 | pitch_tiles = pitch / (tile_width * cpp); | |
2374 | } | |
2375 | ||
2376 | _intel_adjust_tile_offset(x, y, tile_width, tile_height, | |
2377 | tile_size, pitch_tiles, | |
2378 | old_offset, new_offset); | |
2379 | } else { | |
2380 | old_offset += *y * pitch + *x * cpp; | |
2381 | ||
2382 | *y = (old_offset - new_offset) / pitch; | |
2383 | *x = ((old_offset - new_offset) - *y * pitch) / cpp; | |
2384 | } | |
2385 | ||
2386 | return new_offset; | |
2387 | } | |
2388 | ||
8d0deca8 VS |
2389 | /* |
2390 | * Computes the linear offset to the base tile and adjusts | |
2391 | * x, y. bytes per pixel is assumed to be a power-of-two. | |
2392 | * | |
2393 | * In the 90/270 rotated case, x and y are assumed | |
2394 | * to be already rotated to match the rotated GTT view, and | |
2395 | * pitch is the tile_height aligned framebuffer height. | |
6687c906 VS |
2396 | * |
2397 | * This function is used when computing the derived information | |
2398 | * under intel_framebuffer, so using any of that information | |
2399 | * here is not allowed. Anything under drm_framebuffer can be | |
2400 | * used. This is why the user has to pass in the pitch since it | |
2401 | * is specified in the rotated orientation. | |
8d0deca8 | 2402 | */ |
6687c906 VS |
2403 | static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv, |
2404 | int *x, int *y, | |
2405 | const struct drm_framebuffer *fb, int plane, | |
2406 | unsigned int pitch, | |
2407 | unsigned int rotation, | |
2408 | u32 alignment) | |
c2c75131 | 2409 | { |
4f2d9934 VS |
2410 | uint64_t fb_modifier = fb->modifier[plane]; |
2411 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); | |
6687c906 | 2412 | u32 offset, offset_aligned; |
29cf9491 | 2413 | |
29cf9491 VS |
2414 | if (alignment) |
2415 | alignment--; | |
2416 | ||
b5c65338 | 2417 | if (fb_modifier != DRM_FORMAT_MOD_NONE) { |
8d0deca8 VS |
2418 | unsigned int tile_size, tile_width, tile_height; |
2419 | unsigned int tile_rows, tiles, pitch_tiles; | |
c2c75131 | 2420 | |
d843310d | 2421 | tile_size = intel_tile_size(dev_priv); |
8d0deca8 VS |
2422 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2423 | fb_modifier, cpp); | |
2424 | ||
bd2ef25d | 2425 | if (drm_rotation_90_or_270(rotation)) { |
8d0deca8 VS |
2426 | pitch_tiles = pitch / tile_height; |
2427 | swap(tile_width, tile_height); | |
2428 | } else { | |
2429 | pitch_tiles = pitch / (tile_width * cpp); | |
2430 | } | |
d843310d VS |
2431 | |
2432 | tile_rows = *y / tile_height; | |
2433 | *y %= tile_height; | |
c2c75131 | 2434 | |
8d0deca8 VS |
2435 | tiles = *x / tile_width; |
2436 | *x %= tile_width; | |
bc752862 | 2437 | |
29cf9491 VS |
2438 | offset = (tile_rows * pitch_tiles + tiles) * tile_size; |
2439 | offset_aligned = offset & ~alignment; | |
bc752862 | 2440 | |
66a2d927 VS |
2441 | _intel_adjust_tile_offset(x, y, tile_width, tile_height, |
2442 | tile_size, pitch_tiles, | |
2443 | offset, offset_aligned); | |
29cf9491 | 2444 | } else { |
bc752862 | 2445 | offset = *y * pitch + *x * cpp; |
29cf9491 VS |
2446 | offset_aligned = offset & ~alignment; |
2447 | ||
4e9a86b6 VS |
2448 | *y = (offset & alignment) / pitch; |
2449 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
bc752862 | 2450 | } |
29cf9491 VS |
2451 | |
2452 | return offset_aligned; | |
c2c75131 DV |
2453 | } |
2454 | ||
6687c906 | 2455 | u32 intel_compute_tile_offset(int *x, int *y, |
2949056c VS |
2456 | const struct intel_plane_state *state, |
2457 | int plane) | |
6687c906 | 2458 | { |
2949056c VS |
2459 | const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev); |
2460 | const struct drm_framebuffer *fb = state->base.fb; | |
2461 | unsigned int rotation = state->base.rotation; | |
ef78ec94 | 2462 | int pitch = intel_fb_pitch(fb, plane, rotation); |
8d970654 VS |
2463 | u32 alignment; |
2464 | ||
2465 | /* AUX_DIST needs only 4K alignment */ | |
2466 | if (fb->pixel_format == DRM_FORMAT_NV12 && plane == 1) | |
2467 | alignment = 4096; | |
2468 | else | |
2469 | alignment = intel_surf_alignment(dev_priv, fb->modifier[plane]); | |
6687c906 VS |
2470 | |
2471 | return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch, | |
2472 | rotation, alignment); | |
2473 | } | |
2474 | ||
2475 | /* Convert the fb->offset[] linear offset into x/y offsets */ | |
2476 | static void intel_fb_offset_to_xy(int *x, int *y, | |
2477 | const struct drm_framebuffer *fb, int plane) | |
2478 | { | |
2479 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); | |
2480 | unsigned int pitch = fb->pitches[plane]; | |
2481 | u32 linear_offset = fb->offsets[plane]; | |
2482 | ||
2483 | *y = linear_offset / pitch; | |
2484 | *x = linear_offset % pitch / cpp; | |
2485 | } | |
2486 | ||
72618ebf VS |
2487 | static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier) |
2488 | { | |
2489 | switch (fb_modifier) { | |
2490 | case I915_FORMAT_MOD_X_TILED: | |
2491 | return I915_TILING_X; | |
2492 | case I915_FORMAT_MOD_Y_TILED: | |
2493 | return I915_TILING_Y; | |
2494 | default: | |
2495 | return I915_TILING_NONE; | |
2496 | } | |
2497 | } | |
2498 | ||
6687c906 VS |
2499 | static int |
2500 | intel_fill_fb_info(struct drm_i915_private *dev_priv, | |
2501 | struct drm_framebuffer *fb) | |
2502 | { | |
2503 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
2504 | struct intel_rotation_info *rot_info = &intel_fb->rot_info; | |
2505 | u32 gtt_offset_rotated = 0; | |
2506 | unsigned int max_size = 0; | |
2507 | uint32_t format = fb->pixel_format; | |
2508 | int i, num_planes = drm_format_num_planes(format); | |
2509 | unsigned int tile_size = intel_tile_size(dev_priv); | |
2510 | ||
2511 | for (i = 0; i < num_planes; i++) { | |
2512 | unsigned int width, height; | |
2513 | unsigned int cpp, size; | |
2514 | u32 offset; | |
2515 | int x, y; | |
2516 | ||
2517 | cpp = drm_format_plane_cpp(format, i); | |
2518 | width = drm_format_plane_width(fb->width, format, i); | |
2519 | height = drm_format_plane_height(fb->height, format, i); | |
2520 | ||
2521 | intel_fb_offset_to_xy(&x, &y, fb, i); | |
2522 | ||
60d5f2a4 VS |
2523 | /* |
2524 | * The fence (if used) is aligned to the start of the object | |
2525 | * so having the framebuffer wrap around across the edge of the | |
2526 | * fenced region doesn't really work. We have no API to configure | |
2527 | * the fence start offset within the object (nor could we probably | |
2528 | * on gen2/3). So it's just easier if we just require that the | |
2529 | * fb layout agrees with the fence layout. We already check that the | |
2530 | * fb stride matches the fence stride elsewhere. | |
2531 | */ | |
2532 | if (i915_gem_object_is_tiled(intel_fb->obj) && | |
2533 | (x + width) * cpp > fb->pitches[i]) { | |
2534 | DRM_DEBUG("bad fb plane %d offset: 0x%x\n", | |
2535 | i, fb->offsets[i]); | |
2536 | return -EINVAL; | |
2537 | } | |
2538 | ||
6687c906 VS |
2539 | /* |
2540 | * First pixel of the framebuffer from | |
2541 | * the start of the normal gtt mapping. | |
2542 | */ | |
2543 | intel_fb->normal[i].x = x; | |
2544 | intel_fb->normal[i].y = y; | |
2545 | ||
2546 | offset = _intel_compute_tile_offset(dev_priv, &x, &y, | |
2547 | fb, 0, fb->pitches[i], | |
cc926387 | 2548 | DRM_ROTATE_0, tile_size); |
6687c906 VS |
2549 | offset /= tile_size; |
2550 | ||
2551 | if (fb->modifier[i] != DRM_FORMAT_MOD_NONE) { | |
2552 | unsigned int tile_width, tile_height; | |
2553 | unsigned int pitch_tiles; | |
2554 | struct drm_rect r; | |
2555 | ||
2556 | intel_tile_dims(dev_priv, &tile_width, &tile_height, | |
2557 | fb->modifier[i], cpp); | |
2558 | ||
2559 | rot_info->plane[i].offset = offset; | |
2560 | rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp); | |
2561 | rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width); | |
2562 | rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height); | |
2563 | ||
2564 | intel_fb->rotated[i].pitch = | |
2565 | rot_info->plane[i].height * tile_height; | |
2566 | ||
2567 | /* how many tiles does this plane need */ | |
2568 | size = rot_info->plane[i].stride * rot_info->plane[i].height; | |
2569 | /* | |
2570 | * If the plane isn't horizontally tile aligned, | |
2571 | * we need one more tile. | |
2572 | */ | |
2573 | if (x != 0) | |
2574 | size++; | |
2575 | ||
2576 | /* rotate the x/y offsets to match the GTT view */ | |
2577 | r.x1 = x; | |
2578 | r.y1 = y; | |
2579 | r.x2 = x + width; | |
2580 | r.y2 = y + height; | |
2581 | drm_rect_rotate(&r, | |
2582 | rot_info->plane[i].width * tile_width, | |
2583 | rot_info->plane[i].height * tile_height, | |
cc926387 | 2584 | DRM_ROTATE_270); |
6687c906 VS |
2585 | x = r.x1; |
2586 | y = r.y1; | |
2587 | ||
2588 | /* rotate the tile dimensions to match the GTT view */ | |
2589 | pitch_tiles = intel_fb->rotated[i].pitch / tile_height; | |
2590 | swap(tile_width, tile_height); | |
2591 | ||
2592 | /* | |
2593 | * We only keep the x/y offsets, so push all of the | |
2594 | * gtt offset into the x/y offsets. | |
2595 | */ | |
66a2d927 VS |
2596 | _intel_adjust_tile_offset(&x, &y, tile_size, |
2597 | tile_width, tile_height, pitch_tiles, | |
2598 | gtt_offset_rotated * tile_size, 0); | |
6687c906 VS |
2599 | |
2600 | gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height; | |
2601 | ||
2602 | /* | |
2603 | * First pixel of the framebuffer from | |
2604 | * the start of the rotated gtt mapping. | |
2605 | */ | |
2606 | intel_fb->rotated[i].x = x; | |
2607 | intel_fb->rotated[i].y = y; | |
2608 | } else { | |
2609 | size = DIV_ROUND_UP((y + height) * fb->pitches[i] + | |
2610 | x * cpp, tile_size); | |
2611 | } | |
2612 | ||
2613 | /* how many tiles in total needed in the bo */ | |
2614 | max_size = max(max_size, offset + size); | |
2615 | } | |
2616 | ||
2617 | if (max_size * tile_size > to_intel_framebuffer(fb)->obj->base.size) { | |
2618 | DRM_DEBUG("fb too big for bo (need %u bytes, have %zu bytes)\n", | |
2619 | max_size * tile_size, to_intel_framebuffer(fb)->obj->base.size); | |
2620 | return -EINVAL; | |
2621 | } | |
2622 | ||
2623 | return 0; | |
2624 | } | |
2625 | ||
b35d63fa | 2626 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2627 | { |
2628 | switch (format) { | |
2629 | case DISPPLANE_8BPP: | |
2630 | return DRM_FORMAT_C8; | |
2631 | case DISPPLANE_BGRX555: | |
2632 | return DRM_FORMAT_XRGB1555; | |
2633 | case DISPPLANE_BGRX565: | |
2634 | return DRM_FORMAT_RGB565; | |
2635 | default: | |
2636 | case DISPPLANE_BGRX888: | |
2637 | return DRM_FORMAT_XRGB8888; | |
2638 | case DISPPLANE_RGBX888: | |
2639 | return DRM_FORMAT_XBGR8888; | |
2640 | case DISPPLANE_BGRX101010: | |
2641 | return DRM_FORMAT_XRGB2101010; | |
2642 | case DISPPLANE_RGBX101010: | |
2643 | return DRM_FORMAT_XBGR2101010; | |
2644 | } | |
2645 | } | |
2646 | ||
bc8d7dff DL |
2647 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2648 | { | |
2649 | switch (format) { | |
2650 | case PLANE_CTL_FORMAT_RGB_565: | |
2651 | return DRM_FORMAT_RGB565; | |
2652 | default: | |
2653 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2654 | if (rgb_order) { | |
2655 | if (alpha) | |
2656 | return DRM_FORMAT_ABGR8888; | |
2657 | else | |
2658 | return DRM_FORMAT_XBGR8888; | |
2659 | } else { | |
2660 | if (alpha) | |
2661 | return DRM_FORMAT_ARGB8888; | |
2662 | else | |
2663 | return DRM_FORMAT_XRGB8888; | |
2664 | } | |
2665 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2666 | if (rgb_order) | |
2667 | return DRM_FORMAT_XBGR2101010; | |
2668 | else | |
2669 | return DRM_FORMAT_XRGB2101010; | |
2670 | } | |
2671 | } | |
2672 | ||
5724dbd1 | 2673 | static bool |
f6936e29 DV |
2674 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2675 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2676 | { |
2677 | struct drm_device *dev = crtc->base.dev; | |
3badb49f | 2678 | struct drm_i915_private *dev_priv = to_i915(dev); |
72e96d64 | 2679 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
46f297fb JB |
2680 | struct drm_i915_gem_object *obj = NULL; |
2681 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2682 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2683 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2684 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2685 | PAGE_SIZE); | |
2686 | ||
2687 | size_aligned -= base_aligned; | |
46f297fb | 2688 | |
ff2652ea CW |
2689 | if (plane_config->size == 0) |
2690 | return false; | |
2691 | ||
3badb49f PZ |
2692 | /* If the FB is too big, just don't use it since fbdev is not very |
2693 | * important and we should probably use that space with FBC or other | |
2694 | * features. */ | |
72e96d64 | 2695 | if (size_aligned * 2 > ggtt->stolen_usable_size) |
3badb49f PZ |
2696 | return false; |
2697 | ||
12c83d99 TU |
2698 | mutex_lock(&dev->struct_mutex); |
2699 | ||
f37b5c2b DV |
2700 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2701 | base_aligned, | |
2702 | base_aligned, | |
2703 | size_aligned); | |
12c83d99 TU |
2704 | if (!obj) { |
2705 | mutex_unlock(&dev->struct_mutex); | |
484b41dd | 2706 | return false; |
12c83d99 | 2707 | } |
46f297fb | 2708 | |
3e510a8e CW |
2709 | if (plane_config->tiling == I915_TILING_X) |
2710 | obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X; | |
46f297fb | 2711 | |
6bf129df DL |
2712 | mode_cmd.pixel_format = fb->pixel_format; |
2713 | mode_cmd.width = fb->width; | |
2714 | mode_cmd.height = fb->height; | |
2715 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2716 | mode_cmd.modifier[0] = fb->modifier[0]; |
2717 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb | 2718 | |
6bf129df | 2719 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2720 | &mode_cmd, obj)) { |
46f297fb JB |
2721 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2722 | goto out_unref_obj; | |
2723 | } | |
12c83d99 | 2724 | |
46f297fb | 2725 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2726 | |
f6936e29 | 2727 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2728 | return true; |
46f297fb JB |
2729 | |
2730 | out_unref_obj: | |
f8c417cd | 2731 | i915_gem_object_put(obj); |
46f297fb | 2732 | mutex_unlock(&dev->struct_mutex); |
484b41dd JB |
2733 | return false; |
2734 | } | |
2735 | ||
5a21b665 DV |
2736 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2737 | static void | |
2738 | update_state_fb(struct drm_plane *plane) | |
2739 | { | |
2740 | if (plane->fb == plane->state->fb) | |
2741 | return; | |
2742 | ||
2743 | if (plane->state->fb) | |
2744 | drm_framebuffer_unreference(plane->state->fb); | |
2745 | plane->state->fb = plane->fb; | |
2746 | if (plane->state->fb) | |
2747 | drm_framebuffer_reference(plane->state->fb); | |
2748 | } | |
2749 | ||
5724dbd1 | 2750 | static void |
f6936e29 DV |
2751 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2752 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2753 | { |
2754 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 2755 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd JB |
2756 | struct drm_crtc *c; |
2757 | struct intel_crtc *i; | |
2ff8fde1 | 2758 | struct drm_i915_gem_object *obj; |
88595ac9 | 2759 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2760 | struct drm_plane_state *plane_state = primary->state; |
200757f5 MR |
2761 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
2762 | struct intel_plane *intel_plane = to_intel_plane(primary); | |
0a8d8a86 MR |
2763 | struct intel_plane_state *intel_state = |
2764 | to_intel_plane_state(plane_state); | |
88595ac9 | 2765 | struct drm_framebuffer *fb; |
484b41dd | 2766 | |
2d14030b | 2767 | if (!plane_config->fb) |
484b41dd JB |
2768 | return; |
2769 | ||
f6936e29 | 2770 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2771 | fb = &plane_config->fb->base; |
2772 | goto valid_fb; | |
f55548b5 | 2773 | } |
484b41dd | 2774 | |
2d14030b | 2775 | kfree(plane_config->fb); |
484b41dd JB |
2776 | |
2777 | /* | |
2778 | * Failed to alloc the obj, check to see if we should share | |
2779 | * an fb with another CRTC instead | |
2780 | */ | |
70e1e0ec | 2781 | for_each_crtc(dev, c) { |
484b41dd JB |
2782 | i = to_intel_crtc(c); |
2783 | ||
2784 | if (c == &intel_crtc->base) | |
2785 | continue; | |
2786 | ||
2ff8fde1 MR |
2787 | if (!i->active) |
2788 | continue; | |
2789 | ||
88595ac9 DV |
2790 | fb = c->primary->fb; |
2791 | if (!fb) | |
484b41dd JB |
2792 | continue; |
2793 | ||
88595ac9 | 2794 | obj = intel_fb_obj(fb); |
058d88c4 | 2795 | if (i915_gem_object_ggtt_offset(obj, NULL) == plane_config->base) { |
88595ac9 DV |
2796 | drm_framebuffer_reference(fb); |
2797 | goto valid_fb; | |
484b41dd JB |
2798 | } |
2799 | } | |
88595ac9 | 2800 | |
200757f5 MR |
2801 | /* |
2802 | * We've failed to reconstruct the BIOS FB. Current display state | |
2803 | * indicates that the primary plane is visible, but has a NULL FB, | |
2804 | * which will lead to problems later if we don't fix it up. The | |
2805 | * simplest solution is to just disable the primary plane now and | |
2806 | * pretend the BIOS never had it enabled. | |
2807 | */ | |
936e71e3 | 2808 | to_intel_plane_state(plane_state)->base.visible = false; |
200757f5 | 2809 | crtc_state->plane_mask &= ~(1 << drm_plane_index(primary)); |
2622a081 | 2810 | intel_pre_disable_primary_noatomic(&intel_crtc->base); |
200757f5 MR |
2811 | intel_plane->disable_plane(primary, &intel_crtc->base); |
2812 | ||
88595ac9 DV |
2813 | return; |
2814 | ||
2815 | valid_fb: | |
f44e2659 VS |
2816 | plane_state->src_x = 0; |
2817 | plane_state->src_y = 0; | |
be5651f2 ML |
2818 | plane_state->src_w = fb->width << 16; |
2819 | plane_state->src_h = fb->height << 16; | |
2820 | ||
f44e2659 VS |
2821 | plane_state->crtc_x = 0; |
2822 | plane_state->crtc_y = 0; | |
be5651f2 ML |
2823 | plane_state->crtc_w = fb->width; |
2824 | plane_state->crtc_h = fb->height; | |
2825 | ||
936e71e3 VS |
2826 | intel_state->base.src.x1 = plane_state->src_x; |
2827 | intel_state->base.src.y1 = plane_state->src_y; | |
2828 | intel_state->base.src.x2 = plane_state->src_x + plane_state->src_w; | |
2829 | intel_state->base.src.y2 = plane_state->src_y + plane_state->src_h; | |
2830 | intel_state->base.dst.x1 = plane_state->crtc_x; | |
2831 | intel_state->base.dst.y1 = plane_state->crtc_y; | |
2832 | intel_state->base.dst.x2 = plane_state->crtc_x + plane_state->crtc_w; | |
2833 | intel_state->base.dst.y2 = plane_state->crtc_y + plane_state->crtc_h; | |
0a8d8a86 | 2834 | |
88595ac9 | 2835 | obj = intel_fb_obj(fb); |
3e510a8e | 2836 | if (i915_gem_object_is_tiled(obj)) |
88595ac9 DV |
2837 | dev_priv->preserve_bios_swizzle = true; |
2838 | ||
be5651f2 ML |
2839 | drm_framebuffer_reference(fb); |
2840 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2841 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
36750f28 | 2842 | intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); |
faf5bf0a CW |
2843 | atomic_or(to_intel_plane(primary)->frontbuffer_bit, |
2844 | &obj->frontbuffer_bits); | |
46f297fb JB |
2845 | } |
2846 | ||
b63a16f6 VS |
2847 | static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane, |
2848 | unsigned int rotation) | |
2849 | { | |
2850 | int cpp = drm_format_plane_cpp(fb->pixel_format, plane); | |
2851 | ||
2852 | switch (fb->modifier[plane]) { | |
2853 | case DRM_FORMAT_MOD_NONE: | |
2854 | case I915_FORMAT_MOD_X_TILED: | |
2855 | switch (cpp) { | |
2856 | case 8: | |
2857 | return 4096; | |
2858 | case 4: | |
2859 | case 2: | |
2860 | case 1: | |
2861 | return 8192; | |
2862 | default: | |
2863 | MISSING_CASE(cpp); | |
2864 | break; | |
2865 | } | |
2866 | break; | |
2867 | case I915_FORMAT_MOD_Y_TILED: | |
2868 | case I915_FORMAT_MOD_Yf_TILED: | |
2869 | switch (cpp) { | |
2870 | case 8: | |
2871 | return 2048; | |
2872 | case 4: | |
2873 | return 4096; | |
2874 | case 2: | |
2875 | case 1: | |
2876 | return 8192; | |
2877 | default: | |
2878 | MISSING_CASE(cpp); | |
2879 | break; | |
2880 | } | |
2881 | break; | |
2882 | default: | |
2883 | MISSING_CASE(fb->modifier[plane]); | |
2884 | } | |
2885 | ||
2886 | return 2048; | |
2887 | } | |
2888 | ||
2889 | static int skl_check_main_surface(struct intel_plane_state *plane_state) | |
2890 | { | |
2891 | const struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev); | |
2892 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
2893 | unsigned int rotation = plane_state->base.rotation; | |
cc926387 DV |
2894 | int x = plane_state->base.src.x1 >> 16; |
2895 | int y = plane_state->base.src.y1 >> 16; | |
2896 | int w = drm_rect_width(&plane_state->base.src) >> 16; | |
2897 | int h = drm_rect_height(&plane_state->base.src) >> 16; | |
b63a16f6 VS |
2898 | int max_width = skl_max_plane_width(fb, 0, rotation); |
2899 | int max_height = 4096; | |
8d970654 | 2900 | u32 alignment, offset, aux_offset = plane_state->aux.offset; |
b63a16f6 VS |
2901 | |
2902 | if (w > max_width || h > max_height) { | |
2903 | DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n", | |
2904 | w, h, max_width, max_height); | |
2905 | return -EINVAL; | |
2906 | } | |
2907 | ||
2908 | intel_add_fb_offsets(&x, &y, plane_state, 0); | |
2909 | offset = intel_compute_tile_offset(&x, &y, plane_state, 0); | |
2910 | ||
2911 | alignment = intel_surf_alignment(dev_priv, fb->modifier[0]); | |
2912 | ||
8d970654 VS |
2913 | /* |
2914 | * AUX surface offset is specified as the distance from the | |
2915 | * main surface offset, and it must be non-negative. Make | |
2916 | * sure that is what we will get. | |
2917 | */ | |
2918 | if (offset > aux_offset) | |
2919 | offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, | |
2920 | offset, aux_offset & ~(alignment - 1)); | |
2921 | ||
b63a16f6 VS |
2922 | /* |
2923 | * When using an X-tiled surface, the plane blows up | |
2924 | * if the x offset + width exceed the stride. | |
2925 | * | |
2926 | * TODO: linear and Y-tiled seem fine, Yf untested, | |
2927 | */ | |
2928 | if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) { | |
2929 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); | |
2930 | ||
2931 | while ((x + w) * cpp > fb->pitches[0]) { | |
2932 | if (offset == 0) { | |
2933 | DRM_DEBUG_KMS("Unable to find suitable display surface offset\n"); | |
2934 | return -EINVAL; | |
2935 | } | |
2936 | ||
2937 | offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, | |
2938 | offset, offset - alignment); | |
2939 | } | |
2940 | } | |
2941 | ||
2942 | plane_state->main.offset = offset; | |
2943 | plane_state->main.x = x; | |
2944 | plane_state->main.y = y; | |
2945 | ||
2946 | return 0; | |
2947 | } | |
2948 | ||
8d970654 VS |
2949 | static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) |
2950 | { | |
2951 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
2952 | unsigned int rotation = plane_state->base.rotation; | |
2953 | int max_width = skl_max_plane_width(fb, 1, rotation); | |
2954 | int max_height = 4096; | |
cc926387 DV |
2955 | int x = plane_state->base.src.x1 >> 17; |
2956 | int y = plane_state->base.src.y1 >> 17; | |
2957 | int w = drm_rect_width(&plane_state->base.src) >> 17; | |
2958 | int h = drm_rect_height(&plane_state->base.src) >> 17; | |
8d970654 VS |
2959 | u32 offset; |
2960 | ||
2961 | intel_add_fb_offsets(&x, &y, plane_state, 1); | |
2962 | offset = intel_compute_tile_offset(&x, &y, plane_state, 1); | |
2963 | ||
2964 | /* FIXME not quite sure how/if these apply to the chroma plane */ | |
2965 | if (w > max_width || h > max_height) { | |
2966 | DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n", | |
2967 | w, h, max_width, max_height); | |
2968 | return -EINVAL; | |
2969 | } | |
2970 | ||
2971 | plane_state->aux.offset = offset; | |
2972 | plane_state->aux.x = x; | |
2973 | plane_state->aux.y = y; | |
2974 | ||
2975 | return 0; | |
2976 | } | |
2977 | ||
b63a16f6 VS |
2978 | int skl_check_plane_surface(struct intel_plane_state *plane_state) |
2979 | { | |
2980 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
2981 | unsigned int rotation = plane_state->base.rotation; | |
2982 | int ret; | |
2983 | ||
2984 | /* Rotate src coordinates to match rotated GTT view */ | |
bd2ef25d | 2985 | if (drm_rotation_90_or_270(rotation)) |
cc926387 | 2986 | drm_rect_rotate(&plane_state->base.src, |
da064b47 VS |
2987 | fb->width << 16, fb->height << 16, |
2988 | DRM_ROTATE_270); | |
b63a16f6 | 2989 | |
8d970654 VS |
2990 | /* |
2991 | * Handle the AUX surface first since | |
2992 | * the main surface setup depends on it. | |
2993 | */ | |
2994 | if (fb->pixel_format == DRM_FORMAT_NV12) { | |
2995 | ret = skl_check_nv12_aux_surface(plane_state); | |
2996 | if (ret) | |
2997 | return ret; | |
2998 | } else { | |
2999 | plane_state->aux.offset = ~0xfff; | |
3000 | plane_state->aux.x = 0; | |
3001 | plane_state->aux.y = 0; | |
3002 | } | |
3003 | ||
b63a16f6 VS |
3004 | ret = skl_check_main_surface(plane_state); |
3005 | if (ret) | |
3006 | return ret; | |
3007 | ||
3008 | return 0; | |
3009 | } | |
3010 | ||
a8d201af ML |
3011 | static void i9xx_update_primary_plane(struct drm_plane *primary, |
3012 | const struct intel_crtc_state *crtc_state, | |
3013 | const struct intel_plane_state *plane_state) | |
81255565 | 3014 | { |
a8d201af | 3015 | struct drm_device *dev = primary->dev; |
fac5e23e | 3016 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8d201af ML |
3017 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
3018 | struct drm_framebuffer *fb = plane_state->base.fb; | |
3019 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
81255565 | 3020 | int plane = intel_crtc->plane; |
54ea9da8 | 3021 | u32 linear_offset; |
81255565 | 3022 | u32 dspcntr; |
f0f59a00 | 3023 | i915_reg_t reg = DSPCNTR(plane); |
8d0deca8 | 3024 | unsigned int rotation = plane_state->base.rotation; |
936e71e3 VS |
3025 | int x = plane_state->base.src.x1 >> 16; |
3026 | int y = plane_state->base.src.y1 >> 16; | |
c9ba6fad | 3027 | |
f45651ba VS |
3028 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
3029 | ||
fdd508a6 | 3030 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
3031 | |
3032 | if (INTEL_INFO(dev)->gen < 4) { | |
3033 | if (intel_crtc->pipe == PIPE_B) | |
3034 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
3035 | ||
3036 | /* pipesrc and dspsize control the size that is scaled from, | |
3037 | * which should always be the user's requested size. | |
3038 | */ | |
3039 | I915_WRITE(DSPSIZE(plane), | |
a8d201af ML |
3040 | ((crtc_state->pipe_src_h - 1) << 16) | |
3041 | (crtc_state->pipe_src_w - 1)); | |
f45651ba | 3042 | I915_WRITE(DSPPOS(plane), 0); |
920a14b2 | 3043 | } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) { |
c14b0485 | 3044 | I915_WRITE(PRIMSIZE(plane), |
a8d201af ML |
3045 | ((crtc_state->pipe_src_h - 1) << 16) | |
3046 | (crtc_state->pipe_src_w - 1)); | |
c14b0485 VS |
3047 | I915_WRITE(PRIMPOS(plane), 0); |
3048 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 3049 | } |
81255565 | 3050 | |
57779d06 VS |
3051 | switch (fb->pixel_format) { |
3052 | case DRM_FORMAT_C8: | |
81255565 JB |
3053 | dspcntr |= DISPPLANE_8BPP; |
3054 | break; | |
57779d06 | 3055 | case DRM_FORMAT_XRGB1555: |
57779d06 | 3056 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 3057 | break; |
57779d06 VS |
3058 | case DRM_FORMAT_RGB565: |
3059 | dspcntr |= DISPPLANE_BGRX565; | |
3060 | break; | |
3061 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
3062 | dspcntr |= DISPPLANE_BGRX888; |
3063 | break; | |
3064 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
3065 | dspcntr |= DISPPLANE_RGBX888; |
3066 | break; | |
3067 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
3068 | dspcntr |= DISPPLANE_BGRX101010; |
3069 | break; | |
3070 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 3071 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
3072 | break; |
3073 | default: | |
baba133a | 3074 | BUG(); |
81255565 | 3075 | } |
57779d06 | 3076 | |
72618ebf VS |
3077 | if (INTEL_GEN(dev_priv) >= 4 && |
3078 | fb->modifier[0] == I915_FORMAT_MOD_X_TILED) | |
f45651ba | 3079 | dspcntr |= DISPPLANE_TILED; |
81255565 | 3080 | |
9beb5fea | 3081 | if (IS_G4X(dev_priv)) |
de1aa629 VS |
3082 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
3083 | ||
2949056c | 3084 | intel_add_fb_offsets(&x, &y, plane_state, 0); |
81255565 | 3085 | |
6687c906 | 3086 | if (INTEL_INFO(dev)->gen >= 4) |
c2c75131 | 3087 | intel_crtc->dspaddr_offset = |
2949056c | 3088 | intel_compute_tile_offset(&x, &y, plane_state, 0); |
e506a0c6 | 3089 | |
31ad61e4 | 3090 | if (rotation == DRM_ROTATE_180) { |
48404c1e SJ |
3091 | dspcntr |= DISPPLANE_ROTATE_180; |
3092 | ||
a8d201af ML |
3093 | x += (crtc_state->pipe_src_w - 1); |
3094 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
3095 | } |
3096 | ||
2949056c | 3097 | linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); |
6687c906 VS |
3098 | |
3099 | if (INTEL_INFO(dev)->gen < 4) | |
3100 | intel_crtc->dspaddr_offset = linear_offset; | |
3101 | ||
2db3366b PZ |
3102 | intel_crtc->adjusted_x = x; |
3103 | intel_crtc->adjusted_y = y; | |
3104 | ||
48404c1e SJ |
3105 | I915_WRITE(reg, dspcntr); |
3106 | ||
01f2c773 | 3107 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 3108 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d | 3109 | I915_WRITE(DSPSURF(plane), |
6687c906 VS |
3110 | intel_fb_gtt_offset(fb, rotation) + |
3111 | intel_crtc->dspaddr_offset); | |
5eddb70b | 3112 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 3113 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 3114 | } else |
058d88c4 | 3115 | I915_WRITE(DSPADDR(plane), i915_gem_object_ggtt_offset(obj, NULL) + linear_offset); |
5eddb70b | 3116 | POSTING_READ(reg); |
17638cd6 JB |
3117 | } |
3118 | ||
a8d201af ML |
3119 | static void i9xx_disable_primary_plane(struct drm_plane *primary, |
3120 | struct drm_crtc *crtc) | |
17638cd6 JB |
3121 | { |
3122 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3123 | struct drm_i915_private *dev_priv = to_i915(dev); |
17638cd6 | 3124 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
17638cd6 | 3125 | int plane = intel_crtc->plane; |
f45651ba | 3126 | |
a8d201af ML |
3127 | I915_WRITE(DSPCNTR(plane), 0); |
3128 | if (INTEL_INFO(dev_priv)->gen >= 4) | |
fdd508a6 | 3129 | I915_WRITE(DSPSURF(plane), 0); |
a8d201af ML |
3130 | else |
3131 | I915_WRITE(DSPADDR(plane), 0); | |
3132 | POSTING_READ(DSPCNTR(plane)); | |
3133 | } | |
c9ba6fad | 3134 | |
a8d201af ML |
3135 | static void ironlake_update_primary_plane(struct drm_plane *primary, |
3136 | const struct intel_crtc_state *crtc_state, | |
3137 | const struct intel_plane_state *plane_state) | |
3138 | { | |
3139 | struct drm_device *dev = primary->dev; | |
fac5e23e | 3140 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8d201af ML |
3141 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
3142 | struct drm_framebuffer *fb = plane_state->base.fb; | |
a8d201af | 3143 | int plane = intel_crtc->plane; |
54ea9da8 | 3144 | u32 linear_offset; |
a8d201af ML |
3145 | u32 dspcntr; |
3146 | i915_reg_t reg = DSPCNTR(plane); | |
8d0deca8 | 3147 | unsigned int rotation = plane_state->base.rotation; |
936e71e3 VS |
3148 | int x = plane_state->base.src.x1 >> 16; |
3149 | int y = plane_state->base.src.y1 >> 16; | |
c9ba6fad | 3150 | |
f45651ba | 3151 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
fdd508a6 | 3152 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba | 3153 | |
8652744b | 3154 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
f45651ba | 3155 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; |
17638cd6 | 3156 | |
57779d06 VS |
3157 | switch (fb->pixel_format) { |
3158 | case DRM_FORMAT_C8: | |
17638cd6 JB |
3159 | dspcntr |= DISPPLANE_8BPP; |
3160 | break; | |
57779d06 VS |
3161 | case DRM_FORMAT_RGB565: |
3162 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 3163 | break; |
57779d06 | 3164 | case DRM_FORMAT_XRGB8888: |
57779d06 VS |
3165 | dspcntr |= DISPPLANE_BGRX888; |
3166 | break; | |
3167 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
3168 | dspcntr |= DISPPLANE_RGBX888; |
3169 | break; | |
3170 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
3171 | dspcntr |= DISPPLANE_BGRX101010; |
3172 | break; | |
3173 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 3174 | dspcntr |= DISPPLANE_RGBX101010; |
17638cd6 JB |
3175 | break; |
3176 | default: | |
baba133a | 3177 | BUG(); |
17638cd6 JB |
3178 | } |
3179 | ||
72618ebf | 3180 | if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) |
17638cd6 | 3181 | dspcntr |= DISPPLANE_TILED; |
17638cd6 | 3182 | |
8652744b | 3183 | if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) |
1f5d76db | 3184 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 3185 | |
2949056c | 3186 | intel_add_fb_offsets(&x, &y, plane_state, 0); |
6687c906 | 3187 | |
c2c75131 | 3188 | intel_crtc->dspaddr_offset = |
2949056c | 3189 | intel_compute_tile_offset(&x, &y, plane_state, 0); |
6687c906 | 3190 | |
31ad61e4 | 3191 | if (rotation == DRM_ROTATE_180) { |
48404c1e SJ |
3192 | dspcntr |= DISPPLANE_ROTATE_180; |
3193 | ||
8652744b | 3194 | if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) { |
a8d201af ML |
3195 | x += (crtc_state->pipe_src_w - 1); |
3196 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
3197 | } |
3198 | } | |
3199 | ||
2949056c | 3200 | linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); |
6687c906 | 3201 | |
2db3366b PZ |
3202 | intel_crtc->adjusted_x = x; |
3203 | intel_crtc->adjusted_y = y; | |
3204 | ||
48404c1e | 3205 | I915_WRITE(reg, dspcntr); |
17638cd6 | 3206 | |
01f2c773 | 3207 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d | 3208 | I915_WRITE(DSPSURF(plane), |
6687c906 VS |
3209 | intel_fb_gtt_offset(fb, rotation) + |
3210 | intel_crtc->dspaddr_offset); | |
8652744b | 3211 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
bc1c91eb DL |
3212 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
3213 | } else { | |
3214 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
3215 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
3216 | } | |
17638cd6 | 3217 | POSTING_READ(reg); |
17638cd6 JB |
3218 | } |
3219 | ||
7b49f948 VS |
3220 | u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv, |
3221 | uint64_t fb_modifier, uint32_t pixel_format) | |
b321803d | 3222 | { |
7b49f948 | 3223 | if (fb_modifier == DRM_FORMAT_MOD_NONE) { |
b321803d | 3224 | return 64; |
7b49f948 VS |
3225 | } else { |
3226 | int cpp = drm_format_plane_cpp(pixel_format, 0); | |
3227 | ||
27ba3910 | 3228 | return intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
b321803d DL |
3229 | } |
3230 | } | |
3231 | ||
6687c906 VS |
3232 | u32 intel_fb_gtt_offset(struct drm_framebuffer *fb, |
3233 | unsigned int rotation) | |
121920fa | 3234 | { |
6687c906 | 3235 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
ce7f1728 | 3236 | struct i915_ggtt_view view; |
058d88c4 | 3237 | struct i915_vma *vma; |
121920fa | 3238 | |
6687c906 | 3239 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
dedf278c | 3240 | |
058d88c4 CW |
3241 | vma = i915_gem_object_to_ggtt(obj, &view); |
3242 | if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n", | |
3243 | view.type)) | |
3244 | return -1; | |
3245 | ||
bde13ebd | 3246 | return i915_ggtt_offset(vma); |
121920fa TU |
3247 | } |
3248 | ||
e435d6e5 ML |
3249 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
3250 | { | |
3251 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 3252 | struct drm_i915_private *dev_priv = to_i915(dev); |
e435d6e5 ML |
3253 | |
3254 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
3255 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
3256 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
3257 | } |
3258 | ||
a1b2278e CK |
3259 | /* |
3260 | * This function detaches (aka. unbinds) unused scalers in hardware | |
3261 | */ | |
0583236e | 3262 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 3263 | { |
a1b2278e CK |
3264 | struct intel_crtc_scaler_state *scaler_state; |
3265 | int i; | |
3266 | ||
a1b2278e CK |
3267 | scaler_state = &intel_crtc->config->scaler_state; |
3268 | ||
3269 | /* loop through and disable scalers that aren't in use */ | |
3270 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
3271 | if (!scaler_state->scalers[i].in_use) |
3272 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
3273 | } |
3274 | } | |
3275 | ||
d2196774 VS |
3276 | u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane, |
3277 | unsigned int rotation) | |
3278 | { | |
3279 | const struct drm_i915_private *dev_priv = to_i915(fb->dev); | |
3280 | u32 stride = intel_fb_pitch(fb, plane, rotation); | |
3281 | ||
3282 | /* | |
3283 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
3284 | * linear buffers or in number of tiles for tiled buffers. | |
3285 | */ | |
bd2ef25d | 3286 | if (drm_rotation_90_or_270(rotation)) { |
d2196774 VS |
3287 | int cpp = drm_format_plane_cpp(fb->pixel_format, plane); |
3288 | ||
3289 | stride /= intel_tile_height(dev_priv, fb->modifier[0], cpp); | |
3290 | } else { | |
3291 | stride /= intel_fb_stride_alignment(dev_priv, fb->modifier[0], | |
3292 | fb->pixel_format); | |
3293 | } | |
3294 | ||
3295 | return stride; | |
3296 | } | |
3297 | ||
6156a456 | 3298 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 3299 | { |
6156a456 | 3300 | switch (pixel_format) { |
d161cf7a | 3301 | case DRM_FORMAT_C8: |
c34ce3d1 | 3302 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 3303 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 3304 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 3305 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 3306 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 3307 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 3308 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
3309 | /* |
3310 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
3311 | * to be already pre-multiplied. We need to add a knob (or a different | |
3312 | * DRM_FORMAT) for user-space to configure that. | |
3313 | */ | |
f75fb42a | 3314 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 3315 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 3316 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 3317 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 3318 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 3319 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 3320 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 3321 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 3322 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 3323 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 3324 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 3325 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 3326 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 3327 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 3328 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 3329 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 3330 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 3331 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 3332 | default: |
4249eeef | 3333 | MISSING_CASE(pixel_format); |
70d21f0e | 3334 | } |
8cfcba41 | 3335 | |
c34ce3d1 | 3336 | return 0; |
6156a456 | 3337 | } |
70d21f0e | 3338 | |
6156a456 CK |
3339 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
3340 | { | |
6156a456 | 3341 | switch (fb_modifier) { |
30af77c4 | 3342 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 3343 | break; |
30af77c4 | 3344 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 3345 | return PLANE_CTL_TILED_X; |
b321803d | 3346 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 3347 | return PLANE_CTL_TILED_Y; |
b321803d | 3348 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 3349 | return PLANE_CTL_TILED_YF; |
70d21f0e | 3350 | default: |
6156a456 | 3351 | MISSING_CASE(fb_modifier); |
70d21f0e | 3352 | } |
8cfcba41 | 3353 | |
c34ce3d1 | 3354 | return 0; |
6156a456 | 3355 | } |
70d21f0e | 3356 | |
6156a456 CK |
3357 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
3358 | { | |
3b7a5119 | 3359 | switch (rotation) { |
31ad61e4 | 3360 | case DRM_ROTATE_0: |
6156a456 | 3361 | break; |
1e8df167 SJ |
3362 | /* |
3363 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
3364 | * while i915 HW rotation is clockwise, thats why this swapping. | |
3365 | */ | |
31ad61e4 | 3366 | case DRM_ROTATE_90: |
1e8df167 | 3367 | return PLANE_CTL_ROTATE_270; |
31ad61e4 | 3368 | case DRM_ROTATE_180: |
c34ce3d1 | 3369 | return PLANE_CTL_ROTATE_180; |
31ad61e4 | 3370 | case DRM_ROTATE_270: |
1e8df167 | 3371 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
3372 | default: |
3373 | MISSING_CASE(rotation); | |
3374 | } | |
3375 | ||
c34ce3d1 | 3376 | return 0; |
6156a456 CK |
3377 | } |
3378 | ||
a8d201af ML |
3379 | static void skylake_update_primary_plane(struct drm_plane *plane, |
3380 | const struct intel_crtc_state *crtc_state, | |
3381 | const struct intel_plane_state *plane_state) | |
6156a456 | 3382 | { |
a8d201af | 3383 | struct drm_device *dev = plane->dev; |
fac5e23e | 3384 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8d201af ML |
3385 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
3386 | struct drm_framebuffer *fb = plane_state->base.fb; | |
62e0fb88 | 3387 | const struct skl_wm_values *wm = &dev_priv->wm.skl_results; |
d8c0fafc | 3388 | const struct skl_plane_wm *p_wm = |
3389 | &crtc_state->wm.skl.optimal.planes[0]; | |
6156a456 | 3390 | int pipe = intel_crtc->pipe; |
d2196774 | 3391 | u32 plane_ctl; |
a8d201af | 3392 | unsigned int rotation = plane_state->base.rotation; |
d2196774 | 3393 | u32 stride = skl_plane_stride(fb, 0, rotation); |
b63a16f6 | 3394 | u32 surf_addr = plane_state->main.offset; |
a8d201af | 3395 | int scaler_id = plane_state->scaler_id; |
b63a16f6 VS |
3396 | int src_x = plane_state->main.x; |
3397 | int src_y = plane_state->main.y; | |
936e71e3 VS |
3398 | int src_w = drm_rect_width(&plane_state->base.src) >> 16; |
3399 | int src_h = drm_rect_height(&plane_state->base.src) >> 16; | |
3400 | int dst_x = plane_state->base.dst.x1; | |
3401 | int dst_y = plane_state->base.dst.y1; | |
3402 | int dst_w = drm_rect_width(&plane_state->base.dst); | |
3403 | int dst_h = drm_rect_height(&plane_state->base.dst); | |
70d21f0e | 3404 | |
6156a456 CK |
3405 | plane_ctl = PLANE_CTL_ENABLE | |
3406 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3407 | PLANE_CTL_PIPE_CSC_ENABLE; | |
3408 | ||
3409 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); | |
3410 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
3411 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
6156a456 CK |
3412 | plane_ctl |= skl_plane_ctl_rotation(rotation); |
3413 | ||
6687c906 VS |
3414 | /* Sizes are 0 based */ |
3415 | src_w--; | |
3416 | src_h--; | |
3417 | dst_w--; | |
3418 | dst_h--; | |
3419 | ||
4c0b8a8b PZ |
3420 | intel_crtc->dspaddr_offset = surf_addr; |
3421 | ||
6687c906 VS |
3422 | intel_crtc->adjusted_x = src_x; |
3423 | intel_crtc->adjusted_y = src_y; | |
2db3366b | 3424 | |
62e0fb88 | 3425 | if (wm->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) |
d8c0fafc | 3426 | skl_write_plane_wm(intel_crtc, p_wm, &wm->ddb, 0); |
62e0fb88 | 3427 | |
70d21f0e | 3428 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
6687c906 | 3429 | I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x); |
ef78ec94 | 3430 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); |
6687c906 | 3431 | I915_WRITE(PLANE_SIZE(pipe, 0), (src_h << 16) | src_w); |
6156a456 CK |
3432 | |
3433 | if (scaler_id >= 0) { | |
3434 | uint32_t ps_ctrl = 0; | |
3435 | ||
3436 | WARN_ON(!dst_w || !dst_h); | |
3437 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | | |
3438 | crtc_state->scaler_state.scalers[scaler_id].mode; | |
3439 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3440 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3441 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3442 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3443 | I915_WRITE(PLANE_POS(pipe, 0), 0); | |
3444 | } else { | |
3445 | I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); | |
3446 | } | |
3447 | ||
6687c906 VS |
3448 | I915_WRITE(PLANE_SURF(pipe, 0), |
3449 | intel_fb_gtt_offset(fb, rotation) + surf_addr); | |
70d21f0e DL |
3450 | |
3451 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3452 | } | |
3453 | ||
a8d201af ML |
3454 | static void skylake_disable_primary_plane(struct drm_plane *primary, |
3455 | struct drm_crtc *crtc) | |
17638cd6 JB |
3456 | { |
3457 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3458 | struct drm_i915_private *dev_priv = to_i915(dev); |
62e0fb88 | 3459 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
d8c0fafc | 3460 | struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state); |
3461 | const struct skl_plane_wm *p_wm = &cstate->wm.skl.optimal.planes[0]; | |
62e0fb88 L |
3462 | int pipe = intel_crtc->pipe; |
3463 | ||
ccebc23b L |
3464 | /* |
3465 | * We only populate skl_results on watermark updates, and if the | |
3466 | * plane's visiblity isn't actually changing neither is its watermarks. | |
3467 | */ | |
3468 | if (!crtc->primary->state->visible) | |
d8c0fafc | 3469 | skl_write_plane_wm(intel_crtc, p_wm, |
3470 | &dev_priv->wm.skl_results.ddb, 0); | |
17638cd6 | 3471 | |
a8d201af ML |
3472 | I915_WRITE(PLANE_CTL(pipe, 0), 0); |
3473 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
3474 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3475 | } | |
29b9bde6 | 3476 | |
a8d201af ML |
3477 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3478 | static int | |
3479 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3480 | int x, int y, enum mode_set_atomic state) | |
3481 | { | |
3482 | /* Support for kgdboc is disabled, this needs a major rework. */ | |
3483 | DRM_ERROR("legacy panic handler not supported any more.\n"); | |
3484 | ||
3485 | return -ENODEV; | |
81255565 JB |
3486 | } |
3487 | ||
5a21b665 DV |
3488 | static void intel_complete_page_flips(struct drm_i915_private *dev_priv) |
3489 | { | |
3490 | struct intel_crtc *crtc; | |
3491 | ||
91c8a326 | 3492 | for_each_intel_crtc(&dev_priv->drm, crtc) |
5a21b665 DV |
3493 | intel_finish_page_flip_cs(dev_priv, crtc->pipe); |
3494 | } | |
3495 | ||
7514747d VS |
3496 | static void intel_update_primary_planes(struct drm_device *dev) |
3497 | { | |
7514747d | 3498 | struct drm_crtc *crtc; |
96a02917 | 3499 | |
70e1e0ec | 3500 | for_each_crtc(dev, crtc) { |
11c22da6 | 3501 | struct intel_plane *plane = to_intel_plane(crtc->primary); |
73974893 ML |
3502 | struct intel_plane_state *plane_state = |
3503 | to_intel_plane_state(plane->base.state); | |
11c22da6 | 3504 | |
936e71e3 | 3505 | if (plane_state->base.visible) |
a8d201af ML |
3506 | plane->update_plane(&plane->base, |
3507 | to_intel_crtc_state(crtc->state), | |
3508 | plane_state); | |
73974893 ML |
3509 | } |
3510 | } | |
3511 | ||
3512 | static int | |
3513 | __intel_display_resume(struct drm_device *dev, | |
3514 | struct drm_atomic_state *state) | |
3515 | { | |
3516 | struct drm_crtc_state *crtc_state; | |
3517 | struct drm_crtc *crtc; | |
3518 | int i, ret; | |
11c22da6 | 3519 | |
73974893 ML |
3520 | intel_modeset_setup_hw_state(dev); |
3521 | i915_redisable_vga(dev); | |
3522 | ||
3523 | if (!state) | |
3524 | return 0; | |
3525 | ||
3526 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
3527 | /* | |
3528 | * Force recalculation even if we restore | |
3529 | * current state. With fast modeset this may not result | |
3530 | * in a modeset when the state is compatible. | |
3531 | */ | |
3532 | crtc_state->mode_changed = true; | |
96a02917 | 3533 | } |
73974893 ML |
3534 | |
3535 | /* ignore any reset values/BIOS leftovers in the WM registers */ | |
3536 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
3537 | ||
3538 | ret = drm_atomic_commit(state); | |
3539 | ||
3540 | WARN_ON(ret == -EDEADLK); | |
3541 | return ret; | |
96a02917 VS |
3542 | } |
3543 | ||
4ac2ba2f VS |
3544 | static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv) |
3545 | { | |
ae98104b VS |
3546 | return intel_has_gpu_reset(dev_priv) && |
3547 | INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv); | |
4ac2ba2f VS |
3548 | } |
3549 | ||
c033666a | 3550 | void intel_prepare_reset(struct drm_i915_private *dev_priv) |
7514747d | 3551 | { |
73974893 ML |
3552 | struct drm_device *dev = &dev_priv->drm; |
3553 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; | |
3554 | struct drm_atomic_state *state; | |
3555 | int ret; | |
3556 | ||
73974893 ML |
3557 | /* |
3558 | * Need mode_config.mutex so that we don't | |
3559 | * trample ongoing ->detect() and whatnot. | |
3560 | */ | |
3561 | mutex_lock(&dev->mode_config.mutex); | |
3562 | drm_modeset_acquire_init(ctx, 0); | |
3563 | while (1) { | |
3564 | ret = drm_modeset_lock_all_ctx(dev, ctx); | |
3565 | if (ret != -EDEADLK) | |
3566 | break; | |
3567 | ||
3568 | drm_modeset_backoff(ctx); | |
3569 | } | |
3570 | ||
3571 | /* reset doesn't touch the display, but flips might get nuked anyway, */ | |
522a63de | 3572 | if (!i915.force_reset_modeset_test && |
4ac2ba2f | 3573 | !gpu_reset_clobbers_display(dev_priv)) |
7514747d VS |
3574 | return; |
3575 | ||
f98ce92f VS |
3576 | /* |
3577 | * Disabling the crtcs gracefully seems nicer. Also the | |
3578 | * g33 docs say we should at least disable all the planes. | |
3579 | */ | |
73974893 ML |
3580 | state = drm_atomic_helper_duplicate_state(dev, ctx); |
3581 | if (IS_ERR(state)) { | |
3582 | ret = PTR_ERR(state); | |
3583 | state = NULL; | |
3584 | DRM_ERROR("Duplicating state failed with %i\n", ret); | |
3585 | goto err; | |
3586 | } | |
3587 | ||
3588 | ret = drm_atomic_helper_disable_all(dev, ctx); | |
3589 | if (ret) { | |
3590 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
3591 | goto err; | |
3592 | } | |
3593 | ||
3594 | dev_priv->modeset_restore_state = state; | |
3595 | state->acquire_ctx = ctx; | |
3596 | return; | |
3597 | ||
3598 | err: | |
0853695c | 3599 | drm_atomic_state_put(state); |
7514747d VS |
3600 | } |
3601 | ||
c033666a | 3602 | void intel_finish_reset(struct drm_i915_private *dev_priv) |
7514747d | 3603 | { |
73974893 ML |
3604 | struct drm_device *dev = &dev_priv->drm; |
3605 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; | |
3606 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
3607 | int ret; | |
3608 | ||
5a21b665 DV |
3609 | /* |
3610 | * Flips in the rings will be nuked by the reset, | |
3611 | * so complete all pending flips so that user space | |
3612 | * will get its events and not get stuck. | |
3613 | */ | |
3614 | intel_complete_page_flips(dev_priv); | |
3615 | ||
73974893 ML |
3616 | dev_priv->modeset_restore_state = NULL; |
3617 | ||
7514747d | 3618 | /* reset doesn't touch the display */ |
4ac2ba2f | 3619 | if (!gpu_reset_clobbers_display(dev_priv)) { |
522a63de ML |
3620 | if (!state) { |
3621 | /* | |
3622 | * Flips in the rings have been nuked by the reset, | |
3623 | * so update the base address of all primary | |
3624 | * planes to the the last fb to make sure we're | |
3625 | * showing the correct fb after a reset. | |
3626 | * | |
3627 | * FIXME: Atomic will make this obsolete since we won't schedule | |
3628 | * CS-based flips (which might get lost in gpu resets) any more. | |
3629 | */ | |
3630 | intel_update_primary_planes(dev); | |
3631 | } else { | |
3632 | ret = __intel_display_resume(dev, state); | |
3633 | if (ret) | |
3634 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
3635 | } | |
73974893 ML |
3636 | } else { |
3637 | /* | |
3638 | * The display has been reset as well, | |
3639 | * so need a full re-initialization. | |
3640 | */ | |
3641 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3642 | intel_runtime_pm_enable_interrupts(dev_priv); | |
7514747d | 3643 | |
51f59205 | 3644 | intel_pps_unlock_regs_wa(dev_priv); |
73974893 | 3645 | intel_modeset_init_hw(dev); |
7514747d | 3646 | |
73974893 ML |
3647 | spin_lock_irq(&dev_priv->irq_lock); |
3648 | if (dev_priv->display.hpd_irq_setup) | |
3649 | dev_priv->display.hpd_irq_setup(dev_priv); | |
3650 | spin_unlock_irq(&dev_priv->irq_lock); | |
7514747d | 3651 | |
73974893 ML |
3652 | ret = __intel_display_resume(dev, state); |
3653 | if (ret) | |
3654 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
7514747d | 3655 | |
73974893 ML |
3656 | intel_hpd_init(dev_priv); |
3657 | } | |
7514747d | 3658 | |
0853695c CW |
3659 | if (state) |
3660 | drm_atomic_state_put(state); | |
73974893 ML |
3661 | drm_modeset_drop_locks(ctx); |
3662 | drm_modeset_acquire_fini(ctx); | |
3663 | mutex_unlock(&dev->mode_config.mutex); | |
7514747d VS |
3664 | } |
3665 | ||
8af29b0c CW |
3666 | static bool abort_flip_on_reset(struct intel_crtc *crtc) |
3667 | { | |
3668 | struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error; | |
3669 | ||
3670 | if (i915_reset_in_progress(error)) | |
3671 | return true; | |
3672 | ||
3673 | if (crtc->reset_count != i915_reset_count(error)) | |
3674 | return true; | |
3675 | ||
3676 | return false; | |
3677 | } | |
3678 | ||
7d5e3799 CW |
3679 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3680 | { | |
5a21b665 DV |
3681 | struct drm_device *dev = crtc->dev; |
3682 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5a21b665 DV |
3683 | bool pending; |
3684 | ||
8af29b0c | 3685 | if (abort_flip_on_reset(intel_crtc)) |
5a21b665 DV |
3686 | return false; |
3687 | ||
3688 | spin_lock_irq(&dev->event_lock); | |
3689 | pending = to_intel_crtc(crtc)->flip_work != NULL; | |
3690 | spin_unlock_irq(&dev->event_lock); | |
3691 | ||
3692 | return pending; | |
7d5e3799 CW |
3693 | } |
3694 | ||
bfd16b2a ML |
3695 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
3696 | struct intel_crtc_state *old_crtc_state) | |
e30e8f75 GP |
3697 | { |
3698 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 3699 | struct drm_i915_private *dev_priv = to_i915(dev); |
bfd16b2a ML |
3700 | struct intel_crtc_state *pipe_config = |
3701 | to_intel_crtc_state(crtc->base.state); | |
e30e8f75 | 3702 | |
bfd16b2a ML |
3703 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
3704 | crtc->base.mode = crtc->base.state->mode; | |
3705 | ||
3706 | DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n", | |
3707 | old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h, | |
3708 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
e30e8f75 GP |
3709 | |
3710 | /* | |
3711 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3712 | * that in compute_mode_changes we check the native mode (not the pfit | |
3713 | * mode) to see if we can flip rather than do a full mode set. In the | |
3714 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3715 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3716 | * sized surface. | |
e30e8f75 GP |
3717 | */ |
3718 | ||
e30e8f75 | 3719 | I915_WRITE(PIPESRC(crtc->pipe), |
bfd16b2a ML |
3720 | ((pipe_config->pipe_src_w - 1) << 16) | |
3721 | (pipe_config->pipe_src_h - 1)); | |
3722 | ||
3723 | /* on skylake this is done by detaching scalers */ | |
3724 | if (INTEL_INFO(dev)->gen >= 9) { | |
3725 | skl_detach_scalers(crtc); | |
3726 | ||
3727 | if (pipe_config->pch_pfit.enabled) | |
3728 | skylake_pfit_enable(crtc); | |
6e266956 | 3729 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
bfd16b2a ML |
3730 | if (pipe_config->pch_pfit.enabled) |
3731 | ironlake_pfit_enable(crtc); | |
3732 | else if (old_crtc_state->pch_pfit.enabled) | |
3733 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3734 | } |
e30e8f75 GP |
3735 | } |
3736 | ||
5e84e1a4 ZW |
3737 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3738 | { | |
3739 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3740 | struct drm_i915_private *dev_priv = to_i915(dev); |
5e84e1a4 ZW |
3741 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3742 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3743 | i915_reg_t reg; |
3744 | u32 temp; | |
5e84e1a4 ZW |
3745 | |
3746 | /* enable normal train */ | |
3747 | reg = FDI_TX_CTL(pipe); | |
3748 | temp = I915_READ(reg); | |
fd6b8f43 | 3749 | if (IS_IVYBRIDGE(dev_priv)) { |
357555c0 JB |
3750 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3751 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3752 | } else { |
3753 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3754 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3755 | } |
5e84e1a4 ZW |
3756 | I915_WRITE(reg, temp); |
3757 | ||
3758 | reg = FDI_RX_CTL(pipe); | |
3759 | temp = I915_READ(reg); | |
6e266956 | 3760 | if (HAS_PCH_CPT(dev_priv)) { |
5e84e1a4 ZW |
3761 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3762 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3763 | } else { | |
3764 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3765 | temp |= FDI_LINK_TRAIN_NONE; | |
3766 | } | |
3767 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3768 | ||
3769 | /* wait one idle pattern time */ | |
3770 | POSTING_READ(reg); | |
3771 | udelay(1000); | |
357555c0 JB |
3772 | |
3773 | /* IVB wants error correction enabled */ | |
fd6b8f43 | 3774 | if (IS_IVYBRIDGE(dev_priv)) |
357555c0 JB |
3775 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | |
3776 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3777 | } |
3778 | ||
8db9d77b ZW |
3779 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3780 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3781 | { | |
3782 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3783 | struct drm_i915_private *dev_priv = to_i915(dev); |
8db9d77b ZW |
3784 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3785 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3786 | i915_reg_t reg; |
3787 | u32 temp, tries; | |
8db9d77b | 3788 | |
1c8562f6 | 3789 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3790 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3791 | |
e1a44743 AJ |
3792 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3793 | for train result */ | |
5eddb70b CW |
3794 | reg = FDI_RX_IMR(pipe); |
3795 | temp = I915_READ(reg); | |
e1a44743 AJ |
3796 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3797 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3798 | I915_WRITE(reg, temp); |
3799 | I915_READ(reg); | |
e1a44743 AJ |
3800 | udelay(150); |
3801 | ||
8db9d77b | 3802 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3803 | reg = FDI_TX_CTL(pipe); |
3804 | temp = I915_READ(reg); | |
627eb5a3 | 3805 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3806 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3807 | temp &= ~FDI_LINK_TRAIN_NONE; |
3808 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3809 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3810 | |
5eddb70b CW |
3811 | reg = FDI_RX_CTL(pipe); |
3812 | temp = I915_READ(reg); | |
8db9d77b ZW |
3813 | temp &= ~FDI_LINK_TRAIN_NONE; |
3814 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3815 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3816 | ||
3817 | POSTING_READ(reg); | |
8db9d77b ZW |
3818 | udelay(150); |
3819 | ||
5b2adf89 | 3820 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3821 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3822 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3823 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3824 | |
5eddb70b | 3825 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3826 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3827 | temp = I915_READ(reg); |
8db9d77b ZW |
3828 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3829 | ||
3830 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3831 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3832 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3833 | break; |
3834 | } | |
8db9d77b | 3835 | } |
e1a44743 | 3836 | if (tries == 5) |
5eddb70b | 3837 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3838 | |
3839 | /* Train 2 */ | |
5eddb70b CW |
3840 | reg = FDI_TX_CTL(pipe); |
3841 | temp = I915_READ(reg); | |
8db9d77b ZW |
3842 | temp &= ~FDI_LINK_TRAIN_NONE; |
3843 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3844 | I915_WRITE(reg, temp); |
8db9d77b | 3845 | |
5eddb70b CW |
3846 | reg = FDI_RX_CTL(pipe); |
3847 | temp = I915_READ(reg); | |
8db9d77b ZW |
3848 | temp &= ~FDI_LINK_TRAIN_NONE; |
3849 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3850 | I915_WRITE(reg, temp); |
8db9d77b | 3851 | |
5eddb70b CW |
3852 | POSTING_READ(reg); |
3853 | udelay(150); | |
8db9d77b | 3854 | |
5eddb70b | 3855 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3856 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3857 | temp = I915_READ(reg); |
8db9d77b ZW |
3858 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3859 | ||
3860 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3861 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3862 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3863 | break; | |
3864 | } | |
8db9d77b | 3865 | } |
e1a44743 | 3866 | if (tries == 5) |
5eddb70b | 3867 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3868 | |
3869 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3870 | |
8db9d77b ZW |
3871 | } |
3872 | ||
0206e353 | 3873 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3874 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3875 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3876 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3877 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3878 | }; | |
3879 | ||
3880 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3881 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3882 | { | |
3883 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3884 | struct drm_i915_private *dev_priv = to_i915(dev); |
8db9d77b ZW |
3885 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3886 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3887 | i915_reg_t reg; |
3888 | u32 temp, i, retry; | |
8db9d77b | 3889 | |
e1a44743 AJ |
3890 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3891 | for train result */ | |
5eddb70b CW |
3892 | reg = FDI_RX_IMR(pipe); |
3893 | temp = I915_READ(reg); | |
e1a44743 AJ |
3894 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3895 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3896 | I915_WRITE(reg, temp); |
3897 | ||
3898 | POSTING_READ(reg); | |
e1a44743 AJ |
3899 | udelay(150); |
3900 | ||
8db9d77b | 3901 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3902 | reg = FDI_TX_CTL(pipe); |
3903 | temp = I915_READ(reg); | |
627eb5a3 | 3904 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3905 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3906 | temp &= ~FDI_LINK_TRAIN_NONE; |
3907 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3908 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3909 | /* SNB-B */ | |
3910 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3911 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3912 | |
d74cf324 DV |
3913 | I915_WRITE(FDI_RX_MISC(pipe), |
3914 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3915 | ||
5eddb70b CW |
3916 | reg = FDI_RX_CTL(pipe); |
3917 | temp = I915_READ(reg); | |
6e266956 | 3918 | if (HAS_PCH_CPT(dev_priv)) { |
8db9d77b ZW |
3919 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3920 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3921 | } else { | |
3922 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3923 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3924 | } | |
5eddb70b CW |
3925 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3926 | ||
3927 | POSTING_READ(reg); | |
8db9d77b ZW |
3928 | udelay(150); |
3929 | ||
0206e353 | 3930 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3931 | reg = FDI_TX_CTL(pipe); |
3932 | temp = I915_READ(reg); | |
8db9d77b ZW |
3933 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3934 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3935 | I915_WRITE(reg, temp); |
3936 | ||
3937 | POSTING_READ(reg); | |
8db9d77b ZW |
3938 | udelay(500); |
3939 | ||
fa37d39e SP |
3940 | for (retry = 0; retry < 5; retry++) { |
3941 | reg = FDI_RX_IIR(pipe); | |
3942 | temp = I915_READ(reg); | |
3943 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3944 | if (temp & FDI_RX_BIT_LOCK) { | |
3945 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3946 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3947 | break; | |
3948 | } | |
3949 | udelay(50); | |
8db9d77b | 3950 | } |
fa37d39e SP |
3951 | if (retry < 5) |
3952 | break; | |
8db9d77b ZW |
3953 | } |
3954 | if (i == 4) | |
5eddb70b | 3955 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3956 | |
3957 | /* Train 2 */ | |
5eddb70b CW |
3958 | reg = FDI_TX_CTL(pipe); |
3959 | temp = I915_READ(reg); | |
8db9d77b ZW |
3960 | temp &= ~FDI_LINK_TRAIN_NONE; |
3961 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5db94019 | 3962 | if (IS_GEN6(dev_priv)) { |
8db9d77b ZW |
3963 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3964 | /* SNB-B */ | |
3965 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3966 | } | |
5eddb70b | 3967 | I915_WRITE(reg, temp); |
8db9d77b | 3968 | |
5eddb70b CW |
3969 | reg = FDI_RX_CTL(pipe); |
3970 | temp = I915_READ(reg); | |
6e266956 | 3971 | if (HAS_PCH_CPT(dev_priv)) { |
8db9d77b ZW |
3972 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3973 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3974 | } else { | |
3975 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3976 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3977 | } | |
5eddb70b CW |
3978 | I915_WRITE(reg, temp); |
3979 | ||
3980 | POSTING_READ(reg); | |
8db9d77b ZW |
3981 | udelay(150); |
3982 | ||
0206e353 | 3983 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3984 | reg = FDI_TX_CTL(pipe); |
3985 | temp = I915_READ(reg); | |
8db9d77b ZW |
3986 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3987 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3988 | I915_WRITE(reg, temp); |
3989 | ||
3990 | POSTING_READ(reg); | |
8db9d77b ZW |
3991 | udelay(500); |
3992 | ||
fa37d39e SP |
3993 | for (retry = 0; retry < 5; retry++) { |
3994 | reg = FDI_RX_IIR(pipe); | |
3995 | temp = I915_READ(reg); | |
3996 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3997 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3998 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3999 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
4000 | break; | |
4001 | } | |
4002 | udelay(50); | |
8db9d77b | 4003 | } |
fa37d39e SP |
4004 | if (retry < 5) |
4005 | break; | |
8db9d77b ZW |
4006 | } |
4007 | if (i == 4) | |
5eddb70b | 4008 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
4009 | |
4010 | DRM_DEBUG_KMS("FDI train done.\n"); | |
4011 | } | |
4012 | ||
357555c0 JB |
4013 | /* Manual link training for Ivy Bridge A0 parts */ |
4014 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
4015 | { | |
4016 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4017 | struct drm_i915_private *dev_priv = to_i915(dev); |
357555c0 JB |
4018 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4019 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
4020 | i915_reg_t reg; |
4021 | u32 temp, i, j; | |
357555c0 JB |
4022 | |
4023 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
4024 | for train result */ | |
4025 | reg = FDI_RX_IMR(pipe); | |
4026 | temp = I915_READ(reg); | |
4027 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
4028 | temp &= ~FDI_RX_BIT_LOCK; | |
4029 | I915_WRITE(reg, temp); | |
4030 | ||
4031 | POSTING_READ(reg); | |
4032 | udelay(150); | |
4033 | ||
01a415fd DV |
4034 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
4035 | I915_READ(FDI_RX_IIR(pipe))); | |
4036 | ||
139ccd3f JB |
4037 | /* Try each vswing and preemphasis setting twice before moving on */ |
4038 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
4039 | /* disable first in case we need to retry */ | |
4040 | reg = FDI_TX_CTL(pipe); | |
4041 | temp = I915_READ(reg); | |
4042 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
4043 | temp &= ~FDI_TX_ENABLE; | |
4044 | I915_WRITE(reg, temp); | |
357555c0 | 4045 | |
139ccd3f JB |
4046 | reg = FDI_RX_CTL(pipe); |
4047 | temp = I915_READ(reg); | |
4048 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
4049 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
4050 | temp &= ~FDI_RX_ENABLE; | |
4051 | I915_WRITE(reg, temp); | |
357555c0 | 4052 | |
139ccd3f | 4053 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
4054 | reg = FDI_TX_CTL(pipe); |
4055 | temp = I915_READ(reg); | |
139ccd3f | 4056 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 4057 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 4058 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 4059 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
4060 | temp |= snb_b_fdi_train_param[j/2]; |
4061 | temp |= FDI_COMPOSITE_SYNC; | |
4062 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 4063 | |
139ccd3f JB |
4064 | I915_WRITE(FDI_RX_MISC(pipe), |
4065 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 4066 | |
139ccd3f | 4067 | reg = FDI_RX_CTL(pipe); |
357555c0 | 4068 | temp = I915_READ(reg); |
139ccd3f JB |
4069 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
4070 | temp |= FDI_COMPOSITE_SYNC; | |
4071 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 4072 | |
139ccd3f JB |
4073 | POSTING_READ(reg); |
4074 | udelay(1); /* should be 0.5us */ | |
357555c0 | 4075 | |
139ccd3f JB |
4076 | for (i = 0; i < 4; i++) { |
4077 | reg = FDI_RX_IIR(pipe); | |
4078 | temp = I915_READ(reg); | |
4079 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 4080 | |
139ccd3f JB |
4081 | if (temp & FDI_RX_BIT_LOCK || |
4082 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
4083 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
4084 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
4085 | i); | |
4086 | break; | |
4087 | } | |
4088 | udelay(1); /* should be 0.5us */ | |
4089 | } | |
4090 | if (i == 4) { | |
4091 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
4092 | continue; | |
4093 | } | |
357555c0 | 4094 | |
139ccd3f | 4095 | /* Train 2 */ |
357555c0 JB |
4096 | reg = FDI_TX_CTL(pipe); |
4097 | temp = I915_READ(reg); | |
139ccd3f JB |
4098 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
4099 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
4100 | I915_WRITE(reg, temp); | |
4101 | ||
4102 | reg = FDI_RX_CTL(pipe); | |
4103 | temp = I915_READ(reg); | |
4104 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
4105 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
4106 | I915_WRITE(reg, temp); |
4107 | ||
4108 | POSTING_READ(reg); | |
139ccd3f | 4109 | udelay(2); /* should be 1.5us */ |
357555c0 | 4110 | |
139ccd3f JB |
4111 | for (i = 0; i < 4; i++) { |
4112 | reg = FDI_RX_IIR(pipe); | |
4113 | temp = I915_READ(reg); | |
4114 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 4115 | |
139ccd3f JB |
4116 | if (temp & FDI_RX_SYMBOL_LOCK || |
4117 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
4118 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
4119 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
4120 | i); | |
4121 | goto train_done; | |
4122 | } | |
4123 | udelay(2); /* should be 1.5us */ | |
357555c0 | 4124 | } |
139ccd3f JB |
4125 | if (i == 4) |
4126 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 4127 | } |
357555c0 | 4128 | |
139ccd3f | 4129 | train_done: |
357555c0 JB |
4130 | DRM_DEBUG_KMS("FDI train done.\n"); |
4131 | } | |
4132 | ||
88cefb6c | 4133 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 4134 | { |
88cefb6c | 4135 | struct drm_device *dev = intel_crtc->base.dev; |
fac5e23e | 4136 | struct drm_i915_private *dev_priv = to_i915(dev); |
2c07245f | 4137 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
4138 | i915_reg_t reg; |
4139 | u32 temp; | |
c64e311e | 4140 | |
c98e9dcf | 4141 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
4142 | reg = FDI_RX_CTL(pipe); |
4143 | temp = I915_READ(reg); | |
627eb5a3 | 4144 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 4145 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 4146 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
4147 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
4148 | ||
4149 | POSTING_READ(reg); | |
c98e9dcf JB |
4150 | udelay(200); |
4151 | ||
4152 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
4153 | temp = I915_READ(reg); |
4154 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
4155 | ||
4156 | POSTING_READ(reg); | |
c98e9dcf JB |
4157 | udelay(200); |
4158 | ||
20749730 PZ |
4159 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
4160 | reg = FDI_TX_CTL(pipe); | |
4161 | temp = I915_READ(reg); | |
4162 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
4163 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 4164 | |
20749730 PZ |
4165 | POSTING_READ(reg); |
4166 | udelay(100); | |
6be4a607 | 4167 | } |
0e23b99d JB |
4168 | } |
4169 | ||
88cefb6c DV |
4170 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
4171 | { | |
4172 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 4173 | struct drm_i915_private *dev_priv = to_i915(dev); |
88cefb6c | 4174 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
4175 | i915_reg_t reg; |
4176 | u32 temp; | |
88cefb6c DV |
4177 | |
4178 | /* Switch from PCDclk to Rawclk */ | |
4179 | reg = FDI_RX_CTL(pipe); | |
4180 | temp = I915_READ(reg); | |
4181 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
4182 | ||
4183 | /* Disable CPU FDI TX PLL */ | |
4184 | reg = FDI_TX_CTL(pipe); | |
4185 | temp = I915_READ(reg); | |
4186 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
4187 | ||
4188 | POSTING_READ(reg); | |
4189 | udelay(100); | |
4190 | ||
4191 | reg = FDI_RX_CTL(pipe); | |
4192 | temp = I915_READ(reg); | |
4193 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
4194 | ||
4195 | /* Wait for the clocks to turn off. */ | |
4196 | POSTING_READ(reg); | |
4197 | udelay(100); | |
4198 | } | |
4199 | ||
0fc932b8 JB |
4200 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
4201 | { | |
4202 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4203 | struct drm_i915_private *dev_priv = to_i915(dev); |
0fc932b8 JB |
4204 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4205 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
4206 | i915_reg_t reg; |
4207 | u32 temp; | |
0fc932b8 JB |
4208 | |
4209 | /* disable CPU FDI tx and PCH FDI rx */ | |
4210 | reg = FDI_TX_CTL(pipe); | |
4211 | temp = I915_READ(reg); | |
4212 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
4213 | POSTING_READ(reg); | |
4214 | ||
4215 | reg = FDI_RX_CTL(pipe); | |
4216 | temp = I915_READ(reg); | |
4217 | temp &= ~(0x7 << 16); | |
dfd07d72 | 4218 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
4219 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
4220 | ||
4221 | POSTING_READ(reg); | |
4222 | udelay(100); | |
4223 | ||
4224 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
6e266956 | 4225 | if (HAS_PCH_IBX(dev_priv)) |
6f06ce18 | 4226 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
4227 | |
4228 | /* still set train pattern 1 */ | |
4229 | reg = FDI_TX_CTL(pipe); | |
4230 | temp = I915_READ(reg); | |
4231 | temp &= ~FDI_LINK_TRAIN_NONE; | |
4232 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
4233 | I915_WRITE(reg, temp); | |
4234 | ||
4235 | reg = FDI_RX_CTL(pipe); | |
4236 | temp = I915_READ(reg); | |
6e266956 | 4237 | if (HAS_PCH_CPT(dev_priv)) { |
0fc932b8 JB |
4238 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
4239 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
4240 | } else { | |
4241 | temp &= ~FDI_LINK_TRAIN_NONE; | |
4242 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
4243 | } | |
4244 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
4245 | temp &= ~(0x07 << 16); | |
dfd07d72 | 4246 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
4247 | I915_WRITE(reg, temp); |
4248 | ||
4249 | POSTING_READ(reg); | |
4250 | udelay(100); | |
4251 | } | |
4252 | ||
5dce5b93 CW |
4253 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
4254 | { | |
4255 | struct intel_crtc *crtc; | |
4256 | ||
4257 | /* Note that we don't need to be called with mode_config.lock here | |
4258 | * as our list of CRTC objects is static for the lifetime of the | |
4259 | * device and so cannot disappear as we iterate. Similarly, we can | |
4260 | * happily treat the predicates as racy, atomic checks as userspace | |
4261 | * cannot claim and pin a new fb without at least acquring the | |
4262 | * struct_mutex and so serialising with us. | |
4263 | */ | |
d3fcc808 | 4264 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
4265 | if (atomic_read(&crtc->unpin_work_count) == 0) |
4266 | continue; | |
4267 | ||
5a21b665 | 4268 | if (crtc->flip_work) |
5dce5b93 CW |
4269 | intel_wait_for_vblank(dev, crtc->pipe); |
4270 | ||
4271 | return true; | |
4272 | } | |
4273 | ||
4274 | return false; | |
4275 | } | |
4276 | ||
5a21b665 | 4277 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
d6bbafa1 CW |
4278 | { |
4279 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
5a21b665 DV |
4280 | struct intel_flip_work *work = intel_crtc->flip_work; |
4281 | ||
4282 | intel_crtc->flip_work = NULL; | |
d6bbafa1 CW |
4283 | |
4284 | if (work->event) | |
560ce1dc | 4285 | drm_crtc_send_vblank_event(&intel_crtc->base, work->event); |
d6bbafa1 CW |
4286 | |
4287 | drm_crtc_vblank_put(&intel_crtc->base); | |
4288 | ||
5a21b665 | 4289 | wake_up_all(&dev_priv->pending_flip_queue); |
143f73b3 | 4290 | queue_work(dev_priv->wq, &work->unpin_work); |
5a21b665 DV |
4291 | |
4292 | trace_i915_flip_complete(intel_crtc->plane, | |
4293 | work->pending_flip_obj); | |
d6bbafa1 CW |
4294 | } |
4295 | ||
5008e874 | 4296 | static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 4297 | { |
0f91128d | 4298 | struct drm_device *dev = crtc->dev; |
fac5e23e | 4299 | struct drm_i915_private *dev_priv = to_i915(dev); |
5008e874 | 4300 | long ret; |
e6c3a2a6 | 4301 | |
2c10d571 | 4302 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
5008e874 ML |
4303 | |
4304 | ret = wait_event_interruptible_timeout( | |
4305 | dev_priv->pending_flip_queue, | |
4306 | !intel_crtc_has_pending_flip(crtc), | |
4307 | 60*HZ); | |
4308 | ||
4309 | if (ret < 0) | |
4310 | return ret; | |
4311 | ||
5a21b665 DV |
4312 | if (ret == 0) { |
4313 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4314 | struct intel_flip_work *work; | |
4315 | ||
4316 | spin_lock_irq(&dev->event_lock); | |
4317 | work = intel_crtc->flip_work; | |
4318 | if (work && !is_mmio_work(work)) { | |
4319 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
4320 | page_flip_completed(intel_crtc); | |
4321 | } | |
4322 | spin_unlock_irq(&dev->event_lock); | |
4323 | } | |
5bb61643 | 4324 | |
5008e874 | 4325 | return 0; |
e6c3a2a6 CW |
4326 | } |
4327 | ||
b7076546 | 4328 | void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
060f02d8 VS |
4329 | { |
4330 | u32 temp; | |
4331 | ||
4332 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
4333 | ||
4334 | mutex_lock(&dev_priv->sb_lock); | |
4335 | ||
4336 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
4337 | temp |= SBI_SSCCTL_DISABLE; | |
4338 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
4339 | ||
4340 | mutex_unlock(&dev_priv->sb_lock); | |
4341 | } | |
4342 | ||
e615efe4 ED |
4343 | /* Program iCLKIP clock to the desired frequency */ |
4344 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
4345 | { | |
64b46a06 | 4346 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
6e3c9717 | 4347 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
4348 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
4349 | u32 temp; | |
4350 | ||
060f02d8 | 4351 | lpt_disable_iclkip(dev_priv); |
e615efe4 | 4352 | |
64b46a06 VS |
4353 | /* The iCLK virtual clock root frequency is in MHz, |
4354 | * but the adjusted_mode->crtc_clock in in KHz. To get the | |
4355 | * divisors, it is necessary to divide one by another, so we | |
4356 | * convert the virtual clock precision to KHz here for higher | |
4357 | * precision. | |
4358 | */ | |
4359 | for (auxdiv = 0; auxdiv < 2; auxdiv++) { | |
e615efe4 ED |
4360 | u32 iclk_virtual_root_freq = 172800 * 1000; |
4361 | u32 iclk_pi_range = 64; | |
64b46a06 | 4362 | u32 desired_divisor; |
e615efe4 | 4363 | |
64b46a06 VS |
4364 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, |
4365 | clock << auxdiv); | |
4366 | divsel = (desired_divisor / iclk_pi_range) - 2; | |
4367 | phaseinc = desired_divisor % iclk_pi_range; | |
e615efe4 | 4368 | |
64b46a06 VS |
4369 | /* |
4370 | * Near 20MHz is a corner case which is | |
4371 | * out of range for the 7-bit divisor | |
4372 | */ | |
4373 | if (divsel <= 0x7f) | |
4374 | break; | |
e615efe4 ED |
4375 | } |
4376 | ||
4377 | /* This should not happen with any sane values */ | |
4378 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
4379 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
4380 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
4381 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
4382 | ||
4383 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 4384 | clock, |
e615efe4 ED |
4385 | auxdiv, |
4386 | divsel, | |
4387 | phasedir, | |
4388 | phaseinc); | |
4389 | ||
060f02d8 VS |
4390 | mutex_lock(&dev_priv->sb_lock); |
4391 | ||
e615efe4 | 4392 | /* Program SSCDIVINTPHASE6 */ |
988d6ee8 | 4393 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
4394 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
4395 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
4396 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
4397 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
4398 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
4399 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 4400 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
4401 | |
4402 | /* Program SSCAUXDIV */ | |
988d6ee8 | 4403 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
4404 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
4405 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 4406 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
4407 | |
4408 | /* Enable modulator and associated divider */ | |
988d6ee8 | 4409 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 4410 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 4411 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 | 4412 | |
060f02d8 VS |
4413 | mutex_unlock(&dev_priv->sb_lock); |
4414 | ||
e615efe4 ED |
4415 | /* Wait for initialization time */ |
4416 | udelay(24); | |
4417 | ||
4418 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
4419 | } | |
4420 | ||
8802e5b6 VS |
4421 | int lpt_get_iclkip(struct drm_i915_private *dev_priv) |
4422 | { | |
4423 | u32 divsel, phaseinc, auxdiv; | |
4424 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
4425 | u32 iclk_pi_range = 64; | |
4426 | u32 desired_divisor; | |
4427 | u32 temp; | |
4428 | ||
4429 | if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) | |
4430 | return 0; | |
4431 | ||
4432 | mutex_lock(&dev_priv->sb_lock); | |
4433 | ||
4434 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
4435 | if (temp & SBI_SSCCTL_DISABLE) { | |
4436 | mutex_unlock(&dev_priv->sb_lock); | |
4437 | return 0; | |
4438 | } | |
4439 | ||
4440 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); | |
4441 | divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >> | |
4442 | SBI_SSCDIVINTPHASE_DIVSEL_SHIFT; | |
4443 | phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >> | |
4444 | SBI_SSCDIVINTPHASE_INCVAL_SHIFT; | |
4445 | ||
4446 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); | |
4447 | auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >> | |
4448 | SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT; | |
4449 | ||
4450 | mutex_unlock(&dev_priv->sb_lock); | |
4451 | ||
4452 | desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc; | |
4453 | ||
4454 | return DIV_ROUND_CLOSEST(iclk_virtual_root_freq, | |
4455 | desired_divisor << auxdiv); | |
4456 | } | |
4457 | ||
275f01b2 DV |
4458 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4459 | enum pipe pch_transcoder) | |
4460 | { | |
4461 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4462 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 4463 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4464 | |
4465 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4466 | I915_READ(HTOTAL(cpu_transcoder))); | |
4467 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4468 | I915_READ(HBLANK(cpu_transcoder))); | |
4469 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4470 | I915_READ(HSYNC(cpu_transcoder))); | |
4471 | ||
4472 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4473 | I915_READ(VTOTAL(cpu_transcoder))); | |
4474 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4475 | I915_READ(VBLANK(cpu_transcoder))); | |
4476 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4477 | I915_READ(VSYNC(cpu_transcoder))); | |
4478 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4479 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4480 | } | |
4481 | ||
003632d9 | 4482 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 | 4483 | { |
fac5e23e | 4484 | struct drm_i915_private *dev_priv = to_i915(dev); |
1fbc0d78 DV |
4485 | uint32_t temp; |
4486 | ||
4487 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4488 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4489 | return; |
4490 | ||
4491 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4492 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4493 | ||
003632d9 ACO |
4494 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4495 | if (enable) | |
4496 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4497 | ||
4498 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4499 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4500 | POSTING_READ(SOUTH_CHICKEN1); | |
4501 | } | |
4502 | ||
4503 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4504 | { | |
4505 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4506 | |
4507 | switch (intel_crtc->pipe) { | |
4508 | case PIPE_A: | |
4509 | break; | |
4510 | case PIPE_B: | |
6e3c9717 | 4511 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4512 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4513 | else |
003632d9 | 4514 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4515 | |
4516 | break; | |
4517 | case PIPE_C: | |
003632d9 | 4518 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4519 | |
4520 | break; | |
4521 | default: | |
4522 | BUG(); | |
4523 | } | |
4524 | } | |
4525 | ||
c48b5305 VS |
4526 | /* Return which DP Port should be selected for Transcoder DP control */ |
4527 | static enum port | |
4528 | intel_trans_dp_port_sel(struct drm_crtc *crtc) | |
4529 | { | |
4530 | struct drm_device *dev = crtc->dev; | |
4531 | struct intel_encoder *encoder; | |
4532 | ||
4533 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
cca0502b | 4534 | if (encoder->type == INTEL_OUTPUT_DP || |
c48b5305 VS |
4535 | encoder->type == INTEL_OUTPUT_EDP) |
4536 | return enc_to_dig_port(&encoder->base)->port; | |
4537 | } | |
4538 | ||
4539 | return -1; | |
4540 | } | |
4541 | ||
f67a559d JB |
4542 | /* |
4543 | * Enable PCH resources required for PCH ports: | |
4544 | * - PCH PLLs | |
4545 | * - FDI training & RX/TX | |
4546 | * - update transcoder timings | |
4547 | * - DP transcoding bits | |
4548 | * - transcoder | |
4549 | */ | |
4550 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4551 | { |
4552 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4553 | struct drm_i915_private *dev_priv = to_i915(dev); |
0e23b99d JB |
4554 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4555 | int pipe = intel_crtc->pipe; | |
f0f59a00 | 4556 | u32 temp; |
2c07245f | 4557 | |
ab9412ba | 4558 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4559 | |
fd6b8f43 | 4560 | if (IS_IVYBRIDGE(dev_priv)) |
1fbc0d78 DV |
4561 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); |
4562 | ||
cd986abb DV |
4563 | /* Write the TU size bits before fdi link training, so that error |
4564 | * detection works. */ | |
4565 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4566 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4567 | ||
c98e9dcf | 4568 | /* For PCH output, training FDI link */ |
674cf967 | 4569 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4570 | |
3ad8a208 DV |
4571 | /* We need to program the right clock selection before writing the pixel |
4572 | * mutliplier into the DPLL. */ | |
6e266956 | 4573 | if (HAS_PCH_CPT(dev_priv)) { |
ee7b9f93 | 4574 | u32 sel; |
4b645f14 | 4575 | |
c98e9dcf | 4576 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4577 | temp |= TRANS_DPLL_ENABLE(pipe); |
4578 | sel = TRANS_DPLLB_SEL(pipe); | |
8106ddbd ACO |
4579 | if (intel_crtc->config->shared_dpll == |
4580 | intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B)) | |
ee7b9f93 JB |
4581 | temp |= sel; |
4582 | else | |
4583 | temp &= ~sel; | |
c98e9dcf | 4584 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4585 | } |
5eddb70b | 4586 | |
3ad8a208 DV |
4587 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4588 | * transcoder, and we actually should do this to not upset any PCH | |
4589 | * transcoder that already use the clock when we share it. | |
4590 | * | |
4591 | * Note that enable_shared_dpll tries to do the right thing, but | |
4592 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4593 | * the right LVDS enable sequence. */ | |
85b3894f | 4594 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4595 | |
d9b6cb56 JB |
4596 | /* set transcoder timing, panel must allow it */ |
4597 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4598 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4599 | |
303b81e0 | 4600 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4601 | |
c98e9dcf | 4602 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e266956 TU |
4603 | if (HAS_PCH_CPT(dev_priv) && |
4604 | intel_crtc_has_dp_encoder(intel_crtc->config)) { | |
9c4edaee VS |
4605 | const struct drm_display_mode *adjusted_mode = |
4606 | &intel_crtc->config->base.adjusted_mode; | |
dfd07d72 | 4607 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
f0f59a00 | 4608 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
5eddb70b CW |
4609 | temp = I915_READ(reg); |
4610 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4611 | TRANS_DP_SYNC_MASK | |
4612 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4613 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4614 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf | 4615 | |
9c4edaee | 4616 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
5eddb70b | 4617 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
9c4edaee | 4618 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4619 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4620 | |
4621 | switch (intel_trans_dp_port_sel(crtc)) { | |
c48b5305 | 4622 | case PORT_B: |
5eddb70b | 4623 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 4624 | break; |
c48b5305 | 4625 | case PORT_C: |
5eddb70b | 4626 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf | 4627 | break; |
c48b5305 | 4628 | case PORT_D: |
5eddb70b | 4629 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4630 | break; |
4631 | default: | |
e95d41e1 | 4632 | BUG(); |
32f9d658 | 4633 | } |
2c07245f | 4634 | |
5eddb70b | 4635 | I915_WRITE(reg, temp); |
6be4a607 | 4636 | } |
b52eb4dc | 4637 | |
b8a4f404 | 4638 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4639 | } |
4640 | ||
1507e5bd PZ |
4641 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4642 | { | |
4643 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4644 | struct drm_i915_private *dev_priv = to_i915(dev); |
1507e5bd | 4645 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 4646 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4647 | |
ab9412ba | 4648 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4649 | |
8c52b5e8 | 4650 | lpt_program_iclkip(crtc); |
1507e5bd | 4651 | |
0540e488 | 4652 | /* Set transcoder timing. */ |
275f01b2 | 4653 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4654 | |
937bb610 | 4655 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4656 | } |
4657 | ||
a1520318 | 4658 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 | 4659 | { |
fac5e23e | 4660 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 4661 | i915_reg_t dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4662 | u32 temp; |
4663 | ||
4664 | temp = I915_READ(dslreg); | |
4665 | udelay(500); | |
4666 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4667 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4668 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4669 | } |
4670 | } | |
4671 | ||
86adf9d7 ML |
4672 | static int |
4673 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
4674 | unsigned scaler_user, int *scaler_id, unsigned int rotation, | |
4675 | int src_w, int src_h, int dst_w, int dst_h) | |
a1b2278e | 4676 | { |
86adf9d7 ML |
4677 | struct intel_crtc_scaler_state *scaler_state = |
4678 | &crtc_state->scaler_state; | |
4679 | struct intel_crtc *intel_crtc = | |
4680 | to_intel_crtc(crtc_state->base.crtc); | |
a1b2278e | 4681 | int need_scaling; |
6156a456 | 4682 | |
bd2ef25d | 4683 | need_scaling = drm_rotation_90_or_270(rotation) ? |
6156a456 CK |
4684 | (src_h != dst_w || src_w != dst_h): |
4685 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4686 | |
4687 | /* | |
4688 | * if plane is being disabled or scaler is no more required or force detach | |
4689 | * - free scaler binded to this plane/crtc | |
4690 | * - in order to do this, update crtc->scaler_usage | |
4691 | * | |
4692 | * Here scaler state in crtc_state is set free so that | |
4693 | * scaler can be assigned to other user. Actual register | |
4694 | * update to free the scaler is done in plane/panel-fit programming. | |
4695 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4696 | */ | |
86adf9d7 | 4697 | if (force_detach || !need_scaling) { |
a1b2278e | 4698 | if (*scaler_id >= 0) { |
86adf9d7 | 4699 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4700 | scaler_state->scalers[*scaler_id].in_use = 0; |
4701 | ||
86adf9d7 ML |
4702 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4703 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4704 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4705 | scaler_state->scaler_users); |
4706 | *scaler_id = -1; | |
4707 | } | |
4708 | return 0; | |
4709 | } | |
4710 | ||
4711 | /* range checks */ | |
4712 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4713 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4714 | ||
4715 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4716 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4717 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4718 | "size is out of scaler range\n", |
86adf9d7 | 4719 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4720 | return -EINVAL; |
4721 | } | |
4722 | ||
86adf9d7 ML |
4723 | /* mark this plane as a scaler user in crtc_state */ |
4724 | scaler_state->scaler_users |= (1 << scaler_user); | |
4725 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4726 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4727 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4728 | scaler_state->scaler_users); | |
4729 | ||
4730 | return 0; | |
4731 | } | |
4732 | ||
4733 | /** | |
4734 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4735 | * | |
4736 | * @state: crtc's scaler state | |
86adf9d7 ML |
4737 | * |
4738 | * Return | |
4739 | * 0 - scaler_usage updated successfully | |
4740 | * error - requested scaling cannot be supported or other error condition | |
4741 | */ | |
e435d6e5 | 4742 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 ML |
4743 | { |
4744 | struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); | |
7c5f93b0 | 4745 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
86adf9d7 | 4746 | |
78108b7c VS |
4747 | DRM_DEBUG_KMS("Updating scaler for [CRTC:%d:%s] scaler_user index %u.%u\n", |
4748 | intel_crtc->base.base.id, intel_crtc->base.name, | |
4749 | intel_crtc->pipe, SKL_CRTC_INDEX); | |
86adf9d7 | 4750 | |
e435d6e5 | 4751 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
31ad61e4 | 4752 | &state->scaler_state.scaler_id, DRM_ROTATE_0, |
86adf9d7 | 4753 | state->pipe_src_w, state->pipe_src_h, |
aad941d5 | 4754 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
86adf9d7 ML |
4755 | } |
4756 | ||
4757 | /** | |
4758 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4759 | * | |
4760 | * @state: crtc's scaler state | |
86adf9d7 ML |
4761 | * @plane_state: atomic plane state to update |
4762 | * | |
4763 | * Return | |
4764 | * 0 - scaler_usage updated successfully | |
4765 | * error - requested scaling cannot be supported or other error condition | |
4766 | */ | |
da20eabd ML |
4767 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4768 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4769 | { |
4770 | ||
4771 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
da20eabd ML |
4772 | struct intel_plane *intel_plane = |
4773 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4774 | struct drm_framebuffer *fb = plane_state->base.fb; |
4775 | int ret; | |
4776 | ||
936e71e3 | 4777 | bool force_detach = !fb || !plane_state->base.visible; |
86adf9d7 | 4778 | |
72660ce0 VS |
4779 | DRM_DEBUG_KMS("Updating scaler for [PLANE:%d:%s] scaler_user index %u.%u\n", |
4780 | intel_plane->base.base.id, intel_plane->base.name, | |
4781 | intel_crtc->pipe, drm_plane_index(&intel_plane->base)); | |
86adf9d7 ML |
4782 | |
4783 | ret = skl_update_scaler(crtc_state, force_detach, | |
4784 | drm_plane_index(&intel_plane->base), | |
4785 | &plane_state->scaler_id, | |
4786 | plane_state->base.rotation, | |
936e71e3 VS |
4787 | drm_rect_width(&plane_state->base.src) >> 16, |
4788 | drm_rect_height(&plane_state->base.src) >> 16, | |
4789 | drm_rect_width(&plane_state->base.dst), | |
4790 | drm_rect_height(&plane_state->base.dst)); | |
86adf9d7 ML |
4791 | |
4792 | if (ret || plane_state->scaler_id < 0) | |
4793 | return ret; | |
4794 | ||
a1b2278e | 4795 | /* check colorkey */ |
818ed961 | 4796 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
72660ce0 VS |
4797 | DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed", |
4798 | intel_plane->base.base.id, | |
4799 | intel_plane->base.name); | |
a1b2278e CK |
4800 | return -EINVAL; |
4801 | } | |
4802 | ||
4803 | /* Check src format */ | |
86adf9d7 ML |
4804 | switch (fb->pixel_format) { |
4805 | case DRM_FORMAT_RGB565: | |
4806 | case DRM_FORMAT_XBGR8888: | |
4807 | case DRM_FORMAT_XRGB8888: | |
4808 | case DRM_FORMAT_ABGR8888: | |
4809 | case DRM_FORMAT_ARGB8888: | |
4810 | case DRM_FORMAT_XRGB2101010: | |
4811 | case DRM_FORMAT_XBGR2101010: | |
4812 | case DRM_FORMAT_YUYV: | |
4813 | case DRM_FORMAT_YVYU: | |
4814 | case DRM_FORMAT_UYVY: | |
4815 | case DRM_FORMAT_VYUY: | |
4816 | break; | |
4817 | default: | |
72660ce0 VS |
4818 | DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n", |
4819 | intel_plane->base.base.id, intel_plane->base.name, | |
4820 | fb->base.id, fb->pixel_format); | |
86adf9d7 | 4821 | return -EINVAL; |
a1b2278e CK |
4822 | } |
4823 | ||
a1b2278e CK |
4824 | return 0; |
4825 | } | |
4826 | ||
e435d6e5 ML |
4827 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4828 | { | |
4829 | int i; | |
4830 | ||
4831 | for (i = 0; i < crtc->num_scalers; i++) | |
4832 | skl_detach_scaler(crtc, i); | |
4833 | } | |
4834 | ||
4835 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4836 | { |
4837 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4838 | struct drm_i915_private *dev_priv = to_i915(dev); |
bd2e244f | 4839 | int pipe = crtc->pipe; |
a1b2278e CK |
4840 | struct intel_crtc_scaler_state *scaler_state = |
4841 | &crtc->config->scaler_state; | |
4842 | ||
4843 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4844 | ||
6e3c9717 | 4845 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4846 | int id; |
4847 | ||
4848 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4849 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4850 | return; | |
4851 | } | |
4852 | ||
4853 | id = scaler_state->scaler_id; | |
4854 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4855 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4856 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4857 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4858 | ||
4859 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4860 | } |
4861 | } | |
4862 | ||
b074cec8 JB |
4863 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4864 | { | |
4865 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4866 | struct drm_i915_private *dev_priv = to_i915(dev); |
b074cec8 JB |
4867 | int pipe = crtc->pipe; |
4868 | ||
6e3c9717 | 4869 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4870 | /* Force use of hard-coded filter coefficients |
4871 | * as some pre-programmed values are broken, | |
4872 | * e.g. x201. | |
4873 | */ | |
fd6b8f43 | 4874 | if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) |
b074cec8 JB |
4875 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | |
4876 | PF_PIPE_SEL_IVB(pipe)); | |
4877 | else | |
4878 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4879 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4880 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4881 | } |
4882 | } | |
4883 | ||
20bc8673 | 4884 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4885 | { |
cea165c3 | 4886 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4887 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 4888 | |
6e3c9717 | 4889 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4890 | return; |
4891 | ||
307e4498 ML |
4892 | /* |
4893 | * We can only enable IPS after we enable a plane and wait for a vblank | |
4894 | * This function is called from post_plane_update, which is run after | |
4895 | * a vblank wait. | |
4896 | */ | |
cea165c3 | 4897 | |
d77e4531 | 4898 | assert_plane_enabled(dev_priv, crtc->plane); |
8652744b | 4899 | if (IS_BROADWELL(dev_priv)) { |
2a114cc1 BW |
4900 | mutex_lock(&dev_priv->rps.hw_lock); |
4901 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4902 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4903 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4904 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4905 | * mailbox." Moreover, the mailbox may return a bogus state, |
4906 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4907 | */ |
4908 | } else { | |
4909 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4910 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4911 | * is essentially intel_wait_for_vblank. If we don't have this | |
4912 | * and don't wait for vblanks until the end of crtc_enable, then | |
4913 | * the HW state readout code will complain that the expected | |
4914 | * IPS_CTL value is not the one we read. */ | |
2ec9ba3c CW |
4915 | if (intel_wait_for_register(dev_priv, |
4916 | IPS_CTL, IPS_ENABLE, IPS_ENABLE, | |
4917 | 50)) | |
2a114cc1 BW |
4918 | DRM_ERROR("Timed out waiting for IPS enable\n"); |
4919 | } | |
d77e4531 PZ |
4920 | } |
4921 | ||
20bc8673 | 4922 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4923 | { |
4924 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4925 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 4926 | |
6e3c9717 | 4927 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4928 | return; |
4929 | ||
4930 | assert_plane_enabled(dev_priv, crtc->plane); | |
8652744b | 4931 | if (IS_BROADWELL(dev_priv)) { |
2a114cc1 BW |
4932 | mutex_lock(&dev_priv->rps.hw_lock); |
4933 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4934 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 | 4935 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
b85c1ecf CW |
4936 | if (intel_wait_for_register(dev_priv, |
4937 | IPS_CTL, IPS_ENABLE, 0, | |
4938 | 42)) | |
23d0b130 | 4939 | DRM_ERROR("Timed out waiting for IPS disable\n"); |
e59150dc | 4940 | } else { |
2a114cc1 | 4941 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4942 | POSTING_READ(IPS_CTL); |
4943 | } | |
d77e4531 PZ |
4944 | |
4945 | /* We need to wait for a vblank before we can disable the plane. */ | |
4946 | intel_wait_for_vblank(dev, crtc->pipe); | |
4947 | } | |
4948 | ||
7cac945f | 4949 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4950 | { |
7cac945f | 4951 | if (intel_crtc->overlay) { |
d3eedb1a | 4952 | struct drm_device *dev = intel_crtc->base.dev; |
fac5e23e | 4953 | struct drm_i915_private *dev_priv = to_i915(dev); |
d3eedb1a VS |
4954 | |
4955 | mutex_lock(&dev->struct_mutex); | |
4956 | dev_priv->mm.interruptible = false; | |
4957 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4958 | dev_priv->mm.interruptible = true; | |
4959 | mutex_unlock(&dev->struct_mutex); | |
4960 | } | |
4961 | ||
4962 | /* Let userspace switch the overlay on again. In most cases userspace | |
4963 | * has to recompute where to put it anyway. | |
4964 | */ | |
4965 | } | |
4966 | ||
87d4300a ML |
4967 | /** |
4968 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4969 | * @crtc: the CRTC whose primary plane was just enabled | |
4970 | * | |
4971 | * Performs potentially sleeping operations that must be done after the primary | |
4972 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4973 | * called due to an explicit primary plane update, or due to an implicit | |
4974 | * re-enable that is caused when a sprite plane is updated to no longer | |
4975 | * completely hide the primary plane. | |
4976 | */ | |
4977 | static void | |
4978 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4979 | { |
4980 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4981 | struct drm_i915_private *dev_priv = to_i915(dev); |
a5c4d7bc VS |
4982 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4983 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4984 | |
87d4300a ML |
4985 | /* |
4986 | * FIXME IPS should be fine as long as one plane is | |
4987 | * enabled, but in practice it seems to have problems | |
4988 | * when going from primary only to sprite only and vice | |
4989 | * versa. | |
4990 | */ | |
a5c4d7bc VS |
4991 | hsw_enable_ips(intel_crtc); |
4992 | ||
f99d7069 | 4993 | /* |
87d4300a ML |
4994 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4995 | * So don't enable underrun reporting before at least some planes | |
4996 | * are enabled. | |
4997 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4998 | * but leave the pipe running. | |
f99d7069 | 4999 | */ |
5db94019 | 5000 | if (IS_GEN2(dev_priv)) |
87d4300a ML |
5001 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
5002 | ||
aca7b684 VS |
5003 | /* Underruns don't always raise interrupts, so check manually. */ |
5004 | intel_check_cpu_fifo_underruns(dev_priv); | |
5005 | intel_check_pch_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
5006 | } |
5007 | ||
2622a081 | 5008 | /* FIXME move all this to pre_plane_update() with proper state tracking */ |
87d4300a ML |
5009 | static void |
5010 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
5011 | { |
5012 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 5013 | struct drm_i915_private *dev_priv = to_i915(dev); |
a5c4d7bc VS |
5014 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5015 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 5016 | |
87d4300a ML |
5017 | /* |
5018 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
5019 | * So diasble underrun reporting before all the planes get disabled. | |
5020 | * FIXME: Need to fix the logic to work when we turn off all planes | |
5021 | * but leave the pipe running. | |
5022 | */ | |
5db94019 | 5023 | if (IS_GEN2(dev_priv)) |
87d4300a | 5024 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
a5c4d7bc | 5025 | |
2622a081 VS |
5026 | /* |
5027 | * FIXME IPS should be fine as long as one plane is | |
5028 | * enabled, but in practice it seems to have problems | |
5029 | * when going from primary only to sprite only and vice | |
5030 | * versa. | |
5031 | */ | |
5032 | hsw_disable_ips(intel_crtc); | |
5033 | } | |
5034 | ||
5035 | /* FIXME get rid of this and use pre_plane_update */ | |
5036 | static void | |
5037 | intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) | |
5038 | { | |
5039 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 5040 | struct drm_i915_private *dev_priv = to_i915(dev); |
2622a081 VS |
5041 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5042 | int pipe = intel_crtc->pipe; | |
5043 | ||
5044 | intel_pre_disable_primary(crtc); | |
5045 | ||
87d4300a ML |
5046 | /* |
5047 | * Vblank time updates from the shadow to live plane control register | |
5048 | * are blocked if the memory self-refresh mode is active at that | |
5049 | * moment. So to make sure the plane gets truly disabled, disable | |
5050 | * first the self-refresh mode. The self-refresh enable bit in turn | |
5051 | * will be checked/applied by the HW only at the next frame start | |
5052 | * event which is after the vblank start event, so we need to have a | |
5053 | * wait-for-vblank between disabling the plane and the pipe. | |
5054 | */ | |
49cff963 | 5055 | if (HAS_GMCH_DISPLAY(dev_priv)) { |
87d4300a | 5056 | intel_set_memory_cxsr(dev_priv, false); |
262cd2e1 VS |
5057 | dev_priv->wm.vlv.cxsr = false; |
5058 | intel_wait_for_vblank(dev, pipe); | |
5059 | } | |
87d4300a ML |
5060 | } |
5061 | ||
5a21b665 DV |
5062 | static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) |
5063 | { | |
5064 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); | |
5065 | struct drm_atomic_state *old_state = old_crtc_state->base.state; | |
5066 | struct intel_crtc_state *pipe_config = | |
5067 | to_intel_crtc_state(crtc->base.state); | |
5a21b665 DV |
5068 | struct drm_plane *primary = crtc->base.primary; |
5069 | struct drm_plane_state *old_pri_state = | |
5070 | drm_atomic_get_existing_plane_state(old_state, primary); | |
5071 | ||
5748b6a1 | 5072 | intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits); |
5a21b665 DV |
5073 | |
5074 | crtc->wm.cxsr_allowed = true; | |
5075 | ||
5076 | if (pipe_config->update_wm_post && pipe_config->base.active) | |
5077 | intel_update_watermarks(&crtc->base); | |
5078 | ||
5079 | if (old_pri_state) { | |
5080 | struct intel_plane_state *primary_state = | |
5081 | to_intel_plane_state(primary->state); | |
5082 | struct intel_plane_state *old_primary_state = | |
5083 | to_intel_plane_state(old_pri_state); | |
5084 | ||
5085 | intel_fbc_post_update(crtc); | |
5086 | ||
936e71e3 | 5087 | if (primary_state->base.visible && |
5a21b665 | 5088 | (needs_modeset(&pipe_config->base) || |
936e71e3 | 5089 | !old_primary_state->base.visible)) |
5a21b665 DV |
5090 | intel_post_enable_primary(&crtc->base); |
5091 | } | |
5092 | } | |
5093 | ||
5c74cd73 | 5094 | static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state) |
ac21b225 | 5095 | { |
5c74cd73 | 5096 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
ac21b225 | 5097 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 5098 | struct drm_i915_private *dev_priv = to_i915(dev); |
ab1d3a0e ML |
5099 | struct intel_crtc_state *pipe_config = |
5100 | to_intel_crtc_state(crtc->base.state); | |
5c74cd73 ML |
5101 | struct drm_atomic_state *old_state = old_crtc_state->base.state; |
5102 | struct drm_plane *primary = crtc->base.primary; | |
5103 | struct drm_plane_state *old_pri_state = | |
5104 | drm_atomic_get_existing_plane_state(old_state, primary); | |
5105 | bool modeset = needs_modeset(&pipe_config->base); | |
ac21b225 | 5106 | |
5c74cd73 ML |
5107 | if (old_pri_state) { |
5108 | struct intel_plane_state *primary_state = | |
5109 | to_intel_plane_state(primary->state); | |
5110 | struct intel_plane_state *old_primary_state = | |
5111 | to_intel_plane_state(old_pri_state); | |
5112 | ||
faf68d92 | 5113 | intel_fbc_pre_update(crtc, pipe_config, primary_state); |
31ae71fc | 5114 | |
936e71e3 VS |
5115 | if (old_primary_state->base.visible && |
5116 | (modeset || !primary_state->base.visible)) | |
5c74cd73 ML |
5117 | intel_pre_disable_primary(&crtc->base); |
5118 | } | |
852eb00d | 5119 | |
49cff963 | 5120 | if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev_priv)) { |
852eb00d | 5121 | crtc->wm.cxsr_allowed = false; |
2dfd178d | 5122 | |
2622a081 VS |
5123 | /* |
5124 | * Vblank time updates from the shadow to live plane control register | |
5125 | * are blocked if the memory self-refresh mode is active at that | |
5126 | * moment. So to make sure the plane gets truly disabled, disable | |
5127 | * first the self-refresh mode. The self-refresh enable bit in turn | |
5128 | * will be checked/applied by the HW only at the next frame start | |
5129 | * event which is after the vblank start event, so we need to have a | |
5130 | * wait-for-vblank between disabling the plane and the pipe. | |
5131 | */ | |
5132 | if (old_crtc_state->base.active) { | |
2dfd178d | 5133 | intel_set_memory_cxsr(dev_priv, false); |
2622a081 VS |
5134 | dev_priv->wm.vlv.cxsr = false; |
5135 | intel_wait_for_vblank(dev, crtc->pipe); | |
5136 | } | |
852eb00d | 5137 | } |
92826fcd | 5138 | |
ed4a6a7c MR |
5139 | /* |
5140 | * IVB workaround: must disable low power watermarks for at least | |
5141 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
5142 | * when scaling is disabled. | |
5143 | * | |
5144 | * WaCxSRDisabledForSpriteScaling:ivb | |
5145 | */ | |
5146 | if (pipe_config->disable_lp_wm) { | |
5147 | ilk_disable_lp_wm(dev); | |
5148 | intel_wait_for_vblank(dev, crtc->pipe); | |
5149 | } | |
5150 | ||
5151 | /* | |
5152 | * If we're doing a modeset, we're done. No need to do any pre-vblank | |
5153 | * watermark programming here. | |
5154 | */ | |
5155 | if (needs_modeset(&pipe_config->base)) | |
5156 | return; | |
5157 | ||
5158 | /* | |
5159 | * For platforms that support atomic watermarks, program the | |
5160 | * 'intermediate' watermarks immediately. On pre-gen9 platforms, these | |
5161 | * will be the intermediate values that are safe for both pre- and | |
5162 | * post- vblank; when vblank happens, the 'active' values will be set | |
5163 | * to the final 'target' values and we'll do this again to get the | |
5164 | * optimal watermarks. For gen9+ platforms, the values we program here | |
5165 | * will be the final target values which will get automatically latched | |
5166 | * at vblank time; no further programming will be necessary. | |
5167 | * | |
5168 | * If a platform hasn't been transitioned to atomic watermarks yet, | |
5169 | * we'll continue to update watermarks the old way, if flags tell | |
5170 | * us to. | |
5171 | */ | |
5172 | if (dev_priv->display.initial_watermarks != NULL) | |
5173 | dev_priv->display.initial_watermarks(pipe_config); | |
caed361d | 5174 | else if (pipe_config->update_wm_pre) |
92826fcd | 5175 | intel_update_watermarks(&crtc->base); |
ac21b225 ML |
5176 | } |
5177 | ||
d032ffa0 | 5178 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
5179 | { |
5180 | struct drm_device *dev = crtc->dev; | |
5181 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 5182 | struct drm_plane *p; |
87d4300a ML |
5183 | int pipe = intel_crtc->pipe; |
5184 | ||
7cac945f | 5185 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 5186 | |
d032ffa0 ML |
5187 | drm_for_each_plane_mask(p, dev, plane_mask) |
5188 | to_intel_plane(p)->disable_plane(p, crtc); | |
f98551ae | 5189 | |
f99d7069 DV |
5190 | /* |
5191 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
5192 | * to compute the mask of flip planes precisely. For the time being | |
5193 | * consider this a flip to a NULL plane. | |
5194 | */ | |
5748b6a1 | 5195 | intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe)); |
a5c4d7bc VS |
5196 | } |
5197 | ||
fb1c98b1 | 5198 | static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc, |
fd6bbda9 | 5199 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5200 | struct drm_atomic_state *old_state) |
5201 | { | |
5202 | struct drm_connector_state *old_conn_state; | |
5203 | struct drm_connector *conn; | |
5204 | int i; | |
5205 | ||
5206 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5207 | struct drm_connector_state *conn_state = conn->state; | |
5208 | struct intel_encoder *encoder = | |
5209 | to_intel_encoder(conn_state->best_encoder); | |
5210 | ||
5211 | if (conn_state->crtc != crtc) | |
5212 | continue; | |
5213 | ||
5214 | if (encoder->pre_pll_enable) | |
fd6bbda9 | 5215 | encoder->pre_pll_enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5216 | } |
5217 | } | |
5218 | ||
5219 | static void intel_encoders_pre_enable(struct drm_crtc *crtc, | |
fd6bbda9 | 5220 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5221 | struct drm_atomic_state *old_state) |
5222 | { | |
5223 | struct drm_connector_state *old_conn_state; | |
5224 | struct drm_connector *conn; | |
5225 | int i; | |
5226 | ||
5227 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5228 | struct drm_connector_state *conn_state = conn->state; | |
5229 | struct intel_encoder *encoder = | |
5230 | to_intel_encoder(conn_state->best_encoder); | |
5231 | ||
5232 | if (conn_state->crtc != crtc) | |
5233 | continue; | |
5234 | ||
5235 | if (encoder->pre_enable) | |
fd6bbda9 | 5236 | encoder->pre_enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5237 | } |
5238 | } | |
5239 | ||
5240 | static void intel_encoders_enable(struct drm_crtc *crtc, | |
fd6bbda9 | 5241 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5242 | struct drm_atomic_state *old_state) |
5243 | { | |
5244 | struct drm_connector_state *old_conn_state; | |
5245 | struct drm_connector *conn; | |
5246 | int i; | |
5247 | ||
5248 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5249 | struct drm_connector_state *conn_state = conn->state; | |
5250 | struct intel_encoder *encoder = | |
5251 | to_intel_encoder(conn_state->best_encoder); | |
5252 | ||
5253 | if (conn_state->crtc != crtc) | |
5254 | continue; | |
5255 | ||
fd6bbda9 | 5256 | encoder->enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5257 | intel_opregion_notify_encoder(encoder, true); |
5258 | } | |
5259 | } | |
5260 | ||
5261 | static void intel_encoders_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5262 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5263 | struct drm_atomic_state *old_state) |
5264 | { | |
5265 | struct drm_connector_state *old_conn_state; | |
5266 | struct drm_connector *conn; | |
5267 | int i; | |
5268 | ||
5269 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5270 | struct intel_encoder *encoder = | |
5271 | to_intel_encoder(old_conn_state->best_encoder); | |
5272 | ||
5273 | if (old_conn_state->crtc != crtc) | |
5274 | continue; | |
5275 | ||
5276 | intel_opregion_notify_encoder(encoder, false); | |
fd6bbda9 | 5277 | encoder->disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5278 | } |
5279 | } | |
5280 | ||
5281 | static void intel_encoders_post_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5282 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5283 | struct drm_atomic_state *old_state) |
5284 | { | |
5285 | struct drm_connector_state *old_conn_state; | |
5286 | struct drm_connector *conn; | |
5287 | int i; | |
5288 | ||
5289 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5290 | struct intel_encoder *encoder = | |
5291 | to_intel_encoder(old_conn_state->best_encoder); | |
5292 | ||
5293 | if (old_conn_state->crtc != crtc) | |
5294 | continue; | |
5295 | ||
5296 | if (encoder->post_disable) | |
fd6bbda9 | 5297 | encoder->post_disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5298 | } |
5299 | } | |
5300 | ||
5301 | static void intel_encoders_post_pll_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5302 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5303 | struct drm_atomic_state *old_state) |
5304 | { | |
5305 | struct drm_connector_state *old_conn_state; | |
5306 | struct drm_connector *conn; | |
5307 | int i; | |
5308 | ||
5309 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5310 | struct intel_encoder *encoder = | |
5311 | to_intel_encoder(old_conn_state->best_encoder); | |
5312 | ||
5313 | if (old_conn_state->crtc != crtc) | |
5314 | continue; | |
5315 | ||
5316 | if (encoder->post_pll_disable) | |
fd6bbda9 | 5317 | encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5318 | } |
5319 | } | |
5320 | ||
4a806558 ML |
5321 | static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config, |
5322 | struct drm_atomic_state *old_state) | |
f67a559d | 5323 | { |
4a806558 | 5324 | struct drm_crtc *crtc = pipe_config->base.crtc; |
f67a559d | 5325 | struct drm_device *dev = crtc->dev; |
fac5e23e | 5326 | struct drm_i915_private *dev_priv = to_i915(dev); |
f67a559d JB |
5327 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5328 | int pipe = intel_crtc->pipe; | |
f67a559d | 5329 | |
53d9f4e9 | 5330 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
5331 | return; |
5332 | ||
b2c0593a VS |
5333 | /* |
5334 | * Sometimes spurious CPU pipe underruns happen during FDI | |
5335 | * training, at least with VGA+HDMI cloning. Suppress them. | |
5336 | * | |
5337 | * On ILK we get an occasional spurious CPU pipe underruns | |
5338 | * between eDP port A enable and vdd enable. Also PCH port | |
5339 | * enable seems to result in the occasional CPU pipe underrun. | |
5340 | * | |
5341 | * Spurious PCH underruns also occur during PCH enabling. | |
5342 | */ | |
5343 | if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv)) | |
5344 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
81b088ca VS |
5345 | if (intel_crtc->config->has_pch_encoder) |
5346 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
5347 | ||
6e3c9717 | 5348 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
5349 | intel_prepare_shared_dpll(intel_crtc); |
5350 | ||
37a5650b | 5351 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 5352 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
5353 | |
5354 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 5355 | intel_set_pipe_src_size(intel_crtc); |
29407aab | 5356 | |
6e3c9717 | 5357 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 5358 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5359 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
5360 | } |
5361 | ||
5362 | ironlake_set_pipeconf(crtc); | |
5363 | ||
f67a559d | 5364 | intel_crtc->active = true; |
8664281b | 5365 | |
fd6bbda9 | 5366 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
f67a559d | 5367 | |
6e3c9717 | 5368 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
5369 | /* Note: FDI PLL enabling _must_ be done before we enable the |
5370 | * cpu pipes, hence this is separate from all the other fdi/pch | |
5371 | * enabling. */ | |
88cefb6c | 5372 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
5373 | } else { |
5374 | assert_fdi_tx_disabled(dev_priv, pipe); | |
5375 | assert_fdi_rx_disabled(dev_priv, pipe); | |
5376 | } | |
f67a559d | 5377 | |
b074cec8 | 5378 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 5379 | |
9c54c0dd JB |
5380 | /* |
5381 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5382 | * clocks enabled | |
5383 | */ | |
b95c5321 | 5384 | intel_color_load_luts(&pipe_config->base); |
9c54c0dd | 5385 | |
1d5bf5d9 ID |
5386 | if (dev_priv->display.initial_watermarks != NULL) |
5387 | dev_priv->display.initial_watermarks(intel_crtc->config); | |
e1fdc473 | 5388 | intel_enable_pipe(intel_crtc); |
f67a559d | 5389 | |
6e3c9717 | 5390 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 5391 | ironlake_pch_enable(crtc); |
c98e9dcf | 5392 | |
f9b61ff6 DV |
5393 | assert_vblank_disabled(crtc); |
5394 | drm_crtc_vblank_on(crtc); | |
5395 | ||
fd6bbda9 | 5396 | intel_encoders_enable(crtc, pipe_config, old_state); |
61b77ddd | 5397 | |
6e266956 | 5398 | if (HAS_PCH_CPT(dev_priv)) |
a1520318 | 5399 | cpt_verify_modeset(dev, intel_crtc->pipe); |
37ca8d4c VS |
5400 | |
5401 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ | |
5402 | if (intel_crtc->config->has_pch_encoder) | |
5403 | intel_wait_for_vblank(dev, pipe); | |
b2c0593a | 5404 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
37ca8d4c | 5405 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 JB |
5406 | } |
5407 | ||
42db64ef PZ |
5408 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
5409 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
5410 | { | |
50a0bc90 | 5411 | return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A; |
42db64ef PZ |
5412 | } |
5413 | ||
4a806558 ML |
5414 | static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, |
5415 | struct drm_atomic_state *old_state) | |
4f771f10 | 5416 | { |
4a806558 | 5417 | struct drm_crtc *crtc = pipe_config->base.crtc; |
4f771f10 | 5418 | struct drm_device *dev = crtc->dev; |
fac5e23e | 5419 | struct drm_i915_private *dev_priv = to_i915(dev); |
4f771f10 | 5420 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
99d736a2 | 5421 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4d1de975 | 5422 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
4f771f10 | 5423 | |
53d9f4e9 | 5424 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
5425 | return; |
5426 | ||
81b088ca VS |
5427 | if (intel_crtc->config->has_pch_encoder) |
5428 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5429 | false); | |
5430 | ||
fd6bbda9 | 5431 | intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); |
95a7a2ae | 5432 | |
8106ddbd | 5433 | if (intel_crtc->config->shared_dpll) |
df8ad70c DV |
5434 | intel_enable_shared_dpll(intel_crtc); |
5435 | ||
37a5650b | 5436 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 5437 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 | 5438 | |
d7edc4e5 | 5439 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 JN |
5440 | intel_set_pipe_timings(intel_crtc); |
5441 | ||
bc58be60 | 5442 | intel_set_pipe_src_size(intel_crtc); |
229fca97 | 5443 | |
4d1de975 JN |
5444 | if (cpu_transcoder != TRANSCODER_EDP && |
5445 | !transcoder_is_dsi(cpu_transcoder)) { | |
5446 | I915_WRITE(PIPE_MULT(cpu_transcoder), | |
6e3c9717 | 5447 | intel_crtc->config->pixel_multiplier - 1); |
ebb69c95 CT |
5448 | } |
5449 | ||
6e3c9717 | 5450 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 5451 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5452 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
5453 | } |
5454 | ||
d7edc4e5 | 5455 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 JN |
5456 | haswell_set_pipeconf(crtc); |
5457 | ||
391bf048 | 5458 | haswell_set_pipemisc(crtc); |
229fca97 | 5459 | |
b95c5321 | 5460 | intel_color_set_csc(&pipe_config->base); |
229fca97 | 5461 | |
4f771f10 | 5462 | intel_crtc->active = true; |
8664281b | 5463 | |
6b698516 DV |
5464 | if (intel_crtc->config->has_pch_encoder) |
5465 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
5466 | else | |
5467 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
5468 | ||
fd6bbda9 | 5469 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
4f771f10 | 5470 | |
d2d65408 | 5471 | if (intel_crtc->config->has_pch_encoder) |
4fe9467d | 5472 | dev_priv->display.fdi_link_train(crtc); |
4fe9467d | 5473 | |
d7edc4e5 | 5474 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5475 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 5476 | |
1c132b44 | 5477 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5478 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 5479 | else |
1c132b44 | 5480 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
5481 | |
5482 | /* | |
5483 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5484 | * clocks enabled | |
5485 | */ | |
b95c5321 | 5486 | intel_color_load_luts(&pipe_config->base); |
4f771f10 | 5487 | |
1f544388 | 5488 | intel_ddi_set_pipe_settings(crtc); |
d7edc4e5 | 5489 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5490 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 5491 | |
1d5bf5d9 ID |
5492 | if (dev_priv->display.initial_watermarks != NULL) |
5493 | dev_priv->display.initial_watermarks(pipe_config); | |
5494 | else | |
5495 | intel_update_watermarks(crtc); | |
4d1de975 JN |
5496 | |
5497 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ | |
d7edc4e5 | 5498 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 | 5499 | intel_enable_pipe(intel_crtc); |
42db64ef | 5500 | |
6e3c9717 | 5501 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 5502 | lpt_pch_enable(crtc); |
4f771f10 | 5503 | |
a65347ba | 5504 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
5505 | intel_ddi_set_vc_payload_alloc(crtc, true); |
5506 | ||
f9b61ff6 DV |
5507 | assert_vblank_disabled(crtc); |
5508 | drm_crtc_vblank_on(crtc); | |
5509 | ||
fd6bbda9 | 5510 | intel_encoders_enable(crtc, pipe_config, old_state); |
4f771f10 | 5511 | |
6b698516 DV |
5512 | if (intel_crtc->config->has_pch_encoder) { |
5513 | intel_wait_for_vblank(dev, pipe); | |
5514 | intel_wait_for_vblank(dev, pipe); | |
5515 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
d2d65408 VS |
5516 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5517 | true); | |
6b698516 | 5518 | } |
d2d65408 | 5519 | |
e4916946 PZ |
5520 | /* If we change the relative order between pipe/planes enabling, we need |
5521 | * to change the workaround. */ | |
99d736a2 | 5522 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
772c2a51 | 5523 | if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { |
99d736a2 ML |
5524 | intel_wait_for_vblank(dev, hsw_workaround_pipe); |
5525 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
5526 | } | |
4f771f10 PZ |
5527 | } |
5528 | ||
bfd16b2a | 5529 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
5530 | { |
5531 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 5532 | struct drm_i915_private *dev_priv = to_i915(dev); |
3f8dce3a DV |
5533 | int pipe = crtc->pipe; |
5534 | ||
5535 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
5536 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 5537 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
5538 | I915_WRITE(PF_CTL(pipe), 0); |
5539 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
5540 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
5541 | } | |
5542 | } | |
5543 | ||
4a806558 ML |
5544 | static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state, |
5545 | struct drm_atomic_state *old_state) | |
6be4a607 | 5546 | { |
4a806558 | 5547 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
6be4a607 | 5548 | struct drm_device *dev = crtc->dev; |
fac5e23e | 5549 | struct drm_i915_private *dev_priv = to_i915(dev); |
6be4a607 JB |
5550 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5551 | int pipe = intel_crtc->pipe; | |
b52eb4dc | 5552 | |
b2c0593a VS |
5553 | /* |
5554 | * Sometimes spurious CPU pipe underruns happen when the | |
5555 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
5556 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
5557 | */ | |
5558 | if (intel_crtc->config->has_pch_encoder) { | |
5559 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
37ca8d4c | 5560 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
b2c0593a | 5561 | } |
37ca8d4c | 5562 | |
fd6bbda9 | 5563 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
ea9d758d | 5564 | |
f9b61ff6 DV |
5565 | drm_crtc_vblank_off(crtc); |
5566 | assert_vblank_disabled(crtc); | |
5567 | ||
575f7ab7 | 5568 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5569 | |
bfd16b2a | 5570 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 5571 | |
b2c0593a | 5572 | if (intel_crtc->config->has_pch_encoder) |
5a74f70a VS |
5573 | ironlake_fdi_disable(crtc); |
5574 | ||
fd6bbda9 | 5575 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
2c07245f | 5576 | |
6e3c9717 | 5577 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5578 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5579 | |
6e266956 | 5580 | if (HAS_PCH_CPT(dev_priv)) { |
f0f59a00 VS |
5581 | i915_reg_t reg; |
5582 | u32 temp; | |
5583 | ||
d925c59a DV |
5584 | /* disable TRANS_DP_CTL */ |
5585 | reg = TRANS_DP_CTL(pipe); | |
5586 | temp = I915_READ(reg); | |
5587 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5588 | TRANS_DP_PORT_SEL_MASK); | |
5589 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5590 | I915_WRITE(reg, temp); | |
5591 | ||
5592 | /* disable DPLL_SEL */ | |
5593 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5594 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5595 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5596 | } |
e3421a18 | 5597 | |
d925c59a DV |
5598 | ironlake_fdi_pll_disable(intel_crtc); |
5599 | } | |
81b088ca | 5600 | |
b2c0593a | 5601 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
81b088ca | 5602 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 | 5603 | } |
1b3c7a47 | 5604 | |
4a806558 ML |
5605 | static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state, |
5606 | struct drm_atomic_state *old_state) | |
ee7b9f93 | 5607 | { |
4a806558 | 5608 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
4f771f10 | 5609 | struct drm_device *dev = crtc->dev; |
fac5e23e | 5610 | struct drm_i915_private *dev_priv = to_i915(dev); |
ee7b9f93 | 5611 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 5612 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5613 | |
d2d65408 VS |
5614 | if (intel_crtc->config->has_pch_encoder) |
5615 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5616 | false); | |
5617 | ||
fd6bbda9 | 5618 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
4f771f10 | 5619 | |
f9b61ff6 DV |
5620 | drm_crtc_vblank_off(crtc); |
5621 | assert_vblank_disabled(crtc); | |
5622 | ||
4d1de975 | 5623 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ |
d7edc4e5 | 5624 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 | 5625 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5626 | |
6e3c9717 | 5627 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
5628 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5629 | ||
d7edc4e5 | 5630 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5631 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5632 | |
1c132b44 | 5633 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5634 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5635 | else |
bfd16b2a | 5636 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 5637 | |
d7edc4e5 | 5638 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5639 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 5640 | |
fd6bbda9 | 5641 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
81b088ca | 5642 | |
b7076546 | 5643 | if (old_crtc_state->has_pch_encoder) |
81b088ca VS |
5644 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5645 | true); | |
4f771f10 PZ |
5646 | } |
5647 | ||
2dd24552 JB |
5648 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5649 | { | |
5650 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 5651 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 5652 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5653 | |
681a8504 | 5654 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5655 | return; |
5656 | ||
2dd24552 | 5657 | /* |
c0b03411 DV |
5658 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5659 | * according to register description and PRM. | |
2dd24552 | 5660 | */ |
c0b03411 DV |
5661 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5662 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5663 | |
b074cec8 JB |
5664 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5665 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5666 | |
5667 | /* Border color in case we don't scale up to the full screen. Black by | |
5668 | * default, change to something else for debugging. */ | |
5669 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5670 | } |
5671 | ||
d05410f9 DA |
5672 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5673 | { | |
5674 | switch (port) { | |
5675 | case PORT_A: | |
6331a704 | 5676 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
d05410f9 | 5677 | case PORT_B: |
6331a704 | 5678 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
d05410f9 | 5679 | case PORT_C: |
6331a704 | 5680 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
d05410f9 | 5681 | case PORT_D: |
6331a704 | 5682 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
d8e19f99 | 5683 | case PORT_E: |
6331a704 | 5684 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
d05410f9 | 5685 | default: |
b9fec167 | 5686 | MISSING_CASE(port); |
d05410f9 DA |
5687 | return POWER_DOMAIN_PORT_OTHER; |
5688 | } | |
5689 | } | |
5690 | ||
25f78f58 VS |
5691 | static enum intel_display_power_domain port_to_aux_power_domain(enum port port) |
5692 | { | |
5693 | switch (port) { | |
5694 | case PORT_A: | |
5695 | return POWER_DOMAIN_AUX_A; | |
5696 | case PORT_B: | |
5697 | return POWER_DOMAIN_AUX_B; | |
5698 | case PORT_C: | |
5699 | return POWER_DOMAIN_AUX_C; | |
5700 | case PORT_D: | |
5701 | return POWER_DOMAIN_AUX_D; | |
5702 | case PORT_E: | |
5703 | /* FIXME: Check VBT for actual wiring of PORT E */ | |
5704 | return POWER_DOMAIN_AUX_D; | |
5705 | default: | |
b9fec167 | 5706 | MISSING_CASE(port); |
25f78f58 VS |
5707 | return POWER_DOMAIN_AUX_A; |
5708 | } | |
5709 | } | |
5710 | ||
319be8ae ID |
5711 | enum intel_display_power_domain |
5712 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5713 | { | |
4f8036a2 | 5714 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); |
319be8ae ID |
5715 | struct intel_digital_port *intel_dig_port; |
5716 | ||
5717 | switch (intel_encoder->type) { | |
5718 | case INTEL_OUTPUT_UNKNOWN: | |
5719 | /* Only DDI platforms should ever use this output type */ | |
4f8036a2 | 5720 | WARN_ON_ONCE(!HAS_DDI(dev_priv)); |
cca0502b | 5721 | case INTEL_OUTPUT_DP: |
319be8ae ID |
5722 | case INTEL_OUTPUT_HDMI: |
5723 | case INTEL_OUTPUT_EDP: | |
5724 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 5725 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
5726 | case INTEL_OUTPUT_DP_MST: |
5727 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5728 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
5729 | case INTEL_OUTPUT_ANALOG: |
5730 | return POWER_DOMAIN_PORT_CRT; | |
5731 | case INTEL_OUTPUT_DSI: | |
5732 | return POWER_DOMAIN_PORT_DSI; | |
5733 | default: | |
5734 | return POWER_DOMAIN_PORT_OTHER; | |
5735 | } | |
5736 | } | |
5737 | ||
25f78f58 VS |
5738 | enum intel_display_power_domain |
5739 | intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder) | |
5740 | { | |
4f8036a2 | 5741 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); |
25f78f58 VS |
5742 | struct intel_digital_port *intel_dig_port; |
5743 | ||
5744 | switch (intel_encoder->type) { | |
5745 | case INTEL_OUTPUT_UNKNOWN: | |
651174a4 ID |
5746 | case INTEL_OUTPUT_HDMI: |
5747 | /* | |
5748 | * Only DDI platforms should ever use these output types. | |
5749 | * We can get here after the HDMI detect code has already set | |
5750 | * the type of the shared encoder. Since we can't be sure | |
5751 | * what's the status of the given connectors, play safe and | |
5752 | * run the DP detection too. | |
5753 | */ | |
4f8036a2 | 5754 | WARN_ON_ONCE(!HAS_DDI(dev_priv)); |
cca0502b | 5755 | case INTEL_OUTPUT_DP: |
25f78f58 VS |
5756 | case INTEL_OUTPUT_EDP: |
5757 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
5758 | return port_to_aux_power_domain(intel_dig_port->port); | |
5759 | case INTEL_OUTPUT_DP_MST: | |
5760 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5761 | return port_to_aux_power_domain(intel_dig_port->port); | |
5762 | default: | |
b9fec167 | 5763 | MISSING_CASE(intel_encoder->type); |
25f78f58 VS |
5764 | return POWER_DOMAIN_AUX_A; |
5765 | } | |
5766 | } | |
5767 | ||
74bff5f9 ML |
5768 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc, |
5769 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5770 | { |
319be8ae | 5771 | struct drm_device *dev = crtc->dev; |
74bff5f9 | 5772 | struct drm_encoder *encoder; |
319be8ae ID |
5773 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5774 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca | 5775 | unsigned long mask; |
74bff5f9 | 5776 | enum transcoder transcoder = crtc_state->cpu_transcoder; |
77d22dca | 5777 | |
74bff5f9 | 5778 | if (!crtc_state->base.active) |
292b990e ML |
5779 | return 0; |
5780 | ||
77d22dca ID |
5781 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5782 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
74bff5f9 ML |
5783 | if (crtc_state->pch_pfit.enabled || |
5784 | crtc_state->pch_pfit.force_thru) | |
77d22dca ID |
5785 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5786 | ||
74bff5f9 ML |
5787 | drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) { |
5788 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
5789 | ||
319be8ae | 5790 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); |
74bff5f9 | 5791 | } |
319be8ae | 5792 | |
15e7ec29 ML |
5793 | if (crtc_state->shared_dpll) |
5794 | mask |= BIT(POWER_DOMAIN_PLLS); | |
5795 | ||
77d22dca ID |
5796 | return mask; |
5797 | } | |
5798 | ||
74bff5f9 ML |
5799 | static unsigned long |
5800 | modeset_get_crtc_power_domains(struct drm_crtc *crtc, | |
5801 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5802 | { |
fac5e23e | 5803 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
292b990e ML |
5804 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5805 | enum intel_display_power_domain domain; | |
5a21b665 | 5806 | unsigned long domains, new_domains, old_domains; |
77d22dca | 5807 | |
292b990e | 5808 | old_domains = intel_crtc->enabled_power_domains; |
74bff5f9 ML |
5809 | intel_crtc->enabled_power_domains = new_domains = |
5810 | get_crtc_power_domains(crtc, crtc_state); | |
77d22dca | 5811 | |
5a21b665 | 5812 | domains = new_domains & ~old_domains; |
292b990e ML |
5813 | |
5814 | for_each_power_domain(domain, domains) | |
5815 | intel_display_power_get(dev_priv, domain); | |
5816 | ||
5a21b665 | 5817 | return old_domains & ~new_domains; |
292b990e ML |
5818 | } |
5819 | ||
5820 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
5821 | unsigned long domains) | |
5822 | { | |
5823 | enum intel_display_power_domain domain; | |
5824 | ||
5825 | for_each_power_domain(domain, domains) | |
5826 | intel_display_power_put(dev_priv, domain); | |
5827 | } | |
77d22dca | 5828 | |
adafdc6f MK |
5829 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
5830 | { | |
5831 | int max_cdclk_freq = dev_priv->max_cdclk_freq; | |
5832 | ||
5833 | if (INTEL_INFO(dev_priv)->gen >= 9 || | |
5834 | IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
5835 | return max_cdclk_freq; | |
5836 | else if (IS_CHERRYVIEW(dev_priv)) | |
5837 | return max_cdclk_freq*95/100; | |
5838 | else if (INTEL_INFO(dev_priv)->gen < 4) | |
5839 | return 2*max_cdclk_freq*90/100; | |
5840 | else | |
5841 | return max_cdclk_freq*90/100; | |
5842 | } | |
5843 | ||
b2045352 VS |
5844 | static int skl_calc_cdclk(int max_pixclk, int vco); |
5845 | ||
560a7ae4 DL |
5846 | static void intel_update_max_cdclk(struct drm_device *dev) |
5847 | { | |
fac5e23e | 5848 | struct drm_i915_private *dev_priv = to_i915(dev); |
560a7ae4 | 5849 | |
0853723b | 5850 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { |
560a7ae4 | 5851 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; |
b2045352 VS |
5852 | int max_cdclk, vco; |
5853 | ||
5854 | vco = dev_priv->skl_preferred_vco_freq; | |
63911d72 | 5855 | WARN_ON(vco != 8100000 && vco != 8640000); |
560a7ae4 | 5856 | |
b2045352 VS |
5857 | /* |
5858 | * Use the lower (vco 8640) cdclk values as a | |
5859 | * first guess. skl_calc_cdclk() will correct it | |
5860 | * if the preferred vco is 8100 instead. | |
5861 | */ | |
560a7ae4 | 5862 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) |
487ed2e4 | 5863 | max_cdclk = 617143; |
560a7ae4 | 5864 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) |
b2045352 | 5865 | max_cdclk = 540000; |
560a7ae4 | 5866 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) |
b2045352 | 5867 | max_cdclk = 432000; |
560a7ae4 | 5868 | else |
487ed2e4 | 5869 | max_cdclk = 308571; |
b2045352 VS |
5870 | |
5871 | dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); | |
e2d214ae | 5872 | } else if (IS_BROXTON(dev_priv)) { |
281c114f | 5873 | dev_priv->max_cdclk_freq = 624000; |
8652744b | 5874 | } else if (IS_BROADWELL(dev_priv)) { |
560a7ae4 DL |
5875 | /* |
5876 | * FIXME with extra cooling we can allow | |
5877 | * 540 MHz for ULX and 675 Mhz for ULT. | |
5878 | * How can we know if extra cooling is | |
5879 | * available? PCI ID, VTB, something else? | |
5880 | */ | |
5881 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
5882 | dev_priv->max_cdclk_freq = 450000; | |
50a0bc90 | 5883 | else if (IS_BDW_ULX(dev_priv)) |
560a7ae4 | 5884 | dev_priv->max_cdclk_freq = 450000; |
50a0bc90 | 5885 | else if (IS_BDW_ULT(dev_priv)) |
560a7ae4 DL |
5886 | dev_priv->max_cdclk_freq = 540000; |
5887 | else | |
5888 | dev_priv->max_cdclk_freq = 675000; | |
920a14b2 | 5889 | } else if (IS_CHERRYVIEW(dev_priv)) { |
0904deaf | 5890 | dev_priv->max_cdclk_freq = 320000; |
11a914c2 | 5891 | } else if (IS_VALLEYVIEW(dev_priv)) { |
560a7ae4 DL |
5892 | dev_priv->max_cdclk_freq = 400000; |
5893 | } else { | |
5894 | /* otherwise assume cdclk is fixed */ | |
5895 | dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; | |
5896 | } | |
5897 | ||
adafdc6f MK |
5898 | dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); |
5899 | ||
560a7ae4 DL |
5900 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", |
5901 | dev_priv->max_cdclk_freq); | |
adafdc6f MK |
5902 | |
5903 | DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", | |
5904 | dev_priv->max_dotclk_freq); | |
560a7ae4 DL |
5905 | } |
5906 | ||
5907 | static void intel_update_cdclk(struct drm_device *dev) | |
5908 | { | |
fac5e23e | 5909 | struct drm_i915_private *dev_priv = to_i915(dev); |
560a7ae4 DL |
5910 | |
5911 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
2f2a121a | 5912 | |
83d7c81f | 5913 | if (INTEL_GEN(dev_priv) >= 9) |
709e05c3 VS |
5914 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n", |
5915 | dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco, | |
5916 | dev_priv->cdclk_pll.ref); | |
2f2a121a VS |
5917 | else |
5918 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", | |
5919 | dev_priv->cdclk_freq); | |
560a7ae4 DL |
5920 | |
5921 | /* | |
b5d99ff9 VS |
5922 | * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): |
5923 | * Programmng [sic] note: bit[9:2] should be programmed to the number | |
5924 | * of cdclk that generates 4MHz reference clock freq which is used to | |
5925 | * generate GMBus clock. This will vary with the cdclk freq. | |
560a7ae4 | 5926 | */ |
b5d99ff9 | 5927 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
560a7ae4 | 5928 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); |
560a7ae4 DL |
5929 | } |
5930 | ||
92891e45 VS |
5931 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ |
5932 | static int skl_cdclk_decimal(int cdclk) | |
5933 | { | |
5934 | return DIV_ROUND_CLOSEST(cdclk - 1000, 500); | |
5935 | } | |
5936 | ||
5f199dfa VS |
5937 | static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk) |
5938 | { | |
5939 | int ratio; | |
5940 | ||
5941 | if (cdclk == dev_priv->cdclk_pll.ref) | |
5942 | return 0; | |
5943 | ||
5944 | switch (cdclk) { | |
5945 | default: | |
5946 | MISSING_CASE(cdclk); | |
5947 | case 144000: | |
5948 | case 288000: | |
5949 | case 384000: | |
5950 | case 576000: | |
5951 | ratio = 60; | |
5952 | break; | |
5953 | case 624000: | |
5954 | ratio = 65; | |
5955 | break; | |
5956 | } | |
5957 | ||
5958 | return dev_priv->cdclk_pll.ref * ratio; | |
5959 | } | |
5960 | ||
2b73001e VS |
5961 | static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) |
5962 | { | |
5963 | I915_WRITE(BXT_DE_PLL_ENABLE, 0); | |
5964 | ||
5965 | /* Timeout 200us */ | |
95cac283 CW |
5966 | if (intel_wait_for_register(dev_priv, |
5967 | BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0, | |
5968 | 1)) | |
2b73001e | 5969 | DRM_ERROR("timeout waiting for DE PLL unlock\n"); |
83d7c81f VS |
5970 | |
5971 | dev_priv->cdclk_pll.vco = 0; | |
2b73001e VS |
5972 | } |
5973 | ||
5f199dfa | 5974 | static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) |
2b73001e | 5975 | { |
5f199dfa | 5976 | int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref); |
2b73001e VS |
5977 | u32 val; |
5978 | ||
5979 | val = I915_READ(BXT_DE_PLL_CTL); | |
5980 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5f199dfa | 5981 | val |= BXT_DE_PLL_RATIO(ratio); |
2b73001e VS |
5982 | I915_WRITE(BXT_DE_PLL_CTL, val); |
5983 | ||
5984 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5985 | ||
5986 | /* Timeout 200us */ | |
e084e1b9 CW |
5987 | if (intel_wait_for_register(dev_priv, |
5988 | BXT_DE_PLL_ENABLE, | |
5989 | BXT_DE_PLL_LOCK, | |
5990 | BXT_DE_PLL_LOCK, | |
5991 | 1)) | |
2b73001e | 5992 | DRM_ERROR("timeout waiting for DE PLL lock\n"); |
83d7c81f | 5993 | |
5f199dfa | 5994 | dev_priv->cdclk_pll.vco = vco; |
2b73001e VS |
5995 | } |
5996 | ||
324513c0 | 5997 | static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk) |
f8437dd1 | 5998 | { |
5f199dfa VS |
5999 | u32 val, divider; |
6000 | int vco, ret; | |
f8437dd1 | 6001 | |
5f199dfa VS |
6002 | vco = bxt_de_pll_vco(dev_priv, cdclk); |
6003 | ||
6004 | DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco); | |
6005 | ||
6006 | /* cdclk = vco / 2 / div{1,1.5,2,4} */ | |
6007 | switch (DIV_ROUND_CLOSEST(vco, cdclk)) { | |
6008 | case 8: | |
f8437dd1 | 6009 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; |
f8437dd1 | 6010 | break; |
5f199dfa | 6011 | case 4: |
f8437dd1 | 6012 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; |
f8437dd1 | 6013 | break; |
5f199dfa | 6014 | case 3: |
f8437dd1 | 6015 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; |
f8437dd1 | 6016 | break; |
5f199dfa | 6017 | case 2: |
f8437dd1 | 6018 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; |
f8437dd1 VK |
6019 | break; |
6020 | default: | |
5f199dfa VS |
6021 | WARN_ON(cdclk != dev_priv->cdclk_pll.ref); |
6022 | WARN_ON(vco != 0); | |
f8437dd1 | 6023 | |
5f199dfa VS |
6024 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; |
6025 | break; | |
f8437dd1 VK |
6026 | } |
6027 | ||
f8437dd1 | 6028 | /* Inform power controller of upcoming frequency change */ |
5f199dfa | 6029 | mutex_lock(&dev_priv->rps.hw_lock); |
f8437dd1 VK |
6030 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, |
6031 | 0x80000000); | |
6032 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6033 | ||
6034 | if (ret) { | |
6035 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
9ef56154 | 6036 | ret, cdclk); |
f8437dd1 VK |
6037 | return; |
6038 | } | |
6039 | ||
5f199dfa VS |
6040 | if (dev_priv->cdclk_pll.vco != 0 && |
6041 | dev_priv->cdclk_pll.vco != vco) | |
2b73001e | 6042 | bxt_de_pll_disable(dev_priv); |
f8437dd1 | 6043 | |
5f199dfa VS |
6044 | if (dev_priv->cdclk_pll.vco != vco) |
6045 | bxt_de_pll_enable(dev_priv, vco); | |
f8437dd1 | 6046 | |
5f199dfa VS |
6047 | val = divider | skl_cdclk_decimal(cdclk); |
6048 | /* | |
6049 | * FIXME if only the cd2x divider needs changing, it could be done | |
6050 | * without shutting off the pipe (if only one pipe is active). | |
6051 | */ | |
6052 | val |= BXT_CDCLK_CD2X_PIPE_NONE; | |
6053 | /* | |
6054 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
6055 | * enable otherwise. | |
6056 | */ | |
6057 | if (cdclk >= 500000) | |
6058 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
6059 | I915_WRITE(CDCLK_CTL, val); | |
f8437dd1 VK |
6060 | |
6061 | mutex_lock(&dev_priv->rps.hw_lock); | |
6062 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
9ef56154 | 6063 | DIV_ROUND_UP(cdclk, 25000)); |
f8437dd1 VK |
6064 | mutex_unlock(&dev_priv->rps.hw_lock); |
6065 | ||
6066 | if (ret) { | |
6067 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
9ef56154 | 6068 | ret, cdclk); |
f8437dd1 VK |
6069 | return; |
6070 | } | |
6071 | ||
91c8a326 | 6072 | intel_update_cdclk(&dev_priv->drm); |
f8437dd1 VK |
6073 | } |
6074 | ||
d66a2194 | 6075 | static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) |
f8437dd1 | 6076 | { |
d66a2194 ID |
6077 | u32 cdctl, expected; |
6078 | ||
91c8a326 | 6079 | intel_update_cdclk(&dev_priv->drm); |
f8437dd1 | 6080 | |
d66a2194 ID |
6081 | if (dev_priv->cdclk_pll.vco == 0 || |
6082 | dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref) | |
6083 | goto sanitize; | |
6084 | ||
6085 | /* DPLL okay; verify the cdclock | |
6086 | * | |
6087 | * Some BIOS versions leave an incorrect decimal frequency value and | |
6088 | * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, | |
6089 | * so sanitize this register. | |
6090 | */ | |
6091 | cdctl = I915_READ(CDCLK_CTL); | |
6092 | /* | |
6093 | * Let's ignore the pipe field, since BIOS could have configured the | |
6094 | * dividers both synching to an active pipe, or asynchronously | |
6095 | * (PIPE_NONE). | |
6096 | */ | |
6097 | cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE; | |
6098 | ||
6099 | expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) | | |
6100 | skl_cdclk_decimal(dev_priv->cdclk_freq); | |
6101 | /* | |
6102 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
6103 | * enable otherwise. | |
6104 | */ | |
6105 | if (dev_priv->cdclk_freq >= 500000) | |
6106 | expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
6107 | ||
6108 | if (cdctl == expected) | |
6109 | /* All well; nothing to sanitize */ | |
6110 | return; | |
6111 | ||
6112 | sanitize: | |
6113 | DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); | |
6114 | ||
6115 | /* force cdclk programming */ | |
6116 | dev_priv->cdclk_freq = 0; | |
6117 | ||
6118 | /* force full PLL disable + enable */ | |
6119 | dev_priv->cdclk_pll.vco = -1; | |
6120 | } | |
6121 | ||
324513c0 | 6122 | void bxt_init_cdclk(struct drm_i915_private *dev_priv) |
d66a2194 ID |
6123 | { |
6124 | bxt_sanitize_cdclk(dev_priv); | |
6125 | ||
6126 | if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) | |
089c6fd5 | 6127 | return; |
c2e001ef | 6128 | |
f8437dd1 VK |
6129 | /* |
6130 | * FIXME: | |
6131 | * - The initial CDCLK needs to be read from VBT. | |
6132 | * Need to make this change after VBT has changes for BXT. | |
f8437dd1 | 6133 | */ |
324513c0 | 6134 | bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0)); |
f8437dd1 VK |
6135 | } |
6136 | ||
324513c0 | 6137 | void bxt_uninit_cdclk(struct drm_i915_private *dev_priv) |
f8437dd1 | 6138 | { |
324513c0 | 6139 | bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref); |
f8437dd1 VK |
6140 | } |
6141 | ||
a8ca4934 VS |
6142 | static int skl_calc_cdclk(int max_pixclk, int vco) |
6143 | { | |
63911d72 | 6144 | if (vco == 8640000) { |
a8ca4934 | 6145 | if (max_pixclk > 540000) |
487ed2e4 | 6146 | return 617143; |
a8ca4934 VS |
6147 | else if (max_pixclk > 432000) |
6148 | return 540000; | |
487ed2e4 | 6149 | else if (max_pixclk > 308571) |
a8ca4934 VS |
6150 | return 432000; |
6151 | else | |
487ed2e4 | 6152 | return 308571; |
a8ca4934 | 6153 | } else { |
a8ca4934 VS |
6154 | if (max_pixclk > 540000) |
6155 | return 675000; | |
6156 | else if (max_pixclk > 450000) | |
6157 | return 540000; | |
6158 | else if (max_pixclk > 337500) | |
6159 | return 450000; | |
6160 | else | |
6161 | return 337500; | |
6162 | } | |
6163 | } | |
6164 | ||
ea61791e VS |
6165 | static void |
6166 | skl_dpll0_update(struct drm_i915_private *dev_priv) | |
5d96d8af | 6167 | { |
ea61791e | 6168 | u32 val; |
5d96d8af | 6169 | |
709e05c3 | 6170 | dev_priv->cdclk_pll.ref = 24000; |
1c3f7700 | 6171 | dev_priv->cdclk_pll.vco = 0; |
709e05c3 | 6172 | |
ea61791e | 6173 | val = I915_READ(LCPLL1_CTL); |
1c3f7700 | 6174 | if ((val & LCPLL_PLL_ENABLE) == 0) |
ea61791e | 6175 | return; |
5d96d8af | 6176 | |
1c3f7700 ID |
6177 | if (WARN_ON((val & LCPLL_PLL_LOCK) == 0)) |
6178 | return; | |
9f7eb31a | 6179 | |
ea61791e VS |
6180 | val = I915_READ(DPLL_CTRL1); |
6181 | ||
1c3f7700 ID |
6182 | if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | |
6183 | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
6184 | DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != | |
6185 | DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) | |
6186 | return; | |
9f7eb31a | 6187 | |
ea61791e VS |
6188 | switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { |
6189 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): | |
6190 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): | |
6191 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): | |
6192 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): | |
63911d72 | 6193 | dev_priv->cdclk_pll.vco = 8100000; |
ea61791e VS |
6194 | break; |
6195 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): | |
6196 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): | |
63911d72 | 6197 | dev_priv->cdclk_pll.vco = 8640000; |
ea61791e VS |
6198 | break; |
6199 | default: | |
6200 | MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
ea61791e VS |
6201 | break; |
6202 | } | |
5d96d8af DL |
6203 | } |
6204 | ||
b2045352 VS |
6205 | void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco) |
6206 | { | |
6207 | bool changed = dev_priv->skl_preferred_vco_freq != vco; | |
6208 | ||
6209 | dev_priv->skl_preferred_vco_freq = vco; | |
6210 | ||
6211 | if (changed) | |
91c8a326 | 6212 | intel_update_max_cdclk(&dev_priv->drm); |
b2045352 VS |
6213 | } |
6214 | ||
5d96d8af | 6215 | static void |
3861fc60 | 6216 | skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) |
5d96d8af | 6217 | { |
a8ca4934 | 6218 | int min_cdclk = skl_calc_cdclk(0, vco); |
5d96d8af DL |
6219 | u32 val; |
6220 | ||
63911d72 | 6221 | WARN_ON(vco != 8100000 && vco != 8640000); |
b2045352 | 6222 | |
5d96d8af | 6223 | /* select the minimum CDCLK before enabling DPLL 0 */ |
9ef56154 | 6224 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk); |
5d96d8af DL |
6225 | I915_WRITE(CDCLK_CTL, val); |
6226 | POSTING_READ(CDCLK_CTL); | |
6227 | ||
6228 | /* | |
6229 | * We always enable DPLL0 with the lowest link rate possible, but still | |
6230 | * taking into account the VCO required to operate the eDP panel at the | |
6231 | * desired frequency. The usual DP link rates operate with a VCO of | |
6232 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. | |
6233 | * The modeset code is responsible for the selection of the exact link | |
6234 | * rate later on, with the constraint of choosing a frequency that | |
a8ca4934 | 6235 | * works with vco. |
5d96d8af DL |
6236 | */ |
6237 | val = I915_READ(DPLL_CTRL1); | |
6238 | ||
6239 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
6240 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
6241 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
63911d72 | 6242 | if (vco == 8640000) |
5d96d8af DL |
6243 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, |
6244 | SKL_DPLL0); | |
6245 | else | |
6246 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, | |
6247 | SKL_DPLL0); | |
6248 | ||
6249 | I915_WRITE(DPLL_CTRL1, val); | |
6250 | POSTING_READ(DPLL_CTRL1); | |
6251 | ||
6252 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); | |
6253 | ||
e24ca054 CW |
6254 | if (intel_wait_for_register(dev_priv, |
6255 | LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, | |
6256 | 5)) | |
5d96d8af | 6257 | DRM_ERROR("DPLL0 not locked\n"); |
1cd593e0 | 6258 | |
63911d72 | 6259 | dev_priv->cdclk_pll.vco = vco; |
b2045352 VS |
6260 | |
6261 | /* We'll want to keep using the current vco from now on. */ | |
6262 | skl_set_preferred_cdclk_vco(dev_priv, vco); | |
5d96d8af DL |
6263 | } |
6264 | ||
430e05de VS |
6265 | static void |
6266 | skl_dpll0_disable(struct drm_i915_private *dev_priv) | |
6267 | { | |
6268 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); | |
8ad32a05 CW |
6269 | if (intel_wait_for_register(dev_priv, |
6270 | LCPLL1_CTL, LCPLL_PLL_LOCK, 0, | |
6271 | 1)) | |
430e05de | 6272 | DRM_ERROR("Couldn't disable DPLL0\n"); |
1cd593e0 | 6273 | |
63911d72 | 6274 | dev_priv->cdclk_pll.vco = 0; |
430e05de VS |
6275 | } |
6276 | ||
5d96d8af DL |
6277 | static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) |
6278 | { | |
6279 | int ret; | |
6280 | u32 val; | |
6281 | ||
6282 | /* inform PCU we want to change CDCLK */ | |
6283 | val = SKL_CDCLK_PREPARE_FOR_CHANGE; | |
6284 | mutex_lock(&dev_priv->rps.hw_lock); | |
6285 | ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); | |
6286 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6287 | ||
6288 | return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE); | |
6289 | } | |
6290 | ||
6291 | static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) | |
6292 | { | |
848496e5 | 6293 | return _wait_for(skl_cdclk_pcu_ready(dev_priv), 3000, 10) == 0; |
5d96d8af DL |
6294 | } |
6295 | ||
1cd593e0 | 6296 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco) |
5d96d8af | 6297 | { |
91c8a326 | 6298 | struct drm_device *dev = &dev_priv->drm; |
5d96d8af DL |
6299 | u32 freq_select, pcu_ack; |
6300 | ||
1cd593e0 VS |
6301 | WARN_ON((cdclk == 24000) != (vco == 0)); |
6302 | ||
63911d72 | 6303 | DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco); |
5d96d8af DL |
6304 | |
6305 | if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { | |
6306 | DRM_ERROR("failed to inform PCU about cdclk change\n"); | |
6307 | return; | |
6308 | } | |
6309 | ||
6310 | /* set CDCLK_CTL */ | |
9ef56154 | 6311 | switch (cdclk) { |
5d96d8af DL |
6312 | case 450000: |
6313 | case 432000: | |
6314 | freq_select = CDCLK_FREQ_450_432; | |
6315 | pcu_ack = 1; | |
6316 | break; | |
6317 | case 540000: | |
6318 | freq_select = CDCLK_FREQ_540; | |
6319 | pcu_ack = 2; | |
6320 | break; | |
487ed2e4 | 6321 | case 308571: |
5d96d8af DL |
6322 | case 337500: |
6323 | default: | |
6324 | freq_select = CDCLK_FREQ_337_308; | |
6325 | pcu_ack = 0; | |
6326 | break; | |
487ed2e4 | 6327 | case 617143: |
5d96d8af DL |
6328 | case 675000: |
6329 | freq_select = CDCLK_FREQ_675_617; | |
6330 | pcu_ack = 3; | |
6331 | break; | |
6332 | } | |
6333 | ||
63911d72 VS |
6334 | if (dev_priv->cdclk_pll.vco != 0 && |
6335 | dev_priv->cdclk_pll.vco != vco) | |
1cd593e0 VS |
6336 | skl_dpll0_disable(dev_priv); |
6337 | ||
63911d72 | 6338 | if (dev_priv->cdclk_pll.vco != vco) |
1cd593e0 VS |
6339 | skl_dpll0_enable(dev_priv, vco); |
6340 | ||
9ef56154 | 6341 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk)); |
5d96d8af DL |
6342 | POSTING_READ(CDCLK_CTL); |
6343 | ||
6344 | /* inform PCU of the change */ | |
6345 | mutex_lock(&dev_priv->rps.hw_lock); | |
6346 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); | |
6347 | mutex_unlock(&dev_priv->rps.hw_lock); | |
560a7ae4 DL |
6348 | |
6349 | intel_update_cdclk(dev); | |
5d96d8af DL |
6350 | } |
6351 | ||
9f7eb31a VS |
6352 | static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv); |
6353 | ||
5d96d8af DL |
6354 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) |
6355 | { | |
709e05c3 | 6356 | skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0); |
5d96d8af DL |
6357 | } |
6358 | ||
6359 | void skl_init_cdclk(struct drm_i915_private *dev_priv) | |
6360 | { | |
9f7eb31a VS |
6361 | int cdclk, vco; |
6362 | ||
6363 | skl_sanitize_cdclk(dev_priv); | |
5d96d8af | 6364 | |
63911d72 | 6365 | if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) { |
9f7eb31a VS |
6366 | /* |
6367 | * Use the current vco as our initial | |
6368 | * guess as to what the preferred vco is. | |
6369 | */ | |
6370 | if (dev_priv->skl_preferred_vco_freq == 0) | |
6371 | skl_set_preferred_cdclk_vco(dev_priv, | |
63911d72 | 6372 | dev_priv->cdclk_pll.vco); |
70c2c184 | 6373 | return; |
1cd593e0 | 6374 | } |
5d96d8af | 6375 | |
70c2c184 VS |
6376 | vco = dev_priv->skl_preferred_vco_freq; |
6377 | if (vco == 0) | |
63911d72 | 6378 | vco = 8100000; |
70c2c184 | 6379 | cdclk = skl_calc_cdclk(0, vco); |
5d96d8af | 6380 | |
70c2c184 | 6381 | skl_set_cdclk(dev_priv, cdclk, vco); |
5d96d8af DL |
6382 | } |
6383 | ||
9f7eb31a | 6384 | static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) |
c73666f3 | 6385 | { |
09492498 | 6386 | uint32_t cdctl, expected; |
c73666f3 | 6387 | |
f1b391a5 SK |
6388 | /* |
6389 | * check if the pre-os intialized the display | |
6390 | * There is SWF18 scratchpad register defined which is set by the | |
6391 | * pre-os which can be used by the OS drivers to check the status | |
6392 | */ | |
6393 | if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) | |
6394 | goto sanitize; | |
6395 | ||
91c8a326 | 6396 | intel_update_cdclk(&dev_priv->drm); |
c73666f3 | 6397 | /* Is PLL enabled and locked ? */ |
1c3f7700 ID |
6398 | if (dev_priv->cdclk_pll.vco == 0 || |
6399 | dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref) | |
c73666f3 SK |
6400 | goto sanitize; |
6401 | ||
6402 | /* DPLL okay; verify the cdclock | |
6403 | * | |
6404 | * Noticed in some instances that the freq selection is correct but | |
6405 | * decimal part is programmed wrong from BIOS where pre-os does not | |
6406 | * enable display. Verify the same as well. | |
6407 | */ | |
09492498 VS |
6408 | cdctl = I915_READ(CDCLK_CTL); |
6409 | expected = (cdctl & CDCLK_FREQ_SEL_MASK) | | |
6410 | skl_cdclk_decimal(dev_priv->cdclk_freq); | |
6411 | if (cdctl == expected) | |
c73666f3 | 6412 | /* All well; nothing to sanitize */ |
9f7eb31a | 6413 | return; |
c89e39f3 | 6414 | |
9f7eb31a VS |
6415 | sanitize: |
6416 | DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); | |
c73666f3 | 6417 | |
9f7eb31a VS |
6418 | /* force cdclk programming */ |
6419 | dev_priv->cdclk_freq = 0; | |
6420 | /* force full PLL disable + enable */ | |
63911d72 | 6421 | dev_priv->cdclk_pll.vco = -1; |
c73666f3 SK |
6422 | } |
6423 | ||
30a970c6 JB |
6424 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
6425 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
6426 | { | |
fac5e23e | 6427 | struct drm_i915_private *dev_priv = to_i915(dev); |
30a970c6 JB |
6428 | u32 val, cmd; |
6429 | ||
164dfd28 VK |
6430 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
6431 | != dev_priv->cdclk_freq); | |
d60c4473 | 6432 | |
dfcab17e | 6433 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 6434 | cmd = 2; |
dfcab17e | 6435 | else if (cdclk == 266667) |
30a970c6 JB |
6436 | cmd = 1; |
6437 | else | |
6438 | cmd = 0; | |
6439 | ||
6440 | mutex_lock(&dev_priv->rps.hw_lock); | |
6441 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
6442 | val &= ~DSPFREQGUAR_MASK; | |
6443 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
6444 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
6445 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
6446 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
6447 | 50)) { | |
6448 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
6449 | } | |
6450 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6451 | ||
54433e91 VS |
6452 | mutex_lock(&dev_priv->sb_lock); |
6453 | ||
dfcab17e | 6454 | if (cdclk == 400000) { |
6bcda4f0 | 6455 | u32 divider; |
30a970c6 | 6456 | |
6bcda4f0 | 6457 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 | 6458 | |
30a970c6 JB |
6459 | /* adjust cdclk divider */ |
6460 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
87d5d259 | 6461 | val &= ~CCK_FREQUENCY_VALUES; |
30a970c6 JB |
6462 | val |= divider; |
6463 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
6464 | |
6465 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
87d5d259 | 6466 | CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), |
a877e801 VS |
6467 | 50)) |
6468 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
6469 | } |
6470 | ||
30a970c6 JB |
6471 | /* adjust self-refresh exit latency value */ |
6472 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
6473 | val &= ~0x7f; | |
6474 | ||
6475 | /* | |
6476 | * For high bandwidth configs, we set a higher latency in the bunit | |
6477 | * so that the core display fetch happens in time to avoid underruns. | |
6478 | */ | |
dfcab17e | 6479 | if (cdclk == 400000) |
30a970c6 JB |
6480 | val |= 4500 / 250; /* 4.5 usec */ |
6481 | else | |
6482 | val |= 3000 / 250; /* 3.0 usec */ | |
6483 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
54433e91 | 6484 | |
a580516d | 6485 | mutex_unlock(&dev_priv->sb_lock); |
30a970c6 | 6486 | |
b6283055 | 6487 | intel_update_cdclk(dev); |
30a970c6 JB |
6488 | } |
6489 | ||
383c5a6a VS |
6490 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
6491 | { | |
fac5e23e | 6492 | struct drm_i915_private *dev_priv = to_i915(dev); |
383c5a6a VS |
6493 | u32 val, cmd; |
6494 | ||
164dfd28 VK |
6495 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
6496 | != dev_priv->cdclk_freq); | |
383c5a6a VS |
6497 | |
6498 | switch (cdclk) { | |
383c5a6a VS |
6499 | case 333333: |
6500 | case 320000: | |
383c5a6a | 6501 | case 266667: |
383c5a6a | 6502 | case 200000: |
383c5a6a VS |
6503 | break; |
6504 | default: | |
5f77eeb0 | 6505 | MISSING_CASE(cdclk); |
383c5a6a VS |
6506 | return; |
6507 | } | |
6508 | ||
9d0d3fda VS |
6509 | /* |
6510 | * Specs are full of misinformation, but testing on actual | |
6511 | * hardware has shown that we just need to write the desired | |
6512 | * CCK divider into the Punit register. | |
6513 | */ | |
6514 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
6515 | ||
383c5a6a VS |
6516 | mutex_lock(&dev_priv->rps.hw_lock); |
6517 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
6518 | val &= ~DSPFREQGUAR_MASK_CHV; | |
6519 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
6520 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
6521 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
6522 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
6523 | 50)) { | |
6524 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
6525 | } | |
6526 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6527 | ||
b6283055 | 6528 | intel_update_cdclk(dev); |
383c5a6a VS |
6529 | } |
6530 | ||
30a970c6 JB |
6531 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
6532 | int max_pixclk) | |
6533 | { | |
6bcda4f0 | 6534 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 6535 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 6536 | |
30a970c6 JB |
6537 | /* |
6538 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
6539 | * 200MHz | |
6540 | * 267MHz | |
29dc7ef3 | 6541 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
6542 | * 400MHz (VLV only) |
6543 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
6544 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
6545 | * |
6546 | * We seem to get an unstable or solid color picture at 200MHz. | |
6547 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
6548 | * are off. | |
30a970c6 | 6549 | */ |
6cca3195 VS |
6550 | if (!IS_CHERRYVIEW(dev_priv) && |
6551 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 6552 | return 400000; |
6cca3195 | 6553 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 6554 | return freq_320; |
e37c67a1 | 6555 | else if (max_pixclk > 0) |
dfcab17e | 6556 | return 266667; |
e37c67a1 VS |
6557 | else |
6558 | return 200000; | |
30a970c6 JB |
6559 | } |
6560 | ||
324513c0 | 6561 | static int bxt_calc_cdclk(int max_pixclk) |
f8437dd1 | 6562 | { |
760e1477 | 6563 | if (max_pixclk > 576000) |
f8437dd1 | 6564 | return 624000; |
760e1477 | 6565 | else if (max_pixclk > 384000) |
f8437dd1 | 6566 | return 576000; |
760e1477 | 6567 | else if (max_pixclk > 288000) |
f8437dd1 | 6568 | return 384000; |
760e1477 | 6569 | else if (max_pixclk > 144000) |
f8437dd1 VK |
6570 | return 288000; |
6571 | else | |
6572 | return 144000; | |
6573 | } | |
6574 | ||
e8788cbc | 6575 | /* Compute the max pixel clock for new configuration. */ |
a821fc46 ACO |
6576 | static int intel_mode_max_pixclk(struct drm_device *dev, |
6577 | struct drm_atomic_state *state) | |
30a970c6 | 6578 | { |
565602d7 | 6579 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 6580 | struct drm_i915_private *dev_priv = to_i915(dev); |
565602d7 ML |
6581 | struct drm_crtc *crtc; |
6582 | struct drm_crtc_state *crtc_state; | |
6583 | unsigned max_pixclk = 0, i; | |
6584 | enum pipe pipe; | |
30a970c6 | 6585 | |
565602d7 ML |
6586 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
6587 | sizeof(intel_state->min_pixclk)); | |
304603f4 | 6588 | |
565602d7 ML |
6589 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
6590 | int pixclk = 0; | |
6591 | ||
6592 | if (crtc_state->enable) | |
6593 | pixclk = crtc_state->adjusted_mode.crtc_clock; | |
304603f4 | 6594 | |
565602d7 | 6595 | intel_state->min_pixclk[i] = pixclk; |
30a970c6 JB |
6596 | } |
6597 | ||
565602d7 ML |
6598 | for_each_pipe(dev_priv, pipe) |
6599 | max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk); | |
6600 | ||
30a970c6 JB |
6601 | return max_pixclk; |
6602 | } | |
6603 | ||
27c329ed | 6604 | static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) |
30a970c6 | 6605 | { |
27c329ed | 6606 | struct drm_device *dev = state->dev; |
fac5e23e | 6607 | struct drm_i915_private *dev_priv = to_i915(dev); |
27c329ed | 6608 | int max_pixclk = intel_mode_max_pixclk(dev, state); |
1a617b77 ML |
6609 | struct intel_atomic_state *intel_state = |
6610 | to_intel_atomic_state(state); | |
30a970c6 | 6611 | |
1a617b77 | 6612 | intel_state->cdclk = intel_state->dev_cdclk = |
27c329ed | 6613 | valleyview_calc_cdclk(dev_priv, max_pixclk); |
0a9ab303 | 6614 | |
1a617b77 ML |
6615 | if (!intel_state->active_crtcs) |
6616 | intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0); | |
6617 | ||
27c329ed ML |
6618 | return 0; |
6619 | } | |
304603f4 | 6620 | |
324513c0 | 6621 | static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state) |
27c329ed | 6622 | { |
4e5ca60f | 6623 | int max_pixclk = ilk_max_pixel_rate(state); |
1a617b77 ML |
6624 | struct intel_atomic_state *intel_state = |
6625 | to_intel_atomic_state(state); | |
85a96e7a | 6626 | |
1a617b77 | 6627 | intel_state->cdclk = intel_state->dev_cdclk = |
324513c0 | 6628 | bxt_calc_cdclk(max_pixclk); |
85a96e7a | 6629 | |
1a617b77 | 6630 | if (!intel_state->active_crtcs) |
324513c0 | 6631 | intel_state->dev_cdclk = bxt_calc_cdclk(0); |
1a617b77 | 6632 | |
27c329ed | 6633 | return 0; |
30a970c6 JB |
6634 | } |
6635 | ||
1e69cd74 VS |
6636 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
6637 | { | |
6638 | unsigned int credits, default_credits; | |
6639 | ||
6640 | if (IS_CHERRYVIEW(dev_priv)) | |
6641 | default_credits = PFI_CREDIT(12); | |
6642 | else | |
6643 | default_credits = PFI_CREDIT(8); | |
6644 | ||
bfa7df01 | 6645 | if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) { |
1e69cd74 VS |
6646 | /* CHV suggested value is 31 or 63 */ |
6647 | if (IS_CHERRYVIEW(dev_priv)) | |
fcc0008f | 6648 | credits = PFI_CREDIT_63; |
1e69cd74 VS |
6649 | else |
6650 | credits = PFI_CREDIT(15); | |
6651 | } else { | |
6652 | credits = default_credits; | |
6653 | } | |
6654 | ||
6655 | /* | |
6656 | * WA - write default credits before re-programming | |
6657 | * FIXME: should we also set the resend bit here? | |
6658 | */ | |
6659 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6660 | default_credits); | |
6661 | ||
6662 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6663 | credits | PFI_CREDIT_RESEND); | |
6664 | ||
6665 | /* | |
6666 | * FIXME is this guaranteed to clear | |
6667 | * immediately or should we poll for it? | |
6668 | */ | |
6669 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
6670 | } | |
6671 | ||
27c329ed | 6672 | static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
30a970c6 | 6673 | { |
a821fc46 | 6674 | struct drm_device *dev = old_state->dev; |
fac5e23e | 6675 | struct drm_i915_private *dev_priv = to_i915(dev); |
1a617b77 ML |
6676 | struct intel_atomic_state *old_intel_state = |
6677 | to_intel_atomic_state(old_state); | |
6678 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
30a970c6 | 6679 | |
27c329ed ML |
6680 | /* |
6681 | * FIXME: We can end up here with all power domains off, yet | |
6682 | * with a CDCLK frequency other than the minimum. To account | |
6683 | * for this take the PIPE-A power domain, which covers the HW | |
6684 | * blocks needed for the following programming. This can be | |
6685 | * removed once it's guaranteed that we get here either with | |
6686 | * the minimum CDCLK set, or the required power domains | |
6687 | * enabled. | |
6688 | */ | |
6689 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
738c05c0 | 6690 | |
920a14b2 | 6691 | if (IS_CHERRYVIEW(dev_priv)) |
27c329ed ML |
6692 | cherryview_set_cdclk(dev, req_cdclk); |
6693 | else | |
6694 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 6695 | |
27c329ed | 6696 | vlv_program_pfi_credits(dev_priv); |
1e69cd74 | 6697 | |
27c329ed | 6698 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
30a970c6 JB |
6699 | } |
6700 | ||
4a806558 ML |
6701 | static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config, |
6702 | struct drm_atomic_state *old_state) | |
89b667f8 | 6703 | { |
4a806558 | 6704 | struct drm_crtc *crtc = pipe_config->base.crtc; |
89b667f8 | 6705 | struct drm_device *dev = crtc->dev; |
a72e4c9f | 6706 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 | 6707 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
89b667f8 | 6708 | int pipe = intel_crtc->pipe; |
89b667f8 | 6709 | |
53d9f4e9 | 6710 | if (WARN_ON(intel_crtc->active)) |
89b667f8 JB |
6711 | return; |
6712 | ||
37a5650b | 6713 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 6714 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6715 | |
6716 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 6717 | intel_set_pipe_src_size(intel_crtc); |
5b18e57c | 6718 | |
920a14b2 | 6719 | if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { |
fac5e23e | 6720 | struct drm_i915_private *dev_priv = to_i915(dev); |
c14b0485 VS |
6721 | |
6722 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
6723 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
6724 | } | |
6725 | ||
5b18e57c DV |
6726 | i9xx_set_pipeconf(intel_crtc); |
6727 | ||
89b667f8 | 6728 | intel_crtc->active = true; |
89b667f8 | 6729 | |
a72e4c9f | 6730 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6731 | |
fd6bbda9 | 6732 | intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); |
89b667f8 | 6733 | |
920a14b2 | 6734 | if (IS_CHERRYVIEW(dev_priv)) { |
cd2d34d9 VS |
6735 | chv_prepare_pll(intel_crtc, intel_crtc->config); |
6736 | chv_enable_pll(intel_crtc, intel_crtc->config); | |
6737 | } else { | |
6738 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
6739 | vlv_enable_pll(intel_crtc, intel_crtc->config); | |
9d556c99 | 6740 | } |
89b667f8 | 6741 | |
fd6bbda9 | 6742 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
89b667f8 | 6743 | |
2dd24552 JB |
6744 | i9xx_pfit_enable(intel_crtc); |
6745 | ||
b95c5321 | 6746 | intel_color_load_luts(&pipe_config->base); |
63cbb074 | 6747 | |
caed361d | 6748 | intel_update_watermarks(crtc); |
e1fdc473 | 6749 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6750 | |
4b3a9526 VS |
6751 | assert_vblank_disabled(crtc); |
6752 | drm_crtc_vblank_on(crtc); | |
6753 | ||
fd6bbda9 | 6754 | intel_encoders_enable(crtc, pipe_config, old_state); |
89b667f8 JB |
6755 | } |
6756 | ||
f13c2ef3 DV |
6757 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
6758 | { | |
6759 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6760 | struct drm_i915_private *dev_priv = to_i915(dev); |
f13c2ef3 | 6761 | |
6e3c9717 ACO |
6762 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
6763 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
6764 | } |
6765 | ||
4a806558 ML |
6766 | static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config, |
6767 | struct drm_atomic_state *old_state) | |
79e53945 | 6768 | { |
4a806558 | 6769 | struct drm_crtc *crtc = pipe_config->base.crtc; |
79e53945 | 6770 | struct drm_device *dev = crtc->dev; |
a72e4c9f | 6771 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 6772 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cd2d34d9 | 6773 | enum pipe pipe = intel_crtc->pipe; |
79e53945 | 6774 | |
53d9f4e9 | 6775 | if (WARN_ON(intel_crtc->active)) |
f7abfe8b CW |
6776 | return; |
6777 | ||
f13c2ef3 DV |
6778 | i9xx_set_pll_dividers(intel_crtc); |
6779 | ||
37a5650b | 6780 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 6781 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6782 | |
6783 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 6784 | intel_set_pipe_src_size(intel_crtc); |
5b18e57c | 6785 | |
5b18e57c DV |
6786 | i9xx_set_pipeconf(intel_crtc); |
6787 | ||
f7abfe8b | 6788 | intel_crtc->active = true; |
6b383a7f | 6789 | |
5db94019 | 6790 | if (!IS_GEN2(dev_priv)) |
a72e4c9f | 6791 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6792 | |
fd6bbda9 | 6793 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
9d6d9f19 | 6794 | |
f6736a1a DV |
6795 | i9xx_enable_pll(intel_crtc); |
6796 | ||
2dd24552 JB |
6797 | i9xx_pfit_enable(intel_crtc); |
6798 | ||
b95c5321 | 6799 | intel_color_load_luts(&pipe_config->base); |
63cbb074 | 6800 | |
f37fcc2a | 6801 | intel_update_watermarks(crtc); |
e1fdc473 | 6802 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6803 | |
4b3a9526 VS |
6804 | assert_vblank_disabled(crtc); |
6805 | drm_crtc_vblank_on(crtc); | |
6806 | ||
fd6bbda9 | 6807 | intel_encoders_enable(crtc, pipe_config, old_state); |
0b8765c6 | 6808 | } |
79e53945 | 6809 | |
87476d63 DV |
6810 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
6811 | { | |
6812 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6813 | struct drm_i915_private *dev_priv = to_i915(dev); |
87476d63 | 6814 | |
6e3c9717 | 6815 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 6816 | return; |
87476d63 | 6817 | |
328d8e82 | 6818 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 6819 | |
328d8e82 DV |
6820 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
6821 | I915_READ(PFIT_CONTROL)); | |
6822 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
6823 | } |
6824 | ||
4a806558 ML |
6825 | static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state, |
6826 | struct drm_atomic_state *old_state) | |
0b8765c6 | 6827 | { |
4a806558 | 6828 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
0b8765c6 | 6829 | struct drm_device *dev = crtc->dev; |
fac5e23e | 6830 | struct drm_i915_private *dev_priv = to_i915(dev); |
0b8765c6 JB |
6831 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6832 | int pipe = intel_crtc->pipe; | |
ef9c3aee | 6833 | |
6304cd91 VS |
6834 | /* |
6835 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
6836 | * wait for planes to fully turn off before disabling the pipe. | |
6837 | */ | |
5db94019 | 6838 | if (IS_GEN2(dev_priv)) |
90e83e53 | 6839 | intel_wait_for_vblank(dev, pipe); |
6304cd91 | 6840 | |
fd6bbda9 | 6841 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
4b3a9526 | 6842 | |
f9b61ff6 DV |
6843 | drm_crtc_vblank_off(crtc); |
6844 | assert_vblank_disabled(crtc); | |
6845 | ||
575f7ab7 | 6846 | intel_disable_pipe(intel_crtc); |
24a1f16d | 6847 | |
87476d63 | 6848 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 6849 | |
fd6bbda9 | 6850 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
89b667f8 | 6851 | |
d7edc4e5 | 6852 | if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) { |
920a14b2 | 6853 | if (IS_CHERRYVIEW(dev_priv)) |
076ed3b2 | 6854 | chv_disable_pll(dev_priv, pipe); |
11a914c2 | 6855 | else if (IS_VALLEYVIEW(dev_priv)) |
076ed3b2 CML |
6856 | vlv_disable_pll(dev_priv, pipe); |
6857 | else | |
1c4e0274 | 6858 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 6859 | } |
0b8765c6 | 6860 | |
fd6bbda9 | 6861 | intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state); |
d6db995f | 6862 | |
5db94019 | 6863 | if (!IS_GEN2(dev_priv)) |
a72e4c9f | 6864 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
0b8765c6 JB |
6865 | } |
6866 | ||
b17d48e2 ML |
6867 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
6868 | { | |
842e0307 | 6869 | struct intel_encoder *encoder; |
b17d48e2 ML |
6870 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6871 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
6872 | enum intel_display_power_domain domain; | |
6873 | unsigned long domains; | |
4a806558 ML |
6874 | struct drm_atomic_state *state; |
6875 | struct intel_crtc_state *crtc_state; | |
6876 | int ret; | |
b17d48e2 ML |
6877 | |
6878 | if (!intel_crtc->active) | |
6879 | return; | |
6880 | ||
936e71e3 | 6881 | if (to_intel_plane_state(crtc->primary->state)->base.visible) { |
5a21b665 | 6882 | WARN_ON(intel_crtc->flip_work); |
fc32b1fd | 6883 | |
2622a081 | 6884 | intel_pre_disable_primary_noatomic(crtc); |
54a41961 ML |
6885 | |
6886 | intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); | |
936e71e3 | 6887 | to_intel_plane_state(crtc->primary->state)->base.visible = false; |
a539205a ML |
6888 | } |
6889 | ||
4a806558 ML |
6890 | state = drm_atomic_state_alloc(crtc->dev); |
6891 | state->acquire_ctx = crtc->dev->mode_config.acquire_ctx; | |
6892 | ||
6893 | /* Everything's already locked, -EDEADLK can't happen. */ | |
6894 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); | |
6895 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
6896 | ||
6897 | WARN_ON(IS_ERR(crtc_state) || ret); | |
6898 | ||
6899 | dev_priv->display.crtc_disable(crtc_state, state); | |
6900 | ||
0853695c | 6901 | drm_atomic_state_put(state); |
842e0307 | 6902 | |
78108b7c VS |
6903 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", |
6904 | crtc->base.id, crtc->name); | |
842e0307 ML |
6905 | |
6906 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0); | |
6907 | crtc->state->active = false; | |
37d9078b | 6908 | intel_crtc->active = false; |
842e0307 ML |
6909 | crtc->enabled = false; |
6910 | crtc->state->connector_mask = 0; | |
6911 | crtc->state->encoder_mask = 0; | |
6912 | ||
6913 | for_each_encoder_on_crtc(crtc->dev, crtc, encoder) | |
6914 | encoder->base.crtc = NULL; | |
6915 | ||
58f9c0bc | 6916 | intel_fbc_disable(intel_crtc); |
37d9078b | 6917 | intel_update_watermarks(crtc); |
1f7457b1 | 6918 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
6919 | |
6920 | domains = intel_crtc->enabled_power_domains; | |
6921 | for_each_power_domain(domain, domains) | |
6922 | intel_display_power_put(dev_priv, domain); | |
6923 | intel_crtc->enabled_power_domains = 0; | |
565602d7 ML |
6924 | |
6925 | dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); | |
6926 | dev_priv->min_pixclk[intel_crtc->pipe] = 0; | |
b17d48e2 ML |
6927 | } |
6928 | ||
6b72d486 ML |
6929 | /* |
6930 | * turn all crtc's off, but do not adjust state | |
6931 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
6932 | */ | |
70e0bd74 | 6933 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 6934 | { |
e2c8b870 | 6935 | struct drm_i915_private *dev_priv = to_i915(dev); |
70e0bd74 | 6936 | struct drm_atomic_state *state; |
e2c8b870 | 6937 | int ret; |
70e0bd74 | 6938 | |
e2c8b870 ML |
6939 | state = drm_atomic_helper_suspend(dev); |
6940 | ret = PTR_ERR_OR_ZERO(state); | |
70e0bd74 ML |
6941 | if (ret) |
6942 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
e2c8b870 ML |
6943 | else |
6944 | dev_priv->modeset_restore_state = state; | |
70e0bd74 | 6945 | return ret; |
ee7b9f93 JB |
6946 | } |
6947 | ||
ea5b213a | 6948 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6949 | { |
4ef69c7a | 6950 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6951 | |
ea5b213a CW |
6952 | drm_encoder_cleanup(encoder); |
6953 | kfree(intel_encoder); | |
7e7d76c3 JB |
6954 | } |
6955 | ||
0a91ca29 DV |
6956 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6957 | * internal consistency). */ | |
5a21b665 | 6958 | static void intel_connector_verify_state(struct intel_connector *connector) |
79e53945 | 6959 | { |
5a21b665 | 6960 | struct drm_crtc *crtc = connector->base.state->crtc; |
35dd3c64 ML |
6961 | |
6962 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6963 | connector->base.base.id, | |
6964 | connector->base.name); | |
6965 | ||
0a91ca29 | 6966 | if (connector->get_hw_state(connector)) { |
e85376cb | 6967 | struct intel_encoder *encoder = connector->encoder; |
5a21b665 | 6968 | struct drm_connector_state *conn_state = connector->base.state; |
0a91ca29 | 6969 | |
35dd3c64 ML |
6970 | I915_STATE_WARN(!crtc, |
6971 | "connector enabled without attached crtc\n"); | |
0a91ca29 | 6972 | |
35dd3c64 ML |
6973 | if (!crtc) |
6974 | return; | |
6975 | ||
6976 | I915_STATE_WARN(!crtc->state->active, | |
6977 | "connector is active, but attached crtc isn't\n"); | |
6978 | ||
e85376cb | 6979 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
6980 | return; |
6981 | ||
e85376cb | 6982 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
6983 | "atomic encoder doesn't match attached encoder\n"); |
6984 | ||
e85376cb | 6985 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
6986 | "attached encoder crtc differs from connector crtc\n"); |
6987 | } else { | |
4d688a2a ML |
6988 | I915_STATE_WARN(crtc && crtc->state->active, |
6989 | "attached crtc is active, but connector isn't\n"); | |
5a21b665 | 6990 | I915_STATE_WARN(!crtc && connector->base.state->best_encoder, |
35dd3c64 | 6991 | "best encoder set without crtc!\n"); |
0a91ca29 | 6992 | } |
79e53945 JB |
6993 | } |
6994 | ||
08d9bc92 ACO |
6995 | int intel_connector_init(struct intel_connector *connector) |
6996 | { | |
5350a031 | 6997 | drm_atomic_helper_connector_reset(&connector->base); |
08d9bc92 | 6998 | |
5350a031 | 6999 | if (!connector->base.state) |
08d9bc92 ACO |
7000 | return -ENOMEM; |
7001 | ||
08d9bc92 ACO |
7002 | return 0; |
7003 | } | |
7004 | ||
7005 | struct intel_connector *intel_connector_alloc(void) | |
7006 | { | |
7007 | struct intel_connector *connector; | |
7008 | ||
7009 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
7010 | if (!connector) | |
7011 | return NULL; | |
7012 | ||
7013 | if (intel_connector_init(connector) < 0) { | |
7014 | kfree(connector); | |
7015 | return NULL; | |
7016 | } | |
7017 | ||
7018 | return connector; | |
7019 | } | |
7020 | ||
f0947c37 DV |
7021 | /* Simple connector->get_hw_state implementation for encoders that support only |
7022 | * one connector and no cloning and hence the encoder state determines the state | |
7023 | * of the connector. */ | |
7024 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 7025 | { |
24929352 | 7026 | enum pipe pipe = 0; |
f0947c37 | 7027 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 7028 | |
f0947c37 | 7029 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
7030 | } |
7031 | ||
6d293983 | 7032 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 7033 | { |
6d293983 ACO |
7034 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
7035 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
7036 | |
7037 | return 0; | |
7038 | } | |
7039 | ||
6d293983 | 7040 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 7041 | struct intel_crtc_state *pipe_config) |
1857e1da | 7042 | { |
8652744b | 7043 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d293983 ACO |
7044 | struct drm_atomic_state *state = pipe_config->base.state; |
7045 | struct intel_crtc *other_crtc; | |
7046 | struct intel_crtc_state *other_crtc_state; | |
7047 | ||
1857e1da DV |
7048 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
7049 | pipe_name(pipe), pipe_config->fdi_lanes); | |
7050 | if (pipe_config->fdi_lanes > 4) { | |
7051 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
7052 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 7053 | return -EINVAL; |
1857e1da DV |
7054 | } |
7055 | ||
8652744b | 7056 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
1857e1da DV |
7057 | if (pipe_config->fdi_lanes > 2) { |
7058 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
7059 | pipe_config->fdi_lanes); | |
6d293983 | 7060 | return -EINVAL; |
1857e1da | 7061 | } else { |
6d293983 | 7062 | return 0; |
1857e1da DV |
7063 | } |
7064 | } | |
7065 | ||
7066 | if (INTEL_INFO(dev)->num_pipes == 2) | |
6d293983 | 7067 | return 0; |
1857e1da DV |
7068 | |
7069 | /* Ivybridge 3 pipe is really complicated */ | |
7070 | switch (pipe) { | |
7071 | case PIPE_A: | |
6d293983 | 7072 | return 0; |
1857e1da | 7073 | case PIPE_B: |
6d293983 ACO |
7074 | if (pipe_config->fdi_lanes <= 2) |
7075 | return 0; | |
7076 | ||
7077 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); | |
7078 | other_crtc_state = | |
7079 | intel_atomic_get_crtc_state(state, other_crtc); | |
7080 | if (IS_ERR(other_crtc_state)) | |
7081 | return PTR_ERR(other_crtc_state); | |
7082 | ||
7083 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
7084 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
7085 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 7086 | return -EINVAL; |
1857e1da | 7087 | } |
6d293983 | 7088 | return 0; |
1857e1da | 7089 | case PIPE_C: |
251cc67c VS |
7090 | if (pipe_config->fdi_lanes > 2) { |
7091 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
7092 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 7093 | return -EINVAL; |
251cc67c | 7094 | } |
6d293983 ACO |
7095 | |
7096 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); | |
7097 | other_crtc_state = | |
7098 | intel_atomic_get_crtc_state(state, other_crtc); | |
7099 | if (IS_ERR(other_crtc_state)) | |
7100 | return PTR_ERR(other_crtc_state); | |
7101 | ||
7102 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 7103 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 7104 | return -EINVAL; |
1857e1da | 7105 | } |
6d293983 | 7106 | return 0; |
1857e1da DV |
7107 | default: |
7108 | BUG(); | |
7109 | } | |
7110 | } | |
7111 | ||
e29c22c0 DV |
7112 | #define RETRY 1 |
7113 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 7114 | struct intel_crtc_state *pipe_config) |
877d48d5 | 7115 | { |
1857e1da | 7116 | struct drm_device *dev = intel_crtc->base.dev; |
7c5f93b0 | 7117 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
7118 | int lane, link_bw, fdi_dotclock, ret; |
7119 | bool needs_recompute = false; | |
877d48d5 | 7120 | |
e29c22c0 | 7121 | retry: |
877d48d5 DV |
7122 | /* FDI is a binary signal running at ~2.7GHz, encoding |
7123 | * each output octet as 10 bits. The actual frequency | |
7124 | * is stored as a divider into a 100MHz clock, and the | |
7125 | * mode pixel clock is stored in units of 1KHz. | |
7126 | * Hence the bw of each lane in terms of the mode signal | |
7127 | * is: | |
7128 | */ | |
21a727b3 | 7129 | link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config); |
877d48d5 | 7130 | |
241bfc38 | 7131 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 7132 | |
2bd89a07 | 7133 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
7134 | pipe_config->pipe_bpp); |
7135 | ||
7136 | pipe_config->fdi_lanes = lane; | |
7137 | ||
2bd89a07 | 7138 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 7139 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 7140 | |
e3b247da | 7141 | ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); |
6d293983 | 7142 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { |
e29c22c0 DV |
7143 | pipe_config->pipe_bpp -= 2*3; |
7144 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
7145 | pipe_config->pipe_bpp); | |
7146 | needs_recompute = true; | |
7147 | pipe_config->bw_constrained = true; | |
7148 | ||
7149 | goto retry; | |
7150 | } | |
7151 | ||
7152 | if (needs_recompute) | |
7153 | return RETRY; | |
7154 | ||
6d293983 | 7155 | return ret; |
877d48d5 DV |
7156 | } |
7157 | ||
8cfb3407 VS |
7158 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
7159 | struct intel_crtc_state *pipe_config) | |
7160 | { | |
7161 | if (pipe_config->pipe_bpp > 24) | |
7162 | return false; | |
7163 | ||
7164 | /* HSW can handle pixel rate up to cdclk? */ | |
2d1fe073 | 7165 | if (IS_HASWELL(dev_priv)) |
8cfb3407 VS |
7166 | return true; |
7167 | ||
7168 | /* | |
b432e5cf VS |
7169 | * We compare against max which means we must take |
7170 | * the increased cdclk requirement into account when | |
7171 | * calculating the new cdclk. | |
7172 | * | |
7173 | * Should measure whether using a lower cdclk w/o IPS | |
8cfb3407 VS |
7174 | */ |
7175 | return ilk_pipe_pixel_rate(pipe_config) <= | |
7176 | dev_priv->max_cdclk_freq * 95 / 100; | |
7177 | } | |
7178 | ||
42db64ef | 7179 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 7180 | struct intel_crtc_state *pipe_config) |
42db64ef | 7181 | { |
8cfb3407 | 7182 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7183 | struct drm_i915_private *dev_priv = to_i915(dev); |
8cfb3407 | 7184 | |
d330a953 | 7185 | pipe_config->ips_enabled = i915.enable_ips && |
8cfb3407 VS |
7186 | hsw_crtc_supports_ips(crtc) && |
7187 | pipe_config_supports_ips(dev_priv, pipe_config); | |
42db64ef PZ |
7188 | } |
7189 | ||
39acb4aa VS |
7190 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
7191 | { | |
7192 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
7193 | ||
7194 | /* GDG double wide on either pipe, otherwise pipe A only */ | |
7195 | return INTEL_INFO(dev_priv)->gen < 4 && | |
7196 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); | |
7197 | } | |
7198 | ||
a43f6e0f | 7199 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 7200 | struct intel_crtc_state *pipe_config) |
79e53945 | 7201 | { |
a43f6e0f | 7202 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7203 | struct drm_i915_private *dev_priv = to_i915(dev); |
7c5f93b0 | 7204 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
f3261156 | 7205 | int clock_limit = dev_priv->max_dotclk_freq; |
89749350 | 7206 | |
cf532bb2 | 7207 | if (INTEL_INFO(dev)->gen < 4) { |
f3261156 | 7208 | clock_limit = dev_priv->max_cdclk_freq * 9 / 10; |
cf532bb2 VS |
7209 | |
7210 | /* | |
39acb4aa | 7211 | * Enable double wide mode when the dot clock |
cf532bb2 | 7212 | * is > 90% of the (display) core speed. |
cf532bb2 | 7213 | */ |
39acb4aa VS |
7214 | if (intel_crtc_supports_double_wide(crtc) && |
7215 | adjusted_mode->crtc_clock > clock_limit) { | |
f3261156 | 7216 | clock_limit = dev_priv->max_dotclk_freq; |
cf532bb2 | 7217 | pipe_config->double_wide = true; |
ad3a4479 | 7218 | } |
f3261156 | 7219 | } |
ad3a4479 | 7220 | |
f3261156 VS |
7221 | if (adjusted_mode->crtc_clock > clock_limit) { |
7222 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
7223 | adjusted_mode->crtc_clock, clock_limit, | |
7224 | yesno(pipe_config->double_wide)); | |
7225 | return -EINVAL; | |
2c07245f | 7226 | } |
89749350 | 7227 | |
1d1d0e27 VS |
7228 | /* |
7229 | * Pipe horizontal size must be even in: | |
7230 | * - DVO ganged mode | |
7231 | * - LVDS dual channel mode | |
7232 | * - Double wide pipe | |
7233 | */ | |
2d84d2b3 | 7234 | if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
7235 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
7236 | pipe_config->pipe_src_w &= ~1; | |
7237 | ||
8693a824 DL |
7238 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
7239 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 | 7240 | */ |
9beb5fea | 7241 | if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) && |
aad941d5 | 7242 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) |
e29c22c0 | 7243 | return -EINVAL; |
44f46b42 | 7244 | |
50a0bc90 | 7245 | if (HAS_IPS(dev_priv)) |
a43f6e0f DV |
7246 | hsw_compute_ips_config(crtc, pipe_config); |
7247 | ||
877d48d5 | 7248 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 7249 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 7250 | |
cf5a15be | 7251 | return 0; |
79e53945 JB |
7252 | } |
7253 | ||
1652d19e VS |
7254 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
7255 | { | |
7256 | struct drm_i915_private *dev_priv = to_i915(dev); | |
ea61791e | 7257 | uint32_t cdctl; |
1652d19e | 7258 | |
ea61791e | 7259 | skl_dpll0_update(dev_priv); |
1652d19e | 7260 | |
63911d72 | 7261 | if (dev_priv->cdclk_pll.vco == 0) |
709e05c3 | 7262 | return dev_priv->cdclk_pll.ref; |
1652d19e | 7263 | |
ea61791e | 7264 | cdctl = I915_READ(CDCLK_CTL); |
1652d19e | 7265 | |
63911d72 | 7266 | if (dev_priv->cdclk_pll.vco == 8640000) { |
1652d19e VS |
7267 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { |
7268 | case CDCLK_FREQ_450_432: | |
7269 | return 432000; | |
7270 | case CDCLK_FREQ_337_308: | |
487ed2e4 | 7271 | return 308571; |
ea61791e VS |
7272 | case CDCLK_FREQ_540: |
7273 | return 540000; | |
1652d19e | 7274 | case CDCLK_FREQ_675_617: |
487ed2e4 | 7275 | return 617143; |
1652d19e | 7276 | default: |
ea61791e | 7277 | MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); |
1652d19e VS |
7278 | } |
7279 | } else { | |
1652d19e VS |
7280 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { |
7281 | case CDCLK_FREQ_450_432: | |
7282 | return 450000; | |
7283 | case CDCLK_FREQ_337_308: | |
7284 | return 337500; | |
ea61791e VS |
7285 | case CDCLK_FREQ_540: |
7286 | return 540000; | |
1652d19e VS |
7287 | case CDCLK_FREQ_675_617: |
7288 | return 675000; | |
7289 | default: | |
ea61791e | 7290 | MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); |
1652d19e VS |
7291 | } |
7292 | } | |
7293 | ||
709e05c3 | 7294 | return dev_priv->cdclk_pll.ref; |
1652d19e VS |
7295 | } |
7296 | ||
83d7c81f VS |
7297 | static void bxt_de_pll_update(struct drm_i915_private *dev_priv) |
7298 | { | |
7299 | u32 val; | |
7300 | ||
7301 | dev_priv->cdclk_pll.ref = 19200; | |
1c3f7700 | 7302 | dev_priv->cdclk_pll.vco = 0; |
83d7c81f VS |
7303 | |
7304 | val = I915_READ(BXT_DE_PLL_ENABLE); | |
1c3f7700 | 7305 | if ((val & BXT_DE_PLL_PLL_ENABLE) == 0) |
83d7c81f | 7306 | return; |
83d7c81f | 7307 | |
1c3f7700 ID |
7308 | if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0)) |
7309 | return; | |
83d7c81f VS |
7310 | |
7311 | val = I915_READ(BXT_DE_PLL_CTL); | |
7312 | dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) * | |
7313 | dev_priv->cdclk_pll.ref; | |
7314 | } | |
7315 | ||
acd3f3d3 BP |
7316 | static int broxton_get_display_clock_speed(struct drm_device *dev) |
7317 | { | |
7318 | struct drm_i915_private *dev_priv = to_i915(dev); | |
f5986242 VS |
7319 | u32 divider; |
7320 | int div, vco; | |
acd3f3d3 | 7321 | |
83d7c81f VS |
7322 | bxt_de_pll_update(dev_priv); |
7323 | ||
f5986242 VS |
7324 | vco = dev_priv->cdclk_pll.vco; |
7325 | if (vco == 0) | |
7326 | return dev_priv->cdclk_pll.ref; | |
acd3f3d3 | 7327 | |
f5986242 | 7328 | divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; |
acd3f3d3 | 7329 | |
f5986242 | 7330 | switch (divider) { |
acd3f3d3 | 7331 | case BXT_CDCLK_CD2X_DIV_SEL_1: |
f5986242 VS |
7332 | div = 2; |
7333 | break; | |
acd3f3d3 | 7334 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: |
f5986242 VS |
7335 | div = 3; |
7336 | break; | |
acd3f3d3 | 7337 | case BXT_CDCLK_CD2X_DIV_SEL_2: |
f5986242 VS |
7338 | div = 4; |
7339 | break; | |
acd3f3d3 | 7340 | case BXT_CDCLK_CD2X_DIV_SEL_4: |
f5986242 VS |
7341 | div = 8; |
7342 | break; | |
7343 | default: | |
7344 | MISSING_CASE(divider); | |
7345 | return dev_priv->cdclk_pll.ref; | |
acd3f3d3 BP |
7346 | } |
7347 | ||
f5986242 | 7348 | return DIV_ROUND_CLOSEST(vco, div); |
acd3f3d3 BP |
7349 | } |
7350 | ||
1652d19e VS |
7351 | static int broadwell_get_display_clock_speed(struct drm_device *dev) |
7352 | { | |
fac5e23e | 7353 | struct drm_i915_private *dev_priv = to_i915(dev); |
1652d19e VS |
7354 | uint32_t lcpll = I915_READ(LCPLL_CTL); |
7355 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
7356 | ||
7357 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
7358 | return 800000; | |
7359 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
7360 | return 450000; | |
7361 | else if (freq == LCPLL_CLK_FREQ_450) | |
7362 | return 450000; | |
7363 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
7364 | return 540000; | |
7365 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
7366 | return 337500; | |
7367 | else | |
7368 | return 675000; | |
7369 | } | |
7370 | ||
7371 | static int haswell_get_display_clock_speed(struct drm_device *dev) | |
7372 | { | |
fac5e23e | 7373 | struct drm_i915_private *dev_priv = to_i915(dev); |
1652d19e VS |
7374 | uint32_t lcpll = I915_READ(LCPLL_CTL); |
7375 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
7376 | ||
7377 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
7378 | return 800000; | |
7379 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
7380 | return 450000; | |
7381 | else if (freq == LCPLL_CLK_FREQ_450) | |
7382 | return 450000; | |
50a0bc90 | 7383 | else if (IS_HSW_ULT(dev_priv)) |
1652d19e VS |
7384 | return 337500; |
7385 | else | |
7386 | return 540000; | |
79e53945 JB |
7387 | } |
7388 | ||
25eb05fc JB |
7389 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
7390 | { | |
bfa7df01 VS |
7391 | return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk", |
7392 | CCK_DISPLAY_CLOCK_CONTROL); | |
25eb05fc JB |
7393 | } |
7394 | ||
b37a6434 VS |
7395 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
7396 | { | |
7397 | return 450000; | |
7398 | } | |
7399 | ||
e70236a8 JB |
7400 | static int i945_get_display_clock_speed(struct drm_device *dev) |
7401 | { | |
7402 | return 400000; | |
7403 | } | |
79e53945 | 7404 | |
e70236a8 | 7405 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 7406 | { |
e907f170 | 7407 | return 333333; |
e70236a8 | 7408 | } |
79e53945 | 7409 | |
e70236a8 JB |
7410 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
7411 | { | |
7412 | return 200000; | |
7413 | } | |
79e53945 | 7414 | |
257a7ffc DV |
7415 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
7416 | { | |
52a05c30 | 7417 | struct pci_dev *pdev = dev->pdev; |
257a7ffc DV |
7418 | u16 gcfgc = 0; |
7419 | ||
52a05c30 | 7420 | pci_read_config_word(pdev, GCFGC, &gcfgc); |
257a7ffc DV |
7421 | |
7422 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
7423 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 7424 | return 266667; |
257a7ffc | 7425 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 7426 | return 333333; |
257a7ffc | 7427 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 7428 | return 444444; |
257a7ffc DV |
7429 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
7430 | return 200000; | |
7431 | default: | |
7432 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
7433 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 7434 | return 133333; |
257a7ffc | 7435 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 7436 | return 166667; |
257a7ffc DV |
7437 | } |
7438 | } | |
7439 | ||
e70236a8 JB |
7440 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
7441 | { | |
52a05c30 | 7442 | struct pci_dev *pdev = dev->pdev; |
e70236a8 | 7443 | u16 gcfgc = 0; |
79e53945 | 7444 | |
52a05c30 | 7445 | pci_read_config_word(pdev, GCFGC, &gcfgc); |
e70236a8 JB |
7446 | |
7447 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 7448 | return 133333; |
e70236a8 JB |
7449 | else { |
7450 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
7451 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 7452 | return 333333; |
e70236a8 JB |
7453 | default: |
7454 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
7455 | return 190000; | |
79e53945 | 7456 | } |
e70236a8 JB |
7457 | } |
7458 | } | |
7459 | ||
7460 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
7461 | { | |
e907f170 | 7462 | return 266667; |
e70236a8 JB |
7463 | } |
7464 | ||
1b1d2716 | 7465 | static int i85x_get_display_clock_speed(struct drm_device *dev) |
e70236a8 | 7466 | { |
52a05c30 | 7467 | struct pci_dev *pdev = dev->pdev; |
e70236a8 | 7468 | u16 hpllcc = 0; |
1b1d2716 | 7469 | |
65cd2b3f VS |
7470 | /* |
7471 | * 852GM/852GMV only supports 133 MHz and the HPLLCC | |
7472 | * encoding is different :( | |
7473 | * FIXME is this the right way to detect 852GM/852GMV? | |
7474 | */ | |
52a05c30 | 7475 | if (pdev->revision == 0x1) |
65cd2b3f VS |
7476 | return 133333; |
7477 | ||
52a05c30 | 7478 | pci_bus_read_config_word(pdev->bus, |
1b1d2716 VS |
7479 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); |
7480 | ||
e70236a8 JB |
7481 | /* Assume that the hardware is in the high speed state. This |
7482 | * should be the default. | |
7483 | */ | |
7484 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
7485 | case GC_CLOCK_133_200: | |
1b1d2716 | 7486 | case GC_CLOCK_133_200_2: |
e70236a8 JB |
7487 | case GC_CLOCK_100_200: |
7488 | return 200000; | |
7489 | case GC_CLOCK_166_250: | |
7490 | return 250000; | |
7491 | case GC_CLOCK_100_133: | |
e907f170 | 7492 | return 133333; |
1b1d2716 VS |
7493 | case GC_CLOCK_133_266: |
7494 | case GC_CLOCK_133_266_2: | |
7495 | case GC_CLOCK_166_266: | |
7496 | return 266667; | |
e70236a8 | 7497 | } |
79e53945 | 7498 | |
e70236a8 JB |
7499 | /* Shouldn't happen */ |
7500 | return 0; | |
7501 | } | |
79e53945 | 7502 | |
e70236a8 JB |
7503 | static int i830_get_display_clock_speed(struct drm_device *dev) |
7504 | { | |
e907f170 | 7505 | return 133333; |
79e53945 JB |
7506 | } |
7507 | ||
34edce2f VS |
7508 | static unsigned int intel_hpll_vco(struct drm_device *dev) |
7509 | { | |
fac5e23e | 7510 | struct drm_i915_private *dev_priv = to_i915(dev); |
34edce2f VS |
7511 | static const unsigned int blb_vco[8] = { |
7512 | [0] = 3200000, | |
7513 | [1] = 4000000, | |
7514 | [2] = 5333333, | |
7515 | [3] = 4800000, | |
7516 | [4] = 6400000, | |
7517 | }; | |
7518 | static const unsigned int pnv_vco[8] = { | |
7519 | [0] = 3200000, | |
7520 | [1] = 4000000, | |
7521 | [2] = 5333333, | |
7522 | [3] = 4800000, | |
7523 | [4] = 2666667, | |
7524 | }; | |
7525 | static const unsigned int cl_vco[8] = { | |
7526 | [0] = 3200000, | |
7527 | [1] = 4000000, | |
7528 | [2] = 5333333, | |
7529 | [3] = 6400000, | |
7530 | [4] = 3333333, | |
7531 | [5] = 3566667, | |
7532 | [6] = 4266667, | |
7533 | }; | |
7534 | static const unsigned int elk_vco[8] = { | |
7535 | [0] = 3200000, | |
7536 | [1] = 4000000, | |
7537 | [2] = 5333333, | |
7538 | [3] = 4800000, | |
7539 | }; | |
7540 | static const unsigned int ctg_vco[8] = { | |
7541 | [0] = 3200000, | |
7542 | [1] = 4000000, | |
7543 | [2] = 5333333, | |
7544 | [3] = 6400000, | |
7545 | [4] = 2666667, | |
7546 | [5] = 4266667, | |
7547 | }; | |
7548 | const unsigned int *vco_table; | |
7549 | unsigned int vco; | |
7550 | uint8_t tmp = 0; | |
7551 | ||
7552 | /* FIXME other chipsets? */ | |
50a0bc90 | 7553 | if (IS_GM45(dev_priv)) |
34edce2f | 7554 | vco_table = ctg_vco; |
9beb5fea | 7555 | else if (IS_G4X(dev_priv)) |
34edce2f VS |
7556 | vco_table = elk_vco; |
7557 | else if (IS_CRESTLINE(dev)) | |
7558 | vco_table = cl_vco; | |
7559 | else if (IS_PINEVIEW(dev)) | |
7560 | vco_table = pnv_vco; | |
7561 | else if (IS_G33(dev)) | |
7562 | vco_table = blb_vco; | |
7563 | else | |
7564 | return 0; | |
7565 | ||
7566 | tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO); | |
7567 | ||
7568 | vco = vco_table[tmp & 0x7]; | |
7569 | if (vco == 0) | |
7570 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); | |
7571 | else | |
7572 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); | |
7573 | ||
7574 | return vco; | |
7575 | } | |
7576 | ||
7577 | static int gm45_get_display_clock_speed(struct drm_device *dev) | |
7578 | { | |
52a05c30 | 7579 | struct pci_dev *pdev = dev->pdev; |
34edce2f VS |
7580 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); |
7581 | uint16_t tmp = 0; | |
7582 | ||
52a05c30 | 7583 | pci_read_config_word(pdev, GCFGC, &tmp); |
34edce2f VS |
7584 | |
7585 | cdclk_sel = (tmp >> 12) & 0x1; | |
7586 | ||
7587 | switch (vco) { | |
7588 | case 2666667: | |
7589 | case 4000000: | |
7590 | case 5333333: | |
7591 | return cdclk_sel ? 333333 : 222222; | |
7592 | case 3200000: | |
7593 | return cdclk_sel ? 320000 : 228571; | |
7594 | default: | |
7595 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); | |
7596 | return 222222; | |
7597 | } | |
7598 | } | |
7599 | ||
7600 | static int i965gm_get_display_clock_speed(struct drm_device *dev) | |
7601 | { | |
52a05c30 | 7602 | struct pci_dev *pdev = dev->pdev; |
34edce2f VS |
7603 | static const uint8_t div_3200[] = { 16, 10, 8 }; |
7604 | static const uint8_t div_4000[] = { 20, 12, 10 }; | |
7605 | static const uint8_t div_5333[] = { 24, 16, 14 }; | |
7606 | const uint8_t *div_table; | |
7607 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7608 | uint16_t tmp = 0; | |
7609 | ||
52a05c30 | 7610 | pci_read_config_word(pdev, GCFGC, &tmp); |
34edce2f VS |
7611 | |
7612 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; | |
7613 | ||
7614 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7615 | goto fail; | |
7616 | ||
7617 | switch (vco) { | |
7618 | case 3200000: | |
7619 | div_table = div_3200; | |
7620 | break; | |
7621 | case 4000000: | |
7622 | div_table = div_4000; | |
7623 | break; | |
7624 | case 5333333: | |
7625 | div_table = div_5333; | |
7626 | break; | |
7627 | default: | |
7628 | goto fail; | |
7629 | } | |
7630 | ||
7631 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7632 | ||
caf4e252 | 7633 | fail: |
34edce2f VS |
7634 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); |
7635 | return 200000; | |
7636 | } | |
7637 | ||
7638 | static int g33_get_display_clock_speed(struct drm_device *dev) | |
7639 | { | |
52a05c30 | 7640 | struct pci_dev *pdev = dev->pdev; |
34edce2f VS |
7641 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; |
7642 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; | |
7643 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; | |
7644 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; | |
7645 | const uint8_t *div_table; | |
7646 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7647 | uint16_t tmp = 0; | |
7648 | ||
52a05c30 | 7649 | pci_read_config_word(pdev, GCFGC, &tmp); |
34edce2f VS |
7650 | |
7651 | cdclk_sel = (tmp >> 4) & 0x7; | |
7652 | ||
7653 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7654 | goto fail; | |
7655 | ||
7656 | switch (vco) { | |
7657 | case 3200000: | |
7658 | div_table = div_3200; | |
7659 | break; | |
7660 | case 4000000: | |
7661 | div_table = div_4000; | |
7662 | break; | |
7663 | case 4800000: | |
7664 | div_table = div_4800; | |
7665 | break; | |
7666 | case 5333333: | |
7667 | div_table = div_5333; | |
7668 | break; | |
7669 | default: | |
7670 | goto fail; | |
7671 | } | |
7672 | ||
7673 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7674 | ||
caf4e252 | 7675 | fail: |
34edce2f VS |
7676 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); |
7677 | return 190476; | |
7678 | } | |
7679 | ||
2c07245f | 7680 | static void |
a65851af | 7681 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 7682 | { |
a65851af VS |
7683 | while (*num > DATA_LINK_M_N_MASK || |
7684 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
7685 | *num >>= 1; |
7686 | *den >>= 1; | |
7687 | } | |
7688 | } | |
7689 | ||
a65851af VS |
7690 | static void compute_m_n(unsigned int m, unsigned int n, |
7691 | uint32_t *ret_m, uint32_t *ret_n) | |
7692 | { | |
7693 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
7694 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
7695 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
7696 | } | |
7697 | ||
e69d0bc1 DV |
7698 | void |
7699 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
7700 | int pixel_clock, int link_clock, | |
7701 | struct intel_link_m_n *m_n) | |
2c07245f | 7702 | { |
e69d0bc1 | 7703 | m_n->tu = 64; |
a65851af VS |
7704 | |
7705 | compute_m_n(bits_per_pixel * pixel_clock, | |
7706 | link_clock * nlanes * 8, | |
7707 | &m_n->gmch_m, &m_n->gmch_n); | |
7708 | ||
7709 | compute_m_n(pixel_clock, link_clock, | |
7710 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
7711 | } |
7712 | ||
a7615030 CW |
7713 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
7714 | { | |
d330a953 JN |
7715 | if (i915.panel_use_ssc >= 0) |
7716 | return i915.panel_use_ssc != 0; | |
41aa3448 | 7717 | return dev_priv->vbt.lvds_use_ssc |
435793df | 7718 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
7719 | } |
7720 | ||
7429e9d4 | 7721 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 7722 | { |
7df00d7a | 7723 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 7724 | } |
f47709a9 | 7725 | |
7429e9d4 DV |
7726 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
7727 | { | |
7728 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
7729 | } |
7730 | ||
f47709a9 | 7731 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 7732 | struct intel_crtc_state *crtc_state, |
9e2c8475 | 7733 | struct dpll *reduced_clock) |
a7516a05 | 7734 | { |
f47709a9 | 7735 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
7736 | u32 fp, fp2 = 0; |
7737 | ||
7738 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 7739 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7740 | if (reduced_clock) |
7429e9d4 | 7741 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 7742 | } else { |
190f68c5 | 7743 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7744 | if (reduced_clock) |
7429e9d4 | 7745 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
7746 | } |
7747 | ||
190f68c5 | 7748 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 7749 | |
f47709a9 | 7750 | crtc->lowfreq_avail = false; |
2d84d2b3 | 7751 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 7752 | reduced_clock) { |
190f68c5 | 7753 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 7754 | crtc->lowfreq_avail = true; |
a7516a05 | 7755 | } else { |
190f68c5 | 7756 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
7757 | } |
7758 | } | |
7759 | ||
5e69f97f CML |
7760 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
7761 | pipe) | |
89b667f8 JB |
7762 | { |
7763 | u32 reg_val; | |
7764 | ||
7765 | /* | |
7766 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
7767 | * and set it to a reasonable value instead. | |
7768 | */ | |
ab3c759a | 7769 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
7770 | reg_val &= 0xffffff00; |
7771 | reg_val |= 0x00000030; | |
ab3c759a | 7772 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7773 | |
ab3c759a | 7774 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7775 | reg_val &= 0x8cffffff; |
7776 | reg_val = 0x8c000000; | |
ab3c759a | 7777 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 7778 | |
ab3c759a | 7779 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 7780 | reg_val &= 0xffffff00; |
ab3c759a | 7781 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7782 | |
ab3c759a | 7783 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7784 | reg_val &= 0x00ffffff; |
7785 | reg_val |= 0xb0000000; | |
ab3c759a | 7786 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
7787 | } |
7788 | ||
b551842d DV |
7789 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
7790 | struct intel_link_m_n *m_n) | |
7791 | { | |
7792 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7793 | struct drm_i915_private *dev_priv = to_i915(dev); |
b551842d DV |
7794 | int pipe = crtc->pipe; |
7795 | ||
e3b95f1e DV |
7796 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7797 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
7798 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
7799 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
7800 | } |
7801 | ||
7802 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
7803 | struct intel_link_m_n *m_n, |
7804 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
7805 | { |
7806 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7807 | struct drm_i915_private *dev_priv = to_i915(dev); |
b551842d | 7808 | int pipe = crtc->pipe; |
6e3c9717 | 7809 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
7810 | |
7811 | if (INTEL_INFO(dev)->gen >= 5) { | |
7812 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
7813 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
7814 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
7815 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
7816 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
7817 | * for gen < 8) and if DRRS is supported (to make sure the | |
7818 | * registers are not unnecessarily accessed). | |
7819 | */ | |
920a14b2 TU |
7820 | if (m2_n2 && (IS_CHERRYVIEW(dev_priv) || |
7821 | INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) { | |
f769cd24 VK |
7822 | I915_WRITE(PIPE_DATA_M2(transcoder), |
7823 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
7824 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
7825 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
7826 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
7827 | } | |
b551842d | 7828 | } else { |
e3b95f1e DV |
7829 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7830 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
7831 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
7832 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
7833 | } |
7834 | } | |
7835 | ||
fe3cd48d | 7836 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 7837 | { |
fe3cd48d R |
7838 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
7839 | ||
7840 | if (m_n == M1_N1) { | |
7841 | dp_m_n = &crtc->config->dp_m_n; | |
7842 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
7843 | } else if (m_n == M2_N2) { | |
7844 | ||
7845 | /* | |
7846 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
7847 | * needs to be programmed into M1_N1. | |
7848 | */ | |
7849 | dp_m_n = &crtc->config->dp_m2_n2; | |
7850 | } else { | |
7851 | DRM_ERROR("Unsupported divider value\n"); | |
7852 | return; | |
7853 | } | |
7854 | ||
6e3c9717 ACO |
7855 | if (crtc->config->has_pch_encoder) |
7856 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 7857 | else |
fe3cd48d | 7858 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
7859 | } |
7860 | ||
251ac862 DV |
7861 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
7862 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 | 7863 | { |
03ed5cbf | 7864 | pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | |
cd2d34d9 | 7865 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
7866 | if (crtc->pipe != PIPE_A) |
7867 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
bdd4b6a6 | 7868 | |
cd2d34d9 | 7869 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 7870 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
7871 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | |
7872 | DPLL_EXT_BUFFER_ENABLE_VLV; | |
7873 | ||
03ed5cbf VS |
7874 | pipe_config->dpll_hw_state.dpll_md = |
7875 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
7876 | } | |
bdd4b6a6 | 7877 | |
03ed5cbf VS |
7878 | static void chv_compute_dpll(struct intel_crtc *crtc, |
7879 | struct intel_crtc_state *pipe_config) | |
7880 | { | |
7881 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | | |
cd2d34d9 | 7882 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
7883 | if (crtc->pipe != PIPE_A) |
7884 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
7885 | ||
cd2d34d9 | 7886 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 7887 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
7888 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; |
7889 | ||
03ed5cbf VS |
7890 | pipe_config->dpll_hw_state.dpll_md = |
7891 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
bdd4b6a6 DV |
7892 | } |
7893 | ||
d288f65f | 7894 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7895 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 7896 | { |
f47709a9 | 7897 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7898 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 7899 | enum pipe pipe = crtc->pipe; |
bdd4b6a6 | 7900 | u32 mdiv; |
a0c4da24 | 7901 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 7902 | u32 coreclk, reg_val; |
a0c4da24 | 7903 | |
cd2d34d9 VS |
7904 | /* Enable Refclk */ |
7905 | I915_WRITE(DPLL(pipe), | |
7906 | pipe_config->dpll_hw_state.dpll & | |
7907 | ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); | |
7908 | ||
7909 | /* No need to actually set up the DPLL with DSI */ | |
7910 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
7911 | return; | |
7912 | ||
a580516d | 7913 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 7914 | |
d288f65f VS |
7915 | bestn = pipe_config->dpll.n; |
7916 | bestm1 = pipe_config->dpll.m1; | |
7917 | bestm2 = pipe_config->dpll.m2; | |
7918 | bestp1 = pipe_config->dpll.p1; | |
7919 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 7920 | |
89b667f8 JB |
7921 | /* See eDP HDMI DPIO driver vbios notes doc */ |
7922 | ||
7923 | /* PLL B needs special handling */ | |
bdd4b6a6 | 7924 | if (pipe == PIPE_B) |
5e69f97f | 7925 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
7926 | |
7927 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 7928 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
7929 | |
7930 | /* Disable target IRef on PLL */ | |
ab3c759a | 7931 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 7932 | reg_val &= 0x00ffffff; |
ab3c759a | 7933 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
7934 | |
7935 | /* Disable fast lock */ | |
ab3c759a | 7936 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
7937 | |
7938 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
7939 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
7940 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
7941 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 7942 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
7943 | |
7944 | /* | |
7945 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
7946 | * but we don't support that). | |
7947 | * Note: don't use the DAC post divider as it seems unstable. | |
7948 | */ | |
7949 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 7950 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7951 | |
a0c4da24 | 7952 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 7953 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7954 | |
89b667f8 | 7955 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 7956 | if (pipe_config->port_clock == 162000 || |
2d84d2b3 VS |
7957 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) || |
7958 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 7959 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 7960 | 0x009f0003); |
89b667f8 | 7961 | else |
ab3c759a | 7962 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
7963 | 0x00d0000f); |
7964 | ||
37a5650b | 7965 | if (intel_crtc_has_dp_encoder(pipe_config)) { |
89b667f8 | 7966 | /* Use SSC source */ |
bdd4b6a6 | 7967 | if (pipe == PIPE_A) |
ab3c759a | 7968 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7969 | 0x0df40000); |
7970 | else | |
ab3c759a | 7971 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7972 | 0x0df70000); |
7973 | } else { /* HDMI or VGA */ | |
7974 | /* Use bend source */ | |
bdd4b6a6 | 7975 | if (pipe == PIPE_A) |
ab3c759a | 7976 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7977 | 0x0df70000); |
7978 | else | |
ab3c759a | 7979 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7980 | 0x0df40000); |
7981 | } | |
a0c4da24 | 7982 | |
ab3c759a | 7983 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 7984 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
2210ce7f | 7985 | if (intel_crtc_has_dp_encoder(crtc->config)) |
89b667f8 | 7986 | coreclk |= 0x01000000; |
ab3c759a | 7987 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 7988 | |
ab3c759a | 7989 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 7990 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
7991 | } |
7992 | ||
d288f65f | 7993 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7994 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
7995 | { |
7996 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7997 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 7998 | enum pipe pipe = crtc->pipe; |
9d556c99 | 7999 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9cbe40c1 | 8000 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 8001 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 8002 | u32 dpio_val; |
9cbe40c1 | 8003 | int vco; |
9d556c99 | 8004 | |
cd2d34d9 VS |
8005 | /* Enable Refclk and SSC */ |
8006 | I915_WRITE(DPLL(pipe), | |
8007 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); | |
8008 | ||
8009 | /* No need to actually set up the DPLL with DSI */ | |
8010 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
8011 | return; | |
8012 | ||
d288f65f VS |
8013 | bestn = pipe_config->dpll.n; |
8014 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
8015 | bestm1 = pipe_config->dpll.m1; | |
8016 | bestm2 = pipe_config->dpll.m2 >> 22; | |
8017 | bestp1 = pipe_config->dpll.p1; | |
8018 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 8019 | vco = pipe_config->dpll.vco; |
a945ce7e | 8020 | dpio_val = 0; |
9cbe40c1 | 8021 | loopfilter = 0; |
9d556c99 | 8022 | |
a580516d | 8023 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 8024 | |
9d556c99 CML |
8025 | /* p1 and p2 divider */ |
8026 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
8027 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
8028 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
8029 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
8030 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
8031 | ||
8032 | /* Feedback post-divider - m2 */ | |
8033 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
8034 | ||
8035 | /* Feedback refclk divider - n and m1 */ | |
8036 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
8037 | DPIO_CHV_M1_DIV_BY_2 | | |
8038 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
8039 | ||
8040 | /* M2 fraction division */ | |
25a25dfc | 8041 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
8042 | |
8043 | /* M2 fraction division enable */ | |
a945ce7e VP |
8044 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
8045 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
8046 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
8047 | if (bestm2_frac) | |
8048 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
8049 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 8050 | |
de3a0fde VP |
8051 | /* Program digital lock detect threshold */ |
8052 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
8053 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
8054 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
8055 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
8056 | if (!bestm2_frac) | |
8057 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
8058 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
8059 | ||
9d556c99 | 8060 | /* Loop filter */ |
9cbe40c1 VP |
8061 | if (vco == 5400000) { |
8062 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
8063 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
8064 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
8065 | tribuf_calcntr = 0x9; | |
8066 | } else if (vco <= 6200000) { | |
8067 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
8068 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
8069 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
8070 | tribuf_calcntr = 0x9; | |
8071 | } else if (vco <= 6480000) { | |
8072 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
8073 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
8074 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
8075 | tribuf_calcntr = 0x8; | |
8076 | } else { | |
8077 | /* Not supported. Apply the same limits as in the max case */ | |
8078 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
8079 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
8080 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
8081 | tribuf_calcntr = 0; | |
8082 | } | |
9d556c99 CML |
8083 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
8084 | ||
968040b2 | 8085 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
8086 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
8087 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
8088 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
8089 | ||
9d556c99 CML |
8090 | /* AFC Recal */ |
8091 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
8092 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
8093 | DPIO_AFC_RECAL); | |
8094 | ||
a580516d | 8095 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
8096 | } |
8097 | ||
d288f65f VS |
8098 | /** |
8099 | * vlv_force_pll_on - forcibly enable just the PLL | |
8100 | * @dev_priv: i915 private structure | |
8101 | * @pipe: pipe PLL to enable | |
8102 | * @dpll: PLL configuration | |
8103 | * | |
8104 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
8105 | * in cases where we need the PLL enabled even when @pipe is not going to | |
8106 | * be enabled. | |
8107 | */ | |
3f36b937 TU |
8108 | int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, |
8109 | const struct dpll *dpll) | |
d288f65f VS |
8110 | { |
8111 | struct intel_crtc *crtc = | |
8112 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
3f36b937 TU |
8113 | struct intel_crtc_state *pipe_config; |
8114 | ||
8115 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); | |
8116 | if (!pipe_config) | |
8117 | return -ENOMEM; | |
8118 | ||
8119 | pipe_config->base.crtc = &crtc->base; | |
8120 | pipe_config->pixel_multiplier = 1; | |
8121 | pipe_config->dpll = *dpll; | |
d288f65f | 8122 | |
920a14b2 | 8123 | if (IS_CHERRYVIEW(to_i915(dev))) { |
3f36b937 TU |
8124 | chv_compute_dpll(crtc, pipe_config); |
8125 | chv_prepare_pll(crtc, pipe_config); | |
8126 | chv_enable_pll(crtc, pipe_config); | |
d288f65f | 8127 | } else { |
3f36b937 TU |
8128 | vlv_compute_dpll(crtc, pipe_config); |
8129 | vlv_prepare_pll(crtc, pipe_config); | |
8130 | vlv_enable_pll(crtc, pipe_config); | |
d288f65f | 8131 | } |
3f36b937 TU |
8132 | |
8133 | kfree(pipe_config); | |
8134 | ||
8135 | return 0; | |
d288f65f VS |
8136 | } |
8137 | ||
8138 | /** | |
8139 | * vlv_force_pll_off - forcibly disable just the PLL | |
8140 | * @dev_priv: i915 private structure | |
8141 | * @pipe: pipe PLL to disable | |
8142 | * | |
8143 | * Disable the PLL for @pipe. To be used in cases where we need | |
8144 | * the PLL enabled even when @pipe is not going to be enabled. | |
8145 | */ | |
8146 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
8147 | { | |
920a14b2 | 8148 | if (IS_CHERRYVIEW(to_i915(dev))) |
d288f65f VS |
8149 | chv_disable_pll(to_i915(dev), pipe); |
8150 | else | |
8151 | vlv_disable_pll(to_i915(dev), pipe); | |
8152 | } | |
8153 | ||
251ac862 DV |
8154 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
8155 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 8156 | struct dpll *reduced_clock) |
eb1cbe48 | 8157 | { |
f47709a9 | 8158 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 8159 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb1cbe48 | 8160 | u32 dpll; |
190f68c5 | 8161 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 8162 | |
190f68c5 | 8163 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 8164 | |
eb1cbe48 DV |
8165 | dpll = DPLL_VGA_MODE_DIS; |
8166 | ||
2d84d2b3 | 8167 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
8168 | dpll |= DPLLB_MODE_LVDS; |
8169 | else | |
8170 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 8171 | |
50a0bc90 | 8172 | if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || IS_G33(dev_priv)) { |
190f68c5 | 8173 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 8174 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 8175 | } |
198a037f | 8176 | |
3d6e9ee0 VS |
8177 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
8178 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 8179 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 8180 | |
37a5650b | 8181 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 8182 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
8183 | |
8184 | /* compute bitmask from p1 value */ | |
8185 | if (IS_PINEVIEW(dev)) | |
8186 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
8187 | else { | |
8188 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
9beb5fea | 8189 | if (IS_G4X(dev_priv) && reduced_clock) |
eb1cbe48 DV |
8190 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
8191 | } | |
8192 | switch (clock->p2) { | |
8193 | case 5: | |
8194 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8195 | break; | |
8196 | case 7: | |
8197 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8198 | break; | |
8199 | case 10: | |
8200 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8201 | break; | |
8202 | case 14: | |
8203 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8204 | break; | |
8205 | } | |
8206 | if (INTEL_INFO(dev)->gen >= 4) | |
8207 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
8208 | ||
190f68c5 | 8209 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 8210 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
2d84d2b3 | 8211 | else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 8212 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
8213 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
8214 | else | |
8215 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8216 | ||
8217 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 8218 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 8219 | |
eb1cbe48 | 8220 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 8221 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8222 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 8223 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
8224 | } |
8225 | } | |
8226 | ||
251ac862 DV |
8227 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
8228 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 8229 | struct dpll *reduced_clock) |
eb1cbe48 | 8230 | { |
f47709a9 | 8231 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 8232 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb1cbe48 | 8233 | u32 dpll; |
190f68c5 | 8234 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 8235 | |
190f68c5 | 8236 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 8237 | |
eb1cbe48 DV |
8238 | dpll = DPLL_VGA_MODE_DIS; |
8239 | ||
2d84d2b3 | 8240 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
8241 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
8242 | } else { | |
8243 | if (clock->p1 == 2) | |
8244 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
8245 | else | |
8246 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
8247 | if (clock->p2 == 4) | |
8248 | dpll |= PLL_P2_DIVIDE_BY_4; | |
8249 | } | |
8250 | ||
50a0bc90 TU |
8251 | if (!IS_I830(dev_priv) && |
8252 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) | |
4a33e48d DV |
8253 | dpll |= DPLL_DVO_2X_MODE; |
8254 | ||
2d84d2b3 | 8255 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 8256 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
8257 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
8258 | else | |
8259 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8260 | ||
8261 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 8262 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
8263 | } |
8264 | ||
8a654f3b | 8265 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
8266 | { |
8267 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 8268 | struct drm_i915_private *dev_priv = to_i915(dev); |
b0e77b9c | 8269 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 8270 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
7c5f93b0 | 8271 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
8272 | uint32_t crtc_vtotal, crtc_vblank_end; |
8273 | int vsyncshift = 0; | |
4d8a62ea DV |
8274 | |
8275 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
8276 | * the hw state checker will get angry at the mismatch. */ | |
8277 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
8278 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 8279 | |
609aeaca | 8280 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 8281 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
8282 | crtc_vtotal -= 1; |
8283 | crtc_vblank_end -= 1; | |
609aeaca | 8284 | |
2d84d2b3 | 8285 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
8286 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
8287 | else | |
8288 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
8289 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
8290 | if (vsyncshift < 0) |
8291 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
8292 | } |
8293 | ||
8294 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 8295 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 8296 | |
fe2b8f9d | 8297 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
8298 | (adjusted_mode->crtc_hdisplay - 1) | |
8299 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 8300 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
8301 | (adjusted_mode->crtc_hblank_start - 1) | |
8302 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 8303 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
8304 | (adjusted_mode->crtc_hsync_start - 1) | |
8305 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
8306 | ||
fe2b8f9d | 8307 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 8308 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 8309 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 8310 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 8311 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 8312 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 8313 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
8314 | (adjusted_mode->crtc_vsync_start - 1) | |
8315 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
8316 | ||
b5e508d4 PZ |
8317 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
8318 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
8319 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
8320 | * bits. */ | |
772c2a51 | 8321 | if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && |
b5e508d4 PZ |
8322 | (pipe == PIPE_B || pipe == PIPE_C)) |
8323 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
8324 | ||
bc58be60 JN |
8325 | } |
8326 | ||
8327 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc) | |
8328 | { | |
8329 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 8330 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 JN |
8331 | enum pipe pipe = intel_crtc->pipe; |
8332 | ||
b0e77b9c PZ |
8333 | /* pipesrc controls the size that is scaled from, which should |
8334 | * always be the user's requested size. | |
8335 | */ | |
8336 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
8337 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
8338 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
8339 | } |
8340 | ||
1bd1bd80 | 8341 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 8342 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
8343 | { |
8344 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8345 | struct drm_i915_private *dev_priv = to_i915(dev); |
1bd1bd80 DV |
8346 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
8347 | uint32_t tmp; | |
8348 | ||
8349 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
8350 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
8351 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 8352 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
8353 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
8354 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 8355 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
8356 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
8357 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
8358 | |
8359 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
8360 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
8361 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 8362 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
8363 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
8364 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 8365 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
8366 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
8367 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
8368 | |
8369 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
8370 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
8371 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
8372 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 | 8373 | } |
bc58be60 JN |
8374 | } |
8375 | ||
8376 | static void intel_get_pipe_src_size(struct intel_crtc *crtc, | |
8377 | struct intel_crtc_state *pipe_config) | |
8378 | { | |
8379 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8380 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 | 8381 | u32 tmp; |
1bd1bd80 DV |
8382 | |
8383 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
8384 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
8385 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
8386 | ||
2d112de7 ACO |
8387 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
8388 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
8389 | } |
8390 | ||
f6a83288 | 8391 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 8392 | struct intel_crtc_state *pipe_config) |
babea61d | 8393 | { |
2d112de7 ACO |
8394 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
8395 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
8396 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
8397 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 8398 | |
2d112de7 ACO |
8399 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
8400 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
8401 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
8402 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 8403 | |
2d112de7 | 8404 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 8405 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 8406 | |
2d112de7 ACO |
8407 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
8408 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
cd13f5ab ML |
8409 | |
8410 | mode->hsync = drm_mode_hsync(mode); | |
8411 | mode->vrefresh = drm_mode_vrefresh(mode); | |
8412 | drm_mode_set_name(mode); | |
babea61d JB |
8413 | } |
8414 | ||
84b046f3 DV |
8415 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
8416 | { | |
8417 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 8418 | struct drm_i915_private *dev_priv = to_i915(dev); |
84b046f3 DV |
8419 | uint32_t pipeconf; |
8420 | ||
9f11a9e4 | 8421 | pipeconf = 0; |
84b046f3 | 8422 | |
b6b5d049 VS |
8423 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
8424 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8425 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 8426 | |
6e3c9717 | 8427 | if (intel_crtc->config->double_wide) |
cf532bb2 | 8428 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 8429 | |
ff9ce46e | 8430 | /* only g4x and later have fancy bpc/dither controls */ |
9beb5fea TU |
8431 | if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
8432 | IS_CHERRYVIEW(dev_priv)) { | |
ff9ce46e | 8433 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 8434 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 8435 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 8436 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 8437 | |
6e3c9717 | 8438 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
8439 | case 18: |
8440 | pipeconf |= PIPECONF_6BPC; | |
8441 | break; | |
8442 | case 24: | |
8443 | pipeconf |= PIPECONF_8BPC; | |
8444 | break; | |
8445 | case 30: | |
8446 | pipeconf |= PIPECONF_10BPC; | |
8447 | break; | |
8448 | default: | |
8449 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
8450 | BUG(); | |
84b046f3 DV |
8451 | } |
8452 | } | |
8453 | ||
8454 | if (HAS_PIPE_CXSR(dev)) { | |
8455 | if (intel_crtc->lowfreq_avail) { | |
8456 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
8457 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
8458 | } else { | |
8459 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
8460 | } |
8461 | } | |
8462 | ||
6e3c9717 | 8463 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 8464 | if (INTEL_INFO(dev)->gen < 4 || |
2d84d2b3 | 8465 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
8466 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
8467 | else | |
8468 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
8469 | } else | |
84b046f3 DV |
8470 | pipeconf |= PIPECONF_PROGRESSIVE; |
8471 | ||
920a14b2 | 8472 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
666a4537 | 8473 | intel_crtc->config->limited_color_range) |
9f11a9e4 | 8474 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 8475 | |
84b046f3 DV |
8476 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
8477 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
8478 | } | |
8479 | ||
81c97f52 ACO |
8480 | static int i8xx_crtc_compute_clock(struct intel_crtc *crtc, |
8481 | struct intel_crtc_state *crtc_state) | |
8482 | { | |
8483 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8484 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 8485 | const struct intel_limit *limit; |
81c97f52 ACO |
8486 | int refclk = 48000; |
8487 | ||
8488 | memset(&crtc_state->dpll_hw_state, 0, | |
8489 | sizeof(crtc_state->dpll_hw_state)); | |
8490 | ||
2d84d2b3 | 8491 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
81c97f52 ACO |
8492 | if (intel_panel_use_ssc(dev_priv)) { |
8493 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8494 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
8495 | } | |
8496 | ||
8497 | limit = &intel_limits_i8xx_lvds; | |
2d84d2b3 | 8498 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) { |
81c97f52 ACO |
8499 | limit = &intel_limits_i8xx_dvo; |
8500 | } else { | |
8501 | limit = &intel_limits_i8xx_dac; | |
8502 | } | |
8503 | ||
8504 | if (!crtc_state->clock_set && | |
8505 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8506 | refclk, NULL, &crtc_state->dpll)) { | |
8507 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8508 | return -EINVAL; | |
8509 | } | |
8510 | ||
8511 | i8xx_compute_dpll(crtc, crtc_state, NULL); | |
8512 | ||
8513 | return 0; | |
8514 | } | |
8515 | ||
19ec6693 ACO |
8516 | static int g4x_crtc_compute_clock(struct intel_crtc *crtc, |
8517 | struct intel_crtc_state *crtc_state) | |
8518 | { | |
8519 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8520 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 8521 | const struct intel_limit *limit; |
19ec6693 ACO |
8522 | int refclk = 96000; |
8523 | ||
8524 | memset(&crtc_state->dpll_hw_state, 0, | |
8525 | sizeof(crtc_state->dpll_hw_state)); | |
8526 | ||
2d84d2b3 | 8527 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
19ec6693 ACO |
8528 | if (intel_panel_use_ssc(dev_priv)) { |
8529 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8530 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
8531 | } | |
8532 | ||
8533 | if (intel_is_dual_link_lvds(dev)) | |
8534 | limit = &intel_limits_g4x_dual_channel_lvds; | |
8535 | else | |
8536 | limit = &intel_limits_g4x_single_channel_lvds; | |
2d84d2b3 VS |
8537 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) || |
8538 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
19ec6693 | 8539 | limit = &intel_limits_g4x_hdmi; |
2d84d2b3 | 8540 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
19ec6693 ACO |
8541 | limit = &intel_limits_g4x_sdvo; |
8542 | } else { | |
8543 | /* The option is for other outputs */ | |
8544 | limit = &intel_limits_i9xx_sdvo; | |
8545 | } | |
8546 | ||
8547 | if (!crtc_state->clock_set && | |
8548 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8549 | refclk, NULL, &crtc_state->dpll)) { | |
8550 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8551 | return -EINVAL; | |
8552 | } | |
8553 | ||
8554 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
8555 | ||
8556 | return 0; | |
8557 | } | |
8558 | ||
70e8aa21 ACO |
8559 | static int pnv_crtc_compute_clock(struct intel_crtc *crtc, |
8560 | struct intel_crtc_state *crtc_state) | |
8561 | { | |
8562 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8563 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 8564 | const struct intel_limit *limit; |
70e8aa21 ACO |
8565 | int refclk = 96000; |
8566 | ||
8567 | memset(&crtc_state->dpll_hw_state, 0, | |
8568 | sizeof(crtc_state->dpll_hw_state)); | |
8569 | ||
2d84d2b3 | 8570 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
8571 | if (intel_panel_use_ssc(dev_priv)) { |
8572 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8573 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
8574 | } | |
8575 | ||
8576 | limit = &intel_limits_pineview_lvds; | |
8577 | } else { | |
8578 | limit = &intel_limits_pineview_sdvo; | |
8579 | } | |
8580 | ||
8581 | if (!crtc_state->clock_set && | |
8582 | !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8583 | refclk, NULL, &crtc_state->dpll)) { | |
8584 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8585 | return -EINVAL; | |
8586 | } | |
8587 | ||
8588 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
8589 | ||
8590 | return 0; | |
8591 | } | |
8592 | ||
190f68c5 ACO |
8593 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
8594 | struct intel_crtc_state *crtc_state) | |
79e53945 | 8595 | { |
c7653199 | 8596 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 8597 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 8598 | const struct intel_limit *limit; |
81c97f52 | 8599 | int refclk = 96000; |
79e53945 | 8600 | |
dd3cd74a ACO |
8601 | memset(&crtc_state->dpll_hw_state, 0, |
8602 | sizeof(crtc_state->dpll_hw_state)); | |
8603 | ||
2d84d2b3 | 8604 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
8605 | if (intel_panel_use_ssc(dev_priv)) { |
8606 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8607 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
8608 | } | |
43565a06 | 8609 | |
70e8aa21 ACO |
8610 | limit = &intel_limits_i9xx_lvds; |
8611 | } else { | |
8612 | limit = &intel_limits_i9xx_sdvo; | |
81c97f52 | 8613 | } |
79e53945 | 8614 | |
70e8aa21 ACO |
8615 | if (!crtc_state->clock_set && |
8616 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8617 | refclk, NULL, &crtc_state->dpll)) { | |
8618 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8619 | return -EINVAL; | |
f47709a9 | 8620 | } |
7026d4ac | 8621 | |
81c97f52 | 8622 | i9xx_compute_dpll(crtc, crtc_state, NULL); |
79e53945 | 8623 | |
c8f7a0db | 8624 | return 0; |
f564048e EA |
8625 | } |
8626 | ||
65b3d6a9 ACO |
8627 | static int chv_crtc_compute_clock(struct intel_crtc *crtc, |
8628 | struct intel_crtc_state *crtc_state) | |
8629 | { | |
8630 | int refclk = 100000; | |
1b6f4958 | 8631 | const struct intel_limit *limit = &intel_limits_chv; |
65b3d6a9 ACO |
8632 | |
8633 | memset(&crtc_state->dpll_hw_state, 0, | |
8634 | sizeof(crtc_state->dpll_hw_state)); | |
8635 | ||
65b3d6a9 ACO |
8636 | if (!crtc_state->clock_set && |
8637 | !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8638 | refclk, NULL, &crtc_state->dpll)) { | |
8639 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8640 | return -EINVAL; | |
8641 | } | |
8642 | ||
8643 | chv_compute_dpll(crtc, crtc_state); | |
8644 | ||
8645 | return 0; | |
8646 | } | |
8647 | ||
8648 | static int vlv_crtc_compute_clock(struct intel_crtc *crtc, | |
8649 | struct intel_crtc_state *crtc_state) | |
8650 | { | |
8651 | int refclk = 100000; | |
1b6f4958 | 8652 | const struct intel_limit *limit = &intel_limits_vlv; |
65b3d6a9 ACO |
8653 | |
8654 | memset(&crtc_state->dpll_hw_state, 0, | |
8655 | sizeof(crtc_state->dpll_hw_state)); | |
8656 | ||
65b3d6a9 ACO |
8657 | if (!crtc_state->clock_set && |
8658 | !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8659 | refclk, NULL, &crtc_state->dpll)) { | |
8660 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8661 | return -EINVAL; | |
8662 | } | |
8663 | ||
8664 | vlv_compute_dpll(crtc, crtc_state); | |
8665 | ||
8666 | return 0; | |
8667 | } | |
8668 | ||
2fa2fe9a | 8669 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8670 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
8671 | { |
8672 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8673 | struct drm_i915_private *dev_priv = to_i915(dev); |
2fa2fe9a DV |
8674 | uint32_t tmp; |
8675 | ||
50a0bc90 TU |
8676 | if (INTEL_GEN(dev_priv) <= 3 && |
8677 | (IS_I830(dev_priv) || !IS_MOBILE(dev_priv))) | |
dc9e7dec VS |
8678 | return; |
8679 | ||
2fa2fe9a | 8680 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
8681 | if (!(tmp & PFIT_ENABLE)) |
8682 | return; | |
2fa2fe9a | 8683 | |
06922821 | 8684 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
8685 | if (INTEL_INFO(dev)->gen < 4) { |
8686 | if (crtc->pipe != PIPE_B) | |
8687 | return; | |
2fa2fe9a DV |
8688 | } else { |
8689 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
8690 | return; | |
8691 | } | |
8692 | ||
06922821 | 8693 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a | 8694 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
2fa2fe9a DV |
8695 | } |
8696 | ||
acbec814 | 8697 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8698 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
8699 | { |
8700 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8701 | struct drm_i915_private *dev_priv = to_i915(dev); |
acbec814 | 8702 | int pipe = pipe_config->cpu_transcoder; |
9e2c8475 | 8703 | struct dpll clock; |
acbec814 | 8704 | u32 mdiv; |
662c6ecb | 8705 | int refclk = 100000; |
acbec814 | 8706 | |
b521973b VS |
8707 | /* In case of DSI, DPLL will not be used */ |
8708 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
f573de5a SK |
8709 | return; |
8710 | ||
a580516d | 8711 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 8712 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 8713 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
8714 | |
8715 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
8716 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
8717 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
8718 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
8719 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
8720 | ||
dccbea3b | 8721 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
8722 | } |
8723 | ||
5724dbd1 DL |
8724 | static void |
8725 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
8726 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
8727 | { |
8728 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8729 | struct drm_i915_private *dev_priv = to_i915(dev); |
1ad292b5 JB |
8730 | u32 val, base, offset; |
8731 | int pipe = crtc->pipe, plane = crtc->plane; | |
8732 | int fourcc, pixel_format; | |
6761dd31 | 8733 | unsigned int aligned_height; |
b113d5ee | 8734 | struct drm_framebuffer *fb; |
1b842c89 | 8735 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 8736 | |
42a7b088 DL |
8737 | val = I915_READ(DSPCNTR(plane)); |
8738 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8739 | return; | |
8740 | ||
d9806c9f | 8741 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8742 | if (!intel_fb) { |
1ad292b5 JB |
8743 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8744 | return; | |
8745 | } | |
8746 | ||
1b842c89 DL |
8747 | fb = &intel_fb->base; |
8748 | ||
18c5247e DV |
8749 | if (INTEL_INFO(dev)->gen >= 4) { |
8750 | if (val & DISPPLANE_TILED) { | |
49af449b | 8751 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
8752 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
8753 | } | |
8754 | } | |
1ad292b5 JB |
8755 | |
8756 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8757 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
8758 | fb->pixel_format = fourcc; |
8759 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
8760 | |
8761 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 8762 | if (plane_config->tiling) |
1ad292b5 JB |
8763 | offset = I915_READ(DSPTILEOFF(plane)); |
8764 | else | |
8765 | offset = I915_READ(DSPLINOFF(plane)); | |
8766 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
8767 | } else { | |
8768 | base = I915_READ(DSPADDR(plane)); | |
8769 | } | |
8770 | plane_config->base = base; | |
8771 | ||
8772 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8773 | fb->width = ((val >> 16) & 0xfff) + 1; |
8774 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
8775 | |
8776 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8777 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 8778 | |
b113d5ee | 8779 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
8780 | fb->pixel_format, |
8781 | fb->modifier[0]); | |
1ad292b5 | 8782 | |
f37b5c2b | 8783 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 8784 | |
2844a921 DL |
8785 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8786 | pipe_name(pipe), plane, fb->width, fb->height, | |
8787 | fb->bits_per_pixel, base, fb->pitches[0], | |
8788 | plane_config->size); | |
1ad292b5 | 8789 | |
2d14030b | 8790 | plane_config->fb = intel_fb; |
1ad292b5 JB |
8791 | } |
8792 | ||
70b23a98 | 8793 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8794 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
8795 | { |
8796 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8797 | struct drm_i915_private *dev_priv = to_i915(dev); |
70b23a98 VS |
8798 | int pipe = pipe_config->cpu_transcoder; |
8799 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9e2c8475 | 8800 | struct dpll clock; |
0d7b6b11 | 8801 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
8802 | int refclk = 100000; |
8803 | ||
b521973b VS |
8804 | /* In case of DSI, DPLL will not be used */ |
8805 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
8806 | return; | |
8807 | ||
a580516d | 8808 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
8809 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
8810 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
8811 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
8812 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 8813 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 8814 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
8815 | |
8816 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
8817 | clock.m2 = (pll_dw0 & 0xff) << 22; |
8818 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
8819 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
8820 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
8821 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
8822 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
8823 | ||
dccbea3b | 8824 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
8825 | } |
8826 | ||
0e8ffe1b | 8827 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8828 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8829 | { |
8830 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8831 | struct drm_i915_private *dev_priv = to_i915(dev); |
1729050e | 8832 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 8833 | uint32_t tmp; |
1729050e | 8834 | bool ret; |
0e8ffe1b | 8835 | |
1729050e ID |
8836 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
8837 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 ID |
8838 | return false; |
8839 | ||
e143a21c | 8840 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 8841 | pipe_config->shared_dpll = NULL; |
eccb140b | 8842 | |
1729050e ID |
8843 | ret = false; |
8844 | ||
0e8ffe1b DV |
8845 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8846 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 8847 | goto out; |
0e8ffe1b | 8848 | |
9beb5fea TU |
8849 | if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
8850 | IS_CHERRYVIEW(dev_priv)) { | |
42571aef VS |
8851 | switch (tmp & PIPECONF_BPC_MASK) { |
8852 | case PIPECONF_6BPC: | |
8853 | pipe_config->pipe_bpp = 18; | |
8854 | break; | |
8855 | case PIPECONF_8BPC: | |
8856 | pipe_config->pipe_bpp = 24; | |
8857 | break; | |
8858 | case PIPECONF_10BPC: | |
8859 | pipe_config->pipe_bpp = 30; | |
8860 | break; | |
8861 | default: | |
8862 | break; | |
8863 | } | |
8864 | } | |
8865 | ||
920a14b2 | 8866 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
666a4537 | 8867 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
b5a9fa09 DV |
8868 | pipe_config->limited_color_range = true; |
8869 | ||
282740f7 VS |
8870 | if (INTEL_INFO(dev)->gen < 4) |
8871 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
8872 | ||
1bd1bd80 | 8873 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 8874 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 8875 | |
2fa2fe9a DV |
8876 | i9xx_get_pfit_config(crtc, pipe_config); |
8877 | ||
6c49f241 | 8878 | if (INTEL_INFO(dev)->gen >= 4) { |
c231775c | 8879 | /* No way to read it out on pipes B and C */ |
920a14b2 | 8880 | if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) |
c231775c VS |
8881 | tmp = dev_priv->chv_dpll_md[crtc->pipe]; |
8882 | else | |
8883 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
6c49f241 DV |
8884 | pipe_config->pixel_multiplier = |
8885 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
8886 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 8887 | pipe_config->dpll_hw_state.dpll_md = tmp; |
50a0bc90 TU |
8888 | } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || |
8889 | IS_G33(dev_priv)) { | |
6c49f241 DV |
8890 | tmp = I915_READ(DPLL(crtc->pipe)); |
8891 | pipe_config->pixel_multiplier = | |
8892 | ((tmp & SDVO_MULTIPLIER_MASK) | |
8893 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
8894 | } else { | |
8895 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
8896 | * port and will be fixed up in the encoder->get_config | |
8897 | * function. */ | |
8898 | pipe_config->pixel_multiplier = 1; | |
8899 | } | |
8bcc2795 | 8900 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
920a14b2 | 8901 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { |
1c4e0274 VS |
8902 | /* |
8903 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
8904 | * on 830. Filter it out here so that we don't | |
8905 | * report errors due to that. | |
8906 | */ | |
50a0bc90 | 8907 | if (IS_I830(dev_priv)) |
1c4e0274 VS |
8908 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; |
8909 | ||
8bcc2795 DV |
8910 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
8911 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
8912 | } else { |
8913 | /* Mask out read-only status bits. */ | |
8914 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
8915 | DPLL_PORTC_READY_MASK | | |
8916 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 8917 | } |
6c49f241 | 8918 | |
920a14b2 | 8919 | if (IS_CHERRYVIEW(dev_priv)) |
70b23a98 | 8920 | chv_crtc_clock_get(crtc, pipe_config); |
11a914c2 | 8921 | else if (IS_VALLEYVIEW(dev_priv)) |
acbec814 JB |
8922 | vlv_crtc_clock_get(crtc, pipe_config); |
8923 | else | |
8924 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 8925 | |
0f64614d VS |
8926 | /* |
8927 | * Normally the dotclock is filled in by the encoder .get_config() | |
8928 | * but in case the pipe is enabled w/o any ports we need a sane | |
8929 | * default. | |
8930 | */ | |
8931 | pipe_config->base.adjusted_mode.crtc_clock = | |
8932 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
8933 | ||
1729050e ID |
8934 | ret = true; |
8935 | ||
8936 | out: | |
8937 | intel_display_power_put(dev_priv, power_domain); | |
8938 | ||
8939 | return ret; | |
0e8ffe1b DV |
8940 | } |
8941 | ||
dde86e2d | 8942 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 | 8943 | { |
fac5e23e | 8944 | struct drm_i915_private *dev_priv = to_i915(dev); |
13d83a67 | 8945 | struct intel_encoder *encoder; |
1c1a24d2 | 8946 | int i; |
74cfd7ac | 8947 | u32 val, final; |
13d83a67 | 8948 | bool has_lvds = false; |
199e5d79 | 8949 | bool has_cpu_edp = false; |
199e5d79 | 8950 | bool has_panel = false; |
99eb6a01 KP |
8951 | bool has_ck505 = false; |
8952 | bool can_ssc = false; | |
1c1a24d2 | 8953 | bool using_ssc_source = false; |
13d83a67 JB |
8954 | |
8955 | /* We need to take the global config into account */ | |
b2784e15 | 8956 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
8957 | switch (encoder->type) { |
8958 | case INTEL_OUTPUT_LVDS: | |
8959 | has_panel = true; | |
8960 | has_lvds = true; | |
8961 | break; | |
8962 | case INTEL_OUTPUT_EDP: | |
8963 | has_panel = true; | |
2de6905f | 8964 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
8965 | has_cpu_edp = true; |
8966 | break; | |
6847d71b PZ |
8967 | default: |
8968 | break; | |
13d83a67 JB |
8969 | } |
8970 | } | |
8971 | ||
6e266956 | 8972 | if (HAS_PCH_IBX(dev_priv)) { |
41aa3448 | 8973 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
8974 | can_ssc = has_ck505; |
8975 | } else { | |
8976 | has_ck505 = false; | |
8977 | can_ssc = true; | |
8978 | } | |
8979 | ||
1c1a24d2 L |
8980 | /* Check if any DPLLs are using the SSC source */ |
8981 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
8982 | u32 temp = I915_READ(PCH_DPLL(i)); | |
8983 | ||
8984 | if (!(temp & DPLL_VCO_ENABLE)) | |
8985 | continue; | |
8986 | ||
8987 | if ((temp & PLL_REF_INPUT_MASK) == | |
8988 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
8989 | using_ssc_source = true; | |
8990 | break; | |
8991 | } | |
8992 | } | |
8993 | ||
8994 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n", | |
8995 | has_panel, has_lvds, has_ck505, using_ssc_source); | |
13d83a67 JB |
8996 | |
8997 | /* Ironlake: try to setup display ref clock before DPLL | |
8998 | * enabling. This is only under driver's control after | |
8999 | * PCH B stepping, previous chipset stepping should be | |
9000 | * ignoring this setting. | |
9001 | */ | |
74cfd7ac CW |
9002 | val = I915_READ(PCH_DREF_CONTROL); |
9003 | ||
9004 | /* As we must carefully and slowly disable/enable each source in turn, | |
9005 | * compute the final state we want first and check if we need to | |
9006 | * make any changes at all. | |
9007 | */ | |
9008 | final = val; | |
9009 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
9010 | if (has_ck505) | |
9011 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
9012 | else | |
9013 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
9014 | ||
8c07eb68 | 9015 | final &= ~DREF_SSC_SOURCE_MASK; |
74cfd7ac | 9016 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
8c07eb68 | 9017 | final &= ~DREF_SSC1_ENABLE; |
74cfd7ac CW |
9018 | |
9019 | if (has_panel) { | |
9020 | final |= DREF_SSC_SOURCE_ENABLE; | |
9021 | ||
9022 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
9023 | final |= DREF_SSC1_ENABLE; | |
9024 | ||
9025 | if (has_cpu_edp) { | |
9026 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
9027 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
9028 | else | |
9029 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
9030 | } else | |
9031 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
1c1a24d2 L |
9032 | } else if (using_ssc_source) { |
9033 | final |= DREF_SSC_SOURCE_ENABLE; | |
9034 | final |= DREF_SSC1_ENABLE; | |
74cfd7ac CW |
9035 | } |
9036 | ||
9037 | if (final == val) | |
9038 | return; | |
9039 | ||
13d83a67 | 9040 | /* Always enable nonspread source */ |
74cfd7ac | 9041 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 9042 | |
99eb6a01 | 9043 | if (has_ck505) |
74cfd7ac | 9044 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 9045 | else |
74cfd7ac | 9046 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 9047 | |
199e5d79 | 9048 | if (has_panel) { |
74cfd7ac CW |
9049 | val &= ~DREF_SSC_SOURCE_MASK; |
9050 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 9051 | |
199e5d79 | 9052 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 9053 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 9054 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 9055 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 9056 | } else |
74cfd7ac | 9057 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
9058 | |
9059 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 9060 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
9061 | POSTING_READ(PCH_DREF_CONTROL); |
9062 | udelay(200); | |
9063 | ||
74cfd7ac | 9064 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
9065 | |
9066 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 9067 | if (has_cpu_edp) { |
99eb6a01 | 9068 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 9069 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 9070 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 9071 | } else |
74cfd7ac | 9072 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 9073 | } else |
74cfd7ac | 9074 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 9075 | |
74cfd7ac | 9076 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
9077 | POSTING_READ(PCH_DREF_CONTROL); |
9078 | udelay(200); | |
9079 | } else { | |
1c1a24d2 | 9080 | DRM_DEBUG_KMS("Disabling CPU source output\n"); |
199e5d79 | 9081 | |
74cfd7ac | 9082 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
9083 | |
9084 | /* Turn off CPU output */ | |
74cfd7ac | 9085 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 9086 | |
74cfd7ac | 9087 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
9088 | POSTING_READ(PCH_DREF_CONTROL); |
9089 | udelay(200); | |
9090 | ||
1c1a24d2 L |
9091 | if (!using_ssc_source) { |
9092 | DRM_DEBUG_KMS("Disabling SSC source\n"); | |
199e5d79 | 9093 | |
1c1a24d2 L |
9094 | /* Turn off the SSC source */ |
9095 | val &= ~DREF_SSC_SOURCE_MASK; | |
9096 | val |= DREF_SSC_SOURCE_DISABLE; | |
f165d283 | 9097 | |
1c1a24d2 L |
9098 | /* Turn off SSC1 */ |
9099 | val &= ~DREF_SSC1_ENABLE; | |
9100 | ||
9101 | I915_WRITE(PCH_DREF_CONTROL, val); | |
9102 | POSTING_READ(PCH_DREF_CONTROL); | |
9103 | udelay(200); | |
9104 | } | |
13d83a67 | 9105 | } |
74cfd7ac CW |
9106 | |
9107 | BUG_ON(val != final); | |
13d83a67 JB |
9108 | } |
9109 | ||
f31f2d55 | 9110 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 9111 | { |
f31f2d55 | 9112 | uint32_t tmp; |
dde86e2d | 9113 | |
0ff066a9 PZ |
9114 | tmp = I915_READ(SOUTH_CHICKEN2); |
9115 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
9116 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 9117 | |
cf3598c2 ID |
9118 | if (wait_for_us(I915_READ(SOUTH_CHICKEN2) & |
9119 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
0ff066a9 | 9120 | DRM_ERROR("FDI mPHY reset assert timeout\n"); |
dde86e2d | 9121 | |
0ff066a9 PZ |
9122 | tmp = I915_READ(SOUTH_CHICKEN2); |
9123 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
9124 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 9125 | |
cf3598c2 ID |
9126 | if (wait_for_us((I915_READ(SOUTH_CHICKEN2) & |
9127 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
0ff066a9 | 9128 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); |
f31f2d55 PZ |
9129 | } |
9130 | ||
9131 | /* WaMPhyProgramming:hsw */ | |
9132 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
9133 | { | |
9134 | uint32_t tmp; | |
dde86e2d PZ |
9135 | |
9136 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
9137 | tmp &= ~(0xFF << 24); | |
9138 | tmp |= (0x12 << 24); | |
9139 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
9140 | ||
dde86e2d PZ |
9141 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
9142 | tmp |= (1 << 11); | |
9143 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
9144 | ||
9145 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
9146 | tmp |= (1 << 11); | |
9147 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
9148 | ||
dde86e2d PZ |
9149 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
9150 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
9151 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
9152 | ||
9153 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
9154 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
9155 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
9156 | ||
0ff066a9 PZ |
9157 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
9158 | tmp &= ~(7 << 13); | |
9159 | tmp |= (5 << 13); | |
9160 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 9161 | |
0ff066a9 PZ |
9162 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
9163 | tmp &= ~(7 << 13); | |
9164 | tmp |= (5 << 13); | |
9165 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
9166 | |
9167 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
9168 | tmp &= ~0xFF; | |
9169 | tmp |= 0x1C; | |
9170 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
9171 | ||
9172 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
9173 | tmp &= ~0xFF; | |
9174 | tmp |= 0x1C; | |
9175 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
9176 | ||
9177 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
9178 | tmp &= ~(0xFF << 16); | |
9179 | tmp |= (0x1C << 16); | |
9180 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
9181 | ||
9182 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
9183 | tmp &= ~(0xFF << 16); | |
9184 | tmp |= (0x1C << 16); | |
9185 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
9186 | ||
0ff066a9 PZ |
9187 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
9188 | tmp |= (1 << 27); | |
9189 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 9190 | |
0ff066a9 PZ |
9191 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
9192 | tmp |= (1 << 27); | |
9193 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 9194 | |
0ff066a9 PZ |
9195 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
9196 | tmp &= ~(0xF << 28); | |
9197 | tmp |= (4 << 28); | |
9198 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 9199 | |
0ff066a9 PZ |
9200 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
9201 | tmp &= ~(0xF << 28); | |
9202 | tmp |= (4 << 28); | |
9203 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
9204 | } |
9205 | ||
2fa86a1f PZ |
9206 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
9207 | * Programming" based on the parameters passed: | |
9208 | * - Sequence to enable CLKOUT_DP | |
9209 | * - Sequence to enable CLKOUT_DP without spread | |
9210 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
9211 | */ | |
9212 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
9213 | bool with_fdi) | |
f31f2d55 | 9214 | { |
fac5e23e | 9215 | struct drm_i915_private *dev_priv = to_i915(dev); |
2fa86a1f PZ |
9216 | uint32_t reg, tmp; |
9217 | ||
9218 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
9219 | with_spread = true; | |
4f8036a2 TU |
9220 | if (WARN(HAS_PCH_LPT_LP(dev_priv) && |
9221 | with_fdi, "LP PCH doesn't have FDI\n")) | |
2fa86a1f | 9222 | with_fdi = false; |
f31f2d55 | 9223 | |
a580516d | 9224 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
9225 | |
9226 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
9227 | tmp &= ~SBI_SSCCTL_DISABLE; | |
9228 | tmp |= SBI_SSCCTL_PATHALT; | |
9229 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
9230 | ||
9231 | udelay(24); | |
9232 | ||
2fa86a1f PZ |
9233 | if (with_spread) { |
9234 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
9235 | tmp &= ~SBI_SSCCTL_PATHALT; | |
9236 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 9237 | |
2fa86a1f PZ |
9238 | if (with_fdi) { |
9239 | lpt_reset_fdi_mphy(dev_priv); | |
9240 | lpt_program_fdi_mphy(dev_priv); | |
9241 | } | |
9242 | } | |
dde86e2d | 9243 | |
4f8036a2 | 9244 | reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
9245 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
9246 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
9247 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 9248 | |
a580516d | 9249 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
9250 | } |
9251 | ||
47701c3b PZ |
9252 | /* Sequence to disable CLKOUT_DP */ |
9253 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
9254 | { | |
fac5e23e | 9255 | struct drm_i915_private *dev_priv = to_i915(dev); |
47701c3b PZ |
9256 | uint32_t reg, tmp; |
9257 | ||
a580516d | 9258 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 9259 | |
4f8036a2 | 9260 | reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
9261 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
9262 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
9263 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
9264 | ||
9265 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
9266 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
9267 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
9268 | tmp |= SBI_SSCCTL_PATHALT; | |
9269 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
9270 | udelay(32); | |
9271 | } | |
9272 | tmp |= SBI_SSCCTL_DISABLE; | |
9273 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
9274 | } | |
9275 | ||
a580516d | 9276 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
9277 | } |
9278 | ||
f7be2c21 VS |
9279 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
9280 | ||
9281 | static const uint16_t sscdivintphase[] = { | |
9282 | [BEND_IDX( 50)] = 0x3B23, | |
9283 | [BEND_IDX( 45)] = 0x3B23, | |
9284 | [BEND_IDX( 40)] = 0x3C23, | |
9285 | [BEND_IDX( 35)] = 0x3C23, | |
9286 | [BEND_IDX( 30)] = 0x3D23, | |
9287 | [BEND_IDX( 25)] = 0x3D23, | |
9288 | [BEND_IDX( 20)] = 0x3E23, | |
9289 | [BEND_IDX( 15)] = 0x3E23, | |
9290 | [BEND_IDX( 10)] = 0x3F23, | |
9291 | [BEND_IDX( 5)] = 0x3F23, | |
9292 | [BEND_IDX( 0)] = 0x0025, | |
9293 | [BEND_IDX( -5)] = 0x0025, | |
9294 | [BEND_IDX(-10)] = 0x0125, | |
9295 | [BEND_IDX(-15)] = 0x0125, | |
9296 | [BEND_IDX(-20)] = 0x0225, | |
9297 | [BEND_IDX(-25)] = 0x0225, | |
9298 | [BEND_IDX(-30)] = 0x0325, | |
9299 | [BEND_IDX(-35)] = 0x0325, | |
9300 | [BEND_IDX(-40)] = 0x0425, | |
9301 | [BEND_IDX(-45)] = 0x0425, | |
9302 | [BEND_IDX(-50)] = 0x0525, | |
9303 | }; | |
9304 | ||
9305 | /* | |
9306 | * Bend CLKOUT_DP | |
9307 | * steps -50 to 50 inclusive, in steps of 5 | |
9308 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) | |
9309 | * change in clock period = -(steps / 10) * 5.787 ps | |
9310 | */ | |
9311 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) | |
9312 | { | |
9313 | uint32_t tmp; | |
9314 | int idx = BEND_IDX(steps); | |
9315 | ||
9316 | if (WARN_ON(steps % 5 != 0)) | |
9317 | return; | |
9318 | ||
9319 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) | |
9320 | return; | |
9321 | ||
9322 | mutex_lock(&dev_priv->sb_lock); | |
9323 | ||
9324 | if (steps % 10 != 0) | |
9325 | tmp = 0xAAAAAAAB; | |
9326 | else | |
9327 | tmp = 0x00000000; | |
9328 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); | |
9329 | ||
9330 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); | |
9331 | tmp &= 0xffff0000; | |
9332 | tmp |= sscdivintphase[idx]; | |
9333 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); | |
9334 | ||
9335 | mutex_unlock(&dev_priv->sb_lock); | |
9336 | } | |
9337 | ||
9338 | #undef BEND_IDX | |
9339 | ||
bf8fa3d3 PZ |
9340 | static void lpt_init_pch_refclk(struct drm_device *dev) |
9341 | { | |
bf8fa3d3 PZ |
9342 | struct intel_encoder *encoder; |
9343 | bool has_vga = false; | |
9344 | ||
b2784e15 | 9345 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
9346 | switch (encoder->type) { |
9347 | case INTEL_OUTPUT_ANALOG: | |
9348 | has_vga = true; | |
9349 | break; | |
6847d71b PZ |
9350 | default: |
9351 | break; | |
bf8fa3d3 PZ |
9352 | } |
9353 | } | |
9354 | ||
f7be2c21 VS |
9355 | if (has_vga) { |
9356 | lpt_bend_clkout_dp(to_i915(dev), 0); | |
47701c3b | 9357 | lpt_enable_clkout_dp(dev, true, true); |
f7be2c21 | 9358 | } else { |
47701c3b | 9359 | lpt_disable_clkout_dp(dev); |
f7be2c21 | 9360 | } |
bf8fa3d3 PZ |
9361 | } |
9362 | ||
dde86e2d PZ |
9363 | /* |
9364 | * Initialize reference clocks when the driver loads | |
9365 | */ | |
9366 | void intel_init_pch_refclk(struct drm_device *dev) | |
9367 | { | |
6e266956 TU |
9368 | struct drm_i915_private *dev_priv = to_i915(dev); |
9369 | ||
9370 | if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) | |
dde86e2d | 9371 | ironlake_init_pch_refclk(dev); |
6e266956 | 9372 | else if (HAS_PCH_LPT(dev_priv)) |
dde86e2d PZ |
9373 | lpt_init_pch_refclk(dev); |
9374 | } | |
9375 | ||
6ff93609 | 9376 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 9377 | { |
fac5e23e | 9378 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
79e53945 JB |
9379 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9380 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
9381 | uint32_t val; |
9382 | ||
78114071 | 9383 | val = 0; |
c8203565 | 9384 | |
6e3c9717 | 9385 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 9386 | case 18: |
dfd07d72 | 9387 | val |= PIPECONF_6BPC; |
c8203565 PZ |
9388 | break; |
9389 | case 24: | |
dfd07d72 | 9390 | val |= PIPECONF_8BPC; |
c8203565 PZ |
9391 | break; |
9392 | case 30: | |
dfd07d72 | 9393 | val |= PIPECONF_10BPC; |
c8203565 PZ |
9394 | break; |
9395 | case 36: | |
dfd07d72 | 9396 | val |= PIPECONF_12BPC; |
c8203565 PZ |
9397 | break; |
9398 | default: | |
cc769b62 PZ |
9399 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
9400 | BUG(); | |
c8203565 PZ |
9401 | } |
9402 | ||
6e3c9717 | 9403 | if (intel_crtc->config->dither) |
c8203565 PZ |
9404 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
9405 | ||
6e3c9717 | 9406 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
9407 | val |= PIPECONF_INTERLACED_ILK; |
9408 | else | |
9409 | val |= PIPECONF_PROGRESSIVE; | |
9410 | ||
6e3c9717 | 9411 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 9412 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 9413 | |
c8203565 PZ |
9414 | I915_WRITE(PIPECONF(pipe), val); |
9415 | POSTING_READ(PIPECONF(pipe)); | |
9416 | } | |
9417 | ||
6ff93609 | 9418 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 9419 | { |
fac5e23e | 9420 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
ee2b0b38 | 9421 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 9422 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
391bf048 | 9423 | u32 val = 0; |
ee2b0b38 | 9424 | |
391bf048 | 9425 | if (IS_HASWELL(dev_priv) && intel_crtc->config->dither) |
ee2b0b38 PZ |
9426 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
9427 | ||
6e3c9717 | 9428 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
9429 | val |= PIPECONF_INTERLACED_ILK; |
9430 | else | |
9431 | val |= PIPECONF_PROGRESSIVE; | |
9432 | ||
702e7a56 PZ |
9433 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
9434 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
391bf048 JN |
9435 | } |
9436 | ||
391bf048 JN |
9437 | static void haswell_set_pipemisc(struct drm_crtc *crtc) |
9438 | { | |
fac5e23e | 9439 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
391bf048 | 9440 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 9441 | |
391bf048 JN |
9442 | if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) { |
9443 | u32 val = 0; | |
756f85cf | 9444 | |
6e3c9717 | 9445 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
9446 | case 18: |
9447 | val |= PIPEMISC_DITHER_6_BPC; | |
9448 | break; | |
9449 | case 24: | |
9450 | val |= PIPEMISC_DITHER_8_BPC; | |
9451 | break; | |
9452 | case 30: | |
9453 | val |= PIPEMISC_DITHER_10_BPC; | |
9454 | break; | |
9455 | case 36: | |
9456 | val |= PIPEMISC_DITHER_12_BPC; | |
9457 | break; | |
9458 | default: | |
9459 | /* Case prevented by pipe_config_set_bpp. */ | |
9460 | BUG(); | |
9461 | } | |
9462 | ||
6e3c9717 | 9463 | if (intel_crtc->config->dither) |
756f85cf PZ |
9464 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
9465 | ||
391bf048 | 9466 | I915_WRITE(PIPEMISC(intel_crtc->pipe), val); |
756f85cf | 9467 | } |
ee2b0b38 PZ |
9468 | } |
9469 | ||
d4b1931c PZ |
9470 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
9471 | { | |
9472 | /* | |
9473 | * Account for spread spectrum to avoid | |
9474 | * oversubscribing the link. Max center spread | |
9475 | * is 2.5%; use 5% for safety's sake. | |
9476 | */ | |
9477 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 9478 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
9479 | } |
9480 | ||
7429e9d4 | 9481 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 9482 | { |
7429e9d4 | 9483 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
9484 | } |
9485 | ||
b75ca6f6 ACO |
9486 | static void ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
9487 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 9488 | struct dpll *reduced_clock) |
79e53945 | 9489 | { |
de13a2e3 | 9490 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 | 9491 | struct drm_device *dev = crtc->dev; |
fac5e23e | 9492 | struct drm_i915_private *dev_priv = to_i915(dev); |
b75ca6f6 | 9493 | u32 dpll, fp, fp2; |
3d6e9ee0 | 9494 | int factor; |
79e53945 | 9495 | |
c1858123 | 9496 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 | 9497 | factor = 21; |
3d6e9ee0 | 9498 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
8febb297 | 9499 | if ((intel_panel_use_ssc(dev_priv) && |
e91e941b | 9500 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
6e266956 | 9501 | (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev))) |
8febb297 | 9502 | factor = 25; |
190f68c5 | 9503 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 9504 | factor = 20; |
c1858123 | 9505 | |
b75ca6f6 ACO |
9506 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
9507 | ||
190f68c5 | 9508 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
b75ca6f6 ACO |
9509 | fp |= FP_CB_TUNE; |
9510 | ||
9511 | if (reduced_clock) { | |
9512 | fp2 = i9xx_dpll_compute_fp(reduced_clock); | |
2c07245f | 9513 | |
b75ca6f6 ACO |
9514 | if (reduced_clock->m < factor * reduced_clock->n) |
9515 | fp2 |= FP_CB_TUNE; | |
9516 | } else { | |
9517 | fp2 = fp; | |
9518 | } | |
9a7c7890 | 9519 | |
5eddb70b | 9520 | dpll = 0; |
2c07245f | 9521 | |
3d6e9ee0 | 9522 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a07d6787 EA |
9523 | dpll |= DPLLB_MODE_LVDS; |
9524 | else | |
9525 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 9526 | |
190f68c5 | 9527 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 9528 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f | 9529 | |
3d6e9ee0 VS |
9530 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
9531 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 9532 | dpll |= DPLL_SDVO_HIGH_SPEED; |
3d6e9ee0 | 9533 | |
37a5650b | 9534 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 9535 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 9536 | |
7d7f8633 VS |
9537 | /* |
9538 | * The high speed IO clock is only really required for | |
9539 | * SDVO/HDMI/DP, but we also enable it for CRT to make it | |
9540 | * possible to share the DPLL between CRT and HDMI. Enabling | |
9541 | * the clock needlessly does no real harm, except use up a | |
9542 | * bit of power potentially. | |
9543 | * | |
9544 | * We'll limit this to IVB with 3 pipes, since it has only two | |
9545 | * DPLLs and so DPLL sharing is the only way to get three pipes | |
9546 | * driving PCH ports at the same time. On SNB we could do this, | |
9547 | * and potentially avoid enabling the second DPLL, but it's not | |
9548 | * clear if it''s a win or loss power wise. No point in doing | |
9549 | * this on ILK at all since it has a fixed DPLL<->pipe mapping. | |
9550 | */ | |
9551 | if (INTEL_INFO(dev_priv)->num_pipes == 3 && | |
9552 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) | |
9553 | dpll |= DPLL_SDVO_HIGH_SPEED; | |
9554 | ||
a07d6787 | 9555 | /* compute bitmask from p1 value */ |
190f68c5 | 9556 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 9557 | /* also FPA1 */ |
190f68c5 | 9558 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 9559 | |
190f68c5 | 9560 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
9561 | case 5: |
9562 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
9563 | break; | |
9564 | case 7: | |
9565 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
9566 | break; | |
9567 | case 10: | |
9568 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
9569 | break; | |
9570 | case 14: | |
9571 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
9572 | break; | |
79e53945 JB |
9573 | } |
9574 | ||
3d6e9ee0 VS |
9575 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
9576 | intel_panel_use_ssc(dev_priv)) | |
43565a06 | 9577 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
9578 | else |
9579 | dpll |= PLL_REF_INPUT_DREFCLK; | |
9580 | ||
b75ca6f6 ACO |
9581 | dpll |= DPLL_VCO_ENABLE; |
9582 | ||
9583 | crtc_state->dpll_hw_state.dpll = dpll; | |
9584 | crtc_state->dpll_hw_state.fp0 = fp; | |
9585 | crtc_state->dpll_hw_state.fp1 = fp2; | |
de13a2e3 PZ |
9586 | } |
9587 | ||
190f68c5 ACO |
9588 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
9589 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 9590 | { |
997c030c | 9591 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 9592 | struct drm_i915_private *dev_priv = to_i915(dev); |
9e2c8475 | 9593 | struct dpll reduced_clock; |
7ed9f894 | 9594 | bool has_reduced_clock = false; |
e2b78267 | 9595 | struct intel_shared_dpll *pll; |
1b6f4958 | 9596 | const struct intel_limit *limit; |
997c030c | 9597 | int refclk = 120000; |
de13a2e3 | 9598 | |
dd3cd74a ACO |
9599 | memset(&crtc_state->dpll_hw_state, 0, |
9600 | sizeof(crtc_state->dpll_hw_state)); | |
9601 | ||
ded220e2 ACO |
9602 | crtc->lowfreq_avail = false; |
9603 | ||
9604 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ | |
9605 | if (!crtc_state->has_pch_encoder) | |
9606 | return 0; | |
79e53945 | 9607 | |
2d84d2b3 | 9608 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
997c030c ACO |
9609 | if (intel_panel_use_ssc(dev_priv)) { |
9610 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", | |
9611 | dev_priv->vbt.lvds_ssc_freq); | |
9612 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
9613 | } | |
9614 | ||
9615 | if (intel_is_dual_link_lvds(dev)) { | |
9616 | if (refclk == 100000) | |
9617 | limit = &intel_limits_ironlake_dual_lvds_100m; | |
9618 | else | |
9619 | limit = &intel_limits_ironlake_dual_lvds; | |
9620 | } else { | |
9621 | if (refclk == 100000) | |
9622 | limit = &intel_limits_ironlake_single_lvds_100m; | |
9623 | else | |
9624 | limit = &intel_limits_ironlake_single_lvds; | |
9625 | } | |
9626 | } else { | |
9627 | limit = &intel_limits_ironlake_dac; | |
9628 | } | |
9629 | ||
364ee29d | 9630 | if (!crtc_state->clock_set && |
997c030c ACO |
9631 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
9632 | refclk, NULL, &crtc_state->dpll)) { | |
364ee29d ACO |
9633 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
9634 | return -EINVAL; | |
f47709a9 | 9635 | } |
79e53945 | 9636 | |
b75ca6f6 ACO |
9637 | ironlake_compute_dpll(crtc, crtc_state, |
9638 | has_reduced_clock ? &reduced_clock : NULL); | |
66e985c0 | 9639 | |
ded220e2 ACO |
9640 | pll = intel_get_shared_dpll(crtc, crtc_state, NULL); |
9641 | if (pll == NULL) { | |
9642 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
9643 | pipe_name(crtc->pipe)); | |
9644 | return -EINVAL; | |
3fb37703 | 9645 | } |
79e53945 | 9646 | |
2d84d2b3 | 9647 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ded220e2 | 9648 | has_reduced_clock) |
c7653199 | 9649 | crtc->lowfreq_avail = true; |
e2b78267 | 9650 | |
c8f7a0db | 9651 | return 0; |
79e53945 JB |
9652 | } |
9653 | ||
eb14cb74 VS |
9654 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
9655 | struct intel_link_m_n *m_n) | |
9656 | { | |
9657 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9658 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb14cb74 VS |
9659 | enum pipe pipe = crtc->pipe; |
9660 | ||
9661 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
9662 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
9663 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9664 | & ~TU_SIZE_MASK; | |
9665 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
9666 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9667 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9668 | } | |
9669 | ||
9670 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
9671 | enum transcoder transcoder, | |
b95af8be VK |
9672 | struct intel_link_m_n *m_n, |
9673 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
9674 | { |
9675 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9676 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb14cb74 | 9677 | enum pipe pipe = crtc->pipe; |
72419203 | 9678 | |
eb14cb74 VS |
9679 | if (INTEL_INFO(dev)->gen >= 5) { |
9680 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
9681 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
9682 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
9683 | & ~TU_SIZE_MASK; | |
9684 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
9685 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
9686 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
9687 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
9688 | * gen < 8) and if DRRS is supported (to make sure the | |
9689 | * registers are not unnecessarily read). | |
9690 | */ | |
9691 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 9692 | crtc->config->has_drrs) { |
b95af8be VK |
9693 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
9694 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
9695 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
9696 | & ~TU_SIZE_MASK; | |
9697 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
9698 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
9699 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9700 | } | |
eb14cb74 VS |
9701 | } else { |
9702 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
9703 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
9704 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9705 | & ~TU_SIZE_MASK; | |
9706 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
9707 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9708 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9709 | } | |
9710 | } | |
9711 | ||
9712 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 9713 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 9714 | { |
681a8504 | 9715 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
9716 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
9717 | else | |
9718 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
9719 | &pipe_config->dp_m_n, |
9720 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 9721 | } |
72419203 | 9722 | |
eb14cb74 | 9723 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 9724 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
9725 | { |
9726 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 9727 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
9728 | } |
9729 | ||
bd2e244f | 9730 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9731 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
9732 | { |
9733 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9734 | struct drm_i915_private *dev_priv = to_i915(dev); |
a1b2278e CK |
9735 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
9736 | uint32_t ps_ctrl = 0; | |
9737 | int id = -1; | |
9738 | int i; | |
bd2e244f | 9739 | |
a1b2278e CK |
9740 | /* find scaler attached to this pipe */ |
9741 | for (i = 0; i < crtc->num_scalers; i++) { | |
9742 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
9743 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
9744 | id = i; | |
9745 | pipe_config->pch_pfit.enabled = true; | |
9746 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
9747 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
9748 | break; | |
9749 | } | |
9750 | } | |
bd2e244f | 9751 | |
a1b2278e CK |
9752 | scaler_state->scaler_id = id; |
9753 | if (id >= 0) { | |
9754 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
9755 | } else { | |
9756 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
9757 | } |
9758 | } | |
9759 | ||
5724dbd1 DL |
9760 | static void |
9761 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
9762 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
9763 | { |
9764 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9765 | struct drm_i915_private *dev_priv = to_i915(dev); |
40f46283 | 9766 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
9767 | int pipe = crtc->pipe; |
9768 | int fourcc, pixel_format; | |
6761dd31 | 9769 | unsigned int aligned_height; |
bc8d7dff | 9770 | struct drm_framebuffer *fb; |
1b842c89 | 9771 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 9772 | |
d9806c9f | 9773 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9774 | if (!intel_fb) { |
bc8d7dff DL |
9775 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9776 | return; | |
9777 | } | |
9778 | ||
1b842c89 DL |
9779 | fb = &intel_fb->base; |
9780 | ||
bc8d7dff | 9781 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
9782 | if (!(val & PLANE_CTL_ENABLE)) |
9783 | goto error; | |
9784 | ||
bc8d7dff DL |
9785 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
9786 | fourcc = skl_format_to_fourcc(pixel_format, | |
9787 | val & PLANE_CTL_ORDER_RGBX, | |
9788 | val & PLANE_CTL_ALPHA_MASK); | |
9789 | fb->pixel_format = fourcc; | |
9790 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
9791 | ||
40f46283 DL |
9792 | tiling = val & PLANE_CTL_TILED_MASK; |
9793 | switch (tiling) { | |
9794 | case PLANE_CTL_TILED_LINEAR: | |
9795 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
9796 | break; | |
9797 | case PLANE_CTL_TILED_X: | |
9798 | plane_config->tiling = I915_TILING_X; | |
9799 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
9800 | break; | |
9801 | case PLANE_CTL_TILED_Y: | |
9802 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
9803 | break; | |
9804 | case PLANE_CTL_TILED_YF: | |
9805 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
9806 | break; | |
9807 | default: | |
9808 | MISSING_CASE(tiling); | |
9809 | goto error; | |
9810 | } | |
9811 | ||
bc8d7dff DL |
9812 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
9813 | plane_config->base = base; | |
9814 | ||
9815 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
9816 | ||
9817 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
9818 | fb->height = ((val >> 16) & 0xfff) + 1; | |
9819 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
9820 | ||
9821 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
7b49f948 | 9822 | stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
40f46283 | 9823 | fb->pixel_format); |
bc8d7dff DL |
9824 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
9825 | ||
9826 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
9827 | fb->pixel_format, |
9828 | fb->modifier[0]); | |
bc8d7dff | 9829 | |
f37b5c2b | 9830 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
9831 | |
9832 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
9833 | pipe_name(pipe), fb->width, fb->height, | |
9834 | fb->bits_per_pixel, base, fb->pitches[0], | |
9835 | plane_config->size); | |
9836 | ||
2d14030b | 9837 | plane_config->fb = intel_fb; |
bc8d7dff DL |
9838 | return; |
9839 | ||
9840 | error: | |
d1a3a036 | 9841 | kfree(intel_fb); |
bc8d7dff DL |
9842 | } |
9843 | ||
2fa2fe9a | 9844 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9845 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
9846 | { |
9847 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9848 | struct drm_i915_private *dev_priv = to_i915(dev); |
2fa2fe9a DV |
9849 | uint32_t tmp; |
9850 | ||
9851 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
9852 | ||
9853 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 9854 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
9855 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
9856 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
9857 | |
9858 | /* We currently do not free assignements of panel fitters on | |
9859 | * ivb/hsw (since we don't use the higher upscaling modes which | |
9860 | * differentiates them) so just WARN about this case for now. */ | |
5db94019 | 9861 | if (IS_GEN7(dev_priv)) { |
cb8b2a30 DV |
9862 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != |
9863 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
9864 | } | |
2fa2fe9a | 9865 | } |
79e53945 JB |
9866 | } |
9867 | ||
5724dbd1 DL |
9868 | static void |
9869 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
9870 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
9871 | { |
9872 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9873 | struct drm_i915_private *dev_priv = to_i915(dev); |
4c6baa59 | 9874 | u32 val, base, offset; |
aeee5a49 | 9875 | int pipe = crtc->pipe; |
4c6baa59 | 9876 | int fourcc, pixel_format; |
6761dd31 | 9877 | unsigned int aligned_height; |
b113d5ee | 9878 | struct drm_framebuffer *fb; |
1b842c89 | 9879 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 9880 | |
42a7b088 DL |
9881 | val = I915_READ(DSPCNTR(pipe)); |
9882 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
9883 | return; | |
9884 | ||
d9806c9f | 9885 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9886 | if (!intel_fb) { |
4c6baa59 JB |
9887 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9888 | return; | |
9889 | } | |
9890 | ||
1b842c89 DL |
9891 | fb = &intel_fb->base; |
9892 | ||
18c5247e DV |
9893 | if (INTEL_INFO(dev)->gen >= 4) { |
9894 | if (val & DISPPLANE_TILED) { | |
49af449b | 9895 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
9896 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
9897 | } | |
9898 | } | |
4c6baa59 JB |
9899 | |
9900 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 9901 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
9902 | fb->pixel_format = fourcc; |
9903 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 9904 | |
aeee5a49 | 9905 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
8652744b | 9906 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
aeee5a49 | 9907 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 9908 | } else { |
49af449b | 9909 | if (plane_config->tiling) |
aeee5a49 | 9910 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 9911 | else |
aeee5a49 | 9912 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
9913 | } |
9914 | plane_config->base = base; | |
9915 | ||
9916 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
9917 | fb->width = ((val >> 16) & 0xfff) + 1; |
9918 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
9919 | |
9920 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 9921 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 9922 | |
b113d5ee | 9923 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
9924 | fb->pixel_format, |
9925 | fb->modifier[0]); | |
4c6baa59 | 9926 | |
f37b5c2b | 9927 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 9928 | |
2844a921 DL |
9929 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
9930 | pipe_name(pipe), fb->width, fb->height, | |
9931 | fb->bits_per_pixel, base, fb->pitches[0], | |
9932 | plane_config->size); | |
b113d5ee | 9933 | |
2d14030b | 9934 | plane_config->fb = intel_fb; |
4c6baa59 JB |
9935 | } |
9936 | ||
0e8ffe1b | 9937 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9938 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9939 | { |
9940 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9941 | struct drm_i915_private *dev_priv = to_i915(dev); |
1729050e | 9942 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 9943 | uint32_t tmp; |
1729050e | 9944 | bool ret; |
0e8ffe1b | 9945 | |
1729050e ID |
9946 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
9947 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
930e8c9e PZ |
9948 | return false; |
9949 | ||
e143a21c | 9950 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 9951 | pipe_config->shared_dpll = NULL; |
eccb140b | 9952 | |
1729050e | 9953 | ret = false; |
0e8ffe1b DV |
9954 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
9955 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 9956 | goto out; |
0e8ffe1b | 9957 | |
42571aef VS |
9958 | switch (tmp & PIPECONF_BPC_MASK) { |
9959 | case PIPECONF_6BPC: | |
9960 | pipe_config->pipe_bpp = 18; | |
9961 | break; | |
9962 | case PIPECONF_8BPC: | |
9963 | pipe_config->pipe_bpp = 24; | |
9964 | break; | |
9965 | case PIPECONF_10BPC: | |
9966 | pipe_config->pipe_bpp = 30; | |
9967 | break; | |
9968 | case PIPECONF_12BPC: | |
9969 | pipe_config->pipe_bpp = 36; | |
9970 | break; | |
9971 | default: | |
9972 | break; | |
9973 | } | |
9974 | ||
b5a9fa09 DV |
9975 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
9976 | pipe_config->limited_color_range = true; | |
9977 | ||
ab9412ba | 9978 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 | 9979 | struct intel_shared_dpll *pll; |
8106ddbd | 9980 | enum intel_dpll_id pll_id; |
66e985c0 | 9981 | |
88adfff1 DV |
9982 | pipe_config->has_pch_encoder = true; |
9983 | ||
627eb5a3 DV |
9984 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
9985 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9986 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
9987 | |
9988 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 9989 | |
2d1fe073 | 9990 | if (HAS_PCH_IBX(dev_priv)) { |
d9a7bc67 ID |
9991 | /* |
9992 | * The pipe->pch transcoder and pch transcoder->pll | |
9993 | * mapping is fixed. | |
9994 | */ | |
8106ddbd | 9995 | pll_id = (enum intel_dpll_id) crtc->pipe; |
c0d43d62 DV |
9996 | } else { |
9997 | tmp = I915_READ(PCH_DPLL_SEL); | |
9998 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
8106ddbd | 9999 | pll_id = DPLL_ID_PCH_PLL_B; |
c0d43d62 | 10000 | else |
8106ddbd | 10001 | pll_id= DPLL_ID_PCH_PLL_A; |
c0d43d62 | 10002 | } |
66e985c0 | 10003 | |
8106ddbd ACO |
10004 | pipe_config->shared_dpll = |
10005 | intel_get_shared_dpll_by_id(dev_priv, pll_id); | |
10006 | pll = pipe_config->shared_dpll; | |
66e985c0 | 10007 | |
2edd6443 ACO |
10008 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
10009 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
10010 | |
10011 | tmp = pipe_config->dpll_hw_state.dpll; | |
10012 | pipe_config->pixel_multiplier = | |
10013 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
10014 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
10015 | |
10016 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
10017 | } else { |
10018 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
10019 | } |
10020 | ||
1bd1bd80 | 10021 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 10022 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 10023 | |
2fa2fe9a DV |
10024 | ironlake_get_pfit_config(crtc, pipe_config); |
10025 | ||
1729050e ID |
10026 | ret = true; |
10027 | ||
10028 | out: | |
10029 | intel_display_power_put(dev_priv, power_domain); | |
10030 | ||
10031 | return ret; | |
0e8ffe1b DV |
10032 | } |
10033 | ||
be256dc7 PZ |
10034 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
10035 | { | |
91c8a326 | 10036 | struct drm_device *dev = &dev_priv->drm; |
be256dc7 | 10037 | struct intel_crtc *crtc; |
be256dc7 | 10038 | |
d3fcc808 | 10039 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 10040 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
10041 | pipe_name(crtc->pipe)); |
10042 | ||
e2c719b7 RC |
10043 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
10044 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
01403de3 VS |
10045 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
10046 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
44cb734c | 10047 | I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n"); |
e2c719b7 | 10048 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, |
be256dc7 | 10049 | "CPU PWM1 enabled\n"); |
772c2a51 | 10050 | if (IS_HASWELL(dev_priv)) |
e2c719b7 | 10051 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 10052 | "CPU PWM2 enabled\n"); |
e2c719b7 | 10053 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 10054 | "PCH PWM1 enabled\n"); |
e2c719b7 | 10055 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 10056 | "Utility pin enabled\n"); |
e2c719b7 | 10057 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 10058 | |
9926ada1 PZ |
10059 | /* |
10060 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
10061 | * interrupts remain enabled. We used to check for that, but since it's | |
10062 | * gen-specific and since we only disable LCPLL after we fully disable | |
10063 | * the interrupts, the check below should be enough. | |
10064 | */ | |
e2c719b7 | 10065 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
10066 | } |
10067 | ||
9ccd5aeb PZ |
10068 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
10069 | { | |
772c2a51 | 10070 | if (IS_HASWELL(dev_priv)) |
9ccd5aeb PZ |
10071 | return I915_READ(D_COMP_HSW); |
10072 | else | |
10073 | return I915_READ(D_COMP_BDW); | |
10074 | } | |
10075 | ||
3c4c9b81 PZ |
10076 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
10077 | { | |
772c2a51 | 10078 | if (IS_HASWELL(dev_priv)) { |
3c4c9b81 PZ |
10079 | mutex_lock(&dev_priv->rps.hw_lock); |
10080 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
10081 | val)) | |
79cf219a | 10082 | DRM_DEBUG_KMS("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
10083 | mutex_unlock(&dev_priv->rps.hw_lock); |
10084 | } else { | |
9ccd5aeb PZ |
10085 | I915_WRITE(D_COMP_BDW, val); |
10086 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 10087 | } |
be256dc7 PZ |
10088 | } |
10089 | ||
10090 | /* | |
10091 | * This function implements pieces of two sequences from BSpec: | |
10092 | * - Sequence for display software to disable LCPLL | |
10093 | * - Sequence for display software to allow package C8+ | |
10094 | * The steps implemented here are just the steps that actually touch the LCPLL | |
10095 | * register. Callers should take care of disabling all the display engine | |
10096 | * functions, doing the mode unset, fixing interrupts, etc. | |
10097 | */ | |
6ff58d53 PZ |
10098 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
10099 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
10100 | { |
10101 | uint32_t val; | |
10102 | ||
10103 | assert_can_disable_lcpll(dev_priv); | |
10104 | ||
10105 | val = I915_READ(LCPLL_CTL); | |
10106 | ||
10107 | if (switch_to_fclk) { | |
10108 | val |= LCPLL_CD_SOURCE_FCLK; | |
10109 | I915_WRITE(LCPLL_CTL, val); | |
10110 | ||
f53dd63f ID |
10111 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
10112 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
be256dc7 PZ |
10113 | DRM_ERROR("Switching to FCLK failed\n"); |
10114 | ||
10115 | val = I915_READ(LCPLL_CTL); | |
10116 | } | |
10117 | ||
10118 | val |= LCPLL_PLL_DISABLE; | |
10119 | I915_WRITE(LCPLL_CTL, val); | |
10120 | POSTING_READ(LCPLL_CTL); | |
10121 | ||
24d8441d | 10122 | if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1)) |
be256dc7 PZ |
10123 | DRM_ERROR("LCPLL still locked\n"); |
10124 | ||
9ccd5aeb | 10125 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 10126 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 10127 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
10128 | ndelay(100); |
10129 | ||
9ccd5aeb PZ |
10130 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
10131 | 1)) | |
be256dc7 PZ |
10132 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
10133 | ||
10134 | if (allow_power_down) { | |
10135 | val = I915_READ(LCPLL_CTL); | |
10136 | val |= LCPLL_POWER_DOWN_ALLOW; | |
10137 | I915_WRITE(LCPLL_CTL, val); | |
10138 | POSTING_READ(LCPLL_CTL); | |
10139 | } | |
10140 | } | |
10141 | ||
10142 | /* | |
10143 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
10144 | * source. | |
10145 | */ | |
6ff58d53 | 10146 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
10147 | { |
10148 | uint32_t val; | |
10149 | ||
10150 | val = I915_READ(LCPLL_CTL); | |
10151 | ||
10152 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
10153 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
10154 | return; | |
10155 | ||
a8a8bd54 PZ |
10156 | /* |
10157 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
10158 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 10159 | */ |
59bad947 | 10160 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 10161 | |
be256dc7 PZ |
10162 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
10163 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
10164 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 10165 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
10166 | } |
10167 | ||
9ccd5aeb | 10168 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
10169 | val |= D_COMP_COMP_FORCE; |
10170 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 10171 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
10172 | |
10173 | val = I915_READ(LCPLL_CTL); | |
10174 | val &= ~LCPLL_PLL_DISABLE; | |
10175 | I915_WRITE(LCPLL_CTL, val); | |
10176 | ||
93220c08 CW |
10177 | if (intel_wait_for_register(dev_priv, |
10178 | LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, | |
10179 | 5)) | |
be256dc7 PZ |
10180 | DRM_ERROR("LCPLL not locked yet\n"); |
10181 | ||
10182 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
10183 | val = I915_READ(LCPLL_CTL); | |
10184 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
10185 | I915_WRITE(LCPLL_CTL, val); | |
10186 | ||
f53dd63f ID |
10187 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
10188 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
be256dc7 PZ |
10189 | DRM_ERROR("Switching back to LCPLL failed\n"); |
10190 | } | |
215733fa | 10191 | |
59bad947 | 10192 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
91c8a326 | 10193 | intel_update_cdclk(&dev_priv->drm); |
be256dc7 PZ |
10194 | } |
10195 | ||
765dab67 PZ |
10196 | /* |
10197 | * Package states C8 and deeper are really deep PC states that can only be | |
10198 | * reached when all the devices on the system allow it, so even if the graphics | |
10199 | * device allows PC8+, it doesn't mean the system will actually get to these | |
10200 | * states. Our driver only allows PC8+ when going into runtime PM. | |
10201 | * | |
10202 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
10203 | * well is disabled and most interrupts are disabled, and these are also | |
10204 | * requirements for runtime PM. When these conditions are met, we manually do | |
10205 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
10206 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
10207 | * hang the machine. | |
10208 | * | |
10209 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
10210 | * the state of some registers, so when we come back from PC8+ we need to | |
10211 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
10212 | * need to take care of the registers kept by RC6. Notice that this happens even | |
10213 | * if we don't put the device in PCI D3 state (which is what currently happens | |
10214 | * because of the runtime PM support). | |
10215 | * | |
10216 | * For more, read "Display Sequences for Package C8" on the hardware | |
10217 | * documentation. | |
10218 | */ | |
a14cb6fc | 10219 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 10220 | { |
91c8a326 | 10221 | struct drm_device *dev = &dev_priv->drm; |
c67a470b PZ |
10222 | uint32_t val; |
10223 | ||
c67a470b PZ |
10224 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
10225 | ||
4f8036a2 | 10226 | if (HAS_PCH_LPT_LP(dev_priv)) { |
c67a470b PZ |
10227 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
10228 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
10229 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
10230 | } | |
10231 | ||
10232 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
10233 | hsw_disable_lcpll(dev_priv, true, true); |
10234 | } | |
10235 | ||
a14cb6fc | 10236 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 10237 | { |
91c8a326 | 10238 | struct drm_device *dev = &dev_priv->drm; |
c67a470b PZ |
10239 | uint32_t val; |
10240 | ||
c67a470b PZ |
10241 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
10242 | ||
10243 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
10244 | lpt_init_pch_refclk(dev); |
10245 | ||
4f8036a2 | 10246 | if (HAS_PCH_LPT_LP(dev_priv)) { |
c67a470b PZ |
10247 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
10248 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
10249 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
10250 | } | |
c67a470b PZ |
10251 | } |
10252 | ||
324513c0 | 10253 | static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
f8437dd1 | 10254 | { |
a821fc46 | 10255 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
10256 | struct intel_atomic_state *old_intel_state = |
10257 | to_intel_atomic_state(old_state); | |
10258 | unsigned int req_cdclk = old_intel_state->dev_cdclk; | |
f8437dd1 | 10259 | |
324513c0 | 10260 | bxt_set_cdclk(to_i915(dev), req_cdclk); |
f8437dd1 VK |
10261 | } |
10262 | ||
b432e5cf | 10263 | /* compute the max rate for new configuration */ |
27c329ed | 10264 | static int ilk_max_pixel_rate(struct drm_atomic_state *state) |
b432e5cf | 10265 | { |
565602d7 | 10266 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 10267 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
565602d7 ML |
10268 | struct drm_crtc *crtc; |
10269 | struct drm_crtc_state *cstate; | |
27c329ed | 10270 | struct intel_crtc_state *crtc_state; |
565602d7 ML |
10271 | unsigned max_pixel_rate = 0, i; |
10272 | enum pipe pipe; | |
b432e5cf | 10273 | |
565602d7 ML |
10274 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
10275 | sizeof(intel_state->min_pixclk)); | |
27c329ed | 10276 | |
565602d7 ML |
10277 | for_each_crtc_in_state(state, crtc, cstate, i) { |
10278 | int pixel_rate; | |
27c329ed | 10279 | |
565602d7 ML |
10280 | crtc_state = to_intel_crtc_state(cstate); |
10281 | if (!crtc_state->base.enable) { | |
10282 | intel_state->min_pixclk[i] = 0; | |
b432e5cf | 10283 | continue; |
565602d7 | 10284 | } |
b432e5cf | 10285 | |
27c329ed | 10286 | pixel_rate = ilk_pipe_pixel_rate(crtc_state); |
b432e5cf VS |
10287 | |
10288 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
565602d7 | 10289 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) |
b432e5cf VS |
10290 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); |
10291 | ||
565602d7 | 10292 | intel_state->min_pixclk[i] = pixel_rate; |
b432e5cf VS |
10293 | } |
10294 | ||
565602d7 ML |
10295 | for_each_pipe(dev_priv, pipe) |
10296 | max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate); | |
10297 | ||
b432e5cf VS |
10298 | return max_pixel_rate; |
10299 | } | |
10300 | ||
10301 | static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) | |
10302 | { | |
fac5e23e | 10303 | struct drm_i915_private *dev_priv = to_i915(dev); |
b432e5cf VS |
10304 | uint32_t val, data; |
10305 | int ret; | |
10306 | ||
10307 | if (WARN((I915_READ(LCPLL_CTL) & | |
10308 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | | |
10309 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | | |
10310 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | | |
10311 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, | |
10312 | "trying to change cdclk frequency with cdclk not enabled\n")) | |
10313 | return; | |
10314 | ||
10315 | mutex_lock(&dev_priv->rps.hw_lock); | |
10316 | ret = sandybridge_pcode_write(dev_priv, | |
10317 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); | |
10318 | mutex_unlock(&dev_priv->rps.hw_lock); | |
10319 | if (ret) { | |
10320 | DRM_ERROR("failed to inform pcode about cdclk change\n"); | |
10321 | return; | |
10322 | } | |
10323 | ||
10324 | val = I915_READ(LCPLL_CTL); | |
10325 | val |= LCPLL_CD_SOURCE_FCLK; | |
10326 | I915_WRITE(LCPLL_CTL, val); | |
10327 | ||
5ba00178 TU |
10328 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
10329 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
b432e5cf VS |
10330 | DRM_ERROR("Switching to FCLK failed\n"); |
10331 | ||
10332 | val = I915_READ(LCPLL_CTL); | |
10333 | val &= ~LCPLL_CLK_FREQ_MASK; | |
10334 | ||
10335 | switch (cdclk) { | |
10336 | case 450000: | |
10337 | val |= LCPLL_CLK_FREQ_450; | |
10338 | data = 0; | |
10339 | break; | |
10340 | case 540000: | |
10341 | val |= LCPLL_CLK_FREQ_54O_BDW; | |
10342 | data = 1; | |
10343 | break; | |
10344 | case 337500: | |
10345 | val |= LCPLL_CLK_FREQ_337_5_BDW; | |
10346 | data = 2; | |
10347 | break; | |
10348 | case 675000: | |
10349 | val |= LCPLL_CLK_FREQ_675_BDW; | |
10350 | data = 3; | |
10351 | break; | |
10352 | default: | |
10353 | WARN(1, "invalid cdclk frequency\n"); | |
10354 | return; | |
10355 | } | |
10356 | ||
10357 | I915_WRITE(LCPLL_CTL, val); | |
10358 | ||
10359 | val = I915_READ(LCPLL_CTL); | |
10360 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
10361 | I915_WRITE(LCPLL_CTL, val); | |
10362 | ||
5ba00178 TU |
10363 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
10364 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
b432e5cf VS |
10365 | DRM_ERROR("Switching back to LCPLL failed\n"); |
10366 | ||
10367 | mutex_lock(&dev_priv->rps.hw_lock); | |
10368 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); | |
10369 | mutex_unlock(&dev_priv->rps.hw_lock); | |
10370 | ||
7f1052a8 VS |
10371 | I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1); |
10372 | ||
b432e5cf VS |
10373 | intel_update_cdclk(dev); |
10374 | ||
10375 | WARN(cdclk != dev_priv->cdclk_freq, | |
10376 | "cdclk requested %d kHz but got %d kHz\n", | |
10377 | cdclk, dev_priv->cdclk_freq); | |
10378 | } | |
10379 | ||
587c7914 VS |
10380 | static int broadwell_calc_cdclk(int max_pixclk) |
10381 | { | |
10382 | if (max_pixclk > 540000) | |
10383 | return 675000; | |
10384 | else if (max_pixclk > 450000) | |
10385 | return 540000; | |
10386 | else if (max_pixclk > 337500) | |
10387 | return 450000; | |
10388 | else | |
10389 | return 337500; | |
10390 | } | |
10391 | ||
27c329ed | 10392 | static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state) |
b432e5cf | 10393 | { |
27c329ed | 10394 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
1a617b77 | 10395 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
27c329ed | 10396 | int max_pixclk = ilk_max_pixel_rate(state); |
b432e5cf VS |
10397 | int cdclk; |
10398 | ||
10399 | /* | |
10400 | * FIXME should also account for plane ratio | |
10401 | * once 64bpp pixel formats are supported. | |
10402 | */ | |
587c7914 | 10403 | cdclk = broadwell_calc_cdclk(max_pixclk); |
b432e5cf | 10404 | |
b432e5cf | 10405 | if (cdclk > dev_priv->max_cdclk_freq) { |
63ba534e ML |
10406 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", |
10407 | cdclk, dev_priv->max_cdclk_freq); | |
10408 | return -EINVAL; | |
b432e5cf VS |
10409 | } |
10410 | ||
1a617b77 ML |
10411 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; |
10412 | if (!intel_state->active_crtcs) | |
587c7914 | 10413 | intel_state->dev_cdclk = broadwell_calc_cdclk(0); |
b432e5cf VS |
10414 | |
10415 | return 0; | |
10416 | } | |
10417 | ||
27c329ed | 10418 | static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
b432e5cf | 10419 | { |
27c329ed | 10420 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
10421 | struct intel_atomic_state *old_intel_state = |
10422 | to_intel_atomic_state(old_state); | |
10423 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
b432e5cf | 10424 | |
27c329ed | 10425 | broadwell_set_cdclk(dev, req_cdclk); |
b432e5cf VS |
10426 | } |
10427 | ||
c89e39f3 CT |
10428 | static int skl_modeset_calc_cdclk(struct drm_atomic_state *state) |
10429 | { | |
10430 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
10431 | struct drm_i915_private *dev_priv = to_i915(state->dev); | |
10432 | const int max_pixclk = ilk_max_pixel_rate(state); | |
a8ca4934 | 10433 | int vco = intel_state->cdclk_pll_vco; |
c89e39f3 CT |
10434 | int cdclk; |
10435 | ||
10436 | /* | |
10437 | * FIXME should also account for plane ratio | |
10438 | * once 64bpp pixel formats are supported. | |
10439 | */ | |
a8ca4934 | 10440 | cdclk = skl_calc_cdclk(max_pixclk, vco); |
c89e39f3 CT |
10441 | |
10442 | /* | |
10443 | * FIXME move the cdclk caclulation to | |
10444 | * compute_config() so we can fail gracegully. | |
10445 | */ | |
10446 | if (cdclk > dev_priv->max_cdclk_freq) { | |
10447 | DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n", | |
10448 | cdclk, dev_priv->max_cdclk_freq); | |
10449 | cdclk = dev_priv->max_cdclk_freq; | |
10450 | } | |
10451 | ||
10452 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; | |
10453 | if (!intel_state->active_crtcs) | |
a8ca4934 | 10454 | intel_state->dev_cdclk = skl_calc_cdclk(0, vco); |
c89e39f3 CT |
10455 | |
10456 | return 0; | |
10457 | } | |
10458 | ||
10459 | static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state) | |
10460 | { | |
1cd593e0 VS |
10461 | struct drm_i915_private *dev_priv = to_i915(old_state->dev); |
10462 | struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state); | |
10463 | unsigned int req_cdclk = intel_state->dev_cdclk; | |
10464 | unsigned int req_vco = intel_state->cdclk_pll_vco; | |
c89e39f3 | 10465 | |
1cd593e0 | 10466 | skl_set_cdclk(dev_priv, req_cdclk, req_vco); |
c89e39f3 CT |
10467 | } |
10468 | ||
190f68c5 ACO |
10469 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
10470 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 10471 | { |
d7edc4e5 | 10472 | if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) { |
af3997b5 MK |
10473 | if (!intel_ddi_pll_select(crtc, crtc_state)) |
10474 | return -EINVAL; | |
10475 | } | |
716c2e55 | 10476 | |
c7653199 | 10477 | crtc->lowfreq_avail = false; |
644cef34 | 10478 | |
c8f7a0db | 10479 | return 0; |
79e53945 JB |
10480 | } |
10481 | ||
3760b59c S |
10482 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
10483 | enum port port, | |
10484 | struct intel_crtc_state *pipe_config) | |
10485 | { | |
8106ddbd ACO |
10486 | enum intel_dpll_id id; |
10487 | ||
3760b59c S |
10488 | switch (port) { |
10489 | case PORT_A: | |
08250c4b | 10490 | id = DPLL_ID_SKL_DPLL0; |
3760b59c S |
10491 | break; |
10492 | case PORT_B: | |
08250c4b | 10493 | id = DPLL_ID_SKL_DPLL1; |
3760b59c S |
10494 | break; |
10495 | case PORT_C: | |
08250c4b | 10496 | id = DPLL_ID_SKL_DPLL2; |
3760b59c S |
10497 | break; |
10498 | default: | |
10499 | DRM_ERROR("Incorrect port type\n"); | |
8106ddbd | 10500 | return; |
3760b59c | 10501 | } |
8106ddbd ACO |
10502 | |
10503 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
3760b59c S |
10504 | } |
10505 | ||
96b7dfb7 S |
10506 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
10507 | enum port port, | |
5cec258b | 10508 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 10509 | { |
8106ddbd | 10510 | enum intel_dpll_id id; |
a3c988ea | 10511 | u32 temp; |
96b7dfb7 S |
10512 | |
10513 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
c856052a | 10514 | id = temp >> (port * 3 + 1); |
96b7dfb7 | 10515 | |
c856052a | 10516 | if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3)) |
8106ddbd | 10517 | return; |
8106ddbd ACO |
10518 | |
10519 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
96b7dfb7 S |
10520 | } |
10521 | ||
7d2c8175 DL |
10522 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
10523 | enum port port, | |
5cec258b | 10524 | struct intel_crtc_state *pipe_config) |
7d2c8175 | 10525 | { |
8106ddbd | 10526 | enum intel_dpll_id id; |
c856052a | 10527 | uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); |
8106ddbd | 10528 | |
c856052a | 10529 | switch (ddi_pll_sel) { |
7d2c8175 | 10530 | case PORT_CLK_SEL_WRPLL1: |
8106ddbd | 10531 | id = DPLL_ID_WRPLL1; |
7d2c8175 DL |
10532 | break; |
10533 | case PORT_CLK_SEL_WRPLL2: | |
8106ddbd | 10534 | id = DPLL_ID_WRPLL2; |
7d2c8175 | 10535 | break; |
00490c22 | 10536 | case PORT_CLK_SEL_SPLL: |
8106ddbd | 10537 | id = DPLL_ID_SPLL; |
79bd23da | 10538 | break; |
9d16da65 ACO |
10539 | case PORT_CLK_SEL_LCPLL_810: |
10540 | id = DPLL_ID_LCPLL_810; | |
10541 | break; | |
10542 | case PORT_CLK_SEL_LCPLL_1350: | |
10543 | id = DPLL_ID_LCPLL_1350; | |
10544 | break; | |
10545 | case PORT_CLK_SEL_LCPLL_2700: | |
10546 | id = DPLL_ID_LCPLL_2700; | |
10547 | break; | |
8106ddbd | 10548 | default: |
c856052a | 10549 | MISSING_CASE(ddi_pll_sel); |
8106ddbd ACO |
10550 | /* fall through */ |
10551 | case PORT_CLK_SEL_NONE: | |
8106ddbd | 10552 | return; |
7d2c8175 | 10553 | } |
8106ddbd ACO |
10554 | |
10555 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
7d2c8175 DL |
10556 | } |
10557 | ||
cf30429e JN |
10558 | static bool hsw_get_transcoder_state(struct intel_crtc *crtc, |
10559 | struct intel_crtc_state *pipe_config, | |
10560 | unsigned long *power_domain_mask) | |
10561 | { | |
10562 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10563 | struct drm_i915_private *dev_priv = to_i915(dev); |
cf30429e JN |
10564 | enum intel_display_power_domain power_domain; |
10565 | u32 tmp; | |
10566 | ||
d9a7bc67 ID |
10567 | /* |
10568 | * The pipe->transcoder mapping is fixed with the exception of the eDP | |
10569 | * transcoder handled below. | |
10570 | */ | |
cf30429e JN |
10571 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
10572 | ||
10573 | /* | |
10574 | * XXX: Do intel_display_power_get_if_enabled before reading this (for | |
10575 | * consistency and less surprising code; it's in always on power). | |
10576 | */ | |
10577 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
10578 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
10579 | enum pipe trans_edp_pipe; | |
10580 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
10581 | default: | |
10582 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
10583 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
10584 | case TRANS_DDI_EDP_INPUT_A_ON: | |
10585 | trans_edp_pipe = PIPE_A; | |
10586 | break; | |
10587 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
10588 | trans_edp_pipe = PIPE_B; | |
10589 | break; | |
10590 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
10591 | trans_edp_pipe = PIPE_C; | |
10592 | break; | |
10593 | } | |
10594 | ||
10595 | if (trans_edp_pipe == crtc->pipe) | |
10596 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
10597 | } | |
10598 | ||
10599 | power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); | |
10600 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
10601 | return false; | |
10602 | *power_domain_mask |= BIT(power_domain); | |
10603 | ||
10604 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); | |
10605 | ||
10606 | return tmp & PIPECONF_ENABLE; | |
10607 | } | |
10608 | ||
4d1de975 JN |
10609 | static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, |
10610 | struct intel_crtc_state *pipe_config, | |
10611 | unsigned long *power_domain_mask) | |
10612 | { | |
10613 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10614 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 JN |
10615 | enum intel_display_power_domain power_domain; |
10616 | enum port port; | |
10617 | enum transcoder cpu_transcoder; | |
10618 | u32 tmp; | |
10619 | ||
4d1de975 JN |
10620 | for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { |
10621 | if (port == PORT_A) | |
10622 | cpu_transcoder = TRANSCODER_DSI_A; | |
10623 | else | |
10624 | cpu_transcoder = TRANSCODER_DSI_C; | |
10625 | ||
10626 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
10627 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
10628 | continue; | |
10629 | *power_domain_mask |= BIT(power_domain); | |
10630 | ||
db18b6a6 ID |
10631 | /* |
10632 | * The PLL needs to be enabled with a valid divider | |
10633 | * configuration, otherwise accessing DSI registers will hang | |
10634 | * the machine. See BSpec North Display Engine | |
10635 | * registers/MIPI[BXT]. We can break out here early, since we | |
10636 | * need the same DSI PLL to be enabled for both DSI ports. | |
10637 | */ | |
10638 | if (!intel_dsi_pll_is_enabled(dev_priv)) | |
10639 | break; | |
10640 | ||
4d1de975 JN |
10641 | /* XXX: this works for video mode only */ |
10642 | tmp = I915_READ(BXT_MIPI_PORT_CTRL(port)); | |
10643 | if (!(tmp & DPI_ENABLE)) | |
10644 | continue; | |
10645 | ||
10646 | tmp = I915_READ(MIPI_CTRL(port)); | |
10647 | if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) | |
10648 | continue; | |
10649 | ||
10650 | pipe_config->cpu_transcoder = cpu_transcoder; | |
4d1de975 JN |
10651 | break; |
10652 | } | |
10653 | ||
d7edc4e5 | 10654 | return transcoder_is_dsi(pipe_config->cpu_transcoder); |
4d1de975 JN |
10655 | } |
10656 | ||
26804afd | 10657 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 10658 | struct intel_crtc_state *pipe_config) |
26804afd DV |
10659 | { |
10660 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10661 | struct drm_i915_private *dev_priv = to_i915(dev); |
d452c5b6 | 10662 | struct intel_shared_dpll *pll; |
26804afd DV |
10663 | enum port port; |
10664 | uint32_t tmp; | |
10665 | ||
10666 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
10667 | ||
10668 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
10669 | ||
0853723b | 10670 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
96b7dfb7 | 10671 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
e2d214ae | 10672 | else if (IS_BROXTON(dev_priv)) |
3760b59c | 10673 | bxt_get_ddi_pll(dev_priv, port, pipe_config); |
96b7dfb7 S |
10674 | else |
10675 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 10676 | |
8106ddbd ACO |
10677 | pll = pipe_config->shared_dpll; |
10678 | if (pll) { | |
2edd6443 ACO |
10679 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
10680 | &pipe_config->dpll_hw_state)); | |
d452c5b6 DV |
10681 | } |
10682 | ||
26804afd DV |
10683 | /* |
10684 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
10685 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
10686 | * the PCH transcoder is on. | |
10687 | */ | |
ca370455 DL |
10688 | if (INTEL_INFO(dev)->gen < 9 && |
10689 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
10690 | pipe_config->has_pch_encoder = true; |
10691 | ||
10692 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
10693 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
10694 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
10695 | ||
10696 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
10697 | } | |
10698 | } | |
10699 | ||
0e8ffe1b | 10700 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 10701 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
10702 | { |
10703 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10704 | struct drm_i915_private *dev_priv = to_i915(dev); |
1729050e ID |
10705 | enum intel_display_power_domain power_domain; |
10706 | unsigned long power_domain_mask; | |
cf30429e | 10707 | bool active; |
0e8ffe1b | 10708 | |
1729050e ID |
10709 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
10710 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 | 10711 | return false; |
1729050e ID |
10712 | power_domain_mask = BIT(power_domain); |
10713 | ||
8106ddbd | 10714 | pipe_config->shared_dpll = NULL; |
c0d43d62 | 10715 | |
cf30429e | 10716 | active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask); |
eccb140b | 10717 | |
d7edc4e5 VS |
10718 | if (IS_BROXTON(dev_priv) && |
10719 | bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) { | |
10720 | WARN_ON(active); | |
10721 | active = true; | |
4d1de975 JN |
10722 | } |
10723 | ||
cf30429e | 10724 | if (!active) |
1729050e | 10725 | goto out; |
0e8ffe1b | 10726 | |
d7edc4e5 | 10727 | if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { |
4d1de975 JN |
10728 | haswell_get_ddi_port_state(crtc, pipe_config); |
10729 | intel_get_pipe_timings(crtc, pipe_config); | |
10730 | } | |
627eb5a3 | 10731 | |
bc58be60 | 10732 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 10733 | |
05dc698c LL |
10734 | pipe_config->gamma_mode = |
10735 | I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; | |
10736 | ||
a1b2278e CK |
10737 | if (INTEL_INFO(dev)->gen >= 9) { |
10738 | skl_init_scalers(dev, crtc, pipe_config); | |
10739 | } | |
10740 | ||
af99ceda CK |
10741 | if (INTEL_INFO(dev)->gen >= 9) { |
10742 | pipe_config->scaler_state.scaler_id = -1; | |
10743 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
10744 | } | |
10745 | ||
1729050e ID |
10746 | power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
10747 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
10748 | power_domain_mask |= BIT(power_domain); | |
1c132b44 | 10749 | if (INTEL_INFO(dev)->gen >= 9) |
bd2e244f | 10750 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 10751 | else |
1c132b44 | 10752 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 10753 | } |
88adfff1 | 10754 | |
772c2a51 | 10755 | if (IS_HASWELL(dev_priv)) |
e59150dc JB |
10756 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && |
10757 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 10758 | |
4d1de975 JN |
10759 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP && |
10760 | !transcoder_is_dsi(pipe_config->cpu_transcoder)) { | |
ebb69c95 CT |
10761 | pipe_config->pixel_multiplier = |
10762 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
10763 | } else { | |
10764 | pipe_config->pixel_multiplier = 1; | |
10765 | } | |
6c49f241 | 10766 | |
1729050e ID |
10767 | out: |
10768 | for_each_power_domain(power_domain, power_domain_mask) | |
10769 | intel_display_power_put(dev_priv, power_domain); | |
10770 | ||
cf30429e | 10771 | return active; |
0e8ffe1b DV |
10772 | } |
10773 | ||
55a08b3f ML |
10774 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base, |
10775 | const struct intel_plane_state *plane_state) | |
560b85bb CW |
10776 | { |
10777 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 10778 | struct drm_i915_private *dev_priv = to_i915(dev); |
560b85bb | 10779 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
dc41c154 | 10780 | uint32_t cntl = 0, size = 0; |
560b85bb | 10781 | |
936e71e3 | 10782 | if (plane_state && plane_state->base.visible) { |
55a08b3f ML |
10783 | unsigned int width = plane_state->base.crtc_w; |
10784 | unsigned int height = plane_state->base.crtc_h; | |
dc41c154 VS |
10785 | unsigned int stride = roundup_pow_of_two(width) * 4; |
10786 | ||
10787 | switch (stride) { | |
10788 | default: | |
10789 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
10790 | width, stride); | |
10791 | stride = 256; | |
10792 | /* fallthrough */ | |
10793 | case 256: | |
10794 | case 512: | |
10795 | case 1024: | |
10796 | case 2048: | |
10797 | break; | |
4b0e333e CW |
10798 | } |
10799 | ||
dc41c154 VS |
10800 | cntl |= CURSOR_ENABLE | |
10801 | CURSOR_GAMMA_ENABLE | | |
10802 | CURSOR_FORMAT_ARGB | | |
10803 | CURSOR_STRIDE(stride); | |
10804 | ||
10805 | size = (height << 12) | width; | |
4b0e333e | 10806 | } |
560b85bb | 10807 | |
dc41c154 VS |
10808 | if (intel_crtc->cursor_cntl != 0 && |
10809 | (intel_crtc->cursor_base != base || | |
10810 | intel_crtc->cursor_size != size || | |
10811 | intel_crtc->cursor_cntl != cntl)) { | |
10812 | /* On these chipsets we can only modify the base/size/stride | |
10813 | * whilst the cursor is disabled. | |
10814 | */ | |
0b87c24e VS |
10815 | I915_WRITE(CURCNTR(PIPE_A), 0); |
10816 | POSTING_READ(CURCNTR(PIPE_A)); | |
dc41c154 | 10817 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 10818 | } |
560b85bb | 10819 | |
99d1f387 | 10820 | if (intel_crtc->cursor_base != base) { |
0b87c24e | 10821 | I915_WRITE(CURBASE(PIPE_A), base); |
99d1f387 VS |
10822 | intel_crtc->cursor_base = base; |
10823 | } | |
4726e0b0 | 10824 | |
dc41c154 VS |
10825 | if (intel_crtc->cursor_size != size) { |
10826 | I915_WRITE(CURSIZE, size); | |
10827 | intel_crtc->cursor_size = size; | |
4b0e333e | 10828 | } |
560b85bb | 10829 | |
4b0e333e | 10830 | if (intel_crtc->cursor_cntl != cntl) { |
0b87c24e VS |
10831 | I915_WRITE(CURCNTR(PIPE_A), cntl); |
10832 | POSTING_READ(CURCNTR(PIPE_A)); | |
4b0e333e | 10833 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 10834 | } |
560b85bb CW |
10835 | } |
10836 | ||
55a08b3f ML |
10837 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, |
10838 | const struct intel_plane_state *plane_state) | |
65a21cd6 JB |
10839 | { |
10840 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 10841 | struct drm_i915_private *dev_priv = to_i915(dev); |
65a21cd6 | 10842 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
d8c0fafc | 10843 | struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state); |
62e0fb88 | 10844 | const struct skl_wm_values *wm = &dev_priv->wm.skl_results; |
d8c0fafc | 10845 | const struct skl_plane_wm *p_wm = |
10846 | &cstate->wm.skl.optimal.planes[PLANE_CURSOR]; | |
65a21cd6 | 10847 | int pipe = intel_crtc->pipe; |
663f3122 | 10848 | uint32_t cntl = 0; |
4b0e333e | 10849 | |
62e0fb88 | 10850 | if (INTEL_GEN(dev_priv) >= 9 && wm->dirty_pipes & drm_crtc_mask(crtc)) |
d8c0fafc | 10851 | skl_write_cursor_wm(intel_crtc, p_wm, &wm->ddb); |
62e0fb88 | 10852 | |
936e71e3 | 10853 | if (plane_state && plane_state->base.visible) { |
4b0e333e | 10854 | cntl = MCURSOR_GAMMA_ENABLE; |
55a08b3f | 10855 | switch (plane_state->base.crtc_w) { |
4726e0b0 SK |
10856 | case 64: |
10857 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
10858 | break; | |
10859 | case 128: | |
10860 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
10861 | break; | |
10862 | case 256: | |
10863 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
10864 | break; | |
10865 | default: | |
55a08b3f | 10866 | MISSING_CASE(plane_state->base.crtc_w); |
4726e0b0 | 10867 | return; |
65a21cd6 | 10868 | } |
4b0e333e | 10869 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 | 10870 | |
4f8036a2 | 10871 | if (HAS_DDI(dev_priv)) |
47bf17a7 | 10872 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
65a21cd6 | 10873 | |
31ad61e4 | 10874 | if (plane_state->base.rotation == DRM_ROTATE_180) |
55a08b3f ML |
10875 | cntl |= CURSOR_ROTATE_180; |
10876 | } | |
4398ad45 | 10877 | |
4b0e333e CW |
10878 | if (intel_crtc->cursor_cntl != cntl) { |
10879 | I915_WRITE(CURCNTR(pipe), cntl); | |
10880 | POSTING_READ(CURCNTR(pipe)); | |
10881 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 10882 | } |
4b0e333e | 10883 | |
65a21cd6 | 10884 | /* and commit changes on next vblank */ |
5efb3e28 VS |
10885 | I915_WRITE(CURBASE(pipe), base); |
10886 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
10887 | |
10888 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
10889 | } |
10890 | ||
cda4b7d3 | 10891 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f | 10892 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
55a08b3f | 10893 | const struct intel_plane_state *plane_state) |
cda4b7d3 CW |
10894 | { |
10895 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 10896 | struct drm_i915_private *dev_priv = to_i915(dev); |
cda4b7d3 CW |
10897 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10898 | int pipe = intel_crtc->pipe; | |
55a08b3f ML |
10899 | u32 base = intel_crtc->cursor_addr; |
10900 | u32 pos = 0; | |
cda4b7d3 | 10901 | |
55a08b3f ML |
10902 | if (plane_state) { |
10903 | int x = plane_state->base.crtc_x; | |
10904 | int y = plane_state->base.crtc_y; | |
cda4b7d3 | 10905 | |
55a08b3f ML |
10906 | if (x < 0) { |
10907 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
10908 | x = -x; | |
10909 | } | |
10910 | pos |= x << CURSOR_X_SHIFT; | |
cda4b7d3 | 10911 | |
55a08b3f ML |
10912 | if (y < 0) { |
10913 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
10914 | y = -y; | |
10915 | } | |
10916 | pos |= y << CURSOR_Y_SHIFT; | |
10917 | ||
10918 | /* ILK+ do this automagically */ | |
49cff963 | 10919 | if (HAS_GMCH_DISPLAY(dev_priv) && |
31ad61e4 | 10920 | plane_state->base.rotation == DRM_ROTATE_180) { |
55a08b3f ML |
10921 | base += (plane_state->base.crtc_h * |
10922 | plane_state->base.crtc_w - 1) * 4; | |
10923 | } | |
cda4b7d3 | 10924 | } |
cda4b7d3 | 10925 | |
5efb3e28 VS |
10926 | I915_WRITE(CURPOS(pipe), pos); |
10927 | ||
50a0bc90 | 10928 | if (IS_845G(dev_priv) || IS_I865G(dev_priv)) |
55a08b3f | 10929 | i845_update_cursor(crtc, base, plane_state); |
5efb3e28 | 10930 | else |
55a08b3f | 10931 | i9xx_update_cursor(crtc, base, plane_state); |
cda4b7d3 CW |
10932 | } |
10933 | ||
50a0bc90 | 10934 | static bool cursor_size_ok(struct drm_i915_private *dev_priv, |
dc41c154 VS |
10935 | uint32_t width, uint32_t height) |
10936 | { | |
10937 | if (width == 0 || height == 0) | |
10938 | return false; | |
10939 | ||
10940 | /* | |
10941 | * 845g/865g are special in that they are only limited by | |
10942 | * the width of their cursors, the height is arbitrary up to | |
10943 | * the precision of the register. Everything else requires | |
10944 | * square cursors, limited to a few power-of-two sizes. | |
10945 | */ | |
50a0bc90 | 10946 | if (IS_845G(dev_priv) || IS_I865G(dev_priv)) { |
dc41c154 VS |
10947 | if ((width & 63) != 0) |
10948 | return false; | |
10949 | ||
50a0bc90 | 10950 | if (width > (IS_845G(dev_priv) ? 64 : 512)) |
dc41c154 VS |
10951 | return false; |
10952 | ||
10953 | if (height > 1023) | |
10954 | return false; | |
10955 | } else { | |
10956 | switch (width | height) { | |
10957 | case 256: | |
10958 | case 128: | |
50a0bc90 | 10959 | if (IS_GEN2(dev_priv)) |
dc41c154 VS |
10960 | return false; |
10961 | case 64: | |
10962 | break; | |
10963 | default: | |
10964 | return false; | |
10965 | } | |
10966 | } | |
10967 | ||
10968 | return true; | |
10969 | } | |
10970 | ||
79e53945 JB |
10971 | /* VESA 640x480x72Hz mode to set on the pipe */ |
10972 | static struct drm_display_mode load_detect_mode = { | |
10973 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
10974 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
10975 | }; | |
10976 | ||
a8bb6818 DV |
10977 | struct drm_framebuffer * |
10978 | __intel_framebuffer_create(struct drm_device *dev, | |
10979 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10980 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
10981 | { |
10982 | struct intel_framebuffer *intel_fb; | |
10983 | int ret; | |
10984 | ||
10985 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
dcb1394e | 10986 | if (!intel_fb) |
d2dff872 | 10987 | return ERR_PTR(-ENOMEM); |
d2dff872 CW |
10988 | |
10989 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
10990 | if (ret) |
10991 | goto err; | |
d2dff872 CW |
10992 | |
10993 | return &intel_fb->base; | |
dcb1394e | 10994 | |
dd4916c5 | 10995 | err: |
dd4916c5 | 10996 | kfree(intel_fb); |
dd4916c5 | 10997 | return ERR_PTR(ret); |
d2dff872 CW |
10998 | } |
10999 | ||
b5ea642a | 11000 | static struct drm_framebuffer * |
a8bb6818 DV |
11001 | intel_framebuffer_create(struct drm_device *dev, |
11002 | struct drm_mode_fb_cmd2 *mode_cmd, | |
11003 | struct drm_i915_gem_object *obj) | |
11004 | { | |
11005 | struct drm_framebuffer *fb; | |
11006 | int ret; | |
11007 | ||
11008 | ret = i915_mutex_lock_interruptible(dev); | |
11009 | if (ret) | |
11010 | return ERR_PTR(ret); | |
11011 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
11012 | mutex_unlock(&dev->struct_mutex); | |
11013 | ||
11014 | return fb; | |
11015 | } | |
11016 | ||
d2dff872 CW |
11017 | static u32 |
11018 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
11019 | { | |
11020 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
11021 | return ALIGN(pitch, 64); | |
11022 | } | |
11023 | ||
11024 | static u32 | |
11025 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
11026 | { | |
11027 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 11028 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
11029 | } |
11030 | ||
11031 | static struct drm_framebuffer * | |
11032 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
11033 | struct drm_display_mode *mode, | |
11034 | int depth, int bpp) | |
11035 | { | |
dcb1394e | 11036 | struct drm_framebuffer *fb; |
d2dff872 | 11037 | struct drm_i915_gem_object *obj; |
0fed39bd | 11038 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 | 11039 | |
d37cd8a8 | 11040 | obj = i915_gem_object_create(dev, |
d2dff872 | 11041 | intel_framebuffer_size_for_mode(mode, bpp)); |
fe3db79b CW |
11042 | if (IS_ERR(obj)) |
11043 | return ERR_CAST(obj); | |
d2dff872 CW |
11044 | |
11045 | mode_cmd.width = mode->hdisplay; | |
11046 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
11047 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
11048 | bpp); | |
5ca0c34a | 11049 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 | 11050 | |
dcb1394e LW |
11051 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
11052 | if (IS_ERR(fb)) | |
f0cd5182 | 11053 | i915_gem_object_put(obj); |
dcb1394e LW |
11054 | |
11055 | return fb; | |
d2dff872 CW |
11056 | } |
11057 | ||
11058 | static struct drm_framebuffer * | |
11059 | mode_fits_in_fbdev(struct drm_device *dev, | |
11060 | struct drm_display_mode *mode) | |
11061 | { | |
0695726e | 11062 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
fac5e23e | 11063 | struct drm_i915_private *dev_priv = to_i915(dev); |
d2dff872 CW |
11064 | struct drm_i915_gem_object *obj; |
11065 | struct drm_framebuffer *fb; | |
11066 | ||
4c0e5528 | 11067 | if (!dev_priv->fbdev) |
d2dff872 CW |
11068 | return NULL; |
11069 | ||
4c0e5528 | 11070 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
11071 | return NULL; |
11072 | ||
4c0e5528 DV |
11073 | obj = dev_priv->fbdev->fb->obj; |
11074 | BUG_ON(!obj); | |
11075 | ||
8bcd4553 | 11076 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
11077 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
11078 | fb->bits_per_pixel)) | |
d2dff872 CW |
11079 | return NULL; |
11080 | ||
01f2c773 | 11081 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
11082 | return NULL; |
11083 | ||
edde3617 | 11084 | drm_framebuffer_reference(fb); |
d2dff872 | 11085 | return fb; |
4520f53a DV |
11086 | #else |
11087 | return NULL; | |
11088 | #endif | |
d2dff872 CW |
11089 | } |
11090 | ||
d3a40d1b ACO |
11091 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
11092 | struct drm_crtc *crtc, | |
11093 | struct drm_display_mode *mode, | |
11094 | struct drm_framebuffer *fb, | |
11095 | int x, int y) | |
11096 | { | |
11097 | struct drm_plane_state *plane_state; | |
11098 | int hdisplay, vdisplay; | |
11099 | int ret; | |
11100 | ||
11101 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
11102 | if (IS_ERR(plane_state)) | |
11103 | return PTR_ERR(plane_state); | |
11104 | ||
11105 | if (mode) | |
11106 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); | |
11107 | else | |
11108 | hdisplay = vdisplay = 0; | |
11109 | ||
11110 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
11111 | if (ret) | |
11112 | return ret; | |
11113 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
11114 | plane_state->crtc_x = 0; | |
11115 | plane_state->crtc_y = 0; | |
11116 | plane_state->crtc_w = hdisplay; | |
11117 | plane_state->crtc_h = vdisplay; | |
11118 | plane_state->src_x = x << 16; | |
11119 | plane_state->src_y = y << 16; | |
11120 | plane_state->src_w = hdisplay << 16; | |
11121 | plane_state->src_h = vdisplay << 16; | |
11122 | ||
11123 | return 0; | |
11124 | } | |
11125 | ||
d2434ab7 | 11126 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 11127 | struct drm_display_mode *mode, |
51fd371b RC |
11128 | struct intel_load_detect_pipe *old, |
11129 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
11130 | { |
11131 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
11132 | struct intel_encoder *intel_encoder = |
11133 | intel_attached_encoder(connector); | |
79e53945 | 11134 | struct drm_crtc *possible_crtc; |
4ef69c7a | 11135 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
11136 | struct drm_crtc *crtc = NULL; |
11137 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 11138 | struct drm_framebuffer *fb; |
51fd371b | 11139 | struct drm_mode_config *config = &dev->mode_config; |
edde3617 | 11140 | struct drm_atomic_state *state = NULL, *restore_state = NULL; |
944b0c76 | 11141 | struct drm_connector_state *connector_state; |
4be07317 | 11142 | struct intel_crtc_state *crtc_state; |
51fd371b | 11143 | int ret, i = -1; |
79e53945 | 11144 | |
d2dff872 | 11145 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 11146 | connector->base.id, connector->name, |
8e329a03 | 11147 | encoder->base.id, encoder->name); |
d2dff872 | 11148 | |
edde3617 ML |
11149 | old->restore_state = NULL; |
11150 | ||
51fd371b RC |
11151 | retry: |
11152 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
11153 | if (ret) | |
ad3c558f | 11154 | goto fail; |
6e9f798d | 11155 | |
79e53945 JB |
11156 | /* |
11157 | * Algorithm gets a little messy: | |
7a5e4805 | 11158 | * |
79e53945 JB |
11159 | * - if the connector already has an assigned crtc, use it (but make |
11160 | * sure it's on first) | |
7a5e4805 | 11161 | * |
79e53945 JB |
11162 | * - try to find the first unused crtc that can drive this connector, |
11163 | * and use that if we find one | |
79e53945 JB |
11164 | */ |
11165 | ||
11166 | /* See if we already have a CRTC for this connector */ | |
edde3617 ML |
11167 | if (connector->state->crtc) { |
11168 | crtc = connector->state->crtc; | |
8261b191 | 11169 | |
51fd371b | 11170 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 11171 | if (ret) |
ad3c558f | 11172 | goto fail; |
8261b191 CW |
11173 | |
11174 | /* Make sure the crtc and connector are running */ | |
edde3617 | 11175 | goto found; |
79e53945 JB |
11176 | } |
11177 | ||
11178 | /* Find an unused one (if possible) */ | |
70e1e0ec | 11179 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
11180 | i++; |
11181 | if (!(encoder->possible_crtcs & (1 << i))) | |
11182 | continue; | |
edde3617 ML |
11183 | |
11184 | ret = drm_modeset_lock(&possible_crtc->mutex, ctx); | |
11185 | if (ret) | |
11186 | goto fail; | |
11187 | ||
11188 | if (possible_crtc->state->enable) { | |
11189 | drm_modeset_unlock(&possible_crtc->mutex); | |
a459249c | 11190 | continue; |
edde3617 | 11191 | } |
a459249c VS |
11192 | |
11193 | crtc = possible_crtc; | |
11194 | break; | |
79e53945 JB |
11195 | } |
11196 | ||
11197 | /* | |
11198 | * If we didn't find an unused CRTC, don't use any. | |
11199 | */ | |
11200 | if (!crtc) { | |
7173188d | 11201 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
ad3c558f | 11202 | goto fail; |
79e53945 JB |
11203 | } |
11204 | ||
edde3617 ML |
11205 | found: |
11206 | intel_crtc = to_intel_crtc(crtc); | |
11207 | ||
4d02e2de DV |
11208 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
11209 | if (ret) | |
ad3c558f | 11210 | goto fail; |
79e53945 | 11211 | |
83a57153 | 11212 | state = drm_atomic_state_alloc(dev); |
edde3617 ML |
11213 | restore_state = drm_atomic_state_alloc(dev); |
11214 | if (!state || !restore_state) { | |
11215 | ret = -ENOMEM; | |
11216 | goto fail; | |
11217 | } | |
83a57153 ACO |
11218 | |
11219 | state->acquire_ctx = ctx; | |
edde3617 | 11220 | restore_state->acquire_ctx = ctx; |
83a57153 | 11221 | |
944b0c76 ACO |
11222 | connector_state = drm_atomic_get_connector_state(state, connector); |
11223 | if (IS_ERR(connector_state)) { | |
11224 | ret = PTR_ERR(connector_state); | |
11225 | goto fail; | |
11226 | } | |
11227 | ||
edde3617 ML |
11228 | ret = drm_atomic_set_crtc_for_connector(connector_state, crtc); |
11229 | if (ret) | |
11230 | goto fail; | |
944b0c76 | 11231 | |
4be07317 ACO |
11232 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
11233 | if (IS_ERR(crtc_state)) { | |
11234 | ret = PTR_ERR(crtc_state); | |
11235 | goto fail; | |
11236 | } | |
11237 | ||
49d6fa21 | 11238 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 11239 | |
6492711d CW |
11240 | if (!mode) |
11241 | mode = &load_detect_mode; | |
79e53945 | 11242 | |
d2dff872 CW |
11243 | /* We need a framebuffer large enough to accommodate all accesses |
11244 | * that the plane may generate whilst we perform load detection. | |
11245 | * We can not rely on the fbcon either being present (we get called | |
11246 | * during its initialisation to detect all boot displays, or it may | |
11247 | * not even exist) or that it is large enough to satisfy the | |
11248 | * requested mode. | |
11249 | */ | |
94352cf9 DV |
11250 | fb = mode_fits_in_fbdev(dev, mode); |
11251 | if (fb == NULL) { | |
d2dff872 | 11252 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 | 11253 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
d2dff872 CW |
11254 | } else |
11255 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 11256 | if (IS_ERR(fb)) { |
d2dff872 | 11257 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 11258 | goto fail; |
79e53945 | 11259 | } |
79e53945 | 11260 | |
d3a40d1b ACO |
11261 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
11262 | if (ret) | |
11263 | goto fail; | |
11264 | ||
edde3617 ML |
11265 | drm_framebuffer_unreference(fb); |
11266 | ||
11267 | ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode); | |
11268 | if (ret) | |
11269 | goto fail; | |
11270 | ||
11271 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); | |
11272 | if (!ret) | |
11273 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc)); | |
11274 | if (!ret) | |
11275 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary)); | |
11276 | if (ret) { | |
11277 | DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret); | |
11278 | goto fail; | |
11279 | } | |
8c7b5ccb | 11280 | |
3ba86073 ML |
11281 | ret = drm_atomic_commit(state); |
11282 | if (ret) { | |
6492711d | 11283 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
412b61d8 | 11284 | goto fail; |
79e53945 | 11285 | } |
edde3617 ML |
11286 | |
11287 | old->restore_state = restore_state; | |
7173188d | 11288 | |
79e53945 | 11289 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 11290 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 11291 | return true; |
412b61d8 | 11292 | |
ad3c558f | 11293 | fail: |
7fb71c8f CW |
11294 | if (state) { |
11295 | drm_atomic_state_put(state); | |
11296 | state = NULL; | |
11297 | } | |
11298 | if (restore_state) { | |
11299 | drm_atomic_state_put(restore_state); | |
11300 | restore_state = NULL; | |
11301 | } | |
83a57153 | 11302 | |
51fd371b RC |
11303 | if (ret == -EDEADLK) { |
11304 | drm_modeset_backoff(ctx); | |
11305 | goto retry; | |
11306 | } | |
11307 | ||
412b61d8 | 11308 | return false; |
79e53945 JB |
11309 | } |
11310 | ||
d2434ab7 | 11311 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
11312 | struct intel_load_detect_pipe *old, |
11313 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 11314 | { |
d2434ab7 DV |
11315 | struct intel_encoder *intel_encoder = |
11316 | intel_attached_encoder(connector); | |
4ef69c7a | 11317 | struct drm_encoder *encoder = &intel_encoder->base; |
edde3617 | 11318 | struct drm_atomic_state *state = old->restore_state; |
d3a40d1b | 11319 | int ret; |
79e53945 | 11320 | |
d2dff872 | 11321 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 11322 | connector->base.id, connector->name, |
8e329a03 | 11323 | encoder->base.id, encoder->name); |
d2dff872 | 11324 | |
edde3617 | 11325 | if (!state) |
0622a53c | 11326 | return; |
79e53945 | 11327 | |
edde3617 | 11328 | ret = drm_atomic_commit(state); |
0853695c | 11329 | if (ret) |
edde3617 | 11330 | DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret); |
0853695c | 11331 | drm_atomic_state_put(state); |
79e53945 JB |
11332 | } |
11333 | ||
da4a1efa | 11334 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 11335 | const struct intel_crtc_state *pipe_config) |
da4a1efa | 11336 | { |
fac5e23e | 11337 | struct drm_i915_private *dev_priv = to_i915(dev); |
da4a1efa VS |
11338 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
11339 | ||
11340 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 11341 | return dev_priv->vbt.lvds_ssc_freq; |
6e266956 | 11342 | else if (HAS_PCH_SPLIT(dev_priv)) |
da4a1efa | 11343 | return 120000; |
5db94019 | 11344 | else if (!IS_GEN2(dev_priv)) |
da4a1efa VS |
11345 | return 96000; |
11346 | else | |
11347 | return 48000; | |
11348 | } | |
11349 | ||
79e53945 | 11350 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 11351 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 11352 | struct intel_crtc_state *pipe_config) |
79e53945 | 11353 | { |
f1f644dc | 11354 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 11355 | struct drm_i915_private *dev_priv = to_i915(dev); |
f1f644dc | 11356 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 11357 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 | 11358 | u32 fp; |
9e2c8475 | 11359 | struct dpll clock; |
dccbea3b | 11360 | int port_clock; |
da4a1efa | 11361 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
11362 | |
11363 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 11364 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 11365 | else |
293623f7 | 11366 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
11367 | |
11368 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
11369 | if (IS_PINEVIEW(dev)) { |
11370 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
11371 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
11372 | } else { |
11373 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
11374 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
11375 | } | |
11376 | ||
5db94019 | 11377 | if (!IS_GEN2(dev_priv)) { |
f2b115e6 AJ |
11378 | if (IS_PINEVIEW(dev)) |
11379 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
11380 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
11381 | else |
11382 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
11383 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
11384 | ||
11385 | switch (dpll & DPLL_MODE_MASK) { | |
11386 | case DPLLB_MODE_DAC_SERIAL: | |
11387 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
11388 | 5 : 10; | |
11389 | break; | |
11390 | case DPLLB_MODE_LVDS: | |
11391 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
11392 | 7 : 14; | |
11393 | break; | |
11394 | default: | |
28c97730 | 11395 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 11396 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 11397 | return; |
79e53945 JB |
11398 | } |
11399 | ||
ac58c3f0 | 11400 | if (IS_PINEVIEW(dev)) |
dccbea3b | 11401 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 11402 | else |
dccbea3b | 11403 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 11404 | } else { |
50a0bc90 | 11405 | u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS); |
b1c560d1 | 11406 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
11407 | |
11408 | if (is_lvds) { | |
11409 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
11410 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
11411 | |
11412 | if (lvds & LVDS_CLKB_POWER_UP) | |
11413 | clock.p2 = 7; | |
11414 | else | |
11415 | clock.p2 = 14; | |
79e53945 JB |
11416 | } else { |
11417 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
11418 | clock.p1 = 2; | |
11419 | else { | |
11420 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
11421 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
11422 | } | |
11423 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
11424 | clock.p2 = 4; | |
11425 | else | |
11426 | clock.p2 = 2; | |
79e53945 | 11427 | } |
da4a1efa | 11428 | |
dccbea3b | 11429 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
11430 | } |
11431 | ||
18442d08 VS |
11432 | /* |
11433 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 11434 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
11435 | * encoder's get_config() function. |
11436 | */ | |
dccbea3b | 11437 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
11438 | } |
11439 | ||
6878da05 VS |
11440 | int intel_dotclock_calculate(int link_freq, |
11441 | const struct intel_link_m_n *m_n) | |
f1f644dc | 11442 | { |
f1f644dc JB |
11443 | /* |
11444 | * The calculation for the data clock is: | |
1041a02f | 11445 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 11446 | * But we want to avoid losing precison if possible, so: |
1041a02f | 11447 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
11448 | * |
11449 | * and the link clock is simpler: | |
1041a02f | 11450 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
11451 | */ |
11452 | ||
6878da05 VS |
11453 | if (!m_n->link_n) |
11454 | return 0; | |
f1f644dc | 11455 | |
6878da05 VS |
11456 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
11457 | } | |
f1f644dc | 11458 | |
18442d08 | 11459 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 11460 | struct intel_crtc_state *pipe_config) |
6878da05 | 11461 | { |
e3b247da | 11462 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
79e53945 | 11463 | |
18442d08 VS |
11464 | /* read out port_clock from the DPLL */ |
11465 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 11466 | |
f1f644dc | 11467 | /* |
e3b247da VS |
11468 | * In case there is an active pipe without active ports, |
11469 | * we may need some idea for the dotclock anyway. | |
11470 | * Calculate one based on the FDI configuration. | |
79e53945 | 11471 | */ |
2d112de7 | 11472 | pipe_config->base.adjusted_mode.crtc_clock = |
21a727b3 | 11473 | intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
18442d08 | 11474 | &pipe_config->fdi_m_n); |
79e53945 JB |
11475 | } |
11476 | ||
11477 | /** Returns the currently programmed mode of the given pipe. */ | |
11478 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
11479 | struct drm_crtc *crtc) | |
11480 | { | |
fac5e23e | 11481 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 11482 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 11483 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 11484 | struct drm_display_mode *mode; |
3f36b937 | 11485 | struct intel_crtc_state *pipe_config; |
fe2b8f9d PZ |
11486 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
11487 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
11488 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
11489 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 11490 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
11491 | |
11492 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
11493 | if (!mode) | |
11494 | return NULL; | |
11495 | ||
3f36b937 TU |
11496 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
11497 | if (!pipe_config) { | |
11498 | kfree(mode); | |
11499 | return NULL; | |
11500 | } | |
11501 | ||
f1f644dc JB |
11502 | /* |
11503 | * Construct a pipe_config sufficient for getting the clock info | |
11504 | * back out of crtc_clock_get. | |
11505 | * | |
11506 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
11507 | * to use a real value here instead. | |
11508 | */ | |
3f36b937 TU |
11509 | pipe_config->cpu_transcoder = (enum transcoder) pipe; |
11510 | pipe_config->pixel_multiplier = 1; | |
11511 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe)); | |
11512 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
11513 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
11514 | i9xx_crtc_clock_get(intel_crtc, pipe_config); | |
11515 | ||
11516 | mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier; | |
79e53945 JB |
11517 | mode->hdisplay = (htot & 0xffff) + 1; |
11518 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
11519 | mode->hsync_start = (hsync & 0xffff) + 1; | |
11520 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
11521 | mode->vdisplay = (vtot & 0xffff) + 1; | |
11522 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
11523 | mode->vsync_start = (vsync & 0xffff) + 1; | |
11524 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
11525 | ||
11526 | drm_mode_set_name(mode); | |
79e53945 | 11527 | |
3f36b937 TU |
11528 | kfree(pipe_config); |
11529 | ||
79e53945 JB |
11530 | return mode; |
11531 | } | |
11532 | ||
11533 | static void intel_crtc_destroy(struct drm_crtc *crtc) | |
11534 | { | |
11535 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a | 11536 | struct drm_device *dev = crtc->dev; |
51cbaf01 | 11537 | struct intel_flip_work *work; |
67e77c5a | 11538 | |
5e2d7afc | 11539 | spin_lock_irq(&dev->event_lock); |
5a21b665 DV |
11540 | work = intel_crtc->flip_work; |
11541 | intel_crtc->flip_work = NULL; | |
11542 | spin_unlock_irq(&dev->event_lock); | |
67e77c5a | 11543 | |
5a21b665 | 11544 | if (work) { |
51cbaf01 ML |
11545 | cancel_work_sync(&work->mmio_work); |
11546 | cancel_work_sync(&work->unpin_work); | |
5a21b665 | 11547 | kfree(work); |
67e77c5a | 11548 | } |
79e53945 JB |
11549 | |
11550 | drm_crtc_cleanup(crtc); | |
67e77c5a | 11551 | |
79e53945 JB |
11552 | kfree(intel_crtc); |
11553 | } | |
11554 | ||
6b95a207 KH |
11555 | static void intel_unpin_work_fn(struct work_struct *__work) |
11556 | { | |
51cbaf01 ML |
11557 | struct intel_flip_work *work = |
11558 | container_of(__work, struct intel_flip_work, unpin_work); | |
5a21b665 DV |
11559 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); |
11560 | struct drm_device *dev = crtc->base.dev; | |
11561 | struct drm_plane *primary = crtc->base.primary; | |
03f476e1 | 11562 | |
5a21b665 DV |
11563 | if (is_mmio_work(work)) |
11564 | flush_work(&work->mmio_work); | |
03f476e1 | 11565 | |
5a21b665 DV |
11566 | mutex_lock(&dev->struct_mutex); |
11567 | intel_unpin_fb_obj(work->old_fb, primary->state->rotation); | |
f8c417cd | 11568 | i915_gem_object_put(work->pending_flip_obj); |
5a21b665 | 11569 | mutex_unlock(&dev->struct_mutex); |
143f73b3 | 11570 | |
e8a261ea CW |
11571 | i915_gem_request_put(work->flip_queued_req); |
11572 | ||
5748b6a1 CW |
11573 | intel_frontbuffer_flip_complete(to_i915(dev), |
11574 | to_intel_plane(primary)->frontbuffer_bit); | |
5a21b665 DV |
11575 | intel_fbc_post_update(crtc); |
11576 | drm_framebuffer_unreference(work->old_fb); | |
143f73b3 | 11577 | |
5a21b665 DV |
11578 | BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); |
11579 | atomic_dec(&crtc->unpin_work_count); | |
a6747b73 | 11580 | |
5a21b665 DV |
11581 | kfree(work); |
11582 | } | |
d9e86c0e | 11583 | |
5a21b665 DV |
11584 | /* Is 'a' after or equal to 'b'? */ |
11585 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
11586 | { | |
11587 | return !((a - b) & 0x80000000); | |
11588 | } | |
143f73b3 | 11589 | |
5a21b665 DV |
11590 | static bool __pageflip_finished_cs(struct intel_crtc *crtc, |
11591 | struct intel_flip_work *work) | |
11592 | { | |
11593 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 11594 | struct drm_i915_private *dev_priv = to_i915(dev); |
143f73b3 | 11595 | |
8af29b0c | 11596 | if (abort_flip_on_reset(crtc)) |
5a21b665 | 11597 | return true; |
143f73b3 | 11598 | |
5a21b665 DV |
11599 | /* |
11600 | * The relevant registers doen't exist on pre-ctg. | |
11601 | * As the flip done interrupt doesn't trigger for mmio | |
11602 | * flips on gmch platforms, a flip count check isn't | |
11603 | * really needed there. But since ctg has the registers, | |
11604 | * include it in the check anyway. | |
11605 | */ | |
9beb5fea | 11606 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) |
5a21b665 | 11607 | return true; |
b4a98e57 | 11608 | |
5a21b665 DV |
11609 | /* |
11610 | * BDW signals flip done immediately if the plane | |
11611 | * is disabled, even if the plane enable is already | |
11612 | * armed to occur at the next vblank :( | |
11613 | */ | |
f99d7069 | 11614 | |
5a21b665 DV |
11615 | /* |
11616 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
11617 | * used the same base address. In that case the mmio flip might | |
11618 | * have completed, but the CS hasn't even executed the flip yet. | |
11619 | * | |
11620 | * A flip count check isn't enough as the CS might have updated | |
11621 | * the base address just after start of vblank, but before we | |
11622 | * managed to process the interrupt. This means we'd complete the | |
11623 | * CS flip too soon. | |
11624 | * | |
11625 | * Combining both checks should get us a good enough result. It may | |
11626 | * still happen that the CS flip has been executed, but has not | |
11627 | * yet actually completed. But in case the base address is the same | |
11628 | * anyway, we don't really care. | |
11629 | */ | |
11630 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
11631 | crtc->flip_work->gtt_offset && | |
11632 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), | |
11633 | crtc->flip_work->flip_count); | |
11634 | } | |
b4a98e57 | 11635 | |
5a21b665 DV |
11636 | static bool |
11637 | __pageflip_finished_mmio(struct intel_crtc *crtc, | |
11638 | struct intel_flip_work *work) | |
11639 | { | |
11640 | /* | |
11641 | * MMIO work completes when vblank is different from | |
11642 | * flip_queued_vblank. | |
11643 | * | |
11644 | * Reset counter value doesn't matter, this is handled by | |
11645 | * i915_wait_request finishing early, so no need to handle | |
11646 | * reset here. | |
11647 | */ | |
11648 | return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank; | |
6b95a207 KH |
11649 | } |
11650 | ||
51cbaf01 ML |
11651 | |
11652 | static bool pageflip_finished(struct intel_crtc *crtc, | |
11653 | struct intel_flip_work *work) | |
11654 | { | |
11655 | if (!atomic_read(&work->pending)) | |
11656 | return false; | |
11657 | ||
11658 | smp_rmb(); | |
11659 | ||
5a21b665 DV |
11660 | if (is_mmio_work(work)) |
11661 | return __pageflip_finished_mmio(crtc, work); | |
11662 | else | |
11663 | return __pageflip_finished_cs(crtc, work); | |
11664 | } | |
11665 | ||
11666 | void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe) | |
11667 | { | |
91c8a326 | 11668 | struct drm_device *dev = &dev_priv->drm; |
5a21b665 DV |
11669 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
11670 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11671 | struct intel_flip_work *work; | |
11672 | unsigned long flags; | |
11673 | ||
11674 | /* Ignore early vblank irqs */ | |
11675 | if (!crtc) | |
11676 | return; | |
11677 | ||
51cbaf01 | 11678 | /* |
5a21b665 DV |
11679 | * This is called both by irq handlers and the reset code (to complete |
11680 | * lost pageflips) so needs the full irqsave spinlocks. | |
51cbaf01 | 11681 | */ |
5a21b665 DV |
11682 | spin_lock_irqsave(&dev->event_lock, flags); |
11683 | work = intel_crtc->flip_work; | |
11684 | ||
11685 | if (work != NULL && | |
11686 | !is_mmio_work(work) && | |
11687 | pageflip_finished(intel_crtc, work)) | |
11688 | page_flip_completed(intel_crtc); | |
11689 | ||
11690 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
75f7f3ec VS |
11691 | } |
11692 | ||
51cbaf01 | 11693 | void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe) |
6b95a207 | 11694 | { |
91c8a326 | 11695 | struct drm_device *dev = &dev_priv->drm; |
5251f04e ML |
11696 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
11697 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
51cbaf01 | 11698 | struct intel_flip_work *work; |
6b95a207 KH |
11699 | unsigned long flags; |
11700 | ||
5251f04e ML |
11701 | /* Ignore early vblank irqs */ |
11702 | if (!crtc) | |
11703 | return; | |
f326038a DV |
11704 | |
11705 | /* | |
11706 | * This is called both by irq handlers and the reset code (to complete | |
11707 | * lost pageflips) so needs the full irqsave spinlocks. | |
e7d841ca | 11708 | */ |
6b95a207 | 11709 | spin_lock_irqsave(&dev->event_lock, flags); |
5a21b665 | 11710 | work = intel_crtc->flip_work; |
5251f04e | 11711 | |
5a21b665 DV |
11712 | if (work != NULL && |
11713 | is_mmio_work(work) && | |
11714 | pageflip_finished(intel_crtc, work)) | |
11715 | page_flip_completed(intel_crtc); | |
5251f04e | 11716 | |
6b95a207 KH |
11717 | spin_unlock_irqrestore(&dev->event_lock, flags); |
11718 | } | |
11719 | ||
5a21b665 DV |
11720 | static inline void intel_mark_page_flip_active(struct intel_crtc *crtc, |
11721 | struct intel_flip_work *work) | |
84c33a64 | 11722 | { |
5a21b665 | 11723 | work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc); |
84c33a64 | 11724 | |
5a21b665 DV |
11725 | /* Ensure that the work item is consistent when activating it ... */ |
11726 | smp_mb__before_atomic(); | |
11727 | atomic_set(&work->pending, 1); | |
11728 | } | |
a6747b73 | 11729 | |
5a21b665 DV |
11730 | static int intel_gen2_queue_flip(struct drm_device *dev, |
11731 | struct drm_crtc *crtc, | |
11732 | struct drm_framebuffer *fb, | |
11733 | struct drm_i915_gem_object *obj, | |
11734 | struct drm_i915_gem_request *req, | |
11735 | uint32_t flags) | |
11736 | { | |
7e37f889 | 11737 | struct intel_ring *ring = req->ring; |
5a21b665 DV |
11738 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11739 | u32 flip_mask; | |
11740 | int ret; | |
143f73b3 | 11741 | |
5a21b665 DV |
11742 | ret = intel_ring_begin(req, 6); |
11743 | if (ret) | |
11744 | return ret; | |
143f73b3 | 11745 | |
5a21b665 DV |
11746 | /* Can't queue multiple flips, so wait for the previous |
11747 | * one to finish before executing the next. | |
11748 | */ | |
11749 | if (intel_crtc->plane) | |
11750 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11751 | else | |
11752 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
b5321f30 CW |
11753 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
11754 | intel_ring_emit(ring, MI_NOOP); | |
11755 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
5a21b665 | 11756 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
b5321f30 CW |
11757 | intel_ring_emit(ring, fb->pitches[0]); |
11758 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset); | |
11759 | intel_ring_emit(ring, 0); /* aux display base address, unused */ | |
143f73b3 | 11760 | |
5a21b665 DV |
11761 | return 0; |
11762 | } | |
84c33a64 | 11763 | |
5a21b665 DV |
11764 | static int intel_gen3_queue_flip(struct drm_device *dev, |
11765 | struct drm_crtc *crtc, | |
11766 | struct drm_framebuffer *fb, | |
11767 | struct drm_i915_gem_object *obj, | |
11768 | struct drm_i915_gem_request *req, | |
11769 | uint32_t flags) | |
11770 | { | |
7e37f889 | 11771 | struct intel_ring *ring = req->ring; |
5a21b665 DV |
11772 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11773 | u32 flip_mask; | |
11774 | int ret; | |
d55dbd06 | 11775 | |
5a21b665 DV |
11776 | ret = intel_ring_begin(req, 6); |
11777 | if (ret) | |
11778 | return ret; | |
d55dbd06 | 11779 | |
5a21b665 DV |
11780 | if (intel_crtc->plane) |
11781 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11782 | else | |
11783 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
b5321f30 CW |
11784 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
11785 | intel_ring_emit(ring, MI_NOOP); | |
11786 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
5a21b665 | 11787 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
b5321f30 CW |
11788 | intel_ring_emit(ring, fb->pitches[0]); |
11789 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset); | |
11790 | intel_ring_emit(ring, MI_NOOP); | |
fd8e058a | 11791 | |
5a21b665 DV |
11792 | return 0; |
11793 | } | |
84c33a64 | 11794 | |
5a21b665 DV |
11795 | static int intel_gen4_queue_flip(struct drm_device *dev, |
11796 | struct drm_crtc *crtc, | |
11797 | struct drm_framebuffer *fb, | |
11798 | struct drm_i915_gem_object *obj, | |
11799 | struct drm_i915_gem_request *req, | |
11800 | uint32_t flags) | |
11801 | { | |
7e37f889 | 11802 | struct intel_ring *ring = req->ring; |
fac5e23e | 11803 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
11804 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11805 | uint32_t pf, pipesrc; | |
11806 | int ret; | |
143f73b3 | 11807 | |
5a21b665 DV |
11808 | ret = intel_ring_begin(req, 4); |
11809 | if (ret) | |
11810 | return ret; | |
143f73b3 | 11811 | |
5a21b665 DV |
11812 | /* i965+ uses the linear or tiled offsets from the |
11813 | * Display Registers (which do not change across a page-flip) | |
11814 | * so we need only reprogram the base address. | |
11815 | */ | |
b5321f30 | 11816 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
5a21b665 | 11817 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
b5321f30 CW |
11818 | intel_ring_emit(ring, fb->pitches[0]); |
11819 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset | | |
72618ebf | 11820 | intel_fb_modifier_to_tiling(fb->modifier[0])); |
5a21b665 DV |
11821 | |
11822 | /* XXX Enabling the panel-fitter across page-flip is so far | |
11823 | * untested on non-native modes, so ignore it for now. | |
11824 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
11825 | */ | |
11826 | pf = 0; | |
11827 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
b5321f30 | 11828 | intel_ring_emit(ring, pf | pipesrc); |
143f73b3 | 11829 | |
5a21b665 | 11830 | return 0; |
8c9f3aaf JB |
11831 | } |
11832 | ||
5a21b665 DV |
11833 | static int intel_gen6_queue_flip(struct drm_device *dev, |
11834 | struct drm_crtc *crtc, | |
11835 | struct drm_framebuffer *fb, | |
11836 | struct drm_i915_gem_object *obj, | |
11837 | struct drm_i915_gem_request *req, | |
11838 | uint32_t flags) | |
da20eabd | 11839 | { |
7e37f889 | 11840 | struct intel_ring *ring = req->ring; |
fac5e23e | 11841 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
11842 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11843 | uint32_t pf, pipesrc; | |
11844 | int ret; | |
d21fbe87 | 11845 | |
5a21b665 DV |
11846 | ret = intel_ring_begin(req, 4); |
11847 | if (ret) | |
11848 | return ret; | |
92826fcd | 11849 | |
b5321f30 | 11850 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
5a21b665 | 11851 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
72618ebf VS |
11852 | intel_ring_emit(ring, fb->pitches[0] | |
11853 | intel_fb_modifier_to_tiling(fb->modifier[0])); | |
b5321f30 | 11854 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset); |
92826fcd | 11855 | |
5a21b665 DV |
11856 | /* Contrary to the suggestions in the documentation, |
11857 | * "Enable Panel Fitter" does not seem to be required when page | |
11858 | * flipping with a non-native mode, and worse causes a normal | |
11859 | * modeset to fail. | |
11860 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
11861 | */ | |
11862 | pf = 0; | |
11863 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
b5321f30 | 11864 | intel_ring_emit(ring, pf | pipesrc); |
7809e5ae | 11865 | |
5a21b665 | 11866 | return 0; |
7809e5ae MR |
11867 | } |
11868 | ||
5a21b665 DV |
11869 | static int intel_gen7_queue_flip(struct drm_device *dev, |
11870 | struct drm_crtc *crtc, | |
11871 | struct drm_framebuffer *fb, | |
11872 | struct drm_i915_gem_object *obj, | |
11873 | struct drm_i915_gem_request *req, | |
11874 | uint32_t flags) | |
d21fbe87 | 11875 | { |
5db94019 | 11876 | struct drm_i915_private *dev_priv = to_i915(dev); |
7e37f889 | 11877 | struct intel_ring *ring = req->ring; |
5a21b665 DV |
11878 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11879 | uint32_t plane_bit = 0; | |
11880 | int len, ret; | |
d21fbe87 | 11881 | |
5a21b665 DV |
11882 | switch (intel_crtc->plane) { |
11883 | case PLANE_A: | |
11884 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
11885 | break; | |
11886 | case PLANE_B: | |
11887 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
11888 | break; | |
11889 | case PLANE_C: | |
11890 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
11891 | break; | |
11892 | default: | |
11893 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
11894 | return -ENODEV; | |
11895 | } | |
11896 | ||
11897 | len = 4; | |
b5321f30 | 11898 | if (req->engine->id == RCS) { |
5a21b665 DV |
11899 | len += 6; |
11900 | /* | |
11901 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
11902 | * 48bits addresses, and we need a NOOP for the batch size to | |
11903 | * stay even. | |
11904 | */ | |
5db94019 | 11905 | if (IS_GEN8(dev_priv)) |
5a21b665 DV |
11906 | len += 2; |
11907 | } | |
11908 | ||
11909 | /* | |
11910 | * BSpec MI_DISPLAY_FLIP for IVB: | |
11911 | * "The full packet must be contained within the same cache line." | |
11912 | * | |
11913 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
11914 | * cacheline, if we ever start emitting more commands before | |
11915 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
11916 | * then do the cacheline alignment, and finally emit the | |
11917 | * MI_DISPLAY_FLIP. | |
11918 | */ | |
11919 | ret = intel_ring_cacheline_align(req); | |
11920 | if (ret) | |
11921 | return ret; | |
11922 | ||
11923 | ret = intel_ring_begin(req, len); | |
11924 | if (ret) | |
11925 | return ret; | |
11926 | ||
11927 | /* Unmask the flip-done completion message. Note that the bspec says that | |
11928 | * we should do this for both the BCS and RCS, and that we must not unmask | |
11929 | * more than one flip event at any time (or ensure that one flip message | |
11930 | * can be sent by waiting for flip-done prior to queueing new flips). | |
11931 | * Experimentation says that BCS works despite DERRMR masking all | |
11932 | * flip-done completion events and that unmasking all planes at once | |
11933 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
11934 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
11935 | */ | |
b5321f30 CW |
11936 | if (req->engine->id == RCS) { |
11937 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
11938 | intel_ring_emit_reg(ring, DERRMR); | |
11939 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
5a21b665 DV |
11940 | DERRMR_PIPEB_PRI_FLIP_DONE | |
11941 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
5db94019 | 11942 | if (IS_GEN8(dev_priv)) |
b5321f30 | 11943 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 | |
5a21b665 DV |
11944 | MI_SRM_LRM_GLOBAL_GTT); |
11945 | else | |
b5321f30 | 11946 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM | |
5a21b665 | 11947 | MI_SRM_LRM_GLOBAL_GTT); |
b5321f30 | 11948 | intel_ring_emit_reg(ring, DERRMR); |
bde13ebd CW |
11949 | intel_ring_emit(ring, |
11950 | i915_ggtt_offset(req->engine->scratch) + 256); | |
5db94019 | 11951 | if (IS_GEN8(dev_priv)) { |
b5321f30 CW |
11952 | intel_ring_emit(ring, 0); |
11953 | intel_ring_emit(ring, MI_NOOP); | |
5a21b665 DV |
11954 | } |
11955 | } | |
11956 | ||
b5321f30 | 11957 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
72618ebf VS |
11958 | intel_ring_emit(ring, fb->pitches[0] | |
11959 | intel_fb_modifier_to_tiling(fb->modifier[0])); | |
b5321f30 CW |
11960 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset); |
11961 | intel_ring_emit(ring, (MI_NOOP)); | |
5a21b665 DV |
11962 | |
11963 | return 0; | |
11964 | } | |
11965 | ||
11966 | static bool use_mmio_flip(struct intel_engine_cs *engine, | |
11967 | struct drm_i915_gem_object *obj) | |
11968 | { | |
11969 | /* | |
11970 | * This is not being used for older platforms, because | |
11971 | * non-availability of flip done interrupt forces us to use | |
11972 | * CS flips. Older platforms derive flip done using some clever | |
11973 | * tricks involving the flip_pending status bits and vblank irqs. | |
11974 | * So using MMIO flips there would disrupt this mechanism. | |
11975 | */ | |
11976 | ||
11977 | if (engine == NULL) | |
11978 | return true; | |
11979 | ||
11980 | if (INTEL_GEN(engine->i915) < 5) | |
11981 | return false; | |
11982 | ||
11983 | if (i915.use_mmio_flip < 0) | |
11984 | return false; | |
11985 | else if (i915.use_mmio_flip > 0) | |
11986 | return true; | |
11987 | else if (i915.enable_execlists) | |
11988 | return true; | |
c37efb99 | 11989 | |
d07f0e59 | 11990 | return engine != i915_gem_object_last_write_engine(obj); |
5a21b665 DV |
11991 | } |
11992 | ||
11993 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, | |
11994 | unsigned int rotation, | |
11995 | struct intel_flip_work *work) | |
11996 | { | |
11997 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 11998 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
11999 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; |
12000 | const enum pipe pipe = intel_crtc->pipe; | |
d2196774 | 12001 | u32 ctl, stride = skl_plane_stride(fb, 0, rotation); |
5a21b665 DV |
12002 | |
12003 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
12004 | ctl &= ~PLANE_CTL_TILED_MASK; | |
12005 | switch (fb->modifier[0]) { | |
12006 | case DRM_FORMAT_MOD_NONE: | |
12007 | break; | |
12008 | case I915_FORMAT_MOD_X_TILED: | |
12009 | ctl |= PLANE_CTL_TILED_X; | |
12010 | break; | |
12011 | case I915_FORMAT_MOD_Y_TILED: | |
12012 | ctl |= PLANE_CTL_TILED_Y; | |
12013 | break; | |
12014 | case I915_FORMAT_MOD_Yf_TILED: | |
12015 | ctl |= PLANE_CTL_TILED_YF; | |
12016 | break; | |
12017 | default: | |
12018 | MISSING_CASE(fb->modifier[0]); | |
12019 | } | |
12020 | ||
5a21b665 DV |
12021 | /* |
12022 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
12023 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
12024 | */ | |
12025 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
12026 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
12027 | ||
12028 | I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); | |
12029 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
12030 | } | |
12031 | ||
12032 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, | |
12033 | struct intel_flip_work *work) | |
12034 | { | |
12035 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 12036 | struct drm_i915_private *dev_priv = to_i915(dev); |
72618ebf | 12037 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; |
5a21b665 DV |
12038 | i915_reg_t reg = DSPCNTR(intel_crtc->plane); |
12039 | u32 dspcntr; | |
12040 | ||
12041 | dspcntr = I915_READ(reg); | |
12042 | ||
72618ebf | 12043 | if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) |
5a21b665 DV |
12044 | dspcntr |= DISPPLANE_TILED; |
12045 | else | |
12046 | dspcntr &= ~DISPPLANE_TILED; | |
12047 | ||
12048 | I915_WRITE(reg, dspcntr); | |
12049 | ||
12050 | I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); | |
12051 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
12052 | } | |
12053 | ||
12054 | static void intel_mmio_flip_work_func(struct work_struct *w) | |
12055 | { | |
12056 | struct intel_flip_work *work = | |
12057 | container_of(w, struct intel_flip_work, mmio_work); | |
12058 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); | |
12059 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
12060 | struct intel_framebuffer *intel_fb = | |
12061 | to_intel_framebuffer(crtc->base.primary->fb); | |
12062 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
12063 | ||
d07f0e59 | 12064 | WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0); |
5a21b665 DV |
12065 | |
12066 | intel_pipe_update_start(crtc); | |
12067 | ||
12068 | if (INTEL_GEN(dev_priv) >= 9) | |
12069 | skl_do_mmio_flip(crtc, work->rotation, work); | |
12070 | else | |
12071 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
12072 | ilk_do_mmio_flip(crtc, work); | |
12073 | ||
12074 | intel_pipe_update_end(crtc, work); | |
12075 | } | |
12076 | ||
12077 | static int intel_default_queue_flip(struct drm_device *dev, | |
12078 | struct drm_crtc *crtc, | |
12079 | struct drm_framebuffer *fb, | |
12080 | struct drm_i915_gem_object *obj, | |
12081 | struct drm_i915_gem_request *req, | |
12082 | uint32_t flags) | |
12083 | { | |
12084 | return -ENODEV; | |
12085 | } | |
12086 | ||
12087 | static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv, | |
12088 | struct intel_crtc *intel_crtc, | |
12089 | struct intel_flip_work *work) | |
12090 | { | |
12091 | u32 addr, vblank; | |
12092 | ||
12093 | if (!atomic_read(&work->pending)) | |
12094 | return false; | |
12095 | ||
12096 | smp_rmb(); | |
12097 | ||
12098 | vblank = intel_crtc_get_vblank_counter(intel_crtc); | |
12099 | if (work->flip_ready_vblank == 0) { | |
12100 | if (work->flip_queued_req && | |
f69a02c9 | 12101 | !i915_gem_request_completed(work->flip_queued_req)) |
5a21b665 DV |
12102 | return false; |
12103 | ||
12104 | work->flip_ready_vblank = vblank; | |
12105 | } | |
12106 | ||
12107 | if (vblank - work->flip_ready_vblank < 3) | |
12108 | return false; | |
12109 | ||
12110 | /* Potential stall - if we see that the flip has happened, | |
12111 | * assume a missed interrupt. */ | |
12112 | if (INTEL_GEN(dev_priv) >= 4) | |
12113 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
12114 | else | |
12115 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
12116 | ||
12117 | /* There is a potential issue here with a false positive after a flip | |
12118 | * to the same address. We could address this by checking for a | |
12119 | * non-incrementing frame counter. | |
12120 | */ | |
12121 | return addr == work->gtt_offset; | |
12122 | } | |
12123 | ||
12124 | void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe) | |
12125 | { | |
91c8a326 | 12126 | struct drm_device *dev = &dev_priv->drm; |
5a21b665 DV |
12127 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
12128 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12129 | struct intel_flip_work *work; | |
12130 | ||
12131 | WARN_ON(!in_interrupt()); | |
12132 | ||
12133 | if (crtc == NULL) | |
12134 | return; | |
12135 | ||
12136 | spin_lock(&dev->event_lock); | |
12137 | work = intel_crtc->flip_work; | |
12138 | ||
12139 | if (work != NULL && !is_mmio_work(work) && | |
12140 | __pageflip_stall_check_cs(dev_priv, intel_crtc, work)) { | |
12141 | WARN_ONCE(1, | |
12142 | "Kicking stuck page flip: queued at %d, now %d\n", | |
12143 | work->flip_queued_vblank, intel_crtc_get_vblank_counter(intel_crtc)); | |
12144 | page_flip_completed(intel_crtc); | |
12145 | work = NULL; | |
12146 | } | |
12147 | ||
12148 | if (work != NULL && !is_mmio_work(work) && | |
12149 | intel_crtc_get_vblank_counter(intel_crtc) - work->flip_queued_vblank > 1) | |
12150 | intel_queue_rps_boost_for_request(work->flip_queued_req); | |
12151 | spin_unlock(&dev->event_lock); | |
12152 | } | |
12153 | ||
12154 | static int intel_crtc_page_flip(struct drm_crtc *crtc, | |
12155 | struct drm_framebuffer *fb, | |
12156 | struct drm_pending_vblank_event *event, | |
12157 | uint32_t page_flip_flags) | |
12158 | { | |
12159 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 12160 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
12161 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
12162 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
12163 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12164 | struct drm_plane *primary = crtc->primary; | |
12165 | enum pipe pipe = intel_crtc->pipe; | |
12166 | struct intel_flip_work *work; | |
12167 | struct intel_engine_cs *engine; | |
12168 | bool mmio_flip; | |
8e637178 | 12169 | struct drm_i915_gem_request *request; |
058d88c4 | 12170 | struct i915_vma *vma; |
5a21b665 DV |
12171 | int ret; |
12172 | ||
12173 | /* | |
12174 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
12175 | * check to be safe. In the future we may enable pageflipping from | |
12176 | * a disabled primary plane. | |
12177 | */ | |
12178 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
12179 | return -EBUSY; | |
12180 | ||
12181 | /* Can't change pixel format via MI display flips. */ | |
12182 | if (fb->pixel_format != crtc->primary->fb->pixel_format) | |
12183 | return -EINVAL; | |
12184 | ||
12185 | /* | |
12186 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
12187 | * Note that pitch changes could also affect these register. | |
12188 | */ | |
12189 | if (INTEL_INFO(dev)->gen > 3 && | |
12190 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || | |
12191 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
12192 | return -EINVAL; | |
12193 | ||
12194 | if (i915_terminally_wedged(&dev_priv->gpu_error)) | |
12195 | goto out_hang; | |
12196 | ||
12197 | work = kzalloc(sizeof(*work), GFP_KERNEL); | |
12198 | if (work == NULL) | |
12199 | return -ENOMEM; | |
12200 | ||
12201 | work->event = event; | |
12202 | work->crtc = crtc; | |
12203 | work->old_fb = old_fb; | |
12204 | INIT_WORK(&work->unpin_work, intel_unpin_work_fn); | |
12205 | ||
12206 | ret = drm_crtc_vblank_get(crtc); | |
12207 | if (ret) | |
12208 | goto free_work; | |
12209 | ||
12210 | /* We borrow the event spin lock for protecting flip_work */ | |
12211 | spin_lock_irq(&dev->event_lock); | |
12212 | if (intel_crtc->flip_work) { | |
12213 | /* Before declaring the flip queue wedged, check if | |
12214 | * the hardware completed the operation behind our backs. | |
12215 | */ | |
12216 | if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) { | |
12217 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
12218 | page_flip_completed(intel_crtc); | |
12219 | } else { | |
12220 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
12221 | spin_unlock_irq(&dev->event_lock); | |
12222 | ||
12223 | drm_crtc_vblank_put(crtc); | |
12224 | kfree(work); | |
12225 | return -EBUSY; | |
12226 | } | |
12227 | } | |
12228 | intel_crtc->flip_work = work; | |
12229 | spin_unlock_irq(&dev->event_lock); | |
12230 | ||
12231 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) | |
12232 | flush_workqueue(dev_priv->wq); | |
12233 | ||
12234 | /* Reference the objects for the scheduled work. */ | |
12235 | drm_framebuffer_reference(work->old_fb); | |
5a21b665 DV |
12236 | |
12237 | crtc->primary->fb = fb; | |
12238 | update_state_fb(crtc->primary); | |
faf68d92 | 12239 | |
25dc556a | 12240 | work->pending_flip_obj = i915_gem_object_get(obj); |
5a21b665 DV |
12241 | |
12242 | ret = i915_mutex_lock_interruptible(dev); | |
12243 | if (ret) | |
12244 | goto cleanup; | |
12245 | ||
8af29b0c CW |
12246 | intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error); |
12247 | if (i915_reset_in_progress_or_wedged(&dev_priv->gpu_error)) { | |
5a21b665 DV |
12248 | ret = -EIO; |
12249 | goto cleanup; | |
12250 | } | |
12251 | ||
12252 | atomic_inc(&intel_crtc->unpin_work_count); | |
12253 | ||
9beb5fea | 12254 | if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) |
5a21b665 DV |
12255 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; |
12256 | ||
920a14b2 | 12257 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
3b3f1650 | 12258 | engine = dev_priv->engine[BCS]; |
72618ebf | 12259 | if (fb->modifier[0] != old_fb->modifier[0]) |
5a21b665 DV |
12260 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
12261 | engine = NULL; | |
fd6b8f43 | 12262 | } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) { |
3b3f1650 | 12263 | engine = dev_priv->engine[BCS]; |
5a21b665 | 12264 | } else if (INTEL_INFO(dev)->gen >= 7) { |
d07f0e59 | 12265 | engine = i915_gem_object_last_write_engine(obj); |
5a21b665 | 12266 | if (engine == NULL || engine->id != RCS) |
3b3f1650 | 12267 | engine = dev_priv->engine[BCS]; |
5a21b665 | 12268 | } else { |
3b3f1650 | 12269 | engine = dev_priv->engine[RCS]; |
5a21b665 DV |
12270 | } |
12271 | ||
12272 | mmio_flip = use_mmio_flip(engine, obj); | |
12273 | ||
058d88c4 CW |
12274 | vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation); |
12275 | if (IS_ERR(vma)) { | |
12276 | ret = PTR_ERR(vma); | |
5a21b665 | 12277 | goto cleanup_pending; |
058d88c4 | 12278 | } |
5a21b665 | 12279 | |
6687c906 | 12280 | work->gtt_offset = intel_fb_gtt_offset(fb, primary->state->rotation); |
5a21b665 DV |
12281 | work->gtt_offset += intel_crtc->dspaddr_offset; |
12282 | work->rotation = crtc->primary->state->rotation; | |
12283 | ||
1f061316 PZ |
12284 | /* |
12285 | * There's the potential that the next frame will not be compatible with | |
12286 | * FBC, so we want to call pre_update() before the actual page flip. | |
12287 | * The problem is that pre_update() caches some information about the fb | |
12288 | * object, so we want to do this only after the object is pinned. Let's | |
12289 | * be on the safe side and do this immediately before scheduling the | |
12290 | * flip. | |
12291 | */ | |
12292 | intel_fbc_pre_update(intel_crtc, intel_crtc->config, | |
12293 | to_intel_plane_state(primary->state)); | |
12294 | ||
5a21b665 DV |
12295 | if (mmio_flip) { |
12296 | INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func); | |
6277c8d0 | 12297 | queue_work(system_unbound_wq, &work->mmio_work); |
5a21b665 | 12298 | } else { |
8e637178 CW |
12299 | request = i915_gem_request_alloc(engine, engine->last_context); |
12300 | if (IS_ERR(request)) { | |
12301 | ret = PTR_ERR(request); | |
12302 | goto cleanup_unpin; | |
12303 | } | |
12304 | ||
a2bc4695 | 12305 | ret = i915_gem_request_await_object(request, obj, false); |
8e637178 CW |
12306 | if (ret) |
12307 | goto cleanup_request; | |
12308 | ||
5a21b665 DV |
12309 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, |
12310 | page_flip_flags); | |
12311 | if (ret) | |
8e637178 | 12312 | goto cleanup_request; |
5a21b665 DV |
12313 | |
12314 | intel_mark_page_flip_active(intel_crtc, work); | |
12315 | ||
8e637178 | 12316 | work->flip_queued_req = i915_gem_request_get(request); |
5a21b665 DV |
12317 | i915_add_request_no_flush(request); |
12318 | } | |
12319 | ||
12320 | i915_gem_track_fb(intel_fb_obj(old_fb), obj, | |
12321 | to_intel_plane(primary)->frontbuffer_bit); | |
12322 | mutex_unlock(&dev->struct_mutex); | |
12323 | ||
5748b6a1 | 12324 | intel_frontbuffer_flip_prepare(to_i915(dev), |
5a21b665 DV |
12325 | to_intel_plane(primary)->frontbuffer_bit); |
12326 | ||
12327 | trace_i915_flip_request(intel_crtc->plane, obj); | |
12328 | ||
12329 | return 0; | |
12330 | ||
8e637178 CW |
12331 | cleanup_request: |
12332 | i915_add_request_no_flush(request); | |
5a21b665 DV |
12333 | cleanup_unpin: |
12334 | intel_unpin_fb_obj(fb, crtc->primary->state->rotation); | |
12335 | cleanup_pending: | |
5a21b665 DV |
12336 | atomic_dec(&intel_crtc->unpin_work_count); |
12337 | mutex_unlock(&dev->struct_mutex); | |
12338 | cleanup: | |
12339 | crtc->primary->fb = old_fb; | |
12340 | update_state_fb(crtc->primary); | |
12341 | ||
f0cd5182 | 12342 | i915_gem_object_put(obj); |
5a21b665 DV |
12343 | drm_framebuffer_unreference(work->old_fb); |
12344 | ||
12345 | spin_lock_irq(&dev->event_lock); | |
12346 | intel_crtc->flip_work = NULL; | |
12347 | spin_unlock_irq(&dev->event_lock); | |
12348 | ||
12349 | drm_crtc_vblank_put(crtc); | |
12350 | free_work: | |
12351 | kfree(work); | |
12352 | ||
12353 | if (ret == -EIO) { | |
12354 | struct drm_atomic_state *state; | |
12355 | struct drm_plane_state *plane_state; | |
12356 | ||
12357 | out_hang: | |
12358 | state = drm_atomic_state_alloc(dev); | |
12359 | if (!state) | |
12360 | return -ENOMEM; | |
12361 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); | |
12362 | ||
12363 | retry: | |
12364 | plane_state = drm_atomic_get_plane_state(state, primary); | |
12365 | ret = PTR_ERR_OR_ZERO(plane_state); | |
12366 | if (!ret) { | |
12367 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
12368 | ||
12369 | ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); | |
12370 | if (!ret) | |
12371 | ret = drm_atomic_commit(state); | |
12372 | } | |
12373 | ||
12374 | if (ret == -EDEADLK) { | |
12375 | drm_modeset_backoff(state->acquire_ctx); | |
12376 | drm_atomic_state_clear(state); | |
12377 | goto retry; | |
12378 | } | |
12379 | ||
0853695c | 12380 | drm_atomic_state_put(state); |
5a21b665 DV |
12381 | |
12382 | if (ret == 0 && event) { | |
12383 | spin_lock_irq(&dev->event_lock); | |
12384 | drm_crtc_send_vblank_event(crtc, event); | |
12385 | spin_unlock_irq(&dev->event_lock); | |
12386 | } | |
12387 | } | |
12388 | return ret; | |
12389 | } | |
12390 | ||
12391 | ||
12392 | /** | |
12393 | * intel_wm_need_update - Check whether watermarks need updating | |
12394 | * @plane: drm plane | |
12395 | * @state: new plane state | |
12396 | * | |
12397 | * Check current plane state versus the new one to determine whether | |
12398 | * watermarks need to be recalculated. | |
12399 | * | |
12400 | * Returns true or false. | |
12401 | */ | |
12402 | static bool intel_wm_need_update(struct drm_plane *plane, | |
12403 | struct drm_plane_state *state) | |
12404 | { | |
12405 | struct intel_plane_state *new = to_intel_plane_state(state); | |
12406 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); | |
12407 | ||
12408 | /* Update watermarks on tiling or size changes. */ | |
936e71e3 | 12409 | if (new->base.visible != cur->base.visible) |
5a21b665 DV |
12410 | return true; |
12411 | ||
12412 | if (!cur->base.fb || !new->base.fb) | |
12413 | return false; | |
12414 | ||
12415 | if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] || | |
12416 | cur->base.rotation != new->base.rotation || | |
936e71e3 VS |
12417 | drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) || |
12418 | drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) || | |
12419 | drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) || | |
12420 | drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst)) | |
5a21b665 DV |
12421 | return true; |
12422 | ||
12423 | return false; | |
12424 | } | |
12425 | ||
12426 | static bool needs_scaling(struct intel_plane_state *state) | |
12427 | { | |
936e71e3 VS |
12428 | int src_w = drm_rect_width(&state->base.src) >> 16; |
12429 | int src_h = drm_rect_height(&state->base.src) >> 16; | |
12430 | int dst_w = drm_rect_width(&state->base.dst); | |
12431 | int dst_h = drm_rect_height(&state->base.dst); | |
5a21b665 DV |
12432 | |
12433 | return (src_w != dst_w || src_h != dst_h); | |
12434 | } | |
d21fbe87 | 12435 | |
da20eabd ML |
12436 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
12437 | struct drm_plane_state *plane_state) | |
12438 | { | |
ab1d3a0e | 12439 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
da20eabd ML |
12440 | struct drm_crtc *crtc = crtc_state->crtc; |
12441 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12442 | struct drm_plane *plane = plane_state->plane; | |
12443 | struct drm_device *dev = crtc->dev; | |
ed4a6a7c | 12444 | struct drm_i915_private *dev_priv = to_i915(dev); |
da20eabd ML |
12445 | struct intel_plane_state *old_plane_state = |
12446 | to_intel_plane_state(plane->state); | |
da20eabd ML |
12447 | bool mode_changed = needs_modeset(crtc_state); |
12448 | bool was_crtc_enabled = crtc->state->active; | |
12449 | bool is_crtc_enabled = crtc_state->active; | |
da20eabd ML |
12450 | bool turn_off, turn_on, visible, was_visible; |
12451 | struct drm_framebuffer *fb = plane_state->fb; | |
78108b7c | 12452 | int ret; |
da20eabd | 12453 | |
55b8f2a7 | 12454 | if (INTEL_GEN(dev_priv) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) { |
da20eabd ML |
12455 | ret = skl_update_scaler_plane( |
12456 | to_intel_crtc_state(crtc_state), | |
12457 | to_intel_plane_state(plane_state)); | |
12458 | if (ret) | |
12459 | return ret; | |
12460 | } | |
12461 | ||
936e71e3 VS |
12462 | was_visible = old_plane_state->base.visible; |
12463 | visible = to_intel_plane_state(plane_state)->base.visible; | |
da20eabd ML |
12464 | |
12465 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
12466 | was_visible = false; | |
12467 | ||
35c08f43 ML |
12468 | /* |
12469 | * Visibility is calculated as if the crtc was on, but | |
12470 | * after scaler setup everything depends on it being off | |
12471 | * when the crtc isn't active. | |
f818ffea VS |
12472 | * |
12473 | * FIXME this is wrong for watermarks. Watermarks should also | |
12474 | * be computed as if the pipe would be active. Perhaps move | |
12475 | * per-plane wm computation to the .check_plane() hook, and | |
12476 | * only combine the results from all planes in the current place? | |
35c08f43 ML |
12477 | */ |
12478 | if (!is_crtc_enabled) | |
936e71e3 | 12479 | to_intel_plane_state(plane_state)->base.visible = visible = false; |
da20eabd ML |
12480 | |
12481 | if (!was_visible && !visible) | |
12482 | return 0; | |
12483 | ||
e8861675 ML |
12484 | if (fb != old_plane_state->base.fb) |
12485 | pipe_config->fb_changed = true; | |
12486 | ||
da20eabd ML |
12487 | turn_off = was_visible && (!visible || mode_changed); |
12488 | turn_on = visible && (!was_visible || mode_changed); | |
12489 | ||
72660ce0 | 12490 | DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n", |
78108b7c VS |
12491 | intel_crtc->base.base.id, |
12492 | intel_crtc->base.name, | |
72660ce0 VS |
12493 | plane->base.id, plane->name, |
12494 | fb ? fb->base.id : -1); | |
da20eabd | 12495 | |
72660ce0 VS |
12496 | DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n", |
12497 | plane->base.id, plane->name, | |
12498 | was_visible, visible, | |
da20eabd ML |
12499 | turn_off, turn_on, mode_changed); |
12500 | ||
caed361d VS |
12501 | if (turn_on) { |
12502 | pipe_config->update_wm_pre = true; | |
12503 | ||
12504 | /* must disable cxsr around plane enable/disable */ | |
12505 | if (plane->type != DRM_PLANE_TYPE_CURSOR) | |
12506 | pipe_config->disable_cxsr = true; | |
12507 | } else if (turn_off) { | |
12508 | pipe_config->update_wm_post = true; | |
92826fcd | 12509 | |
852eb00d | 12510 | /* must disable cxsr around plane enable/disable */ |
e8861675 | 12511 | if (plane->type != DRM_PLANE_TYPE_CURSOR) |
ab1d3a0e | 12512 | pipe_config->disable_cxsr = true; |
852eb00d | 12513 | } else if (intel_wm_need_update(plane, plane_state)) { |
caed361d VS |
12514 | /* FIXME bollocks */ |
12515 | pipe_config->update_wm_pre = true; | |
12516 | pipe_config->update_wm_post = true; | |
852eb00d | 12517 | } |
da20eabd | 12518 | |
ed4a6a7c | 12519 | /* Pre-gen9 platforms need two-step watermark updates */ |
caed361d VS |
12520 | if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) && |
12521 | INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks) | |
ed4a6a7c MR |
12522 | to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true; |
12523 | ||
8be6ca85 | 12524 | if (visible || was_visible) |
cd202f69 | 12525 | pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit; |
a9ff8714 | 12526 | |
31ae71fc ML |
12527 | /* |
12528 | * WaCxSRDisabledForSpriteScaling:ivb | |
12529 | * | |
12530 | * cstate->update_wm was already set above, so this flag will | |
12531 | * take effect when we commit and program watermarks. | |
12532 | */ | |
fd6b8f43 | 12533 | if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev_priv) && |
31ae71fc ML |
12534 | needs_scaling(to_intel_plane_state(plane_state)) && |
12535 | !needs_scaling(old_plane_state)) | |
12536 | pipe_config->disable_lp_wm = true; | |
d21fbe87 | 12537 | |
da20eabd ML |
12538 | return 0; |
12539 | } | |
12540 | ||
6d3a1ce7 ML |
12541 | static bool encoders_cloneable(const struct intel_encoder *a, |
12542 | const struct intel_encoder *b) | |
12543 | { | |
12544 | /* masks could be asymmetric, so check both ways */ | |
12545 | return a == b || (a->cloneable & (1 << b->type) && | |
12546 | b->cloneable & (1 << a->type)); | |
12547 | } | |
12548 | ||
12549 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
12550 | struct intel_crtc *crtc, | |
12551 | struct intel_encoder *encoder) | |
12552 | { | |
12553 | struct intel_encoder *source_encoder; | |
12554 | struct drm_connector *connector; | |
12555 | struct drm_connector_state *connector_state; | |
12556 | int i; | |
12557 | ||
12558 | for_each_connector_in_state(state, connector, connector_state, i) { | |
12559 | if (connector_state->crtc != &crtc->base) | |
12560 | continue; | |
12561 | ||
12562 | source_encoder = | |
12563 | to_intel_encoder(connector_state->best_encoder); | |
12564 | if (!encoders_cloneable(encoder, source_encoder)) | |
12565 | return false; | |
12566 | } | |
12567 | ||
12568 | return true; | |
12569 | } | |
12570 | ||
6d3a1ce7 ML |
12571 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, |
12572 | struct drm_crtc_state *crtc_state) | |
12573 | { | |
cf5a15be | 12574 | struct drm_device *dev = crtc->dev; |
fac5e23e | 12575 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d3a1ce7 | 12576 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
12577 | struct intel_crtc_state *pipe_config = |
12578 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 12579 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 12580 | int ret; |
6d3a1ce7 ML |
12581 | bool mode_changed = needs_modeset(crtc_state); |
12582 | ||
852eb00d | 12583 | if (mode_changed && !crtc_state->active) |
caed361d | 12584 | pipe_config->update_wm_post = true; |
eddfcbcd | 12585 | |
ad421372 ML |
12586 | if (mode_changed && crtc_state->enable && |
12587 | dev_priv->display.crtc_compute_clock && | |
8106ddbd | 12588 | !WARN_ON(pipe_config->shared_dpll)) { |
ad421372 ML |
12589 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, |
12590 | pipe_config); | |
12591 | if (ret) | |
12592 | return ret; | |
12593 | } | |
12594 | ||
82cf435b LL |
12595 | if (crtc_state->color_mgmt_changed) { |
12596 | ret = intel_color_check(crtc, crtc_state); | |
12597 | if (ret) | |
12598 | return ret; | |
e7852a4b LL |
12599 | |
12600 | /* | |
12601 | * Changing color management on Intel hardware is | |
12602 | * handled as part of planes update. | |
12603 | */ | |
12604 | crtc_state->planes_changed = true; | |
82cf435b LL |
12605 | } |
12606 | ||
e435d6e5 | 12607 | ret = 0; |
86c8bbbe | 12608 | if (dev_priv->display.compute_pipe_wm) { |
e3bddded | 12609 | ret = dev_priv->display.compute_pipe_wm(pipe_config); |
ed4a6a7c MR |
12610 | if (ret) { |
12611 | DRM_DEBUG_KMS("Target pipe watermarks are invalid\n"); | |
12612 | return ret; | |
12613 | } | |
12614 | } | |
12615 | ||
12616 | if (dev_priv->display.compute_intermediate_wm && | |
12617 | !to_intel_atomic_state(state)->skip_intermediate_wm) { | |
12618 | if (WARN_ON(!dev_priv->display.compute_pipe_wm)) | |
12619 | return 0; | |
12620 | ||
12621 | /* | |
12622 | * Calculate 'intermediate' watermarks that satisfy both the | |
12623 | * old state and the new state. We can program these | |
12624 | * immediately. | |
12625 | */ | |
12626 | ret = dev_priv->display.compute_intermediate_wm(crtc->dev, | |
12627 | intel_crtc, | |
12628 | pipe_config); | |
12629 | if (ret) { | |
12630 | DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n"); | |
86c8bbbe | 12631 | return ret; |
ed4a6a7c | 12632 | } |
e3d5457c VS |
12633 | } else if (dev_priv->display.compute_intermediate_wm) { |
12634 | if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9) | |
12635 | pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal; | |
86c8bbbe MR |
12636 | } |
12637 | ||
e435d6e5 ML |
12638 | if (INTEL_INFO(dev)->gen >= 9) { |
12639 | if (mode_changed) | |
12640 | ret = skl_update_scaler_crtc(pipe_config); | |
12641 | ||
12642 | if (!ret) | |
12643 | ret = intel_atomic_setup_scalers(dev, intel_crtc, | |
12644 | pipe_config); | |
12645 | } | |
12646 | ||
12647 | return ret; | |
6d3a1ce7 ML |
12648 | } |
12649 | ||
65b38e0d | 12650 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 | 12651 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
5a21b665 DV |
12652 | .atomic_begin = intel_begin_crtc_commit, |
12653 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 12654 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
12655 | }; |
12656 | ||
d29b2f9d ACO |
12657 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
12658 | { | |
12659 | struct intel_connector *connector; | |
12660 | ||
12661 | for_each_intel_connector(dev, connector) { | |
8863dc7f DV |
12662 | if (connector->base.state->crtc) |
12663 | drm_connector_unreference(&connector->base); | |
12664 | ||
d29b2f9d ACO |
12665 | if (connector->base.encoder) { |
12666 | connector->base.state->best_encoder = | |
12667 | connector->base.encoder; | |
12668 | connector->base.state->crtc = | |
12669 | connector->base.encoder->crtc; | |
8863dc7f DV |
12670 | |
12671 | drm_connector_reference(&connector->base); | |
d29b2f9d ACO |
12672 | } else { |
12673 | connector->base.state->best_encoder = NULL; | |
12674 | connector->base.state->crtc = NULL; | |
12675 | } | |
12676 | } | |
12677 | } | |
12678 | ||
050f7aeb | 12679 | static void |
eba905b2 | 12680 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 12681 | struct intel_crtc_state *pipe_config) |
050f7aeb | 12682 | { |
6a2a5c5d | 12683 | const struct drm_display_info *info = &connector->base.display_info; |
050f7aeb DV |
12684 | int bpp = pipe_config->pipe_bpp; |
12685 | ||
12686 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
6a2a5c5d VS |
12687 | connector->base.base.id, |
12688 | connector->base.name); | |
050f7aeb DV |
12689 | |
12690 | /* Don't use an invalid EDID bpc value */ | |
6a2a5c5d | 12691 | if (info->bpc != 0 && info->bpc * 3 < bpp) { |
050f7aeb | 12692 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", |
6a2a5c5d VS |
12693 | bpp, info->bpc * 3); |
12694 | pipe_config->pipe_bpp = info->bpc * 3; | |
050f7aeb DV |
12695 | } |
12696 | ||
196f954e | 12697 | /* Clamp bpp to 8 on screens without EDID 1.4 */ |
6a2a5c5d | 12698 | if (info->bpc == 0 && bpp > 24) { |
196f954e MK |
12699 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", |
12700 | bpp); | |
12701 | pipe_config->pipe_bpp = 24; | |
050f7aeb DV |
12702 | } |
12703 | } | |
12704 | ||
4e53c2e0 | 12705 | static int |
050f7aeb | 12706 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 12707 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 12708 | { |
9beb5fea | 12709 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1486017f | 12710 | struct drm_atomic_state *state; |
da3ced29 ACO |
12711 | struct drm_connector *connector; |
12712 | struct drm_connector_state *connector_state; | |
1486017f | 12713 | int bpp, i; |
4e53c2e0 | 12714 | |
9beb5fea TU |
12715 | if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
12716 | IS_CHERRYVIEW(dev_priv))) | |
4e53c2e0 | 12717 | bpp = 10*3; |
9beb5fea | 12718 | else if (INTEL_GEN(dev_priv) >= 5) |
d328c9d7 DV |
12719 | bpp = 12*3; |
12720 | else | |
12721 | bpp = 8*3; | |
12722 | ||
4e53c2e0 | 12723 | |
4e53c2e0 DV |
12724 | pipe_config->pipe_bpp = bpp; |
12725 | ||
1486017f ACO |
12726 | state = pipe_config->base.state; |
12727 | ||
4e53c2e0 | 12728 | /* Clamp display bpp to EDID value */ |
da3ced29 ACO |
12729 | for_each_connector_in_state(state, connector, connector_state, i) { |
12730 | if (connector_state->crtc != &crtc->base) | |
4e53c2e0 DV |
12731 | continue; |
12732 | ||
da3ced29 ACO |
12733 | connected_sink_compute_bpp(to_intel_connector(connector), |
12734 | pipe_config); | |
4e53c2e0 DV |
12735 | } |
12736 | ||
12737 | return bpp; | |
12738 | } | |
12739 | ||
644db711 DV |
12740 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
12741 | { | |
12742 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
12743 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 12744 | mode->crtc_clock, |
644db711 DV |
12745 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
12746 | mode->crtc_hsync_end, mode->crtc_htotal, | |
12747 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
12748 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
12749 | } | |
12750 | ||
c0b03411 | 12751 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 12752 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
12753 | const char *context) |
12754 | { | |
6a60cd87 | 12755 | struct drm_device *dev = crtc->base.dev; |
4f8036a2 | 12756 | struct drm_i915_private *dev_priv = to_i915(dev); |
6a60cd87 CK |
12757 | struct drm_plane *plane; |
12758 | struct intel_plane *intel_plane; | |
12759 | struct intel_plane_state *state; | |
12760 | struct drm_framebuffer *fb; | |
12761 | ||
78108b7c VS |
12762 | DRM_DEBUG_KMS("[CRTC:%d:%s]%s config %p for pipe %c\n", |
12763 | crtc->base.base.id, crtc->base.name, | |
6a60cd87 | 12764 | context, pipe_config, pipe_name(crtc->pipe)); |
c0b03411 | 12765 | |
da205630 | 12766 | DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder)); |
c0b03411 DV |
12767 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", |
12768 | pipe_config->pipe_bpp, pipe_config->dither); | |
12769 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
12770 | pipe_config->has_pch_encoder, | |
12771 | pipe_config->fdi_lanes, | |
12772 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
12773 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
12774 | pipe_config->fdi_m_n.tu); | |
90a6b7b0 | 12775 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
37a5650b | 12776 | intel_crtc_has_dp_encoder(pipe_config), |
90a6b7b0 | 12777 | pipe_config->lane_count, |
eb14cb74 VS |
12778 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, |
12779 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
12780 | pipe_config->dp_m_n.tu); | |
b95af8be | 12781 | |
90a6b7b0 | 12782 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", |
37a5650b | 12783 | intel_crtc_has_dp_encoder(pipe_config), |
90a6b7b0 | 12784 | pipe_config->lane_count, |
b95af8be VK |
12785 | pipe_config->dp_m2_n2.gmch_m, |
12786 | pipe_config->dp_m2_n2.gmch_n, | |
12787 | pipe_config->dp_m2_n2.link_m, | |
12788 | pipe_config->dp_m2_n2.link_n, | |
12789 | pipe_config->dp_m2_n2.tu); | |
12790 | ||
55072d19 DV |
12791 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
12792 | pipe_config->has_audio, | |
12793 | pipe_config->has_infoframe); | |
12794 | ||
c0b03411 | 12795 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 12796 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 12797 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
12798 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
12799 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 12800 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
12801 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
12802 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
0ec463d3 TU |
12803 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", |
12804 | crtc->num_scalers, | |
12805 | pipe_config->scaler_state.scaler_users, | |
12806 | pipe_config->scaler_state.scaler_id); | |
c0b03411 DV |
12807 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
12808 | pipe_config->gmch_pfit.control, | |
12809 | pipe_config->gmch_pfit.pgm_ratios, | |
12810 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 12811 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 12812 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
12813 | pipe_config->pch_pfit.size, |
12814 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 12815 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 12816 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
6a60cd87 | 12817 | |
e2d214ae | 12818 | if (IS_BROXTON(dev_priv)) { |
c856052a | 12819 | DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," |
415ff0f6 | 12820 | "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " |
c8453338 | 12821 | "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", |
415ff0f6 | 12822 | pipe_config->dpll_hw_state.ebb0, |
05712c15 | 12823 | pipe_config->dpll_hw_state.ebb4, |
415ff0f6 TU |
12824 | pipe_config->dpll_hw_state.pll0, |
12825 | pipe_config->dpll_hw_state.pll1, | |
12826 | pipe_config->dpll_hw_state.pll2, | |
12827 | pipe_config->dpll_hw_state.pll3, | |
12828 | pipe_config->dpll_hw_state.pll6, | |
12829 | pipe_config->dpll_hw_state.pll8, | |
05712c15 | 12830 | pipe_config->dpll_hw_state.pll9, |
c8453338 | 12831 | pipe_config->dpll_hw_state.pll10, |
415ff0f6 | 12832 | pipe_config->dpll_hw_state.pcsdw12); |
0853723b | 12833 | } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { |
c856052a | 12834 | DRM_DEBUG_KMS("dpll_hw_state: " |
415ff0f6 | 12835 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", |
415ff0f6 TU |
12836 | pipe_config->dpll_hw_state.ctrl1, |
12837 | pipe_config->dpll_hw_state.cfgcr1, | |
12838 | pipe_config->dpll_hw_state.cfgcr2); | |
4f8036a2 | 12839 | } else if (HAS_DDI(dev_priv)) { |
c856052a | 12840 | DRM_DEBUG_KMS("dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", |
00490c22 ML |
12841 | pipe_config->dpll_hw_state.wrpll, |
12842 | pipe_config->dpll_hw_state.spll); | |
415ff0f6 TU |
12843 | } else { |
12844 | DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " | |
12845 | "fp0: 0x%x, fp1: 0x%x\n", | |
12846 | pipe_config->dpll_hw_state.dpll, | |
12847 | pipe_config->dpll_hw_state.dpll_md, | |
12848 | pipe_config->dpll_hw_state.fp0, | |
12849 | pipe_config->dpll_hw_state.fp1); | |
12850 | } | |
12851 | ||
6a60cd87 CK |
12852 | DRM_DEBUG_KMS("planes on this crtc\n"); |
12853 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
d3828147 | 12854 | char *format_name; |
6a60cd87 CK |
12855 | intel_plane = to_intel_plane(plane); |
12856 | if (intel_plane->pipe != crtc->pipe) | |
12857 | continue; | |
12858 | ||
12859 | state = to_intel_plane_state(plane->state); | |
12860 | fb = state->base.fb; | |
12861 | if (!fb) { | |
1d577e02 VS |
12862 | DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n", |
12863 | plane->base.id, plane->name, state->scaler_id); | |
6a60cd87 CK |
12864 | continue; |
12865 | } | |
12866 | ||
90844f00 EE |
12867 | format_name = drm_get_format_name(fb->pixel_format); |
12868 | ||
1d577e02 VS |
12869 | DRM_DEBUG_KMS("[PLANE:%d:%s] enabled", |
12870 | plane->base.id, plane->name); | |
12871 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = %s", | |
90844f00 | 12872 | fb->base.id, fb->width, fb->height, format_name); |
1d577e02 VS |
12873 | DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n", |
12874 | state->scaler_id, | |
936e71e3 VS |
12875 | state->base.src.x1 >> 16, |
12876 | state->base.src.y1 >> 16, | |
12877 | drm_rect_width(&state->base.src) >> 16, | |
12878 | drm_rect_height(&state->base.src) >> 16, | |
12879 | state->base.dst.x1, state->base.dst.y1, | |
12880 | drm_rect_width(&state->base.dst), | |
12881 | drm_rect_height(&state->base.dst)); | |
90844f00 EE |
12882 | |
12883 | kfree(format_name); | |
6a60cd87 | 12884 | } |
c0b03411 DV |
12885 | } |
12886 | ||
5448a00d | 12887 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 12888 | { |
5448a00d | 12889 | struct drm_device *dev = state->dev; |
da3ced29 | 12890 | struct drm_connector *connector; |
00f0b378 | 12891 | unsigned int used_ports = 0; |
477321e0 | 12892 | unsigned int used_mst_ports = 0; |
00f0b378 VS |
12893 | |
12894 | /* | |
12895 | * Walk the connector list instead of the encoder | |
12896 | * list to detect the problem on ddi platforms | |
12897 | * where there's just one encoder per digital port. | |
12898 | */ | |
0bff4858 VS |
12899 | drm_for_each_connector(connector, dev) { |
12900 | struct drm_connector_state *connector_state; | |
12901 | struct intel_encoder *encoder; | |
12902 | ||
12903 | connector_state = drm_atomic_get_existing_connector_state(state, connector); | |
12904 | if (!connector_state) | |
12905 | connector_state = connector->state; | |
12906 | ||
5448a00d | 12907 | if (!connector_state->best_encoder) |
00f0b378 VS |
12908 | continue; |
12909 | ||
5448a00d ACO |
12910 | encoder = to_intel_encoder(connector_state->best_encoder); |
12911 | ||
12912 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
12913 | |
12914 | switch (encoder->type) { | |
12915 | unsigned int port_mask; | |
12916 | case INTEL_OUTPUT_UNKNOWN: | |
4f8036a2 | 12917 | if (WARN_ON(!HAS_DDI(to_i915(dev)))) |
00f0b378 | 12918 | break; |
cca0502b | 12919 | case INTEL_OUTPUT_DP: |
00f0b378 VS |
12920 | case INTEL_OUTPUT_HDMI: |
12921 | case INTEL_OUTPUT_EDP: | |
12922 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
12923 | ||
12924 | /* the same port mustn't appear more than once */ | |
12925 | if (used_ports & port_mask) | |
12926 | return false; | |
12927 | ||
12928 | used_ports |= port_mask; | |
477321e0 VS |
12929 | break; |
12930 | case INTEL_OUTPUT_DP_MST: | |
12931 | used_mst_ports |= | |
12932 | 1 << enc_to_mst(&encoder->base)->primary->port; | |
12933 | break; | |
00f0b378 VS |
12934 | default: |
12935 | break; | |
12936 | } | |
12937 | } | |
12938 | ||
477321e0 VS |
12939 | /* can't mix MST and SST/HDMI on the same port */ |
12940 | if (used_ports & used_mst_ports) | |
12941 | return false; | |
12942 | ||
00f0b378 VS |
12943 | return true; |
12944 | } | |
12945 | ||
83a57153 ACO |
12946 | static void |
12947 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
12948 | { | |
12949 | struct drm_crtc_state tmp_state; | |
663a3640 | 12950 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 | 12951 | struct intel_dpll_hw_state dpll_hw_state; |
8106ddbd | 12952 | struct intel_shared_dpll *shared_dpll; |
c4e2d043 | 12953 | bool force_thru; |
83a57153 | 12954 | |
7546a384 ACO |
12955 | /* FIXME: before the switch to atomic started, a new pipe_config was |
12956 | * kzalloc'd. Code that depends on any field being zero should be | |
12957 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
12958 | * only fields that are know to not cause problems are preserved. */ | |
12959 | ||
83a57153 | 12960 | tmp_state = crtc_state->base; |
663a3640 | 12961 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
12962 | shared_dpll = crtc_state->shared_dpll; |
12963 | dpll_hw_state = crtc_state->dpll_hw_state; | |
c4e2d043 | 12964 | force_thru = crtc_state->pch_pfit.force_thru; |
4978cc93 | 12965 | |
83a57153 | 12966 | memset(crtc_state, 0, sizeof *crtc_state); |
4978cc93 | 12967 | |
83a57153 | 12968 | crtc_state->base = tmp_state; |
663a3640 | 12969 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
12970 | crtc_state->shared_dpll = shared_dpll; |
12971 | crtc_state->dpll_hw_state = dpll_hw_state; | |
c4e2d043 | 12972 | crtc_state->pch_pfit.force_thru = force_thru; |
83a57153 ACO |
12973 | } |
12974 | ||
548ee15b | 12975 | static int |
b8cecdf5 | 12976 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 12977 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 12978 | { |
b359283a | 12979 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 12980 | struct intel_encoder *encoder; |
da3ced29 | 12981 | struct drm_connector *connector; |
0b901879 | 12982 | struct drm_connector_state *connector_state; |
d328c9d7 | 12983 | int base_bpp, ret = -EINVAL; |
0b901879 | 12984 | int i; |
e29c22c0 | 12985 | bool retry = true; |
ee7b9f93 | 12986 | |
83a57153 | 12987 | clear_intel_crtc_state(pipe_config); |
7758a113 | 12988 | |
e143a21c DV |
12989 | pipe_config->cpu_transcoder = |
12990 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 12991 | |
2960bc9c ID |
12992 | /* |
12993 | * Sanitize sync polarity flags based on requested ones. If neither | |
12994 | * positive or negative polarity is requested, treat this as meaning | |
12995 | * negative polarity. | |
12996 | */ | |
2d112de7 | 12997 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12998 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 12999 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 13000 | |
2d112de7 | 13001 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 13002 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 13003 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 13004 | |
d328c9d7 DV |
13005 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
13006 | pipe_config); | |
13007 | if (base_bpp < 0) | |
4e53c2e0 DV |
13008 | goto fail; |
13009 | ||
e41a56be VS |
13010 | /* |
13011 | * Determine the real pipe dimensions. Note that stereo modes can | |
13012 | * increase the actual pipe size due to the frame doubling and | |
13013 | * insertion of additional space for blanks between the frame. This | |
13014 | * is stored in the crtc timings. We use the requested mode to do this | |
13015 | * computation to clearly distinguish it from the adjusted mode, which | |
13016 | * can be changed by the connectors in the below retry loop. | |
13017 | */ | |
2d112de7 | 13018 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
13019 | &pipe_config->pipe_src_w, |
13020 | &pipe_config->pipe_src_h); | |
e41a56be | 13021 | |
253c84c8 VS |
13022 | for_each_connector_in_state(state, connector, connector_state, i) { |
13023 | if (connector_state->crtc != crtc) | |
13024 | continue; | |
13025 | ||
13026 | encoder = to_intel_encoder(connector_state->best_encoder); | |
13027 | ||
e25148d0 VS |
13028 | if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) { |
13029 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
13030 | goto fail; | |
13031 | } | |
13032 | ||
253c84c8 VS |
13033 | /* |
13034 | * Determine output_types before calling the .compute_config() | |
13035 | * hooks so that the hooks can use this information safely. | |
13036 | */ | |
13037 | pipe_config->output_types |= 1 << encoder->type; | |
13038 | } | |
13039 | ||
e29c22c0 | 13040 | encoder_retry: |
ef1b460d | 13041 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 13042 | pipe_config->port_clock = 0; |
ef1b460d | 13043 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 13044 | |
135c81b8 | 13045 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
13046 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
13047 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 13048 | |
7758a113 DV |
13049 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
13050 | * adjust it according to limitations or connector properties, and also | |
13051 | * a chance to reject the mode entirely. | |
47f1c6c9 | 13052 | */ |
da3ced29 | 13053 | for_each_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 13054 | if (connector_state->crtc != crtc) |
7758a113 | 13055 | continue; |
7ae89233 | 13056 | |
0b901879 ACO |
13057 | encoder = to_intel_encoder(connector_state->best_encoder); |
13058 | ||
0a478c27 | 13059 | if (!(encoder->compute_config(encoder, pipe_config, connector_state))) { |
efea6e8e | 13060 | DRM_DEBUG_KMS("Encoder config failure\n"); |
7758a113 DV |
13061 | goto fail; |
13062 | } | |
ee7b9f93 | 13063 | } |
47f1c6c9 | 13064 | |
ff9a6750 DV |
13065 | /* Set default port clock if not overwritten by the encoder. Needs to be |
13066 | * done afterwards in case the encoder adjusts the mode. */ | |
13067 | if (!pipe_config->port_clock) | |
2d112de7 | 13068 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 13069 | * pipe_config->pixel_multiplier; |
ff9a6750 | 13070 | |
a43f6e0f | 13071 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 13072 | if (ret < 0) { |
7758a113 DV |
13073 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
13074 | goto fail; | |
ee7b9f93 | 13075 | } |
e29c22c0 DV |
13076 | |
13077 | if (ret == RETRY) { | |
13078 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
13079 | ret = -EINVAL; | |
13080 | goto fail; | |
13081 | } | |
13082 | ||
13083 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
13084 | retry = false; | |
13085 | goto encoder_retry; | |
13086 | } | |
13087 | ||
e8fa4270 DV |
13088 | /* Dithering seems to not pass-through bits correctly when it should, so |
13089 | * only enable it on 6bpc panels. */ | |
13090 | pipe_config->dither = pipe_config->pipe_bpp == 6*3; | |
62f0ace5 | 13091 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 13092 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 13093 | |
7758a113 | 13094 | fail: |
548ee15b | 13095 | return ret; |
ee7b9f93 | 13096 | } |
47f1c6c9 | 13097 | |
ea9d758d | 13098 | static void |
4740b0f2 | 13099 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 13100 | { |
0a9ab303 ACO |
13101 | struct drm_crtc *crtc; |
13102 | struct drm_crtc_state *crtc_state; | |
8a75d157 | 13103 | int i; |
ea9d758d | 13104 | |
7668851f | 13105 | /* Double check state. */ |
8a75d157 | 13106 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
3cb480bc | 13107 | to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); |
fc467a22 ML |
13108 | |
13109 | /* Update hwmode for vblank functions */ | |
13110 | if (crtc->state->active) | |
13111 | crtc->hwmode = crtc->state->adjusted_mode; | |
13112 | else | |
13113 | crtc->hwmode.crtc_clock = 0; | |
61067a5e ML |
13114 | |
13115 | /* | |
13116 | * Update legacy state to satisfy fbc code. This can | |
13117 | * be removed when fbc uses the atomic state. | |
13118 | */ | |
13119 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
13120 | struct drm_plane_state *plane_state = crtc->primary->state; | |
13121 | ||
13122 | crtc->primary->fb = plane_state->fb; | |
13123 | crtc->x = plane_state->src_x >> 16; | |
13124 | crtc->y = plane_state->src_y >> 16; | |
13125 | } | |
ea9d758d | 13126 | } |
ea9d758d DV |
13127 | } |
13128 | ||
3bd26263 | 13129 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 13130 | { |
3bd26263 | 13131 | int diff; |
f1f644dc JB |
13132 | |
13133 | if (clock1 == clock2) | |
13134 | return true; | |
13135 | ||
13136 | if (!clock1 || !clock2) | |
13137 | return false; | |
13138 | ||
13139 | diff = abs(clock1 - clock2); | |
13140 | ||
13141 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
13142 | return true; | |
13143 | ||
13144 | return false; | |
13145 | } | |
13146 | ||
cfb23ed6 ML |
13147 | static bool |
13148 | intel_compare_m_n(unsigned int m, unsigned int n, | |
13149 | unsigned int m2, unsigned int n2, | |
13150 | bool exact) | |
13151 | { | |
13152 | if (m == m2 && n == n2) | |
13153 | return true; | |
13154 | ||
13155 | if (exact || !m || !n || !m2 || !n2) | |
13156 | return false; | |
13157 | ||
13158 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
13159 | ||
31d10b57 ML |
13160 | if (n > n2) { |
13161 | while (n > n2) { | |
cfb23ed6 ML |
13162 | m2 <<= 1; |
13163 | n2 <<= 1; | |
13164 | } | |
31d10b57 ML |
13165 | } else if (n < n2) { |
13166 | while (n < n2) { | |
cfb23ed6 ML |
13167 | m <<= 1; |
13168 | n <<= 1; | |
13169 | } | |
13170 | } | |
13171 | ||
31d10b57 ML |
13172 | if (n != n2) |
13173 | return false; | |
13174 | ||
13175 | return intel_fuzzy_clock_check(m, m2); | |
cfb23ed6 ML |
13176 | } |
13177 | ||
13178 | static bool | |
13179 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
13180 | struct intel_link_m_n *m2_n2, | |
13181 | bool adjust) | |
13182 | { | |
13183 | if (m_n->tu == m2_n2->tu && | |
13184 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
13185 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
13186 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
13187 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
13188 | if (adjust) | |
13189 | *m2_n2 = *m_n; | |
13190 | ||
13191 | return true; | |
13192 | } | |
13193 | ||
13194 | return false; | |
13195 | } | |
13196 | ||
0e8ffe1b | 13197 | static bool |
2fa2fe9a | 13198 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b | 13199 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
13200 | struct intel_crtc_state *pipe_config, |
13201 | bool adjust) | |
0e8ffe1b | 13202 | { |
772c2a51 | 13203 | struct drm_i915_private *dev_priv = to_i915(dev); |
cfb23ed6 ML |
13204 | bool ret = true; |
13205 | ||
13206 | #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \ | |
13207 | do { \ | |
13208 | if (!adjust) \ | |
13209 | DRM_ERROR(fmt, ##__VA_ARGS__); \ | |
13210 | else \ | |
13211 | DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \ | |
13212 | } while (0) | |
13213 | ||
66e985c0 DV |
13214 | #define PIPE_CONF_CHECK_X(name) \ |
13215 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 13216 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
66e985c0 DV |
13217 | "(expected 0x%08x, found 0x%08x)\n", \ |
13218 | current_config->name, \ | |
13219 | pipe_config->name); \ | |
cfb23ed6 | 13220 | ret = false; \ |
66e985c0 DV |
13221 | } |
13222 | ||
08a24034 DV |
13223 | #define PIPE_CONF_CHECK_I(name) \ |
13224 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 13225 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
08a24034 DV |
13226 | "(expected %i, found %i)\n", \ |
13227 | current_config->name, \ | |
13228 | pipe_config->name); \ | |
cfb23ed6 ML |
13229 | ret = false; \ |
13230 | } | |
13231 | ||
8106ddbd ACO |
13232 | #define PIPE_CONF_CHECK_P(name) \ |
13233 | if (current_config->name != pipe_config->name) { \ | |
13234 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
13235 | "(expected %p, found %p)\n", \ | |
13236 | current_config->name, \ | |
13237 | pipe_config->name); \ | |
13238 | ret = false; \ | |
13239 | } | |
13240 | ||
cfb23ed6 ML |
13241 | #define PIPE_CONF_CHECK_M_N(name) \ |
13242 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
13243 | &pipe_config->name,\ | |
13244 | adjust)) { \ | |
13245 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
13246 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
13247 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
13248 | current_config->name.tu, \ | |
13249 | current_config->name.gmch_m, \ | |
13250 | current_config->name.gmch_n, \ | |
13251 | current_config->name.link_m, \ | |
13252 | current_config->name.link_n, \ | |
13253 | pipe_config->name.tu, \ | |
13254 | pipe_config->name.gmch_m, \ | |
13255 | pipe_config->name.gmch_n, \ | |
13256 | pipe_config->name.link_m, \ | |
13257 | pipe_config->name.link_n); \ | |
13258 | ret = false; \ | |
13259 | } | |
13260 | ||
55c561a7 DV |
13261 | /* This is required for BDW+ where there is only one set of registers for |
13262 | * switching between high and low RR. | |
13263 | * This macro can be used whenever a comparison has to be made between one | |
13264 | * hw state and multiple sw state variables. | |
13265 | */ | |
cfb23ed6 ML |
13266 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ |
13267 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
13268 | &pipe_config->name, adjust) && \ | |
13269 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
13270 | &pipe_config->name, adjust)) { \ | |
13271 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
13272 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
13273 | "or tu %i gmch %i/%i link %i/%i, " \ | |
13274 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
13275 | current_config->name.tu, \ | |
13276 | current_config->name.gmch_m, \ | |
13277 | current_config->name.gmch_n, \ | |
13278 | current_config->name.link_m, \ | |
13279 | current_config->name.link_n, \ | |
13280 | current_config->alt_name.tu, \ | |
13281 | current_config->alt_name.gmch_m, \ | |
13282 | current_config->alt_name.gmch_n, \ | |
13283 | current_config->alt_name.link_m, \ | |
13284 | current_config->alt_name.link_n, \ | |
13285 | pipe_config->name.tu, \ | |
13286 | pipe_config->name.gmch_m, \ | |
13287 | pipe_config->name.gmch_n, \ | |
13288 | pipe_config->name.link_m, \ | |
13289 | pipe_config->name.link_n); \ | |
13290 | ret = false; \ | |
88adfff1 DV |
13291 | } |
13292 | ||
1bd1bd80 DV |
13293 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
13294 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
cfb23ed6 | 13295 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
13296 | "(expected %i, found %i)\n", \ |
13297 | current_config->name & (mask), \ | |
13298 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 13299 | ret = false; \ |
1bd1bd80 DV |
13300 | } |
13301 | ||
5e550656 VS |
13302 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
13303 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
cfb23ed6 | 13304 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
5e550656 VS |
13305 | "(expected %i, found %i)\n", \ |
13306 | current_config->name, \ | |
13307 | pipe_config->name); \ | |
cfb23ed6 | 13308 | ret = false; \ |
5e550656 VS |
13309 | } |
13310 | ||
bb760063 DV |
13311 | #define PIPE_CONF_QUIRK(quirk) \ |
13312 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
13313 | ||
eccb140b DV |
13314 | PIPE_CONF_CHECK_I(cpu_transcoder); |
13315 | ||
08a24034 DV |
13316 | PIPE_CONF_CHECK_I(has_pch_encoder); |
13317 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 13318 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 13319 | |
90a6b7b0 | 13320 | PIPE_CONF_CHECK_I(lane_count); |
95a7a2ae | 13321 | PIPE_CONF_CHECK_X(lane_lat_optim_mask); |
b95af8be VK |
13322 | |
13323 | if (INTEL_INFO(dev)->gen < 8) { | |
cfb23ed6 ML |
13324 | PIPE_CONF_CHECK_M_N(dp_m_n); |
13325 | ||
cfb23ed6 ML |
13326 | if (current_config->has_drrs) |
13327 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
13328 | } else | |
13329 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 13330 | |
253c84c8 | 13331 | PIPE_CONF_CHECK_X(output_types); |
a65347ba | 13332 | |
2d112de7 ACO |
13333 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
13334 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
13335 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
13336 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
13337 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
13338 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 13339 | |
2d112de7 ACO |
13340 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
13341 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
13342 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
13343 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
13344 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
13345 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 13346 | |
c93f54cf | 13347 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 13348 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
772c2a51 | 13349 | if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || |
920a14b2 | 13350 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
b5a9fa09 | 13351 | PIPE_CONF_CHECK_I(limited_color_range); |
e43823ec | 13352 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 13353 | |
9ed109a7 DV |
13354 | PIPE_CONF_CHECK_I(has_audio); |
13355 | ||
2d112de7 | 13356 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
13357 | DRM_MODE_FLAG_INTERLACE); |
13358 | ||
bb760063 | 13359 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 13360 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 13361 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 13362 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 13363 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 13364 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 13365 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 13366 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
13367 | DRM_MODE_FLAG_NVSYNC); |
13368 | } | |
045ac3b5 | 13369 | |
333b8ca8 | 13370 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a DV |
13371 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
13372 | if (INTEL_INFO(dev)->gen < 4) | |
7f7d8dd6 | 13373 | PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); |
333b8ca8 | 13374 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 13375 | |
bfd16b2a ML |
13376 | if (!adjust) { |
13377 | PIPE_CONF_CHECK_I(pipe_src_w); | |
13378 | PIPE_CONF_CHECK_I(pipe_src_h); | |
13379 | ||
13380 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
13381 | if (current_config->pch_pfit.enabled) { | |
13382 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
13383 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
13384 | } | |
2fa2fe9a | 13385 | |
7aefe2b5 ML |
13386 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
13387 | } | |
a1b2278e | 13388 | |
e59150dc | 13389 | /* BDW+ don't expose a synchronous way to read the state */ |
772c2a51 | 13390 | if (IS_HASWELL(dev_priv)) |
e59150dc | 13391 | PIPE_CONF_CHECK_I(ips_enabled); |
42db64ef | 13392 | |
282740f7 VS |
13393 | PIPE_CONF_CHECK_I(double_wide); |
13394 | ||
8106ddbd | 13395 | PIPE_CONF_CHECK_P(shared_dpll); |
66e985c0 | 13396 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 13397 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
13398 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
13399 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 13400 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
00490c22 | 13401 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
3f4cd19f DL |
13402 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
13403 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
13404 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 13405 | |
47eacbab VS |
13406 | PIPE_CONF_CHECK_X(dsi_pll.ctrl); |
13407 | PIPE_CONF_CHECK_X(dsi_pll.div); | |
13408 | ||
9beb5fea | 13409 | if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) |
42571aef VS |
13410 | PIPE_CONF_CHECK_I(pipe_bpp); |
13411 | ||
2d112de7 | 13412 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 13413 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 13414 | |
66e985c0 | 13415 | #undef PIPE_CONF_CHECK_X |
08a24034 | 13416 | #undef PIPE_CONF_CHECK_I |
8106ddbd | 13417 | #undef PIPE_CONF_CHECK_P |
1bd1bd80 | 13418 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 13419 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 13420 | #undef PIPE_CONF_QUIRK |
cfb23ed6 | 13421 | #undef INTEL_ERR_OR_DBG_KMS |
88adfff1 | 13422 | |
cfb23ed6 | 13423 | return ret; |
0e8ffe1b DV |
13424 | } |
13425 | ||
e3b247da VS |
13426 | static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, |
13427 | const struct intel_crtc_state *pipe_config) | |
13428 | { | |
13429 | if (pipe_config->has_pch_encoder) { | |
21a727b3 | 13430 | int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
e3b247da VS |
13431 | &pipe_config->fdi_m_n); |
13432 | int dotclock = pipe_config->base.adjusted_mode.crtc_clock; | |
13433 | ||
13434 | /* | |
13435 | * FDI already provided one idea for the dotclock. | |
13436 | * Yell if the encoder disagrees. | |
13437 | */ | |
13438 | WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock), | |
13439 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", | |
13440 | fdi_dotclock, dotclock); | |
13441 | } | |
13442 | } | |
13443 | ||
c0ead703 ML |
13444 | static void verify_wm_state(struct drm_crtc *crtc, |
13445 | struct drm_crtc_state *new_state) | |
08db6652 | 13446 | { |
e7c84544 | 13447 | struct drm_device *dev = crtc->dev; |
fac5e23e | 13448 | struct drm_i915_private *dev_priv = to_i915(dev); |
08db6652 | 13449 | struct skl_ddb_allocation hw_ddb, *sw_ddb; |
3de8a14c | 13450 | struct skl_pipe_wm hw_wm, *sw_wm; |
13451 | struct skl_plane_wm *hw_plane_wm, *sw_plane_wm; | |
13452 | struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry; | |
e7c84544 ML |
13453 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13454 | const enum pipe pipe = intel_crtc->pipe; | |
3de8a14c | 13455 | int plane, level, max_level = ilk_wm_max_level(dev_priv); |
08db6652 | 13456 | |
e7c84544 | 13457 | if (INTEL_INFO(dev)->gen < 9 || !new_state->active) |
08db6652 DL |
13458 | return; |
13459 | ||
3de8a14c | 13460 | skl_pipe_wm_get_hw_state(crtc, &hw_wm); |
03af79e0 | 13461 | sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal; |
3de8a14c | 13462 | |
08db6652 DL |
13463 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); |
13464 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
13465 | ||
e7c84544 | 13466 | /* planes */ |
8b364b41 | 13467 | for_each_universal_plane(dev_priv, pipe, plane) { |
3de8a14c | 13468 | hw_plane_wm = &hw_wm.planes[plane]; |
13469 | sw_plane_wm = &sw_wm->planes[plane]; | |
08db6652 | 13470 | |
3de8a14c | 13471 | /* Watermarks */ |
13472 | for (level = 0; level <= max_level; level++) { | |
13473 | if (skl_wm_level_equals(&hw_plane_wm->wm[level], | |
13474 | &sw_plane_wm->wm[level])) | |
13475 | continue; | |
13476 | ||
13477 | DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
13478 | pipe_name(pipe), plane + 1, level, | |
13479 | sw_plane_wm->wm[level].plane_en, | |
13480 | sw_plane_wm->wm[level].plane_res_b, | |
13481 | sw_plane_wm->wm[level].plane_res_l, | |
13482 | hw_plane_wm->wm[level].plane_en, | |
13483 | hw_plane_wm->wm[level].plane_res_b, | |
13484 | hw_plane_wm->wm[level].plane_res_l); | |
13485 | } | |
08db6652 | 13486 | |
3de8a14c | 13487 | if (!skl_wm_level_equals(&hw_plane_wm->trans_wm, |
13488 | &sw_plane_wm->trans_wm)) { | |
13489 | DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
13490 | pipe_name(pipe), plane + 1, | |
13491 | sw_plane_wm->trans_wm.plane_en, | |
13492 | sw_plane_wm->trans_wm.plane_res_b, | |
13493 | sw_plane_wm->trans_wm.plane_res_l, | |
13494 | hw_plane_wm->trans_wm.plane_en, | |
13495 | hw_plane_wm->trans_wm.plane_res_b, | |
13496 | hw_plane_wm->trans_wm.plane_res_l); | |
13497 | } | |
13498 | ||
13499 | /* DDB */ | |
13500 | hw_ddb_entry = &hw_ddb.plane[pipe][plane]; | |
13501 | sw_ddb_entry = &sw_ddb->plane[pipe][plane]; | |
13502 | ||
13503 | if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { | |
faccd994 | 13504 | DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n", |
3de8a14c | 13505 | pipe_name(pipe), plane + 1, |
13506 | sw_ddb_entry->start, sw_ddb_entry->end, | |
13507 | hw_ddb_entry->start, hw_ddb_entry->end); | |
13508 | } | |
e7c84544 | 13509 | } |
08db6652 | 13510 | |
27082493 L |
13511 | /* |
13512 | * cursor | |
13513 | * If the cursor plane isn't active, we may not have updated it's ddb | |
13514 | * allocation. In that case since the ddb allocation will be updated | |
13515 | * once the plane becomes visible, we can skip this check | |
13516 | */ | |
13517 | if (intel_crtc->cursor_addr) { | |
3de8a14c | 13518 | hw_plane_wm = &hw_wm.planes[PLANE_CURSOR]; |
13519 | sw_plane_wm = &sw_wm->planes[PLANE_CURSOR]; | |
13520 | ||
13521 | /* Watermarks */ | |
13522 | for (level = 0; level <= max_level; level++) { | |
13523 | if (skl_wm_level_equals(&hw_plane_wm->wm[level], | |
13524 | &sw_plane_wm->wm[level])) | |
13525 | continue; | |
13526 | ||
13527 | DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
13528 | pipe_name(pipe), level, | |
13529 | sw_plane_wm->wm[level].plane_en, | |
13530 | sw_plane_wm->wm[level].plane_res_b, | |
13531 | sw_plane_wm->wm[level].plane_res_l, | |
13532 | hw_plane_wm->wm[level].plane_en, | |
13533 | hw_plane_wm->wm[level].plane_res_b, | |
13534 | hw_plane_wm->wm[level].plane_res_l); | |
13535 | } | |
13536 | ||
13537 | if (!skl_wm_level_equals(&hw_plane_wm->trans_wm, | |
13538 | &sw_plane_wm->trans_wm)) { | |
13539 | DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
13540 | pipe_name(pipe), | |
13541 | sw_plane_wm->trans_wm.plane_en, | |
13542 | sw_plane_wm->trans_wm.plane_res_b, | |
13543 | sw_plane_wm->trans_wm.plane_res_l, | |
13544 | hw_plane_wm->trans_wm.plane_en, | |
13545 | hw_plane_wm->trans_wm.plane_res_b, | |
13546 | hw_plane_wm->trans_wm.plane_res_l); | |
13547 | } | |
13548 | ||
13549 | /* DDB */ | |
13550 | hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; | |
13551 | sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; | |
27082493 | 13552 | |
3de8a14c | 13553 | if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { |
faccd994 | 13554 | DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n", |
27082493 | 13555 | pipe_name(pipe), |
3de8a14c | 13556 | sw_ddb_entry->start, sw_ddb_entry->end, |
13557 | hw_ddb_entry->start, hw_ddb_entry->end); | |
27082493 | 13558 | } |
08db6652 DL |
13559 | } |
13560 | } | |
13561 | ||
91d1b4bd | 13562 | static void |
c0ead703 | 13563 | verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc) |
8af6cf88 | 13564 | { |
35dd3c64 | 13565 | struct drm_connector *connector; |
8af6cf88 | 13566 | |
e7c84544 | 13567 | drm_for_each_connector(connector, dev) { |
35dd3c64 ML |
13568 | struct drm_encoder *encoder = connector->encoder; |
13569 | struct drm_connector_state *state = connector->state; | |
ad3c558f | 13570 | |
e7c84544 ML |
13571 | if (state->crtc != crtc) |
13572 | continue; | |
13573 | ||
5a21b665 | 13574 | intel_connector_verify_state(to_intel_connector(connector)); |
8af6cf88 | 13575 | |
ad3c558f | 13576 | I915_STATE_WARN(state->best_encoder != encoder, |
35dd3c64 | 13577 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 13578 | } |
91d1b4bd DV |
13579 | } |
13580 | ||
13581 | static void | |
c0ead703 | 13582 | verify_encoder_state(struct drm_device *dev) |
91d1b4bd DV |
13583 | { |
13584 | struct intel_encoder *encoder; | |
13585 | struct intel_connector *connector; | |
8af6cf88 | 13586 | |
b2784e15 | 13587 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 | 13588 | bool enabled = false; |
4d20cd86 | 13589 | enum pipe pipe; |
8af6cf88 DV |
13590 | |
13591 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
13592 | encoder->base.base.id, | |
8e329a03 | 13593 | encoder->base.name); |
8af6cf88 | 13594 | |
3a3371ff | 13595 | for_each_intel_connector(dev, connector) { |
4d20cd86 | 13596 | if (connector->base.state->best_encoder != &encoder->base) |
8af6cf88 DV |
13597 | continue; |
13598 | enabled = true; | |
ad3c558f ML |
13599 | |
13600 | I915_STATE_WARN(connector->base.state->crtc != | |
13601 | encoder->base.crtc, | |
13602 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 13603 | } |
0e32b39c | 13604 | |
e2c719b7 | 13605 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
13606 | "encoder's enabled state mismatch " |
13607 | "(expected %i, found %i)\n", | |
13608 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
13609 | |
13610 | if (!encoder->base.crtc) { | |
4d20cd86 | 13611 | bool active; |
7c60d198 | 13612 | |
4d20cd86 ML |
13613 | active = encoder->get_hw_state(encoder, &pipe); |
13614 | I915_STATE_WARN(active, | |
13615 | "encoder detached but still enabled on pipe %c.\n", | |
13616 | pipe_name(pipe)); | |
7c60d198 | 13617 | } |
8af6cf88 | 13618 | } |
91d1b4bd DV |
13619 | } |
13620 | ||
13621 | static void | |
c0ead703 ML |
13622 | verify_crtc_state(struct drm_crtc *crtc, |
13623 | struct drm_crtc_state *old_crtc_state, | |
13624 | struct drm_crtc_state *new_crtc_state) | |
91d1b4bd | 13625 | { |
e7c84544 | 13626 | struct drm_device *dev = crtc->dev; |
fac5e23e | 13627 | struct drm_i915_private *dev_priv = to_i915(dev); |
91d1b4bd | 13628 | struct intel_encoder *encoder; |
e7c84544 ML |
13629 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13630 | struct intel_crtc_state *pipe_config, *sw_config; | |
13631 | struct drm_atomic_state *old_state; | |
13632 | bool active; | |
045ac3b5 | 13633 | |
e7c84544 | 13634 | old_state = old_crtc_state->state; |
ec2dc6a0 | 13635 | __drm_atomic_helper_crtc_destroy_state(old_crtc_state); |
e7c84544 ML |
13636 | pipe_config = to_intel_crtc_state(old_crtc_state); |
13637 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
13638 | pipe_config->base.crtc = crtc; | |
13639 | pipe_config->base.state = old_state; | |
8af6cf88 | 13640 | |
78108b7c | 13641 | DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name); |
8af6cf88 | 13642 | |
e7c84544 | 13643 | active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config); |
d62cf62a | 13644 | |
e7c84544 ML |
13645 | /* hw state is inconsistent with the pipe quirk */ |
13646 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
13647 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
13648 | active = new_crtc_state->active; | |
6c49f241 | 13649 | |
e7c84544 ML |
13650 | I915_STATE_WARN(new_crtc_state->active != active, |
13651 | "crtc active state doesn't match with hw state " | |
13652 | "(expected %i, found %i)\n", new_crtc_state->active, active); | |
0e8ffe1b | 13653 | |
e7c84544 ML |
13654 | I915_STATE_WARN(intel_crtc->active != new_crtc_state->active, |
13655 | "transitional active state does not match atomic hw state " | |
13656 | "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active); | |
4d20cd86 | 13657 | |
e7c84544 ML |
13658 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
13659 | enum pipe pipe; | |
4d20cd86 | 13660 | |
e7c84544 ML |
13661 | active = encoder->get_hw_state(encoder, &pipe); |
13662 | I915_STATE_WARN(active != new_crtc_state->active, | |
13663 | "[ENCODER:%i] active %i with crtc active %i\n", | |
13664 | encoder->base.base.id, active, new_crtc_state->active); | |
4d20cd86 | 13665 | |
e7c84544 ML |
13666 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, |
13667 | "Encoder connected to wrong pipe %c\n", | |
13668 | pipe_name(pipe)); | |
4d20cd86 | 13669 | |
253c84c8 VS |
13670 | if (active) { |
13671 | pipe_config->output_types |= 1 << encoder->type; | |
e7c84544 | 13672 | encoder->get_config(encoder, pipe_config); |
253c84c8 | 13673 | } |
e7c84544 | 13674 | } |
53d9f4e9 | 13675 | |
e7c84544 ML |
13676 | if (!new_crtc_state->active) |
13677 | return; | |
cfb23ed6 | 13678 | |
e7c84544 | 13679 | intel_pipe_config_sanity_check(dev_priv, pipe_config); |
e3b247da | 13680 | |
e7c84544 ML |
13681 | sw_config = to_intel_crtc_state(crtc->state); |
13682 | if (!intel_pipe_config_compare(dev, sw_config, | |
13683 | pipe_config, false)) { | |
13684 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); | |
13685 | intel_dump_pipe_config(intel_crtc, pipe_config, | |
13686 | "[hw state]"); | |
13687 | intel_dump_pipe_config(intel_crtc, sw_config, | |
13688 | "[sw state]"); | |
8af6cf88 DV |
13689 | } |
13690 | } | |
13691 | ||
91d1b4bd | 13692 | static void |
c0ead703 ML |
13693 | verify_single_dpll_state(struct drm_i915_private *dev_priv, |
13694 | struct intel_shared_dpll *pll, | |
13695 | struct drm_crtc *crtc, | |
13696 | struct drm_crtc_state *new_state) | |
91d1b4bd | 13697 | { |
91d1b4bd | 13698 | struct intel_dpll_hw_state dpll_hw_state; |
e7c84544 ML |
13699 | unsigned crtc_mask; |
13700 | bool active; | |
5358901f | 13701 | |
e7c84544 | 13702 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); |
5358901f | 13703 | |
e7c84544 | 13704 | DRM_DEBUG_KMS("%s\n", pll->name); |
5358901f | 13705 | |
e7c84544 | 13706 | active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state); |
5358901f | 13707 | |
e7c84544 ML |
13708 | if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) { |
13709 | I915_STATE_WARN(!pll->on && pll->active_mask, | |
13710 | "pll in active use but not on in sw tracking\n"); | |
13711 | I915_STATE_WARN(pll->on && !pll->active_mask, | |
13712 | "pll is on but not used by any active crtc\n"); | |
13713 | I915_STATE_WARN(pll->on != active, | |
13714 | "pll on state mismatch (expected %i, found %i)\n", | |
13715 | pll->on, active); | |
13716 | } | |
5358901f | 13717 | |
e7c84544 | 13718 | if (!crtc) { |
2dd66ebd | 13719 | I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask, |
e7c84544 ML |
13720 | "more active pll users than references: %x vs %x\n", |
13721 | pll->active_mask, pll->config.crtc_mask); | |
5358901f | 13722 | |
e7c84544 ML |
13723 | return; |
13724 | } | |
13725 | ||
13726 | crtc_mask = 1 << drm_crtc_index(crtc); | |
13727 | ||
13728 | if (new_state->active) | |
13729 | I915_STATE_WARN(!(pll->active_mask & crtc_mask), | |
13730 | "pll active mismatch (expected pipe %c in active mask 0x%02x)\n", | |
13731 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
13732 | else | |
13733 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
13734 | "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n", | |
13735 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
2dd66ebd | 13736 | |
e7c84544 ML |
13737 | I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask), |
13738 | "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n", | |
13739 | crtc_mask, pll->config.crtc_mask); | |
66e985c0 | 13740 | |
e7c84544 ML |
13741 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, |
13742 | &dpll_hw_state, | |
13743 | sizeof(dpll_hw_state)), | |
13744 | "pll hw state mismatch\n"); | |
13745 | } | |
13746 | ||
13747 | static void | |
c0ead703 ML |
13748 | verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc, |
13749 | struct drm_crtc_state *old_crtc_state, | |
13750 | struct drm_crtc_state *new_crtc_state) | |
e7c84544 | 13751 | { |
fac5e23e | 13752 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7c84544 ML |
13753 | struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state); |
13754 | struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state); | |
13755 | ||
13756 | if (new_state->shared_dpll) | |
c0ead703 | 13757 | verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state); |
e7c84544 ML |
13758 | |
13759 | if (old_state->shared_dpll && | |
13760 | old_state->shared_dpll != new_state->shared_dpll) { | |
13761 | unsigned crtc_mask = 1 << drm_crtc_index(crtc); | |
13762 | struct intel_shared_dpll *pll = old_state->shared_dpll; | |
13763 | ||
13764 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
13765 | "pll active mismatch (didn't expect pipe %c in active mask)\n", | |
13766 | pipe_name(drm_crtc_index(crtc))); | |
13767 | I915_STATE_WARN(pll->config.crtc_mask & crtc_mask, | |
13768 | "pll enabled crtcs mismatch (found %x in enabled mask)\n", | |
13769 | pipe_name(drm_crtc_index(crtc))); | |
5358901f | 13770 | } |
8af6cf88 DV |
13771 | } |
13772 | ||
e7c84544 | 13773 | static void |
c0ead703 | 13774 | intel_modeset_verify_crtc(struct drm_crtc *crtc, |
e7c84544 ML |
13775 | struct drm_crtc_state *old_state, |
13776 | struct drm_crtc_state *new_state) | |
13777 | { | |
5a21b665 DV |
13778 | if (!needs_modeset(new_state) && |
13779 | !to_intel_crtc_state(new_state)->update_pipe) | |
13780 | return; | |
13781 | ||
c0ead703 | 13782 | verify_wm_state(crtc, new_state); |
5a21b665 | 13783 | verify_connector_state(crtc->dev, crtc); |
c0ead703 ML |
13784 | verify_crtc_state(crtc, old_state, new_state); |
13785 | verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state); | |
e7c84544 ML |
13786 | } |
13787 | ||
13788 | static void | |
c0ead703 | 13789 | verify_disabled_dpll_state(struct drm_device *dev) |
e7c84544 | 13790 | { |
fac5e23e | 13791 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7c84544 ML |
13792 | int i; |
13793 | ||
13794 | for (i = 0; i < dev_priv->num_shared_dpll; i++) | |
c0ead703 | 13795 | verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL); |
e7c84544 ML |
13796 | } |
13797 | ||
13798 | static void | |
c0ead703 | 13799 | intel_modeset_verify_disabled(struct drm_device *dev) |
e7c84544 | 13800 | { |
c0ead703 ML |
13801 | verify_encoder_state(dev); |
13802 | verify_connector_state(dev, NULL); | |
13803 | verify_disabled_dpll_state(dev); | |
e7c84544 ML |
13804 | } |
13805 | ||
80715b2f VS |
13806 | static void update_scanline_offset(struct intel_crtc *crtc) |
13807 | { | |
4f8036a2 | 13808 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
80715b2f VS |
13809 | |
13810 | /* | |
13811 | * The scanline counter increments at the leading edge of hsync. | |
13812 | * | |
13813 | * On most platforms it starts counting from vtotal-1 on the | |
13814 | * first active line. That means the scanline counter value is | |
13815 | * always one less than what we would expect. Ie. just after | |
13816 | * start of vblank, which also occurs at start of hsync (on the | |
13817 | * last active line), the scanline counter will read vblank_start-1. | |
13818 | * | |
13819 | * On gen2 the scanline counter starts counting from 1 instead | |
13820 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
13821 | * to keep the value positive), instead of adding one. | |
13822 | * | |
13823 | * On HSW+ the behaviour of the scanline counter depends on the output | |
13824 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
13825 | * there's an extra 1 line difference. So we need to add two instead of | |
13826 | * one to the value. | |
13827 | */ | |
4f8036a2 | 13828 | if (IS_GEN2(dev_priv)) { |
124abe07 | 13829 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
13830 | int vtotal; |
13831 | ||
124abe07 VS |
13832 | vtotal = adjusted_mode->crtc_vtotal; |
13833 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
13834 | vtotal /= 2; |
13835 | ||
13836 | crtc->scanline_offset = vtotal - 1; | |
4f8036a2 | 13837 | } else if (HAS_DDI(dev_priv) && |
2d84d2b3 | 13838 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
13839 | crtc->scanline_offset = 2; |
13840 | } else | |
13841 | crtc->scanline_offset = 1; | |
13842 | } | |
13843 | ||
ad421372 | 13844 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 13845 | { |
225da59b | 13846 | struct drm_device *dev = state->dev; |
ed6739ef | 13847 | struct drm_i915_private *dev_priv = to_i915(dev); |
ad421372 | 13848 | struct intel_shared_dpll_config *shared_dpll = NULL; |
0a9ab303 ACO |
13849 | struct drm_crtc *crtc; |
13850 | struct drm_crtc_state *crtc_state; | |
0a9ab303 | 13851 | int i; |
ed6739ef ACO |
13852 | |
13853 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 13854 | return; |
ed6739ef | 13855 | |
0a9ab303 | 13856 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
fb1a38a9 | 13857 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8106ddbd ACO |
13858 | struct intel_shared_dpll *old_dpll = |
13859 | to_intel_crtc_state(crtc->state)->shared_dpll; | |
0a9ab303 | 13860 | |
fb1a38a9 | 13861 | if (!needs_modeset(crtc_state)) |
225da59b ACO |
13862 | continue; |
13863 | ||
8106ddbd | 13864 | to_intel_crtc_state(crtc_state)->shared_dpll = NULL; |
fb1a38a9 | 13865 | |
8106ddbd | 13866 | if (!old_dpll) |
fb1a38a9 | 13867 | continue; |
0a9ab303 | 13868 | |
ad421372 ML |
13869 | if (!shared_dpll) |
13870 | shared_dpll = intel_atomic_get_shared_dpll_state(state); | |
ed6739ef | 13871 | |
8106ddbd | 13872 | intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc); |
ad421372 | 13873 | } |
ed6739ef ACO |
13874 | } |
13875 | ||
99d736a2 ML |
13876 | /* |
13877 | * This implements the workaround described in the "notes" section of the mode | |
13878 | * set sequence documentation. When going from no pipes or single pipe to | |
13879 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
13880 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
13881 | */ | |
13882 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
13883 | { | |
13884 | struct drm_crtc_state *crtc_state; | |
13885 | struct intel_crtc *intel_crtc; | |
13886 | struct drm_crtc *crtc; | |
13887 | struct intel_crtc_state *first_crtc_state = NULL; | |
13888 | struct intel_crtc_state *other_crtc_state = NULL; | |
13889 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
13890 | int i; | |
13891 | ||
13892 | /* look at all crtc's that are going to be enabled in during modeset */ | |
13893 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13894 | intel_crtc = to_intel_crtc(crtc); | |
13895 | ||
13896 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
13897 | continue; | |
13898 | ||
13899 | if (first_crtc_state) { | |
13900 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
13901 | break; | |
13902 | } else { | |
13903 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
13904 | first_pipe = intel_crtc->pipe; | |
13905 | } | |
13906 | } | |
13907 | ||
13908 | /* No workaround needed? */ | |
13909 | if (!first_crtc_state) | |
13910 | return 0; | |
13911 | ||
13912 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
13913 | for_each_intel_crtc(state->dev, intel_crtc) { | |
13914 | struct intel_crtc_state *pipe_config; | |
13915 | ||
13916 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
13917 | if (IS_ERR(pipe_config)) | |
13918 | return PTR_ERR(pipe_config); | |
13919 | ||
13920 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
13921 | ||
13922 | if (!pipe_config->base.active || | |
13923 | needs_modeset(&pipe_config->base)) | |
13924 | continue; | |
13925 | ||
13926 | /* 2 or more enabled crtcs means no need for w/a */ | |
13927 | if (enabled_pipe != INVALID_PIPE) | |
13928 | return 0; | |
13929 | ||
13930 | enabled_pipe = intel_crtc->pipe; | |
13931 | } | |
13932 | ||
13933 | if (enabled_pipe != INVALID_PIPE) | |
13934 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
13935 | else if (other_crtc_state) | |
13936 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
13937 | ||
13938 | return 0; | |
13939 | } | |
13940 | ||
27c329ed ML |
13941 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
13942 | { | |
13943 | struct drm_crtc *crtc; | |
13944 | struct drm_crtc_state *crtc_state; | |
13945 | int ret = 0; | |
13946 | ||
13947 | /* add all active pipes to the state */ | |
13948 | for_each_crtc(state->dev, crtc) { | |
13949 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13950 | if (IS_ERR(crtc_state)) | |
13951 | return PTR_ERR(crtc_state); | |
13952 | ||
13953 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
13954 | continue; | |
13955 | ||
13956 | crtc_state->mode_changed = true; | |
13957 | ||
13958 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
13959 | if (ret) | |
13960 | break; | |
13961 | ||
13962 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13963 | if (ret) | |
13964 | break; | |
13965 | } | |
13966 | ||
13967 | return ret; | |
13968 | } | |
13969 | ||
c347a676 | 13970 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd | 13971 | { |
565602d7 | 13972 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 13973 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
565602d7 ML |
13974 | struct drm_crtc *crtc; |
13975 | struct drm_crtc_state *crtc_state; | |
13976 | int ret = 0, i; | |
054518dd | 13977 | |
b359283a ML |
13978 | if (!check_digital_port_conflicts(state)) { |
13979 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
13980 | return -EINVAL; | |
13981 | } | |
13982 | ||
565602d7 ML |
13983 | intel_state->modeset = true; |
13984 | intel_state->active_crtcs = dev_priv->active_crtcs; | |
13985 | ||
13986 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13987 | if (crtc_state->active) | |
13988 | intel_state->active_crtcs |= 1 << i; | |
13989 | else | |
13990 | intel_state->active_crtcs &= ~(1 << i); | |
8b4a7d05 MR |
13991 | |
13992 | if (crtc_state->active != crtc->state->active) | |
13993 | intel_state->active_pipe_changes |= drm_crtc_mask(crtc); | |
565602d7 ML |
13994 | } |
13995 | ||
054518dd ACO |
13996 | /* |
13997 | * See if the config requires any additional preparation, e.g. | |
13998 | * to adjust global state with pipes off. We need to do this | |
13999 | * here so we can get the modeset_pipe updated config for the new | |
14000 | * mode set on this crtc. For other crtcs we need to use the | |
14001 | * adjusted_mode bits in the crtc directly. | |
14002 | */ | |
27c329ed | 14003 | if (dev_priv->display.modeset_calc_cdclk) { |
c89e39f3 | 14004 | if (!intel_state->cdclk_pll_vco) |
63911d72 | 14005 | intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco; |
b2045352 VS |
14006 | if (!intel_state->cdclk_pll_vco) |
14007 | intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq; | |
c89e39f3 | 14008 | |
27c329ed | 14009 | ret = dev_priv->display.modeset_calc_cdclk(state); |
c89e39f3 CT |
14010 | if (ret < 0) |
14011 | return ret; | |
27c329ed | 14012 | |
c89e39f3 | 14013 | if (intel_state->dev_cdclk != dev_priv->cdclk_freq || |
63911d72 | 14014 | intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco) |
27c329ed ML |
14015 | ret = intel_modeset_all_pipes(state); |
14016 | ||
14017 | if (ret < 0) | |
054518dd | 14018 | return ret; |
e8788cbc ML |
14019 | |
14020 | DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n", | |
14021 | intel_state->cdclk, intel_state->dev_cdclk); | |
27c329ed | 14022 | } else |
1a617b77 | 14023 | to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq; |
054518dd | 14024 | |
ad421372 | 14025 | intel_modeset_clear_plls(state); |
054518dd | 14026 | |
565602d7 | 14027 | if (IS_HASWELL(dev_priv)) |
ad421372 | 14028 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 14029 | |
ad421372 | 14030 | return 0; |
c347a676 ACO |
14031 | } |
14032 | ||
aa363136 MR |
14033 | /* |
14034 | * Handle calculation of various watermark data at the end of the atomic check | |
14035 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
14036 | * handlers to ensure that all derived state has been updated. | |
14037 | */ | |
55994c2c | 14038 | static int calc_watermark_data(struct drm_atomic_state *state) |
aa363136 MR |
14039 | { |
14040 | struct drm_device *dev = state->dev; | |
98d39494 | 14041 | struct drm_i915_private *dev_priv = to_i915(dev); |
98d39494 MR |
14042 | |
14043 | /* Is there platform-specific watermark information to calculate? */ | |
14044 | if (dev_priv->display.compute_global_watermarks) | |
55994c2c MR |
14045 | return dev_priv->display.compute_global_watermarks(state); |
14046 | ||
14047 | return 0; | |
aa363136 MR |
14048 | } |
14049 | ||
74c090b1 ML |
14050 | /** |
14051 | * intel_atomic_check - validate state object | |
14052 | * @dev: drm device | |
14053 | * @state: state to validate | |
14054 | */ | |
14055 | static int intel_atomic_check(struct drm_device *dev, | |
14056 | struct drm_atomic_state *state) | |
c347a676 | 14057 | { |
dd8b3bdb | 14058 | struct drm_i915_private *dev_priv = to_i915(dev); |
aa363136 | 14059 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
c347a676 ACO |
14060 | struct drm_crtc *crtc; |
14061 | struct drm_crtc_state *crtc_state; | |
14062 | int ret, i; | |
61333b60 | 14063 | bool any_ms = false; |
c347a676 | 14064 | |
74c090b1 | 14065 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
14066 | if (ret) |
14067 | return ret; | |
14068 | ||
c347a676 | 14069 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
cfb23ed6 ML |
14070 | struct intel_crtc_state *pipe_config = |
14071 | to_intel_crtc_state(crtc_state); | |
1ed51de9 DV |
14072 | |
14073 | /* Catch I915_MODE_FLAG_INHERITED */ | |
14074 | if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) | |
14075 | crtc_state->mode_changed = true; | |
cfb23ed6 | 14076 | |
af4a879e | 14077 | if (!needs_modeset(crtc_state)) |
c347a676 ACO |
14078 | continue; |
14079 | ||
af4a879e DV |
14080 | if (!crtc_state->enable) { |
14081 | any_ms = true; | |
cfb23ed6 | 14082 | continue; |
af4a879e | 14083 | } |
cfb23ed6 | 14084 | |
26495481 DV |
14085 | /* FIXME: For only active_changed we shouldn't need to do any |
14086 | * state recomputation at all. */ | |
14087 | ||
1ed51de9 DV |
14088 | ret = drm_atomic_add_affected_connectors(state, crtc); |
14089 | if (ret) | |
14090 | return ret; | |
b359283a | 14091 | |
cfb23ed6 | 14092 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
25aa1c39 ML |
14093 | if (ret) { |
14094 | intel_dump_pipe_config(to_intel_crtc(crtc), | |
14095 | pipe_config, "[failed]"); | |
c347a676 | 14096 | return ret; |
25aa1c39 | 14097 | } |
c347a676 | 14098 | |
73831236 | 14099 | if (i915.fastboot && |
dd8b3bdb | 14100 | intel_pipe_config_compare(dev, |
cfb23ed6 | 14101 | to_intel_crtc_state(crtc->state), |
1ed51de9 | 14102 | pipe_config, true)) { |
26495481 | 14103 | crtc_state->mode_changed = false; |
bfd16b2a | 14104 | to_intel_crtc_state(crtc_state)->update_pipe = true; |
26495481 DV |
14105 | } |
14106 | ||
af4a879e | 14107 | if (needs_modeset(crtc_state)) |
26495481 | 14108 | any_ms = true; |
cfb23ed6 | 14109 | |
af4a879e DV |
14110 | ret = drm_atomic_add_affected_planes(state, crtc); |
14111 | if (ret) | |
14112 | return ret; | |
61333b60 | 14113 | |
26495481 DV |
14114 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
14115 | needs_modeset(crtc_state) ? | |
14116 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
14117 | } |
14118 | ||
61333b60 ML |
14119 | if (any_ms) { |
14120 | ret = intel_modeset_checks(state); | |
14121 | ||
14122 | if (ret) | |
14123 | return ret; | |
27c329ed | 14124 | } else |
dd8b3bdb | 14125 | intel_state->cdclk = dev_priv->cdclk_freq; |
76305b1a | 14126 | |
dd8b3bdb | 14127 | ret = drm_atomic_helper_check_planes(dev, state); |
aa363136 MR |
14128 | if (ret) |
14129 | return ret; | |
14130 | ||
f51be2e0 | 14131 | intel_fbc_choose_crtc(dev_priv, state); |
55994c2c | 14132 | return calc_watermark_data(state); |
054518dd ACO |
14133 | } |
14134 | ||
5008e874 | 14135 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
d07f0e59 | 14136 | struct drm_atomic_state *state) |
5008e874 | 14137 | { |
fac5e23e | 14138 | struct drm_i915_private *dev_priv = to_i915(dev); |
5008e874 ML |
14139 | struct drm_crtc_state *crtc_state; |
14140 | struct drm_crtc *crtc; | |
14141 | int i, ret; | |
14142 | ||
5a21b665 DV |
14143 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
14144 | if (state->legacy_cursor_update) | |
a6747b73 ML |
14145 | continue; |
14146 | ||
5a21b665 DV |
14147 | ret = intel_crtc_wait_for_pending_flips(crtc); |
14148 | if (ret) | |
14149 | return ret; | |
5008e874 | 14150 | |
5a21b665 DV |
14151 | if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) |
14152 | flush_workqueue(dev_priv->wq); | |
d55dbd06 ML |
14153 | } |
14154 | ||
f935675f ML |
14155 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
14156 | if (ret) | |
14157 | return ret; | |
14158 | ||
5008e874 | 14159 | ret = drm_atomic_helper_prepare_planes(dev, state); |
f7e5838b | 14160 | mutex_unlock(&dev->struct_mutex); |
7580d774 | 14161 | |
5008e874 ML |
14162 | return ret; |
14163 | } | |
14164 | ||
a2991414 ML |
14165 | u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc) |
14166 | { | |
14167 | struct drm_device *dev = crtc->base.dev; | |
14168 | ||
14169 | if (!dev->max_vblank_count) | |
14170 | return drm_accurate_vblank_count(&crtc->base); | |
14171 | ||
14172 | return dev->driver->get_vblank_counter(dev, crtc->pipe); | |
14173 | } | |
14174 | ||
5a21b665 DV |
14175 | static void intel_atomic_wait_for_vblanks(struct drm_device *dev, |
14176 | struct drm_i915_private *dev_priv, | |
14177 | unsigned crtc_mask) | |
e8861675 | 14178 | { |
5a21b665 DV |
14179 | unsigned last_vblank_count[I915_MAX_PIPES]; |
14180 | enum pipe pipe; | |
14181 | int ret; | |
e8861675 | 14182 | |
5a21b665 DV |
14183 | if (!crtc_mask) |
14184 | return; | |
e8861675 | 14185 | |
5a21b665 DV |
14186 | for_each_pipe(dev_priv, pipe) { |
14187 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
e8861675 | 14188 | |
5a21b665 | 14189 | if (!((1 << pipe) & crtc_mask)) |
e8861675 ML |
14190 | continue; |
14191 | ||
5a21b665 DV |
14192 | ret = drm_crtc_vblank_get(crtc); |
14193 | if (WARN_ON(ret != 0)) { | |
14194 | crtc_mask &= ~(1 << pipe); | |
14195 | continue; | |
e8861675 ML |
14196 | } |
14197 | ||
5a21b665 | 14198 | last_vblank_count[pipe] = drm_crtc_vblank_count(crtc); |
e8861675 ML |
14199 | } |
14200 | ||
5a21b665 DV |
14201 | for_each_pipe(dev_priv, pipe) { |
14202 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
14203 | long lret; | |
e8861675 | 14204 | |
5a21b665 DV |
14205 | if (!((1 << pipe) & crtc_mask)) |
14206 | continue; | |
d55dbd06 | 14207 | |
5a21b665 DV |
14208 | lret = wait_event_timeout(dev->vblank[pipe].queue, |
14209 | last_vblank_count[pipe] != | |
14210 | drm_crtc_vblank_count(crtc), | |
14211 | msecs_to_jiffies(50)); | |
d55dbd06 | 14212 | |
5a21b665 | 14213 | WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe)); |
d55dbd06 | 14214 | |
5a21b665 | 14215 | drm_crtc_vblank_put(crtc); |
d55dbd06 ML |
14216 | } |
14217 | } | |
14218 | ||
5a21b665 | 14219 | static bool needs_vblank_wait(struct intel_crtc_state *crtc_state) |
a6747b73 | 14220 | { |
5a21b665 DV |
14221 | /* fb updated, need to unpin old fb */ |
14222 | if (crtc_state->fb_changed) | |
14223 | return true; | |
a6747b73 | 14224 | |
5a21b665 DV |
14225 | /* wm changes, need vblank before final wm's */ |
14226 | if (crtc_state->update_wm_post) | |
14227 | return true; | |
a6747b73 | 14228 | |
5a21b665 DV |
14229 | /* |
14230 | * cxsr is re-enabled after vblank. | |
14231 | * This is already handled by crtc_state->update_wm_post, | |
14232 | * but added for clarity. | |
14233 | */ | |
14234 | if (crtc_state->disable_cxsr) | |
14235 | return true; | |
a6747b73 | 14236 | |
5a21b665 | 14237 | return false; |
e8861675 ML |
14238 | } |
14239 | ||
896e5bb0 L |
14240 | static void intel_update_crtc(struct drm_crtc *crtc, |
14241 | struct drm_atomic_state *state, | |
14242 | struct drm_crtc_state *old_crtc_state, | |
14243 | unsigned int *crtc_vblank_mask) | |
14244 | { | |
14245 | struct drm_device *dev = crtc->dev; | |
14246 | struct drm_i915_private *dev_priv = to_i915(dev); | |
14247 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
14248 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc->state); | |
14249 | bool modeset = needs_modeset(crtc->state); | |
14250 | ||
14251 | if (modeset) { | |
14252 | update_scanline_offset(intel_crtc); | |
14253 | dev_priv->display.crtc_enable(pipe_config, state); | |
14254 | } else { | |
14255 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); | |
14256 | } | |
14257 | ||
14258 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
14259 | intel_fbc_enable( | |
14260 | intel_crtc, pipe_config, | |
14261 | to_intel_plane_state(crtc->primary->state)); | |
14262 | } | |
14263 | ||
14264 | drm_atomic_helper_commit_planes_on_crtc(old_crtc_state); | |
14265 | ||
14266 | if (needs_vblank_wait(pipe_config)) | |
14267 | *crtc_vblank_mask |= drm_crtc_mask(crtc); | |
14268 | } | |
14269 | ||
14270 | static void intel_update_crtcs(struct drm_atomic_state *state, | |
14271 | unsigned int *crtc_vblank_mask) | |
14272 | { | |
14273 | struct drm_crtc *crtc; | |
14274 | struct drm_crtc_state *old_crtc_state; | |
14275 | int i; | |
14276 | ||
14277 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
14278 | if (!crtc->state->active) | |
14279 | continue; | |
14280 | ||
14281 | intel_update_crtc(crtc, state, old_crtc_state, | |
14282 | crtc_vblank_mask); | |
14283 | } | |
14284 | } | |
14285 | ||
27082493 L |
14286 | static void skl_update_crtcs(struct drm_atomic_state *state, |
14287 | unsigned int *crtc_vblank_mask) | |
14288 | { | |
14289 | struct drm_device *dev = state->dev; | |
27082493 L |
14290 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
14291 | struct drm_crtc *crtc; | |
ce0ba283 | 14292 | struct intel_crtc *intel_crtc; |
27082493 | 14293 | struct drm_crtc_state *old_crtc_state; |
ce0ba283 | 14294 | struct intel_crtc_state *cstate; |
27082493 L |
14295 | unsigned int updated = 0; |
14296 | bool progress; | |
14297 | enum pipe pipe; | |
14298 | ||
14299 | /* | |
14300 | * Whenever the number of active pipes changes, we need to make sure we | |
14301 | * update the pipes in the right order so that their ddb allocations | |
14302 | * never overlap with eachother inbetween CRTC updates. Otherwise we'll | |
14303 | * cause pipe underruns and other bad stuff. | |
14304 | */ | |
14305 | do { | |
14306 | int i; | |
14307 | progress = false; | |
14308 | ||
14309 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
14310 | bool vbl_wait = false; | |
14311 | unsigned int cmask = drm_crtc_mask(crtc); | |
ce0ba283 L |
14312 | |
14313 | intel_crtc = to_intel_crtc(crtc); | |
14314 | cstate = to_intel_crtc_state(crtc->state); | |
14315 | pipe = intel_crtc->pipe; | |
27082493 L |
14316 | |
14317 | if (updated & cmask || !crtc->state->active) | |
14318 | continue; | |
ce0ba283 | 14319 | if (skl_ddb_allocation_overlaps(state, intel_crtc)) |
27082493 L |
14320 | continue; |
14321 | ||
14322 | updated |= cmask; | |
14323 | ||
14324 | /* | |
14325 | * If this is an already active pipe, it's DDB changed, | |
14326 | * and this isn't the last pipe that needs updating | |
14327 | * then we need to wait for a vblank to pass for the | |
14328 | * new ddb allocation to take effect. | |
14329 | */ | |
ce0ba283 L |
14330 | if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb, |
14331 | &intel_crtc->hw_ddb) && | |
27082493 L |
14332 | !crtc->state->active_changed && |
14333 | intel_state->wm_results.dirty_pipes != updated) | |
14334 | vbl_wait = true; | |
14335 | ||
14336 | intel_update_crtc(crtc, state, old_crtc_state, | |
14337 | crtc_vblank_mask); | |
14338 | ||
14339 | if (vbl_wait) | |
14340 | intel_wait_for_vblank(dev, pipe); | |
14341 | ||
14342 | progress = true; | |
14343 | } | |
14344 | } while (progress); | |
14345 | } | |
14346 | ||
94f05024 | 14347 | static void intel_atomic_commit_tail(struct drm_atomic_state *state) |
a6778b3c | 14348 | { |
94f05024 | 14349 | struct drm_device *dev = state->dev; |
565602d7 | 14350 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 14351 | struct drm_i915_private *dev_priv = to_i915(dev); |
29ceb0e6 | 14352 | struct drm_crtc_state *old_crtc_state; |
7580d774 | 14353 | struct drm_crtc *crtc; |
5a21b665 | 14354 | struct intel_crtc_state *intel_cstate; |
5a21b665 DV |
14355 | bool hw_check = intel_state->modeset; |
14356 | unsigned long put_domains[I915_MAX_PIPES] = {}; | |
14357 | unsigned crtc_vblank_mask = 0; | |
e95433c7 | 14358 | int i; |
a6778b3c | 14359 | |
ea0000f0 DV |
14360 | drm_atomic_helper_wait_for_dependencies(state); |
14361 | ||
565602d7 ML |
14362 | if (intel_state->modeset) { |
14363 | memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, | |
14364 | sizeof(intel_state->min_pixclk)); | |
14365 | dev_priv->active_crtcs = intel_state->active_crtcs; | |
1a617b77 | 14366 | dev_priv->atomic_cdclk_freq = intel_state->cdclk; |
5a21b665 DV |
14367 | |
14368 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); | |
565602d7 ML |
14369 | } |
14370 | ||
29ceb0e6 | 14371 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
a539205a ML |
14372 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
14373 | ||
5a21b665 DV |
14374 | if (needs_modeset(crtc->state) || |
14375 | to_intel_crtc_state(crtc->state)->update_pipe) { | |
14376 | hw_check = true; | |
14377 | ||
14378 | put_domains[to_intel_crtc(crtc)->pipe] = | |
14379 | modeset_get_crtc_power_domains(crtc, | |
14380 | to_intel_crtc_state(crtc->state)); | |
14381 | } | |
14382 | ||
61333b60 ML |
14383 | if (!needs_modeset(crtc->state)) |
14384 | continue; | |
14385 | ||
29ceb0e6 | 14386 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); |
460da916 | 14387 | |
29ceb0e6 VS |
14388 | if (old_crtc_state->active) { |
14389 | intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask); | |
4a806558 | 14390 | dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state); |
eddfcbcd | 14391 | intel_crtc->active = false; |
58f9c0bc | 14392 | intel_fbc_disable(intel_crtc); |
eddfcbcd | 14393 | intel_disable_shared_dpll(intel_crtc); |
9bbc8258 VS |
14394 | |
14395 | /* | |
14396 | * Underruns don't always raise | |
14397 | * interrupts, so check manually. | |
14398 | */ | |
14399 | intel_check_cpu_fifo_underruns(dev_priv); | |
14400 | intel_check_pch_fifo_underruns(dev_priv); | |
b9001114 ML |
14401 | |
14402 | if (!crtc->state->active) | |
14403 | intel_update_watermarks(crtc); | |
a539205a | 14404 | } |
b8cecdf5 | 14405 | } |
7758a113 | 14406 | |
ea9d758d DV |
14407 | /* Only after disabling all output pipelines that will be changed can we |
14408 | * update the the output configuration. */ | |
4740b0f2 | 14409 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 14410 | |
565602d7 | 14411 | if (intel_state->modeset) { |
4740b0f2 | 14412 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); |
33c8df89 ML |
14413 | |
14414 | if (dev_priv->display.modeset_commit_cdclk && | |
c89e39f3 | 14415 | (intel_state->dev_cdclk != dev_priv->cdclk_freq || |
63911d72 | 14416 | intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)) |
33c8df89 | 14417 | dev_priv->display.modeset_commit_cdclk(state); |
f6d1973d | 14418 | |
656d1b89 L |
14419 | /* |
14420 | * SKL workaround: bspec recommends we disable the SAGV when we | |
14421 | * have more then one pipe enabled | |
14422 | */ | |
56feca91 | 14423 | if (!intel_can_enable_sagv(state)) |
16dcdc4e | 14424 | intel_disable_sagv(dev_priv); |
656d1b89 | 14425 | |
c0ead703 | 14426 | intel_modeset_verify_disabled(dev); |
4740b0f2 | 14427 | } |
47fab737 | 14428 | |
896e5bb0 | 14429 | /* Complete the events for pipes that have now been disabled */ |
29ceb0e6 | 14430 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
f6ac4b2a | 14431 | bool modeset = needs_modeset(crtc->state); |
80715b2f | 14432 | |
1f7528c4 DV |
14433 | /* Complete events for now disable pipes here. */ |
14434 | if (modeset && !crtc->state->active && crtc->state->event) { | |
14435 | spin_lock_irq(&dev->event_lock); | |
14436 | drm_crtc_send_vblank_event(crtc, crtc->state->event); | |
14437 | spin_unlock_irq(&dev->event_lock); | |
14438 | ||
14439 | crtc->state->event = NULL; | |
14440 | } | |
177246a8 MR |
14441 | } |
14442 | ||
896e5bb0 L |
14443 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
14444 | dev_priv->display.update_crtcs(state, &crtc_vblank_mask); | |
14445 | ||
94f05024 DV |
14446 | /* FIXME: We should call drm_atomic_helper_commit_hw_done() here |
14447 | * already, but still need the state for the delayed optimization. To | |
14448 | * fix this: | |
14449 | * - wrap the optimization/post_plane_update stuff into a per-crtc work. | |
14450 | * - schedule that vblank worker _before_ calling hw_done | |
14451 | * - at the start of commit_tail, cancel it _synchrously | |
14452 | * - switch over to the vblank wait helper in the core after that since | |
14453 | * we don't need out special handling any more. | |
14454 | */ | |
5a21b665 DV |
14455 | if (!state->legacy_cursor_update) |
14456 | intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask); | |
14457 | ||
14458 | /* | |
14459 | * Now that the vblank has passed, we can go ahead and program the | |
14460 | * optimal watermarks on platforms that need two-step watermark | |
14461 | * programming. | |
14462 | * | |
14463 | * TODO: Move this (and other cleanup) to an async worker eventually. | |
14464 | */ | |
14465 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
14466 | intel_cstate = to_intel_crtc_state(crtc->state); | |
14467 | ||
14468 | if (dev_priv->display.optimize_watermarks) | |
14469 | dev_priv->display.optimize_watermarks(intel_cstate); | |
14470 | } | |
14471 | ||
14472 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
14473 | intel_post_plane_update(to_intel_crtc_state(old_crtc_state)); | |
14474 | ||
14475 | if (put_domains[i]) | |
14476 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
14477 | ||
14478 | intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state); | |
14479 | } | |
14480 | ||
56feca91 | 14481 | if (intel_state->modeset && intel_can_enable_sagv(state)) |
16dcdc4e | 14482 | intel_enable_sagv(dev_priv); |
656d1b89 | 14483 | |
94f05024 DV |
14484 | drm_atomic_helper_commit_hw_done(state); |
14485 | ||
5a21b665 DV |
14486 | if (intel_state->modeset) |
14487 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); | |
14488 | ||
14489 | mutex_lock(&dev->struct_mutex); | |
14490 | drm_atomic_helper_cleanup_planes(dev, state); | |
14491 | mutex_unlock(&dev->struct_mutex); | |
14492 | ||
ea0000f0 DV |
14493 | drm_atomic_helper_commit_cleanup_done(state); |
14494 | ||
0853695c | 14495 | drm_atomic_state_put(state); |
f30da187 | 14496 | |
75714940 MK |
14497 | /* As one of the primary mmio accessors, KMS has a high likelihood |
14498 | * of triggering bugs in unclaimed access. After we finish | |
14499 | * modesetting, see if an error has been flagged, and if so | |
14500 | * enable debugging for the next modeset - and hope we catch | |
14501 | * the culprit. | |
14502 | * | |
14503 | * XXX note that we assume display power is on at this point. | |
14504 | * This might hold true now but we need to add pm helper to check | |
14505 | * unclaimed only when the hardware is on, as atomic commits | |
14506 | * can happen also when the device is completely off. | |
14507 | */ | |
14508 | intel_uncore_arm_unclaimed_mmio_detection(dev_priv); | |
94f05024 DV |
14509 | } |
14510 | ||
14511 | static void intel_atomic_commit_work(struct work_struct *work) | |
14512 | { | |
c004a90b CW |
14513 | struct drm_atomic_state *state = |
14514 | container_of(work, struct drm_atomic_state, commit_work); | |
14515 | ||
94f05024 DV |
14516 | intel_atomic_commit_tail(state); |
14517 | } | |
14518 | ||
c004a90b CW |
14519 | static int __i915_sw_fence_call |
14520 | intel_atomic_commit_ready(struct i915_sw_fence *fence, | |
14521 | enum i915_sw_fence_notify notify) | |
14522 | { | |
14523 | struct intel_atomic_state *state = | |
14524 | container_of(fence, struct intel_atomic_state, commit_ready); | |
14525 | ||
14526 | switch (notify) { | |
14527 | case FENCE_COMPLETE: | |
14528 | if (state->base.commit_work.func) | |
14529 | queue_work(system_unbound_wq, &state->base.commit_work); | |
14530 | break; | |
14531 | ||
14532 | case FENCE_FREE: | |
14533 | drm_atomic_state_put(&state->base); | |
14534 | break; | |
14535 | } | |
14536 | ||
14537 | return NOTIFY_DONE; | |
14538 | } | |
14539 | ||
6c9c1b38 DV |
14540 | static void intel_atomic_track_fbs(struct drm_atomic_state *state) |
14541 | { | |
14542 | struct drm_plane_state *old_plane_state; | |
14543 | struct drm_plane *plane; | |
6c9c1b38 DV |
14544 | int i; |
14545 | ||
faf5bf0a CW |
14546 | for_each_plane_in_state(state, plane, old_plane_state, i) |
14547 | i915_gem_track_fb(intel_fb_obj(old_plane_state->fb), | |
14548 | intel_fb_obj(plane->state->fb), | |
14549 | to_intel_plane(plane)->frontbuffer_bit); | |
6c9c1b38 DV |
14550 | } |
14551 | ||
94f05024 DV |
14552 | /** |
14553 | * intel_atomic_commit - commit validated state object | |
14554 | * @dev: DRM device | |
14555 | * @state: the top-level driver state object | |
14556 | * @nonblock: nonblocking commit | |
14557 | * | |
14558 | * This function commits a top-level state object that has been validated | |
14559 | * with drm_atomic_helper_check(). | |
14560 | * | |
14561 | * FIXME: Atomic modeset support for i915 is not yet complete. At the moment | |
14562 | * nonblocking commits are only safe for pure plane updates. Everything else | |
14563 | * should work though. | |
14564 | * | |
14565 | * RETURNS | |
14566 | * Zero for success or -errno. | |
14567 | */ | |
14568 | static int intel_atomic_commit(struct drm_device *dev, | |
14569 | struct drm_atomic_state *state, | |
14570 | bool nonblock) | |
14571 | { | |
14572 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
fac5e23e | 14573 | struct drm_i915_private *dev_priv = to_i915(dev); |
94f05024 DV |
14574 | int ret = 0; |
14575 | ||
14576 | if (intel_state->modeset && nonblock) { | |
14577 | DRM_DEBUG_KMS("nonblocking commit for modeset not yet implemented.\n"); | |
14578 | return -EINVAL; | |
14579 | } | |
14580 | ||
14581 | ret = drm_atomic_helper_setup_commit(state, nonblock); | |
14582 | if (ret) | |
14583 | return ret; | |
14584 | ||
c004a90b CW |
14585 | drm_atomic_state_get(state); |
14586 | i915_sw_fence_init(&intel_state->commit_ready, | |
14587 | intel_atomic_commit_ready); | |
94f05024 | 14588 | |
d07f0e59 | 14589 | ret = intel_atomic_prepare_commit(dev, state); |
94f05024 DV |
14590 | if (ret) { |
14591 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); | |
c004a90b | 14592 | i915_sw_fence_commit(&intel_state->commit_ready); |
94f05024 DV |
14593 | return ret; |
14594 | } | |
14595 | ||
14596 | drm_atomic_helper_swap_state(state, true); | |
14597 | dev_priv->wm.distrust_bios_wm = false; | |
14598 | dev_priv->wm.skl_results = intel_state->wm_results; | |
14599 | intel_shared_dpll_commit(state); | |
6c9c1b38 | 14600 | intel_atomic_track_fbs(state); |
94f05024 | 14601 | |
0853695c | 14602 | drm_atomic_state_get(state); |
c004a90b CW |
14603 | INIT_WORK(&state->commit_work, |
14604 | nonblock ? intel_atomic_commit_work : NULL); | |
14605 | ||
14606 | i915_sw_fence_commit(&intel_state->commit_ready); | |
14607 | if (!nonblock) { | |
14608 | i915_sw_fence_wait(&intel_state->commit_ready); | |
94f05024 | 14609 | intel_atomic_commit_tail(state); |
c004a90b | 14610 | } |
75714940 | 14611 | |
74c090b1 | 14612 | return 0; |
7f27126e JB |
14613 | } |
14614 | ||
c0c36b94 CW |
14615 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
14616 | { | |
83a57153 ACO |
14617 | struct drm_device *dev = crtc->dev; |
14618 | struct drm_atomic_state *state; | |
e694eb02 | 14619 | struct drm_crtc_state *crtc_state; |
2bfb4627 | 14620 | int ret; |
83a57153 ACO |
14621 | |
14622 | state = drm_atomic_state_alloc(dev); | |
14623 | if (!state) { | |
78108b7c VS |
14624 | DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory", |
14625 | crtc->base.id, crtc->name); | |
83a57153 ACO |
14626 | return; |
14627 | } | |
14628 | ||
e694eb02 | 14629 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
83a57153 | 14630 | |
e694eb02 ML |
14631 | retry: |
14632 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
14633 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
14634 | if (!ret) { | |
14635 | if (!crtc_state->active) | |
14636 | goto out; | |
83a57153 | 14637 | |
e694eb02 | 14638 | crtc_state->mode_changed = true; |
74c090b1 | 14639 | ret = drm_atomic_commit(state); |
83a57153 ACO |
14640 | } |
14641 | ||
e694eb02 ML |
14642 | if (ret == -EDEADLK) { |
14643 | drm_atomic_state_clear(state); | |
14644 | drm_modeset_backoff(state->acquire_ctx); | |
14645 | goto retry; | |
4ed9fb37 | 14646 | } |
4be07317 | 14647 | |
e694eb02 | 14648 | out: |
0853695c | 14649 | drm_atomic_state_put(state); |
c0c36b94 CW |
14650 | } |
14651 | ||
a8784875 BP |
14652 | /* |
14653 | * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling | |
14654 | * drm_atomic_helper_legacy_gamma_set() directly. | |
14655 | */ | |
14656 | static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc, | |
14657 | u16 *red, u16 *green, u16 *blue, | |
14658 | uint32_t size) | |
14659 | { | |
14660 | struct drm_device *dev = crtc->dev; | |
14661 | struct drm_mode_config *config = &dev->mode_config; | |
14662 | struct drm_crtc_state *state; | |
14663 | int ret; | |
14664 | ||
14665 | ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size); | |
14666 | if (ret) | |
14667 | return ret; | |
14668 | ||
14669 | /* | |
14670 | * Make sure we update the legacy properties so this works when | |
14671 | * atomic is not enabled. | |
14672 | */ | |
14673 | ||
14674 | state = crtc->state; | |
14675 | ||
14676 | drm_object_property_set_value(&crtc->base, | |
14677 | config->degamma_lut_property, | |
14678 | (state->degamma_lut) ? | |
14679 | state->degamma_lut->base.id : 0); | |
14680 | ||
14681 | drm_object_property_set_value(&crtc->base, | |
14682 | config->ctm_property, | |
14683 | (state->ctm) ? | |
14684 | state->ctm->base.id : 0); | |
14685 | ||
14686 | drm_object_property_set_value(&crtc->base, | |
14687 | config->gamma_lut_property, | |
14688 | (state->gamma_lut) ? | |
14689 | state->gamma_lut->base.id : 0); | |
14690 | ||
14691 | return 0; | |
14692 | } | |
14693 | ||
f6e5b160 | 14694 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
a8784875 | 14695 | .gamma_set = intel_atomic_legacy_gamma_set, |
74c090b1 | 14696 | .set_config = drm_atomic_helper_set_config, |
82cf435b | 14697 | .set_property = drm_atomic_helper_crtc_set_property, |
f6e5b160 | 14698 | .destroy = intel_crtc_destroy, |
527b6abe | 14699 | .page_flip = intel_crtc_page_flip, |
1356837e MR |
14700 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
14701 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
14702 | }; |
14703 | ||
6beb8c23 MR |
14704 | /** |
14705 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
14706 | * @plane: drm plane to prepare for | |
14707 | * @fb: framebuffer to prepare for presentation | |
14708 | * | |
14709 | * Prepares a framebuffer for usage on a display plane. Generally this | |
14710 | * involves pinning the underlying object and updating the frontbuffer tracking | |
14711 | * bits. Some older platforms need special physical address handling for | |
14712 | * cursor planes. | |
14713 | * | |
f935675f ML |
14714 | * Must be called with struct_mutex held. |
14715 | * | |
6beb8c23 MR |
14716 | * Returns 0 on success, negative error code on failure. |
14717 | */ | |
14718 | int | |
14719 | intel_prepare_plane_fb(struct drm_plane *plane, | |
1832040d | 14720 | struct drm_plane_state *new_state) |
465c120c | 14721 | { |
c004a90b CW |
14722 | struct intel_atomic_state *intel_state = |
14723 | to_intel_atomic_state(new_state->state); | |
465c120c | 14724 | struct drm_device *dev = plane->dev; |
50a0bc90 | 14725 | struct drm_i915_private *dev_priv = to_i915(dev); |
844f9111 | 14726 | struct drm_framebuffer *fb = new_state->fb; |
6beb8c23 | 14727 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1ee49399 | 14728 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
c004a90b | 14729 | int ret; |
465c120c | 14730 | |
1ee49399 | 14731 | if (!obj && !old_obj) |
465c120c MR |
14732 | return 0; |
14733 | ||
5008e874 ML |
14734 | if (old_obj) { |
14735 | struct drm_crtc_state *crtc_state = | |
c004a90b CW |
14736 | drm_atomic_get_existing_crtc_state(new_state->state, |
14737 | plane->state->crtc); | |
5008e874 ML |
14738 | |
14739 | /* Big Hammer, we also need to ensure that any pending | |
14740 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
14741 | * current scanout is retired before unpinning the old | |
14742 | * framebuffer. Note that we rely on userspace rendering | |
14743 | * into the buffer attached to the pipe they are waiting | |
14744 | * on. If not, userspace generates a GPU hang with IPEHR | |
14745 | * point to the MI_WAIT_FOR_EVENT. | |
14746 | * | |
14747 | * This should only fail upon a hung GPU, in which case we | |
14748 | * can safely continue. | |
14749 | */ | |
c004a90b CW |
14750 | if (needs_modeset(crtc_state)) { |
14751 | ret = i915_sw_fence_await_reservation(&intel_state->commit_ready, | |
14752 | old_obj->resv, NULL, | |
14753 | false, 0, | |
14754 | GFP_KERNEL); | |
14755 | if (ret < 0) | |
14756 | return ret; | |
f4457ae7 | 14757 | } |
5008e874 ML |
14758 | } |
14759 | ||
c004a90b CW |
14760 | if (new_state->fence) { /* explicit fencing */ |
14761 | ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready, | |
14762 | new_state->fence, | |
14763 | I915_FENCE_TIMEOUT, | |
14764 | GFP_KERNEL); | |
14765 | if (ret < 0) | |
14766 | return ret; | |
14767 | } | |
14768 | ||
c37efb99 CW |
14769 | if (!obj) |
14770 | return 0; | |
14771 | ||
c004a90b CW |
14772 | if (!new_state->fence) { /* implicit fencing */ |
14773 | ret = i915_sw_fence_await_reservation(&intel_state->commit_ready, | |
14774 | obj->resv, NULL, | |
14775 | false, I915_FENCE_TIMEOUT, | |
14776 | GFP_KERNEL); | |
14777 | if (ret < 0) | |
14778 | return ret; | |
14779 | } | |
5a21b665 | 14780 | |
c37efb99 | 14781 | if (plane->type == DRM_PLANE_TYPE_CURSOR && |
6beb8c23 | 14782 | INTEL_INFO(dev)->cursor_needs_physical) { |
50a0bc90 | 14783 | int align = IS_I830(dev_priv) ? 16 * 1024 : 256; |
6beb8c23 | 14784 | ret = i915_gem_object_attach_phys(obj, align); |
d07f0e59 | 14785 | if (ret) { |
6beb8c23 | 14786 | DRM_DEBUG_KMS("failed to attach phys object\n"); |
d07f0e59 CW |
14787 | return ret; |
14788 | } | |
6beb8c23 | 14789 | } else { |
058d88c4 CW |
14790 | struct i915_vma *vma; |
14791 | ||
14792 | vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation); | |
d07f0e59 CW |
14793 | if (IS_ERR(vma)) { |
14794 | DRM_DEBUG_KMS("failed to pin object\n"); | |
14795 | return PTR_ERR(vma); | |
14796 | } | |
7580d774 | 14797 | } |
fdd508a6 | 14798 | |
d07f0e59 | 14799 | return 0; |
6beb8c23 MR |
14800 | } |
14801 | ||
38f3ce3a MR |
14802 | /** |
14803 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
14804 | * @plane: drm plane to clean up for | |
14805 | * @fb: old framebuffer that was on plane | |
14806 | * | |
14807 | * Cleans up a framebuffer that has just been removed from a plane. | |
f935675f ML |
14808 | * |
14809 | * Must be called with struct_mutex held. | |
38f3ce3a MR |
14810 | */ |
14811 | void | |
14812 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
1832040d | 14813 | struct drm_plane_state *old_state) |
38f3ce3a MR |
14814 | { |
14815 | struct drm_device *dev = plane->dev; | |
7580d774 | 14816 | struct intel_plane_state *old_intel_state; |
1ee49399 ML |
14817 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb); |
14818 | struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb); | |
38f3ce3a | 14819 | |
7580d774 ML |
14820 | old_intel_state = to_intel_plane_state(old_state); |
14821 | ||
1ee49399 | 14822 | if (!obj && !old_obj) |
38f3ce3a MR |
14823 | return; |
14824 | ||
1ee49399 ML |
14825 | if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR || |
14826 | !INTEL_INFO(dev)->cursor_needs_physical)) | |
3465c580 | 14827 | intel_unpin_fb_obj(old_state->fb, old_state->rotation); |
465c120c MR |
14828 | } |
14829 | ||
6156a456 CK |
14830 | int |
14831 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
14832 | { | |
14833 | int max_scale; | |
6156a456 CK |
14834 | int crtc_clock, cdclk; |
14835 | ||
bf8a0af0 | 14836 | if (!intel_crtc || !crtc_state->base.enable) |
6156a456 CK |
14837 | return DRM_PLANE_HELPER_NO_SCALING; |
14838 | ||
6156a456 | 14839 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; |
27c329ed | 14840 | cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; |
6156a456 | 14841 | |
54bf1ce6 | 14842 | if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)) |
6156a456 CK |
14843 | return DRM_PLANE_HELPER_NO_SCALING; |
14844 | ||
14845 | /* | |
14846 | * skl max scale is lower of: | |
14847 | * close to 3 but not 3, -1 is for that purpose | |
14848 | * or | |
14849 | * cdclk/crtc_clock | |
14850 | */ | |
14851 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); | |
14852 | ||
14853 | return max_scale; | |
14854 | } | |
14855 | ||
465c120c | 14856 | static int |
3c692a41 | 14857 | intel_check_primary_plane(struct drm_plane *plane, |
061e4b8d | 14858 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
14859 | struct intel_plane_state *state) |
14860 | { | |
b63a16f6 | 14861 | struct drm_i915_private *dev_priv = to_i915(plane->dev); |
2b875c22 | 14862 | struct drm_crtc *crtc = state->base.crtc; |
6156a456 | 14863 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
14864 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
14865 | bool can_position = false; | |
b63a16f6 | 14866 | int ret; |
465c120c | 14867 | |
b63a16f6 | 14868 | if (INTEL_GEN(dev_priv) >= 9) { |
693bdc28 VS |
14869 | /* use scaler when colorkey is not required */ |
14870 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { | |
14871 | min_scale = 1; | |
14872 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
14873 | } | |
d8106366 | 14874 | can_position = true; |
6156a456 | 14875 | } |
d8106366 | 14876 | |
cc926387 DV |
14877 | ret = drm_plane_helper_check_state(&state->base, |
14878 | &state->clip, | |
14879 | min_scale, max_scale, | |
14880 | can_position, true); | |
b63a16f6 VS |
14881 | if (ret) |
14882 | return ret; | |
14883 | ||
cc926387 | 14884 | if (!state->base.fb) |
b63a16f6 VS |
14885 | return 0; |
14886 | ||
14887 | if (INTEL_GEN(dev_priv) >= 9) { | |
14888 | ret = skl_check_plane_surface(state); | |
14889 | if (ret) | |
14890 | return ret; | |
14891 | } | |
14892 | ||
14893 | return 0; | |
14af293f GP |
14894 | } |
14895 | ||
5a21b665 DV |
14896 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
14897 | struct drm_crtc_state *old_crtc_state) | |
14898 | { | |
14899 | struct drm_device *dev = crtc->dev; | |
62e0fb88 | 14900 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 | 14901 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
b707aa50 L |
14902 | struct intel_crtc_state *intel_cstate = |
14903 | to_intel_crtc_state(crtc->state); | |
5a21b665 DV |
14904 | struct intel_crtc_state *old_intel_state = |
14905 | to_intel_crtc_state(old_crtc_state); | |
14906 | bool modeset = needs_modeset(crtc->state); | |
62e0fb88 | 14907 | enum pipe pipe = intel_crtc->pipe; |
5a21b665 DV |
14908 | |
14909 | /* Perform vblank evasion around commit operation */ | |
14910 | intel_pipe_update_start(intel_crtc); | |
14911 | ||
14912 | if (modeset) | |
14913 | return; | |
14914 | ||
14915 | if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) { | |
14916 | intel_color_set_csc(crtc->state); | |
14917 | intel_color_load_luts(crtc->state); | |
14918 | } | |
14919 | ||
b707aa50 | 14920 | if (intel_cstate->update_pipe) { |
5a21b665 | 14921 | intel_update_pipe_config(intel_crtc, old_intel_state); |
b707aa50 | 14922 | } else if (INTEL_GEN(dev_priv) >= 9) { |
5a21b665 | 14923 | skl_detach_scalers(intel_crtc); |
62e0fb88 L |
14924 | |
14925 | I915_WRITE(PIPE_WM_LINETIME(pipe), | |
b707aa50 | 14926 | intel_cstate->wm.skl.optimal.linetime); |
62e0fb88 | 14927 | } |
5a21b665 DV |
14928 | } |
14929 | ||
14930 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, | |
14931 | struct drm_crtc_state *old_crtc_state) | |
14932 | { | |
14933 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
14934 | ||
14935 | intel_pipe_update_end(intel_crtc, NULL); | |
14936 | } | |
14937 | ||
cf4c7c12 | 14938 | /** |
4a3b8769 MR |
14939 | * intel_plane_destroy - destroy a plane |
14940 | * @plane: plane to destroy | |
cf4c7c12 | 14941 | * |
4a3b8769 MR |
14942 | * Common destruction function for all types of planes (primary, cursor, |
14943 | * sprite). | |
cf4c7c12 | 14944 | */ |
4a3b8769 | 14945 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c | 14946 | { |
465c120c | 14947 | drm_plane_cleanup(plane); |
69ae561f | 14948 | kfree(to_intel_plane(plane)); |
465c120c MR |
14949 | } |
14950 | ||
65a3fea0 | 14951 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
14952 | .update_plane = drm_atomic_helper_update_plane, |
14953 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 14954 | .destroy = intel_plane_destroy, |
c196e1d6 | 14955 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
14956 | .atomic_get_property = intel_plane_atomic_get_property, |
14957 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
14958 | .atomic_duplicate_state = intel_plane_duplicate_state, |
14959 | .atomic_destroy_state = intel_plane_destroy_state, | |
465c120c MR |
14960 | }; |
14961 | ||
b079bd17 | 14962 | static struct intel_plane * |
580503c7 | 14963 | intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) |
465c120c | 14964 | { |
fca0ce2a VS |
14965 | struct intel_plane *primary = NULL; |
14966 | struct intel_plane_state *state = NULL; | |
465c120c | 14967 | const uint32_t *intel_primary_formats; |
93ca7e00 | 14968 | unsigned int supported_rotations; |
45e3743a | 14969 | unsigned int num_formats; |
fca0ce2a | 14970 | int ret; |
465c120c MR |
14971 | |
14972 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
b079bd17 VS |
14973 | if (!primary) { |
14974 | ret = -ENOMEM; | |
fca0ce2a | 14975 | goto fail; |
b079bd17 | 14976 | } |
465c120c | 14977 | |
8e7d688b | 14978 | state = intel_create_plane_state(&primary->base); |
b079bd17 VS |
14979 | if (!state) { |
14980 | ret = -ENOMEM; | |
fca0ce2a | 14981 | goto fail; |
b079bd17 VS |
14982 | } |
14983 | ||
8e7d688b | 14984 | primary->base.state = &state->base; |
ea2c67bb | 14985 | |
465c120c MR |
14986 | primary->can_scale = false; |
14987 | primary->max_downscale = 1; | |
580503c7 | 14988 | if (INTEL_GEN(dev_priv) >= 9) { |
6156a456 | 14989 | primary->can_scale = true; |
af99ceda | 14990 | state->scaler_id = -1; |
6156a456 | 14991 | } |
465c120c MR |
14992 | primary->pipe = pipe; |
14993 | primary->plane = pipe; | |
a9ff8714 | 14994 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 | 14995 | primary->check_plane = intel_check_primary_plane; |
580503c7 | 14996 | if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4) |
465c120c MR |
14997 | primary->plane = !pipe; |
14998 | ||
580503c7 | 14999 | if (INTEL_GEN(dev_priv) >= 9) { |
6c0fd451 DL |
15000 | intel_primary_formats = skl_primary_formats; |
15001 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
a8d201af ML |
15002 | |
15003 | primary->update_plane = skylake_update_primary_plane; | |
15004 | primary->disable_plane = skylake_disable_primary_plane; | |
6e266956 | 15005 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
a8d201af ML |
15006 | intel_primary_formats = i965_primary_formats; |
15007 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
15008 | ||
15009 | primary->update_plane = ironlake_update_primary_plane; | |
15010 | primary->disable_plane = i9xx_disable_primary_plane; | |
580503c7 | 15011 | } else if (INTEL_GEN(dev_priv) >= 4) { |
568db4f2 DL |
15012 | intel_primary_formats = i965_primary_formats; |
15013 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
a8d201af ML |
15014 | |
15015 | primary->update_plane = i9xx_update_primary_plane; | |
15016 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 DL |
15017 | } else { |
15018 | intel_primary_formats = i8xx_primary_formats; | |
15019 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
a8d201af ML |
15020 | |
15021 | primary->update_plane = i9xx_update_primary_plane; | |
15022 | primary->disable_plane = i9xx_disable_primary_plane; | |
465c120c MR |
15023 | } |
15024 | ||
580503c7 VS |
15025 | if (INTEL_GEN(dev_priv) >= 9) |
15026 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, | |
15027 | 0, &intel_plane_funcs, | |
38573dc1 VS |
15028 | intel_primary_formats, num_formats, |
15029 | DRM_PLANE_TYPE_PRIMARY, | |
15030 | "plane 1%c", pipe_name(pipe)); | |
9beb5fea | 15031 | else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) |
580503c7 VS |
15032 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, |
15033 | 0, &intel_plane_funcs, | |
38573dc1 VS |
15034 | intel_primary_formats, num_formats, |
15035 | DRM_PLANE_TYPE_PRIMARY, | |
15036 | "primary %c", pipe_name(pipe)); | |
15037 | else | |
580503c7 VS |
15038 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, |
15039 | 0, &intel_plane_funcs, | |
38573dc1 VS |
15040 | intel_primary_formats, num_formats, |
15041 | DRM_PLANE_TYPE_PRIMARY, | |
15042 | "plane %c", plane_name(primary->plane)); | |
fca0ce2a VS |
15043 | if (ret) |
15044 | goto fail; | |
48404c1e | 15045 | |
5481e27f | 15046 | if (INTEL_GEN(dev_priv) >= 9) { |
93ca7e00 VS |
15047 | supported_rotations = |
15048 | DRM_ROTATE_0 | DRM_ROTATE_90 | | |
15049 | DRM_ROTATE_180 | DRM_ROTATE_270; | |
5481e27f | 15050 | } else if (INTEL_GEN(dev_priv) >= 4) { |
93ca7e00 VS |
15051 | supported_rotations = |
15052 | DRM_ROTATE_0 | DRM_ROTATE_180; | |
15053 | } else { | |
15054 | supported_rotations = DRM_ROTATE_0; | |
15055 | } | |
15056 | ||
5481e27f | 15057 | if (INTEL_GEN(dev_priv) >= 4) |
93ca7e00 VS |
15058 | drm_plane_create_rotation_property(&primary->base, |
15059 | DRM_ROTATE_0, | |
15060 | supported_rotations); | |
48404c1e | 15061 | |
ea2c67bb MR |
15062 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
15063 | ||
b079bd17 | 15064 | return primary; |
fca0ce2a VS |
15065 | |
15066 | fail: | |
15067 | kfree(state); | |
15068 | kfree(primary); | |
15069 | ||
b079bd17 | 15070 | return ERR_PTR(ret); |
465c120c MR |
15071 | } |
15072 | ||
3d7d6510 | 15073 | static int |
852e787c | 15074 | intel_check_cursor_plane(struct drm_plane *plane, |
061e4b8d | 15075 | struct intel_crtc_state *crtc_state, |
852e787c | 15076 | struct intel_plane_state *state) |
3d7d6510 | 15077 | { |
2b875c22 | 15078 | struct drm_framebuffer *fb = state->base.fb; |
757f9a3e | 15079 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
b29ec92c | 15080 | enum pipe pipe = to_intel_plane(plane)->pipe; |
757f9a3e GP |
15081 | unsigned stride; |
15082 | int ret; | |
3d7d6510 | 15083 | |
f8856a44 VS |
15084 | ret = drm_plane_helper_check_state(&state->base, |
15085 | &state->clip, | |
15086 | DRM_PLANE_HELPER_NO_SCALING, | |
15087 | DRM_PLANE_HELPER_NO_SCALING, | |
15088 | true, true); | |
757f9a3e GP |
15089 | if (ret) |
15090 | return ret; | |
15091 | ||
757f9a3e GP |
15092 | /* if we want to turn off the cursor ignore width and height */ |
15093 | if (!obj) | |
da20eabd | 15094 | return 0; |
757f9a3e | 15095 | |
757f9a3e | 15096 | /* Check for which cursor types we support */ |
50a0bc90 TU |
15097 | if (!cursor_size_ok(to_i915(plane->dev), state->base.crtc_w, |
15098 | state->base.crtc_h)) { | |
ea2c67bb MR |
15099 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", |
15100 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
15101 | return -EINVAL; |
15102 | } | |
15103 | ||
ea2c67bb MR |
15104 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
15105 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
15106 | DRM_DEBUG_KMS("buffer is too small\n"); |
15107 | return -ENOMEM; | |
15108 | } | |
15109 | ||
3a656b54 | 15110 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e | 15111 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
da20eabd | 15112 | return -EINVAL; |
32b7eeec MR |
15113 | } |
15114 | ||
b29ec92c VS |
15115 | /* |
15116 | * There's something wrong with the cursor on CHV pipe C. | |
15117 | * If it straddles the left edge of the screen then | |
15118 | * moving it away from the edge or disabling it often | |
15119 | * results in a pipe underrun, and often that can lead to | |
15120 | * dead pipe (constant underrun reported, and it scans | |
15121 | * out just a solid color). To recover from that, the | |
15122 | * display power well must be turned off and on again. | |
15123 | * Refuse the put the cursor into that compromised position. | |
15124 | */ | |
920a14b2 | 15125 | if (IS_CHERRYVIEW(to_i915(plane->dev)) && pipe == PIPE_C && |
936e71e3 | 15126 | state->base.visible && state->base.crtc_x < 0) { |
b29ec92c VS |
15127 | DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); |
15128 | return -EINVAL; | |
15129 | } | |
15130 | ||
da20eabd | 15131 | return 0; |
852e787c | 15132 | } |
3d7d6510 | 15133 | |
a8ad0d8e ML |
15134 | static void |
15135 | intel_disable_cursor_plane(struct drm_plane *plane, | |
7fabf5ef | 15136 | struct drm_crtc *crtc) |
a8ad0d8e | 15137 | { |
f2858021 ML |
15138 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
15139 | ||
15140 | intel_crtc->cursor_addr = 0; | |
55a08b3f | 15141 | intel_crtc_update_cursor(crtc, NULL); |
a8ad0d8e ML |
15142 | } |
15143 | ||
f4a2cf29 | 15144 | static void |
55a08b3f ML |
15145 | intel_update_cursor_plane(struct drm_plane *plane, |
15146 | const struct intel_crtc_state *crtc_state, | |
15147 | const struct intel_plane_state *state) | |
852e787c | 15148 | { |
55a08b3f ML |
15149 | struct drm_crtc *crtc = crtc_state->base.crtc; |
15150 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ea2c67bb | 15151 | struct drm_device *dev = plane->dev; |
2b875c22 | 15152 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 15153 | uint32_t addr; |
852e787c | 15154 | |
f4a2cf29 | 15155 | if (!obj) |
a912f12f | 15156 | addr = 0; |
f4a2cf29 | 15157 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
058d88c4 | 15158 | addr = i915_gem_object_ggtt_offset(obj, NULL); |
f4a2cf29 | 15159 | else |
a912f12f | 15160 | addr = obj->phys_handle->busaddr; |
852e787c | 15161 | |
a912f12f | 15162 | intel_crtc->cursor_addr = addr; |
55a08b3f | 15163 | intel_crtc_update_cursor(crtc, state); |
852e787c GP |
15164 | } |
15165 | ||
b079bd17 | 15166 | static struct intel_plane * |
580503c7 | 15167 | intel_cursor_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) |
3d7d6510 | 15168 | { |
fca0ce2a VS |
15169 | struct intel_plane *cursor = NULL; |
15170 | struct intel_plane_state *state = NULL; | |
15171 | int ret; | |
3d7d6510 MR |
15172 | |
15173 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
b079bd17 VS |
15174 | if (!cursor) { |
15175 | ret = -ENOMEM; | |
fca0ce2a | 15176 | goto fail; |
b079bd17 | 15177 | } |
3d7d6510 | 15178 | |
8e7d688b | 15179 | state = intel_create_plane_state(&cursor->base); |
b079bd17 VS |
15180 | if (!state) { |
15181 | ret = -ENOMEM; | |
fca0ce2a | 15182 | goto fail; |
b079bd17 VS |
15183 | } |
15184 | ||
8e7d688b | 15185 | cursor->base.state = &state->base; |
ea2c67bb | 15186 | |
3d7d6510 MR |
15187 | cursor->can_scale = false; |
15188 | cursor->max_downscale = 1; | |
15189 | cursor->pipe = pipe; | |
15190 | cursor->plane = pipe; | |
a9ff8714 | 15191 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
c59cb179 | 15192 | cursor->check_plane = intel_check_cursor_plane; |
55a08b3f | 15193 | cursor->update_plane = intel_update_cursor_plane; |
a8ad0d8e | 15194 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 | 15195 | |
580503c7 VS |
15196 | ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base, |
15197 | 0, &intel_plane_funcs, | |
fca0ce2a VS |
15198 | intel_cursor_formats, |
15199 | ARRAY_SIZE(intel_cursor_formats), | |
38573dc1 VS |
15200 | DRM_PLANE_TYPE_CURSOR, |
15201 | "cursor %c", pipe_name(pipe)); | |
fca0ce2a VS |
15202 | if (ret) |
15203 | goto fail; | |
4398ad45 | 15204 | |
5481e27f | 15205 | if (INTEL_GEN(dev_priv) >= 4) |
93ca7e00 VS |
15206 | drm_plane_create_rotation_property(&cursor->base, |
15207 | DRM_ROTATE_0, | |
15208 | DRM_ROTATE_0 | | |
15209 | DRM_ROTATE_180); | |
4398ad45 | 15210 | |
580503c7 | 15211 | if (INTEL_GEN(dev_priv) >= 9) |
af99ceda CK |
15212 | state->scaler_id = -1; |
15213 | ||
ea2c67bb MR |
15214 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
15215 | ||
b079bd17 | 15216 | return cursor; |
fca0ce2a VS |
15217 | |
15218 | fail: | |
15219 | kfree(state); | |
15220 | kfree(cursor); | |
15221 | ||
b079bd17 | 15222 | return ERR_PTR(ret); |
3d7d6510 MR |
15223 | } |
15224 | ||
549e2bfb CK |
15225 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
15226 | struct intel_crtc_state *crtc_state) | |
15227 | { | |
15228 | int i; | |
15229 | struct intel_scaler *intel_scaler; | |
15230 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; | |
15231 | ||
15232 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
15233 | intel_scaler = &scaler_state->scalers[i]; | |
15234 | intel_scaler->in_use = 0; | |
549e2bfb CK |
15235 | intel_scaler->mode = PS_SCALER_MODE_DYN; |
15236 | } | |
15237 | ||
15238 | scaler_state->scaler_id = -1; | |
15239 | } | |
15240 | ||
b079bd17 | 15241 | static int intel_crtc_init(struct drm_device *dev, enum pipe pipe) |
79e53945 | 15242 | { |
fac5e23e | 15243 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 15244 | struct intel_crtc *intel_crtc; |
f5de6e07 | 15245 | struct intel_crtc_state *crtc_state = NULL; |
b079bd17 VS |
15246 | struct intel_plane *primary = NULL; |
15247 | struct intel_plane *cursor = NULL; | |
a81d6fa0 | 15248 | int sprite, ret; |
79e53945 | 15249 | |
955382f3 | 15250 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
b079bd17 VS |
15251 | if (!intel_crtc) |
15252 | return -ENOMEM; | |
79e53945 | 15253 | |
f5de6e07 | 15254 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
b079bd17 VS |
15255 | if (!crtc_state) { |
15256 | ret = -ENOMEM; | |
f5de6e07 | 15257 | goto fail; |
b079bd17 | 15258 | } |
550acefd ACO |
15259 | intel_crtc->config = crtc_state; |
15260 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 15261 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 15262 | |
549e2bfb CK |
15263 | /* initialize shared scalers */ |
15264 | if (INTEL_INFO(dev)->gen >= 9) { | |
15265 | if (pipe == PIPE_C) | |
15266 | intel_crtc->num_scalers = 1; | |
15267 | else | |
15268 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
15269 | ||
15270 | skl_init_scalers(dev, intel_crtc, crtc_state); | |
15271 | } | |
15272 | ||
580503c7 | 15273 | primary = intel_primary_plane_create(dev_priv, pipe); |
b079bd17 VS |
15274 | if (IS_ERR(primary)) { |
15275 | ret = PTR_ERR(primary); | |
3d7d6510 | 15276 | goto fail; |
b079bd17 | 15277 | } |
3d7d6510 | 15278 | |
a81d6fa0 | 15279 | for_each_sprite(dev_priv, pipe, sprite) { |
b079bd17 VS |
15280 | struct intel_plane *plane; |
15281 | ||
580503c7 | 15282 | plane = intel_sprite_plane_create(dev_priv, pipe, sprite); |
b079bd17 VS |
15283 | if (!plane) { |
15284 | ret = PTR_ERR(plane); | |
15285 | goto fail; | |
15286 | } | |
a81d6fa0 VS |
15287 | } |
15288 | ||
580503c7 | 15289 | cursor = intel_cursor_plane_create(dev_priv, pipe); |
b079bd17 VS |
15290 | if (!cursor) { |
15291 | ret = PTR_ERR(cursor); | |
3d7d6510 | 15292 | goto fail; |
b079bd17 | 15293 | } |
3d7d6510 | 15294 | |
b079bd17 VS |
15295 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, |
15296 | &primary->base, &cursor->base, | |
15297 | &intel_crtc_funcs, | |
4d5d72b7 | 15298 | "pipe %c", pipe_name(pipe)); |
3d7d6510 MR |
15299 | if (ret) |
15300 | goto fail; | |
79e53945 | 15301 | |
1f1c2e24 VS |
15302 | /* |
15303 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 15304 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 15305 | */ |
80824003 | 15306 | intel_crtc->pipe = pipe; |
b079bd17 | 15307 | intel_crtc->plane = (enum plane) pipe; |
3a77c4c4 | 15308 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 15309 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 15310 | intel_crtc->plane = !pipe; |
80824003 JB |
15311 | } |
15312 | ||
4b0e333e CW |
15313 | intel_crtc->cursor_base = ~0; |
15314 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 15315 | intel_crtc->cursor_size = ~0; |
8d7849db | 15316 | |
852eb00d VS |
15317 | intel_crtc->wm.cxsr_allowed = true; |
15318 | ||
22fd0fab JB |
15319 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
15320 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
15321 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
15322 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
15323 | ||
79e53945 | 15324 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 | 15325 | |
8563b1e8 LL |
15326 | intel_color_init(&intel_crtc->base); |
15327 | ||
87b6b101 | 15328 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); |
b079bd17 VS |
15329 | |
15330 | return 0; | |
3d7d6510 MR |
15331 | |
15332 | fail: | |
b079bd17 VS |
15333 | /* |
15334 | * drm_mode_config_cleanup() will free up any | |
15335 | * crtcs/planes already initialized. | |
15336 | */ | |
f5de6e07 | 15337 | kfree(crtc_state); |
3d7d6510 | 15338 | kfree(intel_crtc); |
b079bd17 VS |
15339 | |
15340 | return ret; | |
79e53945 JB |
15341 | } |
15342 | ||
752aa88a JB |
15343 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
15344 | { | |
15345 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 15346 | struct drm_device *dev = connector->base.dev; |
752aa88a | 15347 | |
51fd371b | 15348 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 15349 | |
d3babd3f | 15350 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
15351 | return INVALID_PIPE; |
15352 | ||
15353 | return to_intel_crtc(encoder->crtc)->pipe; | |
15354 | } | |
15355 | ||
08d7b3d1 | 15356 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 15357 | struct drm_file *file) |
08d7b3d1 | 15358 | { |
08d7b3d1 | 15359 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 15360 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 15361 | struct intel_crtc *crtc; |
08d7b3d1 | 15362 | |
7707e653 | 15363 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
71240ed2 | 15364 | if (!drmmode_crtc) |
3f2c2057 | 15365 | return -ENOENT; |
08d7b3d1 | 15366 | |
7707e653 | 15367 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 15368 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 15369 | |
c05422d5 | 15370 | return 0; |
08d7b3d1 CW |
15371 | } |
15372 | ||
66a9278e | 15373 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 15374 | { |
66a9278e DV |
15375 | struct drm_device *dev = encoder->base.dev; |
15376 | struct intel_encoder *source_encoder; | |
79e53945 | 15377 | int index_mask = 0; |
79e53945 JB |
15378 | int entry = 0; |
15379 | ||
b2784e15 | 15380 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 15381 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
15382 | index_mask |= (1 << entry); |
15383 | ||
79e53945 JB |
15384 | entry++; |
15385 | } | |
4ef69c7a | 15386 | |
79e53945 JB |
15387 | return index_mask; |
15388 | } | |
15389 | ||
4d302442 CW |
15390 | static bool has_edp_a(struct drm_device *dev) |
15391 | { | |
fac5e23e | 15392 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d302442 CW |
15393 | |
15394 | if (!IS_MOBILE(dev)) | |
15395 | return false; | |
15396 | ||
15397 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
15398 | return false; | |
15399 | ||
5db94019 | 15400 | if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
15401 | return false; |
15402 | ||
15403 | return true; | |
15404 | } | |
15405 | ||
84b4e042 JB |
15406 | static bool intel_crt_present(struct drm_device *dev) |
15407 | { | |
fac5e23e | 15408 | struct drm_i915_private *dev_priv = to_i915(dev); |
84b4e042 | 15409 | |
884497ed DL |
15410 | if (INTEL_INFO(dev)->gen >= 9) |
15411 | return false; | |
15412 | ||
50a0bc90 | 15413 | if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) |
84b4e042 JB |
15414 | return false; |
15415 | ||
920a14b2 | 15416 | if (IS_CHERRYVIEW(dev_priv)) |
84b4e042 JB |
15417 | return false; |
15418 | ||
4f8036a2 TU |
15419 | if (HAS_PCH_LPT_H(dev_priv) && |
15420 | I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) | |
65e472e4 VS |
15421 | return false; |
15422 | ||
70ac54d0 | 15423 | /* DDI E can't be used if DDI A requires 4 lanes */ |
4f8036a2 | 15424 | if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) |
70ac54d0 VS |
15425 | return false; |
15426 | ||
e4abb733 | 15427 | if (!dev_priv->vbt.int_crt_support) |
84b4e042 JB |
15428 | return false; |
15429 | ||
15430 | return true; | |
15431 | } | |
15432 | ||
8090ba8c ID |
15433 | void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv) |
15434 | { | |
15435 | int pps_num; | |
15436 | int pps_idx; | |
15437 | ||
15438 | if (HAS_DDI(dev_priv)) | |
15439 | return; | |
15440 | /* | |
15441 | * This w/a is needed at least on CPT/PPT, but to be sure apply it | |
15442 | * everywhere where registers can be write protected. | |
15443 | */ | |
15444 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
15445 | pps_num = 2; | |
15446 | else | |
15447 | pps_num = 1; | |
15448 | ||
15449 | for (pps_idx = 0; pps_idx < pps_num; pps_idx++) { | |
15450 | u32 val = I915_READ(PP_CONTROL(pps_idx)); | |
15451 | ||
15452 | val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS; | |
15453 | I915_WRITE(PP_CONTROL(pps_idx), val); | |
15454 | } | |
15455 | } | |
15456 | ||
44cb734c ID |
15457 | static void intel_pps_init(struct drm_i915_private *dev_priv) |
15458 | { | |
15459 | if (HAS_PCH_SPLIT(dev_priv) || IS_BROXTON(dev_priv)) | |
15460 | dev_priv->pps_mmio_base = PCH_PPS_BASE; | |
15461 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
15462 | dev_priv->pps_mmio_base = VLV_PPS_BASE; | |
15463 | else | |
15464 | dev_priv->pps_mmio_base = PPS_BASE; | |
8090ba8c ID |
15465 | |
15466 | intel_pps_unlock_regs_wa(dev_priv); | |
44cb734c ID |
15467 | } |
15468 | ||
79e53945 JB |
15469 | static void intel_setup_outputs(struct drm_device *dev) |
15470 | { | |
fac5e23e | 15471 | struct drm_i915_private *dev_priv = to_i915(dev); |
4ef69c7a | 15472 | struct intel_encoder *encoder; |
cb0953d7 | 15473 | bool dpd_is_edp = false; |
79e53945 | 15474 | |
44cb734c ID |
15475 | intel_pps_init(dev_priv); |
15476 | ||
97a824e1 ID |
15477 | /* |
15478 | * intel_edp_init_connector() depends on this completing first, to | |
15479 | * prevent the registeration of both eDP and LVDS and the incorrect | |
15480 | * sharing of the PPS. | |
15481 | */ | |
c9093354 | 15482 | intel_lvds_init(dev); |
79e53945 | 15483 | |
84b4e042 | 15484 | if (intel_crt_present(dev)) |
79935fca | 15485 | intel_crt_init(dev); |
cb0953d7 | 15486 | |
e2d214ae | 15487 | if (IS_BROXTON(dev_priv)) { |
c776eb2e VK |
15488 | /* |
15489 | * FIXME: Broxton doesn't support port detection via the | |
15490 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
15491 | * detect the ports. | |
15492 | */ | |
15493 | intel_ddi_init(dev, PORT_A); | |
15494 | intel_ddi_init(dev, PORT_B); | |
15495 | intel_ddi_init(dev, PORT_C); | |
c6c794a2 SS |
15496 | |
15497 | intel_dsi_init(dev); | |
4f8036a2 | 15498 | } else if (HAS_DDI(dev_priv)) { |
0e72a5b5 ED |
15499 | int found; |
15500 | ||
de31facd JB |
15501 | /* |
15502 | * Haswell uses DDI functions to detect digital outputs. | |
15503 | * On SKL pre-D0 the strap isn't connected, so we assume | |
15504 | * it's there. | |
15505 | */ | |
77179400 | 15506 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 15507 | /* WaIgnoreDDIAStrap: skl */ |
0853723b | 15508 | if (found || IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
0e72a5b5 ED |
15509 | intel_ddi_init(dev, PORT_A); |
15510 | ||
15511 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
15512 | * register */ | |
15513 | found = I915_READ(SFUSE_STRAP); | |
15514 | ||
15515 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
15516 | intel_ddi_init(dev, PORT_B); | |
15517 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
15518 | intel_ddi_init(dev, PORT_C); | |
15519 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
15520 | intel_ddi_init(dev, PORT_D); | |
2800e4c2 RV |
15521 | /* |
15522 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
15523 | */ | |
0853723b | 15524 | if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) && |
2800e4c2 RV |
15525 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
15526 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
15527 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
15528 | intel_ddi_init(dev, PORT_E); | |
15529 | ||
6e266956 | 15530 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
cb0953d7 | 15531 | int found; |
5d8a7752 | 15532 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
15533 | |
15534 | if (has_edp_a(dev)) | |
15535 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 15536 | |
dc0fa718 | 15537 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 15538 | /* PCH SDVOB multiplex with HDMIB */ |
2a5c0832 | 15539 | found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B); |
30ad48b7 | 15540 | if (!found) |
e2debe91 | 15541 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 15542 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 15543 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
15544 | } |
15545 | ||
dc0fa718 | 15546 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 15547 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 15548 | |
dc0fa718 | 15549 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 15550 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 15551 | |
5eb08b69 | 15552 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 15553 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 15554 | |
270b3042 | 15555 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 15556 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
920a14b2 | 15557 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
22f35042 | 15558 | bool has_edp, has_port; |
457c52d8 | 15559 | |
e17ac6db VS |
15560 | /* |
15561 | * The DP_DETECTED bit is the latched state of the DDC | |
15562 | * SDA pin at boot. However since eDP doesn't require DDC | |
15563 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
15564 | * eDP ports may have been muxed to an alternate function. | |
15565 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
15566 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
15567 | * detect eDP ports. | |
22f35042 VS |
15568 | * |
15569 | * Sadly the straps seem to be missing sometimes even for HDMI | |
15570 | * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap | |
15571 | * and VBT for the presence of the port. Additionally we can't | |
15572 | * trust the port type the VBT declares as we've seen at least | |
15573 | * HDMI ports that the VBT claim are DP or eDP. | |
e17ac6db | 15574 | */ |
457c52d8 | 15575 | has_edp = intel_dp_is_edp(dev, PORT_B); |
22f35042 VS |
15576 | has_port = intel_bios_is_port_present(dev_priv, PORT_B); |
15577 | if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port) | |
457c52d8 | 15578 | has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B); |
22f35042 | 15579 | if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) |
e66eb81d | 15580 | intel_hdmi_init(dev, VLV_HDMIB, PORT_B); |
585a94b8 | 15581 | |
457c52d8 | 15582 | has_edp = intel_dp_is_edp(dev, PORT_C); |
22f35042 VS |
15583 | has_port = intel_bios_is_port_present(dev_priv, PORT_C); |
15584 | if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port) | |
457c52d8 | 15585 | has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C); |
22f35042 | 15586 | if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) |
e66eb81d | 15587 | intel_hdmi_init(dev, VLV_HDMIC, PORT_C); |
19c03924 | 15588 | |
920a14b2 | 15589 | if (IS_CHERRYVIEW(dev_priv)) { |
22f35042 VS |
15590 | /* |
15591 | * eDP not supported on port D, | |
15592 | * so no need to worry about it | |
15593 | */ | |
15594 | has_port = intel_bios_is_port_present(dev_priv, PORT_D); | |
15595 | if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port) | |
e66eb81d | 15596 | intel_dp_init(dev, CHV_DP_D, PORT_D); |
22f35042 VS |
15597 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port) |
15598 | intel_hdmi_init(dev, CHV_HDMID, PORT_D); | |
9418c1f1 VS |
15599 | } |
15600 | ||
3cfca973 | 15601 | intel_dsi_init(dev); |
5db94019 | 15602 | } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) { |
27185ae1 | 15603 | bool found = false; |
7d57382e | 15604 | |
e2debe91 | 15605 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 15606 | DRM_DEBUG_KMS("probing SDVOB\n"); |
2a5c0832 | 15607 | found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B); |
9beb5fea | 15608 | if (!found && IS_G4X(dev_priv)) { |
b01f2c3a | 15609 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
e2debe91 | 15610 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 15611 | } |
27185ae1 | 15612 | |
9beb5fea | 15613 | if (!found && IS_G4X(dev_priv)) |
ab9d7c30 | 15614 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 15615 | } |
13520b05 KH |
15616 | |
15617 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 15618 | |
e2debe91 | 15619 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 15620 | DRM_DEBUG_KMS("probing SDVOC\n"); |
2a5c0832 | 15621 | found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C); |
b01f2c3a | 15622 | } |
27185ae1 | 15623 | |
e2debe91 | 15624 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 15625 | |
9beb5fea | 15626 | if (IS_G4X(dev_priv)) { |
b01f2c3a | 15627 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
e2debe91 | 15628 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 15629 | } |
9beb5fea | 15630 | if (IS_G4X(dev_priv)) |
ab9d7c30 | 15631 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 15632 | } |
27185ae1 | 15633 | |
9beb5fea | 15634 | if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 15635 | intel_dp_init(dev, DP_D, PORT_D); |
5db94019 | 15636 | } else if (IS_GEN2(dev_priv)) |
79e53945 JB |
15637 | intel_dvo_init(dev); |
15638 | ||
103a196f | 15639 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
15640 | intel_tv_init(dev); |
15641 | ||
0bc12bcb | 15642 | intel_psr_init(dev); |
7c8f8a70 | 15643 | |
b2784e15 | 15644 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
15645 | encoder->base.possible_crtcs = encoder->crtc_mask; |
15646 | encoder->base.possible_clones = | |
66a9278e | 15647 | intel_encoder_clones(encoder); |
79e53945 | 15648 | } |
47356eb6 | 15649 | |
dde86e2d | 15650 | intel_init_pch_refclk(dev); |
270b3042 DV |
15651 | |
15652 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
15653 | } |
15654 | ||
15655 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
15656 | { | |
60a5ca01 | 15657 | struct drm_device *dev = fb->dev; |
79e53945 | 15658 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 15659 | |
ef2d633e | 15660 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 15661 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 15662 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
f8c417cd | 15663 | i915_gem_object_put(intel_fb->obj); |
60a5ca01 | 15664 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
15665 | kfree(intel_fb); |
15666 | } | |
15667 | ||
15668 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 15669 | struct drm_file *file, |
79e53945 JB |
15670 | unsigned int *handle) |
15671 | { | |
15672 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 15673 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 15674 | |
cc917ab4 CW |
15675 | if (obj->userptr.mm) { |
15676 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); | |
15677 | return -EINVAL; | |
15678 | } | |
15679 | ||
05394f39 | 15680 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
15681 | } |
15682 | ||
86c98588 RV |
15683 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
15684 | struct drm_file *file, | |
15685 | unsigned flags, unsigned color, | |
15686 | struct drm_clip_rect *clips, | |
15687 | unsigned num_clips) | |
15688 | { | |
15689 | struct drm_device *dev = fb->dev; | |
15690 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
15691 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
15692 | ||
15693 | mutex_lock(&dev->struct_mutex); | |
74b4ea1e | 15694 | intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); |
86c98588 RV |
15695 | mutex_unlock(&dev->struct_mutex); |
15696 | ||
15697 | return 0; | |
15698 | } | |
15699 | ||
79e53945 JB |
15700 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
15701 | .destroy = intel_user_framebuffer_destroy, | |
15702 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 15703 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
15704 | }; |
15705 | ||
b321803d | 15706 | static |
920a14b2 TU |
15707 | u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv, |
15708 | uint64_t fb_modifier, uint32_t pixel_format) | |
b321803d | 15709 | { |
920a14b2 | 15710 | u32 gen = INTEL_INFO(dev_priv)->gen; |
b321803d DL |
15711 | |
15712 | if (gen >= 9) { | |
ac484963 VS |
15713 | int cpp = drm_format_plane_cpp(pixel_format, 0); |
15714 | ||
b321803d DL |
15715 | /* "The stride in bytes must not exceed the of the size of 8K |
15716 | * pixels and 32K bytes." | |
15717 | */ | |
ac484963 | 15718 | return min(8192 * cpp, 32768); |
920a14b2 TU |
15719 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev_priv) && |
15720 | !IS_CHERRYVIEW(dev_priv)) { | |
b321803d DL |
15721 | return 32*1024; |
15722 | } else if (gen >= 4) { | |
15723 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
15724 | return 16*1024; | |
15725 | else | |
15726 | return 32*1024; | |
15727 | } else if (gen >= 3) { | |
15728 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
15729 | return 8*1024; | |
15730 | else | |
15731 | return 16*1024; | |
15732 | } else { | |
15733 | /* XXX DSPC is limited to 4k tiled */ | |
15734 | return 8*1024; | |
15735 | } | |
15736 | } | |
15737 | ||
b5ea642a DV |
15738 | static int intel_framebuffer_init(struct drm_device *dev, |
15739 | struct intel_framebuffer *intel_fb, | |
15740 | struct drm_mode_fb_cmd2 *mode_cmd, | |
15741 | struct drm_i915_gem_object *obj) | |
79e53945 | 15742 | { |
7b49f948 | 15743 | struct drm_i915_private *dev_priv = to_i915(dev); |
c2ff7370 | 15744 | unsigned int tiling = i915_gem_object_get_tiling(obj); |
79e53945 | 15745 | int ret; |
b321803d | 15746 | u32 pitch_limit, stride_alignment; |
d3828147 | 15747 | char *format_name; |
79e53945 | 15748 | |
dd4916c5 DV |
15749 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
15750 | ||
2a80eada | 15751 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
c2ff7370 VS |
15752 | /* |
15753 | * If there's a fence, enforce that | |
15754 | * the fb modifier and tiling mode match. | |
15755 | */ | |
15756 | if (tiling != I915_TILING_NONE && | |
15757 | tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { | |
2a80eada DV |
15758 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); |
15759 | return -EINVAL; | |
15760 | } | |
15761 | } else { | |
c2ff7370 | 15762 | if (tiling == I915_TILING_X) { |
2a80eada | 15763 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; |
c2ff7370 | 15764 | } else if (tiling == I915_TILING_Y) { |
2a80eada DV |
15765 | DRM_DEBUG("No Y tiling for legacy addfb\n"); |
15766 | return -EINVAL; | |
15767 | } | |
15768 | } | |
15769 | ||
9a8f0a12 TU |
15770 | /* Passed in modifier sanity checking. */ |
15771 | switch (mode_cmd->modifier[0]) { | |
15772 | case I915_FORMAT_MOD_Y_TILED: | |
15773 | case I915_FORMAT_MOD_Yf_TILED: | |
15774 | if (INTEL_INFO(dev)->gen < 9) { | |
15775 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
15776 | mode_cmd->modifier[0]); | |
15777 | return -EINVAL; | |
15778 | } | |
15779 | case DRM_FORMAT_MOD_NONE: | |
15780 | case I915_FORMAT_MOD_X_TILED: | |
15781 | break; | |
15782 | default: | |
c0f40428 JB |
15783 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
15784 | mode_cmd->modifier[0]); | |
57cd6508 | 15785 | return -EINVAL; |
c16ed4be | 15786 | } |
57cd6508 | 15787 | |
c2ff7370 VS |
15788 | /* |
15789 | * gen2/3 display engine uses the fence if present, | |
15790 | * so the tiling mode must match the fb modifier exactly. | |
15791 | */ | |
15792 | if (INTEL_INFO(dev_priv)->gen < 4 && | |
15793 | tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { | |
15794 | DRM_DEBUG("tiling_mode must match fb modifier exactly on gen2/3\n"); | |
15795 | return -EINVAL; | |
15796 | } | |
15797 | ||
7b49f948 VS |
15798 | stride_alignment = intel_fb_stride_alignment(dev_priv, |
15799 | mode_cmd->modifier[0], | |
b321803d DL |
15800 | mode_cmd->pixel_format); |
15801 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
15802 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
15803 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 15804 | return -EINVAL; |
c16ed4be | 15805 | } |
57cd6508 | 15806 | |
920a14b2 | 15807 | pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0], |
b321803d | 15808 | mode_cmd->pixel_format); |
a35cdaa0 | 15809 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
15810 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
15811 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 15812 | "tiled" : "linear", |
a35cdaa0 | 15813 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 15814 | return -EINVAL; |
c16ed4be | 15815 | } |
5d7bd705 | 15816 | |
c2ff7370 VS |
15817 | /* |
15818 | * If there's a fence, enforce that | |
15819 | * the fb pitch and fence stride match. | |
15820 | */ | |
15821 | if (tiling != I915_TILING_NONE && | |
3e510a8e | 15822 | mode_cmd->pitches[0] != i915_gem_object_get_stride(obj)) { |
c16ed4be | 15823 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", |
3e510a8e CW |
15824 | mode_cmd->pitches[0], |
15825 | i915_gem_object_get_stride(obj)); | |
5d7bd705 | 15826 | return -EINVAL; |
c16ed4be | 15827 | } |
5d7bd705 | 15828 | |
57779d06 | 15829 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 15830 | switch (mode_cmd->pixel_format) { |
57779d06 | 15831 | case DRM_FORMAT_C8: |
04b3924d VS |
15832 | case DRM_FORMAT_RGB565: |
15833 | case DRM_FORMAT_XRGB8888: | |
15834 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
15835 | break; |
15836 | case DRM_FORMAT_XRGB1555: | |
c16ed4be | 15837 | if (INTEL_INFO(dev)->gen > 3) { |
90844f00 EE |
15838 | format_name = drm_get_format_name(mode_cmd->pixel_format); |
15839 | DRM_DEBUG("unsupported pixel format: %s\n", format_name); | |
15840 | kfree(format_name); | |
57779d06 | 15841 | return -EINVAL; |
c16ed4be | 15842 | } |
57779d06 | 15843 | break; |
57779d06 | 15844 | case DRM_FORMAT_ABGR8888: |
920a14b2 | 15845 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
666a4537 | 15846 | INTEL_INFO(dev)->gen < 9) { |
90844f00 EE |
15847 | format_name = drm_get_format_name(mode_cmd->pixel_format); |
15848 | DRM_DEBUG("unsupported pixel format: %s\n", format_name); | |
15849 | kfree(format_name); | |
6c0fd451 DL |
15850 | return -EINVAL; |
15851 | } | |
15852 | break; | |
15853 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 15854 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 15855 | case DRM_FORMAT_XBGR2101010: |
c16ed4be | 15856 | if (INTEL_INFO(dev)->gen < 4) { |
90844f00 EE |
15857 | format_name = drm_get_format_name(mode_cmd->pixel_format); |
15858 | DRM_DEBUG("unsupported pixel format: %s\n", format_name); | |
15859 | kfree(format_name); | |
57779d06 | 15860 | return -EINVAL; |
c16ed4be | 15861 | } |
b5626747 | 15862 | break; |
7531208b | 15863 | case DRM_FORMAT_ABGR2101010: |
920a14b2 | 15864 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { |
90844f00 EE |
15865 | format_name = drm_get_format_name(mode_cmd->pixel_format); |
15866 | DRM_DEBUG("unsupported pixel format: %s\n", format_name); | |
15867 | kfree(format_name); | |
7531208b DL |
15868 | return -EINVAL; |
15869 | } | |
15870 | break; | |
04b3924d VS |
15871 | case DRM_FORMAT_YUYV: |
15872 | case DRM_FORMAT_UYVY: | |
15873 | case DRM_FORMAT_YVYU: | |
15874 | case DRM_FORMAT_VYUY: | |
c16ed4be | 15875 | if (INTEL_INFO(dev)->gen < 5) { |
90844f00 EE |
15876 | format_name = drm_get_format_name(mode_cmd->pixel_format); |
15877 | DRM_DEBUG("unsupported pixel format: %s\n", format_name); | |
15878 | kfree(format_name); | |
57779d06 | 15879 | return -EINVAL; |
c16ed4be | 15880 | } |
57cd6508 CW |
15881 | break; |
15882 | default: | |
90844f00 EE |
15883 | format_name = drm_get_format_name(mode_cmd->pixel_format); |
15884 | DRM_DEBUG("unsupported pixel format: %s\n", format_name); | |
15885 | kfree(format_name); | |
57cd6508 CW |
15886 | return -EINVAL; |
15887 | } | |
15888 | ||
90f9a336 VS |
15889 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
15890 | if (mode_cmd->offsets[0] != 0) | |
15891 | return -EINVAL; | |
15892 | ||
c7d73f6a DV |
15893 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
15894 | intel_fb->obj = obj; | |
15895 | ||
6687c906 VS |
15896 | ret = intel_fill_fb_info(dev_priv, &intel_fb->base); |
15897 | if (ret) | |
15898 | return ret; | |
2d7a215f | 15899 | |
79e53945 JB |
15900 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
15901 | if (ret) { | |
15902 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
15903 | return ret; | |
15904 | } | |
15905 | ||
0b05e1e0 VS |
15906 | intel_fb->obj->framebuffer_references++; |
15907 | ||
79e53945 JB |
15908 | return 0; |
15909 | } | |
15910 | ||
79e53945 JB |
15911 | static struct drm_framebuffer * |
15912 | intel_user_framebuffer_create(struct drm_device *dev, | |
15913 | struct drm_file *filp, | |
1eb83451 | 15914 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
79e53945 | 15915 | { |
dcb1394e | 15916 | struct drm_framebuffer *fb; |
05394f39 | 15917 | struct drm_i915_gem_object *obj; |
76dc3769 | 15918 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
79e53945 | 15919 | |
03ac0642 CW |
15920 | obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]); |
15921 | if (!obj) | |
cce13ff7 | 15922 | return ERR_PTR(-ENOENT); |
79e53945 | 15923 | |
92907cbb | 15924 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
dcb1394e | 15925 | if (IS_ERR(fb)) |
f0cd5182 | 15926 | i915_gem_object_put(obj); |
dcb1394e LW |
15927 | |
15928 | return fb; | |
79e53945 JB |
15929 | } |
15930 | ||
79e53945 | 15931 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 15932 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 15933 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
15934 | .atomic_check = intel_atomic_check, |
15935 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
15936 | .atomic_state_alloc = intel_atomic_state_alloc, |
15937 | .atomic_state_clear = intel_atomic_state_clear, | |
79e53945 JB |
15938 | }; |
15939 | ||
88212941 ID |
15940 | /** |
15941 | * intel_init_display_hooks - initialize the display modesetting hooks | |
15942 | * @dev_priv: device private | |
15943 | */ | |
15944 | void intel_init_display_hooks(struct drm_i915_private *dev_priv) | |
e70236a8 | 15945 | { |
88212941 | 15946 | if (INTEL_INFO(dev_priv)->gen >= 9) { |
bc8d7dff | 15947 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
15948 | dev_priv->display.get_initial_plane_config = |
15949 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
15950 | dev_priv->display.crtc_compute_clock = |
15951 | haswell_crtc_compute_clock; | |
15952 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
15953 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 15954 | } else if (HAS_DDI(dev_priv)) { |
0e8ffe1b | 15955 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
15956 | dev_priv->display.get_initial_plane_config = |
15957 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
15958 | dev_priv->display.crtc_compute_clock = |
15959 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
15960 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
15961 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 15962 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
0e8ffe1b | 15963 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
15964 | dev_priv->display.get_initial_plane_config = |
15965 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
15966 | dev_priv->display.crtc_compute_clock = |
15967 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
15968 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
15969 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
65b3d6a9 | 15970 | } else if (IS_CHERRYVIEW(dev_priv)) { |
89b667f8 | 15971 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
15972 | dev_priv->display.get_initial_plane_config = |
15973 | i9xx_get_initial_plane_config; | |
65b3d6a9 ACO |
15974 | dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock; |
15975 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
15976 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
15977 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
15978 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
15979 | dev_priv->display.get_initial_plane_config = | |
15980 | i9xx_get_initial_plane_config; | |
15981 | dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock; | |
89b667f8 JB |
15982 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
15983 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
19ec6693 ACO |
15984 | } else if (IS_G4X(dev_priv)) { |
15985 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
15986 | dev_priv->display.get_initial_plane_config = | |
15987 | i9xx_get_initial_plane_config; | |
15988 | dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock; | |
15989 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
15990 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
70e8aa21 ACO |
15991 | } else if (IS_PINEVIEW(dev_priv)) { |
15992 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
15993 | dev_priv->display.get_initial_plane_config = | |
15994 | i9xx_get_initial_plane_config; | |
15995 | dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock; | |
15996 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
15997 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 | 15998 | } else if (!IS_GEN2(dev_priv)) { |
0e8ffe1b | 15999 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
16000 | dev_priv->display.get_initial_plane_config = |
16001 | i9xx_get_initial_plane_config; | |
d6dfee7a | 16002 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
16003 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
16004 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 ACO |
16005 | } else { |
16006 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
16007 | dev_priv->display.get_initial_plane_config = | |
16008 | i9xx_get_initial_plane_config; | |
16009 | dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock; | |
16010 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
16011 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 16012 | } |
e70236a8 | 16013 | |
e70236a8 | 16014 | /* Returns the core display clock speed */ |
88212941 | 16015 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
1652d19e VS |
16016 | dev_priv->display.get_display_clock_speed = |
16017 | skylake_get_display_clock_speed; | |
88212941 | 16018 | else if (IS_BROXTON(dev_priv)) |
acd3f3d3 BP |
16019 | dev_priv->display.get_display_clock_speed = |
16020 | broxton_get_display_clock_speed; | |
88212941 | 16021 | else if (IS_BROADWELL(dev_priv)) |
1652d19e VS |
16022 | dev_priv->display.get_display_clock_speed = |
16023 | broadwell_get_display_clock_speed; | |
88212941 | 16024 | else if (IS_HASWELL(dev_priv)) |
1652d19e VS |
16025 | dev_priv->display.get_display_clock_speed = |
16026 | haswell_get_display_clock_speed; | |
88212941 | 16027 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
25eb05fc JB |
16028 | dev_priv->display.get_display_clock_speed = |
16029 | valleyview_get_display_clock_speed; | |
88212941 | 16030 | else if (IS_GEN5(dev_priv)) |
b37a6434 VS |
16031 | dev_priv->display.get_display_clock_speed = |
16032 | ilk_get_display_clock_speed; | |
88212941 ID |
16033 | else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) || |
16034 | IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) | |
e70236a8 JB |
16035 | dev_priv->display.get_display_clock_speed = |
16036 | i945_get_display_clock_speed; | |
88212941 | 16037 | else if (IS_GM45(dev_priv)) |
34edce2f VS |
16038 | dev_priv->display.get_display_clock_speed = |
16039 | gm45_get_display_clock_speed; | |
88212941 | 16040 | else if (IS_CRESTLINE(dev_priv)) |
34edce2f VS |
16041 | dev_priv->display.get_display_clock_speed = |
16042 | i965gm_get_display_clock_speed; | |
88212941 | 16043 | else if (IS_PINEVIEW(dev_priv)) |
34edce2f VS |
16044 | dev_priv->display.get_display_clock_speed = |
16045 | pnv_get_display_clock_speed; | |
88212941 | 16046 | else if (IS_G33(dev_priv) || IS_G4X(dev_priv)) |
34edce2f VS |
16047 | dev_priv->display.get_display_clock_speed = |
16048 | g33_get_display_clock_speed; | |
88212941 | 16049 | else if (IS_I915G(dev_priv)) |
e70236a8 JB |
16050 | dev_priv->display.get_display_clock_speed = |
16051 | i915_get_display_clock_speed; | |
88212941 | 16052 | else if (IS_I945GM(dev_priv) || IS_845G(dev_priv)) |
e70236a8 JB |
16053 | dev_priv->display.get_display_clock_speed = |
16054 | i9xx_misc_get_display_clock_speed; | |
88212941 | 16055 | else if (IS_I915GM(dev_priv)) |
e70236a8 JB |
16056 | dev_priv->display.get_display_clock_speed = |
16057 | i915gm_get_display_clock_speed; | |
88212941 | 16058 | else if (IS_I865G(dev_priv)) |
e70236a8 JB |
16059 | dev_priv->display.get_display_clock_speed = |
16060 | i865_get_display_clock_speed; | |
88212941 | 16061 | else if (IS_I85X(dev_priv)) |
e70236a8 | 16062 | dev_priv->display.get_display_clock_speed = |
1b1d2716 | 16063 | i85x_get_display_clock_speed; |
623e01e5 | 16064 | else { /* 830 */ |
88212941 | 16065 | WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n"); |
e70236a8 JB |
16066 | dev_priv->display.get_display_clock_speed = |
16067 | i830_get_display_clock_speed; | |
623e01e5 | 16068 | } |
e70236a8 | 16069 | |
88212941 | 16070 | if (IS_GEN5(dev_priv)) { |
3bb11b53 | 16071 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
88212941 | 16072 | } else if (IS_GEN6(dev_priv)) { |
3bb11b53 | 16073 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
88212941 | 16074 | } else if (IS_IVYBRIDGE(dev_priv)) { |
3bb11b53 SJ |
16075 | /* FIXME: detect B0+ stepping and use auto training */ |
16076 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
88212941 | 16077 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
3bb11b53 | 16078 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
445e780b VS |
16079 | } |
16080 | ||
16081 | if (IS_BROADWELL(dev_priv)) { | |
16082 | dev_priv->display.modeset_commit_cdclk = | |
16083 | broadwell_modeset_commit_cdclk; | |
16084 | dev_priv->display.modeset_calc_cdclk = | |
16085 | broadwell_modeset_calc_cdclk; | |
88212941 | 16086 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
27c329ed ML |
16087 | dev_priv->display.modeset_commit_cdclk = |
16088 | valleyview_modeset_commit_cdclk; | |
16089 | dev_priv->display.modeset_calc_cdclk = | |
16090 | valleyview_modeset_calc_cdclk; | |
88212941 | 16091 | } else if (IS_BROXTON(dev_priv)) { |
27c329ed | 16092 | dev_priv->display.modeset_commit_cdclk = |
324513c0 | 16093 | bxt_modeset_commit_cdclk; |
27c329ed | 16094 | dev_priv->display.modeset_calc_cdclk = |
324513c0 | 16095 | bxt_modeset_calc_cdclk; |
c89e39f3 CT |
16096 | } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { |
16097 | dev_priv->display.modeset_commit_cdclk = | |
16098 | skl_modeset_commit_cdclk; | |
16099 | dev_priv->display.modeset_calc_cdclk = | |
16100 | skl_modeset_calc_cdclk; | |
e70236a8 | 16101 | } |
5a21b665 | 16102 | |
27082493 L |
16103 | if (dev_priv->info.gen >= 9) |
16104 | dev_priv->display.update_crtcs = skl_update_crtcs; | |
16105 | else | |
16106 | dev_priv->display.update_crtcs = intel_update_crtcs; | |
16107 | ||
5a21b665 DV |
16108 | switch (INTEL_INFO(dev_priv)->gen) { |
16109 | case 2: | |
16110 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
16111 | break; | |
16112 | ||
16113 | case 3: | |
16114 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
16115 | break; | |
16116 | ||
16117 | case 4: | |
16118 | case 5: | |
16119 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
16120 | break; | |
16121 | ||
16122 | case 6: | |
16123 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
16124 | break; | |
16125 | case 7: | |
16126 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ | |
16127 | dev_priv->display.queue_flip = intel_gen7_queue_flip; | |
16128 | break; | |
16129 | case 9: | |
16130 | /* Drop through - unsupported since execlist only. */ | |
16131 | default: | |
16132 | /* Default just returns -ENODEV to indicate unsupported */ | |
16133 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
16134 | } | |
e70236a8 JB |
16135 | } |
16136 | ||
b690e96c JB |
16137 | /* |
16138 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
16139 | * resume, or other times. This quirk makes sure that's the case for | |
16140 | * affected systems. | |
16141 | */ | |
0206e353 | 16142 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c | 16143 | { |
fac5e23e | 16144 | struct drm_i915_private *dev_priv = to_i915(dev); |
b690e96c JB |
16145 | |
16146 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 16147 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
16148 | } |
16149 | ||
b6b5d049 VS |
16150 | static void quirk_pipeb_force(struct drm_device *dev) |
16151 | { | |
fac5e23e | 16152 | struct drm_i915_private *dev_priv = to_i915(dev); |
b6b5d049 VS |
16153 | |
16154 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
16155 | DRM_INFO("applying pipe b force quirk\n"); | |
16156 | } | |
16157 | ||
435793df KP |
16158 | /* |
16159 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
16160 | */ | |
16161 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
16162 | { | |
fac5e23e | 16163 | struct drm_i915_private *dev_priv = to_i915(dev); |
435793df | 16164 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; |
bc0daf48 | 16165 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
16166 | } |
16167 | ||
4dca20ef | 16168 | /* |
5a15ab5b CE |
16169 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
16170 | * brightness value | |
4dca20ef CE |
16171 | */ |
16172 | static void quirk_invert_brightness(struct drm_device *dev) | |
16173 | { | |
fac5e23e | 16174 | struct drm_i915_private *dev_priv = to_i915(dev); |
4dca20ef | 16175 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; |
bc0daf48 | 16176 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
16177 | } |
16178 | ||
9c72cc6f SD |
16179 | /* Some VBT's incorrectly indicate no backlight is present */ |
16180 | static void quirk_backlight_present(struct drm_device *dev) | |
16181 | { | |
fac5e23e | 16182 | struct drm_i915_private *dev_priv = to_i915(dev); |
9c72cc6f SD |
16183 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; |
16184 | DRM_INFO("applying backlight present quirk\n"); | |
16185 | } | |
16186 | ||
b690e96c JB |
16187 | struct intel_quirk { |
16188 | int device; | |
16189 | int subsystem_vendor; | |
16190 | int subsystem_device; | |
16191 | void (*hook)(struct drm_device *dev); | |
16192 | }; | |
16193 | ||
5f85f176 EE |
16194 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
16195 | struct intel_dmi_quirk { | |
16196 | void (*hook)(struct drm_device *dev); | |
16197 | const struct dmi_system_id (*dmi_id_list)[]; | |
16198 | }; | |
16199 | ||
16200 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
16201 | { | |
16202 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
16203 | return 1; | |
16204 | } | |
16205 | ||
16206 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
16207 | { | |
16208 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
16209 | { | |
16210 | .callback = intel_dmi_reverse_brightness, | |
16211 | .ident = "NCR Corporation", | |
16212 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
16213 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
16214 | }, | |
16215 | }, | |
16216 | { } /* terminating entry */ | |
16217 | }, | |
16218 | .hook = quirk_invert_brightness, | |
16219 | }, | |
16220 | }; | |
16221 | ||
c43b5634 | 16222 | static struct intel_quirk intel_quirks[] = { |
b690e96c JB |
16223 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
16224 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
16225 | ||
b690e96c JB |
16226 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
16227 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
16228 | ||
5f080c0f VS |
16229 | /* 830 needs to leave pipe A & dpll A up */ |
16230 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
16231 | ||
b6b5d049 VS |
16232 | /* 830 needs to leave pipe B & dpll B up */ |
16233 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
16234 | ||
435793df KP |
16235 | /* Lenovo U160 cannot use SSC on LVDS */ |
16236 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
16237 | |
16238 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
16239 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 16240 | |
be505f64 AH |
16241 | /* Acer Aspire 5734Z must invert backlight brightness */ |
16242 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
16243 | ||
16244 | /* Acer/eMachines G725 */ | |
16245 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
16246 | ||
16247 | /* Acer/eMachines e725 */ | |
16248 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
16249 | ||
16250 | /* Acer/Packard Bell NCL20 */ | |
16251 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
16252 | ||
16253 | /* Acer Aspire 4736Z */ | |
16254 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
16255 | |
16256 | /* Acer Aspire 5336 */ | |
16257 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
16258 | |
16259 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
16260 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 16261 | |
dfb3d47b SD |
16262 | /* Acer C720 Chromebook (Core i3 4005U) */ |
16263 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
16264 | ||
b2a9601c | 16265 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
16266 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
16267 | ||
1b9448b0 JN |
16268 | /* Apple Macbook 4,1 */ |
16269 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, | |
16270 | ||
d4967d8c SD |
16271 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
16272 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
16273 | |
16274 | /* HP Chromebook 14 (Celeron 2955U) */ | |
16275 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
16276 | |
16277 | /* Dell Chromebook 11 */ | |
16278 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
9be64eee JN |
16279 | |
16280 | /* Dell Chromebook 11 (2015 version) */ | |
16281 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
16282 | }; |
16283 | ||
16284 | static void intel_init_quirks(struct drm_device *dev) | |
16285 | { | |
16286 | struct pci_dev *d = dev->pdev; | |
16287 | int i; | |
16288 | ||
16289 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
16290 | struct intel_quirk *q = &intel_quirks[i]; | |
16291 | ||
16292 | if (d->device == q->device && | |
16293 | (d->subsystem_vendor == q->subsystem_vendor || | |
16294 | q->subsystem_vendor == PCI_ANY_ID) && | |
16295 | (d->subsystem_device == q->subsystem_device || | |
16296 | q->subsystem_device == PCI_ANY_ID)) | |
16297 | q->hook(dev); | |
16298 | } | |
5f85f176 EE |
16299 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
16300 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
16301 | intel_dmi_quirks[i].hook(dev); | |
16302 | } | |
b690e96c JB |
16303 | } |
16304 | ||
9cce37f4 JB |
16305 | /* Disable the VGA plane that we never use */ |
16306 | static void i915_disable_vga(struct drm_device *dev) | |
16307 | { | |
fac5e23e | 16308 | struct drm_i915_private *dev_priv = to_i915(dev); |
52a05c30 | 16309 | struct pci_dev *pdev = dev_priv->drm.pdev; |
9cce37f4 | 16310 | u8 sr1; |
920a14b2 | 16311 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv); |
9cce37f4 | 16312 | |
2b37c616 | 16313 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
52a05c30 | 16314 | vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 16315 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
16316 | sr1 = inb(VGA_SR_DATA); |
16317 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
52a05c30 | 16318 | vga_put(pdev, VGA_RSRC_LEGACY_IO); |
9cce37f4 JB |
16319 | udelay(300); |
16320 | ||
01f5a626 | 16321 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
16322 | POSTING_READ(vga_reg); |
16323 | } | |
16324 | ||
f817586c DV |
16325 | void intel_modeset_init_hw(struct drm_device *dev) |
16326 | { | |
fac5e23e | 16327 | struct drm_i915_private *dev_priv = to_i915(dev); |
1a617b77 | 16328 | |
b6283055 | 16329 | intel_update_cdclk(dev); |
1a617b77 ML |
16330 | |
16331 | dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq; | |
16332 | ||
f817586c | 16333 | intel_init_clock_gating(dev); |
f817586c DV |
16334 | } |
16335 | ||
d93c0372 MR |
16336 | /* |
16337 | * Calculate what we think the watermarks should be for the state we've read | |
16338 | * out of the hardware and then immediately program those watermarks so that | |
16339 | * we ensure the hardware settings match our internal state. | |
16340 | * | |
16341 | * We can calculate what we think WM's should be by creating a duplicate of the | |
16342 | * current state (which was constructed during hardware readout) and running it | |
16343 | * through the atomic check code to calculate new watermark values in the | |
16344 | * state object. | |
16345 | */ | |
16346 | static void sanitize_watermarks(struct drm_device *dev) | |
16347 | { | |
16348 | struct drm_i915_private *dev_priv = to_i915(dev); | |
16349 | struct drm_atomic_state *state; | |
16350 | struct drm_crtc *crtc; | |
16351 | struct drm_crtc_state *cstate; | |
16352 | struct drm_modeset_acquire_ctx ctx; | |
16353 | int ret; | |
16354 | int i; | |
16355 | ||
16356 | /* Only supported on platforms that use atomic watermark design */ | |
ed4a6a7c | 16357 | if (!dev_priv->display.optimize_watermarks) |
d93c0372 MR |
16358 | return; |
16359 | ||
16360 | /* | |
16361 | * We need to hold connection_mutex before calling duplicate_state so | |
16362 | * that the connector loop is protected. | |
16363 | */ | |
16364 | drm_modeset_acquire_init(&ctx, 0); | |
16365 | retry: | |
0cd1262d | 16366 | ret = drm_modeset_lock_all_ctx(dev, &ctx); |
d93c0372 MR |
16367 | if (ret == -EDEADLK) { |
16368 | drm_modeset_backoff(&ctx); | |
16369 | goto retry; | |
16370 | } else if (WARN_ON(ret)) { | |
0cd1262d | 16371 | goto fail; |
d93c0372 MR |
16372 | } |
16373 | ||
16374 | state = drm_atomic_helper_duplicate_state(dev, &ctx); | |
16375 | if (WARN_ON(IS_ERR(state))) | |
0cd1262d | 16376 | goto fail; |
d93c0372 | 16377 | |
ed4a6a7c MR |
16378 | /* |
16379 | * Hardware readout is the only time we don't want to calculate | |
16380 | * intermediate watermarks (since we don't trust the current | |
16381 | * watermarks). | |
16382 | */ | |
16383 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
16384 | ||
d93c0372 MR |
16385 | ret = intel_atomic_check(dev, state); |
16386 | if (ret) { | |
16387 | /* | |
16388 | * If we fail here, it means that the hardware appears to be | |
16389 | * programmed in a way that shouldn't be possible, given our | |
16390 | * understanding of watermark requirements. This might mean a | |
16391 | * mistake in the hardware readout code or a mistake in the | |
16392 | * watermark calculations for a given platform. Raise a WARN | |
16393 | * so that this is noticeable. | |
16394 | * | |
16395 | * If this actually happens, we'll have to just leave the | |
16396 | * BIOS-programmed watermarks untouched and hope for the best. | |
16397 | */ | |
16398 | WARN(true, "Could not determine valid watermarks for inherited state\n"); | |
b9a1b717 | 16399 | goto put_state; |
d93c0372 MR |
16400 | } |
16401 | ||
16402 | /* Write calculated watermark values back */ | |
d93c0372 MR |
16403 | for_each_crtc_in_state(state, crtc, cstate, i) { |
16404 | struct intel_crtc_state *cs = to_intel_crtc_state(cstate); | |
16405 | ||
ed4a6a7c MR |
16406 | cs->wm.need_postvbl_update = true; |
16407 | dev_priv->display.optimize_watermarks(cs); | |
d93c0372 MR |
16408 | } |
16409 | ||
b9a1b717 | 16410 | put_state: |
0853695c | 16411 | drm_atomic_state_put(state); |
0cd1262d | 16412 | fail: |
d93c0372 MR |
16413 | drm_modeset_drop_locks(&ctx); |
16414 | drm_modeset_acquire_fini(&ctx); | |
16415 | } | |
16416 | ||
b079bd17 | 16417 | int intel_modeset_init(struct drm_device *dev) |
79e53945 | 16418 | { |
72e96d64 JL |
16419 | struct drm_i915_private *dev_priv = to_i915(dev); |
16420 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
8cc87b75 | 16421 | enum pipe pipe; |
46f297fb | 16422 | struct intel_crtc *crtc; |
79e53945 JB |
16423 | |
16424 | drm_mode_config_init(dev); | |
16425 | ||
16426 | dev->mode_config.min_width = 0; | |
16427 | dev->mode_config.min_height = 0; | |
16428 | ||
019d96cb DA |
16429 | dev->mode_config.preferred_depth = 24; |
16430 | dev->mode_config.prefer_shadow = 1; | |
16431 | ||
25bab385 TU |
16432 | dev->mode_config.allow_fb_modifiers = true; |
16433 | ||
e6ecefaa | 16434 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 16435 | |
b690e96c JB |
16436 | intel_init_quirks(dev); |
16437 | ||
1fa61106 ED |
16438 | intel_init_pm(dev); |
16439 | ||
e3c74757 | 16440 | if (INTEL_INFO(dev)->num_pipes == 0) |
b079bd17 | 16441 | return 0; |
e3c74757 | 16442 | |
69f92f67 LW |
16443 | /* |
16444 | * There may be no VBT; and if the BIOS enabled SSC we can | |
16445 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
16446 | * BIOS isn't using it, don't assume it will work even if the VBT | |
16447 | * indicates as much. | |
16448 | */ | |
6e266956 | 16449 | if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { |
69f92f67 LW |
16450 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & |
16451 | DREF_SSC1_ENABLE); | |
16452 | ||
16453 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
16454 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
16455 | bios_lvds_use_ssc ? "en" : "dis", | |
16456 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
16457 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
16458 | } | |
16459 | } | |
16460 | ||
5db94019 | 16461 | if (IS_GEN2(dev_priv)) { |
a6c45cf0 CW |
16462 | dev->mode_config.max_width = 2048; |
16463 | dev->mode_config.max_height = 2048; | |
5db94019 | 16464 | } else if (IS_GEN3(dev_priv)) { |
5e4d6fa7 KP |
16465 | dev->mode_config.max_width = 4096; |
16466 | dev->mode_config.max_height = 4096; | |
79e53945 | 16467 | } else { |
a6c45cf0 CW |
16468 | dev->mode_config.max_width = 8192; |
16469 | dev->mode_config.max_height = 8192; | |
79e53945 | 16470 | } |
068be561 | 16471 | |
50a0bc90 TU |
16472 | if (IS_845G(dev_priv) || IS_I865G(dev_priv)) { |
16473 | dev->mode_config.cursor_width = IS_845G(dev_priv) ? 64 : 512; | |
dc41c154 | 16474 | dev->mode_config.cursor_height = 1023; |
5db94019 | 16475 | } else if (IS_GEN2(dev_priv)) { |
068be561 DL |
16476 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
16477 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
16478 | } else { | |
16479 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
16480 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
16481 | } | |
16482 | ||
72e96d64 | 16483 | dev->mode_config.fb_base = ggtt->mappable_base; |
79e53945 | 16484 | |
28c97730 | 16485 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
16486 | INTEL_INFO(dev)->num_pipes, |
16487 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 16488 | |
055e393f | 16489 | for_each_pipe(dev_priv, pipe) { |
b079bd17 VS |
16490 | int ret; |
16491 | ||
16492 | ret = intel_crtc_init(dev, pipe); | |
16493 | if (ret) { | |
16494 | drm_mode_config_cleanup(dev); | |
16495 | return ret; | |
16496 | } | |
79e53945 JB |
16497 | } |
16498 | ||
bfa7df01 VS |
16499 | intel_update_czclk(dev_priv); |
16500 | intel_update_cdclk(dev); | |
16501 | ||
e72f9fbf | 16502 | intel_shared_dpll_init(dev); |
ee7b9f93 | 16503 | |
b2045352 VS |
16504 | if (dev_priv->max_cdclk_freq == 0) |
16505 | intel_update_max_cdclk(dev); | |
16506 | ||
9cce37f4 JB |
16507 | /* Just disable it once at startup */ |
16508 | i915_disable_vga(dev); | |
79e53945 | 16509 | intel_setup_outputs(dev); |
11be49eb | 16510 | |
6e9f798d | 16511 | drm_modeset_lock_all(dev); |
043e9bda | 16512 | intel_modeset_setup_hw_state(dev); |
6e9f798d | 16513 | drm_modeset_unlock_all(dev); |
46f297fb | 16514 | |
d3fcc808 | 16515 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
16516 | struct intel_initial_plane_config plane_config = {}; |
16517 | ||
46f297fb JB |
16518 | if (!crtc->active) |
16519 | continue; | |
16520 | ||
46f297fb | 16521 | /* |
46f297fb JB |
16522 | * Note that reserving the BIOS fb up front prevents us |
16523 | * from stuffing other stolen allocations like the ring | |
16524 | * on top. This prevents some ugliness at boot time, and | |
16525 | * can even allow for smooth boot transitions if the BIOS | |
16526 | * fb is large enough for the active pipe configuration. | |
16527 | */ | |
eeebeac5 ML |
16528 | dev_priv->display.get_initial_plane_config(crtc, |
16529 | &plane_config); | |
16530 | ||
16531 | /* | |
16532 | * If the fb is shared between multiple heads, we'll | |
16533 | * just get the first one. | |
16534 | */ | |
16535 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 16536 | } |
d93c0372 MR |
16537 | |
16538 | /* | |
16539 | * Make sure hardware watermarks really match the state we read out. | |
16540 | * Note that we need to do this after reconstructing the BIOS fb's | |
16541 | * since the watermark calculation done here will use pstate->fb. | |
16542 | */ | |
16543 | sanitize_watermarks(dev); | |
b079bd17 VS |
16544 | |
16545 | return 0; | |
2c7111db CW |
16546 | } |
16547 | ||
7fad798e DV |
16548 | static void intel_enable_pipe_a(struct drm_device *dev) |
16549 | { | |
16550 | struct intel_connector *connector; | |
16551 | struct drm_connector *crt = NULL; | |
16552 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 16553 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
16554 | |
16555 | /* We can't just switch on the pipe A, we need to set things up with a | |
16556 | * proper mode and output configuration. As a gross hack, enable pipe A | |
16557 | * by enabling the load detect pipe once. */ | |
3a3371ff | 16558 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
16559 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
16560 | crt = &connector->base; | |
16561 | break; | |
16562 | } | |
16563 | } | |
16564 | ||
16565 | if (!crt) | |
16566 | return; | |
16567 | ||
208bf9fd | 16568 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 16569 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
16570 | } |
16571 | ||
fa555837 DV |
16572 | static bool |
16573 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
16574 | { | |
7eb552ae | 16575 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 16576 | struct drm_i915_private *dev_priv = to_i915(dev); |
649636ef | 16577 | u32 val; |
fa555837 | 16578 | |
7eb552ae | 16579 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
16580 | return true; |
16581 | ||
649636ef | 16582 | val = I915_READ(DSPCNTR(!crtc->plane)); |
fa555837 DV |
16583 | |
16584 | if ((val & DISPLAY_PLANE_ENABLE) && | |
16585 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
16586 | return false; | |
16587 | ||
16588 | return true; | |
16589 | } | |
16590 | ||
02e93c35 VS |
16591 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
16592 | { | |
16593 | struct drm_device *dev = crtc->base.dev; | |
16594 | struct intel_encoder *encoder; | |
16595 | ||
16596 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
16597 | return true; | |
16598 | ||
16599 | return false; | |
16600 | } | |
16601 | ||
496b0fc3 ML |
16602 | static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder) |
16603 | { | |
16604 | struct drm_device *dev = encoder->base.dev; | |
16605 | struct intel_connector *connector; | |
16606 | ||
16607 | for_each_connector_on_encoder(dev, &encoder->base, connector) | |
16608 | return connector; | |
16609 | ||
16610 | return NULL; | |
16611 | } | |
16612 | ||
a168f5b3 VS |
16613 | static bool has_pch_trancoder(struct drm_i915_private *dev_priv, |
16614 | enum transcoder pch_transcoder) | |
16615 | { | |
16616 | return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) || | |
16617 | (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A); | |
16618 | } | |
16619 | ||
24929352 DV |
16620 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
16621 | { | |
16622 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 16623 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 | 16624 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
24929352 | 16625 | |
24929352 | 16626 | /* Clear any frame start delays used for debugging left by the BIOS */ |
4d1de975 JN |
16627 | if (!transcoder_is_dsi(cpu_transcoder)) { |
16628 | i915_reg_t reg = PIPECONF(cpu_transcoder); | |
16629 | ||
16630 | I915_WRITE(reg, | |
16631 | I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); | |
16632 | } | |
24929352 | 16633 | |
d3eaf884 | 16634 | /* restore vblank interrupts to correct state */ |
9625604c | 16635 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 16636 | if (crtc->active) { |
f9cd7b88 VS |
16637 | struct intel_plane *plane; |
16638 | ||
9625604c | 16639 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
16640 | |
16641 | /* Disable everything but the primary plane */ | |
16642 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
16643 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
16644 | continue; | |
16645 | ||
16646 | plane->disable_plane(&plane->base, &crtc->base); | |
16647 | } | |
9625604c | 16648 | } |
d3eaf884 | 16649 | |
24929352 | 16650 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
16651 | * disable the crtc (and hence change the state) if it is wrong. Note |
16652 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
16653 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
16654 | bool plane; |
16655 | ||
78108b7c VS |
16656 | DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n", |
16657 | crtc->base.base.id, crtc->base.name); | |
24929352 DV |
16658 | |
16659 | /* Pipe has the wrong plane attached and the plane is active. | |
16660 | * Temporarily change the plane mapping and disable everything | |
16661 | * ... */ | |
16662 | plane = crtc->plane; | |
936e71e3 | 16663 | to_intel_plane_state(crtc->base.primary->state)->base.visible = true; |
24929352 | 16664 | crtc->plane = !plane; |
b17d48e2 | 16665 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 16666 | crtc->plane = plane; |
24929352 | 16667 | } |
24929352 | 16668 | |
7fad798e DV |
16669 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
16670 | crtc->pipe == PIPE_A && !crtc->active) { | |
16671 | /* BIOS forgot to enable pipe A, this mostly happens after | |
16672 | * resume. Force-enable the pipe to fix this, the update_dpms | |
16673 | * call below we restore the pipe to the right state, but leave | |
16674 | * the required bits on. */ | |
16675 | intel_enable_pipe_a(dev); | |
16676 | } | |
16677 | ||
24929352 DV |
16678 | /* Adjust the state of the output pipe according to whether we |
16679 | * have active connectors/encoders. */ | |
842e0307 | 16680 | if (crtc->active && !intel_crtc_has_encoders(crtc)) |
b17d48e2 | 16681 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 16682 | |
49cff963 | 16683 | if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) { |
4cc31489 DV |
16684 | /* |
16685 | * We start out with underrun reporting disabled to avoid races. | |
16686 | * For correct bookkeeping mark this on active crtcs. | |
16687 | * | |
c5ab3bc0 DV |
16688 | * Also on gmch platforms we dont have any hardware bits to |
16689 | * disable the underrun reporting. Which means we need to start | |
16690 | * out with underrun reporting disabled also on inactive pipes, | |
16691 | * since otherwise we'll complain about the garbage we read when | |
16692 | * e.g. coming up after runtime pm. | |
16693 | * | |
4cc31489 DV |
16694 | * No protection against concurrent access is required - at |
16695 | * worst a fifo underrun happens which also sets this to false. | |
16696 | */ | |
16697 | crtc->cpu_fifo_underrun_disabled = true; | |
a168f5b3 VS |
16698 | /* |
16699 | * We track the PCH trancoder underrun reporting state | |
16700 | * within the crtc. With crtc for pipe A housing the underrun | |
16701 | * reporting state for PCH transcoder A, crtc for pipe B housing | |
16702 | * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A, | |
16703 | * and marking underrun reporting as disabled for the non-existing | |
16704 | * PCH transcoders B and C would prevent enabling the south | |
16705 | * error interrupt (see cpt_can_enable_serr_int()). | |
16706 | */ | |
16707 | if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe)) | |
16708 | crtc->pch_fifo_underrun_disabled = true; | |
4cc31489 | 16709 | } |
24929352 DV |
16710 | } |
16711 | ||
16712 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
16713 | { | |
16714 | struct intel_connector *connector; | |
24929352 DV |
16715 | |
16716 | /* We need to check both for a crtc link (meaning that the | |
16717 | * encoder is active and trying to read from a pipe) and the | |
16718 | * pipe itself being active. */ | |
16719 | bool has_active_crtc = encoder->base.crtc && | |
16720 | to_intel_crtc(encoder->base.crtc)->active; | |
16721 | ||
496b0fc3 ML |
16722 | connector = intel_encoder_find_connector(encoder); |
16723 | if (connector && !has_active_crtc) { | |
24929352 DV |
16724 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
16725 | encoder->base.base.id, | |
8e329a03 | 16726 | encoder->base.name); |
24929352 DV |
16727 | |
16728 | /* Connector is active, but has no active pipe. This is | |
16729 | * fallout from our resume register restoring. Disable | |
16730 | * the encoder manually again. */ | |
16731 | if (encoder->base.crtc) { | |
fd6bbda9 ML |
16732 | struct drm_crtc_state *crtc_state = encoder->base.crtc->state; |
16733 | ||
24929352 DV |
16734 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", |
16735 | encoder->base.base.id, | |
8e329a03 | 16736 | encoder->base.name); |
fd6bbda9 | 16737 | encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state); |
a62d1497 | 16738 | if (encoder->post_disable) |
fd6bbda9 | 16739 | encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state); |
24929352 | 16740 | } |
7f1950fb | 16741 | encoder->base.crtc = NULL; |
24929352 DV |
16742 | |
16743 | /* Inconsistent output/port/pipe state happens presumably due to | |
16744 | * a bug in one of the get_hw_state functions. Or someplace else | |
16745 | * in our code, like the register restore mess on resume. Clamp | |
16746 | * things to off as a safer default. */ | |
fd6bbda9 ML |
16747 | |
16748 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
16749 | connector->base.encoder = NULL; | |
24929352 DV |
16750 | } |
16751 | /* Enabled encoders without active connectors will be fixed in | |
16752 | * the crtc fixup. */ | |
16753 | } | |
16754 | ||
04098753 | 16755 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f | 16756 | { |
fac5e23e | 16757 | struct drm_i915_private *dev_priv = to_i915(dev); |
920a14b2 | 16758 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv); |
0fde901f | 16759 | |
04098753 ID |
16760 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
16761 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
16762 | i915_disable_vga(dev); | |
16763 | } | |
16764 | } | |
16765 | ||
16766 | void i915_redisable_vga(struct drm_device *dev) | |
16767 | { | |
fac5e23e | 16768 | struct drm_i915_private *dev_priv = to_i915(dev); |
04098753 | 16769 | |
8dc8a27c PZ |
16770 | /* This function can be called both from intel_modeset_setup_hw_state or |
16771 | * at a very early point in our resume sequence, where the power well | |
16772 | * structures are not yet restored. Since this function is at a very | |
16773 | * paranoid "someone might have enabled VGA while we were not looking" | |
16774 | * level, just check if the power well is enabled instead of trying to | |
16775 | * follow the "don't touch the power well if we don't need it" policy | |
16776 | * the rest of the driver uses. */ | |
6392f847 | 16777 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
16778 | return; |
16779 | ||
04098753 | 16780 | i915_redisable_vga_power_on(dev); |
6392f847 ID |
16781 | |
16782 | intel_display_power_put(dev_priv, POWER_DOMAIN_VGA); | |
0fde901f KM |
16783 | } |
16784 | ||
f9cd7b88 | 16785 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 16786 | { |
f9cd7b88 | 16787 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 16788 | |
f9cd7b88 | 16789 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
16790 | } |
16791 | ||
f9cd7b88 VS |
16792 | /* FIXME read out full plane state for all planes */ |
16793 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 16794 | { |
b26d3ea3 | 16795 | struct drm_plane *primary = crtc->base.primary; |
f9cd7b88 | 16796 | struct intel_plane_state *plane_state = |
b26d3ea3 | 16797 | to_intel_plane_state(primary->state); |
d032ffa0 | 16798 | |
936e71e3 | 16799 | plane_state->base.visible = crtc->active && |
b26d3ea3 ML |
16800 | primary_get_hw_state(to_intel_plane(primary)); |
16801 | ||
936e71e3 | 16802 | if (plane_state->base.visible) |
b26d3ea3 | 16803 | crtc->base.state->plane_mask |= 1 << drm_plane_index(primary); |
98ec7739 VS |
16804 | } |
16805 | ||
30e984df | 16806 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 | 16807 | { |
fac5e23e | 16808 | struct drm_i915_private *dev_priv = to_i915(dev); |
24929352 | 16809 | enum pipe pipe; |
24929352 DV |
16810 | struct intel_crtc *crtc; |
16811 | struct intel_encoder *encoder; | |
16812 | struct intel_connector *connector; | |
5358901f | 16813 | int i; |
24929352 | 16814 | |
565602d7 ML |
16815 | dev_priv->active_crtcs = 0; |
16816 | ||
d3fcc808 | 16817 | for_each_intel_crtc(dev, crtc) { |
565602d7 ML |
16818 | struct intel_crtc_state *crtc_state = crtc->config; |
16819 | int pixclk = 0; | |
3b117c8f | 16820 | |
ec2dc6a0 | 16821 | __drm_atomic_helper_crtc_destroy_state(&crtc_state->base); |
565602d7 ML |
16822 | memset(crtc_state, 0, sizeof(*crtc_state)); |
16823 | crtc_state->base.crtc = &crtc->base; | |
24929352 | 16824 | |
565602d7 ML |
16825 | crtc_state->base.active = crtc_state->base.enable = |
16826 | dev_priv->display.get_pipe_config(crtc, crtc_state); | |
16827 | ||
16828 | crtc->base.enabled = crtc_state->base.enable; | |
16829 | crtc->active = crtc_state->base.active; | |
16830 | ||
16831 | if (crtc_state->base.active) { | |
16832 | dev_priv->active_crtcs |= 1 << crtc->pipe; | |
16833 | ||
c89e39f3 | 16834 | if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) |
565602d7 | 16835 | pixclk = ilk_pipe_pixel_rate(crtc_state); |
9558d15d | 16836 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
565602d7 ML |
16837 | pixclk = crtc_state->base.adjusted_mode.crtc_clock; |
16838 | else | |
16839 | WARN_ON(dev_priv->display.modeset_calc_cdclk); | |
9558d15d VS |
16840 | |
16841 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
16842 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) | |
16843 | pixclk = DIV_ROUND_UP(pixclk * 100, 95); | |
565602d7 ML |
16844 | } |
16845 | ||
16846 | dev_priv->min_pixclk[crtc->pipe] = pixclk; | |
b70709a6 | 16847 | |
f9cd7b88 | 16848 | readout_plane_state(crtc); |
24929352 | 16849 | |
78108b7c VS |
16850 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n", |
16851 | crtc->base.base.id, crtc->base.name, | |
24929352 DV |
16852 | crtc->active ? "enabled" : "disabled"); |
16853 | } | |
16854 | ||
5358901f DV |
16855 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
16856 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
16857 | ||
2edd6443 ACO |
16858 | pll->on = pll->funcs.get_hw_state(dev_priv, pll, |
16859 | &pll->config.hw_state); | |
3e369b76 | 16860 | pll->config.crtc_mask = 0; |
d3fcc808 | 16861 | for_each_intel_crtc(dev, crtc) { |
2dd66ebd | 16862 | if (crtc->active && crtc->config->shared_dpll == pll) |
3e369b76 | 16863 | pll->config.crtc_mask |= 1 << crtc->pipe; |
5358901f | 16864 | } |
2dd66ebd | 16865 | pll->active_mask = pll->config.crtc_mask; |
5358901f | 16866 | |
1e6f2ddc | 16867 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 16868 | pll->name, pll->config.crtc_mask, pll->on); |
5358901f DV |
16869 | } |
16870 | ||
b2784e15 | 16871 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
16872 | pipe = 0; |
16873 | ||
16874 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
16875 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
16876 | encoder->base.crtc = &crtc->base; | |
253c84c8 | 16877 | crtc->config->output_types |= 1 << encoder->type; |
6e3c9717 | 16878 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
16879 | } else { |
16880 | encoder->base.crtc = NULL; | |
16881 | } | |
16882 | ||
6f2bcceb | 16883 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 16884 | encoder->base.base.id, |
8e329a03 | 16885 | encoder->base.name, |
24929352 | 16886 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 16887 | pipe_name(pipe)); |
24929352 DV |
16888 | } |
16889 | ||
3a3371ff | 16890 | for_each_intel_connector(dev, connector) { |
24929352 DV |
16891 | if (connector->get_hw_state(connector)) { |
16892 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
2aa974c9 ML |
16893 | |
16894 | encoder = connector->encoder; | |
16895 | connector->base.encoder = &encoder->base; | |
16896 | ||
16897 | if (encoder->base.crtc && | |
16898 | encoder->base.crtc->state->active) { | |
16899 | /* | |
16900 | * This has to be done during hardware readout | |
16901 | * because anything calling .crtc_disable may | |
16902 | * rely on the connector_mask being accurate. | |
16903 | */ | |
16904 | encoder->base.crtc->state->connector_mask |= | |
16905 | 1 << drm_connector_index(&connector->base); | |
e87a52b3 ML |
16906 | encoder->base.crtc->state->encoder_mask |= |
16907 | 1 << drm_encoder_index(&encoder->base); | |
2aa974c9 ML |
16908 | } |
16909 | ||
24929352 DV |
16910 | } else { |
16911 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
16912 | connector->base.encoder = NULL; | |
16913 | } | |
16914 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
16915 | connector->base.base.id, | |
c23cc417 | 16916 | connector->base.name, |
24929352 DV |
16917 | connector->base.encoder ? "enabled" : "disabled"); |
16918 | } | |
7f4c6284 VS |
16919 | |
16920 | for_each_intel_crtc(dev, crtc) { | |
16921 | crtc->base.hwmode = crtc->config->base.adjusted_mode; | |
16922 | ||
16923 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); | |
16924 | if (crtc->base.state->active) { | |
16925 | intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); | |
16926 | intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config); | |
16927 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); | |
16928 | ||
16929 | /* | |
16930 | * The initial mode needs to be set in order to keep | |
16931 | * the atomic core happy. It wants a valid mode if the | |
16932 | * crtc's enabled, so we do the above call. | |
16933 | * | |
16934 | * At this point some state updated by the connectors | |
16935 | * in their ->detect() callback has not run yet, so | |
16936 | * no recalculation can be done yet. | |
16937 | * | |
16938 | * Even if we could do a recalculation and modeset | |
16939 | * right now it would cause a double modeset if | |
16940 | * fbdev or userspace chooses a different initial mode. | |
16941 | * | |
16942 | * If that happens, someone indicated they wanted a | |
16943 | * mode change, which means it's safe to do a full | |
16944 | * recalculation. | |
16945 | */ | |
16946 | crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED; | |
9eca6832 VS |
16947 | |
16948 | drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); | |
16949 | update_scanline_offset(crtc); | |
7f4c6284 | 16950 | } |
e3b247da VS |
16951 | |
16952 | intel_pipe_config_sanity_check(dev_priv, crtc->config); | |
7f4c6284 | 16953 | } |
30e984df DV |
16954 | } |
16955 | ||
043e9bda ML |
16956 | /* Scan out the current hw modeset state, |
16957 | * and sanitizes it to the current state | |
16958 | */ | |
16959 | static void | |
16960 | intel_modeset_setup_hw_state(struct drm_device *dev) | |
30e984df | 16961 | { |
fac5e23e | 16962 | struct drm_i915_private *dev_priv = to_i915(dev); |
30e984df | 16963 | enum pipe pipe; |
30e984df DV |
16964 | struct intel_crtc *crtc; |
16965 | struct intel_encoder *encoder; | |
35c95375 | 16966 | int i; |
30e984df DV |
16967 | |
16968 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
16969 | |
16970 | /* HW state is read out, now we need to sanitize this mess. */ | |
b2784e15 | 16971 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
16972 | intel_sanitize_encoder(encoder); |
16973 | } | |
16974 | ||
055e393f | 16975 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
16976 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
16977 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
16978 | intel_dump_pipe_config(crtc, crtc->config, |
16979 | "[setup_hw_state]"); | |
24929352 | 16980 | } |
9a935856 | 16981 | |
d29b2f9d ACO |
16982 | intel_modeset_update_connector_atomic_state(dev); |
16983 | ||
35c95375 DV |
16984 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
16985 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
16986 | ||
2dd66ebd | 16987 | if (!pll->on || pll->active_mask) |
35c95375 DV |
16988 | continue; |
16989 | ||
16990 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
16991 | ||
2edd6443 | 16992 | pll->funcs.disable(dev_priv, pll); |
35c95375 DV |
16993 | pll->on = false; |
16994 | } | |
16995 | ||
920a14b2 | 16996 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
6eb1a681 | 16997 | vlv_wm_get_hw_state(dev); |
5db94019 | 16998 | else if (IS_GEN9(dev_priv)) |
3078999f | 16999 | skl_wm_get_hw_state(dev); |
6e266956 | 17000 | else if (HAS_PCH_SPLIT(dev_priv)) |
243e6a44 | 17001 | ilk_wm_get_hw_state(dev); |
292b990e ML |
17002 | |
17003 | for_each_intel_crtc(dev, crtc) { | |
17004 | unsigned long put_domains; | |
17005 | ||
74bff5f9 | 17006 | put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config); |
292b990e ML |
17007 | if (WARN_ON(put_domains)) |
17008 | modeset_put_power_domains(dev_priv, put_domains); | |
17009 | } | |
17010 | intel_display_set_init_power(dev_priv, false); | |
010cf73d PZ |
17011 | |
17012 | intel_fbc_init_pipe_state(dev_priv); | |
043e9bda | 17013 | } |
7d0bc1ea | 17014 | |
043e9bda ML |
17015 | void intel_display_resume(struct drm_device *dev) |
17016 | { | |
e2c8b870 ML |
17017 | struct drm_i915_private *dev_priv = to_i915(dev); |
17018 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
17019 | struct drm_modeset_acquire_ctx ctx; | |
043e9bda | 17020 | int ret; |
f30da187 | 17021 | |
e2c8b870 | 17022 | dev_priv->modeset_restore_state = NULL; |
73974893 ML |
17023 | if (state) |
17024 | state->acquire_ctx = &ctx; | |
043e9bda | 17025 | |
ea49c9ac ML |
17026 | /* |
17027 | * This is a cludge because with real atomic modeset mode_config.mutex | |
17028 | * won't be taken. Unfortunately some probed state like | |
17029 | * audio_codec_enable is still protected by mode_config.mutex, so lock | |
17030 | * it here for now. | |
17031 | */ | |
17032 | mutex_lock(&dev->mode_config.mutex); | |
e2c8b870 | 17033 | drm_modeset_acquire_init(&ctx, 0); |
043e9bda | 17034 | |
73974893 ML |
17035 | while (1) { |
17036 | ret = drm_modeset_lock_all_ctx(dev, &ctx); | |
17037 | if (ret != -EDEADLK) | |
17038 | break; | |
043e9bda | 17039 | |
e2c8b870 | 17040 | drm_modeset_backoff(&ctx); |
e2c8b870 | 17041 | } |
043e9bda | 17042 | |
73974893 ML |
17043 | if (!ret) |
17044 | ret = __intel_display_resume(dev, state); | |
17045 | ||
e2c8b870 ML |
17046 | drm_modeset_drop_locks(&ctx); |
17047 | drm_modeset_acquire_fini(&ctx); | |
ea49c9ac | 17048 | mutex_unlock(&dev->mode_config.mutex); |
043e9bda | 17049 | |
0853695c | 17050 | if (ret) |
e2c8b870 | 17051 | DRM_ERROR("Restoring old state failed with %i\n", ret); |
0853695c | 17052 | drm_atomic_state_put(state); |
2c7111db CW |
17053 | } |
17054 | ||
17055 | void intel_modeset_gem_init(struct drm_device *dev) | |
17056 | { | |
dc97997a | 17057 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd | 17058 | struct drm_crtc *c; |
2ff8fde1 | 17059 | struct drm_i915_gem_object *obj; |
484b41dd | 17060 | |
dc97997a | 17061 | intel_init_gt_powersave(dev_priv); |
ae48434c | 17062 | |
1833b134 | 17063 | intel_modeset_init_hw(dev); |
02e792fb | 17064 | |
1ee8da6d | 17065 | intel_setup_overlay(dev_priv); |
484b41dd JB |
17066 | |
17067 | /* | |
17068 | * Make sure any fbs we allocated at startup are properly | |
17069 | * pinned & fenced. When we do the allocation it's too early | |
17070 | * for this. | |
17071 | */ | |
70e1e0ec | 17072 | for_each_crtc(dev, c) { |
058d88c4 CW |
17073 | struct i915_vma *vma; |
17074 | ||
2ff8fde1 MR |
17075 | obj = intel_fb_obj(c->primary->fb); |
17076 | if (obj == NULL) | |
484b41dd JB |
17077 | continue; |
17078 | ||
e0d6149b | 17079 | mutex_lock(&dev->struct_mutex); |
058d88c4 | 17080 | vma = intel_pin_and_fence_fb_obj(c->primary->fb, |
3465c580 | 17081 | c->primary->state->rotation); |
e0d6149b | 17082 | mutex_unlock(&dev->struct_mutex); |
058d88c4 | 17083 | if (IS_ERR(vma)) { |
484b41dd JB |
17084 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
17085 | to_intel_crtc(c)->pipe); | |
66e514c1 | 17086 | drm_framebuffer_unreference(c->primary->fb); |
5a21b665 | 17087 | c->primary->fb = NULL; |
36750f28 | 17088 | c->primary->crtc = c->primary->state->crtc = NULL; |
5a21b665 | 17089 | update_state_fb(c->primary); |
36750f28 | 17090 | c->state->plane_mask &= ~(1 << drm_plane_index(c->primary)); |
484b41dd JB |
17091 | } |
17092 | } | |
1ebaa0b9 CW |
17093 | } |
17094 | ||
17095 | int intel_connector_register(struct drm_connector *connector) | |
17096 | { | |
17097 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
17098 | int ret; | |
17099 | ||
17100 | ret = intel_backlight_device_register(intel_connector); | |
17101 | if (ret) | |
17102 | goto err; | |
17103 | ||
17104 | return 0; | |
0962c3c9 | 17105 | |
1ebaa0b9 CW |
17106 | err: |
17107 | return ret; | |
79e53945 JB |
17108 | } |
17109 | ||
c191eca1 | 17110 | void intel_connector_unregister(struct drm_connector *connector) |
4932e2c3 | 17111 | { |
e63d87c0 | 17112 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4932e2c3 | 17113 | |
e63d87c0 | 17114 | intel_backlight_device_unregister(intel_connector); |
4932e2c3 | 17115 | intel_panel_destroy_backlight(connector); |
4932e2c3 ID |
17116 | } |
17117 | ||
79e53945 JB |
17118 | void intel_modeset_cleanup(struct drm_device *dev) |
17119 | { | |
fac5e23e | 17120 | struct drm_i915_private *dev_priv = to_i915(dev); |
652c393a | 17121 | |
dc97997a | 17122 | intel_disable_gt_powersave(dev_priv); |
2eb5252e | 17123 | |
fd0c0642 DV |
17124 | /* |
17125 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 17126 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
17127 | * experience fancy races otherwise. |
17128 | */ | |
2aeb7d3a | 17129 | intel_irq_uninstall(dev_priv); |
eb21b92b | 17130 | |
fd0c0642 DV |
17131 | /* |
17132 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
17133 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
17134 | */ | |
f87ea761 | 17135 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 17136 | |
723bfd70 JB |
17137 | intel_unregister_dsm_handler(); |
17138 | ||
c937ab3e | 17139 | intel_fbc_global_disable(dev_priv); |
69341a5e | 17140 | |
1630fe75 CW |
17141 | /* flush any delayed tasks or pending work */ |
17142 | flush_scheduled_work(); | |
17143 | ||
79e53945 | 17144 | drm_mode_config_cleanup(dev); |
4d7bb011 | 17145 | |
1ee8da6d | 17146 | intel_cleanup_overlay(dev_priv); |
ae48434c | 17147 | |
dc97997a | 17148 | intel_cleanup_gt_powersave(dev_priv); |
f5949141 DV |
17149 | |
17150 | intel_teardown_gmbus(dev); | |
79e53945 JB |
17151 | } |
17152 | ||
df0e9248 CW |
17153 | void intel_connector_attach_encoder(struct intel_connector *connector, |
17154 | struct intel_encoder *encoder) | |
17155 | { | |
17156 | connector->encoder = encoder; | |
17157 | drm_mode_connector_attach_encoder(&connector->base, | |
17158 | &encoder->base); | |
79e53945 | 17159 | } |
28d52043 DA |
17160 | |
17161 | /* | |
17162 | * set vga decode state - true == enable VGA decode | |
17163 | */ | |
17164 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
17165 | { | |
fac5e23e | 17166 | struct drm_i915_private *dev_priv = to_i915(dev); |
a885b3cc | 17167 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
17168 | u16 gmch_ctrl; |
17169 | ||
75fa041d CW |
17170 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
17171 | DRM_ERROR("failed to read control word\n"); | |
17172 | return -EIO; | |
17173 | } | |
17174 | ||
c0cc8a55 CW |
17175 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
17176 | return 0; | |
17177 | ||
28d52043 DA |
17178 | if (state) |
17179 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
17180 | else | |
17181 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
17182 | |
17183 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
17184 | DRM_ERROR("failed to write control word\n"); | |
17185 | return -EIO; | |
17186 | } | |
17187 | ||
28d52043 DA |
17188 | return 0; |
17189 | } | |
c4a1d9e4 | 17190 | |
98a2f411 CW |
17191 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
17192 | ||
c4a1d9e4 | 17193 | struct intel_display_error_state { |
ff57f1b0 PZ |
17194 | |
17195 | u32 power_well_driver; | |
17196 | ||
63b66e5b CW |
17197 | int num_transcoders; |
17198 | ||
c4a1d9e4 CW |
17199 | struct intel_cursor_error_state { |
17200 | u32 control; | |
17201 | u32 position; | |
17202 | u32 base; | |
17203 | u32 size; | |
52331309 | 17204 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
17205 | |
17206 | struct intel_pipe_error_state { | |
ddf9c536 | 17207 | bool power_domain_on; |
c4a1d9e4 | 17208 | u32 source; |
f301b1e1 | 17209 | u32 stat; |
52331309 | 17210 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
17211 | |
17212 | struct intel_plane_error_state { | |
17213 | u32 control; | |
17214 | u32 stride; | |
17215 | u32 size; | |
17216 | u32 pos; | |
17217 | u32 addr; | |
17218 | u32 surface; | |
17219 | u32 tile_offset; | |
52331309 | 17220 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
17221 | |
17222 | struct intel_transcoder_error_state { | |
ddf9c536 | 17223 | bool power_domain_on; |
63b66e5b CW |
17224 | enum transcoder cpu_transcoder; |
17225 | ||
17226 | u32 conf; | |
17227 | ||
17228 | u32 htotal; | |
17229 | u32 hblank; | |
17230 | u32 hsync; | |
17231 | u32 vtotal; | |
17232 | u32 vblank; | |
17233 | u32 vsync; | |
17234 | } transcoder[4]; | |
c4a1d9e4 CW |
17235 | }; |
17236 | ||
17237 | struct intel_display_error_state * | |
c033666a | 17238 | intel_display_capture_error_state(struct drm_i915_private *dev_priv) |
c4a1d9e4 | 17239 | { |
c4a1d9e4 | 17240 | struct intel_display_error_state *error; |
63b66e5b CW |
17241 | int transcoders[] = { |
17242 | TRANSCODER_A, | |
17243 | TRANSCODER_B, | |
17244 | TRANSCODER_C, | |
17245 | TRANSCODER_EDP, | |
17246 | }; | |
c4a1d9e4 CW |
17247 | int i; |
17248 | ||
c033666a | 17249 | if (INTEL_INFO(dev_priv)->num_pipes == 0) |
63b66e5b CW |
17250 | return NULL; |
17251 | ||
9d1cb914 | 17252 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
17253 | if (error == NULL) |
17254 | return NULL; | |
17255 | ||
c033666a | 17256 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
ff57f1b0 PZ |
17257 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
17258 | ||
055e393f | 17259 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 17260 | error->pipe[i].power_domain_on = |
f458ebbc DV |
17261 | __intel_display_power_is_enabled(dev_priv, |
17262 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 17263 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
17264 | continue; |
17265 | ||
5efb3e28 VS |
17266 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
17267 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
17268 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
17269 | |
17270 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
17271 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
c033666a | 17272 | if (INTEL_GEN(dev_priv) <= 3) { |
51889b35 | 17273 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
17274 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
17275 | } | |
c033666a | 17276 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
ca291363 | 17277 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
c033666a | 17278 | if (INTEL_GEN(dev_priv) >= 4) { |
c4a1d9e4 CW |
17279 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
17280 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
17281 | } | |
17282 | ||
c4a1d9e4 | 17283 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 17284 | |
c033666a | 17285 | if (HAS_GMCH_DISPLAY(dev_priv)) |
f301b1e1 | 17286 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
17287 | } |
17288 | ||
4d1de975 | 17289 | /* Note: this does not include DSI transcoders. */ |
c033666a | 17290 | error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes; |
2d1fe073 | 17291 | if (HAS_DDI(dev_priv)) |
63b66e5b CW |
17292 | error->num_transcoders++; /* Account for eDP. */ |
17293 | ||
17294 | for (i = 0; i < error->num_transcoders; i++) { | |
17295 | enum transcoder cpu_transcoder = transcoders[i]; | |
17296 | ||
ddf9c536 | 17297 | error->transcoder[i].power_domain_on = |
f458ebbc | 17298 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 17299 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 17300 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
17301 | continue; |
17302 | ||
63b66e5b CW |
17303 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
17304 | ||
17305 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
17306 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
17307 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
17308 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
17309 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
17310 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
17311 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
17312 | } |
17313 | ||
17314 | return error; | |
17315 | } | |
17316 | ||
edc3d884 MK |
17317 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
17318 | ||
c4a1d9e4 | 17319 | void |
edc3d884 | 17320 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
17321 | struct drm_device *dev, |
17322 | struct intel_display_error_state *error) | |
17323 | { | |
fac5e23e | 17324 | struct drm_i915_private *dev_priv = to_i915(dev); |
c4a1d9e4 CW |
17325 | int i; |
17326 | ||
63b66e5b CW |
17327 | if (!error) |
17328 | return; | |
17329 | ||
edc3d884 | 17330 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
8652744b | 17331 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
edc3d884 | 17332 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 17333 | error->power_well_driver); |
055e393f | 17334 | for_each_pipe(dev_priv, i) { |
edc3d884 | 17335 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 | 17336 | err_printf(m, " Power: %s\n", |
87ad3212 | 17337 | onoff(error->pipe[i].power_domain_on)); |
edc3d884 | 17338 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 17339 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
17340 | |
17341 | err_printf(m, "Plane [%d]:\n", i); | |
17342 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
17343 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 17344 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
17345 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
17346 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 17347 | } |
772c2a51 | 17348 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
edc3d884 | 17349 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 17350 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
17351 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
17352 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
17353 | } |
17354 | ||
edc3d884 MK |
17355 | err_printf(m, "Cursor [%d]:\n", i); |
17356 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
17357 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
17358 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 17359 | } |
63b66e5b CW |
17360 | |
17361 | for (i = 0; i < error->num_transcoders; i++) { | |
da205630 | 17362 | err_printf(m, "CPU transcoder: %s\n", |
63b66e5b | 17363 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 | 17364 | err_printf(m, " Power: %s\n", |
87ad3212 | 17365 | onoff(error->transcoder[i].power_domain_on)); |
63b66e5b CW |
17366 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
17367 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
17368 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
17369 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
17370 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
17371 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
17372 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
17373 | } | |
c4a1d9e4 | 17374 | } |
98a2f411 CW |
17375 | |
17376 | #endif |