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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
319c1d42 | 40 | #include <drm/drm_atomic.h> |
c196e1d6 | 41 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
42 | #include <drm/drm_dp_helper.h> |
43 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
44 | #include <drm/drm_plane_helper.h> |
45 | #include <drm/drm_rect.h> | |
c0f372b3 | 46 | #include <linux/dma_remapping.h> |
79e53945 | 47 | |
465c120c | 48 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 49 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
50 | DRM_FORMAT_C8, |
51 | DRM_FORMAT_RGB565, | |
465c120c | 52 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 53 | DRM_FORMAT_XRGB8888, |
465c120c MR |
54 | }; |
55 | ||
56 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 57 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
58 | DRM_FORMAT_C8, |
59 | DRM_FORMAT_RGB565, | |
60 | DRM_FORMAT_XRGB8888, | |
61 | DRM_FORMAT_XBGR8888, | |
62 | DRM_FORMAT_XRGB2101010, | |
63 | DRM_FORMAT_XBGR2101010, | |
64 | }; | |
65 | ||
66 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
67 | DRM_FORMAT_C8, |
68 | DRM_FORMAT_RGB565, | |
69 | DRM_FORMAT_XRGB8888, | |
465c120c | 70 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 71 | DRM_FORMAT_ARGB8888, |
465c120c MR |
72 | DRM_FORMAT_ABGR8888, |
73 | DRM_FORMAT_XRGB2101010, | |
465c120c | 74 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
75 | DRM_FORMAT_YUYV, |
76 | DRM_FORMAT_YVYU, | |
77 | DRM_FORMAT_UYVY, | |
78 | DRM_FORMAT_VYUY, | |
465c120c MR |
79 | }; |
80 | ||
3d7d6510 MR |
81 | /* Cursor formats */ |
82 | static const uint32_t intel_cursor_formats[] = { | |
83 | DRM_FORMAT_ARGB8888, | |
84 | }; | |
85 | ||
6b383a7f | 86 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 87 | |
f1f644dc | 88 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 89 | struct intel_crtc_state *pipe_config); |
18442d08 | 90 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 91 | struct intel_crtc_state *pipe_config); |
f1f644dc | 92 | |
eb1bfe80 JB |
93 | static int intel_framebuffer_init(struct drm_device *dev, |
94 | struct intel_framebuffer *ifb, | |
95 | struct drm_mode_fb_cmd2 *mode_cmd, | |
96 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
97 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
98 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
29407aab | 99 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
100 | struct intel_link_m_n *m_n, |
101 | struct intel_link_m_n *m2_n2); | |
29407aab | 102 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 DV |
103 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
104 | static void intel_set_pipe_csc(struct drm_crtc *crtc); | |
d288f65f | 105 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 106 | const struct intel_crtc_state *pipe_config); |
d288f65f | 107 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 108 | const struct intel_crtc_state *pipe_config); |
613d2b27 ML |
109 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
110 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
549e2bfb CK |
111 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
112 | struct intel_crtc_state *crtc_state); | |
5ab7b0b7 ID |
113 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
114 | int num_connectors); | |
bfd16b2a ML |
115 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
116 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
117 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
043e9bda | 118 | static void intel_modeset_setup_hw_state(struct drm_device *dev); |
e7457a9a | 119 | |
79e53945 | 120 | typedef struct { |
0206e353 | 121 | int min, max; |
79e53945 JB |
122 | } intel_range_t; |
123 | ||
124 | typedef struct { | |
0206e353 AJ |
125 | int dot_limit; |
126 | int p2_slow, p2_fast; | |
79e53945 JB |
127 | } intel_p2_t; |
128 | ||
d4906093 ML |
129 | typedef struct intel_limit intel_limit_t; |
130 | struct intel_limit { | |
0206e353 AJ |
131 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
132 | intel_p2_t p2; | |
d4906093 | 133 | }; |
79e53945 | 134 | |
d2acd215 DV |
135 | int |
136 | intel_pch_rawclk(struct drm_device *dev) | |
137 | { | |
138 | struct drm_i915_private *dev_priv = dev->dev_private; | |
139 | ||
140 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
141 | ||
142 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
143 | } | |
144 | ||
79e50a4f JN |
145 | /* hrawclock is 1/4 the FSB frequency */ |
146 | int intel_hrawclk(struct drm_device *dev) | |
147 | { | |
148 | struct drm_i915_private *dev_priv = dev->dev_private; | |
149 | uint32_t clkcfg; | |
150 | ||
151 | /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ | |
152 | if (IS_VALLEYVIEW(dev)) | |
153 | return 200; | |
154 | ||
155 | clkcfg = I915_READ(CLKCFG); | |
156 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
157 | case CLKCFG_FSB_400: | |
158 | return 100; | |
159 | case CLKCFG_FSB_533: | |
160 | return 133; | |
161 | case CLKCFG_FSB_667: | |
162 | return 166; | |
163 | case CLKCFG_FSB_800: | |
164 | return 200; | |
165 | case CLKCFG_FSB_1067: | |
166 | return 266; | |
167 | case CLKCFG_FSB_1333: | |
168 | return 333; | |
169 | /* these two are just a guess; one of them might be right */ | |
170 | case CLKCFG_FSB_1600: | |
171 | case CLKCFG_FSB_1600_ALT: | |
172 | return 400; | |
173 | default: | |
174 | return 133; | |
175 | } | |
176 | } | |
177 | ||
021357ac CW |
178 | static inline u32 /* units of 100MHz */ |
179 | intel_fdi_link_freq(struct drm_device *dev) | |
180 | { | |
8b99e68c CW |
181 | if (IS_GEN5(dev)) { |
182 | struct drm_i915_private *dev_priv = dev->dev_private; | |
183 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
184 | } else | |
185 | return 27; | |
021357ac CW |
186 | } |
187 | ||
5d536e28 | 188 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 189 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 190 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 191 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
192 | .m = { .min = 96, .max = 140 }, |
193 | .m1 = { .min = 18, .max = 26 }, | |
194 | .m2 = { .min = 6, .max = 16 }, | |
195 | .p = { .min = 4, .max = 128 }, | |
196 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
197 | .p2 = { .dot_limit = 165000, |
198 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
199 | }; |
200 | ||
5d536e28 DV |
201 | static const intel_limit_t intel_limits_i8xx_dvo = { |
202 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 203 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 204 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
205 | .m = { .min = 96, .max = 140 }, |
206 | .m1 = { .min = 18, .max = 26 }, | |
207 | .m2 = { .min = 6, .max = 16 }, | |
208 | .p = { .min = 4, .max = 128 }, | |
209 | .p1 = { .min = 2, .max = 33 }, | |
210 | .p2 = { .dot_limit = 165000, | |
211 | .p2_slow = 4, .p2_fast = 4 }, | |
212 | }; | |
213 | ||
e4b36699 | 214 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 215 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 216 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 217 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
218 | .m = { .min = 96, .max = 140 }, |
219 | .m1 = { .min = 18, .max = 26 }, | |
220 | .m2 = { .min = 6, .max = 16 }, | |
221 | .p = { .min = 4, .max = 128 }, | |
222 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
223 | .p2 = { .dot_limit = 165000, |
224 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 225 | }; |
273e27ca | 226 | |
e4b36699 | 227 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
228 | .dot = { .min = 20000, .max = 400000 }, |
229 | .vco = { .min = 1400000, .max = 2800000 }, | |
230 | .n = { .min = 1, .max = 6 }, | |
231 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
232 | .m1 = { .min = 8, .max = 18 }, |
233 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
234 | .p = { .min = 5, .max = 80 }, |
235 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
236 | .p2 = { .dot_limit = 200000, |
237 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
238 | }; |
239 | ||
240 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
241 | .dot = { .min = 20000, .max = 400000 }, |
242 | .vco = { .min = 1400000, .max = 2800000 }, | |
243 | .n = { .min = 1, .max = 6 }, | |
244 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
245 | .m1 = { .min = 8, .max = 18 }, |
246 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
247 | .p = { .min = 7, .max = 98 }, |
248 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
249 | .p2 = { .dot_limit = 112000, |
250 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
251 | }; |
252 | ||
273e27ca | 253 | |
e4b36699 | 254 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
255 | .dot = { .min = 25000, .max = 270000 }, |
256 | .vco = { .min = 1750000, .max = 3500000}, | |
257 | .n = { .min = 1, .max = 4 }, | |
258 | .m = { .min = 104, .max = 138 }, | |
259 | .m1 = { .min = 17, .max = 23 }, | |
260 | .m2 = { .min = 5, .max = 11 }, | |
261 | .p = { .min = 10, .max = 30 }, | |
262 | .p1 = { .min = 1, .max = 3}, | |
263 | .p2 = { .dot_limit = 270000, | |
264 | .p2_slow = 10, | |
265 | .p2_fast = 10 | |
044c7c41 | 266 | }, |
e4b36699 KP |
267 | }; |
268 | ||
269 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
270 | .dot = { .min = 22000, .max = 400000 }, |
271 | .vco = { .min = 1750000, .max = 3500000}, | |
272 | .n = { .min = 1, .max = 4 }, | |
273 | .m = { .min = 104, .max = 138 }, | |
274 | .m1 = { .min = 16, .max = 23 }, | |
275 | .m2 = { .min = 5, .max = 11 }, | |
276 | .p = { .min = 5, .max = 80 }, | |
277 | .p1 = { .min = 1, .max = 8}, | |
278 | .p2 = { .dot_limit = 165000, | |
279 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
280 | }; |
281 | ||
282 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
283 | .dot = { .min = 20000, .max = 115000 }, |
284 | .vco = { .min = 1750000, .max = 3500000 }, | |
285 | .n = { .min = 1, .max = 3 }, | |
286 | .m = { .min = 104, .max = 138 }, | |
287 | .m1 = { .min = 17, .max = 23 }, | |
288 | .m2 = { .min = 5, .max = 11 }, | |
289 | .p = { .min = 28, .max = 112 }, | |
290 | .p1 = { .min = 2, .max = 8 }, | |
291 | .p2 = { .dot_limit = 0, | |
292 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 293 | }, |
e4b36699 KP |
294 | }; |
295 | ||
296 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
297 | .dot = { .min = 80000, .max = 224000 }, |
298 | .vco = { .min = 1750000, .max = 3500000 }, | |
299 | .n = { .min = 1, .max = 3 }, | |
300 | .m = { .min = 104, .max = 138 }, | |
301 | .m1 = { .min = 17, .max = 23 }, | |
302 | .m2 = { .min = 5, .max = 11 }, | |
303 | .p = { .min = 14, .max = 42 }, | |
304 | .p1 = { .min = 2, .max = 6 }, | |
305 | .p2 = { .dot_limit = 0, | |
306 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 307 | }, |
e4b36699 KP |
308 | }; |
309 | ||
f2b115e6 | 310 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
311 | .dot = { .min = 20000, .max = 400000}, |
312 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 313 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
314 | .n = { .min = 3, .max = 6 }, |
315 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 316 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
317 | .m1 = { .min = 0, .max = 0 }, |
318 | .m2 = { .min = 0, .max = 254 }, | |
319 | .p = { .min = 5, .max = 80 }, | |
320 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
321 | .p2 = { .dot_limit = 200000, |
322 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
323 | }; |
324 | ||
f2b115e6 | 325 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
326 | .dot = { .min = 20000, .max = 400000 }, |
327 | .vco = { .min = 1700000, .max = 3500000 }, | |
328 | .n = { .min = 3, .max = 6 }, | |
329 | .m = { .min = 2, .max = 256 }, | |
330 | .m1 = { .min = 0, .max = 0 }, | |
331 | .m2 = { .min = 0, .max = 254 }, | |
332 | .p = { .min = 7, .max = 112 }, | |
333 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
334 | .p2 = { .dot_limit = 112000, |
335 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
336 | }; |
337 | ||
273e27ca EA |
338 | /* Ironlake / Sandybridge |
339 | * | |
340 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
341 | * the range value for them is (actual_value - 2). | |
342 | */ | |
b91ad0ec | 343 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
344 | .dot = { .min = 25000, .max = 350000 }, |
345 | .vco = { .min = 1760000, .max = 3510000 }, | |
346 | .n = { .min = 1, .max = 5 }, | |
347 | .m = { .min = 79, .max = 127 }, | |
348 | .m1 = { .min = 12, .max = 22 }, | |
349 | .m2 = { .min = 5, .max = 9 }, | |
350 | .p = { .min = 5, .max = 80 }, | |
351 | .p1 = { .min = 1, .max = 8 }, | |
352 | .p2 = { .dot_limit = 225000, | |
353 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
354 | }; |
355 | ||
b91ad0ec | 356 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
357 | .dot = { .min = 25000, .max = 350000 }, |
358 | .vco = { .min = 1760000, .max = 3510000 }, | |
359 | .n = { .min = 1, .max = 3 }, | |
360 | .m = { .min = 79, .max = 118 }, | |
361 | .m1 = { .min = 12, .max = 22 }, | |
362 | .m2 = { .min = 5, .max = 9 }, | |
363 | .p = { .min = 28, .max = 112 }, | |
364 | .p1 = { .min = 2, .max = 8 }, | |
365 | .p2 = { .dot_limit = 225000, | |
366 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
367 | }; |
368 | ||
369 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
370 | .dot = { .min = 25000, .max = 350000 }, |
371 | .vco = { .min = 1760000, .max = 3510000 }, | |
372 | .n = { .min = 1, .max = 3 }, | |
373 | .m = { .min = 79, .max = 127 }, | |
374 | .m1 = { .min = 12, .max = 22 }, | |
375 | .m2 = { .min = 5, .max = 9 }, | |
376 | .p = { .min = 14, .max = 56 }, | |
377 | .p1 = { .min = 2, .max = 8 }, | |
378 | .p2 = { .dot_limit = 225000, | |
379 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
380 | }; |
381 | ||
273e27ca | 382 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 383 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
384 | .dot = { .min = 25000, .max = 350000 }, |
385 | .vco = { .min = 1760000, .max = 3510000 }, | |
386 | .n = { .min = 1, .max = 2 }, | |
387 | .m = { .min = 79, .max = 126 }, | |
388 | .m1 = { .min = 12, .max = 22 }, | |
389 | .m2 = { .min = 5, .max = 9 }, | |
390 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 391 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
392 | .p2 = { .dot_limit = 225000, |
393 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
394 | }; |
395 | ||
396 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
397 | .dot = { .min = 25000, .max = 350000 }, |
398 | .vco = { .min = 1760000, .max = 3510000 }, | |
399 | .n = { .min = 1, .max = 3 }, | |
400 | .m = { .min = 79, .max = 126 }, | |
401 | .m1 = { .min = 12, .max = 22 }, | |
402 | .m2 = { .min = 5, .max = 9 }, | |
403 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 404 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
405 | .p2 = { .dot_limit = 225000, |
406 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
407 | }; |
408 | ||
dc730512 | 409 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
410 | /* |
411 | * These are the data rate limits (measured in fast clocks) | |
412 | * since those are the strictest limits we have. The fast | |
413 | * clock and actual rate limits are more relaxed, so checking | |
414 | * them would make no difference. | |
415 | */ | |
416 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 417 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 418 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
419 | .m1 = { .min = 2, .max = 3 }, |
420 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 421 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 422 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
423 | }; |
424 | ||
ef9348c8 CML |
425 | static const intel_limit_t intel_limits_chv = { |
426 | /* | |
427 | * These are the data rate limits (measured in fast clocks) | |
428 | * since those are the strictest limits we have. The fast | |
429 | * clock and actual rate limits are more relaxed, so checking | |
430 | * them would make no difference. | |
431 | */ | |
432 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 433 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
434 | .n = { .min = 1, .max = 1 }, |
435 | .m1 = { .min = 2, .max = 2 }, | |
436 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
437 | .p1 = { .min = 2, .max = 4 }, | |
438 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
439 | }; | |
440 | ||
5ab7b0b7 ID |
441 | static const intel_limit_t intel_limits_bxt = { |
442 | /* FIXME: find real dot limits */ | |
443 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 444 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
445 | .n = { .min = 1, .max = 1 }, |
446 | .m1 = { .min = 2, .max = 2 }, | |
447 | /* FIXME: find real m2 limits */ | |
448 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
449 | .p1 = { .min = 2, .max = 4 }, | |
450 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
451 | }; | |
452 | ||
cdba954e ACO |
453 | static bool |
454 | needs_modeset(struct drm_crtc_state *state) | |
455 | { | |
fc596660 | 456 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
457 | } |
458 | ||
e0638cdf PZ |
459 | /** |
460 | * Returns whether any output on the specified pipe is of the specified type | |
461 | */ | |
4093561b | 462 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) |
e0638cdf | 463 | { |
409ee761 | 464 | struct drm_device *dev = crtc->base.dev; |
e0638cdf PZ |
465 | struct intel_encoder *encoder; |
466 | ||
409ee761 | 467 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
e0638cdf PZ |
468 | if (encoder->type == type) |
469 | return true; | |
470 | ||
471 | return false; | |
472 | } | |
473 | ||
d0737e1d ACO |
474 | /** |
475 | * Returns whether any output on the specified pipe will have the specified | |
476 | * type after a staged modeset is complete, i.e., the same as | |
477 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of | |
478 | * encoder->crtc. | |
479 | */ | |
a93e255f ACO |
480 | static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state, |
481 | int type) | |
d0737e1d | 482 | { |
a93e255f | 483 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 484 | struct drm_connector *connector; |
a93e255f | 485 | struct drm_connector_state *connector_state; |
d0737e1d | 486 | struct intel_encoder *encoder; |
a93e255f ACO |
487 | int i, num_connectors = 0; |
488 | ||
da3ced29 | 489 | for_each_connector_in_state(state, connector, connector_state, i) { |
a93e255f ACO |
490 | if (connector_state->crtc != crtc_state->base.crtc) |
491 | continue; | |
492 | ||
493 | num_connectors++; | |
d0737e1d | 494 | |
a93e255f ACO |
495 | encoder = to_intel_encoder(connector_state->best_encoder); |
496 | if (encoder->type == type) | |
d0737e1d | 497 | return true; |
a93e255f ACO |
498 | } |
499 | ||
500 | WARN_ON(num_connectors == 0); | |
d0737e1d ACO |
501 | |
502 | return false; | |
503 | } | |
504 | ||
a93e255f ACO |
505 | static const intel_limit_t * |
506 | intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk) | |
2c07245f | 507 | { |
a93e255f | 508 | struct drm_device *dev = crtc_state->base.crtc->dev; |
2c07245f | 509 | const intel_limit_t *limit; |
b91ad0ec | 510 | |
a93e255f | 511 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 512 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 513 | if (refclk == 100000) |
b91ad0ec ZW |
514 | limit = &intel_limits_ironlake_dual_lvds_100m; |
515 | else | |
516 | limit = &intel_limits_ironlake_dual_lvds; | |
517 | } else { | |
1b894b59 | 518 | if (refclk == 100000) |
b91ad0ec ZW |
519 | limit = &intel_limits_ironlake_single_lvds_100m; |
520 | else | |
521 | limit = &intel_limits_ironlake_single_lvds; | |
522 | } | |
c6bb3538 | 523 | } else |
b91ad0ec | 524 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
525 | |
526 | return limit; | |
527 | } | |
528 | ||
a93e255f ACO |
529 | static const intel_limit_t * |
530 | intel_g4x_limit(struct intel_crtc_state *crtc_state) | |
044c7c41 | 531 | { |
a93e255f | 532 | struct drm_device *dev = crtc_state->base.crtc->dev; |
044c7c41 ML |
533 | const intel_limit_t *limit; |
534 | ||
a93e255f | 535 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 536 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 537 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 538 | else |
e4b36699 | 539 | limit = &intel_limits_g4x_single_channel_lvds; |
a93e255f ACO |
540 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) || |
541 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 542 | limit = &intel_limits_g4x_hdmi; |
a93e255f | 543 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 544 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 545 | } else /* The option is for other outputs */ |
e4b36699 | 546 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
547 | |
548 | return limit; | |
549 | } | |
550 | ||
a93e255f ACO |
551 | static const intel_limit_t * |
552 | intel_limit(struct intel_crtc_state *crtc_state, int refclk) | |
79e53945 | 553 | { |
a93e255f | 554 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 JB |
555 | const intel_limit_t *limit; |
556 | ||
5ab7b0b7 ID |
557 | if (IS_BROXTON(dev)) |
558 | limit = &intel_limits_bxt; | |
559 | else if (HAS_PCH_SPLIT(dev)) | |
a93e255f | 560 | limit = intel_ironlake_limit(crtc_state, refclk); |
2c07245f | 561 | else if (IS_G4X(dev)) { |
a93e255f | 562 | limit = intel_g4x_limit(crtc_state); |
f2b115e6 | 563 | } else if (IS_PINEVIEW(dev)) { |
a93e255f | 564 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 565 | limit = &intel_limits_pineview_lvds; |
2177832f | 566 | else |
f2b115e6 | 567 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
568 | } else if (IS_CHERRYVIEW(dev)) { |
569 | limit = &intel_limits_chv; | |
a0c4da24 | 570 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 571 | limit = &intel_limits_vlv; |
a6c45cf0 | 572 | } else if (!IS_GEN2(dev)) { |
a93e255f | 573 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a6c45cf0 CW |
574 | limit = &intel_limits_i9xx_lvds; |
575 | else | |
576 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 | 577 | } else { |
a93e255f | 578 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
e4b36699 | 579 | limit = &intel_limits_i8xx_lvds; |
a93e255f | 580 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
e4b36699 | 581 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
582 | else |
583 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
584 | } |
585 | return limit; | |
586 | } | |
587 | ||
dccbea3b ID |
588 | /* |
589 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
590 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
591 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
592 | * The helpers' return value is the rate of the clock that is fed to the | |
593 | * display engine's pipe which can be the above fast dot clock rate or a | |
594 | * divided-down version of it. | |
595 | */ | |
f2b115e6 | 596 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
dccbea3b | 597 | static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock) |
79e53945 | 598 | { |
2177832f SL |
599 | clock->m = clock->m2 + 2; |
600 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 601 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 602 | return 0; |
fb03ac01 VS |
603 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
604 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
605 | |
606 | return clock->dot; | |
2177832f SL |
607 | } |
608 | ||
7429e9d4 DV |
609 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
610 | { | |
611 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
612 | } | |
613 | ||
dccbea3b | 614 | static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock) |
2177832f | 615 | { |
7429e9d4 | 616 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 617 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 618 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 619 | return 0; |
fb03ac01 VS |
620 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
621 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
622 | |
623 | return clock->dot; | |
79e53945 JB |
624 | } |
625 | ||
dccbea3b | 626 | static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock) |
589eca67 ID |
627 | { |
628 | clock->m = clock->m1 * clock->m2; | |
629 | clock->p = clock->p1 * clock->p2; | |
630 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 631 | return 0; |
589eca67 ID |
632 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
633 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
634 | |
635 | return clock->dot / 5; | |
589eca67 ID |
636 | } |
637 | ||
dccbea3b | 638 | int chv_calc_dpll_params(int refclk, intel_clock_t *clock) |
ef9348c8 CML |
639 | { |
640 | clock->m = clock->m1 * clock->m2; | |
641 | clock->p = clock->p1 * clock->p2; | |
642 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 643 | return 0; |
ef9348c8 CML |
644 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
645 | clock->n << 22); | |
646 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
647 | |
648 | return clock->dot / 5; | |
ef9348c8 CML |
649 | } |
650 | ||
7c04d1d9 | 651 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
652 | /** |
653 | * Returns whether the given set of divisors are valid for a given refclk with | |
654 | * the given connectors. | |
655 | */ | |
656 | ||
1b894b59 CW |
657 | static bool intel_PLL_is_valid(struct drm_device *dev, |
658 | const intel_limit_t *limit, | |
659 | const intel_clock_t *clock) | |
79e53945 | 660 | { |
f01b7962 VS |
661 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
662 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 663 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 664 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 665 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 666 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 667 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 668 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 669 | |
5ab7b0b7 | 670 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) |
f01b7962 VS |
671 | if (clock->m1 <= clock->m2) |
672 | INTELPllInvalid("m1 <= m2\n"); | |
673 | ||
5ab7b0b7 | 674 | if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) { |
f01b7962 VS |
675 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
676 | INTELPllInvalid("p out of range\n"); | |
677 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
678 | INTELPllInvalid("m out of range\n"); | |
679 | } | |
680 | ||
79e53945 | 681 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 682 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
683 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
684 | * connector, etc., rather than just a single range. | |
685 | */ | |
686 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 687 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
688 | |
689 | return true; | |
690 | } | |
691 | ||
3b1429d9 VS |
692 | static int |
693 | i9xx_select_p2_div(const intel_limit_t *limit, | |
694 | const struct intel_crtc_state *crtc_state, | |
695 | int target) | |
79e53945 | 696 | { |
3b1429d9 | 697 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 698 | |
a93e255f | 699 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 700 | /* |
a210b028 DV |
701 | * For LVDS just rely on its current settings for dual-channel. |
702 | * We haven't figured out how to reliably set up different | |
703 | * single/dual channel state, if we even can. | |
79e53945 | 704 | */ |
1974cad0 | 705 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 706 | return limit->p2.p2_fast; |
79e53945 | 707 | else |
3b1429d9 | 708 | return limit->p2.p2_slow; |
79e53945 JB |
709 | } else { |
710 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 711 | return limit->p2.p2_slow; |
79e53945 | 712 | else |
3b1429d9 | 713 | return limit->p2.p2_fast; |
79e53945 | 714 | } |
3b1429d9 VS |
715 | } |
716 | ||
717 | static bool | |
718 | i9xx_find_best_dpll(const intel_limit_t *limit, | |
719 | struct intel_crtc_state *crtc_state, | |
720 | int target, int refclk, intel_clock_t *match_clock, | |
721 | intel_clock_t *best_clock) | |
722 | { | |
723 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
724 | intel_clock_t clock; | |
725 | int err = target; | |
79e53945 | 726 | |
0206e353 | 727 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 728 | |
3b1429d9 VS |
729 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
730 | ||
42158660 ZY |
731 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
732 | clock.m1++) { | |
733 | for (clock.m2 = limit->m2.min; | |
734 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 735 | if (clock.m2 >= clock.m1) |
42158660 ZY |
736 | break; |
737 | for (clock.n = limit->n.min; | |
738 | clock.n <= limit->n.max; clock.n++) { | |
739 | for (clock.p1 = limit->p1.min; | |
740 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
741 | int this_err; |
742 | ||
dccbea3b | 743 | i9xx_calc_dpll_params(refclk, &clock); |
ac58c3f0 DV |
744 | if (!intel_PLL_is_valid(dev, limit, |
745 | &clock)) | |
746 | continue; | |
747 | if (match_clock && | |
748 | clock.p != match_clock->p) | |
749 | continue; | |
750 | ||
751 | this_err = abs(clock.dot - target); | |
752 | if (this_err < err) { | |
753 | *best_clock = clock; | |
754 | err = this_err; | |
755 | } | |
756 | } | |
757 | } | |
758 | } | |
759 | } | |
760 | ||
761 | return (err != target); | |
762 | } | |
763 | ||
764 | static bool | |
a93e255f ACO |
765 | pnv_find_best_dpll(const intel_limit_t *limit, |
766 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
767 | int target, int refclk, intel_clock_t *match_clock, |
768 | intel_clock_t *best_clock) | |
79e53945 | 769 | { |
3b1429d9 | 770 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 771 | intel_clock_t clock; |
79e53945 JB |
772 | int err = target; |
773 | ||
0206e353 | 774 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 775 | |
3b1429d9 VS |
776 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
777 | ||
42158660 ZY |
778 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
779 | clock.m1++) { | |
780 | for (clock.m2 = limit->m2.min; | |
781 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
782 | for (clock.n = limit->n.min; |
783 | clock.n <= limit->n.max; clock.n++) { | |
784 | for (clock.p1 = limit->p1.min; | |
785 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
786 | int this_err; |
787 | ||
dccbea3b | 788 | pnv_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
789 | if (!intel_PLL_is_valid(dev, limit, |
790 | &clock)) | |
79e53945 | 791 | continue; |
cec2f356 SP |
792 | if (match_clock && |
793 | clock.p != match_clock->p) | |
794 | continue; | |
79e53945 JB |
795 | |
796 | this_err = abs(clock.dot - target); | |
797 | if (this_err < err) { | |
798 | *best_clock = clock; | |
799 | err = this_err; | |
800 | } | |
801 | } | |
802 | } | |
803 | } | |
804 | } | |
805 | ||
806 | return (err != target); | |
807 | } | |
808 | ||
d4906093 | 809 | static bool |
a93e255f ACO |
810 | g4x_find_best_dpll(const intel_limit_t *limit, |
811 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
812 | int target, int refclk, intel_clock_t *match_clock, |
813 | intel_clock_t *best_clock) | |
d4906093 | 814 | { |
3b1429d9 | 815 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d4906093 ML |
816 | intel_clock_t clock; |
817 | int max_n; | |
3b1429d9 | 818 | bool found = false; |
6ba770dc AJ |
819 | /* approximately equals target * 0.00585 */ |
820 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
821 | |
822 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
823 | |
824 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
825 | ||
d4906093 | 826 | max_n = limit->n.max; |
f77f13e2 | 827 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 828 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 829 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
830 | for (clock.m1 = limit->m1.max; |
831 | clock.m1 >= limit->m1.min; clock.m1--) { | |
832 | for (clock.m2 = limit->m2.max; | |
833 | clock.m2 >= limit->m2.min; clock.m2--) { | |
834 | for (clock.p1 = limit->p1.max; | |
835 | clock.p1 >= limit->p1.min; clock.p1--) { | |
836 | int this_err; | |
837 | ||
dccbea3b | 838 | i9xx_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
839 | if (!intel_PLL_is_valid(dev, limit, |
840 | &clock)) | |
d4906093 | 841 | continue; |
1b894b59 CW |
842 | |
843 | this_err = abs(clock.dot - target); | |
d4906093 ML |
844 | if (this_err < err_most) { |
845 | *best_clock = clock; | |
846 | err_most = this_err; | |
847 | max_n = clock.n; | |
848 | found = true; | |
849 | } | |
850 | } | |
851 | } | |
852 | } | |
853 | } | |
2c07245f ZW |
854 | return found; |
855 | } | |
856 | ||
d5dd62bd ID |
857 | /* |
858 | * Check if the calculated PLL configuration is more optimal compared to the | |
859 | * best configuration and error found so far. Return the calculated error. | |
860 | */ | |
861 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
862 | const intel_clock_t *calculated_clock, | |
863 | const intel_clock_t *best_clock, | |
864 | unsigned int best_error_ppm, | |
865 | unsigned int *error_ppm) | |
866 | { | |
9ca3ba01 ID |
867 | /* |
868 | * For CHV ignore the error and consider only the P value. | |
869 | * Prefer a bigger P value based on HW requirements. | |
870 | */ | |
871 | if (IS_CHERRYVIEW(dev)) { | |
872 | *error_ppm = 0; | |
873 | ||
874 | return calculated_clock->p > best_clock->p; | |
875 | } | |
876 | ||
24be4e46 ID |
877 | if (WARN_ON_ONCE(!target_freq)) |
878 | return false; | |
879 | ||
d5dd62bd ID |
880 | *error_ppm = div_u64(1000000ULL * |
881 | abs(target_freq - calculated_clock->dot), | |
882 | target_freq); | |
883 | /* | |
884 | * Prefer a better P value over a better (smaller) error if the error | |
885 | * is small. Ensure this preference for future configurations too by | |
886 | * setting the error to 0. | |
887 | */ | |
888 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
889 | *error_ppm = 0; | |
890 | ||
891 | return true; | |
892 | } | |
893 | ||
894 | return *error_ppm + 10 < best_error_ppm; | |
895 | } | |
896 | ||
a0c4da24 | 897 | static bool |
a93e255f ACO |
898 | vlv_find_best_dpll(const intel_limit_t *limit, |
899 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
900 | int target, int refclk, intel_clock_t *match_clock, |
901 | intel_clock_t *best_clock) | |
a0c4da24 | 902 | { |
a93e255f | 903 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 904 | struct drm_device *dev = crtc->base.dev; |
6b4bf1c4 | 905 | intel_clock_t clock; |
69e4f900 | 906 | unsigned int bestppm = 1000000; |
27e639bf VS |
907 | /* min update 19.2 MHz */ |
908 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 909 | bool found = false; |
a0c4da24 | 910 | |
6b4bf1c4 VS |
911 | target *= 5; /* fast clock */ |
912 | ||
913 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
914 | |
915 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 916 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 917 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 918 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 919 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 920 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 921 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 922 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 923 | unsigned int ppm; |
69e4f900 | 924 | |
6b4bf1c4 VS |
925 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
926 | refclk * clock.m1); | |
927 | ||
dccbea3b | 928 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 929 | |
f01b7962 VS |
930 | if (!intel_PLL_is_valid(dev, limit, |
931 | &clock)) | |
43b0ac53 VS |
932 | continue; |
933 | ||
d5dd62bd ID |
934 | if (!vlv_PLL_is_optimal(dev, target, |
935 | &clock, | |
936 | best_clock, | |
937 | bestppm, &ppm)) | |
938 | continue; | |
6b4bf1c4 | 939 | |
d5dd62bd ID |
940 | *best_clock = clock; |
941 | bestppm = ppm; | |
942 | found = true; | |
a0c4da24 JB |
943 | } |
944 | } | |
945 | } | |
946 | } | |
a0c4da24 | 947 | |
49e497ef | 948 | return found; |
a0c4da24 | 949 | } |
a4fc5ed6 | 950 | |
ef9348c8 | 951 | static bool |
a93e255f ACO |
952 | chv_find_best_dpll(const intel_limit_t *limit, |
953 | struct intel_crtc_state *crtc_state, | |
ef9348c8 CML |
954 | int target, int refclk, intel_clock_t *match_clock, |
955 | intel_clock_t *best_clock) | |
956 | { | |
a93e255f | 957 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 958 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 959 | unsigned int best_error_ppm; |
ef9348c8 CML |
960 | intel_clock_t clock; |
961 | uint64_t m2; | |
962 | int found = false; | |
963 | ||
964 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 965 | best_error_ppm = 1000000; |
ef9348c8 CML |
966 | |
967 | /* | |
968 | * Based on hardware doc, the n always set to 1, and m1 always | |
969 | * set to 2. If requires to support 200Mhz refclk, we need to | |
970 | * revisit this because n may not 1 anymore. | |
971 | */ | |
972 | clock.n = 1, clock.m1 = 2; | |
973 | target *= 5; /* fast clock */ | |
974 | ||
975 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
976 | for (clock.p2 = limit->p2.p2_fast; | |
977 | clock.p2 >= limit->p2.p2_slow; | |
978 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 979 | unsigned int error_ppm; |
ef9348c8 CML |
980 | |
981 | clock.p = clock.p1 * clock.p2; | |
982 | ||
983 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
984 | clock.n) << 22, refclk * clock.m1); | |
985 | ||
986 | if (m2 > INT_MAX/clock.m1) | |
987 | continue; | |
988 | ||
989 | clock.m2 = m2; | |
990 | ||
dccbea3b | 991 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 CML |
992 | |
993 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
994 | continue; | |
995 | ||
9ca3ba01 ID |
996 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
997 | best_error_ppm, &error_ppm)) | |
998 | continue; | |
999 | ||
1000 | *best_clock = clock; | |
1001 | best_error_ppm = error_ppm; | |
1002 | found = true; | |
ef9348c8 CML |
1003 | } |
1004 | } | |
1005 | ||
1006 | return found; | |
1007 | } | |
1008 | ||
5ab7b0b7 ID |
1009 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
1010 | intel_clock_t *best_clock) | |
1011 | { | |
1012 | int refclk = i9xx_get_refclk(crtc_state, 0); | |
1013 | ||
1014 | return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state, | |
1015 | target_clock, refclk, NULL, best_clock); | |
1016 | } | |
1017 | ||
20ddf665 VS |
1018 | bool intel_crtc_active(struct drm_crtc *crtc) |
1019 | { | |
1020 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1021 | ||
1022 | /* Be paranoid as we can arrive here with only partial | |
1023 | * state retrieved from the hardware during setup. | |
1024 | * | |
241bfc38 | 1025 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
1026 | * as Haswell has gained clock readout/fastboot support. |
1027 | * | |
66e514c1 | 1028 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 1029 | * properly reconstruct framebuffers. |
c3d1f436 MR |
1030 | * |
1031 | * FIXME: The intel_crtc->active here should be switched to | |
1032 | * crtc->state->active once we have proper CRTC states wired up | |
1033 | * for atomic. | |
20ddf665 | 1034 | */ |
c3d1f436 | 1035 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 1036 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
1037 | } |
1038 | ||
a5c961d1 PZ |
1039 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1040 | enum pipe pipe) | |
1041 | { | |
1042 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1043 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1044 | ||
6e3c9717 | 1045 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1046 | } |
1047 | ||
fbf49ea2 VS |
1048 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
1049 | { | |
1050 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1051 | u32 reg = PIPEDSL(pipe); | |
1052 | u32 line1, line2; | |
1053 | u32 line_mask; | |
1054 | ||
1055 | if (IS_GEN2(dev)) | |
1056 | line_mask = DSL_LINEMASK_GEN2; | |
1057 | else | |
1058 | line_mask = DSL_LINEMASK_GEN3; | |
1059 | ||
1060 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 1061 | msleep(5); |
fbf49ea2 VS |
1062 | line2 = I915_READ(reg) & line_mask; |
1063 | ||
1064 | return line1 == line2; | |
1065 | } | |
1066 | ||
ab7ad7f6 KP |
1067 | /* |
1068 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1069 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1070 | * |
1071 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1072 | * spinning on the vblank interrupt status bit, since we won't actually | |
1073 | * see an interrupt when the pipe is disabled. | |
1074 | * | |
ab7ad7f6 KP |
1075 | * On Gen4 and above: |
1076 | * wait for the pipe register state bit to turn off | |
1077 | * | |
1078 | * Otherwise: | |
1079 | * wait for the display line value to settle (it usually | |
1080 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1081 | * |
9d0498a2 | 1082 | */ |
575f7ab7 | 1083 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1084 | { |
575f7ab7 | 1085 | struct drm_device *dev = crtc->base.dev; |
9d0498a2 | 1086 | struct drm_i915_private *dev_priv = dev->dev_private; |
6e3c9717 | 1087 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1088 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
1089 | |
1090 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 1091 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1092 | |
1093 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
1094 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1095 | 100)) | |
284637d9 | 1096 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1097 | } else { |
ab7ad7f6 | 1098 | /* Wait for the display line to settle */ |
fbf49ea2 | 1099 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1100 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1101 | } |
79e53945 JB |
1102 | } |
1103 | ||
b24e7179 JB |
1104 | static const char *state_string(bool enabled) |
1105 | { | |
1106 | return enabled ? "on" : "off"; | |
1107 | } | |
1108 | ||
1109 | /* Only for pre-ILK configs */ | |
55607e8a DV |
1110 | void assert_pll(struct drm_i915_private *dev_priv, |
1111 | enum pipe pipe, bool state) | |
b24e7179 JB |
1112 | { |
1113 | int reg; | |
1114 | u32 val; | |
1115 | bool cur_state; | |
1116 | ||
1117 | reg = DPLL(pipe); | |
1118 | val = I915_READ(reg); | |
1119 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
e2c719b7 | 1120 | I915_STATE_WARN(cur_state != state, |
b24e7179 JB |
1121 | "PLL state assertion failure (expected %s, current %s)\n", |
1122 | state_string(state), state_string(cur_state)); | |
1123 | } | |
b24e7179 | 1124 | |
23538ef1 JN |
1125 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1126 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1127 | { | |
1128 | u32 val; | |
1129 | bool cur_state; | |
1130 | ||
a580516d | 1131 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1132 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1133 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1134 | |
1135 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1136 | I915_STATE_WARN(cur_state != state, |
23538ef1 JN |
1137 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
1138 | state_string(state), state_string(cur_state)); | |
1139 | } | |
1140 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1141 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1142 | ||
55607e8a | 1143 | struct intel_shared_dpll * |
e2b78267 DV |
1144 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1145 | { | |
1146 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1147 | ||
6e3c9717 | 1148 | if (crtc->config->shared_dpll < 0) |
e2b78267 DV |
1149 | return NULL; |
1150 | ||
6e3c9717 | 1151 | return &dev_priv->shared_dplls[crtc->config->shared_dpll]; |
e2b78267 DV |
1152 | } |
1153 | ||
040484af | 1154 | /* For ILK+ */ |
55607e8a DV |
1155 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1156 | struct intel_shared_dpll *pll, | |
1157 | bool state) | |
040484af | 1158 | { |
040484af | 1159 | bool cur_state; |
5358901f | 1160 | struct intel_dpll_hw_state hw_state; |
040484af | 1161 | |
92b27b08 | 1162 | if (WARN (!pll, |
46edb027 | 1163 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 1164 | return; |
ee7b9f93 | 1165 | |
5358901f | 1166 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
e2c719b7 | 1167 | I915_STATE_WARN(cur_state != state, |
5358901f DV |
1168 | "%s assertion failure (expected %s, current %s)\n", |
1169 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 1170 | } |
040484af JB |
1171 | |
1172 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1173 | enum pipe pipe, bool state) | |
1174 | { | |
1175 | int reg; | |
1176 | u32 val; | |
1177 | bool cur_state; | |
ad80a810 PZ |
1178 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1179 | pipe); | |
040484af | 1180 | |
affa9354 PZ |
1181 | if (HAS_DDI(dev_priv->dev)) { |
1182 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 1183 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 1184 | val = I915_READ(reg); |
ad80a810 | 1185 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
1186 | } else { |
1187 | reg = FDI_TX_CTL(pipe); | |
1188 | val = I915_READ(reg); | |
1189 | cur_state = !!(val & FDI_TX_ENABLE); | |
1190 | } | |
e2c719b7 | 1191 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1192 | "FDI TX state assertion failure (expected %s, current %s)\n", |
1193 | state_string(state), state_string(cur_state)); | |
1194 | } | |
1195 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1196 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1197 | ||
1198 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1199 | enum pipe pipe, bool state) | |
1200 | { | |
1201 | int reg; | |
1202 | u32 val; | |
1203 | bool cur_state; | |
1204 | ||
d63fa0dc PZ |
1205 | reg = FDI_RX_CTL(pipe); |
1206 | val = I915_READ(reg); | |
1207 | cur_state = !!(val & FDI_RX_ENABLE); | |
e2c719b7 | 1208 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1209 | "FDI RX state assertion failure (expected %s, current %s)\n", |
1210 | state_string(state), state_string(cur_state)); | |
1211 | } | |
1212 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1213 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1214 | ||
1215 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1216 | enum pipe pipe) | |
1217 | { | |
1218 | int reg; | |
1219 | u32 val; | |
1220 | ||
1221 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1222 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1223 | return; |
1224 | ||
bf507ef7 | 1225 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1226 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1227 | return; |
1228 | ||
040484af JB |
1229 | reg = FDI_TX_CTL(pipe); |
1230 | val = I915_READ(reg); | |
e2c719b7 | 1231 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1232 | } |
1233 | ||
55607e8a DV |
1234 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1235 | enum pipe pipe, bool state) | |
040484af JB |
1236 | { |
1237 | int reg; | |
1238 | u32 val; | |
55607e8a | 1239 | bool cur_state; |
040484af JB |
1240 | |
1241 | reg = FDI_RX_CTL(pipe); | |
1242 | val = I915_READ(reg); | |
55607e8a | 1243 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1244 | I915_STATE_WARN(cur_state != state, |
55607e8a DV |
1245 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
1246 | state_string(state), state_string(cur_state)); | |
040484af JB |
1247 | } |
1248 | ||
b680c37a DV |
1249 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1250 | enum pipe pipe) | |
ea0760cf | 1251 | { |
bedd4dba JN |
1252 | struct drm_device *dev = dev_priv->dev; |
1253 | int pp_reg; | |
ea0760cf JB |
1254 | u32 val; |
1255 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1256 | bool locked = true; |
ea0760cf | 1257 | |
bedd4dba JN |
1258 | if (WARN_ON(HAS_DDI(dev))) |
1259 | return; | |
1260 | ||
1261 | if (HAS_PCH_SPLIT(dev)) { | |
1262 | u32 port_sel; | |
1263 | ||
ea0760cf | 1264 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1265 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1266 | ||
1267 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1268 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1269 | panel_pipe = PIPE_B; | |
1270 | /* XXX: else fix for eDP */ | |
1271 | } else if (IS_VALLEYVIEW(dev)) { | |
1272 | /* presumably write lock depends on pipe, not port select */ | |
1273 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1274 | panel_pipe = pipe; | |
ea0760cf JB |
1275 | } else { |
1276 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1277 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1278 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1279 | } |
1280 | ||
1281 | val = I915_READ(pp_reg); | |
1282 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1283 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1284 | locked = false; |
1285 | ||
e2c719b7 | 1286 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1287 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1288 | pipe_name(pipe)); |
ea0760cf JB |
1289 | } |
1290 | ||
93ce0ba6 JN |
1291 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1292 | enum pipe pipe, bool state) | |
1293 | { | |
1294 | struct drm_device *dev = dev_priv->dev; | |
1295 | bool cur_state; | |
1296 | ||
d9d82081 | 1297 | if (IS_845G(dev) || IS_I865G(dev)) |
93ce0ba6 | 1298 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; |
d9d82081 | 1299 | else |
5efb3e28 | 1300 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1301 | |
e2c719b7 | 1302 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 JN |
1303 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
1304 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1305 | } | |
1306 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1307 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1308 | ||
b840d907 JB |
1309 | void assert_pipe(struct drm_i915_private *dev_priv, |
1310 | enum pipe pipe, bool state) | |
b24e7179 JB |
1311 | { |
1312 | int reg; | |
1313 | u32 val; | |
63d7bbe9 | 1314 | bool cur_state; |
702e7a56 PZ |
1315 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1316 | pipe); | |
b24e7179 | 1317 | |
b6b5d049 VS |
1318 | /* if we need the pipe quirk it must be always on */ |
1319 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1320 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1321 | state = true; |
1322 | ||
f458ebbc | 1323 | if (!intel_display_power_is_enabled(dev_priv, |
b97186f0 | 1324 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
69310161 PZ |
1325 | cur_state = false; |
1326 | } else { | |
1327 | reg = PIPECONF(cpu_transcoder); | |
1328 | val = I915_READ(reg); | |
1329 | cur_state = !!(val & PIPECONF_ENABLE); | |
1330 | } | |
1331 | ||
e2c719b7 | 1332 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1333 | "pipe %c assertion failure (expected %s, current %s)\n", |
9db4a9c7 | 1334 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1335 | } |
1336 | ||
931872fc CW |
1337 | static void assert_plane(struct drm_i915_private *dev_priv, |
1338 | enum plane plane, bool state) | |
b24e7179 JB |
1339 | { |
1340 | int reg; | |
1341 | u32 val; | |
931872fc | 1342 | bool cur_state; |
b24e7179 JB |
1343 | |
1344 | reg = DSPCNTR(plane); | |
1345 | val = I915_READ(reg); | |
931872fc | 1346 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1347 | I915_STATE_WARN(cur_state != state, |
931872fc CW |
1348 | "plane %c assertion failure (expected %s, current %s)\n", |
1349 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1350 | } |
1351 | ||
931872fc CW |
1352 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1353 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1354 | ||
b24e7179 JB |
1355 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1356 | enum pipe pipe) | |
1357 | { | |
653e1026 | 1358 | struct drm_device *dev = dev_priv->dev; |
b24e7179 JB |
1359 | int reg, i; |
1360 | u32 val; | |
1361 | int cur_pipe; | |
1362 | ||
653e1026 VS |
1363 | /* Primary planes are fixed to pipes on gen4+ */ |
1364 | if (INTEL_INFO(dev)->gen >= 4) { | |
28c05794 AJ |
1365 | reg = DSPCNTR(pipe); |
1366 | val = I915_READ(reg); | |
e2c719b7 | 1367 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1368 | "plane %c assertion failure, should be disabled but not\n", |
1369 | plane_name(pipe)); | |
19ec1358 | 1370 | return; |
28c05794 | 1371 | } |
19ec1358 | 1372 | |
b24e7179 | 1373 | /* Need to check both planes against the pipe */ |
055e393f | 1374 | for_each_pipe(dev_priv, i) { |
b24e7179 JB |
1375 | reg = DSPCNTR(i); |
1376 | val = I915_READ(reg); | |
1377 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1378 | DISPPLANE_SEL_PIPE_SHIFT; | |
e2c719b7 | 1379 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1380 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1381 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1382 | } |
1383 | } | |
1384 | ||
19332d7a JB |
1385 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1386 | enum pipe pipe) | |
1387 | { | |
20674eef | 1388 | struct drm_device *dev = dev_priv->dev; |
1fe47785 | 1389 | int reg, sprite; |
19332d7a JB |
1390 | u32 val; |
1391 | ||
7feb8b88 | 1392 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1393 | for_each_sprite(dev_priv, pipe, sprite) { |
7feb8b88 | 1394 | val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1395 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1396 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1397 | sprite, pipe_name(pipe)); | |
1398 | } | |
1399 | } else if (IS_VALLEYVIEW(dev)) { | |
3bdcfc0c | 1400 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 1401 | reg = SPCNTR(pipe, sprite); |
20674eef | 1402 | val = I915_READ(reg); |
e2c719b7 | 1403 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1404 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1405 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1406 | } |
1407 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
1408 | reg = SPRCTL(pipe); | |
19332d7a | 1409 | val = I915_READ(reg); |
e2c719b7 | 1410 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1411 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1412 | plane_name(pipe), pipe_name(pipe)); |
1413 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1414 | reg = DVSCNTR(pipe); | |
19332d7a | 1415 | val = I915_READ(reg); |
e2c719b7 | 1416 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1417 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1418 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1419 | } |
1420 | } | |
1421 | ||
08c71e5e VS |
1422 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1423 | { | |
e2c719b7 | 1424 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1425 | drm_crtc_vblank_put(crtc); |
1426 | } | |
1427 | ||
89eff4be | 1428 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1429 | { |
1430 | u32 val; | |
1431 | bool enabled; | |
1432 | ||
e2c719b7 | 1433 | I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1434 | |
92f2584a JB |
1435 | val = I915_READ(PCH_DREF_CONTROL); |
1436 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1437 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
e2c719b7 | 1438 | I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
92f2584a JB |
1439 | } |
1440 | ||
ab9412ba DV |
1441 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1442 | enum pipe pipe) | |
92f2584a JB |
1443 | { |
1444 | int reg; | |
1445 | u32 val; | |
1446 | bool enabled; | |
1447 | ||
ab9412ba | 1448 | reg = PCH_TRANSCONF(pipe); |
92f2584a JB |
1449 | val = I915_READ(reg); |
1450 | enabled = !!(val & TRANS_ENABLE); | |
e2c719b7 | 1451 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1452 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1453 | pipe_name(pipe)); | |
92f2584a JB |
1454 | } |
1455 | ||
4e634389 KP |
1456 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1457 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1458 | { |
1459 | if ((val & DP_PORT_EN) == 0) | |
1460 | return false; | |
1461 | ||
1462 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1463 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1464 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1465 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1466 | return false; | |
44f37d1f CML |
1467 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1468 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1469 | return false; | |
f0575e92 KP |
1470 | } else { |
1471 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1472 | return false; | |
1473 | } | |
1474 | return true; | |
1475 | } | |
1476 | ||
1519b995 KP |
1477 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1478 | enum pipe pipe, u32 val) | |
1479 | { | |
dc0fa718 | 1480 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1481 | return false; |
1482 | ||
1483 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1484 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1485 | return false; |
44f37d1f CML |
1486 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1487 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1488 | return false; | |
1519b995 | 1489 | } else { |
dc0fa718 | 1490 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1491 | return false; |
1492 | } | |
1493 | return true; | |
1494 | } | |
1495 | ||
1496 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1497 | enum pipe pipe, u32 val) | |
1498 | { | |
1499 | if ((val & LVDS_PORT_EN) == 0) | |
1500 | return false; | |
1501 | ||
1502 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1503 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1504 | return false; | |
1505 | } else { | |
1506 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1507 | return false; | |
1508 | } | |
1509 | return true; | |
1510 | } | |
1511 | ||
1512 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1513 | enum pipe pipe, u32 val) | |
1514 | { | |
1515 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1516 | return false; | |
1517 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1518 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1519 | return false; | |
1520 | } else { | |
1521 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1522 | return false; | |
1523 | } | |
1524 | return true; | |
1525 | } | |
1526 | ||
291906f1 | 1527 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1528 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1529 | { |
47a05eca | 1530 | u32 val = I915_READ(reg); |
e2c719b7 | 1531 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1532 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1533 | reg, pipe_name(pipe)); |
de9a35ab | 1534 | |
e2c719b7 | 1535 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1536 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1537 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1538 | } |
1539 | ||
1540 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1541 | enum pipe pipe, int reg) | |
1542 | { | |
47a05eca | 1543 | u32 val = I915_READ(reg); |
e2c719b7 | 1544 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1545 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1546 | reg, pipe_name(pipe)); |
de9a35ab | 1547 | |
e2c719b7 | 1548 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1549 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1550 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1551 | } |
1552 | ||
1553 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1554 | enum pipe pipe) | |
1555 | { | |
1556 | int reg; | |
1557 | u32 val; | |
291906f1 | 1558 | |
f0575e92 KP |
1559 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1560 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1561 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1562 | |
1563 | reg = PCH_ADPA; | |
1564 | val = I915_READ(reg); | |
e2c719b7 | 1565 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1566 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1567 | pipe_name(pipe)); |
291906f1 JB |
1568 | |
1569 | reg = PCH_LVDS; | |
1570 | val = I915_READ(reg); | |
e2c719b7 | 1571 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1572 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1573 | pipe_name(pipe)); |
291906f1 | 1574 | |
e2debe91 PZ |
1575 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1576 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1577 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1578 | } |
1579 | ||
d288f65f | 1580 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1581 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1582 | { |
426115cf DV |
1583 | struct drm_device *dev = crtc->base.dev; |
1584 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1585 | int reg = DPLL(crtc->pipe); | |
d288f65f | 1586 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
87442f73 | 1587 | |
426115cf | 1588 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 DV |
1589 | |
1590 | /* No really, not for ILK+ */ | |
1591 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
1592 | ||
1593 | /* PLL is protected by panel, make sure we can write it */ | |
6a9e7363 | 1594 | if (IS_MOBILE(dev_priv->dev)) |
426115cf | 1595 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1596 | |
426115cf DV |
1597 | I915_WRITE(reg, dpll); |
1598 | POSTING_READ(reg); | |
1599 | udelay(150); | |
1600 | ||
1601 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1602 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1603 | ||
d288f65f | 1604 | I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); |
426115cf | 1605 | POSTING_READ(DPLL_MD(crtc->pipe)); |
87442f73 DV |
1606 | |
1607 | /* We do this three times for luck */ | |
426115cf | 1608 | I915_WRITE(reg, dpll); |
87442f73 DV |
1609 | POSTING_READ(reg); |
1610 | udelay(150); /* wait for warmup */ | |
426115cf | 1611 | I915_WRITE(reg, dpll); |
87442f73 DV |
1612 | POSTING_READ(reg); |
1613 | udelay(150); /* wait for warmup */ | |
426115cf | 1614 | I915_WRITE(reg, dpll); |
87442f73 DV |
1615 | POSTING_READ(reg); |
1616 | udelay(150); /* wait for warmup */ | |
1617 | } | |
1618 | ||
d288f65f | 1619 | static void chv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1620 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
1621 | { |
1622 | struct drm_device *dev = crtc->base.dev; | |
1623 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1624 | int pipe = crtc->pipe; | |
1625 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1626 | u32 tmp; |
1627 | ||
1628 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1629 | ||
1630 | BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); | |
1631 | ||
a580516d | 1632 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1633 | |
1634 | /* Enable back the 10bit clock to display controller */ | |
1635 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1636 | tmp |= DPIO_DCLKP_EN; | |
1637 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1638 | ||
54433e91 VS |
1639 | mutex_unlock(&dev_priv->sb_lock); |
1640 | ||
9d556c99 CML |
1641 | /* |
1642 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1643 | */ | |
1644 | udelay(1); | |
1645 | ||
1646 | /* Enable PLL */ | |
d288f65f | 1647 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1648 | |
1649 | /* Check PLL is locked */ | |
a11b0703 | 1650 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1651 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1652 | ||
a11b0703 | 1653 | /* not sure when this should be written */ |
d288f65f | 1654 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
a11b0703 | 1655 | POSTING_READ(DPLL_MD(pipe)); |
9d556c99 CML |
1656 | } |
1657 | ||
1c4e0274 VS |
1658 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1659 | { | |
1660 | struct intel_crtc *crtc; | |
1661 | int count = 0; | |
1662 | ||
1663 | for_each_intel_crtc(dev, crtc) | |
3538b9df | 1664 | count += crtc->base.state->active && |
409ee761 | 1665 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
1c4e0274 VS |
1666 | |
1667 | return count; | |
1668 | } | |
1669 | ||
66e3d5c0 | 1670 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1671 | { |
66e3d5c0 DV |
1672 | struct drm_device *dev = crtc->base.dev; |
1673 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1674 | int reg = DPLL(crtc->pipe); | |
6e3c9717 | 1675 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1676 | |
66e3d5c0 | 1677 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1678 | |
63d7bbe9 | 1679 | /* No really, not for ILK+ */ |
3d13ef2e | 1680 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1681 | |
1682 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1683 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1684 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1685 | |
1c4e0274 VS |
1686 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1687 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1688 | /* | |
1689 | * It appears to be important that we don't enable this | |
1690 | * for the current pipe before otherwise configuring the | |
1691 | * PLL. No idea how this should be handled if multiple | |
1692 | * DVO outputs are enabled simultaneosly. | |
1693 | */ | |
1694 | dpll |= DPLL_DVO_2X_MODE; | |
1695 | I915_WRITE(DPLL(!crtc->pipe), | |
1696 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1697 | } | |
66e3d5c0 DV |
1698 | |
1699 | /* Wait for the clocks to stabilize. */ | |
1700 | POSTING_READ(reg); | |
1701 | udelay(150); | |
1702 | ||
1703 | if (INTEL_INFO(dev)->gen >= 4) { | |
1704 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1705 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1706 | } else { |
1707 | /* The pixel multiplier can only be updated once the | |
1708 | * DPLL is enabled and the clocks are stable. | |
1709 | * | |
1710 | * So write it again. | |
1711 | */ | |
1712 | I915_WRITE(reg, dpll); | |
1713 | } | |
63d7bbe9 JB |
1714 | |
1715 | /* We do this three times for luck */ | |
66e3d5c0 | 1716 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1717 | POSTING_READ(reg); |
1718 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1719 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1720 | POSTING_READ(reg); |
1721 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1722 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1723 | POSTING_READ(reg); |
1724 | udelay(150); /* wait for warmup */ | |
1725 | } | |
1726 | ||
1727 | /** | |
50b44a44 | 1728 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1729 | * @dev_priv: i915 private structure |
1730 | * @pipe: pipe PLL to disable | |
1731 | * | |
1732 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1733 | * | |
1734 | * Note! This is for pre-ILK only. | |
1735 | */ | |
1c4e0274 | 1736 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1737 | { |
1c4e0274 VS |
1738 | struct drm_device *dev = crtc->base.dev; |
1739 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1740 | enum pipe pipe = crtc->pipe; | |
1741 | ||
1742 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1743 | if (IS_I830(dev) && | |
409ee761 | 1744 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
3538b9df | 1745 | !intel_num_dvo_pipes(dev)) { |
1c4e0274 VS |
1746 | I915_WRITE(DPLL(PIPE_B), |
1747 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1748 | I915_WRITE(DPLL(PIPE_A), | |
1749 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1750 | } | |
1751 | ||
b6b5d049 VS |
1752 | /* Don't disable pipe or pipe PLLs if needed */ |
1753 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1754 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1755 | return; |
1756 | ||
1757 | /* Make sure the pipe isn't still relying on us */ | |
1758 | assert_pipe_disabled(dev_priv, pipe); | |
1759 | ||
b8afb911 | 1760 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1761 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1762 | } |
1763 | ||
f6071166 JB |
1764 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1765 | { | |
b8afb911 | 1766 | u32 val; |
f6071166 JB |
1767 | |
1768 | /* Make sure the pipe isn't still relying on us */ | |
1769 | assert_pipe_disabled(dev_priv, pipe); | |
1770 | ||
e5cbfbfb ID |
1771 | /* |
1772 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1773 | * The latter is needed for VGA hotplug / manual detection. | |
1774 | */ | |
b8afb911 | 1775 | val = DPLL_VGA_MODE_DIS; |
f6071166 | 1776 | if (pipe == PIPE_B) |
60bfe44f | 1777 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV; |
f6071166 JB |
1778 | I915_WRITE(DPLL(pipe), val); |
1779 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1780 | |
1781 | } | |
1782 | ||
1783 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1784 | { | |
d752048d | 1785 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1786 | u32 val; |
1787 | ||
a11b0703 VS |
1788 | /* Make sure the pipe isn't still relying on us */ |
1789 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1790 | |
a11b0703 | 1791 | /* Set PLL en = 0 */ |
60bfe44f VS |
1792 | val = DPLL_SSC_REF_CLK_CHV | |
1793 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1794 | if (pipe != PIPE_A) |
1795 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1796 | I915_WRITE(DPLL(pipe), val); | |
1797 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1798 | |
a580516d | 1799 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1800 | |
1801 | /* Disable 10bit clock to display controller */ | |
1802 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1803 | val &= ~DPIO_DCLKP_EN; | |
1804 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1805 | ||
a580516d | 1806 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1807 | } |
1808 | ||
e4607fcf | 1809 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1810 | struct intel_digital_port *dport, |
1811 | unsigned int expected_mask) | |
89b667f8 JB |
1812 | { |
1813 | u32 port_mask; | |
00fc31b7 | 1814 | int dpll_reg; |
89b667f8 | 1815 | |
e4607fcf CML |
1816 | switch (dport->port) { |
1817 | case PORT_B: | |
89b667f8 | 1818 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1819 | dpll_reg = DPLL(0); |
e4607fcf CML |
1820 | break; |
1821 | case PORT_C: | |
89b667f8 | 1822 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1823 | dpll_reg = DPLL(0); |
9b6de0a1 | 1824 | expected_mask <<= 4; |
00fc31b7 CML |
1825 | break; |
1826 | case PORT_D: | |
1827 | port_mask = DPLL_PORTD_READY_MASK; | |
1828 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1829 | break; |
1830 | default: | |
1831 | BUG(); | |
1832 | } | |
89b667f8 | 1833 | |
9b6de0a1 VS |
1834 | if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000)) |
1835 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", | |
1836 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1837 | } |
1838 | ||
b14b1055 DV |
1839 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1840 | { | |
1841 | struct drm_device *dev = crtc->base.dev; | |
1842 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1843 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
1844 | ||
be19f0ff CW |
1845 | if (WARN_ON(pll == NULL)) |
1846 | return; | |
1847 | ||
3e369b76 | 1848 | WARN_ON(!pll->config.crtc_mask); |
b14b1055 DV |
1849 | if (pll->active == 0) { |
1850 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
1851 | WARN_ON(pll->on); | |
1852 | assert_shared_dpll_disabled(dev_priv, pll); | |
1853 | ||
1854 | pll->mode_set(dev_priv, pll); | |
1855 | } | |
1856 | } | |
1857 | ||
92f2584a | 1858 | /** |
85b3894f | 1859 | * intel_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1860 | * @dev_priv: i915 private structure |
1861 | * @pipe: pipe PLL to enable | |
1862 | * | |
1863 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1864 | * drives the transcoder clock. | |
1865 | */ | |
85b3894f | 1866 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1867 | { |
3d13ef2e DL |
1868 | struct drm_device *dev = crtc->base.dev; |
1869 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1870 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1871 | |
87a875bb | 1872 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1873 | return; |
1874 | ||
3e369b76 | 1875 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1876 | return; |
ee7b9f93 | 1877 | |
74dd6928 | 1878 | DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n", |
46edb027 | 1879 | pll->name, pll->active, pll->on, |
e2b78267 | 1880 | crtc->base.base.id); |
92f2584a | 1881 | |
cdbd2316 DV |
1882 | if (pll->active++) { |
1883 | WARN_ON(!pll->on); | |
e9d6944e | 1884 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1885 | return; |
1886 | } | |
f4a091c7 | 1887 | WARN_ON(pll->on); |
ee7b9f93 | 1888 | |
bd2bb1b9 PZ |
1889 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
1890 | ||
46edb027 | 1891 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1892 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1893 | pll->on = true; |
92f2584a JB |
1894 | } |
1895 | ||
f6daaec2 | 1896 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1897 | { |
3d13ef2e DL |
1898 | struct drm_device *dev = crtc->base.dev; |
1899 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1900 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1901 | |
92f2584a | 1902 | /* PCH only available on ILK+ */ |
80aa9312 JB |
1903 | if (INTEL_INFO(dev)->gen < 5) |
1904 | return; | |
1905 | ||
eddfcbcd ML |
1906 | if (pll == NULL) |
1907 | return; | |
92f2584a | 1908 | |
eddfcbcd | 1909 | if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base))))) |
48da64a8 | 1910 | return; |
7a419866 | 1911 | |
46edb027 DV |
1912 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1913 | pll->name, pll->active, pll->on, | |
e2b78267 | 1914 | crtc->base.base.id); |
7a419866 | 1915 | |
48da64a8 | 1916 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1917 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1918 | return; |
1919 | } | |
1920 | ||
e9d6944e | 1921 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1922 | WARN_ON(!pll->on); |
cdbd2316 | 1923 | if (--pll->active) |
7a419866 | 1924 | return; |
ee7b9f93 | 1925 | |
46edb027 | 1926 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1927 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1928 | pll->on = false; |
bd2bb1b9 PZ |
1929 | |
1930 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
92f2584a JB |
1931 | } |
1932 | ||
b8a4f404 PZ |
1933 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1934 | enum pipe pipe) | |
040484af | 1935 | { |
23670b32 | 1936 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1937 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1938 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
23670b32 | 1939 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1940 | |
1941 | /* PCH only available on ILK+ */ | |
55522f37 | 1942 | BUG_ON(!HAS_PCH_SPLIT(dev)); |
040484af JB |
1943 | |
1944 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1945 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1946 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1947 | |
1948 | /* FDI must be feeding us bits for PCH ports */ | |
1949 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1950 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1951 | ||
23670b32 DV |
1952 | if (HAS_PCH_CPT(dev)) { |
1953 | /* Workaround: Set the timing override bit before enabling the | |
1954 | * pch transcoder. */ | |
1955 | reg = TRANS_CHICKEN2(pipe); | |
1956 | val = I915_READ(reg); | |
1957 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1958 | I915_WRITE(reg, val); | |
59c859d6 | 1959 | } |
23670b32 | 1960 | |
ab9412ba | 1961 | reg = PCH_TRANSCONF(pipe); |
040484af | 1962 | val = I915_READ(reg); |
5f7f726d | 1963 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1964 | |
1965 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1966 | /* | |
c5de7c6f VS |
1967 | * Make the BPC in transcoder be consistent with |
1968 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1969 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1970 | */ |
dfd07d72 | 1971 | val &= ~PIPECONF_BPC_MASK; |
c5de7c6f VS |
1972 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI)) |
1973 | val |= PIPECONF_8BPC; | |
1974 | else | |
1975 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1976 | } |
5f7f726d PZ |
1977 | |
1978 | val &= ~TRANS_INTERLACE_MASK; | |
1979 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 | 1980 | if (HAS_PCH_IBX(dev_priv->dev) && |
409ee761 | 1981 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
1982 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1983 | else | |
1984 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1985 | else |
1986 | val |= TRANS_PROGRESSIVE; | |
1987 | ||
040484af JB |
1988 | I915_WRITE(reg, val | TRANS_ENABLE); |
1989 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 1990 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1991 | } |
1992 | ||
8fb033d7 | 1993 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1994 | enum transcoder cpu_transcoder) |
040484af | 1995 | { |
8fb033d7 | 1996 | u32 val, pipeconf_val; |
8fb033d7 PZ |
1997 | |
1998 | /* PCH only available on ILK+ */ | |
55522f37 | 1999 | BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev)); |
8fb033d7 | 2000 | |
8fb033d7 | 2001 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 2002 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 2003 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 2004 | |
223a6fdf PZ |
2005 | /* Workaround: set timing override bit. */ |
2006 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 2007 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
2008 | I915_WRITE(_TRANSA_CHICKEN2, val); |
2009 | ||
25f3ef11 | 2010 | val = TRANS_ENABLE; |
937bb610 | 2011 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 2012 | |
9a76b1c6 PZ |
2013 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
2014 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 2015 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
2016 | else |
2017 | val |= TRANS_PROGRESSIVE; | |
2018 | ||
ab9412ba DV |
2019 | I915_WRITE(LPT_TRANSCONF, val); |
2020 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 2021 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
2022 | } |
2023 | ||
b8a4f404 PZ |
2024 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
2025 | enum pipe pipe) | |
040484af | 2026 | { |
23670b32 DV |
2027 | struct drm_device *dev = dev_priv->dev; |
2028 | uint32_t reg, val; | |
040484af JB |
2029 | |
2030 | /* FDI relies on the transcoder */ | |
2031 | assert_fdi_tx_disabled(dev_priv, pipe); | |
2032 | assert_fdi_rx_disabled(dev_priv, pipe); | |
2033 | ||
291906f1 JB |
2034 | /* Ports must be off as well */ |
2035 | assert_pch_ports_disabled(dev_priv, pipe); | |
2036 | ||
ab9412ba | 2037 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
2038 | val = I915_READ(reg); |
2039 | val &= ~TRANS_ENABLE; | |
2040 | I915_WRITE(reg, val); | |
2041 | /* wait for PCH transcoder off, transcoder state */ | |
2042 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 2043 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 DV |
2044 | |
2045 | if (!HAS_PCH_IBX(dev)) { | |
2046 | /* Workaround: Clear the timing override chicken bit again. */ | |
2047 | reg = TRANS_CHICKEN2(pipe); | |
2048 | val = I915_READ(reg); | |
2049 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
2050 | I915_WRITE(reg, val); | |
2051 | } | |
040484af JB |
2052 | } |
2053 | ||
ab4d966c | 2054 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 2055 | { |
8fb033d7 PZ |
2056 | u32 val; |
2057 | ||
ab9412ba | 2058 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 2059 | val &= ~TRANS_ENABLE; |
ab9412ba | 2060 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 2061 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 2062 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 2063 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
2064 | |
2065 | /* Workaround: clear timing override bit. */ | |
2066 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 2067 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 2068 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
2069 | } |
2070 | ||
b24e7179 | 2071 | /** |
309cfea8 | 2072 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 2073 | * @crtc: crtc responsible for the pipe |
b24e7179 | 2074 | * |
0372264a | 2075 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 2076 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 2077 | */ |
e1fdc473 | 2078 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2079 | { |
0372264a PZ |
2080 | struct drm_device *dev = crtc->base.dev; |
2081 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2082 | enum pipe pipe = crtc->pipe; | |
702e7a56 PZ |
2083 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
2084 | pipe); | |
1a240d4d | 2085 | enum pipe pch_transcoder; |
b24e7179 JB |
2086 | int reg; |
2087 | u32 val; | |
2088 | ||
9e2ee2dd VS |
2089 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
2090 | ||
58c6eaa2 | 2091 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 2092 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
2093 | assert_sprites_disabled(dev_priv, pipe); |
2094 | ||
681e5811 | 2095 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
2096 | pch_transcoder = TRANSCODER_A; |
2097 | else | |
2098 | pch_transcoder = pipe; | |
2099 | ||
b24e7179 JB |
2100 | /* |
2101 | * A pipe without a PLL won't actually be able to drive bits from | |
2102 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
2103 | * need the check. | |
2104 | */ | |
50360403 | 2105 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) |
409ee761 | 2106 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
2107 | assert_dsi_pll_enabled(dev_priv); |
2108 | else | |
2109 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2110 | else { |
6e3c9717 | 2111 | if (crtc->config->has_pch_encoder) { |
040484af | 2112 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2113 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2114 | assert_fdi_tx_pll_enabled(dev_priv, |
2115 | (enum pipe) cpu_transcoder); | |
040484af JB |
2116 | } |
2117 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2118 | } | |
b24e7179 | 2119 | |
702e7a56 | 2120 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2121 | val = I915_READ(reg); |
7ad25d48 | 2122 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
2123 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
2124 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 2125 | return; |
7ad25d48 | 2126 | } |
00d70b15 CW |
2127 | |
2128 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2129 | POSTING_READ(reg); |
b24e7179 JB |
2130 | } |
2131 | ||
2132 | /** | |
309cfea8 | 2133 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2134 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2135 | * |
575f7ab7 VS |
2136 | * Disable the pipe of @crtc, making sure that various hardware |
2137 | * specific requirements are met, if applicable, e.g. plane | |
2138 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2139 | * |
2140 | * Will wait until the pipe has shut down before returning. | |
2141 | */ | |
575f7ab7 | 2142 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2143 | { |
575f7ab7 | 2144 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
6e3c9717 | 2145 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2146 | enum pipe pipe = crtc->pipe; |
b24e7179 JB |
2147 | int reg; |
2148 | u32 val; | |
2149 | ||
9e2ee2dd VS |
2150 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
2151 | ||
b24e7179 JB |
2152 | /* |
2153 | * Make sure planes won't keep trying to pump pixels to us, | |
2154 | * or we might hang the display. | |
2155 | */ | |
2156 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2157 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2158 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2159 | |
702e7a56 | 2160 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2161 | val = I915_READ(reg); |
00d70b15 CW |
2162 | if ((val & PIPECONF_ENABLE) == 0) |
2163 | return; | |
2164 | ||
67adc644 VS |
2165 | /* |
2166 | * Double wide has implications for planes | |
2167 | * so best keep it disabled when not needed. | |
2168 | */ | |
6e3c9717 | 2169 | if (crtc->config->double_wide) |
67adc644 VS |
2170 | val &= ~PIPECONF_DOUBLE_WIDE; |
2171 | ||
2172 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2173 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2174 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2175 | val &= ~PIPECONF_ENABLE; |
2176 | ||
2177 | I915_WRITE(reg, val); | |
2178 | if ((val & PIPECONF_ENABLE) == 0) | |
2179 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2180 | } |
2181 | ||
693db184 CW |
2182 | static bool need_vtd_wa(struct drm_device *dev) |
2183 | { | |
2184 | #ifdef CONFIG_INTEL_IOMMU | |
2185 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2186 | return true; | |
2187 | #endif | |
2188 | return false; | |
2189 | } | |
2190 | ||
50470bb0 | 2191 | unsigned int |
6761dd31 | 2192 | intel_tile_height(struct drm_device *dev, uint32_t pixel_format, |
fe47ea0c | 2193 | uint64_t fb_format_modifier, unsigned int plane) |
a57ce0b2 | 2194 | { |
6761dd31 TU |
2195 | unsigned int tile_height; |
2196 | uint32_t pixel_bytes; | |
a57ce0b2 | 2197 | |
b5d0e9bf DL |
2198 | switch (fb_format_modifier) { |
2199 | case DRM_FORMAT_MOD_NONE: | |
2200 | tile_height = 1; | |
2201 | break; | |
2202 | case I915_FORMAT_MOD_X_TILED: | |
2203 | tile_height = IS_GEN2(dev) ? 16 : 8; | |
2204 | break; | |
2205 | case I915_FORMAT_MOD_Y_TILED: | |
2206 | tile_height = 32; | |
2207 | break; | |
2208 | case I915_FORMAT_MOD_Yf_TILED: | |
fe47ea0c | 2209 | pixel_bytes = drm_format_plane_cpp(pixel_format, plane); |
6761dd31 | 2210 | switch (pixel_bytes) { |
b5d0e9bf | 2211 | default: |
6761dd31 | 2212 | case 1: |
b5d0e9bf DL |
2213 | tile_height = 64; |
2214 | break; | |
6761dd31 TU |
2215 | case 2: |
2216 | case 4: | |
b5d0e9bf DL |
2217 | tile_height = 32; |
2218 | break; | |
6761dd31 | 2219 | case 8: |
b5d0e9bf DL |
2220 | tile_height = 16; |
2221 | break; | |
6761dd31 | 2222 | case 16: |
b5d0e9bf DL |
2223 | WARN_ONCE(1, |
2224 | "128-bit pixels are not supported for display!"); | |
2225 | tile_height = 16; | |
2226 | break; | |
2227 | } | |
2228 | break; | |
2229 | default: | |
2230 | MISSING_CASE(fb_format_modifier); | |
2231 | tile_height = 1; | |
2232 | break; | |
2233 | } | |
091df6cb | 2234 | |
6761dd31 TU |
2235 | return tile_height; |
2236 | } | |
2237 | ||
2238 | unsigned int | |
2239 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
2240 | uint32_t pixel_format, uint64_t fb_format_modifier) | |
2241 | { | |
2242 | return ALIGN(height, intel_tile_height(dev, pixel_format, | |
fe47ea0c | 2243 | fb_format_modifier, 0)); |
a57ce0b2 JB |
2244 | } |
2245 | ||
f64b98cd TU |
2246 | static int |
2247 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb, | |
2248 | const struct drm_plane_state *plane_state) | |
2249 | { | |
50470bb0 | 2250 | struct intel_rotation_info *info = &view->rotation_info; |
84fe03f7 | 2251 | unsigned int tile_height, tile_pitch; |
50470bb0 | 2252 | |
f64b98cd TU |
2253 | *view = i915_ggtt_view_normal; |
2254 | ||
50470bb0 TU |
2255 | if (!plane_state) |
2256 | return 0; | |
2257 | ||
121920fa | 2258 | if (!intel_rotation_90_or_270(plane_state->rotation)) |
50470bb0 TU |
2259 | return 0; |
2260 | ||
9abc4648 | 2261 | *view = i915_ggtt_view_rotated; |
50470bb0 TU |
2262 | |
2263 | info->height = fb->height; | |
2264 | info->pixel_format = fb->pixel_format; | |
2265 | info->pitch = fb->pitches[0]; | |
89e3e142 | 2266 | info->uv_offset = fb->offsets[1]; |
50470bb0 TU |
2267 | info->fb_modifier = fb->modifier[0]; |
2268 | ||
84fe03f7 | 2269 | tile_height = intel_tile_height(fb->dev, fb->pixel_format, |
fe47ea0c | 2270 | fb->modifier[0], 0); |
84fe03f7 TU |
2271 | tile_pitch = PAGE_SIZE / tile_height; |
2272 | info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch); | |
2273 | info->height_pages = DIV_ROUND_UP(fb->height, tile_height); | |
2274 | info->size = info->width_pages * info->height_pages * PAGE_SIZE; | |
2275 | ||
89e3e142 TU |
2276 | if (info->pixel_format == DRM_FORMAT_NV12) { |
2277 | tile_height = intel_tile_height(fb->dev, fb->pixel_format, | |
2278 | fb->modifier[0], 1); | |
2279 | tile_pitch = PAGE_SIZE / tile_height; | |
2280 | info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch); | |
2281 | info->height_pages_uv = DIV_ROUND_UP(fb->height / 2, | |
2282 | tile_height); | |
2283 | info->size_uv = info->width_pages_uv * info->height_pages_uv * | |
2284 | PAGE_SIZE; | |
2285 | } | |
2286 | ||
f64b98cd TU |
2287 | return 0; |
2288 | } | |
2289 | ||
4e9a86b6 VS |
2290 | static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv) |
2291 | { | |
2292 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2293 | return 256 * 1024; | |
985b8bb4 VS |
2294 | else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || |
2295 | IS_VALLEYVIEW(dev_priv)) | |
4e9a86b6 VS |
2296 | return 128 * 1024; |
2297 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2298 | return 4 * 1024; | |
2299 | else | |
44c5905e | 2300 | return 0; |
4e9a86b6 VS |
2301 | } |
2302 | ||
127bd2ac | 2303 | int |
850c4cdc TU |
2304 | intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
2305 | struct drm_framebuffer *fb, | |
82bc3b2d | 2306 | const struct drm_plane_state *plane_state, |
91af127f JH |
2307 | struct intel_engine_cs *pipelined, |
2308 | struct drm_i915_gem_request **pipelined_request) | |
6b95a207 | 2309 | { |
850c4cdc | 2310 | struct drm_device *dev = fb->dev; |
ce453d81 | 2311 | struct drm_i915_private *dev_priv = dev->dev_private; |
850c4cdc | 2312 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2313 | struct i915_ggtt_view view; |
6b95a207 KH |
2314 | u32 alignment; |
2315 | int ret; | |
2316 | ||
ebcdd39e MR |
2317 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2318 | ||
7b911adc TU |
2319 | switch (fb->modifier[0]) { |
2320 | case DRM_FORMAT_MOD_NONE: | |
4e9a86b6 | 2321 | alignment = intel_linear_alignment(dev_priv); |
6b95a207 | 2322 | break; |
7b911adc | 2323 | case I915_FORMAT_MOD_X_TILED: |
1fada4cc DL |
2324 | if (INTEL_INFO(dev)->gen >= 9) |
2325 | alignment = 256 * 1024; | |
2326 | else { | |
2327 | /* pin() will align the object as required by fence */ | |
2328 | alignment = 0; | |
2329 | } | |
6b95a207 | 2330 | break; |
7b911adc | 2331 | case I915_FORMAT_MOD_Y_TILED: |
1327b9a1 DL |
2332 | case I915_FORMAT_MOD_Yf_TILED: |
2333 | if (WARN_ONCE(INTEL_INFO(dev)->gen < 9, | |
2334 | "Y tiling bo slipped through, driver bug!\n")) | |
2335 | return -EINVAL; | |
2336 | alignment = 1 * 1024 * 1024; | |
2337 | break; | |
6b95a207 | 2338 | default: |
7b911adc TU |
2339 | MISSING_CASE(fb->modifier[0]); |
2340 | return -EINVAL; | |
6b95a207 KH |
2341 | } |
2342 | ||
f64b98cd TU |
2343 | ret = intel_fill_fb_ggtt_view(&view, fb, plane_state); |
2344 | if (ret) | |
2345 | return ret; | |
2346 | ||
693db184 CW |
2347 | /* Note that the w/a also requires 64 PTE of padding following the |
2348 | * bo. We currently fill all unused PTE with the shadow page and so | |
2349 | * we should always have valid PTE following the scanout preventing | |
2350 | * the VT-d warning. | |
2351 | */ | |
2352 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2353 | alignment = 256 * 1024; | |
2354 | ||
d6dd6843 PZ |
2355 | /* |
2356 | * Global gtt pte registers are special registers which actually forward | |
2357 | * writes to a chunk of system memory. Which means that there is no risk | |
2358 | * that the register values disappear as soon as we call | |
2359 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2360 | * pin/unpin/fence and not more. | |
2361 | */ | |
2362 | intel_runtime_pm_get(dev_priv); | |
2363 | ||
ce453d81 | 2364 | dev_priv->mm.interruptible = false; |
e6617330 | 2365 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined, |
91af127f | 2366 | pipelined_request, &view); |
48b956c5 | 2367 | if (ret) |
ce453d81 | 2368 | goto err_interruptible; |
6b95a207 KH |
2369 | |
2370 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2371 | * fence, whereas 965+ only requires a fence if using | |
2372 | * framebuffer compression. For simplicity, we always install | |
2373 | * a fence as the cost is not that onerous. | |
2374 | */ | |
06d98131 | 2375 | ret = i915_gem_object_get_fence(obj); |
842315ee ML |
2376 | if (ret == -EDEADLK) { |
2377 | /* | |
2378 | * -EDEADLK means there are no free fences | |
2379 | * no pending flips. | |
2380 | * | |
2381 | * This is propagated to atomic, but it uses | |
2382 | * -EDEADLK to force a locking recovery, so | |
2383 | * change the returned error to -EBUSY. | |
2384 | */ | |
2385 | ret = -EBUSY; | |
2386 | goto err_unpin; | |
2387 | } else if (ret) | |
9a5a53b3 | 2388 | goto err_unpin; |
1690e1eb | 2389 | |
9a5a53b3 | 2390 | i915_gem_object_pin_fence(obj); |
6b95a207 | 2391 | |
ce453d81 | 2392 | dev_priv->mm.interruptible = true; |
d6dd6843 | 2393 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2394 | return 0; |
48b956c5 CW |
2395 | |
2396 | err_unpin: | |
f64b98cd | 2397 | i915_gem_object_unpin_from_display_plane(obj, &view); |
ce453d81 CW |
2398 | err_interruptible: |
2399 | dev_priv->mm.interruptible = true; | |
d6dd6843 | 2400 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2401 | return ret; |
6b95a207 KH |
2402 | } |
2403 | ||
82bc3b2d TU |
2404 | static void intel_unpin_fb_obj(struct drm_framebuffer *fb, |
2405 | const struct drm_plane_state *plane_state) | |
1690e1eb | 2406 | { |
82bc3b2d | 2407 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd TU |
2408 | struct i915_ggtt_view view; |
2409 | int ret; | |
82bc3b2d | 2410 | |
ebcdd39e MR |
2411 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2412 | ||
f64b98cd TU |
2413 | ret = intel_fill_fb_ggtt_view(&view, fb, plane_state); |
2414 | WARN_ONCE(ret, "Couldn't get view from plane state!"); | |
2415 | ||
1690e1eb | 2416 | i915_gem_object_unpin_fence(obj); |
f64b98cd | 2417 | i915_gem_object_unpin_from_display_plane(obj, &view); |
1690e1eb CW |
2418 | } |
2419 | ||
c2c75131 DV |
2420 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2421 | * is assumed to be a power-of-two. */ | |
4e9a86b6 VS |
2422 | unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv, |
2423 | int *x, int *y, | |
bc752862 CW |
2424 | unsigned int tiling_mode, |
2425 | unsigned int cpp, | |
2426 | unsigned int pitch) | |
c2c75131 | 2427 | { |
bc752862 CW |
2428 | if (tiling_mode != I915_TILING_NONE) { |
2429 | unsigned int tile_rows, tiles; | |
c2c75131 | 2430 | |
bc752862 CW |
2431 | tile_rows = *y / 8; |
2432 | *y %= 8; | |
c2c75131 | 2433 | |
bc752862 CW |
2434 | tiles = *x / (512/cpp); |
2435 | *x %= 512/cpp; | |
2436 | ||
2437 | return tile_rows * pitch * 8 + tiles * 4096; | |
2438 | } else { | |
4e9a86b6 | 2439 | unsigned int alignment = intel_linear_alignment(dev_priv) - 1; |
bc752862 CW |
2440 | unsigned int offset; |
2441 | ||
2442 | offset = *y * pitch + *x * cpp; | |
4e9a86b6 VS |
2443 | *y = (offset & alignment) / pitch; |
2444 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
2445 | return offset & ~alignment; | |
bc752862 | 2446 | } |
c2c75131 DV |
2447 | } |
2448 | ||
b35d63fa | 2449 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2450 | { |
2451 | switch (format) { | |
2452 | case DISPPLANE_8BPP: | |
2453 | return DRM_FORMAT_C8; | |
2454 | case DISPPLANE_BGRX555: | |
2455 | return DRM_FORMAT_XRGB1555; | |
2456 | case DISPPLANE_BGRX565: | |
2457 | return DRM_FORMAT_RGB565; | |
2458 | default: | |
2459 | case DISPPLANE_BGRX888: | |
2460 | return DRM_FORMAT_XRGB8888; | |
2461 | case DISPPLANE_RGBX888: | |
2462 | return DRM_FORMAT_XBGR8888; | |
2463 | case DISPPLANE_BGRX101010: | |
2464 | return DRM_FORMAT_XRGB2101010; | |
2465 | case DISPPLANE_RGBX101010: | |
2466 | return DRM_FORMAT_XBGR2101010; | |
2467 | } | |
2468 | } | |
2469 | ||
bc8d7dff DL |
2470 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2471 | { | |
2472 | switch (format) { | |
2473 | case PLANE_CTL_FORMAT_RGB_565: | |
2474 | return DRM_FORMAT_RGB565; | |
2475 | default: | |
2476 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2477 | if (rgb_order) { | |
2478 | if (alpha) | |
2479 | return DRM_FORMAT_ABGR8888; | |
2480 | else | |
2481 | return DRM_FORMAT_XBGR8888; | |
2482 | } else { | |
2483 | if (alpha) | |
2484 | return DRM_FORMAT_ARGB8888; | |
2485 | else | |
2486 | return DRM_FORMAT_XRGB8888; | |
2487 | } | |
2488 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2489 | if (rgb_order) | |
2490 | return DRM_FORMAT_XBGR2101010; | |
2491 | else | |
2492 | return DRM_FORMAT_XRGB2101010; | |
2493 | } | |
2494 | } | |
2495 | ||
5724dbd1 | 2496 | static bool |
f6936e29 DV |
2497 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2498 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2499 | { |
2500 | struct drm_device *dev = crtc->base.dev; | |
2501 | struct drm_i915_gem_object *obj = NULL; | |
2502 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2503 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2504 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2505 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2506 | PAGE_SIZE); | |
2507 | ||
2508 | size_aligned -= base_aligned; | |
46f297fb | 2509 | |
ff2652ea CW |
2510 | if (plane_config->size == 0) |
2511 | return false; | |
2512 | ||
f37b5c2b DV |
2513 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2514 | base_aligned, | |
2515 | base_aligned, | |
2516 | size_aligned); | |
46f297fb | 2517 | if (!obj) |
484b41dd | 2518 | return false; |
46f297fb | 2519 | |
49af449b DL |
2520 | obj->tiling_mode = plane_config->tiling; |
2521 | if (obj->tiling_mode == I915_TILING_X) | |
6bf129df | 2522 | obj->stride = fb->pitches[0]; |
46f297fb | 2523 | |
6bf129df DL |
2524 | mode_cmd.pixel_format = fb->pixel_format; |
2525 | mode_cmd.width = fb->width; | |
2526 | mode_cmd.height = fb->height; | |
2527 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2528 | mode_cmd.modifier[0] = fb->modifier[0]; |
2529 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb JB |
2530 | |
2531 | mutex_lock(&dev->struct_mutex); | |
6bf129df | 2532 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2533 | &mode_cmd, obj)) { |
46f297fb JB |
2534 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2535 | goto out_unref_obj; | |
2536 | } | |
46f297fb | 2537 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2538 | |
f6936e29 | 2539 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2540 | return true; |
46f297fb JB |
2541 | |
2542 | out_unref_obj: | |
2543 | drm_gem_object_unreference(&obj->base); | |
2544 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2545 | return false; |
2546 | } | |
2547 | ||
afd65eb4 MR |
2548 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2549 | static void | |
2550 | update_state_fb(struct drm_plane *plane) | |
2551 | { | |
2552 | if (plane->fb == plane->state->fb) | |
2553 | return; | |
2554 | ||
2555 | if (plane->state->fb) | |
2556 | drm_framebuffer_unreference(plane->state->fb); | |
2557 | plane->state->fb = plane->fb; | |
2558 | if (plane->state->fb) | |
2559 | drm_framebuffer_reference(plane->state->fb); | |
2560 | } | |
2561 | ||
5724dbd1 | 2562 | static void |
f6936e29 DV |
2563 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2564 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2565 | { |
2566 | struct drm_device *dev = intel_crtc->base.dev; | |
d9ceb816 | 2567 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd JB |
2568 | struct drm_crtc *c; |
2569 | struct intel_crtc *i; | |
2ff8fde1 | 2570 | struct drm_i915_gem_object *obj; |
88595ac9 | 2571 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2572 | struct drm_plane_state *plane_state = primary->state; |
88595ac9 | 2573 | struct drm_framebuffer *fb; |
484b41dd | 2574 | |
2d14030b | 2575 | if (!plane_config->fb) |
484b41dd JB |
2576 | return; |
2577 | ||
f6936e29 | 2578 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2579 | fb = &plane_config->fb->base; |
2580 | goto valid_fb; | |
f55548b5 | 2581 | } |
484b41dd | 2582 | |
2d14030b | 2583 | kfree(plane_config->fb); |
484b41dd JB |
2584 | |
2585 | /* | |
2586 | * Failed to alloc the obj, check to see if we should share | |
2587 | * an fb with another CRTC instead | |
2588 | */ | |
70e1e0ec | 2589 | for_each_crtc(dev, c) { |
484b41dd JB |
2590 | i = to_intel_crtc(c); |
2591 | ||
2592 | if (c == &intel_crtc->base) | |
2593 | continue; | |
2594 | ||
2ff8fde1 MR |
2595 | if (!i->active) |
2596 | continue; | |
2597 | ||
88595ac9 DV |
2598 | fb = c->primary->fb; |
2599 | if (!fb) | |
484b41dd JB |
2600 | continue; |
2601 | ||
88595ac9 | 2602 | obj = intel_fb_obj(fb); |
2ff8fde1 | 2603 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
88595ac9 DV |
2604 | drm_framebuffer_reference(fb); |
2605 | goto valid_fb; | |
484b41dd JB |
2606 | } |
2607 | } | |
88595ac9 DV |
2608 | |
2609 | return; | |
2610 | ||
2611 | valid_fb: | |
be5651f2 ML |
2612 | plane_state->src_x = plane_state->src_y = 0; |
2613 | plane_state->src_w = fb->width << 16; | |
2614 | plane_state->src_h = fb->height << 16; | |
2615 | ||
2616 | plane_state->crtc_x = plane_state->src_y = 0; | |
2617 | plane_state->crtc_w = fb->width; | |
2618 | plane_state->crtc_h = fb->height; | |
2619 | ||
88595ac9 DV |
2620 | obj = intel_fb_obj(fb); |
2621 | if (obj->tiling_mode != I915_TILING_NONE) | |
2622 | dev_priv->preserve_bios_swizzle = true; | |
2623 | ||
be5651f2 ML |
2624 | drm_framebuffer_reference(fb); |
2625 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2626 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
36750f28 | 2627 | intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); |
a9ff8714 | 2628 | obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit; |
46f297fb JB |
2629 | } |
2630 | ||
29b9bde6 DV |
2631 | static void i9xx_update_primary_plane(struct drm_crtc *crtc, |
2632 | struct drm_framebuffer *fb, | |
2633 | int x, int y) | |
81255565 JB |
2634 | { |
2635 | struct drm_device *dev = crtc->dev; | |
2636 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2637 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
2638 | struct drm_plane *primary = crtc->primary; |
2639 | bool visible = to_intel_plane_state(primary->state)->visible; | |
c9ba6fad | 2640 | struct drm_i915_gem_object *obj; |
81255565 | 2641 | int plane = intel_crtc->plane; |
e506a0c6 | 2642 | unsigned long linear_offset; |
81255565 | 2643 | u32 dspcntr; |
f45651ba | 2644 | u32 reg = DSPCNTR(plane); |
48404c1e | 2645 | int pixel_size; |
f45651ba | 2646 | |
b70709a6 | 2647 | if (!visible || !fb) { |
fdd508a6 VS |
2648 | I915_WRITE(reg, 0); |
2649 | if (INTEL_INFO(dev)->gen >= 4) | |
2650 | I915_WRITE(DSPSURF(plane), 0); | |
2651 | else | |
2652 | I915_WRITE(DSPADDR(plane), 0); | |
2653 | POSTING_READ(reg); | |
2654 | return; | |
2655 | } | |
2656 | ||
c9ba6fad VS |
2657 | obj = intel_fb_obj(fb); |
2658 | if (WARN_ON(obj == NULL)) | |
2659 | return; | |
2660 | ||
2661 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2662 | ||
f45651ba VS |
2663 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2664 | ||
fdd508a6 | 2665 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2666 | |
2667 | if (INTEL_INFO(dev)->gen < 4) { | |
2668 | if (intel_crtc->pipe == PIPE_B) | |
2669 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2670 | ||
2671 | /* pipesrc and dspsize control the size that is scaled from, | |
2672 | * which should always be the user's requested size. | |
2673 | */ | |
2674 | I915_WRITE(DSPSIZE(plane), | |
6e3c9717 ACO |
2675 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2676 | (intel_crtc->config->pipe_src_w - 1)); | |
f45651ba | 2677 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
2678 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2679 | I915_WRITE(PRIMSIZE(plane), | |
6e3c9717 ACO |
2680 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2681 | (intel_crtc->config->pipe_src_w - 1)); | |
c14b0485 VS |
2682 | I915_WRITE(PRIMPOS(plane), 0); |
2683 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2684 | } |
81255565 | 2685 | |
57779d06 VS |
2686 | switch (fb->pixel_format) { |
2687 | case DRM_FORMAT_C8: | |
81255565 JB |
2688 | dspcntr |= DISPPLANE_8BPP; |
2689 | break; | |
57779d06 | 2690 | case DRM_FORMAT_XRGB1555: |
57779d06 | 2691 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 2692 | break; |
57779d06 VS |
2693 | case DRM_FORMAT_RGB565: |
2694 | dspcntr |= DISPPLANE_BGRX565; | |
2695 | break; | |
2696 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
2697 | dspcntr |= DISPPLANE_BGRX888; |
2698 | break; | |
2699 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2700 | dspcntr |= DISPPLANE_RGBX888; |
2701 | break; | |
2702 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2703 | dspcntr |= DISPPLANE_BGRX101010; |
2704 | break; | |
2705 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2706 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
2707 | break; |
2708 | default: | |
baba133a | 2709 | BUG(); |
81255565 | 2710 | } |
57779d06 | 2711 | |
f45651ba VS |
2712 | if (INTEL_INFO(dev)->gen >= 4 && |
2713 | obj->tiling_mode != I915_TILING_NONE) | |
2714 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2715 | |
de1aa629 VS |
2716 | if (IS_G4X(dev)) |
2717 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2718 | ||
b9897127 | 2719 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
81255565 | 2720 | |
c2c75131 DV |
2721 | if (INTEL_INFO(dev)->gen >= 4) { |
2722 | intel_crtc->dspaddr_offset = | |
4e9a86b6 VS |
2723 | intel_gen4_compute_page_offset(dev_priv, |
2724 | &x, &y, obj->tiling_mode, | |
b9897127 | 2725 | pixel_size, |
bc752862 | 2726 | fb->pitches[0]); |
c2c75131 DV |
2727 | linear_offset -= intel_crtc->dspaddr_offset; |
2728 | } else { | |
e506a0c6 | 2729 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2730 | } |
e506a0c6 | 2731 | |
8e7d688b | 2732 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2733 | dspcntr |= DISPPLANE_ROTATE_180; |
2734 | ||
6e3c9717 ACO |
2735 | x += (intel_crtc->config->pipe_src_w - 1); |
2736 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2737 | |
2738 | /* Finding the last pixel of the last line of the display | |
2739 | data and adding to linear_offset*/ | |
2740 | linear_offset += | |
6e3c9717 ACO |
2741 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2742 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2743 | } |
2744 | ||
2db3366b PZ |
2745 | intel_crtc->adjusted_x = x; |
2746 | intel_crtc->adjusted_y = y; | |
2747 | ||
48404c1e SJ |
2748 | I915_WRITE(reg, dspcntr); |
2749 | ||
01f2c773 | 2750 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2751 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2752 | I915_WRITE(DSPSURF(plane), |
2753 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2754 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2755 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2756 | } else |
f343c5f6 | 2757 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2758 | POSTING_READ(reg); |
17638cd6 JB |
2759 | } |
2760 | ||
29b9bde6 DV |
2761 | static void ironlake_update_primary_plane(struct drm_crtc *crtc, |
2762 | struct drm_framebuffer *fb, | |
2763 | int x, int y) | |
17638cd6 JB |
2764 | { |
2765 | struct drm_device *dev = crtc->dev; | |
2766 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2767 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
2768 | struct drm_plane *primary = crtc->primary; |
2769 | bool visible = to_intel_plane_state(primary->state)->visible; | |
c9ba6fad | 2770 | struct drm_i915_gem_object *obj; |
17638cd6 | 2771 | int plane = intel_crtc->plane; |
e506a0c6 | 2772 | unsigned long linear_offset; |
17638cd6 | 2773 | u32 dspcntr; |
f45651ba | 2774 | u32 reg = DSPCNTR(plane); |
48404c1e | 2775 | int pixel_size; |
f45651ba | 2776 | |
b70709a6 | 2777 | if (!visible || !fb) { |
fdd508a6 VS |
2778 | I915_WRITE(reg, 0); |
2779 | I915_WRITE(DSPSURF(plane), 0); | |
2780 | POSTING_READ(reg); | |
2781 | return; | |
2782 | } | |
2783 | ||
c9ba6fad VS |
2784 | obj = intel_fb_obj(fb); |
2785 | if (WARN_ON(obj == NULL)) | |
2786 | return; | |
2787 | ||
2788 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2789 | ||
f45651ba VS |
2790 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2791 | ||
fdd508a6 | 2792 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2793 | |
2794 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2795 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2796 | |
57779d06 VS |
2797 | switch (fb->pixel_format) { |
2798 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2799 | dspcntr |= DISPPLANE_8BPP; |
2800 | break; | |
57779d06 VS |
2801 | case DRM_FORMAT_RGB565: |
2802 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2803 | break; |
57779d06 | 2804 | case DRM_FORMAT_XRGB8888: |
57779d06 VS |
2805 | dspcntr |= DISPPLANE_BGRX888; |
2806 | break; | |
2807 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2808 | dspcntr |= DISPPLANE_RGBX888; |
2809 | break; | |
2810 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2811 | dspcntr |= DISPPLANE_BGRX101010; |
2812 | break; | |
2813 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2814 | dspcntr |= DISPPLANE_RGBX101010; |
17638cd6 JB |
2815 | break; |
2816 | default: | |
baba133a | 2817 | BUG(); |
17638cd6 JB |
2818 | } |
2819 | ||
2820 | if (obj->tiling_mode != I915_TILING_NONE) | |
2821 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2822 | |
f45651ba | 2823 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2824 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2825 | |
b9897127 | 2826 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
c2c75131 | 2827 | intel_crtc->dspaddr_offset = |
4e9a86b6 VS |
2828 | intel_gen4_compute_page_offset(dev_priv, |
2829 | &x, &y, obj->tiling_mode, | |
b9897127 | 2830 | pixel_size, |
bc752862 | 2831 | fb->pitches[0]); |
c2c75131 | 2832 | linear_offset -= intel_crtc->dspaddr_offset; |
8e7d688b | 2833 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2834 | dspcntr |= DISPPLANE_ROTATE_180; |
2835 | ||
2836 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
6e3c9717 ACO |
2837 | x += (intel_crtc->config->pipe_src_w - 1); |
2838 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2839 | |
2840 | /* Finding the last pixel of the last line of the display | |
2841 | data and adding to linear_offset*/ | |
2842 | linear_offset += | |
6e3c9717 ACO |
2843 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2844 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2845 | } |
2846 | } | |
2847 | ||
2db3366b PZ |
2848 | intel_crtc->adjusted_x = x; |
2849 | intel_crtc->adjusted_y = y; | |
2850 | ||
48404c1e | 2851 | I915_WRITE(reg, dspcntr); |
17638cd6 | 2852 | |
01f2c773 | 2853 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2854 | I915_WRITE(DSPSURF(plane), |
2855 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2856 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2857 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2858 | } else { | |
2859 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2860 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2861 | } | |
17638cd6 | 2862 | POSTING_READ(reg); |
17638cd6 JB |
2863 | } |
2864 | ||
b321803d DL |
2865 | u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier, |
2866 | uint32_t pixel_format) | |
2867 | { | |
2868 | u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8; | |
2869 | ||
2870 | /* | |
2871 | * The stride is either expressed as a multiple of 64 bytes | |
2872 | * chunks for linear buffers or in number of tiles for tiled | |
2873 | * buffers. | |
2874 | */ | |
2875 | switch (fb_modifier) { | |
2876 | case DRM_FORMAT_MOD_NONE: | |
2877 | return 64; | |
2878 | case I915_FORMAT_MOD_X_TILED: | |
2879 | if (INTEL_INFO(dev)->gen == 2) | |
2880 | return 128; | |
2881 | return 512; | |
2882 | case I915_FORMAT_MOD_Y_TILED: | |
2883 | /* No need to check for old gens and Y tiling since this is | |
2884 | * about the display engine and those will be blocked before | |
2885 | * we get here. | |
2886 | */ | |
2887 | return 128; | |
2888 | case I915_FORMAT_MOD_Yf_TILED: | |
2889 | if (bits_per_pixel == 8) | |
2890 | return 64; | |
2891 | else | |
2892 | return 128; | |
2893 | default: | |
2894 | MISSING_CASE(fb_modifier); | |
2895 | return 64; | |
2896 | } | |
2897 | } | |
2898 | ||
121920fa | 2899 | unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane, |
dedf278c TU |
2900 | struct drm_i915_gem_object *obj, |
2901 | unsigned int plane) | |
121920fa | 2902 | { |
9abc4648 | 2903 | const struct i915_ggtt_view *view = &i915_ggtt_view_normal; |
dedf278c TU |
2904 | struct i915_vma *vma; |
2905 | unsigned char *offset; | |
121920fa TU |
2906 | |
2907 | if (intel_rotation_90_or_270(intel_plane->base.state->rotation)) | |
9abc4648 | 2908 | view = &i915_ggtt_view_rotated; |
121920fa | 2909 | |
dedf278c TU |
2910 | vma = i915_gem_obj_to_ggtt_view(obj, view); |
2911 | if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n", | |
2912 | view->type)) | |
2913 | return -1; | |
2914 | ||
2915 | offset = (unsigned char *)vma->node.start; | |
2916 | ||
2917 | if (plane == 1) { | |
2918 | offset += vma->ggtt_view.rotation_info.uv_start_page * | |
2919 | PAGE_SIZE; | |
2920 | } | |
2921 | ||
2922 | return (unsigned long)offset; | |
121920fa TU |
2923 | } |
2924 | ||
e435d6e5 ML |
2925 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
2926 | { | |
2927 | struct drm_device *dev = intel_crtc->base.dev; | |
2928 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2929 | ||
2930 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
2931 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
2932 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
2933 | } |
2934 | ||
a1b2278e CK |
2935 | /* |
2936 | * This function detaches (aka. unbinds) unused scalers in hardware | |
2937 | */ | |
0583236e | 2938 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 2939 | { |
a1b2278e CK |
2940 | struct intel_crtc_scaler_state *scaler_state; |
2941 | int i; | |
2942 | ||
a1b2278e CK |
2943 | scaler_state = &intel_crtc->config->scaler_state; |
2944 | ||
2945 | /* loop through and disable scalers that aren't in use */ | |
2946 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
2947 | if (!scaler_state->scalers[i].in_use) |
2948 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
2949 | } |
2950 | } | |
2951 | ||
6156a456 | 2952 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 2953 | { |
6156a456 | 2954 | switch (pixel_format) { |
d161cf7a | 2955 | case DRM_FORMAT_C8: |
c34ce3d1 | 2956 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 2957 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 2958 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 2959 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 2960 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 2961 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 2962 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
2963 | /* |
2964 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
2965 | * to be already pre-multiplied. We need to add a knob (or a different | |
2966 | * DRM_FORMAT) for user-space to configure that. | |
2967 | */ | |
f75fb42a | 2968 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 2969 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 2970 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 2971 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 2972 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 2973 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 2974 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 2975 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 2976 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 2977 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 2978 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 2979 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 2980 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 2981 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 2982 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 2983 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 2984 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 2985 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 2986 | default: |
4249eeef | 2987 | MISSING_CASE(pixel_format); |
70d21f0e | 2988 | } |
8cfcba41 | 2989 | |
c34ce3d1 | 2990 | return 0; |
6156a456 | 2991 | } |
70d21f0e | 2992 | |
6156a456 CK |
2993 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
2994 | { | |
6156a456 | 2995 | switch (fb_modifier) { |
30af77c4 | 2996 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 2997 | break; |
30af77c4 | 2998 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 2999 | return PLANE_CTL_TILED_X; |
b321803d | 3000 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 3001 | return PLANE_CTL_TILED_Y; |
b321803d | 3002 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 3003 | return PLANE_CTL_TILED_YF; |
70d21f0e | 3004 | default: |
6156a456 | 3005 | MISSING_CASE(fb_modifier); |
70d21f0e | 3006 | } |
8cfcba41 | 3007 | |
c34ce3d1 | 3008 | return 0; |
6156a456 | 3009 | } |
70d21f0e | 3010 | |
6156a456 CK |
3011 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
3012 | { | |
3b7a5119 | 3013 | switch (rotation) { |
6156a456 CK |
3014 | case BIT(DRM_ROTATE_0): |
3015 | break; | |
1e8df167 SJ |
3016 | /* |
3017 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
3018 | * while i915 HW rotation is clockwise, thats why this swapping. | |
3019 | */ | |
3b7a5119 | 3020 | case BIT(DRM_ROTATE_90): |
1e8df167 | 3021 | return PLANE_CTL_ROTATE_270; |
3b7a5119 | 3022 | case BIT(DRM_ROTATE_180): |
c34ce3d1 | 3023 | return PLANE_CTL_ROTATE_180; |
3b7a5119 | 3024 | case BIT(DRM_ROTATE_270): |
1e8df167 | 3025 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
3026 | default: |
3027 | MISSING_CASE(rotation); | |
3028 | } | |
3029 | ||
c34ce3d1 | 3030 | return 0; |
6156a456 CK |
3031 | } |
3032 | ||
3033 | static void skylake_update_primary_plane(struct drm_crtc *crtc, | |
3034 | struct drm_framebuffer *fb, | |
3035 | int x, int y) | |
3036 | { | |
3037 | struct drm_device *dev = crtc->dev; | |
3038 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3039 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
3040 | struct drm_plane *plane = crtc->primary; |
3041 | bool visible = to_intel_plane_state(plane->state)->visible; | |
6156a456 CK |
3042 | struct drm_i915_gem_object *obj; |
3043 | int pipe = intel_crtc->pipe; | |
3044 | u32 plane_ctl, stride_div, stride; | |
3045 | u32 tile_height, plane_offset, plane_size; | |
3046 | unsigned int rotation; | |
3047 | int x_offset, y_offset; | |
3048 | unsigned long surf_addr; | |
6156a456 CK |
3049 | struct intel_crtc_state *crtc_state = intel_crtc->config; |
3050 | struct intel_plane_state *plane_state; | |
3051 | int src_x = 0, src_y = 0, src_w = 0, src_h = 0; | |
3052 | int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0; | |
3053 | int scaler_id = -1; | |
3054 | ||
6156a456 CK |
3055 | plane_state = to_intel_plane_state(plane->state); |
3056 | ||
b70709a6 | 3057 | if (!visible || !fb) { |
6156a456 CK |
3058 | I915_WRITE(PLANE_CTL(pipe, 0), 0); |
3059 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
3060 | POSTING_READ(PLANE_CTL(pipe, 0)); | |
3061 | return; | |
3b7a5119 | 3062 | } |
70d21f0e | 3063 | |
6156a456 CK |
3064 | plane_ctl = PLANE_CTL_ENABLE | |
3065 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3066 | PLANE_CTL_PIPE_CSC_ENABLE; | |
3067 | ||
3068 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); | |
3069 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
3070 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
3071 | ||
3072 | rotation = plane->state->rotation; | |
3073 | plane_ctl |= skl_plane_ctl_rotation(rotation); | |
3074 | ||
b321803d DL |
3075 | obj = intel_fb_obj(fb); |
3076 | stride_div = intel_fb_stride_alignment(dev, fb->modifier[0], | |
3077 | fb->pixel_format); | |
dedf278c | 3078 | surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0); |
3b7a5119 | 3079 | |
6156a456 CK |
3080 | /* |
3081 | * FIXME: intel_plane_state->src, dst aren't set when transitional | |
3082 | * update_plane helpers are called from legacy paths. | |
3083 | * Once full atomic crtc is available, below check can be avoided. | |
3084 | */ | |
3085 | if (drm_rect_width(&plane_state->src)) { | |
3086 | scaler_id = plane_state->scaler_id; | |
3087 | src_x = plane_state->src.x1 >> 16; | |
3088 | src_y = plane_state->src.y1 >> 16; | |
3089 | src_w = drm_rect_width(&plane_state->src) >> 16; | |
3090 | src_h = drm_rect_height(&plane_state->src) >> 16; | |
3091 | dst_x = plane_state->dst.x1; | |
3092 | dst_y = plane_state->dst.y1; | |
3093 | dst_w = drm_rect_width(&plane_state->dst); | |
3094 | dst_h = drm_rect_height(&plane_state->dst); | |
3095 | ||
3096 | WARN_ON(x != src_x || y != src_y); | |
3097 | } else { | |
3098 | src_w = intel_crtc->config->pipe_src_w; | |
3099 | src_h = intel_crtc->config->pipe_src_h; | |
3100 | } | |
3101 | ||
3b7a5119 SJ |
3102 | if (intel_rotation_90_or_270(rotation)) { |
3103 | /* stride = Surface height in tiles */ | |
2614f17d | 3104 | tile_height = intel_tile_height(dev, fb->pixel_format, |
fe47ea0c | 3105 | fb->modifier[0], 0); |
3b7a5119 | 3106 | stride = DIV_ROUND_UP(fb->height, tile_height); |
6156a456 | 3107 | x_offset = stride * tile_height - y - src_h; |
3b7a5119 | 3108 | y_offset = x; |
6156a456 | 3109 | plane_size = (src_w - 1) << 16 | (src_h - 1); |
3b7a5119 SJ |
3110 | } else { |
3111 | stride = fb->pitches[0] / stride_div; | |
3112 | x_offset = x; | |
3113 | y_offset = y; | |
6156a456 | 3114 | plane_size = (src_h - 1) << 16 | (src_w - 1); |
3b7a5119 SJ |
3115 | } |
3116 | plane_offset = y_offset << 16 | x_offset; | |
b321803d | 3117 | |
2db3366b PZ |
3118 | intel_crtc->adjusted_x = x_offset; |
3119 | intel_crtc->adjusted_y = y_offset; | |
3120 | ||
70d21f0e | 3121 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
3b7a5119 SJ |
3122 | I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); |
3123 | I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); | |
3124 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
6156a456 CK |
3125 | |
3126 | if (scaler_id >= 0) { | |
3127 | uint32_t ps_ctrl = 0; | |
3128 | ||
3129 | WARN_ON(!dst_w || !dst_h); | |
3130 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | | |
3131 | crtc_state->scaler_state.scalers[scaler_id].mode; | |
3132 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3133 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3134 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3135 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3136 | I915_WRITE(PLANE_POS(pipe, 0), 0); | |
3137 | } else { | |
3138 | I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); | |
3139 | } | |
3140 | ||
121920fa | 3141 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
70d21f0e DL |
3142 | |
3143 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3144 | } | |
3145 | ||
17638cd6 JB |
3146 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3147 | static int | |
3148 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3149 | int x, int y, enum mode_set_atomic state) | |
3150 | { | |
3151 | struct drm_device *dev = crtc->dev; | |
3152 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 3153 | |
ff2a3117 | 3154 | if (dev_priv->fbc.disable_fbc) |
7733b49b | 3155 | dev_priv->fbc.disable_fbc(dev_priv); |
81255565 | 3156 | |
29b9bde6 DV |
3157 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
3158 | ||
3159 | return 0; | |
81255565 JB |
3160 | } |
3161 | ||
7514747d | 3162 | static void intel_complete_page_flips(struct drm_device *dev) |
96a02917 | 3163 | { |
96a02917 VS |
3164 | struct drm_crtc *crtc; |
3165 | ||
70e1e0ec | 3166 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3167 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3168 | enum plane plane = intel_crtc->plane; | |
3169 | ||
3170 | intel_prepare_page_flip(dev, plane); | |
3171 | intel_finish_page_flip_plane(dev, plane); | |
3172 | } | |
7514747d VS |
3173 | } |
3174 | ||
3175 | static void intel_update_primary_planes(struct drm_device *dev) | |
3176 | { | |
7514747d | 3177 | struct drm_crtc *crtc; |
96a02917 | 3178 | |
70e1e0ec | 3179 | for_each_crtc(dev, crtc) { |
11c22da6 ML |
3180 | struct intel_plane *plane = to_intel_plane(crtc->primary); |
3181 | struct intel_plane_state *plane_state; | |
96a02917 | 3182 | |
11c22da6 ML |
3183 | drm_modeset_lock_crtc(crtc, &plane->base); |
3184 | ||
3185 | plane_state = to_intel_plane_state(plane->base.state); | |
3186 | ||
3187 | if (plane_state->base.fb) | |
3188 | plane->commit_plane(&plane->base, plane_state); | |
3189 | ||
3190 | drm_modeset_unlock_crtc(crtc); | |
96a02917 VS |
3191 | } |
3192 | } | |
3193 | ||
7514747d VS |
3194 | void intel_prepare_reset(struct drm_device *dev) |
3195 | { | |
3196 | /* no reset support for gen2 */ | |
3197 | if (IS_GEN2(dev)) | |
3198 | return; | |
3199 | ||
3200 | /* reset doesn't touch the display */ | |
3201 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
3202 | return; | |
3203 | ||
3204 | drm_modeset_lock_all(dev); | |
f98ce92f VS |
3205 | /* |
3206 | * Disabling the crtcs gracefully seems nicer. Also the | |
3207 | * g33 docs say we should at least disable all the planes. | |
3208 | */ | |
6b72d486 | 3209 | intel_display_suspend(dev); |
7514747d VS |
3210 | } |
3211 | ||
3212 | void intel_finish_reset(struct drm_device *dev) | |
3213 | { | |
3214 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3215 | ||
3216 | /* | |
3217 | * Flips in the rings will be nuked by the reset, | |
3218 | * so complete all pending flips so that user space | |
3219 | * will get its events and not get stuck. | |
3220 | */ | |
3221 | intel_complete_page_flips(dev); | |
3222 | ||
3223 | /* no reset support for gen2 */ | |
3224 | if (IS_GEN2(dev)) | |
3225 | return; | |
3226 | ||
3227 | /* reset doesn't touch the display */ | |
3228 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { | |
3229 | /* | |
3230 | * Flips in the rings have been nuked by the reset, | |
3231 | * so update the base address of all primary | |
3232 | * planes to the the last fb to make sure we're | |
3233 | * showing the correct fb after a reset. | |
11c22da6 ML |
3234 | * |
3235 | * FIXME: Atomic will make this obsolete since we won't schedule | |
3236 | * CS-based flips (which might get lost in gpu resets) any more. | |
7514747d VS |
3237 | */ |
3238 | intel_update_primary_planes(dev); | |
3239 | return; | |
3240 | } | |
3241 | ||
3242 | /* | |
3243 | * The display has been reset as well, | |
3244 | * so need a full re-initialization. | |
3245 | */ | |
3246 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3247 | intel_runtime_pm_enable_interrupts(dev_priv); | |
3248 | ||
3249 | intel_modeset_init_hw(dev); | |
3250 | ||
3251 | spin_lock_irq(&dev_priv->irq_lock); | |
3252 | if (dev_priv->display.hpd_irq_setup) | |
3253 | dev_priv->display.hpd_irq_setup(dev); | |
3254 | spin_unlock_irq(&dev_priv->irq_lock); | |
3255 | ||
043e9bda | 3256 | intel_display_resume(dev); |
7514747d VS |
3257 | |
3258 | intel_hpd_init(dev_priv); | |
3259 | ||
3260 | drm_modeset_unlock_all(dev); | |
3261 | } | |
3262 | ||
2e2f351d | 3263 | static void |
14667a4b CW |
3264 | intel_finish_fb(struct drm_framebuffer *old_fb) |
3265 | { | |
2ff8fde1 | 3266 | struct drm_i915_gem_object *obj = intel_fb_obj(old_fb); |
2e2f351d | 3267 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
14667a4b CW |
3268 | bool was_interruptible = dev_priv->mm.interruptible; |
3269 | int ret; | |
3270 | ||
14667a4b CW |
3271 | /* Big Hammer, we also need to ensure that any pending |
3272 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
3273 | * current scanout is retired before unpinning the old | |
2e2f351d CW |
3274 | * framebuffer. Note that we rely on userspace rendering |
3275 | * into the buffer attached to the pipe they are waiting | |
3276 | * on. If not, userspace generates a GPU hang with IPEHR | |
3277 | * point to the MI_WAIT_FOR_EVENT. | |
14667a4b CW |
3278 | * |
3279 | * This should only fail upon a hung GPU, in which case we | |
3280 | * can safely continue. | |
3281 | */ | |
3282 | dev_priv->mm.interruptible = false; | |
2e2f351d | 3283 | ret = i915_gem_object_wait_rendering(obj, true); |
14667a4b CW |
3284 | dev_priv->mm.interruptible = was_interruptible; |
3285 | ||
2e2f351d | 3286 | WARN_ON(ret); |
14667a4b CW |
3287 | } |
3288 | ||
7d5e3799 CW |
3289 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3290 | { | |
3291 | struct drm_device *dev = crtc->dev; | |
3292 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3293 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7d5e3799 CW |
3294 | bool pending; |
3295 | ||
3296 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
3297 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
3298 | return false; | |
3299 | ||
5e2d7afc | 3300 | spin_lock_irq(&dev->event_lock); |
7d5e3799 | 3301 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
5e2d7afc | 3302 | spin_unlock_irq(&dev->event_lock); |
7d5e3799 CW |
3303 | |
3304 | return pending; | |
3305 | } | |
3306 | ||
bfd16b2a ML |
3307 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
3308 | struct intel_crtc_state *old_crtc_state) | |
e30e8f75 GP |
3309 | { |
3310 | struct drm_device *dev = crtc->base.dev; | |
3311 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bfd16b2a ML |
3312 | struct intel_crtc_state *pipe_config = |
3313 | to_intel_crtc_state(crtc->base.state); | |
e30e8f75 | 3314 | |
bfd16b2a ML |
3315 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
3316 | crtc->base.mode = crtc->base.state->mode; | |
3317 | ||
3318 | DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n", | |
3319 | old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h, | |
3320 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
e30e8f75 | 3321 | |
44522d85 ML |
3322 | if (HAS_DDI(dev)) |
3323 | intel_set_pipe_csc(&crtc->base); | |
3324 | ||
e30e8f75 GP |
3325 | /* |
3326 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3327 | * that in compute_mode_changes we check the native mode (not the pfit | |
3328 | * mode) to see if we can flip rather than do a full mode set. In the | |
3329 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3330 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3331 | * sized surface. | |
e30e8f75 GP |
3332 | */ |
3333 | ||
e30e8f75 | 3334 | I915_WRITE(PIPESRC(crtc->pipe), |
bfd16b2a ML |
3335 | ((pipe_config->pipe_src_w - 1) << 16) | |
3336 | (pipe_config->pipe_src_h - 1)); | |
3337 | ||
3338 | /* on skylake this is done by detaching scalers */ | |
3339 | if (INTEL_INFO(dev)->gen >= 9) { | |
3340 | skl_detach_scalers(crtc); | |
3341 | ||
3342 | if (pipe_config->pch_pfit.enabled) | |
3343 | skylake_pfit_enable(crtc); | |
3344 | } else if (HAS_PCH_SPLIT(dev)) { | |
3345 | if (pipe_config->pch_pfit.enabled) | |
3346 | ironlake_pfit_enable(crtc); | |
3347 | else if (old_crtc_state->pch_pfit.enabled) | |
3348 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3349 | } |
e30e8f75 GP |
3350 | } |
3351 | ||
5e84e1a4 ZW |
3352 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3353 | { | |
3354 | struct drm_device *dev = crtc->dev; | |
3355 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3356 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3357 | int pipe = intel_crtc->pipe; | |
3358 | u32 reg, temp; | |
3359 | ||
3360 | /* enable normal train */ | |
3361 | reg = FDI_TX_CTL(pipe); | |
3362 | temp = I915_READ(reg); | |
61e499bf | 3363 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3364 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3365 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3366 | } else { |
3367 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3368 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3369 | } |
5e84e1a4 ZW |
3370 | I915_WRITE(reg, temp); |
3371 | ||
3372 | reg = FDI_RX_CTL(pipe); | |
3373 | temp = I915_READ(reg); | |
3374 | if (HAS_PCH_CPT(dev)) { | |
3375 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3376 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3377 | } else { | |
3378 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3379 | temp |= FDI_LINK_TRAIN_NONE; | |
3380 | } | |
3381 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3382 | ||
3383 | /* wait one idle pattern time */ | |
3384 | POSTING_READ(reg); | |
3385 | udelay(1000); | |
357555c0 JB |
3386 | |
3387 | /* IVB wants error correction enabled */ | |
3388 | if (IS_IVYBRIDGE(dev)) | |
3389 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3390 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3391 | } |
3392 | ||
8db9d77b ZW |
3393 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3394 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3395 | { | |
3396 | struct drm_device *dev = crtc->dev; | |
3397 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3398 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3399 | int pipe = intel_crtc->pipe; | |
5eddb70b | 3400 | u32 reg, temp, tries; |
8db9d77b | 3401 | |
1c8562f6 | 3402 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3403 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3404 | |
e1a44743 AJ |
3405 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3406 | for train result */ | |
5eddb70b CW |
3407 | reg = FDI_RX_IMR(pipe); |
3408 | temp = I915_READ(reg); | |
e1a44743 AJ |
3409 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3410 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3411 | I915_WRITE(reg, temp); |
3412 | I915_READ(reg); | |
e1a44743 AJ |
3413 | udelay(150); |
3414 | ||
8db9d77b | 3415 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3416 | reg = FDI_TX_CTL(pipe); |
3417 | temp = I915_READ(reg); | |
627eb5a3 | 3418 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3419 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3420 | temp &= ~FDI_LINK_TRAIN_NONE; |
3421 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3422 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3423 | |
5eddb70b CW |
3424 | reg = FDI_RX_CTL(pipe); |
3425 | temp = I915_READ(reg); | |
8db9d77b ZW |
3426 | temp &= ~FDI_LINK_TRAIN_NONE; |
3427 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3428 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3429 | ||
3430 | POSTING_READ(reg); | |
8db9d77b ZW |
3431 | udelay(150); |
3432 | ||
5b2adf89 | 3433 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3434 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3435 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3436 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3437 | |
5eddb70b | 3438 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3439 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3440 | temp = I915_READ(reg); |
8db9d77b ZW |
3441 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3442 | ||
3443 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3444 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3445 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3446 | break; |
3447 | } | |
8db9d77b | 3448 | } |
e1a44743 | 3449 | if (tries == 5) |
5eddb70b | 3450 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3451 | |
3452 | /* Train 2 */ | |
5eddb70b CW |
3453 | reg = FDI_TX_CTL(pipe); |
3454 | temp = I915_READ(reg); | |
8db9d77b ZW |
3455 | temp &= ~FDI_LINK_TRAIN_NONE; |
3456 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3457 | I915_WRITE(reg, temp); |
8db9d77b | 3458 | |
5eddb70b CW |
3459 | reg = FDI_RX_CTL(pipe); |
3460 | temp = I915_READ(reg); | |
8db9d77b ZW |
3461 | temp &= ~FDI_LINK_TRAIN_NONE; |
3462 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3463 | I915_WRITE(reg, temp); |
8db9d77b | 3464 | |
5eddb70b CW |
3465 | POSTING_READ(reg); |
3466 | udelay(150); | |
8db9d77b | 3467 | |
5eddb70b | 3468 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3469 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3470 | temp = I915_READ(reg); |
8db9d77b ZW |
3471 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3472 | ||
3473 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3474 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3475 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3476 | break; | |
3477 | } | |
8db9d77b | 3478 | } |
e1a44743 | 3479 | if (tries == 5) |
5eddb70b | 3480 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3481 | |
3482 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3483 | |
8db9d77b ZW |
3484 | } |
3485 | ||
0206e353 | 3486 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3487 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3488 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3489 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3490 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3491 | }; | |
3492 | ||
3493 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3494 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3495 | { | |
3496 | struct drm_device *dev = crtc->dev; | |
3497 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3498 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3499 | int pipe = intel_crtc->pipe; | |
fa37d39e | 3500 | u32 reg, temp, i, retry; |
8db9d77b | 3501 | |
e1a44743 AJ |
3502 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3503 | for train result */ | |
5eddb70b CW |
3504 | reg = FDI_RX_IMR(pipe); |
3505 | temp = I915_READ(reg); | |
e1a44743 AJ |
3506 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3507 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3508 | I915_WRITE(reg, temp); |
3509 | ||
3510 | POSTING_READ(reg); | |
e1a44743 AJ |
3511 | udelay(150); |
3512 | ||
8db9d77b | 3513 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3514 | reg = FDI_TX_CTL(pipe); |
3515 | temp = I915_READ(reg); | |
627eb5a3 | 3516 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3517 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3518 | temp &= ~FDI_LINK_TRAIN_NONE; |
3519 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3520 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3521 | /* SNB-B */ | |
3522 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3523 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3524 | |
d74cf324 DV |
3525 | I915_WRITE(FDI_RX_MISC(pipe), |
3526 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3527 | ||
5eddb70b CW |
3528 | reg = FDI_RX_CTL(pipe); |
3529 | temp = I915_READ(reg); | |
8db9d77b ZW |
3530 | if (HAS_PCH_CPT(dev)) { |
3531 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3532 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3533 | } else { | |
3534 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3535 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3536 | } | |
5eddb70b CW |
3537 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3538 | ||
3539 | POSTING_READ(reg); | |
8db9d77b ZW |
3540 | udelay(150); |
3541 | ||
0206e353 | 3542 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3543 | reg = FDI_TX_CTL(pipe); |
3544 | temp = I915_READ(reg); | |
8db9d77b ZW |
3545 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3546 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3547 | I915_WRITE(reg, temp); |
3548 | ||
3549 | POSTING_READ(reg); | |
8db9d77b ZW |
3550 | udelay(500); |
3551 | ||
fa37d39e SP |
3552 | for (retry = 0; retry < 5; retry++) { |
3553 | reg = FDI_RX_IIR(pipe); | |
3554 | temp = I915_READ(reg); | |
3555 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3556 | if (temp & FDI_RX_BIT_LOCK) { | |
3557 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3558 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3559 | break; | |
3560 | } | |
3561 | udelay(50); | |
8db9d77b | 3562 | } |
fa37d39e SP |
3563 | if (retry < 5) |
3564 | break; | |
8db9d77b ZW |
3565 | } |
3566 | if (i == 4) | |
5eddb70b | 3567 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3568 | |
3569 | /* Train 2 */ | |
5eddb70b CW |
3570 | reg = FDI_TX_CTL(pipe); |
3571 | temp = I915_READ(reg); | |
8db9d77b ZW |
3572 | temp &= ~FDI_LINK_TRAIN_NONE; |
3573 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3574 | if (IS_GEN6(dev)) { | |
3575 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3576 | /* SNB-B */ | |
3577 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3578 | } | |
5eddb70b | 3579 | I915_WRITE(reg, temp); |
8db9d77b | 3580 | |
5eddb70b CW |
3581 | reg = FDI_RX_CTL(pipe); |
3582 | temp = I915_READ(reg); | |
8db9d77b ZW |
3583 | if (HAS_PCH_CPT(dev)) { |
3584 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3585 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3586 | } else { | |
3587 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3588 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3589 | } | |
5eddb70b CW |
3590 | I915_WRITE(reg, temp); |
3591 | ||
3592 | POSTING_READ(reg); | |
8db9d77b ZW |
3593 | udelay(150); |
3594 | ||
0206e353 | 3595 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3596 | reg = FDI_TX_CTL(pipe); |
3597 | temp = I915_READ(reg); | |
8db9d77b ZW |
3598 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3599 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3600 | I915_WRITE(reg, temp); |
3601 | ||
3602 | POSTING_READ(reg); | |
8db9d77b ZW |
3603 | udelay(500); |
3604 | ||
fa37d39e SP |
3605 | for (retry = 0; retry < 5; retry++) { |
3606 | reg = FDI_RX_IIR(pipe); | |
3607 | temp = I915_READ(reg); | |
3608 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3609 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3610 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3611 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3612 | break; | |
3613 | } | |
3614 | udelay(50); | |
8db9d77b | 3615 | } |
fa37d39e SP |
3616 | if (retry < 5) |
3617 | break; | |
8db9d77b ZW |
3618 | } |
3619 | if (i == 4) | |
5eddb70b | 3620 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3621 | |
3622 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3623 | } | |
3624 | ||
357555c0 JB |
3625 | /* Manual link training for Ivy Bridge A0 parts */ |
3626 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3627 | { | |
3628 | struct drm_device *dev = crtc->dev; | |
3629 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3630 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3631 | int pipe = intel_crtc->pipe; | |
139ccd3f | 3632 | u32 reg, temp, i, j; |
357555c0 JB |
3633 | |
3634 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3635 | for train result */ | |
3636 | reg = FDI_RX_IMR(pipe); | |
3637 | temp = I915_READ(reg); | |
3638 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3639 | temp &= ~FDI_RX_BIT_LOCK; | |
3640 | I915_WRITE(reg, temp); | |
3641 | ||
3642 | POSTING_READ(reg); | |
3643 | udelay(150); | |
3644 | ||
01a415fd DV |
3645 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3646 | I915_READ(FDI_RX_IIR(pipe))); | |
3647 | ||
139ccd3f JB |
3648 | /* Try each vswing and preemphasis setting twice before moving on */ |
3649 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3650 | /* disable first in case we need to retry */ | |
3651 | reg = FDI_TX_CTL(pipe); | |
3652 | temp = I915_READ(reg); | |
3653 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3654 | temp &= ~FDI_TX_ENABLE; | |
3655 | I915_WRITE(reg, temp); | |
357555c0 | 3656 | |
139ccd3f JB |
3657 | reg = FDI_RX_CTL(pipe); |
3658 | temp = I915_READ(reg); | |
3659 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3660 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3661 | temp &= ~FDI_RX_ENABLE; | |
3662 | I915_WRITE(reg, temp); | |
357555c0 | 3663 | |
139ccd3f | 3664 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3665 | reg = FDI_TX_CTL(pipe); |
3666 | temp = I915_READ(reg); | |
139ccd3f | 3667 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3668 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 3669 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3670 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3671 | temp |= snb_b_fdi_train_param[j/2]; |
3672 | temp |= FDI_COMPOSITE_SYNC; | |
3673 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3674 | |
139ccd3f JB |
3675 | I915_WRITE(FDI_RX_MISC(pipe), |
3676 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3677 | |
139ccd3f | 3678 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3679 | temp = I915_READ(reg); |
139ccd3f JB |
3680 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3681 | temp |= FDI_COMPOSITE_SYNC; | |
3682 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3683 | |
139ccd3f JB |
3684 | POSTING_READ(reg); |
3685 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3686 | |
139ccd3f JB |
3687 | for (i = 0; i < 4; i++) { |
3688 | reg = FDI_RX_IIR(pipe); | |
3689 | temp = I915_READ(reg); | |
3690 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3691 | |
139ccd3f JB |
3692 | if (temp & FDI_RX_BIT_LOCK || |
3693 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3694 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3695 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3696 | i); | |
3697 | break; | |
3698 | } | |
3699 | udelay(1); /* should be 0.5us */ | |
3700 | } | |
3701 | if (i == 4) { | |
3702 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3703 | continue; | |
3704 | } | |
357555c0 | 3705 | |
139ccd3f | 3706 | /* Train 2 */ |
357555c0 JB |
3707 | reg = FDI_TX_CTL(pipe); |
3708 | temp = I915_READ(reg); | |
139ccd3f JB |
3709 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3710 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3711 | I915_WRITE(reg, temp); | |
3712 | ||
3713 | reg = FDI_RX_CTL(pipe); | |
3714 | temp = I915_READ(reg); | |
3715 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3716 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3717 | I915_WRITE(reg, temp); |
3718 | ||
3719 | POSTING_READ(reg); | |
139ccd3f | 3720 | udelay(2); /* should be 1.5us */ |
357555c0 | 3721 | |
139ccd3f JB |
3722 | for (i = 0; i < 4; i++) { |
3723 | reg = FDI_RX_IIR(pipe); | |
3724 | temp = I915_READ(reg); | |
3725 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3726 | |
139ccd3f JB |
3727 | if (temp & FDI_RX_SYMBOL_LOCK || |
3728 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3729 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3730 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3731 | i); | |
3732 | goto train_done; | |
3733 | } | |
3734 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3735 | } |
139ccd3f JB |
3736 | if (i == 4) |
3737 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3738 | } |
357555c0 | 3739 | |
139ccd3f | 3740 | train_done: |
357555c0 JB |
3741 | DRM_DEBUG_KMS("FDI train done.\n"); |
3742 | } | |
3743 | ||
88cefb6c | 3744 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3745 | { |
88cefb6c | 3746 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3747 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3748 | int pipe = intel_crtc->pipe; |
5eddb70b | 3749 | u32 reg, temp; |
79e53945 | 3750 | |
c64e311e | 3751 | |
c98e9dcf | 3752 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3753 | reg = FDI_RX_CTL(pipe); |
3754 | temp = I915_READ(reg); | |
627eb5a3 | 3755 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3756 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3757 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3758 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3759 | ||
3760 | POSTING_READ(reg); | |
c98e9dcf JB |
3761 | udelay(200); |
3762 | ||
3763 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3764 | temp = I915_READ(reg); |
3765 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3766 | ||
3767 | POSTING_READ(reg); | |
c98e9dcf JB |
3768 | udelay(200); |
3769 | ||
20749730 PZ |
3770 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3771 | reg = FDI_TX_CTL(pipe); | |
3772 | temp = I915_READ(reg); | |
3773 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3774 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3775 | |
20749730 PZ |
3776 | POSTING_READ(reg); |
3777 | udelay(100); | |
6be4a607 | 3778 | } |
0e23b99d JB |
3779 | } |
3780 | ||
88cefb6c DV |
3781 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3782 | { | |
3783 | struct drm_device *dev = intel_crtc->base.dev; | |
3784 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3785 | int pipe = intel_crtc->pipe; | |
3786 | u32 reg, temp; | |
3787 | ||
3788 | /* Switch from PCDclk to Rawclk */ | |
3789 | reg = FDI_RX_CTL(pipe); | |
3790 | temp = I915_READ(reg); | |
3791 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3792 | ||
3793 | /* Disable CPU FDI TX PLL */ | |
3794 | reg = FDI_TX_CTL(pipe); | |
3795 | temp = I915_READ(reg); | |
3796 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3797 | ||
3798 | POSTING_READ(reg); | |
3799 | udelay(100); | |
3800 | ||
3801 | reg = FDI_RX_CTL(pipe); | |
3802 | temp = I915_READ(reg); | |
3803 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3804 | ||
3805 | /* Wait for the clocks to turn off. */ | |
3806 | POSTING_READ(reg); | |
3807 | udelay(100); | |
3808 | } | |
3809 | ||
0fc932b8 JB |
3810 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3811 | { | |
3812 | struct drm_device *dev = crtc->dev; | |
3813 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3814 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3815 | int pipe = intel_crtc->pipe; | |
3816 | u32 reg, temp; | |
3817 | ||
3818 | /* disable CPU FDI tx and PCH FDI rx */ | |
3819 | reg = FDI_TX_CTL(pipe); | |
3820 | temp = I915_READ(reg); | |
3821 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3822 | POSTING_READ(reg); | |
3823 | ||
3824 | reg = FDI_RX_CTL(pipe); | |
3825 | temp = I915_READ(reg); | |
3826 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3827 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3828 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3829 | ||
3830 | POSTING_READ(reg); | |
3831 | udelay(100); | |
3832 | ||
3833 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3834 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3835 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3836 | |
3837 | /* still set train pattern 1 */ | |
3838 | reg = FDI_TX_CTL(pipe); | |
3839 | temp = I915_READ(reg); | |
3840 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3841 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3842 | I915_WRITE(reg, temp); | |
3843 | ||
3844 | reg = FDI_RX_CTL(pipe); | |
3845 | temp = I915_READ(reg); | |
3846 | if (HAS_PCH_CPT(dev)) { | |
3847 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3848 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3849 | } else { | |
3850 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3851 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3852 | } | |
3853 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3854 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3855 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3856 | I915_WRITE(reg, temp); |
3857 | ||
3858 | POSTING_READ(reg); | |
3859 | udelay(100); | |
3860 | } | |
3861 | ||
5dce5b93 CW |
3862 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3863 | { | |
3864 | struct intel_crtc *crtc; | |
3865 | ||
3866 | /* Note that we don't need to be called with mode_config.lock here | |
3867 | * as our list of CRTC objects is static for the lifetime of the | |
3868 | * device and so cannot disappear as we iterate. Similarly, we can | |
3869 | * happily treat the predicates as racy, atomic checks as userspace | |
3870 | * cannot claim and pin a new fb without at least acquring the | |
3871 | * struct_mutex and so serialising with us. | |
3872 | */ | |
d3fcc808 | 3873 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3874 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3875 | continue; | |
3876 | ||
3877 | if (crtc->unpin_work) | |
3878 | intel_wait_for_vblank(dev, crtc->pipe); | |
3879 | ||
3880 | return true; | |
3881 | } | |
3882 | ||
3883 | return false; | |
3884 | } | |
3885 | ||
d6bbafa1 CW |
3886 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
3887 | { | |
3888 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
3889 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
3890 | ||
3891 | /* ensure that the unpin work is consistent wrt ->pending. */ | |
3892 | smp_rmb(); | |
3893 | intel_crtc->unpin_work = NULL; | |
3894 | ||
3895 | if (work->event) | |
3896 | drm_send_vblank_event(intel_crtc->base.dev, | |
3897 | intel_crtc->pipe, | |
3898 | work->event); | |
3899 | ||
3900 | drm_crtc_vblank_put(&intel_crtc->base); | |
3901 | ||
3902 | wake_up_all(&dev_priv->pending_flip_queue); | |
3903 | queue_work(dev_priv->wq, &work->work); | |
3904 | ||
3905 | trace_i915_flip_complete(intel_crtc->plane, | |
3906 | work->pending_flip_obj); | |
3907 | } | |
3908 | ||
46a55d30 | 3909 | void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3910 | { |
0f91128d | 3911 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3912 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 | 3913 | |
2c10d571 | 3914 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
9c787942 CW |
3915 | if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue, |
3916 | !intel_crtc_has_pending_flip(crtc), | |
3917 | 60*HZ) == 0)) { | |
3918 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2c10d571 | 3919 | |
5e2d7afc | 3920 | spin_lock_irq(&dev->event_lock); |
9c787942 CW |
3921 | if (intel_crtc->unpin_work) { |
3922 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
3923 | page_flip_completed(intel_crtc); | |
3924 | } | |
5e2d7afc | 3925 | spin_unlock_irq(&dev->event_lock); |
9c787942 | 3926 | } |
5bb61643 | 3927 | |
975d568a CW |
3928 | if (crtc->primary->fb) { |
3929 | mutex_lock(&dev->struct_mutex); | |
3930 | intel_finish_fb(crtc->primary->fb); | |
3931 | mutex_unlock(&dev->struct_mutex); | |
3932 | } | |
e6c3a2a6 CW |
3933 | } |
3934 | ||
e615efe4 ED |
3935 | /* Program iCLKIP clock to the desired frequency */ |
3936 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3937 | { | |
3938 | struct drm_device *dev = crtc->dev; | |
3939 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 3940 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
3941 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3942 | u32 temp; | |
3943 | ||
a580516d | 3944 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 3945 | |
e615efe4 ED |
3946 | /* It is necessary to ungate the pixclk gate prior to programming |
3947 | * the divisors, and gate it back when it is done. | |
3948 | */ | |
3949 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3950 | ||
3951 | /* Disable SSCCTL */ | |
3952 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
3953 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
3954 | SBI_SSCCTL_DISABLE, | |
3955 | SBI_ICLK); | |
e615efe4 ED |
3956 | |
3957 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3958 | if (clock == 20000) { |
e615efe4 ED |
3959 | auxdiv = 1; |
3960 | divsel = 0x41; | |
3961 | phaseinc = 0x20; | |
3962 | } else { | |
3963 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3964 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3965 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3966 | * convert the virtual clock precision to KHz here for higher |
3967 | * precision. | |
3968 | */ | |
3969 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3970 | u32 iclk_pi_range = 64; | |
3971 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3972 | ||
12d7ceed | 3973 | desired_divisor = (iclk_virtual_root_freq / clock); |
e615efe4 ED |
3974 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3975 | pi_value = desired_divisor % iclk_pi_range; | |
3976 | ||
3977 | auxdiv = 0; | |
3978 | divsel = msb_divisor_value - 2; | |
3979 | phaseinc = pi_value; | |
3980 | } | |
3981 | ||
3982 | /* This should not happen with any sane values */ | |
3983 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3984 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3985 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3986 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3987 | ||
3988 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3989 | clock, |
e615efe4 ED |
3990 | auxdiv, |
3991 | divsel, | |
3992 | phasedir, | |
3993 | phaseinc); | |
3994 | ||
3995 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 3996 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3997 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3998 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3999 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
4000 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
4001 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
4002 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 4003 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
4004 | |
4005 | /* Program SSCAUXDIV */ | |
988d6ee8 | 4006 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
4007 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
4008 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 4009 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
4010 | |
4011 | /* Enable modulator and associated divider */ | |
988d6ee8 | 4012 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 4013 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 4014 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
4015 | |
4016 | /* Wait for initialization time */ | |
4017 | udelay(24); | |
4018 | ||
4019 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 | 4020 | |
a580516d | 4021 | mutex_unlock(&dev_priv->sb_lock); |
e615efe4 ED |
4022 | } |
4023 | ||
275f01b2 DV |
4024 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4025 | enum pipe pch_transcoder) | |
4026 | { | |
4027 | struct drm_device *dev = crtc->base.dev; | |
4028 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 4029 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4030 | |
4031 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4032 | I915_READ(HTOTAL(cpu_transcoder))); | |
4033 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4034 | I915_READ(HBLANK(cpu_transcoder))); | |
4035 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4036 | I915_READ(HSYNC(cpu_transcoder))); | |
4037 | ||
4038 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4039 | I915_READ(VTOTAL(cpu_transcoder))); | |
4040 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4041 | I915_READ(VBLANK(cpu_transcoder))); | |
4042 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4043 | I915_READ(VSYNC(cpu_transcoder))); | |
4044 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4045 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4046 | } | |
4047 | ||
003632d9 | 4048 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 DV |
4049 | { |
4050 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4051 | uint32_t temp; | |
4052 | ||
4053 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4054 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4055 | return; |
4056 | ||
4057 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4058 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4059 | ||
003632d9 ACO |
4060 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4061 | if (enable) | |
4062 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4063 | ||
4064 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4065 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4066 | POSTING_READ(SOUTH_CHICKEN1); | |
4067 | } | |
4068 | ||
4069 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4070 | { | |
4071 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4072 | |
4073 | switch (intel_crtc->pipe) { | |
4074 | case PIPE_A: | |
4075 | break; | |
4076 | case PIPE_B: | |
6e3c9717 | 4077 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4078 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4079 | else |
003632d9 | 4080 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4081 | |
4082 | break; | |
4083 | case PIPE_C: | |
003632d9 | 4084 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4085 | |
4086 | break; | |
4087 | default: | |
4088 | BUG(); | |
4089 | } | |
4090 | } | |
4091 | ||
f67a559d JB |
4092 | /* |
4093 | * Enable PCH resources required for PCH ports: | |
4094 | * - PCH PLLs | |
4095 | * - FDI training & RX/TX | |
4096 | * - update transcoder timings | |
4097 | * - DP transcoding bits | |
4098 | * - transcoder | |
4099 | */ | |
4100 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4101 | { |
4102 | struct drm_device *dev = crtc->dev; | |
4103 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4104 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4105 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 4106 | u32 reg, temp; |
2c07245f | 4107 | |
ab9412ba | 4108 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4109 | |
1fbc0d78 DV |
4110 | if (IS_IVYBRIDGE(dev)) |
4111 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
4112 | ||
cd986abb DV |
4113 | /* Write the TU size bits before fdi link training, so that error |
4114 | * detection works. */ | |
4115 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4116 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4117 | ||
c98e9dcf | 4118 | /* For PCH output, training FDI link */ |
674cf967 | 4119 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4120 | |
3ad8a208 DV |
4121 | /* We need to program the right clock selection before writing the pixel |
4122 | * mutliplier into the DPLL. */ | |
303b81e0 | 4123 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 4124 | u32 sel; |
4b645f14 | 4125 | |
c98e9dcf | 4126 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4127 | temp |= TRANS_DPLL_ENABLE(pipe); |
4128 | sel = TRANS_DPLLB_SEL(pipe); | |
6e3c9717 | 4129 | if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
4130 | temp |= sel; |
4131 | else | |
4132 | temp &= ~sel; | |
c98e9dcf | 4133 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4134 | } |
5eddb70b | 4135 | |
3ad8a208 DV |
4136 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4137 | * transcoder, and we actually should do this to not upset any PCH | |
4138 | * transcoder that already use the clock when we share it. | |
4139 | * | |
4140 | * Note that enable_shared_dpll tries to do the right thing, but | |
4141 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4142 | * the right LVDS enable sequence. */ | |
85b3894f | 4143 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4144 | |
d9b6cb56 JB |
4145 | /* set transcoder timing, panel must allow it */ |
4146 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4147 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4148 | |
303b81e0 | 4149 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4150 | |
c98e9dcf | 4151 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e3c9717 | 4152 | if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { |
dfd07d72 | 4153 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
4154 | reg = TRANS_DP_CTL(pipe); |
4155 | temp = I915_READ(reg); | |
4156 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4157 | TRANS_DP_SYNC_MASK | |
4158 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4159 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4160 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
4161 | |
4162 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 4163 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 4164 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4165 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4166 | |
4167 | switch (intel_trans_dp_port_sel(crtc)) { | |
4168 | case PCH_DP_B: | |
5eddb70b | 4169 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
4170 | break; |
4171 | case PCH_DP_C: | |
5eddb70b | 4172 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
4173 | break; |
4174 | case PCH_DP_D: | |
5eddb70b | 4175 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4176 | break; |
4177 | default: | |
e95d41e1 | 4178 | BUG(); |
32f9d658 | 4179 | } |
2c07245f | 4180 | |
5eddb70b | 4181 | I915_WRITE(reg, temp); |
6be4a607 | 4182 | } |
b52eb4dc | 4183 | |
b8a4f404 | 4184 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4185 | } |
4186 | ||
1507e5bd PZ |
4187 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4188 | { | |
4189 | struct drm_device *dev = crtc->dev; | |
4190 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4191 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6e3c9717 | 4192 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4193 | |
ab9412ba | 4194 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4195 | |
8c52b5e8 | 4196 | lpt_program_iclkip(crtc); |
1507e5bd | 4197 | |
0540e488 | 4198 | /* Set transcoder timing. */ |
275f01b2 | 4199 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4200 | |
937bb610 | 4201 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4202 | } |
4203 | ||
190f68c5 ACO |
4204 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, |
4205 | struct intel_crtc_state *crtc_state) | |
ee7b9f93 | 4206 | { |
e2b78267 | 4207 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
8bd31e67 | 4208 | struct intel_shared_dpll *pll; |
de419ab6 | 4209 | struct intel_shared_dpll_config *shared_dpll; |
e2b78267 | 4210 | enum intel_dpll_id i; |
ee7b9f93 | 4211 | |
de419ab6 ML |
4212 | shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state); |
4213 | ||
98b6bd99 DV |
4214 | if (HAS_PCH_IBX(dev_priv->dev)) { |
4215 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 4216 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 4217 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 4218 | |
46edb027 DV |
4219 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
4220 | crtc->base.base.id, pll->name); | |
98b6bd99 | 4221 | |
de419ab6 | 4222 | WARN_ON(shared_dpll[i].crtc_mask); |
f2a69f44 | 4223 | |
98b6bd99 DV |
4224 | goto found; |
4225 | } | |
4226 | ||
bcddf610 S |
4227 | if (IS_BROXTON(dev_priv->dev)) { |
4228 | /* PLL is attached to port in bxt */ | |
4229 | struct intel_encoder *encoder; | |
4230 | struct intel_digital_port *intel_dig_port; | |
4231 | ||
4232 | encoder = intel_ddi_get_crtc_new_encoder(crtc_state); | |
4233 | if (WARN_ON(!encoder)) | |
4234 | return NULL; | |
4235 | ||
4236 | intel_dig_port = enc_to_dig_port(&encoder->base); | |
4237 | /* 1:1 mapping between ports and PLLs */ | |
4238 | i = (enum intel_dpll_id)intel_dig_port->port; | |
4239 | pll = &dev_priv->shared_dplls[i]; | |
4240 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", | |
4241 | crtc->base.base.id, pll->name); | |
de419ab6 | 4242 | WARN_ON(shared_dpll[i].crtc_mask); |
bcddf610 S |
4243 | |
4244 | goto found; | |
4245 | } | |
4246 | ||
e72f9fbf DV |
4247 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4248 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 JB |
4249 | |
4250 | /* Only want to check enabled timings first */ | |
de419ab6 | 4251 | if (shared_dpll[i].crtc_mask == 0) |
ee7b9f93 JB |
4252 | continue; |
4253 | ||
190f68c5 | 4254 | if (memcmp(&crtc_state->dpll_hw_state, |
de419ab6 ML |
4255 | &shared_dpll[i].hw_state, |
4256 | sizeof(crtc_state->dpll_hw_state)) == 0) { | |
8bd31e67 | 4257 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n", |
1e6f2ddc | 4258 | crtc->base.base.id, pll->name, |
de419ab6 | 4259 | shared_dpll[i].crtc_mask, |
8bd31e67 | 4260 | pll->active); |
ee7b9f93 JB |
4261 | goto found; |
4262 | } | |
4263 | } | |
4264 | ||
4265 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
4266 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4267 | pll = &dev_priv->shared_dplls[i]; | |
de419ab6 | 4268 | if (shared_dpll[i].crtc_mask == 0) { |
46edb027 DV |
4269 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
4270 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
4271 | goto found; |
4272 | } | |
4273 | } | |
4274 | ||
4275 | return NULL; | |
4276 | ||
4277 | found: | |
de419ab6 ML |
4278 | if (shared_dpll[i].crtc_mask == 0) |
4279 | shared_dpll[i].hw_state = | |
4280 | crtc_state->dpll_hw_state; | |
f2a69f44 | 4281 | |
190f68c5 | 4282 | crtc_state->shared_dpll = i; |
46edb027 DV |
4283 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
4284 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 4285 | |
de419ab6 | 4286 | shared_dpll[i].crtc_mask |= 1 << crtc->pipe; |
e04c7350 | 4287 | |
ee7b9f93 JB |
4288 | return pll; |
4289 | } | |
4290 | ||
de419ab6 | 4291 | static void intel_shared_dpll_commit(struct drm_atomic_state *state) |
8bd31e67 | 4292 | { |
de419ab6 ML |
4293 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
4294 | struct intel_shared_dpll_config *shared_dpll; | |
8bd31e67 ACO |
4295 | struct intel_shared_dpll *pll; |
4296 | enum intel_dpll_id i; | |
4297 | ||
de419ab6 ML |
4298 | if (!to_intel_atomic_state(state)->dpll_set) |
4299 | return; | |
8bd31e67 | 4300 | |
de419ab6 | 4301 | shared_dpll = to_intel_atomic_state(state)->shared_dpll; |
8bd31e67 ACO |
4302 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4303 | pll = &dev_priv->shared_dplls[i]; | |
de419ab6 | 4304 | pll->config = shared_dpll[i]; |
8bd31e67 ACO |
4305 | } |
4306 | } | |
4307 | ||
a1520318 | 4308 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
4309 | { |
4310 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 4311 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4312 | u32 temp; |
4313 | ||
4314 | temp = I915_READ(dslreg); | |
4315 | udelay(500); | |
4316 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4317 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4318 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4319 | } |
4320 | } | |
4321 | ||
86adf9d7 ML |
4322 | static int |
4323 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
4324 | unsigned scaler_user, int *scaler_id, unsigned int rotation, | |
4325 | int src_w, int src_h, int dst_w, int dst_h) | |
a1b2278e | 4326 | { |
86adf9d7 ML |
4327 | struct intel_crtc_scaler_state *scaler_state = |
4328 | &crtc_state->scaler_state; | |
4329 | struct intel_crtc *intel_crtc = | |
4330 | to_intel_crtc(crtc_state->base.crtc); | |
a1b2278e | 4331 | int need_scaling; |
6156a456 CK |
4332 | |
4333 | need_scaling = intel_rotation_90_or_270(rotation) ? | |
4334 | (src_h != dst_w || src_w != dst_h): | |
4335 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4336 | |
4337 | /* | |
4338 | * if plane is being disabled or scaler is no more required or force detach | |
4339 | * - free scaler binded to this plane/crtc | |
4340 | * - in order to do this, update crtc->scaler_usage | |
4341 | * | |
4342 | * Here scaler state in crtc_state is set free so that | |
4343 | * scaler can be assigned to other user. Actual register | |
4344 | * update to free the scaler is done in plane/panel-fit programming. | |
4345 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4346 | */ | |
86adf9d7 | 4347 | if (force_detach || !need_scaling) { |
a1b2278e | 4348 | if (*scaler_id >= 0) { |
86adf9d7 | 4349 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4350 | scaler_state->scalers[*scaler_id].in_use = 0; |
4351 | ||
86adf9d7 ML |
4352 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4353 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4354 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4355 | scaler_state->scaler_users); |
4356 | *scaler_id = -1; | |
4357 | } | |
4358 | return 0; | |
4359 | } | |
4360 | ||
4361 | /* range checks */ | |
4362 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4363 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4364 | ||
4365 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4366 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4367 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4368 | "size is out of scaler range\n", |
86adf9d7 | 4369 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4370 | return -EINVAL; |
4371 | } | |
4372 | ||
86adf9d7 ML |
4373 | /* mark this plane as a scaler user in crtc_state */ |
4374 | scaler_state->scaler_users |= (1 << scaler_user); | |
4375 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4376 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4377 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4378 | scaler_state->scaler_users); | |
4379 | ||
4380 | return 0; | |
4381 | } | |
4382 | ||
4383 | /** | |
4384 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4385 | * | |
4386 | * @state: crtc's scaler state | |
86adf9d7 ML |
4387 | * |
4388 | * Return | |
4389 | * 0 - scaler_usage updated successfully | |
4390 | * error - requested scaling cannot be supported or other error condition | |
4391 | */ | |
e435d6e5 | 4392 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 ML |
4393 | { |
4394 | struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); | |
124abe07 | 4395 | struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
86adf9d7 ML |
4396 | |
4397 | DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n", | |
4398 | intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX); | |
4399 | ||
e435d6e5 | 4400 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
86adf9d7 ML |
4401 | &state->scaler_state.scaler_id, DRM_ROTATE_0, |
4402 | state->pipe_src_w, state->pipe_src_h, | |
8c6cda29 | 4403 | adjusted_mode->hdisplay, adjusted_mode->vdisplay); |
86adf9d7 ML |
4404 | } |
4405 | ||
4406 | /** | |
4407 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4408 | * | |
4409 | * @state: crtc's scaler state | |
86adf9d7 ML |
4410 | * @plane_state: atomic plane state to update |
4411 | * | |
4412 | * Return | |
4413 | * 0 - scaler_usage updated successfully | |
4414 | * error - requested scaling cannot be supported or other error condition | |
4415 | */ | |
da20eabd ML |
4416 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4417 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4418 | { |
4419 | ||
4420 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
da20eabd ML |
4421 | struct intel_plane *intel_plane = |
4422 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4423 | struct drm_framebuffer *fb = plane_state->base.fb; |
4424 | int ret; | |
4425 | ||
4426 | bool force_detach = !fb || !plane_state->visible; | |
4427 | ||
4428 | DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n", | |
4429 | intel_plane->base.base.id, intel_crtc->pipe, | |
4430 | drm_plane_index(&intel_plane->base)); | |
4431 | ||
4432 | ret = skl_update_scaler(crtc_state, force_detach, | |
4433 | drm_plane_index(&intel_plane->base), | |
4434 | &plane_state->scaler_id, | |
4435 | plane_state->base.rotation, | |
4436 | drm_rect_width(&plane_state->src) >> 16, | |
4437 | drm_rect_height(&plane_state->src) >> 16, | |
4438 | drm_rect_width(&plane_state->dst), | |
4439 | drm_rect_height(&plane_state->dst)); | |
4440 | ||
4441 | if (ret || plane_state->scaler_id < 0) | |
4442 | return ret; | |
4443 | ||
a1b2278e | 4444 | /* check colorkey */ |
818ed961 | 4445 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
86adf9d7 | 4446 | DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed", |
818ed961 | 4447 | intel_plane->base.base.id); |
a1b2278e CK |
4448 | return -EINVAL; |
4449 | } | |
4450 | ||
4451 | /* Check src format */ | |
86adf9d7 ML |
4452 | switch (fb->pixel_format) { |
4453 | case DRM_FORMAT_RGB565: | |
4454 | case DRM_FORMAT_XBGR8888: | |
4455 | case DRM_FORMAT_XRGB8888: | |
4456 | case DRM_FORMAT_ABGR8888: | |
4457 | case DRM_FORMAT_ARGB8888: | |
4458 | case DRM_FORMAT_XRGB2101010: | |
4459 | case DRM_FORMAT_XBGR2101010: | |
4460 | case DRM_FORMAT_YUYV: | |
4461 | case DRM_FORMAT_YVYU: | |
4462 | case DRM_FORMAT_UYVY: | |
4463 | case DRM_FORMAT_VYUY: | |
4464 | break; | |
4465 | default: | |
4466 | DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n", | |
4467 | intel_plane->base.base.id, fb->base.id, fb->pixel_format); | |
4468 | return -EINVAL; | |
a1b2278e CK |
4469 | } |
4470 | ||
a1b2278e CK |
4471 | return 0; |
4472 | } | |
4473 | ||
e435d6e5 ML |
4474 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4475 | { | |
4476 | int i; | |
4477 | ||
4478 | for (i = 0; i < crtc->num_scalers; i++) | |
4479 | skl_detach_scaler(crtc, i); | |
4480 | } | |
4481 | ||
4482 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4483 | { |
4484 | struct drm_device *dev = crtc->base.dev; | |
4485 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4486 | int pipe = crtc->pipe; | |
a1b2278e CK |
4487 | struct intel_crtc_scaler_state *scaler_state = |
4488 | &crtc->config->scaler_state; | |
4489 | ||
4490 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4491 | ||
6e3c9717 | 4492 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4493 | int id; |
4494 | ||
4495 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4496 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4497 | return; | |
4498 | } | |
4499 | ||
4500 | id = scaler_state->scaler_id; | |
4501 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4502 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4503 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4504 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4505 | ||
4506 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4507 | } |
4508 | } | |
4509 | ||
b074cec8 JB |
4510 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4511 | { | |
4512 | struct drm_device *dev = crtc->base.dev; | |
4513 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4514 | int pipe = crtc->pipe; | |
4515 | ||
6e3c9717 | 4516 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4517 | /* Force use of hard-coded filter coefficients |
4518 | * as some pre-programmed values are broken, | |
4519 | * e.g. x201. | |
4520 | */ | |
4521 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4522 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4523 | PF_PIPE_SEL_IVB(pipe)); | |
4524 | else | |
4525 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4526 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4527 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4528 | } |
4529 | } | |
4530 | ||
20bc8673 | 4531 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4532 | { |
cea165c3 VS |
4533 | struct drm_device *dev = crtc->base.dev; |
4534 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 | 4535 | |
6e3c9717 | 4536 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4537 | return; |
4538 | ||
cea165c3 VS |
4539 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
4540 | intel_wait_for_vblank(dev, crtc->pipe); | |
4541 | ||
d77e4531 | 4542 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4543 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4544 | mutex_lock(&dev_priv->rps.hw_lock); |
4545 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4546 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4547 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4548 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4549 | * mailbox." Moreover, the mailbox may return a bogus state, |
4550 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4551 | */ |
4552 | } else { | |
4553 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4554 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4555 | * is essentially intel_wait_for_vblank. If we don't have this | |
4556 | * and don't wait for vblanks until the end of crtc_enable, then | |
4557 | * the HW state readout code will complain that the expected | |
4558 | * IPS_CTL value is not the one we read. */ | |
4559 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
4560 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
4561 | } | |
d77e4531 PZ |
4562 | } |
4563 | ||
20bc8673 | 4564 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4565 | { |
4566 | struct drm_device *dev = crtc->base.dev; | |
4567 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4568 | ||
6e3c9717 | 4569 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4570 | return; |
4571 | ||
4572 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4573 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4574 | mutex_lock(&dev_priv->rps.hw_lock); |
4575 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4576 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
4577 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
4578 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
4579 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 4580 | } else { |
2a114cc1 | 4581 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4582 | POSTING_READ(IPS_CTL); |
4583 | } | |
d77e4531 PZ |
4584 | |
4585 | /* We need to wait for a vblank before we can disable the plane. */ | |
4586 | intel_wait_for_vblank(dev, crtc->pipe); | |
4587 | } | |
4588 | ||
4589 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
4590 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
4591 | { | |
4592 | struct drm_device *dev = crtc->dev; | |
4593 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4594 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4595 | enum pipe pipe = intel_crtc->pipe; | |
4596 | int palreg = PALETTE(pipe); | |
4597 | int i; | |
4598 | bool reenable_ips = false; | |
4599 | ||
4600 | /* The clocks have to be on to load the palette. */ | |
53d9f4e9 | 4601 | if (!crtc->state->active) |
d77e4531 PZ |
4602 | return; |
4603 | ||
50360403 | 4604 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) { |
409ee761 | 4605 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) |
d77e4531 PZ |
4606 | assert_dsi_pll_enabled(dev_priv); |
4607 | else | |
4608 | assert_pll_enabled(dev_priv, pipe); | |
4609 | } | |
4610 | ||
4611 | /* use legacy palette for Ironlake */ | |
7a1db49a | 4612 | if (!HAS_GMCH_DISPLAY(dev)) |
d77e4531 PZ |
4613 | palreg = LGC_PALETTE(pipe); |
4614 | ||
4615 | /* Workaround : Do not read or write the pipe palette/gamma data while | |
4616 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
4617 | */ | |
6e3c9717 | 4618 | if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled && |
d77e4531 PZ |
4619 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
4620 | GAMMA_MODE_MODE_SPLIT)) { | |
4621 | hsw_disable_ips(intel_crtc); | |
4622 | reenable_ips = true; | |
4623 | } | |
4624 | ||
4625 | for (i = 0; i < 256; i++) { | |
4626 | I915_WRITE(palreg + 4 * i, | |
4627 | (intel_crtc->lut_r[i] << 16) | | |
4628 | (intel_crtc->lut_g[i] << 8) | | |
4629 | intel_crtc->lut_b[i]); | |
4630 | } | |
4631 | ||
4632 | if (reenable_ips) | |
4633 | hsw_enable_ips(intel_crtc); | |
4634 | } | |
4635 | ||
7cac945f | 4636 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4637 | { |
7cac945f | 4638 | if (intel_crtc->overlay) { |
d3eedb1a VS |
4639 | struct drm_device *dev = intel_crtc->base.dev; |
4640 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4641 | ||
4642 | mutex_lock(&dev->struct_mutex); | |
4643 | dev_priv->mm.interruptible = false; | |
4644 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4645 | dev_priv->mm.interruptible = true; | |
4646 | mutex_unlock(&dev->struct_mutex); | |
4647 | } | |
4648 | ||
4649 | /* Let userspace switch the overlay on again. In most cases userspace | |
4650 | * has to recompute where to put it anyway. | |
4651 | */ | |
4652 | } | |
4653 | ||
87d4300a ML |
4654 | /** |
4655 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4656 | * @crtc: the CRTC whose primary plane was just enabled | |
4657 | * | |
4658 | * Performs potentially sleeping operations that must be done after the primary | |
4659 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4660 | * called due to an explicit primary plane update, or due to an implicit | |
4661 | * re-enable that is caused when a sprite plane is updated to no longer | |
4662 | * completely hide the primary plane. | |
4663 | */ | |
4664 | static void | |
4665 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4666 | { |
4667 | struct drm_device *dev = crtc->dev; | |
87d4300a | 4668 | struct drm_i915_private *dev_priv = dev->dev_private; |
a5c4d7bc VS |
4669 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4670 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4671 | |
87d4300a ML |
4672 | /* |
4673 | * BDW signals flip done immediately if the plane | |
4674 | * is disabled, even if the plane enable is already | |
4675 | * armed to occur at the next vblank :( | |
4676 | */ | |
4677 | if (IS_BROADWELL(dev)) | |
4678 | intel_wait_for_vblank(dev, pipe); | |
a5c4d7bc | 4679 | |
87d4300a ML |
4680 | /* |
4681 | * FIXME IPS should be fine as long as one plane is | |
4682 | * enabled, but in practice it seems to have problems | |
4683 | * when going from primary only to sprite only and vice | |
4684 | * versa. | |
4685 | */ | |
a5c4d7bc VS |
4686 | hsw_enable_ips(intel_crtc); |
4687 | ||
f99d7069 | 4688 | /* |
87d4300a ML |
4689 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4690 | * So don't enable underrun reporting before at least some planes | |
4691 | * are enabled. | |
4692 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4693 | * but leave the pipe running. | |
f99d7069 | 4694 | */ |
87d4300a ML |
4695 | if (IS_GEN2(dev)) |
4696 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4697 | ||
4698 | /* Underruns don't raise interrupts, so check manually. */ | |
4699 | if (HAS_GMCH_DISPLAY(dev)) | |
4700 | i9xx_check_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4701 | } |
4702 | ||
87d4300a ML |
4703 | /** |
4704 | * intel_pre_disable_primary - Perform operations before disabling primary plane | |
4705 | * @crtc: the CRTC whose primary plane is to be disabled | |
4706 | * | |
4707 | * Performs potentially sleeping operations that must be done before the | |
4708 | * primary plane is disabled, such as updating FBC and IPS. Note that this may | |
4709 | * be called due to an explicit primary plane update, or due to an implicit | |
4710 | * disable that is caused when a sprite plane completely hides the primary | |
4711 | * plane. | |
4712 | */ | |
4713 | static void | |
4714 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4715 | { |
4716 | struct drm_device *dev = crtc->dev; | |
4717 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4718 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4719 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4720 | |
87d4300a ML |
4721 | /* |
4722 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4723 | * So diasble underrun reporting before all the planes get disabled. | |
4724 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4725 | * but leave the pipe running. | |
4726 | */ | |
4727 | if (IS_GEN2(dev)) | |
4728 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
a5c4d7bc | 4729 | |
87d4300a ML |
4730 | /* |
4731 | * Vblank time updates from the shadow to live plane control register | |
4732 | * are blocked if the memory self-refresh mode is active at that | |
4733 | * moment. So to make sure the plane gets truly disabled, disable | |
4734 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4735 | * will be checked/applied by the HW only at the next frame start | |
4736 | * event which is after the vblank start event, so we need to have a | |
4737 | * wait-for-vblank between disabling the plane and the pipe. | |
4738 | */ | |
262cd2e1 | 4739 | if (HAS_GMCH_DISPLAY(dev)) { |
87d4300a | 4740 | intel_set_memory_cxsr(dev_priv, false); |
262cd2e1 VS |
4741 | dev_priv->wm.vlv.cxsr = false; |
4742 | intel_wait_for_vblank(dev, pipe); | |
4743 | } | |
87d4300a | 4744 | |
87d4300a ML |
4745 | /* |
4746 | * FIXME IPS should be fine as long as one plane is | |
4747 | * enabled, but in practice it seems to have problems | |
4748 | * when going from primary only to sprite only and vice | |
4749 | * versa. | |
4750 | */ | |
a5c4d7bc | 4751 | hsw_disable_ips(intel_crtc); |
87d4300a ML |
4752 | } |
4753 | ||
ac21b225 ML |
4754 | static void intel_post_plane_update(struct intel_crtc *crtc) |
4755 | { | |
4756 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; | |
4757 | struct drm_device *dev = crtc->base.dev; | |
7733b49b | 4758 | struct drm_i915_private *dev_priv = dev->dev_private; |
ac21b225 ML |
4759 | struct drm_plane *plane; |
4760 | ||
4761 | if (atomic->wait_vblank) | |
4762 | intel_wait_for_vblank(dev, crtc->pipe); | |
4763 | ||
4764 | intel_frontbuffer_flip(dev, atomic->fb_bits); | |
4765 | ||
852eb00d VS |
4766 | if (atomic->disable_cxsr) |
4767 | crtc->wm.cxsr_allowed = true; | |
4768 | ||
f015c551 VS |
4769 | if (crtc->atomic.update_wm_post) |
4770 | intel_update_watermarks(&crtc->base); | |
4771 | ||
c80ac854 | 4772 | if (atomic->update_fbc) |
7733b49b | 4773 | intel_fbc_update(dev_priv); |
ac21b225 ML |
4774 | |
4775 | if (atomic->post_enable_primary) | |
4776 | intel_post_enable_primary(&crtc->base); | |
4777 | ||
4778 | drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks) | |
4779 | intel_update_sprite_watermarks(plane, &crtc->base, | |
4780 | 0, 0, 0, false, false); | |
4781 | ||
4782 | memset(atomic, 0, sizeof(*atomic)); | |
4783 | } | |
4784 | ||
4785 | static void intel_pre_plane_update(struct intel_crtc *crtc) | |
4786 | { | |
4787 | struct drm_device *dev = crtc->base.dev; | |
eddfcbcd | 4788 | struct drm_i915_private *dev_priv = dev->dev_private; |
ac21b225 ML |
4789 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; |
4790 | struct drm_plane *p; | |
4791 | ||
4792 | /* Track fb's for any planes being disabled */ | |
ac21b225 ML |
4793 | drm_for_each_plane_mask(p, dev, atomic->disabled_planes) { |
4794 | struct intel_plane *plane = to_intel_plane(p); | |
ac21b225 ML |
4795 | |
4796 | mutex_lock(&dev->struct_mutex); | |
a9ff8714 VS |
4797 | i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL, |
4798 | plane->frontbuffer_bit); | |
ac21b225 ML |
4799 | mutex_unlock(&dev->struct_mutex); |
4800 | } | |
4801 | ||
4802 | if (atomic->wait_for_flips) | |
4803 | intel_crtc_wait_for_pending_flips(&crtc->base); | |
4804 | ||
c80ac854 | 4805 | if (atomic->disable_fbc) |
25ad93fd | 4806 | intel_fbc_disable_crtc(crtc); |
ac21b225 | 4807 | |
066cf55b RV |
4808 | if (crtc->atomic.disable_ips) |
4809 | hsw_disable_ips(crtc); | |
4810 | ||
ac21b225 ML |
4811 | if (atomic->pre_disable_primary) |
4812 | intel_pre_disable_primary(&crtc->base); | |
852eb00d VS |
4813 | |
4814 | if (atomic->disable_cxsr) { | |
4815 | crtc->wm.cxsr_allowed = false; | |
4816 | intel_set_memory_cxsr(dev_priv, false); | |
4817 | } | |
ac21b225 ML |
4818 | } |
4819 | ||
d032ffa0 | 4820 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
4821 | { |
4822 | struct drm_device *dev = crtc->dev; | |
4823 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 4824 | struct drm_plane *p; |
87d4300a ML |
4825 | int pipe = intel_crtc->pipe; |
4826 | ||
7cac945f | 4827 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 4828 | |
d032ffa0 ML |
4829 | drm_for_each_plane_mask(p, dev, plane_mask) |
4830 | to_intel_plane(p)->disable_plane(p, crtc); | |
f98551ae | 4831 | |
f99d7069 DV |
4832 | /* |
4833 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4834 | * to compute the mask of flip planes precisely. For the time being | |
4835 | * consider this a flip to a NULL plane. | |
4836 | */ | |
4837 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4838 | } |
4839 | ||
f67a559d JB |
4840 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4841 | { | |
4842 | struct drm_device *dev = crtc->dev; | |
4843 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4844 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4845 | struct intel_encoder *encoder; |
f67a559d | 4846 | int pipe = intel_crtc->pipe; |
f67a559d | 4847 | |
53d9f4e9 | 4848 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
4849 | return; |
4850 | ||
6e3c9717 | 4851 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
4852 | intel_prepare_shared_dpll(intel_crtc); |
4853 | ||
6e3c9717 | 4854 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4855 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
4856 | |
4857 | intel_set_pipe_timings(intel_crtc); | |
4858 | ||
6e3c9717 | 4859 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 4860 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4861 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
4862 | } |
4863 | ||
4864 | ironlake_set_pipeconf(crtc); | |
4865 | ||
f67a559d | 4866 | intel_crtc->active = true; |
8664281b | 4867 | |
a72e4c9f DV |
4868 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4869 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
8664281b | 4870 | |
f6736a1a | 4871 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4872 | if (encoder->pre_enable) |
4873 | encoder->pre_enable(encoder); | |
f67a559d | 4874 | |
6e3c9717 | 4875 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
4876 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4877 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4878 | * enabling. */ | |
88cefb6c | 4879 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4880 | } else { |
4881 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4882 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4883 | } | |
f67a559d | 4884 | |
b074cec8 | 4885 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4886 | |
9c54c0dd JB |
4887 | /* |
4888 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4889 | * clocks enabled | |
4890 | */ | |
4891 | intel_crtc_load_lut(crtc); | |
4892 | ||
f37fcc2a | 4893 | intel_update_watermarks(crtc); |
e1fdc473 | 4894 | intel_enable_pipe(intel_crtc); |
f67a559d | 4895 | |
6e3c9717 | 4896 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 4897 | ironlake_pch_enable(crtc); |
c98e9dcf | 4898 | |
f9b61ff6 DV |
4899 | assert_vblank_disabled(crtc); |
4900 | drm_crtc_vblank_on(crtc); | |
4901 | ||
fa5c73b1 DV |
4902 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4903 | encoder->enable(encoder); | |
61b77ddd DV |
4904 | |
4905 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4906 | cpt_verify_modeset(dev, intel_crtc->pipe); |
6be4a607 JB |
4907 | } |
4908 | ||
42db64ef PZ |
4909 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4910 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4911 | { | |
f5adf94e | 4912 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4913 | } |
4914 | ||
4f771f10 PZ |
4915 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4916 | { | |
4917 | struct drm_device *dev = crtc->dev; | |
4918 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4919 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4920 | struct intel_encoder *encoder; | |
99d736a2 ML |
4921 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4922 | struct intel_crtc_state *pipe_config = | |
4923 | to_intel_crtc_state(crtc->state); | |
4f771f10 | 4924 | |
53d9f4e9 | 4925 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
4926 | return; |
4927 | ||
df8ad70c DV |
4928 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
4929 | intel_enable_shared_dpll(intel_crtc); | |
4930 | ||
6e3c9717 | 4931 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4932 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 DV |
4933 | |
4934 | intel_set_pipe_timings(intel_crtc); | |
4935 | ||
6e3c9717 ACO |
4936 | if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) { |
4937 | I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder), | |
4938 | intel_crtc->config->pixel_multiplier - 1); | |
ebb69c95 CT |
4939 | } |
4940 | ||
6e3c9717 | 4941 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 4942 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4943 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
4944 | } |
4945 | ||
4946 | haswell_set_pipeconf(crtc); | |
4947 | ||
4948 | intel_set_pipe_csc(crtc); | |
4949 | ||
4f771f10 | 4950 | intel_crtc->active = true; |
8664281b | 4951 | |
a72e4c9f | 4952 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4f771f10 PZ |
4953 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4954 | if (encoder->pre_enable) | |
4955 | encoder->pre_enable(encoder); | |
4956 | ||
6e3c9717 | 4957 | if (intel_crtc->config->has_pch_encoder) { |
a72e4c9f DV |
4958 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
4959 | true); | |
4fe9467d ID |
4960 | dev_priv->display.fdi_link_train(crtc); |
4961 | } | |
4962 | ||
1f544388 | 4963 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 4964 | |
1c132b44 | 4965 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 4966 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 4967 | else |
1c132b44 | 4968 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
4969 | |
4970 | /* | |
4971 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4972 | * clocks enabled | |
4973 | */ | |
4974 | intel_crtc_load_lut(crtc); | |
4975 | ||
1f544388 | 4976 | intel_ddi_set_pipe_settings(crtc); |
8228c251 | 4977 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 4978 | |
f37fcc2a | 4979 | intel_update_watermarks(crtc); |
e1fdc473 | 4980 | intel_enable_pipe(intel_crtc); |
42db64ef | 4981 | |
6e3c9717 | 4982 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 4983 | lpt_pch_enable(crtc); |
4f771f10 | 4984 | |
6e3c9717 | 4985 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
4986 | intel_ddi_set_vc_payload_alloc(crtc, true); |
4987 | ||
f9b61ff6 DV |
4988 | assert_vblank_disabled(crtc); |
4989 | drm_crtc_vblank_on(crtc); | |
4990 | ||
8807e55b | 4991 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 4992 | encoder->enable(encoder); |
8807e55b JN |
4993 | intel_opregion_notify_encoder(encoder, true); |
4994 | } | |
4f771f10 | 4995 | |
e4916946 PZ |
4996 | /* If we change the relative order between pipe/planes enabling, we need |
4997 | * to change the workaround. */ | |
99d736a2 ML |
4998 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
4999 | if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) { | |
5000 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
5001 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
5002 | } | |
4f771f10 PZ |
5003 | } |
5004 | ||
bfd16b2a | 5005 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
5006 | { |
5007 | struct drm_device *dev = crtc->base.dev; | |
5008 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5009 | int pipe = crtc->pipe; | |
5010 | ||
5011 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
5012 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 5013 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
5014 | I915_WRITE(PF_CTL(pipe), 0); |
5015 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
5016 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
5017 | } | |
5018 | } | |
5019 | ||
6be4a607 JB |
5020 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
5021 | { | |
5022 | struct drm_device *dev = crtc->dev; | |
5023 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5024 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 5025 | struct intel_encoder *encoder; |
6be4a607 | 5026 | int pipe = intel_crtc->pipe; |
5eddb70b | 5027 | u32 reg, temp; |
b52eb4dc | 5028 | |
ea9d758d DV |
5029 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5030 | encoder->disable(encoder); | |
5031 | ||
f9b61ff6 DV |
5032 | drm_crtc_vblank_off(crtc); |
5033 | assert_vblank_disabled(crtc); | |
5034 | ||
6e3c9717 | 5035 | if (intel_crtc->config->has_pch_encoder) |
a72e4c9f | 5036 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
d925c59a | 5037 | |
575f7ab7 | 5038 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5039 | |
bfd16b2a | 5040 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 5041 | |
5a74f70a VS |
5042 | if (intel_crtc->config->has_pch_encoder) |
5043 | ironlake_fdi_disable(crtc); | |
5044 | ||
bf49ec8c DV |
5045 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5046 | if (encoder->post_disable) | |
5047 | encoder->post_disable(encoder); | |
2c07245f | 5048 | |
6e3c9717 | 5049 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5050 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5051 | |
d925c59a DV |
5052 | if (HAS_PCH_CPT(dev)) { |
5053 | /* disable TRANS_DP_CTL */ | |
5054 | reg = TRANS_DP_CTL(pipe); | |
5055 | temp = I915_READ(reg); | |
5056 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5057 | TRANS_DP_PORT_SEL_MASK); | |
5058 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5059 | I915_WRITE(reg, temp); | |
5060 | ||
5061 | /* disable DPLL_SEL */ | |
5062 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5063 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5064 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5065 | } |
e3421a18 | 5066 | |
d925c59a DV |
5067 | ironlake_fdi_pll_disable(intel_crtc); |
5068 | } | |
e4ca0612 PJ |
5069 | |
5070 | intel_crtc->active = false; | |
5071 | intel_update_watermarks(crtc); | |
6be4a607 | 5072 | } |
1b3c7a47 | 5073 | |
4f771f10 | 5074 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 5075 | { |
4f771f10 PZ |
5076 | struct drm_device *dev = crtc->dev; |
5077 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 5078 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 5079 | struct intel_encoder *encoder; |
6e3c9717 | 5080 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5081 | |
8807e55b JN |
5082 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5083 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 5084 | encoder->disable(encoder); |
8807e55b | 5085 | } |
4f771f10 | 5086 | |
f9b61ff6 DV |
5087 | drm_crtc_vblank_off(crtc); |
5088 | assert_vblank_disabled(crtc); | |
5089 | ||
6e3c9717 | 5090 | if (intel_crtc->config->has_pch_encoder) |
a72e4c9f DV |
5091 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5092 | false); | |
575f7ab7 | 5093 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5094 | |
6e3c9717 | 5095 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
5096 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5097 | ||
ad80a810 | 5098 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5099 | |
1c132b44 | 5100 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5101 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5102 | else |
bfd16b2a | 5103 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 5104 | |
1f544388 | 5105 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 5106 | |
6e3c9717 | 5107 | if (intel_crtc->config->has_pch_encoder) { |
ab4d966c | 5108 | lpt_disable_pch_transcoder(dev_priv); |
1ad960f2 | 5109 | intel_ddi_fdi_disable(crtc); |
83616634 | 5110 | } |
4f771f10 | 5111 | |
97b040aa ID |
5112 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5113 | if (encoder->post_disable) | |
5114 | encoder->post_disable(encoder); | |
e4ca0612 PJ |
5115 | |
5116 | intel_crtc->active = false; | |
5117 | intel_update_watermarks(crtc); | |
4f771f10 PZ |
5118 | } |
5119 | ||
2dd24552 JB |
5120 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5121 | { | |
5122 | struct drm_device *dev = crtc->base.dev; | |
5123 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 5124 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5125 | |
681a8504 | 5126 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5127 | return; |
5128 | ||
2dd24552 | 5129 | /* |
c0b03411 DV |
5130 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5131 | * according to register description and PRM. | |
2dd24552 | 5132 | */ |
c0b03411 DV |
5133 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5134 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5135 | |
b074cec8 JB |
5136 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5137 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5138 | |
5139 | /* Border color in case we don't scale up to the full screen. Black by | |
5140 | * default, change to something else for debugging. */ | |
5141 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5142 | } |
5143 | ||
d05410f9 DA |
5144 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5145 | { | |
5146 | switch (port) { | |
5147 | case PORT_A: | |
5148 | return POWER_DOMAIN_PORT_DDI_A_4_LANES; | |
5149 | case PORT_B: | |
5150 | return POWER_DOMAIN_PORT_DDI_B_4_LANES; | |
5151 | case PORT_C: | |
5152 | return POWER_DOMAIN_PORT_DDI_C_4_LANES; | |
5153 | case PORT_D: | |
5154 | return POWER_DOMAIN_PORT_DDI_D_4_LANES; | |
d8e19f99 XZ |
5155 | case PORT_E: |
5156 | return POWER_DOMAIN_PORT_DDI_E_2_LANES; | |
d05410f9 DA |
5157 | default: |
5158 | WARN_ON_ONCE(1); | |
5159 | return POWER_DOMAIN_PORT_OTHER; | |
5160 | } | |
5161 | } | |
5162 | ||
77d22dca ID |
5163 | #define for_each_power_domain(domain, mask) \ |
5164 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
5165 | if ((1 << (domain)) & (mask)) | |
5166 | ||
319be8ae ID |
5167 | enum intel_display_power_domain |
5168 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5169 | { | |
5170 | struct drm_device *dev = intel_encoder->base.dev; | |
5171 | struct intel_digital_port *intel_dig_port; | |
5172 | ||
5173 | switch (intel_encoder->type) { | |
5174 | case INTEL_OUTPUT_UNKNOWN: | |
5175 | /* Only DDI platforms should ever use this output type */ | |
5176 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
5177 | case INTEL_OUTPUT_DISPLAYPORT: | |
5178 | case INTEL_OUTPUT_HDMI: | |
5179 | case INTEL_OUTPUT_EDP: | |
5180 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 5181 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
5182 | case INTEL_OUTPUT_DP_MST: |
5183 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5184 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
5185 | case INTEL_OUTPUT_ANALOG: |
5186 | return POWER_DOMAIN_PORT_CRT; | |
5187 | case INTEL_OUTPUT_DSI: | |
5188 | return POWER_DOMAIN_PORT_DSI; | |
5189 | default: | |
5190 | return POWER_DOMAIN_PORT_OTHER; | |
5191 | } | |
5192 | } | |
5193 | ||
5194 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) | |
77d22dca | 5195 | { |
319be8ae ID |
5196 | struct drm_device *dev = crtc->dev; |
5197 | struct intel_encoder *intel_encoder; | |
5198 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5199 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca ID |
5200 | unsigned long mask; |
5201 | enum transcoder transcoder; | |
5202 | ||
292b990e ML |
5203 | if (!crtc->state->active) |
5204 | return 0; | |
5205 | ||
77d22dca ID |
5206 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); |
5207 | ||
5208 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); | |
5209 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
6e3c9717 ACO |
5210 | if (intel_crtc->config->pch_pfit.enabled || |
5211 | intel_crtc->config->pch_pfit.force_thru) | |
77d22dca ID |
5212 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5213 | ||
319be8ae ID |
5214 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
5215 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); | |
5216 | ||
77d22dca ID |
5217 | return mask; |
5218 | } | |
5219 | ||
292b990e | 5220 | static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc) |
77d22dca | 5221 | { |
292b990e ML |
5222 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
5223 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5224 | enum intel_display_power_domain domain; | |
5225 | unsigned long domains, new_domains, old_domains; | |
77d22dca | 5226 | |
292b990e ML |
5227 | old_domains = intel_crtc->enabled_power_domains; |
5228 | intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc); | |
77d22dca | 5229 | |
292b990e ML |
5230 | domains = new_domains & ~old_domains; |
5231 | ||
5232 | for_each_power_domain(domain, domains) | |
5233 | intel_display_power_get(dev_priv, domain); | |
5234 | ||
5235 | return old_domains & ~new_domains; | |
5236 | } | |
5237 | ||
5238 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
5239 | unsigned long domains) | |
5240 | { | |
5241 | enum intel_display_power_domain domain; | |
5242 | ||
5243 | for_each_power_domain(domain, domains) | |
5244 | intel_display_power_put(dev_priv, domain); | |
5245 | } | |
77d22dca | 5246 | |
292b990e ML |
5247 | static void modeset_update_crtc_power_domains(struct drm_atomic_state *state) |
5248 | { | |
5249 | struct drm_device *dev = state->dev; | |
5250 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5251 | unsigned long put_domains[I915_MAX_PIPES] = {}; | |
5252 | struct drm_crtc_state *crtc_state; | |
5253 | struct drm_crtc *crtc; | |
5254 | int i; | |
77d22dca | 5255 | |
292b990e ML |
5256 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
5257 | if (needs_modeset(crtc->state)) | |
5258 | put_domains[to_intel_crtc(crtc)->pipe] = | |
5259 | modeset_get_crtc_power_domains(crtc); | |
77d22dca ID |
5260 | } |
5261 | ||
27c329ed ML |
5262 | if (dev_priv->display.modeset_commit_cdclk) { |
5263 | unsigned int cdclk = to_intel_atomic_state(state)->cdclk; | |
5264 | ||
5265 | if (cdclk != dev_priv->cdclk_freq && | |
5266 | !WARN_ON(!state->allow_modeset)) | |
5267 | dev_priv->display.modeset_commit_cdclk(state); | |
5268 | } | |
50f6e502 | 5269 | |
292b990e ML |
5270 | for (i = 0; i < I915_MAX_PIPES; i++) |
5271 | if (put_domains[i]) | |
5272 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
77d22dca ID |
5273 | } |
5274 | ||
adafdc6f MK |
5275 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
5276 | { | |
5277 | int max_cdclk_freq = dev_priv->max_cdclk_freq; | |
5278 | ||
5279 | if (INTEL_INFO(dev_priv)->gen >= 9 || | |
5280 | IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
5281 | return max_cdclk_freq; | |
5282 | else if (IS_CHERRYVIEW(dev_priv)) | |
5283 | return max_cdclk_freq*95/100; | |
5284 | else if (INTEL_INFO(dev_priv)->gen < 4) | |
5285 | return 2*max_cdclk_freq*90/100; | |
5286 | else | |
5287 | return max_cdclk_freq*90/100; | |
5288 | } | |
5289 | ||
560a7ae4 DL |
5290 | static void intel_update_max_cdclk(struct drm_device *dev) |
5291 | { | |
5292 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5293 | ||
5294 | if (IS_SKYLAKE(dev)) { | |
5295 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; | |
5296 | ||
5297 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) | |
5298 | dev_priv->max_cdclk_freq = 675000; | |
5299 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) | |
5300 | dev_priv->max_cdclk_freq = 540000; | |
5301 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) | |
5302 | dev_priv->max_cdclk_freq = 450000; | |
5303 | else | |
5304 | dev_priv->max_cdclk_freq = 337500; | |
5305 | } else if (IS_BROADWELL(dev)) { | |
5306 | /* | |
5307 | * FIXME with extra cooling we can allow | |
5308 | * 540 MHz for ULX and 675 Mhz for ULT. | |
5309 | * How can we know if extra cooling is | |
5310 | * available? PCI ID, VTB, something else? | |
5311 | */ | |
5312 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
5313 | dev_priv->max_cdclk_freq = 450000; | |
5314 | else if (IS_BDW_ULX(dev)) | |
5315 | dev_priv->max_cdclk_freq = 450000; | |
5316 | else if (IS_BDW_ULT(dev)) | |
5317 | dev_priv->max_cdclk_freq = 540000; | |
5318 | else | |
5319 | dev_priv->max_cdclk_freq = 675000; | |
0904deaf MK |
5320 | } else if (IS_CHERRYVIEW(dev)) { |
5321 | dev_priv->max_cdclk_freq = 320000; | |
560a7ae4 DL |
5322 | } else if (IS_VALLEYVIEW(dev)) { |
5323 | dev_priv->max_cdclk_freq = 400000; | |
5324 | } else { | |
5325 | /* otherwise assume cdclk is fixed */ | |
5326 | dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; | |
5327 | } | |
5328 | ||
adafdc6f MK |
5329 | dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); |
5330 | ||
560a7ae4 DL |
5331 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", |
5332 | dev_priv->max_cdclk_freq); | |
adafdc6f MK |
5333 | |
5334 | DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", | |
5335 | dev_priv->max_dotclk_freq); | |
560a7ae4 DL |
5336 | } |
5337 | ||
5338 | static void intel_update_cdclk(struct drm_device *dev) | |
5339 | { | |
5340 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5341 | ||
5342 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
5343 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", | |
5344 | dev_priv->cdclk_freq); | |
5345 | ||
5346 | /* | |
5347 | * Program the gmbus_freq based on the cdclk frequency. | |
5348 | * BSpec erroneously claims we should aim for 4MHz, but | |
5349 | * in fact 1MHz is the correct frequency. | |
5350 | */ | |
5351 | if (IS_VALLEYVIEW(dev)) { | |
5352 | /* | |
5353 | * Program the gmbus_freq based on the cdclk frequency. | |
5354 | * BSpec erroneously claims we should aim for 4MHz, but | |
5355 | * in fact 1MHz is the correct frequency. | |
5356 | */ | |
5357 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); | |
5358 | } | |
5359 | ||
5360 | if (dev_priv->max_cdclk_freq == 0) | |
5361 | intel_update_max_cdclk(dev); | |
5362 | } | |
5363 | ||
70d0c574 | 5364 | static void broxton_set_cdclk(struct drm_device *dev, int frequency) |
f8437dd1 VK |
5365 | { |
5366 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5367 | uint32_t divider; | |
5368 | uint32_t ratio; | |
5369 | uint32_t current_freq; | |
5370 | int ret; | |
5371 | ||
5372 | /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */ | |
5373 | switch (frequency) { | |
5374 | case 144000: | |
5375 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; | |
5376 | ratio = BXT_DE_PLL_RATIO(60); | |
5377 | break; | |
5378 | case 288000: | |
5379 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; | |
5380 | ratio = BXT_DE_PLL_RATIO(60); | |
5381 | break; | |
5382 | case 384000: | |
5383 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; | |
5384 | ratio = BXT_DE_PLL_RATIO(60); | |
5385 | break; | |
5386 | case 576000: | |
5387 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5388 | ratio = BXT_DE_PLL_RATIO(60); | |
5389 | break; | |
5390 | case 624000: | |
5391 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5392 | ratio = BXT_DE_PLL_RATIO(65); | |
5393 | break; | |
5394 | case 19200: | |
5395 | /* | |
5396 | * Bypass frequency with DE PLL disabled. Init ratio, divider | |
5397 | * to suppress GCC warning. | |
5398 | */ | |
5399 | ratio = 0; | |
5400 | divider = 0; | |
5401 | break; | |
5402 | default: | |
5403 | DRM_ERROR("unsupported CDCLK freq %d", frequency); | |
5404 | ||
5405 | return; | |
5406 | } | |
5407 | ||
5408 | mutex_lock(&dev_priv->rps.hw_lock); | |
5409 | /* Inform power controller of upcoming frequency change */ | |
5410 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5411 | 0x80000000); | |
5412 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5413 | ||
5414 | if (ret) { | |
5415 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
5416 | ret, frequency); | |
5417 | return; | |
5418 | } | |
5419 | ||
5420 | current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK; | |
5421 | /* convert from .1 fixpoint MHz with -1MHz offset to kHz */ | |
5422 | current_freq = current_freq * 500 + 1000; | |
5423 | ||
5424 | /* | |
5425 | * DE PLL has to be disabled when | |
5426 | * - setting to 19.2MHz (bypass, PLL isn't used) | |
5427 | * - before setting to 624MHz (PLL needs toggling) | |
5428 | * - before setting to any frequency from 624MHz (PLL needs toggling) | |
5429 | */ | |
5430 | if (frequency == 19200 || frequency == 624000 || | |
5431 | current_freq == 624000) { | |
5432 | I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE); | |
5433 | /* Timeout 200us */ | |
5434 | if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK), | |
5435 | 1)) | |
5436 | DRM_ERROR("timout waiting for DE PLL unlock\n"); | |
5437 | } | |
5438 | ||
5439 | if (frequency != 19200) { | |
5440 | uint32_t val; | |
5441 | ||
5442 | val = I915_READ(BXT_DE_PLL_CTL); | |
5443 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5444 | val |= ratio; | |
5445 | I915_WRITE(BXT_DE_PLL_CTL, val); | |
5446 | ||
5447 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5448 | /* Timeout 200us */ | |
5449 | if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1)) | |
5450 | DRM_ERROR("timeout waiting for DE PLL lock\n"); | |
5451 | ||
5452 | val = I915_READ(CDCLK_CTL); | |
5453 | val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK; | |
5454 | val |= divider; | |
5455 | /* | |
5456 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5457 | * enable otherwise. | |
5458 | */ | |
5459 | val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5460 | if (frequency >= 500000) | |
5461 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5462 | ||
5463 | val &= ~CDCLK_FREQ_DECIMAL_MASK; | |
5464 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ | |
5465 | val |= (frequency - 1000) / 500; | |
5466 | I915_WRITE(CDCLK_CTL, val); | |
5467 | } | |
5468 | ||
5469 | mutex_lock(&dev_priv->rps.hw_lock); | |
5470 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5471 | DIV_ROUND_UP(frequency, 25000)); | |
5472 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5473 | ||
5474 | if (ret) { | |
5475 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
5476 | ret, frequency); | |
5477 | return; | |
5478 | } | |
5479 | ||
a47871bd | 5480 | intel_update_cdclk(dev); |
f8437dd1 VK |
5481 | } |
5482 | ||
5483 | void broxton_init_cdclk(struct drm_device *dev) | |
5484 | { | |
5485 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5486 | uint32_t val; | |
5487 | ||
5488 | /* | |
5489 | * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT | |
5490 | * or else the reset will hang because there is no PCH to respond. | |
5491 | * Move the handshake programming to initialization sequence. | |
5492 | * Previously was left up to BIOS. | |
5493 | */ | |
5494 | val = I915_READ(HSW_NDE_RSTWRN_OPT); | |
5495 | val &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
5496 | I915_WRITE(HSW_NDE_RSTWRN_OPT, val); | |
5497 | ||
5498 | /* Enable PG1 for cdclk */ | |
5499 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); | |
5500 | ||
5501 | /* check if cd clock is enabled */ | |
5502 | if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) { | |
5503 | DRM_DEBUG_KMS("Display already initialized\n"); | |
5504 | return; | |
5505 | } | |
5506 | ||
5507 | /* | |
5508 | * FIXME: | |
5509 | * - The initial CDCLK needs to be read from VBT. | |
5510 | * Need to make this change after VBT has changes for BXT. | |
5511 | * - check if setting the max (or any) cdclk freq is really necessary | |
5512 | * here, it belongs to modeset time | |
5513 | */ | |
5514 | broxton_set_cdclk(dev, 624000); | |
5515 | ||
5516 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
22e02c0b VS |
5517 | POSTING_READ(DBUF_CTL); |
5518 | ||
f8437dd1 VK |
5519 | udelay(10); |
5520 | ||
5521 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5522 | DRM_ERROR("DBuf power enable timeout!\n"); | |
5523 | } | |
5524 | ||
5525 | void broxton_uninit_cdclk(struct drm_device *dev) | |
5526 | { | |
5527 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5528 | ||
5529 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
22e02c0b VS |
5530 | POSTING_READ(DBUF_CTL); |
5531 | ||
f8437dd1 VK |
5532 | udelay(10); |
5533 | ||
5534 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5535 | DRM_ERROR("DBuf power disable timeout!\n"); | |
5536 | ||
5537 | /* Set minimum (bypass) frequency, in effect turning off the DE PLL */ | |
5538 | broxton_set_cdclk(dev, 19200); | |
5539 | ||
5540 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
5541 | } | |
5542 | ||
5d96d8af DL |
5543 | static const struct skl_cdclk_entry { |
5544 | unsigned int freq; | |
5545 | unsigned int vco; | |
5546 | } skl_cdclk_frequencies[] = { | |
5547 | { .freq = 308570, .vco = 8640 }, | |
5548 | { .freq = 337500, .vco = 8100 }, | |
5549 | { .freq = 432000, .vco = 8640 }, | |
5550 | { .freq = 450000, .vco = 8100 }, | |
5551 | { .freq = 540000, .vco = 8100 }, | |
5552 | { .freq = 617140, .vco = 8640 }, | |
5553 | { .freq = 675000, .vco = 8100 }, | |
5554 | }; | |
5555 | ||
5556 | static unsigned int skl_cdclk_decimal(unsigned int freq) | |
5557 | { | |
5558 | return (freq - 1000) / 500; | |
5559 | } | |
5560 | ||
5561 | static unsigned int skl_cdclk_get_vco(unsigned int freq) | |
5562 | { | |
5563 | unsigned int i; | |
5564 | ||
5565 | for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) { | |
5566 | const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i]; | |
5567 | ||
5568 | if (e->freq == freq) | |
5569 | return e->vco; | |
5570 | } | |
5571 | ||
5572 | return 8100; | |
5573 | } | |
5574 | ||
5575 | static void | |
5576 | skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco) | |
5577 | { | |
5578 | unsigned int min_freq; | |
5579 | u32 val; | |
5580 | ||
5581 | /* select the minimum CDCLK before enabling DPLL 0 */ | |
5582 | val = I915_READ(CDCLK_CTL); | |
5583 | val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK; | |
5584 | val |= CDCLK_FREQ_337_308; | |
5585 | ||
5586 | if (required_vco == 8640) | |
5587 | min_freq = 308570; | |
5588 | else | |
5589 | min_freq = 337500; | |
5590 | ||
5591 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq); | |
5592 | ||
5593 | I915_WRITE(CDCLK_CTL, val); | |
5594 | POSTING_READ(CDCLK_CTL); | |
5595 | ||
5596 | /* | |
5597 | * We always enable DPLL0 with the lowest link rate possible, but still | |
5598 | * taking into account the VCO required to operate the eDP panel at the | |
5599 | * desired frequency. The usual DP link rates operate with a VCO of | |
5600 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. | |
5601 | * The modeset code is responsible for the selection of the exact link | |
5602 | * rate later on, with the constraint of choosing a frequency that | |
5603 | * works with required_vco. | |
5604 | */ | |
5605 | val = I915_READ(DPLL_CTRL1); | |
5606 | ||
5607 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
5608 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
5609 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
5610 | if (required_vco == 8640) | |
5611 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, | |
5612 | SKL_DPLL0); | |
5613 | else | |
5614 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, | |
5615 | SKL_DPLL0); | |
5616 | ||
5617 | I915_WRITE(DPLL_CTRL1, val); | |
5618 | POSTING_READ(DPLL_CTRL1); | |
5619 | ||
5620 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); | |
5621 | ||
5622 | if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5)) | |
5623 | DRM_ERROR("DPLL0 not locked\n"); | |
5624 | } | |
5625 | ||
5626 | static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) | |
5627 | { | |
5628 | int ret; | |
5629 | u32 val; | |
5630 | ||
5631 | /* inform PCU we want to change CDCLK */ | |
5632 | val = SKL_CDCLK_PREPARE_FOR_CHANGE; | |
5633 | mutex_lock(&dev_priv->rps.hw_lock); | |
5634 | ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); | |
5635 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5636 | ||
5637 | return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE); | |
5638 | } | |
5639 | ||
5640 | static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) | |
5641 | { | |
5642 | unsigned int i; | |
5643 | ||
5644 | for (i = 0; i < 15; i++) { | |
5645 | if (skl_cdclk_pcu_ready(dev_priv)) | |
5646 | return true; | |
5647 | udelay(10); | |
5648 | } | |
5649 | ||
5650 | return false; | |
5651 | } | |
5652 | ||
5653 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq) | |
5654 | { | |
560a7ae4 | 5655 | struct drm_device *dev = dev_priv->dev; |
5d96d8af DL |
5656 | u32 freq_select, pcu_ack; |
5657 | ||
5658 | DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq); | |
5659 | ||
5660 | if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { | |
5661 | DRM_ERROR("failed to inform PCU about cdclk change\n"); | |
5662 | return; | |
5663 | } | |
5664 | ||
5665 | /* set CDCLK_CTL */ | |
5666 | switch(freq) { | |
5667 | case 450000: | |
5668 | case 432000: | |
5669 | freq_select = CDCLK_FREQ_450_432; | |
5670 | pcu_ack = 1; | |
5671 | break; | |
5672 | case 540000: | |
5673 | freq_select = CDCLK_FREQ_540; | |
5674 | pcu_ack = 2; | |
5675 | break; | |
5676 | case 308570: | |
5677 | case 337500: | |
5678 | default: | |
5679 | freq_select = CDCLK_FREQ_337_308; | |
5680 | pcu_ack = 0; | |
5681 | break; | |
5682 | case 617140: | |
5683 | case 675000: | |
5684 | freq_select = CDCLK_FREQ_675_617; | |
5685 | pcu_ack = 3; | |
5686 | break; | |
5687 | } | |
5688 | ||
5689 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq)); | |
5690 | POSTING_READ(CDCLK_CTL); | |
5691 | ||
5692 | /* inform PCU of the change */ | |
5693 | mutex_lock(&dev_priv->rps.hw_lock); | |
5694 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); | |
5695 | mutex_unlock(&dev_priv->rps.hw_lock); | |
560a7ae4 DL |
5696 | |
5697 | intel_update_cdclk(dev); | |
5d96d8af DL |
5698 | } |
5699 | ||
5700 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) | |
5701 | { | |
5702 | /* disable DBUF power */ | |
5703 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
5704 | POSTING_READ(DBUF_CTL); | |
5705 | ||
5706 | udelay(10); | |
5707 | ||
5708 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5709 | DRM_ERROR("DBuf power disable timeout\n"); | |
5710 | ||
4e961e42 AM |
5711 | /* |
5712 | * DMC assumes ownership of LCPLL and will get confused if we touch it. | |
5713 | */ | |
5714 | if (dev_priv->csr.dmc_payload) { | |
5715 | /* disable DPLL0 */ | |
5716 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & | |
5717 | ~LCPLL_PLL_ENABLE); | |
5718 | if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) | |
5719 | DRM_ERROR("Couldn't disable DPLL0\n"); | |
5720 | } | |
5d96d8af DL |
5721 | |
5722 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
5723 | } | |
5724 | ||
5725 | void skl_init_cdclk(struct drm_i915_private *dev_priv) | |
5726 | { | |
5727 | u32 val; | |
5728 | unsigned int required_vco; | |
5729 | ||
5730 | /* enable PCH reset handshake */ | |
5731 | val = I915_READ(HSW_NDE_RSTWRN_OPT); | |
5732 | I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE); | |
5733 | ||
5734 | /* enable PG1 and Misc I/O */ | |
5735 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); | |
5736 | ||
39d9b85a GW |
5737 | /* DPLL0 not enabled (happens on early BIOS versions) */ |
5738 | if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) { | |
5739 | /* enable DPLL0 */ | |
5740 | required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk); | |
5741 | skl_dpll0_enable(dev_priv, required_vco); | |
5d96d8af DL |
5742 | } |
5743 | ||
5d96d8af DL |
5744 | /* set CDCLK to the frequency the BIOS chose */ |
5745 | skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk); | |
5746 | ||
5747 | /* enable DBUF power */ | |
5748 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
5749 | POSTING_READ(DBUF_CTL); | |
5750 | ||
5751 | udelay(10); | |
5752 | ||
5753 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5754 | DRM_ERROR("DBuf power enable timeout\n"); | |
5755 | } | |
5756 | ||
dfcab17e | 5757 | /* returns HPLL frequency in kHz */ |
f8bf63fd | 5758 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) |
30a970c6 | 5759 | { |
586f49dc | 5760 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
30a970c6 | 5761 | |
586f49dc | 5762 | /* Obtain SKU information */ |
a580516d | 5763 | mutex_lock(&dev_priv->sb_lock); |
586f49dc JB |
5764 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & |
5765 | CCK_FUSE_HPLL_FREQ_MASK; | |
a580516d | 5766 | mutex_unlock(&dev_priv->sb_lock); |
30a970c6 | 5767 | |
dfcab17e | 5768 | return vco_freq[hpll_freq] * 1000; |
30a970c6 JB |
5769 | } |
5770 | ||
5771 | /* Adjust CDclk dividers to allow high res or save power if possible */ | |
5772 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
5773 | { | |
5774 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5775 | u32 val, cmd; | |
5776 | ||
164dfd28 VK |
5777 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5778 | != dev_priv->cdclk_freq); | |
d60c4473 | 5779 | |
dfcab17e | 5780 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 5781 | cmd = 2; |
dfcab17e | 5782 | else if (cdclk == 266667) |
30a970c6 JB |
5783 | cmd = 1; |
5784 | else | |
5785 | cmd = 0; | |
5786 | ||
5787 | mutex_lock(&dev_priv->rps.hw_lock); | |
5788 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5789 | val &= ~DSPFREQGUAR_MASK; | |
5790 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
5791 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5792 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5793 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
5794 | 50)) { | |
5795 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5796 | } | |
5797 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5798 | ||
54433e91 VS |
5799 | mutex_lock(&dev_priv->sb_lock); |
5800 | ||
dfcab17e | 5801 | if (cdclk == 400000) { |
6bcda4f0 | 5802 | u32 divider; |
30a970c6 | 5803 | |
6bcda4f0 | 5804 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 | 5805 | |
30a970c6 JB |
5806 | /* adjust cdclk divider */ |
5807 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
9cf33db5 | 5808 | val &= ~DISPLAY_FREQUENCY_VALUES; |
30a970c6 JB |
5809 | val |= divider; |
5810 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
5811 | |
5812 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
5813 | DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
5814 | 50)) | |
5815 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
5816 | } |
5817 | ||
30a970c6 JB |
5818 | /* adjust self-refresh exit latency value */ |
5819 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
5820 | val &= ~0x7f; | |
5821 | ||
5822 | /* | |
5823 | * For high bandwidth configs, we set a higher latency in the bunit | |
5824 | * so that the core display fetch happens in time to avoid underruns. | |
5825 | */ | |
dfcab17e | 5826 | if (cdclk == 400000) |
30a970c6 JB |
5827 | val |= 4500 / 250; /* 4.5 usec */ |
5828 | else | |
5829 | val |= 3000 / 250; /* 3.0 usec */ | |
5830 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
54433e91 | 5831 | |
a580516d | 5832 | mutex_unlock(&dev_priv->sb_lock); |
30a970c6 | 5833 | |
b6283055 | 5834 | intel_update_cdclk(dev); |
30a970c6 JB |
5835 | } |
5836 | ||
383c5a6a VS |
5837 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
5838 | { | |
5839 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5840 | u32 val, cmd; | |
5841 | ||
164dfd28 VK |
5842 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5843 | != dev_priv->cdclk_freq); | |
383c5a6a VS |
5844 | |
5845 | switch (cdclk) { | |
383c5a6a VS |
5846 | case 333333: |
5847 | case 320000: | |
383c5a6a | 5848 | case 266667: |
383c5a6a | 5849 | case 200000: |
383c5a6a VS |
5850 | break; |
5851 | default: | |
5f77eeb0 | 5852 | MISSING_CASE(cdclk); |
383c5a6a VS |
5853 | return; |
5854 | } | |
5855 | ||
9d0d3fda VS |
5856 | /* |
5857 | * Specs are full of misinformation, but testing on actual | |
5858 | * hardware has shown that we just need to write the desired | |
5859 | * CCK divider into the Punit register. | |
5860 | */ | |
5861 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
5862 | ||
383c5a6a VS |
5863 | mutex_lock(&dev_priv->rps.hw_lock); |
5864 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5865 | val &= ~DSPFREQGUAR_MASK_CHV; | |
5866 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
5867 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5868 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5869 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
5870 | 50)) { | |
5871 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5872 | } | |
5873 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5874 | ||
b6283055 | 5875 | intel_update_cdclk(dev); |
383c5a6a VS |
5876 | } |
5877 | ||
30a970c6 JB |
5878 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
5879 | int max_pixclk) | |
5880 | { | |
6bcda4f0 | 5881 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 5882 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 5883 | |
30a970c6 JB |
5884 | /* |
5885 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
5886 | * 200MHz | |
5887 | * 267MHz | |
29dc7ef3 | 5888 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
5889 | * 400MHz (VLV only) |
5890 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
5891 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
5892 | * |
5893 | * We seem to get an unstable or solid color picture at 200MHz. | |
5894 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
5895 | * are off. | |
30a970c6 | 5896 | */ |
6cca3195 VS |
5897 | if (!IS_CHERRYVIEW(dev_priv) && |
5898 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 5899 | return 400000; |
6cca3195 | 5900 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 5901 | return freq_320; |
e37c67a1 | 5902 | else if (max_pixclk > 0) |
dfcab17e | 5903 | return 266667; |
e37c67a1 VS |
5904 | else |
5905 | return 200000; | |
30a970c6 JB |
5906 | } |
5907 | ||
f8437dd1 VK |
5908 | static int broxton_calc_cdclk(struct drm_i915_private *dev_priv, |
5909 | int max_pixclk) | |
5910 | { | |
5911 | /* | |
5912 | * FIXME: | |
5913 | * - remove the guardband, it's not needed on BXT | |
5914 | * - set 19.2MHz bypass frequency if there are no active pipes | |
5915 | */ | |
5916 | if (max_pixclk > 576000*9/10) | |
5917 | return 624000; | |
5918 | else if (max_pixclk > 384000*9/10) | |
5919 | return 576000; | |
5920 | else if (max_pixclk > 288000*9/10) | |
5921 | return 384000; | |
5922 | else if (max_pixclk > 144000*9/10) | |
5923 | return 288000; | |
5924 | else | |
5925 | return 144000; | |
5926 | } | |
5927 | ||
a821fc46 ACO |
5928 | /* Compute the max pixel clock for new configuration. Uses atomic state if |
5929 | * that's non-NULL, look at current state otherwise. */ | |
5930 | static int intel_mode_max_pixclk(struct drm_device *dev, | |
5931 | struct drm_atomic_state *state) | |
30a970c6 | 5932 | { |
30a970c6 | 5933 | struct intel_crtc *intel_crtc; |
304603f4 | 5934 | struct intel_crtc_state *crtc_state; |
30a970c6 JB |
5935 | int max_pixclk = 0; |
5936 | ||
d3fcc808 | 5937 | for_each_intel_crtc(dev, intel_crtc) { |
27c329ed | 5938 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
304603f4 ACO |
5939 | if (IS_ERR(crtc_state)) |
5940 | return PTR_ERR(crtc_state); | |
5941 | ||
5942 | if (!crtc_state->base.enable) | |
5943 | continue; | |
5944 | ||
5945 | max_pixclk = max(max_pixclk, | |
5946 | crtc_state->base.adjusted_mode.crtc_clock); | |
30a970c6 JB |
5947 | } |
5948 | ||
5949 | return max_pixclk; | |
5950 | } | |
5951 | ||
27c329ed | 5952 | static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) |
30a970c6 | 5953 | { |
27c329ed ML |
5954 | struct drm_device *dev = state->dev; |
5955 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5956 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
30a970c6 | 5957 | |
304603f4 ACO |
5958 | if (max_pixclk < 0) |
5959 | return max_pixclk; | |
30a970c6 | 5960 | |
27c329ed ML |
5961 | to_intel_atomic_state(state)->cdclk = |
5962 | valleyview_calc_cdclk(dev_priv, max_pixclk); | |
0a9ab303 | 5963 | |
27c329ed ML |
5964 | return 0; |
5965 | } | |
304603f4 | 5966 | |
27c329ed ML |
5967 | static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state) |
5968 | { | |
5969 | struct drm_device *dev = state->dev; | |
5970 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5971 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
85a96e7a | 5972 | |
27c329ed ML |
5973 | if (max_pixclk < 0) |
5974 | return max_pixclk; | |
85a96e7a | 5975 | |
27c329ed ML |
5976 | to_intel_atomic_state(state)->cdclk = |
5977 | broxton_calc_cdclk(dev_priv, max_pixclk); | |
85a96e7a | 5978 | |
27c329ed | 5979 | return 0; |
30a970c6 JB |
5980 | } |
5981 | ||
1e69cd74 VS |
5982 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
5983 | { | |
5984 | unsigned int credits, default_credits; | |
5985 | ||
5986 | if (IS_CHERRYVIEW(dev_priv)) | |
5987 | default_credits = PFI_CREDIT(12); | |
5988 | else | |
5989 | default_credits = PFI_CREDIT(8); | |
5990 | ||
164dfd28 | 5991 | if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) { |
1e69cd74 VS |
5992 | /* CHV suggested value is 31 or 63 */ |
5993 | if (IS_CHERRYVIEW(dev_priv)) | |
fcc0008f | 5994 | credits = PFI_CREDIT_63; |
1e69cd74 VS |
5995 | else |
5996 | credits = PFI_CREDIT(15); | |
5997 | } else { | |
5998 | credits = default_credits; | |
5999 | } | |
6000 | ||
6001 | /* | |
6002 | * WA - write default credits before re-programming | |
6003 | * FIXME: should we also set the resend bit here? | |
6004 | */ | |
6005 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6006 | default_credits); | |
6007 | ||
6008 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6009 | credits | PFI_CREDIT_RESEND); | |
6010 | ||
6011 | /* | |
6012 | * FIXME is this guaranteed to clear | |
6013 | * immediately or should we poll for it? | |
6014 | */ | |
6015 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
6016 | } | |
6017 | ||
27c329ed | 6018 | static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
30a970c6 | 6019 | { |
a821fc46 | 6020 | struct drm_device *dev = old_state->dev; |
27c329ed | 6021 | unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk; |
30a970c6 | 6022 | struct drm_i915_private *dev_priv = dev->dev_private; |
30a970c6 | 6023 | |
27c329ed ML |
6024 | /* |
6025 | * FIXME: We can end up here with all power domains off, yet | |
6026 | * with a CDCLK frequency other than the minimum. To account | |
6027 | * for this take the PIPE-A power domain, which covers the HW | |
6028 | * blocks needed for the following programming. This can be | |
6029 | * removed once it's guaranteed that we get here either with | |
6030 | * the minimum CDCLK set, or the required power domains | |
6031 | * enabled. | |
6032 | */ | |
6033 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
738c05c0 | 6034 | |
27c329ed ML |
6035 | if (IS_CHERRYVIEW(dev)) |
6036 | cherryview_set_cdclk(dev, req_cdclk); | |
6037 | else | |
6038 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 6039 | |
27c329ed | 6040 | vlv_program_pfi_credits(dev_priv); |
1e69cd74 | 6041 | |
27c329ed | 6042 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
30a970c6 JB |
6043 | } |
6044 | ||
89b667f8 JB |
6045 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
6046 | { | |
6047 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6048 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
6049 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6050 | struct intel_encoder *encoder; | |
6051 | int pipe = intel_crtc->pipe; | |
23538ef1 | 6052 | bool is_dsi; |
89b667f8 | 6053 | |
53d9f4e9 | 6054 | if (WARN_ON(intel_crtc->active)) |
89b667f8 JB |
6055 | return; |
6056 | ||
409ee761 | 6057 | is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI); |
8525a235 | 6058 | |
6e3c9717 | 6059 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6060 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6061 | |
6062 | intel_set_pipe_timings(intel_crtc); | |
6063 | ||
c14b0485 VS |
6064 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
6065 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6066 | ||
6067 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
6068 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
6069 | } | |
6070 | ||
5b18e57c DV |
6071 | i9xx_set_pipeconf(intel_crtc); |
6072 | ||
89b667f8 | 6073 | intel_crtc->active = true; |
89b667f8 | 6074 | |
a72e4c9f | 6075 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6076 | |
89b667f8 JB |
6077 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6078 | if (encoder->pre_pll_enable) | |
6079 | encoder->pre_pll_enable(encoder); | |
6080 | ||
9d556c99 | 6081 | if (!is_dsi) { |
c0b4c660 VS |
6082 | if (IS_CHERRYVIEW(dev)) { |
6083 | chv_prepare_pll(intel_crtc, intel_crtc->config); | |
6e3c9717 | 6084 | chv_enable_pll(intel_crtc, intel_crtc->config); |
c0b4c660 VS |
6085 | } else { |
6086 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
6e3c9717 | 6087 | vlv_enable_pll(intel_crtc, intel_crtc->config); |
c0b4c660 | 6088 | } |
9d556c99 | 6089 | } |
89b667f8 JB |
6090 | |
6091 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
6092 | if (encoder->pre_enable) | |
6093 | encoder->pre_enable(encoder); | |
6094 | ||
2dd24552 JB |
6095 | i9xx_pfit_enable(intel_crtc); |
6096 | ||
63cbb074 VS |
6097 | intel_crtc_load_lut(crtc); |
6098 | ||
e1fdc473 | 6099 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6100 | |
4b3a9526 VS |
6101 | assert_vblank_disabled(crtc); |
6102 | drm_crtc_vblank_on(crtc); | |
6103 | ||
f9b61ff6 DV |
6104 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6105 | encoder->enable(encoder); | |
89b667f8 JB |
6106 | } |
6107 | ||
f13c2ef3 DV |
6108 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
6109 | { | |
6110 | struct drm_device *dev = crtc->base.dev; | |
6111 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6112 | ||
6e3c9717 ACO |
6113 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
6114 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
6115 | } |
6116 | ||
0b8765c6 | 6117 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
6118 | { |
6119 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6120 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 6121 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 6122 | struct intel_encoder *encoder; |
79e53945 | 6123 | int pipe = intel_crtc->pipe; |
79e53945 | 6124 | |
53d9f4e9 | 6125 | if (WARN_ON(intel_crtc->active)) |
f7abfe8b CW |
6126 | return; |
6127 | ||
f13c2ef3 DV |
6128 | i9xx_set_pll_dividers(intel_crtc); |
6129 | ||
6e3c9717 | 6130 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6131 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6132 | |
6133 | intel_set_pipe_timings(intel_crtc); | |
6134 | ||
5b18e57c DV |
6135 | i9xx_set_pipeconf(intel_crtc); |
6136 | ||
f7abfe8b | 6137 | intel_crtc->active = true; |
6b383a7f | 6138 | |
4a3436e8 | 6139 | if (!IS_GEN2(dev)) |
a72e4c9f | 6140 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6141 | |
9d6d9f19 MK |
6142 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6143 | if (encoder->pre_enable) | |
6144 | encoder->pre_enable(encoder); | |
6145 | ||
f6736a1a DV |
6146 | i9xx_enable_pll(intel_crtc); |
6147 | ||
2dd24552 JB |
6148 | i9xx_pfit_enable(intel_crtc); |
6149 | ||
63cbb074 VS |
6150 | intel_crtc_load_lut(crtc); |
6151 | ||
f37fcc2a | 6152 | intel_update_watermarks(crtc); |
e1fdc473 | 6153 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6154 | |
4b3a9526 VS |
6155 | assert_vblank_disabled(crtc); |
6156 | drm_crtc_vblank_on(crtc); | |
6157 | ||
f9b61ff6 DV |
6158 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6159 | encoder->enable(encoder); | |
0b8765c6 | 6160 | } |
79e53945 | 6161 | |
87476d63 DV |
6162 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
6163 | { | |
6164 | struct drm_device *dev = crtc->base.dev; | |
6165 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 6166 | |
6e3c9717 | 6167 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 6168 | return; |
87476d63 | 6169 | |
328d8e82 | 6170 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 6171 | |
328d8e82 DV |
6172 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
6173 | I915_READ(PFIT_CONTROL)); | |
6174 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
6175 | } |
6176 | ||
0b8765c6 JB |
6177 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
6178 | { | |
6179 | struct drm_device *dev = crtc->dev; | |
6180 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6181 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 6182 | struct intel_encoder *encoder; |
0b8765c6 | 6183 | int pipe = intel_crtc->pipe; |
ef9c3aee | 6184 | |
6304cd91 VS |
6185 | /* |
6186 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
6187 | * wait for planes to fully turn off before disabling the pipe. | |
564ed191 ID |
6188 | * We also need to wait on all gmch platforms because of the |
6189 | * self-refresh mode constraint explained above. | |
6304cd91 | 6190 | */ |
564ed191 | 6191 | intel_wait_for_vblank(dev, pipe); |
6304cd91 | 6192 | |
4b3a9526 VS |
6193 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6194 | encoder->disable(encoder); | |
6195 | ||
f9b61ff6 DV |
6196 | drm_crtc_vblank_off(crtc); |
6197 | assert_vblank_disabled(crtc); | |
6198 | ||
575f7ab7 | 6199 | intel_disable_pipe(intel_crtc); |
24a1f16d | 6200 | |
87476d63 | 6201 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 6202 | |
89b667f8 JB |
6203 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6204 | if (encoder->post_disable) | |
6205 | encoder->post_disable(encoder); | |
6206 | ||
409ee761 | 6207 | if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) { |
076ed3b2 CML |
6208 | if (IS_CHERRYVIEW(dev)) |
6209 | chv_disable_pll(dev_priv, pipe); | |
6210 | else if (IS_VALLEYVIEW(dev)) | |
6211 | vlv_disable_pll(dev_priv, pipe); | |
6212 | else | |
1c4e0274 | 6213 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 6214 | } |
0b8765c6 | 6215 | |
d6db995f VS |
6216 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6217 | if (encoder->post_pll_disable) | |
6218 | encoder->post_pll_disable(encoder); | |
6219 | ||
4a3436e8 | 6220 | if (!IS_GEN2(dev)) |
a72e4c9f | 6221 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
e4ca0612 PJ |
6222 | |
6223 | intel_crtc->active = false; | |
6224 | intel_update_watermarks(crtc); | |
0b8765c6 JB |
6225 | } |
6226 | ||
b17d48e2 ML |
6227 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
6228 | { | |
6229 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6230 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
6231 | enum intel_display_power_domain domain; | |
6232 | unsigned long domains; | |
6233 | ||
6234 | if (!intel_crtc->active) | |
6235 | return; | |
6236 | ||
a539205a ML |
6237 | if (to_intel_plane_state(crtc->primary->state)->visible) { |
6238 | intel_crtc_wait_for_pending_flips(crtc); | |
6239 | intel_pre_disable_primary(crtc); | |
6240 | } | |
6241 | ||
d032ffa0 | 6242 | intel_crtc_disable_planes(crtc, crtc->state->plane_mask); |
b17d48e2 | 6243 | dev_priv->display.crtc_disable(crtc); |
1f7457b1 | 6244 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
6245 | |
6246 | domains = intel_crtc->enabled_power_domains; | |
6247 | for_each_power_domain(domain, domains) | |
6248 | intel_display_power_put(dev_priv, domain); | |
6249 | intel_crtc->enabled_power_domains = 0; | |
6250 | } | |
6251 | ||
6b72d486 ML |
6252 | /* |
6253 | * turn all crtc's off, but do not adjust state | |
6254 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
6255 | */ | |
70e0bd74 | 6256 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 6257 | { |
70e0bd74 ML |
6258 | struct drm_mode_config *config = &dev->mode_config; |
6259 | struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx; | |
6260 | struct drm_atomic_state *state; | |
6b72d486 | 6261 | struct drm_crtc *crtc; |
70e0bd74 ML |
6262 | unsigned crtc_mask = 0; |
6263 | int ret = 0; | |
6264 | ||
6265 | if (WARN_ON(!ctx)) | |
6266 | return 0; | |
6267 | ||
6268 | lockdep_assert_held(&ctx->ww_ctx); | |
6269 | state = drm_atomic_state_alloc(dev); | |
6270 | if (WARN_ON(!state)) | |
6271 | return -ENOMEM; | |
6272 | ||
6273 | state->acquire_ctx = ctx; | |
6274 | state->allow_modeset = true; | |
6275 | ||
6276 | for_each_crtc(dev, crtc) { | |
6277 | struct drm_crtc_state *crtc_state = | |
6278 | drm_atomic_get_crtc_state(state, crtc); | |
6b72d486 | 6279 | |
70e0bd74 ML |
6280 | ret = PTR_ERR_OR_ZERO(crtc_state); |
6281 | if (ret) | |
6282 | goto free; | |
6283 | ||
6284 | if (!crtc_state->active) | |
6285 | continue; | |
6286 | ||
6287 | crtc_state->active = false; | |
6288 | crtc_mask |= 1 << drm_crtc_index(crtc); | |
6289 | } | |
6290 | ||
6291 | if (crtc_mask) { | |
74c090b1 | 6292 | ret = drm_atomic_commit(state); |
70e0bd74 ML |
6293 | |
6294 | if (!ret) { | |
6295 | for_each_crtc(dev, crtc) | |
6296 | if (crtc_mask & (1 << drm_crtc_index(crtc))) | |
6297 | crtc->state->active = true; | |
6298 | ||
6299 | return ret; | |
6300 | } | |
6301 | } | |
6302 | ||
6303 | free: | |
6304 | if (ret) | |
6305 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
6306 | drm_atomic_state_free(state); | |
6307 | return ret; | |
ee7b9f93 JB |
6308 | } |
6309 | ||
ea5b213a | 6310 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6311 | { |
4ef69c7a | 6312 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6313 | |
ea5b213a CW |
6314 | drm_encoder_cleanup(encoder); |
6315 | kfree(intel_encoder); | |
7e7d76c3 JB |
6316 | } |
6317 | ||
0a91ca29 DV |
6318 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6319 | * internal consistency). */ | |
b980514c | 6320 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 6321 | { |
35dd3c64 ML |
6322 | struct drm_crtc *crtc = connector->base.state->crtc; |
6323 | ||
6324 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6325 | connector->base.base.id, | |
6326 | connector->base.name); | |
6327 | ||
0a91ca29 | 6328 | if (connector->get_hw_state(connector)) { |
e85376cb | 6329 | struct intel_encoder *encoder = connector->encoder; |
35dd3c64 | 6330 | struct drm_connector_state *conn_state = connector->base.state; |
0a91ca29 | 6331 | |
35dd3c64 ML |
6332 | I915_STATE_WARN(!crtc, |
6333 | "connector enabled without attached crtc\n"); | |
0a91ca29 | 6334 | |
35dd3c64 ML |
6335 | if (!crtc) |
6336 | return; | |
6337 | ||
6338 | I915_STATE_WARN(!crtc->state->active, | |
6339 | "connector is active, but attached crtc isn't\n"); | |
6340 | ||
e85376cb | 6341 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
6342 | return; |
6343 | ||
e85376cb | 6344 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
6345 | "atomic encoder doesn't match attached encoder\n"); |
6346 | ||
e85376cb | 6347 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
6348 | "attached encoder crtc differs from connector crtc\n"); |
6349 | } else { | |
4d688a2a ML |
6350 | I915_STATE_WARN(crtc && crtc->state->active, |
6351 | "attached crtc is active, but connector isn't\n"); | |
35dd3c64 ML |
6352 | I915_STATE_WARN(!crtc && connector->base.state->best_encoder, |
6353 | "best encoder set without crtc!\n"); | |
0a91ca29 | 6354 | } |
79e53945 JB |
6355 | } |
6356 | ||
08d9bc92 ACO |
6357 | int intel_connector_init(struct intel_connector *connector) |
6358 | { | |
6359 | struct drm_connector_state *connector_state; | |
6360 | ||
6361 | connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL); | |
6362 | if (!connector_state) | |
6363 | return -ENOMEM; | |
6364 | ||
6365 | connector->base.state = connector_state; | |
6366 | return 0; | |
6367 | } | |
6368 | ||
6369 | struct intel_connector *intel_connector_alloc(void) | |
6370 | { | |
6371 | struct intel_connector *connector; | |
6372 | ||
6373 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6374 | if (!connector) | |
6375 | return NULL; | |
6376 | ||
6377 | if (intel_connector_init(connector) < 0) { | |
6378 | kfree(connector); | |
6379 | return NULL; | |
6380 | } | |
6381 | ||
6382 | return connector; | |
6383 | } | |
6384 | ||
f0947c37 DV |
6385 | /* Simple connector->get_hw_state implementation for encoders that support only |
6386 | * one connector and no cloning and hence the encoder state determines the state | |
6387 | * of the connector. */ | |
6388 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6389 | { |
24929352 | 6390 | enum pipe pipe = 0; |
f0947c37 | 6391 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6392 | |
f0947c37 | 6393 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6394 | } |
6395 | ||
6d293983 | 6396 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6397 | { |
6d293983 ACO |
6398 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6399 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6400 | |
6401 | return 0; | |
6402 | } | |
6403 | ||
6d293983 | 6404 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6405 | struct intel_crtc_state *pipe_config) |
1857e1da | 6406 | { |
6d293983 ACO |
6407 | struct drm_atomic_state *state = pipe_config->base.state; |
6408 | struct intel_crtc *other_crtc; | |
6409 | struct intel_crtc_state *other_crtc_state; | |
6410 | ||
1857e1da DV |
6411 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6412 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6413 | if (pipe_config->fdi_lanes > 4) { | |
6414 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6415 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6416 | return -EINVAL; |
1857e1da DV |
6417 | } |
6418 | ||
bafb6553 | 6419 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
6420 | if (pipe_config->fdi_lanes > 2) { |
6421 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6422 | pipe_config->fdi_lanes); | |
6d293983 | 6423 | return -EINVAL; |
1857e1da | 6424 | } else { |
6d293983 | 6425 | return 0; |
1857e1da DV |
6426 | } |
6427 | } | |
6428 | ||
6429 | if (INTEL_INFO(dev)->num_pipes == 2) | |
6d293983 | 6430 | return 0; |
1857e1da DV |
6431 | |
6432 | /* Ivybridge 3 pipe is really complicated */ | |
6433 | switch (pipe) { | |
6434 | case PIPE_A: | |
6d293983 | 6435 | return 0; |
1857e1da | 6436 | case PIPE_B: |
6d293983 ACO |
6437 | if (pipe_config->fdi_lanes <= 2) |
6438 | return 0; | |
6439 | ||
6440 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); | |
6441 | other_crtc_state = | |
6442 | intel_atomic_get_crtc_state(state, other_crtc); | |
6443 | if (IS_ERR(other_crtc_state)) | |
6444 | return PTR_ERR(other_crtc_state); | |
6445 | ||
6446 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6447 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6448 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6449 | return -EINVAL; |
1857e1da | 6450 | } |
6d293983 | 6451 | return 0; |
1857e1da | 6452 | case PIPE_C: |
251cc67c VS |
6453 | if (pipe_config->fdi_lanes > 2) { |
6454 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6455 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6456 | return -EINVAL; |
251cc67c | 6457 | } |
6d293983 ACO |
6458 | |
6459 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); | |
6460 | other_crtc_state = | |
6461 | intel_atomic_get_crtc_state(state, other_crtc); | |
6462 | if (IS_ERR(other_crtc_state)) | |
6463 | return PTR_ERR(other_crtc_state); | |
6464 | ||
6465 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6466 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6467 | return -EINVAL; |
1857e1da | 6468 | } |
6d293983 | 6469 | return 0; |
1857e1da DV |
6470 | default: |
6471 | BUG(); | |
6472 | } | |
6473 | } | |
6474 | ||
e29c22c0 DV |
6475 | #define RETRY 1 |
6476 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6477 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6478 | { |
1857e1da | 6479 | struct drm_device *dev = intel_crtc->base.dev; |
2d112de7 | 6480 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6481 | int lane, link_bw, fdi_dotclock, ret; |
6482 | bool needs_recompute = false; | |
877d48d5 | 6483 | |
e29c22c0 | 6484 | retry: |
877d48d5 DV |
6485 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6486 | * each output octet as 10 bits. The actual frequency | |
6487 | * is stored as a divider into a 100MHz clock, and the | |
6488 | * mode pixel clock is stored in units of 1KHz. | |
6489 | * Hence the bw of each lane in terms of the mode signal | |
6490 | * is: | |
6491 | */ | |
6492 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
6493 | ||
241bfc38 | 6494 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6495 | |
2bd89a07 | 6496 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6497 | pipe_config->pipe_bpp); |
6498 | ||
6499 | pipe_config->fdi_lanes = lane; | |
6500 | ||
2bd89a07 | 6501 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 6502 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 6503 | |
6d293983 ACO |
6504 | ret = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
6505 | intel_crtc->pipe, pipe_config); | |
6506 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { | |
e29c22c0 DV |
6507 | pipe_config->pipe_bpp -= 2*3; |
6508 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
6509 | pipe_config->pipe_bpp); | |
6510 | needs_recompute = true; | |
6511 | pipe_config->bw_constrained = true; | |
6512 | ||
6513 | goto retry; | |
6514 | } | |
6515 | ||
6516 | if (needs_recompute) | |
6517 | return RETRY; | |
6518 | ||
6d293983 | 6519 | return ret; |
877d48d5 DV |
6520 | } |
6521 | ||
8cfb3407 VS |
6522 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
6523 | struct intel_crtc_state *pipe_config) | |
6524 | { | |
6525 | if (pipe_config->pipe_bpp > 24) | |
6526 | return false; | |
6527 | ||
6528 | /* HSW can handle pixel rate up to cdclk? */ | |
6529 | if (IS_HASWELL(dev_priv->dev)) | |
6530 | return true; | |
6531 | ||
6532 | /* | |
b432e5cf VS |
6533 | * We compare against max which means we must take |
6534 | * the increased cdclk requirement into account when | |
6535 | * calculating the new cdclk. | |
6536 | * | |
6537 | * Should measure whether using a lower cdclk w/o IPS | |
8cfb3407 VS |
6538 | */ |
6539 | return ilk_pipe_pixel_rate(pipe_config) <= | |
6540 | dev_priv->max_cdclk_freq * 95 / 100; | |
6541 | } | |
6542 | ||
42db64ef | 6543 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 6544 | struct intel_crtc_state *pipe_config) |
42db64ef | 6545 | { |
8cfb3407 VS |
6546 | struct drm_device *dev = crtc->base.dev; |
6547 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6548 | ||
d330a953 | 6549 | pipe_config->ips_enabled = i915.enable_ips && |
8cfb3407 VS |
6550 | hsw_crtc_supports_ips(crtc) && |
6551 | pipe_config_supports_ips(dev_priv, pipe_config); | |
42db64ef PZ |
6552 | } |
6553 | ||
a43f6e0f | 6554 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 6555 | struct intel_crtc_state *pipe_config) |
79e53945 | 6556 | { |
a43f6e0f | 6557 | struct drm_device *dev = crtc->base.dev; |
8bd31e67 | 6558 | struct drm_i915_private *dev_priv = dev->dev_private; |
2d112de7 | 6559 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
89749350 | 6560 | |
ad3a4479 | 6561 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 | 6562 | if (INTEL_INFO(dev)->gen < 4) { |
44913155 | 6563 | int clock_limit = dev_priv->max_cdclk_freq; |
cf532bb2 VS |
6564 | |
6565 | /* | |
6566 | * Enable pixel doubling when the dot clock | |
6567 | * is > 90% of the (display) core speed. | |
6568 | * | |
b397c96b VS |
6569 | * GDG double wide on either pipe, |
6570 | * otherwise pipe A only. | |
cf532bb2 | 6571 | */ |
b397c96b | 6572 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
241bfc38 | 6573 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
ad3a4479 | 6574 | clock_limit *= 2; |
cf532bb2 | 6575 | pipe_config->double_wide = true; |
ad3a4479 VS |
6576 | } |
6577 | ||
241bfc38 | 6578 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
e29c22c0 | 6579 | return -EINVAL; |
2c07245f | 6580 | } |
89749350 | 6581 | |
1d1d0e27 VS |
6582 | /* |
6583 | * Pipe horizontal size must be even in: | |
6584 | * - DVO ganged mode | |
6585 | * - LVDS dual channel mode | |
6586 | * - Double wide pipe | |
6587 | */ | |
a93e255f | 6588 | if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
6589 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
6590 | pipe_config->pipe_src_w &= ~1; | |
6591 | ||
8693a824 DL |
6592 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6593 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
6594 | */ |
6595 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
6596 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
e29c22c0 | 6597 | return -EINVAL; |
44f46b42 | 6598 | |
f5adf94e | 6599 | if (HAS_IPS(dev)) |
a43f6e0f DV |
6600 | hsw_compute_ips_config(crtc, pipe_config); |
6601 | ||
877d48d5 | 6602 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 6603 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 6604 | |
cf5a15be | 6605 | return 0; |
79e53945 JB |
6606 | } |
6607 | ||
1652d19e VS |
6608 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
6609 | { | |
6610 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6611 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
6612 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6613 | uint32_t linkrate; | |
6614 | ||
414355a7 | 6615 | if (!(lcpll1 & LCPLL_PLL_ENABLE)) |
1652d19e | 6616 | return 24000; /* 24MHz is the cd freq with NSSC ref */ |
1652d19e VS |
6617 | |
6618 | if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) | |
6619 | return 540000; | |
6620 | ||
6621 | linkrate = (I915_READ(DPLL_CTRL1) & | |
71cd8423 | 6622 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; |
1652d19e | 6623 | |
71cd8423 DL |
6624 | if (linkrate == DPLL_CTRL1_LINK_RATE_2160 || |
6625 | linkrate == DPLL_CTRL1_LINK_RATE_1080) { | |
1652d19e VS |
6626 | /* vco 8640 */ |
6627 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6628 | case CDCLK_FREQ_450_432: | |
6629 | return 432000; | |
6630 | case CDCLK_FREQ_337_308: | |
6631 | return 308570; | |
6632 | case CDCLK_FREQ_675_617: | |
6633 | return 617140; | |
6634 | default: | |
6635 | WARN(1, "Unknown cd freq selection\n"); | |
6636 | } | |
6637 | } else { | |
6638 | /* vco 8100 */ | |
6639 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6640 | case CDCLK_FREQ_450_432: | |
6641 | return 450000; | |
6642 | case CDCLK_FREQ_337_308: | |
6643 | return 337500; | |
6644 | case CDCLK_FREQ_675_617: | |
6645 | return 675000; | |
6646 | default: | |
6647 | WARN(1, "Unknown cd freq selection\n"); | |
6648 | } | |
6649 | } | |
6650 | ||
6651 | /* error case, do as if DPLL0 isn't enabled */ | |
6652 | return 24000; | |
6653 | } | |
6654 | ||
acd3f3d3 BP |
6655 | static int broxton_get_display_clock_speed(struct drm_device *dev) |
6656 | { | |
6657 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6658 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6659 | uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; | |
6660 | uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE); | |
6661 | int cdclk; | |
6662 | ||
6663 | if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE)) | |
6664 | return 19200; | |
6665 | ||
6666 | cdclk = 19200 * pll_ratio / 2; | |
6667 | ||
6668 | switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) { | |
6669 | case BXT_CDCLK_CD2X_DIV_SEL_1: | |
6670 | return cdclk; /* 576MHz or 624MHz */ | |
6671 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: | |
6672 | return cdclk * 2 / 3; /* 384MHz */ | |
6673 | case BXT_CDCLK_CD2X_DIV_SEL_2: | |
6674 | return cdclk / 2; /* 288MHz */ | |
6675 | case BXT_CDCLK_CD2X_DIV_SEL_4: | |
6676 | return cdclk / 4; /* 144MHz */ | |
6677 | } | |
6678 | ||
6679 | /* error case, do as if DE PLL isn't enabled */ | |
6680 | return 19200; | |
6681 | } | |
6682 | ||
1652d19e VS |
6683 | static int broadwell_get_display_clock_speed(struct drm_device *dev) |
6684 | { | |
6685 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6686 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6687 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6688 | ||
6689 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6690 | return 800000; | |
6691 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6692 | return 450000; | |
6693 | else if (freq == LCPLL_CLK_FREQ_450) | |
6694 | return 450000; | |
6695 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
6696 | return 540000; | |
6697 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
6698 | return 337500; | |
6699 | else | |
6700 | return 675000; | |
6701 | } | |
6702 | ||
6703 | static int haswell_get_display_clock_speed(struct drm_device *dev) | |
6704 | { | |
6705 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6706 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6707 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6708 | ||
6709 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6710 | return 800000; | |
6711 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6712 | return 450000; | |
6713 | else if (freq == LCPLL_CLK_FREQ_450) | |
6714 | return 450000; | |
6715 | else if (IS_HSW_ULT(dev)) | |
6716 | return 337500; | |
6717 | else | |
6718 | return 540000; | |
79e53945 JB |
6719 | } |
6720 | ||
25eb05fc JB |
6721 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
6722 | { | |
d197b7d3 | 6723 | struct drm_i915_private *dev_priv = dev->dev_private; |
d197b7d3 VS |
6724 | u32 val; |
6725 | int divider; | |
6726 | ||
6bcda4f0 VS |
6727 | if (dev_priv->hpll_freq == 0) |
6728 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
6729 | ||
a580516d | 6730 | mutex_lock(&dev_priv->sb_lock); |
d197b7d3 | 6731 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); |
a580516d | 6732 | mutex_unlock(&dev_priv->sb_lock); |
d197b7d3 VS |
6733 | |
6734 | divider = val & DISPLAY_FREQUENCY_VALUES; | |
6735 | ||
7d007f40 VS |
6736 | WARN((val & DISPLAY_FREQUENCY_STATUS) != |
6737 | (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
6738 | "cdclk change in progress\n"); | |
6739 | ||
6bcda4f0 | 6740 | return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); |
25eb05fc JB |
6741 | } |
6742 | ||
b37a6434 VS |
6743 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
6744 | { | |
6745 | return 450000; | |
6746 | } | |
6747 | ||
e70236a8 JB |
6748 | static int i945_get_display_clock_speed(struct drm_device *dev) |
6749 | { | |
6750 | return 400000; | |
6751 | } | |
79e53945 | 6752 | |
e70236a8 | 6753 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 6754 | { |
e907f170 | 6755 | return 333333; |
e70236a8 | 6756 | } |
79e53945 | 6757 | |
e70236a8 JB |
6758 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
6759 | { | |
6760 | return 200000; | |
6761 | } | |
79e53945 | 6762 | |
257a7ffc DV |
6763 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
6764 | { | |
6765 | u16 gcfgc = 0; | |
6766 | ||
6767 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
6768 | ||
6769 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6770 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 6771 | return 266667; |
257a7ffc | 6772 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 6773 | return 333333; |
257a7ffc | 6774 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 6775 | return 444444; |
257a7ffc DV |
6776 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
6777 | return 200000; | |
6778 | default: | |
6779 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
6780 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 6781 | return 133333; |
257a7ffc | 6782 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 6783 | return 166667; |
257a7ffc DV |
6784 | } |
6785 | } | |
6786 | ||
e70236a8 JB |
6787 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
6788 | { | |
6789 | u16 gcfgc = 0; | |
79e53945 | 6790 | |
e70236a8 JB |
6791 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
6792 | ||
6793 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 6794 | return 133333; |
e70236a8 JB |
6795 | else { |
6796 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6797 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 6798 | return 333333; |
e70236a8 JB |
6799 | default: |
6800 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
6801 | return 190000; | |
79e53945 | 6802 | } |
e70236a8 JB |
6803 | } |
6804 | } | |
6805 | ||
6806 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
6807 | { | |
e907f170 | 6808 | return 266667; |
e70236a8 JB |
6809 | } |
6810 | ||
1b1d2716 | 6811 | static int i85x_get_display_clock_speed(struct drm_device *dev) |
e70236a8 JB |
6812 | { |
6813 | u16 hpllcc = 0; | |
1b1d2716 | 6814 | |
65cd2b3f VS |
6815 | /* |
6816 | * 852GM/852GMV only supports 133 MHz and the HPLLCC | |
6817 | * encoding is different :( | |
6818 | * FIXME is this the right way to detect 852GM/852GMV? | |
6819 | */ | |
6820 | if (dev->pdev->revision == 0x1) | |
6821 | return 133333; | |
6822 | ||
1b1d2716 VS |
6823 | pci_bus_read_config_word(dev->pdev->bus, |
6824 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); | |
6825 | ||
e70236a8 JB |
6826 | /* Assume that the hardware is in the high speed state. This |
6827 | * should be the default. | |
6828 | */ | |
6829 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
6830 | case GC_CLOCK_133_200: | |
1b1d2716 | 6831 | case GC_CLOCK_133_200_2: |
e70236a8 JB |
6832 | case GC_CLOCK_100_200: |
6833 | return 200000; | |
6834 | case GC_CLOCK_166_250: | |
6835 | return 250000; | |
6836 | case GC_CLOCK_100_133: | |
e907f170 | 6837 | return 133333; |
1b1d2716 VS |
6838 | case GC_CLOCK_133_266: |
6839 | case GC_CLOCK_133_266_2: | |
6840 | case GC_CLOCK_166_266: | |
6841 | return 266667; | |
e70236a8 | 6842 | } |
79e53945 | 6843 | |
e70236a8 JB |
6844 | /* Shouldn't happen */ |
6845 | return 0; | |
6846 | } | |
79e53945 | 6847 | |
e70236a8 JB |
6848 | static int i830_get_display_clock_speed(struct drm_device *dev) |
6849 | { | |
e907f170 | 6850 | return 133333; |
79e53945 JB |
6851 | } |
6852 | ||
34edce2f VS |
6853 | static unsigned int intel_hpll_vco(struct drm_device *dev) |
6854 | { | |
6855 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6856 | static const unsigned int blb_vco[8] = { | |
6857 | [0] = 3200000, | |
6858 | [1] = 4000000, | |
6859 | [2] = 5333333, | |
6860 | [3] = 4800000, | |
6861 | [4] = 6400000, | |
6862 | }; | |
6863 | static const unsigned int pnv_vco[8] = { | |
6864 | [0] = 3200000, | |
6865 | [1] = 4000000, | |
6866 | [2] = 5333333, | |
6867 | [3] = 4800000, | |
6868 | [4] = 2666667, | |
6869 | }; | |
6870 | static const unsigned int cl_vco[8] = { | |
6871 | [0] = 3200000, | |
6872 | [1] = 4000000, | |
6873 | [2] = 5333333, | |
6874 | [3] = 6400000, | |
6875 | [4] = 3333333, | |
6876 | [5] = 3566667, | |
6877 | [6] = 4266667, | |
6878 | }; | |
6879 | static const unsigned int elk_vco[8] = { | |
6880 | [0] = 3200000, | |
6881 | [1] = 4000000, | |
6882 | [2] = 5333333, | |
6883 | [3] = 4800000, | |
6884 | }; | |
6885 | static const unsigned int ctg_vco[8] = { | |
6886 | [0] = 3200000, | |
6887 | [1] = 4000000, | |
6888 | [2] = 5333333, | |
6889 | [3] = 6400000, | |
6890 | [4] = 2666667, | |
6891 | [5] = 4266667, | |
6892 | }; | |
6893 | const unsigned int *vco_table; | |
6894 | unsigned int vco; | |
6895 | uint8_t tmp = 0; | |
6896 | ||
6897 | /* FIXME other chipsets? */ | |
6898 | if (IS_GM45(dev)) | |
6899 | vco_table = ctg_vco; | |
6900 | else if (IS_G4X(dev)) | |
6901 | vco_table = elk_vco; | |
6902 | else if (IS_CRESTLINE(dev)) | |
6903 | vco_table = cl_vco; | |
6904 | else if (IS_PINEVIEW(dev)) | |
6905 | vco_table = pnv_vco; | |
6906 | else if (IS_G33(dev)) | |
6907 | vco_table = blb_vco; | |
6908 | else | |
6909 | return 0; | |
6910 | ||
6911 | tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO); | |
6912 | ||
6913 | vco = vco_table[tmp & 0x7]; | |
6914 | if (vco == 0) | |
6915 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); | |
6916 | else | |
6917 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); | |
6918 | ||
6919 | return vco; | |
6920 | } | |
6921 | ||
6922 | static int gm45_get_display_clock_speed(struct drm_device *dev) | |
6923 | { | |
6924 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
6925 | uint16_t tmp = 0; | |
6926 | ||
6927 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
6928 | ||
6929 | cdclk_sel = (tmp >> 12) & 0x1; | |
6930 | ||
6931 | switch (vco) { | |
6932 | case 2666667: | |
6933 | case 4000000: | |
6934 | case 5333333: | |
6935 | return cdclk_sel ? 333333 : 222222; | |
6936 | case 3200000: | |
6937 | return cdclk_sel ? 320000 : 228571; | |
6938 | default: | |
6939 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); | |
6940 | return 222222; | |
6941 | } | |
6942 | } | |
6943 | ||
6944 | static int i965gm_get_display_clock_speed(struct drm_device *dev) | |
6945 | { | |
6946 | static const uint8_t div_3200[] = { 16, 10, 8 }; | |
6947 | static const uint8_t div_4000[] = { 20, 12, 10 }; | |
6948 | static const uint8_t div_5333[] = { 24, 16, 14 }; | |
6949 | const uint8_t *div_table; | |
6950 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
6951 | uint16_t tmp = 0; | |
6952 | ||
6953 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
6954 | ||
6955 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; | |
6956 | ||
6957 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
6958 | goto fail; | |
6959 | ||
6960 | switch (vco) { | |
6961 | case 3200000: | |
6962 | div_table = div_3200; | |
6963 | break; | |
6964 | case 4000000: | |
6965 | div_table = div_4000; | |
6966 | break; | |
6967 | case 5333333: | |
6968 | div_table = div_5333; | |
6969 | break; | |
6970 | default: | |
6971 | goto fail; | |
6972 | } | |
6973 | ||
6974 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
6975 | ||
caf4e252 | 6976 | fail: |
34edce2f VS |
6977 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); |
6978 | return 200000; | |
6979 | } | |
6980 | ||
6981 | static int g33_get_display_clock_speed(struct drm_device *dev) | |
6982 | { | |
6983 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; | |
6984 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; | |
6985 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; | |
6986 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; | |
6987 | const uint8_t *div_table; | |
6988 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
6989 | uint16_t tmp = 0; | |
6990 | ||
6991 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
6992 | ||
6993 | cdclk_sel = (tmp >> 4) & 0x7; | |
6994 | ||
6995 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
6996 | goto fail; | |
6997 | ||
6998 | switch (vco) { | |
6999 | case 3200000: | |
7000 | div_table = div_3200; | |
7001 | break; | |
7002 | case 4000000: | |
7003 | div_table = div_4000; | |
7004 | break; | |
7005 | case 4800000: | |
7006 | div_table = div_4800; | |
7007 | break; | |
7008 | case 5333333: | |
7009 | div_table = div_5333; | |
7010 | break; | |
7011 | default: | |
7012 | goto fail; | |
7013 | } | |
7014 | ||
7015 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7016 | ||
caf4e252 | 7017 | fail: |
34edce2f VS |
7018 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); |
7019 | return 190476; | |
7020 | } | |
7021 | ||
2c07245f | 7022 | static void |
a65851af | 7023 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 7024 | { |
a65851af VS |
7025 | while (*num > DATA_LINK_M_N_MASK || |
7026 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
7027 | *num >>= 1; |
7028 | *den >>= 1; | |
7029 | } | |
7030 | } | |
7031 | ||
a65851af VS |
7032 | static void compute_m_n(unsigned int m, unsigned int n, |
7033 | uint32_t *ret_m, uint32_t *ret_n) | |
7034 | { | |
7035 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
7036 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
7037 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
7038 | } | |
7039 | ||
e69d0bc1 DV |
7040 | void |
7041 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
7042 | int pixel_clock, int link_clock, | |
7043 | struct intel_link_m_n *m_n) | |
2c07245f | 7044 | { |
e69d0bc1 | 7045 | m_n->tu = 64; |
a65851af VS |
7046 | |
7047 | compute_m_n(bits_per_pixel * pixel_clock, | |
7048 | link_clock * nlanes * 8, | |
7049 | &m_n->gmch_m, &m_n->gmch_n); | |
7050 | ||
7051 | compute_m_n(pixel_clock, link_clock, | |
7052 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
7053 | } |
7054 | ||
a7615030 CW |
7055 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
7056 | { | |
d330a953 JN |
7057 | if (i915.panel_use_ssc >= 0) |
7058 | return i915.panel_use_ssc != 0; | |
41aa3448 | 7059 | return dev_priv->vbt.lvds_use_ssc |
435793df | 7060 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
7061 | } |
7062 | ||
a93e255f ACO |
7063 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
7064 | int num_connectors) | |
c65d77d8 | 7065 | { |
a93e255f | 7066 | struct drm_device *dev = crtc_state->base.crtc->dev; |
c65d77d8 JB |
7067 | struct drm_i915_private *dev_priv = dev->dev_private; |
7068 | int refclk; | |
7069 | ||
a93e255f ACO |
7070 | WARN_ON(!crtc_state->base.state); |
7071 | ||
5ab7b0b7 | 7072 | if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) { |
9a0ea498 | 7073 | refclk = 100000; |
a93e255f | 7074 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 7075 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
7076 | refclk = dev_priv->vbt.lvds_ssc_freq; |
7077 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
7078 | } else if (!IS_GEN2(dev)) { |
7079 | refclk = 96000; | |
7080 | } else { | |
7081 | refclk = 48000; | |
7082 | } | |
7083 | ||
7084 | return refclk; | |
7085 | } | |
7086 | ||
7429e9d4 | 7087 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 7088 | { |
7df00d7a | 7089 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 7090 | } |
f47709a9 | 7091 | |
7429e9d4 DV |
7092 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
7093 | { | |
7094 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
7095 | } |
7096 | ||
f47709a9 | 7097 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 7098 | struct intel_crtc_state *crtc_state, |
a7516a05 JB |
7099 | intel_clock_t *reduced_clock) |
7100 | { | |
f47709a9 | 7101 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
7102 | u32 fp, fp2 = 0; |
7103 | ||
7104 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 7105 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7106 | if (reduced_clock) |
7429e9d4 | 7107 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 7108 | } else { |
190f68c5 | 7109 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7110 | if (reduced_clock) |
7429e9d4 | 7111 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
7112 | } |
7113 | ||
190f68c5 | 7114 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 7115 | |
f47709a9 | 7116 | crtc->lowfreq_avail = false; |
a93e255f | 7117 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 7118 | reduced_clock) { |
190f68c5 | 7119 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 7120 | crtc->lowfreq_avail = true; |
a7516a05 | 7121 | } else { |
190f68c5 | 7122 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
7123 | } |
7124 | } | |
7125 | ||
5e69f97f CML |
7126 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
7127 | pipe) | |
89b667f8 JB |
7128 | { |
7129 | u32 reg_val; | |
7130 | ||
7131 | /* | |
7132 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
7133 | * and set it to a reasonable value instead. | |
7134 | */ | |
ab3c759a | 7135 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
7136 | reg_val &= 0xffffff00; |
7137 | reg_val |= 0x00000030; | |
ab3c759a | 7138 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7139 | |
ab3c759a | 7140 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7141 | reg_val &= 0x8cffffff; |
7142 | reg_val = 0x8c000000; | |
ab3c759a | 7143 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 7144 | |
ab3c759a | 7145 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 7146 | reg_val &= 0xffffff00; |
ab3c759a | 7147 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7148 | |
ab3c759a | 7149 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7150 | reg_val &= 0x00ffffff; |
7151 | reg_val |= 0xb0000000; | |
ab3c759a | 7152 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
7153 | } |
7154 | ||
b551842d DV |
7155 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
7156 | struct intel_link_m_n *m_n) | |
7157 | { | |
7158 | struct drm_device *dev = crtc->base.dev; | |
7159 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7160 | int pipe = crtc->pipe; | |
7161 | ||
e3b95f1e DV |
7162 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7163 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
7164 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
7165 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
7166 | } |
7167 | ||
7168 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
7169 | struct intel_link_m_n *m_n, |
7170 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
7171 | { |
7172 | struct drm_device *dev = crtc->base.dev; | |
7173 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7174 | int pipe = crtc->pipe; | |
6e3c9717 | 7175 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
7176 | |
7177 | if (INTEL_INFO(dev)->gen >= 5) { | |
7178 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
7179 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
7180 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
7181 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
7182 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
7183 | * for gen < 8) and if DRRS is supported (to make sure the | |
7184 | * registers are not unnecessarily accessed). | |
7185 | */ | |
44395bfe | 7186 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 7187 | crtc->config->has_drrs) { |
f769cd24 VK |
7188 | I915_WRITE(PIPE_DATA_M2(transcoder), |
7189 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
7190 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
7191 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
7192 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
7193 | } | |
b551842d | 7194 | } else { |
e3b95f1e DV |
7195 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7196 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
7197 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
7198 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
7199 | } |
7200 | } | |
7201 | ||
fe3cd48d | 7202 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 7203 | { |
fe3cd48d R |
7204 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
7205 | ||
7206 | if (m_n == M1_N1) { | |
7207 | dp_m_n = &crtc->config->dp_m_n; | |
7208 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
7209 | } else if (m_n == M2_N2) { | |
7210 | ||
7211 | /* | |
7212 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
7213 | * needs to be programmed into M1_N1. | |
7214 | */ | |
7215 | dp_m_n = &crtc->config->dp_m2_n2; | |
7216 | } else { | |
7217 | DRM_ERROR("Unsupported divider value\n"); | |
7218 | return; | |
7219 | } | |
7220 | ||
6e3c9717 ACO |
7221 | if (crtc->config->has_pch_encoder) |
7222 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 7223 | else |
fe3cd48d | 7224 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
7225 | } |
7226 | ||
251ac862 DV |
7227 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
7228 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 DV |
7229 | { |
7230 | u32 dpll, dpll_md; | |
7231 | ||
7232 | /* | |
7233 | * Enable DPIO clock input. We should never disable the reference | |
7234 | * clock for pipe B, since VGA hotplug / manual detection depends | |
7235 | * on it. | |
7236 | */ | |
60bfe44f VS |
7237 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV | |
7238 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV; | |
bdd4b6a6 DV |
7239 | /* We should never disable this, set it here for state tracking */ |
7240 | if (crtc->pipe == PIPE_B) | |
7241 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
7242 | dpll |= DPLL_VCO_ENABLE; | |
d288f65f | 7243 | pipe_config->dpll_hw_state.dpll = dpll; |
bdd4b6a6 | 7244 | |
d288f65f | 7245 | dpll_md = (pipe_config->pixel_multiplier - 1) |
bdd4b6a6 | 7246 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
d288f65f | 7247 | pipe_config->dpll_hw_state.dpll_md = dpll_md; |
bdd4b6a6 DV |
7248 | } |
7249 | ||
d288f65f | 7250 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7251 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 7252 | { |
f47709a9 | 7253 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 7254 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 7255 | int pipe = crtc->pipe; |
bdd4b6a6 | 7256 | u32 mdiv; |
a0c4da24 | 7257 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 7258 | u32 coreclk, reg_val; |
a0c4da24 | 7259 | |
a580516d | 7260 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 7261 | |
d288f65f VS |
7262 | bestn = pipe_config->dpll.n; |
7263 | bestm1 = pipe_config->dpll.m1; | |
7264 | bestm2 = pipe_config->dpll.m2; | |
7265 | bestp1 = pipe_config->dpll.p1; | |
7266 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 7267 | |
89b667f8 JB |
7268 | /* See eDP HDMI DPIO driver vbios notes doc */ |
7269 | ||
7270 | /* PLL B needs special handling */ | |
bdd4b6a6 | 7271 | if (pipe == PIPE_B) |
5e69f97f | 7272 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
7273 | |
7274 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 7275 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
7276 | |
7277 | /* Disable target IRef on PLL */ | |
ab3c759a | 7278 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 7279 | reg_val &= 0x00ffffff; |
ab3c759a | 7280 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
7281 | |
7282 | /* Disable fast lock */ | |
ab3c759a | 7283 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
7284 | |
7285 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
7286 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
7287 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
7288 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 7289 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
7290 | |
7291 | /* | |
7292 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
7293 | * but we don't support that). | |
7294 | * Note: don't use the DAC post divider as it seems unstable. | |
7295 | */ | |
7296 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 7297 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7298 | |
a0c4da24 | 7299 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 7300 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7301 | |
89b667f8 | 7302 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 7303 | if (pipe_config->port_clock == 162000 || |
409ee761 ACO |
7304 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || |
7305 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 7306 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 7307 | 0x009f0003); |
89b667f8 | 7308 | else |
ab3c759a | 7309 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
7310 | 0x00d0000f); |
7311 | ||
681a8504 | 7312 | if (pipe_config->has_dp_encoder) { |
89b667f8 | 7313 | /* Use SSC source */ |
bdd4b6a6 | 7314 | if (pipe == PIPE_A) |
ab3c759a | 7315 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7316 | 0x0df40000); |
7317 | else | |
ab3c759a | 7318 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7319 | 0x0df70000); |
7320 | } else { /* HDMI or VGA */ | |
7321 | /* Use bend source */ | |
bdd4b6a6 | 7322 | if (pipe == PIPE_A) |
ab3c759a | 7323 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7324 | 0x0df70000); |
7325 | else | |
ab3c759a | 7326 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7327 | 0x0df40000); |
7328 | } | |
a0c4da24 | 7329 | |
ab3c759a | 7330 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 7331 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
409ee761 ACO |
7332 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
7333 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) | |
89b667f8 | 7334 | coreclk |= 0x01000000; |
ab3c759a | 7335 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 7336 | |
ab3c759a | 7337 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 7338 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
7339 | } |
7340 | ||
251ac862 DV |
7341 | static void chv_compute_dpll(struct intel_crtc *crtc, |
7342 | struct intel_crtc_state *pipe_config) | |
1ae0d137 | 7343 | { |
60bfe44f VS |
7344 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | |
7345 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | | |
1ae0d137 VS |
7346 | DPLL_VCO_ENABLE; |
7347 | if (crtc->pipe != PIPE_A) | |
d288f65f | 7348 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
1ae0d137 | 7349 | |
d288f65f VS |
7350 | pipe_config->dpll_hw_state.dpll_md = |
7351 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
1ae0d137 VS |
7352 | } |
7353 | ||
d288f65f | 7354 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7355 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
7356 | { |
7357 | struct drm_device *dev = crtc->base.dev; | |
7358 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7359 | int pipe = crtc->pipe; | |
7360 | int dpll_reg = DPLL(crtc->pipe); | |
7361 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9cbe40c1 | 7362 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 7363 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 7364 | u32 dpio_val; |
9cbe40c1 | 7365 | int vco; |
9d556c99 | 7366 | |
d288f65f VS |
7367 | bestn = pipe_config->dpll.n; |
7368 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
7369 | bestm1 = pipe_config->dpll.m1; | |
7370 | bestm2 = pipe_config->dpll.m2 >> 22; | |
7371 | bestp1 = pipe_config->dpll.p1; | |
7372 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 7373 | vco = pipe_config->dpll.vco; |
a945ce7e | 7374 | dpio_val = 0; |
9cbe40c1 | 7375 | loopfilter = 0; |
9d556c99 CML |
7376 | |
7377 | /* | |
7378 | * Enable Refclk and SSC | |
7379 | */ | |
a11b0703 | 7380 | I915_WRITE(dpll_reg, |
d288f65f | 7381 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
a11b0703 | 7382 | |
a580516d | 7383 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 7384 | |
9d556c99 CML |
7385 | /* p1 and p2 divider */ |
7386 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
7387 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
7388 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
7389 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
7390 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
7391 | ||
7392 | /* Feedback post-divider - m2 */ | |
7393 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
7394 | ||
7395 | /* Feedback refclk divider - n and m1 */ | |
7396 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
7397 | DPIO_CHV_M1_DIV_BY_2 | | |
7398 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
7399 | ||
7400 | /* M2 fraction division */ | |
25a25dfc | 7401 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
7402 | |
7403 | /* M2 fraction division enable */ | |
a945ce7e VP |
7404 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
7405 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
7406 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
7407 | if (bestm2_frac) | |
7408 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
7409 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 7410 | |
de3a0fde VP |
7411 | /* Program digital lock detect threshold */ |
7412 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
7413 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
7414 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
7415 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
7416 | if (!bestm2_frac) | |
7417 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
7418 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
7419 | ||
9d556c99 | 7420 | /* Loop filter */ |
9cbe40c1 VP |
7421 | if (vco == 5400000) { |
7422 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7423 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
7424 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7425 | tribuf_calcntr = 0x9; | |
7426 | } else if (vco <= 6200000) { | |
7427 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7428 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
7429 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7430 | tribuf_calcntr = 0x9; | |
7431 | } else if (vco <= 6480000) { | |
7432 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7433 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7434 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7435 | tribuf_calcntr = 0x8; | |
7436 | } else { | |
7437 | /* Not supported. Apply the same limits as in the max case */ | |
7438 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7439 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7440 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7441 | tribuf_calcntr = 0; | |
7442 | } | |
9d556c99 CML |
7443 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
7444 | ||
968040b2 | 7445 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
7446 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
7447 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
7448 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
7449 | ||
9d556c99 CML |
7450 | /* AFC Recal */ |
7451 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
7452 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
7453 | DPIO_AFC_RECAL); | |
7454 | ||
a580516d | 7455 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
7456 | } |
7457 | ||
d288f65f VS |
7458 | /** |
7459 | * vlv_force_pll_on - forcibly enable just the PLL | |
7460 | * @dev_priv: i915 private structure | |
7461 | * @pipe: pipe PLL to enable | |
7462 | * @dpll: PLL configuration | |
7463 | * | |
7464 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
7465 | * in cases where we need the PLL enabled even when @pipe is not going to | |
7466 | * be enabled. | |
7467 | */ | |
7468 | void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, | |
7469 | const struct dpll *dpll) | |
7470 | { | |
7471 | struct intel_crtc *crtc = | |
7472 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
5cec258b | 7473 | struct intel_crtc_state pipe_config = { |
a93e255f | 7474 | .base.crtc = &crtc->base, |
d288f65f VS |
7475 | .pixel_multiplier = 1, |
7476 | .dpll = *dpll, | |
7477 | }; | |
7478 | ||
7479 | if (IS_CHERRYVIEW(dev)) { | |
251ac862 | 7480 | chv_compute_dpll(crtc, &pipe_config); |
d288f65f VS |
7481 | chv_prepare_pll(crtc, &pipe_config); |
7482 | chv_enable_pll(crtc, &pipe_config); | |
7483 | } else { | |
251ac862 | 7484 | vlv_compute_dpll(crtc, &pipe_config); |
d288f65f VS |
7485 | vlv_prepare_pll(crtc, &pipe_config); |
7486 | vlv_enable_pll(crtc, &pipe_config); | |
7487 | } | |
7488 | } | |
7489 | ||
7490 | /** | |
7491 | * vlv_force_pll_off - forcibly disable just the PLL | |
7492 | * @dev_priv: i915 private structure | |
7493 | * @pipe: pipe PLL to disable | |
7494 | * | |
7495 | * Disable the PLL for @pipe. To be used in cases where we need | |
7496 | * the PLL enabled even when @pipe is not going to be enabled. | |
7497 | */ | |
7498 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
7499 | { | |
7500 | if (IS_CHERRYVIEW(dev)) | |
7501 | chv_disable_pll(to_i915(dev), pipe); | |
7502 | else | |
7503 | vlv_disable_pll(to_i915(dev), pipe); | |
7504 | } | |
7505 | ||
251ac862 DV |
7506 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
7507 | struct intel_crtc_state *crtc_state, | |
7508 | intel_clock_t *reduced_clock, | |
7509 | int num_connectors) | |
eb1cbe48 | 7510 | { |
f47709a9 | 7511 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7512 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
7513 | u32 dpll; |
7514 | bool is_sdvo; | |
190f68c5 | 7515 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7516 | |
190f68c5 | 7517 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7518 | |
a93e255f ACO |
7519 | is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) || |
7520 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
7521 | |
7522 | dpll = DPLL_VGA_MODE_DIS; | |
7523 | ||
a93e255f | 7524 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
7525 | dpll |= DPLLB_MODE_LVDS; |
7526 | else | |
7527 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 7528 | |
ef1b460d | 7529 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 7530 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 7531 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 7532 | } |
198a037f DV |
7533 | |
7534 | if (is_sdvo) | |
4a33e48d | 7535 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 7536 | |
190f68c5 | 7537 | if (crtc_state->has_dp_encoder) |
4a33e48d | 7538 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
7539 | |
7540 | /* compute bitmask from p1 value */ | |
7541 | if (IS_PINEVIEW(dev)) | |
7542 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
7543 | else { | |
7544 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7545 | if (IS_G4X(dev) && reduced_clock) | |
7546 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
7547 | } | |
7548 | switch (clock->p2) { | |
7549 | case 5: | |
7550 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7551 | break; | |
7552 | case 7: | |
7553 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7554 | break; | |
7555 | case 10: | |
7556 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7557 | break; | |
7558 | case 14: | |
7559 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7560 | break; | |
7561 | } | |
7562 | if (INTEL_INFO(dev)->gen >= 4) | |
7563 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
7564 | ||
190f68c5 | 7565 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 7566 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
a93e255f | 7567 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7568 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7569 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7570 | else | |
7571 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7572 | ||
7573 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7574 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 7575 | |
eb1cbe48 | 7576 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 7577 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7578 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 7579 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
7580 | } |
7581 | } | |
7582 | ||
251ac862 DV |
7583 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
7584 | struct intel_crtc_state *crtc_state, | |
7585 | intel_clock_t *reduced_clock, | |
7586 | int num_connectors) | |
eb1cbe48 | 7587 | { |
f47709a9 | 7588 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7589 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 7590 | u32 dpll; |
190f68c5 | 7591 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7592 | |
190f68c5 | 7593 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7594 | |
eb1cbe48 DV |
7595 | dpll = DPLL_VGA_MODE_DIS; |
7596 | ||
a93e255f | 7597 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
7598 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
7599 | } else { | |
7600 | if (clock->p1 == 2) | |
7601 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
7602 | else | |
7603 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7604 | if (clock->p2 == 4) | |
7605 | dpll |= PLL_P2_DIVIDE_BY_4; | |
7606 | } | |
7607 | ||
a93e255f | 7608 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
7609 | dpll |= DPLL_DVO_2X_MODE; |
7610 | ||
a93e255f | 7611 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7612 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7613 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7614 | else | |
7615 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7616 | ||
7617 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7618 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
7619 | } |
7620 | ||
8a654f3b | 7621 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
7622 | { |
7623 | struct drm_device *dev = intel_crtc->base.dev; | |
7624 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7625 | enum pipe pipe = intel_crtc->pipe; | |
6e3c9717 | 7626 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
124abe07 | 7627 | struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
7628 | uint32_t crtc_vtotal, crtc_vblank_end; |
7629 | int vsyncshift = 0; | |
4d8a62ea DV |
7630 | |
7631 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
7632 | * the hw state checker will get angry at the mismatch. */ | |
7633 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
7634 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 7635 | |
609aeaca | 7636 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 7637 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
7638 | crtc_vtotal -= 1; |
7639 | crtc_vblank_end -= 1; | |
609aeaca | 7640 | |
409ee761 | 7641 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
7642 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
7643 | else | |
7644 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
7645 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
7646 | if (vsyncshift < 0) |
7647 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
7648 | } |
7649 | ||
7650 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 7651 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 7652 | |
fe2b8f9d | 7653 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
7654 | (adjusted_mode->crtc_hdisplay - 1) | |
7655 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 7656 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
7657 | (adjusted_mode->crtc_hblank_start - 1) | |
7658 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 7659 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
7660 | (adjusted_mode->crtc_hsync_start - 1) | |
7661 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
7662 | ||
fe2b8f9d | 7663 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 7664 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 7665 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 7666 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 7667 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 7668 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 7669 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
7670 | (adjusted_mode->crtc_vsync_start - 1) | |
7671 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
7672 | ||
b5e508d4 PZ |
7673 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
7674 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
7675 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
7676 | * bits. */ | |
7677 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
7678 | (pipe == PIPE_B || pipe == PIPE_C)) | |
7679 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
7680 | ||
b0e77b9c PZ |
7681 | /* pipesrc controls the size that is scaled from, which should |
7682 | * always be the user's requested size. | |
7683 | */ | |
7684 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
7685 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
7686 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
7687 | } |
7688 | ||
1bd1bd80 | 7689 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 7690 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
7691 | { |
7692 | struct drm_device *dev = crtc->base.dev; | |
7693 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7694 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
7695 | uint32_t tmp; | |
7696 | ||
7697 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7698 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
7699 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7700 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
7701 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
7702 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7703 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
7704 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
7705 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7706 | |
7707 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7708 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
7709 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7710 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
7711 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
7712 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7713 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
7714 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
7715 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7716 | |
7717 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
7718 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
7719 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
7720 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 DV |
7721 | } |
7722 | ||
7723 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
7724 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
7725 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
7726 | ||
2d112de7 ACO |
7727 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
7728 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
7729 | } |
7730 | ||
f6a83288 | 7731 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 7732 | struct intel_crtc_state *pipe_config) |
babea61d | 7733 | { |
2d112de7 ACO |
7734 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
7735 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
7736 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
7737 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 7738 | |
2d112de7 ACO |
7739 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
7740 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
7741 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7742 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 7743 | |
2d112de7 | 7744 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 7745 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 7746 | |
2d112de7 ACO |
7747 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
7748 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
cd13f5ab ML |
7749 | |
7750 | mode->hsync = drm_mode_hsync(mode); | |
7751 | mode->vrefresh = drm_mode_vrefresh(mode); | |
7752 | drm_mode_set_name(mode); | |
babea61d JB |
7753 | } |
7754 | ||
84b046f3 DV |
7755 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7756 | { | |
7757 | struct drm_device *dev = intel_crtc->base.dev; | |
7758 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7759 | uint32_t pipeconf; | |
7760 | ||
9f11a9e4 | 7761 | pipeconf = 0; |
84b046f3 | 7762 | |
b6b5d049 VS |
7763 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
7764 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
7765 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 7766 | |
6e3c9717 | 7767 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7768 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7769 | |
ff9ce46e DV |
7770 | /* only g4x and later have fancy bpc/dither controls */ |
7771 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
ff9ce46e | 7772 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 7773 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 7774 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 7775 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 7776 | |
6e3c9717 | 7777 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
7778 | case 18: |
7779 | pipeconf |= PIPECONF_6BPC; | |
7780 | break; | |
7781 | case 24: | |
7782 | pipeconf |= PIPECONF_8BPC; | |
7783 | break; | |
7784 | case 30: | |
7785 | pipeconf |= PIPECONF_10BPC; | |
7786 | break; | |
7787 | default: | |
7788 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7789 | BUG(); | |
84b046f3 DV |
7790 | } |
7791 | } | |
7792 | ||
7793 | if (HAS_PIPE_CXSR(dev)) { | |
7794 | if (intel_crtc->lowfreq_avail) { | |
7795 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
7796 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
7797 | } else { | |
7798 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
7799 | } |
7800 | } | |
7801 | ||
6e3c9717 | 7802 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 7803 | if (INTEL_INFO(dev)->gen < 4 || |
409ee761 | 7804 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
7805 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
7806 | else | |
7807 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7808 | } else | |
84b046f3 DV |
7809 | pipeconf |= PIPECONF_PROGRESSIVE; |
7810 | ||
6e3c9717 | 7811 | if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range) |
9f11a9e4 | 7812 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 7813 | |
84b046f3 DV |
7814 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7815 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7816 | } | |
7817 | ||
190f68c5 ACO |
7818 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
7819 | struct intel_crtc_state *crtc_state) | |
79e53945 | 7820 | { |
c7653199 | 7821 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 7822 | struct drm_i915_private *dev_priv = dev->dev_private; |
c751ce4f | 7823 | int refclk, num_connectors = 0; |
c329a4ec DV |
7824 | intel_clock_t clock; |
7825 | bool ok; | |
7826 | bool is_dsi = false; | |
5eddb70b | 7827 | struct intel_encoder *encoder; |
d4906093 | 7828 | const intel_limit_t *limit; |
55bb9992 | 7829 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 7830 | struct drm_connector *connector; |
55bb9992 ACO |
7831 | struct drm_connector_state *connector_state; |
7832 | int i; | |
79e53945 | 7833 | |
dd3cd74a ACO |
7834 | memset(&crtc_state->dpll_hw_state, 0, |
7835 | sizeof(crtc_state->dpll_hw_state)); | |
7836 | ||
da3ced29 | 7837 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
7838 | if (connector_state->crtc != &crtc->base) |
7839 | continue; | |
7840 | ||
7841 | encoder = to_intel_encoder(connector_state->best_encoder); | |
7842 | ||
5eddb70b | 7843 | switch (encoder->type) { |
e9fd1c02 JN |
7844 | case INTEL_OUTPUT_DSI: |
7845 | is_dsi = true; | |
7846 | break; | |
6847d71b PZ |
7847 | default: |
7848 | break; | |
79e53945 | 7849 | } |
43565a06 | 7850 | |
c751ce4f | 7851 | num_connectors++; |
79e53945 JB |
7852 | } |
7853 | ||
f2335330 | 7854 | if (is_dsi) |
5b18e57c | 7855 | return 0; |
f2335330 | 7856 | |
190f68c5 | 7857 | if (!crtc_state->clock_set) { |
a93e255f | 7858 | refclk = i9xx_get_refclk(crtc_state, num_connectors); |
79e53945 | 7859 | |
e9fd1c02 JN |
7860 | /* |
7861 | * Returns a set of divisors for the desired target clock with | |
7862 | * the given refclk, or FALSE. The returned values represent | |
7863 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
7864 | * 2) / p1 / p2. | |
7865 | */ | |
a93e255f ACO |
7866 | limit = intel_limit(crtc_state, refclk); |
7867 | ok = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 7868 | crtc_state->port_clock, |
e9fd1c02 | 7869 | refclk, NULL, &clock); |
f2335330 | 7870 | if (!ok) { |
e9fd1c02 JN |
7871 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
7872 | return -EINVAL; | |
7873 | } | |
79e53945 | 7874 | |
f2335330 | 7875 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
7876 | crtc_state->dpll.n = clock.n; |
7877 | crtc_state->dpll.m1 = clock.m1; | |
7878 | crtc_state->dpll.m2 = clock.m2; | |
7879 | crtc_state->dpll.p1 = clock.p1; | |
7880 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 7881 | } |
7026d4ac | 7882 | |
e9fd1c02 | 7883 | if (IS_GEN2(dev)) { |
c329a4ec | 7884 | i8xx_compute_dpll(crtc, crtc_state, NULL, |
251ac862 | 7885 | num_connectors); |
9d556c99 | 7886 | } else if (IS_CHERRYVIEW(dev)) { |
251ac862 | 7887 | chv_compute_dpll(crtc, crtc_state); |
e9fd1c02 | 7888 | } else if (IS_VALLEYVIEW(dev)) { |
251ac862 | 7889 | vlv_compute_dpll(crtc, crtc_state); |
e9fd1c02 | 7890 | } else { |
c329a4ec | 7891 | i9xx_compute_dpll(crtc, crtc_state, NULL, |
251ac862 | 7892 | num_connectors); |
e9fd1c02 | 7893 | } |
79e53945 | 7894 | |
c8f7a0db | 7895 | return 0; |
f564048e EA |
7896 | } |
7897 | ||
2fa2fe9a | 7898 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 7899 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
7900 | { |
7901 | struct drm_device *dev = crtc->base.dev; | |
7902 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7903 | uint32_t tmp; | |
7904 | ||
dc9e7dec VS |
7905 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
7906 | return; | |
7907 | ||
2fa2fe9a | 7908 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
7909 | if (!(tmp & PFIT_ENABLE)) |
7910 | return; | |
2fa2fe9a | 7911 | |
06922821 | 7912 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
7913 | if (INTEL_INFO(dev)->gen < 4) { |
7914 | if (crtc->pipe != PIPE_B) | |
7915 | return; | |
2fa2fe9a DV |
7916 | } else { |
7917 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
7918 | return; | |
7919 | } | |
7920 | ||
06922821 | 7921 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
7922 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
7923 | if (INTEL_INFO(dev)->gen < 5) | |
7924 | pipe_config->gmch_pfit.lvds_border_bits = | |
7925 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
7926 | } | |
7927 | ||
acbec814 | 7928 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7929 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
7930 | { |
7931 | struct drm_device *dev = crtc->base.dev; | |
7932 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7933 | int pipe = pipe_config->cpu_transcoder; | |
7934 | intel_clock_t clock; | |
7935 | u32 mdiv; | |
662c6ecb | 7936 | int refclk = 100000; |
acbec814 | 7937 | |
f573de5a SK |
7938 | /* In case of MIPI DPLL will not even be used */ |
7939 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) | |
7940 | return; | |
7941 | ||
a580516d | 7942 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 7943 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 7944 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
7945 | |
7946 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
7947 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
7948 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
7949 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
7950 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
7951 | ||
dccbea3b | 7952 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
7953 | } |
7954 | ||
5724dbd1 DL |
7955 | static void |
7956 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
7957 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
7958 | { |
7959 | struct drm_device *dev = crtc->base.dev; | |
7960 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7961 | u32 val, base, offset; | |
7962 | int pipe = crtc->pipe, plane = crtc->plane; | |
7963 | int fourcc, pixel_format; | |
6761dd31 | 7964 | unsigned int aligned_height; |
b113d5ee | 7965 | struct drm_framebuffer *fb; |
1b842c89 | 7966 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 7967 | |
42a7b088 DL |
7968 | val = I915_READ(DSPCNTR(plane)); |
7969 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
7970 | return; | |
7971 | ||
d9806c9f | 7972 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 7973 | if (!intel_fb) { |
1ad292b5 JB |
7974 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7975 | return; | |
7976 | } | |
7977 | ||
1b842c89 DL |
7978 | fb = &intel_fb->base; |
7979 | ||
18c5247e DV |
7980 | if (INTEL_INFO(dev)->gen >= 4) { |
7981 | if (val & DISPPLANE_TILED) { | |
49af449b | 7982 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
7983 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
7984 | } | |
7985 | } | |
1ad292b5 JB |
7986 | |
7987 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 7988 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
7989 | fb->pixel_format = fourcc; |
7990 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
7991 | |
7992 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 7993 | if (plane_config->tiling) |
1ad292b5 JB |
7994 | offset = I915_READ(DSPTILEOFF(plane)); |
7995 | else | |
7996 | offset = I915_READ(DSPLINOFF(plane)); | |
7997 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
7998 | } else { | |
7999 | base = I915_READ(DSPADDR(plane)); | |
8000 | } | |
8001 | plane_config->base = base; | |
8002 | ||
8003 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8004 | fb->width = ((val >> 16) & 0xfff) + 1; |
8005 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
8006 | |
8007 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8008 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 8009 | |
b113d5ee | 8010 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
8011 | fb->pixel_format, |
8012 | fb->modifier[0]); | |
1ad292b5 | 8013 | |
f37b5c2b | 8014 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 8015 | |
2844a921 DL |
8016 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8017 | pipe_name(pipe), plane, fb->width, fb->height, | |
8018 | fb->bits_per_pixel, base, fb->pitches[0], | |
8019 | plane_config->size); | |
1ad292b5 | 8020 | |
2d14030b | 8021 | plane_config->fb = intel_fb; |
1ad292b5 JB |
8022 | } |
8023 | ||
70b23a98 | 8024 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8025 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
8026 | { |
8027 | struct drm_device *dev = crtc->base.dev; | |
8028 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8029 | int pipe = pipe_config->cpu_transcoder; | |
8030 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
8031 | intel_clock_t clock; | |
0d7b6b11 | 8032 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
8033 | int refclk = 100000; |
8034 | ||
a580516d | 8035 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
8036 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
8037 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
8038 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
8039 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 8040 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 8041 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
8042 | |
8043 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
8044 | clock.m2 = (pll_dw0 & 0xff) << 22; |
8045 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
8046 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
8047 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
8048 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
8049 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
8050 | ||
dccbea3b | 8051 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
8052 | } |
8053 | ||
0e8ffe1b | 8054 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8055 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8056 | { |
8057 | struct drm_device *dev = crtc->base.dev; | |
8058 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8059 | uint32_t tmp; | |
8060 | ||
f458ebbc DV |
8061 | if (!intel_display_power_is_enabled(dev_priv, |
8062 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
b5482bd0 ID |
8063 | return false; |
8064 | ||
e143a21c | 8065 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 8066 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 8067 | |
0e8ffe1b DV |
8068 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8069 | if (!(tmp & PIPECONF_ENABLE)) | |
8070 | return false; | |
8071 | ||
42571aef VS |
8072 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
8073 | switch (tmp & PIPECONF_BPC_MASK) { | |
8074 | case PIPECONF_6BPC: | |
8075 | pipe_config->pipe_bpp = 18; | |
8076 | break; | |
8077 | case PIPECONF_8BPC: | |
8078 | pipe_config->pipe_bpp = 24; | |
8079 | break; | |
8080 | case PIPECONF_10BPC: | |
8081 | pipe_config->pipe_bpp = 30; | |
8082 | break; | |
8083 | default: | |
8084 | break; | |
8085 | } | |
8086 | } | |
8087 | ||
b5a9fa09 DV |
8088 | if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
8089 | pipe_config->limited_color_range = true; | |
8090 | ||
282740f7 VS |
8091 | if (INTEL_INFO(dev)->gen < 4) |
8092 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
8093 | ||
1bd1bd80 DV |
8094 | intel_get_pipe_timings(crtc, pipe_config); |
8095 | ||
2fa2fe9a DV |
8096 | i9xx_get_pfit_config(crtc, pipe_config); |
8097 | ||
6c49f241 DV |
8098 | if (INTEL_INFO(dev)->gen >= 4) { |
8099 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
8100 | pipe_config->pixel_multiplier = | |
8101 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
8102 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 8103 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
8104 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
8105 | tmp = I915_READ(DPLL(crtc->pipe)); | |
8106 | pipe_config->pixel_multiplier = | |
8107 | ((tmp & SDVO_MULTIPLIER_MASK) | |
8108 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
8109 | } else { | |
8110 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
8111 | * port and will be fixed up in the encoder->get_config | |
8112 | * function. */ | |
8113 | pipe_config->pixel_multiplier = 1; | |
8114 | } | |
8bcc2795 DV |
8115 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
8116 | if (!IS_VALLEYVIEW(dev)) { | |
1c4e0274 VS |
8117 | /* |
8118 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
8119 | * on 830. Filter it out here so that we don't | |
8120 | * report errors due to that. | |
8121 | */ | |
8122 | if (IS_I830(dev)) | |
8123 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
8124 | ||
8bcc2795 DV |
8125 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
8126 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
8127 | } else { |
8128 | /* Mask out read-only status bits. */ | |
8129 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
8130 | DPLL_PORTC_READY_MASK | | |
8131 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 8132 | } |
6c49f241 | 8133 | |
70b23a98 VS |
8134 | if (IS_CHERRYVIEW(dev)) |
8135 | chv_crtc_clock_get(crtc, pipe_config); | |
8136 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
8137 | vlv_crtc_clock_get(crtc, pipe_config); |
8138 | else | |
8139 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 8140 | |
0f64614d VS |
8141 | /* |
8142 | * Normally the dotclock is filled in by the encoder .get_config() | |
8143 | * but in case the pipe is enabled w/o any ports we need a sane | |
8144 | * default. | |
8145 | */ | |
8146 | pipe_config->base.adjusted_mode.crtc_clock = | |
8147 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
8148 | ||
0e8ffe1b DV |
8149 | return true; |
8150 | } | |
8151 | ||
dde86e2d | 8152 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
8153 | { |
8154 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 8155 | struct intel_encoder *encoder; |
74cfd7ac | 8156 | u32 val, final; |
13d83a67 | 8157 | bool has_lvds = false; |
199e5d79 | 8158 | bool has_cpu_edp = false; |
199e5d79 | 8159 | bool has_panel = false; |
99eb6a01 KP |
8160 | bool has_ck505 = false; |
8161 | bool can_ssc = false; | |
13d83a67 JB |
8162 | |
8163 | /* We need to take the global config into account */ | |
b2784e15 | 8164 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
8165 | switch (encoder->type) { |
8166 | case INTEL_OUTPUT_LVDS: | |
8167 | has_panel = true; | |
8168 | has_lvds = true; | |
8169 | break; | |
8170 | case INTEL_OUTPUT_EDP: | |
8171 | has_panel = true; | |
2de6905f | 8172 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
8173 | has_cpu_edp = true; |
8174 | break; | |
6847d71b PZ |
8175 | default: |
8176 | break; | |
13d83a67 JB |
8177 | } |
8178 | } | |
8179 | ||
99eb6a01 | 8180 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 8181 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
8182 | can_ssc = has_ck505; |
8183 | } else { | |
8184 | has_ck505 = false; | |
8185 | can_ssc = true; | |
8186 | } | |
8187 | ||
2de6905f ID |
8188 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
8189 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
8190 | |
8191 | /* Ironlake: try to setup display ref clock before DPLL | |
8192 | * enabling. This is only under driver's control after | |
8193 | * PCH B stepping, previous chipset stepping should be | |
8194 | * ignoring this setting. | |
8195 | */ | |
74cfd7ac CW |
8196 | val = I915_READ(PCH_DREF_CONTROL); |
8197 | ||
8198 | /* As we must carefully and slowly disable/enable each source in turn, | |
8199 | * compute the final state we want first and check if we need to | |
8200 | * make any changes at all. | |
8201 | */ | |
8202 | final = val; | |
8203 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
8204 | if (has_ck505) | |
8205 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
8206 | else | |
8207 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
8208 | ||
8209 | final &= ~DREF_SSC_SOURCE_MASK; | |
8210 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
8211 | final &= ~DREF_SSC1_ENABLE; | |
8212 | ||
8213 | if (has_panel) { | |
8214 | final |= DREF_SSC_SOURCE_ENABLE; | |
8215 | ||
8216 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8217 | final |= DREF_SSC1_ENABLE; | |
8218 | ||
8219 | if (has_cpu_edp) { | |
8220 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8221 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
8222 | else | |
8223 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
8224 | } else | |
8225 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8226 | } else { | |
8227 | final |= DREF_SSC_SOURCE_DISABLE; | |
8228 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8229 | } | |
8230 | ||
8231 | if (final == val) | |
8232 | return; | |
8233 | ||
13d83a67 | 8234 | /* Always enable nonspread source */ |
74cfd7ac | 8235 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 8236 | |
99eb6a01 | 8237 | if (has_ck505) |
74cfd7ac | 8238 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 8239 | else |
74cfd7ac | 8240 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 8241 | |
199e5d79 | 8242 | if (has_panel) { |
74cfd7ac CW |
8243 | val &= ~DREF_SSC_SOURCE_MASK; |
8244 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 8245 | |
199e5d79 | 8246 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 8247 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8248 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 8249 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 8250 | } else |
74cfd7ac | 8251 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
8252 | |
8253 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 8254 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8255 | POSTING_READ(PCH_DREF_CONTROL); |
8256 | udelay(200); | |
8257 | ||
74cfd7ac | 8258 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
8259 | |
8260 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 8261 | if (has_cpu_edp) { |
99eb6a01 | 8262 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8263 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 8264 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 8265 | } else |
74cfd7ac | 8266 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 8267 | } else |
74cfd7ac | 8268 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8269 | |
74cfd7ac | 8270 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8271 | POSTING_READ(PCH_DREF_CONTROL); |
8272 | udelay(200); | |
8273 | } else { | |
8274 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
8275 | ||
74cfd7ac | 8276 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
8277 | |
8278 | /* Turn off CPU output */ | |
74cfd7ac | 8279 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8280 | |
74cfd7ac | 8281 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8282 | POSTING_READ(PCH_DREF_CONTROL); |
8283 | udelay(200); | |
8284 | ||
8285 | /* Turn off the SSC source */ | |
74cfd7ac CW |
8286 | val &= ~DREF_SSC_SOURCE_MASK; |
8287 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
8288 | |
8289 | /* Turn off SSC1 */ | |
74cfd7ac | 8290 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 8291 | |
74cfd7ac | 8292 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
8293 | POSTING_READ(PCH_DREF_CONTROL); |
8294 | udelay(200); | |
8295 | } | |
74cfd7ac CW |
8296 | |
8297 | BUG_ON(val != final); | |
13d83a67 JB |
8298 | } |
8299 | ||
f31f2d55 | 8300 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 8301 | { |
f31f2d55 | 8302 | uint32_t tmp; |
dde86e2d | 8303 | |
0ff066a9 PZ |
8304 | tmp = I915_READ(SOUTH_CHICKEN2); |
8305 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
8306 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8307 | |
0ff066a9 PZ |
8308 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
8309 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
8310 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 8311 | |
0ff066a9 PZ |
8312 | tmp = I915_READ(SOUTH_CHICKEN2); |
8313 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
8314 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8315 | |
0ff066a9 PZ |
8316 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
8317 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
8318 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
8319 | } |
8320 | ||
8321 | /* WaMPhyProgramming:hsw */ | |
8322 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
8323 | { | |
8324 | uint32_t tmp; | |
dde86e2d PZ |
8325 | |
8326 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
8327 | tmp &= ~(0xFF << 24); | |
8328 | tmp |= (0x12 << 24); | |
8329 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
8330 | ||
dde86e2d PZ |
8331 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
8332 | tmp |= (1 << 11); | |
8333 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
8334 | ||
8335 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
8336 | tmp |= (1 << 11); | |
8337 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
8338 | ||
dde86e2d PZ |
8339 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
8340 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8341 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
8342 | ||
8343 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
8344 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8345 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
8346 | ||
0ff066a9 PZ |
8347 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
8348 | tmp &= ~(7 << 13); | |
8349 | tmp |= (5 << 13); | |
8350 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 8351 | |
0ff066a9 PZ |
8352 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
8353 | tmp &= ~(7 << 13); | |
8354 | tmp |= (5 << 13); | |
8355 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
8356 | |
8357 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
8358 | tmp &= ~0xFF; | |
8359 | tmp |= 0x1C; | |
8360 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
8361 | ||
8362 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
8363 | tmp &= ~0xFF; | |
8364 | tmp |= 0x1C; | |
8365 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
8366 | ||
8367 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
8368 | tmp &= ~(0xFF << 16); | |
8369 | tmp |= (0x1C << 16); | |
8370 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
8371 | ||
8372 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
8373 | tmp &= ~(0xFF << 16); | |
8374 | tmp |= (0x1C << 16); | |
8375 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
8376 | ||
0ff066a9 PZ |
8377 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
8378 | tmp |= (1 << 27); | |
8379 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 8380 | |
0ff066a9 PZ |
8381 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
8382 | tmp |= (1 << 27); | |
8383 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 8384 | |
0ff066a9 PZ |
8385 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
8386 | tmp &= ~(0xF << 28); | |
8387 | tmp |= (4 << 28); | |
8388 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 8389 | |
0ff066a9 PZ |
8390 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
8391 | tmp &= ~(0xF << 28); | |
8392 | tmp |= (4 << 28); | |
8393 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
8394 | } |
8395 | ||
2fa86a1f PZ |
8396 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
8397 | * Programming" based on the parameters passed: | |
8398 | * - Sequence to enable CLKOUT_DP | |
8399 | * - Sequence to enable CLKOUT_DP without spread | |
8400 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
8401 | */ | |
8402 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
8403 | bool with_fdi) | |
f31f2d55 PZ |
8404 | { |
8405 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
8406 | uint32_t reg, tmp; |
8407 | ||
8408 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
8409 | with_spread = true; | |
c2699524 | 8410 | if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n")) |
2fa86a1f | 8411 | with_fdi = false; |
f31f2d55 | 8412 | |
a580516d | 8413 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
8414 | |
8415 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8416 | tmp &= ~SBI_SSCCTL_DISABLE; | |
8417 | tmp |= SBI_SSCCTL_PATHALT; | |
8418 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8419 | ||
8420 | udelay(24); | |
8421 | ||
2fa86a1f PZ |
8422 | if (with_spread) { |
8423 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8424 | tmp &= ~SBI_SSCCTL_PATHALT; | |
8425 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 8426 | |
2fa86a1f PZ |
8427 | if (with_fdi) { |
8428 | lpt_reset_fdi_mphy(dev_priv); | |
8429 | lpt_program_fdi_mphy(dev_priv); | |
8430 | } | |
8431 | } | |
dde86e2d | 8432 | |
c2699524 | 8433 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
8434 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8435 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8436 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 8437 | |
a580516d | 8438 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
8439 | } |
8440 | ||
47701c3b PZ |
8441 | /* Sequence to disable CLKOUT_DP */ |
8442 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
8443 | { | |
8444 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8445 | uint32_t reg, tmp; | |
8446 | ||
a580516d | 8447 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 8448 | |
c2699524 | 8449 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
8450 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8451 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8452 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
8453 | ||
8454 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8455 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
8456 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
8457 | tmp |= SBI_SSCCTL_PATHALT; | |
8458 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8459 | udelay(32); | |
8460 | } | |
8461 | tmp |= SBI_SSCCTL_DISABLE; | |
8462 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8463 | } | |
8464 | ||
a580516d | 8465 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
8466 | } |
8467 | ||
bf8fa3d3 PZ |
8468 | static void lpt_init_pch_refclk(struct drm_device *dev) |
8469 | { | |
bf8fa3d3 PZ |
8470 | struct intel_encoder *encoder; |
8471 | bool has_vga = false; | |
8472 | ||
b2784e15 | 8473 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
8474 | switch (encoder->type) { |
8475 | case INTEL_OUTPUT_ANALOG: | |
8476 | has_vga = true; | |
8477 | break; | |
6847d71b PZ |
8478 | default: |
8479 | break; | |
bf8fa3d3 PZ |
8480 | } |
8481 | } | |
8482 | ||
47701c3b PZ |
8483 | if (has_vga) |
8484 | lpt_enable_clkout_dp(dev, true, true); | |
8485 | else | |
8486 | lpt_disable_clkout_dp(dev); | |
bf8fa3d3 PZ |
8487 | } |
8488 | ||
dde86e2d PZ |
8489 | /* |
8490 | * Initialize reference clocks when the driver loads | |
8491 | */ | |
8492 | void intel_init_pch_refclk(struct drm_device *dev) | |
8493 | { | |
8494 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
8495 | ironlake_init_pch_refclk(dev); | |
8496 | else if (HAS_PCH_LPT(dev)) | |
8497 | lpt_init_pch_refclk(dev); | |
8498 | } | |
8499 | ||
55bb9992 | 8500 | static int ironlake_get_refclk(struct intel_crtc_state *crtc_state) |
d9d444cb | 8501 | { |
55bb9992 | 8502 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d9d444cb | 8503 | struct drm_i915_private *dev_priv = dev->dev_private; |
55bb9992 | 8504 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8505 | struct drm_connector *connector; |
55bb9992 | 8506 | struct drm_connector_state *connector_state; |
d9d444cb | 8507 | struct intel_encoder *encoder; |
55bb9992 | 8508 | int num_connectors = 0, i; |
d9d444cb JB |
8509 | bool is_lvds = false; |
8510 | ||
da3ced29 | 8511 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8512 | if (connector_state->crtc != crtc_state->base.crtc) |
8513 | continue; | |
8514 | ||
8515 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8516 | ||
d9d444cb JB |
8517 | switch (encoder->type) { |
8518 | case INTEL_OUTPUT_LVDS: | |
8519 | is_lvds = true; | |
8520 | break; | |
6847d71b PZ |
8521 | default: |
8522 | break; | |
d9d444cb JB |
8523 | } |
8524 | num_connectors++; | |
8525 | } | |
8526 | ||
8527 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 8528 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 8529 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 8530 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
8531 | } |
8532 | ||
8533 | return 120000; | |
8534 | } | |
8535 | ||
6ff93609 | 8536 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 8537 | { |
c8203565 | 8538 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
8539 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8540 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
8541 | uint32_t val; |
8542 | ||
78114071 | 8543 | val = 0; |
c8203565 | 8544 | |
6e3c9717 | 8545 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 8546 | case 18: |
dfd07d72 | 8547 | val |= PIPECONF_6BPC; |
c8203565 PZ |
8548 | break; |
8549 | case 24: | |
dfd07d72 | 8550 | val |= PIPECONF_8BPC; |
c8203565 PZ |
8551 | break; |
8552 | case 30: | |
dfd07d72 | 8553 | val |= PIPECONF_10BPC; |
c8203565 PZ |
8554 | break; |
8555 | case 36: | |
dfd07d72 | 8556 | val |= PIPECONF_12BPC; |
c8203565 PZ |
8557 | break; |
8558 | default: | |
cc769b62 PZ |
8559 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
8560 | BUG(); | |
c8203565 PZ |
8561 | } |
8562 | ||
6e3c9717 | 8563 | if (intel_crtc->config->dither) |
c8203565 PZ |
8564 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8565 | ||
6e3c9717 | 8566 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
8567 | val |= PIPECONF_INTERLACED_ILK; |
8568 | else | |
8569 | val |= PIPECONF_PROGRESSIVE; | |
8570 | ||
6e3c9717 | 8571 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 8572 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 8573 | |
c8203565 PZ |
8574 | I915_WRITE(PIPECONF(pipe), val); |
8575 | POSTING_READ(PIPECONF(pipe)); | |
8576 | } | |
8577 | ||
86d3efce VS |
8578 | /* |
8579 | * Set up the pipe CSC unit. | |
8580 | * | |
8581 | * Currently only full range RGB to limited range RGB conversion | |
8582 | * is supported, but eventually this should handle various | |
8583 | * RGB<->YCbCr scenarios as well. | |
8584 | */ | |
50f3b016 | 8585 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
8586 | { |
8587 | struct drm_device *dev = crtc->dev; | |
8588 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8589 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8590 | int pipe = intel_crtc->pipe; | |
8591 | uint16_t coeff = 0x7800; /* 1.0 */ | |
8592 | ||
8593 | /* | |
8594 | * TODO: Check what kind of values actually come out of the pipe | |
8595 | * with these coeff/postoff values and adjust to get the best | |
8596 | * accuracy. Perhaps we even need to take the bpc value into | |
8597 | * consideration. | |
8598 | */ | |
8599 | ||
6e3c9717 | 8600 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8601 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
8602 | ||
8603 | /* | |
8604 | * GY/GU and RY/RU should be the other way around according | |
8605 | * to BSpec, but reality doesn't agree. Just set them up in | |
8606 | * a way that results in the correct picture. | |
8607 | */ | |
8608 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
8609 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
8610 | ||
8611 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
8612 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
8613 | ||
8614 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
8615 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
8616 | ||
8617 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
8618 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
8619 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
8620 | ||
8621 | if (INTEL_INFO(dev)->gen > 6) { | |
8622 | uint16_t postoff = 0; | |
8623 | ||
6e3c9717 | 8624 | if (intel_crtc->config->limited_color_range) |
32cf0cb0 | 8625 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
8626 | |
8627 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
8628 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
8629 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
8630 | ||
8631 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
8632 | } else { | |
8633 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
8634 | ||
6e3c9717 | 8635 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8636 | mode |= CSC_BLACK_SCREEN_OFFSET; |
8637 | ||
8638 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
8639 | } | |
8640 | } | |
8641 | ||
6ff93609 | 8642 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8643 | { |
756f85cf PZ |
8644 | struct drm_device *dev = crtc->dev; |
8645 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 8646 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 8647 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 8648 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee2b0b38 PZ |
8649 | uint32_t val; |
8650 | ||
3eff4faa | 8651 | val = 0; |
ee2b0b38 | 8652 | |
6e3c9717 | 8653 | if (IS_HASWELL(dev) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8654 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8655 | ||
6e3c9717 | 8656 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8657 | val |= PIPECONF_INTERLACED_ILK; |
8658 | else | |
8659 | val |= PIPECONF_PROGRESSIVE; | |
8660 | ||
702e7a56 PZ |
8661 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8662 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
8663 | |
8664 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
8665 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf | 8666 | |
3cdf122c | 8667 | if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { |
756f85cf PZ |
8668 | val = 0; |
8669 | ||
6e3c9717 | 8670 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8671 | case 18: |
8672 | val |= PIPEMISC_DITHER_6_BPC; | |
8673 | break; | |
8674 | case 24: | |
8675 | val |= PIPEMISC_DITHER_8_BPC; | |
8676 | break; | |
8677 | case 30: | |
8678 | val |= PIPEMISC_DITHER_10_BPC; | |
8679 | break; | |
8680 | case 36: | |
8681 | val |= PIPEMISC_DITHER_12_BPC; | |
8682 | break; | |
8683 | default: | |
8684 | /* Case prevented by pipe_config_set_bpp. */ | |
8685 | BUG(); | |
8686 | } | |
8687 | ||
6e3c9717 | 8688 | if (intel_crtc->config->dither) |
756f85cf PZ |
8689 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8690 | ||
8691 | I915_WRITE(PIPEMISC(pipe), val); | |
8692 | } | |
ee2b0b38 PZ |
8693 | } |
8694 | ||
6591c6e4 | 8695 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
190f68c5 | 8696 | struct intel_crtc_state *crtc_state, |
6591c6e4 PZ |
8697 | intel_clock_t *clock, |
8698 | bool *has_reduced_clock, | |
8699 | intel_clock_t *reduced_clock) | |
8700 | { | |
8701 | struct drm_device *dev = crtc->dev; | |
8702 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6591c6e4 | 8703 | int refclk; |
d4906093 | 8704 | const intel_limit_t *limit; |
c329a4ec | 8705 | bool ret; |
79e53945 | 8706 | |
55bb9992 | 8707 | refclk = ironlake_get_refclk(crtc_state); |
79e53945 | 8708 | |
d4906093 ML |
8709 | /* |
8710 | * Returns a set of divisors for the desired target clock with the given | |
8711 | * refclk, or FALSE. The returned values represent the clock equation: | |
8712 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
8713 | */ | |
a93e255f ACO |
8714 | limit = intel_limit(crtc_state, refclk); |
8715 | ret = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 8716 | crtc_state->port_clock, |
ee9300bb | 8717 | refclk, NULL, clock); |
6591c6e4 PZ |
8718 | if (!ret) |
8719 | return false; | |
cda4b7d3 | 8720 | |
6591c6e4 PZ |
8721 | return true; |
8722 | } | |
8723 | ||
d4b1931c PZ |
8724 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
8725 | { | |
8726 | /* | |
8727 | * Account for spread spectrum to avoid | |
8728 | * oversubscribing the link. Max center spread | |
8729 | * is 2.5%; use 5% for safety's sake. | |
8730 | */ | |
8731 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 8732 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
8733 | } |
8734 | ||
7429e9d4 | 8735 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 8736 | { |
7429e9d4 | 8737 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
8738 | } |
8739 | ||
de13a2e3 | 8740 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
190f68c5 | 8741 | struct intel_crtc_state *crtc_state, |
7429e9d4 | 8742 | u32 *fp, |
9a7c7890 | 8743 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 8744 | { |
de13a2e3 | 8745 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
8746 | struct drm_device *dev = crtc->dev; |
8747 | struct drm_i915_private *dev_priv = dev->dev_private; | |
55bb9992 | 8748 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8749 | struct drm_connector *connector; |
55bb9992 ACO |
8750 | struct drm_connector_state *connector_state; |
8751 | struct intel_encoder *encoder; | |
de13a2e3 | 8752 | uint32_t dpll; |
55bb9992 | 8753 | int factor, num_connectors = 0, i; |
09ede541 | 8754 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 8755 | |
da3ced29 | 8756 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8757 | if (connector_state->crtc != crtc_state->base.crtc) |
8758 | continue; | |
8759 | ||
8760 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8761 | ||
8762 | switch (encoder->type) { | |
79e53945 JB |
8763 | case INTEL_OUTPUT_LVDS: |
8764 | is_lvds = true; | |
8765 | break; | |
8766 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 8767 | case INTEL_OUTPUT_HDMI: |
79e53945 | 8768 | is_sdvo = true; |
79e53945 | 8769 | break; |
6847d71b PZ |
8770 | default: |
8771 | break; | |
79e53945 | 8772 | } |
43565a06 | 8773 | |
c751ce4f | 8774 | num_connectors++; |
79e53945 | 8775 | } |
79e53945 | 8776 | |
c1858123 | 8777 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
8778 | factor = 21; |
8779 | if (is_lvds) { | |
8780 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 8781 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 8782 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 8783 | factor = 25; |
190f68c5 | 8784 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 8785 | factor = 20; |
c1858123 | 8786 | |
190f68c5 | 8787 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
7d0ac5b7 | 8788 | *fp |= FP_CB_TUNE; |
2c07245f | 8789 | |
9a7c7890 DV |
8790 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
8791 | *fp2 |= FP_CB_TUNE; | |
8792 | ||
5eddb70b | 8793 | dpll = 0; |
2c07245f | 8794 | |
a07d6787 EA |
8795 | if (is_lvds) |
8796 | dpll |= DPLLB_MODE_LVDS; | |
8797 | else | |
8798 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 8799 | |
190f68c5 | 8800 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8801 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f DV |
8802 | |
8803 | if (is_sdvo) | |
4a33e48d | 8804 | dpll |= DPLL_SDVO_HIGH_SPEED; |
190f68c5 | 8805 | if (crtc_state->has_dp_encoder) |
4a33e48d | 8806 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 8807 | |
a07d6787 | 8808 | /* compute bitmask from p1 value */ |
190f68c5 | 8809 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 8810 | /* also FPA1 */ |
190f68c5 | 8811 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 8812 | |
190f68c5 | 8813 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
8814 | case 5: |
8815 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8816 | break; | |
8817 | case 7: | |
8818 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8819 | break; | |
8820 | case 10: | |
8821 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8822 | break; | |
8823 | case 14: | |
8824 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8825 | break; | |
79e53945 JB |
8826 | } |
8827 | ||
b4c09f3b | 8828 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 8829 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
8830 | else |
8831 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8832 | ||
959e16d6 | 8833 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
8834 | } |
8835 | ||
190f68c5 ACO |
8836 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
8837 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 8838 | { |
c7653199 | 8839 | struct drm_device *dev = crtc->base.dev; |
de13a2e3 | 8840 | intel_clock_t clock, reduced_clock; |
cbbab5bd | 8841 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 8842 | bool ok, has_reduced_clock = false; |
8b47047b | 8843 | bool is_lvds = false; |
e2b78267 | 8844 | struct intel_shared_dpll *pll; |
de13a2e3 | 8845 | |
dd3cd74a ACO |
8846 | memset(&crtc_state->dpll_hw_state, 0, |
8847 | sizeof(crtc_state->dpll_hw_state)); | |
8848 | ||
409ee761 | 8849 | is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS); |
79e53945 | 8850 | |
5dc5298b PZ |
8851 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
8852 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 8853 | |
190f68c5 | 8854 | ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock, |
de13a2e3 | 8855 | &has_reduced_clock, &reduced_clock); |
190f68c5 | 8856 | if (!ok && !crtc_state->clock_set) { |
de13a2e3 PZ |
8857 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
8858 | return -EINVAL; | |
79e53945 | 8859 | } |
f47709a9 | 8860 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
8861 | if (!crtc_state->clock_set) { |
8862 | crtc_state->dpll.n = clock.n; | |
8863 | crtc_state->dpll.m1 = clock.m1; | |
8864 | crtc_state->dpll.m2 = clock.m2; | |
8865 | crtc_state->dpll.p1 = clock.p1; | |
8866 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 8867 | } |
79e53945 | 8868 | |
5dc5298b | 8869 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
190f68c5 ACO |
8870 | if (crtc_state->has_pch_encoder) { |
8871 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); | |
cbbab5bd | 8872 | if (has_reduced_clock) |
7429e9d4 | 8873 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 8874 | |
190f68c5 | 8875 | dpll = ironlake_compute_dpll(crtc, crtc_state, |
cbbab5bd DV |
8876 | &fp, &reduced_clock, |
8877 | has_reduced_clock ? &fp2 : NULL); | |
8878 | ||
190f68c5 ACO |
8879 | crtc_state->dpll_hw_state.dpll = dpll; |
8880 | crtc_state->dpll_hw_state.fp0 = fp; | |
66e985c0 | 8881 | if (has_reduced_clock) |
190f68c5 | 8882 | crtc_state->dpll_hw_state.fp1 = fp2; |
66e985c0 | 8883 | else |
190f68c5 | 8884 | crtc_state->dpll_hw_state.fp1 = fp; |
66e985c0 | 8885 | |
190f68c5 | 8886 | pll = intel_get_shared_dpll(crtc, crtc_state); |
ee7b9f93 | 8887 | if (pll == NULL) { |
84f44ce7 | 8888 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
c7653199 | 8889 | pipe_name(crtc->pipe)); |
4b645f14 JB |
8890 | return -EINVAL; |
8891 | } | |
3fb37703 | 8892 | } |
79e53945 | 8893 | |
ab585dea | 8894 | if (is_lvds && has_reduced_clock) |
c7653199 | 8895 | crtc->lowfreq_avail = true; |
bcd644e0 | 8896 | else |
c7653199 | 8897 | crtc->lowfreq_avail = false; |
e2b78267 | 8898 | |
c8f7a0db | 8899 | return 0; |
79e53945 JB |
8900 | } |
8901 | ||
eb14cb74 VS |
8902 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
8903 | struct intel_link_m_n *m_n) | |
8904 | { | |
8905 | struct drm_device *dev = crtc->base.dev; | |
8906 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8907 | enum pipe pipe = crtc->pipe; | |
8908 | ||
8909 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
8910 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
8911 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8912 | & ~TU_SIZE_MASK; | |
8913 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
8914 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8915 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8916 | } | |
8917 | ||
8918 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
8919 | enum transcoder transcoder, | |
b95af8be VK |
8920 | struct intel_link_m_n *m_n, |
8921 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
8922 | { |
8923 | struct drm_device *dev = crtc->base.dev; | |
8924 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 8925 | enum pipe pipe = crtc->pipe; |
72419203 | 8926 | |
eb14cb74 VS |
8927 | if (INTEL_INFO(dev)->gen >= 5) { |
8928 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
8929 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
8930 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
8931 | & ~TU_SIZE_MASK; | |
8932 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
8933 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
8934 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
8935 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
8936 | * gen < 8) and if DRRS is supported (to make sure the | |
8937 | * registers are not unnecessarily read). | |
8938 | */ | |
8939 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 8940 | crtc->config->has_drrs) { |
b95af8be VK |
8941 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
8942 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
8943 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
8944 | & ~TU_SIZE_MASK; | |
8945 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
8946 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
8947 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8948 | } | |
eb14cb74 VS |
8949 | } else { |
8950 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
8951 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
8952 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8953 | & ~TU_SIZE_MASK; | |
8954 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
8955 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8956 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8957 | } | |
8958 | } | |
8959 | ||
8960 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 8961 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 8962 | { |
681a8504 | 8963 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
8964 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
8965 | else | |
8966 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
8967 | &pipe_config->dp_m_n, |
8968 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 8969 | } |
72419203 | 8970 | |
eb14cb74 | 8971 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 8972 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
8973 | { |
8974 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 8975 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
8976 | } |
8977 | ||
bd2e244f | 8978 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8979 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
8980 | { |
8981 | struct drm_device *dev = crtc->base.dev; | |
8982 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a1b2278e CK |
8983 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
8984 | uint32_t ps_ctrl = 0; | |
8985 | int id = -1; | |
8986 | int i; | |
bd2e244f | 8987 | |
a1b2278e CK |
8988 | /* find scaler attached to this pipe */ |
8989 | for (i = 0; i < crtc->num_scalers; i++) { | |
8990 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
8991 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
8992 | id = i; | |
8993 | pipe_config->pch_pfit.enabled = true; | |
8994 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
8995 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
8996 | break; | |
8997 | } | |
8998 | } | |
bd2e244f | 8999 | |
a1b2278e CK |
9000 | scaler_state->scaler_id = id; |
9001 | if (id >= 0) { | |
9002 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
9003 | } else { | |
9004 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
9005 | } |
9006 | } | |
9007 | ||
5724dbd1 DL |
9008 | static void |
9009 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
9010 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
9011 | { |
9012 | struct drm_device *dev = crtc->base.dev; | |
9013 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40f46283 | 9014 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
9015 | int pipe = crtc->pipe; |
9016 | int fourcc, pixel_format; | |
6761dd31 | 9017 | unsigned int aligned_height; |
bc8d7dff | 9018 | struct drm_framebuffer *fb; |
1b842c89 | 9019 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 9020 | |
d9806c9f | 9021 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9022 | if (!intel_fb) { |
bc8d7dff DL |
9023 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9024 | return; | |
9025 | } | |
9026 | ||
1b842c89 DL |
9027 | fb = &intel_fb->base; |
9028 | ||
bc8d7dff | 9029 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
9030 | if (!(val & PLANE_CTL_ENABLE)) |
9031 | goto error; | |
9032 | ||
bc8d7dff DL |
9033 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
9034 | fourcc = skl_format_to_fourcc(pixel_format, | |
9035 | val & PLANE_CTL_ORDER_RGBX, | |
9036 | val & PLANE_CTL_ALPHA_MASK); | |
9037 | fb->pixel_format = fourcc; | |
9038 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
9039 | ||
40f46283 DL |
9040 | tiling = val & PLANE_CTL_TILED_MASK; |
9041 | switch (tiling) { | |
9042 | case PLANE_CTL_TILED_LINEAR: | |
9043 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
9044 | break; | |
9045 | case PLANE_CTL_TILED_X: | |
9046 | plane_config->tiling = I915_TILING_X; | |
9047 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
9048 | break; | |
9049 | case PLANE_CTL_TILED_Y: | |
9050 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
9051 | break; | |
9052 | case PLANE_CTL_TILED_YF: | |
9053 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
9054 | break; | |
9055 | default: | |
9056 | MISSING_CASE(tiling); | |
9057 | goto error; | |
9058 | } | |
9059 | ||
bc8d7dff DL |
9060 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
9061 | plane_config->base = base; | |
9062 | ||
9063 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
9064 | ||
9065 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
9066 | fb->height = ((val >> 16) & 0xfff) + 1; | |
9067 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
9068 | ||
9069 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
40f46283 DL |
9070 | stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0], |
9071 | fb->pixel_format); | |
bc8d7dff DL |
9072 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
9073 | ||
9074 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
9075 | fb->pixel_format, |
9076 | fb->modifier[0]); | |
bc8d7dff | 9077 | |
f37b5c2b | 9078 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
9079 | |
9080 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
9081 | pipe_name(pipe), fb->width, fb->height, | |
9082 | fb->bits_per_pixel, base, fb->pitches[0], | |
9083 | plane_config->size); | |
9084 | ||
2d14030b | 9085 | plane_config->fb = intel_fb; |
bc8d7dff DL |
9086 | return; |
9087 | ||
9088 | error: | |
9089 | kfree(fb); | |
9090 | } | |
9091 | ||
2fa2fe9a | 9092 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9093 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
9094 | { |
9095 | struct drm_device *dev = crtc->base.dev; | |
9096 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9097 | uint32_t tmp; | |
9098 | ||
9099 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
9100 | ||
9101 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 9102 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
9103 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
9104 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
9105 | |
9106 | /* We currently do not free assignements of panel fitters on | |
9107 | * ivb/hsw (since we don't use the higher upscaling modes which | |
9108 | * differentiates them) so just WARN about this case for now. */ | |
9109 | if (IS_GEN7(dev)) { | |
9110 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
9111 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
9112 | } | |
2fa2fe9a | 9113 | } |
79e53945 JB |
9114 | } |
9115 | ||
5724dbd1 DL |
9116 | static void |
9117 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
9118 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
9119 | { |
9120 | struct drm_device *dev = crtc->base.dev; | |
9121 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9122 | u32 val, base, offset; | |
aeee5a49 | 9123 | int pipe = crtc->pipe; |
4c6baa59 | 9124 | int fourcc, pixel_format; |
6761dd31 | 9125 | unsigned int aligned_height; |
b113d5ee | 9126 | struct drm_framebuffer *fb; |
1b842c89 | 9127 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 9128 | |
42a7b088 DL |
9129 | val = I915_READ(DSPCNTR(pipe)); |
9130 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
9131 | return; | |
9132 | ||
d9806c9f | 9133 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9134 | if (!intel_fb) { |
4c6baa59 JB |
9135 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9136 | return; | |
9137 | } | |
9138 | ||
1b842c89 DL |
9139 | fb = &intel_fb->base; |
9140 | ||
18c5247e DV |
9141 | if (INTEL_INFO(dev)->gen >= 4) { |
9142 | if (val & DISPPLANE_TILED) { | |
49af449b | 9143 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
9144 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
9145 | } | |
9146 | } | |
4c6baa59 JB |
9147 | |
9148 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 9149 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
9150 | fb->pixel_format = fourcc; |
9151 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 9152 | |
aeee5a49 | 9153 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 9154 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 9155 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 9156 | } else { |
49af449b | 9157 | if (plane_config->tiling) |
aeee5a49 | 9158 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 9159 | else |
aeee5a49 | 9160 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
9161 | } |
9162 | plane_config->base = base; | |
9163 | ||
9164 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
9165 | fb->width = ((val >> 16) & 0xfff) + 1; |
9166 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
9167 | |
9168 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 9169 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 9170 | |
b113d5ee | 9171 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
9172 | fb->pixel_format, |
9173 | fb->modifier[0]); | |
4c6baa59 | 9174 | |
f37b5c2b | 9175 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 9176 | |
2844a921 DL |
9177 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
9178 | pipe_name(pipe), fb->width, fb->height, | |
9179 | fb->bits_per_pixel, base, fb->pitches[0], | |
9180 | plane_config->size); | |
b113d5ee | 9181 | |
2d14030b | 9182 | plane_config->fb = intel_fb; |
4c6baa59 JB |
9183 | } |
9184 | ||
0e8ffe1b | 9185 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9186 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9187 | { |
9188 | struct drm_device *dev = crtc->base.dev; | |
9189 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9190 | uint32_t tmp; | |
9191 | ||
f458ebbc DV |
9192 | if (!intel_display_power_is_enabled(dev_priv, |
9193 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
930e8c9e PZ |
9194 | return false; |
9195 | ||
e143a21c | 9196 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 9197 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 9198 | |
0e8ffe1b DV |
9199 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
9200 | if (!(tmp & PIPECONF_ENABLE)) | |
9201 | return false; | |
9202 | ||
42571aef VS |
9203 | switch (tmp & PIPECONF_BPC_MASK) { |
9204 | case PIPECONF_6BPC: | |
9205 | pipe_config->pipe_bpp = 18; | |
9206 | break; | |
9207 | case PIPECONF_8BPC: | |
9208 | pipe_config->pipe_bpp = 24; | |
9209 | break; | |
9210 | case PIPECONF_10BPC: | |
9211 | pipe_config->pipe_bpp = 30; | |
9212 | break; | |
9213 | case PIPECONF_12BPC: | |
9214 | pipe_config->pipe_bpp = 36; | |
9215 | break; | |
9216 | default: | |
9217 | break; | |
9218 | } | |
9219 | ||
b5a9fa09 DV |
9220 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
9221 | pipe_config->limited_color_range = true; | |
9222 | ||
ab9412ba | 9223 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
9224 | struct intel_shared_dpll *pll; |
9225 | ||
88adfff1 DV |
9226 | pipe_config->has_pch_encoder = true; |
9227 | ||
627eb5a3 DV |
9228 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
9229 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9230 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
9231 | |
9232 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 9233 | |
c0d43d62 | 9234 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
9235 | pipe_config->shared_dpll = |
9236 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
9237 | } else { |
9238 | tmp = I915_READ(PCH_DPLL_SEL); | |
9239 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
9240 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
9241 | else | |
9242 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
9243 | } | |
66e985c0 DV |
9244 | |
9245 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
9246 | ||
9247 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
9248 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
9249 | |
9250 | tmp = pipe_config->dpll_hw_state.dpll; | |
9251 | pipe_config->pixel_multiplier = | |
9252 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
9253 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
9254 | |
9255 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
9256 | } else { |
9257 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
9258 | } |
9259 | ||
1bd1bd80 DV |
9260 | intel_get_pipe_timings(crtc, pipe_config); |
9261 | ||
2fa2fe9a DV |
9262 | ironlake_get_pfit_config(crtc, pipe_config); |
9263 | ||
0e8ffe1b DV |
9264 | return true; |
9265 | } | |
9266 | ||
be256dc7 PZ |
9267 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
9268 | { | |
9269 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 9270 | struct intel_crtc *crtc; |
be256dc7 | 9271 | |
d3fcc808 | 9272 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 9273 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
9274 | pipe_name(crtc->pipe)); |
9275 | ||
e2c719b7 RC |
9276 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
9277 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
9278 | I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); | |
9279 | I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
9280 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); | |
9281 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
be256dc7 | 9282 | "CPU PWM1 enabled\n"); |
c5107b87 | 9283 | if (IS_HASWELL(dev)) |
e2c719b7 | 9284 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 9285 | "CPU PWM2 enabled\n"); |
e2c719b7 | 9286 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 9287 | "PCH PWM1 enabled\n"); |
e2c719b7 | 9288 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 9289 | "Utility pin enabled\n"); |
e2c719b7 | 9290 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 9291 | |
9926ada1 PZ |
9292 | /* |
9293 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
9294 | * interrupts remain enabled. We used to check for that, but since it's | |
9295 | * gen-specific and since we only disable LCPLL after we fully disable | |
9296 | * the interrupts, the check below should be enough. | |
9297 | */ | |
e2c719b7 | 9298 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
9299 | } |
9300 | ||
9ccd5aeb PZ |
9301 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
9302 | { | |
9303 | struct drm_device *dev = dev_priv->dev; | |
9304 | ||
9305 | if (IS_HASWELL(dev)) | |
9306 | return I915_READ(D_COMP_HSW); | |
9307 | else | |
9308 | return I915_READ(D_COMP_BDW); | |
9309 | } | |
9310 | ||
3c4c9b81 PZ |
9311 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
9312 | { | |
9313 | struct drm_device *dev = dev_priv->dev; | |
9314 | ||
9315 | if (IS_HASWELL(dev)) { | |
9316 | mutex_lock(&dev_priv->rps.hw_lock); | |
9317 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
9318 | val)) | |
f475dadf | 9319 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
9320 | mutex_unlock(&dev_priv->rps.hw_lock); |
9321 | } else { | |
9ccd5aeb PZ |
9322 | I915_WRITE(D_COMP_BDW, val); |
9323 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 9324 | } |
be256dc7 PZ |
9325 | } |
9326 | ||
9327 | /* | |
9328 | * This function implements pieces of two sequences from BSpec: | |
9329 | * - Sequence for display software to disable LCPLL | |
9330 | * - Sequence for display software to allow package C8+ | |
9331 | * The steps implemented here are just the steps that actually touch the LCPLL | |
9332 | * register. Callers should take care of disabling all the display engine | |
9333 | * functions, doing the mode unset, fixing interrupts, etc. | |
9334 | */ | |
6ff58d53 PZ |
9335 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
9336 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
9337 | { |
9338 | uint32_t val; | |
9339 | ||
9340 | assert_can_disable_lcpll(dev_priv); | |
9341 | ||
9342 | val = I915_READ(LCPLL_CTL); | |
9343 | ||
9344 | if (switch_to_fclk) { | |
9345 | val |= LCPLL_CD_SOURCE_FCLK; | |
9346 | I915_WRITE(LCPLL_CTL, val); | |
9347 | ||
9348 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9349 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9350 | DRM_ERROR("Switching to FCLK failed\n"); | |
9351 | ||
9352 | val = I915_READ(LCPLL_CTL); | |
9353 | } | |
9354 | ||
9355 | val |= LCPLL_PLL_DISABLE; | |
9356 | I915_WRITE(LCPLL_CTL, val); | |
9357 | POSTING_READ(LCPLL_CTL); | |
9358 | ||
9359 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
9360 | DRM_ERROR("LCPLL still locked\n"); | |
9361 | ||
9ccd5aeb | 9362 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 9363 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 9364 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9365 | ndelay(100); |
9366 | ||
9ccd5aeb PZ |
9367 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
9368 | 1)) | |
be256dc7 PZ |
9369 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
9370 | ||
9371 | if (allow_power_down) { | |
9372 | val = I915_READ(LCPLL_CTL); | |
9373 | val |= LCPLL_POWER_DOWN_ALLOW; | |
9374 | I915_WRITE(LCPLL_CTL, val); | |
9375 | POSTING_READ(LCPLL_CTL); | |
9376 | } | |
9377 | } | |
9378 | ||
9379 | /* | |
9380 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
9381 | * source. | |
9382 | */ | |
6ff58d53 | 9383 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
9384 | { |
9385 | uint32_t val; | |
9386 | ||
9387 | val = I915_READ(LCPLL_CTL); | |
9388 | ||
9389 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
9390 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
9391 | return; | |
9392 | ||
a8a8bd54 PZ |
9393 | /* |
9394 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
9395 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 9396 | */ |
59bad947 | 9397 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 9398 | |
be256dc7 PZ |
9399 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
9400 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
9401 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 9402 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
9403 | } |
9404 | ||
9ccd5aeb | 9405 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
9406 | val |= D_COMP_COMP_FORCE; |
9407 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 9408 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9409 | |
9410 | val = I915_READ(LCPLL_CTL); | |
9411 | val &= ~LCPLL_PLL_DISABLE; | |
9412 | I915_WRITE(LCPLL_CTL, val); | |
9413 | ||
9414 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
9415 | DRM_ERROR("LCPLL not locked yet\n"); | |
9416 | ||
9417 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
9418 | val = I915_READ(LCPLL_CTL); | |
9419 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9420 | I915_WRITE(LCPLL_CTL, val); | |
9421 | ||
9422 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9423 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9424 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9425 | } | |
215733fa | 9426 | |
59bad947 | 9427 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b6283055 | 9428 | intel_update_cdclk(dev_priv->dev); |
be256dc7 PZ |
9429 | } |
9430 | ||
765dab67 PZ |
9431 | /* |
9432 | * Package states C8 and deeper are really deep PC states that can only be | |
9433 | * reached when all the devices on the system allow it, so even if the graphics | |
9434 | * device allows PC8+, it doesn't mean the system will actually get to these | |
9435 | * states. Our driver only allows PC8+ when going into runtime PM. | |
9436 | * | |
9437 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
9438 | * well is disabled and most interrupts are disabled, and these are also | |
9439 | * requirements for runtime PM. When these conditions are met, we manually do | |
9440 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
9441 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
9442 | * hang the machine. | |
9443 | * | |
9444 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
9445 | * the state of some registers, so when we come back from PC8+ we need to | |
9446 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
9447 | * need to take care of the registers kept by RC6. Notice that this happens even | |
9448 | * if we don't put the device in PCI D3 state (which is what currently happens | |
9449 | * because of the runtime PM support). | |
9450 | * | |
9451 | * For more, read "Display Sequences for Package C8" on the hardware | |
9452 | * documentation. | |
9453 | */ | |
a14cb6fc | 9454 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 9455 | { |
c67a470b PZ |
9456 | struct drm_device *dev = dev_priv->dev; |
9457 | uint32_t val; | |
9458 | ||
c67a470b PZ |
9459 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
9460 | ||
c2699524 | 9461 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9462 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9463 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
9464 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9465 | } | |
9466 | ||
9467 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
9468 | hsw_disable_lcpll(dev_priv, true, true); |
9469 | } | |
9470 | ||
a14cb6fc | 9471 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
9472 | { |
9473 | struct drm_device *dev = dev_priv->dev; | |
9474 | uint32_t val; | |
9475 | ||
c67a470b PZ |
9476 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
9477 | ||
9478 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
9479 | lpt_init_pch_refclk(dev); |
9480 | ||
c2699524 | 9481 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9482 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9483 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
9484 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9485 | } | |
9486 | ||
9487 | intel_prepare_ddi(dev); | |
c67a470b PZ |
9488 | } |
9489 | ||
27c329ed | 9490 | static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
f8437dd1 | 9491 | { |
a821fc46 | 9492 | struct drm_device *dev = old_state->dev; |
27c329ed | 9493 | unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk; |
f8437dd1 | 9494 | |
27c329ed | 9495 | broxton_set_cdclk(dev, req_cdclk); |
f8437dd1 VK |
9496 | } |
9497 | ||
b432e5cf | 9498 | /* compute the max rate for new configuration */ |
27c329ed | 9499 | static int ilk_max_pixel_rate(struct drm_atomic_state *state) |
b432e5cf | 9500 | { |
b432e5cf | 9501 | struct intel_crtc *intel_crtc; |
27c329ed | 9502 | struct intel_crtc_state *crtc_state; |
b432e5cf | 9503 | int max_pixel_rate = 0; |
b432e5cf | 9504 | |
27c329ed ML |
9505 | for_each_intel_crtc(state->dev, intel_crtc) { |
9506 | int pixel_rate; | |
9507 | ||
9508 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); | |
9509 | if (IS_ERR(crtc_state)) | |
9510 | return PTR_ERR(crtc_state); | |
9511 | ||
9512 | if (!crtc_state->base.enable) | |
b432e5cf VS |
9513 | continue; |
9514 | ||
27c329ed | 9515 | pixel_rate = ilk_pipe_pixel_rate(crtc_state); |
b432e5cf VS |
9516 | |
9517 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
27c329ed | 9518 | if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled) |
b432e5cf VS |
9519 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); |
9520 | ||
9521 | max_pixel_rate = max(max_pixel_rate, pixel_rate); | |
9522 | } | |
9523 | ||
9524 | return max_pixel_rate; | |
9525 | } | |
9526 | ||
9527 | static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) | |
9528 | { | |
9529 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9530 | uint32_t val, data; | |
9531 | int ret; | |
9532 | ||
9533 | if (WARN((I915_READ(LCPLL_CTL) & | |
9534 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | | |
9535 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | | |
9536 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | | |
9537 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, | |
9538 | "trying to change cdclk frequency with cdclk not enabled\n")) | |
9539 | return; | |
9540 | ||
9541 | mutex_lock(&dev_priv->rps.hw_lock); | |
9542 | ret = sandybridge_pcode_write(dev_priv, | |
9543 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); | |
9544 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9545 | if (ret) { | |
9546 | DRM_ERROR("failed to inform pcode about cdclk change\n"); | |
9547 | return; | |
9548 | } | |
9549 | ||
9550 | val = I915_READ(LCPLL_CTL); | |
9551 | val |= LCPLL_CD_SOURCE_FCLK; | |
9552 | I915_WRITE(LCPLL_CTL, val); | |
9553 | ||
9554 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9555 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9556 | DRM_ERROR("Switching to FCLK failed\n"); | |
9557 | ||
9558 | val = I915_READ(LCPLL_CTL); | |
9559 | val &= ~LCPLL_CLK_FREQ_MASK; | |
9560 | ||
9561 | switch (cdclk) { | |
9562 | case 450000: | |
9563 | val |= LCPLL_CLK_FREQ_450; | |
9564 | data = 0; | |
9565 | break; | |
9566 | case 540000: | |
9567 | val |= LCPLL_CLK_FREQ_54O_BDW; | |
9568 | data = 1; | |
9569 | break; | |
9570 | case 337500: | |
9571 | val |= LCPLL_CLK_FREQ_337_5_BDW; | |
9572 | data = 2; | |
9573 | break; | |
9574 | case 675000: | |
9575 | val |= LCPLL_CLK_FREQ_675_BDW; | |
9576 | data = 3; | |
9577 | break; | |
9578 | default: | |
9579 | WARN(1, "invalid cdclk frequency\n"); | |
9580 | return; | |
9581 | } | |
9582 | ||
9583 | I915_WRITE(LCPLL_CTL, val); | |
9584 | ||
9585 | val = I915_READ(LCPLL_CTL); | |
9586 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9587 | I915_WRITE(LCPLL_CTL, val); | |
9588 | ||
9589 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9590 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9591 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9592 | ||
9593 | mutex_lock(&dev_priv->rps.hw_lock); | |
9594 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); | |
9595 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9596 | ||
9597 | intel_update_cdclk(dev); | |
9598 | ||
9599 | WARN(cdclk != dev_priv->cdclk_freq, | |
9600 | "cdclk requested %d kHz but got %d kHz\n", | |
9601 | cdclk, dev_priv->cdclk_freq); | |
9602 | } | |
9603 | ||
27c329ed | 9604 | static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state) |
b432e5cf | 9605 | { |
27c329ed ML |
9606 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
9607 | int max_pixclk = ilk_max_pixel_rate(state); | |
b432e5cf VS |
9608 | int cdclk; |
9609 | ||
9610 | /* | |
9611 | * FIXME should also account for plane ratio | |
9612 | * once 64bpp pixel formats are supported. | |
9613 | */ | |
27c329ed | 9614 | if (max_pixclk > 540000) |
b432e5cf | 9615 | cdclk = 675000; |
27c329ed | 9616 | else if (max_pixclk > 450000) |
b432e5cf | 9617 | cdclk = 540000; |
27c329ed | 9618 | else if (max_pixclk > 337500) |
b432e5cf VS |
9619 | cdclk = 450000; |
9620 | else | |
9621 | cdclk = 337500; | |
9622 | ||
9623 | /* | |
9624 | * FIXME move the cdclk caclulation to | |
9625 | * compute_config() so we can fail gracegully. | |
9626 | */ | |
9627 | if (cdclk > dev_priv->max_cdclk_freq) { | |
9628 | DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n", | |
9629 | cdclk, dev_priv->max_cdclk_freq); | |
9630 | cdclk = dev_priv->max_cdclk_freq; | |
9631 | } | |
9632 | ||
27c329ed | 9633 | to_intel_atomic_state(state)->cdclk = cdclk; |
b432e5cf VS |
9634 | |
9635 | return 0; | |
9636 | } | |
9637 | ||
27c329ed | 9638 | static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
b432e5cf | 9639 | { |
27c329ed ML |
9640 | struct drm_device *dev = old_state->dev; |
9641 | unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk; | |
b432e5cf | 9642 | |
27c329ed | 9643 | broadwell_set_cdclk(dev, req_cdclk); |
b432e5cf VS |
9644 | } |
9645 | ||
190f68c5 ACO |
9646 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
9647 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 9648 | { |
190f68c5 | 9649 | if (!intel_ddi_pll_select(crtc, crtc_state)) |
6441ab5f | 9650 | return -EINVAL; |
716c2e55 | 9651 | |
c7653199 | 9652 | crtc->lowfreq_avail = false; |
644cef34 | 9653 | |
c8f7a0db | 9654 | return 0; |
79e53945 JB |
9655 | } |
9656 | ||
3760b59c S |
9657 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
9658 | enum port port, | |
9659 | struct intel_crtc_state *pipe_config) | |
9660 | { | |
9661 | switch (port) { | |
9662 | case PORT_A: | |
9663 | pipe_config->ddi_pll_sel = SKL_DPLL0; | |
9664 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9665 | break; | |
9666 | case PORT_B: | |
9667 | pipe_config->ddi_pll_sel = SKL_DPLL1; | |
9668 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9669 | break; | |
9670 | case PORT_C: | |
9671 | pipe_config->ddi_pll_sel = SKL_DPLL2; | |
9672 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9673 | break; | |
9674 | default: | |
9675 | DRM_ERROR("Incorrect port type\n"); | |
9676 | } | |
9677 | } | |
9678 | ||
96b7dfb7 S |
9679 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
9680 | enum port port, | |
5cec258b | 9681 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 9682 | { |
3148ade7 | 9683 | u32 temp, dpll_ctl1; |
96b7dfb7 S |
9684 | |
9685 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
9686 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
9687 | ||
9688 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 DL |
9689 | case SKL_DPLL0: |
9690 | /* | |
9691 | * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part | |
9692 | * of the shared DPLL framework and thus needs to be read out | |
9693 | * separately | |
9694 | */ | |
9695 | dpll_ctl1 = I915_READ(DPLL_CTRL1); | |
9696 | pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f; | |
9697 | break; | |
96b7dfb7 S |
9698 | case SKL_DPLL1: |
9699 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9700 | break; | |
9701 | case SKL_DPLL2: | |
9702 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9703 | break; | |
9704 | case SKL_DPLL3: | |
9705 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9706 | break; | |
96b7dfb7 S |
9707 | } |
9708 | } | |
9709 | ||
7d2c8175 DL |
9710 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
9711 | enum port port, | |
5cec258b | 9712 | struct intel_crtc_state *pipe_config) |
7d2c8175 DL |
9713 | { |
9714 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); | |
9715 | ||
9716 | switch (pipe_config->ddi_pll_sel) { | |
9717 | case PORT_CLK_SEL_WRPLL1: | |
9718 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; | |
9719 | break; | |
9720 | case PORT_CLK_SEL_WRPLL2: | |
9721 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; | |
9722 | break; | |
9723 | } | |
9724 | } | |
9725 | ||
26804afd | 9726 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 9727 | struct intel_crtc_state *pipe_config) |
26804afd DV |
9728 | { |
9729 | struct drm_device *dev = crtc->base.dev; | |
9730 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 9731 | struct intel_shared_dpll *pll; |
26804afd DV |
9732 | enum port port; |
9733 | uint32_t tmp; | |
9734 | ||
9735 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
9736 | ||
9737 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
9738 | ||
96b7dfb7 S |
9739 | if (IS_SKYLAKE(dev)) |
9740 | skylake_get_ddi_pll(dev_priv, port, pipe_config); | |
3760b59c S |
9741 | else if (IS_BROXTON(dev)) |
9742 | bxt_get_ddi_pll(dev_priv, port, pipe_config); | |
96b7dfb7 S |
9743 | else |
9744 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 9745 | |
d452c5b6 DV |
9746 | if (pipe_config->shared_dpll >= 0) { |
9747 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
9748 | ||
9749 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
9750 | &pipe_config->dpll_hw_state)); | |
9751 | } | |
9752 | ||
26804afd DV |
9753 | /* |
9754 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
9755 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
9756 | * the PCH transcoder is on. | |
9757 | */ | |
ca370455 DL |
9758 | if (INTEL_INFO(dev)->gen < 9 && |
9759 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
9760 | pipe_config->has_pch_encoder = true; |
9761 | ||
9762 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
9763 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9764 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
9765 | ||
9766 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
9767 | } | |
9768 | } | |
9769 | ||
0e8ffe1b | 9770 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9771 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9772 | { |
9773 | struct drm_device *dev = crtc->base.dev; | |
9774 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 9775 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
9776 | uint32_t tmp; |
9777 | ||
f458ebbc | 9778 | if (!intel_display_power_is_enabled(dev_priv, |
b5482bd0 ID |
9779 | POWER_DOMAIN_PIPE(crtc->pipe))) |
9780 | return false; | |
9781 | ||
e143a21c | 9782 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
9783 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
9784 | ||
eccb140b DV |
9785 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
9786 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
9787 | enum pipe trans_edp_pipe; | |
9788 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
9789 | default: | |
9790 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
9791 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
9792 | case TRANS_DDI_EDP_INPUT_A_ON: | |
9793 | trans_edp_pipe = PIPE_A; | |
9794 | break; | |
9795 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
9796 | trans_edp_pipe = PIPE_B; | |
9797 | break; | |
9798 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
9799 | trans_edp_pipe = PIPE_C; | |
9800 | break; | |
9801 | } | |
9802 | ||
9803 | if (trans_edp_pipe == crtc->pipe) | |
9804 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
9805 | } | |
9806 | ||
f458ebbc | 9807 | if (!intel_display_power_is_enabled(dev_priv, |
eccb140b | 9808 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
9809 | return false; |
9810 | ||
eccb140b | 9811 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
9812 | if (!(tmp & PIPECONF_ENABLE)) |
9813 | return false; | |
9814 | ||
26804afd | 9815 | haswell_get_ddi_port_state(crtc, pipe_config); |
627eb5a3 | 9816 | |
1bd1bd80 DV |
9817 | intel_get_pipe_timings(crtc, pipe_config); |
9818 | ||
a1b2278e CK |
9819 | if (INTEL_INFO(dev)->gen >= 9) { |
9820 | skl_init_scalers(dev, crtc, pipe_config); | |
9821 | } | |
9822 | ||
2fa2fe9a | 9823 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
af99ceda CK |
9824 | |
9825 | if (INTEL_INFO(dev)->gen >= 9) { | |
9826 | pipe_config->scaler_state.scaler_id = -1; | |
9827 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
9828 | } | |
9829 | ||
bd2e244f | 9830 | if (intel_display_power_is_enabled(dev_priv, pfit_domain)) { |
1c132b44 | 9831 | if (INTEL_INFO(dev)->gen >= 9) |
bd2e244f | 9832 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 9833 | else |
1c132b44 | 9834 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 9835 | } |
88adfff1 | 9836 | |
e59150dc JB |
9837 | if (IS_HASWELL(dev)) |
9838 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
9839 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 9840 | |
ebb69c95 CT |
9841 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP) { |
9842 | pipe_config->pixel_multiplier = | |
9843 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
9844 | } else { | |
9845 | pipe_config->pixel_multiplier = 1; | |
9846 | } | |
6c49f241 | 9847 | |
0e8ffe1b DV |
9848 | return true; |
9849 | } | |
9850 | ||
560b85bb CW |
9851 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
9852 | { | |
9853 | struct drm_device *dev = crtc->dev; | |
9854 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9855 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 9856 | uint32_t cntl = 0, size = 0; |
560b85bb | 9857 | |
dc41c154 | 9858 | if (base) { |
3dd512fb MR |
9859 | unsigned int width = intel_crtc->base.cursor->state->crtc_w; |
9860 | unsigned int height = intel_crtc->base.cursor->state->crtc_h; | |
dc41c154 VS |
9861 | unsigned int stride = roundup_pow_of_two(width) * 4; |
9862 | ||
9863 | switch (stride) { | |
9864 | default: | |
9865 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
9866 | width, stride); | |
9867 | stride = 256; | |
9868 | /* fallthrough */ | |
9869 | case 256: | |
9870 | case 512: | |
9871 | case 1024: | |
9872 | case 2048: | |
9873 | break; | |
4b0e333e CW |
9874 | } |
9875 | ||
dc41c154 VS |
9876 | cntl |= CURSOR_ENABLE | |
9877 | CURSOR_GAMMA_ENABLE | | |
9878 | CURSOR_FORMAT_ARGB | | |
9879 | CURSOR_STRIDE(stride); | |
9880 | ||
9881 | size = (height << 12) | width; | |
4b0e333e | 9882 | } |
560b85bb | 9883 | |
dc41c154 VS |
9884 | if (intel_crtc->cursor_cntl != 0 && |
9885 | (intel_crtc->cursor_base != base || | |
9886 | intel_crtc->cursor_size != size || | |
9887 | intel_crtc->cursor_cntl != cntl)) { | |
9888 | /* On these chipsets we can only modify the base/size/stride | |
9889 | * whilst the cursor is disabled. | |
9890 | */ | |
9891 | I915_WRITE(_CURACNTR, 0); | |
4b0e333e | 9892 | POSTING_READ(_CURACNTR); |
dc41c154 | 9893 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 9894 | } |
560b85bb | 9895 | |
99d1f387 | 9896 | if (intel_crtc->cursor_base != base) { |
9db4a9c7 | 9897 | I915_WRITE(_CURABASE, base); |
99d1f387 VS |
9898 | intel_crtc->cursor_base = base; |
9899 | } | |
4726e0b0 | 9900 | |
dc41c154 VS |
9901 | if (intel_crtc->cursor_size != size) { |
9902 | I915_WRITE(CURSIZE, size); | |
9903 | intel_crtc->cursor_size = size; | |
4b0e333e | 9904 | } |
560b85bb | 9905 | |
4b0e333e | 9906 | if (intel_crtc->cursor_cntl != cntl) { |
4b0e333e CW |
9907 | I915_WRITE(_CURACNTR, cntl); |
9908 | POSTING_READ(_CURACNTR); | |
4b0e333e | 9909 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 9910 | } |
560b85bb CW |
9911 | } |
9912 | ||
560b85bb | 9913 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
65a21cd6 JB |
9914 | { |
9915 | struct drm_device *dev = crtc->dev; | |
9916 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9917 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9918 | int pipe = intel_crtc->pipe; | |
4b0e333e CW |
9919 | uint32_t cntl; |
9920 | ||
9921 | cntl = 0; | |
9922 | if (base) { | |
9923 | cntl = MCURSOR_GAMMA_ENABLE; | |
3dd512fb | 9924 | switch (intel_crtc->base.cursor->state->crtc_w) { |
4726e0b0 SK |
9925 | case 64: |
9926 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
9927 | break; | |
9928 | case 128: | |
9929 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
9930 | break; | |
9931 | case 256: | |
9932 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
9933 | break; | |
9934 | default: | |
3dd512fb | 9935 | MISSING_CASE(intel_crtc->base.cursor->state->crtc_w); |
4726e0b0 | 9936 | return; |
65a21cd6 | 9937 | } |
4b0e333e | 9938 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 VS |
9939 | |
9940 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
9941 | cntl |= CURSOR_PIPE_CSC_ENABLE; | |
4b0e333e | 9942 | } |
65a21cd6 | 9943 | |
8e7d688b | 9944 | if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) |
4398ad45 VS |
9945 | cntl |= CURSOR_ROTATE_180; |
9946 | ||
4b0e333e CW |
9947 | if (intel_crtc->cursor_cntl != cntl) { |
9948 | I915_WRITE(CURCNTR(pipe), cntl); | |
9949 | POSTING_READ(CURCNTR(pipe)); | |
9950 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 9951 | } |
4b0e333e | 9952 | |
65a21cd6 | 9953 | /* and commit changes on next vblank */ |
5efb3e28 VS |
9954 | I915_WRITE(CURBASE(pipe), base); |
9955 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
9956 | |
9957 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
9958 | } |
9959 | ||
cda4b7d3 | 9960 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
9961 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
9962 | bool on) | |
cda4b7d3 CW |
9963 | { |
9964 | struct drm_device *dev = crtc->dev; | |
9965 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9966 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9967 | int pipe = intel_crtc->pipe; | |
9b4101be ML |
9968 | struct drm_plane_state *cursor_state = crtc->cursor->state; |
9969 | int x = cursor_state->crtc_x; | |
9970 | int y = cursor_state->crtc_y; | |
d6e4db15 | 9971 | u32 base = 0, pos = 0; |
cda4b7d3 | 9972 | |
d6e4db15 | 9973 | if (on) |
cda4b7d3 | 9974 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 9975 | |
6e3c9717 | 9976 | if (x >= intel_crtc->config->pipe_src_w) |
d6e4db15 VS |
9977 | base = 0; |
9978 | ||
6e3c9717 | 9979 | if (y >= intel_crtc->config->pipe_src_h) |
cda4b7d3 CW |
9980 | base = 0; |
9981 | ||
9982 | if (x < 0) { | |
9b4101be | 9983 | if (x + cursor_state->crtc_w <= 0) |
cda4b7d3 CW |
9984 | base = 0; |
9985 | ||
9986 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
9987 | x = -x; | |
9988 | } | |
9989 | pos |= x << CURSOR_X_SHIFT; | |
9990 | ||
9991 | if (y < 0) { | |
9b4101be | 9992 | if (y + cursor_state->crtc_h <= 0) |
cda4b7d3 CW |
9993 | base = 0; |
9994 | ||
9995 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
9996 | y = -y; | |
9997 | } | |
9998 | pos |= y << CURSOR_Y_SHIFT; | |
9999 | ||
4b0e333e | 10000 | if (base == 0 && intel_crtc->cursor_base == 0) |
cda4b7d3 CW |
10001 | return; |
10002 | ||
5efb3e28 VS |
10003 | I915_WRITE(CURPOS(pipe), pos); |
10004 | ||
4398ad45 VS |
10005 | /* ILK+ do this automagically */ |
10006 | if (HAS_GMCH_DISPLAY(dev) && | |
8e7d688b | 10007 | crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) { |
9b4101be ML |
10008 | base += (cursor_state->crtc_h * |
10009 | cursor_state->crtc_w - 1) * 4; | |
4398ad45 VS |
10010 | } |
10011 | ||
8ac54669 | 10012 | if (IS_845G(dev) || IS_I865G(dev)) |
5efb3e28 VS |
10013 | i845_update_cursor(crtc, base); |
10014 | else | |
10015 | i9xx_update_cursor(crtc, base); | |
cda4b7d3 CW |
10016 | } |
10017 | ||
dc41c154 VS |
10018 | static bool cursor_size_ok(struct drm_device *dev, |
10019 | uint32_t width, uint32_t height) | |
10020 | { | |
10021 | if (width == 0 || height == 0) | |
10022 | return false; | |
10023 | ||
10024 | /* | |
10025 | * 845g/865g are special in that they are only limited by | |
10026 | * the width of their cursors, the height is arbitrary up to | |
10027 | * the precision of the register. Everything else requires | |
10028 | * square cursors, limited to a few power-of-two sizes. | |
10029 | */ | |
10030 | if (IS_845G(dev) || IS_I865G(dev)) { | |
10031 | if ((width & 63) != 0) | |
10032 | return false; | |
10033 | ||
10034 | if (width > (IS_845G(dev) ? 64 : 512)) | |
10035 | return false; | |
10036 | ||
10037 | if (height > 1023) | |
10038 | return false; | |
10039 | } else { | |
10040 | switch (width | height) { | |
10041 | case 256: | |
10042 | case 128: | |
10043 | if (IS_GEN2(dev)) | |
10044 | return false; | |
10045 | case 64: | |
10046 | break; | |
10047 | default: | |
10048 | return false; | |
10049 | } | |
10050 | } | |
10051 | ||
10052 | return true; | |
10053 | } | |
10054 | ||
79e53945 | 10055 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 10056 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 10057 | { |
7203425a | 10058 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 10059 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 10060 | |
7203425a | 10061 | for (i = start; i < end; i++) { |
79e53945 JB |
10062 | intel_crtc->lut_r[i] = red[i] >> 8; |
10063 | intel_crtc->lut_g[i] = green[i] >> 8; | |
10064 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
10065 | } | |
10066 | ||
10067 | intel_crtc_load_lut(crtc); | |
10068 | } | |
10069 | ||
79e53945 JB |
10070 | /* VESA 640x480x72Hz mode to set on the pipe */ |
10071 | static struct drm_display_mode load_detect_mode = { | |
10072 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
10073 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
10074 | }; | |
10075 | ||
a8bb6818 DV |
10076 | struct drm_framebuffer * |
10077 | __intel_framebuffer_create(struct drm_device *dev, | |
10078 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10079 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
10080 | { |
10081 | struct intel_framebuffer *intel_fb; | |
10082 | int ret; | |
10083 | ||
10084 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
10085 | if (!intel_fb) { | |
6ccb81f2 | 10086 | drm_gem_object_unreference(&obj->base); |
d2dff872 CW |
10087 | return ERR_PTR(-ENOMEM); |
10088 | } | |
10089 | ||
10090 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
10091 | if (ret) |
10092 | goto err; | |
d2dff872 CW |
10093 | |
10094 | return &intel_fb->base; | |
dd4916c5 | 10095 | err: |
6ccb81f2 | 10096 | drm_gem_object_unreference(&obj->base); |
dd4916c5 DV |
10097 | kfree(intel_fb); |
10098 | ||
10099 | return ERR_PTR(ret); | |
d2dff872 CW |
10100 | } |
10101 | ||
b5ea642a | 10102 | static struct drm_framebuffer * |
a8bb6818 DV |
10103 | intel_framebuffer_create(struct drm_device *dev, |
10104 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10105 | struct drm_i915_gem_object *obj) | |
10106 | { | |
10107 | struct drm_framebuffer *fb; | |
10108 | int ret; | |
10109 | ||
10110 | ret = i915_mutex_lock_interruptible(dev); | |
10111 | if (ret) | |
10112 | return ERR_PTR(ret); | |
10113 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
10114 | mutex_unlock(&dev->struct_mutex); | |
10115 | ||
10116 | return fb; | |
10117 | } | |
10118 | ||
d2dff872 CW |
10119 | static u32 |
10120 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
10121 | { | |
10122 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
10123 | return ALIGN(pitch, 64); | |
10124 | } | |
10125 | ||
10126 | static u32 | |
10127 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
10128 | { | |
10129 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 10130 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
10131 | } |
10132 | ||
10133 | static struct drm_framebuffer * | |
10134 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
10135 | struct drm_display_mode *mode, | |
10136 | int depth, int bpp) | |
10137 | { | |
10138 | struct drm_i915_gem_object *obj; | |
0fed39bd | 10139 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
10140 | |
10141 | obj = i915_gem_alloc_object(dev, | |
10142 | intel_framebuffer_size_for_mode(mode, bpp)); | |
10143 | if (obj == NULL) | |
10144 | return ERR_PTR(-ENOMEM); | |
10145 | ||
10146 | mode_cmd.width = mode->hdisplay; | |
10147 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
10148 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
10149 | bpp); | |
5ca0c34a | 10150 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
10151 | |
10152 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
10153 | } | |
10154 | ||
10155 | static struct drm_framebuffer * | |
10156 | mode_fits_in_fbdev(struct drm_device *dev, | |
10157 | struct drm_display_mode *mode) | |
10158 | { | |
0695726e | 10159 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
d2dff872 CW |
10160 | struct drm_i915_private *dev_priv = dev->dev_private; |
10161 | struct drm_i915_gem_object *obj; | |
10162 | struct drm_framebuffer *fb; | |
10163 | ||
4c0e5528 | 10164 | if (!dev_priv->fbdev) |
d2dff872 CW |
10165 | return NULL; |
10166 | ||
4c0e5528 | 10167 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
10168 | return NULL; |
10169 | ||
4c0e5528 DV |
10170 | obj = dev_priv->fbdev->fb->obj; |
10171 | BUG_ON(!obj); | |
10172 | ||
8bcd4553 | 10173 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
10174 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
10175 | fb->bits_per_pixel)) | |
d2dff872 CW |
10176 | return NULL; |
10177 | ||
01f2c773 | 10178 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
10179 | return NULL; |
10180 | ||
10181 | return fb; | |
4520f53a DV |
10182 | #else |
10183 | return NULL; | |
10184 | #endif | |
d2dff872 CW |
10185 | } |
10186 | ||
d3a40d1b ACO |
10187 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
10188 | struct drm_crtc *crtc, | |
10189 | struct drm_display_mode *mode, | |
10190 | struct drm_framebuffer *fb, | |
10191 | int x, int y) | |
10192 | { | |
10193 | struct drm_plane_state *plane_state; | |
10194 | int hdisplay, vdisplay; | |
10195 | int ret; | |
10196 | ||
10197 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
10198 | if (IS_ERR(plane_state)) | |
10199 | return PTR_ERR(plane_state); | |
10200 | ||
10201 | if (mode) | |
10202 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); | |
10203 | else | |
10204 | hdisplay = vdisplay = 0; | |
10205 | ||
10206 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
10207 | if (ret) | |
10208 | return ret; | |
10209 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
10210 | plane_state->crtc_x = 0; | |
10211 | plane_state->crtc_y = 0; | |
10212 | plane_state->crtc_w = hdisplay; | |
10213 | plane_state->crtc_h = vdisplay; | |
10214 | plane_state->src_x = x << 16; | |
10215 | plane_state->src_y = y << 16; | |
10216 | plane_state->src_w = hdisplay << 16; | |
10217 | plane_state->src_h = vdisplay << 16; | |
10218 | ||
10219 | return 0; | |
10220 | } | |
10221 | ||
d2434ab7 | 10222 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 10223 | struct drm_display_mode *mode, |
51fd371b RC |
10224 | struct intel_load_detect_pipe *old, |
10225 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
10226 | { |
10227 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
10228 | struct intel_encoder *intel_encoder = |
10229 | intel_attached_encoder(connector); | |
79e53945 | 10230 | struct drm_crtc *possible_crtc; |
4ef69c7a | 10231 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
10232 | struct drm_crtc *crtc = NULL; |
10233 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 10234 | struct drm_framebuffer *fb; |
51fd371b | 10235 | struct drm_mode_config *config = &dev->mode_config; |
83a57153 | 10236 | struct drm_atomic_state *state = NULL; |
944b0c76 | 10237 | struct drm_connector_state *connector_state; |
4be07317 | 10238 | struct intel_crtc_state *crtc_state; |
51fd371b | 10239 | int ret, i = -1; |
79e53945 | 10240 | |
d2dff872 | 10241 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10242 | connector->base.id, connector->name, |
8e329a03 | 10243 | encoder->base.id, encoder->name); |
d2dff872 | 10244 | |
51fd371b RC |
10245 | retry: |
10246 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
10247 | if (ret) | |
ad3c558f | 10248 | goto fail; |
6e9f798d | 10249 | |
79e53945 JB |
10250 | /* |
10251 | * Algorithm gets a little messy: | |
7a5e4805 | 10252 | * |
79e53945 JB |
10253 | * - if the connector already has an assigned crtc, use it (but make |
10254 | * sure it's on first) | |
7a5e4805 | 10255 | * |
79e53945 JB |
10256 | * - try to find the first unused crtc that can drive this connector, |
10257 | * and use that if we find one | |
79e53945 JB |
10258 | */ |
10259 | ||
10260 | /* See if we already have a CRTC for this connector */ | |
10261 | if (encoder->crtc) { | |
10262 | crtc = encoder->crtc; | |
8261b191 | 10263 | |
51fd371b | 10264 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 10265 | if (ret) |
ad3c558f | 10266 | goto fail; |
4d02e2de | 10267 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
51fd371b | 10268 | if (ret) |
ad3c558f | 10269 | goto fail; |
7b24056b | 10270 | |
24218aac | 10271 | old->dpms_mode = connector->dpms; |
8261b191 CW |
10272 | old->load_detect_temp = false; |
10273 | ||
10274 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
10275 | if (connector->dpms != DRM_MODE_DPMS_ON) |
10276 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 10277 | |
7173188d | 10278 | return true; |
79e53945 JB |
10279 | } |
10280 | ||
10281 | /* Find an unused one (if possible) */ | |
70e1e0ec | 10282 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
10283 | i++; |
10284 | if (!(encoder->possible_crtcs & (1 << i))) | |
10285 | continue; | |
83d65738 | 10286 | if (possible_crtc->state->enable) |
a459249c | 10287 | continue; |
a459249c VS |
10288 | |
10289 | crtc = possible_crtc; | |
10290 | break; | |
79e53945 JB |
10291 | } |
10292 | ||
10293 | /* | |
10294 | * If we didn't find an unused CRTC, don't use any. | |
10295 | */ | |
10296 | if (!crtc) { | |
7173188d | 10297 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
ad3c558f | 10298 | goto fail; |
79e53945 JB |
10299 | } |
10300 | ||
51fd371b RC |
10301 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
10302 | if (ret) | |
ad3c558f | 10303 | goto fail; |
4d02e2de DV |
10304 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
10305 | if (ret) | |
ad3c558f | 10306 | goto fail; |
79e53945 JB |
10307 | |
10308 | intel_crtc = to_intel_crtc(crtc); | |
24218aac | 10309 | old->dpms_mode = connector->dpms; |
8261b191 | 10310 | old->load_detect_temp = true; |
d2dff872 | 10311 | old->release_fb = NULL; |
79e53945 | 10312 | |
83a57153 ACO |
10313 | state = drm_atomic_state_alloc(dev); |
10314 | if (!state) | |
10315 | return false; | |
10316 | ||
10317 | state->acquire_ctx = ctx; | |
10318 | ||
944b0c76 ACO |
10319 | connector_state = drm_atomic_get_connector_state(state, connector); |
10320 | if (IS_ERR(connector_state)) { | |
10321 | ret = PTR_ERR(connector_state); | |
10322 | goto fail; | |
10323 | } | |
10324 | ||
10325 | connector_state->crtc = crtc; | |
10326 | connector_state->best_encoder = &intel_encoder->base; | |
10327 | ||
4be07317 ACO |
10328 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10329 | if (IS_ERR(crtc_state)) { | |
10330 | ret = PTR_ERR(crtc_state); | |
10331 | goto fail; | |
10332 | } | |
10333 | ||
49d6fa21 | 10334 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 10335 | |
6492711d CW |
10336 | if (!mode) |
10337 | mode = &load_detect_mode; | |
79e53945 | 10338 | |
d2dff872 CW |
10339 | /* We need a framebuffer large enough to accommodate all accesses |
10340 | * that the plane may generate whilst we perform load detection. | |
10341 | * We can not rely on the fbcon either being present (we get called | |
10342 | * during its initialisation to detect all boot displays, or it may | |
10343 | * not even exist) or that it is large enough to satisfy the | |
10344 | * requested mode. | |
10345 | */ | |
94352cf9 DV |
10346 | fb = mode_fits_in_fbdev(dev, mode); |
10347 | if (fb == NULL) { | |
d2dff872 | 10348 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
10349 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
10350 | old->release_fb = fb; | |
d2dff872 CW |
10351 | } else |
10352 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 10353 | if (IS_ERR(fb)) { |
d2dff872 | 10354 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 10355 | goto fail; |
79e53945 | 10356 | } |
79e53945 | 10357 | |
d3a40d1b ACO |
10358 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
10359 | if (ret) | |
10360 | goto fail; | |
10361 | ||
8c7b5ccb ACO |
10362 | drm_mode_copy(&crtc_state->base.mode, mode); |
10363 | ||
74c090b1 | 10364 | if (drm_atomic_commit(state)) { |
6492711d | 10365 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
10366 | if (old->release_fb) |
10367 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 10368 | goto fail; |
79e53945 | 10369 | } |
9128b040 | 10370 | crtc->primary->crtc = crtc; |
7173188d | 10371 | |
79e53945 | 10372 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 10373 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 10374 | return true; |
412b61d8 | 10375 | |
ad3c558f | 10376 | fail: |
e5d958ef ACO |
10377 | drm_atomic_state_free(state); |
10378 | state = NULL; | |
83a57153 | 10379 | |
51fd371b RC |
10380 | if (ret == -EDEADLK) { |
10381 | drm_modeset_backoff(ctx); | |
10382 | goto retry; | |
10383 | } | |
10384 | ||
412b61d8 | 10385 | return false; |
79e53945 JB |
10386 | } |
10387 | ||
d2434ab7 | 10388 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
10389 | struct intel_load_detect_pipe *old, |
10390 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 10391 | { |
83a57153 | 10392 | struct drm_device *dev = connector->dev; |
d2434ab7 DV |
10393 | struct intel_encoder *intel_encoder = |
10394 | intel_attached_encoder(connector); | |
4ef69c7a | 10395 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 10396 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 10397 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
83a57153 | 10398 | struct drm_atomic_state *state; |
944b0c76 | 10399 | struct drm_connector_state *connector_state; |
4be07317 | 10400 | struct intel_crtc_state *crtc_state; |
d3a40d1b | 10401 | int ret; |
79e53945 | 10402 | |
d2dff872 | 10403 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10404 | connector->base.id, connector->name, |
8e329a03 | 10405 | encoder->base.id, encoder->name); |
d2dff872 | 10406 | |
8261b191 | 10407 | if (old->load_detect_temp) { |
83a57153 | 10408 | state = drm_atomic_state_alloc(dev); |
944b0c76 ACO |
10409 | if (!state) |
10410 | goto fail; | |
83a57153 ACO |
10411 | |
10412 | state->acquire_ctx = ctx; | |
10413 | ||
944b0c76 ACO |
10414 | connector_state = drm_atomic_get_connector_state(state, connector); |
10415 | if (IS_ERR(connector_state)) | |
10416 | goto fail; | |
10417 | ||
4be07317 ACO |
10418 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10419 | if (IS_ERR(crtc_state)) | |
10420 | goto fail; | |
10421 | ||
944b0c76 ACO |
10422 | connector_state->best_encoder = NULL; |
10423 | connector_state->crtc = NULL; | |
10424 | ||
49d6fa21 | 10425 | crtc_state->base.enable = crtc_state->base.active = false; |
4be07317 | 10426 | |
d3a40d1b ACO |
10427 | ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL, |
10428 | 0, 0); | |
10429 | if (ret) | |
10430 | goto fail; | |
10431 | ||
74c090b1 | 10432 | ret = drm_atomic_commit(state); |
2bfb4627 ACO |
10433 | if (ret) |
10434 | goto fail; | |
d2dff872 | 10435 | |
36206361 DV |
10436 | if (old->release_fb) { |
10437 | drm_framebuffer_unregister_private(old->release_fb); | |
10438 | drm_framebuffer_unreference(old->release_fb); | |
10439 | } | |
d2dff872 | 10440 | |
0622a53c | 10441 | return; |
79e53945 JB |
10442 | } |
10443 | ||
c751ce4f | 10444 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
10445 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
10446 | connector->funcs->dpms(connector, old->dpms_mode); | |
944b0c76 ACO |
10447 | |
10448 | return; | |
10449 | fail: | |
10450 | DRM_DEBUG_KMS("Couldn't release load detect pipe.\n"); | |
10451 | drm_atomic_state_free(state); | |
79e53945 JB |
10452 | } |
10453 | ||
da4a1efa | 10454 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 10455 | const struct intel_crtc_state *pipe_config) |
da4a1efa VS |
10456 | { |
10457 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10458 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
10459 | ||
10460 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 10461 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
10462 | else if (HAS_PCH_SPLIT(dev)) |
10463 | return 120000; | |
10464 | else if (!IS_GEN2(dev)) | |
10465 | return 96000; | |
10466 | else | |
10467 | return 48000; | |
10468 | } | |
10469 | ||
79e53945 | 10470 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 10471 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 10472 | struct intel_crtc_state *pipe_config) |
79e53945 | 10473 | { |
f1f644dc | 10474 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 10475 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 10476 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 10477 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
10478 | u32 fp; |
10479 | intel_clock_t clock; | |
dccbea3b | 10480 | int port_clock; |
da4a1efa | 10481 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
10482 | |
10483 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 10484 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 10485 | else |
293623f7 | 10486 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
10487 | |
10488 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
10489 | if (IS_PINEVIEW(dev)) { |
10490 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
10491 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
10492 | } else { |
10493 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
10494 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
10495 | } | |
10496 | ||
a6c45cf0 | 10497 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
10498 | if (IS_PINEVIEW(dev)) |
10499 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
10500 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
10501 | else |
10502 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
10503 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
10504 | ||
10505 | switch (dpll & DPLL_MODE_MASK) { | |
10506 | case DPLLB_MODE_DAC_SERIAL: | |
10507 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
10508 | 5 : 10; | |
10509 | break; | |
10510 | case DPLLB_MODE_LVDS: | |
10511 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
10512 | 7 : 14; | |
10513 | break; | |
10514 | default: | |
28c97730 | 10515 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 10516 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 10517 | return; |
79e53945 JB |
10518 | } |
10519 | ||
ac58c3f0 | 10520 | if (IS_PINEVIEW(dev)) |
dccbea3b | 10521 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 10522 | else |
dccbea3b | 10523 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 10524 | } else { |
0fb58223 | 10525 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 10526 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
10527 | |
10528 | if (is_lvds) { | |
10529 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
10530 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
10531 | |
10532 | if (lvds & LVDS_CLKB_POWER_UP) | |
10533 | clock.p2 = 7; | |
10534 | else | |
10535 | clock.p2 = 14; | |
79e53945 JB |
10536 | } else { |
10537 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
10538 | clock.p1 = 2; | |
10539 | else { | |
10540 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
10541 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
10542 | } | |
10543 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
10544 | clock.p2 = 4; | |
10545 | else | |
10546 | clock.p2 = 2; | |
79e53945 | 10547 | } |
da4a1efa | 10548 | |
dccbea3b | 10549 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
10550 | } |
10551 | ||
18442d08 VS |
10552 | /* |
10553 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 10554 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
10555 | * encoder's get_config() function. |
10556 | */ | |
dccbea3b | 10557 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
10558 | } |
10559 | ||
6878da05 VS |
10560 | int intel_dotclock_calculate(int link_freq, |
10561 | const struct intel_link_m_n *m_n) | |
f1f644dc | 10562 | { |
f1f644dc JB |
10563 | /* |
10564 | * The calculation for the data clock is: | |
1041a02f | 10565 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 10566 | * But we want to avoid losing precison if possible, so: |
1041a02f | 10567 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
10568 | * |
10569 | * and the link clock is simpler: | |
1041a02f | 10570 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
10571 | */ |
10572 | ||
6878da05 VS |
10573 | if (!m_n->link_n) |
10574 | return 0; | |
f1f644dc | 10575 | |
6878da05 VS |
10576 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
10577 | } | |
f1f644dc | 10578 | |
18442d08 | 10579 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 10580 | struct intel_crtc_state *pipe_config) |
6878da05 VS |
10581 | { |
10582 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 10583 | |
18442d08 VS |
10584 | /* read out port_clock from the DPLL */ |
10585 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 10586 | |
f1f644dc | 10587 | /* |
18442d08 | 10588 | * This value does not include pixel_multiplier. |
241bfc38 | 10589 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
10590 | * agree once we know their relationship in the encoder's |
10591 | * get_config() function. | |
79e53945 | 10592 | */ |
2d112de7 | 10593 | pipe_config->base.adjusted_mode.crtc_clock = |
18442d08 VS |
10594 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
10595 | &pipe_config->fdi_m_n); | |
79e53945 JB |
10596 | } |
10597 | ||
10598 | /** Returns the currently programmed mode of the given pipe. */ | |
10599 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
10600 | struct drm_crtc *crtc) | |
10601 | { | |
548f245b | 10602 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 10603 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 10604 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 10605 | struct drm_display_mode *mode; |
5cec258b | 10606 | struct intel_crtc_state pipe_config; |
fe2b8f9d PZ |
10607 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
10608 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
10609 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
10610 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 10611 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
10612 | |
10613 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
10614 | if (!mode) | |
10615 | return NULL; | |
10616 | ||
f1f644dc JB |
10617 | /* |
10618 | * Construct a pipe_config sufficient for getting the clock info | |
10619 | * back out of crtc_clock_get. | |
10620 | * | |
10621 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
10622 | * to use a real value here instead. | |
10623 | */ | |
293623f7 | 10624 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 10625 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
10626 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
10627 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
10628 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
10629 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
10630 | ||
773ae034 | 10631 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
10632 | mode->hdisplay = (htot & 0xffff) + 1; |
10633 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
10634 | mode->hsync_start = (hsync & 0xffff) + 1; | |
10635 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
10636 | mode->vdisplay = (vtot & 0xffff) + 1; | |
10637 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
10638 | mode->vsync_start = (vsync & 0xffff) + 1; | |
10639 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
10640 | ||
10641 | drm_mode_set_name(mode); | |
79e53945 JB |
10642 | |
10643 | return mode; | |
10644 | } | |
10645 | ||
f047e395 CW |
10646 | void intel_mark_busy(struct drm_device *dev) |
10647 | { | |
c67a470b PZ |
10648 | struct drm_i915_private *dev_priv = dev->dev_private; |
10649 | ||
f62a0076 CW |
10650 | if (dev_priv->mm.busy) |
10651 | return; | |
10652 | ||
43694d69 | 10653 | intel_runtime_pm_get(dev_priv); |
c67a470b | 10654 | i915_update_gfx_val(dev_priv); |
43cf3bf0 CW |
10655 | if (INTEL_INFO(dev)->gen >= 6) |
10656 | gen6_rps_busy(dev_priv); | |
f62a0076 | 10657 | dev_priv->mm.busy = true; |
f047e395 CW |
10658 | } |
10659 | ||
10660 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 10661 | { |
c67a470b | 10662 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 10663 | |
f62a0076 CW |
10664 | if (!dev_priv->mm.busy) |
10665 | return; | |
10666 | ||
10667 | dev_priv->mm.busy = false; | |
10668 | ||
3d13ef2e | 10669 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 10670 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 | 10671 | |
43694d69 | 10672 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
10673 | } |
10674 | ||
79e53945 JB |
10675 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
10676 | { | |
10677 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
10678 | struct drm_device *dev = crtc->dev; |
10679 | struct intel_unpin_work *work; | |
67e77c5a | 10680 | |
5e2d7afc | 10681 | spin_lock_irq(&dev->event_lock); |
67e77c5a DV |
10682 | work = intel_crtc->unpin_work; |
10683 | intel_crtc->unpin_work = NULL; | |
5e2d7afc | 10684 | spin_unlock_irq(&dev->event_lock); |
67e77c5a DV |
10685 | |
10686 | if (work) { | |
10687 | cancel_work_sync(&work->work); | |
10688 | kfree(work); | |
10689 | } | |
79e53945 JB |
10690 | |
10691 | drm_crtc_cleanup(crtc); | |
67e77c5a | 10692 | |
79e53945 JB |
10693 | kfree(intel_crtc); |
10694 | } | |
10695 | ||
6b95a207 KH |
10696 | static void intel_unpin_work_fn(struct work_struct *__work) |
10697 | { | |
10698 | struct intel_unpin_work *work = | |
10699 | container_of(__work, struct intel_unpin_work, work); | |
a9ff8714 VS |
10700 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); |
10701 | struct drm_device *dev = crtc->base.dev; | |
10702 | struct drm_plane *primary = crtc->base.primary; | |
6b95a207 | 10703 | |
b4a98e57 | 10704 | mutex_lock(&dev->struct_mutex); |
a9ff8714 | 10705 | intel_unpin_fb_obj(work->old_fb, primary->state); |
05394f39 | 10706 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
d9e86c0e | 10707 | |
f06cc1b9 | 10708 | if (work->flip_queued_req) |
146d84f0 | 10709 | i915_gem_request_assign(&work->flip_queued_req, NULL); |
b4a98e57 CW |
10710 | mutex_unlock(&dev->struct_mutex); |
10711 | ||
a9ff8714 | 10712 | intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit); |
89ed88ba | 10713 | drm_framebuffer_unreference(work->old_fb); |
f99d7069 | 10714 | |
a9ff8714 VS |
10715 | BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); |
10716 | atomic_dec(&crtc->unpin_work_count); | |
b4a98e57 | 10717 | |
6b95a207 KH |
10718 | kfree(work); |
10719 | } | |
10720 | ||
1afe3e9d | 10721 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 10722 | struct drm_crtc *crtc) |
6b95a207 | 10723 | { |
6b95a207 KH |
10724 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10725 | struct intel_unpin_work *work; | |
6b95a207 KH |
10726 | unsigned long flags; |
10727 | ||
10728 | /* Ignore early vblank irqs */ | |
10729 | if (intel_crtc == NULL) | |
10730 | return; | |
10731 | ||
f326038a DV |
10732 | /* |
10733 | * This is called both by irq handlers and the reset code (to complete | |
10734 | * lost pageflips) so needs the full irqsave spinlocks. | |
10735 | */ | |
6b95a207 KH |
10736 | spin_lock_irqsave(&dev->event_lock, flags); |
10737 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
10738 | |
10739 | /* Ensure we don't miss a work->pending update ... */ | |
10740 | smp_rmb(); | |
10741 | ||
10742 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
10743 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10744 | return; | |
10745 | } | |
10746 | ||
d6bbafa1 | 10747 | page_flip_completed(intel_crtc); |
0af7e4df | 10748 | |
6b95a207 | 10749 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6b95a207 KH |
10750 | } |
10751 | ||
1afe3e9d JB |
10752 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
10753 | { | |
fbee40df | 10754 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10755 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
10756 | ||
49b14a5c | 10757 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10758 | } |
10759 | ||
10760 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
10761 | { | |
fbee40df | 10762 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10763 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
10764 | ||
49b14a5c | 10765 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10766 | } |
10767 | ||
75f7f3ec VS |
10768 | /* Is 'a' after or equal to 'b'? */ |
10769 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
10770 | { | |
10771 | return !((a - b) & 0x80000000); | |
10772 | } | |
10773 | ||
10774 | static bool page_flip_finished(struct intel_crtc *crtc) | |
10775 | { | |
10776 | struct drm_device *dev = crtc->base.dev; | |
10777 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10778 | ||
bdfa7542 VS |
10779 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
10780 | crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
10781 | return true; | |
10782 | ||
75f7f3ec VS |
10783 | /* |
10784 | * The relevant registers doen't exist on pre-ctg. | |
10785 | * As the flip done interrupt doesn't trigger for mmio | |
10786 | * flips on gmch platforms, a flip count check isn't | |
10787 | * really needed there. But since ctg has the registers, | |
10788 | * include it in the check anyway. | |
10789 | */ | |
10790 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
10791 | return true; | |
10792 | ||
10793 | /* | |
10794 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
10795 | * used the same base address. In that case the mmio flip might | |
10796 | * have completed, but the CS hasn't even executed the flip yet. | |
10797 | * | |
10798 | * A flip count check isn't enough as the CS might have updated | |
10799 | * the base address just after start of vblank, but before we | |
10800 | * managed to process the interrupt. This means we'd complete the | |
10801 | * CS flip too soon. | |
10802 | * | |
10803 | * Combining both checks should get us a good enough result. It may | |
10804 | * still happen that the CS flip has been executed, but has not | |
10805 | * yet actually completed. But in case the base address is the same | |
10806 | * anyway, we don't really care. | |
10807 | */ | |
10808 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
10809 | crtc->unpin_work->gtt_offset && | |
10810 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)), | |
10811 | crtc->unpin_work->flip_count); | |
10812 | } | |
10813 | ||
6b95a207 KH |
10814 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
10815 | { | |
fbee40df | 10816 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
10817 | struct intel_crtc *intel_crtc = |
10818 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
10819 | unsigned long flags; | |
10820 | ||
f326038a DV |
10821 | |
10822 | /* | |
10823 | * This is called both by irq handlers and the reset code (to complete | |
10824 | * lost pageflips) so needs the full irqsave spinlocks. | |
10825 | * | |
10826 | * NB: An MMIO update of the plane base pointer will also | |
e7d841ca CW |
10827 | * generate a page-flip completion irq, i.e. every modeset |
10828 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
10829 | */ | |
6b95a207 | 10830 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 10831 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 10832 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
10833 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10834 | } | |
10835 | ||
eba905b2 | 10836 | static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
e7d841ca CW |
10837 | { |
10838 | /* Ensure that the work item is consistent when activating it ... */ | |
10839 | smp_wmb(); | |
10840 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
10841 | /* and that it is marked active as soon as the irq could fire. */ | |
10842 | smp_wmb(); | |
10843 | } | |
10844 | ||
8c9f3aaf JB |
10845 | static int intel_gen2_queue_flip(struct drm_device *dev, |
10846 | struct drm_crtc *crtc, | |
10847 | struct drm_framebuffer *fb, | |
ed8d1975 | 10848 | struct drm_i915_gem_object *obj, |
6258fbe2 | 10849 | struct drm_i915_gem_request *req, |
ed8d1975 | 10850 | uint32_t flags) |
8c9f3aaf | 10851 | { |
6258fbe2 | 10852 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf | 10853 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
10854 | u32 flip_mask; |
10855 | int ret; | |
10856 | ||
5fb9de1a | 10857 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 10858 | if (ret) |
4fa62c89 | 10859 | return ret; |
8c9f3aaf JB |
10860 | |
10861 | /* Can't queue multiple flips, so wait for the previous | |
10862 | * one to finish before executing the next. | |
10863 | */ | |
10864 | if (intel_crtc->plane) | |
10865 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
10866 | else | |
10867 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
10868 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
10869 | intel_ring_emit(ring, MI_NOOP); | |
10870 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
10871 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10872 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 10873 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 | 10874 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
10875 | |
10876 | intel_mark_page_flip_active(intel_crtc); | |
83d4092b | 10877 | return 0; |
8c9f3aaf JB |
10878 | } |
10879 | ||
10880 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
10881 | struct drm_crtc *crtc, | |
10882 | struct drm_framebuffer *fb, | |
ed8d1975 | 10883 | struct drm_i915_gem_object *obj, |
6258fbe2 | 10884 | struct drm_i915_gem_request *req, |
ed8d1975 | 10885 | uint32_t flags) |
8c9f3aaf | 10886 | { |
6258fbe2 | 10887 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf | 10888 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
10889 | u32 flip_mask; |
10890 | int ret; | |
10891 | ||
5fb9de1a | 10892 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 10893 | if (ret) |
4fa62c89 | 10894 | return ret; |
8c9f3aaf JB |
10895 | |
10896 | if (intel_crtc->plane) | |
10897 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
10898 | else | |
10899 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
10900 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
10901 | intel_ring_emit(ring, MI_NOOP); | |
10902 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
10903 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10904 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 10905 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 DV |
10906 | intel_ring_emit(ring, MI_NOOP); |
10907 | ||
e7d841ca | 10908 | intel_mark_page_flip_active(intel_crtc); |
83d4092b | 10909 | return 0; |
8c9f3aaf JB |
10910 | } |
10911 | ||
10912 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
10913 | struct drm_crtc *crtc, | |
10914 | struct drm_framebuffer *fb, | |
ed8d1975 | 10915 | struct drm_i915_gem_object *obj, |
6258fbe2 | 10916 | struct drm_i915_gem_request *req, |
ed8d1975 | 10917 | uint32_t flags) |
8c9f3aaf | 10918 | { |
6258fbe2 | 10919 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf JB |
10920 | struct drm_i915_private *dev_priv = dev->dev_private; |
10921 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10922 | uint32_t pf, pipesrc; | |
10923 | int ret; | |
10924 | ||
5fb9de1a | 10925 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 10926 | if (ret) |
4fa62c89 | 10927 | return ret; |
8c9f3aaf JB |
10928 | |
10929 | /* i965+ uses the linear or tiled offsets from the | |
10930 | * Display Registers (which do not change across a page-flip) | |
10931 | * so we need only reprogram the base address. | |
10932 | */ | |
6d90c952 DV |
10933 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
10934 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10935 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 10936 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
c2c75131 | 10937 | obj->tiling_mode); |
8c9f3aaf JB |
10938 | |
10939 | /* XXX Enabling the panel-fitter across page-flip is so far | |
10940 | * untested on non-native modes, so ignore it for now. | |
10941 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
10942 | */ | |
10943 | pf = 0; | |
10944 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 10945 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
10946 | |
10947 | intel_mark_page_flip_active(intel_crtc); | |
83d4092b | 10948 | return 0; |
8c9f3aaf JB |
10949 | } |
10950 | ||
10951 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
10952 | struct drm_crtc *crtc, | |
10953 | struct drm_framebuffer *fb, | |
ed8d1975 | 10954 | struct drm_i915_gem_object *obj, |
6258fbe2 | 10955 | struct drm_i915_gem_request *req, |
ed8d1975 | 10956 | uint32_t flags) |
8c9f3aaf | 10957 | { |
6258fbe2 | 10958 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf JB |
10959 | struct drm_i915_private *dev_priv = dev->dev_private; |
10960 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10961 | uint32_t pf, pipesrc; | |
10962 | int ret; | |
10963 | ||
5fb9de1a | 10964 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 10965 | if (ret) |
4fa62c89 | 10966 | return ret; |
8c9f3aaf | 10967 | |
6d90c952 DV |
10968 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
10969 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10970 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
75f7f3ec | 10971 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8c9f3aaf | 10972 | |
dc257cf1 DV |
10973 | /* Contrary to the suggestions in the documentation, |
10974 | * "Enable Panel Fitter" does not seem to be required when page | |
10975 | * flipping with a non-native mode, and worse causes a normal | |
10976 | * modeset to fail. | |
10977 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
10978 | */ | |
10979 | pf = 0; | |
8c9f3aaf | 10980 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 10981 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
10982 | |
10983 | intel_mark_page_flip_active(intel_crtc); | |
83d4092b | 10984 | return 0; |
8c9f3aaf JB |
10985 | } |
10986 | ||
7c9017e5 JB |
10987 | static int intel_gen7_queue_flip(struct drm_device *dev, |
10988 | struct drm_crtc *crtc, | |
10989 | struct drm_framebuffer *fb, | |
ed8d1975 | 10990 | struct drm_i915_gem_object *obj, |
6258fbe2 | 10991 | struct drm_i915_gem_request *req, |
ed8d1975 | 10992 | uint32_t flags) |
7c9017e5 | 10993 | { |
6258fbe2 | 10994 | struct intel_engine_cs *ring = req->ring; |
7c9017e5 | 10995 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 10996 | uint32_t plane_bit = 0; |
ffe74d75 CW |
10997 | int len, ret; |
10998 | ||
eba905b2 | 10999 | switch (intel_crtc->plane) { |
cb05d8de DV |
11000 | case PLANE_A: |
11001 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
11002 | break; | |
11003 | case PLANE_B: | |
11004 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
11005 | break; | |
11006 | case PLANE_C: | |
11007 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
11008 | break; | |
11009 | default: | |
11010 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 11011 | return -ENODEV; |
cb05d8de DV |
11012 | } |
11013 | ||
ffe74d75 | 11014 | len = 4; |
f476828a | 11015 | if (ring->id == RCS) { |
ffe74d75 | 11016 | len += 6; |
f476828a DL |
11017 | /* |
11018 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
11019 | * 48bits addresses, and we need a NOOP for the batch size to | |
11020 | * stay even. | |
11021 | */ | |
11022 | if (IS_GEN8(dev)) | |
11023 | len += 2; | |
11024 | } | |
ffe74d75 | 11025 | |
f66fab8e VS |
11026 | /* |
11027 | * BSpec MI_DISPLAY_FLIP for IVB: | |
11028 | * "The full packet must be contained within the same cache line." | |
11029 | * | |
11030 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
11031 | * cacheline, if we ever start emitting more commands before | |
11032 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
11033 | * then do the cacheline alignment, and finally emit the | |
11034 | * MI_DISPLAY_FLIP. | |
11035 | */ | |
bba09b12 | 11036 | ret = intel_ring_cacheline_align(req); |
f66fab8e | 11037 | if (ret) |
4fa62c89 | 11038 | return ret; |
f66fab8e | 11039 | |
5fb9de1a | 11040 | ret = intel_ring_begin(req, len); |
7c9017e5 | 11041 | if (ret) |
4fa62c89 | 11042 | return ret; |
7c9017e5 | 11043 | |
ffe74d75 CW |
11044 | /* Unmask the flip-done completion message. Note that the bspec says that |
11045 | * we should do this for both the BCS and RCS, and that we must not unmask | |
11046 | * more than one flip event at any time (or ensure that one flip message | |
11047 | * can be sent by waiting for flip-done prior to queueing new flips). | |
11048 | * Experimentation says that BCS works despite DERRMR masking all | |
11049 | * flip-done completion events and that unmasking all planes at once | |
11050 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
11051 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
11052 | */ | |
11053 | if (ring->id == RCS) { | |
11054 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
11055 | intel_ring_emit(ring, DERRMR); | |
11056 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
11057 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
11058 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a | 11059 | if (IS_GEN8(dev)) |
f1afe24f | 11060 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 | |
f476828a DL |
11061 | MI_SRM_LRM_GLOBAL_GTT); |
11062 | else | |
f1afe24f | 11063 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM | |
f476828a | 11064 | MI_SRM_LRM_GLOBAL_GTT); |
ffe74d75 CW |
11065 | intel_ring_emit(ring, DERRMR); |
11066 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
f476828a DL |
11067 | if (IS_GEN8(dev)) { |
11068 | intel_ring_emit(ring, 0); | |
11069 | intel_ring_emit(ring, MI_NOOP); | |
11070 | } | |
ffe74d75 CW |
11071 | } |
11072 | ||
cb05d8de | 11073 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 11074 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
75f7f3ec | 11075 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
7c9017e5 | 11076 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
11077 | |
11078 | intel_mark_page_flip_active(intel_crtc); | |
83d4092b | 11079 | return 0; |
7c9017e5 JB |
11080 | } |
11081 | ||
84c33a64 SG |
11082 | static bool use_mmio_flip(struct intel_engine_cs *ring, |
11083 | struct drm_i915_gem_object *obj) | |
11084 | { | |
11085 | /* | |
11086 | * This is not being used for older platforms, because | |
11087 | * non-availability of flip done interrupt forces us to use | |
11088 | * CS flips. Older platforms derive flip done using some clever | |
11089 | * tricks involving the flip_pending status bits and vblank irqs. | |
11090 | * So using MMIO flips there would disrupt this mechanism. | |
11091 | */ | |
11092 | ||
8e09bf83 CW |
11093 | if (ring == NULL) |
11094 | return true; | |
11095 | ||
84c33a64 SG |
11096 | if (INTEL_INFO(ring->dev)->gen < 5) |
11097 | return false; | |
11098 | ||
11099 | if (i915.use_mmio_flip < 0) | |
11100 | return false; | |
11101 | else if (i915.use_mmio_flip > 0) | |
11102 | return true; | |
14bf993e OM |
11103 | else if (i915.enable_execlists) |
11104 | return true; | |
84c33a64 | 11105 | else |
b4716185 | 11106 | return ring != i915_gem_request_get_ring(obj->last_write_req); |
84c33a64 SG |
11107 | } |
11108 | ||
ff944564 DL |
11109 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc) |
11110 | { | |
11111 | struct drm_device *dev = intel_crtc->base.dev; | |
11112 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11113 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; | |
ff944564 DL |
11114 | const enum pipe pipe = intel_crtc->pipe; |
11115 | u32 ctl, stride; | |
11116 | ||
11117 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
11118 | ctl &= ~PLANE_CTL_TILED_MASK; | |
2ebef630 TU |
11119 | switch (fb->modifier[0]) { |
11120 | case DRM_FORMAT_MOD_NONE: | |
11121 | break; | |
11122 | case I915_FORMAT_MOD_X_TILED: | |
ff944564 | 11123 | ctl |= PLANE_CTL_TILED_X; |
2ebef630 TU |
11124 | break; |
11125 | case I915_FORMAT_MOD_Y_TILED: | |
11126 | ctl |= PLANE_CTL_TILED_Y; | |
11127 | break; | |
11128 | case I915_FORMAT_MOD_Yf_TILED: | |
11129 | ctl |= PLANE_CTL_TILED_YF; | |
11130 | break; | |
11131 | default: | |
11132 | MISSING_CASE(fb->modifier[0]); | |
11133 | } | |
ff944564 DL |
11134 | |
11135 | /* | |
11136 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
11137 | * linear buffers or in number of tiles for tiled buffers. | |
11138 | */ | |
2ebef630 TU |
11139 | stride = fb->pitches[0] / |
11140 | intel_fb_stride_alignment(dev, fb->modifier[0], | |
11141 | fb->pixel_format); | |
ff944564 DL |
11142 | |
11143 | /* | |
11144 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
11145 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
11146 | */ | |
11147 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
11148 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
11149 | ||
11150 | I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset); | |
11151 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
11152 | } | |
11153 | ||
11154 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc) | |
84c33a64 SG |
11155 | { |
11156 | struct drm_device *dev = intel_crtc->base.dev; | |
11157 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11158 | struct intel_framebuffer *intel_fb = | |
11159 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
11160 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
11161 | u32 dspcntr; | |
11162 | u32 reg; | |
11163 | ||
84c33a64 SG |
11164 | reg = DSPCNTR(intel_crtc->plane); |
11165 | dspcntr = I915_READ(reg); | |
11166 | ||
c5d97472 DL |
11167 | if (obj->tiling_mode != I915_TILING_NONE) |
11168 | dspcntr |= DISPPLANE_TILED; | |
11169 | else | |
11170 | dspcntr &= ~DISPPLANE_TILED; | |
11171 | ||
84c33a64 SG |
11172 | I915_WRITE(reg, dspcntr); |
11173 | ||
11174 | I915_WRITE(DSPSURF(intel_crtc->plane), | |
11175 | intel_crtc->unpin_work->gtt_offset); | |
11176 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
84c33a64 | 11177 | |
ff944564 DL |
11178 | } |
11179 | ||
11180 | /* | |
11181 | * XXX: This is the temporary way to update the plane registers until we get | |
11182 | * around to using the usual plane update functions for MMIO flips | |
11183 | */ | |
11184 | static void intel_do_mmio_flip(struct intel_crtc *intel_crtc) | |
11185 | { | |
11186 | struct drm_device *dev = intel_crtc->base.dev; | |
ff944564 DL |
11187 | |
11188 | intel_mark_page_flip_active(intel_crtc); | |
11189 | ||
34e0adbb | 11190 | intel_pipe_update_start(intel_crtc); |
ff944564 DL |
11191 | |
11192 | if (INTEL_INFO(dev)->gen >= 9) | |
11193 | skl_do_mmio_flip(intel_crtc); | |
11194 | else | |
11195 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
11196 | ilk_do_mmio_flip(intel_crtc); | |
11197 | ||
34e0adbb | 11198 | intel_pipe_update_end(intel_crtc); |
84c33a64 SG |
11199 | } |
11200 | ||
9362c7c5 | 11201 | static void intel_mmio_flip_work_func(struct work_struct *work) |
84c33a64 | 11202 | { |
b2cfe0ab CW |
11203 | struct intel_mmio_flip *mmio_flip = |
11204 | container_of(work, struct intel_mmio_flip, work); | |
84c33a64 | 11205 | |
eed29a5b DV |
11206 | if (mmio_flip->req) |
11207 | WARN_ON(__i915_wait_request(mmio_flip->req, | |
b2cfe0ab | 11208 | mmio_flip->crtc->reset_counter, |
bcafc4e3 CW |
11209 | false, NULL, |
11210 | &mmio_flip->i915->rps.mmioflips)); | |
84c33a64 | 11211 | |
b2cfe0ab CW |
11212 | intel_do_mmio_flip(mmio_flip->crtc); |
11213 | ||
eed29a5b | 11214 | i915_gem_request_unreference__unlocked(mmio_flip->req); |
b2cfe0ab | 11215 | kfree(mmio_flip); |
84c33a64 SG |
11216 | } |
11217 | ||
11218 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
11219 | struct drm_crtc *crtc, | |
11220 | struct drm_framebuffer *fb, | |
11221 | struct drm_i915_gem_object *obj, | |
11222 | struct intel_engine_cs *ring, | |
11223 | uint32_t flags) | |
11224 | { | |
b2cfe0ab CW |
11225 | struct intel_mmio_flip *mmio_flip; |
11226 | ||
11227 | mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL); | |
11228 | if (mmio_flip == NULL) | |
11229 | return -ENOMEM; | |
84c33a64 | 11230 | |
bcafc4e3 | 11231 | mmio_flip->i915 = to_i915(dev); |
eed29a5b | 11232 | mmio_flip->req = i915_gem_request_reference(obj->last_write_req); |
b2cfe0ab | 11233 | mmio_flip->crtc = to_intel_crtc(crtc); |
536f5b5e | 11234 | |
b2cfe0ab CW |
11235 | INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func); |
11236 | schedule_work(&mmio_flip->work); | |
84c33a64 | 11237 | |
84c33a64 SG |
11238 | return 0; |
11239 | } | |
11240 | ||
8c9f3aaf JB |
11241 | static int intel_default_queue_flip(struct drm_device *dev, |
11242 | struct drm_crtc *crtc, | |
11243 | struct drm_framebuffer *fb, | |
ed8d1975 | 11244 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11245 | struct drm_i915_gem_request *req, |
ed8d1975 | 11246 | uint32_t flags) |
8c9f3aaf JB |
11247 | { |
11248 | return -ENODEV; | |
11249 | } | |
11250 | ||
d6bbafa1 CW |
11251 | static bool __intel_pageflip_stall_check(struct drm_device *dev, |
11252 | struct drm_crtc *crtc) | |
11253 | { | |
11254 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11255 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11256 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
11257 | u32 addr; | |
11258 | ||
11259 | if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) | |
11260 | return true; | |
11261 | ||
908565c2 CW |
11262 | if (atomic_read(&work->pending) < INTEL_FLIP_PENDING) |
11263 | return false; | |
11264 | ||
d6bbafa1 CW |
11265 | if (!work->enable_stall_check) |
11266 | return false; | |
11267 | ||
11268 | if (work->flip_ready_vblank == 0) { | |
3a8a946e DV |
11269 | if (work->flip_queued_req && |
11270 | !i915_gem_request_completed(work->flip_queued_req, true)) | |
d6bbafa1 CW |
11271 | return false; |
11272 | ||
1e3feefd | 11273 | work->flip_ready_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 CW |
11274 | } |
11275 | ||
1e3feefd | 11276 | if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) |
d6bbafa1 CW |
11277 | return false; |
11278 | ||
11279 | /* Potential stall - if we see that the flip has happened, | |
11280 | * assume a missed interrupt. */ | |
11281 | if (INTEL_INFO(dev)->gen >= 4) | |
11282 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
11283 | else | |
11284 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
11285 | ||
11286 | /* There is a potential issue here with a false positive after a flip | |
11287 | * to the same address. We could address this by checking for a | |
11288 | * non-incrementing frame counter. | |
11289 | */ | |
11290 | return addr == work->gtt_offset; | |
11291 | } | |
11292 | ||
11293 | void intel_check_page_flip(struct drm_device *dev, int pipe) | |
11294 | { | |
11295 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11296 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
11297 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6ad790c0 | 11298 | struct intel_unpin_work *work; |
f326038a | 11299 | |
6c51d46f | 11300 | WARN_ON(!in_interrupt()); |
d6bbafa1 CW |
11301 | |
11302 | if (crtc == NULL) | |
11303 | return; | |
11304 | ||
f326038a | 11305 | spin_lock(&dev->event_lock); |
6ad790c0 CW |
11306 | work = intel_crtc->unpin_work; |
11307 | if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) { | |
d6bbafa1 | 11308 | WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", |
6ad790c0 | 11309 | work->flip_queued_vblank, drm_vblank_count(dev, pipe)); |
d6bbafa1 | 11310 | page_flip_completed(intel_crtc); |
6ad790c0 | 11311 | work = NULL; |
d6bbafa1 | 11312 | } |
6ad790c0 CW |
11313 | if (work != NULL && |
11314 | drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1) | |
11315 | intel_queue_rps_boost_for_request(dev, work->flip_queued_req); | |
f326038a | 11316 | spin_unlock(&dev->event_lock); |
d6bbafa1 CW |
11317 | } |
11318 | ||
6b95a207 KH |
11319 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
11320 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
11321 | struct drm_pending_vblank_event *event, |
11322 | uint32_t page_flip_flags) | |
6b95a207 KH |
11323 | { |
11324 | struct drm_device *dev = crtc->dev; | |
11325 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 11326 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 11327 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 | 11328 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
455a6808 | 11329 | struct drm_plane *primary = crtc->primary; |
a071fa00 | 11330 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 11331 | struct intel_unpin_work *work; |
a4872ba6 | 11332 | struct intel_engine_cs *ring; |
cf5d8a46 | 11333 | bool mmio_flip; |
91af127f | 11334 | struct drm_i915_gem_request *request = NULL; |
52e68630 | 11335 | int ret; |
6b95a207 | 11336 | |
2ff8fde1 MR |
11337 | /* |
11338 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
11339 | * check to be safe. In the future we may enable pageflipping from | |
11340 | * a disabled primary plane. | |
11341 | */ | |
11342 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
11343 | return -EBUSY; | |
11344 | ||
e6a595d2 | 11345 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 11346 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
11347 | return -EINVAL; |
11348 | ||
11349 | /* | |
11350 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
11351 | * Note that pitch changes could also affect these register. | |
11352 | */ | |
11353 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
11354 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
11355 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
11356 | return -EINVAL; |
11357 | ||
f900db47 CW |
11358 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
11359 | goto out_hang; | |
11360 | ||
b14c5679 | 11361 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
11362 | if (work == NULL) |
11363 | return -ENOMEM; | |
11364 | ||
6b95a207 | 11365 | work->event = event; |
b4a98e57 | 11366 | work->crtc = crtc; |
ab8d6675 | 11367 | work->old_fb = old_fb; |
6b95a207 KH |
11368 | INIT_WORK(&work->work, intel_unpin_work_fn); |
11369 | ||
87b6b101 | 11370 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
11371 | if (ret) |
11372 | goto free_work; | |
11373 | ||
6b95a207 | 11374 | /* We borrow the event spin lock for protecting unpin_work */ |
5e2d7afc | 11375 | spin_lock_irq(&dev->event_lock); |
6b95a207 | 11376 | if (intel_crtc->unpin_work) { |
d6bbafa1 CW |
11377 | /* Before declaring the flip queue wedged, check if |
11378 | * the hardware completed the operation behind our backs. | |
11379 | */ | |
11380 | if (__intel_pageflip_stall_check(dev, crtc)) { | |
11381 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
11382 | page_flip_completed(intel_crtc); | |
11383 | } else { | |
11384 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
5e2d7afc | 11385 | spin_unlock_irq(&dev->event_lock); |
468f0b44 | 11386 | |
d6bbafa1 CW |
11387 | drm_crtc_vblank_put(crtc); |
11388 | kfree(work); | |
11389 | return -EBUSY; | |
11390 | } | |
6b95a207 KH |
11391 | } |
11392 | intel_crtc->unpin_work = work; | |
5e2d7afc | 11393 | spin_unlock_irq(&dev->event_lock); |
6b95a207 | 11394 | |
b4a98e57 CW |
11395 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
11396 | flush_workqueue(dev_priv->wq); | |
11397 | ||
75dfca80 | 11398 | /* Reference the objects for the scheduled work. */ |
ab8d6675 | 11399 | drm_framebuffer_reference(work->old_fb); |
05394f39 | 11400 | drm_gem_object_reference(&obj->base); |
6b95a207 | 11401 | |
f4510a27 | 11402 | crtc->primary->fb = fb; |
afd65eb4 | 11403 | update_state_fb(crtc->primary); |
1ed1f968 | 11404 | |
e1f99ce6 | 11405 | work->pending_flip_obj = obj; |
e1f99ce6 | 11406 | |
89ed88ba CW |
11407 | ret = i915_mutex_lock_interruptible(dev); |
11408 | if (ret) | |
11409 | goto cleanup; | |
11410 | ||
b4a98e57 | 11411 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 11412 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 11413 | |
75f7f3ec | 11414 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
a071fa00 | 11415 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1; |
75f7f3ec | 11416 | |
4fa62c89 VS |
11417 | if (IS_VALLEYVIEW(dev)) { |
11418 | ring = &dev_priv->ring[BCS]; | |
ab8d6675 | 11419 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) |
8e09bf83 CW |
11420 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
11421 | ring = NULL; | |
48bf5b2d | 11422 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
2a92d5bc | 11423 | ring = &dev_priv->ring[BCS]; |
4fa62c89 | 11424 | } else if (INTEL_INFO(dev)->gen >= 7) { |
b4716185 | 11425 | ring = i915_gem_request_get_ring(obj->last_write_req); |
4fa62c89 VS |
11426 | if (ring == NULL || ring->id != RCS) |
11427 | ring = &dev_priv->ring[BCS]; | |
11428 | } else { | |
11429 | ring = &dev_priv->ring[RCS]; | |
11430 | } | |
11431 | ||
cf5d8a46 CW |
11432 | mmio_flip = use_mmio_flip(ring, obj); |
11433 | ||
11434 | /* When using CS flips, we want to emit semaphores between rings. | |
11435 | * However, when using mmio flips we will create a task to do the | |
11436 | * synchronisation, so all we want here is to pin the framebuffer | |
11437 | * into the display plane and skip any waits. | |
11438 | */ | |
82bc3b2d | 11439 | ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, |
cf5d8a46 | 11440 | crtc->primary->state, |
91af127f | 11441 | mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request); |
8c9f3aaf JB |
11442 | if (ret) |
11443 | goto cleanup_pending; | |
6b95a207 | 11444 | |
dedf278c TU |
11445 | work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), |
11446 | obj, 0); | |
11447 | work->gtt_offset += intel_crtc->dspaddr_offset; | |
4fa62c89 | 11448 | |
cf5d8a46 | 11449 | if (mmio_flip) { |
84c33a64 SG |
11450 | ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring, |
11451 | page_flip_flags); | |
d6bbafa1 CW |
11452 | if (ret) |
11453 | goto cleanup_unpin; | |
11454 | ||
f06cc1b9 JH |
11455 | i915_gem_request_assign(&work->flip_queued_req, |
11456 | obj->last_write_req); | |
d6bbafa1 | 11457 | } else { |
6258fbe2 JH |
11458 | if (!request) { |
11459 | ret = i915_gem_request_alloc(ring, ring->default_context, &request); | |
11460 | if (ret) | |
11461 | goto cleanup_unpin; | |
11462 | } | |
11463 | ||
11464 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, | |
d6bbafa1 CW |
11465 | page_flip_flags); |
11466 | if (ret) | |
11467 | goto cleanup_unpin; | |
11468 | ||
6258fbe2 | 11469 | i915_gem_request_assign(&work->flip_queued_req, request); |
d6bbafa1 CW |
11470 | } |
11471 | ||
91af127f | 11472 | if (request) |
75289874 | 11473 | i915_add_request_no_flush(request); |
91af127f | 11474 | |
1e3feefd | 11475 | work->flip_queued_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 | 11476 | work->enable_stall_check = true; |
4fa62c89 | 11477 | |
ab8d6675 | 11478 | i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, |
a9ff8714 | 11479 | to_intel_plane(primary)->frontbuffer_bit); |
c80ac854 | 11480 | mutex_unlock(&dev->struct_mutex); |
a071fa00 | 11481 | |
4e1e26f1 | 11482 | intel_fbc_disable_crtc(intel_crtc); |
a9ff8714 VS |
11483 | intel_frontbuffer_flip_prepare(dev, |
11484 | to_intel_plane(primary)->frontbuffer_bit); | |
6b95a207 | 11485 | |
e5510fac JB |
11486 | trace_i915_flip_request(intel_crtc->plane, obj); |
11487 | ||
6b95a207 | 11488 | return 0; |
96b099fd | 11489 | |
4fa62c89 | 11490 | cleanup_unpin: |
82bc3b2d | 11491 | intel_unpin_fb_obj(fb, crtc->primary->state); |
8c9f3aaf | 11492 | cleanup_pending: |
91af127f JH |
11493 | if (request) |
11494 | i915_gem_request_cancel(request); | |
b4a98e57 | 11495 | atomic_dec(&intel_crtc->unpin_work_count); |
89ed88ba CW |
11496 | mutex_unlock(&dev->struct_mutex); |
11497 | cleanup: | |
f4510a27 | 11498 | crtc->primary->fb = old_fb; |
afd65eb4 | 11499 | update_state_fb(crtc->primary); |
89ed88ba CW |
11500 | |
11501 | drm_gem_object_unreference_unlocked(&obj->base); | |
ab8d6675 | 11502 | drm_framebuffer_unreference(work->old_fb); |
96b099fd | 11503 | |
5e2d7afc | 11504 | spin_lock_irq(&dev->event_lock); |
96b099fd | 11505 | intel_crtc->unpin_work = NULL; |
5e2d7afc | 11506 | spin_unlock_irq(&dev->event_lock); |
96b099fd | 11507 | |
87b6b101 | 11508 | drm_crtc_vblank_put(crtc); |
7317c75e | 11509 | free_work: |
96b099fd CW |
11510 | kfree(work); |
11511 | ||
f900db47 | 11512 | if (ret == -EIO) { |
02e0efb5 ML |
11513 | struct drm_atomic_state *state; |
11514 | struct drm_plane_state *plane_state; | |
11515 | ||
f900db47 | 11516 | out_hang: |
02e0efb5 ML |
11517 | state = drm_atomic_state_alloc(dev); |
11518 | if (!state) | |
11519 | return -ENOMEM; | |
11520 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); | |
11521 | ||
11522 | retry: | |
11523 | plane_state = drm_atomic_get_plane_state(state, primary); | |
11524 | ret = PTR_ERR_OR_ZERO(plane_state); | |
11525 | if (!ret) { | |
11526 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
11527 | ||
11528 | ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); | |
11529 | if (!ret) | |
11530 | ret = drm_atomic_commit(state); | |
11531 | } | |
11532 | ||
11533 | if (ret == -EDEADLK) { | |
11534 | drm_modeset_backoff(state->acquire_ctx); | |
11535 | drm_atomic_state_clear(state); | |
11536 | goto retry; | |
11537 | } | |
11538 | ||
11539 | if (ret) | |
11540 | drm_atomic_state_free(state); | |
11541 | ||
f0d3dad3 | 11542 | if (ret == 0 && event) { |
5e2d7afc | 11543 | spin_lock_irq(&dev->event_lock); |
a071fa00 | 11544 | drm_send_vblank_event(dev, pipe, event); |
5e2d7afc | 11545 | spin_unlock_irq(&dev->event_lock); |
f0d3dad3 | 11546 | } |
f900db47 | 11547 | } |
96b099fd | 11548 | return ret; |
6b95a207 KH |
11549 | } |
11550 | ||
da20eabd ML |
11551 | |
11552 | /** | |
11553 | * intel_wm_need_update - Check whether watermarks need updating | |
11554 | * @plane: drm plane | |
11555 | * @state: new plane state | |
11556 | * | |
11557 | * Check current plane state versus the new one to determine whether | |
11558 | * watermarks need to be recalculated. | |
11559 | * | |
11560 | * Returns true or false. | |
11561 | */ | |
11562 | static bool intel_wm_need_update(struct drm_plane *plane, | |
11563 | struct drm_plane_state *state) | |
11564 | { | |
11565 | /* Update watermarks on tiling changes. */ | |
11566 | if (!plane->state->fb || !state->fb || | |
11567 | plane->state->fb->modifier[0] != state->fb->modifier[0] || | |
11568 | plane->state->rotation != state->rotation) | |
11569 | return true; | |
11570 | ||
11571 | if (plane->state->crtc_w != state->crtc_w) | |
11572 | return true; | |
11573 | ||
11574 | return false; | |
11575 | } | |
11576 | ||
11577 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, | |
11578 | struct drm_plane_state *plane_state) | |
11579 | { | |
11580 | struct drm_crtc *crtc = crtc_state->crtc; | |
11581 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11582 | struct drm_plane *plane = plane_state->plane; | |
11583 | struct drm_device *dev = crtc->dev; | |
11584 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11585 | struct intel_plane_state *old_plane_state = | |
11586 | to_intel_plane_state(plane->state); | |
11587 | int idx = intel_crtc->base.base.id, ret; | |
11588 | int i = drm_plane_index(plane); | |
11589 | bool mode_changed = needs_modeset(crtc_state); | |
11590 | bool was_crtc_enabled = crtc->state->active; | |
11591 | bool is_crtc_enabled = crtc_state->active; | |
11592 | ||
11593 | bool turn_off, turn_on, visible, was_visible; | |
11594 | struct drm_framebuffer *fb = plane_state->fb; | |
11595 | ||
11596 | if (crtc_state && INTEL_INFO(dev)->gen >= 9 && | |
11597 | plane->type != DRM_PLANE_TYPE_CURSOR) { | |
11598 | ret = skl_update_scaler_plane( | |
11599 | to_intel_crtc_state(crtc_state), | |
11600 | to_intel_plane_state(plane_state)); | |
11601 | if (ret) | |
11602 | return ret; | |
11603 | } | |
11604 | ||
11605 | /* | |
11606 | * Disabling a plane is always okay; we just need to update | |
11607 | * fb tracking in a special way since cleanup_fb() won't | |
11608 | * get called by the plane helpers. | |
11609 | */ | |
11610 | if (old_plane_state->base.fb && !fb) | |
11611 | intel_crtc->atomic.disabled_planes |= 1 << i; | |
11612 | ||
da20eabd ML |
11613 | was_visible = old_plane_state->visible; |
11614 | visible = to_intel_plane_state(plane_state)->visible; | |
11615 | ||
11616 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
11617 | was_visible = false; | |
11618 | ||
11619 | if (!is_crtc_enabled && WARN_ON(visible)) | |
11620 | visible = false; | |
11621 | ||
11622 | if (!was_visible && !visible) | |
11623 | return 0; | |
11624 | ||
11625 | turn_off = was_visible && (!visible || mode_changed); | |
11626 | turn_on = visible && (!was_visible || mode_changed); | |
11627 | ||
11628 | DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx, | |
11629 | plane->base.id, fb ? fb->base.id : -1); | |
11630 | ||
11631 | DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n", | |
11632 | plane->base.id, was_visible, visible, | |
11633 | turn_off, turn_on, mode_changed); | |
11634 | ||
852eb00d | 11635 | if (turn_on) { |
f015c551 | 11636 | intel_crtc->atomic.update_wm_pre = true; |
852eb00d VS |
11637 | /* must disable cxsr around plane enable/disable */ |
11638 | if (plane->type != DRM_PLANE_TYPE_CURSOR) { | |
11639 | intel_crtc->atomic.disable_cxsr = true; | |
11640 | /* to potentially re-enable cxsr */ | |
11641 | intel_crtc->atomic.wait_vblank = true; | |
11642 | intel_crtc->atomic.update_wm_post = true; | |
11643 | } | |
11644 | } else if (turn_off) { | |
f015c551 | 11645 | intel_crtc->atomic.update_wm_post = true; |
852eb00d VS |
11646 | /* must disable cxsr around plane enable/disable */ |
11647 | if (plane->type != DRM_PLANE_TYPE_CURSOR) { | |
11648 | if (is_crtc_enabled) | |
11649 | intel_crtc->atomic.wait_vblank = true; | |
11650 | intel_crtc->atomic.disable_cxsr = true; | |
11651 | } | |
11652 | } else if (intel_wm_need_update(plane, plane_state)) { | |
f015c551 | 11653 | intel_crtc->atomic.update_wm_pre = true; |
852eb00d | 11654 | } |
da20eabd | 11655 | |
8be6ca85 | 11656 | if (visible || was_visible) |
a9ff8714 VS |
11657 | intel_crtc->atomic.fb_bits |= |
11658 | to_intel_plane(plane)->frontbuffer_bit; | |
11659 | ||
da20eabd ML |
11660 | switch (plane->type) { |
11661 | case DRM_PLANE_TYPE_PRIMARY: | |
da20eabd ML |
11662 | intel_crtc->atomic.wait_for_flips = true; |
11663 | intel_crtc->atomic.pre_disable_primary = turn_off; | |
11664 | intel_crtc->atomic.post_enable_primary = turn_on; | |
11665 | ||
066cf55b RV |
11666 | if (turn_off) { |
11667 | /* | |
11668 | * FIXME: Actually if we will still have any other | |
11669 | * plane enabled on the pipe we could let IPS enabled | |
11670 | * still, but for now lets consider that when we make | |
11671 | * primary invisible by setting DSPCNTR to 0 on | |
11672 | * update_primary_plane function IPS needs to be | |
11673 | * disable. | |
11674 | */ | |
11675 | intel_crtc->atomic.disable_ips = true; | |
11676 | ||
da20eabd | 11677 | intel_crtc->atomic.disable_fbc = true; |
066cf55b | 11678 | } |
da20eabd ML |
11679 | |
11680 | /* | |
11681 | * FBC does not work on some platforms for rotated | |
11682 | * planes, so disable it when rotation is not 0 and | |
11683 | * update it when rotation is set back to 0. | |
11684 | * | |
11685 | * FIXME: This is redundant with the fbc update done in | |
11686 | * the primary plane enable function except that that | |
11687 | * one is done too late. We eventually need to unify | |
11688 | * this. | |
11689 | */ | |
11690 | ||
11691 | if (visible && | |
11692 | INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && | |
11693 | dev_priv->fbc.crtc == intel_crtc && | |
11694 | plane_state->rotation != BIT(DRM_ROTATE_0)) | |
11695 | intel_crtc->atomic.disable_fbc = true; | |
11696 | ||
11697 | /* | |
11698 | * BDW signals flip done immediately if the plane | |
11699 | * is disabled, even if the plane enable is already | |
11700 | * armed to occur at the next vblank :( | |
11701 | */ | |
11702 | if (turn_on && IS_BROADWELL(dev)) | |
11703 | intel_crtc->atomic.wait_vblank = true; | |
11704 | ||
11705 | intel_crtc->atomic.update_fbc |= visible || mode_changed; | |
11706 | break; | |
11707 | case DRM_PLANE_TYPE_CURSOR: | |
da20eabd ML |
11708 | break; |
11709 | case DRM_PLANE_TYPE_OVERLAY: | |
d032ffa0 | 11710 | if (turn_off && !mode_changed) { |
da20eabd ML |
11711 | intel_crtc->atomic.wait_vblank = true; |
11712 | intel_crtc->atomic.update_sprite_watermarks |= | |
11713 | 1 << i; | |
11714 | } | |
da20eabd ML |
11715 | } |
11716 | return 0; | |
11717 | } | |
11718 | ||
6d3a1ce7 ML |
11719 | static bool encoders_cloneable(const struct intel_encoder *a, |
11720 | const struct intel_encoder *b) | |
11721 | { | |
11722 | /* masks could be asymmetric, so check both ways */ | |
11723 | return a == b || (a->cloneable & (1 << b->type) && | |
11724 | b->cloneable & (1 << a->type)); | |
11725 | } | |
11726 | ||
11727 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
11728 | struct intel_crtc *crtc, | |
11729 | struct intel_encoder *encoder) | |
11730 | { | |
11731 | struct intel_encoder *source_encoder; | |
11732 | struct drm_connector *connector; | |
11733 | struct drm_connector_state *connector_state; | |
11734 | int i; | |
11735 | ||
11736 | for_each_connector_in_state(state, connector, connector_state, i) { | |
11737 | if (connector_state->crtc != &crtc->base) | |
11738 | continue; | |
11739 | ||
11740 | source_encoder = | |
11741 | to_intel_encoder(connector_state->best_encoder); | |
11742 | if (!encoders_cloneable(encoder, source_encoder)) | |
11743 | return false; | |
11744 | } | |
11745 | ||
11746 | return true; | |
11747 | } | |
11748 | ||
11749 | static bool check_encoder_cloning(struct drm_atomic_state *state, | |
11750 | struct intel_crtc *crtc) | |
11751 | { | |
11752 | struct intel_encoder *encoder; | |
11753 | struct drm_connector *connector; | |
11754 | struct drm_connector_state *connector_state; | |
11755 | int i; | |
11756 | ||
11757 | for_each_connector_in_state(state, connector, connector_state, i) { | |
11758 | if (connector_state->crtc != &crtc->base) | |
11759 | continue; | |
11760 | ||
11761 | encoder = to_intel_encoder(connector_state->best_encoder); | |
11762 | if (!check_single_encoder_cloning(state, crtc, encoder)) | |
11763 | return false; | |
11764 | } | |
11765 | ||
11766 | return true; | |
11767 | } | |
11768 | ||
11769 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, | |
11770 | struct drm_crtc_state *crtc_state) | |
11771 | { | |
cf5a15be | 11772 | struct drm_device *dev = crtc->dev; |
ad421372 | 11773 | struct drm_i915_private *dev_priv = dev->dev_private; |
6d3a1ce7 | 11774 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
11775 | struct intel_crtc_state *pipe_config = |
11776 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 11777 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 11778 | int ret; |
6d3a1ce7 ML |
11779 | bool mode_changed = needs_modeset(crtc_state); |
11780 | ||
11781 | if (mode_changed && !check_encoder_cloning(state, intel_crtc)) { | |
11782 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
11783 | return -EINVAL; | |
11784 | } | |
11785 | ||
852eb00d VS |
11786 | if (mode_changed && !crtc_state->active) |
11787 | intel_crtc->atomic.update_wm_post = true; | |
eddfcbcd | 11788 | |
ad421372 ML |
11789 | if (mode_changed && crtc_state->enable && |
11790 | dev_priv->display.crtc_compute_clock && | |
11791 | !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) { | |
11792 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, | |
11793 | pipe_config); | |
11794 | if (ret) | |
11795 | return ret; | |
11796 | } | |
11797 | ||
e435d6e5 ML |
11798 | ret = 0; |
11799 | if (INTEL_INFO(dev)->gen >= 9) { | |
11800 | if (mode_changed) | |
11801 | ret = skl_update_scaler_crtc(pipe_config); | |
11802 | ||
11803 | if (!ret) | |
11804 | ret = intel_atomic_setup_scalers(dev, intel_crtc, | |
11805 | pipe_config); | |
11806 | } | |
11807 | ||
11808 | return ret; | |
6d3a1ce7 ML |
11809 | } |
11810 | ||
65b38e0d | 11811 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
11812 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
11813 | .load_lut = intel_crtc_load_lut, | |
ea2c67bb MR |
11814 | .atomic_begin = intel_begin_crtc_commit, |
11815 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 11816 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
11817 | }; |
11818 | ||
d29b2f9d ACO |
11819 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
11820 | { | |
11821 | struct intel_connector *connector; | |
11822 | ||
11823 | for_each_intel_connector(dev, connector) { | |
11824 | if (connector->base.encoder) { | |
11825 | connector->base.state->best_encoder = | |
11826 | connector->base.encoder; | |
11827 | connector->base.state->crtc = | |
11828 | connector->base.encoder->crtc; | |
11829 | } else { | |
11830 | connector->base.state->best_encoder = NULL; | |
11831 | connector->base.state->crtc = NULL; | |
11832 | } | |
11833 | } | |
11834 | } | |
11835 | ||
050f7aeb | 11836 | static void |
eba905b2 | 11837 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 11838 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
11839 | { |
11840 | int bpp = pipe_config->pipe_bpp; | |
11841 | ||
11842 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
11843 | connector->base.base.id, | |
c23cc417 | 11844 | connector->base.name); |
050f7aeb DV |
11845 | |
11846 | /* Don't use an invalid EDID bpc value */ | |
11847 | if (connector->base.display_info.bpc && | |
11848 | connector->base.display_info.bpc * 3 < bpp) { | |
11849 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
11850 | bpp, connector->base.display_info.bpc*3); | |
11851 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
11852 | } | |
11853 | ||
11854 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
11855 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
11856 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
11857 | bpp); | |
11858 | pipe_config->pipe_bpp = 24; | |
11859 | } | |
11860 | } | |
11861 | ||
4e53c2e0 | 11862 | static int |
050f7aeb | 11863 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 11864 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 11865 | { |
050f7aeb | 11866 | struct drm_device *dev = crtc->base.dev; |
1486017f | 11867 | struct drm_atomic_state *state; |
da3ced29 ACO |
11868 | struct drm_connector *connector; |
11869 | struct drm_connector_state *connector_state; | |
1486017f | 11870 | int bpp, i; |
4e53c2e0 | 11871 | |
d328c9d7 | 11872 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev))) |
4e53c2e0 | 11873 | bpp = 10*3; |
d328c9d7 DV |
11874 | else if (INTEL_INFO(dev)->gen >= 5) |
11875 | bpp = 12*3; | |
11876 | else | |
11877 | bpp = 8*3; | |
11878 | ||
4e53c2e0 | 11879 | |
4e53c2e0 DV |
11880 | pipe_config->pipe_bpp = bpp; |
11881 | ||
1486017f ACO |
11882 | state = pipe_config->base.state; |
11883 | ||
4e53c2e0 | 11884 | /* Clamp display bpp to EDID value */ |
da3ced29 ACO |
11885 | for_each_connector_in_state(state, connector, connector_state, i) { |
11886 | if (connector_state->crtc != &crtc->base) | |
4e53c2e0 DV |
11887 | continue; |
11888 | ||
da3ced29 ACO |
11889 | connected_sink_compute_bpp(to_intel_connector(connector), |
11890 | pipe_config); | |
4e53c2e0 DV |
11891 | } |
11892 | ||
11893 | return bpp; | |
11894 | } | |
11895 | ||
644db711 DV |
11896 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
11897 | { | |
11898 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
11899 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 11900 | mode->crtc_clock, |
644db711 DV |
11901 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
11902 | mode->crtc_hsync_end, mode->crtc_htotal, | |
11903 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
11904 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
11905 | } | |
11906 | ||
c0b03411 | 11907 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 11908 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
11909 | const char *context) |
11910 | { | |
6a60cd87 CK |
11911 | struct drm_device *dev = crtc->base.dev; |
11912 | struct drm_plane *plane; | |
11913 | struct intel_plane *intel_plane; | |
11914 | struct intel_plane_state *state; | |
11915 | struct drm_framebuffer *fb; | |
11916 | ||
11917 | DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id, | |
11918 | context, pipe_config, pipe_name(crtc->pipe)); | |
c0b03411 DV |
11919 | |
11920 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
11921 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
11922 | pipe_config->pipe_bpp, pipe_config->dither); | |
11923 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
11924 | pipe_config->has_pch_encoder, | |
11925 | pipe_config->fdi_lanes, | |
11926 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
11927 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
11928 | pipe_config->fdi_m_n.tu); | |
90a6b7b0 | 11929 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
eb14cb74 | 11930 | pipe_config->has_dp_encoder, |
90a6b7b0 | 11931 | pipe_config->lane_count, |
eb14cb74 VS |
11932 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, |
11933 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
11934 | pipe_config->dp_m_n.tu); | |
b95af8be | 11935 | |
90a6b7b0 | 11936 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", |
b95af8be | 11937 | pipe_config->has_dp_encoder, |
90a6b7b0 | 11938 | pipe_config->lane_count, |
b95af8be VK |
11939 | pipe_config->dp_m2_n2.gmch_m, |
11940 | pipe_config->dp_m2_n2.gmch_n, | |
11941 | pipe_config->dp_m2_n2.link_m, | |
11942 | pipe_config->dp_m2_n2.link_n, | |
11943 | pipe_config->dp_m2_n2.tu); | |
11944 | ||
55072d19 DV |
11945 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
11946 | pipe_config->has_audio, | |
11947 | pipe_config->has_infoframe); | |
11948 | ||
c0b03411 | 11949 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 11950 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 11951 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
11952 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
11953 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 11954 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
11955 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
11956 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
0ec463d3 TU |
11957 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", |
11958 | crtc->num_scalers, | |
11959 | pipe_config->scaler_state.scaler_users, | |
11960 | pipe_config->scaler_state.scaler_id); | |
c0b03411 DV |
11961 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
11962 | pipe_config->gmch_pfit.control, | |
11963 | pipe_config->gmch_pfit.pgm_ratios, | |
11964 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 11965 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 11966 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
11967 | pipe_config->pch_pfit.size, |
11968 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 11969 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 11970 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
6a60cd87 | 11971 | |
415ff0f6 | 11972 | if (IS_BROXTON(dev)) { |
05712c15 | 11973 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," |
415ff0f6 | 11974 | "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " |
c8453338 | 11975 | "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", |
415ff0f6 TU |
11976 | pipe_config->ddi_pll_sel, |
11977 | pipe_config->dpll_hw_state.ebb0, | |
05712c15 | 11978 | pipe_config->dpll_hw_state.ebb4, |
415ff0f6 TU |
11979 | pipe_config->dpll_hw_state.pll0, |
11980 | pipe_config->dpll_hw_state.pll1, | |
11981 | pipe_config->dpll_hw_state.pll2, | |
11982 | pipe_config->dpll_hw_state.pll3, | |
11983 | pipe_config->dpll_hw_state.pll6, | |
11984 | pipe_config->dpll_hw_state.pll8, | |
05712c15 | 11985 | pipe_config->dpll_hw_state.pll9, |
c8453338 | 11986 | pipe_config->dpll_hw_state.pll10, |
415ff0f6 TU |
11987 | pipe_config->dpll_hw_state.pcsdw12); |
11988 | } else if (IS_SKYLAKE(dev)) { | |
11989 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " | |
11990 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", | |
11991 | pipe_config->ddi_pll_sel, | |
11992 | pipe_config->dpll_hw_state.ctrl1, | |
11993 | pipe_config->dpll_hw_state.cfgcr1, | |
11994 | pipe_config->dpll_hw_state.cfgcr2); | |
11995 | } else if (HAS_DDI(dev)) { | |
11996 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n", | |
11997 | pipe_config->ddi_pll_sel, | |
11998 | pipe_config->dpll_hw_state.wrpll); | |
11999 | } else { | |
12000 | DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " | |
12001 | "fp0: 0x%x, fp1: 0x%x\n", | |
12002 | pipe_config->dpll_hw_state.dpll, | |
12003 | pipe_config->dpll_hw_state.dpll_md, | |
12004 | pipe_config->dpll_hw_state.fp0, | |
12005 | pipe_config->dpll_hw_state.fp1); | |
12006 | } | |
12007 | ||
6a60cd87 CK |
12008 | DRM_DEBUG_KMS("planes on this crtc\n"); |
12009 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
12010 | intel_plane = to_intel_plane(plane); | |
12011 | if (intel_plane->pipe != crtc->pipe) | |
12012 | continue; | |
12013 | ||
12014 | state = to_intel_plane_state(plane->state); | |
12015 | fb = state->base.fb; | |
12016 | if (!fb) { | |
12017 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d " | |
12018 | "disabled, scaler_id = %d\n", | |
12019 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12020 | plane->base.id, intel_plane->pipe, | |
12021 | (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1, | |
12022 | drm_plane_index(plane), state->scaler_id); | |
12023 | continue; | |
12024 | } | |
12025 | ||
12026 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled", | |
12027 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12028 | plane->base.id, intel_plane->pipe, | |
12029 | crtc->base.primary == plane ? 0 : intel_plane->plane + 1, | |
12030 | drm_plane_index(plane)); | |
12031 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x", | |
12032 | fb->base.id, fb->width, fb->height, fb->pixel_format); | |
12033 | DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n", | |
12034 | state->scaler_id, | |
12035 | state->src.x1 >> 16, state->src.y1 >> 16, | |
12036 | drm_rect_width(&state->src) >> 16, | |
12037 | drm_rect_height(&state->src) >> 16, | |
12038 | state->dst.x1, state->dst.y1, | |
12039 | drm_rect_width(&state->dst), drm_rect_height(&state->dst)); | |
12040 | } | |
c0b03411 DV |
12041 | } |
12042 | ||
5448a00d | 12043 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 12044 | { |
5448a00d ACO |
12045 | struct drm_device *dev = state->dev; |
12046 | struct intel_encoder *encoder; | |
da3ced29 | 12047 | struct drm_connector *connector; |
5448a00d | 12048 | struct drm_connector_state *connector_state; |
00f0b378 | 12049 | unsigned int used_ports = 0; |
5448a00d | 12050 | int i; |
00f0b378 VS |
12051 | |
12052 | /* | |
12053 | * Walk the connector list instead of the encoder | |
12054 | * list to detect the problem on ddi platforms | |
12055 | * where there's just one encoder per digital port. | |
12056 | */ | |
da3ced29 | 12057 | for_each_connector_in_state(state, connector, connector_state, i) { |
5448a00d | 12058 | if (!connector_state->best_encoder) |
00f0b378 VS |
12059 | continue; |
12060 | ||
5448a00d ACO |
12061 | encoder = to_intel_encoder(connector_state->best_encoder); |
12062 | ||
12063 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
12064 | |
12065 | switch (encoder->type) { | |
12066 | unsigned int port_mask; | |
12067 | case INTEL_OUTPUT_UNKNOWN: | |
12068 | if (WARN_ON(!HAS_DDI(dev))) | |
12069 | break; | |
12070 | case INTEL_OUTPUT_DISPLAYPORT: | |
12071 | case INTEL_OUTPUT_HDMI: | |
12072 | case INTEL_OUTPUT_EDP: | |
12073 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
12074 | ||
12075 | /* the same port mustn't appear more than once */ | |
12076 | if (used_ports & port_mask) | |
12077 | return false; | |
12078 | ||
12079 | used_ports |= port_mask; | |
12080 | default: | |
12081 | break; | |
12082 | } | |
12083 | } | |
12084 | ||
12085 | return true; | |
12086 | } | |
12087 | ||
83a57153 ACO |
12088 | static void |
12089 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
12090 | { | |
12091 | struct drm_crtc_state tmp_state; | |
663a3640 | 12092 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 ACO |
12093 | struct intel_dpll_hw_state dpll_hw_state; |
12094 | enum intel_dpll_id shared_dpll; | |
8504c74c | 12095 | uint32_t ddi_pll_sel; |
c4e2d043 | 12096 | bool force_thru; |
83a57153 | 12097 | |
7546a384 ACO |
12098 | /* FIXME: before the switch to atomic started, a new pipe_config was |
12099 | * kzalloc'd. Code that depends on any field being zero should be | |
12100 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
12101 | * only fields that are know to not cause problems are preserved. */ | |
12102 | ||
83a57153 | 12103 | tmp_state = crtc_state->base; |
663a3640 | 12104 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
12105 | shared_dpll = crtc_state->shared_dpll; |
12106 | dpll_hw_state = crtc_state->dpll_hw_state; | |
8504c74c | 12107 | ddi_pll_sel = crtc_state->ddi_pll_sel; |
c4e2d043 | 12108 | force_thru = crtc_state->pch_pfit.force_thru; |
4978cc93 | 12109 | |
83a57153 | 12110 | memset(crtc_state, 0, sizeof *crtc_state); |
4978cc93 | 12111 | |
83a57153 | 12112 | crtc_state->base = tmp_state; |
663a3640 | 12113 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
12114 | crtc_state->shared_dpll = shared_dpll; |
12115 | crtc_state->dpll_hw_state = dpll_hw_state; | |
8504c74c | 12116 | crtc_state->ddi_pll_sel = ddi_pll_sel; |
c4e2d043 | 12117 | crtc_state->pch_pfit.force_thru = force_thru; |
83a57153 ACO |
12118 | } |
12119 | ||
548ee15b | 12120 | static int |
b8cecdf5 | 12121 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 12122 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 12123 | { |
b359283a | 12124 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 12125 | struct intel_encoder *encoder; |
da3ced29 | 12126 | struct drm_connector *connector; |
0b901879 | 12127 | struct drm_connector_state *connector_state; |
d328c9d7 | 12128 | int base_bpp, ret = -EINVAL; |
0b901879 | 12129 | int i; |
e29c22c0 | 12130 | bool retry = true; |
ee7b9f93 | 12131 | |
83a57153 | 12132 | clear_intel_crtc_state(pipe_config); |
7758a113 | 12133 | |
e143a21c DV |
12134 | pipe_config->cpu_transcoder = |
12135 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 12136 | |
2960bc9c ID |
12137 | /* |
12138 | * Sanitize sync polarity flags based on requested ones. If neither | |
12139 | * positive or negative polarity is requested, treat this as meaning | |
12140 | * negative polarity. | |
12141 | */ | |
2d112de7 | 12142 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12143 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 12144 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 12145 | |
2d112de7 | 12146 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12147 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 12148 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 12149 | |
d328c9d7 DV |
12150 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
12151 | pipe_config); | |
12152 | if (base_bpp < 0) | |
4e53c2e0 DV |
12153 | goto fail; |
12154 | ||
e41a56be VS |
12155 | /* |
12156 | * Determine the real pipe dimensions. Note that stereo modes can | |
12157 | * increase the actual pipe size due to the frame doubling and | |
12158 | * insertion of additional space for blanks between the frame. This | |
12159 | * is stored in the crtc timings. We use the requested mode to do this | |
12160 | * computation to clearly distinguish it from the adjusted mode, which | |
12161 | * can be changed by the connectors in the below retry loop. | |
12162 | */ | |
2d112de7 | 12163 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
12164 | &pipe_config->pipe_src_w, |
12165 | &pipe_config->pipe_src_h); | |
e41a56be | 12166 | |
e29c22c0 | 12167 | encoder_retry: |
ef1b460d | 12168 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 12169 | pipe_config->port_clock = 0; |
ef1b460d | 12170 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 12171 | |
135c81b8 | 12172 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
12173 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
12174 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 12175 | |
7758a113 DV |
12176 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
12177 | * adjust it according to limitations or connector properties, and also | |
12178 | * a chance to reject the mode entirely. | |
47f1c6c9 | 12179 | */ |
da3ced29 | 12180 | for_each_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 12181 | if (connector_state->crtc != crtc) |
7758a113 | 12182 | continue; |
7ae89233 | 12183 | |
0b901879 ACO |
12184 | encoder = to_intel_encoder(connector_state->best_encoder); |
12185 | ||
efea6e8e DV |
12186 | if (!(encoder->compute_config(encoder, pipe_config))) { |
12187 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
12188 | goto fail; |
12189 | } | |
ee7b9f93 | 12190 | } |
47f1c6c9 | 12191 | |
ff9a6750 DV |
12192 | /* Set default port clock if not overwritten by the encoder. Needs to be |
12193 | * done afterwards in case the encoder adjusts the mode. */ | |
12194 | if (!pipe_config->port_clock) | |
2d112de7 | 12195 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 12196 | * pipe_config->pixel_multiplier; |
ff9a6750 | 12197 | |
a43f6e0f | 12198 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 12199 | if (ret < 0) { |
7758a113 DV |
12200 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
12201 | goto fail; | |
ee7b9f93 | 12202 | } |
e29c22c0 DV |
12203 | |
12204 | if (ret == RETRY) { | |
12205 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
12206 | ret = -EINVAL; | |
12207 | goto fail; | |
12208 | } | |
12209 | ||
12210 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
12211 | retry = false; | |
12212 | goto encoder_retry; | |
12213 | } | |
12214 | ||
e8fa4270 DV |
12215 | /* Dithering seems to not pass-through bits correctly when it should, so |
12216 | * only enable it on 6bpc panels. */ | |
12217 | pipe_config->dither = pipe_config->pipe_bpp == 6*3; | |
62f0ace5 | 12218 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 12219 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 12220 | |
7758a113 | 12221 | fail: |
548ee15b | 12222 | return ret; |
ee7b9f93 | 12223 | } |
47f1c6c9 | 12224 | |
ea9d758d | 12225 | static void |
4740b0f2 | 12226 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 12227 | { |
0a9ab303 ACO |
12228 | struct drm_crtc *crtc; |
12229 | struct drm_crtc_state *crtc_state; | |
8a75d157 | 12230 | int i; |
ea9d758d | 12231 | |
7668851f | 12232 | /* Double check state. */ |
8a75d157 | 12233 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
3cb480bc | 12234 | to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); |
fc467a22 ML |
12235 | |
12236 | /* Update hwmode for vblank functions */ | |
12237 | if (crtc->state->active) | |
12238 | crtc->hwmode = crtc->state->adjusted_mode; | |
12239 | else | |
12240 | crtc->hwmode.crtc_clock = 0; | |
ea9d758d | 12241 | } |
ea9d758d DV |
12242 | } |
12243 | ||
3bd26263 | 12244 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 12245 | { |
3bd26263 | 12246 | int diff; |
f1f644dc JB |
12247 | |
12248 | if (clock1 == clock2) | |
12249 | return true; | |
12250 | ||
12251 | if (!clock1 || !clock2) | |
12252 | return false; | |
12253 | ||
12254 | diff = abs(clock1 - clock2); | |
12255 | ||
12256 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
12257 | return true; | |
12258 | ||
12259 | return false; | |
12260 | } | |
12261 | ||
25c5b266 DV |
12262 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
12263 | list_for_each_entry((intel_crtc), \ | |
12264 | &(dev)->mode_config.crtc_list, \ | |
12265 | base.head) \ | |
0973f18f | 12266 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 12267 | |
cfb23ed6 ML |
12268 | static bool |
12269 | intel_compare_m_n(unsigned int m, unsigned int n, | |
12270 | unsigned int m2, unsigned int n2, | |
12271 | bool exact) | |
12272 | { | |
12273 | if (m == m2 && n == n2) | |
12274 | return true; | |
12275 | ||
12276 | if (exact || !m || !n || !m2 || !n2) | |
12277 | return false; | |
12278 | ||
12279 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
12280 | ||
12281 | if (m > m2) { | |
12282 | while (m > m2) { | |
12283 | m2 <<= 1; | |
12284 | n2 <<= 1; | |
12285 | } | |
12286 | } else if (m < m2) { | |
12287 | while (m < m2) { | |
12288 | m <<= 1; | |
12289 | n <<= 1; | |
12290 | } | |
12291 | } | |
12292 | ||
12293 | return m == m2 && n == n2; | |
12294 | } | |
12295 | ||
12296 | static bool | |
12297 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
12298 | struct intel_link_m_n *m2_n2, | |
12299 | bool adjust) | |
12300 | { | |
12301 | if (m_n->tu == m2_n2->tu && | |
12302 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
12303 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
12304 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
12305 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
12306 | if (adjust) | |
12307 | *m2_n2 = *m_n; | |
12308 | ||
12309 | return true; | |
12310 | } | |
12311 | ||
12312 | return false; | |
12313 | } | |
12314 | ||
0e8ffe1b | 12315 | static bool |
2fa2fe9a | 12316 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b | 12317 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
12318 | struct intel_crtc_state *pipe_config, |
12319 | bool adjust) | |
0e8ffe1b | 12320 | { |
cfb23ed6 ML |
12321 | bool ret = true; |
12322 | ||
12323 | #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \ | |
12324 | do { \ | |
12325 | if (!adjust) \ | |
12326 | DRM_ERROR(fmt, ##__VA_ARGS__); \ | |
12327 | else \ | |
12328 | DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \ | |
12329 | } while (0) | |
12330 | ||
66e985c0 DV |
12331 | #define PIPE_CONF_CHECK_X(name) \ |
12332 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12333 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
66e985c0 DV |
12334 | "(expected 0x%08x, found 0x%08x)\n", \ |
12335 | current_config->name, \ | |
12336 | pipe_config->name); \ | |
cfb23ed6 | 12337 | ret = false; \ |
66e985c0 DV |
12338 | } |
12339 | ||
08a24034 DV |
12340 | #define PIPE_CONF_CHECK_I(name) \ |
12341 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12342 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
08a24034 DV |
12343 | "(expected %i, found %i)\n", \ |
12344 | current_config->name, \ | |
12345 | pipe_config->name); \ | |
cfb23ed6 ML |
12346 | ret = false; \ |
12347 | } | |
12348 | ||
12349 | #define PIPE_CONF_CHECK_M_N(name) \ | |
12350 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12351 | &pipe_config->name,\ | |
12352 | adjust)) { \ | |
12353 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12354 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12355 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12356 | current_config->name.tu, \ | |
12357 | current_config->name.gmch_m, \ | |
12358 | current_config->name.gmch_n, \ | |
12359 | current_config->name.link_m, \ | |
12360 | current_config->name.link_n, \ | |
12361 | pipe_config->name.tu, \ | |
12362 | pipe_config->name.gmch_m, \ | |
12363 | pipe_config->name.gmch_n, \ | |
12364 | pipe_config->name.link_m, \ | |
12365 | pipe_config->name.link_n); \ | |
12366 | ret = false; \ | |
12367 | } | |
12368 | ||
12369 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ | |
12370 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12371 | &pipe_config->name, adjust) && \ | |
12372 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
12373 | &pipe_config->name, adjust)) { \ | |
12374 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12375 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12376 | "or tu %i gmch %i/%i link %i/%i, " \ | |
12377 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12378 | current_config->name.tu, \ | |
12379 | current_config->name.gmch_m, \ | |
12380 | current_config->name.gmch_n, \ | |
12381 | current_config->name.link_m, \ | |
12382 | current_config->name.link_n, \ | |
12383 | current_config->alt_name.tu, \ | |
12384 | current_config->alt_name.gmch_m, \ | |
12385 | current_config->alt_name.gmch_n, \ | |
12386 | current_config->alt_name.link_m, \ | |
12387 | current_config->alt_name.link_n, \ | |
12388 | pipe_config->name.tu, \ | |
12389 | pipe_config->name.gmch_m, \ | |
12390 | pipe_config->name.gmch_n, \ | |
12391 | pipe_config->name.link_m, \ | |
12392 | pipe_config->name.link_n); \ | |
12393 | ret = false; \ | |
88adfff1 DV |
12394 | } |
12395 | ||
b95af8be VK |
12396 | /* This is required for BDW+ where there is only one set of registers for |
12397 | * switching between high and low RR. | |
12398 | * This macro can be used whenever a comparison has to be made between one | |
12399 | * hw state and multiple sw state variables. | |
12400 | */ | |
12401 | #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ | |
12402 | if ((current_config->name != pipe_config->name) && \ | |
12403 | (current_config->alt_name != pipe_config->name)) { \ | |
cfb23ed6 | 12404 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
b95af8be VK |
12405 | "(expected %i or %i, found %i)\n", \ |
12406 | current_config->name, \ | |
12407 | current_config->alt_name, \ | |
12408 | pipe_config->name); \ | |
cfb23ed6 | 12409 | ret = false; \ |
b95af8be VK |
12410 | } |
12411 | ||
1bd1bd80 DV |
12412 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
12413 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
cfb23ed6 | 12414 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
12415 | "(expected %i, found %i)\n", \ |
12416 | current_config->name & (mask), \ | |
12417 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 12418 | ret = false; \ |
1bd1bd80 DV |
12419 | } |
12420 | ||
5e550656 VS |
12421 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
12422 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
cfb23ed6 | 12423 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
5e550656 VS |
12424 | "(expected %i, found %i)\n", \ |
12425 | current_config->name, \ | |
12426 | pipe_config->name); \ | |
cfb23ed6 | 12427 | ret = false; \ |
5e550656 VS |
12428 | } |
12429 | ||
bb760063 DV |
12430 | #define PIPE_CONF_QUIRK(quirk) \ |
12431 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
12432 | ||
eccb140b DV |
12433 | PIPE_CONF_CHECK_I(cpu_transcoder); |
12434 | ||
08a24034 DV |
12435 | PIPE_CONF_CHECK_I(has_pch_encoder); |
12436 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 12437 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 12438 | |
eb14cb74 | 12439 | PIPE_CONF_CHECK_I(has_dp_encoder); |
90a6b7b0 | 12440 | PIPE_CONF_CHECK_I(lane_count); |
b95af8be VK |
12441 | |
12442 | if (INTEL_INFO(dev)->gen < 8) { | |
cfb23ed6 ML |
12443 | PIPE_CONF_CHECK_M_N(dp_m_n); |
12444 | ||
12445 | PIPE_CONF_CHECK_I(has_drrs); | |
12446 | if (current_config->has_drrs) | |
12447 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
12448 | } else | |
12449 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 12450 | |
2d112de7 ACO |
12451 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
12452 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
12453 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
12454 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
12455 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
12456 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 12457 | |
2d112de7 ACO |
12458 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
12459 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
12460 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
12461 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
12462 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
12463 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 12464 | |
c93f54cf | 12465 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 12466 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 DV |
12467 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
12468 | IS_VALLEYVIEW(dev)) | |
12469 | PIPE_CONF_CHECK_I(limited_color_range); | |
e43823ec | 12470 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 12471 | |
9ed109a7 DV |
12472 | PIPE_CONF_CHECK_I(has_audio); |
12473 | ||
2d112de7 | 12474 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
12475 | DRM_MODE_FLAG_INTERLACE); |
12476 | ||
bb760063 | 12477 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 12478 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12479 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 12480 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12481 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 12482 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12483 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 12484 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
12485 | DRM_MODE_FLAG_NVSYNC); |
12486 | } | |
045ac3b5 | 12487 | |
333b8ca8 | 12488 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a DV |
12489 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
12490 | if (INTEL_INFO(dev)->gen < 4) | |
12491 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
333b8ca8 | 12492 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 12493 | |
bfd16b2a ML |
12494 | if (!adjust) { |
12495 | PIPE_CONF_CHECK_I(pipe_src_w); | |
12496 | PIPE_CONF_CHECK_I(pipe_src_h); | |
12497 | ||
12498 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
12499 | if (current_config->pch_pfit.enabled) { | |
12500 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
12501 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
12502 | } | |
2fa2fe9a | 12503 | |
7aefe2b5 ML |
12504 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
12505 | } | |
a1b2278e | 12506 | |
e59150dc JB |
12507 | /* BDW+ don't expose a synchronous way to read the state */ |
12508 | if (IS_HASWELL(dev)) | |
12509 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 12510 | |
282740f7 VS |
12511 | PIPE_CONF_CHECK_I(double_wide); |
12512 | ||
26804afd DV |
12513 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
12514 | ||
c0d43d62 | 12515 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 12516 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 12517 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
12518 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
12519 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 12520 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
3f4cd19f DL |
12521 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
12522 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
12523 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 12524 | |
42571aef VS |
12525 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
12526 | PIPE_CONF_CHECK_I(pipe_bpp); | |
12527 | ||
2d112de7 | 12528 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 12529 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 12530 | |
66e985c0 | 12531 | #undef PIPE_CONF_CHECK_X |
08a24034 | 12532 | #undef PIPE_CONF_CHECK_I |
b95af8be | 12533 | #undef PIPE_CONF_CHECK_I_ALT |
1bd1bd80 | 12534 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 12535 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 12536 | #undef PIPE_CONF_QUIRK |
cfb23ed6 | 12537 | #undef INTEL_ERR_OR_DBG_KMS |
88adfff1 | 12538 | |
cfb23ed6 | 12539 | return ret; |
0e8ffe1b DV |
12540 | } |
12541 | ||
08db6652 DL |
12542 | static void check_wm_state(struct drm_device *dev) |
12543 | { | |
12544 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12545 | struct skl_ddb_allocation hw_ddb, *sw_ddb; | |
12546 | struct intel_crtc *intel_crtc; | |
12547 | int plane; | |
12548 | ||
12549 | if (INTEL_INFO(dev)->gen < 9) | |
12550 | return; | |
12551 | ||
12552 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
12553 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
12554 | ||
12555 | for_each_intel_crtc(dev, intel_crtc) { | |
12556 | struct skl_ddb_entry *hw_entry, *sw_entry; | |
12557 | const enum pipe pipe = intel_crtc->pipe; | |
12558 | ||
12559 | if (!intel_crtc->active) | |
12560 | continue; | |
12561 | ||
12562 | /* planes */ | |
dd740780 | 12563 | for_each_plane(dev_priv, pipe, plane) { |
08db6652 DL |
12564 | hw_entry = &hw_ddb.plane[pipe][plane]; |
12565 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
12566 | ||
12567 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12568 | continue; | |
12569 | ||
12570 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " | |
12571 | "(expected (%u,%u), found (%u,%u))\n", | |
12572 | pipe_name(pipe), plane + 1, | |
12573 | sw_entry->start, sw_entry->end, | |
12574 | hw_entry->start, hw_entry->end); | |
12575 | } | |
12576 | ||
12577 | /* cursor */ | |
12578 | hw_entry = &hw_ddb.cursor[pipe]; | |
12579 | sw_entry = &sw_ddb->cursor[pipe]; | |
12580 | ||
12581 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12582 | continue; | |
12583 | ||
12584 | DRM_ERROR("mismatch in DDB state pipe %c cursor " | |
12585 | "(expected (%u,%u), found (%u,%u))\n", | |
12586 | pipe_name(pipe), | |
12587 | sw_entry->start, sw_entry->end, | |
12588 | hw_entry->start, hw_entry->end); | |
12589 | } | |
12590 | } | |
12591 | ||
91d1b4bd | 12592 | static void |
35dd3c64 ML |
12593 | check_connector_state(struct drm_device *dev, |
12594 | struct drm_atomic_state *old_state) | |
8af6cf88 | 12595 | { |
35dd3c64 ML |
12596 | struct drm_connector_state *old_conn_state; |
12597 | struct drm_connector *connector; | |
12598 | int i; | |
8af6cf88 | 12599 | |
35dd3c64 ML |
12600 | for_each_connector_in_state(old_state, connector, old_conn_state, i) { |
12601 | struct drm_encoder *encoder = connector->encoder; | |
12602 | struct drm_connector_state *state = connector->state; | |
ad3c558f | 12603 | |
8af6cf88 DV |
12604 | /* This also checks the encoder/connector hw state with the |
12605 | * ->get_hw_state callbacks. */ | |
35dd3c64 | 12606 | intel_connector_check_state(to_intel_connector(connector)); |
8af6cf88 | 12607 | |
ad3c558f | 12608 | I915_STATE_WARN(state->best_encoder != encoder, |
35dd3c64 | 12609 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 12610 | } |
91d1b4bd DV |
12611 | } |
12612 | ||
12613 | static void | |
12614 | check_encoder_state(struct drm_device *dev) | |
12615 | { | |
12616 | struct intel_encoder *encoder; | |
12617 | struct intel_connector *connector; | |
8af6cf88 | 12618 | |
b2784e15 | 12619 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 | 12620 | bool enabled = false; |
4d20cd86 | 12621 | enum pipe pipe; |
8af6cf88 DV |
12622 | |
12623 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
12624 | encoder->base.base.id, | |
8e329a03 | 12625 | encoder->base.name); |
8af6cf88 | 12626 | |
3a3371ff | 12627 | for_each_intel_connector(dev, connector) { |
4d20cd86 | 12628 | if (connector->base.state->best_encoder != &encoder->base) |
8af6cf88 DV |
12629 | continue; |
12630 | enabled = true; | |
ad3c558f ML |
12631 | |
12632 | I915_STATE_WARN(connector->base.state->crtc != | |
12633 | encoder->base.crtc, | |
12634 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 12635 | } |
0e32b39c | 12636 | |
e2c719b7 | 12637 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
12638 | "encoder's enabled state mismatch " |
12639 | "(expected %i, found %i)\n", | |
12640 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
12641 | |
12642 | if (!encoder->base.crtc) { | |
4d20cd86 | 12643 | bool active; |
7c60d198 | 12644 | |
4d20cd86 ML |
12645 | active = encoder->get_hw_state(encoder, &pipe); |
12646 | I915_STATE_WARN(active, | |
12647 | "encoder detached but still enabled on pipe %c.\n", | |
12648 | pipe_name(pipe)); | |
7c60d198 | 12649 | } |
8af6cf88 | 12650 | } |
91d1b4bd DV |
12651 | } |
12652 | ||
12653 | static void | |
4d20cd86 | 12654 | check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state) |
91d1b4bd | 12655 | { |
fbee40df | 12656 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd | 12657 | struct intel_encoder *encoder; |
4d20cd86 ML |
12658 | struct drm_crtc_state *old_crtc_state; |
12659 | struct drm_crtc *crtc; | |
12660 | int i; | |
8af6cf88 | 12661 | |
4d20cd86 ML |
12662 | for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) { |
12663 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12664 | struct intel_crtc_state *pipe_config, *sw_config; | |
7b89b8de | 12665 | bool active; |
8af6cf88 | 12666 | |
bfd16b2a ML |
12667 | if (!needs_modeset(crtc->state) && |
12668 | !to_intel_crtc_state(crtc->state)->update_pipe) | |
4d20cd86 | 12669 | continue; |
045ac3b5 | 12670 | |
4d20cd86 ML |
12671 | __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state); |
12672 | pipe_config = to_intel_crtc_state(old_crtc_state); | |
12673 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
12674 | pipe_config->base.crtc = crtc; | |
12675 | pipe_config->base.state = old_state; | |
8af6cf88 | 12676 | |
4d20cd86 ML |
12677 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
12678 | crtc->base.id); | |
8af6cf88 | 12679 | |
4d20cd86 ML |
12680 | active = dev_priv->display.get_pipe_config(intel_crtc, |
12681 | pipe_config); | |
d62cf62a | 12682 | |
b6b5d049 | 12683 | /* hw state is inconsistent with the pipe quirk */ |
4d20cd86 ML |
12684 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
12685 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
12686 | active = crtc->state->active; | |
6c49f241 | 12687 | |
4d20cd86 | 12688 | I915_STATE_WARN(crtc->state->active != active, |
0e8ffe1b | 12689 | "crtc active state doesn't match with hw state " |
4d20cd86 | 12690 | "(expected %i, found %i)\n", crtc->state->active, active); |
0e8ffe1b | 12691 | |
4d20cd86 | 12692 | I915_STATE_WARN(intel_crtc->active != crtc->state->active, |
53d9f4e9 | 12693 | "transitional active state does not match atomic hw state " |
4d20cd86 ML |
12694 | "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active); |
12695 | ||
12696 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
12697 | enum pipe pipe; | |
12698 | ||
12699 | active = encoder->get_hw_state(encoder, &pipe); | |
12700 | I915_STATE_WARN(active != crtc->state->active, | |
12701 | "[ENCODER:%i] active %i with crtc active %i\n", | |
12702 | encoder->base.base.id, active, crtc->state->active); | |
12703 | ||
12704 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, | |
12705 | "Encoder connected to wrong pipe %c\n", | |
12706 | pipe_name(pipe)); | |
12707 | ||
12708 | if (active) | |
12709 | encoder->get_config(encoder, pipe_config); | |
12710 | } | |
53d9f4e9 | 12711 | |
4d20cd86 | 12712 | if (!crtc->state->active) |
cfb23ed6 ML |
12713 | continue; |
12714 | ||
4d20cd86 ML |
12715 | sw_config = to_intel_crtc_state(crtc->state); |
12716 | if (!intel_pipe_config_compare(dev, sw_config, | |
12717 | pipe_config, false)) { | |
e2c719b7 | 12718 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); |
4d20cd86 | 12719 | intel_dump_pipe_config(intel_crtc, pipe_config, |
c0b03411 | 12720 | "[hw state]"); |
4d20cd86 | 12721 | intel_dump_pipe_config(intel_crtc, sw_config, |
c0b03411 DV |
12722 | "[sw state]"); |
12723 | } | |
8af6cf88 DV |
12724 | } |
12725 | } | |
12726 | ||
91d1b4bd DV |
12727 | static void |
12728 | check_shared_dpll_state(struct drm_device *dev) | |
12729 | { | |
fbee40df | 12730 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
12731 | struct intel_crtc *crtc; |
12732 | struct intel_dpll_hw_state dpll_hw_state; | |
12733 | int i; | |
5358901f DV |
12734 | |
12735 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
12736 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
12737 | int enabled_crtcs = 0, active_crtcs = 0; | |
12738 | bool active; | |
12739 | ||
12740 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
12741 | ||
12742 | DRM_DEBUG_KMS("%s\n", pll->name); | |
12743 | ||
12744 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
12745 | ||
e2c719b7 | 12746 | I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask), |
5358901f | 12747 | "more active pll users than references: %i vs %i\n", |
3e369b76 | 12748 | pll->active, hweight32(pll->config.crtc_mask)); |
e2c719b7 | 12749 | I915_STATE_WARN(pll->active && !pll->on, |
5358901f | 12750 | "pll in active use but not on in sw tracking\n"); |
e2c719b7 | 12751 | I915_STATE_WARN(pll->on && !pll->active, |
35c95375 | 12752 | "pll in on but not on in use in sw tracking\n"); |
e2c719b7 | 12753 | I915_STATE_WARN(pll->on != active, |
5358901f DV |
12754 | "pll on state mismatch (expected %i, found %i)\n", |
12755 | pll->on, active); | |
12756 | ||
d3fcc808 | 12757 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 12758 | if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll) |
5358901f DV |
12759 | enabled_crtcs++; |
12760 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
12761 | active_crtcs++; | |
12762 | } | |
e2c719b7 | 12763 | I915_STATE_WARN(pll->active != active_crtcs, |
5358901f DV |
12764 | "pll active crtcs mismatch (expected %i, found %i)\n", |
12765 | pll->active, active_crtcs); | |
e2c719b7 | 12766 | I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs, |
5358901f | 12767 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
3e369b76 | 12768 | hweight32(pll->config.crtc_mask), enabled_crtcs); |
66e985c0 | 12769 | |
e2c719b7 | 12770 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state, |
66e985c0 DV |
12771 | sizeof(dpll_hw_state)), |
12772 | "pll hw state mismatch\n"); | |
5358901f | 12773 | } |
8af6cf88 DV |
12774 | } |
12775 | ||
ee165b1a ML |
12776 | static void |
12777 | intel_modeset_check_state(struct drm_device *dev, | |
12778 | struct drm_atomic_state *old_state) | |
91d1b4bd | 12779 | { |
08db6652 | 12780 | check_wm_state(dev); |
35dd3c64 | 12781 | check_connector_state(dev, old_state); |
91d1b4bd | 12782 | check_encoder_state(dev); |
4d20cd86 | 12783 | check_crtc_state(dev, old_state); |
91d1b4bd DV |
12784 | check_shared_dpll_state(dev); |
12785 | } | |
12786 | ||
5cec258b | 12787 | void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config, |
18442d08 VS |
12788 | int dotclock) |
12789 | { | |
12790 | /* | |
12791 | * FDI already provided one idea for the dotclock. | |
12792 | * Yell if the encoder disagrees. | |
12793 | */ | |
2d112de7 | 12794 | WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock), |
18442d08 | 12795 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
2d112de7 | 12796 | pipe_config->base.adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
12797 | } |
12798 | ||
80715b2f VS |
12799 | static void update_scanline_offset(struct intel_crtc *crtc) |
12800 | { | |
12801 | struct drm_device *dev = crtc->base.dev; | |
12802 | ||
12803 | /* | |
12804 | * The scanline counter increments at the leading edge of hsync. | |
12805 | * | |
12806 | * On most platforms it starts counting from vtotal-1 on the | |
12807 | * first active line. That means the scanline counter value is | |
12808 | * always one less than what we would expect. Ie. just after | |
12809 | * start of vblank, which also occurs at start of hsync (on the | |
12810 | * last active line), the scanline counter will read vblank_start-1. | |
12811 | * | |
12812 | * On gen2 the scanline counter starts counting from 1 instead | |
12813 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
12814 | * to keep the value positive), instead of adding one. | |
12815 | * | |
12816 | * On HSW+ the behaviour of the scanline counter depends on the output | |
12817 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
12818 | * there's an extra 1 line difference. So we need to add two instead of | |
12819 | * one to the value. | |
12820 | */ | |
12821 | if (IS_GEN2(dev)) { | |
124abe07 | 12822 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
12823 | int vtotal; |
12824 | ||
124abe07 VS |
12825 | vtotal = adjusted_mode->crtc_vtotal; |
12826 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
12827 | vtotal /= 2; |
12828 | ||
12829 | crtc->scanline_offset = vtotal - 1; | |
12830 | } else if (HAS_DDI(dev) && | |
409ee761 | 12831 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
12832 | crtc->scanline_offset = 2; |
12833 | } else | |
12834 | crtc->scanline_offset = 1; | |
12835 | } | |
12836 | ||
ad421372 | 12837 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 12838 | { |
225da59b | 12839 | struct drm_device *dev = state->dev; |
ed6739ef | 12840 | struct drm_i915_private *dev_priv = to_i915(dev); |
ad421372 | 12841 | struct intel_shared_dpll_config *shared_dpll = NULL; |
ed6739ef | 12842 | struct intel_crtc *intel_crtc; |
0a9ab303 ACO |
12843 | struct intel_crtc_state *intel_crtc_state; |
12844 | struct drm_crtc *crtc; | |
12845 | struct drm_crtc_state *crtc_state; | |
0a9ab303 | 12846 | int i; |
ed6739ef ACO |
12847 | |
12848 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 12849 | return; |
ed6739ef | 12850 | |
0a9ab303 | 12851 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
ad421372 ML |
12852 | int dpll; |
12853 | ||
0a9ab303 | 12854 | intel_crtc = to_intel_crtc(crtc); |
4978cc93 | 12855 | intel_crtc_state = to_intel_crtc_state(crtc_state); |
ad421372 | 12856 | dpll = intel_crtc_state->shared_dpll; |
0a9ab303 | 12857 | |
ad421372 | 12858 | if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE) |
225da59b ACO |
12859 | continue; |
12860 | ||
ad421372 | 12861 | intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE; |
0a9ab303 | 12862 | |
ad421372 ML |
12863 | if (!shared_dpll) |
12864 | shared_dpll = intel_atomic_get_shared_dpll_state(state); | |
ed6739ef | 12865 | |
ad421372 ML |
12866 | shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe); |
12867 | } | |
ed6739ef ACO |
12868 | } |
12869 | ||
99d736a2 ML |
12870 | /* |
12871 | * This implements the workaround described in the "notes" section of the mode | |
12872 | * set sequence documentation. When going from no pipes or single pipe to | |
12873 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
12874 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
12875 | */ | |
12876 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
12877 | { | |
12878 | struct drm_crtc_state *crtc_state; | |
12879 | struct intel_crtc *intel_crtc; | |
12880 | struct drm_crtc *crtc; | |
12881 | struct intel_crtc_state *first_crtc_state = NULL; | |
12882 | struct intel_crtc_state *other_crtc_state = NULL; | |
12883 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
12884 | int i; | |
12885 | ||
12886 | /* look at all crtc's that are going to be enabled in during modeset */ | |
12887 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
12888 | intel_crtc = to_intel_crtc(crtc); | |
12889 | ||
12890 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
12891 | continue; | |
12892 | ||
12893 | if (first_crtc_state) { | |
12894 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
12895 | break; | |
12896 | } else { | |
12897 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
12898 | first_pipe = intel_crtc->pipe; | |
12899 | } | |
12900 | } | |
12901 | ||
12902 | /* No workaround needed? */ | |
12903 | if (!first_crtc_state) | |
12904 | return 0; | |
12905 | ||
12906 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
12907 | for_each_intel_crtc(state->dev, intel_crtc) { | |
12908 | struct intel_crtc_state *pipe_config; | |
12909 | ||
12910 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
12911 | if (IS_ERR(pipe_config)) | |
12912 | return PTR_ERR(pipe_config); | |
12913 | ||
12914 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
12915 | ||
12916 | if (!pipe_config->base.active || | |
12917 | needs_modeset(&pipe_config->base)) | |
12918 | continue; | |
12919 | ||
12920 | /* 2 or more enabled crtcs means no need for w/a */ | |
12921 | if (enabled_pipe != INVALID_PIPE) | |
12922 | return 0; | |
12923 | ||
12924 | enabled_pipe = intel_crtc->pipe; | |
12925 | } | |
12926 | ||
12927 | if (enabled_pipe != INVALID_PIPE) | |
12928 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
12929 | else if (other_crtc_state) | |
12930 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
12931 | ||
12932 | return 0; | |
12933 | } | |
12934 | ||
27c329ed ML |
12935 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
12936 | { | |
12937 | struct drm_crtc *crtc; | |
12938 | struct drm_crtc_state *crtc_state; | |
12939 | int ret = 0; | |
12940 | ||
12941 | /* add all active pipes to the state */ | |
12942 | for_each_crtc(state->dev, crtc) { | |
12943 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
12944 | if (IS_ERR(crtc_state)) | |
12945 | return PTR_ERR(crtc_state); | |
12946 | ||
12947 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
12948 | continue; | |
12949 | ||
12950 | crtc_state->mode_changed = true; | |
12951 | ||
12952 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
12953 | if (ret) | |
12954 | break; | |
12955 | ||
12956 | ret = drm_atomic_add_affected_planes(state, crtc); | |
12957 | if (ret) | |
12958 | break; | |
12959 | } | |
12960 | ||
12961 | return ret; | |
12962 | } | |
12963 | ||
c347a676 | 12964 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd ACO |
12965 | { |
12966 | struct drm_device *dev = state->dev; | |
27c329ed | 12967 | struct drm_i915_private *dev_priv = dev->dev_private; |
054518dd ACO |
12968 | int ret; |
12969 | ||
b359283a ML |
12970 | if (!check_digital_port_conflicts(state)) { |
12971 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
12972 | return -EINVAL; | |
12973 | } | |
12974 | ||
054518dd ACO |
12975 | /* |
12976 | * See if the config requires any additional preparation, e.g. | |
12977 | * to adjust global state with pipes off. We need to do this | |
12978 | * here so we can get the modeset_pipe updated config for the new | |
12979 | * mode set on this crtc. For other crtcs we need to use the | |
12980 | * adjusted_mode bits in the crtc directly. | |
12981 | */ | |
27c329ed ML |
12982 | if (dev_priv->display.modeset_calc_cdclk) { |
12983 | unsigned int cdclk; | |
b432e5cf | 12984 | |
27c329ed ML |
12985 | ret = dev_priv->display.modeset_calc_cdclk(state); |
12986 | ||
12987 | cdclk = to_intel_atomic_state(state)->cdclk; | |
12988 | if (!ret && cdclk != dev_priv->cdclk_freq) | |
12989 | ret = intel_modeset_all_pipes(state); | |
12990 | ||
12991 | if (ret < 0) | |
054518dd | 12992 | return ret; |
27c329ed ML |
12993 | } else |
12994 | to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq; | |
054518dd | 12995 | |
ad421372 | 12996 | intel_modeset_clear_plls(state); |
054518dd | 12997 | |
99d736a2 | 12998 | if (IS_HASWELL(dev)) |
ad421372 | 12999 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 13000 | |
ad421372 | 13001 | return 0; |
c347a676 ACO |
13002 | } |
13003 | ||
74c090b1 ML |
13004 | /** |
13005 | * intel_atomic_check - validate state object | |
13006 | * @dev: drm device | |
13007 | * @state: state to validate | |
13008 | */ | |
13009 | static int intel_atomic_check(struct drm_device *dev, | |
13010 | struct drm_atomic_state *state) | |
c347a676 ACO |
13011 | { |
13012 | struct drm_crtc *crtc; | |
13013 | struct drm_crtc_state *crtc_state; | |
13014 | int ret, i; | |
61333b60 | 13015 | bool any_ms = false; |
c347a676 | 13016 | |
74c090b1 | 13017 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
13018 | if (ret) |
13019 | return ret; | |
13020 | ||
c347a676 | 13021 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
cfb23ed6 ML |
13022 | struct intel_crtc_state *pipe_config = |
13023 | to_intel_crtc_state(crtc_state); | |
1ed51de9 DV |
13024 | |
13025 | /* Catch I915_MODE_FLAG_INHERITED */ | |
13026 | if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) | |
13027 | crtc_state->mode_changed = true; | |
cfb23ed6 | 13028 | |
61333b60 ML |
13029 | if (!crtc_state->enable) { |
13030 | if (needs_modeset(crtc_state)) | |
13031 | any_ms = true; | |
c347a676 | 13032 | continue; |
61333b60 | 13033 | } |
c347a676 | 13034 | |
26495481 | 13035 | if (!needs_modeset(crtc_state)) |
cfb23ed6 ML |
13036 | continue; |
13037 | ||
26495481 DV |
13038 | /* FIXME: For only active_changed we shouldn't need to do any |
13039 | * state recomputation at all. */ | |
13040 | ||
1ed51de9 DV |
13041 | ret = drm_atomic_add_affected_connectors(state, crtc); |
13042 | if (ret) | |
13043 | return ret; | |
b359283a | 13044 | |
cfb23ed6 | 13045 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
c347a676 ACO |
13046 | if (ret) |
13047 | return ret; | |
13048 | ||
6764e9f8 | 13049 | if (intel_pipe_config_compare(state->dev, |
cfb23ed6 | 13050 | to_intel_crtc_state(crtc->state), |
1ed51de9 | 13051 | pipe_config, true)) { |
26495481 | 13052 | crtc_state->mode_changed = false; |
bfd16b2a | 13053 | to_intel_crtc_state(crtc_state)->update_pipe = true; |
26495481 DV |
13054 | } |
13055 | ||
13056 | if (needs_modeset(crtc_state)) { | |
13057 | any_ms = true; | |
cfb23ed6 ML |
13058 | |
13059 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13060 | if (ret) | |
13061 | return ret; | |
13062 | } | |
61333b60 | 13063 | |
26495481 DV |
13064 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
13065 | needs_modeset(crtc_state) ? | |
13066 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
13067 | } |
13068 | ||
61333b60 ML |
13069 | if (any_ms) { |
13070 | ret = intel_modeset_checks(state); | |
13071 | ||
13072 | if (ret) | |
13073 | return ret; | |
27c329ed ML |
13074 | } else |
13075 | to_intel_atomic_state(state)->cdclk = | |
13076 | to_i915(state->dev)->cdclk_freq; | |
c347a676 ACO |
13077 | |
13078 | return drm_atomic_helper_check_planes(state->dev, state); | |
054518dd ACO |
13079 | } |
13080 | ||
74c090b1 ML |
13081 | /** |
13082 | * intel_atomic_commit - commit validated state object | |
13083 | * @dev: DRM device | |
13084 | * @state: the top-level driver state object | |
13085 | * @async: asynchronous commit | |
13086 | * | |
13087 | * This function commits a top-level state object that has been validated | |
13088 | * with drm_atomic_helper_check(). | |
13089 | * | |
13090 | * FIXME: Atomic modeset support for i915 is not yet complete. At the moment | |
13091 | * we can only handle plane-related operations and do not yet support | |
13092 | * asynchronous commit. | |
13093 | * | |
13094 | * RETURNS | |
13095 | * Zero for success or -errno. | |
13096 | */ | |
13097 | static int intel_atomic_commit(struct drm_device *dev, | |
13098 | struct drm_atomic_state *state, | |
13099 | bool async) | |
a6778b3c | 13100 | { |
fbee40df | 13101 | struct drm_i915_private *dev_priv = dev->dev_private; |
0a9ab303 ACO |
13102 | struct drm_crtc *crtc; |
13103 | struct drm_crtc_state *crtc_state; | |
c0c36b94 | 13104 | int ret = 0; |
0a9ab303 | 13105 | int i; |
61333b60 | 13106 | bool any_ms = false; |
a6778b3c | 13107 | |
74c090b1 ML |
13108 | if (async) { |
13109 | DRM_DEBUG_KMS("i915 does not yet support async commit\n"); | |
13110 | return -EINVAL; | |
13111 | } | |
13112 | ||
d4afb8cc ACO |
13113 | ret = drm_atomic_helper_prepare_planes(dev, state); |
13114 | if (ret) | |
13115 | return ret; | |
13116 | ||
1c5e19f8 ML |
13117 | drm_atomic_helper_swap_state(dev, state); |
13118 | ||
0a9ab303 | 13119 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
a539205a ML |
13120 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13121 | ||
61333b60 ML |
13122 | if (!needs_modeset(crtc->state)) |
13123 | continue; | |
13124 | ||
13125 | any_ms = true; | |
a539205a | 13126 | intel_pre_plane_update(intel_crtc); |
460da916 | 13127 | |
a539205a ML |
13128 | if (crtc_state->active) { |
13129 | intel_crtc_disable_planes(crtc, crtc_state->plane_mask); | |
13130 | dev_priv->display.crtc_disable(crtc); | |
eddfcbcd ML |
13131 | intel_crtc->active = false; |
13132 | intel_disable_shared_dpll(intel_crtc); | |
a539205a | 13133 | } |
b8cecdf5 | 13134 | } |
7758a113 | 13135 | |
ea9d758d DV |
13136 | /* Only after disabling all output pipelines that will be changed can we |
13137 | * update the the output configuration. */ | |
4740b0f2 | 13138 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 13139 | |
4740b0f2 ML |
13140 | if (any_ms) { |
13141 | intel_shared_dpll_commit(state); | |
13142 | ||
13143 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); | |
61333b60 | 13144 | modeset_update_crtc_power_domains(state); |
4740b0f2 | 13145 | } |
47fab737 | 13146 | |
a6778b3c | 13147 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
0a9ab303 | 13148 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
f6ac4b2a ML |
13149 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13150 | bool modeset = needs_modeset(crtc->state); | |
bfd16b2a ML |
13151 | bool update_pipe = !modeset && |
13152 | to_intel_crtc_state(crtc->state)->update_pipe; | |
13153 | unsigned long put_domains = 0; | |
f6ac4b2a ML |
13154 | |
13155 | if (modeset && crtc->state->active) { | |
a539205a ML |
13156 | update_scanline_offset(to_intel_crtc(crtc)); |
13157 | dev_priv->display.crtc_enable(crtc); | |
13158 | } | |
80715b2f | 13159 | |
bfd16b2a ML |
13160 | if (update_pipe) { |
13161 | put_domains = modeset_get_crtc_power_domains(crtc); | |
13162 | ||
13163 | /* make sure intel_modeset_check_state runs */ | |
13164 | any_ms = true; | |
13165 | } | |
13166 | ||
f6ac4b2a ML |
13167 | if (!modeset) |
13168 | intel_pre_plane_update(intel_crtc); | |
13169 | ||
a539205a | 13170 | drm_atomic_helper_commit_planes_on_crtc(crtc_state); |
bfd16b2a ML |
13171 | |
13172 | if (put_domains) | |
13173 | modeset_put_power_domains(dev_priv, put_domains); | |
13174 | ||
f6ac4b2a | 13175 | intel_post_plane_update(intel_crtc); |
80715b2f | 13176 | } |
a6778b3c | 13177 | |
a6778b3c | 13178 | /* FIXME: add subpixel order */ |
83a57153 | 13179 | |
74c090b1 | 13180 | drm_atomic_helper_wait_for_vblanks(dev, state); |
d4afb8cc | 13181 | drm_atomic_helper_cleanup_planes(dev, state); |
2bfb4627 | 13182 | |
74c090b1 | 13183 | if (any_ms) |
ee165b1a ML |
13184 | intel_modeset_check_state(dev, state); |
13185 | ||
13186 | drm_atomic_state_free(state); | |
f30da187 | 13187 | |
74c090b1 | 13188 | return 0; |
7f27126e JB |
13189 | } |
13190 | ||
c0c36b94 CW |
13191 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
13192 | { | |
83a57153 ACO |
13193 | struct drm_device *dev = crtc->dev; |
13194 | struct drm_atomic_state *state; | |
e694eb02 | 13195 | struct drm_crtc_state *crtc_state; |
2bfb4627 | 13196 | int ret; |
83a57153 ACO |
13197 | |
13198 | state = drm_atomic_state_alloc(dev); | |
13199 | if (!state) { | |
e694eb02 | 13200 | DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory", |
83a57153 ACO |
13201 | crtc->base.id); |
13202 | return; | |
13203 | } | |
13204 | ||
e694eb02 | 13205 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
83a57153 | 13206 | |
e694eb02 ML |
13207 | retry: |
13208 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13209 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
13210 | if (!ret) { | |
13211 | if (!crtc_state->active) | |
13212 | goto out; | |
83a57153 | 13213 | |
e694eb02 | 13214 | crtc_state->mode_changed = true; |
74c090b1 | 13215 | ret = drm_atomic_commit(state); |
83a57153 ACO |
13216 | } |
13217 | ||
e694eb02 ML |
13218 | if (ret == -EDEADLK) { |
13219 | drm_atomic_state_clear(state); | |
13220 | drm_modeset_backoff(state->acquire_ctx); | |
13221 | goto retry; | |
4ed9fb37 | 13222 | } |
4be07317 | 13223 | |
2bfb4627 | 13224 | if (ret) |
e694eb02 | 13225 | out: |
2bfb4627 | 13226 | drm_atomic_state_free(state); |
c0c36b94 CW |
13227 | } |
13228 | ||
25c5b266 DV |
13229 | #undef for_each_intel_crtc_masked |
13230 | ||
f6e5b160 | 13231 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
f6e5b160 | 13232 | .gamma_set = intel_crtc_gamma_set, |
74c090b1 | 13233 | .set_config = drm_atomic_helper_set_config, |
f6e5b160 CW |
13234 | .destroy = intel_crtc_destroy, |
13235 | .page_flip = intel_crtc_page_flip, | |
1356837e MR |
13236 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
13237 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
13238 | }; |
13239 | ||
5358901f DV |
13240 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
13241 | struct intel_shared_dpll *pll, | |
13242 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 13243 | { |
5358901f | 13244 | uint32_t val; |
ee7b9f93 | 13245 | |
f458ebbc | 13246 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
bd2bb1b9 PZ |
13247 | return false; |
13248 | ||
5358901f | 13249 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
13250 | hw_state->dpll = val; |
13251 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
13252 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
13253 | |
13254 | return val & DPLL_VCO_ENABLE; | |
13255 | } | |
13256 | ||
15bdd4cf DV |
13257 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
13258 | struct intel_shared_dpll *pll) | |
13259 | { | |
3e369b76 ACO |
13260 | I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0); |
13261 | I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1); | |
15bdd4cf DV |
13262 | } |
13263 | ||
e7b903d2 DV |
13264 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
13265 | struct intel_shared_dpll *pll) | |
13266 | { | |
e7b903d2 | 13267 | /* PCH refclock must be enabled first */ |
89eff4be | 13268 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 13269 | |
3e369b76 | 13270 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf DV |
13271 | |
13272 | /* Wait for the clocks to stabilize. */ | |
13273 | POSTING_READ(PCH_DPLL(pll->id)); | |
13274 | udelay(150); | |
13275 | ||
13276 | /* The pixel multiplier can only be updated once the | |
13277 | * DPLL is enabled and the clocks are stable. | |
13278 | * | |
13279 | * So write it again. | |
13280 | */ | |
3e369b76 | 13281 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf | 13282 | POSTING_READ(PCH_DPLL(pll->id)); |
e7b903d2 DV |
13283 | udelay(200); |
13284 | } | |
13285 | ||
13286 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
13287 | struct intel_shared_dpll *pll) | |
13288 | { | |
13289 | struct drm_device *dev = dev_priv->dev; | |
13290 | struct intel_crtc *crtc; | |
e7b903d2 DV |
13291 | |
13292 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 13293 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
13294 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
13295 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
13296 | } |
13297 | ||
15bdd4cf DV |
13298 | I915_WRITE(PCH_DPLL(pll->id), 0); |
13299 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
13300 | udelay(200); |
13301 | } | |
13302 | ||
46edb027 DV |
13303 | static char *ibx_pch_dpll_names[] = { |
13304 | "PCH DPLL A", | |
13305 | "PCH DPLL B", | |
13306 | }; | |
13307 | ||
7c74ade1 | 13308 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 13309 | { |
e7b903d2 | 13310 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
13311 | int i; |
13312 | ||
7c74ade1 | 13313 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 13314 | |
e72f9fbf | 13315 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
13316 | dev_priv->shared_dplls[i].id = i; |
13317 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 13318 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
13319 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
13320 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
13321 | dev_priv->shared_dplls[i].get_hw_state = |
13322 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
13323 | } |
13324 | } | |
13325 | ||
7c74ade1 DV |
13326 | static void intel_shared_dpll_init(struct drm_device *dev) |
13327 | { | |
e7b903d2 | 13328 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 | 13329 | |
b6283055 VS |
13330 | intel_update_cdclk(dev); |
13331 | ||
9cd86933 DV |
13332 | if (HAS_DDI(dev)) |
13333 | intel_ddi_pll_init(dev); | |
13334 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7c74ade1 DV |
13335 | ibx_pch_dpll_init(dev); |
13336 | else | |
13337 | dev_priv->num_shared_dpll = 0; | |
13338 | ||
13339 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
13340 | } |
13341 | ||
6beb8c23 MR |
13342 | /** |
13343 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
13344 | * @plane: drm plane to prepare for | |
13345 | * @fb: framebuffer to prepare for presentation | |
13346 | * | |
13347 | * Prepares a framebuffer for usage on a display plane. Generally this | |
13348 | * involves pinning the underlying object and updating the frontbuffer tracking | |
13349 | * bits. Some older platforms need special physical address handling for | |
13350 | * cursor planes. | |
13351 | * | |
13352 | * Returns 0 on success, negative error code on failure. | |
13353 | */ | |
13354 | int | |
13355 | intel_prepare_plane_fb(struct drm_plane *plane, | |
d136dfee | 13356 | const struct drm_plane_state *new_state) |
465c120c MR |
13357 | { |
13358 | struct drm_device *dev = plane->dev; | |
844f9111 | 13359 | struct drm_framebuffer *fb = new_state->fb; |
6beb8c23 | 13360 | struct intel_plane *intel_plane = to_intel_plane(plane); |
6beb8c23 MR |
13361 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
13362 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); | |
6beb8c23 | 13363 | int ret = 0; |
465c120c | 13364 | |
ea2c67bb | 13365 | if (!obj) |
465c120c MR |
13366 | return 0; |
13367 | ||
6beb8c23 | 13368 | mutex_lock(&dev->struct_mutex); |
465c120c | 13369 | |
6beb8c23 MR |
13370 | if (plane->type == DRM_PLANE_TYPE_CURSOR && |
13371 | INTEL_INFO(dev)->cursor_needs_physical) { | |
13372 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
13373 | ret = i915_gem_object_attach_phys(obj, align); | |
13374 | if (ret) | |
13375 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
13376 | } else { | |
91af127f | 13377 | ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL); |
6beb8c23 | 13378 | } |
465c120c | 13379 | |
6beb8c23 | 13380 | if (ret == 0) |
a9ff8714 | 13381 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); |
fdd508a6 | 13382 | |
4c34574f | 13383 | mutex_unlock(&dev->struct_mutex); |
465c120c | 13384 | |
6beb8c23 MR |
13385 | return ret; |
13386 | } | |
13387 | ||
38f3ce3a MR |
13388 | /** |
13389 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
13390 | * @plane: drm plane to clean up for | |
13391 | * @fb: old framebuffer that was on plane | |
13392 | * | |
13393 | * Cleans up a framebuffer that has just been removed from a plane. | |
13394 | */ | |
13395 | void | |
13396 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
d136dfee | 13397 | const struct drm_plane_state *old_state) |
38f3ce3a MR |
13398 | { |
13399 | struct drm_device *dev = plane->dev; | |
844f9111 | 13400 | struct drm_i915_gem_object *obj = intel_fb_obj(old_state->fb); |
38f3ce3a | 13401 | |
844f9111 | 13402 | if (!obj) |
38f3ce3a MR |
13403 | return; |
13404 | ||
13405 | if (plane->type != DRM_PLANE_TYPE_CURSOR || | |
13406 | !INTEL_INFO(dev)->cursor_needs_physical) { | |
13407 | mutex_lock(&dev->struct_mutex); | |
844f9111 | 13408 | intel_unpin_fb_obj(old_state->fb, old_state); |
38f3ce3a MR |
13409 | mutex_unlock(&dev->struct_mutex); |
13410 | } | |
465c120c MR |
13411 | } |
13412 | ||
6156a456 CK |
13413 | int |
13414 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
13415 | { | |
13416 | int max_scale; | |
13417 | struct drm_device *dev; | |
13418 | struct drm_i915_private *dev_priv; | |
13419 | int crtc_clock, cdclk; | |
13420 | ||
13421 | if (!intel_crtc || !crtc_state) | |
13422 | return DRM_PLANE_HELPER_NO_SCALING; | |
13423 | ||
13424 | dev = intel_crtc->base.dev; | |
13425 | dev_priv = dev->dev_private; | |
13426 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; | |
27c329ed | 13427 | cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; |
6156a456 CK |
13428 | |
13429 | if (!crtc_clock || !cdclk) | |
13430 | return DRM_PLANE_HELPER_NO_SCALING; | |
13431 | ||
13432 | /* | |
13433 | * skl max scale is lower of: | |
13434 | * close to 3 but not 3, -1 is for that purpose | |
13435 | * or | |
13436 | * cdclk/crtc_clock | |
13437 | */ | |
13438 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); | |
13439 | ||
13440 | return max_scale; | |
13441 | } | |
13442 | ||
465c120c | 13443 | static int |
3c692a41 | 13444 | intel_check_primary_plane(struct drm_plane *plane, |
061e4b8d | 13445 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
13446 | struct intel_plane_state *state) |
13447 | { | |
2b875c22 MR |
13448 | struct drm_crtc *crtc = state->base.crtc; |
13449 | struct drm_framebuffer *fb = state->base.fb; | |
6156a456 | 13450 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
13451 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
13452 | bool can_position = false; | |
465c120c | 13453 | |
061e4b8d ML |
13454 | /* use scaler when colorkey is not required */ |
13455 | if (INTEL_INFO(plane->dev)->gen >= 9 && | |
818ed961 | 13456 | state->ckey.flags == I915_SET_COLORKEY_NONE) { |
061e4b8d ML |
13457 | min_scale = 1; |
13458 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
d8106366 | 13459 | can_position = true; |
6156a456 | 13460 | } |
d8106366 | 13461 | |
061e4b8d ML |
13462 | return drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
13463 | &state->dst, &state->clip, | |
da20eabd ML |
13464 | min_scale, max_scale, |
13465 | can_position, true, | |
13466 | &state->visible); | |
14af293f GP |
13467 | } |
13468 | ||
13469 | static void | |
13470 | intel_commit_primary_plane(struct drm_plane *plane, | |
13471 | struct intel_plane_state *state) | |
13472 | { | |
2b875c22 MR |
13473 | struct drm_crtc *crtc = state->base.crtc; |
13474 | struct drm_framebuffer *fb = state->base.fb; | |
13475 | struct drm_device *dev = plane->dev; | |
14af293f | 13476 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea2c67bb | 13477 | struct intel_crtc *intel_crtc; |
14af293f GP |
13478 | struct drm_rect *src = &state->src; |
13479 | ||
ea2c67bb MR |
13480 | crtc = crtc ? crtc : plane->crtc; |
13481 | intel_crtc = to_intel_crtc(crtc); | |
cf4c7c12 MR |
13482 | |
13483 | plane->fb = fb; | |
9dc806fc MR |
13484 | crtc->x = src->x1 >> 16; |
13485 | crtc->y = src->y1 >> 16; | |
ccc759dc | 13486 | |
a539205a | 13487 | if (!crtc->state->active) |
302d19ac | 13488 | return; |
465c120c | 13489 | |
d4b08630 ML |
13490 | dev_priv->display.update_primary_plane(crtc, fb, |
13491 | state->src.x1 >> 16, | |
13492 | state->src.y1 >> 16); | |
465c120c MR |
13493 | } |
13494 | ||
a8ad0d8e ML |
13495 | static void |
13496 | intel_disable_primary_plane(struct drm_plane *plane, | |
7fabf5ef | 13497 | struct drm_crtc *crtc) |
a8ad0d8e ML |
13498 | { |
13499 | struct drm_device *dev = plane->dev; | |
13500 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13501 | ||
a8ad0d8e ML |
13502 | dev_priv->display.update_primary_plane(crtc, NULL, 0, 0); |
13503 | } | |
13504 | ||
613d2b27 ML |
13505 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
13506 | struct drm_crtc_state *old_crtc_state) | |
3c692a41 | 13507 | { |
32b7eeec | 13508 | struct drm_device *dev = crtc->dev; |
3c692a41 | 13509 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
bfd16b2a ML |
13510 | struct intel_crtc_state *old_intel_state = |
13511 | to_intel_crtc_state(old_crtc_state); | |
13512 | bool modeset = needs_modeset(crtc->state); | |
3c692a41 | 13513 | |
f015c551 | 13514 | if (intel_crtc->atomic.update_wm_pre) |
32b7eeec | 13515 | intel_update_watermarks(crtc); |
3c692a41 | 13516 | |
c34c9ee4 | 13517 | /* Perform vblank evasion around commit operation */ |
a539205a | 13518 | if (crtc->state->active) |
34e0adbb | 13519 | intel_pipe_update_start(intel_crtc); |
0583236e | 13520 | |
bfd16b2a ML |
13521 | if (modeset) |
13522 | return; | |
13523 | ||
13524 | if (to_intel_crtc_state(crtc->state)->update_pipe) | |
13525 | intel_update_pipe_config(intel_crtc, old_intel_state); | |
13526 | else if (INTEL_INFO(dev)->gen >= 9) | |
0583236e | 13527 | skl_detach_scalers(intel_crtc); |
32b7eeec MR |
13528 | } |
13529 | ||
613d2b27 ML |
13530 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, |
13531 | struct drm_crtc_state *old_crtc_state) | |
32b7eeec | 13532 | { |
32b7eeec | 13533 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
32b7eeec | 13534 | |
8f539a83 | 13535 | if (crtc->state->active) |
34e0adbb | 13536 | intel_pipe_update_end(intel_crtc); |
3c692a41 GP |
13537 | } |
13538 | ||
cf4c7c12 | 13539 | /** |
4a3b8769 MR |
13540 | * intel_plane_destroy - destroy a plane |
13541 | * @plane: plane to destroy | |
cf4c7c12 | 13542 | * |
4a3b8769 MR |
13543 | * Common destruction function for all types of planes (primary, cursor, |
13544 | * sprite). | |
cf4c7c12 | 13545 | */ |
4a3b8769 | 13546 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c MR |
13547 | { |
13548 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
13549 | drm_plane_cleanup(plane); | |
13550 | kfree(intel_plane); | |
13551 | } | |
13552 | ||
65a3fea0 | 13553 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
13554 | .update_plane = drm_atomic_helper_update_plane, |
13555 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 13556 | .destroy = intel_plane_destroy, |
c196e1d6 | 13557 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
13558 | .atomic_get_property = intel_plane_atomic_get_property, |
13559 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
13560 | .atomic_duplicate_state = intel_plane_duplicate_state, |
13561 | .atomic_destroy_state = intel_plane_destroy_state, | |
13562 | ||
465c120c MR |
13563 | }; |
13564 | ||
13565 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
13566 | int pipe) | |
13567 | { | |
13568 | struct intel_plane *primary; | |
8e7d688b | 13569 | struct intel_plane_state *state; |
465c120c | 13570 | const uint32_t *intel_primary_formats; |
45e3743a | 13571 | unsigned int num_formats; |
465c120c MR |
13572 | |
13573 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
13574 | if (primary == NULL) | |
13575 | return NULL; | |
13576 | ||
8e7d688b MR |
13577 | state = intel_create_plane_state(&primary->base); |
13578 | if (!state) { | |
ea2c67bb MR |
13579 | kfree(primary); |
13580 | return NULL; | |
13581 | } | |
8e7d688b | 13582 | primary->base.state = &state->base; |
ea2c67bb | 13583 | |
465c120c MR |
13584 | primary->can_scale = false; |
13585 | primary->max_downscale = 1; | |
6156a456 CK |
13586 | if (INTEL_INFO(dev)->gen >= 9) { |
13587 | primary->can_scale = true; | |
af99ceda | 13588 | state->scaler_id = -1; |
6156a456 | 13589 | } |
465c120c MR |
13590 | primary->pipe = pipe; |
13591 | primary->plane = pipe; | |
a9ff8714 | 13592 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 MR |
13593 | primary->check_plane = intel_check_primary_plane; |
13594 | primary->commit_plane = intel_commit_primary_plane; | |
a8ad0d8e | 13595 | primary->disable_plane = intel_disable_primary_plane; |
465c120c MR |
13596 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
13597 | primary->plane = !pipe; | |
13598 | ||
6c0fd451 DL |
13599 | if (INTEL_INFO(dev)->gen >= 9) { |
13600 | intel_primary_formats = skl_primary_formats; | |
13601 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
13602 | } else if (INTEL_INFO(dev)->gen >= 4) { | |
568db4f2 DL |
13603 | intel_primary_formats = i965_primary_formats; |
13604 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
6c0fd451 DL |
13605 | } else { |
13606 | intel_primary_formats = i8xx_primary_formats; | |
13607 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
465c120c MR |
13608 | } |
13609 | ||
13610 | drm_universal_plane_init(dev, &primary->base, 0, | |
65a3fea0 | 13611 | &intel_plane_funcs, |
465c120c MR |
13612 | intel_primary_formats, num_formats, |
13613 | DRM_PLANE_TYPE_PRIMARY); | |
48404c1e | 13614 | |
3b7a5119 SJ |
13615 | if (INTEL_INFO(dev)->gen >= 4) |
13616 | intel_create_rotation_property(dev, primary); | |
48404c1e | 13617 | |
ea2c67bb MR |
13618 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
13619 | ||
465c120c MR |
13620 | return &primary->base; |
13621 | } | |
13622 | ||
3b7a5119 SJ |
13623 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
13624 | { | |
13625 | if (!dev->mode_config.rotation_property) { | |
13626 | unsigned long flags = BIT(DRM_ROTATE_0) | | |
13627 | BIT(DRM_ROTATE_180); | |
13628 | ||
13629 | if (INTEL_INFO(dev)->gen >= 9) | |
13630 | flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); | |
13631 | ||
13632 | dev->mode_config.rotation_property = | |
13633 | drm_mode_create_rotation_property(dev, flags); | |
13634 | } | |
13635 | if (dev->mode_config.rotation_property) | |
13636 | drm_object_attach_property(&plane->base.base, | |
13637 | dev->mode_config.rotation_property, | |
13638 | plane->base.state->rotation); | |
13639 | } | |
13640 | ||
3d7d6510 | 13641 | static int |
852e787c | 13642 | intel_check_cursor_plane(struct drm_plane *plane, |
061e4b8d | 13643 | struct intel_crtc_state *crtc_state, |
852e787c | 13644 | struct intel_plane_state *state) |
3d7d6510 | 13645 | { |
061e4b8d | 13646 | struct drm_crtc *crtc = crtc_state->base.crtc; |
2b875c22 | 13647 | struct drm_framebuffer *fb = state->base.fb; |
757f9a3e | 13648 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
757f9a3e GP |
13649 | unsigned stride; |
13650 | int ret; | |
3d7d6510 | 13651 | |
061e4b8d ML |
13652 | ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
13653 | &state->dst, &state->clip, | |
3d7d6510 MR |
13654 | DRM_PLANE_HELPER_NO_SCALING, |
13655 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 13656 | true, true, &state->visible); |
757f9a3e GP |
13657 | if (ret) |
13658 | return ret; | |
13659 | ||
757f9a3e GP |
13660 | /* if we want to turn off the cursor ignore width and height */ |
13661 | if (!obj) | |
da20eabd | 13662 | return 0; |
757f9a3e | 13663 | |
757f9a3e | 13664 | /* Check for which cursor types we support */ |
061e4b8d | 13665 | if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) { |
ea2c67bb MR |
13666 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", |
13667 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
13668 | return -EINVAL; |
13669 | } | |
13670 | ||
ea2c67bb MR |
13671 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
13672 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
13673 | DRM_DEBUG_KMS("buffer is too small\n"); |
13674 | return -ENOMEM; | |
13675 | } | |
13676 | ||
3a656b54 | 13677 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e | 13678 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
da20eabd | 13679 | return -EINVAL; |
32b7eeec MR |
13680 | } |
13681 | ||
da20eabd | 13682 | return 0; |
852e787c | 13683 | } |
3d7d6510 | 13684 | |
a8ad0d8e ML |
13685 | static void |
13686 | intel_disable_cursor_plane(struct drm_plane *plane, | |
7fabf5ef | 13687 | struct drm_crtc *crtc) |
a8ad0d8e | 13688 | { |
a8ad0d8e ML |
13689 | intel_crtc_update_cursor(crtc, false); |
13690 | } | |
13691 | ||
f4a2cf29 | 13692 | static void |
852e787c GP |
13693 | intel_commit_cursor_plane(struct drm_plane *plane, |
13694 | struct intel_plane_state *state) | |
13695 | { | |
2b875c22 | 13696 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb MR |
13697 | struct drm_device *dev = plane->dev; |
13698 | struct intel_crtc *intel_crtc; | |
2b875c22 | 13699 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 13700 | uint32_t addr; |
852e787c | 13701 | |
ea2c67bb MR |
13702 | crtc = crtc ? crtc : plane->crtc; |
13703 | intel_crtc = to_intel_crtc(crtc); | |
13704 | ||
a912f12f GP |
13705 | if (intel_crtc->cursor_bo == obj) |
13706 | goto update; | |
4ed91096 | 13707 | |
f4a2cf29 | 13708 | if (!obj) |
a912f12f | 13709 | addr = 0; |
f4a2cf29 | 13710 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 13711 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 13712 | else |
a912f12f | 13713 | addr = obj->phys_handle->busaddr; |
852e787c | 13714 | |
a912f12f GP |
13715 | intel_crtc->cursor_addr = addr; |
13716 | intel_crtc->cursor_bo = obj; | |
852e787c | 13717 | |
302d19ac | 13718 | update: |
a539205a | 13719 | if (crtc->state->active) |
a912f12f | 13720 | intel_crtc_update_cursor(crtc, state->visible); |
852e787c GP |
13721 | } |
13722 | ||
3d7d6510 MR |
13723 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
13724 | int pipe) | |
13725 | { | |
13726 | struct intel_plane *cursor; | |
8e7d688b | 13727 | struct intel_plane_state *state; |
3d7d6510 MR |
13728 | |
13729 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
13730 | if (cursor == NULL) | |
13731 | return NULL; | |
13732 | ||
8e7d688b MR |
13733 | state = intel_create_plane_state(&cursor->base); |
13734 | if (!state) { | |
ea2c67bb MR |
13735 | kfree(cursor); |
13736 | return NULL; | |
13737 | } | |
8e7d688b | 13738 | cursor->base.state = &state->base; |
ea2c67bb | 13739 | |
3d7d6510 MR |
13740 | cursor->can_scale = false; |
13741 | cursor->max_downscale = 1; | |
13742 | cursor->pipe = pipe; | |
13743 | cursor->plane = pipe; | |
a9ff8714 | 13744 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
c59cb179 MR |
13745 | cursor->check_plane = intel_check_cursor_plane; |
13746 | cursor->commit_plane = intel_commit_cursor_plane; | |
a8ad0d8e | 13747 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 MR |
13748 | |
13749 | drm_universal_plane_init(dev, &cursor->base, 0, | |
65a3fea0 | 13750 | &intel_plane_funcs, |
3d7d6510 MR |
13751 | intel_cursor_formats, |
13752 | ARRAY_SIZE(intel_cursor_formats), | |
13753 | DRM_PLANE_TYPE_CURSOR); | |
4398ad45 VS |
13754 | |
13755 | if (INTEL_INFO(dev)->gen >= 4) { | |
13756 | if (!dev->mode_config.rotation_property) | |
13757 | dev->mode_config.rotation_property = | |
13758 | drm_mode_create_rotation_property(dev, | |
13759 | BIT(DRM_ROTATE_0) | | |
13760 | BIT(DRM_ROTATE_180)); | |
13761 | if (dev->mode_config.rotation_property) | |
13762 | drm_object_attach_property(&cursor->base.base, | |
13763 | dev->mode_config.rotation_property, | |
8e7d688b | 13764 | state->base.rotation); |
4398ad45 VS |
13765 | } |
13766 | ||
af99ceda CK |
13767 | if (INTEL_INFO(dev)->gen >=9) |
13768 | state->scaler_id = -1; | |
13769 | ||
ea2c67bb MR |
13770 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
13771 | ||
3d7d6510 MR |
13772 | return &cursor->base; |
13773 | } | |
13774 | ||
549e2bfb CK |
13775 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
13776 | struct intel_crtc_state *crtc_state) | |
13777 | { | |
13778 | int i; | |
13779 | struct intel_scaler *intel_scaler; | |
13780 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; | |
13781 | ||
13782 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
13783 | intel_scaler = &scaler_state->scalers[i]; | |
13784 | intel_scaler->in_use = 0; | |
549e2bfb CK |
13785 | intel_scaler->mode = PS_SCALER_MODE_DYN; |
13786 | } | |
13787 | ||
13788 | scaler_state->scaler_id = -1; | |
13789 | } | |
13790 | ||
b358d0a6 | 13791 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 13792 | { |
fbee40df | 13793 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 13794 | struct intel_crtc *intel_crtc; |
f5de6e07 | 13795 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
13796 | struct drm_plane *primary = NULL; |
13797 | struct drm_plane *cursor = NULL; | |
465c120c | 13798 | int i, ret; |
79e53945 | 13799 | |
955382f3 | 13800 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
13801 | if (intel_crtc == NULL) |
13802 | return; | |
13803 | ||
f5de6e07 ACO |
13804 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
13805 | if (!crtc_state) | |
13806 | goto fail; | |
550acefd ACO |
13807 | intel_crtc->config = crtc_state; |
13808 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 13809 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 13810 | |
549e2bfb CK |
13811 | /* initialize shared scalers */ |
13812 | if (INTEL_INFO(dev)->gen >= 9) { | |
13813 | if (pipe == PIPE_C) | |
13814 | intel_crtc->num_scalers = 1; | |
13815 | else | |
13816 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
13817 | ||
13818 | skl_init_scalers(dev, intel_crtc, crtc_state); | |
13819 | } | |
13820 | ||
465c120c | 13821 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
13822 | if (!primary) |
13823 | goto fail; | |
13824 | ||
13825 | cursor = intel_cursor_plane_create(dev, pipe); | |
13826 | if (!cursor) | |
13827 | goto fail; | |
13828 | ||
465c120c | 13829 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
3d7d6510 MR |
13830 | cursor, &intel_crtc_funcs); |
13831 | if (ret) | |
13832 | goto fail; | |
79e53945 JB |
13833 | |
13834 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
13835 | for (i = 0; i < 256; i++) { |
13836 | intel_crtc->lut_r[i] = i; | |
13837 | intel_crtc->lut_g[i] = i; | |
13838 | intel_crtc->lut_b[i] = i; | |
13839 | } | |
13840 | ||
1f1c2e24 VS |
13841 | /* |
13842 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 13843 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 13844 | */ |
80824003 JB |
13845 | intel_crtc->pipe = pipe; |
13846 | intel_crtc->plane = pipe; | |
3a77c4c4 | 13847 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 13848 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 13849 | intel_crtc->plane = !pipe; |
80824003 JB |
13850 | } |
13851 | ||
4b0e333e CW |
13852 | intel_crtc->cursor_base = ~0; |
13853 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 13854 | intel_crtc->cursor_size = ~0; |
8d7849db | 13855 | |
852eb00d VS |
13856 | intel_crtc->wm.cxsr_allowed = true; |
13857 | ||
22fd0fab JB |
13858 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
13859 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
13860 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
13861 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
13862 | ||
79e53945 | 13863 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 DV |
13864 | |
13865 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); | |
3d7d6510 MR |
13866 | return; |
13867 | ||
13868 | fail: | |
13869 | if (primary) | |
13870 | drm_plane_cleanup(primary); | |
13871 | if (cursor) | |
13872 | drm_plane_cleanup(cursor); | |
f5de6e07 | 13873 | kfree(crtc_state); |
3d7d6510 | 13874 | kfree(intel_crtc); |
79e53945 JB |
13875 | } |
13876 | ||
752aa88a JB |
13877 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
13878 | { | |
13879 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 13880 | struct drm_device *dev = connector->base.dev; |
752aa88a | 13881 | |
51fd371b | 13882 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 13883 | |
d3babd3f | 13884 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
13885 | return INVALID_PIPE; |
13886 | ||
13887 | return to_intel_crtc(encoder->crtc)->pipe; | |
13888 | } | |
13889 | ||
08d7b3d1 | 13890 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 13891 | struct drm_file *file) |
08d7b3d1 | 13892 | { |
08d7b3d1 | 13893 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 13894 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 13895 | struct intel_crtc *crtc; |
08d7b3d1 | 13896 | |
7707e653 | 13897 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 13898 | |
7707e653 | 13899 | if (!drmmode_crtc) { |
08d7b3d1 | 13900 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 13901 | return -ENOENT; |
08d7b3d1 CW |
13902 | } |
13903 | ||
7707e653 | 13904 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 13905 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 13906 | |
c05422d5 | 13907 | return 0; |
08d7b3d1 CW |
13908 | } |
13909 | ||
66a9278e | 13910 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 13911 | { |
66a9278e DV |
13912 | struct drm_device *dev = encoder->base.dev; |
13913 | struct intel_encoder *source_encoder; | |
79e53945 | 13914 | int index_mask = 0; |
79e53945 JB |
13915 | int entry = 0; |
13916 | ||
b2784e15 | 13917 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 13918 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
13919 | index_mask |= (1 << entry); |
13920 | ||
79e53945 JB |
13921 | entry++; |
13922 | } | |
4ef69c7a | 13923 | |
79e53945 JB |
13924 | return index_mask; |
13925 | } | |
13926 | ||
4d302442 CW |
13927 | static bool has_edp_a(struct drm_device *dev) |
13928 | { | |
13929 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13930 | ||
13931 | if (!IS_MOBILE(dev)) | |
13932 | return false; | |
13933 | ||
13934 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
13935 | return false; | |
13936 | ||
e3589908 | 13937 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
13938 | return false; |
13939 | ||
13940 | return true; | |
13941 | } | |
13942 | ||
84b4e042 JB |
13943 | static bool intel_crt_present(struct drm_device *dev) |
13944 | { | |
13945 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13946 | ||
884497ed DL |
13947 | if (INTEL_INFO(dev)->gen >= 9) |
13948 | return false; | |
13949 | ||
cf404ce4 | 13950 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
13951 | return false; |
13952 | ||
13953 | if (IS_CHERRYVIEW(dev)) | |
13954 | return false; | |
13955 | ||
13956 | if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support) | |
13957 | return false; | |
13958 | ||
13959 | return true; | |
13960 | } | |
13961 | ||
79e53945 JB |
13962 | static void intel_setup_outputs(struct drm_device *dev) |
13963 | { | |
725e30ad | 13964 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 13965 | struct intel_encoder *encoder; |
cb0953d7 | 13966 | bool dpd_is_edp = false; |
79e53945 | 13967 | |
c9093354 | 13968 | intel_lvds_init(dev); |
79e53945 | 13969 | |
84b4e042 | 13970 | if (intel_crt_present(dev)) |
79935fca | 13971 | intel_crt_init(dev); |
cb0953d7 | 13972 | |
c776eb2e VK |
13973 | if (IS_BROXTON(dev)) { |
13974 | /* | |
13975 | * FIXME: Broxton doesn't support port detection via the | |
13976 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
13977 | * detect the ports. | |
13978 | */ | |
13979 | intel_ddi_init(dev, PORT_A); | |
13980 | intel_ddi_init(dev, PORT_B); | |
13981 | intel_ddi_init(dev, PORT_C); | |
13982 | } else if (HAS_DDI(dev)) { | |
0e72a5b5 ED |
13983 | int found; |
13984 | ||
de31facd JB |
13985 | /* |
13986 | * Haswell uses DDI functions to detect digital outputs. | |
13987 | * On SKL pre-D0 the strap isn't connected, so we assume | |
13988 | * it's there. | |
13989 | */ | |
0e72a5b5 | 13990 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 13991 | /* WaIgnoreDDIAStrap: skl */ |
5a2376d1 | 13992 | if (found || IS_SKYLAKE(dev)) |
0e72a5b5 ED |
13993 | intel_ddi_init(dev, PORT_A); |
13994 | ||
13995 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
13996 | * register */ | |
13997 | found = I915_READ(SFUSE_STRAP); | |
13998 | ||
13999 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
14000 | intel_ddi_init(dev, PORT_B); | |
14001 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
14002 | intel_ddi_init(dev, PORT_C); | |
14003 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
14004 | intel_ddi_init(dev, PORT_D); | |
2800e4c2 RV |
14005 | /* |
14006 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
14007 | */ | |
14008 | if (IS_SKYLAKE(dev) && | |
14009 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || | |
14010 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
14011 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
14012 | intel_ddi_init(dev, PORT_E); | |
14013 | ||
0e72a5b5 | 14014 | } else if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 14015 | int found; |
5d8a7752 | 14016 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
14017 | |
14018 | if (has_edp_a(dev)) | |
14019 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 14020 | |
dc0fa718 | 14021 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 14022 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 14023 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 14024 | if (!found) |
e2debe91 | 14025 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 14026 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 14027 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
14028 | } |
14029 | ||
dc0fa718 | 14030 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 14031 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 14032 | |
dc0fa718 | 14033 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 14034 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 14035 | |
5eb08b69 | 14036 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 14037 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 14038 | |
270b3042 | 14039 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 14040 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 14041 | } else if (IS_VALLEYVIEW(dev)) { |
e17ac6db VS |
14042 | /* |
14043 | * The DP_DETECTED bit is the latched state of the DDC | |
14044 | * SDA pin at boot. However since eDP doesn't require DDC | |
14045 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
14046 | * eDP ports may have been muxed to an alternate function. | |
14047 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
14048 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
14049 | * detect eDP ports. | |
14050 | */ | |
d2182a66 VS |
14051 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED && |
14052 | !intel_dp_is_edp(dev, PORT_B)) | |
585a94b8 AB |
14053 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, |
14054 | PORT_B); | |
e17ac6db VS |
14055 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED || |
14056 | intel_dp_is_edp(dev, PORT_B)) | |
14057 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
585a94b8 | 14058 | |
d2182a66 VS |
14059 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED && |
14060 | !intel_dp_is_edp(dev, PORT_C)) | |
6f6005a5 JB |
14061 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, |
14062 | PORT_C); | |
e17ac6db VS |
14063 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED || |
14064 | intel_dp_is_edp(dev, PORT_C)) | |
14065 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); | |
19c03924 | 14066 | |
9418c1f1 | 14067 | if (IS_CHERRYVIEW(dev)) { |
e17ac6db | 14068 | if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) |
9418c1f1 VS |
14069 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID, |
14070 | PORT_D); | |
e17ac6db VS |
14071 | /* eDP not supported on port D, so don't check VBT */ |
14072 | if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED) | |
14073 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D); | |
9418c1f1 VS |
14074 | } |
14075 | ||
3cfca973 | 14076 | intel_dsi_init(dev); |
09da55dc | 14077 | } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) { |
27185ae1 | 14078 | bool found = false; |
7d57382e | 14079 | |
e2debe91 | 14080 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14081 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 14082 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
3fec3d2f | 14083 | if (!found && IS_G4X(dev)) { |
b01f2c3a | 14084 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
e2debe91 | 14085 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 14086 | } |
27185ae1 | 14087 | |
3fec3d2f | 14088 | if (!found && IS_G4X(dev)) |
ab9d7c30 | 14089 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 14090 | } |
13520b05 KH |
14091 | |
14092 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 14093 | |
e2debe91 | 14094 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14095 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 14096 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 14097 | } |
27185ae1 | 14098 | |
e2debe91 | 14099 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 14100 | |
3fec3d2f | 14101 | if (IS_G4X(dev)) { |
b01f2c3a | 14102 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
e2debe91 | 14103 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 14104 | } |
3fec3d2f | 14105 | if (IS_G4X(dev)) |
ab9d7c30 | 14106 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 14107 | } |
27185ae1 | 14108 | |
3fec3d2f | 14109 | if (IS_G4X(dev) && |
e7281eab | 14110 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 14111 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 14112 | } else if (IS_GEN2(dev)) |
79e53945 JB |
14113 | intel_dvo_init(dev); |
14114 | ||
103a196f | 14115 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
14116 | intel_tv_init(dev); |
14117 | ||
0bc12bcb | 14118 | intel_psr_init(dev); |
7c8f8a70 | 14119 | |
b2784e15 | 14120 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
14121 | encoder->base.possible_crtcs = encoder->crtc_mask; |
14122 | encoder->base.possible_clones = | |
66a9278e | 14123 | intel_encoder_clones(encoder); |
79e53945 | 14124 | } |
47356eb6 | 14125 | |
dde86e2d | 14126 | intel_init_pch_refclk(dev); |
270b3042 DV |
14127 | |
14128 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
14129 | } |
14130 | ||
14131 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
14132 | { | |
60a5ca01 | 14133 | struct drm_device *dev = fb->dev; |
79e53945 | 14134 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 14135 | |
ef2d633e | 14136 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 14137 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 14138 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
14139 | drm_gem_object_unreference(&intel_fb->obj->base); |
14140 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
14141 | kfree(intel_fb); |
14142 | } | |
14143 | ||
14144 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 14145 | struct drm_file *file, |
79e53945 JB |
14146 | unsigned int *handle) |
14147 | { | |
14148 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 14149 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 14150 | |
05394f39 | 14151 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
14152 | } |
14153 | ||
86c98588 RV |
14154 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
14155 | struct drm_file *file, | |
14156 | unsigned flags, unsigned color, | |
14157 | struct drm_clip_rect *clips, | |
14158 | unsigned num_clips) | |
14159 | { | |
14160 | struct drm_device *dev = fb->dev; | |
14161 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
14162 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
14163 | ||
14164 | mutex_lock(&dev->struct_mutex); | |
74b4ea1e | 14165 | intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); |
86c98588 RV |
14166 | mutex_unlock(&dev->struct_mutex); |
14167 | ||
14168 | return 0; | |
14169 | } | |
14170 | ||
79e53945 JB |
14171 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
14172 | .destroy = intel_user_framebuffer_destroy, | |
14173 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 14174 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
14175 | }; |
14176 | ||
b321803d DL |
14177 | static |
14178 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
14179 | uint32_t pixel_format) | |
14180 | { | |
14181 | u32 gen = INTEL_INFO(dev)->gen; | |
14182 | ||
14183 | if (gen >= 9) { | |
14184 | /* "The stride in bytes must not exceed the of the size of 8K | |
14185 | * pixels and 32K bytes." | |
14186 | */ | |
14187 | return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768); | |
14188 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) { | |
14189 | return 32*1024; | |
14190 | } else if (gen >= 4) { | |
14191 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14192 | return 16*1024; | |
14193 | else | |
14194 | return 32*1024; | |
14195 | } else if (gen >= 3) { | |
14196 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14197 | return 8*1024; | |
14198 | else | |
14199 | return 16*1024; | |
14200 | } else { | |
14201 | /* XXX DSPC is limited to 4k tiled */ | |
14202 | return 8*1024; | |
14203 | } | |
14204 | } | |
14205 | ||
b5ea642a DV |
14206 | static int intel_framebuffer_init(struct drm_device *dev, |
14207 | struct intel_framebuffer *intel_fb, | |
14208 | struct drm_mode_fb_cmd2 *mode_cmd, | |
14209 | struct drm_i915_gem_object *obj) | |
79e53945 | 14210 | { |
6761dd31 | 14211 | unsigned int aligned_height; |
79e53945 | 14212 | int ret; |
b321803d | 14213 | u32 pitch_limit, stride_alignment; |
79e53945 | 14214 | |
dd4916c5 DV |
14215 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
14216 | ||
2a80eada DV |
14217 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
14218 | /* Enforce that fb modifier and tiling mode match, but only for | |
14219 | * X-tiled. This is needed for FBC. */ | |
14220 | if (!!(obj->tiling_mode == I915_TILING_X) != | |
14221 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { | |
14222 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
14223 | return -EINVAL; | |
14224 | } | |
14225 | } else { | |
14226 | if (obj->tiling_mode == I915_TILING_X) | |
14227 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
14228 | else if (obj->tiling_mode == I915_TILING_Y) { | |
14229 | DRM_DEBUG("No Y tiling for legacy addfb\n"); | |
14230 | return -EINVAL; | |
14231 | } | |
14232 | } | |
14233 | ||
9a8f0a12 TU |
14234 | /* Passed in modifier sanity checking. */ |
14235 | switch (mode_cmd->modifier[0]) { | |
14236 | case I915_FORMAT_MOD_Y_TILED: | |
14237 | case I915_FORMAT_MOD_Yf_TILED: | |
14238 | if (INTEL_INFO(dev)->gen < 9) { | |
14239 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
14240 | mode_cmd->modifier[0]); | |
14241 | return -EINVAL; | |
14242 | } | |
14243 | case DRM_FORMAT_MOD_NONE: | |
14244 | case I915_FORMAT_MOD_X_TILED: | |
14245 | break; | |
14246 | default: | |
c0f40428 JB |
14247 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
14248 | mode_cmd->modifier[0]); | |
57cd6508 | 14249 | return -EINVAL; |
c16ed4be | 14250 | } |
57cd6508 | 14251 | |
b321803d DL |
14252 | stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0], |
14253 | mode_cmd->pixel_format); | |
14254 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
14255 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
14256 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 14257 | return -EINVAL; |
c16ed4be | 14258 | } |
57cd6508 | 14259 | |
b321803d DL |
14260 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
14261 | mode_cmd->pixel_format); | |
a35cdaa0 | 14262 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
14263 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
14264 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 14265 | "tiled" : "linear", |
a35cdaa0 | 14266 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 14267 | return -EINVAL; |
c16ed4be | 14268 | } |
5d7bd705 | 14269 | |
2a80eada | 14270 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
c16ed4be CW |
14271 | mode_cmd->pitches[0] != obj->stride) { |
14272 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
14273 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 14274 | return -EINVAL; |
c16ed4be | 14275 | } |
5d7bd705 | 14276 | |
57779d06 | 14277 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 14278 | switch (mode_cmd->pixel_format) { |
57779d06 | 14279 | case DRM_FORMAT_C8: |
04b3924d VS |
14280 | case DRM_FORMAT_RGB565: |
14281 | case DRM_FORMAT_XRGB8888: | |
14282 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
14283 | break; |
14284 | case DRM_FORMAT_XRGB1555: | |
c16ed4be | 14285 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
14286 | DRM_DEBUG("unsupported pixel format: %s\n", |
14287 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14288 | return -EINVAL; |
c16ed4be | 14289 | } |
57779d06 | 14290 | break; |
57779d06 | 14291 | case DRM_FORMAT_ABGR8888: |
6c0fd451 DL |
14292 | if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) { |
14293 | DRM_DEBUG("unsupported pixel format: %s\n", | |
14294 | drm_get_format_name(mode_cmd->pixel_format)); | |
14295 | return -EINVAL; | |
14296 | } | |
14297 | break; | |
14298 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 14299 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 14300 | case DRM_FORMAT_XBGR2101010: |
c16ed4be | 14301 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
14302 | DRM_DEBUG("unsupported pixel format: %s\n", |
14303 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14304 | return -EINVAL; |
c16ed4be | 14305 | } |
b5626747 | 14306 | break; |
7531208b DL |
14307 | case DRM_FORMAT_ABGR2101010: |
14308 | if (!IS_VALLEYVIEW(dev)) { | |
14309 | DRM_DEBUG("unsupported pixel format: %s\n", | |
14310 | drm_get_format_name(mode_cmd->pixel_format)); | |
14311 | return -EINVAL; | |
14312 | } | |
14313 | break; | |
04b3924d VS |
14314 | case DRM_FORMAT_YUYV: |
14315 | case DRM_FORMAT_UYVY: | |
14316 | case DRM_FORMAT_YVYU: | |
14317 | case DRM_FORMAT_VYUY: | |
c16ed4be | 14318 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
14319 | DRM_DEBUG("unsupported pixel format: %s\n", |
14320 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14321 | return -EINVAL; |
c16ed4be | 14322 | } |
57cd6508 CW |
14323 | break; |
14324 | default: | |
4ee62c76 VS |
14325 | DRM_DEBUG("unsupported pixel format: %s\n", |
14326 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
14327 | return -EINVAL; |
14328 | } | |
14329 | ||
90f9a336 VS |
14330 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
14331 | if (mode_cmd->offsets[0] != 0) | |
14332 | return -EINVAL; | |
14333 | ||
ec2c981e | 14334 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
091df6cb DV |
14335 | mode_cmd->pixel_format, |
14336 | mode_cmd->modifier[0]); | |
53155c0a DV |
14337 | /* FIXME drm helper for size checks (especially planar formats)? */ |
14338 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
14339 | return -EINVAL; | |
14340 | ||
c7d73f6a DV |
14341 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
14342 | intel_fb->obj = obj; | |
80075d49 | 14343 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 14344 | |
79e53945 JB |
14345 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
14346 | if (ret) { | |
14347 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
14348 | return ret; | |
14349 | } | |
14350 | ||
79e53945 JB |
14351 | return 0; |
14352 | } | |
14353 | ||
79e53945 JB |
14354 | static struct drm_framebuffer * |
14355 | intel_user_framebuffer_create(struct drm_device *dev, | |
14356 | struct drm_file *filp, | |
308e5bcb | 14357 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 14358 | { |
05394f39 | 14359 | struct drm_i915_gem_object *obj; |
79e53945 | 14360 | |
308e5bcb JB |
14361 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
14362 | mode_cmd->handles[0])); | |
c8725226 | 14363 | if (&obj->base == NULL) |
cce13ff7 | 14364 | return ERR_PTR(-ENOENT); |
79e53945 | 14365 | |
d2dff872 | 14366 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
14367 | } |
14368 | ||
0695726e | 14369 | #ifndef CONFIG_DRM_FBDEV_EMULATION |
0632fef6 | 14370 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
14371 | { |
14372 | } | |
14373 | #endif | |
14374 | ||
79e53945 | 14375 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 14376 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 14377 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
14378 | .atomic_check = intel_atomic_check, |
14379 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
14380 | .atomic_state_alloc = intel_atomic_state_alloc, |
14381 | .atomic_state_clear = intel_atomic_state_clear, | |
79e53945 JB |
14382 | }; |
14383 | ||
e70236a8 JB |
14384 | /* Set up chip specific display functions */ |
14385 | static void intel_init_display(struct drm_device *dev) | |
14386 | { | |
14387 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14388 | ||
ee9300bb DV |
14389 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
14390 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
14391 | else if (IS_CHERRYVIEW(dev)) |
14392 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
14393 | else if (IS_VALLEYVIEW(dev)) |
14394 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
14395 | else if (IS_PINEVIEW(dev)) | |
14396 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
14397 | else | |
14398 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
14399 | ||
bc8d7dff DL |
14400 | if (INTEL_INFO(dev)->gen >= 9) { |
14401 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; | |
5724dbd1 DL |
14402 | dev_priv->display.get_initial_plane_config = |
14403 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
14404 | dev_priv->display.crtc_compute_clock = |
14405 | haswell_crtc_compute_clock; | |
14406 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
14407 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
bc8d7dff DL |
14408 | dev_priv->display.update_primary_plane = |
14409 | skylake_update_primary_plane; | |
14410 | } else if (HAS_DDI(dev)) { | |
0e8ffe1b | 14411 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14412 | dev_priv->display.get_initial_plane_config = |
14413 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
14414 | dev_priv->display.crtc_compute_clock = |
14415 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
14416 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
14417 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
bc8d7dff DL |
14418 | dev_priv->display.update_primary_plane = |
14419 | ironlake_update_primary_plane; | |
09b4ddf9 | 14420 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 14421 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
14422 | dev_priv->display.get_initial_plane_config = |
14423 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
14424 | dev_priv->display.crtc_compute_clock = |
14425 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
14426 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
14427 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
262ca2b0 MR |
14428 | dev_priv->display.update_primary_plane = |
14429 | ironlake_update_primary_plane; | |
89b667f8 JB |
14430 | } else if (IS_VALLEYVIEW(dev)) { |
14431 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
5724dbd1 DL |
14432 | dev_priv->display.get_initial_plane_config = |
14433 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14434 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
89b667f8 JB |
14435 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
14436 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
262ca2b0 MR |
14437 | dev_priv->display.update_primary_plane = |
14438 | i9xx_update_primary_plane; | |
f564048e | 14439 | } else { |
0e8ffe1b | 14440 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14441 | dev_priv->display.get_initial_plane_config = |
14442 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14443 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
14444 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
14445 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
262ca2b0 MR |
14446 | dev_priv->display.update_primary_plane = |
14447 | i9xx_update_primary_plane; | |
f564048e | 14448 | } |
e70236a8 | 14449 | |
e70236a8 | 14450 | /* Returns the core display clock speed */ |
1652d19e VS |
14451 | if (IS_SKYLAKE(dev)) |
14452 | dev_priv->display.get_display_clock_speed = | |
14453 | skylake_get_display_clock_speed; | |
acd3f3d3 BP |
14454 | else if (IS_BROXTON(dev)) |
14455 | dev_priv->display.get_display_clock_speed = | |
14456 | broxton_get_display_clock_speed; | |
1652d19e VS |
14457 | else if (IS_BROADWELL(dev)) |
14458 | dev_priv->display.get_display_clock_speed = | |
14459 | broadwell_get_display_clock_speed; | |
14460 | else if (IS_HASWELL(dev)) | |
14461 | dev_priv->display.get_display_clock_speed = | |
14462 | haswell_get_display_clock_speed; | |
14463 | else if (IS_VALLEYVIEW(dev)) | |
25eb05fc JB |
14464 | dev_priv->display.get_display_clock_speed = |
14465 | valleyview_get_display_clock_speed; | |
b37a6434 VS |
14466 | else if (IS_GEN5(dev)) |
14467 | dev_priv->display.get_display_clock_speed = | |
14468 | ilk_get_display_clock_speed; | |
a7c66cd8 | 14469 | else if (IS_I945G(dev) || IS_BROADWATER(dev) || |
34edce2f | 14470 | IS_GEN6(dev) || IS_IVYBRIDGE(dev)) |
e70236a8 JB |
14471 | dev_priv->display.get_display_clock_speed = |
14472 | i945_get_display_clock_speed; | |
34edce2f VS |
14473 | else if (IS_GM45(dev)) |
14474 | dev_priv->display.get_display_clock_speed = | |
14475 | gm45_get_display_clock_speed; | |
14476 | else if (IS_CRESTLINE(dev)) | |
14477 | dev_priv->display.get_display_clock_speed = | |
14478 | i965gm_get_display_clock_speed; | |
14479 | else if (IS_PINEVIEW(dev)) | |
14480 | dev_priv->display.get_display_clock_speed = | |
14481 | pnv_get_display_clock_speed; | |
14482 | else if (IS_G33(dev) || IS_G4X(dev)) | |
14483 | dev_priv->display.get_display_clock_speed = | |
14484 | g33_get_display_clock_speed; | |
e70236a8 JB |
14485 | else if (IS_I915G(dev)) |
14486 | dev_priv->display.get_display_clock_speed = | |
14487 | i915_get_display_clock_speed; | |
257a7ffc | 14488 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
14489 | dev_priv->display.get_display_clock_speed = |
14490 | i9xx_misc_get_display_clock_speed; | |
257a7ffc DV |
14491 | else if (IS_PINEVIEW(dev)) |
14492 | dev_priv->display.get_display_clock_speed = | |
14493 | pnv_get_display_clock_speed; | |
e70236a8 JB |
14494 | else if (IS_I915GM(dev)) |
14495 | dev_priv->display.get_display_clock_speed = | |
14496 | i915gm_get_display_clock_speed; | |
14497 | else if (IS_I865G(dev)) | |
14498 | dev_priv->display.get_display_clock_speed = | |
14499 | i865_get_display_clock_speed; | |
f0f8a9ce | 14500 | else if (IS_I85X(dev)) |
e70236a8 | 14501 | dev_priv->display.get_display_clock_speed = |
1b1d2716 | 14502 | i85x_get_display_clock_speed; |
623e01e5 VS |
14503 | else { /* 830 */ |
14504 | WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n"); | |
e70236a8 JB |
14505 | dev_priv->display.get_display_clock_speed = |
14506 | i830_get_display_clock_speed; | |
623e01e5 | 14507 | } |
e70236a8 | 14508 | |
7c10a2b5 | 14509 | if (IS_GEN5(dev)) { |
3bb11b53 | 14510 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
3bb11b53 SJ |
14511 | } else if (IS_GEN6(dev)) { |
14512 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; | |
3bb11b53 SJ |
14513 | } else if (IS_IVYBRIDGE(dev)) { |
14514 | /* FIXME: detect B0+ stepping and use auto training */ | |
14515 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
059b2fe9 | 14516 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
3bb11b53 | 14517 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
27c329ed ML |
14518 | if (IS_BROADWELL(dev)) { |
14519 | dev_priv->display.modeset_commit_cdclk = | |
14520 | broadwell_modeset_commit_cdclk; | |
14521 | dev_priv->display.modeset_calc_cdclk = | |
14522 | broadwell_modeset_calc_cdclk; | |
14523 | } | |
30a970c6 | 14524 | } else if (IS_VALLEYVIEW(dev)) { |
27c329ed ML |
14525 | dev_priv->display.modeset_commit_cdclk = |
14526 | valleyview_modeset_commit_cdclk; | |
14527 | dev_priv->display.modeset_calc_cdclk = | |
14528 | valleyview_modeset_calc_cdclk; | |
f8437dd1 | 14529 | } else if (IS_BROXTON(dev)) { |
27c329ed ML |
14530 | dev_priv->display.modeset_commit_cdclk = |
14531 | broxton_modeset_commit_cdclk; | |
14532 | dev_priv->display.modeset_calc_cdclk = | |
14533 | broxton_modeset_calc_cdclk; | |
e70236a8 | 14534 | } |
8c9f3aaf | 14535 | |
8c9f3aaf JB |
14536 | switch (INTEL_INFO(dev)->gen) { |
14537 | case 2: | |
14538 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
14539 | break; | |
14540 | ||
14541 | case 3: | |
14542 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
14543 | break; | |
14544 | ||
14545 | case 4: | |
14546 | case 5: | |
14547 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
14548 | break; | |
14549 | ||
14550 | case 6: | |
14551 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
14552 | break; | |
7c9017e5 | 14553 | case 7: |
4e0bbc31 | 14554 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
14555 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
14556 | break; | |
830c81db | 14557 | case 9: |
ba343e02 TU |
14558 | /* Drop through - unsupported since execlist only. */ |
14559 | default: | |
14560 | /* Default just returns -ENODEV to indicate unsupported */ | |
14561 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8c9f3aaf | 14562 | } |
7bd688cd JN |
14563 | |
14564 | intel_panel_init_backlight_funcs(dev); | |
e39b999a VS |
14565 | |
14566 | mutex_init(&dev_priv->pps_mutex); | |
e70236a8 JB |
14567 | } |
14568 | ||
b690e96c JB |
14569 | /* |
14570 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
14571 | * resume, or other times. This quirk makes sure that's the case for | |
14572 | * affected systems. | |
14573 | */ | |
0206e353 | 14574 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
14575 | { |
14576 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14577 | ||
14578 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 14579 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
14580 | } |
14581 | ||
b6b5d049 VS |
14582 | static void quirk_pipeb_force(struct drm_device *dev) |
14583 | { | |
14584 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14585 | ||
14586 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
14587 | DRM_INFO("applying pipe b force quirk\n"); | |
14588 | } | |
14589 | ||
435793df KP |
14590 | /* |
14591 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
14592 | */ | |
14593 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
14594 | { | |
14595 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14596 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 14597 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
14598 | } |
14599 | ||
4dca20ef | 14600 | /* |
5a15ab5b CE |
14601 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
14602 | * brightness value | |
4dca20ef CE |
14603 | */ |
14604 | static void quirk_invert_brightness(struct drm_device *dev) | |
14605 | { | |
14606 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14607 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 14608 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
14609 | } |
14610 | ||
9c72cc6f SD |
14611 | /* Some VBT's incorrectly indicate no backlight is present */ |
14612 | static void quirk_backlight_present(struct drm_device *dev) | |
14613 | { | |
14614 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14615 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
14616 | DRM_INFO("applying backlight present quirk\n"); | |
14617 | } | |
14618 | ||
b690e96c JB |
14619 | struct intel_quirk { |
14620 | int device; | |
14621 | int subsystem_vendor; | |
14622 | int subsystem_device; | |
14623 | void (*hook)(struct drm_device *dev); | |
14624 | }; | |
14625 | ||
5f85f176 EE |
14626 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
14627 | struct intel_dmi_quirk { | |
14628 | void (*hook)(struct drm_device *dev); | |
14629 | const struct dmi_system_id (*dmi_id_list)[]; | |
14630 | }; | |
14631 | ||
14632 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
14633 | { | |
14634 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
14635 | return 1; | |
14636 | } | |
14637 | ||
14638 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
14639 | { | |
14640 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
14641 | { | |
14642 | .callback = intel_dmi_reverse_brightness, | |
14643 | .ident = "NCR Corporation", | |
14644 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
14645 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
14646 | }, | |
14647 | }, | |
14648 | { } /* terminating entry */ | |
14649 | }, | |
14650 | .hook = quirk_invert_brightness, | |
14651 | }, | |
14652 | }; | |
14653 | ||
c43b5634 | 14654 | static struct intel_quirk intel_quirks[] = { |
b690e96c JB |
14655 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
14656 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
14657 | ||
b690e96c JB |
14658 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
14659 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
14660 | ||
5f080c0f VS |
14661 | /* 830 needs to leave pipe A & dpll A up */ |
14662 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
14663 | ||
b6b5d049 VS |
14664 | /* 830 needs to leave pipe B & dpll B up */ |
14665 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
14666 | ||
435793df KP |
14667 | /* Lenovo U160 cannot use SSC on LVDS */ |
14668 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
14669 | |
14670 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
14671 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 14672 | |
be505f64 AH |
14673 | /* Acer Aspire 5734Z must invert backlight brightness */ |
14674 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
14675 | ||
14676 | /* Acer/eMachines G725 */ | |
14677 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
14678 | ||
14679 | /* Acer/eMachines e725 */ | |
14680 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
14681 | ||
14682 | /* Acer/Packard Bell NCL20 */ | |
14683 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
14684 | ||
14685 | /* Acer Aspire 4736Z */ | |
14686 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
14687 | |
14688 | /* Acer Aspire 5336 */ | |
14689 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
14690 | |
14691 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
14692 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 14693 | |
dfb3d47b SD |
14694 | /* Acer C720 Chromebook (Core i3 4005U) */ |
14695 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
14696 | ||
b2a9601c | 14697 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
14698 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
14699 | ||
d4967d8c SD |
14700 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
14701 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
14702 | |
14703 | /* HP Chromebook 14 (Celeron 2955U) */ | |
14704 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
14705 | |
14706 | /* Dell Chromebook 11 */ | |
14707 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
14708 | }; |
14709 | ||
14710 | static void intel_init_quirks(struct drm_device *dev) | |
14711 | { | |
14712 | struct pci_dev *d = dev->pdev; | |
14713 | int i; | |
14714 | ||
14715 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
14716 | struct intel_quirk *q = &intel_quirks[i]; | |
14717 | ||
14718 | if (d->device == q->device && | |
14719 | (d->subsystem_vendor == q->subsystem_vendor || | |
14720 | q->subsystem_vendor == PCI_ANY_ID) && | |
14721 | (d->subsystem_device == q->subsystem_device || | |
14722 | q->subsystem_device == PCI_ANY_ID)) | |
14723 | q->hook(dev); | |
14724 | } | |
5f85f176 EE |
14725 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
14726 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
14727 | intel_dmi_quirks[i].hook(dev); | |
14728 | } | |
b690e96c JB |
14729 | } |
14730 | ||
9cce37f4 JB |
14731 | /* Disable the VGA plane that we never use */ |
14732 | static void i915_disable_vga(struct drm_device *dev) | |
14733 | { | |
14734 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14735 | u8 sr1; | |
766aa1c4 | 14736 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 14737 | |
2b37c616 | 14738 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 14739 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 14740 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
14741 | sr1 = inb(VGA_SR_DATA); |
14742 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
14743 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
14744 | udelay(300); | |
14745 | ||
01f5a626 | 14746 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
14747 | POSTING_READ(vga_reg); |
14748 | } | |
14749 | ||
f817586c DV |
14750 | void intel_modeset_init_hw(struct drm_device *dev) |
14751 | { | |
b6283055 | 14752 | intel_update_cdclk(dev); |
a8f78b58 | 14753 | intel_prepare_ddi(dev); |
f817586c | 14754 | intel_init_clock_gating(dev); |
8090c6b9 | 14755 | intel_enable_gt_powersave(dev); |
f817586c DV |
14756 | } |
14757 | ||
79e53945 JB |
14758 | void intel_modeset_init(struct drm_device *dev) |
14759 | { | |
652c393a | 14760 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 14761 | int sprite, ret; |
8cc87b75 | 14762 | enum pipe pipe; |
46f297fb | 14763 | struct intel_crtc *crtc; |
79e53945 JB |
14764 | |
14765 | drm_mode_config_init(dev); | |
14766 | ||
14767 | dev->mode_config.min_width = 0; | |
14768 | dev->mode_config.min_height = 0; | |
14769 | ||
019d96cb DA |
14770 | dev->mode_config.preferred_depth = 24; |
14771 | dev->mode_config.prefer_shadow = 1; | |
14772 | ||
25bab385 TU |
14773 | dev->mode_config.allow_fb_modifiers = true; |
14774 | ||
e6ecefaa | 14775 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 14776 | |
b690e96c JB |
14777 | intel_init_quirks(dev); |
14778 | ||
1fa61106 ED |
14779 | intel_init_pm(dev); |
14780 | ||
e3c74757 BW |
14781 | if (INTEL_INFO(dev)->num_pipes == 0) |
14782 | return; | |
14783 | ||
69f92f67 LW |
14784 | /* |
14785 | * There may be no VBT; and if the BIOS enabled SSC we can | |
14786 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
14787 | * BIOS isn't using it, don't assume it will work even if the VBT | |
14788 | * indicates as much. | |
14789 | */ | |
14790 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { | |
14791 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
14792 | DREF_SSC1_ENABLE); | |
14793 | ||
14794 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
14795 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
14796 | bios_lvds_use_ssc ? "en" : "dis", | |
14797 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
14798 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
14799 | } | |
14800 | } | |
14801 | ||
e70236a8 | 14802 | intel_init_display(dev); |
7c10a2b5 | 14803 | intel_init_audio(dev); |
e70236a8 | 14804 | |
a6c45cf0 CW |
14805 | if (IS_GEN2(dev)) { |
14806 | dev->mode_config.max_width = 2048; | |
14807 | dev->mode_config.max_height = 2048; | |
14808 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
14809 | dev->mode_config.max_width = 4096; |
14810 | dev->mode_config.max_height = 4096; | |
79e53945 | 14811 | } else { |
a6c45cf0 CW |
14812 | dev->mode_config.max_width = 8192; |
14813 | dev->mode_config.max_height = 8192; | |
79e53945 | 14814 | } |
068be561 | 14815 | |
dc41c154 VS |
14816 | if (IS_845G(dev) || IS_I865G(dev)) { |
14817 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
14818 | dev->mode_config.cursor_height = 1023; | |
14819 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
14820 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
14821 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
14822 | } else { | |
14823 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
14824 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
14825 | } | |
14826 | ||
5d4545ae | 14827 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 14828 | |
28c97730 | 14829 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
14830 | INTEL_INFO(dev)->num_pipes, |
14831 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 14832 | |
055e393f | 14833 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 14834 | intel_crtc_init(dev, pipe); |
3bdcfc0c | 14835 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 14836 | ret = intel_plane_init(dev, pipe, sprite); |
7f1f3851 | 14837 | if (ret) |
06da8da2 | 14838 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 14839 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 14840 | } |
79e53945 JB |
14841 | } |
14842 | ||
e72f9fbf | 14843 | intel_shared_dpll_init(dev); |
ee7b9f93 | 14844 | |
9cce37f4 JB |
14845 | /* Just disable it once at startup */ |
14846 | i915_disable_vga(dev); | |
79e53945 | 14847 | intel_setup_outputs(dev); |
11be49eb CW |
14848 | |
14849 | /* Just in case the BIOS is doing something questionable. */ | |
7733b49b | 14850 | intel_fbc_disable(dev_priv); |
fa9fa083 | 14851 | |
6e9f798d | 14852 | drm_modeset_lock_all(dev); |
043e9bda | 14853 | intel_modeset_setup_hw_state(dev); |
6e9f798d | 14854 | drm_modeset_unlock_all(dev); |
46f297fb | 14855 | |
d3fcc808 | 14856 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
14857 | struct intel_initial_plane_config plane_config = {}; |
14858 | ||
46f297fb JB |
14859 | if (!crtc->active) |
14860 | continue; | |
14861 | ||
46f297fb | 14862 | /* |
46f297fb JB |
14863 | * Note that reserving the BIOS fb up front prevents us |
14864 | * from stuffing other stolen allocations like the ring | |
14865 | * on top. This prevents some ugliness at boot time, and | |
14866 | * can even allow for smooth boot transitions if the BIOS | |
14867 | * fb is large enough for the active pipe configuration. | |
14868 | */ | |
eeebeac5 ML |
14869 | dev_priv->display.get_initial_plane_config(crtc, |
14870 | &plane_config); | |
14871 | ||
14872 | /* | |
14873 | * If the fb is shared between multiple heads, we'll | |
14874 | * just get the first one. | |
14875 | */ | |
14876 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 14877 | } |
2c7111db CW |
14878 | } |
14879 | ||
7fad798e DV |
14880 | static void intel_enable_pipe_a(struct drm_device *dev) |
14881 | { | |
14882 | struct intel_connector *connector; | |
14883 | struct drm_connector *crt = NULL; | |
14884 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 14885 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
14886 | |
14887 | /* We can't just switch on the pipe A, we need to set things up with a | |
14888 | * proper mode and output configuration. As a gross hack, enable pipe A | |
14889 | * by enabling the load detect pipe once. */ | |
3a3371ff | 14890 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
14891 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
14892 | crt = &connector->base; | |
14893 | break; | |
14894 | } | |
14895 | } | |
14896 | ||
14897 | if (!crt) | |
14898 | return; | |
14899 | ||
208bf9fd | 14900 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 14901 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
14902 | } |
14903 | ||
fa555837 DV |
14904 | static bool |
14905 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
14906 | { | |
7eb552ae BW |
14907 | struct drm_device *dev = crtc->base.dev; |
14908 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
14909 | u32 reg, val; |
14910 | ||
7eb552ae | 14911 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
14912 | return true; |
14913 | ||
14914 | reg = DSPCNTR(!crtc->plane); | |
14915 | val = I915_READ(reg); | |
14916 | ||
14917 | if ((val & DISPLAY_PLANE_ENABLE) && | |
14918 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
14919 | return false; | |
14920 | ||
14921 | return true; | |
14922 | } | |
14923 | ||
02e93c35 VS |
14924 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
14925 | { | |
14926 | struct drm_device *dev = crtc->base.dev; | |
14927 | struct intel_encoder *encoder; | |
14928 | ||
14929 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
14930 | return true; | |
14931 | ||
14932 | return false; | |
14933 | } | |
14934 | ||
24929352 DV |
14935 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
14936 | { | |
14937 | struct drm_device *dev = crtc->base.dev; | |
14938 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 14939 | u32 reg; |
24929352 | 14940 | |
24929352 | 14941 | /* Clear any frame start delays used for debugging left by the BIOS */ |
6e3c9717 | 14942 | reg = PIPECONF(crtc->config->cpu_transcoder); |
24929352 DV |
14943 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
14944 | ||
d3eaf884 | 14945 | /* restore vblank interrupts to correct state */ |
9625604c | 14946 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 14947 | if (crtc->active) { |
f9cd7b88 VS |
14948 | struct intel_plane *plane; |
14949 | ||
9625604c | 14950 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
14951 | |
14952 | /* Disable everything but the primary plane */ | |
14953 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
14954 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
14955 | continue; | |
14956 | ||
14957 | plane->disable_plane(&plane->base, &crtc->base); | |
14958 | } | |
9625604c | 14959 | } |
d3eaf884 | 14960 | |
24929352 | 14961 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
14962 | * disable the crtc (and hence change the state) if it is wrong. Note |
14963 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
14964 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
14965 | bool plane; |
14966 | ||
24929352 DV |
14967 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
14968 | crtc->base.base.id); | |
14969 | ||
14970 | /* Pipe has the wrong plane attached and the plane is active. | |
14971 | * Temporarily change the plane mapping and disable everything | |
14972 | * ... */ | |
14973 | plane = crtc->plane; | |
b70709a6 | 14974 | to_intel_plane_state(crtc->base.primary->state)->visible = true; |
24929352 | 14975 | crtc->plane = !plane; |
b17d48e2 | 14976 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 14977 | crtc->plane = plane; |
24929352 | 14978 | } |
24929352 | 14979 | |
7fad798e DV |
14980 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
14981 | crtc->pipe == PIPE_A && !crtc->active) { | |
14982 | /* BIOS forgot to enable pipe A, this mostly happens after | |
14983 | * resume. Force-enable the pipe to fix this, the update_dpms | |
14984 | * call below we restore the pipe to the right state, but leave | |
14985 | * the required bits on. */ | |
14986 | intel_enable_pipe_a(dev); | |
14987 | } | |
14988 | ||
24929352 DV |
14989 | /* Adjust the state of the output pipe according to whether we |
14990 | * have active connectors/encoders. */ | |
02e93c35 | 14991 | if (!intel_crtc_has_encoders(crtc)) |
b17d48e2 | 14992 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 14993 | |
53d9f4e9 | 14994 | if (crtc->active != crtc->base.state->active) { |
02e93c35 | 14995 | struct intel_encoder *encoder; |
24929352 DV |
14996 | |
14997 | /* This can happen either due to bugs in the get_hw_state | |
b17d48e2 ML |
14998 | * functions or because of calls to intel_crtc_disable_noatomic, |
14999 | * or because the pipe is force-enabled due to the | |
24929352 DV |
15000 | * pipe A quirk. */ |
15001 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
15002 | crtc->base.base.id, | |
83d65738 | 15003 | crtc->base.state->enable ? "enabled" : "disabled", |
24929352 DV |
15004 | crtc->active ? "enabled" : "disabled"); |
15005 | ||
4be40c98 | 15006 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0); |
49d6fa21 | 15007 | crtc->base.state->active = crtc->active; |
24929352 DV |
15008 | crtc->base.enabled = crtc->active; |
15009 | ||
15010 | /* Because we only establish the connector -> encoder -> | |
15011 | * crtc links if something is active, this means the | |
15012 | * crtc is now deactivated. Break the links. connector | |
15013 | * -> encoder links are only establish when things are | |
15014 | * actually up, hence no need to break them. */ | |
15015 | WARN_ON(crtc->active); | |
15016 | ||
2d406bb0 | 15017 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
24929352 | 15018 | encoder->base.crtc = NULL; |
24929352 | 15019 | } |
c5ab3bc0 | 15020 | |
a3ed6aad | 15021 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
15022 | /* |
15023 | * We start out with underrun reporting disabled to avoid races. | |
15024 | * For correct bookkeeping mark this on active crtcs. | |
15025 | * | |
c5ab3bc0 DV |
15026 | * Also on gmch platforms we dont have any hardware bits to |
15027 | * disable the underrun reporting. Which means we need to start | |
15028 | * out with underrun reporting disabled also on inactive pipes, | |
15029 | * since otherwise we'll complain about the garbage we read when | |
15030 | * e.g. coming up after runtime pm. | |
15031 | * | |
4cc31489 DV |
15032 | * No protection against concurrent access is required - at |
15033 | * worst a fifo underrun happens which also sets this to false. | |
15034 | */ | |
15035 | crtc->cpu_fifo_underrun_disabled = true; | |
15036 | crtc->pch_fifo_underrun_disabled = true; | |
15037 | } | |
24929352 DV |
15038 | } |
15039 | ||
15040 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
15041 | { | |
15042 | struct intel_connector *connector; | |
15043 | struct drm_device *dev = encoder->base.dev; | |
873ffe69 | 15044 | bool active = false; |
24929352 DV |
15045 | |
15046 | /* We need to check both for a crtc link (meaning that the | |
15047 | * encoder is active and trying to read from a pipe) and the | |
15048 | * pipe itself being active. */ | |
15049 | bool has_active_crtc = encoder->base.crtc && | |
15050 | to_intel_crtc(encoder->base.crtc)->active; | |
15051 | ||
873ffe69 ML |
15052 | for_each_intel_connector(dev, connector) { |
15053 | if (connector->base.encoder != &encoder->base) | |
15054 | continue; | |
15055 | ||
15056 | active = true; | |
15057 | break; | |
15058 | } | |
15059 | ||
15060 | if (active && !has_active_crtc) { | |
24929352 DV |
15061 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
15062 | encoder->base.base.id, | |
8e329a03 | 15063 | encoder->base.name); |
24929352 DV |
15064 | |
15065 | /* Connector is active, but has no active pipe. This is | |
15066 | * fallout from our resume register restoring. Disable | |
15067 | * the encoder manually again. */ | |
15068 | if (encoder->base.crtc) { | |
15069 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
15070 | encoder->base.base.id, | |
8e329a03 | 15071 | encoder->base.name); |
24929352 | 15072 | encoder->disable(encoder); |
a62d1497 VS |
15073 | if (encoder->post_disable) |
15074 | encoder->post_disable(encoder); | |
24929352 | 15075 | } |
7f1950fb | 15076 | encoder->base.crtc = NULL; |
24929352 DV |
15077 | |
15078 | /* Inconsistent output/port/pipe state happens presumably due to | |
15079 | * a bug in one of the get_hw_state functions. Or someplace else | |
15080 | * in our code, like the register restore mess on resume. Clamp | |
15081 | * things to off as a safer default. */ | |
3a3371ff | 15082 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15083 | if (connector->encoder != encoder) |
15084 | continue; | |
7f1950fb EE |
15085 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
15086 | connector->base.encoder = NULL; | |
24929352 DV |
15087 | } |
15088 | } | |
15089 | /* Enabled encoders without active connectors will be fixed in | |
15090 | * the crtc fixup. */ | |
15091 | } | |
15092 | ||
04098753 | 15093 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
15094 | { |
15095 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 15096 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 15097 | |
04098753 ID |
15098 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
15099 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
15100 | i915_disable_vga(dev); | |
15101 | } | |
15102 | } | |
15103 | ||
15104 | void i915_redisable_vga(struct drm_device *dev) | |
15105 | { | |
15106 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15107 | ||
8dc8a27c PZ |
15108 | /* This function can be called both from intel_modeset_setup_hw_state or |
15109 | * at a very early point in our resume sequence, where the power well | |
15110 | * structures are not yet restored. Since this function is at a very | |
15111 | * paranoid "someone might have enabled VGA while we were not looking" | |
15112 | * level, just check if the power well is enabled instead of trying to | |
15113 | * follow the "don't touch the power well if we don't need it" policy | |
15114 | * the rest of the driver uses. */ | |
f458ebbc | 15115 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
15116 | return; |
15117 | ||
04098753 | 15118 | i915_redisable_vga_power_on(dev); |
0fde901f KM |
15119 | } |
15120 | ||
f9cd7b88 | 15121 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 15122 | { |
f9cd7b88 | 15123 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 15124 | |
f9cd7b88 | 15125 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
15126 | } |
15127 | ||
f9cd7b88 VS |
15128 | /* FIXME read out full plane state for all planes */ |
15129 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 15130 | { |
b26d3ea3 | 15131 | struct drm_plane *primary = crtc->base.primary; |
f9cd7b88 | 15132 | struct intel_plane_state *plane_state = |
b26d3ea3 | 15133 | to_intel_plane_state(primary->state); |
d032ffa0 | 15134 | |
f9cd7b88 | 15135 | plane_state->visible = |
b26d3ea3 ML |
15136 | primary_get_hw_state(to_intel_plane(primary)); |
15137 | ||
15138 | if (plane_state->visible) | |
15139 | crtc->base.state->plane_mask |= 1 << drm_plane_index(primary); | |
98ec7739 VS |
15140 | } |
15141 | ||
30e984df | 15142 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
15143 | { |
15144 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15145 | enum pipe pipe; | |
24929352 DV |
15146 | struct intel_crtc *crtc; |
15147 | struct intel_encoder *encoder; | |
15148 | struct intel_connector *connector; | |
5358901f | 15149 | int i; |
24929352 | 15150 | |
d3fcc808 | 15151 | for_each_intel_crtc(dev, crtc) { |
b06f8b0d | 15152 | __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state); |
6e3c9717 | 15153 | memset(crtc->config, 0, sizeof(*crtc->config)); |
f7217905 | 15154 | crtc->config->base.crtc = &crtc->base; |
3b117c8f | 15155 | |
0e8ffe1b | 15156 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
6e3c9717 | 15157 | crtc->config); |
24929352 | 15158 | |
49d6fa21 | 15159 | crtc->base.state->active = crtc->active; |
24929352 | 15160 | crtc->base.enabled = crtc->active; |
b70709a6 | 15161 | |
f9cd7b88 | 15162 | readout_plane_state(crtc); |
24929352 DV |
15163 | |
15164 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
15165 | crtc->base.base.id, | |
15166 | crtc->active ? "enabled" : "disabled"); | |
15167 | } | |
15168 | ||
5358901f DV |
15169 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15170 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15171 | ||
3e369b76 ACO |
15172 | pll->on = pll->get_hw_state(dev_priv, pll, |
15173 | &pll->config.hw_state); | |
5358901f | 15174 | pll->active = 0; |
3e369b76 | 15175 | pll->config.crtc_mask = 0; |
d3fcc808 | 15176 | for_each_intel_crtc(dev, crtc) { |
1e6f2ddc | 15177 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) { |
5358901f | 15178 | pll->active++; |
3e369b76 | 15179 | pll->config.crtc_mask |= 1 << crtc->pipe; |
1e6f2ddc | 15180 | } |
5358901f | 15181 | } |
5358901f | 15182 | |
1e6f2ddc | 15183 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 15184 | pll->name, pll->config.crtc_mask, pll->on); |
bd2bb1b9 | 15185 | |
3e369b76 | 15186 | if (pll->config.crtc_mask) |
bd2bb1b9 | 15187 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
5358901f DV |
15188 | } |
15189 | ||
b2784e15 | 15190 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15191 | pipe = 0; |
15192 | ||
15193 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
15194 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15195 | encoder->base.crtc = &crtc->base; | |
6e3c9717 | 15196 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
15197 | } else { |
15198 | encoder->base.crtc = NULL; | |
15199 | } | |
15200 | ||
6f2bcceb | 15201 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 15202 | encoder->base.base.id, |
8e329a03 | 15203 | encoder->base.name, |
24929352 | 15204 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 15205 | pipe_name(pipe)); |
24929352 DV |
15206 | } |
15207 | ||
3a3371ff | 15208 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15209 | if (connector->get_hw_state(connector)) { |
15210 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
24929352 DV |
15211 | connector->base.encoder = &connector->encoder->base; |
15212 | } else { | |
15213 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
15214 | connector->base.encoder = NULL; | |
15215 | } | |
15216 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
15217 | connector->base.base.id, | |
c23cc417 | 15218 | connector->base.name, |
24929352 DV |
15219 | connector->base.encoder ? "enabled" : "disabled"); |
15220 | } | |
7f4c6284 VS |
15221 | |
15222 | for_each_intel_crtc(dev, crtc) { | |
15223 | crtc->base.hwmode = crtc->config->base.adjusted_mode; | |
15224 | ||
15225 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); | |
15226 | if (crtc->base.state->active) { | |
15227 | intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); | |
15228 | intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config); | |
15229 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); | |
15230 | ||
15231 | /* | |
15232 | * The initial mode needs to be set in order to keep | |
15233 | * the atomic core happy. It wants a valid mode if the | |
15234 | * crtc's enabled, so we do the above call. | |
15235 | * | |
15236 | * At this point some state updated by the connectors | |
15237 | * in their ->detect() callback has not run yet, so | |
15238 | * no recalculation can be done yet. | |
15239 | * | |
15240 | * Even if we could do a recalculation and modeset | |
15241 | * right now it would cause a double modeset if | |
15242 | * fbdev or userspace chooses a different initial mode. | |
15243 | * | |
15244 | * If that happens, someone indicated they wanted a | |
15245 | * mode change, which means it's safe to do a full | |
15246 | * recalculation. | |
15247 | */ | |
15248 | crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED; | |
9eca6832 VS |
15249 | |
15250 | drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); | |
15251 | update_scanline_offset(crtc); | |
7f4c6284 VS |
15252 | } |
15253 | } | |
30e984df DV |
15254 | } |
15255 | ||
043e9bda ML |
15256 | /* Scan out the current hw modeset state, |
15257 | * and sanitizes it to the current state | |
15258 | */ | |
15259 | static void | |
15260 | intel_modeset_setup_hw_state(struct drm_device *dev) | |
30e984df DV |
15261 | { |
15262 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15263 | enum pipe pipe; | |
30e984df DV |
15264 | struct intel_crtc *crtc; |
15265 | struct intel_encoder *encoder; | |
35c95375 | 15266 | int i; |
30e984df DV |
15267 | |
15268 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
15269 | |
15270 | /* HW state is read out, now we need to sanitize this mess. */ | |
b2784e15 | 15271 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15272 | intel_sanitize_encoder(encoder); |
15273 | } | |
15274 | ||
055e393f | 15275 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
15276 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15277 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
15278 | intel_dump_pipe_config(crtc, crtc->config, |
15279 | "[setup_hw_state]"); | |
24929352 | 15280 | } |
9a935856 | 15281 | |
d29b2f9d ACO |
15282 | intel_modeset_update_connector_atomic_state(dev); |
15283 | ||
35c95375 DV |
15284 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15285 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15286 | ||
15287 | if (!pll->on || pll->active) | |
15288 | continue; | |
15289 | ||
15290 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
15291 | ||
15292 | pll->disable(dev_priv, pll); | |
15293 | pll->on = false; | |
15294 | } | |
15295 | ||
26e1fe4f | 15296 | if (IS_VALLEYVIEW(dev)) |
6eb1a681 VS |
15297 | vlv_wm_get_hw_state(dev); |
15298 | else if (IS_GEN9(dev)) | |
3078999f PB |
15299 | skl_wm_get_hw_state(dev); |
15300 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 | 15301 | ilk_wm_get_hw_state(dev); |
292b990e ML |
15302 | |
15303 | for_each_intel_crtc(dev, crtc) { | |
15304 | unsigned long put_domains; | |
15305 | ||
15306 | put_domains = modeset_get_crtc_power_domains(&crtc->base); | |
15307 | if (WARN_ON(put_domains)) | |
15308 | modeset_put_power_domains(dev_priv, put_domains); | |
15309 | } | |
15310 | intel_display_set_init_power(dev_priv, false); | |
043e9bda | 15311 | } |
7d0bc1ea | 15312 | |
043e9bda ML |
15313 | void intel_display_resume(struct drm_device *dev) |
15314 | { | |
15315 | struct drm_atomic_state *state = drm_atomic_state_alloc(dev); | |
15316 | struct intel_connector *conn; | |
15317 | struct intel_plane *plane; | |
15318 | struct drm_crtc *crtc; | |
15319 | int ret; | |
f30da187 | 15320 | |
043e9bda ML |
15321 | if (!state) |
15322 | return; | |
15323 | ||
15324 | state->acquire_ctx = dev->mode_config.acquire_ctx; | |
15325 | ||
15326 | /* preserve complete old state, including dpll */ | |
15327 | intel_atomic_get_shared_dpll_state(state); | |
15328 | ||
15329 | for_each_crtc(dev, crtc) { | |
15330 | struct drm_crtc_state *crtc_state = | |
15331 | drm_atomic_get_crtc_state(state, crtc); | |
15332 | ||
15333 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
15334 | if (ret) | |
15335 | goto err; | |
15336 | ||
15337 | /* force a restore */ | |
15338 | crtc_state->mode_changed = true; | |
45e2b5f6 | 15339 | } |
8af6cf88 | 15340 | |
043e9bda ML |
15341 | for_each_intel_plane(dev, plane) { |
15342 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base)); | |
15343 | if (ret) | |
15344 | goto err; | |
15345 | } | |
15346 | ||
15347 | for_each_intel_connector(dev, conn) { | |
15348 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base)); | |
15349 | if (ret) | |
15350 | goto err; | |
15351 | } | |
15352 | ||
15353 | intel_modeset_setup_hw_state(dev); | |
15354 | ||
15355 | i915_redisable_vga(dev); | |
74c090b1 | 15356 | ret = drm_atomic_commit(state); |
043e9bda ML |
15357 | if (!ret) |
15358 | return; | |
15359 | ||
15360 | err: | |
15361 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
15362 | drm_atomic_state_free(state); | |
2c7111db CW |
15363 | } |
15364 | ||
15365 | void intel_modeset_gem_init(struct drm_device *dev) | |
15366 | { | |
484b41dd | 15367 | struct drm_crtc *c; |
2ff8fde1 | 15368 | struct drm_i915_gem_object *obj; |
e0d6149b | 15369 | int ret; |
484b41dd | 15370 | |
ae48434c ID |
15371 | mutex_lock(&dev->struct_mutex); |
15372 | intel_init_gt_powersave(dev); | |
15373 | mutex_unlock(&dev->struct_mutex); | |
15374 | ||
1833b134 | 15375 | intel_modeset_init_hw(dev); |
02e792fb DV |
15376 | |
15377 | intel_setup_overlay(dev); | |
484b41dd JB |
15378 | |
15379 | /* | |
15380 | * Make sure any fbs we allocated at startup are properly | |
15381 | * pinned & fenced. When we do the allocation it's too early | |
15382 | * for this. | |
15383 | */ | |
70e1e0ec | 15384 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
15385 | obj = intel_fb_obj(c->primary->fb); |
15386 | if (obj == NULL) | |
484b41dd JB |
15387 | continue; |
15388 | ||
e0d6149b TU |
15389 | mutex_lock(&dev->struct_mutex); |
15390 | ret = intel_pin_and_fence_fb_obj(c->primary, | |
15391 | c->primary->fb, | |
15392 | c->primary->state, | |
91af127f | 15393 | NULL, NULL); |
e0d6149b TU |
15394 | mutex_unlock(&dev->struct_mutex); |
15395 | if (ret) { | |
484b41dd JB |
15396 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
15397 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
15398 | drm_framebuffer_unreference(c->primary->fb); |
15399 | c->primary->fb = NULL; | |
36750f28 | 15400 | c->primary->crtc = c->primary->state->crtc = NULL; |
afd65eb4 | 15401 | update_state_fb(c->primary); |
36750f28 | 15402 | c->state->plane_mask &= ~(1 << drm_plane_index(c->primary)); |
484b41dd JB |
15403 | } |
15404 | } | |
0962c3c9 VS |
15405 | |
15406 | intel_backlight_register(dev); | |
79e53945 JB |
15407 | } |
15408 | ||
4932e2c3 ID |
15409 | void intel_connector_unregister(struct intel_connector *intel_connector) |
15410 | { | |
15411 | struct drm_connector *connector = &intel_connector->base; | |
15412 | ||
15413 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 15414 | drm_connector_unregister(connector); |
4932e2c3 ID |
15415 | } |
15416 | ||
79e53945 JB |
15417 | void intel_modeset_cleanup(struct drm_device *dev) |
15418 | { | |
652c393a | 15419 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9255d57 | 15420 | struct drm_connector *connector; |
652c393a | 15421 | |
2eb5252e ID |
15422 | intel_disable_gt_powersave(dev); |
15423 | ||
0962c3c9 VS |
15424 | intel_backlight_unregister(dev); |
15425 | ||
fd0c0642 DV |
15426 | /* |
15427 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 15428 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
15429 | * experience fancy races otherwise. |
15430 | */ | |
2aeb7d3a | 15431 | intel_irq_uninstall(dev_priv); |
eb21b92b | 15432 | |
fd0c0642 DV |
15433 | /* |
15434 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
15435 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
15436 | */ | |
f87ea761 | 15437 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 15438 | |
723bfd70 JB |
15439 | intel_unregister_dsm_handler(); |
15440 | ||
7733b49b | 15441 | intel_fbc_disable(dev_priv); |
69341a5e | 15442 | |
1630fe75 CW |
15443 | /* flush any delayed tasks or pending work */ |
15444 | flush_scheduled_work(); | |
15445 | ||
db31af1d JN |
15446 | /* destroy the backlight and sysfs files before encoders/connectors */ |
15447 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4932e2c3 ID |
15448 | struct intel_connector *intel_connector; |
15449 | ||
15450 | intel_connector = to_intel_connector(connector); | |
15451 | intel_connector->unregister(intel_connector); | |
db31af1d | 15452 | } |
d9255d57 | 15453 | |
79e53945 | 15454 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
15455 | |
15456 | intel_cleanup_overlay(dev); | |
ae48434c ID |
15457 | |
15458 | mutex_lock(&dev->struct_mutex); | |
15459 | intel_cleanup_gt_powersave(dev); | |
15460 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
15461 | } |
15462 | ||
f1c79df3 ZW |
15463 | /* |
15464 | * Return which encoder is currently attached for connector. | |
15465 | */ | |
df0e9248 | 15466 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 15467 | { |
df0e9248 CW |
15468 | return &intel_attached_encoder(connector)->base; |
15469 | } | |
f1c79df3 | 15470 | |
df0e9248 CW |
15471 | void intel_connector_attach_encoder(struct intel_connector *connector, |
15472 | struct intel_encoder *encoder) | |
15473 | { | |
15474 | connector->encoder = encoder; | |
15475 | drm_mode_connector_attach_encoder(&connector->base, | |
15476 | &encoder->base); | |
79e53945 | 15477 | } |
28d52043 DA |
15478 | |
15479 | /* | |
15480 | * set vga decode state - true == enable VGA decode | |
15481 | */ | |
15482 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
15483 | { | |
15484 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 15485 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
15486 | u16 gmch_ctrl; |
15487 | ||
75fa041d CW |
15488 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
15489 | DRM_ERROR("failed to read control word\n"); | |
15490 | return -EIO; | |
15491 | } | |
15492 | ||
c0cc8a55 CW |
15493 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
15494 | return 0; | |
15495 | ||
28d52043 DA |
15496 | if (state) |
15497 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
15498 | else | |
15499 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
15500 | |
15501 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
15502 | DRM_ERROR("failed to write control word\n"); | |
15503 | return -EIO; | |
15504 | } | |
15505 | ||
28d52043 DA |
15506 | return 0; |
15507 | } | |
c4a1d9e4 | 15508 | |
c4a1d9e4 | 15509 | struct intel_display_error_state { |
ff57f1b0 PZ |
15510 | |
15511 | u32 power_well_driver; | |
15512 | ||
63b66e5b CW |
15513 | int num_transcoders; |
15514 | ||
c4a1d9e4 CW |
15515 | struct intel_cursor_error_state { |
15516 | u32 control; | |
15517 | u32 position; | |
15518 | u32 base; | |
15519 | u32 size; | |
52331309 | 15520 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15521 | |
15522 | struct intel_pipe_error_state { | |
ddf9c536 | 15523 | bool power_domain_on; |
c4a1d9e4 | 15524 | u32 source; |
f301b1e1 | 15525 | u32 stat; |
52331309 | 15526 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15527 | |
15528 | struct intel_plane_error_state { | |
15529 | u32 control; | |
15530 | u32 stride; | |
15531 | u32 size; | |
15532 | u32 pos; | |
15533 | u32 addr; | |
15534 | u32 surface; | |
15535 | u32 tile_offset; | |
52331309 | 15536 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
15537 | |
15538 | struct intel_transcoder_error_state { | |
ddf9c536 | 15539 | bool power_domain_on; |
63b66e5b CW |
15540 | enum transcoder cpu_transcoder; |
15541 | ||
15542 | u32 conf; | |
15543 | ||
15544 | u32 htotal; | |
15545 | u32 hblank; | |
15546 | u32 hsync; | |
15547 | u32 vtotal; | |
15548 | u32 vblank; | |
15549 | u32 vsync; | |
15550 | } transcoder[4]; | |
c4a1d9e4 CW |
15551 | }; |
15552 | ||
15553 | struct intel_display_error_state * | |
15554 | intel_display_capture_error_state(struct drm_device *dev) | |
15555 | { | |
fbee40df | 15556 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 15557 | struct intel_display_error_state *error; |
63b66e5b CW |
15558 | int transcoders[] = { |
15559 | TRANSCODER_A, | |
15560 | TRANSCODER_B, | |
15561 | TRANSCODER_C, | |
15562 | TRANSCODER_EDP, | |
15563 | }; | |
c4a1d9e4 CW |
15564 | int i; |
15565 | ||
63b66e5b CW |
15566 | if (INTEL_INFO(dev)->num_pipes == 0) |
15567 | return NULL; | |
15568 | ||
9d1cb914 | 15569 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
15570 | if (error == NULL) |
15571 | return NULL; | |
15572 | ||
190be112 | 15573 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
15574 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
15575 | ||
055e393f | 15576 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 15577 | error->pipe[i].power_domain_on = |
f458ebbc DV |
15578 | __intel_display_power_is_enabled(dev_priv, |
15579 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 15580 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
15581 | continue; |
15582 | ||
5efb3e28 VS |
15583 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
15584 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
15585 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
15586 | |
15587 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
15588 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 15589 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 15590 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
15591 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
15592 | } | |
ca291363 PZ |
15593 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
15594 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
15595 | if (INTEL_INFO(dev)->gen >= 4) { |
15596 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
15597 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
15598 | } | |
15599 | ||
c4a1d9e4 | 15600 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 15601 | |
3abfce77 | 15602 | if (HAS_GMCH_DISPLAY(dev)) |
f301b1e1 | 15603 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
15604 | } |
15605 | ||
15606 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
15607 | if (HAS_DDI(dev_priv->dev)) | |
15608 | error->num_transcoders++; /* Account for eDP. */ | |
15609 | ||
15610 | for (i = 0; i < error->num_transcoders; i++) { | |
15611 | enum transcoder cpu_transcoder = transcoders[i]; | |
15612 | ||
ddf9c536 | 15613 | error->transcoder[i].power_domain_on = |
f458ebbc | 15614 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 15615 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 15616 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
15617 | continue; |
15618 | ||
63b66e5b CW |
15619 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
15620 | ||
15621 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
15622 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
15623 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
15624 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
15625 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
15626 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
15627 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
15628 | } |
15629 | ||
15630 | return error; | |
15631 | } | |
15632 | ||
edc3d884 MK |
15633 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
15634 | ||
c4a1d9e4 | 15635 | void |
edc3d884 | 15636 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
15637 | struct drm_device *dev, |
15638 | struct intel_display_error_state *error) | |
15639 | { | |
055e393f | 15640 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
15641 | int i; |
15642 | ||
63b66e5b CW |
15643 | if (!error) |
15644 | return; | |
15645 | ||
edc3d884 | 15646 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 15647 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 15648 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 15649 | error->power_well_driver); |
055e393f | 15650 | for_each_pipe(dev_priv, i) { |
edc3d884 | 15651 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 ID |
15652 | err_printf(m, " Power: %s\n", |
15653 | error->pipe[i].power_domain_on ? "on" : "off"); | |
edc3d884 | 15654 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 15655 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
15656 | |
15657 | err_printf(m, "Plane [%d]:\n", i); | |
15658 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
15659 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 15660 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
15661 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
15662 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 15663 | } |
4b71a570 | 15664 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 15665 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 15666 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
15667 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
15668 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
15669 | } |
15670 | ||
edc3d884 MK |
15671 | err_printf(m, "Cursor [%d]:\n", i); |
15672 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
15673 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
15674 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 15675 | } |
63b66e5b CW |
15676 | |
15677 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 15678 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 15679 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 ID |
15680 | err_printf(m, " Power: %s\n", |
15681 | error->transcoder[i].power_domain_on ? "on" : "off"); | |
63b66e5b CW |
15682 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
15683 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
15684 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
15685 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
15686 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
15687 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
15688 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
15689 | } | |
c4a1d9e4 | 15690 | } |
e2fcdaa9 VS |
15691 | |
15692 | void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file) | |
15693 | { | |
15694 | struct intel_crtc *crtc; | |
15695 | ||
15696 | for_each_intel_crtc(dev, crtc) { | |
15697 | struct intel_unpin_work *work; | |
e2fcdaa9 | 15698 | |
5e2d7afc | 15699 | spin_lock_irq(&dev->event_lock); |
e2fcdaa9 VS |
15700 | |
15701 | work = crtc->unpin_work; | |
15702 | ||
15703 | if (work && work->event && | |
15704 | work->event->base.file_priv == file) { | |
15705 | kfree(work->event); | |
15706 | work->event = NULL; | |
15707 | } | |
15708 | ||
5e2d7afc | 15709 | spin_unlock_irq(&dev->event_lock); |
e2fcdaa9 VS |
15710 | } |
15711 | } |