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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
760285e7 DH |
40 | #include <drm/drm_dp_helper.h> |
41 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
42 | #include <drm/drm_plane_helper.h> |
43 | #include <drm/drm_rect.h> | |
c0f372b3 | 44 | #include <linux/dma_remapping.h> |
79e53945 | 45 | |
465c120c MR |
46 | /* Primary plane formats supported by all gen */ |
47 | #define COMMON_PRIMARY_FORMATS \ | |
48 | DRM_FORMAT_C8, \ | |
49 | DRM_FORMAT_RGB565, \ | |
50 | DRM_FORMAT_XRGB8888, \ | |
51 | DRM_FORMAT_ARGB8888 | |
52 | ||
53 | /* Primary plane formats for gen <= 3 */ | |
54 | static const uint32_t intel_primary_formats_gen2[] = { | |
55 | COMMON_PRIMARY_FORMATS, | |
56 | DRM_FORMAT_XRGB1555, | |
57 | DRM_FORMAT_ARGB1555, | |
58 | }; | |
59 | ||
60 | /* Primary plane formats for gen >= 4 */ | |
61 | static const uint32_t intel_primary_formats_gen4[] = { | |
62 | COMMON_PRIMARY_FORMATS, \ | |
63 | DRM_FORMAT_XBGR8888, | |
64 | DRM_FORMAT_ABGR8888, | |
65 | DRM_FORMAT_XRGB2101010, | |
66 | DRM_FORMAT_ARGB2101010, | |
67 | DRM_FORMAT_XBGR2101010, | |
68 | DRM_FORMAT_ABGR2101010, | |
69 | }; | |
70 | ||
3d7d6510 MR |
71 | /* Cursor formats */ |
72 | static const uint32_t intel_cursor_formats[] = { | |
73 | DRM_FORMAT_ARGB8888, | |
74 | }; | |
75 | ||
ef9348c8 | 76 | #define DIV_ROUND_CLOSEST_ULL(ll, d) \ |
465c120c | 77 | ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; }) |
ef9348c8 | 78 | |
cc36513c DV |
79 | static void intel_increase_pllclock(struct drm_device *dev, |
80 | enum pipe pipe); | |
6b383a7f | 81 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 82 | |
f1f644dc JB |
83 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
84 | struct intel_crtc_config *pipe_config); | |
18442d08 VS |
85 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
86 | struct intel_crtc_config *pipe_config); | |
f1f644dc | 87 | |
e7457a9a DL |
88 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
89 | int x, int y, struct drm_framebuffer *old_fb); | |
eb1bfe80 JB |
90 | static int intel_framebuffer_init(struct drm_device *dev, |
91 | struct intel_framebuffer *ifb, | |
92 | struct drm_mode_fb_cmd2 *mode_cmd, | |
93 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
94 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
95 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
29407aab | 96 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
97 | struct intel_link_m_n *m_n, |
98 | struct intel_link_m_n *m2_n2); | |
29407aab | 99 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 DV |
100 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
101 | static void intel_set_pipe_csc(struct drm_crtc *crtc); | |
bdd4b6a6 | 102 | static void vlv_prepare_pll(struct intel_crtc *crtc); |
1ae0d137 | 103 | static void chv_prepare_pll(struct intel_crtc *crtc); |
e7457a9a | 104 | |
0e32b39c DA |
105 | static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe) |
106 | { | |
107 | if (!connector->mst_port) | |
108 | return connector->encoder; | |
109 | else | |
110 | return &connector->mst_port->mst_encoders[pipe]->base; | |
111 | } | |
112 | ||
79e53945 | 113 | typedef struct { |
0206e353 | 114 | int min, max; |
79e53945 JB |
115 | } intel_range_t; |
116 | ||
117 | typedef struct { | |
0206e353 AJ |
118 | int dot_limit; |
119 | int p2_slow, p2_fast; | |
79e53945 JB |
120 | } intel_p2_t; |
121 | ||
d4906093 ML |
122 | typedef struct intel_limit intel_limit_t; |
123 | struct intel_limit { | |
0206e353 AJ |
124 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
125 | intel_p2_t p2; | |
d4906093 | 126 | }; |
79e53945 | 127 | |
d2acd215 DV |
128 | int |
129 | intel_pch_rawclk(struct drm_device *dev) | |
130 | { | |
131 | struct drm_i915_private *dev_priv = dev->dev_private; | |
132 | ||
133 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
134 | ||
135 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
136 | } | |
137 | ||
021357ac CW |
138 | static inline u32 /* units of 100MHz */ |
139 | intel_fdi_link_freq(struct drm_device *dev) | |
140 | { | |
8b99e68c CW |
141 | if (IS_GEN5(dev)) { |
142 | struct drm_i915_private *dev_priv = dev->dev_private; | |
143 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
144 | } else | |
145 | return 27; | |
021357ac CW |
146 | } |
147 | ||
5d536e28 | 148 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 149 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 150 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 151 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
152 | .m = { .min = 96, .max = 140 }, |
153 | .m1 = { .min = 18, .max = 26 }, | |
154 | .m2 = { .min = 6, .max = 16 }, | |
155 | .p = { .min = 4, .max = 128 }, | |
156 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
157 | .p2 = { .dot_limit = 165000, |
158 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
159 | }; |
160 | ||
5d536e28 DV |
161 | static const intel_limit_t intel_limits_i8xx_dvo = { |
162 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 163 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 164 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
165 | .m = { .min = 96, .max = 140 }, |
166 | .m1 = { .min = 18, .max = 26 }, | |
167 | .m2 = { .min = 6, .max = 16 }, | |
168 | .p = { .min = 4, .max = 128 }, | |
169 | .p1 = { .min = 2, .max = 33 }, | |
170 | .p2 = { .dot_limit = 165000, | |
171 | .p2_slow = 4, .p2_fast = 4 }, | |
172 | }; | |
173 | ||
e4b36699 | 174 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 175 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 176 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 177 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
178 | .m = { .min = 96, .max = 140 }, |
179 | .m1 = { .min = 18, .max = 26 }, | |
180 | .m2 = { .min = 6, .max = 16 }, | |
181 | .p = { .min = 4, .max = 128 }, | |
182 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
183 | .p2 = { .dot_limit = 165000, |
184 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 185 | }; |
273e27ca | 186 | |
e4b36699 | 187 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
188 | .dot = { .min = 20000, .max = 400000 }, |
189 | .vco = { .min = 1400000, .max = 2800000 }, | |
190 | .n = { .min = 1, .max = 6 }, | |
191 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
192 | .m1 = { .min = 8, .max = 18 }, |
193 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
194 | .p = { .min = 5, .max = 80 }, |
195 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
196 | .p2 = { .dot_limit = 200000, |
197 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
198 | }; |
199 | ||
200 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
201 | .dot = { .min = 20000, .max = 400000 }, |
202 | .vco = { .min = 1400000, .max = 2800000 }, | |
203 | .n = { .min = 1, .max = 6 }, | |
204 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
205 | .m1 = { .min = 8, .max = 18 }, |
206 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
207 | .p = { .min = 7, .max = 98 }, |
208 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
209 | .p2 = { .dot_limit = 112000, |
210 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
211 | }; |
212 | ||
273e27ca | 213 | |
e4b36699 | 214 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
215 | .dot = { .min = 25000, .max = 270000 }, |
216 | .vco = { .min = 1750000, .max = 3500000}, | |
217 | .n = { .min = 1, .max = 4 }, | |
218 | .m = { .min = 104, .max = 138 }, | |
219 | .m1 = { .min = 17, .max = 23 }, | |
220 | .m2 = { .min = 5, .max = 11 }, | |
221 | .p = { .min = 10, .max = 30 }, | |
222 | .p1 = { .min = 1, .max = 3}, | |
223 | .p2 = { .dot_limit = 270000, | |
224 | .p2_slow = 10, | |
225 | .p2_fast = 10 | |
044c7c41 | 226 | }, |
e4b36699 KP |
227 | }; |
228 | ||
229 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
230 | .dot = { .min = 22000, .max = 400000 }, |
231 | .vco = { .min = 1750000, .max = 3500000}, | |
232 | .n = { .min = 1, .max = 4 }, | |
233 | .m = { .min = 104, .max = 138 }, | |
234 | .m1 = { .min = 16, .max = 23 }, | |
235 | .m2 = { .min = 5, .max = 11 }, | |
236 | .p = { .min = 5, .max = 80 }, | |
237 | .p1 = { .min = 1, .max = 8}, | |
238 | .p2 = { .dot_limit = 165000, | |
239 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
240 | }; |
241 | ||
242 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
243 | .dot = { .min = 20000, .max = 115000 }, |
244 | .vco = { .min = 1750000, .max = 3500000 }, | |
245 | .n = { .min = 1, .max = 3 }, | |
246 | .m = { .min = 104, .max = 138 }, | |
247 | .m1 = { .min = 17, .max = 23 }, | |
248 | .m2 = { .min = 5, .max = 11 }, | |
249 | .p = { .min = 28, .max = 112 }, | |
250 | .p1 = { .min = 2, .max = 8 }, | |
251 | .p2 = { .dot_limit = 0, | |
252 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 253 | }, |
e4b36699 KP |
254 | }; |
255 | ||
256 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
257 | .dot = { .min = 80000, .max = 224000 }, |
258 | .vco = { .min = 1750000, .max = 3500000 }, | |
259 | .n = { .min = 1, .max = 3 }, | |
260 | .m = { .min = 104, .max = 138 }, | |
261 | .m1 = { .min = 17, .max = 23 }, | |
262 | .m2 = { .min = 5, .max = 11 }, | |
263 | .p = { .min = 14, .max = 42 }, | |
264 | .p1 = { .min = 2, .max = 6 }, | |
265 | .p2 = { .dot_limit = 0, | |
266 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 267 | }, |
e4b36699 KP |
268 | }; |
269 | ||
f2b115e6 | 270 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
271 | .dot = { .min = 20000, .max = 400000}, |
272 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 273 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
274 | .n = { .min = 3, .max = 6 }, |
275 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 276 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
277 | .m1 = { .min = 0, .max = 0 }, |
278 | .m2 = { .min = 0, .max = 254 }, | |
279 | .p = { .min = 5, .max = 80 }, | |
280 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
281 | .p2 = { .dot_limit = 200000, |
282 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
283 | }; |
284 | ||
f2b115e6 | 285 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
286 | .dot = { .min = 20000, .max = 400000 }, |
287 | .vco = { .min = 1700000, .max = 3500000 }, | |
288 | .n = { .min = 3, .max = 6 }, | |
289 | .m = { .min = 2, .max = 256 }, | |
290 | .m1 = { .min = 0, .max = 0 }, | |
291 | .m2 = { .min = 0, .max = 254 }, | |
292 | .p = { .min = 7, .max = 112 }, | |
293 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
294 | .p2 = { .dot_limit = 112000, |
295 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
296 | }; |
297 | ||
273e27ca EA |
298 | /* Ironlake / Sandybridge |
299 | * | |
300 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
301 | * the range value for them is (actual_value - 2). | |
302 | */ | |
b91ad0ec | 303 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
304 | .dot = { .min = 25000, .max = 350000 }, |
305 | .vco = { .min = 1760000, .max = 3510000 }, | |
306 | .n = { .min = 1, .max = 5 }, | |
307 | .m = { .min = 79, .max = 127 }, | |
308 | .m1 = { .min = 12, .max = 22 }, | |
309 | .m2 = { .min = 5, .max = 9 }, | |
310 | .p = { .min = 5, .max = 80 }, | |
311 | .p1 = { .min = 1, .max = 8 }, | |
312 | .p2 = { .dot_limit = 225000, | |
313 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
314 | }; |
315 | ||
b91ad0ec | 316 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
317 | .dot = { .min = 25000, .max = 350000 }, |
318 | .vco = { .min = 1760000, .max = 3510000 }, | |
319 | .n = { .min = 1, .max = 3 }, | |
320 | .m = { .min = 79, .max = 118 }, | |
321 | .m1 = { .min = 12, .max = 22 }, | |
322 | .m2 = { .min = 5, .max = 9 }, | |
323 | .p = { .min = 28, .max = 112 }, | |
324 | .p1 = { .min = 2, .max = 8 }, | |
325 | .p2 = { .dot_limit = 225000, | |
326 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
327 | }; |
328 | ||
329 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
330 | .dot = { .min = 25000, .max = 350000 }, |
331 | .vco = { .min = 1760000, .max = 3510000 }, | |
332 | .n = { .min = 1, .max = 3 }, | |
333 | .m = { .min = 79, .max = 127 }, | |
334 | .m1 = { .min = 12, .max = 22 }, | |
335 | .m2 = { .min = 5, .max = 9 }, | |
336 | .p = { .min = 14, .max = 56 }, | |
337 | .p1 = { .min = 2, .max = 8 }, | |
338 | .p2 = { .dot_limit = 225000, | |
339 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
340 | }; |
341 | ||
273e27ca | 342 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 343 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
344 | .dot = { .min = 25000, .max = 350000 }, |
345 | .vco = { .min = 1760000, .max = 3510000 }, | |
346 | .n = { .min = 1, .max = 2 }, | |
347 | .m = { .min = 79, .max = 126 }, | |
348 | .m1 = { .min = 12, .max = 22 }, | |
349 | .m2 = { .min = 5, .max = 9 }, | |
350 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 351 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
352 | .p2 = { .dot_limit = 225000, |
353 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
354 | }; |
355 | ||
356 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
357 | .dot = { .min = 25000, .max = 350000 }, |
358 | .vco = { .min = 1760000, .max = 3510000 }, | |
359 | .n = { .min = 1, .max = 3 }, | |
360 | .m = { .min = 79, .max = 126 }, | |
361 | .m1 = { .min = 12, .max = 22 }, | |
362 | .m2 = { .min = 5, .max = 9 }, | |
363 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 364 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
365 | .p2 = { .dot_limit = 225000, |
366 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
367 | }; |
368 | ||
dc730512 | 369 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
370 | /* |
371 | * These are the data rate limits (measured in fast clocks) | |
372 | * since those are the strictest limits we have. The fast | |
373 | * clock and actual rate limits are more relaxed, so checking | |
374 | * them would make no difference. | |
375 | */ | |
376 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 377 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 378 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
379 | .m1 = { .min = 2, .max = 3 }, |
380 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 381 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 382 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
383 | }; |
384 | ||
ef9348c8 CML |
385 | static const intel_limit_t intel_limits_chv = { |
386 | /* | |
387 | * These are the data rate limits (measured in fast clocks) | |
388 | * since those are the strictest limits we have. The fast | |
389 | * clock and actual rate limits are more relaxed, so checking | |
390 | * them would make no difference. | |
391 | */ | |
392 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
393 | .vco = { .min = 4860000, .max = 6700000 }, | |
394 | .n = { .min = 1, .max = 1 }, | |
395 | .m1 = { .min = 2, .max = 2 }, | |
396 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
397 | .p1 = { .min = 2, .max = 4 }, | |
398 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
399 | }; | |
400 | ||
6b4bf1c4 VS |
401 | static void vlv_clock(int refclk, intel_clock_t *clock) |
402 | { | |
403 | clock->m = clock->m1 * clock->m2; | |
404 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
405 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
406 | return; | |
fb03ac01 VS |
407 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
408 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
6b4bf1c4 VS |
409 | } |
410 | ||
e0638cdf PZ |
411 | /** |
412 | * Returns whether any output on the specified pipe is of the specified type | |
413 | */ | |
414 | static bool intel_pipe_has_type(struct drm_crtc *crtc, int type) | |
415 | { | |
416 | struct drm_device *dev = crtc->dev; | |
417 | struct intel_encoder *encoder; | |
418 | ||
419 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
420 | if (encoder->type == type) | |
421 | return true; | |
422 | ||
423 | return false; | |
424 | } | |
425 | ||
1b894b59 CW |
426 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
427 | int refclk) | |
2c07245f | 428 | { |
b91ad0ec | 429 | struct drm_device *dev = crtc->dev; |
2c07245f | 430 | const intel_limit_t *limit; |
b91ad0ec ZW |
431 | |
432 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 433 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 434 | if (refclk == 100000) |
b91ad0ec ZW |
435 | limit = &intel_limits_ironlake_dual_lvds_100m; |
436 | else | |
437 | limit = &intel_limits_ironlake_dual_lvds; | |
438 | } else { | |
1b894b59 | 439 | if (refclk == 100000) |
b91ad0ec ZW |
440 | limit = &intel_limits_ironlake_single_lvds_100m; |
441 | else | |
442 | limit = &intel_limits_ironlake_single_lvds; | |
443 | } | |
c6bb3538 | 444 | } else |
b91ad0ec | 445 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
446 | |
447 | return limit; | |
448 | } | |
449 | ||
044c7c41 ML |
450 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
451 | { | |
452 | struct drm_device *dev = crtc->dev; | |
044c7c41 ML |
453 | const intel_limit_t *limit; |
454 | ||
455 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 456 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 457 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 458 | else |
e4b36699 | 459 | limit = &intel_limits_g4x_single_channel_lvds; |
044c7c41 ML |
460 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
461 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 462 | limit = &intel_limits_g4x_hdmi; |
044c7c41 | 463 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 464 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 465 | } else /* The option is for other outputs */ |
e4b36699 | 466 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
467 | |
468 | return limit; | |
469 | } | |
470 | ||
1b894b59 | 471 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
79e53945 JB |
472 | { |
473 | struct drm_device *dev = crtc->dev; | |
474 | const intel_limit_t *limit; | |
475 | ||
bad720ff | 476 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 477 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 478 | else if (IS_G4X(dev)) { |
044c7c41 | 479 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 480 | } else if (IS_PINEVIEW(dev)) { |
2177832f | 481 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 482 | limit = &intel_limits_pineview_lvds; |
2177832f | 483 | else |
f2b115e6 | 484 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
485 | } else if (IS_CHERRYVIEW(dev)) { |
486 | limit = &intel_limits_chv; | |
a0c4da24 | 487 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 488 | limit = &intel_limits_vlv; |
a6c45cf0 CW |
489 | } else if (!IS_GEN2(dev)) { |
490 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
491 | limit = &intel_limits_i9xx_lvds; | |
492 | else | |
493 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 JB |
494 | } else { |
495 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 496 | limit = &intel_limits_i8xx_lvds; |
5d536e28 | 497 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO)) |
e4b36699 | 498 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
499 | else |
500 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
501 | } |
502 | return limit; | |
503 | } | |
504 | ||
f2b115e6 AJ |
505 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
506 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 507 | { |
2177832f SL |
508 | clock->m = clock->m2 + 2; |
509 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
510 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
511 | return; | |
fb03ac01 VS |
512 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
513 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
2177832f SL |
514 | } |
515 | ||
7429e9d4 DV |
516 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
517 | { | |
518 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
519 | } | |
520 | ||
ac58c3f0 | 521 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
2177832f | 522 | { |
7429e9d4 | 523 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 524 | clock->p = clock->p1 * clock->p2; |
ed5ca77e VS |
525 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
526 | return; | |
fb03ac01 VS |
527 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
528 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
79e53945 JB |
529 | } |
530 | ||
ef9348c8 CML |
531 | static void chv_clock(int refclk, intel_clock_t *clock) |
532 | { | |
533 | clock->m = clock->m1 * clock->m2; | |
534 | clock->p = clock->p1 * clock->p2; | |
535 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
536 | return; | |
537 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, | |
538 | clock->n << 22); | |
539 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
540 | } | |
541 | ||
7c04d1d9 | 542 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
543 | /** |
544 | * Returns whether the given set of divisors are valid for a given refclk with | |
545 | * the given connectors. | |
546 | */ | |
547 | ||
1b894b59 CW |
548 | static bool intel_PLL_is_valid(struct drm_device *dev, |
549 | const intel_limit_t *limit, | |
550 | const intel_clock_t *clock) | |
79e53945 | 551 | { |
f01b7962 VS |
552 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
553 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 554 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 555 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 556 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 557 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 558 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 559 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 VS |
560 | |
561 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev)) | |
562 | if (clock->m1 <= clock->m2) | |
563 | INTELPllInvalid("m1 <= m2\n"); | |
564 | ||
565 | if (!IS_VALLEYVIEW(dev)) { | |
566 | if (clock->p < limit->p.min || limit->p.max < clock->p) | |
567 | INTELPllInvalid("p out of range\n"); | |
568 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
569 | INTELPllInvalid("m out of range\n"); | |
570 | } | |
571 | ||
79e53945 | 572 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 573 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
574 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
575 | * connector, etc., rather than just a single range. | |
576 | */ | |
577 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 578 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
579 | |
580 | return true; | |
581 | } | |
582 | ||
d4906093 | 583 | static bool |
ee9300bb | 584 | i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
cec2f356 SP |
585 | int target, int refclk, intel_clock_t *match_clock, |
586 | intel_clock_t *best_clock) | |
79e53945 JB |
587 | { |
588 | struct drm_device *dev = crtc->dev; | |
79e53945 | 589 | intel_clock_t clock; |
79e53945 JB |
590 | int err = target; |
591 | ||
a210b028 | 592 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 593 | /* |
a210b028 DV |
594 | * For LVDS just rely on its current settings for dual-channel. |
595 | * We haven't figured out how to reliably set up different | |
596 | * single/dual channel state, if we even can. | |
79e53945 | 597 | */ |
1974cad0 | 598 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
599 | clock.p2 = limit->p2.p2_fast; |
600 | else | |
601 | clock.p2 = limit->p2.p2_slow; | |
602 | } else { | |
603 | if (target < limit->p2.dot_limit) | |
604 | clock.p2 = limit->p2.p2_slow; | |
605 | else | |
606 | clock.p2 = limit->p2.p2_fast; | |
607 | } | |
608 | ||
0206e353 | 609 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 610 | |
42158660 ZY |
611 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
612 | clock.m1++) { | |
613 | for (clock.m2 = limit->m2.min; | |
614 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 615 | if (clock.m2 >= clock.m1) |
42158660 ZY |
616 | break; |
617 | for (clock.n = limit->n.min; | |
618 | clock.n <= limit->n.max; clock.n++) { | |
619 | for (clock.p1 = limit->p1.min; | |
620 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
621 | int this_err; |
622 | ||
ac58c3f0 DV |
623 | i9xx_clock(refclk, &clock); |
624 | if (!intel_PLL_is_valid(dev, limit, | |
625 | &clock)) | |
626 | continue; | |
627 | if (match_clock && | |
628 | clock.p != match_clock->p) | |
629 | continue; | |
630 | ||
631 | this_err = abs(clock.dot - target); | |
632 | if (this_err < err) { | |
633 | *best_clock = clock; | |
634 | err = this_err; | |
635 | } | |
636 | } | |
637 | } | |
638 | } | |
639 | } | |
640 | ||
641 | return (err != target); | |
642 | } | |
643 | ||
644 | static bool | |
ee9300bb DV |
645 | pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
646 | int target, int refclk, intel_clock_t *match_clock, | |
647 | intel_clock_t *best_clock) | |
79e53945 JB |
648 | { |
649 | struct drm_device *dev = crtc->dev; | |
79e53945 | 650 | intel_clock_t clock; |
79e53945 JB |
651 | int err = target; |
652 | ||
a210b028 | 653 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 654 | /* |
a210b028 DV |
655 | * For LVDS just rely on its current settings for dual-channel. |
656 | * We haven't figured out how to reliably set up different | |
657 | * single/dual channel state, if we even can. | |
79e53945 | 658 | */ |
1974cad0 | 659 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
660 | clock.p2 = limit->p2.p2_fast; |
661 | else | |
662 | clock.p2 = limit->p2.p2_slow; | |
663 | } else { | |
664 | if (target < limit->p2.dot_limit) | |
665 | clock.p2 = limit->p2.p2_slow; | |
666 | else | |
667 | clock.p2 = limit->p2.p2_fast; | |
668 | } | |
669 | ||
0206e353 | 670 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 671 | |
42158660 ZY |
672 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
673 | clock.m1++) { | |
674 | for (clock.m2 = limit->m2.min; | |
675 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
676 | for (clock.n = limit->n.min; |
677 | clock.n <= limit->n.max; clock.n++) { | |
678 | for (clock.p1 = limit->p1.min; | |
679 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
680 | int this_err; |
681 | ||
ac58c3f0 | 682 | pineview_clock(refclk, &clock); |
1b894b59 CW |
683 | if (!intel_PLL_is_valid(dev, limit, |
684 | &clock)) | |
79e53945 | 685 | continue; |
cec2f356 SP |
686 | if (match_clock && |
687 | clock.p != match_clock->p) | |
688 | continue; | |
79e53945 JB |
689 | |
690 | this_err = abs(clock.dot - target); | |
691 | if (this_err < err) { | |
692 | *best_clock = clock; | |
693 | err = this_err; | |
694 | } | |
695 | } | |
696 | } | |
697 | } | |
698 | } | |
699 | ||
700 | return (err != target); | |
701 | } | |
702 | ||
d4906093 | 703 | static bool |
ee9300bb DV |
704 | g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
705 | int target, int refclk, intel_clock_t *match_clock, | |
706 | intel_clock_t *best_clock) | |
d4906093 ML |
707 | { |
708 | struct drm_device *dev = crtc->dev; | |
d4906093 ML |
709 | intel_clock_t clock; |
710 | int max_n; | |
711 | bool found; | |
6ba770dc AJ |
712 | /* approximately equals target * 0.00585 */ |
713 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
714 | found = false; |
715 | ||
716 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 717 | if (intel_is_dual_link_lvds(dev)) |
d4906093 ML |
718 | clock.p2 = limit->p2.p2_fast; |
719 | else | |
720 | clock.p2 = limit->p2.p2_slow; | |
721 | } else { | |
722 | if (target < limit->p2.dot_limit) | |
723 | clock.p2 = limit->p2.p2_slow; | |
724 | else | |
725 | clock.p2 = limit->p2.p2_fast; | |
726 | } | |
727 | ||
728 | memset(best_clock, 0, sizeof(*best_clock)); | |
729 | max_n = limit->n.max; | |
f77f13e2 | 730 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 731 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 732 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
733 | for (clock.m1 = limit->m1.max; |
734 | clock.m1 >= limit->m1.min; clock.m1--) { | |
735 | for (clock.m2 = limit->m2.max; | |
736 | clock.m2 >= limit->m2.min; clock.m2--) { | |
737 | for (clock.p1 = limit->p1.max; | |
738 | clock.p1 >= limit->p1.min; clock.p1--) { | |
739 | int this_err; | |
740 | ||
ac58c3f0 | 741 | i9xx_clock(refclk, &clock); |
1b894b59 CW |
742 | if (!intel_PLL_is_valid(dev, limit, |
743 | &clock)) | |
d4906093 | 744 | continue; |
1b894b59 CW |
745 | |
746 | this_err = abs(clock.dot - target); | |
d4906093 ML |
747 | if (this_err < err_most) { |
748 | *best_clock = clock; | |
749 | err_most = this_err; | |
750 | max_n = clock.n; | |
751 | found = true; | |
752 | } | |
753 | } | |
754 | } | |
755 | } | |
756 | } | |
2c07245f ZW |
757 | return found; |
758 | } | |
759 | ||
a0c4da24 | 760 | static bool |
ee9300bb DV |
761 | vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
762 | int target, int refclk, intel_clock_t *match_clock, | |
763 | intel_clock_t *best_clock) | |
a0c4da24 | 764 | { |
f01b7962 | 765 | struct drm_device *dev = crtc->dev; |
6b4bf1c4 | 766 | intel_clock_t clock; |
69e4f900 | 767 | unsigned int bestppm = 1000000; |
27e639bf VS |
768 | /* min update 19.2 MHz */ |
769 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 770 | bool found = false; |
a0c4da24 | 771 | |
6b4bf1c4 VS |
772 | target *= 5; /* fast clock */ |
773 | ||
774 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
775 | |
776 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 777 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 778 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 779 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 780 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 781 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 782 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 783 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
69e4f900 VS |
784 | unsigned int ppm, diff; |
785 | ||
6b4bf1c4 VS |
786 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
787 | refclk * clock.m1); | |
788 | ||
789 | vlv_clock(refclk, &clock); | |
43b0ac53 | 790 | |
f01b7962 VS |
791 | if (!intel_PLL_is_valid(dev, limit, |
792 | &clock)) | |
43b0ac53 VS |
793 | continue; |
794 | ||
6b4bf1c4 VS |
795 | diff = abs(clock.dot - target); |
796 | ppm = div_u64(1000000ULL * diff, target); | |
797 | ||
798 | if (ppm < 100 && clock.p > best_clock->p) { | |
43b0ac53 | 799 | bestppm = 0; |
6b4bf1c4 | 800 | *best_clock = clock; |
49e497ef | 801 | found = true; |
43b0ac53 | 802 | } |
6b4bf1c4 | 803 | |
c686122c | 804 | if (bestppm >= 10 && ppm < bestppm - 10) { |
69e4f900 | 805 | bestppm = ppm; |
6b4bf1c4 | 806 | *best_clock = clock; |
49e497ef | 807 | found = true; |
a0c4da24 JB |
808 | } |
809 | } | |
810 | } | |
811 | } | |
812 | } | |
a0c4da24 | 813 | |
49e497ef | 814 | return found; |
a0c4da24 | 815 | } |
a4fc5ed6 | 816 | |
ef9348c8 CML |
817 | static bool |
818 | chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, | |
819 | int target, int refclk, intel_clock_t *match_clock, | |
820 | intel_clock_t *best_clock) | |
821 | { | |
822 | struct drm_device *dev = crtc->dev; | |
823 | intel_clock_t clock; | |
824 | uint64_t m2; | |
825 | int found = false; | |
826 | ||
827 | memset(best_clock, 0, sizeof(*best_clock)); | |
828 | ||
829 | /* | |
830 | * Based on hardware doc, the n always set to 1, and m1 always | |
831 | * set to 2. If requires to support 200Mhz refclk, we need to | |
832 | * revisit this because n may not 1 anymore. | |
833 | */ | |
834 | clock.n = 1, clock.m1 = 2; | |
835 | target *= 5; /* fast clock */ | |
836 | ||
837 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
838 | for (clock.p2 = limit->p2.p2_fast; | |
839 | clock.p2 >= limit->p2.p2_slow; | |
840 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
841 | ||
842 | clock.p = clock.p1 * clock.p2; | |
843 | ||
844 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
845 | clock.n) << 22, refclk * clock.m1); | |
846 | ||
847 | if (m2 > INT_MAX/clock.m1) | |
848 | continue; | |
849 | ||
850 | clock.m2 = m2; | |
851 | ||
852 | chv_clock(refclk, &clock); | |
853 | ||
854 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
855 | continue; | |
856 | ||
857 | /* based on hardware requirement, prefer bigger p | |
858 | */ | |
859 | if (clock.p > best_clock->p) { | |
860 | *best_clock = clock; | |
861 | found = true; | |
862 | } | |
863 | } | |
864 | } | |
865 | ||
866 | return found; | |
867 | } | |
868 | ||
20ddf665 VS |
869 | bool intel_crtc_active(struct drm_crtc *crtc) |
870 | { | |
871 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
872 | ||
873 | /* Be paranoid as we can arrive here with only partial | |
874 | * state retrieved from the hardware during setup. | |
875 | * | |
241bfc38 | 876 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
877 | * as Haswell has gained clock readout/fastboot support. |
878 | * | |
66e514c1 | 879 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 VS |
880 | * properly reconstruct framebuffers. |
881 | */ | |
f4510a27 | 882 | return intel_crtc->active && crtc->primary->fb && |
241bfc38 | 883 | intel_crtc->config.adjusted_mode.crtc_clock; |
20ddf665 VS |
884 | } |
885 | ||
a5c961d1 PZ |
886 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
887 | enum pipe pipe) | |
888 | { | |
889 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
890 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
891 | ||
3b117c8f | 892 | return intel_crtc->config.cpu_transcoder; |
a5c961d1 PZ |
893 | } |
894 | ||
57e22f4a | 895 | static void g4x_wait_for_vblank(struct drm_device *dev, int pipe) |
a928d536 PZ |
896 | { |
897 | struct drm_i915_private *dev_priv = dev->dev_private; | |
57e22f4a | 898 | u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe); |
a928d536 PZ |
899 | |
900 | frame = I915_READ(frame_reg); | |
901 | ||
902 | if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) | |
31e4b89a DL |
903 | WARN(1, "vblank wait on pipe %c timed out\n", |
904 | pipe_name(pipe)); | |
a928d536 PZ |
905 | } |
906 | ||
9d0498a2 JB |
907 | /** |
908 | * intel_wait_for_vblank - wait for vblank on a given pipe | |
909 | * @dev: drm device | |
910 | * @pipe: pipe to wait for | |
911 | * | |
912 | * Wait for vblank to occur on a given pipe. Needed for various bits of | |
913 | * mode setting code. | |
914 | */ | |
915 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
79e53945 | 916 | { |
9d0498a2 | 917 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 918 | int pipestat_reg = PIPESTAT(pipe); |
9d0498a2 | 919 | |
57e22f4a VS |
920 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
921 | g4x_wait_for_vblank(dev, pipe); | |
a928d536 PZ |
922 | return; |
923 | } | |
924 | ||
300387c0 CW |
925 | /* Clear existing vblank status. Note this will clear any other |
926 | * sticky status fields as well. | |
927 | * | |
928 | * This races with i915_driver_irq_handler() with the result | |
929 | * that either function could miss a vblank event. Here it is not | |
930 | * fatal, as we will either wait upon the next vblank interrupt or | |
931 | * timeout. Generally speaking intel_wait_for_vblank() is only | |
932 | * called during modeset at which time the GPU should be idle and | |
933 | * should *not* be performing page flips and thus not waiting on | |
934 | * vblanks... | |
935 | * Currently, the result of us stealing a vblank from the irq | |
936 | * handler is that a single frame will be skipped during swapbuffers. | |
937 | */ | |
938 | I915_WRITE(pipestat_reg, | |
939 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); | |
940 | ||
9d0498a2 | 941 | /* Wait for vblank interrupt bit to set */ |
481b6af3 CW |
942 | if (wait_for(I915_READ(pipestat_reg) & |
943 | PIPE_VBLANK_INTERRUPT_STATUS, | |
944 | 50)) | |
31e4b89a DL |
945 | DRM_DEBUG_KMS("vblank wait on pipe %c timed out\n", |
946 | pipe_name(pipe)); | |
9d0498a2 JB |
947 | } |
948 | ||
fbf49ea2 VS |
949 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
950 | { | |
951 | struct drm_i915_private *dev_priv = dev->dev_private; | |
952 | u32 reg = PIPEDSL(pipe); | |
953 | u32 line1, line2; | |
954 | u32 line_mask; | |
955 | ||
956 | if (IS_GEN2(dev)) | |
957 | line_mask = DSL_LINEMASK_GEN2; | |
958 | else | |
959 | line_mask = DSL_LINEMASK_GEN3; | |
960 | ||
961 | line1 = I915_READ(reg) & line_mask; | |
962 | mdelay(5); | |
963 | line2 = I915_READ(reg) & line_mask; | |
964 | ||
965 | return line1 == line2; | |
966 | } | |
967 | ||
ab7ad7f6 KP |
968 | /* |
969 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 970 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
971 | * |
972 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
973 | * spinning on the vblank interrupt status bit, since we won't actually | |
974 | * see an interrupt when the pipe is disabled. | |
975 | * | |
ab7ad7f6 KP |
976 | * On Gen4 and above: |
977 | * wait for the pipe register state bit to turn off | |
978 | * | |
979 | * Otherwise: | |
980 | * wait for the display line value to settle (it usually | |
981 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 982 | * |
9d0498a2 | 983 | */ |
575f7ab7 | 984 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 985 | { |
575f7ab7 | 986 | struct drm_device *dev = crtc->base.dev; |
9d0498a2 | 987 | struct drm_i915_private *dev_priv = dev->dev_private; |
575f7ab7 VS |
988 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; |
989 | enum pipe pipe = crtc->pipe; | |
ab7ad7f6 KP |
990 | |
991 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 992 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
993 | |
994 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
995 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
996 | 100)) | |
284637d9 | 997 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 998 | } else { |
ab7ad7f6 | 999 | /* Wait for the display line to settle */ |
fbf49ea2 | 1000 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1001 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1002 | } |
79e53945 JB |
1003 | } |
1004 | ||
b0ea7d37 DL |
1005 | /* |
1006 | * ibx_digital_port_connected - is the specified port connected? | |
1007 | * @dev_priv: i915 private structure | |
1008 | * @port: the port to test | |
1009 | * | |
1010 | * Returns true if @port is connected, false otherwise. | |
1011 | */ | |
1012 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, | |
1013 | struct intel_digital_port *port) | |
1014 | { | |
1015 | u32 bit; | |
1016 | ||
c36346e3 | 1017 | if (HAS_PCH_IBX(dev_priv->dev)) { |
eba905b2 | 1018 | switch (port->port) { |
c36346e3 DL |
1019 | case PORT_B: |
1020 | bit = SDE_PORTB_HOTPLUG; | |
1021 | break; | |
1022 | case PORT_C: | |
1023 | bit = SDE_PORTC_HOTPLUG; | |
1024 | break; | |
1025 | case PORT_D: | |
1026 | bit = SDE_PORTD_HOTPLUG; | |
1027 | break; | |
1028 | default: | |
1029 | return true; | |
1030 | } | |
1031 | } else { | |
eba905b2 | 1032 | switch (port->port) { |
c36346e3 DL |
1033 | case PORT_B: |
1034 | bit = SDE_PORTB_HOTPLUG_CPT; | |
1035 | break; | |
1036 | case PORT_C: | |
1037 | bit = SDE_PORTC_HOTPLUG_CPT; | |
1038 | break; | |
1039 | case PORT_D: | |
1040 | bit = SDE_PORTD_HOTPLUG_CPT; | |
1041 | break; | |
1042 | default: | |
1043 | return true; | |
1044 | } | |
b0ea7d37 DL |
1045 | } |
1046 | ||
1047 | return I915_READ(SDEISR) & bit; | |
1048 | } | |
1049 | ||
b24e7179 JB |
1050 | static const char *state_string(bool enabled) |
1051 | { | |
1052 | return enabled ? "on" : "off"; | |
1053 | } | |
1054 | ||
1055 | /* Only for pre-ILK configs */ | |
55607e8a DV |
1056 | void assert_pll(struct drm_i915_private *dev_priv, |
1057 | enum pipe pipe, bool state) | |
b24e7179 JB |
1058 | { |
1059 | int reg; | |
1060 | u32 val; | |
1061 | bool cur_state; | |
1062 | ||
1063 | reg = DPLL(pipe); | |
1064 | val = I915_READ(reg); | |
1065 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
1066 | WARN(cur_state != state, | |
1067 | "PLL state assertion failure (expected %s, current %s)\n", | |
1068 | state_string(state), state_string(cur_state)); | |
1069 | } | |
b24e7179 | 1070 | |
23538ef1 JN |
1071 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1072 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1073 | { | |
1074 | u32 val; | |
1075 | bool cur_state; | |
1076 | ||
1077 | mutex_lock(&dev_priv->dpio_lock); | |
1078 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
1079 | mutex_unlock(&dev_priv->dpio_lock); | |
1080 | ||
1081 | cur_state = val & DSI_PLL_VCO_EN; | |
1082 | WARN(cur_state != state, | |
1083 | "DSI PLL state assertion failure (expected %s, current %s)\n", | |
1084 | state_string(state), state_string(cur_state)); | |
1085 | } | |
1086 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1087 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1088 | ||
55607e8a | 1089 | struct intel_shared_dpll * |
e2b78267 DV |
1090 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1091 | { | |
1092 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1093 | ||
a43f6e0f | 1094 | if (crtc->config.shared_dpll < 0) |
e2b78267 DV |
1095 | return NULL; |
1096 | ||
a43f6e0f | 1097 | return &dev_priv->shared_dplls[crtc->config.shared_dpll]; |
e2b78267 DV |
1098 | } |
1099 | ||
040484af | 1100 | /* For ILK+ */ |
55607e8a DV |
1101 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1102 | struct intel_shared_dpll *pll, | |
1103 | bool state) | |
040484af | 1104 | { |
040484af | 1105 | bool cur_state; |
5358901f | 1106 | struct intel_dpll_hw_state hw_state; |
040484af | 1107 | |
92b27b08 | 1108 | if (WARN (!pll, |
46edb027 | 1109 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 1110 | return; |
ee7b9f93 | 1111 | |
5358901f | 1112 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
92b27b08 | 1113 | WARN(cur_state != state, |
5358901f DV |
1114 | "%s assertion failure (expected %s, current %s)\n", |
1115 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 1116 | } |
040484af JB |
1117 | |
1118 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1119 | enum pipe pipe, bool state) | |
1120 | { | |
1121 | int reg; | |
1122 | u32 val; | |
1123 | bool cur_state; | |
ad80a810 PZ |
1124 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1125 | pipe); | |
040484af | 1126 | |
affa9354 PZ |
1127 | if (HAS_DDI(dev_priv->dev)) { |
1128 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 1129 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 1130 | val = I915_READ(reg); |
ad80a810 | 1131 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
1132 | } else { |
1133 | reg = FDI_TX_CTL(pipe); | |
1134 | val = I915_READ(reg); | |
1135 | cur_state = !!(val & FDI_TX_ENABLE); | |
1136 | } | |
040484af JB |
1137 | WARN(cur_state != state, |
1138 | "FDI TX state assertion failure (expected %s, current %s)\n", | |
1139 | state_string(state), state_string(cur_state)); | |
1140 | } | |
1141 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1142 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1143 | ||
1144 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1145 | enum pipe pipe, bool state) | |
1146 | { | |
1147 | int reg; | |
1148 | u32 val; | |
1149 | bool cur_state; | |
1150 | ||
d63fa0dc PZ |
1151 | reg = FDI_RX_CTL(pipe); |
1152 | val = I915_READ(reg); | |
1153 | cur_state = !!(val & FDI_RX_ENABLE); | |
040484af JB |
1154 | WARN(cur_state != state, |
1155 | "FDI RX state assertion failure (expected %s, current %s)\n", | |
1156 | state_string(state), state_string(cur_state)); | |
1157 | } | |
1158 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1159 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1160 | ||
1161 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1162 | enum pipe pipe) | |
1163 | { | |
1164 | int reg; | |
1165 | u32 val; | |
1166 | ||
1167 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1168 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1169 | return; |
1170 | ||
bf507ef7 | 1171 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1172 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1173 | return; |
1174 | ||
040484af JB |
1175 | reg = FDI_TX_CTL(pipe); |
1176 | val = I915_READ(reg); | |
1177 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); | |
1178 | } | |
1179 | ||
55607e8a DV |
1180 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1181 | enum pipe pipe, bool state) | |
040484af JB |
1182 | { |
1183 | int reg; | |
1184 | u32 val; | |
55607e8a | 1185 | bool cur_state; |
040484af JB |
1186 | |
1187 | reg = FDI_RX_CTL(pipe); | |
1188 | val = I915_READ(reg); | |
55607e8a DV |
1189 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
1190 | WARN(cur_state != state, | |
1191 | "FDI RX PLL assertion failure (expected %s, current %s)\n", | |
1192 | state_string(state), state_string(cur_state)); | |
040484af JB |
1193 | } |
1194 | ||
ea0760cf JB |
1195 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1196 | enum pipe pipe) | |
1197 | { | |
bedd4dba JN |
1198 | struct drm_device *dev = dev_priv->dev; |
1199 | int pp_reg; | |
ea0760cf JB |
1200 | u32 val; |
1201 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1202 | bool locked = true; |
ea0760cf | 1203 | |
bedd4dba JN |
1204 | if (WARN_ON(HAS_DDI(dev))) |
1205 | return; | |
1206 | ||
1207 | if (HAS_PCH_SPLIT(dev)) { | |
1208 | u32 port_sel; | |
1209 | ||
ea0760cf | 1210 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1211 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1212 | ||
1213 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1214 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1215 | panel_pipe = PIPE_B; | |
1216 | /* XXX: else fix for eDP */ | |
1217 | } else if (IS_VALLEYVIEW(dev)) { | |
1218 | /* presumably write lock depends on pipe, not port select */ | |
1219 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1220 | panel_pipe = pipe; | |
ea0760cf JB |
1221 | } else { |
1222 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1223 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1224 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1225 | } |
1226 | ||
1227 | val = I915_READ(pp_reg); | |
1228 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1229 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1230 | locked = false; |
1231 | ||
ea0760cf JB |
1232 | WARN(panel_pipe == pipe && locked, |
1233 | "panel assertion failure, pipe %c regs locked\n", | |
9db4a9c7 | 1234 | pipe_name(pipe)); |
ea0760cf JB |
1235 | } |
1236 | ||
93ce0ba6 JN |
1237 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1238 | enum pipe pipe, bool state) | |
1239 | { | |
1240 | struct drm_device *dev = dev_priv->dev; | |
1241 | bool cur_state; | |
1242 | ||
d9d82081 | 1243 | if (IS_845G(dev) || IS_I865G(dev)) |
93ce0ba6 | 1244 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; |
d9d82081 | 1245 | else |
5efb3e28 | 1246 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 JN |
1247 | |
1248 | WARN(cur_state != state, | |
1249 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", | |
1250 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1251 | } | |
1252 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1253 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1254 | ||
b840d907 JB |
1255 | void assert_pipe(struct drm_i915_private *dev_priv, |
1256 | enum pipe pipe, bool state) | |
b24e7179 JB |
1257 | { |
1258 | int reg; | |
1259 | u32 val; | |
63d7bbe9 | 1260 | bool cur_state; |
702e7a56 PZ |
1261 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1262 | pipe); | |
b24e7179 | 1263 | |
8e636784 DV |
1264 | /* if we need the pipe A quirk it must be always on */ |
1265 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
1266 | state = true; | |
1267 | ||
da7e29bd | 1268 | if (!intel_display_power_enabled(dev_priv, |
b97186f0 | 1269 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
69310161 PZ |
1270 | cur_state = false; |
1271 | } else { | |
1272 | reg = PIPECONF(cpu_transcoder); | |
1273 | val = I915_READ(reg); | |
1274 | cur_state = !!(val & PIPECONF_ENABLE); | |
1275 | } | |
1276 | ||
63d7bbe9 JB |
1277 | WARN(cur_state != state, |
1278 | "pipe %c assertion failure (expected %s, current %s)\n", | |
9db4a9c7 | 1279 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1280 | } |
1281 | ||
931872fc CW |
1282 | static void assert_plane(struct drm_i915_private *dev_priv, |
1283 | enum plane plane, bool state) | |
b24e7179 JB |
1284 | { |
1285 | int reg; | |
1286 | u32 val; | |
931872fc | 1287 | bool cur_state; |
b24e7179 JB |
1288 | |
1289 | reg = DSPCNTR(plane); | |
1290 | val = I915_READ(reg); | |
931872fc CW |
1291 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1292 | WARN(cur_state != state, | |
1293 | "plane %c assertion failure (expected %s, current %s)\n", | |
1294 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1295 | } |
1296 | ||
931872fc CW |
1297 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1298 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1299 | ||
b24e7179 JB |
1300 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1301 | enum pipe pipe) | |
1302 | { | |
653e1026 | 1303 | struct drm_device *dev = dev_priv->dev; |
b24e7179 JB |
1304 | int reg, i; |
1305 | u32 val; | |
1306 | int cur_pipe; | |
1307 | ||
653e1026 VS |
1308 | /* Primary planes are fixed to pipes on gen4+ */ |
1309 | if (INTEL_INFO(dev)->gen >= 4) { | |
28c05794 AJ |
1310 | reg = DSPCNTR(pipe); |
1311 | val = I915_READ(reg); | |
83f26f16 | 1312 | WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1313 | "plane %c assertion failure, should be disabled but not\n", |
1314 | plane_name(pipe)); | |
19ec1358 | 1315 | return; |
28c05794 | 1316 | } |
19ec1358 | 1317 | |
b24e7179 | 1318 | /* Need to check both planes against the pipe */ |
055e393f | 1319 | for_each_pipe(dev_priv, i) { |
b24e7179 JB |
1320 | reg = DSPCNTR(i); |
1321 | val = I915_READ(reg); | |
1322 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1323 | DISPPLANE_SEL_PIPE_SHIFT; | |
1324 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, | |
9db4a9c7 JB |
1325 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1326 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1327 | } |
1328 | } | |
1329 | ||
19332d7a JB |
1330 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1331 | enum pipe pipe) | |
1332 | { | |
20674eef | 1333 | struct drm_device *dev = dev_priv->dev; |
1fe47785 | 1334 | int reg, sprite; |
19332d7a JB |
1335 | u32 val; |
1336 | ||
20674eef | 1337 | if (IS_VALLEYVIEW(dev)) { |
1fe47785 DL |
1338 | for_each_sprite(pipe, sprite) { |
1339 | reg = SPCNTR(pipe, sprite); | |
20674eef | 1340 | val = I915_READ(reg); |
83f26f16 | 1341 | WARN(val & SP_ENABLE, |
20674eef | 1342 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1343 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1344 | } |
1345 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
1346 | reg = SPRCTL(pipe); | |
19332d7a | 1347 | val = I915_READ(reg); |
83f26f16 | 1348 | WARN(val & SPRITE_ENABLE, |
06da8da2 | 1349 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1350 | plane_name(pipe), pipe_name(pipe)); |
1351 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1352 | reg = DVSCNTR(pipe); | |
19332d7a | 1353 | val = I915_READ(reg); |
83f26f16 | 1354 | WARN(val & DVS_ENABLE, |
06da8da2 | 1355 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1356 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1357 | } |
1358 | } | |
1359 | ||
89eff4be | 1360 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1361 | { |
1362 | u32 val; | |
1363 | bool enabled; | |
1364 | ||
89eff4be | 1365 | WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1366 | |
92f2584a JB |
1367 | val = I915_READ(PCH_DREF_CONTROL); |
1368 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1369 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
1370 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); | |
1371 | } | |
1372 | ||
ab9412ba DV |
1373 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1374 | enum pipe pipe) | |
92f2584a JB |
1375 | { |
1376 | int reg; | |
1377 | u32 val; | |
1378 | bool enabled; | |
1379 | ||
ab9412ba | 1380 | reg = PCH_TRANSCONF(pipe); |
92f2584a JB |
1381 | val = I915_READ(reg); |
1382 | enabled = !!(val & TRANS_ENABLE); | |
9db4a9c7 JB |
1383 | WARN(enabled, |
1384 | "transcoder assertion failed, should be off on pipe %c but is still active\n", | |
1385 | pipe_name(pipe)); | |
92f2584a JB |
1386 | } |
1387 | ||
4e634389 KP |
1388 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1389 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1390 | { |
1391 | if ((val & DP_PORT_EN) == 0) | |
1392 | return false; | |
1393 | ||
1394 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1395 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1396 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1397 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1398 | return false; | |
44f37d1f CML |
1399 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1400 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1401 | return false; | |
f0575e92 KP |
1402 | } else { |
1403 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1404 | return false; | |
1405 | } | |
1406 | return true; | |
1407 | } | |
1408 | ||
1519b995 KP |
1409 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1410 | enum pipe pipe, u32 val) | |
1411 | { | |
dc0fa718 | 1412 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1413 | return false; |
1414 | ||
1415 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1416 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1417 | return false; |
44f37d1f CML |
1418 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1419 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1420 | return false; | |
1519b995 | 1421 | } else { |
dc0fa718 | 1422 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1423 | return false; |
1424 | } | |
1425 | return true; | |
1426 | } | |
1427 | ||
1428 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1429 | enum pipe pipe, u32 val) | |
1430 | { | |
1431 | if ((val & LVDS_PORT_EN) == 0) | |
1432 | return false; | |
1433 | ||
1434 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1435 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1436 | return false; | |
1437 | } else { | |
1438 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1439 | return false; | |
1440 | } | |
1441 | return true; | |
1442 | } | |
1443 | ||
1444 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1445 | enum pipe pipe, u32 val) | |
1446 | { | |
1447 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1448 | return false; | |
1449 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1450 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1451 | return false; | |
1452 | } else { | |
1453 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1454 | return false; | |
1455 | } | |
1456 | return true; | |
1457 | } | |
1458 | ||
291906f1 | 1459 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1460 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1461 | { |
47a05eca | 1462 | u32 val = I915_READ(reg); |
4e634389 | 1463 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1464 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1465 | reg, pipe_name(pipe)); |
de9a35ab | 1466 | |
75c5da27 DV |
1467 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
1468 | && (val & DP_PIPEB_SELECT), | |
de9a35ab | 1469 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1470 | } |
1471 | ||
1472 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1473 | enum pipe pipe, int reg) | |
1474 | { | |
47a05eca | 1475 | u32 val = I915_READ(reg); |
b70ad586 | 1476 | WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1477 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1478 | reg, pipe_name(pipe)); |
de9a35ab | 1479 | |
dc0fa718 | 1480 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1481 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1482 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1483 | } |
1484 | ||
1485 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1486 | enum pipe pipe) | |
1487 | { | |
1488 | int reg; | |
1489 | u32 val; | |
291906f1 | 1490 | |
f0575e92 KP |
1491 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1492 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1493 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1494 | |
1495 | reg = PCH_ADPA; | |
1496 | val = I915_READ(reg); | |
b70ad586 | 1497 | WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1498 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1499 | pipe_name(pipe)); |
291906f1 JB |
1500 | |
1501 | reg = PCH_LVDS; | |
1502 | val = I915_READ(reg); | |
b70ad586 | 1503 | WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1504 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1505 | pipe_name(pipe)); |
291906f1 | 1506 | |
e2debe91 PZ |
1507 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1508 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1509 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1510 | } |
1511 | ||
40e9cf64 JB |
1512 | static void intel_init_dpio(struct drm_device *dev) |
1513 | { | |
1514 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1515 | ||
1516 | if (!IS_VALLEYVIEW(dev)) | |
1517 | return; | |
1518 | ||
a09caddd CML |
1519 | /* |
1520 | * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), | |
1521 | * CHV x1 PHY (DP/HDMI D) | |
1522 | * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) | |
1523 | */ | |
1524 | if (IS_CHERRYVIEW(dev)) { | |
1525 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; | |
1526 | DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO; | |
1527 | } else { | |
1528 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; | |
1529 | } | |
5382f5f3 JB |
1530 | } |
1531 | ||
426115cf | 1532 | static void vlv_enable_pll(struct intel_crtc *crtc) |
87442f73 | 1533 | { |
426115cf DV |
1534 | struct drm_device *dev = crtc->base.dev; |
1535 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1536 | int reg = DPLL(crtc->pipe); | |
1537 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
87442f73 | 1538 | |
426115cf | 1539 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 DV |
1540 | |
1541 | /* No really, not for ILK+ */ | |
1542 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
1543 | ||
1544 | /* PLL is protected by panel, make sure we can write it */ | |
6a9e7363 | 1545 | if (IS_MOBILE(dev_priv->dev)) |
426115cf | 1546 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1547 | |
426115cf DV |
1548 | I915_WRITE(reg, dpll); |
1549 | POSTING_READ(reg); | |
1550 | udelay(150); | |
1551 | ||
1552 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1553 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1554 | ||
1555 | I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md); | |
1556 | POSTING_READ(DPLL_MD(crtc->pipe)); | |
87442f73 DV |
1557 | |
1558 | /* We do this three times for luck */ | |
426115cf | 1559 | I915_WRITE(reg, dpll); |
87442f73 DV |
1560 | POSTING_READ(reg); |
1561 | udelay(150); /* wait for warmup */ | |
426115cf | 1562 | I915_WRITE(reg, dpll); |
87442f73 DV |
1563 | POSTING_READ(reg); |
1564 | udelay(150); /* wait for warmup */ | |
426115cf | 1565 | I915_WRITE(reg, dpll); |
87442f73 DV |
1566 | POSTING_READ(reg); |
1567 | udelay(150); /* wait for warmup */ | |
1568 | } | |
1569 | ||
9d556c99 CML |
1570 | static void chv_enable_pll(struct intel_crtc *crtc) |
1571 | { | |
1572 | struct drm_device *dev = crtc->base.dev; | |
1573 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1574 | int pipe = crtc->pipe; | |
1575 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1576 | u32 tmp; |
1577 | ||
1578 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1579 | ||
1580 | BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); | |
1581 | ||
1582 | mutex_lock(&dev_priv->dpio_lock); | |
1583 | ||
1584 | /* Enable back the 10bit clock to display controller */ | |
1585 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1586 | tmp |= DPIO_DCLKP_EN; | |
1587 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1588 | ||
1589 | /* | |
1590 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1591 | */ | |
1592 | udelay(1); | |
1593 | ||
1594 | /* Enable PLL */ | |
a11b0703 | 1595 | I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll); |
9d556c99 CML |
1596 | |
1597 | /* Check PLL is locked */ | |
a11b0703 | 1598 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1599 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1600 | ||
a11b0703 VS |
1601 | /* not sure when this should be written */ |
1602 | I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md); | |
1603 | POSTING_READ(DPLL_MD(pipe)); | |
1604 | ||
9d556c99 CML |
1605 | mutex_unlock(&dev_priv->dpio_lock); |
1606 | } | |
1607 | ||
66e3d5c0 | 1608 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1609 | { |
66e3d5c0 DV |
1610 | struct drm_device *dev = crtc->base.dev; |
1611 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1612 | int reg = DPLL(crtc->pipe); | |
1613 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
63d7bbe9 | 1614 | |
66e3d5c0 | 1615 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1616 | |
63d7bbe9 | 1617 | /* No really, not for ILK+ */ |
3d13ef2e | 1618 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1619 | |
1620 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1621 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1622 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1623 | |
66e3d5c0 DV |
1624 | I915_WRITE(reg, dpll); |
1625 | ||
1626 | /* Wait for the clocks to stabilize. */ | |
1627 | POSTING_READ(reg); | |
1628 | udelay(150); | |
1629 | ||
1630 | if (INTEL_INFO(dev)->gen >= 4) { | |
1631 | I915_WRITE(DPLL_MD(crtc->pipe), | |
1632 | crtc->config.dpll_hw_state.dpll_md); | |
1633 | } else { | |
1634 | /* The pixel multiplier can only be updated once the | |
1635 | * DPLL is enabled and the clocks are stable. | |
1636 | * | |
1637 | * So write it again. | |
1638 | */ | |
1639 | I915_WRITE(reg, dpll); | |
1640 | } | |
63d7bbe9 JB |
1641 | |
1642 | /* We do this three times for luck */ | |
66e3d5c0 | 1643 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1644 | POSTING_READ(reg); |
1645 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1646 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1647 | POSTING_READ(reg); |
1648 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1649 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1650 | POSTING_READ(reg); |
1651 | udelay(150); /* wait for warmup */ | |
1652 | } | |
1653 | ||
1654 | /** | |
50b44a44 | 1655 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1656 | * @dev_priv: i915 private structure |
1657 | * @pipe: pipe PLL to disable | |
1658 | * | |
1659 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1660 | * | |
1661 | * Note! This is for pre-ILK only. | |
1662 | */ | |
50b44a44 | 1663 | static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
63d7bbe9 | 1664 | { |
63d7bbe9 JB |
1665 | /* Don't disable pipe A or pipe A PLLs if needed */ |
1666 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1667 | return; | |
1668 | ||
1669 | /* Make sure the pipe isn't still relying on us */ | |
1670 | assert_pipe_disabled(dev_priv, pipe); | |
1671 | ||
50b44a44 DV |
1672 | I915_WRITE(DPLL(pipe), 0); |
1673 | POSTING_READ(DPLL(pipe)); | |
63d7bbe9 JB |
1674 | } |
1675 | ||
f6071166 JB |
1676 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1677 | { | |
1678 | u32 val = 0; | |
1679 | ||
1680 | /* Make sure the pipe isn't still relying on us */ | |
1681 | assert_pipe_disabled(dev_priv, pipe); | |
1682 | ||
e5cbfbfb ID |
1683 | /* |
1684 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1685 | * The latter is needed for VGA hotplug / manual detection. | |
1686 | */ | |
f6071166 | 1687 | if (pipe == PIPE_B) |
e5cbfbfb | 1688 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; |
f6071166 JB |
1689 | I915_WRITE(DPLL(pipe), val); |
1690 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1691 | |
1692 | } | |
1693 | ||
1694 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1695 | { | |
d752048d | 1696 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1697 | u32 val; |
1698 | ||
a11b0703 VS |
1699 | /* Make sure the pipe isn't still relying on us */ |
1700 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1701 | |
a11b0703 | 1702 | /* Set PLL en = 0 */ |
d17ec4ce | 1703 | val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV; |
a11b0703 VS |
1704 | if (pipe != PIPE_A) |
1705 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1706 | I915_WRITE(DPLL(pipe), val); | |
1707 | POSTING_READ(DPLL(pipe)); | |
d752048d VS |
1708 | |
1709 | mutex_lock(&dev_priv->dpio_lock); | |
1710 | ||
1711 | /* Disable 10bit clock to display controller */ | |
1712 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1713 | val &= ~DPIO_DCLKP_EN; | |
1714 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1715 | ||
61407f6d VS |
1716 | /* disable left/right clock distribution */ |
1717 | if (pipe != PIPE_B) { | |
1718 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
1719 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
1720 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
1721 | } else { | |
1722 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
1723 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
1724 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
1725 | } | |
1726 | ||
d752048d | 1727 | mutex_unlock(&dev_priv->dpio_lock); |
f6071166 JB |
1728 | } |
1729 | ||
e4607fcf CML |
1730 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
1731 | struct intel_digital_port *dport) | |
89b667f8 JB |
1732 | { |
1733 | u32 port_mask; | |
00fc31b7 | 1734 | int dpll_reg; |
89b667f8 | 1735 | |
e4607fcf CML |
1736 | switch (dport->port) { |
1737 | case PORT_B: | |
89b667f8 | 1738 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1739 | dpll_reg = DPLL(0); |
e4607fcf CML |
1740 | break; |
1741 | case PORT_C: | |
89b667f8 | 1742 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 CML |
1743 | dpll_reg = DPLL(0); |
1744 | break; | |
1745 | case PORT_D: | |
1746 | port_mask = DPLL_PORTD_READY_MASK; | |
1747 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1748 | break; |
1749 | default: | |
1750 | BUG(); | |
1751 | } | |
89b667f8 | 1752 | |
00fc31b7 | 1753 | if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000)) |
89b667f8 | 1754 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", |
00fc31b7 | 1755 | port_name(dport->port), I915_READ(dpll_reg)); |
89b667f8 JB |
1756 | } |
1757 | ||
b14b1055 DV |
1758 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1759 | { | |
1760 | struct drm_device *dev = crtc->base.dev; | |
1761 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1762 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
1763 | ||
be19f0ff CW |
1764 | if (WARN_ON(pll == NULL)) |
1765 | return; | |
1766 | ||
b14b1055 DV |
1767 | WARN_ON(!pll->refcount); |
1768 | if (pll->active == 0) { | |
1769 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
1770 | WARN_ON(pll->on); | |
1771 | assert_shared_dpll_disabled(dev_priv, pll); | |
1772 | ||
1773 | pll->mode_set(dev_priv, pll); | |
1774 | } | |
1775 | } | |
1776 | ||
92f2584a | 1777 | /** |
85b3894f | 1778 | * intel_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1779 | * @dev_priv: i915 private structure |
1780 | * @pipe: pipe PLL to enable | |
1781 | * | |
1782 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1783 | * drives the transcoder clock. | |
1784 | */ | |
85b3894f | 1785 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1786 | { |
3d13ef2e DL |
1787 | struct drm_device *dev = crtc->base.dev; |
1788 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1789 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1790 | |
87a875bb | 1791 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1792 | return; |
1793 | ||
1794 | if (WARN_ON(pll->refcount == 0)) | |
1795 | return; | |
ee7b9f93 | 1796 | |
74dd6928 | 1797 | DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n", |
46edb027 | 1798 | pll->name, pll->active, pll->on, |
e2b78267 | 1799 | crtc->base.base.id); |
92f2584a | 1800 | |
cdbd2316 DV |
1801 | if (pll->active++) { |
1802 | WARN_ON(!pll->on); | |
e9d6944e | 1803 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1804 | return; |
1805 | } | |
f4a091c7 | 1806 | WARN_ON(pll->on); |
ee7b9f93 | 1807 | |
bd2bb1b9 PZ |
1808 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
1809 | ||
46edb027 | 1810 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1811 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1812 | pll->on = true; |
92f2584a JB |
1813 | } |
1814 | ||
f6daaec2 | 1815 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1816 | { |
3d13ef2e DL |
1817 | struct drm_device *dev = crtc->base.dev; |
1818 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1819 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1820 | |
92f2584a | 1821 | /* PCH only available on ILK+ */ |
3d13ef2e | 1822 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
87a875bb | 1823 | if (WARN_ON(pll == NULL)) |
ee7b9f93 | 1824 | return; |
92f2584a | 1825 | |
48da64a8 CW |
1826 | if (WARN_ON(pll->refcount == 0)) |
1827 | return; | |
7a419866 | 1828 | |
46edb027 DV |
1829 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1830 | pll->name, pll->active, pll->on, | |
e2b78267 | 1831 | crtc->base.base.id); |
7a419866 | 1832 | |
48da64a8 | 1833 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1834 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1835 | return; |
1836 | } | |
1837 | ||
e9d6944e | 1838 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1839 | WARN_ON(!pll->on); |
cdbd2316 | 1840 | if (--pll->active) |
7a419866 | 1841 | return; |
ee7b9f93 | 1842 | |
46edb027 | 1843 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1844 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1845 | pll->on = false; |
bd2bb1b9 PZ |
1846 | |
1847 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
92f2584a JB |
1848 | } |
1849 | ||
b8a4f404 PZ |
1850 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1851 | enum pipe pipe) | |
040484af | 1852 | { |
23670b32 | 1853 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1854 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1855 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
23670b32 | 1856 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1857 | |
1858 | /* PCH only available on ILK+ */ | |
3d13ef2e | 1859 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
040484af JB |
1860 | |
1861 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1862 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1863 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1864 | |
1865 | /* FDI must be feeding us bits for PCH ports */ | |
1866 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1867 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1868 | ||
23670b32 DV |
1869 | if (HAS_PCH_CPT(dev)) { |
1870 | /* Workaround: Set the timing override bit before enabling the | |
1871 | * pch transcoder. */ | |
1872 | reg = TRANS_CHICKEN2(pipe); | |
1873 | val = I915_READ(reg); | |
1874 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1875 | I915_WRITE(reg, val); | |
59c859d6 | 1876 | } |
23670b32 | 1877 | |
ab9412ba | 1878 | reg = PCH_TRANSCONF(pipe); |
040484af | 1879 | val = I915_READ(reg); |
5f7f726d | 1880 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1881 | |
1882 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1883 | /* | |
1884 | * make the BPC in transcoder be consistent with | |
1885 | * that in pipeconf reg. | |
1886 | */ | |
dfd07d72 DV |
1887 | val &= ~PIPECONF_BPC_MASK; |
1888 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1889 | } |
5f7f726d PZ |
1890 | |
1891 | val &= ~TRANS_INTERLACE_MASK; | |
1892 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 PZ |
1893 | if (HAS_PCH_IBX(dev_priv->dev) && |
1894 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) | |
1895 | val |= TRANS_LEGACY_INTERLACED_ILK; | |
1896 | else | |
1897 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1898 | else |
1899 | val |= TRANS_PROGRESSIVE; | |
1900 | ||
040484af JB |
1901 | I915_WRITE(reg, val | TRANS_ENABLE); |
1902 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 1903 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1904 | } |
1905 | ||
8fb033d7 | 1906 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1907 | enum transcoder cpu_transcoder) |
040484af | 1908 | { |
8fb033d7 | 1909 | u32 val, pipeconf_val; |
8fb033d7 PZ |
1910 | |
1911 | /* PCH only available on ILK+ */ | |
3d13ef2e | 1912 | BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5); |
8fb033d7 | 1913 | |
8fb033d7 | 1914 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1915 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1916 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1917 | |
223a6fdf PZ |
1918 | /* Workaround: set timing override bit. */ |
1919 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1920 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
1921 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1922 | ||
25f3ef11 | 1923 | val = TRANS_ENABLE; |
937bb610 | 1924 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1925 | |
9a76b1c6 PZ |
1926 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1927 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1928 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1929 | else |
1930 | val |= TRANS_PROGRESSIVE; | |
1931 | ||
ab9412ba DV |
1932 | I915_WRITE(LPT_TRANSCONF, val); |
1933 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 1934 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1935 | } |
1936 | ||
b8a4f404 PZ |
1937 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1938 | enum pipe pipe) | |
040484af | 1939 | { |
23670b32 DV |
1940 | struct drm_device *dev = dev_priv->dev; |
1941 | uint32_t reg, val; | |
040484af JB |
1942 | |
1943 | /* FDI relies on the transcoder */ | |
1944 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1945 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1946 | ||
291906f1 JB |
1947 | /* Ports must be off as well */ |
1948 | assert_pch_ports_disabled(dev_priv, pipe); | |
1949 | ||
ab9412ba | 1950 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1951 | val = I915_READ(reg); |
1952 | val &= ~TRANS_ENABLE; | |
1953 | I915_WRITE(reg, val); | |
1954 | /* wait for PCH transcoder off, transcoder state */ | |
1955 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 1956 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 DV |
1957 | |
1958 | if (!HAS_PCH_IBX(dev)) { | |
1959 | /* Workaround: Clear the timing override chicken bit again. */ | |
1960 | reg = TRANS_CHICKEN2(pipe); | |
1961 | val = I915_READ(reg); | |
1962 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1963 | I915_WRITE(reg, val); | |
1964 | } | |
040484af JB |
1965 | } |
1966 | ||
ab4d966c | 1967 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1968 | { |
8fb033d7 PZ |
1969 | u32 val; |
1970 | ||
ab9412ba | 1971 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1972 | val &= ~TRANS_ENABLE; |
ab9412ba | 1973 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1974 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 1975 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 1976 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1977 | |
1978 | /* Workaround: clear timing override bit. */ | |
1979 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1980 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 1981 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
1982 | } |
1983 | ||
b24e7179 | 1984 | /** |
309cfea8 | 1985 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 1986 | * @crtc: crtc responsible for the pipe |
b24e7179 | 1987 | * |
0372264a | 1988 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 1989 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 1990 | */ |
e1fdc473 | 1991 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1992 | { |
0372264a PZ |
1993 | struct drm_device *dev = crtc->base.dev; |
1994 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1995 | enum pipe pipe = crtc->pipe; | |
702e7a56 PZ |
1996 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1997 | pipe); | |
1a240d4d | 1998 | enum pipe pch_transcoder; |
b24e7179 JB |
1999 | int reg; |
2000 | u32 val; | |
2001 | ||
58c6eaa2 | 2002 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 2003 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
2004 | assert_sprites_disabled(dev_priv, pipe); |
2005 | ||
681e5811 | 2006 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
2007 | pch_transcoder = TRANSCODER_A; |
2008 | else | |
2009 | pch_transcoder = pipe; | |
2010 | ||
b24e7179 JB |
2011 | /* |
2012 | * A pipe without a PLL won't actually be able to drive bits from | |
2013 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
2014 | * need the check. | |
2015 | */ | |
2016 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
fbf3218a | 2017 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
2018 | assert_dsi_pll_enabled(dev_priv); |
2019 | else | |
2020 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2021 | else { |
30421c4f | 2022 | if (crtc->config.has_pch_encoder) { |
040484af | 2023 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2024 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2025 | assert_fdi_tx_pll_enabled(dev_priv, |
2026 | (enum pipe) cpu_transcoder); | |
040484af JB |
2027 | } |
2028 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2029 | } | |
b24e7179 | 2030 | |
702e7a56 | 2031 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2032 | val = I915_READ(reg); |
7ad25d48 PZ |
2033 | if (val & PIPECONF_ENABLE) { |
2034 | WARN_ON(!(pipe == PIPE_A && | |
2035 | dev_priv->quirks & QUIRK_PIPEA_FORCE)); | |
00d70b15 | 2036 | return; |
7ad25d48 | 2037 | } |
00d70b15 CW |
2038 | |
2039 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2040 | POSTING_READ(reg); |
b24e7179 JB |
2041 | } |
2042 | ||
2043 | /** | |
309cfea8 | 2044 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2045 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2046 | * |
575f7ab7 VS |
2047 | * Disable the pipe of @crtc, making sure that various hardware |
2048 | * specific requirements are met, if applicable, e.g. plane | |
2049 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2050 | * |
2051 | * Will wait until the pipe has shut down before returning. | |
2052 | */ | |
575f7ab7 | 2053 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2054 | { |
575f7ab7 VS |
2055 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
2056 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; | |
2057 | enum pipe pipe = crtc->pipe; | |
b24e7179 JB |
2058 | int reg; |
2059 | u32 val; | |
2060 | ||
2061 | /* | |
2062 | * Make sure planes won't keep trying to pump pixels to us, | |
2063 | * or we might hang the display. | |
2064 | */ | |
2065 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2066 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2067 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2068 | |
702e7a56 | 2069 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2070 | val = I915_READ(reg); |
00d70b15 CW |
2071 | if ((val & PIPECONF_ENABLE) == 0) |
2072 | return; | |
2073 | ||
67adc644 VS |
2074 | /* |
2075 | * Double wide has implications for planes | |
2076 | * so best keep it disabled when not needed. | |
2077 | */ | |
2078 | if (crtc->config.double_wide) | |
2079 | val &= ~PIPECONF_DOUBLE_WIDE; | |
2080 | ||
2081 | /* Don't disable pipe or pipe PLLs if needed */ | |
2082 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
2083 | val &= ~PIPECONF_ENABLE; | |
2084 | ||
2085 | I915_WRITE(reg, val); | |
2086 | if ((val & PIPECONF_ENABLE) == 0) | |
2087 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2088 | } |
2089 | ||
d74362c9 KP |
2090 | /* |
2091 | * Plane regs are double buffered, going from enabled->disabled needs a | |
2092 | * trigger in order to latch. The display address reg provides this. | |
2093 | */ | |
1dba99f4 VS |
2094 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
2095 | enum plane plane) | |
d74362c9 | 2096 | { |
3d13ef2e DL |
2097 | struct drm_device *dev = dev_priv->dev; |
2098 | u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); | |
1dba99f4 VS |
2099 | |
2100 | I915_WRITE(reg, I915_READ(reg)); | |
2101 | POSTING_READ(reg); | |
d74362c9 KP |
2102 | } |
2103 | ||
b24e7179 | 2104 | /** |
262ca2b0 | 2105 | * intel_enable_primary_hw_plane - enable the primary plane on a given pipe |
fdd508a6 VS |
2106 | * @plane: plane to be enabled |
2107 | * @crtc: crtc for the plane | |
b24e7179 | 2108 | * |
fdd508a6 | 2109 | * Enable @plane on @crtc, making sure that the pipe is running first. |
b24e7179 | 2110 | */ |
fdd508a6 VS |
2111 | static void intel_enable_primary_hw_plane(struct drm_plane *plane, |
2112 | struct drm_crtc *crtc) | |
b24e7179 | 2113 | { |
fdd508a6 VS |
2114 | struct drm_device *dev = plane->dev; |
2115 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2116 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b24e7179 JB |
2117 | |
2118 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
fdd508a6 | 2119 | assert_pipe_enabled(dev_priv, intel_crtc->pipe); |
b24e7179 | 2120 | |
98ec7739 VS |
2121 | if (intel_crtc->primary_enabled) |
2122 | return; | |
0037f71c | 2123 | |
4c445e0e | 2124 | intel_crtc->primary_enabled = true; |
939c2fe8 | 2125 | |
fdd508a6 VS |
2126 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
2127 | crtc->x, crtc->y); | |
33c3b0d1 VS |
2128 | |
2129 | /* | |
2130 | * BDW signals flip done immediately if the plane | |
2131 | * is disabled, even if the plane enable is already | |
2132 | * armed to occur at the next vblank :( | |
2133 | */ | |
2134 | if (IS_BROADWELL(dev)) | |
2135 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
b24e7179 JB |
2136 | } |
2137 | ||
b24e7179 | 2138 | /** |
262ca2b0 | 2139 | * intel_disable_primary_hw_plane - disable the primary hardware plane |
fdd508a6 VS |
2140 | * @plane: plane to be disabled |
2141 | * @crtc: crtc for the plane | |
b24e7179 | 2142 | * |
fdd508a6 | 2143 | * Disable @plane on @crtc, making sure that the pipe is running first. |
b24e7179 | 2144 | */ |
fdd508a6 VS |
2145 | static void intel_disable_primary_hw_plane(struct drm_plane *plane, |
2146 | struct drm_crtc *crtc) | |
b24e7179 | 2147 | { |
fdd508a6 VS |
2148 | struct drm_device *dev = plane->dev; |
2149 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2150 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2151 | ||
2152 | assert_pipe_enabled(dev_priv, intel_crtc->pipe); | |
b24e7179 | 2153 | |
98ec7739 VS |
2154 | if (!intel_crtc->primary_enabled) |
2155 | return; | |
0037f71c | 2156 | |
4c445e0e | 2157 | intel_crtc->primary_enabled = false; |
939c2fe8 | 2158 | |
fdd508a6 VS |
2159 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
2160 | crtc->x, crtc->y); | |
b24e7179 JB |
2161 | } |
2162 | ||
693db184 CW |
2163 | static bool need_vtd_wa(struct drm_device *dev) |
2164 | { | |
2165 | #ifdef CONFIG_INTEL_IOMMU | |
2166 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2167 | return true; | |
2168 | #endif | |
2169 | return false; | |
2170 | } | |
2171 | ||
a57ce0b2 JB |
2172 | static int intel_align_height(struct drm_device *dev, int height, bool tiled) |
2173 | { | |
2174 | int tile_height; | |
2175 | ||
2176 | tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1; | |
2177 | return ALIGN(height, tile_height); | |
2178 | } | |
2179 | ||
127bd2ac | 2180 | int |
48b956c5 | 2181 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 2182 | struct drm_i915_gem_object *obj, |
a4872ba6 | 2183 | struct intel_engine_cs *pipelined) |
6b95a207 | 2184 | { |
ce453d81 | 2185 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
2186 | u32 alignment; |
2187 | int ret; | |
2188 | ||
ebcdd39e MR |
2189 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2190 | ||
05394f39 | 2191 | switch (obj->tiling_mode) { |
6b95a207 | 2192 | case I915_TILING_NONE: |
534843da CW |
2193 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
2194 | alignment = 128 * 1024; | |
a6c45cf0 | 2195 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
2196 | alignment = 4 * 1024; |
2197 | else | |
2198 | alignment = 64 * 1024; | |
6b95a207 KH |
2199 | break; |
2200 | case I915_TILING_X: | |
2201 | /* pin() will align the object as required by fence */ | |
2202 | alignment = 0; | |
2203 | break; | |
2204 | case I915_TILING_Y: | |
80075d49 | 2205 | WARN(1, "Y tiled bo slipped through, driver bug!\n"); |
6b95a207 KH |
2206 | return -EINVAL; |
2207 | default: | |
2208 | BUG(); | |
2209 | } | |
2210 | ||
693db184 CW |
2211 | /* Note that the w/a also requires 64 PTE of padding following the |
2212 | * bo. We currently fill all unused PTE with the shadow page and so | |
2213 | * we should always have valid PTE following the scanout preventing | |
2214 | * the VT-d warning. | |
2215 | */ | |
2216 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2217 | alignment = 256 * 1024; | |
2218 | ||
ce453d81 | 2219 | dev_priv->mm.interruptible = false; |
2da3b9b9 | 2220 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
48b956c5 | 2221 | if (ret) |
ce453d81 | 2222 | goto err_interruptible; |
6b95a207 KH |
2223 | |
2224 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2225 | * fence, whereas 965+ only requires a fence if using | |
2226 | * framebuffer compression. For simplicity, we always install | |
2227 | * a fence as the cost is not that onerous. | |
2228 | */ | |
06d98131 | 2229 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
2230 | if (ret) |
2231 | goto err_unpin; | |
1690e1eb | 2232 | |
9a5a53b3 | 2233 | i915_gem_object_pin_fence(obj); |
6b95a207 | 2234 | |
ce453d81 | 2235 | dev_priv->mm.interruptible = true; |
6b95a207 | 2236 | return 0; |
48b956c5 CW |
2237 | |
2238 | err_unpin: | |
cc98b413 | 2239 | i915_gem_object_unpin_from_display_plane(obj); |
ce453d81 CW |
2240 | err_interruptible: |
2241 | dev_priv->mm.interruptible = true; | |
48b956c5 | 2242 | return ret; |
6b95a207 KH |
2243 | } |
2244 | ||
1690e1eb CW |
2245 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
2246 | { | |
ebcdd39e MR |
2247 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2248 | ||
1690e1eb | 2249 | i915_gem_object_unpin_fence(obj); |
cc98b413 | 2250 | i915_gem_object_unpin_from_display_plane(obj); |
1690e1eb CW |
2251 | } |
2252 | ||
c2c75131 DV |
2253 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2254 | * is assumed to be a power-of-two. */ | |
bc752862 CW |
2255 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
2256 | unsigned int tiling_mode, | |
2257 | unsigned int cpp, | |
2258 | unsigned int pitch) | |
c2c75131 | 2259 | { |
bc752862 CW |
2260 | if (tiling_mode != I915_TILING_NONE) { |
2261 | unsigned int tile_rows, tiles; | |
c2c75131 | 2262 | |
bc752862 CW |
2263 | tile_rows = *y / 8; |
2264 | *y %= 8; | |
c2c75131 | 2265 | |
bc752862 CW |
2266 | tiles = *x / (512/cpp); |
2267 | *x %= 512/cpp; | |
2268 | ||
2269 | return tile_rows * pitch * 8 + tiles * 4096; | |
2270 | } else { | |
2271 | unsigned int offset; | |
2272 | ||
2273 | offset = *y * pitch + *x * cpp; | |
2274 | *y = 0; | |
2275 | *x = (offset & 4095) / cpp; | |
2276 | return offset & -4096; | |
2277 | } | |
c2c75131 DV |
2278 | } |
2279 | ||
46f297fb JB |
2280 | int intel_format_to_fourcc(int format) |
2281 | { | |
2282 | switch (format) { | |
2283 | case DISPPLANE_8BPP: | |
2284 | return DRM_FORMAT_C8; | |
2285 | case DISPPLANE_BGRX555: | |
2286 | return DRM_FORMAT_XRGB1555; | |
2287 | case DISPPLANE_BGRX565: | |
2288 | return DRM_FORMAT_RGB565; | |
2289 | default: | |
2290 | case DISPPLANE_BGRX888: | |
2291 | return DRM_FORMAT_XRGB8888; | |
2292 | case DISPPLANE_RGBX888: | |
2293 | return DRM_FORMAT_XBGR8888; | |
2294 | case DISPPLANE_BGRX101010: | |
2295 | return DRM_FORMAT_XRGB2101010; | |
2296 | case DISPPLANE_RGBX101010: | |
2297 | return DRM_FORMAT_XBGR2101010; | |
2298 | } | |
2299 | } | |
2300 | ||
484b41dd | 2301 | static bool intel_alloc_plane_obj(struct intel_crtc *crtc, |
46f297fb JB |
2302 | struct intel_plane_config *plane_config) |
2303 | { | |
2304 | struct drm_device *dev = crtc->base.dev; | |
2305 | struct drm_i915_gem_object *obj = NULL; | |
2306 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2307 | u32 base = plane_config->base; | |
2308 | ||
ff2652ea CW |
2309 | if (plane_config->size == 0) |
2310 | return false; | |
2311 | ||
46f297fb JB |
2312 | obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base, |
2313 | plane_config->size); | |
2314 | if (!obj) | |
484b41dd | 2315 | return false; |
46f297fb JB |
2316 | |
2317 | if (plane_config->tiled) { | |
2318 | obj->tiling_mode = I915_TILING_X; | |
66e514c1 | 2319 | obj->stride = crtc->base.primary->fb->pitches[0]; |
46f297fb JB |
2320 | } |
2321 | ||
66e514c1 DA |
2322 | mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format; |
2323 | mode_cmd.width = crtc->base.primary->fb->width; | |
2324 | mode_cmd.height = crtc->base.primary->fb->height; | |
2325 | mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0]; | |
46f297fb JB |
2326 | |
2327 | mutex_lock(&dev->struct_mutex); | |
2328 | ||
66e514c1 | 2329 | if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb), |
484b41dd | 2330 | &mode_cmd, obj)) { |
46f297fb JB |
2331 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2332 | goto out_unref_obj; | |
2333 | } | |
2334 | ||
a071fa00 | 2335 | obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe); |
46f297fb | 2336 | mutex_unlock(&dev->struct_mutex); |
484b41dd JB |
2337 | |
2338 | DRM_DEBUG_KMS("plane fb obj %p\n", obj); | |
2339 | return true; | |
46f297fb JB |
2340 | |
2341 | out_unref_obj: | |
2342 | drm_gem_object_unreference(&obj->base); | |
2343 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2344 | return false; |
2345 | } | |
2346 | ||
2347 | static void intel_find_plane_obj(struct intel_crtc *intel_crtc, | |
2348 | struct intel_plane_config *plane_config) | |
2349 | { | |
2350 | struct drm_device *dev = intel_crtc->base.dev; | |
2351 | struct drm_crtc *c; | |
2352 | struct intel_crtc *i; | |
2ff8fde1 | 2353 | struct drm_i915_gem_object *obj; |
484b41dd | 2354 | |
66e514c1 | 2355 | if (!intel_crtc->base.primary->fb) |
484b41dd JB |
2356 | return; |
2357 | ||
2358 | if (intel_alloc_plane_obj(intel_crtc, plane_config)) | |
2359 | return; | |
2360 | ||
66e514c1 DA |
2361 | kfree(intel_crtc->base.primary->fb); |
2362 | intel_crtc->base.primary->fb = NULL; | |
484b41dd JB |
2363 | |
2364 | /* | |
2365 | * Failed to alloc the obj, check to see if we should share | |
2366 | * an fb with another CRTC instead | |
2367 | */ | |
70e1e0ec | 2368 | for_each_crtc(dev, c) { |
484b41dd JB |
2369 | i = to_intel_crtc(c); |
2370 | ||
2371 | if (c == &intel_crtc->base) | |
2372 | continue; | |
2373 | ||
2ff8fde1 MR |
2374 | if (!i->active) |
2375 | continue; | |
2376 | ||
2377 | obj = intel_fb_obj(c->primary->fb); | |
2378 | if (obj == NULL) | |
484b41dd JB |
2379 | continue; |
2380 | ||
2ff8fde1 | 2381 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
66e514c1 DA |
2382 | drm_framebuffer_reference(c->primary->fb); |
2383 | intel_crtc->base.primary->fb = c->primary->fb; | |
2ff8fde1 | 2384 | obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); |
484b41dd JB |
2385 | break; |
2386 | } | |
2387 | } | |
46f297fb JB |
2388 | } |
2389 | ||
29b9bde6 DV |
2390 | static void i9xx_update_primary_plane(struct drm_crtc *crtc, |
2391 | struct drm_framebuffer *fb, | |
2392 | int x, int y) | |
81255565 JB |
2393 | { |
2394 | struct drm_device *dev = crtc->dev; | |
2395 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2396 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
c9ba6fad | 2397 | struct drm_i915_gem_object *obj; |
81255565 | 2398 | int plane = intel_crtc->plane; |
e506a0c6 | 2399 | unsigned long linear_offset; |
81255565 | 2400 | u32 dspcntr; |
f45651ba | 2401 | u32 reg = DSPCNTR(plane); |
48404c1e SJ |
2402 | int pixel_size; |
2403 | ||
fdd508a6 VS |
2404 | if (!intel_crtc->primary_enabled) { |
2405 | I915_WRITE(reg, 0); | |
2406 | if (INTEL_INFO(dev)->gen >= 4) | |
2407 | I915_WRITE(DSPSURF(plane), 0); | |
2408 | else | |
2409 | I915_WRITE(DSPADDR(plane), 0); | |
2410 | POSTING_READ(reg); | |
2411 | return; | |
2412 | } | |
2413 | ||
c9ba6fad VS |
2414 | obj = intel_fb_obj(fb); |
2415 | if (WARN_ON(obj == NULL)) | |
2416 | return; | |
2417 | ||
2418 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2419 | ||
f45651ba VS |
2420 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2421 | ||
fdd508a6 | 2422 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2423 | |
2424 | if (INTEL_INFO(dev)->gen < 4) { | |
2425 | if (intel_crtc->pipe == PIPE_B) | |
2426 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2427 | ||
2428 | /* pipesrc and dspsize control the size that is scaled from, | |
2429 | * which should always be the user's requested size. | |
2430 | */ | |
2431 | I915_WRITE(DSPSIZE(plane), | |
2432 | ((intel_crtc->config.pipe_src_h - 1) << 16) | | |
2433 | (intel_crtc->config.pipe_src_w - 1)); | |
2434 | I915_WRITE(DSPPOS(plane), 0); | |
2435 | } | |
81255565 | 2436 | |
57779d06 VS |
2437 | switch (fb->pixel_format) { |
2438 | case DRM_FORMAT_C8: | |
81255565 JB |
2439 | dspcntr |= DISPPLANE_8BPP; |
2440 | break; | |
57779d06 VS |
2441 | case DRM_FORMAT_XRGB1555: |
2442 | case DRM_FORMAT_ARGB1555: | |
2443 | dspcntr |= DISPPLANE_BGRX555; | |
81255565 | 2444 | break; |
57779d06 VS |
2445 | case DRM_FORMAT_RGB565: |
2446 | dspcntr |= DISPPLANE_BGRX565; | |
2447 | break; | |
2448 | case DRM_FORMAT_XRGB8888: | |
2449 | case DRM_FORMAT_ARGB8888: | |
2450 | dspcntr |= DISPPLANE_BGRX888; | |
2451 | break; | |
2452 | case DRM_FORMAT_XBGR8888: | |
2453 | case DRM_FORMAT_ABGR8888: | |
2454 | dspcntr |= DISPPLANE_RGBX888; | |
2455 | break; | |
2456 | case DRM_FORMAT_XRGB2101010: | |
2457 | case DRM_FORMAT_ARGB2101010: | |
2458 | dspcntr |= DISPPLANE_BGRX101010; | |
2459 | break; | |
2460 | case DRM_FORMAT_XBGR2101010: | |
2461 | case DRM_FORMAT_ABGR2101010: | |
2462 | dspcntr |= DISPPLANE_RGBX101010; | |
81255565 JB |
2463 | break; |
2464 | default: | |
baba133a | 2465 | BUG(); |
81255565 | 2466 | } |
57779d06 | 2467 | |
f45651ba VS |
2468 | if (INTEL_INFO(dev)->gen >= 4 && |
2469 | obj->tiling_mode != I915_TILING_NONE) | |
2470 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2471 | |
de1aa629 VS |
2472 | if (IS_G4X(dev)) |
2473 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2474 | ||
b9897127 | 2475 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
81255565 | 2476 | |
c2c75131 DV |
2477 | if (INTEL_INFO(dev)->gen >= 4) { |
2478 | intel_crtc->dspaddr_offset = | |
bc752862 | 2479 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
b9897127 | 2480 | pixel_size, |
bc752862 | 2481 | fb->pitches[0]); |
c2c75131 DV |
2482 | linear_offset -= intel_crtc->dspaddr_offset; |
2483 | } else { | |
e506a0c6 | 2484 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2485 | } |
e506a0c6 | 2486 | |
48404c1e SJ |
2487 | if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) { |
2488 | dspcntr |= DISPPLANE_ROTATE_180; | |
2489 | ||
2490 | x += (intel_crtc->config.pipe_src_w - 1); | |
2491 | y += (intel_crtc->config.pipe_src_h - 1); | |
2492 | ||
2493 | /* Finding the last pixel of the last line of the display | |
2494 | data and adding to linear_offset*/ | |
2495 | linear_offset += | |
2496 | (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] + | |
2497 | (intel_crtc->config.pipe_src_w - 1) * pixel_size; | |
2498 | } | |
2499 | ||
2500 | I915_WRITE(reg, dspcntr); | |
2501 | ||
f343c5f6 BW |
2502 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2503 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2504 | fb->pitches[0]); | |
01f2c773 | 2505 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2506 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2507 | I915_WRITE(DSPSURF(plane), |
2508 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2509 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2510 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2511 | } else |
f343c5f6 | 2512 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2513 | POSTING_READ(reg); |
17638cd6 JB |
2514 | } |
2515 | ||
29b9bde6 DV |
2516 | static void ironlake_update_primary_plane(struct drm_crtc *crtc, |
2517 | struct drm_framebuffer *fb, | |
2518 | int x, int y) | |
17638cd6 JB |
2519 | { |
2520 | struct drm_device *dev = crtc->dev; | |
2521 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2522 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
c9ba6fad | 2523 | struct drm_i915_gem_object *obj; |
17638cd6 | 2524 | int plane = intel_crtc->plane; |
e506a0c6 | 2525 | unsigned long linear_offset; |
17638cd6 | 2526 | u32 dspcntr; |
f45651ba | 2527 | u32 reg = DSPCNTR(plane); |
48404c1e SJ |
2528 | int pixel_size; |
2529 | ||
fdd508a6 VS |
2530 | if (!intel_crtc->primary_enabled) { |
2531 | I915_WRITE(reg, 0); | |
2532 | I915_WRITE(DSPSURF(plane), 0); | |
2533 | POSTING_READ(reg); | |
2534 | return; | |
2535 | } | |
2536 | ||
c9ba6fad VS |
2537 | obj = intel_fb_obj(fb); |
2538 | if (WARN_ON(obj == NULL)) | |
2539 | return; | |
2540 | ||
2541 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2542 | ||
f45651ba VS |
2543 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2544 | ||
fdd508a6 | 2545 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2546 | |
2547 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2548 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2549 | |
57779d06 VS |
2550 | switch (fb->pixel_format) { |
2551 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2552 | dspcntr |= DISPPLANE_8BPP; |
2553 | break; | |
57779d06 VS |
2554 | case DRM_FORMAT_RGB565: |
2555 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2556 | break; |
57779d06 VS |
2557 | case DRM_FORMAT_XRGB8888: |
2558 | case DRM_FORMAT_ARGB8888: | |
2559 | dspcntr |= DISPPLANE_BGRX888; | |
2560 | break; | |
2561 | case DRM_FORMAT_XBGR8888: | |
2562 | case DRM_FORMAT_ABGR8888: | |
2563 | dspcntr |= DISPPLANE_RGBX888; | |
2564 | break; | |
2565 | case DRM_FORMAT_XRGB2101010: | |
2566 | case DRM_FORMAT_ARGB2101010: | |
2567 | dspcntr |= DISPPLANE_BGRX101010; | |
2568 | break; | |
2569 | case DRM_FORMAT_XBGR2101010: | |
2570 | case DRM_FORMAT_ABGR2101010: | |
2571 | dspcntr |= DISPPLANE_RGBX101010; | |
17638cd6 JB |
2572 | break; |
2573 | default: | |
baba133a | 2574 | BUG(); |
17638cd6 JB |
2575 | } |
2576 | ||
2577 | if (obj->tiling_mode != I915_TILING_NONE) | |
2578 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2579 | |
f45651ba | 2580 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2581 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2582 | |
b9897127 | 2583 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
c2c75131 | 2584 | intel_crtc->dspaddr_offset = |
bc752862 | 2585 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
b9897127 | 2586 | pixel_size, |
bc752862 | 2587 | fb->pitches[0]); |
c2c75131 | 2588 | linear_offset -= intel_crtc->dspaddr_offset; |
48404c1e SJ |
2589 | if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) { |
2590 | dspcntr |= DISPPLANE_ROTATE_180; | |
2591 | ||
2592 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
2593 | x += (intel_crtc->config.pipe_src_w - 1); | |
2594 | y += (intel_crtc->config.pipe_src_h - 1); | |
2595 | ||
2596 | /* Finding the last pixel of the last line of the display | |
2597 | data and adding to linear_offset*/ | |
2598 | linear_offset += | |
2599 | (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] + | |
2600 | (intel_crtc->config.pipe_src_w - 1) * pixel_size; | |
2601 | } | |
2602 | } | |
2603 | ||
2604 | I915_WRITE(reg, dspcntr); | |
17638cd6 | 2605 | |
f343c5f6 BW |
2606 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2607 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2608 | fb->pitches[0]); | |
01f2c773 | 2609 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2610 | I915_WRITE(DSPSURF(plane), |
2611 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2612 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2613 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2614 | } else { | |
2615 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2616 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2617 | } | |
17638cd6 | 2618 | POSTING_READ(reg); |
17638cd6 JB |
2619 | } |
2620 | ||
2621 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ | |
2622 | static int | |
2623 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
2624 | int x, int y, enum mode_set_atomic state) | |
2625 | { | |
2626 | struct drm_device *dev = crtc->dev; | |
2627 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 2628 | |
6b8e6ed0 CW |
2629 | if (dev_priv->display.disable_fbc) |
2630 | dev_priv->display.disable_fbc(dev); | |
cc36513c | 2631 | intel_increase_pllclock(dev, to_intel_crtc(crtc)->pipe); |
81255565 | 2632 | |
29b9bde6 DV |
2633 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
2634 | ||
2635 | return 0; | |
81255565 JB |
2636 | } |
2637 | ||
96a02917 VS |
2638 | void intel_display_handle_reset(struct drm_device *dev) |
2639 | { | |
2640 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2641 | struct drm_crtc *crtc; | |
2642 | ||
2643 | /* | |
2644 | * Flips in the rings have been nuked by the reset, | |
2645 | * so complete all pending flips so that user space | |
2646 | * will get its events and not get stuck. | |
2647 | * | |
2648 | * Also update the base address of all primary | |
2649 | * planes to the the last fb to make sure we're | |
2650 | * showing the correct fb after a reset. | |
2651 | * | |
2652 | * Need to make two loops over the crtcs so that we | |
2653 | * don't try to grab a crtc mutex before the | |
2654 | * pending_flip_queue really got woken up. | |
2655 | */ | |
2656 | ||
70e1e0ec | 2657 | for_each_crtc(dev, crtc) { |
96a02917 VS |
2658 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2659 | enum plane plane = intel_crtc->plane; | |
2660 | ||
2661 | intel_prepare_page_flip(dev, plane); | |
2662 | intel_finish_page_flip_plane(dev, plane); | |
2663 | } | |
2664 | ||
70e1e0ec | 2665 | for_each_crtc(dev, crtc) { |
96a02917 VS |
2666 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2667 | ||
51fd371b | 2668 | drm_modeset_lock(&crtc->mutex, NULL); |
947fdaad CW |
2669 | /* |
2670 | * FIXME: Once we have proper support for primary planes (and | |
2671 | * disabling them without disabling the entire crtc) allow again | |
66e514c1 | 2672 | * a NULL crtc->primary->fb. |
947fdaad | 2673 | */ |
f4510a27 | 2674 | if (intel_crtc->active && crtc->primary->fb) |
262ca2b0 | 2675 | dev_priv->display.update_primary_plane(crtc, |
66e514c1 | 2676 | crtc->primary->fb, |
262ca2b0 MR |
2677 | crtc->x, |
2678 | crtc->y); | |
51fd371b | 2679 | drm_modeset_unlock(&crtc->mutex); |
96a02917 VS |
2680 | } |
2681 | } | |
2682 | ||
14667a4b CW |
2683 | static int |
2684 | intel_finish_fb(struct drm_framebuffer *old_fb) | |
2685 | { | |
2ff8fde1 | 2686 | struct drm_i915_gem_object *obj = intel_fb_obj(old_fb); |
14667a4b CW |
2687 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
2688 | bool was_interruptible = dev_priv->mm.interruptible; | |
2689 | int ret; | |
2690 | ||
14667a4b CW |
2691 | /* Big Hammer, we also need to ensure that any pending |
2692 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
2693 | * current scanout is retired before unpinning the old | |
2694 | * framebuffer. | |
2695 | * | |
2696 | * This should only fail upon a hung GPU, in which case we | |
2697 | * can safely continue. | |
2698 | */ | |
2699 | dev_priv->mm.interruptible = false; | |
2700 | ret = i915_gem_object_finish_gpu(obj); | |
2701 | dev_priv->mm.interruptible = was_interruptible; | |
2702 | ||
2703 | return ret; | |
2704 | } | |
2705 | ||
7d5e3799 CW |
2706 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
2707 | { | |
2708 | struct drm_device *dev = crtc->dev; | |
2709 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2710 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2711 | unsigned long flags; | |
2712 | bool pending; | |
2713 | ||
2714 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
2715 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
2716 | return false; | |
2717 | ||
2718 | spin_lock_irqsave(&dev->event_lock, flags); | |
2719 | pending = to_intel_crtc(crtc)->unpin_work != NULL; | |
2720 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
2721 | ||
2722 | return pending; | |
2723 | } | |
2724 | ||
5c3b82e2 | 2725 | static int |
3c4fdcfb | 2726 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
94352cf9 | 2727 | struct drm_framebuffer *fb) |
79e53945 JB |
2728 | { |
2729 | struct drm_device *dev = crtc->dev; | |
6b8e6ed0 | 2730 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 2731 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
a071fa00 | 2732 | enum pipe pipe = intel_crtc->pipe; |
2ff8fde1 MR |
2733 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2734 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
2735 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb); | |
5c3b82e2 | 2736 | int ret; |
79e53945 | 2737 | |
7d5e3799 CW |
2738 | if (intel_crtc_has_pending_flip(crtc)) { |
2739 | DRM_ERROR("pipe is still busy with an old pageflip\n"); | |
2740 | return -EBUSY; | |
2741 | } | |
2742 | ||
79e53945 | 2743 | /* no fb bound */ |
94352cf9 | 2744 | if (!fb) { |
a5071c2f | 2745 | DRM_ERROR("No FB bound\n"); |
5c3b82e2 CW |
2746 | return 0; |
2747 | } | |
2748 | ||
7eb552ae | 2749 | if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) { |
84f44ce7 VS |
2750 | DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n", |
2751 | plane_name(intel_crtc->plane), | |
2752 | INTEL_INFO(dev)->num_pipes); | |
5c3b82e2 | 2753 | return -EINVAL; |
79e53945 JB |
2754 | } |
2755 | ||
5c3b82e2 | 2756 | mutex_lock(&dev->struct_mutex); |
a071fa00 DV |
2757 | ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); |
2758 | if (ret == 0) | |
91565c85 | 2759 | i915_gem_track_fb(old_obj, obj, |
a071fa00 | 2760 | INTEL_FRONTBUFFER_PRIMARY(pipe)); |
8ac36ec1 | 2761 | mutex_unlock(&dev->struct_mutex); |
5c3b82e2 | 2762 | if (ret != 0) { |
a5071c2f | 2763 | DRM_ERROR("pin & fence failed\n"); |
5c3b82e2 CW |
2764 | return ret; |
2765 | } | |
79e53945 | 2766 | |
bb2043de DL |
2767 | /* |
2768 | * Update pipe size and adjust fitter if needed: the reason for this is | |
2769 | * that in compute_mode_changes we check the native mode (not the pfit | |
2770 | * mode) to see if we can flip rather than do a full mode set. In the | |
2771 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
2772 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
2773 | * sized surface. | |
2774 | * | |
2775 | * To fix this properly, we need to hoist the checks up into | |
2776 | * compute_mode_changes (or above), check the actual pfit state and | |
2777 | * whether the platform allows pfit disable with pipe active, and only | |
2778 | * then update the pipesrc and pfit state, even on the flip path. | |
2779 | */ | |
d330a953 | 2780 | if (i915.fastboot) { |
d7bf63f2 DL |
2781 | const struct drm_display_mode *adjusted_mode = |
2782 | &intel_crtc->config.adjusted_mode; | |
2783 | ||
4d6a3e63 | 2784 | I915_WRITE(PIPESRC(intel_crtc->pipe), |
d7bf63f2 DL |
2785 | ((adjusted_mode->crtc_hdisplay - 1) << 16) | |
2786 | (adjusted_mode->crtc_vdisplay - 1)); | |
fd4daa9c | 2787 | if (!intel_crtc->config.pch_pfit.enabled && |
4d6a3e63 JB |
2788 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
2789 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
2790 | I915_WRITE(PF_CTL(intel_crtc->pipe), 0); | |
2791 | I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0); | |
2792 | I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0); | |
2793 | } | |
0637d60d JB |
2794 | intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay; |
2795 | intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay; | |
4d6a3e63 JB |
2796 | } |
2797 | ||
29b9bde6 | 2798 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
3c4fdcfb | 2799 | |
f99d7069 DV |
2800 | if (intel_crtc->active) |
2801 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); | |
2802 | ||
f4510a27 | 2803 | crtc->primary->fb = fb; |
6c4c86f5 DV |
2804 | crtc->x = x; |
2805 | crtc->y = y; | |
94352cf9 | 2806 | |
b7f1de28 | 2807 | if (old_fb) { |
d7697eea DV |
2808 | if (intel_crtc->active && old_fb != fb) |
2809 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
8ac36ec1 | 2810 | mutex_lock(&dev->struct_mutex); |
2ff8fde1 | 2811 | intel_unpin_fb_obj(old_obj); |
8ac36ec1 | 2812 | mutex_unlock(&dev->struct_mutex); |
b7f1de28 | 2813 | } |
652c393a | 2814 | |
8ac36ec1 | 2815 | mutex_lock(&dev->struct_mutex); |
6b8e6ed0 | 2816 | intel_update_fbc(dev); |
5c3b82e2 | 2817 | mutex_unlock(&dev->struct_mutex); |
79e53945 | 2818 | |
5c3b82e2 | 2819 | return 0; |
79e53945 JB |
2820 | } |
2821 | ||
5e84e1a4 ZW |
2822 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2823 | { | |
2824 | struct drm_device *dev = crtc->dev; | |
2825 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2826 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2827 | int pipe = intel_crtc->pipe; | |
2828 | u32 reg, temp; | |
2829 | ||
2830 | /* enable normal train */ | |
2831 | reg = FDI_TX_CTL(pipe); | |
2832 | temp = I915_READ(reg); | |
61e499bf | 2833 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
2834 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2835 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
2836 | } else { |
2837 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2838 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 2839 | } |
5e84e1a4 ZW |
2840 | I915_WRITE(reg, temp); |
2841 | ||
2842 | reg = FDI_RX_CTL(pipe); | |
2843 | temp = I915_READ(reg); | |
2844 | if (HAS_PCH_CPT(dev)) { | |
2845 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2846 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
2847 | } else { | |
2848 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2849 | temp |= FDI_LINK_TRAIN_NONE; | |
2850 | } | |
2851 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
2852 | ||
2853 | /* wait one idle pattern time */ | |
2854 | POSTING_READ(reg); | |
2855 | udelay(1000); | |
357555c0 JB |
2856 | |
2857 | /* IVB wants error correction enabled */ | |
2858 | if (IS_IVYBRIDGE(dev)) | |
2859 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
2860 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
2861 | } |
2862 | ||
1fbc0d78 | 2863 | static bool pipe_has_enabled_pch(struct intel_crtc *crtc) |
1e833f40 | 2864 | { |
1fbc0d78 DV |
2865 | return crtc->base.enabled && crtc->active && |
2866 | crtc->config.has_pch_encoder; | |
1e833f40 DV |
2867 | } |
2868 | ||
01a415fd DV |
2869 | static void ivb_modeset_global_resources(struct drm_device *dev) |
2870 | { | |
2871 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2872 | struct intel_crtc *pipe_B_crtc = | |
2873 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
2874 | struct intel_crtc *pipe_C_crtc = | |
2875 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); | |
2876 | uint32_t temp; | |
2877 | ||
1e833f40 DV |
2878 | /* |
2879 | * When everything is off disable fdi C so that we could enable fdi B | |
2880 | * with all lanes. Note that we don't care about enabled pipes without | |
2881 | * an enabled pch encoder. | |
2882 | */ | |
2883 | if (!pipe_has_enabled_pch(pipe_B_crtc) && | |
2884 | !pipe_has_enabled_pch(pipe_C_crtc)) { | |
01a415fd DV |
2885 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
2886 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
2887 | ||
2888 | temp = I915_READ(SOUTH_CHICKEN1); | |
2889 | temp &= ~FDI_BC_BIFURCATION_SELECT; | |
2890 | DRM_DEBUG_KMS("disabling fdi C rx\n"); | |
2891 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
2892 | } | |
2893 | } | |
2894 | ||
8db9d77b ZW |
2895 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2896 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
2897 | { | |
2898 | struct drm_device *dev = crtc->dev; | |
2899 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2900 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2901 | int pipe = intel_crtc->pipe; | |
5eddb70b | 2902 | u32 reg, temp, tries; |
8db9d77b | 2903 | |
1c8562f6 | 2904 | /* FDI needs bits from pipe first */ |
0fc932b8 | 2905 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 2906 | |
e1a44743 AJ |
2907 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2908 | for train result */ | |
5eddb70b CW |
2909 | reg = FDI_RX_IMR(pipe); |
2910 | temp = I915_READ(reg); | |
e1a44743 AJ |
2911 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2912 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2913 | I915_WRITE(reg, temp); |
2914 | I915_READ(reg); | |
e1a44743 AJ |
2915 | udelay(150); |
2916 | ||
8db9d77b | 2917 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2918 | reg = FDI_TX_CTL(pipe); |
2919 | temp = I915_READ(reg); | |
627eb5a3 DV |
2920 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2921 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
2922 | temp &= ~FDI_LINK_TRAIN_NONE; |
2923 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 2924 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2925 | |
5eddb70b CW |
2926 | reg = FDI_RX_CTL(pipe); |
2927 | temp = I915_READ(reg); | |
8db9d77b ZW |
2928 | temp &= ~FDI_LINK_TRAIN_NONE; |
2929 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
2930 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2931 | ||
2932 | POSTING_READ(reg); | |
8db9d77b ZW |
2933 | udelay(150); |
2934 | ||
5b2adf89 | 2935 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
2936 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
2937 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
2938 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 2939 | |
5eddb70b | 2940 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2941 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2942 | temp = I915_READ(reg); |
8db9d77b ZW |
2943 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2944 | ||
2945 | if ((temp & FDI_RX_BIT_LOCK)) { | |
2946 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 2947 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
2948 | break; |
2949 | } | |
8db9d77b | 2950 | } |
e1a44743 | 2951 | if (tries == 5) |
5eddb70b | 2952 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2953 | |
2954 | /* Train 2 */ | |
5eddb70b CW |
2955 | reg = FDI_TX_CTL(pipe); |
2956 | temp = I915_READ(reg); | |
8db9d77b ZW |
2957 | temp &= ~FDI_LINK_TRAIN_NONE; |
2958 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2959 | I915_WRITE(reg, temp); |
8db9d77b | 2960 | |
5eddb70b CW |
2961 | reg = FDI_RX_CTL(pipe); |
2962 | temp = I915_READ(reg); | |
8db9d77b ZW |
2963 | temp &= ~FDI_LINK_TRAIN_NONE; |
2964 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2965 | I915_WRITE(reg, temp); |
8db9d77b | 2966 | |
5eddb70b CW |
2967 | POSTING_READ(reg); |
2968 | udelay(150); | |
8db9d77b | 2969 | |
5eddb70b | 2970 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2971 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2972 | temp = I915_READ(reg); |
8db9d77b ZW |
2973 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2974 | ||
2975 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 2976 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
2977 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2978 | break; | |
2979 | } | |
8db9d77b | 2980 | } |
e1a44743 | 2981 | if (tries == 5) |
5eddb70b | 2982 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2983 | |
2984 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 2985 | |
8db9d77b ZW |
2986 | } |
2987 | ||
0206e353 | 2988 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
2989 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2990 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
2991 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
2992 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
2993 | }; | |
2994 | ||
2995 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
2996 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
2997 | { | |
2998 | struct drm_device *dev = crtc->dev; | |
2999 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3000 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3001 | int pipe = intel_crtc->pipe; | |
fa37d39e | 3002 | u32 reg, temp, i, retry; |
8db9d77b | 3003 | |
e1a44743 AJ |
3004 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3005 | for train result */ | |
5eddb70b CW |
3006 | reg = FDI_RX_IMR(pipe); |
3007 | temp = I915_READ(reg); | |
e1a44743 AJ |
3008 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3009 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3010 | I915_WRITE(reg, temp); |
3011 | ||
3012 | POSTING_READ(reg); | |
e1a44743 AJ |
3013 | udelay(150); |
3014 | ||
8db9d77b | 3015 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3016 | reg = FDI_TX_CTL(pipe); |
3017 | temp = I915_READ(reg); | |
627eb5a3 DV |
3018 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
3019 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
3020 | temp &= ~FDI_LINK_TRAIN_NONE; |
3021 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3022 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3023 | /* SNB-B */ | |
3024 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3025 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3026 | |
d74cf324 DV |
3027 | I915_WRITE(FDI_RX_MISC(pipe), |
3028 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3029 | ||
5eddb70b CW |
3030 | reg = FDI_RX_CTL(pipe); |
3031 | temp = I915_READ(reg); | |
8db9d77b ZW |
3032 | if (HAS_PCH_CPT(dev)) { |
3033 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3034 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3035 | } else { | |
3036 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3037 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3038 | } | |
5eddb70b CW |
3039 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3040 | ||
3041 | POSTING_READ(reg); | |
8db9d77b ZW |
3042 | udelay(150); |
3043 | ||
0206e353 | 3044 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3045 | reg = FDI_TX_CTL(pipe); |
3046 | temp = I915_READ(reg); | |
8db9d77b ZW |
3047 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3048 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3049 | I915_WRITE(reg, temp); |
3050 | ||
3051 | POSTING_READ(reg); | |
8db9d77b ZW |
3052 | udelay(500); |
3053 | ||
fa37d39e SP |
3054 | for (retry = 0; retry < 5; retry++) { |
3055 | reg = FDI_RX_IIR(pipe); | |
3056 | temp = I915_READ(reg); | |
3057 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3058 | if (temp & FDI_RX_BIT_LOCK) { | |
3059 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3060 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3061 | break; | |
3062 | } | |
3063 | udelay(50); | |
8db9d77b | 3064 | } |
fa37d39e SP |
3065 | if (retry < 5) |
3066 | break; | |
8db9d77b ZW |
3067 | } |
3068 | if (i == 4) | |
5eddb70b | 3069 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3070 | |
3071 | /* Train 2 */ | |
5eddb70b CW |
3072 | reg = FDI_TX_CTL(pipe); |
3073 | temp = I915_READ(reg); | |
8db9d77b ZW |
3074 | temp &= ~FDI_LINK_TRAIN_NONE; |
3075 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3076 | if (IS_GEN6(dev)) { | |
3077 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3078 | /* SNB-B */ | |
3079 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3080 | } | |
5eddb70b | 3081 | I915_WRITE(reg, temp); |
8db9d77b | 3082 | |
5eddb70b CW |
3083 | reg = FDI_RX_CTL(pipe); |
3084 | temp = I915_READ(reg); | |
8db9d77b ZW |
3085 | if (HAS_PCH_CPT(dev)) { |
3086 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3087 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3088 | } else { | |
3089 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3090 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3091 | } | |
5eddb70b CW |
3092 | I915_WRITE(reg, temp); |
3093 | ||
3094 | POSTING_READ(reg); | |
8db9d77b ZW |
3095 | udelay(150); |
3096 | ||
0206e353 | 3097 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3098 | reg = FDI_TX_CTL(pipe); |
3099 | temp = I915_READ(reg); | |
8db9d77b ZW |
3100 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3101 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3102 | I915_WRITE(reg, temp); |
3103 | ||
3104 | POSTING_READ(reg); | |
8db9d77b ZW |
3105 | udelay(500); |
3106 | ||
fa37d39e SP |
3107 | for (retry = 0; retry < 5; retry++) { |
3108 | reg = FDI_RX_IIR(pipe); | |
3109 | temp = I915_READ(reg); | |
3110 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3111 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3112 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3113 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3114 | break; | |
3115 | } | |
3116 | udelay(50); | |
8db9d77b | 3117 | } |
fa37d39e SP |
3118 | if (retry < 5) |
3119 | break; | |
8db9d77b ZW |
3120 | } |
3121 | if (i == 4) | |
5eddb70b | 3122 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3123 | |
3124 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3125 | } | |
3126 | ||
357555c0 JB |
3127 | /* Manual link training for Ivy Bridge A0 parts */ |
3128 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3129 | { | |
3130 | struct drm_device *dev = crtc->dev; | |
3131 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3132 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3133 | int pipe = intel_crtc->pipe; | |
139ccd3f | 3134 | u32 reg, temp, i, j; |
357555c0 JB |
3135 | |
3136 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3137 | for train result */ | |
3138 | reg = FDI_RX_IMR(pipe); | |
3139 | temp = I915_READ(reg); | |
3140 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3141 | temp &= ~FDI_RX_BIT_LOCK; | |
3142 | I915_WRITE(reg, temp); | |
3143 | ||
3144 | POSTING_READ(reg); | |
3145 | udelay(150); | |
3146 | ||
01a415fd DV |
3147 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3148 | I915_READ(FDI_RX_IIR(pipe))); | |
3149 | ||
139ccd3f JB |
3150 | /* Try each vswing and preemphasis setting twice before moving on */ |
3151 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3152 | /* disable first in case we need to retry */ | |
3153 | reg = FDI_TX_CTL(pipe); | |
3154 | temp = I915_READ(reg); | |
3155 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3156 | temp &= ~FDI_TX_ENABLE; | |
3157 | I915_WRITE(reg, temp); | |
357555c0 | 3158 | |
139ccd3f JB |
3159 | reg = FDI_RX_CTL(pipe); |
3160 | temp = I915_READ(reg); | |
3161 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3162 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3163 | temp &= ~FDI_RX_ENABLE; | |
3164 | I915_WRITE(reg, temp); | |
357555c0 | 3165 | |
139ccd3f | 3166 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3167 | reg = FDI_TX_CTL(pipe); |
3168 | temp = I915_READ(reg); | |
139ccd3f JB |
3169 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
3170 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
3171 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; | |
357555c0 | 3172 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3173 | temp |= snb_b_fdi_train_param[j/2]; |
3174 | temp |= FDI_COMPOSITE_SYNC; | |
3175 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3176 | |
139ccd3f JB |
3177 | I915_WRITE(FDI_RX_MISC(pipe), |
3178 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3179 | |
139ccd3f | 3180 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3181 | temp = I915_READ(reg); |
139ccd3f JB |
3182 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3183 | temp |= FDI_COMPOSITE_SYNC; | |
3184 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3185 | |
139ccd3f JB |
3186 | POSTING_READ(reg); |
3187 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3188 | |
139ccd3f JB |
3189 | for (i = 0; i < 4; i++) { |
3190 | reg = FDI_RX_IIR(pipe); | |
3191 | temp = I915_READ(reg); | |
3192 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3193 | |
139ccd3f JB |
3194 | if (temp & FDI_RX_BIT_LOCK || |
3195 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3196 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3197 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3198 | i); | |
3199 | break; | |
3200 | } | |
3201 | udelay(1); /* should be 0.5us */ | |
3202 | } | |
3203 | if (i == 4) { | |
3204 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3205 | continue; | |
3206 | } | |
357555c0 | 3207 | |
139ccd3f | 3208 | /* Train 2 */ |
357555c0 JB |
3209 | reg = FDI_TX_CTL(pipe); |
3210 | temp = I915_READ(reg); | |
139ccd3f JB |
3211 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3212 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3213 | I915_WRITE(reg, temp); | |
3214 | ||
3215 | reg = FDI_RX_CTL(pipe); | |
3216 | temp = I915_READ(reg); | |
3217 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3218 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3219 | I915_WRITE(reg, temp); |
3220 | ||
3221 | POSTING_READ(reg); | |
139ccd3f | 3222 | udelay(2); /* should be 1.5us */ |
357555c0 | 3223 | |
139ccd3f JB |
3224 | for (i = 0; i < 4; i++) { |
3225 | reg = FDI_RX_IIR(pipe); | |
3226 | temp = I915_READ(reg); | |
3227 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3228 | |
139ccd3f JB |
3229 | if (temp & FDI_RX_SYMBOL_LOCK || |
3230 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3231 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3232 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3233 | i); | |
3234 | goto train_done; | |
3235 | } | |
3236 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3237 | } |
139ccd3f JB |
3238 | if (i == 4) |
3239 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3240 | } |
357555c0 | 3241 | |
139ccd3f | 3242 | train_done: |
357555c0 JB |
3243 | DRM_DEBUG_KMS("FDI train done.\n"); |
3244 | } | |
3245 | ||
88cefb6c | 3246 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3247 | { |
88cefb6c | 3248 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3249 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3250 | int pipe = intel_crtc->pipe; |
5eddb70b | 3251 | u32 reg, temp; |
79e53945 | 3252 | |
c64e311e | 3253 | |
c98e9dcf | 3254 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3255 | reg = FDI_RX_CTL(pipe); |
3256 | temp = I915_READ(reg); | |
627eb5a3 DV |
3257 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
3258 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
dfd07d72 | 3259 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3260 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3261 | ||
3262 | POSTING_READ(reg); | |
c98e9dcf JB |
3263 | udelay(200); |
3264 | ||
3265 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3266 | temp = I915_READ(reg); |
3267 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3268 | ||
3269 | POSTING_READ(reg); | |
c98e9dcf JB |
3270 | udelay(200); |
3271 | ||
20749730 PZ |
3272 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3273 | reg = FDI_TX_CTL(pipe); | |
3274 | temp = I915_READ(reg); | |
3275 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3276 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3277 | |
20749730 PZ |
3278 | POSTING_READ(reg); |
3279 | udelay(100); | |
6be4a607 | 3280 | } |
0e23b99d JB |
3281 | } |
3282 | ||
88cefb6c DV |
3283 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3284 | { | |
3285 | struct drm_device *dev = intel_crtc->base.dev; | |
3286 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3287 | int pipe = intel_crtc->pipe; | |
3288 | u32 reg, temp; | |
3289 | ||
3290 | /* Switch from PCDclk to Rawclk */ | |
3291 | reg = FDI_RX_CTL(pipe); | |
3292 | temp = I915_READ(reg); | |
3293 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3294 | ||
3295 | /* Disable CPU FDI TX PLL */ | |
3296 | reg = FDI_TX_CTL(pipe); | |
3297 | temp = I915_READ(reg); | |
3298 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3299 | ||
3300 | POSTING_READ(reg); | |
3301 | udelay(100); | |
3302 | ||
3303 | reg = FDI_RX_CTL(pipe); | |
3304 | temp = I915_READ(reg); | |
3305 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3306 | ||
3307 | /* Wait for the clocks to turn off. */ | |
3308 | POSTING_READ(reg); | |
3309 | udelay(100); | |
3310 | } | |
3311 | ||
0fc932b8 JB |
3312 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3313 | { | |
3314 | struct drm_device *dev = crtc->dev; | |
3315 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3316 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3317 | int pipe = intel_crtc->pipe; | |
3318 | u32 reg, temp; | |
3319 | ||
3320 | /* disable CPU FDI tx and PCH FDI rx */ | |
3321 | reg = FDI_TX_CTL(pipe); | |
3322 | temp = I915_READ(reg); | |
3323 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3324 | POSTING_READ(reg); | |
3325 | ||
3326 | reg = FDI_RX_CTL(pipe); | |
3327 | temp = I915_READ(reg); | |
3328 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3329 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3330 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3331 | ||
3332 | POSTING_READ(reg); | |
3333 | udelay(100); | |
3334 | ||
3335 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3336 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3337 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3338 | |
3339 | /* still set train pattern 1 */ | |
3340 | reg = FDI_TX_CTL(pipe); | |
3341 | temp = I915_READ(reg); | |
3342 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3343 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3344 | I915_WRITE(reg, temp); | |
3345 | ||
3346 | reg = FDI_RX_CTL(pipe); | |
3347 | temp = I915_READ(reg); | |
3348 | if (HAS_PCH_CPT(dev)) { | |
3349 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3350 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3351 | } else { | |
3352 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3353 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3354 | } | |
3355 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3356 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3357 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3358 | I915_WRITE(reg, temp); |
3359 | ||
3360 | POSTING_READ(reg); | |
3361 | udelay(100); | |
3362 | } | |
3363 | ||
5dce5b93 CW |
3364 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3365 | { | |
3366 | struct intel_crtc *crtc; | |
3367 | ||
3368 | /* Note that we don't need to be called with mode_config.lock here | |
3369 | * as our list of CRTC objects is static for the lifetime of the | |
3370 | * device and so cannot disappear as we iterate. Similarly, we can | |
3371 | * happily treat the predicates as racy, atomic checks as userspace | |
3372 | * cannot claim and pin a new fb without at least acquring the | |
3373 | * struct_mutex and so serialising with us. | |
3374 | */ | |
d3fcc808 | 3375 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3376 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3377 | continue; | |
3378 | ||
3379 | if (crtc->unpin_work) | |
3380 | intel_wait_for_vblank(dev, crtc->pipe); | |
3381 | ||
3382 | return true; | |
3383 | } | |
3384 | ||
3385 | return false; | |
3386 | } | |
3387 | ||
46a55d30 | 3388 | void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3389 | { |
0f91128d | 3390 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3391 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 | 3392 | |
2c10d571 | 3393 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
eed6d67d DV |
3394 | WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue, |
3395 | !intel_crtc_has_pending_flip(crtc), | |
3396 | 60*HZ) == 0); | |
5bb61643 | 3397 | |
975d568a CW |
3398 | if (crtc->primary->fb) { |
3399 | mutex_lock(&dev->struct_mutex); | |
3400 | intel_finish_fb(crtc->primary->fb); | |
3401 | mutex_unlock(&dev->struct_mutex); | |
3402 | } | |
e6c3a2a6 CW |
3403 | } |
3404 | ||
e615efe4 ED |
3405 | /* Program iCLKIP clock to the desired frequency */ |
3406 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3407 | { | |
3408 | struct drm_device *dev = crtc->dev; | |
3409 | struct drm_i915_private *dev_priv = dev->dev_private; | |
241bfc38 | 3410 | int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; |
e615efe4 ED |
3411 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3412 | u32 temp; | |
3413 | ||
09153000 DV |
3414 | mutex_lock(&dev_priv->dpio_lock); |
3415 | ||
e615efe4 ED |
3416 | /* It is necessary to ungate the pixclk gate prior to programming |
3417 | * the divisors, and gate it back when it is done. | |
3418 | */ | |
3419 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3420 | ||
3421 | /* Disable SSCCTL */ | |
3422 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
3423 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
3424 | SBI_SSCCTL_DISABLE, | |
3425 | SBI_ICLK); | |
e615efe4 ED |
3426 | |
3427 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3428 | if (clock == 20000) { |
e615efe4 ED |
3429 | auxdiv = 1; |
3430 | divsel = 0x41; | |
3431 | phaseinc = 0x20; | |
3432 | } else { | |
3433 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3434 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3435 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3436 | * convert the virtual clock precision to KHz here for higher |
3437 | * precision. | |
3438 | */ | |
3439 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3440 | u32 iclk_pi_range = 64; | |
3441 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3442 | ||
12d7ceed | 3443 | desired_divisor = (iclk_virtual_root_freq / clock); |
e615efe4 ED |
3444 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3445 | pi_value = desired_divisor % iclk_pi_range; | |
3446 | ||
3447 | auxdiv = 0; | |
3448 | divsel = msb_divisor_value - 2; | |
3449 | phaseinc = pi_value; | |
3450 | } | |
3451 | ||
3452 | /* This should not happen with any sane values */ | |
3453 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3454 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3455 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3456 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3457 | ||
3458 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3459 | clock, |
e615efe4 ED |
3460 | auxdiv, |
3461 | divsel, | |
3462 | phasedir, | |
3463 | phaseinc); | |
3464 | ||
3465 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 3466 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3467 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3468 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3469 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3470 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3471 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3472 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3473 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3474 | |
3475 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3476 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3477 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3478 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3479 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3480 | |
3481 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3482 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3483 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3484 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
3485 | |
3486 | /* Wait for initialization time */ | |
3487 | udelay(24); | |
3488 | ||
3489 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 DV |
3490 | |
3491 | mutex_unlock(&dev_priv->dpio_lock); | |
e615efe4 ED |
3492 | } |
3493 | ||
275f01b2 DV |
3494 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
3495 | enum pipe pch_transcoder) | |
3496 | { | |
3497 | struct drm_device *dev = crtc->base.dev; | |
3498 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3499 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; | |
3500 | ||
3501 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
3502 | I915_READ(HTOTAL(cpu_transcoder))); | |
3503 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
3504 | I915_READ(HBLANK(cpu_transcoder))); | |
3505 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
3506 | I915_READ(HSYNC(cpu_transcoder))); | |
3507 | ||
3508 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
3509 | I915_READ(VTOTAL(cpu_transcoder))); | |
3510 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
3511 | I915_READ(VBLANK(cpu_transcoder))); | |
3512 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
3513 | I915_READ(VSYNC(cpu_transcoder))); | |
3514 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
3515 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
3516 | } | |
3517 | ||
1fbc0d78 DV |
3518 | static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) |
3519 | { | |
3520 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3521 | uint32_t temp; | |
3522 | ||
3523 | temp = I915_READ(SOUTH_CHICKEN1); | |
3524 | if (temp & FDI_BC_BIFURCATION_SELECT) | |
3525 | return; | |
3526 | ||
3527 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
3528 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
3529 | ||
3530 | temp |= FDI_BC_BIFURCATION_SELECT; | |
3531 | DRM_DEBUG_KMS("enabling fdi C rx\n"); | |
3532 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
3533 | POSTING_READ(SOUTH_CHICKEN1); | |
3534 | } | |
3535 | ||
3536 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
3537 | { | |
3538 | struct drm_device *dev = intel_crtc->base.dev; | |
3539 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3540 | ||
3541 | switch (intel_crtc->pipe) { | |
3542 | case PIPE_A: | |
3543 | break; | |
3544 | case PIPE_B: | |
3545 | if (intel_crtc->config.fdi_lanes > 2) | |
3546 | WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); | |
3547 | else | |
3548 | cpt_enable_fdi_bc_bifurcation(dev); | |
3549 | ||
3550 | break; | |
3551 | case PIPE_C: | |
3552 | cpt_enable_fdi_bc_bifurcation(dev); | |
3553 | ||
3554 | break; | |
3555 | default: | |
3556 | BUG(); | |
3557 | } | |
3558 | } | |
3559 | ||
f67a559d JB |
3560 | /* |
3561 | * Enable PCH resources required for PCH ports: | |
3562 | * - PCH PLLs | |
3563 | * - FDI training & RX/TX | |
3564 | * - update transcoder timings | |
3565 | * - DP transcoding bits | |
3566 | * - transcoder | |
3567 | */ | |
3568 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
3569 | { |
3570 | struct drm_device *dev = crtc->dev; | |
3571 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3572 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3573 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 3574 | u32 reg, temp; |
2c07245f | 3575 | |
ab9412ba | 3576 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 3577 | |
1fbc0d78 DV |
3578 | if (IS_IVYBRIDGE(dev)) |
3579 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
3580 | ||
cd986abb DV |
3581 | /* Write the TU size bits before fdi link training, so that error |
3582 | * detection works. */ | |
3583 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
3584 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
3585 | ||
c98e9dcf | 3586 | /* For PCH output, training FDI link */ |
674cf967 | 3587 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 3588 | |
3ad8a208 DV |
3589 | /* We need to program the right clock selection before writing the pixel |
3590 | * mutliplier into the DPLL. */ | |
303b81e0 | 3591 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 3592 | u32 sel; |
4b645f14 | 3593 | |
c98e9dcf | 3594 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
3595 | temp |= TRANS_DPLL_ENABLE(pipe); |
3596 | sel = TRANS_DPLLB_SEL(pipe); | |
a43f6e0f | 3597 | if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
3598 | temp |= sel; |
3599 | else | |
3600 | temp &= ~sel; | |
c98e9dcf | 3601 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 3602 | } |
5eddb70b | 3603 | |
3ad8a208 DV |
3604 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
3605 | * transcoder, and we actually should do this to not upset any PCH | |
3606 | * transcoder that already use the clock when we share it. | |
3607 | * | |
3608 | * Note that enable_shared_dpll tries to do the right thing, but | |
3609 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
3610 | * the right LVDS enable sequence. */ | |
85b3894f | 3611 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 3612 | |
d9b6cb56 JB |
3613 | /* set transcoder timing, panel must allow it */ |
3614 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 3615 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 3616 | |
303b81e0 | 3617 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 3618 | |
c98e9dcf JB |
3619 | /* For PCH DP, enable TRANS_DP_CTL */ |
3620 | if (HAS_PCH_CPT(dev) && | |
417e822d KP |
3621 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
3622 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
dfd07d72 | 3623 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
3624 | reg = TRANS_DP_CTL(pipe); |
3625 | temp = I915_READ(reg); | |
3626 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
3627 | TRANS_DP_SYNC_MASK | |
3628 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
3629 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3630 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 3631 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
3632 | |
3633 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 3634 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 3635 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 3636 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
3637 | |
3638 | switch (intel_trans_dp_port_sel(crtc)) { | |
3639 | case PCH_DP_B: | |
5eddb70b | 3640 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
3641 | break; |
3642 | case PCH_DP_C: | |
5eddb70b | 3643 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
3644 | break; |
3645 | case PCH_DP_D: | |
5eddb70b | 3646 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
3647 | break; |
3648 | default: | |
e95d41e1 | 3649 | BUG(); |
32f9d658 | 3650 | } |
2c07245f | 3651 | |
5eddb70b | 3652 | I915_WRITE(reg, temp); |
6be4a607 | 3653 | } |
b52eb4dc | 3654 | |
b8a4f404 | 3655 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
3656 | } |
3657 | ||
1507e5bd PZ |
3658 | static void lpt_pch_enable(struct drm_crtc *crtc) |
3659 | { | |
3660 | struct drm_device *dev = crtc->dev; | |
3661 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3662 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3b117c8f | 3663 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
1507e5bd | 3664 | |
ab9412ba | 3665 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 3666 | |
8c52b5e8 | 3667 | lpt_program_iclkip(crtc); |
1507e5bd | 3668 | |
0540e488 | 3669 | /* Set transcoder timing. */ |
275f01b2 | 3670 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 3671 | |
937bb610 | 3672 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
3673 | } |
3674 | ||
716c2e55 | 3675 | void intel_put_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3676 | { |
e2b78267 | 3677 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
ee7b9f93 JB |
3678 | |
3679 | if (pll == NULL) | |
3680 | return; | |
3681 | ||
3682 | if (pll->refcount == 0) { | |
46edb027 | 3683 | WARN(1, "bad %s refcount\n", pll->name); |
ee7b9f93 JB |
3684 | return; |
3685 | } | |
3686 | ||
f4a091c7 DV |
3687 | if (--pll->refcount == 0) { |
3688 | WARN_ON(pll->on); | |
3689 | WARN_ON(pll->active); | |
3690 | } | |
3691 | ||
a43f6e0f | 3692 | crtc->config.shared_dpll = DPLL_ID_PRIVATE; |
ee7b9f93 JB |
3693 | } |
3694 | ||
716c2e55 | 3695 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3696 | { |
e2b78267 DV |
3697 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
3698 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
3699 | enum intel_dpll_id i; | |
ee7b9f93 | 3700 | |
ee7b9f93 | 3701 | if (pll) { |
46edb027 DV |
3702 | DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n", |
3703 | crtc->base.base.id, pll->name); | |
e2b78267 | 3704 | intel_put_shared_dpll(crtc); |
ee7b9f93 JB |
3705 | } |
3706 | ||
98b6bd99 DV |
3707 | if (HAS_PCH_IBX(dev_priv->dev)) { |
3708 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 3709 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 3710 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 3711 | |
46edb027 DV |
3712 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
3713 | crtc->base.base.id, pll->name); | |
98b6bd99 | 3714 | |
f2a69f44 DV |
3715 | WARN_ON(pll->refcount); |
3716 | ||
98b6bd99 DV |
3717 | goto found; |
3718 | } | |
3719 | ||
e72f9fbf DV |
3720 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3721 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 JB |
3722 | |
3723 | /* Only want to check enabled timings first */ | |
3724 | if (pll->refcount == 0) | |
3725 | continue; | |
3726 | ||
b89a1d39 DV |
3727 | if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state, |
3728 | sizeof(pll->hw_state)) == 0) { | |
46edb027 | 3729 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n", |
e2b78267 | 3730 | crtc->base.base.id, |
46edb027 | 3731 | pll->name, pll->refcount, pll->active); |
ee7b9f93 JB |
3732 | |
3733 | goto found; | |
3734 | } | |
3735 | } | |
3736 | ||
3737 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
3738 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3739 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 | 3740 | if (pll->refcount == 0) { |
46edb027 DV |
3741 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
3742 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
3743 | goto found; |
3744 | } | |
3745 | } | |
3746 | ||
3747 | return NULL; | |
3748 | ||
3749 | found: | |
f2a69f44 DV |
3750 | if (pll->refcount == 0) |
3751 | pll->hw_state = crtc->config.dpll_hw_state; | |
3752 | ||
a43f6e0f | 3753 | crtc->config.shared_dpll = i; |
46edb027 DV |
3754 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
3755 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 3756 | |
cdbd2316 | 3757 | pll->refcount++; |
e04c7350 | 3758 | |
ee7b9f93 JB |
3759 | return pll; |
3760 | } | |
3761 | ||
a1520318 | 3762 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
3763 | { |
3764 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 3765 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
3766 | u32 temp; |
3767 | ||
3768 | temp = I915_READ(dslreg); | |
3769 | udelay(500); | |
3770 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 3771 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 3772 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
3773 | } |
3774 | } | |
3775 | ||
b074cec8 JB |
3776 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
3777 | { | |
3778 | struct drm_device *dev = crtc->base.dev; | |
3779 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3780 | int pipe = crtc->pipe; | |
3781 | ||
fd4daa9c | 3782 | if (crtc->config.pch_pfit.enabled) { |
b074cec8 JB |
3783 | /* Force use of hard-coded filter coefficients |
3784 | * as some pre-programmed values are broken, | |
3785 | * e.g. x201. | |
3786 | */ | |
3787 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
3788 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
3789 | PF_PIPE_SEL_IVB(pipe)); | |
3790 | else | |
3791 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
3792 | I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos); | |
3793 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size); | |
d4270e57 JB |
3794 | } |
3795 | } | |
3796 | ||
bb53d4ae VS |
3797 | static void intel_enable_planes(struct drm_crtc *crtc) |
3798 | { | |
3799 | struct drm_device *dev = crtc->dev; | |
3800 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 3801 | struct drm_plane *plane; |
bb53d4ae VS |
3802 | struct intel_plane *intel_plane; |
3803 | ||
af2b653b MR |
3804 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
3805 | intel_plane = to_intel_plane(plane); | |
bb53d4ae VS |
3806 | if (intel_plane->pipe == pipe) |
3807 | intel_plane_restore(&intel_plane->base); | |
af2b653b | 3808 | } |
bb53d4ae VS |
3809 | } |
3810 | ||
3811 | static void intel_disable_planes(struct drm_crtc *crtc) | |
3812 | { | |
3813 | struct drm_device *dev = crtc->dev; | |
3814 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 3815 | struct drm_plane *plane; |
bb53d4ae VS |
3816 | struct intel_plane *intel_plane; |
3817 | ||
af2b653b MR |
3818 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
3819 | intel_plane = to_intel_plane(plane); | |
bb53d4ae VS |
3820 | if (intel_plane->pipe == pipe) |
3821 | intel_plane_disable(&intel_plane->base); | |
af2b653b | 3822 | } |
bb53d4ae VS |
3823 | } |
3824 | ||
20bc8673 | 3825 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 3826 | { |
cea165c3 VS |
3827 | struct drm_device *dev = crtc->base.dev; |
3828 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 PZ |
3829 | |
3830 | if (!crtc->config.ips_enabled) | |
3831 | return; | |
3832 | ||
cea165c3 VS |
3833 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
3834 | intel_wait_for_vblank(dev, crtc->pipe); | |
3835 | ||
d77e4531 | 3836 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 3837 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
3838 | mutex_lock(&dev_priv->rps.hw_lock); |
3839 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
3840 | mutex_unlock(&dev_priv->rps.hw_lock); | |
3841 | /* Quoting Art Runyan: "its not safe to expect any particular | |
3842 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
3843 | * mailbox." Moreover, the mailbox may return a bogus state, |
3844 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
3845 | */ |
3846 | } else { | |
3847 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
3848 | /* The bit only becomes 1 in the next vblank, so this wait here | |
3849 | * is essentially intel_wait_for_vblank. If we don't have this | |
3850 | * and don't wait for vblanks until the end of crtc_enable, then | |
3851 | * the HW state readout code will complain that the expected | |
3852 | * IPS_CTL value is not the one we read. */ | |
3853 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
3854 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
3855 | } | |
d77e4531 PZ |
3856 | } |
3857 | ||
20bc8673 | 3858 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
3859 | { |
3860 | struct drm_device *dev = crtc->base.dev; | |
3861 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3862 | ||
3863 | if (!crtc->config.ips_enabled) | |
3864 | return; | |
3865 | ||
3866 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 3867 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
3868 | mutex_lock(&dev_priv->rps.hw_lock); |
3869 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
3870 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
3871 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
3872 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
3873 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 3874 | } else { |
2a114cc1 | 3875 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
3876 | POSTING_READ(IPS_CTL); |
3877 | } | |
d77e4531 PZ |
3878 | |
3879 | /* We need to wait for a vblank before we can disable the plane. */ | |
3880 | intel_wait_for_vblank(dev, crtc->pipe); | |
3881 | } | |
3882 | ||
3883 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
3884 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
3885 | { | |
3886 | struct drm_device *dev = crtc->dev; | |
3887 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3888 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3889 | enum pipe pipe = intel_crtc->pipe; | |
3890 | int palreg = PALETTE(pipe); | |
3891 | int i; | |
3892 | bool reenable_ips = false; | |
3893 | ||
3894 | /* The clocks have to be on to load the palette. */ | |
3895 | if (!crtc->enabled || !intel_crtc->active) | |
3896 | return; | |
3897 | ||
3898 | if (!HAS_PCH_SPLIT(dev_priv->dev)) { | |
3899 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) | |
3900 | assert_dsi_pll_enabled(dev_priv); | |
3901 | else | |
3902 | assert_pll_enabled(dev_priv, pipe); | |
3903 | } | |
3904 | ||
3905 | /* use legacy palette for Ironlake */ | |
7a1db49a | 3906 | if (!HAS_GMCH_DISPLAY(dev)) |
d77e4531 PZ |
3907 | palreg = LGC_PALETTE(pipe); |
3908 | ||
3909 | /* Workaround : Do not read or write the pipe palette/gamma data while | |
3910 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
3911 | */ | |
41e6fc4c | 3912 | if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled && |
d77e4531 PZ |
3913 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
3914 | GAMMA_MODE_MODE_SPLIT)) { | |
3915 | hsw_disable_ips(intel_crtc); | |
3916 | reenable_ips = true; | |
3917 | } | |
3918 | ||
3919 | for (i = 0; i < 256; i++) { | |
3920 | I915_WRITE(palreg + 4 * i, | |
3921 | (intel_crtc->lut_r[i] << 16) | | |
3922 | (intel_crtc->lut_g[i] << 8) | | |
3923 | intel_crtc->lut_b[i]); | |
3924 | } | |
3925 | ||
3926 | if (reenable_ips) | |
3927 | hsw_enable_ips(intel_crtc); | |
3928 | } | |
3929 | ||
d3eedb1a VS |
3930 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
3931 | { | |
3932 | if (!enable && intel_crtc->overlay) { | |
3933 | struct drm_device *dev = intel_crtc->base.dev; | |
3934 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3935 | ||
3936 | mutex_lock(&dev->struct_mutex); | |
3937 | dev_priv->mm.interruptible = false; | |
3938 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
3939 | dev_priv->mm.interruptible = true; | |
3940 | mutex_unlock(&dev->struct_mutex); | |
3941 | } | |
3942 | ||
3943 | /* Let userspace switch the overlay on again. In most cases userspace | |
3944 | * has to recompute where to put it anyway. | |
3945 | */ | |
3946 | } | |
3947 | ||
d3eedb1a | 3948 | static void intel_crtc_enable_planes(struct drm_crtc *crtc) |
a5c4d7bc VS |
3949 | { |
3950 | struct drm_device *dev = crtc->dev; | |
a5c4d7bc VS |
3951 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3952 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 3953 | |
f98551ae VS |
3954 | drm_vblank_on(dev, pipe); |
3955 | ||
fdd508a6 | 3956 | intel_enable_primary_hw_plane(crtc->primary, crtc); |
a5c4d7bc VS |
3957 | intel_enable_planes(crtc); |
3958 | intel_crtc_update_cursor(crtc, true); | |
d3eedb1a | 3959 | intel_crtc_dpms_overlay(intel_crtc, true); |
a5c4d7bc VS |
3960 | |
3961 | hsw_enable_ips(intel_crtc); | |
3962 | ||
3963 | mutex_lock(&dev->struct_mutex); | |
3964 | intel_update_fbc(dev); | |
3965 | mutex_unlock(&dev->struct_mutex); | |
f99d7069 DV |
3966 | |
3967 | /* | |
3968 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
3969 | * to compute the mask of flip planes precisely. For the time being | |
3970 | * consider this a flip from a NULL plane. | |
3971 | */ | |
3972 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
3973 | } |
3974 | ||
d3eedb1a | 3975 | static void intel_crtc_disable_planes(struct drm_crtc *crtc) |
a5c4d7bc VS |
3976 | { |
3977 | struct drm_device *dev = crtc->dev; | |
3978 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3979 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3980 | int pipe = intel_crtc->pipe; | |
3981 | int plane = intel_crtc->plane; | |
3982 | ||
3983 | intel_crtc_wait_for_pending_flips(crtc); | |
a5c4d7bc VS |
3984 | |
3985 | if (dev_priv->fbc.plane == plane) | |
3986 | intel_disable_fbc(dev); | |
3987 | ||
3988 | hsw_disable_ips(intel_crtc); | |
3989 | ||
d3eedb1a | 3990 | intel_crtc_dpms_overlay(intel_crtc, false); |
a5c4d7bc VS |
3991 | intel_crtc_update_cursor(crtc, false); |
3992 | intel_disable_planes(crtc); | |
fdd508a6 | 3993 | intel_disable_primary_hw_plane(crtc->primary, crtc); |
f98551ae | 3994 | |
f99d7069 DV |
3995 | /* |
3996 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
3997 | * to compute the mask of flip planes precisely. For the time being | |
3998 | * consider this a flip to a NULL plane. | |
3999 | */ | |
4000 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
4001 | ||
f98551ae | 4002 | drm_vblank_off(dev, pipe); |
a5c4d7bc VS |
4003 | } |
4004 | ||
f67a559d JB |
4005 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4006 | { | |
4007 | struct drm_device *dev = crtc->dev; | |
4008 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4009 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4010 | struct intel_encoder *encoder; |
f67a559d | 4011 | int pipe = intel_crtc->pipe; |
f67a559d | 4012 | |
08a48469 DV |
4013 | WARN_ON(!crtc->enabled); |
4014 | ||
f67a559d JB |
4015 | if (intel_crtc->active) |
4016 | return; | |
4017 | ||
b14b1055 DV |
4018 | if (intel_crtc->config.has_pch_encoder) |
4019 | intel_prepare_shared_dpll(intel_crtc); | |
4020 | ||
29407aab DV |
4021 | if (intel_crtc->config.has_dp_encoder) |
4022 | intel_dp_set_m_n(intel_crtc); | |
4023 | ||
4024 | intel_set_pipe_timings(intel_crtc); | |
4025 | ||
4026 | if (intel_crtc->config.has_pch_encoder) { | |
4027 | intel_cpu_transcoder_set_m_n(intel_crtc, | |
f769cd24 | 4028 | &intel_crtc->config.fdi_m_n, NULL); |
29407aab DV |
4029 | } |
4030 | ||
4031 | ironlake_set_pipeconf(crtc); | |
4032 | ||
f67a559d | 4033 | intel_crtc->active = true; |
8664281b PZ |
4034 | |
4035 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
4036 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); | |
4037 | ||
f6736a1a | 4038 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4039 | if (encoder->pre_enable) |
4040 | encoder->pre_enable(encoder); | |
f67a559d | 4041 | |
5bfe2ac0 | 4042 | if (intel_crtc->config.has_pch_encoder) { |
fff367c7 DV |
4043 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4044 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4045 | * enabling. */ | |
88cefb6c | 4046 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4047 | } else { |
4048 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4049 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4050 | } | |
f67a559d | 4051 | |
b074cec8 | 4052 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4053 | |
9c54c0dd JB |
4054 | /* |
4055 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4056 | * clocks enabled | |
4057 | */ | |
4058 | intel_crtc_load_lut(crtc); | |
4059 | ||
f37fcc2a | 4060 | intel_update_watermarks(crtc); |
e1fdc473 | 4061 | intel_enable_pipe(intel_crtc); |
f67a559d | 4062 | |
5bfe2ac0 | 4063 | if (intel_crtc->config.has_pch_encoder) |
f67a559d | 4064 | ironlake_pch_enable(crtc); |
c98e9dcf | 4065 | |
fa5c73b1 DV |
4066 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4067 | encoder->enable(encoder); | |
61b77ddd DV |
4068 | |
4069 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4070 | cpt_verify_modeset(dev, intel_crtc->pipe); |
6ce94100 | 4071 | |
d3eedb1a | 4072 | intel_crtc_enable_planes(crtc); |
6be4a607 JB |
4073 | } |
4074 | ||
42db64ef PZ |
4075 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4076 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4077 | { | |
f5adf94e | 4078 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4079 | } |
4080 | ||
e4916946 PZ |
4081 | /* |
4082 | * This implements the workaround described in the "notes" section of the mode | |
4083 | * set sequence documentation. When going from no pipes or single pipe to | |
4084 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
4085 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
4086 | */ | |
4087 | static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) | |
4088 | { | |
4089 | struct drm_device *dev = crtc->base.dev; | |
4090 | struct intel_crtc *crtc_it, *other_active_crtc = NULL; | |
4091 | ||
4092 | /* We want to get the other_active_crtc only if there's only 1 other | |
4093 | * active crtc. */ | |
d3fcc808 | 4094 | for_each_intel_crtc(dev, crtc_it) { |
e4916946 PZ |
4095 | if (!crtc_it->active || crtc_it == crtc) |
4096 | continue; | |
4097 | ||
4098 | if (other_active_crtc) | |
4099 | return; | |
4100 | ||
4101 | other_active_crtc = crtc_it; | |
4102 | } | |
4103 | if (!other_active_crtc) | |
4104 | return; | |
4105 | ||
4106 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4107 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4108 | } | |
4109 | ||
4f771f10 PZ |
4110 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4111 | { | |
4112 | struct drm_device *dev = crtc->dev; | |
4113 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4114 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4115 | struct intel_encoder *encoder; | |
4116 | int pipe = intel_crtc->pipe; | |
4f771f10 PZ |
4117 | |
4118 | WARN_ON(!crtc->enabled); | |
4119 | ||
4120 | if (intel_crtc->active) | |
4121 | return; | |
4122 | ||
df8ad70c DV |
4123 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
4124 | intel_enable_shared_dpll(intel_crtc); | |
4125 | ||
229fca97 DV |
4126 | if (intel_crtc->config.has_dp_encoder) |
4127 | intel_dp_set_m_n(intel_crtc); | |
4128 | ||
4129 | intel_set_pipe_timings(intel_crtc); | |
4130 | ||
4131 | if (intel_crtc->config.has_pch_encoder) { | |
4132 | intel_cpu_transcoder_set_m_n(intel_crtc, | |
f769cd24 | 4133 | &intel_crtc->config.fdi_m_n, NULL); |
229fca97 DV |
4134 | } |
4135 | ||
4136 | haswell_set_pipeconf(crtc); | |
4137 | ||
4138 | intel_set_pipe_csc(crtc); | |
4139 | ||
4f771f10 | 4140 | intel_crtc->active = true; |
8664281b PZ |
4141 | |
4142 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
4f771f10 PZ |
4143 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4144 | if (encoder->pre_enable) | |
4145 | encoder->pre_enable(encoder); | |
4146 | ||
4fe9467d ID |
4147 | if (intel_crtc->config.has_pch_encoder) { |
4148 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); | |
4149 | dev_priv->display.fdi_link_train(crtc); | |
4150 | } | |
4151 | ||
1f544388 | 4152 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 4153 | |
b074cec8 | 4154 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
4155 | |
4156 | /* | |
4157 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4158 | * clocks enabled | |
4159 | */ | |
4160 | intel_crtc_load_lut(crtc); | |
4161 | ||
1f544388 | 4162 | intel_ddi_set_pipe_settings(crtc); |
8228c251 | 4163 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 4164 | |
f37fcc2a | 4165 | intel_update_watermarks(crtc); |
e1fdc473 | 4166 | intel_enable_pipe(intel_crtc); |
42db64ef | 4167 | |
5bfe2ac0 | 4168 | if (intel_crtc->config.has_pch_encoder) |
1507e5bd | 4169 | lpt_pch_enable(crtc); |
4f771f10 | 4170 | |
0e32b39c DA |
4171 | if (intel_crtc->config.dp_encoder_is_mst) |
4172 | intel_ddi_set_vc_payload_alloc(crtc, true); | |
4173 | ||
8807e55b | 4174 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 4175 | encoder->enable(encoder); |
8807e55b JN |
4176 | intel_opregion_notify_encoder(encoder, true); |
4177 | } | |
4f771f10 | 4178 | |
e4916946 PZ |
4179 | /* If we change the relative order between pipe/planes enabling, we need |
4180 | * to change the workaround. */ | |
4181 | haswell_mode_set_planes_workaround(intel_crtc); | |
d3eedb1a | 4182 | intel_crtc_enable_planes(crtc); |
4f771f10 PZ |
4183 | } |
4184 | ||
3f8dce3a DV |
4185 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
4186 | { | |
4187 | struct drm_device *dev = crtc->base.dev; | |
4188 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4189 | int pipe = crtc->pipe; | |
4190 | ||
4191 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
4192 | * it's in use. The hw state code will make sure we get this right. */ | |
fd4daa9c | 4193 | if (crtc->config.pch_pfit.enabled) { |
3f8dce3a DV |
4194 | I915_WRITE(PF_CTL(pipe), 0); |
4195 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
4196 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
4197 | } | |
4198 | } | |
4199 | ||
6be4a607 JB |
4200 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
4201 | { | |
4202 | struct drm_device *dev = crtc->dev; | |
4203 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4204 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4205 | struct intel_encoder *encoder; |
6be4a607 | 4206 | int pipe = intel_crtc->pipe; |
5eddb70b | 4207 | u32 reg, temp; |
b52eb4dc | 4208 | |
f7abfe8b CW |
4209 | if (!intel_crtc->active) |
4210 | return; | |
4211 | ||
d3eedb1a | 4212 | intel_crtc_disable_planes(crtc); |
a5c4d7bc | 4213 | |
ea9d758d DV |
4214 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4215 | encoder->disable(encoder); | |
4216 | ||
d925c59a DV |
4217 | if (intel_crtc->config.has_pch_encoder) |
4218 | intel_set_pch_fifo_underrun_reporting(dev, pipe, false); | |
4219 | ||
575f7ab7 | 4220 | intel_disable_pipe(intel_crtc); |
32f9d658 | 4221 | |
0e32b39c DA |
4222 | if (intel_crtc->config.dp_encoder_is_mst) |
4223 | intel_ddi_set_vc_payload_alloc(crtc, false); | |
4224 | ||
3f8dce3a | 4225 | ironlake_pfit_disable(intel_crtc); |
2c07245f | 4226 | |
bf49ec8c DV |
4227 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4228 | if (encoder->post_disable) | |
4229 | encoder->post_disable(encoder); | |
2c07245f | 4230 | |
d925c59a DV |
4231 | if (intel_crtc->config.has_pch_encoder) { |
4232 | ironlake_fdi_disable(crtc); | |
913d8d11 | 4233 | |
d925c59a DV |
4234 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
4235 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); | |
6be4a607 | 4236 | |
d925c59a DV |
4237 | if (HAS_PCH_CPT(dev)) { |
4238 | /* disable TRANS_DP_CTL */ | |
4239 | reg = TRANS_DP_CTL(pipe); | |
4240 | temp = I915_READ(reg); | |
4241 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
4242 | TRANS_DP_PORT_SEL_MASK); | |
4243 | temp |= TRANS_DP_PORT_SEL_NONE; | |
4244 | I915_WRITE(reg, temp); | |
4245 | ||
4246 | /* disable DPLL_SEL */ | |
4247 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 4248 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 4249 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 4250 | } |
e3421a18 | 4251 | |
d925c59a | 4252 | /* disable PCH DPLL */ |
e72f9fbf | 4253 | intel_disable_shared_dpll(intel_crtc); |
8db9d77b | 4254 | |
d925c59a DV |
4255 | ironlake_fdi_pll_disable(intel_crtc); |
4256 | } | |
6b383a7f | 4257 | |
f7abfe8b | 4258 | intel_crtc->active = false; |
46ba614c | 4259 | intel_update_watermarks(crtc); |
d1ebd816 BW |
4260 | |
4261 | mutex_lock(&dev->struct_mutex); | |
6b383a7f | 4262 | intel_update_fbc(dev); |
d1ebd816 | 4263 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 4264 | } |
1b3c7a47 | 4265 | |
4f771f10 | 4266 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 4267 | { |
4f771f10 PZ |
4268 | struct drm_device *dev = crtc->dev; |
4269 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 4270 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 4271 | struct intel_encoder *encoder; |
3b117c8f | 4272 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee7b9f93 | 4273 | |
4f771f10 PZ |
4274 | if (!intel_crtc->active) |
4275 | return; | |
4276 | ||
d3eedb1a | 4277 | intel_crtc_disable_planes(crtc); |
dda9a66a | 4278 | |
8807e55b JN |
4279 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4280 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 4281 | encoder->disable(encoder); |
8807e55b | 4282 | } |
4f771f10 | 4283 | |
8664281b PZ |
4284 | if (intel_crtc->config.has_pch_encoder) |
4285 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); | |
575f7ab7 | 4286 | intel_disable_pipe(intel_crtc); |
4f771f10 | 4287 | |
ad80a810 | 4288 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 4289 | |
3f8dce3a | 4290 | ironlake_pfit_disable(intel_crtc); |
4f771f10 | 4291 | |
1f544388 | 4292 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 4293 | |
88adfff1 | 4294 | if (intel_crtc->config.has_pch_encoder) { |
ab4d966c | 4295 | lpt_disable_pch_transcoder(dev_priv); |
8664281b | 4296 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
1ad960f2 | 4297 | intel_ddi_fdi_disable(crtc); |
83616634 | 4298 | } |
4f771f10 | 4299 | |
97b040aa ID |
4300 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4301 | if (encoder->post_disable) | |
4302 | encoder->post_disable(encoder); | |
4303 | ||
4f771f10 | 4304 | intel_crtc->active = false; |
46ba614c | 4305 | intel_update_watermarks(crtc); |
4f771f10 PZ |
4306 | |
4307 | mutex_lock(&dev->struct_mutex); | |
4308 | intel_update_fbc(dev); | |
4309 | mutex_unlock(&dev->struct_mutex); | |
df8ad70c DV |
4310 | |
4311 | if (intel_crtc_to_shared_dpll(intel_crtc)) | |
4312 | intel_disable_shared_dpll(intel_crtc); | |
4f771f10 PZ |
4313 | } |
4314 | ||
ee7b9f93 JB |
4315 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
4316 | { | |
4317 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e72f9fbf | 4318 | intel_put_shared_dpll(intel_crtc); |
ee7b9f93 JB |
4319 | } |
4320 | ||
6441ab5f | 4321 | |
2dd24552 JB |
4322 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
4323 | { | |
4324 | struct drm_device *dev = crtc->base.dev; | |
4325 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4326 | struct intel_crtc_config *pipe_config = &crtc->config; | |
4327 | ||
328d8e82 | 4328 | if (!crtc->config.gmch_pfit.control) |
2dd24552 JB |
4329 | return; |
4330 | ||
2dd24552 | 4331 | /* |
c0b03411 DV |
4332 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
4333 | * according to register description and PRM. | |
2dd24552 | 4334 | */ |
c0b03411 DV |
4335 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
4336 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 4337 | |
b074cec8 JB |
4338 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
4339 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
4340 | |
4341 | /* Border color in case we don't scale up to the full screen. Black by | |
4342 | * default, change to something else for debugging. */ | |
4343 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
4344 | } |
4345 | ||
d05410f9 DA |
4346 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
4347 | { | |
4348 | switch (port) { | |
4349 | case PORT_A: | |
4350 | return POWER_DOMAIN_PORT_DDI_A_4_LANES; | |
4351 | case PORT_B: | |
4352 | return POWER_DOMAIN_PORT_DDI_B_4_LANES; | |
4353 | case PORT_C: | |
4354 | return POWER_DOMAIN_PORT_DDI_C_4_LANES; | |
4355 | case PORT_D: | |
4356 | return POWER_DOMAIN_PORT_DDI_D_4_LANES; | |
4357 | default: | |
4358 | WARN_ON_ONCE(1); | |
4359 | return POWER_DOMAIN_PORT_OTHER; | |
4360 | } | |
4361 | } | |
4362 | ||
77d22dca ID |
4363 | #define for_each_power_domain(domain, mask) \ |
4364 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
4365 | if ((1 << (domain)) & (mask)) | |
4366 | ||
319be8ae ID |
4367 | enum intel_display_power_domain |
4368 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
4369 | { | |
4370 | struct drm_device *dev = intel_encoder->base.dev; | |
4371 | struct intel_digital_port *intel_dig_port; | |
4372 | ||
4373 | switch (intel_encoder->type) { | |
4374 | case INTEL_OUTPUT_UNKNOWN: | |
4375 | /* Only DDI platforms should ever use this output type */ | |
4376 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
4377 | case INTEL_OUTPUT_DISPLAYPORT: | |
4378 | case INTEL_OUTPUT_HDMI: | |
4379 | case INTEL_OUTPUT_EDP: | |
4380 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 4381 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
4382 | case INTEL_OUTPUT_DP_MST: |
4383 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
4384 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
4385 | case INTEL_OUTPUT_ANALOG: |
4386 | return POWER_DOMAIN_PORT_CRT; | |
4387 | case INTEL_OUTPUT_DSI: | |
4388 | return POWER_DOMAIN_PORT_DSI; | |
4389 | default: | |
4390 | return POWER_DOMAIN_PORT_OTHER; | |
4391 | } | |
4392 | } | |
4393 | ||
4394 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) | |
77d22dca | 4395 | { |
319be8ae ID |
4396 | struct drm_device *dev = crtc->dev; |
4397 | struct intel_encoder *intel_encoder; | |
4398 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4399 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca ID |
4400 | unsigned long mask; |
4401 | enum transcoder transcoder; | |
4402 | ||
4403 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); | |
4404 | ||
4405 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); | |
4406 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
fabf6e51 DV |
4407 | if (intel_crtc->config.pch_pfit.enabled || |
4408 | intel_crtc->config.pch_pfit.force_thru) | |
77d22dca ID |
4409 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
4410 | ||
319be8ae ID |
4411 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
4412 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); | |
4413 | ||
77d22dca ID |
4414 | return mask; |
4415 | } | |
4416 | ||
4417 | void intel_display_set_init_power(struct drm_i915_private *dev_priv, | |
4418 | bool enable) | |
4419 | { | |
4420 | if (dev_priv->power_domains.init_power_on == enable) | |
4421 | return; | |
4422 | ||
4423 | if (enable) | |
4424 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); | |
4425 | else | |
4426 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); | |
4427 | ||
4428 | dev_priv->power_domains.init_power_on = enable; | |
4429 | } | |
4430 | ||
4431 | static void modeset_update_crtc_power_domains(struct drm_device *dev) | |
4432 | { | |
4433 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4434 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; | |
4435 | struct intel_crtc *crtc; | |
4436 | ||
4437 | /* | |
4438 | * First get all needed power domains, then put all unneeded, to avoid | |
4439 | * any unnecessary toggling of the power wells. | |
4440 | */ | |
d3fcc808 | 4441 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
4442 | enum intel_display_power_domain domain; |
4443 | ||
4444 | if (!crtc->base.enabled) | |
4445 | continue; | |
4446 | ||
319be8ae | 4447 | pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base); |
77d22dca ID |
4448 | |
4449 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) | |
4450 | intel_display_power_get(dev_priv, domain); | |
4451 | } | |
4452 | ||
d3fcc808 | 4453 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
4454 | enum intel_display_power_domain domain; |
4455 | ||
4456 | for_each_power_domain(domain, crtc->enabled_power_domains) | |
4457 | intel_display_power_put(dev_priv, domain); | |
4458 | ||
4459 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; | |
4460 | } | |
4461 | ||
4462 | intel_display_set_init_power(dev_priv, false); | |
4463 | } | |
4464 | ||
dfcab17e | 4465 | /* returns HPLL frequency in kHz */ |
f8bf63fd | 4466 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) |
30a970c6 | 4467 | { |
586f49dc | 4468 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
30a970c6 | 4469 | |
586f49dc JB |
4470 | /* Obtain SKU information */ |
4471 | mutex_lock(&dev_priv->dpio_lock); | |
4472 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
4473 | CCK_FUSE_HPLL_FREQ_MASK; | |
4474 | mutex_unlock(&dev_priv->dpio_lock); | |
30a970c6 | 4475 | |
dfcab17e | 4476 | return vco_freq[hpll_freq] * 1000; |
30a970c6 JB |
4477 | } |
4478 | ||
f8bf63fd VS |
4479 | static void vlv_update_cdclk(struct drm_device *dev) |
4480 | { | |
4481 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4482 | ||
4483 | dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
4484 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz", | |
4485 | dev_priv->vlv_cdclk_freq); | |
4486 | ||
4487 | /* | |
4488 | * Program the gmbus_freq based on the cdclk frequency. | |
4489 | * BSpec erroneously claims we should aim for 4MHz, but | |
4490 | * in fact 1MHz is the correct frequency. | |
4491 | */ | |
4492 | I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq); | |
4493 | } | |
4494 | ||
30a970c6 JB |
4495 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
4496 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
4497 | { | |
4498 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4499 | u32 val, cmd; | |
4500 | ||
d197b7d3 | 4501 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq); |
d60c4473 | 4502 | |
dfcab17e | 4503 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 4504 | cmd = 2; |
dfcab17e | 4505 | else if (cdclk == 266667) |
30a970c6 JB |
4506 | cmd = 1; |
4507 | else | |
4508 | cmd = 0; | |
4509 | ||
4510 | mutex_lock(&dev_priv->rps.hw_lock); | |
4511 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
4512 | val &= ~DSPFREQGUAR_MASK; | |
4513 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
4514 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
4515 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
4516 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
4517 | 50)) { | |
4518 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
4519 | } | |
4520 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4521 | ||
dfcab17e | 4522 | if (cdclk == 400000) { |
30a970c6 JB |
4523 | u32 divider, vco; |
4524 | ||
4525 | vco = valleyview_get_vco(dev_priv); | |
dfcab17e | 4526 | divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1; |
30a970c6 JB |
4527 | |
4528 | mutex_lock(&dev_priv->dpio_lock); | |
4529 | /* adjust cdclk divider */ | |
4530 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
9cf33db5 | 4531 | val &= ~DISPLAY_FREQUENCY_VALUES; |
30a970c6 JB |
4532 | val |= divider; |
4533 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
4534 | |
4535 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
4536 | DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
4537 | 50)) | |
4538 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
4539 | mutex_unlock(&dev_priv->dpio_lock); |
4540 | } | |
4541 | ||
4542 | mutex_lock(&dev_priv->dpio_lock); | |
4543 | /* adjust self-refresh exit latency value */ | |
4544 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
4545 | val &= ~0x7f; | |
4546 | ||
4547 | /* | |
4548 | * For high bandwidth configs, we set a higher latency in the bunit | |
4549 | * so that the core display fetch happens in time to avoid underruns. | |
4550 | */ | |
dfcab17e | 4551 | if (cdclk == 400000) |
30a970c6 JB |
4552 | val |= 4500 / 250; /* 4.5 usec */ |
4553 | else | |
4554 | val |= 3000 / 250; /* 3.0 usec */ | |
4555 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
4556 | mutex_unlock(&dev_priv->dpio_lock); | |
4557 | ||
f8bf63fd | 4558 | vlv_update_cdclk(dev); |
30a970c6 JB |
4559 | } |
4560 | ||
383c5a6a VS |
4561 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
4562 | { | |
4563 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4564 | u32 val, cmd; | |
4565 | ||
4566 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq); | |
4567 | ||
4568 | switch (cdclk) { | |
4569 | case 400000: | |
4570 | cmd = 3; | |
4571 | break; | |
4572 | case 333333: | |
4573 | case 320000: | |
4574 | cmd = 2; | |
4575 | break; | |
4576 | case 266667: | |
4577 | cmd = 1; | |
4578 | break; | |
4579 | case 200000: | |
4580 | cmd = 0; | |
4581 | break; | |
4582 | default: | |
4583 | WARN_ON(1); | |
4584 | return; | |
4585 | } | |
4586 | ||
4587 | mutex_lock(&dev_priv->rps.hw_lock); | |
4588 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
4589 | val &= ~DSPFREQGUAR_MASK_CHV; | |
4590 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
4591 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
4592 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
4593 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
4594 | 50)) { | |
4595 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
4596 | } | |
4597 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4598 | ||
4599 | vlv_update_cdclk(dev); | |
4600 | } | |
4601 | ||
30a970c6 JB |
4602 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
4603 | int max_pixclk) | |
4604 | { | |
29dc7ef3 VS |
4605 | int vco = valleyview_get_vco(dev_priv); |
4606 | int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000; | |
4607 | ||
d49a340d VS |
4608 | /* FIXME: Punit isn't quite ready yet */ |
4609 | if (IS_CHERRYVIEW(dev_priv->dev)) | |
4610 | return 400000; | |
4611 | ||
30a970c6 JB |
4612 | /* |
4613 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
4614 | * 200MHz | |
4615 | * 267MHz | |
29dc7ef3 | 4616 | * 320/333MHz (depends on HPLL freq) |
30a970c6 JB |
4617 | * 400MHz |
4618 | * So we check to see whether we're above 90% of the lower bin and | |
4619 | * adjust if needed. | |
e37c67a1 VS |
4620 | * |
4621 | * We seem to get an unstable or solid color picture at 200MHz. | |
4622 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
4623 | * are off. | |
30a970c6 | 4624 | */ |
29dc7ef3 | 4625 | if (max_pixclk > freq_320*9/10) |
dfcab17e VS |
4626 | return 400000; |
4627 | else if (max_pixclk > 266667*9/10) | |
29dc7ef3 | 4628 | return freq_320; |
e37c67a1 | 4629 | else if (max_pixclk > 0) |
dfcab17e | 4630 | return 266667; |
e37c67a1 VS |
4631 | else |
4632 | return 200000; | |
30a970c6 JB |
4633 | } |
4634 | ||
2f2d7aa1 VS |
4635 | /* compute the max pixel clock for new configuration */ |
4636 | static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv) | |
30a970c6 JB |
4637 | { |
4638 | struct drm_device *dev = dev_priv->dev; | |
4639 | struct intel_crtc *intel_crtc; | |
4640 | int max_pixclk = 0; | |
4641 | ||
d3fcc808 | 4642 | for_each_intel_crtc(dev, intel_crtc) { |
2f2d7aa1 | 4643 | if (intel_crtc->new_enabled) |
30a970c6 | 4644 | max_pixclk = max(max_pixclk, |
2f2d7aa1 | 4645 | intel_crtc->new_config->adjusted_mode.crtc_clock); |
30a970c6 JB |
4646 | } |
4647 | ||
4648 | return max_pixclk; | |
4649 | } | |
4650 | ||
4651 | static void valleyview_modeset_global_pipes(struct drm_device *dev, | |
2f2d7aa1 | 4652 | unsigned *prepare_pipes) |
30a970c6 JB |
4653 | { |
4654 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4655 | struct intel_crtc *intel_crtc; | |
2f2d7aa1 | 4656 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 | 4657 | |
d60c4473 ID |
4658 | if (valleyview_calc_cdclk(dev_priv, max_pixclk) == |
4659 | dev_priv->vlv_cdclk_freq) | |
30a970c6 JB |
4660 | return; |
4661 | ||
2f2d7aa1 | 4662 | /* disable/enable all currently active pipes while we change cdclk */ |
d3fcc808 | 4663 | for_each_intel_crtc(dev, intel_crtc) |
30a970c6 JB |
4664 | if (intel_crtc->base.enabled) |
4665 | *prepare_pipes |= (1 << intel_crtc->pipe); | |
4666 | } | |
4667 | ||
4668 | static void valleyview_modeset_global_resources(struct drm_device *dev) | |
4669 | { | |
4670 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2f2d7aa1 | 4671 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 JB |
4672 | int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); |
4673 | ||
383c5a6a VS |
4674 | if (req_cdclk != dev_priv->vlv_cdclk_freq) { |
4675 | if (IS_CHERRYVIEW(dev)) | |
4676 | cherryview_set_cdclk(dev, req_cdclk); | |
4677 | else | |
4678 | valleyview_set_cdclk(dev, req_cdclk); | |
4679 | } | |
4680 | ||
77961eb9 | 4681 | modeset_update_crtc_power_domains(dev); |
30a970c6 JB |
4682 | } |
4683 | ||
89b667f8 JB |
4684 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
4685 | { | |
4686 | struct drm_device *dev = crtc->dev; | |
89b667f8 JB |
4687 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4688 | struct intel_encoder *encoder; | |
4689 | int pipe = intel_crtc->pipe; | |
23538ef1 | 4690 | bool is_dsi; |
89b667f8 JB |
4691 | |
4692 | WARN_ON(!crtc->enabled); | |
4693 | ||
4694 | if (intel_crtc->active) | |
4695 | return; | |
4696 | ||
8525a235 SK |
4697 | is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI); |
4698 | ||
1ae0d137 VS |
4699 | if (!is_dsi) { |
4700 | if (IS_CHERRYVIEW(dev)) | |
4701 | chv_prepare_pll(intel_crtc); | |
4702 | else | |
4703 | vlv_prepare_pll(intel_crtc); | |
4704 | } | |
bdd4b6a6 | 4705 | |
5b18e57c DV |
4706 | if (intel_crtc->config.has_dp_encoder) |
4707 | intel_dp_set_m_n(intel_crtc); | |
4708 | ||
4709 | intel_set_pipe_timings(intel_crtc); | |
4710 | ||
5b18e57c DV |
4711 | i9xx_set_pipeconf(intel_crtc); |
4712 | ||
89b667f8 | 4713 | intel_crtc->active = true; |
89b667f8 | 4714 | |
4a3436e8 VS |
4715 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
4716 | ||
89b667f8 JB |
4717 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4718 | if (encoder->pre_pll_enable) | |
4719 | encoder->pre_pll_enable(encoder); | |
4720 | ||
9d556c99 CML |
4721 | if (!is_dsi) { |
4722 | if (IS_CHERRYVIEW(dev)) | |
4723 | chv_enable_pll(intel_crtc); | |
4724 | else | |
4725 | vlv_enable_pll(intel_crtc); | |
4726 | } | |
89b667f8 JB |
4727 | |
4728 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
4729 | if (encoder->pre_enable) | |
4730 | encoder->pre_enable(encoder); | |
4731 | ||
2dd24552 JB |
4732 | i9xx_pfit_enable(intel_crtc); |
4733 | ||
63cbb074 VS |
4734 | intel_crtc_load_lut(crtc); |
4735 | ||
f37fcc2a | 4736 | intel_update_watermarks(crtc); |
e1fdc473 | 4737 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 4738 | |
5004945f JN |
4739 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4740 | encoder->enable(encoder); | |
9ab0460b VS |
4741 | |
4742 | intel_crtc_enable_planes(crtc); | |
d40d9187 | 4743 | |
56b80e1f VS |
4744 | /* Underruns don't raise interrupts, so check manually. */ |
4745 | i9xx_check_fifo_underruns(dev); | |
89b667f8 JB |
4746 | } |
4747 | ||
f13c2ef3 DV |
4748 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
4749 | { | |
4750 | struct drm_device *dev = crtc->base.dev; | |
4751 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4752 | ||
4753 | I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0); | |
4754 | I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1); | |
4755 | } | |
4756 | ||
0b8765c6 | 4757 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
4758 | { |
4759 | struct drm_device *dev = crtc->dev; | |
79e53945 | 4760 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 4761 | struct intel_encoder *encoder; |
79e53945 | 4762 | int pipe = intel_crtc->pipe; |
79e53945 | 4763 | |
08a48469 DV |
4764 | WARN_ON(!crtc->enabled); |
4765 | ||
f7abfe8b CW |
4766 | if (intel_crtc->active) |
4767 | return; | |
4768 | ||
f13c2ef3 DV |
4769 | i9xx_set_pll_dividers(intel_crtc); |
4770 | ||
5b18e57c DV |
4771 | if (intel_crtc->config.has_dp_encoder) |
4772 | intel_dp_set_m_n(intel_crtc); | |
4773 | ||
4774 | intel_set_pipe_timings(intel_crtc); | |
4775 | ||
5b18e57c DV |
4776 | i9xx_set_pipeconf(intel_crtc); |
4777 | ||
f7abfe8b | 4778 | intel_crtc->active = true; |
6b383a7f | 4779 | |
4a3436e8 VS |
4780 | if (!IS_GEN2(dev)) |
4781 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
4782 | ||
9d6d9f19 MK |
4783 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4784 | if (encoder->pre_enable) | |
4785 | encoder->pre_enable(encoder); | |
4786 | ||
f6736a1a DV |
4787 | i9xx_enable_pll(intel_crtc); |
4788 | ||
2dd24552 JB |
4789 | i9xx_pfit_enable(intel_crtc); |
4790 | ||
63cbb074 VS |
4791 | intel_crtc_load_lut(crtc); |
4792 | ||
f37fcc2a | 4793 | intel_update_watermarks(crtc); |
e1fdc473 | 4794 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 4795 | |
fa5c73b1 DV |
4796 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4797 | encoder->enable(encoder); | |
9ab0460b VS |
4798 | |
4799 | intel_crtc_enable_planes(crtc); | |
d40d9187 | 4800 | |
4a3436e8 VS |
4801 | /* |
4802 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4803 | * So don't enable underrun reporting before at least some planes | |
4804 | * are enabled. | |
4805 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4806 | * but leave the pipe running. | |
4807 | */ | |
4808 | if (IS_GEN2(dev)) | |
4809 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
4810 | ||
56b80e1f VS |
4811 | /* Underruns don't raise interrupts, so check manually. */ |
4812 | i9xx_check_fifo_underruns(dev); | |
0b8765c6 | 4813 | } |
79e53945 | 4814 | |
87476d63 DV |
4815 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
4816 | { | |
4817 | struct drm_device *dev = crtc->base.dev; | |
4818 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 4819 | |
328d8e82 DV |
4820 | if (!crtc->config.gmch_pfit.control) |
4821 | return; | |
87476d63 | 4822 | |
328d8e82 | 4823 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 4824 | |
328d8e82 DV |
4825 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
4826 | I915_READ(PFIT_CONTROL)); | |
4827 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
4828 | } |
4829 | ||
0b8765c6 JB |
4830 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
4831 | { | |
4832 | struct drm_device *dev = crtc->dev; | |
4833 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4834 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4835 | struct intel_encoder *encoder; |
0b8765c6 | 4836 | int pipe = intel_crtc->pipe; |
ef9c3aee | 4837 | |
f7abfe8b CW |
4838 | if (!intel_crtc->active) |
4839 | return; | |
4840 | ||
4a3436e8 VS |
4841 | /* |
4842 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4843 | * So diasble underrun reporting before all the planes get disabled. | |
4844 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4845 | * but leave the pipe running. | |
4846 | */ | |
4847 | if (IS_GEN2(dev)) | |
4848 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false); | |
4849 | ||
564ed191 ID |
4850 | /* |
4851 | * Vblank time updates from the shadow to live plane control register | |
4852 | * are blocked if the memory self-refresh mode is active at that | |
4853 | * moment. So to make sure the plane gets truly disabled, disable | |
4854 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4855 | * will be checked/applied by the HW only at the next frame start | |
4856 | * event which is after the vblank start event, so we need to have a | |
4857 | * wait-for-vblank between disabling the plane and the pipe. | |
4858 | */ | |
4859 | intel_set_memory_cxsr(dev_priv, false); | |
9ab0460b VS |
4860 | intel_crtc_disable_planes(crtc); |
4861 | ||
ea9d758d DV |
4862 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4863 | encoder->disable(encoder); | |
4864 | ||
6304cd91 VS |
4865 | /* |
4866 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
4867 | * wait for planes to fully turn off before disabling the pipe. | |
564ed191 ID |
4868 | * We also need to wait on all gmch platforms because of the |
4869 | * self-refresh mode constraint explained above. | |
6304cd91 | 4870 | */ |
564ed191 | 4871 | intel_wait_for_vblank(dev, pipe); |
6304cd91 | 4872 | |
575f7ab7 | 4873 | intel_disable_pipe(intel_crtc); |
24a1f16d | 4874 | |
87476d63 | 4875 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 4876 | |
89b667f8 JB |
4877 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4878 | if (encoder->post_disable) | |
4879 | encoder->post_disable(encoder); | |
4880 | ||
076ed3b2 CML |
4881 | if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) { |
4882 | if (IS_CHERRYVIEW(dev)) | |
4883 | chv_disable_pll(dev_priv, pipe); | |
4884 | else if (IS_VALLEYVIEW(dev)) | |
4885 | vlv_disable_pll(dev_priv, pipe); | |
4886 | else | |
4887 | i9xx_disable_pll(dev_priv, pipe); | |
4888 | } | |
0b8765c6 | 4889 | |
4a3436e8 VS |
4890 | if (!IS_GEN2(dev)) |
4891 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false); | |
4892 | ||
f7abfe8b | 4893 | intel_crtc->active = false; |
46ba614c | 4894 | intel_update_watermarks(crtc); |
f37fcc2a | 4895 | |
efa9624e | 4896 | mutex_lock(&dev->struct_mutex); |
6b383a7f | 4897 | intel_update_fbc(dev); |
efa9624e | 4898 | mutex_unlock(&dev->struct_mutex); |
0b8765c6 JB |
4899 | } |
4900 | ||
ee7b9f93 JB |
4901 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
4902 | { | |
4903 | } | |
4904 | ||
976f8a20 DV |
4905 | static void intel_crtc_update_sarea(struct drm_crtc *crtc, |
4906 | bool enabled) | |
2c07245f ZW |
4907 | { |
4908 | struct drm_device *dev = crtc->dev; | |
4909 | struct drm_i915_master_private *master_priv; | |
4910 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4911 | int pipe = intel_crtc->pipe; | |
79e53945 JB |
4912 | |
4913 | if (!dev->primary->master) | |
4914 | return; | |
4915 | ||
4916 | master_priv = dev->primary->master->driver_priv; | |
4917 | if (!master_priv->sarea_priv) | |
4918 | return; | |
4919 | ||
79e53945 JB |
4920 | switch (pipe) { |
4921 | case 0: | |
4922 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
4923 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
4924 | break; | |
4925 | case 1: | |
4926 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
4927 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
4928 | break; | |
4929 | default: | |
9db4a9c7 | 4930 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
79e53945 JB |
4931 | break; |
4932 | } | |
79e53945 JB |
4933 | } |
4934 | ||
b04c5bd6 BF |
4935 | /* Master function to enable/disable CRTC and corresponding power wells */ |
4936 | void intel_crtc_control(struct drm_crtc *crtc, bool enable) | |
976f8a20 DV |
4937 | { |
4938 | struct drm_device *dev = crtc->dev; | |
4939 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0e572fe7 | 4940 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
0e572fe7 DV |
4941 | enum intel_display_power_domain domain; |
4942 | unsigned long domains; | |
976f8a20 | 4943 | |
0e572fe7 DV |
4944 | if (enable) { |
4945 | if (!intel_crtc->active) { | |
e1e9fb84 DV |
4946 | domains = get_crtc_power_domains(crtc); |
4947 | for_each_power_domain(domain, domains) | |
4948 | intel_display_power_get(dev_priv, domain); | |
4949 | intel_crtc->enabled_power_domains = domains; | |
0e572fe7 DV |
4950 | |
4951 | dev_priv->display.crtc_enable(crtc); | |
4952 | } | |
4953 | } else { | |
4954 | if (intel_crtc->active) { | |
4955 | dev_priv->display.crtc_disable(crtc); | |
4956 | ||
e1e9fb84 DV |
4957 | domains = intel_crtc->enabled_power_domains; |
4958 | for_each_power_domain(domain, domains) | |
4959 | intel_display_power_put(dev_priv, domain); | |
4960 | intel_crtc->enabled_power_domains = 0; | |
0e572fe7 DV |
4961 | } |
4962 | } | |
b04c5bd6 BF |
4963 | } |
4964 | ||
4965 | /** | |
4966 | * Sets the power management mode of the pipe and plane. | |
4967 | */ | |
4968 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
4969 | { | |
4970 | struct drm_device *dev = crtc->dev; | |
4971 | struct intel_encoder *intel_encoder; | |
4972 | bool enable = false; | |
4973 | ||
4974 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
4975 | enable |= intel_encoder->connectors_active; | |
4976 | ||
4977 | intel_crtc_control(crtc, enable); | |
976f8a20 DV |
4978 | |
4979 | intel_crtc_update_sarea(crtc, enable); | |
4980 | } | |
4981 | ||
cdd59983 CW |
4982 | static void intel_crtc_disable(struct drm_crtc *crtc) |
4983 | { | |
cdd59983 | 4984 | struct drm_device *dev = crtc->dev; |
976f8a20 | 4985 | struct drm_connector *connector; |
ee7b9f93 | 4986 | struct drm_i915_private *dev_priv = dev->dev_private; |
2ff8fde1 | 4987 | struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb); |
a071fa00 | 4988 | enum pipe pipe = to_intel_crtc(crtc)->pipe; |
cdd59983 | 4989 | |
976f8a20 DV |
4990 | /* crtc should still be enabled when we disable it. */ |
4991 | WARN_ON(!crtc->enabled); | |
4992 | ||
4993 | dev_priv->display.crtc_disable(crtc); | |
4994 | intel_crtc_update_sarea(crtc, false); | |
ee7b9f93 JB |
4995 | dev_priv->display.off(crtc); |
4996 | ||
f4510a27 | 4997 | if (crtc->primary->fb) { |
cdd59983 | 4998 | mutex_lock(&dev->struct_mutex); |
a071fa00 DV |
4999 | intel_unpin_fb_obj(old_obj); |
5000 | i915_gem_track_fb(old_obj, NULL, | |
5001 | INTEL_FRONTBUFFER_PRIMARY(pipe)); | |
cdd59983 | 5002 | mutex_unlock(&dev->struct_mutex); |
f4510a27 | 5003 | crtc->primary->fb = NULL; |
976f8a20 DV |
5004 | } |
5005 | ||
5006 | /* Update computed state. */ | |
5007 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
5008 | if (!connector->encoder || !connector->encoder->crtc) | |
5009 | continue; | |
5010 | ||
5011 | if (connector->encoder->crtc != crtc) | |
5012 | continue; | |
5013 | ||
5014 | connector->dpms = DRM_MODE_DPMS_OFF; | |
5015 | to_intel_encoder(connector->encoder)->connectors_active = false; | |
cdd59983 CW |
5016 | } |
5017 | } | |
5018 | ||
ea5b213a | 5019 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 5020 | { |
4ef69c7a | 5021 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 5022 | |
ea5b213a CW |
5023 | drm_encoder_cleanup(encoder); |
5024 | kfree(intel_encoder); | |
7e7d76c3 JB |
5025 | } |
5026 | ||
9237329d | 5027 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
5ab432ef DV |
5028 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
5029 | * state of the entire output pipe. */ | |
9237329d | 5030 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
7e7d76c3 | 5031 | { |
5ab432ef DV |
5032 | if (mode == DRM_MODE_DPMS_ON) { |
5033 | encoder->connectors_active = true; | |
5034 | ||
b2cabb0e | 5035 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
5036 | } else { |
5037 | encoder->connectors_active = false; | |
5038 | ||
b2cabb0e | 5039 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 5040 | } |
79e53945 JB |
5041 | } |
5042 | ||
0a91ca29 DV |
5043 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
5044 | * internal consistency). */ | |
b980514c | 5045 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 5046 | { |
0a91ca29 DV |
5047 | if (connector->get_hw_state(connector)) { |
5048 | struct intel_encoder *encoder = connector->encoder; | |
5049 | struct drm_crtc *crtc; | |
5050 | bool encoder_enabled; | |
5051 | enum pipe pipe; | |
5052 | ||
5053 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
5054 | connector->base.base.id, | |
c23cc417 | 5055 | connector->base.name); |
0a91ca29 | 5056 | |
0e32b39c DA |
5057 | /* there is no real hw state for MST connectors */ |
5058 | if (connector->mst_port) | |
5059 | return; | |
5060 | ||
0a91ca29 DV |
5061 | WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, |
5062 | "wrong connector dpms state\n"); | |
5063 | WARN(connector->base.encoder != &encoder->base, | |
5064 | "active connector not linked to encoder\n"); | |
0a91ca29 | 5065 | |
36cd7444 DA |
5066 | if (encoder) { |
5067 | WARN(!encoder->connectors_active, | |
5068 | "encoder->connectors_active not set\n"); | |
5069 | ||
5070 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
5071 | WARN(!encoder_enabled, "encoder not enabled\n"); | |
5072 | if (WARN_ON(!encoder->base.crtc)) | |
5073 | return; | |
0a91ca29 | 5074 | |
36cd7444 | 5075 | crtc = encoder->base.crtc; |
0a91ca29 | 5076 | |
36cd7444 DA |
5077 | WARN(!crtc->enabled, "crtc not enabled\n"); |
5078 | WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); | |
5079 | WARN(pipe != to_intel_crtc(crtc)->pipe, | |
5080 | "encoder active on the wrong pipe\n"); | |
5081 | } | |
0a91ca29 | 5082 | } |
79e53945 JB |
5083 | } |
5084 | ||
5ab432ef DV |
5085 | /* Even simpler default implementation, if there's really no special case to |
5086 | * consider. */ | |
5087 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 5088 | { |
5ab432ef DV |
5089 | /* All the simple cases only support two dpms states. */ |
5090 | if (mode != DRM_MODE_DPMS_ON) | |
5091 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 5092 | |
5ab432ef DV |
5093 | if (mode == connector->dpms) |
5094 | return; | |
5095 | ||
5096 | connector->dpms = mode; | |
5097 | ||
5098 | /* Only need to change hw state when actually enabled */ | |
c9976dcf CW |
5099 | if (connector->encoder) |
5100 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); | |
0a91ca29 | 5101 | |
b980514c | 5102 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
5103 | } |
5104 | ||
f0947c37 DV |
5105 | /* Simple connector->get_hw_state implementation for encoders that support only |
5106 | * one connector and no cloning and hence the encoder state determines the state | |
5107 | * of the connector. */ | |
5108 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 5109 | { |
24929352 | 5110 | enum pipe pipe = 0; |
f0947c37 | 5111 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 5112 | |
f0947c37 | 5113 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
5114 | } |
5115 | ||
1857e1da DV |
5116 | static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5117 | struct intel_crtc_config *pipe_config) | |
5118 | { | |
5119 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5120 | struct intel_crtc *pipe_B_crtc = | |
5121 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
5122 | ||
5123 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", | |
5124 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5125 | if (pipe_config->fdi_lanes > 4) { | |
5126 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
5127 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5128 | return false; | |
5129 | } | |
5130 | ||
bafb6553 | 5131 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
5132 | if (pipe_config->fdi_lanes > 2) { |
5133 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
5134 | pipe_config->fdi_lanes); | |
5135 | return false; | |
5136 | } else { | |
5137 | return true; | |
5138 | } | |
5139 | } | |
5140 | ||
5141 | if (INTEL_INFO(dev)->num_pipes == 2) | |
5142 | return true; | |
5143 | ||
5144 | /* Ivybridge 3 pipe is really complicated */ | |
5145 | switch (pipe) { | |
5146 | case PIPE_A: | |
5147 | return true; | |
5148 | case PIPE_B: | |
5149 | if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && | |
5150 | pipe_config->fdi_lanes > 2) { | |
5151 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
5152 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5153 | return false; | |
5154 | } | |
5155 | return true; | |
5156 | case PIPE_C: | |
1e833f40 | 5157 | if (!pipe_has_enabled_pch(pipe_B_crtc) || |
1857e1da DV |
5158 | pipe_B_crtc->config.fdi_lanes <= 2) { |
5159 | if (pipe_config->fdi_lanes > 2) { | |
5160 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
5161 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5162 | return false; | |
5163 | } | |
5164 | } else { | |
5165 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); | |
5166 | return false; | |
5167 | } | |
5168 | return true; | |
5169 | default: | |
5170 | BUG(); | |
5171 | } | |
5172 | } | |
5173 | ||
e29c22c0 DV |
5174 | #define RETRY 1 |
5175 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5176 | struct intel_crtc_config *pipe_config) | |
877d48d5 | 5177 | { |
1857e1da | 5178 | struct drm_device *dev = intel_crtc->base.dev; |
877d48d5 | 5179 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
ff9a6750 | 5180 | int lane, link_bw, fdi_dotclock; |
e29c22c0 | 5181 | bool setup_ok, needs_recompute = false; |
877d48d5 | 5182 | |
e29c22c0 | 5183 | retry: |
877d48d5 DV |
5184 | /* FDI is a binary signal running at ~2.7GHz, encoding |
5185 | * each output octet as 10 bits. The actual frequency | |
5186 | * is stored as a divider into a 100MHz clock, and the | |
5187 | * mode pixel clock is stored in units of 1KHz. | |
5188 | * Hence the bw of each lane in terms of the mode signal | |
5189 | * is: | |
5190 | */ | |
5191 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
5192 | ||
241bfc38 | 5193 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 5194 | |
2bd89a07 | 5195 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
5196 | pipe_config->pipe_bpp); |
5197 | ||
5198 | pipe_config->fdi_lanes = lane; | |
5199 | ||
2bd89a07 | 5200 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 5201 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 5202 | |
e29c22c0 DV |
5203 | setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
5204 | intel_crtc->pipe, pipe_config); | |
5205 | if (!setup_ok && pipe_config->pipe_bpp > 6*3) { | |
5206 | pipe_config->pipe_bpp -= 2*3; | |
5207 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
5208 | pipe_config->pipe_bpp); | |
5209 | needs_recompute = true; | |
5210 | pipe_config->bw_constrained = true; | |
5211 | ||
5212 | goto retry; | |
5213 | } | |
5214 | ||
5215 | if (needs_recompute) | |
5216 | return RETRY; | |
5217 | ||
5218 | return setup_ok ? 0 : -EINVAL; | |
877d48d5 DV |
5219 | } |
5220 | ||
42db64ef PZ |
5221 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5222 | struct intel_crtc_config *pipe_config) | |
5223 | { | |
d330a953 | 5224 | pipe_config->ips_enabled = i915.enable_ips && |
3c4ca58c | 5225 | hsw_crtc_supports_ips(crtc) && |
b6dfdc9b | 5226 | pipe_config->pipe_bpp <= 24; |
42db64ef PZ |
5227 | } |
5228 | ||
a43f6e0f | 5229 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
e29c22c0 | 5230 | struct intel_crtc_config *pipe_config) |
79e53945 | 5231 | { |
a43f6e0f | 5232 | struct drm_device *dev = crtc->base.dev; |
b8cecdf5 | 5233 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
89749350 | 5234 | |
ad3a4479 | 5235 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 VS |
5236 | if (INTEL_INFO(dev)->gen < 4) { |
5237 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5238 | int clock_limit = | |
5239 | dev_priv->display.get_display_clock_speed(dev); | |
5240 | ||
5241 | /* | |
5242 | * Enable pixel doubling when the dot clock | |
5243 | * is > 90% of the (display) core speed. | |
5244 | * | |
b397c96b VS |
5245 | * GDG double wide on either pipe, |
5246 | * otherwise pipe A only. | |
cf532bb2 | 5247 | */ |
b397c96b | 5248 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
241bfc38 | 5249 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
ad3a4479 | 5250 | clock_limit *= 2; |
cf532bb2 | 5251 | pipe_config->double_wide = true; |
ad3a4479 VS |
5252 | } |
5253 | ||
241bfc38 | 5254 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
e29c22c0 | 5255 | return -EINVAL; |
2c07245f | 5256 | } |
89749350 | 5257 | |
1d1d0e27 VS |
5258 | /* |
5259 | * Pipe horizontal size must be even in: | |
5260 | * - DVO ganged mode | |
5261 | * - LVDS dual channel mode | |
5262 | * - Double wide pipe | |
5263 | */ | |
5264 | if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && | |
5265 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) | |
5266 | pipe_config->pipe_src_w &= ~1; | |
5267 | ||
8693a824 DL |
5268 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
5269 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
5270 | */ |
5271 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
5272 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
e29c22c0 | 5273 | return -EINVAL; |
44f46b42 | 5274 | |
bd080ee5 | 5275 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { |
5d2d38dd | 5276 | pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ |
bd080ee5 | 5277 | } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { |
5d2d38dd DV |
5278 | /* only a 8bpc pipe, with 6bpc dither through the panel fitter |
5279 | * for lvds. */ | |
5280 | pipe_config->pipe_bpp = 8*3; | |
5281 | } | |
5282 | ||
f5adf94e | 5283 | if (HAS_IPS(dev)) |
a43f6e0f DV |
5284 | hsw_compute_ips_config(crtc, pipe_config); |
5285 | ||
12030431 DV |
5286 | /* |
5287 | * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the | |
5288 | * old clock survives for now. | |
5289 | */ | |
5290 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev)) | |
a43f6e0f | 5291 | pipe_config->shared_dpll = crtc->config.shared_dpll; |
42db64ef | 5292 | |
877d48d5 | 5293 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 5294 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 5295 | |
e29c22c0 | 5296 | return 0; |
79e53945 JB |
5297 | } |
5298 | ||
25eb05fc JB |
5299 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
5300 | { | |
d197b7d3 VS |
5301 | struct drm_i915_private *dev_priv = dev->dev_private; |
5302 | int vco = valleyview_get_vco(dev_priv); | |
5303 | u32 val; | |
5304 | int divider; | |
5305 | ||
d49a340d VS |
5306 | /* FIXME: Punit isn't quite ready yet */ |
5307 | if (IS_CHERRYVIEW(dev)) | |
5308 | return 400000; | |
5309 | ||
d197b7d3 VS |
5310 | mutex_lock(&dev_priv->dpio_lock); |
5311 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
5312 | mutex_unlock(&dev_priv->dpio_lock); | |
5313 | ||
5314 | divider = val & DISPLAY_FREQUENCY_VALUES; | |
5315 | ||
7d007f40 VS |
5316 | WARN((val & DISPLAY_FREQUENCY_STATUS) != |
5317 | (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
5318 | "cdclk change in progress\n"); | |
5319 | ||
d197b7d3 | 5320 | return DIV_ROUND_CLOSEST(vco << 1, divider + 1); |
25eb05fc JB |
5321 | } |
5322 | ||
e70236a8 JB |
5323 | static int i945_get_display_clock_speed(struct drm_device *dev) |
5324 | { | |
5325 | return 400000; | |
5326 | } | |
79e53945 | 5327 | |
e70236a8 | 5328 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 5329 | { |
e70236a8 JB |
5330 | return 333000; |
5331 | } | |
79e53945 | 5332 | |
e70236a8 JB |
5333 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
5334 | { | |
5335 | return 200000; | |
5336 | } | |
79e53945 | 5337 | |
257a7ffc DV |
5338 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
5339 | { | |
5340 | u16 gcfgc = 0; | |
5341 | ||
5342 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
5343 | ||
5344 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
5345 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
5346 | return 267000; | |
5347 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: | |
5348 | return 333000; | |
5349 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: | |
5350 | return 444000; | |
5351 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: | |
5352 | return 200000; | |
5353 | default: | |
5354 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
5355 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
5356 | return 133000; | |
5357 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: | |
5358 | return 167000; | |
5359 | } | |
5360 | } | |
5361 | ||
e70236a8 JB |
5362 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
5363 | { | |
5364 | u16 gcfgc = 0; | |
79e53945 | 5365 | |
e70236a8 JB |
5366 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
5367 | ||
5368 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
5369 | return 133000; | |
5370 | else { | |
5371 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
5372 | case GC_DISPLAY_CLOCK_333_MHZ: | |
5373 | return 333000; | |
5374 | default: | |
5375 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
5376 | return 190000; | |
79e53945 | 5377 | } |
e70236a8 JB |
5378 | } |
5379 | } | |
5380 | ||
5381 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
5382 | { | |
5383 | return 266000; | |
5384 | } | |
5385 | ||
5386 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
5387 | { | |
5388 | u16 hpllcc = 0; | |
5389 | /* Assume that the hardware is in the high speed state. This | |
5390 | * should be the default. | |
5391 | */ | |
5392 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
5393 | case GC_CLOCK_133_200: | |
5394 | case GC_CLOCK_100_200: | |
5395 | return 200000; | |
5396 | case GC_CLOCK_166_250: | |
5397 | return 250000; | |
5398 | case GC_CLOCK_100_133: | |
79e53945 | 5399 | return 133000; |
e70236a8 | 5400 | } |
79e53945 | 5401 | |
e70236a8 JB |
5402 | /* Shouldn't happen */ |
5403 | return 0; | |
5404 | } | |
79e53945 | 5405 | |
e70236a8 JB |
5406 | static int i830_get_display_clock_speed(struct drm_device *dev) |
5407 | { | |
5408 | return 133000; | |
79e53945 JB |
5409 | } |
5410 | ||
2c07245f | 5411 | static void |
a65851af | 5412 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 5413 | { |
a65851af VS |
5414 | while (*num > DATA_LINK_M_N_MASK || |
5415 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
5416 | *num >>= 1; |
5417 | *den >>= 1; | |
5418 | } | |
5419 | } | |
5420 | ||
a65851af VS |
5421 | static void compute_m_n(unsigned int m, unsigned int n, |
5422 | uint32_t *ret_m, uint32_t *ret_n) | |
5423 | { | |
5424 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
5425 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
5426 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
5427 | } | |
5428 | ||
e69d0bc1 DV |
5429 | void |
5430 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
5431 | int pixel_clock, int link_clock, | |
5432 | struct intel_link_m_n *m_n) | |
2c07245f | 5433 | { |
e69d0bc1 | 5434 | m_n->tu = 64; |
a65851af VS |
5435 | |
5436 | compute_m_n(bits_per_pixel * pixel_clock, | |
5437 | link_clock * nlanes * 8, | |
5438 | &m_n->gmch_m, &m_n->gmch_n); | |
5439 | ||
5440 | compute_m_n(pixel_clock, link_clock, | |
5441 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
5442 | } |
5443 | ||
a7615030 CW |
5444 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
5445 | { | |
d330a953 JN |
5446 | if (i915.panel_use_ssc >= 0) |
5447 | return i915.panel_use_ssc != 0; | |
41aa3448 | 5448 | return dev_priv->vbt.lvds_use_ssc |
435793df | 5449 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
5450 | } |
5451 | ||
c65d77d8 JB |
5452 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
5453 | { | |
5454 | struct drm_device *dev = crtc->dev; | |
5455 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5456 | int refclk; | |
5457 | ||
a0c4da24 | 5458 | if (IS_VALLEYVIEW(dev)) { |
9a0ea498 | 5459 | refclk = 100000; |
a0c4da24 | 5460 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 5461 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
5462 | refclk = dev_priv->vbt.lvds_ssc_freq; |
5463 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
5464 | } else if (!IS_GEN2(dev)) { |
5465 | refclk = 96000; | |
5466 | } else { | |
5467 | refclk = 48000; | |
5468 | } | |
5469 | ||
5470 | return refclk; | |
5471 | } | |
5472 | ||
7429e9d4 | 5473 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 5474 | { |
7df00d7a | 5475 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 5476 | } |
f47709a9 | 5477 | |
7429e9d4 DV |
5478 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
5479 | { | |
5480 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
5481 | } |
5482 | ||
f47709a9 | 5483 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
a7516a05 JB |
5484 | intel_clock_t *reduced_clock) |
5485 | { | |
f47709a9 | 5486 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
5487 | u32 fp, fp2 = 0; |
5488 | ||
5489 | if (IS_PINEVIEW(dev)) { | |
7429e9d4 | 5490 | fp = pnv_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 5491 | if (reduced_clock) |
7429e9d4 | 5492 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 5493 | } else { |
7429e9d4 | 5494 | fp = i9xx_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 5495 | if (reduced_clock) |
7429e9d4 | 5496 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
5497 | } |
5498 | ||
8bcc2795 | 5499 | crtc->config.dpll_hw_state.fp0 = fp; |
a7516a05 | 5500 | |
f47709a9 DV |
5501 | crtc->lowfreq_avail = false; |
5502 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && | |
d330a953 | 5503 | reduced_clock && i915.powersave) { |
8bcc2795 | 5504 | crtc->config.dpll_hw_state.fp1 = fp2; |
f47709a9 | 5505 | crtc->lowfreq_avail = true; |
a7516a05 | 5506 | } else { |
8bcc2795 | 5507 | crtc->config.dpll_hw_state.fp1 = fp; |
a7516a05 JB |
5508 | } |
5509 | } | |
5510 | ||
5e69f97f CML |
5511 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
5512 | pipe) | |
89b667f8 JB |
5513 | { |
5514 | u32 reg_val; | |
5515 | ||
5516 | /* | |
5517 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
5518 | * and set it to a reasonable value instead. | |
5519 | */ | |
ab3c759a | 5520 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
5521 | reg_val &= 0xffffff00; |
5522 | reg_val |= 0x00000030; | |
ab3c759a | 5523 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 5524 | |
ab3c759a | 5525 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
5526 | reg_val &= 0x8cffffff; |
5527 | reg_val = 0x8c000000; | |
ab3c759a | 5528 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 5529 | |
ab3c759a | 5530 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 5531 | reg_val &= 0xffffff00; |
ab3c759a | 5532 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 5533 | |
ab3c759a | 5534 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
5535 | reg_val &= 0x00ffffff; |
5536 | reg_val |= 0xb0000000; | |
ab3c759a | 5537 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
5538 | } |
5539 | ||
b551842d DV |
5540 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
5541 | struct intel_link_m_n *m_n) | |
5542 | { | |
5543 | struct drm_device *dev = crtc->base.dev; | |
5544 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5545 | int pipe = crtc->pipe; | |
5546 | ||
e3b95f1e DV |
5547 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
5548 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
5549 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
5550 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
5551 | } |
5552 | ||
5553 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
5554 | struct intel_link_m_n *m_n, |
5555 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
5556 | { |
5557 | struct drm_device *dev = crtc->base.dev; | |
5558 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5559 | int pipe = crtc->pipe; | |
5560 | enum transcoder transcoder = crtc->config.cpu_transcoder; | |
5561 | ||
5562 | if (INTEL_INFO(dev)->gen >= 5) { | |
5563 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
5564 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
5565 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
5566 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
5567 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
5568 | * for gen < 8) and if DRRS is supported (to make sure the | |
5569 | * registers are not unnecessarily accessed). | |
5570 | */ | |
5571 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
5572 | crtc->config.has_drrs) { | |
5573 | I915_WRITE(PIPE_DATA_M2(transcoder), | |
5574 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
5575 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
5576 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
5577 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
5578 | } | |
b551842d | 5579 | } else { |
e3b95f1e DV |
5580 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
5581 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
5582 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
5583 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
5584 | } |
5585 | } | |
5586 | ||
f769cd24 | 5587 | void intel_dp_set_m_n(struct intel_crtc *crtc) |
03afc4a2 DV |
5588 | { |
5589 | if (crtc->config.has_pch_encoder) | |
5590 | intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
5591 | else | |
f769cd24 VK |
5592 | intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n, |
5593 | &crtc->config.dp_m2_n2); | |
03afc4a2 DV |
5594 | } |
5595 | ||
f47709a9 | 5596 | static void vlv_update_pll(struct intel_crtc *crtc) |
bdd4b6a6 DV |
5597 | { |
5598 | u32 dpll, dpll_md; | |
5599 | ||
5600 | /* | |
5601 | * Enable DPIO clock input. We should never disable the reference | |
5602 | * clock for pipe B, since VGA hotplug / manual detection depends | |
5603 | * on it. | |
5604 | */ | |
5605 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | | |
5606 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; | |
5607 | /* We should never disable this, set it here for state tracking */ | |
5608 | if (crtc->pipe == PIPE_B) | |
5609 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
5610 | dpll |= DPLL_VCO_ENABLE; | |
5611 | crtc->config.dpll_hw_state.dpll = dpll; | |
5612 | ||
5613 | dpll_md = (crtc->config.pixel_multiplier - 1) | |
5614 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
5615 | crtc->config.dpll_hw_state.dpll_md = dpll_md; | |
5616 | } | |
5617 | ||
5618 | static void vlv_prepare_pll(struct intel_crtc *crtc) | |
a0c4da24 | 5619 | { |
f47709a9 | 5620 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 5621 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 5622 | int pipe = crtc->pipe; |
bdd4b6a6 | 5623 | u32 mdiv; |
a0c4da24 | 5624 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 5625 | u32 coreclk, reg_val; |
a0c4da24 | 5626 | |
09153000 DV |
5627 | mutex_lock(&dev_priv->dpio_lock); |
5628 | ||
f47709a9 DV |
5629 | bestn = crtc->config.dpll.n; |
5630 | bestm1 = crtc->config.dpll.m1; | |
5631 | bestm2 = crtc->config.dpll.m2; | |
5632 | bestp1 = crtc->config.dpll.p1; | |
5633 | bestp2 = crtc->config.dpll.p2; | |
a0c4da24 | 5634 | |
89b667f8 JB |
5635 | /* See eDP HDMI DPIO driver vbios notes doc */ |
5636 | ||
5637 | /* PLL B needs special handling */ | |
bdd4b6a6 | 5638 | if (pipe == PIPE_B) |
5e69f97f | 5639 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
5640 | |
5641 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 5642 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
5643 | |
5644 | /* Disable target IRef on PLL */ | |
ab3c759a | 5645 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 5646 | reg_val &= 0x00ffffff; |
ab3c759a | 5647 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
5648 | |
5649 | /* Disable fast lock */ | |
ab3c759a | 5650 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
5651 | |
5652 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
5653 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
5654 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
5655 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 5656 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
5657 | |
5658 | /* | |
5659 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
5660 | * but we don't support that). | |
5661 | * Note: don't use the DAC post divider as it seems unstable. | |
5662 | */ | |
5663 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 5664 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 5665 | |
a0c4da24 | 5666 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 5667 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 5668 | |
89b667f8 | 5669 | /* Set HBR and RBR LPF coefficients */ |
ff9a6750 | 5670 | if (crtc->config.port_clock == 162000 || |
99750bd4 | 5671 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) || |
89b667f8 | 5672 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) |
ab3c759a | 5673 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 5674 | 0x009f0003); |
89b667f8 | 5675 | else |
ab3c759a | 5676 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
5677 | 0x00d0000f); |
5678 | ||
5679 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) || | |
5680 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) { | |
5681 | /* Use SSC source */ | |
bdd4b6a6 | 5682 | if (pipe == PIPE_A) |
ab3c759a | 5683 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5684 | 0x0df40000); |
5685 | else | |
ab3c759a | 5686 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5687 | 0x0df70000); |
5688 | } else { /* HDMI or VGA */ | |
5689 | /* Use bend source */ | |
bdd4b6a6 | 5690 | if (pipe == PIPE_A) |
ab3c759a | 5691 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5692 | 0x0df70000); |
5693 | else | |
ab3c759a | 5694 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5695 | 0x0df40000); |
5696 | } | |
a0c4da24 | 5697 | |
ab3c759a | 5698 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 JB |
5699 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
5700 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) || | |
5701 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) | |
5702 | coreclk |= 0x01000000; | |
ab3c759a | 5703 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 5704 | |
ab3c759a | 5705 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
09153000 | 5706 | mutex_unlock(&dev_priv->dpio_lock); |
a0c4da24 JB |
5707 | } |
5708 | ||
9d556c99 | 5709 | static void chv_update_pll(struct intel_crtc *crtc) |
1ae0d137 VS |
5710 | { |
5711 | crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV | | |
5712 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | | |
5713 | DPLL_VCO_ENABLE; | |
5714 | if (crtc->pipe != PIPE_A) | |
5715 | crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
5716 | ||
5717 | crtc->config.dpll_hw_state.dpll_md = | |
5718 | (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
5719 | } | |
5720 | ||
5721 | static void chv_prepare_pll(struct intel_crtc *crtc) | |
9d556c99 CML |
5722 | { |
5723 | struct drm_device *dev = crtc->base.dev; | |
5724 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5725 | int pipe = crtc->pipe; | |
5726 | int dpll_reg = DPLL(crtc->pipe); | |
5727 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
580d3811 | 5728 | u32 loopfilter, intcoeff; |
9d556c99 CML |
5729 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
5730 | int refclk; | |
5731 | ||
9d556c99 CML |
5732 | bestn = crtc->config.dpll.n; |
5733 | bestm2_frac = crtc->config.dpll.m2 & 0x3fffff; | |
5734 | bestm1 = crtc->config.dpll.m1; | |
5735 | bestm2 = crtc->config.dpll.m2 >> 22; | |
5736 | bestp1 = crtc->config.dpll.p1; | |
5737 | bestp2 = crtc->config.dpll.p2; | |
5738 | ||
5739 | /* | |
5740 | * Enable Refclk and SSC | |
5741 | */ | |
a11b0703 VS |
5742 | I915_WRITE(dpll_reg, |
5743 | crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); | |
5744 | ||
5745 | mutex_lock(&dev_priv->dpio_lock); | |
9d556c99 | 5746 | |
9d556c99 CML |
5747 | /* p1 and p2 divider */ |
5748 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
5749 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
5750 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
5751 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
5752 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
5753 | ||
5754 | /* Feedback post-divider - m2 */ | |
5755 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
5756 | ||
5757 | /* Feedback refclk divider - n and m1 */ | |
5758 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
5759 | DPIO_CHV_M1_DIV_BY_2 | | |
5760 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
5761 | ||
5762 | /* M2 fraction division */ | |
5763 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); | |
5764 | ||
5765 | /* M2 fraction division enable */ | |
5766 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), | |
5767 | DPIO_CHV_FRAC_DIV_EN | | |
5768 | (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT)); | |
5769 | ||
5770 | /* Loop filter */ | |
5771 | refclk = i9xx_get_refclk(&crtc->base, 0); | |
5772 | loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT | | |
5773 | 2 << DPIO_CHV_GAIN_CTRL_SHIFT; | |
5774 | if (refclk == 100000) | |
5775 | intcoeff = 11; | |
5776 | else if (refclk == 38400) | |
5777 | intcoeff = 10; | |
5778 | else | |
5779 | intcoeff = 9; | |
5780 | loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT; | |
5781 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); | |
5782 | ||
5783 | /* AFC Recal */ | |
5784 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
5785 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
5786 | DPIO_AFC_RECAL); | |
5787 | ||
5788 | mutex_unlock(&dev_priv->dpio_lock); | |
5789 | } | |
5790 | ||
f47709a9 DV |
5791 | static void i9xx_update_pll(struct intel_crtc *crtc, |
5792 | intel_clock_t *reduced_clock, | |
eb1cbe48 DV |
5793 | int num_connectors) |
5794 | { | |
f47709a9 | 5795 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 5796 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
5797 | u32 dpll; |
5798 | bool is_sdvo; | |
f47709a9 | 5799 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 5800 | |
f47709a9 | 5801 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 5802 | |
f47709a9 DV |
5803 | is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) || |
5804 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
5805 | |
5806 | dpll = DPLL_VGA_MODE_DIS; | |
5807 | ||
f47709a9 | 5808 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
5809 | dpll |= DPLLB_MODE_LVDS; |
5810 | else | |
5811 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 5812 | |
ef1b460d | 5813 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
198a037f DV |
5814 | dpll |= (crtc->config.pixel_multiplier - 1) |
5815 | << SDVO_MULTIPLIER_SHIFT_HIRES; | |
eb1cbe48 | 5816 | } |
198a037f DV |
5817 | |
5818 | if (is_sdvo) | |
4a33e48d | 5819 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 5820 | |
f47709a9 | 5821 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) |
4a33e48d | 5822 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
5823 | |
5824 | /* compute bitmask from p1 value */ | |
5825 | if (IS_PINEVIEW(dev)) | |
5826 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
5827 | else { | |
5828 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5829 | if (IS_G4X(dev) && reduced_clock) | |
5830 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
5831 | } | |
5832 | switch (clock->p2) { | |
5833 | case 5: | |
5834 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
5835 | break; | |
5836 | case 7: | |
5837 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
5838 | break; | |
5839 | case 10: | |
5840 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
5841 | break; | |
5842 | case 14: | |
5843 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
5844 | break; | |
5845 | } | |
5846 | if (INTEL_INFO(dev)->gen >= 4) | |
5847 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
5848 | ||
09ede541 | 5849 | if (crtc->config.sdvo_tv_clock) |
eb1cbe48 | 5850 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
f47709a9 | 5851 | else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
5852 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5853 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
5854 | else | |
5855 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5856 | ||
5857 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 DV |
5858 | crtc->config.dpll_hw_state.dpll = dpll; |
5859 | ||
eb1cbe48 | 5860 | if (INTEL_INFO(dev)->gen >= 4) { |
ef1b460d DV |
5861 | u32 dpll_md = (crtc->config.pixel_multiplier - 1) |
5862 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
8bcc2795 | 5863 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
5864 | } |
5865 | } | |
5866 | ||
f47709a9 | 5867 | static void i8xx_update_pll(struct intel_crtc *crtc, |
f47709a9 | 5868 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
5869 | int num_connectors) |
5870 | { | |
f47709a9 | 5871 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 5872 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 5873 | u32 dpll; |
f47709a9 | 5874 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 5875 | |
f47709a9 | 5876 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 5877 | |
eb1cbe48 DV |
5878 | dpll = DPLL_VGA_MODE_DIS; |
5879 | ||
f47709a9 | 5880 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
5881 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
5882 | } else { | |
5883 | if (clock->p1 == 2) | |
5884 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
5885 | else | |
5886 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5887 | if (clock->p2 == 4) | |
5888 | dpll |= PLL_P2_DIVIDE_BY_4; | |
5889 | } | |
5890 | ||
4a33e48d DV |
5891 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO)) |
5892 | dpll |= DPLL_DVO_2X_MODE; | |
5893 | ||
f47709a9 | 5894 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
5895 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5896 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
5897 | else | |
5898 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5899 | ||
5900 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 | 5901 | crtc->config.dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
5902 | } |
5903 | ||
8a654f3b | 5904 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
5905 | { |
5906 | struct drm_device *dev = intel_crtc->base.dev; | |
5907 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5908 | enum pipe pipe = intel_crtc->pipe; | |
3b117c8f | 5909 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
8a654f3b DV |
5910 | struct drm_display_mode *adjusted_mode = |
5911 | &intel_crtc->config.adjusted_mode; | |
1caea6e9 VS |
5912 | uint32_t crtc_vtotal, crtc_vblank_end; |
5913 | int vsyncshift = 0; | |
4d8a62ea DV |
5914 | |
5915 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
5916 | * the hw state checker will get angry at the mismatch. */ | |
5917 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
5918 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 5919 | |
609aeaca | 5920 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 5921 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
5922 | crtc_vtotal -= 1; |
5923 | crtc_vblank_end -= 1; | |
609aeaca VS |
5924 | |
5925 | if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO)) | |
5926 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; | |
5927 | else | |
5928 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
5929 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
5930 | if (vsyncshift < 0) |
5931 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
5932 | } |
5933 | ||
5934 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 5935 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 5936 | |
fe2b8f9d | 5937 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
5938 | (adjusted_mode->crtc_hdisplay - 1) | |
5939 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 5940 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
5941 | (adjusted_mode->crtc_hblank_start - 1) | |
5942 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 5943 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
5944 | (adjusted_mode->crtc_hsync_start - 1) | |
5945 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
5946 | ||
fe2b8f9d | 5947 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 5948 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 5949 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 5950 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 5951 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 5952 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 5953 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
5954 | (adjusted_mode->crtc_vsync_start - 1) | |
5955 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
5956 | ||
b5e508d4 PZ |
5957 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
5958 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
5959 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
5960 | * bits. */ | |
5961 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
5962 | (pipe == PIPE_B || pipe == PIPE_C)) | |
5963 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
5964 | ||
b0e77b9c PZ |
5965 | /* pipesrc controls the size that is scaled from, which should |
5966 | * always be the user's requested size. | |
5967 | */ | |
5968 | I915_WRITE(PIPESRC(pipe), | |
37327abd VS |
5969 | ((intel_crtc->config.pipe_src_w - 1) << 16) | |
5970 | (intel_crtc->config.pipe_src_h - 1)); | |
b0e77b9c PZ |
5971 | } |
5972 | ||
1bd1bd80 DV |
5973 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5974 | struct intel_crtc_config *pipe_config) | |
5975 | { | |
5976 | struct drm_device *dev = crtc->base.dev; | |
5977 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5978 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
5979 | uint32_t tmp; | |
5980 | ||
5981 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
5982 | pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; | |
5983 | pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
5984 | tmp = I915_READ(HBLANK(cpu_transcoder)); | |
5985 | pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; | |
5986 | pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
5987 | tmp = I915_READ(HSYNC(cpu_transcoder)); | |
5988 | pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; | |
5989 | pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
5990 | ||
5991 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
5992 | pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; | |
5993 | pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
5994 | tmp = I915_READ(VBLANK(cpu_transcoder)); | |
5995 | pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; | |
5996 | pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
5997 | tmp = I915_READ(VSYNC(cpu_transcoder)); | |
5998 | pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; | |
5999 | pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
6000 | ||
6001 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
6002 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; | |
6003 | pipe_config->adjusted_mode.crtc_vtotal += 1; | |
6004 | pipe_config->adjusted_mode.crtc_vblank_end += 1; | |
6005 | } | |
6006 | ||
6007 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
6008 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
6009 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
6010 | ||
6011 | pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h; | |
6012 | pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
6013 | } |
6014 | ||
f6a83288 DV |
6015 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
6016 | struct intel_crtc_config *pipe_config) | |
babea61d | 6017 | { |
f6a83288 DV |
6018 | mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay; |
6019 | mode->htotal = pipe_config->adjusted_mode.crtc_htotal; | |
6020 | mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start; | |
6021 | mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end; | |
babea61d | 6022 | |
f6a83288 DV |
6023 | mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay; |
6024 | mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal; | |
6025 | mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start; | |
6026 | mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end; | |
babea61d | 6027 | |
f6a83288 | 6028 | mode->flags = pipe_config->adjusted_mode.flags; |
babea61d | 6029 | |
f6a83288 DV |
6030 | mode->clock = pipe_config->adjusted_mode.crtc_clock; |
6031 | mode->flags |= pipe_config->adjusted_mode.flags; | |
babea61d JB |
6032 | } |
6033 | ||
84b046f3 DV |
6034 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
6035 | { | |
6036 | struct drm_device *dev = intel_crtc->base.dev; | |
6037 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6038 | uint32_t pipeconf; | |
6039 | ||
9f11a9e4 | 6040 | pipeconf = 0; |
84b046f3 | 6041 | |
67c72a12 DV |
6042 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
6043 | I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE) | |
6044 | pipeconf |= PIPECONF_ENABLE; | |
6045 | ||
cf532bb2 VS |
6046 | if (intel_crtc->config.double_wide) |
6047 | pipeconf |= PIPECONF_DOUBLE_WIDE; | |
84b046f3 | 6048 | |
ff9ce46e DV |
6049 | /* only g4x and later have fancy bpc/dither controls */ |
6050 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
ff9ce46e DV |
6051 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6052 | if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30) | |
6053 | pipeconf |= PIPECONF_DITHER_EN | | |
84b046f3 | 6054 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 6055 | |
ff9ce46e DV |
6056 | switch (intel_crtc->config.pipe_bpp) { |
6057 | case 18: | |
6058 | pipeconf |= PIPECONF_6BPC; | |
6059 | break; | |
6060 | case 24: | |
6061 | pipeconf |= PIPECONF_8BPC; | |
6062 | break; | |
6063 | case 30: | |
6064 | pipeconf |= PIPECONF_10BPC; | |
6065 | break; | |
6066 | default: | |
6067 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
6068 | BUG(); | |
84b046f3 DV |
6069 | } |
6070 | } | |
6071 | ||
6072 | if (HAS_PIPE_CXSR(dev)) { | |
6073 | if (intel_crtc->lowfreq_avail) { | |
6074 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
6075 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
6076 | } else { | |
6077 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
6078 | } |
6079 | } | |
6080 | ||
efc2cfff VS |
6081 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
6082 | if (INTEL_INFO(dev)->gen < 4 || | |
6083 | intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO)) | |
6084 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; | |
6085 | else | |
6086 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
6087 | } else | |
84b046f3 DV |
6088 | pipeconf |= PIPECONF_PROGRESSIVE; |
6089 | ||
9f11a9e4 DV |
6090 | if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range) |
6091 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; | |
9c8e09b7 | 6092 | |
84b046f3 DV |
6093 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
6094 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
6095 | } | |
6096 | ||
f564048e | 6097 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
f564048e | 6098 | int x, int y, |
94352cf9 | 6099 | struct drm_framebuffer *fb) |
79e53945 JB |
6100 | { |
6101 | struct drm_device *dev = crtc->dev; | |
6102 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6103 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
c751ce4f | 6104 | int refclk, num_connectors = 0; |
652c393a | 6105 | intel_clock_t clock, reduced_clock; |
a16af721 | 6106 | bool ok, has_reduced_clock = false; |
e9fd1c02 | 6107 | bool is_lvds = false, is_dsi = false; |
5eddb70b | 6108 | struct intel_encoder *encoder; |
d4906093 | 6109 | const intel_limit_t *limit; |
79e53945 | 6110 | |
6c2b7c12 | 6111 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5eddb70b | 6112 | switch (encoder->type) { |
79e53945 JB |
6113 | case INTEL_OUTPUT_LVDS: |
6114 | is_lvds = true; | |
6115 | break; | |
e9fd1c02 JN |
6116 | case INTEL_OUTPUT_DSI: |
6117 | is_dsi = true; | |
6118 | break; | |
79e53945 | 6119 | } |
43565a06 | 6120 | |
c751ce4f | 6121 | num_connectors++; |
79e53945 JB |
6122 | } |
6123 | ||
f2335330 | 6124 | if (is_dsi) |
5b18e57c | 6125 | return 0; |
f2335330 JN |
6126 | |
6127 | if (!intel_crtc->config.clock_set) { | |
6128 | refclk = i9xx_get_refclk(crtc, num_connectors); | |
79e53945 | 6129 | |
e9fd1c02 JN |
6130 | /* |
6131 | * Returns a set of divisors for the desired target clock with | |
6132 | * the given refclk, or FALSE. The returned values represent | |
6133 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
6134 | * 2) / p1 / p2. | |
6135 | */ | |
6136 | limit = intel_limit(crtc, refclk); | |
6137 | ok = dev_priv->display.find_dpll(limit, crtc, | |
6138 | intel_crtc->config.port_clock, | |
6139 | refclk, NULL, &clock); | |
f2335330 | 6140 | if (!ok) { |
e9fd1c02 JN |
6141 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
6142 | return -EINVAL; | |
6143 | } | |
79e53945 | 6144 | |
f2335330 JN |
6145 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
6146 | /* | |
6147 | * Ensure we match the reduced clock's P to the target | |
6148 | * clock. If the clocks don't match, we can't switch | |
6149 | * the display clock by using the FP0/FP1. In such case | |
6150 | * we will disable the LVDS downclock feature. | |
6151 | */ | |
6152 | has_reduced_clock = | |
6153 | dev_priv->display.find_dpll(limit, crtc, | |
6154 | dev_priv->lvds_downclock, | |
6155 | refclk, &clock, | |
6156 | &reduced_clock); | |
6157 | } | |
6158 | /* Compat-code for transition, will disappear. */ | |
f47709a9 DV |
6159 | intel_crtc->config.dpll.n = clock.n; |
6160 | intel_crtc->config.dpll.m1 = clock.m1; | |
6161 | intel_crtc->config.dpll.m2 = clock.m2; | |
6162 | intel_crtc->config.dpll.p1 = clock.p1; | |
6163 | intel_crtc->config.dpll.p2 = clock.p2; | |
6164 | } | |
7026d4ac | 6165 | |
e9fd1c02 | 6166 | if (IS_GEN2(dev)) { |
8a654f3b | 6167 | i8xx_update_pll(intel_crtc, |
2a8f64ca VP |
6168 | has_reduced_clock ? &reduced_clock : NULL, |
6169 | num_connectors); | |
9d556c99 CML |
6170 | } else if (IS_CHERRYVIEW(dev)) { |
6171 | chv_update_pll(intel_crtc); | |
e9fd1c02 | 6172 | } else if (IS_VALLEYVIEW(dev)) { |
f2335330 | 6173 | vlv_update_pll(intel_crtc); |
e9fd1c02 | 6174 | } else { |
f47709a9 | 6175 | i9xx_update_pll(intel_crtc, |
eb1cbe48 | 6176 | has_reduced_clock ? &reduced_clock : NULL, |
eba905b2 | 6177 | num_connectors); |
e9fd1c02 | 6178 | } |
79e53945 | 6179 | |
c8f7a0db | 6180 | return 0; |
f564048e EA |
6181 | } |
6182 | ||
2fa2fe9a DV |
6183 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
6184 | struct intel_crtc_config *pipe_config) | |
6185 | { | |
6186 | struct drm_device *dev = crtc->base.dev; | |
6187 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6188 | uint32_t tmp; | |
6189 | ||
dc9e7dec VS |
6190 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
6191 | return; | |
6192 | ||
2fa2fe9a | 6193 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
6194 | if (!(tmp & PFIT_ENABLE)) |
6195 | return; | |
2fa2fe9a | 6196 | |
06922821 | 6197 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
6198 | if (INTEL_INFO(dev)->gen < 4) { |
6199 | if (crtc->pipe != PIPE_B) | |
6200 | return; | |
2fa2fe9a DV |
6201 | } else { |
6202 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
6203 | return; | |
6204 | } | |
6205 | ||
06922821 | 6206 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
6207 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
6208 | if (INTEL_INFO(dev)->gen < 5) | |
6209 | pipe_config->gmch_pfit.lvds_border_bits = | |
6210 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
6211 | } | |
6212 | ||
acbec814 JB |
6213 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
6214 | struct intel_crtc_config *pipe_config) | |
6215 | { | |
6216 | struct drm_device *dev = crtc->base.dev; | |
6217 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6218 | int pipe = pipe_config->cpu_transcoder; | |
6219 | intel_clock_t clock; | |
6220 | u32 mdiv; | |
662c6ecb | 6221 | int refclk = 100000; |
acbec814 | 6222 | |
f573de5a SK |
6223 | /* In case of MIPI DPLL will not even be used */ |
6224 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) | |
6225 | return; | |
6226 | ||
acbec814 | 6227 | mutex_lock(&dev_priv->dpio_lock); |
ab3c759a | 6228 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
acbec814 JB |
6229 | mutex_unlock(&dev_priv->dpio_lock); |
6230 | ||
6231 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
6232 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
6233 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
6234 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
6235 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
6236 | ||
f646628b | 6237 | vlv_clock(refclk, &clock); |
acbec814 | 6238 | |
f646628b VS |
6239 | /* clock.dot is the fast clock */ |
6240 | pipe_config->port_clock = clock.dot / 5; | |
acbec814 JB |
6241 | } |
6242 | ||
1ad292b5 JB |
6243 | static void i9xx_get_plane_config(struct intel_crtc *crtc, |
6244 | struct intel_plane_config *plane_config) | |
6245 | { | |
6246 | struct drm_device *dev = crtc->base.dev; | |
6247 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6248 | u32 val, base, offset; | |
6249 | int pipe = crtc->pipe, plane = crtc->plane; | |
6250 | int fourcc, pixel_format; | |
6251 | int aligned_height; | |
6252 | ||
66e514c1 DA |
6253 | crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL); |
6254 | if (!crtc->base.primary->fb) { | |
1ad292b5 JB |
6255 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
6256 | return; | |
6257 | } | |
6258 | ||
6259 | val = I915_READ(DSPCNTR(plane)); | |
6260 | ||
6261 | if (INTEL_INFO(dev)->gen >= 4) | |
6262 | if (val & DISPPLANE_TILED) | |
6263 | plane_config->tiled = true; | |
6264 | ||
6265 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
6266 | fourcc = intel_format_to_fourcc(pixel_format); | |
66e514c1 DA |
6267 | crtc->base.primary->fb->pixel_format = fourcc; |
6268 | crtc->base.primary->fb->bits_per_pixel = | |
1ad292b5 JB |
6269 | drm_format_plane_cpp(fourcc, 0) * 8; |
6270 | ||
6271 | if (INTEL_INFO(dev)->gen >= 4) { | |
6272 | if (plane_config->tiled) | |
6273 | offset = I915_READ(DSPTILEOFF(plane)); | |
6274 | else | |
6275 | offset = I915_READ(DSPLINOFF(plane)); | |
6276 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
6277 | } else { | |
6278 | base = I915_READ(DSPADDR(plane)); | |
6279 | } | |
6280 | plane_config->base = base; | |
6281 | ||
6282 | val = I915_READ(PIPESRC(pipe)); | |
66e514c1 DA |
6283 | crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1; |
6284 | crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
6285 | |
6286 | val = I915_READ(DSPSTRIDE(pipe)); | |
026b96e2 | 6287 | crtc->base.primary->fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 6288 | |
66e514c1 | 6289 | aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, |
1ad292b5 JB |
6290 | plane_config->tiled); |
6291 | ||
1267a26b FF |
6292 | plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] * |
6293 | aligned_height); | |
1ad292b5 JB |
6294 | |
6295 | DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
66e514c1 DA |
6296 | pipe, plane, crtc->base.primary->fb->width, |
6297 | crtc->base.primary->fb->height, | |
6298 | crtc->base.primary->fb->bits_per_pixel, base, | |
6299 | crtc->base.primary->fb->pitches[0], | |
1ad292b5 JB |
6300 | plane_config->size); |
6301 | ||
6302 | } | |
6303 | ||
70b23a98 VS |
6304 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
6305 | struct intel_crtc_config *pipe_config) | |
6306 | { | |
6307 | struct drm_device *dev = crtc->base.dev; | |
6308 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6309 | int pipe = pipe_config->cpu_transcoder; | |
6310 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
6311 | intel_clock_t clock; | |
6312 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2; | |
6313 | int refclk = 100000; | |
6314 | ||
6315 | mutex_lock(&dev_priv->dpio_lock); | |
6316 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); | |
6317 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
6318 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
6319 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
6320 | mutex_unlock(&dev_priv->dpio_lock); | |
6321 | ||
6322 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
6323 | clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff); | |
6324 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; | |
6325 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
6326 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
6327 | ||
6328 | chv_clock(refclk, &clock); | |
6329 | ||
6330 | /* clock.dot is the fast clock */ | |
6331 | pipe_config->port_clock = clock.dot / 5; | |
6332 | } | |
6333 | ||
0e8ffe1b DV |
6334 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
6335 | struct intel_crtc_config *pipe_config) | |
6336 | { | |
6337 | struct drm_device *dev = crtc->base.dev; | |
6338 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6339 | uint32_t tmp; | |
6340 | ||
b5482bd0 ID |
6341 | if (!intel_display_power_enabled(dev_priv, |
6342 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
6343 | return false; | |
6344 | ||
e143a21c | 6345 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 6346 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 6347 | |
0e8ffe1b DV |
6348 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
6349 | if (!(tmp & PIPECONF_ENABLE)) | |
6350 | return false; | |
6351 | ||
42571aef VS |
6352 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
6353 | switch (tmp & PIPECONF_BPC_MASK) { | |
6354 | case PIPECONF_6BPC: | |
6355 | pipe_config->pipe_bpp = 18; | |
6356 | break; | |
6357 | case PIPECONF_8BPC: | |
6358 | pipe_config->pipe_bpp = 24; | |
6359 | break; | |
6360 | case PIPECONF_10BPC: | |
6361 | pipe_config->pipe_bpp = 30; | |
6362 | break; | |
6363 | default: | |
6364 | break; | |
6365 | } | |
6366 | } | |
6367 | ||
b5a9fa09 DV |
6368 | if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
6369 | pipe_config->limited_color_range = true; | |
6370 | ||
282740f7 VS |
6371 | if (INTEL_INFO(dev)->gen < 4) |
6372 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
6373 | ||
1bd1bd80 DV |
6374 | intel_get_pipe_timings(crtc, pipe_config); |
6375 | ||
2fa2fe9a DV |
6376 | i9xx_get_pfit_config(crtc, pipe_config); |
6377 | ||
6c49f241 DV |
6378 | if (INTEL_INFO(dev)->gen >= 4) { |
6379 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
6380 | pipe_config->pixel_multiplier = | |
6381 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
6382 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 6383 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
6384 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
6385 | tmp = I915_READ(DPLL(crtc->pipe)); | |
6386 | pipe_config->pixel_multiplier = | |
6387 | ((tmp & SDVO_MULTIPLIER_MASK) | |
6388 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
6389 | } else { | |
6390 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
6391 | * port and will be fixed up in the encoder->get_config | |
6392 | * function. */ | |
6393 | pipe_config->pixel_multiplier = 1; | |
6394 | } | |
8bcc2795 DV |
6395 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
6396 | if (!IS_VALLEYVIEW(dev)) { | |
6397 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); | |
6398 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
6399 | } else { |
6400 | /* Mask out read-only status bits. */ | |
6401 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
6402 | DPLL_PORTC_READY_MASK | | |
6403 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 6404 | } |
6c49f241 | 6405 | |
70b23a98 VS |
6406 | if (IS_CHERRYVIEW(dev)) |
6407 | chv_crtc_clock_get(crtc, pipe_config); | |
6408 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
6409 | vlv_crtc_clock_get(crtc, pipe_config); |
6410 | else | |
6411 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 6412 | |
0e8ffe1b DV |
6413 | return true; |
6414 | } | |
6415 | ||
dde86e2d | 6416 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
6417 | { |
6418 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 6419 | struct intel_encoder *encoder; |
74cfd7ac | 6420 | u32 val, final; |
13d83a67 | 6421 | bool has_lvds = false; |
199e5d79 | 6422 | bool has_cpu_edp = false; |
199e5d79 | 6423 | bool has_panel = false; |
99eb6a01 KP |
6424 | bool has_ck505 = false; |
6425 | bool can_ssc = false; | |
13d83a67 JB |
6426 | |
6427 | /* We need to take the global config into account */ | |
b2784e15 | 6428 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
6429 | switch (encoder->type) { |
6430 | case INTEL_OUTPUT_LVDS: | |
6431 | has_panel = true; | |
6432 | has_lvds = true; | |
6433 | break; | |
6434 | case INTEL_OUTPUT_EDP: | |
6435 | has_panel = true; | |
2de6905f | 6436 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
6437 | has_cpu_edp = true; |
6438 | break; | |
13d83a67 JB |
6439 | } |
6440 | } | |
6441 | ||
99eb6a01 | 6442 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 6443 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
6444 | can_ssc = has_ck505; |
6445 | } else { | |
6446 | has_ck505 = false; | |
6447 | can_ssc = true; | |
6448 | } | |
6449 | ||
2de6905f ID |
6450 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
6451 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
6452 | |
6453 | /* Ironlake: try to setup display ref clock before DPLL | |
6454 | * enabling. This is only under driver's control after | |
6455 | * PCH B stepping, previous chipset stepping should be | |
6456 | * ignoring this setting. | |
6457 | */ | |
74cfd7ac CW |
6458 | val = I915_READ(PCH_DREF_CONTROL); |
6459 | ||
6460 | /* As we must carefully and slowly disable/enable each source in turn, | |
6461 | * compute the final state we want first and check if we need to | |
6462 | * make any changes at all. | |
6463 | */ | |
6464 | final = val; | |
6465 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
6466 | if (has_ck505) | |
6467 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
6468 | else | |
6469 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
6470 | ||
6471 | final &= ~DREF_SSC_SOURCE_MASK; | |
6472 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
6473 | final &= ~DREF_SSC1_ENABLE; | |
6474 | ||
6475 | if (has_panel) { | |
6476 | final |= DREF_SSC_SOURCE_ENABLE; | |
6477 | ||
6478 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
6479 | final |= DREF_SSC1_ENABLE; | |
6480 | ||
6481 | if (has_cpu_edp) { | |
6482 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
6483 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
6484 | else | |
6485 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
6486 | } else | |
6487 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
6488 | } else { | |
6489 | final |= DREF_SSC_SOURCE_DISABLE; | |
6490 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
6491 | } | |
6492 | ||
6493 | if (final == val) | |
6494 | return; | |
6495 | ||
13d83a67 | 6496 | /* Always enable nonspread source */ |
74cfd7ac | 6497 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 6498 | |
99eb6a01 | 6499 | if (has_ck505) |
74cfd7ac | 6500 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 6501 | else |
74cfd7ac | 6502 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 6503 | |
199e5d79 | 6504 | if (has_panel) { |
74cfd7ac CW |
6505 | val &= ~DREF_SSC_SOURCE_MASK; |
6506 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 6507 | |
199e5d79 | 6508 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 6509 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 6510 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 6511 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 6512 | } else |
74cfd7ac | 6513 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
6514 | |
6515 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 6516 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
6517 | POSTING_READ(PCH_DREF_CONTROL); |
6518 | udelay(200); | |
6519 | ||
74cfd7ac | 6520 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
6521 | |
6522 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 6523 | if (has_cpu_edp) { |
99eb6a01 | 6524 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 6525 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 6526 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 6527 | } else |
74cfd7ac | 6528 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 6529 | } else |
74cfd7ac | 6530 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 6531 | |
74cfd7ac | 6532 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
6533 | POSTING_READ(PCH_DREF_CONTROL); |
6534 | udelay(200); | |
6535 | } else { | |
6536 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
6537 | ||
74cfd7ac | 6538 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
6539 | |
6540 | /* Turn off CPU output */ | |
74cfd7ac | 6541 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 6542 | |
74cfd7ac | 6543 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
6544 | POSTING_READ(PCH_DREF_CONTROL); |
6545 | udelay(200); | |
6546 | ||
6547 | /* Turn off the SSC source */ | |
74cfd7ac CW |
6548 | val &= ~DREF_SSC_SOURCE_MASK; |
6549 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
6550 | |
6551 | /* Turn off SSC1 */ | |
74cfd7ac | 6552 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 6553 | |
74cfd7ac | 6554 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
6555 | POSTING_READ(PCH_DREF_CONTROL); |
6556 | udelay(200); | |
6557 | } | |
74cfd7ac CW |
6558 | |
6559 | BUG_ON(val != final); | |
13d83a67 JB |
6560 | } |
6561 | ||
f31f2d55 | 6562 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 6563 | { |
f31f2d55 | 6564 | uint32_t tmp; |
dde86e2d | 6565 | |
0ff066a9 PZ |
6566 | tmp = I915_READ(SOUTH_CHICKEN2); |
6567 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
6568 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 6569 | |
0ff066a9 PZ |
6570 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
6571 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
6572 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 6573 | |
0ff066a9 PZ |
6574 | tmp = I915_READ(SOUTH_CHICKEN2); |
6575 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
6576 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 6577 | |
0ff066a9 PZ |
6578 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
6579 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
6580 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
6581 | } |
6582 | ||
6583 | /* WaMPhyProgramming:hsw */ | |
6584 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
6585 | { | |
6586 | uint32_t tmp; | |
dde86e2d PZ |
6587 | |
6588 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
6589 | tmp &= ~(0xFF << 24); | |
6590 | tmp |= (0x12 << 24); | |
6591 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
6592 | ||
dde86e2d PZ |
6593 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
6594 | tmp |= (1 << 11); | |
6595 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
6596 | ||
6597 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
6598 | tmp |= (1 << 11); | |
6599 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
6600 | ||
dde86e2d PZ |
6601 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
6602 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
6603 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
6604 | ||
6605 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
6606 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
6607 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
6608 | ||
0ff066a9 PZ |
6609 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
6610 | tmp &= ~(7 << 13); | |
6611 | tmp |= (5 << 13); | |
6612 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 6613 | |
0ff066a9 PZ |
6614 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
6615 | tmp &= ~(7 << 13); | |
6616 | tmp |= (5 << 13); | |
6617 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
6618 | |
6619 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
6620 | tmp &= ~0xFF; | |
6621 | tmp |= 0x1C; | |
6622 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
6623 | ||
6624 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
6625 | tmp &= ~0xFF; | |
6626 | tmp |= 0x1C; | |
6627 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
6628 | ||
6629 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
6630 | tmp &= ~(0xFF << 16); | |
6631 | tmp |= (0x1C << 16); | |
6632 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
6633 | ||
6634 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
6635 | tmp &= ~(0xFF << 16); | |
6636 | tmp |= (0x1C << 16); | |
6637 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
6638 | ||
0ff066a9 PZ |
6639 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
6640 | tmp |= (1 << 27); | |
6641 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 6642 | |
0ff066a9 PZ |
6643 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
6644 | tmp |= (1 << 27); | |
6645 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 6646 | |
0ff066a9 PZ |
6647 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
6648 | tmp &= ~(0xF << 28); | |
6649 | tmp |= (4 << 28); | |
6650 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 6651 | |
0ff066a9 PZ |
6652 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
6653 | tmp &= ~(0xF << 28); | |
6654 | tmp |= (4 << 28); | |
6655 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
6656 | } |
6657 | ||
2fa86a1f PZ |
6658 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
6659 | * Programming" based on the parameters passed: | |
6660 | * - Sequence to enable CLKOUT_DP | |
6661 | * - Sequence to enable CLKOUT_DP without spread | |
6662 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
6663 | */ | |
6664 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
6665 | bool with_fdi) | |
f31f2d55 PZ |
6666 | { |
6667 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
6668 | uint32_t reg, tmp; |
6669 | ||
6670 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
6671 | with_spread = true; | |
6672 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && | |
6673 | with_fdi, "LP PCH doesn't have FDI\n")) | |
6674 | with_fdi = false; | |
f31f2d55 PZ |
6675 | |
6676 | mutex_lock(&dev_priv->dpio_lock); | |
6677 | ||
6678 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
6679 | tmp &= ~SBI_SSCCTL_DISABLE; | |
6680 | tmp |= SBI_SSCCTL_PATHALT; | |
6681 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
6682 | ||
6683 | udelay(24); | |
6684 | ||
2fa86a1f PZ |
6685 | if (with_spread) { |
6686 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
6687 | tmp &= ~SBI_SSCCTL_PATHALT; | |
6688 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 6689 | |
2fa86a1f PZ |
6690 | if (with_fdi) { |
6691 | lpt_reset_fdi_mphy(dev_priv); | |
6692 | lpt_program_fdi_mphy(dev_priv); | |
6693 | } | |
6694 | } | |
dde86e2d | 6695 | |
2fa86a1f PZ |
6696 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
6697 | SBI_GEN0 : SBI_DBUFF0; | |
6698 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
6699 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
6700 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 DV |
6701 | |
6702 | mutex_unlock(&dev_priv->dpio_lock); | |
dde86e2d PZ |
6703 | } |
6704 | ||
47701c3b PZ |
6705 | /* Sequence to disable CLKOUT_DP */ |
6706 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
6707 | { | |
6708 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6709 | uint32_t reg, tmp; | |
6710 | ||
6711 | mutex_lock(&dev_priv->dpio_lock); | |
6712 | ||
6713 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? | |
6714 | SBI_GEN0 : SBI_DBUFF0; | |
6715 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
6716 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
6717 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
6718 | ||
6719 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
6720 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
6721 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
6722 | tmp |= SBI_SSCCTL_PATHALT; | |
6723 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
6724 | udelay(32); | |
6725 | } | |
6726 | tmp |= SBI_SSCCTL_DISABLE; | |
6727 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
6728 | } | |
6729 | ||
6730 | mutex_unlock(&dev_priv->dpio_lock); | |
6731 | } | |
6732 | ||
bf8fa3d3 PZ |
6733 | static void lpt_init_pch_refclk(struct drm_device *dev) |
6734 | { | |
bf8fa3d3 PZ |
6735 | struct intel_encoder *encoder; |
6736 | bool has_vga = false; | |
6737 | ||
b2784e15 | 6738 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
6739 | switch (encoder->type) { |
6740 | case INTEL_OUTPUT_ANALOG: | |
6741 | has_vga = true; | |
6742 | break; | |
6743 | } | |
6744 | } | |
6745 | ||
47701c3b PZ |
6746 | if (has_vga) |
6747 | lpt_enable_clkout_dp(dev, true, true); | |
6748 | else | |
6749 | lpt_disable_clkout_dp(dev); | |
bf8fa3d3 PZ |
6750 | } |
6751 | ||
dde86e2d PZ |
6752 | /* |
6753 | * Initialize reference clocks when the driver loads | |
6754 | */ | |
6755 | void intel_init_pch_refclk(struct drm_device *dev) | |
6756 | { | |
6757 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
6758 | ironlake_init_pch_refclk(dev); | |
6759 | else if (HAS_PCH_LPT(dev)) | |
6760 | lpt_init_pch_refclk(dev); | |
6761 | } | |
6762 | ||
d9d444cb JB |
6763 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
6764 | { | |
6765 | struct drm_device *dev = crtc->dev; | |
6766 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6767 | struct intel_encoder *encoder; | |
d9d444cb JB |
6768 | int num_connectors = 0; |
6769 | bool is_lvds = false; | |
6770 | ||
6c2b7c12 | 6771 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
d9d444cb JB |
6772 | switch (encoder->type) { |
6773 | case INTEL_OUTPUT_LVDS: | |
6774 | is_lvds = true; | |
6775 | break; | |
d9d444cb JB |
6776 | } |
6777 | num_connectors++; | |
6778 | } | |
6779 | ||
6780 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 6781 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 6782 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 6783 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
6784 | } |
6785 | ||
6786 | return 120000; | |
6787 | } | |
6788 | ||
6ff93609 | 6789 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 6790 | { |
c8203565 | 6791 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
6792 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6793 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
6794 | uint32_t val; |
6795 | ||
78114071 | 6796 | val = 0; |
c8203565 | 6797 | |
965e0c48 | 6798 | switch (intel_crtc->config.pipe_bpp) { |
c8203565 | 6799 | case 18: |
dfd07d72 | 6800 | val |= PIPECONF_6BPC; |
c8203565 PZ |
6801 | break; |
6802 | case 24: | |
dfd07d72 | 6803 | val |= PIPECONF_8BPC; |
c8203565 PZ |
6804 | break; |
6805 | case 30: | |
dfd07d72 | 6806 | val |= PIPECONF_10BPC; |
c8203565 PZ |
6807 | break; |
6808 | case 36: | |
dfd07d72 | 6809 | val |= PIPECONF_12BPC; |
c8203565 PZ |
6810 | break; |
6811 | default: | |
cc769b62 PZ |
6812 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
6813 | BUG(); | |
c8203565 PZ |
6814 | } |
6815 | ||
d8b32247 | 6816 | if (intel_crtc->config.dither) |
c8203565 PZ |
6817 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
6818 | ||
6ff93609 | 6819 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
6820 | val |= PIPECONF_INTERLACED_ILK; |
6821 | else | |
6822 | val |= PIPECONF_PROGRESSIVE; | |
6823 | ||
50f3b016 | 6824 | if (intel_crtc->config.limited_color_range) |
3685a8f3 | 6825 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 6826 | |
c8203565 PZ |
6827 | I915_WRITE(PIPECONF(pipe), val); |
6828 | POSTING_READ(PIPECONF(pipe)); | |
6829 | } | |
6830 | ||
86d3efce VS |
6831 | /* |
6832 | * Set up the pipe CSC unit. | |
6833 | * | |
6834 | * Currently only full range RGB to limited range RGB conversion | |
6835 | * is supported, but eventually this should handle various | |
6836 | * RGB<->YCbCr scenarios as well. | |
6837 | */ | |
50f3b016 | 6838 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
6839 | { |
6840 | struct drm_device *dev = crtc->dev; | |
6841 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6842 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6843 | int pipe = intel_crtc->pipe; | |
6844 | uint16_t coeff = 0x7800; /* 1.0 */ | |
6845 | ||
6846 | /* | |
6847 | * TODO: Check what kind of values actually come out of the pipe | |
6848 | * with these coeff/postoff values and adjust to get the best | |
6849 | * accuracy. Perhaps we even need to take the bpc value into | |
6850 | * consideration. | |
6851 | */ | |
6852 | ||
50f3b016 | 6853 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
6854 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
6855 | ||
6856 | /* | |
6857 | * GY/GU and RY/RU should be the other way around according | |
6858 | * to BSpec, but reality doesn't agree. Just set them up in | |
6859 | * a way that results in the correct picture. | |
6860 | */ | |
6861 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
6862 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
6863 | ||
6864 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
6865 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
6866 | ||
6867 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
6868 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
6869 | ||
6870 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
6871 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
6872 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
6873 | ||
6874 | if (INTEL_INFO(dev)->gen > 6) { | |
6875 | uint16_t postoff = 0; | |
6876 | ||
50f3b016 | 6877 | if (intel_crtc->config.limited_color_range) |
32cf0cb0 | 6878 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
6879 | |
6880 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
6881 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
6882 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
6883 | ||
6884 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
6885 | } else { | |
6886 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
6887 | ||
50f3b016 | 6888 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
6889 | mode |= CSC_BLACK_SCREEN_OFFSET; |
6890 | ||
6891 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
6892 | } | |
6893 | } | |
6894 | ||
6ff93609 | 6895 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 6896 | { |
756f85cf PZ |
6897 | struct drm_device *dev = crtc->dev; |
6898 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 6899 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 6900 | enum pipe pipe = intel_crtc->pipe; |
3b117c8f | 6901 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee2b0b38 PZ |
6902 | uint32_t val; |
6903 | ||
3eff4faa | 6904 | val = 0; |
ee2b0b38 | 6905 | |
756f85cf | 6906 | if (IS_HASWELL(dev) && intel_crtc->config.dither) |
ee2b0b38 PZ |
6907 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
6908 | ||
6ff93609 | 6909 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
6910 | val |= PIPECONF_INTERLACED_ILK; |
6911 | else | |
6912 | val |= PIPECONF_PROGRESSIVE; | |
6913 | ||
702e7a56 PZ |
6914 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
6915 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
6916 | |
6917 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
6918 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf PZ |
6919 | |
6920 | if (IS_BROADWELL(dev)) { | |
6921 | val = 0; | |
6922 | ||
6923 | switch (intel_crtc->config.pipe_bpp) { | |
6924 | case 18: | |
6925 | val |= PIPEMISC_DITHER_6_BPC; | |
6926 | break; | |
6927 | case 24: | |
6928 | val |= PIPEMISC_DITHER_8_BPC; | |
6929 | break; | |
6930 | case 30: | |
6931 | val |= PIPEMISC_DITHER_10_BPC; | |
6932 | break; | |
6933 | case 36: | |
6934 | val |= PIPEMISC_DITHER_12_BPC; | |
6935 | break; | |
6936 | default: | |
6937 | /* Case prevented by pipe_config_set_bpp. */ | |
6938 | BUG(); | |
6939 | } | |
6940 | ||
6941 | if (intel_crtc->config.dither) | |
6942 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; | |
6943 | ||
6944 | I915_WRITE(PIPEMISC(pipe), val); | |
6945 | } | |
ee2b0b38 PZ |
6946 | } |
6947 | ||
6591c6e4 | 6948 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
6591c6e4 PZ |
6949 | intel_clock_t *clock, |
6950 | bool *has_reduced_clock, | |
6951 | intel_clock_t *reduced_clock) | |
6952 | { | |
6953 | struct drm_device *dev = crtc->dev; | |
6954 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6955 | struct intel_encoder *intel_encoder; | |
6956 | int refclk; | |
d4906093 | 6957 | const intel_limit_t *limit; |
a16af721 | 6958 | bool ret, is_lvds = false; |
79e53945 | 6959 | |
6591c6e4 PZ |
6960 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
6961 | switch (intel_encoder->type) { | |
79e53945 JB |
6962 | case INTEL_OUTPUT_LVDS: |
6963 | is_lvds = true; | |
6964 | break; | |
79e53945 JB |
6965 | } |
6966 | } | |
6967 | ||
d9d444cb | 6968 | refclk = ironlake_get_refclk(crtc); |
79e53945 | 6969 | |
d4906093 ML |
6970 | /* |
6971 | * Returns a set of divisors for the desired target clock with the given | |
6972 | * refclk, or FALSE. The returned values represent the clock equation: | |
6973 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
6974 | */ | |
1b894b59 | 6975 | limit = intel_limit(crtc, refclk); |
ff9a6750 DV |
6976 | ret = dev_priv->display.find_dpll(limit, crtc, |
6977 | to_intel_crtc(crtc)->config.port_clock, | |
ee9300bb | 6978 | refclk, NULL, clock); |
6591c6e4 PZ |
6979 | if (!ret) |
6980 | return false; | |
cda4b7d3 | 6981 | |
ddc9003c | 6982 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
6983 | /* |
6984 | * Ensure we match the reduced clock's P to the target clock. | |
6985 | * If the clocks don't match, we can't switch the display clock | |
6986 | * by using the FP0/FP1. In such case we will disable the LVDS | |
6987 | * downclock feature. | |
6988 | */ | |
ee9300bb DV |
6989 | *has_reduced_clock = |
6990 | dev_priv->display.find_dpll(limit, crtc, | |
6991 | dev_priv->lvds_downclock, | |
6992 | refclk, clock, | |
6993 | reduced_clock); | |
652c393a | 6994 | } |
61e9653f | 6995 | |
6591c6e4 PZ |
6996 | return true; |
6997 | } | |
6998 | ||
d4b1931c PZ |
6999 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
7000 | { | |
7001 | /* | |
7002 | * Account for spread spectrum to avoid | |
7003 | * oversubscribing the link. Max center spread | |
7004 | * is 2.5%; use 5% for safety's sake. | |
7005 | */ | |
7006 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 7007 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
7008 | } |
7009 | ||
7429e9d4 | 7010 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 7011 | { |
7429e9d4 | 7012 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
7013 | } |
7014 | ||
de13a2e3 | 7015 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
7429e9d4 | 7016 | u32 *fp, |
9a7c7890 | 7017 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 7018 | { |
de13a2e3 | 7019 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
7020 | struct drm_device *dev = crtc->dev; |
7021 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de13a2e3 PZ |
7022 | struct intel_encoder *intel_encoder; |
7023 | uint32_t dpll; | |
6cc5f341 | 7024 | int factor, num_connectors = 0; |
09ede541 | 7025 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 7026 | |
de13a2e3 PZ |
7027 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
7028 | switch (intel_encoder->type) { | |
79e53945 JB |
7029 | case INTEL_OUTPUT_LVDS: |
7030 | is_lvds = true; | |
7031 | break; | |
7032 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 7033 | case INTEL_OUTPUT_HDMI: |
79e53945 | 7034 | is_sdvo = true; |
79e53945 | 7035 | break; |
79e53945 | 7036 | } |
43565a06 | 7037 | |
c751ce4f | 7038 | num_connectors++; |
79e53945 | 7039 | } |
79e53945 | 7040 | |
c1858123 | 7041 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
7042 | factor = 21; |
7043 | if (is_lvds) { | |
7044 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 7045 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 7046 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 7047 | factor = 25; |
09ede541 | 7048 | } else if (intel_crtc->config.sdvo_tv_clock) |
8febb297 | 7049 | factor = 20; |
c1858123 | 7050 | |
7429e9d4 | 7051 | if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor)) |
7d0ac5b7 | 7052 | *fp |= FP_CB_TUNE; |
2c07245f | 7053 | |
9a7c7890 DV |
7054 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
7055 | *fp2 |= FP_CB_TUNE; | |
7056 | ||
5eddb70b | 7057 | dpll = 0; |
2c07245f | 7058 | |
a07d6787 EA |
7059 | if (is_lvds) |
7060 | dpll |= DPLLB_MODE_LVDS; | |
7061 | else | |
7062 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 7063 | |
ef1b460d DV |
7064 | dpll |= (intel_crtc->config.pixel_multiplier - 1) |
7065 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
198a037f DV |
7066 | |
7067 | if (is_sdvo) | |
4a33e48d | 7068 | dpll |= DPLL_SDVO_HIGH_SPEED; |
9566e9af | 7069 | if (intel_crtc->config.has_dp_encoder) |
4a33e48d | 7070 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 7071 | |
a07d6787 | 7072 | /* compute bitmask from p1 value */ |
7429e9d4 | 7073 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 7074 | /* also FPA1 */ |
7429e9d4 | 7075 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 7076 | |
7429e9d4 | 7077 | switch (intel_crtc->config.dpll.p2) { |
a07d6787 EA |
7078 | case 5: |
7079 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7080 | break; | |
7081 | case 7: | |
7082 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7083 | break; | |
7084 | case 10: | |
7085 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7086 | break; | |
7087 | case 14: | |
7088 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7089 | break; | |
79e53945 JB |
7090 | } |
7091 | ||
b4c09f3b | 7092 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 7093 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
7094 | else |
7095 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7096 | ||
959e16d6 | 7097 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
7098 | } |
7099 | ||
7100 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, | |
de13a2e3 PZ |
7101 | int x, int y, |
7102 | struct drm_framebuffer *fb) | |
7103 | { | |
7104 | struct drm_device *dev = crtc->dev; | |
de13a2e3 | 7105 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
de13a2e3 PZ |
7106 | int num_connectors = 0; |
7107 | intel_clock_t clock, reduced_clock; | |
cbbab5bd | 7108 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 7109 | bool ok, has_reduced_clock = false; |
8b47047b | 7110 | bool is_lvds = false; |
de13a2e3 | 7111 | struct intel_encoder *encoder; |
e2b78267 | 7112 | struct intel_shared_dpll *pll; |
de13a2e3 PZ |
7113 | |
7114 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
7115 | switch (encoder->type) { | |
7116 | case INTEL_OUTPUT_LVDS: | |
7117 | is_lvds = true; | |
7118 | break; | |
de13a2e3 PZ |
7119 | } |
7120 | ||
7121 | num_connectors++; | |
a07d6787 | 7122 | } |
79e53945 | 7123 | |
5dc5298b PZ |
7124 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
7125 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 7126 | |
ff9a6750 | 7127 | ok = ironlake_compute_clocks(crtc, &clock, |
de13a2e3 | 7128 | &has_reduced_clock, &reduced_clock); |
ee9300bb | 7129 | if (!ok && !intel_crtc->config.clock_set) { |
de13a2e3 PZ |
7130 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
7131 | return -EINVAL; | |
79e53945 | 7132 | } |
f47709a9 DV |
7133 | /* Compat-code for transition, will disappear. */ |
7134 | if (!intel_crtc->config.clock_set) { | |
7135 | intel_crtc->config.dpll.n = clock.n; | |
7136 | intel_crtc->config.dpll.m1 = clock.m1; | |
7137 | intel_crtc->config.dpll.m2 = clock.m2; | |
7138 | intel_crtc->config.dpll.p1 = clock.p1; | |
7139 | intel_crtc->config.dpll.p2 = clock.p2; | |
7140 | } | |
79e53945 | 7141 | |
5dc5298b | 7142 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
8b47047b | 7143 | if (intel_crtc->config.has_pch_encoder) { |
7429e9d4 | 7144 | fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll); |
cbbab5bd | 7145 | if (has_reduced_clock) |
7429e9d4 | 7146 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 7147 | |
7429e9d4 | 7148 | dpll = ironlake_compute_dpll(intel_crtc, |
cbbab5bd DV |
7149 | &fp, &reduced_clock, |
7150 | has_reduced_clock ? &fp2 : NULL); | |
7151 | ||
959e16d6 | 7152 | intel_crtc->config.dpll_hw_state.dpll = dpll; |
66e985c0 DV |
7153 | intel_crtc->config.dpll_hw_state.fp0 = fp; |
7154 | if (has_reduced_clock) | |
7155 | intel_crtc->config.dpll_hw_state.fp1 = fp2; | |
7156 | else | |
7157 | intel_crtc->config.dpll_hw_state.fp1 = fp; | |
7158 | ||
b89a1d39 | 7159 | pll = intel_get_shared_dpll(intel_crtc); |
ee7b9f93 | 7160 | if (pll == NULL) { |
84f44ce7 | 7161 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
29407aab | 7162 | pipe_name(intel_crtc->pipe)); |
4b645f14 JB |
7163 | return -EINVAL; |
7164 | } | |
ee7b9f93 | 7165 | } else |
e72f9fbf | 7166 | intel_put_shared_dpll(intel_crtc); |
79e53945 | 7167 | |
d330a953 | 7168 | if (is_lvds && has_reduced_clock && i915.powersave) |
bcd644e0 DV |
7169 | intel_crtc->lowfreq_avail = true; |
7170 | else | |
7171 | intel_crtc->lowfreq_avail = false; | |
e2b78267 | 7172 | |
c8f7a0db | 7173 | return 0; |
79e53945 JB |
7174 | } |
7175 | ||
eb14cb74 VS |
7176 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
7177 | struct intel_link_m_n *m_n) | |
7178 | { | |
7179 | struct drm_device *dev = crtc->base.dev; | |
7180 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7181 | enum pipe pipe = crtc->pipe; | |
7182 | ||
7183 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
7184 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
7185 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
7186 | & ~TU_SIZE_MASK; | |
7187 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
7188 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
7189 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7190 | } | |
7191 | ||
7192 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
7193 | enum transcoder transcoder, | |
b95af8be VK |
7194 | struct intel_link_m_n *m_n, |
7195 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
7196 | { |
7197 | struct drm_device *dev = crtc->base.dev; | |
7198 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 7199 | enum pipe pipe = crtc->pipe; |
72419203 | 7200 | |
eb14cb74 VS |
7201 | if (INTEL_INFO(dev)->gen >= 5) { |
7202 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
7203 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
7204 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
7205 | & ~TU_SIZE_MASK; | |
7206 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
7207 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
7208 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
7209 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
7210 | * gen < 8) and if DRRS is supported (to make sure the | |
7211 | * registers are not unnecessarily read). | |
7212 | */ | |
7213 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
7214 | crtc->config.has_drrs) { | |
7215 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); | |
7216 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
7217 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
7218 | & ~TU_SIZE_MASK; | |
7219 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
7220 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
7221 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7222 | } | |
eb14cb74 VS |
7223 | } else { |
7224 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
7225 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
7226 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
7227 | & ~TU_SIZE_MASK; | |
7228 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
7229 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
7230 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7231 | } | |
7232 | } | |
7233 | ||
7234 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
7235 | struct intel_crtc_config *pipe_config) | |
7236 | { | |
7237 | if (crtc->config.has_pch_encoder) | |
7238 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); | |
7239 | else | |
7240 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
7241 | &pipe_config->dp_m_n, |
7242 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 7243 | } |
72419203 | 7244 | |
eb14cb74 VS |
7245 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
7246 | struct intel_crtc_config *pipe_config) | |
7247 | { | |
7248 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 7249 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
7250 | } |
7251 | ||
2fa2fe9a DV |
7252 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
7253 | struct intel_crtc_config *pipe_config) | |
7254 | { | |
7255 | struct drm_device *dev = crtc->base.dev; | |
7256 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7257 | uint32_t tmp; | |
7258 | ||
7259 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
7260 | ||
7261 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 7262 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
7263 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
7264 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
7265 | |
7266 | /* We currently do not free assignements of panel fitters on | |
7267 | * ivb/hsw (since we don't use the higher upscaling modes which | |
7268 | * differentiates them) so just WARN about this case for now. */ | |
7269 | if (IS_GEN7(dev)) { | |
7270 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
7271 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
7272 | } | |
2fa2fe9a | 7273 | } |
79e53945 JB |
7274 | } |
7275 | ||
4c6baa59 JB |
7276 | static void ironlake_get_plane_config(struct intel_crtc *crtc, |
7277 | struct intel_plane_config *plane_config) | |
7278 | { | |
7279 | struct drm_device *dev = crtc->base.dev; | |
7280 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7281 | u32 val, base, offset; | |
7282 | int pipe = crtc->pipe, plane = crtc->plane; | |
7283 | int fourcc, pixel_format; | |
7284 | int aligned_height; | |
7285 | ||
66e514c1 DA |
7286 | crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL); |
7287 | if (!crtc->base.primary->fb) { | |
4c6baa59 JB |
7288 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7289 | return; | |
7290 | } | |
7291 | ||
7292 | val = I915_READ(DSPCNTR(plane)); | |
7293 | ||
7294 | if (INTEL_INFO(dev)->gen >= 4) | |
7295 | if (val & DISPPLANE_TILED) | |
7296 | plane_config->tiled = true; | |
7297 | ||
7298 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
7299 | fourcc = intel_format_to_fourcc(pixel_format); | |
66e514c1 DA |
7300 | crtc->base.primary->fb->pixel_format = fourcc; |
7301 | crtc->base.primary->fb->bits_per_pixel = | |
4c6baa59 JB |
7302 | drm_format_plane_cpp(fourcc, 0) * 8; |
7303 | ||
7304 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
7305 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
7306 | offset = I915_READ(DSPOFFSET(plane)); | |
7307 | } else { | |
7308 | if (plane_config->tiled) | |
7309 | offset = I915_READ(DSPTILEOFF(plane)); | |
7310 | else | |
7311 | offset = I915_READ(DSPLINOFF(plane)); | |
7312 | } | |
7313 | plane_config->base = base; | |
7314 | ||
7315 | val = I915_READ(PIPESRC(pipe)); | |
66e514c1 DA |
7316 | crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1; |
7317 | crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
7318 | |
7319 | val = I915_READ(DSPSTRIDE(pipe)); | |
026b96e2 | 7320 | crtc->base.primary->fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 7321 | |
66e514c1 | 7322 | aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, |
4c6baa59 JB |
7323 | plane_config->tiled); |
7324 | ||
1267a26b FF |
7325 | plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] * |
7326 | aligned_height); | |
4c6baa59 JB |
7327 | |
7328 | DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
66e514c1 DA |
7329 | pipe, plane, crtc->base.primary->fb->width, |
7330 | crtc->base.primary->fb->height, | |
7331 | crtc->base.primary->fb->bits_per_pixel, base, | |
7332 | crtc->base.primary->fb->pitches[0], | |
4c6baa59 JB |
7333 | plane_config->size); |
7334 | } | |
7335 | ||
0e8ffe1b DV |
7336 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
7337 | struct intel_crtc_config *pipe_config) | |
7338 | { | |
7339 | struct drm_device *dev = crtc->base.dev; | |
7340 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7341 | uint32_t tmp; | |
7342 | ||
930e8c9e PZ |
7343 | if (!intel_display_power_enabled(dev_priv, |
7344 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
7345 | return false; | |
7346 | ||
e143a21c | 7347 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 7348 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 7349 | |
0e8ffe1b DV |
7350 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
7351 | if (!(tmp & PIPECONF_ENABLE)) | |
7352 | return false; | |
7353 | ||
42571aef VS |
7354 | switch (tmp & PIPECONF_BPC_MASK) { |
7355 | case PIPECONF_6BPC: | |
7356 | pipe_config->pipe_bpp = 18; | |
7357 | break; | |
7358 | case PIPECONF_8BPC: | |
7359 | pipe_config->pipe_bpp = 24; | |
7360 | break; | |
7361 | case PIPECONF_10BPC: | |
7362 | pipe_config->pipe_bpp = 30; | |
7363 | break; | |
7364 | case PIPECONF_12BPC: | |
7365 | pipe_config->pipe_bpp = 36; | |
7366 | break; | |
7367 | default: | |
7368 | break; | |
7369 | } | |
7370 | ||
b5a9fa09 DV |
7371 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
7372 | pipe_config->limited_color_range = true; | |
7373 | ||
ab9412ba | 7374 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
7375 | struct intel_shared_dpll *pll; |
7376 | ||
88adfff1 DV |
7377 | pipe_config->has_pch_encoder = true; |
7378 | ||
627eb5a3 DV |
7379 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
7380 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
7381 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
7382 | |
7383 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 7384 | |
c0d43d62 | 7385 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
7386 | pipe_config->shared_dpll = |
7387 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
7388 | } else { |
7389 | tmp = I915_READ(PCH_DPLL_SEL); | |
7390 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
7391 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
7392 | else | |
7393 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
7394 | } | |
66e985c0 DV |
7395 | |
7396 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
7397 | ||
7398 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
7399 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
7400 | |
7401 | tmp = pipe_config->dpll_hw_state.dpll; | |
7402 | pipe_config->pixel_multiplier = | |
7403 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
7404 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
7405 | |
7406 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
7407 | } else { |
7408 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
7409 | } |
7410 | ||
1bd1bd80 DV |
7411 | intel_get_pipe_timings(crtc, pipe_config); |
7412 | ||
2fa2fe9a DV |
7413 | ironlake_get_pfit_config(crtc, pipe_config); |
7414 | ||
0e8ffe1b DV |
7415 | return true; |
7416 | } | |
7417 | ||
be256dc7 PZ |
7418 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
7419 | { | |
7420 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 7421 | struct intel_crtc *crtc; |
be256dc7 | 7422 | |
d3fcc808 | 7423 | for_each_intel_crtc(dev, crtc) |
798183c5 | 7424 | WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
7425 | pipe_name(crtc->pipe)); |
7426 | ||
7427 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); | |
8cc3e169 DV |
7428 | WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); |
7429 | WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); | |
7430 | WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
be256dc7 PZ |
7431 | WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
7432 | WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
7433 | "CPU PWM1 enabled\n"); | |
c5107b87 PZ |
7434 | if (IS_HASWELL(dev)) |
7435 | WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, | |
7436 | "CPU PWM2 enabled\n"); | |
be256dc7 PZ |
7437 | WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
7438 | "PCH PWM1 enabled\n"); | |
7439 | WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, | |
7440 | "Utility pin enabled\n"); | |
7441 | WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); | |
7442 | ||
9926ada1 PZ |
7443 | /* |
7444 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
7445 | * interrupts remain enabled. We used to check for that, but since it's | |
7446 | * gen-specific and since we only disable LCPLL after we fully disable | |
7447 | * the interrupts, the check below should be enough. | |
7448 | */ | |
9df7575f | 7449 | WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
7450 | } |
7451 | ||
9ccd5aeb PZ |
7452 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
7453 | { | |
7454 | struct drm_device *dev = dev_priv->dev; | |
7455 | ||
7456 | if (IS_HASWELL(dev)) | |
7457 | return I915_READ(D_COMP_HSW); | |
7458 | else | |
7459 | return I915_READ(D_COMP_BDW); | |
7460 | } | |
7461 | ||
3c4c9b81 PZ |
7462 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
7463 | { | |
7464 | struct drm_device *dev = dev_priv->dev; | |
7465 | ||
7466 | if (IS_HASWELL(dev)) { | |
7467 | mutex_lock(&dev_priv->rps.hw_lock); | |
7468 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
7469 | val)) | |
f475dadf | 7470 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
7471 | mutex_unlock(&dev_priv->rps.hw_lock); |
7472 | } else { | |
9ccd5aeb PZ |
7473 | I915_WRITE(D_COMP_BDW, val); |
7474 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 7475 | } |
be256dc7 PZ |
7476 | } |
7477 | ||
7478 | /* | |
7479 | * This function implements pieces of two sequences from BSpec: | |
7480 | * - Sequence for display software to disable LCPLL | |
7481 | * - Sequence for display software to allow package C8+ | |
7482 | * The steps implemented here are just the steps that actually touch the LCPLL | |
7483 | * register. Callers should take care of disabling all the display engine | |
7484 | * functions, doing the mode unset, fixing interrupts, etc. | |
7485 | */ | |
6ff58d53 PZ |
7486 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
7487 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
7488 | { |
7489 | uint32_t val; | |
7490 | ||
7491 | assert_can_disable_lcpll(dev_priv); | |
7492 | ||
7493 | val = I915_READ(LCPLL_CTL); | |
7494 | ||
7495 | if (switch_to_fclk) { | |
7496 | val |= LCPLL_CD_SOURCE_FCLK; | |
7497 | I915_WRITE(LCPLL_CTL, val); | |
7498 | ||
7499 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
7500 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
7501 | DRM_ERROR("Switching to FCLK failed\n"); | |
7502 | ||
7503 | val = I915_READ(LCPLL_CTL); | |
7504 | } | |
7505 | ||
7506 | val |= LCPLL_PLL_DISABLE; | |
7507 | I915_WRITE(LCPLL_CTL, val); | |
7508 | POSTING_READ(LCPLL_CTL); | |
7509 | ||
7510 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
7511 | DRM_ERROR("LCPLL still locked\n"); | |
7512 | ||
9ccd5aeb | 7513 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 7514 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 7515 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
7516 | ndelay(100); |
7517 | ||
9ccd5aeb PZ |
7518 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
7519 | 1)) | |
be256dc7 PZ |
7520 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
7521 | ||
7522 | if (allow_power_down) { | |
7523 | val = I915_READ(LCPLL_CTL); | |
7524 | val |= LCPLL_POWER_DOWN_ALLOW; | |
7525 | I915_WRITE(LCPLL_CTL, val); | |
7526 | POSTING_READ(LCPLL_CTL); | |
7527 | } | |
7528 | } | |
7529 | ||
7530 | /* | |
7531 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
7532 | * source. | |
7533 | */ | |
6ff58d53 | 7534 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
7535 | { |
7536 | uint32_t val; | |
a8a8bd54 | 7537 | unsigned long irqflags; |
be256dc7 PZ |
7538 | |
7539 | val = I915_READ(LCPLL_CTL); | |
7540 | ||
7541 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
7542 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
7543 | return; | |
7544 | ||
a8a8bd54 PZ |
7545 | /* |
7546 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
7547 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
7548 | * | |
7549 | * The other problem is that hsw_restore_lcpll() is called as part of | |
7550 | * the runtime PM resume sequence, so we can't just call | |
7551 | * gen6_gt_force_wake_get() because that function calls | |
7552 | * intel_runtime_pm_get(), and we can't change the runtime PM refcount | |
7553 | * while we are on the resume sequence. So to solve this problem we have | |
7554 | * to call special forcewake code that doesn't touch runtime PM and | |
7555 | * doesn't enable the forcewake delayed work. | |
7556 | */ | |
7557 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
7558 | if (dev_priv->uncore.forcewake_count++ == 0) | |
7559 | dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL); | |
7560 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
215733fa | 7561 | |
be256dc7 PZ |
7562 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
7563 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
7564 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 7565 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
7566 | } |
7567 | ||
9ccd5aeb | 7568 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
7569 | val |= D_COMP_COMP_FORCE; |
7570 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 7571 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
7572 | |
7573 | val = I915_READ(LCPLL_CTL); | |
7574 | val &= ~LCPLL_PLL_DISABLE; | |
7575 | I915_WRITE(LCPLL_CTL, val); | |
7576 | ||
7577 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
7578 | DRM_ERROR("LCPLL not locked yet\n"); | |
7579 | ||
7580 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
7581 | val = I915_READ(LCPLL_CTL); | |
7582 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
7583 | I915_WRITE(LCPLL_CTL, val); | |
7584 | ||
7585 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
7586 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
7587 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
7588 | } | |
215733fa | 7589 | |
a8a8bd54 PZ |
7590 | /* See the big comment above. */ |
7591 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
7592 | if (--dev_priv->uncore.forcewake_count == 0) | |
7593 | dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL); | |
7594 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
be256dc7 PZ |
7595 | } |
7596 | ||
765dab67 PZ |
7597 | /* |
7598 | * Package states C8 and deeper are really deep PC states that can only be | |
7599 | * reached when all the devices on the system allow it, so even if the graphics | |
7600 | * device allows PC8+, it doesn't mean the system will actually get to these | |
7601 | * states. Our driver only allows PC8+ when going into runtime PM. | |
7602 | * | |
7603 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
7604 | * well is disabled and most interrupts are disabled, and these are also | |
7605 | * requirements for runtime PM. When these conditions are met, we manually do | |
7606 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
7607 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
7608 | * hang the machine. | |
7609 | * | |
7610 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
7611 | * the state of some registers, so when we come back from PC8+ we need to | |
7612 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
7613 | * need to take care of the registers kept by RC6. Notice that this happens even | |
7614 | * if we don't put the device in PCI D3 state (which is what currently happens | |
7615 | * because of the runtime PM support). | |
7616 | * | |
7617 | * For more, read "Display Sequences for Package C8" on the hardware | |
7618 | * documentation. | |
7619 | */ | |
a14cb6fc | 7620 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 7621 | { |
c67a470b PZ |
7622 | struct drm_device *dev = dev_priv->dev; |
7623 | uint32_t val; | |
7624 | ||
c67a470b PZ |
7625 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
7626 | ||
c67a470b PZ |
7627 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
7628 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
7629 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
7630 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
7631 | } | |
7632 | ||
7633 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
7634 | hsw_disable_lcpll(dev_priv, true, true); |
7635 | } | |
7636 | ||
a14cb6fc | 7637 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
7638 | { |
7639 | struct drm_device *dev = dev_priv->dev; | |
7640 | uint32_t val; | |
7641 | ||
c67a470b PZ |
7642 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
7643 | ||
7644 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
7645 | lpt_init_pch_refclk(dev); |
7646 | ||
7647 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
7648 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
7649 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
7650 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
7651 | } | |
7652 | ||
7653 | intel_prepare_ddi(dev); | |
c67a470b PZ |
7654 | } |
7655 | ||
9a952a0d PZ |
7656 | static void snb_modeset_global_resources(struct drm_device *dev) |
7657 | { | |
7658 | modeset_update_crtc_power_domains(dev); | |
7659 | } | |
7660 | ||
4f074129 ID |
7661 | static void haswell_modeset_global_resources(struct drm_device *dev) |
7662 | { | |
da723569 | 7663 | modeset_update_crtc_power_domains(dev); |
d6dd9eb1 DV |
7664 | } |
7665 | ||
09b4ddf9 | 7666 | static int haswell_crtc_mode_set(struct drm_crtc *crtc, |
09b4ddf9 PZ |
7667 | int x, int y, |
7668 | struct drm_framebuffer *fb) | |
7669 | { | |
09b4ddf9 | 7670 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
09b4ddf9 | 7671 | |
566b734a | 7672 | if (!intel_ddi_pll_select(intel_crtc)) |
6441ab5f | 7673 | return -EINVAL; |
716c2e55 | 7674 | |
644cef34 DV |
7675 | intel_crtc->lowfreq_avail = false; |
7676 | ||
c8f7a0db | 7677 | return 0; |
79e53945 JB |
7678 | } |
7679 | ||
7d2c8175 DL |
7680 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
7681 | enum port port, | |
7682 | struct intel_crtc_config *pipe_config) | |
7683 | { | |
7684 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); | |
7685 | ||
7686 | switch (pipe_config->ddi_pll_sel) { | |
7687 | case PORT_CLK_SEL_WRPLL1: | |
7688 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; | |
7689 | break; | |
7690 | case PORT_CLK_SEL_WRPLL2: | |
7691 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; | |
7692 | break; | |
7693 | } | |
7694 | } | |
7695 | ||
26804afd DV |
7696 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
7697 | struct intel_crtc_config *pipe_config) | |
7698 | { | |
7699 | struct drm_device *dev = crtc->base.dev; | |
7700 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 7701 | struct intel_shared_dpll *pll; |
26804afd DV |
7702 | enum port port; |
7703 | uint32_t tmp; | |
7704 | ||
7705 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
7706 | ||
7707 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
7708 | ||
7d2c8175 | 7709 | haswell_get_ddi_pll(dev_priv, port, pipe_config); |
9cd86933 | 7710 | |
d452c5b6 DV |
7711 | if (pipe_config->shared_dpll >= 0) { |
7712 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
7713 | ||
7714 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
7715 | &pipe_config->dpll_hw_state)); | |
7716 | } | |
7717 | ||
26804afd DV |
7718 | /* |
7719 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
7720 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
7721 | * the PCH transcoder is on. | |
7722 | */ | |
7723 | if ((port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
7724 | pipe_config->has_pch_encoder = true; | |
7725 | ||
7726 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
7727 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
7728 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
7729 | ||
7730 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
7731 | } | |
7732 | } | |
7733 | ||
0e8ffe1b DV |
7734 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
7735 | struct intel_crtc_config *pipe_config) | |
7736 | { | |
7737 | struct drm_device *dev = crtc->base.dev; | |
7738 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 7739 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
7740 | uint32_t tmp; |
7741 | ||
b5482bd0 ID |
7742 | if (!intel_display_power_enabled(dev_priv, |
7743 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
7744 | return false; | |
7745 | ||
e143a21c | 7746 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
7747 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
7748 | ||
eccb140b DV |
7749 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
7750 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
7751 | enum pipe trans_edp_pipe; | |
7752 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
7753 | default: | |
7754 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
7755 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
7756 | case TRANS_DDI_EDP_INPUT_A_ON: | |
7757 | trans_edp_pipe = PIPE_A; | |
7758 | break; | |
7759 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
7760 | trans_edp_pipe = PIPE_B; | |
7761 | break; | |
7762 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
7763 | trans_edp_pipe = PIPE_C; | |
7764 | break; | |
7765 | } | |
7766 | ||
7767 | if (trans_edp_pipe == crtc->pipe) | |
7768 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
7769 | } | |
7770 | ||
da7e29bd | 7771 | if (!intel_display_power_enabled(dev_priv, |
eccb140b | 7772 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
7773 | return false; |
7774 | ||
eccb140b | 7775 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
7776 | if (!(tmp & PIPECONF_ENABLE)) |
7777 | return false; | |
7778 | ||
26804afd | 7779 | haswell_get_ddi_port_state(crtc, pipe_config); |
627eb5a3 | 7780 | |
1bd1bd80 DV |
7781 | intel_get_pipe_timings(crtc, pipe_config); |
7782 | ||
2fa2fe9a | 7783 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
da7e29bd | 7784 | if (intel_display_power_enabled(dev_priv, pfit_domain)) |
2fa2fe9a | 7785 | ironlake_get_pfit_config(crtc, pipe_config); |
88adfff1 | 7786 | |
e59150dc JB |
7787 | if (IS_HASWELL(dev)) |
7788 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
7789 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 7790 | |
6c49f241 DV |
7791 | pipe_config->pixel_multiplier = 1; |
7792 | ||
0e8ffe1b DV |
7793 | return true; |
7794 | } | |
7795 | ||
1a91510d JN |
7796 | static struct { |
7797 | int clock; | |
7798 | u32 config; | |
7799 | } hdmi_audio_clock[] = { | |
7800 | { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, | |
7801 | { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ | |
7802 | { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, | |
7803 | { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, | |
7804 | { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, | |
7805 | { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, | |
7806 | { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, | |
7807 | { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, | |
7808 | { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, | |
7809 | { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, | |
7810 | }; | |
7811 | ||
7812 | /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ | |
7813 | static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode) | |
7814 | { | |
7815 | int i; | |
7816 | ||
7817 | for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { | |
7818 | if (mode->clock == hdmi_audio_clock[i].clock) | |
7819 | break; | |
7820 | } | |
7821 | ||
7822 | if (i == ARRAY_SIZE(hdmi_audio_clock)) { | |
7823 | DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock); | |
7824 | i = 1; | |
7825 | } | |
7826 | ||
7827 | DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", | |
7828 | hdmi_audio_clock[i].clock, | |
7829 | hdmi_audio_clock[i].config); | |
7830 | ||
7831 | return hdmi_audio_clock[i].config; | |
7832 | } | |
7833 | ||
3a9627f4 WF |
7834 | static bool intel_eld_uptodate(struct drm_connector *connector, |
7835 | int reg_eldv, uint32_t bits_eldv, | |
7836 | int reg_elda, uint32_t bits_elda, | |
7837 | int reg_edid) | |
7838 | { | |
7839 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7840 | uint8_t *eld = connector->eld; | |
7841 | uint32_t i; | |
7842 | ||
7843 | i = I915_READ(reg_eldv); | |
7844 | i &= bits_eldv; | |
7845 | ||
7846 | if (!eld[0]) | |
7847 | return !i; | |
7848 | ||
7849 | if (!i) | |
7850 | return false; | |
7851 | ||
7852 | i = I915_READ(reg_elda); | |
7853 | i &= ~bits_elda; | |
7854 | I915_WRITE(reg_elda, i); | |
7855 | ||
7856 | for (i = 0; i < eld[2]; i++) | |
7857 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) | |
7858 | return false; | |
7859 | ||
7860 | return true; | |
7861 | } | |
7862 | ||
e0dac65e | 7863 | static void g4x_write_eld(struct drm_connector *connector, |
34427052 JN |
7864 | struct drm_crtc *crtc, |
7865 | struct drm_display_mode *mode) | |
e0dac65e WF |
7866 | { |
7867 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7868 | uint8_t *eld = connector->eld; | |
7869 | uint32_t eldv; | |
7870 | uint32_t len; | |
7871 | uint32_t i; | |
7872 | ||
7873 | i = I915_READ(G4X_AUD_VID_DID); | |
7874 | ||
7875 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) | |
7876 | eldv = G4X_ELDV_DEVCL_DEVBLC; | |
7877 | else | |
7878 | eldv = G4X_ELDV_DEVCTG; | |
7879 | ||
3a9627f4 WF |
7880 | if (intel_eld_uptodate(connector, |
7881 | G4X_AUD_CNTL_ST, eldv, | |
7882 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, | |
7883 | G4X_HDMIW_HDMIEDID)) | |
7884 | return; | |
7885 | ||
e0dac65e WF |
7886 | i = I915_READ(G4X_AUD_CNTL_ST); |
7887 | i &= ~(eldv | G4X_ELD_ADDR); | |
7888 | len = (i >> 9) & 0x1f; /* ELD buffer size */ | |
7889 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
7890 | ||
7891 | if (!eld[0]) | |
7892 | return; | |
7893 | ||
7894 | len = min_t(uint8_t, eld[2], len); | |
7895 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7896 | for (i = 0; i < len; i++) | |
7897 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); | |
7898 | ||
7899 | i = I915_READ(G4X_AUD_CNTL_ST); | |
7900 | i |= eldv; | |
7901 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
7902 | } | |
7903 | ||
83358c85 | 7904 | static void haswell_write_eld(struct drm_connector *connector, |
34427052 JN |
7905 | struct drm_crtc *crtc, |
7906 | struct drm_display_mode *mode) | |
83358c85 WX |
7907 | { |
7908 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7909 | uint8_t *eld = connector->eld; | |
83358c85 WX |
7910 | uint32_t eldv; |
7911 | uint32_t i; | |
7912 | int len; | |
7913 | int pipe = to_intel_crtc(crtc)->pipe; | |
7914 | int tmp; | |
7915 | ||
7916 | int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); | |
7917 | int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); | |
7918 | int aud_config = HSW_AUD_CFG(pipe); | |
7919 | int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD; | |
7920 | ||
83358c85 WX |
7921 | /* Audio output enable */ |
7922 | DRM_DEBUG_DRIVER("HDMI audio: enable codec\n"); | |
7923 | tmp = I915_READ(aud_cntrl_st2); | |
7924 | tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); | |
7925 | I915_WRITE(aud_cntrl_st2, tmp); | |
c7905792 | 7926 | POSTING_READ(aud_cntrl_st2); |
83358c85 | 7927 | |
c7905792 | 7928 | assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe); |
83358c85 WX |
7929 | |
7930 | /* Set ELD valid state */ | |
7931 | tmp = I915_READ(aud_cntrl_st2); | |
7e7cb34f | 7932 | DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp); |
83358c85 WX |
7933 | tmp |= (AUDIO_ELD_VALID_A << (pipe * 4)); |
7934 | I915_WRITE(aud_cntrl_st2, tmp); | |
7935 | tmp = I915_READ(aud_cntrl_st2); | |
7e7cb34f | 7936 | DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp); |
83358c85 WX |
7937 | |
7938 | /* Enable HDMI mode */ | |
7939 | tmp = I915_READ(aud_config); | |
7e7cb34f | 7940 | DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp); |
83358c85 WX |
7941 | /* clear N_programing_enable and N_value_index */ |
7942 | tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE); | |
7943 | I915_WRITE(aud_config, tmp); | |
7944 | ||
7945 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); | |
7946 | ||
7947 | eldv = AUDIO_ELD_VALID_A << (pipe * 4); | |
7948 | ||
7949 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { | |
7950 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
7951 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
7952 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ | |
1a91510d JN |
7953 | } else { |
7954 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); | |
7955 | } | |
83358c85 WX |
7956 | |
7957 | if (intel_eld_uptodate(connector, | |
7958 | aud_cntrl_st2, eldv, | |
7959 | aud_cntl_st, IBX_ELD_ADDRESS, | |
7960 | hdmiw_hdmiedid)) | |
7961 | return; | |
7962 | ||
7963 | i = I915_READ(aud_cntrl_st2); | |
7964 | i &= ~eldv; | |
7965 | I915_WRITE(aud_cntrl_st2, i); | |
7966 | ||
7967 | if (!eld[0]) | |
7968 | return; | |
7969 | ||
7970 | i = I915_READ(aud_cntl_st); | |
7971 | i &= ~IBX_ELD_ADDRESS; | |
7972 | I915_WRITE(aud_cntl_st, i); | |
7973 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ | |
7974 | DRM_DEBUG_DRIVER("port num:%d\n", i); | |
7975 | ||
7976 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
7977 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7978 | for (i = 0; i < len; i++) | |
7979 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
7980 | ||
7981 | i = I915_READ(aud_cntrl_st2); | |
7982 | i |= eldv; | |
7983 | I915_WRITE(aud_cntrl_st2, i); | |
7984 | ||
7985 | } | |
7986 | ||
e0dac65e | 7987 | static void ironlake_write_eld(struct drm_connector *connector, |
34427052 JN |
7988 | struct drm_crtc *crtc, |
7989 | struct drm_display_mode *mode) | |
e0dac65e WF |
7990 | { |
7991 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7992 | uint8_t *eld = connector->eld; | |
7993 | uint32_t eldv; | |
7994 | uint32_t i; | |
7995 | int len; | |
7996 | int hdmiw_hdmiedid; | |
b6daa025 | 7997 | int aud_config; |
e0dac65e WF |
7998 | int aud_cntl_st; |
7999 | int aud_cntrl_st2; | |
9b138a83 | 8000 | int pipe = to_intel_crtc(crtc)->pipe; |
e0dac65e | 8001 | |
b3f33cbf | 8002 | if (HAS_PCH_IBX(connector->dev)) { |
9b138a83 WX |
8003 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
8004 | aud_config = IBX_AUD_CFG(pipe); | |
8005 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); | |
1202b4c6 | 8006 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
9ca2fe73 ML |
8007 | } else if (IS_VALLEYVIEW(connector->dev)) { |
8008 | hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); | |
8009 | aud_config = VLV_AUD_CFG(pipe); | |
8010 | aud_cntl_st = VLV_AUD_CNTL_ST(pipe); | |
8011 | aud_cntrl_st2 = VLV_AUD_CNTL_ST2; | |
e0dac65e | 8012 | } else { |
9b138a83 WX |
8013 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); |
8014 | aud_config = CPT_AUD_CFG(pipe); | |
8015 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); | |
1202b4c6 | 8016 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
e0dac65e WF |
8017 | } |
8018 | ||
9b138a83 | 8019 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
e0dac65e | 8020 | |
9ca2fe73 ML |
8021 | if (IS_VALLEYVIEW(connector->dev)) { |
8022 | struct intel_encoder *intel_encoder; | |
8023 | struct intel_digital_port *intel_dig_port; | |
8024 | ||
8025 | intel_encoder = intel_attached_encoder(connector); | |
8026 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
8027 | i = intel_dig_port->port; | |
8028 | } else { | |
8029 | i = I915_READ(aud_cntl_st); | |
8030 | i = (i >> 29) & DIP_PORT_SEL_MASK; | |
8031 | /* DIP_Port_Select, 0x1 = PortB */ | |
8032 | } | |
8033 | ||
e0dac65e WF |
8034 | if (!i) { |
8035 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); | |
8036 | /* operate blindly on all ports */ | |
1202b4c6 WF |
8037 | eldv = IBX_ELD_VALIDB; |
8038 | eldv |= IBX_ELD_VALIDB << 4; | |
8039 | eldv |= IBX_ELD_VALIDB << 8; | |
e0dac65e | 8040 | } else { |
2582a850 | 8041 | DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i)); |
1202b4c6 | 8042 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
e0dac65e WF |
8043 | } |
8044 | ||
3a9627f4 WF |
8045 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
8046 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
8047 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
b6daa025 | 8048 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
1a91510d JN |
8049 | } else { |
8050 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); | |
8051 | } | |
e0dac65e | 8052 | |
3a9627f4 WF |
8053 | if (intel_eld_uptodate(connector, |
8054 | aud_cntrl_st2, eldv, | |
8055 | aud_cntl_st, IBX_ELD_ADDRESS, | |
8056 | hdmiw_hdmiedid)) | |
8057 | return; | |
8058 | ||
e0dac65e WF |
8059 | i = I915_READ(aud_cntrl_st2); |
8060 | i &= ~eldv; | |
8061 | I915_WRITE(aud_cntrl_st2, i); | |
8062 | ||
8063 | if (!eld[0]) | |
8064 | return; | |
8065 | ||
e0dac65e | 8066 | i = I915_READ(aud_cntl_st); |
1202b4c6 | 8067 | i &= ~IBX_ELD_ADDRESS; |
e0dac65e WF |
8068 | I915_WRITE(aud_cntl_st, i); |
8069 | ||
8070 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
8071 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
8072 | for (i = 0; i < len; i++) | |
8073 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
8074 | ||
8075 | i = I915_READ(aud_cntrl_st2); | |
8076 | i |= eldv; | |
8077 | I915_WRITE(aud_cntrl_st2, i); | |
8078 | } | |
8079 | ||
8080 | void intel_write_eld(struct drm_encoder *encoder, | |
8081 | struct drm_display_mode *mode) | |
8082 | { | |
8083 | struct drm_crtc *crtc = encoder->crtc; | |
8084 | struct drm_connector *connector; | |
8085 | struct drm_device *dev = encoder->dev; | |
8086 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8087 | ||
8088 | connector = drm_select_eld(encoder, mode); | |
8089 | if (!connector) | |
8090 | return; | |
8091 | ||
8092 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", | |
8093 | connector->base.id, | |
c23cc417 | 8094 | connector->name, |
e0dac65e | 8095 | connector->encoder->base.id, |
8e329a03 | 8096 | connector->encoder->name); |
e0dac65e WF |
8097 | |
8098 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; | |
8099 | ||
8100 | if (dev_priv->display.write_eld) | |
34427052 | 8101 | dev_priv->display.write_eld(connector, crtc, mode); |
e0dac65e WF |
8102 | } |
8103 | ||
560b85bb CW |
8104 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
8105 | { | |
8106 | struct drm_device *dev = crtc->dev; | |
8107 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8108 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 8109 | uint32_t cntl = 0, size = 0; |
560b85bb | 8110 | |
dc41c154 VS |
8111 | if (base) { |
8112 | unsigned int width = intel_crtc->cursor_width; | |
8113 | unsigned int height = intel_crtc->cursor_height; | |
8114 | unsigned int stride = roundup_pow_of_two(width) * 4; | |
8115 | ||
8116 | switch (stride) { | |
8117 | default: | |
8118 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
8119 | width, stride); | |
8120 | stride = 256; | |
8121 | /* fallthrough */ | |
8122 | case 256: | |
8123 | case 512: | |
8124 | case 1024: | |
8125 | case 2048: | |
8126 | break; | |
4b0e333e CW |
8127 | } |
8128 | ||
dc41c154 VS |
8129 | cntl |= CURSOR_ENABLE | |
8130 | CURSOR_GAMMA_ENABLE | | |
8131 | CURSOR_FORMAT_ARGB | | |
8132 | CURSOR_STRIDE(stride); | |
8133 | ||
8134 | size = (height << 12) | width; | |
4b0e333e | 8135 | } |
560b85bb | 8136 | |
dc41c154 VS |
8137 | if (intel_crtc->cursor_cntl != 0 && |
8138 | (intel_crtc->cursor_base != base || | |
8139 | intel_crtc->cursor_size != size || | |
8140 | intel_crtc->cursor_cntl != cntl)) { | |
8141 | /* On these chipsets we can only modify the base/size/stride | |
8142 | * whilst the cursor is disabled. | |
8143 | */ | |
8144 | I915_WRITE(_CURACNTR, 0); | |
4b0e333e | 8145 | POSTING_READ(_CURACNTR); |
dc41c154 | 8146 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 8147 | } |
560b85bb | 8148 | |
dc41c154 | 8149 | if (intel_crtc->cursor_base != base) |
9db4a9c7 | 8150 | I915_WRITE(_CURABASE, base); |
4726e0b0 | 8151 | |
dc41c154 VS |
8152 | if (intel_crtc->cursor_size != size) { |
8153 | I915_WRITE(CURSIZE, size); | |
8154 | intel_crtc->cursor_size = size; | |
4b0e333e | 8155 | } |
560b85bb | 8156 | |
4b0e333e | 8157 | if (intel_crtc->cursor_cntl != cntl) { |
4b0e333e CW |
8158 | I915_WRITE(_CURACNTR, cntl); |
8159 | POSTING_READ(_CURACNTR); | |
4b0e333e | 8160 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 8161 | } |
560b85bb CW |
8162 | } |
8163 | ||
560b85bb | 8164 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
65a21cd6 JB |
8165 | { |
8166 | struct drm_device *dev = crtc->dev; | |
8167 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8168 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8169 | int pipe = intel_crtc->pipe; | |
4b0e333e CW |
8170 | uint32_t cntl; |
8171 | ||
8172 | cntl = 0; | |
8173 | if (base) { | |
8174 | cntl = MCURSOR_GAMMA_ENABLE; | |
8175 | switch (intel_crtc->cursor_width) { | |
4726e0b0 SK |
8176 | case 64: |
8177 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
8178 | break; | |
8179 | case 128: | |
8180 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
8181 | break; | |
8182 | case 256: | |
8183 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
8184 | break; | |
8185 | default: | |
8186 | WARN_ON(1); | |
8187 | return; | |
65a21cd6 | 8188 | } |
4b0e333e | 8189 | cntl |= pipe << 28; /* Connect to correct pipe */ |
4b0e333e CW |
8190 | } |
8191 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
8192 | cntl |= CURSOR_PIPE_CSC_ENABLE; | |
65a21cd6 | 8193 | |
4b0e333e CW |
8194 | if (intel_crtc->cursor_cntl != cntl) { |
8195 | I915_WRITE(CURCNTR(pipe), cntl); | |
8196 | POSTING_READ(CURCNTR(pipe)); | |
8197 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 8198 | } |
4b0e333e | 8199 | |
65a21cd6 | 8200 | /* and commit changes on next vblank */ |
5efb3e28 VS |
8201 | I915_WRITE(CURBASE(pipe), base); |
8202 | POSTING_READ(CURBASE(pipe)); | |
65a21cd6 JB |
8203 | } |
8204 | ||
cda4b7d3 | 8205 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
8206 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
8207 | bool on) | |
cda4b7d3 CW |
8208 | { |
8209 | struct drm_device *dev = crtc->dev; | |
8210 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8211 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8212 | int pipe = intel_crtc->pipe; | |
3d7d6510 MR |
8213 | int x = crtc->cursor_x; |
8214 | int y = crtc->cursor_y; | |
d6e4db15 | 8215 | u32 base = 0, pos = 0; |
cda4b7d3 | 8216 | |
d6e4db15 | 8217 | if (on) |
cda4b7d3 | 8218 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 8219 | |
d6e4db15 VS |
8220 | if (x >= intel_crtc->config.pipe_src_w) |
8221 | base = 0; | |
8222 | ||
8223 | if (y >= intel_crtc->config.pipe_src_h) | |
cda4b7d3 CW |
8224 | base = 0; |
8225 | ||
8226 | if (x < 0) { | |
efc9064e | 8227 | if (x + intel_crtc->cursor_width <= 0) |
cda4b7d3 CW |
8228 | base = 0; |
8229 | ||
8230 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
8231 | x = -x; | |
8232 | } | |
8233 | pos |= x << CURSOR_X_SHIFT; | |
8234 | ||
8235 | if (y < 0) { | |
efc9064e | 8236 | if (y + intel_crtc->cursor_height <= 0) |
cda4b7d3 CW |
8237 | base = 0; |
8238 | ||
8239 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
8240 | y = -y; | |
8241 | } | |
8242 | pos |= y << CURSOR_Y_SHIFT; | |
8243 | ||
4b0e333e | 8244 | if (base == 0 && intel_crtc->cursor_base == 0) |
cda4b7d3 CW |
8245 | return; |
8246 | ||
5efb3e28 VS |
8247 | I915_WRITE(CURPOS(pipe), pos); |
8248 | ||
8ac54669 | 8249 | if (IS_845G(dev) || IS_I865G(dev)) |
5efb3e28 VS |
8250 | i845_update_cursor(crtc, base); |
8251 | else | |
8252 | i9xx_update_cursor(crtc, base); | |
4b0e333e | 8253 | intel_crtc->cursor_base = base; |
cda4b7d3 CW |
8254 | } |
8255 | ||
dc41c154 VS |
8256 | static bool cursor_size_ok(struct drm_device *dev, |
8257 | uint32_t width, uint32_t height) | |
8258 | { | |
8259 | if (width == 0 || height == 0) | |
8260 | return false; | |
8261 | ||
8262 | /* | |
8263 | * 845g/865g are special in that they are only limited by | |
8264 | * the width of their cursors, the height is arbitrary up to | |
8265 | * the precision of the register. Everything else requires | |
8266 | * square cursors, limited to a few power-of-two sizes. | |
8267 | */ | |
8268 | if (IS_845G(dev) || IS_I865G(dev)) { | |
8269 | if ((width & 63) != 0) | |
8270 | return false; | |
8271 | ||
8272 | if (width > (IS_845G(dev) ? 64 : 512)) | |
8273 | return false; | |
8274 | ||
8275 | if (height > 1023) | |
8276 | return false; | |
8277 | } else { | |
8278 | switch (width | height) { | |
8279 | case 256: | |
8280 | case 128: | |
8281 | if (IS_GEN2(dev)) | |
8282 | return false; | |
8283 | case 64: | |
8284 | break; | |
8285 | default: | |
8286 | return false; | |
8287 | } | |
8288 | } | |
8289 | ||
8290 | return true; | |
8291 | } | |
8292 | ||
e3287951 MR |
8293 | /* |
8294 | * intel_crtc_cursor_set_obj - Set cursor to specified GEM object | |
8295 | * | |
8296 | * Note that the object's reference will be consumed if the update fails. If | |
8297 | * the update succeeds, the reference of the old object (if any) will be | |
8298 | * consumed. | |
8299 | */ | |
8300 | static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc, | |
8301 | struct drm_i915_gem_object *obj, | |
8302 | uint32_t width, uint32_t height) | |
79e53945 JB |
8303 | { |
8304 | struct drm_device *dev = crtc->dev; | |
79e53945 | 8305 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
a071fa00 | 8306 | enum pipe pipe = intel_crtc->pipe; |
dc41c154 | 8307 | unsigned old_width, stride; |
cda4b7d3 | 8308 | uint32_t addr; |
3f8bc370 | 8309 | int ret; |
79e53945 | 8310 | |
79e53945 | 8311 | /* if we want to turn off the cursor ignore width and height */ |
e3287951 | 8312 | if (!obj) { |
28c97730 | 8313 | DRM_DEBUG_KMS("cursor off\n"); |
3f8bc370 | 8314 | addr = 0; |
5004417d | 8315 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 8316 | goto finish; |
79e53945 JB |
8317 | } |
8318 | ||
4726e0b0 | 8319 | /* Check for which cursor types we support */ |
dc41c154 | 8320 | if (!cursor_size_ok(dev, width, height)) { |
4726e0b0 | 8321 | DRM_DEBUG("Cursor dimension not supported\n"); |
79e53945 JB |
8322 | return -EINVAL; |
8323 | } | |
8324 | ||
dc41c154 VS |
8325 | stride = roundup_pow_of_two(width) * 4; |
8326 | if (obj->base.size < stride * height) { | |
e3287951 | 8327 | DRM_DEBUG_KMS("buffer is too small\n"); |
34b8686e DA |
8328 | ret = -ENOMEM; |
8329 | goto fail; | |
79e53945 JB |
8330 | } |
8331 | ||
71acb5eb | 8332 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 8333 | mutex_lock(&dev->struct_mutex); |
3d13ef2e | 8334 | if (!INTEL_INFO(dev)->cursor_needs_physical) { |
693db184 CW |
8335 | unsigned alignment; |
8336 | ||
d9e86c0e | 8337 | if (obj->tiling_mode) { |
3b25b31f | 8338 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
d9e86c0e CW |
8339 | ret = -EINVAL; |
8340 | goto fail_locked; | |
8341 | } | |
8342 | ||
693db184 CW |
8343 | /* Note that the w/a also requires 2 PTE of padding following |
8344 | * the bo. We currently fill all unused PTE with the shadow | |
8345 | * page and so we should always have valid PTE following the | |
8346 | * cursor preventing the VT-d warning. | |
8347 | */ | |
8348 | alignment = 0; | |
8349 | if (need_vtd_wa(dev)) | |
8350 | alignment = 64*1024; | |
8351 | ||
8352 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); | |
e7b526bb | 8353 | if (ret) { |
3b25b31f | 8354 | DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n"); |
2da3b9b9 | 8355 | goto fail_locked; |
e7b526bb CW |
8356 | } |
8357 | ||
d9e86c0e CW |
8358 | ret = i915_gem_object_put_fence(obj); |
8359 | if (ret) { | |
3b25b31f | 8360 | DRM_DEBUG_KMS("failed to release fence for cursor"); |
d9e86c0e CW |
8361 | goto fail_unpin; |
8362 | } | |
8363 | ||
f343c5f6 | 8364 | addr = i915_gem_obj_ggtt_offset(obj); |
71acb5eb | 8365 | } else { |
6eeefaf3 | 8366 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
00731155 | 8367 | ret = i915_gem_object_attach_phys(obj, align); |
71acb5eb | 8368 | if (ret) { |
3b25b31f | 8369 | DRM_DEBUG_KMS("failed to attach phys object\n"); |
7f9872e0 | 8370 | goto fail_locked; |
71acb5eb | 8371 | } |
00731155 | 8372 | addr = obj->phys_handle->busaddr; |
3f8bc370 KH |
8373 | } |
8374 | ||
3f8bc370 | 8375 | finish: |
3f8bc370 | 8376 | if (intel_crtc->cursor_bo) { |
00731155 | 8377 | if (!INTEL_INFO(dev)->cursor_needs_physical) |
cc98b413 | 8378 | i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo); |
3f8bc370 | 8379 | } |
80824003 | 8380 | |
a071fa00 DV |
8381 | i915_gem_track_fb(intel_crtc->cursor_bo, obj, |
8382 | INTEL_FRONTBUFFER_CURSOR(pipe)); | |
7f9872e0 | 8383 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 | 8384 | |
64f962e3 CW |
8385 | old_width = intel_crtc->cursor_width; |
8386 | ||
3f8bc370 | 8387 | intel_crtc->cursor_addr = addr; |
05394f39 | 8388 | intel_crtc->cursor_bo = obj; |
cda4b7d3 CW |
8389 | intel_crtc->cursor_width = width; |
8390 | intel_crtc->cursor_height = height; | |
8391 | ||
64f962e3 CW |
8392 | if (intel_crtc->active) { |
8393 | if (old_width != width) | |
8394 | intel_update_watermarks(crtc); | |
f2f5f771 | 8395 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); |
64f962e3 | 8396 | } |
3f8bc370 | 8397 | |
f99d7069 DV |
8398 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe)); |
8399 | ||
79e53945 | 8400 | return 0; |
e7b526bb | 8401 | fail_unpin: |
cc98b413 | 8402 | i915_gem_object_unpin_from_display_plane(obj); |
7f9872e0 | 8403 | fail_locked: |
34b8686e | 8404 | mutex_unlock(&dev->struct_mutex); |
bc9025bd | 8405 | fail: |
05394f39 | 8406 | drm_gem_object_unreference_unlocked(&obj->base); |
34b8686e | 8407 | return ret; |
79e53945 JB |
8408 | } |
8409 | ||
79e53945 | 8410 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 8411 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 8412 | { |
7203425a | 8413 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 8414 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 8415 | |
7203425a | 8416 | for (i = start; i < end; i++) { |
79e53945 JB |
8417 | intel_crtc->lut_r[i] = red[i] >> 8; |
8418 | intel_crtc->lut_g[i] = green[i] >> 8; | |
8419 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
8420 | } | |
8421 | ||
8422 | intel_crtc_load_lut(crtc); | |
8423 | } | |
8424 | ||
79e53945 JB |
8425 | /* VESA 640x480x72Hz mode to set on the pipe */ |
8426 | static struct drm_display_mode load_detect_mode = { | |
8427 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
8428 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
8429 | }; | |
8430 | ||
a8bb6818 DV |
8431 | struct drm_framebuffer * |
8432 | __intel_framebuffer_create(struct drm_device *dev, | |
8433 | struct drm_mode_fb_cmd2 *mode_cmd, | |
8434 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
8435 | { |
8436 | struct intel_framebuffer *intel_fb; | |
8437 | int ret; | |
8438 | ||
8439 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
8440 | if (!intel_fb) { | |
8441 | drm_gem_object_unreference_unlocked(&obj->base); | |
8442 | return ERR_PTR(-ENOMEM); | |
8443 | } | |
8444 | ||
8445 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
8446 | if (ret) |
8447 | goto err; | |
d2dff872 CW |
8448 | |
8449 | return &intel_fb->base; | |
dd4916c5 DV |
8450 | err: |
8451 | drm_gem_object_unreference_unlocked(&obj->base); | |
8452 | kfree(intel_fb); | |
8453 | ||
8454 | return ERR_PTR(ret); | |
d2dff872 CW |
8455 | } |
8456 | ||
b5ea642a | 8457 | static struct drm_framebuffer * |
a8bb6818 DV |
8458 | intel_framebuffer_create(struct drm_device *dev, |
8459 | struct drm_mode_fb_cmd2 *mode_cmd, | |
8460 | struct drm_i915_gem_object *obj) | |
8461 | { | |
8462 | struct drm_framebuffer *fb; | |
8463 | int ret; | |
8464 | ||
8465 | ret = i915_mutex_lock_interruptible(dev); | |
8466 | if (ret) | |
8467 | return ERR_PTR(ret); | |
8468 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
8469 | mutex_unlock(&dev->struct_mutex); | |
8470 | ||
8471 | return fb; | |
8472 | } | |
8473 | ||
d2dff872 CW |
8474 | static u32 |
8475 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
8476 | { | |
8477 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
8478 | return ALIGN(pitch, 64); | |
8479 | } | |
8480 | ||
8481 | static u32 | |
8482 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
8483 | { | |
8484 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 8485 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
8486 | } |
8487 | ||
8488 | static struct drm_framebuffer * | |
8489 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
8490 | struct drm_display_mode *mode, | |
8491 | int depth, int bpp) | |
8492 | { | |
8493 | struct drm_i915_gem_object *obj; | |
0fed39bd | 8494 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
8495 | |
8496 | obj = i915_gem_alloc_object(dev, | |
8497 | intel_framebuffer_size_for_mode(mode, bpp)); | |
8498 | if (obj == NULL) | |
8499 | return ERR_PTR(-ENOMEM); | |
8500 | ||
8501 | mode_cmd.width = mode->hdisplay; | |
8502 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
8503 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
8504 | bpp); | |
5ca0c34a | 8505 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
8506 | |
8507 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
8508 | } | |
8509 | ||
8510 | static struct drm_framebuffer * | |
8511 | mode_fits_in_fbdev(struct drm_device *dev, | |
8512 | struct drm_display_mode *mode) | |
8513 | { | |
4520f53a | 8514 | #ifdef CONFIG_DRM_I915_FBDEV |
d2dff872 CW |
8515 | struct drm_i915_private *dev_priv = dev->dev_private; |
8516 | struct drm_i915_gem_object *obj; | |
8517 | struct drm_framebuffer *fb; | |
8518 | ||
4c0e5528 | 8519 | if (!dev_priv->fbdev) |
d2dff872 CW |
8520 | return NULL; |
8521 | ||
4c0e5528 | 8522 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
8523 | return NULL; |
8524 | ||
4c0e5528 DV |
8525 | obj = dev_priv->fbdev->fb->obj; |
8526 | BUG_ON(!obj); | |
8527 | ||
8bcd4553 | 8528 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
8529 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
8530 | fb->bits_per_pixel)) | |
d2dff872 CW |
8531 | return NULL; |
8532 | ||
01f2c773 | 8533 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
8534 | return NULL; |
8535 | ||
8536 | return fb; | |
4520f53a DV |
8537 | #else |
8538 | return NULL; | |
8539 | #endif | |
d2dff872 CW |
8540 | } |
8541 | ||
d2434ab7 | 8542 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 8543 | struct drm_display_mode *mode, |
51fd371b RC |
8544 | struct intel_load_detect_pipe *old, |
8545 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
8546 | { |
8547 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
8548 | struct intel_encoder *intel_encoder = |
8549 | intel_attached_encoder(connector); | |
79e53945 | 8550 | struct drm_crtc *possible_crtc; |
4ef69c7a | 8551 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
8552 | struct drm_crtc *crtc = NULL; |
8553 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 8554 | struct drm_framebuffer *fb; |
51fd371b RC |
8555 | struct drm_mode_config *config = &dev->mode_config; |
8556 | int ret, i = -1; | |
79e53945 | 8557 | |
d2dff872 | 8558 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 8559 | connector->base.id, connector->name, |
8e329a03 | 8560 | encoder->base.id, encoder->name); |
d2dff872 | 8561 | |
51fd371b RC |
8562 | retry: |
8563 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
8564 | if (ret) | |
8565 | goto fail_unlock; | |
6e9f798d | 8566 | |
79e53945 JB |
8567 | /* |
8568 | * Algorithm gets a little messy: | |
7a5e4805 | 8569 | * |
79e53945 JB |
8570 | * - if the connector already has an assigned crtc, use it (but make |
8571 | * sure it's on first) | |
7a5e4805 | 8572 | * |
79e53945 JB |
8573 | * - try to find the first unused crtc that can drive this connector, |
8574 | * and use that if we find one | |
79e53945 JB |
8575 | */ |
8576 | ||
8577 | /* See if we already have a CRTC for this connector */ | |
8578 | if (encoder->crtc) { | |
8579 | crtc = encoder->crtc; | |
8261b191 | 8580 | |
51fd371b RC |
8581 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
8582 | if (ret) | |
8583 | goto fail_unlock; | |
7b24056b | 8584 | |
24218aac | 8585 | old->dpms_mode = connector->dpms; |
8261b191 CW |
8586 | old->load_detect_temp = false; |
8587 | ||
8588 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
8589 | if (connector->dpms != DRM_MODE_DPMS_ON) |
8590 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 8591 | |
7173188d | 8592 | return true; |
79e53945 JB |
8593 | } |
8594 | ||
8595 | /* Find an unused one (if possible) */ | |
70e1e0ec | 8596 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
8597 | i++; |
8598 | if (!(encoder->possible_crtcs & (1 << i))) | |
8599 | continue; | |
a459249c VS |
8600 | if (possible_crtc->enabled) |
8601 | continue; | |
8602 | /* This can occur when applying the pipe A quirk on resume. */ | |
8603 | if (to_intel_crtc(possible_crtc)->new_enabled) | |
8604 | continue; | |
8605 | ||
8606 | crtc = possible_crtc; | |
8607 | break; | |
79e53945 JB |
8608 | } |
8609 | ||
8610 | /* | |
8611 | * If we didn't find an unused CRTC, don't use any. | |
8612 | */ | |
8613 | if (!crtc) { | |
7173188d | 8614 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
51fd371b | 8615 | goto fail_unlock; |
79e53945 JB |
8616 | } |
8617 | ||
51fd371b RC |
8618 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
8619 | if (ret) | |
8620 | goto fail_unlock; | |
fc303101 DV |
8621 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
8622 | to_intel_connector(connector)->new_encoder = intel_encoder; | |
79e53945 JB |
8623 | |
8624 | intel_crtc = to_intel_crtc(crtc); | |
412b61d8 VS |
8625 | intel_crtc->new_enabled = true; |
8626 | intel_crtc->new_config = &intel_crtc->config; | |
24218aac | 8627 | old->dpms_mode = connector->dpms; |
8261b191 | 8628 | old->load_detect_temp = true; |
d2dff872 | 8629 | old->release_fb = NULL; |
79e53945 | 8630 | |
6492711d CW |
8631 | if (!mode) |
8632 | mode = &load_detect_mode; | |
79e53945 | 8633 | |
d2dff872 CW |
8634 | /* We need a framebuffer large enough to accommodate all accesses |
8635 | * that the plane may generate whilst we perform load detection. | |
8636 | * We can not rely on the fbcon either being present (we get called | |
8637 | * during its initialisation to detect all boot displays, or it may | |
8638 | * not even exist) or that it is large enough to satisfy the | |
8639 | * requested mode. | |
8640 | */ | |
94352cf9 DV |
8641 | fb = mode_fits_in_fbdev(dev, mode); |
8642 | if (fb == NULL) { | |
d2dff872 | 8643 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
8644 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
8645 | old->release_fb = fb; | |
d2dff872 CW |
8646 | } else |
8647 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 8648 | if (IS_ERR(fb)) { |
d2dff872 | 8649 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 8650 | goto fail; |
79e53945 | 8651 | } |
79e53945 | 8652 | |
c0c36b94 | 8653 | if (intel_set_mode(crtc, mode, 0, 0, fb)) { |
6492711d | 8654 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
8655 | if (old->release_fb) |
8656 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 8657 | goto fail; |
79e53945 | 8658 | } |
7173188d | 8659 | |
79e53945 | 8660 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 8661 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 8662 | return true; |
412b61d8 VS |
8663 | |
8664 | fail: | |
8665 | intel_crtc->new_enabled = crtc->enabled; | |
8666 | if (intel_crtc->new_enabled) | |
8667 | intel_crtc->new_config = &intel_crtc->config; | |
8668 | else | |
8669 | intel_crtc->new_config = NULL; | |
51fd371b RC |
8670 | fail_unlock: |
8671 | if (ret == -EDEADLK) { | |
8672 | drm_modeset_backoff(ctx); | |
8673 | goto retry; | |
8674 | } | |
8675 | ||
412b61d8 | 8676 | return false; |
79e53945 JB |
8677 | } |
8678 | ||
d2434ab7 | 8679 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
208bf9fd | 8680 | struct intel_load_detect_pipe *old) |
79e53945 | 8681 | { |
d2434ab7 DV |
8682 | struct intel_encoder *intel_encoder = |
8683 | intel_attached_encoder(connector); | |
4ef69c7a | 8684 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 8685 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 8686 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 8687 | |
d2dff872 | 8688 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 8689 | connector->base.id, connector->name, |
8e329a03 | 8690 | encoder->base.id, encoder->name); |
d2dff872 | 8691 | |
8261b191 | 8692 | if (old->load_detect_temp) { |
fc303101 DV |
8693 | to_intel_connector(connector)->new_encoder = NULL; |
8694 | intel_encoder->new_crtc = NULL; | |
412b61d8 VS |
8695 | intel_crtc->new_enabled = false; |
8696 | intel_crtc->new_config = NULL; | |
fc303101 | 8697 | intel_set_mode(crtc, NULL, 0, 0, NULL); |
d2dff872 | 8698 | |
36206361 DV |
8699 | if (old->release_fb) { |
8700 | drm_framebuffer_unregister_private(old->release_fb); | |
8701 | drm_framebuffer_unreference(old->release_fb); | |
8702 | } | |
d2dff872 | 8703 | |
0622a53c | 8704 | return; |
79e53945 JB |
8705 | } |
8706 | ||
c751ce4f | 8707 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
8708 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
8709 | connector->funcs->dpms(connector, old->dpms_mode); | |
79e53945 JB |
8710 | } |
8711 | ||
da4a1efa VS |
8712 | static int i9xx_pll_refclk(struct drm_device *dev, |
8713 | const struct intel_crtc_config *pipe_config) | |
8714 | { | |
8715 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8716 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
8717 | ||
8718 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 8719 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
8720 | else if (HAS_PCH_SPLIT(dev)) |
8721 | return 120000; | |
8722 | else if (!IS_GEN2(dev)) | |
8723 | return 96000; | |
8724 | else | |
8725 | return 48000; | |
8726 | } | |
8727 | ||
79e53945 | 8728 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc JB |
8729 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
8730 | struct intel_crtc_config *pipe_config) | |
79e53945 | 8731 | { |
f1f644dc | 8732 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 8733 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 8734 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 8735 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
8736 | u32 fp; |
8737 | intel_clock_t clock; | |
da4a1efa | 8738 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
8739 | |
8740 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 8741 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 8742 | else |
293623f7 | 8743 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
8744 | |
8745 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
8746 | if (IS_PINEVIEW(dev)) { |
8747 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
8748 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
8749 | } else { |
8750 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
8751 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
8752 | } | |
8753 | ||
a6c45cf0 | 8754 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
8755 | if (IS_PINEVIEW(dev)) |
8756 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
8757 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
8758 | else |
8759 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
8760 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
8761 | ||
8762 | switch (dpll & DPLL_MODE_MASK) { | |
8763 | case DPLLB_MODE_DAC_SERIAL: | |
8764 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
8765 | 5 : 10; | |
8766 | break; | |
8767 | case DPLLB_MODE_LVDS: | |
8768 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
8769 | 7 : 14; | |
8770 | break; | |
8771 | default: | |
28c97730 | 8772 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 8773 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 8774 | return; |
79e53945 JB |
8775 | } |
8776 | ||
ac58c3f0 | 8777 | if (IS_PINEVIEW(dev)) |
da4a1efa | 8778 | pineview_clock(refclk, &clock); |
ac58c3f0 | 8779 | else |
da4a1efa | 8780 | i9xx_clock(refclk, &clock); |
79e53945 | 8781 | } else { |
0fb58223 | 8782 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 8783 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
8784 | |
8785 | if (is_lvds) { | |
8786 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
8787 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
8788 | |
8789 | if (lvds & LVDS_CLKB_POWER_UP) | |
8790 | clock.p2 = 7; | |
8791 | else | |
8792 | clock.p2 = 14; | |
79e53945 JB |
8793 | } else { |
8794 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
8795 | clock.p1 = 2; | |
8796 | else { | |
8797 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
8798 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
8799 | } | |
8800 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
8801 | clock.p2 = 4; | |
8802 | else | |
8803 | clock.p2 = 2; | |
79e53945 | 8804 | } |
da4a1efa VS |
8805 | |
8806 | i9xx_clock(refclk, &clock); | |
79e53945 JB |
8807 | } |
8808 | ||
18442d08 VS |
8809 | /* |
8810 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 8811 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
8812 | * encoder's get_config() function. |
8813 | */ | |
8814 | pipe_config->port_clock = clock.dot; | |
f1f644dc JB |
8815 | } |
8816 | ||
6878da05 VS |
8817 | int intel_dotclock_calculate(int link_freq, |
8818 | const struct intel_link_m_n *m_n) | |
f1f644dc | 8819 | { |
f1f644dc JB |
8820 | /* |
8821 | * The calculation for the data clock is: | |
1041a02f | 8822 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 8823 | * But we want to avoid losing precison if possible, so: |
1041a02f | 8824 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
8825 | * |
8826 | * and the link clock is simpler: | |
1041a02f | 8827 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
8828 | */ |
8829 | ||
6878da05 VS |
8830 | if (!m_n->link_n) |
8831 | return 0; | |
f1f644dc | 8832 | |
6878da05 VS |
8833 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
8834 | } | |
f1f644dc | 8835 | |
18442d08 VS |
8836 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
8837 | struct intel_crtc_config *pipe_config) | |
6878da05 VS |
8838 | { |
8839 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 8840 | |
18442d08 VS |
8841 | /* read out port_clock from the DPLL */ |
8842 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 8843 | |
f1f644dc | 8844 | /* |
18442d08 | 8845 | * This value does not include pixel_multiplier. |
241bfc38 | 8846 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
8847 | * agree once we know their relationship in the encoder's |
8848 | * get_config() function. | |
79e53945 | 8849 | */ |
241bfc38 | 8850 | pipe_config->adjusted_mode.crtc_clock = |
18442d08 VS |
8851 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
8852 | &pipe_config->fdi_m_n); | |
79e53945 JB |
8853 | } |
8854 | ||
8855 | /** Returns the currently programmed mode of the given pipe. */ | |
8856 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
8857 | struct drm_crtc *crtc) | |
8858 | { | |
548f245b | 8859 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 8860 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3b117c8f | 8861 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
79e53945 | 8862 | struct drm_display_mode *mode; |
f1f644dc | 8863 | struct intel_crtc_config pipe_config; |
fe2b8f9d PZ |
8864 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
8865 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
8866 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
8867 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 8868 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
8869 | |
8870 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
8871 | if (!mode) | |
8872 | return NULL; | |
8873 | ||
f1f644dc JB |
8874 | /* |
8875 | * Construct a pipe_config sufficient for getting the clock info | |
8876 | * back out of crtc_clock_get. | |
8877 | * | |
8878 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
8879 | * to use a real value here instead. | |
8880 | */ | |
293623f7 | 8881 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 8882 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
8883 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
8884 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
8885 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
8886 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
8887 | ||
773ae034 | 8888 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
8889 | mode->hdisplay = (htot & 0xffff) + 1; |
8890 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
8891 | mode->hsync_start = (hsync & 0xffff) + 1; | |
8892 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
8893 | mode->vdisplay = (vtot & 0xffff) + 1; | |
8894 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
8895 | mode->vsync_start = (vsync & 0xffff) + 1; | |
8896 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
8897 | ||
8898 | drm_mode_set_name(mode); | |
79e53945 JB |
8899 | |
8900 | return mode; | |
8901 | } | |
8902 | ||
cc36513c DV |
8903 | static void intel_increase_pllclock(struct drm_device *dev, |
8904 | enum pipe pipe) | |
652c393a | 8905 | { |
fbee40df | 8906 | struct drm_i915_private *dev_priv = dev->dev_private; |
dbdc6479 JB |
8907 | int dpll_reg = DPLL(pipe); |
8908 | int dpll; | |
652c393a | 8909 | |
baff296c | 8910 | if (!HAS_GMCH_DISPLAY(dev)) |
652c393a JB |
8911 | return; |
8912 | ||
8913 | if (!dev_priv->lvds_downclock_avail) | |
8914 | return; | |
8915 | ||
dbdc6479 | 8916 | dpll = I915_READ(dpll_reg); |
652c393a | 8917 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
44d98a61 | 8918 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
652c393a | 8919 | |
8ac5a6d5 | 8920 | assert_panel_unlocked(dev_priv, pipe); |
652c393a JB |
8921 | |
8922 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; | |
8923 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 8924 | intel_wait_for_vblank(dev, pipe); |
dbdc6479 | 8925 | |
652c393a JB |
8926 | dpll = I915_READ(dpll_reg); |
8927 | if (dpll & DISPLAY_RATE_SELECT_FPA1) | |
44d98a61 | 8928 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
652c393a | 8929 | } |
652c393a JB |
8930 | } |
8931 | ||
8932 | static void intel_decrease_pllclock(struct drm_crtc *crtc) | |
8933 | { | |
8934 | struct drm_device *dev = crtc->dev; | |
fbee40df | 8935 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 8936 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
652c393a | 8937 | |
baff296c | 8938 | if (!HAS_GMCH_DISPLAY(dev)) |
652c393a JB |
8939 | return; |
8940 | ||
8941 | if (!dev_priv->lvds_downclock_avail) | |
8942 | return; | |
8943 | ||
8944 | /* | |
8945 | * Since this is called by a timer, we should never get here in | |
8946 | * the manual case. | |
8947 | */ | |
8948 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
8949 | int pipe = intel_crtc->pipe; |
8950 | int dpll_reg = DPLL(pipe); | |
8951 | int dpll; | |
f6e5b160 | 8952 | |
44d98a61 | 8953 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 8954 | |
8ac5a6d5 | 8955 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 8956 | |
dc257cf1 | 8957 | dpll = I915_READ(dpll_reg); |
652c393a JB |
8958 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
8959 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 8960 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
8961 | dpll = I915_READ(dpll_reg); |
8962 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 8963 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
8964 | } |
8965 | ||
8966 | } | |
8967 | ||
f047e395 CW |
8968 | void intel_mark_busy(struct drm_device *dev) |
8969 | { | |
c67a470b PZ |
8970 | struct drm_i915_private *dev_priv = dev->dev_private; |
8971 | ||
f62a0076 CW |
8972 | if (dev_priv->mm.busy) |
8973 | return; | |
8974 | ||
43694d69 | 8975 | intel_runtime_pm_get(dev_priv); |
c67a470b | 8976 | i915_update_gfx_val(dev_priv); |
f62a0076 | 8977 | dev_priv->mm.busy = true; |
f047e395 CW |
8978 | } |
8979 | ||
8980 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 8981 | { |
c67a470b | 8982 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 8983 | struct drm_crtc *crtc; |
652c393a | 8984 | |
f62a0076 CW |
8985 | if (!dev_priv->mm.busy) |
8986 | return; | |
8987 | ||
8988 | dev_priv->mm.busy = false; | |
8989 | ||
d330a953 | 8990 | if (!i915.powersave) |
bb4cdd53 | 8991 | goto out; |
652c393a | 8992 | |
70e1e0ec | 8993 | for_each_crtc(dev, crtc) { |
f4510a27 | 8994 | if (!crtc->primary->fb) |
652c393a JB |
8995 | continue; |
8996 | ||
725a5b54 | 8997 | intel_decrease_pllclock(crtc); |
652c393a | 8998 | } |
b29c19b6 | 8999 | |
3d13ef2e | 9000 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 9001 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 PZ |
9002 | |
9003 | out: | |
43694d69 | 9004 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
9005 | } |
9006 | ||
7c8f8a70 | 9007 | |
f99d7069 DV |
9008 | /** |
9009 | * intel_mark_fb_busy - mark given planes as busy | |
9010 | * @dev: DRM device | |
9011 | * @frontbuffer_bits: bits for the affected planes | |
9012 | * @ring: optional ring for asynchronous commands | |
9013 | * | |
9014 | * This function gets called every time the screen contents change. It can be | |
9015 | * used to keep e.g. the update rate at the nominal refresh rate with DRRS. | |
9016 | */ | |
9017 | static void intel_mark_fb_busy(struct drm_device *dev, | |
9018 | unsigned frontbuffer_bits, | |
9019 | struct intel_engine_cs *ring) | |
652c393a | 9020 | { |
055e393f | 9021 | struct drm_i915_private *dev_priv = dev->dev_private; |
cc36513c | 9022 | enum pipe pipe; |
652c393a | 9023 | |
d330a953 | 9024 | if (!i915.powersave) |
acb87dfb CW |
9025 | return; |
9026 | ||
055e393f | 9027 | for_each_pipe(dev_priv, pipe) { |
f99d7069 | 9028 | if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe))) |
c65355bb CW |
9029 | continue; |
9030 | ||
cc36513c | 9031 | intel_increase_pllclock(dev, pipe); |
c65355bb CW |
9032 | if (ring && intel_fbc_enabled(dev)) |
9033 | ring->fbc_dirty = true; | |
652c393a JB |
9034 | } |
9035 | } | |
9036 | ||
f99d7069 DV |
9037 | /** |
9038 | * intel_fb_obj_invalidate - invalidate frontbuffer object | |
9039 | * @obj: GEM object to invalidate | |
9040 | * @ring: set for asynchronous rendering | |
9041 | * | |
9042 | * This function gets called every time rendering on the given object starts and | |
9043 | * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must | |
9044 | * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed | |
9045 | * until the rendering completes or a flip on this frontbuffer plane is | |
9046 | * scheduled. | |
9047 | */ | |
9048 | void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj, | |
9049 | struct intel_engine_cs *ring) | |
9050 | { | |
9051 | struct drm_device *dev = obj->base.dev; | |
9052 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9053 | ||
9054 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); | |
9055 | ||
9056 | if (!obj->frontbuffer_bits) | |
9057 | return; | |
9058 | ||
9059 | if (ring) { | |
9060 | mutex_lock(&dev_priv->fb_tracking.lock); | |
9061 | dev_priv->fb_tracking.busy_bits | |
9062 | |= obj->frontbuffer_bits; | |
9063 | dev_priv->fb_tracking.flip_bits | |
9064 | &= ~obj->frontbuffer_bits; | |
9065 | mutex_unlock(&dev_priv->fb_tracking.lock); | |
9066 | } | |
9067 | ||
9068 | intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring); | |
9069 | ||
9ca15301 | 9070 | intel_edp_psr_invalidate(dev, obj->frontbuffer_bits); |
f99d7069 DV |
9071 | } |
9072 | ||
9073 | /** | |
9074 | * intel_frontbuffer_flush - flush frontbuffer | |
9075 | * @dev: DRM device | |
9076 | * @frontbuffer_bits: frontbuffer plane tracking bits | |
9077 | * | |
9078 | * This function gets called every time rendering on the given planes has | |
9079 | * completed and frontbuffer caching can be started again. Flushes will get | |
9080 | * delayed if they're blocked by some oustanding asynchronous rendering. | |
9081 | * | |
9082 | * Can be called without any locks held. | |
9083 | */ | |
9084 | void intel_frontbuffer_flush(struct drm_device *dev, | |
9085 | unsigned frontbuffer_bits) | |
9086 | { | |
9087 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9088 | ||
9089 | /* Delay flushing when rings are still busy.*/ | |
9090 | mutex_lock(&dev_priv->fb_tracking.lock); | |
9091 | frontbuffer_bits &= ~dev_priv->fb_tracking.busy_bits; | |
9092 | mutex_unlock(&dev_priv->fb_tracking.lock); | |
9093 | ||
9094 | intel_mark_fb_busy(dev, frontbuffer_bits, NULL); | |
9095 | ||
9ca15301 | 9096 | intel_edp_psr_flush(dev, frontbuffer_bits); |
c5ad011d RV |
9097 | |
9098 | if (IS_GEN8(dev)) | |
9099 | gen8_fbc_sw_flush(dev, FBC_REND_CACHE_CLEAN); | |
f99d7069 DV |
9100 | } |
9101 | ||
9102 | /** | |
9103 | * intel_fb_obj_flush - flush frontbuffer object | |
9104 | * @obj: GEM object to flush | |
9105 | * @retire: set when retiring asynchronous rendering | |
9106 | * | |
9107 | * This function gets called every time rendering on the given object has | |
9108 | * completed and frontbuffer caching can be started again. If @retire is true | |
9109 | * then any delayed flushes will be unblocked. | |
9110 | */ | |
9111 | void intel_fb_obj_flush(struct drm_i915_gem_object *obj, | |
9112 | bool retire) | |
9113 | { | |
9114 | struct drm_device *dev = obj->base.dev; | |
9115 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9116 | unsigned frontbuffer_bits; | |
9117 | ||
9118 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); | |
9119 | ||
9120 | if (!obj->frontbuffer_bits) | |
9121 | return; | |
9122 | ||
9123 | frontbuffer_bits = obj->frontbuffer_bits; | |
9124 | ||
9125 | if (retire) { | |
9126 | mutex_lock(&dev_priv->fb_tracking.lock); | |
9127 | /* Filter out new bits since rendering started. */ | |
9128 | frontbuffer_bits &= dev_priv->fb_tracking.busy_bits; | |
9129 | ||
9130 | dev_priv->fb_tracking.busy_bits &= ~frontbuffer_bits; | |
9131 | mutex_unlock(&dev_priv->fb_tracking.lock); | |
9132 | } | |
9133 | ||
9134 | intel_frontbuffer_flush(dev, frontbuffer_bits); | |
9135 | } | |
9136 | ||
9137 | /** | |
9138 | * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip | |
9139 | * @dev: DRM device | |
9140 | * @frontbuffer_bits: frontbuffer plane tracking bits | |
9141 | * | |
9142 | * This function gets called after scheduling a flip on @obj. The actual | |
9143 | * frontbuffer flushing will be delayed until completion is signalled with | |
9144 | * intel_frontbuffer_flip_complete. If an invalidate happens in between this | |
9145 | * flush will be cancelled. | |
9146 | * | |
9147 | * Can be called without any locks held. | |
9148 | */ | |
9149 | void intel_frontbuffer_flip_prepare(struct drm_device *dev, | |
9150 | unsigned frontbuffer_bits) | |
9151 | { | |
9152 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9153 | ||
9154 | mutex_lock(&dev_priv->fb_tracking.lock); | |
9155 | dev_priv->fb_tracking.flip_bits | |
9156 | |= frontbuffer_bits; | |
9157 | mutex_unlock(&dev_priv->fb_tracking.lock); | |
9158 | } | |
9159 | ||
9160 | /** | |
9161 | * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush | |
9162 | * @dev: DRM device | |
9163 | * @frontbuffer_bits: frontbuffer plane tracking bits | |
9164 | * | |
9165 | * This function gets called after the flip has been latched and will complete | |
9166 | * on the next vblank. It will execute the fush if it hasn't been cancalled yet. | |
9167 | * | |
9168 | * Can be called without any locks held. | |
9169 | */ | |
9170 | void intel_frontbuffer_flip_complete(struct drm_device *dev, | |
9171 | unsigned frontbuffer_bits) | |
9172 | { | |
9173 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9174 | ||
9175 | mutex_lock(&dev_priv->fb_tracking.lock); | |
9176 | /* Mask any cancelled flips. */ | |
9177 | frontbuffer_bits &= dev_priv->fb_tracking.flip_bits; | |
9178 | dev_priv->fb_tracking.flip_bits &= ~frontbuffer_bits; | |
9179 | mutex_unlock(&dev_priv->fb_tracking.lock); | |
9180 | ||
9181 | intel_frontbuffer_flush(dev, frontbuffer_bits); | |
9182 | } | |
9183 | ||
79e53945 JB |
9184 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
9185 | { | |
9186 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
9187 | struct drm_device *dev = crtc->dev; |
9188 | struct intel_unpin_work *work; | |
9189 | unsigned long flags; | |
9190 | ||
9191 | spin_lock_irqsave(&dev->event_lock, flags); | |
9192 | work = intel_crtc->unpin_work; | |
9193 | intel_crtc->unpin_work = NULL; | |
9194 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
9195 | ||
9196 | if (work) { | |
9197 | cancel_work_sync(&work->work); | |
9198 | kfree(work); | |
9199 | } | |
79e53945 JB |
9200 | |
9201 | drm_crtc_cleanup(crtc); | |
67e77c5a | 9202 | |
79e53945 JB |
9203 | kfree(intel_crtc); |
9204 | } | |
9205 | ||
6b95a207 KH |
9206 | static void intel_unpin_work_fn(struct work_struct *__work) |
9207 | { | |
9208 | struct intel_unpin_work *work = | |
9209 | container_of(__work, struct intel_unpin_work, work); | |
b4a98e57 | 9210 | struct drm_device *dev = work->crtc->dev; |
f99d7069 | 9211 | enum pipe pipe = to_intel_crtc(work->crtc)->pipe; |
6b95a207 | 9212 | |
b4a98e57 | 9213 | mutex_lock(&dev->struct_mutex); |
1690e1eb | 9214 | intel_unpin_fb_obj(work->old_fb_obj); |
05394f39 CW |
9215 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
9216 | drm_gem_object_unreference(&work->old_fb_obj->base); | |
d9e86c0e | 9217 | |
b4a98e57 CW |
9218 | intel_update_fbc(dev); |
9219 | mutex_unlock(&dev->struct_mutex); | |
9220 | ||
f99d7069 DV |
9221 | intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
9222 | ||
b4a98e57 CW |
9223 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); |
9224 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); | |
9225 | ||
6b95a207 KH |
9226 | kfree(work); |
9227 | } | |
9228 | ||
1afe3e9d | 9229 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 9230 | struct drm_crtc *crtc) |
6b95a207 | 9231 | { |
fbee40df | 9232 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
9233 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9234 | struct intel_unpin_work *work; | |
6b95a207 KH |
9235 | unsigned long flags; |
9236 | ||
9237 | /* Ignore early vblank irqs */ | |
9238 | if (intel_crtc == NULL) | |
9239 | return; | |
9240 | ||
9241 | spin_lock_irqsave(&dev->event_lock, flags); | |
9242 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
9243 | |
9244 | /* Ensure we don't miss a work->pending update ... */ | |
9245 | smp_rmb(); | |
9246 | ||
9247 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
9248 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9249 | return; | |
9250 | } | |
9251 | ||
e7d841ca CW |
9252 | /* and that the unpin work is consistent wrt ->pending. */ |
9253 | smp_rmb(); | |
9254 | ||
6b95a207 | 9255 | intel_crtc->unpin_work = NULL; |
6b95a207 | 9256 | |
45a066eb RC |
9257 | if (work->event) |
9258 | drm_send_vblank_event(dev, intel_crtc->pipe, work->event); | |
6b95a207 | 9259 | |
87b6b101 | 9260 | drm_crtc_vblank_put(crtc); |
0af7e4df | 9261 | |
6b95a207 KH |
9262 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9263 | ||
2c10d571 | 9264 | wake_up_all(&dev_priv->pending_flip_queue); |
b4a98e57 CW |
9265 | |
9266 | queue_work(dev_priv->wq, &work->work); | |
e5510fac JB |
9267 | |
9268 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); | |
6b95a207 KH |
9269 | } |
9270 | ||
1afe3e9d JB |
9271 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
9272 | { | |
fbee40df | 9273 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
9274 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
9275 | ||
49b14a5c | 9276 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
9277 | } |
9278 | ||
9279 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
9280 | { | |
fbee40df | 9281 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
9282 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
9283 | ||
49b14a5c | 9284 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
9285 | } |
9286 | ||
75f7f3ec VS |
9287 | /* Is 'a' after or equal to 'b'? */ |
9288 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
9289 | { | |
9290 | return !((a - b) & 0x80000000); | |
9291 | } | |
9292 | ||
9293 | static bool page_flip_finished(struct intel_crtc *crtc) | |
9294 | { | |
9295 | struct drm_device *dev = crtc->base.dev; | |
9296 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9297 | ||
9298 | /* | |
9299 | * The relevant registers doen't exist on pre-ctg. | |
9300 | * As the flip done interrupt doesn't trigger for mmio | |
9301 | * flips on gmch platforms, a flip count check isn't | |
9302 | * really needed there. But since ctg has the registers, | |
9303 | * include it in the check anyway. | |
9304 | */ | |
9305 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
9306 | return true; | |
9307 | ||
9308 | /* | |
9309 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
9310 | * used the same base address. In that case the mmio flip might | |
9311 | * have completed, but the CS hasn't even executed the flip yet. | |
9312 | * | |
9313 | * A flip count check isn't enough as the CS might have updated | |
9314 | * the base address just after start of vblank, but before we | |
9315 | * managed to process the interrupt. This means we'd complete the | |
9316 | * CS flip too soon. | |
9317 | * | |
9318 | * Combining both checks should get us a good enough result. It may | |
9319 | * still happen that the CS flip has been executed, but has not | |
9320 | * yet actually completed. But in case the base address is the same | |
9321 | * anyway, we don't really care. | |
9322 | */ | |
9323 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
9324 | crtc->unpin_work->gtt_offset && | |
9325 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)), | |
9326 | crtc->unpin_work->flip_count); | |
9327 | } | |
9328 | ||
6b95a207 KH |
9329 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
9330 | { | |
fbee40df | 9331 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
9332 | struct intel_crtc *intel_crtc = |
9333 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
9334 | unsigned long flags; | |
9335 | ||
e7d841ca CW |
9336 | /* NB: An MMIO update of the plane base pointer will also |
9337 | * generate a page-flip completion irq, i.e. every modeset | |
9338 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
9339 | */ | |
6b95a207 | 9340 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 9341 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 9342 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
9343 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9344 | } | |
9345 | ||
eba905b2 | 9346 | static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
e7d841ca CW |
9347 | { |
9348 | /* Ensure that the work item is consistent when activating it ... */ | |
9349 | smp_wmb(); | |
9350 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
9351 | /* and that it is marked active as soon as the irq could fire. */ | |
9352 | smp_wmb(); | |
9353 | } | |
9354 | ||
8c9f3aaf JB |
9355 | static int intel_gen2_queue_flip(struct drm_device *dev, |
9356 | struct drm_crtc *crtc, | |
9357 | struct drm_framebuffer *fb, | |
ed8d1975 | 9358 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9359 | struct intel_engine_cs *ring, |
ed8d1975 | 9360 | uint32_t flags) |
8c9f3aaf | 9361 | { |
8c9f3aaf | 9362 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
9363 | u32 flip_mask; |
9364 | int ret; | |
9365 | ||
6d90c952 | 9366 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 9367 | if (ret) |
4fa62c89 | 9368 | return ret; |
8c9f3aaf JB |
9369 | |
9370 | /* Can't queue multiple flips, so wait for the previous | |
9371 | * one to finish before executing the next. | |
9372 | */ | |
9373 | if (intel_crtc->plane) | |
9374 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
9375 | else | |
9376 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
9377 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
9378 | intel_ring_emit(ring, MI_NOOP); | |
9379 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
9380 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9381 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9382 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 | 9383 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
9384 | |
9385 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9386 | __intel_ring_advance(ring); |
83d4092b | 9387 | return 0; |
8c9f3aaf JB |
9388 | } |
9389 | ||
9390 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
9391 | struct drm_crtc *crtc, | |
9392 | struct drm_framebuffer *fb, | |
ed8d1975 | 9393 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9394 | struct intel_engine_cs *ring, |
ed8d1975 | 9395 | uint32_t flags) |
8c9f3aaf | 9396 | { |
8c9f3aaf | 9397 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
9398 | u32 flip_mask; |
9399 | int ret; | |
9400 | ||
6d90c952 | 9401 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 9402 | if (ret) |
4fa62c89 | 9403 | return ret; |
8c9f3aaf JB |
9404 | |
9405 | if (intel_crtc->plane) | |
9406 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
9407 | else | |
9408 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
9409 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
9410 | intel_ring_emit(ring, MI_NOOP); | |
9411 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
9412 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9413 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9414 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 DV |
9415 | intel_ring_emit(ring, MI_NOOP); |
9416 | ||
e7d841ca | 9417 | intel_mark_page_flip_active(intel_crtc); |
09246732 | 9418 | __intel_ring_advance(ring); |
83d4092b | 9419 | return 0; |
8c9f3aaf JB |
9420 | } |
9421 | ||
9422 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
9423 | struct drm_crtc *crtc, | |
9424 | struct drm_framebuffer *fb, | |
ed8d1975 | 9425 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9426 | struct intel_engine_cs *ring, |
ed8d1975 | 9427 | uint32_t flags) |
8c9f3aaf JB |
9428 | { |
9429 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9430 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9431 | uint32_t pf, pipesrc; | |
9432 | int ret; | |
9433 | ||
6d90c952 | 9434 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 9435 | if (ret) |
4fa62c89 | 9436 | return ret; |
8c9f3aaf JB |
9437 | |
9438 | /* i965+ uses the linear or tiled offsets from the | |
9439 | * Display Registers (which do not change across a page-flip) | |
9440 | * so we need only reprogram the base address. | |
9441 | */ | |
6d90c952 DV |
9442 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
9443 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9444 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9445 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
c2c75131 | 9446 | obj->tiling_mode); |
8c9f3aaf JB |
9447 | |
9448 | /* XXX Enabling the panel-fitter across page-flip is so far | |
9449 | * untested on non-native modes, so ignore it for now. | |
9450 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
9451 | */ | |
9452 | pf = 0; | |
9453 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 9454 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
9455 | |
9456 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9457 | __intel_ring_advance(ring); |
83d4092b | 9458 | return 0; |
8c9f3aaf JB |
9459 | } |
9460 | ||
9461 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
9462 | struct drm_crtc *crtc, | |
9463 | struct drm_framebuffer *fb, | |
ed8d1975 | 9464 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9465 | struct intel_engine_cs *ring, |
ed8d1975 | 9466 | uint32_t flags) |
8c9f3aaf JB |
9467 | { |
9468 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9469 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9470 | uint32_t pf, pipesrc; | |
9471 | int ret; | |
9472 | ||
6d90c952 | 9473 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 9474 | if (ret) |
4fa62c89 | 9475 | return ret; |
8c9f3aaf | 9476 | |
6d90c952 DV |
9477 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
9478 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9479 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
75f7f3ec | 9480 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8c9f3aaf | 9481 | |
dc257cf1 DV |
9482 | /* Contrary to the suggestions in the documentation, |
9483 | * "Enable Panel Fitter" does not seem to be required when page | |
9484 | * flipping with a non-native mode, and worse causes a normal | |
9485 | * modeset to fail. | |
9486 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
9487 | */ | |
9488 | pf = 0; | |
8c9f3aaf | 9489 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 9490 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
9491 | |
9492 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9493 | __intel_ring_advance(ring); |
83d4092b | 9494 | return 0; |
8c9f3aaf JB |
9495 | } |
9496 | ||
7c9017e5 JB |
9497 | static int intel_gen7_queue_flip(struct drm_device *dev, |
9498 | struct drm_crtc *crtc, | |
9499 | struct drm_framebuffer *fb, | |
ed8d1975 | 9500 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9501 | struct intel_engine_cs *ring, |
ed8d1975 | 9502 | uint32_t flags) |
7c9017e5 | 9503 | { |
7c9017e5 | 9504 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 9505 | uint32_t plane_bit = 0; |
ffe74d75 CW |
9506 | int len, ret; |
9507 | ||
eba905b2 | 9508 | switch (intel_crtc->plane) { |
cb05d8de DV |
9509 | case PLANE_A: |
9510 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
9511 | break; | |
9512 | case PLANE_B: | |
9513 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
9514 | break; | |
9515 | case PLANE_C: | |
9516 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
9517 | break; | |
9518 | default: | |
9519 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 9520 | return -ENODEV; |
cb05d8de DV |
9521 | } |
9522 | ||
ffe74d75 | 9523 | len = 4; |
f476828a | 9524 | if (ring->id == RCS) { |
ffe74d75 | 9525 | len += 6; |
f476828a DL |
9526 | /* |
9527 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
9528 | * 48bits addresses, and we need a NOOP for the batch size to | |
9529 | * stay even. | |
9530 | */ | |
9531 | if (IS_GEN8(dev)) | |
9532 | len += 2; | |
9533 | } | |
ffe74d75 | 9534 | |
f66fab8e VS |
9535 | /* |
9536 | * BSpec MI_DISPLAY_FLIP for IVB: | |
9537 | * "The full packet must be contained within the same cache line." | |
9538 | * | |
9539 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
9540 | * cacheline, if we ever start emitting more commands before | |
9541 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
9542 | * then do the cacheline alignment, and finally emit the | |
9543 | * MI_DISPLAY_FLIP. | |
9544 | */ | |
9545 | ret = intel_ring_cacheline_align(ring); | |
9546 | if (ret) | |
4fa62c89 | 9547 | return ret; |
f66fab8e | 9548 | |
ffe74d75 | 9549 | ret = intel_ring_begin(ring, len); |
7c9017e5 | 9550 | if (ret) |
4fa62c89 | 9551 | return ret; |
7c9017e5 | 9552 | |
ffe74d75 CW |
9553 | /* Unmask the flip-done completion message. Note that the bspec says that |
9554 | * we should do this for both the BCS and RCS, and that we must not unmask | |
9555 | * more than one flip event at any time (or ensure that one flip message | |
9556 | * can be sent by waiting for flip-done prior to queueing new flips). | |
9557 | * Experimentation says that BCS works despite DERRMR masking all | |
9558 | * flip-done completion events and that unmasking all planes at once | |
9559 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
9560 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
9561 | */ | |
9562 | if (ring->id == RCS) { | |
9563 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
9564 | intel_ring_emit(ring, DERRMR); | |
9565 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
9566 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
9567 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a DL |
9568 | if (IS_GEN8(dev)) |
9569 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) | | |
9570 | MI_SRM_LRM_GLOBAL_GTT); | |
9571 | else | |
9572 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | | |
9573 | MI_SRM_LRM_GLOBAL_GTT); | |
ffe74d75 CW |
9574 | intel_ring_emit(ring, DERRMR); |
9575 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
f476828a DL |
9576 | if (IS_GEN8(dev)) { |
9577 | intel_ring_emit(ring, 0); | |
9578 | intel_ring_emit(ring, MI_NOOP); | |
9579 | } | |
ffe74d75 CW |
9580 | } |
9581 | ||
cb05d8de | 9582 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 9583 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
75f7f3ec | 9584 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
7c9017e5 | 9585 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
9586 | |
9587 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9588 | __intel_ring_advance(ring); |
83d4092b | 9589 | return 0; |
7c9017e5 JB |
9590 | } |
9591 | ||
84c33a64 SG |
9592 | static bool use_mmio_flip(struct intel_engine_cs *ring, |
9593 | struct drm_i915_gem_object *obj) | |
9594 | { | |
9595 | /* | |
9596 | * This is not being used for older platforms, because | |
9597 | * non-availability of flip done interrupt forces us to use | |
9598 | * CS flips. Older platforms derive flip done using some clever | |
9599 | * tricks involving the flip_pending status bits and vblank irqs. | |
9600 | * So using MMIO flips there would disrupt this mechanism. | |
9601 | */ | |
9602 | ||
8e09bf83 CW |
9603 | if (ring == NULL) |
9604 | return true; | |
9605 | ||
84c33a64 SG |
9606 | if (INTEL_INFO(ring->dev)->gen < 5) |
9607 | return false; | |
9608 | ||
9609 | if (i915.use_mmio_flip < 0) | |
9610 | return false; | |
9611 | else if (i915.use_mmio_flip > 0) | |
9612 | return true; | |
14bf993e OM |
9613 | else if (i915.enable_execlists) |
9614 | return true; | |
84c33a64 SG |
9615 | else |
9616 | return ring != obj->ring; | |
9617 | } | |
9618 | ||
9619 | static void intel_do_mmio_flip(struct intel_crtc *intel_crtc) | |
9620 | { | |
9621 | struct drm_device *dev = intel_crtc->base.dev; | |
9622 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9623 | struct intel_framebuffer *intel_fb = | |
9624 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
9625 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
9626 | u32 dspcntr; | |
9627 | u32 reg; | |
9628 | ||
9629 | intel_mark_page_flip_active(intel_crtc); | |
9630 | ||
9631 | reg = DSPCNTR(intel_crtc->plane); | |
9632 | dspcntr = I915_READ(reg); | |
9633 | ||
9634 | if (INTEL_INFO(dev)->gen >= 4) { | |
9635 | if (obj->tiling_mode != I915_TILING_NONE) | |
9636 | dspcntr |= DISPPLANE_TILED; | |
9637 | else | |
9638 | dspcntr &= ~DISPPLANE_TILED; | |
9639 | } | |
9640 | I915_WRITE(reg, dspcntr); | |
9641 | ||
9642 | I915_WRITE(DSPSURF(intel_crtc->plane), | |
9643 | intel_crtc->unpin_work->gtt_offset); | |
9644 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
9645 | } | |
9646 | ||
9647 | static int intel_postpone_flip(struct drm_i915_gem_object *obj) | |
9648 | { | |
9649 | struct intel_engine_cs *ring; | |
9650 | int ret; | |
9651 | ||
9652 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
9653 | ||
9654 | if (!obj->last_write_seqno) | |
9655 | return 0; | |
9656 | ||
9657 | ring = obj->ring; | |
9658 | ||
9659 | if (i915_seqno_passed(ring->get_seqno(ring, true), | |
9660 | obj->last_write_seqno)) | |
9661 | return 0; | |
9662 | ||
9663 | ret = i915_gem_check_olr(ring, obj->last_write_seqno); | |
9664 | if (ret) | |
9665 | return ret; | |
9666 | ||
9667 | if (WARN_ON(!ring->irq_get(ring))) | |
9668 | return 0; | |
9669 | ||
9670 | return 1; | |
9671 | } | |
9672 | ||
9673 | void intel_notify_mmio_flip(struct intel_engine_cs *ring) | |
9674 | { | |
9675 | struct drm_i915_private *dev_priv = to_i915(ring->dev); | |
9676 | struct intel_crtc *intel_crtc; | |
9677 | unsigned long irq_flags; | |
9678 | u32 seqno; | |
9679 | ||
9680 | seqno = ring->get_seqno(ring, false); | |
9681 | ||
9682 | spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags); | |
9683 | for_each_intel_crtc(ring->dev, intel_crtc) { | |
9684 | struct intel_mmio_flip *mmio_flip; | |
9685 | ||
9686 | mmio_flip = &intel_crtc->mmio_flip; | |
9687 | if (mmio_flip->seqno == 0) | |
9688 | continue; | |
9689 | ||
9690 | if (ring->id != mmio_flip->ring_id) | |
9691 | continue; | |
9692 | ||
9693 | if (i915_seqno_passed(seqno, mmio_flip->seqno)) { | |
9694 | intel_do_mmio_flip(intel_crtc); | |
9695 | mmio_flip->seqno = 0; | |
9696 | ring->irq_put(ring); | |
9697 | } | |
9698 | } | |
9699 | spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags); | |
9700 | } | |
9701 | ||
9702 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
9703 | struct drm_crtc *crtc, | |
9704 | struct drm_framebuffer *fb, | |
9705 | struct drm_i915_gem_object *obj, | |
9706 | struct intel_engine_cs *ring, | |
9707 | uint32_t flags) | |
9708 | { | |
9709 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9710 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9711 | unsigned long irq_flags; | |
9712 | int ret; | |
9713 | ||
9714 | if (WARN_ON(intel_crtc->mmio_flip.seqno)) | |
9715 | return -EBUSY; | |
9716 | ||
9717 | ret = intel_postpone_flip(obj); | |
9718 | if (ret < 0) | |
9719 | return ret; | |
9720 | if (ret == 0) { | |
9721 | intel_do_mmio_flip(intel_crtc); | |
9722 | return 0; | |
9723 | } | |
9724 | ||
9725 | spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags); | |
9726 | intel_crtc->mmio_flip.seqno = obj->last_write_seqno; | |
9727 | intel_crtc->mmio_flip.ring_id = obj->ring->id; | |
9728 | spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags); | |
9729 | ||
9730 | /* | |
9731 | * Double check to catch cases where irq fired before | |
9732 | * mmio flip data was ready | |
9733 | */ | |
9734 | intel_notify_mmio_flip(obj->ring); | |
9735 | return 0; | |
9736 | } | |
9737 | ||
8c9f3aaf JB |
9738 | static int intel_default_queue_flip(struct drm_device *dev, |
9739 | struct drm_crtc *crtc, | |
9740 | struct drm_framebuffer *fb, | |
ed8d1975 | 9741 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9742 | struct intel_engine_cs *ring, |
ed8d1975 | 9743 | uint32_t flags) |
8c9f3aaf JB |
9744 | { |
9745 | return -ENODEV; | |
9746 | } | |
9747 | ||
6b95a207 KH |
9748 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
9749 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
9750 | struct drm_pending_vblank_event *event, |
9751 | uint32_t page_flip_flags) | |
6b95a207 KH |
9752 | { |
9753 | struct drm_device *dev = crtc->dev; | |
9754 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 9755 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 9756 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 | 9757 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
a071fa00 | 9758 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 9759 | struct intel_unpin_work *work; |
a4872ba6 | 9760 | struct intel_engine_cs *ring; |
8c9f3aaf | 9761 | unsigned long flags; |
52e68630 | 9762 | int ret; |
6b95a207 | 9763 | |
c76bb61a DS |
9764 | //trigger software GT busyness calculation |
9765 | gen8_flip_interrupt(dev); | |
9766 | ||
2ff8fde1 MR |
9767 | /* |
9768 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
9769 | * check to be safe. In the future we may enable pageflipping from | |
9770 | * a disabled primary plane. | |
9771 | */ | |
9772 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
9773 | return -EBUSY; | |
9774 | ||
e6a595d2 | 9775 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 9776 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
9777 | return -EINVAL; |
9778 | ||
9779 | /* | |
9780 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
9781 | * Note that pitch changes could also affect these register. | |
9782 | */ | |
9783 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
9784 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
9785 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
9786 | return -EINVAL; |
9787 | ||
f900db47 CW |
9788 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
9789 | goto out_hang; | |
9790 | ||
b14c5679 | 9791 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
9792 | if (work == NULL) |
9793 | return -ENOMEM; | |
9794 | ||
6b95a207 | 9795 | work->event = event; |
b4a98e57 | 9796 | work->crtc = crtc; |
2ff8fde1 | 9797 | work->old_fb_obj = intel_fb_obj(old_fb); |
6b95a207 KH |
9798 | INIT_WORK(&work->work, intel_unpin_work_fn); |
9799 | ||
87b6b101 | 9800 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
9801 | if (ret) |
9802 | goto free_work; | |
9803 | ||
6b95a207 KH |
9804 | /* We borrow the event spin lock for protecting unpin_work */ |
9805 | spin_lock_irqsave(&dev->event_lock, flags); | |
9806 | if (intel_crtc->unpin_work) { | |
9807 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
9808 | kfree(work); | |
87b6b101 | 9809 | drm_crtc_vblank_put(crtc); |
468f0b44 CW |
9810 | |
9811 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
6b95a207 KH |
9812 | return -EBUSY; |
9813 | } | |
9814 | intel_crtc->unpin_work = work; | |
9815 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
9816 | ||
b4a98e57 CW |
9817 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
9818 | flush_workqueue(dev_priv->wq); | |
9819 | ||
79158103 CW |
9820 | ret = i915_mutex_lock_interruptible(dev); |
9821 | if (ret) | |
9822 | goto cleanup; | |
6b95a207 | 9823 | |
75dfca80 | 9824 | /* Reference the objects for the scheduled work. */ |
05394f39 CW |
9825 | drm_gem_object_reference(&work->old_fb_obj->base); |
9826 | drm_gem_object_reference(&obj->base); | |
6b95a207 | 9827 | |
f4510a27 | 9828 | crtc->primary->fb = fb; |
96b099fd | 9829 | |
e1f99ce6 | 9830 | work->pending_flip_obj = obj; |
e1f99ce6 | 9831 | |
4e5359cd SF |
9832 | work->enable_stall_check = true; |
9833 | ||
b4a98e57 | 9834 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 9835 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 9836 | |
75f7f3ec | 9837 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
a071fa00 | 9838 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1; |
75f7f3ec | 9839 | |
4fa62c89 VS |
9840 | if (IS_VALLEYVIEW(dev)) { |
9841 | ring = &dev_priv->ring[BCS]; | |
8e09bf83 CW |
9842 | if (obj->tiling_mode != work->old_fb_obj->tiling_mode) |
9843 | /* vlv: DISPLAY_FLIP fails to change tiling */ | |
9844 | ring = NULL; | |
2a92d5bc CW |
9845 | } else if (IS_IVYBRIDGE(dev)) { |
9846 | ring = &dev_priv->ring[BCS]; | |
4fa62c89 VS |
9847 | } else if (INTEL_INFO(dev)->gen >= 7) { |
9848 | ring = obj->ring; | |
9849 | if (ring == NULL || ring->id != RCS) | |
9850 | ring = &dev_priv->ring[BCS]; | |
9851 | } else { | |
9852 | ring = &dev_priv->ring[RCS]; | |
9853 | } | |
9854 | ||
9855 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); | |
8c9f3aaf JB |
9856 | if (ret) |
9857 | goto cleanup_pending; | |
6b95a207 | 9858 | |
4fa62c89 VS |
9859 | work->gtt_offset = |
9860 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset; | |
9861 | ||
84c33a64 SG |
9862 | if (use_mmio_flip(ring, obj)) |
9863 | ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring, | |
9864 | page_flip_flags); | |
9865 | else | |
9866 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, | |
9867 | page_flip_flags); | |
4fa62c89 VS |
9868 | if (ret) |
9869 | goto cleanup_unpin; | |
9870 | ||
a071fa00 DV |
9871 | i915_gem_track_fb(work->old_fb_obj, obj, |
9872 | INTEL_FRONTBUFFER_PRIMARY(pipe)); | |
9873 | ||
7782de3b | 9874 | intel_disable_fbc(dev); |
f99d7069 | 9875 | intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
6b95a207 KH |
9876 | mutex_unlock(&dev->struct_mutex); |
9877 | ||
e5510fac JB |
9878 | trace_i915_flip_request(intel_crtc->plane, obj); |
9879 | ||
6b95a207 | 9880 | return 0; |
96b099fd | 9881 | |
4fa62c89 VS |
9882 | cleanup_unpin: |
9883 | intel_unpin_fb_obj(obj); | |
8c9f3aaf | 9884 | cleanup_pending: |
b4a98e57 | 9885 | atomic_dec(&intel_crtc->unpin_work_count); |
f4510a27 | 9886 | crtc->primary->fb = old_fb; |
05394f39 CW |
9887 | drm_gem_object_unreference(&work->old_fb_obj->base); |
9888 | drm_gem_object_unreference(&obj->base); | |
96b099fd CW |
9889 | mutex_unlock(&dev->struct_mutex); |
9890 | ||
79158103 | 9891 | cleanup: |
96b099fd CW |
9892 | spin_lock_irqsave(&dev->event_lock, flags); |
9893 | intel_crtc->unpin_work = NULL; | |
9894 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
9895 | ||
87b6b101 | 9896 | drm_crtc_vblank_put(crtc); |
7317c75e | 9897 | free_work: |
96b099fd CW |
9898 | kfree(work); |
9899 | ||
f900db47 CW |
9900 | if (ret == -EIO) { |
9901 | out_hang: | |
9902 | intel_crtc_wait_for_pending_flips(crtc); | |
9903 | ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb); | |
9904 | if (ret == 0 && event) | |
a071fa00 | 9905 | drm_send_vblank_event(dev, pipe, event); |
f900db47 | 9906 | } |
96b099fd | 9907 | return ret; |
6b95a207 KH |
9908 | } |
9909 | ||
f6e5b160 | 9910 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
9911 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
9912 | .load_lut = intel_crtc_load_lut, | |
f6e5b160 CW |
9913 | }; |
9914 | ||
9a935856 DV |
9915 | /** |
9916 | * intel_modeset_update_staged_output_state | |
9917 | * | |
9918 | * Updates the staged output configuration state, e.g. after we've read out the | |
9919 | * current hw state. | |
9920 | */ | |
9921 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) | |
f6e5b160 | 9922 | { |
7668851f | 9923 | struct intel_crtc *crtc; |
9a935856 DV |
9924 | struct intel_encoder *encoder; |
9925 | struct intel_connector *connector; | |
f6e5b160 | 9926 | |
9a935856 DV |
9927 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9928 | base.head) { | |
9929 | connector->new_encoder = | |
9930 | to_intel_encoder(connector->base.encoder); | |
9931 | } | |
f6e5b160 | 9932 | |
b2784e15 | 9933 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
9934 | encoder->new_crtc = |
9935 | to_intel_crtc(encoder->base.crtc); | |
9936 | } | |
7668851f | 9937 | |
d3fcc808 | 9938 | for_each_intel_crtc(dev, crtc) { |
7668851f | 9939 | crtc->new_enabled = crtc->base.enabled; |
7bd0a8e7 VS |
9940 | |
9941 | if (crtc->new_enabled) | |
9942 | crtc->new_config = &crtc->config; | |
9943 | else | |
9944 | crtc->new_config = NULL; | |
7668851f | 9945 | } |
f6e5b160 CW |
9946 | } |
9947 | ||
9a935856 DV |
9948 | /** |
9949 | * intel_modeset_commit_output_state | |
9950 | * | |
9951 | * This function copies the stage display pipe configuration to the real one. | |
9952 | */ | |
9953 | static void intel_modeset_commit_output_state(struct drm_device *dev) | |
9954 | { | |
7668851f | 9955 | struct intel_crtc *crtc; |
9a935856 DV |
9956 | struct intel_encoder *encoder; |
9957 | struct intel_connector *connector; | |
f6e5b160 | 9958 | |
9a935856 DV |
9959 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9960 | base.head) { | |
9961 | connector->base.encoder = &connector->new_encoder->base; | |
9962 | } | |
f6e5b160 | 9963 | |
b2784e15 | 9964 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
9965 | encoder->base.crtc = &encoder->new_crtc->base; |
9966 | } | |
7668851f | 9967 | |
d3fcc808 | 9968 | for_each_intel_crtc(dev, crtc) { |
7668851f VS |
9969 | crtc->base.enabled = crtc->new_enabled; |
9970 | } | |
9a935856 DV |
9971 | } |
9972 | ||
050f7aeb | 9973 | static void |
eba905b2 | 9974 | connected_sink_compute_bpp(struct intel_connector *connector, |
050f7aeb DV |
9975 | struct intel_crtc_config *pipe_config) |
9976 | { | |
9977 | int bpp = pipe_config->pipe_bpp; | |
9978 | ||
9979 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
9980 | connector->base.base.id, | |
c23cc417 | 9981 | connector->base.name); |
050f7aeb DV |
9982 | |
9983 | /* Don't use an invalid EDID bpc value */ | |
9984 | if (connector->base.display_info.bpc && | |
9985 | connector->base.display_info.bpc * 3 < bpp) { | |
9986 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
9987 | bpp, connector->base.display_info.bpc*3); | |
9988 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
9989 | } | |
9990 | ||
9991 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
9992 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
9993 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
9994 | bpp); | |
9995 | pipe_config->pipe_bpp = 24; | |
9996 | } | |
9997 | } | |
9998 | ||
4e53c2e0 | 9999 | static int |
050f7aeb DV |
10000 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
10001 | struct drm_framebuffer *fb, | |
10002 | struct intel_crtc_config *pipe_config) | |
4e53c2e0 | 10003 | { |
050f7aeb DV |
10004 | struct drm_device *dev = crtc->base.dev; |
10005 | struct intel_connector *connector; | |
4e53c2e0 DV |
10006 | int bpp; |
10007 | ||
d42264b1 DV |
10008 | switch (fb->pixel_format) { |
10009 | case DRM_FORMAT_C8: | |
4e53c2e0 DV |
10010 | bpp = 8*3; /* since we go through a colormap */ |
10011 | break; | |
d42264b1 DV |
10012 | case DRM_FORMAT_XRGB1555: |
10013 | case DRM_FORMAT_ARGB1555: | |
10014 | /* checked in intel_framebuffer_init already */ | |
10015 | if (WARN_ON(INTEL_INFO(dev)->gen > 3)) | |
10016 | return -EINVAL; | |
10017 | case DRM_FORMAT_RGB565: | |
4e53c2e0 DV |
10018 | bpp = 6*3; /* min is 18bpp */ |
10019 | break; | |
d42264b1 DV |
10020 | case DRM_FORMAT_XBGR8888: |
10021 | case DRM_FORMAT_ABGR8888: | |
10022 | /* checked in intel_framebuffer_init already */ | |
10023 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
10024 | return -EINVAL; | |
10025 | case DRM_FORMAT_XRGB8888: | |
10026 | case DRM_FORMAT_ARGB8888: | |
4e53c2e0 DV |
10027 | bpp = 8*3; |
10028 | break; | |
d42264b1 DV |
10029 | case DRM_FORMAT_XRGB2101010: |
10030 | case DRM_FORMAT_ARGB2101010: | |
10031 | case DRM_FORMAT_XBGR2101010: | |
10032 | case DRM_FORMAT_ABGR2101010: | |
10033 | /* checked in intel_framebuffer_init already */ | |
10034 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
baba133a | 10035 | return -EINVAL; |
4e53c2e0 DV |
10036 | bpp = 10*3; |
10037 | break; | |
baba133a | 10038 | /* TODO: gen4+ supports 16 bpc floating point, too. */ |
4e53c2e0 DV |
10039 | default: |
10040 | DRM_DEBUG_KMS("unsupported depth\n"); | |
10041 | return -EINVAL; | |
10042 | } | |
10043 | ||
4e53c2e0 DV |
10044 | pipe_config->pipe_bpp = bpp; |
10045 | ||
10046 | /* Clamp display bpp to EDID value */ | |
10047 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
050f7aeb | 10048 | base.head) { |
1b829e05 DV |
10049 | if (!connector->new_encoder || |
10050 | connector->new_encoder->new_crtc != crtc) | |
4e53c2e0 DV |
10051 | continue; |
10052 | ||
050f7aeb | 10053 | connected_sink_compute_bpp(connector, pipe_config); |
4e53c2e0 DV |
10054 | } |
10055 | ||
10056 | return bpp; | |
10057 | } | |
10058 | ||
644db711 DV |
10059 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
10060 | { | |
10061 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
10062 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 10063 | mode->crtc_clock, |
644db711 DV |
10064 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
10065 | mode->crtc_hsync_end, mode->crtc_htotal, | |
10066 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
10067 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
10068 | } | |
10069 | ||
c0b03411 DV |
10070 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
10071 | struct intel_crtc_config *pipe_config, | |
10072 | const char *context) | |
10073 | { | |
10074 | DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id, | |
10075 | context, pipe_name(crtc->pipe)); | |
10076 | ||
10077 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
10078 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
10079 | pipe_config->pipe_bpp, pipe_config->dither); | |
10080 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
10081 | pipe_config->has_pch_encoder, | |
10082 | pipe_config->fdi_lanes, | |
10083 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
10084 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
10085 | pipe_config->fdi_m_n.tu); | |
eb14cb74 VS |
10086 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
10087 | pipe_config->has_dp_encoder, | |
10088 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, | |
10089 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
10090 | pipe_config->dp_m_n.tu); | |
b95af8be VK |
10091 | |
10092 | DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", | |
10093 | pipe_config->has_dp_encoder, | |
10094 | pipe_config->dp_m2_n2.gmch_m, | |
10095 | pipe_config->dp_m2_n2.gmch_n, | |
10096 | pipe_config->dp_m2_n2.link_m, | |
10097 | pipe_config->dp_m2_n2.link_n, | |
10098 | pipe_config->dp_m2_n2.tu); | |
10099 | ||
c0b03411 DV |
10100 | DRM_DEBUG_KMS("requested mode:\n"); |
10101 | drm_mode_debug_printmodeline(&pipe_config->requested_mode); | |
10102 | DRM_DEBUG_KMS("adjusted mode:\n"); | |
10103 | drm_mode_debug_printmodeline(&pipe_config->adjusted_mode); | |
644db711 | 10104 | intel_dump_crtc_timings(&pipe_config->adjusted_mode); |
d71b8d4a | 10105 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
10106 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
10107 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
c0b03411 DV |
10108 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
10109 | pipe_config->gmch_pfit.control, | |
10110 | pipe_config->gmch_pfit.pgm_ratios, | |
10111 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 10112 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 10113 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
10114 | pipe_config->pch_pfit.size, |
10115 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 10116 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 10117 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
c0b03411 DV |
10118 | } |
10119 | ||
bc079e8b VS |
10120 | static bool encoders_cloneable(const struct intel_encoder *a, |
10121 | const struct intel_encoder *b) | |
accfc0c5 | 10122 | { |
bc079e8b VS |
10123 | /* masks could be asymmetric, so check both ways */ |
10124 | return a == b || (a->cloneable & (1 << b->type) && | |
10125 | b->cloneable & (1 << a->type)); | |
10126 | } | |
10127 | ||
10128 | static bool check_single_encoder_cloning(struct intel_crtc *crtc, | |
10129 | struct intel_encoder *encoder) | |
10130 | { | |
10131 | struct drm_device *dev = crtc->base.dev; | |
10132 | struct intel_encoder *source_encoder; | |
10133 | ||
b2784e15 | 10134 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b VS |
10135 | if (source_encoder->new_crtc != crtc) |
10136 | continue; | |
10137 | ||
10138 | if (!encoders_cloneable(encoder, source_encoder)) | |
10139 | return false; | |
10140 | } | |
10141 | ||
10142 | return true; | |
10143 | } | |
10144 | ||
10145 | static bool check_encoder_cloning(struct intel_crtc *crtc) | |
10146 | { | |
10147 | struct drm_device *dev = crtc->base.dev; | |
accfc0c5 DV |
10148 | struct intel_encoder *encoder; |
10149 | ||
b2784e15 | 10150 | for_each_intel_encoder(dev, encoder) { |
bc079e8b | 10151 | if (encoder->new_crtc != crtc) |
accfc0c5 DV |
10152 | continue; |
10153 | ||
bc079e8b VS |
10154 | if (!check_single_encoder_cloning(crtc, encoder)) |
10155 | return false; | |
accfc0c5 DV |
10156 | } |
10157 | ||
bc079e8b | 10158 | return true; |
accfc0c5 DV |
10159 | } |
10160 | ||
b8cecdf5 DV |
10161 | static struct intel_crtc_config * |
10162 | intel_modeset_pipe_config(struct drm_crtc *crtc, | |
4e53c2e0 | 10163 | struct drm_framebuffer *fb, |
b8cecdf5 | 10164 | struct drm_display_mode *mode) |
ee7b9f93 | 10165 | { |
7758a113 | 10166 | struct drm_device *dev = crtc->dev; |
7758a113 | 10167 | struct intel_encoder *encoder; |
b8cecdf5 | 10168 | struct intel_crtc_config *pipe_config; |
e29c22c0 DV |
10169 | int plane_bpp, ret = -EINVAL; |
10170 | bool retry = true; | |
ee7b9f93 | 10171 | |
bc079e8b | 10172 | if (!check_encoder_cloning(to_intel_crtc(crtc))) { |
accfc0c5 DV |
10173 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
10174 | return ERR_PTR(-EINVAL); | |
10175 | } | |
10176 | ||
b8cecdf5 DV |
10177 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
10178 | if (!pipe_config) | |
7758a113 DV |
10179 | return ERR_PTR(-ENOMEM); |
10180 | ||
b8cecdf5 DV |
10181 | drm_mode_copy(&pipe_config->adjusted_mode, mode); |
10182 | drm_mode_copy(&pipe_config->requested_mode, mode); | |
37327abd | 10183 | |
e143a21c DV |
10184 | pipe_config->cpu_transcoder = |
10185 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
c0d43d62 | 10186 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
b8cecdf5 | 10187 | |
2960bc9c ID |
10188 | /* |
10189 | * Sanitize sync polarity flags based on requested ones. If neither | |
10190 | * positive or negative polarity is requested, treat this as meaning | |
10191 | * negative polarity. | |
10192 | */ | |
10193 | if (!(pipe_config->adjusted_mode.flags & | |
10194 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) | |
10195 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; | |
10196 | ||
10197 | if (!(pipe_config->adjusted_mode.flags & | |
10198 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) | |
10199 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; | |
10200 | ||
050f7aeb DV |
10201 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
10202 | * plane pixel format and any sink constraints into account. Returns the | |
10203 | * source plane bpp so that dithering can be selected on mismatches | |
10204 | * after encoders and crtc also have had their say. */ | |
10205 | plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), | |
10206 | fb, pipe_config); | |
4e53c2e0 DV |
10207 | if (plane_bpp < 0) |
10208 | goto fail; | |
10209 | ||
e41a56be VS |
10210 | /* |
10211 | * Determine the real pipe dimensions. Note that stereo modes can | |
10212 | * increase the actual pipe size due to the frame doubling and | |
10213 | * insertion of additional space for blanks between the frame. This | |
10214 | * is stored in the crtc timings. We use the requested mode to do this | |
10215 | * computation to clearly distinguish it from the adjusted mode, which | |
10216 | * can be changed by the connectors in the below retry loop. | |
10217 | */ | |
10218 | drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE); | |
10219 | pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay; | |
10220 | pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay; | |
10221 | ||
e29c22c0 | 10222 | encoder_retry: |
ef1b460d | 10223 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 10224 | pipe_config->port_clock = 0; |
ef1b460d | 10225 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 10226 | |
135c81b8 | 10227 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
6ce70f5e | 10228 | drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE); |
135c81b8 | 10229 | |
7758a113 DV |
10230 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
10231 | * adjust it according to limitations or connector properties, and also | |
10232 | * a chance to reject the mode entirely. | |
47f1c6c9 | 10233 | */ |
b2784e15 | 10234 | for_each_intel_encoder(dev, encoder) { |
47f1c6c9 | 10235 | |
7758a113 DV |
10236 | if (&encoder->new_crtc->base != crtc) |
10237 | continue; | |
7ae89233 | 10238 | |
efea6e8e DV |
10239 | if (!(encoder->compute_config(encoder, pipe_config))) { |
10240 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
10241 | goto fail; |
10242 | } | |
ee7b9f93 | 10243 | } |
47f1c6c9 | 10244 | |
ff9a6750 DV |
10245 | /* Set default port clock if not overwritten by the encoder. Needs to be |
10246 | * done afterwards in case the encoder adjusts the mode. */ | |
10247 | if (!pipe_config->port_clock) | |
241bfc38 DL |
10248 | pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock |
10249 | * pipe_config->pixel_multiplier; | |
ff9a6750 | 10250 | |
a43f6e0f | 10251 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 10252 | if (ret < 0) { |
7758a113 DV |
10253 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
10254 | goto fail; | |
ee7b9f93 | 10255 | } |
e29c22c0 DV |
10256 | |
10257 | if (ret == RETRY) { | |
10258 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
10259 | ret = -EINVAL; | |
10260 | goto fail; | |
10261 | } | |
10262 | ||
10263 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
10264 | retry = false; | |
10265 | goto encoder_retry; | |
10266 | } | |
10267 | ||
4e53c2e0 DV |
10268 | pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; |
10269 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", | |
10270 | plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); | |
10271 | ||
b8cecdf5 | 10272 | return pipe_config; |
7758a113 | 10273 | fail: |
b8cecdf5 | 10274 | kfree(pipe_config); |
e29c22c0 | 10275 | return ERR_PTR(ret); |
ee7b9f93 | 10276 | } |
47f1c6c9 | 10277 | |
e2e1ed41 DV |
10278 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
10279 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ | |
10280 | static void | |
10281 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, | |
10282 | unsigned *prepare_pipes, unsigned *disable_pipes) | |
79e53945 JB |
10283 | { |
10284 | struct intel_crtc *intel_crtc; | |
e2e1ed41 DV |
10285 | struct drm_device *dev = crtc->dev; |
10286 | struct intel_encoder *encoder; | |
10287 | struct intel_connector *connector; | |
10288 | struct drm_crtc *tmp_crtc; | |
79e53945 | 10289 | |
e2e1ed41 | 10290 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
79e53945 | 10291 | |
e2e1ed41 DV |
10292 | /* Check which crtcs have changed outputs connected to them, these need |
10293 | * to be part of the prepare_pipes mask. We don't (yet) support global | |
10294 | * modeset across multiple crtcs, so modeset_pipes will only have one | |
10295 | * bit set at most. */ | |
10296 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
10297 | base.head) { | |
10298 | if (connector->base.encoder == &connector->new_encoder->base) | |
10299 | continue; | |
79e53945 | 10300 | |
e2e1ed41 DV |
10301 | if (connector->base.encoder) { |
10302 | tmp_crtc = connector->base.encoder->crtc; | |
10303 | ||
10304 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
10305 | } | |
10306 | ||
10307 | if (connector->new_encoder) | |
10308 | *prepare_pipes |= | |
10309 | 1 << connector->new_encoder->new_crtc->pipe; | |
79e53945 JB |
10310 | } |
10311 | ||
b2784e15 | 10312 | for_each_intel_encoder(dev, encoder) { |
e2e1ed41 DV |
10313 | if (encoder->base.crtc == &encoder->new_crtc->base) |
10314 | continue; | |
10315 | ||
10316 | if (encoder->base.crtc) { | |
10317 | tmp_crtc = encoder->base.crtc; | |
10318 | ||
10319 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
10320 | } | |
10321 | ||
10322 | if (encoder->new_crtc) | |
10323 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; | |
80824003 JB |
10324 | } |
10325 | ||
7668851f | 10326 | /* Check for pipes that will be enabled/disabled ... */ |
d3fcc808 | 10327 | for_each_intel_crtc(dev, intel_crtc) { |
7668851f | 10328 | if (intel_crtc->base.enabled == intel_crtc->new_enabled) |
e2e1ed41 | 10329 | continue; |
7e7d76c3 | 10330 | |
7668851f | 10331 | if (!intel_crtc->new_enabled) |
e2e1ed41 | 10332 | *disable_pipes |= 1 << intel_crtc->pipe; |
7668851f VS |
10333 | else |
10334 | *prepare_pipes |= 1 << intel_crtc->pipe; | |
7e7d76c3 JB |
10335 | } |
10336 | ||
e2e1ed41 DV |
10337 | |
10338 | /* set_mode is also used to update properties on life display pipes. */ | |
10339 | intel_crtc = to_intel_crtc(crtc); | |
7668851f | 10340 | if (intel_crtc->new_enabled) |
e2e1ed41 DV |
10341 | *prepare_pipes |= 1 << intel_crtc->pipe; |
10342 | ||
b6c5164d DV |
10343 | /* |
10344 | * For simplicity do a full modeset on any pipe where the output routing | |
10345 | * changed. We could be more clever, but that would require us to be | |
10346 | * more careful with calling the relevant encoder->mode_set functions. | |
10347 | */ | |
e2e1ed41 DV |
10348 | if (*prepare_pipes) |
10349 | *modeset_pipes = *prepare_pipes; | |
10350 | ||
10351 | /* ... and mask these out. */ | |
10352 | *modeset_pipes &= ~(*disable_pipes); | |
10353 | *prepare_pipes &= ~(*disable_pipes); | |
b6c5164d DV |
10354 | |
10355 | /* | |
10356 | * HACK: We don't (yet) fully support global modesets. intel_set_config | |
10357 | * obies this rule, but the modeset restore mode of | |
10358 | * intel_modeset_setup_hw_state does not. | |
10359 | */ | |
10360 | *modeset_pipes &= 1 << intel_crtc->pipe; | |
10361 | *prepare_pipes &= 1 << intel_crtc->pipe; | |
e3641d3f DV |
10362 | |
10363 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", | |
10364 | *modeset_pipes, *prepare_pipes, *disable_pipes); | |
47f1c6c9 | 10365 | } |
79e53945 | 10366 | |
ea9d758d | 10367 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 10368 | { |
ea9d758d | 10369 | struct drm_encoder *encoder; |
f6e5b160 | 10370 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 10371 | |
ea9d758d DV |
10372 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
10373 | if (encoder->crtc == crtc) | |
10374 | return true; | |
10375 | ||
10376 | return false; | |
10377 | } | |
10378 | ||
10379 | static void | |
10380 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) | |
10381 | { | |
10382 | struct intel_encoder *intel_encoder; | |
10383 | struct intel_crtc *intel_crtc; | |
10384 | struct drm_connector *connector; | |
10385 | ||
b2784e15 | 10386 | for_each_intel_encoder(dev, intel_encoder) { |
ea9d758d DV |
10387 | if (!intel_encoder->base.crtc) |
10388 | continue; | |
10389 | ||
10390 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
10391 | ||
10392 | if (prepare_pipes & (1 << intel_crtc->pipe)) | |
10393 | intel_encoder->connectors_active = false; | |
10394 | } | |
10395 | ||
10396 | intel_modeset_commit_output_state(dev); | |
10397 | ||
7668851f | 10398 | /* Double check state. */ |
d3fcc808 | 10399 | for_each_intel_crtc(dev, intel_crtc) { |
7668851f | 10400 | WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base)); |
7bd0a8e7 VS |
10401 | WARN_ON(intel_crtc->new_config && |
10402 | intel_crtc->new_config != &intel_crtc->config); | |
10403 | WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config); | |
ea9d758d DV |
10404 | } |
10405 | ||
10406 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
10407 | if (!connector->encoder || !connector->encoder->crtc) | |
10408 | continue; | |
10409 | ||
10410 | intel_crtc = to_intel_crtc(connector->encoder->crtc); | |
10411 | ||
10412 | if (prepare_pipes & (1 << intel_crtc->pipe)) { | |
68d34720 DV |
10413 | struct drm_property *dpms_property = |
10414 | dev->mode_config.dpms_property; | |
10415 | ||
ea9d758d | 10416 | connector->dpms = DRM_MODE_DPMS_ON; |
662595df | 10417 | drm_object_property_set_value(&connector->base, |
68d34720 DV |
10418 | dpms_property, |
10419 | DRM_MODE_DPMS_ON); | |
ea9d758d DV |
10420 | |
10421 | intel_encoder = to_intel_encoder(connector->encoder); | |
10422 | intel_encoder->connectors_active = true; | |
10423 | } | |
10424 | } | |
10425 | ||
10426 | } | |
10427 | ||
3bd26263 | 10428 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 10429 | { |
3bd26263 | 10430 | int diff; |
f1f644dc JB |
10431 | |
10432 | if (clock1 == clock2) | |
10433 | return true; | |
10434 | ||
10435 | if (!clock1 || !clock2) | |
10436 | return false; | |
10437 | ||
10438 | diff = abs(clock1 - clock2); | |
10439 | ||
10440 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
10441 | return true; | |
10442 | ||
10443 | return false; | |
10444 | } | |
10445 | ||
25c5b266 DV |
10446 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
10447 | list_for_each_entry((intel_crtc), \ | |
10448 | &(dev)->mode_config.crtc_list, \ | |
10449 | base.head) \ | |
0973f18f | 10450 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 10451 | |
0e8ffe1b | 10452 | static bool |
2fa2fe9a DV |
10453 | intel_pipe_config_compare(struct drm_device *dev, |
10454 | struct intel_crtc_config *current_config, | |
0e8ffe1b DV |
10455 | struct intel_crtc_config *pipe_config) |
10456 | { | |
66e985c0 DV |
10457 | #define PIPE_CONF_CHECK_X(name) \ |
10458 | if (current_config->name != pipe_config->name) { \ | |
10459 | DRM_ERROR("mismatch in " #name " " \ | |
10460 | "(expected 0x%08x, found 0x%08x)\n", \ | |
10461 | current_config->name, \ | |
10462 | pipe_config->name); \ | |
10463 | return false; \ | |
10464 | } | |
10465 | ||
08a24034 DV |
10466 | #define PIPE_CONF_CHECK_I(name) \ |
10467 | if (current_config->name != pipe_config->name) { \ | |
10468 | DRM_ERROR("mismatch in " #name " " \ | |
10469 | "(expected %i, found %i)\n", \ | |
10470 | current_config->name, \ | |
10471 | pipe_config->name); \ | |
10472 | return false; \ | |
88adfff1 DV |
10473 | } |
10474 | ||
b95af8be VK |
10475 | /* This is required for BDW+ where there is only one set of registers for |
10476 | * switching between high and low RR. | |
10477 | * This macro can be used whenever a comparison has to be made between one | |
10478 | * hw state and multiple sw state variables. | |
10479 | */ | |
10480 | #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ | |
10481 | if ((current_config->name != pipe_config->name) && \ | |
10482 | (current_config->alt_name != pipe_config->name)) { \ | |
10483 | DRM_ERROR("mismatch in " #name " " \ | |
10484 | "(expected %i or %i, found %i)\n", \ | |
10485 | current_config->name, \ | |
10486 | current_config->alt_name, \ | |
10487 | pipe_config->name); \ | |
10488 | return false; \ | |
10489 | } | |
10490 | ||
1bd1bd80 DV |
10491 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
10492 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
6f02488e | 10493 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
10494 | "(expected %i, found %i)\n", \ |
10495 | current_config->name & (mask), \ | |
10496 | pipe_config->name & (mask)); \ | |
10497 | return false; \ | |
10498 | } | |
10499 | ||
5e550656 VS |
10500 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
10501 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
10502 | DRM_ERROR("mismatch in " #name " " \ | |
10503 | "(expected %i, found %i)\n", \ | |
10504 | current_config->name, \ | |
10505 | pipe_config->name); \ | |
10506 | return false; \ | |
10507 | } | |
10508 | ||
bb760063 DV |
10509 | #define PIPE_CONF_QUIRK(quirk) \ |
10510 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
10511 | ||
eccb140b DV |
10512 | PIPE_CONF_CHECK_I(cpu_transcoder); |
10513 | ||
08a24034 DV |
10514 | PIPE_CONF_CHECK_I(has_pch_encoder); |
10515 | PIPE_CONF_CHECK_I(fdi_lanes); | |
72419203 DV |
10516 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
10517 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); | |
10518 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); | |
10519 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); | |
10520 | PIPE_CONF_CHECK_I(fdi_m_n.tu); | |
08a24034 | 10521 | |
eb14cb74 | 10522 | PIPE_CONF_CHECK_I(has_dp_encoder); |
b95af8be VK |
10523 | |
10524 | if (INTEL_INFO(dev)->gen < 8) { | |
10525 | PIPE_CONF_CHECK_I(dp_m_n.gmch_m); | |
10526 | PIPE_CONF_CHECK_I(dp_m_n.gmch_n); | |
10527 | PIPE_CONF_CHECK_I(dp_m_n.link_m); | |
10528 | PIPE_CONF_CHECK_I(dp_m_n.link_n); | |
10529 | PIPE_CONF_CHECK_I(dp_m_n.tu); | |
10530 | ||
10531 | if (current_config->has_drrs) { | |
10532 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m); | |
10533 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n); | |
10534 | PIPE_CONF_CHECK_I(dp_m2_n2.link_m); | |
10535 | PIPE_CONF_CHECK_I(dp_m2_n2.link_n); | |
10536 | PIPE_CONF_CHECK_I(dp_m2_n2.tu); | |
10537 | } | |
10538 | } else { | |
10539 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m); | |
10540 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n); | |
10541 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m); | |
10542 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n); | |
10543 | PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu); | |
10544 | } | |
eb14cb74 | 10545 | |
1bd1bd80 DV |
10546 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); |
10547 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); | |
10548 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start); | |
10549 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end); | |
10550 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start); | |
10551 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end); | |
10552 | ||
10553 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay); | |
10554 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal); | |
10555 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start); | |
10556 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end); | |
10557 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start); | |
10558 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end); | |
10559 | ||
c93f54cf | 10560 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 10561 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 DV |
10562 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
10563 | IS_VALLEYVIEW(dev)) | |
10564 | PIPE_CONF_CHECK_I(limited_color_range); | |
6c49f241 | 10565 | |
9ed109a7 DV |
10566 | PIPE_CONF_CHECK_I(has_audio); |
10567 | ||
1bd1bd80 DV |
10568 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
10569 | DRM_MODE_FLAG_INTERLACE); | |
10570 | ||
bb760063 DV |
10571 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
10572 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
10573 | DRM_MODE_FLAG_PHSYNC); | |
10574 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
10575 | DRM_MODE_FLAG_NHSYNC); | |
10576 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
10577 | DRM_MODE_FLAG_PVSYNC); | |
10578 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
10579 | DRM_MODE_FLAG_NVSYNC); | |
10580 | } | |
045ac3b5 | 10581 | |
37327abd VS |
10582 | PIPE_CONF_CHECK_I(pipe_src_w); |
10583 | PIPE_CONF_CHECK_I(pipe_src_h); | |
1bd1bd80 | 10584 | |
9953599b DV |
10585 | /* |
10586 | * FIXME: BIOS likes to set up a cloned config with lvds+external | |
10587 | * screen. Since we don't yet re-compute the pipe config when moving | |
10588 | * just the lvds port away to another pipe the sw tracking won't match. | |
10589 | * | |
10590 | * Proper atomic modesets with recomputed global state will fix this. | |
10591 | * Until then just don't check gmch state for inherited modes. | |
10592 | */ | |
10593 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) { | |
10594 | PIPE_CONF_CHECK_I(gmch_pfit.control); | |
10595 | /* pfit ratios are autocomputed by the hw on gen4+ */ | |
10596 | if (INTEL_INFO(dev)->gen < 4) | |
10597 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
10598 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); | |
10599 | } | |
10600 | ||
fd4daa9c CW |
10601 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
10602 | if (current_config->pch_pfit.enabled) { | |
10603 | PIPE_CONF_CHECK_I(pch_pfit.pos); | |
10604 | PIPE_CONF_CHECK_I(pch_pfit.size); | |
10605 | } | |
2fa2fe9a | 10606 | |
e59150dc JB |
10607 | /* BDW+ don't expose a synchronous way to read the state */ |
10608 | if (IS_HASWELL(dev)) | |
10609 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 10610 | |
282740f7 VS |
10611 | PIPE_CONF_CHECK_I(double_wide); |
10612 | ||
26804afd DV |
10613 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
10614 | ||
c0d43d62 | 10615 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 10616 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 10617 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
10618 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
10619 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 10620 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
c0d43d62 | 10621 | |
42571aef VS |
10622 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
10623 | PIPE_CONF_CHECK_I(pipe_bpp); | |
10624 | ||
a9a7e98a JB |
10625 | PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock); |
10626 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); | |
5e550656 | 10627 | |
66e985c0 | 10628 | #undef PIPE_CONF_CHECK_X |
08a24034 | 10629 | #undef PIPE_CONF_CHECK_I |
b95af8be | 10630 | #undef PIPE_CONF_CHECK_I_ALT |
1bd1bd80 | 10631 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 10632 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 10633 | #undef PIPE_CONF_QUIRK |
88adfff1 | 10634 | |
0e8ffe1b DV |
10635 | return true; |
10636 | } | |
10637 | ||
91d1b4bd DV |
10638 | static void |
10639 | check_connector_state(struct drm_device *dev) | |
8af6cf88 | 10640 | { |
8af6cf88 DV |
10641 | struct intel_connector *connector; |
10642 | ||
10643 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
10644 | base.head) { | |
10645 | /* This also checks the encoder/connector hw state with the | |
10646 | * ->get_hw_state callbacks. */ | |
10647 | intel_connector_check_state(connector); | |
10648 | ||
10649 | WARN(&connector->new_encoder->base != connector->base.encoder, | |
10650 | "connector's staged encoder doesn't match current encoder\n"); | |
10651 | } | |
91d1b4bd DV |
10652 | } |
10653 | ||
10654 | static void | |
10655 | check_encoder_state(struct drm_device *dev) | |
10656 | { | |
10657 | struct intel_encoder *encoder; | |
10658 | struct intel_connector *connector; | |
8af6cf88 | 10659 | |
b2784e15 | 10660 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 DV |
10661 | bool enabled = false; |
10662 | bool active = false; | |
10663 | enum pipe pipe, tracked_pipe; | |
10664 | ||
10665 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
10666 | encoder->base.base.id, | |
8e329a03 | 10667 | encoder->base.name); |
8af6cf88 DV |
10668 | |
10669 | WARN(&encoder->new_crtc->base != encoder->base.crtc, | |
10670 | "encoder's stage crtc doesn't match current crtc\n"); | |
10671 | WARN(encoder->connectors_active && !encoder->base.crtc, | |
10672 | "encoder's active_connectors set, but no crtc\n"); | |
10673 | ||
10674 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
10675 | base.head) { | |
10676 | if (connector->base.encoder != &encoder->base) | |
10677 | continue; | |
10678 | enabled = true; | |
10679 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
10680 | active = true; | |
10681 | } | |
0e32b39c DA |
10682 | /* |
10683 | * for MST connectors if we unplug the connector is gone | |
10684 | * away but the encoder is still connected to a crtc | |
10685 | * until a modeset happens in response to the hotplug. | |
10686 | */ | |
10687 | if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST) | |
10688 | continue; | |
10689 | ||
8af6cf88 DV |
10690 | WARN(!!encoder->base.crtc != enabled, |
10691 | "encoder's enabled state mismatch " | |
10692 | "(expected %i, found %i)\n", | |
10693 | !!encoder->base.crtc, enabled); | |
10694 | WARN(active && !encoder->base.crtc, | |
10695 | "active encoder with no crtc\n"); | |
10696 | ||
10697 | WARN(encoder->connectors_active != active, | |
10698 | "encoder's computed active state doesn't match tracked active state " | |
10699 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
10700 | ||
10701 | active = encoder->get_hw_state(encoder, &pipe); | |
10702 | WARN(active != encoder->connectors_active, | |
10703 | "encoder's hw state doesn't match sw tracking " | |
10704 | "(expected %i, found %i)\n", | |
10705 | encoder->connectors_active, active); | |
10706 | ||
10707 | if (!encoder->base.crtc) | |
10708 | continue; | |
10709 | ||
10710 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
10711 | WARN(active && pipe != tracked_pipe, | |
10712 | "active encoder's pipe doesn't match" | |
10713 | "(expected %i, found %i)\n", | |
10714 | tracked_pipe, pipe); | |
10715 | ||
10716 | } | |
91d1b4bd DV |
10717 | } |
10718 | ||
10719 | static void | |
10720 | check_crtc_state(struct drm_device *dev) | |
10721 | { | |
fbee40df | 10722 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
10723 | struct intel_crtc *crtc; |
10724 | struct intel_encoder *encoder; | |
10725 | struct intel_crtc_config pipe_config; | |
8af6cf88 | 10726 | |
d3fcc808 | 10727 | for_each_intel_crtc(dev, crtc) { |
8af6cf88 DV |
10728 | bool enabled = false; |
10729 | bool active = false; | |
10730 | ||
045ac3b5 JB |
10731 | memset(&pipe_config, 0, sizeof(pipe_config)); |
10732 | ||
8af6cf88 DV |
10733 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
10734 | crtc->base.base.id); | |
10735 | ||
10736 | WARN(crtc->active && !crtc->base.enabled, | |
10737 | "active crtc, but not enabled in sw tracking\n"); | |
10738 | ||
b2784e15 | 10739 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 DV |
10740 | if (encoder->base.crtc != &crtc->base) |
10741 | continue; | |
10742 | enabled = true; | |
10743 | if (encoder->connectors_active) | |
10744 | active = true; | |
10745 | } | |
6c49f241 | 10746 | |
8af6cf88 DV |
10747 | WARN(active != crtc->active, |
10748 | "crtc's computed active state doesn't match tracked active state " | |
10749 | "(expected %i, found %i)\n", active, crtc->active); | |
10750 | WARN(enabled != crtc->base.enabled, | |
10751 | "crtc's computed enabled state doesn't match tracked enabled state " | |
10752 | "(expected %i, found %i)\n", enabled, crtc->base.enabled); | |
10753 | ||
0e8ffe1b DV |
10754 | active = dev_priv->display.get_pipe_config(crtc, |
10755 | &pipe_config); | |
d62cf62a DV |
10756 | |
10757 | /* hw state is inconsistent with the pipe A quirk */ | |
10758 | if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
10759 | active = crtc->active; | |
10760 | ||
b2784e15 | 10761 | for_each_intel_encoder(dev, encoder) { |
3eaba51c | 10762 | enum pipe pipe; |
6c49f241 DV |
10763 | if (encoder->base.crtc != &crtc->base) |
10764 | continue; | |
1d37b689 | 10765 | if (encoder->get_hw_state(encoder, &pipe)) |
6c49f241 DV |
10766 | encoder->get_config(encoder, &pipe_config); |
10767 | } | |
10768 | ||
0e8ffe1b DV |
10769 | WARN(crtc->active != active, |
10770 | "crtc active state doesn't match with hw state " | |
10771 | "(expected %i, found %i)\n", crtc->active, active); | |
10772 | ||
c0b03411 DV |
10773 | if (active && |
10774 | !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) { | |
10775 | WARN(1, "pipe state doesn't match!\n"); | |
10776 | intel_dump_pipe_config(crtc, &pipe_config, | |
10777 | "[hw state]"); | |
10778 | intel_dump_pipe_config(crtc, &crtc->config, | |
10779 | "[sw state]"); | |
10780 | } | |
8af6cf88 DV |
10781 | } |
10782 | } | |
10783 | ||
91d1b4bd DV |
10784 | static void |
10785 | check_shared_dpll_state(struct drm_device *dev) | |
10786 | { | |
fbee40df | 10787 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
10788 | struct intel_crtc *crtc; |
10789 | struct intel_dpll_hw_state dpll_hw_state; | |
10790 | int i; | |
5358901f DV |
10791 | |
10792 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
10793 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
10794 | int enabled_crtcs = 0, active_crtcs = 0; | |
10795 | bool active; | |
10796 | ||
10797 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
10798 | ||
10799 | DRM_DEBUG_KMS("%s\n", pll->name); | |
10800 | ||
10801 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
10802 | ||
10803 | WARN(pll->active > pll->refcount, | |
10804 | "more active pll users than references: %i vs %i\n", | |
10805 | pll->active, pll->refcount); | |
10806 | WARN(pll->active && !pll->on, | |
10807 | "pll in active use but not on in sw tracking\n"); | |
35c95375 DV |
10808 | WARN(pll->on && !pll->active, |
10809 | "pll in on but not on in use in sw tracking\n"); | |
5358901f DV |
10810 | WARN(pll->on != active, |
10811 | "pll on state mismatch (expected %i, found %i)\n", | |
10812 | pll->on, active); | |
10813 | ||
d3fcc808 | 10814 | for_each_intel_crtc(dev, crtc) { |
5358901f DV |
10815 | if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll) |
10816 | enabled_crtcs++; | |
10817 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
10818 | active_crtcs++; | |
10819 | } | |
10820 | WARN(pll->active != active_crtcs, | |
10821 | "pll active crtcs mismatch (expected %i, found %i)\n", | |
10822 | pll->active, active_crtcs); | |
10823 | WARN(pll->refcount != enabled_crtcs, | |
10824 | "pll enabled crtcs mismatch (expected %i, found %i)\n", | |
10825 | pll->refcount, enabled_crtcs); | |
66e985c0 DV |
10826 | |
10827 | WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state, | |
10828 | sizeof(dpll_hw_state)), | |
10829 | "pll hw state mismatch\n"); | |
5358901f | 10830 | } |
8af6cf88 DV |
10831 | } |
10832 | ||
91d1b4bd DV |
10833 | void |
10834 | intel_modeset_check_state(struct drm_device *dev) | |
10835 | { | |
10836 | check_connector_state(dev); | |
10837 | check_encoder_state(dev); | |
10838 | check_crtc_state(dev); | |
10839 | check_shared_dpll_state(dev); | |
10840 | } | |
10841 | ||
18442d08 VS |
10842 | void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, |
10843 | int dotclock) | |
10844 | { | |
10845 | /* | |
10846 | * FDI already provided one idea for the dotclock. | |
10847 | * Yell if the encoder disagrees. | |
10848 | */ | |
241bfc38 | 10849 | WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock), |
18442d08 | 10850 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
241bfc38 | 10851 | pipe_config->adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
10852 | } |
10853 | ||
80715b2f VS |
10854 | static void update_scanline_offset(struct intel_crtc *crtc) |
10855 | { | |
10856 | struct drm_device *dev = crtc->base.dev; | |
10857 | ||
10858 | /* | |
10859 | * The scanline counter increments at the leading edge of hsync. | |
10860 | * | |
10861 | * On most platforms it starts counting from vtotal-1 on the | |
10862 | * first active line. That means the scanline counter value is | |
10863 | * always one less than what we would expect. Ie. just after | |
10864 | * start of vblank, which also occurs at start of hsync (on the | |
10865 | * last active line), the scanline counter will read vblank_start-1. | |
10866 | * | |
10867 | * On gen2 the scanline counter starts counting from 1 instead | |
10868 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
10869 | * to keep the value positive), instead of adding one. | |
10870 | * | |
10871 | * On HSW+ the behaviour of the scanline counter depends on the output | |
10872 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
10873 | * there's an extra 1 line difference. So we need to add two instead of | |
10874 | * one to the value. | |
10875 | */ | |
10876 | if (IS_GEN2(dev)) { | |
10877 | const struct drm_display_mode *mode = &crtc->config.adjusted_mode; | |
10878 | int vtotal; | |
10879 | ||
10880 | vtotal = mode->crtc_vtotal; | |
10881 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
10882 | vtotal /= 2; | |
10883 | ||
10884 | crtc->scanline_offset = vtotal - 1; | |
10885 | } else if (HAS_DDI(dev) && | |
10886 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) { | |
10887 | crtc->scanline_offset = 2; | |
10888 | } else | |
10889 | crtc->scanline_offset = 1; | |
10890 | } | |
10891 | ||
f30da187 DV |
10892 | static int __intel_set_mode(struct drm_crtc *crtc, |
10893 | struct drm_display_mode *mode, | |
10894 | int x, int y, struct drm_framebuffer *fb) | |
a6778b3c DV |
10895 | { |
10896 | struct drm_device *dev = crtc->dev; | |
fbee40df | 10897 | struct drm_i915_private *dev_priv = dev->dev_private; |
4b4b9238 | 10898 | struct drm_display_mode *saved_mode; |
b8cecdf5 | 10899 | struct intel_crtc_config *pipe_config = NULL; |
25c5b266 DV |
10900 | struct intel_crtc *intel_crtc; |
10901 | unsigned disable_pipes, prepare_pipes, modeset_pipes; | |
c0c36b94 | 10902 | int ret = 0; |
a6778b3c | 10903 | |
4b4b9238 | 10904 | saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL); |
c0c36b94 CW |
10905 | if (!saved_mode) |
10906 | return -ENOMEM; | |
a6778b3c | 10907 | |
e2e1ed41 | 10908 | intel_modeset_affected_pipes(crtc, &modeset_pipes, |
25c5b266 DV |
10909 | &prepare_pipes, &disable_pipes); |
10910 | ||
3ac18232 | 10911 | *saved_mode = crtc->mode; |
a6778b3c | 10912 | |
25c5b266 DV |
10913 | /* Hack: Because we don't (yet) support global modeset on multiple |
10914 | * crtcs, we don't keep track of the new mode for more than one crtc. | |
10915 | * Hence simply check whether any bit is set in modeset_pipes in all the | |
10916 | * pieces of code that are not yet converted to deal with mutliple crtcs | |
10917 | * changing their mode at the same time. */ | |
25c5b266 | 10918 | if (modeset_pipes) { |
4e53c2e0 | 10919 | pipe_config = intel_modeset_pipe_config(crtc, fb, mode); |
b8cecdf5 DV |
10920 | if (IS_ERR(pipe_config)) { |
10921 | ret = PTR_ERR(pipe_config); | |
10922 | pipe_config = NULL; | |
10923 | ||
3ac18232 | 10924 | goto out; |
25c5b266 | 10925 | } |
c0b03411 DV |
10926 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
10927 | "[modeset]"); | |
50741abc | 10928 | to_intel_crtc(crtc)->new_config = pipe_config; |
25c5b266 | 10929 | } |
a6778b3c | 10930 | |
30a970c6 JB |
10931 | /* |
10932 | * See if the config requires any additional preparation, e.g. | |
10933 | * to adjust global state with pipes off. We need to do this | |
10934 | * here so we can get the modeset_pipe updated config for the new | |
10935 | * mode set on this crtc. For other crtcs we need to use the | |
10936 | * adjusted_mode bits in the crtc directly. | |
10937 | */ | |
c164f833 | 10938 | if (IS_VALLEYVIEW(dev)) { |
2f2d7aa1 | 10939 | valleyview_modeset_global_pipes(dev, &prepare_pipes); |
30a970c6 | 10940 | |
c164f833 VS |
10941 | /* may have added more to prepare_pipes than we should */ |
10942 | prepare_pipes &= ~disable_pipes; | |
10943 | } | |
10944 | ||
460da916 DV |
10945 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
10946 | intel_crtc_disable(&intel_crtc->base); | |
10947 | ||
ea9d758d DV |
10948 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
10949 | if (intel_crtc->base.enabled) | |
10950 | dev_priv->display.crtc_disable(&intel_crtc->base); | |
10951 | } | |
a6778b3c | 10952 | |
6c4c86f5 DV |
10953 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
10954 | * to set it here already despite that we pass it down the callchain. | |
f6e5b160 | 10955 | */ |
b8cecdf5 | 10956 | if (modeset_pipes) { |
25c5b266 | 10957 | crtc->mode = *mode; |
b8cecdf5 DV |
10958 | /* mode_set/enable/disable functions rely on a correct pipe |
10959 | * config. */ | |
10960 | to_intel_crtc(crtc)->config = *pipe_config; | |
50741abc | 10961 | to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config; |
c326c0a9 VS |
10962 | |
10963 | /* | |
10964 | * Calculate and store various constants which | |
10965 | * are later needed by vblank and swap-completion | |
10966 | * timestamping. They are derived from true hwmode. | |
10967 | */ | |
10968 | drm_calc_timestamping_constants(crtc, | |
10969 | &pipe_config->adjusted_mode); | |
b8cecdf5 | 10970 | } |
7758a113 | 10971 | |
ea9d758d DV |
10972 | /* Only after disabling all output pipelines that will be changed can we |
10973 | * update the the output configuration. */ | |
10974 | intel_modeset_update_state(dev, prepare_pipes); | |
f6e5b160 | 10975 | |
47fab737 DV |
10976 | if (dev_priv->display.modeset_global_resources) |
10977 | dev_priv->display.modeset_global_resources(dev); | |
10978 | ||
a6778b3c DV |
10979 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
10980 | * on the DPLL. | |
f6e5b160 | 10981 | */ |
25c5b266 | 10982 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
2ff8fde1 MR |
10983 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
10984 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb); | |
10985 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
4c10794f DV |
10986 | |
10987 | mutex_lock(&dev->struct_mutex); | |
10988 | ret = intel_pin_and_fence_fb_obj(dev, | |
a071fa00 | 10989 | obj, |
4c10794f DV |
10990 | NULL); |
10991 | if (ret != 0) { | |
10992 | DRM_ERROR("pin & fence failed\n"); | |
10993 | mutex_unlock(&dev->struct_mutex); | |
10994 | goto done; | |
10995 | } | |
2ff8fde1 | 10996 | if (old_fb) |
a071fa00 | 10997 | intel_unpin_fb_obj(old_obj); |
a071fa00 DV |
10998 | i915_gem_track_fb(old_obj, obj, |
10999 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe)); | |
4c10794f DV |
11000 | mutex_unlock(&dev->struct_mutex); |
11001 | ||
11002 | crtc->primary->fb = fb; | |
11003 | crtc->x = x; | |
11004 | crtc->y = y; | |
11005 | ||
4271b753 DV |
11006 | ret = dev_priv->display.crtc_mode_set(&intel_crtc->base, |
11007 | x, y, fb); | |
c0c36b94 CW |
11008 | if (ret) |
11009 | goto done; | |
a6778b3c DV |
11010 | } |
11011 | ||
11012 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
80715b2f VS |
11013 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
11014 | update_scanline_offset(intel_crtc); | |
11015 | ||
25c5b266 | 11016 | dev_priv->display.crtc_enable(&intel_crtc->base); |
80715b2f | 11017 | } |
a6778b3c | 11018 | |
a6778b3c DV |
11019 | /* FIXME: add subpixel order */ |
11020 | done: | |
4b4b9238 | 11021 | if (ret && crtc->enabled) |
3ac18232 | 11022 | crtc->mode = *saved_mode; |
a6778b3c | 11023 | |
3ac18232 | 11024 | out: |
b8cecdf5 | 11025 | kfree(pipe_config); |
3ac18232 | 11026 | kfree(saved_mode); |
a6778b3c | 11027 | return ret; |
f6e5b160 CW |
11028 | } |
11029 | ||
e7457a9a DL |
11030 | static int intel_set_mode(struct drm_crtc *crtc, |
11031 | struct drm_display_mode *mode, | |
11032 | int x, int y, struct drm_framebuffer *fb) | |
f30da187 DV |
11033 | { |
11034 | int ret; | |
11035 | ||
11036 | ret = __intel_set_mode(crtc, mode, x, y, fb); | |
11037 | ||
11038 | if (ret == 0) | |
11039 | intel_modeset_check_state(crtc->dev); | |
11040 | ||
11041 | return ret; | |
11042 | } | |
11043 | ||
c0c36b94 CW |
11044 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
11045 | { | |
f4510a27 | 11046 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb); |
c0c36b94 CW |
11047 | } |
11048 | ||
25c5b266 DV |
11049 | #undef for_each_intel_crtc_masked |
11050 | ||
d9e55608 DV |
11051 | static void intel_set_config_free(struct intel_set_config *config) |
11052 | { | |
11053 | if (!config) | |
11054 | return; | |
11055 | ||
1aa4b628 DV |
11056 | kfree(config->save_connector_encoders); |
11057 | kfree(config->save_encoder_crtcs); | |
7668851f | 11058 | kfree(config->save_crtc_enabled); |
d9e55608 DV |
11059 | kfree(config); |
11060 | } | |
11061 | ||
85f9eb71 DV |
11062 | static int intel_set_config_save_state(struct drm_device *dev, |
11063 | struct intel_set_config *config) | |
11064 | { | |
7668851f | 11065 | struct drm_crtc *crtc; |
85f9eb71 DV |
11066 | struct drm_encoder *encoder; |
11067 | struct drm_connector *connector; | |
11068 | int count; | |
11069 | ||
7668851f VS |
11070 | config->save_crtc_enabled = |
11071 | kcalloc(dev->mode_config.num_crtc, | |
11072 | sizeof(bool), GFP_KERNEL); | |
11073 | if (!config->save_crtc_enabled) | |
11074 | return -ENOMEM; | |
11075 | ||
1aa4b628 DV |
11076 | config->save_encoder_crtcs = |
11077 | kcalloc(dev->mode_config.num_encoder, | |
11078 | sizeof(struct drm_crtc *), GFP_KERNEL); | |
11079 | if (!config->save_encoder_crtcs) | |
85f9eb71 DV |
11080 | return -ENOMEM; |
11081 | ||
1aa4b628 DV |
11082 | config->save_connector_encoders = |
11083 | kcalloc(dev->mode_config.num_connector, | |
11084 | sizeof(struct drm_encoder *), GFP_KERNEL); | |
11085 | if (!config->save_connector_encoders) | |
85f9eb71 DV |
11086 | return -ENOMEM; |
11087 | ||
11088 | /* Copy data. Note that driver private data is not affected. | |
11089 | * Should anything bad happen only the expected state is | |
11090 | * restored, not the drivers personal bookkeeping. | |
11091 | */ | |
7668851f | 11092 | count = 0; |
70e1e0ec | 11093 | for_each_crtc(dev, crtc) { |
7668851f VS |
11094 | config->save_crtc_enabled[count++] = crtc->enabled; |
11095 | } | |
11096 | ||
85f9eb71 DV |
11097 | count = 0; |
11098 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1aa4b628 | 11099 | config->save_encoder_crtcs[count++] = encoder->crtc; |
85f9eb71 DV |
11100 | } |
11101 | ||
11102 | count = 0; | |
11103 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1aa4b628 | 11104 | config->save_connector_encoders[count++] = connector->encoder; |
85f9eb71 DV |
11105 | } |
11106 | ||
11107 | return 0; | |
11108 | } | |
11109 | ||
11110 | static void intel_set_config_restore_state(struct drm_device *dev, | |
11111 | struct intel_set_config *config) | |
11112 | { | |
7668851f | 11113 | struct intel_crtc *crtc; |
9a935856 DV |
11114 | struct intel_encoder *encoder; |
11115 | struct intel_connector *connector; | |
85f9eb71 DV |
11116 | int count; |
11117 | ||
7668851f | 11118 | count = 0; |
d3fcc808 | 11119 | for_each_intel_crtc(dev, crtc) { |
7668851f | 11120 | crtc->new_enabled = config->save_crtc_enabled[count++]; |
7bd0a8e7 VS |
11121 | |
11122 | if (crtc->new_enabled) | |
11123 | crtc->new_config = &crtc->config; | |
11124 | else | |
11125 | crtc->new_config = NULL; | |
7668851f VS |
11126 | } |
11127 | ||
85f9eb71 | 11128 | count = 0; |
b2784e15 | 11129 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
11130 | encoder->new_crtc = |
11131 | to_intel_crtc(config->save_encoder_crtcs[count++]); | |
85f9eb71 DV |
11132 | } |
11133 | ||
11134 | count = 0; | |
9a935856 DV |
11135 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
11136 | connector->new_encoder = | |
11137 | to_intel_encoder(config->save_connector_encoders[count++]); | |
85f9eb71 DV |
11138 | } |
11139 | } | |
11140 | ||
e3de42b6 | 11141 | static bool |
2e57f47d | 11142 | is_crtc_connector_off(struct drm_mode_set *set) |
e3de42b6 ID |
11143 | { |
11144 | int i; | |
11145 | ||
2e57f47d CW |
11146 | if (set->num_connectors == 0) |
11147 | return false; | |
11148 | ||
11149 | if (WARN_ON(set->connectors == NULL)) | |
11150 | return false; | |
11151 | ||
11152 | for (i = 0; i < set->num_connectors; i++) | |
11153 | if (set->connectors[i]->encoder && | |
11154 | set->connectors[i]->encoder->crtc == set->crtc && | |
11155 | set->connectors[i]->dpms != DRM_MODE_DPMS_ON) | |
e3de42b6 ID |
11156 | return true; |
11157 | ||
11158 | return false; | |
11159 | } | |
11160 | ||
5e2b584e DV |
11161 | static void |
11162 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, | |
11163 | struct intel_set_config *config) | |
11164 | { | |
11165 | ||
11166 | /* We should be able to check here if the fb has the same properties | |
11167 | * and then just flip_or_move it */ | |
2e57f47d CW |
11168 | if (is_crtc_connector_off(set)) { |
11169 | config->mode_changed = true; | |
f4510a27 | 11170 | } else if (set->crtc->primary->fb != set->fb) { |
3b150f08 MR |
11171 | /* |
11172 | * If we have no fb, we can only flip as long as the crtc is | |
11173 | * active, otherwise we need a full mode set. The crtc may | |
11174 | * be active if we've only disabled the primary plane, or | |
11175 | * in fastboot situations. | |
11176 | */ | |
f4510a27 | 11177 | if (set->crtc->primary->fb == NULL) { |
319d9827 JB |
11178 | struct intel_crtc *intel_crtc = |
11179 | to_intel_crtc(set->crtc); | |
11180 | ||
3b150f08 | 11181 | if (intel_crtc->active) { |
319d9827 JB |
11182 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); |
11183 | config->fb_changed = true; | |
11184 | } else { | |
11185 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); | |
11186 | config->mode_changed = true; | |
11187 | } | |
5e2b584e DV |
11188 | } else if (set->fb == NULL) { |
11189 | config->mode_changed = true; | |
72f4901e | 11190 | } else if (set->fb->pixel_format != |
f4510a27 | 11191 | set->crtc->primary->fb->pixel_format) { |
5e2b584e | 11192 | config->mode_changed = true; |
e3de42b6 | 11193 | } else { |
5e2b584e | 11194 | config->fb_changed = true; |
e3de42b6 | 11195 | } |
5e2b584e DV |
11196 | } |
11197 | ||
835c5873 | 11198 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
5e2b584e DV |
11199 | config->fb_changed = true; |
11200 | ||
11201 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { | |
11202 | DRM_DEBUG_KMS("modes are different, full mode set\n"); | |
11203 | drm_mode_debug_printmodeline(&set->crtc->mode); | |
11204 | drm_mode_debug_printmodeline(set->mode); | |
11205 | config->mode_changed = true; | |
11206 | } | |
a1d95703 CW |
11207 | |
11208 | DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", | |
11209 | set->crtc->base.id, config->mode_changed, config->fb_changed); | |
5e2b584e DV |
11210 | } |
11211 | ||
2e431051 | 11212 | static int |
9a935856 DV |
11213 | intel_modeset_stage_output_state(struct drm_device *dev, |
11214 | struct drm_mode_set *set, | |
11215 | struct intel_set_config *config) | |
50f56119 | 11216 | { |
9a935856 DV |
11217 | struct intel_connector *connector; |
11218 | struct intel_encoder *encoder; | |
7668851f | 11219 | struct intel_crtc *crtc; |
f3f08572 | 11220 | int ro; |
50f56119 | 11221 | |
9abdda74 | 11222 | /* The upper layers ensure that we either disable a crtc or have a list |
9a935856 DV |
11223 | * of connectors. For paranoia, double-check this. */ |
11224 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
11225 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
11226 | ||
9a935856 DV |
11227 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
11228 | base.head) { | |
11229 | /* Otherwise traverse passed in connector list and get encoders | |
11230 | * for them. */ | |
50f56119 | 11231 | for (ro = 0; ro < set->num_connectors; ro++) { |
9a935856 | 11232 | if (set->connectors[ro] == &connector->base) { |
0e32b39c | 11233 | connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe); |
50f56119 DV |
11234 | break; |
11235 | } | |
11236 | } | |
11237 | ||
9a935856 DV |
11238 | /* If we disable the crtc, disable all its connectors. Also, if |
11239 | * the connector is on the changing crtc but not on the new | |
11240 | * connector list, disable it. */ | |
11241 | if ((!set->fb || ro == set->num_connectors) && | |
11242 | connector->base.encoder && | |
11243 | connector->base.encoder->crtc == set->crtc) { | |
11244 | connector->new_encoder = NULL; | |
11245 | ||
11246 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
11247 | connector->base.base.id, | |
c23cc417 | 11248 | connector->base.name); |
9a935856 DV |
11249 | } |
11250 | ||
11251 | ||
11252 | if (&connector->new_encoder->base != connector->base.encoder) { | |
50f56119 | 11253 | DRM_DEBUG_KMS("encoder changed, full mode switch\n"); |
5e2b584e | 11254 | config->mode_changed = true; |
50f56119 DV |
11255 | } |
11256 | } | |
9a935856 | 11257 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 11258 | |
9a935856 | 11259 | /* Update crtc of enabled connectors. */ |
9a935856 DV |
11260 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
11261 | base.head) { | |
7668851f VS |
11262 | struct drm_crtc *new_crtc; |
11263 | ||
9a935856 | 11264 | if (!connector->new_encoder) |
50f56119 DV |
11265 | continue; |
11266 | ||
9a935856 | 11267 | new_crtc = connector->new_encoder->base.crtc; |
50f56119 DV |
11268 | |
11269 | for (ro = 0; ro < set->num_connectors; ro++) { | |
9a935856 | 11270 | if (set->connectors[ro] == &connector->base) |
50f56119 DV |
11271 | new_crtc = set->crtc; |
11272 | } | |
11273 | ||
11274 | /* Make sure the new CRTC will work with the encoder */ | |
14509916 TR |
11275 | if (!drm_encoder_crtc_ok(&connector->new_encoder->base, |
11276 | new_crtc)) { | |
5e2b584e | 11277 | return -EINVAL; |
50f56119 | 11278 | } |
0e32b39c | 11279 | connector->new_encoder->new_crtc = to_intel_crtc(new_crtc); |
9a935856 DV |
11280 | |
11281 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", | |
11282 | connector->base.base.id, | |
c23cc417 | 11283 | connector->base.name, |
9a935856 DV |
11284 | new_crtc->base.id); |
11285 | } | |
11286 | ||
11287 | /* Check for any encoders that needs to be disabled. */ | |
b2784e15 | 11288 | for_each_intel_encoder(dev, encoder) { |
5a65f358 | 11289 | int num_connectors = 0; |
9a935856 DV |
11290 | list_for_each_entry(connector, |
11291 | &dev->mode_config.connector_list, | |
11292 | base.head) { | |
11293 | if (connector->new_encoder == encoder) { | |
11294 | WARN_ON(!connector->new_encoder->new_crtc); | |
5a65f358 | 11295 | num_connectors++; |
9a935856 DV |
11296 | } |
11297 | } | |
5a65f358 PZ |
11298 | |
11299 | if (num_connectors == 0) | |
11300 | encoder->new_crtc = NULL; | |
11301 | else if (num_connectors > 1) | |
11302 | return -EINVAL; | |
11303 | ||
9a935856 DV |
11304 | /* Only now check for crtc changes so we don't miss encoders |
11305 | * that will be disabled. */ | |
11306 | if (&encoder->new_crtc->base != encoder->base.crtc) { | |
50f56119 | 11307 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
5e2b584e | 11308 | config->mode_changed = true; |
50f56119 DV |
11309 | } |
11310 | } | |
9a935856 | 11311 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
0e32b39c DA |
11312 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
11313 | base.head) { | |
11314 | if (connector->new_encoder) | |
11315 | if (connector->new_encoder != connector->encoder) | |
11316 | connector->encoder = connector->new_encoder; | |
11317 | } | |
d3fcc808 | 11318 | for_each_intel_crtc(dev, crtc) { |
7668851f VS |
11319 | crtc->new_enabled = false; |
11320 | ||
b2784e15 | 11321 | for_each_intel_encoder(dev, encoder) { |
7668851f VS |
11322 | if (encoder->new_crtc == crtc) { |
11323 | crtc->new_enabled = true; | |
11324 | break; | |
11325 | } | |
11326 | } | |
11327 | ||
11328 | if (crtc->new_enabled != crtc->base.enabled) { | |
11329 | DRM_DEBUG_KMS("crtc %sabled, full mode switch\n", | |
11330 | crtc->new_enabled ? "en" : "dis"); | |
11331 | config->mode_changed = true; | |
11332 | } | |
7bd0a8e7 VS |
11333 | |
11334 | if (crtc->new_enabled) | |
11335 | crtc->new_config = &crtc->config; | |
11336 | else | |
11337 | crtc->new_config = NULL; | |
7668851f VS |
11338 | } |
11339 | ||
2e431051 DV |
11340 | return 0; |
11341 | } | |
11342 | ||
7d00a1f5 VS |
11343 | static void disable_crtc_nofb(struct intel_crtc *crtc) |
11344 | { | |
11345 | struct drm_device *dev = crtc->base.dev; | |
11346 | struct intel_encoder *encoder; | |
11347 | struct intel_connector *connector; | |
11348 | ||
11349 | DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n", | |
11350 | pipe_name(crtc->pipe)); | |
11351 | ||
11352 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { | |
11353 | if (connector->new_encoder && | |
11354 | connector->new_encoder->new_crtc == crtc) | |
11355 | connector->new_encoder = NULL; | |
11356 | } | |
11357 | ||
b2784e15 | 11358 | for_each_intel_encoder(dev, encoder) { |
7d00a1f5 VS |
11359 | if (encoder->new_crtc == crtc) |
11360 | encoder->new_crtc = NULL; | |
11361 | } | |
11362 | ||
11363 | crtc->new_enabled = false; | |
7bd0a8e7 | 11364 | crtc->new_config = NULL; |
7d00a1f5 VS |
11365 | } |
11366 | ||
2e431051 DV |
11367 | static int intel_crtc_set_config(struct drm_mode_set *set) |
11368 | { | |
11369 | struct drm_device *dev; | |
2e431051 DV |
11370 | struct drm_mode_set save_set; |
11371 | struct intel_set_config *config; | |
11372 | int ret; | |
2e431051 | 11373 | |
8d3e375e DV |
11374 | BUG_ON(!set); |
11375 | BUG_ON(!set->crtc); | |
11376 | BUG_ON(!set->crtc->helper_private); | |
2e431051 | 11377 | |
7e53f3a4 DV |
11378 | /* Enforce sane interface api - has been abused by the fb helper. */ |
11379 | BUG_ON(!set->mode && set->fb); | |
11380 | BUG_ON(set->fb && set->num_connectors == 0); | |
431e50f7 | 11381 | |
2e431051 DV |
11382 | if (set->fb) { |
11383 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
11384 | set->crtc->base.id, set->fb->base.id, | |
11385 | (int)set->num_connectors, set->x, set->y); | |
11386 | } else { | |
11387 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
11388 | } |
11389 | ||
11390 | dev = set->crtc->dev; | |
11391 | ||
11392 | ret = -ENOMEM; | |
11393 | config = kzalloc(sizeof(*config), GFP_KERNEL); | |
11394 | if (!config) | |
11395 | goto out_config; | |
11396 | ||
11397 | ret = intel_set_config_save_state(dev, config); | |
11398 | if (ret) | |
11399 | goto out_config; | |
11400 | ||
11401 | save_set.crtc = set->crtc; | |
11402 | save_set.mode = &set->crtc->mode; | |
11403 | save_set.x = set->crtc->x; | |
11404 | save_set.y = set->crtc->y; | |
f4510a27 | 11405 | save_set.fb = set->crtc->primary->fb; |
2e431051 DV |
11406 | |
11407 | /* Compute whether we need a full modeset, only an fb base update or no | |
11408 | * change at all. In the future we might also check whether only the | |
11409 | * mode changed, e.g. for LVDS where we only change the panel fitter in | |
11410 | * such cases. */ | |
11411 | intel_set_config_compute_mode_changes(set, config); | |
11412 | ||
9a935856 | 11413 | ret = intel_modeset_stage_output_state(dev, set, config); |
2e431051 DV |
11414 | if (ret) |
11415 | goto fail; | |
11416 | ||
5e2b584e | 11417 | if (config->mode_changed) { |
c0c36b94 CW |
11418 | ret = intel_set_mode(set->crtc, set->mode, |
11419 | set->x, set->y, set->fb); | |
5e2b584e | 11420 | } else if (config->fb_changed) { |
3b150f08 MR |
11421 | struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc); |
11422 | ||
4878cae2 VS |
11423 | intel_crtc_wait_for_pending_flips(set->crtc); |
11424 | ||
4f660f49 | 11425 | ret = intel_pipe_set_base(set->crtc, |
94352cf9 | 11426 | set->x, set->y, set->fb); |
3b150f08 MR |
11427 | |
11428 | /* | |
11429 | * We need to make sure the primary plane is re-enabled if it | |
11430 | * has previously been turned off. | |
11431 | */ | |
11432 | if (!intel_crtc->primary_enabled && ret == 0) { | |
11433 | WARN_ON(!intel_crtc->active); | |
fdd508a6 | 11434 | intel_enable_primary_hw_plane(set->crtc->primary, set->crtc); |
3b150f08 MR |
11435 | } |
11436 | ||
7ca51a3a JB |
11437 | /* |
11438 | * In the fastboot case this may be our only check of the | |
11439 | * state after boot. It would be better to only do it on | |
11440 | * the first update, but we don't have a nice way of doing that | |
11441 | * (and really, set_config isn't used much for high freq page | |
11442 | * flipping, so increasing its cost here shouldn't be a big | |
11443 | * deal). | |
11444 | */ | |
d330a953 | 11445 | if (i915.fastboot && ret == 0) |
7ca51a3a | 11446 | intel_modeset_check_state(set->crtc->dev); |
50f56119 DV |
11447 | } |
11448 | ||
2d05eae1 | 11449 | if (ret) { |
bf67dfeb DV |
11450 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
11451 | set->crtc->base.id, ret); | |
50f56119 | 11452 | fail: |
2d05eae1 | 11453 | intel_set_config_restore_state(dev, config); |
50f56119 | 11454 | |
7d00a1f5 VS |
11455 | /* |
11456 | * HACK: if the pipe was on, but we didn't have a framebuffer, | |
11457 | * force the pipe off to avoid oopsing in the modeset code | |
11458 | * due to fb==NULL. This should only happen during boot since | |
11459 | * we don't yet reconstruct the FB from the hardware state. | |
11460 | */ | |
11461 | if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb) | |
11462 | disable_crtc_nofb(to_intel_crtc(save_set.crtc)); | |
11463 | ||
2d05eae1 CW |
11464 | /* Try to restore the config */ |
11465 | if (config->mode_changed && | |
11466 | intel_set_mode(save_set.crtc, save_set.mode, | |
11467 | save_set.x, save_set.y, save_set.fb)) | |
11468 | DRM_ERROR("failed to restore config after modeset failure\n"); | |
11469 | } | |
50f56119 | 11470 | |
d9e55608 DV |
11471 | out_config: |
11472 | intel_set_config_free(config); | |
50f56119 DV |
11473 | return ret; |
11474 | } | |
f6e5b160 CW |
11475 | |
11476 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 | 11477 | .gamma_set = intel_crtc_gamma_set, |
50f56119 | 11478 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
11479 | .destroy = intel_crtc_destroy, |
11480 | .page_flip = intel_crtc_page_flip, | |
11481 | }; | |
11482 | ||
5358901f DV |
11483 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
11484 | struct intel_shared_dpll *pll, | |
11485 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 11486 | { |
5358901f | 11487 | uint32_t val; |
ee7b9f93 | 11488 | |
bd2bb1b9 PZ |
11489 | if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
11490 | return false; | |
11491 | ||
5358901f | 11492 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
11493 | hw_state->dpll = val; |
11494 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
11495 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
11496 | |
11497 | return val & DPLL_VCO_ENABLE; | |
11498 | } | |
11499 | ||
15bdd4cf DV |
11500 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
11501 | struct intel_shared_dpll *pll) | |
11502 | { | |
11503 | I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0); | |
11504 | I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1); | |
11505 | } | |
11506 | ||
e7b903d2 DV |
11507 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
11508 | struct intel_shared_dpll *pll) | |
11509 | { | |
e7b903d2 | 11510 | /* PCH refclock must be enabled first */ |
89eff4be | 11511 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 11512 | |
15bdd4cf DV |
11513 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); |
11514 | ||
11515 | /* Wait for the clocks to stabilize. */ | |
11516 | POSTING_READ(PCH_DPLL(pll->id)); | |
11517 | udelay(150); | |
11518 | ||
11519 | /* The pixel multiplier can only be updated once the | |
11520 | * DPLL is enabled and the clocks are stable. | |
11521 | * | |
11522 | * So write it again. | |
11523 | */ | |
11524 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); | |
11525 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
11526 | udelay(200); |
11527 | } | |
11528 | ||
11529 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
11530 | struct intel_shared_dpll *pll) | |
11531 | { | |
11532 | struct drm_device *dev = dev_priv->dev; | |
11533 | struct intel_crtc *crtc; | |
e7b903d2 DV |
11534 | |
11535 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 11536 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
11537 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
11538 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
11539 | } |
11540 | ||
15bdd4cf DV |
11541 | I915_WRITE(PCH_DPLL(pll->id), 0); |
11542 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
11543 | udelay(200); |
11544 | } | |
11545 | ||
46edb027 DV |
11546 | static char *ibx_pch_dpll_names[] = { |
11547 | "PCH DPLL A", | |
11548 | "PCH DPLL B", | |
11549 | }; | |
11550 | ||
7c74ade1 | 11551 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 11552 | { |
e7b903d2 | 11553 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
11554 | int i; |
11555 | ||
7c74ade1 | 11556 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 11557 | |
e72f9fbf | 11558 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
11559 | dev_priv->shared_dplls[i].id = i; |
11560 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 11561 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
11562 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
11563 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
11564 | dev_priv->shared_dplls[i].get_hw_state = |
11565 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
11566 | } |
11567 | } | |
11568 | ||
7c74ade1 DV |
11569 | static void intel_shared_dpll_init(struct drm_device *dev) |
11570 | { | |
e7b903d2 | 11571 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 | 11572 | |
9cd86933 DV |
11573 | if (HAS_DDI(dev)) |
11574 | intel_ddi_pll_init(dev); | |
11575 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7c74ade1 DV |
11576 | ibx_pch_dpll_init(dev); |
11577 | else | |
11578 | dev_priv->num_shared_dpll = 0; | |
11579 | ||
11580 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
11581 | } |
11582 | ||
465c120c MR |
11583 | static int |
11584 | intel_primary_plane_disable(struct drm_plane *plane) | |
11585 | { | |
11586 | struct drm_device *dev = plane->dev; | |
465c120c MR |
11587 | struct intel_crtc *intel_crtc; |
11588 | ||
11589 | if (!plane->fb) | |
11590 | return 0; | |
11591 | ||
11592 | BUG_ON(!plane->crtc); | |
11593 | ||
11594 | intel_crtc = to_intel_crtc(plane->crtc); | |
11595 | ||
11596 | /* | |
11597 | * Even though we checked plane->fb above, it's still possible that | |
11598 | * the primary plane has been implicitly disabled because the crtc | |
11599 | * coordinates given weren't visible, or because we detected | |
11600 | * that it was 100% covered by a sprite plane. Or, the CRTC may be | |
11601 | * off and we've set a fb, but haven't actually turned on the CRTC yet. | |
11602 | * In either case, we need to unpin the FB and let the fb pointer get | |
11603 | * updated, but otherwise we don't need to touch the hardware. | |
11604 | */ | |
11605 | if (!intel_crtc->primary_enabled) | |
11606 | goto disable_unpin; | |
11607 | ||
11608 | intel_crtc_wait_for_pending_flips(plane->crtc); | |
fdd508a6 VS |
11609 | intel_disable_primary_hw_plane(plane, plane->crtc); |
11610 | ||
465c120c | 11611 | disable_unpin: |
4c34574f | 11612 | mutex_lock(&dev->struct_mutex); |
2ff8fde1 | 11613 | i915_gem_track_fb(intel_fb_obj(plane->fb), NULL, |
a071fa00 | 11614 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe)); |
2ff8fde1 | 11615 | intel_unpin_fb_obj(intel_fb_obj(plane->fb)); |
4c34574f | 11616 | mutex_unlock(&dev->struct_mutex); |
465c120c MR |
11617 | plane->fb = NULL; |
11618 | ||
11619 | return 0; | |
11620 | } | |
11621 | ||
11622 | static int | |
11623 | intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc, | |
11624 | struct drm_framebuffer *fb, int crtc_x, int crtc_y, | |
11625 | unsigned int crtc_w, unsigned int crtc_h, | |
11626 | uint32_t src_x, uint32_t src_y, | |
11627 | uint32_t src_w, uint32_t src_h) | |
11628 | { | |
11629 | struct drm_device *dev = crtc->dev; | |
48404c1e | 11630 | struct drm_i915_private *dev_priv = dev->dev_private; |
465c120c | 11631 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2ff8fde1 MR |
11632 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
11633 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); | |
465c120c MR |
11634 | struct drm_rect dest = { |
11635 | /* integer pixels */ | |
11636 | .x1 = crtc_x, | |
11637 | .y1 = crtc_y, | |
11638 | .x2 = crtc_x + crtc_w, | |
11639 | .y2 = crtc_y + crtc_h, | |
11640 | }; | |
11641 | struct drm_rect src = { | |
11642 | /* 16.16 fixed point */ | |
11643 | .x1 = src_x, | |
11644 | .y1 = src_y, | |
11645 | .x2 = src_x + src_w, | |
11646 | .y2 = src_y + src_h, | |
11647 | }; | |
11648 | const struct drm_rect clip = { | |
11649 | /* integer pixels */ | |
11650 | .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0, | |
11651 | .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0, | |
11652 | }; | |
ce54d85a SJ |
11653 | const struct { |
11654 | int crtc_x, crtc_y; | |
11655 | unsigned int crtc_w, crtc_h; | |
11656 | uint32_t src_x, src_y, src_w, src_h; | |
11657 | } orig = { | |
11658 | .crtc_x = crtc_x, | |
11659 | .crtc_y = crtc_y, | |
11660 | .crtc_w = crtc_w, | |
11661 | .crtc_h = crtc_h, | |
11662 | .src_x = src_x, | |
11663 | .src_y = src_y, | |
11664 | .src_w = src_w, | |
11665 | .src_h = src_h, | |
11666 | }; | |
11667 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
465c120c MR |
11668 | bool visible; |
11669 | int ret; | |
11670 | ||
11671 | ret = drm_plane_helper_check_update(plane, crtc, fb, | |
11672 | &src, &dest, &clip, | |
11673 | DRM_PLANE_HELPER_NO_SCALING, | |
11674 | DRM_PLANE_HELPER_NO_SCALING, | |
11675 | false, true, &visible); | |
11676 | ||
11677 | if (ret) | |
11678 | return ret; | |
11679 | ||
11680 | /* | |
11681 | * If the CRTC isn't enabled, we're just pinning the framebuffer, | |
11682 | * updating the fb pointer, and returning without touching the | |
11683 | * hardware. This allows us to later do a drmModeSetCrtc with fb=-1 to | |
11684 | * turn on the display with all planes setup as desired. | |
11685 | */ | |
11686 | if (!crtc->enabled) { | |
4c34574f MR |
11687 | mutex_lock(&dev->struct_mutex); |
11688 | ||
465c120c MR |
11689 | /* |
11690 | * If we already called setplane while the crtc was disabled, | |
11691 | * we may have an fb pinned; unpin it. | |
11692 | */ | |
11693 | if (plane->fb) | |
a071fa00 DV |
11694 | intel_unpin_fb_obj(old_obj); |
11695 | ||
11696 | i915_gem_track_fb(old_obj, obj, | |
11697 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe)); | |
465c120c MR |
11698 | |
11699 | /* Pin and return without programming hardware */ | |
4c34574f MR |
11700 | ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); |
11701 | mutex_unlock(&dev->struct_mutex); | |
11702 | ||
11703 | return ret; | |
465c120c MR |
11704 | } |
11705 | ||
11706 | intel_crtc_wait_for_pending_flips(crtc); | |
11707 | ||
11708 | /* | |
11709 | * If clipping results in a non-visible primary plane, we'll disable | |
11710 | * the primary plane. Note that this is a bit different than what | |
11711 | * happens if userspace explicitly disables the plane by passing fb=0 | |
11712 | * because plane->fb still gets set and pinned. | |
11713 | */ | |
11714 | if (!visible) { | |
4c34574f MR |
11715 | mutex_lock(&dev->struct_mutex); |
11716 | ||
465c120c MR |
11717 | /* |
11718 | * Try to pin the new fb first so that we can bail out if we | |
11719 | * fail. | |
11720 | */ | |
11721 | if (plane->fb != fb) { | |
a071fa00 | 11722 | ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); |
4c34574f MR |
11723 | if (ret) { |
11724 | mutex_unlock(&dev->struct_mutex); | |
465c120c | 11725 | return ret; |
4c34574f | 11726 | } |
465c120c MR |
11727 | } |
11728 | ||
a071fa00 DV |
11729 | i915_gem_track_fb(old_obj, obj, |
11730 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe)); | |
11731 | ||
465c120c | 11732 | if (intel_crtc->primary_enabled) |
fdd508a6 | 11733 | intel_disable_primary_hw_plane(plane, crtc); |
465c120c MR |
11734 | |
11735 | ||
11736 | if (plane->fb != fb) | |
11737 | if (plane->fb) | |
a071fa00 | 11738 | intel_unpin_fb_obj(old_obj); |
465c120c | 11739 | |
4c34574f MR |
11740 | mutex_unlock(&dev->struct_mutex); |
11741 | ||
ce54d85a | 11742 | } else { |
48404c1e SJ |
11743 | if (intel_crtc && intel_crtc->active && |
11744 | intel_crtc->primary_enabled) { | |
11745 | /* | |
11746 | * FBC does not work on some platforms for rotated | |
11747 | * planes, so disable it when rotation is not 0 and | |
11748 | * update it when rotation is set back to 0. | |
11749 | * | |
11750 | * FIXME: This is redundant with the fbc update done in | |
11751 | * the primary plane enable function except that that | |
11752 | * one is done too late. We eventually need to unify | |
11753 | * this. | |
11754 | */ | |
11755 | if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && | |
11756 | dev_priv->fbc.plane == intel_crtc->plane && | |
11757 | intel_plane->rotation != BIT(DRM_ROTATE_0)) { | |
11758 | intel_disable_fbc(dev); | |
11759 | } | |
11760 | } | |
ce54d85a SJ |
11761 | ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb); |
11762 | if (ret) | |
11763 | return ret; | |
465c120c | 11764 | |
ce54d85a SJ |
11765 | if (!intel_crtc->primary_enabled) |
11766 | intel_enable_primary_hw_plane(plane, crtc); | |
11767 | } | |
465c120c | 11768 | |
ce54d85a SJ |
11769 | intel_plane->crtc_x = orig.crtc_x; |
11770 | intel_plane->crtc_y = orig.crtc_y; | |
11771 | intel_plane->crtc_w = orig.crtc_w; | |
11772 | intel_plane->crtc_h = orig.crtc_h; | |
11773 | intel_plane->src_x = orig.src_x; | |
11774 | intel_plane->src_y = orig.src_y; | |
11775 | intel_plane->src_w = orig.src_w; | |
11776 | intel_plane->src_h = orig.src_h; | |
11777 | intel_plane->obj = obj; | |
465c120c MR |
11778 | |
11779 | return 0; | |
11780 | } | |
11781 | ||
3d7d6510 MR |
11782 | /* Common destruction function for both primary and cursor planes */ |
11783 | static void intel_plane_destroy(struct drm_plane *plane) | |
465c120c MR |
11784 | { |
11785 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
11786 | drm_plane_cleanup(plane); | |
11787 | kfree(intel_plane); | |
11788 | } | |
11789 | ||
11790 | static const struct drm_plane_funcs intel_primary_plane_funcs = { | |
11791 | .update_plane = intel_primary_plane_setplane, | |
11792 | .disable_plane = intel_primary_plane_disable, | |
3d7d6510 | 11793 | .destroy = intel_plane_destroy, |
48404c1e | 11794 | .set_property = intel_plane_set_property |
465c120c MR |
11795 | }; |
11796 | ||
11797 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
11798 | int pipe) | |
11799 | { | |
11800 | struct intel_plane *primary; | |
11801 | const uint32_t *intel_primary_formats; | |
11802 | int num_formats; | |
11803 | ||
11804 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
11805 | if (primary == NULL) | |
11806 | return NULL; | |
11807 | ||
11808 | primary->can_scale = false; | |
11809 | primary->max_downscale = 1; | |
11810 | primary->pipe = pipe; | |
11811 | primary->plane = pipe; | |
48404c1e | 11812 | primary->rotation = BIT(DRM_ROTATE_0); |
465c120c MR |
11813 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
11814 | primary->plane = !pipe; | |
11815 | ||
11816 | if (INTEL_INFO(dev)->gen <= 3) { | |
11817 | intel_primary_formats = intel_primary_formats_gen2; | |
11818 | num_formats = ARRAY_SIZE(intel_primary_formats_gen2); | |
11819 | } else { | |
11820 | intel_primary_formats = intel_primary_formats_gen4; | |
11821 | num_formats = ARRAY_SIZE(intel_primary_formats_gen4); | |
11822 | } | |
11823 | ||
11824 | drm_universal_plane_init(dev, &primary->base, 0, | |
11825 | &intel_primary_plane_funcs, | |
11826 | intel_primary_formats, num_formats, | |
11827 | DRM_PLANE_TYPE_PRIMARY); | |
48404c1e SJ |
11828 | |
11829 | if (INTEL_INFO(dev)->gen >= 4) { | |
11830 | if (!dev->mode_config.rotation_property) | |
11831 | dev->mode_config.rotation_property = | |
11832 | drm_mode_create_rotation_property(dev, | |
11833 | BIT(DRM_ROTATE_0) | | |
11834 | BIT(DRM_ROTATE_180)); | |
11835 | if (dev->mode_config.rotation_property) | |
11836 | drm_object_attach_property(&primary->base.base, | |
11837 | dev->mode_config.rotation_property, | |
11838 | primary->rotation); | |
11839 | } | |
11840 | ||
465c120c MR |
11841 | return &primary->base; |
11842 | } | |
11843 | ||
3d7d6510 MR |
11844 | static int |
11845 | intel_cursor_plane_disable(struct drm_plane *plane) | |
11846 | { | |
11847 | if (!plane->fb) | |
11848 | return 0; | |
11849 | ||
11850 | BUG_ON(!plane->crtc); | |
11851 | ||
11852 | return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0); | |
11853 | } | |
11854 | ||
11855 | static int | |
11856 | intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, | |
11857 | struct drm_framebuffer *fb, int crtc_x, int crtc_y, | |
11858 | unsigned int crtc_w, unsigned int crtc_h, | |
11859 | uint32_t src_x, uint32_t src_y, | |
11860 | uint32_t src_w, uint32_t src_h) | |
11861 | { | |
11862 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11863 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
11864 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
11865 | struct drm_rect dest = { | |
11866 | /* integer pixels */ | |
11867 | .x1 = crtc_x, | |
11868 | .y1 = crtc_y, | |
11869 | .x2 = crtc_x + crtc_w, | |
11870 | .y2 = crtc_y + crtc_h, | |
11871 | }; | |
11872 | struct drm_rect src = { | |
11873 | /* 16.16 fixed point */ | |
11874 | .x1 = src_x, | |
11875 | .y1 = src_y, | |
11876 | .x2 = src_x + src_w, | |
11877 | .y2 = src_y + src_h, | |
11878 | }; | |
11879 | const struct drm_rect clip = { | |
11880 | /* integer pixels */ | |
1add143c VS |
11881 | .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0, |
11882 | .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0, | |
3d7d6510 MR |
11883 | }; |
11884 | bool visible; | |
11885 | int ret; | |
11886 | ||
11887 | ret = drm_plane_helper_check_update(plane, crtc, fb, | |
11888 | &src, &dest, &clip, | |
11889 | DRM_PLANE_HELPER_NO_SCALING, | |
11890 | DRM_PLANE_HELPER_NO_SCALING, | |
11891 | true, true, &visible); | |
11892 | if (ret) | |
11893 | return ret; | |
11894 | ||
11895 | crtc->cursor_x = crtc_x; | |
11896 | crtc->cursor_y = crtc_y; | |
11897 | if (fb != crtc->cursor->fb) { | |
11898 | return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h); | |
11899 | } else { | |
11900 | intel_crtc_update_cursor(crtc, visible); | |
4ed91096 DV |
11901 | |
11902 | intel_frontbuffer_flip(crtc->dev, | |
11903 | INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe)); | |
11904 | ||
3d7d6510 MR |
11905 | return 0; |
11906 | } | |
11907 | } | |
11908 | static const struct drm_plane_funcs intel_cursor_plane_funcs = { | |
11909 | .update_plane = intel_cursor_plane_update, | |
11910 | .disable_plane = intel_cursor_plane_disable, | |
11911 | .destroy = intel_plane_destroy, | |
11912 | }; | |
11913 | ||
11914 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, | |
11915 | int pipe) | |
11916 | { | |
11917 | struct intel_plane *cursor; | |
11918 | ||
11919 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
11920 | if (cursor == NULL) | |
11921 | return NULL; | |
11922 | ||
11923 | cursor->can_scale = false; | |
11924 | cursor->max_downscale = 1; | |
11925 | cursor->pipe = pipe; | |
11926 | cursor->plane = pipe; | |
11927 | ||
11928 | drm_universal_plane_init(dev, &cursor->base, 0, | |
11929 | &intel_cursor_plane_funcs, | |
11930 | intel_cursor_formats, | |
11931 | ARRAY_SIZE(intel_cursor_formats), | |
11932 | DRM_PLANE_TYPE_CURSOR); | |
11933 | return &cursor->base; | |
11934 | } | |
11935 | ||
b358d0a6 | 11936 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 11937 | { |
fbee40df | 11938 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 11939 | struct intel_crtc *intel_crtc; |
3d7d6510 MR |
11940 | struct drm_plane *primary = NULL; |
11941 | struct drm_plane *cursor = NULL; | |
465c120c | 11942 | int i, ret; |
79e53945 | 11943 | |
955382f3 | 11944 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
11945 | if (intel_crtc == NULL) |
11946 | return; | |
11947 | ||
465c120c | 11948 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
11949 | if (!primary) |
11950 | goto fail; | |
11951 | ||
11952 | cursor = intel_cursor_plane_create(dev, pipe); | |
11953 | if (!cursor) | |
11954 | goto fail; | |
11955 | ||
465c120c | 11956 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
3d7d6510 MR |
11957 | cursor, &intel_crtc_funcs); |
11958 | if (ret) | |
11959 | goto fail; | |
79e53945 JB |
11960 | |
11961 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
11962 | for (i = 0; i < 256; i++) { |
11963 | intel_crtc->lut_r[i] = i; | |
11964 | intel_crtc->lut_g[i] = i; | |
11965 | intel_crtc->lut_b[i] = i; | |
11966 | } | |
11967 | ||
1f1c2e24 VS |
11968 | /* |
11969 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 11970 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 11971 | */ |
80824003 JB |
11972 | intel_crtc->pipe = pipe; |
11973 | intel_crtc->plane = pipe; | |
3a77c4c4 | 11974 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 11975 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 11976 | intel_crtc->plane = !pipe; |
80824003 JB |
11977 | } |
11978 | ||
4b0e333e CW |
11979 | intel_crtc->cursor_base = ~0; |
11980 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 11981 | intel_crtc->cursor_size = ~0; |
4b0e333e | 11982 | |
22fd0fab JB |
11983 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
11984 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
11985 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
11986 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
11987 | ||
79e53945 | 11988 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 DV |
11989 | |
11990 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); | |
3d7d6510 MR |
11991 | return; |
11992 | ||
11993 | fail: | |
11994 | if (primary) | |
11995 | drm_plane_cleanup(primary); | |
11996 | if (cursor) | |
11997 | drm_plane_cleanup(cursor); | |
11998 | kfree(intel_crtc); | |
79e53945 JB |
11999 | } |
12000 | ||
752aa88a JB |
12001 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
12002 | { | |
12003 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 12004 | struct drm_device *dev = connector->base.dev; |
752aa88a | 12005 | |
51fd371b | 12006 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a JB |
12007 | |
12008 | if (!encoder) | |
12009 | return INVALID_PIPE; | |
12010 | ||
12011 | return to_intel_crtc(encoder->crtc)->pipe; | |
12012 | } | |
12013 | ||
08d7b3d1 | 12014 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 12015 | struct drm_file *file) |
08d7b3d1 | 12016 | { |
08d7b3d1 | 12017 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 12018 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 12019 | struct intel_crtc *crtc; |
08d7b3d1 | 12020 | |
1cff8f6b DV |
12021 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
12022 | return -ENODEV; | |
08d7b3d1 | 12023 | |
7707e653 | 12024 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 12025 | |
7707e653 | 12026 | if (!drmmode_crtc) { |
08d7b3d1 | 12027 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 12028 | return -ENOENT; |
08d7b3d1 CW |
12029 | } |
12030 | ||
7707e653 | 12031 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 12032 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 12033 | |
c05422d5 | 12034 | return 0; |
08d7b3d1 CW |
12035 | } |
12036 | ||
66a9278e | 12037 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 12038 | { |
66a9278e DV |
12039 | struct drm_device *dev = encoder->base.dev; |
12040 | struct intel_encoder *source_encoder; | |
79e53945 | 12041 | int index_mask = 0; |
79e53945 JB |
12042 | int entry = 0; |
12043 | ||
b2784e15 | 12044 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 12045 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
12046 | index_mask |= (1 << entry); |
12047 | ||
79e53945 JB |
12048 | entry++; |
12049 | } | |
4ef69c7a | 12050 | |
79e53945 JB |
12051 | return index_mask; |
12052 | } | |
12053 | ||
4d302442 CW |
12054 | static bool has_edp_a(struct drm_device *dev) |
12055 | { | |
12056 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12057 | ||
12058 | if (!IS_MOBILE(dev)) | |
12059 | return false; | |
12060 | ||
12061 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
12062 | return false; | |
12063 | ||
e3589908 | 12064 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
12065 | return false; |
12066 | ||
12067 | return true; | |
12068 | } | |
12069 | ||
ba0fbca4 DL |
12070 | const char *intel_output_name(int output) |
12071 | { | |
12072 | static const char *names[] = { | |
12073 | [INTEL_OUTPUT_UNUSED] = "Unused", | |
12074 | [INTEL_OUTPUT_ANALOG] = "Analog", | |
12075 | [INTEL_OUTPUT_DVO] = "DVO", | |
12076 | [INTEL_OUTPUT_SDVO] = "SDVO", | |
12077 | [INTEL_OUTPUT_LVDS] = "LVDS", | |
12078 | [INTEL_OUTPUT_TVOUT] = "TV", | |
12079 | [INTEL_OUTPUT_HDMI] = "HDMI", | |
12080 | [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort", | |
12081 | [INTEL_OUTPUT_EDP] = "eDP", | |
12082 | [INTEL_OUTPUT_DSI] = "DSI", | |
12083 | [INTEL_OUTPUT_UNKNOWN] = "Unknown", | |
12084 | }; | |
12085 | ||
12086 | if (output < 0 || output >= ARRAY_SIZE(names) || !names[output]) | |
12087 | return "Invalid"; | |
12088 | ||
12089 | return names[output]; | |
12090 | } | |
12091 | ||
84b4e042 JB |
12092 | static bool intel_crt_present(struct drm_device *dev) |
12093 | { | |
12094 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12095 | ||
12096 | if (IS_ULT(dev)) | |
12097 | return false; | |
12098 | ||
12099 | if (IS_CHERRYVIEW(dev)) | |
12100 | return false; | |
12101 | ||
12102 | if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support) | |
12103 | return false; | |
12104 | ||
12105 | return true; | |
12106 | } | |
12107 | ||
79e53945 JB |
12108 | static void intel_setup_outputs(struct drm_device *dev) |
12109 | { | |
725e30ad | 12110 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 12111 | struct intel_encoder *encoder; |
cb0953d7 | 12112 | bool dpd_is_edp = false; |
79e53945 | 12113 | |
c9093354 | 12114 | intel_lvds_init(dev); |
79e53945 | 12115 | |
84b4e042 | 12116 | if (intel_crt_present(dev)) |
79935fca | 12117 | intel_crt_init(dev); |
cb0953d7 | 12118 | |
affa9354 | 12119 | if (HAS_DDI(dev)) { |
0e72a5b5 ED |
12120 | int found; |
12121 | ||
12122 | /* Haswell uses DDI functions to detect digital outputs */ | |
12123 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; | |
12124 | /* DDI A only supports eDP */ | |
12125 | if (found) | |
12126 | intel_ddi_init(dev, PORT_A); | |
12127 | ||
12128 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
12129 | * register */ | |
12130 | found = I915_READ(SFUSE_STRAP); | |
12131 | ||
12132 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
12133 | intel_ddi_init(dev, PORT_B); | |
12134 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
12135 | intel_ddi_init(dev, PORT_C); | |
12136 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
12137 | intel_ddi_init(dev, PORT_D); | |
12138 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 12139 | int found; |
5d8a7752 | 12140 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
12141 | |
12142 | if (has_edp_a(dev)) | |
12143 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 12144 | |
dc0fa718 | 12145 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 12146 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 12147 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 12148 | if (!found) |
e2debe91 | 12149 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 12150 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 12151 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
12152 | } |
12153 | ||
dc0fa718 | 12154 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 12155 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 12156 | |
dc0fa718 | 12157 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 12158 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 12159 | |
5eb08b69 | 12160 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 12161 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 12162 | |
270b3042 | 12163 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 12164 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 12165 | } else if (IS_VALLEYVIEW(dev)) { |
585a94b8 AB |
12166 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) { |
12167 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, | |
12168 | PORT_B); | |
12169 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED) | |
12170 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
12171 | } | |
12172 | ||
6f6005a5 JB |
12173 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) { |
12174 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, | |
12175 | PORT_C); | |
12176 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) | |
5d8a7752 | 12177 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); |
6f6005a5 | 12178 | } |
19c03924 | 12179 | |
9418c1f1 VS |
12180 | if (IS_CHERRYVIEW(dev)) { |
12181 | if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) { | |
12182 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID, | |
12183 | PORT_D); | |
12184 | if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED) | |
12185 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D); | |
12186 | } | |
12187 | } | |
12188 | ||
3cfca973 | 12189 | intel_dsi_init(dev); |
103a196f | 12190 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 12191 | bool found = false; |
7d57382e | 12192 | |
e2debe91 | 12193 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 12194 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 12195 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
b01f2c3a JB |
12196 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
12197 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
e2debe91 | 12198 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 12199 | } |
27185ae1 | 12200 | |
e7281eab | 12201 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 12202 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 12203 | } |
13520b05 KH |
12204 | |
12205 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 12206 | |
e2debe91 | 12207 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 12208 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 12209 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 12210 | } |
27185ae1 | 12211 | |
e2debe91 | 12212 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 12213 | |
b01f2c3a JB |
12214 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
12215 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
e2debe91 | 12216 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 12217 | } |
e7281eab | 12218 | if (SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 12219 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 12220 | } |
27185ae1 | 12221 | |
b01f2c3a | 12222 | if (SUPPORTS_INTEGRATED_DP(dev) && |
e7281eab | 12223 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 12224 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 12225 | } else if (IS_GEN2(dev)) |
79e53945 JB |
12226 | intel_dvo_init(dev); |
12227 | ||
103a196f | 12228 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
12229 | intel_tv_init(dev); |
12230 | ||
7c8f8a70 RV |
12231 | intel_edp_psr_init(dev); |
12232 | ||
b2784e15 | 12233 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
12234 | encoder->base.possible_crtcs = encoder->crtc_mask; |
12235 | encoder->base.possible_clones = | |
66a9278e | 12236 | intel_encoder_clones(encoder); |
79e53945 | 12237 | } |
47356eb6 | 12238 | |
dde86e2d | 12239 | intel_init_pch_refclk(dev); |
270b3042 DV |
12240 | |
12241 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
12242 | } |
12243 | ||
12244 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
12245 | { | |
60a5ca01 | 12246 | struct drm_device *dev = fb->dev; |
79e53945 | 12247 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 12248 | |
ef2d633e | 12249 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 12250 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 12251 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
12252 | drm_gem_object_unreference(&intel_fb->obj->base); |
12253 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
12254 | kfree(intel_fb); |
12255 | } | |
12256 | ||
12257 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 12258 | struct drm_file *file, |
79e53945 JB |
12259 | unsigned int *handle) |
12260 | { | |
12261 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 12262 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 12263 | |
05394f39 | 12264 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
12265 | } |
12266 | ||
12267 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
12268 | .destroy = intel_user_framebuffer_destroy, | |
12269 | .create_handle = intel_user_framebuffer_create_handle, | |
12270 | }; | |
12271 | ||
b5ea642a DV |
12272 | static int intel_framebuffer_init(struct drm_device *dev, |
12273 | struct intel_framebuffer *intel_fb, | |
12274 | struct drm_mode_fb_cmd2 *mode_cmd, | |
12275 | struct drm_i915_gem_object *obj) | |
79e53945 | 12276 | { |
a57ce0b2 | 12277 | int aligned_height; |
a35cdaa0 | 12278 | int pitch_limit; |
79e53945 JB |
12279 | int ret; |
12280 | ||
dd4916c5 DV |
12281 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
12282 | ||
c16ed4be CW |
12283 | if (obj->tiling_mode == I915_TILING_Y) { |
12284 | DRM_DEBUG("hardware does not support tiling Y\n"); | |
57cd6508 | 12285 | return -EINVAL; |
c16ed4be | 12286 | } |
57cd6508 | 12287 | |
c16ed4be CW |
12288 | if (mode_cmd->pitches[0] & 63) { |
12289 | DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n", | |
12290 | mode_cmd->pitches[0]); | |
57cd6508 | 12291 | return -EINVAL; |
c16ed4be | 12292 | } |
57cd6508 | 12293 | |
a35cdaa0 CW |
12294 | if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) { |
12295 | pitch_limit = 32*1024; | |
12296 | } else if (INTEL_INFO(dev)->gen >= 4) { | |
12297 | if (obj->tiling_mode) | |
12298 | pitch_limit = 16*1024; | |
12299 | else | |
12300 | pitch_limit = 32*1024; | |
12301 | } else if (INTEL_INFO(dev)->gen >= 3) { | |
12302 | if (obj->tiling_mode) | |
12303 | pitch_limit = 8*1024; | |
12304 | else | |
12305 | pitch_limit = 16*1024; | |
12306 | } else | |
12307 | /* XXX DSPC is limited to 4k tiled */ | |
12308 | pitch_limit = 8*1024; | |
12309 | ||
12310 | if (mode_cmd->pitches[0] > pitch_limit) { | |
12311 | DRM_DEBUG("%s pitch (%d) must be at less than %d\n", | |
12312 | obj->tiling_mode ? "tiled" : "linear", | |
12313 | mode_cmd->pitches[0], pitch_limit); | |
5d7bd705 | 12314 | return -EINVAL; |
c16ed4be | 12315 | } |
5d7bd705 VS |
12316 | |
12317 | if (obj->tiling_mode != I915_TILING_NONE && | |
c16ed4be CW |
12318 | mode_cmd->pitches[0] != obj->stride) { |
12319 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
12320 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 12321 | return -EINVAL; |
c16ed4be | 12322 | } |
5d7bd705 | 12323 | |
57779d06 | 12324 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 12325 | switch (mode_cmd->pixel_format) { |
57779d06 | 12326 | case DRM_FORMAT_C8: |
04b3924d VS |
12327 | case DRM_FORMAT_RGB565: |
12328 | case DRM_FORMAT_XRGB8888: | |
12329 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
12330 | break; |
12331 | case DRM_FORMAT_XRGB1555: | |
12332 | case DRM_FORMAT_ARGB1555: | |
c16ed4be | 12333 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
12334 | DRM_DEBUG("unsupported pixel format: %s\n", |
12335 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 12336 | return -EINVAL; |
c16ed4be | 12337 | } |
57779d06 VS |
12338 | break; |
12339 | case DRM_FORMAT_XBGR8888: | |
12340 | case DRM_FORMAT_ABGR8888: | |
04b3924d VS |
12341 | case DRM_FORMAT_XRGB2101010: |
12342 | case DRM_FORMAT_ARGB2101010: | |
57779d06 VS |
12343 | case DRM_FORMAT_XBGR2101010: |
12344 | case DRM_FORMAT_ABGR2101010: | |
c16ed4be | 12345 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
12346 | DRM_DEBUG("unsupported pixel format: %s\n", |
12347 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 12348 | return -EINVAL; |
c16ed4be | 12349 | } |
b5626747 | 12350 | break; |
04b3924d VS |
12351 | case DRM_FORMAT_YUYV: |
12352 | case DRM_FORMAT_UYVY: | |
12353 | case DRM_FORMAT_YVYU: | |
12354 | case DRM_FORMAT_VYUY: | |
c16ed4be | 12355 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
12356 | DRM_DEBUG("unsupported pixel format: %s\n", |
12357 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 12358 | return -EINVAL; |
c16ed4be | 12359 | } |
57cd6508 CW |
12360 | break; |
12361 | default: | |
4ee62c76 VS |
12362 | DRM_DEBUG("unsupported pixel format: %s\n", |
12363 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
12364 | return -EINVAL; |
12365 | } | |
12366 | ||
90f9a336 VS |
12367 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
12368 | if (mode_cmd->offsets[0] != 0) | |
12369 | return -EINVAL; | |
12370 | ||
a57ce0b2 JB |
12371 | aligned_height = intel_align_height(dev, mode_cmd->height, |
12372 | obj->tiling_mode); | |
53155c0a DV |
12373 | /* FIXME drm helper for size checks (especially planar formats)? */ |
12374 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
12375 | return -EINVAL; | |
12376 | ||
c7d73f6a DV |
12377 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
12378 | intel_fb->obj = obj; | |
80075d49 | 12379 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 12380 | |
79e53945 JB |
12381 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
12382 | if (ret) { | |
12383 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
12384 | return ret; | |
12385 | } | |
12386 | ||
79e53945 JB |
12387 | return 0; |
12388 | } | |
12389 | ||
79e53945 JB |
12390 | static struct drm_framebuffer * |
12391 | intel_user_framebuffer_create(struct drm_device *dev, | |
12392 | struct drm_file *filp, | |
308e5bcb | 12393 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 12394 | { |
05394f39 | 12395 | struct drm_i915_gem_object *obj; |
79e53945 | 12396 | |
308e5bcb JB |
12397 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
12398 | mode_cmd->handles[0])); | |
c8725226 | 12399 | if (&obj->base == NULL) |
cce13ff7 | 12400 | return ERR_PTR(-ENOENT); |
79e53945 | 12401 | |
d2dff872 | 12402 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
12403 | } |
12404 | ||
4520f53a | 12405 | #ifndef CONFIG_DRM_I915_FBDEV |
0632fef6 | 12406 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
12407 | { |
12408 | } | |
12409 | #endif | |
12410 | ||
79e53945 | 12411 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 12412 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 12413 | .output_poll_changed = intel_fbdev_output_poll_changed, |
79e53945 JB |
12414 | }; |
12415 | ||
e70236a8 JB |
12416 | /* Set up chip specific display functions */ |
12417 | static void intel_init_display(struct drm_device *dev) | |
12418 | { | |
12419 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12420 | ||
ee9300bb DV |
12421 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
12422 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
12423 | else if (IS_CHERRYVIEW(dev)) |
12424 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
12425 | else if (IS_VALLEYVIEW(dev)) |
12426 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
12427 | else if (IS_PINEVIEW(dev)) | |
12428 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
12429 | else | |
12430 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
12431 | ||
affa9354 | 12432 | if (HAS_DDI(dev)) { |
0e8ffe1b | 12433 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
4c6baa59 | 12434 | dev_priv->display.get_plane_config = ironlake_get_plane_config; |
09b4ddf9 | 12435 | dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; |
4f771f10 PZ |
12436 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
12437 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
df8ad70c | 12438 | dev_priv->display.off = ironlake_crtc_off; |
262ca2b0 MR |
12439 | dev_priv->display.update_primary_plane = |
12440 | ironlake_update_primary_plane; | |
09b4ddf9 | 12441 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 12442 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
4c6baa59 | 12443 | dev_priv->display.get_plane_config = ironlake_get_plane_config; |
f564048e | 12444 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
76e5a89c DV |
12445 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
12446 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
ee7b9f93 | 12447 | dev_priv->display.off = ironlake_crtc_off; |
262ca2b0 MR |
12448 | dev_priv->display.update_primary_plane = |
12449 | ironlake_update_primary_plane; | |
89b667f8 JB |
12450 | } else if (IS_VALLEYVIEW(dev)) { |
12451 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
1ad292b5 | 12452 | dev_priv->display.get_plane_config = i9xx_get_plane_config; |
89b667f8 JB |
12453 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
12454 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
12455 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
12456 | dev_priv->display.off = i9xx_crtc_off; | |
262ca2b0 MR |
12457 | dev_priv->display.update_primary_plane = |
12458 | i9xx_update_primary_plane; | |
f564048e | 12459 | } else { |
0e8ffe1b | 12460 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
1ad292b5 | 12461 | dev_priv->display.get_plane_config = i9xx_get_plane_config; |
f564048e | 12462 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
76e5a89c DV |
12463 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
12464 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
ee7b9f93 | 12465 | dev_priv->display.off = i9xx_crtc_off; |
262ca2b0 MR |
12466 | dev_priv->display.update_primary_plane = |
12467 | i9xx_update_primary_plane; | |
f564048e | 12468 | } |
e70236a8 | 12469 | |
e70236a8 | 12470 | /* Returns the core display clock speed */ |
25eb05fc JB |
12471 | if (IS_VALLEYVIEW(dev)) |
12472 | dev_priv->display.get_display_clock_speed = | |
12473 | valleyview_get_display_clock_speed; | |
12474 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
12475 | dev_priv->display.get_display_clock_speed = |
12476 | i945_get_display_clock_speed; | |
12477 | else if (IS_I915G(dev)) | |
12478 | dev_priv->display.get_display_clock_speed = | |
12479 | i915_get_display_clock_speed; | |
257a7ffc | 12480 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
12481 | dev_priv->display.get_display_clock_speed = |
12482 | i9xx_misc_get_display_clock_speed; | |
257a7ffc DV |
12483 | else if (IS_PINEVIEW(dev)) |
12484 | dev_priv->display.get_display_clock_speed = | |
12485 | pnv_get_display_clock_speed; | |
e70236a8 JB |
12486 | else if (IS_I915GM(dev)) |
12487 | dev_priv->display.get_display_clock_speed = | |
12488 | i915gm_get_display_clock_speed; | |
12489 | else if (IS_I865G(dev)) | |
12490 | dev_priv->display.get_display_clock_speed = | |
12491 | i865_get_display_clock_speed; | |
f0f8a9ce | 12492 | else if (IS_I85X(dev)) |
e70236a8 JB |
12493 | dev_priv->display.get_display_clock_speed = |
12494 | i855_get_display_clock_speed; | |
12495 | else /* 852, 830 */ | |
12496 | dev_priv->display.get_display_clock_speed = | |
12497 | i830_get_display_clock_speed; | |
12498 | ||
3bb11b53 | 12499 | if (IS_G4X(dev)) { |
e0dac65e | 12500 | dev_priv->display.write_eld = g4x_write_eld; |
3bb11b53 SJ |
12501 | } else if (IS_GEN5(dev)) { |
12502 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; | |
12503 | dev_priv->display.write_eld = ironlake_write_eld; | |
12504 | } else if (IS_GEN6(dev)) { | |
12505 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; | |
12506 | dev_priv->display.write_eld = ironlake_write_eld; | |
12507 | dev_priv->display.modeset_global_resources = | |
12508 | snb_modeset_global_resources; | |
12509 | } else if (IS_IVYBRIDGE(dev)) { | |
12510 | /* FIXME: detect B0+ stepping and use auto training */ | |
12511 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
12512 | dev_priv->display.write_eld = ironlake_write_eld; | |
12513 | dev_priv->display.modeset_global_resources = | |
12514 | ivb_modeset_global_resources; | |
12515 | } else if (IS_HASWELL(dev) || IS_GEN8(dev)) { | |
12516 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; | |
12517 | dev_priv->display.write_eld = haswell_write_eld; | |
12518 | dev_priv->display.modeset_global_resources = | |
12519 | haswell_modeset_global_resources; | |
30a970c6 JB |
12520 | } else if (IS_VALLEYVIEW(dev)) { |
12521 | dev_priv->display.modeset_global_resources = | |
12522 | valleyview_modeset_global_resources; | |
9ca2fe73 | 12523 | dev_priv->display.write_eld = ironlake_write_eld; |
e70236a8 | 12524 | } |
8c9f3aaf JB |
12525 | |
12526 | /* Default just returns -ENODEV to indicate unsupported */ | |
12527 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
12528 | ||
12529 | switch (INTEL_INFO(dev)->gen) { | |
12530 | case 2: | |
12531 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
12532 | break; | |
12533 | ||
12534 | case 3: | |
12535 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
12536 | break; | |
12537 | ||
12538 | case 4: | |
12539 | case 5: | |
12540 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
12541 | break; | |
12542 | ||
12543 | case 6: | |
12544 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
12545 | break; | |
7c9017e5 | 12546 | case 7: |
4e0bbc31 | 12547 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
12548 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
12549 | break; | |
8c9f3aaf | 12550 | } |
7bd688cd JN |
12551 | |
12552 | intel_panel_init_backlight_funcs(dev); | |
e70236a8 JB |
12553 | } |
12554 | ||
b690e96c JB |
12555 | /* |
12556 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
12557 | * resume, or other times. This quirk makes sure that's the case for | |
12558 | * affected systems. | |
12559 | */ | |
0206e353 | 12560 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
12561 | { |
12562 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12563 | ||
12564 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 12565 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
12566 | } |
12567 | ||
435793df KP |
12568 | /* |
12569 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
12570 | */ | |
12571 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
12572 | { | |
12573 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12574 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 12575 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
12576 | } |
12577 | ||
4dca20ef | 12578 | /* |
5a15ab5b CE |
12579 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
12580 | * brightness value | |
4dca20ef CE |
12581 | */ |
12582 | static void quirk_invert_brightness(struct drm_device *dev) | |
12583 | { | |
12584 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12585 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 12586 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
12587 | } |
12588 | ||
9c72cc6f SD |
12589 | /* Some VBT's incorrectly indicate no backlight is present */ |
12590 | static void quirk_backlight_present(struct drm_device *dev) | |
12591 | { | |
12592 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12593 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
12594 | DRM_INFO("applying backlight present quirk\n"); | |
12595 | } | |
12596 | ||
b690e96c JB |
12597 | struct intel_quirk { |
12598 | int device; | |
12599 | int subsystem_vendor; | |
12600 | int subsystem_device; | |
12601 | void (*hook)(struct drm_device *dev); | |
12602 | }; | |
12603 | ||
5f85f176 EE |
12604 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
12605 | struct intel_dmi_quirk { | |
12606 | void (*hook)(struct drm_device *dev); | |
12607 | const struct dmi_system_id (*dmi_id_list)[]; | |
12608 | }; | |
12609 | ||
12610 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
12611 | { | |
12612 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
12613 | return 1; | |
12614 | } | |
12615 | ||
12616 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
12617 | { | |
12618 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
12619 | { | |
12620 | .callback = intel_dmi_reverse_brightness, | |
12621 | .ident = "NCR Corporation", | |
12622 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
12623 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
12624 | }, | |
12625 | }, | |
12626 | { } /* terminating entry */ | |
12627 | }, | |
12628 | .hook = quirk_invert_brightness, | |
12629 | }, | |
12630 | }; | |
12631 | ||
c43b5634 | 12632 | static struct intel_quirk intel_quirks[] = { |
b690e96c | 12633 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 12634 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c | 12635 | |
b690e96c JB |
12636 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
12637 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
12638 | ||
b690e96c JB |
12639 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
12640 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
12641 | ||
5f080c0f VS |
12642 | /* 830 needs to leave pipe A & dpll A up */ |
12643 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
12644 | ||
435793df KP |
12645 | /* Lenovo U160 cannot use SSC on LVDS */ |
12646 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
12647 | |
12648 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
12649 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 12650 | |
be505f64 AH |
12651 | /* Acer Aspire 5734Z must invert backlight brightness */ |
12652 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
12653 | ||
12654 | /* Acer/eMachines G725 */ | |
12655 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
12656 | ||
12657 | /* Acer/eMachines e725 */ | |
12658 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
12659 | ||
12660 | /* Acer/Packard Bell NCL20 */ | |
12661 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
12662 | ||
12663 | /* Acer Aspire 4736Z */ | |
12664 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
12665 | |
12666 | /* Acer Aspire 5336 */ | |
12667 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
12668 | |
12669 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
12670 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c SD |
12671 | |
12672 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ | |
12673 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
12674 | |
12675 | /* HP Chromebook 14 (Celeron 2955U) */ | |
12676 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
b690e96c JB |
12677 | }; |
12678 | ||
12679 | static void intel_init_quirks(struct drm_device *dev) | |
12680 | { | |
12681 | struct pci_dev *d = dev->pdev; | |
12682 | int i; | |
12683 | ||
12684 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
12685 | struct intel_quirk *q = &intel_quirks[i]; | |
12686 | ||
12687 | if (d->device == q->device && | |
12688 | (d->subsystem_vendor == q->subsystem_vendor || | |
12689 | q->subsystem_vendor == PCI_ANY_ID) && | |
12690 | (d->subsystem_device == q->subsystem_device || | |
12691 | q->subsystem_device == PCI_ANY_ID)) | |
12692 | q->hook(dev); | |
12693 | } | |
5f85f176 EE |
12694 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
12695 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
12696 | intel_dmi_quirks[i].hook(dev); | |
12697 | } | |
b690e96c JB |
12698 | } |
12699 | ||
9cce37f4 JB |
12700 | /* Disable the VGA plane that we never use */ |
12701 | static void i915_disable_vga(struct drm_device *dev) | |
12702 | { | |
12703 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12704 | u8 sr1; | |
766aa1c4 | 12705 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 12706 | |
2b37c616 | 12707 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 12708 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 12709 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
12710 | sr1 = inb(VGA_SR_DATA); |
12711 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
12712 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
12713 | udelay(300); | |
12714 | ||
12715 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); | |
12716 | POSTING_READ(vga_reg); | |
12717 | } | |
12718 | ||
f817586c DV |
12719 | void intel_modeset_init_hw(struct drm_device *dev) |
12720 | { | |
a8f78b58 ED |
12721 | intel_prepare_ddi(dev); |
12722 | ||
f8bf63fd VS |
12723 | if (IS_VALLEYVIEW(dev)) |
12724 | vlv_update_cdclk(dev); | |
12725 | ||
f817586c DV |
12726 | intel_init_clock_gating(dev); |
12727 | ||
8090c6b9 | 12728 | intel_enable_gt_powersave(dev); |
f817586c DV |
12729 | } |
12730 | ||
7d708ee4 ID |
12731 | void intel_modeset_suspend_hw(struct drm_device *dev) |
12732 | { | |
12733 | intel_suspend_hw(dev); | |
12734 | } | |
12735 | ||
79e53945 JB |
12736 | void intel_modeset_init(struct drm_device *dev) |
12737 | { | |
652c393a | 12738 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 12739 | int sprite, ret; |
8cc87b75 | 12740 | enum pipe pipe; |
46f297fb | 12741 | struct intel_crtc *crtc; |
79e53945 JB |
12742 | |
12743 | drm_mode_config_init(dev); | |
12744 | ||
12745 | dev->mode_config.min_width = 0; | |
12746 | dev->mode_config.min_height = 0; | |
12747 | ||
019d96cb DA |
12748 | dev->mode_config.preferred_depth = 24; |
12749 | dev->mode_config.prefer_shadow = 1; | |
12750 | ||
e6ecefaa | 12751 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 12752 | |
b690e96c JB |
12753 | intel_init_quirks(dev); |
12754 | ||
1fa61106 ED |
12755 | intel_init_pm(dev); |
12756 | ||
e3c74757 BW |
12757 | if (INTEL_INFO(dev)->num_pipes == 0) |
12758 | return; | |
12759 | ||
e70236a8 JB |
12760 | intel_init_display(dev); |
12761 | ||
a6c45cf0 CW |
12762 | if (IS_GEN2(dev)) { |
12763 | dev->mode_config.max_width = 2048; | |
12764 | dev->mode_config.max_height = 2048; | |
12765 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
12766 | dev->mode_config.max_width = 4096; |
12767 | dev->mode_config.max_height = 4096; | |
79e53945 | 12768 | } else { |
a6c45cf0 CW |
12769 | dev->mode_config.max_width = 8192; |
12770 | dev->mode_config.max_height = 8192; | |
79e53945 | 12771 | } |
068be561 | 12772 | |
dc41c154 VS |
12773 | if (IS_845G(dev) || IS_I865G(dev)) { |
12774 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
12775 | dev->mode_config.cursor_height = 1023; | |
12776 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
12777 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
12778 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
12779 | } else { | |
12780 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
12781 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
12782 | } | |
12783 | ||
5d4545ae | 12784 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 12785 | |
28c97730 | 12786 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
12787 | INTEL_INFO(dev)->num_pipes, |
12788 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 12789 | |
055e393f | 12790 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 12791 | intel_crtc_init(dev, pipe); |
1fe47785 DL |
12792 | for_each_sprite(pipe, sprite) { |
12793 | ret = intel_plane_init(dev, pipe, sprite); | |
7f1f3851 | 12794 | if (ret) |
06da8da2 | 12795 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 12796 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 12797 | } |
79e53945 JB |
12798 | } |
12799 | ||
f42bb70d JB |
12800 | intel_init_dpio(dev); |
12801 | ||
e72f9fbf | 12802 | intel_shared_dpll_init(dev); |
ee7b9f93 | 12803 | |
9cce37f4 JB |
12804 | /* Just disable it once at startup */ |
12805 | i915_disable_vga(dev); | |
79e53945 | 12806 | intel_setup_outputs(dev); |
11be49eb CW |
12807 | |
12808 | /* Just in case the BIOS is doing something questionable. */ | |
12809 | intel_disable_fbc(dev); | |
fa9fa083 | 12810 | |
6e9f798d | 12811 | drm_modeset_lock_all(dev); |
fa9fa083 | 12812 | intel_modeset_setup_hw_state(dev, false); |
6e9f798d | 12813 | drm_modeset_unlock_all(dev); |
46f297fb | 12814 | |
d3fcc808 | 12815 | for_each_intel_crtc(dev, crtc) { |
46f297fb JB |
12816 | if (!crtc->active) |
12817 | continue; | |
12818 | ||
46f297fb | 12819 | /* |
46f297fb JB |
12820 | * Note that reserving the BIOS fb up front prevents us |
12821 | * from stuffing other stolen allocations like the ring | |
12822 | * on top. This prevents some ugliness at boot time, and | |
12823 | * can even allow for smooth boot transitions if the BIOS | |
12824 | * fb is large enough for the active pipe configuration. | |
12825 | */ | |
12826 | if (dev_priv->display.get_plane_config) { | |
12827 | dev_priv->display.get_plane_config(crtc, | |
12828 | &crtc->plane_config); | |
12829 | /* | |
12830 | * If the fb is shared between multiple heads, we'll | |
12831 | * just get the first one. | |
12832 | */ | |
484b41dd | 12833 | intel_find_plane_obj(crtc, &crtc->plane_config); |
46f297fb | 12834 | } |
46f297fb | 12835 | } |
2c7111db CW |
12836 | } |
12837 | ||
7fad798e DV |
12838 | static void intel_enable_pipe_a(struct drm_device *dev) |
12839 | { | |
12840 | struct intel_connector *connector; | |
12841 | struct drm_connector *crt = NULL; | |
12842 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 12843 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
12844 | |
12845 | /* We can't just switch on the pipe A, we need to set things up with a | |
12846 | * proper mode and output configuration. As a gross hack, enable pipe A | |
12847 | * by enabling the load detect pipe once. */ | |
12848 | list_for_each_entry(connector, | |
12849 | &dev->mode_config.connector_list, | |
12850 | base.head) { | |
12851 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { | |
12852 | crt = &connector->base; | |
12853 | break; | |
12854 | } | |
12855 | } | |
12856 | ||
12857 | if (!crt) | |
12858 | return; | |
12859 | ||
208bf9fd VS |
12860 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
12861 | intel_release_load_detect_pipe(crt, &load_detect_temp); | |
7fad798e DV |
12862 | } |
12863 | ||
fa555837 DV |
12864 | static bool |
12865 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
12866 | { | |
7eb552ae BW |
12867 | struct drm_device *dev = crtc->base.dev; |
12868 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
12869 | u32 reg, val; |
12870 | ||
7eb552ae | 12871 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
12872 | return true; |
12873 | ||
12874 | reg = DSPCNTR(!crtc->plane); | |
12875 | val = I915_READ(reg); | |
12876 | ||
12877 | if ((val & DISPLAY_PLANE_ENABLE) && | |
12878 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
12879 | return false; | |
12880 | ||
12881 | return true; | |
12882 | } | |
12883 | ||
24929352 DV |
12884 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
12885 | { | |
12886 | struct drm_device *dev = crtc->base.dev; | |
12887 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 12888 | u32 reg; |
24929352 | 12889 | |
24929352 | 12890 | /* Clear any frame start delays used for debugging left by the BIOS */ |
3b117c8f | 12891 | reg = PIPECONF(crtc->config.cpu_transcoder); |
24929352 DV |
12892 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
12893 | ||
d3eaf884 VS |
12894 | /* restore vblank interrupts to correct state */ |
12895 | if (crtc->active) | |
12896 | drm_vblank_on(dev, crtc->pipe); | |
12897 | else | |
12898 | drm_vblank_off(dev, crtc->pipe); | |
12899 | ||
24929352 | 12900 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
12901 | * disable the crtc (and hence change the state) if it is wrong. Note |
12902 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
12903 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
12904 | struct intel_connector *connector; |
12905 | bool plane; | |
12906 | ||
24929352 DV |
12907 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
12908 | crtc->base.base.id); | |
12909 | ||
12910 | /* Pipe has the wrong plane attached and the plane is active. | |
12911 | * Temporarily change the plane mapping and disable everything | |
12912 | * ... */ | |
12913 | plane = crtc->plane; | |
12914 | crtc->plane = !plane; | |
9c8958bc | 12915 | crtc->primary_enabled = true; |
24929352 DV |
12916 | dev_priv->display.crtc_disable(&crtc->base); |
12917 | crtc->plane = plane; | |
12918 | ||
12919 | /* ... and break all links. */ | |
12920 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
12921 | base.head) { | |
12922 | if (connector->encoder->base.crtc != &crtc->base) | |
12923 | continue; | |
12924 | ||
7f1950fb EE |
12925 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
12926 | connector->base.encoder = NULL; | |
24929352 | 12927 | } |
7f1950fb EE |
12928 | /* multiple connectors may have the same encoder: |
12929 | * handle them and break crtc link separately */ | |
12930 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
12931 | base.head) | |
12932 | if (connector->encoder->base.crtc == &crtc->base) { | |
12933 | connector->encoder->base.crtc = NULL; | |
12934 | connector->encoder->connectors_active = false; | |
12935 | } | |
24929352 DV |
12936 | |
12937 | WARN_ON(crtc->active); | |
12938 | crtc->base.enabled = false; | |
12939 | } | |
24929352 | 12940 | |
7fad798e DV |
12941 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
12942 | crtc->pipe == PIPE_A && !crtc->active) { | |
12943 | /* BIOS forgot to enable pipe A, this mostly happens after | |
12944 | * resume. Force-enable the pipe to fix this, the update_dpms | |
12945 | * call below we restore the pipe to the right state, but leave | |
12946 | * the required bits on. */ | |
12947 | intel_enable_pipe_a(dev); | |
12948 | } | |
12949 | ||
24929352 DV |
12950 | /* Adjust the state of the output pipe according to whether we |
12951 | * have active connectors/encoders. */ | |
12952 | intel_crtc_update_dpms(&crtc->base); | |
12953 | ||
12954 | if (crtc->active != crtc->base.enabled) { | |
12955 | struct intel_encoder *encoder; | |
12956 | ||
12957 | /* This can happen either due to bugs in the get_hw_state | |
12958 | * functions or because the pipe is force-enabled due to the | |
12959 | * pipe A quirk. */ | |
12960 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
12961 | crtc->base.base.id, | |
12962 | crtc->base.enabled ? "enabled" : "disabled", | |
12963 | crtc->active ? "enabled" : "disabled"); | |
12964 | ||
12965 | crtc->base.enabled = crtc->active; | |
12966 | ||
12967 | /* Because we only establish the connector -> encoder -> | |
12968 | * crtc links if something is active, this means the | |
12969 | * crtc is now deactivated. Break the links. connector | |
12970 | * -> encoder links are only establish when things are | |
12971 | * actually up, hence no need to break them. */ | |
12972 | WARN_ON(crtc->active); | |
12973 | ||
12974 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
12975 | WARN_ON(encoder->connectors_active); | |
12976 | encoder->base.crtc = NULL; | |
12977 | } | |
12978 | } | |
c5ab3bc0 DV |
12979 | |
12980 | if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) { | |
4cc31489 DV |
12981 | /* |
12982 | * We start out with underrun reporting disabled to avoid races. | |
12983 | * For correct bookkeeping mark this on active crtcs. | |
12984 | * | |
c5ab3bc0 DV |
12985 | * Also on gmch platforms we dont have any hardware bits to |
12986 | * disable the underrun reporting. Which means we need to start | |
12987 | * out with underrun reporting disabled also on inactive pipes, | |
12988 | * since otherwise we'll complain about the garbage we read when | |
12989 | * e.g. coming up after runtime pm. | |
12990 | * | |
4cc31489 DV |
12991 | * No protection against concurrent access is required - at |
12992 | * worst a fifo underrun happens which also sets this to false. | |
12993 | */ | |
12994 | crtc->cpu_fifo_underrun_disabled = true; | |
12995 | crtc->pch_fifo_underrun_disabled = true; | |
80715b2f VS |
12996 | |
12997 | update_scanline_offset(crtc); | |
4cc31489 | 12998 | } |
24929352 DV |
12999 | } |
13000 | ||
13001 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
13002 | { | |
13003 | struct intel_connector *connector; | |
13004 | struct drm_device *dev = encoder->base.dev; | |
13005 | ||
13006 | /* We need to check both for a crtc link (meaning that the | |
13007 | * encoder is active and trying to read from a pipe) and the | |
13008 | * pipe itself being active. */ | |
13009 | bool has_active_crtc = encoder->base.crtc && | |
13010 | to_intel_crtc(encoder->base.crtc)->active; | |
13011 | ||
13012 | if (encoder->connectors_active && !has_active_crtc) { | |
13013 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
13014 | encoder->base.base.id, | |
8e329a03 | 13015 | encoder->base.name); |
24929352 DV |
13016 | |
13017 | /* Connector is active, but has no active pipe. This is | |
13018 | * fallout from our resume register restoring. Disable | |
13019 | * the encoder manually again. */ | |
13020 | if (encoder->base.crtc) { | |
13021 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
13022 | encoder->base.base.id, | |
8e329a03 | 13023 | encoder->base.name); |
24929352 | 13024 | encoder->disable(encoder); |
a62d1497 VS |
13025 | if (encoder->post_disable) |
13026 | encoder->post_disable(encoder); | |
24929352 | 13027 | } |
7f1950fb EE |
13028 | encoder->base.crtc = NULL; |
13029 | encoder->connectors_active = false; | |
24929352 DV |
13030 | |
13031 | /* Inconsistent output/port/pipe state happens presumably due to | |
13032 | * a bug in one of the get_hw_state functions. Or someplace else | |
13033 | * in our code, like the register restore mess on resume. Clamp | |
13034 | * things to off as a safer default. */ | |
13035 | list_for_each_entry(connector, | |
13036 | &dev->mode_config.connector_list, | |
13037 | base.head) { | |
13038 | if (connector->encoder != encoder) | |
13039 | continue; | |
7f1950fb EE |
13040 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
13041 | connector->base.encoder = NULL; | |
24929352 DV |
13042 | } |
13043 | } | |
13044 | /* Enabled encoders without active connectors will be fixed in | |
13045 | * the crtc fixup. */ | |
13046 | } | |
13047 | ||
04098753 | 13048 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
13049 | { |
13050 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 13051 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 13052 | |
04098753 ID |
13053 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
13054 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
13055 | i915_disable_vga(dev); | |
13056 | } | |
13057 | } | |
13058 | ||
13059 | void i915_redisable_vga(struct drm_device *dev) | |
13060 | { | |
13061 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13062 | ||
8dc8a27c PZ |
13063 | /* This function can be called both from intel_modeset_setup_hw_state or |
13064 | * at a very early point in our resume sequence, where the power well | |
13065 | * structures are not yet restored. Since this function is at a very | |
13066 | * paranoid "someone might have enabled VGA while we were not looking" | |
13067 | * level, just check if the power well is enabled instead of trying to | |
13068 | * follow the "don't touch the power well if we don't need it" policy | |
13069 | * the rest of the driver uses. */ | |
04098753 | 13070 | if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
13071 | return; |
13072 | ||
04098753 | 13073 | i915_redisable_vga_power_on(dev); |
0fde901f KM |
13074 | } |
13075 | ||
98ec7739 VS |
13076 | static bool primary_get_hw_state(struct intel_crtc *crtc) |
13077 | { | |
13078 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
13079 | ||
13080 | if (!crtc->active) | |
13081 | return false; | |
13082 | ||
13083 | return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE; | |
13084 | } | |
13085 | ||
30e984df | 13086 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
13087 | { |
13088 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13089 | enum pipe pipe; | |
24929352 DV |
13090 | struct intel_crtc *crtc; |
13091 | struct intel_encoder *encoder; | |
13092 | struct intel_connector *connector; | |
5358901f | 13093 | int i; |
24929352 | 13094 | |
d3fcc808 | 13095 | for_each_intel_crtc(dev, crtc) { |
88adfff1 | 13096 | memset(&crtc->config, 0, sizeof(crtc->config)); |
3b117c8f | 13097 | |
9953599b DV |
13098 | crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE; |
13099 | ||
0e8ffe1b DV |
13100 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
13101 | &crtc->config); | |
24929352 DV |
13102 | |
13103 | crtc->base.enabled = crtc->active; | |
98ec7739 | 13104 | crtc->primary_enabled = primary_get_hw_state(crtc); |
24929352 DV |
13105 | |
13106 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
13107 | crtc->base.base.id, | |
13108 | crtc->active ? "enabled" : "disabled"); | |
13109 | } | |
13110 | ||
5358901f DV |
13111 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
13112 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
13113 | ||
13114 | pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state); | |
13115 | pll->active = 0; | |
d3fcc808 | 13116 | for_each_intel_crtc(dev, crtc) { |
5358901f DV |
13117 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) |
13118 | pll->active++; | |
13119 | } | |
13120 | pll->refcount = pll->active; | |
13121 | ||
35c95375 DV |
13122 | DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n", |
13123 | pll->name, pll->refcount, pll->on); | |
bd2bb1b9 PZ |
13124 | |
13125 | if (pll->refcount) | |
13126 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); | |
5358901f DV |
13127 | } |
13128 | ||
b2784e15 | 13129 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
13130 | pipe = 0; |
13131 | ||
13132 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
13133 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
13134 | encoder->base.crtc = &crtc->base; | |
1d37b689 | 13135 | encoder->get_config(encoder, &crtc->config); |
24929352 DV |
13136 | } else { |
13137 | encoder->base.crtc = NULL; | |
13138 | } | |
13139 | ||
13140 | encoder->connectors_active = false; | |
6f2bcceb | 13141 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 13142 | encoder->base.base.id, |
8e329a03 | 13143 | encoder->base.name, |
24929352 | 13144 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 13145 | pipe_name(pipe)); |
24929352 DV |
13146 | } |
13147 | ||
13148 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
13149 | base.head) { | |
13150 | if (connector->get_hw_state(connector)) { | |
13151 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
13152 | connector->encoder->connectors_active = true; | |
13153 | connector->base.encoder = &connector->encoder->base; | |
13154 | } else { | |
13155 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
13156 | connector->base.encoder = NULL; | |
13157 | } | |
13158 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
13159 | connector->base.base.id, | |
c23cc417 | 13160 | connector->base.name, |
24929352 DV |
13161 | connector->base.encoder ? "enabled" : "disabled"); |
13162 | } | |
30e984df DV |
13163 | } |
13164 | ||
13165 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm | |
13166 | * and i915 state tracking structures. */ | |
13167 | void intel_modeset_setup_hw_state(struct drm_device *dev, | |
13168 | bool force_restore) | |
13169 | { | |
13170 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13171 | enum pipe pipe; | |
30e984df DV |
13172 | struct intel_crtc *crtc; |
13173 | struct intel_encoder *encoder; | |
35c95375 | 13174 | int i; |
30e984df DV |
13175 | |
13176 | intel_modeset_readout_hw_state(dev); | |
24929352 | 13177 | |
babea61d JB |
13178 | /* |
13179 | * Now that we have the config, copy it to each CRTC struct | |
13180 | * Note that this could go away if we move to using crtc_config | |
13181 | * checking everywhere. | |
13182 | */ | |
d3fcc808 | 13183 | for_each_intel_crtc(dev, crtc) { |
d330a953 | 13184 | if (crtc->active && i915.fastboot) { |
f6a83288 | 13185 | intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config); |
babea61d JB |
13186 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", |
13187 | crtc->base.base.id); | |
13188 | drm_mode_debug_printmodeline(&crtc->base.mode); | |
13189 | } | |
13190 | } | |
13191 | ||
24929352 | 13192 | /* HW state is read out, now we need to sanitize this mess. */ |
b2784e15 | 13193 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
13194 | intel_sanitize_encoder(encoder); |
13195 | } | |
13196 | ||
055e393f | 13197 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
13198 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
13199 | intel_sanitize_crtc(crtc); | |
c0b03411 | 13200 | intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]"); |
24929352 | 13201 | } |
9a935856 | 13202 | |
35c95375 DV |
13203 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
13204 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
13205 | ||
13206 | if (!pll->on || pll->active) | |
13207 | continue; | |
13208 | ||
13209 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
13210 | ||
13211 | pll->disable(dev_priv, pll); | |
13212 | pll->on = false; | |
13213 | } | |
13214 | ||
96f90c54 | 13215 | if (HAS_PCH_SPLIT(dev)) |
243e6a44 VS |
13216 | ilk_wm_get_hw_state(dev); |
13217 | ||
45e2b5f6 | 13218 | if (force_restore) { |
7d0bc1ea VS |
13219 | i915_redisable_vga(dev); |
13220 | ||
f30da187 DV |
13221 | /* |
13222 | * We need to use raw interfaces for restoring state to avoid | |
13223 | * checking (bogus) intermediate states. | |
13224 | */ | |
055e393f | 13225 | for_each_pipe(dev_priv, pipe) { |
b5644d05 JB |
13226 | struct drm_crtc *crtc = |
13227 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
f30da187 DV |
13228 | |
13229 | __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, | |
f4510a27 | 13230 | crtc->primary->fb); |
45e2b5f6 DV |
13231 | } |
13232 | } else { | |
13233 | intel_modeset_update_staged_output_state(dev); | |
13234 | } | |
8af6cf88 DV |
13235 | |
13236 | intel_modeset_check_state(dev); | |
2c7111db CW |
13237 | } |
13238 | ||
13239 | void intel_modeset_gem_init(struct drm_device *dev) | |
13240 | { | |
484b41dd | 13241 | struct drm_crtc *c; |
2ff8fde1 | 13242 | struct drm_i915_gem_object *obj; |
484b41dd | 13243 | |
ae48434c ID |
13244 | mutex_lock(&dev->struct_mutex); |
13245 | intel_init_gt_powersave(dev); | |
13246 | mutex_unlock(&dev->struct_mutex); | |
13247 | ||
1833b134 | 13248 | intel_modeset_init_hw(dev); |
02e792fb DV |
13249 | |
13250 | intel_setup_overlay(dev); | |
484b41dd JB |
13251 | |
13252 | /* | |
13253 | * Make sure any fbs we allocated at startup are properly | |
13254 | * pinned & fenced. When we do the allocation it's too early | |
13255 | * for this. | |
13256 | */ | |
13257 | mutex_lock(&dev->struct_mutex); | |
70e1e0ec | 13258 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
13259 | obj = intel_fb_obj(c->primary->fb); |
13260 | if (obj == NULL) | |
484b41dd JB |
13261 | continue; |
13262 | ||
2ff8fde1 | 13263 | if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) { |
484b41dd JB |
13264 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
13265 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
13266 | drm_framebuffer_unreference(c->primary->fb); |
13267 | c->primary->fb = NULL; | |
484b41dd JB |
13268 | } |
13269 | } | |
13270 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
13271 | } |
13272 | ||
4932e2c3 ID |
13273 | void intel_connector_unregister(struct intel_connector *intel_connector) |
13274 | { | |
13275 | struct drm_connector *connector = &intel_connector->base; | |
13276 | ||
13277 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 13278 | drm_connector_unregister(connector); |
4932e2c3 ID |
13279 | } |
13280 | ||
79e53945 JB |
13281 | void intel_modeset_cleanup(struct drm_device *dev) |
13282 | { | |
652c393a | 13283 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9255d57 | 13284 | struct drm_connector *connector; |
652c393a | 13285 | |
fd0c0642 DV |
13286 | /* |
13287 | * Interrupts and polling as the first thing to avoid creating havoc. | |
13288 | * Too much stuff here (turning of rps, connectors, ...) would | |
13289 | * experience fancy races otherwise. | |
13290 | */ | |
13291 | drm_irq_uninstall(dev); | |
1d0d343a | 13292 | intel_hpd_cancel_work(dev_priv); |
eb21b92b JB |
13293 | dev_priv->pm._irqs_disabled = true; |
13294 | ||
fd0c0642 DV |
13295 | /* |
13296 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
13297 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
13298 | */ | |
f87ea761 | 13299 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 13300 | |
652c393a JB |
13301 | mutex_lock(&dev->struct_mutex); |
13302 | ||
723bfd70 JB |
13303 | intel_unregister_dsm_handler(); |
13304 | ||
973d04f9 | 13305 | intel_disable_fbc(dev); |
e70236a8 | 13306 | |
8090c6b9 | 13307 | intel_disable_gt_powersave(dev); |
0cdab21f | 13308 | |
930ebb46 DV |
13309 | ironlake_teardown_rc6(dev); |
13310 | ||
69341a5e KH |
13311 | mutex_unlock(&dev->struct_mutex); |
13312 | ||
1630fe75 CW |
13313 | /* flush any delayed tasks or pending work */ |
13314 | flush_scheduled_work(); | |
13315 | ||
db31af1d JN |
13316 | /* destroy the backlight and sysfs files before encoders/connectors */ |
13317 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4932e2c3 ID |
13318 | struct intel_connector *intel_connector; |
13319 | ||
13320 | intel_connector = to_intel_connector(connector); | |
13321 | intel_connector->unregister(intel_connector); | |
db31af1d | 13322 | } |
d9255d57 | 13323 | |
79e53945 | 13324 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
13325 | |
13326 | intel_cleanup_overlay(dev); | |
ae48434c ID |
13327 | |
13328 | mutex_lock(&dev->struct_mutex); | |
13329 | intel_cleanup_gt_powersave(dev); | |
13330 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
13331 | } |
13332 | ||
f1c79df3 ZW |
13333 | /* |
13334 | * Return which encoder is currently attached for connector. | |
13335 | */ | |
df0e9248 | 13336 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 13337 | { |
df0e9248 CW |
13338 | return &intel_attached_encoder(connector)->base; |
13339 | } | |
f1c79df3 | 13340 | |
df0e9248 CW |
13341 | void intel_connector_attach_encoder(struct intel_connector *connector, |
13342 | struct intel_encoder *encoder) | |
13343 | { | |
13344 | connector->encoder = encoder; | |
13345 | drm_mode_connector_attach_encoder(&connector->base, | |
13346 | &encoder->base); | |
79e53945 | 13347 | } |
28d52043 DA |
13348 | |
13349 | /* | |
13350 | * set vga decode state - true == enable VGA decode | |
13351 | */ | |
13352 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
13353 | { | |
13354 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 13355 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
13356 | u16 gmch_ctrl; |
13357 | ||
75fa041d CW |
13358 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
13359 | DRM_ERROR("failed to read control word\n"); | |
13360 | return -EIO; | |
13361 | } | |
13362 | ||
c0cc8a55 CW |
13363 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
13364 | return 0; | |
13365 | ||
28d52043 DA |
13366 | if (state) |
13367 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
13368 | else | |
13369 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
13370 | |
13371 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
13372 | DRM_ERROR("failed to write control word\n"); | |
13373 | return -EIO; | |
13374 | } | |
13375 | ||
28d52043 DA |
13376 | return 0; |
13377 | } | |
c4a1d9e4 | 13378 | |
c4a1d9e4 | 13379 | struct intel_display_error_state { |
ff57f1b0 PZ |
13380 | |
13381 | u32 power_well_driver; | |
13382 | ||
63b66e5b CW |
13383 | int num_transcoders; |
13384 | ||
c4a1d9e4 CW |
13385 | struct intel_cursor_error_state { |
13386 | u32 control; | |
13387 | u32 position; | |
13388 | u32 base; | |
13389 | u32 size; | |
52331309 | 13390 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
13391 | |
13392 | struct intel_pipe_error_state { | |
ddf9c536 | 13393 | bool power_domain_on; |
c4a1d9e4 | 13394 | u32 source; |
f301b1e1 | 13395 | u32 stat; |
52331309 | 13396 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
13397 | |
13398 | struct intel_plane_error_state { | |
13399 | u32 control; | |
13400 | u32 stride; | |
13401 | u32 size; | |
13402 | u32 pos; | |
13403 | u32 addr; | |
13404 | u32 surface; | |
13405 | u32 tile_offset; | |
52331309 | 13406 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
13407 | |
13408 | struct intel_transcoder_error_state { | |
ddf9c536 | 13409 | bool power_domain_on; |
63b66e5b CW |
13410 | enum transcoder cpu_transcoder; |
13411 | ||
13412 | u32 conf; | |
13413 | ||
13414 | u32 htotal; | |
13415 | u32 hblank; | |
13416 | u32 hsync; | |
13417 | u32 vtotal; | |
13418 | u32 vblank; | |
13419 | u32 vsync; | |
13420 | } transcoder[4]; | |
c4a1d9e4 CW |
13421 | }; |
13422 | ||
13423 | struct intel_display_error_state * | |
13424 | intel_display_capture_error_state(struct drm_device *dev) | |
13425 | { | |
fbee40df | 13426 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 13427 | struct intel_display_error_state *error; |
63b66e5b CW |
13428 | int transcoders[] = { |
13429 | TRANSCODER_A, | |
13430 | TRANSCODER_B, | |
13431 | TRANSCODER_C, | |
13432 | TRANSCODER_EDP, | |
13433 | }; | |
c4a1d9e4 CW |
13434 | int i; |
13435 | ||
63b66e5b CW |
13436 | if (INTEL_INFO(dev)->num_pipes == 0) |
13437 | return NULL; | |
13438 | ||
9d1cb914 | 13439 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
13440 | if (error == NULL) |
13441 | return NULL; | |
13442 | ||
190be112 | 13443 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
13444 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
13445 | ||
055e393f | 13446 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 13447 | error->pipe[i].power_domain_on = |
bfafe93a ID |
13448 | intel_display_power_enabled_unlocked(dev_priv, |
13449 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 13450 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
13451 | continue; |
13452 | ||
5efb3e28 VS |
13453 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
13454 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
13455 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
13456 | |
13457 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
13458 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 13459 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 13460 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
13461 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
13462 | } | |
ca291363 PZ |
13463 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
13464 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
13465 | if (INTEL_INFO(dev)->gen >= 4) { |
13466 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
13467 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
13468 | } | |
13469 | ||
c4a1d9e4 | 13470 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 13471 | |
3abfce77 | 13472 | if (HAS_GMCH_DISPLAY(dev)) |
f301b1e1 | 13473 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
13474 | } |
13475 | ||
13476 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
13477 | if (HAS_DDI(dev_priv->dev)) | |
13478 | error->num_transcoders++; /* Account for eDP. */ | |
13479 | ||
13480 | for (i = 0; i < error->num_transcoders; i++) { | |
13481 | enum transcoder cpu_transcoder = transcoders[i]; | |
13482 | ||
ddf9c536 | 13483 | error->transcoder[i].power_domain_on = |
bfafe93a | 13484 | intel_display_power_enabled_unlocked(dev_priv, |
38cc1daf | 13485 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 13486 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
13487 | continue; |
13488 | ||
63b66e5b CW |
13489 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
13490 | ||
13491 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
13492 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
13493 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
13494 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
13495 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
13496 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
13497 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
13498 | } |
13499 | ||
13500 | return error; | |
13501 | } | |
13502 | ||
edc3d884 MK |
13503 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
13504 | ||
c4a1d9e4 | 13505 | void |
edc3d884 | 13506 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
13507 | struct drm_device *dev, |
13508 | struct intel_display_error_state *error) | |
13509 | { | |
055e393f | 13510 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
13511 | int i; |
13512 | ||
63b66e5b CW |
13513 | if (!error) |
13514 | return; | |
13515 | ||
edc3d884 | 13516 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 13517 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 13518 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 13519 | error->power_well_driver); |
055e393f | 13520 | for_each_pipe(dev_priv, i) { |
edc3d884 | 13521 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 ID |
13522 | err_printf(m, " Power: %s\n", |
13523 | error->pipe[i].power_domain_on ? "on" : "off"); | |
edc3d884 | 13524 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 13525 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
13526 | |
13527 | err_printf(m, "Plane [%d]:\n", i); | |
13528 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
13529 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 13530 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
13531 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
13532 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 13533 | } |
4b71a570 | 13534 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 13535 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 13536 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
13537 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
13538 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
13539 | } |
13540 | ||
edc3d884 MK |
13541 | err_printf(m, "Cursor [%d]:\n", i); |
13542 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
13543 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
13544 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 13545 | } |
63b66e5b CW |
13546 | |
13547 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 13548 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 13549 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 ID |
13550 | err_printf(m, " Power: %s\n", |
13551 | error->transcoder[i].power_domain_on ? "on" : "off"); | |
63b66e5b CW |
13552 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
13553 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
13554 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
13555 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
13556 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
13557 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
13558 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
13559 | } | |
c4a1d9e4 | 13560 | } |
e2fcdaa9 VS |
13561 | |
13562 | void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file) | |
13563 | { | |
13564 | struct intel_crtc *crtc; | |
13565 | ||
13566 | for_each_intel_crtc(dev, crtc) { | |
13567 | struct intel_unpin_work *work; | |
13568 | unsigned long irqflags; | |
13569 | ||
13570 | spin_lock_irqsave(&dev->event_lock, irqflags); | |
13571 | ||
13572 | work = crtc->unpin_work; | |
13573 | ||
13574 | if (work && work->event && | |
13575 | work->event->base.file_priv == file) { | |
13576 | kfree(work->event); | |
13577 | work->event = NULL; | |
13578 | } | |
13579 | ||
13580 | spin_unlock_irqrestore(&dev->event_lock, irqflags); | |
13581 | } | |
13582 | } |