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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
760285e7 DH |
40 | #include <drm/drm_dp_helper.h> |
41 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
42 | #include <drm/drm_plane_helper.h> |
43 | #include <drm/drm_rect.h> | |
c0f372b3 | 44 | #include <linux/dma_remapping.h> |
79e53945 | 45 | |
465c120c MR |
46 | /* Primary plane formats supported by all gen */ |
47 | #define COMMON_PRIMARY_FORMATS \ | |
48 | DRM_FORMAT_C8, \ | |
49 | DRM_FORMAT_RGB565, \ | |
50 | DRM_FORMAT_XRGB8888, \ | |
51 | DRM_FORMAT_ARGB8888 | |
52 | ||
53 | /* Primary plane formats for gen <= 3 */ | |
54 | static const uint32_t intel_primary_formats_gen2[] = { | |
55 | COMMON_PRIMARY_FORMATS, | |
56 | DRM_FORMAT_XRGB1555, | |
57 | DRM_FORMAT_ARGB1555, | |
58 | }; | |
59 | ||
60 | /* Primary plane formats for gen >= 4 */ | |
61 | static const uint32_t intel_primary_formats_gen4[] = { | |
62 | COMMON_PRIMARY_FORMATS, \ | |
63 | DRM_FORMAT_XBGR8888, | |
64 | DRM_FORMAT_ABGR8888, | |
65 | DRM_FORMAT_XRGB2101010, | |
66 | DRM_FORMAT_ARGB2101010, | |
67 | DRM_FORMAT_XBGR2101010, | |
68 | DRM_FORMAT_ABGR2101010, | |
69 | }; | |
70 | ||
3d7d6510 MR |
71 | /* Cursor formats */ |
72 | static const uint32_t intel_cursor_formats[] = { | |
73 | DRM_FORMAT_ARGB8888, | |
74 | }; | |
75 | ||
ef9348c8 | 76 | #define DIV_ROUND_CLOSEST_ULL(ll, d) \ |
465c120c | 77 | ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; }) |
ef9348c8 | 78 | |
3dec0095 | 79 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
6b383a7f | 80 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 81 | |
f1f644dc JB |
82 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
83 | struct intel_crtc_config *pipe_config); | |
18442d08 VS |
84 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
85 | struct intel_crtc_config *pipe_config); | |
f1f644dc | 86 | |
e7457a9a DL |
87 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
88 | int x, int y, struct drm_framebuffer *old_fb); | |
eb1bfe80 JB |
89 | static int intel_framebuffer_init(struct drm_device *dev, |
90 | struct intel_framebuffer *ifb, | |
91 | struct drm_mode_fb_cmd2 *mode_cmd, | |
92 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
93 | static void intel_dp_set_m_n(struct intel_crtc *crtc); |
94 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); | |
95 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
29407aab DV |
96 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
97 | struct intel_link_m_n *m_n); | |
98 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); | |
229fca97 DV |
99 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
100 | static void intel_set_pipe_csc(struct drm_crtc *crtc); | |
bdd4b6a6 | 101 | static void vlv_prepare_pll(struct intel_crtc *crtc); |
e7457a9a | 102 | |
79e53945 | 103 | typedef struct { |
0206e353 | 104 | int min, max; |
79e53945 JB |
105 | } intel_range_t; |
106 | ||
107 | typedef struct { | |
0206e353 AJ |
108 | int dot_limit; |
109 | int p2_slow, p2_fast; | |
79e53945 JB |
110 | } intel_p2_t; |
111 | ||
d4906093 ML |
112 | typedef struct intel_limit intel_limit_t; |
113 | struct intel_limit { | |
0206e353 AJ |
114 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
115 | intel_p2_t p2; | |
d4906093 | 116 | }; |
79e53945 | 117 | |
d2acd215 DV |
118 | int |
119 | intel_pch_rawclk(struct drm_device *dev) | |
120 | { | |
121 | struct drm_i915_private *dev_priv = dev->dev_private; | |
122 | ||
123 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
124 | ||
125 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
126 | } | |
127 | ||
021357ac CW |
128 | static inline u32 /* units of 100MHz */ |
129 | intel_fdi_link_freq(struct drm_device *dev) | |
130 | { | |
8b99e68c CW |
131 | if (IS_GEN5(dev)) { |
132 | struct drm_i915_private *dev_priv = dev->dev_private; | |
133 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
134 | } else | |
135 | return 27; | |
021357ac CW |
136 | } |
137 | ||
5d536e28 | 138 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 139 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 140 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 141 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
142 | .m = { .min = 96, .max = 140 }, |
143 | .m1 = { .min = 18, .max = 26 }, | |
144 | .m2 = { .min = 6, .max = 16 }, | |
145 | .p = { .min = 4, .max = 128 }, | |
146 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
147 | .p2 = { .dot_limit = 165000, |
148 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
149 | }; |
150 | ||
5d536e28 DV |
151 | static const intel_limit_t intel_limits_i8xx_dvo = { |
152 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 153 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 154 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
155 | .m = { .min = 96, .max = 140 }, |
156 | .m1 = { .min = 18, .max = 26 }, | |
157 | .m2 = { .min = 6, .max = 16 }, | |
158 | .p = { .min = 4, .max = 128 }, | |
159 | .p1 = { .min = 2, .max = 33 }, | |
160 | .p2 = { .dot_limit = 165000, | |
161 | .p2_slow = 4, .p2_fast = 4 }, | |
162 | }; | |
163 | ||
e4b36699 | 164 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 165 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 166 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 167 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
168 | .m = { .min = 96, .max = 140 }, |
169 | .m1 = { .min = 18, .max = 26 }, | |
170 | .m2 = { .min = 6, .max = 16 }, | |
171 | .p = { .min = 4, .max = 128 }, | |
172 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
173 | .p2 = { .dot_limit = 165000, |
174 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 175 | }; |
273e27ca | 176 | |
e4b36699 | 177 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
178 | .dot = { .min = 20000, .max = 400000 }, |
179 | .vco = { .min = 1400000, .max = 2800000 }, | |
180 | .n = { .min = 1, .max = 6 }, | |
181 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
182 | .m1 = { .min = 8, .max = 18 }, |
183 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
184 | .p = { .min = 5, .max = 80 }, |
185 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
186 | .p2 = { .dot_limit = 200000, |
187 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
188 | }; |
189 | ||
190 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
191 | .dot = { .min = 20000, .max = 400000 }, |
192 | .vco = { .min = 1400000, .max = 2800000 }, | |
193 | .n = { .min = 1, .max = 6 }, | |
194 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
195 | .m1 = { .min = 8, .max = 18 }, |
196 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
197 | .p = { .min = 7, .max = 98 }, |
198 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
199 | .p2 = { .dot_limit = 112000, |
200 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
201 | }; |
202 | ||
273e27ca | 203 | |
e4b36699 | 204 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
205 | .dot = { .min = 25000, .max = 270000 }, |
206 | .vco = { .min = 1750000, .max = 3500000}, | |
207 | .n = { .min = 1, .max = 4 }, | |
208 | .m = { .min = 104, .max = 138 }, | |
209 | .m1 = { .min = 17, .max = 23 }, | |
210 | .m2 = { .min = 5, .max = 11 }, | |
211 | .p = { .min = 10, .max = 30 }, | |
212 | .p1 = { .min = 1, .max = 3}, | |
213 | .p2 = { .dot_limit = 270000, | |
214 | .p2_slow = 10, | |
215 | .p2_fast = 10 | |
044c7c41 | 216 | }, |
e4b36699 KP |
217 | }; |
218 | ||
219 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
220 | .dot = { .min = 22000, .max = 400000 }, |
221 | .vco = { .min = 1750000, .max = 3500000}, | |
222 | .n = { .min = 1, .max = 4 }, | |
223 | .m = { .min = 104, .max = 138 }, | |
224 | .m1 = { .min = 16, .max = 23 }, | |
225 | .m2 = { .min = 5, .max = 11 }, | |
226 | .p = { .min = 5, .max = 80 }, | |
227 | .p1 = { .min = 1, .max = 8}, | |
228 | .p2 = { .dot_limit = 165000, | |
229 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
230 | }; |
231 | ||
232 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
233 | .dot = { .min = 20000, .max = 115000 }, |
234 | .vco = { .min = 1750000, .max = 3500000 }, | |
235 | .n = { .min = 1, .max = 3 }, | |
236 | .m = { .min = 104, .max = 138 }, | |
237 | .m1 = { .min = 17, .max = 23 }, | |
238 | .m2 = { .min = 5, .max = 11 }, | |
239 | .p = { .min = 28, .max = 112 }, | |
240 | .p1 = { .min = 2, .max = 8 }, | |
241 | .p2 = { .dot_limit = 0, | |
242 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 243 | }, |
e4b36699 KP |
244 | }; |
245 | ||
246 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
247 | .dot = { .min = 80000, .max = 224000 }, |
248 | .vco = { .min = 1750000, .max = 3500000 }, | |
249 | .n = { .min = 1, .max = 3 }, | |
250 | .m = { .min = 104, .max = 138 }, | |
251 | .m1 = { .min = 17, .max = 23 }, | |
252 | .m2 = { .min = 5, .max = 11 }, | |
253 | .p = { .min = 14, .max = 42 }, | |
254 | .p1 = { .min = 2, .max = 6 }, | |
255 | .p2 = { .dot_limit = 0, | |
256 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 257 | }, |
e4b36699 KP |
258 | }; |
259 | ||
f2b115e6 | 260 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
261 | .dot = { .min = 20000, .max = 400000}, |
262 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 263 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
264 | .n = { .min = 3, .max = 6 }, |
265 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 266 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
267 | .m1 = { .min = 0, .max = 0 }, |
268 | .m2 = { .min = 0, .max = 254 }, | |
269 | .p = { .min = 5, .max = 80 }, | |
270 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
271 | .p2 = { .dot_limit = 200000, |
272 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
273 | }; |
274 | ||
f2b115e6 | 275 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
276 | .dot = { .min = 20000, .max = 400000 }, |
277 | .vco = { .min = 1700000, .max = 3500000 }, | |
278 | .n = { .min = 3, .max = 6 }, | |
279 | .m = { .min = 2, .max = 256 }, | |
280 | .m1 = { .min = 0, .max = 0 }, | |
281 | .m2 = { .min = 0, .max = 254 }, | |
282 | .p = { .min = 7, .max = 112 }, | |
283 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
284 | .p2 = { .dot_limit = 112000, |
285 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
286 | }; |
287 | ||
273e27ca EA |
288 | /* Ironlake / Sandybridge |
289 | * | |
290 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
291 | * the range value for them is (actual_value - 2). | |
292 | */ | |
b91ad0ec | 293 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
294 | .dot = { .min = 25000, .max = 350000 }, |
295 | .vco = { .min = 1760000, .max = 3510000 }, | |
296 | .n = { .min = 1, .max = 5 }, | |
297 | .m = { .min = 79, .max = 127 }, | |
298 | .m1 = { .min = 12, .max = 22 }, | |
299 | .m2 = { .min = 5, .max = 9 }, | |
300 | .p = { .min = 5, .max = 80 }, | |
301 | .p1 = { .min = 1, .max = 8 }, | |
302 | .p2 = { .dot_limit = 225000, | |
303 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
304 | }; |
305 | ||
b91ad0ec | 306 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
307 | .dot = { .min = 25000, .max = 350000 }, |
308 | .vco = { .min = 1760000, .max = 3510000 }, | |
309 | .n = { .min = 1, .max = 3 }, | |
310 | .m = { .min = 79, .max = 118 }, | |
311 | .m1 = { .min = 12, .max = 22 }, | |
312 | .m2 = { .min = 5, .max = 9 }, | |
313 | .p = { .min = 28, .max = 112 }, | |
314 | .p1 = { .min = 2, .max = 8 }, | |
315 | .p2 = { .dot_limit = 225000, | |
316 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
317 | }; |
318 | ||
319 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
320 | .dot = { .min = 25000, .max = 350000 }, |
321 | .vco = { .min = 1760000, .max = 3510000 }, | |
322 | .n = { .min = 1, .max = 3 }, | |
323 | .m = { .min = 79, .max = 127 }, | |
324 | .m1 = { .min = 12, .max = 22 }, | |
325 | .m2 = { .min = 5, .max = 9 }, | |
326 | .p = { .min = 14, .max = 56 }, | |
327 | .p1 = { .min = 2, .max = 8 }, | |
328 | .p2 = { .dot_limit = 225000, | |
329 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
330 | }; |
331 | ||
273e27ca | 332 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 333 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
334 | .dot = { .min = 25000, .max = 350000 }, |
335 | .vco = { .min = 1760000, .max = 3510000 }, | |
336 | .n = { .min = 1, .max = 2 }, | |
337 | .m = { .min = 79, .max = 126 }, | |
338 | .m1 = { .min = 12, .max = 22 }, | |
339 | .m2 = { .min = 5, .max = 9 }, | |
340 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 341 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
342 | .p2 = { .dot_limit = 225000, |
343 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
344 | }; |
345 | ||
346 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
347 | .dot = { .min = 25000, .max = 350000 }, |
348 | .vco = { .min = 1760000, .max = 3510000 }, | |
349 | .n = { .min = 1, .max = 3 }, | |
350 | .m = { .min = 79, .max = 126 }, | |
351 | .m1 = { .min = 12, .max = 22 }, | |
352 | .m2 = { .min = 5, .max = 9 }, | |
353 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 354 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
355 | .p2 = { .dot_limit = 225000, |
356 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
357 | }; |
358 | ||
dc730512 | 359 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
360 | /* |
361 | * These are the data rate limits (measured in fast clocks) | |
362 | * since those are the strictest limits we have. The fast | |
363 | * clock and actual rate limits are more relaxed, so checking | |
364 | * them would make no difference. | |
365 | */ | |
366 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 367 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 368 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
369 | .m1 = { .min = 2, .max = 3 }, |
370 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 371 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 372 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
373 | }; |
374 | ||
ef9348c8 CML |
375 | static const intel_limit_t intel_limits_chv = { |
376 | /* | |
377 | * These are the data rate limits (measured in fast clocks) | |
378 | * since those are the strictest limits we have. The fast | |
379 | * clock and actual rate limits are more relaxed, so checking | |
380 | * them would make no difference. | |
381 | */ | |
382 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
383 | .vco = { .min = 4860000, .max = 6700000 }, | |
384 | .n = { .min = 1, .max = 1 }, | |
385 | .m1 = { .min = 2, .max = 2 }, | |
386 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
387 | .p1 = { .min = 2, .max = 4 }, | |
388 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
389 | }; | |
390 | ||
6b4bf1c4 VS |
391 | static void vlv_clock(int refclk, intel_clock_t *clock) |
392 | { | |
393 | clock->m = clock->m1 * clock->m2; | |
394 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
395 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
396 | return; | |
fb03ac01 VS |
397 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
398 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
6b4bf1c4 VS |
399 | } |
400 | ||
e0638cdf PZ |
401 | /** |
402 | * Returns whether any output on the specified pipe is of the specified type | |
403 | */ | |
404 | static bool intel_pipe_has_type(struct drm_crtc *crtc, int type) | |
405 | { | |
406 | struct drm_device *dev = crtc->dev; | |
407 | struct intel_encoder *encoder; | |
408 | ||
409 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
410 | if (encoder->type == type) | |
411 | return true; | |
412 | ||
413 | return false; | |
414 | } | |
415 | ||
1b894b59 CW |
416 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
417 | int refclk) | |
2c07245f | 418 | { |
b91ad0ec | 419 | struct drm_device *dev = crtc->dev; |
2c07245f | 420 | const intel_limit_t *limit; |
b91ad0ec ZW |
421 | |
422 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 423 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 424 | if (refclk == 100000) |
b91ad0ec ZW |
425 | limit = &intel_limits_ironlake_dual_lvds_100m; |
426 | else | |
427 | limit = &intel_limits_ironlake_dual_lvds; | |
428 | } else { | |
1b894b59 | 429 | if (refclk == 100000) |
b91ad0ec ZW |
430 | limit = &intel_limits_ironlake_single_lvds_100m; |
431 | else | |
432 | limit = &intel_limits_ironlake_single_lvds; | |
433 | } | |
c6bb3538 | 434 | } else |
b91ad0ec | 435 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
436 | |
437 | return limit; | |
438 | } | |
439 | ||
044c7c41 ML |
440 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
441 | { | |
442 | struct drm_device *dev = crtc->dev; | |
044c7c41 ML |
443 | const intel_limit_t *limit; |
444 | ||
445 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 446 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 447 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 448 | else |
e4b36699 | 449 | limit = &intel_limits_g4x_single_channel_lvds; |
044c7c41 ML |
450 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
451 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 452 | limit = &intel_limits_g4x_hdmi; |
044c7c41 | 453 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 454 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 455 | } else /* The option is for other outputs */ |
e4b36699 | 456 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
457 | |
458 | return limit; | |
459 | } | |
460 | ||
1b894b59 | 461 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
79e53945 JB |
462 | { |
463 | struct drm_device *dev = crtc->dev; | |
464 | const intel_limit_t *limit; | |
465 | ||
bad720ff | 466 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 467 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 468 | else if (IS_G4X(dev)) { |
044c7c41 | 469 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 470 | } else if (IS_PINEVIEW(dev)) { |
2177832f | 471 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 472 | limit = &intel_limits_pineview_lvds; |
2177832f | 473 | else |
f2b115e6 | 474 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
475 | } else if (IS_CHERRYVIEW(dev)) { |
476 | limit = &intel_limits_chv; | |
a0c4da24 | 477 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 478 | limit = &intel_limits_vlv; |
a6c45cf0 CW |
479 | } else if (!IS_GEN2(dev)) { |
480 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
481 | limit = &intel_limits_i9xx_lvds; | |
482 | else | |
483 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 JB |
484 | } else { |
485 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 486 | limit = &intel_limits_i8xx_lvds; |
5d536e28 | 487 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO)) |
e4b36699 | 488 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
489 | else |
490 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
491 | } |
492 | return limit; | |
493 | } | |
494 | ||
f2b115e6 AJ |
495 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
496 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 497 | { |
2177832f SL |
498 | clock->m = clock->m2 + 2; |
499 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
500 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
501 | return; | |
fb03ac01 VS |
502 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
503 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
2177832f SL |
504 | } |
505 | ||
7429e9d4 DV |
506 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
507 | { | |
508 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
509 | } | |
510 | ||
ac58c3f0 | 511 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
2177832f | 512 | { |
7429e9d4 | 513 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 514 | clock->p = clock->p1 * clock->p2; |
ed5ca77e VS |
515 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
516 | return; | |
fb03ac01 VS |
517 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
518 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
79e53945 JB |
519 | } |
520 | ||
ef9348c8 CML |
521 | static void chv_clock(int refclk, intel_clock_t *clock) |
522 | { | |
523 | clock->m = clock->m1 * clock->m2; | |
524 | clock->p = clock->p1 * clock->p2; | |
525 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
526 | return; | |
527 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, | |
528 | clock->n << 22); | |
529 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
530 | } | |
531 | ||
7c04d1d9 | 532 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
533 | /** |
534 | * Returns whether the given set of divisors are valid for a given refclk with | |
535 | * the given connectors. | |
536 | */ | |
537 | ||
1b894b59 CW |
538 | static bool intel_PLL_is_valid(struct drm_device *dev, |
539 | const intel_limit_t *limit, | |
540 | const intel_clock_t *clock) | |
79e53945 | 541 | { |
f01b7962 VS |
542 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
543 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 544 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 545 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 546 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 547 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 548 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 549 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 VS |
550 | |
551 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev)) | |
552 | if (clock->m1 <= clock->m2) | |
553 | INTELPllInvalid("m1 <= m2\n"); | |
554 | ||
555 | if (!IS_VALLEYVIEW(dev)) { | |
556 | if (clock->p < limit->p.min || limit->p.max < clock->p) | |
557 | INTELPllInvalid("p out of range\n"); | |
558 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
559 | INTELPllInvalid("m out of range\n"); | |
560 | } | |
561 | ||
79e53945 | 562 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 563 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
564 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
565 | * connector, etc., rather than just a single range. | |
566 | */ | |
567 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 568 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
569 | |
570 | return true; | |
571 | } | |
572 | ||
d4906093 | 573 | static bool |
ee9300bb | 574 | i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
cec2f356 SP |
575 | int target, int refclk, intel_clock_t *match_clock, |
576 | intel_clock_t *best_clock) | |
79e53945 JB |
577 | { |
578 | struct drm_device *dev = crtc->dev; | |
79e53945 | 579 | intel_clock_t clock; |
79e53945 JB |
580 | int err = target; |
581 | ||
a210b028 | 582 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 583 | /* |
a210b028 DV |
584 | * For LVDS just rely on its current settings for dual-channel. |
585 | * We haven't figured out how to reliably set up different | |
586 | * single/dual channel state, if we even can. | |
79e53945 | 587 | */ |
1974cad0 | 588 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
589 | clock.p2 = limit->p2.p2_fast; |
590 | else | |
591 | clock.p2 = limit->p2.p2_slow; | |
592 | } else { | |
593 | if (target < limit->p2.dot_limit) | |
594 | clock.p2 = limit->p2.p2_slow; | |
595 | else | |
596 | clock.p2 = limit->p2.p2_fast; | |
597 | } | |
598 | ||
0206e353 | 599 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 600 | |
42158660 ZY |
601 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
602 | clock.m1++) { | |
603 | for (clock.m2 = limit->m2.min; | |
604 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 605 | if (clock.m2 >= clock.m1) |
42158660 ZY |
606 | break; |
607 | for (clock.n = limit->n.min; | |
608 | clock.n <= limit->n.max; clock.n++) { | |
609 | for (clock.p1 = limit->p1.min; | |
610 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
611 | int this_err; |
612 | ||
ac58c3f0 DV |
613 | i9xx_clock(refclk, &clock); |
614 | if (!intel_PLL_is_valid(dev, limit, | |
615 | &clock)) | |
616 | continue; | |
617 | if (match_clock && | |
618 | clock.p != match_clock->p) | |
619 | continue; | |
620 | ||
621 | this_err = abs(clock.dot - target); | |
622 | if (this_err < err) { | |
623 | *best_clock = clock; | |
624 | err = this_err; | |
625 | } | |
626 | } | |
627 | } | |
628 | } | |
629 | } | |
630 | ||
631 | return (err != target); | |
632 | } | |
633 | ||
634 | static bool | |
ee9300bb DV |
635 | pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
636 | int target, int refclk, intel_clock_t *match_clock, | |
637 | intel_clock_t *best_clock) | |
79e53945 JB |
638 | { |
639 | struct drm_device *dev = crtc->dev; | |
79e53945 | 640 | intel_clock_t clock; |
79e53945 JB |
641 | int err = target; |
642 | ||
a210b028 | 643 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 644 | /* |
a210b028 DV |
645 | * For LVDS just rely on its current settings for dual-channel. |
646 | * We haven't figured out how to reliably set up different | |
647 | * single/dual channel state, if we even can. | |
79e53945 | 648 | */ |
1974cad0 | 649 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
650 | clock.p2 = limit->p2.p2_fast; |
651 | else | |
652 | clock.p2 = limit->p2.p2_slow; | |
653 | } else { | |
654 | if (target < limit->p2.dot_limit) | |
655 | clock.p2 = limit->p2.p2_slow; | |
656 | else | |
657 | clock.p2 = limit->p2.p2_fast; | |
658 | } | |
659 | ||
0206e353 | 660 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 661 | |
42158660 ZY |
662 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
663 | clock.m1++) { | |
664 | for (clock.m2 = limit->m2.min; | |
665 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
666 | for (clock.n = limit->n.min; |
667 | clock.n <= limit->n.max; clock.n++) { | |
668 | for (clock.p1 = limit->p1.min; | |
669 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
670 | int this_err; |
671 | ||
ac58c3f0 | 672 | pineview_clock(refclk, &clock); |
1b894b59 CW |
673 | if (!intel_PLL_is_valid(dev, limit, |
674 | &clock)) | |
79e53945 | 675 | continue; |
cec2f356 SP |
676 | if (match_clock && |
677 | clock.p != match_clock->p) | |
678 | continue; | |
79e53945 JB |
679 | |
680 | this_err = abs(clock.dot - target); | |
681 | if (this_err < err) { | |
682 | *best_clock = clock; | |
683 | err = this_err; | |
684 | } | |
685 | } | |
686 | } | |
687 | } | |
688 | } | |
689 | ||
690 | return (err != target); | |
691 | } | |
692 | ||
d4906093 | 693 | static bool |
ee9300bb DV |
694 | g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
695 | int target, int refclk, intel_clock_t *match_clock, | |
696 | intel_clock_t *best_clock) | |
d4906093 ML |
697 | { |
698 | struct drm_device *dev = crtc->dev; | |
d4906093 ML |
699 | intel_clock_t clock; |
700 | int max_n; | |
701 | bool found; | |
6ba770dc AJ |
702 | /* approximately equals target * 0.00585 */ |
703 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
704 | found = false; |
705 | ||
706 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 707 | if (intel_is_dual_link_lvds(dev)) |
d4906093 ML |
708 | clock.p2 = limit->p2.p2_fast; |
709 | else | |
710 | clock.p2 = limit->p2.p2_slow; | |
711 | } else { | |
712 | if (target < limit->p2.dot_limit) | |
713 | clock.p2 = limit->p2.p2_slow; | |
714 | else | |
715 | clock.p2 = limit->p2.p2_fast; | |
716 | } | |
717 | ||
718 | memset(best_clock, 0, sizeof(*best_clock)); | |
719 | max_n = limit->n.max; | |
f77f13e2 | 720 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 721 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 722 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
723 | for (clock.m1 = limit->m1.max; |
724 | clock.m1 >= limit->m1.min; clock.m1--) { | |
725 | for (clock.m2 = limit->m2.max; | |
726 | clock.m2 >= limit->m2.min; clock.m2--) { | |
727 | for (clock.p1 = limit->p1.max; | |
728 | clock.p1 >= limit->p1.min; clock.p1--) { | |
729 | int this_err; | |
730 | ||
ac58c3f0 | 731 | i9xx_clock(refclk, &clock); |
1b894b59 CW |
732 | if (!intel_PLL_is_valid(dev, limit, |
733 | &clock)) | |
d4906093 | 734 | continue; |
1b894b59 CW |
735 | |
736 | this_err = abs(clock.dot - target); | |
d4906093 ML |
737 | if (this_err < err_most) { |
738 | *best_clock = clock; | |
739 | err_most = this_err; | |
740 | max_n = clock.n; | |
741 | found = true; | |
742 | } | |
743 | } | |
744 | } | |
745 | } | |
746 | } | |
2c07245f ZW |
747 | return found; |
748 | } | |
749 | ||
a0c4da24 | 750 | static bool |
ee9300bb DV |
751 | vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
752 | int target, int refclk, intel_clock_t *match_clock, | |
753 | intel_clock_t *best_clock) | |
a0c4da24 | 754 | { |
f01b7962 | 755 | struct drm_device *dev = crtc->dev; |
6b4bf1c4 | 756 | intel_clock_t clock; |
69e4f900 | 757 | unsigned int bestppm = 1000000; |
27e639bf VS |
758 | /* min update 19.2 MHz */ |
759 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 760 | bool found = false; |
a0c4da24 | 761 | |
6b4bf1c4 VS |
762 | target *= 5; /* fast clock */ |
763 | ||
764 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
765 | |
766 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 767 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 768 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 769 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 770 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 771 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 772 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 773 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
69e4f900 VS |
774 | unsigned int ppm, diff; |
775 | ||
6b4bf1c4 VS |
776 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
777 | refclk * clock.m1); | |
778 | ||
779 | vlv_clock(refclk, &clock); | |
43b0ac53 | 780 | |
f01b7962 VS |
781 | if (!intel_PLL_is_valid(dev, limit, |
782 | &clock)) | |
43b0ac53 VS |
783 | continue; |
784 | ||
6b4bf1c4 VS |
785 | diff = abs(clock.dot - target); |
786 | ppm = div_u64(1000000ULL * diff, target); | |
787 | ||
788 | if (ppm < 100 && clock.p > best_clock->p) { | |
43b0ac53 | 789 | bestppm = 0; |
6b4bf1c4 | 790 | *best_clock = clock; |
49e497ef | 791 | found = true; |
43b0ac53 | 792 | } |
6b4bf1c4 | 793 | |
c686122c | 794 | if (bestppm >= 10 && ppm < bestppm - 10) { |
69e4f900 | 795 | bestppm = ppm; |
6b4bf1c4 | 796 | *best_clock = clock; |
49e497ef | 797 | found = true; |
a0c4da24 JB |
798 | } |
799 | } | |
800 | } | |
801 | } | |
802 | } | |
a0c4da24 | 803 | |
49e497ef | 804 | return found; |
a0c4da24 | 805 | } |
a4fc5ed6 | 806 | |
ef9348c8 CML |
807 | static bool |
808 | chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, | |
809 | int target, int refclk, intel_clock_t *match_clock, | |
810 | intel_clock_t *best_clock) | |
811 | { | |
812 | struct drm_device *dev = crtc->dev; | |
813 | intel_clock_t clock; | |
814 | uint64_t m2; | |
815 | int found = false; | |
816 | ||
817 | memset(best_clock, 0, sizeof(*best_clock)); | |
818 | ||
819 | /* | |
820 | * Based on hardware doc, the n always set to 1, and m1 always | |
821 | * set to 2. If requires to support 200Mhz refclk, we need to | |
822 | * revisit this because n may not 1 anymore. | |
823 | */ | |
824 | clock.n = 1, clock.m1 = 2; | |
825 | target *= 5; /* fast clock */ | |
826 | ||
827 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
828 | for (clock.p2 = limit->p2.p2_fast; | |
829 | clock.p2 >= limit->p2.p2_slow; | |
830 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
831 | ||
832 | clock.p = clock.p1 * clock.p2; | |
833 | ||
834 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
835 | clock.n) << 22, refclk * clock.m1); | |
836 | ||
837 | if (m2 > INT_MAX/clock.m1) | |
838 | continue; | |
839 | ||
840 | clock.m2 = m2; | |
841 | ||
842 | chv_clock(refclk, &clock); | |
843 | ||
844 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
845 | continue; | |
846 | ||
847 | /* based on hardware requirement, prefer bigger p | |
848 | */ | |
849 | if (clock.p > best_clock->p) { | |
850 | *best_clock = clock; | |
851 | found = true; | |
852 | } | |
853 | } | |
854 | } | |
855 | ||
856 | return found; | |
857 | } | |
858 | ||
20ddf665 VS |
859 | bool intel_crtc_active(struct drm_crtc *crtc) |
860 | { | |
861 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
862 | ||
863 | /* Be paranoid as we can arrive here with only partial | |
864 | * state retrieved from the hardware during setup. | |
865 | * | |
241bfc38 | 866 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
867 | * as Haswell has gained clock readout/fastboot support. |
868 | * | |
66e514c1 | 869 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 VS |
870 | * properly reconstruct framebuffers. |
871 | */ | |
f4510a27 | 872 | return intel_crtc->active && crtc->primary->fb && |
241bfc38 | 873 | intel_crtc->config.adjusted_mode.crtc_clock; |
20ddf665 VS |
874 | } |
875 | ||
a5c961d1 PZ |
876 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
877 | enum pipe pipe) | |
878 | { | |
879 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
880 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
881 | ||
3b117c8f | 882 | return intel_crtc->config.cpu_transcoder; |
a5c961d1 PZ |
883 | } |
884 | ||
57e22f4a | 885 | static void g4x_wait_for_vblank(struct drm_device *dev, int pipe) |
a928d536 PZ |
886 | { |
887 | struct drm_i915_private *dev_priv = dev->dev_private; | |
57e22f4a | 888 | u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe); |
a928d536 PZ |
889 | |
890 | frame = I915_READ(frame_reg); | |
891 | ||
892 | if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) | |
93937071 | 893 | WARN(1, "vblank wait timed out\n"); |
a928d536 PZ |
894 | } |
895 | ||
9d0498a2 JB |
896 | /** |
897 | * intel_wait_for_vblank - wait for vblank on a given pipe | |
898 | * @dev: drm device | |
899 | * @pipe: pipe to wait for | |
900 | * | |
901 | * Wait for vblank to occur on a given pipe. Needed for various bits of | |
902 | * mode setting code. | |
903 | */ | |
904 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
79e53945 | 905 | { |
9d0498a2 | 906 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 907 | int pipestat_reg = PIPESTAT(pipe); |
9d0498a2 | 908 | |
57e22f4a VS |
909 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
910 | g4x_wait_for_vblank(dev, pipe); | |
a928d536 PZ |
911 | return; |
912 | } | |
913 | ||
300387c0 CW |
914 | /* Clear existing vblank status. Note this will clear any other |
915 | * sticky status fields as well. | |
916 | * | |
917 | * This races with i915_driver_irq_handler() with the result | |
918 | * that either function could miss a vblank event. Here it is not | |
919 | * fatal, as we will either wait upon the next vblank interrupt or | |
920 | * timeout. Generally speaking intel_wait_for_vblank() is only | |
921 | * called during modeset at which time the GPU should be idle and | |
922 | * should *not* be performing page flips and thus not waiting on | |
923 | * vblanks... | |
924 | * Currently, the result of us stealing a vblank from the irq | |
925 | * handler is that a single frame will be skipped during swapbuffers. | |
926 | */ | |
927 | I915_WRITE(pipestat_reg, | |
928 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); | |
929 | ||
9d0498a2 | 930 | /* Wait for vblank interrupt bit to set */ |
481b6af3 CW |
931 | if (wait_for(I915_READ(pipestat_reg) & |
932 | PIPE_VBLANK_INTERRUPT_STATUS, | |
933 | 50)) | |
9d0498a2 JB |
934 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
935 | } | |
936 | ||
fbf49ea2 VS |
937 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
938 | { | |
939 | struct drm_i915_private *dev_priv = dev->dev_private; | |
940 | u32 reg = PIPEDSL(pipe); | |
941 | u32 line1, line2; | |
942 | u32 line_mask; | |
943 | ||
944 | if (IS_GEN2(dev)) | |
945 | line_mask = DSL_LINEMASK_GEN2; | |
946 | else | |
947 | line_mask = DSL_LINEMASK_GEN3; | |
948 | ||
949 | line1 = I915_READ(reg) & line_mask; | |
950 | mdelay(5); | |
951 | line2 = I915_READ(reg) & line_mask; | |
952 | ||
953 | return line1 == line2; | |
954 | } | |
955 | ||
ab7ad7f6 KP |
956 | /* |
957 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
9d0498a2 JB |
958 | * @dev: drm device |
959 | * @pipe: pipe to wait for | |
960 | * | |
961 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
962 | * spinning on the vblank interrupt status bit, since we won't actually | |
963 | * see an interrupt when the pipe is disabled. | |
964 | * | |
ab7ad7f6 KP |
965 | * On Gen4 and above: |
966 | * wait for the pipe register state bit to turn off | |
967 | * | |
968 | * Otherwise: | |
969 | * wait for the display line value to settle (it usually | |
970 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 971 | * |
9d0498a2 | 972 | */ |
58e10eb9 | 973 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
9d0498a2 JB |
974 | { |
975 | struct drm_i915_private *dev_priv = dev->dev_private; | |
702e7a56 PZ |
976 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
977 | pipe); | |
ab7ad7f6 KP |
978 | |
979 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 980 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
981 | |
982 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
983 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
984 | 100)) | |
284637d9 | 985 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 986 | } else { |
ab7ad7f6 | 987 | /* Wait for the display line to settle */ |
fbf49ea2 | 988 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 989 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 990 | } |
79e53945 JB |
991 | } |
992 | ||
b0ea7d37 DL |
993 | /* |
994 | * ibx_digital_port_connected - is the specified port connected? | |
995 | * @dev_priv: i915 private structure | |
996 | * @port: the port to test | |
997 | * | |
998 | * Returns true if @port is connected, false otherwise. | |
999 | */ | |
1000 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, | |
1001 | struct intel_digital_port *port) | |
1002 | { | |
1003 | u32 bit; | |
1004 | ||
c36346e3 | 1005 | if (HAS_PCH_IBX(dev_priv->dev)) { |
eba905b2 | 1006 | switch (port->port) { |
c36346e3 DL |
1007 | case PORT_B: |
1008 | bit = SDE_PORTB_HOTPLUG; | |
1009 | break; | |
1010 | case PORT_C: | |
1011 | bit = SDE_PORTC_HOTPLUG; | |
1012 | break; | |
1013 | case PORT_D: | |
1014 | bit = SDE_PORTD_HOTPLUG; | |
1015 | break; | |
1016 | default: | |
1017 | return true; | |
1018 | } | |
1019 | } else { | |
eba905b2 | 1020 | switch (port->port) { |
c36346e3 DL |
1021 | case PORT_B: |
1022 | bit = SDE_PORTB_HOTPLUG_CPT; | |
1023 | break; | |
1024 | case PORT_C: | |
1025 | bit = SDE_PORTC_HOTPLUG_CPT; | |
1026 | break; | |
1027 | case PORT_D: | |
1028 | bit = SDE_PORTD_HOTPLUG_CPT; | |
1029 | break; | |
1030 | default: | |
1031 | return true; | |
1032 | } | |
b0ea7d37 DL |
1033 | } |
1034 | ||
1035 | return I915_READ(SDEISR) & bit; | |
1036 | } | |
1037 | ||
b24e7179 JB |
1038 | static const char *state_string(bool enabled) |
1039 | { | |
1040 | return enabled ? "on" : "off"; | |
1041 | } | |
1042 | ||
1043 | /* Only for pre-ILK configs */ | |
55607e8a DV |
1044 | void assert_pll(struct drm_i915_private *dev_priv, |
1045 | enum pipe pipe, bool state) | |
b24e7179 JB |
1046 | { |
1047 | int reg; | |
1048 | u32 val; | |
1049 | bool cur_state; | |
1050 | ||
1051 | reg = DPLL(pipe); | |
1052 | val = I915_READ(reg); | |
1053 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
1054 | WARN(cur_state != state, | |
1055 | "PLL state assertion failure (expected %s, current %s)\n", | |
1056 | state_string(state), state_string(cur_state)); | |
1057 | } | |
b24e7179 | 1058 | |
23538ef1 JN |
1059 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1060 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1061 | { | |
1062 | u32 val; | |
1063 | bool cur_state; | |
1064 | ||
1065 | mutex_lock(&dev_priv->dpio_lock); | |
1066 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
1067 | mutex_unlock(&dev_priv->dpio_lock); | |
1068 | ||
1069 | cur_state = val & DSI_PLL_VCO_EN; | |
1070 | WARN(cur_state != state, | |
1071 | "DSI PLL state assertion failure (expected %s, current %s)\n", | |
1072 | state_string(state), state_string(cur_state)); | |
1073 | } | |
1074 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1075 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1076 | ||
55607e8a | 1077 | struct intel_shared_dpll * |
e2b78267 DV |
1078 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1079 | { | |
1080 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1081 | ||
a43f6e0f | 1082 | if (crtc->config.shared_dpll < 0) |
e2b78267 DV |
1083 | return NULL; |
1084 | ||
a43f6e0f | 1085 | return &dev_priv->shared_dplls[crtc->config.shared_dpll]; |
e2b78267 DV |
1086 | } |
1087 | ||
040484af | 1088 | /* For ILK+ */ |
55607e8a DV |
1089 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1090 | struct intel_shared_dpll *pll, | |
1091 | bool state) | |
040484af | 1092 | { |
040484af | 1093 | bool cur_state; |
5358901f | 1094 | struct intel_dpll_hw_state hw_state; |
040484af | 1095 | |
9d82aa17 ED |
1096 | if (HAS_PCH_LPT(dev_priv->dev)) { |
1097 | DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n"); | |
1098 | return; | |
1099 | } | |
1100 | ||
92b27b08 | 1101 | if (WARN (!pll, |
46edb027 | 1102 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 1103 | return; |
ee7b9f93 | 1104 | |
5358901f | 1105 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
92b27b08 | 1106 | WARN(cur_state != state, |
5358901f DV |
1107 | "%s assertion failure (expected %s, current %s)\n", |
1108 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 1109 | } |
040484af JB |
1110 | |
1111 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1112 | enum pipe pipe, bool state) | |
1113 | { | |
1114 | int reg; | |
1115 | u32 val; | |
1116 | bool cur_state; | |
ad80a810 PZ |
1117 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1118 | pipe); | |
040484af | 1119 | |
affa9354 PZ |
1120 | if (HAS_DDI(dev_priv->dev)) { |
1121 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 1122 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 1123 | val = I915_READ(reg); |
ad80a810 | 1124 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
1125 | } else { |
1126 | reg = FDI_TX_CTL(pipe); | |
1127 | val = I915_READ(reg); | |
1128 | cur_state = !!(val & FDI_TX_ENABLE); | |
1129 | } | |
040484af JB |
1130 | WARN(cur_state != state, |
1131 | "FDI TX state assertion failure (expected %s, current %s)\n", | |
1132 | state_string(state), state_string(cur_state)); | |
1133 | } | |
1134 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1135 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1136 | ||
1137 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1138 | enum pipe pipe, bool state) | |
1139 | { | |
1140 | int reg; | |
1141 | u32 val; | |
1142 | bool cur_state; | |
1143 | ||
d63fa0dc PZ |
1144 | reg = FDI_RX_CTL(pipe); |
1145 | val = I915_READ(reg); | |
1146 | cur_state = !!(val & FDI_RX_ENABLE); | |
040484af JB |
1147 | WARN(cur_state != state, |
1148 | "FDI RX state assertion failure (expected %s, current %s)\n", | |
1149 | state_string(state), state_string(cur_state)); | |
1150 | } | |
1151 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1152 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1153 | ||
1154 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1155 | enum pipe pipe) | |
1156 | { | |
1157 | int reg; | |
1158 | u32 val; | |
1159 | ||
1160 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1161 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1162 | return; |
1163 | ||
bf507ef7 | 1164 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1165 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1166 | return; |
1167 | ||
040484af JB |
1168 | reg = FDI_TX_CTL(pipe); |
1169 | val = I915_READ(reg); | |
1170 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); | |
1171 | } | |
1172 | ||
55607e8a DV |
1173 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1174 | enum pipe pipe, bool state) | |
040484af JB |
1175 | { |
1176 | int reg; | |
1177 | u32 val; | |
55607e8a | 1178 | bool cur_state; |
040484af JB |
1179 | |
1180 | reg = FDI_RX_CTL(pipe); | |
1181 | val = I915_READ(reg); | |
55607e8a DV |
1182 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
1183 | WARN(cur_state != state, | |
1184 | "FDI RX PLL assertion failure (expected %s, current %s)\n", | |
1185 | state_string(state), state_string(cur_state)); | |
040484af JB |
1186 | } |
1187 | ||
ea0760cf JB |
1188 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1189 | enum pipe pipe) | |
1190 | { | |
1191 | int pp_reg, lvds_reg; | |
1192 | u32 val; | |
1193 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1194 | bool locked = true; |
ea0760cf JB |
1195 | |
1196 | if (HAS_PCH_SPLIT(dev_priv->dev)) { | |
1197 | pp_reg = PCH_PP_CONTROL; | |
1198 | lvds_reg = PCH_LVDS; | |
1199 | } else { | |
1200 | pp_reg = PP_CONTROL; | |
1201 | lvds_reg = LVDS; | |
1202 | } | |
1203 | ||
1204 | val = I915_READ(pp_reg); | |
1205 | if (!(val & PANEL_POWER_ON) || | |
1206 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) | |
1207 | locked = false; | |
1208 | ||
1209 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) | |
1210 | panel_pipe = PIPE_B; | |
1211 | ||
1212 | WARN(panel_pipe == pipe && locked, | |
1213 | "panel assertion failure, pipe %c regs locked\n", | |
9db4a9c7 | 1214 | pipe_name(pipe)); |
ea0760cf JB |
1215 | } |
1216 | ||
93ce0ba6 JN |
1217 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1218 | enum pipe pipe, bool state) | |
1219 | { | |
1220 | struct drm_device *dev = dev_priv->dev; | |
1221 | bool cur_state; | |
1222 | ||
d9d82081 | 1223 | if (IS_845G(dev) || IS_I865G(dev)) |
93ce0ba6 | 1224 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; |
d9d82081 | 1225 | else |
5efb3e28 | 1226 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 JN |
1227 | |
1228 | WARN(cur_state != state, | |
1229 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", | |
1230 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1231 | } | |
1232 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1233 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1234 | ||
b840d907 JB |
1235 | void assert_pipe(struct drm_i915_private *dev_priv, |
1236 | enum pipe pipe, bool state) | |
b24e7179 JB |
1237 | { |
1238 | int reg; | |
1239 | u32 val; | |
63d7bbe9 | 1240 | bool cur_state; |
702e7a56 PZ |
1241 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1242 | pipe); | |
b24e7179 | 1243 | |
8e636784 DV |
1244 | /* if we need the pipe A quirk it must be always on */ |
1245 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
1246 | state = true; | |
1247 | ||
da7e29bd | 1248 | if (!intel_display_power_enabled(dev_priv, |
b97186f0 | 1249 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
69310161 PZ |
1250 | cur_state = false; |
1251 | } else { | |
1252 | reg = PIPECONF(cpu_transcoder); | |
1253 | val = I915_READ(reg); | |
1254 | cur_state = !!(val & PIPECONF_ENABLE); | |
1255 | } | |
1256 | ||
63d7bbe9 JB |
1257 | WARN(cur_state != state, |
1258 | "pipe %c assertion failure (expected %s, current %s)\n", | |
9db4a9c7 | 1259 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1260 | } |
1261 | ||
931872fc CW |
1262 | static void assert_plane(struct drm_i915_private *dev_priv, |
1263 | enum plane plane, bool state) | |
b24e7179 JB |
1264 | { |
1265 | int reg; | |
1266 | u32 val; | |
931872fc | 1267 | bool cur_state; |
b24e7179 JB |
1268 | |
1269 | reg = DSPCNTR(plane); | |
1270 | val = I915_READ(reg); | |
931872fc CW |
1271 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1272 | WARN(cur_state != state, | |
1273 | "plane %c assertion failure (expected %s, current %s)\n", | |
1274 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1275 | } |
1276 | ||
931872fc CW |
1277 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1278 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1279 | ||
b24e7179 JB |
1280 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1281 | enum pipe pipe) | |
1282 | { | |
653e1026 | 1283 | struct drm_device *dev = dev_priv->dev; |
b24e7179 JB |
1284 | int reg, i; |
1285 | u32 val; | |
1286 | int cur_pipe; | |
1287 | ||
653e1026 VS |
1288 | /* Primary planes are fixed to pipes on gen4+ */ |
1289 | if (INTEL_INFO(dev)->gen >= 4) { | |
28c05794 AJ |
1290 | reg = DSPCNTR(pipe); |
1291 | val = I915_READ(reg); | |
83f26f16 | 1292 | WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1293 | "plane %c assertion failure, should be disabled but not\n", |
1294 | plane_name(pipe)); | |
19ec1358 | 1295 | return; |
28c05794 | 1296 | } |
19ec1358 | 1297 | |
b24e7179 | 1298 | /* Need to check both planes against the pipe */ |
08e2a7de | 1299 | for_each_pipe(i) { |
b24e7179 JB |
1300 | reg = DSPCNTR(i); |
1301 | val = I915_READ(reg); | |
1302 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1303 | DISPPLANE_SEL_PIPE_SHIFT; | |
1304 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, | |
9db4a9c7 JB |
1305 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1306 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1307 | } |
1308 | } | |
1309 | ||
19332d7a JB |
1310 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1311 | enum pipe pipe) | |
1312 | { | |
20674eef | 1313 | struct drm_device *dev = dev_priv->dev; |
1fe47785 | 1314 | int reg, sprite; |
19332d7a JB |
1315 | u32 val; |
1316 | ||
20674eef | 1317 | if (IS_VALLEYVIEW(dev)) { |
1fe47785 DL |
1318 | for_each_sprite(pipe, sprite) { |
1319 | reg = SPCNTR(pipe, sprite); | |
20674eef | 1320 | val = I915_READ(reg); |
83f26f16 | 1321 | WARN(val & SP_ENABLE, |
20674eef | 1322 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1323 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1324 | } |
1325 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
1326 | reg = SPRCTL(pipe); | |
19332d7a | 1327 | val = I915_READ(reg); |
83f26f16 | 1328 | WARN(val & SPRITE_ENABLE, |
06da8da2 | 1329 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1330 | plane_name(pipe), pipe_name(pipe)); |
1331 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1332 | reg = DVSCNTR(pipe); | |
19332d7a | 1333 | val = I915_READ(reg); |
83f26f16 | 1334 | WARN(val & DVS_ENABLE, |
06da8da2 | 1335 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1336 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1337 | } |
1338 | } | |
1339 | ||
89eff4be | 1340 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1341 | { |
1342 | u32 val; | |
1343 | bool enabled; | |
1344 | ||
89eff4be | 1345 | WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1346 | |
92f2584a JB |
1347 | val = I915_READ(PCH_DREF_CONTROL); |
1348 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1349 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
1350 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); | |
1351 | } | |
1352 | ||
ab9412ba DV |
1353 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1354 | enum pipe pipe) | |
92f2584a JB |
1355 | { |
1356 | int reg; | |
1357 | u32 val; | |
1358 | bool enabled; | |
1359 | ||
ab9412ba | 1360 | reg = PCH_TRANSCONF(pipe); |
92f2584a JB |
1361 | val = I915_READ(reg); |
1362 | enabled = !!(val & TRANS_ENABLE); | |
9db4a9c7 JB |
1363 | WARN(enabled, |
1364 | "transcoder assertion failed, should be off on pipe %c but is still active\n", | |
1365 | pipe_name(pipe)); | |
92f2584a JB |
1366 | } |
1367 | ||
4e634389 KP |
1368 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1369 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1370 | { |
1371 | if ((val & DP_PORT_EN) == 0) | |
1372 | return false; | |
1373 | ||
1374 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1375 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1376 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1377 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1378 | return false; | |
44f37d1f CML |
1379 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1380 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1381 | return false; | |
f0575e92 KP |
1382 | } else { |
1383 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1384 | return false; | |
1385 | } | |
1386 | return true; | |
1387 | } | |
1388 | ||
1519b995 KP |
1389 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1390 | enum pipe pipe, u32 val) | |
1391 | { | |
dc0fa718 | 1392 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1393 | return false; |
1394 | ||
1395 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1396 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1397 | return false; |
44f37d1f CML |
1398 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1399 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1400 | return false; | |
1519b995 | 1401 | } else { |
dc0fa718 | 1402 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1403 | return false; |
1404 | } | |
1405 | return true; | |
1406 | } | |
1407 | ||
1408 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1409 | enum pipe pipe, u32 val) | |
1410 | { | |
1411 | if ((val & LVDS_PORT_EN) == 0) | |
1412 | return false; | |
1413 | ||
1414 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1415 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1416 | return false; | |
1417 | } else { | |
1418 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1419 | return false; | |
1420 | } | |
1421 | return true; | |
1422 | } | |
1423 | ||
1424 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1425 | enum pipe pipe, u32 val) | |
1426 | { | |
1427 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1428 | return false; | |
1429 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1430 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1431 | return false; | |
1432 | } else { | |
1433 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1434 | return false; | |
1435 | } | |
1436 | return true; | |
1437 | } | |
1438 | ||
291906f1 | 1439 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1440 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1441 | { |
47a05eca | 1442 | u32 val = I915_READ(reg); |
4e634389 | 1443 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1444 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1445 | reg, pipe_name(pipe)); |
de9a35ab | 1446 | |
75c5da27 DV |
1447 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
1448 | && (val & DP_PIPEB_SELECT), | |
de9a35ab | 1449 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1450 | } |
1451 | ||
1452 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1453 | enum pipe pipe, int reg) | |
1454 | { | |
47a05eca | 1455 | u32 val = I915_READ(reg); |
b70ad586 | 1456 | WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1457 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1458 | reg, pipe_name(pipe)); |
de9a35ab | 1459 | |
dc0fa718 | 1460 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1461 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1462 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1463 | } |
1464 | ||
1465 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1466 | enum pipe pipe) | |
1467 | { | |
1468 | int reg; | |
1469 | u32 val; | |
291906f1 | 1470 | |
f0575e92 KP |
1471 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1472 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1473 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1474 | |
1475 | reg = PCH_ADPA; | |
1476 | val = I915_READ(reg); | |
b70ad586 | 1477 | WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1478 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1479 | pipe_name(pipe)); |
291906f1 JB |
1480 | |
1481 | reg = PCH_LVDS; | |
1482 | val = I915_READ(reg); | |
b70ad586 | 1483 | WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1484 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1485 | pipe_name(pipe)); |
291906f1 | 1486 | |
e2debe91 PZ |
1487 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1488 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1489 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1490 | } |
1491 | ||
40e9cf64 JB |
1492 | static void intel_init_dpio(struct drm_device *dev) |
1493 | { | |
1494 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1495 | ||
1496 | if (!IS_VALLEYVIEW(dev)) | |
1497 | return; | |
1498 | ||
a09caddd CML |
1499 | /* |
1500 | * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), | |
1501 | * CHV x1 PHY (DP/HDMI D) | |
1502 | * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) | |
1503 | */ | |
1504 | if (IS_CHERRYVIEW(dev)) { | |
1505 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; | |
1506 | DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO; | |
1507 | } else { | |
1508 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; | |
1509 | } | |
5382f5f3 JB |
1510 | } |
1511 | ||
1512 | static void intel_reset_dpio(struct drm_device *dev) | |
1513 | { | |
1514 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1515 | ||
1516 | if (!IS_VALLEYVIEW(dev)) | |
1517 | return; | |
1518 | ||
076ed3b2 CML |
1519 | if (IS_CHERRYVIEW(dev)) { |
1520 | enum dpio_phy phy; | |
1521 | u32 val; | |
1522 | ||
1523 | for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) { | |
1524 | /* Poll for phypwrgood signal */ | |
1525 | if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & | |
1526 | PHY_POWERGOOD(phy), 1)) | |
1527 | DRM_ERROR("Display PHY %d is not power up\n", phy); | |
1528 | ||
1529 | /* | |
1530 | * Deassert common lane reset for PHY. | |
1531 | * | |
1532 | * This should only be done on init and resume from S3 | |
1533 | * with both PLLs disabled, or we risk losing DPIO and | |
1534 | * PLL synchronization. | |
1535 | */ | |
1536 | val = I915_READ(DISPLAY_PHY_CONTROL); | |
1537 | I915_WRITE(DISPLAY_PHY_CONTROL, | |
1538 | PHY_COM_LANE_RESET_DEASSERT(phy, val)); | |
1539 | } | |
1540 | ||
1541 | } else { | |
1542 | /* | |
57021059 JB |
1543 | * If DPIO has already been reset, e.g. by BIOS, just skip all |
1544 | * this. | |
076ed3b2 | 1545 | */ |
57021059 JB |
1546 | if (I915_READ(DPIO_CTL) & DPIO_CMNRST) |
1547 | return; | |
1548 | ||
1549 | /* | |
1550 | * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx: | |
1551 | * Need to assert and de-assert PHY SB reset by gating the | |
1552 | * common lane power, then un-gating it. | |
1553 | * Simply ungating isn't enough to reset the PHY enough to get | |
1554 | * ports and lanes running. | |
1555 | */ | |
1556 | __vlv_set_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC, | |
1557 | false); | |
1558 | __vlv_set_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC, | |
1559 | true); | |
076ed3b2 | 1560 | } |
40e9cf64 JB |
1561 | } |
1562 | ||
426115cf | 1563 | static void vlv_enable_pll(struct intel_crtc *crtc) |
87442f73 | 1564 | { |
426115cf DV |
1565 | struct drm_device *dev = crtc->base.dev; |
1566 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1567 | int reg = DPLL(crtc->pipe); | |
1568 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
87442f73 | 1569 | |
426115cf | 1570 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 DV |
1571 | |
1572 | /* No really, not for ILK+ */ | |
1573 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
1574 | ||
1575 | /* PLL is protected by panel, make sure we can write it */ | |
1576 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) | |
426115cf | 1577 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1578 | |
426115cf DV |
1579 | I915_WRITE(reg, dpll); |
1580 | POSTING_READ(reg); | |
1581 | udelay(150); | |
1582 | ||
1583 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1584 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1585 | ||
1586 | I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md); | |
1587 | POSTING_READ(DPLL_MD(crtc->pipe)); | |
87442f73 DV |
1588 | |
1589 | /* We do this three times for luck */ | |
426115cf | 1590 | I915_WRITE(reg, dpll); |
87442f73 DV |
1591 | POSTING_READ(reg); |
1592 | udelay(150); /* wait for warmup */ | |
426115cf | 1593 | I915_WRITE(reg, dpll); |
87442f73 DV |
1594 | POSTING_READ(reg); |
1595 | udelay(150); /* wait for warmup */ | |
426115cf | 1596 | I915_WRITE(reg, dpll); |
87442f73 DV |
1597 | POSTING_READ(reg); |
1598 | udelay(150); /* wait for warmup */ | |
1599 | } | |
1600 | ||
9d556c99 CML |
1601 | static void chv_enable_pll(struct intel_crtc *crtc) |
1602 | { | |
1603 | struct drm_device *dev = crtc->base.dev; | |
1604 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1605 | int pipe = crtc->pipe; | |
1606 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1607 | u32 tmp; |
1608 | ||
1609 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1610 | ||
1611 | BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); | |
1612 | ||
1613 | mutex_lock(&dev_priv->dpio_lock); | |
1614 | ||
1615 | /* Enable back the 10bit clock to display controller */ | |
1616 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1617 | tmp |= DPIO_DCLKP_EN; | |
1618 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1619 | ||
1620 | /* | |
1621 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1622 | */ | |
1623 | udelay(1); | |
1624 | ||
1625 | /* Enable PLL */ | |
a11b0703 | 1626 | I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll); |
9d556c99 CML |
1627 | |
1628 | /* Check PLL is locked */ | |
a11b0703 | 1629 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1630 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1631 | ||
a11b0703 VS |
1632 | /* not sure when this should be written */ |
1633 | I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md); | |
1634 | POSTING_READ(DPLL_MD(pipe)); | |
1635 | ||
9d556c99 CML |
1636 | mutex_unlock(&dev_priv->dpio_lock); |
1637 | } | |
1638 | ||
66e3d5c0 | 1639 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1640 | { |
66e3d5c0 DV |
1641 | struct drm_device *dev = crtc->base.dev; |
1642 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1643 | int reg = DPLL(crtc->pipe); | |
1644 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
63d7bbe9 | 1645 | |
66e3d5c0 | 1646 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1647 | |
63d7bbe9 | 1648 | /* No really, not for ILK+ */ |
3d13ef2e | 1649 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1650 | |
1651 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1652 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1653 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1654 | |
66e3d5c0 DV |
1655 | I915_WRITE(reg, dpll); |
1656 | ||
1657 | /* Wait for the clocks to stabilize. */ | |
1658 | POSTING_READ(reg); | |
1659 | udelay(150); | |
1660 | ||
1661 | if (INTEL_INFO(dev)->gen >= 4) { | |
1662 | I915_WRITE(DPLL_MD(crtc->pipe), | |
1663 | crtc->config.dpll_hw_state.dpll_md); | |
1664 | } else { | |
1665 | /* The pixel multiplier can only be updated once the | |
1666 | * DPLL is enabled and the clocks are stable. | |
1667 | * | |
1668 | * So write it again. | |
1669 | */ | |
1670 | I915_WRITE(reg, dpll); | |
1671 | } | |
63d7bbe9 JB |
1672 | |
1673 | /* We do this three times for luck */ | |
66e3d5c0 | 1674 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1675 | POSTING_READ(reg); |
1676 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1677 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1678 | POSTING_READ(reg); |
1679 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1680 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1681 | POSTING_READ(reg); |
1682 | udelay(150); /* wait for warmup */ | |
1683 | } | |
1684 | ||
1685 | /** | |
50b44a44 | 1686 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1687 | * @dev_priv: i915 private structure |
1688 | * @pipe: pipe PLL to disable | |
1689 | * | |
1690 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1691 | * | |
1692 | * Note! This is for pre-ILK only. | |
1693 | */ | |
50b44a44 | 1694 | static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
63d7bbe9 | 1695 | { |
63d7bbe9 JB |
1696 | /* Don't disable pipe A or pipe A PLLs if needed */ |
1697 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1698 | return; | |
1699 | ||
1700 | /* Make sure the pipe isn't still relying on us */ | |
1701 | assert_pipe_disabled(dev_priv, pipe); | |
1702 | ||
50b44a44 DV |
1703 | I915_WRITE(DPLL(pipe), 0); |
1704 | POSTING_READ(DPLL(pipe)); | |
63d7bbe9 JB |
1705 | } |
1706 | ||
f6071166 JB |
1707 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1708 | { | |
1709 | u32 val = 0; | |
1710 | ||
1711 | /* Make sure the pipe isn't still relying on us */ | |
1712 | assert_pipe_disabled(dev_priv, pipe); | |
1713 | ||
e5cbfbfb ID |
1714 | /* |
1715 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1716 | * The latter is needed for VGA hotplug / manual detection. | |
1717 | */ | |
f6071166 | 1718 | if (pipe == PIPE_B) |
e5cbfbfb | 1719 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; |
f6071166 JB |
1720 | I915_WRITE(DPLL(pipe), val); |
1721 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1722 | |
1723 | } | |
1724 | ||
1725 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1726 | { | |
d752048d | 1727 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1728 | u32 val; |
1729 | ||
a11b0703 VS |
1730 | /* Make sure the pipe isn't still relying on us */ |
1731 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1732 | |
a11b0703 VS |
1733 | /* Set PLL en = 0 */ |
1734 | val = DPLL_SSC_REF_CLOCK_CHV; | |
1735 | if (pipe != PIPE_A) | |
1736 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1737 | I915_WRITE(DPLL(pipe), val); | |
1738 | POSTING_READ(DPLL(pipe)); | |
d752048d VS |
1739 | |
1740 | mutex_lock(&dev_priv->dpio_lock); | |
1741 | ||
1742 | /* Disable 10bit clock to display controller */ | |
1743 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1744 | val &= ~DPIO_DCLKP_EN; | |
1745 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1746 | ||
61407f6d VS |
1747 | /* disable left/right clock distribution */ |
1748 | if (pipe != PIPE_B) { | |
1749 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
1750 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
1751 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
1752 | } else { | |
1753 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
1754 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
1755 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
1756 | } | |
1757 | ||
d752048d | 1758 | mutex_unlock(&dev_priv->dpio_lock); |
f6071166 JB |
1759 | } |
1760 | ||
e4607fcf CML |
1761 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
1762 | struct intel_digital_port *dport) | |
89b667f8 JB |
1763 | { |
1764 | u32 port_mask; | |
00fc31b7 | 1765 | int dpll_reg; |
89b667f8 | 1766 | |
e4607fcf CML |
1767 | switch (dport->port) { |
1768 | case PORT_B: | |
89b667f8 | 1769 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1770 | dpll_reg = DPLL(0); |
e4607fcf CML |
1771 | break; |
1772 | case PORT_C: | |
89b667f8 | 1773 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 CML |
1774 | dpll_reg = DPLL(0); |
1775 | break; | |
1776 | case PORT_D: | |
1777 | port_mask = DPLL_PORTD_READY_MASK; | |
1778 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1779 | break; |
1780 | default: | |
1781 | BUG(); | |
1782 | } | |
89b667f8 | 1783 | |
00fc31b7 | 1784 | if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000)) |
89b667f8 | 1785 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", |
00fc31b7 | 1786 | port_name(dport->port), I915_READ(dpll_reg)); |
89b667f8 JB |
1787 | } |
1788 | ||
b14b1055 DV |
1789 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1790 | { | |
1791 | struct drm_device *dev = crtc->base.dev; | |
1792 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1793 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
1794 | ||
be19f0ff CW |
1795 | if (WARN_ON(pll == NULL)) |
1796 | return; | |
1797 | ||
b14b1055 DV |
1798 | WARN_ON(!pll->refcount); |
1799 | if (pll->active == 0) { | |
1800 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
1801 | WARN_ON(pll->on); | |
1802 | assert_shared_dpll_disabled(dev_priv, pll); | |
1803 | ||
1804 | pll->mode_set(dev_priv, pll); | |
1805 | } | |
1806 | } | |
1807 | ||
92f2584a | 1808 | /** |
85b3894f | 1809 | * intel_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1810 | * @dev_priv: i915 private structure |
1811 | * @pipe: pipe PLL to enable | |
1812 | * | |
1813 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1814 | * drives the transcoder clock. | |
1815 | */ | |
85b3894f | 1816 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1817 | { |
3d13ef2e DL |
1818 | struct drm_device *dev = crtc->base.dev; |
1819 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1820 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1821 | |
87a875bb | 1822 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1823 | return; |
1824 | ||
1825 | if (WARN_ON(pll->refcount == 0)) | |
1826 | return; | |
ee7b9f93 | 1827 | |
46edb027 DV |
1828 | DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n", |
1829 | pll->name, pll->active, pll->on, | |
e2b78267 | 1830 | crtc->base.base.id); |
92f2584a | 1831 | |
cdbd2316 DV |
1832 | if (pll->active++) { |
1833 | WARN_ON(!pll->on); | |
e9d6944e | 1834 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1835 | return; |
1836 | } | |
f4a091c7 | 1837 | WARN_ON(pll->on); |
ee7b9f93 | 1838 | |
46edb027 | 1839 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1840 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1841 | pll->on = true; |
92f2584a JB |
1842 | } |
1843 | ||
e2b78267 | 1844 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1845 | { |
3d13ef2e DL |
1846 | struct drm_device *dev = crtc->base.dev; |
1847 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1848 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1849 | |
92f2584a | 1850 | /* PCH only available on ILK+ */ |
3d13ef2e | 1851 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
87a875bb | 1852 | if (WARN_ON(pll == NULL)) |
ee7b9f93 | 1853 | return; |
92f2584a | 1854 | |
48da64a8 CW |
1855 | if (WARN_ON(pll->refcount == 0)) |
1856 | return; | |
7a419866 | 1857 | |
46edb027 DV |
1858 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1859 | pll->name, pll->active, pll->on, | |
e2b78267 | 1860 | crtc->base.base.id); |
7a419866 | 1861 | |
48da64a8 | 1862 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1863 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1864 | return; |
1865 | } | |
1866 | ||
e9d6944e | 1867 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1868 | WARN_ON(!pll->on); |
cdbd2316 | 1869 | if (--pll->active) |
7a419866 | 1870 | return; |
ee7b9f93 | 1871 | |
46edb027 | 1872 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1873 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1874 | pll->on = false; |
92f2584a JB |
1875 | } |
1876 | ||
b8a4f404 PZ |
1877 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1878 | enum pipe pipe) | |
040484af | 1879 | { |
23670b32 | 1880 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1881 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1882 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
23670b32 | 1883 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1884 | |
1885 | /* PCH only available on ILK+ */ | |
3d13ef2e | 1886 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
040484af JB |
1887 | |
1888 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1889 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1890 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1891 | |
1892 | /* FDI must be feeding us bits for PCH ports */ | |
1893 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1894 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1895 | ||
23670b32 DV |
1896 | if (HAS_PCH_CPT(dev)) { |
1897 | /* Workaround: Set the timing override bit before enabling the | |
1898 | * pch transcoder. */ | |
1899 | reg = TRANS_CHICKEN2(pipe); | |
1900 | val = I915_READ(reg); | |
1901 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1902 | I915_WRITE(reg, val); | |
59c859d6 | 1903 | } |
23670b32 | 1904 | |
ab9412ba | 1905 | reg = PCH_TRANSCONF(pipe); |
040484af | 1906 | val = I915_READ(reg); |
5f7f726d | 1907 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1908 | |
1909 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1910 | /* | |
1911 | * make the BPC in transcoder be consistent with | |
1912 | * that in pipeconf reg. | |
1913 | */ | |
dfd07d72 DV |
1914 | val &= ~PIPECONF_BPC_MASK; |
1915 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1916 | } |
5f7f726d PZ |
1917 | |
1918 | val &= ~TRANS_INTERLACE_MASK; | |
1919 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 PZ |
1920 | if (HAS_PCH_IBX(dev_priv->dev) && |
1921 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) | |
1922 | val |= TRANS_LEGACY_INTERLACED_ILK; | |
1923 | else | |
1924 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1925 | else |
1926 | val |= TRANS_PROGRESSIVE; | |
1927 | ||
040484af JB |
1928 | I915_WRITE(reg, val | TRANS_ENABLE); |
1929 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 1930 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1931 | } |
1932 | ||
8fb033d7 | 1933 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1934 | enum transcoder cpu_transcoder) |
040484af | 1935 | { |
8fb033d7 | 1936 | u32 val, pipeconf_val; |
8fb033d7 PZ |
1937 | |
1938 | /* PCH only available on ILK+ */ | |
3d13ef2e | 1939 | BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5); |
8fb033d7 | 1940 | |
8fb033d7 | 1941 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1942 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1943 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1944 | |
223a6fdf PZ |
1945 | /* Workaround: set timing override bit. */ |
1946 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1947 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
1948 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1949 | ||
25f3ef11 | 1950 | val = TRANS_ENABLE; |
937bb610 | 1951 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1952 | |
9a76b1c6 PZ |
1953 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1954 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1955 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1956 | else |
1957 | val |= TRANS_PROGRESSIVE; | |
1958 | ||
ab9412ba DV |
1959 | I915_WRITE(LPT_TRANSCONF, val); |
1960 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 1961 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1962 | } |
1963 | ||
b8a4f404 PZ |
1964 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1965 | enum pipe pipe) | |
040484af | 1966 | { |
23670b32 DV |
1967 | struct drm_device *dev = dev_priv->dev; |
1968 | uint32_t reg, val; | |
040484af JB |
1969 | |
1970 | /* FDI relies on the transcoder */ | |
1971 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1972 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1973 | ||
291906f1 JB |
1974 | /* Ports must be off as well */ |
1975 | assert_pch_ports_disabled(dev_priv, pipe); | |
1976 | ||
ab9412ba | 1977 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1978 | val = I915_READ(reg); |
1979 | val &= ~TRANS_ENABLE; | |
1980 | I915_WRITE(reg, val); | |
1981 | /* wait for PCH transcoder off, transcoder state */ | |
1982 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 1983 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 DV |
1984 | |
1985 | if (!HAS_PCH_IBX(dev)) { | |
1986 | /* Workaround: Clear the timing override chicken bit again. */ | |
1987 | reg = TRANS_CHICKEN2(pipe); | |
1988 | val = I915_READ(reg); | |
1989 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1990 | I915_WRITE(reg, val); | |
1991 | } | |
040484af JB |
1992 | } |
1993 | ||
ab4d966c | 1994 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1995 | { |
8fb033d7 PZ |
1996 | u32 val; |
1997 | ||
ab9412ba | 1998 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1999 | val &= ~TRANS_ENABLE; |
ab9412ba | 2000 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 2001 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 2002 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 2003 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
2004 | |
2005 | /* Workaround: clear timing override bit. */ | |
2006 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 2007 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 2008 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
2009 | } |
2010 | ||
b24e7179 | 2011 | /** |
309cfea8 | 2012 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 2013 | * @crtc: crtc responsible for the pipe |
b24e7179 | 2014 | * |
0372264a | 2015 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 2016 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 2017 | */ |
e1fdc473 | 2018 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2019 | { |
0372264a PZ |
2020 | struct drm_device *dev = crtc->base.dev; |
2021 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2022 | enum pipe pipe = crtc->pipe; | |
702e7a56 PZ |
2023 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
2024 | pipe); | |
1a240d4d | 2025 | enum pipe pch_transcoder; |
b24e7179 JB |
2026 | int reg; |
2027 | u32 val; | |
2028 | ||
58c6eaa2 | 2029 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 2030 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
2031 | assert_sprites_disabled(dev_priv, pipe); |
2032 | ||
681e5811 | 2033 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
2034 | pch_transcoder = TRANSCODER_A; |
2035 | else | |
2036 | pch_transcoder = pipe; | |
2037 | ||
b24e7179 JB |
2038 | /* |
2039 | * A pipe without a PLL won't actually be able to drive bits from | |
2040 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
2041 | * need the check. | |
2042 | */ | |
2043 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
fbf3218a | 2044 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
2045 | assert_dsi_pll_enabled(dev_priv); |
2046 | else | |
2047 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2048 | else { |
30421c4f | 2049 | if (crtc->config.has_pch_encoder) { |
040484af | 2050 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2051 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2052 | assert_fdi_tx_pll_enabled(dev_priv, |
2053 | (enum pipe) cpu_transcoder); | |
040484af JB |
2054 | } |
2055 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2056 | } | |
b24e7179 | 2057 | |
702e7a56 | 2058 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2059 | val = I915_READ(reg); |
7ad25d48 PZ |
2060 | if (val & PIPECONF_ENABLE) { |
2061 | WARN_ON(!(pipe == PIPE_A && | |
2062 | dev_priv->quirks & QUIRK_PIPEA_FORCE)); | |
00d70b15 | 2063 | return; |
7ad25d48 | 2064 | } |
00d70b15 CW |
2065 | |
2066 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2067 | POSTING_READ(reg); |
b24e7179 JB |
2068 | } |
2069 | ||
2070 | /** | |
309cfea8 | 2071 | * intel_disable_pipe - disable a pipe, asserting requirements |
b24e7179 JB |
2072 | * @dev_priv: i915 private structure |
2073 | * @pipe: pipe to disable | |
2074 | * | |
2075 | * Disable @pipe, making sure that various hardware specific requirements | |
2076 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. | |
2077 | * | |
2078 | * @pipe should be %PIPE_A or %PIPE_B. | |
2079 | * | |
2080 | * Will wait until the pipe has shut down before returning. | |
2081 | */ | |
2082 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, | |
2083 | enum pipe pipe) | |
2084 | { | |
702e7a56 PZ |
2085 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
2086 | pipe); | |
b24e7179 JB |
2087 | int reg; |
2088 | u32 val; | |
2089 | ||
2090 | /* | |
2091 | * Make sure planes won't keep trying to pump pixels to us, | |
2092 | * or we might hang the display. | |
2093 | */ | |
2094 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2095 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2096 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 JB |
2097 | |
2098 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
2099 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
2100 | return; | |
2101 | ||
702e7a56 | 2102 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2103 | val = I915_READ(reg); |
00d70b15 CW |
2104 | if ((val & PIPECONF_ENABLE) == 0) |
2105 | return; | |
2106 | ||
2107 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); | |
b24e7179 JB |
2108 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
2109 | } | |
2110 | ||
d74362c9 KP |
2111 | /* |
2112 | * Plane regs are double buffered, going from enabled->disabled needs a | |
2113 | * trigger in order to latch. The display address reg provides this. | |
2114 | */ | |
1dba99f4 VS |
2115 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
2116 | enum plane plane) | |
d74362c9 | 2117 | { |
3d13ef2e DL |
2118 | struct drm_device *dev = dev_priv->dev; |
2119 | u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); | |
1dba99f4 VS |
2120 | |
2121 | I915_WRITE(reg, I915_READ(reg)); | |
2122 | POSTING_READ(reg); | |
d74362c9 KP |
2123 | } |
2124 | ||
b24e7179 | 2125 | /** |
262ca2b0 | 2126 | * intel_enable_primary_hw_plane - enable the primary plane on a given pipe |
b24e7179 JB |
2127 | * @dev_priv: i915 private structure |
2128 | * @plane: plane to enable | |
2129 | * @pipe: pipe being fed | |
2130 | * | |
2131 | * Enable @plane on @pipe, making sure that @pipe is running first. | |
2132 | */ | |
262ca2b0 MR |
2133 | static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv, |
2134 | enum plane plane, enum pipe pipe) | |
b24e7179 | 2135 | { |
939c2fe8 VS |
2136 | struct intel_crtc *intel_crtc = |
2137 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
b24e7179 JB |
2138 | int reg; |
2139 | u32 val; | |
2140 | ||
2141 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
2142 | assert_pipe_enabled(dev_priv, pipe); | |
2143 | ||
98ec7739 VS |
2144 | if (intel_crtc->primary_enabled) |
2145 | return; | |
0037f71c | 2146 | |
4c445e0e | 2147 | intel_crtc->primary_enabled = true; |
939c2fe8 | 2148 | |
b24e7179 JB |
2149 | reg = DSPCNTR(plane); |
2150 | val = I915_READ(reg); | |
10efa932 | 2151 | WARN_ON(val & DISPLAY_PLANE_ENABLE); |
00d70b15 CW |
2152 | |
2153 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); | |
1dba99f4 | 2154 | intel_flush_primary_plane(dev_priv, plane); |
b24e7179 JB |
2155 | } |
2156 | ||
b24e7179 | 2157 | /** |
262ca2b0 | 2158 | * intel_disable_primary_hw_plane - disable the primary hardware plane |
b24e7179 JB |
2159 | * @dev_priv: i915 private structure |
2160 | * @plane: plane to disable | |
2161 | * @pipe: pipe consuming the data | |
2162 | * | |
2163 | * Disable @plane; should be an independent operation. | |
2164 | */ | |
262ca2b0 MR |
2165 | static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv, |
2166 | enum plane plane, enum pipe pipe) | |
b24e7179 | 2167 | { |
939c2fe8 VS |
2168 | struct intel_crtc *intel_crtc = |
2169 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
b24e7179 JB |
2170 | int reg; |
2171 | u32 val; | |
2172 | ||
98ec7739 VS |
2173 | if (!intel_crtc->primary_enabled) |
2174 | return; | |
0037f71c | 2175 | |
4c445e0e | 2176 | intel_crtc->primary_enabled = false; |
939c2fe8 | 2177 | |
b24e7179 JB |
2178 | reg = DSPCNTR(plane); |
2179 | val = I915_READ(reg); | |
10efa932 | 2180 | WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0); |
00d70b15 CW |
2181 | |
2182 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); | |
1dba99f4 | 2183 | intel_flush_primary_plane(dev_priv, plane); |
b24e7179 JB |
2184 | } |
2185 | ||
693db184 CW |
2186 | static bool need_vtd_wa(struct drm_device *dev) |
2187 | { | |
2188 | #ifdef CONFIG_INTEL_IOMMU | |
2189 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2190 | return true; | |
2191 | #endif | |
2192 | return false; | |
2193 | } | |
2194 | ||
a57ce0b2 JB |
2195 | static int intel_align_height(struct drm_device *dev, int height, bool tiled) |
2196 | { | |
2197 | int tile_height; | |
2198 | ||
2199 | tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1; | |
2200 | return ALIGN(height, tile_height); | |
2201 | } | |
2202 | ||
127bd2ac | 2203 | int |
48b956c5 | 2204 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 2205 | struct drm_i915_gem_object *obj, |
a4872ba6 | 2206 | struct intel_engine_cs *pipelined) |
6b95a207 | 2207 | { |
ce453d81 | 2208 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
2209 | u32 alignment; |
2210 | int ret; | |
2211 | ||
05394f39 | 2212 | switch (obj->tiling_mode) { |
6b95a207 | 2213 | case I915_TILING_NONE: |
534843da CW |
2214 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
2215 | alignment = 128 * 1024; | |
a6c45cf0 | 2216 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
2217 | alignment = 4 * 1024; |
2218 | else | |
2219 | alignment = 64 * 1024; | |
6b95a207 KH |
2220 | break; |
2221 | case I915_TILING_X: | |
2222 | /* pin() will align the object as required by fence */ | |
2223 | alignment = 0; | |
2224 | break; | |
2225 | case I915_TILING_Y: | |
80075d49 | 2226 | WARN(1, "Y tiled bo slipped through, driver bug!\n"); |
6b95a207 KH |
2227 | return -EINVAL; |
2228 | default: | |
2229 | BUG(); | |
2230 | } | |
2231 | ||
693db184 CW |
2232 | /* Note that the w/a also requires 64 PTE of padding following the |
2233 | * bo. We currently fill all unused PTE with the shadow page and so | |
2234 | * we should always have valid PTE following the scanout preventing | |
2235 | * the VT-d warning. | |
2236 | */ | |
2237 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2238 | alignment = 256 * 1024; | |
2239 | ||
ce453d81 | 2240 | dev_priv->mm.interruptible = false; |
2da3b9b9 | 2241 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
48b956c5 | 2242 | if (ret) |
ce453d81 | 2243 | goto err_interruptible; |
6b95a207 KH |
2244 | |
2245 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2246 | * fence, whereas 965+ only requires a fence if using | |
2247 | * framebuffer compression. For simplicity, we always install | |
2248 | * a fence as the cost is not that onerous. | |
2249 | */ | |
06d98131 | 2250 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
2251 | if (ret) |
2252 | goto err_unpin; | |
1690e1eb | 2253 | |
9a5a53b3 | 2254 | i915_gem_object_pin_fence(obj); |
6b95a207 | 2255 | |
ce453d81 | 2256 | dev_priv->mm.interruptible = true; |
6b95a207 | 2257 | return 0; |
48b956c5 CW |
2258 | |
2259 | err_unpin: | |
cc98b413 | 2260 | i915_gem_object_unpin_from_display_plane(obj); |
ce453d81 CW |
2261 | err_interruptible: |
2262 | dev_priv->mm.interruptible = true; | |
48b956c5 | 2263 | return ret; |
6b95a207 KH |
2264 | } |
2265 | ||
1690e1eb CW |
2266 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
2267 | { | |
2268 | i915_gem_object_unpin_fence(obj); | |
cc98b413 | 2269 | i915_gem_object_unpin_from_display_plane(obj); |
1690e1eb CW |
2270 | } |
2271 | ||
c2c75131 DV |
2272 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2273 | * is assumed to be a power-of-two. */ | |
bc752862 CW |
2274 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
2275 | unsigned int tiling_mode, | |
2276 | unsigned int cpp, | |
2277 | unsigned int pitch) | |
c2c75131 | 2278 | { |
bc752862 CW |
2279 | if (tiling_mode != I915_TILING_NONE) { |
2280 | unsigned int tile_rows, tiles; | |
c2c75131 | 2281 | |
bc752862 CW |
2282 | tile_rows = *y / 8; |
2283 | *y %= 8; | |
c2c75131 | 2284 | |
bc752862 CW |
2285 | tiles = *x / (512/cpp); |
2286 | *x %= 512/cpp; | |
2287 | ||
2288 | return tile_rows * pitch * 8 + tiles * 4096; | |
2289 | } else { | |
2290 | unsigned int offset; | |
2291 | ||
2292 | offset = *y * pitch + *x * cpp; | |
2293 | *y = 0; | |
2294 | *x = (offset & 4095) / cpp; | |
2295 | return offset & -4096; | |
2296 | } | |
c2c75131 DV |
2297 | } |
2298 | ||
46f297fb JB |
2299 | int intel_format_to_fourcc(int format) |
2300 | { | |
2301 | switch (format) { | |
2302 | case DISPPLANE_8BPP: | |
2303 | return DRM_FORMAT_C8; | |
2304 | case DISPPLANE_BGRX555: | |
2305 | return DRM_FORMAT_XRGB1555; | |
2306 | case DISPPLANE_BGRX565: | |
2307 | return DRM_FORMAT_RGB565; | |
2308 | default: | |
2309 | case DISPPLANE_BGRX888: | |
2310 | return DRM_FORMAT_XRGB8888; | |
2311 | case DISPPLANE_RGBX888: | |
2312 | return DRM_FORMAT_XBGR8888; | |
2313 | case DISPPLANE_BGRX101010: | |
2314 | return DRM_FORMAT_XRGB2101010; | |
2315 | case DISPPLANE_RGBX101010: | |
2316 | return DRM_FORMAT_XBGR2101010; | |
2317 | } | |
2318 | } | |
2319 | ||
484b41dd | 2320 | static bool intel_alloc_plane_obj(struct intel_crtc *crtc, |
46f297fb JB |
2321 | struct intel_plane_config *plane_config) |
2322 | { | |
2323 | struct drm_device *dev = crtc->base.dev; | |
2324 | struct drm_i915_gem_object *obj = NULL; | |
2325 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2326 | u32 base = plane_config->base; | |
2327 | ||
ff2652ea CW |
2328 | if (plane_config->size == 0) |
2329 | return false; | |
2330 | ||
46f297fb JB |
2331 | obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base, |
2332 | plane_config->size); | |
2333 | if (!obj) | |
484b41dd | 2334 | return false; |
46f297fb JB |
2335 | |
2336 | if (plane_config->tiled) { | |
2337 | obj->tiling_mode = I915_TILING_X; | |
66e514c1 | 2338 | obj->stride = crtc->base.primary->fb->pitches[0]; |
46f297fb JB |
2339 | } |
2340 | ||
66e514c1 DA |
2341 | mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format; |
2342 | mode_cmd.width = crtc->base.primary->fb->width; | |
2343 | mode_cmd.height = crtc->base.primary->fb->height; | |
2344 | mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0]; | |
46f297fb JB |
2345 | |
2346 | mutex_lock(&dev->struct_mutex); | |
2347 | ||
66e514c1 | 2348 | if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb), |
484b41dd | 2349 | &mode_cmd, obj)) { |
46f297fb JB |
2350 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2351 | goto out_unref_obj; | |
2352 | } | |
2353 | ||
2354 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2355 | |
2356 | DRM_DEBUG_KMS("plane fb obj %p\n", obj); | |
2357 | return true; | |
46f297fb JB |
2358 | |
2359 | out_unref_obj: | |
2360 | drm_gem_object_unreference(&obj->base); | |
2361 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2362 | return false; |
2363 | } | |
2364 | ||
2365 | static void intel_find_plane_obj(struct intel_crtc *intel_crtc, | |
2366 | struct intel_plane_config *plane_config) | |
2367 | { | |
2368 | struct drm_device *dev = intel_crtc->base.dev; | |
2369 | struct drm_crtc *c; | |
2370 | struct intel_crtc *i; | |
2371 | struct intel_framebuffer *fb; | |
2372 | ||
66e514c1 | 2373 | if (!intel_crtc->base.primary->fb) |
484b41dd JB |
2374 | return; |
2375 | ||
2376 | if (intel_alloc_plane_obj(intel_crtc, plane_config)) | |
2377 | return; | |
2378 | ||
66e514c1 DA |
2379 | kfree(intel_crtc->base.primary->fb); |
2380 | intel_crtc->base.primary->fb = NULL; | |
484b41dd JB |
2381 | |
2382 | /* | |
2383 | * Failed to alloc the obj, check to see if we should share | |
2384 | * an fb with another CRTC instead | |
2385 | */ | |
70e1e0ec | 2386 | for_each_crtc(dev, c) { |
484b41dd JB |
2387 | i = to_intel_crtc(c); |
2388 | ||
2389 | if (c == &intel_crtc->base) | |
2390 | continue; | |
2391 | ||
66e514c1 | 2392 | if (!i->active || !c->primary->fb) |
484b41dd JB |
2393 | continue; |
2394 | ||
66e514c1 | 2395 | fb = to_intel_framebuffer(c->primary->fb); |
484b41dd | 2396 | if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) { |
66e514c1 DA |
2397 | drm_framebuffer_reference(c->primary->fb); |
2398 | intel_crtc->base.primary->fb = c->primary->fb; | |
484b41dd JB |
2399 | break; |
2400 | } | |
2401 | } | |
46f297fb JB |
2402 | } |
2403 | ||
29b9bde6 DV |
2404 | static void i9xx_update_primary_plane(struct drm_crtc *crtc, |
2405 | struct drm_framebuffer *fb, | |
2406 | int x, int y) | |
81255565 JB |
2407 | { |
2408 | struct drm_device *dev = crtc->dev; | |
2409 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2410 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2411 | struct intel_framebuffer *intel_fb; | |
05394f39 | 2412 | struct drm_i915_gem_object *obj; |
81255565 | 2413 | int plane = intel_crtc->plane; |
e506a0c6 | 2414 | unsigned long linear_offset; |
81255565 | 2415 | u32 dspcntr; |
5eddb70b | 2416 | u32 reg; |
81255565 | 2417 | |
81255565 JB |
2418 | intel_fb = to_intel_framebuffer(fb); |
2419 | obj = intel_fb->obj; | |
81255565 | 2420 | |
5eddb70b CW |
2421 | reg = DSPCNTR(plane); |
2422 | dspcntr = I915_READ(reg); | |
81255565 JB |
2423 | /* Mask out pixel format bits in case we change it */ |
2424 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
2425 | switch (fb->pixel_format) { |
2426 | case DRM_FORMAT_C8: | |
81255565 JB |
2427 | dspcntr |= DISPPLANE_8BPP; |
2428 | break; | |
57779d06 VS |
2429 | case DRM_FORMAT_XRGB1555: |
2430 | case DRM_FORMAT_ARGB1555: | |
2431 | dspcntr |= DISPPLANE_BGRX555; | |
81255565 | 2432 | break; |
57779d06 VS |
2433 | case DRM_FORMAT_RGB565: |
2434 | dspcntr |= DISPPLANE_BGRX565; | |
2435 | break; | |
2436 | case DRM_FORMAT_XRGB8888: | |
2437 | case DRM_FORMAT_ARGB8888: | |
2438 | dspcntr |= DISPPLANE_BGRX888; | |
2439 | break; | |
2440 | case DRM_FORMAT_XBGR8888: | |
2441 | case DRM_FORMAT_ABGR8888: | |
2442 | dspcntr |= DISPPLANE_RGBX888; | |
2443 | break; | |
2444 | case DRM_FORMAT_XRGB2101010: | |
2445 | case DRM_FORMAT_ARGB2101010: | |
2446 | dspcntr |= DISPPLANE_BGRX101010; | |
2447 | break; | |
2448 | case DRM_FORMAT_XBGR2101010: | |
2449 | case DRM_FORMAT_ABGR2101010: | |
2450 | dspcntr |= DISPPLANE_RGBX101010; | |
81255565 JB |
2451 | break; |
2452 | default: | |
baba133a | 2453 | BUG(); |
81255565 | 2454 | } |
57779d06 | 2455 | |
a6c45cf0 | 2456 | if (INTEL_INFO(dev)->gen >= 4) { |
05394f39 | 2457 | if (obj->tiling_mode != I915_TILING_NONE) |
81255565 JB |
2458 | dspcntr |= DISPPLANE_TILED; |
2459 | else | |
2460 | dspcntr &= ~DISPPLANE_TILED; | |
2461 | } | |
2462 | ||
de1aa629 VS |
2463 | if (IS_G4X(dev)) |
2464 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2465 | ||
5eddb70b | 2466 | I915_WRITE(reg, dspcntr); |
81255565 | 2467 | |
e506a0c6 | 2468 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
81255565 | 2469 | |
c2c75131 DV |
2470 | if (INTEL_INFO(dev)->gen >= 4) { |
2471 | intel_crtc->dspaddr_offset = | |
bc752862 CW |
2472 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2473 | fb->bits_per_pixel / 8, | |
2474 | fb->pitches[0]); | |
c2c75131 DV |
2475 | linear_offset -= intel_crtc->dspaddr_offset; |
2476 | } else { | |
e506a0c6 | 2477 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2478 | } |
e506a0c6 | 2479 | |
f343c5f6 BW |
2480 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2481 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2482 | fb->pitches[0]); | |
01f2c773 | 2483 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2484 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2485 | I915_WRITE(DSPSURF(plane), |
2486 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2487 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2488 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2489 | } else |
f343c5f6 | 2490 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2491 | POSTING_READ(reg); |
17638cd6 JB |
2492 | } |
2493 | ||
29b9bde6 DV |
2494 | static void ironlake_update_primary_plane(struct drm_crtc *crtc, |
2495 | struct drm_framebuffer *fb, | |
2496 | int x, int y) | |
17638cd6 JB |
2497 | { |
2498 | struct drm_device *dev = crtc->dev; | |
2499 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2500 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2501 | struct intel_framebuffer *intel_fb; | |
2502 | struct drm_i915_gem_object *obj; | |
2503 | int plane = intel_crtc->plane; | |
e506a0c6 | 2504 | unsigned long linear_offset; |
17638cd6 JB |
2505 | u32 dspcntr; |
2506 | u32 reg; | |
2507 | ||
17638cd6 JB |
2508 | intel_fb = to_intel_framebuffer(fb); |
2509 | obj = intel_fb->obj; | |
2510 | ||
2511 | reg = DSPCNTR(plane); | |
2512 | dspcntr = I915_READ(reg); | |
2513 | /* Mask out pixel format bits in case we change it */ | |
2514 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
2515 | switch (fb->pixel_format) { |
2516 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2517 | dspcntr |= DISPPLANE_8BPP; |
2518 | break; | |
57779d06 VS |
2519 | case DRM_FORMAT_RGB565: |
2520 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2521 | break; |
57779d06 VS |
2522 | case DRM_FORMAT_XRGB8888: |
2523 | case DRM_FORMAT_ARGB8888: | |
2524 | dspcntr |= DISPPLANE_BGRX888; | |
2525 | break; | |
2526 | case DRM_FORMAT_XBGR8888: | |
2527 | case DRM_FORMAT_ABGR8888: | |
2528 | dspcntr |= DISPPLANE_RGBX888; | |
2529 | break; | |
2530 | case DRM_FORMAT_XRGB2101010: | |
2531 | case DRM_FORMAT_ARGB2101010: | |
2532 | dspcntr |= DISPPLANE_BGRX101010; | |
2533 | break; | |
2534 | case DRM_FORMAT_XBGR2101010: | |
2535 | case DRM_FORMAT_ABGR2101010: | |
2536 | dspcntr |= DISPPLANE_RGBX101010; | |
17638cd6 JB |
2537 | break; |
2538 | default: | |
baba133a | 2539 | BUG(); |
17638cd6 JB |
2540 | } |
2541 | ||
2542 | if (obj->tiling_mode != I915_TILING_NONE) | |
2543 | dspcntr |= DISPPLANE_TILED; | |
2544 | else | |
2545 | dspcntr &= ~DISPPLANE_TILED; | |
2546 | ||
b42c6009 | 2547 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
1f5d76db PZ |
2548 | dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE; |
2549 | else | |
2550 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
17638cd6 JB |
2551 | |
2552 | I915_WRITE(reg, dspcntr); | |
2553 | ||
e506a0c6 | 2554 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
c2c75131 | 2555 | intel_crtc->dspaddr_offset = |
bc752862 CW |
2556 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2557 | fb->bits_per_pixel / 8, | |
2558 | fb->pitches[0]); | |
c2c75131 | 2559 | linear_offset -= intel_crtc->dspaddr_offset; |
17638cd6 | 2560 | |
f343c5f6 BW |
2561 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2562 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2563 | fb->pitches[0]); | |
01f2c773 | 2564 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2565 | I915_WRITE(DSPSURF(plane), |
2566 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2567 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2568 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2569 | } else { | |
2570 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2571 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2572 | } | |
17638cd6 | 2573 | POSTING_READ(reg); |
17638cd6 JB |
2574 | } |
2575 | ||
2576 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ | |
2577 | static int | |
2578 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
2579 | int x, int y, enum mode_set_atomic state) | |
2580 | { | |
2581 | struct drm_device *dev = crtc->dev; | |
2582 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 2583 | |
6b8e6ed0 CW |
2584 | if (dev_priv->display.disable_fbc) |
2585 | dev_priv->display.disable_fbc(dev); | |
3dec0095 | 2586 | intel_increase_pllclock(crtc); |
81255565 | 2587 | |
29b9bde6 DV |
2588 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
2589 | ||
2590 | return 0; | |
81255565 JB |
2591 | } |
2592 | ||
96a02917 VS |
2593 | void intel_display_handle_reset(struct drm_device *dev) |
2594 | { | |
2595 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2596 | struct drm_crtc *crtc; | |
2597 | ||
2598 | /* | |
2599 | * Flips in the rings have been nuked by the reset, | |
2600 | * so complete all pending flips so that user space | |
2601 | * will get its events and not get stuck. | |
2602 | * | |
2603 | * Also update the base address of all primary | |
2604 | * planes to the the last fb to make sure we're | |
2605 | * showing the correct fb after a reset. | |
2606 | * | |
2607 | * Need to make two loops over the crtcs so that we | |
2608 | * don't try to grab a crtc mutex before the | |
2609 | * pending_flip_queue really got woken up. | |
2610 | */ | |
2611 | ||
70e1e0ec | 2612 | for_each_crtc(dev, crtc) { |
96a02917 VS |
2613 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2614 | enum plane plane = intel_crtc->plane; | |
2615 | ||
2616 | intel_prepare_page_flip(dev, plane); | |
2617 | intel_finish_page_flip_plane(dev, plane); | |
2618 | } | |
2619 | ||
70e1e0ec | 2620 | for_each_crtc(dev, crtc) { |
96a02917 VS |
2621 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2622 | ||
51fd371b | 2623 | drm_modeset_lock(&crtc->mutex, NULL); |
947fdaad CW |
2624 | /* |
2625 | * FIXME: Once we have proper support for primary planes (and | |
2626 | * disabling them without disabling the entire crtc) allow again | |
66e514c1 | 2627 | * a NULL crtc->primary->fb. |
947fdaad | 2628 | */ |
f4510a27 | 2629 | if (intel_crtc->active && crtc->primary->fb) |
262ca2b0 | 2630 | dev_priv->display.update_primary_plane(crtc, |
66e514c1 | 2631 | crtc->primary->fb, |
262ca2b0 MR |
2632 | crtc->x, |
2633 | crtc->y); | |
51fd371b | 2634 | drm_modeset_unlock(&crtc->mutex); |
96a02917 VS |
2635 | } |
2636 | } | |
2637 | ||
14667a4b CW |
2638 | static int |
2639 | intel_finish_fb(struct drm_framebuffer *old_fb) | |
2640 | { | |
2641 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; | |
2642 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2643 | bool was_interruptible = dev_priv->mm.interruptible; | |
2644 | int ret; | |
2645 | ||
14667a4b CW |
2646 | /* Big Hammer, we also need to ensure that any pending |
2647 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
2648 | * current scanout is retired before unpinning the old | |
2649 | * framebuffer. | |
2650 | * | |
2651 | * This should only fail upon a hung GPU, in which case we | |
2652 | * can safely continue. | |
2653 | */ | |
2654 | dev_priv->mm.interruptible = false; | |
2655 | ret = i915_gem_object_finish_gpu(obj); | |
2656 | dev_priv->mm.interruptible = was_interruptible; | |
2657 | ||
2658 | return ret; | |
2659 | } | |
2660 | ||
7d5e3799 CW |
2661 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
2662 | { | |
2663 | struct drm_device *dev = crtc->dev; | |
2664 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2665 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2666 | unsigned long flags; | |
2667 | bool pending; | |
2668 | ||
2669 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
2670 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
2671 | return false; | |
2672 | ||
2673 | spin_lock_irqsave(&dev->event_lock, flags); | |
2674 | pending = to_intel_crtc(crtc)->unpin_work != NULL; | |
2675 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
2676 | ||
2677 | return pending; | |
2678 | } | |
2679 | ||
5c3b82e2 | 2680 | static int |
3c4fdcfb | 2681 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
94352cf9 | 2682 | struct drm_framebuffer *fb) |
79e53945 JB |
2683 | { |
2684 | struct drm_device *dev = crtc->dev; | |
6b8e6ed0 | 2685 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 2686 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
94352cf9 | 2687 | struct drm_framebuffer *old_fb; |
5c3b82e2 | 2688 | int ret; |
79e53945 | 2689 | |
7d5e3799 CW |
2690 | if (intel_crtc_has_pending_flip(crtc)) { |
2691 | DRM_ERROR("pipe is still busy with an old pageflip\n"); | |
2692 | return -EBUSY; | |
2693 | } | |
2694 | ||
79e53945 | 2695 | /* no fb bound */ |
94352cf9 | 2696 | if (!fb) { |
a5071c2f | 2697 | DRM_ERROR("No FB bound\n"); |
5c3b82e2 CW |
2698 | return 0; |
2699 | } | |
2700 | ||
7eb552ae | 2701 | if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) { |
84f44ce7 VS |
2702 | DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n", |
2703 | plane_name(intel_crtc->plane), | |
2704 | INTEL_INFO(dev)->num_pipes); | |
5c3b82e2 | 2705 | return -EINVAL; |
79e53945 JB |
2706 | } |
2707 | ||
5c3b82e2 | 2708 | mutex_lock(&dev->struct_mutex); |
265db958 | 2709 | ret = intel_pin_and_fence_fb_obj(dev, |
94352cf9 | 2710 | to_intel_framebuffer(fb)->obj, |
919926ae | 2711 | NULL); |
8ac36ec1 | 2712 | mutex_unlock(&dev->struct_mutex); |
5c3b82e2 | 2713 | if (ret != 0) { |
a5071c2f | 2714 | DRM_ERROR("pin & fence failed\n"); |
5c3b82e2 CW |
2715 | return ret; |
2716 | } | |
79e53945 | 2717 | |
bb2043de DL |
2718 | /* |
2719 | * Update pipe size and adjust fitter if needed: the reason for this is | |
2720 | * that in compute_mode_changes we check the native mode (not the pfit | |
2721 | * mode) to see if we can flip rather than do a full mode set. In the | |
2722 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
2723 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
2724 | * sized surface. | |
2725 | * | |
2726 | * To fix this properly, we need to hoist the checks up into | |
2727 | * compute_mode_changes (or above), check the actual pfit state and | |
2728 | * whether the platform allows pfit disable with pipe active, and only | |
2729 | * then update the pipesrc and pfit state, even on the flip path. | |
2730 | */ | |
d330a953 | 2731 | if (i915.fastboot) { |
d7bf63f2 DL |
2732 | const struct drm_display_mode *adjusted_mode = |
2733 | &intel_crtc->config.adjusted_mode; | |
2734 | ||
4d6a3e63 | 2735 | I915_WRITE(PIPESRC(intel_crtc->pipe), |
d7bf63f2 DL |
2736 | ((adjusted_mode->crtc_hdisplay - 1) << 16) | |
2737 | (adjusted_mode->crtc_vdisplay - 1)); | |
fd4daa9c | 2738 | if (!intel_crtc->config.pch_pfit.enabled && |
4d6a3e63 JB |
2739 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
2740 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
2741 | I915_WRITE(PF_CTL(intel_crtc->pipe), 0); | |
2742 | I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0); | |
2743 | I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0); | |
2744 | } | |
0637d60d JB |
2745 | intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay; |
2746 | intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay; | |
4d6a3e63 JB |
2747 | } |
2748 | ||
29b9bde6 | 2749 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
3c4fdcfb | 2750 | |
f4510a27 MR |
2751 | old_fb = crtc->primary->fb; |
2752 | crtc->primary->fb = fb; | |
6c4c86f5 DV |
2753 | crtc->x = x; |
2754 | crtc->y = y; | |
94352cf9 | 2755 | |
b7f1de28 | 2756 | if (old_fb) { |
d7697eea DV |
2757 | if (intel_crtc->active && old_fb != fb) |
2758 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
8ac36ec1 | 2759 | mutex_lock(&dev->struct_mutex); |
1690e1eb | 2760 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); |
8ac36ec1 | 2761 | mutex_unlock(&dev->struct_mutex); |
b7f1de28 | 2762 | } |
652c393a | 2763 | |
8ac36ec1 | 2764 | mutex_lock(&dev->struct_mutex); |
6b8e6ed0 | 2765 | intel_update_fbc(dev); |
4906557e | 2766 | intel_edp_psr_update(dev); |
5c3b82e2 | 2767 | mutex_unlock(&dev->struct_mutex); |
79e53945 | 2768 | |
5c3b82e2 | 2769 | return 0; |
79e53945 JB |
2770 | } |
2771 | ||
5e84e1a4 ZW |
2772 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2773 | { | |
2774 | struct drm_device *dev = crtc->dev; | |
2775 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2776 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2777 | int pipe = intel_crtc->pipe; | |
2778 | u32 reg, temp; | |
2779 | ||
2780 | /* enable normal train */ | |
2781 | reg = FDI_TX_CTL(pipe); | |
2782 | temp = I915_READ(reg); | |
61e499bf | 2783 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
2784 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2785 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
2786 | } else { |
2787 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2788 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 2789 | } |
5e84e1a4 ZW |
2790 | I915_WRITE(reg, temp); |
2791 | ||
2792 | reg = FDI_RX_CTL(pipe); | |
2793 | temp = I915_READ(reg); | |
2794 | if (HAS_PCH_CPT(dev)) { | |
2795 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2796 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
2797 | } else { | |
2798 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2799 | temp |= FDI_LINK_TRAIN_NONE; | |
2800 | } | |
2801 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
2802 | ||
2803 | /* wait one idle pattern time */ | |
2804 | POSTING_READ(reg); | |
2805 | udelay(1000); | |
357555c0 JB |
2806 | |
2807 | /* IVB wants error correction enabled */ | |
2808 | if (IS_IVYBRIDGE(dev)) | |
2809 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
2810 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
2811 | } |
2812 | ||
1fbc0d78 | 2813 | static bool pipe_has_enabled_pch(struct intel_crtc *crtc) |
1e833f40 | 2814 | { |
1fbc0d78 DV |
2815 | return crtc->base.enabled && crtc->active && |
2816 | crtc->config.has_pch_encoder; | |
1e833f40 DV |
2817 | } |
2818 | ||
01a415fd DV |
2819 | static void ivb_modeset_global_resources(struct drm_device *dev) |
2820 | { | |
2821 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2822 | struct intel_crtc *pipe_B_crtc = | |
2823 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
2824 | struct intel_crtc *pipe_C_crtc = | |
2825 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); | |
2826 | uint32_t temp; | |
2827 | ||
1e833f40 DV |
2828 | /* |
2829 | * When everything is off disable fdi C so that we could enable fdi B | |
2830 | * with all lanes. Note that we don't care about enabled pipes without | |
2831 | * an enabled pch encoder. | |
2832 | */ | |
2833 | if (!pipe_has_enabled_pch(pipe_B_crtc) && | |
2834 | !pipe_has_enabled_pch(pipe_C_crtc)) { | |
01a415fd DV |
2835 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
2836 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
2837 | ||
2838 | temp = I915_READ(SOUTH_CHICKEN1); | |
2839 | temp &= ~FDI_BC_BIFURCATION_SELECT; | |
2840 | DRM_DEBUG_KMS("disabling fdi C rx\n"); | |
2841 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
2842 | } | |
2843 | } | |
2844 | ||
8db9d77b ZW |
2845 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2846 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
2847 | { | |
2848 | struct drm_device *dev = crtc->dev; | |
2849 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2850 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2851 | int pipe = intel_crtc->pipe; | |
5eddb70b | 2852 | u32 reg, temp, tries; |
8db9d77b | 2853 | |
1c8562f6 | 2854 | /* FDI needs bits from pipe first */ |
0fc932b8 | 2855 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 2856 | |
e1a44743 AJ |
2857 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2858 | for train result */ | |
5eddb70b CW |
2859 | reg = FDI_RX_IMR(pipe); |
2860 | temp = I915_READ(reg); | |
e1a44743 AJ |
2861 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2862 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2863 | I915_WRITE(reg, temp); |
2864 | I915_READ(reg); | |
e1a44743 AJ |
2865 | udelay(150); |
2866 | ||
8db9d77b | 2867 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2868 | reg = FDI_TX_CTL(pipe); |
2869 | temp = I915_READ(reg); | |
627eb5a3 DV |
2870 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2871 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
2872 | temp &= ~FDI_LINK_TRAIN_NONE; |
2873 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 2874 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2875 | |
5eddb70b CW |
2876 | reg = FDI_RX_CTL(pipe); |
2877 | temp = I915_READ(reg); | |
8db9d77b ZW |
2878 | temp &= ~FDI_LINK_TRAIN_NONE; |
2879 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
2880 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2881 | ||
2882 | POSTING_READ(reg); | |
8db9d77b ZW |
2883 | udelay(150); |
2884 | ||
5b2adf89 | 2885 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
2886 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
2887 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
2888 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 2889 | |
5eddb70b | 2890 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2891 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2892 | temp = I915_READ(reg); |
8db9d77b ZW |
2893 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2894 | ||
2895 | if ((temp & FDI_RX_BIT_LOCK)) { | |
2896 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 2897 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
2898 | break; |
2899 | } | |
8db9d77b | 2900 | } |
e1a44743 | 2901 | if (tries == 5) |
5eddb70b | 2902 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2903 | |
2904 | /* Train 2 */ | |
5eddb70b CW |
2905 | reg = FDI_TX_CTL(pipe); |
2906 | temp = I915_READ(reg); | |
8db9d77b ZW |
2907 | temp &= ~FDI_LINK_TRAIN_NONE; |
2908 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2909 | I915_WRITE(reg, temp); |
8db9d77b | 2910 | |
5eddb70b CW |
2911 | reg = FDI_RX_CTL(pipe); |
2912 | temp = I915_READ(reg); | |
8db9d77b ZW |
2913 | temp &= ~FDI_LINK_TRAIN_NONE; |
2914 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2915 | I915_WRITE(reg, temp); |
8db9d77b | 2916 | |
5eddb70b CW |
2917 | POSTING_READ(reg); |
2918 | udelay(150); | |
8db9d77b | 2919 | |
5eddb70b | 2920 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2921 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2922 | temp = I915_READ(reg); |
8db9d77b ZW |
2923 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2924 | ||
2925 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 2926 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
2927 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2928 | break; | |
2929 | } | |
8db9d77b | 2930 | } |
e1a44743 | 2931 | if (tries == 5) |
5eddb70b | 2932 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2933 | |
2934 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 2935 | |
8db9d77b ZW |
2936 | } |
2937 | ||
0206e353 | 2938 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
2939 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2940 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
2941 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
2942 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
2943 | }; | |
2944 | ||
2945 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
2946 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
2947 | { | |
2948 | struct drm_device *dev = crtc->dev; | |
2949 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2950 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2951 | int pipe = intel_crtc->pipe; | |
fa37d39e | 2952 | u32 reg, temp, i, retry; |
8db9d77b | 2953 | |
e1a44743 AJ |
2954 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2955 | for train result */ | |
5eddb70b CW |
2956 | reg = FDI_RX_IMR(pipe); |
2957 | temp = I915_READ(reg); | |
e1a44743 AJ |
2958 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2959 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2960 | I915_WRITE(reg, temp); |
2961 | ||
2962 | POSTING_READ(reg); | |
e1a44743 AJ |
2963 | udelay(150); |
2964 | ||
8db9d77b | 2965 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2966 | reg = FDI_TX_CTL(pipe); |
2967 | temp = I915_READ(reg); | |
627eb5a3 DV |
2968 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2969 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
2970 | temp &= ~FDI_LINK_TRAIN_NONE; |
2971 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2972 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2973 | /* SNB-B */ | |
2974 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 2975 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2976 | |
d74cf324 DV |
2977 | I915_WRITE(FDI_RX_MISC(pipe), |
2978 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
2979 | ||
5eddb70b CW |
2980 | reg = FDI_RX_CTL(pipe); |
2981 | temp = I915_READ(reg); | |
8db9d77b ZW |
2982 | if (HAS_PCH_CPT(dev)) { |
2983 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2984 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2985 | } else { | |
2986 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2987 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2988 | } | |
5eddb70b CW |
2989 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2990 | ||
2991 | POSTING_READ(reg); | |
8db9d77b ZW |
2992 | udelay(150); |
2993 | ||
0206e353 | 2994 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2995 | reg = FDI_TX_CTL(pipe); |
2996 | temp = I915_READ(reg); | |
8db9d77b ZW |
2997 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2998 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2999 | I915_WRITE(reg, temp); |
3000 | ||
3001 | POSTING_READ(reg); | |
8db9d77b ZW |
3002 | udelay(500); |
3003 | ||
fa37d39e SP |
3004 | for (retry = 0; retry < 5; retry++) { |
3005 | reg = FDI_RX_IIR(pipe); | |
3006 | temp = I915_READ(reg); | |
3007 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3008 | if (temp & FDI_RX_BIT_LOCK) { | |
3009 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3010 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3011 | break; | |
3012 | } | |
3013 | udelay(50); | |
8db9d77b | 3014 | } |
fa37d39e SP |
3015 | if (retry < 5) |
3016 | break; | |
8db9d77b ZW |
3017 | } |
3018 | if (i == 4) | |
5eddb70b | 3019 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3020 | |
3021 | /* Train 2 */ | |
5eddb70b CW |
3022 | reg = FDI_TX_CTL(pipe); |
3023 | temp = I915_READ(reg); | |
8db9d77b ZW |
3024 | temp &= ~FDI_LINK_TRAIN_NONE; |
3025 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3026 | if (IS_GEN6(dev)) { | |
3027 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3028 | /* SNB-B */ | |
3029 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3030 | } | |
5eddb70b | 3031 | I915_WRITE(reg, temp); |
8db9d77b | 3032 | |
5eddb70b CW |
3033 | reg = FDI_RX_CTL(pipe); |
3034 | temp = I915_READ(reg); | |
8db9d77b ZW |
3035 | if (HAS_PCH_CPT(dev)) { |
3036 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3037 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3038 | } else { | |
3039 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3040 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3041 | } | |
5eddb70b CW |
3042 | I915_WRITE(reg, temp); |
3043 | ||
3044 | POSTING_READ(reg); | |
8db9d77b ZW |
3045 | udelay(150); |
3046 | ||
0206e353 | 3047 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3048 | reg = FDI_TX_CTL(pipe); |
3049 | temp = I915_READ(reg); | |
8db9d77b ZW |
3050 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3051 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3052 | I915_WRITE(reg, temp); |
3053 | ||
3054 | POSTING_READ(reg); | |
8db9d77b ZW |
3055 | udelay(500); |
3056 | ||
fa37d39e SP |
3057 | for (retry = 0; retry < 5; retry++) { |
3058 | reg = FDI_RX_IIR(pipe); | |
3059 | temp = I915_READ(reg); | |
3060 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3061 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3062 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3063 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3064 | break; | |
3065 | } | |
3066 | udelay(50); | |
8db9d77b | 3067 | } |
fa37d39e SP |
3068 | if (retry < 5) |
3069 | break; | |
8db9d77b ZW |
3070 | } |
3071 | if (i == 4) | |
5eddb70b | 3072 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3073 | |
3074 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3075 | } | |
3076 | ||
357555c0 JB |
3077 | /* Manual link training for Ivy Bridge A0 parts */ |
3078 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3079 | { | |
3080 | struct drm_device *dev = crtc->dev; | |
3081 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3082 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3083 | int pipe = intel_crtc->pipe; | |
139ccd3f | 3084 | u32 reg, temp, i, j; |
357555c0 JB |
3085 | |
3086 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3087 | for train result */ | |
3088 | reg = FDI_RX_IMR(pipe); | |
3089 | temp = I915_READ(reg); | |
3090 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3091 | temp &= ~FDI_RX_BIT_LOCK; | |
3092 | I915_WRITE(reg, temp); | |
3093 | ||
3094 | POSTING_READ(reg); | |
3095 | udelay(150); | |
3096 | ||
01a415fd DV |
3097 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3098 | I915_READ(FDI_RX_IIR(pipe))); | |
3099 | ||
139ccd3f JB |
3100 | /* Try each vswing and preemphasis setting twice before moving on */ |
3101 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3102 | /* disable first in case we need to retry */ | |
3103 | reg = FDI_TX_CTL(pipe); | |
3104 | temp = I915_READ(reg); | |
3105 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3106 | temp &= ~FDI_TX_ENABLE; | |
3107 | I915_WRITE(reg, temp); | |
357555c0 | 3108 | |
139ccd3f JB |
3109 | reg = FDI_RX_CTL(pipe); |
3110 | temp = I915_READ(reg); | |
3111 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3112 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3113 | temp &= ~FDI_RX_ENABLE; | |
3114 | I915_WRITE(reg, temp); | |
357555c0 | 3115 | |
139ccd3f | 3116 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3117 | reg = FDI_TX_CTL(pipe); |
3118 | temp = I915_READ(reg); | |
139ccd3f JB |
3119 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
3120 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
3121 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; | |
357555c0 | 3122 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3123 | temp |= snb_b_fdi_train_param[j/2]; |
3124 | temp |= FDI_COMPOSITE_SYNC; | |
3125 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3126 | |
139ccd3f JB |
3127 | I915_WRITE(FDI_RX_MISC(pipe), |
3128 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3129 | |
139ccd3f | 3130 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3131 | temp = I915_READ(reg); |
139ccd3f JB |
3132 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3133 | temp |= FDI_COMPOSITE_SYNC; | |
3134 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3135 | |
139ccd3f JB |
3136 | POSTING_READ(reg); |
3137 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3138 | |
139ccd3f JB |
3139 | for (i = 0; i < 4; i++) { |
3140 | reg = FDI_RX_IIR(pipe); | |
3141 | temp = I915_READ(reg); | |
3142 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3143 | |
139ccd3f JB |
3144 | if (temp & FDI_RX_BIT_LOCK || |
3145 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3146 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3147 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3148 | i); | |
3149 | break; | |
3150 | } | |
3151 | udelay(1); /* should be 0.5us */ | |
3152 | } | |
3153 | if (i == 4) { | |
3154 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3155 | continue; | |
3156 | } | |
357555c0 | 3157 | |
139ccd3f | 3158 | /* Train 2 */ |
357555c0 JB |
3159 | reg = FDI_TX_CTL(pipe); |
3160 | temp = I915_READ(reg); | |
139ccd3f JB |
3161 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3162 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3163 | I915_WRITE(reg, temp); | |
3164 | ||
3165 | reg = FDI_RX_CTL(pipe); | |
3166 | temp = I915_READ(reg); | |
3167 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3168 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3169 | I915_WRITE(reg, temp); |
3170 | ||
3171 | POSTING_READ(reg); | |
139ccd3f | 3172 | udelay(2); /* should be 1.5us */ |
357555c0 | 3173 | |
139ccd3f JB |
3174 | for (i = 0; i < 4; i++) { |
3175 | reg = FDI_RX_IIR(pipe); | |
3176 | temp = I915_READ(reg); | |
3177 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3178 | |
139ccd3f JB |
3179 | if (temp & FDI_RX_SYMBOL_LOCK || |
3180 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3181 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3182 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3183 | i); | |
3184 | goto train_done; | |
3185 | } | |
3186 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3187 | } |
139ccd3f JB |
3188 | if (i == 4) |
3189 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3190 | } |
357555c0 | 3191 | |
139ccd3f | 3192 | train_done: |
357555c0 JB |
3193 | DRM_DEBUG_KMS("FDI train done.\n"); |
3194 | } | |
3195 | ||
88cefb6c | 3196 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3197 | { |
88cefb6c | 3198 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3199 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3200 | int pipe = intel_crtc->pipe; |
5eddb70b | 3201 | u32 reg, temp; |
79e53945 | 3202 | |
c64e311e | 3203 | |
c98e9dcf | 3204 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3205 | reg = FDI_RX_CTL(pipe); |
3206 | temp = I915_READ(reg); | |
627eb5a3 DV |
3207 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
3208 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
dfd07d72 | 3209 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3210 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3211 | ||
3212 | POSTING_READ(reg); | |
c98e9dcf JB |
3213 | udelay(200); |
3214 | ||
3215 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3216 | temp = I915_READ(reg); |
3217 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3218 | ||
3219 | POSTING_READ(reg); | |
c98e9dcf JB |
3220 | udelay(200); |
3221 | ||
20749730 PZ |
3222 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3223 | reg = FDI_TX_CTL(pipe); | |
3224 | temp = I915_READ(reg); | |
3225 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3226 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3227 | |
20749730 PZ |
3228 | POSTING_READ(reg); |
3229 | udelay(100); | |
6be4a607 | 3230 | } |
0e23b99d JB |
3231 | } |
3232 | ||
88cefb6c DV |
3233 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3234 | { | |
3235 | struct drm_device *dev = intel_crtc->base.dev; | |
3236 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3237 | int pipe = intel_crtc->pipe; | |
3238 | u32 reg, temp; | |
3239 | ||
3240 | /* Switch from PCDclk to Rawclk */ | |
3241 | reg = FDI_RX_CTL(pipe); | |
3242 | temp = I915_READ(reg); | |
3243 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3244 | ||
3245 | /* Disable CPU FDI TX PLL */ | |
3246 | reg = FDI_TX_CTL(pipe); | |
3247 | temp = I915_READ(reg); | |
3248 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3249 | ||
3250 | POSTING_READ(reg); | |
3251 | udelay(100); | |
3252 | ||
3253 | reg = FDI_RX_CTL(pipe); | |
3254 | temp = I915_READ(reg); | |
3255 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3256 | ||
3257 | /* Wait for the clocks to turn off. */ | |
3258 | POSTING_READ(reg); | |
3259 | udelay(100); | |
3260 | } | |
3261 | ||
0fc932b8 JB |
3262 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3263 | { | |
3264 | struct drm_device *dev = crtc->dev; | |
3265 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3266 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3267 | int pipe = intel_crtc->pipe; | |
3268 | u32 reg, temp; | |
3269 | ||
3270 | /* disable CPU FDI tx and PCH FDI rx */ | |
3271 | reg = FDI_TX_CTL(pipe); | |
3272 | temp = I915_READ(reg); | |
3273 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3274 | POSTING_READ(reg); | |
3275 | ||
3276 | reg = FDI_RX_CTL(pipe); | |
3277 | temp = I915_READ(reg); | |
3278 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3279 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3280 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3281 | ||
3282 | POSTING_READ(reg); | |
3283 | udelay(100); | |
3284 | ||
3285 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3286 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3287 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3288 | |
3289 | /* still set train pattern 1 */ | |
3290 | reg = FDI_TX_CTL(pipe); | |
3291 | temp = I915_READ(reg); | |
3292 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3293 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3294 | I915_WRITE(reg, temp); | |
3295 | ||
3296 | reg = FDI_RX_CTL(pipe); | |
3297 | temp = I915_READ(reg); | |
3298 | if (HAS_PCH_CPT(dev)) { | |
3299 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3300 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3301 | } else { | |
3302 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3303 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3304 | } | |
3305 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3306 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3307 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3308 | I915_WRITE(reg, temp); |
3309 | ||
3310 | POSTING_READ(reg); | |
3311 | udelay(100); | |
3312 | } | |
3313 | ||
5dce5b93 CW |
3314 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3315 | { | |
3316 | struct intel_crtc *crtc; | |
3317 | ||
3318 | /* Note that we don't need to be called with mode_config.lock here | |
3319 | * as our list of CRTC objects is static for the lifetime of the | |
3320 | * device and so cannot disappear as we iterate. Similarly, we can | |
3321 | * happily treat the predicates as racy, atomic checks as userspace | |
3322 | * cannot claim and pin a new fb without at least acquring the | |
3323 | * struct_mutex and so serialising with us. | |
3324 | */ | |
d3fcc808 | 3325 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3326 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3327 | continue; | |
3328 | ||
3329 | if (crtc->unpin_work) | |
3330 | intel_wait_for_vblank(dev, crtc->pipe); | |
3331 | ||
3332 | return true; | |
3333 | } | |
3334 | ||
3335 | return false; | |
3336 | } | |
3337 | ||
46a55d30 | 3338 | void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3339 | { |
0f91128d | 3340 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3341 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 | 3342 | |
f4510a27 | 3343 | if (crtc->primary->fb == NULL) |
e6c3a2a6 CW |
3344 | return; |
3345 | ||
2c10d571 DV |
3346 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
3347 | ||
eed6d67d DV |
3348 | WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue, |
3349 | !intel_crtc_has_pending_flip(crtc), | |
3350 | 60*HZ) == 0); | |
5bb61643 | 3351 | |
0f91128d | 3352 | mutex_lock(&dev->struct_mutex); |
f4510a27 | 3353 | intel_finish_fb(crtc->primary->fb); |
0f91128d | 3354 | mutex_unlock(&dev->struct_mutex); |
e6c3a2a6 CW |
3355 | } |
3356 | ||
e615efe4 ED |
3357 | /* Program iCLKIP clock to the desired frequency */ |
3358 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3359 | { | |
3360 | struct drm_device *dev = crtc->dev; | |
3361 | struct drm_i915_private *dev_priv = dev->dev_private; | |
241bfc38 | 3362 | int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; |
e615efe4 ED |
3363 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3364 | u32 temp; | |
3365 | ||
09153000 DV |
3366 | mutex_lock(&dev_priv->dpio_lock); |
3367 | ||
e615efe4 ED |
3368 | /* It is necessary to ungate the pixclk gate prior to programming |
3369 | * the divisors, and gate it back when it is done. | |
3370 | */ | |
3371 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3372 | ||
3373 | /* Disable SSCCTL */ | |
3374 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
3375 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
3376 | SBI_SSCCTL_DISABLE, | |
3377 | SBI_ICLK); | |
e615efe4 ED |
3378 | |
3379 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3380 | if (clock == 20000) { |
e615efe4 ED |
3381 | auxdiv = 1; |
3382 | divsel = 0x41; | |
3383 | phaseinc = 0x20; | |
3384 | } else { | |
3385 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3386 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3387 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3388 | * convert the virtual clock precision to KHz here for higher |
3389 | * precision. | |
3390 | */ | |
3391 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3392 | u32 iclk_pi_range = 64; | |
3393 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3394 | ||
12d7ceed | 3395 | desired_divisor = (iclk_virtual_root_freq / clock); |
e615efe4 ED |
3396 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3397 | pi_value = desired_divisor % iclk_pi_range; | |
3398 | ||
3399 | auxdiv = 0; | |
3400 | divsel = msb_divisor_value - 2; | |
3401 | phaseinc = pi_value; | |
3402 | } | |
3403 | ||
3404 | /* This should not happen with any sane values */ | |
3405 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3406 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3407 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3408 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3409 | ||
3410 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3411 | clock, |
e615efe4 ED |
3412 | auxdiv, |
3413 | divsel, | |
3414 | phasedir, | |
3415 | phaseinc); | |
3416 | ||
3417 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 3418 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3419 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3420 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3421 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3422 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3423 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3424 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3425 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3426 | |
3427 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3428 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3429 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3430 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3431 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3432 | |
3433 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3434 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3435 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3436 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
3437 | |
3438 | /* Wait for initialization time */ | |
3439 | udelay(24); | |
3440 | ||
3441 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 DV |
3442 | |
3443 | mutex_unlock(&dev_priv->dpio_lock); | |
e615efe4 ED |
3444 | } |
3445 | ||
275f01b2 DV |
3446 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
3447 | enum pipe pch_transcoder) | |
3448 | { | |
3449 | struct drm_device *dev = crtc->base.dev; | |
3450 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3451 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; | |
3452 | ||
3453 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
3454 | I915_READ(HTOTAL(cpu_transcoder))); | |
3455 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
3456 | I915_READ(HBLANK(cpu_transcoder))); | |
3457 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
3458 | I915_READ(HSYNC(cpu_transcoder))); | |
3459 | ||
3460 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
3461 | I915_READ(VTOTAL(cpu_transcoder))); | |
3462 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
3463 | I915_READ(VBLANK(cpu_transcoder))); | |
3464 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
3465 | I915_READ(VSYNC(cpu_transcoder))); | |
3466 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
3467 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
3468 | } | |
3469 | ||
1fbc0d78 DV |
3470 | static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) |
3471 | { | |
3472 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3473 | uint32_t temp; | |
3474 | ||
3475 | temp = I915_READ(SOUTH_CHICKEN1); | |
3476 | if (temp & FDI_BC_BIFURCATION_SELECT) | |
3477 | return; | |
3478 | ||
3479 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
3480 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
3481 | ||
3482 | temp |= FDI_BC_BIFURCATION_SELECT; | |
3483 | DRM_DEBUG_KMS("enabling fdi C rx\n"); | |
3484 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
3485 | POSTING_READ(SOUTH_CHICKEN1); | |
3486 | } | |
3487 | ||
3488 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
3489 | { | |
3490 | struct drm_device *dev = intel_crtc->base.dev; | |
3491 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3492 | ||
3493 | switch (intel_crtc->pipe) { | |
3494 | case PIPE_A: | |
3495 | break; | |
3496 | case PIPE_B: | |
3497 | if (intel_crtc->config.fdi_lanes > 2) | |
3498 | WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); | |
3499 | else | |
3500 | cpt_enable_fdi_bc_bifurcation(dev); | |
3501 | ||
3502 | break; | |
3503 | case PIPE_C: | |
3504 | cpt_enable_fdi_bc_bifurcation(dev); | |
3505 | ||
3506 | break; | |
3507 | default: | |
3508 | BUG(); | |
3509 | } | |
3510 | } | |
3511 | ||
f67a559d JB |
3512 | /* |
3513 | * Enable PCH resources required for PCH ports: | |
3514 | * - PCH PLLs | |
3515 | * - FDI training & RX/TX | |
3516 | * - update transcoder timings | |
3517 | * - DP transcoding bits | |
3518 | * - transcoder | |
3519 | */ | |
3520 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
3521 | { |
3522 | struct drm_device *dev = crtc->dev; | |
3523 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3524 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3525 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 3526 | u32 reg, temp; |
2c07245f | 3527 | |
ab9412ba | 3528 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 3529 | |
1fbc0d78 DV |
3530 | if (IS_IVYBRIDGE(dev)) |
3531 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
3532 | ||
cd986abb DV |
3533 | /* Write the TU size bits before fdi link training, so that error |
3534 | * detection works. */ | |
3535 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
3536 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
3537 | ||
c98e9dcf | 3538 | /* For PCH output, training FDI link */ |
674cf967 | 3539 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 3540 | |
3ad8a208 DV |
3541 | /* We need to program the right clock selection before writing the pixel |
3542 | * mutliplier into the DPLL. */ | |
303b81e0 | 3543 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 3544 | u32 sel; |
4b645f14 | 3545 | |
c98e9dcf | 3546 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
3547 | temp |= TRANS_DPLL_ENABLE(pipe); |
3548 | sel = TRANS_DPLLB_SEL(pipe); | |
a43f6e0f | 3549 | if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
3550 | temp |= sel; |
3551 | else | |
3552 | temp &= ~sel; | |
c98e9dcf | 3553 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 3554 | } |
5eddb70b | 3555 | |
3ad8a208 DV |
3556 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
3557 | * transcoder, and we actually should do this to not upset any PCH | |
3558 | * transcoder that already use the clock when we share it. | |
3559 | * | |
3560 | * Note that enable_shared_dpll tries to do the right thing, but | |
3561 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
3562 | * the right LVDS enable sequence. */ | |
85b3894f | 3563 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 3564 | |
d9b6cb56 JB |
3565 | /* set transcoder timing, panel must allow it */ |
3566 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 3567 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 3568 | |
303b81e0 | 3569 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 3570 | |
c98e9dcf JB |
3571 | /* For PCH DP, enable TRANS_DP_CTL */ |
3572 | if (HAS_PCH_CPT(dev) && | |
417e822d KP |
3573 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
3574 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
dfd07d72 | 3575 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
3576 | reg = TRANS_DP_CTL(pipe); |
3577 | temp = I915_READ(reg); | |
3578 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
3579 | TRANS_DP_SYNC_MASK | |
3580 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
3581 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3582 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 3583 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
3584 | |
3585 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 3586 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 3587 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 3588 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
3589 | |
3590 | switch (intel_trans_dp_port_sel(crtc)) { | |
3591 | case PCH_DP_B: | |
5eddb70b | 3592 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
3593 | break; |
3594 | case PCH_DP_C: | |
5eddb70b | 3595 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
3596 | break; |
3597 | case PCH_DP_D: | |
5eddb70b | 3598 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
3599 | break; |
3600 | default: | |
e95d41e1 | 3601 | BUG(); |
32f9d658 | 3602 | } |
2c07245f | 3603 | |
5eddb70b | 3604 | I915_WRITE(reg, temp); |
6be4a607 | 3605 | } |
b52eb4dc | 3606 | |
b8a4f404 | 3607 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
3608 | } |
3609 | ||
1507e5bd PZ |
3610 | static void lpt_pch_enable(struct drm_crtc *crtc) |
3611 | { | |
3612 | struct drm_device *dev = crtc->dev; | |
3613 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3614 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3b117c8f | 3615 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
1507e5bd | 3616 | |
ab9412ba | 3617 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 3618 | |
8c52b5e8 | 3619 | lpt_program_iclkip(crtc); |
1507e5bd | 3620 | |
0540e488 | 3621 | /* Set transcoder timing. */ |
275f01b2 | 3622 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 3623 | |
937bb610 | 3624 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
3625 | } |
3626 | ||
e2b78267 | 3627 | static void intel_put_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3628 | { |
e2b78267 | 3629 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
ee7b9f93 JB |
3630 | |
3631 | if (pll == NULL) | |
3632 | return; | |
3633 | ||
3634 | if (pll->refcount == 0) { | |
46edb027 | 3635 | WARN(1, "bad %s refcount\n", pll->name); |
ee7b9f93 JB |
3636 | return; |
3637 | } | |
3638 | ||
f4a091c7 DV |
3639 | if (--pll->refcount == 0) { |
3640 | WARN_ON(pll->on); | |
3641 | WARN_ON(pll->active); | |
3642 | } | |
3643 | ||
a43f6e0f | 3644 | crtc->config.shared_dpll = DPLL_ID_PRIVATE; |
ee7b9f93 JB |
3645 | } |
3646 | ||
b89a1d39 | 3647 | static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3648 | { |
e2b78267 DV |
3649 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
3650 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
3651 | enum intel_dpll_id i; | |
ee7b9f93 | 3652 | |
ee7b9f93 | 3653 | if (pll) { |
46edb027 DV |
3654 | DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n", |
3655 | crtc->base.base.id, pll->name); | |
e2b78267 | 3656 | intel_put_shared_dpll(crtc); |
ee7b9f93 JB |
3657 | } |
3658 | ||
98b6bd99 DV |
3659 | if (HAS_PCH_IBX(dev_priv->dev)) { |
3660 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 3661 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 3662 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 3663 | |
46edb027 DV |
3664 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
3665 | crtc->base.base.id, pll->name); | |
98b6bd99 | 3666 | |
f2a69f44 DV |
3667 | WARN_ON(pll->refcount); |
3668 | ||
98b6bd99 DV |
3669 | goto found; |
3670 | } | |
3671 | ||
e72f9fbf DV |
3672 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3673 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 JB |
3674 | |
3675 | /* Only want to check enabled timings first */ | |
3676 | if (pll->refcount == 0) | |
3677 | continue; | |
3678 | ||
b89a1d39 DV |
3679 | if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state, |
3680 | sizeof(pll->hw_state)) == 0) { | |
46edb027 | 3681 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n", |
e2b78267 | 3682 | crtc->base.base.id, |
46edb027 | 3683 | pll->name, pll->refcount, pll->active); |
ee7b9f93 JB |
3684 | |
3685 | goto found; | |
3686 | } | |
3687 | } | |
3688 | ||
3689 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
3690 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3691 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 | 3692 | if (pll->refcount == 0) { |
46edb027 DV |
3693 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
3694 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
3695 | goto found; |
3696 | } | |
3697 | } | |
3698 | ||
3699 | return NULL; | |
3700 | ||
3701 | found: | |
f2a69f44 DV |
3702 | if (pll->refcount == 0) |
3703 | pll->hw_state = crtc->config.dpll_hw_state; | |
3704 | ||
a43f6e0f | 3705 | crtc->config.shared_dpll = i; |
46edb027 DV |
3706 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
3707 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 3708 | |
cdbd2316 | 3709 | pll->refcount++; |
e04c7350 | 3710 | |
ee7b9f93 JB |
3711 | return pll; |
3712 | } | |
3713 | ||
a1520318 | 3714 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
3715 | { |
3716 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 3717 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
3718 | u32 temp; |
3719 | ||
3720 | temp = I915_READ(dslreg); | |
3721 | udelay(500); | |
3722 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 3723 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 3724 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
3725 | } |
3726 | } | |
3727 | ||
b074cec8 JB |
3728 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
3729 | { | |
3730 | struct drm_device *dev = crtc->base.dev; | |
3731 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3732 | int pipe = crtc->pipe; | |
3733 | ||
fd4daa9c | 3734 | if (crtc->config.pch_pfit.enabled) { |
b074cec8 JB |
3735 | /* Force use of hard-coded filter coefficients |
3736 | * as some pre-programmed values are broken, | |
3737 | * e.g. x201. | |
3738 | */ | |
3739 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
3740 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
3741 | PF_PIPE_SEL_IVB(pipe)); | |
3742 | else | |
3743 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
3744 | I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos); | |
3745 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size); | |
d4270e57 JB |
3746 | } |
3747 | } | |
3748 | ||
bb53d4ae VS |
3749 | static void intel_enable_planes(struct drm_crtc *crtc) |
3750 | { | |
3751 | struct drm_device *dev = crtc->dev; | |
3752 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 3753 | struct drm_plane *plane; |
bb53d4ae VS |
3754 | struct intel_plane *intel_plane; |
3755 | ||
af2b653b MR |
3756 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
3757 | intel_plane = to_intel_plane(plane); | |
bb53d4ae VS |
3758 | if (intel_plane->pipe == pipe) |
3759 | intel_plane_restore(&intel_plane->base); | |
af2b653b | 3760 | } |
bb53d4ae VS |
3761 | } |
3762 | ||
3763 | static void intel_disable_planes(struct drm_crtc *crtc) | |
3764 | { | |
3765 | struct drm_device *dev = crtc->dev; | |
3766 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 3767 | struct drm_plane *plane; |
bb53d4ae VS |
3768 | struct intel_plane *intel_plane; |
3769 | ||
af2b653b MR |
3770 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
3771 | intel_plane = to_intel_plane(plane); | |
bb53d4ae VS |
3772 | if (intel_plane->pipe == pipe) |
3773 | intel_plane_disable(&intel_plane->base); | |
af2b653b | 3774 | } |
bb53d4ae VS |
3775 | } |
3776 | ||
20bc8673 | 3777 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 3778 | { |
cea165c3 VS |
3779 | struct drm_device *dev = crtc->base.dev; |
3780 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 PZ |
3781 | |
3782 | if (!crtc->config.ips_enabled) | |
3783 | return; | |
3784 | ||
cea165c3 VS |
3785 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
3786 | intel_wait_for_vblank(dev, crtc->pipe); | |
3787 | ||
d77e4531 | 3788 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 3789 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
3790 | mutex_lock(&dev_priv->rps.hw_lock); |
3791 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
3792 | mutex_unlock(&dev_priv->rps.hw_lock); | |
3793 | /* Quoting Art Runyan: "its not safe to expect any particular | |
3794 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
3795 | * mailbox." Moreover, the mailbox may return a bogus state, |
3796 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
3797 | */ |
3798 | } else { | |
3799 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
3800 | /* The bit only becomes 1 in the next vblank, so this wait here | |
3801 | * is essentially intel_wait_for_vblank. If we don't have this | |
3802 | * and don't wait for vblanks until the end of crtc_enable, then | |
3803 | * the HW state readout code will complain that the expected | |
3804 | * IPS_CTL value is not the one we read. */ | |
3805 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
3806 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
3807 | } | |
d77e4531 PZ |
3808 | } |
3809 | ||
20bc8673 | 3810 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
3811 | { |
3812 | struct drm_device *dev = crtc->base.dev; | |
3813 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3814 | ||
3815 | if (!crtc->config.ips_enabled) | |
3816 | return; | |
3817 | ||
3818 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 3819 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
3820 | mutex_lock(&dev_priv->rps.hw_lock); |
3821 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
3822 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
3823 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
3824 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
3825 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 3826 | } else { |
2a114cc1 | 3827 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
3828 | POSTING_READ(IPS_CTL); |
3829 | } | |
d77e4531 PZ |
3830 | |
3831 | /* We need to wait for a vblank before we can disable the plane. */ | |
3832 | intel_wait_for_vblank(dev, crtc->pipe); | |
3833 | } | |
3834 | ||
3835 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
3836 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
3837 | { | |
3838 | struct drm_device *dev = crtc->dev; | |
3839 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3840 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3841 | enum pipe pipe = intel_crtc->pipe; | |
3842 | int palreg = PALETTE(pipe); | |
3843 | int i; | |
3844 | bool reenable_ips = false; | |
3845 | ||
3846 | /* The clocks have to be on to load the palette. */ | |
3847 | if (!crtc->enabled || !intel_crtc->active) | |
3848 | return; | |
3849 | ||
3850 | if (!HAS_PCH_SPLIT(dev_priv->dev)) { | |
3851 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) | |
3852 | assert_dsi_pll_enabled(dev_priv); | |
3853 | else | |
3854 | assert_pll_enabled(dev_priv, pipe); | |
3855 | } | |
3856 | ||
3857 | /* use legacy palette for Ironlake */ | |
3858 | if (HAS_PCH_SPLIT(dev)) | |
3859 | palreg = LGC_PALETTE(pipe); | |
3860 | ||
3861 | /* Workaround : Do not read or write the pipe palette/gamma data while | |
3862 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
3863 | */ | |
41e6fc4c | 3864 | if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled && |
d77e4531 PZ |
3865 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
3866 | GAMMA_MODE_MODE_SPLIT)) { | |
3867 | hsw_disable_ips(intel_crtc); | |
3868 | reenable_ips = true; | |
3869 | } | |
3870 | ||
3871 | for (i = 0; i < 256; i++) { | |
3872 | I915_WRITE(palreg + 4 * i, | |
3873 | (intel_crtc->lut_r[i] << 16) | | |
3874 | (intel_crtc->lut_g[i] << 8) | | |
3875 | intel_crtc->lut_b[i]); | |
3876 | } | |
3877 | ||
3878 | if (reenable_ips) | |
3879 | hsw_enable_ips(intel_crtc); | |
3880 | } | |
3881 | ||
d3eedb1a VS |
3882 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
3883 | { | |
3884 | if (!enable && intel_crtc->overlay) { | |
3885 | struct drm_device *dev = intel_crtc->base.dev; | |
3886 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3887 | ||
3888 | mutex_lock(&dev->struct_mutex); | |
3889 | dev_priv->mm.interruptible = false; | |
3890 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
3891 | dev_priv->mm.interruptible = true; | |
3892 | mutex_unlock(&dev->struct_mutex); | |
3893 | } | |
3894 | ||
3895 | /* Let userspace switch the overlay on again. In most cases userspace | |
3896 | * has to recompute where to put it anyway. | |
3897 | */ | |
3898 | } | |
3899 | ||
3900 | /** | |
3901 | * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware | |
3902 | * cursor plane briefly if not already running after enabling the display | |
3903 | * plane. | |
3904 | * This workaround avoids occasional blank screens when self refresh is | |
3905 | * enabled. | |
3906 | */ | |
3907 | static void | |
3908 | g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe) | |
3909 | { | |
3910 | u32 cntl = I915_READ(CURCNTR(pipe)); | |
3911 | ||
3912 | if ((cntl & CURSOR_MODE) == 0) { | |
3913 | u32 fw_bcl_self = I915_READ(FW_BLC_SELF); | |
3914 | ||
3915 | I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN); | |
3916 | I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX); | |
3917 | intel_wait_for_vblank(dev_priv->dev, pipe); | |
3918 | I915_WRITE(CURCNTR(pipe), cntl); | |
3919 | I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); | |
3920 | I915_WRITE(FW_BLC_SELF, fw_bcl_self); | |
3921 | } | |
3922 | } | |
3923 | ||
3924 | static void intel_crtc_enable_planes(struct drm_crtc *crtc) | |
a5c4d7bc VS |
3925 | { |
3926 | struct drm_device *dev = crtc->dev; | |
3927 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3928 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3929 | int pipe = intel_crtc->pipe; | |
3930 | int plane = intel_crtc->plane; | |
3931 | ||
f98551ae VS |
3932 | drm_vblank_on(dev, pipe); |
3933 | ||
a5c4d7bc VS |
3934 | intel_enable_primary_hw_plane(dev_priv, plane, pipe); |
3935 | intel_enable_planes(crtc); | |
d3eedb1a VS |
3936 | /* The fixup needs to happen before cursor is enabled */ |
3937 | if (IS_G4X(dev)) | |
3938 | g4x_fixup_plane(dev_priv, pipe); | |
a5c4d7bc | 3939 | intel_crtc_update_cursor(crtc, true); |
d3eedb1a | 3940 | intel_crtc_dpms_overlay(intel_crtc, true); |
a5c4d7bc VS |
3941 | |
3942 | hsw_enable_ips(intel_crtc); | |
3943 | ||
3944 | mutex_lock(&dev->struct_mutex); | |
3945 | intel_update_fbc(dev); | |
71b1c373 | 3946 | intel_edp_psr_update(dev); |
a5c4d7bc VS |
3947 | mutex_unlock(&dev->struct_mutex); |
3948 | } | |
3949 | ||
d3eedb1a | 3950 | static void intel_crtc_disable_planes(struct drm_crtc *crtc) |
a5c4d7bc VS |
3951 | { |
3952 | struct drm_device *dev = crtc->dev; | |
3953 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3954 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3955 | int pipe = intel_crtc->pipe; | |
3956 | int plane = intel_crtc->plane; | |
3957 | ||
3958 | intel_crtc_wait_for_pending_flips(crtc); | |
a5c4d7bc VS |
3959 | |
3960 | if (dev_priv->fbc.plane == plane) | |
3961 | intel_disable_fbc(dev); | |
3962 | ||
3963 | hsw_disable_ips(intel_crtc); | |
3964 | ||
d3eedb1a | 3965 | intel_crtc_dpms_overlay(intel_crtc, false); |
a5c4d7bc VS |
3966 | intel_crtc_update_cursor(crtc, false); |
3967 | intel_disable_planes(crtc); | |
3968 | intel_disable_primary_hw_plane(dev_priv, plane, pipe); | |
f98551ae VS |
3969 | |
3970 | drm_vblank_off(dev, pipe); | |
a5c4d7bc VS |
3971 | } |
3972 | ||
f67a559d JB |
3973 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
3974 | { | |
3975 | struct drm_device *dev = crtc->dev; | |
3976 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3977 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3978 | struct intel_encoder *encoder; |
f67a559d | 3979 | int pipe = intel_crtc->pipe; |
29407aab | 3980 | enum plane plane = intel_crtc->plane; |
f67a559d | 3981 | |
08a48469 DV |
3982 | WARN_ON(!crtc->enabled); |
3983 | ||
f67a559d JB |
3984 | if (intel_crtc->active) |
3985 | return; | |
3986 | ||
b14b1055 DV |
3987 | if (intel_crtc->config.has_pch_encoder) |
3988 | intel_prepare_shared_dpll(intel_crtc); | |
3989 | ||
29407aab DV |
3990 | if (intel_crtc->config.has_dp_encoder) |
3991 | intel_dp_set_m_n(intel_crtc); | |
3992 | ||
3993 | intel_set_pipe_timings(intel_crtc); | |
3994 | ||
3995 | if (intel_crtc->config.has_pch_encoder) { | |
3996 | intel_cpu_transcoder_set_m_n(intel_crtc, | |
3997 | &intel_crtc->config.fdi_m_n); | |
3998 | } | |
3999 | ||
4000 | ironlake_set_pipeconf(crtc); | |
4001 | ||
4002 | /* Set up the display plane register */ | |
4003 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); | |
4004 | POSTING_READ(DSPCNTR(plane)); | |
4005 | ||
4006 | dev_priv->display.update_primary_plane(crtc, crtc->primary->fb, | |
4007 | crtc->x, crtc->y); | |
4008 | ||
f67a559d | 4009 | intel_crtc->active = true; |
8664281b PZ |
4010 | |
4011 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
4012 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); | |
4013 | ||
f6736a1a | 4014 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4015 | if (encoder->pre_enable) |
4016 | encoder->pre_enable(encoder); | |
f67a559d | 4017 | |
5bfe2ac0 | 4018 | if (intel_crtc->config.has_pch_encoder) { |
fff367c7 DV |
4019 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4020 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4021 | * enabling. */ | |
88cefb6c | 4022 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4023 | } else { |
4024 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4025 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4026 | } | |
f67a559d | 4027 | |
b074cec8 | 4028 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4029 | |
9c54c0dd JB |
4030 | /* |
4031 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4032 | * clocks enabled | |
4033 | */ | |
4034 | intel_crtc_load_lut(crtc); | |
4035 | ||
f37fcc2a | 4036 | intel_update_watermarks(crtc); |
e1fdc473 | 4037 | intel_enable_pipe(intel_crtc); |
f67a559d | 4038 | |
5bfe2ac0 | 4039 | if (intel_crtc->config.has_pch_encoder) |
f67a559d | 4040 | ironlake_pch_enable(crtc); |
c98e9dcf | 4041 | |
fa5c73b1 DV |
4042 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4043 | encoder->enable(encoder); | |
61b77ddd DV |
4044 | |
4045 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4046 | cpt_verify_modeset(dev, intel_crtc->pipe); |
6ce94100 | 4047 | |
d3eedb1a | 4048 | intel_crtc_enable_planes(crtc); |
6be4a607 JB |
4049 | } |
4050 | ||
42db64ef PZ |
4051 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4052 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4053 | { | |
f5adf94e | 4054 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4055 | } |
4056 | ||
e4916946 PZ |
4057 | /* |
4058 | * This implements the workaround described in the "notes" section of the mode | |
4059 | * set sequence documentation. When going from no pipes or single pipe to | |
4060 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
4061 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
4062 | */ | |
4063 | static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) | |
4064 | { | |
4065 | struct drm_device *dev = crtc->base.dev; | |
4066 | struct intel_crtc *crtc_it, *other_active_crtc = NULL; | |
4067 | ||
4068 | /* We want to get the other_active_crtc only if there's only 1 other | |
4069 | * active crtc. */ | |
d3fcc808 | 4070 | for_each_intel_crtc(dev, crtc_it) { |
e4916946 PZ |
4071 | if (!crtc_it->active || crtc_it == crtc) |
4072 | continue; | |
4073 | ||
4074 | if (other_active_crtc) | |
4075 | return; | |
4076 | ||
4077 | other_active_crtc = crtc_it; | |
4078 | } | |
4079 | if (!other_active_crtc) | |
4080 | return; | |
4081 | ||
4082 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4083 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4084 | } | |
4085 | ||
4f771f10 PZ |
4086 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4087 | { | |
4088 | struct drm_device *dev = crtc->dev; | |
4089 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4090 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4091 | struct intel_encoder *encoder; | |
4092 | int pipe = intel_crtc->pipe; | |
229fca97 | 4093 | enum plane plane = intel_crtc->plane; |
4f771f10 PZ |
4094 | |
4095 | WARN_ON(!crtc->enabled); | |
4096 | ||
4097 | if (intel_crtc->active) | |
4098 | return; | |
4099 | ||
229fca97 DV |
4100 | if (intel_crtc->config.has_dp_encoder) |
4101 | intel_dp_set_m_n(intel_crtc); | |
4102 | ||
4103 | intel_set_pipe_timings(intel_crtc); | |
4104 | ||
4105 | if (intel_crtc->config.has_pch_encoder) { | |
4106 | intel_cpu_transcoder_set_m_n(intel_crtc, | |
4107 | &intel_crtc->config.fdi_m_n); | |
4108 | } | |
4109 | ||
4110 | haswell_set_pipeconf(crtc); | |
4111 | ||
4112 | intel_set_pipe_csc(crtc); | |
4113 | ||
4114 | /* Set up the display plane register */ | |
4115 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE); | |
4116 | POSTING_READ(DSPCNTR(plane)); | |
4117 | ||
4118 | dev_priv->display.update_primary_plane(crtc, crtc->primary->fb, | |
4119 | crtc->x, crtc->y); | |
4120 | ||
4f771f10 | 4121 | intel_crtc->active = true; |
8664281b PZ |
4122 | |
4123 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
4124 | if (intel_crtc->config.has_pch_encoder) | |
4125 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); | |
4126 | ||
5bfe2ac0 | 4127 | if (intel_crtc->config.has_pch_encoder) |
04945641 | 4128 | dev_priv->display.fdi_link_train(crtc); |
4f771f10 PZ |
4129 | |
4130 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
4131 | if (encoder->pre_enable) | |
4132 | encoder->pre_enable(encoder); | |
4133 | ||
1f544388 | 4134 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 4135 | |
b074cec8 | 4136 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
4137 | |
4138 | /* | |
4139 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4140 | * clocks enabled | |
4141 | */ | |
4142 | intel_crtc_load_lut(crtc); | |
4143 | ||
1f544388 | 4144 | intel_ddi_set_pipe_settings(crtc); |
8228c251 | 4145 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 4146 | |
f37fcc2a | 4147 | intel_update_watermarks(crtc); |
e1fdc473 | 4148 | intel_enable_pipe(intel_crtc); |
42db64ef | 4149 | |
5bfe2ac0 | 4150 | if (intel_crtc->config.has_pch_encoder) |
1507e5bd | 4151 | lpt_pch_enable(crtc); |
4f771f10 | 4152 | |
8807e55b | 4153 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 4154 | encoder->enable(encoder); |
8807e55b JN |
4155 | intel_opregion_notify_encoder(encoder, true); |
4156 | } | |
4f771f10 | 4157 | |
e4916946 PZ |
4158 | /* If we change the relative order between pipe/planes enabling, we need |
4159 | * to change the workaround. */ | |
4160 | haswell_mode_set_planes_workaround(intel_crtc); | |
d3eedb1a | 4161 | intel_crtc_enable_planes(crtc); |
4f771f10 PZ |
4162 | } |
4163 | ||
3f8dce3a DV |
4164 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
4165 | { | |
4166 | struct drm_device *dev = crtc->base.dev; | |
4167 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4168 | int pipe = crtc->pipe; | |
4169 | ||
4170 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
4171 | * it's in use. The hw state code will make sure we get this right. */ | |
fd4daa9c | 4172 | if (crtc->config.pch_pfit.enabled) { |
3f8dce3a DV |
4173 | I915_WRITE(PF_CTL(pipe), 0); |
4174 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
4175 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
4176 | } | |
4177 | } | |
4178 | ||
6be4a607 JB |
4179 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
4180 | { | |
4181 | struct drm_device *dev = crtc->dev; | |
4182 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4183 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4184 | struct intel_encoder *encoder; |
6be4a607 | 4185 | int pipe = intel_crtc->pipe; |
5eddb70b | 4186 | u32 reg, temp; |
b52eb4dc | 4187 | |
f7abfe8b CW |
4188 | if (!intel_crtc->active) |
4189 | return; | |
4190 | ||
d3eedb1a | 4191 | intel_crtc_disable_planes(crtc); |
a5c4d7bc | 4192 | |
ea9d758d DV |
4193 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4194 | encoder->disable(encoder); | |
4195 | ||
d925c59a DV |
4196 | if (intel_crtc->config.has_pch_encoder) |
4197 | intel_set_pch_fifo_underrun_reporting(dev, pipe, false); | |
4198 | ||
b24e7179 | 4199 | intel_disable_pipe(dev_priv, pipe); |
32f9d658 | 4200 | |
3f8dce3a | 4201 | ironlake_pfit_disable(intel_crtc); |
2c07245f | 4202 | |
bf49ec8c DV |
4203 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4204 | if (encoder->post_disable) | |
4205 | encoder->post_disable(encoder); | |
2c07245f | 4206 | |
d925c59a DV |
4207 | if (intel_crtc->config.has_pch_encoder) { |
4208 | ironlake_fdi_disable(crtc); | |
913d8d11 | 4209 | |
d925c59a DV |
4210 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
4211 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); | |
6be4a607 | 4212 | |
d925c59a DV |
4213 | if (HAS_PCH_CPT(dev)) { |
4214 | /* disable TRANS_DP_CTL */ | |
4215 | reg = TRANS_DP_CTL(pipe); | |
4216 | temp = I915_READ(reg); | |
4217 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
4218 | TRANS_DP_PORT_SEL_MASK); | |
4219 | temp |= TRANS_DP_PORT_SEL_NONE; | |
4220 | I915_WRITE(reg, temp); | |
4221 | ||
4222 | /* disable DPLL_SEL */ | |
4223 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 4224 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 4225 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 4226 | } |
e3421a18 | 4227 | |
d925c59a | 4228 | /* disable PCH DPLL */ |
e72f9fbf | 4229 | intel_disable_shared_dpll(intel_crtc); |
8db9d77b | 4230 | |
d925c59a DV |
4231 | ironlake_fdi_pll_disable(intel_crtc); |
4232 | } | |
6b383a7f | 4233 | |
f7abfe8b | 4234 | intel_crtc->active = false; |
46ba614c | 4235 | intel_update_watermarks(crtc); |
d1ebd816 BW |
4236 | |
4237 | mutex_lock(&dev->struct_mutex); | |
6b383a7f | 4238 | intel_update_fbc(dev); |
71b1c373 | 4239 | intel_edp_psr_update(dev); |
d1ebd816 | 4240 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 4241 | } |
1b3c7a47 | 4242 | |
4f771f10 | 4243 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 4244 | { |
4f771f10 PZ |
4245 | struct drm_device *dev = crtc->dev; |
4246 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 4247 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 PZ |
4248 | struct intel_encoder *encoder; |
4249 | int pipe = intel_crtc->pipe; | |
3b117c8f | 4250 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee7b9f93 | 4251 | |
4f771f10 PZ |
4252 | if (!intel_crtc->active) |
4253 | return; | |
4254 | ||
d3eedb1a | 4255 | intel_crtc_disable_planes(crtc); |
dda9a66a | 4256 | |
8807e55b JN |
4257 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4258 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 4259 | encoder->disable(encoder); |
8807e55b | 4260 | } |
4f771f10 | 4261 | |
8664281b PZ |
4262 | if (intel_crtc->config.has_pch_encoder) |
4263 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); | |
4f771f10 PZ |
4264 | intel_disable_pipe(dev_priv, pipe); |
4265 | ||
ad80a810 | 4266 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 4267 | |
3f8dce3a | 4268 | ironlake_pfit_disable(intel_crtc); |
4f771f10 | 4269 | |
1f544388 | 4270 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 PZ |
4271 | |
4272 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
4273 | if (encoder->post_disable) | |
4274 | encoder->post_disable(encoder); | |
4275 | ||
88adfff1 | 4276 | if (intel_crtc->config.has_pch_encoder) { |
ab4d966c | 4277 | lpt_disable_pch_transcoder(dev_priv); |
8664281b | 4278 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
1ad960f2 | 4279 | intel_ddi_fdi_disable(crtc); |
83616634 | 4280 | } |
4f771f10 PZ |
4281 | |
4282 | intel_crtc->active = false; | |
46ba614c | 4283 | intel_update_watermarks(crtc); |
4f771f10 PZ |
4284 | |
4285 | mutex_lock(&dev->struct_mutex); | |
4286 | intel_update_fbc(dev); | |
71b1c373 | 4287 | intel_edp_psr_update(dev); |
4f771f10 PZ |
4288 | mutex_unlock(&dev->struct_mutex); |
4289 | } | |
4290 | ||
ee7b9f93 JB |
4291 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
4292 | { | |
4293 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e72f9fbf | 4294 | intel_put_shared_dpll(intel_crtc); |
ee7b9f93 JB |
4295 | } |
4296 | ||
6441ab5f PZ |
4297 | static void haswell_crtc_off(struct drm_crtc *crtc) |
4298 | { | |
4299 | intel_ddi_put_crtc_pll(crtc); | |
4300 | } | |
4301 | ||
2dd24552 JB |
4302 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
4303 | { | |
4304 | struct drm_device *dev = crtc->base.dev; | |
4305 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4306 | struct intel_crtc_config *pipe_config = &crtc->config; | |
4307 | ||
328d8e82 | 4308 | if (!crtc->config.gmch_pfit.control) |
2dd24552 JB |
4309 | return; |
4310 | ||
2dd24552 | 4311 | /* |
c0b03411 DV |
4312 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
4313 | * according to register description and PRM. | |
2dd24552 | 4314 | */ |
c0b03411 DV |
4315 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
4316 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 4317 | |
b074cec8 JB |
4318 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
4319 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
4320 | |
4321 | /* Border color in case we don't scale up to the full screen. Black by | |
4322 | * default, change to something else for debugging. */ | |
4323 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
4324 | } |
4325 | ||
77d22dca ID |
4326 | #define for_each_power_domain(domain, mask) \ |
4327 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
4328 | if ((1 << (domain)) & (mask)) | |
4329 | ||
319be8ae ID |
4330 | enum intel_display_power_domain |
4331 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
4332 | { | |
4333 | struct drm_device *dev = intel_encoder->base.dev; | |
4334 | struct intel_digital_port *intel_dig_port; | |
4335 | ||
4336 | switch (intel_encoder->type) { | |
4337 | case INTEL_OUTPUT_UNKNOWN: | |
4338 | /* Only DDI platforms should ever use this output type */ | |
4339 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
4340 | case INTEL_OUTPUT_DISPLAYPORT: | |
4341 | case INTEL_OUTPUT_HDMI: | |
4342 | case INTEL_OUTPUT_EDP: | |
4343 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
4344 | switch (intel_dig_port->port) { | |
4345 | case PORT_A: | |
4346 | return POWER_DOMAIN_PORT_DDI_A_4_LANES; | |
4347 | case PORT_B: | |
4348 | return POWER_DOMAIN_PORT_DDI_B_4_LANES; | |
4349 | case PORT_C: | |
4350 | return POWER_DOMAIN_PORT_DDI_C_4_LANES; | |
4351 | case PORT_D: | |
4352 | return POWER_DOMAIN_PORT_DDI_D_4_LANES; | |
4353 | default: | |
4354 | WARN_ON_ONCE(1); | |
4355 | return POWER_DOMAIN_PORT_OTHER; | |
4356 | } | |
4357 | case INTEL_OUTPUT_ANALOG: | |
4358 | return POWER_DOMAIN_PORT_CRT; | |
4359 | case INTEL_OUTPUT_DSI: | |
4360 | return POWER_DOMAIN_PORT_DSI; | |
4361 | default: | |
4362 | return POWER_DOMAIN_PORT_OTHER; | |
4363 | } | |
4364 | } | |
4365 | ||
4366 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) | |
77d22dca | 4367 | { |
319be8ae ID |
4368 | struct drm_device *dev = crtc->dev; |
4369 | struct intel_encoder *intel_encoder; | |
4370 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4371 | enum pipe pipe = intel_crtc->pipe; | |
4372 | bool pfit_enabled = intel_crtc->config.pch_pfit.enabled; | |
77d22dca ID |
4373 | unsigned long mask; |
4374 | enum transcoder transcoder; | |
4375 | ||
4376 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); | |
4377 | ||
4378 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); | |
4379 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
4380 | if (pfit_enabled) | |
4381 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); | |
4382 | ||
319be8ae ID |
4383 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
4384 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); | |
4385 | ||
77d22dca ID |
4386 | return mask; |
4387 | } | |
4388 | ||
4389 | void intel_display_set_init_power(struct drm_i915_private *dev_priv, | |
4390 | bool enable) | |
4391 | { | |
4392 | if (dev_priv->power_domains.init_power_on == enable) | |
4393 | return; | |
4394 | ||
4395 | if (enable) | |
4396 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); | |
4397 | else | |
4398 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); | |
4399 | ||
4400 | dev_priv->power_domains.init_power_on = enable; | |
4401 | } | |
4402 | ||
4403 | static void modeset_update_crtc_power_domains(struct drm_device *dev) | |
4404 | { | |
4405 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4406 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; | |
4407 | struct intel_crtc *crtc; | |
4408 | ||
4409 | /* | |
4410 | * First get all needed power domains, then put all unneeded, to avoid | |
4411 | * any unnecessary toggling of the power wells. | |
4412 | */ | |
d3fcc808 | 4413 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
4414 | enum intel_display_power_domain domain; |
4415 | ||
4416 | if (!crtc->base.enabled) | |
4417 | continue; | |
4418 | ||
319be8ae | 4419 | pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base); |
77d22dca ID |
4420 | |
4421 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) | |
4422 | intel_display_power_get(dev_priv, domain); | |
4423 | } | |
4424 | ||
d3fcc808 | 4425 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
4426 | enum intel_display_power_domain domain; |
4427 | ||
4428 | for_each_power_domain(domain, crtc->enabled_power_domains) | |
4429 | intel_display_power_put(dev_priv, domain); | |
4430 | ||
4431 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; | |
4432 | } | |
4433 | ||
4434 | intel_display_set_init_power(dev_priv, false); | |
4435 | } | |
4436 | ||
586f49dc | 4437 | int valleyview_get_vco(struct drm_i915_private *dev_priv) |
30a970c6 | 4438 | { |
586f49dc | 4439 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
30a970c6 | 4440 | |
586f49dc JB |
4441 | /* Obtain SKU information */ |
4442 | mutex_lock(&dev_priv->dpio_lock); | |
4443 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
4444 | CCK_FUSE_HPLL_FREQ_MASK; | |
4445 | mutex_unlock(&dev_priv->dpio_lock); | |
30a970c6 | 4446 | |
586f49dc | 4447 | return vco_freq[hpll_freq]; |
30a970c6 JB |
4448 | } |
4449 | ||
4450 | /* Adjust CDclk dividers to allow high res or save power if possible */ | |
4451 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
4452 | { | |
4453 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4454 | u32 val, cmd; | |
4455 | ||
d60c4473 ID |
4456 | WARN_ON(valleyview_cur_cdclk(dev_priv) != dev_priv->vlv_cdclk_freq); |
4457 | dev_priv->vlv_cdclk_freq = cdclk; | |
4458 | ||
30a970c6 JB |
4459 | if (cdclk >= 320) /* jump to highest voltage for 400MHz too */ |
4460 | cmd = 2; | |
4461 | else if (cdclk == 266) | |
4462 | cmd = 1; | |
4463 | else | |
4464 | cmd = 0; | |
4465 | ||
4466 | mutex_lock(&dev_priv->rps.hw_lock); | |
4467 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
4468 | val &= ~DSPFREQGUAR_MASK; | |
4469 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
4470 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
4471 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
4472 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
4473 | 50)) { | |
4474 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
4475 | } | |
4476 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4477 | ||
4478 | if (cdclk == 400) { | |
4479 | u32 divider, vco; | |
4480 | ||
4481 | vco = valleyview_get_vco(dev_priv); | |
4482 | divider = ((vco << 1) / cdclk) - 1; | |
4483 | ||
4484 | mutex_lock(&dev_priv->dpio_lock); | |
4485 | /* adjust cdclk divider */ | |
4486 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
4487 | val &= ~0xf; | |
4488 | val |= divider; | |
4489 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
4490 | mutex_unlock(&dev_priv->dpio_lock); | |
4491 | } | |
4492 | ||
4493 | mutex_lock(&dev_priv->dpio_lock); | |
4494 | /* adjust self-refresh exit latency value */ | |
4495 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
4496 | val &= ~0x7f; | |
4497 | ||
4498 | /* | |
4499 | * For high bandwidth configs, we set a higher latency in the bunit | |
4500 | * so that the core display fetch happens in time to avoid underruns. | |
4501 | */ | |
4502 | if (cdclk == 400) | |
4503 | val |= 4500 / 250; /* 4.5 usec */ | |
4504 | else | |
4505 | val |= 3000 / 250; /* 3.0 usec */ | |
4506 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
4507 | mutex_unlock(&dev_priv->dpio_lock); | |
4508 | ||
4509 | /* Since we changed the CDclk, we need to update the GMBUSFREQ too */ | |
4510 | intel_i2c_reset(dev); | |
4511 | } | |
4512 | ||
d60c4473 | 4513 | int valleyview_cur_cdclk(struct drm_i915_private *dev_priv) |
30a970c6 JB |
4514 | { |
4515 | int cur_cdclk, vco; | |
4516 | int divider; | |
4517 | ||
4518 | vco = valleyview_get_vco(dev_priv); | |
4519 | ||
4520 | mutex_lock(&dev_priv->dpio_lock); | |
4521 | divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
4522 | mutex_unlock(&dev_priv->dpio_lock); | |
4523 | ||
4524 | divider &= 0xf; | |
4525 | ||
4526 | cur_cdclk = (vco << 1) / (divider + 1); | |
4527 | ||
4528 | return cur_cdclk; | |
4529 | } | |
4530 | ||
4531 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, | |
4532 | int max_pixclk) | |
4533 | { | |
30a970c6 JB |
4534 | /* |
4535 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
4536 | * 200MHz | |
4537 | * 267MHz | |
4538 | * 320MHz | |
4539 | * 400MHz | |
4540 | * So we check to see whether we're above 90% of the lower bin and | |
4541 | * adjust if needed. | |
4542 | */ | |
4543 | if (max_pixclk > 288000) { | |
4544 | return 400; | |
4545 | } else if (max_pixclk > 240000) { | |
4546 | return 320; | |
4547 | } else | |
4548 | return 266; | |
4549 | /* Looks like the 200MHz CDclk freq doesn't work on some configs */ | |
4550 | } | |
4551 | ||
2f2d7aa1 VS |
4552 | /* compute the max pixel clock for new configuration */ |
4553 | static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv) | |
30a970c6 JB |
4554 | { |
4555 | struct drm_device *dev = dev_priv->dev; | |
4556 | struct intel_crtc *intel_crtc; | |
4557 | int max_pixclk = 0; | |
4558 | ||
d3fcc808 | 4559 | for_each_intel_crtc(dev, intel_crtc) { |
2f2d7aa1 | 4560 | if (intel_crtc->new_enabled) |
30a970c6 | 4561 | max_pixclk = max(max_pixclk, |
2f2d7aa1 | 4562 | intel_crtc->new_config->adjusted_mode.crtc_clock); |
30a970c6 JB |
4563 | } |
4564 | ||
4565 | return max_pixclk; | |
4566 | } | |
4567 | ||
4568 | static void valleyview_modeset_global_pipes(struct drm_device *dev, | |
2f2d7aa1 | 4569 | unsigned *prepare_pipes) |
30a970c6 JB |
4570 | { |
4571 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4572 | struct intel_crtc *intel_crtc; | |
2f2d7aa1 | 4573 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 | 4574 | |
d60c4473 ID |
4575 | if (valleyview_calc_cdclk(dev_priv, max_pixclk) == |
4576 | dev_priv->vlv_cdclk_freq) | |
30a970c6 JB |
4577 | return; |
4578 | ||
2f2d7aa1 | 4579 | /* disable/enable all currently active pipes while we change cdclk */ |
d3fcc808 | 4580 | for_each_intel_crtc(dev, intel_crtc) |
30a970c6 JB |
4581 | if (intel_crtc->base.enabled) |
4582 | *prepare_pipes |= (1 << intel_crtc->pipe); | |
4583 | } | |
4584 | ||
4585 | static void valleyview_modeset_global_resources(struct drm_device *dev) | |
4586 | { | |
4587 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2f2d7aa1 | 4588 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 JB |
4589 | int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); |
4590 | ||
d60c4473 | 4591 | if (req_cdclk != dev_priv->vlv_cdclk_freq) |
30a970c6 | 4592 | valleyview_set_cdclk(dev, req_cdclk); |
77961eb9 | 4593 | modeset_update_crtc_power_domains(dev); |
30a970c6 JB |
4594 | } |
4595 | ||
89b667f8 JB |
4596 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
4597 | { | |
4598 | struct drm_device *dev = crtc->dev; | |
5b18e57c | 4599 | struct drm_i915_private *dev_priv = dev->dev_private; |
89b667f8 JB |
4600 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4601 | struct intel_encoder *encoder; | |
4602 | int pipe = intel_crtc->pipe; | |
5b18e57c | 4603 | int plane = intel_crtc->plane; |
23538ef1 | 4604 | bool is_dsi; |
5b18e57c | 4605 | u32 dspcntr; |
89b667f8 JB |
4606 | |
4607 | WARN_ON(!crtc->enabled); | |
4608 | ||
4609 | if (intel_crtc->active) | |
4610 | return; | |
4611 | ||
bdd4b6a6 DV |
4612 | vlv_prepare_pll(intel_crtc); |
4613 | ||
5b18e57c DV |
4614 | /* Set up the display plane register */ |
4615 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
4616 | ||
4617 | if (intel_crtc->config.has_dp_encoder) | |
4618 | intel_dp_set_m_n(intel_crtc); | |
4619 | ||
4620 | intel_set_pipe_timings(intel_crtc); | |
4621 | ||
4622 | /* pipesrc and dspsize control the size that is scaled from, | |
4623 | * which should always be the user's requested size. | |
4624 | */ | |
4625 | I915_WRITE(DSPSIZE(plane), | |
4626 | ((intel_crtc->config.pipe_src_h - 1) << 16) | | |
4627 | (intel_crtc->config.pipe_src_w - 1)); | |
4628 | I915_WRITE(DSPPOS(plane), 0); | |
4629 | ||
4630 | i9xx_set_pipeconf(intel_crtc); | |
4631 | ||
4632 | I915_WRITE(DSPCNTR(plane), dspcntr); | |
4633 | POSTING_READ(DSPCNTR(plane)); | |
4634 | ||
4635 | dev_priv->display.update_primary_plane(crtc, crtc->primary->fb, | |
4636 | crtc->x, crtc->y); | |
4637 | ||
89b667f8 | 4638 | intel_crtc->active = true; |
89b667f8 | 4639 | |
4a3436e8 VS |
4640 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
4641 | ||
89b667f8 JB |
4642 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4643 | if (encoder->pre_pll_enable) | |
4644 | encoder->pre_pll_enable(encoder); | |
4645 | ||
23538ef1 JN |
4646 | is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI); |
4647 | ||
9d556c99 CML |
4648 | if (!is_dsi) { |
4649 | if (IS_CHERRYVIEW(dev)) | |
4650 | chv_enable_pll(intel_crtc); | |
4651 | else | |
4652 | vlv_enable_pll(intel_crtc); | |
4653 | } | |
89b667f8 JB |
4654 | |
4655 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
4656 | if (encoder->pre_enable) | |
4657 | encoder->pre_enable(encoder); | |
4658 | ||
2dd24552 JB |
4659 | i9xx_pfit_enable(intel_crtc); |
4660 | ||
63cbb074 VS |
4661 | intel_crtc_load_lut(crtc); |
4662 | ||
f37fcc2a | 4663 | intel_update_watermarks(crtc); |
e1fdc473 | 4664 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 4665 | |
5004945f JN |
4666 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4667 | encoder->enable(encoder); | |
9ab0460b VS |
4668 | |
4669 | intel_crtc_enable_planes(crtc); | |
d40d9187 | 4670 | |
56b80e1f VS |
4671 | /* Underruns don't raise interrupts, so check manually. */ |
4672 | i9xx_check_fifo_underruns(dev); | |
89b667f8 JB |
4673 | } |
4674 | ||
f13c2ef3 DV |
4675 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
4676 | { | |
4677 | struct drm_device *dev = crtc->base.dev; | |
4678 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4679 | ||
4680 | I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0); | |
4681 | I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1); | |
4682 | } | |
4683 | ||
0b8765c6 | 4684 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
4685 | { |
4686 | struct drm_device *dev = crtc->dev; | |
5b18e57c | 4687 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 4688 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 4689 | struct intel_encoder *encoder; |
79e53945 | 4690 | int pipe = intel_crtc->pipe; |
5b18e57c DV |
4691 | int plane = intel_crtc->plane; |
4692 | u32 dspcntr; | |
79e53945 | 4693 | |
08a48469 DV |
4694 | WARN_ON(!crtc->enabled); |
4695 | ||
f7abfe8b CW |
4696 | if (intel_crtc->active) |
4697 | return; | |
4698 | ||
f13c2ef3 DV |
4699 | i9xx_set_pll_dividers(intel_crtc); |
4700 | ||
5b18e57c DV |
4701 | /* Set up the display plane register */ |
4702 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
4703 | ||
4704 | if (pipe == 0) | |
4705 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; | |
4706 | else | |
4707 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
4708 | ||
4709 | if (intel_crtc->config.has_dp_encoder) | |
4710 | intel_dp_set_m_n(intel_crtc); | |
4711 | ||
4712 | intel_set_pipe_timings(intel_crtc); | |
4713 | ||
4714 | /* pipesrc and dspsize control the size that is scaled from, | |
4715 | * which should always be the user's requested size. | |
4716 | */ | |
4717 | I915_WRITE(DSPSIZE(plane), | |
4718 | ((intel_crtc->config.pipe_src_h - 1) << 16) | | |
4719 | (intel_crtc->config.pipe_src_w - 1)); | |
4720 | I915_WRITE(DSPPOS(plane), 0); | |
4721 | ||
4722 | i9xx_set_pipeconf(intel_crtc); | |
4723 | ||
4724 | I915_WRITE(DSPCNTR(plane), dspcntr); | |
4725 | POSTING_READ(DSPCNTR(plane)); | |
4726 | ||
4727 | dev_priv->display.update_primary_plane(crtc, crtc->primary->fb, | |
4728 | crtc->x, crtc->y); | |
4729 | ||
f7abfe8b | 4730 | intel_crtc->active = true; |
6b383a7f | 4731 | |
4a3436e8 VS |
4732 | if (!IS_GEN2(dev)) |
4733 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
4734 | ||
9d6d9f19 MK |
4735 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4736 | if (encoder->pre_enable) | |
4737 | encoder->pre_enable(encoder); | |
4738 | ||
f6736a1a DV |
4739 | i9xx_enable_pll(intel_crtc); |
4740 | ||
2dd24552 JB |
4741 | i9xx_pfit_enable(intel_crtc); |
4742 | ||
63cbb074 VS |
4743 | intel_crtc_load_lut(crtc); |
4744 | ||
f37fcc2a | 4745 | intel_update_watermarks(crtc); |
e1fdc473 | 4746 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 4747 | |
fa5c73b1 DV |
4748 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4749 | encoder->enable(encoder); | |
9ab0460b VS |
4750 | |
4751 | intel_crtc_enable_planes(crtc); | |
d40d9187 | 4752 | |
4a3436e8 VS |
4753 | /* |
4754 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4755 | * So don't enable underrun reporting before at least some planes | |
4756 | * are enabled. | |
4757 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4758 | * but leave the pipe running. | |
4759 | */ | |
4760 | if (IS_GEN2(dev)) | |
4761 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
4762 | ||
56b80e1f VS |
4763 | /* Underruns don't raise interrupts, so check manually. */ |
4764 | i9xx_check_fifo_underruns(dev); | |
0b8765c6 | 4765 | } |
79e53945 | 4766 | |
87476d63 DV |
4767 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
4768 | { | |
4769 | struct drm_device *dev = crtc->base.dev; | |
4770 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 4771 | |
328d8e82 DV |
4772 | if (!crtc->config.gmch_pfit.control) |
4773 | return; | |
87476d63 | 4774 | |
328d8e82 | 4775 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 4776 | |
328d8e82 DV |
4777 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
4778 | I915_READ(PFIT_CONTROL)); | |
4779 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
4780 | } |
4781 | ||
0b8765c6 JB |
4782 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
4783 | { | |
4784 | struct drm_device *dev = crtc->dev; | |
4785 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4786 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4787 | struct intel_encoder *encoder; |
0b8765c6 | 4788 | int pipe = intel_crtc->pipe; |
ef9c3aee | 4789 | |
f7abfe8b CW |
4790 | if (!intel_crtc->active) |
4791 | return; | |
4792 | ||
4a3436e8 VS |
4793 | /* |
4794 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4795 | * So diasble underrun reporting before all the planes get disabled. | |
4796 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4797 | * but leave the pipe running. | |
4798 | */ | |
4799 | if (IS_GEN2(dev)) | |
4800 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false); | |
4801 | ||
9ab0460b VS |
4802 | intel_crtc_disable_planes(crtc); |
4803 | ||
ea9d758d DV |
4804 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4805 | encoder->disable(encoder); | |
4806 | ||
6304cd91 VS |
4807 | /* |
4808 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
4809 | * wait for planes to fully turn off before disabling the pipe. | |
4810 | */ | |
4811 | if (IS_GEN2(dev)) | |
4812 | intel_wait_for_vblank(dev, pipe); | |
4813 | ||
b24e7179 | 4814 | intel_disable_pipe(dev_priv, pipe); |
24a1f16d | 4815 | |
87476d63 | 4816 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 4817 | |
89b667f8 JB |
4818 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4819 | if (encoder->post_disable) | |
4820 | encoder->post_disable(encoder); | |
4821 | ||
076ed3b2 CML |
4822 | if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) { |
4823 | if (IS_CHERRYVIEW(dev)) | |
4824 | chv_disable_pll(dev_priv, pipe); | |
4825 | else if (IS_VALLEYVIEW(dev)) | |
4826 | vlv_disable_pll(dev_priv, pipe); | |
4827 | else | |
4828 | i9xx_disable_pll(dev_priv, pipe); | |
4829 | } | |
0b8765c6 | 4830 | |
4a3436e8 VS |
4831 | if (!IS_GEN2(dev)) |
4832 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false); | |
4833 | ||
f7abfe8b | 4834 | intel_crtc->active = false; |
46ba614c | 4835 | intel_update_watermarks(crtc); |
f37fcc2a | 4836 | |
efa9624e | 4837 | mutex_lock(&dev->struct_mutex); |
6b383a7f | 4838 | intel_update_fbc(dev); |
71b1c373 | 4839 | intel_edp_psr_update(dev); |
efa9624e | 4840 | mutex_unlock(&dev->struct_mutex); |
0b8765c6 JB |
4841 | } |
4842 | ||
ee7b9f93 JB |
4843 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
4844 | { | |
4845 | } | |
4846 | ||
976f8a20 DV |
4847 | static void intel_crtc_update_sarea(struct drm_crtc *crtc, |
4848 | bool enabled) | |
2c07245f ZW |
4849 | { |
4850 | struct drm_device *dev = crtc->dev; | |
4851 | struct drm_i915_master_private *master_priv; | |
4852 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4853 | int pipe = intel_crtc->pipe; | |
79e53945 JB |
4854 | |
4855 | if (!dev->primary->master) | |
4856 | return; | |
4857 | ||
4858 | master_priv = dev->primary->master->driver_priv; | |
4859 | if (!master_priv->sarea_priv) | |
4860 | return; | |
4861 | ||
79e53945 JB |
4862 | switch (pipe) { |
4863 | case 0: | |
4864 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
4865 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
4866 | break; | |
4867 | case 1: | |
4868 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
4869 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
4870 | break; | |
4871 | default: | |
9db4a9c7 | 4872 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
79e53945 JB |
4873 | break; |
4874 | } | |
79e53945 JB |
4875 | } |
4876 | ||
976f8a20 DV |
4877 | /** |
4878 | * Sets the power management mode of the pipe and plane. | |
4879 | */ | |
4880 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
4881 | { | |
4882 | struct drm_device *dev = crtc->dev; | |
4883 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0e572fe7 | 4884 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
976f8a20 | 4885 | struct intel_encoder *intel_encoder; |
0e572fe7 DV |
4886 | enum intel_display_power_domain domain; |
4887 | unsigned long domains; | |
976f8a20 DV |
4888 | bool enable = false; |
4889 | ||
4890 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
4891 | enable |= intel_encoder->connectors_active; | |
4892 | ||
0e572fe7 DV |
4893 | if (enable) { |
4894 | if (!intel_crtc->active) { | |
4895 | /* | |
4896 | * FIXME: DDI plls and relevant code isn't converted | |
4897 | * yet, so do runtime PM for DPMS only for all other | |
4898 | * platforms for now. | |
4899 | */ | |
4900 | if (!HAS_DDI(dev)) { | |
4901 | domains = get_crtc_power_domains(crtc); | |
4902 | for_each_power_domain(domain, domains) | |
4903 | intel_display_power_get(dev_priv, domain); | |
4904 | intel_crtc->enabled_power_domains = domains; | |
4905 | } | |
4906 | ||
4907 | dev_priv->display.crtc_enable(crtc); | |
4908 | } | |
4909 | } else { | |
4910 | if (intel_crtc->active) { | |
4911 | dev_priv->display.crtc_disable(crtc); | |
4912 | ||
4913 | if (!HAS_DDI(dev)) { | |
4914 | domains = intel_crtc->enabled_power_domains; | |
4915 | for_each_power_domain(domain, domains) | |
4916 | intel_display_power_put(dev_priv, domain); | |
4917 | intel_crtc->enabled_power_domains = 0; | |
4918 | } | |
4919 | } | |
4920 | } | |
976f8a20 DV |
4921 | |
4922 | intel_crtc_update_sarea(crtc, enable); | |
4923 | } | |
4924 | ||
cdd59983 CW |
4925 | static void intel_crtc_disable(struct drm_crtc *crtc) |
4926 | { | |
cdd59983 | 4927 | struct drm_device *dev = crtc->dev; |
976f8a20 | 4928 | struct drm_connector *connector; |
ee7b9f93 | 4929 | struct drm_i915_private *dev_priv = dev->dev_private; |
cdd59983 | 4930 | |
976f8a20 DV |
4931 | /* crtc should still be enabled when we disable it. */ |
4932 | WARN_ON(!crtc->enabled); | |
4933 | ||
4934 | dev_priv->display.crtc_disable(crtc); | |
4935 | intel_crtc_update_sarea(crtc, false); | |
ee7b9f93 JB |
4936 | dev_priv->display.off(crtc); |
4937 | ||
931872fc | 4938 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
93ce0ba6 | 4939 | assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe); |
931872fc | 4940 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); |
cdd59983 | 4941 | |
f4510a27 | 4942 | if (crtc->primary->fb) { |
cdd59983 | 4943 | mutex_lock(&dev->struct_mutex); |
f4510a27 | 4944 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->primary->fb)->obj); |
cdd59983 | 4945 | mutex_unlock(&dev->struct_mutex); |
f4510a27 | 4946 | crtc->primary->fb = NULL; |
976f8a20 DV |
4947 | } |
4948 | ||
4949 | /* Update computed state. */ | |
4950 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4951 | if (!connector->encoder || !connector->encoder->crtc) | |
4952 | continue; | |
4953 | ||
4954 | if (connector->encoder->crtc != crtc) | |
4955 | continue; | |
4956 | ||
4957 | connector->dpms = DRM_MODE_DPMS_OFF; | |
4958 | to_intel_encoder(connector->encoder)->connectors_active = false; | |
cdd59983 CW |
4959 | } |
4960 | } | |
4961 | ||
ea5b213a | 4962 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 4963 | { |
4ef69c7a | 4964 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 4965 | |
ea5b213a CW |
4966 | drm_encoder_cleanup(encoder); |
4967 | kfree(intel_encoder); | |
7e7d76c3 JB |
4968 | } |
4969 | ||
9237329d | 4970 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
5ab432ef DV |
4971 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
4972 | * state of the entire output pipe. */ | |
9237329d | 4973 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
7e7d76c3 | 4974 | { |
5ab432ef DV |
4975 | if (mode == DRM_MODE_DPMS_ON) { |
4976 | encoder->connectors_active = true; | |
4977 | ||
b2cabb0e | 4978 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
4979 | } else { |
4980 | encoder->connectors_active = false; | |
4981 | ||
b2cabb0e | 4982 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 4983 | } |
79e53945 JB |
4984 | } |
4985 | ||
0a91ca29 DV |
4986 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
4987 | * internal consistency). */ | |
b980514c | 4988 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 4989 | { |
0a91ca29 DV |
4990 | if (connector->get_hw_state(connector)) { |
4991 | struct intel_encoder *encoder = connector->encoder; | |
4992 | struct drm_crtc *crtc; | |
4993 | bool encoder_enabled; | |
4994 | enum pipe pipe; | |
4995 | ||
4996 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
4997 | connector->base.base.id, | |
c23cc417 | 4998 | connector->base.name); |
0a91ca29 DV |
4999 | |
5000 | WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, | |
5001 | "wrong connector dpms state\n"); | |
5002 | WARN(connector->base.encoder != &encoder->base, | |
5003 | "active connector not linked to encoder\n"); | |
5004 | WARN(!encoder->connectors_active, | |
5005 | "encoder->connectors_active not set\n"); | |
5006 | ||
5007 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
5008 | WARN(!encoder_enabled, "encoder not enabled\n"); | |
5009 | if (WARN_ON(!encoder->base.crtc)) | |
5010 | return; | |
5011 | ||
5012 | crtc = encoder->base.crtc; | |
5013 | ||
5014 | WARN(!crtc->enabled, "crtc not enabled\n"); | |
5015 | WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); | |
5016 | WARN(pipe != to_intel_crtc(crtc)->pipe, | |
5017 | "encoder active on the wrong pipe\n"); | |
5018 | } | |
79e53945 JB |
5019 | } |
5020 | ||
5ab432ef DV |
5021 | /* Even simpler default implementation, if there's really no special case to |
5022 | * consider. */ | |
5023 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 5024 | { |
5ab432ef DV |
5025 | /* All the simple cases only support two dpms states. */ |
5026 | if (mode != DRM_MODE_DPMS_ON) | |
5027 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 5028 | |
5ab432ef DV |
5029 | if (mode == connector->dpms) |
5030 | return; | |
5031 | ||
5032 | connector->dpms = mode; | |
5033 | ||
5034 | /* Only need to change hw state when actually enabled */ | |
c9976dcf CW |
5035 | if (connector->encoder) |
5036 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); | |
0a91ca29 | 5037 | |
b980514c | 5038 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
5039 | } |
5040 | ||
f0947c37 DV |
5041 | /* Simple connector->get_hw_state implementation for encoders that support only |
5042 | * one connector and no cloning and hence the encoder state determines the state | |
5043 | * of the connector. */ | |
5044 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 5045 | { |
24929352 | 5046 | enum pipe pipe = 0; |
f0947c37 | 5047 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 5048 | |
f0947c37 | 5049 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
5050 | } |
5051 | ||
1857e1da DV |
5052 | static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5053 | struct intel_crtc_config *pipe_config) | |
5054 | { | |
5055 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5056 | struct intel_crtc *pipe_B_crtc = | |
5057 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
5058 | ||
5059 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", | |
5060 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5061 | if (pipe_config->fdi_lanes > 4) { | |
5062 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
5063 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5064 | return false; | |
5065 | } | |
5066 | ||
bafb6553 | 5067 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
5068 | if (pipe_config->fdi_lanes > 2) { |
5069 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
5070 | pipe_config->fdi_lanes); | |
5071 | return false; | |
5072 | } else { | |
5073 | return true; | |
5074 | } | |
5075 | } | |
5076 | ||
5077 | if (INTEL_INFO(dev)->num_pipes == 2) | |
5078 | return true; | |
5079 | ||
5080 | /* Ivybridge 3 pipe is really complicated */ | |
5081 | switch (pipe) { | |
5082 | case PIPE_A: | |
5083 | return true; | |
5084 | case PIPE_B: | |
5085 | if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && | |
5086 | pipe_config->fdi_lanes > 2) { | |
5087 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
5088 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5089 | return false; | |
5090 | } | |
5091 | return true; | |
5092 | case PIPE_C: | |
1e833f40 | 5093 | if (!pipe_has_enabled_pch(pipe_B_crtc) || |
1857e1da DV |
5094 | pipe_B_crtc->config.fdi_lanes <= 2) { |
5095 | if (pipe_config->fdi_lanes > 2) { | |
5096 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
5097 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5098 | return false; | |
5099 | } | |
5100 | } else { | |
5101 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); | |
5102 | return false; | |
5103 | } | |
5104 | return true; | |
5105 | default: | |
5106 | BUG(); | |
5107 | } | |
5108 | } | |
5109 | ||
e29c22c0 DV |
5110 | #define RETRY 1 |
5111 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5112 | struct intel_crtc_config *pipe_config) | |
877d48d5 | 5113 | { |
1857e1da | 5114 | struct drm_device *dev = intel_crtc->base.dev; |
877d48d5 | 5115 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
ff9a6750 | 5116 | int lane, link_bw, fdi_dotclock; |
e29c22c0 | 5117 | bool setup_ok, needs_recompute = false; |
877d48d5 | 5118 | |
e29c22c0 | 5119 | retry: |
877d48d5 DV |
5120 | /* FDI is a binary signal running at ~2.7GHz, encoding |
5121 | * each output octet as 10 bits. The actual frequency | |
5122 | * is stored as a divider into a 100MHz clock, and the | |
5123 | * mode pixel clock is stored in units of 1KHz. | |
5124 | * Hence the bw of each lane in terms of the mode signal | |
5125 | * is: | |
5126 | */ | |
5127 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
5128 | ||
241bfc38 | 5129 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 5130 | |
2bd89a07 | 5131 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
5132 | pipe_config->pipe_bpp); |
5133 | ||
5134 | pipe_config->fdi_lanes = lane; | |
5135 | ||
2bd89a07 | 5136 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 5137 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 5138 | |
e29c22c0 DV |
5139 | setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
5140 | intel_crtc->pipe, pipe_config); | |
5141 | if (!setup_ok && pipe_config->pipe_bpp > 6*3) { | |
5142 | pipe_config->pipe_bpp -= 2*3; | |
5143 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
5144 | pipe_config->pipe_bpp); | |
5145 | needs_recompute = true; | |
5146 | pipe_config->bw_constrained = true; | |
5147 | ||
5148 | goto retry; | |
5149 | } | |
5150 | ||
5151 | if (needs_recompute) | |
5152 | return RETRY; | |
5153 | ||
5154 | return setup_ok ? 0 : -EINVAL; | |
877d48d5 DV |
5155 | } |
5156 | ||
42db64ef PZ |
5157 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5158 | struct intel_crtc_config *pipe_config) | |
5159 | { | |
d330a953 | 5160 | pipe_config->ips_enabled = i915.enable_ips && |
3c4ca58c | 5161 | hsw_crtc_supports_ips(crtc) && |
b6dfdc9b | 5162 | pipe_config->pipe_bpp <= 24; |
42db64ef PZ |
5163 | } |
5164 | ||
a43f6e0f | 5165 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
e29c22c0 | 5166 | struct intel_crtc_config *pipe_config) |
79e53945 | 5167 | { |
a43f6e0f | 5168 | struct drm_device *dev = crtc->base.dev; |
b8cecdf5 | 5169 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
89749350 | 5170 | |
ad3a4479 | 5171 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 VS |
5172 | if (INTEL_INFO(dev)->gen < 4) { |
5173 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5174 | int clock_limit = | |
5175 | dev_priv->display.get_display_clock_speed(dev); | |
5176 | ||
5177 | /* | |
5178 | * Enable pixel doubling when the dot clock | |
5179 | * is > 90% of the (display) core speed. | |
5180 | * | |
b397c96b VS |
5181 | * GDG double wide on either pipe, |
5182 | * otherwise pipe A only. | |
cf532bb2 | 5183 | */ |
b397c96b | 5184 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
241bfc38 | 5185 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
ad3a4479 | 5186 | clock_limit *= 2; |
cf532bb2 | 5187 | pipe_config->double_wide = true; |
ad3a4479 VS |
5188 | } |
5189 | ||
241bfc38 | 5190 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
e29c22c0 | 5191 | return -EINVAL; |
2c07245f | 5192 | } |
89749350 | 5193 | |
1d1d0e27 VS |
5194 | /* |
5195 | * Pipe horizontal size must be even in: | |
5196 | * - DVO ganged mode | |
5197 | * - LVDS dual channel mode | |
5198 | * - Double wide pipe | |
5199 | */ | |
5200 | if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && | |
5201 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) | |
5202 | pipe_config->pipe_src_w &= ~1; | |
5203 | ||
8693a824 DL |
5204 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
5205 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
5206 | */ |
5207 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
5208 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
e29c22c0 | 5209 | return -EINVAL; |
44f46b42 | 5210 | |
bd080ee5 | 5211 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { |
5d2d38dd | 5212 | pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ |
bd080ee5 | 5213 | } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { |
5d2d38dd DV |
5214 | /* only a 8bpc pipe, with 6bpc dither through the panel fitter |
5215 | * for lvds. */ | |
5216 | pipe_config->pipe_bpp = 8*3; | |
5217 | } | |
5218 | ||
f5adf94e | 5219 | if (HAS_IPS(dev)) |
a43f6e0f DV |
5220 | hsw_compute_ips_config(crtc, pipe_config); |
5221 | ||
5222 | /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old | |
5223 | * clock survives for now. */ | |
5224 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
5225 | pipe_config->shared_dpll = crtc->config.shared_dpll; | |
42db64ef | 5226 | |
877d48d5 | 5227 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 5228 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 5229 | |
e29c22c0 | 5230 | return 0; |
79e53945 JB |
5231 | } |
5232 | ||
25eb05fc JB |
5233 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
5234 | { | |
5235 | return 400000; /* FIXME */ | |
5236 | } | |
5237 | ||
e70236a8 JB |
5238 | static int i945_get_display_clock_speed(struct drm_device *dev) |
5239 | { | |
5240 | return 400000; | |
5241 | } | |
79e53945 | 5242 | |
e70236a8 | 5243 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 5244 | { |
e70236a8 JB |
5245 | return 333000; |
5246 | } | |
79e53945 | 5247 | |
e70236a8 JB |
5248 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
5249 | { | |
5250 | return 200000; | |
5251 | } | |
79e53945 | 5252 | |
257a7ffc DV |
5253 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
5254 | { | |
5255 | u16 gcfgc = 0; | |
5256 | ||
5257 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
5258 | ||
5259 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
5260 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
5261 | return 267000; | |
5262 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: | |
5263 | return 333000; | |
5264 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: | |
5265 | return 444000; | |
5266 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: | |
5267 | return 200000; | |
5268 | default: | |
5269 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
5270 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
5271 | return 133000; | |
5272 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: | |
5273 | return 167000; | |
5274 | } | |
5275 | } | |
5276 | ||
e70236a8 JB |
5277 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
5278 | { | |
5279 | u16 gcfgc = 0; | |
79e53945 | 5280 | |
e70236a8 JB |
5281 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
5282 | ||
5283 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
5284 | return 133000; | |
5285 | else { | |
5286 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
5287 | case GC_DISPLAY_CLOCK_333_MHZ: | |
5288 | return 333000; | |
5289 | default: | |
5290 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
5291 | return 190000; | |
79e53945 | 5292 | } |
e70236a8 JB |
5293 | } |
5294 | } | |
5295 | ||
5296 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
5297 | { | |
5298 | return 266000; | |
5299 | } | |
5300 | ||
5301 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
5302 | { | |
5303 | u16 hpllcc = 0; | |
5304 | /* Assume that the hardware is in the high speed state. This | |
5305 | * should be the default. | |
5306 | */ | |
5307 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
5308 | case GC_CLOCK_133_200: | |
5309 | case GC_CLOCK_100_200: | |
5310 | return 200000; | |
5311 | case GC_CLOCK_166_250: | |
5312 | return 250000; | |
5313 | case GC_CLOCK_100_133: | |
79e53945 | 5314 | return 133000; |
e70236a8 | 5315 | } |
79e53945 | 5316 | |
e70236a8 JB |
5317 | /* Shouldn't happen */ |
5318 | return 0; | |
5319 | } | |
79e53945 | 5320 | |
e70236a8 JB |
5321 | static int i830_get_display_clock_speed(struct drm_device *dev) |
5322 | { | |
5323 | return 133000; | |
79e53945 JB |
5324 | } |
5325 | ||
2c07245f | 5326 | static void |
a65851af | 5327 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 5328 | { |
a65851af VS |
5329 | while (*num > DATA_LINK_M_N_MASK || |
5330 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
5331 | *num >>= 1; |
5332 | *den >>= 1; | |
5333 | } | |
5334 | } | |
5335 | ||
a65851af VS |
5336 | static void compute_m_n(unsigned int m, unsigned int n, |
5337 | uint32_t *ret_m, uint32_t *ret_n) | |
5338 | { | |
5339 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
5340 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
5341 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
5342 | } | |
5343 | ||
e69d0bc1 DV |
5344 | void |
5345 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
5346 | int pixel_clock, int link_clock, | |
5347 | struct intel_link_m_n *m_n) | |
2c07245f | 5348 | { |
e69d0bc1 | 5349 | m_n->tu = 64; |
a65851af VS |
5350 | |
5351 | compute_m_n(bits_per_pixel * pixel_clock, | |
5352 | link_clock * nlanes * 8, | |
5353 | &m_n->gmch_m, &m_n->gmch_n); | |
5354 | ||
5355 | compute_m_n(pixel_clock, link_clock, | |
5356 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
5357 | } |
5358 | ||
a7615030 CW |
5359 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
5360 | { | |
d330a953 JN |
5361 | if (i915.panel_use_ssc >= 0) |
5362 | return i915.panel_use_ssc != 0; | |
41aa3448 | 5363 | return dev_priv->vbt.lvds_use_ssc |
435793df | 5364 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
5365 | } |
5366 | ||
c65d77d8 JB |
5367 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
5368 | { | |
5369 | struct drm_device *dev = crtc->dev; | |
5370 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5371 | int refclk; | |
5372 | ||
a0c4da24 | 5373 | if (IS_VALLEYVIEW(dev)) { |
9a0ea498 | 5374 | refclk = 100000; |
a0c4da24 | 5375 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 5376 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
5377 | refclk = dev_priv->vbt.lvds_ssc_freq; |
5378 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
5379 | } else if (!IS_GEN2(dev)) { |
5380 | refclk = 96000; | |
5381 | } else { | |
5382 | refclk = 48000; | |
5383 | } | |
5384 | ||
5385 | return refclk; | |
5386 | } | |
5387 | ||
7429e9d4 | 5388 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 5389 | { |
7df00d7a | 5390 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 5391 | } |
f47709a9 | 5392 | |
7429e9d4 DV |
5393 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
5394 | { | |
5395 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
5396 | } |
5397 | ||
f47709a9 | 5398 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
a7516a05 JB |
5399 | intel_clock_t *reduced_clock) |
5400 | { | |
f47709a9 | 5401 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
5402 | u32 fp, fp2 = 0; |
5403 | ||
5404 | if (IS_PINEVIEW(dev)) { | |
7429e9d4 | 5405 | fp = pnv_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 5406 | if (reduced_clock) |
7429e9d4 | 5407 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 5408 | } else { |
7429e9d4 | 5409 | fp = i9xx_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 5410 | if (reduced_clock) |
7429e9d4 | 5411 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
5412 | } |
5413 | ||
8bcc2795 | 5414 | crtc->config.dpll_hw_state.fp0 = fp; |
a7516a05 | 5415 | |
f47709a9 DV |
5416 | crtc->lowfreq_avail = false; |
5417 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && | |
d330a953 | 5418 | reduced_clock && i915.powersave) { |
8bcc2795 | 5419 | crtc->config.dpll_hw_state.fp1 = fp2; |
f47709a9 | 5420 | crtc->lowfreq_avail = true; |
a7516a05 | 5421 | } else { |
8bcc2795 | 5422 | crtc->config.dpll_hw_state.fp1 = fp; |
a7516a05 JB |
5423 | } |
5424 | } | |
5425 | ||
5e69f97f CML |
5426 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
5427 | pipe) | |
89b667f8 JB |
5428 | { |
5429 | u32 reg_val; | |
5430 | ||
5431 | /* | |
5432 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
5433 | * and set it to a reasonable value instead. | |
5434 | */ | |
ab3c759a | 5435 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
5436 | reg_val &= 0xffffff00; |
5437 | reg_val |= 0x00000030; | |
ab3c759a | 5438 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 5439 | |
ab3c759a | 5440 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
5441 | reg_val &= 0x8cffffff; |
5442 | reg_val = 0x8c000000; | |
ab3c759a | 5443 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 5444 | |
ab3c759a | 5445 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 5446 | reg_val &= 0xffffff00; |
ab3c759a | 5447 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 5448 | |
ab3c759a | 5449 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
5450 | reg_val &= 0x00ffffff; |
5451 | reg_val |= 0xb0000000; | |
ab3c759a | 5452 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
5453 | } |
5454 | ||
b551842d DV |
5455 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
5456 | struct intel_link_m_n *m_n) | |
5457 | { | |
5458 | struct drm_device *dev = crtc->base.dev; | |
5459 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5460 | int pipe = crtc->pipe; | |
5461 | ||
e3b95f1e DV |
5462 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
5463 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
5464 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
5465 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
5466 | } |
5467 | ||
5468 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
5469 | struct intel_link_m_n *m_n) | |
5470 | { | |
5471 | struct drm_device *dev = crtc->base.dev; | |
5472 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5473 | int pipe = crtc->pipe; | |
5474 | enum transcoder transcoder = crtc->config.cpu_transcoder; | |
5475 | ||
5476 | if (INTEL_INFO(dev)->gen >= 5) { | |
5477 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
5478 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
5479 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
5480 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
5481 | } else { | |
e3b95f1e DV |
5482 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
5483 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
5484 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
5485 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
5486 | } |
5487 | } | |
5488 | ||
03afc4a2 DV |
5489 | static void intel_dp_set_m_n(struct intel_crtc *crtc) |
5490 | { | |
5491 | if (crtc->config.has_pch_encoder) | |
5492 | intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
5493 | else | |
5494 | intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
5495 | } | |
5496 | ||
f47709a9 | 5497 | static void vlv_update_pll(struct intel_crtc *crtc) |
bdd4b6a6 DV |
5498 | { |
5499 | u32 dpll, dpll_md; | |
5500 | ||
5501 | /* | |
5502 | * Enable DPIO clock input. We should never disable the reference | |
5503 | * clock for pipe B, since VGA hotplug / manual detection depends | |
5504 | * on it. | |
5505 | */ | |
5506 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | | |
5507 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; | |
5508 | /* We should never disable this, set it here for state tracking */ | |
5509 | if (crtc->pipe == PIPE_B) | |
5510 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
5511 | dpll |= DPLL_VCO_ENABLE; | |
5512 | crtc->config.dpll_hw_state.dpll = dpll; | |
5513 | ||
5514 | dpll_md = (crtc->config.pixel_multiplier - 1) | |
5515 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
5516 | crtc->config.dpll_hw_state.dpll_md = dpll_md; | |
5517 | } | |
5518 | ||
5519 | static void vlv_prepare_pll(struct intel_crtc *crtc) | |
a0c4da24 | 5520 | { |
f47709a9 | 5521 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 5522 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 5523 | int pipe = crtc->pipe; |
bdd4b6a6 | 5524 | u32 mdiv; |
a0c4da24 | 5525 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 5526 | u32 coreclk, reg_val; |
a0c4da24 | 5527 | |
09153000 DV |
5528 | mutex_lock(&dev_priv->dpio_lock); |
5529 | ||
f47709a9 DV |
5530 | bestn = crtc->config.dpll.n; |
5531 | bestm1 = crtc->config.dpll.m1; | |
5532 | bestm2 = crtc->config.dpll.m2; | |
5533 | bestp1 = crtc->config.dpll.p1; | |
5534 | bestp2 = crtc->config.dpll.p2; | |
a0c4da24 | 5535 | |
89b667f8 JB |
5536 | /* See eDP HDMI DPIO driver vbios notes doc */ |
5537 | ||
5538 | /* PLL B needs special handling */ | |
bdd4b6a6 | 5539 | if (pipe == PIPE_B) |
5e69f97f | 5540 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
5541 | |
5542 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 5543 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
5544 | |
5545 | /* Disable target IRef on PLL */ | |
ab3c759a | 5546 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 5547 | reg_val &= 0x00ffffff; |
ab3c759a | 5548 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
5549 | |
5550 | /* Disable fast lock */ | |
ab3c759a | 5551 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
5552 | |
5553 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
5554 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
5555 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
5556 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 5557 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
5558 | |
5559 | /* | |
5560 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
5561 | * but we don't support that). | |
5562 | * Note: don't use the DAC post divider as it seems unstable. | |
5563 | */ | |
5564 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 5565 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 5566 | |
a0c4da24 | 5567 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 5568 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 5569 | |
89b667f8 | 5570 | /* Set HBR and RBR LPF coefficients */ |
ff9a6750 | 5571 | if (crtc->config.port_clock == 162000 || |
99750bd4 | 5572 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) || |
89b667f8 | 5573 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) |
ab3c759a | 5574 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 5575 | 0x009f0003); |
89b667f8 | 5576 | else |
ab3c759a | 5577 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
5578 | 0x00d0000f); |
5579 | ||
5580 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) || | |
5581 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) { | |
5582 | /* Use SSC source */ | |
bdd4b6a6 | 5583 | if (pipe == PIPE_A) |
ab3c759a | 5584 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5585 | 0x0df40000); |
5586 | else | |
ab3c759a | 5587 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5588 | 0x0df70000); |
5589 | } else { /* HDMI or VGA */ | |
5590 | /* Use bend source */ | |
bdd4b6a6 | 5591 | if (pipe == PIPE_A) |
ab3c759a | 5592 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5593 | 0x0df70000); |
5594 | else | |
ab3c759a | 5595 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5596 | 0x0df40000); |
5597 | } | |
a0c4da24 | 5598 | |
ab3c759a | 5599 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 JB |
5600 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
5601 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) || | |
5602 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) | |
5603 | coreclk |= 0x01000000; | |
ab3c759a | 5604 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 5605 | |
ab3c759a | 5606 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
09153000 | 5607 | mutex_unlock(&dev_priv->dpio_lock); |
a0c4da24 JB |
5608 | } |
5609 | ||
9d556c99 CML |
5610 | static void chv_update_pll(struct intel_crtc *crtc) |
5611 | { | |
5612 | struct drm_device *dev = crtc->base.dev; | |
5613 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5614 | int pipe = crtc->pipe; | |
5615 | int dpll_reg = DPLL(crtc->pipe); | |
5616 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
580d3811 | 5617 | u32 loopfilter, intcoeff; |
9d556c99 CML |
5618 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
5619 | int refclk; | |
5620 | ||
a11b0703 VS |
5621 | crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV | |
5622 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | | |
5623 | DPLL_VCO_ENABLE; | |
5624 | if (pipe != PIPE_A) | |
5625 | crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
5626 | ||
5627 | crtc->config.dpll_hw_state.dpll_md = | |
5628 | (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
9d556c99 CML |
5629 | |
5630 | bestn = crtc->config.dpll.n; | |
5631 | bestm2_frac = crtc->config.dpll.m2 & 0x3fffff; | |
5632 | bestm1 = crtc->config.dpll.m1; | |
5633 | bestm2 = crtc->config.dpll.m2 >> 22; | |
5634 | bestp1 = crtc->config.dpll.p1; | |
5635 | bestp2 = crtc->config.dpll.p2; | |
5636 | ||
5637 | /* | |
5638 | * Enable Refclk and SSC | |
5639 | */ | |
a11b0703 VS |
5640 | I915_WRITE(dpll_reg, |
5641 | crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); | |
5642 | ||
5643 | mutex_lock(&dev_priv->dpio_lock); | |
9d556c99 | 5644 | |
9d556c99 CML |
5645 | /* p1 and p2 divider */ |
5646 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
5647 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
5648 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
5649 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
5650 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
5651 | ||
5652 | /* Feedback post-divider - m2 */ | |
5653 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
5654 | ||
5655 | /* Feedback refclk divider - n and m1 */ | |
5656 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
5657 | DPIO_CHV_M1_DIV_BY_2 | | |
5658 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
5659 | ||
5660 | /* M2 fraction division */ | |
5661 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); | |
5662 | ||
5663 | /* M2 fraction division enable */ | |
5664 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), | |
5665 | DPIO_CHV_FRAC_DIV_EN | | |
5666 | (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT)); | |
5667 | ||
5668 | /* Loop filter */ | |
5669 | refclk = i9xx_get_refclk(&crtc->base, 0); | |
5670 | loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT | | |
5671 | 2 << DPIO_CHV_GAIN_CTRL_SHIFT; | |
5672 | if (refclk == 100000) | |
5673 | intcoeff = 11; | |
5674 | else if (refclk == 38400) | |
5675 | intcoeff = 10; | |
5676 | else | |
5677 | intcoeff = 9; | |
5678 | loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT; | |
5679 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); | |
5680 | ||
5681 | /* AFC Recal */ | |
5682 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
5683 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
5684 | DPIO_AFC_RECAL); | |
5685 | ||
5686 | mutex_unlock(&dev_priv->dpio_lock); | |
5687 | } | |
5688 | ||
f47709a9 DV |
5689 | static void i9xx_update_pll(struct intel_crtc *crtc, |
5690 | intel_clock_t *reduced_clock, | |
eb1cbe48 DV |
5691 | int num_connectors) |
5692 | { | |
f47709a9 | 5693 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 5694 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
5695 | u32 dpll; |
5696 | bool is_sdvo; | |
f47709a9 | 5697 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 5698 | |
f47709a9 | 5699 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 5700 | |
f47709a9 DV |
5701 | is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) || |
5702 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
5703 | |
5704 | dpll = DPLL_VGA_MODE_DIS; | |
5705 | ||
f47709a9 | 5706 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
5707 | dpll |= DPLLB_MODE_LVDS; |
5708 | else | |
5709 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 5710 | |
ef1b460d | 5711 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
198a037f DV |
5712 | dpll |= (crtc->config.pixel_multiplier - 1) |
5713 | << SDVO_MULTIPLIER_SHIFT_HIRES; | |
eb1cbe48 | 5714 | } |
198a037f DV |
5715 | |
5716 | if (is_sdvo) | |
4a33e48d | 5717 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 5718 | |
f47709a9 | 5719 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) |
4a33e48d | 5720 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
5721 | |
5722 | /* compute bitmask from p1 value */ | |
5723 | if (IS_PINEVIEW(dev)) | |
5724 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
5725 | else { | |
5726 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5727 | if (IS_G4X(dev) && reduced_clock) | |
5728 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
5729 | } | |
5730 | switch (clock->p2) { | |
5731 | case 5: | |
5732 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
5733 | break; | |
5734 | case 7: | |
5735 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
5736 | break; | |
5737 | case 10: | |
5738 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
5739 | break; | |
5740 | case 14: | |
5741 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
5742 | break; | |
5743 | } | |
5744 | if (INTEL_INFO(dev)->gen >= 4) | |
5745 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
5746 | ||
09ede541 | 5747 | if (crtc->config.sdvo_tv_clock) |
eb1cbe48 | 5748 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
f47709a9 | 5749 | else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
5750 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5751 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
5752 | else | |
5753 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5754 | ||
5755 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 DV |
5756 | crtc->config.dpll_hw_state.dpll = dpll; |
5757 | ||
eb1cbe48 | 5758 | if (INTEL_INFO(dev)->gen >= 4) { |
ef1b460d DV |
5759 | u32 dpll_md = (crtc->config.pixel_multiplier - 1) |
5760 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
8bcc2795 | 5761 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
5762 | } |
5763 | } | |
5764 | ||
f47709a9 | 5765 | static void i8xx_update_pll(struct intel_crtc *crtc, |
f47709a9 | 5766 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
5767 | int num_connectors) |
5768 | { | |
f47709a9 | 5769 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 5770 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 5771 | u32 dpll; |
f47709a9 | 5772 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 5773 | |
f47709a9 | 5774 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 5775 | |
eb1cbe48 DV |
5776 | dpll = DPLL_VGA_MODE_DIS; |
5777 | ||
f47709a9 | 5778 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
5779 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
5780 | } else { | |
5781 | if (clock->p1 == 2) | |
5782 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
5783 | else | |
5784 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5785 | if (clock->p2 == 4) | |
5786 | dpll |= PLL_P2_DIVIDE_BY_4; | |
5787 | } | |
5788 | ||
4a33e48d DV |
5789 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO)) |
5790 | dpll |= DPLL_DVO_2X_MODE; | |
5791 | ||
f47709a9 | 5792 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
5793 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5794 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
5795 | else | |
5796 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5797 | ||
5798 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 | 5799 | crtc->config.dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
5800 | } |
5801 | ||
8a654f3b | 5802 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
5803 | { |
5804 | struct drm_device *dev = intel_crtc->base.dev; | |
5805 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5806 | enum pipe pipe = intel_crtc->pipe; | |
3b117c8f | 5807 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
8a654f3b DV |
5808 | struct drm_display_mode *adjusted_mode = |
5809 | &intel_crtc->config.adjusted_mode; | |
1caea6e9 VS |
5810 | uint32_t crtc_vtotal, crtc_vblank_end; |
5811 | int vsyncshift = 0; | |
4d8a62ea DV |
5812 | |
5813 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
5814 | * the hw state checker will get angry at the mismatch. */ | |
5815 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
5816 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 5817 | |
609aeaca | 5818 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 5819 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
5820 | crtc_vtotal -= 1; |
5821 | crtc_vblank_end -= 1; | |
609aeaca VS |
5822 | |
5823 | if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO)) | |
5824 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; | |
5825 | else | |
5826 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
5827 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
5828 | if (vsyncshift < 0) |
5829 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
5830 | } |
5831 | ||
5832 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 5833 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 5834 | |
fe2b8f9d | 5835 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
5836 | (adjusted_mode->crtc_hdisplay - 1) | |
5837 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 5838 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
5839 | (adjusted_mode->crtc_hblank_start - 1) | |
5840 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 5841 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
5842 | (adjusted_mode->crtc_hsync_start - 1) | |
5843 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
5844 | ||
fe2b8f9d | 5845 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 5846 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 5847 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 5848 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 5849 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 5850 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 5851 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
5852 | (adjusted_mode->crtc_vsync_start - 1) | |
5853 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
5854 | ||
b5e508d4 PZ |
5855 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
5856 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
5857 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
5858 | * bits. */ | |
5859 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
5860 | (pipe == PIPE_B || pipe == PIPE_C)) | |
5861 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
5862 | ||
b0e77b9c PZ |
5863 | /* pipesrc controls the size that is scaled from, which should |
5864 | * always be the user's requested size. | |
5865 | */ | |
5866 | I915_WRITE(PIPESRC(pipe), | |
37327abd VS |
5867 | ((intel_crtc->config.pipe_src_w - 1) << 16) | |
5868 | (intel_crtc->config.pipe_src_h - 1)); | |
b0e77b9c PZ |
5869 | } |
5870 | ||
1bd1bd80 DV |
5871 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5872 | struct intel_crtc_config *pipe_config) | |
5873 | { | |
5874 | struct drm_device *dev = crtc->base.dev; | |
5875 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5876 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
5877 | uint32_t tmp; | |
5878 | ||
5879 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
5880 | pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; | |
5881 | pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
5882 | tmp = I915_READ(HBLANK(cpu_transcoder)); | |
5883 | pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; | |
5884 | pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
5885 | tmp = I915_READ(HSYNC(cpu_transcoder)); | |
5886 | pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; | |
5887 | pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
5888 | ||
5889 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
5890 | pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; | |
5891 | pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
5892 | tmp = I915_READ(VBLANK(cpu_transcoder)); | |
5893 | pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; | |
5894 | pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
5895 | tmp = I915_READ(VSYNC(cpu_transcoder)); | |
5896 | pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; | |
5897 | pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
5898 | ||
5899 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
5900 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; | |
5901 | pipe_config->adjusted_mode.crtc_vtotal += 1; | |
5902 | pipe_config->adjusted_mode.crtc_vblank_end += 1; | |
5903 | } | |
5904 | ||
5905 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
5906 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
5907 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
5908 | ||
5909 | pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h; | |
5910 | pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
5911 | } |
5912 | ||
f6a83288 DV |
5913 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5914 | struct intel_crtc_config *pipe_config) | |
babea61d | 5915 | { |
f6a83288 DV |
5916 | mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay; |
5917 | mode->htotal = pipe_config->adjusted_mode.crtc_htotal; | |
5918 | mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start; | |
5919 | mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end; | |
babea61d | 5920 | |
f6a83288 DV |
5921 | mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay; |
5922 | mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal; | |
5923 | mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start; | |
5924 | mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end; | |
babea61d | 5925 | |
f6a83288 | 5926 | mode->flags = pipe_config->adjusted_mode.flags; |
babea61d | 5927 | |
f6a83288 DV |
5928 | mode->clock = pipe_config->adjusted_mode.crtc_clock; |
5929 | mode->flags |= pipe_config->adjusted_mode.flags; | |
babea61d JB |
5930 | } |
5931 | ||
84b046f3 DV |
5932 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
5933 | { | |
5934 | struct drm_device *dev = intel_crtc->base.dev; | |
5935 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5936 | uint32_t pipeconf; | |
5937 | ||
9f11a9e4 | 5938 | pipeconf = 0; |
84b046f3 | 5939 | |
67c72a12 DV |
5940 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
5941 | I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE) | |
5942 | pipeconf |= PIPECONF_ENABLE; | |
5943 | ||
cf532bb2 VS |
5944 | if (intel_crtc->config.double_wide) |
5945 | pipeconf |= PIPECONF_DOUBLE_WIDE; | |
84b046f3 | 5946 | |
ff9ce46e DV |
5947 | /* only g4x and later have fancy bpc/dither controls */ |
5948 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
ff9ce46e DV |
5949 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
5950 | if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30) | |
5951 | pipeconf |= PIPECONF_DITHER_EN | | |
84b046f3 | 5952 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 5953 | |
ff9ce46e DV |
5954 | switch (intel_crtc->config.pipe_bpp) { |
5955 | case 18: | |
5956 | pipeconf |= PIPECONF_6BPC; | |
5957 | break; | |
5958 | case 24: | |
5959 | pipeconf |= PIPECONF_8BPC; | |
5960 | break; | |
5961 | case 30: | |
5962 | pipeconf |= PIPECONF_10BPC; | |
5963 | break; | |
5964 | default: | |
5965 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
5966 | BUG(); | |
84b046f3 DV |
5967 | } |
5968 | } | |
5969 | ||
5970 | if (HAS_PIPE_CXSR(dev)) { | |
5971 | if (intel_crtc->lowfreq_avail) { | |
5972 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
5973 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
5974 | } else { | |
5975 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
5976 | } |
5977 | } | |
5978 | ||
efc2cfff VS |
5979 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
5980 | if (INTEL_INFO(dev)->gen < 4 || | |
5981 | intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO)) | |
5982 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; | |
5983 | else | |
5984 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
5985 | } else | |
84b046f3 DV |
5986 | pipeconf |= PIPECONF_PROGRESSIVE; |
5987 | ||
9f11a9e4 DV |
5988 | if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range) |
5989 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; | |
9c8e09b7 | 5990 | |
84b046f3 DV |
5991 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
5992 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
5993 | } | |
5994 | ||
f564048e | 5995 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
f564048e | 5996 | int x, int y, |
94352cf9 | 5997 | struct drm_framebuffer *fb) |
79e53945 JB |
5998 | { |
5999 | struct drm_device *dev = crtc->dev; | |
6000 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6001 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
c751ce4f | 6002 | int refclk, num_connectors = 0; |
652c393a | 6003 | intel_clock_t clock, reduced_clock; |
a16af721 | 6004 | bool ok, has_reduced_clock = false; |
e9fd1c02 | 6005 | bool is_lvds = false, is_dsi = false; |
5eddb70b | 6006 | struct intel_encoder *encoder; |
d4906093 | 6007 | const intel_limit_t *limit; |
79e53945 | 6008 | |
6c2b7c12 | 6009 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5eddb70b | 6010 | switch (encoder->type) { |
79e53945 JB |
6011 | case INTEL_OUTPUT_LVDS: |
6012 | is_lvds = true; | |
6013 | break; | |
e9fd1c02 JN |
6014 | case INTEL_OUTPUT_DSI: |
6015 | is_dsi = true; | |
6016 | break; | |
79e53945 | 6017 | } |
43565a06 | 6018 | |
c751ce4f | 6019 | num_connectors++; |
79e53945 JB |
6020 | } |
6021 | ||
f2335330 | 6022 | if (is_dsi) |
5b18e57c | 6023 | return 0; |
f2335330 JN |
6024 | |
6025 | if (!intel_crtc->config.clock_set) { | |
6026 | refclk = i9xx_get_refclk(crtc, num_connectors); | |
79e53945 | 6027 | |
e9fd1c02 JN |
6028 | /* |
6029 | * Returns a set of divisors for the desired target clock with | |
6030 | * the given refclk, or FALSE. The returned values represent | |
6031 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
6032 | * 2) / p1 / p2. | |
6033 | */ | |
6034 | limit = intel_limit(crtc, refclk); | |
6035 | ok = dev_priv->display.find_dpll(limit, crtc, | |
6036 | intel_crtc->config.port_clock, | |
6037 | refclk, NULL, &clock); | |
f2335330 | 6038 | if (!ok) { |
e9fd1c02 JN |
6039 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
6040 | return -EINVAL; | |
6041 | } | |
79e53945 | 6042 | |
f2335330 JN |
6043 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
6044 | /* | |
6045 | * Ensure we match the reduced clock's P to the target | |
6046 | * clock. If the clocks don't match, we can't switch | |
6047 | * the display clock by using the FP0/FP1. In such case | |
6048 | * we will disable the LVDS downclock feature. | |
6049 | */ | |
6050 | has_reduced_clock = | |
6051 | dev_priv->display.find_dpll(limit, crtc, | |
6052 | dev_priv->lvds_downclock, | |
6053 | refclk, &clock, | |
6054 | &reduced_clock); | |
6055 | } | |
6056 | /* Compat-code for transition, will disappear. */ | |
f47709a9 DV |
6057 | intel_crtc->config.dpll.n = clock.n; |
6058 | intel_crtc->config.dpll.m1 = clock.m1; | |
6059 | intel_crtc->config.dpll.m2 = clock.m2; | |
6060 | intel_crtc->config.dpll.p1 = clock.p1; | |
6061 | intel_crtc->config.dpll.p2 = clock.p2; | |
6062 | } | |
7026d4ac | 6063 | |
e9fd1c02 | 6064 | if (IS_GEN2(dev)) { |
8a654f3b | 6065 | i8xx_update_pll(intel_crtc, |
2a8f64ca VP |
6066 | has_reduced_clock ? &reduced_clock : NULL, |
6067 | num_connectors); | |
9d556c99 CML |
6068 | } else if (IS_CHERRYVIEW(dev)) { |
6069 | chv_update_pll(intel_crtc); | |
e9fd1c02 | 6070 | } else if (IS_VALLEYVIEW(dev)) { |
f2335330 | 6071 | vlv_update_pll(intel_crtc); |
e9fd1c02 | 6072 | } else { |
f47709a9 | 6073 | i9xx_update_pll(intel_crtc, |
eb1cbe48 | 6074 | has_reduced_clock ? &reduced_clock : NULL, |
eba905b2 | 6075 | num_connectors); |
e9fd1c02 | 6076 | } |
79e53945 | 6077 | |
c8f7a0db | 6078 | return 0; |
f564048e EA |
6079 | } |
6080 | ||
2fa2fe9a DV |
6081 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
6082 | struct intel_crtc_config *pipe_config) | |
6083 | { | |
6084 | struct drm_device *dev = crtc->base.dev; | |
6085 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6086 | uint32_t tmp; | |
6087 | ||
dc9e7dec VS |
6088 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
6089 | return; | |
6090 | ||
2fa2fe9a | 6091 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
6092 | if (!(tmp & PFIT_ENABLE)) |
6093 | return; | |
2fa2fe9a | 6094 | |
06922821 | 6095 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
6096 | if (INTEL_INFO(dev)->gen < 4) { |
6097 | if (crtc->pipe != PIPE_B) | |
6098 | return; | |
2fa2fe9a DV |
6099 | } else { |
6100 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
6101 | return; | |
6102 | } | |
6103 | ||
06922821 | 6104 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
6105 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
6106 | if (INTEL_INFO(dev)->gen < 5) | |
6107 | pipe_config->gmch_pfit.lvds_border_bits = | |
6108 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
6109 | } | |
6110 | ||
acbec814 JB |
6111 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
6112 | struct intel_crtc_config *pipe_config) | |
6113 | { | |
6114 | struct drm_device *dev = crtc->base.dev; | |
6115 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6116 | int pipe = pipe_config->cpu_transcoder; | |
6117 | intel_clock_t clock; | |
6118 | u32 mdiv; | |
662c6ecb | 6119 | int refclk = 100000; |
acbec814 JB |
6120 | |
6121 | mutex_lock(&dev_priv->dpio_lock); | |
ab3c759a | 6122 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
acbec814 JB |
6123 | mutex_unlock(&dev_priv->dpio_lock); |
6124 | ||
6125 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
6126 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
6127 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
6128 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
6129 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
6130 | ||
f646628b | 6131 | vlv_clock(refclk, &clock); |
acbec814 | 6132 | |
f646628b VS |
6133 | /* clock.dot is the fast clock */ |
6134 | pipe_config->port_clock = clock.dot / 5; | |
acbec814 JB |
6135 | } |
6136 | ||
1ad292b5 JB |
6137 | static void i9xx_get_plane_config(struct intel_crtc *crtc, |
6138 | struct intel_plane_config *plane_config) | |
6139 | { | |
6140 | struct drm_device *dev = crtc->base.dev; | |
6141 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6142 | u32 val, base, offset; | |
6143 | int pipe = crtc->pipe, plane = crtc->plane; | |
6144 | int fourcc, pixel_format; | |
6145 | int aligned_height; | |
6146 | ||
66e514c1 DA |
6147 | crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL); |
6148 | if (!crtc->base.primary->fb) { | |
1ad292b5 JB |
6149 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
6150 | return; | |
6151 | } | |
6152 | ||
6153 | val = I915_READ(DSPCNTR(plane)); | |
6154 | ||
6155 | if (INTEL_INFO(dev)->gen >= 4) | |
6156 | if (val & DISPPLANE_TILED) | |
6157 | plane_config->tiled = true; | |
6158 | ||
6159 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
6160 | fourcc = intel_format_to_fourcc(pixel_format); | |
66e514c1 DA |
6161 | crtc->base.primary->fb->pixel_format = fourcc; |
6162 | crtc->base.primary->fb->bits_per_pixel = | |
1ad292b5 JB |
6163 | drm_format_plane_cpp(fourcc, 0) * 8; |
6164 | ||
6165 | if (INTEL_INFO(dev)->gen >= 4) { | |
6166 | if (plane_config->tiled) | |
6167 | offset = I915_READ(DSPTILEOFF(plane)); | |
6168 | else | |
6169 | offset = I915_READ(DSPLINOFF(plane)); | |
6170 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
6171 | } else { | |
6172 | base = I915_READ(DSPADDR(plane)); | |
6173 | } | |
6174 | plane_config->base = base; | |
6175 | ||
6176 | val = I915_READ(PIPESRC(pipe)); | |
66e514c1 DA |
6177 | crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1; |
6178 | crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
6179 | |
6180 | val = I915_READ(DSPSTRIDE(pipe)); | |
66e514c1 | 6181 | crtc->base.primary->fb->pitches[0] = val & 0xffffff80; |
1ad292b5 | 6182 | |
66e514c1 | 6183 | aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, |
1ad292b5 JB |
6184 | plane_config->tiled); |
6185 | ||
66e514c1 | 6186 | plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] * |
1ad292b5 JB |
6187 | aligned_height, PAGE_SIZE); |
6188 | ||
6189 | DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
66e514c1 DA |
6190 | pipe, plane, crtc->base.primary->fb->width, |
6191 | crtc->base.primary->fb->height, | |
6192 | crtc->base.primary->fb->bits_per_pixel, base, | |
6193 | crtc->base.primary->fb->pitches[0], | |
1ad292b5 JB |
6194 | plane_config->size); |
6195 | ||
6196 | } | |
6197 | ||
70b23a98 VS |
6198 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
6199 | struct intel_crtc_config *pipe_config) | |
6200 | { | |
6201 | struct drm_device *dev = crtc->base.dev; | |
6202 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6203 | int pipe = pipe_config->cpu_transcoder; | |
6204 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
6205 | intel_clock_t clock; | |
6206 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2; | |
6207 | int refclk = 100000; | |
6208 | ||
6209 | mutex_lock(&dev_priv->dpio_lock); | |
6210 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); | |
6211 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
6212 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
6213 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
6214 | mutex_unlock(&dev_priv->dpio_lock); | |
6215 | ||
6216 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
6217 | clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff); | |
6218 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; | |
6219 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
6220 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
6221 | ||
6222 | chv_clock(refclk, &clock); | |
6223 | ||
6224 | /* clock.dot is the fast clock */ | |
6225 | pipe_config->port_clock = clock.dot / 5; | |
6226 | } | |
6227 | ||
0e8ffe1b DV |
6228 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
6229 | struct intel_crtc_config *pipe_config) | |
6230 | { | |
6231 | struct drm_device *dev = crtc->base.dev; | |
6232 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6233 | uint32_t tmp; | |
6234 | ||
b5482bd0 ID |
6235 | if (!intel_display_power_enabled(dev_priv, |
6236 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
6237 | return false; | |
6238 | ||
e143a21c | 6239 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 6240 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 6241 | |
0e8ffe1b DV |
6242 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
6243 | if (!(tmp & PIPECONF_ENABLE)) | |
6244 | return false; | |
6245 | ||
42571aef VS |
6246 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
6247 | switch (tmp & PIPECONF_BPC_MASK) { | |
6248 | case PIPECONF_6BPC: | |
6249 | pipe_config->pipe_bpp = 18; | |
6250 | break; | |
6251 | case PIPECONF_8BPC: | |
6252 | pipe_config->pipe_bpp = 24; | |
6253 | break; | |
6254 | case PIPECONF_10BPC: | |
6255 | pipe_config->pipe_bpp = 30; | |
6256 | break; | |
6257 | default: | |
6258 | break; | |
6259 | } | |
6260 | } | |
6261 | ||
b5a9fa09 DV |
6262 | if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
6263 | pipe_config->limited_color_range = true; | |
6264 | ||
282740f7 VS |
6265 | if (INTEL_INFO(dev)->gen < 4) |
6266 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
6267 | ||
1bd1bd80 DV |
6268 | intel_get_pipe_timings(crtc, pipe_config); |
6269 | ||
2fa2fe9a DV |
6270 | i9xx_get_pfit_config(crtc, pipe_config); |
6271 | ||
6c49f241 DV |
6272 | if (INTEL_INFO(dev)->gen >= 4) { |
6273 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
6274 | pipe_config->pixel_multiplier = | |
6275 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
6276 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 6277 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
6278 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
6279 | tmp = I915_READ(DPLL(crtc->pipe)); | |
6280 | pipe_config->pixel_multiplier = | |
6281 | ((tmp & SDVO_MULTIPLIER_MASK) | |
6282 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
6283 | } else { | |
6284 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
6285 | * port and will be fixed up in the encoder->get_config | |
6286 | * function. */ | |
6287 | pipe_config->pixel_multiplier = 1; | |
6288 | } | |
8bcc2795 DV |
6289 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
6290 | if (!IS_VALLEYVIEW(dev)) { | |
6291 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); | |
6292 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
6293 | } else { |
6294 | /* Mask out read-only status bits. */ | |
6295 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
6296 | DPLL_PORTC_READY_MASK | | |
6297 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 6298 | } |
6c49f241 | 6299 | |
70b23a98 VS |
6300 | if (IS_CHERRYVIEW(dev)) |
6301 | chv_crtc_clock_get(crtc, pipe_config); | |
6302 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
6303 | vlv_crtc_clock_get(crtc, pipe_config); |
6304 | else | |
6305 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 6306 | |
0e8ffe1b DV |
6307 | return true; |
6308 | } | |
6309 | ||
dde86e2d | 6310 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
6311 | { |
6312 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6313 | struct drm_mode_config *mode_config = &dev->mode_config; | |
13d83a67 | 6314 | struct intel_encoder *encoder; |
74cfd7ac | 6315 | u32 val, final; |
13d83a67 | 6316 | bool has_lvds = false; |
199e5d79 | 6317 | bool has_cpu_edp = false; |
199e5d79 | 6318 | bool has_panel = false; |
99eb6a01 KP |
6319 | bool has_ck505 = false; |
6320 | bool can_ssc = false; | |
13d83a67 JB |
6321 | |
6322 | /* We need to take the global config into account */ | |
199e5d79 KP |
6323 | list_for_each_entry(encoder, &mode_config->encoder_list, |
6324 | base.head) { | |
6325 | switch (encoder->type) { | |
6326 | case INTEL_OUTPUT_LVDS: | |
6327 | has_panel = true; | |
6328 | has_lvds = true; | |
6329 | break; | |
6330 | case INTEL_OUTPUT_EDP: | |
6331 | has_panel = true; | |
2de6905f | 6332 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
6333 | has_cpu_edp = true; |
6334 | break; | |
13d83a67 JB |
6335 | } |
6336 | } | |
6337 | ||
99eb6a01 | 6338 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 6339 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
6340 | can_ssc = has_ck505; |
6341 | } else { | |
6342 | has_ck505 = false; | |
6343 | can_ssc = true; | |
6344 | } | |
6345 | ||
2de6905f ID |
6346 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
6347 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
6348 | |
6349 | /* Ironlake: try to setup display ref clock before DPLL | |
6350 | * enabling. This is only under driver's control after | |
6351 | * PCH B stepping, previous chipset stepping should be | |
6352 | * ignoring this setting. | |
6353 | */ | |
74cfd7ac CW |
6354 | val = I915_READ(PCH_DREF_CONTROL); |
6355 | ||
6356 | /* As we must carefully and slowly disable/enable each source in turn, | |
6357 | * compute the final state we want first and check if we need to | |
6358 | * make any changes at all. | |
6359 | */ | |
6360 | final = val; | |
6361 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
6362 | if (has_ck505) | |
6363 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
6364 | else | |
6365 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
6366 | ||
6367 | final &= ~DREF_SSC_SOURCE_MASK; | |
6368 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
6369 | final &= ~DREF_SSC1_ENABLE; | |
6370 | ||
6371 | if (has_panel) { | |
6372 | final |= DREF_SSC_SOURCE_ENABLE; | |
6373 | ||
6374 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
6375 | final |= DREF_SSC1_ENABLE; | |
6376 | ||
6377 | if (has_cpu_edp) { | |
6378 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
6379 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
6380 | else | |
6381 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
6382 | } else | |
6383 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
6384 | } else { | |
6385 | final |= DREF_SSC_SOURCE_DISABLE; | |
6386 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
6387 | } | |
6388 | ||
6389 | if (final == val) | |
6390 | return; | |
6391 | ||
13d83a67 | 6392 | /* Always enable nonspread source */ |
74cfd7ac | 6393 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 6394 | |
99eb6a01 | 6395 | if (has_ck505) |
74cfd7ac | 6396 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 6397 | else |
74cfd7ac | 6398 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 6399 | |
199e5d79 | 6400 | if (has_panel) { |
74cfd7ac CW |
6401 | val &= ~DREF_SSC_SOURCE_MASK; |
6402 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 6403 | |
199e5d79 | 6404 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 6405 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 6406 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 6407 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 6408 | } else |
74cfd7ac | 6409 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
6410 | |
6411 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 6412 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
6413 | POSTING_READ(PCH_DREF_CONTROL); |
6414 | udelay(200); | |
6415 | ||
74cfd7ac | 6416 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
6417 | |
6418 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 6419 | if (has_cpu_edp) { |
99eb6a01 | 6420 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 6421 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 6422 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 6423 | } else |
74cfd7ac | 6424 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 6425 | } else |
74cfd7ac | 6426 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 6427 | |
74cfd7ac | 6428 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
6429 | POSTING_READ(PCH_DREF_CONTROL); |
6430 | udelay(200); | |
6431 | } else { | |
6432 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
6433 | ||
74cfd7ac | 6434 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
6435 | |
6436 | /* Turn off CPU output */ | |
74cfd7ac | 6437 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 6438 | |
74cfd7ac | 6439 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
6440 | POSTING_READ(PCH_DREF_CONTROL); |
6441 | udelay(200); | |
6442 | ||
6443 | /* Turn off the SSC source */ | |
74cfd7ac CW |
6444 | val &= ~DREF_SSC_SOURCE_MASK; |
6445 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
6446 | |
6447 | /* Turn off SSC1 */ | |
74cfd7ac | 6448 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 6449 | |
74cfd7ac | 6450 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
6451 | POSTING_READ(PCH_DREF_CONTROL); |
6452 | udelay(200); | |
6453 | } | |
74cfd7ac CW |
6454 | |
6455 | BUG_ON(val != final); | |
13d83a67 JB |
6456 | } |
6457 | ||
f31f2d55 | 6458 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 6459 | { |
f31f2d55 | 6460 | uint32_t tmp; |
dde86e2d | 6461 | |
0ff066a9 PZ |
6462 | tmp = I915_READ(SOUTH_CHICKEN2); |
6463 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
6464 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 6465 | |
0ff066a9 PZ |
6466 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
6467 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
6468 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 6469 | |
0ff066a9 PZ |
6470 | tmp = I915_READ(SOUTH_CHICKEN2); |
6471 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
6472 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 6473 | |
0ff066a9 PZ |
6474 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
6475 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
6476 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
6477 | } |
6478 | ||
6479 | /* WaMPhyProgramming:hsw */ | |
6480 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
6481 | { | |
6482 | uint32_t tmp; | |
dde86e2d PZ |
6483 | |
6484 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
6485 | tmp &= ~(0xFF << 24); | |
6486 | tmp |= (0x12 << 24); | |
6487 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
6488 | ||
dde86e2d PZ |
6489 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
6490 | tmp |= (1 << 11); | |
6491 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
6492 | ||
6493 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
6494 | tmp |= (1 << 11); | |
6495 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
6496 | ||
dde86e2d PZ |
6497 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
6498 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
6499 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
6500 | ||
6501 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
6502 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
6503 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
6504 | ||
0ff066a9 PZ |
6505 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
6506 | tmp &= ~(7 << 13); | |
6507 | tmp |= (5 << 13); | |
6508 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 6509 | |
0ff066a9 PZ |
6510 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
6511 | tmp &= ~(7 << 13); | |
6512 | tmp |= (5 << 13); | |
6513 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
6514 | |
6515 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
6516 | tmp &= ~0xFF; | |
6517 | tmp |= 0x1C; | |
6518 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
6519 | ||
6520 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
6521 | tmp &= ~0xFF; | |
6522 | tmp |= 0x1C; | |
6523 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
6524 | ||
6525 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
6526 | tmp &= ~(0xFF << 16); | |
6527 | tmp |= (0x1C << 16); | |
6528 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
6529 | ||
6530 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
6531 | tmp &= ~(0xFF << 16); | |
6532 | tmp |= (0x1C << 16); | |
6533 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
6534 | ||
0ff066a9 PZ |
6535 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
6536 | tmp |= (1 << 27); | |
6537 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 6538 | |
0ff066a9 PZ |
6539 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
6540 | tmp |= (1 << 27); | |
6541 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 6542 | |
0ff066a9 PZ |
6543 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
6544 | tmp &= ~(0xF << 28); | |
6545 | tmp |= (4 << 28); | |
6546 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 6547 | |
0ff066a9 PZ |
6548 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
6549 | tmp &= ~(0xF << 28); | |
6550 | tmp |= (4 << 28); | |
6551 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
6552 | } |
6553 | ||
2fa86a1f PZ |
6554 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
6555 | * Programming" based on the parameters passed: | |
6556 | * - Sequence to enable CLKOUT_DP | |
6557 | * - Sequence to enable CLKOUT_DP without spread | |
6558 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
6559 | */ | |
6560 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
6561 | bool with_fdi) | |
f31f2d55 PZ |
6562 | { |
6563 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
6564 | uint32_t reg, tmp; |
6565 | ||
6566 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
6567 | with_spread = true; | |
6568 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && | |
6569 | with_fdi, "LP PCH doesn't have FDI\n")) | |
6570 | with_fdi = false; | |
f31f2d55 PZ |
6571 | |
6572 | mutex_lock(&dev_priv->dpio_lock); | |
6573 | ||
6574 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
6575 | tmp &= ~SBI_SSCCTL_DISABLE; | |
6576 | tmp |= SBI_SSCCTL_PATHALT; | |
6577 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
6578 | ||
6579 | udelay(24); | |
6580 | ||
2fa86a1f PZ |
6581 | if (with_spread) { |
6582 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
6583 | tmp &= ~SBI_SSCCTL_PATHALT; | |
6584 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 6585 | |
2fa86a1f PZ |
6586 | if (with_fdi) { |
6587 | lpt_reset_fdi_mphy(dev_priv); | |
6588 | lpt_program_fdi_mphy(dev_priv); | |
6589 | } | |
6590 | } | |
dde86e2d | 6591 | |
2fa86a1f PZ |
6592 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
6593 | SBI_GEN0 : SBI_DBUFF0; | |
6594 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
6595 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
6596 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 DV |
6597 | |
6598 | mutex_unlock(&dev_priv->dpio_lock); | |
dde86e2d PZ |
6599 | } |
6600 | ||
47701c3b PZ |
6601 | /* Sequence to disable CLKOUT_DP */ |
6602 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
6603 | { | |
6604 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6605 | uint32_t reg, tmp; | |
6606 | ||
6607 | mutex_lock(&dev_priv->dpio_lock); | |
6608 | ||
6609 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? | |
6610 | SBI_GEN0 : SBI_DBUFF0; | |
6611 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
6612 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
6613 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
6614 | ||
6615 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
6616 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
6617 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
6618 | tmp |= SBI_SSCCTL_PATHALT; | |
6619 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
6620 | udelay(32); | |
6621 | } | |
6622 | tmp |= SBI_SSCCTL_DISABLE; | |
6623 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
6624 | } | |
6625 | ||
6626 | mutex_unlock(&dev_priv->dpio_lock); | |
6627 | } | |
6628 | ||
bf8fa3d3 PZ |
6629 | static void lpt_init_pch_refclk(struct drm_device *dev) |
6630 | { | |
6631 | struct drm_mode_config *mode_config = &dev->mode_config; | |
6632 | struct intel_encoder *encoder; | |
6633 | bool has_vga = false; | |
6634 | ||
6635 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { | |
6636 | switch (encoder->type) { | |
6637 | case INTEL_OUTPUT_ANALOG: | |
6638 | has_vga = true; | |
6639 | break; | |
6640 | } | |
6641 | } | |
6642 | ||
47701c3b PZ |
6643 | if (has_vga) |
6644 | lpt_enable_clkout_dp(dev, true, true); | |
6645 | else | |
6646 | lpt_disable_clkout_dp(dev); | |
bf8fa3d3 PZ |
6647 | } |
6648 | ||
dde86e2d PZ |
6649 | /* |
6650 | * Initialize reference clocks when the driver loads | |
6651 | */ | |
6652 | void intel_init_pch_refclk(struct drm_device *dev) | |
6653 | { | |
6654 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
6655 | ironlake_init_pch_refclk(dev); | |
6656 | else if (HAS_PCH_LPT(dev)) | |
6657 | lpt_init_pch_refclk(dev); | |
6658 | } | |
6659 | ||
d9d444cb JB |
6660 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
6661 | { | |
6662 | struct drm_device *dev = crtc->dev; | |
6663 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6664 | struct intel_encoder *encoder; | |
d9d444cb JB |
6665 | int num_connectors = 0; |
6666 | bool is_lvds = false; | |
6667 | ||
6c2b7c12 | 6668 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
d9d444cb JB |
6669 | switch (encoder->type) { |
6670 | case INTEL_OUTPUT_LVDS: | |
6671 | is_lvds = true; | |
6672 | break; | |
d9d444cb JB |
6673 | } |
6674 | num_connectors++; | |
6675 | } | |
6676 | ||
6677 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 6678 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 6679 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 6680 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
6681 | } |
6682 | ||
6683 | return 120000; | |
6684 | } | |
6685 | ||
6ff93609 | 6686 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 6687 | { |
c8203565 | 6688 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
6689 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6690 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
6691 | uint32_t val; |
6692 | ||
78114071 | 6693 | val = 0; |
c8203565 | 6694 | |
965e0c48 | 6695 | switch (intel_crtc->config.pipe_bpp) { |
c8203565 | 6696 | case 18: |
dfd07d72 | 6697 | val |= PIPECONF_6BPC; |
c8203565 PZ |
6698 | break; |
6699 | case 24: | |
dfd07d72 | 6700 | val |= PIPECONF_8BPC; |
c8203565 PZ |
6701 | break; |
6702 | case 30: | |
dfd07d72 | 6703 | val |= PIPECONF_10BPC; |
c8203565 PZ |
6704 | break; |
6705 | case 36: | |
dfd07d72 | 6706 | val |= PIPECONF_12BPC; |
c8203565 PZ |
6707 | break; |
6708 | default: | |
cc769b62 PZ |
6709 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
6710 | BUG(); | |
c8203565 PZ |
6711 | } |
6712 | ||
d8b32247 | 6713 | if (intel_crtc->config.dither) |
c8203565 PZ |
6714 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
6715 | ||
6ff93609 | 6716 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
6717 | val |= PIPECONF_INTERLACED_ILK; |
6718 | else | |
6719 | val |= PIPECONF_PROGRESSIVE; | |
6720 | ||
50f3b016 | 6721 | if (intel_crtc->config.limited_color_range) |
3685a8f3 | 6722 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 6723 | |
c8203565 PZ |
6724 | I915_WRITE(PIPECONF(pipe), val); |
6725 | POSTING_READ(PIPECONF(pipe)); | |
6726 | } | |
6727 | ||
86d3efce VS |
6728 | /* |
6729 | * Set up the pipe CSC unit. | |
6730 | * | |
6731 | * Currently only full range RGB to limited range RGB conversion | |
6732 | * is supported, but eventually this should handle various | |
6733 | * RGB<->YCbCr scenarios as well. | |
6734 | */ | |
50f3b016 | 6735 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
6736 | { |
6737 | struct drm_device *dev = crtc->dev; | |
6738 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6739 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6740 | int pipe = intel_crtc->pipe; | |
6741 | uint16_t coeff = 0x7800; /* 1.0 */ | |
6742 | ||
6743 | /* | |
6744 | * TODO: Check what kind of values actually come out of the pipe | |
6745 | * with these coeff/postoff values and adjust to get the best | |
6746 | * accuracy. Perhaps we even need to take the bpc value into | |
6747 | * consideration. | |
6748 | */ | |
6749 | ||
50f3b016 | 6750 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
6751 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
6752 | ||
6753 | /* | |
6754 | * GY/GU and RY/RU should be the other way around according | |
6755 | * to BSpec, but reality doesn't agree. Just set them up in | |
6756 | * a way that results in the correct picture. | |
6757 | */ | |
6758 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
6759 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
6760 | ||
6761 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
6762 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
6763 | ||
6764 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
6765 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
6766 | ||
6767 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
6768 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
6769 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
6770 | ||
6771 | if (INTEL_INFO(dev)->gen > 6) { | |
6772 | uint16_t postoff = 0; | |
6773 | ||
50f3b016 | 6774 | if (intel_crtc->config.limited_color_range) |
32cf0cb0 | 6775 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
6776 | |
6777 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
6778 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
6779 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
6780 | ||
6781 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
6782 | } else { | |
6783 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
6784 | ||
50f3b016 | 6785 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
6786 | mode |= CSC_BLACK_SCREEN_OFFSET; |
6787 | ||
6788 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
6789 | } | |
6790 | } | |
6791 | ||
6ff93609 | 6792 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 6793 | { |
756f85cf PZ |
6794 | struct drm_device *dev = crtc->dev; |
6795 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 6796 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 6797 | enum pipe pipe = intel_crtc->pipe; |
3b117c8f | 6798 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee2b0b38 PZ |
6799 | uint32_t val; |
6800 | ||
3eff4faa | 6801 | val = 0; |
ee2b0b38 | 6802 | |
756f85cf | 6803 | if (IS_HASWELL(dev) && intel_crtc->config.dither) |
ee2b0b38 PZ |
6804 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
6805 | ||
6ff93609 | 6806 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
6807 | val |= PIPECONF_INTERLACED_ILK; |
6808 | else | |
6809 | val |= PIPECONF_PROGRESSIVE; | |
6810 | ||
702e7a56 PZ |
6811 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
6812 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
6813 | |
6814 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
6815 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf PZ |
6816 | |
6817 | if (IS_BROADWELL(dev)) { | |
6818 | val = 0; | |
6819 | ||
6820 | switch (intel_crtc->config.pipe_bpp) { | |
6821 | case 18: | |
6822 | val |= PIPEMISC_DITHER_6_BPC; | |
6823 | break; | |
6824 | case 24: | |
6825 | val |= PIPEMISC_DITHER_8_BPC; | |
6826 | break; | |
6827 | case 30: | |
6828 | val |= PIPEMISC_DITHER_10_BPC; | |
6829 | break; | |
6830 | case 36: | |
6831 | val |= PIPEMISC_DITHER_12_BPC; | |
6832 | break; | |
6833 | default: | |
6834 | /* Case prevented by pipe_config_set_bpp. */ | |
6835 | BUG(); | |
6836 | } | |
6837 | ||
6838 | if (intel_crtc->config.dither) | |
6839 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; | |
6840 | ||
6841 | I915_WRITE(PIPEMISC(pipe), val); | |
6842 | } | |
ee2b0b38 PZ |
6843 | } |
6844 | ||
6591c6e4 | 6845 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
6591c6e4 PZ |
6846 | intel_clock_t *clock, |
6847 | bool *has_reduced_clock, | |
6848 | intel_clock_t *reduced_clock) | |
6849 | { | |
6850 | struct drm_device *dev = crtc->dev; | |
6851 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6852 | struct intel_encoder *intel_encoder; | |
6853 | int refclk; | |
d4906093 | 6854 | const intel_limit_t *limit; |
a16af721 | 6855 | bool ret, is_lvds = false; |
79e53945 | 6856 | |
6591c6e4 PZ |
6857 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
6858 | switch (intel_encoder->type) { | |
79e53945 JB |
6859 | case INTEL_OUTPUT_LVDS: |
6860 | is_lvds = true; | |
6861 | break; | |
79e53945 JB |
6862 | } |
6863 | } | |
6864 | ||
d9d444cb | 6865 | refclk = ironlake_get_refclk(crtc); |
79e53945 | 6866 | |
d4906093 ML |
6867 | /* |
6868 | * Returns a set of divisors for the desired target clock with the given | |
6869 | * refclk, or FALSE. The returned values represent the clock equation: | |
6870 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
6871 | */ | |
1b894b59 | 6872 | limit = intel_limit(crtc, refclk); |
ff9a6750 DV |
6873 | ret = dev_priv->display.find_dpll(limit, crtc, |
6874 | to_intel_crtc(crtc)->config.port_clock, | |
ee9300bb | 6875 | refclk, NULL, clock); |
6591c6e4 PZ |
6876 | if (!ret) |
6877 | return false; | |
cda4b7d3 | 6878 | |
ddc9003c | 6879 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
6880 | /* |
6881 | * Ensure we match the reduced clock's P to the target clock. | |
6882 | * If the clocks don't match, we can't switch the display clock | |
6883 | * by using the FP0/FP1. In such case we will disable the LVDS | |
6884 | * downclock feature. | |
6885 | */ | |
ee9300bb DV |
6886 | *has_reduced_clock = |
6887 | dev_priv->display.find_dpll(limit, crtc, | |
6888 | dev_priv->lvds_downclock, | |
6889 | refclk, clock, | |
6890 | reduced_clock); | |
652c393a | 6891 | } |
61e9653f | 6892 | |
6591c6e4 PZ |
6893 | return true; |
6894 | } | |
6895 | ||
d4b1931c PZ |
6896 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
6897 | { | |
6898 | /* | |
6899 | * Account for spread spectrum to avoid | |
6900 | * oversubscribing the link. Max center spread | |
6901 | * is 2.5%; use 5% for safety's sake. | |
6902 | */ | |
6903 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 6904 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
6905 | } |
6906 | ||
7429e9d4 | 6907 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 6908 | { |
7429e9d4 | 6909 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
6910 | } |
6911 | ||
de13a2e3 | 6912 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
7429e9d4 | 6913 | u32 *fp, |
9a7c7890 | 6914 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 6915 | { |
de13a2e3 | 6916 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
6917 | struct drm_device *dev = crtc->dev; |
6918 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de13a2e3 PZ |
6919 | struct intel_encoder *intel_encoder; |
6920 | uint32_t dpll; | |
6cc5f341 | 6921 | int factor, num_connectors = 0; |
09ede541 | 6922 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 6923 | |
de13a2e3 PZ |
6924 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
6925 | switch (intel_encoder->type) { | |
79e53945 JB |
6926 | case INTEL_OUTPUT_LVDS: |
6927 | is_lvds = true; | |
6928 | break; | |
6929 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 6930 | case INTEL_OUTPUT_HDMI: |
79e53945 | 6931 | is_sdvo = true; |
79e53945 | 6932 | break; |
79e53945 | 6933 | } |
43565a06 | 6934 | |
c751ce4f | 6935 | num_connectors++; |
79e53945 | 6936 | } |
79e53945 | 6937 | |
c1858123 | 6938 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
6939 | factor = 21; |
6940 | if (is_lvds) { | |
6941 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 6942 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 6943 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 6944 | factor = 25; |
09ede541 | 6945 | } else if (intel_crtc->config.sdvo_tv_clock) |
8febb297 | 6946 | factor = 20; |
c1858123 | 6947 | |
7429e9d4 | 6948 | if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor)) |
7d0ac5b7 | 6949 | *fp |= FP_CB_TUNE; |
2c07245f | 6950 | |
9a7c7890 DV |
6951 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
6952 | *fp2 |= FP_CB_TUNE; | |
6953 | ||
5eddb70b | 6954 | dpll = 0; |
2c07245f | 6955 | |
a07d6787 EA |
6956 | if (is_lvds) |
6957 | dpll |= DPLLB_MODE_LVDS; | |
6958 | else | |
6959 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 6960 | |
ef1b460d DV |
6961 | dpll |= (intel_crtc->config.pixel_multiplier - 1) |
6962 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
198a037f DV |
6963 | |
6964 | if (is_sdvo) | |
4a33e48d | 6965 | dpll |= DPLL_SDVO_HIGH_SPEED; |
9566e9af | 6966 | if (intel_crtc->config.has_dp_encoder) |
4a33e48d | 6967 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 6968 | |
a07d6787 | 6969 | /* compute bitmask from p1 value */ |
7429e9d4 | 6970 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 6971 | /* also FPA1 */ |
7429e9d4 | 6972 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 6973 | |
7429e9d4 | 6974 | switch (intel_crtc->config.dpll.p2) { |
a07d6787 EA |
6975 | case 5: |
6976 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
6977 | break; | |
6978 | case 7: | |
6979 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
6980 | break; | |
6981 | case 10: | |
6982 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
6983 | break; | |
6984 | case 14: | |
6985 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
6986 | break; | |
79e53945 JB |
6987 | } |
6988 | ||
b4c09f3b | 6989 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 6990 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
6991 | else |
6992 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6993 | ||
959e16d6 | 6994 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
6995 | } |
6996 | ||
6997 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, | |
de13a2e3 PZ |
6998 | int x, int y, |
6999 | struct drm_framebuffer *fb) | |
7000 | { | |
7001 | struct drm_device *dev = crtc->dev; | |
de13a2e3 | 7002 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
de13a2e3 PZ |
7003 | int num_connectors = 0; |
7004 | intel_clock_t clock, reduced_clock; | |
cbbab5bd | 7005 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 7006 | bool ok, has_reduced_clock = false; |
8b47047b | 7007 | bool is_lvds = false; |
de13a2e3 | 7008 | struct intel_encoder *encoder; |
e2b78267 | 7009 | struct intel_shared_dpll *pll; |
de13a2e3 PZ |
7010 | |
7011 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
7012 | switch (encoder->type) { | |
7013 | case INTEL_OUTPUT_LVDS: | |
7014 | is_lvds = true; | |
7015 | break; | |
de13a2e3 PZ |
7016 | } |
7017 | ||
7018 | num_connectors++; | |
a07d6787 | 7019 | } |
79e53945 | 7020 | |
5dc5298b PZ |
7021 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
7022 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 7023 | |
ff9a6750 | 7024 | ok = ironlake_compute_clocks(crtc, &clock, |
de13a2e3 | 7025 | &has_reduced_clock, &reduced_clock); |
ee9300bb | 7026 | if (!ok && !intel_crtc->config.clock_set) { |
de13a2e3 PZ |
7027 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
7028 | return -EINVAL; | |
79e53945 | 7029 | } |
f47709a9 DV |
7030 | /* Compat-code for transition, will disappear. */ |
7031 | if (!intel_crtc->config.clock_set) { | |
7032 | intel_crtc->config.dpll.n = clock.n; | |
7033 | intel_crtc->config.dpll.m1 = clock.m1; | |
7034 | intel_crtc->config.dpll.m2 = clock.m2; | |
7035 | intel_crtc->config.dpll.p1 = clock.p1; | |
7036 | intel_crtc->config.dpll.p2 = clock.p2; | |
7037 | } | |
79e53945 | 7038 | |
5dc5298b | 7039 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
8b47047b | 7040 | if (intel_crtc->config.has_pch_encoder) { |
7429e9d4 | 7041 | fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll); |
cbbab5bd | 7042 | if (has_reduced_clock) |
7429e9d4 | 7043 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 7044 | |
7429e9d4 | 7045 | dpll = ironlake_compute_dpll(intel_crtc, |
cbbab5bd DV |
7046 | &fp, &reduced_clock, |
7047 | has_reduced_clock ? &fp2 : NULL); | |
7048 | ||
959e16d6 | 7049 | intel_crtc->config.dpll_hw_state.dpll = dpll; |
66e985c0 DV |
7050 | intel_crtc->config.dpll_hw_state.fp0 = fp; |
7051 | if (has_reduced_clock) | |
7052 | intel_crtc->config.dpll_hw_state.fp1 = fp2; | |
7053 | else | |
7054 | intel_crtc->config.dpll_hw_state.fp1 = fp; | |
7055 | ||
b89a1d39 | 7056 | pll = intel_get_shared_dpll(intel_crtc); |
ee7b9f93 | 7057 | if (pll == NULL) { |
84f44ce7 | 7058 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
29407aab | 7059 | pipe_name(intel_crtc->pipe)); |
4b645f14 JB |
7060 | return -EINVAL; |
7061 | } | |
ee7b9f93 | 7062 | } else |
e72f9fbf | 7063 | intel_put_shared_dpll(intel_crtc); |
79e53945 | 7064 | |
d330a953 | 7065 | if (is_lvds && has_reduced_clock && i915.powersave) |
bcd644e0 DV |
7066 | intel_crtc->lowfreq_avail = true; |
7067 | else | |
7068 | intel_crtc->lowfreq_avail = false; | |
e2b78267 | 7069 | |
c8f7a0db | 7070 | return 0; |
79e53945 JB |
7071 | } |
7072 | ||
eb14cb74 VS |
7073 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
7074 | struct intel_link_m_n *m_n) | |
7075 | { | |
7076 | struct drm_device *dev = crtc->base.dev; | |
7077 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7078 | enum pipe pipe = crtc->pipe; | |
7079 | ||
7080 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
7081 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
7082 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
7083 | & ~TU_SIZE_MASK; | |
7084 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
7085 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
7086 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7087 | } | |
7088 | ||
7089 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
7090 | enum transcoder transcoder, | |
7091 | struct intel_link_m_n *m_n) | |
72419203 DV |
7092 | { |
7093 | struct drm_device *dev = crtc->base.dev; | |
7094 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 7095 | enum pipe pipe = crtc->pipe; |
72419203 | 7096 | |
eb14cb74 VS |
7097 | if (INTEL_INFO(dev)->gen >= 5) { |
7098 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
7099 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
7100 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
7101 | & ~TU_SIZE_MASK; | |
7102 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
7103 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
7104 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7105 | } else { | |
7106 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
7107 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
7108 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
7109 | & ~TU_SIZE_MASK; | |
7110 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
7111 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
7112 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7113 | } | |
7114 | } | |
7115 | ||
7116 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
7117 | struct intel_crtc_config *pipe_config) | |
7118 | { | |
7119 | if (crtc->config.has_pch_encoder) | |
7120 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); | |
7121 | else | |
7122 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
7123 | &pipe_config->dp_m_n); | |
7124 | } | |
72419203 | 7125 | |
eb14cb74 VS |
7126 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
7127 | struct intel_crtc_config *pipe_config) | |
7128 | { | |
7129 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
7130 | &pipe_config->fdi_m_n); | |
72419203 DV |
7131 | } |
7132 | ||
2fa2fe9a DV |
7133 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
7134 | struct intel_crtc_config *pipe_config) | |
7135 | { | |
7136 | struct drm_device *dev = crtc->base.dev; | |
7137 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7138 | uint32_t tmp; | |
7139 | ||
7140 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
7141 | ||
7142 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 7143 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
7144 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
7145 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
7146 | |
7147 | /* We currently do not free assignements of panel fitters on | |
7148 | * ivb/hsw (since we don't use the higher upscaling modes which | |
7149 | * differentiates them) so just WARN about this case for now. */ | |
7150 | if (IS_GEN7(dev)) { | |
7151 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
7152 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
7153 | } | |
2fa2fe9a | 7154 | } |
79e53945 JB |
7155 | } |
7156 | ||
4c6baa59 JB |
7157 | static void ironlake_get_plane_config(struct intel_crtc *crtc, |
7158 | struct intel_plane_config *plane_config) | |
7159 | { | |
7160 | struct drm_device *dev = crtc->base.dev; | |
7161 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7162 | u32 val, base, offset; | |
7163 | int pipe = crtc->pipe, plane = crtc->plane; | |
7164 | int fourcc, pixel_format; | |
7165 | int aligned_height; | |
7166 | ||
66e514c1 DA |
7167 | crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL); |
7168 | if (!crtc->base.primary->fb) { | |
4c6baa59 JB |
7169 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7170 | return; | |
7171 | } | |
7172 | ||
7173 | val = I915_READ(DSPCNTR(plane)); | |
7174 | ||
7175 | if (INTEL_INFO(dev)->gen >= 4) | |
7176 | if (val & DISPPLANE_TILED) | |
7177 | plane_config->tiled = true; | |
7178 | ||
7179 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
7180 | fourcc = intel_format_to_fourcc(pixel_format); | |
66e514c1 DA |
7181 | crtc->base.primary->fb->pixel_format = fourcc; |
7182 | crtc->base.primary->fb->bits_per_pixel = | |
4c6baa59 JB |
7183 | drm_format_plane_cpp(fourcc, 0) * 8; |
7184 | ||
7185 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
7186 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
7187 | offset = I915_READ(DSPOFFSET(plane)); | |
7188 | } else { | |
7189 | if (plane_config->tiled) | |
7190 | offset = I915_READ(DSPTILEOFF(plane)); | |
7191 | else | |
7192 | offset = I915_READ(DSPLINOFF(plane)); | |
7193 | } | |
7194 | plane_config->base = base; | |
7195 | ||
7196 | val = I915_READ(PIPESRC(pipe)); | |
66e514c1 DA |
7197 | crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1; |
7198 | crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
7199 | |
7200 | val = I915_READ(DSPSTRIDE(pipe)); | |
66e514c1 | 7201 | crtc->base.primary->fb->pitches[0] = val & 0xffffff80; |
4c6baa59 | 7202 | |
66e514c1 | 7203 | aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, |
4c6baa59 JB |
7204 | plane_config->tiled); |
7205 | ||
66e514c1 | 7206 | plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] * |
4c6baa59 JB |
7207 | aligned_height, PAGE_SIZE); |
7208 | ||
7209 | DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
66e514c1 DA |
7210 | pipe, plane, crtc->base.primary->fb->width, |
7211 | crtc->base.primary->fb->height, | |
7212 | crtc->base.primary->fb->bits_per_pixel, base, | |
7213 | crtc->base.primary->fb->pitches[0], | |
4c6baa59 JB |
7214 | plane_config->size); |
7215 | } | |
7216 | ||
0e8ffe1b DV |
7217 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
7218 | struct intel_crtc_config *pipe_config) | |
7219 | { | |
7220 | struct drm_device *dev = crtc->base.dev; | |
7221 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7222 | uint32_t tmp; | |
7223 | ||
e143a21c | 7224 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 7225 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 7226 | |
0e8ffe1b DV |
7227 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
7228 | if (!(tmp & PIPECONF_ENABLE)) | |
7229 | return false; | |
7230 | ||
42571aef VS |
7231 | switch (tmp & PIPECONF_BPC_MASK) { |
7232 | case PIPECONF_6BPC: | |
7233 | pipe_config->pipe_bpp = 18; | |
7234 | break; | |
7235 | case PIPECONF_8BPC: | |
7236 | pipe_config->pipe_bpp = 24; | |
7237 | break; | |
7238 | case PIPECONF_10BPC: | |
7239 | pipe_config->pipe_bpp = 30; | |
7240 | break; | |
7241 | case PIPECONF_12BPC: | |
7242 | pipe_config->pipe_bpp = 36; | |
7243 | break; | |
7244 | default: | |
7245 | break; | |
7246 | } | |
7247 | ||
b5a9fa09 DV |
7248 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
7249 | pipe_config->limited_color_range = true; | |
7250 | ||
ab9412ba | 7251 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
7252 | struct intel_shared_dpll *pll; |
7253 | ||
88adfff1 DV |
7254 | pipe_config->has_pch_encoder = true; |
7255 | ||
627eb5a3 DV |
7256 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
7257 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
7258 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
7259 | |
7260 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 7261 | |
c0d43d62 | 7262 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
7263 | pipe_config->shared_dpll = |
7264 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
7265 | } else { |
7266 | tmp = I915_READ(PCH_DPLL_SEL); | |
7267 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
7268 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
7269 | else | |
7270 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
7271 | } | |
66e985c0 DV |
7272 | |
7273 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
7274 | ||
7275 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
7276 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
7277 | |
7278 | tmp = pipe_config->dpll_hw_state.dpll; | |
7279 | pipe_config->pixel_multiplier = | |
7280 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
7281 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
7282 | |
7283 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
7284 | } else { |
7285 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
7286 | } |
7287 | ||
1bd1bd80 DV |
7288 | intel_get_pipe_timings(crtc, pipe_config); |
7289 | ||
2fa2fe9a DV |
7290 | ironlake_get_pfit_config(crtc, pipe_config); |
7291 | ||
0e8ffe1b DV |
7292 | return true; |
7293 | } | |
7294 | ||
be256dc7 PZ |
7295 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
7296 | { | |
7297 | struct drm_device *dev = dev_priv->dev; | |
7298 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; | |
7299 | struct intel_crtc *crtc; | |
be256dc7 | 7300 | |
d3fcc808 | 7301 | for_each_intel_crtc(dev, crtc) |
798183c5 | 7302 | WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
7303 | pipe_name(crtc->pipe)); |
7304 | ||
7305 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); | |
7306 | WARN(plls->spll_refcount, "SPLL enabled\n"); | |
7307 | WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n"); | |
7308 | WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n"); | |
7309 | WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); | |
7310 | WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
7311 | "CPU PWM1 enabled\n"); | |
7312 | WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, | |
7313 | "CPU PWM2 enabled\n"); | |
7314 | WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, | |
7315 | "PCH PWM1 enabled\n"); | |
7316 | WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, | |
7317 | "Utility pin enabled\n"); | |
7318 | WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); | |
7319 | ||
9926ada1 PZ |
7320 | /* |
7321 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
7322 | * interrupts remain enabled. We used to check for that, but since it's | |
7323 | * gen-specific and since we only disable LCPLL after we fully disable | |
7324 | * the interrupts, the check below should be enough. | |
7325 | */ | |
7326 | WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n"); | |
be256dc7 PZ |
7327 | } |
7328 | ||
3c4c9b81 PZ |
7329 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
7330 | { | |
7331 | struct drm_device *dev = dev_priv->dev; | |
7332 | ||
7333 | if (IS_HASWELL(dev)) { | |
7334 | mutex_lock(&dev_priv->rps.hw_lock); | |
7335 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
7336 | val)) | |
7337 | DRM_ERROR("Failed to disable D_COMP\n"); | |
7338 | mutex_unlock(&dev_priv->rps.hw_lock); | |
7339 | } else { | |
7340 | I915_WRITE(D_COMP, val); | |
7341 | } | |
7342 | POSTING_READ(D_COMP); | |
be256dc7 PZ |
7343 | } |
7344 | ||
7345 | /* | |
7346 | * This function implements pieces of two sequences from BSpec: | |
7347 | * - Sequence for display software to disable LCPLL | |
7348 | * - Sequence for display software to allow package C8+ | |
7349 | * The steps implemented here are just the steps that actually touch the LCPLL | |
7350 | * register. Callers should take care of disabling all the display engine | |
7351 | * functions, doing the mode unset, fixing interrupts, etc. | |
7352 | */ | |
6ff58d53 PZ |
7353 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
7354 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
7355 | { |
7356 | uint32_t val; | |
7357 | ||
7358 | assert_can_disable_lcpll(dev_priv); | |
7359 | ||
7360 | val = I915_READ(LCPLL_CTL); | |
7361 | ||
7362 | if (switch_to_fclk) { | |
7363 | val |= LCPLL_CD_SOURCE_FCLK; | |
7364 | I915_WRITE(LCPLL_CTL, val); | |
7365 | ||
7366 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
7367 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
7368 | DRM_ERROR("Switching to FCLK failed\n"); | |
7369 | ||
7370 | val = I915_READ(LCPLL_CTL); | |
7371 | } | |
7372 | ||
7373 | val |= LCPLL_PLL_DISABLE; | |
7374 | I915_WRITE(LCPLL_CTL, val); | |
7375 | POSTING_READ(LCPLL_CTL); | |
7376 | ||
7377 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
7378 | DRM_ERROR("LCPLL still locked\n"); | |
7379 | ||
7380 | val = I915_READ(D_COMP); | |
7381 | val |= D_COMP_COMP_DISABLE; | |
3c4c9b81 | 7382 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
7383 | ndelay(100); |
7384 | ||
7385 | if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1)) | |
7386 | DRM_ERROR("D_COMP RCOMP still in progress\n"); | |
7387 | ||
7388 | if (allow_power_down) { | |
7389 | val = I915_READ(LCPLL_CTL); | |
7390 | val |= LCPLL_POWER_DOWN_ALLOW; | |
7391 | I915_WRITE(LCPLL_CTL, val); | |
7392 | POSTING_READ(LCPLL_CTL); | |
7393 | } | |
7394 | } | |
7395 | ||
7396 | /* | |
7397 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
7398 | * source. | |
7399 | */ | |
6ff58d53 | 7400 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
7401 | { |
7402 | uint32_t val; | |
a8a8bd54 | 7403 | unsigned long irqflags; |
be256dc7 PZ |
7404 | |
7405 | val = I915_READ(LCPLL_CTL); | |
7406 | ||
7407 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
7408 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
7409 | return; | |
7410 | ||
a8a8bd54 PZ |
7411 | /* |
7412 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
7413 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
7414 | * | |
7415 | * The other problem is that hsw_restore_lcpll() is called as part of | |
7416 | * the runtime PM resume sequence, so we can't just call | |
7417 | * gen6_gt_force_wake_get() because that function calls | |
7418 | * intel_runtime_pm_get(), and we can't change the runtime PM refcount | |
7419 | * while we are on the resume sequence. So to solve this problem we have | |
7420 | * to call special forcewake code that doesn't touch runtime PM and | |
7421 | * doesn't enable the forcewake delayed work. | |
7422 | */ | |
7423 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
7424 | if (dev_priv->uncore.forcewake_count++ == 0) | |
7425 | dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL); | |
7426 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
215733fa | 7427 | |
be256dc7 PZ |
7428 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
7429 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
7430 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 7431 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
7432 | } |
7433 | ||
7434 | val = I915_READ(D_COMP); | |
7435 | val |= D_COMP_COMP_FORCE; | |
7436 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 7437 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
7438 | |
7439 | val = I915_READ(LCPLL_CTL); | |
7440 | val &= ~LCPLL_PLL_DISABLE; | |
7441 | I915_WRITE(LCPLL_CTL, val); | |
7442 | ||
7443 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
7444 | DRM_ERROR("LCPLL not locked yet\n"); | |
7445 | ||
7446 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
7447 | val = I915_READ(LCPLL_CTL); | |
7448 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
7449 | I915_WRITE(LCPLL_CTL, val); | |
7450 | ||
7451 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
7452 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
7453 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
7454 | } | |
215733fa | 7455 | |
a8a8bd54 PZ |
7456 | /* See the big comment above. */ |
7457 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
7458 | if (--dev_priv->uncore.forcewake_count == 0) | |
7459 | dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL); | |
7460 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
be256dc7 PZ |
7461 | } |
7462 | ||
765dab67 PZ |
7463 | /* |
7464 | * Package states C8 and deeper are really deep PC states that can only be | |
7465 | * reached when all the devices on the system allow it, so even if the graphics | |
7466 | * device allows PC8+, it doesn't mean the system will actually get to these | |
7467 | * states. Our driver only allows PC8+ when going into runtime PM. | |
7468 | * | |
7469 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
7470 | * well is disabled and most interrupts are disabled, and these are also | |
7471 | * requirements for runtime PM. When these conditions are met, we manually do | |
7472 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
7473 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
7474 | * hang the machine. | |
7475 | * | |
7476 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
7477 | * the state of some registers, so when we come back from PC8+ we need to | |
7478 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
7479 | * need to take care of the registers kept by RC6. Notice that this happens even | |
7480 | * if we don't put the device in PCI D3 state (which is what currently happens | |
7481 | * because of the runtime PM support). | |
7482 | * | |
7483 | * For more, read "Display Sequences for Package C8" on the hardware | |
7484 | * documentation. | |
7485 | */ | |
a14cb6fc | 7486 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 7487 | { |
c67a470b PZ |
7488 | struct drm_device *dev = dev_priv->dev; |
7489 | uint32_t val; | |
7490 | ||
c67a470b PZ |
7491 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
7492 | ||
c67a470b PZ |
7493 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
7494 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
7495 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
7496 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
7497 | } | |
7498 | ||
7499 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
7500 | hsw_disable_lcpll(dev_priv, true, true); |
7501 | } | |
7502 | ||
a14cb6fc | 7503 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
7504 | { |
7505 | struct drm_device *dev = dev_priv->dev; | |
7506 | uint32_t val; | |
7507 | ||
c67a470b PZ |
7508 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
7509 | ||
7510 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
7511 | lpt_init_pch_refclk(dev); |
7512 | ||
7513 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
7514 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
7515 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
7516 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
7517 | } | |
7518 | ||
7519 | intel_prepare_ddi(dev); | |
c67a470b PZ |
7520 | } |
7521 | ||
9a952a0d PZ |
7522 | static void snb_modeset_global_resources(struct drm_device *dev) |
7523 | { | |
7524 | modeset_update_crtc_power_domains(dev); | |
7525 | } | |
7526 | ||
4f074129 ID |
7527 | static void haswell_modeset_global_resources(struct drm_device *dev) |
7528 | { | |
da723569 | 7529 | modeset_update_crtc_power_domains(dev); |
d6dd9eb1 DV |
7530 | } |
7531 | ||
09b4ddf9 | 7532 | static int haswell_crtc_mode_set(struct drm_crtc *crtc, |
09b4ddf9 PZ |
7533 | int x, int y, |
7534 | struct drm_framebuffer *fb) | |
7535 | { | |
09b4ddf9 | 7536 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
09b4ddf9 | 7537 | |
566b734a | 7538 | if (!intel_ddi_pll_select(intel_crtc)) |
6441ab5f | 7539 | return -EINVAL; |
566b734a | 7540 | intel_ddi_pll_enable(intel_crtc); |
6441ab5f | 7541 | |
644cef34 DV |
7542 | intel_crtc->lowfreq_avail = false; |
7543 | ||
c8f7a0db | 7544 | return 0; |
79e53945 JB |
7545 | } |
7546 | ||
0e8ffe1b DV |
7547 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
7548 | struct intel_crtc_config *pipe_config) | |
7549 | { | |
7550 | struct drm_device *dev = crtc->base.dev; | |
7551 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 7552 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
7553 | uint32_t tmp; |
7554 | ||
b5482bd0 ID |
7555 | if (!intel_display_power_enabled(dev_priv, |
7556 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
7557 | return false; | |
7558 | ||
e143a21c | 7559 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
7560 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
7561 | ||
eccb140b DV |
7562 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
7563 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
7564 | enum pipe trans_edp_pipe; | |
7565 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
7566 | default: | |
7567 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
7568 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
7569 | case TRANS_DDI_EDP_INPUT_A_ON: | |
7570 | trans_edp_pipe = PIPE_A; | |
7571 | break; | |
7572 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
7573 | trans_edp_pipe = PIPE_B; | |
7574 | break; | |
7575 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
7576 | trans_edp_pipe = PIPE_C; | |
7577 | break; | |
7578 | } | |
7579 | ||
7580 | if (trans_edp_pipe == crtc->pipe) | |
7581 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
7582 | } | |
7583 | ||
da7e29bd | 7584 | if (!intel_display_power_enabled(dev_priv, |
eccb140b | 7585 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
7586 | return false; |
7587 | ||
eccb140b | 7588 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
7589 | if (!(tmp & PIPECONF_ENABLE)) |
7590 | return false; | |
7591 | ||
88adfff1 | 7592 | /* |
f196e6be | 7593 | * Haswell has only FDI/PCH transcoder A. It is which is connected to |
88adfff1 DV |
7594 | * DDI E. So just check whether this pipe is wired to DDI E and whether |
7595 | * the PCH transcoder is on. | |
7596 | */ | |
eccb140b | 7597 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); |
88adfff1 | 7598 | if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) && |
ab9412ba | 7599 | I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
88adfff1 DV |
7600 | pipe_config->has_pch_encoder = true; |
7601 | ||
627eb5a3 DV |
7602 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); |
7603 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
7604 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
7605 | |
7606 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
627eb5a3 DV |
7607 | } |
7608 | ||
1bd1bd80 DV |
7609 | intel_get_pipe_timings(crtc, pipe_config); |
7610 | ||
2fa2fe9a | 7611 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
da7e29bd | 7612 | if (intel_display_power_enabled(dev_priv, pfit_domain)) |
2fa2fe9a | 7613 | ironlake_get_pfit_config(crtc, pipe_config); |
88adfff1 | 7614 | |
e59150dc JB |
7615 | if (IS_HASWELL(dev)) |
7616 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
7617 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 7618 | |
6c49f241 DV |
7619 | pipe_config->pixel_multiplier = 1; |
7620 | ||
0e8ffe1b DV |
7621 | return true; |
7622 | } | |
7623 | ||
1a91510d JN |
7624 | static struct { |
7625 | int clock; | |
7626 | u32 config; | |
7627 | } hdmi_audio_clock[] = { | |
7628 | { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, | |
7629 | { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ | |
7630 | { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, | |
7631 | { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, | |
7632 | { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, | |
7633 | { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, | |
7634 | { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, | |
7635 | { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, | |
7636 | { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, | |
7637 | { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, | |
7638 | }; | |
7639 | ||
7640 | /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ | |
7641 | static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode) | |
7642 | { | |
7643 | int i; | |
7644 | ||
7645 | for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { | |
7646 | if (mode->clock == hdmi_audio_clock[i].clock) | |
7647 | break; | |
7648 | } | |
7649 | ||
7650 | if (i == ARRAY_SIZE(hdmi_audio_clock)) { | |
7651 | DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock); | |
7652 | i = 1; | |
7653 | } | |
7654 | ||
7655 | DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", | |
7656 | hdmi_audio_clock[i].clock, | |
7657 | hdmi_audio_clock[i].config); | |
7658 | ||
7659 | return hdmi_audio_clock[i].config; | |
7660 | } | |
7661 | ||
3a9627f4 WF |
7662 | static bool intel_eld_uptodate(struct drm_connector *connector, |
7663 | int reg_eldv, uint32_t bits_eldv, | |
7664 | int reg_elda, uint32_t bits_elda, | |
7665 | int reg_edid) | |
7666 | { | |
7667 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7668 | uint8_t *eld = connector->eld; | |
7669 | uint32_t i; | |
7670 | ||
7671 | i = I915_READ(reg_eldv); | |
7672 | i &= bits_eldv; | |
7673 | ||
7674 | if (!eld[0]) | |
7675 | return !i; | |
7676 | ||
7677 | if (!i) | |
7678 | return false; | |
7679 | ||
7680 | i = I915_READ(reg_elda); | |
7681 | i &= ~bits_elda; | |
7682 | I915_WRITE(reg_elda, i); | |
7683 | ||
7684 | for (i = 0; i < eld[2]; i++) | |
7685 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) | |
7686 | return false; | |
7687 | ||
7688 | return true; | |
7689 | } | |
7690 | ||
e0dac65e | 7691 | static void g4x_write_eld(struct drm_connector *connector, |
34427052 JN |
7692 | struct drm_crtc *crtc, |
7693 | struct drm_display_mode *mode) | |
e0dac65e WF |
7694 | { |
7695 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7696 | uint8_t *eld = connector->eld; | |
7697 | uint32_t eldv; | |
7698 | uint32_t len; | |
7699 | uint32_t i; | |
7700 | ||
7701 | i = I915_READ(G4X_AUD_VID_DID); | |
7702 | ||
7703 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) | |
7704 | eldv = G4X_ELDV_DEVCL_DEVBLC; | |
7705 | else | |
7706 | eldv = G4X_ELDV_DEVCTG; | |
7707 | ||
3a9627f4 WF |
7708 | if (intel_eld_uptodate(connector, |
7709 | G4X_AUD_CNTL_ST, eldv, | |
7710 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, | |
7711 | G4X_HDMIW_HDMIEDID)) | |
7712 | return; | |
7713 | ||
e0dac65e WF |
7714 | i = I915_READ(G4X_AUD_CNTL_ST); |
7715 | i &= ~(eldv | G4X_ELD_ADDR); | |
7716 | len = (i >> 9) & 0x1f; /* ELD buffer size */ | |
7717 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
7718 | ||
7719 | if (!eld[0]) | |
7720 | return; | |
7721 | ||
7722 | len = min_t(uint8_t, eld[2], len); | |
7723 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7724 | for (i = 0; i < len; i++) | |
7725 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); | |
7726 | ||
7727 | i = I915_READ(G4X_AUD_CNTL_ST); | |
7728 | i |= eldv; | |
7729 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
7730 | } | |
7731 | ||
83358c85 | 7732 | static void haswell_write_eld(struct drm_connector *connector, |
34427052 JN |
7733 | struct drm_crtc *crtc, |
7734 | struct drm_display_mode *mode) | |
83358c85 WX |
7735 | { |
7736 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7737 | uint8_t *eld = connector->eld; | |
83358c85 WX |
7738 | uint32_t eldv; |
7739 | uint32_t i; | |
7740 | int len; | |
7741 | int pipe = to_intel_crtc(crtc)->pipe; | |
7742 | int tmp; | |
7743 | ||
7744 | int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); | |
7745 | int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); | |
7746 | int aud_config = HSW_AUD_CFG(pipe); | |
7747 | int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD; | |
7748 | ||
83358c85 WX |
7749 | /* Audio output enable */ |
7750 | DRM_DEBUG_DRIVER("HDMI audio: enable codec\n"); | |
7751 | tmp = I915_READ(aud_cntrl_st2); | |
7752 | tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); | |
7753 | I915_WRITE(aud_cntrl_st2, tmp); | |
c7905792 | 7754 | POSTING_READ(aud_cntrl_st2); |
83358c85 | 7755 | |
c7905792 | 7756 | assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe); |
83358c85 WX |
7757 | |
7758 | /* Set ELD valid state */ | |
7759 | tmp = I915_READ(aud_cntrl_st2); | |
7e7cb34f | 7760 | DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp); |
83358c85 WX |
7761 | tmp |= (AUDIO_ELD_VALID_A << (pipe * 4)); |
7762 | I915_WRITE(aud_cntrl_st2, tmp); | |
7763 | tmp = I915_READ(aud_cntrl_st2); | |
7e7cb34f | 7764 | DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp); |
83358c85 WX |
7765 | |
7766 | /* Enable HDMI mode */ | |
7767 | tmp = I915_READ(aud_config); | |
7e7cb34f | 7768 | DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp); |
83358c85 WX |
7769 | /* clear N_programing_enable and N_value_index */ |
7770 | tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE); | |
7771 | I915_WRITE(aud_config, tmp); | |
7772 | ||
7773 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); | |
7774 | ||
7775 | eldv = AUDIO_ELD_VALID_A << (pipe * 4); | |
7776 | ||
7777 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { | |
7778 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
7779 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
7780 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ | |
1a91510d JN |
7781 | } else { |
7782 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); | |
7783 | } | |
83358c85 WX |
7784 | |
7785 | if (intel_eld_uptodate(connector, | |
7786 | aud_cntrl_st2, eldv, | |
7787 | aud_cntl_st, IBX_ELD_ADDRESS, | |
7788 | hdmiw_hdmiedid)) | |
7789 | return; | |
7790 | ||
7791 | i = I915_READ(aud_cntrl_st2); | |
7792 | i &= ~eldv; | |
7793 | I915_WRITE(aud_cntrl_st2, i); | |
7794 | ||
7795 | if (!eld[0]) | |
7796 | return; | |
7797 | ||
7798 | i = I915_READ(aud_cntl_st); | |
7799 | i &= ~IBX_ELD_ADDRESS; | |
7800 | I915_WRITE(aud_cntl_st, i); | |
7801 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ | |
7802 | DRM_DEBUG_DRIVER("port num:%d\n", i); | |
7803 | ||
7804 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
7805 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7806 | for (i = 0; i < len; i++) | |
7807 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
7808 | ||
7809 | i = I915_READ(aud_cntrl_st2); | |
7810 | i |= eldv; | |
7811 | I915_WRITE(aud_cntrl_st2, i); | |
7812 | ||
7813 | } | |
7814 | ||
e0dac65e | 7815 | static void ironlake_write_eld(struct drm_connector *connector, |
34427052 JN |
7816 | struct drm_crtc *crtc, |
7817 | struct drm_display_mode *mode) | |
e0dac65e WF |
7818 | { |
7819 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7820 | uint8_t *eld = connector->eld; | |
7821 | uint32_t eldv; | |
7822 | uint32_t i; | |
7823 | int len; | |
7824 | int hdmiw_hdmiedid; | |
b6daa025 | 7825 | int aud_config; |
e0dac65e WF |
7826 | int aud_cntl_st; |
7827 | int aud_cntrl_st2; | |
9b138a83 | 7828 | int pipe = to_intel_crtc(crtc)->pipe; |
e0dac65e | 7829 | |
b3f33cbf | 7830 | if (HAS_PCH_IBX(connector->dev)) { |
9b138a83 WX |
7831 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
7832 | aud_config = IBX_AUD_CFG(pipe); | |
7833 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); | |
1202b4c6 | 7834 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
9ca2fe73 ML |
7835 | } else if (IS_VALLEYVIEW(connector->dev)) { |
7836 | hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); | |
7837 | aud_config = VLV_AUD_CFG(pipe); | |
7838 | aud_cntl_st = VLV_AUD_CNTL_ST(pipe); | |
7839 | aud_cntrl_st2 = VLV_AUD_CNTL_ST2; | |
e0dac65e | 7840 | } else { |
9b138a83 WX |
7841 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); |
7842 | aud_config = CPT_AUD_CFG(pipe); | |
7843 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); | |
1202b4c6 | 7844 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
e0dac65e WF |
7845 | } |
7846 | ||
9b138a83 | 7847 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
e0dac65e | 7848 | |
9ca2fe73 ML |
7849 | if (IS_VALLEYVIEW(connector->dev)) { |
7850 | struct intel_encoder *intel_encoder; | |
7851 | struct intel_digital_port *intel_dig_port; | |
7852 | ||
7853 | intel_encoder = intel_attached_encoder(connector); | |
7854 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
7855 | i = intel_dig_port->port; | |
7856 | } else { | |
7857 | i = I915_READ(aud_cntl_st); | |
7858 | i = (i >> 29) & DIP_PORT_SEL_MASK; | |
7859 | /* DIP_Port_Select, 0x1 = PortB */ | |
7860 | } | |
7861 | ||
e0dac65e WF |
7862 | if (!i) { |
7863 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); | |
7864 | /* operate blindly on all ports */ | |
1202b4c6 WF |
7865 | eldv = IBX_ELD_VALIDB; |
7866 | eldv |= IBX_ELD_VALIDB << 4; | |
7867 | eldv |= IBX_ELD_VALIDB << 8; | |
e0dac65e | 7868 | } else { |
2582a850 | 7869 | DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i)); |
1202b4c6 | 7870 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
e0dac65e WF |
7871 | } |
7872 | ||
3a9627f4 WF |
7873 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
7874 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
7875 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
b6daa025 | 7876 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
1a91510d JN |
7877 | } else { |
7878 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); | |
7879 | } | |
e0dac65e | 7880 | |
3a9627f4 WF |
7881 | if (intel_eld_uptodate(connector, |
7882 | aud_cntrl_st2, eldv, | |
7883 | aud_cntl_st, IBX_ELD_ADDRESS, | |
7884 | hdmiw_hdmiedid)) | |
7885 | return; | |
7886 | ||
e0dac65e WF |
7887 | i = I915_READ(aud_cntrl_st2); |
7888 | i &= ~eldv; | |
7889 | I915_WRITE(aud_cntrl_st2, i); | |
7890 | ||
7891 | if (!eld[0]) | |
7892 | return; | |
7893 | ||
e0dac65e | 7894 | i = I915_READ(aud_cntl_st); |
1202b4c6 | 7895 | i &= ~IBX_ELD_ADDRESS; |
e0dac65e WF |
7896 | I915_WRITE(aud_cntl_st, i); |
7897 | ||
7898 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
7899 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7900 | for (i = 0; i < len; i++) | |
7901 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
7902 | ||
7903 | i = I915_READ(aud_cntrl_st2); | |
7904 | i |= eldv; | |
7905 | I915_WRITE(aud_cntrl_st2, i); | |
7906 | } | |
7907 | ||
7908 | void intel_write_eld(struct drm_encoder *encoder, | |
7909 | struct drm_display_mode *mode) | |
7910 | { | |
7911 | struct drm_crtc *crtc = encoder->crtc; | |
7912 | struct drm_connector *connector; | |
7913 | struct drm_device *dev = encoder->dev; | |
7914 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7915 | ||
7916 | connector = drm_select_eld(encoder, mode); | |
7917 | if (!connector) | |
7918 | return; | |
7919 | ||
7920 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", | |
7921 | connector->base.id, | |
c23cc417 | 7922 | connector->name, |
e0dac65e | 7923 | connector->encoder->base.id, |
8e329a03 | 7924 | connector->encoder->name); |
e0dac65e WF |
7925 | |
7926 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; | |
7927 | ||
7928 | if (dev_priv->display.write_eld) | |
34427052 | 7929 | dev_priv->display.write_eld(connector, crtc, mode); |
e0dac65e WF |
7930 | } |
7931 | ||
560b85bb CW |
7932 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
7933 | { | |
7934 | struct drm_device *dev = crtc->dev; | |
7935 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7936 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4b0e333e | 7937 | uint32_t cntl; |
560b85bb | 7938 | |
4b0e333e | 7939 | if (base != intel_crtc->cursor_base) { |
560b85bb CW |
7940 | /* On these chipsets we can only modify the base whilst |
7941 | * the cursor is disabled. | |
7942 | */ | |
4b0e333e CW |
7943 | if (intel_crtc->cursor_cntl) { |
7944 | I915_WRITE(_CURACNTR, 0); | |
7945 | POSTING_READ(_CURACNTR); | |
7946 | intel_crtc->cursor_cntl = 0; | |
7947 | } | |
7948 | ||
9db4a9c7 | 7949 | I915_WRITE(_CURABASE, base); |
4b0e333e CW |
7950 | POSTING_READ(_CURABASE); |
7951 | } | |
560b85bb | 7952 | |
4b0e333e CW |
7953 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ |
7954 | cntl = 0; | |
7955 | if (base) | |
7956 | cntl = (CURSOR_ENABLE | | |
560b85bb | 7957 | CURSOR_GAMMA_ENABLE | |
4b0e333e CW |
7958 | CURSOR_FORMAT_ARGB); |
7959 | if (intel_crtc->cursor_cntl != cntl) { | |
7960 | I915_WRITE(_CURACNTR, cntl); | |
7961 | POSTING_READ(_CURACNTR); | |
7962 | intel_crtc->cursor_cntl = cntl; | |
7963 | } | |
560b85bb CW |
7964 | } |
7965 | ||
7966 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) | |
7967 | { | |
7968 | struct drm_device *dev = crtc->dev; | |
7969 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7970 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7971 | int pipe = intel_crtc->pipe; | |
4b0e333e | 7972 | uint32_t cntl; |
4726e0b0 | 7973 | |
4b0e333e CW |
7974 | cntl = 0; |
7975 | if (base) { | |
7976 | cntl = MCURSOR_GAMMA_ENABLE; | |
7977 | switch (intel_crtc->cursor_width) { | |
4726e0b0 SK |
7978 | case 64: |
7979 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
7980 | break; | |
7981 | case 128: | |
7982 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
7983 | break; | |
7984 | case 256: | |
7985 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
7986 | break; | |
7987 | default: | |
7988 | WARN_ON(1); | |
7989 | return; | |
560b85bb | 7990 | } |
4b0e333e CW |
7991 | cntl |= pipe << 28; /* Connect to correct pipe */ |
7992 | } | |
7993 | if (intel_crtc->cursor_cntl != cntl) { | |
9db4a9c7 | 7994 | I915_WRITE(CURCNTR(pipe), cntl); |
4b0e333e CW |
7995 | POSTING_READ(CURCNTR(pipe)); |
7996 | intel_crtc->cursor_cntl = cntl; | |
560b85bb | 7997 | } |
4b0e333e | 7998 | |
560b85bb | 7999 | /* and commit changes on next vblank */ |
9db4a9c7 | 8000 | I915_WRITE(CURBASE(pipe), base); |
b2ea8ef5 | 8001 | POSTING_READ(CURBASE(pipe)); |
560b85bb CW |
8002 | } |
8003 | ||
65a21cd6 JB |
8004 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
8005 | { | |
8006 | struct drm_device *dev = crtc->dev; | |
8007 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8008 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8009 | int pipe = intel_crtc->pipe; | |
4b0e333e CW |
8010 | uint32_t cntl; |
8011 | ||
8012 | cntl = 0; | |
8013 | if (base) { | |
8014 | cntl = MCURSOR_GAMMA_ENABLE; | |
8015 | switch (intel_crtc->cursor_width) { | |
4726e0b0 SK |
8016 | case 64: |
8017 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
8018 | break; | |
8019 | case 128: | |
8020 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
8021 | break; | |
8022 | case 256: | |
8023 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
8024 | break; | |
8025 | default: | |
8026 | WARN_ON(1); | |
8027 | return; | |
65a21cd6 | 8028 | } |
4b0e333e CW |
8029 | } |
8030 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
8031 | cntl |= CURSOR_PIPE_CSC_ENABLE; | |
65a21cd6 | 8032 | |
4b0e333e CW |
8033 | if (intel_crtc->cursor_cntl != cntl) { |
8034 | I915_WRITE(CURCNTR(pipe), cntl); | |
8035 | POSTING_READ(CURCNTR(pipe)); | |
8036 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 8037 | } |
4b0e333e | 8038 | |
65a21cd6 | 8039 | /* and commit changes on next vblank */ |
5efb3e28 VS |
8040 | I915_WRITE(CURBASE(pipe), base); |
8041 | POSTING_READ(CURBASE(pipe)); | |
65a21cd6 JB |
8042 | } |
8043 | ||
cda4b7d3 | 8044 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
8045 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
8046 | bool on) | |
cda4b7d3 CW |
8047 | { |
8048 | struct drm_device *dev = crtc->dev; | |
8049 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8050 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8051 | int pipe = intel_crtc->pipe; | |
3d7d6510 MR |
8052 | int x = crtc->cursor_x; |
8053 | int y = crtc->cursor_y; | |
d6e4db15 | 8054 | u32 base = 0, pos = 0; |
cda4b7d3 | 8055 | |
d6e4db15 | 8056 | if (on) |
cda4b7d3 | 8057 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 8058 | |
d6e4db15 VS |
8059 | if (x >= intel_crtc->config.pipe_src_w) |
8060 | base = 0; | |
8061 | ||
8062 | if (y >= intel_crtc->config.pipe_src_h) | |
cda4b7d3 CW |
8063 | base = 0; |
8064 | ||
8065 | if (x < 0) { | |
efc9064e | 8066 | if (x + intel_crtc->cursor_width <= 0) |
cda4b7d3 CW |
8067 | base = 0; |
8068 | ||
8069 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
8070 | x = -x; | |
8071 | } | |
8072 | pos |= x << CURSOR_X_SHIFT; | |
8073 | ||
8074 | if (y < 0) { | |
efc9064e | 8075 | if (y + intel_crtc->cursor_height <= 0) |
cda4b7d3 CW |
8076 | base = 0; |
8077 | ||
8078 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
8079 | y = -y; | |
8080 | } | |
8081 | pos |= y << CURSOR_Y_SHIFT; | |
8082 | ||
4b0e333e | 8083 | if (base == 0 && intel_crtc->cursor_base == 0) |
cda4b7d3 CW |
8084 | return; |
8085 | ||
5efb3e28 VS |
8086 | I915_WRITE(CURPOS(pipe), pos); |
8087 | ||
8088 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
65a21cd6 | 8089 | ivb_update_cursor(crtc, base); |
5efb3e28 VS |
8090 | else if (IS_845G(dev) || IS_I865G(dev)) |
8091 | i845_update_cursor(crtc, base); | |
8092 | else | |
8093 | i9xx_update_cursor(crtc, base); | |
4b0e333e | 8094 | intel_crtc->cursor_base = base; |
cda4b7d3 CW |
8095 | } |
8096 | ||
e3287951 MR |
8097 | /* |
8098 | * intel_crtc_cursor_set_obj - Set cursor to specified GEM object | |
8099 | * | |
8100 | * Note that the object's reference will be consumed if the update fails. If | |
8101 | * the update succeeds, the reference of the old object (if any) will be | |
8102 | * consumed. | |
8103 | */ | |
8104 | static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc, | |
8105 | struct drm_i915_gem_object *obj, | |
8106 | uint32_t width, uint32_t height) | |
79e53945 JB |
8107 | { |
8108 | struct drm_device *dev = crtc->dev; | |
8109 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8110 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
64f962e3 | 8111 | unsigned old_width; |
cda4b7d3 | 8112 | uint32_t addr; |
3f8bc370 | 8113 | int ret; |
79e53945 | 8114 | |
79e53945 | 8115 | /* if we want to turn off the cursor ignore width and height */ |
e3287951 | 8116 | if (!obj) { |
28c97730 | 8117 | DRM_DEBUG_KMS("cursor off\n"); |
3f8bc370 | 8118 | addr = 0; |
05394f39 | 8119 | obj = NULL; |
5004417d | 8120 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 8121 | goto finish; |
79e53945 JB |
8122 | } |
8123 | ||
4726e0b0 SK |
8124 | /* Check for which cursor types we support */ |
8125 | if (!((width == 64 && height == 64) || | |
8126 | (width == 128 && height == 128 && !IS_GEN2(dev)) || | |
8127 | (width == 256 && height == 256 && !IS_GEN2(dev)))) { | |
8128 | DRM_DEBUG("Cursor dimension not supported\n"); | |
79e53945 JB |
8129 | return -EINVAL; |
8130 | } | |
8131 | ||
05394f39 | 8132 | if (obj->base.size < width * height * 4) { |
e3287951 | 8133 | DRM_DEBUG_KMS("buffer is too small\n"); |
34b8686e DA |
8134 | ret = -ENOMEM; |
8135 | goto fail; | |
79e53945 JB |
8136 | } |
8137 | ||
71acb5eb | 8138 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 8139 | mutex_lock(&dev->struct_mutex); |
3d13ef2e | 8140 | if (!INTEL_INFO(dev)->cursor_needs_physical) { |
693db184 CW |
8141 | unsigned alignment; |
8142 | ||
d9e86c0e | 8143 | if (obj->tiling_mode) { |
3b25b31f | 8144 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
d9e86c0e CW |
8145 | ret = -EINVAL; |
8146 | goto fail_locked; | |
8147 | } | |
8148 | ||
693db184 CW |
8149 | /* Note that the w/a also requires 2 PTE of padding following |
8150 | * the bo. We currently fill all unused PTE with the shadow | |
8151 | * page and so we should always have valid PTE following the | |
8152 | * cursor preventing the VT-d warning. | |
8153 | */ | |
8154 | alignment = 0; | |
8155 | if (need_vtd_wa(dev)) | |
8156 | alignment = 64*1024; | |
8157 | ||
8158 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); | |
e7b526bb | 8159 | if (ret) { |
3b25b31f | 8160 | DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n"); |
2da3b9b9 | 8161 | goto fail_locked; |
e7b526bb CW |
8162 | } |
8163 | ||
d9e86c0e CW |
8164 | ret = i915_gem_object_put_fence(obj); |
8165 | if (ret) { | |
3b25b31f | 8166 | DRM_DEBUG_KMS("failed to release fence for cursor"); |
d9e86c0e CW |
8167 | goto fail_unpin; |
8168 | } | |
8169 | ||
f343c5f6 | 8170 | addr = i915_gem_obj_ggtt_offset(obj); |
71acb5eb | 8171 | } else { |
6eeefaf3 | 8172 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
00731155 | 8173 | ret = i915_gem_object_attach_phys(obj, align); |
71acb5eb | 8174 | if (ret) { |
3b25b31f | 8175 | DRM_DEBUG_KMS("failed to attach phys object\n"); |
7f9872e0 | 8176 | goto fail_locked; |
71acb5eb | 8177 | } |
00731155 | 8178 | addr = obj->phys_handle->busaddr; |
3f8bc370 KH |
8179 | } |
8180 | ||
a6c45cf0 | 8181 | if (IS_GEN2(dev)) |
14b60391 JB |
8182 | I915_WRITE(CURSIZE, (height << 12) | width); |
8183 | ||
3f8bc370 | 8184 | finish: |
3f8bc370 | 8185 | if (intel_crtc->cursor_bo) { |
00731155 | 8186 | if (!INTEL_INFO(dev)->cursor_needs_physical) |
cc98b413 | 8187 | i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo); |
3f8bc370 | 8188 | } |
80824003 | 8189 | |
7f9872e0 | 8190 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 | 8191 | |
64f962e3 CW |
8192 | old_width = intel_crtc->cursor_width; |
8193 | ||
3f8bc370 | 8194 | intel_crtc->cursor_addr = addr; |
05394f39 | 8195 | intel_crtc->cursor_bo = obj; |
cda4b7d3 CW |
8196 | intel_crtc->cursor_width = width; |
8197 | intel_crtc->cursor_height = height; | |
8198 | ||
64f962e3 CW |
8199 | if (intel_crtc->active) { |
8200 | if (old_width != width) | |
8201 | intel_update_watermarks(crtc); | |
f2f5f771 | 8202 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); |
64f962e3 | 8203 | } |
3f8bc370 | 8204 | |
79e53945 | 8205 | return 0; |
e7b526bb | 8206 | fail_unpin: |
cc98b413 | 8207 | i915_gem_object_unpin_from_display_plane(obj); |
7f9872e0 | 8208 | fail_locked: |
34b8686e | 8209 | mutex_unlock(&dev->struct_mutex); |
bc9025bd | 8210 | fail: |
05394f39 | 8211 | drm_gem_object_unreference_unlocked(&obj->base); |
34b8686e | 8212 | return ret; |
79e53945 JB |
8213 | } |
8214 | ||
79e53945 | 8215 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 8216 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 8217 | { |
7203425a | 8218 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 8219 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 8220 | |
7203425a | 8221 | for (i = start; i < end; i++) { |
79e53945 JB |
8222 | intel_crtc->lut_r[i] = red[i] >> 8; |
8223 | intel_crtc->lut_g[i] = green[i] >> 8; | |
8224 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
8225 | } | |
8226 | ||
8227 | intel_crtc_load_lut(crtc); | |
8228 | } | |
8229 | ||
79e53945 JB |
8230 | /* VESA 640x480x72Hz mode to set on the pipe */ |
8231 | static struct drm_display_mode load_detect_mode = { | |
8232 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
8233 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
8234 | }; | |
8235 | ||
a8bb6818 DV |
8236 | struct drm_framebuffer * |
8237 | __intel_framebuffer_create(struct drm_device *dev, | |
8238 | struct drm_mode_fb_cmd2 *mode_cmd, | |
8239 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
8240 | { |
8241 | struct intel_framebuffer *intel_fb; | |
8242 | int ret; | |
8243 | ||
8244 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
8245 | if (!intel_fb) { | |
8246 | drm_gem_object_unreference_unlocked(&obj->base); | |
8247 | return ERR_PTR(-ENOMEM); | |
8248 | } | |
8249 | ||
8250 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
8251 | if (ret) |
8252 | goto err; | |
d2dff872 CW |
8253 | |
8254 | return &intel_fb->base; | |
dd4916c5 DV |
8255 | err: |
8256 | drm_gem_object_unreference_unlocked(&obj->base); | |
8257 | kfree(intel_fb); | |
8258 | ||
8259 | return ERR_PTR(ret); | |
d2dff872 CW |
8260 | } |
8261 | ||
b5ea642a | 8262 | static struct drm_framebuffer * |
a8bb6818 DV |
8263 | intel_framebuffer_create(struct drm_device *dev, |
8264 | struct drm_mode_fb_cmd2 *mode_cmd, | |
8265 | struct drm_i915_gem_object *obj) | |
8266 | { | |
8267 | struct drm_framebuffer *fb; | |
8268 | int ret; | |
8269 | ||
8270 | ret = i915_mutex_lock_interruptible(dev); | |
8271 | if (ret) | |
8272 | return ERR_PTR(ret); | |
8273 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
8274 | mutex_unlock(&dev->struct_mutex); | |
8275 | ||
8276 | return fb; | |
8277 | } | |
8278 | ||
d2dff872 CW |
8279 | static u32 |
8280 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
8281 | { | |
8282 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
8283 | return ALIGN(pitch, 64); | |
8284 | } | |
8285 | ||
8286 | static u32 | |
8287 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
8288 | { | |
8289 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
8290 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); | |
8291 | } | |
8292 | ||
8293 | static struct drm_framebuffer * | |
8294 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
8295 | struct drm_display_mode *mode, | |
8296 | int depth, int bpp) | |
8297 | { | |
8298 | struct drm_i915_gem_object *obj; | |
0fed39bd | 8299 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
8300 | |
8301 | obj = i915_gem_alloc_object(dev, | |
8302 | intel_framebuffer_size_for_mode(mode, bpp)); | |
8303 | if (obj == NULL) | |
8304 | return ERR_PTR(-ENOMEM); | |
8305 | ||
8306 | mode_cmd.width = mode->hdisplay; | |
8307 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
8308 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
8309 | bpp); | |
5ca0c34a | 8310 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
8311 | |
8312 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
8313 | } | |
8314 | ||
8315 | static struct drm_framebuffer * | |
8316 | mode_fits_in_fbdev(struct drm_device *dev, | |
8317 | struct drm_display_mode *mode) | |
8318 | { | |
4520f53a | 8319 | #ifdef CONFIG_DRM_I915_FBDEV |
d2dff872 CW |
8320 | struct drm_i915_private *dev_priv = dev->dev_private; |
8321 | struct drm_i915_gem_object *obj; | |
8322 | struct drm_framebuffer *fb; | |
8323 | ||
4c0e5528 | 8324 | if (!dev_priv->fbdev) |
d2dff872 CW |
8325 | return NULL; |
8326 | ||
4c0e5528 | 8327 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
8328 | return NULL; |
8329 | ||
4c0e5528 DV |
8330 | obj = dev_priv->fbdev->fb->obj; |
8331 | BUG_ON(!obj); | |
8332 | ||
8bcd4553 | 8333 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
8334 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
8335 | fb->bits_per_pixel)) | |
d2dff872 CW |
8336 | return NULL; |
8337 | ||
01f2c773 | 8338 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
8339 | return NULL; |
8340 | ||
8341 | return fb; | |
4520f53a DV |
8342 | #else |
8343 | return NULL; | |
8344 | #endif | |
d2dff872 CW |
8345 | } |
8346 | ||
d2434ab7 | 8347 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 8348 | struct drm_display_mode *mode, |
51fd371b RC |
8349 | struct intel_load_detect_pipe *old, |
8350 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
8351 | { |
8352 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
8353 | struct intel_encoder *intel_encoder = |
8354 | intel_attached_encoder(connector); | |
79e53945 | 8355 | struct drm_crtc *possible_crtc; |
4ef69c7a | 8356 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
8357 | struct drm_crtc *crtc = NULL; |
8358 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 8359 | struct drm_framebuffer *fb; |
51fd371b RC |
8360 | struct drm_mode_config *config = &dev->mode_config; |
8361 | int ret, i = -1; | |
79e53945 | 8362 | |
d2dff872 | 8363 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 8364 | connector->base.id, connector->name, |
8e329a03 | 8365 | encoder->base.id, encoder->name); |
d2dff872 | 8366 | |
51fd371b RC |
8367 | drm_modeset_acquire_init(ctx, 0); |
8368 | ||
8369 | retry: | |
8370 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
8371 | if (ret) | |
8372 | goto fail_unlock; | |
6e9f798d | 8373 | |
79e53945 JB |
8374 | /* |
8375 | * Algorithm gets a little messy: | |
7a5e4805 | 8376 | * |
79e53945 JB |
8377 | * - if the connector already has an assigned crtc, use it (but make |
8378 | * sure it's on first) | |
7a5e4805 | 8379 | * |
79e53945 JB |
8380 | * - try to find the first unused crtc that can drive this connector, |
8381 | * and use that if we find one | |
79e53945 JB |
8382 | */ |
8383 | ||
8384 | /* See if we already have a CRTC for this connector */ | |
8385 | if (encoder->crtc) { | |
8386 | crtc = encoder->crtc; | |
8261b191 | 8387 | |
51fd371b RC |
8388 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
8389 | if (ret) | |
8390 | goto fail_unlock; | |
7b24056b | 8391 | |
24218aac | 8392 | old->dpms_mode = connector->dpms; |
8261b191 CW |
8393 | old->load_detect_temp = false; |
8394 | ||
8395 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
8396 | if (connector->dpms != DRM_MODE_DPMS_ON) |
8397 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 8398 | |
7173188d | 8399 | return true; |
79e53945 JB |
8400 | } |
8401 | ||
8402 | /* Find an unused one (if possible) */ | |
70e1e0ec | 8403 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
8404 | i++; |
8405 | if (!(encoder->possible_crtcs & (1 << i))) | |
8406 | continue; | |
8407 | if (!possible_crtc->enabled) { | |
8408 | crtc = possible_crtc; | |
8409 | break; | |
8410 | } | |
79e53945 JB |
8411 | } |
8412 | ||
8413 | /* | |
8414 | * If we didn't find an unused CRTC, don't use any. | |
8415 | */ | |
8416 | if (!crtc) { | |
7173188d | 8417 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
51fd371b | 8418 | goto fail_unlock; |
79e53945 JB |
8419 | } |
8420 | ||
51fd371b RC |
8421 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
8422 | if (ret) | |
8423 | goto fail_unlock; | |
fc303101 DV |
8424 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
8425 | to_intel_connector(connector)->new_encoder = intel_encoder; | |
79e53945 JB |
8426 | |
8427 | intel_crtc = to_intel_crtc(crtc); | |
412b61d8 VS |
8428 | intel_crtc->new_enabled = true; |
8429 | intel_crtc->new_config = &intel_crtc->config; | |
24218aac | 8430 | old->dpms_mode = connector->dpms; |
8261b191 | 8431 | old->load_detect_temp = true; |
d2dff872 | 8432 | old->release_fb = NULL; |
79e53945 | 8433 | |
6492711d CW |
8434 | if (!mode) |
8435 | mode = &load_detect_mode; | |
79e53945 | 8436 | |
d2dff872 CW |
8437 | /* We need a framebuffer large enough to accommodate all accesses |
8438 | * that the plane may generate whilst we perform load detection. | |
8439 | * We can not rely on the fbcon either being present (we get called | |
8440 | * during its initialisation to detect all boot displays, or it may | |
8441 | * not even exist) or that it is large enough to satisfy the | |
8442 | * requested mode. | |
8443 | */ | |
94352cf9 DV |
8444 | fb = mode_fits_in_fbdev(dev, mode); |
8445 | if (fb == NULL) { | |
d2dff872 | 8446 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
8447 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
8448 | old->release_fb = fb; | |
d2dff872 CW |
8449 | } else |
8450 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 8451 | if (IS_ERR(fb)) { |
d2dff872 | 8452 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 8453 | goto fail; |
79e53945 | 8454 | } |
79e53945 | 8455 | |
c0c36b94 | 8456 | if (intel_set_mode(crtc, mode, 0, 0, fb)) { |
6492711d | 8457 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
8458 | if (old->release_fb) |
8459 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 8460 | goto fail; |
79e53945 | 8461 | } |
7173188d | 8462 | |
79e53945 | 8463 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 8464 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 8465 | return true; |
412b61d8 VS |
8466 | |
8467 | fail: | |
8468 | intel_crtc->new_enabled = crtc->enabled; | |
8469 | if (intel_crtc->new_enabled) | |
8470 | intel_crtc->new_config = &intel_crtc->config; | |
8471 | else | |
8472 | intel_crtc->new_config = NULL; | |
51fd371b RC |
8473 | fail_unlock: |
8474 | if (ret == -EDEADLK) { | |
8475 | drm_modeset_backoff(ctx); | |
8476 | goto retry; | |
8477 | } | |
8478 | ||
8479 | drm_modeset_drop_locks(ctx); | |
8480 | drm_modeset_acquire_fini(ctx); | |
6e9f798d | 8481 | |
412b61d8 | 8482 | return false; |
79e53945 JB |
8483 | } |
8484 | ||
d2434ab7 | 8485 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
51fd371b RC |
8486 | struct intel_load_detect_pipe *old, |
8487 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 8488 | { |
d2434ab7 DV |
8489 | struct intel_encoder *intel_encoder = |
8490 | intel_attached_encoder(connector); | |
4ef69c7a | 8491 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 8492 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 8493 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 8494 | |
d2dff872 | 8495 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 8496 | connector->base.id, connector->name, |
8e329a03 | 8497 | encoder->base.id, encoder->name); |
d2dff872 | 8498 | |
8261b191 | 8499 | if (old->load_detect_temp) { |
fc303101 DV |
8500 | to_intel_connector(connector)->new_encoder = NULL; |
8501 | intel_encoder->new_crtc = NULL; | |
412b61d8 VS |
8502 | intel_crtc->new_enabled = false; |
8503 | intel_crtc->new_config = NULL; | |
fc303101 | 8504 | intel_set_mode(crtc, NULL, 0, 0, NULL); |
d2dff872 | 8505 | |
36206361 DV |
8506 | if (old->release_fb) { |
8507 | drm_framebuffer_unregister_private(old->release_fb); | |
8508 | drm_framebuffer_unreference(old->release_fb); | |
8509 | } | |
d2dff872 | 8510 | |
51fd371b | 8511 | goto unlock; |
0622a53c | 8512 | return; |
79e53945 JB |
8513 | } |
8514 | ||
c751ce4f | 8515 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
8516 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
8517 | connector->funcs->dpms(connector, old->dpms_mode); | |
7b24056b | 8518 | |
51fd371b RC |
8519 | unlock: |
8520 | drm_modeset_drop_locks(ctx); | |
8521 | drm_modeset_acquire_fini(ctx); | |
79e53945 JB |
8522 | } |
8523 | ||
da4a1efa VS |
8524 | static int i9xx_pll_refclk(struct drm_device *dev, |
8525 | const struct intel_crtc_config *pipe_config) | |
8526 | { | |
8527 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8528 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
8529 | ||
8530 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 8531 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
8532 | else if (HAS_PCH_SPLIT(dev)) |
8533 | return 120000; | |
8534 | else if (!IS_GEN2(dev)) | |
8535 | return 96000; | |
8536 | else | |
8537 | return 48000; | |
8538 | } | |
8539 | ||
79e53945 | 8540 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc JB |
8541 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
8542 | struct intel_crtc_config *pipe_config) | |
79e53945 | 8543 | { |
f1f644dc | 8544 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 8545 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 8546 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 8547 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
8548 | u32 fp; |
8549 | intel_clock_t clock; | |
da4a1efa | 8550 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
8551 | |
8552 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 8553 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 8554 | else |
293623f7 | 8555 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
8556 | |
8557 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
8558 | if (IS_PINEVIEW(dev)) { |
8559 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
8560 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
8561 | } else { |
8562 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
8563 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
8564 | } | |
8565 | ||
a6c45cf0 | 8566 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
8567 | if (IS_PINEVIEW(dev)) |
8568 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
8569 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
8570 | else |
8571 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
8572 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
8573 | ||
8574 | switch (dpll & DPLL_MODE_MASK) { | |
8575 | case DPLLB_MODE_DAC_SERIAL: | |
8576 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
8577 | 5 : 10; | |
8578 | break; | |
8579 | case DPLLB_MODE_LVDS: | |
8580 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
8581 | 7 : 14; | |
8582 | break; | |
8583 | default: | |
28c97730 | 8584 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 8585 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 8586 | return; |
79e53945 JB |
8587 | } |
8588 | ||
ac58c3f0 | 8589 | if (IS_PINEVIEW(dev)) |
da4a1efa | 8590 | pineview_clock(refclk, &clock); |
ac58c3f0 | 8591 | else |
da4a1efa | 8592 | i9xx_clock(refclk, &clock); |
79e53945 | 8593 | } else { |
0fb58223 | 8594 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 8595 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
8596 | |
8597 | if (is_lvds) { | |
8598 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
8599 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
8600 | |
8601 | if (lvds & LVDS_CLKB_POWER_UP) | |
8602 | clock.p2 = 7; | |
8603 | else | |
8604 | clock.p2 = 14; | |
79e53945 JB |
8605 | } else { |
8606 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
8607 | clock.p1 = 2; | |
8608 | else { | |
8609 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
8610 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
8611 | } | |
8612 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
8613 | clock.p2 = 4; | |
8614 | else | |
8615 | clock.p2 = 2; | |
79e53945 | 8616 | } |
da4a1efa VS |
8617 | |
8618 | i9xx_clock(refclk, &clock); | |
79e53945 JB |
8619 | } |
8620 | ||
18442d08 VS |
8621 | /* |
8622 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 8623 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
8624 | * encoder's get_config() function. |
8625 | */ | |
8626 | pipe_config->port_clock = clock.dot; | |
f1f644dc JB |
8627 | } |
8628 | ||
6878da05 VS |
8629 | int intel_dotclock_calculate(int link_freq, |
8630 | const struct intel_link_m_n *m_n) | |
f1f644dc | 8631 | { |
f1f644dc JB |
8632 | /* |
8633 | * The calculation for the data clock is: | |
1041a02f | 8634 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 8635 | * But we want to avoid losing precison if possible, so: |
1041a02f | 8636 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
8637 | * |
8638 | * and the link clock is simpler: | |
1041a02f | 8639 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
8640 | */ |
8641 | ||
6878da05 VS |
8642 | if (!m_n->link_n) |
8643 | return 0; | |
f1f644dc | 8644 | |
6878da05 VS |
8645 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
8646 | } | |
f1f644dc | 8647 | |
18442d08 VS |
8648 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
8649 | struct intel_crtc_config *pipe_config) | |
6878da05 VS |
8650 | { |
8651 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 8652 | |
18442d08 VS |
8653 | /* read out port_clock from the DPLL */ |
8654 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 8655 | |
f1f644dc | 8656 | /* |
18442d08 | 8657 | * This value does not include pixel_multiplier. |
241bfc38 | 8658 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
8659 | * agree once we know their relationship in the encoder's |
8660 | * get_config() function. | |
79e53945 | 8661 | */ |
241bfc38 | 8662 | pipe_config->adjusted_mode.crtc_clock = |
18442d08 VS |
8663 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
8664 | &pipe_config->fdi_m_n); | |
79e53945 JB |
8665 | } |
8666 | ||
8667 | /** Returns the currently programmed mode of the given pipe. */ | |
8668 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
8669 | struct drm_crtc *crtc) | |
8670 | { | |
548f245b | 8671 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 8672 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3b117c8f | 8673 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
79e53945 | 8674 | struct drm_display_mode *mode; |
f1f644dc | 8675 | struct intel_crtc_config pipe_config; |
fe2b8f9d PZ |
8676 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
8677 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
8678 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
8679 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 8680 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
8681 | |
8682 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
8683 | if (!mode) | |
8684 | return NULL; | |
8685 | ||
f1f644dc JB |
8686 | /* |
8687 | * Construct a pipe_config sufficient for getting the clock info | |
8688 | * back out of crtc_clock_get. | |
8689 | * | |
8690 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
8691 | * to use a real value here instead. | |
8692 | */ | |
293623f7 | 8693 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 8694 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
8695 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
8696 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
8697 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
8698 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
8699 | ||
773ae034 | 8700 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
8701 | mode->hdisplay = (htot & 0xffff) + 1; |
8702 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
8703 | mode->hsync_start = (hsync & 0xffff) + 1; | |
8704 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
8705 | mode->vdisplay = (vtot & 0xffff) + 1; | |
8706 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
8707 | mode->vsync_start = (vsync & 0xffff) + 1; | |
8708 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
8709 | ||
8710 | drm_mode_set_name(mode); | |
79e53945 JB |
8711 | |
8712 | return mode; | |
8713 | } | |
8714 | ||
3dec0095 | 8715 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
652c393a JB |
8716 | { |
8717 | struct drm_device *dev = crtc->dev; | |
fbee40df | 8718 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a JB |
8719 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8720 | int pipe = intel_crtc->pipe; | |
dbdc6479 JB |
8721 | int dpll_reg = DPLL(pipe); |
8722 | int dpll; | |
652c393a | 8723 | |
bad720ff | 8724 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
8725 | return; |
8726 | ||
8727 | if (!dev_priv->lvds_downclock_avail) | |
8728 | return; | |
8729 | ||
dbdc6479 | 8730 | dpll = I915_READ(dpll_reg); |
652c393a | 8731 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
44d98a61 | 8732 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
652c393a | 8733 | |
8ac5a6d5 | 8734 | assert_panel_unlocked(dev_priv, pipe); |
652c393a JB |
8735 | |
8736 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; | |
8737 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 8738 | intel_wait_for_vblank(dev, pipe); |
dbdc6479 | 8739 | |
652c393a JB |
8740 | dpll = I915_READ(dpll_reg); |
8741 | if (dpll & DISPLAY_RATE_SELECT_FPA1) | |
44d98a61 | 8742 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
652c393a | 8743 | } |
652c393a JB |
8744 | } |
8745 | ||
8746 | static void intel_decrease_pllclock(struct drm_crtc *crtc) | |
8747 | { | |
8748 | struct drm_device *dev = crtc->dev; | |
fbee40df | 8749 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 8750 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
652c393a | 8751 | |
bad720ff | 8752 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
8753 | return; |
8754 | ||
8755 | if (!dev_priv->lvds_downclock_avail) | |
8756 | return; | |
8757 | ||
8758 | /* | |
8759 | * Since this is called by a timer, we should never get here in | |
8760 | * the manual case. | |
8761 | */ | |
8762 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
8763 | int pipe = intel_crtc->pipe; |
8764 | int dpll_reg = DPLL(pipe); | |
8765 | int dpll; | |
f6e5b160 | 8766 | |
44d98a61 | 8767 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 8768 | |
8ac5a6d5 | 8769 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 8770 | |
dc257cf1 | 8771 | dpll = I915_READ(dpll_reg); |
652c393a JB |
8772 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
8773 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 8774 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
8775 | dpll = I915_READ(dpll_reg); |
8776 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 8777 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
8778 | } |
8779 | ||
8780 | } | |
8781 | ||
f047e395 CW |
8782 | void intel_mark_busy(struct drm_device *dev) |
8783 | { | |
c67a470b PZ |
8784 | struct drm_i915_private *dev_priv = dev->dev_private; |
8785 | ||
f62a0076 CW |
8786 | if (dev_priv->mm.busy) |
8787 | return; | |
8788 | ||
43694d69 | 8789 | intel_runtime_pm_get(dev_priv); |
c67a470b | 8790 | i915_update_gfx_val(dev_priv); |
f62a0076 | 8791 | dev_priv->mm.busy = true; |
f047e395 CW |
8792 | } |
8793 | ||
8794 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 8795 | { |
c67a470b | 8796 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 8797 | struct drm_crtc *crtc; |
652c393a | 8798 | |
f62a0076 CW |
8799 | if (!dev_priv->mm.busy) |
8800 | return; | |
8801 | ||
8802 | dev_priv->mm.busy = false; | |
8803 | ||
d330a953 | 8804 | if (!i915.powersave) |
bb4cdd53 | 8805 | goto out; |
652c393a | 8806 | |
70e1e0ec | 8807 | for_each_crtc(dev, crtc) { |
f4510a27 | 8808 | if (!crtc->primary->fb) |
652c393a JB |
8809 | continue; |
8810 | ||
725a5b54 | 8811 | intel_decrease_pllclock(crtc); |
652c393a | 8812 | } |
b29c19b6 | 8813 | |
3d13ef2e | 8814 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 8815 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 PZ |
8816 | |
8817 | out: | |
43694d69 | 8818 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
8819 | } |
8820 | ||
c65355bb | 8821 | void intel_mark_fb_busy(struct drm_i915_gem_object *obj, |
a4872ba6 | 8822 | struct intel_engine_cs *ring) |
652c393a | 8823 | { |
f047e395 CW |
8824 | struct drm_device *dev = obj->base.dev; |
8825 | struct drm_crtc *crtc; | |
652c393a | 8826 | |
d330a953 | 8827 | if (!i915.powersave) |
acb87dfb CW |
8828 | return; |
8829 | ||
70e1e0ec | 8830 | for_each_crtc(dev, crtc) { |
f4510a27 | 8831 | if (!crtc->primary->fb) |
652c393a JB |
8832 | continue; |
8833 | ||
f4510a27 | 8834 | if (to_intel_framebuffer(crtc->primary->fb)->obj != obj) |
c65355bb CW |
8835 | continue; |
8836 | ||
8837 | intel_increase_pllclock(crtc); | |
8838 | if (ring && intel_fbc_enabled(dev)) | |
8839 | ring->fbc_dirty = true; | |
652c393a JB |
8840 | } |
8841 | } | |
8842 | ||
79e53945 JB |
8843 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
8844 | { | |
8845 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
8846 | struct drm_device *dev = crtc->dev; |
8847 | struct intel_unpin_work *work; | |
8848 | unsigned long flags; | |
8849 | ||
8850 | spin_lock_irqsave(&dev->event_lock, flags); | |
8851 | work = intel_crtc->unpin_work; | |
8852 | intel_crtc->unpin_work = NULL; | |
8853 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
8854 | ||
8855 | if (work) { | |
8856 | cancel_work_sync(&work->work); | |
8857 | kfree(work); | |
8858 | } | |
79e53945 JB |
8859 | |
8860 | drm_crtc_cleanup(crtc); | |
67e77c5a | 8861 | |
79e53945 JB |
8862 | kfree(intel_crtc); |
8863 | } | |
8864 | ||
6b95a207 KH |
8865 | static void intel_unpin_work_fn(struct work_struct *__work) |
8866 | { | |
8867 | struct intel_unpin_work *work = | |
8868 | container_of(__work, struct intel_unpin_work, work); | |
b4a98e57 | 8869 | struct drm_device *dev = work->crtc->dev; |
6b95a207 | 8870 | |
b4a98e57 | 8871 | mutex_lock(&dev->struct_mutex); |
1690e1eb | 8872 | intel_unpin_fb_obj(work->old_fb_obj); |
05394f39 CW |
8873 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
8874 | drm_gem_object_unreference(&work->old_fb_obj->base); | |
d9e86c0e | 8875 | |
b4a98e57 CW |
8876 | intel_update_fbc(dev); |
8877 | mutex_unlock(&dev->struct_mutex); | |
8878 | ||
8879 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); | |
8880 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); | |
8881 | ||
6b95a207 KH |
8882 | kfree(work); |
8883 | } | |
8884 | ||
1afe3e9d | 8885 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 8886 | struct drm_crtc *crtc) |
6b95a207 | 8887 | { |
fbee40df | 8888 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
8889 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8890 | struct intel_unpin_work *work; | |
6b95a207 KH |
8891 | unsigned long flags; |
8892 | ||
8893 | /* Ignore early vblank irqs */ | |
8894 | if (intel_crtc == NULL) | |
8895 | return; | |
8896 | ||
8897 | spin_lock_irqsave(&dev->event_lock, flags); | |
8898 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
8899 | |
8900 | /* Ensure we don't miss a work->pending update ... */ | |
8901 | smp_rmb(); | |
8902 | ||
8903 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
8904 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8905 | return; | |
8906 | } | |
8907 | ||
e7d841ca CW |
8908 | /* and that the unpin work is consistent wrt ->pending. */ |
8909 | smp_rmb(); | |
8910 | ||
6b95a207 | 8911 | intel_crtc->unpin_work = NULL; |
6b95a207 | 8912 | |
45a066eb RC |
8913 | if (work->event) |
8914 | drm_send_vblank_event(dev, intel_crtc->pipe, work->event); | |
6b95a207 | 8915 | |
87b6b101 | 8916 | drm_crtc_vblank_put(crtc); |
0af7e4df | 8917 | |
6b95a207 KH |
8918 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8919 | ||
2c10d571 | 8920 | wake_up_all(&dev_priv->pending_flip_queue); |
b4a98e57 CW |
8921 | |
8922 | queue_work(dev_priv->wq, &work->work); | |
e5510fac JB |
8923 | |
8924 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); | |
6b95a207 KH |
8925 | } |
8926 | ||
1afe3e9d JB |
8927 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
8928 | { | |
fbee40df | 8929 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
8930 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
8931 | ||
49b14a5c | 8932 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
8933 | } |
8934 | ||
8935 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
8936 | { | |
fbee40df | 8937 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
8938 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
8939 | ||
49b14a5c | 8940 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
8941 | } |
8942 | ||
75f7f3ec VS |
8943 | /* Is 'a' after or equal to 'b'? */ |
8944 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
8945 | { | |
8946 | return !((a - b) & 0x80000000); | |
8947 | } | |
8948 | ||
8949 | static bool page_flip_finished(struct intel_crtc *crtc) | |
8950 | { | |
8951 | struct drm_device *dev = crtc->base.dev; | |
8952 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8953 | ||
8954 | /* | |
8955 | * The relevant registers doen't exist on pre-ctg. | |
8956 | * As the flip done interrupt doesn't trigger for mmio | |
8957 | * flips on gmch platforms, a flip count check isn't | |
8958 | * really needed there. But since ctg has the registers, | |
8959 | * include it in the check anyway. | |
8960 | */ | |
8961 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
8962 | return true; | |
8963 | ||
8964 | /* | |
8965 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
8966 | * used the same base address. In that case the mmio flip might | |
8967 | * have completed, but the CS hasn't even executed the flip yet. | |
8968 | * | |
8969 | * A flip count check isn't enough as the CS might have updated | |
8970 | * the base address just after start of vblank, but before we | |
8971 | * managed to process the interrupt. This means we'd complete the | |
8972 | * CS flip too soon. | |
8973 | * | |
8974 | * Combining both checks should get us a good enough result. It may | |
8975 | * still happen that the CS flip has been executed, but has not | |
8976 | * yet actually completed. But in case the base address is the same | |
8977 | * anyway, we don't really care. | |
8978 | */ | |
8979 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
8980 | crtc->unpin_work->gtt_offset && | |
8981 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)), | |
8982 | crtc->unpin_work->flip_count); | |
8983 | } | |
8984 | ||
6b95a207 KH |
8985 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
8986 | { | |
fbee40df | 8987 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
8988 | struct intel_crtc *intel_crtc = |
8989 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
8990 | unsigned long flags; | |
8991 | ||
e7d841ca CW |
8992 | /* NB: An MMIO update of the plane base pointer will also |
8993 | * generate a page-flip completion irq, i.e. every modeset | |
8994 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
8995 | */ | |
6b95a207 | 8996 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 8997 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 8998 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
8999 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9000 | } | |
9001 | ||
eba905b2 | 9002 | static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
e7d841ca CW |
9003 | { |
9004 | /* Ensure that the work item is consistent when activating it ... */ | |
9005 | smp_wmb(); | |
9006 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
9007 | /* and that it is marked active as soon as the irq could fire. */ | |
9008 | smp_wmb(); | |
9009 | } | |
9010 | ||
8c9f3aaf JB |
9011 | static int intel_gen2_queue_flip(struct drm_device *dev, |
9012 | struct drm_crtc *crtc, | |
9013 | struct drm_framebuffer *fb, | |
ed8d1975 | 9014 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9015 | struct intel_engine_cs *ring, |
ed8d1975 | 9016 | uint32_t flags) |
8c9f3aaf | 9017 | { |
8c9f3aaf | 9018 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
9019 | u32 flip_mask; |
9020 | int ret; | |
9021 | ||
6d90c952 | 9022 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 9023 | if (ret) |
4fa62c89 | 9024 | return ret; |
8c9f3aaf JB |
9025 | |
9026 | /* Can't queue multiple flips, so wait for the previous | |
9027 | * one to finish before executing the next. | |
9028 | */ | |
9029 | if (intel_crtc->plane) | |
9030 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
9031 | else | |
9032 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
9033 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
9034 | intel_ring_emit(ring, MI_NOOP); | |
9035 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
9036 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9037 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9038 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 | 9039 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
9040 | |
9041 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9042 | __intel_ring_advance(ring); |
83d4092b | 9043 | return 0; |
8c9f3aaf JB |
9044 | } |
9045 | ||
9046 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
9047 | struct drm_crtc *crtc, | |
9048 | struct drm_framebuffer *fb, | |
ed8d1975 | 9049 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9050 | struct intel_engine_cs *ring, |
ed8d1975 | 9051 | uint32_t flags) |
8c9f3aaf | 9052 | { |
8c9f3aaf | 9053 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
9054 | u32 flip_mask; |
9055 | int ret; | |
9056 | ||
6d90c952 | 9057 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 9058 | if (ret) |
4fa62c89 | 9059 | return ret; |
8c9f3aaf JB |
9060 | |
9061 | if (intel_crtc->plane) | |
9062 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
9063 | else | |
9064 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
9065 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
9066 | intel_ring_emit(ring, MI_NOOP); | |
9067 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
9068 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9069 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9070 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 DV |
9071 | intel_ring_emit(ring, MI_NOOP); |
9072 | ||
e7d841ca | 9073 | intel_mark_page_flip_active(intel_crtc); |
09246732 | 9074 | __intel_ring_advance(ring); |
83d4092b | 9075 | return 0; |
8c9f3aaf JB |
9076 | } |
9077 | ||
9078 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
9079 | struct drm_crtc *crtc, | |
9080 | struct drm_framebuffer *fb, | |
ed8d1975 | 9081 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9082 | struct intel_engine_cs *ring, |
ed8d1975 | 9083 | uint32_t flags) |
8c9f3aaf JB |
9084 | { |
9085 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9086 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9087 | uint32_t pf, pipesrc; | |
9088 | int ret; | |
9089 | ||
6d90c952 | 9090 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 9091 | if (ret) |
4fa62c89 | 9092 | return ret; |
8c9f3aaf JB |
9093 | |
9094 | /* i965+ uses the linear or tiled offsets from the | |
9095 | * Display Registers (which do not change across a page-flip) | |
9096 | * so we need only reprogram the base address. | |
9097 | */ | |
6d90c952 DV |
9098 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
9099 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9100 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9101 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
c2c75131 | 9102 | obj->tiling_mode); |
8c9f3aaf JB |
9103 | |
9104 | /* XXX Enabling the panel-fitter across page-flip is so far | |
9105 | * untested on non-native modes, so ignore it for now. | |
9106 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
9107 | */ | |
9108 | pf = 0; | |
9109 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 9110 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
9111 | |
9112 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9113 | __intel_ring_advance(ring); |
83d4092b | 9114 | return 0; |
8c9f3aaf JB |
9115 | } |
9116 | ||
9117 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
9118 | struct drm_crtc *crtc, | |
9119 | struct drm_framebuffer *fb, | |
ed8d1975 | 9120 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9121 | struct intel_engine_cs *ring, |
ed8d1975 | 9122 | uint32_t flags) |
8c9f3aaf JB |
9123 | { |
9124 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9125 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9126 | uint32_t pf, pipesrc; | |
9127 | int ret; | |
9128 | ||
6d90c952 | 9129 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 9130 | if (ret) |
4fa62c89 | 9131 | return ret; |
8c9f3aaf | 9132 | |
6d90c952 DV |
9133 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
9134 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9135 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
75f7f3ec | 9136 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8c9f3aaf | 9137 | |
dc257cf1 DV |
9138 | /* Contrary to the suggestions in the documentation, |
9139 | * "Enable Panel Fitter" does not seem to be required when page | |
9140 | * flipping with a non-native mode, and worse causes a normal | |
9141 | * modeset to fail. | |
9142 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
9143 | */ | |
9144 | pf = 0; | |
8c9f3aaf | 9145 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 9146 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
9147 | |
9148 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9149 | __intel_ring_advance(ring); |
83d4092b | 9150 | return 0; |
8c9f3aaf JB |
9151 | } |
9152 | ||
7c9017e5 JB |
9153 | static int intel_gen7_queue_flip(struct drm_device *dev, |
9154 | struct drm_crtc *crtc, | |
9155 | struct drm_framebuffer *fb, | |
ed8d1975 | 9156 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9157 | struct intel_engine_cs *ring, |
ed8d1975 | 9158 | uint32_t flags) |
7c9017e5 | 9159 | { |
7c9017e5 | 9160 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 9161 | uint32_t plane_bit = 0; |
ffe74d75 CW |
9162 | int len, ret; |
9163 | ||
eba905b2 | 9164 | switch (intel_crtc->plane) { |
cb05d8de DV |
9165 | case PLANE_A: |
9166 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
9167 | break; | |
9168 | case PLANE_B: | |
9169 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
9170 | break; | |
9171 | case PLANE_C: | |
9172 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
9173 | break; | |
9174 | default: | |
9175 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 9176 | return -ENODEV; |
cb05d8de DV |
9177 | } |
9178 | ||
ffe74d75 | 9179 | len = 4; |
f476828a | 9180 | if (ring->id == RCS) { |
ffe74d75 | 9181 | len += 6; |
f476828a DL |
9182 | /* |
9183 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
9184 | * 48bits addresses, and we need a NOOP for the batch size to | |
9185 | * stay even. | |
9186 | */ | |
9187 | if (IS_GEN8(dev)) | |
9188 | len += 2; | |
9189 | } | |
ffe74d75 | 9190 | |
f66fab8e VS |
9191 | /* |
9192 | * BSpec MI_DISPLAY_FLIP for IVB: | |
9193 | * "The full packet must be contained within the same cache line." | |
9194 | * | |
9195 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
9196 | * cacheline, if we ever start emitting more commands before | |
9197 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
9198 | * then do the cacheline alignment, and finally emit the | |
9199 | * MI_DISPLAY_FLIP. | |
9200 | */ | |
9201 | ret = intel_ring_cacheline_align(ring); | |
9202 | if (ret) | |
4fa62c89 | 9203 | return ret; |
f66fab8e | 9204 | |
ffe74d75 | 9205 | ret = intel_ring_begin(ring, len); |
7c9017e5 | 9206 | if (ret) |
4fa62c89 | 9207 | return ret; |
7c9017e5 | 9208 | |
ffe74d75 CW |
9209 | /* Unmask the flip-done completion message. Note that the bspec says that |
9210 | * we should do this for both the BCS and RCS, and that we must not unmask | |
9211 | * more than one flip event at any time (or ensure that one flip message | |
9212 | * can be sent by waiting for flip-done prior to queueing new flips). | |
9213 | * Experimentation says that BCS works despite DERRMR masking all | |
9214 | * flip-done completion events and that unmasking all planes at once | |
9215 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
9216 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
9217 | */ | |
9218 | if (ring->id == RCS) { | |
9219 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
9220 | intel_ring_emit(ring, DERRMR); | |
9221 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
9222 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
9223 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a DL |
9224 | if (IS_GEN8(dev)) |
9225 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) | | |
9226 | MI_SRM_LRM_GLOBAL_GTT); | |
9227 | else | |
9228 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | | |
9229 | MI_SRM_LRM_GLOBAL_GTT); | |
ffe74d75 CW |
9230 | intel_ring_emit(ring, DERRMR); |
9231 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
f476828a DL |
9232 | if (IS_GEN8(dev)) { |
9233 | intel_ring_emit(ring, 0); | |
9234 | intel_ring_emit(ring, MI_NOOP); | |
9235 | } | |
ffe74d75 CW |
9236 | } |
9237 | ||
cb05d8de | 9238 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 9239 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
75f7f3ec | 9240 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
7c9017e5 | 9241 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
9242 | |
9243 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9244 | __intel_ring_advance(ring); |
83d4092b | 9245 | return 0; |
7c9017e5 JB |
9246 | } |
9247 | ||
8c9f3aaf JB |
9248 | static int intel_default_queue_flip(struct drm_device *dev, |
9249 | struct drm_crtc *crtc, | |
9250 | struct drm_framebuffer *fb, | |
ed8d1975 | 9251 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9252 | struct intel_engine_cs *ring, |
ed8d1975 | 9253 | uint32_t flags) |
8c9f3aaf JB |
9254 | { |
9255 | return -ENODEV; | |
9256 | } | |
9257 | ||
6b95a207 KH |
9258 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
9259 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
9260 | struct drm_pending_vblank_event *event, |
9261 | uint32_t page_flip_flags) | |
6b95a207 KH |
9262 | { |
9263 | struct drm_device *dev = crtc->dev; | |
9264 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 9265 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
4a35f83b | 9266 | struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj; |
6b95a207 KH |
9267 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9268 | struct intel_unpin_work *work; | |
a4872ba6 | 9269 | struct intel_engine_cs *ring; |
8c9f3aaf | 9270 | unsigned long flags; |
52e68630 | 9271 | int ret; |
6b95a207 | 9272 | |
e6a595d2 | 9273 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 9274 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
9275 | return -EINVAL; |
9276 | ||
9277 | /* | |
9278 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
9279 | * Note that pitch changes could also affect these register. | |
9280 | */ | |
9281 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
9282 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
9283 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
9284 | return -EINVAL; |
9285 | ||
f900db47 CW |
9286 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
9287 | goto out_hang; | |
9288 | ||
b14c5679 | 9289 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
9290 | if (work == NULL) |
9291 | return -ENOMEM; | |
9292 | ||
6b95a207 | 9293 | work->event = event; |
b4a98e57 | 9294 | work->crtc = crtc; |
4a35f83b | 9295 | work->old_fb_obj = to_intel_framebuffer(old_fb)->obj; |
6b95a207 KH |
9296 | INIT_WORK(&work->work, intel_unpin_work_fn); |
9297 | ||
87b6b101 | 9298 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
9299 | if (ret) |
9300 | goto free_work; | |
9301 | ||
6b95a207 KH |
9302 | /* We borrow the event spin lock for protecting unpin_work */ |
9303 | spin_lock_irqsave(&dev->event_lock, flags); | |
9304 | if (intel_crtc->unpin_work) { | |
9305 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
9306 | kfree(work); | |
87b6b101 | 9307 | drm_crtc_vblank_put(crtc); |
468f0b44 CW |
9308 | |
9309 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
6b95a207 KH |
9310 | return -EBUSY; |
9311 | } | |
9312 | intel_crtc->unpin_work = work; | |
9313 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
9314 | ||
b4a98e57 CW |
9315 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
9316 | flush_workqueue(dev_priv->wq); | |
9317 | ||
79158103 CW |
9318 | ret = i915_mutex_lock_interruptible(dev); |
9319 | if (ret) | |
9320 | goto cleanup; | |
6b95a207 | 9321 | |
75dfca80 | 9322 | /* Reference the objects for the scheduled work. */ |
05394f39 CW |
9323 | drm_gem_object_reference(&work->old_fb_obj->base); |
9324 | drm_gem_object_reference(&obj->base); | |
6b95a207 | 9325 | |
f4510a27 | 9326 | crtc->primary->fb = fb; |
96b099fd | 9327 | |
e1f99ce6 | 9328 | work->pending_flip_obj = obj; |
e1f99ce6 | 9329 | |
4e5359cd SF |
9330 | work->enable_stall_check = true; |
9331 | ||
b4a98e57 | 9332 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 9333 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 9334 | |
75f7f3ec VS |
9335 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
9336 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(intel_crtc->pipe)) + 1; | |
9337 | ||
4fa62c89 VS |
9338 | if (IS_VALLEYVIEW(dev)) { |
9339 | ring = &dev_priv->ring[BCS]; | |
9340 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
9341 | ring = obj->ring; | |
9342 | if (ring == NULL || ring->id != RCS) | |
9343 | ring = &dev_priv->ring[BCS]; | |
9344 | } else { | |
9345 | ring = &dev_priv->ring[RCS]; | |
9346 | } | |
9347 | ||
9348 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); | |
8c9f3aaf JB |
9349 | if (ret) |
9350 | goto cleanup_pending; | |
6b95a207 | 9351 | |
4fa62c89 VS |
9352 | work->gtt_offset = |
9353 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset; | |
9354 | ||
9355 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, page_flip_flags); | |
9356 | if (ret) | |
9357 | goto cleanup_unpin; | |
9358 | ||
7782de3b | 9359 | intel_disable_fbc(dev); |
c65355bb | 9360 | intel_mark_fb_busy(obj, NULL); |
6b95a207 KH |
9361 | mutex_unlock(&dev->struct_mutex); |
9362 | ||
e5510fac JB |
9363 | trace_i915_flip_request(intel_crtc->plane, obj); |
9364 | ||
6b95a207 | 9365 | return 0; |
96b099fd | 9366 | |
4fa62c89 VS |
9367 | cleanup_unpin: |
9368 | intel_unpin_fb_obj(obj); | |
8c9f3aaf | 9369 | cleanup_pending: |
b4a98e57 | 9370 | atomic_dec(&intel_crtc->unpin_work_count); |
f4510a27 | 9371 | crtc->primary->fb = old_fb; |
05394f39 CW |
9372 | drm_gem_object_unreference(&work->old_fb_obj->base); |
9373 | drm_gem_object_unreference(&obj->base); | |
96b099fd CW |
9374 | mutex_unlock(&dev->struct_mutex); |
9375 | ||
79158103 | 9376 | cleanup: |
96b099fd CW |
9377 | spin_lock_irqsave(&dev->event_lock, flags); |
9378 | intel_crtc->unpin_work = NULL; | |
9379 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
9380 | ||
87b6b101 | 9381 | drm_crtc_vblank_put(crtc); |
7317c75e | 9382 | free_work: |
96b099fd CW |
9383 | kfree(work); |
9384 | ||
f900db47 CW |
9385 | if (ret == -EIO) { |
9386 | out_hang: | |
9387 | intel_crtc_wait_for_pending_flips(crtc); | |
9388 | ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb); | |
9389 | if (ret == 0 && event) | |
9390 | drm_send_vblank_event(dev, intel_crtc->pipe, event); | |
9391 | } | |
96b099fd | 9392 | return ret; |
6b95a207 KH |
9393 | } |
9394 | ||
f6e5b160 | 9395 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
9396 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
9397 | .load_lut = intel_crtc_load_lut, | |
f6e5b160 CW |
9398 | }; |
9399 | ||
9a935856 DV |
9400 | /** |
9401 | * intel_modeset_update_staged_output_state | |
9402 | * | |
9403 | * Updates the staged output configuration state, e.g. after we've read out the | |
9404 | * current hw state. | |
9405 | */ | |
9406 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) | |
f6e5b160 | 9407 | { |
7668851f | 9408 | struct intel_crtc *crtc; |
9a935856 DV |
9409 | struct intel_encoder *encoder; |
9410 | struct intel_connector *connector; | |
f6e5b160 | 9411 | |
9a935856 DV |
9412 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9413 | base.head) { | |
9414 | connector->new_encoder = | |
9415 | to_intel_encoder(connector->base.encoder); | |
9416 | } | |
f6e5b160 | 9417 | |
9a935856 DV |
9418 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9419 | base.head) { | |
9420 | encoder->new_crtc = | |
9421 | to_intel_crtc(encoder->base.crtc); | |
9422 | } | |
7668851f | 9423 | |
d3fcc808 | 9424 | for_each_intel_crtc(dev, crtc) { |
7668851f | 9425 | crtc->new_enabled = crtc->base.enabled; |
7bd0a8e7 VS |
9426 | |
9427 | if (crtc->new_enabled) | |
9428 | crtc->new_config = &crtc->config; | |
9429 | else | |
9430 | crtc->new_config = NULL; | |
7668851f | 9431 | } |
f6e5b160 CW |
9432 | } |
9433 | ||
9a935856 DV |
9434 | /** |
9435 | * intel_modeset_commit_output_state | |
9436 | * | |
9437 | * This function copies the stage display pipe configuration to the real one. | |
9438 | */ | |
9439 | static void intel_modeset_commit_output_state(struct drm_device *dev) | |
9440 | { | |
7668851f | 9441 | struct intel_crtc *crtc; |
9a935856 DV |
9442 | struct intel_encoder *encoder; |
9443 | struct intel_connector *connector; | |
f6e5b160 | 9444 | |
9a935856 DV |
9445 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9446 | base.head) { | |
9447 | connector->base.encoder = &connector->new_encoder->base; | |
9448 | } | |
f6e5b160 | 9449 | |
9a935856 DV |
9450 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9451 | base.head) { | |
9452 | encoder->base.crtc = &encoder->new_crtc->base; | |
9453 | } | |
7668851f | 9454 | |
d3fcc808 | 9455 | for_each_intel_crtc(dev, crtc) { |
7668851f VS |
9456 | crtc->base.enabled = crtc->new_enabled; |
9457 | } | |
9a935856 DV |
9458 | } |
9459 | ||
050f7aeb | 9460 | static void |
eba905b2 | 9461 | connected_sink_compute_bpp(struct intel_connector *connector, |
050f7aeb DV |
9462 | struct intel_crtc_config *pipe_config) |
9463 | { | |
9464 | int bpp = pipe_config->pipe_bpp; | |
9465 | ||
9466 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
9467 | connector->base.base.id, | |
c23cc417 | 9468 | connector->base.name); |
050f7aeb DV |
9469 | |
9470 | /* Don't use an invalid EDID bpc value */ | |
9471 | if (connector->base.display_info.bpc && | |
9472 | connector->base.display_info.bpc * 3 < bpp) { | |
9473 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
9474 | bpp, connector->base.display_info.bpc*3); | |
9475 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
9476 | } | |
9477 | ||
9478 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
9479 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
9480 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
9481 | bpp); | |
9482 | pipe_config->pipe_bpp = 24; | |
9483 | } | |
9484 | } | |
9485 | ||
4e53c2e0 | 9486 | static int |
050f7aeb DV |
9487 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
9488 | struct drm_framebuffer *fb, | |
9489 | struct intel_crtc_config *pipe_config) | |
4e53c2e0 | 9490 | { |
050f7aeb DV |
9491 | struct drm_device *dev = crtc->base.dev; |
9492 | struct intel_connector *connector; | |
4e53c2e0 DV |
9493 | int bpp; |
9494 | ||
d42264b1 DV |
9495 | switch (fb->pixel_format) { |
9496 | case DRM_FORMAT_C8: | |
4e53c2e0 DV |
9497 | bpp = 8*3; /* since we go through a colormap */ |
9498 | break; | |
d42264b1 DV |
9499 | case DRM_FORMAT_XRGB1555: |
9500 | case DRM_FORMAT_ARGB1555: | |
9501 | /* checked in intel_framebuffer_init already */ | |
9502 | if (WARN_ON(INTEL_INFO(dev)->gen > 3)) | |
9503 | return -EINVAL; | |
9504 | case DRM_FORMAT_RGB565: | |
4e53c2e0 DV |
9505 | bpp = 6*3; /* min is 18bpp */ |
9506 | break; | |
d42264b1 DV |
9507 | case DRM_FORMAT_XBGR8888: |
9508 | case DRM_FORMAT_ABGR8888: | |
9509 | /* checked in intel_framebuffer_init already */ | |
9510 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
9511 | return -EINVAL; | |
9512 | case DRM_FORMAT_XRGB8888: | |
9513 | case DRM_FORMAT_ARGB8888: | |
4e53c2e0 DV |
9514 | bpp = 8*3; |
9515 | break; | |
d42264b1 DV |
9516 | case DRM_FORMAT_XRGB2101010: |
9517 | case DRM_FORMAT_ARGB2101010: | |
9518 | case DRM_FORMAT_XBGR2101010: | |
9519 | case DRM_FORMAT_ABGR2101010: | |
9520 | /* checked in intel_framebuffer_init already */ | |
9521 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
baba133a | 9522 | return -EINVAL; |
4e53c2e0 DV |
9523 | bpp = 10*3; |
9524 | break; | |
baba133a | 9525 | /* TODO: gen4+ supports 16 bpc floating point, too. */ |
4e53c2e0 DV |
9526 | default: |
9527 | DRM_DEBUG_KMS("unsupported depth\n"); | |
9528 | return -EINVAL; | |
9529 | } | |
9530 | ||
4e53c2e0 DV |
9531 | pipe_config->pipe_bpp = bpp; |
9532 | ||
9533 | /* Clamp display bpp to EDID value */ | |
9534 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
050f7aeb | 9535 | base.head) { |
1b829e05 DV |
9536 | if (!connector->new_encoder || |
9537 | connector->new_encoder->new_crtc != crtc) | |
4e53c2e0 DV |
9538 | continue; |
9539 | ||
050f7aeb | 9540 | connected_sink_compute_bpp(connector, pipe_config); |
4e53c2e0 DV |
9541 | } |
9542 | ||
9543 | return bpp; | |
9544 | } | |
9545 | ||
644db711 DV |
9546 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
9547 | { | |
9548 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
9549 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 9550 | mode->crtc_clock, |
644db711 DV |
9551 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
9552 | mode->crtc_hsync_end, mode->crtc_htotal, | |
9553 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
9554 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
9555 | } | |
9556 | ||
c0b03411 DV |
9557 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
9558 | struct intel_crtc_config *pipe_config, | |
9559 | const char *context) | |
9560 | { | |
9561 | DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id, | |
9562 | context, pipe_name(crtc->pipe)); | |
9563 | ||
9564 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
9565 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
9566 | pipe_config->pipe_bpp, pipe_config->dither); | |
9567 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
9568 | pipe_config->has_pch_encoder, | |
9569 | pipe_config->fdi_lanes, | |
9570 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
9571 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
9572 | pipe_config->fdi_m_n.tu); | |
eb14cb74 VS |
9573 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
9574 | pipe_config->has_dp_encoder, | |
9575 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, | |
9576 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
9577 | pipe_config->dp_m_n.tu); | |
c0b03411 DV |
9578 | DRM_DEBUG_KMS("requested mode:\n"); |
9579 | drm_mode_debug_printmodeline(&pipe_config->requested_mode); | |
9580 | DRM_DEBUG_KMS("adjusted mode:\n"); | |
9581 | drm_mode_debug_printmodeline(&pipe_config->adjusted_mode); | |
644db711 | 9582 | intel_dump_crtc_timings(&pipe_config->adjusted_mode); |
d71b8d4a | 9583 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
9584 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
9585 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
c0b03411 DV |
9586 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
9587 | pipe_config->gmch_pfit.control, | |
9588 | pipe_config->gmch_pfit.pgm_ratios, | |
9589 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 9590 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 9591 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
9592 | pipe_config->pch_pfit.size, |
9593 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 9594 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 9595 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
c0b03411 DV |
9596 | } |
9597 | ||
bc079e8b VS |
9598 | static bool encoders_cloneable(const struct intel_encoder *a, |
9599 | const struct intel_encoder *b) | |
accfc0c5 | 9600 | { |
bc079e8b VS |
9601 | /* masks could be asymmetric, so check both ways */ |
9602 | return a == b || (a->cloneable & (1 << b->type) && | |
9603 | b->cloneable & (1 << a->type)); | |
9604 | } | |
9605 | ||
9606 | static bool check_single_encoder_cloning(struct intel_crtc *crtc, | |
9607 | struct intel_encoder *encoder) | |
9608 | { | |
9609 | struct drm_device *dev = crtc->base.dev; | |
9610 | struct intel_encoder *source_encoder; | |
9611 | ||
9612 | list_for_each_entry(source_encoder, | |
9613 | &dev->mode_config.encoder_list, base.head) { | |
9614 | if (source_encoder->new_crtc != crtc) | |
9615 | continue; | |
9616 | ||
9617 | if (!encoders_cloneable(encoder, source_encoder)) | |
9618 | return false; | |
9619 | } | |
9620 | ||
9621 | return true; | |
9622 | } | |
9623 | ||
9624 | static bool check_encoder_cloning(struct intel_crtc *crtc) | |
9625 | { | |
9626 | struct drm_device *dev = crtc->base.dev; | |
accfc0c5 DV |
9627 | struct intel_encoder *encoder; |
9628 | ||
bc079e8b VS |
9629 | list_for_each_entry(encoder, |
9630 | &dev->mode_config.encoder_list, base.head) { | |
9631 | if (encoder->new_crtc != crtc) | |
accfc0c5 DV |
9632 | continue; |
9633 | ||
bc079e8b VS |
9634 | if (!check_single_encoder_cloning(crtc, encoder)) |
9635 | return false; | |
accfc0c5 DV |
9636 | } |
9637 | ||
bc079e8b | 9638 | return true; |
accfc0c5 DV |
9639 | } |
9640 | ||
b8cecdf5 DV |
9641 | static struct intel_crtc_config * |
9642 | intel_modeset_pipe_config(struct drm_crtc *crtc, | |
4e53c2e0 | 9643 | struct drm_framebuffer *fb, |
b8cecdf5 | 9644 | struct drm_display_mode *mode) |
ee7b9f93 | 9645 | { |
7758a113 | 9646 | struct drm_device *dev = crtc->dev; |
7758a113 | 9647 | struct intel_encoder *encoder; |
b8cecdf5 | 9648 | struct intel_crtc_config *pipe_config; |
e29c22c0 DV |
9649 | int plane_bpp, ret = -EINVAL; |
9650 | bool retry = true; | |
ee7b9f93 | 9651 | |
bc079e8b | 9652 | if (!check_encoder_cloning(to_intel_crtc(crtc))) { |
accfc0c5 DV |
9653 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
9654 | return ERR_PTR(-EINVAL); | |
9655 | } | |
9656 | ||
b8cecdf5 DV |
9657 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
9658 | if (!pipe_config) | |
7758a113 DV |
9659 | return ERR_PTR(-ENOMEM); |
9660 | ||
b8cecdf5 DV |
9661 | drm_mode_copy(&pipe_config->adjusted_mode, mode); |
9662 | drm_mode_copy(&pipe_config->requested_mode, mode); | |
37327abd | 9663 | |
e143a21c DV |
9664 | pipe_config->cpu_transcoder = |
9665 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
c0d43d62 | 9666 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
b8cecdf5 | 9667 | |
2960bc9c ID |
9668 | /* |
9669 | * Sanitize sync polarity flags based on requested ones. If neither | |
9670 | * positive or negative polarity is requested, treat this as meaning | |
9671 | * negative polarity. | |
9672 | */ | |
9673 | if (!(pipe_config->adjusted_mode.flags & | |
9674 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) | |
9675 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; | |
9676 | ||
9677 | if (!(pipe_config->adjusted_mode.flags & | |
9678 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) | |
9679 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; | |
9680 | ||
050f7aeb DV |
9681 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
9682 | * plane pixel format and any sink constraints into account. Returns the | |
9683 | * source plane bpp so that dithering can be selected on mismatches | |
9684 | * after encoders and crtc also have had their say. */ | |
9685 | plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), | |
9686 | fb, pipe_config); | |
4e53c2e0 DV |
9687 | if (plane_bpp < 0) |
9688 | goto fail; | |
9689 | ||
e41a56be VS |
9690 | /* |
9691 | * Determine the real pipe dimensions. Note that stereo modes can | |
9692 | * increase the actual pipe size due to the frame doubling and | |
9693 | * insertion of additional space for blanks between the frame. This | |
9694 | * is stored in the crtc timings. We use the requested mode to do this | |
9695 | * computation to clearly distinguish it from the adjusted mode, which | |
9696 | * can be changed by the connectors in the below retry loop. | |
9697 | */ | |
9698 | drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE); | |
9699 | pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay; | |
9700 | pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay; | |
9701 | ||
e29c22c0 | 9702 | encoder_retry: |
ef1b460d | 9703 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 9704 | pipe_config->port_clock = 0; |
ef1b460d | 9705 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 9706 | |
135c81b8 | 9707 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
6ce70f5e | 9708 | drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE); |
135c81b8 | 9709 | |
7758a113 DV |
9710 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
9711 | * adjust it according to limitations or connector properties, and also | |
9712 | * a chance to reject the mode entirely. | |
47f1c6c9 | 9713 | */ |
7758a113 DV |
9714 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9715 | base.head) { | |
47f1c6c9 | 9716 | |
7758a113 DV |
9717 | if (&encoder->new_crtc->base != crtc) |
9718 | continue; | |
7ae89233 | 9719 | |
efea6e8e DV |
9720 | if (!(encoder->compute_config(encoder, pipe_config))) { |
9721 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
9722 | goto fail; |
9723 | } | |
ee7b9f93 | 9724 | } |
47f1c6c9 | 9725 | |
ff9a6750 DV |
9726 | /* Set default port clock if not overwritten by the encoder. Needs to be |
9727 | * done afterwards in case the encoder adjusts the mode. */ | |
9728 | if (!pipe_config->port_clock) | |
241bfc38 DL |
9729 | pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock |
9730 | * pipe_config->pixel_multiplier; | |
ff9a6750 | 9731 | |
a43f6e0f | 9732 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 9733 | if (ret < 0) { |
7758a113 DV |
9734 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
9735 | goto fail; | |
ee7b9f93 | 9736 | } |
e29c22c0 DV |
9737 | |
9738 | if (ret == RETRY) { | |
9739 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
9740 | ret = -EINVAL; | |
9741 | goto fail; | |
9742 | } | |
9743 | ||
9744 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
9745 | retry = false; | |
9746 | goto encoder_retry; | |
9747 | } | |
9748 | ||
4e53c2e0 DV |
9749 | pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; |
9750 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", | |
9751 | plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); | |
9752 | ||
b8cecdf5 | 9753 | return pipe_config; |
7758a113 | 9754 | fail: |
b8cecdf5 | 9755 | kfree(pipe_config); |
e29c22c0 | 9756 | return ERR_PTR(ret); |
ee7b9f93 | 9757 | } |
47f1c6c9 | 9758 | |
e2e1ed41 DV |
9759 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
9760 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ | |
9761 | static void | |
9762 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, | |
9763 | unsigned *prepare_pipes, unsigned *disable_pipes) | |
79e53945 JB |
9764 | { |
9765 | struct intel_crtc *intel_crtc; | |
e2e1ed41 DV |
9766 | struct drm_device *dev = crtc->dev; |
9767 | struct intel_encoder *encoder; | |
9768 | struct intel_connector *connector; | |
9769 | struct drm_crtc *tmp_crtc; | |
79e53945 | 9770 | |
e2e1ed41 | 9771 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
79e53945 | 9772 | |
e2e1ed41 DV |
9773 | /* Check which crtcs have changed outputs connected to them, these need |
9774 | * to be part of the prepare_pipes mask. We don't (yet) support global | |
9775 | * modeset across multiple crtcs, so modeset_pipes will only have one | |
9776 | * bit set at most. */ | |
9777 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
9778 | base.head) { | |
9779 | if (connector->base.encoder == &connector->new_encoder->base) | |
9780 | continue; | |
79e53945 | 9781 | |
e2e1ed41 DV |
9782 | if (connector->base.encoder) { |
9783 | tmp_crtc = connector->base.encoder->crtc; | |
9784 | ||
9785 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
9786 | } | |
9787 | ||
9788 | if (connector->new_encoder) | |
9789 | *prepare_pipes |= | |
9790 | 1 << connector->new_encoder->new_crtc->pipe; | |
79e53945 JB |
9791 | } |
9792 | ||
e2e1ed41 DV |
9793 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9794 | base.head) { | |
9795 | if (encoder->base.crtc == &encoder->new_crtc->base) | |
9796 | continue; | |
9797 | ||
9798 | if (encoder->base.crtc) { | |
9799 | tmp_crtc = encoder->base.crtc; | |
9800 | ||
9801 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
9802 | } | |
9803 | ||
9804 | if (encoder->new_crtc) | |
9805 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; | |
80824003 JB |
9806 | } |
9807 | ||
7668851f | 9808 | /* Check for pipes that will be enabled/disabled ... */ |
d3fcc808 | 9809 | for_each_intel_crtc(dev, intel_crtc) { |
7668851f | 9810 | if (intel_crtc->base.enabled == intel_crtc->new_enabled) |
e2e1ed41 | 9811 | continue; |
7e7d76c3 | 9812 | |
7668851f | 9813 | if (!intel_crtc->new_enabled) |
e2e1ed41 | 9814 | *disable_pipes |= 1 << intel_crtc->pipe; |
7668851f VS |
9815 | else |
9816 | *prepare_pipes |= 1 << intel_crtc->pipe; | |
7e7d76c3 JB |
9817 | } |
9818 | ||
e2e1ed41 DV |
9819 | |
9820 | /* set_mode is also used to update properties on life display pipes. */ | |
9821 | intel_crtc = to_intel_crtc(crtc); | |
7668851f | 9822 | if (intel_crtc->new_enabled) |
e2e1ed41 DV |
9823 | *prepare_pipes |= 1 << intel_crtc->pipe; |
9824 | ||
b6c5164d DV |
9825 | /* |
9826 | * For simplicity do a full modeset on any pipe where the output routing | |
9827 | * changed. We could be more clever, but that would require us to be | |
9828 | * more careful with calling the relevant encoder->mode_set functions. | |
9829 | */ | |
e2e1ed41 DV |
9830 | if (*prepare_pipes) |
9831 | *modeset_pipes = *prepare_pipes; | |
9832 | ||
9833 | /* ... and mask these out. */ | |
9834 | *modeset_pipes &= ~(*disable_pipes); | |
9835 | *prepare_pipes &= ~(*disable_pipes); | |
b6c5164d DV |
9836 | |
9837 | /* | |
9838 | * HACK: We don't (yet) fully support global modesets. intel_set_config | |
9839 | * obies this rule, but the modeset restore mode of | |
9840 | * intel_modeset_setup_hw_state does not. | |
9841 | */ | |
9842 | *modeset_pipes &= 1 << intel_crtc->pipe; | |
9843 | *prepare_pipes &= 1 << intel_crtc->pipe; | |
e3641d3f DV |
9844 | |
9845 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", | |
9846 | *modeset_pipes, *prepare_pipes, *disable_pipes); | |
47f1c6c9 | 9847 | } |
79e53945 | 9848 | |
ea9d758d | 9849 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 9850 | { |
ea9d758d | 9851 | struct drm_encoder *encoder; |
f6e5b160 | 9852 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 9853 | |
ea9d758d DV |
9854 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
9855 | if (encoder->crtc == crtc) | |
9856 | return true; | |
9857 | ||
9858 | return false; | |
9859 | } | |
9860 | ||
9861 | static void | |
9862 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) | |
9863 | { | |
9864 | struct intel_encoder *intel_encoder; | |
9865 | struct intel_crtc *intel_crtc; | |
9866 | struct drm_connector *connector; | |
9867 | ||
9868 | list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list, | |
9869 | base.head) { | |
9870 | if (!intel_encoder->base.crtc) | |
9871 | continue; | |
9872 | ||
9873 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
9874 | ||
9875 | if (prepare_pipes & (1 << intel_crtc->pipe)) | |
9876 | intel_encoder->connectors_active = false; | |
9877 | } | |
9878 | ||
9879 | intel_modeset_commit_output_state(dev); | |
9880 | ||
7668851f | 9881 | /* Double check state. */ |
d3fcc808 | 9882 | for_each_intel_crtc(dev, intel_crtc) { |
7668851f | 9883 | WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base)); |
7bd0a8e7 VS |
9884 | WARN_ON(intel_crtc->new_config && |
9885 | intel_crtc->new_config != &intel_crtc->config); | |
9886 | WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config); | |
ea9d758d DV |
9887 | } |
9888 | ||
9889 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
9890 | if (!connector->encoder || !connector->encoder->crtc) | |
9891 | continue; | |
9892 | ||
9893 | intel_crtc = to_intel_crtc(connector->encoder->crtc); | |
9894 | ||
9895 | if (prepare_pipes & (1 << intel_crtc->pipe)) { | |
68d34720 DV |
9896 | struct drm_property *dpms_property = |
9897 | dev->mode_config.dpms_property; | |
9898 | ||
ea9d758d | 9899 | connector->dpms = DRM_MODE_DPMS_ON; |
662595df | 9900 | drm_object_property_set_value(&connector->base, |
68d34720 DV |
9901 | dpms_property, |
9902 | DRM_MODE_DPMS_ON); | |
ea9d758d DV |
9903 | |
9904 | intel_encoder = to_intel_encoder(connector->encoder); | |
9905 | intel_encoder->connectors_active = true; | |
9906 | } | |
9907 | } | |
9908 | ||
9909 | } | |
9910 | ||
3bd26263 | 9911 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 9912 | { |
3bd26263 | 9913 | int diff; |
f1f644dc JB |
9914 | |
9915 | if (clock1 == clock2) | |
9916 | return true; | |
9917 | ||
9918 | if (!clock1 || !clock2) | |
9919 | return false; | |
9920 | ||
9921 | diff = abs(clock1 - clock2); | |
9922 | ||
9923 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
9924 | return true; | |
9925 | ||
9926 | return false; | |
9927 | } | |
9928 | ||
25c5b266 DV |
9929 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
9930 | list_for_each_entry((intel_crtc), \ | |
9931 | &(dev)->mode_config.crtc_list, \ | |
9932 | base.head) \ | |
0973f18f | 9933 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 9934 | |
0e8ffe1b | 9935 | static bool |
2fa2fe9a DV |
9936 | intel_pipe_config_compare(struct drm_device *dev, |
9937 | struct intel_crtc_config *current_config, | |
0e8ffe1b DV |
9938 | struct intel_crtc_config *pipe_config) |
9939 | { | |
66e985c0 DV |
9940 | #define PIPE_CONF_CHECK_X(name) \ |
9941 | if (current_config->name != pipe_config->name) { \ | |
9942 | DRM_ERROR("mismatch in " #name " " \ | |
9943 | "(expected 0x%08x, found 0x%08x)\n", \ | |
9944 | current_config->name, \ | |
9945 | pipe_config->name); \ | |
9946 | return false; \ | |
9947 | } | |
9948 | ||
08a24034 DV |
9949 | #define PIPE_CONF_CHECK_I(name) \ |
9950 | if (current_config->name != pipe_config->name) { \ | |
9951 | DRM_ERROR("mismatch in " #name " " \ | |
9952 | "(expected %i, found %i)\n", \ | |
9953 | current_config->name, \ | |
9954 | pipe_config->name); \ | |
9955 | return false; \ | |
88adfff1 DV |
9956 | } |
9957 | ||
1bd1bd80 DV |
9958 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
9959 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
6f02488e | 9960 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
9961 | "(expected %i, found %i)\n", \ |
9962 | current_config->name & (mask), \ | |
9963 | pipe_config->name & (mask)); \ | |
9964 | return false; \ | |
9965 | } | |
9966 | ||
5e550656 VS |
9967 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
9968 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
9969 | DRM_ERROR("mismatch in " #name " " \ | |
9970 | "(expected %i, found %i)\n", \ | |
9971 | current_config->name, \ | |
9972 | pipe_config->name); \ | |
9973 | return false; \ | |
9974 | } | |
9975 | ||
bb760063 DV |
9976 | #define PIPE_CONF_QUIRK(quirk) \ |
9977 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
9978 | ||
eccb140b DV |
9979 | PIPE_CONF_CHECK_I(cpu_transcoder); |
9980 | ||
08a24034 DV |
9981 | PIPE_CONF_CHECK_I(has_pch_encoder); |
9982 | PIPE_CONF_CHECK_I(fdi_lanes); | |
72419203 DV |
9983 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
9984 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); | |
9985 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); | |
9986 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); | |
9987 | PIPE_CONF_CHECK_I(fdi_m_n.tu); | |
08a24034 | 9988 | |
eb14cb74 VS |
9989 | PIPE_CONF_CHECK_I(has_dp_encoder); |
9990 | PIPE_CONF_CHECK_I(dp_m_n.gmch_m); | |
9991 | PIPE_CONF_CHECK_I(dp_m_n.gmch_n); | |
9992 | PIPE_CONF_CHECK_I(dp_m_n.link_m); | |
9993 | PIPE_CONF_CHECK_I(dp_m_n.link_n); | |
9994 | PIPE_CONF_CHECK_I(dp_m_n.tu); | |
9995 | ||
1bd1bd80 DV |
9996 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); |
9997 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); | |
9998 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start); | |
9999 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end); | |
10000 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start); | |
10001 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end); | |
10002 | ||
10003 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay); | |
10004 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal); | |
10005 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start); | |
10006 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end); | |
10007 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start); | |
10008 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end); | |
10009 | ||
c93f54cf | 10010 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 10011 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 DV |
10012 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
10013 | IS_VALLEYVIEW(dev)) | |
10014 | PIPE_CONF_CHECK_I(limited_color_range); | |
6c49f241 | 10015 | |
9ed109a7 DV |
10016 | PIPE_CONF_CHECK_I(has_audio); |
10017 | ||
1bd1bd80 DV |
10018 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
10019 | DRM_MODE_FLAG_INTERLACE); | |
10020 | ||
bb760063 DV |
10021 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
10022 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
10023 | DRM_MODE_FLAG_PHSYNC); | |
10024 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
10025 | DRM_MODE_FLAG_NHSYNC); | |
10026 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
10027 | DRM_MODE_FLAG_PVSYNC); | |
10028 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
10029 | DRM_MODE_FLAG_NVSYNC); | |
10030 | } | |
045ac3b5 | 10031 | |
37327abd VS |
10032 | PIPE_CONF_CHECK_I(pipe_src_w); |
10033 | PIPE_CONF_CHECK_I(pipe_src_h); | |
1bd1bd80 | 10034 | |
9953599b DV |
10035 | /* |
10036 | * FIXME: BIOS likes to set up a cloned config with lvds+external | |
10037 | * screen. Since we don't yet re-compute the pipe config when moving | |
10038 | * just the lvds port away to another pipe the sw tracking won't match. | |
10039 | * | |
10040 | * Proper atomic modesets with recomputed global state will fix this. | |
10041 | * Until then just don't check gmch state for inherited modes. | |
10042 | */ | |
10043 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) { | |
10044 | PIPE_CONF_CHECK_I(gmch_pfit.control); | |
10045 | /* pfit ratios are autocomputed by the hw on gen4+ */ | |
10046 | if (INTEL_INFO(dev)->gen < 4) | |
10047 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
10048 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); | |
10049 | } | |
10050 | ||
fd4daa9c CW |
10051 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
10052 | if (current_config->pch_pfit.enabled) { | |
10053 | PIPE_CONF_CHECK_I(pch_pfit.pos); | |
10054 | PIPE_CONF_CHECK_I(pch_pfit.size); | |
10055 | } | |
2fa2fe9a | 10056 | |
e59150dc JB |
10057 | /* BDW+ don't expose a synchronous way to read the state */ |
10058 | if (IS_HASWELL(dev)) | |
10059 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 10060 | |
282740f7 VS |
10061 | PIPE_CONF_CHECK_I(double_wide); |
10062 | ||
c0d43d62 | 10063 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 10064 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 10065 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
10066 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
10067 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
c0d43d62 | 10068 | |
42571aef VS |
10069 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
10070 | PIPE_CONF_CHECK_I(pipe_bpp); | |
10071 | ||
a9a7e98a JB |
10072 | PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock); |
10073 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); | |
5e550656 | 10074 | |
66e985c0 | 10075 | #undef PIPE_CONF_CHECK_X |
08a24034 | 10076 | #undef PIPE_CONF_CHECK_I |
1bd1bd80 | 10077 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 10078 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 10079 | #undef PIPE_CONF_QUIRK |
88adfff1 | 10080 | |
0e8ffe1b DV |
10081 | return true; |
10082 | } | |
10083 | ||
91d1b4bd DV |
10084 | static void |
10085 | check_connector_state(struct drm_device *dev) | |
8af6cf88 | 10086 | { |
8af6cf88 DV |
10087 | struct intel_connector *connector; |
10088 | ||
10089 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
10090 | base.head) { | |
10091 | /* This also checks the encoder/connector hw state with the | |
10092 | * ->get_hw_state callbacks. */ | |
10093 | intel_connector_check_state(connector); | |
10094 | ||
10095 | WARN(&connector->new_encoder->base != connector->base.encoder, | |
10096 | "connector's staged encoder doesn't match current encoder\n"); | |
10097 | } | |
91d1b4bd DV |
10098 | } |
10099 | ||
10100 | static void | |
10101 | check_encoder_state(struct drm_device *dev) | |
10102 | { | |
10103 | struct intel_encoder *encoder; | |
10104 | struct intel_connector *connector; | |
8af6cf88 DV |
10105 | |
10106 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
10107 | base.head) { | |
10108 | bool enabled = false; | |
10109 | bool active = false; | |
10110 | enum pipe pipe, tracked_pipe; | |
10111 | ||
10112 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
10113 | encoder->base.base.id, | |
8e329a03 | 10114 | encoder->base.name); |
8af6cf88 DV |
10115 | |
10116 | WARN(&encoder->new_crtc->base != encoder->base.crtc, | |
10117 | "encoder's stage crtc doesn't match current crtc\n"); | |
10118 | WARN(encoder->connectors_active && !encoder->base.crtc, | |
10119 | "encoder's active_connectors set, but no crtc\n"); | |
10120 | ||
10121 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
10122 | base.head) { | |
10123 | if (connector->base.encoder != &encoder->base) | |
10124 | continue; | |
10125 | enabled = true; | |
10126 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
10127 | active = true; | |
10128 | } | |
10129 | WARN(!!encoder->base.crtc != enabled, | |
10130 | "encoder's enabled state mismatch " | |
10131 | "(expected %i, found %i)\n", | |
10132 | !!encoder->base.crtc, enabled); | |
10133 | WARN(active && !encoder->base.crtc, | |
10134 | "active encoder with no crtc\n"); | |
10135 | ||
10136 | WARN(encoder->connectors_active != active, | |
10137 | "encoder's computed active state doesn't match tracked active state " | |
10138 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
10139 | ||
10140 | active = encoder->get_hw_state(encoder, &pipe); | |
10141 | WARN(active != encoder->connectors_active, | |
10142 | "encoder's hw state doesn't match sw tracking " | |
10143 | "(expected %i, found %i)\n", | |
10144 | encoder->connectors_active, active); | |
10145 | ||
10146 | if (!encoder->base.crtc) | |
10147 | continue; | |
10148 | ||
10149 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
10150 | WARN(active && pipe != tracked_pipe, | |
10151 | "active encoder's pipe doesn't match" | |
10152 | "(expected %i, found %i)\n", | |
10153 | tracked_pipe, pipe); | |
10154 | ||
10155 | } | |
91d1b4bd DV |
10156 | } |
10157 | ||
10158 | static void | |
10159 | check_crtc_state(struct drm_device *dev) | |
10160 | { | |
fbee40df | 10161 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
10162 | struct intel_crtc *crtc; |
10163 | struct intel_encoder *encoder; | |
10164 | struct intel_crtc_config pipe_config; | |
8af6cf88 | 10165 | |
d3fcc808 | 10166 | for_each_intel_crtc(dev, crtc) { |
8af6cf88 DV |
10167 | bool enabled = false; |
10168 | bool active = false; | |
10169 | ||
045ac3b5 JB |
10170 | memset(&pipe_config, 0, sizeof(pipe_config)); |
10171 | ||
8af6cf88 DV |
10172 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
10173 | crtc->base.base.id); | |
10174 | ||
10175 | WARN(crtc->active && !crtc->base.enabled, | |
10176 | "active crtc, but not enabled in sw tracking\n"); | |
10177 | ||
10178 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
10179 | base.head) { | |
10180 | if (encoder->base.crtc != &crtc->base) | |
10181 | continue; | |
10182 | enabled = true; | |
10183 | if (encoder->connectors_active) | |
10184 | active = true; | |
10185 | } | |
6c49f241 | 10186 | |
8af6cf88 DV |
10187 | WARN(active != crtc->active, |
10188 | "crtc's computed active state doesn't match tracked active state " | |
10189 | "(expected %i, found %i)\n", active, crtc->active); | |
10190 | WARN(enabled != crtc->base.enabled, | |
10191 | "crtc's computed enabled state doesn't match tracked enabled state " | |
10192 | "(expected %i, found %i)\n", enabled, crtc->base.enabled); | |
10193 | ||
0e8ffe1b DV |
10194 | active = dev_priv->display.get_pipe_config(crtc, |
10195 | &pipe_config); | |
d62cf62a DV |
10196 | |
10197 | /* hw state is inconsistent with the pipe A quirk */ | |
10198 | if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
10199 | active = crtc->active; | |
10200 | ||
6c49f241 DV |
10201 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
10202 | base.head) { | |
3eaba51c | 10203 | enum pipe pipe; |
6c49f241 DV |
10204 | if (encoder->base.crtc != &crtc->base) |
10205 | continue; | |
1d37b689 | 10206 | if (encoder->get_hw_state(encoder, &pipe)) |
6c49f241 DV |
10207 | encoder->get_config(encoder, &pipe_config); |
10208 | } | |
10209 | ||
0e8ffe1b DV |
10210 | WARN(crtc->active != active, |
10211 | "crtc active state doesn't match with hw state " | |
10212 | "(expected %i, found %i)\n", crtc->active, active); | |
10213 | ||
c0b03411 DV |
10214 | if (active && |
10215 | !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) { | |
10216 | WARN(1, "pipe state doesn't match!\n"); | |
10217 | intel_dump_pipe_config(crtc, &pipe_config, | |
10218 | "[hw state]"); | |
10219 | intel_dump_pipe_config(crtc, &crtc->config, | |
10220 | "[sw state]"); | |
10221 | } | |
8af6cf88 DV |
10222 | } |
10223 | } | |
10224 | ||
91d1b4bd DV |
10225 | static void |
10226 | check_shared_dpll_state(struct drm_device *dev) | |
10227 | { | |
fbee40df | 10228 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
10229 | struct intel_crtc *crtc; |
10230 | struct intel_dpll_hw_state dpll_hw_state; | |
10231 | int i; | |
5358901f DV |
10232 | |
10233 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
10234 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
10235 | int enabled_crtcs = 0, active_crtcs = 0; | |
10236 | bool active; | |
10237 | ||
10238 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
10239 | ||
10240 | DRM_DEBUG_KMS("%s\n", pll->name); | |
10241 | ||
10242 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
10243 | ||
10244 | WARN(pll->active > pll->refcount, | |
10245 | "more active pll users than references: %i vs %i\n", | |
10246 | pll->active, pll->refcount); | |
10247 | WARN(pll->active && !pll->on, | |
10248 | "pll in active use but not on in sw tracking\n"); | |
35c95375 DV |
10249 | WARN(pll->on && !pll->active, |
10250 | "pll in on but not on in use in sw tracking\n"); | |
5358901f DV |
10251 | WARN(pll->on != active, |
10252 | "pll on state mismatch (expected %i, found %i)\n", | |
10253 | pll->on, active); | |
10254 | ||
d3fcc808 | 10255 | for_each_intel_crtc(dev, crtc) { |
5358901f DV |
10256 | if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll) |
10257 | enabled_crtcs++; | |
10258 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
10259 | active_crtcs++; | |
10260 | } | |
10261 | WARN(pll->active != active_crtcs, | |
10262 | "pll active crtcs mismatch (expected %i, found %i)\n", | |
10263 | pll->active, active_crtcs); | |
10264 | WARN(pll->refcount != enabled_crtcs, | |
10265 | "pll enabled crtcs mismatch (expected %i, found %i)\n", | |
10266 | pll->refcount, enabled_crtcs); | |
66e985c0 DV |
10267 | |
10268 | WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state, | |
10269 | sizeof(dpll_hw_state)), | |
10270 | "pll hw state mismatch\n"); | |
5358901f | 10271 | } |
8af6cf88 DV |
10272 | } |
10273 | ||
91d1b4bd DV |
10274 | void |
10275 | intel_modeset_check_state(struct drm_device *dev) | |
10276 | { | |
10277 | check_connector_state(dev); | |
10278 | check_encoder_state(dev); | |
10279 | check_crtc_state(dev); | |
10280 | check_shared_dpll_state(dev); | |
10281 | } | |
10282 | ||
18442d08 VS |
10283 | void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, |
10284 | int dotclock) | |
10285 | { | |
10286 | /* | |
10287 | * FDI already provided one idea for the dotclock. | |
10288 | * Yell if the encoder disagrees. | |
10289 | */ | |
241bfc38 | 10290 | WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock), |
18442d08 | 10291 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
241bfc38 | 10292 | pipe_config->adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
10293 | } |
10294 | ||
80715b2f VS |
10295 | static void update_scanline_offset(struct intel_crtc *crtc) |
10296 | { | |
10297 | struct drm_device *dev = crtc->base.dev; | |
10298 | ||
10299 | /* | |
10300 | * The scanline counter increments at the leading edge of hsync. | |
10301 | * | |
10302 | * On most platforms it starts counting from vtotal-1 on the | |
10303 | * first active line. That means the scanline counter value is | |
10304 | * always one less than what we would expect. Ie. just after | |
10305 | * start of vblank, which also occurs at start of hsync (on the | |
10306 | * last active line), the scanline counter will read vblank_start-1. | |
10307 | * | |
10308 | * On gen2 the scanline counter starts counting from 1 instead | |
10309 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
10310 | * to keep the value positive), instead of adding one. | |
10311 | * | |
10312 | * On HSW+ the behaviour of the scanline counter depends on the output | |
10313 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
10314 | * there's an extra 1 line difference. So we need to add two instead of | |
10315 | * one to the value. | |
10316 | */ | |
10317 | if (IS_GEN2(dev)) { | |
10318 | const struct drm_display_mode *mode = &crtc->config.adjusted_mode; | |
10319 | int vtotal; | |
10320 | ||
10321 | vtotal = mode->crtc_vtotal; | |
10322 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
10323 | vtotal /= 2; | |
10324 | ||
10325 | crtc->scanline_offset = vtotal - 1; | |
10326 | } else if (HAS_DDI(dev) && | |
10327 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) { | |
10328 | crtc->scanline_offset = 2; | |
10329 | } else | |
10330 | crtc->scanline_offset = 1; | |
10331 | } | |
10332 | ||
f30da187 DV |
10333 | static int __intel_set_mode(struct drm_crtc *crtc, |
10334 | struct drm_display_mode *mode, | |
10335 | int x, int y, struct drm_framebuffer *fb) | |
a6778b3c DV |
10336 | { |
10337 | struct drm_device *dev = crtc->dev; | |
fbee40df | 10338 | struct drm_i915_private *dev_priv = dev->dev_private; |
4b4b9238 | 10339 | struct drm_display_mode *saved_mode; |
b8cecdf5 | 10340 | struct intel_crtc_config *pipe_config = NULL; |
25c5b266 DV |
10341 | struct intel_crtc *intel_crtc; |
10342 | unsigned disable_pipes, prepare_pipes, modeset_pipes; | |
c0c36b94 | 10343 | int ret = 0; |
a6778b3c | 10344 | |
4b4b9238 | 10345 | saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL); |
c0c36b94 CW |
10346 | if (!saved_mode) |
10347 | return -ENOMEM; | |
a6778b3c | 10348 | |
e2e1ed41 | 10349 | intel_modeset_affected_pipes(crtc, &modeset_pipes, |
25c5b266 DV |
10350 | &prepare_pipes, &disable_pipes); |
10351 | ||
3ac18232 | 10352 | *saved_mode = crtc->mode; |
a6778b3c | 10353 | |
25c5b266 DV |
10354 | /* Hack: Because we don't (yet) support global modeset on multiple |
10355 | * crtcs, we don't keep track of the new mode for more than one crtc. | |
10356 | * Hence simply check whether any bit is set in modeset_pipes in all the | |
10357 | * pieces of code that are not yet converted to deal with mutliple crtcs | |
10358 | * changing their mode at the same time. */ | |
25c5b266 | 10359 | if (modeset_pipes) { |
4e53c2e0 | 10360 | pipe_config = intel_modeset_pipe_config(crtc, fb, mode); |
b8cecdf5 DV |
10361 | if (IS_ERR(pipe_config)) { |
10362 | ret = PTR_ERR(pipe_config); | |
10363 | pipe_config = NULL; | |
10364 | ||
3ac18232 | 10365 | goto out; |
25c5b266 | 10366 | } |
c0b03411 DV |
10367 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
10368 | "[modeset]"); | |
50741abc | 10369 | to_intel_crtc(crtc)->new_config = pipe_config; |
25c5b266 | 10370 | } |
a6778b3c | 10371 | |
30a970c6 JB |
10372 | /* |
10373 | * See if the config requires any additional preparation, e.g. | |
10374 | * to adjust global state with pipes off. We need to do this | |
10375 | * here so we can get the modeset_pipe updated config for the new | |
10376 | * mode set on this crtc. For other crtcs we need to use the | |
10377 | * adjusted_mode bits in the crtc directly. | |
10378 | */ | |
c164f833 | 10379 | if (IS_VALLEYVIEW(dev)) { |
2f2d7aa1 | 10380 | valleyview_modeset_global_pipes(dev, &prepare_pipes); |
30a970c6 | 10381 | |
c164f833 VS |
10382 | /* may have added more to prepare_pipes than we should */ |
10383 | prepare_pipes &= ~disable_pipes; | |
10384 | } | |
10385 | ||
460da916 DV |
10386 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
10387 | intel_crtc_disable(&intel_crtc->base); | |
10388 | ||
ea9d758d DV |
10389 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
10390 | if (intel_crtc->base.enabled) | |
10391 | dev_priv->display.crtc_disable(&intel_crtc->base); | |
10392 | } | |
a6778b3c | 10393 | |
6c4c86f5 DV |
10394 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
10395 | * to set it here already despite that we pass it down the callchain. | |
f6e5b160 | 10396 | */ |
b8cecdf5 | 10397 | if (modeset_pipes) { |
25c5b266 | 10398 | crtc->mode = *mode; |
b8cecdf5 DV |
10399 | /* mode_set/enable/disable functions rely on a correct pipe |
10400 | * config. */ | |
10401 | to_intel_crtc(crtc)->config = *pipe_config; | |
50741abc | 10402 | to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config; |
c326c0a9 VS |
10403 | |
10404 | /* | |
10405 | * Calculate and store various constants which | |
10406 | * are later needed by vblank and swap-completion | |
10407 | * timestamping. They are derived from true hwmode. | |
10408 | */ | |
10409 | drm_calc_timestamping_constants(crtc, | |
10410 | &pipe_config->adjusted_mode); | |
b8cecdf5 | 10411 | } |
7758a113 | 10412 | |
ea9d758d DV |
10413 | /* Only after disabling all output pipelines that will be changed can we |
10414 | * update the the output configuration. */ | |
10415 | intel_modeset_update_state(dev, prepare_pipes); | |
f6e5b160 | 10416 | |
47fab737 DV |
10417 | if (dev_priv->display.modeset_global_resources) |
10418 | dev_priv->display.modeset_global_resources(dev); | |
10419 | ||
a6778b3c DV |
10420 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
10421 | * on the DPLL. | |
f6e5b160 | 10422 | */ |
25c5b266 | 10423 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
4c10794f DV |
10424 | struct drm_framebuffer *old_fb; |
10425 | ||
10426 | mutex_lock(&dev->struct_mutex); | |
10427 | ret = intel_pin_and_fence_fb_obj(dev, | |
10428 | to_intel_framebuffer(fb)->obj, | |
10429 | NULL); | |
10430 | if (ret != 0) { | |
10431 | DRM_ERROR("pin & fence failed\n"); | |
10432 | mutex_unlock(&dev->struct_mutex); | |
10433 | goto done; | |
10434 | } | |
10435 | old_fb = crtc->primary->fb; | |
10436 | if (old_fb) | |
10437 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); | |
10438 | mutex_unlock(&dev->struct_mutex); | |
10439 | ||
10440 | crtc->primary->fb = fb; | |
10441 | crtc->x = x; | |
10442 | crtc->y = y; | |
10443 | ||
4271b753 DV |
10444 | ret = dev_priv->display.crtc_mode_set(&intel_crtc->base, |
10445 | x, y, fb); | |
c0c36b94 CW |
10446 | if (ret) |
10447 | goto done; | |
a6778b3c DV |
10448 | } |
10449 | ||
10450 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
80715b2f VS |
10451 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
10452 | update_scanline_offset(intel_crtc); | |
10453 | ||
25c5b266 | 10454 | dev_priv->display.crtc_enable(&intel_crtc->base); |
80715b2f | 10455 | } |
a6778b3c | 10456 | |
a6778b3c DV |
10457 | /* FIXME: add subpixel order */ |
10458 | done: | |
4b4b9238 | 10459 | if (ret && crtc->enabled) |
3ac18232 | 10460 | crtc->mode = *saved_mode; |
a6778b3c | 10461 | |
3ac18232 | 10462 | out: |
b8cecdf5 | 10463 | kfree(pipe_config); |
3ac18232 | 10464 | kfree(saved_mode); |
a6778b3c | 10465 | return ret; |
f6e5b160 CW |
10466 | } |
10467 | ||
e7457a9a DL |
10468 | static int intel_set_mode(struct drm_crtc *crtc, |
10469 | struct drm_display_mode *mode, | |
10470 | int x, int y, struct drm_framebuffer *fb) | |
f30da187 DV |
10471 | { |
10472 | int ret; | |
10473 | ||
10474 | ret = __intel_set_mode(crtc, mode, x, y, fb); | |
10475 | ||
10476 | if (ret == 0) | |
10477 | intel_modeset_check_state(crtc->dev); | |
10478 | ||
10479 | return ret; | |
10480 | } | |
10481 | ||
c0c36b94 CW |
10482 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
10483 | { | |
f4510a27 | 10484 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb); |
c0c36b94 CW |
10485 | } |
10486 | ||
25c5b266 DV |
10487 | #undef for_each_intel_crtc_masked |
10488 | ||
d9e55608 DV |
10489 | static void intel_set_config_free(struct intel_set_config *config) |
10490 | { | |
10491 | if (!config) | |
10492 | return; | |
10493 | ||
1aa4b628 DV |
10494 | kfree(config->save_connector_encoders); |
10495 | kfree(config->save_encoder_crtcs); | |
7668851f | 10496 | kfree(config->save_crtc_enabled); |
d9e55608 DV |
10497 | kfree(config); |
10498 | } | |
10499 | ||
85f9eb71 DV |
10500 | static int intel_set_config_save_state(struct drm_device *dev, |
10501 | struct intel_set_config *config) | |
10502 | { | |
7668851f | 10503 | struct drm_crtc *crtc; |
85f9eb71 DV |
10504 | struct drm_encoder *encoder; |
10505 | struct drm_connector *connector; | |
10506 | int count; | |
10507 | ||
7668851f VS |
10508 | config->save_crtc_enabled = |
10509 | kcalloc(dev->mode_config.num_crtc, | |
10510 | sizeof(bool), GFP_KERNEL); | |
10511 | if (!config->save_crtc_enabled) | |
10512 | return -ENOMEM; | |
10513 | ||
1aa4b628 DV |
10514 | config->save_encoder_crtcs = |
10515 | kcalloc(dev->mode_config.num_encoder, | |
10516 | sizeof(struct drm_crtc *), GFP_KERNEL); | |
10517 | if (!config->save_encoder_crtcs) | |
85f9eb71 DV |
10518 | return -ENOMEM; |
10519 | ||
1aa4b628 DV |
10520 | config->save_connector_encoders = |
10521 | kcalloc(dev->mode_config.num_connector, | |
10522 | sizeof(struct drm_encoder *), GFP_KERNEL); | |
10523 | if (!config->save_connector_encoders) | |
85f9eb71 DV |
10524 | return -ENOMEM; |
10525 | ||
10526 | /* Copy data. Note that driver private data is not affected. | |
10527 | * Should anything bad happen only the expected state is | |
10528 | * restored, not the drivers personal bookkeeping. | |
10529 | */ | |
7668851f | 10530 | count = 0; |
70e1e0ec | 10531 | for_each_crtc(dev, crtc) { |
7668851f VS |
10532 | config->save_crtc_enabled[count++] = crtc->enabled; |
10533 | } | |
10534 | ||
85f9eb71 DV |
10535 | count = 0; |
10536 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1aa4b628 | 10537 | config->save_encoder_crtcs[count++] = encoder->crtc; |
85f9eb71 DV |
10538 | } |
10539 | ||
10540 | count = 0; | |
10541 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1aa4b628 | 10542 | config->save_connector_encoders[count++] = connector->encoder; |
85f9eb71 DV |
10543 | } |
10544 | ||
10545 | return 0; | |
10546 | } | |
10547 | ||
10548 | static void intel_set_config_restore_state(struct drm_device *dev, | |
10549 | struct intel_set_config *config) | |
10550 | { | |
7668851f | 10551 | struct intel_crtc *crtc; |
9a935856 DV |
10552 | struct intel_encoder *encoder; |
10553 | struct intel_connector *connector; | |
85f9eb71 DV |
10554 | int count; |
10555 | ||
7668851f | 10556 | count = 0; |
d3fcc808 | 10557 | for_each_intel_crtc(dev, crtc) { |
7668851f | 10558 | crtc->new_enabled = config->save_crtc_enabled[count++]; |
7bd0a8e7 VS |
10559 | |
10560 | if (crtc->new_enabled) | |
10561 | crtc->new_config = &crtc->config; | |
10562 | else | |
10563 | crtc->new_config = NULL; | |
7668851f VS |
10564 | } |
10565 | ||
85f9eb71 | 10566 | count = 0; |
9a935856 DV |
10567 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
10568 | encoder->new_crtc = | |
10569 | to_intel_crtc(config->save_encoder_crtcs[count++]); | |
85f9eb71 DV |
10570 | } |
10571 | ||
10572 | count = 0; | |
9a935856 DV |
10573 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
10574 | connector->new_encoder = | |
10575 | to_intel_encoder(config->save_connector_encoders[count++]); | |
85f9eb71 DV |
10576 | } |
10577 | } | |
10578 | ||
e3de42b6 | 10579 | static bool |
2e57f47d | 10580 | is_crtc_connector_off(struct drm_mode_set *set) |
e3de42b6 ID |
10581 | { |
10582 | int i; | |
10583 | ||
2e57f47d CW |
10584 | if (set->num_connectors == 0) |
10585 | return false; | |
10586 | ||
10587 | if (WARN_ON(set->connectors == NULL)) | |
10588 | return false; | |
10589 | ||
10590 | for (i = 0; i < set->num_connectors; i++) | |
10591 | if (set->connectors[i]->encoder && | |
10592 | set->connectors[i]->encoder->crtc == set->crtc && | |
10593 | set->connectors[i]->dpms != DRM_MODE_DPMS_ON) | |
e3de42b6 ID |
10594 | return true; |
10595 | ||
10596 | return false; | |
10597 | } | |
10598 | ||
5e2b584e DV |
10599 | static void |
10600 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, | |
10601 | struct intel_set_config *config) | |
10602 | { | |
10603 | ||
10604 | /* We should be able to check here if the fb has the same properties | |
10605 | * and then just flip_or_move it */ | |
2e57f47d CW |
10606 | if (is_crtc_connector_off(set)) { |
10607 | config->mode_changed = true; | |
f4510a27 | 10608 | } else if (set->crtc->primary->fb != set->fb) { |
3b150f08 MR |
10609 | /* |
10610 | * If we have no fb, we can only flip as long as the crtc is | |
10611 | * active, otherwise we need a full mode set. The crtc may | |
10612 | * be active if we've only disabled the primary plane, or | |
10613 | * in fastboot situations. | |
10614 | */ | |
f4510a27 | 10615 | if (set->crtc->primary->fb == NULL) { |
319d9827 JB |
10616 | struct intel_crtc *intel_crtc = |
10617 | to_intel_crtc(set->crtc); | |
10618 | ||
3b150f08 | 10619 | if (intel_crtc->active) { |
319d9827 JB |
10620 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); |
10621 | config->fb_changed = true; | |
10622 | } else { | |
10623 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); | |
10624 | config->mode_changed = true; | |
10625 | } | |
5e2b584e DV |
10626 | } else if (set->fb == NULL) { |
10627 | config->mode_changed = true; | |
72f4901e | 10628 | } else if (set->fb->pixel_format != |
f4510a27 | 10629 | set->crtc->primary->fb->pixel_format) { |
5e2b584e | 10630 | config->mode_changed = true; |
e3de42b6 | 10631 | } else { |
5e2b584e | 10632 | config->fb_changed = true; |
e3de42b6 | 10633 | } |
5e2b584e DV |
10634 | } |
10635 | ||
835c5873 | 10636 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
5e2b584e DV |
10637 | config->fb_changed = true; |
10638 | ||
10639 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { | |
10640 | DRM_DEBUG_KMS("modes are different, full mode set\n"); | |
10641 | drm_mode_debug_printmodeline(&set->crtc->mode); | |
10642 | drm_mode_debug_printmodeline(set->mode); | |
10643 | config->mode_changed = true; | |
10644 | } | |
a1d95703 CW |
10645 | |
10646 | DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", | |
10647 | set->crtc->base.id, config->mode_changed, config->fb_changed); | |
5e2b584e DV |
10648 | } |
10649 | ||
2e431051 | 10650 | static int |
9a935856 DV |
10651 | intel_modeset_stage_output_state(struct drm_device *dev, |
10652 | struct drm_mode_set *set, | |
10653 | struct intel_set_config *config) | |
50f56119 | 10654 | { |
9a935856 DV |
10655 | struct intel_connector *connector; |
10656 | struct intel_encoder *encoder; | |
7668851f | 10657 | struct intel_crtc *crtc; |
f3f08572 | 10658 | int ro; |
50f56119 | 10659 | |
9abdda74 | 10660 | /* The upper layers ensure that we either disable a crtc or have a list |
9a935856 DV |
10661 | * of connectors. For paranoia, double-check this. */ |
10662 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
10663 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
10664 | ||
9a935856 DV |
10665 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
10666 | base.head) { | |
10667 | /* Otherwise traverse passed in connector list and get encoders | |
10668 | * for them. */ | |
50f56119 | 10669 | for (ro = 0; ro < set->num_connectors; ro++) { |
9a935856 DV |
10670 | if (set->connectors[ro] == &connector->base) { |
10671 | connector->new_encoder = connector->encoder; | |
50f56119 DV |
10672 | break; |
10673 | } | |
10674 | } | |
10675 | ||
9a935856 DV |
10676 | /* If we disable the crtc, disable all its connectors. Also, if |
10677 | * the connector is on the changing crtc but not on the new | |
10678 | * connector list, disable it. */ | |
10679 | if ((!set->fb || ro == set->num_connectors) && | |
10680 | connector->base.encoder && | |
10681 | connector->base.encoder->crtc == set->crtc) { | |
10682 | connector->new_encoder = NULL; | |
10683 | ||
10684 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
10685 | connector->base.base.id, | |
c23cc417 | 10686 | connector->base.name); |
9a935856 DV |
10687 | } |
10688 | ||
10689 | ||
10690 | if (&connector->new_encoder->base != connector->base.encoder) { | |
50f56119 | 10691 | DRM_DEBUG_KMS("encoder changed, full mode switch\n"); |
5e2b584e | 10692 | config->mode_changed = true; |
50f56119 DV |
10693 | } |
10694 | } | |
9a935856 | 10695 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 10696 | |
9a935856 | 10697 | /* Update crtc of enabled connectors. */ |
9a935856 DV |
10698 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
10699 | base.head) { | |
7668851f VS |
10700 | struct drm_crtc *new_crtc; |
10701 | ||
9a935856 | 10702 | if (!connector->new_encoder) |
50f56119 DV |
10703 | continue; |
10704 | ||
9a935856 | 10705 | new_crtc = connector->new_encoder->base.crtc; |
50f56119 DV |
10706 | |
10707 | for (ro = 0; ro < set->num_connectors; ro++) { | |
9a935856 | 10708 | if (set->connectors[ro] == &connector->base) |
50f56119 DV |
10709 | new_crtc = set->crtc; |
10710 | } | |
10711 | ||
10712 | /* Make sure the new CRTC will work with the encoder */ | |
14509916 TR |
10713 | if (!drm_encoder_crtc_ok(&connector->new_encoder->base, |
10714 | new_crtc)) { | |
5e2b584e | 10715 | return -EINVAL; |
50f56119 | 10716 | } |
9a935856 DV |
10717 | connector->encoder->new_crtc = to_intel_crtc(new_crtc); |
10718 | ||
10719 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", | |
10720 | connector->base.base.id, | |
c23cc417 | 10721 | connector->base.name, |
9a935856 DV |
10722 | new_crtc->base.id); |
10723 | } | |
10724 | ||
10725 | /* Check for any encoders that needs to be disabled. */ | |
10726 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
10727 | base.head) { | |
5a65f358 | 10728 | int num_connectors = 0; |
9a935856 DV |
10729 | list_for_each_entry(connector, |
10730 | &dev->mode_config.connector_list, | |
10731 | base.head) { | |
10732 | if (connector->new_encoder == encoder) { | |
10733 | WARN_ON(!connector->new_encoder->new_crtc); | |
5a65f358 | 10734 | num_connectors++; |
9a935856 DV |
10735 | } |
10736 | } | |
5a65f358 PZ |
10737 | |
10738 | if (num_connectors == 0) | |
10739 | encoder->new_crtc = NULL; | |
10740 | else if (num_connectors > 1) | |
10741 | return -EINVAL; | |
10742 | ||
9a935856 DV |
10743 | /* Only now check for crtc changes so we don't miss encoders |
10744 | * that will be disabled. */ | |
10745 | if (&encoder->new_crtc->base != encoder->base.crtc) { | |
50f56119 | 10746 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
5e2b584e | 10747 | config->mode_changed = true; |
50f56119 DV |
10748 | } |
10749 | } | |
9a935856 | 10750 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
50f56119 | 10751 | |
d3fcc808 | 10752 | for_each_intel_crtc(dev, crtc) { |
7668851f VS |
10753 | crtc->new_enabled = false; |
10754 | ||
10755 | list_for_each_entry(encoder, | |
10756 | &dev->mode_config.encoder_list, | |
10757 | base.head) { | |
10758 | if (encoder->new_crtc == crtc) { | |
10759 | crtc->new_enabled = true; | |
10760 | break; | |
10761 | } | |
10762 | } | |
10763 | ||
10764 | if (crtc->new_enabled != crtc->base.enabled) { | |
10765 | DRM_DEBUG_KMS("crtc %sabled, full mode switch\n", | |
10766 | crtc->new_enabled ? "en" : "dis"); | |
10767 | config->mode_changed = true; | |
10768 | } | |
7bd0a8e7 VS |
10769 | |
10770 | if (crtc->new_enabled) | |
10771 | crtc->new_config = &crtc->config; | |
10772 | else | |
10773 | crtc->new_config = NULL; | |
7668851f VS |
10774 | } |
10775 | ||
2e431051 DV |
10776 | return 0; |
10777 | } | |
10778 | ||
7d00a1f5 VS |
10779 | static void disable_crtc_nofb(struct intel_crtc *crtc) |
10780 | { | |
10781 | struct drm_device *dev = crtc->base.dev; | |
10782 | struct intel_encoder *encoder; | |
10783 | struct intel_connector *connector; | |
10784 | ||
10785 | DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n", | |
10786 | pipe_name(crtc->pipe)); | |
10787 | ||
10788 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { | |
10789 | if (connector->new_encoder && | |
10790 | connector->new_encoder->new_crtc == crtc) | |
10791 | connector->new_encoder = NULL; | |
10792 | } | |
10793 | ||
10794 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { | |
10795 | if (encoder->new_crtc == crtc) | |
10796 | encoder->new_crtc = NULL; | |
10797 | } | |
10798 | ||
10799 | crtc->new_enabled = false; | |
7bd0a8e7 | 10800 | crtc->new_config = NULL; |
7d00a1f5 VS |
10801 | } |
10802 | ||
2e431051 DV |
10803 | static int intel_crtc_set_config(struct drm_mode_set *set) |
10804 | { | |
10805 | struct drm_device *dev; | |
2e431051 DV |
10806 | struct drm_mode_set save_set; |
10807 | struct intel_set_config *config; | |
10808 | int ret; | |
2e431051 | 10809 | |
8d3e375e DV |
10810 | BUG_ON(!set); |
10811 | BUG_ON(!set->crtc); | |
10812 | BUG_ON(!set->crtc->helper_private); | |
2e431051 | 10813 | |
7e53f3a4 DV |
10814 | /* Enforce sane interface api - has been abused by the fb helper. */ |
10815 | BUG_ON(!set->mode && set->fb); | |
10816 | BUG_ON(set->fb && set->num_connectors == 0); | |
431e50f7 | 10817 | |
2e431051 DV |
10818 | if (set->fb) { |
10819 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
10820 | set->crtc->base.id, set->fb->base.id, | |
10821 | (int)set->num_connectors, set->x, set->y); | |
10822 | } else { | |
10823 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
10824 | } |
10825 | ||
10826 | dev = set->crtc->dev; | |
10827 | ||
10828 | ret = -ENOMEM; | |
10829 | config = kzalloc(sizeof(*config), GFP_KERNEL); | |
10830 | if (!config) | |
10831 | goto out_config; | |
10832 | ||
10833 | ret = intel_set_config_save_state(dev, config); | |
10834 | if (ret) | |
10835 | goto out_config; | |
10836 | ||
10837 | save_set.crtc = set->crtc; | |
10838 | save_set.mode = &set->crtc->mode; | |
10839 | save_set.x = set->crtc->x; | |
10840 | save_set.y = set->crtc->y; | |
f4510a27 | 10841 | save_set.fb = set->crtc->primary->fb; |
2e431051 DV |
10842 | |
10843 | /* Compute whether we need a full modeset, only an fb base update or no | |
10844 | * change at all. In the future we might also check whether only the | |
10845 | * mode changed, e.g. for LVDS where we only change the panel fitter in | |
10846 | * such cases. */ | |
10847 | intel_set_config_compute_mode_changes(set, config); | |
10848 | ||
9a935856 | 10849 | ret = intel_modeset_stage_output_state(dev, set, config); |
2e431051 DV |
10850 | if (ret) |
10851 | goto fail; | |
10852 | ||
5e2b584e | 10853 | if (config->mode_changed) { |
c0c36b94 CW |
10854 | ret = intel_set_mode(set->crtc, set->mode, |
10855 | set->x, set->y, set->fb); | |
5e2b584e | 10856 | } else if (config->fb_changed) { |
3b150f08 MR |
10857 | struct drm_i915_private *dev_priv = dev->dev_private; |
10858 | struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc); | |
10859 | ||
4878cae2 VS |
10860 | intel_crtc_wait_for_pending_flips(set->crtc); |
10861 | ||
4f660f49 | 10862 | ret = intel_pipe_set_base(set->crtc, |
94352cf9 | 10863 | set->x, set->y, set->fb); |
3b150f08 MR |
10864 | |
10865 | /* | |
10866 | * We need to make sure the primary plane is re-enabled if it | |
10867 | * has previously been turned off. | |
10868 | */ | |
10869 | if (!intel_crtc->primary_enabled && ret == 0) { | |
10870 | WARN_ON(!intel_crtc->active); | |
10871 | intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane, | |
10872 | intel_crtc->pipe); | |
10873 | } | |
10874 | ||
7ca51a3a JB |
10875 | /* |
10876 | * In the fastboot case this may be our only check of the | |
10877 | * state after boot. It would be better to only do it on | |
10878 | * the first update, but we don't have a nice way of doing that | |
10879 | * (and really, set_config isn't used much for high freq page | |
10880 | * flipping, so increasing its cost here shouldn't be a big | |
10881 | * deal). | |
10882 | */ | |
d330a953 | 10883 | if (i915.fastboot && ret == 0) |
7ca51a3a | 10884 | intel_modeset_check_state(set->crtc->dev); |
50f56119 DV |
10885 | } |
10886 | ||
2d05eae1 | 10887 | if (ret) { |
bf67dfeb DV |
10888 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
10889 | set->crtc->base.id, ret); | |
50f56119 | 10890 | fail: |
2d05eae1 | 10891 | intel_set_config_restore_state(dev, config); |
50f56119 | 10892 | |
7d00a1f5 VS |
10893 | /* |
10894 | * HACK: if the pipe was on, but we didn't have a framebuffer, | |
10895 | * force the pipe off to avoid oopsing in the modeset code | |
10896 | * due to fb==NULL. This should only happen during boot since | |
10897 | * we don't yet reconstruct the FB from the hardware state. | |
10898 | */ | |
10899 | if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb) | |
10900 | disable_crtc_nofb(to_intel_crtc(save_set.crtc)); | |
10901 | ||
2d05eae1 CW |
10902 | /* Try to restore the config */ |
10903 | if (config->mode_changed && | |
10904 | intel_set_mode(save_set.crtc, save_set.mode, | |
10905 | save_set.x, save_set.y, save_set.fb)) | |
10906 | DRM_ERROR("failed to restore config after modeset failure\n"); | |
10907 | } | |
50f56119 | 10908 | |
d9e55608 DV |
10909 | out_config: |
10910 | intel_set_config_free(config); | |
50f56119 DV |
10911 | return ret; |
10912 | } | |
f6e5b160 CW |
10913 | |
10914 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 | 10915 | .gamma_set = intel_crtc_gamma_set, |
50f56119 | 10916 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
10917 | .destroy = intel_crtc_destroy, |
10918 | .page_flip = intel_crtc_page_flip, | |
10919 | }; | |
10920 | ||
79f689aa PZ |
10921 | static void intel_cpu_pll_init(struct drm_device *dev) |
10922 | { | |
affa9354 | 10923 | if (HAS_DDI(dev)) |
79f689aa PZ |
10924 | intel_ddi_pll_init(dev); |
10925 | } | |
10926 | ||
5358901f DV |
10927 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
10928 | struct intel_shared_dpll *pll, | |
10929 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 10930 | { |
5358901f | 10931 | uint32_t val; |
ee7b9f93 | 10932 | |
5358901f | 10933 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
10934 | hw_state->dpll = val; |
10935 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
10936 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
10937 | |
10938 | return val & DPLL_VCO_ENABLE; | |
10939 | } | |
10940 | ||
15bdd4cf DV |
10941 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
10942 | struct intel_shared_dpll *pll) | |
10943 | { | |
10944 | I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0); | |
10945 | I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1); | |
10946 | } | |
10947 | ||
e7b903d2 DV |
10948 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
10949 | struct intel_shared_dpll *pll) | |
10950 | { | |
e7b903d2 | 10951 | /* PCH refclock must be enabled first */ |
89eff4be | 10952 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 10953 | |
15bdd4cf DV |
10954 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); |
10955 | ||
10956 | /* Wait for the clocks to stabilize. */ | |
10957 | POSTING_READ(PCH_DPLL(pll->id)); | |
10958 | udelay(150); | |
10959 | ||
10960 | /* The pixel multiplier can only be updated once the | |
10961 | * DPLL is enabled and the clocks are stable. | |
10962 | * | |
10963 | * So write it again. | |
10964 | */ | |
10965 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); | |
10966 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
10967 | udelay(200); |
10968 | } | |
10969 | ||
10970 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
10971 | struct intel_shared_dpll *pll) | |
10972 | { | |
10973 | struct drm_device *dev = dev_priv->dev; | |
10974 | struct intel_crtc *crtc; | |
e7b903d2 DV |
10975 | |
10976 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 10977 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
10978 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
10979 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
10980 | } |
10981 | ||
15bdd4cf DV |
10982 | I915_WRITE(PCH_DPLL(pll->id), 0); |
10983 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
10984 | udelay(200); |
10985 | } | |
10986 | ||
46edb027 DV |
10987 | static char *ibx_pch_dpll_names[] = { |
10988 | "PCH DPLL A", | |
10989 | "PCH DPLL B", | |
10990 | }; | |
10991 | ||
7c74ade1 | 10992 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 10993 | { |
e7b903d2 | 10994 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
10995 | int i; |
10996 | ||
7c74ade1 | 10997 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 10998 | |
e72f9fbf | 10999 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
11000 | dev_priv->shared_dplls[i].id = i; |
11001 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 11002 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
11003 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
11004 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
11005 | dev_priv->shared_dplls[i].get_hw_state = |
11006 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
11007 | } |
11008 | } | |
11009 | ||
7c74ade1 DV |
11010 | static void intel_shared_dpll_init(struct drm_device *dev) |
11011 | { | |
e7b903d2 | 11012 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 DV |
11013 | |
11014 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
11015 | ibx_pch_dpll_init(dev); | |
11016 | else | |
11017 | dev_priv->num_shared_dpll = 0; | |
11018 | ||
11019 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
11020 | } |
11021 | ||
465c120c MR |
11022 | static int |
11023 | intel_primary_plane_disable(struct drm_plane *plane) | |
11024 | { | |
11025 | struct drm_device *dev = plane->dev; | |
11026 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11027 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
11028 | struct intel_crtc *intel_crtc; | |
11029 | ||
11030 | if (!plane->fb) | |
11031 | return 0; | |
11032 | ||
11033 | BUG_ON(!plane->crtc); | |
11034 | ||
11035 | intel_crtc = to_intel_crtc(plane->crtc); | |
11036 | ||
11037 | /* | |
11038 | * Even though we checked plane->fb above, it's still possible that | |
11039 | * the primary plane has been implicitly disabled because the crtc | |
11040 | * coordinates given weren't visible, or because we detected | |
11041 | * that it was 100% covered by a sprite plane. Or, the CRTC may be | |
11042 | * off and we've set a fb, but haven't actually turned on the CRTC yet. | |
11043 | * In either case, we need to unpin the FB and let the fb pointer get | |
11044 | * updated, but otherwise we don't need to touch the hardware. | |
11045 | */ | |
11046 | if (!intel_crtc->primary_enabled) | |
11047 | goto disable_unpin; | |
11048 | ||
11049 | intel_crtc_wait_for_pending_flips(plane->crtc); | |
11050 | intel_disable_primary_hw_plane(dev_priv, intel_plane->plane, | |
11051 | intel_plane->pipe); | |
11052 | ||
11053 | disable_unpin: | |
11054 | intel_unpin_fb_obj(to_intel_framebuffer(plane->fb)->obj); | |
11055 | plane->fb = NULL; | |
11056 | ||
11057 | return 0; | |
11058 | } | |
11059 | ||
11060 | static int | |
11061 | intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc, | |
11062 | struct drm_framebuffer *fb, int crtc_x, int crtc_y, | |
11063 | unsigned int crtc_w, unsigned int crtc_h, | |
11064 | uint32_t src_x, uint32_t src_y, | |
11065 | uint32_t src_w, uint32_t src_h) | |
11066 | { | |
11067 | struct drm_device *dev = crtc->dev; | |
11068 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11069 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11070 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
11071 | struct drm_rect dest = { | |
11072 | /* integer pixels */ | |
11073 | .x1 = crtc_x, | |
11074 | .y1 = crtc_y, | |
11075 | .x2 = crtc_x + crtc_w, | |
11076 | .y2 = crtc_y + crtc_h, | |
11077 | }; | |
11078 | struct drm_rect src = { | |
11079 | /* 16.16 fixed point */ | |
11080 | .x1 = src_x, | |
11081 | .y1 = src_y, | |
11082 | .x2 = src_x + src_w, | |
11083 | .y2 = src_y + src_h, | |
11084 | }; | |
11085 | const struct drm_rect clip = { | |
11086 | /* integer pixels */ | |
11087 | .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0, | |
11088 | .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0, | |
11089 | }; | |
11090 | bool visible; | |
11091 | int ret; | |
11092 | ||
11093 | ret = drm_plane_helper_check_update(plane, crtc, fb, | |
11094 | &src, &dest, &clip, | |
11095 | DRM_PLANE_HELPER_NO_SCALING, | |
11096 | DRM_PLANE_HELPER_NO_SCALING, | |
11097 | false, true, &visible); | |
11098 | ||
11099 | if (ret) | |
11100 | return ret; | |
11101 | ||
11102 | /* | |
11103 | * If the CRTC isn't enabled, we're just pinning the framebuffer, | |
11104 | * updating the fb pointer, and returning without touching the | |
11105 | * hardware. This allows us to later do a drmModeSetCrtc with fb=-1 to | |
11106 | * turn on the display with all planes setup as desired. | |
11107 | */ | |
11108 | if (!crtc->enabled) { | |
11109 | /* | |
11110 | * If we already called setplane while the crtc was disabled, | |
11111 | * we may have an fb pinned; unpin it. | |
11112 | */ | |
11113 | if (plane->fb) | |
11114 | intel_unpin_fb_obj(to_intel_framebuffer(plane->fb)->obj); | |
11115 | ||
11116 | /* Pin and return without programming hardware */ | |
11117 | return intel_pin_and_fence_fb_obj(dev, | |
11118 | to_intel_framebuffer(fb)->obj, | |
11119 | NULL); | |
11120 | } | |
11121 | ||
11122 | intel_crtc_wait_for_pending_flips(crtc); | |
11123 | ||
11124 | /* | |
11125 | * If clipping results in a non-visible primary plane, we'll disable | |
11126 | * the primary plane. Note that this is a bit different than what | |
11127 | * happens if userspace explicitly disables the plane by passing fb=0 | |
11128 | * because plane->fb still gets set and pinned. | |
11129 | */ | |
11130 | if (!visible) { | |
11131 | /* | |
11132 | * Try to pin the new fb first so that we can bail out if we | |
11133 | * fail. | |
11134 | */ | |
11135 | if (plane->fb != fb) { | |
11136 | ret = intel_pin_and_fence_fb_obj(dev, | |
11137 | to_intel_framebuffer(fb)->obj, | |
11138 | NULL); | |
11139 | if (ret) | |
11140 | return ret; | |
11141 | } | |
11142 | ||
11143 | if (intel_crtc->primary_enabled) | |
11144 | intel_disable_primary_hw_plane(dev_priv, | |
11145 | intel_plane->plane, | |
11146 | intel_plane->pipe); | |
11147 | ||
11148 | ||
11149 | if (plane->fb != fb) | |
11150 | if (plane->fb) | |
11151 | intel_unpin_fb_obj(to_intel_framebuffer(plane->fb)->obj); | |
11152 | ||
11153 | return 0; | |
11154 | } | |
11155 | ||
11156 | ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb); | |
11157 | if (ret) | |
11158 | return ret; | |
11159 | ||
11160 | if (!intel_crtc->primary_enabled) | |
11161 | intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane, | |
11162 | intel_crtc->pipe); | |
11163 | ||
11164 | return 0; | |
11165 | } | |
11166 | ||
3d7d6510 MR |
11167 | /* Common destruction function for both primary and cursor planes */ |
11168 | static void intel_plane_destroy(struct drm_plane *plane) | |
465c120c MR |
11169 | { |
11170 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
11171 | drm_plane_cleanup(plane); | |
11172 | kfree(intel_plane); | |
11173 | } | |
11174 | ||
11175 | static const struct drm_plane_funcs intel_primary_plane_funcs = { | |
11176 | .update_plane = intel_primary_plane_setplane, | |
11177 | .disable_plane = intel_primary_plane_disable, | |
3d7d6510 | 11178 | .destroy = intel_plane_destroy, |
465c120c MR |
11179 | }; |
11180 | ||
11181 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
11182 | int pipe) | |
11183 | { | |
11184 | struct intel_plane *primary; | |
11185 | const uint32_t *intel_primary_formats; | |
11186 | int num_formats; | |
11187 | ||
11188 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
11189 | if (primary == NULL) | |
11190 | return NULL; | |
11191 | ||
11192 | primary->can_scale = false; | |
11193 | primary->max_downscale = 1; | |
11194 | primary->pipe = pipe; | |
11195 | primary->plane = pipe; | |
11196 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) | |
11197 | primary->plane = !pipe; | |
11198 | ||
11199 | if (INTEL_INFO(dev)->gen <= 3) { | |
11200 | intel_primary_formats = intel_primary_formats_gen2; | |
11201 | num_formats = ARRAY_SIZE(intel_primary_formats_gen2); | |
11202 | } else { | |
11203 | intel_primary_formats = intel_primary_formats_gen4; | |
11204 | num_formats = ARRAY_SIZE(intel_primary_formats_gen4); | |
11205 | } | |
11206 | ||
11207 | drm_universal_plane_init(dev, &primary->base, 0, | |
11208 | &intel_primary_plane_funcs, | |
11209 | intel_primary_formats, num_formats, | |
11210 | DRM_PLANE_TYPE_PRIMARY); | |
11211 | return &primary->base; | |
11212 | } | |
11213 | ||
3d7d6510 MR |
11214 | static int |
11215 | intel_cursor_plane_disable(struct drm_plane *plane) | |
11216 | { | |
11217 | if (!plane->fb) | |
11218 | return 0; | |
11219 | ||
11220 | BUG_ON(!plane->crtc); | |
11221 | ||
11222 | return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0); | |
11223 | } | |
11224 | ||
11225 | static int | |
11226 | intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, | |
11227 | struct drm_framebuffer *fb, int crtc_x, int crtc_y, | |
11228 | unsigned int crtc_w, unsigned int crtc_h, | |
11229 | uint32_t src_x, uint32_t src_y, | |
11230 | uint32_t src_w, uint32_t src_h) | |
11231 | { | |
11232 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11233 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
11234 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
11235 | struct drm_rect dest = { | |
11236 | /* integer pixels */ | |
11237 | .x1 = crtc_x, | |
11238 | .y1 = crtc_y, | |
11239 | .x2 = crtc_x + crtc_w, | |
11240 | .y2 = crtc_y + crtc_h, | |
11241 | }; | |
11242 | struct drm_rect src = { | |
11243 | /* 16.16 fixed point */ | |
11244 | .x1 = src_x, | |
11245 | .y1 = src_y, | |
11246 | .x2 = src_x + src_w, | |
11247 | .y2 = src_y + src_h, | |
11248 | }; | |
11249 | const struct drm_rect clip = { | |
11250 | /* integer pixels */ | |
11251 | .x2 = intel_crtc->config.pipe_src_w, | |
11252 | .y2 = intel_crtc->config.pipe_src_h, | |
11253 | }; | |
11254 | bool visible; | |
11255 | int ret; | |
11256 | ||
11257 | ret = drm_plane_helper_check_update(plane, crtc, fb, | |
11258 | &src, &dest, &clip, | |
11259 | DRM_PLANE_HELPER_NO_SCALING, | |
11260 | DRM_PLANE_HELPER_NO_SCALING, | |
11261 | true, true, &visible); | |
11262 | if (ret) | |
11263 | return ret; | |
11264 | ||
11265 | crtc->cursor_x = crtc_x; | |
11266 | crtc->cursor_y = crtc_y; | |
11267 | if (fb != crtc->cursor->fb) { | |
11268 | return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h); | |
11269 | } else { | |
11270 | intel_crtc_update_cursor(crtc, visible); | |
11271 | return 0; | |
11272 | } | |
11273 | } | |
11274 | static const struct drm_plane_funcs intel_cursor_plane_funcs = { | |
11275 | .update_plane = intel_cursor_plane_update, | |
11276 | .disable_plane = intel_cursor_plane_disable, | |
11277 | .destroy = intel_plane_destroy, | |
11278 | }; | |
11279 | ||
11280 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, | |
11281 | int pipe) | |
11282 | { | |
11283 | struct intel_plane *cursor; | |
11284 | ||
11285 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
11286 | if (cursor == NULL) | |
11287 | return NULL; | |
11288 | ||
11289 | cursor->can_scale = false; | |
11290 | cursor->max_downscale = 1; | |
11291 | cursor->pipe = pipe; | |
11292 | cursor->plane = pipe; | |
11293 | ||
11294 | drm_universal_plane_init(dev, &cursor->base, 0, | |
11295 | &intel_cursor_plane_funcs, | |
11296 | intel_cursor_formats, | |
11297 | ARRAY_SIZE(intel_cursor_formats), | |
11298 | DRM_PLANE_TYPE_CURSOR); | |
11299 | return &cursor->base; | |
11300 | } | |
11301 | ||
b358d0a6 | 11302 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 11303 | { |
fbee40df | 11304 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 11305 | struct intel_crtc *intel_crtc; |
3d7d6510 MR |
11306 | struct drm_plane *primary = NULL; |
11307 | struct drm_plane *cursor = NULL; | |
465c120c | 11308 | int i, ret; |
79e53945 | 11309 | |
955382f3 | 11310 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
11311 | if (intel_crtc == NULL) |
11312 | return; | |
11313 | ||
465c120c | 11314 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
11315 | if (!primary) |
11316 | goto fail; | |
11317 | ||
11318 | cursor = intel_cursor_plane_create(dev, pipe); | |
11319 | if (!cursor) | |
11320 | goto fail; | |
11321 | ||
465c120c | 11322 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
3d7d6510 MR |
11323 | cursor, &intel_crtc_funcs); |
11324 | if (ret) | |
11325 | goto fail; | |
79e53945 JB |
11326 | |
11327 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
11328 | for (i = 0; i < 256; i++) { |
11329 | intel_crtc->lut_r[i] = i; | |
11330 | intel_crtc->lut_g[i] = i; | |
11331 | intel_crtc->lut_b[i] = i; | |
11332 | } | |
11333 | ||
1f1c2e24 VS |
11334 | /* |
11335 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
11336 | * is hooked to plane B. Hence we want plane A feeding pipe B. | |
11337 | */ | |
80824003 JB |
11338 | intel_crtc->pipe = pipe; |
11339 | intel_crtc->plane = pipe; | |
3a77c4c4 | 11340 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 11341 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 11342 | intel_crtc->plane = !pipe; |
80824003 JB |
11343 | } |
11344 | ||
4b0e333e CW |
11345 | intel_crtc->cursor_base = ~0; |
11346 | intel_crtc->cursor_cntl = ~0; | |
11347 | ||
8d7849db VS |
11348 | init_waitqueue_head(&intel_crtc->vbl_wait); |
11349 | ||
22fd0fab JB |
11350 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
11351 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
11352 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
11353 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
11354 | ||
79e53945 | 11355 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 DV |
11356 | |
11357 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); | |
3d7d6510 MR |
11358 | return; |
11359 | ||
11360 | fail: | |
11361 | if (primary) | |
11362 | drm_plane_cleanup(primary); | |
11363 | if (cursor) | |
11364 | drm_plane_cleanup(cursor); | |
11365 | kfree(intel_crtc); | |
79e53945 JB |
11366 | } |
11367 | ||
752aa88a JB |
11368 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
11369 | { | |
11370 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 11371 | struct drm_device *dev = connector->base.dev; |
752aa88a | 11372 | |
51fd371b | 11373 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a JB |
11374 | |
11375 | if (!encoder) | |
11376 | return INVALID_PIPE; | |
11377 | ||
11378 | return to_intel_crtc(encoder->crtc)->pipe; | |
11379 | } | |
11380 | ||
08d7b3d1 | 11381 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 11382 | struct drm_file *file) |
08d7b3d1 | 11383 | { |
08d7b3d1 | 11384 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
c05422d5 DV |
11385 | struct drm_mode_object *drmmode_obj; |
11386 | struct intel_crtc *crtc; | |
08d7b3d1 | 11387 | |
1cff8f6b DV |
11388 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
11389 | return -ENODEV; | |
08d7b3d1 | 11390 | |
c05422d5 DV |
11391 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
11392 | DRM_MODE_OBJECT_CRTC); | |
08d7b3d1 | 11393 | |
c05422d5 | 11394 | if (!drmmode_obj) { |
08d7b3d1 | 11395 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 11396 | return -ENOENT; |
08d7b3d1 CW |
11397 | } |
11398 | ||
c05422d5 DV |
11399 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
11400 | pipe_from_crtc_id->pipe = crtc->pipe; | |
08d7b3d1 | 11401 | |
c05422d5 | 11402 | return 0; |
08d7b3d1 CW |
11403 | } |
11404 | ||
66a9278e | 11405 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 11406 | { |
66a9278e DV |
11407 | struct drm_device *dev = encoder->base.dev; |
11408 | struct intel_encoder *source_encoder; | |
79e53945 | 11409 | int index_mask = 0; |
79e53945 JB |
11410 | int entry = 0; |
11411 | ||
66a9278e DV |
11412 | list_for_each_entry(source_encoder, |
11413 | &dev->mode_config.encoder_list, base.head) { | |
bc079e8b | 11414 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
11415 | index_mask |= (1 << entry); |
11416 | ||
79e53945 JB |
11417 | entry++; |
11418 | } | |
4ef69c7a | 11419 | |
79e53945 JB |
11420 | return index_mask; |
11421 | } | |
11422 | ||
4d302442 CW |
11423 | static bool has_edp_a(struct drm_device *dev) |
11424 | { | |
11425 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11426 | ||
11427 | if (!IS_MOBILE(dev)) | |
11428 | return false; | |
11429 | ||
11430 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
11431 | return false; | |
11432 | ||
e3589908 | 11433 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
11434 | return false; |
11435 | ||
11436 | return true; | |
11437 | } | |
11438 | ||
ba0fbca4 DL |
11439 | const char *intel_output_name(int output) |
11440 | { | |
11441 | static const char *names[] = { | |
11442 | [INTEL_OUTPUT_UNUSED] = "Unused", | |
11443 | [INTEL_OUTPUT_ANALOG] = "Analog", | |
11444 | [INTEL_OUTPUT_DVO] = "DVO", | |
11445 | [INTEL_OUTPUT_SDVO] = "SDVO", | |
11446 | [INTEL_OUTPUT_LVDS] = "LVDS", | |
11447 | [INTEL_OUTPUT_TVOUT] = "TV", | |
11448 | [INTEL_OUTPUT_HDMI] = "HDMI", | |
11449 | [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort", | |
11450 | [INTEL_OUTPUT_EDP] = "eDP", | |
11451 | [INTEL_OUTPUT_DSI] = "DSI", | |
11452 | [INTEL_OUTPUT_UNKNOWN] = "Unknown", | |
11453 | }; | |
11454 | ||
11455 | if (output < 0 || output >= ARRAY_SIZE(names) || !names[output]) | |
11456 | return "Invalid"; | |
11457 | ||
11458 | return names[output]; | |
11459 | } | |
11460 | ||
79e53945 JB |
11461 | static void intel_setup_outputs(struct drm_device *dev) |
11462 | { | |
725e30ad | 11463 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 11464 | struct intel_encoder *encoder; |
cb0953d7 | 11465 | bool dpd_is_edp = false; |
79e53945 | 11466 | |
c9093354 | 11467 | intel_lvds_init(dev); |
79e53945 | 11468 | |
27da3bdf | 11469 | if (!IS_ULT(dev) && !IS_CHERRYVIEW(dev) && dev_priv->vbt.int_crt_support) |
79935fca | 11470 | intel_crt_init(dev); |
cb0953d7 | 11471 | |
affa9354 | 11472 | if (HAS_DDI(dev)) { |
0e72a5b5 ED |
11473 | int found; |
11474 | ||
11475 | /* Haswell uses DDI functions to detect digital outputs */ | |
11476 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; | |
11477 | /* DDI A only supports eDP */ | |
11478 | if (found) | |
11479 | intel_ddi_init(dev, PORT_A); | |
11480 | ||
11481 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
11482 | * register */ | |
11483 | found = I915_READ(SFUSE_STRAP); | |
11484 | ||
11485 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
11486 | intel_ddi_init(dev, PORT_B); | |
11487 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
11488 | intel_ddi_init(dev, PORT_C); | |
11489 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
11490 | intel_ddi_init(dev, PORT_D); | |
11491 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 11492 | int found; |
5d8a7752 | 11493 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
11494 | |
11495 | if (has_edp_a(dev)) | |
11496 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 11497 | |
dc0fa718 | 11498 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 11499 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 11500 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 11501 | if (!found) |
e2debe91 | 11502 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 11503 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 11504 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
11505 | } |
11506 | ||
dc0fa718 | 11507 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 11508 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 11509 | |
dc0fa718 | 11510 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 11511 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 11512 | |
5eb08b69 | 11513 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 11514 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 11515 | |
270b3042 | 11516 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 11517 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 11518 | } else if (IS_VALLEYVIEW(dev)) { |
585a94b8 AB |
11519 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) { |
11520 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, | |
11521 | PORT_B); | |
11522 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED) | |
11523 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
11524 | } | |
11525 | ||
6f6005a5 JB |
11526 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) { |
11527 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, | |
11528 | PORT_C); | |
11529 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) | |
5d8a7752 | 11530 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); |
6f6005a5 | 11531 | } |
19c03924 | 11532 | |
9418c1f1 VS |
11533 | if (IS_CHERRYVIEW(dev)) { |
11534 | if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) { | |
11535 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID, | |
11536 | PORT_D); | |
11537 | if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED) | |
11538 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D); | |
11539 | } | |
11540 | } | |
11541 | ||
3cfca973 | 11542 | intel_dsi_init(dev); |
103a196f | 11543 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 11544 | bool found = false; |
7d57382e | 11545 | |
e2debe91 | 11546 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 11547 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 11548 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
b01f2c3a JB |
11549 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
11550 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
e2debe91 | 11551 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 11552 | } |
27185ae1 | 11553 | |
e7281eab | 11554 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 11555 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 11556 | } |
13520b05 KH |
11557 | |
11558 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 11559 | |
e2debe91 | 11560 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 11561 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 11562 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 11563 | } |
27185ae1 | 11564 | |
e2debe91 | 11565 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 11566 | |
b01f2c3a JB |
11567 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
11568 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
e2debe91 | 11569 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 11570 | } |
e7281eab | 11571 | if (SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 11572 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 11573 | } |
27185ae1 | 11574 | |
b01f2c3a | 11575 | if (SUPPORTS_INTEGRATED_DP(dev) && |
e7281eab | 11576 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 11577 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 11578 | } else if (IS_GEN2(dev)) |
79e53945 JB |
11579 | intel_dvo_init(dev); |
11580 | ||
103a196f | 11581 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
11582 | intel_tv_init(dev); |
11583 | ||
4ef69c7a CW |
11584 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
11585 | encoder->base.possible_crtcs = encoder->crtc_mask; | |
11586 | encoder->base.possible_clones = | |
66a9278e | 11587 | intel_encoder_clones(encoder); |
79e53945 | 11588 | } |
47356eb6 | 11589 | |
dde86e2d | 11590 | intel_init_pch_refclk(dev); |
270b3042 DV |
11591 | |
11592 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
11593 | } |
11594 | ||
11595 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
11596 | { | |
60a5ca01 | 11597 | struct drm_device *dev = fb->dev; |
79e53945 | 11598 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 11599 | |
ef2d633e | 11600 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 11601 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 11602 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
11603 | drm_gem_object_unreference(&intel_fb->obj->base); |
11604 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
11605 | kfree(intel_fb); |
11606 | } | |
11607 | ||
11608 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 11609 | struct drm_file *file, |
79e53945 JB |
11610 | unsigned int *handle) |
11611 | { | |
11612 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 11613 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 11614 | |
05394f39 | 11615 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
11616 | } |
11617 | ||
11618 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
11619 | .destroy = intel_user_framebuffer_destroy, | |
11620 | .create_handle = intel_user_framebuffer_create_handle, | |
11621 | }; | |
11622 | ||
b5ea642a DV |
11623 | static int intel_framebuffer_init(struct drm_device *dev, |
11624 | struct intel_framebuffer *intel_fb, | |
11625 | struct drm_mode_fb_cmd2 *mode_cmd, | |
11626 | struct drm_i915_gem_object *obj) | |
79e53945 | 11627 | { |
a57ce0b2 | 11628 | int aligned_height; |
a35cdaa0 | 11629 | int pitch_limit; |
79e53945 JB |
11630 | int ret; |
11631 | ||
dd4916c5 DV |
11632 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
11633 | ||
c16ed4be CW |
11634 | if (obj->tiling_mode == I915_TILING_Y) { |
11635 | DRM_DEBUG("hardware does not support tiling Y\n"); | |
57cd6508 | 11636 | return -EINVAL; |
c16ed4be | 11637 | } |
57cd6508 | 11638 | |
c16ed4be CW |
11639 | if (mode_cmd->pitches[0] & 63) { |
11640 | DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n", | |
11641 | mode_cmd->pitches[0]); | |
57cd6508 | 11642 | return -EINVAL; |
c16ed4be | 11643 | } |
57cd6508 | 11644 | |
a35cdaa0 CW |
11645 | if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) { |
11646 | pitch_limit = 32*1024; | |
11647 | } else if (INTEL_INFO(dev)->gen >= 4) { | |
11648 | if (obj->tiling_mode) | |
11649 | pitch_limit = 16*1024; | |
11650 | else | |
11651 | pitch_limit = 32*1024; | |
11652 | } else if (INTEL_INFO(dev)->gen >= 3) { | |
11653 | if (obj->tiling_mode) | |
11654 | pitch_limit = 8*1024; | |
11655 | else | |
11656 | pitch_limit = 16*1024; | |
11657 | } else | |
11658 | /* XXX DSPC is limited to 4k tiled */ | |
11659 | pitch_limit = 8*1024; | |
11660 | ||
11661 | if (mode_cmd->pitches[0] > pitch_limit) { | |
11662 | DRM_DEBUG("%s pitch (%d) must be at less than %d\n", | |
11663 | obj->tiling_mode ? "tiled" : "linear", | |
11664 | mode_cmd->pitches[0], pitch_limit); | |
5d7bd705 | 11665 | return -EINVAL; |
c16ed4be | 11666 | } |
5d7bd705 VS |
11667 | |
11668 | if (obj->tiling_mode != I915_TILING_NONE && | |
c16ed4be CW |
11669 | mode_cmd->pitches[0] != obj->stride) { |
11670 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
11671 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 11672 | return -EINVAL; |
c16ed4be | 11673 | } |
5d7bd705 | 11674 | |
57779d06 | 11675 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 11676 | switch (mode_cmd->pixel_format) { |
57779d06 | 11677 | case DRM_FORMAT_C8: |
04b3924d VS |
11678 | case DRM_FORMAT_RGB565: |
11679 | case DRM_FORMAT_XRGB8888: | |
11680 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
11681 | break; |
11682 | case DRM_FORMAT_XRGB1555: | |
11683 | case DRM_FORMAT_ARGB1555: | |
c16ed4be | 11684 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
11685 | DRM_DEBUG("unsupported pixel format: %s\n", |
11686 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 11687 | return -EINVAL; |
c16ed4be | 11688 | } |
57779d06 VS |
11689 | break; |
11690 | case DRM_FORMAT_XBGR8888: | |
11691 | case DRM_FORMAT_ABGR8888: | |
04b3924d VS |
11692 | case DRM_FORMAT_XRGB2101010: |
11693 | case DRM_FORMAT_ARGB2101010: | |
57779d06 VS |
11694 | case DRM_FORMAT_XBGR2101010: |
11695 | case DRM_FORMAT_ABGR2101010: | |
c16ed4be | 11696 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
11697 | DRM_DEBUG("unsupported pixel format: %s\n", |
11698 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 11699 | return -EINVAL; |
c16ed4be | 11700 | } |
b5626747 | 11701 | break; |
04b3924d VS |
11702 | case DRM_FORMAT_YUYV: |
11703 | case DRM_FORMAT_UYVY: | |
11704 | case DRM_FORMAT_YVYU: | |
11705 | case DRM_FORMAT_VYUY: | |
c16ed4be | 11706 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
11707 | DRM_DEBUG("unsupported pixel format: %s\n", |
11708 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 11709 | return -EINVAL; |
c16ed4be | 11710 | } |
57cd6508 CW |
11711 | break; |
11712 | default: | |
4ee62c76 VS |
11713 | DRM_DEBUG("unsupported pixel format: %s\n", |
11714 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
11715 | return -EINVAL; |
11716 | } | |
11717 | ||
90f9a336 VS |
11718 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
11719 | if (mode_cmd->offsets[0] != 0) | |
11720 | return -EINVAL; | |
11721 | ||
a57ce0b2 JB |
11722 | aligned_height = intel_align_height(dev, mode_cmd->height, |
11723 | obj->tiling_mode); | |
53155c0a DV |
11724 | /* FIXME drm helper for size checks (especially planar formats)? */ |
11725 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
11726 | return -EINVAL; | |
11727 | ||
c7d73f6a DV |
11728 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
11729 | intel_fb->obj = obj; | |
80075d49 | 11730 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 11731 | |
79e53945 JB |
11732 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
11733 | if (ret) { | |
11734 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
11735 | return ret; | |
11736 | } | |
11737 | ||
79e53945 JB |
11738 | return 0; |
11739 | } | |
11740 | ||
79e53945 JB |
11741 | static struct drm_framebuffer * |
11742 | intel_user_framebuffer_create(struct drm_device *dev, | |
11743 | struct drm_file *filp, | |
308e5bcb | 11744 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 11745 | { |
05394f39 | 11746 | struct drm_i915_gem_object *obj; |
79e53945 | 11747 | |
308e5bcb JB |
11748 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
11749 | mode_cmd->handles[0])); | |
c8725226 | 11750 | if (&obj->base == NULL) |
cce13ff7 | 11751 | return ERR_PTR(-ENOENT); |
79e53945 | 11752 | |
d2dff872 | 11753 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
11754 | } |
11755 | ||
4520f53a | 11756 | #ifndef CONFIG_DRM_I915_FBDEV |
0632fef6 | 11757 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
11758 | { |
11759 | } | |
11760 | #endif | |
11761 | ||
79e53945 | 11762 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 11763 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 11764 | .output_poll_changed = intel_fbdev_output_poll_changed, |
79e53945 JB |
11765 | }; |
11766 | ||
e70236a8 JB |
11767 | /* Set up chip specific display functions */ |
11768 | static void intel_init_display(struct drm_device *dev) | |
11769 | { | |
11770 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11771 | ||
ee9300bb DV |
11772 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
11773 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
11774 | else if (IS_CHERRYVIEW(dev)) |
11775 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
11776 | else if (IS_VALLEYVIEW(dev)) |
11777 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
11778 | else if (IS_PINEVIEW(dev)) | |
11779 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
11780 | else | |
11781 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
11782 | ||
affa9354 | 11783 | if (HAS_DDI(dev)) { |
0e8ffe1b | 11784 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
4c6baa59 | 11785 | dev_priv->display.get_plane_config = ironlake_get_plane_config; |
09b4ddf9 | 11786 | dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; |
4f771f10 PZ |
11787 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
11788 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
6441ab5f | 11789 | dev_priv->display.off = haswell_crtc_off; |
262ca2b0 MR |
11790 | dev_priv->display.update_primary_plane = |
11791 | ironlake_update_primary_plane; | |
09b4ddf9 | 11792 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 11793 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
4c6baa59 | 11794 | dev_priv->display.get_plane_config = ironlake_get_plane_config; |
f564048e | 11795 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
76e5a89c DV |
11796 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
11797 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
ee7b9f93 | 11798 | dev_priv->display.off = ironlake_crtc_off; |
262ca2b0 MR |
11799 | dev_priv->display.update_primary_plane = |
11800 | ironlake_update_primary_plane; | |
89b667f8 JB |
11801 | } else if (IS_VALLEYVIEW(dev)) { |
11802 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
1ad292b5 | 11803 | dev_priv->display.get_plane_config = i9xx_get_plane_config; |
89b667f8 JB |
11804 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
11805 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
11806 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
11807 | dev_priv->display.off = i9xx_crtc_off; | |
262ca2b0 MR |
11808 | dev_priv->display.update_primary_plane = |
11809 | i9xx_update_primary_plane; | |
f564048e | 11810 | } else { |
0e8ffe1b | 11811 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
1ad292b5 | 11812 | dev_priv->display.get_plane_config = i9xx_get_plane_config; |
f564048e | 11813 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
76e5a89c DV |
11814 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
11815 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
ee7b9f93 | 11816 | dev_priv->display.off = i9xx_crtc_off; |
262ca2b0 MR |
11817 | dev_priv->display.update_primary_plane = |
11818 | i9xx_update_primary_plane; | |
f564048e | 11819 | } |
e70236a8 | 11820 | |
e70236a8 | 11821 | /* Returns the core display clock speed */ |
25eb05fc JB |
11822 | if (IS_VALLEYVIEW(dev)) |
11823 | dev_priv->display.get_display_clock_speed = | |
11824 | valleyview_get_display_clock_speed; | |
11825 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
11826 | dev_priv->display.get_display_clock_speed = |
11827 | i945_get_display_clock_speed; | |
11828 | else if (IS_I915G(dev)) | |
11829 | dev_priv->display.get_display_clock_speed = | |
11830 | i915_get_display_clock_speed; | |
257a7ffc | 11831 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
11832 | dev_priv->display.get_display_clock_speed = |
11833 | i9xx_misc_get_display_clock_speed; | |
257a7ffc DV |
11834 | else if (IS_PINEVIEW(dev)) |
11835 | dev_priv->display.get_display_clock_speed = | |
11836 | pnv_get_display_clock_speed; | |
e70236a8 JB |
11837 | else if (IS_I915GM(dev)) |
11838 | dev_priv->display.get_display_clock_speed = | |
11839 | i915gm_get_display_clock_speed; | |
11840 | else if (IS_I865G(dev)) | |
11841 | dev_priv->display.get_display_clock_speed = | |
11842 | i865_get_display_clock_speed; | |
f0f8a9ce | 11843 | else if (IS_I85X(dev)) |
e70236a8 JB |
11844 | dev_priv->display.get_display_clock_speed = |
11845 | i855_get_display_clock_speed; | |
11846 | else /* 852, 830 */ | |
11847 | dev_priv->display.get_display_clock_speed = | |
11848 | i830_get_display_clock_speed; | |
11849 | ||
7f8a8569 | 11850 | if (HAS_PCH_SPLIT(dev)) { |
f00a3ddf | 11851 | if (IS_GEN5(dev)) { |
674cf967 | 11852 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
e0dac65e | 11853 | dev_priv->display.write_eld = ironlake_write_eld; |
1398261a | 11854 | } else if (IS_GEN6(dev)) { |
674cf967 | 11855 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
e0dac65e | 11856 | dev_priv->display.write_eld = ironlake_write_eld; |
9a952a0d PZ |
11857 | dev_priv->display.modeset_global_resources = |
11858 | snb_modeset_global_resources; | |
357555c0 JB |
11859 | } else if (IS_IVYBRIDGE(dev)) { |
11860 | /* FIXME: detect B0+ stepping and use auto training */ | |
11861 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
e0dac65e | 11862 | dev_priv->display.write_eld = ironlake_write_eld; |
01a415fd DV |
11863 | dev_priv->display.modeset_global_resources = |
11864 | ivb_modeset_global_resources; | |
4e0bbc31 | 11865 | } else if (IS_HASWELL(dev) || IS_GEN8(dev)) { |
c82e4d26 | 11866 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
83358c85 | 11867 | dev_priv->display.write_eld = haswell_write_eld; |
d6dd9eb1 DV |
11868 | dev_priv->display.modeset_global_resources = |
11869 | haswell_modeset_global_resources; | |
a0e63c22 | 11870 | } |
6067aaea | 11871 | } else if (IS_G4X(dev)) { |
e0dac65e | 11872 | dev_priv->display.write_eld = g4x_write_eld; |
30a970c6 JB |
11873 | } else if (IS_VALLEYVIEW(dev)) { |
11874 | dev_priv->display.modeset_global_resources = | |
11875 | valleyview_modeset_global_resources; | |
9ca2fe73 | 11876 | dev_priv->display.write_eld = ironlake_write_eld; |
e70236a8 | 11877 | } |
8c9f3aaf JB |
11878 | |
11879 | /* Default just returns -ENODEV to indicate unsupported */ | |
11880 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
11881 | ||
11882 | switch (INTEL_INFO(dev)->gen) { | |
11883 | case 2: | |
11884 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
11885 | break; | |
11886 | ||
11887 | case 3: | |
11888 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
11889 | break; | |
11890 | ||
11891 | case 4: | |
11892 | case 5: | |
11893 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
11894 | break; | |
11895 | ||
11896 | case 6: | |
11897 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
11898 | break; | |
7c9017e5 | 11899 | case 7: |
4e0bbc31 | 11900 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
11901 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
11902 | break; | |
8c9f3aaf | 11903 | } |
7bd688cd JN |
11904 | |
11905 | intel_panel_init_backlight_funcs(dev); | |
e70236a8 JB |
11906 | } |
11907 | ||
b690e96c JB |
11908 | /* |
11909 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
11910 | * resume, or other times. This quirk makes sure that's the case for | |
11911 | * affected systems. | |
11912 | */ | |
0206e353 | 11913 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
11914 | { |
11915 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11916 | ||
11917 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 11918 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
11919 | } |
11920 | ||
435793df KP |
11921 | /* |
11922 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
11923 | */ | |
11924 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
11925 | { | |
11926 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11927 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 11928 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
11929 | } |
11930 | ||
4dca20ef | 11931 | /* |
5a15ab5b CE |
11932 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
11933 | * brightness value | |
4dca20ef CE |
11934 | */ |
11935 | static void quirk_invert_brightness(struct drm_device *dev) | |
11936 | { | |
11937 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11938 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 11939 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
11940 | } |
11941 | ||
b690e96c JB |
11942 | struct intel_quirk { |
11943 | int device; | |
11944 | int subsystem_vendor; | |
11945 | int subsystem_device; | |
11946 | void (*hook)(struct drm_device *dev); | |
11947 | }; | |
11948 | ||
5f85f176 EE |
11949 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
11950 | struct intel_dmi_quirk { | |
11951 | void (*hook)(struct drm_device *dev); | |
11952 | const struct dmi_system_id (*dmi_id_list)[]; | |
11953 | }; | |
11954 | ||
11955 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
11956 | { | |
11957 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
11958 | return 1; | |
11959 | } | |
11960 | ||
11961 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
11962 | { | |
11963 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
11964 | { | |
11965 | .callback = intel_dmi_reverse_brightness, | |
11966 | .ident = "NCR Corporation", | |
11967 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
11968 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
11969 | }, | |
11970 | }, | |
11971 | { } /* terminating entry */ | |
11972 | }, | |
11973 | .hook = quirk_invert_brightness, | |
11974 | }, | |
11975 | }; | |
11976 | ||
c43b5634 | 11977 | static struct intel_quirk intel_quirks[] = { |
b690e96c | 11978 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 11979 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c | 11980 | |
b690e96c JB |
11981 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
11982 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
11983 | ||
b690e96c JB |
11984 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
11985 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
11986 | ||
435793df KP |
11987 | /* Lenovo U160 cannot use SSC on LVDS */ |
11988 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
11989 | |
11990 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
11991 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 11992 | |
be505f64 AH |
11993 | /* Acer Aspire 5734Z must invert backlight brightness */ |
11994 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
11995 | ||
11996 | /* Acer/eMachines G725 */ | |
11997 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
11998 | ||
11999 | /* Acer/eMachines e725 */ | |
12000 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
12001 | ||
12002 | /* Acer/Packard Bell NCL20 */ | |
12003 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
12004 | ||
12005 | /* Acer Aspire 4736Z */ | |
12006 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
12007 | |
12008 | /* Acer Aspire 5336 */ | |
12009 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
b690e96c JB |
12010 | }; |
12011 | ||
12012 | static void intel_init_quirks(struct drm_device *dev) | |
12013 | { | |
12014 | struct pci_dev *d = dev->pdev; | |
12015 | int i; | |
12016 | ||
12017 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
12018 | struct intel_quirk *q = &intel_quirks[i]; | |
12019 | ||
12020 | if (d->device == q->device && | |
12021 | (d->subsystem_vendor == q->subsystem_vendor || | |
12022 | q->subsystem_vendor == PCI_ANY_ID) && | |
12023 | (d->subsystem_device == q->subsystem_device || | |
12024 | q->subsystem_device == PCI_ANY_ID)) | |
12025 | q->hook(dev); | |
12026 | } | |
5f85f176 EE |
12027 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
12028 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
12029 | intel_dmi_quirks[i].hook(dev); | |
12030 | } | |
b690e96c JB |
12031 | } |
12032 | ||
9cce37f4 JB |
12033 | /* Disable the VGA plane that we never use */ |
12034 | static void i915_disable_vga(struct drm_device *dev) | |
12035 | { | |
12036 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12037 | u8 sr1; | |
766aa1c4 | 12038 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 12039 | |
2b37c616 | 12040 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 12041 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 12042 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
12043 | sr1 = inb(VGA_SR_DATA); |
12044 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
12045 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
12046 | udelay(300); | |
12047 | ||
12048 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); | |
12049 | POSTING_READ(vga_reg); | |
12050 | } | |
12051 | ||
f817586c DV |
12052 | void intel_modeset_init_hw(struct drm_device *dev) |
12053 | { | |
a8f78b58 ED |
12054 | intel_prepare_ddi(dev); |
12055 | ||
f817586c DV |
12056 | intel_init_clock_gating(dev); |
12057 | ||
5382f5f3 | 12058 | intel_reset_dpio(dev); |
40e9cf64 | 12059 | |
8090c6b9 | 12060 | intel_enable_gt_powersave(dev); |
f817586c DV |
12061 | } |
12062 | ||
7d708ee4 ID |
12063 | void intel_modeset_suspend_hw(struct drm_device *dev) |
12064 | { | |
12065 | intel_suspend_hw(dev); | |
12066 | } | |
12067 | ||
79e53945 JB |
12068 | void intel_modeset_init(struct drm_device *dev) |
12069 | { | |
652c393a | 12070 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 12071 | int sprite, ret; |
8cc87b75 | 12072 | enum pipe pipe; |
46f297fb | 12073 | struct intel_crtc *crtc; |
79e53945 JB |
12074 | |
12075 | drm_mode_config_init(dev); | |
12076 | ||
12077 | dev->mode_config.min_width = 0; | |
12078 | dev->mode_config.min_height = 0; | |
12079 | ||
019d96cb DA |
12080 | dev->mode_config.preferred_depth = 24; |
12081 | dev->mode_config.prefer_shadow = 1; | |
12082 | ||
e6ecefaa | 12083 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 12084 | |
b690e96c JB |
12085 | intel_init_quirks(dev); |
12086 | ||
1fa61106 ED |
12087 | intel_init_pm(dev); |
12088 | ||
e3c74757 BW |
12089 | if (INTEL_INFO(dev)->num_pipes == 0) |
12090 | return; | |
12091 | ||
e70236a8 JB |
12092 | intel_init_display(dev); |
12093 | ||
a6c45cf0 CW |
12094 | if (IS_GEN2(dev)) { |
12095 | dev->mode_config.max_width = 2048; | |
12096 | dev->mode_config.max_height = 2048; | |
12097 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
12098 | dev->mode_config.max_width = 4096; |
12099 | dev->mode_config.max_height = 4096; | |
79e53945 | 12100 | } else { |
a6c45cf0 CW |
12101 | dev->mode_config.max_width = 8192; |
12102 | dev->mode_config.max_height = 8192; | |
79e53945 | 12103 | } |
068be561 DL |
12104 | |
12105 | if (IS_GEN2(dev)) { | |
12106 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; | |
12107 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
12108 | } else { | |
12109 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
12110 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
12111 | } | |
12112 | ||
5d4545ae | 12113 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 12114 | |
28c97730 | 12115 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
12116 | INTEL_INFO(dev)->num_pipes, |
12117 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 12118 | |
8cc87b75 DL |
12119 | for_each_pipe(pipe) { |
12120 | intel_crtc_init(dev, pipe); | |
1fe47785 DL |
12121 | for_each_sprite(pipe, sprite) { |
12122 | ret = intel_plane_init(dev, pipe, sprite); | |
7f1f3851 | 12123 | if (ret) |
06da8da2 | 12124 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 12125 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 12126 | } |
79e53945 JB |
12127 | } |
12128 | ||
f42bb70d | 12129 | intel_init_dpio(dev); |
5382f5f3 | 12130 | intel_reset_dpio(dev); |
f42bb70d | 12131 | |
79f689aa | 12132 | intel_cpu_pll_init(dev); |
e72f9fbf | 12133 | intel_shared_dpll_init(dev); |
ee7b9f93 | 12134 | |
9cce37f4 JB |
12135 | /* Just disable it once at startup */ |
12136 | i915_disable_vga(dev); | |
79e53945 | 12137 | intel_setup_outputs(dev); |
11be49eb CW |
12138 | |
12139 | /* Just in case the BIOS is doing something questionable. */ | |
12140 | intel_disable_fbc(dev); | |
fa9fa083 | 12141 | |
6e9f798d | 12142 | drm_modeset_lock_all(dev); |
fa9fa083 | 12143 | intel_modeset_setup_hw_state(dev, false); |
6e9f798d | 12144 | drm_modeset_unlock_all(dev); |
46f297fb | 12145 | |
d3fcc808 | 12146 | for_each_intel_crtc(dev, crtc) { |
46f297fb JB |
12147 | if (!crtc->active) |
12148 | continue; | |
12149 | ||
46f297fb | 12150 | /* |
46f297fb JB |
12151 | * Note that reserving the BIOS fb up front prevents us |
12152 | * from stuffing other stolen allocations like the ring | |
12153 | * on top. This prevents some ugliness at boot time, and | |
12154 | * can even allow for smooth boot transitions if the BIOS | |
12155 | * fb is large enough for the active pipe configuration. | |
12156 | */ | |
12157 | if (dev_priv->display.get_plane_config) { | |
12158 | dev_priv->display.get_plane_config(crtc, | |
12159 | &crtc->plane_config); | |
12160 | /* | |
12161 | * If the fb is shared between multiple heads, we'll | |
12162 | * just get the first one. | |
12163 | */ | |
484b41dd | 12164 | intel_find_plane_obj(crtc, &crtc->plane_config); |
46f297fb | 12165 | } |
46f297fb | 12166 | } |
2c7111db CW |
12167 | } |
12168 | ||
7fad798e DV |
12169 | static void intel_enable_pipe_a(struct drm_device *dev) |
12170 | { | |
12171 | struct intel_connector *connector; | |
12172 | struct drm_connector *crt = NULL; | |
12173 | struct intel_load_detect_pipe load_detect_temp; | |
51fd371b | 12174 | struct drm_modeset_acquire_ctx ctx; |
7fad798e DV |
12175 | |
12176 | /* We can't just switch on the pipe A, we need to set things up with a | |
12177 | * proper mode and output configuration. As a gross hack, enable pipe A | |
12178 | * by enabling the load detect pipe once. */ | |
12179 | list_for_each_entry(connector, | |
12180 | &dev->mode_config.connector_list, | |
12181 | base.head) { | |
12182 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { | |
12183 | crt = &connector->base; | |
12184 | break; | |
12185 | } | |
12186 | } | |
12187 | ||
12188 | if (!crt) | |
12189 | return; | |
12190 | ||
51fd371b RC |
12191 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, &ctx)) |
12192 | intel_release_load_detect_pipe(crt, &load_detect_temp, &ctx); | |
7fad798e | 12193 | |
652c393a | 12194 | |
7fad798e DV |
12195 | } |
12196 | ||
fa555837 DV |
12197 | static bool |
12198 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
12199 | { | |
7eb552ae BW |
12200 | struct drm_device *dev = crtc->base.dev; |
12201 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
12202 | u32 reg, val; |
12203 | ||
7eb552ae | 12204 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
12205 | return true; |
12206 | ||
12207 | reg = DSPCNTR(!crtc->plane); | |
12208 | val = I915_READ(reg); | |
12209 | ||
12210 | if ((val & DISPLAY_PLANE_ENABLE) && | |
12211 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
12212 | return false; | |
12213 | ||
12214 | return true; | |
12215 | } | |
12216 | ||
24929352 DV |
12217 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
12218 | { | |
12219 | struct drm_device *dev = crtc->base.dev; | |
12220 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 12221 | u32 reg; |
24929352 | 12222 | |
24929352 | 12223 | /* Clear any frame start delays used for debugging left by the BIOS */ |
3b117c8f | 12224 | reg = PIPECONF(crtc->config.cpu_transcoder); |
24929352 DV |
12225 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
12226 | ||
d3eaf884 VS |
12227 | /* restore vblank interrupts to correct state */ |
12228 | if (crtc->active) | |
12229 | drm_vblank_on(dev, crtc->pipe); | |
12230 | else | |
12231 | drm_vblank_off(dev, crtc->pipe); | |
12232 | ||
24929352 | 12233 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
12234 | * disable the crtc (and hence change the state) if it is wrong. Note |
12235 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
12236 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
12237 | struct intel_connector *connector; |
12238 | bool plane; | |
12239 | ||
24929352 DV |
12240 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
12241 | crtc->base.base.id); | |
12242 | ||
12243 | /* Pipe has the wrong plane attached and the plane is active. | |
12244 | * Temporarily change the plane mapping and disable everything | |
12245 | * ... */ | |
12246 | plane = crtc->plane; | |
12247 | crtc->plane = !plane; | |
12248 | dev_priv->display.crtc_disable(&crtc->base); | |
12249 | crtc->plane = plane; | |
12250 | ||
12251 | /* ... and break all links. */ | |
12252 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
12253 | base.head) { | |
12254 | if (connector->encoder->base.crtc != &crtc->base) | |
12255 | continue; | |
12256 | ||
7f1950fb EE |
12257 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
12258 | connector->base.encoder = NULL; | |
24929352 | 12259 | } |
7f1950fb EE |
12260 | /* multiple connectors may have the same encoder: |
12261 | * handle them and break crtc link separately */ | |
12262 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
12263 | base.head) | |
12264 | if (connector->encoder->base.crtc == &crtc->base) { | |
12265 | connector->encoder->base.crtc = NULL; | |
12266 | connector->encoder->connectors_active = false; | |
12267 | } | |
24929352 DV |
12268 | |
12269 | WARN_ON(crtc->active); | |
12270 | crtc->base.enabled = false; | |
12271 | } | |
24929352 | 12272 | |
7fad798e DV |
12273 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
12274 | crtc->pipe == PIPE_A && !crtc->active) { | |
12275 | /* BIOS forgot to enable pipe A, this mostly happens after | |
12276 | * resume. Force-enable the pipe to fix this, the update_dpms | |
12277 | * call below we restore the pipe to the right state, but leave | |
12278 | * the required bits on. */ | |
12279 | intel_enable_pipe_a(dev); | |
12280 | } | |
12281 | ||
24929352 DV |
12282 | /* Adjust the state of the output pipe according to whether we |
12283 | * have active connectors/encoders. */ | |
12284 | intel_crtc_update_dpms(&crtc->base); | |
12285 | ||
12286 | if (crtc->active != crtc->base.enabled) { | |
12287 | struct intel_encoder *encoder; | |
12288 | ||
12289 | /* This can happen either due to bugs in the get_hw_state | |
12290 | * functions or because the pipe is force-enabled due to the | |
12291 | * pipe A quirk. */ | |
12292 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
12293 | crtc->base.base.id, | |
12294 | crtc->base.enabled ? "enabled" : "disabled", | |
12295 | crtc->active ? "enabled" : "disabled"); | |
12296 | ||
12297 | crtc->base.enabled = crtc->active; | |
12298 | ||
12299 | /* Because we only establish the connector -> encoder -> | |
12300 | * crtc links if something is active, this means the | |
12301 | * crtc is now deactivated. Break the links. connector | |
12302 | * -> encoder links are only establish when things are | |
12303 | * actually up, hence no need to break them. */ | |
12304 | WARN_ON(crtc->active); | |
12305 | ||
12306 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
12307 | WARN_ON(encoder->connectors_active); | |
12308 | encoder->base.crtc = NULL; | |
12309 | } | |
12310 | } | |
c5ab3bc0 DV |
12311 | |
12312 | if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) { | |
4cc31489 DV |
12313 | /* |
12314 | * We start out with underrun reporting disabled to avoid races. | |
12315 | * For correct bookkeeping mark this on active crtcs. | |
12316 | * | |
c5ab3bc0 DV |
12317 | * Also on gmch platforms we dont have any hardware bits to |
12318 | * disable the underrun reporting. Which means we need to start | |
12319 | * out with underrun reporting disabled also on inactive pipes, | |
12320 | * since otherwise we'll complain about the garbage we read when | |
12321 | * e.g. coming up after runtime pm. | |
12322 | * | |
4cc31489 DV |
12323 | * No protection against concurrent access is required - at |
12324 | * worst a fifo underrun happens which also sets this to false. | |
12325 | */ | |
12326 | crtc->cpu_fifo_underrun_disabled = true; | |
12327 | crtc->pch_fifo_underrun_disabled = true; | |
80715b2f VS |
12328 | |
12329 | update_scanline_offset(crtc); | |
4cc31489 | 12330 | } |
24929352 DV |
12331 | } |
12332 | ||
12333 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
12334 | { | |
12335 | struct intel_connector *connector; | |
12336 | struct drm_device *dev = encoder->base.dev; | |
12337 | ||
12338 | /* We need to check both for a crtc link (meaning that the | |
12339 | * encoder is active and trying to read from a pipe) and the | |
12340 | * pipe itself being active. */ | |
12341 | bool has_active_crtc = encoder->base.crtc && | |
12342 | to_intel_crtc(encoder->base.crtc)->active; | |
12343 | ||
12344 | if (encoder->connectors_active && !has_active_crtc) { | |
12345 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
12346 | encoder->base.base.id, | |
8e329a03 | 12347 | encoder->base.name); |
24929352 DV |
12348 | |
12349 | /* Connector is active, but has no active pipe. This is | |
12350 | * fallout from our resume register restoring. Disable | |
12351 | * the encoder manually again. */ | |
12352 | if (encoder->base.crtc) { | |
12353 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
12354 | encoder->base.base.id, | |
8e329a03 | 12355 | encoder->base.name); |
24929352 DV |
12356 | encoder->disable(encoder); |
12357 | } | |
7f1950fb EE |
12358 | encoder->base.crtc = NULL; |
12359 | encoder->connectors_active = false; | |
24929352 DV |
12360 | |
12361 | /* Inconsistent output/port/pipe state happens presumably due to | |
12362 | * a bug in one of the get_hw_state functions. Or someplace else | |
12363 | * in our code, like the register restore mess on resume. Clamp | |
12364 | * things to off as a safer default. */ | |
12365 | list_for_each_entry(connector, | |
12366 | &dev->mode_config.connector_list, | |
12367 | base.head) { | |
12368 | if (connector->encoder != encoder) | |
12369 | continue; | |
7f1950fb EE |
12370 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
12371 | connector->base.encoder = NULL; | |
24929352 DV |
12372 | } |
12373 | } | |
12374 | /* Enabled encoders without active connectors will be fixed in | |
12375 | * the crtc fixup. */ | |
12376 | } | |
12377 | ||
04098753 | 12378 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
12379 | { |
12380 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 12381 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 12382 | |
04098753 ID |
12383 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
12384 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
12385 | i915_disable_vga(dev); | |
12386 | } | |
12387 | } | |
12388 | ||
12389 | void i915_redisable_vga(struct drm_device *dev) | |
12390 | { | |
12391 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12392 | ||
8dc8a27c PZ |
12393 | /* This function can be called both from intel_modeset_setup_hw_state or |
12394 | * at a very early point in our resume sequence, where the power well | |
12395 | * structures are not yet restored. Since this function is at a very | |
12396 | * paranoid "someone might have enabled VGA while we were not looking" | |
12397 | * level, just check if the power well is enabled instead of trying to | |
12398 | * follow the "don't touch the power well if we don't need it" policy | |
12399 | * the rest of the driver uses. */ | |
04098753 | 12400 | if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
12401 | return; |
12402 | ||
04098753 | 12403 | i915_redisable_vga_power_on(dev); |
0fde901f KM |
12404 | } |
12405 | ||
98ec7739 VS |
12406 | static bool primary_get_hw_state(struct intel_crtc *crtc) |
12407 | { | |
12408 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
12409 | ||
12410 | if (!crtc->active) | |
12411 | return false; | |
12412 | ||
12413 | return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE; | |
12414 | } | |
12415 | ||
30e984df | 12416 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
12417 | { |
12418 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12419 | enum pipe pipe; | |
24929352 DV |
12420 | struct intel_crtc *crtc; |
12421 | struct intel_encoder *encoder; | |
12422 | struct intel_connector *connector; | |
5358901f | 12423 | int i; |
24929352 | 12424 | |
d3fcc808 | 12425 | for_each_intel_crtc(dev, crtc) { |
88adfff1 | 12426 | memset(&crtc->config, 0, sizeof(crtc->config)); |
3b117c8f | 12427 | |
9953599b DV |
12428 | crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE; |
12429 | ||
0e8ffe1b DV |
12430 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
12431 | &crtc->config); | |
24929352 DV |
12432 | |
12433 | crtc->base.enabled = crtc->active; | |
98ec7739 | 12434 | crtc->primary_enabled = primary_get_hw_state(crtc); |
24929352 DV |
12435 | |
12436 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
12437 | crtc->base.base.id, | |
12438 | crtc->active ? "enabled" : "disabled"); | |
12439 | } | |
12440 | ||
5358901f | 12441 | /* FIXME: Smash this into the new shared dpll infrastructure. */ |
affa9354 | 12442 | if (HAS_DDI(dev)) |
6441ab5f PZ |
12443 | intel_ddi_setup_hw_pll_state(dev); |
12444 | ||
5358901f DV |
12445 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
12446 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
12447 | ||
12448 | pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state); | |
12449 | pll->active = 0; | |
d3fcc808 | 12450 | for_each_intel_crtc(dev, crtc) { |
5358901f DV |
12451 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) |
12452 | pll->active++; | |
12453 | } | |
12454 | pll->refcount = pll->active; | |
12455 | ||
35c95375 DV |
12456 | DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n", |
12457 | pll->name, pll->refcount, pll->on); | |
5358901f DV |
12458 | } |
12459 | ||
24929352 DV |
12460 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
12461 | base.head) { | |
12462 | pipe = 0; | |
12463 | ||
12464 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
12465 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
12466 | encoder->base.crtc = &crtc->base; | |
1d37b689 | 12467 | encoder->get_config(encoder, &crtc->config); |
24929352 DV |
12468 | } else { |
12469 | encoder->base.crtc = NULL; | |
12470 | } | |
12471 | ||
12472 | encoder->connectors_active = false; | |
6f2bcceb | 12473 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 12474 | encoder->base.base.id, |
8e329a03 | 12475 | encoder->base.name, |
24929352 | 12476 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 12477 | pipe_name(pipe)); |
24929352 DV |
12478 | } |
12479 | ||
12480 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
12481 | base.head) { | |
12482 | if (connector->get_hw_state(connector)) { | |
12483 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
12484 | connector->encoder->connectors_active = true; | |
12485 | connector->base.encoder = &connector->encoder->base; | |
12486 | } else { | |
12487 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
12488 | connector->base.encoder = NULL; | |
12489 | } | |
12490 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
12491 | connector->base.base.id, | |
c23cc417 | 12492 | connector->base.name, |
24929352 DV |
12493 | connector->base.encoder ? "enabled" : "disabled"); |
12494 | } | |
30e984df DV |
12495 | } |
12496 | ||
12497 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm | |
12498 | * and i915 state tracking structures. */ | |
12499 | void intel_modeset_setup_hw_state(struct drm_device *dev, | |
12500 | bool force_restore) | |
12501 | { | |
12502 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12503 | enum pipe pipe; | |
30e984df DV |
12504 | struct intel_crtc *crtc; |
12505 | struct intel_encoder *encoder; | |
35c95375 | 12506 | int i; |
30e984df DV |
12507 | |
12508 | intel_modeset_readout_hw_state(dev); | |
24929352 | 12509 | |
babea61d JB |
12510 | /* |
12511 | * Now that we have the config, copy it to each CRTC struct | |
12512 | * Note that this could go away if we move to using crtc_config | |
12513 | * checking everywhere. | |
12514 | */ | |
d3fcc808 | 12515 | for_each_intel_crtc(dev, crtc) { |
d330a953 | 12516 | if (crtc->active && i915.fastboot) { |
f6a83288 | 12517 | intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config); |
babea61d JB |
12518 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", |
12519 | crtc->base.base.id); | |
12520 | drm_mode_debug_printmodeline(&crtc->base.mode); | |
12521 | } | |
12522 | } | |
12523 | ||
24929352 DV |
12524 | /* HW state is read out, now we need to sanitize this mess. */ |
12525 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
12526 | base.head) { | |
12527 | intel_sanitize_encoder(encoder); | |
12528 | } | |
12529 | ||
12530 | for_each_pipe(pipe) { | |
12531 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
12532 | intel_sanitize_crtc(crtc); | |
c0b03411 | 12533 | intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]"); |
24929352 | 12534 | } |
9a935856 | 12535 | |
35c95375 DV |
12536 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
12537 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
12538 | ||
12539 | if (!pll->on || pll->active) | |
12540 | continue; | |
12541 | ||
12542 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
12543 | ||
12544 | pll->disable(dev_priv, pll); | |
12545 | pll->on = false; | |
12546 | } | |
12547 | ||
96f90c54 | 12548 | if (HAS_PCH_SPLIT(dev)) |
243e6a44 VS |
12549 | ilk_wm_get_hw_state(dev); |
12550 | ||
45e2b5f6 | 12551 | if (force_restore) { |
7d0bc1ea VS |
12552 | i915_redisable_vga(dev); |
12553 | ||
f30da187 DV |
12554 | /* |
12555 | * We need to use raw interfaces for restoring state to avoid | |
12556 | * checking (bogus) intermediate states. | |
12557 | */ | |
45e2b5f6 | 12558 | for_each_pipe(pipe) { |
b5644d05 JB |
12559 | struct drm_crtc *crtc = |
12560 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
f30da187 DV |
12561 | |
12562 | __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, | |
f4510a27 | 12563 | crtc->primary->fb); |
45e2b5f6 DV |
12564 | } |
12565 | } else { | |
12566 | intel_modeset_update_staged_output_state(dev); | |
12567 | } | |
8af6cf88 DV |
12568 | |
12569 | intel_modeset_check_state(dev); | |
2c7111db CW |
12570 | } |
12571 | ||
12572 | void intel_modeset_gem_init(struct drm_device *dev) | |
12573 | { | |
484b41dd JB |
12574 | struct drm_crtc *c; |
12575 | struct intel_framebuffer *fb; | |
12576 | ||
ae48434c ID |
12577 | mutex_lock(&dev->struct_mutex); |
12578 | intel_init_gt_powersave(dev); | |
12579 | mutex_unlock(&dev->struct_mutex); | |
12580 | ||
1833b134 | 12581 | intel_modeset_init_hw(dev); |
02e792fb DV |
12582 | |
12583 | intel_setup_overlay(dev); | |
484b41dd JB |
12584 | |
12585 | /* | |
12586 | * Make sure any fbs we allocated at startup are properly | |
12587 | * pinned & fenced. When we do the allocation it's too early | |
12588 | * for this. | |
12589 | */ | |
12590 | mutex_lock(&dev->struct_mutex); | |
70e1e0ec | 12591 | for_each_crtc(dev, c) { |
66e514c1 | 12592 | if (!c->primary->fb) |
484b41dd JB |
12593 | continue; |
12594 | ||
66e514c1 | 12595 | fb = to_intel_framebuffer(c->primary->fb); |
484b41dd JB |
12596 | if (intel_pin_and_fence_fb_obj(dev, fb->obj, NULL)) { |
12597 | DRM_ERROR("failed to pin boot fb on pipe %d\n", | |
12598 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
12599 | drm_framebuffer_unreference(c->primary->fb); |
12600 | c->primary->fb = NULL; | |
484b41dd JB |
12601 | } |
12602 | } | |
12603 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
12604 | } |
12605 | ||
4932e2c3 ID |
12606 | void intel_connector_unregister(struct intel_connector *intel_connector) |
12607 | { | |
12608 | struct drm_connector *connector = &intel_connector->base; | |
12609 | ||
12610 | intel_panel_destroy_backlight(connector); | |
12611 | drm_sysfs_connector_remove(connector); | |
12612 | } | |
12613 | ||
79e53945 JB |
12614 | void intel_modeset_cleanup(struct drm_device *dev) |
12615 | { | |
652c393a JB |
12616 | struct drm_i915_private *dev_priv = dev->dev_private; |
12617 | struct drm_crtc *crtc; | |
d9255d57 | 12618 | struct drm_connector *connector; |
652c393a | 12619 | |
fd0c0642 DV |
12620 | /* |
12621 | * Interrupts and polling as the first thing to avoid creating havoc. | |
12622 | * Too much stuff here (turning of rps, connectors, ...) would | |
12623 | * experience fancy races otherwise. | |
12624 | */ | |
12625 | drm_irq_uninstall(dev); | |
12626 | cancel_work_sync(&dev_priv->hotplug_work); | |
12627 | /* | |
12628 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
12629 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
12630 | */ | |
f87ea761 | 12631 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 12632 | |
652c393a JB |
12633 | mutex_lock(&dev->struct_mutex); |
12634 | ||
723bfd70 JB |
12635 | intel_unregister_dsm_handler(); |
12636 | ||
70e1e0ec | 12637 | for_each_crtc(dev, crtc) { |
652c393a | 12638 | /* Skip inactive CRTCs */ |
f4510a27 | 12639 | if (!crtc->primary->fb) |
652c393a JB |
12640 | continue; |
12641 | ||
3dec0095 | 12642 | intel_increase_pllclock(crtc); |
652c393a JB |
12643 | } |
12644 | ||
973d04f9 | 12645 | intel_disable_fbc(dev); |
e70236a8 | 12646 | |
8090c6b9 | 12647 | intel_disable_gt_powersave(dev); |
0cdab21f | 12648 | |
930ebb46 DV |
12649 | ironlake_teardown_rc6(dev); |
12650 | ||
69341a5e KH |
12651 | mutex_unlock(&dev->struct_mutex); |
12652 | ||
1630fe75 CW |
12653 | /* flush any delayed tasks or pending work */ |
12654 | flush_scheduled_work(); | |
12655 | ||
db31af1d JN |
12656 | /* destroy the backlight and sysfs files before encoders/connectors */ |
12657 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4932e2c3 ID |
12658 | struct intel_connector *intel_connector; |
12659 | ||
12660 | intel_connector = to_intel_connector(connector); | |
12661 | intel_connector->unregister(intel_connector); | |
db31af1d | 12662 | } |
d9255d57 | 12663 | |
79e53945 | 12664 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
12665 | |
12666 | intel_cleanup_overlay(dev); | |
ae48434c ID |
12667 | |
12668 | mutex_lock(&dev->struct_mutex); | |
12669 | intel_cleanup_gt_powersave(dev); | |
12670 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
12671 | } |
12672 | ||
f1c79df3 ZW |
12673 | /* |
12674 | * Return which encoder is currently attached for connector. | |
12675 | */ | |
df0e9248 | 12676 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 12677 | { |
df0e9248 CW |
12678 | return &intel_attached_encoder(connector)->base; |
12679 | } | |
f1c79df3 | 12680 | |
df0e9248 CW |
12681 | void intel_connector_attach_encoder(struct intel_connector *connector, |
12682 | struct intel_encoder *encoder) | |
12683 | { | |
12684 | connector->encoder = encoder; | |
12685 | drm_mode_connector_attach_encoder(&connector->base, | |
12686 | &encoder->base); | |
79e53945 | 12687 | } |
28d52043 DA |
12688 | |
12689 | /* | |
12690 | * set vga decode state - true == enable VGA decode | |
12691 | */ | |
12692 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
12693 | { | |
12694 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 12695 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
12696 | u16 gmch_ctrl; |
12697 | ||
75fa041d CW |
12698 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
12699 | DRM_ERROR("failed to read control word\n"); | |
12700 | return -EIO; | |
12701 | } | |
12702 | ||
c0cc8a55 CW |
12703 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
12704 | return 0; | |
12705 | ||
28d52043 DA |
12706 | if (state) |
12707 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
12708 | else | |
12709 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
12710 | |
12711 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
12712 | DRM_ERROR("failed to write control word\n"); | |
12713 | return -EIO; | |
12714 | } | |
12715 | ||
28d52043 DA |
12716 | return 0; |
12717 | } | |
c4a1d9e4 | 12718 | |
c4a1d9e4 | 12719 | struct intel_display_error_state { |
ff57f1b0 PZ |
12720 | |
12721 | u32 power_well_driver; | |
12722 | ||
63b66e5b CW |
12723 | int num_transcoders; |
12724 | ||
c4a1d9e4 CW |
12725 | struct intel_cursor_error_state { |
12726 | u32 control; | |
12727 | u32 position; | |
12728 | u32 base; | |
12729 | u32 size; | |
52331309 | 12730 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
12731 | |
12732 | struct intel_pipe_error_state { | |
ddf9c536 | 12733 | bool power_domain_on; |
c4a1d9e4 | 12734 | u32 source; |
f301b1e1 | 12735 | u32 stat; |
52331309 | 12736 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
12737 | |
12738 | struct intel_plane_error_state { | |
12739 | u32 control; | |
12740 | u32 stride; | |
12741 | u32 size; | |
12742 | u32 pos; | |
12743 | u32 addr; | |
12744 | u32 surface; | |
12745 | u32 tile_offset; | |
52331309 | 12746 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
12747 | |
12748 | struct intel_transcoder_error_state { | |
ddf9c536 | 12749 | bool power_domain_on; |
63b66e5b CW |
12750 | enum transcoder cpu_transcoder; |
12751 | ||
12752 | u32 conf; | |
12753 | ||
12754 | u32 htotal; | |
12755 | u32 hblank; | |
12756 | u32 hsync; | |
12757 | u32 vtotal; | |
12758 | u32 vblank; | |
12759 | u32 vsync; | |
12760 | } transcoder[4]; | |
c4a1d9e4 CW |
12761 | }; |
12762 | ||
12763 | struct intel_display_error_state * | |
12764 | intel_display_capture_error_state(struct drm_device *dev) | |
12765 | { | |
fbee40df | 12766 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 12767 | struct intel_display_error_state *error; |
63b66e5b CW |
12768 | int transcoders[] = { |
12769 | TRANSCODER_A, | |
12770 | TRANSCODER_B, | |
12771 | TRANSCODER_C, | |
12772 | TRANSCODER_EDP, | |
12773 | }; | |
c4a1d9e4 CW |
12774 | int i; |
12775 | ||
63b66e5b CW |
12776 | if (INTEL_INFO(dev)->num_pipes == 0) |
12777 | return NULL; | |
12778 | ||
9d1cb914 | 12779 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
12780 | if (error == NULL) |
12781 | return NULL; | |
12782 | ||
190be112 | 12783 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
12784 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
12785 | ||
52331309 | 12786 | for_each_pipe(i) { |
ddf9c536 | 12787 | error->pipe[i].power_domain_on = |
da7e29bd ID |
12788 | intel_display_power_enabled_sw(dev_priv, |
12789 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 12790 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
12791 | continue; |
12792 | ||
5efb3e28 VS |
12793 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
12794 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
12795 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
12796 | |
12797 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
12798 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 12799 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 12800 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
12801 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
12802 | } | |
ca291363 PZ |
12803 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
12804 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
12805 | if (INTEL_INFO(dev)->gen >= 4) { |
12806 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
12807 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
12808 | } | |
12809 | ||
c4a1d9e4 | 12810 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 ID |
12811 | |
12812 | if (!HAS_PCH_SPLIT(dev)) | |
12813 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); | |
63b66e5b CW |
12814 | } |
12815 | ||
12816 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
12817 | if (HAS_DDI(dev_priv->dev)) | |
12818 | error->num_transcoders++; /* Account for eDP. */ | |
12819 | ||
12820 | for (i = 0; i < error->num_transcoders; i++) { | |
12821 | enum transcoder cpu_transcoder = transcoders[i]; | |
12822 | ||
ddf9c536 | 12823 | error->transcoder[i].power_domain_on = |
da7e29bd | 12824 | intel_display_power_enabled_sw(dev_priv, |
38cc1daf | 12825 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 12826 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
12827 | continue; |
12828 | ||
63b66e5b CW |
12829 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
12830 | ||
12831 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
12832 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
12833 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
12834 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
12835 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
12836 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
12837 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
12838 | } |
12839 | ||
12840 | return error; | |
12841 | } | |
12842 | ||
edc3d884 MK |
12843 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
12844 | ||
c4a1d9e4 | 12845 | void |
edc3d884 | 12846 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
12847 | struct drm_device *dev, |
12848 | struct intel_display_error_state *error) | |
12849 | { | |
12850 | int i; | |
12851 | ||
63b66e5b CW |
12852 | if (!error) |
12853 | return; | |
12854 | ||
edc3d884 | 12855 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 12856 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 12857 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 12858 | error->power_well_driver); |
52331309 | 12859 | for_each_pipe(i) { |
edc3d884 | 12860 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 ID |
12861 | err_printf(m, " Power: %s\n", |
12862 | error->pipe[i].power_domain_on ? "on" : "off"); | |
edc3d884 | 12863 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 12864 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
12865 | |
12866 | err_printf(m, "Plane [%d]:\n", i); | |
12867 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
12868 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 12869 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
12870 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
12871 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 12872 | } |
4b71a570 | 12873 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 12874 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 12875 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
12876 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
12877 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
12878 | } |
12879 | ||
edc3d884 MK |
12880 | err_printf(m, "Cursor [%d]:\n", i); |
12881 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
12882 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
12883 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 12884 | } |
63b66e5b CW |
12885 | |
12886 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 12887 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 12888 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 ID |
12889 | err_printf(m, " Power: %s\n", |
12890 | error->transcoder[i].power_domain_on ? "on" : "off"); | |
63b66e5b CW |
12891 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
12892 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
12893 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
12894 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
12895 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
12896 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
12897 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
12898 | } | |
c4a1d9e4 | 12899 | } |