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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
760285e7 DH |
40 | #include <drm/drm_dp_helper.h> |
41 | #include <drm/drm_crtc_helper.h> | |
c0f372b3 | 42 | #include <linux/dma_remapping.h> |
79e53945 | 43 | |
3dec0095 | 44 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
6b383a7f | 45 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 46 | |
f1f644dc JB |
47 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
48 | struct intel_crtc_config *pipe_config); | |
18442d08 VS |
49 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
50 | struct intel_crtc_config *pipe_config); | |
f1f644dc | 51 | |
e7457a9a DL |
52 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
53 | int x, int y, struct drm_framebuffer *old_fb); | |
54 | ||
55 | ||
79e53945 | 56 | typedef struct { |
0206e353 | 57 | int min, max; |
79e53945 JB |
58 | } intel_range_t; |
59 | ||
60 | typedef struct { | |
0206e353 AJ |
61 | int dot_limit; |
62 | int p2_slow, p2_fast; | |
79e53945 JB |
63 | } intel_p2_t; |
64 | ||
d4906093 ML |
65 | typedef struct intel_limit intel_limit_t; |
66 | struct intel_limit { | |
0206e353 AJ |
67 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
68 | intel_p2_t p2; | |
d4906093 | 69 | }; |
79e53945 | 70 | |
d2acd215 DV |
71 | int |
72 | intel_pch_rawclk(struct drm_device *dev) | |
73 | { | |
74 | struct drm_i915_private *dev_priv = dev->dev_private; | |
75 | ||
76 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
77 | ||
78 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
79 | } | |
80 | ||
021357ac CW |
81 | static inline u32 /* units of 100MHz */ |
82 | intel_fdi_link_freq(struct drm_device *dev) | |
83 | { | |
8b99e68c CW |
84 | if (IS_GEN5(dev)) { |
85 | struct drm_i915_private *dev_priv = dev->dev_private; | |
86 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
87 | } else | |
88 | return 27; | |
021357ac CW |
89 | } |
90 | ||
5d536e28 | 91 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 92 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 93 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 94 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
95 | .m = { .min = 96, .max = 140 }, |
96 | .m1 = { .min = 18, .max = 26 }, | |
97 | .m2 = { .min = 6, .max = 16 }, | |
98 | .p = { .min = 4, .max = 128 }, | |
99 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
100 | .p2 = { .dot_limit = 165000, |
101 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
102 | }; |
103 | ||
5d536e28 DV |
104 | static const intel_limit_t intel_limits_i8xx_dvo = { |
105 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 106 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 107 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
108 | .m = { .min = 96, .max = 140 }, |
109 | .m1 = { .min = 18, .max = 26 }, | |
110 | .m2 = { .min = 6, .max = 16 }, | |
111 | .p = { .min = 4, .max = 128 }, | |
112 | .p1 = { .min = 2, .max = 33 }, | |
113 | .p2 = { .dot_limit = 165000, | |
114 | .p2_slow = 4, .p2_fast = 4 }, | |
115 | }; | |
116 | ||
e4b36699 | 117 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 118 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 119 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 120 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
121 | .m = { .min = 96, .max = 140 }, |
122 | .m1 = { .min = 18, .max = 26 }, | |
123 | .m2 = { .min = 6, .max = 16 }, | |
124 | .p = { .min = 4, .max = 128 }, | |
125 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
126 | .p2 = { .dot_limit = 165000, |
127 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 128 | }; |
273e27ca | 129 | |
e4b36699 | 130 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
131 | .dot = { .min = 20000, .max = 400000 }, |
132 | .vco = { .min = 1400000, .max = 2800000 }, | |
133 | .n = { .min = 1, .max = 6 }, | |
134 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
135 | .m1 = { .min = 8, .max = 18 }, |
136 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
137 | .p = { .min = 5, .max = 80 }, |
138 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
139 | .p2 = { .dot_limit = 200000, |
140 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
141 | }; |
142 | ||
143 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
144 | .dot = { .min = 20000, .max = 400000 }, |
145 | .vco = { .min = 1400000, .max = 2800000 }, | |
146 | .n = { .min = 1, .max = 6 }, | |
147 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
148 | .m1 = { .min = 8, .max = 18 }, |
149 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
150 | .p = { .min = 7, .max = 98 }, |
151 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
152 | .p2 = { .dot_limit = 112000, |
153 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
154 | }; |
155 | ||
273e27ca | 156 | |
e4b36699 | 157 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
158 | .dot = { .min = 25000, .max = 270000 }, |
159 | .vco = { .min = 1750000, .max = 3500000}, | |
160 | .n = { .min = 1, .max = 4 }, | |
161 | .m = { .min = 104, .max = 138 }, | |
162 | .m1 = { .min = 17, .max = 23 }, | |
163 | .m2 = { .min = 5, .max = 11 }, | |
164 | .p = { .min = 10, .max = 30 }, | |
165 | .p1 = { .min = 1, .max = 3}, | |
166 | .p2 = { .dot_limit = 270000, | |
167 | .p2_slow = 10, | |
168 | .p2_fast = 10 | |
044c7c41 | 169 | }, |
e4b36699 KP |
170 | }; |
171 | ||
172 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
173 | .dot = { .min = 22000, .max = 400000 }, |
174 | .vco = { .min = 1750000, .max = 3500000}, | |
175 | .n = { .min = 1, .max = 4 }, | |
176 | .m = { .min = 104, .max = 138 }, | |
177 | .m1 = { .min = 16, .max = 23 }, | |
178 | .m2 = { .min = 5, .max = 11 }, | |
179 | .p = { .min = 5, .max = 80 }, | |
180 | .p1 = { .min = 1, .max = 8}, | |
181 | .p2 = { .dot_limit = 165000, | |
182 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
183 | }; |
184 | ||
185 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
186 | .dot = { .min = 20000, .max = 115000 }, |
187 | .vco = { .min = 1750000, .max = 3500000 }, | |
188 | .n = { .min = 1, .max = 3 }, | |
189 | .m = { .min = 104, .max = 138 }, | |
190 | .m1 = { .min = 17, .max = 23 }, | |
191 | .m2 = { .min = 5, .max = 11 }, | |
192 | .p = { .min = 28, .max = 112 }, | |
193 | .p1 = { .min = 2, .max = 8 }, | |
194 | .p2 = { .dot_limit = 0, | |
195 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 196 | }, |
e4b36699 KP |
197 | }; |
198 | ||
199 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
200 | .dot = { .min = 80000, .max = 224000 }, |
201 | .vco = { .min = 1750000, .max = 3500000 }, | |
202 | .n = { .min = 1, .max = 3 }, | |
203 | .m = { .min = 104, .max = 138 }, | |
204 | .m1 = { .min = 17, .max = 23 }, | |
205 | .m2 = { .min = 5, .max = 11 }, | |
206 | .p = { .min = 14, .max = 42 }, | |
207 | .p1 = { .min = 2, .max = 6 }, | |
208 | .p2 = { .dot_limit = 0, | |
209 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 210 | }, |
e4b36699 KP |
211 | }; |
212 | ||
f2b115e6 | 213 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
214 | .dot = { .min = 20000, .max = 400000}, |
215 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 216 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
217 | .n = { .min = 3, .max = 6 }, |
218 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 219 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
220 | .m1 = { .min = 0, .max = 0 }, |
221 | .m2 = { .min = 0, .max = 254 }, | |
222 | .p = { .min = 5, .max = 80 }, | |
223 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
224 | .p2 = { .dot_limit = 200000, |
225 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
226 | }; |
227 | ||
f2b115e6 | 228 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
229 | .dot = { .min = 20000, .max = 400000 }, |
230 | .vco = { .min = 1700000, .max = 3500000 }, | |
231 | .n = { .min = 3, .max = 6 }, | |
232 | .m = { .min = 2, .max = 256 }, | |
233 | .m1 = { .min = 0, .max = 0 }, | |
234 | .m2 = { .min = 0, .max = 254 }, | |
235 | .p = { .min = 7, .max = 112 }, | |
236 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
237 | .p2 = { .dot_limit = 112000, |
238 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
239 | }; |
240 | ||
273e27ca EA |
241 | /* Ironlake / Sandybridge |
242 | * | |
243 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
244 | * the range value for them is (actual_value - 2). | |
245 | */ | |
b91ad0ec | 246 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
247 | .dot = { .min = 25000, .max = 350000 }, |
248 | .vco = { .min = 1760000, .max = 3510000 }, | |
249 | .n = { .min = 1, .max = 5 }, | |
250 | .m = { .min = 79, .max = 127 }, | |
251 | .m1 = { .min = 12, .max = 22 }, | |
252 | .m2 = { .min = 5, .max = 9 }, | |
253 | .p = { .min = 5, .max = 80 }, | |
254 | .p1 = { .min = 1, .max = 8 }, | |
255 | .p2 = { .dot_limit = 225000, | |
256 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
257 | }; |
258 | ||
b91ad0ec | 259 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
260 | .dot = { .min = 25000, .max = 350000 }, |
261 | .vco = { .min = 1760000, .max = 3510000 }, | |
262 | .n = { .min = 1, .max = 3 }, | |
263 | .m = { .min = 79, .max = 118 }, | |
264 | .m1 = { .min = 12, .max = 22 }, | |
265 | .m2 = { .min = 5, .max = 9 }, | |
266 | .p = { .min = 28, .max = 112 }, | |
267 | .p1 = { .min = 2, .max = 8 }, | |
268 | .p2 = { .dot_limit = 225000, | |
269 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
270 | }; |
271 | ||
272 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
273 | .dot = { .min = 25000, .max = 350000 }, |
274 | .vco = { .min = 1760000, .max = 3510000 }, | |
275 | .n = { .min = 1, .max = 3 }, | |
276 | .m = { .min = 79, .max = 127 }, | |
277 | .m1 = { .min = 12, .max = 22 }, | |
278 | .m2 = { .min = 5, .max = 9 }, | |
279 | .p = { .min = 14, .max = 56 }, | |
280 | .p1 = { .min = 2, .max = 8 }, | |
281 | .p2 = { .dot_limit = 225000, | |
282 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
283 | }; |
284 | ||
273e27ca | 285 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 286 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
287 | .dot = { .min = 25000, .max = 350000 }, |
288 | .vco = { .min = 1760000, .max = 3510000 }, | |
289 | .n = { .min = 1, .max = 2 }, | |
290 | .m = { .min = 79, .max = 126 }, | |
291 | .m1 = { .min = 12, .max = 22 }, | |
292 | .m2 = { .min = 5, .max = 9 }, | |
293 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 294 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
295 | .p2 = { .dot_limit = 225000, |
296 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
297 | }; |
298 | ||
299 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
300 | .dot = { .min = 25000, .max = 350000 }, |
301 | .vco = { .min = 1760000, .max = 3510000 }, | |
302 | .n = { .min = 1, .max = 3 }, | |
303 | .m = { .min = 79, .max = 126 }, | |
304 | .m1 = { .min = 12, .max = 22 }, | |
305 | .m2 = { .min = 5, .max = 9 }, | |
306 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 307 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
308 | .p2 = { .dot_limit = 225000, |
309 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
310 | }; |
311 | ||
dc730512 | 312 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
313 | /* |
314 | * These are the data rate limits (measured in fast clocks) | |
315 | * since those are the strictest limits we have. The fast | |
316 | * clock and actual rate limits are more relaxed, so checking | |
317 | * them would make no difference. | |
318 | */ | |
319 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 320 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 321 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
322 | .m1 = { .min = 2, .max = 3 }, |
323 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 324 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 325 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
326 | }; |
327 | ||
6b4bf1c4 VS |
328 | static void vlv_clock(int refclk, intel_clock_t *clock) |
329 | { | |
330 | clock->m = clock->m1 * clock->m2; | |
331 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
332 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
333 | return; | |
fb03ac01 VS |
334 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
335 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
6b4bf1c4 VS |
336 | } |
337 | ||
e0638cdf PZ |
338 | /** |
339 | * Returns whether any output on the specified pipe is of the specified type | |
340 | */ | |
341 | static bool intel_pipe_has_type(struct drm_crtc *crtc, int type) | |
342 | { | |
343 | struct drm_device *dev = crtc->dev; | |
344 | struct intel_encoder *encoder; | |
345 | ||
346 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
347 | if (encoder->type == type) | |
348 | return true; | |
349 | ||
350 | return false; | |
351 | } | |
352 | ||
1b894b59 CW |
353 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
354 | int refclk) | |
2c07245f | 355 | { |
b91ad0ec | 356 | struct drm_device *dev = crtc->dev; |
2c07245f | 357 | const intel_limit_t *limit; |
b91ad0ec ZW |
358 | |
359 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 360 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 361 | if (refclk == 100000) |
b91ad0ec ZW |
362 | limit = &intel_limits_ironlake_dual_lvds_100m; |
363 | else | |
364 | limit = &intel_limits_ironlake_dual_lvds; | |
365 | } else { | |
1b894b59 | 366 | if (refclk == 100000) |
b91ad0ec ZW |
367 | limit = &intel_limits_ironlake_single_lvds_100m; |
368 | else | |
369 | limit = &intel_limits_ironlake_single_lvds; | |
370 | } | |
c6bb3538 | 371 | } else |
b91ad0ec | 372 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
373 | |
374 | return limit; | |
375 | } | |
376 | ||
044c7c41 ML |
377 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
378 | { | |
379 | struct drm_device *dev = crtc->dev; | |
044c7c41 ML |
380 | const intel_limit_t *limit; |
381 | ||
382 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 383 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 384 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 385 | else |
e4b36699 | 386 | limit = &intel_limits_g4x_single_channel_lvds; |
044c7c41 ML |
387 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
388 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 389 | limit = &intel_limits_g4x_hdmi; |
044c7c41 | 390 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 391 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 392 | } else /* The option is for other outputs */ |
e4b36699 | 393 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
394 | |
395 | return limit; | |
396 | } | |
397 | ||
1b894b59 | 398 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
79e53945 JB |
399 | { |
400 | struct drm_device *dev = crtc->dev; | |
401 | const intel_limit_t *limit; | |
402 | ||
bad720ff | 403 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 404 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 405 | else if (IS_G4X(dev)) { |
044c7c41 | 406 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 407 | } else if (IS_PINEVIEW(dev)) { |
2177832f | 408 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 409 | limit = &intel_limits_pineview_lvds; |
2177832f | 410 | else |
f2b115e6 | 411 | limit = &intel_limits_pineview_sdvo; |
a0c4da24 | 412 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 413 | limit = &intel_limits_vlv; |
a6c45cf0 CW |
414 | } else if (!IS_GEN2(dev)) { |
415 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
416 | limit = &intel_limits_i9xx_lvds; | |
417 | else | |
418 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 JB |
419 | } else { |
420 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 421 | limit = &intel_limits_i8xx_lvds; |
5d536e28 | 422 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO)) |
e4b36699 | 423 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
424 | else |
425 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
426 | } |
427 | return limit; | |
428 | } | |
429 | ||
f2b115e6 AJ |
430 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
431 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 432 | { |
2177832f SL |
433 | clock->m = clock->m2 + 2; |
434 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
435 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
436 | return; | |
fb03ac01 VS |
437 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
438 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
2177832f SL |
439 | } |
440 | ||
7429e9d4 DV |
441 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
442 | { | |
443 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
444 | } | |
445 | ||
ac58c3f0 | 446 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
2177832f | 447 | { |
7429e9d4 | 448 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 449 | clock->p = clock->p1 * clock->p2; |
ed5ca77e VS |
450 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
451 | return; | |
fb03ac01 VS |
452 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
453 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
79e53945 JB |
454 | } |
455 | ||
7c04d1d9 | 456 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
457 | /** |
458 | * Returns whether the given set of divisors are valid for a given refclk with | |
459 | * the given connectors. | |
460 | */ | |
461 | ||
1b894b59 CW |
462 | static bool intel_PLL_is_valid(struct drm_device *dev, |
463 | const intel_limit_t *limit, | |
464 | const intel_clock_t *clock) | |
79e53945 | 465 | { |
f01b7962 VS |
466 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
467 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 468 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 469 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 470 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 471 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 472 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 473 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 VS |
474 | |
475 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev)) | |
476 | if (clock->m1 <= clock->m2) | |
477 | INTELPllInvalid("m1 <= m2\n"); | |
478 | ||
479 | if (!IS_VALLEYVIEW(dev)) { | |
480 | if (clock->p < limit->p.min || limit->p.max < clock->p) | |
481 | INTELPllInvalid("p out of range\n"); | |
482 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
483 | INTELPllInvalid("m out of range\n"); | |
484 | } | |
485 | ||
79e53945 | 486 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 487 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
488 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
489 | * connector, etc., rather than just a single range. | |
490 | */ | |
491 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 492 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
493 | |
494 | return true; | |
495 | } | |
496 | ||
d4906093 | 497 | static bool |
ee9300bb | 498 | i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
cec2f356 SP |
499 | int target, int refclk, intel_clock_t *match_clock, |
500 | intel_clock_t *best_clock) | |
79e53945 JB |
501 | { |
502 | struct drm_device *dev = crtc->dev; | |
79e53945 | 503 | intel_clock_t clock; |
79e53945 JB |
504 | int err = target; |
505 | ||
a210b028 | 506 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 507 | /* |
a210b028 DV |
508 | * For LVDS just rely on its current settings for dual-channel. |
509 | * We haven't figured out how to reliably set up different | |
510 | * single/dual channel state, if we even can. | |
79e53945 | 511 | */ |
1974cad0 | 512 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
513 | clock.p2 = limit->p2.p2_fast; |
514 | else | |
515 | clock.p2 = limit->p2.p2_slow; | |
516 | } else { | |
517 | if (target < limit->p2.dot_limit) | |
518 | clock.p2 = limit->p2.p2_slow; | |
519 | else | |
520 | clock.p2 = limit->p2.p2_fast; | |
521 | } | |
522 | ||
0206e353 | 523 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 524 | |
42158660 ZY |
525 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
526 | clock.m1++) { | |
527 | for (clock.m2 = limit->m2.min; | |
528 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 529 | if (clock.m2 >= clock.m1) |
42158660 ZY |
530 | break; |
531 | for (clock.n = limit->n.min; | |
532 | clock.n <= limit->n.max; clock.n++) { | |
533 | for (clock.p1 = limit->p1.min; | |
534 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
535 | int this_err; |
536 | ||
ac58c3f0 DV |
537 | i9xx_clock(refclk, &clock); |
538 | if (!intel_PLL_is_valid(dev, limit, | |
539 | &clock)) | |
540 | continue; | |
541 | if (match_clock && | |
542 | clock.p != match_clock->p) | |
543 | continue; | |
544 | ||
545 | this_err = abs(clock.dot - target); | |
546 | if (this_err < err) { | |
547 | *best_clock = clock; | |
548 | err = this_err; | |
549 | } | |
550 | } | |
551 | } | |
552 | } | |
553 | } | |
554 | ||
555 | return (err != target); | |
556 | } | |
557 | ||
558 | static bool | |
ee9300bb DV |
559 | pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
560 | int target, int refclk, intel_clock_t *match_clock, | |
561 | intel_clock_t *best_clock) | |
79e53945 JB |
562 | { |
563 | struct drm_device *dev = crtc->dev; | |
79e53945 | 564 | intel_clock_t clock; |
79e53945 JB |
565 | int err = target; |
566 | ||
a210b028 | 567 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 568 | /* |
a210b028 DV |
569 | * For LVDS just rely on its current settings for dual-channel. |
570 | * We haven't figured out how to reliably set up different | |
571 | * single/dual channel state, if we even can. | |
79e53945 | 572 | */ |
1974cad0 | 573 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
574 | clock.p2 = limit->p2.p2_fast; |
575 | else | |
576 | clock.p2 = limit->p2.p2_slow; | |
577 | } else { | |
578 | if (target < limit->p2.dot_limit) | |
579 | clock.p2 = limit->p2.p2_slow; | |
580 | else | |
581 | clock.p2 = limit->p2.p2_fast; | |
582 | } | |
583 | ||
0206e353 | 584 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 585 | |
42158660 ZY |
586 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
587 | clock.m1++) { | |
588 | for (clock.m2 = limit->m2.min; | |
589 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
590 | for (clock.n = limit->n.min; |
591 | clock.n <= limit->n.max; clock.n++) { | |
592 | for (clock.p1 = limit->p1.min; | |
593 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
594 | int this_err; |
595 | ||
ac58c3f0 | 596 | pineview_clock(refclk, &clock); |
1b894b59 CW |
597 | if (!intel_PLL_is_valid(dev, limit, |
598 | &clock)) | |
79e53945 | 599 | continue; |
cec2f356 SP |
600 | if (match_clock && |
601 | clock.p != match_clock->p) | |
602 | continue; | |
79e53945 JB |
603 | |
604 | this_err = abs(clock.dot - target); | |
605 | if (this_err < err) { | |
606 | *best_clock = clock; | |
607 | err = this_err; | |
608 | } | |
609 | } | |
610 | } | |
611 | } | |
612 | } | |
613 | ||
614 | return (err != target); | |
615 | } | |
616 | ||
d4906093 | 617 | static bool |
ee9300bb DV |
618 | g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
619 | int target, int refclk, intel_clock_t *match_clock, | |
620 | intel_clock_t *best_clock) | |
d4906093 ML |
621 | { |
622 | struct drm_device *dev = crtc->dev; | |
d4906093 ML |
623 | intel_clock_t clock; |
624 | int max_n; | |
625 | bool found; | |
6ba770dc AJ |
626 | /* approximately equals target * 0.00585 */ |
627 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
628 | found = false; |
629 | ||
630 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 631 | if (intel_is_dual_link_lvds(dev)) |
d4906093 ML |
632 | clock.p2 = limit->p2.p2_fast; |
633 | else | |
634 | clock.p2 = limit->p2.p2_slow; | |
635 | } else { | |
636 | if (target < limit->p2.dot_limit) | |
637 | clock.p2 = limit->p2.p2_slow; | |
638 | else | |
639 | clock.p2 = limit->p2.p2_fast; | |
640 | } | |
641 | ||
642 | memset(best_clock, 0, sizeof(*best_clock)); | |
643 | max_n = limit->n.max; | |
f77f13e2 | 644 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 645 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 646 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
647 | for (clock.m1 = limit->m1.max; |
648 | clock.m1 >= limit->m1.min; clock.m1--) { | |
649 | for (clock.m2 = limit->m2.max; | |
650 | clock.m2 >= limit->m2.min; clock.m2--) { | |
651 | for (clock.p1 = limit->p1.max; | |
652 | clock.p1 >= limit->p1.min; clock.p1--) { | |
653 | int this_err; | |
654 | ||
ac58c3f0 | 655 | i9xx_clock(refclk, &clock); |
1b894b59 CW |
656 | if (!intel_PLL_is_valid(dev, limit, |
657 | &clock)) | |
d4906093 | 658 | continue; |
1b894b59 CW |
659 | |
660 | this_err = abs(clock.dot - target); | |
d4906093 ML |
661 | if (this_err < err_most) { |
662 | *best_clock = clock; | |
663 | err_most = this_err; | |
664 | max_n = clock.n; | |
665 | found = true; | |
666 | } | |
667 | } | |
668 | } | |
669 | } | |
670 | } | |
2c07245f ZW |
671 | return found; |
672 | } | |
673 | ||
a0c4da24 | 674 | static bool |
ee9300bb DV |
675 | vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
676 | int target, int refclk, intel_clock_t *match_clock, | |
677 | intel_clock_t *best_clock) | |
a0c4da24 | 678 | { |
f01b7962 | 679 | struct drm_device *dev = crtc->dev; |
6b4bf1c4 | 680 | intel_clock_t clock; |
69e4f900 | 681 | unsigned int bestppm = 1000000; |
27e639bf VS |
682 | /* min update 19.2 MHz */ |
683 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 684 | bool found = false; |
a0c4da24 | 685 | |
6b4bf1c4 VS |
686 | target *= 5; /* fast clock */ |
687 | ||
688 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
689 | |
690 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 691 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 692 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 693 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 694 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 695 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 696 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 697 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
69e4f900 VS |
698 | unsigned int ppm, diff; |
699 | ||
6b4bf1c4 VS |
700 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
701 | refclk * clock.m1); | |
702 | ||
703 | vlv_clock(refclk, &clock); | |
43b0ac53 | 704 | |
f01b7962 VS |
705 | if (!intel_PLL_is_valid(dev, limit, |
706 | &clock)) | |
43b0ac53 VS |
707 | continue; |
708 | ||
6b4bf1c4 VS |
709 | diff = abs(clock.dot - target); |
710 | ppm = div_u64(1000000ULL * diff, target); | |
711 | ||
712 | if (ppm < 100 && clock.p > best_clock->p) { | |
43b0ac53 | 713 | bestppm = 0; |
6b4bf1c4 | 714 | *best_clock = clock; |
49e497ef | 715 | found = true; |
43b0ac53 | 716 | } |
6b4bf1c4 | 717 | |
c686122c | 718 | if (bestppm >= 10 && ppm < bestppm - 10) { |
69e4f900 | 719 | bestppm = ppm; |
6b4bf1c4 | 720 | *best_clock = clock; |
49e497ef | 721 | found = true; |
a0c4da24 JB |
722 | } |
723 | } | |
724 | } | |
725 | } | |
726 | } | |
a0c4da24 | 727 | |
49e497ef | 728 | return found; |
a0c4da24 | 729 | } |
a4fc5ed6 | 730 | |
20ddf665 VS |
731 | bool intel_crtc_active(struct drm_crtc *crtc) |
732 | { | |
733 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
734 | ||
735 | /* Be paranoid as we can arrive here with only partial | |
736 | * state retrieved from the hardware during setup. | |
737 | * | |
241bfc38 | 738 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
739 | * as Haswell has gained clock readout/fastboot support. |
740 | * | |
741 | * We can ditch the crtc->fb check as soon as we can | |
742 | * properly reconstruct framebuffers. | |
743 | */ | |
744 | return intel_crtc->active && crtc->fb && | |
241bfc38 | 745 | intel_crtc->config.adjusted_mode.crtc_clock; |
20ddf665 VS |
746 | } |
747 | ||
a5c961d1 PZ |
748 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
749 | enum pipe pipe) | |
750 | { | |
751 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
752 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
753 | ||
3b117c8f | 754 | return intel_crtc->config.cpu_transcoder; |
a5c961d1 PZ |
755 | } |
756 | ||
57e22f4a | 757 | static void g4x_wait_for_vblank(struct drm_device *dev, int pipe) |
a928d536 PZ |
758 | { |
759 | struct drm_i915_private *dev_priv = dev->dev_private; | |
57e22f4a | 760 | u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe); |
a928d536 PZ |
761 | |
762 | frame = I915_READ(frame_reg); | |
763 | ||
764 | if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) | |
765 | DRM_DEBUG_KMS("vblank wait timed out\n"); | |
766 | } | |
767 | ||
9d0498a2 JB |
768 | /** |
769 | * intel_wait_for_vblank - wait for vblank on a given pipe | |
770 | * @dev: drm device | |
771 | * @pipe: pipe to wait for | |
772 | * | |
773 | * Wait for vblank to occur on a given pipe. Needed for various bits of | |
774 | * mode setting code. | |
775 | */ | |
776 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
79e53945 | 777 | { |
9d0498a2 | 778 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 779 | int pipestat_reg = PIPESTAT(pipe); |
9d0498a2 | 780 | |
57e22f4a VS |
781 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
782 | g4x_wait_for_vblank(dev, pipe); | |
a928d536 PZ |
783 | return; |
784 | } | |
785 | ||
300387c0 CW |
786 | /* Clear existing vblank status. Note this will clear any other |
787 | * sticky status fields as well. | |
788 | * | |
789 | * This races with i915_driver_irq_handler() with the result | |
790 | * that either function could miss a vblank event. Here it is not | |
791 | * fatal, as we will either wait upon the next vblank interrupt or | |
792 | * timeout. Generally speaking intel_wait_for_vblank() is only | |
793 | * called during modeset at which time the GPU should be idle and | |
794 | * should *not* be performing page flips and thus not waiting on | |
795 | * vblanks... | |
796 | * Currently, the result of us stealing a vblank from the irq | |
797 | * handler is that a single frame will be skipped during swapbuffers. | |
798 | */ | |
799 | I915_WRITE(pipestat_reg, | |
800 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); | |
801 | ||
9d0498a2 | 802 | /* Wait for vblank interrupt bit to set */ |
481b6af3 CW |
803 | if (wait_for(I915_READ(pipestat_reg) & |
804 | PIPE_VBLANK_INTERRUPT_STATUS, | |
805 | 50)) | |
9d0498a2 JB |
806 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
807 | } | |
808 | ||
fbf49ea2 VS |
809 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
810 | { | |
811 | struct drm_i915_private *dev_priv = dev->dev_private; | |
812 | u32 reg = PIPEDSL(pipe); | |
813 | u32 line1, line2; | |
814 | u32 line_mask; | |
815 | ||
816 | if (IS_GEN2(dev)) | |
817 | line_mask = DSL_LINEMASK_GEN2; | |
818 | else | |
819 | line_mask = DSL_LINEMASK_GEN3; | |
820 | ||
821 | line1 = I915_READ(reg) & line_mask; | |
822 | mdelay(5); | |
823 | line2 = I915_READ(reg) & line_mask; | |
824 | ||
825 | return line1 == line2; | |
826 | } | |
827 | ||
ab7ad7f6 KP |
828 | /* |
829 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
9d0498a2 JB |
830 | * @dev: drm device |
831 | * @pipe: pipe to wait for | |
832 | * | |
833 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
834 | * spinning on the vblank interrupt status bit, since we won't actually | |
835 | * see an interrupt when the pipe is disabled. | |
836 | * | |
ab7ad7f6 KP |
837 | * On Gen4 and above: |
838 | * wait for the pipe register state bit to turn off | |
839 | * | |
840 | * Otherwise: | |
841 | * wait for the display line value to settle (it usually | |
842 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 843 | * |
9d0498a2 | 844 | */ |
58e10eb9 | 845 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
9d0498a2 JB |
846 | { |
847 | struct drm_i915_private *dev_priv = dev->dev_private; | |
702e7a56 PZ |
848 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
849 | pipe); | |
ab7ad7f6 KP |
850 | |
851 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 852 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
853 | |
854 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
855 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
856 | 100)) | |
284637d9 | 857 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 858 | } else { |
ab7ad7f6 | 859 | /* Wait for the display line to settle */ |
fbf49ea2 | 860 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 861 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 862 | } |
79e53945 JB |
863 | } |
864 | ||
b0ea7d37 DL |
865 | /* |
866 | * ibx_digital_port_connected - is the specified port connected? | |
867 | * @dev_priv: i915 private structure | |
868 | * @port: the port to test | |
869 | * | |
870 | * Returns true if @port is connected, false otherwise. | |
871 | */ | |
872 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, | |
873 | struct intel_digital_port *port) | |
874 | { | |
875 | u32 bit; | |
876 | ||
c36346e3 DL |
877 | if (HAS_PCH_IBX(dev_priv->dev)) { |
878 | switch(port->port) { | |
879 | case PORT_B: | |
880 | bit = SDE_PORTB_HOTPLUG; | |
881 | break; | |
882 | case PORT_C: | |
883 | bit = SDE_PORTC_HOTPLUG; | |
884 | break; | |
885 | case PORT_D: | |
886 | bit = SDE_PORTD_HOTPLUG; | |
887 | break; | |
888 | default: | |
889 | return true; | |
890 | } | |
891 | } else { | |
892 | switch(port->port) { | |
893 | case PORT_B: | |
894 | bit = SDE_PORTB_HOTPLUG_CPT; | |
895 | break; | |
896 | case PORT_C: | |
897 | bit = SDE_PORTC_HOTPLUG_CPT; | |
898 | break; | |
899 | case PORT_D: | |
900 | bit = SDE_PORTD_HOTPLUG_CPT; | |
901 | break; | |
902 | default: | |
903 | return true; | |
904 | } | |
b0ea7d37 DL |
905 | } |
906 | ||
907 | return I915_READ(SDEISR) & bit; | |
908 | } | |
909 | ||
b24e7179 JB |
910 | static const char *state_string(bool enabled) |
911 | { | |
912 | return enabled ? "on" : "off"; | |
913 | } | |
914 | ||
915 | /* Only for pre-ILK configs */ | |
55607e8a DV |
916 | void assert_pll(struct drm_i915_private *dev_priv, |
917 | enum pipe pipe, bool state) | |
b24e7179 JB |
918 | { |
919 | int reg; | |
920 | u32 val; | |
921 | bool cur_state; | |
922 | ||
923 | reg = DPLL(pipe); | |
924 | val = I915_READ(reg); | |
925 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
926 | WARN(cur_state != state, | |
927 | "PLL state assertion failure (expected %s, current %s)\n", | |
928 | state_string(state), state_string(cur_state)); | |
929 | } | |
b24e7179 | 930 | |
23538ef1 JN |
931 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
932 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
933 | { | |
934 | u32 val; | |
935 | bool cur_state; | |
936 | ||
937 | mutex_lock(&dev_priv->dpio_lock); | |
938 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
939 | mutex_unlock(&dev_priv->dpio_lock); | |
940 | ||
941 | cur_state = val & DSI_PLL_VCO_EN; | |
942 | WARN(cur_state != state, | |
943 | "DSI PLL state assertion failure (expected %s, current %s)\n", | |
944 | state_string(state), state_string(cur_state)); | |
945 | } | |
946 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
947 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
948 | ||
55607e8a | 949 | struct intel_shared_dpll * |
e2b78267 DV |
950 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
951 | { | |
952 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
953 | ||
a43f6e0f | 954 | if (crtc->config.shared_dpll < 0) |
e2b78267 DV |
955 | return NULL; |
956 | ||
a43f6e0f | 957 | return &dev_priv->shared_dplls[crtc->config.shared_dpll]; |
e2b78267 DV |
958 | } |
959 | ||
040484af | 960 | /* For ILK+ */ |
55607e8a DV |
961 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
962 | struct intel_shared_dpll *pll, | |
963 | bool state) | |
040484af | 964 | { |
040484af | 965 | bool cur_state; |
5358901f | 966 | struct intel_dpll_hw_state hw_state; |
040484af | 967 | |
9d82aa17 ED |
968 | if (HAS_PCH_LPT(dev_priv->dev)) { |
969 | DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n"); | |
970 | return; | |
971 | } | |
972 | ||
92b27b08 | 973 | if (WARN (!pll, |
46edb027 | 974 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 975 | return; |
ee7b9f93 | 976 | |
5358901f | 977 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
92b27b08 | 978 | WARN(cur_state != state, |
5358901f DV |
979 | "%s assertion failure (expected %s, current %s)\n", |
980 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 981 | } |
040484af JB |
982 | |
983 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
984 | enum pipe pipe, bool state) | |
985 | { | |
986 | int reg; | |
987 | u32 val; | |
988 | bool cur_state; | |
ad80a810 PZ |
989 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
990 | pipe); | |
040484af | 991 | |
affa9354 PZ |
992 | if (HAS_DDI(dev_priv->dev)) { |
993 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 994 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 995 | val = I915_READ(reg); |
ad80a810 | 996 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
997 | } else { |
998 | reg = FDI_TX_CTL(pipe); | |
999 | val = I915_READ(reg); | |
1000 | cur_state = !!(val & FDI_TX_ENABLE); | |
1001 | } | |
040484af JB |
1002 | WARN(cur_state != state, |
1003 | "FDI TX state assertion failure (expected %s, current %s)\n", | |
1004 | state_string(state), state_string(cur_state)); | |
1005 | } | |
1006 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1007 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1008 | ||
1009 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1010 | enum pipe pipe, bool state) | |
1011 | { | |
1012 | int reg; | |
1013 | u32 val; | |
1014 | bool cur_state; | |
1015 | ||
d63fa0dc PZ |
1016 | reg = FDI_RX_CTL(pipe); |
1017 | val = I915_READ(reg); | |
1018 | cur_state = !!(val & FDI_RX_ENABLE); | |
040484af JB |
1019 | WARN(cur_state != state, |
1020 | "FDI RX state assertion failure (expected %s, current %s)\n", | |
1021 | state_string(state), state_string(cur_state)); | |
1022 | } | |
1023 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1024 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1025 | ||
1026 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1027 | enum pipe pipe) | |
1028 | { | |
1029 | int reg; | |
1030 | u32 val; | |
1031 | ||
1032 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1033 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1034 | return; |
1035 | ||
bf507ef7 | 1036 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1037 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1038 | return; |
1039 | ||
040484af JB |
1040 | reg = FDI_TX_CTL(pipe); |
1041 | val = I915_READ(reg); | |
1042 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); | |
1043 | } | |
1044 | ||
55607e8a DV |
1045 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1046 | enum pipe pipe, bool state) | |
040484af JB |
1047 | { |
1048 | int reg; | |
1049 | u32 val; | |
55607e8a | 1050 | bool cur_state; |
040484af JB |
1051 | |
1052 | reg = FDI_RX_CTL(pipe); | |
1053 | val = I915_READ(reg); | |
55607e8a DV |
1054 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
1055 | WARN(cur_state != state, | |
1056 | "FDI RX PLL assertion failure (expected %s, current %s)\n", | |
1057 | state_string(state), state_string(cur_state)); | |
040484af JB |
1058 | } |
1059 | ||
ea0760cf JB |
1060 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1061 | enum pipe pipe) | |
1062 | { | |
1063 | int pp_reg, lvds_reg; | |
1064 | u32 val; | |
1065 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1066 | bool locked = true; |
ea0760cf JB |
1067 | |
1068 | if (HAS_PCH_SPLIT(dev_priv->dev)) { | |
1069 | pp_reg = PCH_PP_CONTROL; | |
1070 | lvds_reg = PCH_LVDS; | |
1071 | } else { | |
1072 | pp_reg = PP_CONTROL; | |
1073 | lvds_reg = LVDS; | |
1074 | } | |
1075 | ||
1076 | val = I915_READ(pp_reg); | |
1077 | if (!(val & PANEL_POWER_ON) || | |
1078 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) | |
1079 | locked = false; | |
1080 | ||
1081 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) | |
1082 | panel_pipe = PIPE_B; | |
1083 | ||
1084 | WARN(panel_pipe == pipe && locked, | |
1085 | "panel assertion failure, pipe %c regs locked\n", | |
9db4a9c7 | 1086 | pipe_name(pipe)); |
ea0760cf JB |
1087 | } |
1088 | ||
93ce0ba6 JN |
1089 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1090 | enum pipe pipe, bool state) | |
1091 | { | |
1092 | struct drm_device *dev = dev_priv->dev; | |
1093 | bool cur_state; | |
1094 | ||
1095 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
1096 | cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE; | |
1097 | else if (IS_845G(dev) || IS_I865G(dev)) | |
1098 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; | |
1099 | else | |
1100 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; | |
1101 | ||
1102 | WARN(cur_state != state, | |
1103 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", | |
1104 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1105 | } | |
1106 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1107 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1108 | ||
b840d907 JB |
1109 | void assert_pipe(struct drm_i915_private *dev_priv, |
1110 | enum pipe pipe, bool state) | |
b24e7179 JB |
1111 | { |
1112 | int reg; | |
1113 | u32 val; | |
63d7bbe9 | 1114 | bool cur_state; |
702e7a56 PZ |
1115 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1116 | pipe); | |
b24e7179 | 1117 | |
8e636784 DV |
1118 | /* if we need the pipe A quirk it must be always on */ |
1119 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
1120 | state = true; | |
1121 | ||
b97186f0 PZ |
1122 | if (!intel_display_power_enabled(dev_priv->dev, |
1123 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { | |
69310161 PZ |
1124 | cur_state = false; |
1125 | } else { | |
1126 | reg = PIPECONF(cpu_transcoder); | |
1127 | val = I915_READ(reg); | |
1128 | cur_state = !!(val & PIPECONF_ENABLE); | |
1129 | } | |
1130 | ||
63d7bbe9 JB |
1131 | WARN(cur_state != state, |
1132 | "pipe %c assertion failure (expected %s, current %s)\n", | |
9db4a9c7 | 1133 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1134 | } |
1135 | ||
931872fc CW |
1136 | static void assert_plane(struct drm_i915_private *dev_priv, |
1137 | enum plane plane, bool state) | |
b24e7179 JB |
1138 | { |
1139 | int reg; | |
1140 | u32 val; | |
931872fc | 1141 | bool cur_state; |
b24e7179 JB |
1142 | |
1143 | reg = DSPCNTR(plane); | |
1144 | val = I915_READ(reg); | |
931872fc CW |
1145 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1146 | WARN(cur_state != state, | |
1147 | "plane %c assertion failure (expected %s, current %s)\n", | |
1148 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1149 | } |
1150 | ||
931872fc CW |
1151 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1152 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1153 | ||
b24e7179 JB |
1154 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1155 | enum pipe pipe) | |
1156 | { | |
653e1026 | 1157 | struct drm_device *dev = dev_priv->dev; |
b24e7179 JB |
1158 | int reg, i; |
1159 | u32 val; | |
1160 | int cur_pipe; | |
1161 | ||
653e1026 VS |
1162 | /* Primary planes are fixed to pipes on gen4+ */ |
1163 | if (INTEL_INFO(dev)->gen >= 4) { | |
28c05794 AJ |
1164 | reg = DSPCNTR(pipe); |
1165 | val = I915_READ(reg); | |
1166 | WARN((val & DISPLAY_PLANE_ENABLE), | |
1167 | "plane %c assertion failure, should be disabled but not\n", | |
1168 | plane_name(pipe)); | |
19ec1358 | 1169 | return; |
28c05794 | 1170 | } |
19ec1358 | 1171 | |
b24e7179 | 1172 | /* Need to check both planes against the pipe */ |
08e2a7de | 1173 | for_each_pipe(i) { |
b24e7179 JB |
1174 | reg = DSPCNTR(i); |
1175 | val = I915_READ(reg); | |
1176 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1177 | DISPPLANE_SEL_PIPE_SHIFT; | |
1178 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, | |
9db4a9c7 JB |
1179 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1180 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1181 | } |
1182 | } | |
1183 | ||
19332d7a JB |
1184 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1185 | enum pipe pipe) | |
1186 | { | |
20674eef | 1187 | struct drm_device *dev = dev_priv->dev; |
19332d7a JB |
1188 | int reg, i; |
1189 | u32 val; | |
1190 | ||
20674eef | 1191 | if (IS_VALLEYVIEW(dev)) { |
22d3fd46 | 1192 | for (i = 0; i < INTEL_INFO(dev)->num_sprites; i++) { |
20674eef VS |
1193 | reg = SPCNTR(pipe, i); |
1194 | val = I915_READ(reg); | |
1195 | WARN((val & SP_ENABLE), | |
1196 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", | |
1197 | sprite_name(pipe, i), pipe_name(pipe)); | |
1198 | } | |
1199 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
1200 | reg = SPRCTL(pipe); | |
19332d7a | 1201 | val = I915_READ(reg); |
20674eef | 1202 | WARN((val & SPRITE_ENABLE), |
06da8da2 | 1203 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1204 | plane_name(pipe), pipe_name(pipe)); |
1205 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1206 | reg = DVSCNTR(pipe); | |
19332d7a | 1207 | val = I915_READ(reg); |
20674eef | 1208 | WARN((val & DVS_ENABLE), |
06da8da2 | 1209 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1210 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1211 | } |
1212 | } | |
1213 | ||
89eff4be | 1214 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1215 | { |
1216 | u32 val; | |
1217 | bool enabled; | |
1218 | ||
89eff4be | 1219 | WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1220 | |
92f2584a JB |
1221 | val = I915_READ(PCH_DREF_CONTROL); |
1222 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1223 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
1224 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); | |
1225 | } | |
1226 | ||
ab9412ba DV |
1227 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1228 | enum pipe pipe) | |
92f2584a JB |
1229 | { |
1230 | int reg; | |
1231 | u32 val; | |
1232 | bool enabled; | |
1233 | ||
ab9412ba | 1234 | reg = PCH_TRANSCONF(pipe); |
92f2584a JB |
1235 | val = I915_READ(reg); |
1236 | enabled = !!(val & TRANS_ENABLE); | |
9db4a9c7 JB |
1237 | WARN(enabled, |
1238 | "transcoder assertion failed, should be off on pipe %c but is still active\n", | |
1239 | pipe_name(pipe)); | |
92f2584a JB |
1240 | } |
1241 | ||
4e634389 KP |
1242 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1243 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1244 | { |
1245 | if ((val & DP_PORT_EN) == 0) | |
1246 | return false; | |
1247 | ||
1248 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1249 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1250 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1251 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1252 | return false; | |
1253 | } else { | |
1254 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1255 | return false; | |
1256 | } | |
1257 | return true; | |
1258 | } | |
1259 | ||
1519b995 KP |
1260 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1261 | enum pipe pipe, u32 val) | |
1262 | { | |
dc0fa718 | 1263 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1264 | return false; |
1265 | ||
1266 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1267 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 KP |
1268 | return false; |
1269 | } else { | |
dc0fa718 | 1270 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1271 | return false; |
1272 | } | |
1273 | return true; | |
1274 | } | |
1275 | ||
1276 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1277 | enum pipe pipe, u32 val) | |
1278 | { | |
1279 | if ((val & LVDS_PORT_EN) == 0) | |
1280 | return false; | |
1281 | ||
1282 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1283 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1284 | return false; | |
1285 | } else { | |
1286 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1287 | return false; | |
1288 | } | |
1289 | return true; | |
1290 | } | |
1291 | ||
1292 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1293 | enum pipe pipe, u32 val) | |
1294 | { | |
1295 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1296 | return false; | |
1297 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1298 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1299 | return false; | |
1300 | } else { | |
1301 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1302 | return false; | |
1303 | } | |
1304 | return true; | |
1305 | } | |
1306 | ||
291906f1 | 1307 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1308 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1309 | { |
47a05eca | 1310 | u32 val = I915_READ(reg); |
4e634389 | 1311 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1312 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1313 | reg, pipe_name(pipe)); |
de9a35ab | 1314 | |
75c5da27 DV |
1315 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
1316 | && (val & DP_PIPEB_SELECT), | |
de9a35ab | 1317 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1318 | } |
1319 | ||
1320 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1321 | enum pipe pipe, int reg) | |
1322 | { | |
47a05eca | 1323 | u32 val = I915_READ(reg); |
b70ad586 | 1324 | WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1325 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1326 | reg, pipe_name(pipe)); |
de9a35ab | 1327 | |
dc0fa718 | 1328 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1329 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1330 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1331 | } |
1332 | ||
1333 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1334 | enum pipe pipe) | |
1335 | { | |
1336 | int reg; | |
1337 | u32 val; | |
291906f1 | 1338 | |
f0575e92 KP |
1339 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1340 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1341 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1342 | |
1343 | reg = PCH_ADPA; | |
1344 | val = I915_READ(reg); | |
b70ad586 | 1345 | WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1346 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1347 | pipe_name(pipe)); |
291906f1 JB |
1348 | |
1349 | reg = PCH_LVDS; | |
1350 | val = I915_READ(reg); | |
b70ad586 | 1351 | WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1352 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1353 | pipe_name(pipe)); |
291906f1 | 1354 | |
e2debe91 PZ |
1355 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1356 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1357 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1358 | } |
1359 | ||
40e9cf64 JB |
1360 | static void intel_init_dpio(struct drm_device *dev) |
1361 | { | |
1362 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1363 | ||
1364 | if (!IS_VALLEYVIEW(dev)) | |
1365 | return; | |
1366 | ||
e4607fcf | 1367 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; |
5382f5f3 JB |
1368 | } |
1369 | ||
1370 | static void intel_reset_dpio(struct drm_device *dev) | |
1371 | { | |
1372 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1373 | ||
1374 | if (!IS_VALLEYVIEW(dev)) | |
1375 | return; | |
1376 | ||
e5cbfbfb ID |
1377 | /* |
1378 | * Enable the CRI clock source so we can get at the display and the | |
1379 | * reference clock for VGA hotplug / manual detection. | |
1380 | */ | |
404faabc | 1381 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | |
e5cbfbfb | 1382 | DPLL_REFA_CLK_ENABLE_VLV | |
404faabc ID |
1383 | DPLL_INTEGRATED_CRI_CLK_VLV); |
1384 | ||
40e9cf64 JB |
1385 | /* |
1386 | * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - | |
1387 | * 6. De-assert cmn_reset/side_reset. Same as VLV X0. | |
1388 | * a. GUnit 0x2110 bit[0] set to 1 (def 0) | |
1389 | * b. The other bits such as sfr settings / modesel may all be set | |
1390 | * to 0. | |
1391 | * | |
1392 | * This should only be done on init and resume from S3 with both | |
1393 | * PLLs disabled, or we risk losing DPIO and PLL synchronization. | |
1394 | */ | |
1395 | I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); | |
1396 | } | |
1397 | ||
426115cf | 1398 | static void vlv_enable_pll(struct intel_crtc *crtc) |
87442f73 | 1399 | { |
426115cf DV |
1400 | struct drm_device *dev = crtc->base.dev; |
1401 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1402 | int reg = DPLL(crtc->pipe); | |
1403 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
87442f73 | 1404 | |
426115cf | 1405 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 DV |
1406 | |
1407 | /* No really, not for ILK+ */ | |
1408 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
1409 | ||
1410 | /* PLL is protected by panel, make sure we can write it */ | |
1411 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) | |
426115cf | 1412 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1413 | |
426115cf DV |
1414 | I915_WRITE(reg, dpll); |
1415 | POSTING_READ(reg); | |
1416 | udelay(150); | |
1417 | ||
1418 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1419 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1420 | ||
1421 | I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md); | |
1422 | POSTING_READ(DPLL_MD(crtc->pipe)); | |
87442f73 DV |
1423 | |
1424 | /* We do this three times for luck */ | |
426115cf | 1425 | I915_WRITE(reg, dpll); |
87442f73 DV |
1426 | POSTING_READ(reg); |
1427 | udelay(150); /* wait for warmup */ | |
426115cf | 1428 | I915_WRITE(reg, dpll); |
87442f73 DV |
1429 | POSTING_READ(reg); |
1430 | udelay(150); /* wait for warmup */ | |
426115cf | 1431 | I915_WRITE(reg, dpll); |
87442f73 DV |
1432 | POSTING_READ(reg); |
1433 | udelay(150); /* wait for warmup */ | |
1434 | } | |
1435 | ||
66e3d5c0 | 1436 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1437 | { |
66e3d5c0 DV |
1438 | struct drm_device *dev = crtc->base.dev; |
1439 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1440 | int reg = DPLL(crtc->pipe); | |
1441 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
63d7bbe9 | 1442 | |
66e3d5c0 | 1443 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1444 | |
63d7bbe9 | 1445 | /* No really, not for ILK+ */ |
3d13ef2e | 1446 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1447 | |
1448 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1449 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1450 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1451 | |
66e3d5c0 DV |
1452 | I915_WRITE(reg, dpll); |
1453 | ||
1454 | /* Wait for the clocks to stabilize. */ | |
1455 | POSTING_READ(reg); | |
1456 | udelay(150); | |
1457 | ||
1458 | if (INTEL_INFO(dev)->gen >= 4) { | |
1459 | I915_WRITE(DPLL_MD(crtc->pipe), | |
1460 | crtc->config.dpll_hw_state.dpll_md); | |
1461 | } else { | |
1462 | /* The pixel multiplier can only be updated once the | |
1463 | * DPLL is enabled and the clocks are stable. | |
1464 | * | |
1465 | * So write it again. | |
1466 | */ | |
1467 | I915_WRITE(reg, dpll); | |
1468 | } | |
63d7bbe9 JB |
1469 | |
1470 | /* We do this three times for luck */ | |
66e3d5c0 | 1471 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1472 | POSTING_READ(reg); |
1473 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1474 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1475 | POSTING_READ(reg); |
1476 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1477 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1478 | POSTING_READ(reg); |
1479 | udelay(150); /* wait for warmup */ | |
1480 | } | |
1481 | ||
1482 | /** | |
50b44a44 | 1483 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1484 | * @dev_priv: i915 private structure |
1485 | * @pipe: pipe PLL to disable | |
1486 | * | |
1487 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1488 | * | |
1489 | * Note! This is for pre-ILK only. | |
1490 | */ | |
50b44a44 | 1491 | static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
63d7bbe9 | 1492 | { |
63d7bbe9 JB |
1493 | /* Don't disable pipe A or pipe A PLLs if needed */ |
1494 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1495 | return; | |
1496 | ||
1497 | /* Make sure the pipe isn't still relying on us */ | |
1498 | assert_pipe_disabled(dev_priv, pipe); | |
1499 | ||
50b44a44 DV |
1500 | I915_WRITE(DPLL(pipe), 0); |
1501 | POSTING_READ(DPLL(pipe)); | |
63d7bbe9 JB |
1502 | } |
1503 | ||
f6071166 JB |
1504 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1505 | { | |
1506 | u32 val = 0; | |
1507 | ||
1508 | /* Make sure the pipe isn't still relying on us */ | |
1509 | assert_pipe_disabled(dev_priv, pipe); | |
1510 | ||
e5cbfbfb ID |
1511 | /* |
1512 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1513 | * The latter is needed for VGA hotplug / manual detection. | |
1514 | */ | |
f6071166 | 1515 | if (pipe == PIPE_B) |
e5cbfbfb | 1516 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; |
f6071166 JB |
1517 | I915_WRITE(DPLL(pipe), val); |
1518 | POSTING_READ(DPLL(pipe)); | |
1519 | } | |
1520 | ||
e4607fcf CML |
1521 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
1522 | struct intel_digital_port *dport) | |
89b667f8 JB |
1523 | { |
1524 | u32 port_mask; | |
1525 | ||
e4607fcf CML |
1526 | switch (dport->port) { |
1527 | case PORT_B: | |
89b667f8 | 1528 | port_mask = DPLL_PORTB_READY_MASK; |
e4607fcf CML |
1529 | break; |
1530 | case PORT_C: | |
89b667f8 | 1531 | port_mask = DPLL_PORTC_READY_MASK; |
e4607fcf CML |
1532 | break; |
1533 | default: | |
1534 | BUG(); | |
1535 | } | |
89b667f8 JB |
1536 | |
1537 | if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000)) | |
1538 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", | |
be46ffd4 | 1539 | port_name(dport->port), I915_READ(DPLL(0))); |
89b667f8 JB |
1540 | } |
1541 | ||
92f2584a | 1542 | /** |
e72f9fbf | 1543 | * ironlake_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1544 | * @dev_priv: i915 private structure |
1545 | * @pipe: pipe PLL to enable | |
1546 | * | |
1547 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1548 | * drives the transcoder clock. | |
1549 | */ | |
e2b78267 | 1550 | static void ironlake_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1551 | { |
3d13ef2e DL |
1552 | struct drm_device *dev = crtc->base.dev; |
1553 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1554 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1555 | |
48da64a8 | 1556 | /* PCH PLLs only available on ILK, SNB and IVB */ |
3d13ef2e | 1557 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
87a875bb | 1558 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1559 | return; |
1560 | ||
1561 | if (WARN_ON(pll->refcount == 0)) | |
1562 | return; | |
ee7b9f93 | 1563 | |
46edb027 DV |
1564 | DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n", |
1565 | pll->name, pll->active, pll->on, | |
e2b78267 | 1566 | crtc->base.base.id); |
92f2584a | 1567 | |
cdbd2316 DV |
1568 | if (pll->active++) { |
1569 | WARN_ON(!pll->on); | |
e9d6944e | 1570 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1571 | return; |
1572 | } | |
f4a091c7 | 1573 | WARN_ON(pll->on); |
ee7b9f93 | 1574 | |
46edb027 | 1575 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1576 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1577 | pll->on = true; |
92f2584a JB |
1578 | } |
1579 | ||
e2b78267 | 1580 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1581 | { |
3d13ef2e DL |
1582 | struct drm_device *dev = crtc->base.dev; |
1583 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1584 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1585 | |
92f2584a | 1586 | /* PCH only available on ILK+ */ |
3d13ef2e | 1587 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
87a875bb | 1588 | if (WARN_ON(pll == NULL)) |
ee7b9f93 | 1589 | return; |
92f2584a | 1590 | |
48da64a8 CW |
1591 | if (WARN_ON(pll->refcount == 0)) |
1592 | return; | |
7a419866 | 1593 | |
46edb027 DV |
1594 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1595 | pll->name, pll->active, pll->on, | |
e2b78267 | 1596 | crtc->base.base.id); |
7a419866 | 1597 | |
48da64a8 | 1598 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1599 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1600 | return; |
1601 | } | |
1602 | ||
e9d6944e | 1603 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1604 | WARN_ON(!pll->on); |
cdbd2316 | 1605 | if (--pll->active) |
7a419866 | 1606 | return; |
ee7b9f93 | 1607 | |
46edb027 | 1608 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1609 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1610 | pll->on = false; |
92f2584a JB |
1611 | } |
1612 | ||
b8a4f404 PZ |
1613 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1614 | enum pipe pipe) | |
040484af | 1615 | { |
23670b32 | 1616 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1617 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1618 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
23670b32 | 1619 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1620 | |
1621 | /* PCH only available on ILK+ */ | |
3d13ef2e | 1622 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
040484af JB |
1623 | |
1624 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1625 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1626 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1627 | |
1628 | /* FDI must be feeding us bits for PCH ports */ | |
1629 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1630 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1631 | ||
23670b32 DV |
1632 | if (HAS_PCH_CPT(dev)) { |
1633 | /* Workaround: Set the timing override bit before enabling the | |
1634 | * pch transcoder. */ | |
1635 | reg = TRANS_CHICKEN2(pipe); | |
1636 | val = I915_READ(reg); | |
1637 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1638 | I915_WRITE(reg, val); | |
59c859d6 | 1639 | } |
23670b32 | 1640 | |
ab9412ba | 1641 | reg = PCH_TRANSCONF(pipe); |
040484af | 1642 | val = I915_READ(reg); |
5f7f726d | 1643 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1644 | |
1645 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1646 | /* | |
1647 | * make the BPC in transcoder be consistent with | |
1648 | * that in pipeconf reg. | |
1649 | */ | |
dfd07d72 DV |
1650 | val &= ~PIPECONF_BPC_MASK; |
1651 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1652 | } |
5f7f726d PZ |
1653 | |
1654 | val &= ~TRANS_INTERLACE_MASK; | |
1655 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 PZ |
1656 | if (HAS_PCH_IBX(dev_priv->dev) && |
1657 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) | |
1658 | val |= TRANS_LEGACY_INTERLACED_ILK; | |
1659 | else | |
1660 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1661 | else |
1662 | val |= TRANS_PROGRESSIVE; | |
1663 | ||
040484af JB |
1664 | I915_WRITE(reg, val | TRANS_ENABLE); |
1665 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 1666 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1667 | } |
1668 | ||
8fb033d7 | 1669 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1670 | enum transcoder cpu_transcoder) |
040484af | 1671 | { |
8fb033d7 | 1672 | u32 val, pipeconf_val; |
8fb033d7 PZ |
1673 | |
1674 | /* PCH only available on ILK+ */ | |
3d13ef2e | 1675 | BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5); |
8fb033d7 | 1676 | |
8fb033d7 | 1677 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1678 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1679 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1680 | |
223a6fdf PZ |
1681 | /* Workaround: set timing override bit. */ |
1682 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1683 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
1684 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1685 | ||
25f3ef11 | 1686 | val = TRANS_ENABLE; |
937bb610 | 1687 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1688 | |
9a76b1c6 PZ |
1689 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1690 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1691 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1692 | else |
1693 | val |= TRANS_PROGRESSIVE; | |
1694 | ||
ab9412ba DV |
1695 | I915_WRITE(LPT_TRANSCONF, val); |
1696 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 1697 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1698 | } |
1699 | ||
b8a4f404 PZ |
1700 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1701 | enum pipe pipe) | |
040484af | 1702 | { |
23670b32 DV |
1703 | struct drm_device *dev = dev_priv->dev; |
1704 | uint32_t reg, val; | |
040484af JB |
1705 | |
1706 | /* FDI relies on the transcoder */ | |
1707 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1708 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1709 | ||
291906f1 JB |
1710 | /* Ports must be off as well */ |
1711 | assert_pch_ports_disabled(dev_priv, pipe); | |
1712 | ||
ab9412ba | 1713 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1714 | val = I915_READ(reg); |
1715 | val &= ~TRANS_ENABLE; | |
1716 | I915_WRITE(reg, val); | |
1717 | /* wait for PCH transcoder off, transcoder state */ | |
1718 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 1719 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 DV |
1720 | |
1721 | if (!HAS_PCH_IBX(dev)) { | |
1722 | /* Workaround: Clear the timing override chicken bit again. */ | |
1723 | reg = TRANS_CHICKEN2(pipe); | |
1724 | val = I915_READ(reg); | |
1725 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1726 | I915_WRITE(reg, val); | |
1727 | } | |
040484af JB |
1728 | } |
1729 | ||
ab4d966c | 1730 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1731 | { |
8fb033d7 PZ |
1732 | u32 val; |
1733 | ||
ab9412ba | 1734 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1735 | val &= ~TRANS_ENABLE; |
ab9412ba | 1736 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1737 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 1738 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 1739 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1740 | |
1741 | /* Workaround: clear timing override bit. */ | |
1742 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1743 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 1744 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
1745 | } |
1746 | ||
b24e7179 | 1747 | /** |
309cfea8 | 1748 | * intel_enable_pipe - enable a pipe, asserting requirements |
b24e7179 JB |
1749 | * @dev_priv: i915 private structure |
1750 | * @pipe: pipe to enable | |
040484af | 1751 | * @pch_port: on ILK+, is this pipe driving a PCH port or not |
b24e7179 JB |
1752 | * |
1753 | * Enable @pipe, making sure that various hardware specific requirements | |
1754 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. | |
1755 | * | |
1756 | * @pipe should be %PIPE_A or %PIPE_B. | |
1757 | * | |
1758 | * Will wait until the pipe is actually running (i.e. first vblank) before | |
1759 | * returning. | |
1760 | */ | |
040484af | 1761 | static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
23538ef1 | 1762 | bool pch_port, bool dsi) |
b24e7179 | 1763 | { |
702e7a56 PZ |
1764 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1765 | pipe); | |
1a240d4d | 1766 | enum pipe pch_transcoder; |
b24e7179 JB |
1767 | int reg; |
1768 | u32 val; | |
1769 | ||
58c6eaa2 | 1770 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 1771 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
1772 | assert_sprites_disabled(dev_priv, pipe); |
1773 | ||
681e5811 | 1774 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
1775 | pch_transcoder = TRANSCODER_A; |
1776 | else | |
1777 | pch_transcoder = pipe; | |
1778 | ||
b24e7179 JB |
1779 | /* |
1780 | * A pipe without a PLL won't actually be able to drive bits from | |
1781 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1782 | * need the check. | |
1783 | */ | |
1784 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
23538ef1 JN |
1785 | if (dsi) |
1786 | assert_dsi_pll_enabled(dev_priv); | |
1787 | else | |
1788 | assert_pll_enabled(dev_priv, pipe); | |
040484af JB |
1789 | else { |
1790 | if (pch_port) { | |
1791 | /* if driving the PCH, we need FDI enabled */ | |
cc391bbb | 1792 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
1793 | assert_fdi_tx_pll_enabled(dev_priv, |
1794 | (enum pipe) cpu_transcoder); | |
040484af JB |
1795 | } |
1796 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1797 | } | |
b24e7179 | 1798 | |
702e7a56 | 1799 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1800 | val = I915_READ(reg); |
00d70b15 CW |
1801 | if (val & PIPECONF_ENABLE) |
1802 | return; | |
1803 | ||
1804 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
b24e7179 JB |
1805 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1806 | } | |
1807 | ||
1808 | /** | |
309cfea8 | 1809 | * intel_disable_pipe - disable a pipe, asserting requirements |
b24e7179 JB |
1810 | * @dev_priv: i915 private structure |
1811 | * @pipe: pipe to disable | |
1812 | * | |
1813 | * Disable @pipe, making sure that various hardware specific requirements | |
1814 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. | |
1815 | * | |
1816 | * @pipe should be %PIPE_A or %PIPE_B. | |
1817 | * | |
1818 | * Will wait until the pipe has shut down before returning. | |
1819 | */ | |
1820 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, | |
1821 | enum pipe pipe) | |
1822 | { | |
702e7a56 PZ |
1823 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1824 | pipe); | |
b24e7179 JB |
1825 | int reg; |
1826 | u32 val; | |
1827 | ||
1828 | /* | |
1829 | * Make sure planes won't keep trying to pump pixels to us, | |
1830 | * or we might hang the display. | |
1831 | */ | |
1832 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 1833 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 1834 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 JB |
1835 | |
1836 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
1837 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1838 | return; | |
1839 | ||
702e7a56 | 1840 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1841 | val = I915_READ(reg); |
00d70b15 CW |
1842 | if ((val & PIPECONF_ENABLE) == 0) |
1843 | return; | |
1844 | ||
1845 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); | |
b24e7179 JB |
1846 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
1847 | } | |
1848 | ||
d74362c9 KP |
1849 | /* |
1850 | * Plane regs are double buffered, going from enabled->disabled needs a | |
1851 | * trigger in order to latch. The display address reg provides this. | |
1852 | */ | |
1dba99f4 VS |
1853 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
1854 | enum plane plane) | |
d74362c9 | 1855 | { |
3d13ef2e DL |
1856 | struct drm_device *dev = dev_priv->dev; |
1857 | u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); | |
1dba99f4 VS |
1858 | |
1859 | I915_WRITE(reg, I915_READ(reg)); | |
1860 | POSTING_READ(reg); | |
d74362c9 KP |
1861 | } |
1862 | ||
b24e7179 | 1863 | /** |
d1de00ef | 1864 | * intel_enable_primary_plane - enable the primary plane on a given pipe |
b24e7179 JB |
1865 | * @dev_priv: i915 private structure |
1866 | * @plane: plane to enable | |
1867 | * @pipe: pipe being fed | |
1868 | * | |
1869 | * Enable @plane on @pipe, making sure that @pipe is running first. | |
1870 | */ | |
d1de00ef VS |
1871 | static void intel_enable_primary_plane(struct drm_i915_private *dev_priv, |
1872 | enum plane plane, enum pipe pipe) | |
b24e7179 | 1873 | { |
939c2fe8 VS |
1874 | struct intel_crtc *intel_crtc = |
1875 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
b24e7179 JB |
1876 | int reg; |
1877 | u32 val; | |
1878 | ||
1879 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
1880 | assert_pipe_enabled(dev_priv, pipe); | |
1881 | ||
4c445e0e | 1882 | WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n"); |
0037f71c | 1883 | |
4c445e0e | 1884 | intel_crtc->primary_enabled = true; |
939c2fe8 | 1885 | |
b24e7179 JB |
1886 | reg = DSPCNTR(plane); |
1887 | val = I915_READ(reg); | |
00d70b15 CW |
1888 | if (val & DISPLAY_PLANE_ENABLE) |
1889 | return; | |
1890 | ||
1891 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); | |
1dba99f4 | 1892 | intel_flush_primary_plane(dev_priv, plane); |
b24e7179 JB |
1893 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1894 | } | |
1895 | ||
b24e7179 | 1896 | /** |
d1de00ef | 1897 | * intel_disable_primary_plane - disable the primary plane |
b24e7179 JB |
1898 | * @dev_priv: i915 private structure |
1899 | * @plane: plane to disable | |
1900 | * @pipe: pipe consuming the data | |
1901 | * | |
1902 | * Disable @plane; should be an independent operation. | |
1903 | */ | |
d1de00ef VS |
1904 | static void intel_disable_primary_plane(struct drm_i915_private *dev_priv, |
1905 | enum plane plane, enum pipe pipe) | |
b24e7179 | 1906 | { |
939c2fe8 VS |
1907 | struct intel_crtc *intel_crtc = |
1908 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
b24e7179 JB |
1909 | int reg; |
1910 | u32 val; | |
1911 | ||
4c445e0e | 1912 | WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n"); |
0037f71c | 1913 | |
4c445e0e | 1914 | intel_crtc->primary_enabled = false; |
939c2fe8 | 1915 | |
b24e7179 JB |
1916 | reg = DSPCNTR(plane); |
1917 | val = I915_READ(reg); | |
00d70b15 CW |
1918 | if ((val & DISPLAY_PLANE_ENABLE) == 0) |
1919 | return; | |
1920 | ||
1921 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); | |
1dba99f4 | 1922 | intel_flush_primary_plane(dev_priv, plane); |
b24e7179 JB |
1923 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1924 | } | |
1925 | ||
693db184 CW |
1926 | static bool need_vtd_wa(struct drm_device *dev) |
1927 | { | |
1928 | #ifdef CONFIG_INTEL_IOMMU | |
1929 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
1930 | return true; | |
1931 | #endif | |
1932 | return false; | |
1933 | } | |
1934 | ||
127bd2ac | 1935 | int |
48b956c5 | 1936 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 1937 | struct drm_i915_gem_object *obj, |
919926ae | 1938 | struct intel_ring_buffer *pipelined) |
6b95a207 | 1939 | { |
ce453d81 | 1940 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
1941 | u32 alignment; |
1942 | int ret; | |
1943 | ||
05394f39 | 1944 | switch (obj->tiling_mode) { |
6b95a207 | 1945 | case I915_TILING_NONE: |
534843da CW |
1946 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
1947 | alignment = 128 * 1024; | |
a6c45cf0 | 1948 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
1949 | alignment = 4 * 1024; |
1950 | else | |
1951 | alignment = 64 * 1024; | |
6b95a207 KH |
1952 | break; |
1953 | case I915_TILING_X: | |
1954 | /* pin() will align the object as required by fence */ | |
1955 | alignment = 0; | |
1956 | break; | |
1957 | case I915_TILING_Y: | |
80075d49 | 1958 | WARN(1, "Y tiled bo slipped through, driver bug!\n"); |
6b95a207 KH |
1959 | return -EINVAL; |
1960 | default: | |
1961 | BUG(); | |
1962 | } | |
1963 | ||
693db184 CW |
1964 | /* Note that the w/a also requires 64 PTE of padding following the |
1965 | * bo. We currently fill all unused PTE with the shadow page and so | |
1966 | * we should always have valid PTE following the scanout preventing | |
1967 | * the VT-d warning. | |
1968 | */ | |
1969 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
1970 | alignment = 256 * 1024; | |
1971 | ||
ce453d81 | 1972 | dev_priv->mm.interruptible = false; |
2da3b9b9 | 1973 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
48b956c5 | 1974 | if (ret) |
ce453d81 | 1975 | goto err_interruptible; |
6b95a207 KH |
1976 | |
1977 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
1978 | * fence, whereas 965+ only requires a fence if using | |
1979 | * framebuffer compression. For simplicity, we always install | |
1980 | * a fence as the cost is not that onerous. | |
1981 | */ | |
06d98131 | 1982 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
1983 | if (ret) |
1984 | goto err_unpin; | |
1690e1eb | 1985 | |
9a5a53b3 | 1986 | i915_gem_object_pin_fence(obj); |
6b95a207 | 1987 | |
ce453d81 | 1988 | dev_priv->mm.interruptible = true; |
6b95a207 | 1989 | return 0; |
48b956c5 CW |
1990 | |
1991 | err_unpin: | |
cc98b413 | 1992 | i915_gem_object_unpin_from_display_plane(obj); |
ce453d81 CW |
1993 | err_interruptible: |
1994 | dev_priv->mm.interruptible = true; | |
48b956c5 | 1995 | return ret; |
6b95a207 KH |
1996 | } |
1997 | ||
1690e1eb CW |
1998 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
1999 | { | |
2000 | i915_gem_object_unpin_fence(obj); | |
cc98b413 | 2001 | i915_gem_object_unpin_from_display_plane(obj); |
1690e1eb CW |
2002 | } |
2003 | ||
c2c75131 DV |
2004 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2005 | * is assumed to be a power-of-two. */ | |
bc752862 CW |
2006 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
2007 | unsigned int tiling_mode, | |
2008 | unsigned int cpp, | |
2009 | unsigned int pitch) | |
c2c75131 | 2010 | { |
bc752862 CW |
2011 | if (tiling_mode != I915_TILING_NONE) { |
2012 | unsigned int tile_rows, tiles; | |
c2c75131 | 2013 | |
bc752862 CW |
2014 | tile_rows = *y / 8; |
2015 | *y %= 8; | |
c2c75131 | 2016 | |
bc752862 CW |
2017 | tiles = *x / (512/cpp); |
2018 | *x %= 512/cpp; | |
2019 | ||
2020 | return tile_rows * pitch * 8 + tiles * 4096; | |
2021 | } else { | |
2022 | unsigned int offset; | |
2023 | ||
2024 | offset = *y * pitch + *x * cpp; | |
2025 | *y = 0; | |
2026 | *x = (offset & 4095) / cpp; | |
2027 | return offset & -4096; | |
2028 | } | |
c2c75131 DV |
2029 | } |
2030 | ||
17638cd6 JB |
2031 | static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
2032 | int x, int y) | |
81255565 JB |
2033 | { |
2034 | struct drm_device *dev = crtc->dev; | |
2035 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2036 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2037 | struct intel_framebuffer *intel_fb; | |
05394f39 | 2038 | struct drm_i915_gem_object *obj; |
81255565 | 2039 | int plane = intel_crtc->plane; |
e506a0c6 | 2040 | unsigned long linear_offset; |
81255565 | 2041 | u32 dspcntr; |
5eddb70b | 2042 | u32 reg; |
81255565 JB |
2043 | |
2044 | switch (plane) { | |
2045 | case 0: | |
2046 | case 1: | |
2047 | break; | |
2048 | default: | |
84f44ce7 | 2049 | DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane)); |
81255565 JB |
2050 | return -EINVAL; |
2051 | } | |
2052 | ||
2053 | intel_fb = to_intel_framebuffer(fb); | |
2054 | obj = intel_fb->obj; | |
81255565 | 2055 | |
5eddb70b CW |
2056 | reg = DSPCNTR(plane); |
2057 | dspcntr = I915_READ(reg); | |
81255565 JB |
2058 | /* Mask out pixel format bits in case we change it */ |
2059 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
2060 | switch (fb->pixel_format) { |
2061 | case DRM_FORMAT_C8: | |
81255565 JB |
2062 | dspcntr |= DISPPLANE_8BPP; |
2063 | break; | |
57779d06 VS |
2064 | case DRM_FORMAT_XRGB1555: |
2065 | case DRM_FORMAT_ARGB1555: | |
2066 | dspcntr |= DISPPLANE_BGRX555; | |
81255565 | 2067 | break; |
57779d06 VS |
2068 | case DRM_FORMAT_RGB565: |
2069 | dspcntr |= DISPPLANE_BGRX565; | |
2070 | break; | |
2071 | case DRM_FORMAT_XRGB8888: | |
2072 | case DRM_FORMAT_ARGB8888: | |
2073 | dspcntr |= DISPPLANE_BGRX888; | |
2074 | break; | |
2075 | case DRM_FORMAT_XBGR8888: | |
2076 | case DRM_FORMAT_ABGR8888: | |
2077 | dspcntr |= DISPPLANE_RGBX888; | |
2078 | break; | |
2079 | case DRM_FORMAT_XRGB2101010: | |
2080 | case DRM_FORMAT_ARGB2101010: | |
2081 | dspcntr |= DISPPLANE_BGRX101010; | |
2082 | break; | |
2083 | case DRM_FORMAT_XBGR2101010: | |
2084 | case DRM_FORMAT_ABGR2101010: | |
2085 | dspcntr |= DISPPLANE_RGBX101010; | |
81255565 JB |
2086 | break; |
2087 | default: | |
baba133a | 2088 | BUG(); |
81255565 | 2089 | } |
57779d06 | 2090 | |
a6c45cf0 | 2091 | if (INTEL_INFO(dev)->gen >= 4) { |
05394f39 | 2092 | if (obj->tiling_mode != I915_TILING_NONE) |
81255565 JB |
2093 | dspcntr |= DISPPLANE_TILED; |
2094 | else | |
2095 | dspcntr &= ~DISPPLANE_TILED; | |
2096 | } | |
2097 | ||
de1aa629 VS |
2098 | if (IS_G4X(dev)) |
2099 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2100 | ||
5eddb70b | 2101 | I915_WRITE(reg, dspcntr); |
81255565 | 2102 | |
e506a0c6 | 2103 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
81255565 | 2104 | |
c2c75131 DV |
2105 | if (INTEL_INFO(dev)->gen >= 4) { |
2106 | intel_crtc->dspaddr_offset = | |
bc752862 CW |
2107 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2108 | fb->bits_per_pixel / 8, | |
2109 | fb->pitches[0]); | |
c2c75131 DV |
2110 | linear_offset -= intel_crtc->dspaddr_offset; |
2111 | } else { | |
e506a0c6 | 2112 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2113 | } |
e506a0c6 | 2114 | |
f343c5f6 BW |
2115 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2116 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2117 | fb->pitches[0]); | |
01f2c773 | 2118 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2119 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2120 | I915_WRITE(DSPSURF(plane), |
2121 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2122 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2123 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2124 | } else |
f343c5f6 | 2125 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2126 | POSTING_READ(reg); |
81255565 | 2127 | |
17638cd6 JB |
2128 | return 0; |
2129 | } | |
2130 | ||
2131 | static int ironlake_update_plane(struct drm_crtc *crtc, | |
2132 | struct drm_framebuffer *fb, int x, int y) | |
2133 | { | |
2134 | struct drm_device *dev = crtc->dev; | |
2135 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2136 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2137 | struct intel_framebuffer *intel_fb; | |
2138 | struct drm_i915_gem_object *obj; | |
2139 | int plane = intel_crtc->plane; | |
e506a0c6 | 2140 | unsigned long linear_offset; |
17638cd6 JB |
2141 | u32 dspcntr; |
2142 | u32 reg; | |
2143 | ||
2144 | switch (plane) { | |
2145 | case 0: | |
2146 | case 1: | |
27f8227b | 2147 | case 2: |
17638cd6 JB |
2148 | break; |
2149 | default: | |
84f44ce7 | 2150 | DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane)); |
17638cd6 JB |
2151 | return -EINVAL; |
2152 | } | |
2153 | ||
2154 | intel_fb = to_intel_framebuffer(fb); | |
2155 | obj = intel_fb->obj; | |
2156 | ||
2157 | reg = DSPCNTR(plane); | |
2158 | dspcntr = I915_READ(reg); | |
2159 | /* Mask out pixel format bits in case we change it */ | |
2160 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
2161 | switch (fb->pixel_format) { |
2162 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2163 | dspcntr |= DISPPLANE_8BPP; |
2164 | break; | |
57779d06 VS |
2165 | case DRM_FORMAT_RGB565: |
2166 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2167 | break; |
57779d06 VS |
2168 | case DRM_FORMAT_XRGB8888: |
2169 | case DRM_FORMAT_ARGB8888: | |
2170 | dspcntr |= DISPPLANE_BGRX888; | |
2171 | break; | |
2172 | case DRM_FORMAT_XBGR8888: | |
2173 | case DRM_FORMAT_ABGR8888: | |
2174 | dspcntr |= DISPPLANE_RGBX888; | |
2175 | break; | |
2176 | case DRM_FORMAT_XRGB2101010: | |
2177 | case DRM_FORMAT_ARGB2101010: | |
2178 | dspcntr |= DISPPLANE_BGRX101010; | |
2179 | break; | |
2180 | case DRM_FORMAT_XBGR2101010: | |
2181 | case DRM_FORMAT_ABGR2101010: | |
2182 | dspcntr |= DISPPLANE_RGBX101010; | |
17638cd6 JB |
2183 | break; |
2184 | default: | |
baba133a | 2185 | BUG(); |
17638cd6 JB |
2186 | } |
2187 | ||
2188 | if (obj->tiling_mode != I915_TILING_NONE) | |
2189 | dspcntr |= DISPPLANE_TILED; | |
2190 | else | |
2191 | dspcntr &= ~DISPPLANE_TILED; | |
2192 | ||
b42c6009 | 2193 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
1f5d76db PZ |
2194 | dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE; |
2195 | else | |
2196 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
17638cd6 JB |
2197 | |
2198 | I915_WRITE(reg, dspcntr); | |
2199 | ||
e506a0c6 | 2200 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
c2c75131 | 2201 | intel_crtc->dspaddr_offset = |
bc752862 CW |
2202 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2203 | fb->bits_per_pixel / 8, | |
2204 | fb->pitches[0]); | |
c2c75131 | 2205 | linear_offset -= intel_crtc->dspaddr_offset; |
17638cd6 | 2206 | |
f343c5f6 BW |
2207 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2208 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2209 | fb->pitches[0]); | |
01f2c773 | 2210 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2211 | I915_WRITE(DSPSURF(plane), |
2212 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2213 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2214 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2215 | } else { | |
2216 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2217 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2218 | } | |
17638cd6 JB |
2219 | POSTING_READ(reg); |
2220 | ||
2221 | return 0; | |
2222 | } | |
2223 | ||
2224 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ | |
2225 | static int | |
2226 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
2227 | int x, int y, enum mode_set_atomic state) | |
2228 | { | |
2229 | struct drm_device *dev = crtc->dev; | |
2230 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 2231 | |
6b8e6ed0 CW |
2232 | if (dev_priv->display.disable_fbc) |
2233 | dev_priv->display.disable_fbc(dev); | |
3dec0095 | 2234 | intel_increase_pllclock(crtc); |
81255565 | 2235 | |
6b8e6ed0 | 2236 | return dev_priv->display.update_plane(crtc, fb, x, y); |
81255565 JB |
2237 | } |
2238 | ||
96a02917 VS |
2239 | void intel_display_handle_reset(struct drm_device *dev) |
2240 | { | |
2241 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2242 | struct drm_crtc *crtc; | |
2243 | ||
2244 | /* | |
2245 | * Flips in the rings have been nuked by the reset, | |
2246 | * so complete all pending flips so that user space | |
2247 | * will get its events and not get stuck. | |
2248 | * | |
2249 | * Also update the base address of all primary | |
2250 | * planes to the the last fb to make sure we're | |
2251 | * showing the correct fb after a reset. | |
2252 | * | |
2253 | * Need to make two loops over the crtcs so that we | |
2254 | * don't try to grab a crtc mutex before the | |
2255 | * pending_flip_queue really got woken up. | |
2256 | */ | |
2257 | ||
2258 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2259 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2260 | enum plane plane = intel_crtc->plane; | |
2261 | ||
2262 | intel_prepare_page_flip(dev, plane); | |
2263 | intel_finish_page_flip_plane(dev, plane); | |
2264 | } | |
2265 | ||
2266 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2267 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2268 | ||
2269 | mutex_lock(&crtc->mutex); | |
947fdaad CW |
2270 | /* |
2271 | * FIXME: Once we have proper support for primary planes (and | |
2272 | * disabling them without disabling the entire crtc) allow again | |
2273 | * a NULL crtc->fb. | |
2274 | */ | |
2275 | if (intel_crtc->active && crtc->fb) | |
96a02917 VS |
2276 | dev_priv->display.update_plane(crtc, crtc->fb, |
2277 | crtc->x, crtc->y); | |
2278 | mutex_unlock(&crtc->mutex); | |
2279 | } | |
2280 | } | |
2281 | ||
14667a4b CW |
2282 | static int |
2283 | intel_finish_fb(struct drm_framebuffer *old_fb) | |
2284 | { | |
2285 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; | |
2286 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2287 | bool was_interruptible = dev_priv->mm.interruptible; | |
2288 | int ret; | |
2289 | ||
14667a4b CW |
2290 | /* Big Hammer, we also need to ensure that any pending |
2291 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
2292 | * current scanout is retired before unpinning the old | |
2293 | * framebuffer. | |
2294 | * | |
2295 | * This should only fail upon a hung GPU, in which case we | |
2296 | * can safely continue. | |
2297 | */ | |
2298 | dev_priv->mm.interruptible = false; | |
2299 | ret = i915_gem_object_finish_gpu(obj); | |
2300 | dev_priv->mm.interruptible = was_interruptible; | |
2301 | ||
2302 | return ret; | |
2303 | } | |
2304 | ||
198598d0 VS |
2305 | static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y) |
2306 | { | |
2307 | struct drm_device *dev = crtc->dev; | |
2308 | struct drm_i915_master_private *master_priv; | |
2309 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2310 | ||
2311 | if (!dev->primary->master) | |
2312 | return; | |
2313 | ||
2314 | master_priv = dev->primary->master->driver_priv; | |
2315 | if (!master_priv->sarea_priv) | |
2316 | return; | |
2317 | ||
2318 | switch (intel_crtc->pipe) { | |
2319 | case 0: | |
2320 | master_priv->sarea_priv->pipeA_x = x; | |
2321 | master_priv->sarea_priv->pipeA_y = y; | |
2322 | break; | |
2323 | case 1: | |
2324 | master_priv->sarea_priv->pipeB_x = x; | |
2325 | master_priv->sarea_priv->pipeB_y = y; | |
2326 | break; | |
2327 | default: | |
2328 | break; | |
2329 | } | |
2330 | } | |
2331 | ||
5c3b82e2 | 2332 | static int |
3c4fdcfb | 2333 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
94352cf9 | 2334 | struct drm_framebuffer *fb) |
79e53945 JB |
2335 | { |
2336 | struct drm_device *dev = crtc->dev; | |
6b8e6ed0 | 2337 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 2338 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
94352cf9 | 2339 | struct drm_framebuffer *old_fb; |
5c3b82e2 | 2340 | int ret; |
79e53945 JB |
2341 | |
2342 | /* no fb bound */ | |
94352cf9 | 2343 | if (!fb) { |
a5071c2f | 2344 | DRM_ERROR("No FB bound\n"); |
5c3b82e2 CW |
2345 | return 0; |
2346 | } | |
2347 | ||
7eb552ae | 2348 | if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) { |
84f44ce7 VS |
2349 | DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n", |
2350 | plane_name(intel_crtc->plane), | |
2351 | INTEL_INFO(dev)->num_pipes); | |
5c3b82e2 | 2352 | return -EINVAL; |
79e53945 JB |
2353 | } |
2354 | ||
5c3b82e2 | 2355 | mutex_lock(&dev->struct_mutex); |
265db958 | 2356 | ret = intel_pin_and_fence_fb_obj(dev, |
94352cf9 | 2357 | to_intel_framebuffer(fb)->obj, |
919926ae | 2358 | NULL); |
5c3b82e2 CW |
2359 | if (ret != 0) { |
2360 | mutex_unlock(&dev->struct_mutex); | |
a5071c2f | 2361 | DRM_ERROR("pin & fence failed\n"); |
5c3b82e2 CW |
2362 | return ret; |
2363 | } | |
79e53945 | 2364 | |
bb2043de DL |
2365 | /* |
2366 | * Update pipe size and adjust fitter if needed: the reason for this is | |
2367 | * that in compute_mode_changes we check the native mode (not the pfit | |
2368 | * mode) to see if we can flip rather than do a full mode set. In the | |
2369 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
2370 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
2371 | * sized surface. | |
2372 | * | |
2373 | * To fix this properly, we need to hoist the checks up into | |
2374 | * compute_mode_changes (or above), check the actual pfit state and | |
2375 | * whether the platform allows pfit disable with pipe active, and only | |
2376 | * then update the pipesrc and pfit state, even on the flip path. | |
2377 | */ | |
d330a953 | 2378 | if (i915.fastboot) { |
d7bf63f2 DL |
2379 | const struct drm_display_mode *adjusted_mode = |
2380 | &intel_crtc->config.adjusted_mode; | |
2381 | ||
4d6a3e63 | 2382 | I915_WRITE(PIPESRC(intel_crtc->pipe), |
d7bf63f2 DL |
2383 | ((adjusted_mode->crtc_hdisplay - 1) << 16) | |
2384 | (adjusted_mode->crtc_vdisplay - 1)); | |
fd4daa9c | 2385 | if (!intel_crtc->config.pch_pfit.enabled && |
4d6a3e63 JB |
2386 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
2387 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
2388 | I915_WRITE(PF_CTL(intel_crtc->pipe), 0); | |
2389 | I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0); | |
2390 | I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0); | |
2391 | } | |
0637d60d JB |
2392 | intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay; |
2393 | intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay; | |
4d6a3e63 JB |
2394 | } |
2395 | ||
94352cf9 | 2396 | ret = dev_priv->display.update_plane(crtc, fb, x, y); |
4e6cfefc | 2397 | if (ret) { |
94352cf9 | 2398 | intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj); |
5c3b82e2 | 2399 | mutex_unlock(&dev->struct_mutex); |
a5071c2f | 2400 | DRM_ERROR("failed to update base address\n"); |
4e6cfefc | 2401 | return ret; |
79e53945 | 2402 | } |
3c4fdcfb | 2403 | |
94352cf9 DV |
2404 | old_fb = crtc->fb; |
2405 | crtc->fb = fb; | |
6c4c86f5 DV |
2406 | crtc->x = x; |
2407 | crtc->y = y; | |
94352cf9 | 2408 | |
b7f1de28 | 2409 | if (old_fb) { |
d7697eea DV |
2410 | if (intel_crtc->active && old_fb != fb) |
2411 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1690e1eb | 2412 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); |
b7f1de28 | 2413 | } |
652c393a | 2414 | |
6b8e6ed0 | 2415 | intel_update_fbc(dev); |
4906557e | 2416 | intel_edp_psr_update(dev); |
5c3b82e2 | 2417 | mutex_unlock(&dev->struct_mutex); |
79e53945 | 2418 | |
198598d0 | 2419 | intel_crtc_update_sarea_pos(crtc, x, y); |
5c3b82e2 CW |
2420 | |
2421 | return 0; | |
79e53945 JB |
2422 | } |
2423 | ||
5e84e1a4 ZW |
2424 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2425 | { | |
2426 | struct drm_device *dev = crtc->dev; | |
2427 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2428 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2429 | int pipe = intel_crtc->pipe; | |
2430 | u32 reg, temp; | |
2431 | ||
2432 | /* enable normal train */ | |
2433 | reg = FDI_TX_CTL(pipe); | |
2434 | temp = I915_READ(reg); | |
61e499bf | 2435 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
2436 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2437 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
2438 | } else { |
2439 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2440 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 2441 | } |
5e84e1a4 ZW |
2442 | I915_WRITE(reg, temp); |
2443 | ||
2444 | reg = FDI_RX_CTL(pipe); | |
2445 | temp = I915_READ(reg); | |
2446 | if (HAS_PCH_CPT(dev)) { | |
2447 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2448 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
2449 | } else { | |
2450 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2451 | temp |= FDI_LINK_TRAIN_NONE; | |
2452 | } | |
2453 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
2454 | ||
2455 | /* wait one idle pattern time */ | |
2456 | POSTING_READ(reg); | |
2457 | udelay(1000); | |
357555c0 JB |
2458 | |
2459 | /* IVB wants error correction enabled */ | |
2460 | if (IS_IVYBRIDGE(dev)) | |
2461 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
2462 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
2463 | } |
2464 | ||
1fbc0d78 | 2465 | static bool pipe_has_enabled_pch(struct intel_crtc *crtc) |
1e833f40 | 2466 | { |
1fbc0d78 DV |
2467 | return crtc->base.enabled && crtc->active && |
2468 | crtc->config.has_pch_encoder; | |
1e833f40 DV |
2469 | } |
2470 | ||
01a415fd DV |
2471 | static void ivb_modeset_global_resources(struct drm_device *dev) |
2472 | { | |
2473 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2474 | struct intel_crtc *pipe_B_crtc = | |
2475 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
2476 | struct intel_crtc *pipe_C_crtc = | |
2477 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); | |
2478 | uint32_t temp; | |
2479 | ||
1e833f40 DV |
2480 | /* |
2481 | * When everything is off disable fdi C so that we could enable fdi B | |
2482 | * with all lanes. Note that we don't care about enabled pipes without | |
2483 | * an enabled pch encoder. | |
2484 | */ | |
2485 | if (!pipe_has_enabled_pch(pipe_B_crtc) && | |
2486 | !pipe_has_enabled_pch(pipe_C_crtc)) { | |
01a415fd DV |
2487 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
2488 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
2489 | ||
2490 | temp = I915_READ(SOUTH_CHICKEN1); | |
2491 | temp &= ~FDI_BC_BIFURCATION_SELECT; | |
2492 | DRM_DEBUG_KMS("disabling fdi C rx\n"); | |
2493 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
2494 | } | |
2495 | } | |
2496 | ||
8db9d77b ZW |
2497 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2498 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
2499 | { | |
2500 | struct drm_device *dev = crtc->dev; | |
2501 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2502 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2503 | int pipe = intel_crtc->pipe; | |
0fc932b8 | 2504 | int plane = intel_crtc->plane; |
5eddb70b | 2505 | u32 reg, temp, tries; |
8db9d77b | 2506 | |
0fc932b8 JB |
2507 | /* FDI needs bits from pipe & plane first */ |
2508 | assert_pipe_enabled(dev_priv, pipe); | |
2509 | assert_plane_enabled(dev_priv, plane); | |
2510 | ||
e1a44743 AJ |
2511 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2512 | for train result */ | |
5eddb70b CW |
2513 | reg = FDI_RX_IMR(pipe); |
2514 | temp = I915_READ(reg); | |
e1a44743 AJ |
2515 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2516 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2517 | I915_WRITE(reg, temp); |
2518 | I915_READ(reg); | |
e1a44743 AJ |
2519 | udelay(150); |
2520 | ||
8db9d77b | 2521 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2522 | reg = FDI_TX_CTL(pipe); |
2523 | temp = I915_READ(reg); | |
627eb5a3 DV |
2524 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2525 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
2526 | temp &= ~FDI_LINK_TRAIN_NONE; |
2527 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 2528 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2529 | |
5eddb70b CW |
2530 | reg = FDI_RX_CTL(pipe); |
2531 | temp = I915_READ(reg); | |
8db9d77b ZW |
2532 | temp &= ~FDI_LINK_TRAIN_NONE; |
2533 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
2534 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2535 | ||
2536 | POSTING_READ(reg); | |
8db9d77b ZW |
2537 | udelay(150); |
2538 | ||
5b2adf89 | 2539 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
2540 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
2541 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
2542 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 2543 | |
5eddb70b | 2544 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2545 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2546 | temp = I915_READ(reg); |
8db9d77b ZW |
2547 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2548 | ||
2549 | if ((temp & FDI_RX_BIT_LOCK)) { | |
2550 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 2551 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
2552 | break; |
2553 | } | |
8db9d77b | 2554 | } |
e1a44743 | 2555 | if (tries == 5) |
5eddb70b | 2556 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2557 | |
2558 | /* Train 2 */ | |
5eddb70b CW |
2559 | reg = FDI_TX_CTL(pipe); |
2560 | temp = I915_READ(reg); | |
8db9d77b ZW |
2561 | temp &= ~FDI_LINK_TRAIN_NONE; |
2562 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2563 | I915_WRITE(reg, temp); |
8db9d77b | 2564 | |
5eddb70b CW |
2565 | reg = FDI_RX_CTL(pipe); |
2566 | temp = I915_READ(reg); | |
8db9d77b ZW |
2567 | temp &= ~FDI_LINK_TRAIN_NONE; |
2568 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2569 | I915_WRITE(reg, temp); |
8db9d77b | 2570 | |
5eddb70b CW |
2571 | POSTING_READ(reg); |
2572 | udelay(150); | |
8db9d77b | 2573 | |
5eddb70b | 2574 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2575 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2576 | temp = I915_READ(reg); |
8db9d77b ZW |
2577 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2578 | ||
2579 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 2580 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
2581 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2582 | break; | |
2583 | } | |
8db9d77b | 2584 | } |
e1a44743 | 2585 | if (tries == 5) |
5eddb70b | 2586 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2587 | |
2588 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 2589 | |
8db9d77b ZW |
2590 | } |
2591 | ||
0206e353 | 2592 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
2593 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2594 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
2595 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
2596 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
2597 | }; | |
2598 | ||
2599 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
2600 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
2601 | { | |
2602 | struct drm_device *dev = crtc->dev; | |
2603 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2604 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2605 | int pipe = intel_crtc->pipe; | |
fa37d39e | 2606 | u32 reg, temp, i, retry; |
8db9d77b | 2607 | |
e1a44743 AJ |
2608 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2609 | for train result */ | |
5eddb70b CW |
2610 | reg = FDI_RX_IMR(pipe); |
2611 | temp = I915_READ(reg); | |
e1a44743 AJ |
2612 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2613 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2614 | I915_WRITE(reg, temp); |
2615 | ||
2616 | POSTING_READ(reg); | |
e1a44743 AJ |
2617 | udelay(150); |
2618 | ||
8db9d77b | 2619 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2620 | reg = FDI_TX_CTL(pipe); |
2621 | temp = I915_READ(reg); | |
627eb5a3 DV |
2622 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2623 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
2624 | temp &= ~FDI_LINK_TRAIN_NONE; |
2625 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2626 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2627 | /* SNB-B */ | |
2628 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 2629 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2630 | |
d74cf324 DV |
2631 | I915_WRITE(FDI_RX_MISC(pipe), |
2632 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
2633 | ||
5eddb70b CW |
2634 | reg = FDI_RX_CTL(pipe); |
2635 | temp = I915_READ(reg); | |
8db9d77b ZW |
2636 | if (HAS_PCH_CPT(dev)) { |
2637 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2638 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2639 | } else { | |
2640 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2641 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2642 | } | |
5eddb70b CW |
2643 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2644 | ||
2645 | POSTING_READ(reg); | |
8db9d77b ZW |
2646 | udelay(150); |
2647 | ||
0206e353 | 2648 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2649 | reg = FDI_TX_CTL(pipe); |
2650 | temp = I915_READ(reg); | |
8db9d77b ZW |
2651 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2652 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2653 | I915_WRITE(reg, temp); |
2654 | ||
2655 | POSTING_READ(reg); | |
8db9d77b ZW |
2656 | udelay(500); |
2657 | ||
fa37d39e SP |
2658 | for (retry = 0; retry < 5; retry++) { |
2659 | reg = FDI_RX_IIR(pipe); | |
2660 | temp = I915_READ(reg); | |
2661 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2662 | if (temp & FDI_RX_BIT_LOCK) { | |
2663 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
2664 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
2665 | break; | |
2666 | } | |
2667 | udelay(50); | |
8db9d77b | 2668 | } |
fa37d39e SP |
2669 | if (retry < 5) |
2670 | break; | |
8db9d77b ZW |
2671 | } |
2672 | if (i == 4) | |
5eddb70b | 2673 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2674 | |
2675 | /* Train 2 */ | |
5eddb70b CW |
2676 | reg = FDI_TX_CTL(pipe); |
2677 | temp = I915_READ(reg); | |
8db9d77b ZW |
2678 | temp &= ~FDI_LINK_TRAIN_NONE; |
2679 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2680 | if (IS_GEN6(dev)) { | |
2681 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2682 | /* SNB-B */ | |
2683 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
2684 | } | |
5eddb70b | 2685 | I915_WRITE(reg, temp); |
8db9d77b | 2686 | |
5eddb70b CW |
2687 | reg = FDI_RX_CTL(pipe); |
2688 | temp = I915_READ(reg); | |
8db9d77b ZW |
2689 | if (HAS_PCH_CPT(dev)) { |
2690 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2691 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
2692 | } else { | |
2693 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2694 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2695 | } | |
5eddb70b CW |
2696 | I915_WRITE(reg, temp); |
2697 | ||
2698 | POSTING_READ(reg); | |
8db9d77b ZW |
2699 | udelay(150); |
2700 | ||
0206e353 | 2701 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2702 | reg = FDI_TX_CTL(pipe); |
2703 | temp = I915_READ(reg); | |
8db9d77b ZW |
2704 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2705 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2706 | I915_WRITE(reg, temp); |
2707 | ||
2708 | POSTING_READ(reg); | |
8db9d77b ZW |
2709 | udelay(500); |
2710 | ||
fa37d39e SP |
2711 | for (retry = 0; retry < 5; retry++) { |
2712 | reg = FDI_RX_IIR(pipe); | |
2713 | temp = I915_READ(reg); | |
2714 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2715 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
2716 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
2717 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
2718 | break; | |
2719 | } | |
2720 | udelay(50); | |
8db9d77b | 2721 | } |
fa37d39e SP |
2722 | if (retry < 5) |
2723 | break; | |
8db9d77b ZW |
2724 | } |
2725 | if (i == 4) | |
5eddb70b | 2726 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2727 | |
2728 | DRM_DEBUG_KMS("FDI train done.\n"); | |
2729 | } | |
2730 | ||
357555c0 JB |
2731 | /* Manual link training for Ivy Bridge A0 parts */ |
2732 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
2733 | { | |
2734 | struct drm_device *dev = crtc->dev; | |
2735 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2736 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2737 | int pipe = intel_crtc->pipe; | |
139ccd3f | 2738 | u32 reg, temp, i, j; |
357555c0 JB |
2739 | |
2740 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
2741 | for train result */ | |
2742 | reg = FDI_RX_IMR(pipe); | |
2743 | temp = I915_READ(reg); | |
2744 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
2745 | temp &= ~FDI_RX_BIT_LOCK; | |
2746 | I915_WRITE(reg, temp); | |
2747 | ||
2748 | POSTING_READ(reg); | |
2749 | udelay(150); | |
2750 | ||
01a415fd DV |
2751 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
2752 | I915_READ(FDI_RX_IIR(pipe))); | |
2753 | ||
139ccd3f JB |
2754 | /* Try each vswing and preemphasis setting twice before moving on */ |
2755 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
2756 | /* disable first in case we need to retry */ | |
2757 | reg = FDI_TX_CTL(pipe); | |
2758 | temp = I915_READ(reg); | |
2759 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
2760 | temp &= ~FDI_TX_ENABLE; | |
2761 | I915_WRITE(reg, temp); | |
357555c0 | 2762 | |
139ccd3f JB |
2763 | reg = FDI_RX_CTL(pipe); |
2764 | temp = I915_READ(reg); | |
2765 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
2766 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2767 | temp &= ~FDI_RX_ENABLE; | |
2768 | I915_WRITE(reg, temp); | |
357555c0 | 2769 | |
139ccd3f | 2770 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
2771 | reg = FDI_TX_CTL(pipe); |
2772 | temp = I915_READ(reg); | |
139ccd3f JB |
2773 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2774 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
2775 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; | |
357555c0 | 2776 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
2777 | temp |= snb_b_fdi_train_param[j/2]; |
2778 | temp |= FDI_COMPOSITE_SYNC; | |
2779 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 2780 | |
139ccd3f JB |
2781 | I915_WRITE(FDI_RX_MISC(pipe), |
2782 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 2783 | |
139ccd3f | 2784 | reg = FDI_RX_CTL(pipe); |
357555c0 | 2785 | temp = I915_READ(reg); |
139ccd3f JB |
2786 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
2787 | temp |= FDI_COMPOSITE_SYNC; | |
2788 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 2789 | |
139ccd3f JB |
2790 | POSTING_READ(reg); |
2791 | udelay(1); /* should be 0.5us */ | |
357555c0 | 2792 | |
139ccd3f JB |
2793 | for (i = 0; i < 4; i++) { |
2794 | reg = FDI_RX_IIR(pipe); | |
2795 | temp = I915_READ(reg); | |
2796 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 2797 | |
139ccd3f JB |
2798 | if (temp & FDI_RX_BIT_LOCK || |
2799 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
2800 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
2801 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
2802 | i); | |
2803 | break; | |
2804 | } | |
2805 | udelay(1); /* should be 0.5us */ | |
2806 | } | |
2807 | if (i == 4) { | |
2808 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
2809 | continue; | |
2810 | } | |
357555c0 | 2811 | |
139ccd3f | 2812 | /* Train 2 */ |
357555c0 JB |
2813 | reg = FDI_TX_CTL(pipe); |
2814 | temp = I915_READ(reg); | |
139ccd3f JB |
2815 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2816 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
2817 | I915_WRITE(reg, temp); | |
2818 | ||
2819 | reg = FDI_RX_CTL(pipe); | |
2820 | temp = I915_READ(reg); | |
2821 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2822 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
2823 | I915_WRITE(reg, temp); |
2824 | ||
2825 | POSTING_READ(reg); | |
139ccd3f | 2826 | udelay(2); /* should be 1.5us */ |
357555c0 | 2827 | |
139ccd3f JB |
2828 | for (i = 0; i < 4; i++) { |
2829 | reg = FDI_RX_IIR(pipe); | |
2830 | temp = I915_READ(reg); | |
2831 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 2832 | |
139ccd3f JB |
2833 | if (temp & FDI_RX_SYMBOL_LOCK || |
2834 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
2835 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
2836 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
2837 | i); | |
2838 | goto train_done; | |
2839 | } | |
2840 | udelay(2); /* should be 1.5us */ | |
357555c0 | 2841 | } |
139ccd3f JB |
2842 | if (i == 4) |
2843 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 2844 | } |
357555c0 | 2845 | |
139ccd3f | 2846 | train_done: |
357555c0 JB |
2847 | DRM_DEBUG_KMS("FDI train done.\n"); |
2848 | } | |
2849 | ||
88cefb6c | 2850 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 2851 | { |
88cefb6c | 2852 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 2853 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 2854 | int pipe = intel_crtc->pipe; |
5eddb70b | 2855 | u32 reg, temp; |
79e53945 | 2856 | |
c64e311e | 2857 | |
c98e9dcf | 2858 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
2859 | reg = FDI_RX_CTL(pipe); |
2860 | temp = I915_READ(reg); | |
627eb5a3 DV |
2861 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
2862 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
dfd07d72 | 2863 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
2864 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
2865 | ||
2866 | POSTING_READ(reg); | |
c98e9dcf JB |
2867 | udelay(200); |
2868 | ||
2869 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
2870 | temp = I915_READ(reg); |
2871 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
2872 | ||
2873 | POSTING_READ(reg); | |
c98e9dcf JB |
2874 | udelay(200); |
2875 | ||
20749730 PZ |
2876 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
2877 | reg = FDI_TX_CTL(pipe); | |
2878 | temp = I915_READ(reg); | |
2879 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
2880 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 2881 | |
20749730 PZ |
2882 | POSTING_READ(reg); |
2883 | udelay(100); | |
6be4a607 | 2884 | } |
0e23b99d JB |
2885 | } |
2886 | ||
88cefb6c DV |
2887 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
2888 | { | |
2889 | struct drm_device *dev = intel_crtc->base.dev; | |
2890 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2891 | int pipe = intel_crtc->pipe; | |
2892 | u32 reg, temp; | |
2893 | ||
2894 | /* Switch from PCDclk to Rawclk */ | |
2895 | reg = FDI_RX_CTL(pipe); | |
2896 | temp = I915_READ(reg); | |
2897 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
2898 | ||
2899 | /* Disable CPU FDI TX PLL */ | |
2900 | reg = FDI_TX_CTL(pipe); | |
2901 | temp = I915_READ(reg); | |
2902 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
2903 | ||
2904 | POSTING_READ(reg); | |
2905 | udelay(100); | |
2906 | ||
2907 | reg = FDI_RX_CTL(pipe); | |
2908 | temp = I915_READ(reg); | |
2909 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
2910 | ||
2911 | /* Wait for the clocks to turn off. */ | |
2912 | POSTING_READ(reg); | |
2913 | udelay(100); | |
2914 | } | |
2915 | ||
0fc932b8 JB |
2916 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
2917 | { | |
2918 | struct drm_device *dev = crtc->dev; | |
2919 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2920 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2921 | int pipe = intel_crtc->pipe; | |
2922 | u32 reg, temp; | |
2923 | ||
2924 | /* disable CPU FDI tx and PCH FDI rx */ | |
2925 | reg = FDI_TX_CTL(pipe); | |
2926 | temp = I915_READ(reg); | |
2927 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
2928 | POSTING_READ(reg); | |
2929 | ||
2930 | reg = FDI_RX_CTL(pipe); | |
2931 | temp = I915_READ(reg); | |
2932 | temp &= ~(0x7 << 16); | |
dfd07d72 | 2933 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
2934 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
2935 | ||
2936 | POSTING_READ(reg); | |
2937 | udelay(100); | |
2938 | ||
2939 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
6f06ce18 JB |
2940 | if (HAS_PCH_IBX(dev)) { |
2941 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); | |
6f06ce18 | 2942 | } |
0fc932b8 JB |
2943 | |
2944 | /* still set train pattern 1 */ | |
2945 | reg = FDI_TX_CTL(pipe); | |
2946 | temp = I915_READ(reg); | |
2947 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2948 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2949 | I915_WRITE(reg, temp); | |
2950 | ||
2951 | reg = FDI_RX_CTL(pipe); | |
2952 | temp = I915_READ(reg); | |
2953 | if (HAS_PCH_CPT(dev)) { | |
2954 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2955 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2956 | } else { | |
2957 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2958 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2959 | } | |
2960 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
2961 | temp &= ~(0x07 << 16); | |
dfd07d72 | 2962 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
2963 | I915_WRITE(reg, temp); |
2964 | ||
2965 | POSTING_READ(reg); | |
2966 | udelay(100); | |
2967 | } | |
2968 | ||
5bb61643 CW |
2969 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
2970 | { | |
2971 | struct drm_device *dev = crtc->dev; | |
2972 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10d83730 | 2973 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5bb61643 CW |
2974 | unsigned long flags; |
2975 | bool pending; | |
2976 | ||
10d83730 VS |
2977 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
2978 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
5bb61643 CW |
2979 | return false; |
2980 | ||
2981 | spin_lock_irqsave(&dev->event_lock, flags); | |
2982 | pending = to_intel_crtc(crtc)->unpin_work != NULL; | |
2983 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
2984 | ||
2985 | return pending; | |
2986 | } | |
2987 | ||
5dce5b93 CW |
2988 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
2989 | { | |
2990 | struct intel_crtc *crtc; | |
2991 | ||
2992 | /* Note that we don't need to be called with mode_config.lock here | |
2993 | * as our list of CRTC objects is static for the lifetime of the | |
2994 | * device and so cannot disappear as we iterate. Similarly, we can | |
2995 | * happily treat the predicates as racy, atomic checks as userspace | |
2996 | * cannot claim and pin a new fb without at least acquring the | |
2997 | * struct_mutex and so serialising with us. | |
2998 | */ | |
2999 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
3000 | if (atomic_read(&crtc->unpin_work_count) == 0) | |
3001 | continue; | |
3002 | ||
3003 | if (crtc->unpin_work) | |
3004 | intel_wait_for_vblank(dev, crtc->pipe); | |
3005 | ||
3006 | return true; | |
3007 | } | |
3008 | ||
3009 | return false; | |
3010 | } | |
3011 | ||
e6c3a2a6 CW |
3012 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
3013 | { | |
0f91128d | 3014 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3015 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 CW |
3016 | |
3017 | if (crtc->fb == NULL) | |
3018 | return; | |
3019 | ||
2c10d571 DV |
3020 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
3021 | ||
5bb61643 CW |
3022 | wait_event(dev_priv->pending_flip_queue, |
3023 | !intel_crtc_has_pending_flip(crtc)); | |
3024 | ||
0f91128d CW |
3025 | mutex_lock(&dev->struct_mutex); |
3026 | intel_finish_fb(crtc->fb); | |
3027 | mutex_unlock(&dev->struct_mutex); | |
e6c3a2a6 CW |
3028 | } |
3029 | ||
e615efe4 ED |
3030 | /* Program iCLKIP clock to the desired frequency */ |
3031 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3032 | { | |
3033 | struct drm_device *dev = crtc->dev; | |
3034 | struct drm_i915_private *dev_priv = dev->dev_private; | |
241bfc38 | 3035 | int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; |
e615efe4 ED |
3036 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3037 | u32 temp; | |
3038 | ||
09153000 DV |
3039 | mutex_lock(&dev_priv->dpio_lock); |
3040 | ||
e615efe4 ED |
3041 | /* It is necessary to ungate the pixclk gate prior to programming |
3042 | * the divisors, and gate it back when it is done. | |
3043 | */ | |
3044 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3045 | ||
3046 | /* Disable SSCCTL */ | |
3047 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
3048 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
3049 | SBI_SSCCTL_DISABLE, | |
3050 | SBI_ICLK); | |
e615efe4 ED |
3051 | |
3052 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3053 | if (clock == 20000) { |
e615efe4 ED |
3054 | auxdiv = 1; |
3055 | divsel = 0x41; | |
3056 | phaseinc = 0x20; | |
3057 | } else { | |
3058 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3059 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3060 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3061 | * convert the virtual clock precision to KHz here for higher |
3062 | * precision. | |
3063 | */ | |
3064 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3065 | u32 iclk_pi_range = 64; | |
3066 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3067 | ||
12d7ceed | 3068 | desired_divisor = (iclk_virtual_root_freq / clock); |
e615efe4 ED |
3069 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3070 | pi_value = desired_divisor % iclk_pi_range; | |
3071 | ||
3072 | auxdiv = 0; | |
3073 | divsel = msb_divisor_value - 2; | |
3074 | phaseinc = pi_value; | |
3075 | } | |
3076 | ||
3077 | /* This should not happen with any sane values */ | |
3078 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3079 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3080 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3081 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3082 | ||
3083 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3084 | clock, |
e615efe4 ED |
3085 | auxdiv, |
3086 | divsel, | |
3087 | phasedir, | |
3088 | phaseinc); | |
3089 | ||
3090 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 3091 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3092 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3093 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3094 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3095 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3096 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3097 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3098 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3099 | |
3100 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3101 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3102 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3103 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3104 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3105 | |
3106 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3107 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3108 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3109 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
3110 | |
3111 | /* Wait for initialization time */ | |
3112 | udelay(24); | |
3113 | ||
3114 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 DV |
3115 | |
3116 | mutex_unlock(&dev_priv->dpio_lock); | |
e615efe4 ED |
3117 | } |
3118 | ||
275f01b2 DV |
3119 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
3120 | enum pipe pch_transcoder) | |
3121 | { | |
3122 | struct drm_device *dev = crtc->base.dev; | |
3123 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3124 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; | |
3125 | ||
3126 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
3127 | I915_READ(HTOTAL(cpu_transcoder))); | |
3128 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
3129 | I915_READ(HBLANK(cpu_transcoder))); | |
3130 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
3131 | I915_READ(HSYNC(cpu_transcoder))); | |
3132 | ||
3133 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
3134 | I915_READ(VTOTAL(cpu_transcoder))); | |
3135 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
3136 | I915_READ(VBLANK(cpu_transcoder))); | |
3137 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
3138 | I915_READ(VSYNC(cpu_transcoder))); | |
3139 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
3140 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
3141 | } | |
3142 | ||
1fbc0d78 DV |
3143 | static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) |
3144 | { | |
3145 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3146 | uint32_t temp; | |
3147 | ||
3148 | temp = I915_READ(SOUTH_CHICKEN1); | |
3149 | if (temp & FDI_BC_BIFURCATION_SELECT) | |
3150 | return; | |
3151 | ||
3152 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
3153 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
3154 | ||
3155 | temp |= FDI_BC_BIFURCATION_SELECT; | |
3156 | DRM_DEBUG_KMS("enabling fdi C rx\n"); | |
3157 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
3158 | POSTING_READ(SOUTH_CHICKEN1); | |
3159 | } | |
3160 | ||
3161 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
3162 | { | |
3163 | struct drm_device *dev = intel_crtc->base.dev; | |
3164 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3165 | ||
3166 | switch (intel_crtc->pipe) { | |
3167 | case PIPE_A: | |
3168 | break; | |
3169 | case PIPE_B: | |
3170 | if (intel_crtc->config.fdi_lanes > 2) | |
3171 | WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); | |
3172 | else | |
3173 | cpt_enable_fdi_bc_bifurcation(dev); | |
3174 | ||
3175 | break; | |
3176 | case PIPE_C: | |
3177 | cpt_enable_fdi_bc_bifurcation(dev); | |
3178 | ||
3179 | break; | |
3180 | default: | |
3181 | BUG(); | |
3182 | } | |
3183 | } | |
3184 | ||
f67a559d JB |
3185 | /* |
3186 | * Enable PCH resources required for PCH ports: | |
3187 | * - PCH PLLs | |
3188 | * - FDI training & RX/TX | |
3189 | * - update transcoder timings | |
3190 | * - DP transcoding bits | |
3191 | * - transcoder | |
3192 | */ | |
3193 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
3194 | { |
3195 | struct drm_device *dev = crtc->dev; | |
3196 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3197 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3198 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 3199 | u32 reg, temp; |
2c07245f | 3200 | |
ab9412ba | 3201 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 3202 | |
1fbc0d78 DV |
3203 | if (IS_IVYBRIDGE(dev)) |
3204 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
3205 | ||
cd986abb DV |
3206 | /* Write the TU size bits before fdi link training, so that error |
3207 | * detection works. */ | |
3208 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
3209 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
3210 | ||
c98e9dcf | 3211 | /* For PCH output, training FDI link */ |
674cf967 | 3212 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 3213 | |
3ad8a208 DV |
3214 | /* We need to program the right clock selection before writing the pixel |
3215 | * mutliplier into the DPLL. */ | |
303b81e0 | 3216 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 3217 | u32 sel; |
4b645f14 | 3218 | |
c98e9dcf | 3219 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
3220 | temp |= TRANS_DPLL_ENABLE(pipe); |
3221 | sel = TRANS_DPLLB_SEL(pipe); | |
a43f6e0f | 3222 | if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
3223 | temp |= sel; |
3224 | else | |
3225 | temp &= ~sel; | |
c98e9dcf | 3226 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 3227 | } |
5eddb70b | 3228 | |
3ad8a208 DV |
3229 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
3230 | * transcoder, and we actually should do this to not upset any PCH | |
3231 | * transcoder that already use the clock when we share it. | |
3232 | * | |
3233 | * Note that enable_shared_dpll tries to do the right thing, but | |
3234 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
3235 | * the right LVDS enable sequence. */ | |
3236 | ironlake_enable_shared_dpll(intel_crtc); | |
3237 | ||
d9b6cb56 JB |
3238 | /* set transcoder timing, panel must allow it */ |
3239 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 3240 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 3241 | |
303b81e0 | 3242 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 3243 | |
c98e9dcf JB |
3244 | /* For PCH DP, enable TRANS_DP_CTL */ |
3245 | if (HAS_PCH_CPT(dev) && | |
417e822d KP |
3246 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
3247 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
dfd07d72 | 3248 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
3249 | reg = TRANS_DP_CTL(pipe); |
3250 | temp = I915_READ(reg); | |
3251 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
3252 | TRANS_DP_SYNC_MASK | |
3253 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
3254 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3255 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 3256 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
3257 | |
3258 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 3259 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 3260 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 3261 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
3262 | |
3263 | switch (intel_trans_dp_port_sel(crtc)) { | |
3264 | case PCH_DP_B: | |
5eddb70b | 3265 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
3266 | break; |
3267 | case PCH_DP_C: | |
5eddb70b | 3268 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
3269 | break; |
3270 | case PCH_DP_D: | |
5eddb70b | 3271 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
3272 | break; |
3273 | default: | |
e95d41e1 | 3274 | BUG(); |
32f9d658 | 3275 | } |
2c07245f | 3276 | |
5eddb70b | 3277 | I915_WRITE(reg, temp); |
6be4a607 | 3278 | } |
b52eb4dc | 3279 | |
b8a4f404 | 3280 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
3281 | } |
3282 | ||
1507e5bd PZ |
3283 | static void lpt_pch_enable(struct drm_crtc *crtc) |
3284 | { | |
3285 | struct drm_device *dev = crtc->dev; | |
3286 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3287 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3b117c8f | 3288 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
1507e5bd | 3289 | |
ab9412ba | 3290 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 3291 | |
8c52b5e8 | 3292 | lpt_program_iclkip(crtc); |
1507e5bd | 3293 | |
0540e488 | 3294 | /* Set transcoder timing. */ |
275f01b2 | 3295 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 3296 | |
937bb610 | 3297 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
3298 | } |
3299 | ||
e2b78267 | 3300 | static void intel_put_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3301 | { |
e2b78267 | 3302 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
ee7b9f93 JB |
3303 | |
3304 | if (pll == NULL) | |
3305 | return; | |
3306 | ||
3307 | if (pll->refcount == 0) { | |
46edb027 | 3308 | WARN(1, "bad %s refcount\n", pll->name); |
ee7b9f93 JB |
3309 | return; |
3310 | } | |
3311 | ||
f4a091c7 DV |
3312 | if (--pll->refcount == 0) { |
3313 | WARN_ON(pll->on); | |
3314 | WARN_ON(pll->active); | |
3315 | } | |
3316 | ||
a43f6e0f | 3317 | crtc->config.shared_dpll = DPLL_ID_PRIVATE; |
ee7b9f93 JB |
3318 | } |
3319 | ||
b89a1d39 | 3320 | static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3321 | { |
e2b78267 DV |
3322 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
3323 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
3324 | enum intel_dpll_id i; | |
ee7b9f93 | 3325 | |
ee7b9f93 | 3326 | if (pll) { |
46edb027 DV |
3327 | DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n", |
3328 | crtc->base.base.id, pll->name); | |
e2b78267 | 3329 | intel_put_shared_dpll(crtc); |
ee7b9f93 JB |
3330 | } |
3331 | ||
98b6bd99 DV |
3332 | if (HAS_PCH_IBX(dev_priv->dev)) { |
3333 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 3334 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 3335 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 3336 | |
46edb027 DV |
3337 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
3338 | crtc->base.base.id, pll->name); | |
98b6bd99 DV |
3339 | |
3340 | goto found; | |
3341 | } | |
3342 | ||
e72f9fbf DV |
3343 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3344 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 JB |
3345 | |
3346 | /* Only want to check enabled timings first */ | |
3347 | if (pll->refcount == 0) | |
3348 | continue; | |
3349 | ||
b89a1d39 DV |
3350 | if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state, |
3351 | sizeof(pll->hw_state)) == 0) { | |
46edb027 | 3352 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n", |
e2b78267 | 3353 | crtc->base.base.id, |
46edb027 | 3354 | pll->name, pll->refcount, pll->active); |
ee7b9f93 JB |
3355 | |
3356 | goto found; | |
3357 | } | |
3358 | } | |
3359 | ||
3360 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
3361 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3362 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 | 3363 | if (pll->refcount == 0) { |
46edb027 DV |
3364 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
3365 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
3366 | goto found; |
3367 | } | |
3368 | } | |
3369 | ||
3370 | return NULL; | |
3371 | ||
3372 | found: | |
a43f6e0f | 3373 | crtc->config.shared_dpll = i; |
46edb027 DV |
3374 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
3375 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 3376 | |
cdbd2316 | 3377 | if (pll->active == 0) { |
66e985c0 DV |
3378 | memcpy(&pll->hw_state, &crtc->config.dpll_hw_state, |
3379 | sizeof(pll->hw_state)); | |
3380 | ||
46edb027 | 3381 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); |
cdbd2316 | 3382 | WARN_ON(pll->on); |
e9d6944e | 3383 | assert_shared_dpll_disabled(dev_priv, pll); |
ee7b9f93 | 3384 | |
15bdd4cf | 3385 | pll->mode_set(dev_priv, pll); |
cdbd2316 DV |
3386 | } |
3387 | pll->refcount++; | |
e04c7350 | 3388 | |
ee7b9f93 JB |
3389 | return pll; |
3390 | } | |
3391 | ||
a1520318 | 3392 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
3393 | { |
3394 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 3395 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
3396 | u32 temp; |
3397 | ||
3398 | temp = I915_READ(dslreg); | |
3399 | udelay(500); | |
3400 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 3401 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 3402 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
3403 | } |
3404 | } | |
3405 | ||
b074cec8 JB |
3406 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
3407 | { | |
3408 | struct drm_device *dev = crtc->base.dev; | |
3409 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3410 | int pipe = crtc->pipe; | |
3411 | ||
fd4daa9c | 3412 | if (crtc->config.pch_pfit.enabled) { |
b074cec8 JB |
3413 | /* Force use of hard-coded filter coefficients |
3414 | * as some pre-programmed values are broken, | |
3415 | * e.g. x201. | |
3416 | */ | |
3417 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
3418 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
3419 | PF_PIPE_SEL_IVB(pipe)); | |
3420 | else | |
3421 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
3422 | I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos); | |
3423 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size); | |
d4270e57 JB |
3424 | } |
3425 | } | |
3426 | ||
bb53d4ae VS |
3427 | static void intel_enable_planes(struct drm_crtc *crtc) |
3428 | { | |
3429 | struct drm_device *dev = crtc->dev; | |
3430 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
3431 | struct intel_plane *intel_plane; | |
3432 | ||
3433 | list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head) | |
3434 | if (intel_plane->pipe == pipe) | |
3435 | intel_plane_restore(&intel_plane->base); | |
3436 | } | |
3437 | ||
3438 | static void intel_disable_planes(struct drm_crtc *crtc) | |
3439 | { | |
3440 | struct drm_device *dev = crtc->dev; | |
3441 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
3442 | struct intel_plane *intel_plane; | |
3443 | ||
3444 | list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head) | |
3445 | if (intel_plane->pipe == pipe) | |
3446 | intel_plane_disable(&intel_plane->base); | |
3447 | } | |
3448 | ||
20bc8673 | 3449 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
3450 | { |
3451 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
3452 | ||
3453 | if (!crtc->config.ips_enabled) | |
3454 | return; | |
3455 | ||
3456 | /* We can only enable IPS after we enable a plane and wait for a vblank. | |
3457 | * We guarantee that the plane is enabled by calling intel_enable_ips | |
3458 | * only after intel_enable_plane. And intel_enable_plane already waits | |
3459 | * for a vblank, so all we need to do here is to enable the IPS bit. */ | |
3460 | assert_plane_enabled(dev_priv, crtc->plane); | |
2a114cc1 BW |
3461 | if (IS_BROADWELL(crtc->base.dev)) { |
3462 | mutex_lock(&dev_priv->rps.hw_lock); | |
3463 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
3464 | mutex_unlock(&dev_priv->rps.hw_lock); | |
3465 | /* Quoting Art Runyan: "its not safe to expect any particular | |
3466 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
3467 | * mailbox." Moreover, the mailbox may return a bogus state, |
3468 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
3469 | */ |
3470 | } else { | |
3471 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
3472 | /* The bit only becomes 1 in the next vblank, so this wait here | |
3473 | * is essentially intel_wait_for_vblank. If we don't have this | |
3474 | * and don't wait for vblanks until the end of crtc_enable, then | |
3475 | * the HW state readout code will complain that the expected | |
3476 | * IPS_CTL value is not the one we read. */ | |
3477 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
3478 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
3479 | } | |
d77e4531 PZ |
3480 | } |
3481 | ||
20bc8673 | 3482 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
3483 | { |
3484 | struct drm_device *dev = crtc->base.dev; | |
3485 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3486 | ||
3487 | if (!crtc->config.ips_enabled) | |
3488 | return; | |
3489 | ||
3490 | assert_plane_enabled(dev_priv, crtc->plane); | |
2a114cc1 BW |
3491 | if (IS_BROADWELL(crtc->base.dev)) { |
3492 | mutex_lock(&dev_priv->rps.hw_lock); | |
3493 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
3494 | mutex_unlock(&dev_priv->rps.hw_lock); | |
e59150dc | 3495 | } else { |
2a114cc1 | 3496 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
3497 | POSTING_READ(IPS_CTL); |
3498 | } | |
d77e4531 PZ |
3499 | |
3500 | /* We need to wait for a vblank before we can disable the plane. */ | |
3501 | intel_wait_for_vblank(dev, crtc->pipe); | |
3502 | } | |
3503 | ||
3504 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
3505 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
3506 | { | |
3507 | struct drm_device *dev = crtc->dev; | |
3508 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3509 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3510 | enum pipe pipe = intel_crtc->pipe; | |
3511 | int palreg = PALETTE(pipe); | |
3512 | int i; | |
3513 | bool reenable_ips = false; | |
3514 | ||
3515 | /* The clocks have to be on to load the palette. */ | |
3516 | if (!crtc->enabled || !intel_crtc->active) | |
3517 | return; | |
3518 | ||
3519 | if (!HAS_PCH_SPLIT(dev_priv->dev)) { | |
3520 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) | |
3521 | assert_dsi_pll_enabled(dev_priv); | |
3522 | else | |
3523 | assert_pll_enabled(dev_priv, pipe); | |
3524 | } | |
3525 | ||
3526 | /* use legacy palette for Ironlake */ | |
3527 | if (HAS_PCH_SPLIT(dev)) | |
3528 | palreg = LGC_PALETTE(pipe); | |
3529 | ||
3530 | /* Workaround : Do not read or write the pipe palette/gamma data while | |
3531 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
3532 | */ | |
41e6fc4c | 3533 | if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled && |
d77e4531 PZ |
3534 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
3535 | GAMMA_MODE_MODE_SPLIT)) { | |
3536 | hsw_disable_ips(intel_crtc); | |
3537 | reenable_ips = true; | |
3538 | } | |
3539 | ||
3540 | for (i = 0; i < 256; i++) { | |
3541 | I915_WRITE(palreg + 4 * i, | |
3542 | (intel_crtc->lut_r[i] << 16) | | |
3543 | (intel_crtc->lut_g[i] << 8) | | |
3544 | intel_crtc->lut_b[i]); | |
3545 | } | |
3546 | ||
3547 | if (reenable_ips) | |
3548 | hsw_enable_ips(intel_crtc); | |
3549 | } | |
3550 | ||
f67a559d JB |
3551 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
3552 | { | |
3553 | struct drm_device *dev = crtc->dev; | |
3554 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3555 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3556 | struct intel_encoder *encoder; |
f67a559d JB |
3557 | int pipe = intel_crtc->pipe; |
3558 | int plane = intel_crtc->plane; | |
f67a559d | 3559 | |
08a48469 DV |
3560 | WARN_ON(!crtc->enabled); |
3561 | ||
f67a559d JB |
3562 | if (intel_crtc->active) |
3563 | return; | |
3564 | ||
3565 | intel_crtc->active = true; | |
8664281b PZ |
3566 | |
3567 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
3568 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); | |
3569 | ||
f6736a1a | 3570 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
3571 | if (encoder->pre_enable) |
3572 | encoder->pre_enable(encoder); | |
f67a559d | 3573 | |
5bfe2ac0 | 3574 | if (intel_crtc->config.has_pch_encoder) { |
fff367c7 DV |
3575 | /* Note: FDI PLL enabling _must_ be done before we enable the |
3576 | * cpu pipes, hence this is separate from all the other fdi/pch | |
3577 | * enabling. */ | |
88cefb6c | 3578 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
3579 | } else { |
3580 | assert_fdi_tx_disabled(dev_priv, pipe); | |
3581 | assert_fdi_rx_disabled(dev_priv, pipe); | |
3582 | } | |
f67a559d | 3583 | |
b074cec8 | 3584 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 3585 | |
9c54c0dd JB |
3586 | /* |
3587 | * On ILK+ LUT must be loaded before the pipe is running but with | |
3588 | * clocks enabled | |
3589 | */ | |
3590 | intel_crtc_load_lut(crtc); | |
3591 | ||
f37fcc2a | 3592 | intel_update_watermarks(crtc); |
5bfe2ac0 | 3593 | intel_enable_pipe(dev_priv, pipe, |
23538ef1 | 3594 | intel_crtc->config.has_pch_encoder, false); |
d1de00ef | 3595 | intel_enable_primary_plane(dev_priv, plane, pipe); |
bb53d4ae | 3596 | intel_enable_planes(crtc); |
5c38d48c | 3597 | intel_crtc_update_cursor(crtc, true); |
f67a559d | 3598 | |
5bfe2ac0 | 3599 | if (intel_crtc->config.has_pch_encoder) |
f67a559d | 3600 | ironlake_pch_enable(crtc); |
c98e9dcf | 3601 | |
d1ebd816 | 3602 | mutex_lock(&dev->struct_mutex); |
bed4a673 | 3603 | intel_update_fbc(dev); |
d1ebd816 BW |
3604 | mutex_unlock(&dev->struct_mutex); |
3605 | ||
fa5c73b1 DV |
3606 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3607 | encoder->enable(encoder); | |
61b77ddd DV |
3608 | |
3609 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 3610 | cpt_verify_modeset(dev, intel_crtc->pipe); |
6ce94100 DV |
3611 | |
3612 | /* | |
3613 | * There seems to be a race in PCH platform hw (at least on some | |
3614 | * outputs) where an enabled pipe still completes any pageflip right | |
3615 | * away (as if the pipe is off) instead of waiting for vblank. As soon | |
3616 | * as the first vblank happend, everything works as expected. Hence just | |
3617 | * wait for one vblank before returning to avoid strange things | |
3618 | * happening. | |
3619 | */ | |
3620 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
6be4a607 JB |
3621 | } |
3622 | ||
42db64ef PZ |
3623 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
3624 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
3625 | { | |
f5adf94e | 3626 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
3627 | } |
3628 | ||
dda9a66a VS |
3629 | static void haswell_crtc_enable_planes(struct drm_crtc *crtc) |
3630 | { | |
3631 | struct drm_device *dev = crtc->dev; | |
3632 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3633 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3634 | int pipe = intel_crtc->pipe; | |
3635 | int plane = intel_crtc->plane; | |
3636 | ||
d1de00ef | 3637 | intel_enable_primary_plane(dev_priv, plane, pipe); |
dda9a66a VS |
3638 | intel_enable_planes(crtc); |
3639 | intel_crtc_update_cursor(crtc, true); | |
3640 | ||
3641 | hsw_enable_ips(intel_crtc); | |
3642 | ||
3643 | mutex_lock(&dev->struct_mutex); | |
3644 | intel_update_fbc(dev); | |
3645 | mutex_unlock(&dev->struct_mutex); | |
3646 | } | |
3647 | ||
3648 | static void haswell_crtc_disable_planes(struct drm_crtc *crtc) | |
3649 | { | |
3650 | struct drm_device *dev = crtc->dev; | |
3651 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3652 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3653 | int pipe = intel_crtc->pipe; | |
3654 | int plane = intel_crtc->plane; | |
3655 | ||
3656 | intel_crtc_wait_for_pending_flips(crtc); | |
3657 | drm_vblank_off(dev, pipe); | |
3658 | ||
3659 | /* FBC must be disabled before disabling the plane on HSW. */ | |
3660 | if (dev_priv->fbc.plane == plane) | |
3661 | intel_disable_fbc(dev); | |
3662 | ||
3663 | hsw_disable_ips(intel_crtc); | |
3664 | ||
3665 | intel_crtc_update_cursor(crtc, false); | |
3666 | intel_disable_planes(crtc); | |
d1de00ef | 3667 | intel_disable_primary_plane(dev_priv, plane, pipe); |
dda9a66a VS |
3668 | } |
3669 | ||
e4916946 PZ |
3670 | /* |
3671 | * This implements the workaround described in the "notes" section of the mode | |
3672 | * set sequence documentation. When going from no pipes or single pipe to | |
3673 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
3674 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
3675 | */ | |
3676 | static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) | |
3677 | { | |
3678 | struct drm_device *dev = crtc->base.dev; | |
3679 | struct intel_crtc *crtc_it, *other_active_crtc = NULL; | |
3680 | ||
3681 | /* We want to get the other_active_crtc only if there's only 1 other | |
3682 | * active crtc. */ | |
3683 | list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) { | |
3684 | if (!crtc_it->active || crtc_it == crtc) | |
3685 | continue; | |
3686 | ||
3687 | if (other_active_crtc) | |
3688 | return; | |
3689 | ||
3690 | other_active_crtc = crtc_it; | |
3691 | } | |
3692 | if (!other_active_crtc) | |
3693 | return; | |
3694 | ||
3695 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
3696 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
3697 | } | |
3698 | ||
4f771f10 PZ |
3699 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
3700 | { | |
3701 | struct drm_device *dev = crtc->dev; | |
3702 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3703 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3704 | struct intel_encoder *encoder; | |
3705 | int pipe = intel_crtc->pipe; | |
4f771f10 PZ |
3706 | |
3707 | WARN_ON(!crtc->enabled); | |
3708 | ||
3709 | if (intel_crtc->active) | |
3710 | return; | |
3711 | ||
3712 | intel_crtc->active = true; | |
8664281b PZ |
3713 | |
3714 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
3715 | if (intel_crtc->config.has_pch_encoder) | |
3716 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); | |
3717 | ||
5bfe2ac0 | 3718 | if (intel_crtc->config.has_pch_encoder) |
04945641 | 3719 | dev_priv->display.fdi_link_train(crtc); |
4f771f10 PZ |
3720 | |
3721 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3722 | if (encoder->pre_enable) | |
3723 | encoder->pre_enable(encoder); | |
3724 | ||
1f544388 | 3725 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 3726 | |
b074cec8 | 3727 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
3728 | |
3729 | /* | |
3730 | * On ILK+ LUT must be loaded before the pipe is running but with | |
3731 | * clocks enabled | |
3732 | */ | |
3733 | intel_crtc_load_lut(crtc); | |
3734 | ||
1f544388 | 3735 | intel_ddi_set_pipe_settings(crtc); |
8228c251 | 3736 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 3737 | |
f37fcc2a | 3738 | intel_update_watermarks(crtc); |
5bfe2ac0 | 3739 | intel_enable_pipe(dev_priv, pipe, |
23538ef1 | 3740 | intel_crtc->config.has_pch_encoder, false); |
42db64ef | 3741 | |
5bfe2ac0 | 3742 | if (intel_crtc->config.has_pch_encoder) |
1507e5bd | 3743 | lpt_pch_enable(crtc); |
4f771f10 | 3744 | |
8807e55b | 3745 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 3746 | encoder->enable(encoder); |
8807e55b JN |
3747 | intel_opregion_notify_encoder(encoder, true); |
3748 | } | |
4f771f10 | 3749 | |
e4916946 PZ |
3750 | /* If we change the relative order between pipe/planes enabling, we need |
3751 | * to change the workaround. */ | |
3752 | haswell_mode_set_planes_workaround(intel_crtc); | |
dda9a66a VS |
3753 | haswell_crtc_enable_planes(crtc); |
3754 | ||
4f771f10 PZ |
3755 | /* |
3756 | * There seems to be a race in PCH platform hw (at least on some | |
3757 | * outputs) where an enabled pipe still completes any pageflip right | |
3758 | * away (as if the pipe is off) instead of waiting for vblank. As soon | |
3759 | * as the first vblank happend, everything works as expected. Hence just | |
3760 | * wait for one vblank before returning to avoid strange things | |
3761 | * happening. | |
3762 | */ | |
3763 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
3764 | } | |
3765 | ||
3f8dce3a DV |
3766 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
3767 | { | |
3768 | struct drm_device *dev = crtc->base.dev; | |
3769 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3770 | int pipe = crtc->pipe; | |
3771 | ||
3772 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
3773 | * it's in use. The hw state code will make sure we get this right. */ | |
fd4daa9c | 3774 | if (crtc->config.pch_pfit.enabled) { |
3f8dce3a DV |
3775 | I915_WRITE(PF_CTL(pipe), 0); |
3776 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
3777 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
3778 | } | |
3779 | } | |
3780 | ||
6be4a607 JB |
3781 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
3782 | { | |
3783 | struct drm_device *dev = crtc->dev; | |
3784 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3785 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3786 | struct intel_encoder *encoder; |
6be4a607 JB |
3787 | int pipe = intel_crtc->pipe; |
3788 | int plane = intel_crtc->plane; | |
5eddb70b | 3789 | u32 reg, temp; |
b52eb4dc | 3790 | |
ef9c3aee | 3791 | |
f7abfe8b CW |
3792 | if (!intel_crtc->active) |
3793 | return; | |
3794 | ||
ea9d758d DV |
3795 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3796 | encoder->disable(encoder); | |
3797 | ||
e6c3a2a6 | 3798 | intel_crtc_wait_for_pending_flips(crtc); |
6be4a607 | 3799 | drm_vblank_off(dev, pipe); |
913d8d11 | 3800 | |
5c3fe8b0 | 3801 | if (dev_priv->fbc.plane == plane) |
973d04f9 | 3802 | intel_disable_fbc(dev); |
2c07245f | 3803 | |
0d5b8c61 | 3804 | intel_crtc_update_cursor(crtc, false); |
bb53d4ae | 3805 | intel_disable_planes(crtc); |
d1de00ef | 3806 | intel_disable_primary_plane(dev_priv, plane, pipe); |
0d5b8c61 | 3807 | |
d925c59a DV |
3808 | if (intel_crtc->config.has_pch_encoder) |
3809 | intel_set_pch_fifo_underrun_reporting(dev, pipe, false); | |
3810 | ||
b24e7179 | 3811 | intel_disable_pipe(dev_priv, pipe); |
32f9d658 | 3812 | |
3f8dce3a | 3813 | ironlake_pfit_disable(intel_crtc); |
2c07245f | 3814 | |
bf49ec8c DV |
3815 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3816 | if (encoder->post_disable) | |
3817 | encoder->post_disable(encoder); | |
2c07245f | 3818 | |
d925c59a DV |
3819 | if (intel_crtc->config.has_pch_encoder) { |
3820 | ironlake_fdi_disable(crtc); | |
913d8d11 | 3821 | |
d925c59a DV |
3822 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
3823 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); | |
6be4a607 | 3824 | |
d925c59a DV |
3825 | if (HAS_PCH_CPT(dev)) { |
3826 | /* disable TRANS_DP_CTL */ | |
3827 | reg = TRANS_DP_CTL(pipe); | |
3828 | temp = I915_READ(reg); | |
3829 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
3830 | TRANS_DP_PORT_SEL_MASK); | |
3831 | temp |= TRANS_DP_PORT_SEL_NONE; | |
3832 | I915_WRITE(reg, temp); | |
3833 | ||
3834 | /* disable DPLL_SEL */ | |
3835 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 3836 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 3837 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 3838 | } |
e3421a18 | 3839 | |
d925c59a | 3840 | /* disable PCH DPLL */ |
e72f9fbf | 3841 | intel_disable_shared_dpll(intel_crtc); |
8db9d77b | 3842 | |
d925c59a DV |
3843 | ironlake_fdi_pll_disable(intel_crtc); |
3844 | } | |
6b383a7f | 3845 | |
f7abfe8b | 3846 | intel_crtc->active = false; |
46ba614c | 3847 | intel_update_watermarks(crtc); |
d1ebd816 BW |
3848 | |
3849 | mutex_lock(&dev->struct_mutex); | |
6b383a7f | 3850 | intel_update_fbc(dev); |
d1ebd816 | 3851 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 3852 | } |
1b3c7a47 | 3853 | |
4f771f10 | 3854 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 3855 | { |
4f771f10 PZ |
3856 | struct drm_device *dev = crtc->dev; |
3857 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 3858 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 PZ |
3859 | struct intel_encoder *encoder; |
3860 | int pipe = intel_crtc->pipe; | |
3b117c8f | 3861 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee7b9f93 | 3862 | |
4f771f10 PZ |
3863 | if (!intel_crtc->active) |
3864 | return; | |
3865 | ||
dda9a66a VS |
3866 | haswell_crtc_disable_planes(crtc); |
3867 | ||
8807e55b JN |
3868 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
3869 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 3870 | encoder->disable(encoder); |
8807e55b | 3871 | } |
4f771f10 | 3872 | |
8664281b PZ |
3873 | if (intel_crtc->config.has_pch_encoder) |
3874 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); | |
4f771f10 PZ |
3875 | intel_disable_pipe(dev_priv, pipe); |
3876 | ||
ad80a810 | 3877 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 3878 | |
3f8dce3a | 3879 | ironlake_pfit_disable(intel_crtc); |
4f771f10 | 3880 | |
1f544388 | 3881 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 PZ |
3882 | |
3883 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3884 | if (encoder->post_disable) | |
3885 | encoder->post_disable(encoder); | |
3886 | ||
88adfff1 | 3887 | if (intel_crtc->config.has_pch_encoder) { |
ab4d966c | 3888 | lpt_disable_pch_transcoder(dev_priv); |
8664281b | 3889 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
1ad960f2 | 3890 | intel_ddi_fdi_disable(crtc); |
83616634 | 3891 | } |
4f771f10 PZ |
3892 | |
3893 | intel_crtc->active = false; | |
46ba614c | 3894 | intel_update_watermarks(crtc); |
4f771f10 PZ |
3895 | |
3896 | mutex_lock(&dev->struct_mutex); | |
3897 | intel_update_fbc(dev); | |
3898 | mutex_unlock(&dev->struct_mutex); | |
3899 | } | |
3900 | ||
ee7b9f93 JB |
3901 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
3902 | { | |
3903 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e72f9fbf | 3904 | intel_put_shared_dpll(intel_crtc); |
ee7b9f93 JB |
3905 | } |
3906 | ||
6441ab5f PZ |
3907 | static void haswell_crtc_off(struct drm_crtc *crtc) |
3908 | { | |
3909 | intel_ddi_put_crtc_pll(crtc); | |
3910 | } | |
3911 | ||
02e792fb DV |
3912 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
3913 | { | |
02e792fb | 3914 | if (!enable && intel_crtc->overlay) { |
23f09ce3 | 3915 | struct drm_device *dev = intel_crtc->base.dev; |
ce453d81 | 3916 | struct drm_i915_private *dev_priv = dev->dev_private; |
03f77ea5 | 3917 | |
23f09ce3 | 3918 | mutex_lock(&dev->struct_mutex); |
ce453d81 CW |
3919 | dev_priv->mm.interruptible = false; |
3920 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
3921 | dev_priv->mm.interruptible = true; | |
23f09ce3 | 3922 | mutex_unlock(&dev->struct_mutex); |
02e792fb | 3923 | } |
02e792fb | 3924 | |
5dcdbcb0 CW |
3925 | /* Let userspace switch the overlay on again. In most cases userspace |
3926 | * has to recompute where to put it anyway. | |
3927 | */ | |
02e792fb DV |
3928 | } |
3929 | ||
61bc95c1 EE |
3930 | /** |
3931 | * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware | |
3932 | * cursor plane briefly if not already running after enabling the display | |
3933 | * plane. | |
3934 | * This workaround avoids occasional blank screens when self refresh is | |
3935 | * enabled. | |
3936 | */ | |
3937 | static void | |
3938 | g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe) | |
3939 | { | |
3940 | u32 cntl = I915_READ(CURCNTR(pipe)); | |
3941 | ||
3942 | if ((cntl & CURSOR_MODE) == 0) { | |
3943 | u32 fw_bcl_self = I915_READ(FW_BLC_SELF); | |
3944 | ||
3945 | I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN); | |
3946 | I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX); | |
3947 | intel_wait_for_vblank(dev_priv->dev, pipe); | |
3948 | I915_WRITE(CURCNTR(pipe), cntl); | |
3949 | I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); | |
3950 | I915_WRITE(FW_BLC_SELF, fw_bcl_self); | |
3951 | } | |
3952 | } | |
3953 | ||
2dd24552 JB |
3954 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
3955 | { | |
3956 | struct drm_device *dev = crtc->base.dev; | |
3957 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3958 | struct intel_crtc_config *pipe_config = &crtc->config; | |
3959 | ||
328d8e82 | 3960 | if (!crtc->config.gmch_pfit.control) |
2dd24552 JB |
3961 | return; |
3962 | ||
2dd24552 | 3963 | /* |
c0b03411 DV |
3964 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
3965 | * according to register description and PRM. | |
2dd24552 | 3966 | */ |
c0b03411 DV |
3967 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
3968 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 3969 | |
b074cec8 JB |
3970 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
3971 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
3972 | |
3973 | /* Border color in case we don't scale up to the full screen. Black by | |
3974 | * default, change to something else for debugging. */ | |
3975 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
3976 | } |
3977 | ||
586f49dc | 3978 | int valleyview_get_vco(struct drm_i915_private *dev_priv) |
30a970c6 | 3979 | { |
586f49dc | 3980 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
30a970c6 | 3981 | |
586f49dc JB |
3982 | /* Obtain SKU information */ |
3983 | mutex_lock(&dev_priv->dpio_lock); | |
3984 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
3985 | CCK_FUSE_HPLL_FREQ_MASK; | |
3986 | mutex_unlock(&dev_priv->dpio_lock); | |
30a970c6 | 3987 | |
586f49dc | 3988 | return vco_freq[hpll_freq]; |
30a970c6 JB |
3989 | } |
3990 | ||
3991 | /* Adjust CDclk dividers to allow high res or save power if possible */ | |
3992 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
3993 | { | |
3994 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3995 | u32 val, cmd; | |
3996 | ||
3997 | if (cdclk >= 320) /* jump to highest voltage for 400MHz too */ | |
3998 | cmd = 2; | |
3999 | else if (cdclk == 266) | |
4000 | cmd = 1; | |
4001 | else | |
4002 | cmd = 0; | |
4003 | ||
4004 | mutex_lock(&dev_priv->rps.hw_lock); | |
4005 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
4006 | val &= ~DSPFREQGUAR_MASK; | |
4007 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
4008 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
4009 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
4010 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
4011 | 50)) { | |
4012 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
4013 | } | |
4014 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4015 | ||
4016 | if (cdclk == 400) { | |
4017 | u32 divider, vco; | |
4018 | ||
4019 | vco = valleyview_get_vco(dev_priv); | |
4020 | divider = ((vco << 1) / cdclk) - 1; | |
4021 | ||
4022 | mutex_lock(&dev_priv->dpio_lock); | |
4023 | /* adjust cdclk divider */ | |
4024 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
4025 | val &= ~0xf; | |
4026 | val |= divider; | |
4027 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
4028 | mutex_unlock(&dev_priv->dpio_lock); | |
4029 | } | |
4030 | ||
4031 | mutex_lock(&dev_priv->dpio_lock); | |
4032 | /* adjust self-refresh exit latency value */ | |
4033 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
4034 | val &= ~0x7f; | |
4035 | ||
4036 | /* | |
4037 | * For high bandwidth configs, we set a higher latency in the bunit | |
4038 | * so that the core display fetch happens in time to avoid underruns. | |
4039 | */ | |
4040 | if (cdclk == 400) | |
4041 | val |= 4500 / 250; /* 4.5 usec */ | |
4042 | else | |
4043 | val |= 3000 / 250; /* 3.0 usec */ | |
4044 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
4045 | mutex_unlock(&dev_priv->dpio_lock); | |
4046 | ||
4047 | /* Since we changed the CDclk, we need to update the GMBUSFREQ too */ | |
4048 | intel_i2c_reset(dev); | |
4049 | } | |
4050 | ||
4051 | static int valleyview_cur_cdclk(struct drm_i915_private *dev_priv) | |
4052 | { | |
4053 | int cur_cdclk, vco; | |
4054 | int divider; | |
4055 | ||
4056 | vco = valleyview_get_vco(dev_priv); | |
4057 | ||
4058 | mutex_lock(&dev_priv->dpio_lock); | |
4059 | divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
4060 | mutex_unlock(&dev_priv->dpio_lock); | |
4061 | ||
4062 | divider &= 0xf; | |
4063 | ||
4064 | cur_cdclk = (vco << 1) / (divider + 1); | |
4065 | ||
4066 | return cur_cdclk; | |
4067 | } | |
4068 | ||
4069 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, | |
4070 | int max_pixclk) | |
4071 | { | |
4072 | int cur_cdclk; | |
4073 | ||
4074 | cur_cdclk = valleyview_cur_cdclk(dev_priv); | |
4075 | ||
4076 | /* | |
4077 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
4078 | * 200MHz | |
4079 | * 267MHz | |
4080 | * 320MHz | |
4081 | * 400MHz | |
4082 | * So we check to see whether we're above 90% of the lower bin and | |
4083 | * adjust if needed. | |
4084 | */ | |
4085 | if (max_pixclk > 288000) { | |
4086 | return 400; | |
4087 | } else if (max_pixclk > 240000) { | |
4088 | return 320; | |
4089 | } else | |
4090 | return 266; | |
4091 | /* Looks like the 200MHz CDclk freq doesn't work on some configs */ | |
4092 | } | |
4093 | ||
2f2d7aa1 VS |
4094 | /* compute the max pixel clock for new configuration */ |
4095 | static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv) | |
30a970c6 JB |
4096 | { |
4097 | struct drm_device *dev = dev_priv->dev; | |
4098 | struct intel_crtc *intel_crtc; | |
4099 | int max_pixclk = 0; | |
4100 | ||
4101 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, | |
4102 | base.head) { | |
2f2d7aa1 | 4103 | if (intel_crtc->new_enabled) |
30a970c6 | 4104 | max_pixclk = max(max_pixclk, |
2f2d7aa1 | 4105 | intel_crtc->new_config->adjusted_mode.crtc_clock); |
30a970c6 JB |
4106 | } |
4107 | ||
4108 | return max_pixclk; | |
4109 | } | |
4110 | ||
4111 | static void valleyview_modeset_global_pipes(struct drm_device *dev, | |
2f2d7aa1 | 4112 | unsigned *prepare_pipes) |
30a970c6 JB |
4113 | { |
4114 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4115 | struct intel_crtc *intel_crtc; | |
2f2d7aa1 | 4116 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 JB |
4117 | int cur_cdclk = valleyview_cur_cdclk(dev_priv); |
4118 | ||
4119 | if (valleyview_calc_cdclk(dev_priv, max_pixclk) == cur_cdclk) | |
4120 | return; | |
4121 | ||
2f2d7aa1 | 4122 | /* disable/enable all currently active pipes while we change cdclk */ |
30a970c6 JB |
4123 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
4124 | base.head) | |
4125 | if (intel_crtc->base.enabled) | |
4126 | *prepare_pipes |= (1 << intel_crtc->pipe); | |
4127 | } | |
4128 | ||
4129 | static void valleyview_modeset_global_resources(struct drm_device *dev) | |
4130 | { | |
4131 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2f2d7aa1 | 4132 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 JB |
4133 | int cur_cdclk = valleyview_cur_cdclk(dev_priv); |
4134 | int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); | |
4135 | ||
4136 | if (req_cdclk != cur_cdclk) | |
4137 | valleyview_set_cdclk(dev, req_cdclk); | |
4138 | } | |
4139 | ||
89b667f8 JB |
4140 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
4141 | { | |
4142 | struct drm_device *dev = crtc->dev; | |
4143 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4144 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4145 | struct intel_encoder *encoder; | |
4146 | int pipe = intel_crtc->pipe; | |
4147 | int plane = intel_crtc->plane; | |
23538ef1 | 4148 | bool is_dsi; |
89b667f8 JB |
4149 | |
4150 | WARN_ON(!crtc->enabled); | |
4151 | ||
4152 | if (intel_crtc->active) | |
4153 | return; | |
4154 | ||
4155 | intel_crtc->active = true; | |
89b667f8 | 4156 | |
89b667f8 JB |
4157 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4158 | if (encoder->pre_pll_enable) | |
4159 | encoder->pre_pll_enable(encoder); | |
4160 | ||
23538ef1 JN |
4161 | is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI); |
4162 | ||
e9fd1c02 JN |
4163 | if (!is_dsi) |
4164 | vlv_enable_pll(intel_crtc); | |
89b667f8 JB |
4165 | |
4166 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
4167 | if (encoder->pre_enable) | |
4168 | encoder->pre_enable(encoder); | |
4169 | ||
2dd24552 JB |
4170 | i9xx_pfit_enable(intel_crtc); |
4171 | ||
63cbb074 VS |
4172 | intel_crtc_load_lut(crtc); |
4173 | ||
f37fcc2a | 4174 | intel_update_watermarks(crtc); |
23538ef1 | 4175 | intel_enable_pipe(dev_priv, pipe, false, is_dsi); |
2d9d2b0b | 4176 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
d1de00ef | 4177 | intel_enable_primary_plane(dev_priv, plane, pipe); |
bb53d4ae | 4178 | intel_enable_planes(crtc); |
5c38d48c | 4179 | intel_crtc_update_cursor(crtc, true); |
89b667f8 | 4180 | |
89b667f8 | 4181 | intel_update_fbc(dev); |
5004945f JN |
4182 | |
4183 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
4184 | encoder->enable(encoder); | |
89b667f8 JB |
4185 | } |
4186 | ||
0b8765c6 | 4187 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
4188 | { |
4189 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
4190 | struct drm_i915_private *dev_priv = dev->dev_private; |
4191 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4192 | struct intel_encoder *encoder; |
79e53945 | 4193 | int pipe = intel_crtc->pipe; |
80824003 | 4194 | int plane = intel_crtc->plane; |
79e53945 | 4195 | |
08a48469 DV |
4196 | WARN_ON(!crtc->enabled); |
4197 | ||
f7abfe8b CW |
4198 | if (intel_crtc->active) |
4199 | return; | |
4200 | ||
4201 | intel_crtc->active = true; | |
6b383a7f | 4202 | |
9d6d9f19 MK |
4203 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4204 | if (encoder->pre_enable) | |
4205 | encoder->pre_enable(encoder); | |
4206 | ||
f6736a1a DV |
4207 | i9xx_enable_pll(intel_crtc); |
4208 | ||
2dd24552 JB |
4209 | i9xx_pfit_enable(intel_crtc); |
4210 | ||
63cbb074 VS |
4211 | intel_crtc_load_lut(crtc); |
4212 | ||
f37fcc2a | 4213 | intel_update_watermarks(crtc); |
23538ef1 | 4214 | intel_enable_pipe(dev_priv, pipe, false, false); |
2d9d2b0b | 4215 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
d1de00ef | 4216 | intel_enable_primary_plane(dev_priv, plane, pipe); |
bb53d4ae | 4217 | intel_enable_planes(crtc); |
22e407d7 | 4218 | /* The fixup needs to happen before cursor is enabled */ |
61bc95c1 EE |
4219 | if (IS_G4X(dev)) |
4220 | g4x_fixup_plane(dev_priv, pipe); | |
22e407d7 | 4221 | intel_crtc_update_cursor(crtc, true); |
79e53945 | 4222 | |
0b8765c6 JB |
4223 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
4224 | intel_crtc_dpms_overlay(intel_crtc, true); | |
ef9c3aee | 4225 | |
f440eb13 | 4226 | intel_update_fbc(dev); |
ef9c3aee | 4227 | |
fa5c73b1 DV |
4228 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4229 | encoder->enable(encoder); | |
0b8765c6 | 4230 | } |
79e53945 | 4231 | |
87476d63 DV |
4232 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
4233 | { | |
4234 | struct drm_device *dev = crtc->base.dev; | |
4235 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 4236 | |
328d8e82 DV |
4237 | if (!crtc->config.gmch_pfit.control) |
4238 | return; | |
87476d63 | 4239 | |
328d8e82 | 4240 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 4241 | |
328d8e82 DV |
4242 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
4243 | I915_READ(PFIT_CONTROL)); | |
4244 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
4245 | } |
4246 | ||
0b8765c6 JB |
4247 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
4248 | { | |
4249 | struct drm_device *dev = crtc->dev; | |
4250 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4251 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4252 | struct intel_encoder *encoder; |
0b8765c6 JB |
4253 | int pipe = intel_crtc->pipe; |
4254 | int plane = intel_crtc->plane; | |
ef9c3aee | 4255 | |
f7abfe8b CW |
4256 | if (!intel_crtc->active) |
4257 | return; | |
4258 | ||
ea9d758d DV |
4259 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4260 | encoder->disable(encoder); | |
4261 | ||
0b8765c6 | 4262 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
e6c3a2a6 CW |
4263 | intel_crtc_wait_for_pending_flips(crtc); |
4264 | drm_vblank_off(dev, pipe); | |
0b8765c6 | 4265 | |
5c3fe8b0 | 4266 | if (dev_priv->fbc.plane == plane) |
973d04f9 | 4267 | intel_disable_fbc(dev); |
79e53945 | 4268 | |
0d5b8c61 VS |
4269 | intel_crtc_dpms_overlay(intel_crtc, false); |
4270 | intel_crtc_update_cursor(crtc, false); | |
bb53d4ae | 4271 | intel_disable_planes(crtc); |
d1de00ef | 4272 | intel_disable_primary_plane(dev_priv, plane, pipe); |
0d5b8c61 | 4273 | |
2d9d2b0b | 4274 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false); |
b24e7179 | 4275 | intel_disable_pipe(dev_priv, pipe); |
24a1f16d | 4276 | |
87476d63 | 4277 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 4278 | |
89b667f8 JB |
4279 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4280 | if (encoder->post_disable) | |
4281 | encoder->post_disable(encoder); | |
4282 | ||
f6071166 JB |
4283 | if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) |
4284 | vlv_disable_pll(dev_priv, pipe); | |
4285 | else if (!IS_VALLEYVIEW(dev)) | |
e9fd1c02 | 4286 | i9xx_disable_pll(dev_priv, pipe); |
0b8765c6 | 4287 | |
f7abfe8b | 4288 | intel_crtc->active = false; |
46ba614c | 4289 | intel_update_watermarks(crtc); |
f37fcc2a | 4290 | |
6b383a7f | 4291 | intel_update_fbc(dev); |
0b8765c6 JB |
4292 | } |
4293 | ||
ee7b9f93 JB |
4294 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
4295 | { | |
4296 | } | |
4297 | ||
976f8a20 DV |
4298 | static void intel_crtc_update_sarea(struct drm_crtc *crtc, |
4299 | bool enabled) | |
2c07245f ZW |
4300 | { |
4301 | struct drm_device *dev = crtc->dev; | |
4302 | struct drm_i915_master_private *master_priv; | |
4303 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4304 | int pipe = intel_crtc->pipe; | |
79e53945 JB |
4305 | |
4306 | if (!dev->primary->master) | |
4307 | return; | |
4308 | ||
4309 | master_priv = dev->primary->master->driver_priv; | |
4310 | if (!master_priv->sarea_priv) | |
4311 | return; | |
4312 | ||
79e53945 JB |
4313 | switch (pipe) { |
4314 | case 0: | |
4315 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
4316 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
4317 | break; | |
4318 | case 1: | |
4319 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
4320 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
4321 | break; | |
4322 | default: | |
9db4a9c7 | 4323 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
79e53945 JB |
4324 | break; |
4325 | } | |
79e53945 JB |
4326 | } |
4327 | ||
976f8a20 DV |
4328 | /** |
4329 | * Sets the power management mode of the pipe and plane. | |
4330 | */ | |
4331 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
4332 | { | |
4333 | struct drm_device *dev = crtc->dev; | |
4334 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4335 | struct intel_encoder *intel_encoder; | |
4336 | bool enable = false; | |
4337 | ||
4338 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
4339 | enable |= intel_encoder->connectors_active; | |
4340 | ||
4341 | if (enable) | |
4342 | dev_priv->display.crtc_enable(crtc); | |
4343 | else | |
4344 | dev_priv->display.crtc_disable(crtc); | |
4345 | ||
4346 | intel_crtc_update_sarea(crtc, enable); | |
4347 | } | |
4348 | ||
cdd59983 CW |
4349 | static void intel_crtc_disable(struct drm_crtc *crtc) |
4350 | { | |
cdd59983 | 4351 | struct drm_device *dev = crtc->dev; |
976f8a20 | 4352 | struct drm_connector *connector; |
ee7b9f93 | 4353 | struct drm_i915_private *dev_priv = dev->dev_private; |
7b9f35a6 | 4354 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cdd59983 | 4355 | |
976f8a20 DV |
4356 | /* crtc should still be enabled when we disable it. */ |
4357 | WARN_ON(!crtc->enabled); | |
4358 | ||
4359 | dev_priv->display.crtc_disable(crtc); | |
c77bf565 | 4360 | intel_crtc->eld_vld = false; |
976f8a20 | 4361 | intel_crtc_update_sarea(crtc, false); |
ee7b9f93 JB |
4362 | dev_priv->display.off(crtc); |
4363 | ||
931872fc | 4364 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
93ce0ba6 | 4365 | assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe); |
931872fc | 4366 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); |
cdd59983 CW |
4367 | |
4368 | if (crtc->fb) { | |
4369 | mutex_lock(&dev->struct_mutex); | |
1690e1eb | 4370 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); |
cdd59983 | 4371 | mutex_unlock(&dev->struct_mutex); |
976f8a20 DV |
4372 | crtc->fb = NULL; |
4373 | } | |
4374 | ||
4375 | /* Update computed state. */ | |
4376 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4377 | if (!connector->encoder || !connector->encoder->crtc) | |
4378 | continue; | |
4379 | ||
4380 | if (connector->encoder->crtc != crtc) | |
4381 | continue; | |
4382 | ||
4383 | connector->dpms = DRM_MODE_DPMS_OFF; | |
4384 | to_intel_encoder(connector->encoder)->connectors_active = false; | |
cdd59983 CW |
4385 | } |
4386 | } | |
4387 | ||
ea5b213a | 4388 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 4389 | { |
4ef69c7a | 4390 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 4391 | |
ea5b213a CW |
4392 | drm_encoder_cleanup(encoder); |
4393 | kfree(intel_encoder); | |
7e7d76c3 JB |
4394 | } |
4395 | ||
9237329d | 4396 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
5ab432ef DV |
4397 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
4398 | * state of the entire output pipe. */ | |
9237329d | 4399 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
7e7d76c3 | 4400 | { |
5ab432ef DV |
4401 | if (mode == DRM_MODE_DPMS_ON) { |
4402 | encoder->connectors_active = true; | |
4403 | ||
b2cabb0e | 4404 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
4405 | } else { |
4406 | encoder->connectors_active = false; | |
4407 | ||
b2cabb0e | 4408 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 4409 | } |
79e53945 JB |
4410 | } |
4411 | ||
0a91ca29 DV |
4412 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
4413 | * internal consistency). */ | |
b980514c | 4414 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 4415 | { |
0a91ca29 DV |
4416 | if (connector->get_hw_state(connector)) { |
4417 | struct intel_encoder *encoder = connector->encoder; | |
4418 | struct drm_crtc *crtc; | |
4419 | bool encoder_enabled; | |
4420 | enum pipe pipe; | |
4421 | ||
4422 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
4423 | connector->base.base.id, | |
4424 | drm_get_connector_name(&connector->base)); | |
4425 | ||
4426 | WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, | |
4427 | "wrong connector dpms state\n"); | |
4428 | WARN(connector->base.encoder != &encoder->base, | |
4429 | "active connector not linked to encoder\n"); | |
4430 | WARN(!encoder->connectors_active, | |
4431 | "encoder->connectors_active not set\n"); | |
4432 | ||
4433 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
4434 | WARN(!encoder_enabled, "encoder not enabled\n"); | |
4435 | if (WARN_ON(!encoder->base.crtc)) | |
4436 | return; | |
4437 | ||
4438 | crtc = encoder->base.crtc; | |
4439 | ||
4440 | WARN(!crtc->enabled, "crtc not enabled\n"); | |
4441 | WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); | |
4442 | WARN(pipe != to_intel_crtc(crtc)->pipe, | |
4443 | "encoder active on the wrong pipe\n"); | |
4444 | } | |
79e53945 JB |
4445 | } |
4446 | ||
5ab432ef DV |
4447 | /* Even simpler default implementation, if there's really no special case to |
4448 | * consider. */ | |
4449 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 4450 | { |
5ab432ef DV |
4451 | /* All the simple cases only support two dpms states. */ |
4452 | if (mode != DRM_MODE_DPMS_ON) | |
4453 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 4454 | |
5ab432ef DV |
4455 | if (mode == connector->dpms) |
4456 | return; | |
4457 | ||
4458 | connector->dpms = mode; | |
4459 | ||
4460 | /* Only need to change hw state when actually enabled */ | |
c9976dcf CW |
4461 | if (connector->encoder) |
4462 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); | |
0a91ca29 | 4463 | |
b980514c | 4464 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
4465 | } |
4466 | ||
f0947c37 DV |
4467 | /* Simple connector->get_hw_state implementation for encoders that support only |
4468 | * one connector and no cloning and hence the encoder state determines the state | |
4469 | * of the connector. */ | |
4470 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 4471 | { |
24929352 | 4472 | enum pipe pipe = 0; |
f0947c37 | 4473 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 4474 | |
f0947c37 | 4475 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
4476 | } |
4477 | ||
1857e1da DV |
4478 | static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
4479 | struct intel_crtc_config *pipe_config) | |
4480 | { | |
4481 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4482 | struct intel_crtc *pipe_B_crtc = | |
4483 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
4484 | ||
4485 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", | |
4486 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4487 | if (pipe_config->fdi_lanes > 4) { | |
4488 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
4489 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4490 | return false; | |
4491 | } | |
4492 | ||
bafb6553 | 4493 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
4494 | if (pipe_config->fdi_lanes > 2) { |
4495 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
4496 | pipe_config->fdi_lanes); | |
4497 | return false; | |
4498 | } else { | |
4499 | return true; | |
4500 | } | |
4501 | } | |
4502 | ||
4503 | if (INTEL_INFO(dev)->num_pipes == 2) | |
4504 | return true; | |
4505 | ||
4506 | /* Ivybridge 3 pipe is really complicated */ | |
4507 | switch (pipe) { | |
4508 | case PIPE_A: | |
4509 | return true; | |
4510 | case PIPE_B: | |
4511 | if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && | |
4512 | pipe_config->fdi_lanes > 2) { | |
4513 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
4514 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4515 | return false; | |
4516 | } | |
4517 | return true; | |
4518 | case PIPE_C: | |
1e833f40 | 4519 | if (!pipe_has_enabled_pch(pipe_B_crtc) || |
1857e1da DV |
4520 | pipe_B_crtc->config.fdi_lanes <= 2) { |
4521 | if (pipe_config->fdi_lanes > 2) { | |
4522 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
4523 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4524 | return false; | |
4525 | } | |
4526 | } else { | |
4527 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); | |
4528 | return false; | |
4529 | } | |
4530 | return true; | |
4531 | default: | |
4532 | BUG(); | |
4533 | } | |
4534 | } | |
4535 | ||
e29c22c0 DV |
4536 | #define RETRY 1 |
4537 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
4538 | struct intel_crtc_config *pipe_config) | |
877d48d5 | 4539 | { |
1857e1da | 4540 | struct drm_device *dev = intel_crtc->base.dev; |
877d48d5 | 4541 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
ff9a6750 | 4542 | int lane, link_bw, fdi_dotclock; |
e29c22c0 | 4543 | bool setup_ok, needs_recompute = false; |
877d48d5 | 4544 | |
e29c22c0 | 4545 | retry: |
877d48d5 DV |
4546 | /* FDI is a binary signal running at ~2.7GHz, encoding |
4547 | * each output octet as 10 bits. The actual frequency | |
4548 | * is stored as a divider into a 100MHz clock, and the | |
4549 | * mode pixel clock is stored in units of 1KHz. | |
4550 | * Hence the bw of each lane in terms of the mode signal | |
4551 | * is: | |
4552 | */ | |
4553 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
4554 | ||
241bfc38 | 4555 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 4556 | |
2bd89a07 | 4557 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
4558 | pipe_config->pipe_bpp); |
4559 | ||
4560 | pipe_config->fdi_lanes = lane; | |
4561 | ||
2bd89a07 | 4562 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 4563 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 4564 | |
e29c22c0 DV |
4565 | setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
4566 | intel_crtc->pipe, pipe_config); | |
4567 | if (!setup_ok && pipe_config->pipe_bpp > 6*3) { | |
4568 | pipe_config->pipe_bpp -= 2*3; | |
4569 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
4570 | pipe_config->pipe_bpp); | |
4571 | needs_recompute = true; | |
4572 | pipe_config->bw_constrained = true; | |
4573 | ||
4574 | goto retry; | |
4575 | } | |
4576 | ||
4577 | if (needs_recompute) | |
4578 | return RETRY; | |
4579 | ||
4580 | return setup_ok ? 0 : -EINVAL; | |
877d48d5 DV |
4581 | } |
4582 | ||
42db64ef PZ |
4583 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
4584 | struct intel_crtc_config *pipe_config) | |
4585 | { | |
d330a953 | 4586 | pipe_config->ips_enabled = i915.enable_ips && |
3c4ca58c | 4587 | hsw_crtc_supports_ips(crtc) && |
b6dfdc9b | 4588 | pipe_config->pipe_bpp <= 24; |
42db64ef PZ |
4589 | } |
4590 | ||
a43f6e0f | 4591 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
e29c22c0 | 4592 | struct intel_crtc_config *pipe_config) |
79e53945 | 4593 | { |
a43f6e0f | 4594 | struct drm_device *dev = crtc->base.dev; |
b8cecdf5 | 4595 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
89749350 | 4596 | |
ad3a4479 | 4597 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 VS |
4598 | if (INTEL_INFO(dev)->gen < 4) { |
4599 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4600 | int clock_limit = | |
4601 | dev_priv->display.get_display_clock_speed(dev); | |
4602 | ||
4603 | /* | |
4604 | * Enable pixel doubling when the dot clock | |
4605 | * is > 90% of the (display) core speed. | |
4606 | * | |
b397c96b VS |
4607 | * GDG double wide on either pipe, |
4608 | * otherwise pipe A only. | |
cf532bb2 | 4609 | */ |
b397c96b | 4610 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
241bfc38 | 4611 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
ad3a4479 | 4612 | clock_limit *= 2; |
cf532bb2 | 4613 | pipe_config->double_wide = true; |
ad3a4479 VS |
4614 | } |
4615 | ||
241bfc38 | 4616 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
e29c22c0 | 4617 | return -EINVAL; |
2c07245f | 4618 | } |
89749350 | 4619 | |
1d1d0e27 VS |
4620 | /* |
4621 | * Pipe horizontal size must be even in: | |
4622 | * - DVO ganged mode | |
4623 | * - LVDS dual channel mode | |
4624 | * - Double wide pipe | |
4625 | */ | |
4626 | if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && | |
4627 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) | |
4628 | pipe_config->pipe_src_w &= ~1; | |
4629 | ||
8693a824 DL |
4630 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
4631 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
4632 | */ |
4633 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
4634 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
e29c22c0 | 4635 | return -EINVAL; |
44f46b42 | 4636 | |
bd080ee5 | 4637 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { |
5d2d38dd | 4638 | pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ |
bd080ee5 | 4639 | } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { |
5d2d38dd DV |
4640 | /* only a 8bpc pipe, with 6bpc dither through the panel fitter |
4641 | * for lvds. */ | |
4642 | pipe_config->pipe_bpp = 8*3; | |
4643 | } | |
4644 | ||
f5adf94e | 4645 | if (HAS_IPS(dev)) |
a43f6e0f DV |
4646 | hsw_compute_ips_config(crtc, pipe_config); |
4647 | ||
4648 | /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old | |
4649 | * clock survives for now. */ | |
4650 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
4651 | pipe_config->shared_dpll = crtc->config.shared_dpll; | |
42db64ef | 4652 | |
877d48d5 | 4653 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 4654 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 4655 | |
e29c22c0 | 4656 | return 0; |
79e53945 JB |
4657 | } |
4658 | ||
25eb05fc JB |
4659 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
4660 | { | |
4661 | return 400000; /* FIXME */ | |
4662 | } | |
4663 | ||
e70236a8 JB |
4664 | static int i945_get_display_clock_speed(struct drm_device *dev) |
4665 | { | |
4666 | return 400000; | |
4667 | } | |
79e53945 | 4668 | |
e70236a8 | 4669 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 4670 | { |
e70236a8 JB |
4671 | return 333000; |
4672 | } | |
79e53945 | 4673 | |
e70236a8 JB |
4674 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
4675 | { | |
4676 | return 200000; | |
4677 | } | |
79e53945 | 4678 | |
257a7ffc DV |
4679 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
4680 | { | |
4681 | u16 gcfgc = 0; | |
4682 | ||
4683 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
4684 | ||
4685 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
4686 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
4687 | return 267000; | |
4688 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: | |
4689 | return 333000; | |
4690 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: | |
4691 | return 444000; | |
4692 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: | |
4693 | return 200000; | |
4694 | default: | |
4695 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
4696 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
4697 | return 133000; | |
4698 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: | |
4699 | return 167000; | |
4700 | } | |
4701 | } | |
4702 | ||
e70236a8 JB |
4703 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
4704 | { | |
4705 | u16 gcfgc = 0; | |
79e53945 | 4706 | |
e70236a8 JB |
4707 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
4708 | ||
4709 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
4710 | return 133000; | |
4711 | else { | |
4712 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
4713 | case GC_DISPLAY_CLOCK_333_MHZ: | |
4714 | return 333000; | |
4715 | default: | |
4716 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
4717 | return 190000; | |
79e53945 | 4718 | } |
e70236a8 JB |
4719 | } |
4720 | } | |
4721 | ||
4722 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
4723 | { | |
4724 | return 266000; | |
4725 | } | |
4726 | ||
4727 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
4728 | { | |
4729 | u16 hpllcc = 0; | |
4730 | /* Assume that the hardware is in the high speed state. This | |
4731 | * should be the default. | |
4732 | */ | |
4733 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
4734 | case GC_CLOCK_133_200: | |
4735 | case GC_CLOCK_100_200: | |
4736 | return 200000; | |
4737 | case GC_CLOCK_166_250: | |
4738 | return 250000; | |
4739 | case GC_CLOCK_100_133: | |
79e53945 | 4740 | return 133000; |
e70236a8 | 4741 | } |
79e53945 | 4742 | |
e70236a8 JB |
4743 | /* Shouldn't happen */ |
4744 | return 0; | |
4745 | } | |
79e53945 | 4746 | |
e70236a8 JB |
4747 | static int i830_get_display_clock_speed(struct drm_device *dev) |
4748 | { | |
4749 | return 133000; | |
79e53945 JB |
4750 | } |
4751 | ||
2c07245f | 4752 | static void |
a65851af | 4753 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 4754 | { |
a65851af VS |
4755 | while (*num > DATA_LINK_M_N_MASK || |
4756 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
4757 | *num >>= 1; |
4758 | *den >>= 1; | |
4759 | } | |
4760 | } | |
4761 | ||
a65851af VS |
4762 | static void compute_m_n(unsigned int m, unsigned int n, |
4763 | uint32_t *ret_m, uint32_t *ret_n) | |
4764 | { | |
4765 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
4766 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
4767 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
4768 | } | |
4769 | ||
e69d0bc1 DV |
4770 | void |
4771 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
4772 | int pixel_clock, int link_clock, | |
4773 | struct intel_link_m_n *m_n) | |
2c07245f | 4774 | { |
e69d0bc1 | 4775 | m_n->tu = 64; |
a65851af VS |
4776 | |
4777 | compute_m_n(bits_per_pixel * pixel_clock, | |
4778 | link_clock * nlanes * 8, | |
4779 | &m_n->gmch_m, &m_n->gmch_n); | |
4780 | ||
4781 | compute_m_n(pixel_clock, link_clock, | |
4782 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
4783 | } |
4784 | ||
a7615030 CW |
4785 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
4786 | { | |
d330a953 JN |
4787 | if (i915.panel_use_ssc >= 0) |
4788 | return i915.panel_use_ssc != 0; | |
41aa3448 | 4789 | return dev_priv->vbt.lvds_use_ssc |
435793df | 4790 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
4791 | } |
4792 | ||
c65d77d8 JB |
4793 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
4794 | { | |
4795 | struct drm_device *dev = crtc->dev; | |
4796 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4797 | int refclk; | |
4798 | ||
a0c4da24 | 4799 | if (IS_VALLEYVIEW(dev)) { |
9a0ea498 | 4800 | refclk = 100000; |
a0c4da24 | 4801 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 4802 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
4803 | refclk = dev_priv->vbt.lvds_ssc_freq; |
4804 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
4805 | } else if (!IS_GEN2(dev)) { |
4806 | refclk = 96000; | |
4807 | } else { | |
4808 | refclk = 48000; | |
4809 | } | |
4810 | ||
4811 | return refclk; | |
4812 | } | |
4813 | ||
7429e9d4 | 4814 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 4815 | { |
7df00d7a | 4816 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 4817 | } |
f47709a9 | 4818 | |
7429e9d4 DV |
4819 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
4820 | { | |
4821 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
4822 | } |
4823 | ||
f47709a9 | 4824 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
a7516a05 JB |
4825 | intel_clock_t *reduced_clock) |
4826 | { | |
f47709a9 | 4827 | struct drm_device *dev = crtc->base.dev; |
a7516a05 | 4828 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 4829 | int pipe = crtc->pipe; |
a7516a05 JB |
4830 | u32 fp, fp2 = 0; |
4831 | ||
4832 | if (IS_PINEVIEW(dev)) { | |
7429e9d4 | 4833 | fp = pnv_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 4834 | if (reduced_clock) |
7429e9d4 | 4835 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 4836 | } else { |
7429e9d4 | 4837 | fp = i9xx_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 4838 | if (reduced_clock) |
7429e9d4 | 4839 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
4840 | } |
4841 | ||
4842 | I915_WRITE(FP0(pipe), fp); | |
8bcc2795 | 4843 | crtc->config.dpll_hw_state.fp0 = fp; |
a7516a05 | 4844 | |
f47709a9 DV |
4845 | crtc->lowfreq_avail = false; |
4846 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && | |
d330a953 | 4847 | reduced_clock && i915.powersave) { |
a7516a05 | 4848 | I915_WRITE(FP1(pipe), fp2); |
8bcc2795 | 4849 | crtc->config.dpll_hw_state.fp1 = fp2; |
f47709a9 | 4850 | crtc->lowfreq_avail = true; |
a7516a05 JB |
4851 | } else { |
4852 | I915_WRITE(FP1(pipe), fp); | |
8bcc2795 | 4853 | crtc->config.dpll_hw_state.fp1 = fp; |
a7516a05 JB |
4854 | } |
4855 | } | |
4856 | ||
5e69f97f CML |
4857 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
4858 | pipe) | |
89b667f8 JB |
4859 | { |
4860 | u32 reg_val; | |
4861 | ||
4862 | /* | |
4863 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
4864 | * and set it to a reasonable value instead. | |
4865 | */ | |
ab3c759a | 4866 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
4867 | reg_val &= 0xffffff00; |
4868 | reg_val |= 0x00000030; | |
ab3c759a | 4869 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 4870 | |
ab3c759a | 4871 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
4872 | reg_val &= 0x8cffffff; |
4873 | reg_val = 0x8c000000; | |
ab3c759a | 4874 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 4875 | |
ab3c759a | 4876 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 4877 | reg_val &= 0xffffff00; |
ab3c759a | 4878 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 4879 | |
ab3c759a | 4880 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
4881 | reg_val &= 0x00ffffff; |
4882 | reg_val |= 0xb0000000; | |
ab3c759a | 4883 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
4884 | } |
4885 | ||
b551842d DV |
4886 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
4887 | struct intel_link_m_n *m_n) | |
4888 | { | |
4889 | struct drm_device *dev = crtc->base.dev; | |
4890 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4891 | int pipe = crtc->pipe; | |
4892 | ||
e3b95f1e DV |
4893 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
4894 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
4895 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
4896 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
4897 | } |
4898 | ||
4899 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
4900 | struct intel_link_m_n *m_n) | |
4901 | { | |
4902 | struct drm_device *dev = crtc->base.dev; | |
4903 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4904 | int pipe = crtc->pipe; | |
4905 | enum transcoder transcoder = crtc->config.cpu_transcoder; | |
4906 | ||
4907 | if (INTEL_INFO(dev)->gen >= 5) { | |
4908 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
4909 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
4910 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
4911 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
4912 | } else { | |
e3b95f1e DV |
4913 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
4914 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
4915 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
4916 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
4917 | } |
4918 | } | |
4919 | ||
03afc4a2 DV |
4920 | static void intel_dp_set_m_n(struct intel_crtc *crtc) |
4921 | { | |
4922 | if (crtc->config.has_pch_encoder) | |
4923 | intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
4924 | else | |
4925 | intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
4926 | } | |
4927 | ||
f47709a9 | 4928 | static void vlv_update_pll(struct intel_crtc *crtc) |
a0c4da24 | 4929 | { |
f47709a9 | 4930 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 4931 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 4932 | int pipe = crtc->pipe; |
89b667f8 | 4933 | u32 dpll, mdiv; |
a0c4da24 | 4934 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
198a037f | 4935 | u32 coreclk, reg_val, dpll_md; |
a0c4da24 | 4936 | |
09153000 DV |
4937 | mutex_lock(&dev_priv->dpio_lock); |
4938 | ||
f47709a9 DV |
4939 | bestn = crtc->config.dpll.n; |
4940 | bestm1 = crtc->config.dpll.m1; | |
4941 | bestm2 = crtc->config.dpll.m2; | |
4942 | bestp1 = crtc->config.dpll.p1; | |
4943 | bestp2 = crtc->config.dpll.p2; | |
a0c4da24 | 4944 | |
89b667f8 JB |
4945 | /* See eDP HDMI DPIO driver vbios notes doc */ |
4946 | ||
4947 | /* PLL B needs special handling */ | |
4948 | if (pipe) | |
5e69f97f | 4949 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
4950 | |
4951 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 4952 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
4953 | |
4954 | /* Disable target IRef on PLL */ | |
ab3c759a | 4955 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 4956 | reg_val &= 0x00ffffff; |
ab3c759a | 4957 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
4958 | |
4959 | /* Disable fast lock */ | |
ab3c759a | 4960 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
4961 | |
4962 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
4963 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
4964 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
4965 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 4966 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
4967 | |
4968 | /* | |
4969 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
4970 | * but we don't support that). | |
4971 | * Note: don't use the DAC post divider as it seems unstable. | |
4972 | */ | |
4973 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 4974 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 4975 | |
a0c4da24 | 4976 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 4977 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 4978 | |
89b667f8 | 4979 | /* Set HBR and RBR LPF coefficients */ |
ff9a6750 | 4980 | if (crtc->config.port_clock == 162000 || |
99750bd4 | 4981 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) || |
89b667f8 | 4982 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) |
ab3c759a | 4983 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 4984 | 0x009f0003); |
89b667f8 | 4985 | else |
ab3c759a | 4986 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
4987 | 0x00d0000f); |
4988 | ||
4989 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) || | |
4990 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) { | |
4991 | /* Use SSC source */ | |
4992 | if (!pipe) | |
ab3c759a | 4993 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
4994 | 0x0df40000); |
4995 | else | |
ab3c759a | 4996 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
4997 | 0x0df70000); |
4998 | } else { /* HDMI or VGA */ | |
4999 | /* Use bend source */ | |
5000 | if (!pipe) | |
ab3c759a | 5001 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5002 | 0x0df70000); |
5003 | else | |
ab3c759a | 5004 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5005 | 0x0df40000); |
5006 | } | |
a0c4da24 | 5007 | |
ab3c759a | 5008 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 JB |
5009 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
5010 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) || | |
5011 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) | |
5012 | coreclk |= 0x01000000; | |
ab3c759a | 5013 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 5014 | |
ab3c759a | 5015 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a0c4da24 | 5016 | |
e5cbfbfb ID |
5017 | /* |
5018 | * Enable DPIO clock input. We should never disable the reference | |
5019 | * clock for pipe B, since VGA hotplug / manual detection depends | |
5020 | * on it. | |
5021 | */ | |
89b667f8 JB |
5022 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | |
5023 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; | |
f6071166 JB |
5024 | /* We should never disable this, set it here for state tracking */ |
5025 | if (pipe == PIPE_B) | |
89b667f8 | 5026 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
a0c4da24 | 5027 | dpll |= DPLL_VCO_ENABLE; |
8bcc2795 DV |
5028 | crtc->config.dpll_hw_state.dpll = dpll; |
5029 | ||
ef1b460d DV |
5030 | dpll_md = (crtc->config.pixel_multiplier - 1) |
5031 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
8bcc2795 DV |
5032 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
5033 | ||
89b667f8 JB |
5034 | if (crtc->config.has_dp_encoder) |
5035 | intel_dp_set_m_n(crtc); | |
09153000 DV |
5036 | |
5037 | mutex_unlock(&dev_priv->dpio_lock); | |
a0c4da24 JB |
5038 | } |
5039 | ||
f47709a9 DV |
5040 | static void i9xx_update_pll(struct intel_crtc *crtc, |
5041 | intel_clock_t *reduced_clock, | |
eb1cbe48 DV |
5042 | int num_connectors) |
5043 | { | |
f47709a9 | 5044 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 5045 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
5046 | u32 dpll; |
5047 | bool is_sdvo; | |
f47709a9 | 5048 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 5049 | |
f47709a9 | 5050 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 5051 | |
f47709a9 DV |
5052 | is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) || |
5053 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
5054 | |
5055 | dpll = DPLL_VGA_MODE_DIS; | |
5056 | ||
f47709a9 | 5057 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
5058 | dpll |= DPLLB_MODE_LVDS; |
5059 | else | |
5060 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 5061 | |
ef1b460d | 5062 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
198a037f DV |
5063 | dpll |= (crtc->config.pixel_multiplier - 1) |
5064 | << SDVO_MULTIPLIER_SHIFT_HIRES; | |
eb1cbe48 | 5065 | } |
198a037f DV |
5066 | |
5067 | if (is_sdvo) | |
4a33e48d | 5068 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 5069 | |
f47709a9 | 5070 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) |
4a33e48d | 5071 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
5072 | |
5073 | /* compute bitmask from p1 value */ | |
5074 | if (IS_PINEVIEW(dev)) | |
5075 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
5076 | else { | |
5077 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5078 | if (IS_G4X(dev) && reduced_clock) | |
5079 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
5080 | } | |
5081 | switch (clock->p2) { | |
5082 | case 5: | |
5083 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
5084 | break; | |
5085 | case 7: | |
5086 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
5087 | break; | |
5088 | case 10: | |
5089 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
5090 | break; | |
5091 | case 14: | |
5092 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
5093 | break; | |
5094 | } | |
5095 | if (INTEL_INFO(dev)->gen >= 4) | |
5096 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
5097 | ||
09ede541 | 5098 | if (crtc->config.sdvo_tv_clock) |
eb1cbe48 | 5099 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
f47709a9 | 5100 | else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
5101 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5102 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
5103 | else | |
5104 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5105 | ||
5106 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 DV |
5107 | crtc->config.dpll_hw_state.dpll = dpll; |
5108 | ||
eb1cbe48 | 5109 | if (INTEL_INFO(dev)->gen >= 4) { |
ef1b460d DV |
5110 | u32 dpll_md = (crtc->config.pixel_multiplier - 1) |
5111 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
8bcc2795 | 5112 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 | 5113 | } |
66e3d5c0 DV |
5114 | |
5115 | if (crtc->config.has_dp_encoder) | |
5116 | intel_dp_set_m_n(crtc); | |
eb1cbe48 DV |
5117 | } |
5118 | ||
f47709a9 | 5119 | static void i8xx_update_pll(struct intel_crtc *crtc, |
f47709a9 | 5120 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
5121 | int num_connectors) |
5122 | { | |
f47709a9 | 5123 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 5124 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 5125 | u32 dpll; |
f47709a9 | 5126 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 5127 | |
f47709a9 | 5128 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 5129 | |
eb1cbe48 DV |
5130 | dpll = DPLL_VGA_MODE_DIS; |
5131 | ||
f47709a9 | 5132 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
5133 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
5134 | } else { | |
5135 | if (clock->p1 == 2) | |
5136 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
5137 | else | |
5138 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5139 | if (clock->p2 == 4) | |
5140 | dpll |= PLL_P2_DIVIDE_BY_4; | |
5141 | } | |
5142 | ||
4a33e48d DV |
5143 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO)) |
5144 | dpll |= DPLL_DVO_2X_MODE; | |
5145 | ||
f47709a9 | 5146 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
5147 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5148 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
5149 | else | |
5150 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5151 | ||
5152 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 | 5153 | crtc->config.dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
5154 | } |
5155 | ||
8a654f3b | 5156 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
5157 | { |
5158 | struct drm_device *dev = intel_crtc->base.dev; | |
5159 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5160 | enum pipe pipe = intel_crtc->pipe; | |
3b117c8f | 5161 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
8a654f3b DV |
5162 | struct drm_display_mode *adjusted_mode = |
5163 | &intel_crtc->config.adjusted_mode; | |
4d8a62ea DV |
5164 | uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end; |
5165 | ||
5166 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
5167 | * the hw state checker will get angry at the mismatch. */ | |
5168 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
5169 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c PZ |
5170 | |
5171 | if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
5172 | /* the chip adds 2 halflines automatically */ | |
4d8a62ea DV |
5173 | crtc_vtotal -= 1; |
5174 | crtc_vblank_end -= 1; | |
b0e77b9c PZ |
5175 | vsyncshift = adjusted_mode->crtc_hsync_start |
5176 | - adjusted_mode->crtc_htotal / 2; | |
5177 | } else { | |
5178 | vsyncshift = 0; | |
5179 | } | |
5180 | ||
5181 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 5182 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 5183 | |
fe2b8f9d | 5184 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
5185 | (adjusted_mode->crtc_hdisplay - 1) | |
5186 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 5187 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
5188 | (adjusted_mode->crtc_hblank_start - 1) | |
5189 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 5190 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
5191 | (adjusted_mode->crtc_hsync_start - 1) | |
5192 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
5193 | ||
fe2b8f9d | 5194 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 5195 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 5196 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 5197 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 5198 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 5199 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 5200 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
5201 | (adjusted_mode->crtc_vsync_start - 1) | |
5202 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
5203 | ||
b5e508d4 PZ |
5204 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
5205 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
5206 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
5207 | * bits. */ | |
5208 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
5209 | (pipe == PIPE_B || pipe == PIPE_C)) | |
5210 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
5211 | ||
b0e77b9c PZ |
5212 | /* pipesrc controls the size that is scaled from, which should |
5213 | * always be the user's requested size. | |
5214 | */ | |
5215 | I915_WRITE(PIPESRC(pipe), | |
37327abd VS |
5216 | ((intel_crtc->config.pipe_src_w - 1) << 16) | |
5217 | (intel_crtc->config.pipe_src_h - 1)); | |
b0e77b9c PZ |
5218 | } |
5219 | ||
1bd1bd80 DV |
5220 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5221 | struct intel_crtc_config *pipe_config) | |
5222 | { | |
5223 | struct drm_device *dev = crtc->base.dev; | |
5224 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5225 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
5226 | uint32_t tmp; | |
5227 | ||
5228 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
5229 | pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; | |
5230 | pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
5231 | tmp = I915_READ(HBLANK(cpu_transcoder)); | |
5232 | pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; | |
5233 | pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
5234 | tmp = I915_READ(HSYNC(cpu_transcoder)); | |
5235 | pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; | |
5236 | pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
5237 | ||
5238 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
5239 | pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; | |
5240 | pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
5241 | tmp = I915_READ(VBLANK(cpu_transcoder)); | |
5242 | pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; | |
5243 | pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
5244 | tmp = I915_READ(VSYNC(cpu_transcoder)); | |
5245 | pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; | |
5246 | pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
5247 | ||
5248 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
5249 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; | |
5250 | pipe_config->adjusted_mode.crtc_vtotal += 1; | |
5251 | pipe_config->adjusted_mode.crtc_vblank_end += 1; | |
5252 | } | |
5253 | ||
5254 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
5255 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
5256 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
5257 | ||
5258 | pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h; | |
5259 | pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
5260 | } |
5261 | ||
babea61d JB |
5262 | static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc, |
5263 | struct intel_crtc_config *pipe_config) | |
5264 | { | |
5265 | struct drm_crtc *crtc = &intel_crtc->base; | |
5266 | ||
5267 | crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay; | |
5268 | crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal; | |
5269 | crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start; | |
5270 | crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end; | |
5271 | ||
5272 | crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay; | |
5273 | crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal; | |
5274 | crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start; | |
5275 | crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end; | |
5276 | ||
5277 | crtc->mode.flags = pipe_config->adjusted_mode.flags; | |
5278 | ||
241bfc38 | 5279 | crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock; |
babea61d JB |
5280 | crtc->mode.flags |= pipe_config->adjusted_mode.flags; |
5281 | } | |
5282 | ||
84b046f3 DV |
5283 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
5284 | { | |
5285 | struct drm_device *dev = intel_crtc->base.dev; | |
5286 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5287 | uint32_t pipeconf; | |
5288 | ||
9f11a9e4 | 5289 | pipeconf = 0; |
84b046f3 | 5290 | |
67c72a12 DV |
5291 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
5292 | I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE) | |
5293 | pipeconf |= PIPECONF_ENABLE; | |
5294 | ||
cf532bb2 VS |
5295 | if (intel_crtc->config.double_wide) |
5296 | pipeconf |= PIPECONF_DOUBLE_WIDE; | |
84b046f3 | 5297 | |
ff9ce46e DV |
5298 | /* only g4x and later have fancy bpc/dither controls */ |
5299 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
ff9ce46e DV |
5300 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
5301 | if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30) | |
5302 | pipeconf |= PIPECONF_DITHER_EN | | |
84b046f3 | 5303 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 5304 | |
ff9ce46e DV |
5305 | switch (intel_crtc->config.pipe_bpp) { |
5306 | case 18: | |
5307 | pipeconf |= PIPECONF_6BPC; | |
5308 | break; | |
5309 | case 24: | |
5310 | pipeconf |= PIPECONF_8BPC; | |
5311 | break; | |
5312 | case 30: | |
5313 | pipeconf |= PIPECONF_10BPC; | |
5314 | break; | |
5315 | default: | |
5316 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
5317 | BUG(); | |
84b046f3 DV |
5318 | } |
5319 | } | |
5320 | ||
5321 | if (HAS_PIPE_CXSR(dev)) { | |
5322 | if (intel_crtc->lowfreq_avail) { | |
5323 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
5324 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
5325 | } else { | |
5326 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
5327 | } |
5328 | } | |
5329 | ||
84b046f3 DV |
5330 | if (!IS_GEN2(dev) && |
5331 | intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) | |
5332 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; | |
5333 | else | |
5334 | pipeconf |= PIPECONF_PROGRESSIVE; | |
5335 | ||
9f11a9e4 DV |
5336 | if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range) |
5337 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; | |
9c8e09b7 | 5338 | |
84b046f3 DV |
5339 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
5340 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
5341 | } | |
5342 | ||
f564048e | 5343 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
f564048e | 5344 | int x, int y, |
94352cf9 | 5345 | struct drm_framebuffer *fb) |
79e53945 JB |
5346 | { |
5347 | struct drm_device *dev = crtc->dev; | |
5348 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5349 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5350 | int pipe = intel_crtc->pipe; | |
80824003 | 5351 | int plane = intel_crtc->plane; |
c751ce4f | 5352 | int refclk, num_connectors = 0; |
652c393a | 5353 | intel_clock_t clock, reduced_clock; |
84b046f3 | 5354 | u32 dspcntr; |
a16af721 | 5355 | bool ok, has_reduced_clock = false; |
e9fd1c02 | 5356 | bool is_lvds = false, is_dsi = false; |
5eddb70b | 5357 | struct intel_encoder *encoder; |
d4906093 | 5358 | const intel_limit_t *limit; |
5c3b82e2 | 5359 | int ret; |
79e53945 | 5360 | |
6c2b7c12 | 5361 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5eddb70b | 5362 | switch (encoder->type) { |
79e53945 JB |
5363 | case INTEL_OUTPUT_LVDS: |
5364 | is_lvds = true; | |
5365 | break; | |
e9fd1c02 JN |
5366 | case INTEL_OUTPUT_DSI: |
5367 | is_dsi = true; | |
5368 | break; | |
79e53945 | 5369 | } |
43565a06 | 5370 | |
c751ce4f | 5371 | num_connectors++; |
79e53945 JB |
5372 | } |
5373 | ||
f2335330 JN |
5374 | if (is_dsi) |
5375 | goto skip_dpll; | |
5376 | ||
5377 | if (!intel_crtc->config.clock_set) { | |
5378 | refclk = i9xx_get_refclk(crtc, num_connectors); | |
79e53945 | 5379 | |
e9fd1c02 JN |
5380 | /* |
5381 | * Returns a set of divisors for the desired target clock with | |
5382 | * the given refclk, or FALSE. The returned values represent | |
5383 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
5384 | * 2) / p1 / p2. | |
5385 | */ | |
5386 | limit = intel_limit(crtc, refclk); | |
5387 | ok = dev_priv->display.find_dpll(limit, crtc, | |
5388 | intel_crtc->config.port_clock, | |
5389 | refclk, NULL, &clock); | |
f2335330 | 5390 | if (!ok) { |
e9fd1c02 JN |
5391 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
5392 | return -EINVAL; | |
5393 | } | |
79e53945 | 5394 | |
f2335330 JN |
5395 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
5396 | /* | |
5397 | * Ensure we match the reduced clock's P to the target | |
5398 | * clock. If the clocks don't match, we can't switch | |
5399 | * the display clock by using the FP0/FP1. In such case | |
5400 | * we will disable the LVDS downclock feature. | |
5401 | */ | |
5402 | has_reduced_clock = | |
5403 | dev_priv->display.find_dpll(limit, crtc, | |
5404 | dev_priv->lvds_downclock, | |
5405 | refclk, &clock, | |
5406 | &reduced_clock); | |
5407 | } | |
5408 | /* Compat-code for transition, will disappear. */ | |
f47709a9 DV |
5409 | intel_crtc->config.dpll.n = clock.n; |
5410 | intel_crtc->config.dpll.m1 = clock.m1; | |
5411 | intel_crtc->config.dpll.m2 = clock.m2; | |
5412 | intel_crtc->config.dpll.p1 = clock.p1; | |
5413 | intel_crtc->config.dpll.p2 = clock.p2; | |
5414 | } | |
7026d4ac | 5415 | |
e9fd1c02 | 5416 | if (IS_GEN2(dev)) { |
8a654f3b | 5417 | i8xx_update_pll(intel_crtc, |
2a8f64ca VP |
5418 | has_reduced_clock ? &reduced_clock : NULL, |
5419 | num_connectors); | |
e9fd1c02 | 5420 | } else if (IS_VALLEYVIEW(dev)) { |
f2335330 | 5421 | vlv_update_pll(intel_crtc); |
e9fd1c02 | 5422 | } else { |
f47709a9 | 5423 | i9xx_update_pll(intel_crtc, |
eb1cbe48 | 5424 | has_reduced_clock ? &reduced_clock : NULL, |
89b667f8 | 5425 | num_connectors); |
e9fd1c02 | 5426 | } |
79e53945 | 5427 | |
f2335330 | 5428 | skip_dpll: |
79e53945 JB |
5429 | /* Set up the display plane register */ |
5430 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
5431 | ||
da6ecc5d JB |
5432 | if (!IS_VALLEYVIEW(dev)) { |
5433 | if (pipe == 0) | |
5434 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; | |
5435 | else | |
5436 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
5437 | } | |
79e53945 | 5438 | |
8a654f3b | 5439 | intel_set_pipe_timings(intel_crtc); |
5eddb70b CW |
5440 | |
5441 | /* pipesrc and dspsize control the size that is scaled from, | |
5442 | * which should always be the user's requested size. | |
79e53945 | 5443 | */ |
929c77fb | 5444 | I915_WRITE(DSPSIZE(plane), |
37327abd VS |
5445 | ((intel_crtc->config.pipe_src_h - 1) << 16) | |
5446 | (intel_crtc->config.pipe_src_w - 1)); | |
929c77fb | 5447 | I915_WRITE(DSPPOS(plane), 0); |
2c07245f | 5448 | |
84b046f3 DV |
5449 | i9xx_set_pipeconf(intel_crtc); |
5450 | ||
f564048e EA |
5451 | I915_WRITE(DSPCNTR(plane), dspcntr); |
5452 | POSTING_READ(DSPCNTR(plane)); | |
5453 | ||
94352cf9 | 5454 | ret = intel_pipe_set_base(crtc, x, y, fb); |
f564048e | 5455 | |
f564048e EA |
5456 | return ret; |
5457 | } | |
5458 | ||
2fa2fe9a DV |
5459 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5460 | struct intel_crtc_config *pipe_config) | |
5461 | { | |
5462 | struct drm_device *dev = crtc->base.dev; | |
5463 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5464 | uint32_t tmp; | |
5465 | ||
dc9e7dec VS |
5466 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
5467 | return; | |
5468 | ||
2fa2fe9a | 5469 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
5470 | if (!(tmp & PFIT_ENABLE)) |
5471 | return; | |
2fa2fe9a | 5472 | |
06922821 | 5473 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
5474 | if (INTEL_INFO(dev)->gen < 4) { |
5475 | if (crtc->pipe != PIPE_B) | |
5476 | return; | |
2fa2fe9a DV |
5477 | } else { |
5478 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
5479 | return; | |
5480 | } | |
5481 | ||
06922821 | 5482 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
5483 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
5484 | if (INTEL_INFO(dev)->gen < 5) | |
5485 | pipe_config->gmch_pfit.lvds_border_bits = | |
5486 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
5487 | } | |
5488 | ||
acbec814 JB |
5489 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5490 | struct intel_crtc_config *pipe_config) | |
5491 | { | |
5492 | struct drm_device *dev = crtc->base.dev; | |
5493 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5494 | int pipe = pipe_config->cpu_transcoder; | |
5495 | intel_clock_t clock; | |
5496 | u32 mdiv; | |
662c6ecb | 5497 | int refclk = 100000; |
acbec814 JB |
5498 | |
5499 | mutex_lock(&dev_priv->dpio_lock); | |
ab3c759a | 5500 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
acbec814 JB |
5501 | mutex_unlock(&dev_priv->dpio_lock); |
5502 | ||
5503 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
5504 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
5505 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
5506 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
5507 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
5508 | ||
f646628b | 5509 | vlv_clock(refclk, &clock); |
acbec814 | 5510 | |
f646628b VS |
5511 | /* clock.dot is the fast clock */ |
5512 | pipe_config->port_clock = clock.dot / 5; | |
acbec814 JB |
5513 | } |
5514 | ||
0e8ffe1b DV |
5515 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5516 | struct intel_crtc_config *pipe_config) | |
5517 | { | |
5518 | struct drm_device *dev = crtc->base.dev; | |
5519 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5520 | uint32_t tmp; | |
5521 | ||
e143a21c | 5522 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 5523 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 5524 | |
0e8ffe1b DV |
5525 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
5526 | if (!(tmp & PIPECONF_ENABLE)) | |
5527 | return false; | |
5528 | ||
42571aef VS |
5529 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
5530 | switch (tmp & PIPECONF_BPC_MASK) { | |
5531 | case PIPECONF_6BPC: | |
5532 | pipe_config->pipe_bpp = 18; | |
5533 | break; | |
5534 | case PIPECONF_8BPC: | |
5535 | pipe_config->pipe_bpp = 24; | |
5536 | break; | |
5537 | case PIPECONF_10BPC: | |
5538 | pipe_config->pipe_bpp = 30; | |
5539 | break; | |
5540 | default: | |
5541 | break; | |
5542 | } | |
5543 | } | |
5544 | ||
282740f7 VS |
5545 | if (INTEL_INFO(dev)->gen < 4) |
5546 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
5547 | ||
1bd1bd80 DV |
5548 | intel_get_pipe_timings(crtc, pipe_config); |
5549 | ||
2fa2fe9a DV |
5550 | i9xx_get_pfit_config(crtc, pipe_config); |
5551 | ||
6c49f241 DV |
5552 | if (INTEL_INFO(dev)->gen >= 4) { |
5553 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
5554 | pipe_config->pixel_multiplier = | |
5555 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
5556 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 5557 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
5558 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
5559 | tmp = I915_READ(DPLL(crtc->pipe)); | |
5560 | pipe_config->pixel_multiplier = | |
5561 | ((tmp & SDVO_MULTIPLIER_MASK) | |
5562 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
5563 | } else { | |
5564 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
5565 | * port and will be fixed up in the encoder->get_config | |
5566 | * function. */ | |
5567 | pipe_config->pixel_multiplier = 1; | |
5568 | } | |
8bcc2795 DV |
5569 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
5570 | if (!IS_VALLEYVIEW(dev)) { | |
5571 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); | |
5572 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
5573 | } else { |
5574 | /* Mask out read-only status bits. */ | |
5575 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
5576 | DPLL_PORTC_READY_MASK | | |
5577 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 5578 | } |
6c49f241 | 5579 | |
acbec814 JB |
5580 | if (IS_VALLEYVIEW(dev)) |
5581 | vlv_crtc_clock_get(crtc, pipe_config); | |
5582 | else | |
5583 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 5584 | |
0e8ffe1b DV |
5585 | return true; |
5586 | } | |
5587 | ||
dde86e2d | 5588 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
5589 | { |
5590 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5591 | struct drm_mode_config *mode_config = &dev->mode_config; | |
13d83a67 | 5592 | struct intel_encoder *encoder; |
74cfd7ac | 5593 | u32 val, final; |
13d83a67 | 5594 | bool has_lvds = false; |
199e5d79 | 5595 | bool has_cpu_edp = false; |
199e5d79 | 5596 | bool has_panel = false; |
99eb6a01 KP |
5597 | bool has_ck505 = false; |
5598 | bool can_ssc = false; | |
13d83a67 JB |
5599 | |
5600 | /* We need to take the global config into account */ | |
199e5d79 KP |
5601 | list_for_each_entry(encoder, &mode_config->encoder_list, |
5602 | base.head) { | |
5603 | switch (encoder->type) { | |
5604 | case INTEL_OUTPUT_LVDS: | |
5605 | has_panel = true; | |
5606 | has_lvds = true; | |
5607 | break; | |
5608 | case INTEL_OUTPUT_EDP: | |
5609 | has_panel = true; | |
2de6905f | 5610 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
5611 | has_cpu_edp = true; |
5612 | break; | |
13d83a67 JB |
5613 | } |
5614 | } | |
5615 | ||
99eb6a01 | 5616 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 5617 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
5618 | can_ssc = has_ck505; |
5619 | } else { | |
5620 | has_ck505 = false; | |
5621 | can_ssc = true; | |
5622 | } | |
5623 | ||
2de6905f ID |
5624 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
5625 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
5626 | |
5627 | /* Ironlake: try to setup display ref clock before DPLL | |
5628 | * enabling. This is only under driver's control after | |
5629 | * PCH B stepping, previous chipset stepping should be | |
5630 | * ignoring this setting. | |
5631 | */ | |
74cfd7ac CW |
5632 | val = I915_READ(PCH_DREF_CONTROL); |
5633 | ||
5634 | /* As we must carefully and slowly disable/enable each source in turn, | |
5635 | * compute the final state we want first and check if we need to | |
5636 | * make any changes at all. | |
5637 | */ | |
5638 | final = val; | |
5639 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
5640 | if (has_ck505) | |
5641 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
5642 | else | |
5643 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
5644 | ||
5645 | final &= ~DREF_SSC_SOURCE_MASK; | |
5646 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
5647 | final &= ~DREF_SSC1_ENABLE; | |
5648 | ||
5649 | if (has_panel) { | |
5650 | final |= DREF_SSC_SOURCE_ENABLE; | |
5651 | ||
5652 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
5653 | final |= DREF_SSC1_ENABLE; | |
5654 | ||
5655 | if (has_cpu_edp) { | |
5656 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
5657 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
5658 | else | |
5659 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
5660 | } else | |
5661 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
5662 | } else { | |
5663 | final |= DREF_SSC_SOURCE_DISABLE; | |
5664 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
5665 | } | |
5666 | ||
5667 | if (final == val) | |
5668 | return; | |
5669 | ||
13d83a67 | 5670 | /* Always enable nonspread source */ |
74cfd7ac | 5671 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 5672 | |
99eb6a01 | 5673 | if (has_ck505) |
74cfd7ac | 5674 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 5675 | else |
74cfd7ac | 5676 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 5677 | |
199e5d79 | 5678 | if (has_panel) { |
74cfd7ac CW |
5679 | val &= ~DREF_SSC_SOURCE_MASK; |
5680 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 5681 | |
199e5d79 | 5682 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 5683 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 5684 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 5685 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 5686 | } else |
74cfd7ac | 5687 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
5688 | |
5689 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 5690 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
5691 | POSTING_READ(PCH_DREF_CONTROL); |
5692 | udelay(200); | |
5693 | ||
74cfd7ac | 5694 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
5695 | |
5696 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 5697 | if (has_cpu_edp) { |
99eb6a01 | 5698 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 5699 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 5700 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
199e5d79 | 5701 | } |
13d83a67 | 5702 | else |
74cfd7ac | 5703 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 5704 | } else |
74cfd7ac | 5705 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 5706 | |
74cfd7ac | 5707 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
5708 | POSTING_READ(PCH_DREF_CONTROL); |
5709 | udelay(200); | |
5710 | } else { | |
5711 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
5712 | ||
74cfd7ac | 5713 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
5714 | |
5715 | /* Turn off CPU output */ | |
74cfd7ac | 5716 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 5717 | |
74cfd7ac | 5718 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
5719 | POSTING_READ(PCH_DREF_CONTROL); |
5720 | udelay(200); | |
5721 | ||
5722 | /* Turn off the SSC source */ | |
74cfd7ac CW |
5723 | val &= ~DREF_SSC_SOURCE_MASK; |
5724 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
5725 | |
5726 | /* Turn off SSC1 */ | |
74cfd7ac | 5727 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 5728 | |
74cfd7ac | 5729 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
5730 | POSTING_READ(PCH_DREF_CONTROL); |
5731 | udelay(200); | |
5732 | } | |
74cfd7ac CW |
5733 | |
5734 | BUG_ON(val != final); | |
13d83a67 JB |
5735 | } |
5736 | ||
f31f2d55 | 5737 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 5738 | { |
f31f2d55 | 5739 | uint32_t tmp; |
dde86e2d | 5740 | |
0ff066a9 PZ |
5741 | tmp = I915_READ(SOUTH_CHICKEN2); |
5742 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
5743 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 5744 | |
0ff066a9 PZ |
5745 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
5746 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
5747 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 5748 | |
0ff066a9 PZ |
5749 | tmp = I915_READ(SOUTH_CHICKEN2); |
5750 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
5751 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 5752 | |
0ff066a9 PZ |
5753 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
5754 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
5755 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
5756 | } |
5757 | ||
5758 | /* WaMPhyProgramming:hsw */ | |
5759 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
5760 | { | |
5761 | uint32_t tmp; | |
dde86e2d PZ |
5762 | |
5763 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
5764 | tmp &= ~(0xFF << 24); | |
5765 | tmp |= (0x12 << 24); | |
5766 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
5767 | ||
dde86e2d PZ |
5768 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
5769 | tmp |= (1 << 11); | |
5770 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
5771 | ||
5772 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
5773 | tmp |= (1 << 11); | |
5774 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
5775 | ||
dde86e2d PZ |
5776 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
5777 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
5778 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
5779 | ||
5780 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
5781 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
5782 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
5783 | ||
0ff066a9 PZ |
5784 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
5785 | tmp &= ~(7 << 13); | |
5786 | tmp |= (5 << 13); | |
5787 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 5788 | |
0ff066a9 PZ |
5789 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
5790 | tmp &= ~(7 << 13); | |
5791 | tmp |= (5 << 13); | |
5792 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
5793 | |
5794 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
5795 | tmp &= ~0xFF; | |
5796 | tmp |= 0x1C; | |
5797 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
5798 | ||
5799 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
5800 | tmp &= ~0xFF; | |
5801 | tmp |= 0x1C; | |
5802 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
5803 | ||
5804 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
5805 | tmp &= ~(0xFF << 16); | |
5806 | tmp |= (0x1C << 16); | |
5807 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
5808 | ||
5809 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
5810 | tmp &= ~(0xFF << 16); | |
5811 | tmp |= (0x1C << 16); | |
5812 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
5813 | ||
0ff066a9 PZ |
5814 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
5815 | tmp |= (1 << 27); | |
5816 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 5817 | |
0ff066a9 PZ |
5818 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
5819 | tmp |= (1 << 27); | |
5820 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 5821 | |
0ff066a9 PZ |
5822 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
5823 | tmp &= ~(0xF << 28); | |
5824 | tmp |= (4 << 28); | |
5825 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 5826 | |
0ff066a9 PZ |
5827 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
5828 | tmp &= ~(0xF << 28); | |
5829 | tmp |= (4 << 28); | |
5830 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
5831 | } |
5832 | ||
2fa86a1f PZ |
5833 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
5834 | * Programming" based on the parameters passed: | |
5835 | * - Sequence to enable CLKOUT_DP | |
5836 | * - Sequence to enable CLKOUT_DP without spread | |
5837 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
5838 | */ | |
5839 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
5840 | bool with_fdi) | |
f31f2d55 PZ |
5841 | { |
5842 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
5843 | uint32_t reg, tmp; |
5844 | ||
5845 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
5846 | with_spread = true; | |
5847 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && | |
5848 | with_fdi, "LP PCH doesn't have FDI\n")) | |
5849 | with_fdi = false; | |
f31f2d55 PZ |
5850 | |
5851 | mutex_lock(&dev_priv->dpio_lock); | |
5852 | ||
5853 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
5854 | tmp &= ~SBI_SSCCTL_DISABLE; | |
5855 | tmp |= SBI_SSCCTL_PATHALT; | |
5856 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
5857 | ||
5858 | udelay(24); | |
5859 | ||
2fa86a1f PZ |
5860 | if (with_spread) { |
5861 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
5862 | tmp &= ~SBI_SSCCTL_PATHALT; | |
5863 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 5864 | |
2fa86a1f PZ |
5865 | if (with_fdi) { |
5866 | lpt_reset_fdi_mphy(dev_priv); | |
5867 | lpt_program_fdi_mphy(dev_priv); | |
5868 | } | |
5869 | } | |
dde86e2d | 5870 | |
2fa86a1f PZ |
5871 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
5872 | SBI_GEN0 : SBI_DBUFF0; | |
5873 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
5874 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
5875 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 DV |
5876 | |
5877 | mutex_unlock(&dev_priv->dpio_lock); | |
dde86e2d PZ |
5878 | } |
5879 | ||
47701c3b PZ |
5880 | /* Sequence to disable CLKOUT_DP */ |
5881 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
5882 | { | |
5883 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5884 | uint32_t reg, tmp; | |
5885 | ||
5886 | mutex_lock(&dev_priv->dpio_lock); | |
5887 | ||
5888 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? | |
5889 | SBI_GEN0 : SBI_DBUFF0; | |
5890 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
5891 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
5892 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
5893 | ||
5894 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
5895 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
5896 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
5897 | tmp |= SBI_SSCCTL_PATHALT; | |
5898 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
5899 | udelay(32); | |
5900 | } | |
5901 | tmp |= SBI_SSCCTL_DISABLE; | |
5902 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
5903 | } | |
5904 | ||
5905 | mutex_unlock(&dev_priv->dpio_lock); | |
5906 | } | |
5907 | ||
bf8fa3d3 PZ |
5908 | static void lpt_init_pch_refclk(struct drm_device *dev) |
5909 | { | |
5910 | struct drm_mode_config *mode_config = &dev->mode_config; | |
5911 | struct intel_encoder *encoder; | |
5912 | bool has_vga = false; | |
5913 | ||
5914 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { | |
5915 | switch (encoder->type) { | |
5916 | case INTEL_OUTPUT_ANALOG: | |
5917 | has_vga = true; | |
5918 | break; | |
5919 | } | |
5920 | } | |
5921 | ||
47701c3b PZ |
5922 | if (has_vga) |
5923 | lpt_enable_clkout_dp(dev, true, true); | |
5924 | else | |
5925 | lpt_disable_clkout_dp(dev); | |
bf8fa3d3 PZ |
5926 | } |
5927 | ||
dde86e2d PZ |
5928 | /* |
5929 | * Initialize reference clocks when the driver loads | |
5930 | */ | |
5931 | void intel_init_pch_refclk(struct drm_device *dev) | |
5932 | { | |
5933 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
5934 | ironlake_init_pch_refclk(dev); | |
5935 | else if (HAS_PCH_LPT(dev)) | |
5936 | lpt_init_pch_refclk(dev); | |
5937 | } | |
5938 | ||
d9d444cb JB |
5939 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
5940 | { | |
5941 | struct drm_device *dev = crtc->dev; | |
5942 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5943 | struct intel_encoder *encoder; | |
d9d444cb JB |
5944 | int num_connectors = 0; |
5945 | bool is_lvds = false; | |
5946 | ||
6c2b7c12 | 5947 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
d9d444cb JB |
5948 | switch (encoder->type) { |
5949 | case INTEL_OUTPUT_LVDS: | |
5950 | is_lvds = true; | |
5951 | break; | |
d9d444cb JB |
5952 | } |
5953 | num_connectors++; | |
5954 | } | |
5955 | ||
5956 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 5957 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 5958 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 5959 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
5960 | } |
5961 | ||
5962 | return 120000; | |
5963 | } | |
5964 | ||
6ff93609 | 5965 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 5966 | { |
c8203565 | 5967 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
5968 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5969 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
5970 | uint32_t val; |
5971 | ||
78114071 | 5972 | val = 0; |
c8203565 | 5973 | |
965e0c48 | 5974 | switch (intel_crtc->config.pipe_bpp) { |
c8203565 | 5975 | case 18: |
dfd07d72 | 5976 | val |= PIPECONF_6BPC; |
c8203565 PZ |
5977 | break; |
5978 | case 24: | |
dfd07d72 | 5979 | val |= PIPECONF_8BPC; |
c8203565 PZ |
5980 | break; |
5981 | case 30: | |
dfd07d72 | 5982 | val |= PIPECONF_10BPC; |
c8203565 PZ |
5983 | break; |
5984 | case 36: | |
dfd07d72 | 5985 | val |= PIPECONF_12BPC; |
c8203565 PZ |
5986 | break; |
5987 | default: | |
cc769b62 PZ |
5988 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
5989 | BUG(); | |
c8203565 PZ |
5990 | } |
5991 | ||
d8b32247 | 5992 | if (intel_crtc->config.dither) |
c8203565 PZ |
5993 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
5994 | ||
6ff93609 | 5995 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
5996 | val |= PIPECONF_INTERLACED_ILK; |
5997 | else | |
5998 | val |= PIPECONF_PROGRESSIVE; | |
5999 | ||
50f3b016 | 6000 | if (intel_crtc->config.limited_color_range) |
3685a8f3 | 6001 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 6002 | |
c8203565 PZ |
6003 | I915_WRITE(PIPECONF(pipe), val); |
6004 | POSTING_READ(PIPECONF(pipe)); | |
6005 | } | |
6006 | ||
86d3efce VS |
6007 | /* |
6008 | * Set up the pipe CSC unit. | |
6009 | * | |
6010 | * Currently only full range RGB to limited range RGB conversion | |
6011 | * is supported, but eventually this should handle various | |
6012 | * RGB<->YCbCr scenarios as well. | |
6013 | */ | |
50f3b016 | 6014 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
6015 | { |
6016 | struct drm_device *dev = crtc->dev; | |
6017 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6018 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6019 | int pipe = intel_crtc->pipe; | |
6020 | uint16_t coeff = 0x7800; /* 1.0 */ | |
6021 | ||
6022 | /* | |
6023 | * TODO: Check what kind of values actually come out of the pipe | |
6024 | * with these coeff/postoff values and adjust to get the best | |
6025 | * accuracy. Perhaps we even need to take the bpc value into | |
6026 | * consideration. | |
6027 | */ | |
6028 | ||
50f3b016 | 6029 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
6030 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
6031 | ||
6032 | /* | |
6033 | * GY/GU and RY/RU should be the other way around according | |
6034 | * to BSpec, but reality doesn't agree. Just set them up in | |
6035 | * a way that results in the correct picture. | |
6036 | */ | |
6037 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
6038 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
6039 | ||
6040 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
6041 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
6042 | ||
6043 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
6044 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
6045 | ||
6046 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
6047 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
6048 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
6049 | ||
6050 | if (INTEL_INFO(dev)->gen > 6) { | |
6051 | uint16_t postoff = 0; | |
6052 | ||
50f3b016 | 6053 | if (intel_crtc->config.limited_color_range) |
32cf0cb0 | 6054 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
6055 | |
6056 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
6057 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
6058 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
6059 | ||
6060 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
6061 | } else { | |
6062 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
6063 | ||
50f3b016 | 6064 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
6065 | mode |= CSC_BLACK_SCREEN_OFFSET; |
6066 | ||
6067 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
6068 | } | |
6069 | } | |
6070 | ||
6ff93609 | 6071 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 6072 | { |
756f85cf PZ |
6073 | struct drm_device *dev = crtc->dev; |
6074 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 6075 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 6076 | enum pipe pipe = intel_crtc->pipe; |
3b117c8f | 6077 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee2b0b38 PZ |
6078 | uint32_t val; |
6079 | ||
3eff4faa | 6080 | val = 0; |
ee2b0b38 | 6081 | |
756f85cf | 6082 | if (IS_HASWELL(dev) && intel_crtc->config.dither) |
ee2b0b38 PZ |
6083 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
6084 | ||
6ff93609 | 6085 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
6086 | val |= PIPECONF_INTERLACED_ILK; |
6087 | else | |
6088 | val |= PIPECONF_PROGRESSIVE; | |
6089 | ||
702e7a56 PZ |
6090 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
6091 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
6092 | |
6093 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
6094 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf PZ |
6095 | |
6096 | if (IS_BROADWELL(dev)) { | |
6097 | val = 0; | |
6098 | ||
6099 | switch (intel_crtc->config.pipe_bpp) { | |
6100 | case 18: | |
6101 | val |= PIPEMISC_DITHER_6_BPC; | |
6102 | break; | |
6103 | case 24: | |
6104 | val |= PIPEMISC_DITHER_8_BPC; | |
6105 | break; | |
6106 | case 30: | |
6107 | val |= PIPEMISC_DITHER_10_BPC; | |
6108 | break; | |
6109 | case 36: | |
6110 | val |= PIPEMISC_DITHER_12_BPC; | |
6111 | break; | |
6112 | default: | |
6113 | /* Case prevented by pipe_config_set_bpp. */ | |
6114 | BUG(); | |
6115 | } | |
6116 | ||
6117 | if (intel_crtc->config.dither) | |
6118 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; | |
6119 | ||
6120 | I915_WRITE(PIPEMISC(pipe), val); | |
6121 | } | |
ee2b0b38 PZ |
6122 | } |
6123 | ||
6591c6e4 | 6124 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
6591c6e4 PZ |
6125 | intel_clock_t *clock, |
6126 | bool *has_reduced_clock, | |
6127 | intel_clock_t *reduced_clock) | |
6128 | { | |
6129 | struct drm_device *dev = crtc->dev; | |
6130 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6131 | struct intel_encoder *intel_encoder; | |
6132 | int refclk; | |
d4906093 | 6133 | const intel_limit_t *limit; |
a16af721 | 6134 | bool ret, is_lvds = false; |
79e53945 | 6135 | |
6591c6e4 PZ |
6136 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
6137 | switch (intel_encoder->type) { | |
79e53945 JB |
6138 | case INTEL_OUTPUT_LVDS: |
6139 | is_lvds = true; | |
6140 | break; | |
79e53945 JB |
6141 | } |
6142 | } | |
6143 | ||
d9d444cb | 6144 | refclk = ironlake_get_refclk(crtc); |
79e53945 | 6145 | |
d4906093 ML |
6146 | /* |
6147 | * Returns a set of divisors for the desired target clock with the given | |
6148 | * refclk, or FALSE. The returned values represent the clock equation: | |
6149 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
6150 | */ | |
1b894b59 | 6151 | limit = intel_limit(crtc, refclk); |
ff9a6750 DV |
6152 | ret = dev_priv->display.find_dpll(limit, crtc, |
6153 | to_intel_crtc(crtc)->config.port_clock, | |
ee9300bb | 6154 | refclk, NULL, clock); |
6591c6e4 PZ |
6155 | if (!ret) |
6156 | return false; | |
cda4b7d3 | 6157 | |
ddc9003c | 6158 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
6159 | /* |
6160 | * Ensure we match the reduced clock's P to the target clock. | |
6161 | * If the clocks don't match, we can't switch the display clock | |
6162 | * by using the FP0/FP1. In such case we will disable the LVDS | |
6163 | * downclock feature. | |
6164 | */ | |
ee9300bb DV |
6165 | *has_reduced_clock = |
6166 | dev_priv->display.find_dpll(limit, crtc, | |
6167 | dev_priv->lvds_downclock, | |
6168 | refclk, clock, | |
6169 | reduced_clock); | |
652c393a | 6170 | } |
61e9653f | 6171 | |
6591c6e4 PZ |
6172 | return true; |
6173 | } | |
6174 | ||
d4b1931c PZ |
6175 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
6176 | { | |
6177 | /* | |
6178 | * Account for spread spectrum to avoid | |
6179 | * oversubscribing the link. Max center spread | |
6180 | * is 2.5%; use 5% for safety's sake. | |
6181 | */ | |
6182 | u32 bps = target_clock * bpp * 21 / 20; | |
6183 | return bps / (link_bw * 8) + 1; | |
6184 | } | |
6185 | ||
7429e9d4 | 6186 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 6187 | { |
7429e9d4 | 6188 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
6189 | } |
6190 | ||
de13a2e3 | 6191 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
7429e9d4 | 6192 | u32 *fp, |
9a7c7890 | 6193 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 6194 | { |
de13a2e3 | 6195 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
6196 | struct drm_device *dev = crtc->dev; |
6197 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de13a2e3 PZ |
6198 | struct intel_encoder *intel_encoder; |
6199 | uint32_t dpll; | |
6cc5f341 | 6200 | int factor, num_connectors = 0; |
09ede541 | 6201 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 6202 | |
de13a2e3 PZ |
6203 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
6204 | switch (intel_encoder->type) { | |
79e53945 JB |
6205 | case INTEL_OUTPUT_LVDS: |
6206 | is_lvds = true; | |
6207 | break; | |
6208 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 6209 | case INTEL_OUTPUT_HDMI: |
79e53945 | 6210 | is_sdvo = true; |
79e53945 | 6211 | break; |
79e53945 | 6212 | } |
43565a06 | 6213 | |
c751ce4f | 6214 | num_connectors++; |
79e53945 | 6215 | } |
79e53945 | 6216 | |
c1858123 | 6217 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
6218 | factor = 21; |
6219 | if (is_lvds) { | |
6220 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 6221 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 6222 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 6223 | factor = 25; |
09ede541 | 6224 | } else if (intel_crtc->config.sdvo_tv_clock) |
8febb297 | 6225 | factor = 20; |
c1858123 | 6226 | |
7429e9d4 | 6227 | if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor)) |
7d0ac5b7 | 6228 | *fp |= FP_CB_TUNE; |
2c07245f | 6229 | |
9a7c7890 DV |
6230 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
6231 | *fp2 |= FP_CB_TUNE; | |
6232 | ||
5eddb70b | 6233 | dpll = 0; |
2c07245f | 6234 | |
a07d6787 EA |
6235 | if (is_lvds) |
6236 | dpll |= DPLLB_MODE_LVDS; | |
6237 | else | |
6238 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 6239 | |
ef1b460d DV |
6240 | dpll |= (intel_crtc->config.pixel_multiplier - 1) |
6241 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
198a037f DV |
6242 | |
6243 | if (is_sdvo) | |
4a33e48d | 6244 | dpll |= DPLL_SDVO_HIGH_SPEED; |
9566e9af | 6245 | if (intel_crtc->config.has_dp_encoder) |
4a33e48d | 6246 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 6247 | |
a07d6787 | 6248 | /* compute bitmask from p1 value */ |
7429e9d4 | 6249 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 6250 | /* also FPA1 */ |
7429e9d4 | 6251 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 6252 | |
7429e9d4 | 6253 | switch (intel_crtc->config.dpll.p2) { |
a07d6787 EA |
6254 | case 5: |
6255 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
6256 | break; | |
6257 | case 7: | |
6258 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
6259 | break; | |
6260 | case 10: | |
6261 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
6262 | break; | |
6263 | case 14: | |
6264 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
6265 | break; | |
79e53945 JB |
6266 | } |
6267 | ||
b4c09f3b | 6268 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 6269 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
6270 | else |
6271 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6272 | ||
959e16d6 | 6273 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
6274 | } |
6275 | ||
6276 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, | |
de13a2e3 PZ |
6277 | int x, int y, |
6278 | struct drm_framebuffer *fb) | |
6279 | { | |
6280 | struct drm_device *dev = crtc->dev; | |
6281 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6282 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6283 | int pipe = intel_crtc->pipe; | |
6284 | int plane = intel_crtc->plane; | |
6285 | int num_connectors = 0; | |
6286 | intel_clock_t clock, reduced_clock; | |
cbbab5bd | 6287 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 6288 | bool ok, has_reduced_clock = false; |
8b47047b | 6289 | bool is_lvds = false; |
de13a2e3 | 6290 | struct intel_encoder *encoder; |
e2b78267 | 6291 | struct intel_shared_dpll *pll; |
de13a2e3 | 6292 | int ret; |
de13a2e3 PZ |
6293 | |
6294 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
6295 | switch (encoder->type) { | |
6296 | case INTEL_OUTPUT_LVDS: | |
6297 | is_lvds = true; | |
6298 | break; | |
de13a2e3 PZ |
6299 | } |
6300 | ||
6301 | num_connectors++; | |
a07d6787 | 6302 | } |
79e53945 | 6303 | |
5dc5298b PZ |
6304 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
6305 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 6306 | |
ff9a6750 | 6307 | ok = ironlake_compute_clocks(crtc, &clock, |
de13a2e3 | 6308 | &has_reduced_clock, &reduced_clock); |
ee9300bb | 6309 | if (!ok && !intel_crtc->config.clock_set) { |
de13a2e3 PZ |
6310 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
6311 | return -EINVAL; | |
79e53945 | 6312 | } |
f47709a9 DV |
6313 | /* Compat-code for transition, will disappear. */ |
6314 | if (!intel_crtc->config.clock_set) { | |
6315 | intel_crtc->config.dpll.n = clock.n; | |
6316 | intel_crtc->config.dpll.m1 = clock.m1; | |
6317 | intel_crtc->config.dpll.m2 = clock.m2; | |
6318 | intel_crtc->config.dpll.p1 = clock.p1; | |
6319 | intel_crtc->config.dpll.p2 = clock.p2; | |
6320 | } | |
79e53945 | 6321 | |
5dc5298b | 6322 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
8b47047b | 6323 | if (intel_crtc->config.has_pch_encoder) { |
7429e9d4 | 6324 | fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll); |
cbbab5bd | 6325 | if (has_reduced_clock) |
7429e9d4 | 6326 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 6327 | |
7429e9d4 | 6328 | dpll = ironlake_compute_dpll(intel_crtc, |
cbbab5bd DV |
6329 | &fp, &reduced_clock, |
6330 | has_reduced_clock ? &fp2 : NULL); | |
6331 | ||
959e16d6 | 6332 | intel_crtc->config.dpll_hw_state.dpll = dpll; |
66e985c0 DV |
6333 | intel_crtc->config.dpll_hw_state.fp0 = fp; |
6334 | if (has_reduced_clock) | |
6335 | intel_crtc->config.dpll_hw_state.fp1 = fp2; | |
6336 | else | |
6337 | intel_crtc->config.dpll_hw_state.fp1 = fp; | |
6338 | ||
b89a1d39 | 6339 | pll = intel_get_shared_dpll(intel_crtc); |
ee7b9f93 | 6340 | if (pll == NULL) { |
84f44ce7 VS |
6341 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
6342 | pipe_name(pipe)); | |
4b645f14 JB |
6343 | return -EINVAL; |
6344 | } | |
ee7b9f93 | 6345 | } else |
e72f9fbf | 6346 | intel_put_shared_dpll(intel_crtc); |
79e53945 | 6347 | |
03afc4a2 DV |
6348 | if (intel_crtc->config.has_dp_encoder) |
6349 | intel_dp_set_m_n(intel_crtc); | |
79e53945 | 6350 | |
d330a953 | 6351 | if (is_lvds && has_reduced_clock && i915.powersave) |
bcd644e0 DV |
6352 | intel_crtc->lowfreq_avail = true; |
6353 | else | |
6354 | intel_crtc->lowfreq_avail = false; | |
e2b78267 | 6355 | |
8a654f3b | 6356 | intel_set_pipe_timings(intel_crtc); |
5eddb70b | 6357 | |
ca3a0ff8 | 6358 | if (intel_crtc->config.has_pch_encoder) { |
ca3a0ff8 DV |
6359 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6360 | &intel_crtc->config.fdi_m_n); | |
6361 | } | |
2c07245f | 6362 | |
6ff93609 | 6363 | ironlake_set_pipeconf(crtc); |
79e53945 | 6364 | |
a1f9e77e PZ |
6365 | /* Set up the display plane register */ |
6366 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); | |
b24e7179 | 6367 | POSTING_READ(DSPCNTR(plane)); |
79e53945 | 6368 | |
94352cf9 | 6369 | ret = intel_pipe_set_base(crtc, x, y, fb); |
7662c8bd | 6370 | |
1857e1da | 6371 | return ret; |
79e53945 JB |
6372 | } |
6373 | ||
eb14cb74 VS |
6374 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
6375 | struct intel_link_m_n *m_n) | |
6376 | { | |
6377 | struct drm_device *dev = crtc->base.dev; | |
6378 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6379 | enum pipe pipe = crtc->pipe; | |
6380 | ||
6381 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
6382 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
6383 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
6384 | & ~TU_SIZE_MASK; | |
6385 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
6386 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
6387 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
6388 | } | |
6389 | ||
6390 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
6391 | enum transcoder transcoder, | |
6392 | struct intel_link_m_n *m_n) | |
72419203 DV |
6393 | { |
6394 | struct drm_device *dev = crtc->base.dev; | |
6395 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 6396 | enum pipe pipe = crtc->pipe; |
72419203 | 6397 | |
eb14cb74 VS |
6398 | if (INTEL_INFO(dev)->gen >= 5) { |
6399 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
6400 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
6401 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
6402 | & ~TU_SIZE_MASK; | |
6403 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
6404 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
6405 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
6406 | } else { | |
6407 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
6408 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
6409 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
6410 | & ~TU_SIZE_MASK; | |
6411 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
6412 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
6413 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
6414 | } | |
6415 | } | |
6416 | ||
6417 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
6418 | struct intel_crtc_config *pipe_config) | |
6419 | { | |
6420 | if (crtc->config.has_pch_encoder) | |
6421 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); | |
6422 | else | |
6423 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
6424 | &pipe_config->dp_m_n); | |
6425 | } | |
72419203 | 6426 | |
eb14cb74 VS |
6427 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
6428 | struct intel_crtc_config *pipe_config) | |
6429 | { | |
6430 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
6431 | &pipe_config->fdi_m_n); | |
72419203 DV |
6432 | } |
6433 | ||
2fa2fe9a DV |
6434 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
6435 | struct intel_crtc_config *pipe_config) | |
6436 | { | |
6437 | struct drm_device *dev = crtc->base.dev; | |
6438 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6439 | uint32_t tmp; | |
6440 | ||
6441 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
6442 | ||
6443 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 6444 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
6445 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
6446 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
6447 | |
6448 | /* We currently do not free assignements of panel fitters on | |
6449 | * ivb/hsw (since we don't use the higher upscaling modes which | |
6450 | * differentiates them) so just WARN about this case for now. */ | |
6451 | if (IS_GEN7(dev)) { | |
6452 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
6453 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
6454 | } | |
2fa2fe9a | 6455 | } |
79e53945 JB |
6456 | } |
6457 | ||
0e8ffe1b DV |
6458 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
6459 | struct intel_crtc_config *pipe_config) | |
6460 | { | |
6461 | struct drm_device *dev = crtc->base.dev; | |
6462 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6463 | uint32_t tmp; | |
6464 | ||
e143a21c | 6465 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 6466 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 6467 | |
0e8ffe1b DV |
6468 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
6469 | if (!(tmp & PIPECONF_ENABLE)) | |
6470 | return false; | |
6471 | ||
42571aef VS |
6472 | switch (tmp & PIPECONF_BPC_MASK) { |
6473 | case PIPECONF_6BPC: | |
6474 | pipe_config->pipe_bpp = 18; | |
6475 | break; | |
6476 | case PIPECONF_8BPC: | |
6477 | pipe_config->pipe_bpp = 24; | |
6478 | break; | |
6479 | case PIPECONF_10BPC: | |
6480 | pipe_config->pipe_bpp = 30; | |
6481 | break; | |
6482 | case PIPECONF_12BPC: | |
6483 | pipe_config->pipe_bpp = 36; | |
6484 | break; | |
6485 | default: | |
6486 | break; | |
6487 | } | |
6488 | ||
ab9412ba | 6489 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
6490 | struct intel_shared_dpll *pll; |
6491 | ||
88adfff1 DV |
6492 | pipe_config->has_pch_encoder = true; |
6493 | ||
627eb5a3 DV |
6494 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
6495 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
6496 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
6497 | |
6498 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 6499 | |
c0d43d62 | 6500 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
6501 | pipe_config->shared_dpll = |
6502 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
6503 | } else { |
6504 | tmp = I915_READ(PCH_DPLL_SEL); | |
6505 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
6506 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
6507 | else | |
6508 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
6509 | } | |
66e985c0 DV |
6510 | |
6511 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
6512 | ||
6513 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
6514 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
6515 | |
6516 | tmp = pipe_config->dpll_hw_state.dpll; | |
6517 | pipe_config->pixel_multiplier = | |
6518 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
6519 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
6520 | |
6521 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
6522 | } else { |
6523 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
6524 | } |
6525 | ||
1bd1bd80 DV |
6526 | intel_get_pipe_timings(crtc, pipe_config); |
6527 | ||
2fa2fe9a DV |
6528 | ironlake_get_pfit_config(crtc, pipe_config); |
6529 | ||
0e8ffe1b DV |
6530 | return true; |
6531 | } | |
6532 | ||
be256dc7 PZ |
6533 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
6534 | { | |
6535 | struct drm_device *dev = dev_priv->dev; | |
6536 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; | |
6537 | struct intel_crtc *crtc; | |
6538 | unsigned long irqflags; | |
bd633a7c | 6539 | uint32_t val; |
be256dc7 PZ |
6540 | |
6541 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) | |
798183c5 | 6542 | WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
6543 | pipe_name(crtc->pipe)); |
6544 | ||
6545 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); | |
6546 | WARN(plls->spll_refcount, "SPLL enabled\n"); | |
6547 | WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n"); | |
6548 | WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n"); | |
6549 | WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); | |
6550 | WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
6551 | "CPU PWM1 enabled\n"); | |
6552 | WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, | |
6553 | "CPU PWM2 enabled\n"); | |
6554 | WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, | |
6555 | "PCH PWM1 enabled\n"); | |
6556 | WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, | |
6557 | "Utility pin enabled\n"); | |
6558 | WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); | |
6559 | ||
6560 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
6561 | val = I915_READ(DEIMR); | |
6806e63f | 6562 | WARN((val | DE_PCH_EVENT_IVB) != 0xffffffff, |
be256dc7 PZ |
6563 | "Unexpected DEIMR bits enabled: 0x%x\n", val); |
6564 | val = I915_READ(SDEIMR); | |
bd633a7c | 6565 | WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff, |
be256dc7 PZ |
6566 | "Unexpected SDEIMR bits enabled: 0x%x\n", val); |
6567 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
6568 | } | |
6569 | ||
6570 | /* | |
6571 | * This function implements pieces of two sequences from BSpec: | |
6572 | * - Sequence for display software to disable LCPLL | |
6573 | * - Sequence for display software to allow package C8+ | |
6574 | * The steps implemented here are just the steps that actually touch the LCPLL | |
6575 | * register. Callers should take care of disabling all the display engine | |
6576 | * functions, doing the mode unset, fixing interrupts, etc. | |
6577 | */ | |
6ff58d53 PZ |
6578 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
6579 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
6580 | { |
6581 | uint32_t val; | |
6582 | ||
6583 | assert_can_disable_lcpll(dev_priv); | |
6584 | ||
6585 | val = I915_READ(LCPLL_CTL); | |
6586 | ||
6587 | if (switch_to_fclk) { | |
6588 | val |= LCPLL_CD_SOURCE_FCLK; | |
6589 | I915_WRITE(LCPLL_CTL, val); | |
6590 | ||
6591 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
6592 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
6593 | DRM_ERROR("Switching to FCLK failed\n"); | |
6594 | ||
6595 | val = I915_READ(LCPLL_CTL); | |
6596 | } | |
6597 | ||
6598 | val |= LCPLL_PLL_DISABLE; | |
6599 | I915_WRITE(LCPLL_CTL, val); | |
6600 | POSTING_READ(LCPLL_CTL); | |
6601 | ||
6602 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
6603 | DRM_ERROR("LCPLL still locked\n"); | |
6604 | ||
6605 | val = I915_READ(D_COMP); | |
6606 | val |= D_COMP_COMP_DISABLE; | |
515b2392 PZ |
6607 | mutex_lock(&dev_priv->rps.hw_lock); |
6608 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val)) | |
6609 | DRM_ERROR("Failed to disable D_COMP\n"); | |
6610 | mutex_unlock(&dev_priv->rps.hw_lock); | |
be256dc7 PZ |
6611 | POSTING_READ(D_COMP); |
6612 | ndelay(100); | |
6613 | ||
6614 | if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1)) | |
6615 | DRM_ERROR("D_COMP RCOMP still in progress\n"); | |
6616 | ||
6617 | if (allow_power_down) { | |
6618 | val = I915_READ(LCPLL_CTL); | |
6619 | val |= LCPLL_POWER_DOWN_ALLOW; | |
6620 | I915_WRITE(LCPLL_CTL, val); | |
6621 | POSTING_READ(LCPLL_CTL); | |
6622 | } | |
6623 | } | |
6624 | ||
6625 | /* | |
6626 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
6627 | * source. | |
6628 | */ | |
6ff58d53 | 6629 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
6630 | { |
6631 | uint32_t val; | |
6632 | ||
6633 | val = I915_READ(LCPLL_CTL); | |
6634 | ||
6635 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
6636 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
6637 | return; | |
6638 | ||
215733fa PZ |
6639 | /* Make sure we're not on PC8 state before disabling PC8, otherwise |
6640 | * we'll hang the machine! */ | |
0d9d349d | 6641 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 6642 | |
be256dc7 PZ |
6643 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
6644 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
6645 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 6646 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
6647 | } |
6648 | ||
6649 | val = I915_READ(D_COMP); | |
6650 | val |= D_COMP_COMP_FORCE; | |
6651 | val &= ~D_COMP_COMP_DISABLE; | |
515b2392 PZ |
6652 | mutex_lock(&dev_priv->rps.hw_lock); |
6653 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val)) | |
6654 | DRM_ERROR("Failed to enable D_COMP\n"); | |
6655 | mutex_unlock(&dev_priv->rps.hw_lock); | |
35d8f2eb | 6656 | POSTING_READ(D_COMP); |
be256dc7 PZ |
6657 | |
6658 | val = I915_READ(LCPLL_CTL); | |
6659 | val &= ~LCPLL_PLL_DISABLE; | |
6660 | I915_WRITE(LCPLL_CTL, val); | |
6661 | ||
6662 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
6663 | DRM_ERROR("LCPLL not locked yet\n"); | |
6664 | ||
6665 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
6666 | val = I915_READ(LCPLL_CTL); | |
6667 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
6668 | I915_WRITE(LCPLL_CTL, val); | |
6669 | ||
6670 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
6671 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
6672 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
6673 | } | |
215733fa | 6674 | |
0d9d349d | 6675 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
be256dc7 PZ |
6676 | } |
6677 | ||
c67a470b PZ |
6678 | void hsw_enable_pc8_work(struct work_struct *__work) |
6679 | { | |
6680 | struct drm_i915_private *dev_priv = | |
6681 | container_of(to_delayed_work(__work), struct drm_i915_private, | |
6682 | pc8.enable_work); | |
6683 | struct drm_device *dev = dev_priv->dev; | |
6684 | uint32_t val; | |
6685 | ||
7125ecb8 PZ |
6686 | WARN_ON(!HAS_PC8(dev)); |
6687 | ||
c67a470b PZ |
6688 | if (dev_priv->pc8.enabled) |
6689 | return; | |
6690 | ||
6691 | DRM_DEBUG_KMS("Enabling package C8+\n"); | |
6692 | ||
6693 | dev_priv->pc8.enabled = true; | |
6694 | ||
6695 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
6696 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
6697 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
6698 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
6699 | } | |
6700 | ||
6701 | lpt_disable_clkout_dp(dev); | |
6702 | hsw_pc8_disable_interrupts(dev); | |
6703 | hsw_disable_lcpll(dev_priv, true, true); | |
8771a7f8 PZ |
6704 | |
6705 | intel_runtime_pm_put(dev_priv); | |
c67a470b PZ |
6706 | } |
6707 | ||
6708 | static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv) | |
6709 | { | |
6710 | WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock)); | |
6711 | WARN(dev_priv->pc8.disable_count < 1, | |
6712 | "pc8.disable_count: %d\n", dev_priv->pc8.disable_count); | |
6713 | ||
6714 | dev_priv->pc8.disable_count--; | |
6715 | if (dev_priv->pc8.disable_count != 0) | |
6716 | return; | |
6717 | ||
6718 | schedule_delayed_work(&dev_priv->pc8.enable_work, | |
d330a953 | 6719 | msecs_to_jiffies(i915.pc8_timeout)); |
c67a470b PZ |
6720 | } |
6721 | ||
6722 | static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv) | |
6723 | { | |
6724 | struct drm_device *dev = dev_priv->dev; | |
6725 | uint32_t val; | |
6726 | ||
6727 | WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock)); | |
6728 | WARN(dev_priv->pc8.disable_count < 0, | |
6729 | "pc8.disable_count: %d\n", dev_priv->pc8.disable_count); | |
6730 | ||
6731 | dev_priv->pc8.disable_count++; | |
6732 | if (dev_priv->pc8.disable_count != 1) | |
6733 | return; | |
6734 | ||
7125ecb8 PZ |
6735 | WARN_ON(!HAS_PC8(dev)); |
6736 | ||
c67a470b PZ |
6737 | cancel_delayed_work_sync(&dev_priv->pc8.enable_work); |
6738 | if (!dev_priv->pc8.enabled) | |
6739 | return; | |
6740 | ||
6741 | DRM_DEBUG_KMS("Disabling package C8+\n"); | |
6742 | ||
8771a7f8 PZ |
6743 | intel_runtime_pm_get(dev_priv); |
6744 | ||
c67a470b PZ |
6745 | hsw_restore_lcpll(dev_priv); |
6746 | hsw_pc8_restore_interrupts(dev); | |
6747 | lpt_init_pch_refclk(dev); | |
6748 | ||
6749 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
6750 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
6751 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
6752 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
6753 | } | |
6754 | ||
6755 | intel_prepare_ddi(dev); | |
6756 | i915_gem_init_swizzling(dev); | |
6757 | mutex_lock(&dev_priv->rps.hw_lock); | |
6758 | gen6_update_ring_freq(dev); | |
6759 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6760 | dev_priv->pc8.enabled = false; | |
6761 | } | |
6762 | ||
6763 | void hsw_enable_package_c8(struct drm_i915_private *dev_priv) | |
6764 | { | |
7c6c2652 CW |
6765 | if (!HAS_PC8(dev_priv->dev)) |
6766 | return; | |
6767 | ||
c67a470b PZ |
6768 | mutex_lock(&dev_priv->pc8.lock); |
6769 | __hsw_enable_package_c8(dev_priv); | |
6770 | mutex_unlock(&dev_priv->pc8.lock); | |
6771 | } | |
6772 | ||
6773 | void hsw_disable_package_c8(struct drm_i915_private *dev_priv) | |
6774 | { | |
7c6c2652 CW |
6775 | if (!HAS_PC8(dev_priv->dev)) |
6776 | return; | |
6777 | ||
c67a470b PZ |
6778 | mutex_lock(&dev_priv->pc8.lock); |
6779 | __hsw_disable_package_c8(dev_priv); | |
6780 | mutex_unlock(&dev_priv->pc8.lock); | |
6781 | } | |
6782 | ||
6783 | static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv) | |
6784 | { | |
6785 | struct drm_device *dev = dev_priv->dev; | |
6786 | struct intel_crtc *crtc; | |
6787 | uint32_t val; | |
6788 | ||
6789 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) | |
6790 | if (crtc->base.enabled) | |
6791 | return false; | |
6792 | ||
6793 | /* This case is still possible since we have the i915.disable_power_well | |
6794 | * parameter and also the KVMr or something else might be requesting the | |
6795 | * power well. */ | |
6796 | val = I915_READ(HSW_PWR_WELL_DRIVER); | |
6797 | if (val != 0) { | |
6798 | DRM_DEBUG_KMS("Not enabling PC8: power well on\n"); | |
6799 | return false; | |
6800 | } | |
6801 | ||
6802 | return true; | |
6803 | } | |
6804 | ||
6805 | /* Since we're called from modeset_global_resources there's no way to | |
6806 | * symmetrically increase and decrease the refcount, so we use | |
6807 | * dev_priv->pc8.requirements_met to track whether we already have the refcount | |
6808 | * or not. | |
6809 | */ | |
6810 | static void hsw_update_package_c8(struct drm_device *dev) | |
6811 | { | |
6812 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6813 | bool allow; | |
6814 | ||
7c6c2652 CW |
6815 | if (!HAS_PC8(dev_priv->dev)) |
6816 | return; | |
6817 | ||
d330a953 | 6818 | if (!i915.enable_pc8) |
c67a470b PZ |
6819 | return; |
6820 | ||
6821 | mutex_lock(&dev_priv->pc8.lock); | |
6822 | ||
6823 | allow = hsw_can_enable_package_c8(dev_priv); | |
6824 | ||
6825 | if (allow == dev_priv->pc8.requirements_met) | |
6826 | goto done; | |
6827 | ||
6828 | dev_priv->pc8.requirements_met = allow; | |
6829 | ||
6830 | if (allow) | |
6831 | __hsw_enable_package_c8(dev_priv); | |
6832 | else | |
6833 | __hsw_disable_package_c8(dev_priv); | |
6834 | ||
6835 | done: | |
6836 | mutex_unlock(&dev_priv->pc8.lock); | |
6837 | } | |
6838 | ||
6839 | static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv) | |
6840 | { | |
7c6c2652 CW |
6841 | if (!HAS_PC8(dev_priv->dev)) |
6842 | return; | |
6843 | ||
3458122e | 6844 | mutex_lock(&dev_priv->pc8.lock); |
c67a470b PZ |
6845 | if (!dev_priv->pc8.gpu_idle) { |
6846 | dev_priv->pc8.gpu_idle = true; | |
3458122e | 6847 | __hsw_enable_package_c8(dev_priv); |
c67a470b | 6848 | } |
3458122e | 6849 | mutex_unlock(&dev_priv->pc8.lock); |
c67a470b PZ |
6850 | } |
6851 | ||
6852 | static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv) | |
6853 | { | |
7c6c2652 CW |
6854 | if (!HAS_PC8(dev_priv->dev)) |
6855 | return; | |
6856 | ||
3458122e | 6857 | mutex_lock(&dev_priv->pc8.lock); |
c67a470b PZ |
6858 | if (dev_priv->pc8.gpu_idle) { |
6859 | dev_priv->pc8.gpu_idle = false; | |
3458122e | 6860 | __hsw_disable_package_c8(dev_priv); |
c67a470b | 6861 | } |
3458122e | 6862 | mutex_unlock(&dev_priv->pc8.lock); |
be256dc7 PZ |
6863 | } |
6864 | ||
6efdf354 ID |
6865 | #define for_each_power_domain(domain, mask) \ |
6866 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
6867 | if ((1 << (domain)) & (mask)) | |
6868 | ||
6869 | static unsigned long get_pipe_power_domains(struct drm_device *dev, | |
6870 | enum pipe pipe, bool pfit_enabled) | |
6871 | { | |
6872 | unsigned long mask; | |
6873 | enum transcoder transcoder; | |
6874 | ||
6875 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); | |
6876 | ||
6877 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); | |
6878 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
6879 | if (pfit_enabled) | |
6880 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); | |
6881 | ||
6882 | return mask; | |
6883 | } | |
6884 | ||
baa70707 ID |
6885 | void intel_display_set_init_power(struct drm_device *dev, bool enable) |
6886 | { | |
6887 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6888 | ||
6889 | if (dev_priv->power_domains.init_power_on == enable) | |
6890 | return; | |
6891 | ||
6892 | if (enable) | |
6893 | intel_display_power_get(dev, POWER_DOMAIN_INIT); | |
6894 | else | |
6895 | intel_display_power_put(dev, POWER_DOMAIN_INIT); | |
6896 | ||
6897 | dev_priv->power_domains.init_power_on = enable; | |
6898 | } | |
6899 | ||
4f074129 | 6900 | static void modeset_update_power_wells(struct drm_device *dev) |
d6dd9eb1 | 6901 | { |
6efdf354 | 6902 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; |
d6dd9eb1 | 6903 | struct intel_crtc *crtc; |
d6dd9eb1 | 6904 | |
6efdf354 ID |
6905 | /* |
6906 | * First get all needed power domains, then put all unneeded, to avoid | |
6907 | * any unnecessary toggling of the power wells. | |
6908 | */ | |
d6dd9eb1 | 6909 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
6efdf354 ID |
6910 | enum intel_display_power_domain domain; |
6911 | ||
e7a639c4 DV |
6912 | if (!crtc->base.enabled) |
6913 | continue; | |
d6dd9eb1 | 6914 | |
6efdf354 ID |
6915 | pipe_domains[crtc->pipe] = get_pipe_power_domains(dev, |
6916 | crtc->pipe, | |
6917 | crtc->config.pch_pfit.enabled); | |
6918 | ||
6919 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) | |
6920 | intel_display_power_get(dev, domain); | |
d6dd9eb1 DV |
6921 | } |
6922 | ||
6efdf354 ID |
6923 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
6924 | enum intel_display_power_domain domain; | |
6925 | ||
6926 | for_each_power_domain(domain, crtc->enabled_power_domains) | |
6927 | intel_display_power_put(dev, domain); | |
6928 | ||
6929 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; | |
6930 | } | |
baa70707 ID |
6931 | |
6932 | intel_display_set_init_power(dev, false); | |
4f074129 | 6933 | } |
c67a470b | 6934 | |
4f074129 ID |
6935 | static void haswell_modeset_global_resources(struct drm_device *dev) |
6936 | { | |
6937 | modeset_update_power_wells(dev); | |
c67a470b | 6938 | hsw_update_package_c8(dev); |
d6dd9eb1 DV |
6939 | } |
6940 | ||
09b4ddf9 | 6941 | static int haswell_crtc_mode_set(struct drm_crtc *crtc, |
09b4ddf9 PZ |
6942 | int x, int y, |
6943 | struct drm_framebuffer *fb) | |
6944 | { | |
6945 | struct drm_device *dev = crtc->dev; | |
6946 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6947 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
09b4ddf9 | 6948 | int plane = intel_crtc->plane; |
09b4ddf9 | 6949 | int ret; |
09b4ddf9 | 6950 | |
566b734a | 6951 | if (!intel_ddi_pll_select(intel_crtc)) |
6441ab5f | 6952 | return -EINVAL; |
566b734a | 6953 | intel_ddi_pll_enable(intel_crtc); |
6441ab5f | 6954 | |
03afc4a2 DV |
6955 | if (intel_crtc->config.has_dp_encoder) |
6956 | intel_dp_set_m_n(intel_crtc); | |
09b4ddf9 PZ |
6957 | |
6958 | intel_crtc->lowfreq_avail = false; | |
09b4ddf9 | 6959 | |
8a654f3b | 6960 | intel_set_pipe_timings(intel_crtc); |
09b4ddf9 | 6961 | |
ca3a0ff8 | 6962 | if (intel_crtc->config.has_pch_encoder) { |
ca3a0ff8 DV |
6963 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6964 | &intel_crtc->config.fdi_m_n); | |
6965 | } | |
09b4ddf9 | 6966 | |
6ff93609 | 6967 | haswell_set_pipeconf(crtc); |
09b4ddf9 | 6968 | |
50f3b016 | 6969 | intel_set_pipe_csc(crtc); |
86d3efce | 6970 | |
09b4ddf9 | 6971 | /* Set up the display plane register */ |
86d3efce | 6972 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE); |
09b4ddf9 PZ |
6973 | POSTING_READ(DSPCNTR(plane)); |
6974 | ||
6975 | ret = intel_pipe_set_base(crtc, x, y, fb); | |
6976 | ||
1f803ee5 | 6977 | return ret; |
79e53945 JB |
6978 | } |
6979 | ||
0e8ffe1b DV |
6980 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
6981 | struct intel_crtc_config *pipe_config) | |
6982 | { | |
6983 | struct drm_device *dev = crtc->base.dev; | |
6984 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 6985 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
6986 | uint32_t tmp; |
6987 | ||
e143a21c | 6988 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
6989 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
6990 | ||
eccb140b DV |
6991 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
6992 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
6993 | enum pipe trans_edp_pipe; | |
6994 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
6995 | default: | |
6996 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
6997 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
6998 | case TRANS_DDI_EDP_INPUT_A_ON: | |
6999 | trans_edp_pipe = PIPE_A; | |
7000 | break; | |
7001 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
7002 | trans_edp_pipe = PIPE_B; | |
7003 | break; | |
7004 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
7005 | trans_edp_pipe = PIPE_C; | |
7006 | break; | |
7007 | } | |
7008 | ||
7009 | if (trans_edp_pipe == crtc->pipe) | |
7010 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
7011 | } | |
7012 | ||
b97186f0 | 7013 | if (!intel_display_power_enabled(dev, |
eccb140b | 7014 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
7015 | return false; |
7016 | ||
eccb140b | 7017 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
7018 | if (!(tmp & PIPECONF_ENABLE)) |
7019 | return false; | |
7020 | ||
88adfff1 | 7021 | /* |
f196e6be | 7022 | * Haswell has only FDI/PCH transcoder A. It is which is connected to |
88adfff1 DV |
7023 | * DDI E. So just check whether this pipe is wired to DDI E and whether |
7024 | * the PCH transcoder is on. | |
7025 | */ | |
eccb140b | 7026 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); |
88adfff1 | 7027 | if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) && |
ab9412ba | 7028 | I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
88adfff1 DV |
7029 | pipe_config->has_pch_encoder = true; |
7030 | ||
627eb5a3 DV |
7031 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); |
7032 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
7033 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
7034 | |
7035 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
627eb5a3 DV |
7036 | } |
7037 | ||
1bd1bd80 DV |
7038 | intel_get_pipe_timings(crtc, pipe_config); |
7039 | ||
2fa2fe9a DV |
7040 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
7041 | if (intel_display_power_enabled(dev, pfit_domain)) | |
7042 | ironlake_get_pfit_config(crtc, pipe_config); | |
88adfff1 | 7043 | |
e59150dc JB |
7044 | if (IS_HASWELL(dev)) |
7045 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
7046 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 7047 | |
6c49f241 DV |
7048 | pipe_config->pixel_multiplier = 1; |
7049 | ||
0e8ffe1b DV |
7050 | return true; |
7051 | } | |
7052 | ||
f564048e | 7053 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
f564048e | 7054 | int x, int y, |
94352cf9 | 7055 | struct drm_framebuffer *fb) |
f564048e EA |
7056 | { |
7057 | struct drm_device *dev = crtc->dev; | |
7058 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9256aa19 | 7059 | struct intel_encoder *encoder; |
0b701d27 | 7060 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
b8cecdf5 | 7061 | struct drm_display_mode *mode = &intel_crtc->config.requested_mode; |
0b701d27 | 7062 | int pipe = intel_crtc->pipe; |
f564048e EA |
7063 | int ret; |
7064 | ||
0b701d27 | 7065 | drm_vblank_pre_modeset(dev, pipe); |
7662c8bd | 7066 | |
b8cecdf5 DV |
7067 | ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb); |
7068 | ||
79e53945 | 7069 | drm_vblank_post_modeset(dev, pipe); |
5c3b82e2 | 7070 | |
9256aa19 DV |
7071 | if (ret != 0) |
7072 | return ret; | |
7073 | ||
7074 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
7075 | DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n", | |
7076 | encoder->base.base.id, | |
7077 | drm_get_encoder_name(&encoder->base), | |
7078 | mode->base.id, mode->name); | |
36f2d1f1 | 7079 | encoder->mode_set(encoder); |
9256aa19 DV |
7080 | } |
7081 | ||
7082 | return 0; | |
79e53945 JB |
7083 | } |
7084 | ||
1a91510d JN |
7085 | static struct { |
7086 | int clock; | |
7087 | u32 config; | |
7088 | } hdmi_audio_clock[] = { | |
7089 | { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, | |
7090 | { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ | |
7091 | { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, | |
7092 | { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, | |
7093 | { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, | |
7094 | { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, | |
7095 | { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, | |
7096 | { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, | |
7097 | { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, | |
7098 | { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, | |
7099 | }; | |
7100 | ||
7101 | /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ | |
7102 | static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode) | |
7103 | { | |
7104 | int i; | |
7105 | ||
7106 | for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { | |
7107 | if (mode->clock == hdmi_audio_clock[i].clock) | |
7108 | break; | |
7109 | } | |
7110 | ||
7111 | if (i == ARRAY_SIZE(hdmi_audio_clock)) { | |
7112 | DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock); | |
7113 | i = 1; | |
7114 | } | |
7115 | ||
7116 | DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", | |
7117 | hdmi_audio_clock[i].clock, | |
7118 | hdmi_audio_clock[i].config); | |
7119 | ||
7120 | return hdmi_audio_clock[i].config; | |
7121 | } | |
7122 | ||
3a9627f4 WF |
7123 | static bool intel_eld_uptodate(struct drm_connector *connector, |
7124 | int reg_eldv, uint32_t bits_eldv, | |
7125 | int reg_elda, uint32_t bits_elda, | |
7126 | int reg_edid) | |
7127 | { | |
7128 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7129 | uint8_t *eld = connector->eld; | |
7130 | uint32_t i; | |
7131 | ||
7132 | i = I915_READ(reg_eldv); | |
7133 | i &= bits_eldv; | |
7134 | ||
7135 | if (!eld[0]) | |
7136 | return !i; | |
7137 | ||
7138 | if (!i) | |
7139 | return false; | |
7140 | ||
7141 | i = I915_READ(reg_elda); | |
7142 | i &= ~bits_elda; | |
7143 | I915_WRITE(reg_elda, i); | |
7144 | ||
7145 | for (i = 0; i < eld[2]; i++) | |
7146 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) | |
7147 | return false; | |
7148 | ||
7149 | return true; | |
7150 | } | |
7151 | ||
e0dac65e | 7152 | static void g4x_write_eld(struct drm_connector *connector, |
34427052 JN |
7153 | struct drm_crtc *crtc, |
7154 | struct drm_display_mode *mode) | |
e0dac65e WF |
7155 | { |
7156 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7157 | uint8_t *eld = connector->eld; | |
7158 | uint32_t eldv; | |
7159 | uint32_t len; | |
7160 | uint32_t i; | |
7161 | ||
7162 | i = I915_READ(G4X_AUD_VID_DID); | |
7163 | ||
7164 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) | |
7165 | eldv = G4X_ELDV_DEVCL_DEVBLC; | |
7166 | else | |
7167 | eldv = G4X_ELDV_DEVCTG; | |
7168 | ||
3a9627f4 WF |
7169 | if (intel_eld_uptodate(connector, |
7170 | G4X_AUD_CNTL_ST, eldv, | |
7171 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, | |
7172 | G4X_HDMIW_HDMIEDID)) | |
7173 | return; | |
7174 | ||
e0dac65e WF |
7175 | i = I915_READ(G4X_AUD_CNTL_ST); |
7176 | i &= ~(eldv | G4X_ELD_ADDR); | |
7177 | len = (i >> 9) & 0x1f; /* ELD buffer size */ | |
7178 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
7179 | ||
7180 | if (!eld[0]) | |
7181 | return; | |
7182 | ||
7183 | len = min_t(uint8_t, eld[2], len); | |
7184 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7185 | for (i = 0; i < len; i++) | |
7186 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); | |
7187 | ||
7188 | i = I915_READ(G4X_AUD_CNTL_ST); | |
7189 | i |= eldv; | |
7190 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
7191 | } | |
7192 | ||
83358c85 | 7193 | static void haswell_write_eld(struct drm_connector *connector, |
34427052 JN |
7194 | struct drm_crtc *crtc, |
7195 | struct drm_display_mode *mode) | |
83358c85 WX |
7196 | { |
7197 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7198 | uint8_t *eld = connector->eld; | |
7199 | struct drm_device *dev = crtc->dev; | |
7b9f35a6 | 7200 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
83358c85 WX |
7201 | uint32_t eldv; |
7202 | uint32_t i; | |
7203 | int len; | |
7204 | int pipe = to_intel_crtc(crtc)->pipe; | |
7205 | int tmp; | |
7206 | ||
7207 | int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); | |
7208 | int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); | |
7209 | int aud_config = HSW_AUD_CFG(pipe); | |
7210 | int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD; | |
7211 | ||
7212 | ||
7213 | DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n"); | |
7214 | ||
7215 | /* Audio output enable */ | |
7216 | DRM_DEBUG_DRIVER("HDMI audio: enable codec\n"); | |
7217 | tmp = I915_READ(aud_cntrl_st2); | |
7218 | tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); | |
7219 | I915_WRITE(aud_cntrl_st2, tmp); | |
7220 | ||
7221 | /* Wait for 1 vertical blank */ | |
7222 | intel_wait_for_vblank(dev, pipe); | |
7223 | ||
7224 | /* Set ELD valid state */ | |
7225 | tmp = I915_READ(aud_cntrl_st2); | |
7e7cb34f | 7226 | DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp); |
83358c85 WX |
7227 | tmp |= (AUDIO_ELD_VALID_A << (pipe * 4)); |
7228 | I915_WRITE(aud_cntrl_st2, tmp); | |
7229 | tmp = I915_READ(aud_cntrl_st2); | |
7e7cb34f | 7230 | DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp); |
83358c85 WX |
7231 | |
7232 | /* Enable HDMI mode */ | |
7233 | tmp = I915_READ(aud_config); | |
7e7cb34f | 7234 | DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp); |
83358c85 WX |
7235 | /* clear N_programing_enable and N_value_index */ |
7236 | tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE); | |
7237 | I915_WRITE(aud_config, tmp); | |
7238 | ||
7239 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); | |
7240 | ||
7241 | eldv = AUDIO_ELD_VALID_A << (pipe * 4); | |
7b9f35a6 | 7242 | intel_crtc->eld_vld = true; |
83358c85 WX |
7243 | |
7244 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { | |
7245 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
7246 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
7247 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ | |
1a91510d JN |
7248 | } else { |
7249 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); | |
7250 | } | |
83358c85 WX |
7251 | |
7252 | if (intel_eld_uptodate(connector, | |
7253 | aud_cntrl_st2, eldv, | |
7254 | aud_cntl_st, IBX_ELD_ADDRESS, | |
7255 | hdmiw_hdmiedid)) | |
7256 | return; | |
7257 | ||
7258 | i = I915_READ(aud_cntrl_st2); | |
7259 | i &= ~eldv; | |
7260 | I915_WRITE(aud_cntrl_st2, i); | |
7261 | ||
7262 | if (!eld[0]) | |
7263 | return; | |
7264 | ||
7265 | i = I915_READ(aud_cntl_st); | |
7266 | i &= ~IBX_ELD_ADDRESS; | |
7267 | I915_WRITE(aud_cntl_st, i); | |
7268 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ | |
7269 | DRM_DEBUG_DRIVER("port num:%d\n", i); | |
7270 | ||
7271 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
7272 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7273 | for (i = 0; i < len; i++) | |
7274 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
7275 | ||
7276 | i = I915_READ(aud_cntrl_st2); | |
7277 | i |= eldv; | |
7278 | I915_WRITE(aud_cntrl_st2, i); | |
7279 | ||
7280 | } | |
7281 | ||
e0dac65e | 7282 | static void ironlake_write_eld(struct drm_connector *connector, |
34427052 JN |
7283 | struct drm_crtc *crtc, |
7284 | struct drm_display_mode *mode) | |
e0dac65e WF |
7285 | { |
7286 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7287 | uint8_t *eld = connector->eld; | |
7288 | uint32_t eldv; | |
7289 | uint32_t i; | |
7290 | int len; | |
7291 | int hdmiw_hdmiedid; | |
b6daa025 | 7292 | int aud_config; |
e0dac65e WF |
7293 | int aud_cntl_st; |
7294 | int aud_cntrl_st2; | |
9b138a83 | 7295 | int pipe = to_intel_crtc(crtc)->pipe; |
e0dac65e | 7296 | |
b3f33cbf | 7297 | if (HAS_PCH_IBX(connector->dev)) { |
9b138a83 WX |
7298 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
7299 | aud_config = IBX_AUD_CFG(pipe); | |
7300 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); | |
1202b4c6 | 7301 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
9ca2fe73 ML |
7302 | } else if (IS_VALLEYVIEW(connector->dev)) { |
7303 | hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); | |
7304 | aud_config = VLV_AUD_CFG(pipe); | |
7305 | aud_cntl_st = VLV_AUD_CNTL_ST(pipe); | |
7306 | aud_cntrl_st2 = VLV_AUD_CNTL_ST2; | |
e0dac65e | 7307 | } else { |
9b138a83 WX |
7308 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); |
7309 | aud_config = CPT_AUD_CFG(pipe); | |
7310 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); | |
1202b4c6 | 7311 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
e0dac65e WF |
7312 | } |
7313 | ||
9b138a83 | 7314 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
e0dac65e | 7315 | |
9ca2fe73 ML |
7316 | if (IS_VALLEYVIEW(connector->dev)) { |
7317 | struct intel_encoder *intel_encoder; | |
7318 | struct intel_digital_port *intel_dig_port; | |
7319 | ||
7320 | intel_encoder = intel_attached_encoder(connector); | |
7321 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
7322 | i = intel_dig_port->port; | |
7323 | } else { | |
7324 | i = I915_READ(aud_cntl_st); | |
7325 | i = (i >> 29) & DIP_PORT_SEL_MASK; | |
7326 | /* DIP_Port_Select, 0x1 = PortB */ | |
7327 | } | |
7328 | ||
e0dac65e WF |
7329 | if (!i) { |
7330 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); | |
7331 | /* operate blindly on all ports */ | |
1202b4c6 WF |
7332 | eldv = IBX_ELD_VALIDB; |
7333 | eldv |= IBX_ELD_VALIDB << 4; | |
7334 | eldv |= IBX_ELD_VALIDB << 8; | |
e0dac65e | 7335 | } else { |
2582a850 | 7336 | DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i)); |
1202b4c6 | 7337 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
e0dac65e WF |
7338 | } |
7339 | ||
3a9627f4 WF |
7340 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
7341 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
7342 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
b6daa025 | 7343 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
1a91510d JN |
7344 | } else { |
7345 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); | |
7346 | } | |
e0dac65e | 7347 | |
3a9627f4 WF |
7348 | if (intel_eld_uptodate(connector, |
7349 | aud_cntrl_st2, eldv, | |
7350 | aud_cntl_st, IBX_ELD_ADDRESS, | |
7351 | hdmiw_hdmiedid)) | |
7352 | return; | |
7353 | ||
e0dac65e WF |
7354 | i = I915_READ(aud_cntrl_st2); |
7355 | i &= ~eldv; | |
7356 | I915_WRITE(aud_cntrl_st2, i); | |
7357 | ||
7358 | if (!eld[0]) | |
7359 | return; | |
7360 | ||
e0dac65e | 7361 | i = I915_READ(aud_cntl_st); |
1202b4c6 | 7362 | i &= ~IBX_ELD_ADDRESS; |
e0dac65e WF |
7363 | I915_WRITE(aud_cntl_st, i); |
7364 | ||
7365 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
7366 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7367 | for (i = 0; i < len; i++) | |
7368 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
7369 | ||
7370 | i = I915_READ(aud_cntrl_st2); | |
7371 | i |= eldv; | |
7372 | I915_WRITE(aud_cntrl_st2, i); | |
7373 | } | |
7374 | ||
7375 | void intel_write_eld(struct drm_encoder *encoder, | |
7376 | struct drm_display_mode *mode) | |
7377 | { | |
7378 | struct drm_crtc *crtc = encoder->crtc; | |
7379 | struct drm_connector *connector; | |
7380 | struct drm_device *dev = encoder->dev; | |
7381 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7382 | ||
7383 | connector = drm_select_eld(encoder, mode); | |
7384 | if (!connector) | |
7385 | return; | |
7386 | ||
7387 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", | |
7388 | connector->base.id, | |
7389 | drm_get_connector_name(connector), | |
7390 | connector->encoder->base.id, | |
7391 | drm_get_encoder_name(connector->encoder)); | |
7392 | ||
7393 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; | |
7394 | ||
7395 | if (dev_priv->display.write_eld) | |
34427052 | 7396 | dev_priv->display.write_eld(connector, crtc, mode); |
e0dac65e WF |
7397 | } |
7398 | ||
560b85bb CW |
7399 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
7400 | { | |
7401 | struct drm_device *dev = crtc->dev; | |
7402 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7403 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7404 | bool visible = base != 0; | |
7405 | u32 cntl; | |
7406 | ||
7407 | if (intel_crtc->cursor_visible == visible) | |
7408 | return; | |
7409 | ||
9db4a9c7 | 7410 | cntl = I915_READ(_CURACNTR); |
560b85bb CW |
7411 | if (visible) { |
7412 | /* On these chipsets we can only modify the base whilst | |
7413 | * the cursor is disabled. | |
7414 | */ | |
9db4a9c7 | 7415 | I915_WRITE(_CURABASE, base); |
560b85bb CW |
7416 | |
7417 | cntl &= ~(CURSOR_FORMAT_MASK); | |
7418 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ | |
7419 | cntl |= CURSOR_ENABLE | | |
7420 | CURSOR_GAMMA_ENABLE | | |
7421 | CURSOR_FORMAT_ARGB; | |
7422 | } else | |
7423 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); | |
9db4a9c7 | 7424 | I915_WRITE(_CURACNTR, cntl); |
560b85bb CW |
7425 | |
7426 | intel_crtc->cursor_visible = visible; | |
7427 | } | |
7428 | ||
7429 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) | |
7430 | { | |
7431 | struct drm_device *dev = crtc->dev; | |
7432 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7433 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7434 | int pipe = intel_crtc->pipe; | |
7435 | bool visible = base != 0; | |
7436 | ||
7437 | if (intel_crtc->cursor_visible != visible) { | |
548f245b | 7438 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
560b85bb CW |
7439 | if (base) { |
7440 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); | |
7441 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
7442 | cntl |= pipe << 28; /* Connect to correct pipe */ | |
7443 | } else { | |
7444 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
7445 | cntl |= CURSOR_MODE_DISABLE; | |
7446 | } | |
9db4a9c7 | 7447 | I915_WRITE(CURCNTR(pipe), cntl); |
560b85bb CW |
7448 | |
7449 | intel_crtc->cursor_visible = visible; | |
7450 | } | |
7451 | /* and commit changes on next vblank */ | |
b2ea8ef5 | 7452 | POSTING_READ(CURCNTR(pipe)); |
9db4a9c7 | 7453 | I915_WRITE(CURBASE(pipe), base); |
b2ea8ef5 | 7454 | POSTING_READ(CURBASE(pipe)); |
560b85bb CW |
7455 | } |
7456 | ||
65a21cd6 JB |
7457 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
7458 | { | |
7459 | struct drm_device *dev = crtc->dev; | |
7460 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7461 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7462 | int pipe = intel_crtc->pipe; | |
7463 | bool visible = base != 0; | |
7464 | ||
7465 | if (intel_crtc->cursor_visible != visible) { | |
7466 | uint32_t cntl = I915_READ(CURCNTR_IVB(pipe)); | |
7467 | if (base) { | |
7468 | cntl &= ~CURSOR_MODE; | |
7469 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
7470 | } else { | |
7471 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
7472 | cntl |= CURSOR_MODE_DISABLE; | |
7473 | } | |
6bbfa1c5 | 7474 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
86d3efce | 7475 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
1f5d76db PZ |
7476 | cntl &= ~CURSOR_TRICKLE_FEED_DISABLE; |
7477 | } | |
65a21cd6 JB |
7478 | I915_WRITE(CURCNTR_IVB(pipe), cntl); |
7479 | ||
7480 | intel_crtc->cursor_visible = visible; | |
7481 | } | |
7482 | /* and commit changes on next vblank */ | |
b2ea8ef5 | 7483 | POSTING_READ(CURCNTR_IVB(pipe)); |
65a21cd6 | 7484 | I915_WRITE(CURBASE_IVB(pipe), base); |
b2ea8ef5 | 7485 | POSTING_READ(CURBASE_IVB(pipe)); |
65a21cd6 JB |
7486 | } |
7487 | ||
cda4b7d3 | 7488 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
7489 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
7490 | bool on) | |
cda4b7d3 CW |
7491 | { |
7492 | struct drm_device *dev = crtc->dev; | |
7493 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7494 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7495 | int pipe = intel_crtc->pipe; | |
7496 | int x = intel_crtc->cursor_x; | |
7497 | int y = intel_crtc->cursor_y; | |
d6e4db15 | 7498 | u32 base = 0, pos = 0; |
cda4b7d3 CW |
7499 | bool visible; |
7500 | ||
d6e4db15 | 7501 | if (on) |
cda4b7d3 | 7502 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 7503 | |
d6e4db15 VS |
7504 | if (x >= intel_crtc->config.pipe_src_w) |
7505 | base = 0; | |
7506 | ||
7507 | if (y >= intel_crtc->config.pipe_src_h) | |
cda4b7d3 CW |
7508 | base = 0; |
7509 | ||
7510 | if (x < 0) { | |
efc9064e | 7511 | if (x + intel_crtc->cursor_width <= 0) |
cda4b7d3 CW |
7512 | base = 0; |
7513 | ||
7514 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
7515 | x = -x; | |
7516 | } | |
7517 | pos |= x << CURSOR_X_SHIFT; | |
7518 | ||
7519 | if (y < 0) { | |
efc9064e | 7520 | if (y + intel_crtc->cursor_height <= 0) |
cda4b7d3 CW |
7521 | base = 0; |
7522 | ||
7523 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
7524 | y = -y; | |
7525 | } | |
7526 | pos |= y << CURSOR_Y_SHIFT; | |
7527 | ||
7528 | visible = base != 0; | |
560b85bb | 7529 | if (!visible && !intel_crtc->cursor_visible) |
cda4b7d3 CW |
7530 | return; |
7531 | ||
b3dc685e | 7532 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
65a21cd6 JB |
7533 | I915_WRITE(CURPOS_IVB(pipe), pos); |
7534 | ivb_update_cursor(crtc, base); | |
7535 | } else { | |
7536 | I915_WRITE(CURPOS(pipe), pos); | |
7537 | if (IS_845G(dev) || IS_I865G(dev)) | |
7538 | i845_update_cursor(crtc, base); | |
7539 | else | |
7540 | i9xx_update_cursor(crtc, base); | |
7541 | } | |
cda4b7d3 CW |
7542 | } |
7543 | ||
79e53945 | 7544 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
05394f39 | 7545 | struct drm_file *file, |
79e53945 JB |
7546 | uint32_t handle, |
7547 | uint32_t width, uint32_t height) | |
7548 | { | |
7549 | struct drm_device *dev = crtc->dev; | |
7550 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7551 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 7552 | struct drm_i915_gem_object *obj; |
cda4b7d3 | 7553 | uint32_t addr; |
3f8bc370 | 7554 | int ret; |
79e53945 | 7555 | |
79e53945 JB |
7556 | /* if we want to turn off the cursor ignore width and height */ |
7557 | if (!handle) { | |
28c97730 | 7558 | DRM_DEBUG_KMS("cursor off\n"); |
3f8bc370 | 7559 | addr = 0; |
05394f39 | 7560 | obj = NULL; |
5004417d | 7561 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 7562 | goto finish; |
79e53945 JB |
7563 | } |
7564 | ||
7565 | /* Currently we only support 64x64 cursors */ | |
7566 | if (width != 64 || height != 64) { | |
7567 | DRM_ERROR("we currently only support 64x64 cursors\n"); | |
7568 | return -EINVAL; | |
7569 | } | |
7570 | ||
05394f39 | 7571 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 7572 | if (&obj->base == NULL) |
79e53945 JB |
7573 | return -ENOENT; |
7574 | ||
05394f39 | 7575 | if (obj->base.size < width * height * 4) { |
79e53945 | 7576 | DRM_ERROR("buffer is to small\n"); |
34b8686e DA |
7577 | ret = -ENOMEM; |
7578 | goto fail; | |
79e53945 JB |
7579 | } |
7580 | ||
71acb5eb | 7581 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 7582 | mutex_lock(&dev->struct_mutex); |
3d13ef2e | 7583 | if (!INTEL_INFO(dev)->cursor_needs_physical) { |
693db184 CW |
7584 | unsigned alignment; |
7585 | ||
d9e86c0e CW |
7586 | if (obj->tiling_mode) { |
7587 | DRM_ERROR("cursor cannot be tiled\n"); | |
7588 | ret = -EINVAL; | |
7589 | goto fail_locked; | |
7590 | } | |
7591 | ||
693db184 CW |
7592 | /* Note that the w/a also requires 2 PTE of padding following |
7593 | * the bo. We currently fill all unused PTE with the shadow | |
7594 | * page and so we should always have valid PTE following the | |
7595 | * cursor preventing the VT-d warning. | |
7596 | */ | |
7597 | alignment = 0; | |
7598 | if (need_vtd_wa(dev)) | |
7599 | alignment = 64*1024; | |
7600 | ||
7601 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); | |
e7b526bb CW |
7602 | if (ret) { |
7603 | DRM_ERROR("failed to move cursor bo into the GTT\n"); | |
2da3b9b9 | 7604 | goto fail_locked; |
e7b526bb CW |
7605 | } |
7606 | ||
d9e86c0e CW |
7607 | ret = i915_gem_object_put_fence(obj); |
7608 | if (ret) { | |
2da3b9b9 | 7609 | DRM_ERROR("failed to release fence for cursor"); |
d9e86c0e CW |
7610 | goto fail_unpin; |
7611 | } | |
7612 | ||
f343c5f6 | 7613 | addr = i915_gem_obj_ggtt_offset(obj); |
71acb5eb | 7614 | } else { |
6eeefaf3 | 7615 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
05394f39 | 7616 | ret = i915_gem_attach_phys_object(dev, obj, |
6eeefaf3 CW |
7617 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
7618 | align); | |
71acb5eb DA |
7619 | if (ret) { |
7620 | DRM_ERROR("failed to attach phys object\n"); | |
7f9872e0 | 7621 | goto fail_locked; |
71acb5eb | 7622 | } |
05394f39 | 7623 | addr = obj->phys_obj->handle->busaddr; |
3f8bc370 KH |
7624 | } |
7625 | ||
a6c45cf0 | 7626 | if (IS_GEN2(dev)) |
14b60391 JB |
7627 | I915_WRITE(CURSIZE, (height << 12) | width); |
7628 | ||
3f8bc370 | 7629 | finish: |
3f8bc370 | 7630 | if (intel_crtc->cursor_bo) { |
3d13ef2e | 7631 | if (INTEL_INFO(dev)->cursor_needs_physical) { |
05394f39 | 7632 | if (intel_crtc->cursor_bo != obj) |
71acb5eb DA |
7633 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
7634 | } else | |
cc98b413 | 7635 | i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo); |
05394f39 | 7636 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
3f8bc370 | 7637 | } |
80824003 | 7638 | |
7f9872e0 | 7639 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 KH |
7640 | |
7641 | intel_crtc->cursor_addr = addr; | |
05394f39 | 7642 | intel_crtc->cursor_bo = obj; |
cda4b7d3 CW |
7643 | intel_crtc->cursor_width = width; |
7644 | intel_crtc->cursor_height = height; | |
7645 | ||
f2f5f771 VS |
7646 | if (intel_crtc->active) |
7647 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); | |
3f8bc370 | 7648 | |
79e53945 | 7649 | return 0; |
e7b526bb | 7650 | fail_unpin: |
cc98b413 | 7651 | i915_gem_object_unpin_from_display_plane(obj); |
7f9872e0 | 7652 | fail_locked: |
34b8686e | 7653 | mutex_unlock(&dev->struct_mutex); |
bc9025bd | 7654 | fail: |
05394f39 | 7655 | drm_gem_object_unreference_unlocked(&obj->base); |
34b8686e | 7656 | return ret; |
79e53945 JB |
7657 | } |
7658 | ||
7659 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
7660 | { | |
79e53945 | 7661 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 7662 | |
92e76c8c VS |
7663 | intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX); |
7664 | intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX); | |
652c393a | 7665 | |
f2f5f771 VS |
7666 | if (intel_crtc->active) |
7667 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); | |
79e53945 JB |
7668 | |
7669 | return 0; | |
b8c00ac5 DA |
7670 | } |
7671 | ||
79e53945 | 7672 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 7673 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 7674 | { |
7203425a | 7675 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 7676 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 7677 | |
7203425a | 7678 | for (i = start; i < end; i++) { |
79e53945 JB |
7679 | intel_crtc->lut_r[i] = red[i] >> 8; |
7680 | intel_crtc->lut_g[i] = green[i] >> 8; | |
7681 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
7682 | } | |
7683 | ||
7684 | intel_crtc_load_lut(crtc); | |
7685 | } | |
7686 | ||
79e53945 JB |
7687 | /* VESA 640x480x72Hz mode to set on the pipe */ |
7688 | static struct drm_display_mode load_detect_mode = { | |
7689 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
7690 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
7691 | }; | |
7692 | ||
d2dff872 CW |
7693 | static struct drm_framebuffer * |
7694 | intel_framebuffer_create(struct drm_device *dev, | |
308e5bcb | 7695 | struct drm_mode_fb_cmd2 *mode_cmd, |
d2dff872 CW |
7696 | struct drm_i915_gem_object *obj) |
7697 | { | |
7698 | struct intel_framebuffer *intel_fb; | |
7699 | int ret; | |
7700 | ||
7701 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
7702 | if (!intel_fb) { | |
7703 | drm_gem_object_unreference_unlocked(&obj->base); | |
7704 | return ERR_PTR(-ENOMEM); | |
7705 | } | |
7706 | ||
dd4916c5 DV |
7707 | ret = i915_mutex_lock_interruptible(dev); |
7708 | if (ret) | |
7709 | goto err; | |
7710 | ||
d2dff872 | 7711 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); |
dd4916c5 DV |
7712 | mutex_unlock(&dev->struct_mutex); |
7713 | if (ret) | |
7714 | goto err; | |
d2dff872 CW |
7715 | |
7716 | return &intel_fb->base; | |
dd4916c5 DV |
7717 | err: |
7718 | drm_gem_object_unreference_unlocked(&obj->base); | |
7719 | kfree(intel_fb); | |
7720 | ||
7721 | return ERR_PTR(ret); | |
d2dff872 CW |
7722 | } |
7723 | ||
7724 | static u32 | |
7725 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
7726 | { | |
7727 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
7728 | return ALIGN(pitch, 64); | |
7729 | } | |
7730 | ||
7731 | static u32 | |
7732 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
7733 | { | |
7734 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
7735 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); | |
7736 | } | |
7737 | ||
7738 | static struct drm_framebuffer * | |
7739 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
7740 | struct drm_display_mode *mode, | |
7741 | int depth, int bpp) | |
7742 | { | |
7743 | struct drm_i915_gem_object *obj; | |
0fed39bd | 7744 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
7745 | |
7746 | obj = i915_gem_alloc_object(dev, | |
7747 | intel_framebuffer_size_for_mode(mode, bpp)); | |
7748 | if (obj == NULL) | |
7749 | return ERR_PTR(-ENOMEM); | |
7750 | ||
7751 | mode_cmd.width = mode->hdisplay; | |
7752 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
7753 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
7754 | bpp); | |
5ca0c34a | 7755 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
7756 | |
7757 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
7758 | } | |
7759 | ||
7760 | static struct drm_framebuffer * | |
7761 | mode_fits_in_fbdev(struct drm_device *dev, | |
7762 | struct drm_display_mode *mode) | |
7763 | { | |
4520f53a | 7764 | #ifdef CONFIG_DRM_I915_FBDEV |
d2dff872 CW |
7765 | struct drm_i915_private *dev_priv = dev->dev_private; |
7766 | struct drm_i915_gem_object *obj; | |
7767 | struct drm_framebuffer *fb; | |
7768 | ||
7769 | if (dev_priv->fbdev == NULL) | |
7770 | return NULL; | |
7771 | ||
8bcd4553 | 7772 | obj = dev_priv->fbdev->fb->obj; |
d2dff872 CW |
7773 | if (obj == NULL) |
7774 | return NULL; | |
7775 | ||
8bcd4553 | 7776 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
7777 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
7778 | fb->bits_per_pixel)) | |
d2dff872 CW |
7779 | return NULL; |
7780 | ||
01f2c773 | 7781 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
7782 | return NULL; |
7783 | ||
7784 | return fb; | |
4520f53a DV |
7785 | #else |
7786 | return NULL; | |
7787 | #endif | |
d2dff872 CW |
7788 | } |
7789 | ||
d2434ab7 | 7790 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 7791 | struct drm_display_mode *mode, |
8261b191 | 7792 | struct intel_load_detect_pipe *old) |
79e53945 JB |
7793 | { |
7794 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
7795 | struct intel_encoder *intel_encoder = |
7796 | intel_attached_encoder(connector); | |
79e53945 | 7797 | struct drm_crtc *possible_crtc; |
4ef69c7a | 7798 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
7799 | struct drm_crtc *crtc = NULL; |
7800 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 7801 | struct drm_framebuffer *fb; |
79e53945 JB |
7802 | int i = -1; |
7803 | ||
d2dff872 CW |
7804 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
7805 | connector->base.id, drm_get_connector_name(connector), | |
7806 | encoder->base.id, drm_get_encoder_name(encoder)); | |
7807 | ||
79e53945 JB |
7808 | /* |
7809 | * Algorithm gets a little messy: | |
7a5e4805 | 7810 | * |
79e53945 JB |
7811 | * - if the connector already has an assigned crtc, use it (but make |
7812 | * sure it's on first) | |
7a5e4805 | 7813 | * |
79e53945 JB |
7814 | * - try to find the first unused crtc that can drive this connector, |
7815 | * and use that if we find one | |
79e53945 JB |
7816 | */ |
7817 | ||
7818 | /* See if we already have a CRTC for this connector */ | |
7819 | if (encoder->crtc) { | |
7820 | crtc = encoder->crtc; | |
8261b191 | 7821 | |
7b24056b DV |
7822 | mutex_lock(&crtc->mutex); |
7823 | ||
24218aac | 7824 | old->dpms_mode = connector->dpms; |
8261b191 CW |
7825 | old->load_detect_temp = false; |
7826 | ||
7827 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
7828 | if (connector->dpms != DRM_MODE_DPMS_ON) |
7829 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 7830 | |
7173188d | 7831 | return true; |
79e53945 JB |
7832 | } |
7833 | ||
7834 | /* Find an unused one (if possible) */ | |
7835 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { | |
7836 | i++; | |
7837 | if (!(encoder->possible_crtcs & (1 << i))) | |
7838 | continue; | |
7839 | if (!possible_crtc->enabled) { | |
7840 | crtc = possible_crtc; | |
7841 | break; | |
7842 | } | |
79e53945 JB |
7843 | } |
7844 | ||
7845 | /* | |
7846 | * If we didn't find an unused CRTC, don't use any. | |
7847 | */ | |
7848 | if (!crtc) { | |
7173188d CW |
7849 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
7850 | return false; | |
79e53945 JB |
7851 | } |
7852 | ||
7b24056b | 7853 | mutex_lock(&crtc->mutex); |
fc303101 DV |
7854 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
7855 | to_intel_connector(connector)->new_encoder = intel_encoder; | |
79e53945 JB |
7856 | |
7857 | intel_crtc = to_intel_crtc(crtc); | |
412b61d8 VS |
7858 | intel_crtc->new_enabled = true; |
7859 | intel_crtc->new_config = &intel_crtc->config; | |
24218aac | 7860 | old->dpms_mode = connector->dpms; |
8261b191 | 7861 | old->load_detect_temp = true; |
d2dff872 | 7862 | old->release_fb = NULL; |
79e53945 | 7863 | |
6492711d CW |
7864 | if (!mode) |
7865 | mode = &load_detect_mode; | |
79e53945 | 7866 | |
d2dff872 CW |
7867 | /* We need a framebuffer large enough to accommodate all accesses |
7868 | * that the plane may generate whilst we perform load detection. | |
7869 | * We can not rely on the fbcon either being present (we get called | |
7870 | * during its initialisation to detect all boot displays, or it may | |
7871 | * not even exist) or that it is large enough to satisfy the | |
7872 | * requested mode. | |
7873 | */ | |
94352cf9 DV |
7874 | fb = mode_fits_in_fbdev(dev, mode); |
7875 | if (fb == NULL) { | |
d2dff872 | 7876 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
7877 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
7878 | old->release_fb = fb; | |
d2dff872 CW |
7879 | } else |
7880 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 7881 | if (IS_ERR(fb)) { |
d2dff872 | 7882 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 7883 | goto fail; |
79e53945 | 7884 | } |
79e53945 | 7885 | |
c0c36b94 | 7886 | if (intel_set_mode(crtc, mode, 0, 0, fb)) { |
6492711d | 7887 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
7888 | if (old->release_fb) |
7889 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 7890 | goto fail; |
79e53945 | 7891 | } |
7173188d | 7892 | |
79e53945 | 7893 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 7894 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 7895 | return true; |
412b61d8 VS |
7896 | |
7897 | fail: | |
7898 | intel_crtc->new_enabled = crtc->enabled; | |
7899 | if (intel_crtc->new_enabled) | |
7900 | intel_crtc->new_config = &intel_crtc->config; | |
7901 | else | |
7902 | intel_crtc->new_config = NULL; | |
7903 | mutex_unlock(&crtc->mutex); | |
7904 | return false; | |
79e53945 JB |
7905 | } |
7906 | ||
d2434ab7 | 7907 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
8261b191 | 7908 | struct intel_load_detect_pipe *old) |
79e53945 | 7909 | { |
d2434ab7 DV |
7910 | struct intel_encoder *intel_encoder = |
7911 | intel_attached_encoder(connector); | |
4ef69c7a | 7912 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 7913 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 7914 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 7915 | |
d2dff872 CW |
7916 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
7917 | connector->base.id, drm_get_connector_name(connector), | |
7918 | encoder->base.id, drm_get_encoder_name(encoder)); | |
7919 | ||
8261b191 | 7920 | if (old->load_detect_temp) { |
fc303101 DV |
7921 | to_intel_connector(connector)->new_encoder = NULL; |
7922 | intel_encoder->new_crtc = NULL; | |
412b61d8 VS |
7923 | intel_crtc->new_enabled = false; |
7924 | intel_crtc->new_config = NULL; | |
fc303101 | 7925 | intel_set_mode(crtc, NULL, 0, 0, NULL); |
d2dff872 | 7926 | |
36206361 DV |
7927 | if (old->release_fb) { |
7928 | drm_framebuffer_unregister_private(old->release_fb); | |
7929 | drm_framebuffer_unreference(old->release_fb); | |
7930 | } | |
d2dff872 | 7931 | |
67c96400 | 7932 | mutex_unlock(&crtc->mutex); |
0622a53c | 7933 | return; |
79e53945 JB |
7934 | } |
7935 | ||
c751ce4f | 7936 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
7937 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
7938 | connector->funcs->dpms(connector, old->dpms_mode); | |
7b24056b DV |
7939 | |
7940 | mutex_unlock(&crtc->mutex); | |
79e53945 JB |
7941 | } |
7942 | ||
da4a1efa VS |
7943 | static int i9xx_pll_refclk(struct drm_device *dev, |
7944 | const struct intel_crtc_config *pipe_config) | |
7945 | { | |
7946 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7947 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
7948 | ||
7949 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 7950 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
7951 | else if (HAS_PCH_SPLIT(dev)) |
7952 | return 120000; | |
7953 | else if (!IS_GEN2(dev)) | |
7954 | return 96000; | |
7955 | else | |
7956 | return 48000; | |
7957 | } | |
7958 | ||
79e53945 | 7959 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc JB |
7960 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
7961 | struct intel_crtc_config *pipe_config) | |
79e53945 | 7962 | { |
f1f644dc | 7963 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 7964 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 7965 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 7966 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
7967 | u32 fp; |
7968 | intel_clock_t clock; | |
da4a1efa | 7969 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
7970 | |
7971 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 7972 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 7973 | else |
293623f7 | 7974 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
7975 | |
7976 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
7977 | if (IS_PINEVIEW(dev)) { |
7978 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
7979 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
7980 | } else { |
7981 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
7982 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
7983 | } | |
7984 | ||
a6c45cf0 | 7985 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
7986 | if (IS_PINEVIEW(dev)) |
7987 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
7988 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
7989 | else |
7990 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
7991 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
7992 | ||
7993 | switch (dpll & DPLL_MODE_MASK) { | |
7994 | case DPLLB_MODE_DAC_SERIAL: | |
7995 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
7996 | 5 : 10; | |
7997 | break; | |
7998 | case DPLLB_MODE_LVDS: | |
7999 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
8000 | 7 : 14; | |
8001 | break; | |
8002 | default: | |
28c97730 | 8003 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 8004 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 8005 | return; |
79e53945 JB |
8006 | } |
8007 | ||
ac58c3f0 | 8008 | if (IS_PINEVIEW(dev)) |
da4a1efa | 8009 | pineview_clock(refclk, &clock); |
ac58c3f0 | 8010 | else |
da4a1efa | 8011 | i9xx_clock(refclk, &clock); |
79e53945 | 8012 | } else { |
0fb58223 | 8013 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 8014 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
8015 | |
8016 | if (is_lvds) { | |
8017 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
8018 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
8019 | |
8020 | if (lvds & LVDS_CLKB_POWER_UP) | |
8021 | clock.p2 = 7; | |
8022 | else | |
8023 | clock.p2 = 14; | |
79e53945 JB |
8024 | } else { |
8025 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
8026 | clock.p1 = 2; | |
8027 | else { | |
8028 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
8029 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
8030 | } | |
8031 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
8032 | clock.p2 = 4; | |
8033 | else | |
8034 | clock.p2 = 2; | |
79e53945 | 8035 | } |
da4a1efa VS |
8036 | |
8037 | i9xx_clock(refclk, &clock); | |
79e53945 JB |
8038 | } |
8039 | ||
18442d08 VS |
8040 | /* |
8041 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 8042 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
8043 | * encoder's get_config() function. |
8044 | */ | |
8045 | pipe_config->port_clock = clock.dot; | |
f1f644dc JB |
8046 | } |
8047 | ||
6878da05 VS |
8048 | int intel_dotclock_calculate(int link_freq, |
8049 | const struct intel_link_m_n *m_n) | |
f1f644dc | 8050 | { |
f1f644dc JB |
8051 | /* |
8052 | * The calculation for the data clock is: | |
1041a02f | 8053 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 8054 | * But we want to avoid losing precison if possible, so: |
1041a02f | 8055 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
8056 | * |
8057 | * and the link clock is simpler: | |
1041a02f | 8058 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
8059 | */ |
8060 | ||
6878da05 VS |
8061 | if (!m_n->link_n) |
8062 | return 0; | |
f1f644dc | 8063 | |
6878da05 VS |
8064 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
8065 | } | |
f1f644dc | 8066 | |
18442d08 VS |
8067 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
8068 | struct intel_crtc_config *pipe_config) | |
6878da05 VS |
8069 | { |
8070 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 8071 | |
18442d08 VS |
8072 | /* read out port_clock from the DPLL */ |
8073 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 8074 | |
f1f644dc | 8075 | /* |
18442d08 | 8076 | * This value does not include pixel_multiplier. |
241bfc38 | 8077 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
8078 | * agree once we know their relationship in the encoder's |
8079 | * get_config() function. | |
79e53945 | 8080 | */ |
241bfc38 | 8081 | pipe_config->adjusted_mode.crtc_clock = |
18442d08 VS |
8082 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
8083 | &pipe_config->fdi_m_n); | |
79e53945 JB |
8084 | } |
8085 | ||
8086 | /** Returns the currently programmed mode of the given pipe. */ | |
8087 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
8088 | struct drm_crtc *crtc) | |
8089 | { | |
548f245b | 8090 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 8091 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3b117c8f | 8092 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
79e53945 | 8093 | struct drm_display_mode *mode; |
f1f644dc | 8094 | struct intel_crtc_config pipe_config; |
fe2b8f9d PZ |
8095 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
8096 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
8097 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
8098 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 8099 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
8100 | |
8101 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
8102 | if (!mode) | |
8103 | return NULL; | |
8104 | ||
f1f644dc JB |
8105 | /* |
8106 | * Construct a pipe_config sufficient for getting the clock info | |
8107 | * back out of crtc_clock_get. | |
8108 | * | |
8109 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
8110 | * to use a real value here instead. | |
8111 | */ | |
293623f7 | 8112 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 8113 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
8114 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
8115 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
8116 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
8117 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
8118 | ||
773ae034 | 8119 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
8120 | mode->hdisplay = (htot & 0xffff) + 1; |
8121 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
8122 | mode->hsync_start = (hsync & 0xffff) + 1; | |
8123 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
8124 | mode->vdisplay = (vtot & 0xffff) + 1; | |
8125 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
8126 | mode->vsync_start = (vsync & 0xffff) + 1; | |
8127 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
8128 | ||
8129 | drm_mode_set_name(mode); | |
79e53945 JB |
8130 | |
8131 | return mode; | |
8132 | } | |
8133 | ||
3dec0095 | 8134 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
652c393a JB |
8135 | { |
8136 | struct drm_device *dev = crtc->dev; | |
8137 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8138 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8139 | int pipe = intel_crtc->pipe; | |
dbdc6479 JB |
8140 | int dpll_reg = DPLL(pipe); |
8141 | int dpll; | |
652c393a | 8142 | |
bad720ff | 8143 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
8144 | return; |
8145 | ||
8146 | if (!dev_priv->lvds_downclock_avail) | |
8147 | return; | |
8148 | ||
dbdc6479 | 8149 | dpll = I915_READ(dpll_reg); |
652c393a | 8150 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
44d98a61 | 8151 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
652c393a | 8152 | |
8ac5a6d5 | 8153 | assert_panel_unlocked(dev_priv, pipe); |
652c393a JB |
8154 | |
8155 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; | |
8156 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 8157 | intel_wait_for_vblank(dev, pipe); |
dbdc6479 | 8158 | |
652c393a JB |
8159 | dpll = I915_READ(dpll_reg); |
8160 | if (dpll & DISPLAY_RATE_SELECT_FPA1) | |
44d98a61 | 8161 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
652c393a | 8162 | } |
652c393a JB |
8163 | } |
8164 | ||
8165 | static void intel_decrease_pllclock(struct drm_crtc *crtc) | |
8166 | { | |
8167 | struct drm_device *dev = crtc->dev; | |
8168 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8169 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
652c393a | 8170 | |
bad720ff | 8171 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
8172 | return; |
8173 | ||
8174 | if (!dev_priv->lvds_downclock_avail) | |
8175 | return; | |
8176 | ||
8177 | /* | |
8178 | * Since this is called by a timer, we should never get here in | |
8179 | * the manual case. | |
8180 | */ | |
8181 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
8182 | int pipe = intel_crtc->pipe; |
8183 | int dpll_reg = DPLL(pipe); | |
8184 | int dpll; | |
f6e5b160 | 8185 | |
44d98a61 | 8186 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 8187 | |
8ac5a6d5 | 8188 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 8189 | |
dc257cf1 | 8190 | dpll = I915_READ(dpll_reg); |
652c393a JB |
8191 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
8192 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 8193 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
8194 | dpll = I915_READ(dpll_reg); |
8195 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 8196 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
8197 | } |
8198 | ||
8199 | } | |
8200 | ||
f047e395 CW |
8201 | void intel_mark_busy(struct drm_device *dev) |
8202 | { | |
c67a470b PZ |
8203 | struct drm_i915_private *dev_priv = dev->dev_private; |
8204 | ||
8205 | hsw_package_c8_gpu_busy(dev_priv); | |
8206 | i915_update_gfx_val(dev_priv); | |
f047e395 CW |
8207 | } |
8208 | ||
8209 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 8210 | { |
c67a470b | 8211 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 8212 | struct drm_crtc *crtc; |
652c393a | 8213 | |
c67a470b PZ |
8214 | hsw_package_c8_gpu_idle(dev_priv); |
8215 | ||
d330a953 | 8216 | if (!i915.powersave) |
652c393a JB |
8217 | return; |
8218 | ||
652c393a | 8219 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
652c393a JB |
8220 | if (!crtc->fb) |
8221 | continue; | |
8222 | ||
725a5b54 | 8223 | intel_decrease_pllclock(crtc); |
652c393a | 8224 | } |
b29c19b6 | 8225 | |
3d13ef2e | 8226 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 8227 | gen6_rps_idle(dev->dev_private); |
652c393a JB |
8228 | } |
8229 | ||
c65355bb CW |
8230 | void intel_mark_fb_busy(struct drm_i915_gem_object *obj, |
8231 | struct intel_ring_buffer *ring) | |
652c393a | 8232 | { |
f047e395 CW |
8233 | struct drm_device *dev = obj->base.dev; |
8234 | struct drm_crtc *crtc; | |
652c393a | 8235 | |
d330a953 | 8236 | if (!i915.powersave) |
acb87dfb CW |
8237 | return; |
8238 | ||
652c393a JB |
8239 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
8240 | if (!crtc->fb) | |
8241 | continue; | |
8242 | ||
c65355bb CW |
8243 | if (to_intel_framebuffer(crtc->fb)->obj != obj) |
8244 | continue; | |
8245 | ||
8246 | intel_increase_pllclock(crtc); | |
8247 | if (ring && intel_fbc_enabled(dev)) | |
8248 | ring->fbc_dirty = true; | |
652c393a JB |
8249 | } |
8250 | } | |
8251 | ||
79e53945 JB |
8252 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
8253 | { | |
8254 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
8255 | struct drm_device *dev = crtc->dev; |
8256 | struct intel_unpin_work *work; | |
8257 | unsigned long flags; | |
8258 | ||
8259 | spin_lock_irqsave(&dev->event_lock, flags); | |
8260 | work = intel_crtc->unpin_work; | |
8261 | intel_crtc->unpin_work = NULL; | |
8262 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
8263 | ||
8264 | if (work) { | |
8265 | cancel_work_sync(&work->work); | |
8266 | kfree(work); | |
8267 | } | |
79e53945 | 8268 | |
40ccc72b MK |
8269 | intel_crtc_cursor_set(crtc, NULL, 0, 0, 0); |
8270 | ||
79e53945 | 8271 | drm_crtc_cleanup(crtc); |
67e77c5a | 8272 | |
79e53945 JB |
8273 | kfree(intel_crtc); |
8274 | } | |
8275 | ||
6b95a207 KH |
8276 | static void intel_unpin_work_fn(struct work_struct *__work) |
8277 | { | |
8278 | struct intel_unpin_work *work = | |
8279 | container_of(__work, struct intel_unpin_work, work); | |
b4a98e57 | 8280 | struct drm_device *dev = work->crtc->dev; |
6b95a207 | 8281 | |
b4a98e57 | 8282 | mutex_lock(&dev->struct_mutex); |
1690e1eb | 8283 | intel_unpin_fb_obj(work->old_fb_obj); |
05394f39 CW |
8284 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
8285 | drm_gem_object_unreference(&work->old_fb_obj->base); | |
d9e86c0e | 8286 | |
b4a98e57 CW |
8287 | intel_update_fbc(dev); |
8288 | mutex_unlock(&dev->struct_mutex); | |
8289 | ||
8290 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); | |
8291 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); | |
8292 | ||
6b95a207 KH |
8293 | kfree(work); |
8294 | } | |
8295 | ||
1afe3e9d | 8296 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 8297 | struct drm_crtc *crtc) |
6b95a207 KH |
8298 | { |
8299 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6b95a207 KH |
8300 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8301 | struct intel_unpin_work *work; | |
6b95a207 KH |
8302 | unsigned long flags; |
8303 | ||
8304 | /* Ignore early vblank irqs */ | |
8305 | if (intel_crtc == NULL) | |
8306 | return; | |
8307 | ||
8308 | spin_lock_irqsave(&dev->event_lock, flags); | |
8309 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
8310 | |
8311 | /* Ensure we don't miss a work->pending update ... */ | |
8312 | smp_rmb(); | |
8313 | ||
8314 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
8315 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8316 | return; | |
8317 | } | |
8318 | ||
e7d841ca CW |
8319 | /* and that the unpin work is consistent wrt ->pending. */ |
8320 | smp_rmb(); | |
8321 | ||
6b95a207 | 8322 | intel_crtc->unpin_work = NULL; |
6b95a207 | 8323 | |
45a066eb RC |
8324 | if (work->event) |
8325 | drm_send_vblank_event(dev, intel_crtc->pipe, work->event); | |
6b95a207 | 8326 | |
0af7e4df MK |
8327 | drm_vblank_put(dev, intel_crtc->pipe); |
8328 | ||
6b95a207 KH |
8329 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8330 | ||
2c10d571 | 8331 | wake_up_all(&dev_priv->pending_flip_queue); |
b4a98e57 CW |
8332 | |
8333 | queue_work(dev_priv->wq, &work->work); | |
e5510fac JB |
8334 | |
8335 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); | |
6b95a207 KH |
8336 | } |
8337 | ||
1afe3e9d JB |
8338 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
8339 | { | |
8340 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8341 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
8342 | ||
49b14a5c | 8343 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
8344 | } |
8345 | ||
8346 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
8347 | { | |
8348 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8349 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; | |
8350 | ||
49b14a5c | 8351 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
8352 | } |
8353 | ||
6b95a207 KH |
8354 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
8355 | { | |
8356 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8357 | struct intel_crtc *intel_crtc = | |
8358 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
8359 | unsigned long flags; | |
8360 | ||
e7d841ca CW |
8361 | /* NB: An MMIO update of the plane base pointer will also |
8362 | * generate a page-flip completion irq, i.e. every modeset | |
8363 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
8364 | */ | |
6b95a207 | 8365 | spin_lock_irqsave(&dev->event_lock, flags); |
e7d841ca CW |
8366 | if (intel_crtc->unpin_work) |
8367 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); | |
6b95a207 KH |
8368 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8369 | } | |
8370 | ||
e7d841ca CW |
8371 | inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
8372 | { | |
8373 | /* Ensure that the work item is consistent when activating it ... */ | |
8374 | smp_wmb(); | |
8375 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
8376 | /* and that it is marked active as soon as the irq could fire. */ | |
8377 | smp_wmb(); | |
8378 | } | |
8379 | ||
8c9f3aaf JB |
8380 | static int intel_gen2_queue_flip(struct drm_device *dev, |
8381 | struct drm_crtc *crtc, | |
8382 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8383 | struct drm_i915_gem_object *obj, |
8384 | uint32_t flags) | |
8c9f3aaf JB |
8385 | { |
8386 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8387 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8c9f3aaf | 8388 | u32 flip_mask; |
6d90c952 | 8389 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
8390 | int ret; |
8391 | ||
6d90c952 | 8392 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 8393 | if (ret) |
83d4092b | 8394 | goto err; |
8c9f3aaf | 8395 | |
6d90c952 | 8396 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 8397 | if (ret) |
83d4092b | 8398 | goto err_unpin; |
8c9f3aaf JB |
8399 | |
8400 | /* Can't queue multiple flips, so wait for the previous | |
8401 | * one to finish before executing the next. | |
8402 | */ | |
8403 | if (intel_crtc->plane) | |
8404 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
8405 | else | |
8406 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
8407 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
8408 | intel_ring_emit(ring, MI_NOOP); | |
8409 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
8410 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
8411 | intel_ring_emit(ring, fb->pitches[0]); | |
f343c5f6 | 8412 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
6d90c952 | 8413 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
8414 | |
8415 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 8416 | __intel_ring_advance(ring); |
83d4092b CW |
8417 | return 0; |
8418 | ||
8419 | err_unpin: | |
8420 | intel_unpin_fb_obj(obj); | |
8421 | err: | |
8c9f3aaf JB |
8422 | return ret; |
8423 | } | |
8424 | ||
8425 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
8426 | struct drm_crtc *crtc, | |
8427 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8428 | struct drm_i915_gem_object *obj, |
8429 | uint32_t flags) | |
8c9f3aaf JB |
8430 | { |
8431 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8432 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8c9f3aaf | 8433 | u32 flip_mask; |
6d90c952 | 8434 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
8435 | int ret; |
8436 | ||
6d90c952 | 8437 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 8438 | if (ret) |
83d4092b | 8439 | goto err; |
8c9f3aaf | 8440 | |
6d90c952 | 8441 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 8442 | if (ret) |
83d4092b | 8443 | goto err_unpin; |
8c9f3aaf JB |
8444 | |
8445 | if (intel_crtc->plane) | |
8446 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
8447 | else | |
8448 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
8449 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
8450 | intel_ring_emit(ring, MI_NOOP); | |
8451 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
8452 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
8453 | intel_ring_emit(ring, fb->pitches[0]); | |
f343c5f6 | 8454 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
6d90c952 DV |
8455 | intel_ring_emit(ring, MI_NOOP); |
8456 | ||
e7d841ca | 8457 | intel_mark_page_flip_active(intel_crtc); |
09246732 | 8458 | __intel_ring_advance(ring); |
83d4092b CW |
8459 | return 0; |
8460 | ||
8461 | err_unpin: | |
8462 | intel_unpin_fb_obj(obj); | |
8463 | err: | |
8c9f3aaf JB |
8464 | return ret; |
8465 | } | |
8466 | ||
8467 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
8468 | struct drm_crtc *crtc, | |
8469 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8470 | struct drm_i915_gem_object *obj, |
8471 | uint32_t flags) | |
8c9f3aaf JB |
8472 | { |
8473 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8474 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8475 | uint32_t pf, pipesrc; | |
6d90c952 | 8476 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
8477 | int ret; |
8478 | ||
6d90c952 | 8479 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 8480 | if (ret) |
83d4092b | 8481 | goto err; |
8c9f3aaf | 8482 | |
6d90c952 | 8483 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 8484 | if (ret) |
83d4092b | 8485 | goto err_unpin; |
8c9f3aaf JB |
8486 | |
8487 | /* i965+ uses the linear or tiled offsets from the | |
8488 | * Display Registers (which do not change across a page-flip) | |
8489 | * so we need only reprogram the base address. | |
8490 | */ | |
6d90c952 DV |
8491 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
8492 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
8493 | intel_ring_emit(ring, fb->pitches[0]); | |
c2c75131 | 8494 | intel_ring_emit(ring, |
f343c5f6 | 8495 | (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) | |
c2c75131 | 8496 | obj->tiling_mode); |
8c9f3aaf JB |
8497 | |
8498 | /* XXX Enabling the panel-fitter across page-flip is so far | |
8499 | * untested on non-native modes, so ignore it for now. | |
8500 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
8501 | */ | |
8502 | pf = 0; | |
8503 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 8504 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
8505 | |
8506 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 8507 | __intel_ring_advance(ring); |
83d4092b CW |
8508 | return 0; |
8509 | ||
8510 | err_unpin: | |
8511 | intel_unpin_fb_obj(obj); | |
8512 | err: | |
8c9f3aaf JB |
8513 | return ret; |
8514 | } | |
8515 | ||
8516 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
8517 | struct drm_crtc *crtc, | |
8518 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8519 | struct drm_i915_gem_object *obj, |
8520 | uint32_t flags) | |
8c9f3aaf JB |
8521 | { |
8522 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8523 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6d90c952 | 8524 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
8525 | uint32_t pf, pipesrc; |
8526 | int ret; | |
8527 | ||
6d90c952 | 8528 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 8529 | if (ret) |
83d4092b | 8530 | goto err; |
8c9f3aaf | 8531 | |
6d90c952 | 8532 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 8533 | if (ret) |
83d4092b | 8534 | goto err_unpin; |
8c9f3aaf | 8535 | |
6d90c952 DV |
8536 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
8537 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
8538 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
f343c5f6 | 8539 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
8c9f3aaf | 8540 | |
dc257cf1 DV |
8541 | /* Contrary to the suggestions in the documentation, |
8542 | * "Enable Panel Fitter" does not seem to be required when page | |
8543 | * flipping with a non-native mode, and worse causes a normal | |
8544 | * modeset to fail. | |
8545 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
8546 | */ | |
8547 | pf = 0; | |
8c9f3aaf | 8548 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 8549 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
8550 | |
8551 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 8552 | __intel_ring_advance(ring); |
83d4092b CW |
8553 | return 0; |
8554 | ||
8555 | err_unpin: | |
8556 | intel_unpin_fb_obj(obj); | |
8557 | err: | |
8c9f3aaf JB |
8558 | return ret; |
8559 | } | |
8560 | ||
7c9017e5 JB |
8561 | static int intel_gen7_queue_flip(struct drm_device *dev, |
8562 | struct drm_crtc *crtc, | |
8563 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8564 | struct drm_i915_gem_object *obj, |
8565 | uint32_t flags) | |
7c9017e5 JB |
8566 | { |
8567 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8568 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ffe74d75 | 8569 | struct intel_ring_buffer *ring; |
cb05d8de | 8570 | uint32_t plane_bit = 0; |
ffe74d75 CW |
8571 | int len, ret; |
8572 | ||
8573 | ring = obj->ring; | |
1c5fd085 | 8574 | if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS) |
ffe74d75 | 8575 | ring = &dev_priv->ring[BCS]; |
7c9017e5 JB |
8576 | |
8577 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); | |
8578 | if (ret) | |
83d4092b | 8579 | goto err; |
7c9017e5 | 8580 | |
cb05d8de DV |
8581 | switch(intel_crtc->plane) { |
8582 | case PLANE_A: | |
8583 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
8584 | break; | |
8585 | case PLANE_B: | |
8586 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
8587 | break; | |
8588 | case PLANE_C: | |
8589 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
8590 | break; | |
8591 | default: | |
8592 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
8593 | ret = -ENODEV; | |
ab3951eb | 8594 | goto err_unpin; |
cb05d8de DV |
8595 | } |
8596 | ||
ffe74d75 CW |
8597 | len = 4; |
8598 | if (ring->id == RCS) | |
8599 | len += 6; | |
8600 | ||
8601 | ret = intel_ring_begin(ring, len); | |
7c9017e5 | 8602 | if (ret) |
83d4092b | 8603 | goto err_unpin; |
7c9017e5 | 8604 | |
ffe74d75 CW |
8605 | /* Unmask the flip-done completion message. Note that the bspec says that |
8606 | * we should do this for both the BCS and RCS, and that we must not unmask | |
8607 | * more than one flip event at any time (or ensure that one flip message | |
8608 | * can be sent by waiting for flip-done prior to queueing new flips). | |
8609 | * Experimentation says that BCS works despite DERRMR masking all | |
8610 | * flip-done completion events and that unmasking all planes at once | |
8611 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
8612 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
8613 | */ | |
8614 | if (ring->id == RCS) { | |
8615 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
8616 | intel_ring_emit(ring, DERRMR); | |
8617 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
8618 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
8619 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
22613c96 VS |
8620 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | |
8621 | MI_SRM_LRM_GLOBAL_GTT); | |
ffe74d75 CW |
8622 | intel_ring_emit(ring, DERRMR); |
8623 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
8624 | } | |
8625 | ||
cb05d8de | 8626 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 8627 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
f343c5f6 | 8628 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
7c9017e5 | 8629 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
8630 | |
8631 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 8632 | __intel_ring_advance(ring); |
83d4092b CW |
8633 | return 0; |
8634 | ||
8635 | err_unpin: | |
8636 | intel_unpin_fb_obj(obj); | |
8637 | err: | |
7c9017e5 JB |
8638 | return ret; |
8639 | } | |
8640 | ||
8c9f3aaf JB |
8641 | static int intel_default_queue_flip(struct drm_device *dev, |
8642 | struct drm_crtc *crtc, | |
8643 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8644 | struct drm_i915_gem_object *obj, |
8645 | uint32_t flags) | |
8c9f3aaf JB |
8646 | { |
8647 | return -ENODEV; | |
8648 | } | |
8649 | ||
6b95a207 KH |
8650 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
8651 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8652 | struct drm_pending_vblank_event *event, |
8653 | uint32_t page_flip_flags) | |
6b95a207 KH |
8654 | { |
8655 | struct drm_device *dev = crtc->dev; | |
8656 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4a35f83b VS |
8657 | struct drm_framebuffer *old_fb = crtc->fb; |
8658 | struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj; | |
6b95a207 KH |
8659 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8660 | struct intel_unpin_work *work; | |
8c9f3aaf | 8661 | unsigned long flags; |
52e68630 | 8662 | int ret; |
6b95a207 | 8663 | |
e6a595d2 VS |
8664 | /* Can't change pixel format via MI display flips. */ |
8665 | if (fb->pixel_format != crtc->fb->pixel_format) | |
8666 | return -EINVAL; | |
8667 | ||
8668 | /* | |
8669 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
8670 | * Note that pitch changes could also affect these register. | |
8671 | */ | |
8672 | if (INTEL_INFO(dev)->gen > 3 && | |
8673 | (fb->offsets[0] != crtc->fb->offsets[0] || | |
8674 | fb->pitches[0] != crtc->fb->pitches[0])) | |
8675 | return -EINVAL; | |
8676 | ||
b14c5679 | 8677 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
8678 | if (work == NULL) |
8679 | return -ENOMEM; | |
8680 | ||
6b95a207 | 8681 | work->event = event; |
b4a98e57 | 8682 | work->crtc = crtc; |
4a35f83b | 8683 | work->old_fb_obj = to_intel_framebuffer(old_fb)->obj; |
6b95a207 KH |
8684 | INIT_WORK(&work->work, intel_unpin_work_fn); |
8685 | ||
7317c75e JB |
8686 | ret = drm_vblank_get(dev, intel_crtc->pipe); |
8687 | if (ret) | |
8688 | goto free_work; | |
8689 | ||
6b95a207 KH |
8690 | /* We borrow the event spin lock for protecting unpin_work */ |
8691 | spin_lock_irqsave(&dev->event_lock, flags); | |
8692 | if (intel_crtc->unpin_work) { | |
8693 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
8694 | kfree(work); | |
7317c75e | 8695 | drm_vblank_put(dev, intel_crtc->pipe); |
468f0b44 CW |
8696 | |
8697 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
6b95a207 KH |
8698 | return -EBUSY; |
8699 | } | |
8700 | intel_crtc->unpin_work = work; | |
8701 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
8702 | ||
b4a98e57 CW |
8703 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
8704 | flush_workqueue(dev_priv->wq); | |
8705 | ||
79158103 CW |
8706 | ret = i915_mutex_lock_interruptible(dev); |
8707 | if (ret) | |
8708 | goto cleanup; | |
6b95a207 | 8709 | |
75dfca80 | 8710 | /* Reference the objects for the scheduled work. */ |
05394f39 CW |
8711 | drm_gem_object_reference(&work->old_fb_obj->base); |
8712 | drm_gem_object_reference(&obj->base); | |
6b95a207 KH |
8713 | |
8714 | crtc->fb = fb; | |
96b099fd | 8715 | |
e1f99ce6 | 8716 | work->pending_flip_obj = obj; |
e1f99ce6 | 8717 | |
4e5359cd SF |
8718 | work->enable_stall_check = true; |
8719 | ||
b4a98e57 | 8720 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 8721 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 8722 | |
ed8d1975 | 8723 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags); |
8c9f3aaf JB |
8724 | if (ret) |
8725 | goto cleanup_pending; | |
6b95a207 | 8726 | |
7782de3b | 8727 | intel_disable_fbc(dev); |
c65355bb | 8728 | intel_mark_fb_busy(obj, NULL); |
6b95a207 KH |
8729 | mutex_unlock(&dev->struct_mutex); |
8730 | ||
e5510fac JB |
8731 | trace_i915_flip_request(intel_crtc->plane, obj); |
8732 | ||
6b95a207 | 8733 | return 0; |
96b099fd | 8734 | |
8c9f3aaf | 8735 | cleanup_pending: |
b4a98e57 | 8736 | atomic_dec(&intel_crtc->unpin_work_count); |
4a35f83b | 8737 | crtc->fb = old_fb; |
05394f39 CW |
8738 | drm_gem_object_unreference(&work->old_fb_obj->base); |
8739 | drm_gem_object_unreference(&obj->base); | |
96b099fd CW |
8740 | mutex_unlock(&dev->struct_mutex); |
8741 | ||
79158103 | 8742 | cleanup: |
96b099fd CW |
8743 | spin_lock_irqsave(&dev->event_lock, flags); |
8744 | intel_crtc->unpin_work = NULL; | |
8745 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
8746 | ||
7317c75e JB |
8747 | drm_vblank_put(dev, intel_crtc->pipe); |
8748 | free_work: | |
96b099fd CW |
8749 | kfree(work); |
8750 | ||
8751 | return ret; | |
6b95a207 KH |
8752 | } |
8753 | ||
f6e5b160 | 8754 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
8755 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
8756 | .load_lut = intel_crtc_load_lut, | |
f6e5b160 CW |
8757 | }; |
8758 | ||
9a935856 DV |
8759 | /** |
8760 | * intel_modeset_update_staged_output_state | |
8761 | * | |
8762 | * Updates the staged output configuration state, e.g. after we've read out the | |
8763 | * current hw state. | |
8764 | */ | |
8765 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) | |
f6e5b160 | 8766 | { |
7668851f | 8767 | struct intel_crtc *crtc; |
9a935856 DV |
8768 | struct intel_encoder *encoder; |
8769 | struct intel_connector *connector; | |
f6e5b160 | 8770 | |
9a935856 DV |
8771 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8772 | base.head) { | |
8773 | connector->new_encoder = | |
8774 | to_intel_encoder(connector->base.encoder); | |
8775 | } | |
f6e5b160 | 8776 | |
9a935856 DV |
8777 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8778 | base.head) { | |
8779 | encoder->new_crtc = | |
8780 | to_intel_crtc(encoder->base.crtc); | |
8781 | } | |
7668851f VS |
8782 | |
8783 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
8784 | base.head) { | |
8785 | crtc->new_enabled = crtc->base.enabled; | |
7bd0a8e7 VS |
8786 | |
8787 | if (crtc->new_enabled) | |
8788 | crtc->new_config = &crtc->config; | |
8789 | else | |
8790 | crtc->new_config = NULL; | |
7668851f | 8791 | } |
f6e5b160 CW |
8792 | } |
8793 | ||
9a935856 DV |
8794 | /** |
8795 | * intel_modeset_commit_output_state | |
8796 | * | |
8797 | * This function copies the stage display pipe configuration to the real one. | |
8798 | */ | |
8799 | static void intel_modeset_commit_output_state(struct drm_device *dev) | |
8800 | { | |
7668851f | 8801 | struct intel_crtc *crtc; |
9a935856 DV |
8802 | struct intel_encoder *encoder; |
8803 | struct intel_connector *connector; | |
f6e5b160 | 8804 | |
9a935856 DV |
8805 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8806 | base.head) { | |
8807 | connector->base.encoder = &connector->new_encoder->base; | |
8808 | } | |
f6e5b160 | 8809 | |
9a935856 DV |
8810 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8811 | base.head) { | |
8812 | encoder->base.crtc = &encoder->new_crtc->base; | |
8813 | } | |
7668851f VS |
8814 | |
8815 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
8816 | base.head) { | |
8817 | crtc->base.enabled = crtc->new_enabled; | |
8818 | } | |
9a935856 DV |
8819 | } |
8820 | ||
050f7aeb DV |
8821 | static void |
8822 | connected_sink_compute_bpp(struct intel_connector * connector, | |
8823 | struct intel_crtc_config *pipe_config) | |
8824 | { | |
8825 | int bpp = pipe_config->pipe_bpp; | |
8826 | ||
8827 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
8828 | connector->base.base.id, | |
8829 | drm_get_connector_name(&connector->base)); | |
8830 | ||
8831 | /* Don't use an invalid EDID bpc value */ | |
8832 | if (connector->base.display_info.bpc && | |
8833 | connector->base.display_info.bpc * 3 < bpp) { | |
8834 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
8835 | bpp, connector->base.display_info.bpc*3); | |
8836 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
8837 | } | |
8838 | ||
8839 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
8840 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
8841 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
8842 | bpp); | |
8843 | pipe_config->pipe_bpp = 24; | |
8844 | } | |
8845 | } | |
8846 | ||
4e53c2e0 | 8847 | static int |
050f7aeb DV |
8848 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
8849 | struct drm_framebuffer *fb, | |
8850 | struct intel_crtc_config *pipe_config) | |
4e53c2e0 | 8851 | { |
050f7aeb DV |
8852 | struct drm_device *dev = crtc->base.dev; |
8853 | struct intel_connector *connector; | |
4e53c2e0 DV |
8854 | int bpp; |
8855 | ||
d42264b1 DV |
8856 | switch (fb->pixel_format) { |
8857 | case DRM_FORMAT_C8: | |
4e53c2e0 DV |
8858 | bpp = 8*3; /* since we go through a colormap */ |
8859 | break; | |
d42264b1 DV |
8860 | case DRM_FORMAT_XRGB1555: |
8861 | case DRM_FORMAT_ARGB1555: | |
8862 | /* checked in intel_framebuffer_init already */ | |
8863 | if (WARN_ON(INTEL_INFO(dev)->gen > 3)) | |
8864 | return -EINVAL; | |
8865 | case DRM_FORMAT_RGB565: | |
4e53c2e0 DV |
8866 | bpp = 6*3; /* min is 18bpp */ |
8867 | break; | |
d42264b1 DV |
8868 | case DRM_FORMAT_XBGR8888: |
8869 | case DRM_FORMAT_ABGR8888: | |
8870 | /* checked in intel_framebuffer_init already */ | |
8871 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
8872 | return -EINVAL; | |
8873 | case DRM_FORMAT_XRGB8888: | |
8874 | case DRM_FORMAT_ARGB8888: | |
4e53c2e0 DV |
8875 | bpp = 8*3; |
8876 | break; | |
d42264b1 DV |
8877 | case DRM_FORMAT_XRGB2101010: |
8878 | case DRM_FORMAT_ARGB2101010: | |
8879 | case DRM_FORMAT_XBGR2101010: | |
8880 | case DRM_FORMAT_ABGR2101010: | |
8881 | /* checked in intel_framebuffer_init already */ | |
8882 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
baba133a | 8883 | return -EINVAL; |
4e53c2e0 DV |
8884 | bpp = 10*3; |
8885 | break; | |
baba133a | 8886 | /* TODO: gen4+ supports 16 bpc floating point, too. */ |
4e53c2e0 DV |
8887 | default: |
8888 | DRM_DEBUG_KMS("unsupported depth\n"); | |
8889 | return -EINVAL; | |
8890 | } | |
8891 | ||
4e53c2e0 DV |
8892 | pipe_config->pipe_bpp = bpp; |
8893 | ||
8894 | /* Clamp display bpp to EDID value */ | |
8895 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
050f7aeb | 8896 | base.head) { |
1b829e05 DV |
8897 | if (!connector->new_encoder || |
8898 | connector->new_encoder->new_crtc != crtc) | |
4e53c2e0 DV |
8899 | continue; |
8900 | ||
050f7aeb | 8901 | connected_sink_compute_bpp(connector, pipe_config); |
4e53c2e0 DV |
8902 | } |
8903 | ||
8904 | return bpp; | |
8905 | } | |
8906 | ||
644db711 DV |
8907 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
8908 | { | |
8909 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
8910 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 8911 | mode->crtc_clock, |
644db711 DV |
8912 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
8913 | mode->crtc_hsync_end, mode->crtc_htotal, | |
8914 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
8915 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
8916 | } | |
8917 | ||
c0b03411 DV |
8918 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
8919 | struct intel_crtc_config *pipe_config, | |
8920 | const char *context) | |
8921 | { | |
8922 | DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id, | |
8923 | context, pipe_name(crtc->pipe)); | |
8924 | ||
8925 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
8926 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
8927 | pipe_config->pipe_bpp, pipe_config->dither); | |
8928 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
8929 | pipe_config->has_pch_encoder, | |
8930 | pipe_config->fdi_lanes, | |
8931 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
8932 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
8933 | pipe_config->fdi_m_n.tu); | |
eb14cb74 VS |
8934 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
8935 | pipe_config->has_dp_encoder, | |
8936 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, | |
8937 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
8938 | pipe_config->dp_m_n.tu); | |
c0b03411 DV |
8939 | DRM_DEBUG_KMS("requested mode:\n"); |
8940 | drm_mode_debug_printmodeline(&pipe_config->requested_mode); | |
8941 | DRM_DEBUG_KMS("adjusted mode:\n"); | |
8942 | drm_mode_debug_printmodeline(&pipe_config->adjusted_mode); | |
644db711 | 8943 | intel_dump_crtc_timings(&pipe_config->adjusted_mode); |
d71b8d4a | 8944 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
8945 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
8946 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
c0b03411 DV |
8947 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
8948 | pipe_config->gmch_pfit.control, | |
8949 | pipe_config->gmch_pfit.pgm_ratios, | |
8950 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 8951 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 8952 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
8953 | pipe_config->pch_pfit.size, |
8954 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 8955 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 8956 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
c0b03411 DV |
8957 | } |
8958 | ||
accfc0c5 DV |
8959 | static bool check_encoder_cloning(struct drm_crtc *crtc) |
8960 | { | |
8961 | int num_encoders = 0; | |
8962 | bool uncloneable_encoders = false; | |
8963 | struct intel_encoder *encoder; | |
8964 | ||
8965 | list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, | |
8966 | base.head) { | |
8967 | if (&encoder->new_crtc->base != crtc) | |
8968 | continue; | |
8969 | ||
8970 | num_encoders++; | |
8971 | if (!encoder->cloneable) | |
8972 | uncloneable_encoders = true; | |
8973 | } | |
8974 | ||
8975 | return !(num_encoders > 1 && uncloneable_encoders); | |
8976 | } | |
8977 | ||
b8cecdf5 DV |
8978 | static struct intel_crtc_config * |
8979 | intel_modeset_pipe_config(struct drm_crtc *crtc, | |
4e53c2e0 | 8980 | struct drm_framebuffer *fb, |
b8cecdf5 | 8981 | struct drm_display_mode *mode) |
ee7b9f93 | 8982 | { |
7758a113 | 8983 | struct drm_device *dev = crtc->dev; |
7758a113 | 8984 | struct intel_encoder *encoder; |
b8cecdf5 | 8985 | struct intel_crtc_config *pipe_config; |
e29c22c0 DV |
8986 | int plane_bpp, ret = -EINVAL; |
8987 | bool retry = true; | |
ee7b9f93 | 8988 | |
accfc0c5 DV |
8989 | if (!check_encoder_cloning(crtc)) { |
8990 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
8991 | return ERR_PTR(-EINVAL); | |
8992 | } | |
8993 | ||
b8cecdf5 DV |
8994 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
8995 | if (!pipe_config) | |
7758a113 DV |
8996 | return ERR_PTR(-ENOMEM); |
8997 | ||
b8cecdf5 DV |
8998 | drm_mode_copy(&pipe_config->adjusted_mode, mode); |
8999 | drm_mode_copy(&pipe_config->requested_mode, mode); | |
37327abd | 9000 | |
e143a21c DV |
9001 | pipe_config->cpu_transcoder = |
9002 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
c0d43d62 | 9003 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
b8cecdf5 | 9004 | |
2960bc9c ID |
9005 | /* |
9006 | * Sanitize sync polarity flags based on requested ones. If neither | |
9007 | * positive or negative polarity is requested, treat this as meaning | |
9008 | * negative polarity. | |
9009 | */ | |
9010 | if (!(pipe_config->adjusted_mode.flags & | |
9011 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) | |
9012 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; | |
9013 | ||
9014 | if (!(pipe_config->adjusted_mode.flags & | |
9015 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) | |
9016 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; | |
9017 | ||
050f7aeb DV |
9018 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
9019 | * plane pixel format and any sink constraints into account. Returns the | |
9020 | * source plane bpp so that dithering can be selected on mismatches | |
9021 | * after encoders and crtc also have had their say. */ | |
9022 | plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), | |
9023 | fb, pipe_config); | |
4e53c2e0 DV |
9024 | if (plane_bpp < 0) |
9025 | goto fail; | |
9026 | ||
e41a56be VS |
9027 | /* |
9028 | * Determine the real pipe dimensions. Note that stereo modes can | |
9029 | * increase the actual pipe size due to the frame doubling and | |
9030 | * insertion of additional space for blanks between the frame. This | |
9031 | * is stored in the crtc timings. We use the requested mode to do this | |
9032 | * computation to clearly distinguish it from the adjusted mode, which | |
9033 | * can be changed by the connectors in the below retry loop. | |
9034 | */ | |
9035 | drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE); | |
9036 | pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay; | |
9037 | pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay; | |
9038 | ||
e29c22c0 | 9039 | encoder_retry: |
ef1b460d | 9040 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 9041 | pipe_config->port_clock = 0; |
ef1b460d | 9042 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 9043 | |
135c81b8 | 9044 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
6ce70f5e | 9045 | drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE); |
135c81b8 | 9046 | |
7758a113 DV |
9047 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
9048 | * adjust it according to limitations or connector properties, and also | |
9049 | * a chance to reject the mode entirely. | |
47f1c6c9 | 9050 | */ |
7758a113 DV |
9051 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9052 | base.head) { | |
47f1c6c9 | 9053 | |
7758a113 DV |
9054 | if (&encoder->new_crtc->base != crtc) |
9055 | continue; | |
7ae89233 | 9056 | |
efea6e8e DV |
9057 | if (!(encoder->compute_config(encoder, pipe_config))) { |
9058 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
9059 | goto fail; |
9060 | } | |
ee7b9f93 | 9061 | } |
47f1c6c9 | 9062 | |
ff9a6750 DV |
9063 | /* Set default port clock if not overwritten by the encoder. Needs to be |
9064 | * done afterwards in case the encoder adjusts the mode. */ | |
9065 | if (!pipe_config->port_clock) | |
241bfc38 DL |
9066 | pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock |
9067 | * pipe_config->pixel_multiplier; | |
ff9a6750 | 9068 | |
a43f6e0f | 9069 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 9070 | if (ret < 0) { |
7758a113 DV |
9071 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
9072 | goto fail; | |
ee7b9f93 | 9073 | } |
e29c22c0 DV |
9074 | |
9075 | if (ret == RETRY) { | |
9076 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
9077 | ret = -EINVAL; | |
9078 | goto fail; | |
9079 | } | |
9080 | ||
9081 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
9082 | retry = false; | |
9083 | goto encoder_retry; | |
9084 | } | |
9085 | ||
4e53c2e0 DV |
9086 | pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; |
9087 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", | |
9088 | plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); | |
9089 | ||
b8cecdf5 | 9090 | return pipe_config; |
7758a113 | 9091 | fail: |
b8cecdf5 | 9092 | kfree(pipe_config); |
e29c22c0 | 9093 | return ERR_PTR(ret); |
ee7b9f93 | 9094 | } |
47f1c6c9 | 9095 | |
e2e1ed41 DV |
9096 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
9097 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ | |
9098 | static void | |
9099 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, | |
9100 | unsigned *prepare_pipes, unsigned *disable_pipes) | |
79e53945 JB |
9101 | { |
9102 | struct intel_crtc *intel_crtc; | |
e2e1ed41 DV |
9103 | struct drm_device *dev = crtc->dev; |
9104 | struct intel_encoder *encoder; | |
9105 | struct intel_connector *connector; | |
9106 | struct drm_crtc *tmp_crtc; | |
79e53945 | 9107 | |
e2e1ed41 | 9108 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
79e53945 | 9109 | |
e2e1ed41 DV |
9110 | /* Check which crtcs have changed outputs connected to them, these need |
9111 | * to be part of the prepare_pipes mask. We don't (yet) support global | |
9112 | * modeset across multiple crtcs, so modeset_pipes will only have one | |
9113 | * bit set at most. */ | |
9114 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
9115 | base.head) { | |
9116 | if (connector->base.encoder == &connector->new_encoder->base) | |
9117 | continue; | |
79e53945 | 9118 | |
e2e1ed41 DV |
9119 | if (connector->base.encoder) { |
9120 | tmp_crtc = connector->base.encoder->crtc; | |
9121 | ||
9122 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
9123 | } | |
9124 | ||
9125 | if (connector->new_encoder) | |
9126 | *prepare_pipes |= | |
9127 | 1 << connector->new_encoder->new_crtc->pipe; | |
79e53945 JB |
9128 | } |
9129 | ||
e2e1ed41 DV |
9130 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9131 | base.head) { | |
9132 | if (encoder->base.crtc == &encoder->new_crtc->base) | |
9133 | continue; | |
9134 | ||
9135 | if (encoder->base.crtc) { | |
9136 | tmp_crtc = encoder->base.crtc; | |
9137 | ||
9138 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
9139 | } | |
9140 | ||
9141 | if (encoder->new_crtc) | |
9142 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; | |
80824003 JB |
9143 | } |
9144 | ||
7668851f | 9145 | /* Check for pipes that will be enabled/disabled ... */ |
e2e1ed41 DV |
9146 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
9147 | base.head) { | |
7668851f | 9148 | if (intel_crtc->base.enabled == intel_crtc->new_enabled) |
e2e1ed41 | 9149 | continue; |
7e7d76c3 | 9150 | |
7668851f | 9151 | if (!intel_crtc->new_enabled) |
e2e1ed41 | 9152 | *disable_pipes |= 1 << intel_crtc->pipe; |
7668851f VS |
9153 | else |
9154 | *prepare_pipes |= 1 << intel_crtc->pipe; | |
7e7d76c3 JB |
9155 | } |
9156 | ||
e2e1ed41 DV |
9157 | |
9158 | /* set_mode is also used to update properties on life display pipes. */ | |
9159 | intel_crtc = to_intel_crtc(crtc); | |
7668851f | 9160 | if (intel_crtc->new_enabled) |
e2e1ed41 DV |
9161 | *prepare_pipes |= 1 << intel_crtc->pipe; |
9162 | ||
b6c5164d DV |
9163 | /* |
9164 | * For simplicity do a full modeset on any pipe where the output routing | |
9165 | * changed. We could be more clever, but that would require us to be | |
9166 | * more careful with calling the relevant encoder->mode_set functions. | |
9167 | */ | |
e2e1ed41 DV |
9168 | if (*prepare_pipes) |
9169 | *modeset_pipes = *prepare_pipes; | |
9170 | ||
9171 | /* ... and mask these out. */ | |
9172 | *modeset_pipes &= ~(*disable_pipes); | |
9173 | *prepare_pipes &= ~(*disable_pipes); | |
b6c5164d DV |
9174 | |
9175 | /* | |
9176 | * HACK: We don't (yet) fully support global modesets. intel_set_config | |
9177 | * obies this rule, but the modeset restore mode of | |
9178 | * intel_modeset_setup_hw_state does not. | |
9179 | */ | |
9180 | *modeset_pipes &= 1 << intel_crtc->pipe; | |
9181 | *prepare_pipes &= 1 << intel_crtc->pipe; | |
e3641d3f DV |
9182 | |
9183 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", | |
9184 | *modeset_pipes, *prepare_pipes, *disable_pipes); | |
47f1c6c9 | 9185 | } |
79e53945 | 9186 | |
ea9d758d | 9187 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 9188 | { |
ea9d758d | 9189 | struct drm_encoder *encoder; |
f6e5b160 | 9190 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 9191 | |
ea9d758d DV |
9192 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
9193 | if (encoder->crtc == crtc) | |
9194 | return true; | |
9195 | ||
9196 | return false; | |
9197 | } | |
9198 | ||
9199 | static void | |
9200 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) | |
9201 | { | |
9202 | struct intel_encoder *intel_encoder; | |
9203 | struct intel_crtc *intel_crtc; | |
9204 | struct drm_connector *connector; | |
9205 | ||
9206 | list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list, | |
9207 | base.head) { | |
9208 | if (!intel_encoder->base.crtc) | |
9209 | continue; | |
9210 | ||
9211 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
9212 | ||
9213 | if (prepare_pipes & (1 << intel_crtc->pipe)) | |
9214 | intel_encoder->connectors_active = false; | |
9215 | } | |
9216 | ||
9217 | intel_modeset_commit_output_state(dev); | |
9218 | ||
7668851f | 9219 | /* Double check state. */ |
ea9d758d DV |
9220 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
9221 | base.head) { | |
7668851f | 9222 | WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base)); |
7bd0a8e7 VS |
9223 | WARN_ON(intel_crtc->new_config && |
9224 | intel_crtc->new_config != &intel_crtc->config); | |
9225 | WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config); | |
ea9d758d DV |
9226 | } |
9227 | ||
9228 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
9229 | if (!connector->encoder || !connector->encoder->crtc) | |
9230 | continue; | |
9231 | ||
9232 | intel_crtc = to_intel_crtc(connector->encoder->crtc); | |
9233 | ||
9234 | if (prepare_pipes & (1 << intel_crtc->pipe)) { | |
68d34720 DV |
9235 | struct drm_property *dpms_property = |
9236 | dev->mode_config.dpms_property; | |
9237 | ||
ea9d758d | 9238 | connector->dpms = DRM_MODE_DPMS_ON; |
662595df | 9239 | drm_object_property_set_value(&connector->base, |
68d34720 DV |
9240 | dpms_property, |
9241 | DRM_MODE_DPMS_ON); | |
ea9d758d DV |
9242 | |
9243 | intel_encoder = to_intel_encoder(connector->encoder); | |
9244 | intel_encoder->connectors_active = true; | |
9245 | } | |
9246 | } | |
9247 | ||
9248 | } | |
9249 | ||
3bd26263 | 9250 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 9251 | { |
3bd26263 | 9252 | int diff; |
f1f644dc JB |
9253 | |
9254 | if (clock1 == clock2) | |
9255 | return true; | |
9256 | ||
9257 | if (!clock1 || !clock2) | |
9258 | return false; | |
9259 | ||
9260 | diff = abs(clock1 - clock2); | |
9261 | ||
9262 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
9263 | return true; | |
9264 | ||
9265 | return false; | |
9266 | } | |
9267 | ||
25c5b266 DV |
9268 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
9269 | list_for_each_entry((intel_crtc), \ | |
9270 | &(dev)->mode_config.crtc_list, \ | |
9271 | base.head) \ | |
0973f18f | 9272 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 9273 | |
0e8ffe1b | 9274 | static bool |
2fa2fe9a DV |
9275 | intel_pipe_config_compare(struct drm_device *dev, |
9276 | struct intel_crtc_config *current_config, | |
0e8ffe1b DV |
9277 | struct intel_crtc_config *pipe_config) |
9278 | { | |
66e985c0 DV |
9279 | #define PIPE_CONF_CHECK_X(name) \ |
9280 | if (current_config->name != pipe_config->name) { \ | |
9281 | DRM_ERROR("mismatch in " #name " " \ | |
9282 | "(expected 0x%08x, found 0x%08x)\n", \ | |
9283 | current_config->name, \ | |
9284 | pipe_config->name); \ | |
9285 | return false; \ | |
9286 | } | |
9287 | ||
08a24034 DV |
9288 | #define PIPE_CONF_CHECK_I(name) \ |
9289 | if (current_config->name != pipe_config->name) { \ | |
9290 | DRM_ERROR("mismatch in " #name " " \ | |
9291 | "(expected %i, found %i)\n", \ | |
9292 | current_config->name, \ | |
9293 | pipe_config->name); \ | |
9294 | return false; \ | |
88adfff1 DV |
9295 | } |
9296 | ||
1bd1bd80 DV |
9297 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
9298 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
6f02488e | 9299 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
9300 | "(expected %i, found %i)\n", \ |
9301 | current_config->name & (mask), \ | |
9302 | pipe_config->name & (mask)); \ | |
9303 | return false; \ | |
9304 | } | |
9305 | ||
5e550656 VS |
9306 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
9307 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
9308 | DRM_ERROR("mismatch in " #name " " \ | |
9309 | "(expected %i, found %i)\n", \ | |
9310 | current_config->name, \ | |
9311 | pipe_config->name); \ | |
9312 | return false; \ | |
9313 | } | |
9314 | ||
bb760063 DV |
9315 | #define PIPE_CONF_QUIRK(quirk) \ |
9316 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
9317 | ||
eccb140b DV |
9318 | PIPE_CONF_CHECK_I(cpu_transcoder); |
9319 | ||
08a24034 DV |
9320 | PIPE_CONF_CHECK_I(has_pch_encoder); |
9321 | PIPE_CONF_CHECK_I(fdi_lanes); | |
72419203 DV |
9322 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
9323 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); | |
9324 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); | |
9325 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); | |
9326 | PIPE_CONF_CHECK_I(fdi_m_n.tu); | |
08a24034 | 9327 | |
eb14cb74 VS |
9328 | PIPE_CONF_CHECK_I(has_dp_encoder); |
9329 | PIPE_CONF_CHECK_I(dp_m_n.gmch_m); | |
9330 | PIPE_CONF_CHECK_I(dp_m_n.gmch_n); | |
9331 | PIPE_CONF_CHECK_I(dp_m_n.link_m); | |
9332 | PIPE_CONF_CHECK_I(dp_m_n.link_n); | |
9333 | PIPE_CONF_CHECK_I(dp_m_n.tu); | |
9334 | ||
1bd1bd80 DV |
9335 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); |
9336 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); | |
9337 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start); | |
9338 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end); | |
9339 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start); | |
9340 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end); | |
9341 | ||
9342 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay); | |
9343 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal); | |
9344 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start); | |
9345 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end); | |
9346 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start); | |
9347 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end); | |
9348 | ||
c93f54cf | 9349 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6c49f241 | 9350 | |
1bd1bd80 DV |
9351 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
9352 | DRM_MODE_FLAG_INTERLACE); | |
9353 | ||
bb760063 DV |
9354 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
9355 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
9356 | DRM_MODE_FLAG_PHSYNC); | |
9357 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
9358 | DRM_MODE_FLAG_NHSYNC); | |
9359 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
9360 | DRM_MODE_FLAG_PVSYNC); | |
9361 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
9362 | DRM_MODE_FLAG_NVSYNC); | |
9363 | } | |
045ac3b5 | 9364 | |
37327abd VS |
9365 | PIPE_CONF_CHECK_I(pipe_src_w); |
9366 | PIPE_CONF_CHECK_I(pipe_src_h); | |
1bd1bd80 | 9367 | |
2fa2fe9a DV |
9368 | PIPE_CONF_CHECK_I(gmch_pfit.control); |
9369 | /* pfit ratios are autocomputed by the hw on gen4+ */ | |
9370 | if (INTEL_INFO(dev)->gen < 4) | |
9371 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
9372 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); | |
fd4daa9c CW |
9373 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
9374 | if (current_config->pch_pfit.enabled) { | |
9375 | PIPE_CONF_CHECK_I(pch_pfit.pos); | |
9376 | PIPE_CONF_CHECK_I(pch_pfit.size); | |
9377 | } | |
2fa2fe9a | 9378 | |
e59150dc JB |
9379 | /* BDW+ don't expose a synchronous way to read the state */ |
9380 | if (IS_HASWELL(dev)) | |
9381 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 9382 | |
282740f7 VS |
9383 | PIPE_CONF_CHECK_I(double_wide); |
9384 | ||
c0d43d62 | 9385 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 9386 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 9387 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
9388 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
9389 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
c0d43d62 | 9390 | |
42571aef VS |
9391 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
9392 | PIPE_CONF_CHECK_I(pipe_bpp); | |
9393 | ||
a9a7e98a JB |
9394 | PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock); |
9395 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); | |
5e550656 | 9396 | |
66e985c0 | 9397 | #undef PIPE_CONF_CHECK_X |
08a24034 | 9398 | #undef PIPE_CONF_CHECK_I |
1bd1bd80 | 9399 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 9400 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 9401 | #undef PIPE_CONF_QUIRK |
88adfff1 | 9402 | |
0e8ffe1b DV |
9403 | return true; |
9404 | } | |
9405 | ||
91d1b4bd DV |
9406 | static void |
9407 | check_connector_state(struct drm_device *dev) | |
8af6cf88 | 9408 | { |
8af6cf88 DV |
9409 | struct intel_connector *connector; |
9410 | ||
9411 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
9412 | base.head) { | |
9413 | /* This also checks the encoder/connector hw state with the | |
9414 | * ->get_hw_state callbacks. */ | |
9415 | intel_connector_check_state(connector); | |
9416 | ||
9417 | WARN(&connector->new_encoder->base != connector->base.encoder, | |
9418 | "connector's staged encoder doesn't match current encoder\n"); | |
9419 | } | |
91d1b4bd DV |
9420 | } |
9421 | ||
9422 | static void | |
9423 | check_encoder_state(struct drm_device *dev) | |
9424 | { | |
9425 | struct intel_encoder *encoder; | |
9426 | struct intel_connector *connector; | |
8af6cf88 DV |
9427 | |
9428 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
9429 | base.head) { | |
9430 | bool enabled = false; | |
9431 | bool active = false; | |
9432 | enum pipe pipe, tracked_pipe; | |
9433 | ||
9434 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
9435 | encoder->base.base.id, | |
9436 | drm_get_encoder_name(&encoder->base)); | |
9437 | ||
9438 | WARN(&encoder->new_crtc->base != encoder->base.crtc, | |
9439 | "encoder's stage crtc doesn't match current crtc\n"); | |
9440 | WARN(encoder->connectors_active && !encoder->base.crtc, | |
9441 | "encoder's active_connectors set, but no crtc\n"); | |
9442 | ||
9443 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
9444 | base.head) { | |
9445 | if (connector->base.encoder != &encoder->base) | |
9446 | continue; | |
9447 | enabled = true; | |
9448 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
9449 | active = true; | |
9450 | } | |
9451 | WARN(!!encoder->base.crtc != enabled, | |
9452 | "encoder's enabled state mismatch " | |
9453 | "(expected %i, found %i)\n", | |
9454 | !!encoder->base.crtc, enabled); | |
9455 | WARN(active && !encoder->base.crtc, | |
9456 | "active encoder with no crtc\n"); | |
9457 | ||
9458 | WARN(encoder->connectors_active != active, | |
9459 | "encoder's computed active state doesn't match tracked active state " | |
9460 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
9461 | ||
9462 | active = encoder->get_hw_state(encoder, &pipe); | |
9463 | WARN(active != encoder->connectors_active, | |
9464 | "encoder's hw state doesn't match sw tracking " | |
9465 | "(expected %i, found %i)\n", | |
9466 | encoder->connectors_active, active); | |
9467 | ||
9468 | if (!encoder->base.crtc) | |
9469 | continue; | |
9470 | ||
9471 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
9472 | WARN(active && pipe != tracked_pipe, | |
9473 | "active encoder's pipe doesn't match" | |
9474 | "(expected %i, found %i)\n", | |
9475 | tracked_pipe, pipe); | |
9476 | ||
9477 | } | |
91d1b4bd DV |
9478 | } |
9479 | ||
9480 | static void | |
9481 | check_crtc_state(struct drm_device *dev) | |
9482 | { | |
9483 | drm_i915_private_t *dev_priv = dev->dev_private; | |
9484 | struct intel_crtc *crtc; | |
9485 | struct intel_encoder *encoder; | |
9486 | struct intel_crtc_config pipe_config; | |
8af6cf88 DV |
9487 | |
9488 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
9489 | base.head) { | |
9490 | bool enabled = false; | |
9491 | bool active = false; | |
9492 | ||
045ac3b5 JB |
9493 | memset(&pipe_config, 0, sizeof(pipe_config)); |
9494 | ||
8af6cf88 DV |
9495 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
9496 | crtc->base.base.id); | |
9497 | ||
9498 | WARN(crtc->active && !crtc->base.enabled, | |
9499 | "active crtc, but not enabled in sw tracking\n"); | |
9500 | ||
9501 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
9502 | base.head) { | |
9503 | if (encoder->base.crtc != &crtc->base) | |
9504 | continue; | |
9505 | enabled = true; | |
9506 | if (encoder->connectors_active) | |
9507 | active = true; | |
9508 | } | |
6c49f241 | 9509 | |
8af6cf88 DV |
9510 | WARN(active != crtc->active, |
9511 | "crtc's computed active state doesn't match tracked active state " | |
9512 | "(expected %i, found %i)\n", active, crtc->active); | |
9513 | WARN(enabled != crtc->base.enabled, | |
9514 | "crtc's computed enabled state doesn't match tracked enabled state " | |
9515 | "(expected %i, found %i)\n", enabled, crtc->base.enabled); | |
9516 | ||
0e8ffe1b DV |
9517 | active = dev_priv->display.get_pipe_config(crtc, |
9518 | &pipe_config); | |
d62cf62a DV |
9519 | |
9520 | /* hw state is inconsistent with the pipe A quirk */ | |
9521 | if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
9522 | active = crtc->active; | |
9523 | ||
6c49f241 DV |
9524 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9525 | base.head) { | |
3eaba51c | 9526 | enum pipe pipe; |
6c49f241 DV |
9527 | if (encoder->base.crtc != &crtc->base) |
9528 | continue; | |
1d37b689 | 9529 | if (encoder->get_hw_state(encoder, &pipe)) |
6c49f241 DV |
9530 | encoder->get_config(encoder, &pipe_config); |
9531 | } | |
9532 | ||
0e8ffe1b DV |
9533 | WARN(crtc->active != active, |
9534 | "crtc active state doesn't match with hw state " | |
9535 | "(expected %i, found %i)\n", crtc->active, active); | |
9536 | ||
c0b03411 DV |
9537 | if (active && |
9538 | !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) { | |
9539 | WARN(1, "pipe state doesn't match!\n"); | |
9540 | intel_dump_pipe_config(crtc, &pipe_config, | |
9541 | "[hw state]"); | |
9542 | intel_dump_pipe_config(crtc, &crtc->config, | |
9543 | "[sw state]"); | |
9544 | } | |
8af6cf88 DV |
9545 | } |
9546 | } | |
9547 | ||
91d1b4bd DV |
9548 | static void |
9549 | check_shared_dpll_state(struct drm_device *dev) | |
9550 | { | |
9551 | drm_i915_private_t *dev_priv = dev->dev_private; | |
9552 | struct intel_crtc *crtc; | |
9553 | struct intel_dpll_hw_state dpll_hw_state; | |
9554 | int i; | |
5358901f DV |
9555 | |
9556 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
9557 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
9558 | int enabled_crtcs = 0, active_crtcs = 0; | |
9559 | bool active; | |
9560 | ||
9561 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
9562 | ||
9563 | DRM_DEBUG_KMS("%s\n", pll->name); | |
9564 | ||
9565 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
9566 | ||
9567 | WARN(pll->active > pll->refcount, | |
9568 | "more active pll users than references: %i vs %i\n", | |
9569 | pll->active, pll->refcount); | |
9570 | WARN(pll->active && !pll->on, | |
9571 | "pll in active use but not on in sw tracking\n"); | |
35c95375 DV |
9572 | WARN(pll->on && !pll->active, |
9573 | "pll in on but not on in use in sw tracking\n"); | |
5358901f DV |
9574 | WARN(pll->on != active, |
9575 | "pll on state mismatch (expected %i, found %i)\n", | |
9576 | pll->on, active); | |
9577 | ||
9578 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
9579 | base.head) { | |
9580 | if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll) | |
9581 | enabled_crtcs++; | |
9582 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
9583 | active_crtcs++; | |
9584 | } | |
9585 | WARN(pll->active != active_crtcs, | |
9586 | "pll active crtcs mismatch (expected %i, found %i)\n", | |
9587 | pll->active, active_crtcs); | |
9588 | WARN(pll->refcount != enabled_crtcs, | |
9589 | "pll enabled crtcs mismatch (expected %i, found %i)\n", | |
9590 | pll->refcount, enabled_crtcs); | |
66e985c0 DV |
9591 | |
9592 | WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state, | |
9593 | sizeof(dpll_hw_state)), | |
9594 | "pll hw state mismatch\n"); | |
5358901f | 9595 | } |
8af6cf88 DV |
9596 | } |
9597 | ||
91d1b4bd DV |
9598 | void |
9599 | intel_modeset_check_state(struct drm_device *dev) | |
9600 | { | |
9601 | check_connector_state(dev); | |
9602 | check_encoder_state(dev); | |
9603 | check_crtc_state(dev); | |
9604 | check_shared_dpll_state(dev); | |
9605 | } | |
9606 | ||
18442d08 VS |
9607 | void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, |
9608 | int dotclock) | |
9609 | { | |
9610 | /* | |
9611 | * FDI already provided one idea for the dotclock. | |
9612 | * Yell if the encoder disagrees. | |
9613 | */ | |
241bfc38 | 9614 | WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock), |
18442d08 | 9615 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
241bfc38 | 9616 | pipe_config->adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
9617 | } |
9618 | ||
f30da187 DV |
9619 | static int __intel_set_mode(struct drm_crtc *crtc, |
9620 | struct drm_display_mode *mode, | |
9621 | int x, int y, struct drm_framebuffer *fb) | |
a6778b3c DV |
9622 | { |
9623 | struct drm_device *dev = crtc->dev; | |
dbf2b54e | 9624 | drm_i915_private_t *dev_priv = dev->dev_private; |
4b4b9238 | 9625 | struct drm_display_mode *saved_mode; |
b8cecdf5 | 9626 | struct intel_crtc_config *pipe_config = NULL; |
25c5b266 DV |
9627 | struct intel_crtc *intel_crtc; |
9628 | unsigned disable_pipes, prepare_pipes, modeset_pipes; | |
c0c36b94 | 9629 | int ret = 0; |
a6778b3c | 9630 | |
4b4b9238 | 9631 | saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL); |
c0c36b94 CW |
9632 | if (!saved_mode) |
9633 | return -ENOMEM; | |
a6778b3c | 9634 | |
e2e1ed41 | 9635 | intel_modeset_affected_pipes(crtc, &modeset_pipes, |
25c5b266 DV |
9636 | &prepare_pipes, &disable_pipes); |
9637 | ||
3ac18232 | 9638 | *saved_mode = crtc->mode; |
a6778b3c | 9639 | |
25c5b266 DV |
9640 | /* Hack: Because we don't (yet) support global modeset on multiple |
9641 | * crtcs, we don't keep track of the new mode for more than one crtc. | |
9642 | * Hence simply check whether any bit is set in modeset_pipes in all the | |
9643 | * pieces of code that are not yet converted to deal with mutliple crtcs | |
9644 | * changing their mode at the same time. */ | |
25c5b266 | 9645 | if (modeset_pipes) { |
4e53c2e0 | 9646 | pipe_config = intel_modeset_pipe_config(crtc, fb, mode); |
b8cecdf5 DV |
9647 | if (IS_ERR(pipe_config)) { |
9648 | ret = PTR_ERR(pipe_config); | |
9649 | pipe_config = NULL; | |
9650 | ||
3ac18232 | 9651 | goto out; |
25c5b266 | 9652 | } |
c0b03411 DV |
9653 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
9654 | "[modeset]"); | |
50741abc | 9655 | to_intel_crtc(crtc)->new_config = pipe_config; |
25c5b266 | 9656 | } |
a6778b3c | 9657 | |
30a970c6 JB |
9658 | /* |
9659 | * See if the config requires any additional preparation, e.g. | |
9660 | * to adjust global state with pipes off. We need to do this | |
9661 | * here so we can get the modeset_pipe updated config for the new | |
9662 | * mode set on this crtc. For other crtcs we need to use the | |
9663 | * adjusted_mode bits in the crtc directly. | |
9664 | */ | |
c164f833 | 9665 | if (IS_VALLEYVIEW(dev)) { |
2f2d7aa1 | 9666 | valleyview_modeset_global_pipes(dev, &prepare_pipes); |
30a970c6 | 9667 | |
c164f833 VS |
9668 | /* may have added more to prepare_pipes than we should */ |
9669 | prepare_pipes &= ~disable_pipes; | |
9670 | } | |
9671 | ||
460da916 DV |
9672 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
9673 | intel_crtc_disable(&intel_crtc->base); | |
9674 | ||
ea9d758d DV |
9675 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
9676 | if (intel_crtc->base.enabled) | |
9677 | dev_priv->display.crtc_disable(&intel_crtc->base); | |
9678 | } | |
a6778b3c | 9679 | |
6c4c86f5 DV |
9680 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
9681 | * to set it here already despite that we pass it down the callchain. | |
f6e5b160 | 9682 | */ |
b8cecdf5 | 9683 | if (modeset_pipes) { |
25c5b266 | 9684 | crtc->mode = *mode; |
b8cecdf5 DV |
9685 | /* mode_set/enable/disable functions rely on a correct pipe |
9686 | * config. */ | |
9687 | to_intel_crtc(crtc)->config = *pipe_config; | |
50741abc | 9688 | to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config; |
c326c0a9 VS |
9689 | |
9690 | /* | |
9691 | * Calculate and store various constants which | |
9692 | * are later needed by vblank and swap-completion | |
9693 | * timestamping. They are derived from true hwmode. | |
9694 | */ | |
9695 | drm_calc_timestamping_constants(crtc, | |
9696 | &pipe_config->adjusted_mode); | |
b8cecdf5 | 9697 | } |
7758a113 | 9698 | |
ea9d758d DV |
9699 | /* Only after disabling all output pipelines that will be changed can we |
9700 | * update the the output configuration. */ | |
9701 | intel_modeset_update_state(dev, prepare_pipes); | |
f6e5b160 | 9702 | |
47fab737 DV |
9703 | if (dev_priv->display.modeset_global_resources) |
9704 | dev_priv->display.modeset_global_resources(dev); | |
9705 | ||
a6778b3c DV |
9706 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
9707 | * on the DPLL. | |
f6e5b160 | 9708 | */ |
25c5b266 | 9709 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
c0c36b94 | 9710 | ret = intel_crtc_mode_set(&intel_crtc->base, |
c0c36b94 CW |
9711 | x, y, fb); |
9712 | if (ret) | |
9713 | goto done; | |
a6778b3c DV |
9714 | } |
9715 | ||
9716 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
25c5b266 DV |
9717 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) |
9718 | dev_priv->display.crtc_enable(&intel_crtc->base); | |
a6778b3c | 9719 | |
a6778b3c DV |
9720 | /* FIXME: add subpixel order */ |
9721 | done: | |
4b4b9238 | 9722 | if (ret && crtc->enabled) |
3ac18232 | 9723 | crtc->mode = *saved_mode; |
a6778b3c | 9724 | |
3ac18232 | 9725 | out: |
b8cecdf5 | 9726 | kfree(pipe_config); |
3ac18232 | 9727 | kfree(saved_mode); |
a6778b3c | 9728 | return ret; |
f6e5b160 CW |
9729 | } |
9730 | ||
e7457a9a DL |
9731 | static int intel_set_mode(struct drm_crtc *crtc, |
9732 | struct drm_display_mode *mode, | |
9733 | int x, int y, struct drm_framebuffer *fb) | |
f30da187 DV |
9734 | { |
9735 | int ret; | |
9736 | ||
9737 | ret = __intel_set_mode(crtc, mode, x, y, fb); | |
9738 | ||
9739 | if (ret == 0) | |
9740 | intel_modeset_check_state(crtc->dev); | |
9741 | ||
9742 | return ret; | |
9743 | } | |
9744 | ||
c0c36b94 CW |
9745 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
9746 | { | |
9747 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb); | |
9748 | } | |
9749 | ||
25c5b266 DV |
9750 | #undef for_each_intel_crtc_masked |
9751 | ||
d9e55608 DV |
9752 | static void intel_set_config_free(struct intel_set_config *config) |
9753 | { | |
9754 | if (!config) | |
9755 | return; | |
9756 | ||
1aa4b628 DV |
9757 | kfree(config->save_connector_encoders); |
9758 | kfree(config->save_encoder_crtcs); | |
7668851f | 9759 | kfree(config->save_crtc_enabled); |
d9e55608 DV |
9760 | kfree(config); |
9761 | } | |
9762 | ||
85f9eb71 DV |
9763 | static int intel_set_config_save_state(struct drm_device *dev, |
9764 | struct intel_set_config *config) | |
9765 | { | |
7668851f | 9766 | struct drm_crtc *crtc; |
85f9eb71 DV |
9767 | struct drm_encoder *encoder; |
9768 | struct drm_connector *connector; | |
9769 | int count; | |
9770 | ||
7668851f VS |
9771 | config->save_crtc_enabled = |
9772 | kcalloc(dev->mode_config.num_crtc, | |
9773 | sizeof(bool), GFP_KERNEL); | |
9774 | if (!config->save_crtc_enabled) | |
9775 | return -ENOMEM; | |
9776 | ||
1aa4b628 DV |
9777 | config->save_encoder_crtcs = |
9778 | kcalloc(dev->mode_config.num_encoder, | |
9779 | sizeof(struct drm_crtc *), GFP_KERNEL); | |
9780 | if (!config->save_encoder_crtcs) | |
85f9eb71 DV |
9781 | return -ENOMEM; |
9782 | ||
1aa4b628 DV |
9783 | config->save_connector_encoders = |
9784 | kcalloc(dev->mode_config.num_connector, | |
9785 | sizeof(struct drm_encoder *), GFP_KERNEL); | |
9786 | if (!config->save_connector_encoders) | |
85f9eb71 DV |
9787 | return -ENOMEM; |
9788 | ||
9789 | /* Copy data. Note that driver private data is not affected. | |
9790 | * Should anything bad happen only the expected state is | |
9791 | * restored, not the drivers personal bookkeeping. | |
9792 | */ | |
7668851f VS |
9793 | count = 0; |
9794 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
9795 | config->save_crtc_enabled[count++] = crtc->enabled; | |
9796 | } | |
9797 | ||
85f9eb71 DV |
9798 | count = 0; |
9799 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1aa4b628 | 9800 | config->save_encoder_crtcs[count++] = encoder->crtc; |
85f9eb71 DV |
9801 | } |
9802 | ||
9803 | count = 0; | |
9804 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1aa4b628 | 9805 | config->save_connector_encoders[count++] = connector->encoder; |
85f9eb71 DV |
9806 | } |
9807 | ||
9808 | return 0; | |
9809 | } | |
9810 | ||
9811 | static void intel_set_config_restore_state(struct drm_device *dev, | |
9812 | struct intel_set_config *config) | |
9813 | { | |
7668851f | 9814 | struct intel_crtc *crtc; |
9a935856 DV |
9815 | struct intel_encoder *encoder; |
9816 | struct intel_connector *connector; | |
85f9eb71 DV |
9817 | int count; |
9818 | ||
7668851f VS |
9819 | count = 0; |
9820 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
9821 | crtc->new_enabled = config->save_crtc_enabled[count++]; | |
7bd0a8e7 VS |
9822 | |
9823 | if (crtc->new_enabled) | |
9824 | crtc->new_config = &crtc->config; | |
9825 | else | |
9826 | crtc->new_config = NULL; | |
7668851f VS |
9827 | } |
9828 | ||
85f9eb71 | 9829 | count = 0; |
9a935856 DV |
9830 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
9831 | encoder->new_crtc = | |
9832 | to_intel_crtc(config->save_encoder_crtcs[count++]); | |
85f9eb71 DV |
9833 | } |
9834 | ||
9835 | count = 0; | |
9a935856 DV |
9836 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
9837 | connector->new_encoder = | |
9838 | to_intel_encoder(config->save_connector_encoders[count++]); | |
85f9eb71 DV |
9839 | } |
9840 | } | |
9841 | ||
e3de42b6 | 9842 | static bool |
2e57f47d | 9843 | is_crtc_connector_off(struct drm_mode_set *set) |
e3de42b6 ID |
9844 | { |
9845 | int i; | |
9846 | ||
2e57f47d CW |
9847 | if (set->num_connectors == 0) |
9848 | return false; | |
9849 | ||
9850 | if (WARN_ON(set->connectors == NULL)) | |
9851 | return false; | |
9852 | ||
9853 | for (i = 0; i < set->num_connectors; i++) | |
9854 | if (set->connectors[i]->encoder && | |
9855 | set->connectors[i]->encoder->crtc == set->crtc && | |
9856 | set->connectors[i]->dpms != DRM_MODE_DPMS_ON) | |
e3de42b6 ID |
9857 | return true; |
9858 | ||
9859 | return false; | |
9860 | } | |
9861 | ||
5e2b584e DV |
9862 | static void |
9863 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, | |
9864 | struct intel_set_config *config) | |
9865 | { | |
9866 | ||
9867 | /* We should be able to check here if the fb has the same properties | |
9868 | * and then just flip_or_move it */ | |
2e57f47d CW |
9869 | if (is_crtc_connector_off(set)) { |
9870 | config->mode_changed = true; | |
e3de42b6 | 9871 | } else if (set->crtc->fb != set->fb) { |
5e2b584e DV |
9872 | /* If we have no fb then treat it as a full mode set */ |
9873 | if (set->crtc->fb == NULL) { | |
319d9827 JB |
9874 | struct intel_crtc *intel_crtc = |
9875 | to_intel_crtc(set->crtc); | |
9876 | ||
d330a953 | 9877 | if (intel_crtc->active && i915.fastboot) { |
319d9827 JB |
9878 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); |
9879 | config->fb_changed = true; | |
9880 | } else { | |
9881 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); | |
9882 | config->mode_changed = true; | |
9883 | } | |
5e2b584e DV |
9884 | } else if (set->fb == NULL) { |
9885 | config->mode_changed = true; | |
72f4901e DV |
9886 | } else if (set->fb->pixel_format != |
9887 | set->crtc->fb->pixel_format) { | |
5e2b584e | 9888 | config->mode_changed = true; |
e3de42b6 | 9889 | } else { |
5e2b584e | 9890 | config->fb_changed = true; |
e3de42b6 | 9891 | } |
5e2b584e DV |
9892 | } |
9893 | ||
835c5873 | 9894 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
5e2b584e DV |
9895 | config->fb_changed = true; |
9896 | ||
9897 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { | |
9898 | DRM_DEBUG_KMS("modes are different, full mode set\n"); | |
9899 | drm_mode_debug_printmodeline(&set->crtc->mode); | |
9900 | drm_mode_debug_printmodeline(set->mode); | |
9901 | config->mode_changed = true; | |
9902 | } | |
a1d95703 CW |
9903 | |
9904 | DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", | |
9905 | set->crtc->base.id, config->mode_changed, config->fb_changed); | |
5e2b584e DV |
9906 | } |
9907 | ||
2e431051 | 9908 | static int |
9a935856 DV |
9909 | intel_modeset_stage_output_state(struct drm_device *dev, |
9910 | struct drm_mode_set *set, | |
9911 | struct intel_set_config *config) | |
50f56119 | 9912 | { |
9a935856 DV |
9913 | struct intel_connector *connector; |
9914 | struct intel_encoder *encoder; | |
7668851f | 9915 | struct intel_crtc *crtc; |
f3f08572 | 9916 | int ro; |
50f56119 | 9917 | |
9abdda74 | 9918 | /* The upper layers ensure that we either disable a crtc or have a list |
9a935856 DV |
9919 | * of connectors. For paranoia, double-check this. */ |
9920 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
9921 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
9922 | ||
9a935856 DV |
9923 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9924 | base.head) { | |
9925 | /* Otherwise traverse passed in connector list and get encoders | |
9926 | * for them. */ | |
50f56119 | 9927 | for (ro = 0; ro < set->num_connectors; ro++) { |
9a935856 DV |
9928 | if (set->connectors[ro] == &connector->base) { |
9929 | connector->new_encoder = connector->encoder; | |
50f56119 DV |
9930 | break; |
9931 | } | |
9932 | } | |
9933 | ||
9a935856 DV |
9934 | /* If we disable the crtc, disable all its connectors. Also, if |
9935 | * the connector is on the changing crtc but not on the new | |
9936 | * connector list, disable it. */ | |
9937 | if ((!set->fb || ro == set->num_connectors) && | |
9938 | connector->base.encoder && | |
9939 | connector->base.encoder->crtc == set->crtc) { | |
9940 | connector->new_encoder = NULL; | |
9941 | ||
9942 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
9943 | connector->base.base.id, | |
9944 | drm_get_connector_name(&connector->base)); | |
9945 | } | |
9946 | ||
9947 | ||
9948 | if (&connector->new_encoder->base != connector->base.encoder) { | |
50f56119 | 9949 | DRM_DEBUG_KMS("encoder changed, full mode switch\n"); |
5e2b584e | 9950 | config->mode_changed = true; |
50f56119 DV |
9951 | } |
9952 | } | |
9a935856 | 9953 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 9954 | |
9a935856 | 9955 | /* Update crtc of enabled connectors. */ |
9a935856 DV |
9956 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9957 | base.head) { | |
7668851f VS |
9958 | struct drm_crtc *new_crtc; |
9959 | ||
9a935856 | 9960 | if (!connector->new_encoder) |
50f56119 DV |
9961 | continue; |
9962 | ||
9a935856 | 9963 | new_crtc = connector->new_encoder->base.crtc; |
50f56119 DV |
9964 | |
9965 | for (ro = 0; ro < set->num_connectors; ro++) { | |
9a935856 | 9966 | if (set->connectors[ro] == &connector->base) |
50f56119 DV |
9967 | new_crtc = set->crtc; |
9968 | } | |
9969 | ||
9970 | /* Make sure the new CRTC will work with the encoder */ | |
14509916 TR |
9971 | if (!drm_encoder_crtc_ok(&connector->new_encoder->base, |
9972 | new_crtc)) { | |
5e2b584e | 9973 | return -EINVAL; |
50f56119 | 9974 | } |
9a935856 DV |
9975 | connector->encoder->new_crtc = to_intel_crtc(new_crtc); |
9976 | ||
9977 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", | |
9978 | connector->base.base.id, | |
9979 | drm_get_connector_name(&connector->base), | |
9980 | new_crtc->base.id); | |
9981 | } | |
9982 | ||
9983 | /* Check for any encoders that needs to be disabled. */ | |
9984 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
9985 | base.head) { | |
5a65f358 | 9986 | int num_connectors = 0; |
9a935856 DV |
9987 | list_for_each_entry(connector, |
9988 | &dev->mode_config.connector_list, | |
9989 | base.head) { | |
9990 | if (connector->new_encoder == encoder) { | |
9991 | WARN_ON(!connector->new_encoder->new_crtc); | |
5a65f358 | 9992 | num_connectors++; |
9a935856 DV |
9993 | } |
9994 | } | |
5a65f358 PZ |
9995 | |
9996 | if (num_connectors == 0) | |
9997 | encoder->new_crtc = NULL; | |
9998 | else if (num_connectors > 1) | |
9999 | return -EINVAL; | |
10000 | ||
9a935856 DV |
10001 | /* Only now check for crtc changes so we don't miss encoders |
10002 | * that will be disabled. */ | |
10003 | if (&encoder->new_crtc->base != encoder->base.crtc) { | |
50f56119 | 10004 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
5e2b584e | 10005 | config->mode_changed = true; |
50f56119 DV |
10006 | } |
10007 | } | |
9a935856 | 10008 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
50f56119 | 10009 | |
7668851f VS |
10010 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
10011 | base.head) { | |
10012 | crtc->new_enabled = false; | |
10013 | ||
10014 | list_for_each_entry(encoder, | |
10015 | &dev->mode_config.encoder_list, | |
10016 | base.head) { | |
10017 | if (encoder->new_crtc == crtc) { | |
10018 | crtc->new_enabled = true; | |
10019 | break; | |
10020 | } | |
10021 | } | |
10022 | ||
10023 | if (crtc->new_enabled != crtc->base.enabled) { | |
10024 | DRM_DEBUG_KMS("crtc %sabled, full mode switch\n", | |
10025 | crtc->new_enabled ? "en" : "dis"); | |
10026 | config->mode_changed = true; | |
10027 | } | |
7bd0a8e7 VS |
10028 | |
10029 | if (crtc->new_enabled) | |
10030 | crtc->new_config = &crtc->config; | |
10031 | else | |
10032 | crtc->new_config = NULL; | |
7668851f VS |
10033 | } |
10034 | ||
2e431051 DV |
10035 | return 0; |
10036 | } | |
10037 | ||
7d00a1f5 VS |
10038 | static void disable_crtc_nofb(struct intel_crtc *crtc) |
10039 | { | |
10040 | struct drm_device *dev = crtc->base.dev; | |
10041 | struct intel_encoder *encoder; | |
10042 | struct intel_connector *connector; | |
10043 | ||
10044 | DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n", | |
10045 | pipe_name(crtc->pipe)); | |
10046 | ||
10047 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { | |
10048 | if (connector->new_encoder && | |
10049 | connector->new_encoder->new_crtc == crtc) | |
10050 | connector->new_encoder = NULL; | |
10051 | } | |
10052 | ||
10053 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { | |
10054 | if (encoder->new_crtc == crtc) | |
10055 | encoder->new_crtc = NULL; | |
10056 | } | |
10057 | ||
10058 | crtc->new_enabled = false; | |
7bd0a8e7 | 10059 | crtc->new_config = NULL; |
7d00a1f5 VS |
10060 | } |
10061 | ||
2e431051 DV |
10062 | static int intel_crtc_set_config(struct drm_mode_set *set) |
10063 | { | |
10064 | struct drm_device *dev; | |
2e431051 DV |
10065 | struct drm_mode_set save_set; |
10066 | struct intel_set_config *config; | |
10067 | int ret; | |
2e431051 | 10068 | |
8d3e375e DV |
10069 | BUG_ON(!set); |
10070 | BUG_ON(!set->crtc); | |
10071 | BUG_ON(!set->crtc->helper_private); | |
2e431051 | 10072 | |
7e53f3a4 DV |
10073 | /* Enforce sane interface api - has been abused by the fb helper. */ |
10074 | BUG_ON(!set->mode && set->fb); | |
10075 | BUG_ON(set->fb && set->num_connectors == 0); | |
431e50f7 | 10076 | |
2e431051 DV |
10077 | if (set->fb) { |
10078 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
10079 | set->crtc->base.id, set->fb->base.id, | |
10080 | (int)set->num_connectors, set->x, set->y); | |
10081 | } else { | |
10082 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
10083 | } |
10084 | ||
10085 | dev = set->crtc->dev; | |
10086 | ||
10087 | ret = -ENOMEM; | |
10088 | config = kzalloc(sizeof(*config), GFP_KERNEL); | |
10089 | if (!config) | |
10090 | goto out_config; | |
10091 | ||
10092 | ret = intel_set_config_save_state(dev, config); | |
10093 | if (ret) | |
10094 | goto out_config; | |
10095 | ||
10096 | save_set.crtc = set->crtc; | |
10097 | save_set.mode = &set->crtc->mode; | |
10098 | save_set.x = set->crtc->x; | |
10099 | save_set.y = set->crtc->y; | |
10100 | save_set.fb = set->crtc->fb; | |
10101 | ||
10102 | /* Compute whether we need a full modeset, only an fb base update or no | |
10103 | * change at all. In the future we might also check whether only the | |
10104 | * mode changed, e.g. for LVDS where we only change the panel fitter in | |
10105 | * such cases. */ | |
10106 | intel_set_config_compute_mode_changes(set, config); | |
10107 | ||
9a935856 | 10108 | ret = intel_modeset_stage_output_state(dev, set, config); |
2e431051 DV |
10109 | if (ret) |
10110 | goto fail; | |
10111 | ||
5e2b584e | 10112 | if (config->mode_changed) { |
c0c36b94 CW |
10113 | ret = intel_set_mode(set->crtc, set->mode, |
10114 | set->x, set->y, set->fb); | |
5e2b584e | 10115 | } else if (config->fb_changed) { |
4878cae2 VS |
10116 | intel_crtc_wait_for_pending_flips(set->crtc); |
10117 | ||
4f660f49 | 10118 | ret = intel_pipe_set_base(set->crtc, |
94352cf9 | 10119 | set->x, set->y, set->fb); |
7ca51a3a JB |
10120 | /* |
10121 | * In the fastboot case this may be our only check of the | |
10122 | * state after boot. It would be better to only do it on | |
10123 | * the first update, but we don't have a nice way of doing that | |
10124 | * (and really, set_config isn't used much for high freq page | |
10125 | * flipping, so increasing its cost here shouldn't be a big | |
10126 | * deal). | |
10127 | */ | |
d330a953 | 10128 | if (i915.fastboot && ret == 0) |
7ca51a3a | 10129 | intel_modeset_check_state(set->crtc->dev); |
50f56119 DV |
10130 | } |
10131 | ||
2d05eae1 | 10132 | if (ret) { |
bf67dfeb DV |
10133 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
10134 | set->crtc->base.id, ret); | |
50f56119 | 10135 | fail: |
2d05eae1 | 10136 | intel_set_config_restore_state(dev, config); |
50f56119 | 10137 | |
7d00a1f5 VS |
10138 | /* |
10139 | * HACK: if the pipe was on, but we didn't have a framebuffer, | |
10140 | * force the pipe off to avoid oopsing in the modeset code | |
10141 | * due to fb==NULL. This should only happen during boot since | |
10142 | * we don't yet reconstruct the FB from the hardware state. | |
10143 | */ | |
10144 | if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb) | |
10145 | disable_crtc_nofb(to_intel_crtc(save_set.crtc)); | |
10146 | ||
2d05eae1 CW |
10147 | /* Try to restore the config */ |
10148 | if (config->mode_changed && | |
10149 | intel_set_mode(save_set.crtc, save_set.mode, | |
10150 | save_set.x, save_set.y, save_set.fb)) | |
10151 | DRM_ERROR("failed to restore config after modeset failure\n"); | |
10152 | } | |
50f56119 | 10153 | |
d9e55608 DV |
10154 | out_config: |
10155 | intel_set_config_free(config); | |
50f56119 DV |
10156 | return ret; |
10157 | } | |
f6e5b160 CW |
10158 | |
10159 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 CW |
10160 | .cursor_set = intel_crtc_cursor_set, |
10161 | .cursor_move = intel_crtc_cursor_move, | |
10162 | .gamma_set = intel_crtc_gamma_set, | |
50f56119 | 10163 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
10164 | .destroy = intel_crtc_destroy, |
10165 | .page_flip = intel_crtc_page_flip, | |
10166 | }; | |
10167 | ||
79f689aa PZ |
10168 | static void intel_cpu_pll_init(struct drm_device *dev) |
10169 | { | |
affa9354 | 10170 | if (HAS_DDI(dev)) |
79f689aa PZ |
10171 | intel_ddi_pll_init(dev); |
10172 | } | |
10173 | ||
5358901f DV |
10174 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
10175 | struct intel_shared_dpll *pll, | |
10176 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 10177 | { |
5358901f | 10178 | uint32_t val; |
ee7b9f93 | 10179 | |
5358901f | 10180 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
10181 | hw_state->dpll = val; |
10182 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
10183 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
10184 | |
10185 | return val & DPLL_VCO_ENABLE; | |
10186 | } | |
10187 | ||
15bdd4cf DV |
10188 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
10189 | struct intel_shared_dpll *pll) | |
10190 | { | |
10191 | I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0); | |
10192 | I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1); | |
10193 | } | |
10194 | ||
e7b903d2 DV |
10195 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
10196 | struct intel_shared_dpll *pll) | |
10197 | { | |
e7b903d2 | 10198 | /* PCH refclock must be enabled first */ |
89eff4be | 10199 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 10200 | |
15bdd4cf DV |
10201 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); |
10202 | ||
10203 | /* Wait for the clocks to stabilize. */ | |
10204 | POSTING_READ(PCH_DPLL(pll->id)); | |
10205 | udelay(150); | |
10206 | ||
10207 | /* The pixel multiplier can only be updated once the | |
10208 | * DPLL is enabled and the clocks are stable. | |
10209 | * | |
10210 | * So write it again. | |
10211 | */ | |
10212 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); | |
10213 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
10214 | udelay(200); |
10215 | } | |
10216 | ||
10217 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
10218 | struct intel_shared_dpll *pll) | |
10219 | { | |
10220 | struct drm_device *dev = dev_priv->dev; | |
10221 | struct intel_crtc *crtc; | |
e7b903d2 DV |
10222 | |
10223 | /* Make sure no transcoder isn't still depending on us. */ | |
10224 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
10225 | if (intel_crtc_to_shared_dpll(crtc) == pll) | |
10226 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
10227 | } |
10228 | ||
15bdd4cf DV |
10229 | I915_WRITE(PCH_DPLL(pll->id), 0); |
10230 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
10231 | udelay(200); |
10232 | } | |
10233 | ||
46edb027 DV |
10234 | static char *ibx_pch_dpll_names[] = { |
10235 | "PCH DPLL A", | |
10236 | "PCH DPLL B", | |
10237 | }; | |
10238 | ||
7c74ade1 | 10239 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 10240 | { |
e7b903d2 | 10241 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
10242 | int i; |
10243 | ||
7c74ade1 | 10244 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 10245 | |
e72f9fbf | 10246 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
10247 | dev_priv->shared_dplls[i].id = i; |
10248 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 10249 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
10250 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
10251 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
10252 | dev_priv->shared_dplls[i].get_hw_state = |
10253 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
10254 | } |
10255 | } | |
10256 | ||
7c74ade1 DV |
10257 | static void intel_shared_dpll_init(struct drm_device *dev) |
10258 | { | |
e7b903d2 | 10259 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 DV |
10260 | |
10261 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
10262 | ibx_pch_dpll_init(dev); | |
10263 | else | |
10264 | dev_priv->num_shared_dpll = 0; | |
10265 | ||
10266 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
10267 | } |
10268 | ||
b358d0a6 | 10269 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 10270 | { |
22fd0fab | 10271 | drm_i915_private_t *dev_priv = dev->dev_private; |
79e53945 JB |
10272 | struct intel_crtc *intel_crtc; |
10273 | int i; | |
10274 | ||
955382f3 | 10275 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
10276 | if (intel_crtc == NULL) |
10277 | return; | |
10278 | ||
10279 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); | |
10280 | ||
10281 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
10282 | for (i = 0; i < 256; i++) { |
10283 | intel_crtc->lut_r[i] = i; | |
10284 | intel_crtc->lut_g[i] = i; | |
10285 | intel_crtc->lut_b[i] = i; | |
10286 | } | |
10287 | ||
1f1c2e24 VS |
10288 | /* |
10289 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
10290 | * is hooked to plane B. Hence we want plane A feeding pipe B. | |
10291 | */ | |
80824003 JB |
10292 | intel_crtc->pipe = pipe; |
10293 | intel_crtc->plane = pipe; | |
3a77c4c4 | 10294 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 10295 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 10296 | intel_crtc->plane = !pipe; |
80824003 JB |
10297 | } |
10298 | ||
22fd0fab JB |
10299 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
10300 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
10301 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
10302 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
10303 | ||
79e53945 | 10304 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
79e53945 JB |
10305 | } |
10306 | ||
752aa88a JB |
10307 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
10308 | { | |
10309 | struct drm_encoder *encoder = connector->base.encoder; | |
10310 | ||
10311 | WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex)); | |
10312 | ||
10313 | if (!encoder) | |
10314 | return INVALID_PIPE; | |
10315 | ||
10316 | return to_intel_crtc(encoder->crtc)->pipe; | |
10317 | } | |
10318 | ||
08d7b3d1 | 10319 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 10320 | struct drm_file *file) |
08d7b3d1 | 10321 | { |
08d7b3d1 | 10322 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
c05422d5 DV |
10323 | struct drm_mode_object *drmmode_obj; |
10324 | struct intel_crtc *crtc; | |
08d7b3d1 | 10325 | |
1cff8f6b DV |
10326 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
10327 | return -ENODEV; | |
08d7b3d1 | 10328 | |
c05422d5 DV |
10329 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
10330 | DRM_MODE_OBJECT_CRTC); | |
08d7b3d1 | 10331 | |
c05422d5 | 10332 | if (!drmmode_obj) { |
08d7b3d1 | 10333 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 10334 | return -ENOENT; |
08d7b3d1 CW |
10335 | } |
10336 | ||
c05422d5 DV |
10337 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
10338 | pipe_from_crtc_id->pipe = crtc->pipe; | |
08d7b3d1 | 10339 | |
c05422d5 | 10340 | return 0; |
08d7b3d1 CW |
10341 | } |
10342 | ||
66a9278e | 10343 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 10344 | { |
66a9278e DV |
10345 | struct drm_device *dev = encoder->base.dev; |
10346 | struct intel_encoder *source_encoder; | |
79e53945 | 10347 | int index_mask = 0; |
79e53945 JB |
10348 | int entry = 0; |
10349 | ||
66a9278e DV |
10350 | list_for_each_entry(source_encoder, |
10351 | &dev->mode_config.encoder_list, base.head) { | |
10352 | ||
10353 | if (encoder == source_encoder) | |
79e53945 | 10354 | index_mask |= (1 << entry); |
66a9278e DV |
10355 | |
10356 | /* Intel hw has only one MUX where enocoders could be cloned. */ | |
10357 | if (encoder->cloneable && source_encoder->cloneable) | |
10358 | index_mask |= (1 << entry); | |
10359 | ||
79e53945 JB |
10360 | entry++; |
10361 | } | |
4ef69c7a | 10362 | |
79e53945 JB |
10363 | return index_mask; |
10364 | } | |
10365 | ||
4d302442 CW |
10366 | static bool has_edp_a(struct drm_device *dev) |
10367 | { | |
10368 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10369 | ||
10370 | if (!IS_MOBILE(dev)) | |
10371 | return false; | |
10372 | ||
10373 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
10374 | return false; | |
10375 | ||
e3589908 | 10376 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
10377 | return false; |
10378 | ||
10379 | return true; | |
10380 | } | |
10381 | ||
ba0fbca4 DL |
10382 | const char *intel_output_name(int output) |
10383 | { | |
10384 | static const char *names[] = { | |
10385 | [INTEL_OUTPUT_UNUSED] = "Unused", | |
10386 | [INTEL_OUTPUT_ANALOG] = "Analog", | |
10387 | [INTEL_OUTPUT_DVO] = "DVO", | |
10388 | [INTEL_OUTPUT_SDVO] = "SDVO", | |
10389 | [INTEL_OUTPUT_LVDS] = "LVDS", | |
10390 | [INTEL_OUTPUT_TVOUT] = "TV", | |
10391 | [INTEL_OUTPUT_HDMI] = "HDMI", | |
10392 | [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort", | |
10393 | [INTEL_OUTPUT_EDP] = "eDP", | |
10394 | [INTEL_OUTPUT_DSI] = "DSI", | |
10395 | [INTEL_OUTPUT_UNKNOWN] = "Unknown", | |
10396 | }; | |
10397 | ||
10398 | if (output < 0 || output >= ARRAY_SIZE(names) || !names[output]) | |
10399 | return "Invalid"; | |
10400 | ||
10401 | return names[output]; | |
10402 | } | |
10403 | ||
79e53945 JB |
10404 | static void intel_setup_outputs(struct drm_device *dev) |
10405 | { | |
725e30ad | 10406 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 10407 | struct intel_encoder *encoder; |
cb0953d7 | 10408 | bool dpd_is_edp = false; |
79e53945 | 10409 | |
c9093354 | 10410 | intel_lvds_init(dev); |
79e53945 | 10411 | |
c40c0f5b | 10412 | if (!IS_ULT(dev)) |
79935fca | 10413 | intel_crt_init(dev); |
cb0953d7 | 10414 | |
affa9354 | 10415 | if (HAS_DDI(dev)) { |
0e72a5b5 ED |
10416 | int found; |
10417 | ||
10418 | /* Haswell uses DDI functions to detect digital outputs */ | |
10419 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; | |
10420 | /* DDI A only supports eDP */ | |
10421 | if (found) | |
10422 | intel_ddi_init(dev, PORT_A); | |
10423 | ||
10424 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
10425 | * register */ | |
10426 | found = I915_READ(SFUSE_STRAP); | |
10427 | ||
10428 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
10429 | intel_ddi_init(dev, PORT_B); | |
10430 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
10431 | intel_ddi_init(dev, PORT_C); | |
10432 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
10433 | intel_ddi_init(dev, PORT_D); | |
10434 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 10435 | int found; |
5d8a7752 | 10436 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
10437 | |
10438 | if (has_edp_a(dev)) | |
10439 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 10440 | |
dc0fa718 | 10441 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 10442 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 10443 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 10444 | if (!found) |
e2debe91 | 10445 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 10446 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 10447 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
10448 | } |
10449 | ||
dc0fa718 | 10450 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 10451 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 10452 | |
dc0fa718 | 10453 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 10454 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 10455 | |
5eb08b69 | 10456 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 10457 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 10458 | |
270b3042 | 10459 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 10460 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 10461 | } else if (IS_VALLEYVIEW(dev)) { |
585a94b8 AB |
10462 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) { |
10463 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, | |
10464 | PORT_B); | |
10465 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED) | |
10466 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
10467 | } | |
10468 | ||
6f6005a5 JB |
10469 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) { |
10470 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, | |
10471 | PORT_C); | |
10472 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) | |
5d8a7752 | 10473 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); |
6f6005a5 | 10474 | } |
19c03924 | 10475 | |
3cfca973 | 10476 | intel_dsi_init(dev); |
103a196f | 10477 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 10478 | bool found = false; |
7d57382e | 10479 | |
e2debe91 | 10480 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 10481 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 10482 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
b01f2c3a JB |
10483 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
10484 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
e2debe91 | 10485 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 10486 | } |
27185ae1 | 10487 | |
e7281eab | 10488 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 10489 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 10490 | } |
13520b05 KH |
10491 | |
10492 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 10493 | |
e2debe91 | 10494 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 10495 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 10496 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 10497 | } |
27185ae1 | 10498 | |
e2debe91 | 10499 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 10500 | |
b01f2c3a JB |
10501 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
10502 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
e2debe91 | 10503 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 10504 | } |
e7281eab | 10505 | if (SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 10506 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 10507 | } |
27185ae1 | 10508 | |
b01f2c3a | 10509 | if (SUPPORTS_INTEGRATED_DP(dev) && |
e7281eab | 10510 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 10511 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 10512 | } else if (IS_GEN2(dev)) |
79e53945 JB |
10513 | intel_dvo_init(dev); |
10514 | ||
103a196f | 10515 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
10516 | intel_tv_init(dev); |
10517 | ||
4ef69c7a CW |
10518 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
10519 | encoder->base.possible_crtcs = encoder->crtc_mask; | |
10520 | encoder->base.possible_clones = | |
66a9278e | 10521 | intel_encoder_clones(encoder); |
79e53945 | 10522 | } |
47356eb6 | 10523 | |
dde86e2d | 10524 | intel_init_pch_refclk(dev); |
270b3042 DV |
10525 | |
10526 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
10527 | } |
10528 | ||
ddfe1567 CW |
10529 | void intel_framebuffer_fini(struct intel_framebuffer *fb) |
10530 | { | |
10531 | drm_framebuffer_cleanup(&fb->base); | |
80075d49 | 10532 | WARN_ON(!fb->obj->framebuffer_references--); |
ddfe1567 CW |
10533 | drm_gem_object_unreference_unlocked(&fb->obj->base); |
10534 | } | |
10535 | ||
79e53945 JB |
10536 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) |
10537 | { | |
10538 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 | 10539 | |
ddfe1567 | 10540 | intel_framebuffer_fini(intel_fb); |
79e53945 JB |
10541 | kfree(intel_fb); |
10542 | } | |
10543 | ||
10544 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 10545 | struct drm_file *file, |
79e53945 JB |
10546 | unsigned int *handle) |
10547 | { | |
10548 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 10549 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 10550 | |
05394f39 | 10551 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
10552 | } |
10553 | ||
10554 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
10555 | .destroy = intel_user_framebuffer_destroy, | |
10556 | .create_handle = intel_user_framebuffer_create_handle, | |
10557 | }; | |
10558 | ||
38651674 DA |
10559 | int intel_framebuffer_init(struct drm_device *dev, |
10560 | struct intel_framebuffer *intel_fb, | |
308e5bcb | 10561 | struct drm_mode_fb_cmd2 *mode_cmd, |
05394f39 | 10562 | struct drm_i915_gem_object *obj) |
79e53945 | 10563 | { |
53155c0a | 10564 | int aligned_height, tile_height; |
a35cdaa0 | 10565 | int pitch_limit; |
79e53945 JB |
10566 | int ret; |
10567 | ||
dd4916c5 DV |
10568 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
10569 | ||
c16ed4be CW |
10570 | if (obj->tiling_mode == I915_TILING_Y) { |
10571 | DRM_DEBUG("hardware does not support tiling Y\n"); | |
57cd6508 | 10572 | return -EINVAL; |
c16ed4be | 10573 | } |
57cd6508 | 10574 | |
c16ed4be CW |
10575 | if (mode_cmd->pitches[0] & 63) { |
10576 | DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n", | |
10577 | mode_cmd->pitches[0]); | |
57cd6508 | 10578 | return -EINVAL; |
c16ed4be | 10579 | } |
57cd6508 | 10580 | |
a35cdaa0 CW |
10581 | if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) { |
10582 | pitch_limit = 32*1024; | |
10583 | } else if (INTEL_INFO(dev)->gen >= 4) { | |
10584 | if (obj->tiling_mode) | |
10585 | pitch_limit = 16*1024; | |
10586 | else | |
10587 | pitch_limit = 32*1024; | |
10588 | } else if (INTEL_INFO(dev)->gen >= 3) { | |
10589 | if (obj->tiling_mode) | |
10590 | pitch_limit = 8*1024; | |
10591 | else | |
10592 | pitch_limit = 16*1024; | |
10593 | } else | |
10594 | /* XXX DSPC is limited to 4k tiled */ | |
10595 | pitch_limit = 8*1024; | |
10596 | ||
10597 | if (mode_cmd->pitches[0] > pitch_limit) { | |
10598 | DRM_DEBUG("%s pitch (%d) must be at less than %d\n", | |
10599 | obj->tiling_mode ? "tiled" : "linear", | |
10600 | mode_cmd->pitches[0], pitch_limit); | |
5d7bd705 | 10601 | return -EINVAL; |
c16ed4be | 10602 | } |
5d7bd705 VS |
10603 | |
10604 | if (obj->tiling_mode != I915_TILING_NONE && | |
c16ed4be CW |
10605 | mode_cmd->pitches[0] != obj->stride) { |
10606 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
10607 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 10608 | return -EINVAL; |
c16ed4be | 10609 | } |
5d7bd705 | 10610 | |
57779d06 | 10611 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 10612 | switch (mode_cmd->pixel_format) { |
57779d06 | 10613 | case DRM_FORMAT_C8: |
04b3924d VS |
10614 | case DRM_FORMAT_RGB565: |
10615 | case DRM_FORMAT_XRGB8888: | |
10616 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
10617 | break; |
10618 | case DRM_FORMAT_XRGB1555: | |
10619 | case DRM_FORMAT_ARGB1555: | |
c16ed4be | 10620 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
10621 | DRM_DEBUG("unsupported pixel format: %s\n", |
10622 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 10623 | return -EINVAL; |
c16ed4be | 10624 | } |
57779d06 VS |
10625 | break; |
10626 | case DRM_FORMAT_XBGR8888: | |
10627 | case DRM_FORMAT_ABGR8888: | |
04b3924d VS |
10628 | case DRM_FORMAT_XRGB2101010: |
10629 | case DRM_FORMAT_ARGB2101010: | |
57779d06 VS |
10630 | case DRM_FORMAT_XBGR2101010: |
10631 | case DRM_FORMAT_ABGR2101010: | |
c16ed4be | 10632 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
10633 | DRM_DEBUG("unsupported pixel format: %s\n", |
10634 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 10635 | return -EINVAL; |
c16ed4be | 10636 | } |
b5626747 | 10637 | break; |
04b3924d VS |
10638 | case DRM_FORMAT_YUYV: |
10639 | case DRM_FORMAT_UYVY: | |
10640 | case DRM_FORMAT_YVYU: | |
10641 | case DRM_FORMAT_VYUY: | |
c16ed4be | 10642 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
10643 | DRM_DEBUG("unsupported pixel format: %s\n", |
10644 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 10645 | return -EINVAL; |
c16ed4be | 10646 | } |
57cd6508 CW |
10647 | break; |
10648 | default: | |
4ee62c76 VS |
10649 | DRM_DEBUG("unsupported pixel format: %s\n", |
10650 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
10651 | return -EINVAL; |
10652 | } | |
10653 | ||
90f9a336 VS |
10654 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
10655 | if (mode_cmd->offsets[0] != 0) | |
10656 | return -EINVAL; | |
10657 | ||
53155c0a DV |
10658 | tile_height = IS_GEN2(dev) ? 16 : 8; |
10659 | aligned_height = ALIGN(mode_cmd->height, | |
10660 | obj->tiling_mode ? tile_height : 1); | |
10661 | /* FIXME drm helper for size checks (especially planar formats)? */ | |
10662 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
10663 | return -EINVAL; | |
10664 | ||
c7d73f6a DV |
10665 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
10666 | intel_fb->obj = obj; | |
80075d49 | 10667 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 10668 | |
79e53945 JB |
10669 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
10670 | if (ret) { | |
10671 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
10672 | return ret; | |
10673 | } | |
10674 | ||
79e53945 JB |
10675 | return 0; |
10676 | } | |
10677 | ||
79e53945 JB |
10678 | static struct drm_framebuffer * |
10679 | intel_user_framebuffer_create(struct drm_device *dev, | |
10680 | struct drm_file *filp, | |
308e5bcb | 10681 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 10682 | { |
05394f39 | 10683 | struct drm_i915_gem_object *obj; |
79e53945 | 10684 | |
308e5bcb JB |
10685 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
10686 | mode_cmd->handles[0])); | |
c8725226 | 10687 | if (&obj->base == NULL) |
cce13ff7 | 10688 | return ERR_PTR(-ENOENT); |
79e53945 | 10689 | |
d2dff872 | 10690 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
10691 | } |
10692 | ||
4520f53a | 10693 | #ifndef CONFIG_DRM_I915_FBDEV |
0632fef6 | 10694 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
10695 | { |
10696 | } | |
10697 | #endif | |
10698 | ||
79e53945 | 10699 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 10700 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 10701 | .output_poll_changed = intel_fbdev_output_poll_changed, |
79e53945 JB |
10702 | }; |
10703 | ||
e70236a8 JB |
10704 | /* Set up chip specific display functions */ |
10705 | static void intel_init_display(struct drm_device *dev) | |
10706 | { | |
10707 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10708 | ||
ee9300bb DV |
10709 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
10710 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
10711 | else if (IS_VALLEYVIEW(dev)) | |
10712 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
10713 | else if (IS_PINEVIEW(dev)) | |
10714 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
10715 | else | |
10716 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
10717 | ||
affa9354 | 10718 | if (HAS_DDI(dev)) { |
0e8ffe1b | 10719 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
09b4ddf9 | 10720 | dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; |
4f771f10 PZ |
10721 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
10722 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
6441ab5f | 10723 | dev_priv->display.off = haswell_crtc_off; |
09b4ddf9 PZ |
10724 | dev_priv->display.update_plane = ironlake_update_plane; |
10725 | } else if (HAS_PCH_SPLIT(dev)) { | |
0e8ffe1b | 10726 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
f564048e | 10727 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
76e5a89c DV |
10728 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
10729 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
ee7b9f93 | 10730 | dev_priv->display.off = ironlake_crtc_off; |
17638cd6 | 10731 | dev_priv->display.update_plane = ironlake_update_plane; |
89b667f8 JB |
10732 | } else if (IS_VALLEYVIEW(dev)) { |
10733 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
10734 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; | |
10735 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
10736 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
10737 | dev_priv->display.off = i9xx_crtc_off; | |
10738 | dev_priv->display.update_plane = i9xx_update_plane; | |
f564048e | 10739 | } else { |
0e8ffe1b | 10740 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
f564048e | 10741 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
76e5a89c DV |
10742 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
10743 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
ee7b9f93 | 10744 | dev_priv->display.off = i9xx_crtc_off; |
17638cd6 | 10745 | dev_priv->display.update_plane = i9xx_update_plane; |
f564048e | 10746 | } |
e70236a8 | 10747 | |
e70236a8 | 10748 | /* Returns the core display clock speed */ |
25eb05fc JB |
10749 | if (IS_VALLEYVIEW(dev)) |
10750 | dev_priv->display.get_display_clock_speed = | |
10751 | valleyview_get_display_clock_speed; | |
10752 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
10753 | dev_priv->display.get_display_clock_speed = |
10754 | i945_get_display_clock_speed; | |
10755 | else if (IS_I915G(dev)) | |
10756 | dev_priv->display.get_display_clock_speed = | |
10757 | i915_get_display_clock_speed; | |
257a7ffc | 10758 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
10759 | dev_priv->display.get_display_clock_speed = |
10760 | i9xx_misc_get_display_clock_speed; | |
257a7ffc DV |
10761 | else if (IS_PINEVIEW(dev)) |
10762 | dev_priv->display.get_display_clock_speed = | |
10763 | pnv_get_display_clock_speed; | |
e70236a8 JB |
10764 | else if (IS_I915GM(dev)) |
10765 | dev_priv->display.get_display_clock_speed = | |
10766 | i915gm_get_display_clock_speed; | |
10767 | else if (IS_I865G(dev)) | |
10768 | dev_priv->display.get_display_clock_speed = | |
10769 | i865_get_display_clock_speed; | |
f0f8a9ce | 10770 | else if (IS_I85X(dev)) |
e70236a8 JB |
10771 | dev_priv->display.get_display_clock_speed = |
10772 | i855_get_display_clock_speed; | |
10773 | else /* 852, 830 */ | |
10774 | dev_priv->display.get_display_clock_speed = | |
10775 | i830_get_display_clock_speed; | |
10776 | ||
7f8a8569 | 10777 | if (HAS_PCH_SPLIT(dev)) { |
f00a3ddf | 10778 | if (IS_GEN5(dev)) { |
674cf967 | 10779 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
e0dac65e | 10780 | dev_priv->display.write_eld = ironlake_write_eld; |
1398261a | 10781 | } else if (IS_GEN6(dev)) { |
674cf967 | 10782 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
e0dac65e | 10783 | dev_priv->display.write_eld = ironlake_write_eld; |
357555c0 JB |
10784 | } else if (IS_IVYBRIDGE(dev)) { |
10785 | /* FIXME: detect B0+ stepping and use auto training */ | |
10786 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
e0dac65e | 10787 | dev_priv->display.write_eld = ironlake_write_eld; |
01a415fd DV |
10788 | dev_priv->display.modeset_global_resources = |
10789 | ivb_modeset_global_resources; | |
4e0bbc31 | 10790 | } else if (IS_HASWELL(dev) || IS_GEN8(dev)) { |
c82e4d26 | 10791 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
83358c85 | 10792 | dev_priv->display.write_eld = haswell_write_eld; |
d6dd9eb1 DV |
10793 | dev_priv->display.modeset_global_resources = |
10794 | haswell_modeset_global_resources; | |
a0e63c22 | 10795 | } |
6067aaea | 10796 | } else if (IS_G4X(dev)) { |
e0dac65e | 10797 | dev_priv->display.write_eld = g4x_write_eld; |
30a970c6 JB |
10798 | } else if (IS_VALLEYVIEW(dev)) { |
10799 | dev_priv->display.modeset_global_resources = | |
10800 | valleyview_modeset_global_resources; | |
9ca2fe73 | 10801 | dev_priv->display.write_eld = ironlake_write_eld; |
e70236a8 | 10802 | } |
8c9f3aaf JB |
10803 | |
10804 | /* Default just returns -ENODEV to indicate unsupported */ | |
10805 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
10806 | ||
10807 | switch (INTEL_INFO(dev)->gen) { | |
10808 | case 2: | |
10809 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
10810 | break; | |
10811 | ||
10812 | case 3: | |
10813 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
10814 | break; | |
10815 | ||
10816 | case 4: | |
10817 | case 5: | |
10818 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
10819 | break; | |
10820 | ||
10821 | case 6: | |
10822 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
10823 | break; | |
7c9017e5 | 10824 | case 7: |
4e0bbc31 | 10825 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
10826 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
10827 | break; | |
8c9f3aaf | 10828 | } |
7bd688cd JN |
10829 | |
10830 | intel_panel_init_backlight_funcs(dev); | |
e70236a8 JB |
10831 | } |
10832 | ||
b690e96c JB |
10833 | /* |
10834 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
10835 | * resume, or other times. This quirk makes sure that's the case for | |
10836 | * affected systems. | |
10837 | */ | |
0206e353 | 10838 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
10839 | { |
10840 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10841 | ||
10842 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 10843 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
10844 | } |
10845 | ||
435793df KP |
10846 | /* |
10847 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
10848 | */ | |
10849 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
10850 | { | |
10851 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10852 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 10853 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
10854 | } |
10855 | ||
4dca20ef | 10856 | /* |
5a15ab5b CE |
10857 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
10858 | * brightness value | |
4dca20ef CE |
10859 | */ |
10860 | static void quirk_invert_brightness(struct drm_device *dev) | |
10861 | { | |
10862 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10863 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 10864 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
10865 | } |
10866 | ||
b690e96c JB |
10867 | struct intel_quirk { |
10868 | int device; | |
10869 | int subsystem_vendor; | |
10870 | int subsystem_device; | |
10871 | void (*hook)(struct drm_device *dev); | |
10872 | }; | |
10873 | ||
5f85f176 EE |
10874 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
10875 | struct intel_dmi_quirk { | |
10876 | void (*hook)(struct drm_device *dev); | |
10877 | const struct dmi_system_id (*dmi_id_list)[]; | |
10878 | }; | |
10879 | ||
10880 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
10881 | { | |
10882 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
10883 | return 1; | |
10884 | } | |
10885 | ||
10886 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
10887 | { | |
10888 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
10889 | { | |
10890 | .callback = intel_dmi_reverse_brightness, | |
10891 | .ident = "NCR Corporation", | |
10892 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
10893 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
10894 | }, | |
10895 | }, | |
10896 | { } /* terminating entry */ | |
10897 | }, | |
10898 | .hook = quirk_invert_brightness, | |
10899 | }, | |
10900 | }; | |
10901 | ||
c43b5634 | 10902 | static struct intel_quirk intel_quirks[] = { |
b690e96c | 10903 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 10904 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c | 10905 | |
b690e96c JB |
10906 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
10907 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
10908 | ||
b690e96c JB |
10909 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
10910 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
10911 | ||
a4945f95 | 10912 | /* 830 needs to leave pipe A & dpll A up */ |
dcdaed6e | 10913 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
435793df KP |
10914 | |
10915 | /* Lenovo U160 cannot use SSC on LVDS */ | |
10916 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
10917 | |
10918 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
10919 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 10920 | |
be505f64 AH |
10921 | /* Acer Aspire 5734Z must invert backlight brightness */ |
10922 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
10923 | ||
10924 | /* Acer/eMachines G725 */ | |
10925 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
10926 | ||
10927 | /* Acer/eMachines e725 */ | |
10928 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
10929 | ||
10930 | /* Acer/Packard Bell NCL20 */ | |
10931 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
10932 | ||
10933 | /* Acer Aspire 4736Z */ | |
10934 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
10935 | |
10936 | /* Acer Aspire 5336 */ | |
10937 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
b690e96c JB |
10938 | }; |
10939 | ||
10940 | static void intel_init_quirks(struct drm_device *dev) | |
10941 | { | |
10942 | struct pci_dev *d = dev->pdev; | |
10943 | int i; | |
10944 | ||
10945 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
10946 | struct intel_quirk *q = &intel_quirks[i]; | |
10947 | ||
10948 | if (d->device == q->device && | |
10949 | (d->subsystem_vendor == q->subsystem_vendor || | |
10950 | q->subsystem_vendor == PCI_ANY_ID) && | |
10951 | (d->subsystem_device == q->subsystem_device || | |
10952 | q->subsystem_device == PCI_ANY_ID)) | |
10953 | q->hook(dev); | |
10954 | } | |
5f85f176 EE |
10955 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
10956 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
10957 | intel_dmi_quirks[i].hook(dev); | |
10958 | } | |
b690e96c JB |
10959 | } |
10960 | ||
9cce37f4 JB |
10961 | /* Disable the VGA plane that we never use */ |
10962 | static void i915_disable_vga(struct drm_device *dev) | |
10963 | { | |
10964 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10965 | u8 sr1; | |
766aa1c4 | 10966 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 10967 | |
2b37c616 | 10968 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 10969 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 10970 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
10971 | sr1 = inb(VGA_SR_DATA); |
10972 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
10973 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
10974 | udelay(300); | |
10975 | ||
10976 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); | |
10977 | POSTING_READ(vga_reg); | |
10978 | } | |
10979 | ||
f817586c DV |
10980 | void intel_modeset_init_hw(struct drm_device *dev) |
10981 | { | |
a8f78b58 ED |
10982 | intel_prepare_ddi(dev); |
10983 | ||
f817586c DV |
10984 | intel_init_clock_gating(dev); |
10985 | ||
5382f5f3 | 10986 | intel_reset_dpio(dev); |
40e9cf64 | 10987 | |
79f5b2c7 | 10988 | mutex_lock(&dev->struct_mutex); |
8090c6b9 | 10989 | intel_enable_gt_powersave(dev); |
79f5b2c7 | 10990 | mutex_unlock(&dev->struct_mutex); |
f817586c DV |
10991 | } |
10992 | ||
7d708ee4 ID |
10993 | void intel_modeset_suspend_hw(struct drm_device *dev) |
10994 | { | |
10995 | intel_suspend_hw(dev); | |
10996 | } | |
10997 | ||
79e53945 JB |
10998 | void intel_modeset_init(struct drm_device *dev) |
10999 | { | |
652c393a | 11000 | struct drm_i915_private *dev_priv = dev->dev_private; |
7f1f3851 | 11001 | int i, j, ret; |
79e53945 JB |
11002 | |
11003 | drm_mode_config_init(dev); | |
11004 | ||
11005 | dev->mode_config.min_width = 0; | |
11006 | dev->mode_config.min_height = 0; | |
11007 | ||
019d96cb DA |
11008 | dev->mode_config.preferred_depth = 24; |
11009 | dev->mode_config.prefer_shadow = 1; | |
11010 | ||
e6ecefaa | 11011 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 11012 | |
b690e96c JB |
11013 | intel_init_quirks(dev); |
11014 | ||
1fa61106 ED |
11015 | intel_init_pm(dev); |
11016 | ||
e3c74757 BW |
11017 | if (INTEL_INFO(dev)->num_pipes == 0) |
11018 | return; | |
11019 | ||
e70236a8 JB |
11020 | intel_init_display(dev); |
11021 | ||
a6c45cf0 CW |
11022 | if (IS_GEN2(dev)) { |
11023 | dev->mode_config.max_width = 2048; | |
11024 | dev->mode_config.max_height = 2048; | |
11025 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
11026 | dev->mode_config.max_width = 4096; |
11027 | dev->mode_config.max_height = 4096; | |
79e53945 | 11028 | } else { |
a6c45cf0 CW |
11029 | dev->mode_config.max_width = 8192; |
11030 | dev->mode_config.max_height = 8192; | |
79e53945 | 11031 | } |
5d4545ae | 11032 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 11033 | |
28c97730 | 11034 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
11035 | INTEL_INFO(dev)->num_pipes, |
11036 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 11037 | |
08e2a7de | 11038 | for_each_pipe(i) { |
79e53945 | 11039 | intel_crtc_init(dev, i); |
22d3fd46 | 11040 | for (j = 0; j < INTEL_INFO(dev)->num_sprites; j++) { |
7f1f3851 JB |
11041 | ret = intel_plane_init(dev, i, j); |
11042 | if (ret) | |
06da8da2 VS |
11043 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
11044 | pipe_name(i), sprite_name(i, j), ret); | |
7f1f3851 | 11045 | } |
79e53945 JB |
11046 | } |
11047 | ||
f42bb70d | 11048 | intel_init_dpio(dev); |
5382f5f3 | 11049 | intel_reset_dpio(dev); |
f42bb70d | 11050 | |
79f689aa | 11051 | intel_cpu_pll_init(dev); |
e72f9fbf | 11052 | intel_shared_dpll_init(dev); |
ee7b9f93 | 11053 | |
9cce37f4 JB |
11054 | /* Just disable it once at startup */ |
11055 | i915_disable_vga(dev); | |
79e53945 | 11056 | intel_setup_outputs(dev); |
11be49eb CW |
11057 | |
11058 | /* Just in case the BIOS is doing something questionable. */ | |
11059 | intel_disable_fbc(dev); | |
2c7111db CW |
11060 | } |
11061 | ||
24929352 DV |
11062 | static void |
11063 | intel_connector_break_all_links(struct intel_connector *connector) | |
11064 | { | |
11065 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
11066 | connector->base.encoder = NULL; | |
11067 | connector->encoder->connectors_active = false; | |
11068 | connector->encoder->base.crtc = NULL; | |
11069 | } | |
11070 | ||
7fad798e DV |
11071 | static void intel_enable_pipe_a(struct drm_device *dev) |
11072 | { | |
11073 | struct intel_connector *connector; | |
11074 | struct drm_connector *crt = NULL; | |
11075 | struct intel_load_detect_pipe load_detect_temp; | |
11076 | ||
11077 | /* We can't just switch on the pipe A, we need to set things up with a | |
11078 | * proper mode and output configuration. As a gross hack, enable pipe A | |
11079 | * by enabling the load detect pipe once. */ | |
11080 | list_for_each_entry(connector, | |
11081 | &dev->mode_config.connector_list, | |
11082 | base.head) { | |
11083 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { | |
11084 | crt = &connector->base; | |
11085 | break; | |
11086 | } | |
11087 | } | |
11088 | ||
11089 | if (!crt) | |
11090 | return; | |
11091 | ||
11092 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp)) | |
11093 | intel_release_load_detect_pipe(crt, &load_detect_temp); | |
11094 | ||
652c393a | 11095 | |
7fad798e DV |
11096 | } |
11097 | ||
fa555837 DV |
11098 | static bool |
11099 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
11100 | { | |
7eb552ae BW |
11101 | struct drm_device *dev = crtc->base.dev; |
11102 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
11103 | u32 reg, val; |
11104 | ||
7eb552ae | 11105 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
11106 | return true; |
11107 | ||
11108 | reg = DSPCNTR(!crtc->plane); | |
11109 | val = I915_READ(reg); | |
11110 | ||
11111 | if ((val & DISPLAY_PLANE_ENABLE) && | |
11112 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
11113 | return false; | |
11114 | ||
11115 | return true; | |
11116 | } | |
11117 | ||
24929352 DV |
11118 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
11119 | { | |
11120 | struct drm_device *dev = crtc->base.dev; | |
11121 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 11122 | u32 reg; |
24929352 | 11123 | |
24929352 | 11124 | /* Clear any frame start delays used for debugging left by the BIOS */ |
3b117c8f | 11125 | reg = PIPECONF(crtc->config.cpu_transcoder); |
24929352 DV |
11126 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
11127 | ||
11128 | /* We need to sanitize the plane -> pipe mapping first because this will | |
fa555837 DV |
11129 | * disable the crtc (and hence change the state) if it is wrong. Note |
11130 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
11131 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
11132 | struct intel_connector *connector; |
11133 | bool plane; | |
11134 | ||
24929352 DV |
11135 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
11136 | crtc->base.base.id); | |
11137 | ||
11138 | /* Pipe has the wrong plane attached and the plane is active. | |
11139 | * Temporarily change the plane mapping and disable everything | |
11140 | * ... */ | |
11141 | plane = crtc->plane; | |
11142 | crtc->plane = !plane; | |
11143 | dev_priv->display.crtc_disable(&crtc->base); | |
11144 | crtc->plane = plane; | |
11145 | ||
11146 | /* ... and break all links. */ | |
11147 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
11148 | base.head) { | |
11149 | if (connector->encoder->base.crtc != &crtc->base) | |
11150 | continue; | |
11151 | ||
11152 | intel_connector_break_all_links(connector); | |
11153 | } | |
11154 | ||
11155 | WARN_ON(crtc->active); | |
11156 | crtc->base.enabled = false; | |
11157 | } | |
24929352 | 11158 | |
7fad798e DV |
11159 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
11160 | crtc->pipe == PIPE_A && !crtc->active) { | |
11161 | /* BIOS forgot to enable pipe A, this mostly happens after | |
11162 | * resume. Force-enable the pipe to fix this, the update_dpms | |
11163 | * call below we restore the pipe to the right state, but leave | |
11164 | * the required bits on. */ | |
11165 | intel_enable_pipe_a(dev); | |
11166 | } | |
11167 | ||
24929352 DV |
11168 | /* Adjust the state of the output pipe according to whether we |
11169 | * have active connectors/encoders. */ | |
11170 | intel_crtc_update_dpms(&crtc->base); | |
11171 | ||
11172 | if (crtc->active != crtc->base.enabled) { | |
11173 | struct intel_encoder *encoder; | |
11174 | ||
11175 | /* This can happen either due to bugs in the get_hw_state | |
11176 | * functions or because the pipe is force-enabled due to the | |
11177 | * pipe A quirk. */ | |
11178 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
11179 | crtc->base.base.id, | |
11180 | crtc->base.enabled ? "enabled" : "disabled", | |
11181 | crtc->active ? "enabled" : "disabled"); | |
11182 | ||
11183 | crtc->base.enabled = crtc->active; | |
11184 | ||
11185 | /* Because we only establish the connector -> encoder -> | |
11186 | * crtc links if something is active, this means the | |
11187 | * crtc is now deactivated. Break the links. connector | |
11188 | * -> encoder links are only establish when things are | |
11189 | * actually up, hence no need to break them. */ | |
11190 | WARN_ON(crtc->active); | |
11191 | ||
11192 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
11193 | WARN_ON(encoder->connectors_active); | |
11194 | encoder->base.crtc = NULL; | |
11195 | } | |
11196 | } | |
11197 | } | |
11198 | ||
11199 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
11200 | { | |
11201 | struct intel_connector *connector; | |
11202 | struct drm_device *dev = encoder->base.dev; | |
11203 | ||
11204 | /* We need to check both for a crtc link (meaning that the | |
11205 | * encoder is active and trying to read from a pipe) and the | |
11206 | * pipe itself being active. */ | |
11207 | bool has_active_crtc = encoder->base.crtc && | |
11208 | to_intel_crtc(encoder->base.crtc)->active; | |
11209 | ||
11210 | if (encoder->connectors_active && !has_active_crtc) { | |
11211 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
11212 | encoder->base.base.id, | |
11213 | drm_get_encoder_name(&encoder->base)); | |
11214 | ||
11215 | /* Connector is active, but has no active pipe. This is | |
11216 | * fallout from our resume register restoring. Disable | |
11217 | * the encoder manually again. */ | |
11218 | if (encoder->base.crtc) { | |
11219 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
11220 | encoder->base.base.id, | |
11221 | drm_get_encoder_name(&encoder->base)); | |
11222 | encoder->disable(encoder); | |
11223 | } | |
11224 | ||
11225 | /* Inconsistent output/port/pipe state happens presumably due to | |
11226 | * a bug in one of the get_hw_state functions. Or someplace else | |
11227 | * in our code, like the register restore mess on resume. Clamp | |
11228 | * things to off as a safer default. */ | |
11229 | list_for_each_entry(connector, | |
11230 | &dev->mode_config.connector_list, | |
11231 | base.head) { | |
11232 | if (connector->encoder != encoder) | |
11233 | continue; | |
11234 | ||
11235 | intel_connector_break_all_links(connector); | |
11236 | } | |
11237 | } | |
11238 | /* Enabled encoders without active connectors will be fixed in | |
11239 | * the crtc fixup. */ | |
11240 | } | |
11241 | ||
44cec740 | 11242 | void i915_redisable_vga(struct drm_device *dev) |
0fde901f KM |
11243 | { |
11244 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 11245 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 11246 | |
8dc8a27c PZ |
11247 | /* This function can be called both from intel_modeset_setup_hw_state or |
11248 | * at a very early point in our resume sequence, where the power well | |
11249 | * structures are not yet restored. Since this function is at a very | |
11250 | * paranoid "someone might have enabled VGA while we were not looking" | |
11251 | * level, just check if the power well is enabled instead of trying to | |
11252 | * follow the "don't touch the power well if we don't need it" policy | |
11253 | * the rest of the driver uses. */ | |
f9e711e9 | 11254 | if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && |
6aedd1f5 | 11255 | (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0) |
8dc8a27c PZ |
11256 | return; |
11257 | ||
e1553faa | 11258 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
0fde901f | 11259 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); |
209d5211 | 11260 | i915_disable_vga(dev); |
0fde901f KM |
11261 | } |
11262 | } | |
11263 | ||
30e984df | 11264 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
11265 | { |
11266 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11267 | enum pipe pipe; | |
24929352 DV |
11268 | struct intel_crtc *crtc; |
11269 | struct intel_encoder *encoder; | |
11270 | struct intel_connector *connector; | |
5358901f | 11271 | int i; |
24929352 | 11272 | |
0e8ffe1b DV |
11273 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
11274 | base.head) { | |
88adfff1 | 11275 | memset(&crtc->config, 0, sizeof(crtc->config)); |
3b117c8f | 11276 | |
0e8ffe1b DV |
11277 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
11278 | &crtc->config); | |
24929352 DV |
11279 | |
11280 | crtc->base.enabled = crtc->active; | |
4c445e0e | 11281 | crtc->primary_enabled = crtc->active; |
24929352 DV |
11282 | |
11283 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
11284 | crtc->base.base.id, | |
11285 | crtc->active ? "enabled" : "disabled"); | |
11286 | } | |
11287 | ||
5358901f | 11288 | /* FIXME: Smash this into the new shared dpll infrastructure. */ |
affa9354 | 11289 | if (HAS_DDI(dev)) |
6441ab5f PZ |
11290 | intel_ddi_setup_hw_pll_state(dev); |
11291 | ||
5358901f DV |
11292 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
11293 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
11294 | ||
11295 | pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state); | |
11296 | pll->active = 0; | |
11297 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
11298 | base.head) { | |
11299 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
11300 | pll->active++; | |
11301 | } | |
11302 | pll->refcount = pll->active; | |
11303 | ||
35c95375 DV |
11304 | DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n", |
11305 | pll->name, pll->refcount, pll->on); | |
5358901f DV |
11306 | } |
11307 | ||
24929352 DV |
11308 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
11309 | base.head) { | |
11310 | pipe = 0; | |
11311 | ||
11312 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
11313 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
11314 | encoder->base.crtc = &crtc->base; | |
1d37b689 | 11315 | encoder->get_config(encoder, &crtc->config); |
24929352 DV |
11316 | } else { |
11317 | encoder->base.crtc = NULL; | |
11318 | } | |
11319 | ||
11320 | encoder->connectors_active = false; | |
6f2bcceb | 11321 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 DV |
11322 | encoder->base.base.id, |
11323 | drm_get_encoder_name(&encoder->base), | |
11324 | encoder->base.crtc ? "enabled" : "disabled", | |
6f2bcceb | 11325 | pipe_name(pipe)); |
24929352 DV |
11326 | } |
11327 | ||
11328 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
11329 | base.head) { | |
11330 | if (connector->get_hw_state(connector)) { | |
11331 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
11332 | connector->encoder->connectors_active = true; | |
11333 | connector->base.encoder = &connector->encoder->base; | |
11334 | } else { | |
11335 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
11336 | connector->base.encoder = NULL; | |
11337 | } | |
11338 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
11339 | connector->base.base.id, | |
11340 | drm_get_connector_name(&connector->base), | |
11341 | connector->base.encoder ? "enabled" : "disabled"); | |
11342 | } | |
30e984df DV |
11343 | } |
11344 | ||
11345 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm | |
11346 | * and i915 state tracking structures. */ | |
11347 | void intel_modeset_setup_hw_state(struct drm_device *dev, | |
11348 | bool force_restore) | |
11349 | { | |
11350 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11351 | enum pipe pipe; | |
30e984df DV |
11352 | struct intel_crtc *crtc; |
11353 | struct intel_encoder *encoder; | |
35c95375 | 11354 | int i; |
30e984df DV |
11355 | |
11356 | intel_modeset_readout_hw_state(dev); | |
24929352 | 11357 | |
babea61d JB |
11358 | /* |
11359 | * Now that we have the config, copy it to each CRTC struct | |
11360 | * Note that this could go away if we move to using crtc_config | |
11361 | * checking everywhere. | |
11362 | */ | |
11363 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
11364 | base.head) { | |
d330a953 | 11365 | if (crtc->active && i915.fastboot) { |
babea61d JB |
11366 | intel_crtc_mode_from_pipe_config(crtc, &crtc->config); |
11367 | ||
11368 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", | |
11369 | crtc->base.base.id); | |
11370 | drm_mode_debug_printmodeline(&crtc->base.mode); | |
11371 | } | |
11372 | } | |
11373 | ||
24929352 DV |
11374 | /* HW state is read out, now we need to sanitize this mess. */ |
11375 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
11376 | base.head) { | |
11377 | intel_sanitize_encoder(encoder); | |
11378 | } | |
11379 | ||
11380 | for_each_pipe(pipe) { | |
11381 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
11382 | intel_sanitize_crtc(crtc); | |
c0b03411 | 11383 | intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]"); |
24929352 | 11384 | } |
9a935856 | 11385 | |
35c95375 DV |
11386 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
11387 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
11388 | ||
11389 | if (!pll->on || pll->active) | |
11390 | continue; | |
11391 | ||
11392 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
11393 | ||
11394 | pll->disable(dev_priv, pll); | |
11395 | pll->on = false; | |
11396 | } | |
11397 | ||
96f90c54 | 11398 | if (HAS_PCH_SPLIT(dev)) |
243e6a44 VS |
11399 | ilk_wm_get_hw_state(dev); |
11400 | ||
45e2b5f6 | 11401 | if (force_restore) { |
7d0bc1ea VS |
11402 | i915_redisable_vga(dev); |
11403 | ||
f30da187 DV |
11404 | /* |
11405 | * We need to use raw interfaces for restoring state to avoid | |
11406 | * checking (bogus) intermediate states. | |
11407 | */ | |
45e2b5f6 | 11408 | for_each_pipe(pipe) { |
b5644d05 JB |
11409 | struct drm_crtc *crtc = |
11410 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
f30da187 DV |
11411 | |
11412 | __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, | |
11413 | crtc->fb); | |
45e2b5f6 DV |
11414 | } |
11415 | } else { | |
11416 | intel_modeset_update_staged_output_state(dev); | |
11417 | } | |
8af6cf88 DV |
11418 | |
11419 | intel_modeset_check_state(dev); | |
2c7111db CW |
11420 | } |
11421 | ||
11422 | void intel_modeset_gem_init(struct drm_device *dev) | |
11423 | { | |
1833b134 | 11424 | intel_modeset_init_hw(dev); |
02e792fb DV |
11425 | |
11426 | intel_setup_overlay(dev); | |
24929352 | 11427 | |
7ad228b1 | 11428 | mutex_lock(&dev->mode_config.mutex); |
45e2b5f6 | 11429 | intel_modeset_setup_hw_state(dev, false); |
7ad228b1 | 11430 | mutex_unlock(&dev->mode_config.mutex); |
79e53945 JB |
11431 | } |
11432 | ||
11433 | void intel_modeset_cleanup(struct drm_device *dev) | |
11434 | { | |
652c393a JB |
11435 | struct drm_i915_private *dev_priv = dev->dev_private; |
11436 | struct drm_crtc *crtc; | |
d9255d57 | 11437 | struct drm_connector *connector; |
652c393a | 11438 | |
fd0c0642 DV |
11439 | /* |
11440 | * Interrupts and polling as the first thing to avoid creating havoc. | |
11441 | * Too much stuff here (turning of rps, connectors, ...) would | |
11442 | * experience fancy races otherwise. | |
11443 | */ | |
11444 | drm_irq_uninstall(dev); | |
11445 | cancel_work_sync(&dev_priv->hotplug_work); | |
11446 | /* | |
11447 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
11448 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
11449 | */ | |
f87ea761 | 11450 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 11451 | |
652c393a JB |
11452 | mutex_lock(&dev->struct_mutex); |
11453 | ||
723bfd70 JB |
11454 | intel_unregister_dsm_handler(); |
11455 | ||
652c393a JB |
11456 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
11457 | /* Skip inactive CRTCs */ | |
11458 | if (!crtc->fb) | |
11459 | continue; | |
11460 | ||
3dec0095 | 11461 | intel_increase_pllclock(crtc); |
652c393a JB |
11462 | } |
11463 | ||
973d04f9 | 11464 | intel_disable_fbc(dev); |
e70236a8 | 11465 | |
8090c6b9 | 11466 | intel_disable_gt_powersave(dev); |
0cdab21f | 11467 | |
930ebb46 DV |
11468 | ironlake_teardown_rc6(dev); |
11469 | ||
69341a5e KH |
11470 | mutex_unlock(&dev->struct_mutex); |
11471 | ||
1630fe75 CW |
11472 | /* flush any delayed tasks or pending work */ |
11473 | flush_scheduled_work(); | |
11474 | ||
db31af1d JN |
11475 | /* destroy the backlight and sysfs files before encoders/connectors */ |
11476 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
11477 | intel_panel_destroy_backlight(connector); | |
d9255d57 | 11478 | drm_sysfs_connector_remove(connector); |
db31af1d | 11479 | } |
d9255d57 | 11480 | |
79e53945 | 11481 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
11482 | |
11483 | intel_cleanup_overlay(dev); | |
79e53945 JB |
11484 | } |
11485 | ||
f1c79df3 ZW |
11486 | /* |
11487 | * Return which encoder is currently attached for connector. | |
11488 | */ | |
df0e9248 | 11489 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 11490 | { |
df0e9248 CW |
11491 | return &intel_attached_encoder(connector)->base; |
11492 | } | |
f1c79df3 | 11493 | |
df0e9248 CW |
11494 | void intel_connector_attach_encoder(struct intel_connector *connector, |
11495 | struct intel_encoder *encoder) | |
11496 | { | |
11497 | connector->encoder = encoder; | |
11498 | drm_mode_connector_attach_encoder(&connector->base, | |
11499 | &encoder->base); | |
79e53945 | 11500 | } |
28d52043 DA |
11501 | |
11502 | /* | |
11503 | * set vga decode state - true == enable VGA decode | |
11504 | */ | |
11505 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
11506 | { | |
11507 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 11508 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
11509 | u16 gmch_ctrl; |
11510 | ||
75fa041d CW |
11511 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
11512 | DRM_ERROR("failed to read control word\n"); | |
11513 | return -EIO; | |
11514 | } | |
11515 | ||
28d52043 DA |
11516 | if (state) |
11517 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
11518 | else | |
11519 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
11520 | |
11521 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
11522 | DRM_ERROR("failed to write control word\n"); | |
11523 | return -EIO; | |
11524 | } | |
11525 | ||
28d52043 DA |
11526 | return 0; |
11527 | } | |
c4a1d9e4 | 11528 | |
c4a1d9e4 | 11529 | struct intel_display_error_state { |
ff57f1b0 PZ |
11530 | |
11531 | u32 power_well_driver; | |
11532 | ||
63b66e5b CW |
11533 | int num_transcoders; |
11534 | ||
c4a1d9e4 CW |
11535 | struct intel_cursor_error_state { |
11536 | u32 control; | |
11537 | u32 position; | |
11538 | u32 base; | |
11539 | u32 size; | |
52331309 | 11540 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
11541 | |
11542 | struct intel_pipe_error_state { | |
ddf9c536 | 11543 | bool power_domain_on; |
c4a1d9e4 | 11544 | u32 source; |
52331309 | 11545 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
11546 | |
11547 | struct intel_plane_error_state { | |
11548 | u32 control; | |
11549 | u32 stride; | |
11550 | u32 size; | |
11551 | u32 pos; | |
11552 | u32 addr; | |
11553 | u32 surface; | |
11554 | u32 tile_offset; | |
52331309 | 11555 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
11556 | |
11557 | struct intel_transcoder_error_state { | |
ddf9c536 | 11558 | bool power_domain_on; |
63b66e5b CW |
11559 | enum transcoder cpu_transcoder; |
11560 | ||
11561 | u32 conf; | |
11562 | ||
11563 | u32 htotal; | |
11564 | u32 hblank; | |
11565 | u32 hsync; | |
11566 | u32 vtotal; | |
11567 | u32 vblank; | |
11568 | u32 vsync; | |
11569 | } transcoder[4]; | |
c4a1d9e4 CW |
11570 | }; |
11571 | ||
11572 | struct intel_display_error_state * | |
11573 | intel_display_capture_error_state(struct drm_device *dev) | |
11574 | { | |
0206e353 | 11575 | drm_i915_private_t *dev_priv = dev->dev_private; |
c4a1d9e4 | 11576 | struct intel_display_error_state *error; |
63b66e5b CW |
11577 | int transcoders[] = { |
11578 | TRANSCODER_A, | |
11579 | TRANSCODER_B, | |
11580 | TRANSCODER_C, | |
11581 | TRANSCODER_EDP, | |
11582 | }; | |
c4a1d9e4 CW |
11583 | int i; |
11584 | ||
63b66e5b CW |
11585 | if (INTEL_INFO(dev)->num_pipes == 0) |
11586 | return NULL; | |
11587 | ||
9d1cb914 | 11588 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
11589 | if (error == NULL) |
11590 | return NULL; | |
11591 | ||
190be112 | 11592 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
11593 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
11594 | ||
52331309 | 11595 | for_each_pipe(i) { |
ddf9c536 ID |
11596 | error->pipe[i].power_domain_on = |
11597 | intel_display_power_enabled_sw(dev, POWER_DOMAIN_PIPE(i)); | |
11598 | if (!error->pipe[i].power_domain_on) | |
9d1cb914 PZ |
11599 | continue; |
11600 | ||
a18c4c3d PZ |
11601 | if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) { |
11602 | error->cursor[i].control = I915_READ(CURCNTR(i)); | |
11603 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
11604 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
11605 | } else { | |
11606 | error->cursor[i].control = I915_READ(CURCNTR_IVB(i)); | |
11607 | error->cursor[i].position = I915_READ(CURPOS_IVB(i)); | |
11608 | error->cursor[i].base = I915_READ(CURBASE_IVB(i)); | |
11609 | } | |
c4a1d9e4 CW |
11610 | |
11611 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
11612 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 11613 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 11614 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
11615 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
11616 | } | |
ca291363 PZ |
11617 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
11618 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
11619 | if (INTEL_INFO(dev)->gen >= 4) { |
11620 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
11621 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
11622 | } | |
11623 | ||
c4a1d9e4 | 11624 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
63b66e5b CW |
11625 | } |
11626 | ||
11627 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
11628 | if (HAS_DDI(dev_priv->dev)) | |
11629 | error->num_transcoders++; /* Account for eDP. */ | |
11630 | ||
11631 | for (i = 0; i < error->num_transcoders; i++) { | |
11632 | enum transcoder cpu_transcoder = transcoders[i]; | |
11633 | ||
ddf9c536 | 11634 | error->transcoder[i].power_domain_on = |
38cc1daf PZ |
11635 | intel_display_power_enabled_sw(dev, |
11636 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); | |
ddf9c536 | 11637 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
11638 | continue; |
11639 | ||
63b66e5b CW |
11640 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
11641 | ||
11642 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
11643 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
11644 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
11645 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
11646 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
11647 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
11648 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
11649 | } |
11650 | ||
11651 | return error; | |
11652 | } | |
11653 | ||
edc3d884 MK |
11654 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
11655 | ||
c4a1d9e4 | 11656 | void |
edc3d884 | 11657 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
11658 | struct drm_device *dev, |
11659 | struct intel_display_error_state *error) | |
11660 | { | |
11661 | int i; | |
11662 | ||
63b66e5b CW |
11663 | if (!error) |
11664 | return; | |
11665 | ||
edc3d884 | 11666 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 11667 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 11668 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 11669 | error->power_well_driver); |
52331309 | 11670 | for_each_pipe(i) { |
edc3d884 | 11671 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 ID |
11672 | err_printf(m, " Power: %s\n", |
11673 | error->pipe[i].power_domain_on ? "on" : "off"); | |
edc3d884 | 11674 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
edc3d884 MK |
11675 | |
11676 | err_printf(m, "Plane [%d]:\n", i); | |
11677 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
11678 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 11679 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
11680 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
11681 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 11682 | } |
4b71a570 | 11683 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 11684 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 11685 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
11686 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
11687 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
11688 | } |
11689 | ||
edc3d884 MK |
11690 | err_printf(m, "Cursor [%d]:\n", i); |
11691 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
11692 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
11693 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 11694 | } |
63b66e5b CW |
11695 | |
11696 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 11697 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 11698 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 ID |
11699 | err_printf(m, " Power: %s\n", |
11700 | error->transcoder[i].power_domain_on ? "on" : "off"); | |
63b66e5b CW |
11701 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
11702 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
11703 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
11704 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
11705 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
11706 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
11707 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
11708 | } | |
c4a1d9e4 | 11709 | } |