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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
319c1d42 | 40 | #include <drm/drm_atomic.h> |
c196e1d6 | 41 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
42 | #include <drm/drm_dp_helper.h> |
43 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
44 | #include <drm/drm_plane_helper.h> |
45 | #include <drm/drm_rect.h> | |
c0f372b3 | 46 | #include <linux/dma_remapping.h> |
79e53945 | 47 | |
465c120c MR |
48 | /* Primary plane formats supported by all gen */ |
49 | #define COMMON_PRIMARY_FORMATS \ | |
50 | DRM_FORMAT_C8, \ | |
51 | DRM_FORMAT_RGB565, \ | |
52 | DRM_FORMAT_XRGB8888, \ | |
53 | DRM_FORMAT_ARGB8888 | |
54 | ||
55 | /* Primary plane formats for gen <= 3 */ | |
56 | static const uint32_t intel_primary_formats_gen2[] = { | |
57 | COMMON_PRIMARY_FORMATS, | |
58 | DRM_FORMAT_XRGB1555, | |
59 | DRM_FORMAT_ARGB1555, | |
60 | }; | |
61 | ||
62 | /* Primary plane formats for gen >= 4 */ | |
63 | static const uint32_t intel_primary_formats_gen4[] = { | |
64 | COMMON_PRIMARY_FORMATS, \ | |
65 | DRM_FORMAT_XBGR8888, | |
66 | DRM_FORMAT_ABGR8888, | |
67 | DRM_FORMAT_XRGB2101010, | |
68 | DRM_FORMAT_ARGB2101010, | |
69 | DRM_FORMAT_XBGR2101010, | |
70 | DRM_FORMAT_ABGR2101010, | |
71 | }; | |
72 | ||
3d7d6510 MR |
73 | /* Cursor formats */ |
74 | static const uint32_t intel_cursor_formats[] = { | |
75 | DRM_FORMAT_ARGB8888, | |
76 | }; | |
77 | ||
6b383a7f | 78 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 79 | |
f1f644dc | 80 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 81 | struct intel_crtc_state *pipe_config); |
18442d08 | 82 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 83 | struct intel_crtc_state *pipe_config); |
f1f644dc | 84 | |
e7457a9a DL |
85 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
86 | int x, int y, struct drm_framebuffer *old_fb); | |
eb1bfe80 JB |
87 | static int intel_framebuffer_init(struct drm_device *dev, |
88 | struct intel_framebuffer *ifb, | |
89 | struct drm_mode_fb_cmd2 *mode_cmd, | |
90 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
91 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
92 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
29407aab | 93 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
94 | struct intel_link_m_n *m_n, |
95 | struct intel_link_m_n *m2_n2); | |
29407aab | 96 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 DV |
97 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
98 | static void intel_set_pipe_csc(struct drm_crtc *crtc); | |
d288f65f | 99 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 100 | const struct intel_crtc_state *pipe_config); |
d288f65f | 101 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 102 | const struct intel_crtc_state *pipe_config); |
ea2c67bb MR |
103 | static void intel_begin_crtc_commit(struct drm_crtc *crtc); |
104 | static void intel_finish_crtc_commit(struct drm_crtc *crtc); | |
e7457a9a | 105 | |
0e32b39c DA |
106 | static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe) |
107 | { | |
108 | if (!connector->mst_port) | |
109 | return connector->encoder; | |
110 | else | |
111 | return &connector->mst_port->mst_encoders[pipe]->base; | |
112 | } | |
113 | ||
79e53945 | 114 | typedef struct { |
0206e353 | 115 | int min, max; |
79e53945 JB |
116 | } intel_range_t; |
117 | ||
118 | typedef struct { | |
0206e353 AJ |
119 | int dot_limit; |
120 | int p2_slow, p2_fast; | |
79e53945 JB |
121 | } intel_p2_t; |
122 | ||
d4906093 ML |
123 | typedef struct intel_limit intel_limit_t; |
124 | struct intel_limit { | |
0206e353 AJ |
125 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
126 | intel_p2_t p2; | |
d4906093 | 127 | }; |
79e53945 | 128 | |
d2acd215 DV |
129 | int |
130 | intel_pch_rawclk(struct drm_device *dev) | |
131 | { | |
132 | struct drm_i915_private *dev_priv = dev->dev_private; | |
133 | ||
134 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
135 | ||
136 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
137 | } | |
138 | ||
021357ac CW |
139 | static inline u32 /* units of 100MHz */ |
140 | intel_fdi_link_freq(struct drm_device *dev) | |
141 | { | |
8b99e68c CW |
142 | if (IS_GEN5(dev)) { |
143 | struct drm_i915_private *dev_priv = dev->dev_private; | |
144 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
145 | } else | |
146 | return 27; | |
021357ac CW |
147 | } |
148 | ||
5d536e28 | 149 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 150 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 151 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 152 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
153 | .m = { .min = 96, .max = 140 }, |
154 | .m1 = { .min = 18, .max = 26 }, | |
155 | .m2 = { .min = 6, .max = 16 }, | |
156 | .p = { .min = 4, .max = 128 }, | |
157 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
158 | .p2 = { .dot_limit = 165000, |
159 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
160 | }; |
161 | ||
5d536e28 DV |
162 | static const intel_limit_t intel_limits_i8xx_dvo = { |
163 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 164 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 165 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
166 | .m = { .min = 96, .max = 140 }, |
167 | .m1 = { .min = 18, .max = 26 }, | |
168 | .m2 = { .min = 6, .max = 16 }, | |
169 | .p = { .min = 4, .max = 128 }, | |
170 | .p1 = { .min = 2, .max = 33 }, | |
171 | .p2 = { .dot_limit = 165000, | |
172 | .p2_slow = 4, .p2_fast = 4 }, | |
173 | }; | |
174 | ||
e4b36699 | 175 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 176 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 177 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 178 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
179 | .m = { .min = 96, .max = 140 }, |
180 | .m1 = { .min = 18, .max = 26 }, | |
181 | .m2 = { .min = 6, .max = 16 }, | |
182 | .p = { .min = 4, .max = 128 }, | |
183 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
184 | .p2 = { .dot_limit = 165000, |
185 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 186 | }; |
273e27ca | 187 | |
e4b36699 | 188 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
189 | .dot = { .min = 20000, .max = 400000 }, |
190 | .vco = { .min = 1400000, .max = 2800000 }, | |
191 | .n = { .min = 1, .max = 6 }, | |
192 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
193 | .m1 = { .min = 8, .max = 18 }, |
194 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
195 | .p = { .min = 5, .max = 80 }, |
196 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
197 | .p2 = { .dot_limit = 200000, |
198 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
199 | }; |
200 | ||
201 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
202 | .dot = { .min = 20000, .max = 400000 }, |
203 | .vco = { .min = 1400000, .max = 2800000 }, | |
204 | .n = { .min = 1, .max = 6 }, | |
205 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
206 | .m1 = { .min = 8, .max = 18 }, |
207 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
208 | .p = { .min = 7, .max = 98 }, |
209 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
210 | .p2 = { .dot_limit = 112000, |
211 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
212 | }; |
213 | ||
273e27ca | 214 | |
e4b36699 | 215 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
216 | .dot = { .min = 25000, .max = 270000 }, |
217 | .vco = { .min = 1750000, .max = 3500000}, | |
218 | .n = { .min = 1, .max = 4 }, | |
219 | .m = { .min = 104, .max = 138 }, | |
220 | .m1 = { .min = 17, .max = 23 }, | |
221 | .m2 = { .min = 5, .max = 11 }, | |
222 | .p = { .min = 10, .max = 30 }, | |
223 | .p1 = { .min = 1, .max = 3}, | |
224 | .p2 = { .dot_limit = 270000, | |
225 | .p2_slow = 10, | |
226 | .p2_fast = 10 | |
044c7c41 | 227 | }, |
e4b36699 KP |
228 | }; |
229 | ||
230 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
231 | .dot = { .min = 22000, .max = 400000 }, |
232 | .vco = { .min = 1750000, .max = 3500000}, | |
233 | .n = { .min = 1, .max = 4 }, | |
234 | .m = { .min = 104, .max = 138 }, | |
235 | .m1 = { .min = 16, .max = 23 }, | |
236 | .m2 = { .min = 5, .max = 11 }, | |
237 | .p = { .min = 5, .max = 80 }, | |
238 | .p1 = { .min = 1, .max = 8}, | |
239 | .p2 = { .dot_limit = 165000, | |
240 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
241 | }; |
242 | ||
243 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
244 | .dot = { .min = 20000, .max = 115000 }, |
245 | .vco = { .min = 1750000, .max = 3500000 }, | |
246 | .n = { .min = 1, .max = 3 }, | |
247 | .m = { .min = 104, .max = 138 }, | |
248 | .m1 = { .min = 17, .max = 23 }, | |
249 | .m2 = { .min = 5, .max = 11 }, | |
250 | .p = { .min = 28, .max = 112 }, | |
251 | .p1 = { .min = 2, .max = 8 }, | |
252 | .p2 = { .dot_limit = 0, | |
253 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 254 | }, |
e4b36699 KP |
255 | }; |
256 | ||
257 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
258 | .dot = { .min = 80000, .max = 224000 }, |
259 | .vco = { .min = 1750000, .max = 3500000 }, | |
260 | .n = { .min = 1, .max = 3 }, | |
261 | .m = { .min = 104, .max = 138 }, | |
262 | .m1 = { .min = 17, .max = 23 }, | |
263 | .m2 = { .min = 5, .max = 11 }, | |
264 | .p = { .min = 14, .max = 42 }, | |
265 | .p1 = { .min = 2, .max = 6 }, | |
266 | .p2 = { .dot_limit = 0, | |
267 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 268 | }, |
e4b36699 KP |
269 | }; |
270 | ||
f2b115e6 | 271 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
272 | .dot = { .min = 20000, .max = 400000}, |
273 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 274 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
275 | .n = { .min = 3, .max = 6 }, |
276 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 277 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
278 | .m1 = { .min = 0, .max = 0 }, |
279 | .m2 = { .min = 0, .max = 254 }, | |
280 | .p = { .min = 5, .max = 80 }, | |
281 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
282 | .p2 = { .dot_limit = 200000, |
283 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
284 | }; |
285 | ||
f2b115e6 | 286 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
287 | .dot = { .min = 20000, .max = 400000 }, |
288 | .vco = { .min = 1700000, .max = 3500000 }, | |
289 | .n = { .min = 3, .max = 6 }, | |
290 | .m = { .min = 2, .max = 256 }, | |
291 | .m1 = { .min = 0, .max = 0 }, | |
292 | .m2 = { .min = 0, .max = 254 }, | |
293 | .p = { .min = 7, .max = 112 }, | |
294 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
295 | .p2 = { .dot_limit = 112000, |
296 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
297 | }; |
298 | ||
273e27ca EA |
299 | /* Ironlake / Sandybridge |
300 | * | |
301 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
302 | * the range value for them is (actual_value - 2). | |
303 | */ | |
b91ad0ec | 304 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
305 | .dot = { .min = 25000, .max = 350000 }, |
306 | .vco = { .min = 1760000, .max = 3510000 }, | |
307 | .n = { .min = 1, .max = 5 }, | |
308 | .m = { .min = 79, .max = 127 }, | |
309 | .m1 = { .min = 12, .max = 22 }, | |
310 | .m2 = { .min = 5, .max = 9 }, | |
311 | .p = { .min = 5, .max = 80 }, | |
312 | .p1 = { .min = 1, .max = 8 }, | |
313 | .p2 = { .dot_limit = 225000, | |
314 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
315 | }; |
316 | ||
b91ad0ec | 317 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
318 | .dot = { .min = 25000, .max = 350000 }, |
319 | .vco = { .min = 1760000, .max = 3510000 }, | |
320 | .n = { .min = 1, .max = 3 }, | |
321 | .m = { .min = 79, .max = 118 }, | |
322 | .m1 = { .min = 12, .max = 22 }, | |
323 | .m2 = { .min = 5, .max = 9 }, | |
324 | .p = { .min = 28, .max = 112 }, | |
325 | .p1 = { .min = 2, .max = 8 }, | |
326 | .p2 = { .dot_limit = 225000, | |
327 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
328 | }; |
329 | ||
330 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
331 | .dot = { .min = 25000, .max = 350000 }, |
332 | .vco = { .min = 1760000, .max = 3510000 }, | |
333 | .n = { .min = 1, .max = 3 }, | |
334 | .m = { .min = 79, .max = 127 }, | |
335 | .m1 = { .min = 12, .max = 22 }, | |
336 | .m2 = { .min = 5, .max = 9 }, | |
337 | .p = { .min = 14, .max = 56 }, | |
338 | .p1 = { .min = 2, .max = 8 }, | |
339 | .p2 = { .dot_limit = 225000, | |
340 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
341 | }; |
342 | ||
273e27ca | 343 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 344 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
345 | .dot = { .min = 25000, .max = 350000 }, |
346 | .vco = { .min = 1760000, .max = 3510000 }, | |
347 | .n = { .min = 1, .max = 2 }, | |
348 | .m = { .min = 79, .max = 126 }, | |
349 | .m1 = { .min = 12, .max = 22 }, | |
350 | .m2 = { .min = 5, .max = 9 }, | |
351 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 352 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
353 | .p2 = { .dot_limit = 225000, |
354 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
355 | }; |
356 | ||
357 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
358 | .dot = { .min = 25000, .max = 350000 }, |
359 | .vco = { .min = 1760000, .max = 3510000 }, | |
360 | .n = { .min = 1, .max = 3 }, | |
361 | .m = { .min = 79, .max = 126 }, | |
362 | .m1 = { .min = 12, .max = 22 }, | |
363 | .m2 = { .min = 5, .max = 9 }, | |
364 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 365 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
366 | .p2 = { .dot_limit = 225000, |
367 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
368 | }; |
369 | ||
dc730512 | 370 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
371 | /* |
372 | * These are the data rate limits (measured in fast clocks) | |
373 | * since those are the strictest limits we have. The fast | |
374 | * clock and actual rate limits are more relaxed, so checking | |
375 | * them would make no difference. | |
376 | */ | |
377 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 378 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 379 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
380 | .m1 = { .min = 2, .max = 3 }, |
381 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 382 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 383 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
384 | }; |
385 | ||
ef9348c8 CML |
386 | static const intel_limit_t intel_limits_chv = { |
387 | /* | |
388 | * These are the data rate limits (measured in fast clocks) | |
389 | * since those are the strictest limits we have. The fast | |
390 | * clock and actual rate limits are more relaxed, so checking | |
391 | * them would make no difference. | |
392 | */ | |
393 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 394 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
395 | .n = { .min = 1, .max = 1 }, |
396 | .m1 = { .min = 2, .max = 2 }, | |
397 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
398 | .p1 = { .min = 2, .max = 4 }, | |
399 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
400 | }; | |
401 | ||
6b4bf1c4 VS |
402 | static void vlv_clock(int refclk, intel_clock_t *clock) |
403 | { | |
404 | clock->m = clock->m1 * clock->m2; | |
405 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
406 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
407 | return; | |
fb03ac01 VS |
408 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
409 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
6b4bf1c4 VS |
410 | } |
411 | ||
e0638cdf PZ |
412 | /** |
413 | * Returns whether any output on the specified pipe is of the specified type | |
414 | */ | |
4093561b | 415 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) |
e0638cdf | 416 | { |
409ee761 | 417 | struct drm_device *dev = crtc->base.dev; |
e0638cdf PZ |
418 | struct intel_encoder *encoder; |
419 | ||
409ee761 | 420 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
e0638cdf PZ |
421 | if (encoder->type == type) |
422 | return true; | |
423 | ||
424 | return false; | |
425 | } | |
426 | ||
d0737e1d ACO |
427 | /** |
428 | * Returns whether any output on the specified pipe will have the specified | |
429 | * type after a staged modeset is complete, i.e., the same as | |
430 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of | |
431 | * encoder->crtc. | |
432 | */ | |
433 | static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type) | |
434 | { | |
435 | struct drm_device *dev = crtc->base.dev; | |
436 | struct intel_encoder *encoder; | |
437 | ||
438 | for_each_intel_encoder(dev, encoder) | |
439 | if (encoder->new_crtc == crtc && encoder->type == type) | |
440 | return true; | |
441 | ||
442 | return false; | |
443 | } | |
444 | ||
409ee761 | 445 | static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc, |
1b894b59 | 446 | int refclk) |
2c07245f | 447 | { |
409ee761 | 448 | struct drm_device *dev = crtc->base.dev; |
2c07245f | 449 | const intel_limit_t *limit; |
b91ad0ec | 450 | |
d0737e1d | 451 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 452 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 453 | if (refclk == 100000) |
b91ad0ec ZW |
454 | limit = &intel_limits_ironlake_dual_lvds_100m; |
455 | else | |
456 | limit = &intel_limits_ironlake_dual_lvds; | |
457 | } else { | |
1b894b59 | 458 | if (refclk == 100000) |
b91ad0ec ZW |
459 | limit = &intel_limits_ironlake_single_lvds_100m; |
460 | else | |
461 | limit = &intel_limits_ironlake_single_lvds; | |
462 | } | |
c6bb3538 | 463 | } else |
b91ad0ec | 464 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
465 | |
466 | return limit; | |
467 | } | |
468 | ||
409ee761 | 469 | static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc) |
044c7c41 | 470 | { |
409ee761 | 471 | struct drm_device *dev = crtc->base.dev; |
044c7c41 ML |
472 | const intel_limit_t *limit; |
473 | ||
d0737e1d | 474 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 475 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 476 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 477 | else |
e4b36699 | 478 | limit = &intel_limits_g4x_single_channel_lvds; |
d0737e1d ACO |
479 | } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) || |
480 | intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 481 | limit = &intel_limits_g4x_hdmi; |
d0737e1d | 482 | } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 483 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 484 | } else /* The option is for other outputs */ |
e4b36699 | 485 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
486 | |
487 | return limit; | |
488 | } | |
489 | ||
409ee761 | 490 | static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk) |
79e53945 | 491 | { |
409ee761 | 492 | struct drm_device *dev = crtc->base.dev; |
79e53945 JB |
493 | const intel_limit_t *limit; |
494 | ||
bad720ff | 495 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 496 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 497 | else if (IS_G4X(dev)) { |
044c7c41 | 498 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 499 | } else if (IS_PINEVIEW(dev)) { |
d0737e1d | 500 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 501 | limit = &intel_limits_pineview_lvds; |
2177832f | 502 | else |
f2b115e6 | 503 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
504 | } else if (IS_CHERRYVIEW(dev)) { |
505 | limit = &intel_limits_chv; | |
a0c4da24 | 506 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 507 | limit = &intel_limits_vlv; |
a6c45cf0 | 508 | } else if (!IS_GEN2(dev)) { |
d0737e1d | 509 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) |
a6c45cf0 CW |
510 | limit = &intel_limits_i9xx_lvds; |
511 | else | |
512 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 | 513 | } else { |
d0737e1d | 514 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) |
e4b36699 | 515 | limit = &intel_limits_i8xx_lvds; |
d0737e1d | 516 | else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO)) |
e4b36699 | 517 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
518 | else |
519 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
520 | } |
521 | return limit; | |
522 | } | |
523 | ||
f2b115e6 AJ |
524 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
525 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 526 | { |
2177832f SL |
527 | clock->m = clock->m2 + 2; |
528 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
529 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
530 | return; | |
fb03ac01 VS |
531 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
532 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
2177832f SL |
533 | } |
534 | ||
7429e9d4 DV |
535 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
536 | { | |
537 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
538 | } | |
539 | ||
ac58c3f0 | 540 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
2177832f | 541 | { |
7429e9d4 | 542 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 543 | clock->p = clock->p1 * clock->p2; |
ed5ca77e VS |
544 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
545 | return; | |
fb03ac01 VS |
546 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
547 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
79e53945 JB |
548 | } |
549 | ||
ef9348c8 CML |
550 | static void chv_clock(int refclk, intel_clock_t *clock) |
551 | { | |
552 | clock->m = clock->m1 * clock->m2; | |
553 | clock->p = clock->p1 * clock->p2; | |
554 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
555 | return; | |
556 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, | |
557 | clock->n << 22); | |
558 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
559 | } | |
560 | ||
7c04d1d9 | 561 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
562 | /** |
563 | * Returns whether the given set of divisors are valid for a given refclk with | |
564 | * the given connectors. | |
565 | */ | |
566 | ||
1b894b59 CW |
567 | static bool intel_PLL_is_valid(struct drm_device *dev, |
568 | const intel_limit_t *limit, | |
569 | const intel_clock_t *clock) | |
79e53945 | 570 | { |
f01b7962 VS |
571 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
572 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 573 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 574 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 575 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 576 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 577 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 578 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 VS |
579 | |
580 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev)) | |
581 | if (clock->m1 <= clock->m2) | |
582 | INTELPllInvalid("m1 <= m2\n"); | |
583 | ||
584 | if (!IS_VALLEYVIEW(dev)) { | |
585 | if (clock->p < limit->p.min || limit->p.max < clock->p) | |
586 | INTELPllInvalid("p out of range\n"); | |
587 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
588 | INTELPllInvalid("m out of range\n"); | |
589 | } | |
590 | ||
79e53945 | 591 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 592 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
593 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
594 | * connector, etc., rather than just a single range. | |
595 | */ | |
596 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 597 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
598 | |
599 | return true; | |
600 | } | |
601 | ||
d4906093 | 602 | static bool |
a919ff14 | 603 | i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, |
cec2f356 SP |
604 | int target, int refclk, intel_clock_t *match_clock, |
605 | intel_clock_t *best_clock) | |
79e53945 | 606 | { |
a919ff14 | 607 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 608 | intel_clock_t clock; |
79e53945 JB |
609 | int err = target; |
610 | ||
d0737e1d | 611 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 612 | /* |
a210b028 DV |
613 | * For LVDS just rely on its current settings for dual-channel. |
614 | * We haven't figured out how to reliably set up different | |
615 | * single/dual channel state, if we even can. | |
79e53945 | 616 | */ |
1974cad0 | 617 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
618 | clock.p2 = limit->p2.p2_fast; |
619 | else | |
620 | clock.p2 = limit->p2.p2_slow; | |
621 | } else { | |
622 | if (target < limit->p2.dot_limit) | |
623 | clock.p2 = limit->p2.p2_slow; | |
624 | else | |
625 | clock.p2 = limit->p2.p2_fast; | |
626 | } | |
627 | ||
0206e353 | 628 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 629 | |
42158660 ZY |
630 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
631 | clock.m1++) { | |
632 | for (clock.m2 = limit->m2.min; | |
633 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 634 | if (clock.m2 >= clock.m1) |
42158660 ZY |
635 | break; |
636 | for (clock.n = limit->n.min; | |
637 | clock.n <= limit->n.max; clock.n++) { | |
638 | for (clock.p1 = limit->p1.min; | |
639 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
640 | int this_err; |
641 | ||
ac58c3f0 DV |
642 | i9xx_clock(refclk, &clock); |
643 | if (!intel_PLL_is_valid(dev, limit, | |
644 | &clock)) | |
645 | continue; | |
646 | if (match_clock && | |
647 | clock.p != match_clock->p) | |
648 | continue; | |
649 | ||
650 | this_err = abs(clock.dot - target); | |
651 | if (this_err < err) { | |
652 | *best_clock = clock; | |
653 | err = this_err; | |
654 | } | |
655 | } | |
656 | } | |
657 | } | |
658 | } | |
659 | ||
660 | return (err != target); | |
661 | } | |
662 | ||
663 | static bool | |
a919ff14 | 664 | pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, |
ee9300bb DV |
665 | int target, int refclk, intel_clock_t *match_clock, |
666 | intel_clock_t *best_clock) | |
79e53945 | 667 | { |
a919ff14 | 668 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 669 | intel_clock_t clock; |
79e53945 JB |
670 | int err = target; |
671 | ||
d0737e1d | 672 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 673 | /* |
a210b028 DV |
674 | * For LVDS just rely on its current settings for dual-channel. |
675 | * We haven't figured out how to reliably set up different | |
676 | * single/dual channel state, if we even can. | |
79e53945 | 677 | */ |
1974cad0 | 678 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
679 | clock.p2 = limit->p2.p2_fast; |
680 | else | |
681 | clock.p2 = limit->p2.p2_slow; | |
682 | } else { | |
683 | if (target < limit->p2.dot_limit) | |
684 | clock.p2 = limit->p2.p2_slow; | |
685 | else | |
686 | clock.p2 = limit->p2.p2_fast; | |
687 | } | |
688 | ||
0206e353 | 689 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 690 | |
42158660 ZY |
691 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
692 | clock.m1++) { | |
693 | for (clock.m2 = limit->m2.min; | |
694 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
695 | for (clock.n = limit->n.min; |
696 | clock.n <= limit->n.max; clock.n++) { | |
697 | for (clock.p1 = limit->p1.min; | |
698 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
699 | int this_err; |
700 | ||
ac58c3f0 | 701 | pineview_clock(refclk, &clock); |
1b894b59 CW |
702 | if (!intel_PLL_is_valid(dev, limit, |
703 | &clock)) | |
79e53945 | 704 | continue; |
cec2f356 SP |
705 | if (match_clock && |
706 | clock.p != match_clock->p) | |
707 | continue; | |
79e53945 JB |
708 | |
709 | this_err = abs(clock.dot - target); | |
710 | if (this_err < err) { | |
711 | *best_clock = clock; | |
712 | err = this_err; | |
713 | } | |
714 | } | |
715 | } | |
716 | } | |
717 | } | |
718 | ||
719 | return (err != target); | |
720 | } | |
721 | ||
d4906093 | 722 | static bool |
a919ff14 | 723 | g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, |
ee9300bb DV |
724 | int target, int refclk, intel_clock_t *match_clock, |
725 | intel_clock_t *best_clock) | |
d4906093 | 726 | { |
a919ff14 | 727 | struct drm_device *dev = crtc->base.dev; |
d4906093 ML |
728 | intel_clock_t clock; |
729 | int max_n; | |
730 | bool found; | |
6ba770dc AJ |
731 | /* approximately equals target * 0.00585 */ |
732 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
733 | found = false; |
734 | ||
d0737e1d | 735 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 736 | if (intel_is_dual_link_lvds(dev)) |
d4906093 ML |
737 | clock.p2 = limit->p2.p2_fast; |
738 | else | |
739 | clock.p2 = limit->p2.p2_slow; | |
740 | } else { | |
741 | if (target < limit->p2.dot_limit) | |
742 | clock.p2 = limit->p2.p2_slow; | |
743 | else | |
744 | clock.p2 = limit->p2.p2_fast; | |
745 | } | |
746 | ||
747 | memset(best_clock, 0, sizeof(*best_clock)); | |
748 | max_n = limit->n.max; | |
f77f13e2 | 749 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 750 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 751 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
752 | for (clock.m1 = limit->m1.max; |
753 | clock.m1 >= limit->m1.min; clock.m1--) { | |
754 | for (clock.m2 = limit->m2.max; | |
755 | clock.m2 >= limit->m2.min; clock.m2--) { | |
756 | for (clock.p1 = limit->p1.max; | |
757 | clock.p1 >= limit->p1.min; clock.p1--) { | |
758 | int this_err; | |
759 | ||
ac58c3f0 | 760 | i9xx_clock(refclk, &clock); |
1b894b59 CW |
761 | if (!intel_PLL_is_valid(dev, limit, |
762 | &clock)) | |
d4906093 | 763 | continue; |
1b894b59 CW |
764 | |
765 | this_err = abs(clock.dot - target); | |
d4906093 ML |
766 | if (this_err < err_most) { |
767 | *best_clock = clock; | |
768 | err_most = this_err; | |
769 | max_n = clock.n; | |
770 | found = true; | |
771 | } | |
772 | } | |
773 | } | |
774 | } | |
775 | } | |
2c07245f ZW |
776 | return found; |
777 | } | |
778 | ||
d5dd62bd ID |
779 | /* |
780 | * Check if the calculated PLL configuration is more optimal compared to the | |
781 | * best configuration and error found so far. Return the calculated error. | |
782 | */ | |
783 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
784 | const intel_clock_t *calculated_clock, | |
785 | const intel_clock_t *best_clock, | |
786 | unsigned int best_error_ppm, | |
787 | unsigned int *error_ppm) | |
788 | { | |
9ca3ba01 ID |
789 | /* |
790 | * For CHV ignore the error and consider only the P value. | |
791 | * Prefer a bigger P value based on HW requirements. | |
792 | */ | |
793 | if (IS_CHERRYVIEW(dev)) { | |
794 | *error_ppm = 0; | |
795 | ||
796 | return calculated_clock->p > best_clock->p; | |
797 | } | |
798 | ||
24be4e46 ID |
799 | if (WARN_ON_ONCE(!target_freq)) |
800 | return false; | |
801 | ||
d5dd62bd ID |
802 | *error_ppm = div_u64(1000000ULL * |
803 | abs(target_freq - calculated_clock->dot), | |
804 | target_freq); | |
805 | /* | |
806 | * Prefer a better P value over a better (smaller) error if the error | |
807 | * is small. Ensure this preference for future configurations too by | |
808 | * setting the error to 0. | |
809 | */ | |
810 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
811 | *error_ppm = 0; | |
812 | ||
813 | return true; | |
814 | } | |
815 | ||
816 | return *error_ppm + 10 < best_error_ppm; | |
817 | } | |
818 | ||
a0c4da24 | 819 | static bool |
a919ff14 | 820 | vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, |
ee9300bb DV |
821 | int target, int refclk, intel_clock_t *match_clock, |
822 | intel_clock_t *best_clock) | |
a0c4da24 | 823 | { |
a919ff14 | 824 | struct drm_device *dev = crtc->base.dev; |
6b4bf1c4 | 825 | intel_clock_t clock; |
69e4f900 | 826 | unsigned int bestppm = 1000000; |
27e639bf VS |
827 | /* min update 19.2 MHz */ |
828 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 829 | bool found = false; |
a0c4da24 | 830 | |
6b4bf1c4 VS |
831 | target *= 5; /* fast clock */ |
832 | ||
833 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
834 | |
835 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 836 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 837 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 838 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 839 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 840 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 841 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 842 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 843 | unsigned int ppm; |
69e4f900 | 844 | |
6b4bf1c4 VS |
845 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
846 | refclk * clock.m1); | |
847 | ||
848 | vlv_clock(refclk, &clock); | |
43b0ac53 | 849 | |
f01b7962 VS |
850 | if (!intel_PLL_is_valid(dev, limit, |
851 | &clock)) | |
43b0ac53 VS |
852 | continue; |
853 | ||
d5dd62bd ID |
854 | if (!vlv_PLL_is_optimal(dev, target, |
855 | &clock, | |
856 | best_clock, | |
857 | bestppm, &ppm)) | |
858 | continue; | |
6b4bf1c4 | 859 | |
d5dd62bd ID |
860 | *best_clock = clock; |
861 | bestppm = ppm; | |
862 | found = true; | |
a0c4da24 JB |
863 | } |
864 | } | |
865 | } | |
866 | } | |
a0c4da24 | 867 | |
49e497ef | 868 | return found; |
a0c4da24 | 869 | } |
a4fc5ed6 | 870 | |
ef9348c8 | 871 | static bool |
a919ff14 | 872 | chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, |
ef9348c8 CML |
873 | int target, int refclk, intel_clock_t *match_clock, |
874 | intel_clock_t *best_clock) | |
875 | { | |
a919ff14 | 876 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 877 | unsigned int best_error_ppm; |
ef9348c8 CML |
878 | intel_clock_t clock; |
879 | uint64_t m2; | |
880 | int found = false; | |
881 | ||
882 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 883 | best_error_ppm = 1000000; |
ef9348c8 CML |
884 | |
885 | /* | |
886 | * Based on hardware doc, the n always set to 1, and m1 always | |
887 | * set to 2. If requires to support 200Mhz refclk, we need to | |
888 | * revisit this because n may not 1 anymore. | |
889 | */ | |
890 | clock.n = 1, clock.m1 = 2; | |
891 | target *= 5; /* fast clock */ | |
892 | ||
893 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
894 | for (clock.p2 = limit->p2.p2_fast; | |
895 | clock.p2 >= limit->p2.p2_slow; | |
896 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 897 | unsigned int error_ppm; |
ef9348c8 CML |
898 | |
899 | clock.p = clock.p1 * clock.p2; | |
900 | ||
901 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
902 | clock.n) << 22, refclk * clock.m1); | |
903 | ||
904 | if (m2 > INT_MAX/clock.m1) | |
905 | continue; | |
906 | ||
907 | clock.m2 = m2; | |
908 | ||
909 | chv_clock(refclk, &clock); | |
910 | ||
911 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
912 | continue; | |
913 | ||
9ca3ba01 ID |
914 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
915 | best_error_ppm, &error_ppm)) | |
916 | continue; | |
917 | ||
918 | *best_clock = clock; | |
919 | best_error_ppm = error_ppm; | |
920 | found = true; | |
ef9348c8 CML |
921 | } |
922 | } | |
923 | ||
924 | return found; | |
925 | } | |
926 | ||
20ddf665 VS |
927 | bool intel_crtc_active(struct drm_crtc *crtc) |
928 | { | |
929 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
930 | ||
931 | /* Be paranoid as we can arrive here with only partial | |
932 | * state retrieved from the hardware during setup. | |
933 | * | |
241bfc38 | 934 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
935 | * as Haswell has gained clock readout/fastboot support. |
936 | * | |
66e514c1 | 937 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 938 | * properly reconstruct framebuffers. |
c3d1f436 MR |
939 | * |
940 | * FIXME: The intel_crtc->active here should be switched to | |
941 | * crtc->state->active once we have proper CRTC states wired up | |
942 | * for atomic. | |
20ddf665 | 943 | */ |
c3d1f436 | 944 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 945 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
946 | } |
947 | ||
a5c961d1 PZ |
948 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
949 | enum pipe pipe) | |
950 | { | |
951 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
952 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
953 | ||
6e3c9717 | 954 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
955 | } |
956 | ||
fbf49ea2 VS |
957 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
958 | { | |
959 | struct drm_i915_private *dev_priv = dev->dev_private; | |
960 | u32 reg = PIPEDSL(pipe); | |
961 | u32 line1, line2; | |
962 | u32 line_mask; | |
963 | ||
964 | if (IS_GEN2(dev)) | |
965 | line_mask = DSL_LINEMASK_GEN2; | |
966 | else | |
967 | line_mask = DSL_LINEMASK_GEN3; | |
968 | ||
969 | line1 = I915_READ(reg) & line_mask; | |
970 | mdelay(5); | |
971 | line2 = I915_READ(reg) & line_mask; | |
972 | ||
973 | return line1 == line2; | |
974 | } | |
975 | ||
ab7ad7f6 KP |
976 | /* |
977 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 978 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
979 | * |
980 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
981 | * spinning on the vblank interrupt status bit, since we won't actually | |
982 | * see an interrupt when the pipe is disabled. | |
983 | * | |
ab7ad7f6 KP |
984 | * On Gen4 and above: |
985 | * wait for the pipe register state bit to turn off | |
986 | * | |
987 | * Otherwise: | |
988 | * wait for the display line value to settle (it usually | |
989 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 990 | * |
9d0498a2 | 991 | */ |
575f7ab7 | 992 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 993 | { |
575f7ab7 | 994 | struct drm_device *dev = crtc->base.dev; |
9d0498a2 | 995 | struct drm_i915_private *dev_priv = dev->dev_private; |
6e3c9717 | 996 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 997 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
998 | |
999 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 1000 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1001 | |
1002 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
1003 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1004 | 100)) | |
284637d9 | 1005 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1006 | } else { |
ab7ad7f6 | 1007 | /* Wait for the display line to settle */ |
fbf49ea2 | 1008 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1009 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1010 | } |
79e53945 JB |
1011 | } |
1012 | ||
b0ea7d37 DL |
1013 | /* |
1014 | * ibx_digital_port_connected - is the specified port connected? | |
1015 | * @dev_priv: i915 private structure | |
1016 | * @port: the port to test | |
1017 | * | |
1018 | * Returns true if @port is connected, false otherwise. | |
1019 | */ | |
1020 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, | |
1021 | struct intel_digital_port *port) | |
1022 | { | |
1023 | u32 bit; | |
1024 | ||
c36346e3 | 1025 | if (HAS_PCH_IBX(dev_priv->dev)) { |
eba905b2 | 1026 | switch (port->port) { |
c36346e3 DL |
1027 | case PORT_B: |
1028 | bit = SDE_PORTB_HOTPLUG; | |
1029 | break; | |
1030 | case PORT_C: | |
1031 | bit = SDE_PORTC_HOTPLUG; | |
1032 | break; | |
1033 | case PORT_D: | |
1034 | bit = SDE_PORTD_HOTPLUG; | |
1035 | break; | |
1036 | default: | |
1037 | return true; | |
1038 | } | |
1039 | } else { | |
eba905b2 | 1040 | switch (port->port) { |
c36346e3 DL |
1041 | case PORT_B: |
1042 | bit = SDE_PORTB_HOTPLUG_CPT; | |
1043 | break; | |
1044 | case PORT_C: | |
1045 | bit = SDE_PORTC_HOTPLUG_CPT; | |
1046 | break; | |
1047 | case PORT_D: | |
1048 | bit = SDE_PORTD_HOTPLUG_CPT; | |
1049 | break; | |
1050 | default: | |
1051 | return true; | |
1052 | } | |
b0ea7d37 DL |
1053 | } |
1054 | ||
1055 | return I915_READ(SDEISR) & bit; | |
1056 | } | |
1057 | ||
b24e7179 JB |
1058 | static const char *state_string(bool enabled) |
1059 | { | |
1060 | return enabled ? "on" : "off"; | |
1061 | } | |
1062 | ||
1063 | /* Only for pre-ILK configs */ | |
55607e8a DV |
1064 | void assert_pll(struct drm_i915_private *dev_priv, |
1065 | enum pipe pipe, bool state) | |
b24e7179 JB |
1066 | { |
1067 | int reg; | |
1068 | u32 val; | |
1069 | bool cur_state; | |
1070 | ||
1071 | reg = DPLL(pipe); | |
1072 | val = I915_READ(reg); | |
1073 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
e2c719b7 | 1074 | I915_STATE_WARN(cur_state != state, |
b24e7179 JB |
1075 | "PLL state assertion failure (expected %s, current %s)\n", |
1076 | state_string(state), state_string(cur_state)); | |
1077 | } | |
b24e7179 | 1078 | |
23538ef1 JN |
1079 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1080 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1081 | { | |
1082 | u32 val; | |
1083 | bool cur_state; | |
1084 | ||
1085 | mutex_lock(&dev_priv->dpio_lock); | |
1086 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
1087 | mutex_unlock(&dev_priv->dpio_lock); | |
1088 | ||
1089 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1090 | I915_STATE_WARN(cur_state != state, |
23538ef1 JN |
1091 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
1092 | state_string(state), state_string(cur_state)); | |
1093 | } | |
1094 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1095 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1096 | ||
55607e8a | 1097 | struct intel_shared_dpll * |
e2b78267 DV |
1098 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1099 | { | |
1100 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1101 | ||
6e3c9717 | 1102 | if (crtc->config->shared_dpll < 0) |
e2b78267 DV |
1103 | return NULL; |
1104 | ||
6e3c9717 | 1105 | return &dev_priv->shared_dplls[crtc->config->shared_dpll]; |
e2b78267 DV |
1106 | } |
1107 | ||
040484af | 1108 | /* For ILK+ */ |
55607e8a DV |
1109 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1110 | struct intel_shared_dpll *pll, | |
1111 | bool state) | |
040484af | 1112 | { |
040484af | 1113 | bool cur_state; |
5358901f | 1114 | struct intel_dpll_hw_state hw_state; |
040484af | 1115 | |
92b27b08 | 1116 | if (WARN (!pll, |
46edb027 | 1117 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 1118 | return; |
ee7b9f93 | 1119 | |
5358901f | 1120 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
e2c719b7 | 1121 | I915_STATE_WARN(cur_state != state, |
5358901f DV |
1122 | "%s assertion failure (expected %s, current %s)\n", |
1123 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 1124 | } |
040484af JB |
1125 | |
1126 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1127 | enum pipe pipe, bool state) | |
1128 | { | |
1129 | int reg; | |
1130 | u32 val; | |
1131 | bool cur_state; | |
ad80a810 PZ |
1132 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1133 | pipe); | |
040484af | 1134 | |
affa9354 PZ |
1135 | if (HAS_DDI(dev_priv->dev)) { |
1136 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 1137 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 1138 | val = I915_READ(reg); |
ad80a810 | 1139 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
1140 | } else { |
1141 | reg = FDI_TX_CTL(pipe); | |
1142 | val = I915_READ(reg); | |
1143 | cur_state = !!(val & FDI_TX_ENABLE); | |
1144 | } | |
e2c719b7 | 1145 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1146 | "FDI TX state assertion failure (expected %s, current %s)\n", |
1147 | state_string(state), state_string(cur_state)); | |
1148 | } | |
1149 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1150 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1151 | ||
1152 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1153 | enum pipe pipe, bool state) | |
1154 | { | |
1155 | int reg; | |
1156 | u32 val; | |
1157 | bool cur_state; | |
1158 | ||
d63fa0dc PZ |
1159 | reg = FDI_RX_CTL(pipe); |
1160 | val = I915_READ(reg); | |
1161 | cur_state = !!(val & FDI_RX_ENABLE); | |
e2c719b7 | 1162 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1163 | "FDI RX state assertion failure (expected %s, current %s)\n", |
1164 | state_string(state), state_string(cur_state)); | |
1165 | } | |
1166 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1167 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1168 | ||
1169 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1170 | enum pipe pipe) | |
1171 | { | |
1172 | int reg; | |
1173 | u32 val; | |
1174 | ||
1175 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1176 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1177 | return; |
1178 | ||
bf507ef7 | 1179 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1180 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1181 | return; |
1182 | ||
040484af JB |
1183 | reg = FDI_TX_CTL(pipe); |
1184 | val = I915_READ(reg); | |
e2c719b7 | 1185 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1186 | } |
1187 | ||
55607e8a DV |
1188 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1189 | enum pipe pipe, bool state) | |
040484af JB |
1190 | { |
1191 | int reg; | |
1192 | u32 val; | |
55607e8a | 1193 | bool cur_state; |
040484af JB |
1194 | |
1195 | reg = FDI_RX_CTL(pipe); | |
1196 | val = I915_READ(reg); | |
55607e8a | 1197 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1198 | I915_STATE_WARN(cur_state != state, |
55607e8a DV |
1199 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
1200 | state_string(state), state_string(cur_state)); | |
040484af JB |
1201 | } |
1202 | ||
b680c37a DV |
1203 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1204 | enum pipe pipe) | |
ea0760cf | 1205 | { |
bedd4dba JN |
1206 | struct drm_device *dev = dev_priv->dev; |
1207 | int pp_reg; | |
ea0760cf JB |
1208 | u32 val; |
1209 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1210 | bool locked = true; |
ea0760cf | 1211 | |
bedd4dba JN |
1212 | if (WARN_ON(HAS_DDI(dev))) |
1213 | return; | |
1214 | ||
1215 | if (HAS_PCH_SPLIT(dev)) { | |
1216 | u32 port_sel; | |
1217 | ||
ea0760cf | 1218 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1219 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1220 | ||
1221 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1222 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1223 | panel_pipe = PIPE_B; | |
1224 | /* XXX: else fix for eDP */ | |
1225 | } else if (IS_VALLEYVIEW(dev)) { | |
1226 | /* presumably write lock depends on pipe, not port select */ | |
1227 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1228 | panel_pipe = pipe; | |
ea0760cf JB |
1229 | } else { |
1230 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1231 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1232 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1233 | } |
1234 | ||
1235 | val = I915_READ(pp_reg); | |
1236 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1237 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1238 | locked = false; |
1239 | ||
e2c719b7 | 1240 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1241 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1242 | pipe_name(pipe)); |
ea0760cf JB |
1243 | } |
1244 | ||
93ce0ba6 JN |
1245 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1246 | enum pipe pipe, bool state) | |
1247 | { | |
1248 | struct drm_device *dev = dev_priv->dev; | |
1249 | bool cur_state; | |
1250 | ||
d9d82081 | 1251 | if (IS_845G(dev) || IS_I865G(dev)) |
93ce0ba6 | 1252 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; |
d9d82081 | 1253 | else |
5efb3e28 | 1254 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1255 | |
e2c719b7 | 1256 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 JN |
1257 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
1258 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1259 | } | |
1260 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1261 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1262 | ||
b840d907 JB |
1263 | void assert_pipe(struct drm_i915_private *dev_priv, |
1264 | enum pipe pipe, bool state) | |
b24e7179 JB |
1265 | { |
1266 | int reg; | |
1267 | u32 val; | |
63d7bbe9 | 1268 | bool cur_state; |
702e7a56 PZ |
1269 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1270 | pipe); | |
b24e7179 | 1271 | |
b6b5d049 VS |
1272 | /* if we need the pipe quirk it must be always on */ |
1273 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1274 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1275 | state = true; |
1276 | ||
f458ebbc | 1277 | if (!intel_display_power_is_enabled(dev_priv, |
b97186f0 | 1278 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
69310161 PZ |
1279 | cur_state = false; |
1280 | } else { | |
1281 | reg = PIPECONF(cpu_transcoder); | |
1282 | val = I915_READ(reg); | |
1283 | cur_state = !!(val & PIPECONF_ENABLE); | |
1284 | } | |
1285 | ||
e2c719b7 | 1286 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1287 | "pipe %c assertion failure (expected %s, current %s)\n", |
9db4a9c7 | 1288 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1289 | } |
1290 | ||
931872fc CW |
1291 | static void assert_plane(struct drm_i915_private *dev_priv, |
1292 | enum plane plane, bool state) | |
b24e7179 JB |
1293 | { |
1294 | int reg; | |
1295 | u32 val; | |
931872fc | 1296 | bool cur_state; |
b24e7179 JB |
1297 | |
1298 | reg = DSPCNTR(plane); | |
1299 | val = I915_READ(reg); | |
931872fc | 1300 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1301 | I915_STATE_WARN(cur_state != state, |
931872fc CW |
1302 | "plane %c assertion failure (expected %s, current %s)\n", |
1303 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1304 | } |
1305 | ||
931872fc CW |
1306 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1307 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1308 | ||
b24e7179 JB |
1309 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1310 | enum pipe pipe) | |
1311 | { | |
653e1026 | 1312 | struct drm_device *dev = dev_priv->dev; |
b24e7179 JB |
1313 | int reg, i; |
1314 | u32 val; | |
1315 | int cur_pipe; | |
1316 | ||
653e1026 VS |
1317 | /* Primary planes are fixed to pipes on gen4+ */ |
1318 | if (INTEL_INFO(dev)->gen >= 4) { | |
28c05794 AJ |
1319 | reg = DSPCNTR(pipe); |
1320 | val = I915_READ(reg); | |
e2c719b7 | 1321 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1322 | "plane %c assertion failure, should be disabled but not\n", |
1323 | plane_name(pipe)); | |
19ec1358 | 1324 | return; |
28c05794 | 1325 | } |
19ec1358 | 1326 | |
b24e7179 | 1327 | /* Need to check both planes against the pipe */ |
055e393f | 1328 | for_each_pipe(dev_priv, i) { |
b24e7179 JB |
1329 | reg = DSPCNTR(i); |
1330 | val = I915_READ(reg); | |
1331 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1332 | DISPPLANE_SEL_PIPE_SHIFT; | |
e2c719b7 | 1333 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1334 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1335 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1336 | } |
1337 | } | |
1338 | ||
19332d7a JB |
1339 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1340 | enum pipe pipe) | |
1341 | { | |
20674eef | 1342 | struct drm_device *dev = dev_priv->dev; |
1fe47785 | 1343 | int reg, sprite; |
19332d7a JB |
1344 | u32 val; |
1345 | ||
7feb8b88 | 1346 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1347 | for_each_sprite(dev_priv, pipe, sprite) { |
7feb8b88 | 1348 | val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1349 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1350 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1351 | sprite, pipe_name(pipe)); | |
1352 | } | |
1353 | } else if (IS_VALLEYVIEW(dev)) { | |
3bdcfc0c | 1354 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 1355 | reg = SPCNTR(pipe, sprite); |
20674eef | 1356 | val = I915_READ(reg); |
e2c719b7 | 1357 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1358 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1359 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1360 | } |
1361 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
1362 | reg = SPRCTL(pipe); | |
19332d7a | 1363 | val = I915_READ(reg); |
e2c719b7 | 1364 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1365 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1366 | plane_name(pipe), pipe_name(pipe)); |
1367 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1368 | reg = DVSCNTR(pipe); | |
19332d7a | 1369 | val = I915_READ(reg); |
e2c719b7 | 1370 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1371 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1372 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1373 | } |
1374 | } | |
1375 | ||
08c71e5e VS |
1376 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1377 | { | |
e2c719b7 | 1378 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1379 | drm_crtc_vblank_put(crtc); |
1380 | } | |
1381 | ||
89eff4be | 1382 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1383 | { |
1384 | u32 val; | |
1385 | bool enabled; | |
1386 | ||
e2c719b7 | 1387 | I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1388 | |
92f2584a JB |
1389 | val = I915_READ(PCH_DREF_CONTROL); |
1390 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1391 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
e2c719b7 | 1392 | I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
92f2584a JB |
1393 | } |
1394 | ||
ab9412ba DV |
1395 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1396 | enum pipe pipe) | |
92f2584a JB |
1397 | { |
1398 | int reg; | |
1399 | u32 val; | |
1400 | bool enabled; | |
1401 | ||
ab9412ba | 1402 | reg = PCH_TRANSCONF(pipe); |
92f2584a JB |
1403 | val = I915_READ(reg); |
1404 | enabled = !!(val & TRANS_ENABLE); | |
e2c719b7 | 1405 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1406 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1407 | pipe_name(pipe)); | |
92f2584a JB |
1408 | } |
1409 | ||
4e634389 KP |
1410 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1411 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1412 | { |
1413 | if ((val & DP_PORT_EN) == 0) | |
1414 | return false; | |
1415 | ||
1416 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1417 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1418 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1419 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1420 | return false; | |
44f37d1f CML |
1421 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1422 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1423 | return false; | |
f0575e92 KP |
1424 | } else { |
1425 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1426 | return false; | |
1427 | } | |
1428 | return true; | |
1429 | } | |
1430 | ||
1519b995 KP |
1431 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1432 | enum pipe pipe, u32 val) | |
1433 | { | |
dc0fa718 | 1434 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1435 | return false; |
1436 | ||
1437 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1438 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1439 | return false; |
44f37d1f CML |
1440 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1441 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1442 | return false; | |
1519b995 | 1443 | } else { |
dc0fa718 | 1444 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1445 | return false; |
1446 | } | |
1447 | return true; | |
1448 | } | |
1449 | ||
1450 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1451 | enum pipe pipe, u32 val) | |
1452 | { | |
1453 | if ((val & LVDS_PORT_EN) == 0) | |
1454 | return false; | |
1455 | ||
1456 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1457 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1458 | return false; | |
1459 | } else { | |
1460 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1461 | return false; | |
1462 | } | |
1463 | return true; | |
1464 | } | |
1465 | ||
1466 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1467 | enum pipe pipe, u32 val) | |
1468 | { | |
1469 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1470 | return false; | |
1471 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1472 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1473 | return false; | |
1474 | } else { | |
1475 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1476 | return false; | |
1477 | } | |
1478 | return true; | |
1479 | } | |
1480 | ||
291906f1 | 1481 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1482 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1483 | { |
47a05eca | 1484 | u32 val = I915_READ(reg); |
e2c719b7 | 1485 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1486 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1487 | reg, pipe_name(pipe)); |
de9a35ab | 1488 | |
e2c719b7 | 1489 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1490 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1491 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1492 | } |
1493 | ||
1494 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1495 | enum pipe pipe, int reg) | |
1496 | { | |
47a05eca | 1497 | u32 val = I915_READ(reg); |
e2c719b7 | 1498 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1499 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1500 | reg, pipe_name(pipe)); |
de9a35ab | 1501 | |
e2c719b7 | 1502 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1503 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1504 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1505 | } |
1506 | ||
1507 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1508 | enum pipe pipe) | |
1509 | { | |
1510 | int reg; | |
1511 | u32 val; | |
291906f1 | 1512 | |
f0575e92 KP |
1513 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1514 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1515 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1516 | |
1517 | reg = PCH_ADPA; | |
1518 | val = I915_READ(reg); | |
e2c719b7 | 1519 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1520 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1521 | pipe_name(pipe)); |
291906f1 JB |
1522 | |
1523 | reg = PCH_LVDS; | |
1524 | val = I915_READ(reg); | |
e2c719b7 | 1525 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1526 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1527 | pipe_name(pipe)); |
291906f1 | 1528 | |
e2debe91 PZ |
1529 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1530 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1531 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1532 | } |
1533 | ||
40e9cf64 JB |
1534 | static void intel_init_dpio(struct drm_device *dev) |
1535 | { | |
1536 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1537 | ||
1538 | if (!IS_VALLEYVIEW(dev)) | |
1539 | return; | |
1540 | ||
a09caddd CML |
1541 | /* |
1542 | * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), | |
1543 | * CHV x1 PHY (DP/HDMI D) | |
1544 | * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) | |
1545 | */ | |
1546 | if (IS_CHERRYVIEW(dev)) { | |
1547 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; | |
1548 | DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO; | |
1549 | } else { | |
1550 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; | |
1551 | } | |
5382f5f3 JB |
1552 | } |
1553 | ||
d288f65f | 1554 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1555 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1556 | { |
426115cf DV |
1557 | struct drm_device *dev = crtc->base.dev; |
1558 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1559 | int reg = DPLL(crtc->pipe); | |
d288f65f | 1560 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
87442f73 | 1561 | |
426115cf | 1562 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 DV |
1563 | |
1564 | /* No really, not for ILK+ */ | |
1565 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
1566 | ||
1567 | /* PLL is protected by panel, make sure we can write it */ | |
6a9e7363 | 1568 | if (IS_MOBILE(dev_priv->dev)) |
426115cf | 1569 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1570 | |
426115cf DV |
1571 | I915_WRITE(reg, dpll); |
1572 | POSTING_READ(reg); | |
1573 | udelay(150); | |
1574 | ||
1575 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1576 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1577 | ||
d288f65f | 1578 | I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); |
426115cf | 1579 | POSTING_READ(DPLL_MD(crtc->pipe)); |
87442f73 DV |
1580 | |
1581 | /* We do this three times for luck */ | |
426115cf | 1582 | I915_WRITE(reg, dpll); |
87442f73 DV |
1583 | POSTING_READ(reg); |
1584 | udelay(150); /* wait for warmup */ | |
426115cf | 1585 | I915_WRITE(reg, dpll); |
87442f73 DV |
1586 | POSTING_READ(reg); |
1587 | udelay(150); /* wait for warmup */ | |
426115cf | 1588 | I915_WRITE(reg, dpll); |
87442f73 DV |
1589 | POSTING_READ(reg); |
1590 | udelay(150); /* wait for warmup */ | |
1591 | } | |
1592 | ||
d288f65f | 1593 | static void chv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1594 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
1595 | { |
1596 | struct drm_device *dev = crtc->base.dev; | |
1597 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1598 | int pipe = crtc->pipe; | |
1599 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1600 | u32 tmp; |
1601 | ||
1602 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1603 | ||
1604 | BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); | |
1605 | ||
1606 | mutex_lock(&dev_priv->dpio_lock); | |
1607 | ||
1608 | /* Enable back the 10bit clock to display controller */ | |
1609 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1610 | tmp |= DPIO_DCLKP_EN; | |
1611 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1612 | ||
1613 | /* | |
1614 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1615 | */ | |
1616 | udelay(1); | |
1617 | ||
1618 | /* Enable PLL */ | |
d288f65f | 1619 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1620 | |
1621 | /* Check PLL is locked */ | |
a11b0703 | 1622 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1623 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1624 | ||
a11b0703 | 1625 | /* not sure when this should be written */ |
d288f65f | 1626 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
a11b0703 VS |
1627 | POSTING_READ(DPLL_MD(pipe)); |
1628 | ||
9d556c99 CML |
1629 | mutex_unlock(&dev_priv->dpio_lock); |
1630 | } | |
1631 | ||
1c4e0274 VS |
1632 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1633 | { | |
1634 | struct intel_crtc *crtc; | |
1635 | int count = 0; | |
1636 | ||
1637 | for_each_intel_crtc(dev, crtc) | |
1638 | count += crtc->active && | |
409ee761 | 1639 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
1c4e0274 VS |
1640 | |
1641 | return count; | |
1642 | } | |
1643 | ||
66e3d5c0 | 1644 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1645 | { |
66e3d5c0 DV |
1646 | struct drm_device *dev = crtc->base.dev; |
1647 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1648 | int reg = DPLL(crtc->pipe); | |
6e3c9717 | 1649 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1650 | |
66e3d5c0 | 1651 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1652 | |
63d7bbe9 | 1653 | /* No really, not for ILK+ */ |
3d13ef2e | 1654 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1655 | |
1656 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1657 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1658 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1659 | |
1c4e0274 VS |
1660 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1661 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1662 | /* | |
1663 | * It appears to be important that we don't enable this | |
1664 | * for the current pipe before otherwise configuring the | |
1665 | * PLL. No idea how this should be handled if multiple | |
1666 | * DVO outputs are enabled simultaneosly. | |
1667 | */ | |
1668 | dpll |= DPLL_DVO_2X_MODE; | |
1669 | I915_WRITE(DPLL(!crtc->pipe), | |
1670 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1671 | } | |
66e3d5c0 DV |
1672 | |
1673 | /* Wait for the clocks to stabilize. */ | |
1674 | POSTING_READ(reg); | |
1675 | udelay(150); | |
1676 | ||
1677 | if (INTEL_INFO(dev)->gen >= 4) { | |
1678 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1679 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1680 | } else { |
1681 | /* The pixel multiplier can only be updated once the | |
1682 | * DPLL is enabled and the clocks are stable. | |
1683 | * | |
1684 | * So write it again. | |
1685 | */ | |
1686 | I915_WRITE(reg, dpll); | |
1687 | } | |
63d7bbe9 JB |
1688 | |
1689 | /* We do this three times for luck */ | |
66e3d5c0 | 1690 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1691 | POSTING_READ(reg); |
1692 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1693 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1694 | POSTING_READ(reg); |
1695 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1696 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1697 | POSTING_READ(reg); |
1698 | udelay(150); /* wait for warmup */ | |
1699 | } | |
1700 | ||
1701 | /** | |
50b44a44 | 1702 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1703 | * @dev_priv: i915 private structure |
1704 | * @pipe: pipe PLL to disable | |
1705 | * | |
1706 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1707 | * | |
1708 | * Note! This is for pre-ILK only. | |
1709 | */ | |
1c4e0274 | 1710 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1711 | { |
1c4e0274 VS |
1712 | struct drm_device *dev = crtc->base.dev; |
1713 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1714 | enum pipe pipe = crtc->pipe; | |
1715 | ||
1716 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1717 | if (IS_I830(dev) && | |
409ee761 | 1718 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
1c4e0274 VS |
1719 | intel_num_dvo_pipes(dev) == 1) { |
1720 | I915_WRITE(DPLL(PIPE_B), | |
1721 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1722 | I915_WRITE(DPLL(PIPE_A), | |
1723 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1724 | } | |
1725 | ||
b6b5d049 VS |
1726 | /* Don't disable pipe or pipe PLLs if needed */ |
1727 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1728 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1729 | return; |
1730 | ||
1731 | /* Make sure the pipe isn't still relying on us */ | |
1732 | assert_pipe_disabled(dev_priv, pipe); | |
1733 | ||
50b44a44 DV |
1734 | I915_WRITE(DPLL(pipe), 0); |
1735 | POSTING_READ(DPLL(pipe)); | |
63d7bbe9 JB |
1736 | } |
1737 | ||
f6071166 JB |
1738 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1739 | { | |
1740 | u32 val = 0; | |
1741 | ||
1742 | /* Make sure the pipe isn't still relying on us */ | |
1743 | assert_pipe_disabled(dev_priv, pipe); | |
1744 | ||
e5cbfbfb ID |
1745 | /* |
1746 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1747 | * The latter is needed for VGA hotplug / manual detection. | |
1748 | */ | |
f6071166 | 1749 | if (pipe == PIPE_B) |
e5cbfbfb | 1750 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; |
f6071166 JB |
1751 | I915_WRITE(DPLL(pipe), val); |
1752 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1753 | |
1754 | } | |
1755 | ||
1756 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1757 | { | |
d752048d | 1758 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1759 | u32 val; |
1760 | ||
a11b0703 VS |
1761 | /* Make sure the pipe isn't still relying on us */ |
1762 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1763 | |
a11b0703 | 1764 | /* Set PLL en = 0 */ |
d17ec4ce | 1765 | val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV; |
a11b0703 VS |
1766 | if (pipe != PIPE_A) |
1767 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1768 | I915_WRITE(DPLL(pipe), val); | |
1769 | POSTING_READ(DPLL(pipe)); | |
d752048d VS |
1770 | |
1771 | mutex_lock(&dev_priv->dpio_lock); | |
1772 | ||
1773 | /* Disable 10bit clock to display controller */ | |
1774 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1775 | val &= ~DPIO_DCLKP_EN; | |
1776 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1777 | ||
61407f6d VS |
1778 | /* disable left/right clock distribution */ |
1779 | if (pipe != PIPE_B) { | |
1780 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
1781 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
1782 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
1783 | } else { | |
1784 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
1785 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
1786 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
1787 | } | |
1788 | ||
d752048d | 1789 | mutex_unlock(&dev_priv->dpio_lock); |
f6071166 JB |
1790 | } |
1791 | ||
e4607fcf CML |
1792 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
1793 | struct intel_digital_port *dport) | |
89b667f8 JB |
1794 | { |
1795 | u32 port_mask; | |
00fc31b7 | 1796 | int dpll_reg; |
89b667f8 | 1797 | |
e4607fcf CML |
1798 | switch (dport->port) { |
1799 | case PORT_B: | |
89b667f8 | 1800 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1801 | dpll_reg = DPLL(0); |
e4607fcf CML |
1802 | break; |
1803 | case PORT_C: | |
89b667f8 | 1804 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 CML |
1805 | dpll_reg = DPLL(0); |
1806 | break; | |
1807 | case PORT_D: | |
1808 | port_mask = DPLL_PORTD_READY_MASK; | |
1809 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1810 | break; |
1811 | default: | |
1812 | BUG(); | |
1813 | } | |
89b667f8 | 1814 | |
00fc31b7 | 1815 | if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000)) |
89b667f8 | 1816 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", |
00fc31b7 | 1817 | port_name(dport->port), I915_READ(dpll_reg)); |
89b667f8 JB |
1818 | } |
1819 | ||
b14b1055 DV |
1820 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1821 | { | |
1822 | struct drm_device *dev = crtc->base.dev; | |
1823 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1824 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
1825 | ||
be19f0ff CW |
1826 | if (WARN_ON(pll == NULL)) |
1827 | return; | |
1828 | ||
3e369b76 | 1829 | WARN_ON(!pll->config.crtc_mask); |
b14b1055 DV |
1830 | if (pll->active == 0) { |
1831 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
1832 | WARN_ON(pll->on); | |
1833 | assert_shared_dpll_disabled(dev_priv, pll); | |
1834 | ||
1835 | pll->mode_set(dev_priv, pll); | |
1836 | } | |
1837 | } | |
1838 | ||
92f2584a | 1839 | /** |
85b3894f | 1840 | * intel_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1841 | * @dev_priv: i915 private structure |
1842 | * @pipe: pipe PLL to enable | |
1843 | * | |
1844 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1845 | * drives the transcoder clock. | |
1846 | */ | |
85b3894f | 1847 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1848 | { |
3d13ef2e DL |
1849 | struct drm_device *dev = crtc->base.dev; |
1850 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1851 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1852 | |
87a875bb | 1853 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1854 | return; |
1855 | ||
3e369b76 | 1856 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1857 | return; |
ee7b9f93 | 1858 | |
74dd6928 | 1859 | DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n", |
46edb027 | 1860 | pll->name, pll->active, pll->on, |
e2b78267 | 1861 | crtc->base.base.id); |
92f2584a | 1862 | |
cdbd2316 DV |
1863 | if (pll->active++) { |
1864 | WARN_ON(!pll->on); | |
e9d6944e | 1865 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1866 | return; |
1867 | } | |
f4a091c7 | 1868 | WARN_ON(pll->on); |
ee7b9f93 | 1869 | |
bd2bb1b9 PZ |
1870 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
1871 | ||
46edb027 | 1872 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1873 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1874 | pll->on = true; |
92f2584a JB |
1875 | } |
1876 | ||
f6daaec2 | 1877 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1878 | { |
3d13ef2e DL |
1879 | struct drm_device *dev = crtc->base.dev; |
1880 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1881 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1882 | |
92f2584a | 1883 | /* PCH only available on ILK+ */ |
3d13ef2e | 1884 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
87a875bb | 1885 | if (WARN_ON(pll == NULL)) |
ee7b9f93 | 1886 | return; |
92f2584a | 1887 | |
3e369b76 | 1888 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1889 | return; |
7a419866 | 1890 | |
46edb027 DV |
1891 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1892 | pll->name, pll->active, pll->on, | |
e2b78267 | 1893 | crtc->base.base.id); |
7a419866 | 1894 | |
48da64a8 | 1895 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1896 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1897 | return; |
1898 | } | |
1899 | ||
e9d6944e | 1900 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1901 | WARN_ON(!pll->on); |
cdbd2316 | 1902 | if (--pll->active) |
7a419866 | 1903 | return; |
ee7b9f93 | 1904 | |
46edb027 | 1905 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1906 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1907 | pll->on = false; |
bd2bb1b9 PZ |
1908 | |
1909 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
92f2584a JB |
1910 | } |
1911 | ||
b8a4f404 PZ |
1912 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1913 | enum pipe pipe) | |
040484af | 1914 | { |
23670b32 | 1915 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1916 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1917 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
23670b32 | 1918 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1919 | |
1920 | /* PCH only available on ILK+ */ | |
55522f37 | 1921 | BUG_ON(!HAS_PCH_SPLIT(dev)); |
040484af JB |
1922 | |
1923 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1924 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1925 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1926 | |
1927 | /* FDI must be feeding us bits for PCH ports */ | |
1928 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1929 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1930 | ||
23670b32 DV |
1931 | if (HAS_PCH_CPT(dev)) { |
1932 | /* Workaround: Set the timing override bit before enabling the | |
1933 | * pch transcoder. */ | |
1934 | reg = TRANS_CHICKEN2(pipe); | |
1935 | val = I915_READ(reg); | |
1936 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1937 | I915_WRITE(reg, val); | |
59c859d6 | 1938 | } |
23670b32 | 1939 | |
ab9412ba | 1940 | reg = PCH_TRANSCONF(pipe); |
040484af | 1941 | val = I915_READ(reg); |
5f7f726d | 1942 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1943 | |
1944 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1945 | /* | |
1946 | * make the BPC in transcoder be consistent with | |
1947 | * that in pipeconf reg. | |
1948 | */ | |
dfd07d72 DV |
1949 | val &= ~PIPECONF_BPC_MASK; |
1950 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1951 | } |
5f7f726d PZ |
1952 | |
1953 | val &= ~TRANS_INTERLACE_MASK; | |
1954 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 | 1955 | if (HAS_PCH_IBX(dev_priv->dev) && |
409ee761 | 1956 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
1957 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1958 | else | |
1959 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1960 | else |
1961 | val |= TRANS_PROGRESSIVE; | |
1962 | ||
040484af JB |
1963 | I915_WRITE(reg, val | TRANS_ENABLE); |
1964 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 1965 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1966 | } |
1967 | ||
8fb033d7 | 1968 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1969 | enum transcoder cpu_transcoder) |
040484af | 1970 | { |
8fb033d7 | 1971 | u32 val, pipeconf_val; |
8fb033d7 PZ |
1972 | |
1973 | /* PCH only available on ILK+ */ | |
55522f37 | 1974 | BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev)); |
8fb033d7 | 1975 | |
8fb033d7 | 1976 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1977 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1978 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1979 | |
223a6fdf PZ |
1980 | /* Workaround: set timing override bit. */ |
1981 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1982 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
1983 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1984 | ||
25f3ef11 | 1985 | val = TRANS_ENABLE; |
937bb610 | 1986 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1987 | |
9a76b1c6 PZ |
1988 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1989 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1990 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1991 | else |
1992 | val |= TRANS_PROGRESSIVE; | |
1993 | ||
ab9412ba DV |
1994 | I915_WRITE(LPT_TRANSCONF, val); |
1995 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 1996 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1997 | } |
1998 | ||
b8a4f404 PZ |
1999 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
2000 | enum pipe pipe) | |
040484af | 2001 | { |
23670b32 DV |
2002 | struct drm_device *dev = dev_priv->dev; |
2003 | uint32_t reg, val; | |
040484af JB |
2004 | |
2005 | /* FDI relies on the transcoder */ | |
2006 | assert_fdi_tx_disabled(dev_priv, pipe); | |
2007 | assert_fdi_rx_disabled(dev_priv, pipe); | |
2008 | ||
291906f1 JB |
2009 | /* Ports must be off as well */ |
2010 | assert_pch_ports_disabled(dev_priv, pipe); | |
2011 | ||
ab9412ba | 2012 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
2013 | val = I915_READ(reg); |
2014 | val &= ~TRANS_ENABLE; | |
2015 | I915_WRITE(reg, val); | |
2016 | /* wait for PCH transcoder off, transcoder state */ | |
2017 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 2018 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 DV |
2019 | |
2020 | if (!HAS_PCH_IBX(dev)) { | |
2021 | /* Workaround: Clear the timing override chicken bit again. */ | |
2022 | reg = TRANS_CHICKEN2(pipe); | |
2023 | val = I915_READ(reg); | |
2024 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
2025 | I915_WRITE(reg, val); | |
2026 | } | |
040484af JB |
2027 | } |
2028 | ||
ab4d966c | 2029 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 2030 | { |
8fb033d7 PZ |
2031 | u32 val; |
2032 | ||
ab9412ba | 2033 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 2034 | val &= ~TRANS_ENABLE; |
ab9412ba | 2035 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 2036 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 2037 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 2038 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
2039 | |
2040 | /* Workaround: clear timing override bit. */ | |
2041 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 2042 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 2043 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
2044 | } |
2045 | ||
b24e7179 | 2046 | /** |
309cfea8 | 2047 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 2048 | * @crtc: crtc responsible for the pipe |
b24e7179 | 2049 | * |
0372264a | 2050 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 2051 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 2052 | */ |
e1fdc473 | 2053 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2054 | { |
0372264a PZ |
2055 | struct drm_device *dev = crtc->base.dev; |
2056 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2057 | enum pipe pipe = crtc->pipe; | |
702e7a56 PZ |
2058 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
2059 | pipe); | |
1a240d4d | 2060 | enum pipe pch_transcoder; |
b24e7179 JB |
2061 | int reg; |
2062 | u32 val; | |
2063 | ||
58c6eaa2 | 2064 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 2065 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
2066 | assert_sprites_disabled(dev_priv, pipe); |
2067 | ||
681e5811 | 2068 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
2069 | pch_transcoder = TRANSCODER_A; |
2070 | else | |
2071 | pch_transcoder = pipe; | |
2072 | ||
b24e7179 JB |
2073 | /* |
2074 | * A pipe without a PLL won't actually be able to drive bits from | |
2075 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
2076 | * need the check. | |
2077 | */ | |
2078 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
409ee761 | 2079 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
2080 | assert_dsi_pll_enabled(dev_priv); |
2081 | else | |
2082 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2083 | else { |
6e3c9717 | 2084 | if (crtc->config->has_pch_encoder) { |
040484af | 2085 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2086 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2087 | assert_fdi_tx_pll_enabled(dev_priv, |
2088 | (enum pipe) cpu_transcoder); | |
040484af JB |
2089 | } |
2090 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2091 | } | |
b24e7179 | 2092 | |
702e7a56 | 2093 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2094 | val = I915_READ(reg); |
7ad25d48 | 2095 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
2096 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
2097 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 2098 | return; |
7ad25d48 | 2099 | } |
00d70b15 CW |
2100 | |
2101 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2102 | POSTING_READ(reg); |
b24e7179 JB |
2103 | } |
2104 | ||
2105 | /** | |
309cfea8 | 2106 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2107 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2108 | * |
575f7ab7 VS |
2109 | * Disable the pipe of @crtc, making sure that various hardware |
2110 | * specific requirements are met, if applicable, e.g. plane | |
2111 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2112 | * |
2113 | * Will wait until the pipe has shut down before returning. | |
2114 | */ | |
575f7ab7 | 2115 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2116 | { |
575f7ab7 | 2117 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
6e3c9717 | 2118 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2119 | enum pipe pipe = crtc->pipe; |
b24e7179 JB |
2120 | int reg; |
2121 | u32 val; | |
2122 | ||
2123 | /* | |
2124 | * Make sure planes won't keep trying to pump pixels to us, | |
2125 | * or we might hang the display. | |
2126 | */ | |
2127 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2128 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2129 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2130 | |
702e7a56 | 2131 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2132 | val = I915_READ(reg); |
00d70b15 CW |
2133 | if ((val & PIPECONF_ENABLE) == 0) |
2134 | return; | |
2135 | ||
67adc644 VS |
2136 | /* |
2137 | * Double wide has implications for planes | |
2138 | * so best keep it disabled when not needed. | |
2139 | */ | |
6e3c9717 | 2140 | if (crtc->config->double_wide) |
67adc644 VS |
2141 | val &= ~PIPECONF_DOUBLE_WIDE; |
2142 | ||
2143 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2144 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2145 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2146 | val &= ~PIPECONF_ENABLE; |
2147 | ||
2148 | I915_WRITE(reg, val); | |
2149 | if ((val & PIPECONF_ENABLE) == 0) | |
2150 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2151 | } |
2152 | ||
d74362c9 KP |
2153 | /* |
2154 | * Plane regs are double buffered, going from enabled->disabled needs a | |
2155 | * trigger in order to latch. The display address reg provides this. | |
2156 | */ | |
1dba99f4 VS |
2157 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
2158 | enum plane plane) | |
d74362c9 | 2159 | { |
3d13ef2e DL |
2160 | struct drm_device *dev = dev_priv->dev; |
2161 | u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); | |
1dba99f4 VS |
2162 | |
2163 | I915_WRITE(reg, I915_READ(reg)); | |
2164 | POSTING_READ(reg); | |
d74362c9 KP |
2165 | } |
2166 | ||
b24e7179 | 2167 | /** |
262ca2b0 | 2168 | * intel_enable_primary_hw_plane - enable the primary plane on a given pipe |
fdd508a6 VS |
2169 | * @plane: plane to be enabled |
2170 | * @crtc: crtc for the plane | |
b24e7179 | 2171 | * |
fdd508a6 | 2172 | * Enable @plane on @crtc, making sure that the pipe is running first. |
b24e7179 | 2173 | */ |
fdd508a6 VS |
2174 | static void intel_enable_primary_hw_plane(struct drm_plane *plane, |
2175 | struct drm_crtc *crtc) | |
b24e7179 | 2176 | { |
fdd508a6 VS |
2177 | struct drm_device *dev = plane->dev; |
2178 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2179 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b24e7179 JB |
2180 | |
2181 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
fdd508a6 | 2182 | assert_pipe_enabled(dev_priv, intel_crtc->pipe); |
b24e7179 | 2183 | |
98ec7739 VS |
2184 | if (intel_crtc->primary_enabled) |
2185 | return; | |
0037f71c | 2186 | |
4c445e0e | 2187 | intel_crtc->primary_enabled = true; |
939c2fe8 | 2188 | |
fdd508a6 VS |
2189 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
2190 | crtc->x, crtc->y); | |
33c3b0d1 VS |
2191 | |
2192 | /* | |
2193 | * BDW signals flip done immediately if the plane | |
2194 | * is disabled, even if the plane enable is already | |
2195 | * armed to occur at the next vblank :( | |
2196 | */ | |
2197 | if (IS_BROADWELL(dev)) | |
2198 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
b24e7179 JB |
2199 | } |
2200 | ||
b24e7179 | 2201 | /** |
262ca2b0 | 2202 | * intel_disable_primary_hw_plane - disable the primary hardware plane |
fdd508a6 VS |
2203 | * @plane: plane to be disabled |
2204 | * @crtc: crtc for the plane | |
b24e7179 | 2205 | * |
fdd508a6 | 2206 | * Disable @plane on @crtc, making sure that the pipe is running first. |
b24e7179 | 2207 | */ |
fdd508a6 VS |
2208 | static void intel_disable_primary_hw_plane(struct drm_plane *plane, |
2209 | struct drm_crtc *crtc) | |
b24e7179 | 2210 | { |
fdd508a6 VS |
2211 | struct drm_device *dev = plane->dev; |
2212 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2213 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2214 | ||
32b7eeec MR |
2215 | if (WARN_ON(!intel_crtc->active)) |
2216 | return; | |
b24e7179 | 2217 | |
98ec7739 VS |
2218 | if (!intel_crtc->primary_enabled) |
2219 | return; | |
0037f71c | 2220 | |
4c445e0e | 2221 | intel_crtc->primary_enabled = false; |
939c2fe8 | 2222 | |
fdd508a6 VS |
2223 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
2224 | crtc->x, crtc->y); | |
b24e7179 JB |
2225 | } |
2226 | ||
693db184 CW |
2227 | static bool need_vtd_wa(struct drm_device *dev) |
2228 | { | |
2229 | #ifdef CONFIG_INTEL_IOMMU | |
2230 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2231 | return true; | |
2232 | #endif | |
2233 | return false; | |
2234 | } | |
2235 | ||
6761dd31 TU |
2236 | static unsigned int |
2237 | intel_tile_height(struct drm_device *dev, uint32_t pixel_format, | |
2238 | uint64_t fb_format_modifier) | |
a57ce0b2 | 2239 | { |
6761dd31 TU |
2240 | unsigned int tile_height; |
2241 | uint32_t pixel_bytes; | |
a57ce0b2 | 2242 | |
b5d0e9bf DL |
2243 | switch (fb_format_modifier) { |
2244 | case DRM_FORMAT_MOD_NONE: | |
2245 | tile_height = 1; | |
2246 | break; | |
2247 | case I915_FORMAT_MOD_X_TILED: | |
2248 | tile_height = IS_GEN2(dev) ? 16 : 8; | |
2249 | break; | |
2250 | case I915_FORMAT_MOD_Y_TILED: | |
2251 | tile_height = 32; | |
2252 | break; | |
2253 | case I915_FORMAT_MOD_Yf_TILED: | |
6761dd31 TU |
2254 | pixel_bytes = drm_format_plane_cpp(pixel_format, 0); |
2255 | switch (pixel_bytes) { | |
b5d0e9bf | 2256 | default: |
6761dd31 | 2257 | case 1: |
b5d0e9bf DL |
2258 | tile_height = 64; |
2259 | break; | |
6761dd31 TU |
2260 | case 2: |
2261 | case 4: | |
b5d0e9bf DL |
2262 | tile_height = 32; |
2263 | break; | |
6761dd31 | 2264 | case 8: |
b5d0e9bf DL |
2265 | tile_height = 16; |
2266 | break; | |
6761dd31 | 2267 | case 16: |
b5d0e9bf DL |
2268 | WARN_ONCE(1, |
2269 | "128-bit pixels are not supported for display!"); | |
2270 | tile_height = 16; | |
2271 | break; | |
2272 | } | |
2273 | break; | |
2274 | default: | |
2275 | MISSING_CASE(fb_format_modifier); | |
2276 | tile_height = 1; | |
2277 | break; | |
2278 | } | |
091df6cb | 2279 | |
6761dd31 TU |
2280 | return tile_height; |
2281 | } | |
2282 | ||
2283 | unsigned int | |
2284 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
2285 | uint32_t pixel_format, uint64_t fb_format_modifier) | |
2286 | { | |
2287 | return ALIGN(height, intel_tile_height(dev, pixel_format, | |
2288 | fb_format_modifier)); | |
a57ce0b2 JB |
2289 | } |
2290 | ||
127bd2ac | 2291 | int |
850c4cdc TU |
2292 | intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
2293 | struct drm_framebuffer *fb, | |
82bc3b2d | 2294 | const struct drm_plane_state *plane_state, |
a4872ba6 | 2295 | struct intel_engine_cs *pipelined) |
6b95a207 | 2296 | { |
850c4cdc | 2297 | struct drm_device *dev = fb->dev; |
ce453d81 | 2298 | struct drm_i915_private *dev_priv = dev->dev_private; |
850c4cdc | 2299 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 KH |
2300 | u32 alignment; |
2301 | int ret; | |
2302 | ||
ebcdd39e MR |
2303 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2304 | ||
7b911adc TU |
2305 | switch (fb->modifier[0]) { |
2306 | case DRM_FORMAT_MOD_NONE: | |
1fada4cc DL |
2307 | if (INTEL_INFO(dev)->gen >= 9) |
2308 | alignment = 256 * 1024; | |
2309 | else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) | |
534843da | 2310 | alignment = 128 * 1024; |
a6c45cf0 | 2311 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
2312 | alignment = 4 * 1024; |
2313 | else | |
2314 | alignment = 64 * 1024; | |
6b95a207 | 2315 | break; |
7b911adc | 2316 | case I915_FORMAT_MOD_X_TILED: |
1fada4cc DL |
2317 | if (INTEL_INFO(dev)->gen >= 9) |
2318 | alignment = 256 * 1024; | |
2319 | else { | |
2320 | /* pin() will align the object as required by fence */ | |
2321 | alignment = 0; | |
2322 | } | |
6b95a207 | 2323 | break; |
7b911adc | 2324 | case I915_FORMAT_MOD_Y_TILED: |
1327b9a1 DL |
2325 | case I915_FORMAT_MOD_Yf_TILED: |
2326 | if (WARN_ONCE(INTEL_INFO(dev)->gen < 9, | |
2327 | "Y tiling bo slipped through, driver bug!\n")) | |
2328 | return -EINVAL; | |
2329 | alignment = 1 * 1024 * 1024; | |
2330 | break; | |
6b95a207 | 2331 | default: |
7b911adc TU |
2332 | MISSING_CASE(fb->modifier[0]); |
2333 | return -EINVAL; | |
6b95a207 KH |
2334 | } |
2335 | ||
693db184 CW |
2336 | /* Note that the w/a also requires 64 PTE of padding following the |
2337 | * bo. We currently fill all unused PTE with the shadow page and so | |
2338 | * we should always have valid PTE following the scanout preventing | |
2339 | * the VT-d warning. | |
2340 | */ | |
2341 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2342 | alignment = 256 * 1024; | |
2343 | ||
d6dd6843 PZ |
2344 | /* |
2345 | * Global gtt pte registers are special registers which actually forward | |
2346 | * writes to a chunk of system memory. Which means that there is no risk | |
2347 | * that the register values disappear as soon as we call | |
2348 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2349 | * pin/unpin/fence and not more. | |
2350 | */ | |
2351 | intel_runtime_pm_get(dev_priv); | |
2352 | ||
ce453d81 | 2353 | dev_priv->mm.interruptible = false; |
e6617330 TU |
2354 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined, |
2355 | &i915_ggtt_view_normal); | |
48b956c5 | 2356 | if (ret) |
ce453d81 | 2357 | goto err_interruptible; |
6b95a207 KH |
2358 | |
2359 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2360 | * fence, whereas 965+ only requires a fence if using | |
2361 | * framebuffer compression. For simplicity, we always install | |
2362 | * a fence as the cost is not that onerous. | |
2363 | */ | |
06d98131 | 2364 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
2365 | if (ret) |
2366 | goto err_unpin; | |
1690e1eb | 2367 | |
9a5a53b3 | 2368 | i915_gem_object_pin_fence(obj); |
6b95a207 | 2369 | |
ce453d81 | 2370 | dev_priv->mm.interruptible = true; |
d6dd6843 | 2371 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2372 | return 0; |
48b956c5 CW |
2373 | |
2374 | err_unpin: | |
e6617330 | 2375 | i915_gem_object_unpin_from_display_plane(obj, &i915_ggtt_view_normal); |
ce453d81 CW |
2376 | err_interruptible: |
2377 | dev_priv->mm.interruptible = true; | |
d6dd6843 | 2378 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2379 | return ret; |
6b95a207 KH |
2380 | } |
2381 | ||
82bc3b2d TU |
2382 | static void intel_unpin_fb_obj(struct drm_framebuffer *fb, |
2383 | const struct drm_plane_state *plane_state) | |
1690e1eb | 2384 | { |
82bc3b2d TU |
2385 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
2386 | ||
ebcdd39e MR |
2387 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2388 | ||
1690e1eb | 2389 | i915_gem_object_unpin_fence(obj); |
e6617330 | 2390 | i915_gem_object_unpin_from_display_plane(obj, &i915_ggtt_view_normal); |
1690e1eb CW |
2391 | } |
2392 | ||
c2c75131 DV |
2393 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2394 | * is assumed to be a power-of-two. */ | |
bc752862 CW |
2395 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
2396 | unsigned int tiling_mode, | |
2397 | unsigned int cpp, | |
2398 | unsigned int pitch) | |
c2c75131 | 2399 | { |
bc752862 CW |
2400 | if (tiling_mode != I915_TILING_NONE) { |
2401 | unsigned int tile_rows, tiles; | |
c2c75131 | 2402 | |
bc752862 CW |
2403 | tile_rows = *y / 8; |
2404 | *y %= 8; | |
c2c75131 | 2405 | |
bc752862 CW |
2406 | tiles = *x / (512/cpp); |
2407 | *x %= 512/cpp; | |
2408 | ||
2409 | return tile_rows * pitch * 8 + tiles * 4096; | |
2410 | } else { | |
2411 | unsigned int offset; | |
2412 | ||
2413 | offset = *y * pitch + *x * cpp; | |
2414 | *y = 0; | |
2415 | *x = (offset & 4095) / cpp; | |
2416 | return offset & -4096; | |
2417 | } | |
c2c75131 DV |
2418 | } |
2419 | ||
b35d63fa | 2420 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2421 | { |
2422 | switch (format) { | |
2423 | case DISPPLANE_8BPP: | |
2424 | return DRM_FORMAT_C8; | |
2425 | case DISPPLANE_BGRX555: | |
2426 | return DRM_FORMAT_XRGB1555; | |
2427 | case DISPPLANE_BGRX565: | |
2428 | return DRM_FORMAT_RGB565; | |
2429 | default: | |
2430 | case DISPPLANE_BGRX888: | |
2431 | return DRM_FORMAT_XRGB8888; | |
2432 | case DISPPLANE_RGBX888: | |
2433 | return DRM_FORMAT_XBGR8888; | |
2434 | case DISPPLANE_BGRX101010: | |
2435 | return DRM_FORMAT_XRGB2101010; | |
2436 | case DISPPLANE_RGBX101010: | |
2437 | return DRM_FORMAT_XBGR2101010; | |
2438 | } | |
2439 | } | |
2440 | ||
bc8d7dff DL |
2441 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2442 | { | |
2443 | switch (format) { | |
2444 | case PLANE_CTL_FORMAT_RGB_565: | |
2445 | return DRM_FORMAT_RGB565; | |
2446 | default: | |
2447 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2448 | if (rgb_order) { | |
2449 | if (alpha) | |
2450 | return DRM_FORMAT_ABGR8888; | |
2451 | else | |
2452 | return DRM_FORMAT_XBGR8888; | |
2453 | } else { | |
2454 | if (alpha) | |
2455 | return DRM_FORMAT_ARGB8888; | |
2456 | else | |
2457 | return DRM_FORMAT_XRGB8888; | |
2458 | } | |
2459 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2460 | if (rgb_order) | |
2461 | return DRM_FORMAT_XBGR2101010; | |
2462 | else | |
2463 | return DRM_FORMAT_XRGB2101010; | |
2464 | } | |
2465 | } | |
2466 | ||
5724dbd1 DL |
2467 | static bool |
2468 | intel_alloc_plane_obj(struct intel_crtc *crtc, | |
2469 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2470 | { |
2471 | struct drm_device *dev = crtc->base.dev; | |
2472 | struct drm_i915_gem_object *obj = NULL; | |
2473 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2474 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2475 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2476 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2477 | PAGE_SIZE); | |
2478 | ||
2479 | size_aligned -= base_aligned; | |
46f297fb | 2480 | |
ff2652ea CW |
2481 | if (plane_config->size == 0) |
2482 | return false; | |
2483 | ||
f37b5c2b DV |
2484 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2485 | base_aligned, | |
2486 | base_aligned, | |
2487 | size_aligned); | |
46f297fb | 2488 | if (!obj) |
484b41dd | 2489 | return false; |
46f297fb | 2490 | |
49af449b DL |
2491 | obj->tiling_mode = plane_config->tiling; |
2492 | if (obj->tiling_mode == I915_TILING_X) | |
6bf129df | 2493 | obj->stride = fb->pitches[0]; |
46f297fb | 2494 | |
6bf129df DL |
2495 | mode_cmd.pixel_format = fb->pixel_format; |
2496 | mode_cmd.width = fb->width; | |
2497 | mode_cmd.height = fb->height; | |
2498 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2499 | mode_cmd.modifier[0] = fb->modifier[0]; |
2500 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb JB |
2501 | |
2502 | mutex_lock(&dev->struct_mutex); | |
2503 | ||
6bf129df | 2504 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2505 | &mode_cmd, obj)) { |
46f297fb JB |
2506 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2507 | goto out_unref_obj; | |
2508 | } | |
2509 | ||
a071fa00 | 2510 | obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe); |
46f297fb | 2511 | mutex_unlock(&dev->struct_mutex); |
484b41dd JB |
2512 | |
2513 | DRM_DEBUG_KMS("plane fb obj %p\n", obj); | |
2514 | return true; | |
46f297fb JB |
2515 | |
2516 | out_unref_obj: | |
2517 | drm_gem_object_unreference(&obj->base); | |
2518 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2519 | return false; |
2520 | } | |
2521 | ||
afd65eb4 MR |
2522 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2523 | static void | |
2524 | update_state_fb(struct drm_plane *plane) | |
2525 | { | |
2526 | if (plane->fb == plane->state->fb) | |
2527 | return; | |
2528 | ||
2529 | if (plane->state->fb) | |
2530 | drm_framebuffer_unreference(plane->state->fb); | |
2531 | plane->state->fb = plane->fb; | |
2532 | if (plane->state->fb) | |
2533 | drm_framebuffer_reference(plane->state->fb); | |
2534 | } | |
2535 | ||
5724dbd1 DL |
2536 | static void |
2537 | intel_find_plane_obj(struct intel_crtc *intel_crtc, | |
2538 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2539 | { |
2540 | struct drm_device *dev = intel_crtc->base.dev; | |
d9ceb816 | 2541 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd JB |
2542 | struct drm_crtc *c; |
2543 | struct intel_crtc *i; | |
2ff8fde1 | 2544 | struct drm_i915_gem_object *obj; |
484b41dd | 2545 | |
2d14030b | 2546 | if (!plane_config->fb) |
484b41dd JB |
2547 | return; |
2548 | ||
f55548b5 | 2549 | if (intel_alloc_plane_obj(intel_crtc, plane_config)) { |
fb9981aa DL |
2550 | struct drm_plane *primary = intel_crtc->base.primary; |
2551 | ||
2552 | primary->fb = &plane_config->fb->base; | |
2553 | primary->state->crtc = &intel_crtc->base; | |
2554 | update_state_fb(primary); | |
2555 | ||
484b41dd | 2556 | return; |
f55548b5 | 2557 | } |
484b41dd | 2558 | |
2d14030b | 2559 | kfree(plane_config->fb); |
484b41dd JB |
2560 | |
2561 | /* | |
2562 | * Failed to alloc the obj, check to see if we should share | |
2563 | * an fb with another CRTC instead | |
2564 | */ | |
70e1e0ec | 2565 | for_each_crtc(dev, c) { |
484b41dd JB |
2566 | i = to_intel_crtc(c); |
2567 | ||
2568 | if (c == &intel_crtc->base) | |
2569 | continue; | |
2570 | ||
2ff8fde1 MR |
2571 | if (!i->active) |
2572 | continue; | |
2573 | ||
2574 | obj = intel_fb_obj(c->primary->fb); | |
2575 | if (obj == NULL) | |
484b41dd JB |
2576 | continue; |
2577 | ||
2ff8fde1 | 2578 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
fb9981aa DL |
2579 | struct drm_plane *primary = intel_crtc->base.primary; |
2580 | ||
d9ceb816 JB |
2581 | if (obj->tiling_mode != I915_TILING_NONE) |
2582 | dev_priv->preserve_bios_swizzle = true; | |
2583 | ||
66e514c1 | 2584 | drm_framebuffer_reference(c->primary->fb); |
fb9981aa DL |
2585 | primary->fb = c->primary->fb; |
2586 | primary->state->crtc = &intel_crtc->base; | |
5ba76c41 | 2587 | update_state_fb(intel_crtc->base.primary); |
2ff8fde1 | 2588 | obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); |
484b41dd JB |
2589 | break; |
2590 | } | |
2591 | } | |
46f297fb JB |
2592 | } |
2593 | ||
29b9bde6 DV |
2594 | static void i9xx_update_primary_plane(struct drm_crtc *crtc, |
2595 | struct drm_framebuffer *fb, | |
2596 | int x, int y) | |
81255565 JB |
2597 | { |
2598 | struct drm_device *dev = crtc->dev; | |
2599 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2600 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
c9ba6fad | 2601 | struct drm_i915_gem_object *obj; |
81255565 | 2602 | int plane = intel_crtc->plane; |
e506a0c6 | 2603 | unsigned long linear_offset; |
81255565 | 2604 | u32 dspcntr; |
f45651ba | 2605 | u32 reg = DSPCNTR(plane); |
48404c1e | 2606 | int pixel_size; |
f45651ba | 2607 | |
fdd508a6 VS |
2608 | if (!intel_crtc->primary_enabled) { |
2609 | I915_WRITE(reg, 0); | |
2610 | if (INTEL_INFO(dev)->gen >= 4) | |
2611 | I915_WRITE(DSPSURF(plane), 0); | |
2612 | else | |
2613 | I915_WRITE(DSPADDR(plane), 0); | |
2614 | POSTING_READ(reg); | |
2615 | return; | |
2616 | } | |
2617 | ||
c9ba6fad VS |
2618 | obj = intel_fb_obj(fb); |
2619 | if (WARN_ON(obj == NULL)) | |
2620 | return; | |
2621 | ||
2622 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2623 | ||
f45651ba VS |
2624 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2625 | ||
fdd508a6 | 2626 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2627 | |
2628 | if (INTEL_INFO(dev)->gen < 4) { | |
2629 | if (intel_crtc->pipe == PIPE_B) | |
2630 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2631 | ||
2632 | /* pipesrc and dspsize control the size that is scaled from, | |
2633 | * which should always be the user's requested size. | |
2634 | */ | |
2635 | I915_WRITE(DSPSIZE(plane), | |
6e3c9717 ACO |
2636 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2637 | (intel_crtc->config->pipe_src_w - 1)); | |
f45651ba | 2638 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
2639 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2640 | I915_WRITE(PRIMSIZE(plane), | |
6e3c9717 ACO |
2641 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2642 | (intel_crtc->config->pipe_src_w - 1)); | |
c14b0485 VS |
2643 | I915_WRITE(PRIMPOS(plane), 0); |
2644 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2645 | } |
81255565 | 2646 | |
57779d06 VS |
2647 | switch (fb->pixel_format) { |
2648 | case DRM_FORMAT_C8: | |
81255565 JB |
2649 | dspcntr |= DISPPLANE_8BPP; |
2650 | break; | |
57779d06 VS |
2651 | case DRM_FORMAT_XRGB1555: |
2652 | case DRM_FORMAT_ARGB1555: | |
2653 | dspcntr |= DISPPLANE_BGRX555; | |
81255565 | 2654 | break; |
57779d06 VS |
2655 | case DRM_FORMAT_RGB565: |
2656 | dspcntr |= DISPPLANE_BGRX565; | |
2657 | break; | |
2658 | case DRM_FORMAT_XRGB8888: | |
2659 | case DRM_FORMAT_ARGB8888: | |
2660 | dspcntr |= DISPPLANE_BGRX888; | |
2661 | break; | |
2662 | case DRM_FORMAT_XBGR8888: | |
2663 | case DRM_FORMAT_ABGR8888: | |
2664 | dspcntr |= DISPPLANE_RGBX888; | |
2665 | break; | |
2666 | case DRM_FORMAT_XRGB2101010: | |
2667 | case DRM_FORMAT_ARGB2101010: | |
2668 | dspcntr |= DISPPLANE_BGRX101010; | |
2669 | break; | |
2670 | case DRM_FORMAT_XBGR2101010: | |
2671 | case DRM_FORMAT_ABGR2101010: | |
2672 | dspcntr |= DISPPLANE_RGBX101010; | |
81255565 JB |
2673 | break; |
2674 | default: | |
baba133a | 2675 | BUG(); |
81255565 | 2676 | } |
57779d06 | 2677 | |
f45651ba VS |
2678 | if (INTEL_INFO(dev)->gen >= 4 && |
2679 | obj->tiling_mode != I915_TILING_NONE) | |
2680 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2681 | |
de1aa629 VS |
2682 | if (IS_G4X(dev)) |
2683 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2684 | ||
b9897127 | 2685 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
81255565 | 2686 | |
c2c75131 DV |
2687 | if (INTEL_INFO(dev)->gen >= 4) { |
2688 | intel_crtc->dspaddr_offset = | |
bc752862 | 2689 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
b9897127 | 2690 | pixel_size, |
bc752862 | 2691 | fb->pitches[0]); |
c2c75131 DV |
2692 | linear_offset -= intel_crtc->dspaddr_offset; |
2693 | } else { | |
e506a0c6 | 2694 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2695 | } |
e506a0c6 | 2696 | |
8e7d688b | 2697 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2698 | dspcntr |= DISPPLANE_ROTATE_180; |
2699 | ||
6e3c9717 ACO |
2700 | x += (intel_crtc->config->pipe_src_w - 1); |
2701 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2702 | |
2703 | /* Finding the last pixel of the last line of the display | |
2704 | data and adding to linear_offset*/ | |
2705 | linear_offset += | |
6e3c9717 ACO |
2706 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2707 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2708 | } |
2709 | ||
2710 | I915_WRITE(reg, dspcntr); | |
2711 | ||
01f2c773 | 2712 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2713 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2714 | I915_WRITE(DSPSURF(plane), |
2715 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2716 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2717 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2718 | } else |
f343c5f6 | 2719 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2720 | POSTING_READ(reg); |
17638cd6 JB |
2721 | } |
2722 | ||
29b9bde6 DV |
2723 | static void ironlake_update_primary_plane(struct drm_crtc *crtc, |
2724 | struct drm_framebuffer *fb, | |
2725 | int x, int y) | |
17638cd6 JB |
2726 | { |
2727 | struct drm_device *dev = crtc->dev; | |
2728 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2729 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
c9ba6fad | 2730 | struct drm_i915_gem_object *obj; |
17638cd6 | 2731 | int plane = intel_crtc->plane; |
e506a0c6 | 2732 | unsigned long linear_offset; |
17638cd6 | 2733 | u32 dspcntr; |
f45651ba | 2734 | u32 reg = DSPCNTR(plane); |
48404c1e | 2735 | int pixel_size; |
f45651ba | 2736 | |
fdd508a6 VS |
2737 | if (!intel_crtc->primary_enabled) { |
2738 | I915_WRITE(reg, 0); | |
2739 | I915_WRITE(DSPSURF(plane), 0); | |
2740 | POSTING_READ(reg); | |
2741 | return; | |
2742 | } | |
2743 | ||
c9ba6fad VS |
2744 | obj = intel_fb_obj(fb); |
2745 | if (WARN_ON(obj == NULL)) | |
2746 | return; | |
2747 | ||
2748 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2749 | ||
f45651ba VS |
2750 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2751 | ||
fdd508a6 | 2752 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2753 | |
2754 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2755 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2756 | |
57779d06 VS |
2757 | switch (fb->pixel_format) { |
2758 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2759 | dspcntr |= DISPPLANE_8BPP; |
2760 | break; | |
57779d06 VS |
2761 | case DRM_FORMAT_RGB565: |
2762 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2763 | break; |
57779d06 VS |
2764 | case DRM_FORMAT_XRGB8888: |
2765 | case DRM_FORMAT_ARGB8888: | |
2766 | dspcntr |= DISPPLANE_BGRX888; | |
2767 | break; | |
2768 | case DRM_FORMAT_XBGR8888: | |
2769 | case DRM_FORMAT_ABGR8888: | |
2770 | dspcntr |= DISPPLANE_RGBX888; | |
2771 | break; | |
2772 | case DRM_FORMAT_XRGB2101010: | |
2773 | case DRM_FORMAT_ARGB2101010: | |
2774 | dspcntr |= DISPPLANE_BGRX101010; | |
2775 | break; | |
2776 | case DRM_FORMAT_XBGR2101010: | |
2777 | case DRM_FORMAT_ABGR2101010: | |
2778 | dspcntr |= DISPPLANE_RGBX101010; | |
17638cd6 JB |
2779 | break; |
2780 | default: | |
baba133a | 2781 | BUG(); |
17638cd6 JB |
2782 | } |
2783 | ||
2784 | if (obj->tiling_mode != I915_TILING_NONE) | |
2785 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2786 | |
f45651ba | 2787 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2788 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2789 | |
b9897127 | 2790 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
c2c75131 | 2791 | intel_crtc->dspaddr_offset = |
bc752862 | 2792 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
b9897127 | 2793 | pixel_size, |
bc752862 | 2794 | fb->pitches[0]); |
c2c75131 | 2795 | linear_offset -= intel_crtc->dspaddr_offset; |
8e7d688b | 2796 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2797 | dspcntr |= DISPPLANE_ROTATE_180; |
2798 | ||
2799 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
6e3c9717 ACO |
2800 | x += (intel_crtc->config->pipe_src_w - 1); |
2801 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2802 | |
2803 | /* Finding the last pixel of the last line of the display | |
2804 | data and adding to linear_offset*/ | |
2805 | linear_offset += | |
6e3c9717 ACO |
2806 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2807 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2808 | } |
2809 | } | |
2810 | ||
2811 | I915_WRITE(reg, dspcntr); | |
17638cd6 | 2812 | |
01f2c773 | 2813 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2814 | I915_WRITE(DSPSURF(plane), |
2815 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2816 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2817 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2818 | } else { | |
2819 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2820 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2821 | } | |
17638cd6 | 2822 | POSTING_READ(reg); |
17638cd6 JB |
2823 | } |
2824 | ||
b321803d DL |
2825 | u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier, |
2826 | uint32_t pixel_format) | |
2827 | { | |
2828 | u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8; | |
2829 | ||
2830 | /* | |
2831 | * The stride is either expressed as a multiple of 64 bytes | |
2832 | * chunks for linear buffers or in number of tiles for tiled | |
2833 | * buffers. | |
2834 | */ | |
2835 | switch (fb_modifier) { | |
2836 | case DRM_FORMAT_MOD_NONE: | |
2837 | return 64; | |
2838 | case I915_FORMAT_MOD_X_TILED: | |
2839 | if (INTEL_INFO(dev)->gen == 2) | |
2840 | return 128; | |
2841 | return 512; | |
2842 | case I915_FORMAT_MOD_Y_TILED: | |
2843 | /* No need to check for old gens and Y tiling since this is | |
2844 | * about the display engine and those will be blocked before | |
2845 | * we get here. | |
2846 | */ | |
2847 | return 128; | |
2848 | case I915_FORMAT_MOD_Yf_TILED: | |
2849 | if (bits_per_pixel == 8) | |
2850 | return 64; | |
2851 | else | |
2852 | return 128; | |
2853 | default: | |
2854 | MISSING_CASE(fb_modifier); | |
2855 | return 64; | |
2856 | } | |
2857 | } | |
2858 | ||
70d21f0e DL |
2859 | static void skylake_update_primary_plane(struct drm_crtc *crtc, |
2860 | struct drm_framebuffer *fb, | |
2861 | int x, int y) | |
2862 | { | |
2863 | struct drm_device *dev = crtc->dev; | |
2864 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2865 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
70d21f0e DL |
2866 | struct drm_i915_gem_object *obj; |
2867 | int pipe = intel_crtc->pipe; | |
b321803d | 2868 | u32 plane_ctl, stride_div; |
70d21f0e DL |
2869 | |
2870 | if (!intel_crtc->primary_enabled) { | |
2871 | I915_WRITE(PLANE_CTL(pipe, 0), 0); | |
2872 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
2873 | POSTING_READ(PLANE_CTL(pipe, 0)); | |
2874 | return; | |
2875 | } | |
2876 | ||
2877 | plane_ctl = PLANE_CTL_ENABLE | | |
2878 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
2879 | PLANE_CTL_PIPE_CSC_ENABLE; | |
2880 | ||
2881 | switch (fb->pixel_format) { | |
2882 | case DRM_FORMAT_RGB565: | |
2883 | plane_ctl |= PLANE_CTL_FORMAT_RGB_565; | |
2884 | break; | |
2885 | case DRM_FORMAT_XRGB8888: | |
2886 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; | |
2887 | break; | |
f75fb42a JN |
2888 | case DRM_FORMAT_ARGB8888: |
2889 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; | |
2890 | plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY; | |
2891 | break; | |
70d21f0e DL |
2892 | case DRM_FORMAT_XBGR8888: |
2893 | plane_ctl |= PLANE_CTL_ORDER_RGBX; | |
2894 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; | |
2895 | break; | |
f75fb42a JN |
2896 | case DRM_FORMAT_ABGR8888: |
2897 | plane_ctl |= PLANE_CTL_ORDER_RGBX; | |
2898 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; | |
2899 | plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY; | |
2900 | break; | |
70d21f0e DL |
2901 | case DRM_FORMAT_XRGB2101010: |
2902 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010; | |
2903 | break; | |
2904 | case DRM_FORMAT_XBGR2101010: | |
2905 | plane_ctl |= PLANE_CTL_ORDER_RGBX; | |
2906 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010; | |
2907 | break; | |
2908 | default: | |
2909 | BUG(); | |
2910 | } | |
2911 | ||
30af77c4 DV |
2912 | switch (fb->modifier[0]) { |
2913 | case DRM_FORMAT_MOD_NONE: | |
70d21f0e | 2914 | break; |
30af77c4 | 2915 | case I915_FORMAT_MOD_X_TILED: |
70d21f0e | 2916 | plane_ctl |= PLANE_CTL_TILED_X; |
b321803d DL |
2917 | break; |
2918 | case I915_FORMAT_MOD_Y_TILED: | |
2919 | plane_ctl |= PLANE_CTL_TILED_Y; | |
2920 | break; | |
2921 | case I915_FORMAT_MOD_Yf_TILED: | |
2922 | plane_ctl |= PLANE_CTL_TILED_YF; | |
70d21f0e DL |
2923 | break; |
2924 | default: | |
b321803d | 2925 | MISSING_CASE(fb->modifier[0]); |
70d21f0e DL |
2926 | } |
2927 | ||
2928 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
8e7d688b | 2929 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) |
1447dde0 | 2930 | plane_ctl |= PLANE_CTL_ROTATE_180; |
70d21f0e | 2931 | |
b321803d DL |
2932 | obj = intel_fb_obj(fb); |
2933 | stride_div = intel_fb_stride_alignment(dev, fb->modifier[0], | |
2934 | fb->pixel_format); | |
2935 | ||
70d21f0e DL |
2936 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
2937 | ||
70d21f0e DL |
2938 | I915_WRITE(PLANE_POS(pipe, 0), 0); |
2939 | I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x); | |
2940 | I915_WRITE(PLANE_SIZE(pipe, 0), | |
6e3c9717 ACO |
2941 | (intel_crtc->config->pipe_src_h - 1) << 16 | |
2942 | (intel_crtc->config->pipe_src_w - 1)); | |
b321803d | 2943 | I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div); |
70d21f0e DL |
2944 | I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj)); |
2945 | ||
2946 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
2947 | } | |
2948 | ||
17638cd6 JB |
2949 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
2950 | static int | |
2951 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
2952 | int x, int y, enum mode_set_atomic state) | |
2953 | { | |
2954 | struct drm_device *dev = crtc->dev; | |
2955 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 2956 | |
6b8e6ed0 CW |
2957 | if (dev_priv->display.disable_fbc) |
2958 | dev_priv->display.disable_fbc(dev); | |
81255565 | 2959 | |
29b9bde6 DV |
2960 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
2961 | ||
2962 | return 0; | |
81255565 JB |
2963 | } |
2964 | ||
7514747d | 2965 | static void intel_complete_page_flips(struct drm_device *dev) |
96a02917 | 2966 | { |
96a02917 VS |
2967 | struct drm_crtc *crtc; |
2968 | ||
70e1e0ec | 2969 | for_each_crtc(dev, crtc) { |
96a02917 VS |
2970 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2971 | enum plane plane = intel_crtc->plane; | |
2972 | ||
2973 | intel_prepare_page_flip(dev, plane); | |
2974 | intel_finish_page_flip_plane(dev, plane); | |
2975 | } | |
7514747d VS |
2976 | } |
2977 | ||
2978 | static void intel_update_primary_planes(struct drm_device *dev) | |
2979 | { | |
2980 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2981 | struct drm_crtc *crtc; | |
96a02917 | 2982 | |
70e1e0ec | 2983 | for_each_crtc(dev, crtc) { |
96a02917 VS |
2984 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2985 | ||
51fd371b | 2986 | drm_modeset_lock(&crtc->mutex, NULL); |
947fdaad CW |
2987 | /* |
2988 | * FIXME: Once we have proper support for primary planes (and | |
2989 | * disabling them without disabling the entire crtc) allow again | |
66e514c1 | 2990 | * a NULL crtc->primary->fb. |
947fdaad | 2991 | */ |
f4510a27 | 2992 | if (intel_crtc->active && crtc->primary->fb) |
262ca2b0 | 2993 | dev_priv->display.update_primary_plane(crtc, |
66e514c1 | 2994 | crtc->primary->fb, |
262ca2b0 MR |
2995 | crtc->x, |
2996 | crtc->y); | |
51fd371b | 2997 | drm_modeset_unlock(&crtc->mutex); |
96a02917 VS |
2998 | } |
2999 | } | |
3000 | ||
7514747d VS |
3001 | void intel_prepare_reset(struct drm_device *dev) |
3002 | { | |
f98ce92f VS |
3003 | struct drm_i915_private *dev_priv = to_i915(dev); |
3004 | struct intel_crtc *crtc; | |
3005 | ||
7514747d VS |
3006 | /* no reset support for gen2 */ |
3007 | if (IS_GEN2(dev)) | |
3008 | return; | |
3009 | ||
3010 | /* reset doesn't touch the display */ | |
3011 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
3012 | return; | |
3013 | ||
3014 | drm_modeset_lock_all(dev); | |
f98ce92f VS |
3015 | |
3016 | /* | |
3017 | * Disabling the crtcs gracefully seems nicer. Also the | |
3018 | * g33 docs say we should at least disable all the planes. | |
3019 | */ | |
3020 | for_each_intel_crtc(dev, crtc) { | |
3021 | if (crtc->active) | |
3022 | dev_priv->display.crtc_disable(&crtc->base); | |
3023 | } | |
7514747d VS |
3024 | } |
3025 | ||
3026 | void intel_finish_reset(struct drm_device *dev) | |
3027 | { | |
3028 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3029 | ||
3030 | /* | |
3031 | * Flips in the rings will be nuked by the reset, | |
3032 | * so complete all pending flips so that user space | |
3033 | * will get its events and not get stuck. | |
3034 | */ | |
3035 | intel_complete_page_flips(dev); | |
3036 | ||
3037 | /* no reset support for gen2 */ | |
3038 | if (IS_GEN2(dev)) | |
3039 | return; | |
3040 | ||
3041 | /* reset doesn't touch the display */ | |
3042 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { | |
3043 | /* | |
3044 | * Flips in the rings have been nuked by the reset, | |
3045 | * so update the base address of all primary | |
3046 | * planes to the the last fb to make sure we're | |
3047 | * showing the correct fb after a reset. | |
3048 | */ | |
3049 | intel_update_primary_planes(dev); | |
3050 | return; | |
3051 | } | |
3052 | ||
3053 | /* | |
3054 | * The display has been reset as well, | |
3055 | * so need a full re-initialization. | |
3056 | */ | |
3057 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3058 | intel_runtime_pm_enable_interrupts(dev_priv); | |
3059 | ||
3060 | intel_modeset_init_hw(dev); | |
3061 | ||
3062 | spin_lock_irq(&dev_priv->irq_lock); | |
3063 | if (dev_priv->display.hpd_irq_setup) | |
3064 | dev_priv->display.hpd_irq_setup(dev); | |
3065 | spin_unlock_irq(&dev_priv->irq_lock); | |
3066 | ||
3067 | intel_modeset_setup_hw_state(dev, true); | |
3068 | ||
3069 | intel_hpd_init(dev_priv); | |
3070 | ||
3071 | drm_modeset_unlock_all(dev); | |
3072 | } | |
3073 | ||
14667a4b CW |
3074 | static int |
3075 | intel_finish_fb(struct drm_framebuffer *old_fb) | |
3076 | { | |
2ff8fde1 | 3077 | struct drm_i915_gem_object *obj = intel_fb_obj(old_fb); |
14667a4b CW |
3078 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
3079 | bool was_interruptible = dev_priv->mm.interruptible; | |
3080 | int ret; | |
3081 | ||
14667a4b CW |
3082 | /* Big Hammer, we also need to ensure that any pending |
3083 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
3084 | * current scanout is retired before unpinning the old | |
3085 | * framebuffer. | |
3086 | * | |
3087 | * This should only fail upon a hung GPU, in which case we | |
3088 | * can safely continue. | |
3089 | */ | |
3090 | dev_priv->mm.interruptible = false; | |
3091 | ret = i915_gem_object_finish_gpu(obj); | |
3092 | dev_priv->mm.interruptible = was_interruptible; | |
3093 | ||
3094 | return ret; | |
3095 | } | |
3096 | ||
7d5e3799 CW |
3097 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3098 | { | |
3099 | struct drm_device *dev = crtc->dev; | |
3100 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3101 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7d5e3799 CW |
3102 | bool pending; |
3103 | ||
3104 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
3105 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
3106 | return false; | |
3107 | ||
5e2d7afc | 3108 | spin_lock_irq(&dev->event_lock); |
7d5e3799 | 3109 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
5e2d7afc | 3110 | spin_unlock_irq(&dev->event_lock); |
7d5e3799 CW |
3111 | |
3112 | return pending; | |
3113 | } | |
3114 | ||
e30e8f75 GP |
3115 | static void intel_update_pipe_size(struct intel_crtc *crtc) |
3116 | { | |
3117 | struct drm_device *dev = crtc->base.dev; | |
3118 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3119 | const struct drm_display_mode *adjusted_mode; | |
3120 | ||
3121 | if (!i915.fastboot) | |
3122 | return; | |
3123 | ||
3124 | /* | |
3125 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3126 | * that in compute_mode_changes we check the native mode (not the pfit | |
3127 | * mode) to see if we can flip rather than do a full mode set. In the | |
3128 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3129 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3130 | * sized surface. | |
3131 | * | |
3132 | * To fix this properly, we need to hoist the checks up into | |
3133 | * compute_mode_changes (or above), check the actual pfit state and | |
3134 | * whether the platform allows pfit disable with pipe active, and only | |
3135 | * then update the pipesrc and pfit state, even on the flip path. | |
3136 | */ | |
3137 | ||
6e3c9717 | 3138 | adjusted_mode = &crtc->config->base.adjusted_mode; |
e30e8f75 GP |
3139 | |
3140 | I915_WRITE(PIPESRC(crtc->pipe), | |
3141 | ((adjusted_mode->crtc_hdisplay - 1) << 16) | | |
3142 | (adjusted_mode->crtc_vdisplay - 1)); | |
6e3c9717 | 3143 | if (!crtc->config->pch_pfit.enabled && |
409ee761 ACO |
3144 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
3145 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
e30e8f75 GP |
3146 | I915_WRITE(PF_CTL(crtc->pipe), 0); |
3147 | I915_WRITE(PF_WIN_POS(crtc->pipe), 0); | |
3148 | I915_WRITE(PF_WIN_SZ(crtc->pipe), 0); | |
3149 | } | |
6e3c9717 ACO |
3150 | crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay; |
3151 | crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay; | |
e30e8f75 GP |
3152 | } |
3153 | ||
5e84e1a4 ZW |
3154 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3155 | { | |
3156 | struct drm_device *dev = crtc->dev; | |
3157 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3158 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3159 | int pipe = intel_crtc->pipe; | |
3160 | u32 reg, temp; | |
3161 | ||
3162 | /* enable normal train */ | |
3163 | reg = FDI_TX_CTL(pipe); | |
3164 | temp = I915_READ(reg); | |
61e499bf | 3165 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3166 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3167 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3168 | } else { |
3169 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3170 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3171 | } |
5e84e1a4 ZW |
3172 | I915_WRITE(reg, temp); |
3173 | ||
3174 | reg = FDI_RX_CTL(pipe); | |
3175 | temp = I915_READ(reg); | |
3176 | if (HAS_PCH_CPT(dev)) { | |
3177 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3178 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3179 | } else { | |
3180 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3181 | temp |= FDI_LINK_TRAIN_NONE; | |
3182 | } | |
3183 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3184 | ||
3185 | /* wait one idle pattern time */ | |
3186 | POSTING_READ(reg); | |
3187 | udelay(1000); | |
357555c0 JB |
3188 | |
3189 | /* IVB wants error correction enabled */ | |
3190 | if (IS_IVYBRIDGE(dev)) | |
3191 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3192 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3193 | } |
3194 | ||
8db9d77b ZW |
3195 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3196 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3197 | { | |
3198 | struct drm_device *dev = crtc->dev; | |
3199 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3200 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3201 | int pipe = intel_crtc->pipe; | |
5eddb70b | 3202 | u32 reg, temp, tries; |
8db9d77b | 3203 | |
1c8562f6 | 3204 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3205 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3206 | |
e1a44743 AJ |
3207 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3208 | for train result */ | |
5eddb70b CW |
3209 | reg = FDI_RX_IMR(pipe); |
3210 | temp = I915_READ(reg); | |
e1a44743 AJ |
3211 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3212 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3213 | I915_WRITE(reg, temp); |
3214 | I915_READ(reg); | |
e1a44743 AJ |
3215 | udelay(150); |
3216 | ||
8db9d77b | 3217 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3218 | reg = FDI_TX_CTL(pipe); |
3219 | temp = I915_READ(reg); | |
627eb5a3 | 3220 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3221 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3222 | temp &= ~FDI_LINK_TRAIN_NONE; |
3223 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3224 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3225 | |
5eddb70b CW |
3226 | reg = FDI_RX_CTL(pipe); |
3227 | temp = I915_READ(reg); | |
8db9d77b ZW |
3228 | temp &= ~FDI_LINK_TRAIN_NONE; |
3229 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3230 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3231 | ||
3232 | POSTING_READ(reg); | |
8db9d77b ZW |
3233 | udelay(150); |
3234 | ||
5b2adf89 | 3235 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3236 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3237 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3238 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3239 | |
5eddb70b | 3240 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3241 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3242 | temp = I915_READ(reg); |
8db9d77b ZW |
3243 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3244 | ||
3245 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3246 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3247 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3248 | break; |
3249 | } | |
8db9d77b | 3250 | } |
e1a44743 | 3251 | if (tries == 5) |
5eddb70b | 3252 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3253 | |
3254 | /* Train 2 */ | |
5eddb70b CW |
3255 | reg = FDI_TX_CTL(pipe); |
3256 | temp = I915_READ(reg); | |
8db9d77b ZW |
3257 | temp &= ~FDI_LINK_TRAIN_NONE; |
3258 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3259 | I915_WRITE(reg, temp); |
8db9d77b | 3260 | |
5eddb70b CW |
3261 | reg = FDI_RX_CTL(pipe); |
3262 | temp = I915_READ(reg); | |
8db9d77b ZW |
3263 | temp &= ~FDI_LINK_TRAIN_NONE; |
3264 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3265 | I915_WRITE(reg, temp); |
8db9d77b | 3266 | |
5eddb70b CW |
3267 | POSTING_READ(reg); |
3268 | udelay(150); | |
8db9d77b | 3269 | |
5eddb70b | 3270 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3271 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3272 | temp = I915_READ(reg); |
8db9d77b ZW |
3273 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3274 | ||
3275 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3276 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3277 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3278 | break; | |
3279 | } | |
8db9d77b | 3280 | } |
e1a44743 | 3281 | if (tries == 5) |
5eddb70b | 3282 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3283 | |
3284 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3285 | |
8db9d77b ZW |
3286 | } |
3287 | ||
0206e353 | 3288 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3289 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3290 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3291 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3292 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3293 | }; | |
3294 | ||
3295 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3296 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3297 | { | |
3298 | struct drm_device *dev = crtc->dev; | |
3299 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3300 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3301 | int pipe = intel_crtc->pipe; | |
fa37d39e | 3302 | u32 reg, temp, i, retry; |
8db9d77b | 3303 | |
e1a44743 AJ |
3304 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3305 | for train result */ | |
5eddb70b CW |
3306 | reg = FDI_RX_IMR(pipe); |
3307 | temp = I915_READ(reg); | |
e1a44743 AJ |
3308 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3309 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3310 | I915_WRITE(reg, temp); |
3311 | ||
3312 | POSTING_READ(reg); | |
e1a44743 AJ |
3313 | udelay(150); |
3314 | ||
8db9d77b | 3315 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3316 | reg = FDI_TX_CTL(pipe); |
3317 | temp = I915_READ(reg); | |
627eb5a3 | 3318 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3319 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3320 | temp &= ~FDI_LINK_TRAIN_NONE; |
3321 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3322 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3323 | /* SNB-B */ | |
3324 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3325 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3326 | |
d74cf324 DV |
3327 | I915_WRITE(FDI_RX_MISC(pipe), |
3328 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3329 | ||
5eddb70b CW |
3330 | reg = FDI_RX_CTL(pipe); |
3331 | temp = I915_READ(reg); | |
8db9d77b ZW |
3332 | if (HAS_PCH_CPT(dev)) { |
3333 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3334 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3335 | } else { | |
3336 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3337 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3338 | } | |
5eddb70b CW |
3339 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3340 | ||
3341 | POSTING_READ(reg); | |
8db9d77b ZW |
3342 | udelay(150); |
3343 | ||
0206e353 | 3344 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3345 | reg = FDI_TX_CTL(pipe); |
3346 | temp = I915_READ(reg); | |
8db9d77b ZW |
3347 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3348 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3349 | I915_WRITE(reg, temp); |
3350 | ||
3351 | POSTING_READ(reg); | |
8db9d77b ZW |
3352 | udelay(500); |
3353 | ||
fa37d39e SP |
3354 | for (retry = 0; retry < 5; retry++) { |
3355 | reg = FDI_RX_IIR(pipe); | |
3356 | temp = I915_READ(reg); | |
3357 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3358 | if (temp & FDI_RX_BIT_LOCK) { | |
3359 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3360 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3361 | break; | |
3362 | } | |
3363 | udelay(50); | |
8db9d77b | 3364 | } |
fa37d39e SP |
3365 | if (retry < 5) |
3366 | break; | |
8db9d77b ZW |
3367 | } |
3368 | if (i == 4) | |
5eddb70b | 3369 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3370 | |
3371 | /* Train 2 */ | |
5eddb70b CW |
3372 | reg = FDI_TX_CTL(pipe); |
3373 | temp = I915_READ(reg); | |
8db9d77b ZW |
3374 | temp &= ~FDI_LINK_TRAIN_NONE; |
3375 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3376 | if (IS_GEN6(dev)) { | |
3377 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3378 | /* SNB-B */ | |
3379 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3380 | } | |
5eddb70b | 3381 | I915_WRITE(reg, temp); |
8db9d77b | 3382 | |
5eddb70b CW |
3383 | reg = FDI_RX_CTL(pipe); |
3384 | temp = I915_READ(reg); | |
8db9d77b ZW |
3385 | if (HAS_PCH_CPT(dev)) { |
3386 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3387 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3388 | } else { | |
3389 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3390 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3391 | } | |
5eddb70b CW |
3392 | I915_WRITE(reg, temp); |
3393 | ||
3394 | POSTING_READ(reg); | |
8db9d77b ZW |
3395 | udelay(150); |
3396 | ||
0206e353 | 3397 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3398 | reg = FDI_TX_CTL(pipe); |
3399 | temp = I915_READ(reg); | |
8db9d77b ZW |
3400 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3401 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3402 | I915_WRITE(reg, temp); |
3403 | ||
3404 | POSTING_READ(reg); | |
8db9d77b ZW |
3405 | udelay(500); |
3406 | ||
fa37d39e SP |
3407 | for (retry = 0; retry < 5; retry++) { |
3408 | reg = FDI_RX_IIR(pipe); | |
3409 | temp = I915_READ(reg); | |
3410 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3411 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3412 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3413 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3414 | break; | |
3415 | } | |
3416 | udelay(50); | |
8db9d77b | 3417 | } |
fa37d39e SP |
3418 | if (retry < 5) |
3419 | break; | |
8db9d77b ZW |
3420 | } |
3421 | if (i == 4) | |
5eddb70b | 3422 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3423 | |
3424 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3425 | } | |
3426 | ||
357555c0 JB |
3427 | /* Manual link training for Ivy Bridge A0 parts */ |
3428 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3429 | { | |
3430 | struct drm_device *dev = crtc->dev; | |
3431 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3432 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3433 | int pipe = intel_crtc->pipe; | |
139ccd3f | 3434 | u32 reg, temp, i, j; |
357555c0 JB |
3435 | |
3436 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3437 | for train result */ | |
3438 | reg = FDI_RX_IMR(pipe); | |
3439 | temp = I915_READ(reg); | |
3440 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3441 | temp &= ~FDI_RX_BIT_LOCK; | |
3442 | I915_WRITE(reg, temp); | |
3443 | ||
3444 | POSTING_READ(reg); | |
3445 | udelay(150); | |
3446 | ||
01a415fd DV |
3447 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3448 | I915_READ(FDI_RX_IIR(pipe))); | |
3449 | ||
139ccd3f JB |
3450 | /* Try each vswing and preemphasis setting twice before moving on */ |
3451 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3452 | /* disable first in case we need to retry */ | |
3453 | reg = FDI_TX_CTL(pipe); | |
3454 | temp = I915_READ(reg); | |
3455 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3456 | temp &= ~FDI_TX_ENABLE; | |
3457 | I915_WRITE(reg, temp); | |
357555c0 | 3458 | |
139ccd3f JB |
3459 | reg = FDI_RX_CTL(pipe); |
3460 | temp = I915_READ(reg); | |
3461 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3462 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3463 | temp &= ~FDI_RX_ENABLE; | |
3464 | I915_WRITE(reg, temp); | |
357555c0 | 3465 | |
139ccd3f | 3466 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3467 | reg = FDI_TX_CTL(pipe); |
3468 | temp = I915_READ(reg); | |
139ccd3f | 3469 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3470 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 3471 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3472 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3473 | temp |= snb_b_fdi_train_param[j/2]; |
3474 | temp |= FDI_COMPOSITE_SYNC; | |
3475 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3476 | |
139ccd3f JB |
3477 | I915_WRITE(FDI_RX_MISC(pipe), |
3478 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3479 | |
139ccd3f | 3480 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3481 | temp = I915_READ(reg); |
139ccd3f JB |
3482 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3483 | temp |= FDI_COMPOSITE_SYNC; | |
3484 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3485 | |
139ccd3f JB |
3486 | POSTING_READ(reg); |
3487 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3488 | |
139ccd3f JB |
3489 | for (i = 0; i < 4; i++) { |
3490 | reg = FDI_RX_IIR(pipe); | |
3491 | temp = I915_READ(reg); | |
3492 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3493 | |
139ccd3f JB |
3494 | if (temp & FDI_RX_BIT_LOCK || |
3495 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3496 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3497 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3498 | i); | |
3499 | break; | |
3500 | } | |
3501 | udelay(1); /* should be 0.5us */ | |
3502 | } | |
3503 | if (i == 4) { | |
3504 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3505 | continue; | |
3506 | } | |
357555c0 | 3507 | |
139ccd3f | 3508 | /* Train 2 */ |
357555c0 JB |
3509 | reg = FDI_TX_CTL(pipe); |
3510 | temp = I915_READ(reg); | |
139ccd3f JB |
3511 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3512 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3513 | I915_WRITE(reg, temp); | |
3514 | ||
3515 | reg = FDI_RX_CTL(pipe); | |
3516 | temp = I915_READ(reg); | |
3517 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3518 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3519 | I915_WRITE(reg, temp); |
3520 | ||
3521 | POSTING_READ(reg); | |
139ccd3f | 3522 | udelay(2); /* should be 1.5us */ |
357555c0 | 3523 | |
139ccd3f JB |
3524 | for (i = 0; i < 4; i++) { |
3525 | reg = FDI_RX_IIR(pipe); | |
3526 | temp = I915_READ(reg); | |
3527 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3528 | |
139ccd3f JB |
3529 | if (temp & FDI_RX_SYMBOL_LOCK || |
3530 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3531 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3532 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3533 | i); | |
3534 | goto train_done; | |
3535 | } | |
3536 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3537 | } |
139ccd3f JB |
3538 | if (i == 4) |
3539 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3540 | } |
357555c0 | 3541 | |
139ccd3f | 3542 | train_done: |
357555c0 JB |
3543 | DRM_DEBUG_KMS("FDI train done.\n"); |
3544 | } | |
3545 | ||
88cefb6c | 3546 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3547 | { |
88cefb6c | 3548 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3549 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3550 | int pipe = intel_crtc->pipe; |
5eddb70b | 3551 | u32 reg, temp; |
79e53945 | 3552 | |
c64e311e | 3553 | |
c98e9dcf | 3554 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3555 | reg = FDI_RX_CTL(pipe); |
3556 | temp = I915_READ(reg); | |
627eb5a3 | 3557 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3558 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3559 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3560 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3561 | ||
3562 | POSTING_READ(reg); | |
c98e9dcf JB |
3563 | udelay(200); |
3564 | ||
3565 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3566 | temp = I915_READ(reg); |
3567 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3568 | ||
3569 | POSTING_READ(reg); | |
c98e9dcf JB |
3570 | udelay(200); |
3571 | ||
20749730 PZ |
3572 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3573 | reg = FDI_TX_CTL(pipe); | |
3574 | temp = I915_READ(reg); | |
3575 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3576 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3577 | |
20749730 PZ |
3578 | POSTING_READ(reg); |
3579 | udelay(100); | |
6be4a607 | 3580 | } |
0e23b99d JB |
3581 | } |
3582 | ||
88cefb6c DV |
3583 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3584 | { | |
3585 | struct drm_device *dev = intel_crtc->base.dev; | |
3586 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3587 | int pipe = intel_crtc->pipe; | |
3588 | u32 reg, temp; | |
3589 | ||
3590 | /* Switch from PCDclk to Rawclk */ | |
3591 | reg = FDI_RX_CTL(pipe); | |
3592 | temp = I915_READ(reg); | |
3593 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3594 | ||
3595 | /* Disable CPU FDI TX PLL */ | |
3596 | reg = FDI_TX_CTL(pipe); | |
3597 | temp = I915_READ(reg); | |
3598 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3599 | ||
3600 | POSTING_READ(reg); | |
3601 | udelay(100); | |
3602 | ||
3603 | reg = FDI_RX_CTL(pipe); | |
3604 | temp = I915_READ(reg); | |
3605 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3606 | ||
3607 | /* Wait for the clocks to turn off. */ | |
3608 | POSTING_READ(reg); | |
3609 | udelay(100); | |
3610 | } | |
3611 | ||
0fc932b8 JB |
3612 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3613 | { | |
3614 | struct drm_device *dev = crtc->dev; | |
3615 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3616 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3617 | int pipe = intel_crtc->pipe; | |
3618 | u32 reg, temp; | |
3619 | ||
3620 | /* disable CPU FDI tx and PCH FDI rx */ | |
3621 | reg = FDI_TX_CTL(pipe); | |
3622 | temp = I915_READ(reg); | |
3623 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3624 | POSTING_READ(reg); | |
3625 | ||
3626 | reg = FDI_RX_CTL(pipe); | |
3627 | temp = I915_READ(reg); | |
3628 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3629 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3630 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3631 | ||
3632 | POSTING_READ(reg); | |
3633 | udelay(100); | |
3634 | ||
3635 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3636 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3637 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3638 | |
3639 | /* still set train pattern 1 */ | |
3640 | reg = FDI_TX_CTL(pipe); | |
3641 | temp = I915_READ(reg); | |
3642 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3643 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3644 | I915_WRITE(reg, temp); | |
3645 | ||
3646 | reg = FDI_RX_CTL(pipe); | |
3647 | temp = I915_READ(reg); | |
3648 | if (HAS_PCH_CPT(dev)) { | |
3649 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3650 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3651 | } else { | |
3652 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3653 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3654 | } | |
3655 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3656 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3657 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3658 | I915_WRITE(reg, temp); |
3659 | ||
3660 | POSTING_READ(reg); | |
3661 | udelay(100); | |
3662 | } | |
3663 | ||
5dce5b93 CW |
3664 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3665 | { | |
3666 | struct intel_crtc *crtc; | |
3667 | ||
3668 | /* Note that we don't need to be called with mode_config.lock here | |
3669 | * as our list of CRTC objects is static for the lifetime of the | |
3670 | * device and so cannot disappear as we iterate. Similarly, we can | |
3671 | * happily treat the predicates as racy, atomic checks as userspace | |
3672 | * cannot claim and pin a new fb without at least acquring the | |
3673 | * struct_mutex and so serialising with us. | |
3674 | */ | |
d3fcc808 | 3675 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3676 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3677 | continue; | |
3678 | ||
3679 | if (crtc->unpin_work) | |
3680 | intel_wait_for_vblank(dev, crtc->pipe); | |
3681 | ||
3682 | return true; | |
3683 | } | |
3684 | ||
3685 | return false; | |
3686 | } | |
3687 | ||
d6bbafa1 CW |
3688 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
3689 | { | |
3690 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
3691 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
3692 | ||
3693 | /* ensure that the unpin work is consistent wrt ->pending. */ | |
3694 | smp_rmb(); | |
3695 | intel_crtc->unpin_work = NULL; | |
3696 | ||
3697 | if (work->event) | |
3698 | drm_send_vblank_event(intel_crtc->base.dev, | |
3699 | intel_crtc->pipe, | |
3700 | work->event); | |
3701 | ||
3702 | drm_crtc_vblank_put(&intel_crtc->base); | |
3703 | ||
3704 | wake_up_all(&dev_priv->pending_flip_queue); | |
3705 | queue_work(dev_priv->wq, &work->work); | |
3706 | ||
3707 | trace_i915_flip_complete(intel_crtc->plane, | |
3708 | work->pending_flip_obj); | |
3709 | } | |
3710 | ||
46a55d30 | 3711 | void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3712 | { |
0f91128d | 3713 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3714 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 | 3715 | |
2c10d571 | 3716 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
9c787942 CW |
3717 | if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue, |
3718 | !intel_crtc_has_pending_flip(crtc), | |
3719 | 60*HZ) == 0)) { | |
3720 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2c10d571 | 3721 | |
5e2d7afc | 3722 | spin_lock_irq(&dev->event_lock); |
9c787942 CW |
3723 | if (intel_crtc->unpin_work) { |
3724 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
3725 | page_flip_completed(intel_crtc); | |
3726 | } | |
5e2d7afc | 3727 | spin_unlock_irq(&dev->event_lock); |
9c787942 | 3728 | } |
5bb61643 | 3729 | |
975d568a CW |
3730 | if (crtc->primary->fb) { |
3731 | mutex_lock(&dev->struct_mutex); | |
3732 | intel_finish_fb(crtc->primary->fb); | |
3733 | mutex_unlock(&dev->struct_mutex); | |
3734 | } | |
e6c3a2a6 CW |
3735 | } |
3736 | ||
e615efe4 ED |
3737 | /* Program iCLKIP clock to the desired frequency */ |
3738 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3739 | { | |
3740 | struct drm_device *dev = crtc->dev; | |
3741 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 3742 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
3743 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3744 | u32 temp; | |
3745 | ||
09153000 DV |
3746 | mutex_lock(&dev_priv->dpio_lock); |
3747 | ||
e615efe4 ED |
3748 | /* It is necessary to ungate the pixclk gate prior to programming |
3749 | * the divisors, and gate it back when it is done. | |
3750 | */ | |
3751 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3752 | ||
3753 | /* Disable SSCCTL */ | |
3754 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
3755 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
3756 | SBI_SSCCTL_DISABLE, | |
3757 | SBI_ICLK); | |
e615efe4 ED |
3758 | |
3759 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3760 | if (clock == 20000) { |
e615efe4 ED |
3761 | auxdiv = 1; |
3762 | divsel = 0x41; | |
3763 | phaseinc = 0x20; | |
3764 | } else { | |
3765 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3766 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3767 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3768 | * convert the virtual clock precision to KHz here for higher |
3769 | * precision. | |
3770 | */ | |
3771 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3772 | u32 iclk_pi_range = 64; | |
3773 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3774 | ||
12d7ceed | 3775 | desired_divisor = (iclk_virtual_root_freq / clock); |
e615efe4 ED |
3776 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3777 | pi_value = desired_divisor % iclk_pi_range; | |
3778 | ||
3779 | auxdiv = 0; | |
3780 | divsel = msb_divisor_value - 2; | |
3781 | phaseinc = pi_value; | |
3782 | } | |
3783 | ||
3784 | /* This should not happen with any sane values */ | |
3785 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3786 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3787 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3788 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3789 | ||
3790 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3791 | clock, |
e615efe4 ED |
3792 | auxdiv, |
3793 | divsel, | |
3794 | phasedir, | |
3795 | phaseinc); | |
3796 | ||
3797 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 3798 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3799 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3800 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3801 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3802 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3803 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3804 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3805 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3806 | |
3807 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3808 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3809 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3810 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3811 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3812 | |
3813 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3814 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3815 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3816 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
3817 | |
3818 | /* Wait for initialization time */ | |
3819 | udelay(24); | |
3820 | ||
3821 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 DV |
3822 | |
3823 | mutex_unlock(&dev_priv->dpio_lock); | |
e615efe4 ED |
3824 | } |
3825 | ||
275f01b2 DV |
3826 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
3827 | enum pipe pch_transcoder) | |
3828 | { | |
3829 | struct drm_device *dev = crtc->base.dev; | |
3830 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 3831 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
3832 | |
3833 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
3834 | I915_READ(HTOTAL(cpu_transcoder))); | |
3835 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
3836 | I915_READ(HBLANK(cpu_transcoder))); | |
3837 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
3838 | I915_READ(HSYNC(cpu_transcoder))); | |
3839 | ||
3840 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
3841 | I915_READ(VTOTAL(cpu_transcoder))); | |
3842 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
3843 | I915_READ(VBLANK(cpu_transcoder))); | |
3844 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
3845 | I915_READ(VSYNC(cpu_transcoder))); | |
3846 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
3847 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
3848 | } | |
3849 | ||
003632d9 | 3850 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 DV |
3851 | { |
3852 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3853 | uint32_t temp; | |
3854 | ||
3855 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 3856 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
3857 | return; |
3858 | ||
3859 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
3860 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
3861 | ||
003632d9 ACO |
3862 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
3863 | if (enable) | |
3864 | temp |= FDI_BC_BIFURCATION_SELECT; | |
3865 | ||
3866 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
3867 | I915_WRITE(SOUTH_CHICKEN1, temp); |
3868 | POSTING_READ(SOUTH_CHICKEN1); | |
3869 | } | |
3870 | ||
3871 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
3872 | { | |
3873 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
3874 | |
3875 | switch (intel_crtc->pipe) { | |
3876 | case PIPE_A: | |
3877 | break; | |
3878 | case PIPE_B: | |
6e3c9717 | 3879 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 3880 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 3881 | else |
003632d9 | 3882 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
3883 | |
3884 | break; | |
3885 | case PIPE_C: | |
003632d9 | 3886 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
3887 | |
3888 | break; | |
3889 | default: | |
3890 | BUG(); | |
3891 | } | |
3892 | } | |
3893 | ||
f67a559d JB |
3894 | /* |
3895 | * Enable PCH resources required for PCH ports: | |
3896 | * - PCH PLLs | |
3897 | * - FDI training & RX/TX | |
3898 | * - update transcoder timings | |
3899 | * - DP transcoding bits | |
3900 | * - transcoder | |
3901 | */ | |
3902 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
3903 | { |
3904 | struct drm_device *dev = crtc->dev; | |
3905 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3906 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3907 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 3908 | u32 reg, temp; |
2c07245f | 3909 | |
ab9412ba | 3910 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 3911 | |
1fbc0d78 DV |
3912 | if (IS_IVYBRIDGE(dev)) |
3913 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
3914 | ||
cd986abb DV |
3915 | /* Write the TU size bits before fdi link training, so that error |
3916 | * detection works. */ | |
3917 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
3918 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
3919 | ||
c98e9dcf | 3920 | /* For PCH output, training FDI link */ |
674cf967 | 3921 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 3922 | |
3ad8a208 DV |
3923 | /* We need to program the right clock selection before writing the pixel |
3924 | * mutliplier into the DPLL. */ | |
303b81e0 | 3925 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 3926 | u32 sel; |
4b645f14 | 3927 | |
c98e9dcf | 3928 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
3929 | temp |= TRANS_DPLL_ENABLE(pipe); |
3930 | sel = TRANS_DPLLB_SEL(pipe); | |
6e3c9717 | 3931 | if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
3932 | temp |= sel; |
3933 | else | |
3934 | temp &= ~sel; | |
c98e9dcf | 3935 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 3936 | } |
5eddb70b | 3937 | |
3ad8a208 DV |
3938 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
3939 | * transcoder, and we actually should do this to not upset any PCH | |
3940 | * transcoder that already use the clock when we share it. | |
3941 | * | |
3942 | * Note that enable_shared_dpll tries to do the right thing, but | |
3943 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
3944 | * the right LVDS enable sequence. */ | |
85b3894f | 3945 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 3946 | |
d9b6cb56 JB |
3947 | /* set transcoder timing, panel must allow it */ |
3948 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 3949 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 3950 | |
303b81e0 | 3951 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 3952 | |
c98e9dcf | 3953 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e3c9717 | 3954 | if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { |
dfd07d72 | 3955 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
3956 | reg = TRANS_DP_CTL(pipe); |
3957 | temp = I915_READ(reg); | |
3958 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
3959 | TRANS_DP_SYNC_MASK | |
3960 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
3961 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3962 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 3963 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
3964 | |
3965 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 3966 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 3967 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 3968 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
3969 | |
3970 | switch (intel_trans_dp_port_sel(crtc)) { | |
3971 | case PCH_DP_B: | |
5eddb70b | 3972 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
3973 | break; |
3974 | case PCH_DP_C: | |
5eddb70b | 3975 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
3976 | break; |
3977 | case PCH_DP_D: | |
5eddb70b | 3978 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
3979 | break; |
3980 | default: | |
e95d41e1 | 3981 | BUG(); |
32f9d658 | 3982 | } |
2c07245f | 3983 | |
5eddb70b | 3984 | I915_WRITE(reg, temp); |
6be4a607 | 3985 | } |
b52eb4dc | 3986 | |
b8a4f404 | 3987 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
3988 | } |
3989 | ||
1507e5bd PZ |
3990 | static void lpt_pch_enable(struct drm_crtc *crtc) |
3991 | { | |
3992 | struct drm_device *dev = crtc->dev; | |
3993 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3994 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6e3c9717 | 3995 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 3996 | |
ab9412ba | 3997 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 3998 | |
8c52b5e8 | 3999 | lpt_program_iclkip(crtc); |
1507e5bd | 4000 | |
0540e488 | 4001 | /* Set transcoder timing. */ |
275f01b2 | 4002 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4003 | |
937bb610 | 4004 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4005 | } |
4006 | ||
716c2e55 | 4007 | void intel_put_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 4008 | { |
e2b78267 | 4009 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
ee7b9f93 JB |
4010 | |
4011 | if (pll == NULL) | |
4012 | return; | |
4013 | ||
3e369b76 | 4014 | if (!(pll->config.crtc_mask & (1 << crtc->pipe))) { |
1e6f2ddc | 4015 | WARN(1, "bad %s crtc mask\n", pll->name); |
ee7b9f93 JB |
4016 | return; |
4017 | } | |
4018 | ||
3e369b76 ACO |
4019 | pll->config.crtc_mask &= ~(1 << crtc->pipe); |
4020 | if (pll->config.crtc_mask == 0) { | |
f4a091c7 DV |
4021 | WARN_ON(pll->on); |
4022 | WARN_ON(pll->active); | |
4023 | } | |
4024 | ||
6e3c9717 | 4025 | crtc->config->shared_dpll = DPLL_ID_PRIVATE; |
ee7b9f93 JB |
4026 | } |
4027 | ||
190f68c5 ACO |
4028 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, |
4029 | struct intel_crtc_state *crtc_state) | |
ee7b9f93 | 4030 | { |
e2b78267 | 4031 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
8bd31e67 | 4032 | struct intel_shared_dpll *pll; |
e2b78267 | 4033 | enum intel_dpll_id i; |
ee7b9f93 | 4034 | |
98b6bd99 DV |
4035 | if (HAS_PCH_IBX(dev_priv->dev)) { |
4036 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 4037 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 4038 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 4039 | |
46edb027 DV |
4040 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
4041 | crtc->base.base.id, pll->name); | |
98b6bd99 | 4042 | |
8bd31e67 | 4043 | WARN_ON(pll->new_config->crtc_mask); |
f2a69f44 | 4044 | |
98b6bd99 DV |
4045 | goto found; |
4046 | } | |
4047 | ||
e72f9fbf DV |
4048 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4049 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 JB |
4050 | |
4051 | /* Only want to check enabled timings first */ | |
8bd31e67 | 4052 | if (pll->new_config->crtc_mask == 0) |
ee7b9f93 JB |
4053 | continue; |
4054 | ||
190f68c5 | 4055 | if (memcmp(&crtc_state->dpll_hw_state, |
8bd31e67 ACO |
4056 | &pll->new_config->hw_state, |
4057 | sizeof(pll->new_config->hw_state)) == 0) { | |
4058 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n", | |
1e6f2ddc | 4059 | crtc->base.base.id, pll->name, |
8bd31e67 ACO |
4060 | pll->new_config->crtc_mask, |
4061 | pll->active); | |
ee7b9f93 JB |
4062 | goto found; |
4063 | } | |
4064 | } | |
4065 | ||
4066 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
4067 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4068 | pll = &dev_priv->shared_dplls[i]; | |
8bd31e67 | 4069 | if (pll->new_config->crtc_mask == 0) { |
46edb027 DV |
4070 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
4071 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
4072 | goto found; |
4073 | } | |
4074 | } | |
4075 | ||
4076 | return NULL; | |
4077 | ||
4078 | found: | |
8bd31e67 | 4079 | if (pll->new_config->crtc_mask == 0) |
190f68c5 | 4080 | pll->new_config->hw_state = crtc_state->dpll_hw_state; |
f2a69f44 | 4081 | |
190f68c5 | 4082 | crtc_state->shared_dpll = i; |
46edb027 DV |
4083 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
4084 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 4085 | |
8bd31e67 | 4086 | pll->new_config->crtc_mask |= 1 << crtc->pipe; |
e04c7350 | 4087 | |
ee7b9f93 JB |
4088 | return pll; |
4089 | } | |
4090 | ||
8bd31e67 ACO |
4091 | /** |
4092 | * intel_shared_dpll_start_config - start a new PLL staged config | |
4093 | * @dev_priv: DRM device | |
4094 | * @clear_pipes: mask of pipes that will have their PLLs freed | |
4095 | * | |
4096 | * Starts a new PLL staged config, copying the current config but | |
4097 | * releasing the references of pipes specified in clear_pipes. | |
4098 | */ | |
4099 | static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv, | |
4100 | unsigned clear_pipes) | |
4101 | { | |
4102 | struct intel_shared_dpll *pll; | |
4103 | enum intel_dpll_id i; | |
4104 | ||
4105 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
4106 | pll = &dev_priv->shared_dplls[i]; | |
4107 | ||
4108 | pll->new_config = kmemdup(&pll->config, sizeof pll->config, | |
4109 | GFP_KERNEL); | |
4110 | if (!pll->new_config) | |
4111 | goto cleanup; | |
4112 | ||
4113 | pll->new_config->crtc_mask &= ~clear_pipes; | |
4114 | } | |
4115 | ||
4116 | return 0; | |
4117 | ||
4118 | cleanup: | |
4119 | while (--i >= 0) { | |
4120 | pll = &dev_priv->shared_dplls[i]; | |
f354d733 | 4121 | kfree(pll->new_config); |
8bd31e67 ACO |
4122 | pll->new_config = NULL; |
4123 | } | |
4124 | ||
4125 | return -ENOMEM; | |
4126 | } | |
4127 | ||
4128 | static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv) | |
4129 | { | |
4130 | struct intel_shared_dpll *pll; | |
4131 | enum intel_dpll_id i; | |
4132 | ||
4133 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
4134 | pll = &dev_priv->shared_dplls[i]; | |
4135 | ||
4136 | WARN_ON(pll->new_config == &pll->config); | |
4137 | ||
4138 | pll->config = *pll->new_config; | |
4139 | kfree(pll->new_config); | |
4140 | pll->new_config = NULL; | |
4141 | } | |
4142 | } | |
4143 | ||
4144 | static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv) | |
4145 | { | |
4146 | struct intel_shared_dpll *pll; | |
4147 | enum intel_dpll_id i; | |
4148 | ||
4149 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
4150 | pll = &dev_priv->shared_dplls[i]; | |
4151 | ||
4152 | WARN_ON(pll->new_config == &pll->config); | |
4153 | ||
4154 | kfree(pll->new_config); | |
4155 | pll->new_config = NULL; | |
4156 | } | |
4157 | } | |
4158 | ||
a1520318 | 4159 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
4160 | { |
4161 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 4162 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4163 | u32 temp; |
4164 | ||
4165 | temp = I915_READ(dslreg); | |
4166 | udelay(500); | |
4167 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4168 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4169 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4170 | } |
4171 | } | |
4172 | ||
bd2e244f JB |
4173 | static void skylake_pfit_enable(struct intel_crtc *crtc) |
4174 | { | |
4175 | struct drm_device *dev = crtc->base.dev; | |
4176 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4177 | int pipe = crtc->pipe; | |
4178 | ||
6e3c9717 | 4179 | if (crtc->config->pch_pfit.enabled) { |
bd2e244f | 4180 | I915_WRITE(PS_CTL(pipe), PS_ENABLE); |
6e3c9717 ACO |
4181 | I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4182 | I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
bd2e244f JB |
4183 | } |
4184 | } | |
4185 | ||
b074cec8 JB |
4186 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4187 | { | |
4188 | struct drm_device *dev = crtc->base.dev; | |
4189 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4190 | int pipe = crtc->pipe; | |
4191 | ||
6e3c9717 | 4192 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4193 | /* Force use of hard-coded filter coefficients |
4194 | * as some pre-programmed values are broken, | |
4195 | * e.g. x201. | |
4196 | */ | |
4197 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4198 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4199 | PF_PIPE_SEL_IVB(pipe)); | |
4200 | else | |
4201 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4202 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4203 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4204 | } |
4205 | } | |
4206 | ||
4a3b8769 | 4207 | static void intel_enable_sprite_planes(struct drm_crtc *crtc) |
bb53d4ae VS |
4208 | { |
4209 | struct drm_device *dev = crtc->dev; | |
4210 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 4211 | struct drm_plane *plane; |
bb53d4ae VS |
4212 | struct intel_plane *intel_plane; |
4213 | ||
af2b653b MR |
4214 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
4215 | intel_plane = to_intel_plane(plane); | |
bb53d4ae VS |
4216 | if (intel_plane->pipe == pipe) |
4217 | intel_plane_restore(&intel_plane->base); | |
af2b653b | 4218 | } |
bb53d4ae VS |
4219 | } |
4220 | ||
0d703d4e MR |
4221 | /* |
4222 | * Disable a plane internally without actually modifying the plane's state. | |
4223 | * This will allow us to easily restore the plane later by just reprogramming | |
4224 | * its state. | |
4225 | */ | |
4226 | static void disable_plane_internal(struct drm_plane *plane) | |
4227 | { | |
4228 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
4229 | struct drm_plane_state *state = | |
4230 | plane->funcs->atomic_duplicate_state(plane); | |
4231 | struct intel_plane_state *intel_state = to_intel_plane_state(state); | |
4232 | ||
4233 | intel_state->visible = false; | |
4234 | intel_plane->commit_plane(plane, intel_state); | |
4235 | ||
4236 | intel_plane_destroy_state(plane, state); | |
4237 | } | |
4238 | ||
4a3b8769 | 4239 | static void intel_disable_sprite_planes(struct drm_crtc *crtc) |
bb53d4ae VS |
4240 | { |
4241 | struct drm_device *dev = crtc->dev; | |
4242 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 4243 | struct drm_plane *plane; |
bb53d4ae VS |
4244 | struct intel_plane *intel_plane; |
4245 | ||
af2b653b MR |
4246 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
4247 | intel_plane = to_intel_plane(plane); | |
0d703d4e MR |
4248 | if (plane->fb && intel_plane->pipe == pipe) |
4249 | disable_plane_internal(plane); | |
af2b653b | 4250 | } |
bb53d4ae VS |
4251 | } |
4252 | ||
20bc8673 | 4253 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4254 | { |
cea165c3 VS |
4255 | struct drm_device *dev = crtc->base.dev; |
4256 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 | 4257 | |
6e3c9717 | 4258 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4259 | return; |
4260 | ||
cea165c3 VS |
4261 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
4262 | intel_wait_for_vblank(dev, crtc->pipe); | |
4263 | ||
d77e4531 | 4264 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4265 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4266 | mutex_lock(&dev_priv->rps.hw_lock); |
4267 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4268 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4269 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4270 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4271 | * mailbox." Moreover, the mailbox may return a bogus state, |
4272 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4273 | */ |
4274 | } else { | |
4275 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4276 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4277 | * is essentially intel_wait_for_vblank. If we don't have this | |
4278 | * and don't wait for vblanks until the end of crtc_enable, then | |
4279 | * the HW state readout code will complain that the expected | |
4280 | * IPS_CTL value is not the one we read. */ | |
4281 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
4282 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
4283 | } | |
d77e4531 PZ |
4284 | } |
4285 | ||
20bc8673 | 4286 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4287 | { |
4288 | struct drm_device *dev = crtc->base.dev; | |
4289 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4290 | ||
6e3c9717 | 4291 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4292 | return; |
4293 | ||
4294 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4295 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4296 | mutex_lock(&dev_priv->rps.hw_lock); |
4297 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4298 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
4299 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
4300 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
4301 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 4302 | } else { |
2a114cc1 | 4303 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4304 | POSTING_READ(IPS_CTL); |
4305 | } | |
d77e4531 PZ |
4306 | |
4307 | /* We need to wait for a vblank before we can disable the plane. */ | |
4308 | intel_wait_for_vblank(dev, crtc->pipe); | |
4309 | } | |
4310 | ||
4311 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
4312 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
4313 | { | |
4314 | struct drm_device *dev = crtc->dev; | |
4315 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4316 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4317 | enum pipe pipe = intel_crtc->pipe; | |
4318 | int palreg = PALETTE(pipe); | |
4319 | int i; | |
4320 | bool reenable_ips = false; | |
4321 | ||
4322 | /* The clocks have to be on to load the palette. */ | |
83d65738 | 4323 | if (!crtc->state->enable || !intel_crtc->active) |
d77e4531 PZ |
4324 | return; |
4325 | ||
4326 | if (!HAS_PCH_SPLIT(dev_priv->dev)) { | |
409ee761 | 4327 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) |
d77e4531 PZ |
4328 | assert_dsi_pll_enabled(dev_priv); |
4329 | else | |
4330 | assert_pll_enabled(dev_priv, pipe); | |
4331 | } | |
4332 | ||
4333 | /* use legacy palette for Ironlake */ | |
7a1db49a | 4334 | if (!HAS_GMCH_DISPLAY(dev)) |
d77e4531 PZ |
4335 | palreg = LGC_PALETTE(pipe); |
4336 | ||
4337 | /* Workaround : Do not read or write the pipe palette/gamma data while | |
4338 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
4339 | */ | |
6e3c9717 | 4340 | if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled && |
d77e4531 PZ |
4341 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
4342 | GAMMA_MODE_MODE_SPLIT)) { | |
4343 | hsw_disable_ips(intel_crtc); | |
4344 | reenable_ips = true; | |
4345 | } | |
4346 | ||
4347 | for (i = 0; i < 256; i++) { | |
4348 | I915_WRITE(palreg + 4 * i, | |
4349 | (intel_crtc->lut_r[i] << 16) | | |
4350 | (intel_crtc->lut_g[i] << 8) | | |
4351 | intel_crtc->lut_b[i]); | |
4352 | } | |
4353 | ||
4354 | if (reenable_ips) | |
4355 | hsw_enable_ips(intel_crtc); | |
4356 | } | |
4357 | ||
d3eedb1a VS |
4358 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
4359 | { | |
4360 | if (!enable && intel_crtc->overlay) { | |
4361 | struct drm_device *dev = intel_crtc->base.dev; | |
4362 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4363 | ||
4364 | mutex_lock(&dev->struct_mutex); | |
4365 | dev_priv->mm.interruptible = false; | |
4366 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4367 | dev_priv->mm.interruptible = true; | |
4368 | mutex_unlock(&dev->struct_mutex); | |
4369 | } | |
4370 | ||
4371 | /* Let userspace switch the overlay on again. In most cases userspace | |
4372 | * has to recompute where to put it anyway. | |
4373 | */ | |
4374 | } | |
4375 | ||
d3eedb1a | 4376 | static void intel_crtc_enable_planes(struct drm_crtc *crtc) |
a5c4d7bc VS |
4377 | { |
4378 | struct drm_device *dev = crtc->dev; | |
a5c4d7bc VS |
4379 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4380 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4381 | |
fdd508a6 | 4382 | intel_enable_primary_hw_plane(crtc->primary, crtc); |
4a3b8769 | 4383 | intel_enable_sprite_planes(crtc); |
a5c4d7bc | 4384 | intel_crtc_update_cursor(crtc, true); |
d3eedb1a | 4385 | intel_crtc_dpms_overlay(intel_crtc, true); |
a5c4d7bc VS |
4386 | |
4387 | hsw_enable_ips(intel_crtc); | |
4388 | ||
4389 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 4390 | intel_fbc_update(dev); |
a5c4d7bc | 4391 | mutex_unlock(&dev->struct_mutex); |
f99d7069 DV |
4392 | |
4393 | /* | |
4394 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4395 | * to compute the mask of flip planes precisely. For the time being | |
4396 | * consider this a flip from a NULL plane. | |
4397 | */ | |
4398 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4399 | } |
4400 | ||
d3eedb1a | 4401 | static void intel_crtc_disable_planes(struct drm_crtc *crtc) |
a5c4d7bc VS |
4402 | { |
4403 | struct drm_device *dev = crtc->dev; | |
4404 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4405 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4406 | int pipe = intel_crtc->pipe; | |
a5c4d7bc VS |
4407 | |
4408 | intel_crtc_wait_for_pending_flips(crtc); | |
a5c4d7bc | 4409 | |
e35fef21 | 4410 | if (dev_priv->fbc.crtc == intel_crtc) |
7ff0ebcc | 4411 | intel_fbc_disable(dev); |
a5c4d7bc VS |
4412 | |
4413 | hsw_disable_ips(intel_crtc); | |
4414 | ||
d3eedb1a | 4415 | intel_crtc_dpms_overlay(intel_crtc, false); |
a5c4d7bc | 4416 | intel_crtc_update_cursor(crtc, false); |
4a3b8769 | 4417 | intel_disable_sprite_planes(crtc); |
fdd508a6 | 4418 | intel_disable_primary_hw_plane(crtc->primary, crtc); |
f98551ae | 4419 | |
f99d7069 DV |
4420 | /* |
4421 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4422 | * to compute the mask of flip planes precisely. For the time being | |
4423 | * consider this a flip to a NULL plane. | |
4424 | */ | |
4425 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4426 | } |
4427 | ||
f67a559d JB |
4428 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4429 | { | |
4430 | struct drm_device *dev = crtc->dev; | |
4431 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4432 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4433 | struct intel_encoder *encoder; |
f67a559d | 4434 | int pipe = intel_crtc->pipe; |
f67a559d | 4435 | |
83d65738 | 4436 | WARN_ON(!crtc->state->enable); |
08a48469 | 4437 | |
f67a559d JB |
4438 | if (intel_crtc->active) |
4439 | return; | |
4440 | ||
6e3c9717 | 4441 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
4442 | intel_prepare_shared_dpll(intel_crtc); |
4443 | ||
6e3c9717 | 4444 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4445 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
4446 | |
4447 | intel_set_pipe_timings(intel_crtc); | |
4448 | ||
6e3c9717 | 4449 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 4450 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4451 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
4452 | } |
4453 | ||
4454 | ironlake_set_pipeconf(crtc); | |
4455 | ||
f67a559d | 4456 | intel_crtc->active = true; |
8664281b | 4457 | |
a72e4c9f DV |
4458 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4459 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
8664281b | 4460 | |
f6736a1a | 4461 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4462 | if (encoder->pre_enable) |
4463 | encoder->pre_enable(encoder); | |
f67a559d | 4464 | |
6e3c9717 | 4465 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
4466 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4467 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4468 | * enabling. */ | |
88cefb6c | 4469 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4470 | } else { |
4471 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4472 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4473 | } | |
f67a559d | 4474 | |
b074cec8 | 4475 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4476 | |
9c54c0dd JB |
4477 | /* |
4478 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4479 | * clocks enabled | |
4480 | */ | |
4481 | intel_crtc_load_lut(crtc); | |
4482 | ||
f37fcc2a | 4483 | intel_update_watermarks(crtc); |
e1fdc473 | 4484 | intel_enable_pipe(intel_crtc); |
f67a559d | 4485 | |
6e3c9717 | 4486 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 4487 | ironlake_pch_enable(crtc); |
c98e9dcf | 4488 | |
f9b61ff6 DV |
4489 | assert_vblank_disabled(crtc); |
4490 | drm_crtc_vblank_on(crtc); | |
4491 | ||
fa5c73b1 DV |
4492 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4493 | encoder->enable(encoder); | |
61b77ddd DV |
4494 | |
4495 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4496 | cpt_verify_modeset(dev, intel_crtc->pipe); |
6ce94100 | 4497 | |
d3eedb1a | 4498 | intel_crtc_enable_planes(crtc); |
6be4a607 JB |
4499 | } |
4500 | ||
42db64ef PZ |
4501 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4502 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4503 | { | |
f5adf94e | 4504 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4505 | } |
4506 | ||
e4916946 PZ |
4507 | /* |
4508 | * This implements the workaround described in the "notes" section of the mode | |
4509 | * set sequence documentation. When going from no pipes or single pipe to | |
4510 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
4511 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
4512 | */ | |
4513 | static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) | |
4514 | { | |
4515 | struct drm_device *dev = crtc->base.dev; | |
4516 | struct intel_crtc *crtc_it, *other_active_crtc = NULL; | |
4517 | ||
4518 | /* We want to get the other_active_crtc only if there's only 1 other | |
4519 | * active crtc. */ | |
d3fcc808 | 4520 | for_each_intel_crtc(dev, crtc_it) { |
e4916946 PZ |
4521 | if (!crtc_it->active || crtc_it == crtc) |
4522 | continue; | |
4523 | ||
4524 | if (other_active_crtc) | |
4525 | return; | |
4526 | ||
4527 | other_active_crtc = crtc_it; | |
4528 | } | |
4529 | if (!other_active_crtc) | |
4530 | return; | |
4531 | ||
4532 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4533 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4534 | } | |
4535 | ||
4f771f10 PZ |
4536 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4537 | { | |
4538 | struct drm_device *dev = crtc->dev; | |
4539 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4540 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4541 | struct intel_encoder *encoder; | |
4542 | int pipe = intel_crtc->pipe; | |
4f771f10 | 4543 | |
83d65738 | 4544 | WARN_ON(!crtc->state->enable); |
4f771f10 PZ |
4545 | |
4546 | if (intel_crtc->active) | |
4547 | return; | |
4548 | ||
df8ad70c DV |
4549 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
4550 | intel_enable_shared_dpll(intel_crtc); | |
4551 | ||
6e3c9717 | 4552 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4553 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 DV |
4554 | |
4555 | intel_set_pipe_timings(intel_crtc); | |
4556 | ||
6e3c9717 ACO |
4557 | if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) { |
4558 | I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder), | |
4559 | intel_crtc->config->pixel_multiplier - 1); | |
ebb69c95 CT |
4560 | } |
4561 | ||
6e3c9717 | 4562 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 4563 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4564 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
4565 | } |
4566 | ||
4567 | haswell_set_pipeconf(crtc); | |
4568 | ||
4569 | intel_set_pipe_csc(crtc); | |
4570 | ||
4f771f10 | 4571 | intel_crtc->active = true; |
8664281b | 4572 | |
a72e4c9f | 4573 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4f771f10 PZ |
4574 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4575 | if (encoder->pre_enable) | |
4576 | encoder->pre_enable(encoder); | |
4577 | ||
6e3c9717 | 4578 | if (intel_crtc->config->has_pch_encoder) { |
a72e4c9f DV |
4579 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
4580 | true); | |
4fe9467d ID |
4581 | dev_priv->display.fdi_link_train(crtc); |
4582 | } | |
4583 | ||
1f544388 | 4584 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 4585 | |
bd2e244f JB |
4586 | if (IS_SKYLAKE(dev)) |
4587 | skylake_pfit_enable(intel_crtc); | |
4588 | else | |
4589 | ironlake_pfit_enable(intel_crtc); | |
4f771f10 PZ |
4590 | |
4591 | /* | |
4592 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4593 | * clocks enabled | |
4594 | */ | |
4595 | intel_crtc_load_lut(crtc); | |
4596 | ||
1f544388 | 4597 | intel_ddi_set_pipe_settings(crtc); |
8228c251 | 4598 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 4599 | |
f37fcc2a | 4600 | intel_update_watermarks(crtc); |
e1fdc473 | 4601 | intel_enable_pipe(intel_crtc); |
42db64ef | 4602 | |
6e3c9717 | 4603 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 4604 | lpt_pch_enable(crtc); |
4f771f10 | 4605 | |
6e3c9717 | 4606 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
4607 | intel_ddi_set_vc_payload_alloc(crtc, true); |
4608 | ||
f9b61ff6 DV |
4609 | assert_vblank_disabled(crtc); |
4610 | drm_crtc_vblank_on(crtc); | |
4611 | ||
8807e55b | 4612 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 4613 | encoder->enable(encoder); |
8807e55b JN |
4614 | intel_opregion_notify_encoder(encoder, true); |
4615 | } | |
4f771f10 | 4616 | |
e4916946 PZ |
4617 | /* If we change the relative order between pipe/planes enabling, we need |
4618 | * to change the workaround. */ | |
4619 | haswell_mode_set_planes_workaround(intel_crtc); | |
d3eedb1a | 4620 | intel_crtc_enable_planes(crtc); |
4f771f10 PZ |
4621 | } |
4622 | ||
bd2e244f JB |
4623 | static void skylake_pfit_disable(struct intel_crtc *crtc) |
4624 | { | |
4625 | struct drm_device *dev = crtc->base.dev; | |
4626 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4627 | int pipe = crtc->pipe; | |
4628 | ||
4629 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
4630 | * it's in use. The hw state code will make sure we get this right. */ | |
6e3c9717 | 4631 | if (crtc->config->pch_pfit.enabled) { |
bd2e244f JB |
4632 | I915_WRITE(PS_CTL(pipe), 0); |
4633 | I915_WRITE(PS_WIN_POS(pipe), 0); | |
4634 | I915_WRITE(PS_WIN_SZ(pipe), 0); | |
4635 | } | |
4636 | } | |
4637 | ||
3f8dce3a DV |
4638 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
4639 | { | |
4640 | struct drm_device *dev = crtc->base.dev; | |
4641 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4642 | int pipe = crtc->pipe; | |
4643 | ||
4644 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
4645 | * it's in use. The hw state code will make sure we get this right. */ | |
6e3c9717 | 4646 | if (crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
4647 | I915_WRITE(PF_CTL(pipe), 0); |
4648 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
4649 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
4650 | } | |
4651 | } | |
4652 | ||
6be4a607 JB |
4653 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
4654 | { | |
4655 | struct drm_device *dev = crtc->dev; | |
4656 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4657 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4658 | struct intel_encoder *encoder; |
6be4a607 | 4659 | int pipe = intel_crtc->pipe; |
5eddb70b | 4660 | u32 reg, temp; |
b52eb4dc | 4661 | |
f7abfe8b CW |
4662 | if (!intel_crtc->active) |
4663 | return; | |
4664 | ||
d3eedb1a | 4665 | intel_crtc_disable_planes(crtc); |
a5c4d7bc | 4666 | |
ea9d758d DV |
4667 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4668 | encoder->disable(encoder); | |
4669 | ||
f9b61ff6 DV |
4670 | drm_crtc_vblank_off(crtc); |
4671 | assert_vblank_disabled(crtc); | |
4672 | ||
6e3c9717 | 4673 | if (intel_crtc->config->has_pch_encoder) |
a72e4c9f | 4674 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
d925c59a | 4675 | |
575f7ab7 | 4676 | intel_disable_pipe(intel_crtc); |
32f9d658 | 4677 | |
3f8dce3a | 4678 | ironlake_pfit_disable(intel_crtc); |
2c07245f | 4679 | |
bf49ec8c DV |
4680 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4681 | if (encoder->post_disable) | |
4682 | encoder->post_disable(encoder); | |
2c07245f | 4683 | |
6e3c9717 | 4684 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 4685 | ironlake_fdi_disable(crtc); |
913d8d11 | 4686 | |
d925c59a | 4687 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 4688 | |
d925c59a DV |
4689 | if (HAS_PCH_CPT(dev)) { |
4690 | /* disable TRANS_DP_CTL */ | |
4691 | reg = TRANS_DP_CTL(pipe); | |
4692 | temp = I915_READ(reg); | |
4693 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
4694 | TRANS_DP_PORT_SEL_MASK); | |
4695 | temp |= TRANS_DP_PORT_SEL_NONE; | |
4696 | I915_WRITE(reg, temp); | |
4697 | ||
4698 | /* disable DPLL_SEL */ | |
4699 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 4700 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 4701 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 4702 | } |
e3421a18 | 4703 | |
d925c59a | 4704 | /* disable PCH DPLL */ |
e72f9fbf | 4705 | intel_disable_shared_dpll(intel_crtc); |
8db9d77b | 4706 | |
d925c59a DV |
4707 | ironlake_fdi_pll_disable(intel_crtc); |
4708 | } | |
6b383a7f | 4709 | |
f7abfe8b | 4710 | intel_crtc->active = false; |
46ba614c | 4711 | intel_update_watermarks(crtc); |
d1ebd816 BW |
4712 | |
4713 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 4714 | intel_fbc_update(dev); |
d1ebd816 | 4715 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 4716 | } |
1b3c7a47 | 4717 | |
4f771f10 | 4718 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 4719 | { |
4f771f10 PZ |
4720 | struct drm_device *dev = crtc->dev; |
4721 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 4722 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 4723 | struct intel_encoder *encoder; |
6e3c9717 | 4724 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 4725 | |
4f771f10 PZ |
4726 | if (!intel_crtc->active) |
4727 | return; | |
4728 | ||
d3eedb1a | 4729 | intel_crtc_disable_planes(crtc); |
dda9a66a | 4730 | |
8807e55b JN |
4731 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4732 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 4733 | encoder->disable(encoder); |
8807e55b | 4734 | } |
4f771f10 | 4735 | |
f9b61ff6 DV |
4736 | drm_crtc_vblank_off(crtc); |
4737 | assert_vblank_disabled(crtc); | |
4738 | ||
6e3c9717 | 4739 | if (intel_crtc->config->has_pch_encoder) |
a72e4c9f DV |
4740 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
4741 | false); | |
575f7ab7 | 4742 | intel_disable_pipe(intel_crtc); |
4f771f10 | 4743 | |
6e3c9717 | 4744 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
4745 | intel_ddi_set_vc_payload_alloc(crtc, false); |
4746 | ||
ad80a810 | 4747 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 4748 | |
bd2e244f JB |
4749 | if (IS_SKYLAKE(dev)) |
4750 | skylake_pfit_disable(intel_crtc); | |
4751 | else | |
4752 | ironlake_pfit_disable(intel_crtc); | |
4f771f10 | 4753 | |
1f544388 | 4754 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 4755 | |
6e3c9717 | 4756 | if (intel_crtc->config->has_pch_encoder) { |
ab4d966c | 4757 | lpt_disable_pch_transcoder(dev_priv); |
1ad960f2 | 4758 | intel_ddi_fdi_disable(crtc); |
83616634 | 4759 | } |
4f771f10 | 4760 | |
97b040aa ID |
4761 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4762 | if (encoder->post_disable) | |
4763 | encoder->post_disable(encoder); | |
4764 | ||
4f771f10 | 4765 | intel_crtc->active = false; |
46ba614c | 4766 | intel_update_watermarks(crtc); |
4f771f10 PZ |
4767 | |
4768 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 4769 | intel_fbc_update(dev); |
4f771f10 | 4770 | mutex_unlock(&dev->struct_mutex); |
df8ad70c DV |
4771 | |
4772 | if (intel_crtc_to_shared_dpll(intel_crtc)) | |
4773 | intel_disable_shared_dpll(intel_crtc); | |
4f771f10 PZ |
4774 | } |
4775 | ||
ee7b9f93 JB |
4776 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
4777 | { | |
4778 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e72f9fbf | 4779 | intel_put_shared_dpll(intel_crtc); |
ee7b9f93 JB |
4780 | } |
4781 | ||
6441ab5f | 4782 | |
2dd24552 JB |
4783 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
4784 | { | |
4785 | struct drm_device *dev = crtc->base.dev; | |
4786 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 4787 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 4788 | |
681a8504 | 4789 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
4790 | return; |
4791 | ||
2dd24552 | 4792 | /* |
c0b03411 DV |
4793 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
4794 | * according to register description and PRM. | |
2dd24552 | 4795 | */ |
c0b03411 DV |
4796 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
4797 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 4798 | |
b074cec8 JB |
4799 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
4800 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
4801 | |
4802 | /* Border color in case we don't scale up to the full screen. Black by | |
4803 | * default, change to something else for debugging. */ | |
4804 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
4805 | } |
4806 | ||
d05410f9 DA |
4807 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
4808 | { | |
4809 | switch (port) { | |
4810 | case PORT_A: | |
4811 | return POWER_DOMAIN_PORT_DDI_A_4_LANES; | |
4812 | case PORT_B: | |
4813 | return POWER_DOMAIN_PORT_DDI_B_4_LANES; | |
4814 | case PORT_C: | |
4815 | return POWER_DOMAIN_PORT_DDI_C_4_LANES; | |
4816 | case PORT_D: | |
4817 | return POWER_DOMAIN_PORT_DDI_D_4_LANES; | |
4818 | default: | |
4819 | WARN_ON_ONCE(1); | |
4820 | return POWER_DOMAIN_PORT_OTHER; | |
4821 | } | |
4822 | } | |
4823 | ||
77d22dca ID |
4824 | #define for_each_power_domain(domain, mask) \ |
4825 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
4826 | if ((1 << (domain)) & (mask)) | |
4827 | ||
319be8ae ID |
4828 | enum intel_display_power_domain |
4829 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
4830 | { | |
4831 | struct drm_device *dev = intel_encoder->base.dev; | |
4832 | struct intel_digital_port *intel_dig_port; | |
4833 | ||
4834 | switch (intel_encoder->type) { | |
4835 | case INTEL_OUTPUT_UNKNOWN: | |
4836 | /* Only DDI platforms should ever use this output type */ | |
4837 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
4838 | case INTEL_OUTPUT_DISPLAYPORT: | |
4839 | case INTEL_OUTPUT_HDMI: | |
4840 | case INTEL_OUTPUT_EDP: | |
4841 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 4842 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
4843 | case INTEL_OUTPUT_DP_MST: |
4844 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
4845 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
4846 | case INTEL_OUTPUT_ANALOG: |
4847 | return POWER_DOMAIN_PORT_CRT; | |
4848 | case INTEL_OUTPUT_DSI: | |
4849 | return POWER_DOMAIN_PORT_DSI; | |
4850 | default: | |
4851 | return POWER_DOMAIN_PORT_OTHER; | |
4852 | } | |
4853 | } | |
4854 | ||
4855 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) | |
77d22dca | 4856 | { |
319be8ae ID |
4857 | struct drm_device *dev = crtc->dev; |
4858 | struct intel_encoder *intel_encoder; | |
4859 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4860 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca ID |
4861 | unsigned long mask; |
4862 | enum transcoder transcoder; | |
4863 | ||
4864 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); | |
4865 | ||
4866 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); | |
4867 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
6e3c9717 ACO |
4868 | if (intel_crtc->config->pch_pfit.enabled || |
4869 | intel_crtc->config->pch_pfit.force_thru) | |
77d22dca ID |
4870 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
4871 | ||
319be8ae ID |
4872 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
4873 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); | |
4874 | ||
77d22dca ID |
4875 | return mask; |
4876 | } | |
4877 | ||
77d22dca ID |
4878 | static void modeset_update_crtc_power_domains(struct drm_device *dev) |
4879 | { | |
4880 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4881 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; | |
4882 | struct intel_crtc *crtc; | |
4883 | ||
4884 | /* | |
4885 | * First get all needed power domains, then put all unneeded, to avoid | |
4886 | * any unnecessary toggling of the power wells. | |
4887 | */ | |
d3fcc808 | 4888 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
4889 | enum intel_display_power_domain domain; |
4890 | ||
83d65738 | 4891 | if (!crtc->base.state->enable) |
77d22dca ID |
4892 | continue; |
4893 | ||
319be8ae | 4894 | pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base); |
77d22dca ID |
4895 | |
4896 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) | |
4897 | intel_display_power_get(dev_priv, domain); | |
4898 | } | |
4899 | ||
50f6e502 VS |
4900 | if (dev_priv->display.modeset_global_resources) |
4901 | dev_priv->display.modeset_global_resources(dev); | |
4902 | ||
d3fcc808 | 4903 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
4904 | enum intel_display_power_domain domain; |
4905 | ||
4906 | for_each_power_domain(domain, crtc->enabled_power_domains) | |
4907 | intel_display_power_put(dev_priv, domain); | |
4908 | ||
4909 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; | |
4910 | } | |
4911 | ||
4912 | intel_display_set_init_power(dev_priv, false); | |
4913 | } | |
4914 | ||
dfcab17e | 4915 | /* returns HPLL frequency in kHz */ |
f8bf63fd | 4916 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) |
30a970c6 | 4917 | { |
586f49dc | 4918 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
30a970c6 | 4919 | |
586f49dc JB |
4920 | /* Obtain SKU information */ |
4921 | mutex_lock(&dev_priv->dpio_lock); | |
4922 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
4923 | CCK_FUSE_HPLL_FREQ_MASK; | |
4924 | mutex_unlock(&dev_priv->dpio_lock); | |
30a970c6 | 4925 | |
dfcab17e | 4926 | return vco_freq[hpll_freq] * 1000; |
30a970c6 JB |
4927 | } |
4928 | ||
f8bf63fd VS |
4929 | static void vlv_update_cdclk(struct drm_device *dev) |
4930 | { | |
4931 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4932 | ||
4933 | dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
43dc52c3 | 4934 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", |
f8bf63fd VS |
4935 | dev_priv->vlv_cdclk_freq); |
4936 | ||
4937 | /* | |
4938 | * Program the gmbus_freq based on the cdclk frequency. | |
4939 | * BSpec erroneously claims we should aim for 4MHz, but | |
4940 | * in fact 1MHz is the correct frequency. | |
4941 | */ | |
6be1e3d3 | 4942 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000)); |
f8bf63fd VS |
4943 | } |
4944 | ||
30a970c6 JB |
4945 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
4946 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
4947 | { | |
4948 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4949 | u32 val, cmd; | |
4950 | ||
d197b7d3 | 4951 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq); |
d60c4473 | 4952 | |
dfcab17e | 4953 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 4954 | cmd = 2; |
dfcab17e | 4955 | else if (cdclk == 266667) |
30a970c6 JB |
4956 | cmd = 1; |
4957 | else | |
4958 | cmd = 0; | |
4959 | ||
4960 | mutex_lock(&dev_priv->rps.hw_lock); | |
4961 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
4962 | val &= ~DSPFREQGUAR_MASK; | |
4963 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
4964 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
4965 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
4966 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
4967 | 50)) { | |
4968 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
4969 | } | |
4970 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4971 | ||
dfcab17e | 4972 | if (cdclk == 400000) { |
6bcda4f0 | 4973 | u32 divider; |
30a970c6 | 4974 | |
6bcda4f0 | 4975 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 JB |
4976 | |
4977 | mutex_lock(&dev_priv->dpio_lock); | |
4978 | /* adjust cdclk divider */ | |
4979 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
9cf33db5 | 4980 | val &= ~DISPLAY_FREQUENCY_VALUES; |
30a970c6 JB |
4981 | val |= divider; |
4982 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
4983 | |
4984 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
4985 | DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
4986 | 50)) | |
4987 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
4988 | mutex_unlock(&dev_priv->dpio_lock); |
4989 | } | |
4990 | ||
4991 | mutex_lock(&dev_priv->dpio_lock); | |
4992 | /* adjust self-refresh exit latency value */ | |
4993 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
4994 | val &= ~0x7f; | |
4995 | ||
4996 | /* | |
4997 | * For high bandwidth configs, we set a higher latency in the bunit | |
4998 | * so that the core display fetch happens in time to avoid underruns. | |
4999 | */ | |
dfcab17e | 5000 | if (cdclk == 400000) |
30a970c6 JB |
5001 | val |= 4500 / 250; /* 4.5 usec */ |
5002 | else | |
5003 | val |= 3000 / 250; /* 3.0 usec */ | |
5004 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
5005 | mutex_unlock(&dev_priv->dpio_lock); | |
5006 | ||
f8bf63fd | 5007 | vlv_update_cdclk(dev); |
30a970c6 JB |
5008 | } |
5009 | ||
383c5a6a VS |
5010 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
5011 | { | |
5012 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5013 | u32 val, cmd; | |
5014 | ||
5015 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq); | |
5016 | ||
5017 | switch (cdclk) { | |
383c5a6a VS |
5018 | case 333333: |
5019 | case 320000: | |
383c5a6a | 5020 | case 266667: |
383c5a6a | 5021 | case 200000: |
383c5a6a VS |
5022 | break; |
5023 | default: | |
5f77eeb0 | 5024 | MISSING_CASE(cdclk); |
383c5a6a VS |
5025 | return; |
5026 | } | |
5027 | ||
9d0d3fda VS |
5028 | /* |
5029 | * Specs are full of misinformation, but testing on actual | |
5030 | * hardware has shown that we just need to write the desired | |
5031 | * CCK divider into the Punit register. | |
5032 | */ | |
5033 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
5034 | ||
383c5a6a VS |
5035 | mutex_lock(&dev_priv->rps.hw_lock); |
5036 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5037 | val &= ~DSPFREQGUAR_MASK_CHV; | |
5038 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
5039 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5040 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5041 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
5042 | 50)) { | |
5043 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5044 | } | |
5045 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5046 | ||
5047 | vlv_update_cdclk(dev); | |
5048 | } | |
5049 | ||
30a970c6 JB |
5050 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
5051 | int max_pixclk) | |
5052 | { | |
6bcda4f0 | 5053 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 5054 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 5055 | |
30a970c6 JB |
5056 | /* |
5057 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
5058 | * 200MHz | |
5059 | * 267MHz | |
29dc7ef3 | 5060 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
5061 | * 400MHz (VLV only) |
5062 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
5063 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
5064 | * |
5065 | * We seem to get an unstable or solid color picture at 200MHz. | |
5066 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
5067 | * are off. | |
30a970c6 | 5068 | */ |
6cca3195 VS |
5069 | if (!IS_CHERRYVIEW(dev_priv) && |
5070 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 5071 | return 400000; |
6cca3195 | 5072 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 5073 | return freq_320; |
e37c67a1 | 5074 | else if (max_pixclk > 0) |
dfcab17e | 5075 | return 266667; |
e37c67a1 VS |
5076 | else |
5077 | return 200000; | |
30a970c6 JB |
5078 | } |
5079 | ||
2f2d7aa1 VS |
5080 | /* compute the max pixel clock for new configuration */ |
5081 | static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv) | |
30a970c6 JB |
5082 | { |
5083 | struct drm_device *dev = dev_priv->dev; | |
5084 | struct intel_crtc *intel_crtc; | |
5085 | int max_pixclk = 0; | |
5086 | ||
d3fcc808 | 5087 | for_each_intel_crtc(dev, intel_crtc) { |
2f2d7aa1 | 5088 | if (intel_crtc->new_enabled) |
30a970c6 | 5089 | max_pixclk = max(max_pixclk, |
2d112de7 | 5090 | intel_crtc->new_config->base.adjusted_mode.crtc_clock); |
30a970c6 JB |
5091 | } |
5092 | ||
5093 | return max_pixclk; | |
5094 | } | |
5095 | ||
5096 | static void valleyview_modeset_global_pipes(struct drm_device *dev, | |
2f2d7aa1 | 5097 | unsigned *prepare_pipes) |
30a970c6 JB |
5098 | { |
5099 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5100 | struct intel_crtc *intel_crtc; | |
2f2d7aa1 | 5101 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 | 5102 | |
d60c4473 ID |
5103 | if (valleyview_calc_cdclk(dev_priv, max_pixclk) == |
5104 | dev_priv->vlv_cdclk_freq) | |
30a970c6 JB |
5105 | return; |
5106 | ||
2f2d7aa1 | 5107 | /* disable/enable all currently active pipes while we change cdclk */ |
d3fcc808 | 5108 | for_each_intel_crtc(dev, intel_crtc) |
83d65738 | 5109 | if (intel_crtc->base.state->enable) |
30a970c6 JB |
5110 | *prepare_pipes |= (1 << intel_crtc->pipe); |
5111 | } | |
5112 | ||
1e69cd74 VS |
5113 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
5114 | { | |
5115 | unsigned int credits, default_credits; | |
5116 | ||
5117 | if (IS_CHERRYVIEW(dev_priv)) | |
5118 | default_credits = PFI_CREDIT(12); | |
5119 | else | |
5120 | default_credits = PFI_CREDIT(8); | |
5121 | ||
5122 | if (DIV_ROUND_CLOSEST(dev_priv->vlv_cdclk_freq, 1000) >= dev_priv->rps.cz_freq) { | |
5123 | /* CHV suggested value is 31 or 63 */ | |
5124 | if (IS_CHERRYVIEW(dev_priv)) | |
5125 | credits = PFI_CREDIT_31; | |
5126 | else | |
5127 | credits = PFI_CREDIT(15); | |
5128 | } else { | |
5129 | credits = default_credits; | |
5130 | } | |
5131 | ||
5132 | /* | |
5133 | * WA - write default credits before re-programming | |
5134 | * FIXME: should we also set the resend bit here? | |
5135 | */ | |
5136 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
5137 | default_credits); | |
5138 | ||
5139 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
5140 | credits | PFI_CREDIT_RESEND); | |
5141 | ||
5142 | /* | |
5143 | * FIXME is this guaranteed to clear | |
5144 | * immediately or should we poll for it? | |
5145 | */ | |
5146 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
5147 | } | |
5148 | ||
30a970c6 JB |
5149 | static void valleyview_modeset_global_resources(struct drm_device *dev) |
5150 | { | |
5151 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2f2d7aa1 | 5152 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 JB |
5153 | int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); |
5154 | ||
383c5a6a | 5155 | if (req_cdclk != dev_priv->vlv_cdclk_freq) { |
738c05c0 ID |
5156 | /* |
5157 | * FIXME: We can end up here with all power domains off, yet | |
5158 | * with a CDCLK frequency other than the minimum. To account | |
5159 | * for this take the PIPE-A power domain, which covers the HW | |
5160 | * blocks needed for the following programming. This can be | |
5161 | * removed once it's guaranteed that we get here either with | |
5162 | * the minimum CDCLK set, or the required power domains | |
5163 | * enabled. | |
5164 | */ | |
5165 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
5166 | ||
383c5a6a VS |
5167 | if (IS_CHERRYVIEW(dev)) |
5168 | cherryview_set_cdclk(dev, req_cdclk); | |
5169 | else | |
5170 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 5171 | |
1e69cd74 VS |
5172 | vlv_program_pfi_credits(dev_priv); |
5173 | ||
738c05c0 | 5174 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
383c5a6a | 5175 | } |
30a970c6 JB |
5176 | } |
5177 | ||
89b667f8 JB |
5178 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
5179 | { | |
5180 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 5181 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
5182 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5183 | struct intel_encoder *encoder; | |
5184 | int pipe = intel_crtc->pipe; | |
23538ef1 | 5185 | bool is_dsi; |
89b667f8 | 5186 | |
83d65738 | 5187 | WARN_ON(!crtc->state->enable); |
89b667f8 JB |
5188 | |
5189 | if (intel_crtc->active) | |
5190 | return; | |
5191 | ||
409ee761 | 5192 | is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI); |
8525a235 | 5193 | |
1ae0d137 VS |
5194 | if (!is_dsi) { |
5195 | if (IS_CHERRYVIEW(dev)) | |
6e3c9717 | 5196 | chv_prepare_pll(intel_crtc, intel_crtc->config); |
1ae0d137 | 5197 | else |
6e3c9717 | 5198 | vlv_prepare_pll(intel_crtc, intel_crtc->config); |
1ae0d137 | 5199 | } |
5b18e57c | 5200 | |
6e3c9717 | 5201 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 5202 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
5203 | |
5204 | intel_set_pipe_timings(intel_crtc); | |
5205 | ||
c14b0485 VS |
5206 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
5207 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5208 | ||
5209 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
5210 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
5211 | } | |
5212 | ||
5b18e57c DV |
5213 | i9xx_set_pipeconf(intel_crtc); |
5214 | ||
89b667f8 | 5215 | intel_crtc->active = true; |
89b667f8 | 5216 | |
a72e4c9f | 5217 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 5218 | |
89b667f8 JB |
5219 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5220 | if (encoder->pre_pll_enable) | |
5221 | encoder->pre_pll_enable(encoder); | |
5222 | ||
9d556c99 CML |
5223 | if (!is_dsi) { |
5224 | if (IS_CHERRYVIEW(dev)) | |
6e3c9717 | 5225 | chv_enable_pll(intel_crtc, intel_crtc->config); |
9d556c99 | 5226 | else |
6e3c9717 | 5227 | vlv_enable_pll(intel_crtc, intel_crtc->config); |
9d556c99 | 5228 | } |
89b667f8 JB |
5229 | |
5230 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
5231 | if (encoder->pre_enable) | |
5232 | encoder->pre_enable(encoder); | |
5233 | ||
2dd24552 JB |
5234 | i9xx_pfit_enable(intel_crtc); |
5235 | ||
63cbb074 VS |
5236 | intel_crtc_load_lut(crtc); |
5237 | ||
f37fcc2a | 5238 | intel_update_watermarks(crtc); |
e1fdc473 | 5239 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 5240 | |
4b3a9526 VS |
5241 | assert_vblank_disabled(crtc); |
5242 | drm_crtc_vblank_on(crtc); | |
5243 | ||
f9b61ff6 DV |
5244 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5245 | encoder->enable(encoder); | |
5246 | ||
9ab0460b | 5247 | intel_crtc_enable_planes(crtc); |
d40d9187 | 5248 | |
56b80e1f | 5249 | /* Underruns don't raise interrupts, so check manually. */ |
a72e4c9f | 5250 | i9xx_check_fifo_underruns(dev_priv); |
89b667f8 JB |
5251 | } |
5252 | ||
f13c2ef3 DV |
5253 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
5254 | { | |
5255 | struct drm_device *dev = crtc->base.dev; | |
5256 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5257 | ||
6e3c9717 ACO |
5258 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
5259 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
5260 | } |
5261 | ||
0b8765c6 | 5262 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
5263 | { |
5264 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 5265 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 5266 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 5267 | struct intel_encoder *encoder; |
79e53945 | 5268 | int pipe = intel_crtc->pipe; |
79e53945 | 5269 | |
83d65738 | 5270 | WARN_ON(!crtc->state->enable); |
08a48469 | 5271 | |
f7abfe8b CW |
5272 | if (intel_crtc->active) |
5273 | return; | |
5274 | ||
f13c2ef3 DV |
5275 | i9xx_set_pll_dividers(intel_crtc); |
5276 | ||
6e3c9717 | 5277 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 5278 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
5279 | |
5280 | intel_set_pipe_timings(intel_crtc); | |
5281 | ||
5b18e57c DV |
5282 | i9xx_set_pipeconf(intel_crtc); |
5283 | ||
f7abfe8b | 5284 | intel_crtc->active = true; |
6b383a7f | 5285 | |
4a3436e8 | 5286 | if (!IS_GEN2(dev)) |
a72e4c9f | 5287 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 5288 | |
9d6d9f19 MK |
5289 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5290 | if (encoder->pre_enable) | |
5291 | encoder->pre_enable(encoder); | |
5292 | ||
f6736a1a DV |
5293 | i9xx_enable_pll(intel_crtc); |
5294 | ||
2dd24552 JB |
5295 | i9xx_pfit_enable(intel_crtc); |
5296 | ||
63cbb074 VS |
5297 | intel_crtc_load_lut(crtc); |
5298 | ||
f37fcc2a | 5299 | intel_update_watermarks(crtc); |
e1fdc473 | 5300 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 5301 | |
4b3a9526 VS |
5302 | assert_vblank_disabled(crtc); |
5303 | drm_crtc_vblank_on(crtc); | |
5304 | ||
f9b61ff6 DV |
5305 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5306 | encoder->enable(encoder); | |
5307 | ||
9ab0460b | 5308 | intel_crtc_enable_planes(crtc); |
d40d9187 | 5309 | |
4a3436e8 VS |
5310 | /* |
5311 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
5312 | * So don't enable underrun reporting before at least some planes | |
5313 | * are enabled. | |
5314 | * FIXME: Need to fix the logic to work when we turn off all planes | |
5315 | * but leave the pipe running. | |
5316 | */ | |
5317 | if (IS_GEN2(dev)) | |
a72e4c9f | 5318 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 5319 | |
56b80e1f | 5320 | /* Underruns don't raise interrupts, so check manually. */ |
a72e4c9f | 5321 | i9xx_check_fifo_underruns(dev_priv); |
0b8765c6 | 5322 | } |
79e53945 | 5323 | |
87476d63 DV |
5324 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
5325 | { | |
5326 | struct drm_device *dev = crtc->base.dev; | |
5327 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 5328 | |
6e3c9717 | 5329 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 5330 | return; |
87476d63 | 5331 | |
328d8e82 | 5332 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 5333 | |
328d8e82 DV |
5334 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
5335 | I915_READ(PFIT_CONTROL)); | |
5336 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
5337 | } |
5338 | ||
0b8765c6 JB |
5339 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
5340 | { | |
5341 | struct drm_device *dev = crtc->dev; | |
5342 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5343 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 5344 | struct intel_encoder *encoder; |
0b8765c6 | 5345 | int pipe = intel_crtc->pipe; |
ef9c3aee | 5346 | |
f7abfe8b CW |
5347 | if (!intel_crtc->active) |
5348 | return; | |
5349 | ||
4a3436e8 VS |
5350 | /* |
5351 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
5352 | * So diasble underrun reporting before all the planes get disabled. | |
5353 | * FIXME: Need to fix the logic to work when we turn off all planes | |
5354 | * but leave the pipe running. | |
5355 | */ | |
5356 | if (IS_GEN2(dev)) | |
a72e4c9f | 5357 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
4a3436e8 | 5358 | |
564ed191 ID |
5359 | /* |
5360 | * Vblank time updates from the shadow to live plane control register | |
5361 | * are blocked if the memory self-refresh mode is active at that | |
5362 | * moment. So to make sure the plane gets truly disabled, disable | |
5363 | * first the self-refresh mode. The self-refresh enable bit in turn | |
5364 | * will be checked/applied by the HW only at the next frame start | |
5365 | * event which is after the vblank start event, so we need to have a | |
5366 | * wait-for-vblank between disabling the plane and the pipe. | |
5367 | */ | |
5368 | intel_set_memory_cxsr(dev_priv, false); | |
9ab0460b VS |
5369 | intel_crtc_disable_planes(crtc); |
5370 | ||
6304cd91 VS |
5371 | /* |
5372 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
5373 | * wait for planes to fully turn off before disabling the pipe. | |
564ed191 ID |
5374 | * We also need to wait on all gmch platforms because of the |
5375 | * self-refresh mode constraint explained above. | |
6304cd91 | 5376 | */ |
564ed191 | 5377 | intel_wait_for_vblank(dev, pipe); |
6304cd91 | 5378 | |
4b3a9526 VS |
5379 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5380 | encoder->disable(encoder); | |
5381 | ||
f9b61ff6 DV |
5382 | drm_crtc_vblank_off(crtc); |
5383 | assert_vblank_disabled(crtc); | |
5384 | ||
575f7ab7 | 5385 | intel_disable_pipe(intel_crtc); |
24a1f16d | 5386 | |
87476d63 | 5387 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 5388 | |
89b667f8 JB |
5389 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5390 | if (encoder->post_disable) | |
5391 | encoder->post_disable(encoder); | |
5392 | ||
409ee761 | 5393 | if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) { |
076ed3b2 CML |
5394 | if (IS_CHERRYVIEW(dev)) |
5395 | chv_disable_pll(dev_priv, pipe); | |
5396 | else if (IS_VALLEYVIEW(dev)) | |
5397 | vlv_disable_pll(dev_priv, pipe); | |
5398 | else | |
1c4e0274 | 5399 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 5400 | } |
0b8765c6 | 5401 | |
4a3436e8 | 5402 | if (!IS_GEN2(dev)) |
a72e4c9f | 5403 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
4a3436e8 | 5404 | |
f7abfe8b | 5405 | intel_crtc->active = false; |
46ba614c | 5406 | intel_update_watermarks(crtc); |
f37fcc2a | 5407 | |
efa9624e | 5408 | mutex_lock(&dev->struct_mutex); |
7ff0ebcc | 5409 | intel_fbc_update(dev); |
efa9624e | 5410 | mutex_unlock(&dev->struct_mutex); |
0b8765c6 JB |
5411 | } |
5412 | ||
ee7b9f93 JB |
5413 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
5414 | { | |
5415 | } | |
5416 | ||
b04c5bd6 BF |
5417 | /* Master function to enable/disable CRTC and corresponding power wells */ |
5418 | void intel_crtc_control(struct drm_crtc *crtc, bool enable) | |
976f8a20 DV |
5419 | { |
5420 | struct drm_device *dev = crtc->dev; | |
5421 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0e572fe7 | 5422 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
0e572fe7 DV |
5423 | enum intel_display_power_domain domain; |
5424 | unsigned long domains; | |
976f8a20 | 5425 | |
0e572fe7 DV |
5426 | if (enable) { |
5427 | if (!intel_crtc->active) { | |
e1e9fb84 DV |
5428 | domains = get_crtc_power_domains(crtc); |
5429 | for_each_power_domain(domain, domains) | |
5430 | intel_display_power_get(dev_priv, domain); | |
5431 | intel_crtc->enabled_power_domains = domains; | |
0e572fe7 DV |
5432 | |
5433 | dev_priv->display.crtc_enable(crtc); | |
5434 | } | |
5435 | } else { | |
5436 | if (intel_crtc->active) { | |
5437 | dev_priv->display.crtc_disable(crtc); | |
5438 | ||
e1e9fb84 DV |
5439 | domains = intel_crtc->enabled_power_domains; |
5440 | for_each_power_domain(domain, domains) | |
5441 | intel_display_power_put(dev_priv, domain); | |
5442 | intel_crtc->enabled_power_domains = 0; | |
0e572fe7 DV |
5443 | } |
5444 | } | |
b04c5bd6 BF |
5445 | } |
5446 | ||
5447 | /** | |
5448 | * Sets the power management mode of the pipe and plane. | |
5449 | */ | |
5450 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
5451 | { | |
5452 | struct drm_device *dev = crtc->dev; | |
5453 | struct intel_encoder *intel_encoder; | |
5454 | bool enable = false; | |
5455 | ||
5456 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
5457 | enable |= intel_encoder->connectors_active; | |
5458 | ||
5459 | intel_crtc_control(crtc, enable); | |
976f8a20 DV |
5460 | } |
5461 | ||
cdd59983 CW |
5462 | static void intel_crtc_disable(struct drm_crtc *crtc) |
5463 | { | |
cdd59983 | 5464 | struct drm_device *dev = crtc->dev; |
976f8a20 | 5465 | struct drm_connector *connector; |
ee7b9f93 | 5466 | struct drm_i915_private *dev_priv = dev->dev_private; |
cdd59983 | 5467 | |
976f8a20 | 5468 | /* crtc should still be enabled when we disable it. */ |
83d65738 | 5469 | WARN_ON(!crtc->state->enable); |
976f8a20 DV |
5470 | |
5471 | dev_priv->display.crtc_disable(crtc); | |
ee7b9f93 JB |
5472 | dev_priv->display.off(crtc); |
5473 | ||
455a6808 | 5474 | crtc->primary->funcs->disable_plane(crtc->primary); |
976f8a20 DV |
5475 | |
5476 | /* Update computed state. */ | |
5477 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
5478 | if (!connector->encoder || !connector->encoder->crtc) | |
5479 | continue; | |
5480 | ||
5481 | if (connector->encoder->crtc != crtc) | |
5482 | continue; | |
5483 | ||
5484 | connector->dpms = DRM_MODE_DPMS_OFF; | |
5485 | to_intel_encoder(connector->encoder)->connectors_active = false; | |
cdd59983 CW |
5486 | } |
5487 | } | |
5488 | ||
ea5b213a | 5489 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 5490 | { |
4ef69c7a | 5491 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 5492 | |
ea5b213a CW |
5493 | drm_encoder_cleanup(encoder); |
5494 | kfree(intel_encoder); | |
7e7d76c3 JB |
5495 | } |
5496 | ||
9237329d | 5497 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
5ab432ef DV |
5498 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
5499 | * state of the entire output pipe. */ | |
9237329d | 5500 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
7e7d76c3 | 5501 | { |
5ab432ef DV |
5502 | if (mode == DRM_MODE_DPMS_ON) { |
5503 | encoder->connectors_active = true; | |
5504 | ||
b2cabb0e | 5505 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
5506 | } else { |
5507 | encoder->connectors_active = false; | |
5508 | ||
b2cabb0e | 5509 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 5510 | } |
79e53945 JB |
5511 | } |
5512 | ||
0a91ca29 DV |
5513 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
5514 | * internal consistency). */ | |
b980514c | 5515 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 5516 | { |
0a91ca29 DV |
5517 | if (connector->get_hw_state(connector)) { |
5518 | struct intel_encoder *encoder = connector->encoder; | |
5519 | struct drm_crtc *crtc; | |
5520 | bool encoder_enabled; | |
5521 | enum pipe pipe; | |
5522 | ||
5523 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
5524 | connector->base.base.id, | |
c23cc417 | 5525 | connector->base.name); |
0a91ca29 | 5526 | |
0e32b39c DA |
5527 | /* there is no real hw state for MST connectors */ |
5528 | if (connector->mst_port) | |
5529 | return; | |
5530 | ||
e2c719b7 | 5531 | I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, |
0a91ca29 | 5532 | "wrong connector dpms state\n"); |
e2c719b7 | 5533 | I915_STATE_WARN(connector->base.encoder != &encoder->base, |
0a91ca29 | 5534 | "active connector not linked to encoder\n"); |
0a91ca29 | 5535 | |
36cd7444 | 5536 | if (encoder) { |
e2c719b7 | 5537 | I915_STATE_WARN(!encoder->connectors_active, |
36cd7444 DA |
5538 | "encoder->connectors_active not set\n"); |
5539 | ||
5540 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
e2c719b7 RC |
5541 | I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n"); |
5542 | if (I915_STATE_WARN_ON(!encoder->base.crtc)) | |
36cd7444 | 5543 | return; |
0a91ca29 | 5544 | |
36cd7444 | 5545 | crtc = encoder->base.crtc; |
0a91ca29 | 5546 | |
83d65738 MR |
5547 | I915_STATE_WARN(!crtc->state->enable, |
5548 | "crtc not enabled\n"); | |
e2c719b7 RC |
5549 | I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); |
5550 | I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe, | |
36cd7444 DA |
5551 | "encoder active on the wrong pipe\n"); |
5552 | } | |
0a91ca29 | 5553 | } |
79e53945 JB |
5554 | } |
5555 | ||
5ab432ef DV |
5556 | /* Even simpler default implementation, if there's really no special case to |
5557 | * consider. */ | |
5558 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 5559 | { |
5ab432ef DV |
5560 | /* All the simple cases only support two dpms states. */ |
5561 | if (mode != DRM_MODE_DPMS_ON) | |
5562 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 5563 | |
5ab432ef DV |
5564 | if (mode == connector->dpms) |
5565 | return; | |
5566 | ||
5567 | connector->dpms = mode; | |
5568 | ||
5569 | /* Only need to change hw state when actually enabled */ | |
c9976dcf CW |
5570 | if (connector->encoder) |
5571 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); | |
0a91ca29 | 5572 | |
b980514c | 5573 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
5574 | } |
5575 | ||
f0947c37 DV |
5576 | /* Simple connector->get_hw_state implementation for encoders that support only |
5577 | * one connector and no cloning and hence the encoder state determines the state | |
5578 | * of the connector. */ | |
5579 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 5580 | { |
24929352 | 5581 | enum pipe pipe = 0; |
f0947c37 | 5582 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 5583 | |
f0947c37 | 5584 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
5585 | } |
5586 | ||
d272ddfa VS |
5587 | static int pipe_required_fdi_lanes(struct drm_device *dev, enum pipe pipe) |
5588 | { | |
5589 | struct intel_crtc *crtc = | |
5590 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
5591 | ||
5592 | if (crtc->base.state->enable && | |
5593 | crtc->config->has_pch_encoder) | |
5594 | return crtc->config->fdi_lanes; | |
5595 | ||
5596 | return 0; | |
5597 | } | |
5598 | ||
1857e1da | 5599 | static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 5600 | struct intel_crtc_state *pipe_config) |
1857e1da | 5601 | { |
1857e1da DV |
5602 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
5603 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5604 | if (pipe_config->fdi_lanes > 4) { | |
5605 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
5606 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5607 | return false; | |
5608 | } | |
5609 | ||
bafb6553 | 5610 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
5611 | if (pipe_config->fdi_lanes > 2) { |
5612 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
5613 | pipe_config->fdi_lanes); | |
5614 | return false; | |
5615 | } else { | |
5616 | return true; | |
5617 | } | |
5618 | } | |
5619 | ||
5620 | if (INTEL_INFO(dev)->num_pipes == 2) | |
5621 | return true; | |
5622 | ||
5623 | /* Ivybridge 3 pipe is really complicated */ | |
5624 | switch (pipe) { | |
5625 | case PIPE_A: | |
5626 | return true; | |
5627 | case PIPE_B: | |
d272ddfa VS |
5628 | if (pipe_config->fdi_lanes > 2 && |
5629 | pipe_required_fdi_lanes(dev, PIPE_C) > 0) { | |
1857e1da DV |
5630 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
5631 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5632 | return false; | |
5633 | } | |
5634 | return true; | |
5635 | case PIPE_C: | |
251cc67c VS |
5636 | if (pipe_config->fdi_lanes > 2) { |
5637 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
5638 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5639 | return false; | |
5640 | } | |
d272ddfa | 5641 | if (pipe_required_fdi_lanes(dev, PIPE_B) > 2) { |
1857e1da DV |
5642 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
5643 | return false; | |
5644 | } | |
5645 | return true; | |
5646 | default: | |
5647 | BUG(); | |
5648 | } | |
5649 | } | |
5650 | ||
e29c22c0 DV |
5651 | #define RETRY 1 |
5652 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 5653 | struct intel_crtc_state *pipe_config) |
877d48d5 | 5654 | { |
1857e1da | 5655 | struct drm_device *dev = intel_crtc->base.dev; |
2d112de7 | 5656 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
ff9a6750 | 5657 | int lane, link_bw, fdi_dotclock; |
e29c22c0 | 5658 | bool setup_ok, needs_recompute = false; |
877d48d5 | 5659 | |
e29c22c0 | 5660 | retry: |
877d48d5 DV |
5661 | /* FDI is a binary signal running at ~2.7GHz, encoding |
5662 | * each output octet as 10 bits. The actual frequency | |
5663 | * is stored as a divider into a 100MHz clock, and the | |
5664 | * mode pixel clock is stored in units of 1KHz. | |
5665 | * Hence the bw of each lane in terms of the mode signal | |
5666 | * is: | |
5667 | */ | |
5668 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
5669 | ||
241bfc38 | 5670 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 5671 | |
2bd89a07 | 5672 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
5673 | pipe_config->pipe_bpp); |
5674 | ||
5675 | pipe_config->fdi_lanes = lane; | |
5676 | ||
2bd89a07 | 5677 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 5678 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 5679 | |
e29c22c0 DV |
5680 | setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
5681 | intel_crtc->pipe, pipe_config); | |
5682 | if (!setup_ok && pipe_config->pipe_bpp > 6*3) { | |
5683 | pipe_config->pipe_bpp -= 2*3; | |
5684 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
5685 | pipe_config->pipe_bpp); | |
5686 | needs_recompute = true; | |
5687 | pipe_config->bw_constrained = true; | |
5688 | ||
5689 | goto retry; | |
5690 | } | |
5691 | ||
5692 | if (needs_recompute) | |
5693 | return RETRY; | |
5694 | ||
5695 | return setup_ok ? 0 : -EINVAL; | |
877d48d5 DV |
5696 | } |
5697 | ||
42db64ef | 5698 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 5699 | struct intel_crtc_state *pipe_config) |
42db64ef | 5700 | { |
d330a953 | 5701 | pipe_config->ips_enabled = i915.enable_ips && |
3c4ca58c | 5702 | hsw_crtc_supports_ips(crtc) && |
b6dfdc9b | 5703 | pipe_config->pipe_bpp <= 24; |
42db64ef PZ |
5704 | } |
5705 | ||
a43f6e0f | 5706 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 5707 | struct intel_crtc_state *pipe_config) |
79e53945 | 5708 | { |
a43f6e0f | 5709 | struct drm_device *dev = crtc->base.dev; |
8bd31e67 | 5710 | struct drm_i915_private *dev_priv = dev->dev_private; |
2d112de7 | 5711 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
89749350 | 5712 | |
ad3a4479 | 5713 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 | 5714 | if (INTEL_INFO(dev)->gen < 4) { |
cf532bb2 VS |
5715 | int clock_limit = |
5716 | dev_priv->display.get_display_clock_speed(dev); | |
5717 | ||
5718 | /* | |
5719 | * Enable pixel doubling when the dot clock | |
5720 | * is > 90% of the (display) core speed. | |
5721 | * | |
b397c96b VS |
5722 | * GDG double wide on either pipe, |
5723 | * otherwise pipe A only. | |
cf532bb2 | 5724 | */ |
b397c96b | 5725 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
241bfc38 | 5726 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
ad3a4479 | 5727 | clock_limit *= 2; |
cf532bb2 | 5728 | pipe_config->double_wide = true; |
ad3a4479 VS |
5729 | } |
5730 | ||
241bfc38 | 5731 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
e29c22c0 | 5732 | return -EINVAL; |
2c07245f | 5733 | } |
89749350 | 5734 | |
1d1d0e27 VS |
5735 | /* |
5736 | * Pipe horizontal size must be even in: | |
5737 | * - DVO ganged mode | |
5738 | * - LVDS dual channel mode | |
5739 | * - Double wide pipe | |
5740 | */ | |
b4f2bf4c | 5741 | if ((intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
5742 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
5743 | pipe_config->pipe_src_w &= ~1; | |
5744 | ||
8693a824 DL |
5745 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
5746 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
5747 | */ |
5748 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
5749 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
e29c22c0 | 5750 | return -EINVAL; |
44f46b42 | 5751 | |
bd080ee5 | 5752 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { |
5d2d38dd | 5753 | pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ |
bd080ee5 | 5754 | } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { |
5d2d38dd DV |
5755 | /* only a 8bpc pipe, with 6bpc dither through the panel fitter |
5756 | * for lvds. */ | |
5757 | pipe_config->pipe_bpp = 8*3; | |
5758 | } | |
5759 | ||
f5adf94e | 5760 | if (HAS_IPS(dev)) |
a43f6e0f DV |
5761 | hsw_compute_ips_config(crtc, pipe_config); |
5762 | ||
877d48d5 | 5763 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 5764 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 5765 | |
e29c22c0 | 5766 | return 0; |
79e53945 JB |
5767 | } |
5768 | ||
25eb05fc JB |
5769 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
5770 | { | |
d197b7d3 | 5771 | struct drm_i915_private *dev_priv = dev->dev_private; |
d197b7d3 VS |
5772 | u32 val; |
5773 | int divider; | |
5774 | ||
6bcda4f0 VS |
5775 | if (dev_priv->hpll_freq == 0) |
5776 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
5777 | ||
d197b7d3 VS |
5778 | mutex_lock(&dev_priv->dpio_lock); |
5779 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
5780 | mutex_unlock(&dev_priv->dpio_lock); | |
5781 | ||
5782 | divider = val & DISPLAY_FREQUENCY_VALUES; | |
5783 | ||
7d007f40 VS |
5784 | WARN((val & DISPLAY_FREQUENCY_STATUS) != |
5785 | (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
5786 | "cdclk change in progress\n"); | |
5787 | ||
6bcda4f0 | 5788 | return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); |
25eb05fc JB |
5789 | } |
5790 | ||
e70236a8 JB |
5791 | static int i945_get_display_clock_speed(struct drm_device *dev) |
5792 | { | |
5793 | return 400000; | |
5794 | } | |
79e53945 | 5795 | |
e70236a8 | 5796 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 5797 | { |
e70236a8 JB |
5798 | return 333000; |
5799 | } | |
79e53945 | 5800 | |
e70236a8 JB |
5801 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
5802 | { | |
5803 | return 200000; | |
5804 | } | |
79e53945 | 5805 | |
257a7ffc DV |
5806 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
5807 | { | |
5808 | u16 gcfgc = 0; | |
5809 | ||
5810 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
5811 | ||
5812 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
5813 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
5814 | return 267000; | |
5815 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: | |
5816 | return 333000; | |
5817 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: | |
5818 | return 444000; | |
5819 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: | |
5820 | return 200000; | |
5821 | default: | |
5822 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
5823 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
5824 | return 133000; | |
5825 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: | |
5826 | return 167000; | |
5827 | } | |
5828 | } | |
5829 | ||
e70236a8 JB |
5830 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
5831 | { | |
5832 | u16 gcfgc = 0; | |
79e53945 | 5833 | |
e70236a8 JB |
5834 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
5835 | ||
5836 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
5837 | return 133000; | |
5838 | else { | |
5839 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
5840 | case GC_DISPLAY_CLOCK_333_MHZ: | |
5841 | return 333000; | |
5842 | default: | |
5843 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
5844 | return 190000; | |
79e53945 | 5845 | } |
e70236a8 JB |
5846 | } |
5847 | } | |
5848 | ||
5849 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
5850 | { | |
5851 | return 266000; | |
5852 | } | |
5853 | ||
5854 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
5855 | { | |
5856 | u16 hpllcc = 0; | |
5857 | /* Assume that the hardware is in the high speed state. This | |
5858 | * should be the default. | |
5859 | */ | |
5860 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
5861 | case GC_CLOCK_133_200: | |
5862 | case GC_CLOCK_100_200: | |
5863 | return 200000; | |
5864 | case GC_CLOCK_166_250: | |
5865 | return 250000; | |
5866 | case GC_CLOCK_100_133: | |
79e53945 | 5867 | return 133000; |
e70236a8 | 5868 | } |
79e53945 | 5869 | |
e70236a8 JB |
5870 | /* Shouldn't happen */ |
5871 | return 0; | |
5872 | } | |
79e53945 | 5873 | |
e70236a8 JB |
5874 | static int i830_get_display_clock_speed(struct drm_device *dev) |
5875 | { | |
5876 | return 133000; | |
79e53945 JB |
5877 | } |
5878 | ||
2c07245f | 5879 | static void |
a65851af | 5880 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 5881 | { |
a65851af VS |
5882 | while (*num > DATA_LINK_M_N_MASK || |
5883 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
5884 | *num >>= 1; |
5885 | *den >>= 1; | |
5886 | } | |
5887 | } | |
5888 | ||
a65851af VS |
5889 | static void compute_m_n(unsigned int m, unsigned int n, |
5890 | uint32_t *ret_m, uint32_t *ret_n) | |
5891 | { | |
5892 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
5893 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
5894 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
5895 | } | |
5896 | ||
e69d0bc1 DV |
5897 | void |
5898 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
5899 | int pixel_clock, int link_clock, | |
5900 | struct intel_link_m_n *m_n) | |
2c07245f | 5901 | { |
e69d0bc1 | 5902 | m_n->tu = 64; |
a65851af VS |
5903 | |
5904 | compute_m_n(bits_per_pixel * pixel_clock, | |
5905 | link_clock * nlanes * 8, | |
5906 | &m_n->gmch_m, &m_n->gmch_n); | |
5907 | ||
5908 | compute_m_n(pixel_clock, link_clock, | |
5909 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
5910 | } |
5911 | ||
a7615030 CW |
5912 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
5913 | { | |
d330a953 JN |
5914 | if (i915.panel_use_ssc >= 0) |
5915 | return i915.panel_use_ssc != 0; | |
41aa3448 | 5916 | return dev_priv->vbt.lvds_use_ssc |
435793df | 5917 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
5918 | } |
5919 | ||
409ee761 | 5920 | static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors) |
c65d77d8 | 5921 | { |
409ee761 | 5922 | struct drm_device *dev = crtc->base.dev; |
c65d77d8 JB |
5923 | struct drm_i915_private *dev_priv = dev->dev_private; |
5924 | int refclk; | |
5925 | ||
a0c4da24 | 5926 | if (IS_VALLEYVIEW(dev)) { |
9a0ea498 | 5927 | refclk = 100000; |
d0737e1d | 5928 | } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 5929 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
5930 | refclk = dev_priv->vbt.lvds_ssc_freq; |
5931 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
5932 | } else if (!IS_GEN2(dev)) { |
5933 | refclk = 96000; | |
5934 | } else { | |
5935 | refclk = 48000; | |
5936 | } | |
5937 | ||
5938 | return refclk; | |
5939 | } | |
5940 | ||
7429e9d4 | 5941 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 5942 | { |
7df00d7a | 5943 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 5944 | } |
f47709a9 | 5945 | |
7429e9d4 DV |
5946 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
5947 | { | |
5948 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
5949 | } |
5950 | ||
f47709a9 | 5951 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 5952 | struct intel_crtc_state *crtc_state, |
a7516a05 JB |
5953 | intel_clock_t *reduced_clock) |
5954 | { | |
f47709a9 | 5955 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
5956 | u32 fp, fp2 = 0; |
5957 | ||
5958 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 5959 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 5960 | if (reduced_clock) |
7429e9d4 | 5961 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 5962 | } else { |
190f68c5 | 5963 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 5964 | if (reduced_clock) |
7429e9d4 | 5965 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
5966 | } |
5967 | ||
190f68c5 | 5968 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 5969 | |
f47709a9 | 5970 | crtc->lowfreq_avail = false; |
e1f234bd | 5971 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) && |
d330a953 | 5972 | reduced_clock && i915.powersave) { |
190f68c5 | 5973 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 5974 | crtc->lowfreq_avail = true; |
a7516a05 | 5975 | } else { |
190f68c5 | 5976 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
5977 | } |
5978 | } | |
5979 | ||
5e69f97f CML |
5980 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
5981 | pipe) | |
89b667f8 JB |
5982 | { |
5983 | u32 reg_val; | |
5984 | ||
5985 | /* | |
5986 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
5987 | * and set it to a reasonable value instead. | |
5988 | */ | |
ab3c759a | 5989 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
5990 | reg_val &= 0xffffff00; |
5991 | reg_val |= 0x00000030; | |
ab3c759a | 5992 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 5993 | |
ab3c759a | 5994 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
5995 | reg_val &= 0x8cffffff; |
5996 | reg_val = 0x8c000000; | |
ab3c759a | 5997 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 5998 | |
ab3c759a | 5999 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 6000 | reg_val &= 0xffffff00; |
ab3c759a | 6001 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 6002 | |
ab3c759a | 6003 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
6004 | reg_val &= 0x00ffffff; |
6005 | reg_val |= 0xb0000000; | |
ab3c759a | 6006 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
6007 | } |
6008 | ||
b551842d DV |
6009 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
6010 | struct intel_link_m_n *m_n) | |
6011 | { | |
6012 | struct drm_device *dev = crtc->base.dev; | |
6013 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6014 | int pipe = crtc->pipe; | |
6015 | ||
e3b95f1e DV |
6016 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6017 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
6018 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
6019 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
6020 | } |
6021 | ||
6022 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
6023 | struct intel_link_m_n *m_n, |
6024 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
6025 | { |
6026 | struct drm_device *dev = crtc->base.dev; | |
6027 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6028 | int pipe = crtc->pipe; | |
6e3c9717 | 6029 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
6030 | |
6031 | if (INTEL_INFO(dev)->gen >= 5) { | |
6032 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
6033 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
6034 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
6035 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
6036 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
6037 | * for gen < 8) and if DRRS is supported (to make sure the | |
6038 | * registers are not unnecessarily accessed). | |
6039 | */ | |
44395bfe | 6040 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 6041 | crtc->config->has_drrs) { |
f769cd24 VK |
6042 | I915_WRITE(PIPE_DATA_M2(transcoder), |
6043 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
6044 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
6045 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
6046 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
6047 | } | |
b551842d | 6048 | } else { |
e3b95f1e DV |
6049 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6050 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
6051 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
6052 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
6053 | } |
6054 | } | |
6055 | ||
fe3cd48d | 6056 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 6057 | { |
fe3cd48d R |
6058 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
6059 | ||
6060 | if (m_n == M1_N1) { | |
6061 | dp_m_n = &crtc->config->dp_m_n; | |
6062 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
6063 | } else if (m_n == M2_N2) { | |
6064 | ||
6065 | /* | |
6066 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
6067 | * needs to be programmed into M1_N1. | |
6068 | */ | |
6069 | dp_m_n = &crtc->config->dp_m2_n2; | |
6070 | } else { | |
6071 | DRM_ERROR("Unsupported divider value\n"); | |
6072 | return; | |
6073 | } | |
6074 | ||
6e3c9717 ACO |
6075 | if (crtc->config->has_pch_encoder) |
6076 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 6077 | else |
fe3cd48d | 6078 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
6079 | } |
6080 | ||
d288f65f | 6081 | static void vlv_update_pll(struct intel_crtc *crtc, |
5cec258b | 6082 | struct intel_crtc_state *pipe_config) |
bdd4b6a6 DV |
6083 | { |
6084 | u32 dpll, dpll_md; | |
6085 | ||
6086 | /* | |
6087 | * Enable DPIO clock input. We should never disable the reference | |
6088 | * clock for pipe B, since VGA hotplug / manual detection depends | |
6089 | * on it. | |
6090 | */ | |
6091 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | | |
6092 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; | |
6093 | /* We should never disable this, set it here for state tracking */ | |
6094 | if (crtc->pipe == PIPE_B) | |
6095 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
6096 | dpll |= DPLL_VCO_ENABLE; | |
d288f65f | 6097 | pipe_config->dpll_hw_state.dpll = dpll; |
bdd4b6a6 | 6098 | |
d288f65f | 6099 | dpll_md = (pipe_config->pixel_multiplier - 1) |
bdd4b6a6 | 6100 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
d288f65f | 6101 | pipe_config->dpll_hw_state.dpll_md = dpll_md; |
bdd4b6a6 DV |
6102 | } |
6103 | ||
d288f65f | 6104 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 6105 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 6106 | { |
f47709a9 | 6107 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 6108 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 6109 | int pipe = crtc->pipe; |
bdd4b6a6 | 6110 | u32 mdiv; |
a0c4da24 | 6111 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 6112 | u32 coreclk, reg_val; |
a0c4da24 | 6113 | |
09153000 DV |
6114 | mutex_lock(&dev_priv->dpio_lock); |
6115 | ||
d288f65f VS |
6116 | bestn = pipe_config->dpll.n; |
6117 | bestm1 = pipe_config->dpll.m1; | |
6118 | bestm2 = pipe_config->dpll.m2; | |
6119 | bestp1 = pipe_config->dpll.p1; | |
6120 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 6121 | |
89b667f8 JB |
6122 | /* See eDP HDMI DPIO driver vbios notes doc */ |
6123 | ||
6124 | /* PLL B needs special handling */ | |
bdd4b6a6 | 6125 | if (pipe == PIPE_B) |
5e69f97f | 6126 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
6127 | |
6128 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 6129 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
6130 | |
6131 | /* Disable target IRef on PLL */ | |
ab3c759a | 6132 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 6133 | reg_val &= 0x00ffffff; |
ab3c759a | 6134 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
6135 | |
6136 | /* Disable fast lock */ | |
ab3c759a | 6137 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
6138 | |
6139 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
6140 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
6141 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
6142 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 6143 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
6144 | |
6145 | /* | |
6146 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
6147 | * but we don't support that). | |
6148 | * Note: don't use the DAC post divider as it seems unstable. | |
6149 | */ | |
6150 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 6151 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6152 | |
a0c4da24 | 6153 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 6154 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6155 | |
89b667f8 | 6156 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 6157 | if (pipe_config->port_clock == 162000 || |
409ee761 ACO |
6158 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || |
6159 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 6160 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 6161 | 0x009f0003); |
89b667f8 | 6162 | else |
ab3c759a | 6163 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
6164 | 0x00d0000f); |
6165 | ||
681a8504 | 6166 | if (pipe_config->has_dp_encoder) { |
89b667f8 | 6167 | /* Use SSC source */ |
bdd4b6a6 | 6168 | if (pipe == PIPE_A) |
ab3c759a | 6169 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6170 | 0x0df40000); |
6171 | else | |
ab3c759a | 6172 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6173 | 0x0df70000); |
6174 | } else { /* HDMI or VGA */ | |
6175 | /* Use bend source */ | |
bdd4b6a6 | 6176 | if (pipe == PIPE_A) |
ab3c759a | 6177 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6178 | 0x0df70000); |
6179 | else | |
ab3c759a | 6180 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6181 | 0x0df40000); |
6182 | } | |
a0c4da24 | 6183 | |
ab3c759a | 6184 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 6185 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
409ee761 ACO |
6186 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
6187 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) | |
89b667f8 | 6188 | coreclk |= 0x01000000; |
ab3c759a | 6189 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 6190 | |
ab3c759a | 6191 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
09153000 | 6192 | mutex_unlock(&dev_priv->dpio_lock); |
a0c4da24 JB |
6193 | } |
6194 | ||
d288f65f | 6195 | static void chv_update_pll(struct intel_crtc *crtc, |
5cec258b | 6196 | struct intel_crtc_state *pipe_config) |
1ae0d137 | 6197 | { |
d288f65f | 6198 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV | |
1ae0d137 VS |
6199 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | |
6200 | DPLL_VCO_ENABLE; | |
6201 | if (crtc->pipe != PIPE_A) | |
d288f65f | 6202 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
1ae0d137 | 6203 | |
d288f65f VS |
6204 | pipe_config->dpll_hw_state.dpll_md = |
6205 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
1ae0d137 VS |
6206 | } |
6207 | ||
d288f65f | 6208 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 6209 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
6210 | { |
6211 | struct drm_device *dev = crtc->base.dev; | |
6212 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6213 | int pipe = crtc->pipe; | |
6214 | int dpll_reg = DPLL(crtc->pipe); | |
6215 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9cbe40c1 | 6216 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 6217 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 6218 | u32 dpio_val; |
9cbe40c1 | 6219 | int vco; |
9d556c99 | 6220 | |
d288f65f VS |
6221 | bestn = pipe_config->dpll.n; |
6222 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
6223 | bestm1 = pipe_config->dpll.m1; | |
6224 | bestm2 = pipe_config->dpll.m2 >> 22; | |
6225 | bestp1 = pipe_config->dpll.p1; | |
6226 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 6227 | vco = pipe_config->dpll.vco; |
a945ce7e | 6228 | dpio_val = 0; |
9cbe40c1 | 6229 | loopfilter = 0; |
9d556c99 CML |
6230 | |
6231 | /* | |
6232 | * Enable Refclk and SSC | |
6233 | */ | |
a11b0703 | 6234 | I915_WRITE(dpll_reg, |
d288f65f | 6235 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
a11b0703 VS |
6236 | |
6237 | mutex_lock(&dev_priv->dpio_lock); | |
9d556c99 | 6238 | |
9d556c99 CML |
6239 | /* p1 and p2 divider */ |
6240 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
6241 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
6242 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
6243 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
6244 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
6245 | ||
6246 | /* Feedback post-divider - m2 */ | |
6247 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
6248 | ||
6249 | /* Feedback refclk divider - n and m1 */ | |
6250 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
6251 | DPIO_CHV_M1_DIV_BY_2 | | |
6252 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
6253 | ||
6254 | /* M2 fraction division */ | |
a945ce7e VP |
6255 | if (bestm2_frac) |
6256 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); | |
9d556c99 CML |
6257 | |
6258 | /* M2 fraction division enable */ | |
a945ce7e VP |
6259 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
6260 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
6261 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
6262 | if (bestm2_frac) | |
6263 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
6264 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 6265 | |
de3a0fde VP |
6266 | /* Program digital lock detect threshold */ |
6267 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
6268 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
6269 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
6270 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
6271 | if (!bestm2_frac) | |
6272 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
6273 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
6274 | ||
9d556c99 | 6275 | /* Loop filter */ |
9cbe40c1 VP |
6276 | if (vco == 5400000) { |
6277 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6278 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
6279 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6280 | tribuf_calcntr = 0x9; | |
6281 | } else if (vco <= 6200000) { | |
6282 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6283 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
6284 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6285 | tribuf_calcntr = 0x9; | |
6286 | } else if (vco <= 6480000) { | |
6287 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6288 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
6289 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6290 | tribuf_calcntr = 0x8; | |
6291 | } else { | |
6292 | /* Not supported. Apply the same limits as in the max case */ | |
6293 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6294 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
6295 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6296 | tribuf_calcntr = 0; | |
6297 | } | |
9d556c99 CML |
6298 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
6299 | ||
968040b2 | 6300 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
6301 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
6302 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
6303 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
6304 | ||
9d556c99 CML |
6305 | /* AFC Recal */ |
6306 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
6307 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
6308 | DPIO_AFC_RECAL); | |
6309 | ||
6310 | mutex_unlock(&dev_priv->dpio_lock); | |
6311 | } | |
6312 | ||
d288f65f VS |
6313 | /** |
6314 | * vlv_force_pll_on - forcibly enable just the PLL | |
6315 | * @dev_priv: i915 private structure | |
6316 | * @pipe: pipe PLL to enable | |
6317 | * @dpll: PLL configuration | |
6318 | * | |
6319 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
6320 | * in cases where we need the PLL enabled even when @pipe is not going to | |
6321 | * be enabled. | |
6322 | */ | |
6323 | void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, | |
6324 | const struct dpll *dpll) | |
6325 | { | |
6326 | struct intel_crtc *crtc = | |
6327 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
5cec258b | 6328 | struct intel_crtc_state pipe_config = { |
d288f65f VS |
6329 | .pixel_multiplier = 1, |
6330 | .dpll = *dpll, | |
6331 | }; | |
6332 | ||
6333 | if (IS_CHERRYVIEW(dev)) { | |
6334 | chv_update_pll(crtc, &pipe_config); | |
6335 | chv_prepare_pll(crtc, &pipe_config); | |
6336 | chv_enable_pll(crtc, &pipe_config); | |
6337 | } else { | |
6338 | vlv_update_pll(crtc, &pipe_config); | |
6339 | vlv_prepare_pll(crtc, &pipe_config); | |
6340 | vlv_enable_pll(crtc, &pipe_config); | |
6341 | } | |
6342 | } | |
6343 | ||
6344 | /** | |
6345 | * vlv_force_pll_off - forcibly disable just the PLL | |
6346 | * @dev_priv: i915 private structure | |
6347 | * @pipe: pipe PLL to disable | |
6348 | * | |
6349 | * Disable the PLL for @pipe. To be used in cases where we need | |
6350 | * the PLL enabled even when @pipe is not going to be enabled. | |
6351 | */ | |
6352 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
6353 | { | |
6354 | if (IS_CHERRYVIEW(dev)) | |
6355 | chv_disable_pll(to_i915(dev), pipe); | |
6356 | else | |
6357 | vlv_disable_pll(to_i915(dev), pipe); | |
6358 | } | |
6359 | ||
f47709a9 | 6360 | static void i9xx_update_pll(struct intel_crtc *crtc, |
190f68c5 | 6361 | struct intel_crtc_state *crtc_state, |
f47709a9 | 6362 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
6363 | int num_connectors) |
6364 | { | |
f47709a9 | 6365 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 6366 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
6367 | u32 dpll; |
6368 | bool is_sdvo; | |
190f68c5 | 6369 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 6370 | |
190f68c5 | 6371 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 6372 | |
d0737e1d ACO |
6373 | is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) || |
6374 | intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
6375 | |
6376 | dpll = DPLL_VGA_MODE_DIS; | |
6377 | ||
d0737e1d | 6378 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
6379 | dpll |= DPLLB_MODE_LVDS; |
6380 | else | |
6381 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 6382 | |
ef1b460d | 6383 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 6384 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 6385 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 6386 | } |
198a037f DV |
6387 | |
6388 | if (is_sdvo) | |
4a33e48d | 6389 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 6390 | |
190f68c5 | 6391 | if (crtc_state->has_dp_encoder) |
4a33e48d | 6392 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
6393 | |
6394 | /* compute bitmask from p1 value */ | |
6395 | if (IS_PINEVIEW(dev)) | |
6396 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
6397 | else { | |
6398 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
6399 | if (IS_G4X(dev) && reduced_clock) | |
6400 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
6401 | } | |
6402 | switch (clock->p2) { | |
6403 | case 5: | |
6404 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
6405 | break; | |
6406 | case 7: | |
6407 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
6408 | break; | |
6409 | case 10: | |
6410 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
6411 | break; | |
6412 | case 14: | |
6413 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
6414 | break; | |
6415 | } | |
6416 | if (INTEL_INFO(dev)->gen >= 4) | |
6417 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
6418 | ||
190f68c5 | 6419 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 6420 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
d0737e1d | 6421 | else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
6422 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
6423 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
6424 | else | |
6425 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6426 | ||
6427 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 6428 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 6429 | |
eb1cbe48 | 6430 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 6431 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 6432 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 6433 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
6434 | } |
6435 | } | |
6436 | ||
f47709a9 | 6437 | static void i8xx_update_pll(struct intel_crtc *crtc, |
190f68c5 | 6438 | struct intel_crtc_state *crtc_state, |
f47709a9 | 6439 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
6440 | int num_connectors) |
6441 | { | |
f47709a9 | 6442 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 6443 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 6444 | u32 dpll; |
190f68c5 | 6445 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 6446 | |
190f68c5 | 6447 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 6448 | |
eb1cbe48 DV |
6449 | dpll = DPLL_VGA_MODE_DIS; |
6450 | ||
d0737e1d | 6451 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
6452 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
6453 | } else { | |
6454 | if (clock->p1 == 2) | |
6455 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
6456 | else | |
6457 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
6458 | if (clock->p2 == 4) | |
6459 | dpll |= PLL_P2_DIVIDE_BY_4; | |
6460 | } | |
6461 | ||
d0737e1d | 6462 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
6463 | dpll |= DPLL_DVO_2X_MODE; |
6464 | ||
d0737e1d | 6465 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
6466 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
6467 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
6468 | else | |
6469 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6470 | ||
6471 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 6472 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
6473 | } |
6474 | ||
8a654f3b | 6475 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
6476 | { |
6477 | struct drm_device *dev = intel_crtc->base.dev; | |
6478 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6479 | enum pipe pipe = intel_crtc->pipe; | |
6e3c9717 | 6480 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
8a654f3b | 6481 | struct drm_display_mode *adjusted_mode = |
6e3c9717 | 6482 | &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
6483 | uint32_t crtc_vtotal, crtc_vblank_end; |
6484 | int vsyncshift = 0; | |
4d8a62ea DV |
6485 | |
6486 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
6487 | * the hw state checker will get angry at the mismatch. */ | |
6488 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
6489 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 6490 | |
609aeaca | 6491 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 6492 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
6493 | crtc_vtotal -= 1; |
6494 | crtc_vblank_end -= 1; | |
609aeaca | 6495 | |
409ee761 | 6496 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
6497 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
6498 | else | |
6499 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
6500 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
6501 | if (vsyncshift < 0) |
6502 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
6503 | } |
6504 | ||
6505 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 6506 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 6507 | |
fe2b8f9d | 6508 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
6509 | (adjusted_mode->crtc_hdisplay - 1) | |
6510 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 6511 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
6512 | (adjusted_mode->crtc_hblank_start - 1) | |
6513 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 6514 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
6515 | (adjusted_mode->crtc_hsync_start - 1) | |
6516 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
6517 | ||
fe2b8f9d | 6518 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 6519 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 6520 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 6521 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 6522 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 6523 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 6524 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
6525 | (adjusted_mode->crtc_vsync_start - 1) | |
6526 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
6527 | ||
b5e508d4 PZ |
6528 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
6529 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
6530 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
6531 | * bits. */ | |
6532 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
6533 | (pipe == PIPE_B || pipe == PIPE_C)) | |
6534 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
6535 | ||
b0e77b9c PZ |
6536 | /* pipesrc controls the size that is scaled from, which should |
6537 | * always be the user's requested size. | |
6538 | */ | |
6539 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
6540 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
6541 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
6542 | } |
6543 | ||
1bd1bd80 | 6544 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 6545 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
6546 | { |
6547 | struct drm_device *dev = crtc->base.dev; | |
6548 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6549 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
6550 | uint32_t tmp; | |
6551 | ||
6552 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
6553 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
6554 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6555 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
6556 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
6557 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6558 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
6559 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
6560 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
6561 | |
6562 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
6563 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
6564 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6565 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
6566 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
6567 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6568 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
6569 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
6570 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
6571 | |
6572 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
6573 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
6574 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
6575 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 DV |
6576 | } |
6577 | ||
6578 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
6579 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
6580 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
6581 | ||
2d112de7 ACO |
6582 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
6583 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
6584 | } |
6585 | ||
f6a83288 | 6586 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 6587 | struct intel_crtc_state *pipe_config) |
babea61d | 6588 | { |
2d112de7 ACO |
6589 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
6590 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
6591 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
6592 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 6593 | |
2d112de7 ACO |
6594 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
6595 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
6596 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
6597 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 6598 | |
2d112de7 | 6599 | mode->flags = pipe_config->base.adjusted_mode.flags; |
babea61d | 6600 | |
2d112de7 ACO |
6601 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
6602 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
babea61d JB |
6603 | } |
6604 | ||
84b046f3 DV |
6605 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
6606 | { | |
6607 | struct drm_device *dev = intel_crtc->base.dev; | |
6608 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6609 | uint32_t pipeconf; | |
6610 | ||
9f11a9e4 | 6611 | pipeconf = 0; |
84b046f3 | 6612 | |
b6b5d049 VS |
6613 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
6614 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
6615 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 6616 | |
6e3c9717 | 6617 | if (intel_crtc->config->double_wide) |
cf532bb2 | 6618 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 6619 | |
ff9ce46e DV |
6620 | /* only g4x and later have fancy bpc/dither controls */ |
6621 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
ff9ce46e | 6622 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 6623 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 6624 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 6625 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 6626 | |
6e3c9717 | 6627 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
6628 | case 18: |
6629 | pipeconf |= PIPECONF_6BPC; | |
6630 | break; | |
6631 | case 24: | |
6632 | pipeconf |= PIPECONF_8BPC; | |
6633 | break; | |
6634 | case 30: | |
6635 | pipeconf |= PIPECONF_10BPC; | |
6636 | break; | |
6637 | default: | |
6638 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
6639 | BUG(); | |
84b046f3 DV |
6640 | } |
6641 | } | |
6642 | ||
6643 | if (HAS_PIPE_CXSR(dev)) { | |
6644 | if (intel_crtc->lowfreq_avail) { | |
6645 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
6646 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
6647 | } else { | |
6648 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
6649 | } |
6650 | } | |
6651 | ||
6e3c9717 | 6652 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 6653 | if (INTEL_INFO(dev)->gen < 4 || |
409ee761 | 6654 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
6655 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
6656 | else | |
6657 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
6658 | } else | |
84b046f3 DV |
6659 | pipeconf |= PIPECONF_PROGRESSIVE; |
6660 | ||
6e3c9717 | 6661 | if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range) |
9f11a9e4 | 6662 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 6663 | |
84b046f3 DV |
6664 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
6665 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
6666 | } | |
6667 | ||
190f68c5 ACO |
6668 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
6669 | struct intel_crtc_state *crtc_state) | |
79e53945 | 6670 | { |
c7653199 | 6671 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 6672 | struct drm_i915_private *dev_priv = dev->dev_private; |
c751ce4f | 6673 | int refclk, num_connectors = 0; |
652c393a | 6674 | intel_clock_t clock, reduced_clock; |
a16af721 | 6675 | bool ok, has_reduced_clock = false; |
e9fd1c02 | 6676 | bool is_lvds = false, is_dsi = false; |
5eddb70b | 6677 | struct intel_encoder *encoder; |
d4906093 | 6678 | const intel_limit_t *limit; |
79e53945 | 6679 | |
d0737e1d ACO |
6680 | for_each_intel_encoder(dev, encoder) { |
6681 | if (encoder->new_crtc != crtc) | |
6682 | continue; | |
6683 | ||
5eddb70b | 6684 | switch (encoder->type) { |
79e53945 JB |
6685 | case INTEL_OUTPUT_LVDS: |
6686 | is_lvds = true; | |
6687 | break; | |
e9fd1c02 JN |
6688 | case INTEL_OUTPUT_DSI: |
6689 | is_dsi = true; | |
6690 | break; | |
6847d71b PZ |
6691 | default: |
6692 | break; | |
79e53945 | 6693 | } |
43565a06 | 6694 | |
c751ce4f | 6695 | num_connectors++; |
79e53945 JB |
6696 | } |
6697 | ||
f2335330 | 6698 | if (is_dsi) |
5b18e57c | 6699 | return 0; |
f2335330 | 6700 | |
190f68c5 | 6701 | if (!crtc_state->clock_set) { |
409ee761 | 6702 | refclk = i9xx_get_refclk(crtc, num_connectors); |
79e53945 | 6703 | |
e9fd1c02 JN |
6704 | /* |
6705 | * Returns a set of divisors for the desired target clock with | |
6706 | * the given refclk, or FALSE. The returned values represent | |
6707 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
6708 | * 2) / p1 / p2. | |
6709 | */ | |
409ee761 | 6710 | limit = intel_limit(crtc, refclk); |
c7653199 | 6711 | ok = dev_priv->display.find_dpll(limit, crtc, |
190f68c5 | 6712 | crtc_state->port_clock, |
e9fd1c02 | 6713 | refclk, NULL, &clock); |
f2335330 | 6714 | if (!ok) { |
e9fd1c02 JN |
6715 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
6716 | return -EINVAL; | |
6717 | } | |
79e53945 | 6718 | |
f2335330 JN |
6719 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
6720 | /* | |
6721 | * Ensure we match the reduced clock's P to the target | |
6722 | * clock. If the clocks don't match, we can't switch | |
6723 | * the display clock by using the FP0/FP1. In such case | |
6724 | * we will disable the LVDS downclock feature. | |
6725 | */ | |
6726 | has_reduced_clock = | |
c7653199 | 6727 | dev_priv->display.find_dpll(limit, crtc, |
f2335330 JN |
6728 | dev_priv->lvds_downclock, |
6729 | refclk, &clock, | |
6730 | &reduced_clock); | |
6731 | } | |
6732 | /* Compat-code for transition, will disappear. */ | |
190f68c5 ACO |
6733 | crtc_state->dpll.n = clock.n; |
6734 | crtc_state->dpll.m1 = clock.m1; | |
6735 | crtc_state->dpll.m2 = clock.m2; | |
6736 | crtc_state->dpll.p1 = clock.p1; | |
6737 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 6738 | } |
7026d4ac | 6739 | |
e9fd1c02 | 6740 | if (IS_GEN2(dev)) { |
190f68c5 | 6741 | i8xx_update_pll(crtc, crtc_state, |
2a8f64ca VP |
6742 | has_reduced_clock ? &reduced_clock : NULL, |
6743 | num_connectors); | |
9d556c99 | 6744 | } else if (IS_CHERRYVIEW(dev)) { |
190f68c5 | 6745 | chv_update_pll(crtc, crtc_state); |
e9fd1c02 | 6746 | } else if (IS_VALLEYVIEW(dev)) { |
190f68c5 | 6747 | vlv_update_pll(crtc, crtc_state); |
e9fd1c02 | 6748 | } else { |
190f68c5 | 6749 | i9xx_update_pll(crtc, crtc_state, |
eb1cbe48 | 6750 | has_reduced_clock ? &reduced_clock : NULL, |
eba905b2 | 6751 | num_connectors); |
e9fd1c02 | 6752 | } |
79e53945 | 6753 | |
c8f7a0db | 6754 | return 0; |
f564048e EA |
6755 | } |
6756 | ||
2fa2fe9a | 6757 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 6758 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
6759 | { |
6760 | struct drm_device *dev = crtc->base.dev; | |
6761 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6762 | uint32_t tmp; | |
6763 | ||
dc9e7dec VS |
6764 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
6765 | return; | |
6766 | ||
2fa2fe9a | 6767 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
6768 | if (!(tmp & PFIT_ENABLE)) |
6769 | return; | |
2fa2fe9a | 6770 | |
06922821 | 6771 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
6772 | if (INTEL_INFO(dev)->gen < 4) { |
6773 | if (crtc->pipe != PIPE_B) | |
6774 | return; | |
2fa2fe9a DV |
6775 | } else { |
6776 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
6777 | return; | |
6778 | } | |
6779 | ||
06922821 | 6780 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
6781 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
6782 | if (INTEL_INFO(dev)->gen < 5) | |
6783 | pipe_config->gmch_pfit.lvds_border_bits = | |
6784 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
6785 | } | |
6786 | ||
acbec814 | 6787 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 6788 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
6789 | { |
6790 | struct drm_device *dev = crtc->base.dev; | |
6791 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6792 | int pipe = pipe_config->cpu_transcoder; | |
6793 | intel_clock_t clock; | |
6794 | u32 mdiv; | |
662c6ecb | 6795 | int refclk = 100000; |
acbec814 | 6796 | |
f573de5a SK |
6797 | /* In case of MIPI DPLL will not even be used */ |
6798 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) | |
6799 | return; | |
6800 | ||
acbec814 | 6801 | mutex_lock(&dev_priv->dpio_lock); |
ab3c759a | 6802 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
acbec814 JB |
6803 | mutex_unlock(&dev_priv->dpio_lock); |
6804 | ||
6805 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
6806 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
6807 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
6808 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
6809 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
6810 | ||
f646628b | 6811 | vlv_clock(refclk, &clock); |
acbec814 | 6812 | |
f646628b VS |
6813 | /* clock.dot is the fast clock */ |
6814 | pipe_config->port_clock = clock.dot / 5; | |
acbec814 JB |
6815 | } |
6816 | ||
5724dbd1 DL |
6817 | static void |
6818 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
6819 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
6820 | { |
6821 | struct drm_device *dev = crtc->base.dev; | |
6822 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6823 | u32 val, base, offset; | |
6824 | int pipe = crtc->pipe, plane = crtc->plane; | |
6825 | int fourcc, pixel_format; | |
6761dd31 | 6826 | unsigned int aligned_height; |
b113d5ee | 6827 | struct drm_framebuffer *fb; |
1b842c89 | 6828 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 6829 | |
42a7b088 DL |
6830 | val = I915_READ(DSPCNTR(plane)); |
6831 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
6832 | return; | |
6833 | ||
d9806c9f | 6834 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 6835 | if (!intel_fb) { |
1ad292b5 JB |
6836 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
6837 | return; | |
6838 | } | |
6839 | ||
1b842c89 DL |
6840 | fb = &intel_fb->base; |
6841 | ||
18c5247e DV |
6842 | if (INTEL_INFO(dev)->gen >= 4) { |
6843 | if (val & DISPPLANE_TILED) { | |
49af449b | 6844 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
6845 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
6846 | } | |
6847 | } | |
1ad292b5 JB |
6848 | |
6849 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 6850 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
6851 | fb->pixel_format = fourcc; |
6852 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
6853 | |
6854 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 6855 | if (plane_config->tiling) |
1ad292b5 JB |
6856 | offset = I915_READ(DSPTILEOFF(plane)); |
6857 | else | |
6858 | offset = I915_READ(DSPLINOFF(plane)); | |
6859 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
6860 | } else { | |
6861 | base = I915_READ(DSPADDR(plane)); | |
6862 | } | |
6863 | plane_config->base = base; | |
6864 | ||
6865 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
6866 | fb->width = ((val >> 16) & 0xfff) + 1; |
6867 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
6868 | |
6869 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 6870 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 6871 | |
b113d5ee | 6872 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
6873 | fb->pixel_format, |
6874 | fb->modifier[0]); | |
1ad292b5 | 6875 | |
f37b5c2b | 6876 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 6877 | |
2844a921 DL |
6878 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
6879 | pipe_name(pipe), plane, fb->width, fb->height, | |
6880 | fb->bits_per_pixel, base, fb->pitches[0], | |
6881 | plane_config->size); | |
1ad292b5 | 6882 | |
2d14030b | 6883 | plane_config->fb = intel_fb; |
1ad292b5 JB |
6884 | } |
6885 | ||
70b23a98 | 6886 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 6887 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
6888 | { |
6889 | struct drm_device *dev = crtc->base.dev; | |
6890 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6891 | int pipe = pipe_config->cpu_transcoder; | |
6892 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
6893 | intel_clock_t clock; | |
6894 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2; | |
6895 | int refclk = 100000; | |
6896 | ||
6897 | mutex_lock(&dev_priv->dpio_lock); | |
6898 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); | |
6899 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
6900 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
6901 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
6902 | mutex_unlock(&dev_priv->dpio_lock); | |
6903 | ||
6904 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
6905 | clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff); | |
6906 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; | |
6907 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
6908 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
6909 | ||
6910 | chv_clock(refclk, &clock); | |
6911 | ||
6912 | /* clock.dot is the fast clock */ | |
6913 | pipe_config->port_clock = clock.dot / 5; | |
6914 | } | |
6915 | ||
0e8ffe1b | 6916 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 6917 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
6918 | { |
6919 | struct drm_device *dev = crtc->base.dev; | |
6920 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6921 | uint32_t tmp; | |
6922 | ||
f458ebbc DV |
6923 | if (!intel_display_power_is_enabled(dev_priv, |
6924 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
b5482bd0 ID |
6925 | return false; |
6926 | ||
e143a21c | 6927 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 6928 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 6929 | |
0e8ffe1b DV |
6930 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
6931 | if (!(tmp & PIPECONF_ENABLE)) | |
6932 | return false; | |
6933 | ||
42571aef VS |
6934 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
6935 | switch (tmp & PIPECONF_BPC_MASK) { | |
6936 | case PIPECONF_6BPC: | |
6937 | pipe_config->pipe_bpp = 18; | |
6938 | break; | |
6939 | case PIPECONF_8BPC: | |
6940 | pipe_config->pipe_bpp = 24; | |
6941 | break; | |
6942 | case PIPECONF_10BPC: | |
6943 | pipe_config->pipe_bpp = 30; | |
6944 | break; | |
6945 | default: | |
6946 | break; | |
6947 | } | |
6948 | } | |
6949 | ||
b5a9fa09 DV |
6950 | if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
6951 | pipe_config->limited_color_range = true; | |
6952 | ||
282740f7 VS |
6953 | if (INTEL_INFO(dev)->gen < 4) |
6954 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
6955 | ||
1bd1bd80 DV |
6956 | intel_get_pipe_timings(crtc, pipe_config); |
6957 | ||
2fa2fe9a DV |
6958 | i9xx_get_pfit_config(crtc, pipe_config); |
6959 | ||
6c49f241 DV |
6960 | if (INTEL_INFO(dev)->gen >= 4) { |
6961 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
6962 | pipe_config->pixel_multiplier = | |
6963 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
6964 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 6965 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
6966 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
6967 | tmp = I915_READ(DPLL(crtc->pipe)); | |
6968 | pipe_config->pixel_multiplier = | |
6969 | ((tmp & SDVO_MULTIPLIER_MASK) | |
6970 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
6971 | } else { | |
6972 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
6973 | * port and will be fixed up in the encoder->get_config | |
6974 | * function. */ | |
6975 | pipe_config->pixel_multiplier = 1; | |
6976 | } | |
8bcc2795 DV |
6977 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
6978 | if (!IS_VALLEYVIEW(dev)) { | |
1c4e0274 VS |
6979 | /* |
6980 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
6981 | * on 830. Filter it out here so that we don't | |
6982 | * report errors due to that. | |
6983 | */ | |
6984 | if (IS_I830(dev)) | |
6985 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
6986 | ||
8bcc2795 DV |
6987 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
6988 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
6989 | } else { |
6990 | /* Mask out read-only status bits. */ | |
6991 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
6992 | DPLL_PORTC_READY_MASK | | |
6993 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 6994 | } |
6c49f241 | 6995 | |
70b23a98 VS |
6996 | if (IS_CHERRYVIEW(dev)) |
6997 | chv_crtc_clock_get(crtc, pipe_config); | |
6998 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
6999 | vlv_crtc_clock_get(crtc, pipe_config); |
7000 | else | |
7001 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 7002 | |
0e8ffe1b DV |
7003 | return true; |
7004 | } | |
7005 | ||
dde86e2d | 7006 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
7007 | { |
7008 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 7009 | struct intel_encoder *encoder; |
74cfd7ac | 7010 | u32 val, final; |
13d83a67 | 7011 | bool has_lvds = false; |
199e5d79 | 7012 | bool has_cpu_edp = false; |
199e5d79 | 7013 | bool has_panel = false; |
99eb6a01 KP |
7014 | bool has_ck505 = false; |
7015 | bool can_ssc = false; | |
13d83a67 JB |
7016 | |
7017 | /* We need to take the global config into account */ | |
b2784e15 | 7018 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
7019 | switch (encoder->type) { |
7020 | case INTEL_OUTPUT_LVDS: | |
7021 | has_panel = true; | |
7022 | has_lvds = true; | |
7023 | break; | |
7024 | case INTEL_OUTPUT_EDP: | |
7025 | has_panel = true; | |
2de6905f | 7026 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
7027 | has_cpu_edp = true; |
7028 | break; | |
6847d71b PZ |
7029 | default: |
7030 | break; | |
13d83a67 JB |
7031 | } |
7032 | } | |
7033 | ||
99eb6a01 | 7034 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 7035 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
7036 | can_ssc = has_ck505; |
7037 | } else { | |
7038 | has_ck505 = false; | |
7039 | can_ssc = true; | |
7040 | } | |
7041 | ||
2de6905f ID |
7042 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
7043 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
7044 | |
7045 | /* Ironlake: try to setup display ref clock before DPLL | |
7046 | * enabling. This is only under driver's control after | |
7047 | * PCH B stepping, previous chipset stepping should be | |
7048 | * ignoring this setting. | |
7049 | */ | |
74cfd7ac CW |
7050 | val = I915_READ(PCH_DREF_CONTROL); |
7051 | ||
7052 | /* As we must carefully and slowly disable/enable each source in turn, | |
7053 | * compute the final state we want first and check if we need to | |
7054 | * make any changes at all. | |
7055 | */ | |
7056 | final = val; | |
7057 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
7058 | if (has_ck505) | |
7059 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
7060 | else | |
7061 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
7062 | ||
7063 | final &= ~DREF_SSC_SOURCE_MASK; | |
7064 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
7065 | final &= ~DREF_SSC1_ENABLE; | |
7066 | ||
7067 | if (has_panel) { | |
7068 | final |= DREF_SSC_SOURCE_ENABLE; | |
7069 | ||
7070 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
7071 | final |= DREF_SSC1_ENABLE; | |
7072 | ||
7073 | if (has_cpu_edp) { | |
7074 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
7075 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
7076 | else | |
7077 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
7078 | } else | |
7079 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
7080 | } else { | |
7081 | final |= DREF_SSC_SOURCE_DISABLE; | |
7082 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
7083 | } | |
7084 | ||
7085 | if (final == val) | |
7086 | return; | |
7087 | ||
13d83a67 | 7088 | /* Always enable nonspread source */ |
74cfd7ac | 7089 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 7090 | |
99eb6a01 | 7091 | if (has_ck505) |
74cfd7ac | 7092 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 7093 | else |
74cfd7ac | 7094 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 7095 | |
199e5d79 | 7096 | if (has_panel) { |
74cfd7ac CW |
7097 | val &= ~DREF_SSC_SOURCE_MASK; |
7098 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 7099 | |
199e5d79 | 7100 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 7101 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 7102 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 7103 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 7104 | } else |
74cfd7ac | 7105 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
7106 | |
7107 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 7108 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7109 | POSTING_READ(PCH_DREF_CONTROL); |
7110 | udelay(200); | |
7111 | ||
74cfd7ac | 7112 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
7113 | |
7114 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 7115 | if (has_cpu_edp) { |
99eb6a01 | 7116 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 7117 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 7118 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 7119 | } else |
74cfd7ac | 7120 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 7121 | } else |
74cfd7ac | 7122 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7123 | |
74cfd7ac | 7124 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7125 | POSTING_READ(PCH_DREF_CONTROL); |
7126 | udelay(200); | |
7127 | } else { | |
7128 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
7129 | ||
74cfd7ac | 7130 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
7131 | |
7132 | /* Turn off CPU output */ | |
74cfd7ac | 7133 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7134 | |
74cfd7ac | 7135 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7136 | POSTING_READ(PCH_DREF_CONTROL); |
7137 | udelay(200); | |
7138 | ||
7139 | /* Turn off the SSC source */ | |
74cfd7ac CW |
7140 | val &= ~DREF_SSC_SOURCE_MASK; |
7141 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
7142 | |
7143 | /* Turn off SSC1 */ | |
74cfd7ac | 7144 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 7145 | |
74cfd7ac | 7146 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
7147 | POSTING_READ(PCH_DREF_CONTROL); |
7148 | udelay(200); | |
7149 | } | |
74cfd7ac CW |
7150 | |
7151 | BUG_ON(val != final); | |
13d83a67 JB |
7152 | } |
7153 | ||
f31f2d55 | 7154 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 7155 | { |
f31f2d55 | 7156 | uint32_t tmp; |
dde86e2d | 7157 | |
0ff066a9 PZ |
7158 | tmp = I915_READ(SOUTH_CHICKEN2); |
7159 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
7160 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7161 | |
0ff066a9 PZ |
7162 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
7163 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
7164 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 7165 | |
0ff066a9 PZ |
7166 | tmp = I915_READ(SOUTH_CHICKEN2); |
7167 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
7168 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7169 | |
0ff066a9 PZ |
7170 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
7171 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
7172 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
7173 | } |
7174 | ||
7175 | /* WaMPhyProgramming:hsw */ | |
7176 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
7177 | { | |
7178 | uint32_t tmp; | |
dde86e2d PZ |
7179 | |
7180 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
7181 | tmp &= ~(0xFF << 24); | |
7182 | tmp |= (0x12 << 24); | |
7183 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
7184 | ||
dde86e2d PZ |
7185 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
7186 | tmp |= (1 << 11); | |
7187 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
7188 | ||
7189 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
7190 | tmp |= (1 << 11); | |
7191 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
7192 | ||
dde86e2d PZ |
7193 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
7194 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7195 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
7196 | ||
7197 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
7198 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7199 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
7200 | ||
0ff066a9 PZ |
7201 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
7202 | tmp &= ~(7 << 13); | |
7203 | tmp |= (5 << 13); | |
7204 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 7205 | |
0ff066a9 PZ |
7206 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
7207 | tmp &= ~(7 << 13); | |
7208 | tmp |= (5 << 13); | |
7209 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
7210 | |
7211 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
7212 | tmp &= ~0xFF; | |
7213 | tmp |= 0x1C; | |
7214 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
7215 | ||
7216 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
7217 | tmp &= ~0xFF; | |
7218 | tmp |= 0x1C; | |
7219 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
7220 | ||
7221 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
7222 | tmp &= ~(0xFF << 16); | |
7223 | tmp |= (0x1C << 16); | |
7224 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
7225 | ||
7226 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
7227 | tmp &= ~(0xFF << 16); | |
7228 | tmp |= (0x1C << 16); | |
7229 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
7230 | ||
0ff066a9 PZ |
7231 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
7232 | tmp |= (1 << 27); | |
7233 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 7234 | |
0ff066a9 PZ |
7235 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
7236 | tmp |= (1 << 27); | |
7237 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 7238 | |
0ff066a9 PZ |
7239 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
7240 | tmp &= ~(0xF << 28); | |
7241 | tmp |= (4 << 28); | |
7242 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 7243 | |
0ff066a9 PZ |
7244 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
7245 | tmp &= ~(0xF << 28); | |
7246 | tmp |= (4 << 28); | |
7247 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
7248 | } |
7249 | ||
2fa86a1f PZ |
7250 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
7251 | * Programming" based on the parameters passed: | |
7252 | * - Sequence to enable CLKOUT_DP | |
7253 | * - Sequence to enable CLKOUT_DP without spread | |
7254 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
7255 | */ | |
7256 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
7257 | bool with_fdi) | |
f31f2d55 PZ |
7258 | { |
7259 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
7260 | uint32_t reg, tmp; |
7261 | ||
7262 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
7263 | with_spread = true; | |
7264 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && | |
7265 | with_fdi, "LP PCH doesn't have FDI\n")) | |
7266 | with_fdi = false; | |
f31f2d55 PZ |
7267 | |
7268 | mutex_lock(&dev_priv->dpio_lock); | |
7269 | ||
7270 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7271 | tmp &= ~SBI_SSCCTL_DISABLE; | |
7272 | tmp |= SBI_SSCCTL_PATHALT; | |
7273 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7274 | ||
7275 | udelay(24); | |
7276 | ||
2fa86a1f PZ |
7277 | if (with_spread) { |
7278 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7279 | tmp &= ~SBI_SSCCTL_PATHALT; | |
7280 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 7281 | |
2fa86a1f PZ |
7282 | if (with_fdi) { |
7283 | lpt_reset_fdi_mphy(dev_priv); | |
7284 | lpt_program_fdi_mphy(dev_priv); | |
7285 | } | |
7286 | } | |
dde86e2d | 7287 | |
2fa86a1f PZ |
7288 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
7289 | SBI_GEN0 : SBI_DBUFF0; | |
7290 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
7291 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
7292 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 DV |
7293 | |
7294 | mutex_unlock(&dev_priv->dpio_lock); | |
dde86e2d PZ |
7295 | } |
7296 | ||
47701c3b PZ |
7297 | /* Sequence to disable CLKOUT_DP */ |
7298 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
7299 | { | |
7300 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7301 | uint32_t reg, tmp; | |
7302 | ||
7303 | mutex_lock(&dev_priv->dpio_lock); | |
7304 | ||
7305 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? | |
7306 | SBI_GEN0 : SBI_DBUFF0; | |
7307 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
7308 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
7309 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
7310 | ||
7311 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7312 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
7313 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
7314 | tmp |= SBI_SSCCTL_PATHALT; | |
7315 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7316 | udelay(32); | |
7317 | } | |
7318 | tmp |= SBI_SSCCTL_DISABLE; | |
7319 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7320 | } | |
7321 | ||
7322 | mutex_unlock(&dev_priv->dpio_lock); | |
7323 | } | |
7324 | ||
bf8fa3d3 PZ |
7325 | static void lpt_init_pch_refclk(struct drm_device *dev) |
7326 | { | |
bf8fa3d3 PZ |
7327 | struct intel_encoder *encoder; |
7328 | bool has_vga = false; | |
7329 | ||
b2784e15 | 7330 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
7331 | switch (encoder->type) { |
7332 | case INTEL_OUTPUT_ANALOG: | |
7333 | has_vga = true; | |
7334 | break; | |
6847d71b PZ |
7335 | default: |
7336 | break; | |
bf8fa3d3 PZ |
7337 | } |
7338 | } | |
7339 | ||
47701c3b PZ |
7340 | if (has_vga) |
7341 | lpt_enable_clkout_dp(dev, true, true); | |
7342 | else | |
7343 | lpt_disable_clkout_dp(dev); | |
bf8fa3d3 PZ |
7344 | } |
7345 | ||
dde86e2d PZ |
7346 | /* |
7347 | * Initialize reference clocks when the driver loads | |
7348 | */ | |
7349 | void intel_init_pch_refclk(struct drm_device *dev) | |
7350 | { | |
7351 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7352 | ironlake_init_pch_refclk(dev); | |
7353 | else if (HAS_PCH_LPT(dev)) | |
7354 | lpt_init_pch_refclk(dev); | |
7355 | } | |
7356 | ||
d9d444cb JB |
7357 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
7358 | { | |
7359 | struct drm_device *dev = crtc->dev; | |
7360 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7361 | struct intel_encoder *encoder; | |
d9d444cb JB |
7362 | int num_connectors = 0; |
7363 | bool is_lvds = false; | |
7364 | ||
d0737e1d ACO |
7365 | for_each_intel_encoder(dev, encoder) { |
7366 | if (encoder->new_crtc != to_intel_crtc(crtc)) | |
7367 | continue; | |
7368 | ||
d9d444cb JB |
7369 | switch (encoder->type) { |
7370 | case INTEL_OUTPUT_LVDS: | |
7371 | is_lvds = true; | |
7372 | break; | |
6847d71b PZ |
7373 | default: |
7374 | break; | |
d9d444cb JB |
7375 | } |
7376 | num_connectors++; | |
7377 | } | |
7378 | ||
7379 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 7380 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 7381 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 7382 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
7383 | } |
7384 | ||
7385 | return 120000; | |
7386 | } | |
7387 | ||
6ff93609 | 7388 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 7389 | { |
c8203565 | 7390 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
7391 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7392 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
7393 | uint32_t val; |
7394 | ||
78114071 | 7395 | val = 0; |
c8203565 | 7396 | |
6e3c9717 | 7397 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 7398 | case 18: |
dfd07d72 | 7399 | val |= PIPECONF_6BPC; |
c8203565 PZ |
7400 | break; |
7401 | case 24: | |
dfd07d72 | 7402 | val |= PIPECONF_8BPC; |
c8203565 PZ |
7403 | break; |
7404 | case 30: | |
dfd07d72 | 7405 | val |= PIPECONF_10BPC; |
c8203565 PZ |
7406 | break; |
7407 | case 36: | |
dfd07d72 | 7408 | val |= PIPECONF_12BPC; |
c8203565 PZ |
7409 | break; |
7410 | default: | |
cc769b62 PZ |
7411 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
7412 | BUG(); | |
c8203565 PZ |
7413 | } |
7414 | ||
6e3c9717 | 7415 | if (intel_crtc->config->dither) |
c8203565 PZ |
7416 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
7417 | ||
6e3c9717 | 7418 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
7419 | val |= PIPECONF_INTERLACED_ILK; |
7420 | else | |
7421 | val |= PIPECONF_PROGRESSIVE; | |
7422 | ||
6e3c9717 | 7423 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 7424 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 7425 | |
c8203565 PZ |
7426 | I915_WRITE(PIPECONF(pipe), val); |
7427 | POSTING_READ(PIPECONF(pipe)); | |
7428 | } | |
7429 | ||
86d3efce VS |
7430 | /* |
7431 | * Set up the pipe CSC unit. | |
7432 | * | |
7433 | * Currently only full range RGB to limited range RGB conversion | |
7434 | * is supported, but eventually this should handle various | |
7435 | * RGB<->YCbCr scenarios as well. | |
7436 | */ | |
50f3b016 | 7437 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
7438 | { |
7439 | struct drm_device *dev = crtc->dev; | |
7440 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7441 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7442 | int pipe = intel_crtc->pipe; | |
7443 | uint16_t coeff = 0x7800; /* 1.0 */ | |
7444 | ||
7445 | /* | |
7446 | * TODO: Check what kind of values actually come out of the pipe | |
7447 | * with these coeff/postoff values and adjust to get the best | |
7448 | * accuracy. Perhaps we even need to take the bpc value into | |
7449 | * consideration. | |
7450 | */ | |
7451 | ||
6e3c9717 | 7452 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
7453 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
7454 | ||
7455 | /* | |
7456 | * GY/GU and RY/RU should be the other way around according | |
7457 | * to BSpec, but reality doesn't agree. Just set them up in | |
7458 | * a way that results in the correct picture. | |
7459 | */ | |
7460 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
7461 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
7462 | ||
7463 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
7464 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
7465 | ||
7466 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
7467 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
7468 | ||
7469 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
7470 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
7471 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
7472 | ||
7473 | if (INTEL_INFO(dev)->gen > 6) { | |
7474 | uint16_t postoff = 0; | |
7475 | ||
6e3c9717 | 7476 | if (intel_crtc->config->limited_color_range) |
32cf0cb0 | 7477 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
7478 | |
7479 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
7480 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
7481 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
7482 | ||
7483 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
7484 | } else { | |
7485 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
7486 | ||
6e3c9717 | 7487 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
7488 | mode |= CSC_BLACK_SCREEN_OFFSET; |
7489 | ||
7490 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
7491 | } | |
7492 | } | |
7493 | ||
6ff93609 | 7494 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 7495 | { |
756f85cf PZ |
7496 | struct drm_device *dev = crtc->dev; |
7497 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 7498 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 7499 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 7500 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee2b0b38 PZ |
7501 | uint32_t val; |
7502 | ||
3eff4faa | 7503 | val = 0; |
ee2b0b38 | 7504 | |
6e3c9717 | 7505 | if (IS_HASWELL(dev) && intel_crtc->config->dither) |
ee2b0b38 PZ |
7506 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
7507 | ||
6e3c9717 | 7508 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
7509 | val |= PIPECONF_INTERLACED_ILK; |
7510 | else | |
7511 | val |= PIPECONF_PROGRESSIVE; | |
7512 | ||
702e7a56 PZ |
7513 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
7514 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
7515 | |
7516 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
7517 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf | 7518 | |
3cdf122c | 7519 | if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { |
756f85cf PZ |
7520 | val = 0; |
7521 | ||
6e3c9717 | 7522 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
7523 | case 18: |
7524 | val |= PIPEMISC_DITHER_6_BPC; | |
7525 | break; | |
7526 | case 24: | |
7527 | val |= PIPEMISC_DITHER_8_BPC; | |
7528 | break; | |
7529 | case 30: | |
7530 | val |= PIPEMISC_DITHER_10_BPC; | |
7531 | break; | |
7532 | case 36: | |
7533 | val |= PIPEMISC_DITHER_12_BPC; | |
7534 | break; | |
7535 | default: | |
7536 | /* Case prevented by pipe_config_set_bpp. */ | |
7537 | BUG(); | |
7538 | } | |
7539 | ||
6e3c9717 | 7540 | if (intel_crtc->config->dither) |
756f85cf PZ |
7541 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
7542 | ||
7543 | I915_WRITE(PIPEMISC(pipe), val); | |
7544 | } | |
ee2b0b38 PZ |
7545 | } |
7546 | ||
6591c6e4 | 7547 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
190f68c5 | 7548 | struct intel_crtc_state *crtc_state, |
6591c6e4 PZ |
7549 | intel_clock_t *clock, |
7550 | bool *has_reduced_clock, | |
7551 | intel_clock_t *reduced_clock) | |
7552 | { | |
7553 | struct drm_device *dev = crtc->dev; | |
7554 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a919ff14 | 7555 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6591c6e4 | 7556 | int refclk; |
d4906093 | 7557 | const intel_limit_t *limit; |
a16af721 | 7558 | bool ret, is_lvds = false; |
79e53945 | 7559 | |
d0737e1d | 7560 | is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS); |
79e53945 | 7561 | |
d9d444cb | 7562 | refclk = ironlake_get_refclk(crtc); |
79e53945 | 7563 | |
d4906093 ML |
7564 | /* |
7565 | * Returns a set of divisors for the desired target clock with the given | |
7566 | * refclk, or FALSE. The returned values represent the clock equation: | |
7567 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
7568 | */ | |
409ee761 | 7569 | limit = intel_limit(intel_crtc, refclk); |
a919ff14 | 7570 | ret = dev_priv->display.find_dpll(limit, intel_crtc, |
190f68c5 | 7571 | crtc_state->port_clock, |
ee9300bb | 7572 | refclk, NULL, clock); |
6591c6e4 PZ |
7573 | if (!ret) |
7574 | return false; | |
cda4b7d3 | 7575 | |
ddc9003c | 7576 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
7577 | /* |
7578 | * Ensure we match the reduced clock's P to the target clock. | |
7579 | * If the clocks don't match, we can't switch the display clock | |
7580 | * by using the FP0/FP1. In such case we will disable the LVDS | |
7581 | * downclock feature. | |
7582 | */ | |
ee9300bb | 7583 | *has_reduced_clock = |
a919ff14 | 7584 | dev_priv->display.find_dpll(limit, intel_crtc, |
ee9300bb DV |
7585 | dev_priv->lvds_downclock, |
7586 | refclk, clock, | |
7587 | reduced_clock); | |
652c393a | 7588 | } |
61e9653f | 7589 | |
6591c6e4 PZ |
7590 | return true; |
7591 | } | |
7592 | ||
d4b1931c PZ |
7593 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
7594 | { | |
7595 | /* | |
7596 | * Account for spread spectrum to avoid | |
7597 | * oversubscribing the link. Max center spread | |
7598 | * is 2.5%; use 5% for safety's sake. | |
7599 | */ | |
7600 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 7601 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
7602 | } |
7603 | ||
7429e9d4 | 7604 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 7605 | { |
7429e9d4 | 7606 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
7607 | } |
7608 | ||
de13a2e3 | 7609 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
190f68c5 | 7610 | struct intel_crtc_state *crtc_state, |
7429e9d4 | 7611 | u32 *fp, |
9a7c7890 | 7612 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 7613 | { |
de13a2e3 | 7614 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
7615 | struct drm_device *dev = crtc->dev; |
7616 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de13a2e3 PZ |
7617 | struct intel_encoder *intel_encoder; |
7618 | uint32_t dpll; | |
6cc5f341 | 7619 | int factor, num_connectors = 0; |
09ede541 | 7620 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 7621 | |
d0737e1d ACO |
7622 | for_each_intel_encoder(dev, intel_encoder) { |
7623 | if (intel_encoder->new_crtc != to_intel_crtc(crtc)) | |
7624 | continue; | |
7625 | ||
de13a2e3 | 7626 | switch (intel_encoder->type) { |
79e53945 JB |
7627 | case INTEL_OUTPUT_LVDS: |
7628 | is_lvds = true; | |
7629 | break; | |
7630 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 7631 | case INTEL_OUTPUT_HDMI: |
79e53945 | 7632 | is_sdvo = true; |
79e53945 | 7633 | break; |
6847d71b PZ |
7634 | default: |
7635 | break; | |
79e53945 | 7636 | } |
43565a06 | 7637 | |
c751ce4f | 7638 | num_connectors++; |
79e53945 | 7639 | } |
79e53945 | 7640 | |
c1858123 | 7641 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
7642 | factor = 21; |
7643 | if (is_lvds) { | |
7644 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 7645 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 7646 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 7647 | factor = 25; |
190f68c5 | 7648 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 7649 | factor = 20; |
c1858123 | 7650 | |
190f68c5 | 7651 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
7d0ac5b7 | 7652 | *fp |= FP_CB_TUNE; |
2c07245f | 7653 | |
9a7c7890 DV |
7654 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
7655 | *fp2 |= FP_CB_TUNE; | |
7656 | ||
5eddb70b | 7657 | dpll = 0; |
2c07245f | 7658 | |
a07d6787 EA |
7659 | if (is_lvds) |
7660 | dpll |= DPLLB_MODE_LVDS; | |
7661 | else | |
7662 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 7663 | |
190f68c5 | 7664 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7665 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f DV |
7666 | |
7667 | if (is_sdvo) | |
4a33e48d | 7668 | dpll |= DPLL_SDVO_HIGH_SPEED; |
190f68c5 | 7669 | if (crtc_state->has_dp_encoder) |
4a33e48d | 7670 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 7671 | |
a07d6787 | 7672 | /* compute bitmask from p1 value */ |
190f68c5 | 7673 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 7674 | /* also FPA1 */ |
190f68c5 | 7675 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 7676 | |
190f68c5 | 7677 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
7678 | case 5: |
7679 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7680 | break; | |
7681 | case 7: | |
7682 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7683 | break; | |
7684 | case 10: | |
7685 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7686 | break; | |
7687 | case 14: | |
7688 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7689 | break; | |
79e53945 JB |
7690 | } |
7691 | ||
b4c09f3b | 7692 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 7693 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
7694 | else |
7695 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7696 | ||
959e16d6 | 7697 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
7698 | } |
7699 | ||
190f68c5 ACO |
7700 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
7701 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 7702 | { |
c7653199 | 7703 | struct drm_device *dev = crtc->base.dev; |
de13a2e3 | 7704 | intel_clock_t clock, reduced_clock; |
cbbab5bd | 7705 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 7706 | bool ok, has_reduced_clock = false; |
8b47047b | 7707 | bool is_lvds = false; |
e2b78267 | 7708 | struct intel_shared_dpll *pll; |
de13a2e3 | 7709 | |
409ee761 | 7710 | is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS); |
79e53945 | 7711 | |
5dc5298b PZ |
7712 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
7713 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 7714 | |
190f68c5 | 7715 | ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock, |
de13a2e3 | 7716 | &has_reduced_clock, &reduced_clock); |
190f68c5 | 7717 | if (!ok && !crtc_state->clock_set) { |
de13a2e3 PZ |
7718 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
7719 | return -EINVAL; | |
79e53945 | 7720 | } |
f47709a9 | 7721 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
7722 | if (!crtc_state->clock_set) { |
7723 | crtc_state->dpll.n = clock.n; | |
7724 | crtc_state->dpll.m1 = clock.m1; | |
7725 | crtc_state->dpll.m2 = clock.m2; | |
7726 | crtc_state->dpll.p1 = clock.p1; | |
7727 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 7728 | } |
79e53945 | 7729 | |
5dc5298b | 7730 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
190f68c5 ACO |
7731 | if (crtc_state->has_pch_encoder) { |
7732 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); | |
cbbab5bd | 7733 | if (has_reduced_clock) |
7429e9d4 | 7734 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 7735 | |
190f68c5 | 7736 | dpll = ironlake_compute_dpll(crtc, crtc_state, |
cbbab5bd DV |
7737 | &fp, &reduced_clock, |
7738 | has_reduced_clock ? &fp2 : NULL); | |
7739 | ||
190f68c5 ACO |
7740 | crtc_state->dpll_hw_state.dpll = dpll; |
7741 | crtc_state->dpll_hw_state.fp0 = fp; | |
66e985c0 | 7742 | if (has_reduced_clock) |
190f68c5 | 7743 | crtc_state->dpll_hw_state.fp1 = fp2; |
66e985c0 | 7744 | else |
190f68c5 | 7745 | crtc_state->dpll_hw_state.fp1 = fp; |
66e985c0 | 7746 | |
190f68c5 | 7747 | pll = intel_get_shared_dpll(crtc, crtc_state); |
ee7b9f93 | 7748 | if (pll == NULL) { |
84f44ce7 | 7749 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
c7653199 | 7750 | pipe_name(crtc->pipe)); |
4b645f14 JB |
7751 | return -EINVAL; |
7752 | } | |
3fb37703 | 7753 | } |
79e53945 | 7754 | |
d330a953 | 7755 | if (is_lvds && has_reduced_clock && i915.powersave) |
c7653199 | 7756 | crtc->lowfreq_avail = true; |
bcd644e0 | 7757 | else |
c7653199 | 7758 | crtc->lowfreq_avail = false; |
e2b78267 | 7759 | |
c8f7a0db | 7760 | return 0; |
79e53945 JB |
7761 | } |
7762 | ||
eb14cb74 VS |
7763 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
7764 | struct intel_link_m_n *m_n) | |
7765 | { | |
7766 | struct drm_device *dev = crtc->base.dev; | |
7767 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7768 | enum pipe pipe = crtc->pipe; | |
7769 | ||
7770 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
7771 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
7772 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
7773 | & ~TU_SIZE_MASK; | |
7774 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
7775 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
7776 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7777 | } | |
7778 | ||
7779 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
7780 | enum transcoder transcoder, | |
b95af8be VK |
7781 | struct intel_link_m_n *m_n, |
7782 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
7783 | { |
7784 | struct drm_device *dev = crtc->base.dev; | |
7785 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 7786 | enum pipe pipe = crtc->pipe; |
72419203 | 7787 | |
eb14cb74 VS |
7788 | if (INTEL_INFO(dev)->gen >= 5) { |
7789 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
7790 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
7791 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
7792 | & ~TU_SIZE_MASK; | |
7793 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
7794 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
7795 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
7796 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
7797 | * gen < 8) and if DRRS is supported (to make sure the | |
7798 | * registers are not unnecessarily read). | |
7799 | */ | |
7800 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 7801 | crtc->config->has_drrs) { |
b95af8be VK |
7802 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
7803 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
7804 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
7805 | & ~TU_SIZE_MASK; | |
7806 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
7807 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
7808 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7809 | } | |
eb14cb74 VS |
7810 | } else { |
7811 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
7812 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
7813 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
7814 | & ~TU_SIZE_MASK; | |
7815 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
7816 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
7817 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7818 | } | |
7819 | } | |
7820 | ||
7821 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 7822 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 7823 | { |
681a8504 | 7824 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
7825 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
7826 | else | |
7827 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
7828 | &pipe_config->dp_m_n, |
7829 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 7830 | } |
72419203 | 7831 | |
eb14cb74 | 7832 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 7833 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
7834 | { |
7835 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 7836 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
7837 | } |
7838 | ||
bd2e244f | 7839 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 7840 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
7841 | { |
7842 | struct drm_device *dev = crtc->base.dev; | |
7843 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7844 | uint32_t tmp; | |
7845 | ||
7846 | tmp = I915_READ(PS_CTL(crtc->pipe)); | |
7847 | ||
7848 | if (tmp & PS_ENABLE) { | |
7849 | pipe_config->pch_pfit.enabled = true; | |
7850 | pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe)); | |
7851 | pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe)); | |
7852 | } | |
7853 | } | |
7854 | ||
5724dbd1 DL |
7855 | static void |
7856 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
7857 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
7858 | { |
7859 | struct drm_device *dev = crtc->base.dev; | |
7860 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40f46283 | 7861 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
7862 | int pipe = crtc->pipe; |
7863 | int fourcc, pixel_format; | |
6761dd31 | 7864 | unsigned int aligned_height; |
bc8d7dff | 7865 | struct drm_framebuffer *fb; |
1b842c89 | 7866 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 7867 | |
d9806c9f | 7868 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 7869 | if (!intel_fb) { |
bc8d7dff DL |
7870 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7871 | return; | |
7872 | } | |
7873 | ||
1b842c89 DL |
7874 | fb = &intel_fb->base; |
7875 | ||
bc8d7dff | 7876 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
7877 | if (!(val & PLANE_CTL_ENABLE)) |
7878 | goto error; | |
7879 | ||
bc8d7dff DL |
7880 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
7881 | fourcc = skl_format_to_fourcc(pixel_format, | |
7882 | val & PLANE_CTL_ORDER_RGBX, | |
7883 | val & PLANE_CTL_ALPHA_MASK); | |
7884 | fb->pixel_format = fourcc; | |
7885 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
7886 | ||
40f46283 DL |
7887 | tiling = val & PLANE_CTL_TILED_MASK; |
7888 | switch (tiling) { | |
7889 | case PLANE_CTL_TILED_LINEAR: | |
7890 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
7891 | break; | |
7892 | case PLANE_CTL_TILED_X: | |
7893 | plane_config->tiling = I915_TILING_X; | |
7894 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
7895 | break; | |
7896 | case PLANE_CTL_TILED_Y: | |
7897 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
7898 | break; | |
7899 | case PLANE_CTL_TILED_YF: | |
7900 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
7901 | break; | |
7902 | default: | |
7903 | MISSING_CASE(tiling); | |
7904 | goto error; | |
7905 | } | |
7906 | ||
bc8d7dff DL |
7907 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
7908 | plane_config->base = base; | |
7909 | ||
7910 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
7911 | ||
7912 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
7913 | fb->height = ((val >> 16) & 0xfff) + 1; | |
7914 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
7915 | ||
7916 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
40f46283 DL |
7917 | stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0], |
7918 | fb->pixel_format); | |
bc8d7dff DL |
7919 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
7920 | ||
7921 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
7922 | fb->pixel_format, |
7923 | fb->modifier[0]); | |
bc8d7dff | 7924 | |
f37b5c2b | 7925 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
7926 | |
7927 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
7928 | pipe_name(pipe), fb->width, fb->height, | |
7929 | fb->bits_per_pixel, base, fb->pitches[0], | |
7930 | plane_config->size); | |
7931 | ||
2d14030b | 7932 | plane_config->fb = intel_fb; |
bc8d7dff DL |
7933 | return; |
7934 | ||
7935 | error: | |
7936 | kfree(fb); | |
7937 | } | |
7938 | ||
2fa2fe9a | 7939 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 7940 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
7941 | { |
7942 | struct drm_device *dev = crtc->base.dev; | |
7943 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7944 | uint32_t tmp; | |
7945 | ||
7946 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
7947 | ||
7948 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 7949 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
7950 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
7951 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
7952 | |
7953 | /* We currently do not free assignements of panel fitters on | |
7954 | * ivb/hsw (since we don't use the higher upscaling modes which | |
7955 | * differentiates them) so just WARN about this case for now. */ | |
7956 | if (IS_GEN7(dev)) { | |
7957 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
7958 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
7959 | } | |
2fa2fe9a | 7960 | } |
79e53945 JB |
7961 | } |
7962 | ||
5724dbd1 DL |
7963 | static void |
7964 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
7965 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
7966 | { |
7967 | struct drm_device *dev = crtc->base.dev; | |
7968 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7969 | u32 val, base, offset; | |
aeee5a49 | 7970 | int pipe = crtc->pipe; |
4c6baa59 | 7971 | int fourcc, pixel_format; |
6761dd31 | 7972 | unsigned int aligned_height; |
b113d5ee | 7973 | struct drm_framebuffer *fb; |
1b842c89 | 7974 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 7975 | |
42a7b088 DL |
7976 | val = I915_READ(DSPCNTR(pipe)); |
7977 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
7978 | return; | |
7979 | ||
d9806c9f | 7980 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 7981 | if (!intel_fb) { |
4c6baa59 JB |
7982 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7983 | return; | |
7984 | } | |
7985 | ||
1b842c89 DL |
7986 | fb = &intel_fb->base; |
7987 | ||
18c5247e DV |
7988 | if (INTEL_INFO(dev)->gen >= 4) { |
7989 | if (val & DISPPLANE_TILED) { | |
49af449b | 7990 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
7991 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
7992 | } | |
7993 | } | |
4c6baa59 JB |
7994 | |
7995 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 7996 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
7997 | fb->pixel_format = fourcc; |
7998 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 7999 | |
aeee5a49 | 8000 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 8001 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 8002 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 8003 | } else { |
49af449b | 8004 | if (plane_config->tiling) |
aeee5a49 | 8005 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 8006 | else |
aeee5a49 | 8007 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
8008 | } |
8009 | plane_config->base = base; | |
8010 | ||
8011 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8012 | fb->width = ((val >> 16) & 0xfff) + 1; |
8013 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
8014 | |
8015 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8016 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 8017 | |
b113d5ee | 8018 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
8019 | fb->pixel_format, |
8020 | fb->modifier[0]); | |
4c6baa59 | 8021 | |
f37b5c2b | 8022 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 8023 | |
2844a921 DL |
8024 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8025 | pipe_name(pipe), fb->width, fb->height, | |
8026 | fb->bits_per_pixel, base, fb->pitches[0], | |
8027 | plane_config->size); | |
b113d5ee | 8028 | |
2d14030b | 8029 | plane_config->fb = intel_fb; |
4c6baa59 JB |
8030 | } |
8031 | ||
0e8ffe1b | 8032 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8033 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8034 | { |
8035 | struct drm_device *dev = crtc->base.dev; | |
8036 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8037 | uint32_t tmp; | |
8038 | ||
f458ebbc DV |
8039 | if (!intel_display_power_is_enabled(dev_priv, |
8040 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
930e8c9e PZ |
8041 | return false; |
8042 | ||
e143a21c | 8043 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 8044 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 8045 | |
0e8ffe1b DV |
8046 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8047 | if (!(tmp & PIPECONF_ENABLE)) | |
8048 | return false; | |
8049 | ||
42571aef VS |
8050 | switch (tmp & PIPECONF_BPC_MASK) { |
8051 | case PIPECONF_6BPC: | |
8052 | pipe_config->pipe_bpp = 18; | |
8053 | break; | |
8054 | case PIPECONF_8BPC: | |
8055 | pipe_config->pipe_bpp = 24; | |
8056 | break; | |
8057 | case PIPECONF_10BPC: | |
8058 | pipe_config->pipe_bpp = 30; | |
8059 | break; | |
8060 | case PIPECONF_12BPC: | |
8061 | pipe_config->pipe_bpp = 36; | |
8062 | break; | |
8063 | default: | |
8064 | break; | |
8065 | } | |
8066 | ||
b5a9fa09 DV |
8067 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
8068 | pipe_config->limited_color_range = true; | |
8069 | ||
ab9412ba | 8070 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
8071 | struct intel_shared_dpll *pll; |
8072 | ||
88adfff1 DV |
8073 | pipe_config->has_pch_encoder = true; |
8074 | ||
627eb5a3 DV |
8075 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
8076 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
8077 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
8078 | |
8079 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 8080 | |
c0d43d62 | 8081 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
8082 | pipe_config->shared_dpll = |
8083 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
8084 | } else { |
8085 | tmp = I915_READ(PCH_DPLL_SEL); | |
8086 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
8087 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
8088 | else | |
8089 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
8090 | } | |
66e985c0 DV |
8091 | |
8092 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
8093 | ||
8094 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
8095 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
8096 | |
8097 | tmp = pipe_config->dpll_hw_state.dpll; | |
8098 | pipe_config->pixel_multiplier = | |
8099 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
8100 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
8101 | |
8102 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
8103 | } else { |
8104 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
8105 | } |
8106 | ||
1bd1bd80 DV |
8107 | intel_get_pipe_timings(crtc, pipe_config); |
8108 | ||
2fa2fe9a DV |
8109 | ironlake_get_pfit_config(crtc, pipe_config); |
8110 | ||
0e8ffe1b DV |
8111 | return true; |
8112 | } | |
8113 | ||
be256dc7 PZ |
8114 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
8115 | { | |
8116 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 8117 | struct intel_crtc *crtc; |
be256dc7 | 8118 | |
d3fcc808 | 8119 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 8120 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
8121 | pipe_name(crtc->pipe)); |
8122 | ||
e2c719b7 RC |
8123 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
8124 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
8125 | I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); | |
8126 | I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
8127 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); | |
8128 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
be256dc7 | 8129 | "CPU PWM1 enabled\n"); |
c5107b87 | 8130 | if (IS_HASWELL(dev)) |
e2c719b7 | 8131 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 8132 | "CPU PWM2 enabled\n"); |
e2c719b7 | 8133 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 8134 | "PCH PWM1 enabled\n"); |
e2c719b7 | 8135 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 8136 | "Utility pin enabled\n"); |
e2c719b7 | 8137 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 8138 | |
9926ada1 PZ |
8139 | /* |
8140 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
8141 | * interrupts remain enabled. We used to check for that, but since it's | |
8142 | * gen-specific and since we only disable LCPLL after we fully disable | |
8143 | * the interrupts, the check below should be enough. | |
8144 | */ | |
e2c719b7 | 8145 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
8146 | } |
8147 | ||
9ccd5aeb PZ |
8148 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
8149 | { | |
8150 | struct drm_device *dev = dev_priv->dev; | |
8151 | ||
8152 | if (IS_HASWELL(dev)) | |
8153 | return I915_READ(D_COMP_HSW); | |
8154 | else | |
8155 | return I915_READ(D_COMP_BDW); | |
8156 | } | |
8157 | ||
3c4c9b81 PZ |
8158 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
8159 | { | |
8160 | struct drm_device *dev = dev_priv->dev; | |
8161 | ||
8162 | if (IS_HASWELL(dev)) { | |
8163 | mutex_lock(&dev_priv->rps.hw_lock); | |
8164 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
8165 | val)) | |
f475dadf | 8166 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
8167 | mutex_unlock(&dev_priv->rps.hw_lock); |
8168 | } else { | |
9ccd5aeb PZ |
8169 | I915_WRITE(D_COMP_BDW, val); |
8170 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 8171 | } |
be256dc7 PZ |
8172 | } |
8173 | ||
8174 | /* | |
8175 | * This function implements pieces of two sequences from BSpec: | |
8176 | * - Sequence for display software to disable LCPLL | |
8177 | * - Sequence for display software to allow package C8+ | |
8178 | * The steps implemented here are just the steps that actually touch the LCPLL | |
8179 | * register. Callers should take care of disabling all the display engine | |
8180 | * functions, doing the mode unset, fixing interrupts, etc. | |
8181 | */ | |
6ff58d53 PZ |
8182 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
8183 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
8184 | { |
8185 | uint32_t val; | |
8186 | ||
8187 | assert_can_disable_lcpll(dev_priv); | |
8188 | ||
8189 | val = I915_READ(LCPLL_CTL); | |
8190 | ||
8191 | if (switch_to_fclk) { | |
8192 | val |= LCPLL_CD_SOURCE_FCLK; | |
8193 | I915_WRITE(LCPLL_CTL, val); | |
8194 | ||
8195 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
8196 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
8197 | DRM_ERROR("Switching to FCLK failed\n"); | |
8198 | ||
8199 | val = I915_READ(LCPLL_CTL); | |
8200 | } | |
8201 | ||
8202 | val |= LCPLL_PLL_DISABLE; | |
8203 | I915_WRITE(LCPLL_CTL, val); | |
8204 | POSTING_READ(LCPLL_CTL); | |
8205 | ||
8206 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
8207 | DRM_ERROR("LCPLL still locked\n"); | |
8208 | ||
9ccd5aeb | 8209 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 8210 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 8211 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
8212 | ndelay(100); |
8213 | ||
9ccd5aeb PZ |
8214 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
8215 | 1)) | |
be256dc7 PZ |
8216 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
8217 | ||
8218 | if (allow_power_down) { | |
8219 | val = I915_READ(LCPLL_CTL); | |
8220 | val |= LCPLL_POWER_DOWN_ALLOW; | |
8221 | I915_WRITE(LCPLL_CTL, val); | |
8222 | POSTING_READ(LCPLL_CTL); | |
8223 | } | |
8224 | } | |
8225 | ||
8226 | /* | |
8227 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
8228 | * source. | |
8229 | */ | |
6ff58d53 | 8230 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
8231 | { |
8232 | uint32_t val; | |
8233 | ||
8234 | val = I915_READ(LCPLL_CTL); | |
8235 | ||
8236 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
8237 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
8238 | return; | |
8239 | ||
a8a8bd54 PZ |
8240 | /* |
8241 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
8242 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 8243 | */ |
59bad947 | 8244 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 8245 | |
be256dc7 PZ |
8246 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
8247 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
8248 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 8249 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
8250 | } |
8251 | ||
9ccd5aeb | 8252 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
8253 | val |= D_COMP_COMP_FORCE; |
8254 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 8255 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
8256 | |
8257 | val = I915_READ(LCPLL_CTL); | |
8258 | val &= ~LCPLL_PLL_DISABLE; | |
8259 | I915_WRITE(LCPLL_CTL, val); | |
8260 | ||
8261 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
8262 | DRM_ERROR("LCPLL not locked yet\n"); | |
8263 | ||
8264 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
8265 | val = I915_READ(LCPLL_CTL); | |
8266 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
8267 | I915_WRITE(LCPLL_CTL, val); | |
8268 | ||
8269 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
8270 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
8271 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
8272 | } | |
215733fa | 8273 | |
59bad947 | 8274 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
be256dc7 PZ |
8275 | } |
8276 | ||
765dab67 PZ |
8277 | /* |
8278 | * Package states C8 and deeper are really deep PC states that can only be | |
8279 | * reached when all the devices on the system allow it, so even if the graphics | |
8280 | * device allows PC8+, it doesn't mean the system will actually get to these | |
8281 | * states. Our driver only allows PC8+ when going into runtime PM. | |
8282 | * | |
8283 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
8284 | * well is disabled and most interrupts are disabled, and these are also | |
8285 | * requirements for runtime PM. When these conditions are met, we manually do | |
8286 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
8287 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
8288 | * hang the machine. | |
8289 | * | |
8290 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
8291 | * the state of some registers, so when we come back from PC8+ we need to | |
8292 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
8293 | * need to take care of the registers kept by RC6. Notice that this happens even | |
8294 | * if we don't put the device in PCI D3 state (which is what currently happens | |
8295 | * because of the runtime PM support). | |
8296 | * | |
8297 | * For more, read "Display Sequences for Package C8" on the hardware | |
8298 | * documentation. | |
8299 | */ | |
a14cb6fc | 8300 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 8301 | { |
c67a470b PZ |
8302 | struct drm_device *dev = dev_priv->dev; |
8303 | uint32_t val; | |
8304 | ||
c67a470b PZ |
8305 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
8306 | ||
c67a470b PZ |
8307 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
8308 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
8309 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
8310 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
8311 | } | |
8312 | ||
8313 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
8314 | hsw_disable_lcpll(dev_priv, true, true); |
8315 | } | |
8316 | ||
a14cb6fc | 8317 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
8318 | { |
8319 | struct drm_device *dev = dev_priv->dev; | |
8320 | uint32_t val; | |
8321 | ||
c67a470b PZ |
8322 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
8323 | ||
8324 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
8325 | lpt_init_pch_refclk(dev); |
8326 | ||
8327 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
8328 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
8329 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
8330 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
8331 | } | |
8332 | ||
8333 | intel_prepare_ddi(dev); | |
c67a470b PZ |
8334 | } |
8335 | ||
190f68c5 ACO |
8336 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
8337 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 8338 | { |
190f68c5 | 8339 | if (!intel_ddi_pll_select(crtc, crtc_state)) |
6441ab5f | 8340 | return -EINVAL; |
716c2e55 | 8341 | |
c7653199 | 8342 | crtc->lowfreq_avail = false; |
644cef34 | 8343 | |
c8f7a0db | 8344 | return 0; |
79e53945 JB |
8345 | } |
8346 | ||
96b7dfb7 S |
8347 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
8348 | enum port port, | |
5cec258b | 8349 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 8350 | { |
3148ade7 | 8351 | u32 temp, dpll_ctl1; |
96b7dfb7 S |
8352 | |
8353 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
8354 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
8355 | ||
8356 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 DL |
8357 | case SKL_DPLL0: |
8358 | /* | |
8359 | * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part | |
8360 | * of the shared DPLL framework and thus needs to be read out | |
8361 | * separately | |
8362 | */ | |
8363 | dpll_ctl1 = I915_READ(DPLL_CTRL1); | |
8364 | pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f; | |
8365 | break; | |
96b7dfb7 S |
8366 | case SKL_DPLL1: |
8367 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
8368 | break; | |
8369 | case SKL_DPLL2: | |
8370 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
8371 | break; | |
8372 | case SKL_DPLL3: | |
8373 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
8374 | break; | |
96b7dfb7 S |
8375 | } |
8376 | } | |
8377 | ||
7d2c8175 DL |
8378 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
8379 | enum port port, | |
5cec258b | 8380 | struct intel_crtc_state *pipe_config) |
7d2c8175 DL |
8381 | { |
8382 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); | |
8383 | ||
8384 | switch (pipe_config->ddi_pll_sel) { | |
8385 | case PORT_CLK_SEL_WRPLL1: | |
8386 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; | |
8387 | break; | |
8388 | case PORT_CLK_SEL_WRPLL2: | |
8389 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; | |
8390 | break; | |
8391 | } | |
8392 | } | |
8393 | ||
26804afd | 8394 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 8395 | struct intel_crtc_state *pipe_config) |
26804afd DV |
8396 | { |
8397 | struct drm_device *dev = crtc->base.dev; | |
8398 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 8399 | struct intel_shared_dpll *pll; |
26804afd DV |
8400 | enum port port; |
8401 | uint32_t tmp; | |
8402 | ||
8403 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
8404 | ||
8405 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
8406 | ||
96b7dfb7 S |
8407 | if (IS_SKYLAKE(dev)) |
8408 | skylake_get_ddi_pll(dev_priv, port, pipe_config); | |
8409 | else | |
8410 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 8411 | |
d452c5b6 DV |
8412 | if (pipe_config->shared_dpll >= 0) { |
8413 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
8414 | ||
8415 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
8416 | &pipe_config->dpll_hw_state)); | |
8417 | } | |
8418 | ||
26804afd DV |
8419 | /* |
8420 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
8421 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
8422 | * the PCH transcoder is on. | |
8423 | */ | |
ca370455 DL |
8424 | if (INTEL_INFO(dev)->gen < 9 && |
8425 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
8426 | pipe_config->has_pch_encoder = true; |
8427 | ||
8428 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
8429 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
8430 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
8431 | ||
8432 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
8433 | } | |
8434 | } | |
8435 | ||
0e8ffe1b | 8436 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8437 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8438 | { |
8439 | struct drm_device *dev = crtc->base.dev; | |
8440 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 8441 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
8442 | uint32_t tmp; |
8443 | ||
f458ebbc | 8444 | if (!intel_display_power_is_enabled(dev_priv, |
b5482bd0 ID |
8445 | POWER_DOMAIN_PIPE(crtc->pipe))) |
8446 | return false; | |
8447 | ||
e143a21c | 8448 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
8449 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
8450 | ||
eccb140b DV |
8451 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
8452 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
8453 | enum pipe trans_edp_pipe; | |
8454 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
8455 | default: | |
8456 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
8457 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
8458 | case TRANS_DDI_EDP_INPUT_A_ON: | |
8459 | trans_edp_pipe = PIPE_A; | |
8460 | break; | |
8461 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
8462 | trans_edp_pipe = PIPE_B; | |
8463 | break; | |
8464 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
8465 | trans_edp_pipe = PIPE_C; | |
8466 | break; | |
8467 | } | |
8468 | ||
8469 | if (trans_edp_pipe == crtc->pipe) | |
8470 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
8471 | } | |
8472 | ||
f458ebbc | 8473 | if (!intel_display_power_is_enabled(dev_priv, |
eccb140b | 8474 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
8475 | return false; |
8476 | ||
eccb140b | 8477 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
8478 | if (!(tmp & PIPECONF_ENABLE)) |
8479 | return false; | |
8480 | ||
26804afd | 8481 | haswell_get_ddi_port_state(crtc, pipe_config); |
627eb5a3 | 8482 | |
1bd1bd80 DV |
8483 | intel_get_pipe_timings(crtc, pipe_config); |
8484 | ||
2fa2fe9a | 8485 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
bd2e244f JB |
8486 | if (intel_display_power_is_enabled(dev_priv, pfit_domain)) { |
8487 | if (IS_SKYLAKE(dev)) | |
8488 | skylake_get_pfit_config(crtc, pipe_config); | |
8489 | else | |
8490 | ironlake_get_pfit_config(crtc, pipe_config); | |
8491 | } | |
88adfff1 | 8492 | |
e59150dc JB |
8493 | if (IS_HASWELL(dev)) |
8494 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
8495 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 8496 | |
ebb69c95 CT |
8497 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP) { |
8498 | pipe_config->pixel_multiplier = | |
8499 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
8500 | } else { | |
8501 | pipe_config->pixel_multiplier = 1; | |
8502 | } | |
6c49f241 | 8503 | |
0e8ffe1b DV |
8504 | return true; |
8505 | } | |
8506 | ||
560b85bb CW |
8507 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
8508 | { | |
8509 | struct drm_device *dev = crtc->dev; | |
8510 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8511 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 8512 | uint32_t cntl = 0, size = 0; |
560b85bb | 8513 | |
dc41c154 | 8514 | if (base) { |
3dd512fb MR |
8515 | unsigned int width = intel_crtc->base.cursor->state->crtc_w; |
8516 | unsigned int height = intel_crtc->base.cursor->state->crtc_h; | |
dc41c154 VS |
8517 | unsigned int stride = roundup_pow_of_two(width) * 4; |
8518 | ||
8519 | switch (stride) { | |
8520 | default: | |
8521 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
8522 | width, stride); | |
8523 | stride = 256; | |
8524 | /* fallthrough */ | |
8525 | case 256: | |
8526 | case 512: | |
8527 | case 1024: | |
8528 | case 2048: | |
8529 | break; | |
4b0e333e CW |
8530 | } |
8531 | ||
dc41c154 VS |
8532 | cntl |= CURSOR_ENABLE | |
8533 | CURSOR_GAMMA_ENABLE | | |
8534 | CURSOR_FORMAT_ARGB | | |
8535 | CURSOR_STRIDE(stride); | |
8536 | ||
8537 | size = (height << 12) | width; | |
4b0e333e | 8538 | } |
560b85bb | 8539 | |
dc41c154 VS |
8540 | if (intel_crtc->cursor_cntl != 0 && |
8541 | (intel_crtc->cursor_base != base || | |
8542 | intel_crtc->cursor_size != size || | |
8543 | intel_crtc->cursor_cntl != cntl)) { | |
8544 | /* On these chipsets we can only modify the base/size/stride | |
8545 | * whilst the cursor is disabled. | |
8546 | */ | |
8547 | I915_WRITE(_CURACNTR, 0); | |
4b0e333e | 8548 | POSTING_READ(_CURACNTR); |
dc41c154 | 8549 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 8550 | } |
560b85bb | 8551 | |
99d1f387 | 8552 | if (intel_crtc->cursor_base != base) { |
9db4a9c7 | 8553 | I915_WRITE(_CURABASE, base); |
99d1f387 VS |
8554 | intel_crtc->cursor_base = base; |
8555 | } | |
4726e0b0 | 8556 | |
dc41c154 VS |
8557 | if (intel_crtc->cursor_size != size) { |
8558 | I915_WRITE(CURSIZE, size); | |
8559 | intel_crtc->cursor_size = size; | |
4b0e333e | 8560 | } |
560b85bb | 8561 | |
4b0e333e | 8562 | if (intel_crtc->cursor_cntl != cntl) { |
4b0e333e CW |
8563 | I915_WRITE(_CURACNTR, cntl); |
8564 | POSTING_READ(_CURACNTR); | |
4b0e333e | 8565 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 8566 | } |
560b85bb CW |
8567 | } |
8568 | ||
560b85bb | 8569 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
65a21cd6 JB |
8570 | { |
8571 | struct drm_device *dev = crtc->dev; | |
8572 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8573 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8574 | int pipe = intel_crtc->pipe; | |
4b0e333e CW |
8575 | uint32_t cntl; |
8576 | ||
8577 | cntl = 0; | |
8578 | if (base) { | |
8579 | cntl = MCURSOR_GAMMA_ENABLE; | |
3dd512fb | 8580 | switch (intel_crtc->base.cursor->state->crtc_w) { |
4726e0b0 SK |
8581 | case 64: |
8582 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
8583 | break; | |
8584 | case 128: | |
8585 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
8586 | break; | |
8587 | case 256: | |
8588 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
8589 | break; | |
8590 | default: | |
3dd512fb | 8591 | MISSING_CASE(intel_crtc->base.cursor->state->crtc_w); |
4726e0b0 | 8592 | return; |
65a21cd6 | 8593 | } |
4b0e333e | 8594 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 VS |
8595 | |
8596 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
8597 | cntl |= CURSOR_PIPE_CSC_ENABLE; | |
4b0e333e | 8598 | } |
65a21cd6 | 8599 | |
8e7d688b | 8600 | if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) |
4398ad45 VS |
8601 | cntl |= CURSOR_ROTATE_180; |
8602 | ||
4b0e333e CW |
8603 | if (intel_crtc->cursor_cntl != cntl) { |
8604 | I915_WRITE(CURCNTR(pipe), cntl); | |
8605 | POSTING_READ(CURCNTR(pipe)); | |
8606 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 8607 | } |
4b0e333e | 8608 | |
65a21cd6 | 8609 | /* and commit changes on next vblank */ |
5efb3e28 VS |
8610 | I915_WRITE(CURBASE(pipe), base); |
8611 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
8612 | |
8613 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
8614 | } |
8615 | ||
cda4b7d3 | 8616 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
8617 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
8618 | bool on) | |
cda4b7d3 CW |
8619 | { |
8620 | struct drm_device *dev = crtc->dev; | |
8621 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8622 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8623 | int pipe = intel_crtc->pipe; | |
3d7d6510 MR |
8624 | int x = crtc->cursor_x; |
8625 | int y = crtc->cursor_y; | |
d6e4db15 | 8626 | u32 base = 0, pos = 0; |
cda4b7d3 | 8627 | |
d6e4db15 | 8628 | if (on) |
cda4b7d3 | 8629 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 8630 | |
6e3c9717 | 8631 | if (x >= intel_crtc->config->pipe_src_w) |
d6e4db15 VS |
8632 | base = 0; |
8633 | ||
6e3c9717 | 8634 | if (y >= intel_crtc->config->pipe_src_h) |
cda4b7d3 CW |
8635 | base = 0; |
8636 | ||
8637 | if (x < 0) { | |
3dd512fb | 8638 | if (x + intel_crtc->base.cursor->state->crtc_w <= 0) |
cda4b7d3 CW |
8639 | base = 0; |
8640 | ||
8641 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
8642 | x = -x; | |
8643 | } | |
8644 | pos |= x << CURSOR_X_SHIFT; | |
8645 | ||
8646 | if (y < 0) { | |
3dd512fb | 8647 | if (y + intel_crtc->base.cursor->state->crtc_h <= 0) |
cda4b7d3 CW |
8648 | base = 0; |
8649 | ||
8650 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
8651 | y = -y; | |
8652 | } | |
8653 | pos |= y << CURSOR_Y_SHIFT; | |
8654 | ||
4b0e333e | 8655 | if (base == 0 && intel_crtc->cursor_base == 0) |
cda4b7d3 CW |
8656 | return; |
8657 | ||
5efb3e28 VS |
8658 | I915_WRITE(CURPOS(pipe), pos); |
8659 | ||
4398ad45 VS |
8660 | /* ILK+ do this automagically */ |
8661 | if (HAS_GMCH_DISPLAY(dev) && | |
8e7d688b | 8662 | crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) { |
3dd512fb MR |
8663 | base += (intel_crtc->base.cursor->state->crtc_h * |
8664 | intel_crtc->base.cursor->state->crtc_w - 1) * 4; | |
4398ad45 VS |
8665 | } |
8666 | ||
8ac54669 | 8667 | if (IS_845G(dev) || IS_I865G(dev)) |
5efb3e28 VS |
8668 | i845_update_cursor(crtc, base); |
8669 | else | |
8670 | i9xx_update_cursor(crtc, base); | |
cda4b7d3 CW |
8671 | } |
8672 | ||
dc41c154 VS |
8673 | static bool cursor_size_ok(struct drm_device *dev, |
8674 | uint32_t width, uint32_t height) | |
8675 | { | |
8676 | if (width == 0 || height == 0) | |
8677 | return false; | |
8678 | ||
8679 | /* | |
8680 | * 845g/865g are special in that they are only limited by | |
8681 | * the width of their cursors, the height is arbitrary up to | |
8682 | * the precision of the register. Everything else requires | |
8683 | * square cursors, limited to a few power-of-two sizes. | |
8684 | */ | |
8685 | if (IS_845G(dev) || IS_I865G(dev)) { | |
8686 | if ((width & 63) != 0) | |
8687 | return false; | |
8688 | ||
8689 | if (width > (IS_845G(dev) ? 64 : 512)) | |
8690 | return false; | |
8691 | ||
8692 | if (height > 1023) | |
8693 | return false; | |
8694 | } else { | |
8695 | switch (width | height) { | |
8696 | case 256: | |
8697 | case 128: | |
8698 | if (IS_GEN2(dev)) | |
8699 | return false; | |
8700 | case 64: | |
8701 | break; | |
8702 | default: | |
8703 | return false; | |
8704 | } | |
8705 | } | |
8706 | ||
8707 | return true; | |
8708 | } | |
8709 | ||
79e53945 | 8710 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 8711 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 8712 | { |
7203425a | 8713 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 8714 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 8715 | |
7203425a | 8716 | for (i = start; i < end; i++) { |
79e53945 JB |
8717 | intel_crtc->lut_r[i] = red[i] >> 8; |
8718 | intel_crtc->lut_g[i] = green[i] >> 8; | |
8719 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
8720 | } | |
8721 | ||
8722 | intel_crtc_load_lut(crtc); | |
8723 | } | |
8724 | ||
79e53945 JB |
8725 | /* VESA 640x480x72Hz mode to set on the pipe */ |
8726 | static struct drm_display_mode load_detect_mode = { | |
8727 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
8728 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
8729 | }; | |
8730 | ||
a8bb6818 DV |
8731 | struct drm_framebuffer * |
8732 | __intel_framebuffer_create(struct drm_device *dev, | |
8733 | struct drm_mode_fb_cmd2 *mode_cmd, | |
8734 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
8735 | { |
8736 | struct intel_framebuffer *intel_fb; | |
8737 | int ret; | |
8738 | ||
8739 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
8740 | if (!intel_fb) { | |
6ccb81f2 | 8741 | drm_gem_object_unreference(&obj->base); |
d2dff872 CW |
8742 | return ERR_PTR(-ENOMEM); |
8743 | } | |
8744 | ||
8745 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
8746 | if (ret) |
8747 | goto err; | |
d2dff872 CW |
8748 | |
8749 | return &intel_fb->base; | |
dd4916c5 | 8750 | err: |
6ccb81f2 | 8751 | drm_gem_object_unreference(&obj->base); |
dd4916c5 DV |
8752 | kfree(intel_fb); |
8753 | ||
8754 | return ERR_PTR(ret); | |
d2dff872 CW |
8755 | } |
8756 | ||
b5ea642a | 8757 | static struct drm_framebuffer * |
a8bb6818 DV |
8758 | intel_framebuffer_create(struct drm_device *dev, |
8759 | struct drm_mode_fb_cmd2 *mode_cmd, | |
8760 | struct drm_i915_gem_object *obj) | |
8761 | { | |
8762 | struct drm_framebuffer *fb; | |
8763 | int ret; | |
8764 | ||
8765 | ret = i915_mutex_lock_interruptible(dev); | |
8766 | if (ret) | |
8767 | return ERR_PTR(ret); | |
8768 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
8769 | mutex_unlock(&dev->struct_mutex); | |
8770 | ||
8771 | return fb; | |
8772 | } | |
8773 | ||
d2dff872 CW |
8774 | static u32 |
8775 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
8776 | { | |
8777 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
8778 | return ALIGN(pitch, 64); | |
8779 | } | |
8780 | ||
8781 | static u32 | |
8782 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
8783 | { | |
8784 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 8785 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
8786 | } |
8787 | ||
8788 | static struct drm_framebuffer * | |
8789 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
8790 | struct drm_display_mode *mode, | |
8791 | int depth, int bpp) | |
8792 | { | |
8793 | struct drm_i915_gem_object *obj; | |
0fed39bd | 8794 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
8795 | |
8796 | obj = i915_gem_alloc_object(dev, | |
8797 | intel_framebuffer_size_for_mode(mode, bpp)); | |
8798 | if (obj == NULL) | |
8799 | return ERR_PTR(-ENOMEM); | |
8800 | ||
8801 | mode_cmd.width = mode->hdisplay; | |
8802 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
8803 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
8804 | bpp); | |
5ca0c34a | 8805 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
8806 | |
8807 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
8808 | } | |
8809 | ||
8810 | static struct drm_framebuffer * | |
8811 | mode_fits_in_fbdev(struct drm_device *dev, | |
8812 | struct drm_display_mode *mode) | |
8813 | { | |
4520f53a | 8814 | #ifdef CONFIG_DRM_I915_FBDEV |
d2dff872 CW |
8815 | struct drm_i915_private *dev_priv = dev->dev_private; |
8816 | struct drm_i915_gem_object *obj; | |
8817 | struct drm_framebuffer *fb; | |
8818 | ||
4c0e5528 | 8819 | if (!dev_priv->fbdev) |
d2dff872 CW |
8820 | return NULL; |
8821 | ||
4c0e5528 | 8822 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
8823 | return NULL; |
8824 | ||
4c0e5528 DV |
8825 | obj = dev_priv->fbdev->fb->obj; |
8826 | BUG_ON(!obj); | |
8827 | ||
8bcd4553 | 8828 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
8829 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
8830 | fb->bits_per_pixel)) | |
d2dff872 CW |
8831 | return NULL; |
8832 | ||
01f2c773 | 8833 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
8834 | return NULL; |
8835 | ||
8836 | return fb; | |
4520f53a DV |
8837 | #else |
8838 | return NULL; | |
8839 | #endif | |
d2dff872 CW |
8840 | } |
8841 | ||
d2434ab7 | 8842 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 8843 | struct drm_display_mode *mode, |
51fd371b RC |
8844 | struct intel_load_detect_pipe *old, |
8845 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
8846 | { |
8847 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
8848 | struct intel_encoder *intel_encoder = |
8849 | intel_attached_encoder(connector); | |
79e53945 | 8850 | struct drm_crtc *possible_crtc; |
4ef69c7a | 8851 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
8852 | struct drm_crtc *crtc = NULL; |
8853 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 8854 | struct drm_framebuffer *fb; |
51fd371b RC |
8855 | struct drm_mode_config *config = &dev->mode_config; |
8856 | int ret, i = -1; | |
79e53945 | 8857 | |
d2dff872 | 8858 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 8859 | connector->base.id, connector->name, |
8e329a03 | 8860 | encoder->base.id, encoder->name); |
d2dff872 | 8861 | |
51fd371b RC |
8862 | retry: |
8863 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
8864 | if (ret) | |
8865 | goto fail_unlock; | |
6e9f798d | 8866 | |
79e53945 JB |
8867 | /* |
8868 | * Algorithm gets a little messy: | |
7a5e4805 | 8869 | * |
79e53945 JB |
8870 | * - if the connector already has an assigned crtc, use it (but make |
8871 | * sure it's on first) | |
7a5e4805 | 8872 | * |
79e53945 JB |
8873 | * - try to find the first unused crtc that can drive this connector, |
8874 | * and use that if we find one | |
79e53945 JB |
8875 | */ |
8876 | ||
8877 | /* See if we already have a CRTC for this connector */ | |
8878 | if (encoder->crtc) { | |
8879 | crtc = encoder->crtc; | |
8261b191 | 8880 | |
51fd371b | 8881 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de DV |
8882 | if (ret) |
8883 | goto fail_unlock; | |
8884 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); | |
51fd371b RC |
8885 | if (ret) |
8886 | goto fail_unlock; | |
7b24056b | 8887 | |
24218aac | 8888 | old->dpms_mode = connector->dpms; |
8261b191 CW |
8889 | old->load_detect_temp = false; |
8890 | ||
8891 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
8892 | if (connector->dpms != DRM_MODE_DPMS_ON) |
8893 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 8894 | |
7173188d | 8895 | return true; |
79e53945 JB |
8896 | } |
8897 | ||
8898 | /* Find an unused one (if possible) */ | |
70e1e0ec | 8899 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
8900 | i++; |
8901 | if (!(encoder->possible_crtcs & (1 << i))) | |
8902 | continue; | |
83d65738 | 8903 | if (possible_crtc->state->enable) |
a459249c VS |
8904 | continue; |
8905 | /* This can occur when applying the pipe A quirk on resume. */ | |
8906 | if (to_intel_crtc(possible_crtc)->new_enabled) | |
8907 | continue; | |
8908 | ||
8909 | crtc = possible_crtc; | |
8910 | break; | |
79e53945 JB |
8911 | } |
8912 | ||
8913 | /* | |
8914 | * If we didn't find an unused CRTC, don't use any. | |
8915 | */ | |
8916 | if (!crtc) { | |
7173188d | 8917 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
51fd371b | 8918 | goto fail_unlock; |
79e53945 JB |
8919 | } |
8920 | ||
51fd371b RC |
8921 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
8922 | if (ret) | |
4d02e2de DV |
8923 | goto fail_unlock; |
8924 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); | |
8925 | if (ret) | |
51fd371b | 8926 | goto fail_unlock; |
fc303101 DV |
8927 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
8928 | to_intel_connector(connector)->new_encoder = intel_encoder; | |
79e53945 JB |
8929 | |
8930 | intel_crtc = to_intel_crtc(crtc); | |
412b61d8 | 8931 | intel_crtc->new_enabled = true; |
6e3c9717 | 8932 | intel_crtc->new_config = intel_crtc->config; |
24218aac | 8933 | old->dpms_mode = connector->dpms; |
8261b191 | 8934 | old->load_detect_temp = true; |
d2dff872 | 8935 | old->release_fb = NULL; |
79e53945 | 8936 | |
6492711d CW |
8937 | if (!mode) |
8938 | mode = &load_detect_mode; | |
79e53945 | 8939 | |
d2dff872 CW |
8940 | /* We need a framebuffer large enough to accommodate all accesses |
8941 | * that the plane may generate whilst we perform load detection. | |
8942 | * We can not rely on the fbcon either being present (we get called | |
8943 | * during its initialisation to detect all boot displays, or it may | |
8944 | * not even exist) or that it is large enough to satisfy the | |
8945 | * requested mode. | |
8946 | */ | |
94352cf9 DV |
8947 | fb = mode_fits_in_fbdev(dev, mode); |
8948 | if (fb == NULL) { | |
d2dff872 | 8949 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
8950 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
8951 | old->release_fb = fb; | |
d2dff872 CW |
8952 | } else |
8953 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 8954 | if (IS_ERR(fb)) { |
d2dff872 | 8955 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 8956 | goto fail; |
79e53945 | 8957 | } |
79e53945 | 8958 | |
c0c36b94 | 8959 | if (intel_set_mode(crtc, mode, 0, 0, fb)) { |
6492711d | 8960 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
8961 | if (old->release_fb) |
8962 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 8963 | goto fail; |
79e53945 | 8964 | } |
9128b040 | 8965 | crtc->primary->crtc = crtc; |
7173188d | 8966 | |
79e53945 | 8967 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 8968 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 8969 | return true; |
412b61d8 VS |
8970 | |
8971 | fail: | |
83d65738 | 8972 | intel_crtc->new_enabled = crtc->state->enable; |
412b61d8 | 8973 | if (intel_crtc->new_enabled) |
6e3c9717 | 8974 | intel_crtc->new_config = intel_crtc->config; |
412b61d8 VS |
8975 | else |
8976 | intel_crtc->new_config = NULL; | |
51fd371b RC |
8977 | fail_unlock: |
8978 | if (ret == -EDEADLK) { | |
8979 | drm_modeset_backoff(ctx); | |
8980 | goto retry; | |
8981 | } | |
8982 | ||
412b61d8 | 8983 | return false; |
79e53945 JB |
8984 | } |
8985 | ||
d2434ab7 | 8986 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
208bf9fd | 8987 | struct intel_load_detect_pipe *old) |
79e53945 | 8988 | { |
d2434ab7 DV |
8989 | struct intel_encoder *intel_encoder = |
8990 | intel_attached_encoder(connector); | |
4ef69c7a | 8991 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 8992 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 8993 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 8994 | |
d2dff872 | 8995 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 8996 | connector->base.id, connector->name, |
8e329a03 | 8997 | encoder->base.id, encoder->name); |
d2dff872 | 8998 | |
8261b191 | 8999 | if (old->load_detect_temp) { |
fc303101 DV |
9000 | to_intel_connector(connector)->new_encoder = NULL; |
9001 | intel_encoder->new_crtc = NULL; | |
412b61d8 VS |
9002 | intel_crtc->new_enabled = false; |
9003 | intel_crtc->new_config = NULL; | |
fc303101 | 9004 | intel_set_mode(crtc, NULL, 0, 0, NULL); |
d2dff872 | 9005 | |
36206361 DV |
9006 | if (old->release_fb) { |
9007 | drm_framebuffer_unregister_private(old->release_fb); | |
9008 | drm_framebuffer_unreference(old->release_fb); | |
9009 | } | |
d2dff872 | 9010 | |
0622a53c | 9011 | return; |
79e53945 JB |
9012 | } |
9013 | ||
c751ce4f | 9014 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
9015 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
9016 | connector->funcs->dpms(connector, old->dpms_mode); | |
79e53945 JB |
9017 | } |
9018 | ||
da4a1efa | 9019 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 9020 | const struct intel_crtc_state *pipe_config) |
da4a1efa VS |
9021 | { |
9022 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9023 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
9024 | ||
9025 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 9026 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
9027 | else if (HAS_PCH_SPLIT(dev)) |
9028 | return 120000; | |
9029 | else if (!IS_GEN2(dev)) | |
9030 | return 96000; | |
9031 | else | |
9032 | return 48000; | |
9033 | } | |
9034 | ||
79e53945 | 9035 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 9036 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 9037 | struct intel_crtc_state *pipe_config) |
79e53945 | 9038 | { |
f1f644dc | 9039 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 9040 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 9041 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 9042 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
9043 | u32 fp; |
9044 | intel_clock_t clock; | |
da4a1efa | 9045 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
9046 | |
9047 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 9048 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 9049 | else |
293623f7 | 9050 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
9051 | |
9052 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
9053 | if (IS_PINEVIEW(dev)) { |
9054 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
9055 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
9056 | } else { |
9057 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
9058 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
9059 | } | |
9060 | ||
a6c45cf0 | 9061 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
9062 | if (IS_PINEVIEW(dev)) |
9063 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
9064 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
9065 | else |
9066 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
9067 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
9068 | ||
9069 | switch (dpll & DPLL_MODE_MASK) { | |
9070 | case DPLLB_MODE_DAC_SERIAL: | |
9071 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
9072 | 5 : 10; | |
9073 | break; | |
9074 | case DPLLB_MODE_LVDS: | |
9075 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
9076 | 7 : 14; | |
9077 | break; | |
9078 | default: | |
28c97730 | 9079 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 9080 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 9081 | return; |
79e53945 JB |
9082 | } |
9083 | ||
ac58c3f0 | 9084 | if (IS_PINEVIEW(dev)) |
da4a1efa | 9085 | pineview_clock(refclk, &clock); |
ac58c3f0 | 9086 | else |
da4a1efa | 9087 | i9xx_clock(refclk, &clock); |
79e53945 | 9088 | } else { |
0fb58223 | 9089 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 9090 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
9091 | |
9092 | if (is_lvds) { | |
9093 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
9094 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
9095 | |
9096 | if (lvds & LVDS_CLKB_POWER_UP) | |
9097 | clock.p2 = 7; | |
9098 | else | |
9099 | clock.p2 = 14; | |
79e53945 JB |
9100 | } else { |
9101 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
9102 | clock.p1 = 2; | |
9103 | else { | |
9104 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
9105 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
9106 | } | |
9107 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
9108 | clock.p2 = 4; | |
9109 | else | |
9110 | clock.p2 = 2; | |
79e53945 | 9111 | } |
da4a1efa VS |
9112 | |
9113 | i9xx_clock(refclk, &clock); | |
79e53945 JB |
9114 | } |
9115 | ||
18442d08 VS |
9116 | /* |
9117 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 9118 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
9119 | * encoder's get_config() function. |
9120 | */ | |
9121 | pipe_config->port_clock = clock.dot; | |
f1f644dc JB |
9122 | } |
9123 | ||
6878da05 VS |
9124 | int intel_dotclock_calculate(int link_freq, |
9125 | const struct intel_link_m_n *m_n) | |
f1f644dc | 9126 | { |
f1f644dc JB |
9127 | /* |
9128 | * The calculation for the data clock is: | |
1041a02f | 9129 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 9130 | * But we want to avoid losing precison if possible, so: |
1041a02f | 9131 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
9132 | * |
9133 | * and the link clock is simpler: | |
1041a02f | 9134 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
9135 | */ |
9136 | ||
6878da05 VS |
9137 | if (!m_n->link_n) |
9138 | return 0; | |
f1f644dc | 9139 | |
6878da05 VS |
9140 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
9141 | } | |
f1f644dc | 9142 | |
18442d08 | 9143 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 9144 | struct intel_crtc_state *pipe_config) |
6878da05 VS |
9145 | { |
9146 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 9147 | |
18442d08 VS |
9148 | /* read out port_clock from the DPLL */ |
9149 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 9150 | |
f1f644dc | 9151 | /* |
18442d08 | 9152 | * This value does not include pixel_multiplier. |
241bfc38 | 9153 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
9154 | * agree once we know their relationship in the encoder's |
9155 | * get_config() function. | |
79e53945 | 9156 | */ |
2d112de7 | 9157 | pipe_config->base.adjusted_mode.crtc_clock = |
18442d08 VS |
9158 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
9159 | &pipe_config->fdi_m_n); | |
79e53945 JB |
9160 | } |
9161 | ||
9162 | /** Returns the currently programmed mode of the given pipe. */ | |
9163 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
9164 | struct drm_crtc *crtc) | |
9165 | { | |
548f245b | 9166 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 9167 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 9168 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 9169 | struct drm_display_mode *mode; |
5cec258b | 9170 | struct intel_crtc_state pipe_config; |
fe2b8f9d PZ |
9171 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
9172 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
9173 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
9174 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 9175 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
9176 | |
9177 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
9178 | if (!mode) | |
9179 | return NULL; | |
9180 | ||
f1f644dc JB |
9181 | /* |
9182 | * Construct a pipe_config sufficient for getting the clock info | |
9183 | * back out of crtc_clock_get. | |
9184 | * | |
9185 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
9186 | * to use a real value here instead. | |
9187 | */ | |
293623f7 | 9188 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 9189 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
9190 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
9191 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
9192 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
9193 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
9194 | ||
773ae034 | 9195 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
9196 | mode->hdisplay = (htot & 0xffff) + 1; |
9197 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
9198 | mode->hsync_start = (hsync & 0xffff) + 1; | |
9199 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
9200 | mode->vdisplay = (vtot & 0xffff) + 1; | |
9201 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
9202 | mode->vsync_start = (vsync & 0xffff) + 1; | |
9203 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
9204 | ||
9205 | drm_mode_set_name(mode); | |
79e53945 JB |
9206 | |
9207 | return mode; | |
9208 | } | |
9209 | ||
652c393a JB |
9210 | static void intel_decrease_pllclock(struct drm_crtc *crtc) |
9211 | { | |
9212 | struct drm_device *dev = crtc->dev; | |
fbee40df | 9213 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 9214 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
652c393a | 9215 | |
baff296c | 9216 | if (!HAS_GMCH_DISPLAY(dev)) |
652c393a JB |
9217 | return; |
9218 | ||
9219 | if (!dev_priv->lvds_downclock_avail) | |
9220 | return; | |
9221 | ||
9222 | /* | |
9223 | * Since this is called by a timer, we should never get here in | |
9224 | * the manual case. | |
9225 | */ | |
9226 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
9227 | int pipe = intel_crtc->pipe; |
9228 | int dpll_reg = DPLL(pipe); | |
9229 | int dpll; | |
f6e5b160 | 9230 | |
44d98a61 | 9231 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 9232 | |
8ac5a6d5 | 9233 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 9234 | |
dc257cf1 | 9235 | dpll = I915_READ(dpll_reg); |
652c393a JB |
9236 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
9237 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 9238 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
9239 | dpll = I915_READ(dpll_reg); |
9240 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 9241 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
9242 | } |
9243 | ||
9244 | } | |
9245 | ||
f047e395 CW |
9246 | void intel_mark_busy(struct drm_device *dev) |
9247 | { | |
c67a470b PZ |
9248 | struct drm_i915_private *dev_priv = dev->dev_private; |
9249 | ||
f62a0076 CW |
9250 | if (dev_priv->mm.busy) |
9251 | return; | |
9252 | ||
43694d69 | 9253 | intel_runtime_pm_get(dev_priv); |
c67a470b | 9254 | i915_update_gfx_val(dev_priv); |
43cf3bf0 CW |
9255 | if (INTEL_INFO(dev)->gen >= 6) |
9256 | gen6_rps_busy(dev_priv); | |
f62a0076 | 9257 | dev_priv->mm.busy = true; |
f047e395 CW |
9258 | } |
9259 | ||
9260 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 9261 | { |
c67a470b | 9262 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 9263 | struct drm_crtc *crtc; |
652c393a | 9264 | |
f62a0076 CW |
9265 | if (!dev_priv->mm.busy) |
9266 | return; | |
9267 | ||
9268 | dev_priv->mm.busy = false; | |
9269 | ||
d330a953 | 9270 | if (!i915.powersave) |
bb4cdd53 | 9271 | goto out; |
652c393a | 9272 | |
70e1e0ec | 9273 | for_each_crtc(dev, crtc) { |
f4510a27 | 9274 | if (!crtc->primary->fb) |
652c393a JB |
9275 | continue; |
9276 | ||
725a5b54 | 9277 | intel_decrease_pllclock(crtc); |
652c393a | 9278 | } |
b29c19b6 | 9279 | |
3d13ef2e | 9280 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 9281 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 PZ |
9282 | |
9283 | out: | |
43694d69 | 9284 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
9285 | } |
9286 | ||
f5de6e07 ACO |
9287 | static void intel_crtc_set_state(struct intel_crtc *crtc, |
9288 | struct intel_crtc_state *crtc_state) | |
9289 | { | |
9290 | kfree(crtc->config); | |
9291 | crtc->config = crtc_state; | |
16f3f658 | 9292 | crtc->base.state = &crtc_state->base; |
f5de6e07 ACO |
9293 | } |
9294 | ||
79e53945 JB |
9295 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
9296 | { | |
9297 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
9298 | struct drm_device *dev = crtc->dev; |
9299 | struct intel_unpin_work *work; | |
67e77c5a | 9300 | |
5e2d7afc | 9301 | spin_lock_irq(&dev->event_lock); |
67e77c5a DV |
9302 | work = intel_crtc->unpin_work; |
9303 | intel_crtc->unpin_work = NULL; | |
5e2d7afc | 9304 | spin_unlock_irq(&dev->event_lock); |
67e77c5a DV |
9305 | |
9306 | if (work) { | |
9307 | cancel_work_sync(&work->work); | |
9308 | kfree(work); | |
9309 | } | |
79e53945 | 9310 | |
f5de6e07 | 9311 | intel_crtc_set_state(intel_crtc, NULL); |
79e53945 | 9312 | drm_crtc_cleanup(crtc); |
67e77c5a | 9313 | |
79e53945 JB |
9314 | kfree(intel_crtc); |
9315 | } | |
9316 | ||
6b95a207 KH |
9317 | static void intel_unpin_work_fn(struct work_struct *__work) |
9318 | { | |
9319 | struct intel_unpin_work *work = | |
9320 | container_of(__work, struct intel_unpin_work, work); | |
b4a98e57 | 9321 | struct drm_device *dev = work->crtc->dev; |
f99d7069 | 9322 | enum pipe pipe = to_intel_crtc(work->crtc)->pipe; |
6b95a207 | 9323 | |
b4a98e57 | 9324 | mutex_lock(&dev->struct_mutex); |
82bc3b2d | 9325 | intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state); |
05394f39 | 9326 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
d9e86c0e | 9327 | |
7ff0ebcc | 9328 | intel_fbc_update(dev); |
f06cc1b9 JH |
9329 | |
9330 | if (work->flip_queued_req) | |
146d84f0 | 9331 | i915_gem_request_assign(&work->flip_queued_req, NULL); |
b4a98e57 CW |
9332 | mutex_unlock(&dev->struct_mutex); |
9333 | ||
f99d7069 | 9334 | intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
89ed88ba | 9335 | drm_framebuffer_unreference(work->old_fb); |
f99d7069 | 9336 | |
b4a98e57 CW |
9337 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); |
9338 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); | |
9339 | ||
6b95a207 KH |
9340 | kfree(work); |
9341 | } | |
9342 | ||
1afe3e9d | 9343 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 9344 | struct drm_crtc *crtc) |
6b95a207 | 9345 | { |
6b95a207 KH |
9346 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9347 | struct intel_unpin_work *work; | |
6b95a207 KH |
9348 | unsigned long flags; |
9349 | ||
9350 | /* Ignore early vblank irqs */ | |
9351 | if (intel_crtc == NULL) | |
9352 | return; | |
9353 | ||
f326038a DV |
9354 | /* |
9355 | * This is called both by irq handlers and the reset code (to complete | |
9356 | * lost pageflips) so needs the full irqsave spinlocks. | |
9357 | */ | |
6b95a207 KH |
9358 | spin_lock_irqsave(&dev->event_lock, flags); |
9359 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
9360 | |
9361 | /* Ensure we don't miss a work->pending update ... */ | |
9362 | smp_rmb(); | |
9363 | ||
9364 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
9365 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9366 | return; | |
9367 | } | |
9368 | ||
d6bbafa1 | 9369 | page_flip_completed(intel_crtc); |
0af7e4df | 9370 | |
6b95a207 | 9371 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6b95a207 KH |
9372 | } |
9373 | ||
1afe3e9d JB |
9374 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
9375 | { | |
fbee40df | 9376 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
9377 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
9378 | ||
49b14a5c | 9379 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
9380 | } |
9381 | ||
9382 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
9383 | { | |
fbee40df | 9384 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
9385 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
9386 | ||
49b14a5c | 9387 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
9388 | } |
9389 | ||
75f7f3ec VS |
9390 | /* Is 'a' after or equal to 'b'? */ |
9391 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
9392 | { | |
9393 | return !((a - b) & 0x80000000); | |
9394 | } | |
9395 | ||
9396 | static bool page_flip_finished(struct intel_crtc *crtc) | |
9397 | { | |
9398 | struct drm_device *dev = crtc->base.dev; | |
9399 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9400 | ||
bdfa7542 VS |
9401 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
9402 | crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
9403 | return true; | |
9404 | ||
75f7f3ec VS |
9405 | /* |
9406 | * The relevant registers doen't exist on pre-ctg. | |
9407 | * As the flip done interrupt doesn't trigger for mmio | |
9408 | * flips on gmch platforms, a flip count check isn't | |
9409 | * really needed there. But since ctg has the registers, | |
9410 | * include it in the check anyway. | |
9411 | */ | |
9412 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
9413 | return true; | |
9414 | ||
9415 | /* | |
9416 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
9417 | * used the same base address. In that case the mmio flip might | |
9418 | * have completed, but the CS hasn't even executed the flip yet. | |
9419 | * | |
9420 | * A flip count check isn't enough as the CS might have updated | |
9421 | * the base address just after start of vblank, but before we | |
9422 | * managed to process the interrupt. This means we'd complete the | |
9423 | * CS flip too soon. | |
9424 | * | |
9425 | * Combining both checks should get us a good enough result. It may | |
9426 | * still happen that the CS flip has been executed, but has not | |
9427 | * yet actually completed. But in case the base address is the same | |
9428 | * anyway, we don't really care. | |
9429 | */ | |
9430 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
9431 | crtc->unpin_work->gtt_offset && | |
9432 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)), | |
9433 | crtc->unpin_work->flip_count); | |
9434 | } | |
9435 | ||
6b95a207 KH |
9436 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
9437 | { | |
fbee40df | 9438 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
9439 | struct intel_crtc *intel_crtc = |
9440 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
9441 | unsigned long flags; | |
9442 | ||
f326038a DV |
9443 | |
9444 | /* | |
9445 | * This is called both by irq handlers and the reset code (to complete | |
9446 | * lost pageflips) so needs the full irqsave spinlocks. | |
9447 | * | |
9448 | * NB: An MMIO update of the plane base pointer will also | |
e7d841ca CW |
9449 | * generate a page-flip completion irq, i.e. every modeset |
9450 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
9451 | */ | |
6b95a207 | 9452 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 9453 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 9454 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
9455 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9456 | } | |
9457 | ||
eba905b2 | 9458 | static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
e7d841ca CW |
9459 | { |
9460 | /* Ensure that the work item is consistent when activating it ... */ | |
9461 | smp_wmb(); | |
9462 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
9463 | /* and that it is marked active as soon as the irq could fire. */ | |
9464 | smp_wmb(); | |
9465 | } | |
9466 | ||
8c9f3aaf JB |
9467 | static int intel_gen2_queue_flip(struct drm_device *dev, |
9468 | struct drm_crtc *crtc, | |
9469 | struct drm_framebuffer *fb, | |
ed8d1975 | 9470 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9471 | struct intel_engine_cs *ring, |
ed8d1975 | 9472 | uint32_t flags) |
8c9f3aaf | 9473 | { |
8c9f3aaf | 9474 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
9475 | u32 flip_mask; |
9476 | int ret; | |
9477 | ||
6d90c952 | 9478 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 9479 | if (ret) |
4fa62c89 | 9480 | return ret; |
8c9f3aaf JB |
9481 | |
9482 | /* Can't queue multiple flips, so wait for the previous | |
9483 | * one to finish before executing the next. | |
9484 | */ | |
9485 | if (intel_crtc->plane) | |
9486 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
9487 | else | |
9488 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
9489 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
9490 | intel_ring_emit(ring, MI_NOOP); | |
9491 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
9492 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9493 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9494 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 | 9495 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
9496 | |
9497 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9498 | __intel_ring_advance(ring); |
83d4092b | 9499 | return 0; |
8c9f3aaf JB |
9500 | } |
9501 | ||
9502 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
9503 | struct drm_crtc *crtc, | |
9504 | struct drm_framebuffer *fb, | |
ed8d1975 | 9505 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9506 | struct intel_engine_cs *ring, |
ed8d1975 | 9507 | uint32_t flags) |
8c9f3aaf | 9508 | { |
8c9f3aaf | 9509 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
9510 | u32 flip_mask; |
9511 | int ret; | |
9512 | ||
6d90c952 | 9513 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 9514 | if (ret) |
4fa62c89 | 9515 | return ret; |
8c9f3aaf JB |
9516 | |
9517 | if (intel_crtc->plane) | |
9518 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
9519 | else | |
9520 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
9521 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
9522 | intel_ring_emit(ring, MI_NOOP); | |
9523 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
9524 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9525 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9526 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 DV |
9527 | intel_ring_emit(ring, MI_NOOP); |
9528 | ||
e7d841ca | 9529 | intel_mark_page_flip_active(intel_crtc); |
09246732 | 9530 | __intel_ring_advance(ring); |
83d4092b | 9531 | return 0; |
8c9f3aaf JB |
9532 | } |
9533 | ||
9534 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
9535 | struct drm_crtc *crtc, | |
9536 | struct drm_framebuffer *fb, | |
ed8d1975 | 9537 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9538 | struct intel_engine_cs *ring, |
ed8d1975 | 9539 | uint32_t flags) |
8c9f3aaf JB |
9540 | { |
9541 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9542 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9543 | uint32_t pf, pipesrc; | |
9544 | int ret; | |
9545 | ||
6d90c952 | 9546 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 9547 | if (ret) |
4fa62c89 | 9548 | return ret; |
8c9f3aaf JB |
9549 | |
9550 | /* i965+ uses the linear or tiled offsets from the | |
9551 | * Display Registers (which do not change across a page-flip) | |
9552 | * so we need only reprogram the base address. | |
9553 | */ | |
6d90c952 DV |
9554 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
9555 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9556 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9557 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
c2c75131 | 9558 | obj->tiling_mode); |
8c9f3aaf JB |
9559 | |
9560 | /* XXX Enabling the panel-fitter across page-flip is so far | |
9561 | * untested on non-native modes, so ignore it for now. | |
9562 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
9563 | */ | |
9564 | pf = 0; | |
9565 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 9566 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
9567 | |
9568 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9569 | __intel_ring_advance(ring); |
83d4092b | 9570 | return 0; |
8c9f3aaf JB |
9571 | } |
9572 | ||
9573 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
9574 | struct drm_crtc *crtc, | |
9575 | struct drm_framebuffer *fb, | |
ed8d1975 | 9576 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9577 | struct intel_engine_cs *ring, |
ed8d1975 | 9578 | uint32_t flags) |
8c9f3aaf JB |
9579 | { |
9580 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9581 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9582 | uint32_t pf, pipesrc; | |
9583 | int ret; | |
9584 | ||
6d90c952 | 9585 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 9586 | if (ret) |
4fa62c89 | 9587 | return ret; |
8c9f3aaf | 9588 | |
6d90c952 DV |
9589 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
9590 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9591 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
75f7f3ec | 9592 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8c9f3aaf | 9593 | |
dc257cf1 DV |
9594 | /* Contrary to the suggestions in the documentation, |
9595 | * "Enable Panel Fitter" does not seem to be required when page | |
9596 | * flipping with a non-native mode, and worse causes a normal | |
9597 | * modeset to fail. | |
9598 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
9599 | */ | |
9600 | pf = 0; | |
8c9f3aaf | 9601 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 9602 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
9603 | |
9604 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9605 | __intel_ring_advance(ring); |
83d4092b | 9606 | return 0; |
8c9f3aaf JB |
9607 | } |
9608 | ||
7c9017e5 JB |
9609 | static int intel_gen7_queue_flip(struct drm_device *dev, |
9610 | struct drm_crtc *crtc, | |
9611 | struct drm_framebuffer *fb, | |
ed8d1975 | 9612 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9613 | struct intel_engine_cs *ring, |
ed8d1975 | 9614 | uint32_t flags) |
7c9017e5 | 9615 | { |
7c9017e5 | 9616 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 9617 | uint32_t plane_bit = 0; |
ffe74d75 CW |
9618 | int len, ret; |
9619 | ||
eba905b2 | 9620 | switch (intel_crtc->plane) { |
cb05d8de DV |
9621 | case PLANE_A: |
9622 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
9623 | break; | |
9624 | case PLANE_B: | |
9625 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
9626 | break; | |
9627 | case PLANE_C: | |
9628 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
9629 | break; | |
9630 | default: | |
9631 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 9632 | return -ENODEV; |
cb05d8de DV |
9633 | } |
9634 | ||
ffe74d75 | 9635 | len = 4; |
f476828a | 9636 | if (ring->id == RCS) { |
ffe74d75 | 9637 | len += 6; |
f476828a DL |
9638 | /* |
9639 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
9640 | * 48bits addresses, and we need a NOOP for the batch size to | |
9641 | * stay even. | |
9642 | */ | |
9643 | if (IS_GEN8(dev)) | |
9644 | len += 2; | |
9645 | } | |
ffe74d75 | 9646 | |
f66fab8e VS |
9647 | /* |
9648 | * BSpec MI_DISPLAY_FLIP for IVB: | |
9649 | * "The full packet must be contained within the same cache line." | |
9650 | * | |
9651 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
9652 | * cacheline, if we ever start emitting more commands before | |
9653 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
9654 | * then do the cacheline alignment, and finally emit the | |
9655 | * MI_DISPLAY_FLIP. | |
9656 | */ | |
9657 | ret = intel_ring_cacheline_align(ring); | |
9658 | if (ret) | |
4fa62c89 | 9659 | return ret; |
f66fab8e | 9660 | |
ffe74d75 | 9661 | ret = intel_ring_begin(ring, len); |
7c9017e5 | 9662 | if (ret) |
4fa62c89 | 9663 | return ret; |
7c9017e5 | 9664 | |
ffe74d75 CW |
9665 | /* Unmask the flip-done completion message. Note that the bspec says that |
9666 | * we should do this for both the BCS and RCS, and that we must not unmask | |
9667 | * more than one flip event at any time (or ensure that one flip message | |
9668 | * can be sent by waiting for flip-done prior to queueing new flips). | |
9669 | * Experimentation says that BCS works despite DERRMR masking all | |
9670 | * flip-done completion events and that unmasking all planes at once | |
9671 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
9672 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
9673 | */ | |
9674 | if (ring->id == RCS) { | |
9675 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
9676 | intel_ring_emit(ring, DERRMR); | |
9677 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
9678 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
9679 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a DL |
9680 | if (IS_GEN8(dev)) |
9681 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) | | |
9682 | MI_SRM_LRM_GLOBAL_GTT); | |
9683 | else | |
9684 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | | |
9685 | MI_SRM_LRM_GLOBAL_GTT); | |
ffe74d75 CW |
9686 | intel_ring_emit(ring, DERRMR); |
9687 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
f476828a DL |
9688 | if (IS_GEN8(dev)) { |
9689 | intel_ring_emit(ring, 0); | |
9690 | intel_ring_emit(ring, MI_NOOP); | |
9691 | } | |
ffe74d75 CW |
9692 | } |
9693 | ||
cb05d8de | 9694 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 9695 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
75f7f3ec | 9696 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
7c9017e5 | 9697 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
9698 | |
9699 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9700 | __intel_ring_advance(ring); |
83d4092b | 9701 | return 0; |
7c9017e5 JB |
9702 | } |
9703 | ||
84c33a64 SG |
9704 | static bool use_mmio_flip(struct intel_engine_cs *ring, |
9705 | struct drm_i915_gem_object *obj) | |
9706 | { | |
9707 | /* | |
9708 | * This is not being used for older platforms, because | |
9709 | * non-availability of flip done interrupt forces us to use | |
9710 | * CS flips. Older platforms derive flip done using some clever | |
9711 | * tricks involving the flip_pending status bits and vblank irqs. | |
9712 | * So using MMIO flips there would disrupt this mechanism. | |
9713 | */ | |
9714 | ||
8e09bf83 CW |
9715 | if (ring == NULL) |
9716 | return true; | |
9717 | ||
84c33a64 SG |
9718 | if (INTEL_INFO(ring->dev)->gen < 5) |
9719 | return false; | |
9720 | ||
9721 | if (i915.use_mmio_flip < 0) | |
9722 | return false; | |
9723 | else if (i915.use_mmio_flip > 0) | |
9724 | return true; | |
14bf993e OM |
9725 | else if (i915.enable_execlists) |
9726 | return true; | |
84c33a64 | 9727 | else |
41c52415 | 9728 | return ring != i915_gem_request_get_ring(obj->last_read_req); |
84c33a64 SG |
9729 | } |
9730 | ||
ff944564 DL |
9731 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc) |
9732 | { | |
9733 | struct drm_device *dev = intel_crtc->base.dev; | |
9734 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9735 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; | |
9736 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
9737 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
9738 | const enum pipe pipe = intel_crtc->pipe; | |
9739 | u32 ctl, stride; | |
9740 | ||
9741 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
9742 | ctl &= ~PLANE_CTL_TILED_MASK; | |
9743 | if (obj->tiling_mode == I915_TILING_X) | |
9744 | ctl |= PLANE_CTL_TILED_X; | |
9745 | ||
9746 | /* | |
9747 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
9748 | * linear buffers or in number of tiles for tiled buffers. | |
9749 | */ | |
9750 | stride = fb->pitches[0] >> 6; | |
9751 | if (obj->tiling_mode == I915_TILING_X) | |
9752 | stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */ | |
9753 | ||
9754 | /* | |
9755 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
9756 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
9757 | */ | |
9758 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
9759 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
9760 | ||
9761 | I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset); | |
9762 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
9763 | } | |
9764 | ||
9765 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc) | |
84c33a64 SG |
9766 | { |
9767 | struct drm_device *dev = intel_crtc->base.dev; | |
9768 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9769 | struct intel_framebuffer *intel_fb = | |
9770 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
9771 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
9772 | u32 dspcntr; | |
9773 | u32 reg; | |
9774 | ||
84c33a64 SG |
9775 | reg = DSPCNTR(intel_crtc->plane); |
9776 | dspcntr = I915_READ(reg); | |
9777 | ||
c5d97472 DL |
9778 | if (obj->tiling_mode != I915_TILING_NONE) |
9779 | dspcntr |= DISPPLANE_TILED; | |
9780 | else | |
9781 | dspcntr &= ~DISPPLANE_TILED; | |
9782 | ||
84c33a64 SG |
9783 | I915_WRITE(reg, dspcntr); |
9784 | ||
9785 | I915_WRITE(DSPSURF(intel_crtc->plane), | |
9786 | intel_crtc->unpin_work->gtt_offset); | |
9787 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
84c33a64 | 9788 | |
ff944564 DL |
9789 | } |
9790 | ||
9791 | /* | |
9792 | * XXX: This is the temporary way to update the plane registers until we get | |
9793 | * around to using the usual plane update functions for MMIO flips | |
9794 | */ | |
9795 | static void intel_do_mmio_flip(struct intel_crtc *intel_crtc) | |
9796 | { | |
9797 | struct drm_device *dev = intel_crtc->base.dev; | |
9798 | bool atomic_update; | |
9799 | u32 start_vbl_count; | |
9800 | ||
9801 | intel_mark_page_flip_active(intel_crtc); | |
9802 | ||
9803 | atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count); | |
9804 | ||
9805 | if (INTEL_INFO(dev)->gen >= 9) | |
9806 | skl_do_mmio_flip(intel_crtc); | |
9807 | else | |
9808 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
9809 | ilk_do_mmio_flip(intel_crtc); | |
9810 | ||
9362c7c5 ACO |
9811 | if (atomic_update) |
9812 | intel_pipe_update_end(intel_crtc, start_vbl_count); | |
84c33a64 SG |
9813 | } |
9814 | ||
9362c7c5 | 9815 | static void intel_mmio_flip_work_func(struct work_struct *work) |
84c33a64 | 9816 | { |
cc8c4cc2 | 9817 | struct intel_crtc *crtc = |
9362c7c5 | 9818 | container_of(work, struct intel_crtc, mmio_flip.work); |
cc8c4cc2 | 9819 | struct intel_mmio_flip *mmio_flip; |
84c33a64 | 9820 | |
cc8c4cc2 JH |
9821 | mmio_flip = &crtc->mmio_flip; |
9822 | if (mmio_flip->req) | |
9c654818 JH |
9823 | WARN_ON(__i915_wait_request(mmio_flip->req, |
9824 | crtc->reset_counter, | |
9825 | false, NULL, NULL) != 0); | |
84c33a64 | 9826 | |
cc8c4cc2 JH |
9827 | intel_do_mmio_flip(crtc); |
9828 | if (mmio_flip->req) { | |
9829 | mutex_lock(&crtc->base.dev->struct_mutex); | |
146d84f0 | 9830 | i915_gem_request_assign(&mmio_flip->req, NULL); |
cc8c4cc2 JH |
9831 | mutex_unlock(&crtc->base.dev->struct_mutex); |
9832 | } | |
84c33a64 SG |
9833 | } |
9834 | ||
9835 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
9836 | struct drm_crtc *crtc, | |
9837 | struct drm_framebuffer *fb, | |
9838 | struct drm_i915_gem_object *obj, | |
9839 | struct intel_engine_cs *ring, | |
9840 | uint32_t flags) | |
9841 | { | |
84c33a64 | 9842 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
84c33a64 | 9843 | |
cc8c4cc2 JH |
9844 | i915_gem_request_assign(&intel_crtc->mmio_flip.req, |
9845 | obj->last_write_req); | |
536f5b5e ACO |
9846 | |
9847 | schedule_work(&intel_crtc->mmio_flip.work); | |
84c33a64 | 9848 | |
84c33a64 SG |
9849 | return 0; |
9850 | } | |
9851 | ||
8c9f3aaf JB |
9852 | static int intel_default_queue_flip(struct drm_device *dev, |
9853 | struct drm_crtc *crtc, | |
9854 | struct drm_framebuffer *fb, | |
ed8d1975 | 9855 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9856 | struct intel_engine_cs *ring, |
ed8d1975 | 9857 | uint32_t flags) |
8c9f3aaf JB |
9858 | { |
9859 | return -ENODEV; | |
9860 | } | |
9861 | ||
d6bbafa1 CW |
9862 | static bool __intel_pageflip_stall_check(struct drm_device *dev, |
9863 | struct drm_crtc *crtc) | |
9864 | { | |
9865 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9866 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9867 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
9868 | u32 addr; | |
9869 | ||
9870 | if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) | |
9871 | return true; | |
9872 | ||
9873 | if (!work->enable_stall_check) | |
9874 | return false; | |
9875 | ||
9876 | if (work->flip_ready_vblank == 0) { | |
3a8a946e DV |
9877 | if (work->flip_queued_req && |
9878 | !i915_gem_request_completed(work->flip_queued_req, true)) | |
d6bbafa1 CW |
9879 | return false; |
9880 | ||
1e3feefd | 9881 | work->flip_ready_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 CW |
9882 | } |
9883 | ||
1e3feefd | 9884 | if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) |
d6bbafa1 CW |
9885 | return false; |
9886 | ||
9887 | /* Potential stall - if we see that the flip has happened, | |
9888 | * assume a missed interrupt. */ | |
9889 | if (INTEL_INFO(dev)->gen >= 4) | |
9890 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
9891 | else | |
9892 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
9893 | ||
9894 | /* There is a potential issue here with a false positive after a flip | |
9895 | * to the same address. We could address this by checking for a | |
9896 | * non-incrementing frame counter. | |
9897 | */ | |
9898 | return addr == work->gtt_offset; | |
9899 | } | |
9900 | ||
9901 | void intel_check_page_flip(struct drm_device *dev, int pipe) | |
9902 | { | |
9903 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9904 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
9905 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
f326038a | 9906 | |
6c51d46f | 9907 | WARN_ON(!in_interrupt()); |
d6bbafa1 CW |
9908 | |
9909 | if (crtc == NULL) | |
9910 | return; | |
9911 | ||
f326038a | 9912 | spin_lock(&dev->event_lock); |
d6bbafa1 CW |
9913 | if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) { |
9914 | WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", | |
1e3feefd DV |
9915 | intel_crtc->unpin_work->flip_queued_vblank, |
9916 | drm_vblank_count(dev, pipe)); | |
d6bbafa1 CW |
9917 | page_flip_completed(intel_crtc); |
9918 | } | |
f326038a | 9919 | spin_unlock(&dev->event_lock); |
d6bbafa1 CW |
9920 | } |
9921 | ||
6b95a207 KH |
9922 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
9923 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
9924 | struct drm_pending_vblank_event *event, |
9925 | uint32_t page_flip_flags) | |
6b95a207 KH |
9926 | { |
9927 | struct drm_device *dev = crtc->dev; | |
9928 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 9929 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 9930 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 | 9931 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
455a6808 | 9932 | struct drm_plane *primary = crtc->primary; |
a071fa00 | 9933 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 9934 | struct intel_unpin_work *work; |
a4872ba6 | 9935 | struct intel_engine_cs *ring; |
52e68630 | 9936 | int ret; |
6b95a207 | 9937 | |
2ff8fde1 MR |
9938 | /* |
9939 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
9940 | * check to be safe. In the future we may enable pageflipping from | |
9941 | * a disabled primary plane. | |
9942 | */ | |
9943 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
9944 | return -EBUSY; | |
9945 | ||
e6a595d2 | 9946 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 9947 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
9948 | return -EINVAL; |
9949 | ||
9950 | /* | |
9951 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
9952 | * Note that pitch changes could also affect these register. | |
9953 | */ | |
9954 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
9955 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
9956 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
9957 | return -EINVAL; |
9958 | ||
f900db47 CW |
9959 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
9960 | goto out_hang; | |
9961 | ||
b14c5679 | 9962 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
9963 | if (work == NULL) |
9964 | return -ENOMEM; | |
9965 | ||
6b95a207 | 9966 | work->event = event; |
b4a98e57 | 9967 | work->crtc = crtc; |
ab8d6675 | 9968 | work->old_fb = old_fb; |
6b95a207 KH |
9969 | INIT_WORK(&work->work, intel_unpin_work_fn); |
9970 | ||
87b6b101 | 9971 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
9972 | if (ret) |
9973 | goto free_work; | |
9974 | ||
6b95a207 | 9975 | /* We borrow the event spin lock for protecting unpin_work */ |
5e2d7afc | 9976 | spin_lock_irq(&dev->event_lock); |
6b95a207 | 9977 | if (intel_crtc->unpin_work) { |
d6bbafa1 CW |
9978 | /* Before declaring the flip queue wedged, check if |
9979 | * the hardware completed the operation behind our backs. | |
9980 | */ | |
9981 | if (__intel_pageflip_stall_check(dev, crtc)) { | |
9982 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
9983 | page_flip_completed(intel_crtc); | |
9984 | } else { | |
9985 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
5e2d7afc | 9986 | spin_unlock_irq(&dev->event_lock); |
468f0b44 | 9987 | |
d6bbafa1 CW |
9988 | drm_crtc_vblank_put(crtc); |
9989 | kfree(work); | |
9990 | return -EBUSY; | |
9991 | } | |
6b95a207 KH |
9992 | } |
9993 | intel_crtc->unpin_work = work; | |
5e2d7afc | 9994 | spin_unlock_irq(&dev->event_lock); |
6b95a207 | 9995 | |
b4a98e57 CW |
9996 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
9997 | flush_workqueue(dev_priv->wq); | |
9998 | ||
75dfca80 | 9999 | /* Reference the objects for the scheduled work. */ |
ab8d6675 | 10000 | drm_framebuffer_reference(work->old_fb); |
05394f39 | 10001 | drm_gem_object_reference(&obj->base); |
6b95a207 | 10002 | |
f4510a27 | 10003 | crtc->primary->fb = fb; |
afd65eb4 | 10004 | update_state_fb(crtc->primary); |
1ed1f968 | 10005 | |
e1f99ce6 | 10006 | work->pending_flip_obj = obj; |
e1f99ce6 | 10007 | |
89ed88ba CW |
10008 | ret = i915_mutex_lock_interruptible(dev); |
10009 | if (ret) | |
10010 | goto cleanup; | |
10011 | ||
b4a98e57 | 10012 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 10013 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 10014 | |
75f7f3ec | 10015 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
a071fa00 | 10016 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1; |
75f7f3ec | 10017 | |
4fa62c89 VS |
10018 | if (IS_VALLEYVIEW(dev)) { |
10019 | ring = &dev_priv->ring[BCS]; | |
ab8d6675 | 10020 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) |
8e09bf83 CW |
10021 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
10022 | ring = NULL; | |
48bf5b2d | 10023 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
2a92d5bc | 10024 | ring = &dev_priv->ring[BCS]; |
4fa62c89 | 10025 | } else if (INTEL_INFO(dev)->gen >= 7) { |
41c52415 | 10026 | ring = i915_gem_request_get_ring(obj->last_read_req); |
4fa62c89 VS |
10027 | if (ring == NULL || ring->id != RCS) |
10028 | ring = &dev_priv->ring[BCS]; | |
10029 | } else { | |
10030 | ring = &dev_priv->ring[RCS]; | |
10031 | } | |
10032 | ||
82bc3b2d TU |
10033 | ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, |
10034 | crtc->primary->state, ring); | |
8c9f3aaf JB |
10035 | if (ret) |
10036 | goto cleanup_pending; | |
6b95a207 | 10037 | |
4fa62c89 VS |
10038 | work->gtt_offset = |
10039 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset; | |
10040 | ||
d6bbafa1 | 10041 | if (use_mmio_flip(ring, obj)) { |
84c33a64 SG |
10042 | ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring, |
10043 | page_flip_flags); | |
d6bbafa1 CW |
10044 | if (ret) |
10045 | goto cleanup_unpin; | |
10046 | ||
f06cc1b9 JH |
10047 | i915_gem_request_assign(&work->flip_queued_req, |
10048 | obj->last_write_req); | |
d6bbafa1 | 10049 | } else { |
84c33a64 | 10050 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, |
d6bbafa1 CW |
10051 | page_flip_flags); |
10052 | if (ret) | |
10053 | goto cleanup_unpin; | |
10054 | ||
f06cc1b9 JH |
10055 | i915_gem_request_assign(&work->flip_queued_req, |
10056 | intel_ring_get_request(ring)); | |
d6bbafa1 CW |
10057 | } |
10058 | ||
1e3feefd | 10059 | work->flip_queued_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 | 10060 | work->enable_stall_check = true; |
4fa62c89 | 10061 | |
ab8d6675 | 10062 | i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, |
a071fa00 DV |
10063 | INTEL_FRONTBUFFER_PRIMARY(pipe)); |
10064 | ||
7ff0ebcc | 10065 | intel_fbc_disable(dev); |
f99d7069 | 10066 | intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
6b95a207 KH |
10067 | mutex_unlock(&dev->struct_mutex); |
10068 | ||
e5510fac JB |
10069 | trace_i915_flip_request(intel_crtc->plane, obj); |
10070 | ||
6b95a207 | 10071 | return 0; |
96b099fd | 10072 | |
4fa62c89 | 10073 | cleanup_unpin: |
82bc3b2d | 10074 | intel_unpin_fb_obj(fb, crtc->primary->state); |
8c9f3aaf | 10075 | cleanup_pending: |
b4a98e57 | 10076 | atomic_dec(&intel_crtc->unpin_work_count); |
89ed88ba CW |
10077 | mutex_unlock(&dev->struct_mutex); |
10078 | cleanup: | |
f4510a27 | 10079 | crtc->primary->fb = old_fb; |
afd65eb4 | 10080 | update_state_fb(crtc->primary); |
89ed88ba CW |
10081 | |
10082 | drm_gem_object_unreference_unlocked(&obj->base); | |
ab8d6675 | 10083 | drm_framebuffer_unreference(work->old_fb); |
96b099fd | 10084 | |
5e2d7afc | 10085 | spin_lock_irq(&dev->event_lock); |
96b099fd | 10086 | intel_crtc->unpin_work = NULL; |
5e2d7afc | 10087 | spin_unlock_irq(&dev->event_lock); |
96b099fd | 10088 | |
87b6b101 | 10089 | drm_crtc_vblank_put(crtc); |
7317c75e | 10090 | free_work: |
96b099fd CW |
10091 | kfree(work); |
10092 | ||
f900db47 CW |
10093 | if (ret == -EIO) { |
10094 | out_hang: | |
53a366b9 | 10095 | ret = intel_plane_restore(primary); |
f0d3dad3 | 10096 | if (ret == 0 && event) { |
5e2d7afc | 10097 | spin_lock_irq(&dev->event_lock); |
a071fa00 | 10098 | drm_send_vblank_event(dev, pipe, event); |
5e2d7afc | 10099 | spin_unlock_irq(&dev->event_lock); |
f0d3dad3 | 10100 | } |
f900db47 | 10101 | } |
96b099fd | 10102 | return ret; |
6b95a207 KH |
10103 | } |
10104 | ||
f6e5b160 | 10105 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
10106 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
10107 | .load_lut = intel_crtc_load_lut, | |
ea2c67bb MR |
10108 | .atomic_begin = intel_begin_crtc_commit, |
10109 | .atomic_flush = intel_finish_crtc_commit, | |
f6e5b160 CW |
10110 | }; |
10111 | ||
9a935856 DV |
10112 | /** |
10113 | * intel_modeset_update_staged_output_state | |
10114 | * | |
10115 | * Updates the staged output configuration state, e.g. after we've read out the | |
10116 | * current hw state. | |
10117 | */ | |
10118 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) | |
f6e5b160 | 10119 | { |
7668851f | 10120 | struct intel_crtc *crtc; |
9a935856 DV |
10121 | struct intel_encoder *encoder; |
10122 | struct intel_connector *connector; | |
f6e5b160 | 10123 | |
3a3371ff | 10124 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
10125 | connector->new_encoder = |
10126 | to_intel_encoder(connector->base.encoder); | |
10127 | } | |
f6e5b160 | 10128 | |
b2784e15 | 10129 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
10130 | encoder->new_crtc = |
10131 | to_intel_crtc(encoder->base.crtc); | |
10132 | } | |
7668851f | 10133 | |
d3fcc808 | 10134 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 10135 | crtc->new_enabled = crtc->base.state->enable; |
7bd0a8e7 VS |
10136 | |
10137 | if (crtc->new_enabled) | |
6e3c9717 | 10138 | crtc->new_config = crtc->config; |
7bd0a8e7 VS |
10139 | else |
10140 | crtc->new_config = NULL; | |
7668851f | 10141 | } |
f6e5b160 CW |
10142 | } |
10143 | ||
9a935856 DV |
10144 | /** |
10145 | * intel_modeset_commit_output_state | |
10146 | * | |
10147 | * This function copies the stage display pipe configuration to the real one. | |
10148 | */ | |
10149 | static void intel_modeset_commit_output_state(struct drm_device *dev) | |
10150 | { | |
7668851f | 10151 | struct intel_crtc *crtc; |
9a935856 DV |
10152 | struct intel_encoder *encoder; |
10153 | struct intel_connector *connector; | |
f6e5b160 | 10154 | |
3a3371ff | 10155 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
10156 | connector->base.encoder = &connector->new_encoder->base; |
10157 | } | |
f6e5b160 | 10158 | |
b2784e15 | 10159 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
10160 | encoder->base.crtc = &encoder->new_crtc->base; |
10161 | } | |
7668851f | 10162 | |
d3fcc808 | 10163 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 10164 | crtc->base.state->enable = crtc->new_enabled; |
7668851f VS |
10165 | crtc->base.enabled = crtc->new_enabled; |
10166 | } | |
9a935856 DV |
10167 | } |
10168 | ||
050f7aeb | 10169 | static void |
eba905b2 | 10170 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 10171 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
10172 | { |
10173 | int bpp = pipe_config->pipe_bpp; | |
10174 | ||
10175 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
10176 | connector->base.base.id, | |
c23cc417 | 10177 | connector->base.name); |
050f7aeb DV |
10178 | |
10179 | /* Don't use an invalid EDID bpc value */ | |
10180 | if (connector->base.display_info.bpc && | |
10181 | connector->base.display_info.bpc * 3 < bpp) { | |
10182 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
10183 | bpp, connector->base.display_info.bpc*3); | |
10184 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
10185 | } | |
10186 | ||
10187 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
10188 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
10189 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
10190 | bpp); | |
10191 | pipe_config->pipe_bpp = 24; | |
10192 | } | |
10193 | } | |
10194 | ||
4e53c2e0 | 10195 | static int |
050f7aeb DV |
10196 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
10197 | struct drm_framebuffer *fb, | |
5cec258b | 10198 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 10199 | { |
050f7aeb DV |
10200 | struct drm_device *dev = crtc->base.dev; |
10201 | struct intel_connector *connector; | |
4e53c2e0 DV |
10202 | int bpp; |
10203 | ||
d42264b1 DV |
10204 | switch (fb->pixel_format) { |
10205 | case DRM_FORMAT_C8: | |
4e53c2e0 DV |
10206 | bpp = 8*3; /* since we go through a colormap */ |
10207 | break; | |
d42264b1 DV |
10208 | case DRM_FORMAT_XRGB1555: |
10209 | case DRM_FORMAT_ARGB1555: | |
10210 | /* checked in intel_framebuffer_init already */ | |
10211 | if (WARN_ON(INTEL_INFO(dev)->gen > 3)) | |
10212 | return -EINVAL; | |
10213 | case DRM_FORMAT_RGB565: | |
4e53c2e0 DV |
10214 | bpp = 6*3; /* min is 18bpp */ |
10215 | break; | |
d42264b1 DV |
10216 | case DRM_FORMAT_XBGR8888: |
10217 | case DRM_FORMAT_ABGR8888: | |
10218 | /* checked in intel_framebuffer_init already */ | |
10219 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
10220 | return -EINVAL; | |
10221 | case DRM_FORMAT_XRGB8888: | |
10222 | case DRM_FORMAT_ARGB8888: | |
4e53c2e0 DV |
10223 | bpp = 8*3; |
10224 | break; | |
d42264b1 DV |
10225 | case DRM_FORMAT_XRGB2101010: |
10226 | case DRM_FORMAT_ARGB2101010: | |
10227 | case DRM_FORMAT_XBGR2101010: | |
10228 | case DRM_FORMAT_ABGR2101010: | |
10229 | /* checked in intel_framebuffer_init already */ | |
10230 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
baba133a | 10231 | return -EINVAL; |
4e53c2e0 DV |
10232 | bpp = 10*3; |
10233 | break; | |
baba133a | 10234 | /* TODO: gen4+ supports 16 bpc floating point, too. */ |
4e53c2e0 DV |
10235 | default: |
10236 | DRM_DEBUG_KMS("unsupported depth\n"); | |
10237 | return -EINVAL; | |
10238 | } | |
10239 | ||
4e53c2e0 DV |
10240 | pipe_config->pipe_bpp = bpp; |
10241 | ||
10242 | /* Clamp display bpp to EDID value */ | |
3a3371ff | 10243 | for_each_intel_connector(dev, connector) { |
1b829e05 DV |
10244 | if (!connector->new_encoder || |
10245 | connector->new_encoder->new_crtc != crtc) | |
4e53c2e0 DV |
10246 | continue; |
10247 | ||
050f7aeb | 10248 | connected_sink_compute_bpp(connector, pipe_config); |
4e53c2e0 DV |
10249 | } |
10250 | ||
10251 | return bpp; | |
10252 | } | |
10253 | ||
644db711 DV |
10254 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
10255 | { | |
10256 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
10257 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 10258 | mode->crtc_clock, |
644db711 DV |
10259 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
10260 | mode->crtc_hsync_end, mode->crtc_htotal, | |
10261 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
10262 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
10263 | } | |
10264 | ||
c0b03411 | 10265 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 10266 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
10267 | const char *context) |
10268 | { | |
10269 | DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id, | |
10270 | context, pipe_name(crtc->pipe)); | |
10271 | ||
10272 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
10273 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
10274 | pipe_config->pipe_bpp, pipe_config->dither); | |
10275 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
10276 | pipe_config->has_pch_encoder, | |
10277 | pipe_config->fdi_lanes, | |
10278 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
10279 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
10280 | pipe_config->fdi_m_n.tu); | |
eb14cb74 VS |
10281 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
10282 | pipe_config->has_dp_encoder, | |
10283 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, | |
10284 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
10285 | pipe_config->dp_m_n.tu); | |
b95af8be VK |
10286 | |
10287 | DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", | |
10288 | pipe_config->has_dp_encoder, | |
10289 | pipe_config->dp_m2_n2.gmch_m, | |
10290 | pipe_config->dp_m2_n2.gmch_n, | |
10291 | pipe_config->dp_m2_n2.link_m, | |
10292 | pipe_config->dp_m2_n2.link_n, | |
10293 | pipe_config->dp_m2_n2.tu); | |
10294 | ||
55072d19 DV |
10295 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
10296 | pipe_config->has_audio, | |
10297 | pipe_config->has_infoframe); | |
10298 | ||
c0b03411 | 10299 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 10300 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 10301 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
10302 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
10303 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 10304 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
10305 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
10306 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
c0b03411 DV |
10307 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
10308 | pipe_config->gmch_pfit.control, | |
10309 | pipe_config->gmch_pfit.pgm_ratios, | |
10310 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 10311 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 10312 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
10313 | pipe_config->pch_pfit.size, |
10314 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 10315 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 10316 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
c0b03411 DV |
10317 | } |
10318 | ||
bc079e8b VS |
10319 | static bool encoders_cloneable(const struct intel_encoder *a, |
10320 | const struct intel_encoder *b) | |
accfc0c5 | 10321 | { |
bc079e8b VS |
10322 | /* masks could be asymmetric, so check both ways */ |
10323 | return a == b || (a->cloneable & (1 << b->type) && | |
10324 | b->cloneable & (1 << a->type)); | |
10325 | } | |
10326 | ||
10327 | static bool check_single_encoder_cloning(struct intel_crtc *crtc, | |
10328 | struct intel_encoder *encoder) | |
10329 | { | |
10330 | struct drm_device *dev = crtc->base.dev; | |
10331 | struct intel_encoder *source_encoder; | |
10332 | ||
b2784e15 | 10333 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b VS |
10334 | if (source_encoder->new_crtc != crtc) |
10335 | continue; | |
10336 | ||
10337 | if (!encoders_cloneable(encoder, source_encoder)) | |
10338 | return false; | |
10339 | } | |
10340 | ||
10341 | return true; | |
10342 | } | |
10343 | ||
10344 | static bool check_encoder_cloning(struct intel_crtc *crtc) | |
10345 | { | |
10346 | struct drm_device *dev = crtc->base.dev; | |
accfc0c5 DV |
10347 | struct intel_encoder *encoder; |
10348 | ||
b2784e15 | 10349 | for_each_intel_encoder(dev, encoder) { |
bc079e8b | 10350 | if (encoder->new_crtc != crtc) |
accfc0c5 DV |
10351 | continue; |
10352 | ||
bc079e8b VS |
10353 | if (!check_single_encoder_cloning(crtc, encoder)) |
10354 | return false; | |
accfc0c5 DV |
10355 | } |
10356 | ||
bc079e8b | 10357 | return true; |
accfc0c5 DV |
10358 | } |
10359 | ||
00f0b378 VS |
10360 | static bool check_digital_port_conflicts(struct drm_device *dev) |
10361 | { | |
10362 | struct intel_connector *connector; | |
10363 | unsigned int used_ports = 0; | |
10364 | ||
10365 | /* | |
10366 | * Walk the connector list instead of the encoder | |
10367 | * list to detect the problem on ddi platforms | |
10368 | * where there's just one encoder per digital port. | |
10369 | */ | |
3a3371ff | 10370 | for_each_intel_connector(dev, connector) { |
00f0b378 VS |
10371 | struct intel_encoder *encoder = connector->new_encoder; |
10372 | ||
10373 | if (!encoder) | |
10374 | continue; | |
10375 | ||
10376 | WARN_ON(!encoder->new_crtc); | |
10377 | ||
10378 | switch (encoder->type) { | |
10379 | unsigned int port_mask; | |
10380 | case INTEL_OUTPUT_UNKNOWN: | |
10381 | if (WARN_ON(!HAS_DDI(dev))) | |
10382 | break; | |
10383 | case INTEL_OUTPUT_DISPLAYPORT: | |
10384 | case INTEL_OUTPUT_HDMI: | |
10385 | case INTEL_OUTPUT_EDP: | |
10386 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
10387 | ||
10388 | /* the same port mustn't appear more than once */ | |
10389 | if (used_ports & port_mask) | |
10390 | return false; | |
10391 | ||
10392 | used_ports |= port_mask; | |
10393 | default: | |
10394 | break; | |
10395 | } | |
10396 | } | |
10397 | ||
10398 | return true; | |
10399 | } | |
10400 | ||
5cec258b | 10401 | static struct intel_crtc_state * |
b8cecdf5 | 10402 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
4e53c2e0 | 10403 | struct drm_framebuffer *fb, |
b8cecdf5 | 10404 | struct drm_display_mode *mode) |
ee7b9f93 | 10405 | { |
7758a113 | 10406 | struct drm_device *dev = crtc->dev; |
7758a113 | 10407 | struct intel_encoder *encoder; |
5cec258b | 10408 | struct intel_crtc_state *pipe_config; |
e29c22c0 DV |
10409 | int plane_bpp, ret = -EINVAL; |
10410 | bool retry = true; | |
ee7b9f93 | 10411 | |
bc079e8b | 10412 | if (!check_encoder_cloning(to_intel_crtc(crtc))) { |
accfc0c5 DV |
10413 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
10414 | return ERR_PTR(-EINVAL); | |
10415 | } | |
10416 | ||
00f0b378 VS |
10417 | if (!check_digital_port_conflicts(dev)) { |
10418 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
10419 | return ERR_PTR(-EINVAL); | |
10420 | } | |
10421 | ||
b8cecdf5 DV |
10422 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
10423 | if (!pipe_config) | |
7758a113 DV |
10424 | return ERR_PTR(-ENOMEM); |
10425 | ||
07878248 | 10426 | pipe_config->base.crtc = crtc; |
2d112de7 ACO |
10427 | drm_mode_copy(&pipe_config->base.adjusted_mode, mode); |
10428 | drm_mode_copy(&pipe_config->base.mode, mode); | |
37327abd | 10429 | |
e143a21c DV |
10430 | pipe_config->cpu_transcoder = |
10431 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
c0d43d62 | 10432 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
b8cecdf5 | 10433 | |
2960bc9c ID |
10434 | /* |
10435 | * Sanitize sync polarity flags based on requested ones. If neither | |
10436 | * positive or negative polarity is requested, treat this as meaning | |
10437 | * negative polarity. | |
10438 | */ | |
2d112de7 | 10439 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 10440 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 10441 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 10442 | |
2d112de7 | 10443 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 10444 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 10445 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 10446 | |
050f7aeb DV |
10447 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
10448 | * plane pixel format and any sink constraints into account. Returns the | |
10449 | * source plane bpp so that dithering can be selected on mismatches | |
10450 | * after encoders and crtc also have had their say. */ | |
10451 | plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), | |
10452 | fb, pipe_config); | |
4e53c2e0 DV |
10453 | if (plane_bpp < 0) |
10454 | goto fail; | |
10455 | ||
e41a56be VS |
10456 | /* |
10457 | * Determine the real pipe dimensions. Note that stereo modes can | |
10458 | * increase the actual pipe size due to the frame doubling and | |
10459 | * insertion of additional space for blanks between the frame. This | |
10460 | * is stored in the crtc timings. We use the requested mode to do this | |
10461 | * computation to clearly distinguish it from the adjusted mode, which | |
10462 | * can be changed by the connectors in the below retry loop. | |
10463 | */ | |
2d112de7 | 10464 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
10465 | &pipe_config->pipe_src_w, |
10466 | &pipe_config->pipe_src_h); | |
e41a56be | 10467 | |
e29c22c0 | 10468 | encoder_retry: |
ef1b460d | 10469 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 10470 | pipe_config->port_clock = 0; |
ef1b460d | 10471 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 10472 | |
135c81b8 | 10473 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
10474 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
10475 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 10476 | |
7758a113 DV |
10477 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
10478 | * adjust it according to limitations or connector properties, and also | |
10479 | * a chance to reject the mode entirely. | |
47f1c6c9 | 10480 | */ |
b2784e15 | 10481 | for_each_intel_encoder(dev, encoder) { |
47f1c6c9 | 10482 | |
7758a113 DV |
10483 | if (&encoder->new_crtc->base != crtc) |
10484 | continue; | |
7ae89233 | 10485 | |
efea6e8e DV |
10486 | if (!(encoder->compute_config(encoder, pipe_config))) { |
10487 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
10488 | goto fail; |
10489 | } | |
ee7b9f93 | 10490 | } |
47f1c6c9 | 10491 | |
ff9a6750 DV |
10492 | /* Set default port clock if not overwritten by the encoder. Needs to be |
10493 | * done afterwards in case the encoder adjusts the mode. */ | |
10494 | if (!pipe_config->port_clock) | |
2d112de7 | 10495 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 10496 | * pipe_config->pixel_multiplier; |
ff9a6750 | 10497 | |
a43f6e0f | 10498 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 10499 | if (ret < 0) { |
7758a113 DV |
10500 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
10501 | goto fail; | |
ee7b9f93 | 10502 | } |
e29c22c0 DV |
10503 | |
10504 | if (ret == RETRY) { | |
10505 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
10506 | ret = -EINVAL; | |
10507 | goto fail; | |
10508 | } | |
10509 | ||
10510 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
10511 | retry = false; | |
10512 | goto encoder_retry; | |
10513 | } | |
10514 | ||
4e53c2e0 DV |
10515 | pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; |
10516 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", | |
10517 | plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); | |
10518 | ||
b8cecdf5 | 10519 | return pipe_config; |
7758a113 | 10520 | fail: |
b8cecdf5 | 10521 | kfree(pipe_config); |
e29c22c0 | 10522 | return ERR_PTR(ret); |
ee7b9f93 | 10523 | } |
47f1c6c9 | 10524 | |
e2e1ed41 DV |
10525 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
10526 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ | |
10527 | static void | |
10528 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, | |
10529 | unsigned *prepare_pipes, unsigned *disable_pipes) | |
79e53945 JB |
10530 | { |
10531 | struct intel_crtc *intel_crtc; | |
e2e1ed41 DV |
10532 | struct drm_device *dev = crtc->dev; |
10533 | struct intel_encoder *encoder; | |
10534 | struct intel_connector *connector; | |
10535 | struct drm_crtc *tmp_crtc; | |
79e53945 | 10536 | |
e2e1ed41 | 10537 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
79e53945 | 10538 | |
e2e1ed41 DV |
10539 | /* Check which crtcs have changed outputs connected to them, these need |
10540 | * to be part of the prepare_pipes mask. We don't (yet) support global | |
10541 | * modeset across multiple crtcs, so modeset_pipes will only have one | |
10542 | * bit set at most. */ | |
3a3371ff | 10543 | for_each_intel_connector(dev, connector) { |
e2e1ed41 DV |
10544 | if (connector->base.encoder == &connector->new_encoder->base) |
10545 | continue; | |
79e53945 | 10546 | |
e2e1ed41 DV |
10547 | if (connector->base.encoder) { |
10548 | tmp_crtc = connector->base.encoder->crtc; | |
10549 | ||
10550 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
10551 | } | |
10552 | ||
10553 | if (connector->new_encoder) | |
10554 | *prepare_pipes |= | |
10555 | 1 << connector->new_encoder->new_crtc->pipe; | |
79e53945 JB |
10556 | } |
10557 | ||
b2784e15 | 10558 | for_each_intel_encoder(dev, encoder) { |
e2e1ed41 DV |
10559 | if (encoder->base.crtc == &encoder->new_crtc->base) |
10560 | continue; | |
10561 | ||
10562 | if (encoder->base.crtc) { | |
10563 | tmp_crtc = encoder->base.crtc; | |
10564 | ||
10565 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
10566 | } | |
10567 | ||
10568 | if (encoder->new_crtc) | |
10569 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; | |
80824003 JB |
10570 | } |
10571 | ||
7668851f | 10572 | /* Check for pipes that will be enabled/disabled ... */ |
d3fcc808 | 10573 | for_each_intel_crtc(dev, intel_crtc) { |
83d65738 | 10574 | if (intel_crtc->base.state->enable == intel_crtc->new_enabled) |
e2e1ed41 | 10575 | continue; |
7e7d76c3 | 10576 | |
7668851f | 10577 | if (!intel_crtc->new_enabled) |
e2e1ed41 | 10578 | *disable_pipes |= 1 << intel_crtc->pipe; |
7668851f VS |
10579 | else |
10580 | *prepare_pipes |= 1 << intel_crtc->pipe; | |
7e7d76c3 JB |
10581 | } |
10582 | ||
e2e1ed41 DV |
10583 | |
10584 | /* set_mode is also used to update properties on life display pipes. */ | |
10585 | intel_crtc = to_intel_crtc(crtc); | |
7668851f | 10586 | if (intel_crtc->new_enabled) |
e2e1ed41 DV |
10587 | *prepare_pipes |= 1 << intel_crtc->pipe; |
10588 | ||
b6c5164d DV |
10589 | /* |
10590 | * For simplicity do a full modeset on any pipe where the output routing | |
10591 | * changed. We could be more clever, but that would require us to be | |
10592 | * more careful with calling the relevant encoder->mode_set functions. | |
10593 | */ | |
e2e1ed41 DV |
10594 | if (*prepare_pipes) |
10595 | *modeset_pipes = *prepare_pipes; | |
10596 | ||
10597 | /* ... and mask these out. */ | |
10598 | *modeset_pipes &= ~(*disable_pipes); | |
10599 | *prepare_pipes &= ~(*disable_pipes); | |
b6c5164d DV |
10600 | |
10601 | /* | |
10602 | * HACK: We don't (yet) fully support global modesets. intel_set_config | |
10603 | * obies this rule, but the modeset restore mode of | |
10604 | * intel_modeset_setup_hw_state does not. | |
10605 | */ | |
10606 | *modeset_pipes &= 1 << intel_crtc->pipe; | |
10607 | *prepare_pipes &= 1 << intel_crtc->pipe; | |
e3641d3f DV |
10608 | |
10609 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", | |
10610 | *modeset_pipes, *prepare_pipes, *disable_pipes); | |
47f1c6c9 | 10611 | } |
79e53945 | 10612 | |
ea9d758d | 10613 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 10614 | { |
ea9d758d | 10615 | struct drm_encoder *encoder; |
f6e5b160 | 10616 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 10617 | |
ea9d758d DV |
10618 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
10619 | if (encoder->crtc == crtc) | |
10620 | return true; | |
10621 | ||
10622 | return false; | |
10623 | } | |
10624 | ||
10625 | static void | |
10626 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) | |
10627 | { | |
ba41c0de | 10628 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea9d758d DV |
10629 | struct intel_encoder *intel_encoder; |
10630 | struct intel_crtc *intel_crtc; | |
10631 | struct drm_connector *connector; | |
10632 | ||
ba41c0de DV |
10633 | intel_shared_dpll_commit(dev_priv); |
10634 | ||
b2784e15 | 10635 | for_each_intel_encoder(dev, intel_encoder) { |
ea9d758d DV |
10636 | if (!intel_encoder->base.crtc) |
10637 | continue; | |
10638 | ||
10639 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
10640 | ||
10641 | if (prepare_pipes & (1 << intel_crtc->pipe)) | |
10642 | intel_encoder->connectors_active = false; | |
10643 | } | |
10644 | ||
10645 | intel_modeset_commit_output_state(dev); | |
10646 | ||
7668851f | 10647 | /* Double check state. */ |
d3fcc808 | 10648 | for_each_intel_crtc(dev, intel_crtc) { |
83d65738 | 10649 | WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base)); |
7bd0a8e7 | 10650 | WARN_ON(intel_crtc->new_config && |
6e3c9717 | 10651 | intel_crtc->new_config != intel_crtc->config); |
83d65738 | 10652 | WARN_ON(intel_crtc->base.state->enable != !!intel_crtc->new_config); |
ea9d758d DV |
10653 | } |
10654 | ||
10655 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
10656 | if (!connector->encoder || !connector->encoder->crtc) | |
10657 | continue; | |
10658 | ||
10659 | intel_crtc = to_intel_crtc(connector->encoder->crtc); | |
10660 | ||
10661 | if (prepare_pipes & (1 << intel_crtc->pipe)) { | |
68d34720 DV |
10662 | struct drm_property *dpms_property = |
10663 | dev->mode_config.dpms_property; | |
10664 | ||
ea9d758d | 10665 | connector->dpms = DRM_MODE_DPMS_ON; |
662595df | 10666 | drm_object_property_set_value(&connector->base, |
68d34720 DV |
10667 | dpms_property, |
10668 | DRM_MODE_DPMS_ON); | |
ea9d758d DV |
10669 | |
10670 | intel_encoder = to_intel_encoder(connector->encoder); | |
10671 | intel_encoder->connectors_active = true; | |
10672 | } | |
10673 | } | |
10674 | ||
10675 | } | |
10676 | ||
3bd26263 | 10677 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 10678 | { |
3bd26263 | 10679 | int diff; |
f1f644dc JB |
10680 | |
10681 | if (clock1 == clock2) | |
10682 | return true; | |
10683 | ||
10684 | if (!clock1 || !clock2) | |
10685 | return false; | |
10686 | ||
10687 | diff = abs(clock1 - clock2); | |
10688 | ||
10689 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
10690 | return true; | |
10691 | ||
10692 | return false; | |
10693 | } | |
10694 | ||
25c5b266 DV |
10695 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
10696 | list_for_each_entry((intel_crtc), \ | |
10697 | &(dev)->mode_config.crtc_list, \ | |
10698 | base.head) \ | |
0973f18f | 10699 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 10700 | |
0e8ffe1b | 10701 | static bool |
2fa2fe9a | 10702 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b ACO |
10703 | struct intel_crtc_state *current_config, |
10704 | struct intel_crtc_state *pipe_config) | |
0e8ffe1b | 10705 | { |
66e985c0 DV |
10706 | #define PIPE_CONF_CHECK_X(name) \ |
10707 | if (current_config->name != pipe_config->name) { \ | |
10708 | DRM_ERROR("mismatch in " #name " " \ | |
10709 | "(expected 0x%08x, found 0x%08x)\n", \ | |
10710 | current_config->name, \ | |
10711 | pipe_config->name); \ | |
10712 | return false; \ | |
10713 | } | |
10714 | ||
08a24034 DV |
10715 | #define PIPE_CONF_CHECK_I(name) \ |
10716 | if (current_config->name != pipe_config->name) { \ | |
10717 | DRM_ERROR("mismatch in " #name " " \ | |
10718 | "(expected %i, found %i)\n", \ | |
10719 | current_config->name, \ | |
10720 | pipe_config->name); \ | |
10721 | return false; \ | |
88adfff1 DV |
10722 | } |
10723 | ||
b95af8be VK |
10724 | /* This is required for BDW+ where there is only one set of registers for |
10725 | * switching between high and low RR. | |
10726 | * This macro can be used whenever a comparison has to be made between one | |
10727 | * hw state and multiple sw state variables. | |
10728 | */ | |
10729 | #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ | |
10730 | if ((current_config->name != pipe_config->name) && \ | |
10731 | (current_config->alt_name != pipe_config->name)) { \ | |
10732 | DRM_ERROR("mismatch in " #name " " \ | |
10733 | "(expected %i or %i, found %i)\n", \ | |
10734 | current_config->name, \ | |
10735 | current_config->alt_name, \ | |
10736 | pipe_config->name); \ | |
10737 | return false; \ | |
10738 | } | |
10739 | ||
1bd1bd80 DV |
10740 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
10741 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
6f02488e | 10742 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
10743 | "(expected %i, found %i)\n", \ |
10744 | current_config->name & (mask), \ | |
10745 | pipe_config->name & (mask)); \ | |
10746 | return false; \ | |
10747 | } | |
10748 | ||
5e550656 VS |
10749 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
10750 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
10751 | DRM_ERROR("mismatch in " #name " " \ | |
10752 | "(expected %i, found %i)\n", \ | |
10753 | current_config->name, \ | |
10754 | pipe_config->name); \ | |
10755 | return false; \ | |
10756 | } | |
10757 | ||
bb760063 DV |
10758 | #define PIPE_CONF_QUIRK(quirk) \ |
10759 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
10760 | ||
eccb140b DV |
10761 | PIPE_CONF_CHECK_I(cpu_transcoder); |
10762 | ||
08a24034 DV |
10763 | PIPE_CONF_CHECK_I(has_pch_encoder); |
10764 | PIPE_CONF_CHECK_I(fdi_lanes); | |
72419203 DV |
10765 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
10766 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); | |
10767 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); | |
10768 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); | |
10769 | PIPE_CONF_CHECK_I(fdi_m_n.tu); | |
08a24034 | 10770 | |
eb14cb74 | 10771 | PIPE_CONF_CHECK_I(has_dp_encoder); |
b95af8be VK |
10772 | |
10773 | if (INTEL_INFO(dev)->gen < 8) { | |
10774 | PIPE_CONF_CHECK_I(dp_m_n.gmch_m); | |
10775 | PIPE_CONF_CHECK_I(dp_m_n.gmch_n); | |
10776 | PIPE_CONF_CHECK_I(dp_m_n.link_m); | |
10777 | PIPE_CONF_CHECK_I(dp_m_n.link_n); | |
10778 | PIPE_CONF_CHECK_I(dp_m_n.tu); | |
10779 | ||
10780 | if (current_config->has_drrs) { | |
10781 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m); | |
10782 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n); | |
10783 | PIPE_CONF_CHECK_I(dp_m2_n2.link_m); | |
10784 | PIPE_CONF_CHECK_I(dp_m2_n2.link_n); | |
10785 | PIPE_CONF_CHECK_I(dp_m2_n2.tu); | |
10786 | } | |
10787 | } else { | |
10788 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m); | |
10789 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n); | |
10790 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m); | |
10791 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n); | |
10792 | PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu); | |
10793 | } | |
eb14cb74 | 10794 | |
2d112de7 ACO |
10795 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
10796 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
10797 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
10798 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
10799 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
10800 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 10801 | |
2d112de7 ACO |
10802 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
10803 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
10804 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
10805 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
10806 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
10807 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 10808 | |
c93f54cf | 10809 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 10810 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 DV |
10811 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
10812 | IS_VALLEYVIEW(dev)) | |
10813 | PIPE_CONF_CHECK_I(limited_color_range); | |
e43823ec | 10814 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 10815 | |
9ed109a7 DV |
10816 | PIPE_CONF_CHECK_I(has_audio); |
10817 | ||
2d112de7 | 10818 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
10819 | DRM_MODE_FLAG_INTERLACE); |
10820 | ||
bb760063 | 10821 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 10822 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 10823 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 10824 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 10825 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 10826 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 10827 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 10828 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
10829 | DRM_MODE_FLAG_NVSYNC); |
10830 | } | |
045ac3b5 | 10831 | |
37327abd VS |
10832 | PIPE_CONF_CHECK_I(pipe_src_w); |
10833 | PIPE_CONF_CHECK_I(pipe_src_h); | |
1bd1bd80 | 10834 | |
9953599b DV |
10835 | /* |
10836 | * FIXME: BIOS likes to set up a cloned config with lvds+external | |
10837 | * screen. Since we don't yet re-compute the pipe config when moving | |
10838 | * just the lvds port away to another pipe the sw tracking won't match. | |
10839 | * | |
10840 | * Proper atomic modesets with recomputed global state will fix this. | |
10841 | * Until then just don't check gmch state for inherited modes. | |
10842 | */ | |
10843 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) { | |
10844 | PIPE_CONF_CHECK_I(gmch_pfit.control); | |
10845 | /* pfit ratios are autocomputed by the hw on gen4+ */ | |
10846 | if (INTEL_INFO(dev)->gen < 4) | |
10847 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
10848 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); | |
10849 | } | |
10850 | ||
fd4daa9c CW |
10851 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
10852 | if (current_config->pch_pfit.enabled) { | |
10853 | PIPE_CONF_CHECK_I(pch_pfit.pos); | |
10854 | PIPE_CONF_CHECK_I(pch_pfit.size); | |
10855 | } | |
2fa2fe9a | 10856 | |
e59150dc JB |
10857 | /* BDW+ don't expose a synchronous way to read the state */ |
10858 | if (IS_HASWELL(dev)) | |
10859 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 10860 | |
282740f7 VS |
10861 | PIPE_CONF_CHECK_I(double_wide); |
10862 | ||
26804afd DV |
10863 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
10864 | ||
c0d43d62 | 10865 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 10866 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 10867 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
10868 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
10869 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 10870 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
3f4cd19f DL |
10871 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
10872 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
10873 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 10874 | |
42571aef VS |
10875 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
10876 | PIPE_CONF_CHECK_I(pipe_bpp); | |
10877 | ||
2d112de7 | 10878 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 10879 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 10880 | |
66e985c0 | 10881 | #undef PIPE_CONF_CHECK_X |
08a24034 | 10882 | #undef PIPE_CONF_CHECK_I |
b95af8be | 10883 | #undef PIPE_CONF_CHECK_I_ALT |
1bd1bd80 | 10884 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 10885 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 10886 | #undef PIPE_CONF_QUIRK |
88adfff1 | 10887 | |
0e8ffe1b DV |
10888 | return true; |
10889 | } | |
10890 | ||
08db6652 DL |
10891 | static void check_wm_state(struct drm_device *dev) |
10892 | { | |
10893 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10894 | struct skl_ddb_allocation hw_ddb, *sw_ddb; | |
10895 | struct intel_crtc *intel_crtc; | |
10896 | int plane; | |
10897 | ||
10898 | if (INTEL_INFO(dev)->gen < 9) | |
10899 | return; | |
10900 | ||
10901 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
10902 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
10903 | ||
10904 | for_each_intel_crtc(dev, intel_crtc) { | |
10905 | struct skl_ddb_entry *hw_entry, *sw_entry; | |
10906 | const enum pipe pipe = intel_crtc->pipe; | |
10907 | ||
10908 | if (!intel_crtc->active) | |
10909 | continue; | |
10910 | ||
10911 | /* planes */ | |
dd740780 | 10912 | for_each_plane(dev_priv, pipe, plane) { |
08db6652 DL |
10913 | hw_entry = &hw_ddb.plane[pipe][plane]; |
10914 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
10915 | ||
10916 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
10917 | continue; | |
10918 | ||
10919 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " | |
10920 | "(expected (%u,%u), found (%u,%u))\n", | |
10921 | pipe_name(pipe), plane + 1, | |
10922 | sw_entry->start, sw_entry->end, | |
10923 | hw_entry->start, hw_entry->end); | |
10924 | } | |
10925 | ||
10926 | /* cursor */ | |
10927 | hw_entry = &hw_ddb.cursor[pipe]; | |
10928 | sw_entry = &sw_ddb->cursor[pipe]; | |
10929 | ||
10930 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
10931 | continue; | |
10932 | ||
10933 | DRM_ERROR("mismatch in DDB state pipe %c cursor " | |
10934 | "(expected (%u,%u), found (%u,%u))\n", | |
10935 | pipe_name(pipe), | |
10936 | sw_entry->start, sw_entry->end, | |
10937 | hw_entry->start, hw_entry->end); | |
10938 | } | |
10939 | } | |
10940 | ||
91d1b4bd DV |
10941 | static void |
10942 | check_connector_state(struct drm_device *dev) | |
8af6cf88 | 10943 | { |
8af6cf88 DV |
10944 | struct intel_connector *connector; |
10945 | ||
3a3371ff | 10946 | for_each_intel_connector(dev, connector) { |
8af6cf88 DV |
10947 | /* This also checks the encoder/connector hw state with the |
10948 | * ->get_hw_state callbacks. */ | |
10949 | intel_connector_check_state(connector); | |
10950 | ||
e2c719b7 | 10951 | I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder, |
8af6cf88 DV |
10952 | "connector's staged encoder doesn't match current encoder\n"); |
10953 | } | |
91d1b4bd DV |
10954 | } |
10955 | ||
10956 | static void | |
10957 | check_encoder_state(struct drm_device *dev) | |
10958 | { | |
10959 | struct intel_encoder *encoder; | |
10960 | struct intel_connector *connector; | |
8af6cf88 | 10961 | |
b2784e15 | 10962 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 DV |
10963 | bool enabled = false; |
10964 | bool active = false; | |
10965 | enum pipe pipe, tracked_pipe; | |
10966 | ||
10967 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
10968 | encoder->base.base.id, | |
8e329a03 | 10969 | encoder->base.name); |
8af6cf88 | 10970 | |
e2c719b7 | 10971 | I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc, |
8af6cf88 | 10972 | "encoder's stage crtc doesn't match current crtc\n"); |
e2c719b7 | 10973 | I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc, |
8af6cf88 DV |
10974 | "encoder's active_connectors set, but no crtc\n"); |
10975 | ||
3a3371ff | 10976 | for_each_intel_connector(dev, connector) { |
8af6cf88 DV |
10977 | if (connector->base.encoder != &encoder->base) |
10978 | continue; | |
10979 | enabled = true; | |
10980 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
10981 | active = true; | |
10982 | } | |
0e32b39c DA |
10983 | /* |
10984 | * for MST connectors if we unplug the connector is gone | |
10985 | * away but the encoder is still connected to a crtc | |
10986 | * until a modeset happens in response to the hotplug. | |
10987 | */ | |
10988 | if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST) | |
10989 | continue; | |
10990 | ||
e2c719b7 | 10991 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
10992 | "encoder's enabled state mismatch " |
10993 | "(expected %i, found %i)\n", | |
10994 | !!encoder->base.crtc, enabled); | |
e2c719b7 | 10995 | I915_STATE_WARN(active && !encoder->base.crtc, |
8af6cf88 DV |
10996 | "active encoder with no crtc\n"); |
10997 | ||
e2c719b7 | 10998 | I915_STATE_WARN(encoder->connectors_active != active, |
8af6cf88 DV |
10999 | "encoder's computed active state doesn't match tracked active state " |
11000 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
11001 | ||
11002 | active = encoder->get_hw_state(encoder, &pipe); | |
e2c719b7 | 11003 | I915_STATE_WARN(active != encoder->connectors_active, |
8af6cf88 DV |
11004 | "encoder's hw state doesn't match sw tracking " |
11005 | "(expected %i, found %i)\n", | |
11006 | encoder->connectors_active, active); | |
11007 | ||
11008 | if (!encoder->base.crtc) | |
11009 | continue; | |
11010 | ||
11011 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
e2c719b7 | 11012 | I915_STATE_WARN(active && pipe != tracked_pipe, |
8af6cf88 DV |
11013 | "active encoder's pipe doesn't match" |
11014 | "(expected %i, found %i)\n", | |
11015 | tracked_pipe, pipe); | |
11016 | ||
11017 | } | |
91d1b4bd DV |
11018 | } |
11019 | ||
11020 | static void | |
11021 | check_crtc_state(struct drm_device *dev) | |
11022 | { | |
fbee40df | 11023 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
11024 | struct intel_crtc *crtc; |
11025 | struct intel_encoder *encoder; | |
5cec258b | 11026 | struct intel_crtc_state pipe_config; |
8af6cf88 | 11027 | |
d3fcc808 | 11028 | for_each_intel_crtc(dev, crtc) { |
8af6cf88 DV |
11029 | bool enabled = false; |
11030 | bool active = false; | |
11031 | ||
045ac3b5 JB |
11032 | memset(&pipe_config, 0, sizeof(pipe_config)); |
11033 | ||
8af6cf88 DV |
11034 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
11035 | crtc->base.base.id); | |
11036 | ||
83d65738 | 11037 | I915_STATE_WARN(crtc->active && !crtc->base.state->enable, |
8af6cf88 DV |
11038 | "active crtc, but not enabled in sw tracking\n"); |
11039 | ||
b2784e15 | 11040 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 DV |
11041 | if (encoder->base.crtc != &crtc->base) |
11042 | continue; | |
11043 | enabled = true; | |
11044 | if (encoder->connectors_active) | |
11045 | active = true; | |
11046 | } | |
6c49f241 | 11047 | |
e2c719b7 | 11048 | I915_STATE_WARN(active != crtc->active, |
8af6cf88 DV |
11049 | "crtc's computed active state doesn't match tracked active state " |
11050 | "(expected %i, found %i)\n", active, crtc->active); | |
83d65738 | 11051 | I915_STATE_WARN(enabled != crtc->base.state->enable, |
8af6cf88 | 11052 | "crtc's computed enabled state doesn't match tracked enabled state " |
83d65738 MR |
11053 | "(expected %i, found %i)\n", enabled, |
11054 | crtc->base.state->enable); | |
8af6cf88 | 11055 | |
0e8ffe1b DV |
11056 | active = dev_priv->display.get_pipe_config(crtc, |
11057 | &pipe_config); | |
d62cf62a | 11058 | |
b6b5d049 VS |
11059 | /* hw state is inconsistent with the pipe quirk */ |
11060 | if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
11061 | (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
d62cf62a DV |
11062 | active = crtc->active; |
11063 | ||
b2784e15 | 11064 | for_each_intel_encoder(dev, encoder) { |
3eaba51c | 11065 | enum pipe pipe; |
6c49f241 DV |
11066 | if (encoder->base.crtc != &crtc->base) |
11067 | continue; | |
1d37b689 | 11068 | if (encoder->get_hw_state(encoder, &pipe)) |
6c49f241 DV |
11069 | encoder->get_config(encoder, &pipe_config); |
11070 | } | |
11071 | ||
e2c719b7 | 11072 | I915_STATE_WARN(crtc->active != active, |
0e8ffe1b DV |
11073 | "crtc active state doesn't match with hw state " |
11074 | "(expected %i, found %i)\n", crtc->active, active); | |
11075 | ||
c0b03411 | 11076 | if (active && |
6e3c9717 | 11077 | !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) { |
e2c719b7 | 11078 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); |
c0b03411 DV |
11079 | intel_dump_pipe_config(crtc, &pipe_config, |
11080 | "[hw state]"); | |
6e3c9717 | 11081 | intel_dump_pipe_config(crtc, crtc->config, |
c0b03411 DV |
11082 | "[sw state]"); |
11083 | } | |
8af6cf88 DV |
11084 | } |
11085 | } | |
11086 | ||
91d1b4bd DV |
11087 | static void |
11088 | check_shared_dpll_state(struct drm_device *dev) | |
11089 | { | |
fbee40df | 11090 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
11091 | struct intel_crtc *crtc; |
11092 | struct intel_dpll_hw_state dpll_hw_state; | |
11093 | int i; | |
5358901f DV |
11094 | |
11095 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
11096 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
11097 | int enabled_crtcs = 0, active_crtcs = 0; | |
11098 | bool active; | |
11099 | ||
11100 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
11101 | ||
11102 | DRM_DEBUG_KMS("%s\n", pll->name); | |
11103 | ||
11104 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
11105 | ||
e2c719b7 | 11106 | I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask), |
5358901f | 11107 | "more active pll users than references: %i vs %i\n", |
3e369b76 | 11108 | pll->active, hweight32(pll->config.crtc_mask)); |
e2c719b7 | 11109 | I915_STATE_WARN(pll->active && !pll->on, |
5358901f | 11110 | "pll in active use but not on in sw tracking\n"); |
e2c719b7 | 11111 | I915_STATE_WARN(pll->on && !pll->active, |
35c95375 | 11112 | "pll in on but not on in use in sw tracking\n"); |
e2c719b7 | 11113 | I915_STATE_WARN(pll->on != active, |
5358901f DV |
11114 | "pll on state mismatch (expected %i, found %i)\n", |
11115 | pll->on, active); | |
11116 | ||
d3fcc808 | 11117 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 11118 | if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll) |
5358901f DV |
11119 | enabled_crtcs++; |
11120 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
11121 | active_crtcs++; | |
11122 | } | |
e2c719b7 | 11123 | I915_STATE_WARN(pll->active != active_crtcs, |
5358901f DV |
11124 | "pll active crtcs mismatch (expected %i, found %i)\n", |
11125 | pll->active, active_crtcs); | |
e2c719b7 | 11126 | I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs, |
5358901f | 11127 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
3e369b76 | 11128 | hweight32(pll->config.crtc_mask), enabled_crtcs); |
66e985c0 | 11129 | |
e2c719b7 | 11130 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state, |
66e985c0 DV |
11131 | sizeof(dpll_hw_state)), |
11132 | "pll hw state mismatch\n"); | |
5358901f | 11133 | } |
8af6cf88 DV |
11134 | } |
11135 | ||
91d1b4bd DV |
11136 | void |
11137 | intel_modeset_check_state(struct drm_device *dev) | |
11138 | { | |
08db6652 | 11139 | check_wm_state(dev); |
91d1b4bd DV |
11140 | check_connector_state(dev); |
11141 | check_encoder_state(dev); | |
11142 | check_crtc_state(dev); | |
11143 | check_shared_dpll_state(dev); | |
11144 | } | |
11145 | ||
5cec258b | 11146 | void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config, |
18442d08 VS |
11147 | int dotclock) |
11148 | { | |
11149 | /* | |
11150 | * FDI already provided one idea for the dotclock. | |
11151 | * Yell if the encoder disagrees. | |
11152 | */ | |
2d112de7 | 11153 | WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock), |
18442d08 | 11154 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
2d112de7 | 11155 | pipe_config->base.adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
11156 | } |
11157 | ||
80715b2f VS |
11158 | static void update_scanline_offset(struct intel_crtc *crtc) |
11159 | { | |
11160 | struct drm_device *dev = crtc->base.dev; | |
11161 | ||
11162 | /* | |
11163 | * The scanline counter increments at the leading edge of hsync. | |
11164 | * | |
11165 | * On most platforms it starts counting from vtotal-1 on the | |
11166 | * first active line. That means the scanline counter value is | |
11167 | * always one less than what we would expect. Ie. just after | |
11168 | * start of vblank, which also occurs at start of hsync (on the | |
11169 | * last active line), the scanline counter will read vblank_start-1. | |
11170 | * | |
11171 | * On gen2 the scanline counter starts counting from 1 instead | |
11172 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
11173 | * to keep the value positive), instead of adding one. | |
11174 | * | |
11175 | * On HSW+ the behaviour of the scanline counter depends on the output | |
11176 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
11177 | * there's an extra 1 line difference. So we need to add two instead of | |
11178 | * one to the value. | |
11179 | */ | |
11180 | if (IS_GEN2(dev)) { | |
6e3c9717 | 11181 | const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
11182 | int vtotal; |
11183 | ||
11184 | vtotal = mode->crtc_vtotal; | |
11185 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
11186 | vtotal /= 2; | |
11187 | ||
11188 | crtc->scanline_offset = vtotal - 1; | |
11189 | } else if (HAS_DDI(dev) && | |
409ee761 | 11190 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
11191 | crtc->scanline_offset = 2; |
11192 | } else | |
11193 | crtc->scanline_offset = 1; | |
11194 | } | |
11195 | ||
5cec258b | 11196 | static struct intel_crtc_state * |
7f27126e JB |
11197 | intel_modeset_compute_config(struct drm_crtc *crtc, |
11198 | struct drm_display_mode *mode, | |
11199 | struct drm_framebuffer *fb, | |
11200 | unsigned *modeset_pipes, | |
11201 | unsigned *prepare_pipes, | |
11202 | unsigned *disable_pipes) | |
11203 | { | |
5cec258b | 11204 | struct intel_crtc_state *pipe_config = NULL; |
7f27126e JB |
11205 | |
11206 | intel_modeset_affected_pipes(crtc, modeset_pipes, | |
11207 | prepare_pipes, disable_pipes); | |
11208 | ||
11209 | if ((*modeset_pipes) == 0) | |
11210 | goto out; | |
11211 | ||
11212 | /* | |
11213 | * Note this needs changes when we start tracking multiple modes | |
11214 | * and crtcs. At that point we'll need to compute the whole config | |
11215 | * (i.e. one pipe_config for each crtc) rather than just the one | |
11216 | * for this crtc. | |
11217 | */ | |
11218 | pipe_config = intel_modeset_pipe_config(crtc, fb, mode); | |
11219 | if (IS_ERR(pipe_config)) { | |
11220 | goto out; | |
11221 | } | |
11222 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, | |
11223 | "[modeset]"); | |
7f27126e JB |
11224 | |
11225 | out: | |
11226 | return pipe_config; | |
11227 | } | |
11228 | ||
ed6739ef ACO |
11229 | static int __intel_set_mode_setup_plls(struct drm_device *dev, |
11230 | unsigned modeset_pipes, | |
11231 | unsigned disable_pipes) | |
11232 | { | |
11233 | struct drm_i915_private *dev_priv = to_i915(dev); | |
11234 | unsigned clear_pipes = modeset_pipes | disable_pipes; | |
11235 | struct intel_crtc *intel_crtc; | |
11236 | int ret = 0; | |
11237 | ||
11238 | if (!dev_priv->display.crtc_compute_clock) | |
11239 | return 0; | |
11240 | ||
11241 | ret = intel_shared_dpll_start_config(dev_priv, clear_pipes); | |
11242 | if (ret) | |
11243 | goto done; | |
11244 | ||
11245 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { | |
11246 | struct intel_crtc_state *state = intel_crtc->new_config; | |
11247 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, | |
11248 | state); | |
11249 | if (ret) { | |
11250 | intel_shared_dpll_abort_config(dev_priv); | |
11251 | goto done; | |
11252 | } | |
11253 | } | |
11254 | ||
11255 | done: | |
11256 | return ret; | |
11257 | } | |
11258 | ||
f30da187 DV |
11259 | static int __intel_set_mode(struct drm_crtc *crtc, |
11260 | struct drm_display_mode *mode, | |
7f27126e | 11261 | int x, int y, struct drm_framebuffer *fb, |
5cec258b | 11262 | struct intel_crtc_state *pipe_config, |
7f27126e JB |
11263 | unsigned modeset_pipes, |
11264 | unsigned prepare_pipes, | |
11265 | unsigned disable_pipes) | |
a6778b3c DV |
11266 | { |
11267 | struct drm_device *dev = crtc->dev; | |
fbee40df | 11268 | struct drm_i915_private *dev_priv = dev->dev_private; |
4b4b9238 | 11269 | struct drm_display_mode *saved_mode; |
25c5b266 | 11270 | struct intel_crtc *intel_crtc; |
c0c36b94 | 11271 | int ret = 0; |
a6778b3c | 11272 | |
4b4b9238 | 11273 | saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL); |
c0c36b94 CW |
11274 | if (!saved_mode) |
11275 | return -ENOMEM; | |
a6778b3c | 11276 | |
3ac18232 | 11277 | *saved_mode = crtc->mode; |
a6778b3c | 11278 | |
b9950a13 VS |
11279 | if (modeset_pipes) |
11280 | to_intel_crtc(crtc)->new_config = pipe_config; | |
11281 | ||
30a970c6 JB |
11282 | /* |
11283 | * See if the config requires any additional preparation, e.g. | |
11284 | * to adjust global state with pipes off. We need to do this | |
11285 | * here so we can get the modeset_pipe updated config for the new | |
11286 | * mode set on this crtc. For other crtcs we need to use the | |
11287 | * adjusted_mode bits in the crtc directly. | |
11288 | */ | |
c164f833 | 11289 | if (IS_VALLEYVIEW(dev)) { |
2f2d7aa1 | 11290 | valleyview_modeset_global_pipes(dev, &prepare_pipes); |
30a970c6 | 11291 | |
c164f833 VS |
11292 | /* may have added more to prepare_pipes than we should */ |
11293 | prepare_pipes &= ~disable_pipes; | |
11294 | } | |
11295 | ||
ed6739ef ACO |
11296 | ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes); |
11297 | if (ret) | |
11298 | goto done; | |
8bd31e67 | 11299 | |
460da916 DV |
11300 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
11301 | intel_crtc_disable(&intel_crtc->base); | |
11302 | ||
ea9d758d | 11303 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
83d65738 | 11304 | if (intel_crtc->base.state->enable) |
ea9d758d DV |
11305 | dev_priv->display.crtc_disable(&intel_crtc->base); |
11306 | } | |
a6778b3c | 11307 | |
6c4c86f5 DV |
11308 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
11309 | * to set it here already despite that we pass it down the callchain. | |
7f27126e JB |
11310 | * |
11311 | * Note we'll need to fix this up when we start tracking multiple | |
11312 | * pipes; here we assume a single modeset_pipe and only track the | |
11313 | * single crtc and mode. | |
f6e5b160 | 11314 | */ |
b8cecdf5 | 11315 | if (modeset_pipes) { |
25c5b266 | 11316 | crtc->mode = *mode; |
b8cecdf5 DV |
11317 | /* mode_set/enable/disable functions rely on a correct pipe |
11318 | * config. */ | |
f5de6e07 | 11319 | intel_crtc_set_state(to_intel_crtc(crtc), pipe_config); |
c326c0a9 VS |
11320 | |
11321 | /* | |
11322 | * Calculate and store various constants which | |
11323 | * are later needed by vblank and swap-completion | |
11324 | * timestamping. They are derived from true hwmode. | |
11325 | */ | |
11326 | drm_calc_timestamping_constants(crtc, | |
2d112de7 | 11327 | &pipe_config->base.adjusted_mode); |
b8cecdf5 | 11328 | } |
7758a113 | 11329 | |
ea9d758d DV |
11330 | /* Only after disabling all output pipelines that will be changed can we |
11331 | * update the the output configuration. */ | |
11332 | intel_modeset_update_state(dev, prepare_pipes); | |
f6e5b160 | 11333 | |
50f6e502 | 11334 | modeset_update_crtc_power_domains(dev); |
47fab737 | 11335 | |
a6778b3c DV |
11336 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
11337 | * on the DPLL. | |
f6e5b160 | 11338 | */ |
25c5b266 | 11339 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
455a6808 GP |
11340 | struct drm_plane *primary = intel_crtc->base.primary; |
11341 | int vdisplay, hdisplay; | |
4c10794f | 11342 | |
455a6808 GP |
11343 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); |
11344 | ret = primary->funcs->update_plane(primary, &intel_crtc->base, | |
11345 | fb, 0, 0, | |
11346 | hdisplay, vdisplay, | |
11347 | x << 16, y << 16, | |
11348 | hdisplay << 16, vdisplay << 16); | |
a6778b3c DV |
11349 | } |
11350 | ||
11351 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
80715b2f VS |
11352 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
11353 | update_scanline_offset(intel_crtc); | |
11354 | ||
25c5b266 | 11355 | dev_priv->display.crtc_enable(&intel_crtc->base); |
80715b2f | 11356 | } |
a6778b3c | 11357 | |
a6778b3c DV |
11358 | /* FIXME: add subpixel order */ |
11359 | done: | |
83d65738 | 11360 | if (ret && crtc->state->enable) |
3ac18232 | 11361 | crtc->mode = *saved_mode; |
a6778b3c | 11362 | |
3ac18232 | 11363 | kfree(saved_mode); |
a6778b3c | 11364 | return ret; |
f6e5b160 CW |
11365 | } |
11366 | ||
7f27126e JB |
11367 | static int intel_set_mode_pipes(struct drm_crtc *crtc, |
11368 | struct drm_display_mode *mode, | |
11369 | int x, int y, struct drm_framebuffer *fb, | |
5cec258b | 11370 | struct intel_crtc_state *pipe_config, |
7f27126e JB |
11371 | unsigned modeset_pipes, |
11372 | unsigned prepare_pipes, | |
11373 | unsigned disable_pipes) | |
f30da187 DV |
11374 | { |
11375 | int ret; | |
11376 | ||
7f27126e JB |
11377 | ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes, |
11378 | prepare_pipes, disable_pipes); | |
f30da187 DV |
11379 | |
11380 | if (ret == 0) | |
11381 | intel_modeset_check_state(crtc->dev); | |
11382 | ||
11383 | return ret; | |
11384 | } | |
11385 | ||
7f27126e JB |
11386 | static int intel_set_mode(struct drm_crtc *crtc, |
11387 | struct drm_display_mode *mode, | |
11388 | int x, int y, struct drm_framebuffer *fb) | |
11389 | { | |
5cec258b | 11390 | struct intel_crtc_state *pipe_config; |
7f27126e JB |
11391 | unsigned modeset_pipes, prepare_pipes, disable_pipes; |
11392 | ||
11393 | pipe_config = intel_modeset_compute_config(crtc, mode, fb, | |
11394 | &modeset_pipes, | |
11395 | &prepare_pipes, | |
11396 | &disable_pipes); | |
11397 | ||
11398 | if (IS_ERR(pipe_config)) | |
11399 | return PTR_ERR(pipe_config); | |
11400 | ||
11401 | return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config, | |
11402 | modeset_pipes, prepare_pipes, | |
11403 | disable_pipes); | |
11404 | } | |
11405 | ||
c0c36b94 CW |
11406 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
11407 | { | |
f4510a27 | 11408 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb); |
c0c36b94 CW |
11409 | } |
11410 | ||
25c5b266 DV |
11411 | #undef for_each_intel_crtc_masked |
11412 | ||
d9e55608 DV |
11413 | static void intel_set_config_free(struct intel_set_config *config) |
11414 | { | |
11415 | if (!config) | |
11416 | return; | |
11417 | ||
1aa4b628 DV |
11418 | kfree(config->save_connector_encoders); |
11419 | kfree(config->save_encoder_crtcs); | |
7668851f | 11420 | kfree(config->save_crtc_enabled); |
d9e55608 DV |
11421 | kfree(config); |
11422 | } | |
11423 | ||
85f9eb71 DV |
11424 | static int intel_set_config_save_state(struct drm_device *dev, |
11425 | struct intel_set_config *config) | |
11426 | { | |
7668851f | 11427 | struct drm_crtc *crtc; |
85f9eb71 DV |
11428 | struct drm_encoder *encoder; |
11429 | struct drm_connector *connector; | |
11430 | int count; | |
11431 | ||
7668851f VS |
11432 | config->save_crtc_enabled = |
11433 | kcalloc(dev->mode_config.num_crtc, | |
11434 | sizeof(bool), GFP_KERNEL); | |
11435 | if (!config->save_crtc_enabled) | |
11436 | return -ENOMEM; | |
11437 | ||
1aa4b628 DV |
11438 | config->save_encoder_crtcs = |
11439 | kcalloc(dev->mode_config.num_encoder, | |
11440 | sizeof(struct drm_crtc *), GFP_KERNEL); | |
11441 | if (!config->save_encoder_crtcs) | |
85f9eb71 DV |
11442 | return -ENOMEM; |
11443 | ||
1aa4b628 DV |
11444 | config->save_connector_encoders = |
11445 | kcalloc(dev->mode_config.num_connector, | |
11446 | sizeof(struct drm_encoder *), GFP_KERNEL); | |
11447 | if (!config->save_connector_encoders) | |
85f9eb71 DV |
11448 | return -ENOMEM; |
11449 | ||
11450 | /* Copy data. Note that driver private data is not affected. | |
11451 | * Should anything bad happen only the expected state is | |
11452 | * restored, not the drivers personal bookkeeping. | |
11453 | */ | |
7668851f | 11454 | count = 0; |
70e1e0ec | 11455 | for_each_crtc(dev, crtc) { |
83d65738 | 11456 | config->save_crtc_enabled[count++] = crtc->state->enable; |
7668851f VS |
11457 | } |
11458 | ||
85f9eb71 DV |
11459 | count = 0; |
11460 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1aa4b628 | 11461 | config->save_encoder_crtcs[count++] = encoder->crtc; |
85f9eb71 DV |
11462 | } |
11463 | ||
11464 | count = 0; | |
11465 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1aa4b628 | 11466 | config->save_connector_encoders[count++] = connector->encoder; |
85f9eb71 DV |
11467 | } |
11468 | ||
11469 | return 0; | |
11470 | } | |
11471 | ||
11472 | static void intel_set_config_restore_state(struct drm_device *dev, | |
11473 | struct intel_set_config *config) | |
11474 | { | |
7668851f | 11475 | struct intel_crtc *crtc; |
9a935856 DV |
11476 | struct intel_encoder *encoder; |
11477 | struct intel_connector *connector; | |
85f9eb71 DV |
11478 | int count; |
11479 | ||
7668851f | 11480 | count = 0; |
d3fcc808 | 11481 | for_each_intel_crtc(dev, crtc) { |
7668851f | 11482 | crtc->new_enabled = config->save_crtc_enabled[count++]; |
7bd0a8e7 VS |
11483 | |
11484 | if (crtc->new_enabled) | |
6e3c9717 | 11485 | crtc->new_config = crtc->config; |
7bd0a8e7 VS |
11486 | else |
11487 | crtc->new_config = NULL; | |
7668851f VS |
11488 | } |
11489 | ||
85f9eb71 | 11490 | count = 0; |
b2784e15 | 11491 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
11492 | encoder->new_crtc = |
11493 | to_intel_crtc(config->save_encoder_crtcs[count++]); | |
85f9eb71 DV |
11494 | } |
11495 | ||
11496 | count = 0; | |
3a3371ff | 11497 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
11498 | connector->new_encoder = |
11499 | to_intel_encoder(config->save_connector_encoders[count++]); | |
85f9eb71 DV |
11500 | } |
11501 | } | |
11502 | ||
e3de42b6 | 11503 | static bool |
2e57f47d | 11504 | is_crtc_connector_off(struct drm_mode_set *set) |
e3de42b6 ID |
11505 | { |
11506 | int i; | |
11507 | ||
2e57f47d CW |
11508 | if (set->num_connectors == 0) |
11509 | return false; | |
11510 | ||
11511 | if (WARN_ON(set->connectors == NULL)) | |
11512 | return false; | |
11513 | ||
11514 | for (i = 0; i < set->num_connectors; i++) | |
11515 | if (set->connectors[i]->encoder && | |
11516 | set->connectors[i]->encoder->crtc == set->crtc && | |
11517 | set->connectors[i]->dpms != DRM_MODE_DPMS_ON) | |
e3de42b6 ID |
11518 | return true; |
11519 | ||
11520 | return false; | |
11521 | } | |
11522 | ||
5e2b584e DV |
11523 | static void |
11524 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, | |
11525 | struct intel_set_config *config) | |
11526 | { | |
11527 | ||
11528 | /* We should be able to check here if the fb has the same properties | |
11529 | * and then just flip_or_move it */ | |
2e57f47d CW |
11530 | if (is_crtc_connector_off(set)) { |
11531 | config->mode_changed = true; | |
f4510a27 | 11532 | } else if (set->crtc->primary->fb != set->fb) { |
3b150f08 MR |
11533 | /* |
11534 | * If we have no fb, we can only flip as long as the crtc is | |
11535 | * active, otherwise we need a full mode set. The crtc may | |
11536 | * be active if we've only disabled the primary plane, or | |
11537 | * in fastboot situations. | |
11538 | */ | |
f4510a27 | 11539 | if (set->crtc->primary->fb == NULL) { |
319d9827 JB |
11540 | struct intel_crtc *intel_crtc = |
11541 | to_intel_crtc(set->crtc); | |
11542 | ||
3b150f08 | 11543 | if (intel_crtc->active) { |
319d9827 JB |
11544 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); |
11545 | config->fb_changed = true; | |
11546 | } else { | |
11547 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); | |
11548 | config->mode_changed = true; | |
11549 | } | |
5e2b584e DV |
11550 | } else if (set->fb == NULL) { |
11551 | config->mode_changed = true; | |
72f4901e | 11552 | } else if (set->fb->pixel_format != |
f4510a27 | 11553 | set->crtc->primary->fb->pixel_format) { |
5e2b584e | 11554 | config->mode_changed = true; |
e3de42b6 | 11555 | } else { |
5e2b584e | 11556 | config->fb_changed = true; |
e3de42b6 | 11557 | } |
5e2b584e DV |
11558 | } |
11559 | ||
835c5873 | 11560 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
5e2b584e DV |
11561 | config->fb_changed = true; |
11562 | ||
11563 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { | |
11564 | DRM_DEBUG_KMS("modes are different, full mode set\n"); | |
11565 | drm_mode_debug_printmodeline(&set->crtc->mode); | |
11566 | drm_mode_debug_printmodeline(set->mode); | |
11567 | config->mode_changed = true; | |
11568 | } | |
a1d95703 CW |
11569 | |
11570 | DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", | |
11571 | set->crtc->base.id, config->mode_changed, config->fb_changed); | |
5e2b584e DV |
11572 | } |
11573 | ||
2e431051 | 11574 | static int |
9a935856 DV |
11575 | intel_modeset_stage_output_state(struct drm_device *dev, |
11576 | struct drm_mode_set *set, | |
11577 | struct intel_set_config *config) | |
50f56119 | 11578 | { |
9a935856 DV |
11579 | struct intel_connector *connector; |
11580 | struct intel_encoder *encoder; | |
7668851f | 11581 | struct intel_crtc *crtc; |
f3f08572 | 11582 | int ro; |
50f56119 | 11583 | |
9abdda74 | 11584 | /* The upper layers ensure that we either disable a crtc or have a list |
9a935856 DV |
11585 | * of connectors. For paranoia, double-check this. */ |
11586 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
11587 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
11588 | ||
3a3371ff | 11589 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
11590 | /* Otherwise traverse passed in connector list and get encoders |
11591 | * for them. */ | |
50f56119 | 11592 | for (ro = 0; ro < set->num_connectors; ro++) { |
9a935856 | 11593 | if (set->connectors[ro] == &connector->base) { |
0e32b39c | 11594 | connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe); |
50f56119 DV |
11595 | break; |
11596 | } | |
11597 | } | |
11598 | ||
9a935856 DV |
11599 | /* If we disable the crtc, disable all its connectors. Also, if |
11600 | * the connector is on the changing crtc but not on the new | |
11601 | * connector list, disable it. */ | |
11602 | if ((!set->fb || ro == set->num_connectors) && | |
11603 | connector->base.encoder && | |
11604 | connector->base.encoder->crtc == set->crtc) { | |
11605 | connector->new_encoder = NULL; | |
11606 | ||
11607 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
11608 | connector->base.base.id, | |
c23cc417 | 11609 | connector->base.name); |
9a935856 DV |
11610 | } |
11611 | ||
11612 | ||
11613 | if (&connector->new_encoder->base != connector->base.encoder) { | |
10634189 ACO |
11614 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n", |
11615 | connector->base.base.id, | |
11616 | connector->base.name); | |
5e2b584e | 11617 | config->mode_changed = true; |
50f56119 DV |
11618 | } |
11619 | } | |
9a935856 | 11620 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 11621 | |
9a935856 | 11622 | /* Update crtc of enabled connectors. */ |
3a3371ff | 11623 | for_each_intel_connector(dev, connector) { |
7668851f VS |
11624 | struct drm_crtc *new_crtc; |
11625 | ||
9a935856 | 11626 | if (!connector->new_encoder) |
50f56119 DV |
11627 | continue; |
11628 | ||
9a935856 | 11629 | new_crtc = connector->new_encoder->base.crtc; |
50f56119 DV |
11630 | |
11631 | for (ro = 0; ro < set->num_connectors; ro++) { | |
9a935856 | 11632 | if (set->connectors[ro] == &connector->base) |
50f56119 DV |
11633 | new_crtc = set->crtc; |
11634 | } | |
11635 | ||
11636 | /* Make sure the new CRTC will work with the encoder */ | |
14509916 TR |
11637 | if (!drm_encoder_crtc_ok(&connector->new_encoder->base, |
11638 | new_crtc)) { | |
5e2b584e | 11639 | return -EINVAL; |
50f56119 | 11640 | } |
0e32b39c | 11641 | connector->new_encoder->new_crtc = to_intel_crtc(new_crtc); |
9a935856 DV |
11642 | |
11643 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", | |
11644 | connector->base.base.id, | |
c23cc417 | 11645 | connector->base.name, |
9a935856 DV |
11646 | new_crtc->base.id); |
11647 | } | |
11648 | ||
11649 | /* Check for any encoders that needs to be disabled. */ | |
b2784e15 | 11650 | for_each_intel_encoder(dev, encoder) { |
5a65f358 | 11651 | int num_connectors = 0; |
3a3371ff | 11652 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
11653 | if (connector->new_encoder == encoder) { |
11654 | WARN_ON(!connector->new_encoder->new_crtc); | |
5a65f358 | 11655 | num_connectors++; |
9a935856 DV |
11656 | } |
11657 | } | |
5a65f358 PZ |
11658 | |
11659 | if (num_connectors == 0) | |
11660 | encoder->new_crtc = NULL; | |
11661 | else if (num_connectors > 1) | |
11662 | return -EINVAL; | |
11663 | ||
9a935856 DV |
11664 | /* Only now check for crtc changes so we don't miss encoders |
11665 | * that will be disabled. */ | |
11666 | if (&encoder->new_crtc->base != encoder->base.crtc) { | |
10634189 ACO |
11667 | DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n", |
11668 | encoder->base.base.id, | |
11669 | encoder->base.name); | |
5e2b584e | 11670 | config->mode_changed = true; |
50f56119 DV |
11671 | } |
11672 | } | |
9a935856 | 11673 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
3a3371ff | 11674 | for_each_intel_connector(dev, connector) { |
0e32b39c DA |
11675 | if (connector->new_encoder) |
11676 | if (connector->new_encoder != connector->encoder) | |
11677 | connector->encoder = connector->new_encoder; | |
11678 | } | |
d3fcc808 | 11679 | for_each_intel_crtc(dev, crtc) { |
7668851f VS |
11680 | crtc->new_enabled = false; |
11681 | ||
b2784e15 | 11682 | for_each_intel_encoder(dev, encoder) { |
7668851f VS |
11683 | if (encoder->new_crtc == crtc) { |
11684 | crtc->new_enabled = true; | |
11685 | break; | |
11686 | } | |
11687 | } | |
11688 | ||
83d65738 | 11689 | if (crtc->new_enabled != crtc->base.state->enable) { |
10634189 ACO |
11690 | DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n", |
11691 | crtc->base.base.id, | |
7668851f VS |
11692 | crtc->new_enabled ? "en" : "dis"); |
11693 | config->mode_changed = true; | |
11694 | } | |
7bd0a8e7 VS |
11695 | |
11696 | if (crtc->new_enabled) | |
6e3c9717 | 11697 | crtc->new_config = crtc->config; |
7bd0a8e7 VS |
11698 | else |
11699 | crtc->new_config = NULL; | |
7668851f VS |
11700 | } |
11701 | ||
2e431051 DV |
11702 | return 0; |
11703 | } | |
11704 | ||
7d00a1f5 VS |
11705 | static void disable_crtc_nofb(struct intel_crtc *crtc) |
11706 | { | |
11707 | struct drm_device *dev = crtc->base.dev; | |
11708 | struct intel_encoder *encoder; | |
11709 | struct intel_connector *connector; | |
11710 | ||
11711 | DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n", | |
11712 | pipe_name(crtc->pipe)); | |
11713 | ||
3a3371ff | 11714 | for_each_intel_connector(dev, connector) { |
7d00a1f5 VS |
11715 | if (connector->new_encoder && |
11716 | connector->new_encoder->new_crtc == crtc) | |
11717 | connector->new_encoder = NULL; | |
11718 | } | |
11719 | ||
b2784e15 | 11720 | for_each_intel_encoder(dev, encoder) { |
7d00a1f5 VS |
11721 | if (encoder->new_crtc == crtc) |
11722 | encoder->new_crtc = NULL; | |
11723 | } | |
11724 | ||
11725 | crtc->new_enabled = false; | |
7bd0a8e7 | 11726 | crtc->new_config = NULL; |
7d00a1f5 VS |
11727 | } |
11728 | ||
2e431051 DV |
11729 | static int intel_crtc_set_config(struct drm_mode_set *set) |
11730 | { | |
11731 | struct drm_device *dev; | |
2e431051 DV |
11732 | struct drm_mode_set save_set; |
11733 | struct intel_set_config *config; | |
5cec258b | 11734 | struct intel_crtc_state *pipe_config; |
50f52756 | 11735 | unsigned modeset_pipes, prepare_pipes, disable_pipes; |
2e431051 | 11736 | int ret; |
2e431051 | 11737 | |
8d3e375e DV |
11738 | BUG_ON(!set); |
11739 | BUG_ON(!set->crtc); | |
11740 | BUG_ON(!set->crtc->helper_private); | |
2e431051 | 11741 | |
7e53f3a4 DV |
11742 | /* Enforce sane interface api - has been abused by the fb helper. */ |
11743 | BUG_ON(!set->mode && set->fb); | |
11744 | BUG_ON(set->fb && set->num_connectors == 0); | |
431e50f7 | 11745 | |
2e431051 DV |
11746 | if (set->fb) { |
11747 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
11748 | set->crtc->base.id, set->fb->base.id, | |
11749 | (int)set->num_connectors, set->x, set->y); | |
11750 | } else { | |
11751 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
11752 | } |
11753 | ||
11754 | dev = set->crtc->dev; | |
11755 | ||
11756 | ret = -ENOMEM; | |
11757 | config = kzalloc(sizeof(*config), GFP_KERNEL); | |
11758 | if (!config) | |
11759 | goto out_config; | |
11760 | ||
11761 | ret = intel_set_config_save_state(dev, config); | |
11762 | if (ret) | |
11763 | goto out_config; | |
11764 | ||
11765 | save_set.crtc = set->crtc; | |
11766 | save_set.mode = &set->crtc->mode; | |
11767 | save_set.x = set->crtc->x; | |
11768 | save_set.y = set->crtc->y; | |
f4510a27 | 11769 | save_set.fb = set->crtc->primary->fb; |
2e431051 DV |
11770 | |
11771 | /* Compute whether we need a full modeset, only an fb base update or no | |
11772 | * change at all. In the future we might also check whether only the | |
11773 | * mode changed, e.g. for LVDS where we only change the panel fitter in | |
11774 | * such cases. */ | |
11775 | intel_set_config_compute_mode_changes(set, config); | |
11776 | ||
9a935856 | 11777 | ret = intel_modeset_stage_output_state(dev, set, config); |
2e431051 DV |
11778 | if (ret) |
11779 | goto fail; | |
11780 | ||
50f52756 JB |
11781 | pipe_config = intel_modeset_compute_config(set->crtc, set->mode, |
11782 | set->fb, | |
11783 | &modeset_pipes, | |
11784 | &prepare_pipes, | |
11785 | &disable_pipes); | |
20664591 | 11786 | if (IS_ERR(pipe_config)) { |
6ac0483b | 11787 | ret = PTR_ERR(pipe_config); |
50f52756 | 11788 | goto fail; |
20664591 | 11789 | } else if (pipe_config) { |
b9950a13 | 11790 | if (pipe_config->has_audio != |
6e3c9717 | 11791 | to_intel_crtc(set->crtc)->config->has_audio) |
20664591 JB |
11792 | config->mode_changed = true; |
11793 | ||
af15d2ce JB |
11794 | /* |
11795 | * Note we have an issue here with infoframes: current code | |
11796 | * only updates them on the full mode set path per hw | |
11797 | * requirements. So here we should be checking for any | |
11798 | * required changes and forcing a mode set. | |
11799 | */ | |
20664591 | 11800 | } |
50f52756 JB |
11801 | |
11802 | /* set_mode will free it in the mode_changed case */ | |
11803 | if (!config->mode_changed) | |
11804 | kfree(pipe_config); | |
11805 | ||
1f9954d0 JB |
11806 | intel_update_pipe_size(to_intel_crtc(set->crtc)); |
11807 | ||
5e2b584e | 11808 | if (config->mode_changed) { |
50f52756 JB |
11809 | ret = intel_set_mode_pipes(set->crtc, set->mode, |
11810 | set->x, set->y, set->fb, pipe_config, | |
11811 | modeset_pipes, prepare_pipes, | |
11812 | disable_pipes); | |
5e2b584e | 11813 | } else if (config->fb_changed) { |
3b150f08 | 11814 | struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc); |
455a6808 GP |
11815 | struct drm_plane *primary = set->crtc->primary; |
11816 | int vdisplay, hdisplay; | |
3b150f08 | 11817 | |
455a6808 GP |
11818 | drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay); |
11819 | ret = primary->funcs->update_plane(primary, set->crtc, set->fb, | |
11820 | 0, 0, hdisplay, vdisplay, | |
11821 | set->x << 16, set->y << 16, | |
11822 | hdisplay << 16, vdisplay << 16); | |
3b150f08 MR |
11823 | |
11824 | /* | |
11825 | * We need to make sure the primary plane is re-enabled if it | |
11826 | * has previously been turned off. | |
11827 | */ | |
11828 | if (!intel_crtc->primary_enabled && ret == 0) { | |
11829 | WARN_ON(!intel_crtc->active); | |
fdd508a6 | 11830 | intel_enable_primary_hw_plane(set->crtc->primary, set->crtc); |
3b150f08 MR |
11831 | } |
11832 | ||
7ca51a3a JB |
11833 | /* |
11834 | * In the fastboot case this may be our only check of the | |
11835 | * state after boot. It would be better to only do it on | |
11836 | * the first update, but we don't have a nice way of doing that | |
11837 | * (and really, set_config isn't used much for high freq page | |
11838 | * flipping, so increasing its cost here shouldn't be a big | |
11839 | * deal). | |
11840 | */ | |
d330a953 | 11841 | if (i915.fastboot && ret == 0) |
7ca51a3a | 11842 | intel_modeset_check_state(set->crtc->dev); |
50f56119 DV |
11843 | } |
11844 | ||
2d05eae1 | 11845 | if (ret) { |
bf67dfeb DV |
11846 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
11847 | set->crtc->base.id, ret); | |
50f56119 | 11848 | fail: |
2d05eae1 | 11849 | intel_set_config_restore_state(dev, config); |
50f56119 | 11850 | |
7d00a1f5 VS |
11851 | /* |
11852 | * HACK: if the pipe was on, but we didn't have a framebuffer, | |
11853 | * force the pipe off to avoid oopsing in the modeset code | |
11854 | * due to fb==NULL. This should only happen during boot since | |
11855 | * we don't yet reconstruct the FB from the hardware state. | |
11856 | */ | |
11857 | if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb) | |
11858 | disable_crtc_nofb(to_intel_crtc(save_set.crtc)); | |
11859 | ||
2d05eae1 CW |
11860 | /* Try to restore the config */ |
11861 | if (config->mode_changed && | |
11862 | intel_set_mode(save_set.crtc, save_set.mode, | |
11863 | save_set.x, save_set.y, save_set.fb)) | |
11864 | DRM_ERROR("failed to restore config after modeset failure\n"); | |
11865 | } | |
50f56119 | 11866 | |
d9e55608 DV |
11867 | out_config: |
11868 | intel_set_config_free(config); | |
50f56119 DV |
11869 | return ret; |
11870 | } | |
f6e5b160 CW |
11871 | |
11872 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 | 11873 | .gamma_set = intel_crtc_gamma_set, |
50f56119 | 11874 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
11875 | .destroy = intel_crtc_destroy, |
11876 | .page_flip = intel_crtc_page_flip, | |
1356837e MR |
11877 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
11878 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
11879 | }; |
11880 | ||
5358901f DV |
11881 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
11882 | struct intel_shared_dpll *pll, | |
11883 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 11884 | { |
5358901f | 11885 | uint32_t val; |
ee7b9f93 | 11886 | |
f458ebbc | 11887 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
bd2bb1b9 PZ |
11888 | return false; |
11889 | ||
5358901f | 11890 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
11891 | hw_state->dpll = val; |
11892 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
11893 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
11894 | |
11895 | return val & DPLL_VCO_ENABLE; | |
11896 | } | |
11897 | ||
15bdd4cf DV |
11898 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
11899 | struct intel_shared_dpll *pll) | |
11900 | { | |
3e369b76 ACO |
11901 | I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0); |
11902 | I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1); | |
15bdd4cf DV |
11903 | } |
11904 | ||
e7b903d2 DV |
11905 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
11906 | struct intel_shared_dpll *pll) | |
11907 | { | |
e7b903d2 | 11908 | /* PCH refclock must be enabled first */ |
89eff4be | 11909 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 11910 | |
3e369b76 | 11911 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf DV |
11912 | |
11913 | /* Wait for the clocks to stabilize. */ | |
11914 | POSTING_READ(PCH_DPLL(pll->id)); | |
11915 | udelay(150); | |
11916 | ||
11917 | /* The pixel multiplier can only be updated once the | |
11918 | * DPLL is enabled and the clocks are stable. | |
11919 | * | |
11920 | * So write it again. | |
11921 | */ | |
3e369b76 | 11922 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf | 11923 | POSTING_READ(PCH_DPLL(pll->id)); |
e7b903d2 DV |
11924 | udelay(200); |
11925 | } | |
11926 | ||
11927 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
11928 | struct intel_shared_dpll *pll) | |
11929 | { | |
11930 | struct drm_device *dev = dev_priv->dev; | |
11931 | struct intel_crtc *crtc; | |
e7b903d2 DV |
11932 | |
11933 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 11934 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
11935 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
11936 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
11937 | } |
11938 | ||
15bdd4cf DV |
11939 | I915_WRITE(PCH_DPLL(pll->id), 0); |
11940 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
11941 | udelay(200); |
11942 | } | |
11943 | ||
46edb027 DV |
11944 | static char *ibx_pch_dpll_names[] = { |
11945 | "PCH DPLL A", | |
11946 | "PCH DPLL B", | |
11947 | }; | |
11948 | ||
7c74ade1 | 11949 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 11950 | { |
e7b903d2 | 11951 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
11952 | int i; |
11953 | ||
7c74ade1 | 11954 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 11955 | |
e72f9fbf | 11956 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
11957 | dev_priv->shared_dplls[i].id = i; |
11958 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 11959 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
11960 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
11961 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
11962 | dev_priv->shared_dplls[i].get_hw_state = |
11963 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
11964 | } |
11965 | } | |
11966 | ||
7c74ade1 DV |
11967 | static void intel_shared_dpll_init(struct drm_device *dev) |
11968 | { | |
e7b903d2 | 11969 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 | 11970 | |
9cd86933 DV |
11971 | if (HAS_DDI(dev)) |
11972 | intel_ddi_pll_init(dev); | |
11973 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7c74ade1 DV |
11974 | ibx_pch_dpll_init(dev); |
11975 | else | |
11976 | dev_priv->num_shared_dpll = 0; | |
11977 | ||
11978 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
11979 | } |
11980 | ||
6beb8c23 MR |
11981 | /** |
11982 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
11983 | * @plane: drm plane to prepare for | |
11984 | * @fb: framebuffer to prepare for presentation | |
11985 | * | |
11986 | * Prepares a framebuffer for usage on a display plane. Generally this | |
11987 | * involves pinning the underlying object and updating the frontbuffer tracking | |
11988 | * bits. Some older platforms need special physical address handling for | |
11989 | * cursor planes. | |
11990 | * | |
11991 | * Returns 0 on success, negative error code on failure. | |
11992 | */ | |
11993 | int | |
11994 | intel_prepare_plane_fb(struct drm_plane *plane, | |
d136dfee TU |
11995 | struct drm_framebuffer *fb, |
11996 | const struct drm_plane_state *new_state) | |
465c120c MR |
11997 | { |
11998 | struct drm_device *dev = plane->dev; | |
6beb8c23 MR |
11999 | struct intel_plane *intel_plane = to_intel_plane(plane); |
12000 | enum pipe pipe = intel_plane->pipe; | |
12001 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
12002 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); | |
12003 | unsigned frontbuffer_bits = 0; | |
12004 | int ret = 0; | |
465c120c | 12005 | |
ea2c67bb | 12006 | if (!obj) |
465c120c MR |
12007 | return 0; |
12008 | ||
6beb8c23 MR |
12009 | switch (plane->type) { |
12010 | case DRM_PLANE_TYPE_PRIMARY: | |
12011 | frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe); | |
12012 | break; | |
12013 | case DRM_PLANE_TYPE_CURSOR: | |
12014 | frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe); | |
12015 | break; | |
12016 | case DRM_PLANE_TYPE_OVERLAY: | |
12017 | frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe); | |
12018 | break; | |
12019 | } | |
465c120c | 12020 | |
6beb8c23 | 12021 | mutex_lock(&dev->struct_mutex); |
465c120c | 12022 | |
6beb8c23 MR |
12023 | if (plane->type == DRM_PLANE_TYPE_CURSOR && |
12024 | INTEL_INFO(dev)->cursor_needs_physical) { | |
12025 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
12026 | ret = i915_gem_object_attach_phys(obj, align); | |
12027 | if (ret) | |
12028 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
12029 | } else { | |
82bc3b2d | 12030 | ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL); |
6beb8c23 | 12031 | } |
465c120c | 12032 | |
6beb8c23 MR |
12033 | if (ret == 0) |
12034 | i915_gem_track_fb(old_obj, obj, frontbuffer_bits); | |
fdd508a6 | 12035 | |
4c34574f | 12036 | mutex_unlock(&dev->struct_mutex); |
465c120c | 12037 | |
6beb8c23 MR |
12038 | return ret; |
12039 | } | |
12040 | ||
38f3ce3a MR |
12041 | /** |
12042 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
12043 | * @plane: drm plane to clean up for | |
12044 | * @fb: old framebuffer that was on plane | |
12045 | * | |
12046 | * Cleans up a framebuffer that has just been removed from a plane. | |
12047 | */ | |
12048 | void | |
12049 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
d136dfee TU |
12050 | struct drm_framebuffer *fb, |
12051 | const struct drm_plane_state *old_state) | |
38f3ce3a MR |
12052 | { |
12053 | struct drm_device *dev = plane->dev; | |
12054 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
12055 | ||
12056 | if (WARN_ON(!obj)) | |
12057 | return; | |
12058 | ||
12059 | if (plane->type != DRM_PLANE_TYPE_CURSOR || | |
12060 | !INTEL_INFO(dev)->cursor_needs_physical) { | |
12061 | mutex_lock(&dev->struct_mutex); | |
82bc3b2d | 12062 | intel_unpin_fb_obj(fb, old_state); |
38f3ce3a MR |
12063 | mutex_unlock(&dev->struct_mutex); |
12064 | } | |
465c120c MR |
12065 | } |
12066 | ||
12067 | static int | |
3c692a41 GP |
12068 | intel_check_primary_plane(struct drm_plane *plane, |
12069 | struct intel_plane_state *state) | |
12070 | { | |
32b7eeec MR |
12071 | struct drm_device *dev = plane->dev; |
12072 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2b875c22 | 12073 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb | 12074 | struct intel_crtc *intel_crtc; |
2b875c22 | 12075 | struct drm_framebuffer *fb = state->base.fb; |
3c692a41 GP |
12076 | struct drm_rect *dest = &state->dst; |
12077 | struct drm_rect *src = &state->src; | |
12078 | const struct drm_rect *clip = &state->clip; | |
465c120c MR |
12079 | int ret; |
12080 | ||
ea2c67bb MR |
12081 | crtc = crtc ? crtc : plane->crtc; |
12082 | intel_crtc = to_intel_crtc(crtc); | |
12083 | ||
c59cb179 MR |
12084 | ret = drm_plane_helper_check_update(plane, crtc, fb, |
12085 | src, dest, clip, | |
12086 | DRM_PLANE_HELPER_NO_SCALING, | |
12087 | DRM_PLANE_HELPER_NO_SCALING, | |
12088 | false, true, &state->visible); | |
12089 | if (ret) | |
12090 | return ret; | |
465c120c | 12091 | |
32b7eeec MR |
12092 | if (intel_crtc->active) { |
12093 | intel_crtc->atomic.wait_for_flips = true; | |
12094 | ||
12095 | /* | |
12096 | * FBC does not work on some platforms for rotated | |
12097 | * planes, so disable it when rotation is not 0 and | |
12098 | * update it when rotation is set back to 0. | |
12099 | * | |
12100 | * FIXME: This is redundant with the fbc update done in | |
12101 | * the primary plane enable function except that that | |
12102 | * one is done too late. We eventually need to unify | |
12103 | * this. | |
12104 | */ | |
12105 | if (intel_crtc->primary_enabled && | |
12106 | INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && | |
e35fef21 | 12107 | dev_priv->fbc.crtc == intel_crtc && |
8e7d688b | 12108 | state->base.rotation != BIT(DRM_ROTATE_0)) { |
32b7eeec MR |
12109 | intel_crtc->atomic.disable_fbc = true; |
12110 | } | |
12111 | ||
12112 | if (state->visible) { | |
12113 | /* | |
12114 | * BDW signals flip done immediately if the plane | |
12115 | * is disabled, even if the plane enable is already | |
12116 | * armed to occur at the next vblank :( | |
12117 | */ | |
12118 | if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled) | |
12119 | intel_crtc->atomic.wait_vblank = true; | |
12120 | } | |
12121 | ||
12122 | intel_crtc->atomic.fb_bits |= | |
12123 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); | |
12124 | ||
12125 | intel_crtc->atomic.update_fbc = true; | |
0fda6568 TU |
12126 | |
12127 | /* Update watermarks on tiling changes. */ | |
12128 | if (!plane->state->fb || !state->base.fb || | |
12129 | plane->state->fb->modifier[0] != | |
12130 | state->base.fb->modifier[0]) | |
12131 | intel_crtc->atomic.update_wm = true; | |
ccc759dc GP |
12132 | } |
12133 | ||
14af293f GP |
12134 | return 0; |
12135 | } | |
12136 | ||
12137 | static void | |
12138 | intel_commit_primary_plane(struct drm_plane *plane, | |
12139 | struct intel_plane_state *state) | |
12140 | { | |
2b875c22 MR |
12141 | struct drm_crtc *crtc = state->base.crtc; |
12142 | struct drm_framebuffer *fb = state->base.fb; | |
12143 | struct drm_device *dev = plane->dev; | |
14af293f | 12144 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea2c67bb | 12145 | struct intel_crtc *intel_crtc; |
14af293f GP |
12146 | struct drm_rect *src = &state->src; |
12147 | ||
ea2c67bb MR |
12148 | crtc = crtc ? crtc : plane->crtc; |
12149 | intel_crtc = to_intel_crtc(crtc); | |
cf4c7c12 MR |
12150 | |
12151 | plane->fb = fb; | |
9dc806fc MR |
12152 | crtc->x = src->x1 >> 16; |
12153 | crtc->y = src->y1 >> 16; | |
ccc759dc | 12154 | |
ccc759dc | 12155 | if (intel_crtc->active) { |
ccc759dc | 12156 | if (state->visible) { |
ccc759dc GP |
12157 | /* FIXME: kill this fastboot hack */ |
12158 | intel_update_pipe_size(intel_crtc); | |
465c120c | 12159 | |
ccc759dc | 12160 | intel_crtc->primary_enabled = true; |
465c120c | 12161 | |
ccc759dc GP |
12162 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
12163 | crtc->x, crtc->y); | |
ccc759dc GP |
12164 | } else { |
12165 | /* | |
12166 | * If clipping results in a non-visible primary plane, | |
12167 | * we'll disable the primary plane. Note that this is | |
12168 | * a bit different than what happens if userspace | |
12169 | * explicitly disables the plane by passing fb=0 | |
12170 | * because plane->fb still gets set and pinned. | |
12171 | */ | |
12172 | intel_disable_primary_hw_plane(plane, crtc); | |
48404c1e | 12173 | } |
ccc759dc | 12174 | } |
465c120c MR |
12175 | } |
12176 | ||
32b7eeec | 12177 | static void intel_begin_crtc_commit(struct drm_crtc *crtc) |
3c692a41 | 12178 | { |
32b7eeec | 12179 | struct drm_device *dev = crtc->dev; |
140fd38d | 12180 | struct drm_i915_private *dev_priv = dev->dev_private; |
3c692a41 | 12181 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ea2c67bb MR |
12182 | struct intel_plane *intel_plane; |
12183 | struct drm_plane *p; | |
12184 | unsigned fb_bits = 0; | |
12185 | ||
12186 | /* Track fb's for any planes being disabled */ | |
12187 | list_for_each_entry(p, &dev->mode_config.plane_list, head) { | |
12188 | intel_plane = to_intel_plane(p); | |
12189 | ||
12190 | if (intel_crtc->atomic.disabled_planes & | |
12191 | (1 << drm_plane_index(p))) { | |
12192 | switch (p->type) { | |
12193 | case DRM_PLANE_TYPE_PRIMARY: | |
12194 | fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe); | |
12195 | break; | |
12196 | case DRM_PLANE_TYPE_CURSOR: | |
12197 | fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe); | |
12198 | break; | |
12199 | case DRM_PLANE_TYPE_OVERLAY: | |
12200 | fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe); | |
12201 | break; | |
12202 | } | |
3c692a41 | 12203 | |
ea2c67bb MR |
12204 | mutex_lock(&dev->struct_mutex); |
12205 | i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits); | |
12206 | mutex_unlock(&dev->struct_mutex); | |
12207 | } | |
12208 | } | |
3c692a41 | 12209 | |
32b7eeec MR |
12210 | if (intel_crtc->atomic.wait_for_flips) |
12211 | intel_crtc_wait_for_pending_flips(crtc); | |
3c692a41 | 12212 | |
32b7eeec MR |
12213 | if (intel_crtc->atomic.disable_fbc) |
12214 | intel_fbc_disable(dev); | |
3c692a41 | 12215 | |
32b7eeec MR |
12216 | if (intel_crtc->atomic.pre_disable_primary) |
12217 | intel_pre_disable_primary(crtc); | |
3c692a41 | 12218 | |
32b7eeec MR |
12219 | if (intel_crtc->atomic.update_wm) |
12220 | intel_update_watermarks(crtc); | |
3c692a41 | 12221 | |
32b7eeec | 12222 | intel_runtime_pm_get(dev_priv); |
3c692a41 | 12223 | |
c34c9ee4 MR |
12224 | /* Perform vblank evasion around commit operation */ |
12225 | if (intel_crtc->active) | |
12226 | intel_crtc->atomic.evade = | |
12227 | intel_pipe_update_start(intel_crtc, | |
12228 | &intel_crtc->atomic.start_vbl_count); | |
32b7eeec MR |
12229 | } |
12230 | ||
12231 | static void intel_finish_crtc_commit(struct drm_crtc *crtc) | |
12232 | { | |
12233 | struct drm_device *dev = crtc->dev; | |
12234 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12235 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12236 | struct drm_plane *p; | |
12237 | ||
c34c9ee4 MR |
12238 | if (intel_crtc->atomic.evade) |
12239 | intel_pipe_update_end(intel_crtc, | |
12240 | intel_crtc->atomic.start_vbl_count); | |
3c692a41 | 12241 | |
140fd38d | 12242 | intel_runtime_pm_put(dev_priv); |
3c692a41 | 12243 | |
32b7eeec MR |
12244 | if (intel_crtc->atomic.wait_vblank) |
12245 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
12246 | ||
12247 | intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits); | |
12248 | ||
12249 | if (intel_crtc->atomic.update_fbc) { | |
ccc759dc | 12250 | mutex_lock(&dev->struct_mutex); |
7ff0ebcc | 12251 | intel_fbc_update(dev); |
ccc759dc | 12252 | mutex_unlock(&dev->struct_mutex); |
38f3ce3a | 12253 | } |
3c692a41 | 12254 | |
32b7eeec MR |
12255 | if (intel_crtc->atomic.post_enable_primary) |
12256 | intel_post_enable_primary(crtc); | |
3c692a41 | 12257 | |
32b7eeec MR |
12258 | drm_for_each_legacy_plane(p, &dev->mode_config.plane_list) |
12259 | if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p)) | |
12260 | intel_update_sprite_watermarks(p, crtc, 0, 0, 0, | |
12261 | false, false); | |
12262 | ||
12263 | memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic)); | |
3c692a41 GP |
12264 | } |
12265 | ||
cf4c7c12 | 12266 | /** |
4a3b8769 MR |
12267 | * intel_plane_destroy - destroy a plane |
12268 | * @plane: plane to destroy | |
cf4c7c12 | 12269 | * |
4a3b8769 MR |
12270 | * Common destruction function for all types of planes (primary, cursor, |
12271 | * sprite). | |
cf4c7c12 | 12272 | */ |
4a3b8769 | 12273 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c MR |
12274 | { |
12275 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
12276 | drm_plane_cleanup(plane); | |
12277 | kfree(intel_plane); | |
12278 | } | |
12279 | ||
65a3fea0 | 12280 | const struct drm_plane_funcs intel_plane_funcs = { |
ff42e093 DV |
12281 | .update_plane = drm_plane_helper_update, |
12282 | .disable_plane = drm_plane_helper_disable, | |
3d7d6510 | 12283 | .destroy = intel_plane_destroy, |
c196e1d6 | 12284 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
12285 | .atomic_get_property = intel_plane_atomic_get_property, |
12286 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
12287 | .atomic_duplicate_state = intel_plane_duplicate_state, |
12288 | .atomic_destroy_state = intel_plane_destroy_state, | |
12289 | ||
465c120c MR |
12290 | }; |
12291 | ||
12292 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
12293 | int pipe) | |
12294 | { | |
12295 | struct intel_plane *primary; | |
8e7d688b | 12296 | struct intel_plane_state *state; |
465c120c MR |
12297 | const uint32_t *intel_primary_formats; |
12298 | int num_formats; | |
12299 | ||
12300 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
12301 | if (primary == NULL) | |
12302 | return NULL; | |
12303 | ||
8e7d688b MR |
12304 | state = intel_create_plane_state(&primary->base); |
12305 | if (!state) { | |
ea2c67bb MR |
12306 | kfree(primary); |
12307 | return NULL; | |
12308 | } | |
8e7d688b | 12309 | primary->base.state = &state->base; |
ea2c67bb | 12310 | |
465c120c MR |
12311 | primary->can_scale = false; |
12312 | primary->max_downscale = 1; | |
12313 | primary->pipe = pipe; | |
12314 | primary->plane = pipe; | |
c59cb179 MR |
12315 | primary->check_plane = intel_check_primary_plane; |
12316 | primary->commit_plane = intel_commit_primary_plane; | |
465c120c MR |
12317 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
12318 | primary->plane = !pipe; | |
12319 | ||
12320 | if (INTEL_INFO(dev)->gen <= 3) { | |
12321 | intel_primary_formats = intel_primary_formats_gen2; | |
12322 | num_formats = ARRAY_SIZE(intel_primary_formats_gen2); | |
12323 | } else { | |
12324 | intel_primary_formats = intel_primary_formats_gen4; | |
12325 | num_formats = ARRAY_SIZE(intel_primary_formats_gen4); | |
12326 | } | |
12327 | ||
12328 | drm_universal_plane_init(dev, &primary->base, 0, | |
65a3fea0 | 12329 | &intel_plane_funcs, |
465c120c MR |
12330 | intel_primary_formats, num_formats, |
12331 | DRM_PLANE_TYPE_PRIMARY); | |
48404c1e SJ |
12332 | |
12333 | if (INTEL_INFO(dev)->gen >= 4) { | |
12334 | if (!dev->mode_config.rotation_property) | |
12335 | dev->mode_config.rotation_property = | |
12336 | drm_mode_create_rotation_property(dev, | |
12337 | BIT(DRM_ROTATE_0) | | |
12338 | BIT(DRM_ROTATE_180)); | |
12339 | if (dev->mode_config.rotation_property) | |
12340 | drm_object_attach_property(&primary->base.base, | |
12341 | dev->mode_config.rotation_property, | |
8e7d688b | 12342 | state->base.rotation); |
48404c1e SJ |
12343 | } |
12344 | ||
ea2c67bb MR |
12345 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
12346 | ||
465c120c MR |
12347 | return &primary->base; |
12348 | } | |
12349 | ||
3d7d6510 | 12350 | static int |
852e787c GP |
12351 | intel_check_cursor_plane(struct drm_plane *plane, |
12352 | struct intel_plane_state *state) | |
3d7d6510 | 12353 | { |
2b875c22 | 12354 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb | 12355 | struct drm_device *dev = plane->dev; |
2b875c22 | 12356 | struct drm_framebuffer *fb = state->base.fb; |
852e787c GP |
12357 | struct drm_rect *dest = &state->dst; |
12358 | struct drm_rect *src = &state->src; | |
12359 | const struct drm_rect *clip = &state->clip; | |
757f9a3e | 12360 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
ea2c67bb | 12361 | struct intel_crtc *intel_crtc; |
757f9a3e GP |
12362 | unsigned stride; |
12363 | int ret; | |
3d7d6510 | 12364 | |
ea2c67bb MR |
12365 | crtc = crtc ? crtc : plane->crtc; |
12366 | intel_crtc = to_intel_crtc(crtc); | |
12367 | ||
757f9a3e | 12368 | ret = drm_plane_helper_check_update(plane, crtc, fb, |
852e787c | 12369 | src, dest, clip, |
3d7d6510 MR |
12370 | DRM_PLANE_HELPER_NO_SCALING, |
12371 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 12372 | true, true, &state->visible); |
757f9a3e GP |
12373 | if (ret) |
12374 | return ret; | |
12375 | ||
12376 | ||
12377 | /* if we want to turn off the cursor ignore width and height */ | |
12378 | if (!obj) | |
32b7eeec | 12379 | goto finish; |
757f9a3e | 12380 | |
757f9a3e | 12381 | /* Check for which cursor types we support */ |
ea2c67bb MR |
12382 | if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) { |
12383 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", | |
12384 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
12385 | return -EINVAL; |
12386 | } | |
12387 | ||
ea2c67bb MR |
12388 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
12389 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
12390 | DRM_DEBUG_KMS("buffer is too small\n"); |
12391 | return -ENOMEM; | |
12392 | } | |
12393 | ||
3a656b54 | 12394 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e GP |
12395 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
12396 | ret = -EINVAL; | |
12397 | } | |
757f9a3e | 12398 | |
32b7eeec MR |
12399 | finish: |
12400 | if (intel_crtc->active) { | |
3749f463 | 12401 | if (plane->state->crtc_w != state->base.crtc_w) |
32b7eeec MR |
12402 | intel_crtc->atomic.update_wm = true; |
12403 | ||
12404 | intel_crtc->atomic.fb_bits |= | |
12405 | INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe); | |
12406 | } | |
12407 | ||
757f9a3e | 12408 | return ret; |
852e787c | 12409 | } |
3d7d6510 | 12410 | |
f4a2cf29 | 12411 | static void |
852e787c GP |
12412 | intel_commit_cursor_plane(struct drm_plane *plane, |
12413 | struct intel_plane_state *state) | |
12414 | { | |
2b875c22 | 12415 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb MR |
12416 | struct drm_device *dev = plane->dev; |
12417 | struct intel_crtc *intel_crtc; | |
2b875c22 | 12418 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 12419 | uint32_t addr; |
852e787c | 12420 | |
ea2c67bb MR |
12421 | crtc = crtc ? crtc : plane->crtc; |
12422 | intel_crtc = to_intel_crtc(crtc); | |
12423 | ||
2b875c22 | 12424 | plane->fb = state->base.fb; |
ea2c67bb MR |
12425 | crtc->cursor_x = state->base.crtc_x; |
12426 | crtc->cursor_y = state->base.crtc_y; | |
12427 | ||
a912f12f GP |
12428 | if (intel_crtc->cursor_bo == obj) |
12429 | goto update; | |
4ed91096 | 12430 | |
f4a2cf29 | 12431 | if (!obj) |
a912f12f | 12432 | addr = 0; |
f4a2cf29 | 12433 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 12434 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 12435 | else |
a912f12f | 12436 | addr = obj->phys_handle->busaddr; |
852e787c | 12437 | |
a912f12f GP |
12438 | intel_crtc->cursor_addr = addr; |
12439 | intel_crtc->cursor_bo = obj; | |
12440 | update: | |
852e787c | 12441 | |
32b7eeec | 12442 | if (intel_crtc->active) |
a912f12f | 12443 | intel_crtc_update_cursor(crtc, state->visible); |
852e787c GP |
12444 | } |
12445 | ||
3d7d6510 MR |
12446 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
12447 | int pipe) | |
12448 | { | |
12449 | struct intel_plane *cursor; | |
8e7d688b | 12450 | struct intel_plane_state *state; |
3d7d6510 MR |
12451 | |
12452 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
12453 | if (cursor == NULL) | |
12454 | return NULL; | |
12455 | ||
8e7d688b MR |
12456 | state = intel_create_plane_state(&cursor->base); |
12457 | if (!state) { | |
ea2c67bb MR |
12458 | kfree(cursor); |
12459 | return NULL; | |
12460 | } | |
8e7d688b | 12461 | cursor->base.state = &state->base; |
ea2c67bb | 12462 | |
3d7d6510 MR |
12463 | cursor->can_scale = false; |
12464 | cursor->max_downscale = 1; | |
12465 | cursor->pipe = pipe; | |
12466 | cursor->plane = pipe; | |
c59cb179 MR |
12467 | cursor->check_plane = intel_check_cursor_plane; |
12468 | cursor->commit_plane = intel_commit_cursor_plane; | |
3d7d6510 MR |
12469 | |
12470 | drm_universal_plane_init(dev, &cursor->base, 0, | |
65a3fea0 | 12471 | &intel_plane_funcs, |
3d7d6510 MR |
12472 | intel_cursor_formats, |
12473 | ARRAY_SIZE(intel_cursor_formats), | |
12474 | DRM_PLANE_TYPE_CURSOR); | |
4398ad45 VS |
12475 | |
12476 | if (INTEL_INFO(dev)->gen >= 4) { | |
12477 | if (!dev->mode_config.rotation_property) | |
12478 | dev->mode_config.rotation_property = | |
12479 | drm_mode_create_rotation_property(dev, | |
12480 | BIT(DRM_ROTATE_0) | | |
12481 | BIT(DRM_ROTATE_180)); | |
12482 | if (dev->mode_config.rotation_property) | |
12483 | drm_object_attach_property(&cursor->base.base, | |
12484 | dev->mode_config.rotation_property, | |
8e7d688b | 12485 | state->base.rotation); |
4398ad45 VS |
12486 | } |
12487 | ||
ea2c67bb MR |
12488 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
12489 | ||
3d7d6510 MR |
12490 | return &cursor->base; |
12491 | } | |
12492 | ||
b358d0a6 | 12493 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 12494 | { |
fbee40df | 12495 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 12496 | struct intel_crtc *intel_crtc; |
f5de6e07 | 12497 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
12498 | struct drm_plane *primary = NULL; |
12499 | struct drm_plane *cursor = NULL; | |
465c120c | 12500 | int i, ret; |
79e53945 | 12501 | |
955382f3 | 12502 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
12503 | if (intel_crtc == NULL) |
12504 | return; | |
12505 | ||
f5de6e07 ACO |
12506 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
12507 | if (!crtc_state) | |
12508 | goto fail; | |
12509 | intel_crtc_set_state(intel_crtc, crtc_state); | |
07878248 | 12510 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 12511 | |
465c120c | 12512 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
12513 | if (!primary) |
12514 | goto fail; | |
12515 | ||
12516 | cursor = intel_cursor_plane_create(dev, pipe); | |
12517 | if (!cursor) | |
12518 | goto fail; | |
12519 | ||
465c120c | 12520 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
3d7d6510 MR |
12521 | cursor, &intel_crtc_funcs); |
12522 | if (ret) | |
12523 | goto fail; | |
79e53945 JB |
12524 | |
12525 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
12526 | for (i = 0; i < 256; i++) { |
12527 | intel_crtc->lut_r[i] = i; | |
12528 | intel_crtc->lut_g[i] = i; | |
12529 | intel_crtc->lut_b[i] = i; | |
12530 | } | |
12531 | ||
1f1c2e24 VS |
12532 | /* |
12533 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 12534 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 12535 | */ |
80824003 JB |
12536 | intel_crtc->pipe = pipe; |
12537 | intel_crtc->plane = pipe; | |
3a77c4c4 | 12538 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 12539 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 12540 | intel_crtc->plane = !pipe; |
80824003 JB |
12541 | } |
12542 | ||
4b0e333e CW |
12543 | intel_crtc->cursor_base = ~0; |
12544 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 12545 | intel_crtc->cursor_size = ~0; |
8d7849db | 12546 | |
22fd0fab JB |
12547 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
12548 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
12549 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
12550 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
12551 | ||
9362c7c5 ACO |
12552 | INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func); |
12553 | ||
79e53945 | 12554 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 DV |
12555 | |
12556 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); | |
3d7d6510 MR |
12557 | return; |
12558 | ||
12559 | fail: | |
12560 | if (primary) | |
12561 | drm_plane_cleanup(primary); | |
12562 | if (cursor) | |
12563 | drm_plane_cleanup(cursor); | |
f5de6e07 | 12564 | kfree(crtc_state); |
3d7d6510 | 12565 | kfree(intel_crtc); |
79e53945 JB |
12566 | } |
12567 | ||
752aa88a JB |
12568 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
12569 | { | |
12570 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 12571 | struct drm_device *dev = connector->base.dev; |
752aa88a | 12572 | |
51fd371b | 12573 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 12574 | |
d3babd3f | 12575 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
12576 | return INVALID_PIPE; |
12577 | ||
12578 | return to_intel_crtc(encoder->crtc)->pipe; | |
12579 | } | |
12580 | ||
08d7b3d1 | 12581 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 12582 | struct drm_file *file) |
08d7b3d1 | 12583 | { |
08d7b3d1 | 12584 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 12585 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 12586 | struct intel_crtc *crtc; |
08d7b3d1 | 12587 | |
7707e653 | 12588 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 12589 | |
7707e653 | 12590 | if (!drmmode_crtc) { |
08d7b3d1 | 12591 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 12592 | return -ENOENT; |
08d7b3d1 CW |
12593 | } |
12594 | ||
7707e653 | 12595 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 12596 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 12597 | |
c05422d5 | 12598 | return 0; |
08d7b3d1 CW |
12599 | } |
12600 | ||
66a9278e | 12601 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 12602 | { |
66a9278e DV |
12603 | struct drm_device *dev = encoder->base.dev; |
12604 | struct intel_encoder *source_encoder; | |
79e53945 | 12605 | int index_mask = 0; |
79e53945 JB |
12606 | int entry = 0; |
12607 | ||
b2784e15 | 12608 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 12609 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
12610 | index_mask |= (1 << entry); |
12611 | ||
79e53945 JB |
12612 | entry++; |
12613 | } | |
4ef69c7a | 12614 | |
79e53945 JB |
12615 | return index_mask; |
12616 | } | |
12617 | ||
4d302442 CW |
12618 | static bool has_edp_a(struct drm_device *dev) |
12619 | { | |
12620 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12621 | ||
12622 | if (!IS_MOBILE(dev)) | |
12623 | return false; | |
12624 | ||
12625 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
12626 | return false; | |
12627 | ||
e3589908 | 12628 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
12629 | return false; |
12630 | ||
12631 | return true; | |
12632 | } | |
12633 | ||
84b4e042 JB |
12634 | static bool intel_crt_present(struct drm_device *dev) |
12635 | { | |
12636 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12637 | ||
884497ed DL |
12638 | if (INTEL_INFO(dev)->gen >= 9) |
12639 | return false; | |
12640 | ||
cf404ce4 | 12641 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
12642 | return false; |
12643 | ||
12644 | if (IS_CHERRYVIEW(dev)) | |
12645 | return false; | |
12646 | ||
12647 | if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support) | |
12648 | return false; | |
12649 | ||
12650 | return true; | |
12651 | } | |
12652 | ||
79e53945 JB |
12653 | static void intel_setup_outputs(struct drm_device *dev) |
12654 | { | |
725e30ad | 12655 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 12656 | struct intel_encoder *encoder; |
c6f95f27 | 12657 | struct drm_connector *connector; |
cb0953d7 | 12658 | bool dpd_is_edp = false; |
79e53945 | 12659 | |
c9093354 | 12660 | intel_lvds_init(dev); |
79e53945 | 12661 | |
84b4e042 | 12662 | if (intel_crt_present(dev)) |
79935fca | 12663 | intel_crt_init(dev); |
cb0953d7 | 12664 | |
affa9354 | 12665 | if (HAS_DDI(dev)) { |
0e72a5b5 ED |
12666 | int found; |
12667 | ||
de31facd JB |
12668 | /* |
12669 | * Haswell uses DDI functions to detect digital outputs. | |
12670 | * On SKL pre-D0 the strap isn't connected, so we assume | |
12671 | * it's there. | |
12672 | */ | |
0e72a5b5 | 12673 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; |
de31facd JB |
12674 | /* WaIgnoreDDIAStrap: skl */ |
12675 | if (found || | |
12676 | (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0)) | |
0e72a5b5 ED |
12677 | intel_ddi_init(dev, PORT_A); |
12678 | ||
12679 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
12680 | * register */ | |
12681 | found = I915_READ(SFUSE_STRAP); | |
12682 | ||
12683 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
12684 | intel_ddi_init(dev, PORT_B); | |
12685 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
12686 | intel_ddi_init(dev, PORT_C); | |
12687 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
12688 | intel_ddi_init(dev, PORT_D); | |
12689 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 12690 | int found; |
5d8a7752 | 12691 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
12692 | |
12693 | if (has_edp_a(dev)) | |
12694 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 12695 | |
dc0fa718 | 12696 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 12697 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 12698 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 12699 | if (!found) |
e2debe91 | 12700 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 12701 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 12702 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
12703 | } |
12704 | ||
dc0fa718 | 12705 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 12706 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 12707 | |
dc0fa718 | 12708 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 12709 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 12710 | |
5eb08b69 | 12711 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 12712 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 12713 | |
270b3042 | 12714 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 12715 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 12716 | } else if (IS_VALLEYVIEW(dev)) { |
e17ac6db VS |
12717 | /* |
12718 | * The DP_DETECTED bit is the latched state of the DDC | |
12719 | * SDA pin at boot. However since eDP doesn't require DDC | |
12720 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
12721 | * eDP ports may have been muxed to an alternate function. | |
12722 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
12723 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
12724 | * detect eDP ports. | |
12725 | */ | |
d2182a66 VS |
12726 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED && |
12727 | !intel_dp_is_edp(dev, PORT_B)) | |
585a94b8 AB |
12728 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, |
12729 | PORT_B); | |
e17ac6db VS |
12730 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED || |
12731 | intel_dp_is_edp(dev, PORT_B)) | |
12732 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
585a94b8 | 12733 | |
d2182a66 VS |
12734 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED && |
12735 | !intel_dp_is_edp(dev, PORT_C)) | |
6f6005a5 JB |
12736 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, |
12737 | PORT_C); | |
e17ac6db VS |
12738 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED || |
12739 | intel_dp_is_edp(dev, PORT_C)) | |
12740 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); | |
19c03924 | 12741 | |
9418c1f1 | 12742 | if (IS_CHERRYVIEW(dev)) { |
e17ac6db | 12743 | if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) |
9418c1f1 VS |
12744 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID, |
12745 | PORT_D); | |
e17ac6db VS |
12746 | /* eDP not supported on port D, so don't check VBT */ |
12747 | if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED) | |
12748 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D); | |
9418c1f1 VS |
12749 | } |
12750 | ||
3cfca973 | 12751 | intel_dsi_init(dev); |
103a196f | 12752 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 12753 | bool found = false; |
7d57382e | 12754 | |
e2debe91 | 12755 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 12756 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 12757 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
b01f2c3a JB |
12758 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
12759 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
e2debe91 | 12760 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 12761 | } |
27185ae1 | 12762 | |
e7281eab | 12763 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 12764 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 12765 | } |
13520b05 KH |
12766 | |
12767 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 12768 | |
e2debe91 | 12769 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 12770 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 12771 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 12772 | } |
27185ae1 | 12773 | |
e2debe91 | 12774 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 12775 | |
b01f2c3a JB |
12776 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
12777 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
e2debe91 | 12778 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 12779 | } |
e7281eab | 12780 | if (SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 12781 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 12782 | } |
27185ae1 | 12783 | |
b01f2c3a | 12784 | if (SUPPORTS_INTEGRATED_DP(dev) && |
e7281eab | 12785 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 12786 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 12787 | } else if (IS_GEN2(dev)) |
79e53945 JB |
12788 | intel_dvo_init(dev); |
12789 | ||
103a196f | 12790 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
12791 | intel_tv_init(dev); |
12792 | ||
c6f95f27 MR |
12793 | /* |
12794 | * FIXME: We don't have full atomic support yet, but we want to be | |
12795 | * able to enable/test plane updates via the atomic interface in the | |
12796 | * meantime. However as soon as we flip DRIVER_ATOMIC on, the DRM core | |
12797 | * will take some atomic codepaths to lookup properties during | |
12798 | * drmModeGetConnector() that unconditionally dereference | |
12799 | * connector->state. | |
12800 | * | |
12801 | * We create a dummy connector state here for each connector to ensure | |
12802 | * the DRM core doesn't try to dereference a NULL connector->state. | |
12803 | * The actual connector properties will never be updated or contain | |
12804 | * useful information, but since we're doing this specifically for | |
12805 | * testing/debug of the plane operations (and only when a specific | |
12806 | * kernel module option is given), that shouldn't really matter. | |
12807 | * | |
12808 | * Once atomic support for crtc's + connectors lands, this loop should | |
12809 | * be removed since we'll be setting up real connector state, which | |
12810 | * will contain Intel-specific properties. | |
12811 | */ | |
12812 | if (drm_core_check_feature(dev, DRIVER_ATOMIC)) { | |
12813 | list_for_each_entry(connector, | |
12814 | &dev->mode_config.connector_list, | |
12815 | head) { | |
12816 | if (!WARN_ON(connector->state)) { | |
12817 | connector->state = | |
12818 | kzalloc(sizeof(*connector->state), | |
12819 | GFP_KERNEL); | |
12820 | } | |
12821 | } | |
12822 | } | |
12823 | ||
0bc12bcb | 12824 | intel_psr_init(dev); |
7c8f8a70 | 12825 | |
b2784e15 | 12826 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
12827 | encoder->base.possible_crtcs = encoder->crtc_mask; |
12828 | encoder->base.possible_clones = | |
66a9278e | 12829 | intel_encoder_clones(encoder); |
79e53945 | 12830 | } |
47356eb6 | 12831 | |
dde86e2d | 12832 | intel_init_pch_refclk(dev); |
270b3042 DV |
12833 | |
12834 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
12835 | } |
12836 | ||
12837 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
12838 | { | |
60a5ca01 | 12839 | struct drm_device *dev = fb->dev; |
79e53945 | 12840 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 12841 | |
ef2d633e | 12842 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 12843 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 12844 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
12845 | drm_gem_object_unreference(&intel_fb->obj->base); |
12846 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
12847 | kfree(intel_fb); |
12848 | } | |
12849 | ||
12850 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 12851 | struct drm_file *file, |
79e53945 JB |
12852 | unsigned int *handle) |
12853 | { | |
12854 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 12855 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 12856 | |
05394f39 | 12857 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
12858 | } |
12859 | ||
12860 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
12861 | .destroy = intel_user_framebuffer_destroy, | |
12862 | .create_handle = intel_user_framebuffer_create_handle, | |
12863 | }; | |
12864 | ||
b321803d DL |
12865 | static |
12866 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
12867 | uint32_t pixel_format) | |
12868 | { | |
12869 | u32 gen = INTEL_INFO(dev)->gen; | |
12870 | ||
12871 | if (gen >= 9) { | |
12872 | /* "The stride in bytes must not exceed the of the size of 8K | |
12873 | * pixels and 32K bytes." | |
12874 | */ | |
12875 | return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768); | |
12876 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) { | |
12877 | return 32*1024; | |
12878 | } else if (gen >= 4) { | |
12879 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
12880 | return 16*1024; | |
12881 | else | |
12882 | return 32*1024; | |
12883 | } else if (gen >= 3) { | |
12884 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
12885 | return 8*1024; | |
12886 | else | |
12887 | return 16*1024; | |
12888 | } else { | |
12889 | /* XXX DSPC is limited to 4k tiled */ | |
12890 | return 8*1024; | |
12891 | } | |
12892 | } | |
12893 | ||
b5ea642a DV |
12894 | static int intel_framebuffer_init(struct drm_device *dev, |
12895 | struct intel_framebuffer *intel_fb, | |
12896 | struct drm_mode_fb_cmd2 *mode_cmd, | |
12897 | struct drm_i915_gem_object *obj) | |
79e53945 | 12898 | { |
6761dd31 | 12899 | unsigned int aligned_height; |
79e53945 | 12900 | int ret; |
b321803d | 12901 | u32 pitch_limit, stride_alignment; |
79e53945 | 12902 | |
dd4916c5 DV |
12903 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
12904 | ||
2a80eada DV |
12905 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
12906 | /* Enforce that fb modifier and tiling mode match, but only for | |
12907 | * X-tiled. This is needed for FBC. */ | |
12908 | if (!!(obj->tiling_mode == I915_TILING_X) != | |
12909 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { | |
12910 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
12911 | return -EINVAL; | |
12912 | } | |
12913 | } else { | |
12914 | if (obj->tiling_mode == I915_TILING_X) | |
12915 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
12916 | else if (obj->tiling_mode == I915_TILING_Y) { | |
12917 | DRM_DEBUG("No Y tiling for legacy addfb\n"); | |
12918 | return -EINVAL; | |
12919 | } | |
12920 | } | |
12921 | ||
9a8f0a12 TU |
12922 | /* Passed in modifier sanity checking. */ |
12923 | switch (mode_cmd->modifier[0]) { | |
12924 | case I915_FORMAT_MOD_Y_TILED: | |
12925 | case I915_FORMAT_MOD_Yf_TILED: | |
12926 | if (INTEL_INFO(dev)->gen < 9) { | |
12927 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
12928 | mode_cmd->modifier[0]); | |
12929 | return -EINVAL; | |
12930 | } | |
12931 | case DRM_FORMAT_MOD_NONE: | |
12932 | case I915_FORMAT_MOD_X_TILED: | |
12933 | break; | |
12934 | default: | |
12935 | DRM_ERROR("Unsupported fb modifier 0x%llx!\n", | |
12936 | mode_cmd->modifier[0]); | |
57cd6508 | 12937 | return -EINVAL; |
c16ed4be | 12938 | } |
57cd6508 | 12939 | |
b321803d DL |
12940 | stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0], |
12941 | mode_cmd->pixel_format); | |
12942 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
12943 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
12944 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 12945 | return -EINVAL; |
c16ed4be | 12946 | } |
57cd6508 | 12947 | |
b321803d DL |
12948 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
12949 | mode_cmd->pixel_format); | |
a35cdaa0 | 12950 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
12951 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
12952 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 12953 | "tiled" : "linear", |
a35cdaa0 | 12954 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 12955 | return -EINVAL; |
c16ed4be | 12956 | } |
5d7bd705 | 12957 | |
2a80eada | 12958 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
c16ed4be CW |
12959 | mode_cmd->pitches[0] != obj->stride) { |
12960 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
12961 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 12962 | return -EINVAL; |
c16ed4be | 12963 | } |
5d7bd705 | 12964 | |
57779d06 | 12965 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 12966 | switch (mode_cmd->pixel_format) { |
57779d06 | 12967 | case DRM_FORMAT_C8: |
04b3924d VS |
12968 | case DRM_FORMAT_RGB565: |
12969 | case DRM_FORMAT_XRGB8888: | |
12970 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
12971 | break; |
12972 | case DRM_FORMAT_XRGB1555: | |
12973 | case DRM_FORMAT_ARGB1555: | |
c16ed4be | 12974 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
12975 | DRM_DEBUG("unsupported pixel format: %s\n", |
12976 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 12977 | return -EINVAL; |
c16ed4be | 12978 | } |
57779d06 VS |
12979 | break; |
12980 | case DRM_FORMAT_XBGR8888: | |
12981 | case DRM_FORMAT_ABGR8888: | |
04b3924d VS |
12982 | case DRM_FORMAT_XRGB2101010: |
12983 | case DRM_FORMAT_ARGB2101010: | |
57779d06 VS |
12984 | case DRM_FORMAT_XBGR2101010: |
12985 | case DRM_FORMAT_ABGR2101010: | |
c16ed4be | 12986 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
12987 | DRM_DEBUG("unsupported pixel format: %s\n", |
12988 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 12989 | return -EINVAL; |
c16ed4be | 12990 | } |
b5626747 | 12991 | break; |
04b3924d VS |
12992 | case DRM_FORMAT_YUYV: |
12993 | case DRM_FORMAT_UYVY: | |
12994 | case DRM_FORMAT_YVYU: | |
12995 | case DRM_FORMAT_VYUY: | |
c16ed4be | 12996 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
12997 | DRM_DEBUG("unsupported pixel format: %s\n", |
12998 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 12999 | return -EINVAL; |
c16ed4be | 13000 | } |
57cd6508 CW |
13001 | break; |
13002 | default: | |
4ee62c76 VS |
13003 | DRM_DEBUG("unsupported pixel format: %s\n", |
13004 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
13005 | return -EINVAL; |
13006 | } | |
13007 | ||
90f9a336 VS |
13008 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
13009 | if (mode_cmd->offsets[0] != 0) | |
13010 | return -EINVAL; | |
13011 | ||
ec2c981e | 13012 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
091df6cb DV |
13013 | mode_cmd->pixel_format, |
13014 | mode_cmd->modifier[0]); | |
53155c0a DV |
13015 | /* FIXME drm helper for size checks (especially planar formats)? */ |
13016 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
13017 | return -EINVAL; | |
13018 | ||
c7d73f6a DV |
13019 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
13020 | intel_fb->obj = obj; | |
80075d49 | 13021 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 13022 | |
79e53945 JB |
13023 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
13024 | if (ret) { | |
13025 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
13026 | return ret; | |
13027 | } | |
13028 | ||
79e53945 JB |
13029 | return 0; |
13030 | } | |
13031 | ||
79e53945 JB |
13032 | static struct drm_framebuffer * |
13033 | intel_user_framebuffer_create(struct drm_device *dev, | |
13034 | struct drm_file *filp, | |
308e5bcb | 13035 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 13036 | { |
05394f39 | 13037 | struct drm_i915_gem_object *obj; |
79e53945 | 13038 | |
308e5bcb JB |
13039 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
13040 | mode_cmd->handles[0])); | |
c8725226 | 13041 | if (&obj->base == NULL) |
cce13ff7 | 13042 | return ERR_PTR(-ENOENT); |
79e53945 | 13043 | |
d2dff872 | 13044 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
13045 | } |
13046 | ||
4520f53a | 13047 | #ifndef CONFIG_DRM_I915_FBDEV |
0632fef6 | 13048 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
13049 | { |
13050 | } | |
13051 | #endif | |
13052 | ||
79e53945 | 13053 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 13054 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 13055 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
13056 | .atomic_check = intel_atomic_check, |
13057 | .atomic_commit = intel_atomic_commit, | |
79e53945 JB |
13058 | }; |
13059 | ||
e70236a8 JB |
13060 | /* Set up chip specific display functions */ |
13061 | static void intel_init_display(struct drm_device *dev) | |
13062 | { | |
13063 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13064 | ||
ee9300bb DV |
13065 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
13066 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
13067 | else if (IS_CHERRYVIEW(dev)) |
13068 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
13069 | else if (IS_VALLEYVIEW(dev)) |
13070 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
13071 | else if (IS_PINEVIEW(dev)) | |
13072 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
13073 | else | |
13074 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
13075 | ||
bc8d7dff DL |
13076 | if (INTEL_INFO(dev)->gen >= 9) { |
13077 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; | |
5724dbd1 DL |
13078 | dev_priv->display.get_initial_plane_config = |
13079 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
13080 | dev_priv->display.crtc_compute_clock = |
13081 | haswell_crtc_compute_clock; | |
13082 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
13083 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
13084 | dev_priv->display.off = ironlake_crtc_off; | |
13085 | dev_priv->display.update_primary_plane = | |
13086 | skylake_update_primary_plane; | |
13087 | } else if (HAS_DDI(dev)) { | |
0e8ffe1b | 13088 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
13089 | dev_priv->display.get_initial_plane_config = |
13090 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
13091 | dev_priv->display.crtc_compute_clock = |
13092 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
13093 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
13094 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
df8ad70c | 13095 | dev_priv->display.off = ironlake_crtc_off; |
bc8d7dff DL |
13096 | dev_priv->display.update_primary_plane = |
13097 | ironlake_update_primary_plane; | |
09b4ddf9 | 13098 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 13099 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
13100 | dev_priv->display.get_initial_plane_config = |
13101 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
13102 | dev_priv->display.crtc_compute_clock = |
13103 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
13104 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
13105 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
ee7b9f93 | 13106 | dev_priv->display.off = ironlake_crtc_off; |
262ca2b0 MR |
13107 | dev_priv->display.update_primary_plane = |
13108 | ironlake_update_primary_plane; | |
89b667f8 JB |
13109 | } else if (IS_VALLEYVIEW(dev)) { |
13110 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
5724dbd1 DL |
13111 | dev_priv->display.get_initial_plane_config = |
13112 | i9xx_get_initial_plane_config; | |
d6dfee7a | 13113 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
89b667f8 JB |
13114 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
13115 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
13116 | dev_priv->display.off = i9xx_crtc_off; | |
262ca2b0 MR |
13117 | dev_priv->display.update_primary_plane = |
13118 | i9xx_update_primary_plane; | |
f564048e | 13119 | } else { |
0e8ffe1b | 13120 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
13121 | dev_priv->display.get_initial_plane_config = |
13122 | i9xx_get_initial_plane_config; | |
d6dfee7a | 13123 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
13124 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
13125 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
ee7b9f93 | 13126 | dev_priv->display.off = i9xx_crtc_off; |
262ca2b0 MR |
13127 | dev_priv->display.update_primary_plane = |
13128 | i9xx_update_primary_plane; | |
f564048e | 13129 | } |
e70236a8 | 13130 | |
e70236a8 | 13131 | /* Returns the core display clock speed */ |
25eb05fc JB |
13132 | if (IS_VALLEYVIEW(dev)) |
13133 | dev_priv->display.get_display_clock_speed = | |
13134 | valleyview_get_display_clock_speed; | |
13135 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
13136 | dev_priv->display.get_display_clock_speed = |
13137 | i945_get_display_clock_speed; | |
13138 | else if (IS_I915G(dev)) | |
13139 | dev_priv->display.get_display_clock_speed = | |
13140 | i915_get_display_clock_speed; | |
257a7ffc | 13141 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
13142 | dev_priv->display.get_display_clock_speed = |
13143 | i9xx_misc_get_display_clock_speed; | |
257a7ffc DV |
13144 | else if (IS_PINEVIEW(dev)) |
13145 | dev_priv->display.get_display_clock_speed = | |
13146 | pnv_get_display_clock_speed; | |
e70236a8 JB |
13147 | else if (IS_I915GM(dev)) |
13148 | dev_priv->display.get_display_clock_speed = | |
13149 | i915gm_get_display_clock_speed; | |
13150 | else if (IS_I865G(dev)) | |
13151 | dev_priv->display.get_display_clock_speed = | |
13152 | i865_get_display_clock_speed; | |
f0f8a9ce | 13153 | else if (IS_I85X(dev)) |
e70236a8 JB |
13154 | dev_priv->display.get_display_clock_speed = |
13155 | i855_get_display_clock_speed; | |
13156 | else /* 852, 830 */ | |
13157 | dev_priv->display.get_display_clock_speed = | |
13158 | i830_get_display_clock_speed; | |
13159 | ||
7c10a2b5 | 13160 | if (IS_GEN5(dev)) { |
3bb11b53 | 13161 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
3bb11b53 SJ |
13162 | } else if (IS_GEN6(dev)) { |
13163 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; | |
3bb11b53 SJ |
13164 | } else if (IS_IVYBRIDGE(dev)) { |
13165 | /* FIXME: detect B0+ stepping and use auto training */ | |
13166 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
059b2fe9 | 13167 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
3bb11b53 | 13168 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
30a970c6 JB |
13169 | } else if (IS_VALLEYVIEW(dev)) { |
13170 | dev_priv->display.modeset_global_resources = | |
13171 | valleyview_modeset_global_resources; | |
e70236a8 | 13172 | } |
8c9f3aaf | 13173 | |
8c9f3aaf JB |
13174 | switch (INTEL_INFO(dev)->gen) { |
13175 | case 2: | |
13176 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
13177 | break; | |
13178 | ||
13179 | case 3: | |
13180 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
13181 | break; | |
13182 | ||
13183 | case 4: | |
13184 | case 5: | |
13185 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
13186 | break; | |
13187 | ||
13188 | case 6: | |
13189 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
13190 | break; | |
7c9017e5 | 13191 | case 7: |
4e0bbc31 | 13192 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
13193 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
13194 | break; | |
830c81db | 13195 | case 9: |
ba343e02 TU |
13196 | /* Drop through - unsupported since execlist only. */ |
13197 | default: | |
13198 | /* Default just returns -ENODEV to indicate unsupported */ | |
13199 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8c9f3aaf | 13200 | } |
7bd688cd JN |
13201 | |
13202 | intel_panel_init_backlight_funcs(dev); | |
e39b999a VS |
13203 | |
13204 | mutex_init(&dev_priv->pps_mutex); | |
e70236a8 JB |
13205 | } |
13206 | ||
b690e96c JB |
13207 | /* |
13208 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
13209 | * resume, or other times. This quirk makes sure that's the case for | |
13210 | * affected systems. | |
13211 | */ | |
0206e353 | 13212 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
13213 | { |
13214 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13215 | ||
13216 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 13217 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
13218 | } |
13219 | ||
b6b5d049 VS |
13220 | static void quirk_pipeb_force(struct drm_device *dev) |
13221 | { | |
13222 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13223 | ||
13224 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
13225 | DRM_INFO("applying pipe b force quirk\n"); | |
13226 | } | |
13227 | ||
435793df KP |
13228 | /* |
13229 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
13230 | */ | |
13231 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
13232 | { | |
13233 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13234 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 13235 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
13236 | } |
13237 | ||
4dca20ef | 13238 | /* |
5a15ab5b CE |
13239 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
13240 | * brightness value | |
4dca20ef CE |
13241 | */ |
13242 | static void quirk_invert_brightness(struct drm_device *dev) | |
13243 | { | |
13244 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13245 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 13246 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
13247 | } |
13248 | ||
9c72cc6f SD |
13249 | /* Some VBT's incorrectly indicate no backlight is present */ |
13250 | static void quirk_backlight_present(struct drm_device *dev) | |
13251 | { | |
13252 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13253 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
13254 | DRM_INFO("applying backlight present quirk\n"); | |
13255 | } | |
13256 | ||
b690e96c JB |
13257 | struct intel_quirk { |
13258 | int device; | |
13259 | int subsystem_vendor; | |
13260 | int subsystem_device; | |
13261 | void (*hook)(struct drm_device *dev); | |
13262 | }; | |
13263 | ||
5f85f176 EE |
13264 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
13265 | struct intel_dmi_quirk { | |
13266 | void (*hook)(struct drm_device *dev); | |
13267 | const struct dmi_system_id (*dmi_id_list)[]; | |
13268 | }; | |
13269 | ||
13270 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
13271 | { | |
13272 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
13273 | return 1; | |
13274 | } | |
13275 | ||
13276 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
13277 | { | |
13278 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
13279 | { | |
13280 | .callback = intel_dmi_reverse_brightness, | |
13281 | .ident = "NCR Corporation", | |
13282 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
13283 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
13284 | }, | |
13285 | }, | |
13286 | { } /* terminating entry */ | |
13287 | }, | |
13288 | .hook = quirk_invert_brightness, | |
13289 | }, | |
13290 | }; | |
13291 | ||
c43b5634 | 13292 | static struct intel_quirk intel_quirks[] = { |
b690e96c | 13293 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 13294 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c | 13295 | |
b690e96c JB |
13296 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
13297 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
13298 | ||
b690e96c JB |
13299 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
13300 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
13301 | ||
5f080c0f VS |
13302 | /* 830 needs to leave pipe A & dpll A up */ |
13303 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
13304 | ||
b6b5d049 VS |
13305 | /* 830 needs to leave pipe B & dpll B up */ |
13306 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
13307 | ||
435793df KP |
13308 | /* Lenovo U160 cannot use SSC on LVDS */ |
13309 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
13310 | |
13311 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
13312 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 13313 | |
be505f64 AH |
13314 | /* Acer Aspire 5734Z must invert backlight brightness */ |
13315 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
13316 | ||
13317 | /* Acer/eMachines G725 */ | |
13318 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
13319 | ||
13320 | /* Acer/eMachines e725 */ | |
13321 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
13322 | ||
13323 | /* Acer/Packard Bell NCL20 */ | |
13324 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
13325 | ||
13326 | /* Acer Aspire 4736Z */ | |
13327 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
13328 | |
13329 | /* Acer Aspire 5336 */ | |
13330 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
13331 | |
13332 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
13333 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 13334 | |
dfb3d47b SD |
13335 | /* Acer C720 Chromebook (Core i3 4005U) */ |
13336 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
13337 | ||
b2a9601c | 13338 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
13339 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
13340 | ||
d4967d8c SD |
13341 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
13342 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
13343 | |
13344 | /* HP Chromebook 14 (Celeron 2955U) */ | |
13345 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
13346 | |
13347 | /* Dell Chromebook 11 */ | |
13348 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
13349 | }; |
13350 | ||
13351 | static void intel_init_quirks(struct drm_device *dev) | |
13352 | { | |
13353 | struct pci_dev *d = dev->pdev; | |
13354 | int i; | |
13355 | ||
13356 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
13357 | struct intel_quirk *q = &intel_quirks[i]; | |
13358 | ||
13359 | if (d->device == q->device && | |
13360 | (d->subsystem_vendor == q->subsystem_vendor || | |
13361 | q->subsystem_vendor == PCI_ANY_ID) && | |
13362 | (d->subsystem_device == q->subsystem_device || | |
13363 | q->subsystem_device == PCI_ANY_ID)) | |
13364 | q->hook(dev); | |
13365 | } | |
5f85f176 EE |
13366 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
13367 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
13368 | intel_dmi_quirks[i].hook(dev); | |
13369 | } | |
b690e96c JB |
13370 | } |
13371 | ||
9cce37f4 JB |
13372 | /* Disable the VGA plane that we never use */ |
13373 | static void i915_disable_vga(struct drm_device *dev) | |
13374 | { | |
13375 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13376 | u8 sr1; | |
766aa1c4 | 13377 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 13378 | |
2b37c616 | 13379 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 13380 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 13381 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
13382 | sr1 = inb(VGA_SR_DATA); |
13383 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
13384 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
13385 | udelay(300); | |
13386 | ||
01f5a626 | 13387 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
13388 | POSTING_READ(vga_reg); |
13389 | } | |
13390 | ||
f817586c DV |
13391 | void intel_modeset_init_hw(struct drm_device *dev) |
13392 | { | |
a8f78b58 ED |
13393 | intel_prepare_ddi(dev); |
13394 | ||
f8bf63fd VS |
13395 | if (IS_VALLEYVIEW(dev)) |
13396 | vlv_update_cdclk(dev); | |
13397 | ||
f817586c DV |
13398 | intel_init_clock_gating(dev); |
13399 | ||
8090c6b9 | 13400 | intel_enable_gt_powersave(dev); |
f817586c DV |
13401 | } |
13402 | ||
79e53945 JB |
13403 | void intel_modeset_init(struct drm_device *dev) |
13404 | { | |
652c393a | 13405 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 13406 | int sprite, ret; |
8cc87b75 | 13407 | enum pipe pipe; |
46f297fb | 13408 | struct intel_crtc *crtc; |
79e53945 JB |
13409 | |
13410 | drm_mode_config_init(dev); | |
13411 | ||
13412 | dev->mode_config.min_width = 0; | |
13413 | dev->mode_config.min_height = 0; | |
13414 | ||
019d96cb DA |
13415 | dev->mode_config.preferred_depth = 24; |
13416 | dev->mode_config.prefer_shadow = 1; | |
13417 | ||
25bab385 TU |
13418 | dev->mode_config.allow_fb_modifiers = true; |
13419 | ||
e6ecefaa | 13420 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 13421 | |
b690e96c JB |
13422 | intel_init_quirks(dev); |
13423 | ||
1fa61106 ED |
13424 | intel_init_pm(dev); |
13425 | ||
e3c74757 BW |
13426 | if (INTEL_INFO(dev)->num_pipes == 0) |
13427 | return; | |
13428 | ||
e70236a8 | 13429 | intel_init_display(dev); |
7c10a2b5 | 13430 | intel_init_audio(dev); |
e70236a8 | 13431 | |
a6c45cf0 CW |
13432 | if (IS_GEN2(dev)) { |
13433 | dev->mode_config.max_width = 2048; | |
13434 | dev->mode_config.max_height = 2048; | |
13435 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
13436 | dev->mode_config.max_width = 4096; |
13437 | dev->mode_config.max_height = 4096; | |
79e53945 | 13438 | } else { |
a6c45cf0 CW |
13439 | dev->mode_config.max_width = 8192; |
13440 | dev->mode_config.max_height = 8192; | |
79e53945 | 13441 | } |
068be561 | 13442 | |
dc41c154 VS |
13443 | if (IS_845G(dev) || IS_I865G(dev)) { |
13444 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
13445 | dev->mode_config.cursor_height = 1023; | |
13446 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
13447 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
13448 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
13449 | } else { | |
13450 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
13451 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
13452 | } | |
13453 | ||
5d4545ae | 13454 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 13455 | |
28c97730 | 13456 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
13457 | INTEL_INFO(dev)->num_pipes, |
13458 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 13459 | |
055e393f | 13460 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 13461 | intel_crtc_init(dev, pipe); |
3bdcfc0c | 13462 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 13463 | ret = intel_plane_init(dev, pipe, sprite); |
7f1f3851 | 13464 | if (ret) |
06da8da2 | 13465 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 13466 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 13467 | } |
79e53945 JB |
13468 | } |
13469 | ||
f42bb70d JB |
13470 | intel_init_dpio(dev); |
13471 | ||
e72f9fbf | 13472 | intel_shared_dpll_init(dev); |
ee7b9f93 | 13473 | |
9cce37f4 JB |
13474 | /* Just disable it once at startup */ |
13475 | i915_disable_vga(dev); | |
79e53945 | 13476 | intel_setup_outputs(dev); |
11be49eb CW |
13477 | |
13478 | /* Just in case the BIOS is doing something questionable. */ | |
7ff0ebcc | 13479 | intel_fbc_disable(dev); |
fa9fa083 | 13480 | |
6e9f798d | 13481 | drm_modeset_lock_all(dev); |
fa9fa083 | 13482 | intel_modeset_setup_hw_state(dev, false); |
6e9f798d | 13483 | drm_modeset_unlock_all(dev); |
46f297fb | 13484 | |
d3fcc808 | 13485 | for_each_intel_crtc(dev, crtc) { |
46f297fb JB |
13486 | if (!crtc->active) |
13487 | continue; | |
13488 | ||
46f297fb | 13489 | /* |
46f297fb JB |
13490 | * Note that reserving the BIOS fb up front prevents us |
13491 | * from stuffing other stolen allocations like the ring | |
13492 | * on top. This prevents some ugliness at boot time, and | |
13493 | * can even allow for smooth boot transitions if the BIOS | |
13494 | * fb is large enough for the active pipe configuration. | |
13495 | */ | |
5724dbd1 DL |
13496 | if (dev_priv->display.get_initial_plane_config) { |
13497 | dev_priv->display.get_initial_plane_config(crtc, | |
46f297fb JB |
13498 | &crtc->plane_config); |
13499 | /* | |
13500 | * If the fb is shared between multiple heads, we'll | |
13501 | * just get the first one. | |
13502 | */ | |
484b41dd | 13503 | intel_find_plane_obj(crtc, &crtc->plane_config); |
46f297fb | 13504 | } |
46f297fb | 13505 | } |
2c7111db CW |
13506 | } |
13507 | ||
7fad798e DV |
13508 | static void intel_enable_pipe_a(struct drm_device *dev) |
13509 | { | |
13510 | struct intel_connector *connector; | |
13511 | struct drm_connector *crt = NULL; | |
13512 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 13513 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
13514 | |
13515 | /* We can't just switch on the pipe A, we need to set things up with a | |
13516 | * proper mode and output configuration. As a gross hack, enable pipe A | |
13517 | * by enabling the load detect pipe once. */ | |
3a3371ff | 13518 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
13519 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
13520 | crt = &connector->base; | |
13521 | break; | |
13522 | } | |
13523 | } | |
13524 | ||
13525 | if (!crt) | |
13526 | return; | |
13527 | ||
208bf9fd VS |
13528 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
13529 | intel_release_load_detect_pipe(crt, &load_detect_temp); | |
7fad798e DV |
13530 | } |
13531 | ||
fa555837 DV |
13532 | static bool |
13533 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
13534 | { | |
7eb552ae BW |
13535 | struct drm_device *dev = crtc->base.dev; |
13536 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
13537 | u32 reg, val; |
13538 | ||
7eb552ae | 13539 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
13540 | return true; |
13541 | ||
13542 | reg = DSPCNTR(!crtc->plane); | |
13543 | val = I915_READ(reg); | |
13544 | ||
13545 | if ((val & DISPLAY_PLANE_ENABLE) && | |
13546 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
13547 | return false; | |
13548 | ||
13549 | return true; | |
13550 | } | |
13551 | ||
24929352 DV |
13552 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
13553 | { | |
13554 | struct drm_device *dev = crtc->base.dev; | |
13555 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 13556 | u32 reg; |
24929352 | 13557 | |
24929352 | 13558 | /* Clear any frame start delays used for debugging left by the BIOS */ |
6e3c9717 | 13559 | reg = PIPECONF(crtc->config->cpu_transcoder); |
24929352 DV |
13560 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
13561 | ||
d3eaf884 | 13562 | /* restore vblank interrupts to correct state */ |
9625604c | 13563 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 VS |
13564 | if (crtc->active) { |
13565 | update_scanline_offset(crtc); | |
9625604c DV |
13566 | drm_crtc_vblank_on(&crtc->base); |
13567 | } | |
d3eaf884 | 13568 | |
24929352 | 13569 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
13570 | * disable the crtc (and hence change the state) if it is wrong. Note |
13571 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
13572 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
13573 | struct intel_connector *connector; |
13574 | bool plane; | |
13575 | ||
24929352 DV |
13576 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
13577 | crtc->base.base.id); | |
13578 | ||
13579 | /* Pipe has the wrong plane attached and the plane is active. | |
13580 | * Temporarily change the plane mapping and disable everything | |
13581 | * ... */ | |
13582 | plane = crtc->plane; | |
13583 | crtc->plane = !plane; | |
9c8958bc | 13584 | crtc->primary_enabled = true; |
24929352 DV |
13585 | dev_priv->display.crtc_disable(&crtc->base); |
13586 | crtc->plane = plane; | |
13587 | ||
13588 | /* ... and break all links. */ | |
3a3371ff | 13589 | for_each_intel_connector(dev, connector) { |
24929352 DV |
13590 | if (connector->encoder->base.crtc != &crtc->base) |
13591 | continue; | |
13592 | ||
7f1950fb EE |
13593 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
13594 | connector->base.encoder = NULL; | |
24929352 | 13595 | } |
7f1950fb EE |
13596 | /* multiple connectors may have the same encoder: |
13597 | * handle them and break crtc link separately */ | |
3a3371ff | 13598 | for_each_intel_connector(dev, connector) |
7f1950fb EE |
13599 | if (connector->encoder->base.crtc == &crtc->base) { |
13600 | connector->encoder->base.crtc = NULL; | |
13601 | connector->encoder->connectors_active = false; | |
13602 | } | |
24929352 DV |
13603 | |
13604 | WARN_ON(crtc->active); | |
83d65738 | 13605 | crtc->base.state->enable = false; |
24929352 DV |
13606 | crtc->base.enabled = false; |
13607 | } | |
24929352 | 13608 | |
7fad798e DV |
13609 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
13610 | crtc->pipe == PIPE_A && !crtc->active) { | |
13611 | /* BIOS forgot to enable pipe A, this mostly happens after | |
13612 | * resume. Force-enable the pipe to fix this, the update_dpms | |
13613 | * call below we restore the pipe to the right state, but leave | |
13614 | * the required bits on. */ | |
13615 | intel_enable_pipe_a(dev); | |
13616 | } | |
13617 | ||
24929352 DV |
13618 | /* Adjust the state of the output pipe according to whether we |
13619 | * have active connectors/encoders. */ | |
13620 | intel_crtc_update_dpms(&crtc->base); | |
13621 | ||
83d65738 | 13622 | if (crtc->active != crtc->base.state->enable) { |
24929352 DV |
13623 | struct intel_encoder *encoder; |
13624 | ||
13625 | /* This can happen either due to bugs in the get_hw_state | |
13626 | * functions or because the pipe is force-enabled due to the | |
13627 | * pipe A quirk. */ | |
13628 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
13629 | crtc->base.base.id, | |
83d65738 | 13630 | crtc->base.state->enable ? "enabled" : "disabled", |
24929352 DV |
13631 | crtc->active ? "enabled" : "disabled"); |
13632 | ||
83d65738 | 13633 | crtc->base.state->enable = crtc->active; |
24929352 DV |
13634 | crtc->base.enabled = crtc->active; |
13635 | ||
13636 | /* Because we only establish the connector -> encoder -> | |
13637 | * crtc links if something is active, this means the | |
13638 | * crtc is now deactivated. Break the links. connector | |
13639 | * -> encoder links are only establish when things are | |
13640 | * actually up, hence no need to break them. */ | |
13641 | WARN_ON(crtc->active); | |
13642 | ||
13643 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
13644 | WARN_ON(encoder->connectors_active); | |
13645 | encoder->base.crtc = NULL; | |
13646 | } | |
13647 | } | |
c5ab3bc0 | 13648 | |
a3ed6aad | 13649 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
13650 | /* |
13651 | * We start out with underrun reporting disabled to avoid races. | |
13652 | * For correct bookkeeping mark this on active crtcs. | |
13653 | * | |
c5ab3bc0 DV |
13654 | * Also on gmch platforms we dont have any hardware bits to |
13655 | * disable the underrun reporting. Which means we need to start | |
13656 | * out with underrun reporting disabled also on inactive pipes, | |
13657 | * since otherwise we'll complain about the garbage we read when | |
13658 | * e.g. coming up after runtime pm. | |
13659 | * | |
4cc31489 DV |
13660 | * No protection against concurrent access is required - at |
13661 | * worst a fifo underrun happens which also sets this to false. | |
13662 | */ | |
13663 | crtc->cpu_fifo_underrun_disabled = true; | |
13664 | crtc->pch_fifo_underrun_disabled = true; | |
13665 | } | |
24929352 DV |
13666 | } |
13667 | ||
13668 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
13669 | { | |
13670 | struct intel_connector *connector; | |
13671 | struct drm_device *dev = encoder->base.dev; | |
13672 | ||
13673 | /* We need to check both for a crtc link (meaning that the | |
13674 | * encoder is active and trying to read from a pipe) and the | |
13675 | * pipe itself being active. */ | |
13676 | bool has_active_crtc = encoder->base.crtc && | |
13677 | to_intel_crtc(encoder->base.crtc)->active; | |
13678 | ||
13679 | if (encoder->connectors_active && !has_active_crtc) { | |
13680 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
13681 | encoder->base.base.id, | |
8e329a03 | 13682 | encoder->base.name); |
24929352 DV |
13683 | |
13684 | /* Connector is active, but has no active pipe. This is | |
13685 | * fallout from our resume register restoring. Disable | |
13686 | * the encoder manually again. */ | |
13687 | if (encoder->base.crtc) { | |
13688 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
13689 | encoder->base.base.id, | |
8e329a03 | 13690 | encoder->base.name); |
24929352 | 13691 | encoder->disable(encoder); |
a62d1497 VS |
13692 | if (encoder->post_disable) |
13693 | encoder->post_disable(encoder); | |
24929352 | 13694 | } |
7f1950fb EE |
13695 | encoder->base.crtc = NULL; |
13696 | encoder->connectors_active = false; | |
24929352 DV |
13697 | |
13698 | /* Inconsistent output/port/pipe state happens presumably due to | |
13699 | * a bug in one of the get_hw_state functions. Or someplace else | |
13700 | * in our code, like the register restore mess on resume. Clamp | |
13701 | * things to off as a safer default. */ | |
3a3371ff | 13702 | for_each_intel_connector(dev, connector) { |
24929352 DV |
13703 | if (connector->encoder != encoder) |
13704 | continue; | |
7f1950fb EE |
13705 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
13706 | connector->base.encoder = NULL; | |
24929352 DV |
13707 | } |
13708 | } | |
13709 | /* Enabled encoders without active connectors will be fixed in | |
13710 | * the crtc fixup. */ | |
13711 | } | |
13712 | ||
04098753 | 13713 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
13714 | { |
13715 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 13716 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 13717 | |
04098753 ID |
13718 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
13719 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
13720 | i915_disable_vga(dev); | |
13721 | } | |
13722 | } | |
13723 | ||
13724 | void i915_redisable_vga(struct drm_device *dev) | |
13725 | { | |
13726 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13727 | ||
8dc8a27c PZ |
13728 | /* This function can be called both from intel_modeset_setup_hw_state or |
13729 | * at a very early point in our resume sequence, where the power well | |
13730 | * structures are not yet restored. Since this function is at a very | |
13731 | * paranoid "someone might have enabled VGA while we were not looking" | |
13732 | * level, just check if the power well is enabled instead of trying to | |
13733 | * follow the "don't touch the power well if we don't need it" policy | |
13734 | * the rest of the driver uses. */ | |
f458ebbc | 13735 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
13736 | return; |
13737 | ||
04098753 | 13738 | i915_redisable_vga_power_on(dev); |
0fde901f KM |
13739 | } |
13740 | ||
98ec7739 VS |
13741 | static bool primary_get_hw_state(struct intel_crtc *crtc) |
13742 | { | |
13743 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
13744 | ||
13745 | if (!crtc->active) | |
13746 | return false; | |
13747 | ||
13748 | return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE; | |
13749 | } | |
13750 | ||
30e984df | 13751 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
13752 | { |
13753 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13754 | enum pipe pipe; | |
24929352 DV |
13755 | struct intel_crtc *crtc; |
13756 | struct intel_encoder *encoder; | |
13757 | struct intel_connector *connector; | |
5358901f | 13758 | int i; |
24929352 | 13759 | |
d3fcc808 | 13760 | for_each_intel_crtc(dev, crtc) { |
6e3c9717 | 13761 | memset(crtc->config, 0, sizeof(*crtc->config)); |
3b117c8f | 13762 | |
6e3c9717 | 13763 | crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE; |
9953599b | 13764 | |
0e8ffe1b | 13765 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
6e3c9717 | 13766 | crtc->config); |
24929352 | 13767 | |
83d65738 | 13768 | crtc->base.state->enable = crtc->active; |
24929352 | 13769 | crtc->base.enabled = crtc->active; |
98ec7739 | 13770 | crtc->primary_enabled = primary_get_hw_state(crtc); |
24929352 DV |
13771 | |
13772 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
13773 | crtc->base.base.id, | |
13774 | crtc->active ? "enabled" : "disabled"); | |
13775 | } | |
13776 | ||
5358901f DV |
13777 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
13778 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
13779 | ||
3e369b76 ACO |
13780 | pll->on = pll->get_hw_state(dev_priv, pll, |
13781 | &pll->config.hw_state); | |
5358901f | 13782 | pll->active = 0; |
3e369b76 | 13783 | pll->config.crtc_mask = 0; |
d3fcc808 | 13784 | for_each_intel_crtc(dev, crtc) { |
1e6f2ddc | 13785 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) { |
5358901f | 13786 | pll->active++; |
3e369b76 | 13787 | pll->config.crtc_mask |= 1 << crtc->pipe; |
1e6f2ddc | 13788 | } |
5358901f | 13789 | } |
5358901f | 13790 | |
1e6f2ddc | 13791 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 13792 | pll->name, pll->config.crtc_mask, pll->on); |
bd2bb1b9 | 13793 | |
3e369b76 | 13794 | if (pll->config.crtc_mask) |
bd2bb1b9 | 13795 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
5358901f DV |
13796 | } |
13797 | ||
b2784e15 | 13798 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
13799 | pipe = 0; |
13800 | ||
13801 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
13802 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
13803 | encoder->base.crtc = &crtc->base; | |
6e3c9717 | 13804 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
13805 | } else { |
13806 | encoder->base.crtc = NULL; | |
13807 | } | |
13808 | ||
13809 | encoder->connectors_active = false; | |
6f2bcceb | 13810 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 13811 | encoder->base.base.id, |
8e329a03 | 13812 | encoder->base.name, |
24929352 | 13813 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 13814 | pipe_name(pipe)); |
24929352 DV |
13815 | } |
13816 | ||
3a3371ff | 13817 | for_each_intel_connector(dev, connector) { |
24929352 DV |
13818 | if (connector->get_hw_state(connector)) { |
13819 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
13820 | connector->encoder->connectors_active = true; | |
13821 | connector->base.encoder = &connector->encoder->base; | |
13822 | } else { | |
13823 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
13824 | connector->base.encoder = NULL; | |
13825 | } | |
13826 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
13827 | connector->base.base.id, | |
c23cc417 | 13828 | connector->base.name, |
24929352 DV |
13829 | connector->base.encoder ? "enabled" : "disabled"); |
13830 | } | |
30e984df DV |
13831 | } |
13832 | ||
13833 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm | |
13834 | * and i915 state tracking structures. */ | |
13835 | void intel_modeset_setup_hw_state(struct drm_device *dev, | |
13836 | bool force_restore) | |
13837 | { | |
13838 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13839 | enum pipe pipe; | |
30e984df DV |
13840 | struct intel_crtc *crtc; |
13841 | struct intel_encoder *encoder; | |
35c95375 | 13842 | int i; |
30e984df DV |
13843 | |
13844 | intel_modeset_readout_hw_state(dev); | |
24929352 | 13845 | |
babea61d JB |
13846 | /* |
13847 | * Now that we have the config, copy it to each CRTC struct | |
13848 | * Note that this could go away if we move to using crtc_config | |
13849 | * checking everywhere. | |
13850 | */ | |
d3fcc808 | 13851 | for_each_intel_crtc(dev, crtc) { |
d330a953 | 13852 | if (crtc->active && i915.fastboot) { |
6e3c9717 ACO |
13853 | intel_mode_from_pipe_config(&crtc->base.mode, |
13854 | crtc->config); | |
babea61d JB |
13855 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", |
13856 | crtc->base.base.id); | |
13857 | drm_mode_debug_printmodeline(&crtc->base.mode); | |
13858 | } | |
13859 | } | |
13860 | ||
24929352 | 13861 | /* HW state is read out, now we need to sanitize this mess. */ |
b2784e15 | 13862 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
13863 | intel_sanitize_encoder(encoder); |
13864 | } | |
13865 | ||
055e393f | 13866 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
13867 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
13868 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
13869 | intel_dump_pipe_config(crtc, crtc->config, |
13870 | "[setup_hw_state]"); | |
24929352 | 13871 | } |
9a935856 | 13872 | |
35c95375 DV |
13873 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
13874 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
13875 | ||
13876 | if (!pll->on || pll->active) | |
13877 | continue; | |
13878 | ||
13879 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
13880 | ||
13881 | pll->disable(dev_priv, pll); | |
13882 | pll->on = false; | |
13883 | } | |
13884 | ||
3078999f PB |
13885 | if (IS_GEN9(dev)) |
13886 | skl_wm_get_hw_state(dev); | |
13887 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 VS |
13888 | ilk_wm_get_hw_state(dev); |
13889 | ||
45e2b5f6 | 13890 | if (force_restore) { |
7d0bc1ea VS |
13891 | i915_redisable_vga(dev); |
13892 | ||
f30da187 DV |
13893 | /* |
13894 | * We need to use raw interfaces for restoring state to avoid | |
13895 | * checking (bogus) intermediate states. | |
13896 | */ | |
055e393f | 13897 | for_each_pipe(dev_priv, pipe) { |
b5644d05 JB |
13898 | struct drm_crtc *crtc = |
13899 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
f30da187 | 13900 | |
7f27126e JB |
13901 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, |
13902 | crtc->primary->fb); | |
45e2b5f6 DV |
13903 | } |
13904 | } else { | |
13905 | intel_modeset_update_staged_output_state(dev); | |
13906 | } | |
8af6cf88 DV |
13907 | |
13908 | intel_modeset_check_state(dev); | |
2c7111db CW |
13909 | } |
13910 | ||
13911 | void intel_modeset_gem_init(struct drm_device *dev) | |
13912 | { | |
92122789 | 13913 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd | 13914 | struct drm_crtc *c; |
2ff8fde1 | 13915 | struct drm_i915_gem_object *obj; |
484b41dd | 13916 | |
ae48434c ID |
13917 | mutex_lock(&dev->struct_mutex); |
13918 | intel_init_gt_powersave(dev); | |
13919 | mutex_unlock(&dev->struct_mutex); | |
13920 | ||
92122789 JB |
13921 | /* |
13922 | * There may be no VBT; and if the BIOS enabled SSC we can | |
13923 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
13924 | * BIOS isn't using it, don't assume it will work even if the VBT | |
13925 | * indicates as much. | |
13926 | */ | |
13927 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
13928 | dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
13929 | DREF_SSC1_ENABLE); | |
13930 | ||
1833b134 | 13931 | intel_modeset_init_hw(dev); |
02e792fb DV |
13932 | |
13933 | intel_setup_overlay(dev); | |
484b41dd JB |
13934 | |
13935 | /* | |
13936 | * Make sure any fbs we allocated at startup are properly | |
13937 | * pinned & fenced. When we do the allocation it's too early | |
13938 | * for this. | |
13939 | */ | |
13940 | mutex_lock(&dev->struct_mutex); | |
70e1e0ec | 13941 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
13942 | obj = intel_fb_obj(c->primary->fb); |
13943 | if (obj == NULL) | |
484b41dd JB |
13944 | continue; |
13945 | ||
850c4cdc TU |
13946 | if (intel_pin_and_fence_fb_obj(c->primary, |
13947 | c->primary->fb, | |
82bc3b2d | 13948 | c->primary->state, |
850c4cdc | 13949 | NULL)) { |
484b41dd JB |
13950 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
13951 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
13952 | drm_framebuffer_unreference(c->primary->fb); |
13953 | c->primary->fb = NULL; | |
afd65eb4 | 13954 | update_state_fb(c->primary); |
484b41dd JB |
13955 | } |
13956 | } | |
13957 | mutex_unlock(&dev->struct_mutex); | |
0962c3c9 VS |
13958 | |
13959 | intel_backlight_register(dev); | |
79e53945 JB |
13960 | } |
13961 | ||
4932e2c3 ID |
13962 | void intel_connector_unregister(struct intel_connector *intel_connector) |
13963 | { | |
13964 | struct drm_connector *connector = &intel_connector->base; | |
13965 | ||
13966 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 13967 | drm_connector_unregister(connector); |
4932e2c3 ID |
13968 | } |
13969 | ||
79e53945 JB |
13970 | void intel_modeset_cleanup(struct drm_device *dev) |
13971 | { | |
652c393a | 13972 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9255d57 | 13973 | struct drm_connector *connector; |
652c393a | 13974 | |
2eb5252e ID |
13975 | intel_disable_gt_powersave(dev); |
13976 | ||
0962c3c9 VS |
13977 | intel_backlight_unregister(dev); |
13978 | ||
fd0c0642 DV |
13979 | /* |
13980 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 13981 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
13982 | * experience fancy races otherwise. |
13983 | */ | |
2aeb7d3a | 13984 | intel_irq_uninstall(dev_priv); |
eb21b92b | 13985 | |
fd0c0642 DV |
13986 | /* |
13987 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
13988 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
13989 | */ | |
f87ea761 | 13990 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 13991 | |
652c393a JB |
13992 | mutex_lock(&dev->struct_mutex); |
13993 | ||
723bfd70 JB |
13994 | intel_unregister_dsm_handler(); |
13995 | ||
7ff0ebcc | 13996 | intel_fbc_disable(dev); |
e70236a8 | 13997 | |
69341a5e KH |
13998 | mutex_unlock(&dev->struct_mutex); |
13999 | ||
1630fe75 CW |
14000 | /* flush any delayed tasks or pending work */ |
14001 | flush_scheduled_work(); | |
14002 | ||
db31af1d JN |
14003 | /* destroy the backlight and sysfs files before encoders/connectors */ |
14004 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4932e2c3 ID |
14005 | struct intel_connector *intel_connector; |
14006 | ||
14007 | intel_connector = to_intel_connector(connector); | |
14008 | intel_connector->unregister(intel_connector); | |
db31af1d | 14009 | } |
d9255d57 | 14010 | |
79e53945 | 14011 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
14012 | |
14013 | intel_cleanup_overlay(dev); | |
ae48434c ID |
14014 | |
14015 | mutex_lock(&dev->struct_mutex); | |
14016 | intel_cleanup_gt_powersave(dev); | |
14017 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
14018 | } |
14019 | ||
f1c79df3 ZW |
14020 | /* |
14021 | * Return which encoder is currently attached for connector. | |
14022 | */ | |
df0e9248 | 14023 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 14024 | { |
df0e9248 CW |
14025 | return &intel_attached_encoder(connector)->base; |
14026 | } | |
f1c79df3 | 14027 | |
df0e9248 CW |
14028 | void intel_connector_attach_encoder(struct intel_connector *connector, |
14029 | struct intel_encoder *encoder) | |
14030 | { | |
14031 | connector->encoder = encoder; | |
14032 | drm_mode_connector_attach_encoder(&connector->base, | |
14033 | &encoder->base); | |
79e53945 | 14034 | } |
28d52043 DA |
14035 | |
14036 | /* | |
14037 | * set vga decode state - true == enable VGA decode | |
14038 | */ | |
14039 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
14040 | { | |
14041 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 14042 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
14043 | u16 gmch_ctrl; |
14044 | ||
75fa041d CW |
14045 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
14046 | DRM_ERROR("failed to read control word\n"); | |
14047 | return -EIO; | |
14048 | } | |
14049 | ||
c0cc8a55 CW |
14050 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
14051 | return 0; | |
14052 | ||
28d52043 DA |
14053 | if (state) |
14054 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
14055 | else | |
14056 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
14057 | |
14058 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
14059 | DRM_ERROR("failed to write control word\n"); | |
14060 | return -EIO; | |
14061 | } | |
14062 | ||
28d52043 DA |
14063 | return 0; |
14064 | } | |
c4a1d9e4 | 14065 | |
c4a1d9e4 | 14066 | struct intel_display_error_state { |
ff57f1b0 PZ |
14067 | |
14068 | u32 power_well_driver; | |
14069 | ||
63b66e5b CW |
14070 | int num_transcoders; |
14071 | ||
c4a1d9e4 CW |
14072 | struct intel_cursor_error_state { |
14073 | u32 control; | |
14074 | u32 position; | |
14075 | u32 base; | |
14076 | u32 size; | |
52331309 | 14077 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
14078 | |
14079 | struct intel_pipe_error_state { | |
ddf9c536 | 14080 | bool power_domain_on; |
c4a1d9e4 | 14081 | u32 source; |
f301b1e1 | 14082 | u32 stat; |
52331309 | 14083 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
14084 | |
14085 | struct intel_plane_error_state { | |
14086 | u32 control; | |
14087 | u32 stride; | |
14088 | u32 size; | |
14089 | u32 pos; | |
14090 | u32 addr; | |
14091 | u32 surface; | |
14092 | u32 tile_offset; | |
52331309 | 14093 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
14094 | |
14095 | struct intel_transcoder_error_state { | |
ddf9c536 | 14096 | bool power_domain_on; |
63b66e5b CW |
14097 | enum transcoder cpu_transcoder; |
14098 | ||
14099 | u32 conf; | |
14100 | ||
14101 | u32 htotal; | |
14102 | u32 hblank; | |
14103 | u32 hsync; | |
14104 | u32 vtotal; | |
14105 | u32 vblank; | |
14106 | u32 vsync; | |
14107 | } transcoder[4]; | |
c4a1d9e4 CW |
14108 | }; |
14109 | ||
14110 | struct intel_display_error_state * | |
14111 | intel_display_capture_error_state(struct drm_device *dev) | |
14112 | { | |
fbee40df | 14113 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 14114 | struct intel_display_error_state *error; |
63b66e5b CW |
14115 | int transcoders[] = { |
14116 | TRANSCODER_A, | |
14117 | TRANSCODER_B, | |
14118 | TRANSCODER_C, | |
14119 | TRANSCODER_EDP, | |
14120 | }; | |
c4a1d9e4 CW |
14121 | int i; |
14122 | ||
63b66e5b CW |
14123 | if (INTEL_INFO(dev)->num_pipes == 0) |
14124 | return NULL; | |
14125 | ||
9d1cb914 | 14126 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
14127 | if (error == NULL) |
14128 | return NULL; | |
14129 | ||
190be112 | 14130 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
14131 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
14132 | ||
055e393f | 14133 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 14134 | error->pipe[i].power_domain_on = |
f458ebbc DV |
14135 | __intel_display_power_is_enabled(dev_priv, |
14136 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 14137 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
14138 | continue; |
14139 | ||
5efb3e28 VS |
14140 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
14141 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
14142 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
14143 | |
14144 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
14145 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 14146 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 14147 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
14148 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
14149 | } | |
ca291363 PZ |
14150 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
14151 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
14152 | if (INTEL_INFO(dev)->gen >= 4) { |
14153 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
14154 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
14155 | } | |
14156 | ||
c4a1d9e4 | 14157 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 14158 | |
3abfce77 | 14159 | if (HAS_GMCH_DISPLAY(dev)) |
f301b1e1 | 14160 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
14161 | } |
14162 | ||
14163 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
14164 | if (HAS_DDI(dev_priv->dev)) | |
14165 | error->num_transcoders++; /* Account for eDP. */ | |
14166 | ||
14167 | for (i = 0; i < error->num_transcoders; i++) { | |
14168 | enum transcoder cpu_transcoder = transcoders[i]; | |
14169 | ||
ddf9c536 | 14170 | error->transcoder[i].power_domain_on = |
f458ebbc | 14171 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 14172 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 14173 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
14174 | continue; |
14175 | ||
63b66e5b CW |
14176 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
14177 | ||
14178 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
14179 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
14180 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
14181 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
14182 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
14183 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
14184 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
14185 | } |
14186 | ||
14187 | return error; | |
14188 | } | |
14189 | ||
edc3d884 MK |
14190 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
14191 | ||
c4a1d9e4 | 14192 | void |
edc3d884 | 14193 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
14194 | struct drm_device *dev, |
14195 | struct intel_display_error_state *error) | |
14196 | { | |
055e393f | 14197 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
14198 | int i; |
14199 | ||
63b66e5b CW |
14200 | if (!error) |
14201 | return; | |
14202 | ||
edc3d884 | 14203 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 14204 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 14205 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 14206 | error->power_well_driver); |
055e393f | 14207 | for_each_pipe(dev_priv, i) { |
edc3d884 | 14208 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 ID |
14209 | err_printf(m, " Power: %s\n", |
14210 | error->pipe[i].power_domain_on ? "on" : "off"); | |
edc3d884 | 14211 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 14212 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
14213 | |
14214 | err_printf(m, "Plane [%d]:\n", i); | |
14215 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
14216 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 14217 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
14218 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
14219 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 14220 | } |
4b71a570 | 14221 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 14222 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 14223 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
14224 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
14225 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
14226 | } |
14227 | ||
edc3d884 MK |
14228 | err_printf(m, "Cursor [%d]:\n", i); |
14229 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
14230 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
14231 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 14232 | } |
63b66e5b CW |
14233 | |
14234 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 14235 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 14236 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 ID |
14237 | err_printf(m, " Power: %s\n", |
14238 | error->transcoder[i].power_domain_on ? "on" : "off"); | |
63b66e5b CW |
14239 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
14240 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
14241 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
14242 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
14243 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
14244 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
14245 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
14246 | } | |
c4a1d9e4 | 14247 | } |
e2fcdaa9 VS |
14248 | |
14249 | void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file) | |
14250 | { | |
14251 | struct intel_crtc *crtc; | |
14252 | ||
14253 | for_each_intel_crtc(dev, crtc) { | |
14254 | struct intel_unpin_work *work; | |
e2fcdaa9 | 14255 | |
5e2d7afc | 14256 | spin_lock_irq(&dev->event_lock); |
e2fcdaa9 VS |
14257 | |
14258 | work = crtc->unpin_work; | |
14259 | ||
14260 | if (work && work->event && | |
14261 | work->event->base.file_priv == file) { | |
14262 | kfree(work->event); | |
14263 | work->event = NULL; | |
14264 | } | |
14265 | ||
5e2d7afc | 14266 | spin_unlock_irq(&dev->event_lock); |
e2fcdaa9 VS |
14267 | } |
14268 | } |