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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
319c1d42 | 40 | #include <drm/drm_atomic.h> |
c196e1d6 | 41 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
42 | #include <drm/drm_dp_helper.h> |
43 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
44 | #include <drm/drm_plane_helper.h> |
45 | #include <drm/drm_rect.h> | |
c0f372b3 | 46 | #include <linux/dma_remapping.h> |
fd8e058a AG |
47 | #include <linux/reservation.h> |
48 | #include <linux/dma-buf.h> | |
79e53945 | 49 | |
465c120c | 50 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 51 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
52 | DRM_FORMAT_C8, |
53 | DRM_FORMAT_RGB565, | |
465c120c | 54 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 55 | DRM_FORMAT_XRGB8888, |
465c120c MR |
56 | }; |
57 | ||
58 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 59 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
60 | DRM_FORMAT_C8, |
61 | DRM_FORMAT_RGB565, | |
62 | DRM_FORMAT_XRGB8888, | |
63 | DRM_FORMAT_XBGR8888, | |
64 | DRM_FORMAT_XRGB2101010, | |
65 | DRM_FORMAT_XBGR2101010, | |
66 | }; | |
67 | ||
68 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
69 | DRM_FORMAT_C8, |
70 | DRM_FORMAT_RGB565, | |
71 | DRM_FORMAT_XRGB8888, | |
465c120c | 72 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 73 | DRM_FORMAT_ARGB8888, |
465c120c MR |
74 | DRM_FORMAT_ABGR8888, |
75 | DRM_FORMAT_XRGB2101010, | |
465c120c | 76 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
77 | DRM_FORMAT_YUYV, |
78 | DRM_FORMAT_YVYU, | |
79 | DRM_FORMAT_UYVY, | |
80 | DRM_FORMAT_VYUY, | |
465c120c MR |
81 | }; |
82 | ||
3d7d6510 MR |
83 | /* Cursor formats */ |
84 | static const uint32_t intel_cursor_formats[] = { | |
85 | DRM_FORMAT_ARGB8888, | |
86 | }; | |
87 | ||
f1f644dc | 88 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 89 | struct intel_crtc_state *pipe_config); |
18442d08 | 90 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 91 | struct intel_crtc_state *pipe_config); |
f1f644dc | 92 | |
eb1bfe80 JB |
93 | static int intel_framebuffer_init(struct drm_device *dev, |
94 | struct intel_framebuffer *ifb, | |
95 | struct drm_mode_fb_cmd2 *mode_cmd, | |
96 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
97 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
98 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
bc58be60 | 99 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc); |
29407aab | 100 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
101 | struct intel_link_m_n *m_n, |
102 | struct intel_link_m_n *m2_n2); | |
29407aab | 103 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 | 104 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
391bf048 | 105 | static void haswell_set_pipemisc(struct drm_crtc *crtc); |
d288f65f | 106 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 107 | const struct intel_crtc_state *pipe_config); |
d288f65f | 108 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 109 | const struct intel_crtc_state *pipe_config); |
613d2b27 ML |
110 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
111 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
549e2bfb CK |
112 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
113 | struct intel_crtc_state *crtc_state); | |
ceb41007 | 114 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state); |
bfd16b2a ML |
115 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
116 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
117 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
043e9bda | 118 | static void intel_modeset_setup_hw_state(struct drm_device *dev); |
2622a081 | 119 | static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc); |
e7457a9a | 120 | |
79e53945 | 121 | typedef struct { |
0206e353 | 122 | int min, max; |
79e53945 JB |
123 | } intel_range_t; |
124 | ||
125 | typedef struct { | |
0206e353 AJ |
126 | int dot_limit; |
127 | int p2_slow, p2_fast; | |
79e53945 JB |
128 | } intel_p2_t; |
129 | ||
d4906093 ML |
130 | typedef struct intel_limit intel_limit_t; |
131 | struct intel_limit { | |
0206e353 AJ |
132 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
133 | intel_p2_t p2; | |
d4906093 | 134 | }; |
79e53945 | 135 | |
bfa7df01 VS |
136 | /* returns HPLL frequency in kHz */ |
137 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) | |
138 | { | |
139 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
140 | ||
141 | /* Obtain SKU information */ | |
142 | mutex_lock(&dev_priv->sb_lock); | |
143 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
144 | CCK_FUSE_HPLL_FREQ_MASK; | |
145 | mutex_unlock(&dev_priv->sb_lock); | |
146 | ||
147 | return vco_freq[hpll_freq] * 1000; | |
148 | } | |
149 | ||
150 | static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, | |
151 | const char *name, u32 reg) | |
152 | { | |
153 | u32 val; | |
154 | int divider; | |
155 | ||
156 | if (dev_priv->hpll_freq == 0) | |
157 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
158 | ||
159 | mutex_lock(&dev_priv->sb_lock); | |
160 | val = vlv_cck_read(dev_priv, reg); | |
161 | mutex_unlock(&dev_priv->sb_lock); | |
162 | ||
163 | divider = val & CCK_FREQUENCY_VALUES; | |
164 | ||
165 | WARN((val & CCK_FREQUENCY_STATUS) != | |
166 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
167 | "%s change in progress\n", name); | |
168 | ||
169 | return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); | |
170 | } | |
171 | ||
e7dc33f3 VS |
172 | static int |
173 | intel_pch_rawclk(struct drm_i915_private *dev_priv) | |
d2acd215 | 174 | { |
e7dc33f3 VS |
175 | return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; |
176 | } | |
d2acd215 | 177 | |
e7dc33f3 VS |
178 | static int |
179 | intel_vlv_hrawclk(struct drm_i915_private *dev_priv) | |
180 | { | |
35d38d1f VS |
181 | return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", |
182 | CCK_DISPLAY_REF_CLOCK_CONTROL); | |
d2acd215 DV |
183 | } |
184 | ||
e7dc33f3 VS |
185 | static int |
186 | intel_g4x_hrawclk(struct drm_i915_private *dev_priv) | |
79e50a4f | 187 | { |
79e50a4f JN |
188 | uint32_t clkcfg; |
189 | ||
e7dc33f3 | 190 | /* hrawclock is 1/4 the FSB frequency */ |
79e50a4f JN |
191 | clkcfg = I915_READ(CLKCFG); |
192 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
193 | case CLKCFG_FSB_400: | |
e7dc33f3 | 194 | return 100000; |
79e50a4f | 195 | case CLKCFG_FSB_533: |
e7dc33f3 | 196 | return 133333; |
79e50a4f | 197 | case CLKCFG_FSB_667: |
e7dc33f3 | 198 | return 166667; |
79e50a4f | 199 | case CLKCFG_FSB_800: |
e7dc33f3 | 200 | return 200000; |
79e50a4f | 201 | case CLKCFG_FSB_1067: |
e7dc33f3 | 202 | return 266667; |
79e50a4f | 203 | case CLKCFG_FSB_1333: |
e7dc33f3 | 204 | return 333333; |
79e50a4f JN |
205 | /* these two are just a guess; one of them might be right */ |
206 | case CLKCFG_FSB_1600: | |
207 | case CLKCFG_FSB_1600_ALT: | |
e7dc33f3 | 208 | return 400000; |
79e50a4f | 209 | default: |
e7dc33f3 | 210 | return 133333; |
79e50a4f JN |
211 | } |
212 | } | |
213 | ||
e7dc33f3 VS |
214 | static void intel_update_rawclk(struct drm_i915_private *dev_priv) |
215 | { | |
216 | if (HAS_PCH_SPLIT(dev_priv)) | |
217 | dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv); | |
218 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
219 | dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv); | |
220 | else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv)) | |
221 | dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv); | |
222 | else | |
223 | return; /* no rawclk on other platforms, or no need to know it */ | |
224 | ||
225 | DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq); | |
226 | } | |
227 | ||
bfa7df01 VS |
228 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
229 | { | |
666a4537 | 230 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
bfa7df01 VS |
231 | return; |
232 | ||
233 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
234 | CCK_CZ_CLOCK_CONTROL); | |
235 | ||
236 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); | |
237 | } | |
238 | ||
021357ac | 239 | static inline u32 /* units of 100MHz */ |
21a727b3 VS |
240 | intel_fdi_link_freq(struct drm_i915_private *dev_priv, |
241 | const struct intel_crtc_state *pipe_config) | |
021357ac | 242 | { |
21a727b3 VS |
243 | if (HAS_DDI(dev_priv)) |
244 | return pipe_config->port_clock; /* SPLL */ | |
245 | else if (IS_GEN5(dev_priv)) | |
246 | return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000; | |
e3b247da | 247 | else |
21a727b3 | 248 | return 270000; |
021357ac CW |
249 | } |
250 | ||
5d536e28 | 251 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 252 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 253 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 254 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
255 | .m = { .min = 96, .max = 140 }, |
256 | .m1 = { .min = 18, .max = 26 }, | |
257 | .m2 = { .min = 6, .max = 16 }, | |
258 | .p = { .min = 4, .max = 128 }, | |
259 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
260 | .p2 = { .dot_limit = 165000, |
261 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
262 | }; |
263 | ||
5d536e28 DV |
264 | static const intel_limit_t intel_limits_i8xx_dvo = { |
265 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 266 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 267 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
268 | .m = { .min = 96, .max = 140 }, |
269 | .m1 = { .min = 18, .max = 26 }, | |
270 | .m2 = { .min = 6, .max = 16 }, | |
271 | .p = { .min = 4, .max = 128 }, | |
272 | .p1 = { .min = 2, .max = 33 }, | |
273 | .p2 = { .dot_limit = 165000, | |
274 | .p2_slow = 4, .p2_fast = 4 }, | |
275 | }; | |
276 | ||
e4b36699 | 277 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 278 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 279 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 280 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
281 | .m = { .min = 96, .max = 140 }, |
282 | .m1 = { .min = 18, .max = 26 }, | |
283 | .m2 = { .min = 6, .max = 16 }, | |
284 | .p = { .min = 4, .max = 128 }, | |
285 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
286 | .p2 = { .dot_limit = 165000, |
287 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 288 | }; |
273e27ca | 289 | |
e4b36699 | 290 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
291 | .dot = { .min = 20000, .max = 400000 }, |
292 | .vco = { .min = 1400000, .max = 2800000 }, | |
293 | .n = { .min = 1, .max = 6 }, | |
294 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
295 | .m1 = { .min = 8, .max = 18 }, |
296 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
297 | .p = { .min = 5, .max = 80 }, |
298 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
299 | .p2 = { .dot_limit = 200000, |
300 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
301 | }; |
302 | ||
303 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
304 | .dot = { .min = 20000, .max = 400000 }, |
305 | .vco = { .min = 1400000, .max = 2800000 }, | |
306 | .n = { .min = 1, .max = 6 }, | |
307 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
308 | .m1 = { .min = 8, .max = 18 }, |
309 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
310 | .p = { .min = 7, .max = 98 }, |
311 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
312 | .p2 = { .dot_limit = 112000, |
313 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
314 | }; |
315 | ||
273e27ca | 316 | |
e4b36699 | 317 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
318 | .dot = { .min = 25000, .max = 270000 }, |
319 | .vco = { .min = 1750000, .max = 3500000}, | |
320 | .n = { .min = 1, .max = 4 }, | |
321 | .m = { .min = 104, .max = 138 }, | |
322 | .m1 = { .min = 17, .max = 23 }, | |
323 | .m2 = { .min = 5, .max = 11 }, | |
324 | .p = { .min = 10, .max = 30 }, | |
325 | .p1 = { .min = 1, .max = 3}, | |
326 | .p2 = { .dot_limit = 270000, | |
327 | .p2_slow = 10, | |
328 | .p2_fast = 10 | |
044c7c41 | 329 | }, |
e4b36699 KP |
330 | }; |
331 | ||
332 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
333 | .dot = { .min = 22000, .max = 400000 }, |
334 | .vco = { .min = 1750000, .max = 3500000}, | |
335 | .n = { .min = 1, .max = 4 }, | |
336 | .m = { .min = 104, .max = 138 }, | |
337 | .m1 = { .min = 16, .max = 23 }, | |
338 | .m2 = { .min = 5, .max = 11 }, | |
339 | .p = { .min = 5, .max = 80 }, | |
340 | .p1 = { .min = 1, .max = 8}, | |
341 | .p2 = { .dot_limit = 165000, | |
342 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
343 | }; |
344 | ||
345 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
346 | .dot = { .min = 20000, .max = 115000 }, |
347 | .vco = { .min = 1750000, .max = 3500000 }, | |
348 | .n = { .min = 1, .max = 3 }, | |
349 | .m = { .min = 104, .max = 138 }, | |
350 | .m1 = { .min = 17, .max = 23 }, | |
351 | .m2 = { .min = 5, .max = 11 }, | |
352 | .p = { .min = 28, .max = 112 }, | |
353 | .p1 = { .min = 2, .max = 8 }, | |
354 | .p2 = { .dot_limit = 0, | |
355 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 356 | }, |
e4b36699 KP |
357 | }; |
358 | ||
359 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
360 | .dot = { .min = 80000, .max = 224000 }, |
361 | .vco = { .min = 1750000, .max = 3500000 }, | |
362 | .n = { .min = 1, .max = 3 }, | |
363 | .m = { .min = 104, .max = 138 }, | |
364 | .m1 = { .min = 17, .max = 23 }, | |
365 | .m2 = { .min = 5, .max = 11 }, | |
366 | .p = { .min = 14, .max = 42 }, | |
367 | .p1 = { .min = 2, .max = 6 }, | |
368 | .p2 = { .dot_limit = 0, | |
369 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 370 | }, |
e4b36699 KP |
371 | }; |
372 | ||
f2b115e6 | 373 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
374 | .dot = { .min = 20000, .max = 400000}, |
375 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 376 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
377 | .n = { .min = 3, .max = 6 }, |
378 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 379 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
380 | .m1 = { .min = 0, .max = 0 }, |
381 | .m2 = { .min = 0, .max = 254 }, | |
382 | .p = { .min = 5, .max = 80 }, | |
383 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
384 | .p2 = { .dot_limit = 200000, |
385 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
386 | }; |
387 | ||
f2b115e6 | 388 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
389 | .dot = { .min = 20000, .max = 400000 }, |
390 | .vco = { .min = 1700000, .max = 3500000 }, | |
391 | .n = { .min = 3, .max = 6 }, | |
392 | .m = { .min = 2, .max = 256 }, | |
393 | .m1 = { .min = 0, .max = 0 }, | |
394 | .m2 = { .min = 0, .max = 254 }, | |
395 | .p = { .min = 7, .max = 112 }, | |
396 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
397 | .p2 = { .dot_limit = 112000, |
398 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
399 | }; |
400 | ||
273e27ca EA |
401 | /* Ironlake / Sandybridge |
402 | * | |
403 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
404 | * the range value for them is (actual_value - 2). | |
405 | */ | |
b91ad0ec | 406 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
407 | .dot = { .min = 25000, .max = 350000 }, |
408 | .vco = { .min = 1760000, .max = 3510000 }, | |
409 | .n = { .min = 1, .max = 5 }, | |
410 | .m = { .min = 79, .max = 127 }, | |
411 | .m1 = { .min = 12, .max = 22 }, | |
412 | .m2 = { .min = 5, .max = 9 }, | |
413 | .p = { .min = 5, .max = 80 }, | |
414 | .p1 = { .min = 1, .max = 8 }, | |
415 | .p2 = { .dot_limit = 225000, | |
416 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
417 | }; |
418 | ||
b91ad0ec | 419 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
420 | .dot = { .min = 25000, .max = 350000 }, |
421 | .vco = { .min = 1760000, .max = 3510000 }, | |
422 | .n = { .min = 1, .max = 3 }, | |
423 | .m = { .min = 79, .max = 118 }, | |
424 | .m1 = { .min = 12, .max = 22 }, | |
425 | .m2 = { .min = 5, .max = 9 }, | |
426 | .p = { .min = 28, .max = 112 }, | |
427 | .p1 = { .min = 2, .max = 8 }, | |
428 | .p2 = { .dot_limit = 225000, | |
429 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
430 | }; |
431 | ||
432 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
433 | .dot = { .min = 25000, .max = 350000 }, |
434 | .vco = { .min = 1760000, .max = 3510000 }, | |
435 | .n = { .min = 1, .max = 3 }, | |
436 | .m = { .min = 79, .max = 127 }, | |
437 | .m1 = { .min = 12, .max = 22 }, | |
438 | .m2 = { .min = 5, .max = 9 }, | |
439 | .p = { .min = 14, .max = 56 }, | |
440 | .p1 = { .min = 2, .max = 8 }, | |
441 | .p2 = { .dot_limit = 225000, | |
442 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
443 | }; |
444 | ||
273e27ca | 445 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 446 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
447 | .dot = { .min = 25000, .max = 350000 }, |
448 | .vco = { .min = 1760000, .max = 3510000 }, | |
449 | .n = { .min = 1, .max = 2 }, | |
450 | .m = { .min = 79, .max = 126 }, | |
451 | .m1 = { .min = 12, .max = 22 }, | |
452 | .m2 = { .min = 5, .max = 9 }, | |
453 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 454 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
455 | .p2 = { .dot_limit = 225000, |
456 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
457 | }; |
458 | ||
459 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
460 | .dot = { .min = 25000, .max = 350000 }, |
461 | .vco = { .min = 1760000, .max = 3510000 }, | |
462 | .n = { .min = 1, .max = 3 }, | |
463 | .m = { .min = 79, .max = 126 }, | |
464 | .m1 = { .min = 12, .max = 22 }, | |
465 | .m2 = { .min = 5, .max = 9 }, | |
466 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 467 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
468 | .p2 = { .dot_limit = 225000, |
469 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
470 | }; |
471 | ||
dc730512 | 472 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
473 | /* |
474 | * These are the data rate limits (measured in fast clocks) | |
475 | * since those are the strictest limits we have. The fast | |
476 | * clock and actual rate limits are more relaxed, so checking | |
477 | * them would make no difference. | |
478 | */ | |
479 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 480 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 481 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
482 | .m1 = { .min = 2, .max = 3 }, |
483 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 484 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 485 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
486 | }; |
487 | ||
ef9348c8 CML |
488 | static const intel_limit_t intel_limits_chv = { |
489 | /* | |
490 | * These are the data rate limits (measured in fast clocks) | |
491 | * since those are the strictest limits we have. The fast | |
492 | * clock and actual rate limits are more relaxed, so checking | |
493 | * them would make no difference. | |
494 | */ | |
495 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 496 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
497 | .n = { .min = 1, .max = 1 }, |
498 | .m1 = { .min = 2, .max = 2 }, | |
499 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
500 | .p1 = { .min = 2, .max = 4 }, | |
501 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
502 | }; | |
503 | ||
5ab7b0b7 ID |
504 | static const intel_limit_t intel_limits_bxt = { |
505 | /* FIXME: find real dot limits */ | |
506 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 507 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
508 | .n = { .min = 1, .max = 1 }, |
509 | .m1 = { .min = 2, .max = 2 }, | |
510 | /* FIXME: find real m2 limits */ | |
511 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
512 | .p1 = { .min = 2, .max = 4 }, | |
513 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
514 | }; | |
515 | ||
cdba954e ACO |
516 | static bool |
517 | needs_modeset(struct drm_crtc_state *state) | |
518 | { | |
fc596660 | 519 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
520 | } |
521 | ||
e0638cdf PZ |
522 | /** |
523 | * Returns whether any output on the specified pipe is of the specified type | |
524 | */ | |
4093561b | 525 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) |
e0638cdf | 526 | { |
409ee761 | 527 | struct drm_device *dev = crtc->base.dev; |
e0638cdf PZ |
528 | struct intel_encoder *encoder; |
529 | ||
409ee761 | 530 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
e0638cdf PZ |
531 | if (encoder->type == type) |
532 | return true; | |
533 | ||
534 | return false; | |
535 | } | |
536 | ||
d0737e1d ACO |
537 | /** |
538 | * Returns whether any output on the specified pipe will have the specified | |
539 | * type after a staged modeset is complete, i.e., the same as | |
540 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of | |
541 | * encoder->crtc. | |
542 | */ | |
a93e255f ACO |
543 | static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state, |
544 | int type) | |
d0737e1d | 545 | { |
a93e255f | 546 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 547 | struct drm_connector *connector; |
a93e255f | 548 | struct drm_connector_state *connector_state; |
d0737e1d | 549 | struct intel_encoder *encoder; |
a93e255f ACO |
550 | int i, num_connectors = 0; |
551 | ||
da3ced29 | 552 | for_each_connector_in_state(state, connector, connector_state, i) { |
a93e255f ACO |
553 | if (connector_state->crtc != crtc_state->base.crtc) |
554 | continue; | |
555 | ||
556 | num_connectors++; | |
d0737e1d | 557 | |
a93e255f ACO |
558 | encoder = to_intel_encoder(connector_state->best_encoder); |
559 | if (encoder->type == type) | |
d0737e1d | 560 | return true; |
a93e255f ACO |
561 | } |
562 | ||
563 | WARN_ON(num_connectors == 0); | |
d0737e1d ACO |
564 | |
565 | return false; | |
566 | } | |
567 | ||
a93e255f ACO |
568 | static const intel_limit_t * |
569 | intel_g4x_limit(struct intel_crtc_state *crtc_state) | |
044c7c41 | 570 | { |
a93e255f | 571 | struct drm_device *dev = crtc_state->base.crtc->dev; |
044c7c41 ML |
572 | const intel_limit_t *limit; |
573 | ||
a93e255f | 574 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 575 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 576 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 577 | else |
e4b36699 | 578 | limit = &intel_limits_g4x_single_channel_lvds; |
a93e255f ACO |
579 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) || |
580 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 581 | limit = &intel_limits_g4x_hdmi; |
a93e255f | 582 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 583 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 584 | } else /* The option is for other outputs */ |
e4b36699 | 585 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
586 | |
587 | return limit; | |
588 | } | |
589 | ||
a93e255f ACO |
590 | static const intel_limit_t * |
591 | intel_limit(struct intel_crtc_state *crtc_state, int refclk) | |
79e53945 | 592 | { |
a93e255f | 593 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 JB |
594 | const intel_limit_t *limit; |
595 | ||
5ab7b0b7 ID |
596 | if (IS_BROXTON(dev)) |
597 | limit = &intel_limits_bxt; | |
8f0d5b9b ACO |
598 | else if (WARN_ON(HAS_PCH_SPLIT(dev))) |
599 | limit = NULL; | |
2c07245f | 600 | else if (IS_G4X(dev)) { |
a93e255f | 601 | limit = intel_g4x_limit(crtc_state); |
f2b115e6 | 602 | } else if (IS_PINEVIEW(dev)) { |
a93e255f | 603 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 604 | limit = &intel_limits_pineview_lvds; |
2177832f | 605 | else |
f2b115e6 | 606 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
607 | } else if (IS_CHERRYVIEW(dev)) { |
608 | limit = &intel_limits_chv; | |
a0c4da24 | 609 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 610 | limit = &intel_limits_vlv; |
a6c45cf0 | 611 | } else if (!IS_GEN2(dev)) { |
a93e255f | 612 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a6c45cf0 CW |
613 | limit = &intel_limits_i9xx_lvds; |
614 | else | |
615 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 | 616 | } else { |
a93e255f | 617 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
e4b36699 | 618 | limit = &intel_limits_i8xx_lvds; |
a93e255f | 619 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
e4b36699 | 620 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
621 | else |
622 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
623 | } |
624 | return limit; | |
625 | } | |
626 | ||
dccbea3b ID |
627 | /* |
628 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
629 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
630 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
631 | * The helpers' return value is the rate of the clock that is fed to the | |
632 | * display engine's pipe which can be the above fast dot clock rate or a | |
633 | * divided-down version of it. | |
634 | */ | |
f2b115e6 | 635 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
dccbea3b | 636 | static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock) |
79e53945 | 637 | { |
2177832f SL |
638 | clock->m = clock->m2 + 2; |
639 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 640 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 641 | return 0; |
fb03ac01 VS |
642 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
643 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
644 | |
645 | return clock->dot; | |
2177832f SL |
646 | } |
647 | ||
7429e9d4 DV |
648 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
649 | { | |
650 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
651 | } | |
652 | ||
dccbea3b | 653 | static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock) |
2177832f | 654 | { |
7429e9d4 | 655 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 656 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 657 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 658 | return 0; |
fb03ac01 VS |
659 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
660 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
661 | |
662 | return clock->dot; | |
79e53945 JB |
663 | } |
664 | ||
dccbea3b | 665 | static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock) |
589eca67 ID |
666 | { |
667 | clock->m = clock->m1 * clock->m2; | |
668 | clock->p = clock->p1 * clock->p2; | |
669 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 670 | return 0; |
589eca67 ID |
671 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
672 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
673 | |
674 | return clock->dot / 5; | |
589eca67 ID |
675 | } |
676 | ||
dccbea3b | 677 | int chv_calc_dpll_params(int refclk, intel_clock_t *clock) |
ef9348c8 CML |
678 | { |
679 | clock->m = clock->m1 * clock->m2; | |
680 | clock->p = clock->p1 * clock->p2; | |
681 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 682 | return 0; |
ef9348c8 CML |
683 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
684 | clock->n << 22); | |
685 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
686 | |
687 | return clock->dot / 5; | |
ef9348c8 CML |
688 | } |
689 | ||
7c04d1d9 | 690 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
691 | /** |
692 | * Returns whether the given set of divisors are valid for a given refclk with | |
693 | * the given connectors. | |
694 | */ | |
695 | ||
1b894b59 CW |
696 | static bool intel_PLL_is_valid(struct drm_device *dev, |
697 | const intel_limit_t *limit, | |
698 | const intel_clock_t *clock) | |
79e53945 | 699 | { |
f01b7962 VS |
700 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
701 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 702 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 703 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 704 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 705 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 706 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 707 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 708 | |
666a4537 WB |
709 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && |
710 | !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) | |
f01b7962 VS |
711 | if (clock->m1 <= clock->m2) |
712 | INTELPllInvalid("m1 <= m2\n"); | |
713 | ||
666a4537 | 714 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) { |
f01b7962 VS |
715 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
716 | INTELPllInvalid("p out of range\n"); | |
717 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
718 | INTELPllInvalid("m out of range\n"); | |
719 | } | |
720 | ||
79e53945 | 721 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 722 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
723 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
724 | * connector, etc., rather than just a single range. | |
725 | */ | |
726 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 727 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
728 | |
729 | return true; | |
730 | } | |
731 | ||
3b1429d9 VS |
732 | static int |
733 | i9xx_select_p2_div(const intel_limit_t *limit, | |
734 | const struct intel_crtc_state *crtc_state, | |
735 | int target) | |
79e53945 | 736 | { |
3b1429d9 | 737 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 738 | |
a93e255f | 739 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 740 | /* |
a210b028 DV |
741 | * For LVDS just rely on its current settings for dual-channel. |
742 | * We haven't figured out how to reliably set up different | |
743 | * single/dual channel state, if we even can. | |
79e53945 | 744 | */ |
1974cad0 | 745 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 746 | return limit->p2.p2_fast; |
79e53945 | 747 | else |
3b1429d9 | 748 | return limit->p2.p2_slow; |
79e53945 JB |
749 | } else { |
750 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 751 | return limit->p2.p2_slow; |
79e53945 | 752 | else |
3b1429d9 | 753 | return limit->p2.p2_fast; |
79e53945 | 754 | } |
3b1429d9 VS |
755 | } |
756 | ||
757 | static bool | |
758 | i9xx_find_best_dpll(const intel_limit_t *limit, | |
759 | struct intel_crtc_state *crtc_state, | |
760 | int target, int refclk, intel_clock_t *match_clock, | |
761 | intel_clock_t *best_clock) | |
762 | { | |
763 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
764 | intel_clock_t clock; | |
765 | int err = target; | |
79e53945 | 766 | |
0206e353 | 767 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 768 | |
3b1429d9 VS |
769 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
770 | ||
42158660 ZY |
771 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
772 | clock.m1++) { | |
773 | for (clock.m2 = limit->m2.min; | |
774 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 775 | if (clock.m2 >= clock.m1) |
42158660 ZY |
776 | break; |
777 | for (clock.n = limit->n.min; | |
778 | clock.n <= limit->n.max; clock.n++) { | |
779 | for (clock.p1 = limit->p1.min; | |
780 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
781 | int this_err; |
782 | ||
dccbea3b | 783 | i9xx_calc_dpll_params(refclk, &clock); |
ac58c3f0 DV |
784 | if (!intel_PLL_is_valid(dev, limit, |
785 | &clock)) | |
786 | continue; | |
787 | if (match_clock && | |
788 | clock.p != match_clock->p) | |
789 | continue; | |
790 | ||
791 | this_err = abs(clock.dot - target); | |
792 | if (this_err < err) { | |
793 | *best_clock = clock; | |
794 | err = this_err; | |
795 | } | |
796 | } | |
797 | } | |
798 | } | |
799 | } | |
800 | ||
801 | return (err != target); | |
802 | } | |
803 | ||
804 | static bool | |
a93e255f ACO |
805 | pnv_find_best_dpll(const intel_limit_t *limit, |
806 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
807 | int target, int refclk, intel_clock_t *match_clock, |
808 | intel_clock_t *best_clock) | |
79e53945 | 809 | { |
3b1429d9 | 810 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 811 | intel_clock_t clock; |
79e53945 JB |
812 | int err = target; |
813 | ||
0206e353 | 814 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 815 | |
3b1429d9 VS |
816 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
817 | ||
42158660 ZY |
818 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
819 | clock.m1++) { | |
820 | for (clock.m2 = limit->m2.min; | |
821 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
822 | for (clock.n = limit->n.min; |
823 | clock.n <= limit->n.max; clock.n++) { | |
824 | for (clock.p1 = limit->p1.min; | |
825 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
826 | int this_err; |
827 | ||
dccbea3b | 828 | pnv_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
829 | if (!intel_PLL_is_valid(dev, limit, |
830 | &clock)) | |
79e53945 | 831 | continue; |
cec2f356 SP |
832 | if (match_clock && |
833 | clock.p != match_clock->p) | |
834 | continue; | |
79e53945 JB |
835 | |
836 | this_err = abs(clock.dot - target); | |
837 | if (this_err < err) { | |
838 | *best_clock = clock; | |
839 | err = this_err; | |
840 | } | |
841 | } | |
842 | } | |
843 | } | |
844 | } | |
845 | ||
846 | return (err != target); | |
847 | } | |
848 | ||
997c030c ACO |
849 | /* |
850 | * Returns a set of divisors for the desired target clock with the given | |
851 | * refclk, or FALSE. The returned values represent the clock equation: | |
852 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
853 | */ | |
d4906093 | 854 | static bool |
a93e255f ACO |
855 | g4x_find_best_dpll(const intel_limit_t *limit, |
856 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
857 | int target, int refclk, intel_clock_t *match_clock, |
858 | intel_clock_t *best_clock) | |
d4906093 | 859 | { |
3b1429d9 | 860 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d4906093 ML |
861 | intel_clock_t clock; |
862 | int max_n; | |
3b1429d9 | 863 | bool found = false; |
6ba770dc AJ |
864 | /* approximately equals target * 0.00585 */ |
865 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
866 | |
867 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
868 | |
869 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
870 | ||
d4906093 | 871 | max_n = limit->n.max; |
f77f13e2 | 872 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 873 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 874 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
875 | for (clock.m1 = limit->m1.max; |
876 | clock.m1 >= limit->m1.min; clock.m1--) { | |
877 | for (clock.m2 = limit->m2.max; | |
878 | clock.m2 >= limit->m2.min; clock.m2--) { | |
879 | for (clock.p1 = limit->p1.max; | |
880 | clock.p1 >= limit->p1.min; clock.p1--) { | |
881 | int this_err; | |
882 | ||
dccbea3b | 883 | i9xx_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
884 | if (!intel_PLL_is_valid(dev, limit, |
885 | &clock)) | |
d4906093 | 886 | continue; |
1b894b59 CW |
887 | |
888 | this_err = abs(clock.dot - target); | |
d4906093 ML |
889 | if (this_err < err_most) { |
890 | *best_clock = clock; | |
891 | err_most = this_err; | |
892 | max_n = clock.n; | |
893 | found = true; | |
894 | } | |
895 | } | |
896 | } | |
897 | } | |
898 | } | |
2c07245f ZW |
899 | return found; |
900 | } | |
901 | ||
d5dd62bd ID |
902 | /* |
903 | * Check if the calculated PLL configuration is more optimal compared to the | |
904 | * best configuration and error found so far. Return the calculated error. | |
905 | */ | |
906 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
907 | const intel_clock_t *calculated_clock, | |
908 | const intel_clock_t *best_clock, | |
909 | unsigned int best_error_ppm, | |
910 | unsigned int *error_ppm) | |
911 | { | |
9ca3ba01 ID |
912 | /* |
913 | * For CHV ignore the error and consider only the P value. | |
914 | * Prefer a bigger P value based on HW requirements. | |
915 | */ | |
916 | if (IS_CHERRYVIEW(dev)) { | |
917 | *error_ppm = 0; | |
918 | ||
919 | return calculated_clock->p > best_clock->p; | |
920 | } | |
921 | ||
24be4e46 ID |
922 | if (WARN_ON_ONCE(!target_freq)) |
923 | return false; | |
924 | ||
d5dd62bd ID |
925 | *error_ppm = div_u64(1000000ULL * |
926 | abs(target_freq - calculated_clock->dot), | |
927 | target_freq); | |
928 | /* | |
929 | * Prefer a better P value over a better (smaller) error if the error | |
930 | * is small. Ensure this preference for future configurations too by | |
931 | * setting the error to 0. | |
932 | */ | |
933 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
934 | *error_ppm = 0; | |
935 | ||
936 | return true; | |
937 | } | |
938 | ||
939 | return *error_ppm + 10 < best_error_ppm; | |
940 | } | |
941 | ||
a0c4da24 | 942 | static bool |
a93e255f ACO |
943 | vlv_find_best_dpll(const intel_limit_t *limit, |
944 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
945 | int target, int refclk, intel_clock_t *match_clock, |
946 | intel_clock_t *best_clock) | |
a0c4da24 | 947 | { |
a93e255f | 948 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 949 | struct drm_device *dev = crtc->base.dev; |
6b4bf1c4 | 950 | intel_clock_t clock; |
69e4f900 | 951 | unsigned int bestppm = 1000000; |
27e639bf VS |
952 | /* min update 19.2 MHz */ |
953 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 954 | bool found = false; |
a0c4da24 | 955 | |
6b4bf1c4 VS |
956 | target *= 5; /* fast clock */ |
957 | ||
958 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
959 | |
960 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 961 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 962 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 963 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 964 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 965 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 966 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 967 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 968 | unsigned int ppm; |
69e4f900 | 969 | |
6b4bf1c4 VS |
970 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
971 | refclk * clock.m1); | |
972 | ||
dccbea3b | 973 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 974 | |
f01b7962 VS |
975 | if (!intel_PLL_is_valid(dev, limit, |
976 | &clock)) | |
43b0ac53 VS |
977 | continue; |
978 | ||
d5dd62bd ID |
979 | if (!vlv_PLL_is_optimal(dev, target, |
980 | &clock, | |
981 | best_clock, | |
982 | bestppm, &ppm)) | |
983 | continue; | |
6b4bf1c4 | 984 | |
d5dd62bd ID |
985 | *best_clock = clock; |
986 | bestppm = ppm; | |
987 | found = true; | |
a0c4da24 JB |
988 | } |
989 | } | |
990 | } | |
991 | } | |
a0c4da24 | 992 | |
49e497ef | 993 | return found; |
a0c4da24 | 994 | } |
a4fc5ed6 | 995 | |
ef9348c8 | 996 | static bool |
a93e255f ACO |
997 | chv_find_best_dpll(const intel_limit_t *limit, |
998 | struct intel_crtc_state *crtc_state, | |
ef9348c8 CML |
999 | int target, int refclk, intel_clock_t *match_clock, |
1000 | intel_clock_t *best_clock) | |
1001 | { | |
a93e255f | 1002 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 1003 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 1004 | unsigned int best_error_ppm; |
ef9348c8 CML |
1005 | intel_clock_t clock; |
1006 | uint64_t m2; | |
1007 | int found = false; | |
1008 | ||
1009 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 1010 | best_error_ppm = 1000000; |
ef9348c8 CML |
1011 | |
1012 | /* | |
1013 | * Based on hardware doc, the n always set to 1, and m1 always | |
1014 | * set to 2. If requires to support 200Mhz refclk, we need to | |
1015 | * revisit this because n may not 1 anymore. | |
1016 | */ | |
1017 | clock.n = 1, clock.m1 = 2; | |
1018 | target *= 5; /* fast clock */ | |
1019 | ||
1020 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
1021 | for (clock.p2 = limit->p2.p2_fast; | |
1022 | clock.p2 >= limit->p2.p2_slow; | |
1023 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 1024 | unsigned int error_ppm; |
ef9348c8 CML |
1025 | |
1026 | clock.p = clock.p1 * clock.p2; | |
1027 | ||
1028 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
1029 | clock.n) << 22, refclk * clock.m1); | |
1030 | ||
1031 | if (m2 > INT_MAX/clock.m1) | |
1032 | continue; | |
1033 | ||
1034 | clock.m2 = m2; | |
1035 | ||
dccbea3b | 1036 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 CML |
1037 | |
1038 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
1039 | continue; | |
1040 | ||
9ca3ba01 ID |
1041 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
1042 | best_error_ppm, &error_ppm)) | |
1043 | continue; | |
1044 | ||
1045 | *best_clock = clock; | |
1046 | best_error_ppm = error_ppm; | |
1047 | found = true; | |
ef9348c8 CML |
1048 | } |
1049 | } | |
1050 | ||
1051 | return found; | |
1052 | } | |
1053 | ||
5ab7b0b7 ID |
1054 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
1055 | intel_clock_t *best_clock) | |
1056 | { | |
ceb41007 | 1057 | int refclk = i9xx_get_refclk(crtc_state); |
5ab7b0b7 ID |
1058 | |
1059 | return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state, | |
1060 | target_clock, refclk, NULL, best_clock); | |
1061 | } | |
1062 | ||
20ddf665 VS |
1063 | bool intel_crtc_active(struct drm_crtc *crtc) |
1064 | { | |
1065 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1066 | ||
1067 | /* Be paranoid as we can arrive here with only partial | |
1068 | * state retrieved from the hardware during setup. | |
1069 | * | |
241bfc38 | 1070 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
1071 | * as Haswell has gained clock readout/fastboot support. |
1072 | * | |
66e514c1 | 1073 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 1074 | * properly reconstruct framebuffers. |
c3d1f436 MR |
1075 | * |
1076 | * FIXME: The intel_crtc->active here should be switched to | |
1077 | * crtc->state->active once we have proper CRTC states wired up | |
1078 | * for atomic. | |
20ddf665 | 1079 | */ |
c3d1f436 | 1080 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 1081 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
1082 | } |
1083 | ||
a5c961d1 PZ |
1084 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1085 | enum pipe pipe) | |
1086 | { | |
1087 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1088 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1089 | ||
6e3c9717 | 1090 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1091 | } |
1092 | ||
fbf49ea2 VS |
1093 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
1094 | { | |
1095 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1096 | i915_reg_t reg = PIPEDSL(pipe); |
fbf49ea2 VS |
1097 | u32 line1, line2; |
1098 | u32 line_mask; | |
1099 | ||
1100 | if (IS_GEN2(dev)) | |
1101 | line_mask = DSL_LINEMASK_GEN2; | |
1102 | else | |
1103 | line_mask = DSL_LINEMASK_GEN3; | |
1104 | ||
1105 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 1106 | msleep(5); |
fbf49ea2 VS |
1107 | line2 = I915_READ(reg) & line_mask; |
1108 | ||
1109 | return line1 == line2; | |
1110 | } | |
1111 | ||
ab7ad7f6 KP |
1112 | /* |
1113 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1114 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1115 | * |
1116 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1117 | * spinning on the vblank interrupt status bit, since we won't actually | |
1118 | * see an interrupt when the pipe is disabled. | |
1119 | * | |
ab7ad7f6 KP |
1120 | * On Gen4 and above: |
1121 | * wait for the pipe register state bit to turn off | |
1122 | * | |
1123 | * Otherwise: | |
1124 | * wait for the display line value to settle (it usually | |
1125 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1126 | * |
9d0498a2 | 1127 | */ |
575f7ab7 | 1128 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1129 | { |
575f7ab7 | 1130 | struct drm_device *dev = crtc->base.dev; |
9d0498a2 | 1131 | struct drm_i915_private *dev_priv = dev->dev_private; |
6e3c9717 | 1132 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1133 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
1134 | |
1135 | if (INTEL_INFO(dev)->gen >= 4) { | |
f0f59a00 | 1136 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1137 | |
1138 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
1139 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1140 | 100)) | |
284637d9 | 1141 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1142 | } else { |
ab7ad7f6 | 1143 | /* Wait for the display line to settle */ |
fbf49ea2 | 1144 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1145 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1146 | } |
79e53945 JB |
1147 | } |
1148 | ||
b24e7179 | 1149 | /* Only for pre-ILK configs */ |
55607e8a DV |
1150 | void assert_pll(struct drm_i915_private *dev_priv, |
1151 | enum pipe pipe, bool state) | |
b24e7179 | 1152 | { |
b24e7179 JB |
1153 | u32 val; |
1154 | bool cur_state; | |
1155 | ||
649636ef | 1156 | val = I915_READ(DPLL(pipe)); |
b24e7179 | 1157 | cur_state = !!(val & DPLL_VCO_ENABLE); |
e2c719b7 | 1158 | I915_STATE_WARN(cur_state != state, |
b24e7179 | 1159 | "PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1160 | onoff(state), onoff(cur_state)); |
b24e7179 | 1161 | } |
b24e7179 | 1162 | |
23538ef1 | 1163 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
8563b1e8 | 1164 | void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) |
23538ef1 JN |
1165 | { |
1166 | u32 val; | |
1167 | bool cur_state; | |
1168 | ||
a580516d | 1169 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1170 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1171 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1172 | |
1173 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1174 | I915_STATE_WARN(cur_state != state, |
23538ef1 | 1175 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1176 | onoff(state), onoff(cur_state)); |
23538ef1 | 1177 | } |
23538ef1 | 1178 | |
040484af JB |
1179 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
1180 | enum pipe pipe, bool state) | |
1181 | { | |
040484af | 1182 | bool cur_state; |
ad80a810 PZ |
1183 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1184 | pipe); | |
040484af | 1185 | |
affa9354 PZ |
1186 | if (HAS_DDI(dev_priv->dev)) { |
1187 | /* DDI does not have a specific FDI_TX register */ | |
649636ef | 1188 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
ad80a810 | 1189 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 | 1190 | } else { |
649636ef | 1191 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
bf507ef7 ED |
1192 | cur_state = !!(val & FDI_TX_ENABLE); |
1193 | } | |
e2c719b7 | 1194 | I915_STATE_WARN(cur_state != state, |
040484af | 1195 | "FDI TX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1196 | onoff(state), onoff(cur_state)); |
040484af JB |
1197 | } |
1198 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1199 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1200 | ||
1201 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1202 | enum pipe pipe, bool state) | |
1203 | { | |
040484af JB |
1204 | u32 val; |
1205 | bool cur_state; | |
1206 | ||
649636ef | 1207 | val = I915_READ(FDI_RX_CTL(pipe)); |
d63fa0dc | 1208 | cur_state = !!(val & FDI_RX_ENABLE); |
e2c719b7 | 1209 | I915_STATE_WARN(cur_state != state, |
040484af | 1210 | "FDI RX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1211 | onoff(state), onoff(cur_state)); |
040484af JB |
1212 | } |
1213 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1214 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1215 | ||
1216 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1217 | enum pipe pipe) | |
1218 | { | |
040484af JB |
1219 | u32 val; |
1220 | ||
1221 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1222 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1223 | return; |
1224 | ||
bf507ef7 | 1225 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1226 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1227 | return; |
1228 | ||
649636ef | 1229 | val = I915_READ(FDI_TX_CTL(pipe)); |
e2c719b7 | 1230 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1231 | } |
1232 | ||
55607e8a DV |
1233 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1234 | enum pipe pipe, bool state) | |
040484af | 1235 | { |
040484af | 1236 | u32 val; |
55607e8a | 1237 | bool cur_state; |
040484af | 1238 | |
649636ef | 1239 | val = I915_READ(FDI_RX_CTL(pipe)); |
55607e8a | 1240 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1241 | I915_STATE_WARN(cur_state != state, |
55607e8a | 1242 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
87ad3212 | 1243 | onoff(state), onoff(cur_state)); |
040484af JB |
1244 | } |
1245 | ||
b680c37a DV |
1246 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1247 | enum pipe pipe) | |
ea0760cf | 1248 | { |
bedd4dba | 1249 | struct drm_device *dev = dev_priv->dev; |
f0f59a00 | 1250 | i915_reg_t pp_reg; |
ea0760cf JB |
1251 | u32 val; |
1252 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1253 | bool locked = true; |
ea0760cf | 1254 | |
bedd4dba JN |
1255 | if (WARN_ON(HAS_DDI(dev))) |
1256 | return; | |
1257 | ||
1258 | if (HAS_PCH_SPLIT(dev)) { | |
1259 | u32 port_sel; | |
1260 | ||
ea0760cf | 1261 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1262 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1263 | ||
1264 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1265 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1266 | panel_pipe = PIPE_B; | |
1267 | /* XXX: else fix for eDP */ | |
666a4537 | 1268 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
bedd4dba JN |
1269 | /* presumably write lock depends on pipe, not port select */ |
1270 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1271 | panel_pipe = pipe; | |
ea0760cf JB |
1272 | } else { |
1273 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1274 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1275 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1276 | } |
1277 | ||
1278 | val = I915_READ(pp_reg); | |
1279 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1280 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1281 | locked = false; |
1282 | ||
e2c719b7 | 1283 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1284 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1285 | pipe_name(pipe)); |
ea0760cf JB |
1286 | } |
1287 | ||
93ce0ba6 JN |
1288 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1289 | enum pipe pipe, bool state) | |
1290 | { | |
1291 | struct drm_device *dev = dev_priv->dev; | |
1292 | bool cur_state; | |
1293 | ||
d9d82081 | 1294 | if (IS_845G(dev) || IS_I865G(dev)) |
0b87c24e | 1295 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
d9d82081 | 1296 | else |
5efb3e28 | 1297 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1298 | |
e2c719b7 | 1299 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 | 1300 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1301 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
93ce0ba6 JN |
1302 | } |
1303 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1304 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1305 | ||
b840d907 JB |
1306 | void assert_pipe(struct drm_i915_private *dev_priv, |
1307 | enum pipe pipe, bool state) | |
b24e7179 | 1308 | { |
63d7bbe9 | 1309 | bool cur_state; |
702e7a56 PZ |
1310 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1311 | pipe); | |
4feed0eb | 1312 | enum intel_display_power_domain power_domain; |
b24e7179 | 1313 | |
b6b5d049 VS |
1314 | /* if we need the pipe quirk it must be always on */ |
1315 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1316 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1317 | state = true; |
1318 | ||
4feed0eb ID |
1319 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); |
1320 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
649636ef | 1321 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
69310161 | 1322 | cur_state = !!(val & PIPECONF_ENABLE); |
4feed0eb ID |
1323 | |
1324 | intel_display_power_put(dev_priv, power_domain); | |
1325 | } else { | |
1326 | cur_state = false; | |
69310161 PZ |
1327 | } |
1328 | ||
e2c719b7 | 1329 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1330 | "pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1331 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1332 | } |
1333 | ||
931872fc CW |
1334 | static void assert_plane(struct drm_i915_private *dev_priv, |
1335 | enum plane plane, bool state) | |
b24e7179 | 1336 | { |
b24e7179 | 1337 | u32 val; |
931872fc | 1338 | bool cur_state; |
b24e7179 | 1339 | |
649636ef | 1340 | val = I915_READ(DSPCNTR(plane)); |
931872fc | 1341 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1342 | I915_STATE_WARN(cur_state != state, |
931872fc | 1343 | "plane %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1344 | plane_name(plane), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1345 | } |
1346 | ||
931872fc CW |
1347 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1348 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1349 | ||
b24e7179 JB |
1350 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1351 | enum pipe pipe) | |
1352 | { | |
653e1026 | 1353 | struct drm_device *dev = dev_priv->dev; |
649636ef | 1354 | int i; |
b24e7179 | 1355 | |
653e1026 VS |
1356 | /* Primary planes are fixed to pipes on gen4+ */ |
1357 | if (INTEL_INFO(dev)->gen >= 4) { | |
649636ef | 1358 | u32 val = I915_READ(DSPCNTR(pipe)); |
e2c719b7 | 1359 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1360 | "plane %c assertion failure, should be disabled but not\n", |
1361 | plane_name(pipe)); | |
19ec1358 | 1362 | return; |
28c05794 | 1363 | } |
19ec1358 | 1364 | |
b24e7179 | 1365 | /* Need to check both planes against the pipe */ |
055e393f | 1366 | for_each_pipe(dev_priv, i) { |
649636ef VS |
1367 | u32 val = I915_READ(DSPCNTR(i)); |
1368 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
b24e7179 | 1369 | DISPPLANE_SEL_PIPE_SHIFT; |
e2c719b7 | 1370 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1371 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1372 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1373 | } |
1374 | } | |
1375 | ||
19332d7a JB |
1376 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1377 | enum pipe pipe) | |
1378 | { | |
20674eef | 1379 | struct drm_device *dev = dev_priv->dev; |
649636ef | 1380 | int sprite; |
19332d7a | 1381 | |
7feb8b88 | 1382 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1383 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1384 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1385 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1386 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1387 | sprite, pipe_name(pipe)); | |
1388 | } | |
666a4537 | 1389 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
3bdcfc0c | 1390 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1391 | u32 val = I915_READ(SPCNTR(pipe, sprite)); |
e2c719b7 | 1392 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1393 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1394 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1395 | } |
1396 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
649636ef | 1397 | u32 val = I915_READ(SPRCTL(pipe)); |
e2c719b7 | 1398 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1399 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1400 | plane_name(pipe), pipe_name(pipe)); |
1401 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
649636ef | 1402 | u32 val = I915_READ(DVSCNTR(pipe)); |
e2c719b7 | 1403 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1404 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1405 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1406 | } |
1407 | } | |
1408 | ||
08c71e5e VS |
1409 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1410 | { | |
e2c719b7 | 1411 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1412 | drm_crtc_vblank_put(crtc); |
1413 | } | |
1414 | ||
7abd4b35 ACO |
1415 | void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1416 | enum pipe pipe) | |
92f2584a | 1417 | { |
92f2584a JB |
1418 | u32 val; |
1419 | bool enabled; | |
1420 | ||
649636ef | 1421 | val = I915_READ(PCH_TRANSCONF(pipe)); |
92f2584a | 1422 | enabled = !!(val & TRANS_ENABLE); |
e2c719b7 | 1423 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1424 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1425 | pipe_name(pipe)); | |
92f2584a JB |
1426 | } |
1427 | ||
4e634389 KP |
1428 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1429 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1430 | { |
1431 | if ((val & DP_PORT_EN) == 0) | |
1432 | return false; | |
1433 | ||
1434 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
f0f59a00 | 1435 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
f0575e92 KP |
1436 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1437 | return false; | |
44f37d1f CML |
1438 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1439 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1440 | return false; | |
f0575e92 KP |
1441 | } else { |
1442 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1443 | return false; | |
1444 | } | |
1445 | return true; | |
1446 | } | |
1447 | ||
1519b995 KP |
1448 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1449 | enum pipe pipe, u32 val) | |
1450 | { | |
dc0fa718 | 1451 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1452 | return false; |
1453 | ||
1454 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1455 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1456 | return false; |
44f37d1f CML |
1457 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1458 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1459 | return false; | |
1519b995 | 1460 | } else { |
dc0fa718 | 1461 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1462 | return false; |
1463 | } | |
1464 | return true; | |
1465 | } | |
1466 | ||
1467 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1468 | enum pipe pipe, u32 val) | |
1469 | { | |
1470 | if ((val & LVDS_PORT_EN) == 0) | |
1471 | return false; | |
1472 | ||
1473 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1474 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1475 | return false; | |
1476 | } else { | |
1477 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1478 | return false; | |
1479 | } | |
1480 | return true; | |
1481 | } | |
1482 | ||
1483 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1484 | enum pipe pipe, u32 val) | |
1485 | { | |
1486 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1487 | return false; | |
1488 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1489 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1490 | return false; | |
1491 | } else { | |
1492 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1493 | return false; | |
1494 | } | |
1495 | return true; | |
1496 | } | |
1497 | ||
291906f1 | 1498 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
1499 | enum pipe pipe, i915_reg_t reg, |
1500 | u32 port_sel) | |
291906f1 | 1501 | { |
47a05eca | 1502 | u32 val = I915_READ(reg); |
e2c719b7 | 1503 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1504 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1505 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1506 | |
e2c719b7 | 1507 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1508 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1509 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1510 | } |
1511 | ||
1512 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
f0f59a00 | 1513 | enum pipe pipe, i915_reg_t reg) |
291906f1 | 1514 | { |
47a05eca | 1515 | u32 val = I915_READ(reg); |
e2c719b7 | 1516 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1517 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1518 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1519 | |
e2c719b7 | 1520 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1521 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1522 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1523 | } |
1524 | ||
1525 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1526 | enum pipe pipe) | |
1527 | { | |
291906f1 | 1528 | u32 val; |
291906f1 | 1529 | |
f0575e92 KP |
1530 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1531 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1532 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 | 1533 | |
649636ef | 1534 | val = I915_READ(PCH_ADPA); |
e2c719b7 | 1535 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1536 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1537 | pipe_name(pipe)); |
291906f1 | 1538 | |
649636ef | 1539 | val = I915_READ(PCH_LVDS); |
e2c719b7 | 1540 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1541 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1542 | pipe_name(pipe)); |
291906f1 | 1543 | |
e2debe91 PZ |
1544 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1545 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1546 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1547 | } |
1548 | ||
d288f65f | 1549 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1550 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1551 | { |
426115cf DV |
1552 | struct drm_device *dev = crtc->base.dev; |
1553 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1554 | i915_reg_t reg = DPLL(crtc->pipe); |
d288f65f | 1555 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
87442f73 | 1556 | |
426115cf | 1557 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 | 1558 | |
87442f73 | 1559 | /* PLL is protected by panel, make sure we can write it */ |
6a9e7363 | 1560 | if (IS_MOBILE(dev_priv->dev)) |
426115cf | 1561 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1562 | |
426115cf DV |
1563 | I915_WRITE(reg, dpll); |
1564 | POSTING_READ(reg); | |
1565 | udelay(150); | |
1566 | ||
1567 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1568 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1569 | ||
d288f65f | 1570 | I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); |
426115cf | 1571 | POSTING_READ(DPLL_MD(crtc->pipe)); |
87442f73 DV |
1572 | |
1573 | /* We do this three times for luck */ | |
426115cf | 1574 | I915_WRITE(reg, dpll); |
87442f73 DV |
1575 | POSTING_READ(reg); |
1576 | udelay(150); /* wait for warmup */ | |
426115cf | 1577 | I915_WRITE(reg, dpll); |
87442f73 DV |
1578 | POSTING_READ(reg); |
1579 | udelay(150); /* wait for warmup */ | |
426115cf | 1580 | I915_WRITE(reg, dpll); |
87442f73 DV |
1581 | POSTING_READ(reg); |
1582 | udelay(150); /* wait for warmup */ | |
1583 | } | |
1584 | ||
d288f65f | 1585 | static void chv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1586 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
1587 | { |
1588 | struct drm_device *dev = crtc->base.dev; | |
1589 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1590 | int pipe = crtc->pipe; | |
1591 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1592 | u32 tmp; |
1593 | ||
1594 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1595 | ||
a580516d | 1596 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1597 | |
1598 | /* Enable back the 10bit clock to display controller */ | |
1599 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1600 | tmp |= DPIO_DCLKP_EN; | |
1601 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1602 | ||
54433e91 VS |
1603 | mutex_unlock(&dev_priv->sb_lock); |
1604 | ||
9d556c99 CML |
1605 | /* |
1606 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1607 | */ | |
1608 | udelay(1); | |
1609 | ||
1610 | /* Enable PLL */ | |
d288f65f | 1611 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1612 | |
1613 | /* Check PLL is locked */ | |
a11b0703 | 1614 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1615 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1616 | ||
a11b0703 | 1617 | /* not sure when this should be written */ |
d288f65f | 1618 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
a11b0703 | 1619 | POSTING_READ(DPLL_MD(pipe)); |
9d556c99 CML |
1620 | } |
1621 | ||
1c4e0274 VS |
1622 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1623 | { | |
1624 | struct intel_crtc *crtc; | |
1625 | int count = 0; | |
1626 | ||
1627 | for_each_intel_crtc(dev, crtc) | |
3538b9df | 1628 | count += crtc->base.state->active && |
409ee761 | 1629 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
1c4e0274 VS |
1630 | |
1631 | return count; | |
1632 | } | |
1633 | ||
66e3d5c0 | 1634 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1635 | { |
66e3d5c0 DV |
1636 | struct drm_device *dev = crtc->base.dev; |
1637 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1638 | i915_reg_t reg = DPLL(crtc->pipe); |
6e3c9717 | 1639 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1640 | |
66e3d5c0 | 1641 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1642 | |
63d7bbe9 | 1643 | /* No really, not for ILK+ */ |
3d13ef2e | 1644 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1645 | |
1646 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1647 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1648 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1649 | |
1c4e0274 VS |
1650 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1651 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1652 | /* | |
1653 | * It appears to be important that we don't enable this | |
1654 | * for the current pipe before otherwise configuring the | |
1655 | * PLL. No idea how this should be handled if multiple | |
1656 | * DVO outputs are enabled simultaneosly. | |
1657 | */ | |
1658 | dpll |= DPLL_DVO_2X_MODE; | |
1659 | I915_WRITE(DPLL(!crtc->pipe), | |
1660 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1661 | } | |
66e3d5c0 | 1662 | |
c2b63374 VS |
1663 | /* |
1664 | * Apparently we need to have VGA mode enabled prior to changing | |
1665 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1666 | * dividers, even though the register value does change. | |
1667 | */ | |
1668 | I915_WRITE(reg, 0); | |
1669 | ||
8e7a65aa VS |
1670 | I915_WRITE(reg, dpll); |
1671 | ||
66e3d5c0 DV |
1672 | /* Wait for the clocks to stabilize. */ |
1673 | POSTING_READ(reg); | |
1674 | udelay(150); | |
1675 | ||
1676 | if (INTEL_INFO(dev)->gen >= 4) { | |
1677 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1678 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1679 | } else { |
1680 | /* The pixel multiplier can only be updated once the | |
1681 | * DPLL is enabled and the clocks are stable. | |
1682 | * | |
1683 | * So write it again. | |
1684 | */ | |
1685 | I915_WRITE(reg, dpll); | |
1686 | } | |
63d7bbe9 JB |
1687 | |
1688 | /* We do this three times for luck */ | |
66e3d5c0 | 1689 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1690 | POSTING_READ(reg); |
1691 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1692 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1693 | POSTING_READ(reg); |
1694 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1695 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1696 | POSTING_READ(reg); |
1697 | udelay(150); /* wait for warmup */ | |
1698 | } | |
1699 | ||
1700 | /** | |
50b44a44 | 1701 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1702 | * @dev_priv: i915 private structure |
1703 | * @pipe: pipe PLL to disable | |
1704 | * | |
1705 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1706 | * | |
1707 | * Note! This is for pre-ILK only. | |
1708 | */ | |
1c4e0274 | 1709 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1710 | { |
1c4e0274 VS |
1711 | struct drm_device *dev = crtc->base.dev; |
1712 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1713 | enum pipe pipe = crtc->pipe; | |
1714 | ||
1715 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1716 | if (IS_I830(dev) && | |
409ee761 | 1717 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
3538b9df | 1718 | !intel_num_dvo_pipes(dev)) { |
1c4e0274 VS |
1719 | I915_WRITE(DPLL(PIPE_B), |
1720 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1721 | I915_WRITE(DPLL(PIPE_A), | |
1722 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1723 | } | |
1724 | ||
b6b5d049 VS |
1725 | /* Don't disable pipe or pipe PLLs if needed */ |
1726 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1727 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1728 | return; |
1729 | ||
1730 | /* Make sure the pipe isn't still relying on us */ | |
1731 | assert_pipe_disabled(dev_priv, pipe); | |
1732 | ||
b8afb911 | 1733 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1734 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1735 | } |
1736 | ||
f6071166 JB |
1737 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1738 | { | |
b8afb911 | 1739 | u32 val; |
f6071166 JB |
1740 | |
1741 | /* Make sure the pipe isn't still relying on us */ | |
1742 | assert_pipe_disabled(dev_priv, pipe); | |
1743 | ||
e5cbfbfb ID |
1744 | /* |
1745 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1746 | * The latter is needed for VGA hotplug / manual detection. | |
1747 | */ | |
b8afb911 | 1748 | val = DPLL_VGA_MODE_DIS; |
f6071166 | 1749 | if (pipe == PIPE_B) |
60bfe44f | 1750 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV; |
f6071166 JB |
1751 | I915_WRITE(DPLL(pipe), val); |
1752 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1753 | |
1754 | } | |
1755 | ||
1756 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1757 | { | |
d752048d | 1758 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1759 | u32 val; |
1760 | ||
a11b0703 VS |
1761 | /* Make sure the pipe isn't still relying on us */ |
1762 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1763 | |
a11b0703 | 1764 | /* Set PLL en = 0 */ |
60bfe44f VS |
1765 | val = DPLL_SSC_REF_CLK_CHV | |
1766 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1767 | if (pipe != PIPE_A) |
1768 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1769 | I915_WRITE(DPLL(pipe), val); | |
1770 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1771 | |
a580516d | 1772 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1773 | |
1774 | /* Disable 10bit clock to display controller */ | |
1775 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1776 | val &= ~DPIO_DCLKP_EN; | |
1777 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1778 | ||
a580516d | 1779 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1780 | } |
1781 | ||
e4607fcf | 1782 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1783 | struct intel_digital_port *dport, |
1784 | unsigned int expected_mask) | |
89b667f8 JB |
1785 | { |
1786 | u32 port_mask; | |
f0f59a00 | 1787 | i915_reg_t dpll_reg; |
89b667f8 | 1788 | |
e4607fcf CML |
1789 | switch (dport->port) { |
1790 | case PORT_B: | |
89b667f8 | 1791 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1792 | dpll_reg = DPLL(0); |
e4607fcf CML |
1793 | break; |
1794 | case PORT_C: | |
89b667f8 | 1795 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1796 | dpll_reg = DPLL(0); |
9b6de0a1 | 1797 | expected_mask <<= 4; |
00fc31b7 CML |
1798 | break; |
1799 | case PORT_D: | |
1800 | port_mask = DPLL_PORTD_READY_MASK; | |
1801 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1802 | break; |
1803 | default: | |
1804 | BUG(); | |
1805 | } | |
89b667f8 | 1806 | |
9b6de0a1 VS |
1807 | if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000)) |
1808 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", | |
1809 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1810 | } |
1811 | ||
b8a4f404 PZ |
1812 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1813 | enum pipe pipe) | |
040484af | 1814 | { |
23670b32 | 1815 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1816 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1817 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
f0f59a00 VS |
1818 | i915_reg_t reg; |
1819 | uint32_t val, pipeconf_val; | |
040484af JB |
1820 | |
1821 | /* PCH only available on ILK+ */ | |
55522f37 | 1822 | BUG_ON(!HAS_PCH_SPLIT(dev)); |
040484af JB |
1823 | |
1824 | /* Make sure PCH DPLL is enabled */ | |
8106ddbd | 1825 | assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll); |
040484af JB |
1826 | |
1827 | /* FDI must be feeding us bits for PCH ports */ | |
1828 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1829 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1830 | ||
23670b32 DV |
1831 | if (HAS_PCH_CPT(dev)) { |
1832 | /* Workaround: Set the timing override bit before enabling the | |
1833 | * pch transcoder. */ | |
1834 | reg = TRANS_CHICKEN2(pipe); | |
1835 | val = I915_READ(reg); | |
1836 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1837 | I915_WRITE(reg, val); | |
59c859d6 | 1838 | } |
23670b32 | 1839 | |
ab9412ba | 1840 | reg = PCH_TRANSCONF(pipe); |
040484af | 1841 | val = I915_READ(reg); |
5f7f726d | 1842 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1843 | |
1844 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1845 | /* | |
c5de7c6f VS |
1846 | * Make the BPC in transcoder be consistent with |
1847 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1848 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1849 | */ |
dfd07d72 | 1850 | val &= ~PIPECONF_BPC_MASK; |
c5de7c6f VS |
1851 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI)) |
1852 | val |= PIPECONF_8BPC; | |
1853 | else | |
1854 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1855 | } |
5f7f726d PZ |
1856 | |
1857 | val &= ~TRANS_INTERLACE_MASK; | |
1858 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 | 1859 | if (HAS_PCH_IBX(dev_priv->dev) && |
409ee761 | 1860 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
1861 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1862 | else | |
1863 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1864 | else |
1865 | val |= TRANS_PROGRESSIVE; | |
1866 | ||
040484af JB |
1867 | I915_WRITE(reg, val | TRANS_ENABLE); |
1868 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 1869 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1870 | } |
1871 | ||
8fb033d7 | 1872 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1873 | enum transcoder cpu_transcoder) |
040484af | 1874 | { |
8fb033d7 | 1875 | u32 val, pipeconf_val; |
8fb033d7 PZ |
1876 | |
1877 | /* PCH only available on ILK+ */ | |
55522f37 | 1878 | BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev)); |
8fb033d7 | 1879 | |
8fb033d7 | 1880 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1881 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1882 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1883 | |
223a6fdf | 1884 | /* Workaround: set timing override bit. */ |
36c0d0cf | 1885 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1886 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1887 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 1888 | |
25f3ef11 | 1889 | val = TRANS_ENABLE; |
937bb610 | 1890 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1891 | |
9a76b1c6 PZ |
1892 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1893 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1894 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1895 | else |
1896 | val |= TRANS_PROGRESSIVE; | |
1897 | ||
ab9412ba DV |
1898 | I915_WRITE(LPT_TRANSCONF, val); |
1899 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 1900 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1901 | } |
1902 | ||
b8a4f404 PZ |
1903 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1904 | enum pipe pipe) | |
040484af | 1905 | { |
23670b32 | 1906 | struct drm_device *dev = dev_priv->dev; |
f0f59a00 VS |
1907 | i915_reg_t reg; |
1908 | uint32_t val; | |
040484af JB |
1909 | |
1910 | /* FDI relies on the transcoder */ | |
1911 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1912 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1913 | ||
291906f1 JB |
1914 | /* Ports must be off as well */ |
1915 | assert_pch_ports_disabled(dev_priv, pipe); | |
1916 | ||
ab9412ba | 1917 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1918 | val = I915_READ(reg); |
1919 | val &= ~TRANS_ENABLE; | |
1920 | I915_WRITE(reg, val); | |
1921 | /* wait for PCH transcoder off, transcoder state */ | |
1922 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 1923 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 | 1924 | |
c465613b | 1925 | if (HAS_PCH_CPT(dev)) { |
23670b32 DV |
1926 | /* Workaround: Clear the timing override chicken bit again. */ |
1927 | reg = TRANS_CHICKEN2(pipe); | |
1928 | val = I915_READ(reg); | |
1929 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1930 | I915_WRITE(reg, val); | |
1931 | } | |
040484af JB |
1932 | } |
1933 | ||
ab4d966c | 1934 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1935 | { |
8fb033d7 PZ |
1936 | u32 val; |
1937 | ||
ab9412ba | 1938 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1939 | val &= ~TRANS_ENABLE; |
ab9412ba | 1940 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1941 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 1942 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 1943 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1944 | |
1945 | /* Workaround: clear timing override bit. */ | |
36c0d0cf | 1946 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1947 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1948 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
1949 | } |
1950 | ||
b24e7179 | 1951 | /** |
309cfea8 | 1952 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 1953 | * @crtc: crtc responsible for the pipe |
b24e7179 | 1954 | * |
0372264a | 1955 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 1956 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 1957 | */ |
e1fdc473 | 1958 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1959 | { |
0372264a PZ |
1960 | struct drm_device *dev = crtc->base.dev; |
1961 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1962 | enum pipe pipe = crtc->pipe; | |
1a70a728 | 1963 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
1a240d4d | 1964 | enum pipe pch_transcoder; |
f0f59a00 | 1965 | i915_reg_t reg; |
b24e7179 JB |
1966 | u32 val; |
1967 | ||
9e2ee2dd VS |
1968 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
1969 | ||
58c6eaa2 | 1970 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 1971 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
1972 | assert_sprites_disabled(dev_priv, pipe); |
1973 | ||
681e5811 | 1974 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
1975 | pch_transcoder = TRANSCODER_A; |
1976 | else | |
1977 | pch_transcoder = pipe; | |
1978 | ||
b24e7179 JB |
1979 | /* |
1980 | * A pipe without a PLL won't actually be able to drive bits from | |
1981 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1982 | * need the check. | |
1983 | */ | |
50360403 | 1984 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) |
a65347ba | 1985 | if (crtc->config->has_dsi_encoder) |
23538ef1 JN |
1986 | assert_dsi_pll_enabled(dev_priv); |
1987 | else | |
1988 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 1989 | else { |
6e3c9717 | 1990 | if (crtc->config->has_pch_encoder) { |
040484af | 1991 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 1992 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
1993 | assert_fdi_tx_pll_enabled(dev_priv, |
1994 | (enum pipe) cpu_transcoder); | |
040484af JB |
1995 | } |
1996 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1997 | } | |
b24e7179 | 1998 | |
702e7a56 | 1999 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2000 | val = I915_READ(reg); |
7ad25d48 | 2001 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
2002 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
2003 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 2004 | return; |
7ad25d48 | 2005 | } |
00d70b15 CW |
2006 | |
2007 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2008 | POSTING_READ(reg); |
b7792d8b VS |
2009 | |
2010 | /* | |
2011 | * Until the pipe starts DSL will read as 0, which would cause | |
2012 | * an apparent vblank timestamp jump, which messes up also the | |
2013 | * frame count when it's derived from the timestamps. So let's | |
2014 | * wait for the pipe to start properly before we call | |
2015 | * drm_crtc_vblank_on() | |
2016 | */ | |
2017 | if (dev->max_vblank_count == 0 && | |
2018 | wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50)) | |
2019 | DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe)); | |
b24e7179 JB |
2020 | } |
2021 | ||
2022 | /** | |
309cfea8 | 2023 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2024 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2025 | * |
575f7ab7 VS |
2026 | * Disable the pipe of @crtc, making sure that various hardware |
2027 | * specific requirements are met, if applicable, e.g. plane | |
2028 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2029 | * |
2030 | * Will wait until the pipe has shut down before returning. | |
2031 | */ | |
575f7ab7 | 2032 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2033 | { |
575f7ab7 | 2034 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
6e3c9717 | 2035 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2036 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 2037 | i915_reg_t reg; |
b24e7179 JB |
2038 | u32 val; |
2039 | ||
9e2ee2dd VS |
2040 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
2041 | ||
b24e7179 JB |
2042 | /* |
2043 | * Make sure planes won't keep trying to pump pixels to us, | |
2044 | * or we might hang the display. | |
2045 | */ | |
2046 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2047 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2048 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2049 | |
702e7a56 | 2050 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2051 | val = I915_READ(reg); |
00d70b15 CW |
2052 | if ((val & PIPECONF_ENABLE) == 0) |
2053 | return; | |
2054 | ||
67adc644 VS |
2055 | /* |
2056 | * Double wide has implications for planes | |
2057 | * so best keep it disabled when not needed. | |
2058 | */ | |
6e3c9717 | 2059 | if (crtc->config->double_wide) |
67adc644 VS |
2060 | val &= ~PIPECONF_DOUBLE_WIDE; |
2061 | ||
2062 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2063 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2064 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2065 | val &= ~PIPECONF_ENABLE; |
2066 | ||
2067 | I915_WRITE(reg, val); | |
2068 | if ((val & PIPECONF_ENABLE) == 0) | |
2069 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2070 | } |
2071 | ||
693db184 CW |
2072 | static bool need_vtd_wa(struct drm_device *dev) |
2073 | { | |
2074 | #ifdef CONFIG_INTEL_IOMMU | |
2075 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2076 | return true; | |
2077 | #endif | |
2078 | return false; | |
2079 | } | |
2080 | ||
832be82f VS |
2081 | static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) |
2082 | { | |
2083 | return IS_GEN2(dev_priv) ? 2048 : 4096; | |
2084 | } | |
2085 | ||
27ba3910 VS |
2086 | static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv, |
2087 | uint64_t fb_modifier, unsigned int cpp) | |
7b49f948 VS |
2088 | { |
2089 | switch (fb_modifier) { | |
2090 | case DRM_FORMAT_MOD_NONE: | |
2091 | return cpp; | |
2092 | case I915_FORMAT_MOD_X_TILED: | |
2093 | if (IS_GEN2(dev_priv)) | |
2094 | return 128; | |
2095 | else | |
2096 | return 512; | |
2097 | case I915_FORMAT_MOD_Y_TILED: | |
2098 | if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) | |
2099 | return 128; | |
2100 | else | |
2101 | return 512; | |
2102 | case I915_FORMAT_MOD_Yf_TILED: | |
2103 | switch (cpp) { | |
2104 | case 1: | |
2105 | return 64; | |
2106 | case 2: | |
2107 | case 4: | |
2108 | return 128; | |
2109 | case 8: | |
2110 | case 16: | |
2111 | return 256; | |
2112 | default: | |
2113 | MISSING_CASE(cpp); | |
2114 | return cpp; | |
2115 | } | |
2116 | break; | |
2117 | default: | |
2118 | MISSING_CASE(fb_modifier); | |
2119 | return cpp; | |
2120 | } | |
2121 | } | |
2122 | ||
832be82f VS |
2123 | unsigned int intel_tile_height(const struct drm_i915_private *dev_priv, |
2124 | uint64_t fb_modifier, unsigned int cpp) | |
a57ce0b2 | 2125 | { |
832be82f VS |
2126 | if (fb_modifier == DRM_FORMAT_MOD_NONE) |
2127 | return 1; | |
2128 | else | |
2129 | return intel_tile_size(dev_priv) / | |
27ba3910 | 2130 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
6761dd31 TU |
2131 | } |
2132 | ||
8d0deca8 VS |
2133 | /* Return the tile dimensions in pixel units */ |
2134 | static void intel_tile_dims(const struct drm_i915_private *dev_priv, | |
2135 | unsigned int *tile_width, | |
2136 | unsigned int *tile_height, | |
2137 | uint64_t fb_modifier, | |
2138 | unsigned int cpp) | |
2139 | { | |
2140 | unsigned int tile_width_bytes = | |
2141 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); | |
2142 | ||
2143 | *tile_width = tile_width_bytes / cpp; | |
2144 | *tile_height = intel_tile_size(dev_priv) / tile_width_bytes; | |
2145 | } | |
2146 | ||
6761dd31 TU |
2147 | unsigned int |
2148 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
832be82f | 2149 | uint32_t pixel_format, uint64_t fb_modifier) |
6761dd31 | 2150 | { |
832be82f VS |
2151 | unsigned int cpp = drm_format_plane_cpp(pixel_format, 0); |
2152 | unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp); | |
2153 | ||
2154 | return ALIGN(height, tile_height); | |
a57ce0b2 JB |
2155 | } |
2156 | ||
1663b9d6 VS |
2157 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) |
2158 | { | |
2159 | unsigned int size = 0; | |
2160 | int i; | |
2161 | ||
2162 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) | |
2163 | size += rot_info->plane[i].width * rot_info->plane[i].height; | |
2164 | ||
2165 | return size; | |
2166 | } | |
2167 | ||
75c82a53 | 2168 | static void |
3465c580 VS |
2169 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, |
2170 | const struct drm_framebuffer *fb, | |
2171 | unsigned int rotation) | |
f64b98cd | 2172 | { |
2d7a215f VS |
2173 | if (intel_rotation_90_or_270(rotation)) { |
2174 | *view = i915_ggtt_view_rotated; | |
2175 | view->params.rotated = to_intel_framebuffer(fb)->rot_info; | |
2176 | } else { | |
2177 | *view = i915_ggtt_view_normal; | |
2178 | } | |
2179 | } | |
50470bb0 | 2180 | |
2d7a215f VS |
2181 | static void |
2182 | intel_fill_fb_info(struct drm_i915_private *dev_priv, | |
2183 | struct drm_framebuffer *fb) | |
2184 | { | |
2185 | struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info; | |
2186 | unsigned int tile_size, tile_width, tile_height, cpp; | |
50470bb0 | 2187 | |
d9b3288e VS |
2188 | tile_size = intel_tile_size(dev_priv); |
2189 | ||
2190 | cpp = drm_format_plane_cpp(fb->pixel_format, 0); | |
8d0deca8 VS |
2191 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2192 | fb->modifier[0], cpp); | |
d9b3288e | 2193 | |
1663b9d6 VS |
2194 | info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp); |
2195 | info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height); | |
84fe03f7 | 2196 | |
89e3e142 | 2197 | if (info->pixel_format == DRM_FORMAT_NV12) { |
832be82f | 2198 | cpp = drm_format_plane_cpp(fb->pixel_format, 1); |
8d0deca8 VS |
2199 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2200 | fb->modifier[1], cpp); | |
d9b3288e | 2201 | |
2d7a215f | 2202 | info->uv_offset = fb->offsets[1]; |
1663b9d6 VS |
2203 | info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp); |
2204 | info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height); | |
89e3e142 | 2205 | } |
f64b98cd TU |
2206 | } |
2207 | ||
603525d7 | 2208 | static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) |
4e9a86b6 VS |
2209 | { |
2210 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2211 | return 256 * 1024; | |
985b8bb4 | 2212 | else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || |
666a4537 | 2213 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
4e9a86b6 VS |
2214 | return 128 * 1024; |
2215 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2216 | return 4 * 1024; | |
2217 | else | |
44c5905e | 2218 | return 0; |
4e9a86b6 VS |
2219 | } |
2220 | ||
603525d7 VS |
2221 | static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv, |
2222 | uint64_t fb_modifier) | |
2223 | { | |
2224 | switch (fb_modifier) { | |
2225 | case DRM_FORMAT_MOD_NONE: | |
2226 | return intel_linear_alignment(dev_priv); | |
2227 | case I915_FORMAT_MOD_X_TILED: | |
2228 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2229 | return 256 * 1024; | |
2230 | return 0; | |
2231 | case I915_FORMAT_MOD_Y_TILED: | |
2232 | case I915_FORMAT_MOD_Yf_TILED: | |
2233 | return 1 * 1024 * 1024; | |
2234 | default: | |
2235 | MISSING_CASE(fb_modifier); | |
2236 | return 0; | |
2237 | } | |
2238 | } | |
2239 | ||
127bd2ac | 2240 | int |
3465c580 VS |
2241 | intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, |
2242 | unsigned int rotation) | |
6b95a207 | 2243 | { |
850c4cdc | 2244 | struct drm_device *dev = fb->dev; |
ce453d81 | 2245 | struct drm_i915_private *dev_priv = dev->dev_private; |
850c4cdc | 2246 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2247 | struct i915_ggtt_view view; |
6b95a207 KH |
2248 | u32 alignment; |
2249 | int ret; | |
2250 | ||
ebcdd39e MR |
2251 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2252 | ||
603525d7 | 2253 | alignment = intel_surf_alignment(dev_priv, fb->modifier[0]); |
6b95a207 | 2254 | |
3465c580 | 2255 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2256 | |
693db184 CW |
2257 | /* Note that the w/a also requires 64 PTE of padding following the |
2258 | * bo. We currently fill all unused PTE with the shadow page and so | |
2259 | * we should always have valid PTE following the scanout preventing | |
2260 | * the VT-d warning. | |
2261 | */ | |
2262 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2263 | alignment = 256 * 1024; | |
2264 | ||
d6dd6843 PZ |
2265 | /* |
2266 | * Global gtt pte registers are special registers which actually forward | |
2267 | * writes to a chunk of system memory. Which means that there is no risk | |
2268 | * that the register values disappear as soon as we call | |
2269 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2270 | * pin/unpin/fence and not more. | |
2271 | */ | |
2272 | intel_runtime_pm_get(dev_priv); | |
2273 | ||
7580d774 ML |
2274 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, |
2275 | &view); | |
48b956c5 | 2276 | if (ret) |
b26a6b35 | 2277 | goto err_pm; |
6b95a207 KH |
2278 | |
2279 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2280 | * fence, whereas 965+ only requires a fence if using | |
2281 | * framebuffer compression. For simplicity, we always install | |
2282 | * a fence as the cost is not that onerous. | |
2283 | */ | |
9807216f VK |
2284 | if (view.type == I915_GGTT_VIEW_NORMAL) { |
2285 | ret = i915_gem_object_get_fence(obj); | |
2286 | if (ret == -EDEADLK) { | |
2287 | /* | |
2288 | * -EDEADLK means there are no free fences | |
2289 | * no pending flips. | |
2290 | * | |
2291 | * This is propagated to atomic, but it uses | |
2292 | * -EDEADLK to force a locking recovery, so | |
2293 | * change the returned error to -EBUSY. | |
2294 | */ | |
2295 | ret = -EBUSY; | |
2296 | goto err_unpin; | |
2297 | } else if (ret) | |
2298 | goto err_unpin; | |
1690e1eb | 2299 | |
9807216f VK |
2300 | i915_gem_object_pin_fence(obj); |
2301 | } | |
6b95a207 | 2302 | |
d6dd6843 | 2303 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2304 | return 0; |
48b956c5 CW |
2305 | |
2306 | err_unpin: | |
f64b98cd | 2307 | i915_gem_object_unpin_from_display_plane(obj, &view); |
b26a6b35 | 2308 | err_pm: |
d6dd6843 | 2309 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2310 | return ret; |
6b95a207 KH |
2311 | } |
2312 | ||
3465c580 | 2313 | static void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) |
1690e1eb | 2314 | { |
82bc3b2d | 2315 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2316 | struct i915_ggtt_view view; |
82bc3b2d | 2317 | |
ebcdd39e MR |
2318 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2319 | ||
3465c580 | 2320 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2321 | |
9807216f VK |
2322 | if (view.type == I915_GGTT_VIEW_NORMAL) |
2323 | i915_gem_object_unpin_fence(obj); | |
2324 | ||
f64b98cd | 2325 | i915_gem_object_unpin_from_display_plane(obj, &view); |
1690e1eb CW |
2326 | } |
2327 | ||
29cf9491 VS |
2328 | /* |
2329 | * Adjust the tile offset by moving the difference into | |
2330 | * the x/y offsets. | |
2331 | * | |
2332 | * Input tile dimensions and pitch must already be | |
2333 | * rotated to match x and y, and in pixel units. | |
2334 | */ | |
2335 | static u32 intel_adjust_tile_offset(int *x, int *y, | |
2336 | unsigned int tile_width, | |
2337 | unsigned int tile_height, | |
2338 | unsigned int tile_size, | |
2339 | unsigned int pitch_tiles, | |
2340 | u32 old_offset, | |
2341 | u32 new_offset) | |
2342 | { | |
2343 | unsigned int tiles; | |
2344 | ||
2345 | WARN_ON(old_offset & (tile_size - 1)); | |
2346 | WARN_ON(new_offset & (tile_size - 1)); | |
2347 | WARN_ON(new_offset > old_offset); | |
2348 | ||
2349 | tiles = (old_offset - new_offset) / tile_size; | |
2350 | ||
2351 | *y += tiles / pitch_tiles * tile_height; | |
2352 | *x += tiles % pitch_tiles * tile_width; | |
2353 | ||
2354 | return new_offset; | |
2355 | } | |
2356 | ||
8d0deca8 VS |
2357 | /* |
2358 | * Computes the linear offset to the base tile and adjusts | |
2359 | * x, y. bytes per pixel is assumed to be a power-of-two. | |
2360 | * | |
2361 | * In the 90/270 rotated case, x and y are assumed | |
2362 | * to be already rotated to match the rotated GTT view, and | |
2363 | * pitch is the tile_height aligned framebuffer height. | |
2364 | */ | |
4f2d9934 VS |
2365 | u32 intel_compute_tile_offset(int *x, int *y, |
2366 | const struct drm_framebuffer *fb, int plane, | |
8d0deca8 VS |
2367 | unsigned int pitch, |
2368 | unsigned int rotation) | |
c2c75131 | 2369 | { |
4f2d9934 VS |
2370 | const struct drm_i915_private *dev_priv = to_i915(fb->dev); |
2371 | uint64_t fb_modifier = fb->modifier[plane]; | |
2372 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); | |
29cf9491 VS |
2373 | u32 offset, offset_aligned, alignment; |
2374 | ||
2375 | alignment = intel_surf_alignment(dev_priv, fb_modifier); | |
2376 | if (alignment) | |
2377 | alignment--; | |
2378 | ||
b5c65338 | 2379 | if (fb_modifier != DRM_FORMAT_MOD_NONE) { |
8d0deca8 VS |
2380 | unsigned int tile_size, tile_width, tile_height; |
2381 | unsigned int tile_rows, tiles, pitch_tiles; | |
c2c75131 | 2382 | |
d843310d | 2383 | tile_size = intel_tile_size(dev_priv); |
8d0deca8 VS |
2384 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2385 | fb_modifier, cpp); | |
2386 | ||
2387 | if (intel_rotation_90_or_270(rotation)) { | |
2388 | pitch_tiles = pitch / tile_height; | |
2389 | swap(tile_width, tile_height); | |
2390 | } else { | |
2391 | pitch_tiles = pitch / (tile_width * cpp); | |
2392 | } | |
d843310d VS |
2393 | |
2394 | tile_rows = *y / tile_height; | |
2395 | *y %= tile_height; | |
c2c75131 | 2396 | |
8d0deca8 VS |
2397 | tiles = *x / tile_width; |
2398 | *x %= tile_width; | |
bc752862 | 2399 | |
29cf9491 VS |
2400 | offset = (tile_rows * pitch_tiles + tiles) * tile_size; |
2401 | offset_aligned = offset & ~alignment; | |
bc752862 | 2402 | |
29cf9491 VS |
2403 | intel_adjust_tile_offset(x, y, tile_width, tile_height, |
2404 | tile_size, pitch_tiles, | |
2405 | offset, offset_aligned); | |
2406 | } else { | |
bc752862 | 2407 | offset = *y * pitch + *x * cpp; |
29cf9491 VS |
2408 | offset_aligned = offset & ~alignment; |
2409 | ||
4e9a86b6 VS |
2410 | *y = (offset & alignment) / pitch; |
2411 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
bc752862 | 2412 | } |
29cf9491 VS |
2413 | |
2414 | return offset_aligned; | |
c2c75131 DV |
2415 | } |
2416 | ||
b35d63fa | 2417 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2418 | { |
2419 | switch (format) { | |
2420 | case DISPPLANE_8BPP: | |
2421 | return DRM_FORMAT_C8; | |
2422 | case DISPPLANE_BGRX555: | |
2423 | return DRM_FORMAT_XRGB1555; | |
2424 | case DISPPLANE_BGRX565: | |
2425 | return DRM_FORMAT_RGB565; | |
2426 | default: | |
2427 | case DISPPLANE_BGRX888: | |
2428 | return DRM_FORMAT_XRGB8888; | |
2429 | case DISPPLANE_RGBX888: | |
2430 | return DRM_FORMAT_XBGR8888; | |
2431 | case DISPPLANE_BGRX101010: | |
2432 | return DRM_FORMAT_XRGB2101010; | |
2433 | case DISPPLANE_RGBX101010: | |
2434 | return DRM_FORMAT_XBGR2101010; | |
2435 | } | |
2436 | } | |
2437 | ||
bc8d7dff DL |
2438 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2439 | { | |
2440 | switch (format) { | |
2441 | case PLANE_CTL_FORMAT_RGB_565: | |
2442 | return DRM_FORMAT_RGB565; | |
2443 | default: | |
2444 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2445 | if (rgb_order) { | |
2446 | if (alpha) | |
2447 | return DRM_FORMAT_ABGR8888; | |
2448 | else | |
2449 | return DRM_FORMAT_XBGR8888; | |
2450 | } else { | |
2451 | if (alpha) | |
2452 | return DRM_FORMAT_ARGB8888; | |
2453 | else | |
2454 | return DRM_FORMAT_XRGB8888; | |
2455 | } | |
2456 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2457 | if (rgb_order) | |
2458 | return DRM_FORMAT_XBGR2101010; | |
2459 | else | |
2460 | return DRM_FORMAT_XRGB2101010; | |
2461 | } | |
2462 | } | |
2463 | ||
5724dbd1 | 2464 | static bool |
f6936e29 DV |
2465 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2466 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2467 | { |
2468 | struct drm_device *dev = crtc->base.dev; | |
3badb49f | 2469 | struct drm_i915_private *dev_priv = to_i915(dev); |
46f297fb JB |
2470 | struct drm_i915_gem_object *obj = NULL; |
2471 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2472 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2473 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2474 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2475 | PAGE_SIZE); | |
2476 | ||
2477 | size_aligned -= base_aligned; | |
46f297fb | 2478 | |
ff2652ea CW |
2479 | if (plane_config->size == 0) |
2480 | return false; | |
2481 | ||
3badb49f PZ |
2482 | /* If the FB is too big, just don't use it since fbdev is not very |
2483 | * important and we should probably use that space with FBC or other | |
2484 | * features. */ | |
62106b4f | 2485 | if (size_aligned * 2 > dev_priv->ggtt.stolen_usable_size) |
3badb49f PZ |
2486 | return false; |
2487 | ||
12c83d99 TU |
2488 | mutex_lock(&dev->struct_mutex); |
2489 | ||
f37b5c2b DV |
2490 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2491 | base_aligned, | |
2492 | base_aligned, | |
2493 | size_aligned); | |
12c83d99 TU |
2494 | if (!obj) { |
2495 | mutex_unlock(&dev->struct_mutex); | |
484b41dd | 2496 | return false; |
12c83d99 | 2497 | } |
46f297fb | 2498 | |
49af449b DL |
2499 | obj->tiling_mode = plane_config->tiling; |
2500 | if (obj->tiling_mode == I915_TILING_X) | |
6bf129df | 2501 | obj->stride = fb->pitches[0]; |
46f297fb | 2502 | |
6bf129df DL |
2503 | mode_cmd.pixel_format = fb->pixel_format; |
2504 | mode_cmd.width = fb->width; | |
2505 | mode_cmd.height = fb->height; | |
2506 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2507 | mode_cmd.modifier[0] = fb->modifier[0]; |
2508 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb | 2509 | |
6bf129df | 2510 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2511 | &mode_cmd, obj)) { |
46f297fb JB |
2512 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2513 | goto out_unref_obj; | |
2514 | } | |
12c83d99 | 2515 | |
46f297fb | 2516 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2517 | |
f6936e29 | 2518 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2519 | return true; |
46f297fb JB |
2520 | |
2521 | out_unref_obj: | |
2522 | drm_gem_object_unreference(&obj->base); | |
2523 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2524 | return false; |
2525 | } | |
2526 | ||
afd65eb4 MR |
2527 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2528 | static void | |
2529 | update_state_fb(struct drm_plane *plane) | |
2530 | { | |
2531 | if (plane->fb == plane->state->fb) | |
2532 | return; | |
2533 | ||
2534 | if (plane->state->fb) | |
2535 | drm_framebuffer_unreference(plane->state->fb); | |
2536 | plane->state->fb = plane->fb; | |
2537 | if (plane->state->fb) | |
2538 | drm_framebuffer_reference(plane->state->fb); | |
2539 | } | |
2540 | ||
5724dbd1 | 2541 | static void |
f6936e29 DV |
2542 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2543 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2544 | { |
2545 | struct drm_device *dev = intel_crtc->base.dev; | |
d9ceb816 | 2546 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd JB |
2547 | struct drm_crtc *c; |
2548 | struct intel_crtc *i; | |
2ff8fde1 | 2549 | struct drm_i915_gem_object *obj; |
88595ac9 | 2550 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2551 | struct drm_plane_state *plane_state = primary->state; |
200757f5 MR |
2552 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
2553 | struct intel_plane *intel_plane = to_intel_plane(primary); | |
0a8d8a86 MR |
2554 | struct intel_plane_state *intel_state = |
2555 | to_intel_plane_state(plane_state); | |
88595ac9 | 2556 | struct drm_framebuffer *fb; |
484b41dd | 2557 | |
2d14030b | 2558 | if (!plane_config->fb) |
484b41dd JB |
2559 | return; |
2560 | ||
f6936e29 | 2561 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2562 | fb = &plane_config->fb->base; |
2563 | goto valid_fb; | |
f55548b5 | 2564 | } |
484b41dd | 2565 | |
2d14030b | 2566 | kfree(plane_config->fb); |
484b41dd JB |
2567 | |
2568 | /* | |
2569 | * Failed to alloc the obj, check to see if we should share | |
2570 | * an fb with another CRTC instead | |
2571 | */ | |
70e1e0ec | 2572 | for_each_crtc(dev, c) { |
484b41dd JB |
2573 | i = to_intel_crtc(c); |
2574 | ||
2575 | if (c == &intel_crtc->base) | |
2576 | continue; | |
2577 | ||
2ff8fde1 MR |
2578 | if (!i->active) |
2579 | continue; | |
2580 | ||
88595ac9 DV |
2581 | fb = c->primary->fb; |
2582 | if (!fb) | |
484b41dd JB |
2583 | continue; |
2584 | ||
88595ac9 | 2585 | obj = intel_fb_obj(fb); |
2ff8fde1 | 2586 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
88595ac9 DV |
2587 | drm_framebuffer_reference(fb); |
2588 | goto valid_fb; | |
484b41dd JB |
2589 | } |
2590 | } | |
88595ac9 | 2591 | |
200757f5 MR |
2592 | /* |
2593 | * We've failed to reconstruct the BIOS FB. Current display state | |
2594 | * indicates that the primary plane is visible, but has a NULL FB, | |
2595 | * which will lead to problems later if we don't fix it up. The | |
2596 | * simplest solution is to just disable the primary plane now and | |
2597 | * pretend the BIOS never had it enabled. | |
2598 | */ | |
2599 | to_intel_plane_state(plane_state)->visible = false; | |
2600 | crtc_state->plane_mask &= ~(1 << drm_plane_index(primary)); | |
2622a081 | 2601 | intel_pre_disable_primary_noatomic(&intel_crtc->base); |
200757f5 MR |
2602 | intel_plane->disable_plane(primary, &intel_crtc->base); |
2603 | ||
88595ac9 DV |
2604 | return; |
2605 | ||
2606 | valid_fb: | |
f44e2659 VS |
2607 | plane_state->src_x = 0; |
2608 | plane_state->src_y = 0; | |
be5651f2 ML |
2609 | plane_state->src_w = fb->width << 16; |
2610 | plane_state->src_h = fb->height << 16; | |
2611 | ||
f44e2659 VS |
2612 | plane_state->crtc_x = 0; |
2613 | plane_state->crtc_y = 0; | |
be5651f2 ML |
2614 | plane_state->crtc_w = fb->width; |
2615 | plane_state->crtc_h = fb->height; | |
2616 | ||
0a8d8a86 MR |
2617 | intel_state->src.x1 = plane_state->src_x; |
2618 | intel_state->src.y1 = plane_state->src_y; | |
2619 | intel_state->src.x2 = plane_state->src_x + plane_state->src_w; | |
2620 | intel_state->src.y2 = plane_state->src_y + plane_state->src_h; | |
2621 | intel_state->dst.x1 = plane_state->crtc_x; | |
2622 | intel_state->dst.y1 = plane_state->crtc_y; | |
2623 | intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w; | |
2624 | intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h; | |
2625 | ||
88595ac9 DV |
2626 | obj = intel_fb_obj(fb); |
2627 | if (obj->tiling_mode != I915_TILING_NONE) | |
2628 | dev_priv->preserve_bios_swizzle = true; | |
2629 | ||
be5651f2 ML |
2630 | drm_framebuffer_reference(fb); |
2631 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2632 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
36750f28 | 2633 | intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); |
a9ff8714 | 2634 | obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit; |
46f297fb JB |
2635 | } |
2636 | ||
a8d201af ML |
2637 | static void i9xx_update_primary_plane(struct drm_plane *primary, |
2638 | const struct intel_crtc_state *crtc_state, | |
2639 | const struct intel_plane_state *plane_state) | |
81255565 | 2640 | { |
a8d201af | 2641 | struct drm_device *dev = primary->dev; |
81255565 | 2642 | struct drm_i915_private *dev_priv = dev->dev_private; |
a8d201af ML |
2643 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
2644 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2645 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
81255565 | 2646 | int plane = intel_crtc->plane; |
54ea9da8 | 2647 | u32 linear_offset; |
81255565 | 2648 | u32 dspcntr; |
f0f59a00 | 2649 | i915_reg_t reg = DSPCNTR(plane); |
8d0deca8 | 2650 | unsigned int rotation = plane_state->base.rotation; |
ac484963 | 2651 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
54ea9da8 VS |
2652 | int x = plane_state->src.x1 >> 16; |
2653 | int y = plane_state->src.y1 >> 16; | |
c9ba6fad | 2654 | |
f45651ba VS |
2655 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2656 | ||
fdd508a6 | 2657 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2658 | |
2659 | if (INTEL_INFO(dev)->gen < 4) { | |
2660 | if (intel_crtc->pipe == PIPE_B) | |
2661 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2662 | ||
2663 | /* pipesrc and dspsize control the size that is scaled from, | |
2664 | * which should always be the user's requested size. | |
2665 | */ | |
2666 | I915_WRITE(DSPSIZE(plane), | |
a8d201af ML |
2667 | ((crtc_state->pipe_src_h - 1) << 16) | |
2668 | (crtc_state->pipe_src_w - 1)); | |
f45651ba | 2669 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
2670 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2671 | I915_WRITE(PRIMSIZE(plane), | |
a8d201af ML |
2672 | ((crtc_state->pipe_src_h - 1) << 16) | |
2673 | (crtc_state->pipe_src_w - 1)); | |
c14b0485 VS |
2674 | I915_WRITE(PRIMPOS(plane), 0); |
2675 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2676 | } |
81255565 | 2677 | |
57779d06 VS |
2678 | switch (fb->pixel_format) { |
2679 | case DRM_FORMAT_C8: | |
81255565 JB |
2680 | dspcntr |= DISPPLANE_8BPP; |
2681 | break; | |
57779d06 | 2682 | case DRM_FORMAT_XRGB1555: |
57779d06 | 2683 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 2684 | break; |
57779d06 VS |
2685 | case DRM_FORMAT_RGB565: |
2686 | dspcntr |= DISPPLANE_BGRX565; | |
2687 | break; | |
2688 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
2689 | dspcntr |= DISPPLANE_BGRX888; |
2690 | break; | |
2691 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2692 | dspcntr |= DISPPLANE_RGBX888; |
2693 | break; | |
2694 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2695 | dspcntr |= DISPPLANE_BGRX101010; |
2696 | break; | |
2697 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2698 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
2699 | break; |
2700 | default: | |
baba133a | 2701 | BUG(); |
81255565 | 2702 | } |
57779d06 | 2703 | |
f45651ba VS |
2704 | if (INTEL_INFO(dev)->gen >= 4 && |
2705 | obj->tiling_mode != I915_TILING_NONE) | |
2706 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2707 | |
de1aa629 VS |
2708 | if (IS_G4X(dev)) |
2709 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2710 | ||
ac484963 | 2711 | linear_offset = y * fb->pitches[0] + x * cpp; |
81255565 | 2712 | |
c2c75131 DV |
2713 | if (INTEL_INFO(dev)->gen >= 4) { |
2714 | intel_crtc->dspaddr_offset = | |
4f2d9934 | 2715 | intel_compute_tile_offset(&x, &y, fb, 0, |
8d0deca8 | 2716 | fb->pitches[0], rotation); |
c2c75131 DV |
2717 | linear_offset -= intel_crtc->dspaddr_offset; |
2718 | } else { | |
e506a0c6 | 2719 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2720 | } |
e506a0c6 | 2721 | |
8d0deca8 | 2722 | if (rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2723 | dspcntr |= DISPPLANE_ROTATE_180; |
2724 | ||
a8d201af ML |
2725 | x += (crtc_state->pipe_src_w - 1); |
2726 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
2727 | |
2728 | /* Finding the last pixel of the last line of the display | |
2729 | data and adding to linear_offset*/ | |
2730 | linear_offset += | |
a8d201af | 2731 | (crtc_state->pipe_src_h - 1) * fb->pitches[0] + |
ac484963 | 2732 | (crtc_state->pipe_src_w - 1) * cpp; |
48404c1e SJ |
2733 | } |
2734 | ||
2db3366b PZ |
2735 | intel_crtc->adjusted_x = x; |
2736 | intel_crtc->adjusted_y = y; | |
2737 | ||
48404c1e SJ |
2738 | I915_WRITE(reg, dspcntr); |
2739 | ||
01f2c773 | 2740 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2741 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2742 | I915_WRITE(DSPSURF(plane), |
2743 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2744 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2745 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2746 | } else |
f343c5f6 | 2747 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2748 | POSTING_READ(reg); |
17638cd6 JB |
2749 | } |
2750 | ||
a8d201af ML |
2751 | static void i9xx_disable_primary_plane(struct drm_plane *primary, |
2752 | struct drm_crtc *crtc) | |
17638cd6 JB |
2753 | { |
2754 | struct drm_device *dev = crtc->dev; | |
2755 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2756 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
17638cd6 | 2757 | int plane = intel_crtc->plane; |
f45651ba | 2758 | |
a8d201af ML |
2759 | I915_WRITE(DSPCNTR(plane), 0); |
2760 | if (INTEL_INFO(dev_priv)->gen >= 4) | |
fdd508a6 | 2761 | I915_WRITE(DSPSURF(plane), 0); |
a8d201af ML |
2762 | else |
2763 | I915_WRITE(DSPADDR(plane), 0); | |
2764 | POSTING_READ(DSPCNTR(plane)); | |
2765 | } | |
c9ba6fad | 2766 | |
a8d201af ML |
2767 | static void ironlake_update_primary_plane(struct drm_plane *primary, |
2768 | const struct intel_crtc_state *crtc_state, | |
2769 | const struct intel_plane_state *plane_state) | |
2770 | { | |
2771 | struct drm_device *dev = primary->dev; | |
2772 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2773 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
2774 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2775 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
2776 | int plane = intel_crtc->plane; | |
54ea9da8 | 2777 | u32 linear_offset; |
a8d201af ML |
2778 | u32 dspcntr; |
2779 | i915_reg_t reg = DSPCNTR(plane); | |
8d0deca8 | 2780 | unsigned int rotation = plane_state->base.rotation; |
ac484963 | 2781 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
a8d201af ML |
2782 | int x = plane_state->src.x1 >> 16; |
2783 | int y = plane_state->src.y1 >> 16; | |
c9ba6fad | 2784 | |
f45651ba | 2785 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
fdd508a6 | 2786 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2787 | |
2788 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2789 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2790 | |
57779d06 VS |
2791 | switch (fb->pixel_format) { |
2792 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2793 | dspcntr |= DISPPLANE_8BPP; |
2794 | break; | |
57779d06 VS |
2795 | case DRM_FORMAT_RGB565: |
2796 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2797 | break; |
57779d06 | 2798 | case DRM_FORMAT_XRGB8888: |
57779d06 VS |
2799 | dspcntr |= DISPPLANE_BGRX888; |
2800 | break; | |
2801 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2802 | dspcntr |= DISPPLANE_RGBX888; |
2803 | break; | |
2804 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2805 | dspcntr |= DISPPLANE_BGRX101010; |
2806 | break; | |
2807 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2808 | dspcntr |= DISPPLANE_RGBX101010; |
17638cd6 JB |
2809 | break; |
2810 | default: | |
baba133a | 2811 | BUG(); |
17638cd6 JB |
2812 | } |
2813 | ||
2814 | if (obj->tiling_mode != I915_TILING_NONE) | |
2815 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2816 | |
f45651ba | 2817 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2818 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2819 | |
ac484963 | 2820 | linear_offset = y * fb->pitches[0] + x * cpp; |
c2c75131 | 2821 | intel_crtc->dspaddr_offset = |
4f2d9934 | 2822 | intel_compute_tile_offset(&x, &y, fb, 0, |
8d0deca8 | 2823 | fb->pitches[0], rotation); |
c2c75131 | 2824 | linear_offset -= intel_crtc->dspaddr_offset; |
8d0deca8 | 2825 | if (rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2826 | dspcntr |= DISPPLANE_ROTATE_180; |
2827 | ||
2828 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
a8d201af ML |
2829 | x += (crtc_state->pipe_src_w - 1); |
2830 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
2831 | |
2832 | /* Finding the last pixel of the last line of the display | |
2833 | data and adding to linear_offset*/ | |
2834 | linear_offset += | |
a8d201af | 2835 | (crtc_state->pipe_src_h - 1) * fb->pitches[0] + |
ac484963 | 2836 | (crtc_state->pipe_src_w - 1) * cpp; |
48404c1e SJ |
2837 | } |
2838 | } | |
2839 | ||
2db3366b PZ |
2840 | intel_crtc->adjusted_x = x; |
2841 | intel_crtc->adjusted_y = y; | |
2842 | ||
48404c1e | 2843 | I915_WRITE(reg, dspcntr); |
17638cd6 | 2844 | |
01f2c773 | 2845 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2846 | I915_WRITE(DSPSURF(plane), |
2847 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2848 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2849 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2850 | } else { | |
2851 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2852 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2853 | } | |
17638cd6 | 2854 | POSTING_READ(reg); |
17638cd6 JB |
2855 | } |
2856 | ||
7b49f948 VS |
2857 | u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv, |
2858 | uint64_t fb_modifier, uint32_t pixel_format) | |
b321803d | 2859 | { |
7b49f948 | 2860 | if (fb_modifier == DRM_FORMAT_MOD_NONE) { |
b321803d | 2861 | return 64; |
7b49f948 VS |
2862 | } else { |
2863 | int cpp = drm_format_plane_cpp(pixel_format, 0); | |
2864 | ||
27ba3910 | 2865 | return intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
b321803d DL |
2866 | } |
2867 | } | |
2868 | ||
44eb0cb9 MK |
2869 | u32 intel_plane_obj_offset(struct intel_plane *intel_plane, |
2870 | struct drm_i915_gem_object *obj, | |
2871 | unsigned int plane) | |
121920fa | 2872 | { |
ce7f1728 | 2873 | struct i915_ggtt_view view; |
dedf278c | 2874 | struct i915_vma *vma; |
44eb0cb9 | 2875 | u64 offset; |
121920fa | 2876 | |
e7941294 | 2877 | intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb, |
3465c580 | 2878 | intel_plane->base.state->rotation); |
121920fa | 2879 | |
ce7f1728 | 2880 | vma = i915_gem_obj_to_ggtt_view(obj, &view); |
dedf278c | 2881 | if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n", |
ce7f1728 | 2882 | view.type)) |
dedf278c TU |
2883 | return -1; |
2884 | ||
44eb0cb9 | 2885 | offset = vma->node.start; |
dedf278c TU |
2886 | |
2887 | if (plane == 1) { | |
7723f47d | 2888 | offset += vma->ggtt_view.params.rotated.uv_start_page * |
dedf278c TU |
2889 | PAGE_SIZE; |
2890 | } | |
2891 | ||
44eb0cb9 MK |
2892 | WARN_ON(upper_32_bits(offset)); |
2893 | ||
2894 | return lower_32_bits(offset); | |
121920fa TU |
2895 | } |
2896 | ||
e435d6e5 ML |
2897 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
2898 | { | |
2899 | struct drm_device *dev = intel_crtc->base.dev; | |
2900 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2901 | ||
2902 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
2903 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
2904 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
2905 | } |
2906 | ||
a1b2278e CK |
2907 | /* |
2908 | * This function detaches (aka. unbinds) unused scalers in hardware | |
2909 | */ | |
0583236e | 2910 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 2911 | { |
a1b2278e CK |
2912 | struct intel_crtc_scaler_state *scaler_state; |
2913 | int i; | |
2914 | ||
a1b2278e CK |
2915 | scaler_state = &intel_crtc->config->scaler_state; |
2916 | ||
2917 | /* loop through and disable scalers that aren't in use */ | |
2918 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
2919 | if (!scaler_state->scalers[i].in_use) |
2920 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
2921 | } |
2922 | } | |
2923 | ||
6156a456 | 2924 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 2925 | { |
6156a456 | 2926 | switch (pixel_format) { |
d161cf7a | 2927 | case DRM_FORMAT_C8: |
c34ce3d1 | 2928 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 2929 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 2930 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 2931 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 2932 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 2933 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 2934 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
2935 | /* |
2936 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
2937 | * to be already pre-multiplied. We need to add a knob (or a different | |
2938 | * DRM_FORMAT) for user-space to configure that. | |
2939 | */ | |
f75fb42a | 2940 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 2941 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 2942 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 2943 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 2944 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 2945 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 2946 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 2947 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 2948 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 2949 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 2950 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 2951 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 2952 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 2953 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 2954 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 2955 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 2956 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 2957 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 2958 | default: |
4249eeef | 2959 | MISSING_CASE(pixel_format); |
70d21f0e | 2960 | } |
8cfcba41 | 2961 | |
c34ce3d1 | 2962 | return 0; |
6156a456 | 2963 | } |
70d21f0e | 2964 | |
6156a456 CK |
2965 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
2966 | { | |
6156a456 | 2967 | switch (fb_modifier) { |
30af77c4 | 2968 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 2969 | break; |
30af77c4 | 2970 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 2971 | return PLANE_CTL_TILED_X; |
b321803d | 2972 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 2973 | return PLANE_CTL_TILED_Y; |
b321803d | 2974 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 2975 | return PLANE_CTL_TILED_YF; |
70d21f0e | 2976 | default: |
6156a456 | 2977 | MISSING_CASE(fb_modifier); |
70d21f0e | 2978 | } |
8cfcba41 | 2979 | |
c34ce3d1 | 2980 | return 0; |
6156a456 | 2981 | } |
70d21f0e | 2982 | |
6156a456 CK |
2983 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
2984 | { | |
3b7a5119 | 2985 | switch (rotation) { |
6156a456 CK |
2986 | case BIT(DRM_ROTATE_0): |
2987 | break; | |
1e8df167 SJ |
2988 | /* |
2989 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
2990 | * while i915 HW rotation is clockwise, thats why this swapping. | |
2991 | */ | |
3b7a5119 | 2992 | case BIT(DRM_ROTATE_90): |
1e8df167 | 2993 | return PLANE_CTL_ROTATE_270; |
3b7a5119 | 2994 | case BIT(DRM_ROTATE_180): |
c34ce3d1 | 2995 | return PLANE_CTL_ROTATE_180; |
3b7a5119 | 2996 | case BIT(DRM_ROTATE_270): |
1e8df167 | 2997 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
2998 | default: |
2999 | MISSING_CASE(rotation); | |
3000 | } | |
3001 | ||
c34ce3d1 | 3002 | return 0; |
6156a456 CK |
3003 | } |
3004 | ||
a8d201af ML |
3005 | static void skylake_update_primary_plane(struct drm_plane *plane, |
3006 | const struct intel_crtc_state *crtc_state, | |
3007 | const struct intel_plane_state *plane_state) | |
6156a456 | 3008 | { |
a8d201af | 3009 | struct drm_device *dev = plane->dev; |
6156a456 | 3010 | struct drm_i915_private *dev_priv = dev->dev_private; |
a8d201af ML |
3011 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
3012 | struct drm_framebuffer *fb = plane_state->base.fb; | |
3013 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
6156a456 CK |
3014 | int pipe = intel_crtc->pipe; |
3015 | u32 plane_ctl, stride_div, stride; | |
3016 | u32 tile_height, plane_offset, plane_size; | |
a8d201af | 3017 | unsigned int rotation = plane_state->base.rotation; |
6156a456 | 3018 | int x_offset, y_offset; |
44eb0cb9 | 3019 | u32 surf_addr; |
a8d201af ML |
3020 | int scaler_id = plane_state->scaler_id; |
3021 | int src_x = plane_state->src.x1 >> 16; | |
3022 | int src_y = plane_state->src.y1 >> 16; | |
3023 | int src_w = drm_rect_width(&plane_state->src) >> 16; | |
3024 | int src_h = drm_rect_height(&plane_state->src) >> 16; | |
3025 | int dst_x = plane_state->dst.x1; | |
3026 | int dst_y = plane_state->dst.y1; | |
3027 | int dst_w = drm_rect_width(&plane_state->dst); | |
3028 | int dst_h = drm_rect_height(&plane_state->dst); | |
70d21f0e | 3029 | |
6156a456 CK |
3030 | plane_ctl = PLANE_CTL_ENABLE | |
3031 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3032 | PLANE_CTL_PIPE_CSC_ENABLE; | |
3033 | ||
3034 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); | |
3035 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
3036 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
6156a456 CK |
3037 | plane_ctl |= skl_plane_ctl_rotation(rotation); |
3038 | ||
7b49f948 | 3039 | stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
b321803d | 3040 | fb->pixel_format); |
dedf278c | 3041 | surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0); |
3b7a5119 | 3042 | |
a42e5a23 PZ |
3043 | WARN_ON(drm_rect_width(&plane_state->src) == 0); |
3044 | ||
3b7a5119 | 3045 | if (intel_rotation_90_or_270(rotation)) { |
832be82f VS |
3046 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
3047 | ||
3b7a5119 | 3048 | /* stride = Surface height in tiles */ |
832be82f | 3049 | tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp); |
3b7a5119 | 3050 | stride = DIV_ROUND_UP(fb->height, tile_height); |
a8d201af ML |
3051 | x_offset = stride * tile_height - src_y - src_h; |
3052 | y_offset = src_x; | |
6156a456 | 3053 | plane_size = (src_w - 1) << 16 | (src_h - 1); |
3b7a5119 SJ |
3054 | } else { |
3055 | stride = fb->pitches[0] / stride_div; | |
a8d201af ML |
3056 | x_offset = src_x; |
3057 | y_offset = src_y; | |
6156a456 | 3058 | plane_size = (src_h - 1) << 16 | (src_w - 1); |
3b7a5119 SJ |
3059 | } |
3060 | plane_offset = y_offset << 16 | x_offset; | |
b321803d | 3061 | |
2db3366b PZ |
3062 | intel_crtc->adjusted_x = x_offset; |
3063 | intel_crtc->adjusted_y = y_offset; | |
3064 | ||
70d21f0e | 3065 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
3b7a5119 SJ |
3066 | I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); |
3067 | I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); | |
3068 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
6156a456 CK |
3069 | |
3070 | if (scaler_id >= 0) { | |
3071 | uint32_t ps_ctrl = 0; | |
3072 | ||
3073 | WARN_ON(!dst_w || !dst_h); | |
3074 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | | |
3075 | crtc_state->scaler_state.scalers[scaler_id].mode; | |
3076 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3077 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3078 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3079 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3080 | I915_WRITE(PLANE_POS(pipe, 0), 0); | |
3081 | } else { | |
3082 | I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); | |
3083 | } | |
3084 | ||
121920fa | 3085 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
70d21f0e DL |
3086 | |
3087 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3088 | } | |
3089 | ||
a8d201af ML |
3090 | static void skylake_disable_primary_plane(struct drm_plane *primary, |
3091 | struct drm_crtc *crtc) | |
17638cd6 JB |
3092 | { |
3093 | struct drm_device *dev = crtc->dev; | |
3094 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a8d201af | 3095 | int pipe = to_intel_crtc(crtc)->pipe; |
17638cd6 | 3096 | |
a8d201af ML |
3097 | I915_WRITE(PLANE_CTL(pipe, 0), 0); |
3098 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
3099 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3100 | } | |
29b9bde6 | 3101 | |
a8d201af ML |
3102 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3103 | static int | |
3104 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3105 | int x, int y, enum mode_set_atomic state) | |
3106 | { | |
3107 | /* Support for kgdboc is disabled, this needs a major rework. */ | |
3108 | DRM_ERROR("legacy panic handler not supported any more.\n"); | |
3109 | ||
3110 | return -ENODEV; | |
81255565 JB |
3111 | } |
3112 | ||
7514747d | 3113 | static void intel_complete_page_flips(struct drm_device *dev) |
96a02917 | 3114 | { |
96a02917 VS |
3115 | struct drm_crtc *crtc; |
3116 | ||
70e1e0ec | 3117 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3118 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3119 | enum plane plane = intel_crtc->plane; | |
3120 | ||
3121 | intel_prepare_page_flip(dev, plane); | |
3122 | intel_finish_page_flip_plane(dev, plane); | |
3123 | } | |
7514747d VS |
3124 | } |
3125 | ||
3126 | static void intel_update_primary_planes(struct drm_device *dev) | |
3127 | { | |
7514747d | 3128 | struct drm_crtc *crtc; |
96a02917 | 3129 | |
70e1e0ec | 3130 | for_each_crtc(dev, crtc) { |
11c22da6 ML |
3131 | struct intel_plane *plane = to_intel_plane(crtc->primary); |
3132 | struct intel_plane_state *plane_state; | |
96a02917 | 3133 | |
11c22da6 | 3134 | drm_modeset_lock_crtc(crtc, &plane->base); |
11c22da6 ML |
3135 | plane_state = to_intel_plane_state(plane->base.state); |
3136 | ||
a8d201af ML |
3137 | if (plane_state->visible) |
3138 | plane->update_plane(&plane->base, | |
3139 | to_intel_crtc_state(crtc->state), | |
3140 | plane_state); | |
11c22da6 ML |
3141 | |
3142 | drm_modeset_unlock_crtc(crtc); | |
96a02917 VS |
3143 | } |
3144 | } | |
3145 | ||
7514747d VS |
3146 | void intel_prepare_reset(struct drm_device *dev) |
3147 | { | |
3148 | /* no reset support for gen2 */ | |
3149 | if (IS_GEN2(dev)) | |
3150 | return; | |
3151 | ||
3152 | /* reset doesn't touch the display */ | |
3153 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
3154 | return; | |
3155 | ||
3156 | drm_modeset_lock_all(dev); | |
f98ce92f VS |
3157 | /* |
3158 | * Disabling the crtcs gracefully seems nicer. Also the | |
3159 | * g33 docs say we should at least disable all the planes. | |
3160 | */ | |
6b72d486 | 3161 | intel_display_suspend(dev); |
7514747d VS |
3162 | } |
3163 | ||
3164 | void intel_finish_reset(struct drm_device *dev) | |
3165 | { | |
3166 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3167 | ||
3168 | /* | |
3169 | * Flips in the rings will be nuked by the reset, | |
3170 | * so complete all pending flips so that user space | |
3171 | * will get its events and not get stuck. | |
3172 | */ | |
3173 | intel_complete_page_flips(dev); | |
3174 | ||
3175 | /* no reset support for gen2 */ | |
3176 | if (IS_GEN2(dev)) | |
3177 | return; | |
3178 | ||
3179 | /* reset doesn't touch the display */ | |
3180 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { | |
3181 | /* | |
3182 | * Flips in the rings have been nuked by the reset, | |
3183 | * so update the base address of all primary | |
3184 | * planes to the the last fb to make sure we're | |
3185 | * showing the correct fb after a reset. | |
11c22da6 ML |
3186 | * |
3187 | * FIXME: Atomic will make this obsolete since we won't schedule | |
3188 | * CS-based flips (which might get lost in gpu resets) any more. | |
7514747d VS |
3189 | */ |
3190 | intel_update_primary_planes(dev); | |
3191 | return; | |
3192 | } | |
3193 | ||
3194 | /* | |
3195 | * The display has been reset as well, | |
3196 | * so need a full re-initialization. | |
3197 | */ | |
3198 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3199 | intel_runtime_pm_enable_interrupts(dev_priv); | |
3200 | ||
3201 | intel_modeset_init_hw(dev); | |
3202 | ||
3203 | spin_lock_irq(&dev_priv->irq_lock); | |
3204 | if (dev_priv->display.hpd_irq_setup) | |
3205 | dev_priv->display.hpd_irq_setup(dev); | |
3206 | spin_unlock_irq(&dev_priv->irq_lock); | |
3207 | ||
043e9bda | 3208 | intel_display_resume(dev); |
7514747d VS |
3209 | |
3210 | intel_hpd_init(dev_priv); | |
3211 | ||
3212 | drm_modeset_unlock_all(dev); | |
3213 | } | |
3214 | ||
7d5e3799 CW |
3215 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3216 | { | |
3217 | struct drm_device *dev = crtc->dev; | |
3218 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3219 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7d5e3799 CW |
3220 | bool pending; |
3221 | ||
3222 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
3223 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
3224 | return false; | |
3225 | ||
5e2d7afc | 3226 | spin_lock_irq(&dev->event_lock); |
7d5e3799 | 3227 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
5e2d7afc | 3228 | spin_unlock_irq(&dev->event_lock); |
7d5e3799 CW |
3229 | |
3230 | return pending; | |
3231 | } | |
3232 | ||
bfd16b2a ML |
3233 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
3234 | struct intel_crtc_state *old_crtc_state) | |
e30e8f75 GP |
3235 | { |
3236 | struct drm_device *dev = crtc->base.dev; | |
3237 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bfd16b2a ML |
3238 | struct intel_crtc_state *pipe_config = |
3239 | to_intel_crtc_state(crtc->base.state); | |
e30e8f75 | 3240 | |
bfd16b2a ML |
3241 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
3242 | crtc->base.mode = crtc->base.state->mode; | |
3243 | ||
3244 | DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n", | |
3245 | old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h, | |
3246 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
e30e8f75 | 3247 | |
44522d85 | 3248 | if (HAS_DDI(dev)) |
8563b1e8 | 3249 | intel_color_set_csc(&crtc->base); |
44522d85 | 3250 | |
e30e8f75 GP |
3251 | /* |
3252 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3253 | * that in compute_mode_changes we check the native mode (not the pfit | |
3254 | * mode) to see if we can flip rather than do a full mode set. In the | |
3255 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3256 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3257 | * sized surface. | |
e30e8f75 GP |
3258 | */ |
3259 | ||
e30e8f75 | 3260 | I915_WRITE(PIPESRC(crtc->pipe), |
bfd16b2a ML |
3261 | ((pipe_config->pipe_src_w - 1) << 16) | |
3262 | (pipe_config->pipe_src_h - 1)); | |
3263 | ||
3264 | /* on skylake this is done by detaching scalers */ | |
3265 | if (INTEL_INFO(dev)->gen >= 9) { | |
3266 | skl_detach_scalers(crtc); | |
3267 | ||
3268 | if (pipe_config->pch_pfit.enabled) | |
3269 | skylake_pfit_enable(crtc); | |
3270 | } else if (HAS_PCH_SPLIT(dev)) { | |
3271 | if (pipe_config->pch_pfit.enabled) | |
3272 | ironlake_pfit_enable(crtc); | |
3273 | else if (old_crtc_state->pch_pfit.enabled) | |
3274 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3275 | } |
e30e8f75 GP |
3276 | } |
3277 | ||
5e84e1a4 ZW |
3278 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3279 | { | |
3280 | struct drm_device *dev = crtc->dev; | |
3281 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3282 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3283 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3284 | i915_reg_t reg; |
3285 | u32 temp; | |
5e84e1a4 ZW |
3286 | |
3287 | /* enable normal train */ | |
3288 | reg = FDI_TX_CTL(pipe); | |
3289 | temp = I915_READ(reg); | |
61e499bf | 3290 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3291 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3292 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3293 | } else { |
3294 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3295 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3296 | } |
5e84e1a4 ZW |
3297 | I915_WRITE(reg, temp); |
3298 | ||
3299 | reg = FDI_RX_CTL(pipe); | |
3300 | temp = I915_READ(reg); | |
3301 | if (HAS_PCH_CPT(dev)) { | |
3302 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3303 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3304 | } else { | |
3305 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3306 | temp |= FDI_LINK_TRAIN_NONE; | |
3307 | } | |
3308 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3309 | ||
3310 | /* wait one idle pattern time */ | |
3311 | POSTING_READ(reg); | |
3312 | udelay(1000); | |
357555c0 JB |
3313 | |
3314 | /* IVB wants error correction enabled */ | |
3315 | if (IS_IVYBRIDGE(dev)) | |
3316 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3317 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3318 | } |
3319 | ||
8db9d77b ZW |
3320 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3321 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3322 | { | |
3323 | struct drm_device *dev = crtc->dev; | |
3324 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3325 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3326 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3327 | i915_reg_t reg; |
3328 | u32 temp, tries; | |
8db9d77b | 3329 | |
1c8562f6 | 3330 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3331 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3332 | |
e1a44743 AJ |
3333 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3334 | for train result */ | |
5eddb70b CW |
3335 | reg = FDI_RX_IMR(pipe); |
3336 | temp = I915_READ(reg); | |
e1a44743 AJ |
3337 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3338 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3339 | I915_WRITE(reg, temp); |
3340 | I915_READ(reg); | |
e1a44743 AJ |
3341 | udelay(150); |
3342 | ||
8db9d77b | 3343 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3344 | reg = FDI_TX_CTL(pipe); |
3345 | temp = I915_READ(reg); | |
627eb5a3 | 3346 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3347 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3348 | temp &= ~FDI_LINK_TRAIN_NONE; |
3349 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3350 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3351 | |
5eddb70b CW |
3352 | reg = FDI_RX_CTL(pipe); |
3353 | temp = I915_READ(reg); | |
8db9d77b ZW |
3354 | temp &= ~FDI_LINK_TRAIN_NONE; |
3355 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3356 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3357 | ||
3358 | POSTING_READ(reg); | |
8db9d77b ZW |
3359 | udelay(150); |
3360 | ||
5b2adf89 | 3361 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3362 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3363 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3364 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3365 | |
5eddb70b | 3366 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3367 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3368 | temp = I915_READ(reg); |
8db9d77b ZW |
3369 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3370 | ||
3371 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3372 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3373 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3374 | break; |
3375 | } | |
8db9d77b | 3376 | } |
e1a44743 | 3377 | if (tries == 5) |
5eddb70b | 3378 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3379 | |
3380 | /* Train 2 */ | |
5eddb70b CW |
3381 | reg = FDI_TX_CTL(pipe); |
3382 | temp = I915_READ(reg); | |
8db9d77b ZW |
3383 | temp &= ~FDI_LINK_TRAIN_NONE; |
3384 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3385 | I915_WRITE(reg, temp); |
8db9d77b | 3386 | |
5eddb70b CW |
3387 | reg = FDI_RX_CTL(pipe); |
3388 | temp = I915_READ(reg); | |
8db9d77b ZW |
3389 | temp &= ~FDI_LINK_TRAIN_NONE; |
3390 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3391 | I915_WRITE(reg, temp); |
8db9d77b | 3392 | |
5eddb70b CW |
3393 | POSTING_READ(reg); |
3394 | udelay(150); | |
8db9d77b | 3395 | |
5eddb70b | 3396 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3397 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3398 | temp = I915_READ(reg); |
8db9d77b ZW |
3399 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3400 | ||
3401 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3402 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3403 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3404 | break; | |
3405 | } | |
8db9d77b | 3406 | } |
e1a44743 | 3407 | if (tries == 5) |
5eddb70b | 3408 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3409 | |
3410 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3411 | |
8db9d77b ZW |
3412 | } |
3413 | ||
0206e353 | 3414 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3415 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3416 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3417 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3418 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3419 | }; | |
3420 | ||
3421 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3422 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3423 | { | |
3424 | struct drm_device *dev = crtc->dev; | |
3425 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3426 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3427 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3428 | i915_reg_t reg; |
3429 | u32 temp, i, retry; | |
8db9d77b | 3430 | |
e1a44743 AJ |
3431 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3432 | for train result */ | |
5eddb70b CW |
3433 | reg = FDI_RX_IMR(pipe); |
3434 | temp = I915_READ(reg); | |
e1a44743 AJ |
3435 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3436 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3437 | I915_WRITE(reg, temp); |
3438 | ||
3439 | POSTING_READ(reg); | |
e1a44743 AJ |
3440 | udelay(150); |
3441 | ||
8db9d77b | 3442 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3443 | reg = FDI_TX_CTL(pipe); |
3444 | temp = I915_READ(reg); | |
627eb5a3 | 3445 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3446 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3447 | temp &= ~FDI_LINK_TRAIN_NONE; |
3448 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3449 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3450 | /* SNB-B */ | |
3451 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3452 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3453 | |
d74cf324 DV |
3454 | I915_WRITE(FDI_RX_MISC(pipe), |
3455 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3456 | ||
5eddb70b CW |
3457 | reg = FDI_RX_CTL(pipe); |
3458 | temp = I915_READ(reg); | |
8db9d77b ZW |
3459 | if (HAS_PCH_CPT(dev)) { |
3460 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3461 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3462 | } else { | |
3463 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3464 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3465 | } | |
5eddb70b CW |
3466 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3467 | ||
3468 | POSTING_READ(reg); | |
8db9d77b ZW |
3469 | udelay(150); |
3470 | ||
0206e353 | 3471 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3472 | reg = FDI_TX_CTL(pipe); |
3473 | temp = I915_READ(reg); | |
8db9d77b ZW |
3474 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3475 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3476 | I915_WRITE(reg, temp); |
3477 | ||
3478 | POSTING_READ(reg); | |
8db9d77b ZW |
3479 | udelay(500); |
3480 | ||
fa37d39e SP |
3481 | for (retry = 0; retry < 5; retry++) { |
3482 | reg = FDI_RX_IIR(pipe); | |
3483 | temp = I915_READ(reg); | |
3484 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3485 | if (temp & FDI_RX_BIT_LOCK) { | |
3486 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3487 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3488 | break; | |
3489 | } | |
3490 | udelay(50); | |
8db9d77b | 3491 | } |
fa37d39e SP |
3492 | if (retry < 5) |
3493 | break; | |
8db9d77b ZW |
3494 | } |
3495 | if (i == 4) | |
5eddb70b | 3496 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3497 | |
3498 | /* Train 2 */ | |
5eddb70b CW |
3499 | reg = FDI_TX_CTL(pipe); |
3500 | temp = I915_READ(reg); | |
8db9d77b ZW |
3501 | temp &= ~FDI_LINK_TRAIN_NONE; |
3502 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3503 | if (IS_GEN6(dev)) { | |
3504 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3505 | /* SNB-B */ | |
3506 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3507 | } | |
5eddb70b | 3508 | I915_WRITE(reg, temp); |
8db9d77b | 3509 | |
5eddb70b CW |
3510 | reg = FDI_RX_CTL(pipe); |
3511 | temp = I915_READ(reg); | |
8db9d77b ZW |
3512 | if (HAS_PCH_CPT(dev)) { |
3513 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3514 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3515 | } else { | |
3516 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3517 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3518 | } | |
5eddb70b CW |
3519 | I915_WRITE(reg, temp); |
3520 | ||
3521 | POSTING_READ(reg); | |
8db9d77b ZW |
3522 | udelay(150); |
3523 | ||
0206e353 | 3524 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3525 | reg = FDI_TX_CTL(pipe); |
3526 | temp = I915_READ(reg); | |
8db9d77b ZW |
3527 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3528 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3529 | I915_WRITE(reg, temp); |
3530 | ||
3531 | POSTING_READ(reg); | |
8db9d77b ZW |
3532 | udelay(500); |
3533 | ||
fa37d39e SP |
3534 | for (retry = 0; retry < 5; retry++) { |
3535 | reg = FDI_RX_IIR(pipe); | |
3536 | temp = I915_READ(reg); | |
3537 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3538 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3539 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3540 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3541 | break; | |
3542 | } | |
3543 | udelay(50); | |
8db9d77b | 3544 | } |
fa37d39e SP |
3545 | if (retry < 5) |
3546 | break; | |
8db9d77b ZW |
3547 | } |
3548 | if (i == 4) | |
5eddb70b | 3549 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3550 | |
3551 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3552 | } | |
3553 | ||
357555c0 JB |
3554 | /* Manual link training for Ivy Bridge A0 parts */ |
3555 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3556 | { | |
3557 | struct drm_device *dev = crtc->dev; | |
3558 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3559 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3560 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3561 | i915_reg_t reg; |
3562 | u32 temp, i, j; | |
357555c0 JB |
3563 | |
3564 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3565 | for train result */ | |
3566 | reg = FDI_RX_IMR(pipe); | |
3567 | temp = I915_READ(reg); | |
3568 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3569 | temp &= ~FDI_RX_BIT_LOCK; | |
3570 | I915_WRITE(reg, temp); | |
3571 | ||
3572 | POSTING_READ(reg); | |
3573 | udelay(150); | |
3574 | ||
01a415fd DV |
3575 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3576 | I915_READ(FDI_RX_IIR(pipe))); | |
3577 | ||
139ccd3f JB |
3578 | /* Try each vswing and preemphasis setting twice before moving on */ |
3579 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3580 | /* disable first in case we need to retry */ | |
3581 | reg = FDI_TX_CTL(pipe); | |
3582 | temp = I915_READ(reg); | |
3583 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3584 | temp &= ~FDI_TX_ENABLE; | |
3585 | I915_WRITE(reg, temp); | |
357555c0 | 3586 | |
139ccd3f JB |
3587 | reg = FDI_RX_CTL(pipe); |
3588 | temp = I915_READ(reg); | |
3589 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3590 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3591 | temp &= ~FDI_RX_ENABLE; | |
3592 | I915_WRITE(reg, temp); | |
357555c0 | 3593 | |
139ccd3f | 3594 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3595 | reg = FDI_TX_CTL(pipe); |
3596 | temp = I915_READ(reg); | |
139ccd3f | 3597 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3598 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 3599 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3600 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3601 | temp |= snb_b_fdi_train_param[j/2]; |
3602 | temp |= FDI_COMPOSITE_SYNC; | |
3603 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3604 | |
139ccd3f JB |
3605 | I915_WRITE(FDI_RX_MISC(pipe), |
3606 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3607 | |
139ccd3f | 3608 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3609 | temp = I915_READ(reg); |
139ccd3f JB |
3610 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3611 | temp |= FDI_COMPOSITE_SYNC; | |
3612 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3613 | |
139ccd3f JB |
3614 | POSTING_READ(reg); |
3615 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3616 | |
139ccd3f JB |
3617 | for (i = 0; i < 4; i++) { |
3618 | reg = FDI_RX_IIR(pipe); | |
3619 | temp = I915_READ(reg); | |
3620 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3621 | |
139ccd3f JB |
3622 | if (temp & FDI_RX_BIT_LOCK || |
3623 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3624 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3625 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3626 | i); | |
3627 | break; | |
3628 | } | |
3629 | udelay(1); /* should be 0.5us */ | |
3630 | } | |
3631 | if (i == 4) { | |
3632 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3633 | continue; | |
3634 | } | |
357555c0 | 3635 | |
139ccd3f | 3636 | /* Train 2 */ |
357555c0 JB |
3637 | reg = FDI_TX_CTL(pipe); |
3638 | temp = I915_READ(reg); | |
139ccd3f JB |
3639 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3640 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3641 | I915_WRITE(reg, temp); | |
3642 | ||
3643 | reg = FDI_RX_CTL(pipe); | |
3644 | temp = I915_READ(reg); | |
3645 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3646 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3647 | I915_WRITE(reg, temp); |
3648 | ||
3649 | POSTING_READ(reg); | |
139ccd3f | 3650 | udelay(2); /* should be 1.5us */ |
357555c0 | 3651 | |
139ccd3f JB |
3652 | for (i = 0; i < 4; i++) { |
3653 | reg = FDI_RX_IIR(pipe); | |
3654 | temp = I915_READ(reg); | |
3655 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3656 | |
139ccd3f JB |
3657 | if (temp & FDI_RX_SYMBOL_LOCK || |
3658 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3659 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3660 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3661 | i); | |
3662 | goto train_done; | |
3663 | } | |
3664 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3665 | } |
139ccd3f JB |
3666 | if (i == 4) |
3667 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3668 | } |
357555c0 | 3669 | |
139ccd3f | 3670 | train_done: |
357555c0 JB |
3671 | DRM_DEBUG_KMS("FDI train done.\n"); |
3672 | } | |
3673 | ||
88cefb6c | 3674 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3675 | { |
88cefb6c | 3676 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3677 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3678 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
3679 | i915_reg_t reg; |
3680 | u32 temp; | |
c64e311e | 3681 | |
c98e9dcf | 3682 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3683 | reg = FDI_RX_CTL(pipe); |
3684 | temp = I915_READ(reg); | |
627eb5a3 | 3685 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3686 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3687 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3688 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3689 | ||
3690 | POSTING_READ(reg); | |
c98e9dcf JB |
3691 | udelay(200); |
3692 | ||
3693 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3694 | temp = I915_READ(reg); |
3695 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3696 | ||
3697 | POSTING_READ(reg); | |
c98e9dcf JB |
3698 | udelay(200); |
3699 | ||
20749730 PZ |
3700 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3701 | reg = FDI_TX_CTL(pipe); | |
3702 | temp = I915_READ(reg); | |
3703 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3704 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3705 | |
20749730 PZ |
3706 | POSTING_READ(reg); |
3707 | udelay(100); | |
6be4a607 | 3708 | } |
0e23b99d JB |
3709 | } |
3710 | ||
88cefb6c DV |
3711 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3712 | { | |
3713 | struct drm_device *dev = intel_crtc->base.dev; | |
3714 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3715 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3716 | i915_reg_t reg; |
3717 | u32 temp; | |
88cefb6c DV |
3718 | |
3719 | /* Switch from PCDclk to Rawclk */ | |
3720 | reg = FDI_RX_CTL(pipe); | |
3721 | temp = I915_READ(reg); | |
3722 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3723 | ||
3724 | /* Disable CPU FDI TX PLL */ | |
3725 | reg = FDI_TX_CTL(pipe); | |
3726 | temp = I915_READ(reg); | |
3727 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3728 | ||
3729 | POSTING_READ(reg); | |
3730 | udelay(100); | |
3731 | ||
3732 | reg = FDI_RX_CTL(pipe); | |
3733 | temp = I915_READ(reg); | |
3734 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3735 | ||
3736 | /* Wait for the clocks to turn off. */ | |
3737 | POSTING_READ(reg); | |
3738 | udelay(100); | |
3739 | } | |
3740 | ||
0fc932b8 JB |
3741 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3742 | { | |
3743 | struct drm_device *dev = crtc->dev; | |
3744 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3745 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3746 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3747 | i915_reg_t reg; |
3748 | u32 temp; | |
0fc932b8 JB |
3749 | |
3750 | /* disable CPU FDI tx and PCH FDI rx */ | |
3751 | reg = FDI_TX_CTL(pipe); | |
3752 | temp = I915_READ(reg); | |
3753 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3754 | POSTING_READ(reg); | |
3755 | ||
3756 | reg = FDI_RX_CTL(pipe); | |
3757 | temp = I915_READ(reg); | |
3758 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3759 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3760 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3761 | ||
3762 | POSTING_READ(reg); | |
3763 | udelay(100); | |
3764 | ||
3765 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3766 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3767 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3768 | |
3769 | /* still set train pattern 1 */ | |
3770 | reg = FDI_TX_CTL(pipe); | |
3771 | temp = I915_READ(reg); | |
3772 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3773 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3774 | I915_WRITE(reg, temp); | |
3775 | ||
3776 | reg = FDI_RX_CTL(pipe); | |
3777 | temp = I915_READ(reg); | |
3778 | if (HAS_PCH_CPT(dev)) { | |
3779 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3780 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3781 | } else { | |
3782 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3783 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3784 | } | |
3785 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3786 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3787 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3788 | I915_WRITE(reg, temp); |
3789 | ||
3790 | POSTING_READ(reg); | |
3791 | udelay(100); | |
3792 | } | |
3793 | ||
5dce5b93 CW |
3794 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3795 | { | |
3796 | struct intel_crtc *crtc; | |
3797 | ||
3798 | /* Note that we don't need to be called with mode_config.lock here | |
3799 | * as our list of CRTC objects is static for the lifetime of the | |
3800 | * device and so cannot disappear as we iterate. Similarly, we can | |
3801 | * happily treat the predicates as racy, atomic checks as userspace | |
3802 | * cannot claim and pin a new fb without at least acquring the | |
3803 | * struct_mutex and so serialising with us. | |
3804 | */ | |
d3fcc808 | 3805 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3806 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3807 | continue; | |
3808 | ||
3809 | if (crtc->unpin_work) | |
3810 | intel_wait_for_vblank(dev, crtc->pipe); | |
3811 | ||
3812 | return true; | |
3813 | } | |
3814 | ||
3815 | return false; | |
3816 | } | |
3817 | ||
d6bbafa1 CW |
3818 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
3819 | { | |
3820 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
3821 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
3822 | ||
3823 | /* ensure that the unpin work is consistent wrt ->pending. */ | |
3824 | smp_rmb(); | |
3825 | intel_crtc->unpin_work = NULL; | |
3826 | ||
3827 | if (work->event) | |
3828 | drm_send_vblank_event(intel_crtc->base.dev, | |
3829 | intel_crtc->pipe, | |
3830 | work->event); | |
3831 | ||
3832 | drm_crtc_vblank_put(&intel_crtc->base); | |
3833 | ||
3834 | wake_up_all(&dev_priv->pending_flip_queue); | |
3835 | queue_work(dev_priv->wq, &work->work); | |
3836 | ||
3837 | trace_i915_flip_complete(intel_crtc->plane, | |
3838 | work->pending_flip_obj); | |
3839 | } | |
3840 | ||
5008e874 | 3841 | static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3842 | { |
0f91128d | 3843 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3844 | struct drm_i915_private *dev_priv = dev->dev_private; |
5008e874 | 3845 | long ret; |
e6c3a2a6 | 3846 | |
2c10d571 | 3847 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
5008e874 ML |
3848 | |
3849 | ret = wait_event_interruptible_timeout( | |
3850 | dev_priv->pending_flip_queue, | |
3851 | !intel_crtc_has_pending_flip(crtc), | |
3852 | 60*HZ); | |
3853 | ||
3854 | if (ret < 0) | |
3855 | return ret; | |
3856 | ||
3857 | if (ret == 0) { | |
9c787942 | 3858 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2c10d571 | 3859 | |
5e2d7afc | 3860 | spin_lock_irq(&dev->event_lock); |
9c787942 CW |
3861 | if (intel_crtc->unpin_work) { |
3862 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
3863 | page_flip_completed(intel_crtc); | |
3864 | } | |
5e2d7afc | 3865 | spin_unlock_irq(&dev->event_lock); |
9c787942 | 3866 | } |
5bb61643 | 3867 | |
5008e874 | 3868 | return 0; |
e6c3a2a6 CW |
3869 | } |
3870 | ||
060f02d8 VS |
3871 | static void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
3872 | { | |
3873 | u32 temp; | |
3874 | ||
3875 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3876 | ||
3877 | mutex_lock(&dev_priv->sb_lock); | |
3878 | ||
3879 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
3880 | temp |= SBI_SSCCTL_DISABLE; | |
3881 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
3882 | ||
3883 | mutex_unlock(&dev_priv->sb_lock); | |
3884 | } | |
3885 | ||
e615efe4 ED |
3886 | /* Program iCLKIP clock to the desired frequency */ |
3887 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3888 | { | |
64b46a06 | 3889 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
6e3c9717 | 3890 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
3891 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3892 | u32 temp; | |
3893 | ||
060f02d8 | 3894 | lpt_disable_iclkip(dev_priv); |
e615efe4 | 3895 | |
64b46a06 VS |
3896 | /* The iCLK virtual clock root frequency is in MHz, |
3897 | * but the adjusted_mode->crtc_clock in in KHz. To get the | |
3898 | * divisors, it is necessary to divide one by another, so we | |
3899 | * convert the virtual clock precision to KHz here for higher | |
3900 | * precision. | |
3901 | */ | |
3902 | for (auxdiv = 0; auxdiv < 2; auxdiv++) { | |
e615efe4 ED |
3903 | u32 iclk_virtual_root_freq = 172800 * 1000; |
3904 | u32 iclk_pi_range = 64; | |
64b46a06 | 3905 | u32 desired_divisor; |
e615efe4 | 3906 | |
64b46a06 VS |
3907 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, |
3908 | clock << auxdiv); | |
3909 | divsel = (desired_divisor / iclk_pi_range) - 2; | |
3910 | phaseinc = desired_divisor % iclk_pi_range; | |
e615efe4 | 3911 | |
64b46a06 VS |
3912 | /* |
3913 | * Near 20MHz is a corner case which is | |
3914 | * out of range for the 7-bit divisor | |
3915 | */ | |
3916 | if (divsel <= 0x7f) | |
3917 | break; | |
e615efe4 ED |
3918 | } |
3919 | ||
3920 | /* This should not happen with any sane values */ | |
3921 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3922 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3923 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3924 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3925 | ||
3926 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3927 | clock, |
e615efe4 ED |
3928 | auxdiv, |
3929 | divsel, | |
3930 | phasedir, | |
3931 | phaseinc); | |
3932 | ||
060f02d8 VS |
3933 | mutex_lock(&dev_priv->sb_lock); |
3934 | ||
e615efe4 | 3935 | /* Program SSCDIVINTPHASE6 */ |
988d6ee8 | 3936 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3937 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3938 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3939 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3940 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3941 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3942 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3943 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3944 | |
3945 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3946 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3947 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3948 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3949 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3950 | |
3951 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3952 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3953 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3954 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 | 3955 | |
060f02d8 VS |
3956 | mutex_unlock(&dev_priv->sb_lock); |
3957 | ||
e615efe4 ED |
3958 | /* Wait for initialization time */ |
3959 | udelay(24); | |
3960 | ||
3961 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
3962 | } | |
3963 | ||
8802e5b6 VS |
3964 | int lpt_get_iclkip(struct drm_i915_private *dev_priv) |
3965 | { | |
3966 | u32 divsel, phaseinc, auxdiv; | |
3967 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3968 | u32 iclk_pi_range = 64; | |
3969 | u32 desired_divisor; | |
3970 | u32 temp; | |
3971 | ||
3972 | if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) | |
3973 | return 0; | |
3974 | ||
3975 | mutex_lock(&dev_priv->sb_lock); | |
3976 | ||
3977 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
3978 | if (temp & SBI_SSCCTL_DISABLE) { | |
3979 | mutex_unlock(&dev_priv->sb_lock); | |
3980 | return 0; | |
3981 | } | |
3982 | ||
3983 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); | |
3984 | divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >> | |
3985 | SBI_SSCDIVINTPHASE_DIVSEL_SHIFT; | |
3986 | phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >> | |
3987 | SBI_SSCDIVINTPHASE_INCVAL_SHIFT; | |
3988 | ||
3989 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); | |
3990 | auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >> | |
3991 | SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT; | |
3992 | ||
3993 | mutex_unlock(&dev_priv->sb_lock); | |
3994 | ||
3995 | desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc; | |
3996 | ||
3997 | return DIV_ROUND_CLOSEST(iclk_virtual_root_freq, | |
3998 | desired_divisor << auxdiv); | |
3999 | } | |
4000 | ||
275f01b2 DV |
4001 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4002 | enum pipe pch_transcoder) | |
4003 | { | |
4004 | struct drm_device *dev = crtc->base.dev; | |
4005 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 4006 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4007 | |
4008 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4009 | I915_READ(HTOTAL(cpu_transcoder))); | |
4010 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4011 | I915_READ(HBLANK(cpu_transcoder))); | |
4012 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4013 | I915_READ(HSYNC(cpu_transcoder))); | |
4014 | ||
4015 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4016 | I915_READ(VTOTAL(cpu_transcoder))); | |
4017 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4018 | I915_READ(VBLANK(cpu_transcoder))); | |
4019 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4020 | I915_READ(VSYNC(cpu_transcoder))); | |
4021 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4022 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4023 | } | |
4024 | ||
003632d9 | 4025 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 DV |
4026 | { |
4027 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4028 | uint32_t temp; | |
4029 | ||
4030 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4031 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4032 | return; |
4033 | ||
4034 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4035 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4036 | ||
003632d9 ACO |
4037 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4038 | if (enable) | |
4039 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4040 | ||
4041 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4042 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4043 | POSTING_READ(SOUTH_CHICKEN1); | |
4044 | } | |
4045 | ||
4046 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4047 | { | |
4048 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4049 | |
4050 | switch (intel_crtc->pipe) { | |
4051 | case PIPE_A: | |
4052 | break; | |
4053 | case PIPE_B: | |
6e3c9717 | 4054 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4055 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4056 | else |
003632d9 | 4057 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4058 | |
4059 | break; | |
4060 | case PIPE_C: | |
003632d9 | 4061 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4062 | |
4063 | break; | |
4064 | default: | |
4065 | BUG(); | |
4066 | } | |
4067 | } | |
4068 | ||
c48b5305 VS |
4069 | /* Return which DP Port should be selected for Transcoder DP control */ |
4070 | static enum port | |
4071 | intel_trans_dp_port_sel(struct drm_crtc *crtc) | |
4072 | { | |
4073 | struct drm_device *dev = crtc->dev; | |
4074 | struct intel_encoder *encoder; | |
4075 | ||
4076 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
4077 | if (encoder->type == INTEL_OUTPUT_DISPLAYPORT || | |
4078 | encoder->type == INTEL_OUTPUT_EDP) | |
4079 | return enc_to_dig_port(&encoder->base)->port; | |
4080 | } | |
4081 | ||
4082 | return -1; | |
4083 | } | |
4084 | ||
f67a559d JB |
4085 | /* |
4086 | * Enable PCH resources required for PCH ports: | |
4087 | * - PCH PLLs | |
4088 | * - FDI training & RX/TX | |
4089 | * - update transcoder timings | |
4090 | * - DP transcoding bits | |
4091 | * - transcoder | |
4092 | */ | |
4093 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4094 | { |
4095 | struct drm_device *dev = crtc->dev; | |
4096 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4097 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4098 | int pipe = intel_crtc->pipe; | |
f0f59a00 | 4099 | u32 temp; |
2c07245f | 4100 | |
ab9412ba | 4101 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4102 | |
1fbc0d78 DV |
4103 | if (IS_IVYBRIDGE(dev)) |
4104 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
4105 | ||
cd986abb DV |
4106 | /* Write the TU size bits before fdi link training, so that error |
4107 | * detection works. */ | |
4108 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4109 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4110 | ||
3860b2ec VS |
4111 | /* |
4112 | * Sometimes spurious CPU pipe underruns happen during FDI | |
4113 | * training, at least with VGA+HDMI cloning. Suppress them. | |
4114 | */ | |
4115 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
4116 | ||
c98e9dcf | 4117 | /* For PCH output, training FDI link */ |
674cf967 | 4118 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4119 | |
3ad8a208 DV |
4120 | /* We need to program the right clock selection before writing the pixel |
4121 | * mutliplier into the DPLL. */ | |
303b81e0 | 4122 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 4123 | u32 sel; |
4b645f14 | 4124 | |
c98e9dcf | 4125 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4126 | temp |= TRANS_DPLL_ENABLE(pipe); |
4127 | sel = TRANS_DPLLB_SEL(pipe); | |
8106ddbd ACO |
4128 | if (intel_crtc->config->shared_dpll == |
4129 | intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B)) | |
ee7b9f93 JB |
4130 | temp |= sel; |
4131 | else | |
4132 | temp &= ~sel; | |
c98e9dcf | 4133 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4134 | } |
5eddb70b | 4135 | |
3ad8a208 DV |
4136 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4137 | * transcoder, and we actually should do this to not upset any PCH | |
4138 | * transcoder that already use the clock when we share it. | |
4139 | * | |
4140 | * Note that enable_shared_dpll tries to do the right thing, but | |
4141 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4142 | * the right LVDS enable sequence. */ | |
85b3894f | 4143 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4144 | |
d9b6cb56 JB |
4145 | /* set transcoder timing, panel must allow it */ |
4146 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4147 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4148 | |
303b81e0 | 4149 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4150 | |
3860b2ec VS |
4151 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4152 | ||
c98e9dcf | 4153 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e3c9717 | 4154 | if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { |
9c4edaee VS |
4155 | const struct drm_display_mode *adjusted_mode = |
4156 | &intel_crtc->config->base.adjusted_mode; | |
dfd07d72 | 4157 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
f0f59a00 | 4158 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
5eddb70b CW |
4159 | temp = I915_READ(reg); |
4160 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4161 | TRANS_DP_SYNC_MASK | |
4162 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4163 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4164 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf | 4165 | |
9c4edaee | 4166 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
5eddb70b | 4167 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
9c4edaee | 4168 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4169 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4170 | |
4171 | switch (intel_trans_dp_port_sel(crtc)) { | |
c48b5305 | 4172 | case PORT_B: |
5eddb70b | 4173 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 4174 | break; |
c48b5305 | 4175 | case PORT_C: |
5eddb70b | 4176 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf | 4177 | break; |
c48b5305 | 4178 | case PORT_D: |
5eddb70b | 4179 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4180 | break; |
4181 | default: | |
e95d41e1 | 4182 | BUG(); |
32f9d658 | 4183 | } |
2c07245f | 4184 | |
5eddb70b | 4185 | I915_WRITE(reg, temp); |
6be4a607 | 4186 | } |
b52eb4dc | 4187 | |
b8a4f404 | 4188 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4189 | } |
4190 | ||
1507e5bd PZ |
4191 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4192 | { | |
4193 | struct drm_device *dev = crtc->dev; | |
4194 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4195 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6e3c9717 | 4196 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4197 | |
ab9412ba | 4198 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4199 | |
8c52b5e8 | 4200 | lpt_program_iclkip(crtc); |
1507e5bd | 4201 | |
0540e488 | 4202 | /* Set transcoder timing. */ |
275f01b2 | 4203 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4204 | |
937bb610 | 4205 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4206 | } |
4207 | ||
a1520318 | 4208 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
4209 | { |
4210 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 4211 | i915_reg_t dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4212 | u32 temp; |
4213 | ||
4214 | temp = I915_READ(dslreg); | |
4215 | udelay(500); | |
4216 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4217 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4218 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4219 | } |
4220 | } | |
4221 | ||
86adf9d7 ML |
4222 | static int |
4223 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
4224 | unsigned scaler_user, int *scaler_id, unsigned int rotation, | |
4225 | int src_w, int src_h, int dst_w, int dst_h) | |
a1b2278e | 4226 | { |
86adf9d7 ML |
4227 | struct intel_crtc_scaler_state *scaler_state = |
4228 | &crtc_state->scaler_state; | |
4229 | struct intel_crtc *intel_crtc = | |
4230 | to_intel_crtc(crtc_state->base.crtc); | |
a1b2278e | 4231 | int need_scaling; |
6156a456 CK |
4232 | |
4233 | need_scaling = intel_rotation_90_or_270(rotation) ? | |
4234 | (src_h != dst_w || src_w != dst_h): | |
4235 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4236 | |
4237 | /* | |
4238 | * if plane is being disabled or scaler is no more required or force detach | |
4239 | * - free scaler binded to this plane/crtc | |
4240 | * - in order to do this, update crtc->scaler_usage | |
4241 | * | |
4242 | * Here scaler state in crtc_state is set free so that | |
4243 | * scaler can be assigned to other user. Actual register | |
4244 | * update to free the scaler is done in plane/panel-fit programming. | |
4245 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4246 | */ | |
86adf9d7 | 4247 | if (force_detach || !need_scaling) { |
a1b2278e | 4248 | if (*scaler_id >= 0) { |
86adf9d7 | 4249 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4250 | scaler_state->scalers[*scaler_id].in_use = 0; |
4251 | ||
86adf9d7 ML |
4252 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4253 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4254 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4255 | scaler_state->scaler_users); |
4256 | *scaler_id = -1; | |
4257 | } | |
4258 | return 0; | |
4259 | } | |
4260 | ||
4261 | /* range checks */ | |
4262 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4263 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4264 | ||
4265 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4266 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4267 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4268 | "size is out of scaler range\n", |
86adf9d7 | 4269 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4270 | return -EINVAL; |
4271 | } | |
4272 | ||
86adf9d7 ML |
4273 | /* mark this plane as a scaler user in crtc_state */ |
4274 | scaler_state->scaler_users |= (1 << scaler_user); | |
4275 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4276 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4277 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4278 | scaler_state->scaler_users); | |
4279 | ||
4280 | return 0; | |
4281 | } | |
4282 | ||
4283 | /** | |
4284 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4285 | * | |
4286 | * @state: crtc's scaler state | |
86adf9d7 ML |
4287 | * |
4288 | * Return | |
4289 | * 0 - scaler_usage updated successfully | |
4290 | * error - requested scaling cannot be supported or other error condition | |
4291 | */ | |
e435d6e5 | 4292 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 ML |
4293 | { |
4294 | struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); | |
7c5f93b0 | 4295 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
86adf9d7 ML |
4296 | |
4297 | DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n", | |
4298 | intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX); | |
4299 | ||
e435d6e5 | 4300 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
fa5a7970 | 4301 | &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0), |
86adf9d7 | 4302 | state->pipe_src_w, state->pipe_src_h, |
aad941d5 | 4303 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
86adf9d7 ML |
4304 | } |
4305 | ||
4306 | /** | |
4307 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4308 | * | |
4309 | * @state: crtc's scaler state | |
86adf9d7 ML |
4310 | * @plane_state: atomic plane state to update |
4311 | * | |
4312 | * Return | |
4313 | * 0 - scaler_usage updated successfully | |
4314 | * error - requested scaling cannot be supported or other error condition | |
4315 | */ | |
da20eabd ML |
4316 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4317 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4318 | { |
4319 | ||
4320 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
da20eabd ML |
4321 | struct intel_plane *intel_plane = |
4322 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4323 | struct drm_framebuffer *fb = plane_state->base.fb; |
4324 | int ret; | |
4325 | ||
4326 | bool force_detach = !fb || !plane_state->visible; | |
4327 | ||
4328 | DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n", | |
4329 | intel_plane->base.base.id, intel_crtc->pipe, | |
4330 | drm_plane_index(&intel_plane->base)); | |
4331 | ||
4332 | ret = skl_update_scaler(crtc_state, force_detach, | |
4333 | drm_plane_index(&intel_plane->base), | |
4334 | &plane_state->scaler_id, | |
4335 | plane_state->base.rotation, | |
4336 | drm_rect_width(&plane_state->src) >> 16, | |
4337 | drm_rect_height(&plane_state->src) >> 16, | |
4338 | drm_rect_width(&plane_state->dst), | |
4339 | drm_rect_height(&plane_state->dst)); | |
4340 | ||
4341 | if (ret || plane_state->scaler_id < 0) | |
4342 | return ret; | |
4343 | ||
a1b2278e | 4344 | /* check colorkey */ |
818ed961 | 4345 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
86adf9d7 | 4346 | DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed", |
818ed961 | 4347 | intel_plane->base.base.id); |
a1b2278e CK |
4348 | return -EINVAL; |
4349 | } | |
4350 | ||
4351 | /* Check src format */ | |
86adf9d7 ML |
4352 | switch (fb->pixel_format) { |
4353 | case DRM_FORMAT_RGB565: | |
4354 | case DRM_FORMAT_XBGR8888: | |
4355 | case DRM_FORMAT_XRGB8888: | |
4356 | case DRM_FORMAT_ABGR8888: | |
4357 | case DRM_FORMAT_ARGB8888: | |
4358 | case DRM_FORMAT_XRGB2101010: | |
4359 | case DRM_FORMAT_XBGR2101010: | |
4360 | case DRM_FORMAT_YUYV: | |
4361 | case DRM_FORMAT_YVYU: | |
4362 | case DRM_FORMAT_UYVY: | |
4363 | case DRM_FORMAT_VYUY: | |
4364 | break; | |
4365 | default: | |
4366 | DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n", | |
4367 | intel_plane->base.base.id, fb->base.id, fb->pixel_format); | |
4368 | return -EINVAL; | |
a1b2278e CK |
4369 | } |
4370 | ||
a1b2278e CK |
4371 | return 0; |
4372 | } | |
4373 | ||
e435d6e5 ML |
4374 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4375 | { | |
4376 | int i; | |
4377 | ||
4378 | for (i = 0; i < crtc->num_scalers; i++) | |
4379 | skl_detach_scaler(crtc, i); | |
4380 | } | |
4381 | ||
4382 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4383 | { |
4384 | struct drm_device *dev = crtc->base.dev; | |
4385 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4386 | int pipe = crtc->pipe; | |
a1b2278e CK |
4387 | struct intel_crtc_scaler_state *scaler_state = |
4388 | &crtc->config->scaler_state; | |
4389 | ||
4390 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4391 | ||
6e3c9717 | 4392 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4393 | int id; |
4394 | ||
4395 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4396 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4397 | return; | |
4398 | } | |
4399 | ||
4400 | id = scaler_state->scaler_id; | |
4401 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4402 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4403 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4404 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4405 | ||
4406 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4407 | } |
4408 | } | |
4409 | ||
b074cec8 JB |
4410 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4411 | { | |
4412 | struct drm_device *dev = crtc->base.dev; | |
4413 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4414 | int pipe = crtc->pipe; | |
4415 | ||
6e3c9717 | 4416 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4417 | /* Force use of hard-coded filter coefficients |
4418 | * as some pre-programmed values are broken, | |
4419 | * e.g. x201. | |
4420 | */ | |
4421 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4422 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4423 | PF_PIPE_SEL_IVB(pipe)); | |
4424 | else | |
4425 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4426 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4427 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4428 | } |
4429 | } | |
4430 | ||
20bc8673 | 4431 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4432 | { |
cea165c3 VS |
4433 | struct drm_device *dev = crtc->base.dev; |
4434 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 | 4435 | |
6e3c9717 | 4436 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4437 | return; |
4438 | ||
cea165c3 VS |
4439 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
4440 | intel_wait_for_vblank(dev, crtc->pipe); | |
4441 | ||
d77e4531 | 4442 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4443 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4444 | mutex_lock(&dev_priv->rps.hw_lock); |
4445 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4446 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4447 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4448 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4449 | * mailbox." Moreover, the mailbox may return a bogus state, |
4450 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4451 | */ |
4452 | } else { | |
4453 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4454 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4455 | * is essentially intel_wait_for_vblank. If we don't have this | |
4456 | * and don't wait for vblanks until the end of crtc_enable, then | |
4457 | * the HW state readout code will complain that the expected | |
4458 | * IPS_CTL value is not the one we read. */ | |
4459 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
4460 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
4461 | } | |
d77e4531 PZ |
4462 | } |
4463 | ||
20bc8673 | 4464 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4465 | { |
4466 | struct drm_device *dev = crtc->base.dev; | |
4467 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4468 | ||
6e3c9717 | 4469 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4470 | return; |
4471 | ||
4472 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4473 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4474 | mutex_lock(&dev_priv->rps.hw_lock); |
4475 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4476 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
4477 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
4478 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
4479 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 4480 | } else { |
2a114cc1 | 4481 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4482 | POSTING_READ(IPS_CTL); |
4483 | } | |
d77e4531 PZ |
4484 | |
4485 | /* We need to wait for a vblank before we can disable the plane. */ | |
4486 | intel_wait_for_vblank(dev, crtc->pipe); | |
4487 | } | |
4488 | ||
7cac945f | 4489 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4490 | { |
7cac945f | 4491 | if (intel_crtc->overlay) { |
d3eedb1a VS |
4492 | struct drm_device *dev = intel_crtc->base.dev; |
4493 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4494 | ||
4495 | mutex_lock(&dev->struct_mutex); | |
4496 | dev_priv->mm.interruptible = false; | |
4497 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4498 | dev_priv->mm.interruptible = true; | |
4499 | mutex_unlock(&dev->struct_mutex); | |
4500 | } | |
4501 | ||
4502 | /* Let userspace switch the overlay on again. In most cases userspace | |
4503 | * has to recompute where to put it anyway. | |
4504 | */ | |
4505 | } | |
4506 | ||
87d4300a ML |
4507 | /** |
4508 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4509 | * @crtc: the CRTC whose primary plane was just enabled | |
4510 | * | |
4511 | * Performs potentially sleeping operations that must be done after the primary | |
4512 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4513 | * called due to an explicit primary plane update, or due to an implicit | |
4514 | * re-enable that is caused when a sprite plane is updated to no longer | |
4515 | * completely hide the primary plane. | |
4516 | */ | |
4517 | static void | |
4518 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4519 | { |
4520 | struct drm_device *dev = crtc->dev; | |
87d4300a | 4521 | struct drm_i915_private *dev_priv = dev->dev_private; |
a5c4d7bc VS |
4522 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4523 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4524 | |
87d4300a ML |
4525 | /* |
4526 | * FIXME IPS should be fine as long as one plane is | |
4527 | * enabled, but in practice it seems to have problems | |
4528 | * when going from primary only to sprite only and vice | |
4529 | * versa. | |
4530 | */ | |
a5c4d7bc VS |
4531 | hsw_enable_ips(intel_crtc); |
4532 | ||
f99d7069 | 4533 | /* |
87d4300a ML |
4534 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4535 | * So don't enable underrun reporting before at least some planes | |
4536 | * are enabled. | |
4537 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4538 | * but leave the pipe running. | |
f99d7069 | 4539 | */ |
87d4300a ML |
4540 | if (IS_GEN2(dev)) |
4541 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4542 | ||
aca7b684 VS |
4543 | /* Underruns don't always raise interrupts, so check manually. */ |
4544 | intel_check_cpu_fifo_underruns(dev_priv); | |
4545 | intel_check_pch_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4546 | } |
4547 | ||
2622a081 | 4548 | /* FIXME move all this to pre_plane_update() with proper state tracking */ |
87d4300a ML |
4549 | static void |
4550 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4551 | { |
4552 | struct drm_device *dev = crtc->dev; | |
4553 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4554 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4555 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4556 | |
87d4300a ML |
4557 | /* |
4558 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4559 | * So diasble underrun reporting before all the planes get disabled. | |
4560 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4561 | * but leave the pipe running. | |
4562 | */ | |
4563 | if (IS_GEN2(dev)) | |
4564 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
a5c4d7bc | 4565 | |
2622a081 VS |
4566 | /* |
4567 | * FIXME IPS should be fine as long as one plane is | |
4568 | * enabled, but in practice it seems to have problems | |
4569 | * when going from primary only to sprite only and vice | |
4570 | * versa. | |
4571 | */ | |
4572 | hsw_disable_ips(intel_crtc); | |
4573 | } | |
4574 | ||
4575 | /* FIXME get rid of this and use pre_plane_update */ | |
4576 | static void | |
4577 | intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) | |
4578 | { | |
4579 | struct drm_device *dev = crtc->dev; | |
4580 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4581 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4582 | int pipe = intel_crtc->pipe; | |
4583 | ||
4584 | intel_pre_disable_primary(crtc); | |
4585 | ||
87d4300a ML |
4586 | /* |
4587 | * Vblank time updates from the shadow to live plane control register | |
4588 | * are blocked if the memory self-refresh mode is active at that | |
4589 | * moment. So to make sure the plane gets truly disabled, disable | |
4590 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4591 | * will be checked/applied by the HW only at the next frame start | |
4592 | * event which is after the vblank start event, so we need to have a | |
4593 | * wait-for-vblank between disabling the plane and the pipe. | |
4594 | */ | |
262cd2e1 | 4595 | if (HAS_GMCH_DISPLAY(dev)) { |
87d4300a | 4596 | intel_set_memory_cxsr(dev_priv, false); |
262cd2e1 VS |
4597 | dev_priv->wm.vlv.cxsr = false; |
4598 | intel_wait_for_vblank(dev, pipe); | |
4599 | } | |
87d4300a ML |
4600 | } |
4601 | ||
cd202f69 | 4602 | static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) |
ac21b225 | 4603 | { |
cd202f69 ML |
4604 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
4605 | struct drm_atomic_state *old_state = old_crtc_state->base.state; | |
92826fcd ML |
4606 | struct intel_crtc_state *pipe_config = |
4607 | to_intel_crtc_state(crtc->base.state); | |
ac21b225 | 4608 | struct drm_device *dev = crtc->base.dev; |
cd202f69 ML |
4609 | struct drm_plane *primary = crtc->base.primary; |
4610 | struct drm_plane_state *old_pri_state = | |
4611 | drm_atomic_get_existing_plane_state(old_state, primary); | |
ac21b225 | 4612 | |
cd202f69 | 4613 | intel_frontbuffer_flip(dev, pipe_config->fb_bits); |
ac21b225 | 4614 | |
ab1d3a0e | 4615 | crtc->wm.cxsr_allowed = true; |
852eb00d | 4616 | |
caed361d | 4617 | if (pipe_config->update_wm_post && pipe_config->base.active) |
f015c551 VS |
4618 | intel_update_watermarks(&crtc->base); |
4619 | ||
cd202f69 ML |
4620 | if (old_pri_state) { |
4621 | struct intel_plane_state *primary_state = | |
4622 | to_intel_plane_state(primary->state); | |
4623 | struct intel_plane_state *old_primary_state = | |
4624 | to_intel_plane_state(old_pri_state); | |
4625 | ||
31ae71fc ML |
4626 | intel_fbc_post_update(crtc); |
4627 | ||
cd202f69 ML |
4628 | if (primary_state->visible && |
4629 | (needs_modeset(&pipe_config->base) || | |
4630 | !old_primary_state->visible)) | |
4631 | intel_post_enable_primary(&crtc->base); | |
4632 | } | |
ac21b225 ML |
4633 | } |
4634 | ||
5c74cd73 | 4635 | static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state) |
ac21b225 | 4636 | { |
5c74cd73 | 4637 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
ac21b225 | 4638 | struct drm_device *dev = crtc->base.dev; |
eddfcbcd | 4639 | struct drm_i915_private *dev_priv = dev->dev_private; |
ab1d3a0e ML |
4640 | struct intel_crtc_state *pipe_config = |
4641 | to_intel_crtc_state(crtc->base.state); | |
5c74cd73 ML |
4642 | struct drm_atomic_state *old_state = old_crtc_state->base.state; |
4643 | struct drm_plane *primary = crtc->base.primary; | |
4644 | struct drm_plane_state *old_pri_state = | |
4645 | drm_atomic_get_existing_plane_state(old_state, primary); | |
4646 | bool modeset = needs_modeset(&pipe_config->base); | |
ac21b225 | 4647 | |
5c74cd73 ML |
4648 | if (old_pri_state) { |
4649 | struct intel_plane_state *primary_state = | |
4650 | to_intel_plane_state(primary->state); | |
4651 | struct intel_plane_state *old_primary_state = | |
4652 | to_intel_plane_state(old_pri_state); | |
4653 | ||
31ae71fc ML |
4654 | intel_fbc_pre_update(crtc); |
4655 | ||
5c74cd73 ML |
4656 | if (old_primary_state->visible && |
4657 | (modeset || !primary_state->visible)) | |
4658 | intel_pre_disable_primary(&crtc->base); | |
4659 | } | |
852eb00d | 4660 | |
ab1d3a0e | 4661 | if (pipe_config->disable_cxsr) { |
852eb00d | 4662 | crtc->wm.cxsr_allowed = false; |
2dfd178d | 4663 | |
2622a081 VS |
4664 | /* |
4665 | * Vblank time updates from the shadow to live plane control register | |
4666 | * are blocked if the memory self-refresh mode is active at that | |
4667 | * moment. So to make sure the plane gets truly disabled, disable | |
4668 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4669 | * will be checked/applied by the HW only at the next frame start | |
4670 | * event which is after the vblank start event, so we need to have a | |
4671 | * wait-for-vblank between disabling the plane and the pipe. | |
4672 | */ | |
4673 | if (old_crtc_state->base.active) { | |
2dfd178d | 4674 | intel_set_memory_cxsr(dev_priv, false); |
2622a081 VS |
4675 | dev_priv->wm.vlv.cxsr = false; |
4676 | intel_wait_for_vblank(dev, crtc->pipe); | |
4677 | } | |
852eb00d | 4678 | } |
92826fcd | 4679 | |
ed4a6a7c MR |
4680 | /* |
4681 | * IVB workaround: must disable low power watermarks for at least | |
4682 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
4683 | * when scaling is disabled. | |
4684 | * | |
4685 | * WaCxSRDisabledForSpriteScaling:ivb | |
4686 | */ | |
4687 | if (pipe_config->disable_lp_wm) { | |
4688 | ilk_disable_lp_wm(dev); | |
4689 | intel_wait_for_vblank(dev, crtc->pipe); | |
4690 | } | |
4691 | ||
4692 | /* | |
4693 | * If we're doing a modeset, we're done. No need to do any pre-vblank | |
4694 | * watermark programming here. | |
4695 | */ | |
4696 | if (needs_modeset(&pipe_config->base)) | |
4697 | return; | |
4698 | ||
4699 | /* | |
4700 | * For platforms that support atomic watermarks, program the | |
4701 | * 'intermediate' watermarks immediately. On pre-gen9 platforms, these | |
4702 | * will be the intermediate values that are safe for both pre- and | |
4703 | * post- vblank; when vblank happens, the 'active' values will be set | |
4704 | * to the final 'target' values and we'll do this again to get the | |
4705 | * optimal watermarks. For gen9+ platforms, the values we program here | |
4706 | * will be the final target values which will get automatically latched | |
4707 | * at vblank time; no further programming will be necessary. | |
4708 | * | |
4709 | * If a platform hasn't been transitioned to atomic watermarks yet, | |
4710 | * we'll continue to update watermarks the old way, if flags tell | |
4711 | * us to. | |
4712 | */ | |
4713 | if (dev_priv->display.initial_watermarks != NULL) | |
4714 | dev_priv->display.initial_watermarks(pipe_config); | |
caed361d | 4715 | else if (pipe_config->update_wm_pre) |
92826fcd | 4716 | intel_update_watermarks(&crtc->base); |
ac21b225 ML |
4717 | } |
4718 | ||
d032ffa0 | 4719 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
4720 | { |
4721 | struct drm_device *dev = crtc->dev; | |
4722 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 4723 | struct drm_plane *p; |
87d4300a ML |
4724 | int pipe = intel_crtc->pipe; |
4725 | ||
7cac945f | 4726 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 4727 | |
d032ffa0 ML |
4728 | drm_for_each_plane_mask(p, dev, plane_mask) |
4729 | to_intel_plane(p)->disable_plane(p, crtc); | |
f98551ae | 4730 | |
f99d7069 DV |
4731 | /* |
4732 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4733 | * to compute the mask of flip planes precisely. For the time being | |
4734 | * consider this a flip to a NULL plane. | |
4735 | */ | |
4736 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4737 | } |
4738 | ||
f67a559d JB |
4739 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4740 | { | |
4741 | struct drm_device *dev = crtc->dev; | |
4742 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4743 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4744 | struct intel_encoder *encoder; |
f67a559d | 4745 | int pipe = intel_crtc->pipe; |
f67a559d | 4746 | |
53d9f4e9 | 4747 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
4748 | return; |
4749 | ||
81b088ca VS |
4750 | if (intel_crtc->config->has_pch_encoder) |
4751 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
4752 | ||
6e3c9717 | 4753 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
4754 | intel_prepare_shared_dpll(intel_crtc); |
4755 | ||
6e3c9717 | 4756 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4757 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
4758 | |
4759 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 4760 | intel_set_pipe_src_size(intel_crtc); |
29407aab | 4761 | |
6e3c9717 | 4762 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 4763 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4764 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
4765 | } |
4766 | ||
4767 | ironlake_set_pipeconf(crtc); | |
4768 | ||
f67a559d | 4769 | intel_crtc->active = true; |
8664281b | 4770 | |
a72e4c9f | 4771 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
8664281b | 4772 | |
f6736a1a | 4773 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4774 | if (encoder->pre_enable) |
4775 | encoder->pre_enable(encoder); | |
f67a559d | 4776 | |
6e3c9717 | 4777 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
4778 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4779 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4780 | * enabling. */ | |
88cefb6c | 4781 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4782 | } else { |
4783 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4784 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4785 | } | |
f67a559d | 4786 | |
b074cec8 | 4787 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4788 | |
9c54c0dd JB |
4789 | /* |
4790 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4791 | * clocks enabled | |
4792 | */ | |
8563b1e8 | 4793 | intel_color_load_luts(crtc); |
9c54c0dd | 4794 | |
1d5bf5d9 ID |
4795 | if (dev_priv->display.initial_watermarks != NULL) |
4796 | dev_priv->display.initial_watermarks(intel_crtc->config); | |
e1fdc473 | 4797 | intel_enable_pipe(intel_crtc); |
f67a559d | 4798 | |
6e3c9717 | 4799 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 4800 | ironlake_pch_enable(crtc); |
c98e9dcf | 4801 | |
f9b61ff6 DV |
4802 | assert_vblank_disabled(crtc); |
4803 | drm_crtc_vblank_on(crtc); | |
4804 | ||
fa5c73b1 DV |
4805 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4806 | encoder->enable(encoder); | |
61b77ddd DV |
4807 | |
4808 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4809 | cpt_verify_modeset(dev, intel_crtc->pipe); |
37ca8d4c VS |
4810 | |
4811 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ | |
4812 | if (intel_crtc->config->has_pch_encoder) | |
4813 | intel_wait_for_vblank(dev, pipe); | |
4814 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
6be4a607 JB |
4815 | } |
4816 | ||
42db64ef PZ |
4817 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4818 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4819 | { | |
f5adf94e | 4820 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4821 | } |
4822 | ||
4f771f10 PZ |
4823 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4824 | { | |
4825 | struct drm_device *dev = crtc->dev; | |
4826 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4827 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4828 | struct intel_encoder *encoder; | |
99d736a2 | 4829 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4d1de975 | 4830 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
99d736a2 ML |
4831 | struct intel_crtc_state *pipe_config = |
4832 | to_intel_crtc_state(crtc->state); | |
4f771f10 | 4833 | |
53d9f4e9 | 4834 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
4835 | return; |
4836 | ||
81b088ca VS |
4837 | if (intel_crtc->config->has_pch_encoder) |
4838 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
4839 | false); | |
4840 | ||
8106ddbd | 4841 | if (intel_crtc->config->shared_dpll) |
df8ad70c DV |
4842 | intel_enable_shared_dpll(intel_crtc); |
4843 | ||
6e3c9717 | 4844 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4845 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 | 4846 | |
4d1de975 JN |
4847 | if (!intel_crtc->config->has_dsi_encoder) |
4848 | intel_set_pipe_timings(intel_crtc); | |
4849 | ||
bc58be60 | 4850 | intel_set_pipe_src_size(intel_crtc); |
229fca97 | 4851 | |
4d1de975 JN |
4852 | if (cpu_transcoder != TRANSCODER_EDP && |
4853 | !transcoder_is_dsi(cpu_transcoder)) { | |
4854 | I915_WRITE(PIPE_MULT(cpu_transcoder), | |
6e3c9717 | 4855 | intel_crtc->config->pixel_multiplier - 1); |
ebb69c95 CT |
4856 | } |
4857 | ||
6e3c9717 | 4858 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 4859 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4860 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
4861 | } |
4862 | ||
4d1de975 JN |
4863 | if (!intel_crtc->config->has_dsi_encoder) |
4864 | haswell_set_pipeconf(crtc); | |
4865 | ||
391bf048 | 4866 | haswell_set_pipemisc(crtc); |
229fca97 | 4867 | |
8563b1e8 | 4868 | intel_color_set_csc(crtc); |
229fca97 | 4869 | |
4f771f10 | 4870 | intel_crtc->active = true; |
8664281b | 4871 | |
6b698516 DV |
4872 | if (intel_crtc->config->has_pch_encoder) |
4873 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
4874 | else | |
4875 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4876 | ||
7d4aefd0 | 4877 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 PZ |
4878 | if (encoder->pre_enable) |
4879 | encoder->pre_enable(encoder); | |
7d4aefd0 | 4880 | } |
4f771f10 | 4881 | |
d2d65408 | 4882 | if (intel_crtc->config->has_pch_encoder) |
4fe9467d | 4883 | dev_priv->display.fdi_link_train(crtc); |
4fe9467d | 4884 | |
a65347ba | 4885 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 4886 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 4887 | |
1c132b44 | 4888 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 4889 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 4890 | else |
1c132b44 | 4891 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
4892 | |
4893 | /* | |
4894 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4895 | * clocks enabled | |
4896 | */ | |
8563b1e8 | 4897 | intel_color_load_luts(crtc); |
4f771f10 | 4898 | |
1f544388 | 4899 | intel_ddi_set_pipe_settings(crtc); |
a65347ba | 4900 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 4901 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 4902 | |
1d5bf5d9 ID |
4903 | if (dev_priv->display.initial_watermarks != NULL) |
4904 | dev_priv->display.initial_watermarks(pipe_config); | |
4905 | else | |
4906 | intel_update_watermarks(crtc); | |
4d1de975 JN |
4907 | |
4908 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ | |
4909 | if (!intel_crtc->config->has_dsi_encoder) | |
4910 | intel_enable_pipe(intel_crtc); | |
42db64ef | 4911 | |
6e3c9717 | 4912 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 4913 | lpt_pch_enable(crtc); |
4f771f10 | 4914 | |
a65347ba | 4915 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
4916 | intel_ddi_set_vc_payload_alloc(crtc, true); |
4917 | ||
f9b61ff6 DV |
4918 | assert_vblank_disabled(crtc); |
4919 | drm_crtc_vblank_on(crtc); | |
4920 | ||
8807e55b | 4921 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 4922 | encoder->enable(encoder); |
8807e55b JN |
4923 | intel_opregion_notify_encoder(encoder, true); |
4924 | } | |
4f771f10 | 4925 | |
6b698516 DV |
4926 | if (intel_crtc->config->has_pch_encoder) { |
4927 | intel_wait_for_vblank(dev, pipe); | |
4928 | intel_wait_for_vblank(dev, pipe); | |
4929 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
d2d65408 VS |
4930 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
4931 | true); | |
6b698516 | 4932 | } |
d2d65408 | 4933 | |
e4916946 PZ |
4934 | /* If we change the relative order between pipe/planes enabling, we need |
4935 | * to change the workaround. */ | |
99d736a2 ML |
4936 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
4937 | if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) { | |
4938 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
4939 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
4940 | } | |
4f771f10 PZ |
4941 | } |
4942 | ||
bfd16b2a | 4943 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
4944 | { |
4945 | struct drm_device *dev = crtc->base.dev; | |
4946 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4947 | int pipe = crtc->pipe; | |
4948 | ||
4949 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
4950 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 4951 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
4952 | I915_WRITE(PF_CTL(pipe), 0); |
4953 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
4954 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
4955 | } | |
4956 | } | |
4957 | ||
6be4a607 JB |
4958 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
4959 | { | |
4960 | struct drm_device *dev = crtc->dev; | |
4961 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4962 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4963 | struct intel_encoder *encoder; |
6be4a607 | 4964 | int pipe = intel_crtc->pipe; |
b52eb4dc | 4965 | |
37ca8d4c VS |
4966 | if (intel_crtc->config->has_pch_encoder) |
4967 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
4968 | ||
ea9d758d DV |
4969 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4970 | encoder->disable(encoder); | |
4971 | ||
f9b61ff6 DV |
4972 | drm_crtc_vblank_off(crtc); |
4973 | assert_vblank_disabled(crtc); | |
4974 | ||
3860b2ec VS |
4975 | /* |
4976 | * Sometimes spurious CPU pipe underruns happen when the | |
4977 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
4978 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
4979 | */ | |
4980 | if (intel_crtc->config->has_pch_encoder) | |
4981 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
4982 | ||
575f7ab7 | 4983 | intel_disable_pipe(intel_crtc); |
32f9d658 | 4984 | |
bfd16b2a | 4985 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 4986 | |
3860b2ec | 4987 | if (intel_crtc->config->has_pch_encoder) { |
5a74f70a | 4988 | ironlake_fdi_disable(crtc); |
3860b2ec VS |
4989 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4990 | } | |
5a74f70a | 4991 | |
bf49ec8c DV |
4992 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4993 | if (encoder->post_disable) | |
4994 | encoder->post_disable(encoder); | |
2c07245f | 4995 | |
6e3c9717 | 4996 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 4997 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 4998 | |
d925c59a | 4999 | if (HAS_PCH_CPT(dev)) { |
f0f59a00 VS |
5000 | i915_reg_t reg; |
5001 | u32 temp; | |
5002 | ||
d925c59a DV |
5003 | /* disable TRANS_DP_CTL */ |
5004 | reg = TRANS_DP_CTL(pipe); | |
5005 | temp = I915_READ(reg); | |
5006 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5007 | TRANS_DP_PORT_SEL_MASK); | |
5008 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5009 | I915_WRITE(reg, temp); | |
5010 | ||
5011 | /* disable DPLL_SEL */ | |
5012 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5013 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5014 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5015 | } |
e3421a18 | 5016 | |
d925c59a DV |
5017 | ironlake_fdi_pll_disable(intel_crtc); |
5018 | } | |
81b088ca VS |
5019 | |
5020 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
6be4a607 | 5021 | } |
1b3c7a47 | 5022 | |
4f771f10 | 5023 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 5024 | { |
4f771f10 PZ |
5025 | struct drm_device *dev = crtc->dev; |
5026 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 5027 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 5028 | struct intel_encoder *encoder; |
6e3c9717 | 5029 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5030 | |
d2d65408 VS |
5031 | if (intel_crtc->config->has_pch_encoder) |
5032 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5033 | false); | |
5034 | ||
8807e55b JN |
5035 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5036 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 5037 | encoder->disable(encoder); |
8807e55b | 5038 | } |
4f771f10 | 5039 | |
f9b61ff6 DV |
5040 | drm_crtc_vblank_off(crtc); |
5041 | assert_vblank_disabled(crtc); | |
5042 | ||
4d1de975 JN |
5043 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ |
5044 | if (!intel_crtc->config->has_dsi_encoder) | |
5045 | intel_disable_pipe(intel_crtc); | |
4f771f10 | 5046 | |
6e3c9717 | 5047 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
5048 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5049 | ||
a65347ba | 5050 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5051 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5052 | |
1c132b44 | 5053 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5054 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5055 | else |
bfd16b2a | 5056 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 5057 | |
a65347ba | 5058 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5059 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 5060 | |
97b040aa ID |
5061 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5062 | if (encoder->post_disable) | |
5063 | encoder->post_disable(encoder); | |
81b088ca | 5064 | |
92966a37 VS |
5065 | if (intel_crtc->config->has_pch_encoder) { |
5066 | lpt_disable_pch_transcoder(dev_priv); | |
503a74e9 | 5067 | lpt_disable_iclkip(dev_priv); |
92966a37 VS |
5068 | intel_ddi_fdi_disable(crtc); |
5069 | ||
81b088ca VS |
5070 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5071 | true); | |
92966a37 | 5072 | } |
4f771f10 PZ |
5073 | } |
5074 | ||
2dd24552 JB |
5075 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5076 | { | |
5077 | struct drm_device *dev = crtc->base.dev; | |
5078 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 5079 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5080 | |
681a8504 | 5081 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5082 | return; |
5083 | ||
2dd24552 | 5084 | /* |
c0b03411 DV |
5085 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5086 | * according to register description and PRM. | |
2dd24552 | 5087 | */ |
c0b03411 DV |
5088 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5089 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5090 | |
b074cec8 JB |
5091 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5092 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5093 | |
5094 | /* Border color in case we don't scale up to the full screen. Black by | |
5095 | * default, change to something else for debugging. */ | |
5096 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5097 | } |
5098 | ||
d05410f9 DA |
5099 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5100 | { | |
5101 | switch (port) { | |
5102 | case PORT_A: | |
6331a704 | 5103 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
d05410f9 | 5104 | case PORT_B: |
6331a704 | 5105 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
d05410f9 | 5106 | case PORT_C: |
6331a704 | 5107 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
d05410f9 | 5108 | case PORT_D: |
6331a704 | 5109 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
d8e19f99 | 5110 | case PORT_E: |
6331a704 | 5111 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
d05410f9 | 5112 | default: |
b9fec167 | 5113 | MISSING_CASE(port); |
d05410f9 DA |
5114 | return POWER_DOMAIN_PORT_OTHER; |
5115 | } | |
5116 | } | |
5117 | ||
25f78f58 VS |
5118 | static enum intel_display_power_domain port_to_aux_power_domain(enum port port) |
5119 | { | |
5120 | switch (port) { | |
5121 | case PORT_A: | |
5122 | return POWER_DOMAIN_AUX_A; | |
5123 | case PORT_B: | |
5124 | return POWER_DOMAIN_AUX_B; | |
5125 | case PORT_C: | |
5126 | return POWER_DOMAIN_AUX_C; | |
5127 | case PORT_D: | |
5128 | return POWER_DOMAIN_AUX_D; | |
5129 | case PORT_E: | |
5130 | /* FIXME: Check VBT for actual wiring of PORT E */ | |
5131 | return POWER_DOMAIN_AUX_D; | |
5132 | default: | |
b9fec167 | 5133 | MISSING_CASE(port); |
25f78f58 VS |
5134 | return POWER_DOMAIN_AUX_A; |
5135 | } | |
5136 | } | |
5137 | ||
319be8ae ID |
5138 | enum intel_display_power_domain |
5139 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5140 | { | |
5141 | struct drm_device *dev = intel_encoder->base.dev; | |
5142 | struct intel_digital_port *intel_dig_port; | |
5143 | ||
5144 | switch (intel_encoder->type) { | |
5145 | case INTEL_OUTPUT_UNKNOWN: | |
5146 | /* Only DDI platforms should ever use this output type */ | |
5147 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
5148 | case INTEL_OUTPUT_DISPLAYPORT: | |
5149 | case INTEL_OUTPUT_HDMI: | |
5150 | case INTEL_OUTPUT_EDP: | |
5151 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 5152 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
5153 | case INTEL_OUTPUT_DP_MST: |
5154 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5155 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
5156 | case INTEL_OUTPUT_ANALOG: |
5157 | return POWER_DOMAIN_PORT_CRT; | |
5158 | case INTEL_OUTPUT_DSI: | |
5159 | return POWER_DOMAIN_PORT_DSI; | |
5160 | default: | |
5161 | return POWER_DOMAIN_PORT_OTHER; | |
5162 | } | |
5163 | } | |
5164 | ||
25f78f58 VS |
5165 | enum intel_display_power_domain |
5166 | intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder) | |
5167 | { | |
5168 | struct drm_device *dev = intel_encoder->base.dev; | |
5169 | struct intel_digital_port *intel_dig_port; | |
5170 | ||
5171 | switch (intel_encoder->type) { | |
5172 | case INTEL_OUTPUT_UNKNOWN: | |
651174a4 ID |
5173 | case INTEL_OUTPUT_HDMI: |
5174 | /* | |
5175 | * Only DDI platforms should ever use these output types. | |
5176 | * We can get here after the HDMI detect code has already set | |
5177 | * the type of the shared encoder. Since we can't be sure | |
5178 | * what's the status of the given connectors, play safe and | |
5179 | * run the DP detection too. | |
5180 | */ | |
25f78f58 VS |
5181 | WARN_ON_ONCE(!HAS_DDI(dev)); |
5182 | case INTEL_OUTPUT_DISPLAYPORT: | |
5183 | case INTEL_OUTPUT_EDP: | |
5184 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
5185 | return port_to_aux_power_domain(intel_dig_port->port); | |
5186 | case INTEL_OUTPUT_DP_MST: | |
5187 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5188 | return port_to_aux_power_domain(intel_dig_port->port); | |
5189 | default: | |
b9fec167 | 5190 | MISSING_CASE(intel_encoder->type); |
25f78f58 VS |
5191 | return POWER_DOMAIN_AUX_A; |
5192 | } | |
5193 | } | |
5194 | ||
74bff5f9 ML |
5195 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc, |
5196 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5197 | { |
319be8ae | 5198 | struct drm_device *dev = crtc->dev; |
74bff5f9 | 5199 | struct drm_encoder *encoder; |
319be8ae ID |
5200 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5201 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca | 5202 | unsigned long mask; |
74bff5f9 | 5203 | enum transcoder transcoder = crtc_state->cpu_transcoder; |
77d22dca | 5204 | |
74bff5f9 | 5205 | if (!crtc_state->base.active) |
292b990e ML |
5206 | return 0; |
5207 | ||
77d22dca ID |
5208 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5209 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
74bff5f9 ML |
5210 | if (crtc_state->pch_pfit.enabled || |
5211 | crtc_state->pch_pfit.force_thru) | |
77d22dca ID |
5212 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5213 | ||
74bff5f9 ML |
5214 | drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) { |
5215 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
5216 | ||
319be8ae | 5217 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); |
74bff5f9 | 5218 | } |
319be8ae | 5219 | |
15e7ec29 ML |
5220 | if (crtc_state->shared_dpll) |
5221 | mask |= BIT(POWER_DOMAIN_PLLS); | |
5222 | ||
77d22dca ID |
5223 | return mask; |
5224 | } | |
5225 | ||
74bff5f9 ML |
5226 | static unsigned long |
5227 | modeset_get_crtc_power_domains(struct drm_crtc *crtc, | |
5228 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5229 | { |
292b990e ML |
5230 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
5231 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5232 | enum intel_display_power_domain domain; | |
5233 | unsigned long domains, new_domains, old_domains; | |
77d22dca | 5234 | |
292b990e | 5235 | old_domains = intel_crtc->enabled_power_domains; |
74bff5f9 ML |
5236 | intel_crtc->enabled_power_domains = new_domains = |
5237 | get_crtc_power_domains(crtc, crtc_state); | |
77d22dca | 5238 | |
292b990e ML |
5239 | domains = new_domains & ~old_domains; |
5240 | ||
5241 | for_each_power_domain(domain, domains) | |
5242 | intel_display_power_get(dev_priv, domain); | |
5243 | ||
5244 | return old_domains & ~new_domains; | |
5245 | } | |
5246 | ||
5247 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
5248 | unsigned long domains) | |
5249 | { | |
5250 | enum intel_display_power_domain domain; | |
5251 | ||
5252 | for_each_power_domain(domain, domains) | |
5253 | intel_display_power_put(dev_priv, domain); | |
5254 | } | |
77d22dca | 5255 | |
adafdc6f MK |
5256 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
5257 | { | |
5258 | int max_cdclk_freq = dev_priv->max_cdclk_freq; | |
5259 | ||
5260 | if (INTEL_INFO(dev_priv)->gen >= 9 || | |
5261 | IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
5262 | return max_cdclk_freq; | |
5263 | else if (IS_CHERRYVIEW(dev_priv)) | |
5264 | return max_cdclk_freq*95/100; | |
5265 | else if (INTEL_INFO(dev_priv)->gen < 4) | |
5266 | return 2*max_cdclk_freq*90/100; | |
5267 | else | |
5268 | return max_cdclk_freq*90/100; | |
5269 | } | |
5270 | ||
560a7ae4 DL |
5271 | static void intel_update_max_cdclk(struct drm_device *dev) |
5272 | { | |
5273 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5274 | ||
ef11bdb3 | 5275 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
560a7ae4 DL |
5276 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; |
5277 | ||
5278 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) | |
5279 | dev_priv->max_cdclk_freq = 675000; | |
5280 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) | |
5281 | dev_priv->max_cdclk_freq = 540000; | |
5282 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) | |
5283 | dev_priv->max_cdclk_freq = 450000; | |
5284 | else | |
5285 | dev_priv->max_cdclk_freq = 337500; | |
5286 | } else if (IS_BROADWELL(dev)) { | |
5287 | /* | |
5288 | * FIXME with extra cooling we can allow | |
5289 | * 540 MHz for ULX and 675 Mhz for ULT. | |
5290 | * How can we know if extra cooling is | |
5291 | * available? PCI ID, VTB, something else? | |
5292 | */ | |
5293 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
5294 | dev_priv->max_cdclk_freq = 450000; | |
5295 | else if (IS_BDW_ULX(dev)) | |
5296 | dev_priv->max_cdclk_freq = 450000; | |
5297 | else if (IS_BDW_ULT(dev)) | |
5298 | dev_priv->max_cdclk_freq = 540000; | |
5299 | else | |
5300 | dev_priv->max_cdclk_freq = 675000; | |
0904deaf MK |
5301 | } else if (IS_CHERRYVIEW(dev)) { |
5302 | dev_priv->max_cdclk_freq = 320000; | |
560a7ae4 DL |
5303 | } else if (IS_VALLEYVIEW(dev)) { |
5304 | dev_priv->max_cdclk_freq = 400000; | |
5305 | } else { | |
5306 | /* otherwise assume cdclk is fixed */ | |
5307 | dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; | |
5308 | } | |
5309 | ||
adafdc6f MK |
5310 | dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); |
5311 | ||
560a7ae4 DL |
5312 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", |
5313 | dev_priv->max_cdclk_freq); | |
adafdc6f MK |
5314 | |
5315 | DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", | |
5316 | dev_priv->max_dotclk_freq); | |
560a7ae4 DL |
5317 | } |
5318 | ||
5319 | static void intel_update_cdclk(struct drm_device *dev) | |
5320 | { | |
5321 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5322 | ||
5323 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
5324 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", | |
5325 | dev_priv->cdclk_freq); | |
5326 | ||
5327 | /* | |
5328 | * Program the gmbus_freq based on the cdclk frequency. | |
5329 | * BSpec erroneously claims we should aim for 4MHz, but | |
5330 | * in fact 1MHz is the correct frequency. | |
5331 | */ | |
666a4537 | 5332 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
560a7ae4 DL |
5333 | /* |
5334 | * Program the gmbus_freq based on the cdclk frequency. | |
5335 | * BSpec erroneously claims we should aim for 4MHz, but | |
5336 | * in fact 1MHz is the correct frequency. | |
5337 | */ | |
5338 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); | |
5339 | } | |
5340 | ||
5341 | if (dev_priv->max_cdclk_freq == 0) | |
5342 | intel_update_max_cdclk(dev); | |
5343 | } | |
5344 | ||
70d0c574 | 5345 | static void broxton_set_cdclk(struct drm_device *dev, int frequency) |
f8437dd1 VK |
5346 | { |
5347 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5348 | uint32_t divider; | |
5349 | uint32_t ratio; | |
5350 | uint32_t current_freq; | |
5351 | int ret; | |
5352 | ||
5353 | /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */ | |
5354 | switch (frequency) { | |
5355 | case 144000: | |
5356 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; | |
5357 | ratio = BXT_DE_PLL_RATIO(60); | |
5358 | break; | |
5359 | case 288000: | |
5360 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; | |
5361 | ratio = BXT_DE_PLL_RATIO(60); | |
5362 | break; | |
5363 | case 384000: | |
5364 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; | |
5365 | ratio = BXT_DE_PLL_RATIO(60); | |
5366 | break; | |
5367 | case 576000: | |
5368 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5369 | ratio = BXT_DE_PLL_RATIO(60); | |
5370 | break; | |
5371 | case 624000: | |
5372 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5373 | ratio = BXT_DE_PLL_RATIO(65); | |
5374 | break; | |
5375 | case 19200: | |
5376 | /* | |
5377 | * Bypass frequency with DE PLL disabled. Init ratio, divider | |
5378 | * to suppress GCC warning. | |
5379 | */ | |
5380 | ratio = 0; | |
5381 | divider = 0; | |
5382 | break; | |
5383 | default: | |
5384 | DRM_ERROR("unsupported CDCLK freq %d", frequency); | |
5385 | ||
5386 | return; | |
5387 | } | |
5388 | ||
5389 | mutex_lock(&dev_priv->rps.hw_lock); | |
5390 | /* Inform power controller of upcoming frequency change */ | |
5391 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5392 | 0x80000000); | |
5393 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5394 | ||
5395 | if (ret) { | |
5396 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
5397 | ret, frequency); | |
5398 | return; | |
5399 | } | |
5400 | ||
5401 | current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK; | |
5402 | /* convert from .1 fixpoint MHz with -1MHz offset to kHz */ | |
5403 | current_freq = current_freq * 500 + 1000; | |
5404 | ||
5405 | /* | |
5406 | * DE PLL has to be disabled when | |
5407 | * - setting to 19.2MHz (bypass, PLL isn't used) | |
5408 | * - before setting to 624MHz (PLL needs toggling) | |
5409 | * - before setting to any frequency from 624MHz (PLL needs toggling) | |
5410 | */ | |
5411 | if (frequency == 19200 || frequency == 624000 || | |
5412 | current_freq == 624000) { | |
5413 | I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE); | |
5414 | /* Timeout 200us */ | |
5415 | if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK), | |
5416 | 1)) | |
5417 | DRM_ERROR("timout waiting for DE PLL unlock\n"); | |
5418 | } | |
5419 | ||
5420 | if (frequency != 19200) { | |
5421 | uint32_t val; | |
5422 | ||
5423 | val = I915_READ(BXT_DE_PLL_CTL); | |
5424 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5425 | val |= ratio; | |
5426 | I915_WRITE(BXT_DE_PLL_CTL, val); | |
5427 | ||
5428 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5429 | /* Timeout 200us */ | |
5430 | if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1)) | |
5431 | DRM_ERROR("timeout waiting for DE PLL lock\n"); | |
5432 | ||
5433 | val = I915_READ(CDCLK_CTL); | |
5434 | val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK; | |
5435 | val |= divider; | |
5436 | /* | |
5437 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5438 | * enable otherwise. | |
5439 | */ | |
5440 | val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5441 | if (frequency >= 500000) | |
5442 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5443 | ||
5444 | val &= ~CDCLK_FREQ_DECIMAL_MASK; | |
5445 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ | |
5446 | val |= (frequency - 1000) / 500; | |
5447 | I915_WRITE(CDCLK_CTL, val); | |
5448 | } | |
5449 | ||
5450 | mutex_lock(&dev_priv->rps.hw_lock); | |
5451 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5452 | DIV_ROUND_UP(frequency, 25000)); | |
5453 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5454 | ||
5455 | if (ret) { | |
5456 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
5457 | ret, frequency); | |
5458 | return; | |
5459 | } | |
5460 | ||
a47871bd | 5461 | intel_update_cdclk(dev); |
f8437dd1 VK |
5462 | } |
5463 | ||
5464 | void broxton_init_cdclk(struct drm_device *dev) | |
5465 | { | |
5466 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5467 | uint32_t val; | |
5468 | ||
5469 | /* | |
5470 | * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT | |
5471 | * or else the reset will hang because there is no PCH to respond. | |
5472 | * Move the handshake programming to initialization sequence. | |
5473 | * Previously was left up to BIOS. | |
5474 | */ | |
5475 | val = I915_READ(HSW_NDE_RSTWRN_OPT); | |
5476 | val &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
5477 | I915_WRITE(HSW_NDE_RSTWRN_OPT, val); | |
5478 | ||
5479 | /* Enable PG1 for cdclk */ | |
5480 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); | |
5481 | ||
5482 | /* check if cd clock is enabled */ | |
5483 | if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) { | |
5484 | DRM_DEBUG_KMS("Display already initialized\n"); | |
5485 | return; | |
5486 | } | |
5487 | ||
5488 | /* | |
5489 | * FIXME: | |
5490 | * - The initial CDCLK needs to be read from VBT. | |
5491 | * Need to make this change after VBT has changes for BXT. | |
5492 | * - check if setting the max (or any) cdclk freq is really necessary | |
5493 | * here, it belongs to modeset time | |
5494 | */ | |
5495 | broxton_set_cdclk(dev, 624000); | |
5496 | ||
5497 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
22e02c0b VS |
5498 | POSTING_READ(DBUF_CTL); |
5499 | ||
f8437dd1 VK |
5500 | udelay(10); |
5501 | ||
5502 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5503 | DRM_ERROR("DBuf power enable timeout!\n"); | |
5504 | } | |
5505 | ||
5506 | void broxton_uninit_cdclk(struct drm_device *dev) | |
5507 | { | |
5508 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5509 | ||
5510 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
22e02c0b VS |
5511 | POSTING_READ(DBUF_CTL); |
5512 | ||
f8437dd1 VK |
5513 | udelay(10); |
5514 | ||
5515 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5516 | DRM_ERROR("DBuf power disable timeout!\n"); | |
5517 | ||
5518 | /* Set minimum (bypass) frequency, in effect turning off the DE PLL */ | |
5519 | broxton_set_cdclk(dev, 19200); | |
5520 | ||
5521 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
5522 | } | |
5523 | ||
5d96d8af DL |
5524 | static const struct skl_cdclk_entry { |
5525 | unsigned int freq; | |
5526 | unsigned int vco; | |
5527 | } skl_cdclk_frequencies[] = { | |
5528 | { .freq = 308570, .vco = 8640 }, | |
5529 | { .freq = 337500, .vco = 8100 }, | |
5530 | { .freq = 432000, .vco = 8640 }, | |
5531 | { .freq = 450000, .vco = 8100 }, | |
5532 | { .freq = 540000, .vco = 8100 }, | |
5533 | { .freq = 617140, .vco = 8640 }, | |
5534 | { .freq = 675000, .vco = 8100 }, | |
5535 | }; | |
5536 | ||
5537 | static unsigned int skl_cdclk_decimal(unsigned int freq) | |
5538 | { | |
5539 | return (freq - 1000) / 500; | |
5540 | } | |
5541 | ||
5542 | static unsigned int skl_cdclk_get_vco(unsigned int freq) | |
5543 | { | |
5544 | unsigned int i; | |
5545 | ||
5546 | for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) { | |
5547 | const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i]; | |
5548 | ||
5549 | if (e->freq == freq) | |
5550 | return e->vco; | |
5551 | } | |
5552 | ||
5553 | return 8100; | |
5554 | } | |
5555 | ||
5556 | static void | |
5557 | skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco) | |
5558 | { | |
5559 | unsigned int min_freq; | |
5560 | u32 val; | |
5561 | ||
5562 | /* select the minimum CDCLK before enabling DPLL 0 */ | |
5563 | val = I915_READ(CDCLK_CTL); | |
5564 | val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK; | |
5565 | val |= CDCLK_FREQ_337_308; | |
5566 | ||
5567 | if (required_vco == 8640) | |
5568 | min_freq = 308570; | |
5569 | else | |
5570 | min_freq = 337500; | |
5571 | ||
5572 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq); | |
5573 | ||
5574 | I915_WRITE(CDCLK_CTL, val); | |
5575 | POSTING_READ(CDCLK_CTL); | |
5576 | ||
5577 | /* | |
5578 | * We always enable DPLL0 with the lowest link rate possible, but still | |
5579 | * taking into account the VCO required to operate the eDP panel at the | |
5580 | * desired frequency. The usual DP link rates operate with a VCO of | |
5581 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. | |
5582 | * The modeset code is responsible for the selection of the exact link | |
5583 | * rate later on, with the constraint of choosing a frequency that | |
5584 | * works with required_vco. | |
5585 | */ | |
5586 | val = I915_READ(DPLL_CTRL1); | |
5587 | ||
5588 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
5589 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
5590 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
5591 | if (required_vco == 8640) | |
5592 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, | |
5593 | SKL_DPLL0); | |
5594 | else | |
5595 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, | |
5596 | SKL_DPLL0); | |
5597 | ||
5598 | I915_WRITE(DPLL_CTRL1, val); | |
5599 | POSTING_READ(DPLL_CTRL1); | |
5600 | ||
5601 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); | |
5602 | ||
5603 | if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5)) | |
5604 | DRM_ERROR("DPLL0 not locked\n"); | |
5605 | } | |
5606 | ||
5607 | static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) | |
5608 | { | |
5609 | int ret; | |
5610 | u32 val; | |
5611 | ||
5612 | /* inform PCU we want to change CDCLK */ | |
5613 | val = SKL_CDCLK_PREPARE_FOR_CHANGE; | |
5614 | mutex_lock(&dev_priv->rps.hw_lock); | |
5615 | ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); | |
5616 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5617 | ||
5618 | return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE); | |
5619 | } | |
5620 | ||
5621 | static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) | |
5622 | { | |
5623 | unsigned int i; | |
5624 | ||
5625 | for (i = 0; i < 15; i++) { | |
5626 | if (skl_cdclk_pcu_ready(dev_priv)) | |
5627 | return true; | |
5628 | udelay(10); | |
5629 | } | |
5630 | ||
5631 | return false; | |
5632 | } | |
5633 | ||
5634 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq) | |
5635 | { | |
560a7ae4 | 5636 | struct drm_device *dev = dev_priv->dev; |
5d96d8af DL |
5637 | u32 freq_select, pcu_ack; |
5638 | ||
5639 | DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq); | |
5640 | ||
5641 | if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { | |
5642 | DRM_ERROR("failed to inform PCU about cdclk change\n"); | |
5643 | return; | |
5644 | } | |
5645 | ||
5646 | /* set CDCLK_CTL */ | |
5647 | switch(freq) { | |
5648 | case 450000: | |
5649 | case 432000: | |
5650 | freq_select = CDCLK_FREQ_450_432; | |
5651 | pcu_ack = 1; | |
5652 | break; | |
5653 | case 540000: | |
5654 | freq_select = CDCLK_FREQ_540; | |
5655 | pcu_ack = 2; | |
5656 | break; | |
5657 | case 308570: | |
5658 | case 337500: | |
5659 | default: | |
5660 | freq_select = CDCLK_FREQ_337_308; | |
5661 | pcu_ack = 0; | |
5662 | break; | |
5663 | case 617140: | |
5664 | case 675000: | |
5665 | freq_select = CDCLK_FREQ_675_617; | |
5666 | pcu_ack = 3; | |
5667 | break; | |
5668 | } | |
5669 | ||
5670 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq)); | |
5671 | POSTING_READ(CDCLK_CTL); | |
5672 | ||
5673 | /* inform PCU of the change */ | |
5674 | mutex_lock(&dev_priv->rps.hw_lock); | |
5675 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); | |
5676 | mutex_unlock(&dev_priv->rps.hw_lock); | |
560a7ae4 DL |
5677 | |
5678 | intel_update_cdclk(dev); | |
5d96d8af DL |
5679 | } |
5680 | ||
5681 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) | |
5682 | { | |
5683 | /* disable DBUF power */ | |
5684 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
5685 | POSTING_READ(DBUF_CTL); | |
5686 | ||
5687 | udelay(10); | |
5688 | ||
5689 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5690 | DRM_ERROR("DBuf power disable timeout\n"); | |
5691 | ||
ab96c1ee ID |
5692 | /* disable DPLL0 */ |
5693 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); | |
5694 | if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) | |
5695 | DRM_ERROR("Couldn't disable DPLL0\n"); | |
5d96d8af DL |
5696 | } |
5697 | ||
5698 | void skl_init_cdclk(struct drm_i915_private *dev_priv) | |
5699 | { | |
5d96d8af DL |
5700 | unsigned int required_vco; |
5701 | ||
39d9b85a GW |
5702 | /* DPLL0 not enabled (happens on early BIOS versions) */ |
5703 | if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) { | |
5704 | /* enable DPLL0 */ | |
5705 | required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk); | |
5706 | skl_dpll0_enable(dev_priv, required_vco); | |
5d96d8af DL |
5707 | } |
5708 | ||
5d96d8af DL |
5709 | /* set CDCLK to the frequency the BIOS chose */ |
5710 | skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk); | |
5711 | ||
5712 | /* enable DBUF power */ | |
5713 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
5714 | POSTING_READ(DBUF_CTL); | |
5715 | ||
5716 | udelay(10); | |
5717 | ||
5718 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5719 | DRM_ERROR("DBuf power enable timeout\n"); | |
5720 | } | |
5721 | ||
c73666f3 SK |
5722 | int skl_sanitize_cdclk(struct drm_i915_private *dev_priv) |
5723 | { | |
5724 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
5725 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
5726 | int freq = dev_priv->skl_boot_cdclk; | |
5727 | ||
f1b391a5 SK |
5728 | /* |
5729 | * check if the pre-os intialized the display | |
5730 | * There is SWF18 scratchpad register defined which is set by the | |
5731 | * pre-os which can be used by the OS drivers to check the status | |
5732 | */ | |
5733 | if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) | |
5734 | goto sanitize; | |
5735 | ||
c73666f3 SK |
5736 | /* Is PLL enabled and locked ? */ |
5737 | if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK))) | |
5738 | goto sanitize; | |
5739 | ||
5740 | /* DPLL okay; verify the cdclock | |
5741 | * | |
5742 | * Noticed in some instances that the freq selection is correct but | |
5743 | * decimal part is programmed wrong from BIOS where pre-os does not | |
5744 | * enable display. Verify the same as well. | |
5745 | */ | |
5746 | if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq))) | |
5747 | /* All well; nothing to sanitize */ | |
5748 | return false; | |
5749 | sanitize: | |
5750 | /* | |
5751 | * As of now initialize with max cdclk till | |
5752 | * we get dynamic cdclk support | |
5753 | * */ | |
5754 | dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq; | |
5755 | skl_init_cdclk(dev_priv); | |
5756 | ||
5757 | /* we did have to sanitize */ | |
5758 | return true; | |
5759 | } | |
5760 | ||
30a970c6 JB |
5761 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
5762 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
5763 | { | |
5764 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5765 | u32 val, cmd; | |
5766 | ||
164dfd28 VK |
5767 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5768 | != dev_priv->cdclk_freq); | |
d60c4473 | 5769 | |
dfcab17e | 5770 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 5771 | cmd = 2; |
dfcab17e | 5772 | else if (cdclk == 266667) |
30a970c6 JB |
5773 | cmd = 1; |
5774 | else | |
5775 | cmd = 0; | |
5776 | ||
5777 | mutex_lock(&dev_priv->rps.hw_lock); | |
5778 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5779 | val &= ~DSPFREQGUAR_MASK; | |
5780 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
5781 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5782 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5783 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
5784 | 50)) { | |
5785 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5786 | } | |
5787 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5788 | ||
54433e91 VS |
5789 | mutex_lock(&dev_priv->sb_lock); |
5790 | ||
dfcab17e | 5791 | if (cdclk == 400000) { |
6bcda4f0 | 5792 | u32 divider; |
30a970c6 | 5793 | |
6bcda4f0 | 5794 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 | 5795 | |
30a970c6 JB |
5796 | /* adjust cdclk divider */ |
5797 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
87d5d259 | 5798 | val &= ~CCK_FREQUENCY_VALUES; |
30a970c6 JB |
5799 | val |= divider; |
5800 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
5801 | |
5802 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
87d5d259 | 5803 | CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), |
a877e801 VS |
5804 | 50)) |
5805 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
5806 | } |
5807 | ||
30a970c6 JB |
5808 | /* adjust self-refresh exit latency value */ |
5809 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
5810 | val &= ~0x7f; | |
5811 | ||
5812 | /* | |
5813 | * For high bandwidth configs, we set a higher latency in the bunit | |
5814 | * so that the core display fetch happens in time to avoid underruns. | |
5815 | */ | |
dfcab17e | 5816 | if (cdclk == 400000) |
30a970c6 JB |
5817 | val |= 4500 / 250; /* 4.5 usec */ |
5818 | else | |
5819 | val |= 3000 / 250; /* 3.0 usec */ | |
5820 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
54433e91 | 5821 | |
a580516d | 5822 | mutex_unlock(&dev_priv->sb_lock); |
30a970c6 | 5823 | |
b6283055 | 5824 | intel_update_cdclk(dev); |
30a970c6 JB |
5825 | } |
5826 | ||
383c5a6a VS |
5827 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
5828 | { | |
5829 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5830 | u32 val, cmd; | |
5831 | ||
164dfd28 VK |
5832 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5833 | != dev_priv->cdclk_freq); | |
383c5a6a VS |
5834 | |
5835 | switch (cdclk) { | |
383c5a6a VS |
5836 | case 333333: |
5837 | case 320000: | |
383c5a6a | 5838 | case 266667: |
383c5a6a | 5839 | case 200000: |
383c5a6a VS |
5840 | break; |
5841 | default: | |
5f77eeb0 | 5842 | MISSING_CASE(cdclk); |
383c5a6a VS |
5843 | return; |
5844 | } | |
5845 | ||
9d0d3fda VS |
5846 | /* |
5847 | * Specs are full of misinformation, but testing on actual | |
5848 | * hardware has shown that we just need to write the desired | |
5849 | * CCK divider into the Punit register. | |
5850 | */ | |
5851 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
5852 | ||
383c5a6a VS |
5853 | mutex_lock(&dev_priv->rps.hw_lock); |
5854 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5855 | val &= ~DSPFREQGUAR_MASK_CHV; | |
5856 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
5857 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5858 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5859 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
5860 | 50)) { | |
5861 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5862 | } | |
5863 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5864 | ||
b6283055 | 5865 | intel_update_cdclk(dev); |
383c5a6a VS |
5866 | } |
5867 | ||
30a970c6 JB |
5868 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
5869 | int max_pixclk) | |
5870 | { | |
6bcda4f0 | 5871 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 5872 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 5873 | |
30a970c6 JB |
5874 | /* |
5875 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
5876 | * 200MHz | |
5877 | * 267MHz | |
29dc7ef3 | 5878 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
5879 | * 400MHz (VLV only) |
5880 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
5881 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
5882 | * |
5883 | * We seem to get an unstable or solid color picture at 200MHz. | |
5884 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
5885 | * are off. | |
30a970c6 | 5886 | */ |
6cca3195 VS |
5887 | if (!IS_CHERRYVIEW(dev_priv) && |
5888 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 5889 | return 400000; |
6cca3195 | 5890 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 5891 | return freq_320; |
e37c67a1 | 5892 | else if (max_pixclk > 0) |
dfcab17e | 5893 | return 266667; |
e37c67a1 VS |
5894 | else |
5895 | return 200000; | |
30a970c6 JB |
5896 | } |
5897 | ||
f8437dd1 VK |
5898 | static int broxton_calc_cdclk(struct drm_i915_private *dev_priv, |
5899 | int max_pixclk) | |
5900 | { | |
5901 | /* | |
5902 | * FIXME: | |
5903 | * - remove the guardband, it's not needed on BXT | |
5904 | * - set 19.2MHz bypass frequency if there are no active pipes | |
5905 | */ | |
5906 | if (max_pixclk > 576000*9/10) | |
5907 | return 624000; | |
5908 | else if (max_pixclk > 384000*9/10) | |
5909 | return 576000; | |
5910 | else if (max_pixclk > 288000*9/10) | |
5911 | return 384000; | |
5912 | else if (max_pixclk > 144000*9/10) | |
5913 | return 288000; | |
5914 | else | |
5915 | return 144000; | |
5916 | } | |
5917 | ||
e8788cbc | 5918 | /* Compute the max pixel clock for new configuration. */ |
a821fc46 ACO |
5919 | static int intel_mode_max_pixclk(struct drm_device *dev, |
5920 | struct drm_atomic_state *state) | |
30a970c6 | 5921 | { |
565602d7 ML |
5922 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
5923 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5924 | struct drm_crtc *crtc; | |
5925 | struct drm_crtc_state *crtc_state; | |
5926 | unsigned max_pixclk = 0, i; | |
5927 | enum pipe pipe; | |
30a970c6 | 5928 | |
565602d7 ML |
5929 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
5930 | sizeof(intel_state->min_pixclk)); | |
304603f4 | 5931 | |
565602d7 ML |
5932 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
5933 | int pixclk = 0; | |
5934 | ||
5935 | if (crtc_state->enable) | |
5936 | pixclk = crtc_state->adjusted_mode.crtc_clock; | |
304603f4 | 5937 | |
565602d7 | 5938 | intel_state->min_pixclk[i] = pixclk; |
30a970c6 JB |
5939 | } |
5940 | ||
565602d7 ML |
5941 | for_each_pipe(dev_priv, pipe) |
5942 | max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk); | |
5943 | ||
30a970c6 JB |
5944 | return max_pixclk; |
5945 | } | |
5946 | ||
27c329ed | 5947 | static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) |
30a970c6 | 5948 | { |
27c329ed ML |
5949 | struct drm_device *dev = state->dev; |
5950 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5951 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
1a617b77 ML |
5952 | struct intel_atomic_state *intel_state = |
5953 | to_intel_atomic_state(state); | |
30a970c6 | 5954 | |
304603f4 ACO |
5955 | if (max_pixclk < 0) |
5956 | return max_pixclk; | |
30a970c6 | 5957 | |
1a617b77 | 5958 | intel_state->cdclk = intel_state->dev_cdclk = |
27c329ed | 5959 | valleyview_calc_cdclk(dev_priv, max_pixclk); |
0a9ab303 | 5960 | |
1a617b77 ML |
5961 | if (!intel_state->active_crtcs) |
5962 | intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0); | |
5963 | ||
27c329ed ML |
5964 | return 0; |
5965 | } | |
304603f4 | 5966 | |
27c329ed ML |
5967 | static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state) |
5968 | { | |
5969 | struct drm_device *dev = state->dev; | |
5970 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5971 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
1a617b77 ML |
5972 | struct intel_atomic_state *intel_state = |
5973 | to_intel_atomic_state(state); | |
85a96e7a | 5974 | |
27c329ed ML |
5975 | if (max_pixclk < 0) |
5976 | return max_pixclk; | |
85a96e7a | 5977 | |
1a617b77 | 5978 | intel_state->cdclk = intel_state->dev_cdclk = |
27c329ed | 5979 | broxton_calc_cdclk(dev_priv, max_pixclk); |
85a96e7a | 5980 | |
1a617b77 ML |
5981 | if (!intel_state->active_crtcs) |
5982 | intel_state->dev_cdclk = broxton_calc_cdclk(dev_priv, 0); | |
5983 | ||
27c329ed | 5984 | return 0; |
30a970c6 JB |
5985 | } |
5986 | ||
1e69cd74 VS |
5987 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
5988 | { | |
5989 | unsigned int credits, default_credits; | |
5990 | ||
5991 | if (IS_CHERRYVIEW(dev_priv)) | |
5992 | default_credits = PFI_CREDIT(12); | |
5993 | else | |
5994 | default_credits = PFI_CREDIT(8); | |
5995 | ||
bfa7df01 | 5996 | if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) { |
1e69cd74 VS |
5997 | /* CHV suggested value is 31 or 63 */ |
5998 | if (IS_CHERRYVIEW(dev_priv)) | |
fcc0008f | 5999 | credits = PFI_CREDIT_63; |
1e69cd74 VS |
6000 | else |
6001 | credits = PFI_CREDIT(15); | |
6002 | } else { | |
6003 | credits = default_credits; | |
6004 | } | |
6005 | ||
6006 | /* | |
6007 | * WA - write default credits before re-programming | |
6008 | * FIXME: should we also set the resend bit here? | |
6009 | */ | |
6010 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6011 | default_credits); | |
6012 | ||
6013 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6014 | credits | PFI_CREDIT_RESEND); | |
6015 | ||
6016 | /* | |
6017 | * FIXME is this guaranteed to clear | |
6018 | * immediately or should we poll for it? | |
6019 | */ | |
6020 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
6021 | } | |
6022 | ||
27c329ed | 6023 | static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
30a970c6 | 6024 | { |
a821fc46 | 6025 | struct drm_device *dev = old_state->dev; |
30a970c6 | 6026 | struct drm_i915_private *dev_priv = dev->dev_private; |
1a617b77 ML |
6027 | struct intel_atomic_state *old_intel_state = |
6028 | to_intel_atomic_state(old_state); | |
6029 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
30a970c6 | 6030 | |
27c329ed ML |
6031 | /* |
6032 | * FIXME: We can end up here with all power domains off, yet | |
6033 | * with a CDCLK frequency other than the minimum. To account | |
6034 | * for this take the PIPE-A power domain, which covers the HW | |
6035 | * blocks needed for the following programming. This can be | |
6036 | * removed once it's guaranteed that we get here either with | |
6037 | * the minimum CDCLK set, or the required power domains | |
6038 | * enabled. | |
6039 | */ | |
6040 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
738c05c0 | 6041 | |
27c329ed ML |
6042 | if (IS_CHERRYVIEW(dev)) |
6043 | cherryview_set_cdclk(dev, req_cdclk); | |
6044 | else | |
6045 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 6046 | |
27c329ed | 6047 | vlv_program_pfi_credits(dev_priv); |
1e69cd74 | 6048 | |
27c329ed | 6049 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
30a970c6 JB |
6050 | } |
6051 | ||
89b667f8 JB |
6052 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
6053 | { | |
6054 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6055 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
6056 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6057 | struct intel_encoder *encoder; | |
6058 | int pipe = intel_crtc->pipe; | |
89b667f8 | 6059 | |
53d9f4e9 | 6060 | if (WARN_ON(intel_crtc->active)) |
89b667f8 JB |
6061 | return; |
6062 | ||
6e3c9717 | 6063 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6064 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6065 | |
6066 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 6067 | intel_set_pipe_src_size(intel_crtc); |
5b18e57c | 6068 | |
c14b0485 VS |
6069 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
6070 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6071 | ||
6072 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
6073 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
6074 | } | |
6075 | ||
5b18e57c DV |
6076 | i9xx_set_pipeconf(intel_crtc); |
6077 | ||
89b667f8 | 6078 | intel_crtc->active = true; |
89b667f8 | 6079 | |
a72e4c9f | 6080 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6081 | |
89b667f8 JB |
6082 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6083 | if (encoder->pre_pll_enable) | |
6084 | encoder->pre_pll_enable(encoder); | |
6085 | ||
a65347ba | 6086 | if (!intel_crtc->config->has_dsi_encoder) { |
c0b4c660 VS |
6087 | if (IS_CHERRYVIEW(dev)) { |
6088 | chv_prepare_pll(intel_crtc, intel_crtc->config); | |
6e3c9717 | 6089 | chv_enable_pll(intel_crtc, intel_crtc->config); |
c0b4c660 VS |
6090 | } else { |
6091 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
6e3c9717 | 6092 | vlv_enable_pll(intel_crtc, intel_crtc->config); |
c0b4c660 | 6093 | } |
9d556c99 | 6094 | } |
89b667f8 JB |
6095 | |
6096 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
6097 | if (encoder->pre_enable) | |
6098 | encoder->pre_enable(encoder); | |
6099 | ||
2dd24552 JB |
6100 | i9xx_pfit_enable(intel_crtc); |
6101 | ||
8563b1e8 | 6102 | intel_color_load_luts(crtc); |
63cbb074 | 6103 | |
caed361d | 6104 | intel_update_watermarks(crtc); |
e1fdc473 | 6105 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6106 | |
4b3a9526 VS |
6107 | assert_vblank_disabled(crtc); |
6108 | drm_crtc_vblank_on(crtc); | |
6109 | ||
f9b61ff6 DV |
6110 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6111 | encoder->enable(encoder); | |
89b667f8 JB |
6112 | } |
6113 | ||
f13c2ef3 DV |
6114 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
6115 | { | |
6116 | struct drm_device *dev = crtc->base.dev; | |
6117 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6118 | ||
6e3c9717 ACO |
6119 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
6120 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
6121 | } |
6122 | ||
0b8765c6 | 6123 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
6124 | { |
6125 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6126 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 6127 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 6128 | struct intel_encoder *encoder; |
79e53945 | 6129 | int pipe = intel_crtc->pipe; |
79e53945 | 6130 | |
53d9f4e9 | 6131 | if (WARN_ON(intel_crtc->active)) |
f7abfe8b CW |
6132 | return; |
6133 | ||
f13c2ef3 DV |
6134 | i9xx_set_pll_dividers(intel_crtc); |
6135 | ||
6e3c9717 | 6136 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6137 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6138 | |
6139 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 6140 | intel_set_pipe_src_size(intel_crtc); |
5b18e57c | 6141 | |
5b18e57c DV |
6142 | i9xx_set_pipeconf(intel_crtc); |
6143 | ||
f7abfe8b | 6144 | intel_crtc->active = true; |
6b383a7f | 6145 | |
4a3436e8 | 6146 | if (!IS_GEN2(dev)) |
a72e4c9f | 6147 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6148 | |
9d6d9f19 MK |
6149 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6150 | if (encoder->pre_enable) | |
6151 | encoder->pre_enable(encoder); | |
6152 | ||
f6736a1a DV |
6153 | i9xx_enable_pll(intel_crtc); |
6154 | ||
2dd24552 JB |
6155 | i9xx_pfit_enable(intel_crtc); |
6156 | ||
8563b1e8 | 6157 | intel_color_load_luts(crtc); |
63cbb074 | 6158 | |
f37fcc2a | 6159 | intel_update_watermarks(crtc); |
e1fdc473 | 6160 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6161 | |
4b3a9526 VS |
6162 | assert_vblank_disabled(crtc); |
6163 | drm_crtc_vblank_on(crtc); | |
6164 | ||
f9b61ff6 DV |
6165 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6166 | encoder->enable(encoder); | |
0b8765c6 | 6167 | } |
79e53945 | 6168 | |
87476d63 DV |
6169 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
6170 | { | |
6171 | struct drm_device *dev = crtc->base.dev; | |
6172 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 6173 | |
6e3c9717 | 6174 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 6175 | return; |
87476d63 | 6176 | |
328d8e82 | 6177 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 6178 | |
328d8e82 DV |
6179 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
6180 | I915_READ(PFIT_CONTROL)); | |
6181 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
6182 | } |
6183 | ||
0b8765c6 JB |
6184 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
6185 | { | |
6186 | struct drm_device *dev = crtc->dev; | |
6187 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6188 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 6189 | struct intel_encoder *encoder; |
0b8765c6 | 6190 | int pipe = intel_crtc->pipe; |
ef9c3aee | 6191 | |
6304cd91 VS |
6192 | /* |
6193 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
6194 | * wait for planes to fully turn off before disabling the pipe. | |
6195 | */ | |
90e83e53 ACO |
6196 | if (IS_GEN2(dev)) |
6197 | intel_wait_for_vblank(dev, pipe); | |
6304cd91 | 6198 | |
4b3a9526 VS |
6199 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6200 | encoder->disable(encoder); | |
6201 | ||
f9b61ff6 DV |
6202 | drm_crtc_vblank_off(crtc); |
6203 | assert_vblank_disabled(crtc); | |
6204 | ||
575f7ab7 | 6205 | intel_disable_pipe(intel_crtc); |
24a1f16d | 6206 | |
87476d63 | 6207 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 6208 | |
89b667f8 JB |
6209 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6210 | if (encoder->post_disable) | |
6211 | encoder->post_disable(encoder); | |
6212 | ||
a65347ba | 6213 | if (!intel_crtc->config->has_dsi_encoder) { |
076ed3b2 CML |
6214 | if (IS_CHERRYVIEW(dev)) |
6215 | chv_disable_pll(dev_priv, pipe); | |
6216 | else if (IS_VALLEYVIEW(dev)) | |
6217 | vlv_disable_pll(dev_priv, pipe); | |
6218 | else | |
1c4e0274 | 6219 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 6220 | } |
0b8765c6 | 6221 | |
d6db995f VS |
6222 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6223 | if (encoder->post_pll_disable) | |
6224 | encoder->post_pll_disable(encoder); | |
6225 | ||
4a3436e8 | 6226 | if (!IS_GEN2(dev)) |
a72e4c9f | 6227 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
0b8765c6 JB |
6228 | } |
6229 | ||
b17d48e2 ML |
6230 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
6231 | { | |
842e0307 | 6232 | struct intel_encoder *encoder; |
b17d48e2 ML |
6233 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6234 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
6235 | enum intel_display_power_domain domain; | |
6236 | unsigned long domains; | |
6237 | ||
6238 | if (!intel_crtc->active) | |
6239 | return; | |
6240 | ||
a539205a | 6241 | if (to_intel_plane_state(crtc->primary->state)->visible) { |
fc32b1fd ML |
6242 | WARN_ON(intel_crtc->unpin_work); |
6243 | ||
2622a081 | 6244 | intel_pre_disable_primary_noatomic(crtc); |
54a41961 ML |
6245 | |
6246 | intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); | |
6247 | to_intel_plane_state(crtc->primary->state)->visible = false; | |
a539205a ML |
6248 | } |
6249 | ||
b17d48e2 | 6250 | dev_priv->display.crtc_disable(crtc); |
842e0307 ML |
6251 | |
6252 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was enabled, now disabled\n", | |
6253 | crtc->base.id); | |
6254 | ||
6255 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0); | |
6256 | crtc->state->active = false; | |
37d9078b | 6257 | intel_crtc->active = false; |
842e0307 ML |
6258 | crtc->enabled = false; |
6259 | crtc->state->connector_mask = 0; | |
6260 | crtc->state->encoder_mask = 0; | |
6261 | ||
6262 | for_each_encoder_on_crtc(crtc->dev, crtc, encoder) | |
6263 | encoder->base.crtc = NULL; | |
6264 | ||
58f9c0bc | 6265 | intel_fbc_disable(intel_crtc); |
37d9078b | 6266 | intel_update_watermarks(crtc); |
1f7457b1 | 6267 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
6268 | |
6269 | domains = intel_crtc->enabled_power_domains; | |
6270 | for_each_power_domain(domain, domains) | |
6271 | intel_display_power_put(dev_priv, domain); | |
6272 | intel_crtc->enabled_power_domains = 0; | |
565602d7 ML |
6273 | |
6274 | dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); | |
6275 | dev_priv->min_pixclk[intel_crtc->pipe] = 0; | |
b17d48e2 ML |
6276 | } |
6277 | ||
6b72d486 ML |
6278 | /* |
6279 | * turn all crtc's off, but do not adjust state | |
6280 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
6281 | */ | |
70e0bd74 | 6282 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 6283 | { |
e2c8b870 | 6284 | struct drm_i915_private *dev_priv = to_i915(dev); |
70e0bd74 | 6285 | struct drm_atomic_state *state; |
e2c8b870 | 6286 | int ret; |
70e0bd74 | 6287 | |
e2c8b870 ML |
6288 | state = drm_atomic_helper_suspend(dev); |
6289 | ret = PTR_ERR_OR_ZERO(state); | |
70e0bd74 ML |
6290 | if (ret) |
6291 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
e2c8b870 ML |
6292 | else |
6293 | dev_priv->modeset_restore_state = state; | |
70e0bd74 | 6294 | return ret; |
ee7b9f93 JB |
6295 | } |
6296 | ||
ea5b213a | 6297 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6298 | { |
4ef69c7a | 6299 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6300 | |
ea5b213a CW |
6301 | drm_encoder_cleanup(encoder); |
6302 | kfree(intel_encoder); | |
7e7d76c3 JB |
6303 | } |
6304 | ||
0a91ca29 DV |
6305 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6306 | * internal consistency). */ | |
b980514c | 6307 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 6308 | { |
35dd3c64 ML |
6309 | struct drm_crtc *crtc = connector->base.state->crtc; |
6310 | ||
6311 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6312 | connector->base.base.id, | |
6313 | connector->base.name); | |
6314 | ||
0a91ca29 | 6315 | if (connector->get_hw_state(connector)) { |
e85376cb | 6316 | struct intel_encoder *encoder = connector->encoder; |
35dd3c64 | 6317 | struct drm_connector_state *conn_state = connector->base.state; |
0a91ca29 | 6318 | |
35dd3c64 ML |
6319 | I915_STATE_WARN(!crtc, |
6320 | "connector enabled without attached crtc\n"); | |
0a91ca29 | 6321 | |
35dd3c64 ML |
6322 | if (!crtc) |
6323 | return; | |
6324 | ||
6325 | I915_STATE_WARN(!crtc->state->active, | |
6326 | "connector is active, but attached crtc isn't\n"); | |
6327 | ||
e85376cb | 6328 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
6329 | return; |
6330 | ||
e85376cb | 6331 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
6332 | "atomic encoder doesn't match attached encoder\n"); |
6333 | ||
e85376cb | 6334 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
6335 | "attached encoder crtc differs from connector crtc\n"); |
6336 | } else { | |
4d688a2a ML |
6337 | I915_STATE_WARN(crtc && crtc->state->active, |
6338 | "attached crtc is active, but connector isn't\n"); | |
35dd3c64 ML |
6339 | I915_STATE_WARN(!crtc && connector->base.state->best_encoder, |
6340 | "best encoder set without crtc!\n"); | |
0a91ca29 | 6341 | } |
79e53945 JB |
6342 | } |
6343 | ||
08d9bc92 ACO |
6344 | int intel_connector_init(struct intel_connector *connector) |
6345 | { | |
5350a031 | 6346 | drm_atomic_helper_connector_reset(&connector->base); |
08d9bc92 | 6347 | |
5350a031 | 6348 | if (!connector->base.state) |
08d9bc92 ACO |
6349 | return -ENOMEM; |
6350 | ||
08d9bc92 ACO |
6351 | return 0; |
6352 | } | |
6353 | ||
6354 | struct intel_connector *intel_connector_alloc(void) | |
6355 | { | |
6356 | struct intel_connector *connector; | |
6357 | ||
6358 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6359 | if (!connector) | |
6360 | return NULL; | |
6361 | ||
6362 | if (intel_connector_init(connector) < 0) { | |
6363 | kfree(connector); | |
6364 | return NULL; | |
6365 | } | |
6366 | ||
6367 | return connector; | |
6368 | } | |
6369 | ||
f0947c37 DV |
6370 | /* Simple connector->get_hw_state implementation for encoders that support only |
6371 | * one connector and no cloning and hence the encoder state determines the state | |
6372 | * of the connector. */ | |
6373 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6374 | { |
24929352 | 6375 | enum pipe pipe = 0; |
f0947c37 | 6376 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6377 | |
f0947c37 | 6378 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6379 | } |
6380 | ||
6d293983 | 6381 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6382 | { |
6d293983 ACO |
6383 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6384 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6385 | |
6386 | return 0; | |
6387 | } | |
6388 | ||
6d293983 | 6389 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6390 | struct intel_crtc_state *pipe_config) |
1857e1da | 6391 | { |
6d293983 ACO |
6392 | struct drm_atomic_state *state = pipe_config->base.state; |
6393 | struct intel_crtc *other_crtc; | |
6394 | struct intel_crtc_state *other_crtc_state; | |
6395 | ||
1857e1da DV |
6396 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6397 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6398 | if (pipe_config->fdi_lanes > 4) { | |
6399 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6400 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6401 | return -EINVAL; |
1857e1da DV |
6402 | } |
6403 | ||
bafb6553 | 6404 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
6405 | if (pipe_config->fdi_lanes > 2) { |
6406 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6407 | pipe_config->fdi_lanes); | |
6d293983 | 6408 | return -EINVAL; |
1857e1da | 6409 | } else { |
6d293983 | 6410 | return 0; |
1857e1da DV |
6411 | } |
6412 | } | |
6413 | ||
6414 | if (INTEL_INFO(dev)->num_pipes == 2) | |
6d293983 | 6415 | return 0; |
1857e1da DV |
6416 | |
6417 | /* Ivybridge 3 pipe is really complicated */ | |
6418 | switch (pipe) { | |
6419 | case PIPE_A: | |
6d293983 | 6420 | return 0; |
1857e1da | 6421 | case PIPE_B: |
6d293983 ACO |
6422 | if (pipe_config->fdi_lanes <= 2) |
6423 | return 0; | |
6424 | ||
6425 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); | |
6426 | other_crtc_state = | |
6427 | intel_atomic_get_crtc_state(state, other_crtc); | |
6428 | if (IS_ERR(other_crtc_state)) | |
6429 | return PTR_ERR(other_crtc_state); | |
6430 | ||
6431 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6432 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6433 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6434 | return -EINVAL; |
1857e1da | 6435 | } |
6d293983 | 6436 | return 0; |
1857e1da | 6437 | case PIPE_C: |
251cc67c VS |
6438 | if (pipe_config->fdi_lanes > 2) { |
6439 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6440 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6441 | return -EINVAL; |
251cc67c | 6442 | } |
6d293983 ACO |
6443 | |
6444 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); | |
6445 | other_crtc_state = | |
6446 | intel_atomic_get_crtc_state(state, other_crtc); | |
6447 | if (IS_ERR(other_crtc_state)) | |
6448 | return PTR_ERR(other_crtc_state); | |
6449 | ||
6450 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6451 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6452 | return -EINVAL; |
1857e1da | 6453 | } |
6d293983 | 6454 | return 0; |
1857e1da DV |
6455 | default: |
6456 | BUG(); | |
6457 | } | |
6458 | } | |
6459 | ||
e29c22c0 DV |
6460 | #define RETRY 1 |
6461 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6462 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6463 | { |
1857e1da | 6464 | struct drm_device *dev = intel_crtc->base.dev; |
7c5f93b0 | 6465 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6466 | int lane, link_bw, fdi_dotclock, ret; |
6467 | bool needs_recompute = false; | |
877d48d5 | 6468 | |
e29c22c0 | 6469 | retry: |
877d48d5 DV |
6470 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6471 | * each output octet as 10 bits. The actual frequency | |
6472 | * is stored as a divider into a 100MHz clock, and the | |
6473 | * mode pixel clock is stored in units of 1KHz. | |
6474 | * Hence the bw of each lane in terms of the mode signal | |
6475 | * is: | |
6476 | */ | |
21a727b3 | 6477 | link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config); |
877d48d5 | 6478 | |
241bfc38 | 6479 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6480 | |
2bd89a07 | 6481 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6482 | pipe_config->pipe_bpp); |
6483 | ||
6484 | pipe_config->fdi_lanes = lane; | |
6485 | ||
2bd89a07 | 6486 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 6487 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 6488 | |
e3b247da | 6489 | ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); |
6d293983 | 6490 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { |
e29c22c0 DV |
6491 | pipe_config->pipe_bpp -= 2*3; |
6492 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
6493 | pipe_config->pipe_bpp); | |
6494 | needs_recompute = true; | |
6495 | pipe_config->bw_constrained = true; | |
6496 | ||
6497 | goto retry; | |
6498 | } | |
6499 | ||
6500 | if (needs_recompute) | |
6501 | return RETRY; | |
6502 | ||
6d293983 | 6503 | return ret; |
877d48d5 DV |
6504 | } |
6505 | ||
8cfb3407 VS |
6506 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
6507 | struct intel_crtc_state *pipe_config) | |
6508 | { | |
6509 | if (pipe_config->pipe_bpp > 24) | |
6510 | return false; | |
6511 | ||
6512 | /* HSW can handle pixel rate up to cdclk? */ | |
6513 | if (IS_HASWELL(dev_priv->dev)) | |
6514 | return true; | |
6515 | ||
6516 | /* | |
b432e5cf VS |
6517 | * We compare against max which means we must take |
6518 | * the increased cdclk requirement into account when | |
6519 | * calculating the new cdclk. | |
6520 | * | |
6521 | * Should measure whether using a lower cdclk w/o IPS | |
8cfb3407 VS |
6522 | */ |
6523 | return ilk_pipe_pixel_rate(pipe_config) <= | |
6524 | dev_priv->max_cdclk_freq * 95 / 100; | |
6525 | } | |
6526 | ||
42db64ef | 6527 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 6528 | struct intel_crtc_state *pipe_config) |
42db64ef | 6529 | { |
8cfb3407 VS |
6530 | struct drm_device *dev = crtc->base.dev; |
6531 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6532 | ||
d330a953 | 6533 | pipe_config->ips_enabled = i915.enable_ips && |
8cfb3407 VS |
6534 | hsw_crtc_supports_ips(crtc) && |
6535 | pipe_config_supports_ips(dev_priv, pipe_config); | |
42db64ef PZ |
6536 | } |
6537 | ||
39acb4aa VS |
6538 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
6539 | { | |
6540 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
6541 | ||
6542 | /* GDG double wide on either pipe, otherwise pipe A only */ | |
6543 | return INTEL_INFO(dev_priv)->gen < 4 && | |
6544 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); | |
6545 | } | |
6546 | ||
a43f6e0f | 6547 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 6548 | struct intel_crtc_state *pipe_config) |
79e53945 | 6549 | { |
a43f6e0f | 6550 | struct drm_device *dev = crtc->base.dev; |
8bd31e67 | 6551 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c5f93b0 | 6552 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
89749350 | 6553 | |
ad3a4479 | 6554 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 | 6555 | if (INTEL_INFO(dev)->gen < 4) { |
39acb4aa | 6556 | int clock_limit = dev_priv->max_cdclk_freq * 9 / 10; |
cf532bb2 VS |
6557 | |
6558 | /* | |
39acb4aa | 6559 | * Enable double wide mode when the dot clock |
cf532bb2 | 6560 | * is > 90% of the (display) core speed. |
cf532bb2 | 6561 | */ |
39acb4aa VS |
6562 | if (intel_crtc_supports_double_wide(crtc) && |
6563 | adjusted_mode->crtc_clock > clock_limit) { | |
ad3a4479 | 6564 | clock_limit *= 2; |
cf532bb2 | 6565 | pipe_config->double_wide = true; |
ad3a4479 VS |
6566 | } |
6567 | ||
39acb4aa VS |
6568 | if (adjusted_mode->crtc_clock > clock_limit) { |
6569 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
6570 | adjusted_mode->crtc_clock, clock_limit, | |
6571 | yesno(pipe_config->double_wide)); | |
e29c22c0 | 6572 | return -EINVAL; |
39acb4aa | 6573 | } |
2c07245f | 6574 | } |
89749350 | 6575 | |
1d1d0e27 VS |
6576 | /* |
6577 | * Pipe horizontal size must be even in: | |
6578 | * - DVO ganged mode | |
6579 | * - LVDS dual channel mode | |
6580 | * - Double wide pipe | |
6581 | */ | |
a93e255f | 6582 | if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
6583 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
6584 | pipe_config->pipe_src_w &= ~1; | |
6585 | ||
8693a824 DL |
6586 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6587 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
6588 | */ |
6589 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
aad941d5 | 6590 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) |
e29c22c0 | 6591 | return -EINVAL; |
44f46b42 | 6592 | |
f5adf94e | 6593 | if (HAS_IPS(dev)) |
a43f6e0f DV |
6594 | hsw_compute_ips_config(crtc, pipe_config); |
6595 | ||
877d48d5 | 6596 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 6597 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 6598 | |
cf5a15be | 6599 | return 0; |
79e53945 JB |
6600 | } |
6601 | ||
1652d19e VS |
6602 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
6603 | { | |
6604 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6605 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
6606 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6607 | uint32_t linkrate; | |
6608 | ||
414355a7 | 6609 | if (!(lcpll1 & LCPLL_PLL_ENABLE)) |
1652d19e | 6610 | return 24000; /* 24MHz is the cd freq with NSSC ref */ |
1652d19e VS |
6611 | |
6612 | if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) | |
6613 | return 540000; | |
6614 | ||
6615 | linkrate = (I915_READ(DPLL_CTRL1) & | |
71cd8423 | 6616 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; |
1652d19e | 6617 | |
71cd8423 DL |
6618 | if (linkrate == DPLL_CTRL1_LINK_RATE_2160 || |
6619 | linkrate == DPLL_CTRL1_LINK_RATE_1080) { | |
1652d19e VS |
6620 | /* vco 8640 */ |
6621 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6622 | case CDCLK_FREQ_450_432: | |
6623 | return 432000; | |
6624 | case CDCLK_FREQ_337_308: | |
6625 | return 308570; | |
6626 | case CDCLK_FREQ_675_617: | |
6627 | return 617140; | |
6628 | default: | |
6629 | WARN(1, "Unknown cd freq selection\n"); | |
6630 | } | |
6631 | } else { | |
6632 | /* vco 8100 */ | |
6633 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6634 | case CDCLK_FREQ_450_432: | |
6635 | return 450000; | |
6636 | case CDCLK_FREQ_337_308: | |
6637 | return 337500; | |
6638 | case CDCLK_FREQ_675_617: | |
6639 | return 675000; | |
6640 | default: | |
6641 | WARN(1, "Unknown cd freq selection\n"); | |
6642 | } | |
6643 | } | |
6644 | ||
6645 | /* error case, do as if DPLL0 isn't enabled */ | |
6646 | return 24000; | |
6647 | } | |
6648 | ||
acd3f3d3 BP |
6649 | static int broxton_get_display_clock_speed(struct drm_device *dev) |
6650 | { | |
6651 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6652 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6653 | uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; | |
6654 | uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE); | |
6655 | int cdclk; | |
6656 | ||
6657 | if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE)) | |
6658 | return 19200; | |
6659 | ||
6660 | cdclk = 19200 * pll_ratio / 2; | |
6661 | ||
6662 | switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) { | |
6663 | case BXT_CDCLK_CD2X_DIV_SEL_1: | |
6664 | return cdclk; /* 576MHz or 624MHz */ | |
6665 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: | |
6666 | return cdclk * 2 / 3; /* 384MHz */ | |
6667 | case BXT_CDCLK_CD2X_DIV_SEL_2: | |
6668 | return cdclk / 2; /* 288MHz */ | |
6669 | case BXT_CDCLK_CD2X_DIV_SEL_4: | |
6670 | return cdclk / 4; /* 144MHz */ | |
6671 | } | |
6672 | ||
6673 | /* error case, do as if DE PLL isn't enabled */ | |
6674 | return 19200; | |
6675 | } | |
6676 | ||
1652d19e VS |
6677 | static int broadwell_get_display_clock_speed(struct drm_device *dev) |
6678 | { | |
6679 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6680 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6681 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6682 | ||
6683 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6684 | return 800000; | |
6685 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6686 | return 450000; | |
6687 | else if (freq == LCPLL_CLK_FREQ_450) | |
6688 | return 450000; | |
6689 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
6690 | return 540000; | |
6691 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
6692 | return 337500; | |
6693 | else | |
6694 | return 675000; | |
6695 | } | |
6696 | ||
6697 | static int haswell_get_display_clock_speed(struct drm_device *dev) | |
6698 | { | |
6699 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6700 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6701 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6702 | ||
6703 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6704 | return 800000; | |
6705 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6706 | return 450000; | |
6707 | else if (freq == LCPLL_CLK_FREQ_450) | |
6708 | return 450000; | |
6709 | else if (IS_HSW_ULT(dev)) | |
6710 | return 337500; | |
6711 | else | |
6712 | return 540000; | |
79e53945 JB |
6713 | } |
6714 | ||
25eb05fc JB |
6715 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
6716 | { | |
bfa7df01 VS |
6717 | return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk", |
6718 | CCK_DISPLAY_CLOCK_CONTROL); | |
25eb05fc JB |
6719 | } |
6720 | ||
b37a6434 VS |
6721 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
6722 | { | |
6723 | return 450000; | |
6724 | } | |
6725 | ||
e70236a8 JB |
6726 | static int i945_get_display_clock_speed(struct drm_device *dev) |
6727 | { | |
6728 | return 400000; | |
6729 | } | |
79e53945 | 6730 | |
e70236a8 | 6731 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 6732 | { |
e907f170 | 6733 | return 333333; |
e70236a8 | 6734 | } |
79e53945 | 6735 | |
e70236a8 JB |
6736 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
6737 | { | |
6738 | return 200000; | |
6739 | } | |
79e53945 | 6740 | |
257a7ffc DV |
6741 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
6742 | { | |
6743 | u16 gcfgc = 0; | |
6744 | ||
6745 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
6746 | ||
6747 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6748 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 6749 | return 266667; |
257a7ffc | 6750 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 6751 | return 333333; |
257a7ffc | 6752 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 6753 | return 444444; |
257a7ffc DV |
6754 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
6755 | return 200000; | |
6756 | default: | |
6757 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
6758 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 6759 | return 133333; |
257a7ffc | 6760 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 6761 | return 166667; |
257a7ffc DV |
6762 | } |
6763 | } | |
6764 | ||
e70236a8 JB |
6765 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
6766 | { | |
6767 | u16 gcfgc = 0; | |
79e53945 | 6768 | |
e70236a8 JB |
6769 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
6770 | ||
6771 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 6772 | return 133333; |
e70236a8 JB |
6773 | else { |
6774 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6775 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 6776 | return 333333; |
e70236a8 JB |
6777 | default: |
6778 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
6779 | return 190000; | |
79e53945 | 6780 | } |
e70236a8 JB |
6781 | } |
6782 | } | |
6783 | ||
6784 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
6785 | { | |
e907f170 | 6786 | return 266667; |
e70236a8 JB |
6787 | } |
6788 | ||
1b1d2716 | 6789 | static int i85x_get_display_clock_speed(struct drm_device *dev) |
e70236a8 JB |
6790 | { |
6791 | u16 hpllcc = 0; | |
1b1d2716 | 6792 | |
65cd2b3f VS |
6793 | /* |
6794 | * 852GM/852GMV only supports 133 MHz and the HPLLCC | |
6795 | * encoding is different :( | |
6796 | * FIXME is this the right way to detect 852GM/852GMV? | |
6797 | */ | |
6798 | if (dev->pdev->revision == 0x1) | |
6799 | return 133333; | |
6800 | ||
1b1d2716 VS |
6801 | pci_bus_read_config_word(dev->pdev->bus, |
6802 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); | |
6803 | ||
e70236a8 JB |
6804 | /* Assume that the hardware is in the high speed state. This |
6805 | * should be the default. | |
6806 | */ | |
6807 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
6808 | case GC_CLOCK_133_200: | |
1b1d2716 | 6809 | case GC_CLOCK_133_200_2: |
e70236a8 JB |
6810 | case GC_CLOCK_100_200: |
6811 | return 200000; | |
6812 | case GC_CLOCK_166_250: | |
6813 | return 250000; | |
6814 | case GC_CLOCK_100_133: | |
e907f170 | 6815 | return 133333; |
1b1d2716 VS |
6816 | case GC_CLOCK_133_266: |
6817 | case GC_CLOCK_133_266_2: | |
6818 | case GC_CLOCK_166_266: | |
6819 | return 266667; | |
e70236a8 | 6820 | } |
79e53945 | 6821 | |
e70236a8 JB |
6822 | /* Shouldn't happen */ |
6823 | return 0; | |
6824 | } | |
79e53945 | 6825 | |
e70236a8 JB |
6826 | static int i830_get_display_clock_speed(struct drm_device *dev) |
6827 | { | |
e907f170 | 6828 | return 133333; |
79e53945 JB |
6829 | } |
6830 | ||
34edce2f VS |
6831 | static unsigned int intel_hpll_vco(struct drm_device *dev) |
6832 | { | |
6833 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6834 | static const unsigned int blb_vco[8] = { | |
6835 | [0] = 3200000, | |
6836 | [1] = 4000000, | |
6837 | [2] = 5333333, | |
6838 | [3] = 4800000, | |
6839 | [4] = 6400000, | |
6840 | }; | |
6841 | static const unsigned int pnv_vco[8] = { | |
6842 | [0] = 3200000, | |
6843 | [1] = 4000000, | |
6844 | [2] = 5333333, | |
6845 | [3] = 4800000, | |
6846 | [4] = 2666667, | |
6847 | }; | |
6848 | static const unsigned int cl_vco[8] = { | |
6849 | [0] = 3200000, | |
6850 | [1] = 4000000, | |
6851 | [2] = 5333333, | |
6852 | [3] = 6400000, | |
6853 | [4] = 3333333, | |
6854 | [5] = 3566667, | |
6855 | [6] = 4266667, | |
6856 | }; | |
6857 | static const unsigned int elk_vco[8] = { | |
6858 | [0] = 3200000, | |
6859 | [1] = 4000000, | |
6860 | [2] = 5333333, | |
6861 | [3] = 4800000, | |
6862 | }; | |
6863 | static const unsigned int ctg_vco[8] = { | |
6864 | [0] = 3200000, | |
6865 | [1] = 4000000, | |
6866 | [2] = 5333333, | |
6867 | [3] = 6400000, | |
6868 | [4] = 2666667, | |
6869 | [5] = 4266667, | |
6870 | }; | |
6871 | const unsigned int *vco_table; | |
6872 | unsigned int vco; | |
6873 | uint8_t tmp = 0; | |
6874 | ||
6875 | /* FIXME other chipsets? */ | |
6876 | if (IS_GM45(dev)) | |
6877 | vco_table = ctg_vco; | |
6878 | else if (IS_G4X(dev)) | |
6879 | vco_table = elk_vco; | |
6880 | else if (IS_CRESTLINE(dev)) | |
6881 | vco_table = cl_vco; | |
6882 | else if (IS_PINEVIEW(dev)) | |
6883 | vco_table = pnv_vco; | |
6884 | else if (IS_G33(dev)) | |
6885 | vco_table = blb_vco; | |
6886 | else | |
6887 | return 0; | |
6888 | ||
6889 | tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO); | |
6890 | ||
6891 | vco = vco_table[tmp & 0x7]; | |
6892 | if (vco == 0) | |
6893 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); | |
6894 | else | |
6895 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); | |
6896 | ||
6897 | return vco; | |
6898 | } | |
6899 | ||
6900 | static int gm45_get_display_clock_speed(struct drm_device *dev) | |
6901 | { | |
6902 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
6903 | uint16_t tmp = 0; | |
6904 | ||
6905 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
6906 | ||
6907 | cdclk_sel = (tmp >> 12) & 0x1; | |
6908 | ||
6909 | switch (vco) { | |
6910 | case 2666667: | |
6911 | case 4000000: | |
6912 | case 5333333: | |
6913 | return cdclk_sel ? 333333 : 222222; | |
6914 | case 3200000: | |
6915 | return cdclk_sel ? 320000 : 228571; | |
6916 | default: | |
6917 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); | |
6918 | return 222222; | |
6919 | } | |
6920 | } | |
6921 | ||
6922 | static int i965gm_get_display_clock_speed(struct drm_device *dev) | |
6923 | { | |
6924 | static const uint8_t div_3200[] = { 16, 10, 8 }; | |
6925 | static const uint8_t div_4000[] = { 20, 12, 10 }; | |
6926 | static const uint8_t div_5333[] = { 24, 16, 14 }; | |
6927 | const uint8_t *div_table; | |
6928 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
6929 | uint16_t tmp = 0; | |
6930 | ||
6931 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
6932 | ||
6933 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; | |
6934 | ||
6935 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
6936 | goto fail; | |
6937 | ||
6938 | switch (vco) { | |
6939 | case 3200000: | |
6940 | div_table = div_3200; | |
6941 | break; | |
6942 | case 4000000: | |
6943 | div_table = div_4000; | |
6944 | break; | |
6945 | case 5333333: | |
6946 | div_table = div_5333; | |
6947 | break; | |
6948 | default: | |
6949 | goto fail; | |
6950 | } | |
6951 | ||
6952 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
6953 | ||
caf4e252 | 6954 | fail: |
34edce2f VS |
6955 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); |
6956 | return 200000; | |
6957 | } | |
6958 | ||
6959 | static int g33_get_display_clock_speed(struct drm_device *dev) | |
6960 | { | |
6961 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; | |
6962 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; | |
6963 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; | |
6964 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; | |
6965 | const uint8_t *div_table; | |
6966 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
6967 | uint16_t tmp = 0; | |
6968 | ||
6969 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
6970 | ||
6971 | cdclk_sel = (tmp >> 4) & 0x7; | |
6972 | ||
6973 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
6974 | goto fail; | |
6975 | ||
6976 | switch (vco) { | |
6977 | case 3200000: | |
6978 | div_table = div_3200; | |
6979 | break; | |
6980 | case 4000000: | |
6981 | div_table = div_4000; | |
6982 | break; | |
6983 | case 4800000: | |
6984 | div_table = div_4800; | |
6985 | break; | |
6986 | case 5333333: | |
6987 | div_table = div_5333; | |
6988 | break; | |
6989 | default: | |
6990 | goto fail; | |
6991 | } | |
6992 | ||
6993 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
6994 | ||
caf4e252 | 6995 | fail: |
34edce2f VS |
6996 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); |
6997 | return 190476; | |
6998 | } | |
6999 | ||
2c07245f | 7000 | static void |
a65851af | 7001 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 7002 | { |
a65851af VS |
7003 | while (*num > DATA_LINK_M_N_MASK || |
7004 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
7005 | *num >>= 1; |
7006 | *den >>= 1; | |
7007 | } | |
7008 | } | |
7009 | ||
a65851af VS |
7010 | static void compute_m_n(unsigned int m, unsigned int n, |
7011 | uint32_t *ret_m, uint32_t *ret_n) | |
7012 | { | |
7013 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
7014 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
7015 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
7016 | } | |
7017 | ||
e69d0bc1 DV |
7018 | void |
7019 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
7020 | int pixel_clock, int link_clock, | |
7021 | struct intel_link_m_n *m_n) | |
2c07245f | 7022 | { |
e69d0bc1 | 7023 | m_n->tu = 64; |
a65851af VS |
7024 | |
7025 | compute_m_n(bits_per_pixel * pixel_clock, | |
7026 | link_clock * nlanes * 8, | |
7027 | &m_n->gmch_m, &m_n->gmch_n); | |
7028 | ||
7029 | compute_m_n(pixel_clock, link_clock, | |
7030 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
7031 | } |
7032 | ||
a7615030 CW |
7033 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
7034 | { | |
d330a953 JN |
7035 | if (i915.panel_use_ssc >= 0) |
7036 | return i915.panel_use_ssc != 0; | |
41aa3448 | 7037 | return dev_priv->vbt.lvds_use_ssc |
435793df | 7038 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
7039 | } |
7040 | ||
ceb41007 | 7041 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state) |
c65d77d8 | 7042 | { |
a93e255f | 7043 | struct drm_device *dev = crtc_state->base.crtc->dev; |
c65d77d8 JB |
7044 | struct drm_i915_private *dev_priv = dev->dev_private; |
7045 | int refclk; | |
7046 | ||
a93e255f ACO |
7047 | WARN_ON(!crtc_state->base.state); |
7048 | ||
666a4537 | 7049 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) { |
9a0ea498 | 7050 | refclk = 100000; |
a93e255f | 7051 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 7052 | intel_panel_use_ssc(dev_priv)) { |
e91e941b VS |
7053 | refclk = dev_priv->vbt.lvds_ssc_freq; |
7054 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
7055 | } else if (!IS_GEN2(dev)) { |
7056 | refclk = 96000; | |
7057 | } else { | |
7058 | refclk = 48000; | |
7059 | } | |
7060 | ||
7061 | return refclk; | |
7062 | } | |
7063 | ||
7429e9d4 | 7064 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 7065 | { |
7df00d7a | 7066 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 7067 | } |
f47709a9 | 7068 | |
7429e9d4 DV |
7069 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
7070 | { | |
7071 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
7072 | } |
7073 | ||
f47709a9 | 7074 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 7075 | struct intel_crtc_state *crtc_state, |
a7516a05 JB |
7076 | intel_clock_t *reduced_clock) |
7077 | { | |
f47709a9 | 7078 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
7079 | u32 fp, fp2 = 0; |
7080 | ||
7081 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 7082 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7083 | if (reduced_clock) |
7429e9d4 | 7084 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 7085 | } else { |
190f68c5 | 7086 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7087 | if (reduced_clock) |
7429e9d4 | 7088 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
7089 | } |
7090 | ||
190f68c5 | 7091 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 7092 | |
f47709a9 | 7093 | crtc->lowfreq_avail = false; |
a93e255f | 7094 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 7095 | reduced_clock) { |
190f68c5 | 7096 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 7097 | crtc->lowfreq_avail = true; |
a7516a05 | 7098 | } else { |
190f68c5 | 7099 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
7100 | } |
7101 | } | |
7102 | ||
5e69f97f CML |
7103 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
7104 | pipe) | |
89b667f8 JB |
7105 | { |
7106 | u32 reg_val; | |
7107 | ||
7108 | /* | |
7109 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
7110 | * and set it to a reasonable value instead. | |
7111 | */ | |
ab3c759a | 7112 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
7113 | reg_val &= 0xffffff00; |
7114 | reg_val |= 0x00000030; | |
ab3c759a | 7115 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7116 | |
ab3c759a | 7117 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7118 | reg_val &= 0x8cffffff; |
7119 | reg_val = 0x8c000000; | |
ab3c759a | 7120 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 7121 | |
ab3c759a | 7122 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 7123 | reg_val &= 0xffffff00; |
ab3c759a | 7124 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7125 | |
ab3c759a | 7126 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7127 | reg_val &= 0x00ffffff; |
7128 | reg_val |= 0xb0000000; | |
ab3c759a | 7129 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
7130 | } |
7131 | ||
b551842d DV |
7132 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
7133 | struct intel_link_m_n *m_n) | |
7134 | { | |
7135 | struct drm_device *dev = crtc->base.dev; | |
7136 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7137 | int pipe = crtc->pipe; | |
7138 | ||
e3b95f1e DV |
7139 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7140 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
7141 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
7142 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
7143 | } |
7144 | ||
7145 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
7146 | struct intel_link_m_n *m_n, |
7147 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
7148 | { |
7149 | struct drm_device *dev = crtc->base.dev; | |
7150 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7151 | int pipe = crtc->pipe; | |
6e3c9717 | 7152 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
7153 | |
7154 | if (INTEL_INFO(dev)->gen >= 5) { | |
7155 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
7156 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
7157 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
7158 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
7159 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
7160 | * for gen < 8) and if DRRS is supported (to make sure the | |
7161 | * registers are not unnecessarily accessed). | |
7162 | */ | |
44395bfe | 7163 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 7164 | crtc->config->has_drrs) { |
f769cd24 VK |
7165 | I915_WRITE(PIPE_DATA_M2(transcoder), |
7166 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
7167 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
7168 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
7169 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
7170 | } | |
b551842d | 7171 | } else { |
e3b95f1e DV |
7172 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7173 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
7174 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
7175 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
7176 | } |
7177 | } | |
7178 | ||
fe3cd48d | 7179 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 7180 | { |
fe3cd48d R |
7181 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
7182 | ||
7183 | if (m_n == M1_N1) { | |
7184 | dp_m_n = &crtc->config->dp_m_n; | |
7185 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
7186 | } else if (m_n == M2_N2) { | |
7187 | ||
7188 | /* | |
7189 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
7190 | * needs to be programmed into M1_N1. | |
7191 | */ | |
7192 | dp_m_n = &crtc->config->dp_m2_n2; | |
7193 | } else { | |
7194 | DRM_ERROR("Unsupported divider value\n"); | |
7195 | return; | |
7196 | } | |
7197 | ||
6e3c9717 ACO |
7198 | if (crtc->config->has_pch_encoder) |
7199 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 7200 | else |
fe3cd48d | 7201 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
7202 | } |
7203 | ||
251ac862 DV |
7204 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
7205 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 DV |
7206 | { |
7207 | u32 dpll, dpll_md; | |
7208 | ||
7209 | /* | |
7210 | * Enable DPIO clock input. We should never disable the reference | |
7211 | * clock for pipe B, since VGA hotplug / manual detection depends | |
7212 | * on it. | |
7213 | */ | |
60bfe44f VS |
7214 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV | |
7215 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV; | |
bdd4b6a6 DV |
7216 | /* We should never disable this, set it here for state tracking */ |
7217 | if (crtc->pipe == PIPE_B) | |
7218 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
7219 | dpll |= DPLL_VCO_ENABLE; | |
d288f65f | 7220 | pipe_config->dpll_hw_state.dpll = dpll; |
bdd4b6a6 | 7221 | |
d288f65f | 7222 | dpll_md = (pipe_config->pixel_multiplier - 1) |
bdd4b6a6 | 7223 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
d288f65f | 7224 | pipe_config->dpll_hw_state.dpll_md = dpll_md; |
bdd4b6a6 DV |
7225 | } |
7226 | ||
d288f65f | 7227 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7228 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 7229 | { |
f47709a9 | 7230 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 7231 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 7232 | int pipe = crtc->pipe; |
bdd4b6a6 | 7233 | u32 mdiv; |
a0c4da24 | 7234 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 7235 | u32 coreclk, reg_val; |
a0c4da24 | 7236 | |
a580516d | 7237 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 7238 | |
d288f65f VS |
7239 | bestn = pipe_config->dpll.n; |
7240 | bestm1 = pipe_config->dpll.m1; | |
7241 | bestm2 = pipe_config->dpll.m2; | |
7242 | bestp1 = pipe_config->dpll.p1; | |
7243 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 7244 | |
89b667f8 JB |
7245 | /* See eDP HDMI DPIO driver vbios notes doc */ |
7246 | ||
7247 | /* PLL B needs special handling */ | |
bdd4b6a6 | 7248 | if (pipe == PIPE_B) |
5e69f97f | 7249 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
7250 | |
7251 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 7252 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
7253 | |
7254 | /* Disable target IRef on PLL */ | |
ab3c759a | 7255 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 7256 | reg_val &= 0x00ffffff; |
ab3c759a | 7257 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
7258 | |
7259 | /* Disable fast lock */ | |
ab3c759a | 7260 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
7261 | |
7262 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
7263 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
7264 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
7265 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 7266 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
7267 | |
7268 | /* | |
7269 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
7270 | * but we don't support that). | |
7271 | * Note: don't use the DAC post divider as it seems unstable. | |
7272 | */ | |
7273 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 7274 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7275 | |
a0c4da24 | 7276 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 7277 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7278 | |
89b667f8 | 7279 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 7280 | if (pipe_config->port_clock == 162000 || |
409ee761 ACO |
7281 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || |
7282 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 7283 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 7284 | 0x009f0003); |
89b667f8 | 7285 | else |
ab3c759a | 7286 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
7287 | 0x00d0000f); |
7288 | ||
681a8504 | 7289 | if (pipe_config->has_dp_encoder) { |
89b667f8 | 7290 | /* Use SSC source */ |
bdd4b6a6 | 7291 | if (pipe == PIPE_A) |
ab3c759a | 7292 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7293 | 0x0df40000); |
7294 | else | |
ab3c759a | 7295 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7296 | 0x0df70000); |
7297 | } else { /* HDMI or VGA */ | |
7298 | /* Use bend source */ | |
bdd4b6a6 | 7299 | if (pipe == PIPE_A) |
ab3c759a | 7300 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7301 | 0x0df70000); |
7302 | else | |
ab3c759a | 7303 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7304 | 0x0df40000); |
7305 | } | |
a0c4da24 | 7306 | |
ab3c759a | 7307 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 7308 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
409ee761 ACO |
7309 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
7310 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) | |
89b667f8 | 7311 | coreclk |= 0x01000000; |
ab3c759a | 7312 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 7313 | |
ab3c759a | 7314 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 7315 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
7316 | } |
7317 | ||
251ac862 DV |
7318 | static void chv_compute_dpll(struct intel_crtc *crtc, |
7319 | struct intel_crtc_state *pipe_config) | |
1ae0d137 | 7320 | { |
60bfe44f VS |
7321 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | |
7322 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | | |
1ae0d137 VS |
7323 | DPLL_VCO_ENABLE; |
7324 | if (crtc->pipe != PIPE_A) | |
d288f65f | 7325 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
1ae0d137 | 7326 | |
d288f65f VS |
7327 | pipe_config->dpll_hw_state.dpll_md = |
7328 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
1ae0d137 VS |
7329 | } |
7330 | ||
d288f65f | 7331 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7332 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
7333 | { |
7334 | struct drm_device *dev = crtc->base.dev; | |
7335 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7336 | int pipe = crtc->pipe; | |
f0f59a00 | 7337 | i915_reg_t dpll_reg = DPLL(crtc->pipe); |
9d556c99 | 7338 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9cbe40c1 | 7339 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 7340 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 7341 | u32 dpio_val; |
9cbe40c1 | 7342 | int vco; |
9d556c99 | 7343 | |
d288f65f VS |
7344 | bestn = pipe_config->dpll.n; |
7345 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
7346 | bestm1 = pipe_config->dpll.m1; | |
7347 | bestm2 = pipe_config->dpll.m2 >> 22; | |
7348 | bestp1 = pipe_config->dpll.p1; | |
7349 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 7350 | vco = pipe_config->dpll.vco; |
a945ce7e | 7351 | dpio_val = 0; |
9cbe40c1 | 7352 | loopfilter = 0; |
9d556c99 CML |
7353 | |
7354 | /* | |
7355 | * Enable Refclk and SSC | |
7356 | */ | |
a11b0703 | 7357 | I915_WRITE(dpll_reg, |
d288f65f | 7358 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
a11b0703 | 7359 | |
a580516d | 7360 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 7361 | |
9d556c99 CML |
7362 | /* p1 and p2 divider */ |
7363 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
7364 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
7365 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
7366 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
7367 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
7368 | ||
7369 | /* Feedback post-divider - m2 */ | |
7370 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
7371 | ||
7372 | /* Feedback refclk divider - n and m1 */ | |
7373 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
7374 | DPIO_CHV_M1_DIV_BY_2 | | |
7375 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
7376 | ||
7377 | /* M2 fraction division */ | |
25a25dfc | 7378 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
7379 | |
7380 | /* M2 fraction division enable */ | |
a945ce7e VP |
7381 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
7382 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
7383 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
7384 | if (bestm2_frac) | |
7385 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
7386 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 7387 | |
de3a0fde VP |
7388 | /* Program digital lock detect threshold */ |
7389 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
7390 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
7391 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
7392 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
7393 | if (!bestm2_frac) | |
7394 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
7395 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
7396 | ||
9d556c99 | 7397 | /* Loop filter */ |
9cbe40c1 VP |
7398 | if (vco == 5400000) { |
7399 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7400 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
7401 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7402 | tribuf_calcntr = 0x9; | |
7403 | } else if (vco <= 6200000) { | |
7404 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7405 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
7406 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7407 | tribuf_calcntr = 0x9; | |
7408 | } else if (vco <= 6480000) { | |
7409 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7410 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7411 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7412 | tribuf_calcntr = 0x8; | |
7413 | } else { | |
7414 | /* Not supported. Apply the same limits as in the max case */ | |
7415 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7416 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7417 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7418 | tribuf_calcntr = 0; | |
7419 | } | |
9d556c99 CML |
7420 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
7421 | ||
968040b2 | 7422 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
7423 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
7424 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
7425 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
7426 | ||
9d556c99 CML |
7427 | /* AFC Recal */ |
7428 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
7429 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
7430 | DPIO_AFC_RECAL); | |
7431 | ||
a580516d | 7432 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
7433 | } |
7434 | ||
d288f65f VS |
7435 | /** |
7436 | * vlv_force_pll_on - forcibly enable just the PLL | |
7437 | * @dev_priv: i915 private structure | |
7438 | * @pipe: pipe PLL to enable | |
7439 | * @dpll: PLL configuration | |
7440 | * | |
7441 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
7442 | * in cases where we need the PLL enabled even when @pipe is not going to | |
7443 | * be enabled. | |
7444 | */ | |
3f36b937 TU |
7445 | int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, |
7446 | const struct dpll *dpll) | |
d288f65f VS |
7447 | { |
7448 | struct intel_crtc *crtc = | |
7449 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
3f36b937 TU |
7450 | struct intel_crtc_state *pipe_config; |
7451 | ||
7452 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); | |
7453 | if (!pipe_config) | |
7454 | return -ENOMEM; | |
7455 | ||
7456 | pipe_config->base.crtc = &crtc->base; | |
7457 | pipe_config->pixel_multiplier = 1; | |
7458 | pipe_config->dpll = *dpll; | |
d288f65f VS |
7459 | |
7460 | if (IS_CHERRYVIEW(dev)) { | |
3f36b937 TU |
7461 | chv_compute_dpll(crtc, pipe_config); |
7462 | chv_prepare_pll(crtc, pipe_config); | |
7463 | chv_enable_pll(crtc, pipe_config); | |
d288f65f | 7464 | } else { |
3f36b937 TU |
7465 | vlv_compute_dpll(crtc, pipe_config); |
7466 | vlv_prepare_pll(crtc, pipe_config); | |
7467 | vlv_enable_pll(crtc, pipe_config); | |
d288f65f | 7468 | } |
3f36b937 TU |
7469 | |
7470 | kfree(pipe_config); | |
7471 | ||
7472 | return 0; | |
d288f65f VS |
7473 | } |
7474 | ||
7475 | /** | |
7476 | * vlv_force_pll_off - forcibly disable just the PLL | |
7477 | * @dev_priv: i915 private structure | |
7478 | * @pipe: pipe PLL to disable | |
7479 | * | |
7480 | * Disable the PLL for @pipe. To be used in cases where we need | |
7481 | * the PLL enabled even when @pipe is not going to be enabled. | |
7482 | */ | |
7483 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
7484 | { | |
7485 | if (IS_CHERRYVIEW(dev)) | |
7486 | chv_disable_pll(to_i915(dev), pipe); | |
7487 | else | |
7488 | vlv_disable_pll(to_i915(dev), pipe); | |
7489 | } | |
7490 | ||
251ac862 DV |
7491 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
7492 | struct intel_crtc_state *crtc_state, | |
ceb41007 | 7493 | intel_clock_t *reduced_clock) |
eb1cbe48 | 7494 | { |
f47709a9 | 7495 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7496 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
7497 | u32 dpll; |
7498 | bool is_sdvo; | |
190f68c5 | 7499 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7500 | |
190f68c5 | 7501 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7502 | |
a93e255f ACO |
7503 | is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) || |
7504 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
7505 | |
7506 | dpll = DPLL_VGA_MODE_DIS; | |
7507 | ||
a93e255f | 7508 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
7509 | dpll |= DPLLB_MODE_LVDS; |
7510 | else | |
7511 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 7512 | |
ef1b460d | 7513 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 7514 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 7515 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 7516 | } |
198a037f DV |
7517 | |
7518 | if (is_sdvo) | |
4a33e48d | 7519 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 7520 | |
190f68c5 | 7521 | if (crtc_state->has_dp_encoder) |
4a33e48d | 7522 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
7523 | |
7524 | /* compute bitmask from p1 value */ | |
7525 | if (IS_PINEVIEW(dev)) | |
7526 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
7527 | else { | |
7528 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7529 | if (IS_G4X(dev) && reduced_clock) | |
7530 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
7531 | } | |
7532 | switch (clock->p2) { | |
7533 | case 5: | |
7534 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7535 | break; | |
7536 | case 7: | |
7537 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7538 | break; | |
7539 | case 10: | |
7540 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7541 | break; | |
7542 | case 14: | |
7543 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7544 | break; | |
7545 | } | |
7546 | if (INTEL_INFO(dev)->gen >= 4) | |
7547 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
7548 | ||
190f68c5 | 7549 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 7550 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
a93e255f | 7551 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 7552 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
7553 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
7554 | else | |
7555 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7556 | ||
7557 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7558 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 7559 | |
eb1cbe48 | 7560 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 7561 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7562 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 7563 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
7564 | } |
7565 | } | |
7566 | ||
251ac862 DV |
7567 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
7568 | struct intel_crtc_state *crtc_state, | |
ceb41007 | 7569 | intel_clock_t *reduced_clock) |
eb1cbe48 | 7570 | { |
f47709a9 | 7571 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7572 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 7573 | u32 dpll; |
190f68c5 | 7574 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7575 | |
190f68c5 | 7576 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7577 | |
eb1cbe48 DV |
7578 | dpll = DPLL_VGA_MODE_DIS; |
7579 | ||
a93e255f | 7580 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
7581 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
7582 | } else { | |
7583 | if (clock->p1 == 2) | |
7584 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
7585 | else | |
7586 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7587 | if (clock->p2 == 4) | |
7588 | dpll |= PLL_P2_DIVIDE_BY_4; | |
7589 | } | |
7590 | ||
a93e255f | 7591 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
7592 | dpll |= DPLL_DVO_2X_MODE; |
7593 | ||
a93e255f | 7594 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 7595 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
7596 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
7597 | else | |
7598 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7599 | ||
7600 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7601 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
7602 | } |
7603 | ||
8a654f3b | 7604 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
7605 | { |
7606 | struct drm_device *dev = intel_crtc->base.dev; | |
7607 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7608 | enum pipe pipe = intel_crtc->pipe; | |
6e3c9717 | 7609 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
7c5f93b0 | 7610 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
7611 | uint32_t crtc_vtotal, crtc_vblank_end; |
7612 | int vsyncshift = 0; | |
4d8a62ea DV |
7613 | |
7614 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
7615 | * the hw state checker will get angry at the mismatch. */ | |
7616 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
7617 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 7618 | |
609aeaca | 7619 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 7620 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
7621 | crtc_vtotal -= 1; |
7622 | crtc_vblank_end -= 1; | |
609aeaca | 7623 | |
409ee761 | 7624 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
7625 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
7626 | else | |
7627 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
7628 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
7629 | if (vsyncshift < 0) |
7630 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
7631 | } |
7632 | ||
7633 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 7634 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 7635 | |
fe2b8f9d | 7636 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
7637 | (adjusted_mode->crtc_hdisplay - 1) | |
7638 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 7639 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
7640 | (adjusted_mode->crtc_hblank_start - 1) | |
7641 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 7642 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
7643 | (adjusted_mode->crtc_hsync_start - 1) | |
7644 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
7645 | ||
fe2b8f9d | 7646 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 7647 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 7648 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 7649 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 7650 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 7651 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 7652 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
7653 | (adjusted_mode->crtc_vsync_start - 1) | |
7654 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
7655 | ||
b5e508d4 PZ |
7656 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
7657 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
7658 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
7659 | * bits. */ | |
7660 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
7661 | (pipe == PIPE_B || pipe == PIPE_C)) | |
7662 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
7663 | ||
bc58be60 JN |
7664 | } |
7665 | ||
7666 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc) | |
7667 | { | |
7668 | struct drm_device *dev = intel_crtc->base.dev; | |
7669 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7670 | enum pipe pipe = intel_crtc->pipe; | |
7671 | ||
b0e77b9c PZ |
7672 | /* pipesrc controls the size that is scaled from, which should |
7673 | * always be the user's requested size. | |
7674 | */ | |
7675 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
7676 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
7677 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
7678 | } |
7679 | ||
1bd1bd80 | 7680 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 7681 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
7682 | { |
7683 | struct drm_device *dev = crtc->base.dev; | |
7684 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7685 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
7686 | uint32_t tmp; | |
7687 | ||
7688 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7689 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
7690 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7691 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
7692 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
7693 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7694 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
7695 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
7696 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7697 | |
7698 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7699 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
7700 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7701 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
7702 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
7703 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7704 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
7705 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
7706 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7707 | |
7708 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
7709 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
7710 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
7711 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 | 7712 | } |
bc58be60 JN |
7713 | } |
7714 | ||
7715 | static void intel_get_pipe_src_size(struct intel_crtc *crtc, | |
7716 | struct intel_crtc_state *pipe_config) | |
7717 | { | |
7718 | struct drm_device *dev = crtc->base.dev; | |
7719 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7720 | u32 tmp; | |
1bd1bd80 DV |
7721 | |
7722 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
7723 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
7724 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
7725 | ||
2d112de7 ACO |
7726 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
7727 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
7728 | } |
7729 | ||
f6a83288 | 7730 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 7731 | struct intel_crtc_state *pipe_config) |
babea61d | 7732 | { |
2d112de7 ACO |
7733 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
7734 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
7735 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
7736 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 7737 | |
2d112de7 ACO |
7738 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
7739 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
7740 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7741 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 7742 | |
2d112de7 | 7743 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 7744 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 7745 | |
2d112de7 ACO |
7746 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
7747 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
cd13f5ab ML |
7748 | |
7749 | mode->hsync = drm_mode_hsync(mode); | |
7750 | mode->vrefresh = drm_mode_vrefresh(mode); | |
7751 | drm_mode_set_name(mode); | |
babea61d JB |
7752 | } |
7753 | ||
84b046f3 DV |
7754 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7755 | { | |
7756 | struct drm_device *dev = intel_crtc->base.dev; | |
7757 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7758 | uint32_t pipeconf; | |
7759 | ||
9f11a9e4 | 7760 | pipeconf = 0; |
84b046f3 | 7761 | |
b6b5d049 VS |
7762 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
7763 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
7764 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 7765 | |
6e3c9717 | 7766 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7767 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7768 | |
ff9ce46e | 7769 | /* only g4x and later have fancy bpc/dither controls */ |
666a4537 | 7770 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
ff9ce46e | 7771 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 7772 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 7773 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 7774 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 7775 | |
6e3c9717 | 7776 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
7777 | case 18: |
7778 | pipeconf |= PIPECONF_6BPC; | |
7779 | break; | |
7780 | case 24: | |
7781 | pipeconf |= PIPECONF_8BPC; | |
7782 | break; | |
7783 | case 30: | |
7784 | pipeconf |= PIPECONF_10BPC; | |
7785 | break; | |
7786 | default: | |
7787 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7788 | BUG(); | |
84b046f3 DV |
7789 | } |
7790 | } | |
7791 | ||
7792 | if (HAS_PIPE_CXSR(dev)) { | |
7793 | if (intel_crtc->lowfreq_avail) { | |
7794 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
7795 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
7796 | } else { | |
7797 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
7798 | } |
7799 | } | |
7800 | ||
6e3c9717 | 7801 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 7802 | if (INTEL_INFO(dev)->gen < 4 || |
409ee761 | 7803 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
7804 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
7805 | else | |
7806 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7807 | } else | |
84b046f3 DV |
7808 | pipeconf |= PIPECONF_PROGRESSIVE; |
7809 | ||
666a4537 WB |
7810 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
7811 | intel_crtc->config->limited_color_range) | |
9f11a9e4 | 7812 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 7813 | |
84b046f3 DV |
7814 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7815 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7816 | } | |
7817 | ||
190f68c5 ACO |
7818 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
7819 | struct intel_crtc_state *crtc_state) | |
79e53945 | 7820 | { |
c7653199 | 7821 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 7822 | struct drm_i915_private *dev_priv = dev->dev_private; |
ceb41007 | 7823 | int refclk; |
c329a4ec | 7824 | bool ok; |
d4906093 | 7825 | const intel_limit_t *limit; |
79e53945 | 7826 | |
dd3cd74a ACO |
7827 | memset(&crtc_state->dpll_hw_state, 0, |
7828 | sizeof(crtc_state->dpll_hw_state)); | |
7829 | ||
a65347ba JN |
7830 | if (crtc_state->has_dsi_encoder) |
7831 | return 0; | |
43565a06 | 7832 | |
190f68c5 | 7833 | if (!crtc_state->clock_set) { |
ceb41007 | 7834 | refclk = i9xx_get_refclk(crtc_state); |
79e53945 | 7835 | |
e9fd1c02 JN |
7836 | /* |
7837 | * Returns a set of divisors for the desired target clock with | |
7838 | * the given refclk, or FALSE. The returned values represent | |
7839 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
7840 | * 2) / p1 / p2. | |
7841 | */ | |
a93e255f ACO |
7842 | limit = intel_limit(crtc_state, refclk); |
7843 | ok = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 7844 | crtc_state->port_clock, |
364ee29d ACO |
7845 | refclk, NULL, |
7846 | &crtc_state->dpll); | |
f2335330 | 7847 | if (!ok) { |
e9fd1c02 JN |
7848 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
7849 | return -EINVAL; | |
7850 | } | |
f47709a9 | 7851 | } |
7026d4ac | 7852 | |
e9fd1c02 | 7853 | if (IS_GEN2(dev)) { |
ceb41007 | 7854 | i8xx_compute_dpll(crtc, crtc_state, NULL); |
9d556c99 | 7855 | } else if (IS_CHERRYVIEW(dev)) { |
251ac862 | 7856 | chv_compute_dpll(crtc, crtc_state); |
e9fd1c02 | 7857 | } else if (IS_VALLEYVIEW(dev)) { |
251ac862 | 7858 | vlv_compute_dpll(crtc, crtc_state); |
e9fd1c02 | 7859 | } else { |
ceb41007 | 7860 | i9xx_compute_dpll(crtc, crtc_state, NULL); |
e9fd1c02 | 7861 | } |
79e53945 | 7862 | |
c8f7a0db | 7863 | return 0; |
f564048e EA |
7864 | } |
7865 | ||
2fa2fe9a | 7866 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 7867 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
7868 | { |
7869 | struct drm_device *dev = crtc->base.dev; | |
7870 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7871 | uint32_t tmp; | |
7872 | ||
dc9e7dec VS |
7873 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
7874 | return; | |
7875 | ||
2fa2fe9a | 7876 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
7877 | if (!(tmp & PFIT_ENABLE)) |
7878 | return; | |
2fa2fe9a | 7879 | |
06922821 | 7880 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
7881 | if (INTEL_INFO(dev)->gen < 4) { |
7882 | if (crtc->pipe != PIPE_B) | |
7883 | return; | |
2fa2fe9a DV |
7884 | } else { |
7885 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
7886 | return; | |
7887 | } | |
7888 | ||
06922821 | 7889 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
7890 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
7891 | if (INTEL_INFO(dev)->gen < 5) | |
7892 | pipe_config->gmch_pfit.lvds_border_bits = | |
7893 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
7894 | } | |
7895 | ||
acbec814 | 7896 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7897 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
7898 | { |
7899 | struct drm_device *dev = crtc->base.dev; | |
7900 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7901 | int pipe = pipe_config->cpu_transcoder; | |
7902 | intel_clock_t clock; | |
7903 | u32 mdiv; | |
662c6ecb | 7904 | int refclk = 100000; |
acbec814 | 7905 | |
f573de5a SK |
7906 | /* In case of MIPI DPLL will not even be used */ |
7907 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) | |
7908 | return; | |
7909 | ||
a580516d | 7910 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 7911 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 7912 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
7913 | |
7914 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
7915 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
7916 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
7917 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
7918 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
7919 | ||
dccbea3b | 7920 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
7921 | } |
7922 | ||
5724dbd1 DL |
7923 | static void |
7924 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
7925 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
7926 | { |
7927 | struct drm_device *dev = crtc->base.dev; | |
7928 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7929 | u32 val, base, offset; | |
7930 | int pipe = crtc->pipe, plane = crtc->plane; | |
7931 | int fourcc, pixel_format; | |
6761dd31 | 7932 | unsigned int aligned_height; |
b113d5ee | 7933 | struct drm_framebuffer *fb; |
1b842c89 | 7934 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 7935 | |
42a7b088 DL |
7936 | val = I915_READ(DSPCNTR(plane)); |
7937 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
7938 | return; | |
7939 | ||
d9806c9f | 7940 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 7941 | if (!intel_fb) { |
1ad292b5 JB |
7942 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7943 | return; | |
7944 | } | |
7945 | ||
1b842c89 DL |
7946 | fb = &intel_fb->base; |
7947 | ||
18c5247e DV |
7948 | if (INTEL_INFO(dev)->gen >= 4) { |
7949 | if (val & DISPPLANE_TILED) { | |
49af449b | 7950 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
7951 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
7952 | } | |
7953 | } | |
1ad292b5 JB |
7954 | |
7955 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 7956 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
7957 | fb->pixel_format = fourcc; |
7958 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
7959 | |
7960 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 7961 | if (plane_config->tiling) |
1ad292b5 JB |
7962 | offset = I915_READ(DSPTILEOFF(plane)); |
7963 | else | |
7964 | offset = I915_READ(DSPLINOFF(plane)); | |
7965 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
7966 | } else { | |
7967 | base = I915_READ(DSPADDR(plane)); | |
7968 | } | |
7969 | plane_config->base = base; | |
7970 | ||
7971 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
7972 | fb->width = ((val >> 16) & 0xfff) + 1; |
7973 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
7974 | |
7975 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 7976 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 7977 | |
b113d5ee | 7978 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
7979 | fb->pixel_format, |
7980 | fb->modifier[0]); | |
1ad292b5 | 7981 | |
f37b5c2b | 7982 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 7983 | |
2844a921 DL |
7984 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
7985 | pipe_name(pipe), plane, fb->width, fb->height, | |
7986 | fb->bits_per_pixel, base, fb->pitches[0], | |
7987 | plane_config->size); | |
1ad292b5 | 7988 | |
2d14030b | 7989 | plane_config->fb = intel_fb; |
1ad292b5 JB |
7990 | } |
7991 | ||
70b23a98 | 7992 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7993 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
7994 | { |
7995 | struct drm_device *dev = crtc->base.dev; | |
7996 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7997 | int pipe = pipe_config->cpu_transcoder; | |
7998 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
7999 | intel_clock_t clock; | |
0d7b6b11 | 8000 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
8001 | int refclk = 100000; |
8002 | ||
a580516d | 8003 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
8004 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
8005 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
8006 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
8007 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 8008 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 8009 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
8010 | |
8011 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
8012 | clock.m2 = (pll_dw0 & 0xff) << 22; |
8013 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
8014 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
8015 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
8016 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
8017 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
8018 | ||
dccbea3b | 8019 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
8020 | } |
8021 | ||
0e8ffe1b | 8022 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8023 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8024 | { |
8025 | struct drm_device *dev = crtc->base.dev; | |
8026 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1729050e | 8027 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 8028 | uint32_t tmp; |
1729050e | 8029 | bool ret; |
0e8ffe1b | 8030 | |
1729050e ID |
8031 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
8032 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 ID |
8033 | return false; |
8034 | ||
e143a21c | 8035 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 8036 | pipe_config->shared_dpll = NULL; |
eccb140b | 8037 | |
1729050e ID |
8038 | ret = false; |
8039 | ||
0e8ffe1b DV |
8040 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8041 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 8042 | goto out; |
0e8ffe1b | 8043 | |
666a4537 | 8044 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
42571aef VS |
8045 | switch (tmp & PIPECONF_BPC_MASK) { |
8046 | case PIPECONF_6BPC: | |
8047 | pipe_config->pipe_bpp = 18; | |
8048 | break; | |
8049 | case PIPECONF_8BPC: | |
8050 | pipe_config->pipe_bpp = 24; | |
8051 | break; | |
8052 | case PIPECONF_10BPC: | |
8053 | pipe_config->pipe_bpp = 30; | |
8054 | break; | |
8055 | default: | |
8056 | break; | |
8057 | } | |
8058 | } | |
8059 | ||
666a4537 WB |
8060 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
8061 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) | |
b5a9fa09 DV |
8062 | pipe_config->limited_color_range = true; |
8063 | ||
282740f7 VS |
8064 | if (INTEL_INFO(dev)->gen < 4) |
8065 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
8066 | ||
1bd1bd80 | 8067 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 8068 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 8069 | |
2fa2fe9a DV |
8070 | i9xx_get_pfit_config(crtc, pipe_config); |
8071 | ||
6c49f241 DV |
8072 | if (INTEL_INFO(dev)->gen >= 4) { |
8073 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
8074 | pipe_config->pixel_multiplier = | |
8075 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
8076 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 8077 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
8078 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
8079 | tmp = I915_READ(DPLL(crtc->pipe)); | |
8080 | pipe_config->pixel_multiplier = | |
8081 | ((tmp & SDVO_MULTIPLIER_MASK) | |
8082 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
8083 | } else { | |
8084 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
8085 | * port and will be fixed up in the encoder->get_config | |
8086 | * function. */ | |
8087 | pipe_config->pixel_multiplier = 1; | |
8088 | } | |
8bcc2795 | 8089 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
666a4537 | 8090 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
1c4e0274 VS |
8091 | /* |
8092 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
8093 | * on 830. Filter it out here so that we don't | |
8094 | * report errors due to that. | |
8095 | */ | |
8096 | if (IS_I830(dev)) | |
8097 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
8098 | ||
8bcc2795 DV |
8099 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
8100 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
8101 | } else { |
8102 | /* Mask out read-only status bits. */ | |
8103 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
8104 | DPLL_PORTC_READY_MASK | | |
8105 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 8106 | } |
6c49f241 | 8107 | |
70b23a98 VS |
8108 | if (IS_CHERRYVIEW(dev)) |
8109 | chv_crtc_clock_get(crtc, pipe_config); | |
8110 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
8111 | vlv_crtc_clock_get(crtc, pipe_config); |
8112 | else | |
8113 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 8114 | |
0f64614d VS |
8115 | /* |
8116 | * Normally the dotclock is filled in by the encoder .get_config() | |
8117 | * but in case the pipe is enabled w/o any ports we need a sane | |
8118 | * default. | |
8119 | */ | |
8120 | pipe_config->base.adjusted_mode.crtc_clock = | |
8121 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
8122 | ||
1729050e ID |
8123 | ret = true; |
8124 | ||
8125 | out: | |
8126 | intel_display_power_put(dev_priv, power_domain); | |
8127 | ||
8128 | return ret; | |
0e8ffe1b DV |
8129 | } |
8130 | ||
dde86e2d | 8131 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
8132 | { |
8133 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 8134 | struct intel_encoder *encoder; |
74cfd7ac | 8135 | u32 val, final; |
13d83a67 | 8136 | bool has_lvds = false; |
199e5d79 | 8137 | bool has_cpu_edp = false; |
199e5d79 | 8138 | bool has_panel = false; |
99eb6a01 KP |
8139 | bool has_ck505 = false; |
8140 | bool can_ssc = false; | |
13d83a67 JB |
8141 | |
8142 | /* We need to take the global config into account */ | |
b2784e15 | 8143 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
8144 | switch (encoder->type) { |
8145 | case INTEL_OUTPUT_LVDS: | |
8146 | has_panel = true; | |
8147 | has_lvds = true; | |
8148 | break; | |
8149 | case INTEL_OUTPUT_EDP: | |
8150 | has_panel = true; | |
2de6905f | 8151 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
8152 | has_cpu_edp = true; |
8153 | break; | |
6847d71b PZ |
8154 | default: |
8155 | break; | |
13d83a67 JB |
8156 | } |
8157 | } | |
8158 | ||
99eb6a01 | 8159 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 8160 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
8161 | can_ssc = has_ck505; |
8162 | } else { | |
8163 | has_ck505 = false; | |
8164 | can_ssc = true; | |
8165 | } | |
8166 | ||
2de6905f ID |
8167 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
8168 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
8169 | |
8170 | /* Ironlake: try to setup display ref clock before DPLL | |
8171 | * enabling. This is only under driver's control after | |
8172 | * PCH B stepping, previous chipset stepping should be | |
8173 | * ignoring this setting. | |
8174 | */ | |
74cfd7ac CW |
8175 | val = I915_READ(PCH_DREF_CONTROL); |
8176 | ||
8177 | /* As we must carefully and slowly disable/enable each source in turn, | |
8178 | * compute the final state we want first and check if we need to | |
8179 | * make any changes at all. | |
8180 | */ | |
8181 | final = val; | |
8182 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
8183 | if (has_ck505) | |
8184 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
8185 | else | |
8186 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
8187 | ||
8188 | final &= ~DREF_SSC_SOURCE_MASK; | |
8189 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
8190 | final &= ~DREF_SSC1_ENABLE; | |
8191 | ||
8192 | if (has_panel) { | |
8193 | final |= DREF_SSC_SOURCE_ENABLE; | |
8194 | ||
8195 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8196 | final |= DREF_SSC1_ENABLE; | |
8197 | ||
8198 | if (has_cpu_edp) { | |
8199 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8200 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
8201 | else | |
8202 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
8203 | } else | |
8204 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8205 | } else { | |
8206 | final |= DREF_SSC_SOURCE_DISABLE; | |
8207 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8208 | } | |
8209 | ||
8210 | if (final == val) | |
8211 | return; | |
8212 | ||
13d83a67 | 8213 | /* Always enable nonspread source */ |
74cfd7ac | 8214 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 8215 | |
99eb6a01 | 8216 | if (has_ck505) |
74cfd7ac | 8217 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 8218 | else |
74cfd7ac | 8219 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 8220 | |
199e5d79 | 8221 | if (has_panel) { |
74cfd7ac CW |
8222 | val &= ~DREF_SSC_SOURCE_MASK; |
8223 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 8224 | |
199e5d79 | 8225 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 8226 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8227 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 8228 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 8229 | } else |
74cfd7ac | 8230 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
8231 | |
8232 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 8233 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8234 | POSTING_READ(PCH_DREF_CONTROL); |
8235 | udelay(200); | |
8236 | ||
74cfd7ac | 8237 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
8238 | |
8239 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 8240 | if (has_cpu_edp) { |
99eb6a01 | 8241 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8242 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 8243 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 8244 | } else |
74cfd7ac | 8245 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 8246 | } else |
74cfd7ac | 8247 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8248 | |
74cfd7ac | 8249 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8250 | POSTING_READ(PCH_DREF_CONTROL); |
8251 | udelay(200); | |
8252 | } else { | |
8253 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
8254 | ||
74cfd7ac | 8255 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
8256 | |
8257 | /* Turn off CPU output */ | |
74cfd7ac | 8258 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8259 | |
74cfd7ac | 8260 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8261 | POSTING_READ(PCH_DREF_CONTROL); |
8262 | udelay(200); | |
8263 | ||
8264 | /* Turn off the SSC source */ | |
74cfd7ac CW |
8265 | val &= ~DREF_SSC_SOURCE_MASK; |
8266 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
8267 | |
8268 | /* Turn off SSC1 */ | |
74cfd7ac | 8269 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 8270 | |
74cfd7ac | 8271 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
8272 | POSTING_READ(PCH_DREF_CONTROL); |
8273 | udelay(200); | |
8274 | } | |
74cfd7ac CW |
8275 | |
8276 | BUG_ON(val != final); | |
13d83a67 JB |
8277 | } |
8278 | ||
f31f2d55 | 8279 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 8280 | { |
f31f2d55 | 8281 | uint32_t tmp; |
dde86e2d | 8282 | |
0ff066a9 PZ |
8283 | tmp = I915_READ(SOUTH_CHICKEN2); |
8284 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
8285 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8286 | |
0ff066a9 PZ |
8287 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
8288 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
8289 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 8290 | |
0ff066a9 PZ |
8291 | tmp = I915_READ(SOUTH_CHICKEN2); |
8292 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
8293 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8294 | |
0ff066a9 PZ |
8295 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
8296 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
8297 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
8298 | } |
8299 | ||
8300 | /* WaMPhyProgramming:hsw */ | |
8301 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
8302 | { | |
8303 | uint32_t tmp; | |
dde86e2d PZ |
8304 | |
8305 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
8306 | tmp &= ~(0xFF << 24); | |
8307 | tmp |= (0x12 << 24); | |
8308 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
8309 | ||
dde86e2d PZ |
8310 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
8311 | tmp |= (1 << 11); | |
8312 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
8313 | ||
8314 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
8315 | tmp |= (1 << 11); | |
8316 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
8317 | ||
dde86e2d PZ |
8318 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
8319 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8320 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
8321 | ||
8322 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
8323 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8324 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
8325 | ||
0ff066a9 PZ |
8326 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
8327 | tmp &= ~(7 << 13); | |
8328 | tmp |= (5 << 13); | |
8329 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 8330 | |
0ff066a9 PZ |
8331 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
8332 | tmp &= ~(7 << 13); | |
8333 | tmp |= (5 << 13); | |
8334 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
8335 | |
8336 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
8337 | tmp &= ~0xFF; | |
8338 | tmp |= 0x1C; | |
8339 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
8340 | ||
8341 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
8342 | tmp &= ~0xFF; | |
8343 | tmp |= 0x1C; | |
8344 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
8345 | ||
8346 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
8347 | tmp &= ~(0xFF << 16); | |
8348 | tmp |= (0x1C << 16); | |
8349 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
8350 | ||
8351 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
8352 | tmp &= ~(0xFF << 16); | |
8353 | tmp |= (0x1C << 16); | |
8354 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
8355 | ||
0ff066a9 PZ |
8356 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
8357 | tmp |= (1 << 27); | |
8358 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 8359 | |
0ff066a9 PZ |
8360 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
8361 | tmp |= (1 << 27); | |
8362 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 8363 | |
0ff066a9 PZ |
8364 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
8365 | tmp &= ~(0xF << 28); | |
8366 | tmp |= (4 << 28); | |
8367 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 8368 | |
0ff066a9 PZ |
8369 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
8370 | tmp &= ~(0xF << 28); | |
8371 | tmp |= (4 << 28); | |
8372 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
8373 | } |
8374 | ||
2fa86a1f PZ |
8375 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
8376 | * Programming" based on the parameters passed: | |
8377 | * - Sequence to enable CLKOUT_DP | |
8378 | * - Sequence to enable CLKOUT_DP without spread | |
8379 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
8380 | */ | |
8381 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
8382 | bool with_fdi) | |
f31f2d55 PZ |
8383 | { |
8384 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
8385 | uint32_t reg, tmp; |
8386 | ||
8387 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
8388 | with_spread = true; | |
c2699524 | 8389 | if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n")) |
2fa86a1f | 8390 | with_fdi = false; |
f31f2d55 | 8391 | |
a580516d | 8392 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
8393 | |
8394 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8395 | tmp &= ~SBI_SSCCTL_DISABLE; | |
8396 | tmp |= SBI_SSCCTL_PATHALT; | |
8397 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8398 | ||
8399 | udelay(24); | |
8400 | ||
2fa86a1f PZ |
8401 | if (with_spread) { |
8402 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8403 | tmp &= ~SBI_SSCCTL_PATHALT; | |
8404 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 8405 | |
2fa86a1f PZ |
8406 | if (with_fdi) { |
8407 | lpt_reset_fdi_mphy(dev_priv); | |
8408 | lpt_program_fdi_mphy(dev_priv); | |
8409 | } | |
8410 | } | |
dde86e2d | 8411 | |
c2699524 | 8412 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
8413 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8414 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8415 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 8416 | |
a580516d | 8417 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
8418 | } |
8419 | ||
47701c3b PZ |
8420 | /* Sequence to disable CLKOUT_DP */ |
8421 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
8422 | { | |
8423 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8424 | uint32_t reg, tmp; | |
8425 | ||
a580516d | 8426 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 8427 | |
c2699524 | 8428 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
8429 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8430 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8431 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
8432 | ||
8433 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8434 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
8435 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
8436 | tmp |= SBI_SSCCTL_PATHALT; | |
8437 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8438 | udelay(32); | |
8439 | } | |
8440 | tmp |= SBI_SSCCTL_DISABLE; | |
8441 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8442 | } | |
8443 | ||
a580516d | 8444 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
8445 | } |
8446 | ||
f7be2c21 VS |
8447 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
8448 | ||
8449 | static const uint16_t sscdivintphase[] = { | |
8450 | [BEND_IDX( 50)] = 0x3B23, | |
8451 | [BEND_IDX( 45)] = 0x3B23, | |
8452 | [BEND_IDX( 40)] = 0x3C23, | |
8453 | [BEND_IDX( 35)] = 0x3C23, | |
8454 | [BEND_IDX( 30)] = 0x3D23, | |
8455 | [BEND_IDX( 25)] = 0x3D23, | |
8456 | [BEND_IDX( 20)] = 0x3E23, | |
8457 | [BEND_IDX( 15)] = 0x3E23, | |
8458 | [BEND_IDX( 10)] = 0x3F23, | |
8459 | [BEND_IDX( 5)] = 0x3F23, | |
8460 | [BEND_IDX( 0)] = 0x0025, | |
8461 | [BEND_IDX( -5)] = 0x0025, | |
8462 | [BEND_IDX(-10)] = 0x0125, | |
8463 | [BEND_IDX(-15)] = 0x0125, | |
8464 | [BEND_IDX(-20)] = 0x0225, | |
8465 | [BEND_IDX(-25)] = 0x0225, | |
8466 | [BEND_IDX(-30)] = 0x0325, | |
8467 | [BEND_IDX(-35)] = 0x0325, | |
8468 | [BEND_IDX(-40)] = 0x0425, | |
8469 | [BEND_IDX(-45)] = 0x0425, | |
8470 | [BEND_IDX(-50)] = 0x0525, | |
8471 | }; | |
8472 | ||
8473 | /* | |
8474 | * Bend CLKOUT_DP | |
8475 | * steps -50 to 50 inclusive, in steps of 5 | |
8476 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) | |
8477 | * change in clock period = -(steps / 10) * 5.787 ps | |
8478 | */ | |
8479 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) | |
8480 | { | |
8481 | uint32_t tmp; | |
8482 | int idx = BEND_IDX(steps); | |
8483 | ||
8484 | if (WARN_ON(steps % 5 != 0)) | |
8485 | return; | |
8486 | ||
8487 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) | |
8488 | return; | |
8489 | ||
8490 | mutex_lock(&dev_priv->sb_lock); | |
8491 | ||
8492 | if (steps % 10 != 0) | |
8493 | tmp = 0xAAAAAAAB; | |
8494 | else | |
8495 | tmp = 0x00000000; | |
8496 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); | |
8497 | ||
8498 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); | |
8499 | tmp &= 0xffff0000; | |
8500 | tmp |= sscdivintphase[idx]; | |
8501 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); | |
8502 | ||
8503 | mutex_unlock(&dev_priv->sb_lock); | |
8504 | } | |
8505 | ||
8506 | #undef BEND_IDX | |
8507 | ||
bf8fa3d3 PZ |
8508 | static void lpt_init_pch_refclk(struct drm_device *dev) |
8509 | { | |
bf8fa3d3 PZ |
8510 | struct intel_encoder *encoder; |
8511 | bool has_vga = false; | |
8512 | ||
b2784e15 | 8513 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
8514 | switch (encoder->type) { |
8515 | case INTEL_OUTPUT_ANALOG: | |
8516 | has_vga = true; | |
8517 | break; | |
6847d71b PZ |
8518 | default: |
8519 | break; | |
bf8fa3d3 PZ |
8520 | } |
8521 | } | |
8522 | ||
f7be2c21 VS |
8523 | if (has_vga) { |
8524 | lpt_bend_clkout_dp(to_i915(dev), 0); | |
47701c3b | 8525 | lpt_enable_clkout_dp(dev, true, true); |
f7be2c21 | 8526 | } else { |
47701c3b | 8527 | lpt_disable_clkout_dp(dev); |
f7be2c21 | 8528 | } |
bf8fa3d3 PZ |
8529 | } |
8530 | ||
dde86e2d PZ |
8531 | /* |
8532 | * Initialize reference clocks when the driver loads | |
8533 | */ | |
8534 | void intel_init_pch_refclk(struct drm_device *dev) | |
8535 | { | |
8536 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
8537 | ironlake_init_pch_refclk(dev); | |
8538 | else if (HAS_PCH_LPT(dev)) | |
8539 | lpt_init_pch_refclk(dev); | |
8540 | } | |
8541 | ||
6ff93609 | 8542 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 8543 | { |
c8203565 | 8544 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
8545 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8546 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
8547 | uint32_t val; |
8548 | ||
78114071 | 8549 | val = 0; |
c8203565 | 8550 | |
6e3c9717 | 8551 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 8552 | case 18: |
dfd07d72 | 8553 | val |= PIPECONF_6BPC; |
c8203565 PZ |
8554 | break; |
8555 | case 24: | |
dfd07d72 | 8556 | val |= PIPECONF_8BPC; |
c8203565 PZ |
8557 | break; |
8558 | case 30: | |
dfd07d72 | 8559 | val |= PIPECONF_10BPC; |
c8203565 PZ |
8560 | break; |
8561 | case 36: | |
dfd07d72 | 8562 | val |= PIPECONF_12BPC; |
c8203565 PZ |
8563 | break; |
8564 | default: | |
cc769b62 PZ |
8565 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
8566 | BUG(); | |
c8203565 PZ |
8567 | } |
8568 | ||
6e3c9717 | 8569 | if (intel_crtc->config->dither) |
c8203565 PZ |
8570 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8571 | ||
6e3c9717 | 8572 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
8573 | val |= PIPECONF_INTERLACED_ILK; |
8574 | else | |
8575 | val |= PIPECONF_PROGRESSIVE; | |
8576 | ||
6e3c9717 | 8577 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 8578 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 8579 | |
c8203565 PZ |
8580 | I915_WRITE(PIPECONF(pipe), val); |
8581 | POSTING_READ(PIPECONF(pipe)); | |
8582 | } | |
8583 | ||
6ff93609 | 8584 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8585 | { |
391bf048 | 8586 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
ee2b0b38 | 8587 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 8588 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
391bf048 | 8589 | u32 val = 0; |
ee2b0b38 | 8590 | |
391bf048 | 8591 | if (IS_HASWELL(dev_priv) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8592 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8593 | ||
6e3c9717 | 8594 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8595 | val |= PIPECONF_INTERLACED_ILK; |
8596 | else | |
8597 | val |= PIPECONF_PROGRESSIVE; | |
8598 | ||
702e7a56 PZ |
8599 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8600 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
391bf048 JN |
8601 | } |
8602 | ||
391bf048 JN |
8603 | static void haswell_set_pipemisc(struct drm_crtc *crtc) |
8604 | { | |
8605 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
8606 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
756f85cf | 8607 | |
391bf048 JN |
8608 | if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) { |
8609 | u32 val = 0; | |
756f85cf | 8610 | |
6e3c9717 | 8611 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8612 | case 18: |
8613 | val |= PIPEMISC_DITHER_6_BPC; | |
8614 | break; | |
8615 | case 24: | |
8616 | val |= PIPEMISC_DITHER_8_BPC; | |
8617 | break; | |
8618 | case 30: | |
8619 | val |= PIPEMISC_DITHER_10_BPC; | |
8620 | break; | |
8621 | case 36: | |
8622 | val |= PIPEMISC_DITHER_12_BPC; | |
8623 | break; | |
8624 | default: | |
8625 | /* Case prevented by pipe_config_set_bpp. */ | |
8626 | BUG(); | |
8627 | } | |
8628 | ||
6e3c9717 | 8629 | if (intel_crtc->config->dither) |
756f85cf PZ |
8630 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8631 | ||
391bf048 | 8632 | I915_WRITE(PIPEMISC(intel_crtc->pipe), val); |
756f85cf | 8633 | } |
ee2b0b38 PZ |
8634 | } |
8635 | ||
d4b1931c PZ |
8636 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
8637 | { | |
8638 | /* | |
8639 | * Account for spread spectrum to avoid | |
8640 | * oversubscribing the link. Max center spread | |
8641 | * is 2.5%; use 5% for safety's sake. | |
8642 | */ | |
8643 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 8644 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
8645 | } |
8646 | ||
7429e9d4 | 8647 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 8648 | { |
7429e9d4 | 8649 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
8650 | } |
8651 | ||
b75ca6f6 ACO |
8652 | static void ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
8653 | struct intel_crtc_state *crtc_state, | |
8654 | intel_clock_t *reduced_clock) | |
79e53945 | 8655 | { |
de13a2e3 | 8656 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
8657 | struct drm_device *dev = crtc->dev; |
8658 | struct drm_i915_private *dev_priv = dev->dev_private; | |
55bb9992 | 8659 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8660 | struct drm_connector *connector; |
55bb9992 ACO |
8661 | struct drm_connector_state *connector_state; |
8662 | struct intel_encoder *encoder; | |
b75ca6f6 | 8663 | u32 dpll, fp, fp2; |
ceb41007 | 8664 | int factor, i; |
09ede541 | 8665 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 8666 | |
da3ced29 | 8667 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8668 | if (connector_state->crtc != crtc_state->base.crtc) |
8669 | continue; | |
8670 | ||
8671 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8672 | ||
8673 | switch (encoder->type) { | |
79e53945 JB |
8674 | case INTEL_OUTPUT_LVDS: |
8675 | is_lvds = true; | |
8676 | break; | |
8677 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 8678 | case INTEL_OUTPUT_HDMI: |
79e53945 | 8679 | is_sdvo = true; |
79e53945 | 8680 | break; |
6847d71b PZ |
8681 | default: |
8682 | break; | |
79e53945 JB |
8683 | } |
8684 | } | |
79e53945 | 8685 | |
c1858123 | 8686 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
8687 | factor = 21; |
8688 | if (is_lvds) { | |
8689 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 8690 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 8691 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 8692 | factor = 25; |
190f68c5 | 8693 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 8694 | factor = 20; |
c1858123 | 8695 | |
b75ca6f6 ACO |
8696 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
8697 | ||
190f68c5 | 8698 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
b75ca6f6 ACO |
8699 | fp |= FP_CB_TUNE; |
8700 | ||
8701 | if (reduced_clock) { | |
8702 | fp2 = i9xx_dpll_compute_fp(reduced_clock); | |
2c07245f | 8703 | |
b75ca6f6 ACO |
8704 | if (reduced_clock->m < factor * reduced_clock->n) |
8705 | fp2 |= FP_CB_TUNE; | |
8706 | } else { | |
8707 | fp2 = fp; | |
8708 | } | |
9a7c7890 | 8709 | |
5eddb70b | 8710 | dpll = 0; |
2c07245f | 8711 | |
a07d6787 EA |
8712 | if (is_lvds) |
8713 | dpll |= DPLLB_MODE_LVDS; | |
8714 | else | |
8715 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 8716 | |
190f68c5 | 8717 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8718 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f DV |
8719 | |
8720 | if (is_sdvo) | |
4a33e48d | 8721 | dpll |= DPLL_SDVO_HIGH_SPEED; |
190f68c5 | 8722 | if (crtc_state->has_dp_encoder) |
4a33e48d | 8723 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 8724 | |
a07d6787 | 8725 | /* compute bitmask from p1 value */ |
190f68c5 | 8726 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 8727 | /* also FPA1 */ |
190f68c5 | 8728 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 8729 | |
190f68c5 | 8730 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
8731 | case 5: |
8732 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8733 | break; | |
8734 | case 7: | |
8735 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8736 | break; | |
8737 | case 10: | |
8738 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8739 | break; | |
8740 | case 14: | |
8741 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8742 | break; | |
79e53945 JB |
8743 | } |
8744 | ||
ceb41007 | 8745 | if (is_lvds && intel_panel_use_ssc(dev_priv)) |
43565a06 | 8746 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
8747 | else |
8748 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8749 | ||
b75ca6f6 ACO |
8750 | dpll |= DPLL_VCO_ENABLE; |
8751 | ||
8752 | crtc_state->dpll_hw_state.dpll = dpll; | |
8753 | crtc_state->dpll_hw_state.fp0 = fp; | |
8754 | crtc_state->dpll_hw_state.fp1 = fp2; | |
de13a2e3 PZ |
8755 | } |
8756 | ||
190f68c5 ACO |
8757 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
8758 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 8759 | { |
997c030c ACO |
8760 | struct drm_device *dev = crtc->base.dev; |
8761 | struct drm_i915_private *dev_priv = dev->dev_private; | |
364ee29d | 8762 | intel_clock_t reduced_clock; |
7ed9f894 | 8763 | bool has_reduced_clock = false; |
e2b78267 | 8764 | struct intel_shared_dpll *pll; |
997c030c ACO |
8765 | const intel_limit_t *limit; |
8766 | int refclk = 120000; | |
de13a2e3 | 8767 | |
dd3cd74a ACO |
8768 | memset(&crtc_state->dpll_hw_state, 0, |
8769 | sizeof(crtc_state->dpll_hw_state)); | |
8770 | ||
ded220e2 ACO |
8771 | crtc->lowfreq_avail = false; |
8772 | ||
8773 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ | |
8774 | if (!crtc_state->has_pch_encoder) | |
8775 | return 0; | |
79e53945 | 8776 | |
997c030c ACO |
8777 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
8778 | if (intel_panel_use_ssc(dev_priv)) { | |
8779 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", | |
8780 | dev_priv->vbt.lvds_ssc_freq); | |
8781 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8782 | } | |
8783 | ||
8784 | if (intel_is_dual_link_lvds(dev)) { | |
8785 | if (refclk == 100000) | |
8786 | limit = &intel_limits_ironlake_dual_lvds_100m; | |
8787 | else | |
8788 | limit = &intel_limits_ironlake_dual_lvds; | |
8789 | } else { | |
8790 | if (refclk == 100000) | |
8791 | limit = &intel_limits_ironlake_single_lvds_100m; | |
8792 | else | |
8793 | limit = &intel_limits_ironlake_single_lvds; | |
8794 | } | |
8795 | } else { | |
8796 | limit = &intel_limits_ironlake_dac; | |
8797 | } | |
8798 | ||
364ee29d | 8799 | if (!crtc_state->clock_set && |
997c030c ACO |
8800 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
8801 | refclk, NULL, &crtc_state->dpll)) { | |
364ee29d ACO |
8802 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
8803 | return -EINVAL; | |
f47709a9 | 8804 | } |
79e53945 | 8805 | |
b75ca6f6 ACO |
8806 | ironlake_compute_dpll(crtc, crtc_state, |
8807 | has_reduced_clock ? &reduced_clock : NULL); | |
66e985c0 | 8808 | |
ded220e2 ACO |
8809 | pll = intel_get_shared_dpll(crtc, crtc_state, NULL); |
8810 | if (pll == NULL) { | |
8811 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
8812 | pipe_name(crtc->pipe)); | |
8813 | return -EINVAL; | |
3fb37703 | 8814 | } |
79e53945 | 8815 | |
ded220e2 ACO |
8816 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
8817 | has_reduced_clock) | |
c7653199 | 8818 | crtc->lowfreq_avail = true; |
e2b78267 | 8819 | |
c8f7a0db | 8820 | return 0; |
79e53945 JB |
8821 | } |
8822 | ||
eb14cb74 VS |
8823 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
8824 | struct intel_link_m_n *m_n) | |
8825 | { | |
8826 | struct drm_device *dev = crtc->base.dev; | |
8827 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8828 | enum pipe pipe = crtc->pipe; | |
8829 | ||
8830 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
8831 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
8832 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8833 | & ~TU_SIZE_MASK; | |
8834 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
8835 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8836 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8837 | } | |
8838 | ||
8839 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
8840 | enum transcoder transcoder, | |
b95af8be VK |
8841 | struct intel_link_m_n *m_n, |
8842 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
8843 | { |
8844 | struct drm_device *dev = crtc->base.dev; | |
8845 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 8846 | enum pipe pipe = crtc->pipe; |
72419203 | 8847 | |
eb14cb74 VS |
8848 | if (INTEL_INFO(dev)->gen >= 5) { |
8849 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
8850 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
8851 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
8852 | & ~TU_SIZE_MASK; | |
8853 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
8854 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
8855 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
8856 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
8857 | * gen < 8) and if DRRS is supported (to make sure the | |
8858 | * registers are not unnecessarily read). | |
8859 | */ | |
8860 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 8861 | crtc->config->has_drrs) { |
b95af8be VK |
8862 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
8863 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
8864 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
8865 | & ~TU_SIZE_MASK; | |
8866 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
8867 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
8868 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8869 | } | |
eb14cb74 VS |
8870 | } else { |
8871 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
8872 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
8873 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8874 | & ~TU_SIZE_MASK; | |
8875 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
8876 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8877 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8878 | } | |
8879 | } | |
8880 | ||
8881 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 8882 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 8883 | { |
681a8504 | 8884 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
8885 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
8886 | else | |
8887 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
8888 | &pipe_config->dp_m_n, |
8889 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 8890 | } |
72419203 | 8891 | |
eb14cb74 | 8892 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 8893 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
8894 | { |
8895 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 8896 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
8897 | } |
8898 | ||
bd2e244f | 8899 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8900 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
8901 | { |
8902 | struct drm_device *dev = crtc->base.dev; | |
8903 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a1b2278e CK |
8904 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
8905 | uint32_t ps_ctrl = 0; | |
8906 | int id = -1; | |
8907 | int i; | |
bd2e244f | 8908 | |
a1b2278e CK |
8909 | /* find scaler attached to this pipe */ |
8910 | for (i = 0; i < crtc->num_scalers; i++) { | |
8911 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
8912 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
8913 | id = i; | |
8914 | pipe_config->pch_pfit.enabled = true; | |
8915 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
8916 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
8917 | break; | |
8918 | } | |
8919 | } | |
bd2e244f | 8920 | |
a1b2278e CK |
8921 | scaler_state->scaler_id = id; |
8922 | if (id >= 0) { | |
8923 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
8924 | } else { | |
8925 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
8926 | } |
8927 | } | |
8928 | ||
5724dbd1 DL |
8929 | static void |
8930 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
8931 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
8932 | { |
8933 | struct drm_device *dev = crtc->base.dev; | |
8934 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40f46283 | 8935 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
8936 | int pipe = crtc->pipe; |
8937 | int fourcc, pixel_format; | |
6761dd31 | 8938 | unsigned int aligned_height; |
bc8d7dff | 8939 | struct drm_framebuffer *fb; |
1b842c89 | 8940 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 8941 | |
d9806c9f | 8942 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8943 | if (!intel_fb) { |
bc8d7dff DL |
8944 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8945 | return; | |
8946 | } | |
8947 | ||
1b842c89 DL |
8948 | fb = &intel_fb->base; |
8949 | ||
bc8d7dff | 8950 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
8951 | if (!(val & PLANE_CTL_ENABLE)) |
8952 | goto error; | |
8953 | ||
bc8d7dff DL |
8954 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
8955 | fourcc = skl_format_to_fourcc(pixel_format, | |
8956 | val & PLANE_CTL_ORDER_RGBX, | |
8957 | val & PLANE_CTL_ALPHA_MASK); | |
8958 | fb->pixel_format = fourcc; | |
8959 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
8960 | ||
40f46283 DL |
8961 | tiling = val & PLANE_CTL_TILED_MASK; |
8962 | switch (tiling) { | |
8963 | case PLANE_CTL_TILED_LINEAR: | |
8964 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
8965 | break; | |
8966 | case PLANE_CTL_TILED_X: | |
8967 | plane_config->tiling = I915_TILING_X; | |
8968 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
8969 | break; | |
8970 | case PLANE_CTL_TILED_Y: | |
8971 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
8972 | break; | |
8973 | case PLANE_CTL_TILED_YF: | |
8974 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
8975 | break; | |
8976 | default: | |
8977 | MISSING_CASE(tiling); | |
8978 | goto error; | |
8979 | } | |
8980 | ||
bc8d7dff DL |
8981 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
8982 | plane_config->base = base; | |
8983 | ||
8984 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
8985 | ||
8986 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
8987 | fb->height = ((val >> 16) & 0xfff) + 1; | |
8988 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
8989 | ||
8990 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
7b49f948 | 8991 | stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
40f46283 | 8992 | fb->pixel_format); |
bc8d7dff DL |
8993 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
8994 | ||
8995 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
8996 | fb->pixel_format, |
8997 | fb->modifier[0]); | |
bc8d7dff | 8998 | |
f37b5c2b | 8999 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
9000 | |
9001 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
9002 | pipe_name(pipe), fb->width, fb->height, | |
9003 | fb->bits_per_pixel, base, fb->pitches[0], | |
9004 | plane_config->size); | |
9005 | ||
2d14030b | 9006 | plane_config->fb = intel_fb; |
bc8d7dff DL |
9007 | return; |
9008 | ||
9009 | error: | |
9010 | kfree(fb); | |
9011 | } | |
9012 | ||
2fa2fe9a | 9013 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9014 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
9015 | { |
9016 | struct drm_device *dev = crtc->base.dev; | |
9017 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9018 | uint32_t tmp; | |
9019 | ||
9020 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
9021 | ||
9022 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 9023 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
9024 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
9025 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
9026 | |
9027 | /* We currently do not free assignements of panel fitters on | |
9028 | * ivb/hsw (since we don't use the higher upscaling modes which | |
9029 | * differentiates them) so just WARN about this case for now. */ | |
9030 | if (IS_GEN7(dev)) { | |
9031 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
9032 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
9033 | } | |
2fa2fe9a | 9034 | } |
79e53945 JB |
9035 | } |
9036 | ||
5724dbd1 DL |
9037 | static void |
9038 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
9039 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
9040 | { |
9041 | struct drm_device *dev = crtc->base.dev; | |
9042 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9043 | u32 val, base, offset; | |
aeee5a49 | 9044 | int pipe = crtc->pipe; |
4c6baa59 | 9045 | int fourcc, pixel_format; |
6761dd31 | 9046 | unsigned int aligned_height; |
b113d5ee | 9047 | struct drm_framebuffer *fb; |
1b842c89 | 9048 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 9049 | |
42a7b088 DL |
9050 | val = I915_READ(DSPCNTR(pipe)); |
9051 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
9052 | return; | |
9053 | ||
d9806c9f | 9054 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9055 | if (!intel_fb) { |
4c6baa59 JB |
9056 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9057 | return; | |
9058 | } | |
9059 | ||
1b842c89 DL |
9060 | fb = &intel_fb->base; |
9061 | ||
18c5247e DV |
9062 | if (INTEL_INFO(dev)->gen >= 4) { |
9063 | if (val & DISPPLANE_TILED) { | |
49af449b | 9064 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
9065 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
9066 | } | |
9067 | } | |
4c6baa59 JB |
9068 | |
9069 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 9070 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
9071 | fb->pixel_format = fourcc; |
9072 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 9073 | |
aeee5a49 | 9074 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 9075 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 9076 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 9077 | } else { |
49af449b | 9078 | if (plane_config->tiling) |
aeee5a49 | 9079 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 9080 | else |
aeee5a49 | 9081 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
9082 | } |
9083 | plane_config->base = base; | |
9084 | ||
9085 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
9086 | fb->width = ((val >> 16) & 0xfff) + 1; |
9087 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
9088 | |
9089 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 9090 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 9091 | |
b113d5ee | 9092 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
9093 | fb->pixel_format, |
9094 | fb->modifier[0]); | |
4c6baa59 | 9095 | |
f37b5c2b | 9096 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 9097 | |
2844a921 DL |
9098 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
9099 | pipe_name(pipe), fb->width, fb->height, | |
9100 | fb->bits_per_pixel, base, fb->pitches[0], | |
9101 | plane_config->size); | |
b113d5ee | 9102 | |
2d14030b | 9103 | plane_config->fb = intel_fb; |
4c6baa59 JB |
9104 | } |
9105 | ||
0e8ffe1b | 9106 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9107 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9108 | { |
9109 | struct drm_device *dev = crtc->base.dev; | |
9110 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1729050e | 9111 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 9112 | uint32_t tmp; |
1729050e | 9113 | bool ret; |
0e8ffe1b | 9114 | |
1729050e ID |
9115 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
9116 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
930e8c9e PZ |
9117 | return false; |
9118 | ||
e143a21c | 9119 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 9120 | pipe_config->shared_dpll = NULL; |
eccb140b | 9121 | |
1729050e | 9122 | ret = false; |
0e8ffe1b DV |
9123 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
9124 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 9125 | goto out; |
0e8ffe1b | 9126 | |
42571aef VS |
9127 | switch (tmp & PIPECONF_BPC_MASK) { |
9128 | case PIPECONF_6BPC: | |
9129 | pipe_config->pipe_bpp = 18; | |
9130 | break; | |
9131 | case PIPECONF_8BPC: | |
9132 | pipe_config->pipe_bpp = 24; | |
9133 | break; | |
9134 | case PIPECONF_10BPC: | |
9135 | pipe_config->pipe_bpp = 30; | |
9136 | break; | |
9137 | case PIPECONF_12BPC: | |
9138 | pipe_config->pipe_bpp = 36; | |
9139 | break; | |
9140 | default: | |
9141 | break; | |
9142 | } | |
9143 | ||
b5a9fa09 DV |
9144 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
9145 | pipe_config->limited_color_range = true; | |
9146 | ||
ab9412ba | 9147 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 | 9148 | struct intel_shared_dpll *pll; |
8106ddbd | 9149 | enum intel_dpll_id pll_id; |
66e985c0 | 9150 | |
88adfff1 DV |
9151 | pipe_config->has_pch_encoder = true; |
9152 | ||
627eb5a3 DV |
9153 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
9154 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9155 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
9156 | |
9157 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 9158 | |
c0d43d62 | 9159 | if (HAS_PCH_IBX(dev_priv->dev)) { |
8106ddbd | 9160 | pll_id = (enum intel_dpll_id) crtc->pipe; |
c0d43d62 DV |
9161 | } else { |
9162 | tmp = I915_READ(PCH_DPLL_SEL); | |
9163 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
8106ddbd | 9164 | pll_id = DPLL_ID_PCH_PLL_B; |
c0d43d62 | 9165 | else |
8106ddbd | 9166 | pll_id= DPLL_ID_PCH_PLL_A; |
c0d43d62 | 9167 | } |
66e985c0 | 9168 | |
8106ddbd ACO |
9169 | pipe_config->shared_dpll = |
9170 | intel_get_shared_dpll_by_id(dev_priv, pll_id); | |
9171 | pll = pipe_config->shared_dpll; | |
66e985c0 | 9172 | |
2edd6443 ACO |
9173 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
9174 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
9175 | |
9176 | tmp = pipe_config->dpll_hw_state.dpll; | |
9177 | pipe_config->pixel_multiplier = | |
9178 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
9179 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
9180 | |
9181 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
9182 | } else { |
9183 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
9184 | } |
9185 | ||
1bd1bd80 | 9186 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 9187 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 9188 | |
2fa2fe9a DV |
9189 | ironlake_get_pfit_config(crtc, pipe_config); |
9190 | ||
1729050e ID |
9191 | ret = true; |
9192 | ||
9193 | out: | |
9194 | intel_display_power_put(dev_priv, power_domain); | |
9195 | ||
9196 | return ret; | |
0e8ffe1b DV |
9197 | } |
9198 | ||
be256dc7 PZ |
9199 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
9200 | { | |
9201 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 9202 | struct intel_crtc *crtc; |
be256dc7 | 9203 | |
d3fcc808 | 9204 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 9205 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
9206 | pipe_name(crtc->pipe)); |
9207 | ||
e2c719b7 RC |
9208 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
9209 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
01403de3 VS |
9210 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
9211 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
e2c719b7 RC |
9212 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
9213 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
be256dc7 | 9214 | "CPU PWM1 enabled\n"); |
c5107b87 | 9215 | if (IS_HASWELL(dev)) |
e2c719b7 | 9216 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 9217 | "CPU PWM2 enabled\n"); |
e2c719b7 | 9218 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 9219 | "PCH PWM1 enabled\n"); |
e2c719b7 | 9220 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 9221 | "Utility pin enabled\n"); |
e2c719b7 | 9222 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 9223 | |
9926ada1 PZ |
9224 | /* |
9225 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
9226 | * interrupts remain enabled. We used to check for that, but since it's | |
9227 | * gen-specific and since we only disable LCPLL after we fully disable | |
9228 | * the interrupts, the check below should be enough. | |
9229 | */ | |
e2c719b7 | 9230 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
9231 | } |
9232 | ||
9ccd5aeb PZ |
9233 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
9234 | { | |
9235 | struct drm_device *dev = dev_priv->dev; | |
9236 | ||
9237 | if (IS_HASWELL(dev)) | |
9238 | return I915_READ(D_COMP_HSW); | |
9239 | else | |
9240 | return I915_READ(D_COMP_BDW); | |
9241 | } | |
9242 | ||
3c4c9b81 PZ |
9243 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
9244 | { | |
9245 | struct drm_device *dev = dev_priv->dev; | |
9246 | ||
9247 | if (IS_HASWELL(dev)) { | |
9248 | mutex_lock(&dev_priv->rps.hw_lock); | |
9249 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
9250 | val)) | |
f475dadf | 9251 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
9252 | mutex_unlock(&dev_priv->rps.hw_lock); |
9253 | } else { | |
9ccd5aeb PZ |
9254 | I915_WRITE(D_COMP_BDW, val); |
9255 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 9256 | } |
be256dc7 PZ |
9257 | } |
9258 | ||
9259 | /* | |
9260 | * This function implements pieces of two sequences from BSpec: | |
9261 | * - Sequence for display software to disable LCPLL | |
9262 | * - Sequence for display software to allow package C8+ | |
9263 | * The steps implemented here are just the steps that actually touch the LCPLL | |
9264 | * register. Callers should take care of disabling all the display engine | |
9265 | * functions, doing the mode unset, fixing interrupts, etc. | |
9266 | */ | |
6ff58d53 PZ |
9267 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
9268 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
9269 | { |
9270 | uint32_t val; | |
9271 | ||
9272 | assert_can_disable_lcpll(dev_priv); | |
9273 | ||
9274 | val = I915_READ(LCPLL_CTL); | |
9275 | ||
9276 | if (switch_to_fclk) { | |
9277 | val |= LCPLL_CD_SOURCE_FCLK; | |
9278 | I915_WRITE(LCPLL_CTL, val); | |
9279 | ||
9280 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9281 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9282 | DRM_ERROR("Switching to FCLK failed\n"); | |
9283 | ||
9284 | val = I915_READ(LCPLL_CTL); | |
9285 | } | |
9286 | ||
9287 | val |= LCPLL_PLL_DISABLE; | |
9288 | I915_WRITE(LCPLL_CTL, val); | |
9289 | POSTING_READ(LCPLL_CTL); | |
9290 | ||
9291 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
9292 | DRM_ERROR("LCPLL still locked\n"); | |
9293 | ||
9ccd5aeb | 9294 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 9295 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 9296 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9297 | ndelay(100); |
9298 | ||
9ccd5aeb PZ |
9299 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
9300 | 1)) | |
be256dc7 PZ |
9301 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
9302 | ||
9303 | if (allow_power_down) { | |
9304 | val = I915_READ(LCPLL_CTL); | |
9305 | val |= LCPLL_POWER_DOWN_ALLOW; | |
9306 | I915_WRITE(LCPLL_CTL, val); | |
9307 | POSTING_READ(LCPLL_CTL); | |
9308 | } | |
9309 | } | |
9310 | ||
9311 | /* | |
9312 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
9313 | * source. | |
9314 | */ | |
6ff58d53 | 9315 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
9316 | { |
9317 | uint32_t val; | |
9318 | ||
9319 | val = I915_READ(LCPLL_CTL); | |
9320 | ||
9321 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
9322 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
9323 | return; | |
9324 | ||
a8a8bd54 PZ |
9325 | /* |
9326 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
9327 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 9328 | */ |
59bad947 | 9329 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 9330 | |
be256dc7 PZ |
9331 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
9332 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
9333 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 9334 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
9335 | } |
9336 | ||
9ccd5aeb | 9337 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
9338 | val |= D_COMP_COMP_FORCE; |
9339 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 9340 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9341 | |
9342 | val = I915_READ(LCPLL_CTL); | |
9343 | val &= ~LCPLL_PLL_DISABLE; | |
9344 | I915_WRITE(LCPLL_CTL, val); | |
9345 | ||
9346 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
9347 | DRM_ERROR("LCPLL not locked yet\n"); | |
9348 | ||
9349 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
9350 | val = I915_READ(LCPLL_CTL); | |
9351 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9352 | I915_WRITE(LCPLL_CTL, val); | |
9353 | ||
9354 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9355 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9356 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9357 | } | |
215733fa | 9358 | |
59bad947 | 9359 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b6283055 | 9360 | intel_update_cdclk(dev_priv->dev); |
be256dc7 PZ |
9361 | } |
9362 | ||
765dab67 PZ |
9363 | /* |
9364 | * Package states C8 and deeper are really deep PC states that can only be | |
9365 | * reached when all the devices on the system allow it, so even if the graphics | |
9366 | * device allows PC8+, it doesn't mean the system will actually get to these | |
9367 | * states. Our driver only allows PC8+ when going into runtime PM. | |
9368 | * | |
9369 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
9370 | * well is disabled and most interrupts are disabled, and these are also | |
9371 | * requirements for runtime PM. When these conditions are met, we manually do | |
9372 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
9373 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
9374 | * hang the machine. | |
9375 | * | |
9376 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
9377 | * the state of some registers, so when we come back from PC8+ we need to | |
9378 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
9379 | * need to take care of the registers kept by RC6. Notice that this happens even | |
9380 | * if we don't put the device in PCI D3 state (which is what currently happens | |
9381 | * because of the runtime PM support). | |
9382 | * | |
9383 | * For more, read "Display Sequences for Package C8" on the hardware | |
9384 | * documentation. | |
9385 | */ | |
a14cb6fc | 9386 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 9387 | { |
c67a470b PZ |
9388 | struct drm_device *dev = dev_priv->dev; |
9389 | uint32_t val; | |
9390 | ||
c67a470b PZ |
9391 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
9392 | ||
c2699524 | 9393 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9394 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9395 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
9396 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9397 | } | |
9398 | ||
9399 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
9400 | hsw_disable_lcpll(dev_priv, true, true); |
9401 | } | |
9402 | ||
a14cb6fc | 9403 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
9404 | { |
9405 | struct drm_device *dev = dev_priv->dev; | |
9406 | uint32_t val; | |
9407 | ||
c67a470b PZ |
9408 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
9409 | ||
9410 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
9411 | lpt_init_pch_refclk(dev); |
9412 | ||
c2699524 | 9413 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9414 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9415 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
9416 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9417 | } | |
c67a470b PZ |
9418 | } |
9419 | ||
27c329ed | 9420 | static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
f8437dd1 | 9421 | { |
a821fc46 | 9422 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
9423 | struct intel_atomic_state *old_intel_state = |
9424 | to_intel_atomic_state(old_state); | |
9425 | unsigned int req_cdclk = old_intel_state->dev_cdclk; | |
f8437dd1 | 9426 | |
27c329ed | 9427 | broxton_set_cdclk(dev, req_cdclk); |
f8437dd1 VK |
9428 | } |
9429 | ||
b432e5cf | 9430 | /* compute the max rate for new configuration */ |
27c329ed | 9431 | static int ilk_max_pixel_rate(struct drm_atomic_state *state) |
b432e5cf | 9432 | { |
565602d7 ML |
9433 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
9434 | struct drm_i915_private *dev_priv = state->dev->dev_private; | |
9435 | struct drm_crtc *crtc; | |
9436 | struct drm_crtc_state *cstate; | |
27c329ed | 9437 | struct intel_crtc_state *crtc_state; |
565602d7 ML |
9438 | unsigned max_pixel_rate = 0, i; |
9439 | enum pipe pipe; | |
b432e5cf | 9440 | |
565602d7 ML |
9441 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
9442 | sizeof(intel_state->min_pixclk)); | |
27c329ed | 9443 | |
565602d7 ML |
9444 | for_each_crtc_in_state(state, crtc, cstate, i) { |
9445 | int pixel_rate; | |
27c329ed | 9446 | |
565602d7 ML |
9447 | crtc_state = to_intel_crtc_state(cstate); |
9448 | if (!crtc_state->base.enable) { | |
9449 | intel_state->min_pixclk[i] = 0; | |
b432e5cf | 9450 | continue; |
565602d7 | 9451 | } |
b432e5cf | 9452 | |
27c329ed | 9453 | pixel_rate = ilk_pipe_pixel_rate(crtc_state); |
b432e5cf VS |
9454 | |
9455 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
565602d7 | 9456 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) |
b432e5cf VS |
9457 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); |
9458 | ||
565602d7 | 9459 | intel_state->min_pixclk[i] = pixel_rate; |
b432e5cf VS |
9460 | } |
9461 | ||
565602d7 ML |
9462 | for_each_pipe(dev_priv, pipe) |
9463 | max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate); | |
9464 | ||
b432e5cf VS |
9465 | return max_pixel_rate; |
9466 | } | |
9467 | ||
9468 | static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) | |
9469 | { | |
9470 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9471 | uint32_t val, data; | |
9472 | int ret; | |
9473 | ||
9474 | if (WARN((I915_READ(LCPLL_CTL) & | |
9475 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | | |
9476 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | | |
9477 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | | |
9478 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, | |
9479 | "trying to change cdclk frequency with cdclk not enabled\n")) | |
9480 | return; | |
9481 | ||
9482 | mutex_lock(&dev_priv->rps.hw_lock); | |
9483 | ret = sandybridge_pcode_write(dev_priv, | |
9484 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); | |
9485 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9486 | if (ret) { | |
9487 | DRM_ERROR("failed to inform pcode about cdclk change\n"); | |
9488 | return; | |
9489 | } | |
9490 | ||
9491 | val = I915_READ(LCPLL_CTL); | |
9492 | val |= LCPLL_CD_SOURCE_FCLK; | |
9493 | I915_WRITE(LCPLL_CTL, val); | |
9494 | ||
5ba00178 TU |
9495 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
9496 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
b432e5cf VS |
9497 | DRM_ERROR("Switching to FCLK failed\n"); |
9498 | ||
9499 | val = I915_READ(LCPLL_CTL); | |
9500 | val &= ~LCPLL_CLK_FREQ_MASK; | |
9501 | ||
9502 | switch (cdclk) { | |
9503 | case 450000: | |
9504 | val |= LCPLL_CLK_FREQ_450; | |
9505 | data = 0; | |
9506 | break; | |
9507 | case 540000: | |
9508 | val |= LCPLL_CLK_FREQ_54O_BDW; | |
9509 | data = 1; | |
9510 | break; | |
9511 | case 337500: | |
9512 | val |= LCPLL_CLK_FREQ_337_5_BDW; | |
9513 | data = 2; | |
9514 | break; | |
9515 | case 675000: | |
9516 | val |= LCPLL_CLK_FREQ_675_BDW; | |
9517 | data = 3; | |
9518 | break; | |
9519 | default: | |
9520 | WARN(1, "invalid cdclk frequency\n"); | |
9521 | return; | |
9522 | } | |
9523 | ||
9524 | I915_WRITE(LCPLL_CTL, val); | |
9525 | ||
9526 | val = I915_READ(LCPLL_CTL); | |
9527 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9528 | I915_WRITE(LCPLL_CTL, val); | |
9529 | ||
5ba00178 TU |
9530 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
9531 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
b432e5cf VS |
9532 | DRM_ERROR("Switching back to LCPLL failed\n"); |
9533 | ||
9534 | mutex_lock(&dev_priv->rps.hw_lock); | |
9535 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); | |
9536 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9537 | ||
9538 | intel_update_cdclk(dev); | |
9539 | ||
9540 | WARN(cdclk != dev_priv->cdclk_freq, | |
9541 | "cdclk requested %d kHz but got %d kHz\n", | |
9542 | cdclk, dev_priv->cdclk_freq); | |
9543 | } | |
9544 | ||
27c329ed | 9545 | static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state) |
b432e5cf | 9546 | { |
27c329ed | 9547 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
1a617b77 | 9548 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
27c329ed | 9549 | int max_pixclk = ilk_max_pixel_rate(state); |
b432e5cf VS |
9550 | int cdclk; |
9551 | ||
9552 | /* | |
9553 | * FIXME should also account for plane ratio | |
9554 | * once 64bpp pixel formats are supported. | |
9555 | */ | |
27c329ed | 9556 | if (max_pixclk > 540000) |
b432e5cf | 9557 | cdclk = 675000; |
27c329ed | 9558 | else if (max_pixclk > 450000) |
b432e5cf | 9559 | cdclk = 540000; |
27c329ed | 9560 | else if (max_pixclk > 337500) |
b432e5cf VS |
9561 | cdclk = 450000; |
9562 | else | |
9563 | cdclk = 337500; | |
9564 | ||
b432e5cf | 9565 | if (cdclk > dev_priv->max_cdclk_freq) { |
63ba534e ML |
9566 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", |
9567 | cdclk, dev_priv->max_cdclk_freq); | |
9568 | return -EINVAL; | |
b432e5cf VS |
9569 | } |
9570 | ||
1a617b77 ML |
9571 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; |
9572 | if (!intel_state->active_crtcs) | |
9573 | intel_state->dev_cdclk = 337500; | |
b432e5cf VS |
9574 | |
9575 | return 0; | |
9576 | } | |
9577 | ||
27c329ed | 9578 | static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
b432e5cf | 9579 | { |
27c329ed | 9580 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
9581 | struct intel_atomic_state *old_intel_state = |
9582 | to_intel_atomic_state(old_state); | |
9583 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
b432e5cf | 9584 | |
27c329ed | 9585 | broadwell_set_cdclk(dev, req_cdclk); |
b432e5cf VS |
9586 | } |
9587 | ||
190f68c5 ACO |
9588 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
9589 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 9590 | { |
af3997b5 MK |
9591 | struct intel_encoder *intel_encoder = |
9592 | intel_ddi_get_crtc_new_encoder(crtc_state); | |
9593 | ||
9594 | if (intel_encoder->type != INTEL_OUTPUT_DSI) { | |
9595 | if (!intel_ddi_pll_select(crtc, crtc_state)) | |
9596 | return -EINVAL; | |
9597 | } | |
716c2e55 | 9598 | |
c7653199 | 9599 | crtc->lowfreq_avail = false; |
644cef34 | 9600 | |
c8f7a0db | 9601 | return 0; |
79e53945 JB |
9602 | } |
9603 | ||
3760b59c S |
9604 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
9605 | enum port port, | |
9606 | struct intel_crtc_state *pipe_config) | |
9607 | { | |
8106ddbd ACO |
9608 | enum intel_dpll_id id; |
9609 | ||
3760b59c S |
9610 | switch (port) { |
9611 | case PORT_A: | |
9612 | pipe_config->ddi_pll_sel = SKL_DPLL0; | |
08250c4b | 9613 | id = DPLL_ID_SKL_DPLL0; |
3760b59c S |
9614 | break; |
9615 | case PORT_B: | |
9616 | pipe_config->ddi_pll_sel = SKL_DPLL1; | |
08250c4b | 9617 | id = DPLL_ID_SKL_DPLL1; |
3760b59c S |
9618 | break; |
9619 | case PORT_C: | |
9620 | pipe_config->ddi_pll_sel = SKL_DPLL2; | |
08250c4b | 9621 | id = DPLL_ID_SKL_DPLL2; |
3760b59c S |
9622 | break; |
9623 | default: | |
9624 | DRM_ERROR("Incorrect port type\n"); | |
8106ddbd | 9625 | return; |
3760b59c | 9626 | } |
8106ddbd ACO |
9627 | |
9628 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
3760b59c S |
9629 | } |
9630 | ||
96b7dfb7 S |
9631 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
9632 | enum port port, | |
5cec258b | 9633 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 9634 | { |
8106ddbd | 9635 | enum intel_dpll_id id; |
a3c988ea | 9636 | u32 temp; |
96b7dfb7 S |
9637 | |
9638 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
9639 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
9640 | ||
9641 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 | 9642 | case SKL_DPLL0: |
a3c988ea ACO |
9643 | id = DPLL_ID_SKL_DPLL0; |
9644 | break; | |
96b7dfb7 | 9645 | case SKL_DPLL1: |
8106ddbd | 9646 | id = DPLL_ID_SKL_DPLL1; |
96b7dfb7 S |
9647 | break; |
9648 | case SKL_DPLL2: | |
8106ddbd | 9649 | id = DPLL_ID_SKL_DPLL2; |
96b7dfb7 S |
9650 | break; |
9651 | case SKL_DPLL3: | |
8106ddbd | 9652 | id = DPLL_ID_SKL_DPLL3; |
96b7dfb7 | 9653 | break; |
8106ddbd ACO |
9654 | default: |
9655 | MISSING_CASE(pipe_config->ddi_pll_sel); | |
9656 | return; | |
96b7dfb7 | 9657 | } |
8106ddbd ACO |
9658 | |
9659 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
96b7dfb7 S |
9660 | } |
9661 | ||
7d2c8175 DL |
9662 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
9663 | enum port port, | |
5cec258b | 9664 | struct intel_crtc_state *pipe_config) |
7d2c8175 | 9665 | { |
8106ddbd ACO |
9666 | enum intel_dpll_id id; |
9667 | ||
7d2c8175 DL |
9668 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); |
9669 | ||
9670 | switch (pipe_config->ddi_pll_sel) { | |
9671 | case PORT_CLK_SEL_WRPLL1: | |
8106ddbd | 9672 | id = DPLL_ID_WRPLL1; |
7d2c8175 DL |
9673 | break; |
9674 | case PORT_CLK_SEL_WRPLL2: | |
8106ddbd | 9675 | id = DPLL_ID_WRPLL2; |
7d2c8175 | 9676 | break; |
00490c22 | 9677 | case PORT_CLK_SEL_SPLL: |
8106ddbd | 9678 | id = DPLL_ID_SPLL; |
79bd23da | 9679 | break; |
9d16da65 ACO |
9680 | case PORT_CLK_SEL_LCPLL_810: |
9681 | id = DPLL_ID_LCPLL_810; | |
9682 | break; | |
9683 | case PORT_CLK_SEL_LCPLL_1350: | |
9684 | id = DPLL_ID_LCPLL_1350; | |
9685 | break; | |
9686 | case PORT_CLK_SEL_LCPLL_2700: | |
9687 | id = DPLL_ID_LCPLL_2700; | |
9688 | break; | |
8106ddbd ACO |
9689 | default: |
9690 | MISSING_CASE(pipe_config->ddi_pll_sel); | |
9691 | /* fall through */ | |
9692 | case PORT_CLK_SEL_NONE: | |
8106ddbd | 9693 | return; |
7d2c8175 | 9694 | } |
8106ddbd ACO |
9695 | |
9696 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
7d2c8175 DL |
9697 | } |
9698 | ||
cf30429e JN |
9699 | static bool hsw_get_transcoder_state(struct intel_crtc *crtc, |
9700 | struct intel_crtc_state *pipe_config, | |
9701 | unsigned long *power_domain_mask) | |
9702 | { | |
9703 | struct drm_device *dev = crtc->base.dev; | |
9704 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9705 | enum intel_display_power_domain power_domain; | |
9706 | u32 tmp; | |
9707 | ||
9708 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; | |
9709 | ||
9710 | /* | |
9711 | * XXX: Do intel_display_power_get_if_enabled before reading this (for | |
9712 | * consistency and less surprising code; it's in always on power). | |
9713 | */ | |
9714 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
9715 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
9716 | enum pipe trans_edp_pipe; | |
9717 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
9718 | default: | |
9719 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
9720 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
9721 | case TRANS_DDI_EDP_INPUT_A_ON: | |
9722 | trans_edp_pipe = PIPE_A; | |
9723 | break; | |
9724 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
9725 | trans_edp_pipe = PIPE_B; | |
9726 | break; | |
9727 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
9728 | trans_edp_pipe = PIPE_C; | |
9729 | break; | |
9730 | } | |
9731 | ||
9732 | if (trans_edp_pipe == crtc->pipe) | |
9733 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
9734 | } | |
9735 | ||
9736 | power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); | |
9737 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
9738 | return false; | |
9739 | *power_domain_mask |= BIT(power_domain); | |
9740 | ||
9741 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); | |
9742 | ||
9743 | return tmp & PIPECONF_ENABLE; | |
9744 | } | |
9745 | ||
4d1de975 JN |
9746 | static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, |
9747 | struct intel_crtc_state *pipe_config, | |
9748 | unsigned long *power_domain_mask) | |
9749 | { | |
9750 | struct drm_device *dev = crtc->base.dev; | |
9751 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9752 | enum intel_display_power_domain power_domain; | |
9753 | enum port port; | |
9754 | enum transcoder cpu_transcoder; | |
9755 | u32 tmp; | |
9756 | ||
9757 | pipe_config->has_dsi_encoder = false; | |
9758 | ||
9759 | for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { | |
9760 | if (port == PORT_A) | |
9761 | cpu_transcoder = TRANSCODER_DSI_A; | |
9762 | else | |
9763 | cpu_transcoder = TRANSCODER_DSI_C; | |
9764 | ||
9765 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
9766 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
9767 | continue; | |
9768 | *power_domain_mask |= BIT(power_domain); | |
9769 | ||
9770 | /* XXX: this works for video mode only */ | |
9771 | tmp = I915_READ(BXT_MIPI_PORT_CTRL(port)); | |
9772 | if (!(tmp & DPI_ENABLE)) | |
9773 | continue; | |
9774 | ||
9775 | tmp = I915_READ(MIPI_CTRL(port)); | |
9776 | if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) | |
9777 | continue; | |
9778 | ||
9779 | pipe_config->cpu_transcoder = cpu_transcoder; | |
9780 | pipe_config->has_dsi_encoder = true; | |
9781 | break; | |
9782 | } | |
9783 | ||
9784 | return pipe_config->has_dsi_encoder; | |
9785 | } | |
9786 | ||
26804afd | 9787 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 9788 | struct intel_crtc_state *pipe_config) |
26804afd DV |
9789 | { |
9790 | struct drm_device *dev = crtc->base.dev; | |
9791 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 9792 | struct intel_shared_dpll *pll; |
26804afd DV |
9793 | enum port port; |
9794 | uint32_t tmp; | |
9795 | ||
9796 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
9797 | ||
9798 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
9799 | ||
ef11bdb3 | 9800 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
96b7dfb7 | 9801 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
3760b59c S |
9802 | else if (IS_BROXTON(dev)) |
9803 | bxt_get_ddi_pll(dev_priv, port, pipe_config); | |
96b7dfb7 S |
9804 | else |
9805 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 9806 | |
8106ddbd ACO |
9807 | pll = pipe_config->shared_dpll; |
9808 | if (pll) { | |
2edd6443 ACO |
9809 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
9810 | &pipe_config->dpll_hw_state)); | |
d452c5b6 DV |
9811 | } |
9812 | ||
26804afd DV |
9813 | /* |
9814 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
9815 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
9816 | * the PCH transcoder is on. | |
9817 | */ | |
ca370455 DL |
9818 | if (INTEL_INFO(dev)->gen < 9 && |
9819 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
9820 | pipe_config->has_pch_encoder = true; |
9821 | ||
9822 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
9823 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9824 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
9825 | ||
9826 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
9827 | } | |
9828 | } | |
9829 | ||
0e8ffe1b | 9830 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9831 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9832 | { |
9833 | struct drm_device *dev = crtc->base.dev; | |
9834 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1729050e ID |
9835 | enum intel_display_power_domain power_domain; |
9836 | unsigned long power_domain_mask; | |
cf30429e | 9837 | bool active; |
0e8ffe1b | 9838 | |
1729050e ID |
9839 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
9840 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 | 9841 | return false; |
1729050e ID |
9842 | power_domain_mask = BIT(power_domain); |
9843 | ||
8106ddbd | 9844 | pipe_config->shared_dpll = NULL; |
c0d43d62 | 9845 | |
cf30429e | 9846 | active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask); |
eccb140b | 9847 | |
4d1de975 JN |
9848 | if (IS_BROXTON(dev_priv)) { |
9849 | bxt_get_dsi_transcoder_state(crtc, pipe_config, | |
9850 | &power_domain_mask); | |
9851 | WARN_ON(active && pipe_config->has_dsi_encoder); | |
9852 | if (pipe_config->has_dsi_encoder) | |
9853 | active = true; | |
9854 | } | |
9855 | ||
cf30429e | 9856 | if (!active) |
1729050e | 9857 | goto out; |
0e8ffe1b | 9858 | |
4d1de975 JN |
9859 | if (!pipe_config->has_dsi_encoder) { |
9860 | haswell_get_ddi_port_state(crtc, pipe_config); | |
9861 | intel_get_pipe_timings(crtc, pipe_config); | |
9862 | } | |
627eb5a3 | 9863 | |
bc58be60 | 9864 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 9865 | |
05dc698c LL |
9866 | pipe_config->gamma_mode = |
9867 | I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; | |
9868 | ||
a1b2278e CK |
9869 | if (INTEL_INFO(dev)->gen >= 9) { |
9870 | skl_init_scalers(dev, crtc, pipe_config); | |
9871 | } | |
9872 | ||
af99ceda CK |
9873 | if (INTEL_INFO(dev)->gen >= 9) { |
9874 | pipe_config->scaler_state.scaler_id = -1; | |
9875 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
9876 | } | |
9877 | ||
1729050e ID |
9878 | power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
9879 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
9880 | power_domain_mask |= BIT(power_domain); | |
1c132b44 | 9881 | if (INTEL_INFO(dev)->gen >= 9) |
bd2e244f | 9882 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 9883 | else |
1c132b44 | 9884 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 9885 | } |
88adfff1 | 9886 | |
e59150dc JB |
9887 | if (IS_HASWELL(dev)) |
9888 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
9889 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 9890 | |
4d1de975 JN |
9891 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP && |
9892 | !transcoder_is_dsi(pipe_config->cpu_transcoder)) { | |
ebb69c95 CT |
9893 | pipe_config->pixel_multiplier = |
9894 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
9895 | } else { | |
9896 | pipe_config->pixel_multiplier = 1; | |
9897 | } | |
6c49f241 | 9898 | |
1729050e ID |
9899 | out: |
9900 | for_each_power_domain(power_domain, power_domain_mask) | |
9901 | intel_display_power_put(dev_priv, power_domain); | |
9902 | ||
cf30429e | 9903 | return active; |
0e8ffe1b DV |
9904 | } |
9905 | ||
55a08b3f ML |
9906 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base, |
9907 | const struct intel_plane_state *plane_state) | |
560b85bb CW |
9908 | { |
9909 | struct drm_device *dev = crtc->dev; | |
9910 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9911 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 9912 | uint32_t cntl = 0, size = 0; |
560b85bb | 9913 | |
55a08b3f ML |
9914 | if (plane_state && plane_state->visible) { |
9915 | unsigned int width = plane_state->base.crtc_w; | |
9916 | unsigned int height = plane_state->base.crtc_h; | |
dc41c154 VS |
9917 | unsigned int stride = roundup_pow_of_two(width) * 4; |
9918 | ||
9919 | switch (stride) { | |
9920 | default: | |
9921 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
9922 | width, stride); | |
9923 | stride = 256; | |
9924 | /* fallthrough */ | |
9925 | case 256: | |
9926 | case 512: | |
9927 | case 1024: | |
9928 | case 2048: | |
9929 | break; | |
4b0e333e CW |
9930 | } |
9931 | ||
dc41c154 VS |
9932 | cntl |= CURSOR_ENABLE | |
9933 | CURSOR_GAMMA_ENABLE | | |
9934 | CURSOR_FORMAT_ARGB | | |
9935 | CURSOR_STRIDE(stride); | |
9936 | ||
9937 | size = (height << 12) | width; | |
4b0e333e | 9938 | } |
560b85bb | 9939 | |
dc41c154 VS |
9940 | if (intel_crtc->cursor_cntl != 0 && |
9941 | (intel_crtc->cursor_base != base || | |
9942 | intel_crtc->cursor_size != size || | |
9943 | intel_crtc->cursor_cntl != cntl)) { | |
9944 | /* On these chipsets we can only modify the base/size/stride | |
9945 | * whilst the cursor is disabled. | |
9946 | */ | |
0b87c24e VS |
9947 | I915_WRITE(CURCNTR(PIPE_A), 0); |
9948 | POSTING_READ(CURCNTR(PIPE_A)); | |
dc41c154 | 9949 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 9950 | } |
560b85bb | 9951 | |
99d1f387 | 9952 | if (intel_crtc->cursor_base != base) { |
0b87c24e | 9953 | I915_WRITE(CURBASE(PIPE_A), base); |
99d1f387 VS |
9954 | intel_crtc->cursor_base = base; |
9955 | } | |
4726e0b0 | 9956 | |
dc41c154 VS |
9957 | if (intel_crtc->cursor_size != size) { |
9958 | I915_WRITE(CURSIZE, size); | |
9959 | intel_crtc->cursor_size = size; | |
4b0e333e | 9960 | } |
560b85bb | 9961 | |
4b0e333e | 9962 | if (intel_crtc->cursor_cntl != cntl) { |
0b87c24e VS |
9963 | I915_WRITE(CURCNTR(PIPE_A), cntl); |
9964 | POSTING_READ(CURCNTR(PIPE_A)); | |
4b0e333e | 9965 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 9966 | } |
560b85bb CW |
9967 | } |
9968 | ||
55a08b3f ML |
9969 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, |
9970 | const struct intel_plane_state *plane_state) | |
65a21cd6 JB |
9971 | { |
9972 | struct drm_device *dev = crtc->dev; | |
9973 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9974 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9975 | int pipe = intel_crtc->pipe; | |
663f3122 | 9976 | uint32_t cntl = 0; |
4b0e333e | 9977 | |
55a08b3f | 9978 | if (plane_state && plane_state->visible) { |
4b0e333e | 9979 | cntl = MCURSOR_GAMMA_ENABLE; |
55a08b3f | 9980 | switch (plane_state->base.crtc_w) { |
4726e0b0 SK |
9981 | case 64: |
9982 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
9983 | break; | |
9984 | case 128: | |
9985 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
9986 | break; | |
9987 | case 256: | |
9988 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
9989 | break; | |
9990 | default: | |
55a08b3f | 9991 | MISSING_CASE(plane_state->base.crtc_w); |
4726e0b0 | 9992 | return; |
65a21cd6 | 9993 | } |
4b0e333e | 9994 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 | 9995 | |
fc6f93bc | 9996 | if (HAS_DDI(dev)) |
47bf17a7 | 9997 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
65a21cd6 | 9998 | |
55a08b3f ML |
9999 | if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) |
10000 | cntl |= CURSOR_ROTATE_180; | |
10001 | } | |
4398ad45 | 10002 | |
4b0e333e CW |
10003 | if (intel_crtc->cursor_cntl != cntl) { |
10004 | I915_WRITE(CURCNTR(pipe), cntl); | |
10005 | POSTING_READ(CURCNTR(pipe)); | |
10006 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 10007 | } |
4b0e333e | 10008 | |
65a21cd6 | 10009 | /* and commit changes on next vblank */ |
5efb3e28 VS |
10010 | I915_WRITE(CURBASE(pipe), base); |
10011 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
10012 | |
10013 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
10014 | } |
10015 | ||
cda4b7d3 | 10016 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f | 10017 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
55a08b3f | 10018 | const struct intel_plane_state *plane_state) |
cda4b7d3 CW |
10019 | { |
10020 | struct drm_device *dev = crtc->dev; | |
10021 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10022 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10023 | int pipe = intel_crtc->pipe; | |
55a08b3f ML |
10024 | u32 base = intel_crtc->cursor_addr; |
10025 | u32 pos = 0; | |
cda4b7d3 | 10026 | |
55a08b3f ML |
10027 | if (plane_state) { |
10028 | int x = plane_state->base.crtc_x; | |
10029 | int y = plane_state->base.crtc_y; | |
cda4b7d3 | 10030 | |
55a08b3f ML |
10031 | if (x < 0) { |
10032 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
10033 | x = -x; | |
10034 | } | |
10035 | pos |= x << CURSOR_X_SHIFT; | |
cda4b7d3 | 10036 | |
55a08b3f ML |
10037 | if (y < 0) { |
10038 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
10039 | y = -y; | |
10040 | } | |
10041 | pos |= y << CURSOR_Y_SHIFT; | |
10042 | ||
10043 | /* ILK+ do this automagically */ | |
10044 | if (HAS_GMCH_DISPLAY(dev) && | |
10045 | plane_state->base.rotation == BIT(DRM_ROTATE_180)) { | |
10046 | base += (plane_state->base.crtc_h * | |
10047 | plane_state->base.crtc_w - 1) * 4; | |
10048 | } | |
cda4b7d3 | 10049 | } |
cda4b7d3 | 10050 | |
5efb3e28 VS |
10051 | I915_WRITE(CURPOS(pipe), pos); |
10052 | ||
8ac54669 | 10053 | if (IS_845G(dev) || IS_I865G(dev)) |
55a08b3f | 10054 | i845_update_cursor(crtc, base, plane_state); |
5efb3e28 | 10055 | else |
55a08b3f | 10056 | i9xx_update_cursor(crtc, base, plane_state); |
cda4b7d3 CW |
10057 | } |
10058 | ||
dc41c154 VS |
10059 | static bool cursor_size_ok(struct drm_device *dev, |
10060 | uint32_t width, uint32_t height) | |
10061 | { | |
10062 | if (width == 0 || height == 0) | |
10063 | return false; | |
10064 | ||
10065 | /* | |
10066 | * 845g/865g are special in that they are only limited by | |
10067 | * the width of their cursors, the height is arbitrary up to | |
10068 | * the precision of the register. Everything else requires | |
10069 | * square cursors, limited to a few power-of-two sizes. | |
10070 | */ | |
10071 | if (IS_845G(dev) || IS_I865G(dev)) { | |
10072 | if ((width & 63) != 0) | |
10073 | return false; | |
10074 | ||
10075 | if (width > (IS_845G(dev) ? 64 : 512)) | |
10076 | return false; | |
10077 | ||
10078 | if (height > 1023) | |
10079 | return false; | |
10080 | } else { | |
10081 | switch (width | height) { | |
10082 | case 256: | |
10083 | case 128: | |
10084 | if (IS_GEN2(dev)) | |
10085 | return false; | |
10086 | case 64: | |
10087 | break; | |
10088 | default: | |
10089 | return false; | |
10090 | } | |
10091 | } | |
10092 | ||
10093 | return true; | |
10094 | } | |
10095 | ||
79e53945 JB |
10096 | /* VESA 640x480x72Hz mode to set on the pipe */ |
10097 | static struct drm_display_mode load_detect_mode = { | |
10098 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
10099 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
10100 | }; | |
10101 | ||
a8bb6818 DV |
10102 | struct drm_framebuffer * |
10103 | __intel_framebuffer_create(struct drm_device *dev, | |
10104 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10105 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
10106 | { |
10107 | struct intel_framebuffer *intel_fb; | |
10108 | int ret; | |
10109 | ||
10110 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
dcb1394e | 10111 | if (!intel_fb) |
d2dff872 | 10112 | return ERR_PTR(-ENOMEM); |
d2dff872 CW |
10113 | |
10114 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
10115 | if (ret) |
10116 | goto err; | |
d2dff872 CW |
10117 | |
10118 | return &intel_fb->base; | |
dcb1394e | 10119 | |
dd4916c5 | 10120 | err: |
dd4916c5 | 10121 | kfree(intel_fb); |
dd4916c5 | 10122 | return ERR_PTR(ret); |
d2dff872 CW |
10123 | } |
10124 | ||
b5ea642a | 10125 | static struct drm_framebuffer * |
a8bb6818 DV |
10126 | intel_framebuffer_create(struct drm_device *dev, |
10127 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10128 | struct drm_i915_gem_object *obj) | |
10129 | { | |
10130 | struct drm_framebuffer *fb; | |
10131 | int ret; | |
10132 | ||
10133 | ret = i915_mutex_lock_interruptible(dev); | |
10134 | if (ret) | |
10135 | return ERR_PTR(ret); | |
10136 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
10137 | mutex_unlock(&dev->struct_mutex); | |
10138 | ||
10139 | return fb; | |
10140 | } | |
10141 | ||
d2dff872 CW |
10142 | static u32 |
10143 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
10144 | { | |
10145 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
10146 | return ALIGN(pitch, 64); | |
10147 | } | |
10148 | ||
10149 | static u32 | |
10150 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
10151 | { | |
10152 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 10153 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
10154 | } |
10155 | ||
10156 | static struct drm_framebuffer * | |
10157 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
10158 | struct drm_display_mode *mode, | |
10159 | int depth, int bpp) | |
10160 | { | |
dcb1394e | 10161 | struct drm_framebuffer *fb; |
d2dff872 | 10162 | struct drm_i915_gem_object *obj; |
0fed39bd | 10163 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
10164 | |
10165 | obj = i915_gem_alloc_object(dev, | |
10166 | intel_framebuffer_size_for_mode(mode, bpp)); | |
10167 | if (obj == NULL) | |
10168 | return ERR_PTR(-ENOMEM); | |
10169 | ||
10170 | mode_cmd.width = mode->hdisplay; | |
10171 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
10172 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
10173 | bpp); | |
5ca0c34a | 10174 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 | 10175 | |
dcb1394e LW |
10176 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
10177 | if (IS_ERR(fb)) | |
10178 | drm_gem_object_unreference_unlocked(&obj->base); | |
10179 | ||
10180 | return fb; | |
d2dff872 CW |
10181 | } |
10182 | ||
10183 | static struct drm_framebuffer * | |
10184 | mode_fits_in_fbdev(struct drm_device *dev, | |
10185 | struct drm_display_mode *mode) | |
10186 | { | |
0695726e | 10187 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
d2dff872 CW |
10188 | struct drm_i915_private *dev_priv = dev->dev_private; |
10189 | struct drm_i915_gem_object *obj; | |
10190 | struct drm_framebuffer *fb; | |
10191 | ||
4c0e5528 | 10192 | if (!dev_priv->fbdev) |
d2dff872 CW |
10193 | return NULL; |
10194 | ||
4c0e5528 | 10195 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
10196 | return NULL; |
10197 | ||
4c0e5528 DV |
10198 | obj = dev_priv->fbdev->fb->obj; |
10199 | BUG_ON(!obj); | |
10200 | ||
8bcd4553 | 10201 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
10202 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
10203 | fb->bits_per_pixel)) | |
d2dff872 CW |
10204 | return NULL; |
10205 | ||
01f2c773 | 10206 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
10207 | return NULL; |
10208 | ||
edde3617 | 10209 | drm_framebuffer_reference(fb); |
d2dff872 | 10210 | return fb; |
4520f53a DV |
10211 | #else |
10212 | return NULL; | |
10213 | #endif | |
d2dff872 CW |
10214 | } |
10215 | ||
d3a40d1b ACO |
10216 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
10217 | struct drm_crtc *crtc, | |
10218 | struct drm_display_mode *mode, | |
10219 | struct drm_framebuffer *fb, | |
10220 | int x, int y) | |
10221 | { | |
10222 | struct drm_plane_state *plane_state; | |
10223 | int hdisplay, vdisplay; | |
10224 | int ret; | |
10225 | ||
10226 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
10227 | if (IS_ERR(plane_state)) | |
10228 | return PTR_ERR(plane_state); | |
10229 | ||
10230 | if (mode) | |
10231 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); | |
10232 | else | |
10233 | hdisplay = vdisplay = 0; | |
10234 | ||
10235 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
10236 | if (ret) | |
10237 | return ret; | |
10238 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
10239 | plane_state->crtc_x = 0; | |
10240 | plane_state->crtc_y = 0; | |
10241 | plane_state->crtc_w = hdisplay; | |
10242 | plane_state->crtc_h = vdisplay; | |
10243 | plane_state->src_x = x << 16; | |
10244 | plane_state->src_y = y << 16; | |
10245 | plane_state->src_w = hdisplay << 16; | |
10246 | plane_state->src_h = vdisplay << 16; | |
10247 | ||
10248 | return 0; | |
10249 | } | |
10250 | ||
d2434ab7 | 10251 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 10252 | struct drm_display_mode *mode, |
51fd371b RC |
10253 | struct intel_load_detect_pipe *old, |
10254 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
10255 | { |
10256 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
10257 | struct intel_encoder *intel_encoder = |
10258 | intel_attached_encoder(connector); | |
79e53945 | 10259 | struct drm_crtc *possible_crtc; |
4ef69c7a | 10260 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
10261 | struct drm_crtc *crtc = NULL; |
10262 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 10263 | struct drm_framebuffer *fb; |
51fd371b | 10264 | struct drm_mode_config *config = &dev->mode_config; |
edde3617 | 10265 | struct drm_atomic_state *state = NULL, *restore_state = NULL; |
944b0c76 | 10266 | struct drm_connector_state *connector_state; |
4be07317 | 10267 | struct intel_crtc_state *crtc_state; |
51fd371b | 10268 | int ret, i = -1; |
79e53945 | 10269 | |
d2dff872 | 10270 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10271 | connector->base.id, connector->name, |
8e329a03 | 10272 | encoder->base.id, encoder->name); |
d2dff872 | 10273 | |
edde3617 ML |
10274 | old->restore_state = NULL; |
10275 | ||
51fd371b RC |
10276 | retry: |
10277 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
10278 | if (ret) | |
ad3c558f | 10279 | goto fail; |
6e9f798d | 10280 | |
79e53945 JB |
10281 | /* |
10282 | * Algorithm gets a little messy: | |
7a5e4805 | 10283 | * |
79e53945 JB |
10284 | * - if the connector already has an assigned crtc, use it (but make |
10285 | * sure it's on first) | |
7a5e4805 | 10286 | * |
79e53945 JB |
10287 | * - try to find the first unused crtc that can drive this connector, |
10288 | * and use that if we find one | |
79e53945 JB |
10289 | */ |
10290 | ||
10291 | /* See if we already have a CRTC for this connector */ | |
edde3617 ML |
10292 | if (connector->state->crtc) { |
10293 | crtc = connector->state->crtc; | |
8261b191 | 10294 | |
51fd371b | 10295 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 10296 | if (ret) |
ad3c558f | 10297 | goto fail; |
8261b191 CW |
10298 | |
10299 | /* Make sure the crtc and connector are running */ | |
edde3617 | 10300 | goto found; |
79e53945 JB |
10301 | } |
10302 | ||
10303 | /* Find an unused one (if possible) */ | |
70e1e0ec | 10304 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
10305 | i++; |
10306 | if (!(encoder->possible_crtcs & (1 << i))) | |
10307 | continue; | |
edde3617 ML |
10308 | |
10309 | ret = drm_modeset_lock(&possible_crtc->mutex, ctx); | |
10310 | if (ret) | |
10311 | goto fail; | |
10312 | ||
10313 | if (possible_crtc->state->enable) { | |
10314 | drm_modeset_unlock(&possible_crtc->mutex); | |
a459249c | 10315 | continue; |
edde3617 | 10316 | } |
a459249c VS |
10317 | |
10318 | crtc = possible_crtc; | |
10319 | break; | |
79e53945 JB |
10320 | } |
10321 | ||
10322 | /* | |
10323 | * If we didn't find an unused CRTC, don't use any. | |
10324 | */ | |
10325 | if (!crtc) { | |
7173188d | 10326 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
ad3c558f | 10327 | goto fail; |
79e53945 JB |
10328 | } |
10329 | ||
edde3617 ML |
10330 | found: |
10331 | intel_crtc = to_intel_crtc(crtc); | |
10332 | ||
4d02e2de DV |
10333 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
10334 | if (ret) | |
ad3c558f | 10335 | goto fail; |
79e53945 | 10336 | |
83a57153 | 10337 | state = drm_atomic_state_alloc(dev); |
edde3617 ML |
10338 | restore_state = drm_atomic_state_alloc(dev); |
10339 | if (!state || !restore_state) { | |
10340 | ret = -ENOMEM; | |
10341 | goto fail; | |
10342 | } | |
83a57153 ACO |
10343 | |
10344 | state->acquire_ctx = ctx; | |
edde3617 | 10345 | restore_state->acquire_ctx = ctx; |
83a57153 | 10346 | |
944b0c76 ACO |
10347 | connector_state = drm_atomic_get_connector_state(state, connector); |
10348 | if (IS_ERR(connector_state)) { | |
10349 | ret = PTR_ERR(connector_state); | |
10350 | goto fail; | |
10351 | } | |
10352 | ||
edde3617 ML |
10353 | ret = drm_atomic_set_crtc_for_connector(connector_state, crtc); |
10354 | if (ret) | |
10355 | goto fail; | |
944b0c76 | 10356 | |
4be07317 ACO |
10357 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10358 | if (IS_ERR(crtc_state)) { | |
10359 | ret = PTR_ERR(crtc_state); | |
10360 | goto fail; | |
10361 | } | |
10362 | ||
49d6fa21 | 10363 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 10364 | |
6492711d CW |
10365 | if (!mode) |
10366 | mode = &load_detect_mode; | |
79e53945 | 10367 | |
d2dff872 CW |
10368 | /* We need a framebuffer large enough to accommodate all accesses |
10369 | * that the plane may generate whilst we perform load detection. | |
10370 | * We can not rely on the fbcon either being present (we get called | |
10371 | * during its initialisation to detect all boot displays, or it may | |
10372 | * not even exist) or that it is large enough to satisfy the | |
10373 | * requested mode. | |
10374 | */ | |
94352cf9 DV |
10375 | fb = mode_fits_in_fbdev(dev, mode); |
10376 | if (fb == NULL) { | |
d2dff872 | 10377 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 | 10378 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
d2dff872 CW |
10379 | } else |
10380 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 10381 | if (IS_ERR(fb)) { |
d2dff872 | 10382 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 10383 | goto fail; |
79e53945 | 10384 | } |
79e53945 | 10385 | |
d3a40d1b ACO |
10386 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
10387 | if (ret) | |
10388 | goto fail; | |
10389 | ||
edde3617 ML |
10390 | drm_framebuffer_unreference(fb); |
10391 | ||
10392 | ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode); | |
10393 | if (ret) | |
10394 | goto fail; | |
10395 | ||
10396 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); | |
10397 | if (!ret) | |
10398 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc)); | |
10399 | if (!ret) | |
10400 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary)); | |
10401 | if (ret) { | |
10402 | DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret); | |
10403 | goto fail; | |
10404 | } | |
8c7b5ccb | 10405 | |
3ba86073 ML |
10406 | ret = drm_atomic_commit(state); |
10407 | if (ret) { | |
6492711d | 10408 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
412b61d8 | 10409 | goto fail; |
79e53945 | 10410 | } |
edde3617 ML |
10411 | |
10412 | old->restore_state = restore_state; | |
7173188d | 10413 | |
79e53945 | 10414 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 10415 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 10416 | return true; |
412b61d8 | 10417 | |
ad3c558f | 10418 | fail: |
e5d958ef | 10419 | drm_atomic_state_free(state); |
edde3617 ML |
10420 | drm_atomic_state_free(restore_state); |
10421 | restore_state = state = NULL; | |
83a57153 | 10422 | |
51fd371b RC |
10423 | if (ret == -EDEADLK) { |
10424 | drm_modeset_backoff(ctx); | |
10425 | goto retry; | |
10426 | } | |
10427 | ||
412b61d8 | 10428 | return false; |
79e53945 JB |
10429 | } |
10430 | ||
d2434ab7 | 10431 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
10432 | struct intel_load_detect_pipe *old, |
10433 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 10434 | { |
d2434ab7 DV |
10435 | struct intel_encoder *intel_encoder = |
10436 | intel_attached_encoder(connector); | |
4ef69c7a | 10437 | struct drm_encoder *encoder = &intel_encoder->base; |
edde3617 | 10438 | struct drm_atomic_state *state = old->restore_state; |
d3a40d1b | 10439 | int ret; |
79e53945 | 10440 | |
d2dff872 | 10441 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10442 | connector->base.id, connector->name, |
8e329a03 | 10443 | encoder->base.id, encoder->name); |
d2dff872 | 10444 | |
edde3617 | 10445 | if (!state) |
0622a53c | 10446 | return; |
79e53945 | 10447 | |
edde3617 ML |
10448 | ret = drm_atomic_commit(state); |
10449 | if (ret) { | |
10450 | DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret); | |
10451 | drm_atomic_state_free(state); | |
10452 | } | |
79e53945 JB |
10453 | } |
10454 | ||
da4a1efa | 10455 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 10456 | const struct intel_crtc_state *pipe_config) |
da4a1efa VS |
10457 | { |
10458 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10459 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
10460 | ||
10461 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 10462 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
10463 | else if (HAS_PCH_SPLIT(dev)) |
10464 | return 120000; | |
10465 | else if (!IS_GEN2(dev)) | |
10466 | return 96000; | |
10467 | else | |
10468 | return 48000; | |
10469 | } | |
10470 | ||
79e53945 | 10471 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 10472 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 10473 | struct intel_crtc_state *pipe_config) |
79e53945 | 10474 | { |
f1f644dc | 10475 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 10476 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 10477 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 10478 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
10479 | u32 fp; |
10480 | intel_clock_t clock; | |
dccbea3b | 10481 | int port_clock; |
da4a1efa | 10482 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
10483 | |
10484 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 10485 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 10486 | else |
293623f7 | 10487 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
10488 | |
10489 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
10490 | if (IS_PINEVIEW(dev)) { |
10491 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
10492 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
10493 | } else { |
10494 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
10495 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
10496 | } | |
10497 | ||
a6c45cf0 | 10498 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
10499 | if (IS_PINEVIEW(dev)) |
10500 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
10501 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
10502 | else |
10503 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
10504 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
10505 | ||
10506 | switch (dpll & DPLL_MODE_MASK) { | |
10507 | case DPLLB_MODE_DAC_SERIAL: | |
10508 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
10509 | 5 : 10; | |
10510 | break; | |
10511 | case DPLLB_MODE_LVDS: | |
10512 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
10513 | 7 : 14; | |
10514 | break; | |
10515 | default: | |
28c97730 | 10516 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 10517 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 10518 | return; |
79e53945 JB |
10519 | } |
10520 | ||
ac58c3f0 | 10521 | if (IS_PINEVIEW(dev)) |
dccbea3b | 10522 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 10523 | else |
dccbea3b | 10524 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 10525 | } else { |
0fb58223 | 10526 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 10527 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
10528 | |
10529 | if (is_lvds) { | |
10530 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
10531 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
10532 | |
10533 | if (lvds & LVDS_CLKB_POWER_UP) | |
10534 | clock.p2 = 7; | |
10535 | else | |
10536 | clock.p2 = 14; | |
79e53945 JB |
10537 | } else { |
10538 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
10539 | clock.p1 = 2; | |
10540 | else { | |
10541 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
10542 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
10543 | } | |
10544 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
10545 | clock.p2 = 4; | |
10546 | else | |
10547 | clock.p2 = 2; | |
79e53945 | 10548 | } |
da4a1efa | 10549 | |
dccbea3b | 10550 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
10551 | } |
10552 | ||
18442d08 VS |
10553 | /* |
10554 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 10555 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
10556 | * encoder's get_config() function. |
10557 | */ | |
dccbea3b | 10558 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
10559 | } |
10560 | ||
6878da05 VS |
10561 | int intel_dotclock_calculate(int link_freq, |
10562 | const struct intel_link_m_n *m_n) | |
f1f644dc | 10563 | { |
f1f644dc JB |
10564 | /* |
10565 | * The calculation for the data clock is: | |
1041a02f | 10566 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 10567 | * But we want to avoid losing precison if possible, so: |
1041a02f | 10568 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
10569 | * |
10570 | * and the link clock is simpler: | |
1041a02f | 10571 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
10572 | */ |
10573 | ||
6878da05 VS |
10574 | if (!m_n->link_n) |
10575 | return 0; | |
f1f644dc | 10576 | |
6878da05 VS |
10577 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
10578 | } | |
f1f644dc | 10579 | |
18442d08 | 10580 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 10581 | struct intel_crtc_state *pipe_config) |
6878da05 | 10582 | { |
e3b247da | 10583 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
79e53945 | 10584 | |
18442d08 VS |
10585 | /* read out port_clock from the DPLL */ |
10586 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 10587 | |
f1f644dc | 10588 | /* |
e3b247da VS |
10589 | * In case there is an active pipe without active ports, |
10590 | * we may need some idea for the dotclock anyway. | |
10591 | * Calculate one based on the FDI configuration. | |
79e53945 | 10592 | */ |
2d112de7 | 10593 | pipe_config->base.adjusted_mode.crtc_clock = |
21a727b3 | 10594 | intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
18442d08 | 10595 | &pipe_config->fdi_m_n); |
79e53945 JB |
10596 | } |
10597 | ||
10598 | /** Returns the currently programmed mode of the given pipe. */ | |
10599 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
10600 | struct drm_crtc *crtc) | |
10601 | { | |
548f245b | 10602 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 10603 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 10604 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 10605 | struct drm_display_mode *mode; |
3f36b937 | 10606 | struct intel_crtc_state *pipe_config; |
fe2b8f9d PZ |
10607 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
10608 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
10609 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
10610 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 10611 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
10612 | |
10613 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
10614 | if (!mode) | |
10615 | return NULL; | |
10616 | ||
3f36b937 TU |
10617 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
10618 | if (!pipe_config) { | |
10619 | kfree(mode); | |
10620 | return NULL; | |
10621 | } | |
10622 | ||
f1f644dc JB |
10623 | /* |
10624 | * Construct a pipe_config sufficient for getting the clock info | |
10625 | * back out of crtc_clock_get. | |
10626 | * | |
10627 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
10628 | * to use a real value here instead. | |
10629 | */ | |
3f36b937 TU |
10630 | pipe_config->cpu_transcoder = (enum transcoder) pipe; |
10631 | pipe_config->pixel_multiplier = 1; | |
10632 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe)); | |
10633 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
10634 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
10635 | i9xx_crtc_clock_get(intel_crtc, pipe_config); | |
10636 | ||
10637 | mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier; | |
79e53945 JB |
10638 | mode->hdisplay = (htot & 0xffff) + 1; |
10639 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
10640 | mode->hsync_start = (hsync & 0xffff) + 1; | |
10641 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
10642 | mode->vdisplay = (vtot & 0xffff) + 1; | |
10643 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
10644 | mode->vsync_start = (vsync & 0xffff) + 1; | |
10645 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
10646 | ||
10647 | drm_mode_set_name(mode); | |
79e53945 | 10648 | |
3f36b937 TU |
10649 | kfree(pipe_config); |
10650 | ||
79e53945 JB |
10651 | return mode; |
10652 | } | |
10653 | ||
f047e395 CW |
10654 | void intel_mark_busy(struct drm_device *dev) |
10655 | { | |
c67a470b PZ |
10656 | struct drm_i915_private *dev_priv = dev->dev_private; |
10657 | ||
f62a0076 CW |
10658 | if (dev_priv->mm.busy) |
10659 | return; | |
10660 | ||
43694d69 | 10661 | intel_runtime_pm_get(dev_priv); |
c67a470b | 10662 | i915_update_gfx_val(dev_priv); |
43cf3bf0 CW |
10663 | if (INTEL_INFO(dev)->gen >= 6) |
10664 | gen6_rps_busy(dev_priv); | |
f62a0076 | 10665 | dev_priv->mm.busy = true; |
f047e395 CW |
10666 | } |
10667 | ||
10668 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 10669 | { |
c67a470b | 10670 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 10671 | |
f62a0076 CW |
10672 | if (!dev_priv->mm.busy) |
10673 | return; | |
10674 | ||
10675 | dev_priv->mm.busy = false; | |
10676 | ||
3d13ef2e | 10677 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 10678 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 | 10679 | |
43694d69 | 10680 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
10681 | } |
10682 | ||
79e53945 JB |
10683 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
10684 | { | |
10685 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
10686 | struct drm_device *dev = crtc->dev; |
10687 | struct intel_unpin_work *work; | |
67e77c5a | 10688 | |
5e2d7afc | 10689 | spin_lock_irq(&dev->event_lock); |
67e77c5a DV |
10690 | work = intel_crtc->unpin_work; |
10691 | intel_crtc->unpin_work = NULL; | |
5e2d7afc | 10692 | spin_unlock_irq(&dev->event_lock); |
67e77c5a DV |
10693 | |
10694 | if (work) { | |
10695 | cancel_work_sync(&work->work); | |
10696 | kfree(work); | |
10697 | } | |
79e53945 JB |
10698 | |
10699 | drm_crtc_cleanup(crtc); | |
67e77c5a | 10700 | |
79e53945 JB |
10701 | kfree(intel_crtc); |
10702 | } | |
10703 | ||
6b95a207 KH |
10704 | static void intel_unpin_work_fn(struct work_struct *__work) |
10705 | { | |
10706 | struct intel_unpin_work *work = | |
10707 | container_of(__work, struct intel_unpin_work, work); | |
a9ff8714 VS |
10708 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); |
10709 | struct drm_device *dev = crtc->base.dev; | |
10710 | struct drm_plane *primary = crtc->base.primary; | |
6b95a207 | 10711 | |
b4a98e57 | 10712 | mutex_lock(&dev->struct_mutex); |
3465c580 | 10713 | intel_unpin_fb_obj(work->old_fb, primary->state->rotation); |
05394f39 | 10714 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
d9e86c0e | 10715 | |
f06cc1b9 | 10716 | if (work->flip_queued_req) |
146d84f0 | 10717 | i915_gem_request_assign(&work->flip_queued_req, NULL); |
b4a98e57 CW |
10718 | mutex_unlock(&dev->struct_mutex); |
10719 | ||
a9ff8714 | 10720 | intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit); |
1eb52238 | 10721 | intel_fbc_post_update(crtc); |
89ed88ba | 10722 | drm_framebuffer_unreference(work->old_fb); |
f99d7069 | 10723 | |
a9ff8714 VS |
10724 | BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); |
10725 | atomic_dec(&crtc->unpin_work_count); | |
b4a98e57 | 10726 | |
6b95a207 KH |
10727 | kfree(work); |
10728 | } | |
10729 | ||
1afe3e9d | 10730 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 10731 | struct drm_crtc *crtc) |
6b95a207 | 10732 | { |
6b95a207 KH |
10733 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10734 | struct intel_unpin_work *work; | |
6b95a207 KH |
10735 | unsigned long flags; |
10736 | ||
10737 | /* Ignore early vblank irqs */ | |
10738 | if (intel_crtc == NULL) | |
10739 | return; | |
10740 | ||
f326038a DV |
10741 | /* |
10742 | * This is called both by irq handlers and the reset code (to complete | |
10743 | * lost pageflips) so needs the full irqsave spinlocks. | |
10744 | */ | |
6b95a207 KH |
10745 | spin_lock_irqsave(&dev->event_lock, flags); |
10746 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
10747 | |
10748 | /* Ensure we don't miss a work->pending update ... */ | |
10749 | smp_rmb(); | |
10750 | ||
10751 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
10752 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10753 | return; | |
10754 | } | |
10755 | ||
d6bbafa1 | 10756 | page_flip_completed(intel_crtc); |
0af7e4df | 10757 | |
6b95a207 | 10758 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6b95a207 KH |
10759 | } |
10760 | ||
1afe3e9d JB |
10761 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
10762 | { | |
fbee40df | 10763 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10764 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
10765 | ||
49b14a5c | 10766 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10767 | } |
10768 | ||
10769 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
10770 | { | |
fbee40df | 10771 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10772 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
10773 | ||
49b14a5c | 10774 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10775 | } |
10776 | ||
75f7f3ec VS |
10777 | /* Is 'a' after or equal to 'b'? */ |
10778 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
10779 | { | |
10780 | return !((a - b) & 0x80000000); | |
10781 | } | |
10782 | ||
10783 | static bool page_flip_finished(struct intel_crtc *crtc) | |
10784 | { | |
10785 | struct drm_device *dev = crtc->base.dev; | |
10786 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10787 | ||
bdfa7542 VS |
10788 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
10789 | crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
10790 | return true; | |
10791 | ||
75f7f3ec VS |
10792 | /* |
10793 | * The relevant registers doen't exist on pre-ctg. | |
10794 | * As the flip done interrupt doesn't trigger for mmio | |
10795 | * flips on gmch platforms, a flip count check isn't | |
10796 | * really needed there. But since ctg has the registers, | |
10797 | * include it in the check anyway. | |
10798 | */ | |
10799 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
10800 | return true; | |
10801 | ||
e8861675 ML |
10802 | /* |
10803 | * BDW signals flip done immediately if the plane | |
10804 | * is disabled, even if the plane enable is already | |
10805 | * armed to occur at the next vblank :( | |
10806 | */ | |
10807 | ||
75f7f3ec VS |
10808 | /* |
10809 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
10810 | * used the same base address. In that case the mmio flip might | |
10811 | * have completed, but the CS hasn't even executed the flip yet. | |
10812 | * | |
10813 | * A flip count check isn't enough as the CS might have updated | |
10814 | * the base address just after start of vblank, but before we | |
10815 | * managed to process the interrupt. This means we'd complete the | |
10816 | * CS flip too soon. | |
10817 | * | |
10818 | * Combining both checks should get us a good enough result. It may | |
10819 | * still happen that the CS flip has been executed, but has not | |
10820 | * yet actually completed. But in case the base address is the same | |
10821 | * anyway, we don't really care. | |
10822 | */ | |
10823 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
10824 | crtc->unpin_work->gtt_offset && | |
fd8f507c | 10825 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), |
75f7f3ec VS |
10826 | crtc->unpin_work->flip_count); |
10827 | } | |
10828 | ||
6b95a207 KH |
10829 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
10830 | { | |
fbee40df | 10831 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
10832 | struct intel_crtc *intel_crtc = |
10833 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
10834 | unsigned long flags; | |
10835 | ||
f326038a DV |
10836 | |
10837 | /* | |
10838 | * This is called both by irq handlers and the reset code (to complete | |
10839 | * lost pageflips) so needs the full irqsave spinlocks. | |
10840 | * | |
10841 | * NB: An MMIO update of the plane base pointer will also | |
e7d841ca CW |
10842 | * generate a page-flip completion irq, i.e. every modeset |
10843 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
10844 | */ | |
6b95a207 | 10845 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 10846 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 10847 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
10848 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10849 | } | |
10850 | ||
6042639c | 10851 | static inline void intel_mark_page_flip_active(struct intel_unpin_work *work) |
e7d841ca CW |
10852 | { |
10853 | /* Ensure that the work item is consistent when activating it ... */ | |
10854 | smp_wmb(); | |
6042639c | 10855 | atomic_set(&work->pending, INTEL_FLIP_PENDING); |
e7d841ca CW |
10856 | /* and that it is marked active as soon as the irq could fire. */ |
10857 | smp_wmb(); | |
10858 | } | |
10859 | ||
8c9f3aaf JB |
10860 | static int intel_gen2_queue_flip(struct drm_device *dev, |
10861 | struct drm_crtc *crtc, | |
10862 | struct drm_framebuffer *fb, | |
ed8d1975 | 10863 | struct drm_i915_gem_object *obj, |
6258fbe2 | 10864 | struct drm_i915_gem_request *req, |
ed8d1975 | 10865 | uint32_t flags) |
8c9f3aaf | 10866 | { |
4a570db5 | 10867 | struct intel_engine_cs *engine = req->engine; |
8c9f3aaf | 10868 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
10869 | u32 flip_mask; |
10870 | int ret; | |
10871 | ||
5fb9de1a | 10872 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 10873 | if (ret) |
4fa62c89 | 10874 | return ret; |
8c9f3aaf JB |
10875 | |
10876 | /* Can't queue multiple flips, so wait for the previous | |
10877 | * one to finish before executing the next. | |
10878 | */ | |
10879 | if (intel_crtc->plane) | |
10880 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
10881 | else | |
10882 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
e2f80391 TU |
10883 | intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask); |
10884 | intel_ring_emit(engine, MI_NOOP); | |
10885 | intel_ring_emit(engine, MI_DISPLAY_FLIP | | |
6d90c952 | 10886 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
e2f80391 TU |
10887 | intel_ring_emit(engine, fb->pitches[0]); |
10888 | intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset); | |
10889 | intel_ring_emit(engine, 0); /* aux display base address, unused */ | |
e7d841ca | 10890 | |
6042639c | 10891 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 10892 | return 0; |
8c9f3aaf JB |
10893 | } |
10894 | ||
10895 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
10896 | struct drm_crtc *crtc, | |
10897 | struct drm_framebuffer *fb, | |
ed8d1975 | 10898 | struct drm_i915_gem_object *obj, |
6258fbe2 | 10899 | struct drm_i915_gem_request *req, |
ed8d1975 | 10900 | uint32_t flags) |
8c9f3aaf | 10901 | { |
4a570db5 | 10902 | struct intel_engine_cs *engine = req->engine; |
8c9f3aaf | 10903 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
10904 | u32 flip_mask; |
10905 | int ret; | |
10906 | ||
5fb9de1a | 10907 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 10908 | if (ret) |
4fa62c89 | 10909 | return ret; |
8c9f3aaf JB |
10910 | |
10911 | if (intel_crtc->plane) | |
10912 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
10913 | else | |
10914 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
e2f80391 TU |
10915 | intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask); |
10916 | intel_ring_emit(engine, MI_NOOP); | |
10917 | intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | | |
6d90c952 | 10918 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
e2f80391 TU |
10919 | intel_ring_emit(engine, fb->pitches[0]); |
10920 | intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset); | |
10921 | intel_ring_emit(engine, MI_NOOP); | |
6d90c952 | 10922 | |
6042639c | 10923 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 10924 | return 0; |
8c9f3aaf JB |
10925 | } |
10926 | ||
10927 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
10928 | struct drm_crtc *crtc, | |
10929 | struct drm_framebuffer *fb, | |
ed8d1975 | 10930 | struct drm_i915_gem_object *obj, |
6258fbe2 | 10931 | struct drm_i915_gem_request *req, |
ed8d1975 | 10932 | uint32_t flags) |
8c9f3aaf | 10933 | { |
4a570db5 | 10934 | struct intel_engine_cs *engine = req->engine; |
8c9f3aaf JB |
10935 | struct drm_i915_private *dev_priv = dev->dev_private; |
10936 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10937 | uint32_t pf, pipesrc; | |
10938 | int ret; | |
10939 | ||
5fb9de1a | 10940 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 10941 | if (ret) |
4fa62c89 | 10942 | return ret; |
8c9f3aaf JB |
10943 | |
10944 | /* i965+ uses the linear or tiled offsets from the | |
10945 | * Display Registers (which do not change across a page-flip) | |
10946 | * so we need only reprogram the base address. | |
10947 | */ | |
e2f80391 | 10948 | intel_ring_emit(engine, MI_DISPLAY_FLIP | |
6d90c952 | 10949 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
e2f80391 TU |
10950 | intel_ring_emit(engine, fb->pitches[0]); |
10951 | intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset | | |
c2c75131 | 10952 | obj->tiling_mode); |
8c9f3aaf JB |
10953 | |
10954 | /* XXX Enabling the panel-fitter across page-flip is so far | |
10955 | * untested on non-native modes, so ignore it for now. | |
10956 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
10957 | */ | |
10958 | pf = 0; | |
10959 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
e2f80391 | 10960 | intel_ring_emit(engine, pf | pipesrc); |
e7d841ca | 10961 | |
6042639c | 10962 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 10963 | return 0; |
8c9f3aaf JB |
10964 | } |
10965 | ||
10966 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
10967 | struct drm_crtc *crtc, | |
10968 | struct drm_framebuffer *fb, | |
ed8d1975 | 10969 | struct drm_i915_gem_object *obj, |
6258fbe2 | 10970 | struct drm_i915_gem_request *req, |
ed8d1975 | 10971 | uint32_t flags) |
8c9f3aaf | 10972 | { |
4a570db5 | 10973 | struct intel_engine_cs *engine = req->engine; |
8c9f3aaf JB |
10974 | struct drm_i915_private *dev_priv = dev->dev_private; |
10975 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10976 | uint32_t pf, pipesrc; | |
10977 | int ret; | |
10978 | ||
5fb9de1a | 10979 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 10980 | if (ret) |
4fa62c89 | 10981 | return ret; |
8c9f3aaf | 10982 | |
e2f80391 | 10983 | intel_ring_emit(engine, MI_DISPLAY_FLIP | |
6d90c952 | 10984 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
e2f80391 TU |
10985 | intel_ring_emit(engine, fb->pitches[0] | obj->tiling_mode); |
10986 | intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset); | |
8c9f3aaf | 10987 | |
dc257cf1 DV |
10988 | /* Contrary to the suggestions in the documentation, |
10989 | * "Enable Panel Fitter" does not seem to be required when page | |
10990 | * flipping with a non-native mode, and worse causes a normal | |
10991 | * modeset to fail. | |
10992 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
10993 | */ | |
10994 | pf = 0; | |
8c9f3aaf | 10995 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
e2f80391 | 10996 | intel_ring_emit(engine, pf | pipesrc); |
e7d841ca | 10997 | |
6042639c | 10998 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 10999 | return 0; |
8c9f3aaf JB |
11000 | } |
11001 | ||
7c9017e5 JB |
11002 | static int intel_gen7_queue_flip(struct drm_device *dev, |
11003 | struct drm_crtc *crtc, | |
11004 | struct drm_framebuffer *fb, | |
ed8d1975 | 11005 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11006 | struct drm_i915_gem_request *req, |
ed8d1975 | 11007 | uint32_t flags) |
7c9017e5 | 11008 | { |
4a570db5 | 11009 | struct intel_engine_cs *engine = req->engine; |
7c9017e5 | 11010 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 11011 | uint32_t plane_bit = 0; |
ffe74d75 CW |
11012 | int len, ret; |
11013 | ||
eba905b2 | 11014 | switch (intel_crtc->plane) { |
cb05d8de DV |
11015 | case PLANE_A: |
11016 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
11017 | break; | |
11018 | case PLANE_B: | |
11019 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
11020 | break; | |
11021 | case PLANE_C: | |
11022 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
11023 | break; | |
11024 | default: | |
11025 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 11026 | return -ENODEV; |
cb05d8de DV |
11027 | } |
11028 | ||
ffe74d75 | 11029 | len = 4; |
e2f80391 | 11030 | if (engine->id == RCS) { |
ffe74d75 | 11031 | len += 6; |
f476828a DL |
11032 | /* |
11033 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
11034 | * 48bits addresses, and we need a NOOP for the batch size to | |
11035 | * stay even. | |
11036 | */ | |
11037 | if (IS_GEN8(dev)) | |
11038 | len += 2; | |
11039 | } | |
ffe74d75 | 11040 | |
f66fab8e VS |
11041 | /* |
11042 | * BSpec MI_DISPLAY_FLIP for IVB: | |
11043 | * "The full packet must be contained within the same cache line." | |
11044 | * | |
11045 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
11046 | * cacheline, if we ever start emitting more commands before | |
11047 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
11048 | * then do the cacheline alignment, and finally emit the | |
11049 | * MI_DISPLAY_FLIP. | |
11050 | */ | |
bba09b12 | 11051 | ret = intel_ring_cacheline_align(req); |
f66fab8e | 11052 | if (ret) |
4fa62c89 | 11053 | return ret; |
f66fab8e | 11054 | |
5fb9de1a | 11055 | ret = intel_ring_begin(req, len); |
7c9017e5 | 11056 | if (ret) |
4fa62c89 | 11057 | return ret; |
7c9017e5 | 11058 | |
ffe74d75 CW |
11059 | /* Unmask the flip-done completion message. Note that the bspec says that |
11060 | * we should do this for both the BCS and RCS, and that we must not unmask | |
11061 | * more than one flip event at any time (or ensure that one flip message | |
11062 | * can be sent by waiting for flip-done prior to queueing new flips). | |
11063 | * Experimentation says that BCS works despite DERRMR masking all | |
11064 | * flip-done completion events and that unmasking all planes at once | |
11065 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
11066 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
11067 | */ | |
e2f80391 TU |
11068 | if (engine->id == RCS) { |
11069 | intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1)); | |
11070 | intel_ring_emit_reg(engine, DERRMR); | |
11071 | intel_ring_emit(engine, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
11072 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
11073 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a | 11074 | if (IS_GEN8(dev)) |
e2f80391 | 11075 | intel_ring_emit(engine, MI_STORE_REGISTER_MEM_GEN8 | |
f476828a DL |
11076 | MI_SRM_LRM_GLOBAL_GTT); |
11077 | else | |
e2f80391 | 11078 | intel_ring_emit(engine, MI_STORE_REGISTER_MEM | |
f476828a | 11079 | MI_SRM_LRM_GLOBAL_GTT); |
e2f80391 TU |
11080 | intel_ring_emit_reg(engine, DERRMR); |
11081 | intel_ring_emit(engine, engine->scratch.gtt_offset + 256); | |
f476828a | 11082 | if (IS_GEN8(dev)) { |
e2f80391 TU |
11083 | intel_ring_emit(engine, 0); |
11084 | intel_ring_emit(engine, MI_NOOP); | |
f476828a | 11085 | } |
ffe74d75 CW |
11086 | } |
11087 | ||
e2f80391 TU |
11088 | intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | plane_bit); |
11089 | intel_ring_emit(engine, (fb->pitches[0] | obj->tiling_mode)); | |
11090 | intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset); | |
11091 | intel_ring_emit(engine, (MI_NOOP)); | |
e7d841ca | 11092 | |
6042639c | 11093 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11094 | return 0; |
7c9017e5 JB |
11095 | } |
11096 | ||
0bc40be8 | 11097 | static bool use_mmio_flip(struct intel_engine_cs *engine, |
84c33a64 SG |
11098 | struct drm_i915_gem_object *obj) |
11099 | { | |
11100 | /* | |
11101 | * This is not being used for older platforms, because | |
11102 | * non-availability of flip done interrupt forces us to use | |
11103 | * CS flips. Older platforms derive flip done using some clever | |
11104 | * tricks involving the flip_pending status bits and vblank irqs. | |
11105 | * So using MMIO flips there would disrupt this mechanism. | |
11106 | */ | |
11107 | ||
0bc40be8 | 11108 | if (engine == NULL) |
8e09bf83 CW |
11109 | return true; |
11110 | ||
0bc40be8 | 11111 | if (INTEL_INFO(engine->dev)->gen < 5) |
84c33a64 SG |
11112 | return false; |
11113 | ||
11114 | if (i915.use_mmio_flip < 0) | |
11115 | return false; | |
11116 | else if (i915.use_mmio_flip > 0) | |
11117 | return true; | |
14bf993e OM |
11118 | else if (i915.enable_execlists) |
11119 | return true; | |
fd8e058a AG |
11120 | else if (obj->base.dma_buf && |
11121 | !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv, | |
11122 | false)) | |
11123 | return true; | |
84c33a64 | 11124 | else |
666796da | 11125 | return engine != i915_gem_request_get_engine(obj->last_write_req); |
84c33a64 SG |
11126 | } |
11127 | ||
6042639c | 11128 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, |
86efe24a | 11129 | unsigned int rotation, |
6042639c | 11130 | struct intel_unpin_work *work) |
ff944564 DL |
11131 | { |
11132 | struct drm_device *dev = intel_crtc->base.dev; | |
11133 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11134 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; | |
ff944564 | 11135 | const enum pipe pipe = intel_crtc->pipe; |
86efe24a | 11136 | u32 ctl, stride, tile_height; |
ff944564 DL |
11137 | |
11138 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
11139 | ctl &= ~PLANE_CTL_TILED_MASK; | |
2ebef630 TU |
11140 | switch (fb->modifier[0]) { |
11141 | case DRM_FORMAT_MOD_NONE: | |
11142 | break; | |
11143 | case I915_FORMAT_MOD_X_TILED: | |
ff944564 | 11144 | ctl |= PLANE_CTL_TILED_X; |
2ebef630 TU |
11145 | break; |
11146 | case I915_FORMAT_MOD_Y_TILED: | |
11147 | ctl |= PLANE_CTL_TILED_Y; | |
11148 | break; | |
11149 | case I915_FORMAT_MOD_Yf_TILED: | |
11150 | ctl |= PLANE_CTL_TILED_YF; | |
11151 | break; | |
11152 | default: | |
11153 | MISSING_CASE(fb->modifier[0]); | |
11154 | } | |
ff944564 DL |
11155 | |
11156 | /* | |
11157 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
11158 | * linear buffers or in number of tiles for tiled buffers. | |
11159 | */ | |
86efe24a TU |
11160 | if (intel_rotation_90_or_270(rotation)) { |
11161 | /* stride = Surface height in tiles */ | |
832be82f | 11162 | tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0); |
86efe24a TU |
11163 | stride = DIV_ROUND_UP(fb->height, tile_height); |
11164 | } else { | |
11165 | stride = fb->pitches[0] / | |
7b49f948 VS |
11166 | intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
11167 | fb->pixel_format); | |
86efe24a | 11168 | } |
ff944564 DL |
11169 | |
11170 | /* | |
11171 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
11172 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
11173 | */ | |
11174 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
11175 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
11176 | ||
6042639c | 11177 | I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); |
ff944564 DL |
11178 | POSTING_READ(PLANE_SURF(pipe, 0)); |
11179 | } | |
11180 | ||
6042639c CW |
11181 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, |
11182 | struct intel_unpin_work *work) | |
84c33a64 SG |
11183 | { |
11184 | struct drm_device *dev = intel_crtc->base.dev; | |
11185 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11186 | struct intel_framebuffer *intel_fb = | |
11187 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
11188 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
f0f59a00 | 11189 | i915_reg_t reg = DSPCNTR(intel_crtc->plane); |
84c33a64 | 11190 | u32 dspcntr; |
84c33a64 | 11191 | |
84c33a64 SG |
11192 | dspcntr = I915_READ(reg); |
11193 | ||
c5d97472 DL |
11194 | if (obj->tiling_mode != I915_TILING_NONE) |
11195 | dspcntr |= DISPPLANE_TILED; | |
11196 | else | |
11197 | dspcntr &= ~DISPPLANE_TILED; | |
11198 | ||
84c33a64 SG |
11199 | I915_WRITE(reg, dspcntr); |
11200 | ||
6042639c | 11201 | I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); |
84c33a64 | 11202 | POSTING_READ(DSPSURF(intel_crtc->plane)); |
ff944564 DL |
11203 | } |
11204 | ||
11205 | /* | |
11206 | * XXX: This is the temporary way to update the plane registers until we get | |
11207 | * around to using the usual plane update functions for MMIO flips | |
11208 | */ | |
6042639c | 11209 | static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip) |
ff944564 | 11210 | { |
6042639c CW |
11211 | struct intel_crtc *crtc = mmio_flip->crtc; |
11212 | struct intel_unpin_work *work; | |
11213 | ||
11214 | spin_lock_irq(&crtc->base.dev->event_lock); | |
11215 | work = crtc->unpin_work; | |
11216 | spin_unlock_irq(&crtc->base.dev->event_lock); | |
11217 | if (work == NULL) | |
11218 | return; | |
ff944564 | 11219 | |
6042639c | 11220 | intel_mark_page_flip_active(work); |
ff944564 | 11221 | |
6042639c | 11222 | intel_pipe_update_start(crtc); |
ff944564 | 11223 | |
6042639c | 11224 | if (INTEL_INFO(mmio_flip->i915)->gen >= 9) |
86efe24a | 11225 | skl_do_mmio_flip(crtc, mmio_flip->rotation, work); |
ff944564 DL |
11226 | else |
11227 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
6042639c | 11228 | ilk_do_mmio_flip(crtc, work); |
ff944564 | 11229 | |
6042639c | 11230 | intel_pipe_update_end(crtc); |
84c33a64 SG |
11231 | } |
11232 | ||
9362c7c5 | 11233 | static void intel_mmio_flip_work_func(struct work_struct *work) |
84c33a64 | 11234 | { |
b2cfe0ab CW |
11235 | struct intel_mmio_flip *mmio_flip = |
11236 | container_of(work, struct intel_mmio_flip, work); | |
fd8e058a AG |
11237 | struct intel_framebuffer *intel_fb = |
11238 | to_intel_framebuffer(mmio_flip->crtc->base.primary->fb); | |
11239 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
84c33a64 | 11240 | |
6042639c | 11241 | if (mmio_flip->req) { |
eed29a5b | 11242 | WARN_ON(__i915_wait_request(mmio_flip->req, |
b2cfe0ab | 11243 | mmio_flip->crtc->reset_counter, |
bcafc4e3 CW |
11244 | false, NULL, |
11245 | &mmio_flip->i915->rps.mmioflips)); | |
6042639c CW |
11246 | i915_gem_request_unreference__unlocked(mmio_flip->req); |
11247 | } | |
84c33a64 | 11248 | |
fd8e058a AG |
11249 | /* For framebuffer backed by dmabuf, wait for fence */ |
11250 | if (obj->base.dma_buf) | |
11251 | WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv, | |
11252 | false, false, | |
11253 | MAX_SCHEDULE_TIMEOUT) < 0); | |
11254 | ||
6042639c | 11255 | intel_do_mmio_flip(mmio_flip); |
b2cfe0ab | 11256 | kfree(mmio_flip); |
84c33a64 SG |
11257 | } |
11258 | ||
11259 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
11260 | struct drm_crtc *crtc, | |
86efe24a | 11261 | struct drm_i915_gem_object *obj) |
84c33a64 | 11262 | { |
b2cfe0ab CW |
11263 | struct intel_mmio_flip *mmio_flip; |
11264 | ||
11265 | mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL); | |
11266 | if (mmio_flip == NULL) | |
11267 | return -ENOMEM; | |
84c33a64 | 11268 | |
bcafc4e3 | 11269 | mmio_flip->i915 = to_i915(dev); |
eed29a5b | 11270 | mmio_flip->req = i915_gem_request_reference(obj->last_write_req); |
b2cfe0ab | 11271 | mmio_flip->crtc = to_intel_crtc(crtc); |
86efe24a | 11272 | mmio_flip->rotation = crtc->primary->state->rotation; |
536f5b5e | 11273 | |
b2cfe0ab CW |
11274 | INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func); |
11275 | schedule_work(&mmio_flip->work); | |
84c33a64 | 11276 | |
84c33a64 SG |
11277 | return 0; |
11278 | } | |
11279 | ||
8c9f3aaf JB |
11280 | static int intel_default_queue_flip(struct drm_device *dev, |
11281 | struct drm_crtc *crtc, | |
11282 | struct drm_framebuffer *fb, | |
ed8d1975 | 11283 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11284 | struct drm_i915_gem_request *req, |
ed8d1975 | 11285 | uint32_t flags) |
8c9f3aaf JB |
11286 | { |
11287 | return -ENODEV; | |
11288 | } | |
11289 | ||
d6bbafa1 CW |
11290 | static bool __intel_pageflip_stall_check(struct drm_device *dev, |
11291 | struct drm_crtc *crtc) | |
11292 | { | |
11293 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11294 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11295 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
11296 | u32 addr; | |
11297 | ||
11298 | if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) | |
11299 | return true; | |
11300 | ||
908565c2 CW |
11301 | if (atomic_read(&work->pending) < INTEL_FLIP_PENDING) |
11302 | return false; | |
11303 | ||
d6bbafa1 CW |
11304 | if (!work->enable_stall_check) |
11305 | return false; | |
11306 | ||
11307 | if (work->flip_ready_vblank == 0) { | |
3a8a946e DV |
11308 | if (work->flip_queued_req && |
11309 | !i915_gem_request_completed(work->flip_queued_req, true)) | |
d6bbafa1 CW |
11310 | return false; |
11311 | ||
1e3feefd | 11312 | work->flip_ready_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 CW |
11313 | } |
11314 | ||
1e3feefd | 11315 | if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) |
d6bbafa1 CW |
11316 | return false; |
11317 | ||
11318 | /* Potential stall - if we see that the flip has happened, | |
11319 | * assume a missed interrupt. */ | |
11320 | if (INTEL_INFO(dev)->gen >= 4) | |
11321 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
11322 | else | |
11323 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
11324 | ||
11325 | /* There is a potential issue here with a false positive after a flip | |
11326 | * to the same address. We could address this by checking for a | |
11327 | * non-incrementing frame counter. | |
11328 | */ | |
11329 | return addr == work->gtt_offset; | |
11330 | } | |
11331 | ||
11332 | void intel_check_page_flip(struct drm_device *dev, int pipe) | |
11333 | { | |
11334 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11335 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
11336 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6ad790c0 | 11337 | struct intel_unpin_work *work; |
f326038a | 11338 | |
6c51d46f | 11339 | WARN_ON(!in_interrupt()); |
d6bbafa1 CW |
11340 | |
11341 | if (crtc == NULL) | |
11342 | return; | |
11343 | ||
f326038a | 11344 | spin_lock(&dev->event_lock); |
6ad790c0 CW |
11345 | work = intel_crtc->unpin_work; |
11346 | if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) { | |
d6bbafa1 | 11347 | WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", |
6ad790c0 | 11348 | work->flip_queued_vblank, drm_vblank_count(dev, pipe)); |
d6bbafa1 | 11349 | page_flip_completed(intel_crtc); |
6ad790c0 | 11350 | work = NULL; |
d6bbafa1 | 11351 | } |
6ad790c0 CW |
11352 | if (work != NULL && |
11353 | drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1) | |
11354 | intel_queue_rps_boost_for_request(dev, work->flip_queued_req); | |
f326038a | 11355 | spin_unlock(&dev->event_lock); |
d6bbafa1 CW |
11356 | } |
11357 | ||
6b95a207 KH |
11358 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
11359 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
11360 | struct drm_pending_vblank_event *event, |
11361 | uint32_t page_flip_flags) | |
6b95a207 KH |
11362 | { |
11363 | struct drm_device *dev = crtc->dev; | |
11364 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 11365 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 11366 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 | 11367 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
455a6808 | 11368 | struct drm_plane *primary = crtc->primary; |
a071fa00 | 11369 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 11370 | struct intel_unpin_work *work; |
e2f80391 | 11371 | struct intel_engine_cs *engine; |
cf5d8a46 | 11372 | bool mmio_flip; |
91af127f | 11373 | struct drm_i915_gem_request *request = NULL; |
52e68630 | 11374 | int ret; |
6b95a207 | 11375 | |
2ff8fde1 MR |
11376 | /* |
11377 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
11378 | * check to be safe. In the future we may enable pageflipping from | |
11379 | * a disabled primary plane. | |
11380 | */ | |
11381 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
11382 | return -EBUSY; | |
11383 | ||
e6a595d2 | 11384 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 11385 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
11386 | return -EINVAL; |
11387 | ||
11388 | /* | |
11389 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
11390 | * Note that pitch changes could also affect these register. | |
11391 | */ | |
11392 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
11393 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
11394 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
11395 | return -EINVAL; |
11396 | ||
f900db47 CW |
11397 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
11398 | goto out_hang; | |
11399 | ||
b14c5679 | 11400 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
11401 | if (work == NULL) |
11402 | return -ENOMEM; | |
11403 | ||
6b95a207 | 11404 | work->event = event; |
b4a98e57 | 11405 | work->crtc = crtc; |
ab8d6675 | 11406 | work->old_fb = old_fb; |
6b95a207 KH |
11407 | INIT_WORK(&work->work, intel_unpin_work_fn); |
11408 | ||
87b6b101 | 11409 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
11410 | if (ret) |
11411 | goto free_work; | |
11412 | ||
6b95a207 | 11413 | /* We borrow the event spin lock for protecting unpin_work */ |
5e2d7afc | 11414 | spin_lock_irq(&dev->event_lock); |
6b95a207 | 11415 | if (intel_crtc->unpin_work) { |
d6bbafa1 CW |
11416 | /* Before declaring the flip queue wedged, check if |
11417 | * the hardware completed the operation behind our backs. | |
11418 | */ | |
11419 | if (__intel_pageflip_stall_check(dev, crtc)) { | |
11420 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
11421 | page_flip_completed(intel_crtc); | |
11422 | } else { | |
11423 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
5e2d7afc | 11424 | spin_unlock_irq(&dev->event_lock); |
468f0b44 | 11425 | |
d6bbafa1 CW |
11426 | drm_crtc_vblank_put(crtc); |
11427 | kfree(work); | |
11428 | return -EBUSY; | |
11429 | } | |
6b95a207 KH |
11430 | } |
11431 | intel_crtc->unpin_work = work; | |
5e2d7afc | 11432 | spin_unlock_irq(&dev->event_lock); |
6b95a207 | 11433 | |
b4a98e57 CW |
11434 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
11435 | flush_workqueue(dev_priv->wq); | |
11436 | ||
75dfca80 | 11437 | /* Reference the objects for the scheduled work. */ |
ab8d6675 | 11438 | drm_framebuffer_reference(work->old_fb); |
05394f39 | 11439 | drm_gem_object_reference(&obj->base); |
6b95a207 | 11440 | |
f4510a27 | 11441 | crtc->primary->fb = fb; |
afd65eb4 | 11442 | update_state_fb(crtc->primary); |
e8216e50 | 11443 | intel_fbc_pre_update(intel_crtc); |
1ed1f968 | 11444 | |
e1f99ce6 | 11445 | work->pending_flip_obj = obj; |
e1f99ce6 | 11446 | |
89ed88ba CW |
11447 | ret = i915_mutex_lock_interruptible(dev); |
11448 | if (ret) | |
11449 | goto cleanup; | |
11450 | ||
b4a98e57 | 11451 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 11452 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 11453 | |
75f7f3ec | 11454 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
fd8f507c | 11455 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; |
75f7f3ec | 11456 | |
666a4537 | 11457 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
4a570db5 | 11458 | engine = &dev_priv->engine[BCS]; |
ab8d6675 | 11459 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) |
8e09bf83 | 11460 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
e2f80391 | 11461 | engine = NULL; |
48bf5b2d | 11462 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
4a570db5 | 11463 | engine = &dev_priv->engine[BCS]; |
4fa62c89 | 11464 | } else if (INTEL_INFO(dev)->gen >= 7) { |
666796da | 11465 | engine = i915_gem_request_get_engine(obj->last_write_req); |
e2f80391 | 11466 | if (engine == NULL || engine->id != RCS) |
4a570db5 | 11467 | engine = &dev_priv->engine[BCS]; |
4fa62c89 | 11468 | } else { |
4a570db5 | 11469 | engine = &dev_priv->engine[RCS]; |
4fa62c89 VS |
11470 | } |
11471 | ||
e2f80391 | 11472 | mmio_flip = use_mmio_flip(engine, obj); |
cf5d8a46 CW |
11473 | |
11474 | /* When using CS flips, we want to emit semaphores between rings. | |
11475 | * However, when using mmio flips we will create a task to do the | |
11476 | * synchronisation, so all we want here is to pin the framebuffer | |
11477 | * into the display plane and skip any waits. | |
11478 | */ | |
7580d774 | 11479 | if (!mmio_flip) { |
e2f80391 | 11480 | ret = i915_gem_object_sync(obj, engine, &request); |
7580d774 ML |
11481 | if (ret) |
11482 | goto cleanup_pending; | |
11483 | } | |
11484 | ||
3465c580 | 11485 | ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation); |
8c9f3aaf JB |
11486 | if (ret) |
11487 | goto cleanup_pending; | |
6b95a207 | 11488 | |
dedf278c TU |
11489 | work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), |
11490 | obj, 0); | |
11491 | work->gtt_offset += intel_crtc->dspaddr_offset; | |
4fa62c89 | 11492 | |
cf5d8a46 | 11493 | if (mmio_flip) { |
86efe24a | 11494 | ret = intel_queue_mmio_flip(dev, crtc, obj); |
d6bbafa1 CW |
11495 | if (ret) |
11496 | goto cleanup_unpin; | |
11497 | ||
f06cc1b9 JH |
11498 | i915_gem_request_assign(&work->flip_queued_req, |
11499 | obj->last_write_req); | |
d6bbafa1 | 11500 | } else { |
6258fbe2 | 11501 | if (!request) { |
e2f80391 | 11502 | request = i915_gem_request_alloc(engine, NULL); |
26827088 DG |
11503 | if (IS_ERR(request)) { |
11504 | ret = PTR_ERR(request); | |
6258fbe2 | 11505 | goto cleanup_unpin; |
26827088 | 11506 | } |
6258fbe2 JH |
11507 | } |
11508 | ||
11509 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, | |
d6bbafa1 CW |
11510 | page_flip_flags); |
11511 | if (ret) | |
11512 | goto cleanup_unpin; | |
11513 | ||
6258fbe2 | 11514 | i915_gem_request_assign(&work->flip_queued_req, request); |
d6bbafa1 CW |
11515 | } |
11516 | ||
91af127f | 11517 | if (request) |
75289874 | 11518 | i915_add_request_no_flush(request); |
91af127f | 11519 | |
1e3feefd | 11520 | work->flip_queued_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 | 11521 | work->enable_stall_check = true; |
4fa62c89 | 11522 | |
ab8d6675 | 11523 | i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, |
a9ff8714 | 11524 | to_intel_plane(primary)->frontbuffer_bit); |
c80ac854 | 11525 | mutex_unlock(&dev->struct_mutex); |
a071fa00 | 11526 | |
a9ff8714 VS |
11527 | intel_frontbuffer_flip_prepare(dev, |
11528 | to_intel_plane(primary)->frontbuffer_bit); | |
6b95a207 | 11529 | |
e5510fac JB |
11530 | trace_i915_flip_request(intel_crtc->plane, obj); |
11531 | ||
6b95a207 | 11532 | return 0; |
96b099fd | 11533 | |
4fa62c89 | 11534 | cleanup_unpin: |
3465c580 | 11535 | intel_unpin_fb_obj(fb, crtc->primary->state->rotation); |
8c9f3aaf | 11536 | cleanup_pending: |
0aa498d5 | 11537 | if (!IS_ERR_OR_NULL(request)) |
91af127f | 11538 | i915_gem_request_cancel(request); |
b4a98e57 | 11539 | atomic_dec(&intel_crtc->unpin_work_count); |
89ed88ba CW |
11540 | mutex_unlock(&dev->struct_mutex); |
11541 | cleanup: | |
f4510a27 | 11542 | crtc->primary->fb = old_fb; |
afd65eb4 | 11543 | update_state_fb(crtc->primary); |
89ed88ba CW |
11544 | |
11545 | drm_gem_object_unreference_unlocked(&obj->base); | |
ab8d6675 | 11546 | drm_framebuffer_unreference(work->old_fb); |
96b099fd | 11547 | |
5e2d7afc | 11548 | spin_lock_irq(&dev->event_lock); |
96b099fd | 11549 | intel_crtc->unpin_work = NULL; |
5e2d7afc | 11550 | spin_unlock_irq(&dev->event_lock); |
96b099fd | 11551 | |
87b6b101 | 11552 | drm_crtc_vblank_put(crtc); |
7317c75e | 11553 | free_work: |
96b099fd CW |
11554 | kfree(work); |
11555 | ||
f900db47 | 11556 | if (ret == -EIO) { |
02e0efb5 ML |
11557 | struct drm_atomic_state *state; |
11558 | struct drm_plane_state *plane_state; | |
11559 | ||
f900db47 | 11560 | out_hang: |
02e0efb5 ML |
11561 | state = drm_atomic_state_alloc(dev); |
11562 | if (!state) | |
11563 | return -ENOMEM; | |
11564 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); | |
11565 | ||
11566 | retry: | |
11567 | plane_state = drm_atomic_get_plane_state(state, primary); | |
11568 | ret = PTR_ERR_OR_ZERO(plane_state); | |
11569 | if (!ret) { | |
11570 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
11571 | ||
11572 | ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); | |
11573 | if (!ret) | |
11574 | ret = drm_atomic_commit(state); | |
11575 | } | |
11576 | ||
11577 | if (ret == -EDEADLK) { | |
11578 | drm_modeset_backoff(state->acquire_ctx); | |
11579 | drm_atomic_state_clear(state); | |
11580 | goto retry; | |
11581 | } | |
11582 | ||
11583 | if (ret) | |
11584 | drm_atomic_state_free(state); | |
11585 | ||
f0d3dad3 | 11586 | if (ret == 0 && event) { |
5e2d7afc | 11587 | spin_lock_irq(&dev->event_lock); |
a071fa00 | 11588 | drm_send_vblank_event(dev, pipe, event); |
5e2d7afc | 11589 | spin_unlock_irq(&dev->event_lock); |
f0d3dad3 | 11590 | } |
f900db47 | 11591 | } |
96b099fd | 11592 | return ret; |
6b95a207 KH |
11593 | } |
11594 | ||
da20eabd ML |
11595 | |
11596 | /** | |
11597 | * intel_wm_need_update - Check whether watermarks need updating | |
11598 | * @plane: drm plane | |
11599 | * @state: new plane state | |
11600 | * | |
11601 | * Check current plane state versus the new one to determine whether | |
11602 | * watermarks need to be recalculated. | |
11603 | * | |
11604 | * Returns true or false. | |
11605 | */ | |
11606 | static bool intel_wm_need_update(struct drm_plane *plane, | |
11607 | struct drm_plane_state *state) | |
11608 | { | |
d21fbe87 MR |
11609 | struct intel_plane_state *new = to_intel_plane_state(state); |
11610 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); | |
11611 | ||
11612 | /* Update watermarks on tiling or size changes. */ | |
92826fcd ML |
11613 | if (new->visible != cur->visible) |
11614 | return true; | |
11615 | ||
11616 | if (!cur->base.fb || !new->base.fb) | |
11617 | return false; | |
11618 | ||
11619 | if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] || | |
11620 | cur->base.rotation != new->base.rotation || | |
d21fbe87 MR |
11621 | drm_rect_width(&new->src) != drm_rect_width(&cur->src) || |
11622 | drm_rect_height(&new->src) != drm_rect_height(&cur->src) || | |
11623 | drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) || | |
11624 | drm_rect_height(&new->dst) != drm_rect_height(&cur->dst)) | |
2791a16c | 11625 | return true; |
7809e5ae | 11626 | |
2791a16c | 11627 | return false; |
7809e5ae MR |
11628 | } |
11629 | ||
d21fbe87 MR |
11630 | static bool needs_scaling(struct intel_plane_state *state) |
11631 | { | |
11632 | int src_w = drm_rect_width(&state->src) >> 16; | |
11633 | int src_h = drm_rect_height(&state->src) >> 16; | |
11634 | int dst_w = drm_rect_width(&state->dst); | |
11635 | int dst_h = drm_rect_height(&state->dst); | |
11636 | ||
11637 | return (src_w != dst_w || src_h != dst_h); | |
11638 | } | |
11639 | ||
da20eabd ML |
11640 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
11641 | struct drm_plane_state *plane_state) | |
11642 | { | |
ab1d3a0e | 11643 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
da20eabd ML |
11644 | struct drm_crtc *crtc = crtc_state->crtc; |
11645 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11646 | struct drm_plane *plane = plane_state->plane; | |
11647 | struct drm_device *dev = crtc->dev; | |
ed4a6a7c | 11648 | struct drm_i915_private *dev_priv = to_i915(dev); |
da20eabd ML |
11649 | struct intel_plane_state *old_plane_state = |
11650 | to_intel_plane_state(plane->state); | |
11651 | int idx = intel_crtc->base.base.id, ret; | |
da20eabd ML |
11652 | bool mode_changed = needs_modeset(crtc_state); |
11653 | bool was_crtc_enabled = crtc->state->active; | |
11654 | bool is_crtc_enabled = crtc_state->active; | |
da20eabd ML |
11655 | bool turn_off, turn_on, visible, was_visible; |
11656 | struct drm_framebuffer *fb = plane_state->fb; | |
11657 | ||
11658 | if (crtc_state && INTEL_INFO(dev)->gen >= 9 && | |
11659 | plane->type != DRM_PLANE_TYPE_CURSOR) { | |
11660 | ret = skl_update_scaler_plane( | |
11661 | to_intel_crtc_state(crtc_state), | |
11662 | to_intel_plane_state(plane_state)); | |
11663 | if (ret) | |
11664 | return ret; | |
11665 | } | |
11666 | ||
da20eabd ML |
11667 | was_visible = old_plane_state->visible; |
11668 | visible = to_intel_plane_state(plane_state)->visible; | |
11669 | ||
11670 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
11671 | was_visible = false; | |
11672 | ||
35c08f43 ML |
11673 | /* |
11674 | * Visibility is calculated as if the crtc was on, but | |
11675 | * after scaler setup everything depends on it being off | |
11676 | * when the crtc isn't active. | |
11677 | */ | |
11678 | if (!is_crtc_enabled) | |
11679 | to_intel_plane_state(plane_state)->visible = visible = false; | |
da20eabd ML |
11680 | |
11681 | if (!was_visible && !visible) | |
11682 | return 0; | |
11683 | ||
e8861675 ML |
11684 | if (fb != old_plane_state->base.fb) |
11685 | pipe_config->fb_changed = true; | |
11686 | ||
da20eabd ML |
11687 | turn_off = was_visible && (!visible || mode_changed); |
11688 | turn_on = visible && (!was_visible || mode_changed); | |
11689 | ||
11690 | DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx, | |
11691 | plane->base.id, fb ? fb->base.id : -1); | |
11692 | ||
11693 | DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n", | |
11694 | plane->base.id, was_visible, visible, | |
11695 | turn_off, turn_on, mode_changed); | |
11696 | ||
caed361d VS |
11697 | if (turn_on) { |
11698 | pipe_config->update_wm_pre = true; | |
11699 | ||
11700 | /* must disable cxsr around plane enable/disable */ | |
11701 | if (plane->type != DRM_PLANE_TYPE_CURSOR) | |
11702 | pipe_config->disable_cxsr = true; | |
11703 | } else if (turn_off) { | |
11704 | pipe_config->update_wm_post = true; | |
92826fcd | 11705 | |
852eb00d | 11706 | /* must disable cxsr around plane enable/disable */ |
e8861675 | 11707 | if (plane->type != DRM_PLANE_TYPE_CURSOR) |
ab1d3a0e | 11708 | pipe_config->disable_cxsr = true; |
852eb00d | 11709 | } else if (intel_wm_need_update(plane, plane_state)) { |
caed361d VS |
11710 | /* FIXME bollocks */ |
11711 | pipe_config->update_wm_pre = true; | |
11712 | pipe_config->update_wm_post = true; | |
852eb00d | 11713 | } |
da20eabd | 11714 | |
ed4a6a7c | 11715 | /* Pre-gen9 platforms need two-step watermark updates */ |
caed361d VS |
11716 | if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) && |
11717 | INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks) | |
ed4a6a7c MR |
11718 | to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true; |
11719 | ||
8be6ca85 | 11720 | if (visible || was_visible) |
cd202f69 | 11721 | pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit; |
a9ff8714 | 11722 | |
31ae71fc ML |
11723 | /* |
11724 | * WaCxSRDisabledForSpriteScaling:ivb | |
11725 | * | |
11726 | * cstate->update_wm was already set above, so this flag will | |
11727 | * take effect when we commit and program watermarks. | |
11728 | */ | |
11729 | if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) && | |
11730 | needs_scaling(to_intel_plane_state(plane_state)) && | |
11731 | !needs_scaling(old_plane_state)) | |
11732 | pipe_config->disable_lp_wm = true; | |
d21fbe87 | 11733 | |
da20eabd ML |
11734 | return 0; |
11735 | } | |
11736 | ||
6d3a1ce7 ML |
11737 | static bool encoders_cloneable(const struct intel_encoder *a, |
11738 | const struct intel_encoder *b) | |
11739 | { | |
11740 | /* masks could be asymmetric, so check both ways */ | |
11741 | return a == b || (a->cloneable & (1 << b->type) && | |
11742 | b->cloneable & (1 << a->type)); | |
11743 | } | |
11744 | ||
11745 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
11746 | struct intel_crtc *crtc, | |
11747 | struct intel_encoder *encoder) | |
11748 | { | |
11749 | struct intel_encoder *source_encoder; | |
11750 | struct drm_connector *connector; | |
11751 | struct drm_connector_state *connector_state; | |
11752 | int i; | |
11753 | ||
11754 | for_each_connector_in_state(state, connector, connector_state, i) { | |
11755 | if (connector_state->crtc != &crtc->base) | |
11756 | continue; | |
11757 | ||
11758 | source_encoder = | |
11759 | to_intel_encoder(connector_state->best_encoder); | |
11760 | if (!encoders_cloneable(encoder, source_encoder)) | |
11761 | return false; | |
11762 | } | |
11763 | ||
11764 | return true; | |
11765 | } | |
11766 | ||
11767 | static bool check_encoder_cloning(struct drm_atomic_state *state, | |
11768 | struct intel_crtc *crtc) | |
11769 | { | |
11770 | struct intel_encoder *encoder; | |
11771 | struct drm_connector *connector; | |
11772 | struct drm_connector_state *connector_state; | |
11773 | int i; | |
11774 | ||
11775 | for_each_connector_in_state(state, connector, connector_state, i) { | |
11776 | if (connector_state->crtc != &crtc->base) | |
11777 | continue; | |
11778 | ||
11779 | encoder = to_intel_encoder(connector_state->best_encoder); | |
11780 | if (!check_single_encoder_cloning(state, crtc, encoder)) | |
11781 | return false; | |
11782 | } | |
11783 | ||
11784 | return true; | |
11785 | } | |
11786 | ||
11787 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, | |
11788 | struct drm_crtc_state *crtc_state) | |
11789 | { | |
cf5a15be | 11790 | struct drm_device *dev = crtc->dev; |
ad421372 | 11791 | struct drm_i915_private *dev_priv = dev->dev_private; |
6d3a1ce7 | 11792 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
11793 | struct intel_crtc_state *pipe_config = |
11794 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 11795 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 11796 | int ret; |
6d3a1ce7 ML |
11797 | bool mode_changed = needs_modeset(crtc_state); |
11798 | ||
11799 | if (mode_changed && !check_encoder_cloning(state, intel_crtc)) { | |
11800 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
11801 | return -EINVAL; | |
11802 | } | |
11803 | ||
852eb00d | 11804 | if (mode_changed && !crtc_state->active) |
caed361d | 11805 | pipe_config->update_wm_post = true; |
eddfcbcd | 11806 | |
ad421372 ML |
11807 | if (mode_changed && crtc_state->enable && |
11808 | dev_priv->display.crtc_compute_clock && | |
8106ddbd | 11809 | !WARN_ON(pipe_config->shared_dpll)) { |
ad421372 ML |
11810 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, |
11811 | pipe_config); | |
11812 | if (ret) | |
11813 | return ret; | |
11814 | } | |
11815 | ||
82cf435b LL |
11816 | if (crtc_state->color_mgmt_changed) { |
11817 | ret = intel_color_check(crtc, crtc_state); | |
11818 | if (ret) | |
11819 | return ret; | |
11820 | } | |
11821 | ||
e435d6e5 | 11822 | ret = 0; |
86c8bbbe | 11823 | if (dev_priv->display.compute_pipe_wm) { |
e3bddded | 11824 | ret = dev_priv->display.compute_pipe_wm(pipe_config); |
ed4a6a7c MR |
11825 | if (ret) { |
11826 | DRM_DEBUG_KMS("Target pipe watermarks are invalid\n"); | |
11827 | return ret; | |
11828 | } | |
11829 | } | |
11830 | ||
11831 | if (dev_priv->display.compute_intermediate_wm && | |
11832 | !to_intel_atomic_state(state)->skip_intermediate_wm) { | |
11833 | if (WARN_ON(!dev_priv->display.compute_pipe_wm)) | |
11834 | return 0; | |
11835 | ||
11836 | /* | |
11837 | * Calculate 'intermediate' watermarks that satisfy both the | |
11838 | * old state and the new state. We can program these | |
11839 | * immediately. | |
11840 | */ | |
11841 | ret = dev_priv->display.compute_intermediate_wm(crtc->dev, | |
11842 | intel_crtc, | |
11843 | pipe_config); | |
11844 | if (ret) { | |
11845 | DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n"); | |
86c8bbbe | 11846 | return ret; |
ed4a6a7c | 11847 | } |
86c8bbbe MR |
11848 | } |
11849 | ||
e435d6e5 ML |
11850 | if (INTEL_INFO(dev)->gen >= 9) { |
11851 | if (mode_changed) | |
11852 | ret = skl_update_scaler_crtc(pipe_config); | |
11853 | ||
11854 | if (!ret) | |
11855 | ret = intel_atomic_setup_scalers(dev, intel_crtc, | |
11856 | pipe_config); | |
11857 | } | |
11858 | ||
11859 | return ret; | |
6d3a1ce7 ML |
11860 | } |
11861 | ||
65b38e0d | 11862 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 | 11863 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
ea2c67bb MR |
11864 | .atomic_begin = intel_begin_crtc_commit, |
11865 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 11866 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
11867 | }; |
11868 | ||
d29b2f9d ACO |
11869 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
11870 | { | |
11871 | struct intel_connector *connector; | |
11872 | ||
11873 | for_each_intel_connector(dev, connector) { | |
11874 | if (connector->base.encoder) { | |
11875 | connector->base.state->best_encoder = | |
11876 | connector->base.encoder; | |
11877 | connector->base.state->crtc = | |
11878 | connector->base.encoder->crtc; | |
11879 | } else { | |
11880 | connector->base.state->best_encoder = NULL; | |
11881 | connector->base.state->crtc = NULL; | |
11882 | } | |
11883 | } | |
11884 | } | |
11885 | ||
050f7aeb | 11886 | static void |
eba905b2 | 11887 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 11888 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
11889 | { |
11890 | int bpp = pipe_config->pipe_bpp; | |
11891 | ||
11892 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
11893 | connector->base.base.id, | |
c23cc417 | 11894 | connector->base.name); |
050f7aeb DV |
11895 | |
11896 | /* Don't use an invalid EDID bpc value */ | |
11897 | if (connector->base.display_info.bpc && | |
11898 | connector->base.display_info.bpc * 3 < bpp) { | |
11899 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
11900 | bpp, connector->base.display_info.bpc*3); | |
11901 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
11902 | } | |
11903 | ||
013dd9e0 JN |
11904 | /* Clamp bpp to default limit on screens without EDID 1.4 */ |
11905 | if (connector->base.display_info.bpc == 0) { | |
11906 | int type = connector->base.connector_type; | |
11907 | int clamp_bpp = 24; | |
11908 | ||
11909 | /* Fall back to 18 bpp when DP sink capability is unknown. */ | |
11910 | if (type == DRM_MODE_CONNECTOR_DisplayPort || | |
11911 | type == DRM_MODE_CONNECTOR_eDP) | |
11912 | clamp_bpp = 18; | |
11913 | ||
11914 | if (bpp > clamp_bpp) { | |
11915 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n", | |
11916 | bpp, clamp_bpp); | |
11917 | pipe_config->pipe_bpp = clamp_bpp; | |
11918 | } | |
050f7aeb DV |
11919 | } |
11920 | } | |
11921 | ||
4e53c2e0 | 11922 | static int |
050f7aeb | 11923 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 11924 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 11925 | { |
050f7aeb | 11926 | struct drm_device *dev = crtc->base.dev; |
1486017f | 11927 | struct drm_atomic_state *state; |
da3ced29 ACO |
11928 | struct drm_connector *connector; |
11929 | struct drm_connector_state *connector_state; | |
1486017f | 11930 | int bpp, i; |
4e53c2e0 | 11931 | |
666a4537 | 11932 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) |
4e53c2e0 | 11933 | bpp = 10*3; |
d328c9d7 DV |
11934 | else if (INTEL_INFO(dev)->gen >= 5) |
11935 | bpp = 12*3; | |
11936 | else | |
11937 | bpp = 8*3; | |
11938 | ||
4e53c2e0 | 11939 | |
4e53c2e0 DV |
11940 | pipe_config->pipe_bpp = bpp; |
11941 | ||
1486017f ACO |
11942 | state = pipe_config->base.state; |
11943 | ||
4e53c2e0 | 11944 | /* Clamp display bpp to EDID value */ |
da3ced29 ACO |
11945 | for_each_connector_in_state(state, connector, connector_state, i) { |
11946 | if (connector_state->crtc != &crtc->base) | |
4e53c2e0 DV |
11947 | continue; |
11948 | ||
da3ced29 ACO |
11949 | connected_sink_compute_bpp(to_intel_connector(connector), |
11950 | pipe_config); | |
4e53c2e0 DV |
11951 | } |
11952 | ||
11953 | return bpp; | |
11954 | } | |
11955 | ||
644db711 DV |
11956 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
11957 | { | |
11958 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
11959 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 11960 | mode->crtc_clock, |
644db711 DV |
11961 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
11962 | mode->crtc_hsync_end, mode->crtc_htotal, | |
11963 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
11964 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
11965 | } | |
11966 | ||
c0b03411 | 11967 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 11968 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
11969 | const char *context) |
11970 | { | |
6a60cd87 CK |
11971 | struct drm_device *dev = crtc->base.dev; |
11972 | struct drm_plane *plane; | |
11973 | struct intel_plane *intel_plane; | |
11974 | struct intel_plane_state *state; | |
11975 | struct drm_framebuffer *fb; | |
11976 | ||
11977 | DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id, | |
11978 | context, pipe_config, pipe_name(crtc->pipe)); | |
c0b03411 | 11979 | |
da205630 | 11980 | DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder)); |
c0b03411 DV |
11981 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", |
11982 | pipe_config->pipe_bpp, pipe_config->dither); | |
11983 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
11984 | pipe_config->has_pch_encoder, | |
11985 | pipe_config->fdi_lanes, | |
11986 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
11987 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
11988 | pipe_config->fdi_m_n.tu); | |
90a6b7b0 | 11989 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
eb14cb74 | 11990 | pipe_config->has_dp_encoder, |
90a6b7b0 | 11991 | pipe_config->lane_count, |
eb14cb74 VS |
11992 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, |
11993 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
11994 | pipe_config->dp_m_n.tu); | |
b95af8be | 11995 | |
90a6b7b0 | 11996 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", |
b95af8be | 11997 | pipe_config->has_dp_encoder, |
90a6b7b0 | 11998 | pipe_config->lane_count, |
b95af8be VK |
11999 | pipe_config->dp_m2_n2.gmch_m, |
12000 | pipe_config->dp_m2_n2.gmch_n, | |
12001 | pipe_config->dp_m2_n2.link_m, | |
12002 | pipe_config->dp_m2_n2.link_n, | |
12003 | pipe_config->dp_m2_n2.tu); | |
12004 | ||
55072d19 DV |
12005 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
12006 | pipe_config->has_audio, | |
12007 | pipe_config->has_infoframe); | |
12008 | ||
c0b03411 | 12009 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 12010 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 12011 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
12012 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
12013 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 12014 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
12015 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
12016 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
0ec463d3 TU |
12017 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", |
12018 | crtc->num_scalers, | |
12019 | pipe_config->scaler_state.scaler_users, | |
12020 | pipe_config->scaler_state.scaler_id); | |
c0b03411 DV |
12021 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
12022 | pipe_config->gmch_pfit.control, | |
12023 | pipe_config->gmch_pfit.pgm_ratios, | |
12024 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 12025 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 12026 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
12027 | pipe_config->pch_pfit.size, |
12028 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 12029 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 12030 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
6a60cd87 | 12031 | |
415ff0f6 | 12032 | if (IS_BROXTON(dev)) { |
05712c15 | 12033 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," |
415ff0f6 | 12034 | "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " |
c8453338 | 12035 | "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", |
415ff0f6 TU |
12036 | pipe_config->ddi_pll_sel, |
12037 | pipe_config->dpll_hw_state.ebb0, | |
05712c15 | 12038 | pipe_config->dpll_hw_state.ebb4, |
415ff0f6 TU |
12039 | pipe_config->dpll_hw_state.pll0, |
12040 | pipe_config->dpll_hw_state.pll1, | |
12041 | pipe_config->dpll_hw_state.pll2, | |
12042 | pipe_config->dpll_hw_state.pll3, | |
12043 | pipe_config->dpll_hw_state.pll6, | |
12044 | pipe_config->dpll_hw_state.pll8, | |
05712c15 | 12045 | pipe_config->dpll_hw_state.pll9, |
c8453338 | 12046 | pipe_config->dpll_hw_state.pll10, |
415ff0f6 | 12047 | pipe_config->dpll_hw_state.pcsdw12); |
ef11bdb3 | 12048 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
415ff0f6 TU |
12049 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " |
12050 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", | |
12051 | pipe_config->ddi_pll_sel, | |
12052 | pipe_config->dpll_hw_state.ctrl1, | |
12053 | pipe_config->dpll_hw_state.cfgcr1, | |
12054 | pipe_config->dpll_hw_state.cfgcr2); | |
12055 | } else if (HAS_DDI(dev)) { | |
1260f07e | 12056 | DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", |
415ff0f6 | 12057 | pipe_config->ddi_pll_sel, |
00490c22 ML |
12058 | pipe_config->dpll_hw_state.wrpll, |
12059 | pipe_config->dpll_hw_state.spll); | |
415ff0f6 TU |
12060 | } else { |
12061 | DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " | |
12062 | "fp0: 0x%x, fp1: 0x%x\n", | |
12063 | pipe_config->dpll_hw_state.dpll, | |
12064 | pipe_config->dpll_hw_state.dpll_md, | |
12065 | pipe_config->dpll_hw_state.fp0, | |
12066 | pipe_config->dpll_hw_state.fp1); | |
12067 | } | |
12068 | ||
6a60cd87 CK |
12069 | DRM_DEBUG_KMS("planes on this crtc\n"); |
12070 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
12071 | intel_plane = to_intel_plane(plane); | |
12072 | if (intel_plane->pipe != crtc->pipe) | |
12073 | continue; | |
12074 | ||
12075 | state = to_intel_plane_state(plane->state); | |
12076 | fb = state->base.fb; | |
12077 | if (!fb) { | |
12078 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d " | |
12079 | "disabled, scaler_id = %d\n", | |
12080 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12081 | plane->base.id, intel_plane->pipe, | |
12082 | (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1, | |
12083 | drm_plane_index(plane), state->scaler_id); | |
12084 | continue; | |
12085 | } | |
12086 | ||
12087 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled", | |
12088 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12089 | plane->base.id, intel_plane->pipe, | |
12090 | crtc->base.primary == plane ? 0 : intel_plane->plane + 1, | |
12091 | drm_plane_index(plane)); | |
12092 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x", | |
12093 | fb->base.id, fb->width, fb->height, fb->pixel_format); | |
12094 | DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n", | |
12095 | state->scaler_id, | |
12096 | state->src.x1 >> 16, state->src.y1 >> 16, | |
12097 | drm_rect_width(&state->src) >> 16, | |
12098 | drm_rect_height(&state->src) >> 16, | |
12099 | state->dst.x1, state->dst.y1, | |
12100 | drm_rect_width(&state->dst), drm_rect_height(&state->dst)); | |
12101 | } | |
c0b03411 DV |
12102 | } |
12103 | ||
5448a00d | 12104 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 12105 | { |
5448a00d | 12106 | struct drm_device *dev = state->dev; |
da3ced29 | 12107 | struct drm_connector *connector; |
00f0b378 VS |
12108 | unsigned int used_ports = 0; |
12109 | ||
12110 | /* | |
12111 | * Walk the connector list instead of the encoder | |
12112 | * list to detect the problem on ddi platforms | |
12113 | * where there's just one encoder per digital port. | |
12114 | */ | |
0bff4858 VS |
12115 | drm_for_each_connector(connector, dev) { |
12116 | struct drm_connector_state *connector_state; | |
12117 | struct intel_encoder *encoder; | |
12118 | ||
12119 | connector_state = drm_atomic_get_existing_connector_state(state, connector); | |
12120 | if (!connector_state) | |
12121 | connector_state = connector->state; | |
12122 | ||
5448a00d | 12123 | if (!connector_state->best_encoder) |
00f0b378 VS |
12124 | continue; |
12125 | ||
5448a00d ACO |
12126 | encoder = to_intel_encoder(connector_state->best_encoder); |
12127 | ||
12128 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
12129 | |
12130 | switch (encoder->type) { | |
12131 | unsigned int port_mask; | |
12132 | case INTEL_OUTPUT_UNKNOWN: | |
12133 | if (WARN_ON(!HAS_DDI(dev))) | |
12134 | break; | |
12135 | case INTEL_OUTPUT_DISPLAYPORT: | |
12136 | case INTEL_OUTPUT_HDMI: | |
12137 | case INTEL_OUTPUT_EDP: | |
12138 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
12139 | ||
12140 | /* the same port mustn't appear more than once */ | |
12141 | if (used_ports & port_mask) | |
12142 | return false; | |
12143 | ||
12144 | used_ports |= port_mask; | |
12145 | default: | |
12146 | break; | |
12147 | } | |
12148 | } | |
12149 | ||
12150 | return true; | |
12151 | } | |
12152 | ||
83a57153 ACO |
12153 | static void |
12154 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
12155 | { | |
12156 | struct drm_crtc_state tmp_state; | |
663a3640 | 12157 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 | 12158 | struct intel_dpll_hw_state dpll_hw_state; |
8106ddbd | 12159 | struct intel_shared_dpll *shared_dpll; |
8504c74c | 12160 | uint32_t ddi_pll_sel; |
c4e2d043 | 12161 | bool force_thru; |
83a57153 | 12162 | |
7546a384 ACO |
12163 | /* FIXME: before the switch to atomic started, a new pipe_config was |
12164 | * kzalloc'd. Code that depends on any field being zero should be | |
12165 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
12166 | * only fields that are know to not cause problems are preserved. */ | |
12167 | ||
83a57153 | 12168 | tmp_state = crtc_state->base; |
663a3640 | 12169 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
12170 | shared_dpll = crtc_state->shared_dpll; |
12171 | dpll_hw_state = crtc_state->dpll_hw_state; | |
8504c74c | 12172 | ddi_pll_sel = crtc_state->ddi_pll_sel; |
c4e2d043 | 12173 | force_thru = crtc_state->pch_pfit.force_thru; |
4978cc93 | 12174 | |
83a57153 | 12175 | memset(crtc_state, 0, sizeof *crtc_state); |
4978cc93 | 12176 | |
83a57153 | 12177 | crtc_state->base = tmp_state; |
663a3640 | 12178 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
12179 | crtc_state->shared_dpll = shared_dpll; |
12180 | crtc_state->dpll_hw_state = dpll_hw_state; | |
8504c74c | 12181 | crtc_state->ddi_pll_sel = ddi_pll_sel; |
c4e2d043 | 12182 | crtc_state->pch_pfit.force_thru = force_thru; |
83a57153 ACO |
12183 | } |
12184 | ||
548ee15b | 12185 | static int |
b8cecdf5 | 12186 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 12187 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 12188 | { |
b359283a | 12189 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 12190 | struct intel_encoder *encoder; |
da3ced29 | 12191 | struct drm_connector *connector; |
0b901879 | 12192 | struct drm_connector_state *connector_state; |
d328c9d7 | 12193 | int base_bpp, ret = -EINVAL; |
0b901879 | 12194 | int i; |
e29c22c0 | 12195 | bool retry = true; |
ee7b9f93 | 12196 | |
83a57153 | 12197 | clear_intel_crtc_state(pipe_config); |
7758a113 | 12198 | |
e143a21c DV |
12199 | pipe_config->cpu_transcoder = |
12200 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 12201 | |
2960bc9c ID |
12202 | /* |
12203 | * Sanitize sync polarity flags based on requested ones. If neither | |
12204 | * positive or negative polarity is requested, treat this as meaning | |
12205 | * negative polarity. | |
12206 | */ | |
2d112de7 | 12207 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12208 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 12209 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 12210 | |
2d112de7 | 12211 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12212 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 12213 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 12214 | |
d328c9d7 DV |
12215 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
12216 | pipe_config); | |
12217 | if (base_bpp < 0) | |
4e53c2e0 DV |
12218 | goto fail; |
12219 | ||
e41a56be VS |
12220 | /* |
12221 | * Determine the real pipe dimensions. Note that stereo modes can | |
12222 | * increase the actual pipe size due to the frame doubling and | |
12223 | * insertion of additional space for blanks between the frame. This | |
12224 | * is stored in the crtc timings. We use the requested mode to do this | |
12225 | * computation to clearly distinguish it from the adjusted mode, which | |
12226 | * can be changed by the connectors in the below retry loop. | |
12227 | */ | |
2d112de7 | 12228 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
12229 | &pipe_config->pipe_src_w, |
12230 | &pipe_config->pipe_src_h); | |
e41a56be | 12231 | |
e29c22c0 | 12232 | encoder_retry: |
ef1b460d | 12233 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 12234 | pipe_config->port_clock = 0; |
ef1b460d | 12235 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 12236 | |
135c81b8 | 12237 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
12238 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
12239 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 12240 | |
7758a113 DV |
12241 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
12242 | * adjust it according to limitations or connector properties, and also | |
12243 | * a chance to reject the mode entirely. | |
47f1c6c9 | 12244 | */ |
da3ced29 | 12245 | for_each_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 12246 | if (connector_state->crtc != crtc) |
7758a113 | 12247 | continue; |
7ae89233 | 12248 | |
0b901879 ACO |
12249 | encoder = to_intel_encoder(connector_state->best_encoder); |
12250 | ||
efea6e8e DV |
12251 | if (!(encoder->compute_config(encoder, pipe_config))) { |
12252 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
12253 | goto fail; |
12254 | } | |
ee7b9f93 | 12255 | } |
47f1c6c9 | 12256 | |
ff9a6750 DV |
12257 | /* Set default port clock if not overwritten by the encoder. Needs to be |
12258 | * done afterwards in case the encoder adjusts the mode. */ | |
12259 | if (!pipe_config->port_clock) | |
2d112de7 | 12260 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 12261 | * pipe_config->pixel_multiplier; |
ff9a6750 | 12262 | |
a43f6e0f | 12263 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 12264 | if (ret < 0) { |
7758a113 DV |
12265 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
12266 | goto fail; | |
ee7b9f93 | 12267 | } |
e29c22c0 DV |
12268 | |
12269 | if (ret == RETRY) { | |
12270 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
12271 | ret = -EINVAL; | |
12272 | goto fail; | |
12273 | } | |
12274 | ||
12275 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
12276 | retry = false; | |
12277 | goto encoder_retry; | |
12278 | } | |
12279 | ||
e8fa4270 DV |
12280 | /* Dithering seems to not pass-through bits correctly when it should, so |
12281 | * only enable it on 6bpc panels. */ | |
12282 | pipe_config->dither = pipe_config->pipe_bpp == 6*3; | |
62f0ace5 | 12283 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 12284 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 12285 | |
7758a113 | 12286 | fail: |
548ee15b | 12287 | return ret; |
ee7b9f93 | 12288 | } |
47f1c6c9 | 12289 | |
ea9d758d | 12290 | static void |
4740b0f2 | 12291 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 12292 | { |
0a9ab303 ACO |
12293 | struct drm_crtc *crtc; |
12294 | struct drm_crtc_state *crtc_state; | |
8a75d157 | 12295 | int i; |
ea9d758d | 12296 | |
7668851f | 12297 | /* Double check state. */ |
8a75d157 | 12298 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
3cb480bc | 12299 | to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); |
fc467a22 ML |
12300 | |
12301 | /* Update hwmode for vblank functions */ | |
12302 | if (crtc->state->active) | |
12303 | crtc->hwmode = crtc->state->adjusted_mode; | |
12304 | else | |
12305 | crtc->hwmode.crtc_clock = 0; | |
61067a5e ML |
12306 | |
12307 | /* | |
12308 | * Update legacy state to satisfy fbc code. This can | |
12309 | * be removed when fbc uses the atomic state. | |
12310 | */ | |
12311 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
12312 | struct drm_plane_state *plane_state = crtc->primary->state; | |
12313 | ||
12314 | crtc->primary->fb = plane_state->fb; | |
12315 | crtc->x = plane_state->src_x >> 16; | |
12316 | crtc->y = plane_state->src_y >> 16; | |
12317 | } | |
ea9d758d | 12318 | } |
ea9d758d DV |
12319 | } |
12320 | ||
3bd26263 | 12321 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 12322 | { |
3bd26263 | 12323 | int diff; |
f1f644dc JB |
12324 | |
12325 | if (clock1 == clock2) | |
12326 | return true; | |
12327 | ||
12328 | if (!clock1 || !clock2) | |
12329 | return false; | |
12330 | ||
12331 | diff = abs(clock1 - clock2); | |
12332 | ||
12333 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
12334 | return true; | |
12335 | ||
12336 | return false; | |
12337 | } | |
12338 | ||
25c5b266 DV |
12339 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
12340 | list_for_each_entry((intel_crtc), \ | |
12341 | &(dev)->mode_config.crtc_list, \ | |
12342 | base.head) \ | |
95150bdf | 12343 | for_each_if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 12344 | |
cfb23ed6 ML |
12345 | static bool |
12346 | intel_compare_m_n(unsigned int m, unsigned int n, | |
12347 | unsigned int m2, unsigned int n2, | |
12348 | bool exact) | |
12349 | { | |
12350 | if (m == m2 && n == n2) | |
12351 | return true; | |
12352 | ||
12353 | if (exact || !m || !n || !m2 || !n2) | |
12354 | return false; | |
12355 | ||
12356 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
12357 | ||
31d10b57 ML |
12358 | if (n > n2) { |
12359 | while (n > n2) { | |
cfb23ed6 ML |
12360 | m2 <<= 1; |
12361 | n2 <<= 1; | |
12362 | } | |
31d10b57 ML |
12363 | } else if (n < n2) { |
12364 | while (n < n2) { | |
cfb23ed6 ML |
12365 | m <<= 1; |
12366 | n <<= 1; | |
12367 | } | |
12368 | } | |
12369 | ||
31d10b57 ML |
12370 | if (n != n2) |
12371 | return false; | |
12372 | ||
12373 | return intel_fuzzy_clock_check(m, m2); | |
cfb23ed6 ML |
12374 | } |
12375 | ||
12376 | static bool | |
12377 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
12378 | struct intel_link_m_n *m2_n2, | |
12379 | bool adjust) | |
12380 | { | |
12381 | if (m_n->tu == m2_n2->tu && | |
12382 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
12383 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
12384 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
12385 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
12386 | if (adjust) | |
12387 | *m2_n2 = *m_n; | |
12388 | ||
12389 | return true; | |
12390 | } | |
12391 | ||
12392 | return false; | |
12393 | } | |
12394 | ||
0e8ffe1b | 12395 | static bool |
2fa2fe9a | 12396 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b | 12397 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
12398 | struct intel_crtc_state *pipe_config, |
12399 | bool adjust) | |
0e8ffe1b | 12400 | { |
cfb23ed6 ML |
12401 | bool ret = true; |
12402 | ||
12403 | #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \ | |
12404 | do { \ | |
12405 | if (!adjust) \ | |
12406 | DRM_ERROR(fmt, ##__VA_ARGS__); \ | |
12407 | else \ | |
12408 | DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \ | |
12409 | } while (0) | |
12410 | ||
66e985c0 DV |
12411 | #define PIPE_CONF_CHECK_X(name) \ |
12412 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12413 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
66e985c0 DV |
12414 | "(expected 0x%08x, found 0x%08x)\n", \ |
12415 | current_config->name, \ | |
12416 | pipe_config->name); \ | |
cfb23ed6 | 12417 | ret = false; \ |
66e985c0 DV |
12418 | } |
12419 | ||
08a24034 DV |
12420 | #define PIPE_CONF_CHECK_I(name) \ |
12421 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12422 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
08a24034 DV |
12423 | "(expected %i, found %i)\n", \ |
12424 | current_config->name, \ | |
12425 | pipe_config->name); \ | |
cfb23ed6 ML |
12426 | ret = false; \ |
12427 | } | |
12428 | ||
8106ddbd ACO |
12429 | #define PIPE_CONF_CHECK_P(name) \ |
12430 | if (current_config->name != pipe_config->name) { \ | |
12431 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12432 | "(expected %p, found %p)\n", \ | |
12433 | current_config->name, \ | |
12434 | pipe_config->name); \ | |
12435 | ret = false; \ | |
12436 | } | |
12437 | ||
cfb23ed6 ML |
12438 | #define PIPE_CONF_CHECK_M_N(name) \ |
12439 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12440 | &pipe_config->name,\ | |
12441 | adjust)) { \ | |
12442 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12443 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12444 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12445 | current_config->name.tu, \ | |
12446 | current_config->name.gmch_m, \ | |
12447 | current_config->name.gmch_n, \ | |
12448 | current_config->name.link_m, \ | |
12449 | current_config->name.link_n, \ | |
12450 | pipe_config->name.tu, \ | |
12451 | pipe_config->name.gmch_m, \ | |
12452 | pipe_config->name.gmch_n, \ | |
12453 | pipe_config->name.link_m, \ | |
12454 | pipe_config->name.link_n); \ | |
12455 | ret = false; \ | |
12456 | } | |
12457 | ||
12458 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ | |
12459 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12460 | &pipe_config->name, adjust) && \ | |
12461 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
12462 | &pipe_config->name, adjust)) { \ | |
12463 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12464 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12465 | "or tu %i gmch %i/%i link %i/%i, " \ | |
12466 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12467 | current_config->name.tu, \ | |
12468 | current_config->name.gmch_m, \ | |
12469 | current_config->name.gmch_n, \ | |
12470 | current_config->name.link_m, \ | |
12471 | current_config->name.link_n, \ | |
12472 | current_config->alt_name.tu, \ | |
12473 | current_config->alt_name.gmch_m, \ | |
12474 | current_config->alt_name.gmch_n, \ | |
12475 | current_config->alt_name.link_m, \ | |
12476 | current_config->alt_name.link_n, \ | |
12477 | pipe_config->name.tu, \ | |
12478 | pipe_config->name.gmch_m, \ | |
12479 | pipe_config->name.gmch_n, \ | |
12480 | pipe_config->name.link_m, \ | |
12481 | pipe_config->name.link_n); \ | |
12482 | ret = false; \ | |
88adfff1 DV |
12483 | } |
12484 | ||
b95af8be VK |
12485 | /* This is required for BDW+ where there is only one set of registers for |
12486 | * switching between high and low RR. | |
12487 | * This macro can be used whenever a comparison has to be made between one | |
12488 | * hw state and multiple sw state variables. | |
12489 | */ | |
12490 | #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ | |
12491 | if ((current_config->name != pipe_config->name) && \ | |
12492 | (current_config->alt_name != pipe_config->name)) { \ | |
cfb23ed6 | 12493 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
b95af8be VK |
12494 | "(expected %i or %i, found %i)\n", \ |
12495 | current_config->name, \ | |
12496 | current_config->alt_name, \ | |
12497 | pipe_config->name); \ | |
cfb23ed6 | 12498 | ret = false; \ |
b95af8be VK |
12499 | } |
12500 | ||
1bd1bd80 DV |
12501 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
12502 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
cfb23ed6 | 12503 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
12504 | "(expected %i, found %i)\n", \ |
12505 | current_config->name & (mask), \ | |
12506 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 12507 | ret = false; \ |
1bd1bd80 DV |
12508 | } |
12509 | ||
5e550656 VS |
12510 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
12511 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
cfb23ed6 | 12512 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
5e550656 VS |
12513 | "(expected %i, found %i)\n", \ |
12514 | current_config->name, \ | |
12515 | pipe_config->name); \ | |
cfb23ed6 | 12516 | ret = false; \ |
5e550656 VS |
12517 | } |
12518 | ||
bb760063 DV |
12519 | #define PIPE_CONF_QUIRK(quirk) \ |
12520 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
12521 | ||
eccb140b DV |
12522 | PIPE_CONF_CHECK_I(cpu_transcoder); |
12523 | ||
08a24034 DV |
12524 | PIPE_CONF_CHECK_I(has_pch_encoder); |
12525 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 12526 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 12527 | |
eb14cb74 | 12528 | PIPE_CONF_CHECK_I(has_dp_encoder); |
90a6b7b0 | 12529 | PIPE_CONF_CHECK_I(lane_count); |
b95af8be VK |
12530 | |
12531 | if (INTEL_INFO(dev)->gen < 8) { | |
cfb23ed6 ML |
12532 | PIPE_CONF_CHECK_M_N(dp_m_n); |
12533 | ||
cfb23ed6 ML |
12534 | if (current_config->has_drrs) |
12535 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
12536 | } else | |
12537 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 12538 | |
a65347ba JN |
12539 | PIPE_CONF_CHECK_I(has_dsi_encoder); |
12540 | ||
2d112de7 ACO |
12541 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
12542 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
12543 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
12544 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
12545 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
12546 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 12547 | |
2d112de7 ACO |
12548 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
12549 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
12550 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
12551 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
12552 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
12553 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 12554 | |
c93f54cf | 12555 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 12556 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 | 12557 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
666a4537 | 12558 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
b5a9fa09 | 12559 | PIPE_CONF_CHECK_I(limited_color_range); |
e43823ec | 12560 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 12561 | |
9ed109a7 DV |
12562 | PIPE_CONF_CHECK_I(has_audio); |
12563 | ||
2d112de7 | 12564 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
12565 | DRM_MODE_FLAG_INTERLACE); |
12566 | ||
bb760063 | 12567 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 12568 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12569 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 12570 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12571 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 12572 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12573 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 12574 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
12575 | DRM_MODE_FLAG_NVSYNC); |
12576 | } | |
045ac3b5 | 12577 | |
333b8ca8 | 12578 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a DV |
12579 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
12580 | if (INTEL_INFO(dev)->gen < 4) | |
12581 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
333b8ca8 | 12582 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 12583 | |
bfd16b2a ML |
12584 | if (!adjust) { |
12585 | PIPE_CONF_CHECK_I(pipe_src_w); | |
12586 | PIPE_CONF_CHECK_I(pipe_src_h); | |
12587 | ||
12588 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
12589 | if (current_config->pch_pfit.enabled) { | |
12590 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
12591 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
12592 | } | |
2fa2fe9a | 12593 | |
7aefe2b5 ML |
12594 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
12595 | } | |
a1b2278e | 12596 | |
e59150dc JB |
12597 | /* BDW+ don't expose a synchronous way to read the state */ |
12598 | if (IS_HASWELL(dev)) | |
12599 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 12600 | |
282740f7 VS |
12601 | PIPE_CONF_CHECK_I(double_wide); |
12602 | ||
26804afd DV |
12603 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
12604 | ||
8106ddbd | 12605 | PIPE_CONF_CHECK_P(shared_dpll); |
66e985c0 | 12606 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 12607 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
12608 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
12609 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 12610 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
00490c22 | 12611 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
3f4cd19f DL |
12612 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
12613 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
12614 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 12615 | |
42571aef VS |
12616 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
12617 | PIPE_CONF_CHECK_I(pipe_bpp); | |
12618 | ||
2d112de7 | 12619 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 12620 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 12621 | |
66e985c0 | 12622 | #undef PIPE_CONF_CHECK_X |
08a24034 | 12623 | #undef PIPE_CONF_CHECK_I |
8106ddbd | 12624 | #undef PIPE_CONF_CHECK_P |
b95af8be | 12625 | #undef PIPE_CONF_CHECK_I_ALT |
1bd1bd80 | 12626 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 12627 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 12628 | #undef PIPE_CONF_QUIRK |
cfb23ed6 | 12629 | #undef INTEL_ERR_OR_DBG_KMS |
88adfff1 | 12630 | |
cfb23ed6 | 12631 | return ret; |
0e8ffe1b DV |
12632 | } |
12633 | ||
e3b247da VS |
12634 | static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, |
12635 | const struct intel_crtc_state *pipe_config) | |
12636 | { | |
12637 | if (pipe_config->has_pch_encoder) { | |
21a727b3 | 12638 | int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
e3b247da VS |
12639 | &pipe_config->fdi_m_n); |
12640 | int dotclock = pipe_config->base.adjusted_mode.crtc_clock; | |
12641 | ||
12642 | /* | |
12643 | * FDI already provided one idea for the dotclock. | |
12644 | * Yell if the encoder disagrees. | |
12645 | */ | |
12646 | WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock), | |
12647 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", | |
12648 | fdi_dotclock, dotclock); | |
12649 | } | |
12650 | } | |
12651 | ||
08db6652 DL |
12652 | static void check_wm_state(struct drm_device *dev) |
12653 | { | |
12654 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12655 | struct skl_ddb_allocation hw_ddb, *sw_ddb; | |
12656 | struct intel_crtc *intel_crtc; | |
12657 | int plane; | |
12658 | ||
12659 | if (INTEL_INFO(dev)->gen < 9) | |
12660 | return; | |
12661 | ||
12662 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
12663 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
12664 | ||
12665 | for_each_intel_crtc(dev, intel_crtc) { | |
12666 | struct skl_ddb_entry *hw_entry, *sw_entry; | |
12667 | const enum pipe pipe = intel_crtc->pipe; | |
12668 | ||
12669 | if (!intel_crtc->active) | |
12670 | continue; | |
12671 | ||
12672 | /* planes */ | |
dd740780 | 12673 | for_each_plane(dev_priv, pipe, plane) { |
08db6652 DL |
12674 | hw_entry = &hw_ddb.plane[pipe][plane]; |
12675 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
12676 | ||
12677 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12678 | continue; | |
12679 | ||
12680 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " | |
12681 | "(expected (%u,%u), found (%u,%u))\n", | |
12682 | pipe_name(pipe), plane + 1, | |
12683 | sw_entry->start, sw_entry->end, | |
12684 | hw_entry->start, hw_entry->end); | |
12685 | } | |
12686 | ||
12687 | /* cursor */ | |
4969d33e MR |
12688 | hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; |
12689 | sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; | |
08db6652 DL |
12690 | |
12691 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12692 | continue; | |
12693 | ||
12694 | DRM_ERROR("mismatch in DDB state pipe %c cursor " | |
12695 | "(expected (%u,%u), found (%u,%u))\n", | |
12696 | pipe_name(pipe), | |
12697 | sw_entry->start, sw_entry->end, | |
12698 | hw_entry->start, hw_entry->end); | |
12699 | } | |
12700 | } | |
12701 | ||
91d1b4bd | 12702 | static void |
35dd3c64 ML |
12703 | check_connector_state(struct drm_device *dev, |
12704 | struct drm_atomic_state *old_state) | |
8af6cf88 | 12705 | { |
35dd3c64 ML |
12706 | struct drm_connector_state *old_conn_state; |
12707 | struct drm_connector *connector; | |
12708 | int i; | |
8af6cf88 | 12709 | |
35dd3c64 ML |
12710 | for_each_connector_in_state(old_state, connector, old_conn_state, i) { |
12711 | struct drm_encoder *encoder = connector->encoder; | |
12712 | struct drm_connector_state *state = connector->state; | |
ad3c558f | 12713 | |
8af6cf88 DV |
12714 | /* This also checks the encoder/connector hw state with the |
12715 | * ->get_hw_state callbacks. */ | |
35dd3c64 | 12716 | intel_connector_check_state(to_intel_connector(connector)); |
8af6cf88 | 12717 | |
ad3c558f | 12718 | I915_STATE_WARN(state->best_encoder != encoder, |
35dd3c64 | 12719 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 12720 | } |
91d1b4bd DV |
12721 | } |
12722 | ||
12723 | static void | |
12724 | check_encoder_state(struct drm_device *dev) | |
12725 | { | |
12726 | struct intel_encoder *encoder; | |
12727 | struct intel_connector *connector; | |
8af6cf88 | 12728 | |
b2784e15 | 12729 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 | 12730 | bool enabled = false; |
4d20cd86 | 12731 | enum pipe pipe; |
8af6cf88 DV |
12732 | |
12733 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
12734 | encoder->base.base.id, | |
8e329a03 | 12735 | encoder->base.name); |
8af6cf88 | 12736 | |
3a3371ff | 12737 | for_each_intel_connector(dev, connector) { |
4d20cd86 | 12738 | if (connector->base.state->best_encoder != &encoder->base) |
8af6cf88 DV |
12739 | continue; |
12740 | enabled = true; | |
ad3c558f ML |
12741 | |
12742 | I915_STATE_WARN(connector->base.state->crtc != | |
12743 | encoder->base.crtc, | |
12744 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 12745 | } |
0e32b39c | 12746 | |
e2c719b7 | 12747 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
12748 | "encoder's enabled state mismatch " |
12749 | "(expected %i, found %i)\n", | |
12750 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
12751 | |
12752 | if (!encoder->base.crtc) { | |
4d20cd86 | 12753 | bool active; |
7c60d198 | 12754 | |
4d20cd86 ML |
12755 | active = encoder->get_hw_state(encoder, &pipe); |
12756 | I915_STATE_WARN(active, | |
12757 | "encoder detached but still enabled on pipe %c.\n", | |
12758 | pipe_name(pipe)); | |
7c60d198 | 12759 | } |
8af6cf88 | 12760 | } |
91d1b4bd DV |
12761 | } |
12762 | ||
12763 | static void | |
4d20cd86 | 12764 | check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state) |
91d1b4bd | 12765 | { |
fbee40df | 12766 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd | 12767 | struct intel_encoder *encoder; |
4d20cd86 ML |
12768 | struct drm_crtc_state *old_crtc_state; |
12769 | struct drm_crtc *crtc; | |
12770 | int i; | |
8af6cf88 | 12771 | |
4d20cd86 ML |
12772 | for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) { |
12773 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12774 | struct intel_crtc_state *pipe_config, *sw_config; | |
7b89b8de | 12775 | bool active; |
8af6cf88 | 12776 | |
bfd16b2a ML |
12777 | if (!needs_modeset(crtc->state) && |
12778 | !to_intel_crtc_state(crtc->state)->update_pipe) | |
4d20cd86 | 12779 | continue; |
045ac3b5 | 12780 | |
4d20cd86 ML |
12781 | __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state); |
12782 | pipe_config = to_intel_crtc_state(old_crtc_state); | |
12783 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
12784 | pipe_config->base.crtc = crtc; | |
12785 | pipe_config->base.state = old_state; | |
8af6cf88 | 12786 | |
4d20cd86 ML |
12787 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
12788 | crtc->base.id); | |
8af6cf88 | 12789 | |
4d20cd86 ML |
12790 | active = dev_priv->display.get_pipe_config(intel_crtc, |
12791 | pipe_config); | |
d62cf62a | 12792 | |
b6b5d049 | 12793 | /* hw state is inconsistent with the pipe quirk */ |
4d20cd86 ML |
12794 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
12795 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
12796 | active = crtc->state->active; | |
6c49f241 | 12797 | |
4d20cd86 | 12798 | I915_STATE_WARN(crtc->state->active != active, |
0e8ffe1b | 12799 | "crtc active state doesn't match with hw state " |
4d20cd86 | 12800 | "(expected %i, found %i)\n", crtc->state->active, active); |
0e8ffe1b | 12801 | |
4d20cd86 | 12802 | I915_STATE_WARN(intel_crtc->active != crtc->state->active, |
53d9f4e9 | 12803 | "transitional active state does not match atomic hw state " |
4d20cd86 ML |
12804 | "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active); |
12805 | ||
12806 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
12807 | enum pipe pipe; | |
12808 | ||
12809 | active = encoder->get_hw_state(encoder, &pipe); | |
12810 | I915_STATE_WARN(active != crtc->state->active, | |
12811 | "[ENCODER:%i] active %i with crtc active %i\n", | |
12812 | encoder->base.base.id, active, crtc->state->active); | |
12813 | ||
12814 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, | |
12815 | "Encoder connected to wrong pipe %c\n", | |
12816 | pipe_name(pipe)); | |
12817 | ||
12818 | if (active) | |
12819 | encoder->get_config(encoder, pipe_config); | |
12820 | } | |
53d9f4e9 | 12821 | |
4d20cd86 | 12822 | if (!crtc->state->active) |
cfb23ed6 ML |
12823 | continue; |
12824 | ||
e3b247da VS |
12825 | intel_pipe_config_sanity_check(dev_priv, pipe_config); |
12826 | ||
4d20cd86 ML |
12827 | sw_config = to_intel_crtc_state(crtc->state); |
12828 | if (!intel_pipe_config_compare(dev, sw_config, | |
12829 | pipe_config, false)) { | |
e2c719b7 | 12830 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); |
4d20cd86 | 12831 | intel_dump_pipe_config(intel_crtc, pipe_config, |
c0b03411 | 12832 | "[hw state]"); |
4d20cd86 | 12833 | intel_dump_pipe_config(intel_crtc, sw_config, |
c0b03411 DV |
12834 | "[sw state]"); |
12835 | } | |
8af6cf88 DV |
12836 | } |
12837 | } | |
12838 | ||
91d1b4bd DV |
12839 | static void |
12840 | check_shared_dpll_state(struct drm_device *dev) | |
12841 | { | |
fbee40df | 12842 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
12843 | struct intel_crtc *crtc; |
12844 | struct intel_dpll_hw_state dpll_hw_state; | |
12845 | int i; | |
5358901f DV |
12846 | |
12847 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
8106ddbd ACO |
12848 | struct intel_shared_dpll *pll = |
12849 | intel_get_shared_dpll_by_id(dev_priv, i); | |
2dd66ebd | 12850 | unsigned enabled_crtcs = 0, active_crtcs = 0; |
5358901f DV |
12851 | bool active; |
12852 | ||
12853 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
12854 | ||
12855 | DRM_DEBUG_KMS("%s\n", pll->name); | |
12856 | ||
2edd6443 | 12857 | active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state); |
5358901f | 12858 | |
2dd66ebd ML |
12859 | I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask, |
12860 | "more active pll users than references: %x vs %x\n", | |
12861 | pll->active_mask, pll->config.crtc_mask); | |
9d16da65 ACO |
12862 | |
12863 | if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) { | |
2dd66ebd ML |
12864 | I915_STATE_WARN(!pll->on && pll->active_mask, |
12865 | "pll in active use but not on in sw tracking\n"); | |
12866 | I915_STATE_WARN(pll->on && !pll->active_mask, | |
12867 | "pll is on but not used by any active crtc\n"); | |
9d16da65 ACO |
12868 | I915_STATE_WARN(pll->on != active, |
12869 | "pll on state mismatch (expected %i, found %i)\n", | |
12870 | pll->on, active); | |
12871 | } | |
5358901f | 12872 | |
d3fcc808 | 12873 | for_each_intel_crtc(dev, crtc) { |
8106ddbd | 12874 | if (crtc->base.state->enable && crtc->config->shared_dpll == pll) |
2dd66ebd ML |
12875 | enabled_crtcs |= 1 << drm_crtc_index(&crtc->base); |
12876 | if (crtc->base.state->active && crtc->config->shared_dpll == pll) | |
12877 | active_crtcs |= 1 << drm_crtc_index(&crtc->base); | |
5358901f | 12878 | } |
2dd66ebd ML |
12879 | |
12880 | I915_STATE_WARN(pll->active_mask != active_crtcs, | |
12881 | "pll active crtcs mismatch (expected %x, found %x)\n", | |
12882 | pll->active_mask, active_crtcs); | |
12883 | I915_STATE_WARN(pll->config.crtc_mask != enabled_crtcs, | |
12884 | "pll enabled crtcs mismatch (expected %x, found %x)\n", | |
12885 | pll->config.crtc_mask, enabled_crtcs); | |
66e985c0 | 12886 | |
e2c719b7 | 12887 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state, |
66e985c0 DV |
12888 | sizeof(dpll_hw_state)), |
12889 | "pll hw state mismatch\n"); | |
5358901f | 12890 | } |
8af6cf88 DV |
12891 | } |
12892 | ||
ee165b1a ML |
12893 | static void |
12894 | intel_modeset_check_state(struct drm_device *dev, | |
12895 | struct drm_atomic_state *old_state) | |
91d1b4bd | 12896 | { |
08db6652 | 12897 | check_wm_state(dev); |
35dd3c64 | 12898 | check_connector_state(dev, old_state); |
91d1b4bd | 12899 | check_encoder_state(dev); |
4d20cd86 | 12900 | check_crtc_state(dev, old_state); |
91d1b4bd DV |
12901 | check_shared_dpll_state(dev); |
12902 | } | |
12903 | ||
80715b2f VS |
12904 | static void update_scanline_offset(struct intel_crtc *crtc) |
12905 | { | |
12906 | struct drm_device *dev = crtc->base.dev; | |
12907 | ||
12908 | /* | |
12909 | * The scanline counter increments at the leading edge of hsync. | |
12910 | * | |
12911 | * On most platforms it starts counting from vtotal-1 on the | |
12912 | * first active line. That means the scanline counter value is | |
12913 | * always one less than what we would expect. Ie. just after | |
12914 | * start of vblank, which also occurs at start of hsync (on the | |
12915 | * last active line), the scanline counter will read vblank_start-1. | |
12916 | * | |
12917 | * On gen2 the scanline counter starts counting from 1 instead | |
12918 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
12919 | * to keep the value positive), instead of adding one. | |
12920 | * | |
12921 | * On HSW+ the behaviour of the scanline counter depends on the output | |
12922 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
12923 | * there's an extra 1 line difference. So we need to add two instead of | |
12924 | * one to the value. | |
12925 | */ | |
12926 | if (IS_GEN2(dev)) { | |
124abe07 | 12927 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
12928 | int vtotal; |
12929 | ||
124abe07 VS |
12930 | vtotal = adjusted_mode->crtc_vtotal; |
12931 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
12932 | vtotal /= 2; |
12933 | ||
12934 | crtc->scanline_offset = vtotal - 1; | |
12935 | } else if (HAS_DDI(dev) && | |
409ee761 | 12936 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
12937 | crtc->scanline_offset = 2; |
12938 | } else | |
12939 | crtc->scanline_offset = 1; | |
12940 | } | |
12941 | ||
ad421372 | 12942 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 12943 | { |
225da59b | 12944 | struct drm_device *dev = state->dev; |
ed6739ef | 12945 | struct drm_i915_private *dev_priv = to_i915(dev); |
ad421372 | 12946 | struct intel_shared_dpll_config *shared_dpll = NULL; |
0a9ab303 ACO |
12947 | struct drm_crtc *crtc; |
12948 | struct drm_crtc_state *crtc_state; | |
0a9ab303 | 12949 | int i; |
ed6739ef ACO |
12950 | |
12951 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 12952 | return; |
ed6739ef | 12953 | |
0a9ab303 | 12954 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
fb1a38a9 | 12955 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8106ddbd ACO |
12956 | struct intel_shared_dpll *old_dpll = |
12957 | to_intel_crtc_state(crtc->state)->shared_dpll; | |
0a9ab303 | 12958 | |
fb1a38a9 | 12959 | if (!needs_modeset(crtc_state)) |
225da59b ACO |
12960 | continue; |
12961 | ||
8106ddbd | 12962 | to_intel_crtc_state(crtc_state)->shared_dpll = NULL; |
fb1a38a9 | 12963 | |
8106ddbd | 12964 | if (!old_dpll) |
fb1a38a9 | 12965 | continue; |
0a9ab303 | 12966 | |
ad421372 ML |
12967 | if (!shared_dpll) |
12968 | shared_dpll = intel_atomic_get_shared_dpll_state(state); | |
ed6739ef | 12969 | |
8106ddbd | 12970 | intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc); |
ad421372 | 12971 | } |
ed6739ef ACO |
12972 | } |
12973 | ||
99d736a2 ML |
12974 | /* |
12975 | * This implements the workaround described in the "notes" section of the mode | |
12976 | * set sequence documentation. When going from no pipes or single pipe to | |
12977 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
12978 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
12979 | */ | |
12980 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
12981 | { | |
12982 | struct drm_crtc_state *crtc_state; | |
12983 | struct intel_crtc *intel_crtc; | |
12984 | struct drm_crtc *crtc; | |
12985 | struct intel_crtc_state *first_crtc_state = NULL; | |
12986 | struct intel_crtc_state *other_crtc_state = NULL; | |
12987 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
12988 | int i; | |
12989 | ||
12990 | /* look at all crtc's that are going to be enabled in during modeset */ | |
12991 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
12992 | intel_crtc = to_intel_crtc(crtc); | |
12993 | ||
12994 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
12995 | continue; | |
12996 | ||
12997 | if (first_crtc_state) { | |
12998 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
12999 | break; | |
13000 | } else { | |
13001 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
13002 | first_pipe = intel_crtc->pipe; | |
13003 | } | |
13004 | } | |
13005 | ||
13006 | /* No workaround needed? */ | |
13007 | if (!first_crtc_state) | |
13008 | return 0; | |
13009 | ||
13010 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
13011 | for_each_intel_crtc(state->dev, intel_crtc) { | |
13012 | struct intel_crtc_state *pipe_config; | |
13013 | ||
13014 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
13015 | if (IS_ERR(pipe_config)) | |
13016 | return PTR_ERR(pipe_config); | |
13017 | ||
13018 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
13019 | ||
13020 | if (!pipe_config->base.active || | |
13021 | needs_modeset(&pipe_config->base)) | |
13022 | continue; | |
13023 | ||
13024 | /* 2 or more enabled crtcs means no need for w/a */ | |
13025 | if (enabled_pipe != INVALID_PIPE) | |
13026 | return 0; | |
13027 | ||
13028 | enabled_pipe = intel_crtc->pipe; | |
13029 | } | |
13030 | ||
13031 | if (enabled_pipe != INVALID_PIPE) | |
13032 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
13033 | else if (other_crtc_state) | |
13034 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
13035 | ||
13036 | return 0; | |
13037 | } | |
13038 | ||
27c329ed ML |
13039 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
13040 | { | |
13041 | struct drm_crtc *crtc; | |
13042 | struct drm_crtc_state *crtc_state; | |
13043 | int ret = 0; | |
13044 | ||
13045 | /* add all active pipes to the state */ | |
13046 | for_each_crtc(state->dev, crtc) { | |
13047 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13048 | if (IS_ERR(crtc_state)) | |
13049 | return PTR_ERR(crtc_state); | |
13050 | ||
13051 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
13052 | continue; | |
13053 | ||
13054 | crtc_state->mode_changed = true; | |
13055 | ||
13056 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
13057 | if (ret) | |
13058 | break; | |
13059 | ||
13060 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13061 | if (ret) | |
13062 | break; | |
13063 | } | |
13064 | ||
13065 | return ret; | |
13066 | } | |
13067 | ||
c347a676 | 13068 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd | 13069 | { |
565602d7 ML |
13070 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
13071 | struct drm_i915_private *dev_priv = state->dev->dev_private; | |
13072 | struct drm_crtc *crtc; | |
13073 | struct drm_crtc_state *crtc_state; | |
13074 | int ret = 0, i; | |
054518dd | 13075 | |
b359283a ML |
13076 | if (!check_digital_port_conflicts(state)) { |
13077 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
13078 | return -EINVAL; | |
13079 | } | |
13080 | ||
565602d7 ML |
13081 | intel_state->modeset = true; |
13082 | intel_state->active_crtcs = dev_priv->active_crtcs; | |
13083 | ||
13084 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13085 | if (crtc_state->active) | |
13086 | intel_state->active_crtcs |= 1 << i; | |
13087 | else | |
13088 | intel_state->active_crtcs &= ~(1 << i); | |
13089 | } | |
13090 | ||
054518dd ACO |
13091 | /* |
13092 | * See if the config requires any additional preparation, e.g. | |
13093 | * to adjust global state with pipes off. We need to do this | |
13094 | * here so we can get the modeset_pipe updated config for the new | |
13095 | * mode set on this crtc. For other crtcs we need to use the | |
13096 | * adjusted_mode bits in the crtc directly. | |
13097 | */ | |
27c329ed | 13098 | if (dev_priv->display.modeset_calc_cdclk) { |
27c329ed ML |
13099 | ret = dev_priv->display.modeset_calc_cdclk(state); |
13100 | ||
1a617b77 | 13101 | if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq) |
27c329ed ML |
13102 | ret = intel_modeset_all_pipes(state); |
13103 | ||
13104 | if (ret < 0) | |
054518dd | 13105 | return ret; |
e8788cbc ML |
13106 | |
13107 | DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n", | |
13108 | intel_state->cdclk, intel_state->dev_cdclk); | |
27c329ed | 13109 | } else |
1a617b77 | 13110 | to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq; |
054518dd | 13111 | |
ad421372 | 13112 | intel_modeset_clear_plls(state); |
054518dd | 13113 | |
565602d7 | 13114 | if (IS_HASWELL(dev_priv)) |
ad421372 | 13115 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 13116 | |
ad421372 | 13117 | return 0; |
c347a676 ACO |
13118 | } |
13119 | ||
aa363136 MR |
13120 | /* |
13121 | * Handle calculation of various watermark data at the end of the atomic check | |
13122 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
13123 | * handlers to ensure that all derived state has been updated. | |
13124 | */ | |
13125 | static void calc_watermark_data(struct drm_atomic_state *state) | |
13126 | { | |
13127 | struct drm_device *dev = state->dev; | |
13128 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
13129 | struct drm_crtc *crtc; | |
13130 | struct drm_crtc_state *cstate; | |
13131 | struct drm_plane *plane; | |
13132 | struct drm_plane_state *pstate; | |
13133 | ||
13134 | /* | |
13135 | * Calculate watermark configuration details now that derived | |
13136 | * plane/crtc state is all properly updated. | |
13137 | */ | |
13138 | drm_for_each_crtc(crtc, dev) { | |
13139 | cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?: | |
13140 | crtc->state; | |
13141 | ||
13142 | if (cstate->active) | |
13143 | intel_state->wm_config.num_pipes_active++; | |
13144 | } | |
13145 | drm_for_each_legacy_plane(plane, dev) { | |
13146 | pstate = drm_atomic_get_existing_plane_state(state, plane) ?: | |
13147 | plane->state; | |
13148 | ||
13149 | if (!to_intel_plane_state(pstate)->visible) | |
13150 | continue; | |
13151 | ||
13152 | intel_state->wm_config.sprites_enabled = true; | |
13153 | if (pstate->crtc_w != pstate->src_w >> 16 || | |
13154 | pstate->crtc_h != pstate->src_h >> 16) | |
13155 | intel_state->wm_config.sprites_scaled = true; | |
13156 | } | |
13157 | } | |
13158 | ||
74c090b1 ML |
13159 | /** |
13160 | * intel_atomic_check - validate state object | |
13161 | * @dev: drm device | |
13162 | * @state: state to validate | |
13163 | */ | |
13164 | static int intel_atomic_check(struct drm_device *dev, | |
13165 | struct drm_atomic_state *state) | |
c347a676 | 13166 | { |
dd8b3bdb | 13167 | struct drm_i915_private *dev_priv = to_i915(dev); |
aa363136 | 13168 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
c347a676 ACO |
13169 | struct drm_crtc *crtc; |
13170 | struct drm_crtc_state *crtc_state; | |
13171 | int ret, i; | |
61333b60 | 13172 | bool any_ms = false; |
c347a676 | 13173 | |
74c090b1 | 13174 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
13175 | if (ret) |
13176 | return ret; | |
13177 | ||
c347a676 | 13178 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
cfb23ed6 ML |
13179 | struct intel_crtc_state *pipe_config = |
13180 | to_intel_crtc_state(crtc_state); | |
1ed51de9 DV |
13181 | |
13182 | /* Catch I915_MODE_FLAG_INHERITED */ | |
13183 | if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) | |
13184 | crtc_state->mode_changed = true; | |
cfb23ed6 | 13185 | |
61333b60 ML |
13186 | if (!crtc_state->enable) { |
13187 | if (needs_modeset(crtc_state)) | |
13188 | any_ms = true; | |
c347a676 | 13189 | continue; |
61333b60 | 13190 | } |
c347a676 | 13191 | |
26495481 | 13192 | if (!needs_modeset(crtc_state)) |
cfb23ed6 ML |
13193 | continue; |
13194 | ||
26495481 DV |
13195 | /* FIXME: For only active_changed we shouldn't need to do any |
13196 | * state recomputation at all. */ | |
13197 | ||
1ed51de9 DV |
13198 | ret = drm_atomic_add_affected_connectors(state, crtc); |
13199 | if (ret) | |
13200 | return ret; | |
b359283a | 13201 | |
cfb23ed6 | 13202 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
c347a676 ACO |
13203 | if (ret) |
13204 | return ret; | |
13205 | ||
73831236 | 13206 | if (i915.fastboot && |
dd8b3bdb | 13207 | intel_pipe_config_compare(dev, |
cfb23ed6 | 13208 | to_intel_crtc_state(crtc->state), |
1ed51de9 | 13209 | pipe_config, true)) { |
26495481 | 13210 | crtc_state->mode_changed = false; |
bfd16b2a | 13211 | to_intel_crtc_state(crtc_state)->update_pipe = true; |
26495481 DV |
13212 | } |
13213 | ||
13214 | if (needs_modeset(crtc_state)) { | |
13215 | any_ms = true; | |
cfb23ed6 ML |
13216 | |
13217 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13218 | if (ret) | |
13219 | return ret; | |
13220 | } | |
61333b60 | 13221 | |
26495481 DV |
13222 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
13223 | needs_modeset(crtc_state) ? | |
13224 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
13225 | } |
13226 | ||
61333b60 ML |
13227 | if (any_ms) { |
13228 | ret = intel_modeset_checks(state); | |
13229 | ||
13230 | if (ret) | |
13231 | return ret; | |
27c329ed | 13232 | } else |
dd8b3bdb | 13233 | intel_state->cdclk = dev_priv->cdclk_freq; |
76305b1a | 13234 | |
dd8b3bdb | 13235 | ret = drm_atomic_helper_check_planes(dev, state); |
aa363136 MR |
13236 | if (ret) |
13237 | return ret; | |
13238 | ||
f51be2e0 | 13239 | intel_fbc_choose_crtc(dev_priv, state); |
aa363136 MR |
13240 | calc_watermark_data(state); |
13241 | ||
13242 | return 0; | |
054518dd ACO |
13243 | } |
13244 | ||
5008e874 ML |
13245 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
13246 | struct drm_atomic_state *state, | |
13247 | bool async) | |
13248 | { | |
7580d774 ML |
13249 | struct drm_i915_private *dev_priv = dev->dev_private; |
13250 | struct drm_plane_state *plane_state; | |
5008e874 | 13251 | struct drm_crtc_state *crtc_state; |
7580d774 | 13252 | struct drm_plane *plane; |
5008e874 ML |
13253 | struct drm_crtc *crtc; |
13254 | int i, ret; | |
13255 | ||
13256 | if (async) { | |
13257 | DRM_DEBUG_KMS("i915 does not yet support async commit\n"); | |
13258 | return -EINVAL; | |
13259 | } | |
13260 | ||
13261 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13262 | ret = intel_crtc_wait_for_pending_flips(crtc); | |
13263 | if (ret) | |
13264 | return ret; | |
7580d774 ML |
13265 | |
13266 | if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) | |
13267 | flush_workqueue(dev_priv->wq); | |
5008e874 ML |
13268 | } |
13269 | ||
f935675f ML |
13270 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
13271 | if (ret) | |
13272 | return ret; | |
13273 | ||
5008e874 | 13274 | ret = drm_atomic_helper_prepare_planes(dev, state); |
7580d774 ML |
13275 | if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) { |
13276 | u32 reset_counter; | |
13277 | ||
13278 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); | |
13279 | mutex_unlock(&dev->struct_mutex); | |
13280 | ||
13281 | for_each_plane_in_state(state, plane, plane_state, i) { | |
13282 | struct intel_plane_state *intel_plane_state = | |
13283 | to_intel_plane_state(plane_state); | |
13284 | ||
13285 | if (!intel_plane_state->wait_req) | |
13286 | continue; | |
13287 | ||
13288 | ret = __i915_wait_request(intel_plane_state->wait_req, | |
13289 | reset_counter, true, | |
13290 | NULL, NULL); | |
13291 | ||
13292 | /* Swallow -EIO errors to allow updates during hw lockup. */ | |
13293 | if (ret == -EIO) | |
13294 | ret = 0; | |
13295 | ||
13296 | if (ret) | |
13297 | break; | |
13298 | } | |
13299 | ||
13300 | if (!ret) | |
13301 | return 0; | |
13302 | ||
13303 | mutex_lock(&dev->struct_mutex); | |
13304 | drm_atomic_helper_cleanup_planes(dev, state); | |
13305 | } | |
5008e874 | 13306 | |
f935675f | 13307 | mutex_unlock(&dev->struct_mutex); |
5008e874 ML |
13308 | return ret; |
13309 | } | |
13310 | ||
e8861675 ML |
13311 | static void intel_atomic_wait_for_vblanks(struct drm_device *dev, |
13312 | struct drm_i915_private *dev_priv, | |
13313 | unsigned crtc_mask) | |
13314 | { | |
13315 | unsigned last_vblank_count[I915_MAX_PIPES]; | |
13316 | enum pipe pipe; | |
13317 | int ret; | |
13318 | ||
13319 | if (!crtc_mask) | |
13320 | return; | |
13321 | ||
13322 | for_each_pipe(dev_priv, pipe) { | |
13323 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
13324 | ||
13325 | if (!((1 << pipe) & crtc_mask)) | |
13326 | continue; | |
13327 | ||
13328 | ret = drm_crtc_vblank_get(crtc); | |
13329 | if (WARN_ON(ret != 0)) { | |
13330 | crtc_mask &= ~(1 << pipe); | |
13331 | continue; | |
13332 | } | |
13333 | ||
13334 | last_vblank_count[pipe] = drm_crtc_vblank_count(crtc); | |
13335 | } | |
13336 | ||
13337 | for_each_pipe(dev_priv, pipe) { | |
13338 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
13339 | long lret; | |
13340 | ||
13341 | if (!((1 << pipe) & crtc_mask)) | |
13342 | continue; | |
13343 | ||
13344 | lret = wait_event_timeout(dev->vblank[pipe].queue, | |
13345 | last_vblank_count[pipe] != | |
13346 | drm_crtc_vblank_count(crtc), | |
13347 | msecs_to_jiffies(50)); | |
13348 | ||
13349 | WARN_ON(!lret); | |
13350 | ||
13351 | drm_crtc_vblank_put(crtc); | |
13352 | } | |
13353 | } | |
13354 | ||
13355 | static bool needs_vblank_wait(struct intel_crtc_state *crtc_state) | |
13356 | { | |
13357 | /* fb updated, need to unpin old fb */ | |
13358 | if (crtc_state->fb_changed) | |
13359 | return true; | |
13360 | ||
13361 | /* wm changes, need vblank before final wm's */ | |
caed361d | 13362 | if (crtc_state->update_wm_post) |
e8861675 ML |
13363 | return true; |
13364 | ||
13365 | /* | |
13366 | * cxsr is re-enabled after vblank. | |
caed361d | 13367 | * This is already handled by crtc_state->update_wm_post, |
e8861675 ML |
13368 | * but added for clarity. |
13369 | */ | |
13370 | if (crtc_state->disable_cxsr) | |
13371 | return true; | |
13372 | ||
13373 | return false; | |
13374 | } | |
13375 | ||
74c090b1 ML |
13376 | /** |
13377 | * intel_atomic_commit - commit validated state object | |
13378 | * @dev: DRM device | |
13379 | * @state: the top-level driver state object | |
13380 | * @async: asynchronous commit | |
13381 | * | |
13382 | * This function commits a top-level state object that has been validated | |
13383 | * with drm_atomic_helper_check(). | |
13384 | * | |
13385 | * FIXME: Atomic modeset support for i915 is not yet complete. At the moment | |
13386 | * we can only handle plane-related operations and do not yet support | |
13387 | * asynchronous commit. | |
13388 | * | |
13389 | * RETURNS | |
13390 | * Zero for success or -errno. | |
13391 | */ | |
13392 | static int intel_atomic_commit(struct drm_device *dev, | |
13393 | struct drm_atomic_state *state, | |
13394 | bool async) | |
a6778b3c | 13395 | { |
565602d7 | 13396 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fbee40df | 13397 | struct drm_i915_private *dev_priv = dev->dev_private; |
29ceb0e6 | 13398 | struct drm_crtc_state *old_crtc_state; |
7580d774 | 13399 | struct drm_crtc *crtc; |
ed4a6a7c | 13400 | struct intel_crtc_state *intel_cstate; |
565602d7 ML |
13401 | int ret = 0, i; |
13402 | bool hw_check = intel_state->modeset; | |
33c8df89 | 13403 | unsigned long put_domains[I915_MAX_PIPES] = {}; |
e8861675 | 13404 | unsigned crtc_vblank_mask = 0; |
a6778b3c | 13405 | |
5008e874 | 13406 | ret = intel_atomic_prepare_commit(dev, state, async); |
7580d774 ML |
13407 | if (ret) { |
13408 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); | |
d4afb8cc | 13409 | return ret; |
7580d774 | 13410 | } |
d4afb8cc | 13411 | |
1c5e19f8 | 13412 | drm_atomic_helper_swap_state(dev, state); |
a1475e77 ML |
13413 | dev_priv->wm.config = intel_state->wm_config; |
13414 | intel_shared_dpll_commit(state); | |
1c5e19f8 | 13415 | |
565602d7 ML |
13416 | if (intel_state->modeset) { |
13417 | memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, | |
13418 | sizeof(intel_state->min_pixclk)); | |
13419 | dev_priv->active_crtcs = intel_state->active_crtcs; | |
1a617b77 | 13420 | dev_priv->atomic_cdclk_freq = intel_state->cdclk; |
33c8df89 ML |
13421 | |
13422 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); | |
565602d7 ML |
13423 | } |
13424 | ||
29ceb0e6 | 13425 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
a539205a ML |
13426 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13427 | ||
33c8df89 ML |
13428 | if (needs_modeset(crtc->state) || |
13429 | to_intel_crtc_state(crtc->state)->update_pipe) { | |
13430 | hw_check = true; | |
13431 | ||
13432 | put_domains[to_intel_crtc(crtc)->pipe] = | |
13433 | modeset_get_crtc_power_domains(crtc, | |
13434 | to_intel_crtc_state(crtc->state)); | |
13435 | } | |
13436 | ||
61333b60 ML |
13437 | if (!needs_modeset(crtc->state)) |
13438 | continue; | |
13439 | ||
29ceb0e6 | 13440 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); |
460da916 | 13441 | |
29ceb0e6 VS |
13442 | if (old_crtc_state->active) { |
13443 | intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask); | |
a539205a | 13444 | dev_priv->display.crtc_disable(crtc); |
eddfcbcd | 13445 | intel_crtc->active = false; |
58f9c0bc | 13446 | intel_fbc_disable(intel_crtc); |
eddfcbcd | 13447 | intel_disable_shared_dpll(intel_crtc); |
9bbc8258 VS |
13448 | |
13449 | /* | |
13450 | * Underruns don't always raise | |
13451 | * interrupts, so check manually. | |
13452 | */ | |
13453 | intel_check_cpu_fifo_underruns(dev_priv); | |
13454 | intel_check_pch_fifo_underruns(dev_priv); | |
b9001114 ML |
13455 | |
13456 | if (!crtc->state->active) | |
13457 | intel_update_watermarks(crtc); | |
a539205a | 13458 | } |
b8cecdf5 | 13459 | } |
7758a113 | 13460 | |
ea9d758d DV |
13461 | /* Only after disabling all output pipelines that will be changed can we |
13462 | * update the the output configuration. */ | |
4740b0f2 | 13463 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 13464 | |
565602d7 | 13465 | if (intel_state->modeset) { |
4740b0f2 | 13466 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); |
33c8df89 ML |
13467 | |
13468 | if (dev_priv->display.modeset_commit_cdclk && | |
13469 | intel_state->dev_cdclk != dev_priv->cdclk_freq) | |
13470 | dev_priv->display.modeset_commit_cdclk(state); | |
4740b0f2 | 13471 | } |
47fab737 | 13472 | |
a6778b3c | 13473 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
29ceb0e6 | 13474 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
f6ac4b2a ML |
13475 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13476 | bool modeset = needs_modeset(crtc->state); | |
e8861675 ML |
13477 | struct intel_crtc_state *pipe_config = |
13478 | to_intel_crtc_state(crtc->state); | |
13479 | bool update_pipe = !modeset && pipe_config->update_pipe; | |
9f836f90 | 13480 | |
f6ac4b2a | 13481 | if (modeset && crtc->state->active) { |
a539205a ML |
13482 | update_scanline_offset(to_intel_crtc(crtc)); |
13483 | dev_priv->display.crtc_enable(crtc); | |
13484 | } | |
80715b2f | 13485 | |
82cf435b LL |
13486 | if (!modeset && |
13487 | crtc->state->active && | |
13488 | crtc->state->color_mgmt_changed) { | |
13489 | /* | |
13490 | * Only update color management when not doing | |
13491 | * a modeset as this will be done by | |
13492 | * crtc_enable already. | |
13493 | */ | |
13494 | intel_color_set_csc(crtc); | |
13495 | intel_color_load_luts(crtc); | |
13496 | } | |
13497 | ||
f6ac4b2a | 13498 | if (!modeset) |
29ceb0e6 | 13499 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); |
f6ac4b2a | 13500 | |
31ae71fc ML |
13501 | if (crtc->state->active && |
13502 | drm_atomic_get_existing_plane_state(state, crtc->primary)) | |
49227c4a PZ |
13503 | intel_fbc_enable(intel_crtc); |
13504 | ||
6173ee28 ML |
13505 | if (crtc->state->active && |
13506 | (crtc->state->planes_changed || update_pipe)) | |
29ceb0e6 | 13507 | drm_atomic_helper_commit_planes_on_crtc(old_crtc_state); |
bfd16b2a | 13508 | |
e8861675 ML |
13509 | if (pipe_config->base.active && needs_vblank_wait(pipe_config)) |
13510 | crtc_vblank_mask |= 1 << i; | |
80715b2f | 13511 | } |
a6778b3c | 13512 | |
a6778b3c | 13513 | /* FIXME: add subpixel order */ |
83a57153 | 13514 | |
e8861675 ML |
13515 | if (!state->legacy_cursor_update) |
13516 | intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask); | |
f935675f | 13517 | |
ed4a6a7c MR |
13518 | /* |
13519 | * Now that the vblank has passed, we can go ahead and program the | |
13520 | * optimal watermarks on platforms that need two-step watermark | |
13521 | * programming. | |
13522 | * | |
13523 | * TODO: Move this (and other cleanup) to an async worker eventually. | |
13524 | */ | |
29ceb0e6 | 13525 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
ed4a6a7c MR |
13526 | intel_cstate = to_intel_crtc_state(crtc->state); |
13527 | ||
13528 | if (dev_priv->display.optimize_watermarks) | |
13529 | dev_priv->display.optimize_watermarks(intel_cstate); | |
13530 | } | |
13531 | ||
177246a8 MR |
13532 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
13533 | intel_post_plane_update(to_intel_crtc_state(old_crtc_state)); | |
13534 | ||
13535 | if (put_domains[i]) | |
13536 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
13537 | } | |
13538 | ||
13539 | if (intel_state->modeset) | |
13540 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); | |
13541 | ||
f935675f | 13542 | mutex_lock(&dev->struct_mutex); |
d4afb8cc | 13543 | drm_atomic_helper_cleanup_planes(dev, state); |
f935675f | 13544 | mutex_unlock(&dev->struct_mutex); |
2bfb4627 | 13545 | |
565602d7 | 13546 | if (hw_check) |
ee165b1a ML |
13547 | intel_modeset_check_state(dev, state); |
13548 | ||
13549 | drm_atomic_state_free(state); | |
f30da187 | 13550 | |
75714940 MK |
13551 | /* As one of the primary mmio accessors, KMS has a high likelihood |
13552 | * of triggering bugs in unclaimed access. After we finish | |
13553 | * modesetting, see if an error has been flagged, and if so | |
13554 | * enable debugging for the next modeset - and hope we catch | |
13555 | * the culprit. | |
13556 | * | |
13557 | * XXX note that we assume display power is on at this point. | |
13558 | * This might hold true now but we need to add pm helper to check | |
13559 | * unclaimed only when the hardware is on, as atomic commits | |
13560 | * can happen also when the device is completely off. | |
13561 | */ | |
13562 | intel_uncore_arm_unclaimed_mmio_detection(dev_priv); | |
13563 | ||
74c090b1 | 13564 | return 0; |
7f27126e JB |
13565 | } |
13566 | ||
c0c36b94 CW |
13567 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
13568 | { | |
83a57153 ACO |
13569 | struct drm_device *dev = crtc->dev; |
13570 | struct drm_atomic_state *state; | |
e694eb02 | 13571 | struct drm_crtc_state *crtc_state; |
2bfb4627 | 13572 | int ret; |
83a57153 ACO |
13573 | |
13574 | state = drm_atomic_state_alloc(dev); | |
13575 | if (!state) { | |
e694eb02 | 13576 | DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory", |
83a57153 ACO |
13577 | crtc->base.id); |
13578 | return; | |
13579 | } | |
13580 | ||
e694eb02 | 13581 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
83a57153 | 13582 | |
e694eb02 ML |
13583 | retry: |
13584 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13585 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
13586 | if (!ret) { | |
13587 | if (!crtc_state->active) | |
13588 | goto out; | |
83a57153 | 13589 | |
e694eb02 | 13590 | crtc_state->mode_changed = true; |
74c090b1 | 13591 | ret = drm_atomic_commit(state); |
83a57153 ACO |
13592 | } |
13593 | ||
e694eb02 ML |
13594 | if (ret == -EDEADLK) { |
13595 | drm_atomic_state_clear(state); | |
13596 | drm_modeset_backoff(state->acquire_ctx); | |
13597 | goto retry; | |
4ed9fb37 | 13598 | } |
4be07317 | 13599 | |
2bfb4627 | 13600 | if (ret) |
e694eb02 | 13601 | out: |
2bfb4627 | 13602 | drm_atomic_state_free(state); |
c0c36b94 CW |
13603 | } |
13604 | ||
25c5b266 DV |
13605 | #undef for_each_intel_crtc_masked |
13606 | ||
f6e5b160 | 13607 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
82cf435b | 13608 | .gamma_set = drm_atomic_helper_legacy_gamma_set, |
74c090b1 | 13609 | .set_config = drm_atomic_helper_set_config, |
82cf435b | 13610 | .set_property = drm_atomic_helper_crtc_set_property, |
f6e5b160 CW |
13611 | .destroy = intel_crtc_destroy, |
13612 | .page_flip = intel_crtc_page_flip, | |
1356837e MR |
13613 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
13614 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
13615 | }; |
13616 | ||
6beb8c23 MR |
13617 | /** |
13618 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
13619 | * @plane: drm plane to prepare for | |
13620 | * @fb: framebuffer to prepare for presentation | |
13621 | * | |
13622 | * Prepares a framebuffer for usage on a display plane. Generally this | |
13623 | * involves pinning the underlying object and updating the frontbuffer tracking | |
13624 | * bits. Some older platforms need special physical address handling for | |
13625 | * cursor planes. | |
13626 | * | |
f935675f ML |
13627 | * Must be called with struct_mutex held. |
13628 | * | |
6beb8c23 MR |
13629 | * Returns 0 on success, negative error code on failure. |
13630 | */ | |
13631 | int | |
13632 | intel_prepare_plane_fb(struct drm_plane *plane, | |
d136dfee | 13633 | const struct drm_plane_state *new_state) |
465c120c MR |
13634 | { |
13635 | struct drm_device *dev = plane->dev; | |
844f9111 | 13636 | struct drm_framebuffer *fb = new_state->fb; |
6beb8c23 | 13637 | struct intel_plane *intel_plane = to_intel_plane(plane); |
6beb8c23 | 13638 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1ee49399 | 13639 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
6beb8c23 | 13640 | int ret = 0; |
465c120c | 13641 | |
1ee49399 | 13642 | if (!obj && !old_obj) |
465c120c MR |
13643 | return 0; |
13644 | ||
5008e874 ML |
13645 | if (old_obj) { |
13646 | struct drm_crtc_state *crtc_state = | |
13647 | drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc); | |
13648 | ||
13649 | /* Big Hammer, we also need to ensure that any pending | |
13650 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
13651 | * current scanout is retired before unpinning the old | |
13652 | * framebuffer. Note that we rely on userspace rendering | |
13653 | * into the buffer attached to the pipe they are waiting | |
13654 | * on. If not, userspace generates a GPU hang with IPEHR | |
13655 | * point to the MI_WAIT_FOR_EVENT. | |
13656 | * | |
13657 | * This should only fail upon a hung GPU, in which case we | |
13658 | * can safely continue. | |
13659 | */ | |
13660 | if (needs_modeset(crtc_state)) | |
13661 | ret = i915_gem_object_wait_rendering(old_obj, true); | |
13662 | ||
13663 | /* Swallow -EIO errors to allow updates during hw lockup. */ | |
13664 | if (ret && ret != -EIO) | |
f935675f | 13665 | return ret; |
5008e874 ML |
13666 | } |
13667 | ||
3c28ff22 AG |
13668 | /* For framebuffer backed by dmabuf, wait for fence */ |
13669 | if (obj && obj->base.dma_buf) { | |
bcf8be27 ML |
13670 | long lret; |
13671 | ||
13672 | lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv, | |
13673 | false, true, | |
13674 | MAX_SCHEDULE_TIMEOUT); | |
13675 | if (lret == -ERESTARTSYS) | |
13676 | return lret; | |
3c28ff22 | 13677 | |
bcf8be27 | 13678 | WARN(lret < 0, "waiting returns %li\n", lret); |
3c28ff22 AG |
13679 | } |
13680 | ||
1ee49399 ML |
13681 | if (!obj) { |
13682 | ret = 0; | |
13683 | } else if (plane->type == DRM_PLANE_TYPE_CURSOR && | |
6beb8c23 MR |
13684 | INTEL_INFO(dev)->cursor_needs_physical) { |
13685 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
13686 | ret = i915_gem_object_attach_phys(obj, align); | |
13687 | if (ret) | |
13688 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
13689 | } else { | |
3465c580 | 13690 | ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation); |
6beb8c23 | 13691 | } |
465c120c | 13692 | |
7580d774 ML |
13693 | if (ret == 0) { |
13694 | if (obj) { | |
13695 | struct intel_plane_state *plane_state = | |
13696 | to_intel_plane_state(new_state); | |
13697 | ||
13698 | i915_gem_request_assign(&plane_state->wait_req, | |
13699 | obj->last_write_req); | |
13700 | } | |
13701 | ||
a9ff8714 | 13702 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); |
7580d774 | 13703 | } |
fdd508a6 | 13704 | |
6beb8c23 MR |
13705 | return ret; |
13706 | } | |
13707 | ||
38f3ce3a MR |
13708 | /** |
13709 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
13710 | * @plane: drm plane to clean up for | |
13711 | * @fb: old framebuffer that was on plane | |
13712 | * | |
13713 | * Cleans up a framebuffer that has just been removed from a plane. | |
f935675f ML |
13714 | * |
13715 | * Must be called with struct_mutex held. | |
38f3ce3a MR |
13716 | */ |
13717 | void | |
13718 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
d136dfee | 13719 | const struct drm_plane_state *old_state) |
38f3ce3a MR |
13720 | { |
13721 | struct drm_device *dev = plane->dev; | |
1ee49399 | 13722 | struct intel_plane *intel_plane = to_intel_plane(plane); |
7580d774 | 13723 | struct intel_plane_state *old_intel_state; |
1ee49399 ML |
13724 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb); |
13725 | struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb); | |
38f3ce3a | 13726 | |
7580d774 ML |
13727 | old_intel_state = to_intel_plane_state(old_state); |
13728 | ||
1ee49399 | 13729 | if (!obj && !old_obj) |
38f3ce3a MR |
13730 | return; |
13731 | ||
1ee49399 ML |
13732 | if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR || |
13733 | !INTEL_INFO(dev)->cursor_needs_physical)) | |
3465c580 | 13734 | intel_unpin_fb_obj(old_state->fb, old_state->rotation); |
1ee49399 ML |
13735 | |
13736 | /* prepare_fb aborted? */ | |
13737 | if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) || | |
13738 | (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit))) | |
13739 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); | |
7580d774 ML |
13740 | |
13741 | i915_gem_request_assign(&old_intel_state->wait_req, NULL); | |
465c120c MR |
13742 | } |
13743 | ||
6156a456 CK |
13744 | int |
13745 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
13746 | { | |
13747 | int max_scale; | |
13748 | struct drm_device *dev; | |
13749 | struct drm_i915_private *dev_priv; | |
13750 | int crtc_clock, cdclk; | |
13751 | ||
bf8a0af0 | 13752 | if (!intel_crtc || !crtc_state->base.enable) |
6156a456 CK |
13753 | return DRM_PLANE_HELPER_NO_SCALING; |
13754 | ||
13755 | dev = intel_crtc->base.dev; | |
13756 | dev_priv = dev->dev_private; | |
13757 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; | |
27c329ed | 13758 | cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; |
6156a456 | 13759 | |
54bf1ce6 | 13760 | if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)) |
6156a456 CK |
13761 | return DRM_PLANE_HELPER_NO_SCALING; |
13762 | ||
13763 | /* | |
13764 | * skl max scale is lower of: | |
13765 | * close to 3 but not 3, -1 is for that purpose | |
13766 | * or | |
13767 | * cdclk/crtc_clock | |
13768 | */ | |
13769 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); | |
13770 | ||
13771 | return max_scale; | |
13772 | } | |
13773 | ||
465c120c | 13774 | static int |
3c692a41 | 13775 | intel_check_primary_plane(struct drm_plane *plane, |
061e4b8d | 13776 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
13777 | struct intel_plane_state *state) |
13778 | { | |
2b875c22 MR |
13779 | struct drm_crtc *crtc = state->base.crtc; |
13780 | struct drm_framebuffer *fb = state->base.fb; | |
6156a456 | 13781 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
13782 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
13783 | bool can_position = false; | |
465c120c | 13784 | |
693bdc28 VS |
13785 | if (INTEL_INFO(plane->dev)->gen >= 9) { |
13786 | /* use scaler when colorkey is not required */ | |
13787 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { | |
13788 | min_scale = 1; | |
13789 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
13790 | } | |
d8106366 | 13791 | can_position = true; |
6156a456 | 13792 | } |
d8106366 | 13793 | |
061e4b8d ML |
13794 | return drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
13795 | &state->dst, &state->clip, | |
da20eabd ML |
13796 | min_scale, max_scale, |
13797 | can_position, true, | |
13798 | &state->visible); | |
14af293f GP |
13799 | } |
13800 | ||
613d2b27 ML |
13801 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
13802 | struct drm_crtc_state *old_crtc_state) | |
3c692a41 | 13803 | { |
32b7eeec | 13804 | struct drm_device *dev = crtc->dev; |
3c692a41 | 13805 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
bfd16b2a ML |
13806 | struct intel_crtc_state *old_intel_state = |
13807 | to_intel_crtc_state(old_crtc_state); | |
13808 | bool modeset = needs_modeset(crtc->state); | |
3c692a41 | 13809 | |
c34c9ee4 | 13810 | /* Perform vblank evasion around commit operation */ |
62852622 | 13811 | intel_pipe_update_start(intel_crtc); |
0583236e | 13812 | |
bfd16b2a ML |
13813 | if (modeset) |
13814 | return; | |
13815 | ||
13816 | if (to_intel_crtc_state(crtc->state)->update_pipe) | |
13817 | intel_update_pipe_config(intel_crtc, old_intel_state); | |
13818 | else if (INTEL_INFO(dev)->gen >= 9) | |
0583236e | 13819 | skl_detach_scalers(intel_crtc); |
32b7eeec MR |
13820 | } |
13821 | ||
613d2b27 ML |
13822 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, |
13823 | struct drm_crtc_state *old_crtc_state) | |
32b7eeec | 13824 | { |
32b7eeec | 13825 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
32b7eeec | 13826 | |
62852622 | 13827 | intel_pipe_update_end(intel_crtc); |
3c692a41 GP |
13828 | } |
13829 | ||
cf4c7c12 | 13830 | /** |
4a3b8769 MR |
13831 | * intel_plane_destroy - destroy a plane |
13832 | * @plane: plane to destroy | |
cf4c7c12 | 13833 | * |
4a3b8769 MR |
13834 | * Common destruction function for all types of planes (primary, cursor, |
13835 | * sprite). | |
cf4c7c12 | 13836 | */ |
4a3b8769 | 13837 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c MR |
13838 | { |
13839 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
13840 | drm_plane_cleanup(plane); | |
13841 | kfree(intel_plane); | |
13842 | } | |
13843 | ||
65a3fea0 | 13844 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
13845 | .update_plane = drm_atomic_helper_update_plane, |
13846 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 13847 | .destroy = intel_plane_destroy, |
c196e1d6 | 13848 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
13849 | .atomic_get_property = intel_plane_atomic_get_property, |
13850 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
13851 | .atomic_duplicate_state = intel_plane_duplicate_state, |
13852 | .atomic_destroy_state = intel_plane_destroy_state, | |
13853 | ||
465c120c MR |
13854 | }; |
13855 | ||
13856 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
13857 | int pipe) | |
13858 | { | |
13859 | struct intel_plane *primary; | |
8e7d688b | 13860 | struct intel_plane_state *state; |
465c120c | 13861 | const uint32_t *intel_primary_formats; |
45e3743a | 13862 | unsigned int num_formats; |
465c120c MR |
13863 | |
13864 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
13865 | if (primary == NULL) | |
13866 | return NULL; | |
13867 | ||
8e7d688b MR |
13868 | state = intel_create_plane_state(&primary->base); |
13869 | if (!state) { | |
ea2c67bb MR |
13870 | kfree(primary); |
13871 | return NULL; | |
13872 | } | |
8e7d688b | 13873 | primary->base.state = &state->base; |
ea2c67bb | 13874 | |
465c120c MR |
13875 | primary->can_scale = false; |
13876 | primary->max_downscale = 1; | |
6156a456 CK |
13877 | if (INTEL_INFO(dev)->gen >= 9) { |
13878 | primary->can_scale = true; | |
af99ceda | 13879 | state->scaler_id = -1; |
6156a456 | 13880 | } |
465c120c MR |
13881 | primary->pipe = pipe; |
13882 | primary->plane = pipe; | |
a9ff8714 | 13883 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 | 13884 | primary->check_plane = intel_check_primary_plane; |
465c120c MR |
13885 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
13886 | primary->plane = !pipe; | |
13887 | ||
6c0fd451 DL |
13888 | if (INTEL_INFO(dev)->gen >= 9) { |
13889 | intel_primary_formats = skl_primary_formats; | |
13890 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
a8d201af ML |
13891 | |
13892 | primary->update_plane = skylake_update_primary_plane; | |
13893 | primary->disable_plane = skylake_disable_primary_plane; | |
13894 | } else if (HAS_PCH_SPLIT(dev)) { | |
13895 | intel_primary_formats = i965_primary_formats; | |
13896 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
13897 | ||
13898 | primary->update_plane = ironlake_update_primary_plane; | |
13899 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 | 13900 | } else if (INTEL_INFO(dev)->gen >= 4) { |
568db4f2 DL |
13901 | intel_primary_formats = i965_primary_formats; |
13902 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
a8d201af ML |
13903 | |
13904 | primary->update_plane = i9xx_update_primary_plane; | |
13905 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 DL |
13906 | } else { |
13907 | intel_primary_formats = i8xx_primary_formats; | |
13908 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
a8d201af ML |
13909 | |
13910 | primary->update_plane = i9xx_update_primary_plane; | |
13911 | primary->disable_plane = i9xx_disable_primary_plane; | |
465c120c MR |
13912 | } |
13913 | ||
13914 | drm_universal_plane_init(dev, &primary->base, 0, | |
65a3fea0 | 13915 | &intel_plane_funcs, |
465c120c | 13916 | intel_primary_formats, num_formats, |
b0b3b795 | 13917 | DRM_PLANE_TYPE_PRIMARY, NULL); |
48404c1e | 13918 | |
3b7a5119 SJ |
13919 | if (INTEL_INFO(dev)->gen >= 4) |
13920 | intel_create_rotation_property(dev, primary); | |
48404c1e | 13921 | |
ea2c67bb MR |
13922 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
13923 | ||
465c120c MR |
13924 | return &primary->base; |
13925 | } | |
13926 | ||
3b7a5119 SJ |
13927 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
13928 | { | |
13929 | if (!dev->mode_config.rotation_property) { | |
13930 | unsigned long flags = BIT(DRM_ROTATE_0) | | |
13931 | BIT(DRM_ROTATE_180); | |
13932 | ||
13933 | if (INTEL_INFO(dev)->gen >= 9) | |
13934 | flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); | |
13935 | ||
13936 | dev->mode_config.rotation_property = | |
13937 | drm_mode_create_rotation_property(dev, flags); | |
13938 | } | |
13939 | if (dev->mode_config.rotation_property) | |
13940 | drm_object_attach_property(&plane->base.base, | |
13941 | dev->mode_config.rotation_property, | |
13942 | plane->base.state->rotation); | |
13943 | } | |
13944 | ||
3d7d6510 | 13945 | static int |
852e787c | 13946 | intel_check_cursor_plane(struct drm_plane *plane, |
061e4b8d | 13947 | struct intel_crtc_state *crtc_state, |
852e787c | 13948 | struct intel_plane_state *state) |
3d7d6510 | 13949 | { |
061e4b8d | 13950 | struct drm_crtc *crtc = crtc_state->base.crtc; |
2b875c22 | 13951 | struct drm_framebuffer *fb = state->base.fb; |
757f9a3e | 13952 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
b29ec92c | 13953 | enum pipe pipe = to_intel_plane(plane)->pipe; |
757f9a3e GP |
13954 | unsigned stride; |
13955 | int ret; | |
3d7d6510 | 13956 | |
061e4b8d ML |
13957 | ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
13958 | &state->dst, &state->clip, | |
3d7d6510 MR |
13959 | DRM_PLANE_HELPER_NO_SCALING, |
13960 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 13961 | true, true, &state->visible); |
757f9a3e GP |
13962 | if (ret) |
13963 | return ret; | |
13964 | ||
757f9a3e GP |
13965 | /* if we want to turn off the cursor ignore width and height */ |
13966 | if (!obj) | |
da20eabd | 13967 | return 0; |
757f9a3e | 13968 | |
757f9a3e | 13969 | /* Check for which cursor types we support */ |
061e4b8d | 13970 | if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) { |
ea2c67bb MR |
13971 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", |
13972 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
13973 | return -EINVAL; |
13974 | } | |
13975 | ||
ea2c67bb MR |
13976 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
13977 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
13978 | DRM_DEBUG_KMS("buffer is too small\n"); |
13979 | return -ENOMEM; | |
13980 | } | |
13981 | ||
3a656b54 | 13982 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e | 13983 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
da20eabd | 13984 | return -EINVAL; |
32b7eeec MR |
13985 | } |
13986 | ||
b29ec92c VS |
13987 | /* |
13988 | * There's something wrong with the cursor on CHV pipe C. | |
13989 | * If it straddles the left edge of the screen then | |
13990 | * moving it away from the edge or disabling it often | |
13991 | * results in a pipe underrun, and often that can lead to | |
13992 | * dead pipe (constant underrun reported, and it scans | |
13993 | * out just a solid color). To recover from that, the | |
13994 | * display power well must be turned off and on again. | |
13995 | * Refuse the put the cursor into that compromised position. | |
13996 | */ | |
13997 | if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C && | |
13998 | state->visible && state->base.crtc_x < 0) { | |
13999 | DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); | |
14000 | return -EINVAL; | |
14001 | } | |
14002 | ||
da20eabd | 14003 | return 0; |
852e787c | 14004 | } |
3d7d6510 | 14005 | |
a8ad0d8e ML |
14006 | static void |
14007 | intel_disable_cursor_plane(struct drm_plane *plane, | |
7fabf5ef | 14008 | struct drm_crtc *crtc) |
a8ad0d8e | 14009 | { |
f2858021 ML |
14010 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
14011 | ||
14012 | intel_crtc->cursor_addr = 0; | |
55a08b3f | 14013 | intel_crtc_update_cursor(crtc, NULL); |
a8ad0d8e ML |
14014 | } |
14015 | ||
f4a2cf29 | 14016 | static void |
55a08b3f ML |
14017 | intel_update_cursor_plane(struct drm_plane *plane, |
14018 | const struct intel_crtc_state *crtc_state, | |
14019 | const struct intel_plane_state *state) | |
852e787c | 14020 | { |
55a08b3f ML |
14021 | struct drm_crtc *crtc = crtc_state->base.crtc; |
14022 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ea2c67bb | 14023 | struct drm_device *dev = plane->dev; |
2b875c22 | 14024 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 14025 | uint32_t addr; |
852e787c | 14026 | |
f4a2cf29 | 14027 | if (!obj) |
a912f12f | 14028 | addr = 0; |
f4a2cf29 | 14029 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 14030 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 14031 | else |
a912f12f | 14032 | addr = obj->phys_handle->busaddr; |
852e787c | 14033 | |
a912f12f | 14034 | intel_crtc->cursor_addr = addr; |
55a08b3f | 14035 | intel_crtc_update_cursor(crtc, state); |
852e787c GP |
14036 | } |
14037 | ||
3d7d6510 MR |
14038 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
14039 | int pipe) | |
14040 | { | |
14041 | struct intel_plane *cursor; | |
8e7d688b | 14042 | struct intel_plane_state *state; |
3d7d6510 MR |
14043 | |
14044 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
14045 | if (cursor == NULL) | |
14046 | return NULL; | |
14047 | ||
8e7d688b MR |
14048 | state = intel_create_plane_state(&cursor->base); |
14049 | if (!state) { | |
ea2c67bb MR |
14050 | kfree(cursor); |
14051 | return NULL; | |
14052 | } | |
8e7d688b | 14053 | cursor->base.state = &state->base; |
ea2c67bb | 14054 | |
3d7d6510 MR |
14055 | cursor->can_scale = false; |
14056 | cursor->max_downscale = 1; | |
14057 | cursor->pipe = pipe; | |
14058 | cursor->plane = pipe; | |
a9ff8714 | 14059 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
c59cb179 | 14060 | cursor->check_plane = intel_check_cursor_plane; |
55a08b3f | 14061 | cursor->update_plane = intel_update_cursor_plane; |
a8ad0d8e | 14062 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 MR |
14063 | |
14064 | drm_universal_plane_init(dev, &cursor->base, 0, | |
65a3fea0 | 14065 | &intel_plane_funcs, |
3d7d6510 MR |
14066 | intel_cursor_formats, |
14067 | ARRAY_SIZE(intel_cursor_formats), | |
b0b3b795 | 14068 | DRM_PLANE_TYPE_CURSOR, NULL); |
4398ad45 VS |
14069 | |
14070 | if (INTEL_INFO(dev)->gen >= 4) { | |
14071 | if (!dev->mode_config.rotation_property) | |
14072 | dev->mode_config.rotation_property = | |
14073 | drm_mode_create_rotation_property(dev, | |
14074 | BIT(DRM_ROTATE_0) | | |
14075 | BIT(DRM_ROTATE_180)); | |
14076 | if (dev->mode_config.rotation_property) | |
14077 | drm_object_attach_property(&cursor->base.base, | |
14078 | dev->mode_config.rotation_property, | |
8e7d688b | 14079 | state->base.rotation); |
4398ad45 VS |
14080 | } |
14081 | ||
af99ceda CK |
14082 | if (INTEL_INFO(dev)->gen >=9) |
14083 | state->scaler_id = -1; | |
14084 | ||
ea2c67bb MR |
14085 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
14086 | ||
3d7d6510 MR |
14087 | return &cursor->base; |
14088 | } | |
14089 | ||
549e2bfb CK |
14090 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
14091 | struct intel_crtc_state *crtc_state) | |
14092 | { | |
14093 | int i; | |
14094 | struct intel_scaler *intel_scaler; | |
14095 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; | |
14096 | ||
14097 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
14098 | intel_scaler = &scaler_state->scalers[i]; | |
14099 | intel_scaler->in_use = 0; | |
549e2bfb CK |
14100 | intel_scaler->mode = PS_SCALER_MODE_DYN; |
14101 | } | |
14102 | ||
14103 | scaler_state->scaler_id = -1; | |
14104 | } | |
14105 | ||
b358d0a6 | 14106 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 14107 | { |
fbee40df | 14108 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 14109 | struct intel_crtc *intel_crtc; |
f5de6e07 | 14110 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
14111 | struct drm_plane *primary = NULL; |
14112 | struct drm_plane *cursor = NULL; | |
8563b1e8 | 14113 | int ret; |
79e53945 | 14114 | |
955382f3 | 14115 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
14116 | if (intel_crtc == NULL) |
14117 | return; | |
14118 | ||
f5de6e07 ACO |
14119 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
14120 | if (!crtc_state) | |
14121 | goto fail; | |
550acefd ACO |
14122 | intel_crtc->config = crtc_state; |
14123 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 14124 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 14125 | |
549e2bfb CK |
14126 | /* initialize shared scalers */ |
14127 | if (INTEL_INFO(dev)->gen >= 9) { | |
14128 | if (pipe == PIPE_C) | |
14129 | intel_crtc->num_scalers = 1; | |
14130 | else | |
14131 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
14132 | ||
14133 | skl_init_scalers(dev, intel_crtc, crtc_state); | |
14134 | } | |
14135 | ||
465c120c | 14136 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
14137 | if (!primary) |
14138 | goto fail; | |
14139 | ||
14140 | cursor = intel_cursor_plane_create(dev, pipe); | |
14141 | if (!cursor) | |
14142 | goto fail; | |
14143 | ||
465c120c | 14144 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
f9882876 | 14145 | cursor, &intel_crtc_funcs, NULL); |
3d7d6510 MR |
14146 | if (ret) |
14147 | goto fail; | |
79e53945 | 14148 | |
1f1c2e24 VS |
14149 | /* |
14150 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 14151 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 14152 | */ |
80824003 JB |
14153 | intel_crtc->pipe = pipe; |
14154 | intel_crtc->plane = pipe; | |
3a77c4c4 | 14155 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 14156 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 14157 | intel_crtc->plane = !pipe; |
80824003 JB |
14158 | } |
14159 | ||
4b0e333e CW |
14160 | intel_crtc->cursor_base = ~0; |
14161 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 14162 | intel_crtc->cursor_size = ~0; |
8d7849db | 14163 | |
852eb00d VS |
14164 | intel_crtc->wm.cxsr_allowed = true; |
14165 | ||
22fd0fab JB |
14166 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
14167 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
14168 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
14169 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
14170 | ||
79e53945 | 14171 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 | 14172 | |
8563b1e8 LL |
14173 | intel_color_init(&intel_crtc->base); |
14174 | ||
87b6b101 | 14175 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); |
3d7d6510 MR |
14176 | return; |
14177 | ||
14178 | fail: | |
14179 | if (primary) | |
14180 | drm_plane_cleanup(primary); | |
14181 | if (cursor) | |
14182 | drm_plane_cleanup(cursor); | |
f5de6e07 | 14183 | kfree(crtc_state); |
3d7d6510 | 14184 | kfree(intel_crtc); |
79e53945 JB |
14185 | } |
14186 | ||
752aa88a JB |
14187 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
14188 | { | |
14189 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 14190 | struct drm_device *dev = connector->base.dev; |
752aa88a | 14191 | |
51fd371b | 14192 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 14193 | |
d3babd3f | 14194 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
14195 | return INVALID_PIPE; |
14196 | ||
14197 | return to_intel_crtc(encoder->crtc)->pipe; | |
14198 | } | |
14199 | ||
08d7b3d1 | 14200 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 14201 | struct drm_file *file) |
08d7b3d1 | 14202 | { |
08d7b3d1 | 14203 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 14204 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 14205 | struct intel_crtc *crtc; |
08d7b3d1 | 14206 | |
7707e653 | 14207 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 14208 | |
7707e653 | 14209 | if (!drmmode_crtc) { |
08d7b3d1 | 14210 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 14211 | return -ENOENT; |
08d7b3d1 CW |
14212 | } |
14213 | ||
7707e653 | 14214 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 14215 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 14216 | |
c05422d5 | 14217 | return 0; |
08d7b3d1 CW |
14218 | } |
14219 | ||
66a9278e | 14220 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 14221 | { |
66a9278e DV |
14222 | struct drm_device *dev = encoder->base.dev; |
14223 | struct intel_encoder *source_encoder; | |
79e53945 | 14224 | int index_mask = 0; |
79e53945 JB |
14225 | int entry = 0; |
14226 | ||
b2784e15 | 14227 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 14228 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
14229 | index_mask |= (1 << entry); |
14230 | ||
79e53945 JB |
14231 | entry++; |
14232 | } | |
4ef69c7a | 14233 | |
79e53945 JB |
14234 | return index_mask; |
14235 | } | |
14236 | ||
4d302442 CW |
14237 | static bool has_edp_a(struct drm_device *dev) |
14238 | { | |
14239 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14240 | ||
14241 | if (!IS_MOBILE(dev)) | |
14242 | return false; | |
14243 | ||
14244 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
14245 | return false; | |
14246 | ||
e3589908 | 14247 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
14248 | return false; |
14249 | ||
14250 | return true; | |
14251 | } | |
14252 | ||
84b4e042 JB |
14253 | static bool intel_crt_present(struct drm_device *dev) |
14254 | { | |
14255 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14256 | ||
884497ed DL |
14257 | if (INTEL_INFO(dev)->gen >= 9) |
14258 | return false; | |
14259 | ||
cf404ce4 | 14260 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
14261 | return false; |
14262 | ||
14263 | if (IS_CHERRYVIEW(dev)) | |
14264 | return false; | |
14265 | ||
65e472e4 VS |
14266 | if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) |
14267 | return false; | |
14268 | ||
70ac54d0 VS |
14269 | /* DDI E can't be used if DDI A requires 4 lanes */ |
14270 | if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) | |
14271 | return false; | |
14272 | ||
e4abb733 | 14273 | if (!dev_priv->vbt.int_crt_support) |
84b4e042 JB |
14274 | return false; |
14275 | ||
14276 | return true; | |
14277 | } | |
14278 | ||
79e53945 JB |
14279 | static void intel_setup_outputs(struct drm_device *dev) |
14280 | { | |
725e30ad | 14281 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 14282 | struct intel_encoder *encoder; |
cb0953d7 | 14283 | bool dpd_is_edp = false; |
79e53945 | 14284 | |
c9093354 | 14285 | intel_lvds_init(dev); |
79e53945 | 14286 | |
84b4e042 | 14287 | if (intel_crt_present(dev)) |
79935fca | 14288 | intel_crt_init(dev); |
cb0953d7 | 14289 | |
c776eb2e VK |
14290 | if (IS_BROXTON(dev)) { |
14291 | /* | |
14292 | * FIXME: Broxton doesn't support port detection via the | |
14293 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
14294 | * detect the ports. | |
14295 | */ | |
14296 | intel_ddi_init(dev, PORT_A); | |
14297 | intel_ddi_init(dev, PORT_B); | |
14298 | intel_ddi_init(dev, PORT_C); | |
c6c794a2 SS |
14299 | |
14300 | intel_dsi_init(dev); | |
c776eb2e | 14301 | } else if (HAS_DDI(dev)) { |
0e72a5b5 ED |
14302 | int found; |
14303 | ||
de31facd JB |
14304 | /* |
14305 | * Haswell uses DDI functions to detect digital outputs. | |
14306 | * On SKL pre-D0 the strap isn't connected, so we assume | |
14307 | * it's there. | |
14308 | */ | |
77179400 | 14309 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 14310 | /* WaIgnoreDDIAStrap: skl */ |
ef11bdb3 | 14311 | if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
0e72a5b5 ED |
14312 | intel_ddi_init(dev, PORT_A); |
14313 | ||
14314 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
14315 | * register */ | |
14316 | found = I915_READ(SFUSE_STRAP); | |
14317 | ||
14318 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
14319 | intel_ddi_init(dev, PORT_B); | |
14320 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
14321 | intel_ddi_init(dev, PORT_C); | |
14322 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
14323 | intel_ddi_init(dev, PORT_D); | |
2800e4c2 RV |
14324 | /* |
14325 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
14326 | */ | |
ef11bdb3 | 14327 | if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && |
2800e4c2 RV |
14328 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
14329 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
14330 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
14331 | intel_ddi_init(dev, PORT_E); | |
14332 | ||
0e72a5b5 | 14333 | } else if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 14334 | int found; |
5d8a7752 | 14335 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
14336 | |
14337 | if (has_edp_a(dev)) | |
14338 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 14339 | |
dc0fa718 | 14340 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 14341 | /* PCH SDVOB multiplex with HDMIB */ |
2a5c0832 | 14342 | found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B); |
30ad48b7 | 14343 | if (!found) |
e2debe91 | 14344 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 14345 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 14346 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
14347 | } |
14348 | ||
dc0fa718 | 14349 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 14350 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 14351 | |
dc0fa718 | 14352 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 14353 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 14354 | |
5eb08b69 | 14355 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 14356 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 14357 | |
270b3042 | 14358 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 14359 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
666a4537 | 14360 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
e17ac6db VS |
14361 | /* |
14362 | * The DP_DETECTED bit is the latched state of the DDC | |
14363 | * SDA pin at boot. However since eDP doesn't require DDC | |
14364 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
14365 | * eDP ports may have been muxed to an alternate function. | |
14366 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
14367 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
14368 | * detect eDP ports. | |
14369 | */ | |
e66eb81d | 14370 | if (I915_READ(VLV_HDMIB) & SDVO_DETECTED && |
d2182a66 | 14371 | !intel_dp_is_edp(dev, PORT_B)) |
e66eb81d VS |
14372 | intel_hdmi_init(dev, VLV_HDMIB, PORT_B); |
14373 | if (I915_READ(VLV_DP_B) & DP_DETECTED || | |
e17ac6db | 14374 | intel_dp_is_edp(dev, PORT_B)) |
e66eb81d | 14375 | intel_dp_init(dev, VLV_DP_B, PORT_B); |
585a94b8 | 14376 | |
e66eb81d | 14377 | if (I915_READ(VLV_HDMIC) & SDVO_DETECTED && |
d2182a66 | 14378 | !intel_dp_is_edp(dev, PORT_C)) |
e66eb81d VS |
14379 | intel_hdmi_init(dev, VLV_HDMIC, PORT_C); |
14380 | if (I915_READ(VLV_DP_C) & DP_DETECTED || | |
e17ac6db | 14381 | intel_dp_is_edp(dev, PORT_C)) |
e66eb81d | 14382 | intel_dp_init(dev, VLV_DP_C, PORT_C); |
19c03924 | 14383 | |
9418c1f1 | 14384 | if (IS_CHERRYVIEW(dev)) { |
e17ac6db | 14385 | /* eDP not supported on port D, so don't check VBT */ |
e66eb81d VS |
14386 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED) |
14387 | intel_hdmi_init(dev, CHV_HDMID, PORT_D); | |
14388 | if (I915_READ(CHV_DP_D) & DP_DETECTED) | |
14389 | intel_dp_init(dev, CHV_DP_D, PORT_D); | |
9418c1f1 VS |
14390 | } |
14391 | ||
3cfca973 | 14392 | intel_dsi_init(dev); |
09da55dc | 14393 | } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) { |
27185ae1 | 14394 | bool found = false; |
7d57382e | 14395 | |
e2debe91 | 14396 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14397 | DRM_DEBUG_KMS("probing SDVOB\n"); |
2a5c0832 | 14398 | found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B); |
3fec3d2f | 14399 | if (!found && IS_G4X(dev)) { |
b01f2c3a | 14400 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
e2debe91 | 14401 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 14402 | } |
27185ae1 | 14403 | |
3fec3d2f | 14404 | if (!found && IS_G4X(dev)) |
ab9d7c30 | 14405 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 14406 | } |
13520b05 KH |
14407 | |
14408 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 14409 | |
e2debe91 | 14410 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14411 | DRM_DEBUG_KMS("probing SDVOC\n"); |
2a5c0832 | 14412 | found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C); |
b01f2c3a | 14413 | } |
27185ae1 | 14414 | |
e2debe91 | 14415 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 14416 | |
3fec3d2f | 14417 | if (IS_G4X(dev)) { |
b01f2c3a | 14418 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
e2debe91 | 14419 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 14420 | } |
3fec3d2f | 14421 | if (IS_G4X(dev)) |
ab9d7c30 | 14422 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 14423 | } |
27185ae1 | 14424 | |
3fec3d2f | 14425 | if (IS_G4X(dev) && |
e7281eab | 14426 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 14427 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 14428 | } else if (IS_GEN2(dev)) |
79e53945 JB |
14429 | intel_dvo_init(dev); |
14430 | ||
103a196f | 14431 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
14432 | intel_tv_init(dev); |
14433 | ||
0bc12bcb | 14434 | intel_psr_init(dev); |
7c8f8a70 | 14435 | |
b2784e15 | 14436 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
14437 | encoder->base.possible_crtcs = encoder->crtc_mask; |
14438 | encoder->base.possible_clones = | |
66a9278e | 14439 | intel_encoder_clones(encoder); |
79e53945 | 14440 | } |
47356eb6 | 14441 | |
dde86e2d | 14442 | intel_init_pch_refclk(dev); |
270b3042 DV |
14443 | |
14444 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
14445 | } |
14446 | ||
14447 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
14448 | { | |
60a5ca01 | 14449 | struct drm_device *dev = fb->dev; |
79e53945 | 14450 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 14451 | |
ef2d633e | 14452 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 14453 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 14454 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
14455 | drm_gem_object_unreference(&intel_fb->obj->base); |
14456 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
14457 | kfree(intel_fb); |
14458 | } | |
14459 | ||
14460 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 14461 | struct drm_file *file, |
79e53945 JB |
14462 | unsigned int *handle) |
14463 | { | |
14464 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 14465 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 14466 | |
cc917ab4 CW |
14467 | if (obj->userptr.mm) { |
14468 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); | |
14469 | return -EINVAL; | |
14470 | } | |
14471 | ||
05394f39 | 14472 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
14473 | } |
14474 | ||
86c98588 RV |
14475 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
14476 | struct drm_file *file, | |
14477 | unsigned flags, unsigned color, | |
14478 | struct drm_clip_rect *clips, | |
14479 | unsigned num_clips) | |
14480 | { | |
14481 | struct drm_device *dev = fb->dev; | |
14482 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
14483 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
14484 | ||
14485 | mutex_lock(&dev->struct_mutex); | |
74b4ea1e | 14486 | intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); |
86c98588 RV |
14487 | mutex_unlock(&dev->struct_mutex); |
14488 | ||
14489 | return 0; | |
14490 | } | |
14491 | ||
79e53945 JB |
14492 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
14493 | .destroy = intel_user_framebuffer_destroy, | |
14494 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 14495 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
14496 | }; |
14497 | ||
b321803d DL |
14498 | static |
14499 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
14500 | uint32_t pixel_format) | |
14501 | { | |
14502 | u32 gen = INTEL_INFO(dev)->gen; | |
14503 | ||
14504 | if (gen >= 9) { | |
ac484963 VS |
14505 | int cpp = drm_format_plane_cpp(pixel_format, 0); |
14506 | ||
b321803d DL |
14507 | /* "The stride in bytes must not exceed the of the size of 8K |
14508 | * pixels and 32K bytes." | |
14509 | */ | |
ac484963 | 14510 | return min(8192 * cpp, 32768); |
666a4537 | 14511 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
b321803d DL |
14512 | return 32*1024; |
14513 | } else if (gen >= 4) { | |
14514 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14515 | return 16*1024; | |
14516 | else | |
14517 | return 32*1024; | |
14518 | } else if (gen >= 3) { | |
14519 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14520 | return 8*1024; | |
14521 | else | |
14522 | return 16*1024; | |
14523 | } else { | |
14524 | /* XXX DSPC is limited to 4k tiled */ | |
14525 | return 8*1024; | |
14526 | } | |
14527 | } | |
14528 | ||
b5ea642a DV |
14529 | static int intel_framebuffer_init(struct drm_device *dev, |
14530 | struct intel_framebuffer *intel_fb, | |
14531 | struct drm_mode_fb_cmd2 *mode_cmd, | |
14532 | struct drm_i915_gem_object *obj) | |
79e53945 | 14533 | { |
7b49f948 | 14534 | struct drm_i915_private *dev_priv = to_i915(dev); |
6761dd31 | 14535 | unsigned int aligned_height; |
79e53945 | 14536 | int ret; |
b321803d | 14537 | u32 pitch_limit, stride_alignment; |
79e53945 | 14538 | |
dd4916c5 DV |
14539 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
14540 | ||
2a80eada DV |
14541 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
14542 | /* Enforce that fb modifier and tiling mode match, but only for | |
14543 | * X-tiled. This is needed for FBC. */ | |
14544 | if (!!(obj->tiling_mode == I915_TILING_X) != | |
14545 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { | |
14546 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
14547 | return -EINVAL; | |
14548 | } | |
14549 | } else { | |
14550 | if (obj->tiling_mode == I915_TILING_X) | |
14551 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
14552 | else if (obj->tiling_mode == I915_TILING_Y) { | |
14553 | DRM_DEBUG("No Y tiling for legacy addfb\n"); | |
14554 | return -EINVAL; | |
14555 | } | |
14556 | } | |
14557 | ||
9a8f0a12 TU |
14558 | /* Passed in modifier sanity checking. */ |
14559 | switch (mode_cmd->modifier[0]) { | |
14560 | case I915_FORMAT_MOD_Y_TILED: | |
14561 | case I915_FORMAT_MOD_Yf_TILED: | |
14562 | if (INTEL_INFO(dev)->gen < 9) { | |
14563 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
14564 | mode_cmd->modifier[0]); | |
14565 | return -EINVAL; | |
14566 | } | |
14567 | case DRM_FORMAT_MOD_NONE: | |
14568 | case I915_FORMAT_MOD_X_TILED: | |
14569 | break; | |
14570 | default: | |
c0f40428 JB |
14571 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
14572 | mode_cmd->modifier[0]); | |
57cd6508 | 14573 | return -EINVAL; |
c16ed4be | 14574 | } |
57cd6508 | 14575 | |
7b49f948 VS |
14576 | stride_alignment = intel_fb_stride_alignment(dev_priv, |
14577 | mode_cmd->modifier[0], | |
b321803d DL |
14578 | mode_cmd->pixel_format); |
14579 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
14580 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
14581 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 14582 | return -EINVAL; |
c16ed4be | 14583 | } |
57cd6508 | 14584 | |
b321803d DL |
14585 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
14586 | mode_cmd->pixel_format); | |
a35cdaa0 | 14587 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
14588 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
14589 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 14590 | "tiled" : "linear", |
a35cdaa0 | 14591 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 14592 | return -EINVAL; |
c16ed4be | 14593 | } |
5d7bd705 | 14594 | |
2a80eada | 14595 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
c16ed4be CW |
14596 | mode_cmd->pitches[0] != obj->stride) { |
14597 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
14598 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 14599 | return -EINVAL; |
c16ed4be | 14600 | } |
5d7bd705 | 14601 | |
57779d06 | 14602 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 14603 | switch (mode_cmd->pixel_format) { |
57779d06 | 14604 | case DRM_FORMAT_C8: |
04b3924d VS |
14605 | case DRM_FORMAT_RGB565: |
14606 | case DRM_FORMAT_XRGB8888: | |
14607 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
14608 | break; |
14609 | case DRM_FORMAT_XRGB1555: | |
c16ed4be | 14610 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
14611 | DRM_DEBUG("unsupported pixel format: %s\n", |
14612 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14613 | return -EINVAL; |
c16ed4be | 14614 | } |
57779d06 | 14615 | break; |
57779d06 | 14616 | case DRM_FORMAT_ABGR8888: |
666a4537 WB |
14617 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
14618 | INTEL_INFO(dev)->gen < 9) { | |
6c0fd451 DL |
14619 | DRM_DEBUG("unsupported pixel format: %s\n", |
14620 | drm_get_format_name(mode_cmd->pixel_format)); | |
14621 | return -EINVAL; | |
14622 | } | |
14623 | break; | |
14624 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 14625 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 14626 | case DRM_FORMAT_XBGR2101010: |
c16ed4be | 14627 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
14628 | DRM_DEBUG("unsupported pixel format: %s\n", |
14629 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14630 | return -EINVAL; |
c16ed4be | 14631 | } |
b5626747 | 14632 | break; |
7531208b | 14633 | case DRM_FORMAT_ABGR2101010: |
666a4537 | 14634 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
7531208b DL |
14635 | DRM_DEBUG("unsupported pixel format: %s\n", |
14636 | drm_get_format_name(mode_cmd->pixel_format)); | |
14637 | return -EINVAL; | |
14638 | } | |
14639 | break; | |
04b3924d VS |
14640 | case DRM_FORMAT_YUYV: |
14641 | case DRM_FORMAT_UYVY: | |
14642 | case DRM_FORMAT_YVYU: | |
14643 | case DRM_FORMAT_VYUY: | |
c16ed4be | 14644 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
14645 | DRM_DEBUG("unsupported pixel format: %s\n", |
14646 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14647 | return -EINVAL; |
c16ed4be | 14648 | } |
57cd6508 CW |
14649 | break; |
14650 | default: | |
4ee62c76 VS |
14651 | DRM_DEBUG("unsupported pixel format: %s\n", |
14652 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
14653 | return -EINVAL; |
14654 | } | |
14655 | ||
90f9a336 VS |
14656 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
14657 | if (mode_cmd->offsets[0] != 0) | |
14658 | return -EINVAL; | |
14659 | ||
ec2c981e | 14660 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
091df6cb DV |
14661 | mode_cmd->pixel_format, |
14662 | mode_cmd->modifier[0]); | |
53155c0a DV |
14663 | /* FIXME drm helper for size checks (especially planar formats)? */ |
14664 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
14665 | return -EINVAL; | |
14666 | ||
c7d73f6a DV |
14667 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
14668 | intel_fb->obj = obj; | |
14669 | ||
2d7a215f VS |
14670 | intel_fill_fb_info(dev_priv, &intel_fb->base); |
14671 | ||
79e53945 JB |
14672 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
14673 | if (ret) { | |
14674 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
14675 | return ret; | |
14676 | } | |
14677 | ||
0b05e1e0 VS |
14678 | intel_fb->obj->framebuffer_references++; |
14679 | ||
79e53945 JB |
14680 | return 0; |
14681 | } | |
14682 | ||
79e53945 JB |
14683 | static struct drm_framebuffer * |
14684 | intel_user_framebuffer_create(struct drm_device *dev, | |
14685 | struct drm_file *filp, | |
1eb83451 | 14686 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
79e53945 | 14687 | { |
dcb1394e | 14688 | struct drm_framebuffer *fb; |
05394f39 | 14689 | struct drm_i915_gem_object *obj; |
76dc3769 | 14690 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
79e53945 | 14691 | |
308e5bcb | 14692 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
76dc3769 | 14693 | mode_cmd.handles[0])); |
c8725226 | 14694 | if (&obj->base == NULL) |
cce13ff7 | 14695 | return ERR_PTR(-ENOENT); |
79e53945 | 14696 | |
92907cbb | 14697 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
dcb1394e LW |
14698 | if (IS_ERR(fb)) |
14699 | drm_gem_object_unreference_unlocked(&obj->base); | |
14700 | ||
14701 | return fb; | |
79e53945 JB |
14702 | } |
14703 | ||
0695726e | 14704 | #ifndef CONFIG_DRM_FBDEV_EMULATION |
0632fef6 | 14705 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
14706 | { |
14707 | } | |
14708 | #endif | |
14709 | ||
79e53945 | 14710 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 14711 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 14712 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
14713 | .atomic_check = intel_atomic_check, |
14714 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
14715 | .atomic_state_alloc = intel_atomic_state_alloc, |
14716 | .atomic_state_clear = intel_atomic_state_clear, | |
79e53945 JB |
14717 | }; |
14718 | ||
88212941 ID |
14719 | /** |
14720 | * intel_init_display_hooks - initialize the display modesetting hooks | |
14721 | * @dev_priv: device private | |
14722 | */ | |
14723 | void intel_init_display_hooks(struct drm_i915_private *dev_priv) | |
e70236a8 | 14724 | { |
88212941 | 14725 | if (HAS_PCH_SPLIT(dev_priv) || IS_G4X(dev_priv)) |
ee9300bb | 14726 | dev_priv->display.find_dpll = g4x_find_best_dpll; |
88212941 | 14727 | else if (IS_CHERRYVIEW(dev_priv)) |
ef9348c8 | 14728 | dev_priv->display.find_dpll = chv_find_best_dpll; |
88212941 | 14729 | else if (IS_VALLEYVIEW(dev_priv)) |
ee9300bb | 14730 | dev_priv->display.find_dpll = vlv_find_best_dpll; |
88212941 | 14731 | else if (IS_PINEVIEW(dev_priv)) |
ee9300bb DV |
14732 | dev_priv->display.find_dpll = pnv_find_best_dpll; |
14733 | else | |
14734 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
14735 | ||
88212941 | 14736 | if (INTEL_INFO(dev_priv)->gen >= 9) { |
bc8d7dff | 14737 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14738 | dev_priv->display.get_initial_plane_config = |
14739 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
14740 | dev_priv->display.crtc_compute_clock = |
14741 | haswell_crtc_compute_clock; | |
14742 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
14743 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 14744 | } else if (HAS_DDI(dev_priv)) { |
0e8ffe1b | 14745 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14746 | dev_priv->display.get_initial_plane_config = |
14747 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
14748 | dev_priv->display.crtc_compute_clock = |
14749 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
14750 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
14751 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 14752 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
0e8ffe1b | 14753 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
14754 | dev_priv->display.get_initial_plane_config = |
14755 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
14756 | dev_priv->display.crtc_compute_clock = |
14757 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
14758 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
14759 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
88212941 | 14760 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
89b667f8 | 14761 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14762 | dev_priv->display.get_initial_plane_config = |
14763 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14764 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
89b667f8 JB |
14765 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
14766 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 14767 | } else { |
0e8ffe1b | 14768 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14769 | dev_priv->display.get_initial_plane_config = |
14770 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14771 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
14772 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
14773 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 14774 | } |
e70236a8 | 14775 | |
e70236a8 | 14776 | /* Returns the core display clock speed */ |
88212941 | 14777 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
1652d19e VS |
14778 | dev_priv->display.get_display_clock_speed = |
14779 | skylake_get_display_clock_speed; | |
88212941 | 14780 | else if (IS_BROXTON(dev_priv)) |
acd3f3d3 BP |
14781 | dev_priv->display.get_display_clock_speed = |
14782 | broxton_get_display_clock_speed; | |
88212941 | 14783 | else if (IS_BROADWELL(dev_priv)) |
1652d19e VS |
14784 | dev_priv->display.get_display_clock_speed = |
14785 | broadwell_get_display_clock_speed; | |
88212941 | 14786 | else if (IS_HASWELL(dev_priv)) |
1652d19e VS |
14787 | dev_priv->display.get_display_clock_speed = |
14788 | haswell_get_display_clock_speed; | |
88212941 | 14789 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
25eb05fc JB |
14790 | dev_priv->display.get_display_clock_speed = |
14791 | valleyview_get_display_clock_speed; | |
88212941 | 14792 | else if (IS_GEN5(dev_priv)) |
b37a6434 VS |
14793 | dev_priv->display.get_display_clock_speed = |
14794 | ilk_get_display_clock_speed; | |
88212941 ID |
14795 | else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) || |
14796 | IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) | |
e70236a8 JB |
14797 | dev_priv->display.get_display_clock_speed = |
14798 | i945_get_display_clock_speed; | |
88212941 | 14799 | else if (IS_GM45(dev_priv)) |
34edce2f VS |
14800 | dev_priv->display.get_display_clock_speed = |
14801 | gm45_get_display_clock_speed; | |
88212941 | 14802 | else if (IS_CRESTLINE(dev_priv)) |
34edce2f VS |
14803 | dev_priv->display.get_display_clock_speed = |
14804 | i965gm_get_display_clock_speed; | |
88212941 | 14805 | else if (IS_PINEVIEW(dev_priv)) |
34edce2f VS |
14806 | dev_priv->display.get_display_clock_speed = |
14807 | pnv_get_display_clock_speed; | |
88212941 | 14808 | else if (IS_G33(dev_priv) || IS_G4X(dev_priv)) |
34edce2f VS |
14809 | dev_priv->display.get_display_clock_speed = |
14810 | g33_get_display_clock_speed; | |
88212941 | 14811 | else if (IS_I915G(dev_priv)) |
e70236a8 JB |
14812 | dev_priv->display.get_display_clock_speed = |
14813 | i915_get_display_clock_speed; | |
88212941 | 14814 | else if (IS_I945GM(dev_priv) || IS_845G(dev_priv)) |
e70236a8 JB |
14815 | dev_priv->display.get_display_clock_speed = |
14816 | i9xx_misc_get_display_clock_speed; | |
88212941 | 14817 | else if (IS_I915GM(dev_priv)) |
e70236a8 JB |
14818 | dev_priv->display.get_display_clock_speed = |
14819 | i915gm_get_display_clock_speed; | |
88212941 | 14820 | else if (IS_I865G(dev_priv)) |
e70236a8 JB |
14821 | dev_priv->display.get_display_clock_speed = |
14822 | i865_get_display_clock_speed; | |
88212941 | 14823 | else if (IS_I85X(dev_priv)) |
e70236a8 | 14824 | dev_priv->display.get_display_clock_speed = |
1b1d2716 | 14825 | i85x_get_display_clock_speed; |
623e01e5 | 14826 | else { /* 830 */ |
88212941 | 14827 | WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n"); |
e70236a8 JB |
14828 | dev_priv->display.get_display_clock_speed = |
14829 | i830_get_display_clock_speed; | |
623e01e5 | 14830 | } |
e70236a8 | 14831 | |
88212941 | 14832 | if (IS_GEN5(dev_priv)) { |
3bb11b53 | 14833 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
88212941 | 14834 | } else if (IS_GEN6(dev_priv)) { |
3bb11b53 | 14835 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
88212941 | 14836 | } else if (IS_IVYBRIDGE(dev_priv)) { |
3bb11b53 SJ |
14837 | /* FIXME: detect B0+ stepping and use auto training */ |
14838 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
88212941 | 14839 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
3bb11b53 | 14840 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
88212941 | 14841 | if (IS_BROADWELL(dev_priv)) { |
27c329ed ML |
14842 | dev_priv->display.modeset_commit_cdclk = |
14843 | broadwell_modeset_commit_cdclk; | |
14844 | dev_priv->display.modeset_calc_cdclk = | |
14845 | broadwell_modeset_calc_cdclk; | |
14846 | } | |
88212941 | 14847 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
27c329ed ML |
14848 | dev_priv->display.modeset_commit_cdclk = |
14849 | valleyview_modeset_commit_cdclk; | |
14850 | dev_priv->display.modeset_calc_cdclk = | |
14851 | valleyview_modeset_calc_cdclk; | |
88212941 | 14852 | } else if (IS_BROXTON(dev_priv)) { |
27c329ed ML |
14853 | dev_priv->display.modeset_commit_cdclk = |
14854 | broxton_modeset_commit_cdclk; | |
14855 | dev_priv->display.modeset_calc_cdclk = | |
14856 | broxton_modeset_calc_cdclk; | |
e70236a8 | 14857 | } |
8c9f3aaf | 14858 | |
88212941 | 14859 | switch (INTEL_INFO(dev_priv)->gen) { |
8c9f3aaf JB |
14860 | case 2: |
14861 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
14862 | break; | |
14863 | ||
14864 | case 3: | |
14865 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
14866 | break; | |
14867 | ||
14868 | case 4: | |
14869 | case 5: | |
14870 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
14871 | break; | |
14872 | ||
14873 | case 6: | |
14874 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
14875 | break; | |
7c9017e5 | 14876 | case 7: |
4e0bbc31 | 14877 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
14878 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
14879 | break; | |
830c81db | 14880 | case 9: |
ba343e02 TU |
14881 | /* Drop through - unsupported since execlist only. */ |
14882 | default: | |
14883 | /* Default just returns -ENODEV to indicate unsupported */ | |
14884 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8c9f3aaf | 14885 | } |
e70236a8 JB |
14886 | } |
14887 | ||
b690e96c JB |
14888 | /* |
14889 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
14890 | * resume, or other times. This quirk makes sure that's the case for | |
14891 | * affected systems. | |
14892 | */ | |
0206e353 | 14893 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
14894 | { |
14895 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14896 | ||
14897 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 14898 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
14899 | } |
14900 | ||
b6b5d049 VS |
14901 | static void quirk_pipeb_force(struct drm_device *dev) |
14902 | { | |
14903 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14904 | ||
14905 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
14906 | DRM_INFO("applying pipe b force quirk\n"); | |
14907 | } | |
14908 | ||
435793df KP |
14909 | /* |
14910 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
14911 | */ | |
14912 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
14913 | { | |
14914 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14915 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 14916 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
14917 | } |
14918 | ||
4dca20ef | 14919 | /* |
5a15ab5b CE |
14920 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
14921 | * brightness value | |
4dca20ef CE |
14922 | */ |
14923 | static void quirk_invert_brightness(struct drm_device *dev) | |
14924 | { | |
14925 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14926 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 14927 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
14928 | } |
14929 | ||
9c72cc6f SD |
14930 | /* Some VBT's incorrectly indicate no backlight is present */ |
14931 | static void quirk_backlight_present(struct drm_device *dev) | |
14932 | { | |
14933 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14934 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
14935 | DRM_INFO("applying backlight present quirk\n"); | |
14936 | } | |
14937 | ||
b690e96c JB |
14938 | struct intel_quirk { |
14939 | int device; | |
14940 | int subsystem_vendor; | |
14941 | int subsystem_device; | |
14942 | void (*hook)(struct drm_device *dev); | |
14943 | }; | |
14944 | ||
5f85f176 EE |
14945 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
14946 | struct intel_dmi_quirk { | |
14947 | void (*hook)(struct drm_device *dev); | |
14948 | const struct dmi_system_id (*dmi_id_list)[]; | |
14949 | }; | |
14950 | ||
14951 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
14952 | { | |
14953 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
14954 | return 1; | |
14955 | } | |
14956 | ||
14957 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
14958 | { | |
14959 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
14960 | { | |
14961 | .callback = intel_dmi_reverse_brightness, | |
14962 | .ident = "NCR Corporation", | |
14963 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
14964 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
14965 | }, | |
14966 | }, | |
14967 | { } /* terminating entry */ | |
14968 | }, | |
14969 | .hook = quirk_invert_brightness, | |
14970 | }, | |
14971 | }; | |
14972 | ||
c43b5634 | 14973 | static struct intel_quirk intel_quirks[] = { |
b690e96c JB |
14974 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
14975 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
14976 | ||
b690e96c JB |
14977 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
14978 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
14979 | ||
5f080c0f VS |
14980 | /* 830 needs to leave pipe A & dpll A up */ |
14981 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
14982 | ||
b6b5d049 VS |
14983 | /* 830 needs to leave pipe B & dpll B up */ |
14984 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
14985 | ||
435793df KP |
14986 | /* Lenovo U160 cannot use SSC on LVDS */ |
14987 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
14988 | |
14989 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
14990 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 14991 | |
be505f64 AH |
14992 | /* Acer Aspire 5734Z must invert backlight brightness */ |
14993 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
14994 | ||
14995 | /* Acer/eMachines G725 */ | |
14996 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
14997 | ||
14998 | /* Acer/eMachines e725 */ | |
14999 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
15000 | ||
15001 | /* Acer/Packard Bell NCL20 */ | |
15002 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
15003 | ||
15004 | /* Acer Aspire 4736Z */ | |
15005 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
15006 | |
15007 | /* Acer Aspire 5336 */ | |
15008 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
15009 | |
15010 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
15011 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 15012 | |
dfb3d47b SD |
15013 | /* Acer C720 Chromebook (Core i3 4005U) */ |
15014 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
15015 | ||
b2a9601c | 15016 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
15017 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
15018 | ||
1b9448b0 JN |
15019 | /* Apple Macbook 4,1 */ |
15020 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, | |
15021 | ||
d4967d8c SD |
15022 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
15023 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
15024 | |
15025 | /* HP Chromebook 14 (Celeron 2955U) */ | |
15026 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
15027 | |
15028 | /* Dell Chromebook 11 */ | |
15029 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
9be64eee JN |
15030 | |
15031 | /* Dell Chromebook 11 (2015 version) */ | |
15032 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
15033 | }; |
15034 | ||
15035 | static void intel_init_quirks(struct drm_device *dev) | |
15036 | { | |
15037 | struct pci_dev *d = dev->pdev; | |
15038 | int i; | |
15039 | ||
15040 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
15041 | struct intel_quirk *q = &intel_quirks[i]; | |
15042 | ||
15043 | if (d->device == q->device && | |
15044 | (d->subsystem_vendor == q->subsystem_vendor || | |
15045 | q->subsystem_vendor == PCI_ANY_ID) && | |
15046 | (d->subsystem_device == q->subsystem_device || | |
15047 | q->subsystem_device == PCI_ANY_ID)) | |
15048 | q->hook(dev); | |
15049 | } | |
5f85f176 EE |
15050 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
15051 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
15052 | intel_dmi_quirks[i].hook(dev); | |
15053 | } | |
b690e96c JB |
15054 | } |
15055 | ||
9cce37f4 JB |
15056 | /* Disable the VGA plane that we never use */ |
15057 | static void i915_disable_vga(struct drm_device *dev) | |
15058 | { | |
15059 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15060 | u8 sr1; | |
f0f59a00 | 15061 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 15062 | |
2b37c616 | 15063 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 15064 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 15065 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
15066 | sr1 = inb(VGA_SR_DATA); |
15067 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
15068 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
15069 | udelay(300); | |
15070 | ||
01f5a626 | 15071 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
15072 | POSTING_READ(vga_reg); |
15073 | } | |
15074 | ||
f817586c DV |
15075 | void intel_modeset_init_hw(struct drm_device *dev) |
15076 | { | |
1a617b77 ML |
15077 | struct drm_i915_private *dev_priv = dev->dev_private; |
15078 | ||
b6283055 | 15079 | intel_update_cdclk(dev); |
1a617b77 ML |
15080 | |
15081 | dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq; | |
15082 | ||
f817586c | 15083 | intel_init_clock_gating(dev); |
8090c6b9 | 15084 | intel_enable_gt_powersave(dev); |
f817586c DV |
15085 | } |
15086 | ||
d93c0372 MR |
15087 | /* |
15088 | * Calculate what we think the watermarks should be for the state we've read | |
15089 | * out of the hardware and then immediately program those watermarks so that | |
15090 | * we ensure the hardware settings match our internal state. | |
15091 | * | |
15092 | * We can calculate what we think WM's should be by creating a duplicate of the | |
15093 | * current state (which was constructed during hardware readout) and running it | |
15094 | * through the atomic check code to calculate new watermark values in the | |
15095 | * state object. | |
15096 | */ | |
15097 | static void sanitize_watermarks(struct drm_device *dev) | |
15098 | { | |
15099 | struct drm_i915_private *dev_priv = to_i915(dev); | |
15100 | struct drm_atomic_state *state; | |
15101 | struct drm_crtc *crtc; | |
15102 | struct drm_crtc_state *cstate; | |
15103 | struct drm_modeset_acquire_ctx ctx; | |
15104 | int ret; | |
15105 | int i; | |
15106 | ||
15107 | /* Only supported on platforms that use atomic watermark design */ | |
ed4a6a7c | 15108 | if (!dev_priv->display.optimize_watermarks) |
d93c0372 MR |
15109 | return; |
15110 | ||
15111 | /* | |
15112 | * We need to hold connection_mutex before calling duplicate_state so | |
15113 | * that the connector loop is protected. | |
15114 | */ | |
15115 | drm_modeset_acquire_init(&ctx, 0); | |
15116 | retry: | |
0cd1262d | 15117 | ret = drm_modeset_lock_all_ctx(dev, &ctx); |
d93c0372 MR |
15118 | if (ret == -EDEADLK) { |
15119 | drm_modeset_backoff(&ctx); | |
15120 | goto retry; | |
15121 | } else if (WARN_ON(ret)) { | |
0cd1262d | 15122 | goto fail; |
d93c0372 MR |
15123 | } |
15124 | ||
15125 | state = drm_atomic_helper_duplicate_state(dev, &ctx); | |
15126 | if (WARN_ON(IS_ERR(state))) | |
0cd1262d | 15127 | goto fail; |
d93c0372 | 15128 | |
ed4a6a7c MR |
15129 | /* |
15130 | * Hardware readout is the only time we don't want to calculate | |
15131 | * intermediate watermarks (since we don't trust the current | |
15132 | * watermarks). | |
15133 | */ | |
15134 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
15135 | ||
d93c0372 MR |
15136 | ret = intel_atomic_check(dev, state); |
15137 | if (ret) { | |
15138 | /* | |
15139 | * If we fail here, it means that the hardware appears to be | |
15140 | * programmed in a way that shouldn't be possible, given our | |
15141 | * understanding of watermark requirements. This might mean a | |
15142 | * mistake in the hardware readout code or a mistake in the | |
15143 | * watermark calculations for a given platform. Raise a WARN | |
15144 | * so that this is noticeable. | |
15145 | * | |
15146 | * If this actually happens, we'll have to just leave the | |
15147 | * BIOS-programmed watermarks untouched and hope for the best. | |
15148 | */ | |
15149 | WARN(true, "Could not determine valid watermarks for inherited state\n"); | |
0cd1262d | 15150 | goto fail; |
d93c0372 MR |
15151 | } |
15152 | ||
15153 | /* Write calculated watermark values back */ | |
15154 | to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config; | |
15155 | for_each_crtc_in_state(state, crtc, cstate, i) { | |
15156 | struct intel_crtc_state *cs = to_intel_crtc_state(cstate); | |
15157 | ||
ed4a6a7c MR |
15158 | cs->wm.need_postvbl_update = true; |
15159 | dev_priv->display.optimize_watermarks(cs); | |
d93c0372 MR |
15160 | } |
15161 | ||
15162 | drm_atomic_state_free(state); | |
0cd1262d | 15163 | fail: |
d93c0372 MR |
15164 | drm_modeset_drop_locks(&ctx); |
15165 | drm_modeset_acquire_fini(&ctx); | |
15166 | } | |
15167 | ||
79e53945 JB |
15168 | void intel_modeset_init(struct drm_device *dev) |
15169 | { | |
652c393a | 15170 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 15171 | int sprite, ret; |
8cc87b75 | 15172 | enum pipe pipe; |
46f297fb | 15173 | struct intel_crtc *crtc; |
79e53945 JB |
15174 | |
15175 | drm_mode_config_init(dev); | |
15176 | ||
15177 | dev->mode_config.min_width = 0; | |
15178 | dev->mode_config.min_height = 0; | |
15179 | ||
019d96cb DA |
15180 | dev->mode_config.preferred_depth = 24; |
15181 | dev->mode_config.prefer_shadow = 1; | |
15182 | ||
25bab385 TU |
15183 | dev->mode_config.allow_fb_modifiers = true; |
15184 | ||
e6ecefaa | 15185 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 15186 | |
b690e96c JB |
15187 | intel_init_quirks(dev); |
15188 | ||
1fa61106 ED |
15189 | intel_init_pm(dev); |
15190 | ||
e3c74757 BW |
15191 | if (INTEL_INFO(dev)->num_pipes == 0) |
15192 | return; | |
15193 | ||
69f92f67 LW |
15194 | /* |
15195 | * There may be no VBT; and if the BIOS enabled SSC we can | |
15196 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
15197 | * BIOS isn't using it, don't assume it will work even if the VBT | |
15198 | * indicates as much. | |
15199 | */ | |
15200 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { | |
15201 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
15202 | DREF_SSC1_ENABLE); | |
15203 | ||
15204 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
15205 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
15206 | bios_lvds_use_ssc ? "en" : "dis", | |
15207 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
15208 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
15209 | } | |
15210 | } | |
15211 | ||
a6c45cf0 CW |
15212 | if (IS_GEN2(dev)) { |
15213 | dev->mode_config.max_width = 2048; | |
15214 | dev->mode_config.max_height = 2048; | |
15215 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
15216 | dev->mode_config.max_width = 4096; |
15217 | dev->mode_config.max_height = 4096; | |
79e53945 | 15218 | } else { |
a6c45cf0 CW |
15219 | dev->mode_config.max_width = 8192; |
15220 | dev->mode_config.max_height = 8192; | |
79e53945 | 15221 | } |
068be561 | 15222 | |
dc41c154 VS |
15223 | if (IS_845G(dev) || IS_I865G(dev)) { |
15224 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
15225 | dev->mode_config.cursor_height = 1023; | |
15226 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
15227 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
15228 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
15229 | } else { | |
15230 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
15231 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
15232 | } | |
15233 | ||
62106b4f | 15234 | dev->mode_config.fb_base = dev_priv->ggtt.mappable_base; |
79e53945 | 15235 | |
28c97730 | 15236 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
15237 | INTEL_INFO(dev)->num_pipes, |
15238 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 15239 | |
055e393f | 15240 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 15241 | intel_crtc_init(dev, pipe); |
3bdcfc0c | 15242 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 15243 | ret = intel_plane_init(dev, pipe, sprite); |
7f1f3851 | 15244 | if (ret) |
06da8da2 | 15245 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 15246 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 15247 | } |
79e53945 JB |
15248 | } |
15249 | ||
bfa7df01 | 15250 | intel_update_czclk(dev_priv); |
e7dc33f3 | 15251 | intel_update_rawclk(dev_priv); |
bfa7df01 VS |
15252 | intel_update_cdclk(dev); |
15253 | ||
e72f9fbf | 15254 | intel_shared_dpll_init(dev); |
ee7b9f93 | 15255 | |
9cce37f4 JB |
15256 | /* Just disable it once at startup */ |
15257 | i915_disable_vga(dev); | |
79e53945 | 15258 | intel_setup_outputs(dev); |
11be49eb | 15259 | |
6e9f798d | 15260 | drm_modeset_lock_all(dev); |
043e9bda | 15261 | intel_modeset_setup_hw_state(dev); |
6e9f798d | 15262 | drm_modeset_unlock_all(dev); |
46f297fb | 15263 | |
d3fcc808 | 15264 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
15265 | struct intel_initial_plane_config plane_config = {}; |
15266 | ||
46f297fb JB |
15267 | if (!crtc->active) |
15268 | continue; | |
15269 | ||
46f297fb | 15270 | /* |
46f297fb JB |
15271 | * Note that reserving the BIOS fb up front prevents us |
15272 | * from stuffing other stolen allocations like the ring | |
15273 | * on top. This prevents some ugliness at boot time, and | |
15274 | * can even allow for smooth boot transitions if the BIOS | |
15275 | * fb is large enough for the active pipe configuration. | |
15276 | */ | |
eeebeac5 ML |
15277 | dev_priv->display.get_initial_plane_config(crtc, |
15278 | &plane_config); | |
15279 | ||
15280 | /* | |
15281 | * If the fb is shared between multiple heads, we'll | |
15282 | * just get the first one. | |
15283 | */ | |
15284 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 15285 | } |
d93c0372 MR |
15286 | |
15287 | /* | |
15288 | * Make sure hardware watermarks really match the state we read out. | |
15289 | * Note that we need to do this after reconstructing the BIOS fb's | |
15290 | * since the watermark calculation done here will use pstate->fb. | |
15291 | */ | |
15292 | sanitize_watermarks(dev); | |
2c7111db CW |
15293 | } |
15294 | ||
7fad798e DV |
15295 | static void intel_enable_pipe_a(struct drm_device *dev) |
15296 | { | |
15297 | struct intel_connector *connector; | |
15298 | struct drm_connector *crt = NULL; | |
15299 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 15300 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
15301 | |
15302 | /* We can't just switch on the pipe A, we need to set things up with a | |
15303 | * proper mode and output configuration. As a gross hack, enable pipe A | |
15304 | * by enabling the load detect pipe once. */ | |
3a3371ff | 15305 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
15306 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
15307 | crt = &connector->base; | |
15308 | break; | |
15309 | } | |
15310 | } | |
15311 | ||
15312 | if (!crt) | |
15313 | return; | |
15314 | ||
208bf9fd | 15315 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 15316 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
15317 | } |
15318 | ||
fa555837 DV |
15319 | static bool |
15320 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
15321 | { | |
7eb552ae BW |
15322 | struct drm_device *dev = crtc->base.dev; |
15323 | struct drm_i915_private *dev_priv = dev->dev_private; | |
649636ef | 15324 | u32 val; |
fa555837 | 15325 | |
7eb552ae | 15326 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
15327 | return true; |
15328 | ||
649636ef | 15329 | val = I915_READ(DSPCNTR(!crtc->plane)); |
fa555837 DV |
15330 | |
15331 | if ((val & DISPLAY_PLANE_ENABLE) && | |
15332 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
15333 | return false; | |
15334 | ||
15335 | return true; | |
15336 | } | |
15337 | ||
02e93c35 VS |
15338 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
15339 | { | |
15340 | struct drm_device *dev = crtc->base.dev; | |
15341 | struct intel_encoder *encoder; | |
15342 | ||
15343 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
15344 | return true; | |
15345 | ||
15346 | return false; | |
15347 | } | |
15348 | ||
dd756198 VS |
15349 | static bool intel_encoder_has_connectors(struct intel_encoder *encoder) |
15350 | { | |
15351 | struct drm_device *dev = encoder->base.dev; | |
15352 | struct intel_connector *connector; | |
15353 | ||
15354 | for_each_connector_on_encoder(dev, &encoder->base, connector) | |
15355 | return true; | |
15356 | ||
15357 | return false; | |
15358 | } | |
15359 | ||
24929352 DV |
15360 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
15361 | { | |
15362 | struct drm_device *dev = crtc->base.dev; | |
15363 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4d1de975 | 15364 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
24929352 | 15365 | |
24929352 | 15366 | /* Clear any frame start delays used for debugging left by the BIOS */ |
4d1de975 JN |
15367 | if (!transcoder_is_dsi(cpu_transcoder)) { |
15368 | i915_reg_t reg = PIPECONF(cpu_transcoder); | |
15369 | ||
15370 | I915_WRITE(reg, | |
15371 | I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); | |
15372 | } | |
24929352 | 15373 | |
d3eaf884 | 15374 | /* restore vblank interrupts to correct state */ |
9625604c | 15375 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 15376 | if (crtc->active) { |
f9cd7b88 VS |
15377 | struct intel_plane *plane; |
15378 | ||
9625604c | 15379 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
15380 | |
15381 | /* Disable everything but the primary plane */ | |
15382 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
15383 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
15384 | continue; | |
15385 | ||
15386 | plane->disable_plane(&plane->base, &crtc->base); | |
15387 | } | |
9625604c | 15388 | } |
d3eaf884 | 15389 | |
24929352 | 15390 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
15391 | * disable the crtc (and hence change the state) if it is wrong. Note |
15392 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
15393 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
15394 | bool plane; |
15395 | ||
24929352 DV |
15396 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
15397 | crtc->base.base.id); | |
15398 | ||
15399 | /* Pipe has the wrong plane attached and the plane is active. | |
15400 | * Temporarily change the plane mapping and disable everything | |
15401 | * ... */ | |
15402 | plane = crtc->plane; | |
b70709a6 | 15403 | to_intel_plane_state(crtc->base.primary->state)->visible = true; |
24929352 | 15404 | crtc->plane = !plane; |
b17d48e2 | 15405 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15406 | crtc->plane = plane; |
24929352 | 15407 | } |
24929352 | 15408 | |
7fad798e DV |
15409 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
15410 | crtc->pipe == PIPE_A && !crtc->active) { | |
15411 | /* BIOS forgot to enable pipe A, this mostly happens after | |
15412 | * resume. Force-enable the pipe to fix this, the update_dpms | |
15413 | * call below we restore the pipe to the right state, but leave | |
15414 | * the required bits on. */ | |
15415 | intel_enable_pipe_a(dev); | |
15416 | } | |
15417 | ||
24929352 DV |
15418 | /* Adjust the state of the output pipe according to whether we |
15419 | * have active connectors/encoders. */ | |
842e0307 | 15420 | if (crtc->active && !intel_crtc_has_encoders(crtc)) |
b17d48e2 | 15421 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15422 | |
a3ed6aad | 15423 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
15424 | /* |
15425 | * We start out with underrun reporting disabled to avoid races. | |
15426 | * For correct bookkeeping mark this on active crtcs. | |
15427 | * | |
c5ab3bc0 DV |
15428 | * Also on gmch platforms we dont have any hardware bits to |
15429 | * disable the underrun reporting. Which means we need to start | |
15430 | * out with underrun reporting disabled also on inactive pipes, | |
15431 | * since otherwise we'll complain about the garbage we read when | |
15432 | * e.g. coming up after runtime pm. | |
15433 | * | |
4cc31489 DV |
15434 | * No protection against concurrent access is required - at |
15435 | * worst a fifo underrun happens which also sets this to false. | |
15436 | */ | |
15437 | crtc->cpu_fifo_underrun_disabled = true; | |
15438 | crtc->pch_fifo_underrun_disabled = true; | |
15439 | } | |
24929352 DV |
15440 | } |
15441 | ||
15442 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
15443 | { | |
15444 | struct intel_connector *connector; | |
15445 | struct drm_device *dev = encoder->base.dev; | |
15446 | ||
15447 | /* We need to check both for a crtc link (meaning that the | |
15448 | * encoder is active and trying to read from a pipe) and the | |
15449 | * pipe itself being active. */ | |
15450 | bool has_active_crtc = encoder->base.crtc && | |
15451 | to_intel_crtc(encoder->base.crtc)->active; | |
15452 | ||
dd756198 | 15453 | if (intel_encoder_has_connectors(encoder) && !has_active_crtc) { |
24929352 DV |
15454 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
15455 | encoder->base.base.id, | |
8e329a03 | 15456 | encoder->base.name); |
24929352 DV |
15457 | |
15458 | /* Connector is active, but has no active pipe. This is | |
15459 | * fallout from our resume register restoring. Disable | |
15460 | * the encoder manually again. */ | |
15461 | if (encoder->base.crtc) { | |
15462 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
15463 | encoder->base.base.id, | |
8e329a03 | 15464 | encoder->base.name); |
24929352 | 15465 | encoder->disable(encoder); |
a62d1497 VS |
15466 | if (encoder->post_disable) |
15467 | encoder->post_disable(encoder); | |
24929352 | 15468 | } |
7f1950fb | 15469 | encoder->base.crtc = NULL; |
24929352 DV |
15470 | |
15471 | /* Inconsistent output/port/pipe state happens presumably due to | |
15472 | * a bug in one of the get_hw_state functions. Or someplace else | |
15473 | * in our code, like the register restore mess on resume. Clamp | |
15474 | * things to off as a safer default. */ | |
3a3371ff | 15475 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15476 | if (connector->encoder != encoder) |
15477 | continue; | |
7f1950fb EE |
15478 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
15479 | connector->base.encoder = NULL; | |
24929352 DV |
15480 | } |
15481 | } | |
15482 | /* Enabled encoders without active connectors will be fixed in | |
15483 | * the crtc fixup. */ | |
15484 | } | |
15485 | ||
04098753 | 15486 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
15487 | { |
15488 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 15489 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 15490 | |
04098753 ID |
15491 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
15492 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
15493 | i915_disable_vga(dev); | |
15494 | } | |
15495 | } | |
15496 | ||
15497 | void i915_redisable_vga(struct drm_device *dev) | |
15498 | { | |
15499 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15500 | ||
8dc8a27c PZ |
15501 | /* This function can be called both from intel_modeset_setup_hw_state or |
15502 | * at a very early point in our resume sequence, where the power well | |
15503 | * structures are not yet restored. Since this function is at a very | |
15504 | * paranoid "someone might have enabled VGA while we were not looking" | |
15505 | * level, just check if the power well is enabled instead of trying to | |
15506 | * follow the "don't touch the power well if we don't need it" policy | |
15507 | * the rest of the driver uses. */ | |
6392f847 | 15508 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
15509 | return; |
15510 | ||
04098753 | 15511 | i915_redisable_vga_power_on(dev); |
6392f847 ID |
15512 | |
15513 | intel_display_power_put(dev_priv, POWER_DOMAIN_VGA); | |
0fde901f KM |
15514 | } |
15515 | ||
f9cd7b88 | 15516 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 15517 | { |
f9cd7b88 | 15518 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 15519 | |
f9cd7b88 | 15520 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
15521 | } |
15522 | ||
f9cd7b88 VS |
15523 | /* FIXME read out full plane state for all planes */ |
15524 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 15525 | { |
b26d3ea3 | 15526 | struct drm_plane *primary = crtc->base.primary; |
f9cd7b88 | 15527 | struct intel_plane_state *plane_state = |
b26d3ea3 | 15528 | to_intel_plane_state(primary->state); |
d032ffa0 | 15529 | |
19b8d387 | 15530 | plane_state->visible = crtc->active && |
b26d3ea3 ML |
15531 | primary_get_hw_state(to_intel_plane(primary)); |
15532 | ||
15533 | if (plane_state->visible) | |
15534 | crtc->base.state->plane_mask |= 1 << drm_plane_index(primary); | |
98ec7739 VS |
15535 | } |
15536 | ||
30e984df | 15537 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
15538 | { |
15539 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15540 | enum pipe pipe; | |
24929352 DV |
15541 | struct intel_crtc *crtc; |
15542 | struct intel_encoder *encoder; | |
15543 | struct intel_connector *connector; | |
5358901f | 15544 | int i; |
24929352 | 15545 | |
565602d7 ML |
15546 | dev_priv->active_crtcs = 0; |
15547 | ||
d3fcc808 | 15548 | for_each_intel_crtc(dev, crtc) { |
565602d7 ML |
15549 | struct intel_crtc_state *crtc_state = crtc->config; |
15550 | int pixclk = 0; | |
3b117c8f | 15551 | |
565602d7 ML |
15552 | __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base); |
15553 | memset(crtc_state, 0, sizeof(*crtc_state)); | |
15554 | crtc_state->base.crtc = &crtc->base; | |
24929352 | 15555 | |
565602d7 ML |
15556 | crtc_state->base.active = crtc_state->base.enable = |
15557 | dev_priv->display.get_pipe_config(crtc, crtc_state); | |
15558 | ||
15559 | crtc->base.enabled = crtc_state->base.enable; | |
15560 | crtc->active = crtc_state->base.active; | |
15561 | ||
15562 | if (crtc_state->base.active) { | |
15563 | dev_priv->active_crtcs |= 1 << crtc->pipe; | |
15564 | ||
15565 | if (IS_BROADWELL(dev_priv)) { | |
15566 | pixclk = ilk_pipe_pixel_rate(crtc_state); | |
15567 | ||
15568 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
15569 | if (crtc_state->ips_enabled) | |
15570 | pixclk = DIV_ROUND_UP(pixclk * 100, 95); | |
15571 | } else if (IS_VALLEYVIEW(dev_priv) || | |
15572 | IS_CHERRYVIEW(dev_priv) || | |
15573 | IS_BROXTON(dev_priv)) | |
15574 | pixclk = crtc_state->base.adjusted_mode.crtc_clock; | |
15575 | else | |
15576 | WARN_ON(dev_priv->display.modeset_calc_cdclk); | |
15577 | } | |
15578 | ||
15579 | dev_priv->min_pixclk[crtc->pipe] = pixclk; | |
b70709a6 | 15580 | |
f9cd7b88 | 15581 | readout_plane_state(crtc); |
24929352 DV |
15582 | |
15583 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
15584 | crtc->base.base.id, | |
15585 | crtc->active ? "enabled" : "disabled"); | |
15586 | } | |
15587 | ||
5358901f DV |
15588 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15589 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15590 | ||
2edd6443 ACO |
15591 | pll->on = pll->funcs.get_hw_state(dev_priv, pll, |
15592 | &pll->config.hw_state); | |
3e369b76 | 15593 | pll->config.crtc_mask = 0; |
d3fcc808 | 15594 | for_each_intel_crtc(dev, crtc) { |
2dd66ebd | 15595 | if (crtc->active && crtc->config->shared_dpll == pll) |
3e369b76 | 15596 | pll->config.crtc_mask |= 1 << crtc->pipe; |
5358901f | 15597 | } |
2dd66ebd | 15598 | pll->active_mask = pll->config.crtc_mask; |
5358901f | 15599 | |
1e6f2ddc | 15600 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 15601 | pll->name, pll->config.crtc_mask, pll->on); |
5358901f DV |
15602 | } |
15603 | ||
b2784e15 | 15604 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15605 | pipe = 0; |
15606 | ||
15607 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
15608 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15609 | encoder->base.crtc = &crtc->base; | |
6e3c9717 | 15610 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
15611 | } else { |
15612 | encoder->base.crtc = NULL; | |
15613 | } | |
15614 | ||
6f2bcceb | 15615 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 15616 | encoder->base.base.id, |
8e329a03 | 15617 | encoder->base.name, |
24929352 | 15618 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 15619 | pipe_name(pipe)); |
24929352 DV |
15620 | } |
15621 | ||
3a3371ff | 15622 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15623 | if (connector->get_hw_state(connector)) { |
15624 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
2aa974c9 ML |
15625 | |
15626 | encoder = connector->encoder; | |
15627 | connector->base.encoder = &encoder->base; | |
15628 | ||
15629 | if (encoder->base.crtc && | |
15630 | encoder->base.crtc->state->active) { | |
15631 | /* | |
15632 | * This has to be done during hardware readout | |
15633 | * because anything calling .crtc_disable may | |
15634 | * rely on the connector_mask being accurate. | |
15635 | */ | |
15636 | encoder->base.crtc->state->connector_mask |= | |
15637 | 1 << drm_connector_index(&connector->base); | |
e87a52b3 ML |
15638 | encoder->base.crtc->state->encoder_mask |= |
15639 | 1 << drm_encoder_index(&encoder->base); | |
2aa974c9 ML |
15640 | } |
15641 | ||
24929352 DV |
15642 | } else { |
15643 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
15644 | connector->base.encoder = NULL; | |
15645 | } | |
15646 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
15647 | connector->base.base.id, | |
c23cc417 | 15648 | connector->base.name, |
24929352 DV |
15649 | connector->base.encoder ? "enabled" : "disabled"); |
15650 | } | |
7f4c6284 VS |
15651 | |
15652 | for_each_intel_crtc(dev, crtc) { | |
15653 | crtc->base.hwmode = crtc->config->base.adjusted_mode; | |
15654 | ||
15655 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); | |
15656 | if (crtc->base.state->active) { | |
15657 | intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); | |
15658 | intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config); | |
15659 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); | |
15660 | ||
15661 | /* | |
15662 | * The initial mode needs to be set in order to keep | |
15663 | * the atomic core happy. It wants a valid mode if the | |
15664 | * crtc's enabled, so we do the above call. | |
15665 | * | |
15666 | * At this point some state updated by the connectors | |
15667 | * in their ->detect() callback has not run yet, so | |
15668 | * no recalculation can be done yet. | |
15669 | * | |
15670 | * Even if we could do a recalculation and modeset | |
15671 | * right now it would cause a double modeset if | |
15672 | * fbdev or userspace chooses a different initial mode. | |
15673 | * | |
15674 | * If that happens, someone indicated they wanted a | |
15675 | * mode change, which means it's safe to do a full | |
15676 | * recalculation. | |
15677 | */ | |
15678 | crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED; | |
9eca6832 VS |
15679 | |
15680 | drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); | |
15681 | update_scanline_offset(crtc); | |
7f4c6284 | 15682 | } |
e3b247da VS |
15683 | |
15684 | intel_pipe_config_sanity_check(dev_priv, crtc->config); | |
7f4c6284 | 15685 | } |
30e984df DV |
15686 | } |
15687 | ||
043e9bda ML |
15688 | /* Scan out the current hw modeset state, |
15689 | * and sanitizes it to the current state | |
15690 | */ | |
15691 | static void | |
15692 | intel_modeset_setup_hw_state(struct drm_device *dev) | |
30e984df DV |
15693 | { |
15694 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15695 | enum pipe pipe; | |
30e984df DV |
15696 | struct intel_crtc *crtc; |
15697 | struct intel_encoder *encoder; | |
35c95375 | 15698 | int i; |
30e984df DV |
15699 | |
15700 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
15701 | |
15702 | /* HW state is read out, now we need to sanitize this mess. */ | |
b2784e15 | 15703 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15704 | intel_sanitize_encoder(encoder); |
15705 | } | |
15706 | ||
055e393f | 15707 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
15708 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15709 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
15710 | intel_dump_pipe_config(crtc, crtc->config, |
15711 | "[setup_hw_state]"); | |
24929352 | 15712 | } |
9a935856 | 15713 | |
d29b2f9d ACO |
15714 | intel_modeset_update_connector_atomic_state(dev); |
15715 | ||
35c95375 DV |
15716 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15717 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15718 | ||
2dd66ebd | 15719 | if (!pll->on || pll->active_mask) |
35c95375 DV |
15720 | continue; |
15721 | ||
15722 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
15723 | ||
2edd6443 | 15724 | pll->funcs.disable(dev_priv, pll); |
35c95375 DV |
15725 | pll->on = false; |
15726 | } | |
15727 | ||
666a4537 | 15728 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
6eb1a681 VS |
15729 | vlv_wm_get_hw_state(dev); |
15730 | else if (IS_GEN9(dev)) | |
3078999f PB |
15731 | skl_wm_get_hw_state(dev); |
15732 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 | 15733 | ilk_wm_get_hw_state(dev); |
292b990e ML |
15734 | |
15735 | for_each_intel_crtc(dev, crtc) { | |
15736 | unsigned long put_domains; | |
15737 | ||
74bff5f9 | 15738 | put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config); |
292b990e ML |
15739 | if (WARN_ON(put_domains)) |
15740 | modeset_put_power_domains(dev_priv, put_domains); | |
15741 | } | |
15742 | intel_display_set_init_power(dev_priv, false); | |
010cf73d PZ |
15743 | |
15744 | intel_fbc_init_pipe_state(dev_priv); | |
043e9bda | 15745 | } |
7d0bc1ea | 15746 | |
043e9bda ML |
15747 | void intel_display_resume(struct drm_device *dev) |
15748 | { | |
e2c8b870 ML |
15749 | struct drm_i915_private *dev_priv = to_i915(dev); |
15750 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
15751 | struct drm_modeset_acquire_ctx ctx; | |
043e9bda | 15752 | int ret; |
e2c8b870 | 15753 | bool setup = false; |
f30da187 | 15754 | |
e2c8b870 | 15755 | dev_priv->modeset_restore_state = NULL; |
043e9bda | 15756 | |
ea49c9ac ML |
15757 | /* |
15758 | * This is a cludge because with real atomic modeset mode_config.mutex | |
15759 | * won't be taken. Unfortunately some probed state like | |
15760 | * audio_codec_enable is still protected by mode_config.mutex, so lock | |
15761 | * it here for now. | |
15762 | */ | |
15763 | mutex_lock(&dev->mode_config.mutex); | |
e2c8b870 | 15764 | drm_modeset_acquire_init(&ctx, 0); |
043e9bda | 15765 | |
e2c8b870 ML |
15766 | retry: |
15767 | ret = drm_modeset_lock_all_ctx(dev, &ctx); | |
043e9bda | 15768 | |
e2c8b870 ML |
15769 | if (ret == 0 && !setup) { |
15770 | setup = true; | |
043e9bda | 15771 | |
e2c8b870 ML |
15772 | intel_modeset_setup_hw_state(dev); |
15773 | i915_redisable_vga(dev); | |
45e2b5f6 | 15774 | } |
8af6cf88 | 15775 | |
e2c8b870 ML |
15776 | if (ret == 0 && state) { |
15777 | struct drm_crtc_state *crtc_state; | |
15778 | struct drm_crtc *crtc; | |
15779 | int i; | |
043e9bda | 15780 | |
e2c8b870 ML |
15781 | state->acquire_ctx = &ctx; |
15782 | ||
15783 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
15784 | /* | |
15785 | * Force recalculation even if we restore | |
15786 | * current state. With fast modeset this may not result | |
15787 | * in a modeset when the state is compatible. | |
15788 | */ | |
15789 | crtc_state->mode_changed = true; | |
15790 | } | |
15791 | ||
15792 | ret = drm_atomic_commit(state); | |
043e9bda ML |
15793 | } |
15794 | ||
e2c8b870 ML |
15795 | if (ret == -EDEADLK) { |
15796 | drm_modeset_backoff(&ctx); | |
15797 | goto retry; | |
15798 | } | |
043e9bda | 15799 | |
e2c8b870 ML |
15800 | drm_modeset_drop_locks(&ctx); |
15801 | drm_modeset_acquire_fini(&ctx); | |
ea49c9ac | 15802 | mutex_unlock(&dev->mode_config.mutex); |
043e9bda | 15803 | |
e2c8b870 ML |
15804 | if (ret) { |
15805 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
15806 | drm_atomic_state_free(state); | |
15807 | } | |
2c7111db CW |
15808 | } |
15809 | ||
15810 | void intel_modeset_gem_init(struct drm_device *dev) | |
15811 | { | |
484b41dd | 15812 | struct drm_crtc *c; |
2ff8fde1 | 15813 | struct drm_i915_gem_object *obj; |
e0d6149b | 15814 | int ret; |
484b41dd | 15815 | |
ae48434c | 15816 | intel_init_gt_powersave(dev); |
ae48434c | 15817 | |
1833b134 | 15818 | intel_modeset_init_hw(dev); |
02e792fb DV |
15819 | |
15820 | intel_setup_overlay(dev); | |
484b41dd JB |
15821 | |
15822 | /* | |
15823 | * Make sure any fbs we allocated at startup are properly | |
15824 | * pinned & fenced. When we do the allocation it's too early | |
15825 | * for this. | |
15826 | */ | |
70e1e0ec | 15827 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
15828 | obj = intel_fb_obj(c->primary->fb); |
15829 | if (obj == NULL) | |
484b41dd JB |
15830 | continue; |
15831 | ||
e0d6149b | 15832 | mutex_lock(&dev->struct_mutex); |
3465c580 VS |
15833 | ret = intel_pin_and_fence_fb_obj(c->primary->fb, |
15834 | c->primary->state->rotation); | |
e0d6149b TU |
15835 | mutex_unlock(&dev->struct_mutex); |
15836 | if (ret) { | |
484b41dd JB |
15837 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
15838 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
15839 | drm_framebuffer_unreference(c->primary->fb); |
15840 | c->primary->fb = NULL; | |
36750f28 | 15841 | c->primary->crtc = c->primary->state->crtc = NULL; |
afd65eb4 | 15842 | update_state_fb(c->primary); |
36750f28 | 15843 | c->state->plane_mask &= ~(1 << drm_plane_index(c->primary)); |
484b41dd JB |
15844 | } |
15845 | } | |
0962c3c9 VS |
15846 | |
15847 | intel_backlight_register(dev); | |
79e53945 JB |
15848 | } |
15849 | ||
4932e2c3 ID |
15850 | void intel_connector_unregister(struct intel_connector *intel_connector) |
15851 | { | |
15852 | struct drm_connector *connector = &intel_connector->base; | |
15853 | ||
15854 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 15855 | drm_connector_unregister(connector); |
4932e2c3 ID |
15856 | } |
15857 | ||
79e53945 JB |
15858 | void intel_modeset_cleanup(struct drm_device *dev) |
15859 | { | |
652c393a | 15860 | struct drm_i915_private *dev_priv = dev->dev_private; |
19c8054c | 15861 | struct intel_connector *connector; |
652c393a | 15862 | |
2eb5252e ID |
15863 | intel_disable_gt_powersave(dev); |
15864 | ||
0962c3c9 VS |
15865 | intel_backlight_unregister(dev); |
15866 | ||
fd0c0642 DV |
15867 | /* |
15868 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 15869 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
15870 | * experience fancy races otherwise. |
15871 | */ | |
2aeb7d3a | 15872 | intel_irq_uninstall(dev_priv); |
eb21b92b | 15873 | |
fd0c0642 DV |
15874 | /* |
15875 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
15876 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
15877 | */ | |
f87ea761 | 15878 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 15879 | |
723bfd70 JB |
15880 | intel_unregister_dsm_handler(); |
15881 | ||
c937ab3e | 15882 | intel_fbc_global_disable(dev_priv); |
69341a5e | 15883 | |
1630fe75 CW |
15884 | /* flush any delayed tasks or pending work */ |
15885 | flush_scheduled_work(); | |
15886 | ||
db31af1d | 15887 | /* destroy the backlight and sysfs files before encoders/connectors */ |
19c8054c JN |
15888 | for_each_intel_connector(dev, connector) |
15889 | connector->unregister(connector); | |
d9255d57 | 15890 | |
79e53945 | 15891 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
15892 | |
15893 | intel_cleanup_overlay(dev); | |
ae48434c | 15894 | |
ae48434c | 15895 | intel_cleanup_gt_powersave(dev); |
f5949141 DV |
15896 | |
15897 | intel_teardown_gmbus(dev); | |
79e53945 JB |
15898 | } |
15899 | ||
f1c79df3 ZW |
15900 | /* |
15901 | * Return which encoder is currently attached for connector. | |
15902 | */ | |
df0e9248 | 15903 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 15904 | { |
df0e9248 CW |
15905 | return &intel_attached_encoder(connector)->base; |
15906 | } | |
f1c79df3 | 15907 | |
df0e9248 CW |
15908 | void intel_connector_attach_encoder(struct intel_connector *connector, |
15909 | struct intel_encoder *encoder) | |
15910 | { | |
15911 | connector->encoder = encoder; | |
15912 | drm_mode_connector_attach_encoder(&connector->base, | |
15913 | &encoder->base); | |
79e53945 | 15914 | } |
28d52043 DA |
15915 | |
15916 | /* | |
15917 | * set vga decode state - true == enable VGA decode | |
15918 | */ | |
15919 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
15920 | { | |
15921 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 15922 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
15923 | u16 gmch_ctrl; |
15924 | ||
75fa041d CW |
15925 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
15926 | DRM_ERROR("failed to read control word\n"); | |
15927 | return -EIO; | |
15928 | } | |
15929 | ||
c0cc8a55 CW |
15930 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
15931 | return 0; | |
15932 | ||
28d52043 DA |
15933 | if (state) |
15934 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
15935 | else | |
15936 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
15937 | |
15938 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
15939 | DRM_ERROR("failed to write control word\n"); | |
15940 | return -EIO; | |
15941 | } | |
15942 | ||
28d52043 DA |
15943 | return 0; |
15944 | } | |
c4a1d9e4 | 15945 | |
c4a1d9e4 | 15946 | struct intel_display_error_state { |
ff57f1b0 PZ |
15947 | |
15948 | u32 power_well_driver; | |
15949 | ||
63b66e5b CW |
15950 | int num_transcoders; |
15951 | ||
c4a1d9e4 CW |
15952 | struct intel_cursor_error_state { |
15953 | u32 control; | |
15954 | u32 position; | |
15955 | u32 base; | |
15956 | u32 size; | |
52331309 | 15957 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15958 | |
15959 | struct intel_pipe_error_state { | |
ddf9c536 | 15960 | bool power_domain_on; |
c4a1d9e4 | 15961 | u32 source; |
f301b1e1 | 15962 | u32 stat; |
52331309 | 15963 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15964 | |
15965 | struct intel_plane_error_state { | |
15966 | u32 control; | |
15967 | u32 stride; | |
15968 | u32 size; | |
15969 | u32 pos; | |
15970 | u32 addr; | |
15971 | u32 surface; | |
15972 | u32 tile_offset; | |
52331309 | 15973 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
15974 | |
15975 | struct intel_transcoder_error_state { | |
ddf9c536 | 15976 | bool power_domain_on; |
63b66e5b CW |
15977 | enum transcoder cpu_transcoder; |
15978 | ||
15979 | u32 conf; | |
15980 | ||
15981 | u32 htotal; | |
15982 | u32 hblank; | |
15983 | u32 hsync; | |
15984 | u32 vtotal; | |
15985 | u32 vblank; | |
15986 | u32 vsync; | |
15987 | } transcoder[4]; | |
c4a1d9e4 CW |
15988 | }; |
15989 | ||
15990 | struct intel_display_error_state * | |
15991 | intel_display_capture_error_state(struct drm_device *dev) | |
15992 | { | |
fbee40df | 15993 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 15994 | struct intel_display_error_state *error; |
63b66e5b CW |
15995 | int transcoders[] = { |
15996 | TRANSCODER_A, | |
15997 | TRANSCODER_B, | |
15998 | TRANSCODER_C, | |
15999 | TRANSCODER_EDP, | |
16000 | }; | |
c4a1d9e4 CW |
16001 | int i; |
16002 | ||
63b66e5b CW |
16003 | if (INTEL_INFO(dev)->num_pipes == 0) |
16004 | return NULL; | |
16005 | ||
9d1cb914 | 16006 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
16007 | if (error == NULL) |
16008 | return NULL; | |
16009 | ||
190be112 | 16010 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
16011 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
16012 | ||
055e393f | 16013 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 16014 | error->pipe[i].power_domain_on = |
f458ebbc DV |
16015 | __intel_display_power_is_enabled(dev_priv, |
16016 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 16017 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
16018 | continue; |
16019 | ||
5efb3e28 VS |
16020 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
16021 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
16022 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
16023 | |
16024 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
16025 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 16026 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 16027 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
16028 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
16029 | } | |
ca291363 PZ |
16030 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
16031 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
16032 | if (INTEL_INFO(dev)->gen >= 4) { |
16033 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
16034 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
16035 | } | |
16036 | ||
c4a1d9e4 | 16037 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 16038 | |
3abfce77 | 16039 | if (HAS_GMCH_DISPLAY(dev)) |
f301b1e1 | 16040 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
16041 | } |
16042 | ||
4d1de975 | 16043 | /* Note: this does not include DSI transcoders. */ |
63b66e5b CW |
16044 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; |
16045 | if (HAS_DDI(dev_priv->dev)) | |
16046 | error->num_transcoders++; /* Account for eDP. */ | |
16047 | ||
16048 | for (i = 0; i < error->num_transcoders; i++) { | |
16049 | enum transcoder cpu_transcoder = transcoders[i]; | |
16050 | ||
ddf9c536 | 16051 | error->transcoder[i].power_domain_on = |
f458ebbc | 16052 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 16053 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 16054 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
16055 | continue; |
16056 | ||
63b66e5b CW |
16057 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
16058 | ||
16059 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
16060 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
16061 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
16062 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
16063 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
16064 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
16065 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
16066 | } |
16067 | ||
16068 | return error; | |
16069 | } | |
16070 | ||
edc3d884 MK |
16071 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
16072 | ||
c4a1d9e4 | 16073 | void |
edc3d884 | 16074 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
16075 | struct drm_device *dev, |
16076 | struct intel_display_error_state *error) | |
16077 | { | |
055e393f | 16078 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
16079 | int i; |
16080 | ||
63b66e5b CW |
16081 | if (!error) |
16082 | return; | |
16083 | ||
edc3d884 | 16084 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 16085 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 16086 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 16087 | error->power_well_driver); |
055e393f | 16088 | for_each_pipe(dev_priv, i) { |
edc3d884 | 16089 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 | 16090 | err_printf(m, " Power: %s\n", |
87ad3212 | 16091 | onoff(error->pipe[i].power_domain_on)); |
edc3d884 | 16092 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 16093 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
16094 | |
16095 | err_printf(m, "Plane [%d]:\n", i); | |
16096 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
16097 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 16098 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
16099 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
16100 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 16101 | } |
4b71a570 | 16102 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 16103 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 16104 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
16105 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
16106 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
16107 | } |
16108 | ||
edc3d884 MK |
16109 | err_printf(m, "Cursor [%d]:\n", i); |
16110 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
16111 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
16112 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 16113 | } |
63b66e5b CW |
16114 | |
16115 | for (i = 0; i < error->num_transcoders; i++) { | |
da205630 | 16116 | err_printf(m, "CPU transcoder: %s\n", |
63b66e5b | 16117 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 | 16118 | err_printf(m, " Power: %s\n", |
87ad3212 | 16119 | onoff(error->transcoder[i].power_domain_on)); |
63b66e5b CW |
16120 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
16121 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
16122 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
16123 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
16124 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
16125 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
16126 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
16127 | } | |
c4a1d9e4 | 16128 | } |