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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
319c1d42 | 40 | #include <drm/drm_atomic.h> |
c196e1d6 | 41 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
42 | #include <drm/drm_dp_helper.h> |
43 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
44 | #include <drm/drm_plane_helper.h> |
45 | #include <drm/drm_rect.h> | |
c0f372b3 | 46 | #include <linux/dma_remapping.h> |
79e53945 | 47 | |
465c120c | 48 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 49 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
50 | DRM_FORMAT_C8, |
51 | DRM_FORMAT_RGB565, | |
465c120c | 52 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 53 | DRM_FORMAT_XRGB8888, |
465c120c MR |
54 | }; |
55 | ||
56 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 57 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
58 | DRM_FORMAT_C8, |
59 | DRM_FORMAT_RGB565, | |
60 | DRM_FORMAT_XRGB8888, | |
61 | DRM_FORMAT_XBGR8888, | |
62 | DRM_FORMAT_XRGB2101010, | |
63 | DRM_FORMAT_XBGR2101010, | |
64 | }; | |
65 | ||
66 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
67 | DRM_FORMAT_C8, |
68 | DRM_FORMAT_RGB565, | |
69 | DRM_FORMAT_XRGB8888, | |
465c120c | 70 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 71 | DRM_FORMAT_ARGB8888, |
465c120c MR |
72 | DRM_FORMAT_ABGR8888, |
73 | DRM_FORMAT_XRGB2101010, | |
465c120c | 74 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
75 | DRM_FORMAT_YUYV, |
76 | DRM_FORMAT_YVYU, | |
77 | DRM_FORMAT_UYVY, | |
78 | DRM_FORMAT_VYUY, | |
465c120c MR |
79 | }; |
80 | ||
3d7d6510 MR |
81 | /* Cursor formats */ |
82 | static const uint32_t intel_cursor_formats[] = { | |
83 | DRM_FORMAT_ARGB8888, | |
84 | }; | |
85 | ||
6b383a7f | 86 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 87 | |
f1f644dc | 88 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 89 | struct intel_crtc_state *pipe_config); |
18442d08 | 90 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 91 | struct intel_crtc_state *pipe_config); |
f1f644dc | 92 | |
eb1bfe80 JB |
93 | static int intel_framebuffer_init(struct drm_device *dev, |
94 | struct intel_framebuffer *ifb, | |
95 | struct drm_mode_fb_cmd2 *mode_cmd, | |
96 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
97 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
98 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
29407aab | 99 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
100 | struct intel_link_m_n *m_n, |
101 | struct intel_link_m_n *m2_n2); | |
29407aab | 102 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 DV |
103 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
104 | static void intel_set_pipe_csc(struct drm_crtc *crtc); | |
d288f65f | 105 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 106 | const struct intel_crtc_state *pipe_config); |
d288f65f | 107 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 108 | const struct intel_crtc_state *pipe_config); |
613d2b27 ML |
109 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
110 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
549e2bfb CK |
111 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
112 | struct intel_crtc_state *crtc_state); | |
5ab7b0b7 ID |
113 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
114 | int num_connectors); | |
bfd16b2a ML |
115 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
116 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
117 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
043e9bda | 118 | static void intel_modeset_setup_hw_state(struct drm_device *dev); |
e7457a9a | 119 | |
79e53945 | 120 | typedef struct { |
0206e353 | 121 | int min, max; |
79e53945 JB |
122 | } intel_range_t; |
123 | ||
124 | typedef struct { | |
0206e353 AJ |
125 | int dot_limit; |
126 | int p2_slow, p2_fast; | |
79e53945 JB |
127 | } intel_p2_t; |
128 | ||
d4906093 ML |
129 | typedef struct intel_limit intel_limit_t; |
130 | struct intel_limit { | |
0206e353 AJ |
131 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
132 | intel_p2_t p2; | |
d4906093 | 133 | }; |
79e53945 | 134 | |
bfa7df01 VS |
135 | /* returns HPLL frequency in kHz */ |
136 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) | |
137 | { | |
138 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
139 | ||
140 | /* Obtain SKU information */ | |
141 | mutex_lock(&dev_priv->sb_lock); | |
142 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
143 | CCK_FUSE_HPLL_FREQ_MASK; | |
144 | mutex_unlock(&dev_priv->sb_lock); | |
145 | ||
146 | return vco_freq[hpll_freq] * 1000; | |
147 | } | |
148 | ||
149 | static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, | |
150 | const char *name, u32 reg) | |
151 | { | |
152 | u32 val; | |
153 | int divider; | |
154 | ||
155 | if (dev_priv->hpll_freq == 0) | |
156 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
157 | ||
158 | mutex_lock(&dev_priv->sb_lock); | |
159 | val = vlv_cck_read(dev_priv, reg); | |
160 | mutex_unlock(&dev_priv->sb_lock); | |
161 | ||
162 | divider = val & CCK_FREQUENCY_VALUES; | |
163 | ||
164 | WARN((val & CCK_FREQUENCY_STATUS) != | |
165 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
166 | "%s change in progress\n", name); | |
167 | ||
168 | return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); | |
169 | } | |
170 | ||
d2acd215 DV |
171 | int |
172 | intel_pch_rawclk(struct drm_device *dev) | |
173 | { | |
174 | struct drm_i915_private *dev_priv = dev->dev_private; | |
175 | ||
176 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
177 | ||
178 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
179 | } | |
180 | ||
79e50a4f JN |
181 | /* hrawclock is 1/4 the FSB frequency */ |
182 | int intel_hrawclk(struct drm_device *dev) | |
183 | { | |
184 | struct drm_i915_private *dev_priv = dev->dev_private; | |
185 | uint32_t clkcfg; | |
186 | ||
187 | /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ | |
188 | if (IS_VALLEYVIEW(dev)) | |
189 | return 200; | |
190 | ||
191 | clkcfg = I915_READ(CLKCFG); | |
192 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
193 | case CLKCFG_FSB_400: | |
194 | return 100; | |
195 | case CLKCFG_FSB_533: | |
196 | return 133; | |
197 | case CLKCFG_FSB_667: | |
198 | return 166; | |
199 | case CLKCFG_FSB_800: | |
200 | return 200; | |
201 | case CLKCFG_FSB_1067: | |
202 | return 266; | |
203 | case CLKCFG_FSB_1333: | |
204 | return 333; | |
205 | /* these two are just a guess; one of them might be right */ | |
206 | case CLKCFG_FSB_1600: | |
207 | case CLKCFG_FSB_1600_ALT: | |
208 | return 400; | |
209 | default: | |
210 | return 133; | |
211 | } | |
212 | } | |
213 | ||
bfa7df01 VS |
214 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
215 | { | |
216 | if (!IS_VALLEYVIEW(dev_priv)) | |
217 | return; | |
218 | ||
219 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
220 | CCK_CZ_CLOCK_CONTROL); | |
221 | ||
222 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); | |
223 | } | |
224 | ||
021357ac CW |
225 | static inline u32 /* units of 100MHz */ |
226 | intel_fdi_link_freq(struct drm_device *dev) | |
227 | { | |
8b99e68c CW |
228 | if (IS_GEN5(dev)) { |
229 | struct drm_i915_private *dev_priv = dev->dev_private; | |
230 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
231 | } else | |
232 | return 27; | |
021357ac CW |
233 | } |
234 | ||
5d536e28 | 235 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 236 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 237 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 238 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
239 | .m = { .min = 96, .max = 140 }, |
240 | .m1 = { .min = 18, .max = 26 }, | |
241 | .m2 = { .min = 6, .max = 16 }, | |
242 | .p = { .min = 4, .max = 128 }, | |
243 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
244 | .p2 = { .dot_limit = 165000, |
245 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
246 | }; |
247 | ||
5d536e28 DV |
248 | static const intel_limit_t intel_limits_i8xx_dvo = { |
249 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 250 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 251 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
252 | .m = { .min = 96, .max = 140 }, |
253 | .m1 = { .min = 18, .max = 26 }, | |
254 | .m2 = { .min = 6, .max = 16 }, | |
255 | .p = { .min = 4, .max = 128 }, | |
256 | .p1 = { .min = 2, .max = 33 }, | |
257 | .p2 = { .dot_limit = 165000, | |
258 | .p2_slow = 4, .p2_fast = 4 }, | |
259 | }; | |
260 | ||
e4b36699 | 261 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 262 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 263 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 264 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
265 | .m = { .min = 96, .max = 140 }, |
266 | .m1 = { .min = 18, .max = 26 }, | |
267 | .m2 = { .min = 6, .max = 16 }, | |
268 | .p = { .min = 4, .max = 128 }, | |
269 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
270 | .p2 = { .dot_limit = 165000, |
271 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 272 | }; |
273e27ca | 273 | |
e4b36699 | 274 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
275 | .dot = { .min = 20000, .max = 400000 }, |
276 | .vco = { .min = 1400000, .max = 2800000 }, | |
277 | .n = { .min = 1, .max = 6 }, | |
278 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
279 | .m1 = { .min = 8, .max = 18 }, |
280 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
281 | .p = { .min = 5, .max = 80 }, |
282 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
283 | .p2 = { .dot_limit = 200000, |
284 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
285 | }; |
286 | ||
287 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
288 | .dot = { .min = 20000, .max = 400000 }, |
289 | .vco = { .min = 1400000, .max = 2800000 }, | |
290 | .n = { .min = 1, .max = 6 }, | |
291 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
292 | .m1 = { .min = 8, .max = 18 }, |
293 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
294 | .p = { .min = 7, .max = 98 }, |
295 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
296 | .p2 = { .dot_limit = 112000, |
297 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
298 | }; |
299 | ||
273e27ca | 300 | |
e4b36699 | 301 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
302 | .dot = { .min = 25000, .max = 270000 }, |
303 | .vco = { .min = 1750000, .max = 3500000}, | |
304 | .n = { .min = 1, .max = 4 }, | |
305 | .m = { .min = 104, .max = 138 }, | |
306 | .m1 = { .min = 17, .max = 23 }, | |
307 | .m2 = { .min = 5, .max = 11 }, | |
308 | .p = { .min = 10, .max = 30 }, | |
309 | .p1 = { .min = 1, .max = 3}, | |
310 | .p2 = { .dot_limit = 270000, | |
311 | .p2_slow = 10, | |
312 | .p2_fast = 10 | |
044c7c41 | 313 | }, |
e4b36699 KP |
314 | }; |
315 | ||
316 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
317 | .dot = { .min = 22000, .max = 400000 }, |
318 | .vco = { .min = 1750000, .max = 3500000}, | |
319 | .n = { .min = 1, .max = 4 }, | |
320 | .m = { .min = 104, .max = 138 }, | |
321 | .m1 = { .min = 16, .max = 23 }, | |
322 | .m2 = { .min = 5, .max = 11 }, | |
323 | .p = { .min = 5, .max = 80 }, | |
324 | .p1 = { .min = 1, .max = 8}, | |
325 | .p2 = { .dot_limit = 165000, | |
326 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
327 | }; |
328 | ||
329 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
330 | .dot = { .min = 20000, .max = 115000 }, |
331 | .vco = { .min = 1750000, .max = 3500000 }, | |
332 | .n = { .min = 1, .max = 3 }, | |
333 | .m = { .min = 104, .max = 138 }, | |
334 | .m1 = { .min = 17, .max = 23 }, | |
335 | .m2 = { .min = 5, .max = 11 }, | |
336 | .p = { .min = 28, .max = 112 }, | |
337 | .p1 = { .min = 2, .max = 8 }, | |
338 | .p2 = { .dot_limit = 0, | |
339 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 340 | }, |
e4b36699 KP |
341 | }; |
342 | ||
343 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
344 | .dot = { .min = 80000, .max = 224000 }, |
345 | .vco = { .min = 1750000, .max = 3500000 }, | |
346 | .n = { .min = 1, .max = 3 }, | |
347 | .m = { .min = 104, .max = 138 }, | |
348 | .m1 = { .min = 17, .max = 23 }, | |
349 | .m2 = { .min = 5, .max = 11 }, | |
350 | .p = { .min = 14, .max = 42 }, | |
351 | .p1 = { .min = 2, .max = 6 }, | |
352 | .p2 = { .dot_limit = 0, | |
353 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 354 | }, |
e4b36699 KP |
355 | }; |
356 | ||
f2b115e6 | 357 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
358 | .dot = { .min = 20000, .max = 400000}, |
359 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 360 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
361 | .n = { .min = 3, .max = 6 }, |
362 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 363 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
364 | .m1 = { .min = 0, .max = 0 }, |
365 | .m2 = { .min = 0, .max = 254 }, | |
366 | .p = { .min = 5, .max = 80 }, | |
367 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
368 | .p2 = { .dot_limit = 200000, |
369 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
370 | }; |
371 | ||
f2b115e6 | 372 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
373 | .dot = { .min = 20000, .max = 400000 }, |
374 | .vco = { .min = 1700000, .max = 3500000 }, | |
375 | .n = { .min = 3, .max = 6 }, | |
376 | .m = { .min = 2, .max = 256 }, | |
377 | .m1 = { .min = 0, .max = 0 }, | |
378 | .m2 = { .min = 0, .max = 254 }, | |
379 | .p = { .min = 7, .max = 112 }, | |
380 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
381 | .p2 = { .dot_limit = 112000, |
382 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
383 | }; |
384 | ||
273e27ca EA |
385 | /* Ironlake / Sandybridge |
386 | * | |
387 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
388 | * the range value for them is (actual_value - 2). | |
389 | */ | |
b91ad0ec | 390 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
391 | .dot = { .min = 25000, .max = 350000 }, |
392 | .vco = { .min = 1760000, .max = 3510000 }, | |
393 | .n = { .min = 1, .max = 5 }, | |
394 | .m = { .min = 79, .max = 127 }, | |
395 | .m1 = { .min = 12, .max = 22 }, | |
396 | .m2 = { .min = 5, .max = 9 }, | |
397 | .p = { .min = 5, .max = 80 }, | |
398 | .p1 = { .min = 1, .max = 8 }, | |
399 | .p2 = { .dot_limit = 225000, | |
400 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
401 | }; |
402 | ||
b91ad0ec | 403 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
404 | .dot = { .min = 25000, .max = 350000 }, |
405 | .vco = { .min = 1760000, .max = 3510000 }, | |
406 | .n = { .min = 1, .max = 3 }, | |
407 | .m = { .min = 79, .max = 118 }, | |
408 | .m1 = { .min = 12, .max = 22 }, | |
409 | .m2 = { .min = 5, .max = 9 }, | |
410 | .p = { .min = 28, .max = 112 }, | |
411 | .p1 = { .min = 2, .max = 8 }, | |
412 | .p2 = { .dot_limit = 225000, | |
413 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
414 | }; |
415 | ||
416 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
417 | .dot = { .min = 25000, .max = 350000 }, |
418 | .vco = { .min = 1760000, .max = 3510000 }, | |
419 | .n = { .min = 1, .max = 3 }, | |
420 | .m = { .min = 79, .max = 127 }, | |
421 | .m1 = { .min = 12, .max = 22 }, | |
422 | .m2 = { .min = 5, .max = 9 }, | |
423 | .p = { .min = 14, .max = 56 }, | |
424 | .p1 = { .min = 2, .max = 8 }, | |
425 | .p2 = { .dot_limit = 225000, | |
426 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
427 | }; |
428 | ||
273e27ca | 429 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 430 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
431 | .dot = { .min = 25000, .max = 350000 }, |
432 | .vco = { .min = 1760000, .max = 3510000 }, | |
433 | .n = { .min = 1, .max = 2 }, | |
434 | .m = { .min = 79, .max = 126 }, | |
435 | .m1 = { .min = 12, .max = 22 }, | |
436 | .m2 = { .min = 5, .max = 9 }, | |
437 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 438 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
439 | .p2 = { .dot_limit = 225000, |
440 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
441 | }; |
442 | ||
443 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
444 | .dot = { .min = 25000, .max = 350000 }, |
445 | .vco = { .min = 1760000, .max = 3510000 }, | |
446 | .n = { .min = 1, .max = 3 }, | |
447 | .m = { .min = 79, .max = 126 }, | |
448 | .m1 = { .min = 12, .max = 22 }, | |
449 | .m2 = { .min = 5, .max = 9 }, | |
450 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 451 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
452 | .p2 = { .dot_limit = 225000, |
453 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
454 | }; |
455 | ||
dc730512 | 456 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
457 | /* |
458 | * These are the data rate limits (measured in fast clocks) | |
459 | * since those are the strictest limits we have. The fast | |
460 | * clock and actual rate limits are more relaxed, so checking | |
461 | * them would make no difference. | |
462 | */ | |
463 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 464 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 465 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
466 | .m1 = { .min = 2, .max = 3 }, |
467 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 468 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 469 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
470 | }; |
471 | ||
ef9348c8 CML |
472 | static const intel_limit_t intel_limits_chv = { |
473 | /* | |
474 | * These are the data rate limits (measured in fast clocks) | |
475 | * since those are the strictest limits we have. The fast | |
476 | * clock and actual rate limits are more relaxed, so checking | |
477 | * them would make no difference. | |
478 | */ | |
479 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 480 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
481 | .n = { .min = 1, .max = 1 }, |
482 | .m1 = { .min = 2, .max = 2 }, | |
483 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
484 | .p1 = { .min = 2, .max = 4 }, | |
485 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
486 | }; | |
487 | ||
5ab7b0b7 ID |
488 | static const intel_limit_t intel_limits_bxt = { |
489 | /* FIXME: find real dot limits */ | |
490 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 491 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
492 | .n = { .min = 1, .max = 1 }, |
493 | .m1 = { .min = 2, .max = 2 }, | |
494 | /* FIXME: find real m2 limits */ | |
495 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
496 | .p1 = { .min = 2, .max = 4 }, | |
497 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
498 | }; | |
499 | ||
cdba954e ACO |
500 | static bool |
501 | needs_modeset(struct drm_crtc_state *state) | |
502 | { | |
fc596660 | 503 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
504 | } |
505 | ||
e0638cdf PZ |
506 | /** |
507 | * Returns whether any output on the specified pipe is of the specified type | |
508 | */ | |
4093561b | 509 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) |
e0638cdf | 510 | { |
409ee761 | 511 | struct drm_device *dev = crtc->base.dev; |
e0638cdf PZ |
512 | struct intel_encoder *encoder; |
513 | ||
409ee761 | 514 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
e0638cdf PZ |
515 | if (encoder->type == type) |
516 | return true; | |
517 | ||
518 | return false; | |
519 | } | |
520 | ||
d0737e1d ACO |
521 | /** |
522 | * Returns whether any output on the specified pipe will have the specified | |
523 | * type after a staged modeset is complete, i.e., the same as | |
524 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of | |
525 | * encoder->crtc. | |
526 | */ | |
a93e255f ACO |
527 | static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state, |
528 | int type) | |
d0737e1d | 529 | { |
a93e255f | 530 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 531 | struct drm_connector *connector; |
a93e255f | 532 | struct drm_connector_state *connector_state; |
d0737e1d | 533 | struct intel_encoder *encoder; |
a93e255f ACO |
534 | int i, num_connectors = 0; |
535 | ||
da3ced29 | 536 | for_each_connector_in_state(state, connector, connector_state, i) { |
a93e255f ACO |
537 | if (connector_state->crtc != crtc_state->base.crtc) |
538 | continue; | |
539 | ||
540 | num_connectors++; | |
d0737e1d | 541 | |
a93e255f ACO |
542 | encoder = to_intel_encoder(connector_state->best_encoder); |
543 | if (encoder->type == type) | |
d0737e1d | 544 | return true; |
a93e255f ACO |
545 | } |
546 | ||
547 | WARN_ON(num_connectors == 0); | |
d0737e1d ACO |
548 | |
549 | return false; | |
550 | } | |
551 | ||
a93e255f ACO |
552 | static const intel_limit_t * |
553 | intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk) | |
2c07245f | 554 | { |
a93e255f | 555 | struct drm_device *dev = crtc_state->base.crtc->dev; |
2c07245f | 556 | const intel_limit_t *limit; |
b91ad0ec | 557 | |
a93e255f | 558 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 559 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 560 | if (refclk == 100000) |
b91ad0ec ZW |
561 | limit = &intel_limits_ironlake_dual_lvds_100m; |
562 | else | |
563 | limit = &intel_limits_ironlake_dual_lvds; | |
564 | } else { | |
1b894b59 | 565 | if (refclk == 100000) |
b91ad0ec ZW |
566 | limit = &intel_limits_ironlake_single_lvds_100m; |
567 | else | |
568 | limit = &intel_limits_ironlake_single_lvds; | |
569 | } | |
c6bb3538 | 570 | } else |
b91ad0ec | 571 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
572 | |
573 | return limit; | |
574 | } | |
575 | ||
a93e255f ACO |
576 | static const intel_limit_t * |
577 | intel_g4x_limit(struct intel_crtc_state *crtc_state) | |
044c7c41 | 578 | { |
a93e255f | 579 | struct drm_device *dev = crtc_state->base.crtc->dev; |
044c7c41 ML |
580 | const intel_limit_t *limit; |
581 | ||
a93e255f | 582 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 583 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 584 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 585 | else |
e4b36699 | 586 | limit = &intel_limits_g4x_single_channel_lvds; |
a93e255f ACO |
587 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) || |
588 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 589 | limit = &intel_limits_g4x_hdmi; |
a93e255f | 590 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 591 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 592 | } else /* The option is for other outputs */ |
e4b36699 | 593 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
594 | |
595 | return limit; | |
596 | } | |
597 | ||
a93e255f ACO |
598 | static const intel_limit_t * |
599 | intel_limit(struct intel_crtc_state *crtc_state, int refclk) | |
79e53945 | 600 | { |
a93e255f | 601 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 JB |
602 | const intel_limit_t *limit; |
603 | ||
5ab7b0b7 ID |
604 | if (IS_BROXTON(dev)) |
605 | limit = &intel_limits_bxt; | |
606 | else if (HAS_PCH_SPLIT(dev)) | |
a93e255f | 607 | limit = intel_ironlake_limit(crtc_state, refclk); |
2c07245f | 608 | else if (IS_G4X(dev)) { |
a93e255f | 609 | limit = intel_g4x_limit(crtc_state); |
f2b115e6 | 610 | } else if (IS_PINEVIEW(dev)) { |
a93e255f | 611 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 612 | limit = &intel_limits_pineview_lvds; |
2177832f | 613 | else |
f2b115e6 | 614 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
615 | } else if (IS_CHERRYVIEW(dev)) { |
616 | limit = &intel_limits_chv; | |
a0c4da24 | 617 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 618 | limit = &intel_limits_vlv; |
a6c45cf0 | 619 | } else if (!IS_GEN2(dev)) { |
a93e255f | 620 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a6c45cf0 CW |
621 | limit = &intel_limits_i9xx_lvds; |
622 | else | |
623 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 | 624 | } else { |
a93e255f | 625 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
e4b36699 | 626 | limit = &intel_limits_i8xx_lvds; |
a93e255f | 627 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
e4b36699 | 628 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
629 | else |
630 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
631 | } |
632 | return limit; | |
633 | } | |
634 | ||
dccbea3b ID |
635 | /* |
636 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
637 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
638 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
639 | * The helpers' return value is the rate of the clock that is fed to the | |
640 | * display engine's pipe which can be the above fast dot clock rate or a | |
641 | * divided-down version of it. | |
642 | */ | |
f2b115e6 | 643 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
dccbea3b | 644 | static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock) |
79e53945 | 645 | { |
2177832f SL |
646 | clock->m = clock->m2 + 2; |
647 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 648 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 649 | return 0; |
fb03ac01 VS |
650 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
651 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
652 | |
653 | return clock->dot; | |
2177832f SL |
654 | } |
655 | ||
7429e9d4 DV |
656 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
657 | { | |
658 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
659 | } | |
660 | ||
dccbea3b | 661 | static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock) |
2177832f | 662 | { |
7429e9d4 | 663 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 664 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 665 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 666 | return 0; |
fb03ac01 VS |
667 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
668 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
669 | |
670 | return clock->dot; | |
79e53945 JB |
671 | } |
672 | ||
dccbea3b | 673 | static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock) |
589eca67 ID |
674 | { |
675 | clock->m = clock->m1 * clock->m2; | |
676 | clock->p = clock->p1 * clock->p2; | |
677 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 678 | return 0; |
589eca67 ID |
679 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
680 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
681 | |
682 | return clock->dot / 5; | |
589eca67 ID |
683 | } |
684 | ||
dccbea3b | 685 | int chv_calc_dpll_params(int refclk, intel_clock_t *clock) |
ef9348c8 CML |
686 | { |
687 | clock->m = clock->m1 * clock->m2; | |
688 | clock->p = clock->p1 * clock->p2; | |
689 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 690 | return 0; |
ef9348c8 CML |
691 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
692 | clock->n << 22); | |
693 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
694 | |
695 | return clock->dot / 5; | |
ef9348c8 CML |
696 | } |
697 | ||
7c04d1d9 | 698 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
699 | /** |
700 | * Returns whether the given set of divisors are valid for a given refclk with | |
701 | * the given connectors. | |
702 | */ | |
703 | ||
1b894b59 CW |
704 | static bool intel_PLL_is_valid(struct drm_device *dev, |
705 | const intel_limit_t *limit, | |
706 | const intel_clock_t *clock) | |
79e53945 | 707 | { |
f01b7962 VS |
708 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
709 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 710 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 711 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 712 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 713 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 714 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 715 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 716 | |
5ab7b0b7 | 717 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) |
f01b7962 VS |
718 | if (clock->m1 <= clock->m2) |
719 | INTELPllInvalid("m1 <= m2\n"); | |
720 | ||
5ab7b0b7 | 721 | if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) { |
f01b7962 VS |
722 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
723 | INTELPllInvalid("p out of range\n"); | |
724 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
725 | INTELPllInvalid("m out of range\n"); | |
726 | } | |
727 | ||
79e53945 | 728 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 729 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
730 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
731 | * connector, etc., rather than just a single range. | |
732 | */ | |
733 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 734 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
735 | |
736 | return true; | |
737 | } | |
738 | ||
3b1429d9 VS |
739 | static int |
740 | i9xx_select_p2_div(const intel_limit_t *limit, | |
741 | const struct intel_crtc_state *crtc_state, | |
742 | int target) | |
79e53945 | 743 | { |
3b1429d9 | 744 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 745 | |
a93e255f | 746 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 747 | /* |
a210b028 DV |
748 | * For LVDS just rely on its current settings for dual-channel. |
749 | * We haven't figured out how to reliably set up different | |
750 | * single/dual channel state, if we even can. | |
79e53945 | 751 | */ |
1974cad0 | 752 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 753 | return limit->p2.p2_fast; |
79e53945 | 754 | else |
3b1429d9 | 755 | return limit->p2.p2_slow; |
79e53945 JB |
756 | } else { |
757 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 758 | return limit->p2.p2_slow; |
79e53945 | 759 | else |
3b1429d9 | 760 | return limit->p2.p2_fast; |
79e53945 | 761 | } |
3b1429d9 VS |
762 | } |
763 | ||
764 | static bool | |
765 | i9xx_find_best_dpll(const intel_limit_t *limit, | |
766 | struct intel_crtc_state *crtc_state, | |
767 | int target, int refclk, intel_clock_t *match_clock, | |
768 | intel_clock_t *best_clock) | |
769 | { | |
770 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
771 | intel_clock_t clock; | |
772 | int err = target; | |
79e53945 | 773 | |
0206e353 | 774 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 775 | |
3b1429d9 VS |
776 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
777 | ||
42158660 ZY |
778 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
779 | clock.m1++) { | |
780 | for (clock.m2 = limit->m2.min; | |
781 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 782 | if (clock.m2 >= clock.m1) |
42158660 ZY |
783 | break; |
784 | for (clock.n = limit->n.min; | |
785 | clock.n <= limit->n.max; clock.n++) { | |
786 | for (clock.p1 = limit->p1.min; | |
787 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
788 | int this_err; |
789 | ||
dccbea3b | 790 | i9xx_calc_dpll_params(refclk, &clock); |
ac58c3f0 DV |
791 | if (!intel_PLL_is_valid(dev, limit, |
792 | &clock)) | |
793 | continue; | |
794 | if (match_clock && | |
795 | clock.p != match_clock->p) | |
796 | continue; | |
797 | ||
798 | this_err = abs(clock.dot - target); | |
799 | if (this_err < err) { | |
800 | *best_clock = clock; | |
801 | err = this_err; | |
802 | } | |
803 | } | |
804 | } | |
805 | } | |
806 | } | |
807 | ||
808 | return (err != target); | |
809 | } | |
810 | ||
811 | static bool | |
a93e255f ACO |
812 | pnv_find_best_dpll(const intel_limit_t *limit, |
813 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
814 | int target, int refclk, intel_clock_t *match_clock, |
815 | intel_clock_t *best_clock) | |
79e53945 | 816 | { |
3b1429d9 | 817 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 818 | intel_clock_t clock; |
79e53945 JB |
819 | int err = target; |
820 | ||
0206e353 | 821 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 822 | |
3b1429d9 VS |
823 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
824 | ||
42158660 ZY |
825 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
826 | clock.m1++) { | |
827 | for (clock.m2 = limit->m2.min; | |
828 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
829 | for (clock.n = limit->n.min; |
830 | clock.n <= limit->n.max; clock.n++) { | |
831 | for (clock.p1 = limit->p1.min; | |
832 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
833 | int this_err; |
834 | ||
dccbea3b | 835 | pnv_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
836 | if (!intel_PLL_is_valid(dev, limit, |
837 | &clock)) | |
79e53945 | 838 | continue; |
cec2f356 SP |
839 | if (match_clock && |
840 | clock.p != match_clock->p) | |
841 | continue; | |
79e53945 JB |
842 | |
843 | this_err = abs(clock.dot - target); | |
844 | if (this_err < err) { | |
845 | *best_clock = clock; | |
846 | err = this_err; | |
847 | } | |
848 | } | |
849 | } | |
850 | } | |
851 | } | |
852 | ||
853 | return (err != target); | |
854 | } | |
855 | ||
d4906093 | 856 | static bool |
a93e255f ACO |
857 | g4x_find_best_dpll(const intel_limit_t *limit, |
858 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
859 | int target, int refclk, intel_clock_t *match_clock, |
860 | intel_clock_t *best_clock) | |
d4906093 | 861 | { |
3b1429d9 | 862 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d4906093 ML |
863 | intel_clock_t clock; |
864 | int max_n; | |
3b1429d9 | 865 | bool found = false; |
6ba770dc AJ |
866 | /* approximately equals target * 0.00585 */ |
867 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
868 | |
869 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
870 | |
871 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
872 | ||
d4906093 | 873 | max_n = limit->n.max; |
f77f13e2 | 874 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 875 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 876 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
877 | for (clock.m1 = limit->m1.max; |
878 | clock.m1 >= limit->m1.min; clock.m1--) { | |
879 | for (clock.m2 = limit->m2.max; | |
880 | clock.m2 >= limit->m2.min; clock.m2--) { | |
881 | for (clock.p1 = limit->p1.max; | |
882 | clock.p1 >= limit->p1.min; clock.p1--) { | |
883 | int this_err; | |
884 | ||
dccbea3b | 885 | i9xx_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
886 | if (!intel_PLL_is_valid(dev, limit, |
887 | &clock)) | |
d4906093 | 888 | continue; |
1b894b59 CW |
889 | |
890 | this_err = abs(clock.dot - target); | |
d4906093 ML |
891 | if (this_err < err_most) { |
892 | *best_clock = clock; | |
893 | err_most = this_err; | |
894 | max_n = clock.n; | |
895 | found = true; | |
896 | } | |
897 | } | |
898 | } | |
899 | } | |
900 | } | |
2c07245f ZW |
901 | return found; |
902 | } | |
903 | ||
d5dd62bd ID |
904 | /* |
905 | * Check if the calculated PLL configuration is more optimal compared to the | |
906 | * best configuration and error found so far. Return the calculated error. | |
907 | */ | |
908 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
909 | const intel_clock_t *calculated_clock, | |
910 | const intel_clock_t *best_clock, | |
911 | unsigned int best_error_ppm, | |
912 | unsigned int *error_ppm) | |
913 | { | |
9ca3ba01 ID |
914 | /* |
915 | * For CHV ignore the error and consider only the P value. | |
916 | * Prefer a bigger P value based on HW requirements. | |
917 | */ | |
918 | if (IS_CHERRYVIEW(dev)) { | |
919 | *error_ppm = 0; | |
920 | ||
921 | return calculated_clock->p > best_clock->p; | |
922 | } | |
923 | ||
24be4e46 ID |
924 | if (WARN_ON_ONCE(!target_freq)) |
925 | return false; | |
926 | ||
d5dd62bd ID |
927 | *error_ppm = div_u64(1000000ULL * |
928 | abs(target_freq - calculated_clock->dot), | |
929 | target_freq); | |
930 | /* | |
931 | * Prefer a better P value over a better (smaller) error if the error | |
932 | * is small. Ensure this preference for future configurations too by | |
933 | * setting the error to 0. | |
934 | */ | |
935 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
936 | *error_ppm = 0; | |
937 | ||
938 | return true; | |
939 | } | |
940 | ||
941 | return *error_ppm + 10 < best_error_ppm; | |
942 | } | |
943 | ||
a0c4da24 | 944 | static bool |
a93e255f ACO |
945 | vlv_find_best_dpll(const intel_limit_t *limit, |
946 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
947 | int target, int refclk, intel_clock_t *match_clock, |
948 | intel_clock_t *best_clock) | |
a0c4da24 | 949 | { |
a93e255f | 950 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 951 | struct drm_device *dev = crtc->base.dev; |
6b4bf1c4 | 952 | intel_clock_t clock; |
69e4f900 | 953 | unsigned int bestppm = 1000000; |
27e639bf VS |
954 | /* min update 19.2 MHz */ |
955 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 956 | bool found = false; |
a0c4da24 | 957 | |
6b4bf1c4 VS |
958 | target *= 5; /* fast clock */ |
959 | ||
960 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
961 | |
962 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 963 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 964 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 965 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 966 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 967 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 968 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 969 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 970 | unsigned int ppm; |
69e4f900 | 971 | |
6b4bf1c4 VS |
972 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
973 | refclk * clock.m1); | |
974 | ||
dccbea3b | 975 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 976 | |
f01b7962 VS |
977 | if (!intel_PLL_is_valid(dev, limit, |
978 | &clock)) | |
43b0ac53 VS |
979 | continue; |
980 | ||
d5dd62bd ID |
981 | if (!vlv_PLL_is_optimal(dev, target, |
982 | &clock, | |
983 | best_clock, | |
984 | bestppm, &ppm)) | |
985 | continue; | |
6b4bf1c4 | 986 | |
d5dd62bd ID |
987 | *best_clock = clock; |
988 | bestppm = ppm; | |
989 | found = true; | |
a0c4da24 JB |
990 | } |
991 | } | |
992 | } | |
993 | } | |
a0c4da24 | 994 | |
49e497ef | 995 | return found; |
a0c4da24 | 996 | } |
a4fc5ed6 | 997 | |
ef9348c8 | 998 | static bool |
a93e255f ACO |
999 | chv_find_best_dpll(const intel_limit_t *limit, |
1000 | struct intel_crtc_state *crtc_state, | |
ef9348c8 CML |
1001 | int target, int refclk, intel_clock_t *match_clock, |
1002 | intel_clock_t *best_clock) | |
1003 | { | |
a93e255f | 1004 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 1005 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 1006 | unsigned int best_error_ppm; |
ef9348c8 CML |
1007 | intel_clock_t clock; |
1008 | uint64_t m2; | |
1009 | int found = false; | |
1010 | ||
1011 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 1012 | best_error_ppm = 1000000; |
ef9348c8 CML |
1013 | |
1014 | /* | |
1015 | * Based on hardware doc, the n always set to 1, and m1 always | |
1016 | * set to 2. If requires to support 200Mhz refclk, we need to | |
1017 | * revisit this because n may not 1 anymore. | |
1018 | */ | |
1019 | clock.n = 1, clock.m1 = 2; | |
1020 | target *= 5; /* fast clock */ | |
1021 | ||
1022 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
1023 | for (clock.p2 = limit->p2.p2_fast; | |
1024 | clock.p2 >= limit->p2.p2_slow; | |
1025 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 1026 | unsigned int error_ppm; |
ef9348c8 CML |
1027 | |
1028 | clock.p = clock.p1 * clock.p2; | |
1029 | ||
1030 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
1031 | clock.n) << 22, refclk * clock.m1); | |
1032 | ||
1033 | if (m2 > INT_MAX/clock.m1) | |
1034 | continue; | |
1035 | ||
1036 | clock.m2 = m2; | |
1037 | ||
dccbea3b | 1038 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 CML |
1039 | |
1040 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
1041 | continue; | |
1042 | ||
9ca3ba01 ID |
1043 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
1044 | best_error_ppm, &error_ppm)) | |
1045 | continue; | |
1046 | ||
1047 | *best_clock = clock; | |
1048 | best_error_ppm = error_ppm; | |
1049 | found = true; | |
ef9348c8 CML |
1050 | } |
1051 | } | |
1052 | ||
1053 | return found; | |
1054 | } | |
1055 | ||
5ab7b0b7 ID |
1056 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
1057 | intel_clock_t *best_clock) | |
1058 | { | |
1059 | int refclk = i9xx_get_refclk(crtc_state, 0); | |
1060 | ||
1061 | return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state, | |
1062 | target_clock, refclk, NULL, best_clock); | |
1063 | } | |
1064 | ||
20ddf665 VS |
1065 | bool intel_crtc_active(struct drm_crtc *crtc) |
1066 | { | |
1067 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1068 | ||
1069 | /* Be paranoid as we can arrive here with only partial | |
1070 | * state retrieved from the hardware during setup. | |
1071 | * | |
241bfc38 | 1072 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
1073 | * as Haswell has gained clock readout/fastboot support. |
1074 | * | |
66e514c1 | 1075 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 1076 | * properly reconstruct framebuffers. |
c3d1f436 MR |
1077 | * |
1078 | * FIXME: The intel_crtc->active here should be switched to | |
1079 | * crtc->state->active once we have proper CRTC states wired up | |
1080 | * for atomic. | |
20ddf665 | 1081 | */ |
c3d1f436 | 1082 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 1083 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
1084 | } |
1085 | ||
a5c961d1 PZ |
1086 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1087 | enum pipe pipe) | |
1088 | { | |
1089 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1090 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1091 | ||
6e3c9717 | 1092 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1093 | } |
1094 | ||
fbf49ea2 VS |
1095 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
1096 | { | |
1097 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1098 | i915_reg_t reg = PIPEDSL(pipe); |
fbf49ea2 VS |
1099 | u32 line1, line2; |
1100 | u32 line_mask; | |
1101 | ||
1102 | if (IS_GEN2(dev)) | |
1103 | line_mask = DSL_LINEMASK_GEN2; | |
1104 | else | |
1105 | line_mask = DSL_LINEMASK_GEN3; | |
1106 | ||
1107 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 1108 | msleep(5); |
fbf49ea2 VS |
1109 | line2 = I915_READ(reg) & line_mask; |
1110 | ||
1111 | return line1 == line2; | |
1112 | } | |
1113 | ||
ab7ad7f6 KP |
1114 | /* |
1115 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1116 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1117 | * |
1118 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1119 | * spinning on the vblank interrupt status bit, since we won't actually | |
1120 | * see an interrupt when the pipe is disabled. | |
1121 | * | |
ab7ad7f6 KP |
1122 | * On Gen4 and above: |
1123 | * wait for the pipe register state bit to turn off | |
1124 | * | |
1125 | * Otherwise: | |
1126 | * wait for the display line value to settle (it usually | |
1127 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1128 | * |
9d0498a2 | 1129 | */ |
575f7ab7 | 1130 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1131 | { |
575f7ab7 | 1132 | struct drm_device *dev = crtc->base.dev; |
9d0498a2 | 1133 | struct drm_i915_private *dev_priv = dev->dev_private; |
6e3c9717 | 1134 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1135 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
1136 | |
1137 | if (INTEL_INFO(dev)->gen >= 4) { | |
f0f59a00 | 1138 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1139 | |
1140 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
1141 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1142 | 100)) | |
284637d9 | 1143 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1144 | } else { |
ab7ad7f6 | 1145 | /* Wait for the display line to settle */ |
fbf49ea2 | 1146 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1147 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1148 | } |
79e53945 JB |
1149 | } |
1150 | ||
b24e7179 JB |
1151 | static const char *state_string(bool enabled) |
1152 | { | |
1153 | return enabled ? "on" : "off"; | |
1154 | } | |
1155 | ||
1156 | /* Only for pre-ILK configs */ | |
55607e8a DV |
1157 | void assert_pll(struct drm_i915_private *dev_priv, |
1158 | enum pipe pipe, bool state) | |
b24e7179 | 1159 | { |
b24e7179 JB |
1160 | u32 val; |
1161 | bool cur_state; | |
1162 | ||
649636ef | 1163 | val = I915_READ(DPLL(pipe)); |
b24e7179 | 1164 | cur_state = !!(val & DPLL_VCO_ENABLE); |
e2c719b7 | 1165 | I915_STATE_WARN(cur_state != state, |
b24e7179 JB |
1166 | "PLL state assertion failure (expected %s, current %s)\n", |
1167 | state_string(state), state_string(cur_state)); | |
1168 | } | |
b24e7179 | 1169 | |
23538ef1 JN |
1170 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1171 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1172 | { | |
1173 | u32 val; | |
1174 | bool cur_state; | |
1175 | ||
a580516d | 1176 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1177 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1178 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1179 | |
1180 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1181 | I915_STATE_WARN(cur_state != state, |
23538ef1 JN |
1182 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
1183 | state_string(state), state_string(cur_state)); | |
1184 | } | |
1185 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1186 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1187 | ||
55607e8a | 1188 | struct intel_shared_dpll * |
e2b78267 DV |
1189 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1190 | { | |
1191 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1192 | ||
6e3c9717 | 1193 | if (crtc->config->shared_dpll < 0) |
e2b78267 DV |
1194 | return NULL; |
1195 | ||
6e3c9717 | 1196 | return &dev_priv->shared_dplls[crtc->config->shared_dpll]; |
e2b78267 DV |
1197 | } |
1198 | ||
040484af | 1199 | /* For ILK+ */ |
55607e8a DV |
1200 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1201 | struct intel_shared_dpll *pll, | |
1202 | bool state) | |
040484af | 1203 | { |
040484af | 1204 | bool cur_state; |
5358901f | 1205 | struct intel_dpll_hw_state hw_state; |
040484af | 1206 | |
92b27b08 | 1207 | if (WARN (!pll, |
46edb027 | 1208 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 1209 | return; |
ee7b9f93 | 1210 | |
5358901f | 1211 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
e2c719b7 | 1212 | I915_STATE_WARN(cur_state != state, |
5358901f DV |
1213 | "%s assertion failure (expected %s, current %s)\n", |
1214 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 1215 | } |
040484af JB |
1216 | |
1217 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1218 | enum pipe pipe, bool state) | |
1219 | { | |
040484af | 1220 | bool cur_state; |
ad80a810 PZ |
1221 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1222 | pipe); | |
040484af | 1223 | |
affa9354 PZ |
1224 | if (HAS_DDI(dev_priv->dev)) { |
1225 | /* DDI does not have a specific FDI_TX register */ | |
649636ef | 1226 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
ad80a810 | 1227 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 | 1228 | } else { |
649636ef | 1229 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
bf507ef7 ED |
1230 | cur_state = !!(val & FDI_TX_ENABLE); |
1231 | } | |
e2c719b7 | 1232 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1233 | "FDI TX state assertion failure (expected %s, current %s)\n", |
1234 | state_string(state), state_string(cur_state)); | |
1235 | } | |
1236 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1237 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1238 | ||
1239 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1240 | enum pipe pipe, bool state) | |
1241 | { | |
040484af JB |
1242 | u32 val; |
1243 | bool cur_state; | |
1244 | ||
649636ef | 1245 | val = I915_READ(FDI_RX_CTL(pipe)); |
d63fa0dc | 1246 | cur_state = !!(val & FDI_RX_ENABLE); |
e2c719b7 | 1247 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1248 | "FDI RX state assertion failure (expected %s, current %s)\n", |
1249 | state_string(state), state_string(cur_state)); | |
1250 | } | |
1251 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1252 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1253 | ||
1254 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1255 | enum pipe pipe) | |
1256 | { | |
040484af JB |
1257 | u32 val; |
1258 | ||
1259 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1260 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1261 | return; |
1262 | ||
bf507ef7 | 1263 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1264 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1265 | return; |
1266 | ||
649636ef | 1267 | val = I915_READ(FDI_TX_CTL(pipe)); |
e2c719b7 | 1268 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1269 | } |
1270 | ||
55607e8a DV |
1271 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1272 | enum pipe pipe, bool state) | |
040484af | 1273 | { |
040484af | 1274 | u32 val; |
55607e8a | 1275 | bool cur_state; |
040484af | 1276 | |
649636ef | 1277 | val = I915_READ(FDI_RX_CTL(pipe)); |
55607e8a | 1278 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1279 | I915_STATE_WARN(cur_state != state, |
55607e8a DV |
1280 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
1281 | state_string(state), state_string(cur_state)); | |
040484af JB |
1282 | } |
1283 | ||
b680c37a DV |
1284 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1285 | enum pipe pipe) | |
ea0760cf | 1286 | { |
bedd4dba | 1287 | struct drm_device *dev = dev_priv->dev; |
f0f59a00 | 1288 | i915_reg_t pp_reg; |
ea0760cf JB |
1289 | u32 val; |
1290 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1291 | bool locked = true; |
ea0760cf | 1292 | |
bedd4dba JN |
1293 | if (WARN_ON(HAS_DDI(dev))) |
1294 | return; | |
1295 | ||
1296 | if (HAS_PCH_SPLIT(dev)) { | |
1297 | u32 port_sel; | |
1298 | ||
ea0760cf | 1299 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1300 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1301 | ||
1302 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1303 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1304 | panel_pipe = PIPE_B; | |
1305 | /* XXX: else fix for eDP */ | |
1306 | } else if (IS_VALLEYVIEW(dev)) { | |
1307 | /* presumably write lock depends on pipe, not port select */ | |
1308 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1309 | panel_pipe = pipe; | |
ea0760cf JB |
1310 | } else { |
1311 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1312 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1313 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1314 | } |
1315 | ||
1316 | val = I915_READ(pp_reg); | |
1317 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1318 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1319 | locked = false; |
1320 | ||
e2c719b7 | 1321 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1322 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1323 | pipe_name(pipe)); |
ea0760cf JB |
1324 | } |
1325 | ||
93ce0ba6 JN |
1326 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1327 | enum pipe pipe, bool state) | |
1328 | { | |
1329 | struct drm_device *dev = dev_priv->dev; | |
1330 | bool cur_state; | |
1331 | ||
d9d82081 | 1332 | if (IS_845G(dev) || IS_I865G(dev)) |
0b87c24e | 1333 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
d9d82081 | 1334 | else |
5efb3e28 | 1335 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1336 | |
e2c719b7 | 1337 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 JN |
1338 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
1339 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1340 | } | |
1341 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1342 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1343 | ||
b840d907 JB |
1344 | void assert_pipe(struct drm_i915_private *dev_priv, |
1345 | enum pipe pipe, bool state) | |
b24e7179 | 1346 | { |
63d7bbe9 | 1347 | bool cur_state; |
702e7a56 PZ |
1348 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1349 | pipe); | |
b24e7179 | 1350 | |
b6b5d049 VS |
1351 | /* if we need the pipe quirk it must be always on */ |
1352 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1353 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1354 | state = true; |
1355 | ||
f458ebbc | 1356 | if (!intel_display_power_is_enabled(dev_priv, |
b97186f0 | 1357 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
69310161 PZ |
1358 | cur_state = false; |
1359 | } else { | |
649636ef | 1360 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
69310161 PZ |
1361 | cur_state = !!(val & PIPECONF_ENABLE); |
1362 | } | |
1363 | ||
e2c719b7 | 1364 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1365 | "pipe %c assertion failure (expected %s, current %s)\n", |
9db4a9c7 | 1366 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1367 | } |
1368 | ||
931872fc CW |
1369 | static void assert_plane(struct drm_i915_private *dev_priv, |
1370 | enum plane plane, bool state) | |
b24e7179 | 1371 | { |
b24e7179 | 1372 | u32 val; |
931872fc | 1373 | bool cur_state; |
b24e7179 | 1374 | |
649636ef | 1375 | val = I915_READ(DSPCNTR(plane)); |
931872fc | 1376 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1377 | I915_STATE_WARN(cur_state != state, |
931872fc CW |
1378 | "plane %c assertion failure (expected %s, current %s)\n", |
1379 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1380 | } |
1381 | ||
931872fc CW |
1382 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1383 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1384 | ||
b24e7179 JB |
1385 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1386 | enum pipe pipe) | |
1387 | { | |
653e1026 | 1388 | struct drm_device *dev = dev_priv->dev; |
649636ef | 1389 | int i; |
b24e7179 | 1390 | |
653e1026 VS |
1391 | /* Primary planes are fixed to pipes on gen4+ */ |
1392 | if (INTEL_INFO(dev)->gen >= 4) { | |
649636ef | 1393 | u32 val = I915_READ(DSPCNTR(pipe)); |
e2c719b7 | 1394 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1395 | "plane %c assertion failure, should be disabled but not\n", |
1396 | plane_name(pipe)); | |
19ec1358 | 1397 | return; |
28c05794 | 1398 | } |
19ec1358 | 1399 | |
b24e7179 | 1400 | /* Need to check both planes against the pipe */ |
055e393f | 1401 | for_each_pipe(dev_priv, i) { |
649636ef VS |
1402 | u32 val = I915_READ(DSPCNTR(i)); |
1403 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
b24e7179 | 1404 | DISPPLANE_SEL_PIPE_SHIFT; |
e2c719b7 | 1405 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1406 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1407 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1408 | } |
1409 | } | |
1410 | ||
19332d7a JB |
1411 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1412 | enum pipe pipe) | |
1413 | { | |
20674eef | 1414 | struct drm_device *dev = dev_priv->dev; |
649636ef | 1415 | int sprite; |
19332d7a | 1416 | |
7feb8b88 | 1417 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1418 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1419 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1420 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1421 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1422 | sprite, pipe_name(pipe)); | |
1423 | } | |
1424 | } else if (IS_VALLEYVIEW(dev)) { | |
3bdcfc0c | 1425 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1426 | u32 val = I915_READ(SPCNTR(pipe, sprite)); |
e2c719b7 | 1427 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1428 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1429 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1430 | } |
1431 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
649636ef | 1432 | u32 val = I915_READ(SPRCTL(pipe)); |
e2c719b7 | 1433 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1434 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1435 | plane_name(pipe), pipe_name(pipe)); |
1436 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
649636ef | 1437 | u32 val = I915_READ(DVSCNTR(pipe)); |
e2c719b7 | 1438 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1439 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1440 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1441 | } |
1442 | } | |
1443 | ||
08c71e5e VS |
1444 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1445 | { | |
e2c719b7 | 1446 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1447 | drm_crtc_vblank_put(crtc); |
1448 | } | |
1449 | ||
89eff4be | 1450 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1451 | { |
1452 | u32 val; | |
1453 | bool enabled; | |
1454 | ||
e2c719b7 | 1455 | I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1456 | |
92f2584a JB |
1457 | val = I915_READ(PCH_DREF_CONTROL); |
1458 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1459 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
e2c719b7 | 1460 | I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
92f2584a JB |
1461 | } |
1462 | ||
ab9412ba DV |
1463 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1464 | enum pipe pipe) | |
92f2584a | 1465 | { |
92f2584a JB |
1466 | u32 val; |
1467 | bool enabled; | |
1468 | ||
649636ef | 1469 | val = I915_READ(PCH_TRANSCONF(pipe)); |
92f2584a | 1470 | enabled = !!(val & TRANS_ENABLE); |
e2c719b7 | 1471 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1472 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1473 | pipe_name(pipe)); | |
92f2584a JB |
1474 | } |
1475 | ||
4e634389 KP |
1476 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1477 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1478 | { |
1479 | if ((val & DP_PORT_EN) == 0) | |
1480 | return false; | |
1481 | ||
1482 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
f0f59a00 | 1483 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
f0575e92 KP |
1484 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1485 | return false; | |
44f37d1f CML |
1486 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1487 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1488 | return false; | |
f0575e92 KP |
1489 | } else { |
1490 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1491 | return false; | |
1492 | } | |
1493 | return true; | |
1494 | } | |
1495 | ||
1519b995 KP |
1496 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1497 | enum pipe pipe, u32 val) | |
1498 | { | |
dc0fa718 | 1499 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1500 | return false; |
1501 | ||
1502 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1503 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1504 | return false; |
44f37d1f CML |
1505 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1506 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1507 | return false; | |
1519b995 | 1508 | } else { |
dc0fa718 | 1509 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1510 | return false; |
1511 | } | |
1512 | return true; | |
1513 | } | |
1514 | ||
1515 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1516 | enum pipe pipe, u32 val) | |
1517 | { | |
1518 | if ((val & LVDS_PORT_EN) == 0) | |
1519 | return false; | |
1520 | ||
1521 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1522 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1523 | return false; | |
1524 | } else { | |
1525 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1526 | return false; | |
1527 | } | |
1528 | return true; | |
1529 | } | |
1530 | ||
1531 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1532 | enum pipe pipe, u32 val) | |
1533 | { | |
1534 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1535 | return false; | |
1536 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1537 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1538 | return false; | |
1539 | } else { | |
1540 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1541 | return false; | |
1542 | } | |
1543 | return true; | |
1544 | } | |
1545 | ||
291906f1 | 1546 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
1547 | enum pipe pipe, i915_reg_t reg, |
1548 | u32 port_sel) | |
291906f1 | 1549 | { |
47a05eca | 1550 | u32 val = I915_READ(reg); |
e2c719b7 | 1551 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1552 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1553 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1554 | |
e2c719b7 | 1555 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1556 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1557 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1558 | } |
1559 | ||
1560 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
f0f59a00 | 1561 | enum pipe pipe, i915_reg_t reg) |
291906f1 | 1562 | { |
47a05eca | 1563 | u32 val = I915_READ(reg); |
e2c719b7 | 1564 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1565 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1566 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1567 | |
e2c719b7 | 1568 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1569 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1570 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1571 | } |
1572 | ||
1573 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1574 | enum pipe pipe) | |
1575 | { | |
291906f1 | 1576 | u32 val; |
291906f1 | 1577 | |
f0575e92 KP |
1578 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1579 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1580 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 | 1581 | |
649636ef | 1582 | val = I915_READ(PCH_ADPA); |
e2c719b7 | 1583 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1584 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1585 | pipe_name(pipe)); |
291906f1 | 1586 | |
649636ef | 1587 | val = I915_READ(PCH_LVDS); |
e2c719b7 | 1588 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1589 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1590 | pipe_name(pipe)); |
291906f1 | 1591 | |
e2debe91 PZ |
1592 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1593 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1594 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1595 | } |
1596 | ||
d288f65f | 1597 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1598 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1599 | { |
426115cf DV |
1600 | struct drm_device *dev = crtc->base.dev; |
1601 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1602 | i915_reg_t reg = DPLL(crtc->pipe); |
d288f65f | 1603 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
87442f73 | 1604 | |
426115cf | 1605 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 DV |
1606 | |
1607 | /* No really, not for ILK+ */ | |
1608 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
1609 | ||
1610 | /* PLL is protected by panel, make sure we can write it */ | |
6a9e7363 | 1611 | if (IS_MOBILE(dev_priv->dev)) |
426115cf | 1612 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1613 | |
426115cf DV |
1614 | I915_WRITE(reg, dpll); |
1615 | POSTING_READ(reg); | |
1616 | udelay(150); | |
1617 | ||
1618 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1619 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1620 | ||
d288f65f | 1621 | I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); |
426115cf | 1622 | POSTING_READ(DPLL_MD(crtc->pipe)); |
87442f73 DV |
1623 | |
1624 | /* We do this three times for luck */ | |
426115cf | 1625 | I915_WRITE(reg, dpll); |
87442f73 DV |
1626 | POSTING_READ(reg); |
1627 | udelay(150); /* wait for warmup */ | |
426115cf | 1628 | I915_WRITE(reg, dpll); |
87442f73 DV |
1629 | POSTING_READ(reg); |
1630 | udelay(150); /* wait for warmup */ | |
426115cf | 1631 | I915_WRITE(reg, dpll); |
87442f73 DV |
1632 | POSTING_READ(reg); |
1633 | udelay(150); /* wait for warmup */ | |
1634 | } | |
1635 | ||
d288f65f | 1636 | static void chv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1637 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
1638 | { |
1639 | struct drm_device *dev = crtc->base.dev; | |
1640 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1641 | int pipe = crtc->pipe; | |
1642 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1643 | u32 tmp; |
1644 | ||
1645 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1646 | ||
1647 | BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); | |
1648 | ||
a580516d | 1649 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1650 | |
1651 | /* Enable back the 10bit clock to display controller */ | |
1652 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1653 | tmp |= DPIO_DCLKP_EN; | |
1654 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1655 | ||
54433e91 VS |
1656 | mutex_unlock(&dev_priv->sb_lock); |
1657 | ||
9d556c99 CML |
1658 | /* |
1659 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1660 | */ | |
1661 | udelay(1); | |
1662 | ||
1663 | /* Enable PLL */ | |
d288f65f | 1664 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1665 | |
1666 | /* Check PLL is locked */ | |
a11b0703 | 1667 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1668 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1669 | ||
a11b0703 | 1670 | /* not sure when this should be written */ |
d288f65f | 1671 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
a11b0703 | 1672 | POSTING_READ(DPLL_MD(pipe)); |
9d556c99 CML |
1673 | } |
1674 | ||
1c4e0274 VS |
1675 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1676 | { | |
1677 | struct intel_crtc *crtc; | |
1678 | int count = 0; | |
1679 | ||
1680 | for_each_intel_crtc(dev, crtc) | |
3538b9df | 1681 | count += crtc->base.state->active && |
409ee761 | 1682 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
1c4e0274 VS |
1683 | |
1684 | return count; | |
1685 | } | |
1686 | ||
66e3d5c0 | 1687 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1688 | { |
66e3d5c0 DV |
1689 | struct drm_device *dev = crtc->base.dev; |
1690 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1691 | i915_reg_t reg = DPLL(crtc->pipe); |
6e3c9717 | 1692 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1693 | |
66e3d5c0 | 1694 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1695 | |
63d7bbe9 | 1696 | /* No really, not for ILK+ */ |
3d13ef2e | 1697 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1698 | |
1699 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1700 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1701 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1702 | |
1c4e0274 VS |
1703 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1704 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1705 | /* | |
1706 | * It appears to be important that we don't enable this | |
1707 | * for the current pipe before otherwise configuring the | |
1708 | * PLL. No idea how this should be handled if multiple | |
1709 | * DVO outputs are enabled simultaneosly. | |
1710 | */ | |
1711 | dpll |= DPLL_DVO_2X_MODE; | |
1712 | I915_WRITE(DPLL(!crtc->pipe), | |
1713 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1714 | } | |
66e3d5c0 | 1715 | |
c2b63374 VS |
1716 | /* |
1717 | * Apparently we need to have VGA mode enabled prior to changing | |
1718 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1719 | * dividers, even though the register value does change. | |
1720 | */ | |
1721 | I915_WRITE(reg, 0); | |
1722 | ||
8e7a65aa VS |
1723 | I915_WRITE(reg, dpll); |
1724 | ||
66e3d5c0 DV |
1725 | /* Wait for the clocks to stabilize. */ |
1726 | POSTING_READ(reg); | |
1727 | udelay(150); | |
1728 | ||
1729 | if (INTEL_INFO(dev)->gen >= 4) { | |
1730 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1731 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1732 | } else { |
1733 | /* The pixel multiplier can only be updated once the | |
1734 | * DPLL is enabled and the clocks are stable. | |
1735 | * | |
1736 | * So write it again. | |
1737 | */ | |
1738 | I915_WRITE(reg, dpll); | |
1739 | } | |
63d7bbe9 JB |
1740 | |
1741 | /* We do this three times for luck */ | |
66e3d5c0 | 1742 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1743 | POSTING_READ(reg); |
1744 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1745 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1746 | POSTING_READ(reg); |
1747 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1748 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1749 | POSTING_READ(reg); |
1750 | udelay(150); /* wait for warmup */ | |
1751 | } | |
1752 | ||
1753 | /** | |
50b44a44 | 1754 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1755 | * @dev_priv: i915 private structure |
1756 | * @pipe: pipe PLL to disable | |
1757 | * | |
1758 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1759 | * | |
1760 | * Note! This is for pre-ILK only. | |
1761 | */ | |
1c4e0274 | 1762 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1763 | { |
1c4e0274 VS |
1764 | struct drm_device *dev = crtc->base.dev; |
1765 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1766 | enum pipe pipe = crtc->pipe; | |
1767 | ||
1768 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1769 | if (IS_I830(dev) && | |
409ee761 | 1770 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
3538b9df | 1771 | !intel_num_dvo_pipes(dev)) { |
1c4e0274 VS |
1772 | I915_WRITE(DPLL(PIPE_B), |
1773 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1774 | I915_WRITE(DPLL(PIPE_A), | |
1775 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1776 | } | |
1777 | ||
b6b5d049 VS |
1778 | /* Don't disable pipe or pipe PLLs if needed */ |
1779 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1780 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1781 | return; |
1782 | ||
1783 | /* Make sure the pipe isn't still relying on us */ | |
1784 | assert_pipe_disabled(dev_priv, pipe); | |
1785 | ||
b8afb911 | 1786 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1787 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1788 | } |
1789 | ||
f6071166 JB |
1790 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1791 | { | |
b8afb911 | 1792 | u32 val; |
f6071166 JB |
1793 | |
1794 | /* Make sure the pipe isn't still relying on us */ | |
1795 | assert_pipe_disabled(dev_priv, pipe); | |
1796 | ||
e5cbfbfb ID |
1797 | /* |
1798 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1799 | * The latter is needed for VGA hotplug / manual detection. | |
1800 | */ | |
b8afb911 | 1801 | val = DPLL_VGA_MODE_DIS; |
f6071166 | 1802 | if (pipe == PIPE_B) |
60bfe44f | 1803 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV; |
f6071166 JB |
1804 | I915_WRITE(DPLL(pipe), val); |
1805 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1806 | |
1807 | } | |
1808 | ||
1809 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1810 | { | |
d752048d | 1811 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1812 | u32 val; |
1813 | ||
a11b0703 VS |
1814 | /* Make sure the pipe isn't still relying on us */ |
1815 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1816 | |
a11b0703 | 1817 | /* Set PLL en = 0 */ |
60bfe44f VS |
1818 | val = DPLL_SSC_REF_CLK_CHV | |
1819 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1820 | if (pipe != PIPE_A) |
1821 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1822 | I915_WRITE(DPLL(pipe), val); | |
1823 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1824 | |
a580516d | 1825 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1826 | |
1827 | /* Disable 10bit clock to display controller */ | |
1828 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1829 | val &= ~DPIO_DCLKP_EN; | |
1830 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1831 | ||
a580516d | 1832 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1833 | } |
1834 | ||
e4607fcf | 1835 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1836 | struct intel_digital_port *dport, |
1837 | unsigned int expected_mask) | |
89b667f8 JB |
1838 | { |
1839 | u32 port_mask; | |
f0f59a00 | 1840 | i915_reg_t dpll_reg; |
89b667f8 | 1841 | |
e4607fcf CML |
1842 | switch (dport->port) { |
1843 | case PORT_B: | |
89b667f8 | 1844 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1845 | dpll_reg = DPLL(0); |
e4607fcf CML |
1846 | break; |
1847 | case PORT_C: | |
89b667f8 | 1848 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1849 | dpll_reg = DPLL(0); |
9b6de0a1 | 1850 | expected_mask <<= 4; |
00fc31b7 CML |
1851 | break; |
1852 | case PORT_D: | |
1853 | port_mask = DPLL_PORTD_READY_MASK; | |
1854 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1855 | break; |
1856 | default: | |
1857 | BUG(); | |
1858 | } | |
89b667f8 | 1859 | |
9b6de0a1 VS |
1860 | if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000)) |
1861 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", | |
1862 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1863 | } |
1864 | ||
b14b1055 DV |
1865 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1866 | { | |
1867 | struct drm_device *dev = crtc->base.dev; | |
1868 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1869 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
1870 | ||
be19f0ff CW |
1871 | if (WARN_ON(pll == NULL)) |
1872 | return; | |
1873 | ||
3e369b76 | 1874 | WARN_ON(!pll->config.crtc_mask); |
b14b1055 DV |
1875 | if (pll->active == 0) { |
1876 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
1877 | WARN_ON(pll->on); | |
1878 | assert_shared_dpll_disabled(dev_priv, pll); | |
1879 | ||
1880 | pll->mode_set(dev_priv, pll); | |
1881 | } | |
1882 | } | |
1883 | ||
92f2584a | 1884 | /** |
85b3894f | 1885 | * intel_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1886 | * @dev_priv: i915 private structure |
1887 | * @pipe: pipe PLL to enable | |
1888 | * | |
1889 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1890 | * drives the transcoder clock. | |
1891 | */ | |
85b3894f | 1892 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1893 | { |
3d13ef2e DL |
1894 | struct drm_device *dev = crtc->base.dev; |
1895 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1896 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1897 | |
87a875bb | 1898 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1899 | return; |
1900 | ||
3e369b76 | 1901 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1902 | return; |
ee7b9f93 | 1903 | |
74dd6928 | 1904 | DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n", |
46edb027 | 1905 | pll->name, pll->active, pll->on, |
e2b78267 | 1906 | crtc->base.base.id); |
92f2584a | 1907 | |
cdbd2316 DV |
1908 | if (pll->active++) { |
1909 | WARN_ON(!pll->on); | |
e9d6944e | 1910 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1911 | return; |
1912 | } | |
f4a091c7 | 1913 | WARN_ON(pll->on); |
ee7b9f93 | 1914 | |
bd2bb1b9 PZ |
1915 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
1916 | ||
46edb027 | 1917 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1918 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1919 | pll->on = true; |
92f2584a JB |
1920 | } |
1921 | ||
f6daaec2 | 1922 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1923 | { |
3d13ef2e DL |
1924 | struct drm_device *dev = crtc->base.dev; |
1925 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1926 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1927 | |
92f2584a | 1928 | /* PCH only available on ILK+ */ |
80aa9312 JB |
1929 | if (INTEL_INFO(dev)->gen < 5) |
1930 | return; | |
1931 | ||
eddfcbcd ML |
1932 | if (pll == NULL) |
1933 | return; | |
92f2584a | 1934 | |
eddfcbcd | 1935 | if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base))))) |
48da64a8 | 1936 | return; |
7a419866 | 1937 | |
46edb027 DV |
1938 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1939 | pll->name, pll->active, pll->on, | |
e2b78267 | 1940 | crtc->base.base.id); |
7a419866 | 1941 | |
48da64a8 | 1942 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1943 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1944 | return; |
1945 | } | |
1946 | ||
e9d6944e | 1947 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1948 | WARN_ON(!pll->on); |
cdbd2316 | 1949 | if (--pll->active) |
7a419866 | 1950 | return; |
ee7b9f93 | 1951 | |
46edb027 | 1952 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1953 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1954 | pll->on = false; |
bd2bb1b9 PZ |
1955 | |
1956 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
92f2584a JB |
1957 | } |
1958 | ||
b8a4f404 PZ |
1959 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1960 | enum pipe pipe) | |
040484af | 1961 | { |
23670b32 | 1962 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1963 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1964 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
f0f59a00 VS |
1965 | i915_reg_t reg; |
1966 | uint32_t val, pipeconf_val; | |
040484af JB |
1967 | |
1968 | /* PCH only available on ILK+ */ | |
55522f37 | 1969 | BUG_ON(!HAS_PCH_SPLIT(dev)); |
040484af JB |
1970 | |
1971 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1972 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1973 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1974 | |
1975 | /* FDI must be feeding us bits for PCH ports */ | |
1976 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1977 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1978 | ||
23670b32 DV |
1979 | if (HAS_PCH_CPT(dev)) { |
1980 | /* Workaround: Set the timing override bit before enabling the | |
1981 | * pch transcoder. */ | |
1982 | reg = TRANS_CHICKEN2(pipe); | |
1983 | val = I915_READ(reg); | |
1984 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1985 | I915_WRITE(reg, val); | |
59c859d6 | 1986 | } |
23670b32 | 1987 | |
ab9412ba | 1988 | reg = PCH_TRANSCONF(pipe); |
040484af | 1989 | val = I915_READ(reg); |
5f7f726d | 1990 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1991 | |
1992 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1993 | /* | |
c5de7c6f VS |
1994 | * Make the BPC in transcoder be consistent with |
1995 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1996 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1997 | */ |
dfd07d72 | 1998 | val &= ~PIPECONF_BPC_MASK; |
c5de7c6f VS |
1999 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI)) |
2000 | val |= PIPECONF_8BPC; | |
2001 | else | |
2002 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 2003 | } |
5f7f726d PZ |
2004 | |
2005 | val &= ~TRANS_INTERLACE_MASK; | |
2006 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 | 2007 | if (HAS_PCH_IBX(dev_priv->dev) && |
409ee761 | 2008 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
2009 | val |= TRANS_LEGACY_INTERLACED_ILK; |
2010 | else | |
2011 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
2012 | else |
2013 | val |= TRANS_PROGRESSIVE; | |
2014 | ||
040484af JB |
2015 | I915_WRITE(reg, val | TRANS_ENABLE); |
2016 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 2017 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
2018 | } |
2019 | ||
8fb033d7 | 2020 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 2021 | enum transcoder cpu_transcoder) |
040484af | 2022 | { |
8fb033d7 | 2023 | u32 val, pipeconf_val; |
8fb033d7 PZ |
2024 | |
2025 | /* PCH only available on ILK+ */ | |
55522f37 | 2026 | BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev)); |
8fb033d7 | 2027 | |
8fb033d7 | 2028 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 2029 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 2030 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 2031 | |
223a6fdf | 2032 | /* Workaround: set timing override bit. */ |
36c0d0cf | 2033 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 2034 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 2035 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 2036 | |
25f3ef11 | 2037 | val = TRANS_ENABLE; |
937bb610 | 2038 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 2039 | |
9a76b1c6 PZ |
2040 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
2041 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 2042 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
2043 | else |
2044 | val |= TRANS_PROGRESSIVE; | |
2045 | ||
ab9412ba DV |
2046 | I915_WRITE(LPT_TRANSCONF, val); |
2047 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 2048 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
2049 | } |
2050 | ||
b8a4f404 PZ |
2051 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
2052 | enum pipe pipe) | |
040484af | 2053 | { |
23670b32 | 2054 | struct drm_device *dev = dev_priv->dev; |
f0f59a00 VS |
2055 | i915_reg_t reg; |
2056 | uint32_t val; | |
040484af JB |
2057 | |
2058 | /* FDI relies on the transcoder */ | |
2059 | assert_fdi_tx_disabled(dev_priv, pipe); | |
2060 | assert_fdi_rx_disabled(dev_priv, pipe); | |
2061 | ||
291906f1 JB |
2062 | /* Ports must be off as well */ |
2063 | assert_pch_ports_disabled(dev_priv, pipe); | |
2064 | ||
ab9412ba | 2065 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
2066 | val = I915_READ(reg); |
2067 | val &= ~TRANS_ENABLE; | |
2068 | I915_WRITE(reg, val); | |
2069 | /* wait for PCH transcoder off, transcoder state */ | |
2070 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 2071 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 | 2072 | |
c465613b | 2073 | if (HAS_PCH_CPT(dev)) { |
23670b32 DV |
2074 | /* Workaround: Clear the timing override chicken bit again. */ |
2075 | reg = TRANS_CHICKEN2(pipe); | |
2076 | val = I915_READ(reg); | |
2077 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
2078 | I915_WRITE(reg, val); | |
2079 | } | |
040484af JB |
2080 | } |
2081 | ||
ab4d966c | 2082 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 2083 | { |
8fb033d7 PZ |
2084 | u32 val; |
2085 | ||
ab9412ba | 2086 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 2087 | val &= ~TRANS_ENABLE; |
ab9412ba | 2088 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 2089 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 2090 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 2091 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
2092 | |
2093 | /* Workaround: clear timing override bit. */ | |
36c0d0cf | 2094 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 2095 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 2096 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
2097 | } |
2098 | ||
b24e7179 | 2099 | /** |
309cfea8 | 2100 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 2101 | * @crtc: crtc responsible for the pipe |
b24e7179 | 2102 | * |
0372264a | 2103 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 2104 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 2105 | */ |
e1fdc473 | 2106 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2107 | { |
0372264a PZ |
2108 | struct drm_device *dev = crtc->base.dev; |
2109 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2110 | enum pipe pipe = crtc->pipe; | |
1a70a728 | 2111 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
1a240d4d | 2112 | enum pipe pch_transcoder; |
f0f59a00 | 2113 | i915_reg_t reg; |
b24e7179 JB |
2114 | u32 val; |
2115 | ||
9e2ee2dd VS |
2116 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
2117 | ||
58c6eaa2 | 2118 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 2119 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
2120 | assert_sprites_disabled(dev_priv, pipe); |
2121 | ||
681e5811 | 2122 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
2123 | pch_transcoder = TRANSCODER_A; |
2124 | else | |
2125 | pch_transcoder = pipe; | |
2126 | ||
b24e7179 JB |
2127 | /* |
2128 | * A pipe without a PLL won't actually be able to drive bits from | |
2129 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
2130 | * need the check. | |
2131 | */ | |
50360403 | 2132 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) |
a65347ba | 2133 | if (crtc->config->has_dsi_encoder) |
23538ef1 JN |
2134 | assert_dsi_pll_enabled(dev_priv); |
2135 | else | |
2136 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2137 | else { |
6e3c9717 | 2138 | if (crtc->config->has_pch_encoder) { |
040484af | 2139 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2140 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2141 | assert_fdi_tx_pll_enabled(dev_priv, |
2142 | (enum pipe) cpu_transcoder); | |
040484af JB |
2143 | } |
2144 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2145 | } | |
b24e7179 | 2146 | |
702e7a56 | 2147 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2148 | val = I915_READ(reg); |
7ad25d48 | 2149 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
2150 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
2151 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 2152 | return; |
7ad25d48 | 2153 | } |
00d70b15 CW |
2154 | |
2155 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2156 | POSTING_READ(reg); |
b24e7179 JB |
2157 | } |
2158 | ||
2159 | /** | |
309cfea8 | 2160 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2161 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2162 | * |
575f7ab7 VS |
2163 | * Disable the pipe of @crtc, making sure that various hardware |
2164 | * specific requirements are met, if applicable, e.g. plane | |
2165 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2166 | * |
2167 | * Will wait until the pipe has shut down before returning. | |
2168 | */ | |
575f7ab7 | 2169 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2170 | { |
575f7ab7 | 2171 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
6e3c9717 | 2172 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2173 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 2174 | i915_reg_t reg; |
b24e7179 JB |
2175 | u32 val; |
2176 | ||
9e2ee2dd VS |
2177 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
2178 | ||
b24e7179 JB |
2179 | /* |
2180 | * Make sure planes won't keep trying to pump pixels to us, | |
2181 | * or we might hang the display. | |
2182 | */ | |
2183 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2184 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2185 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2186 | |
702e7a56 | 2187 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2188 | val = I915_READ(reg); |
00d70b15 CW |
2189 | if ((val & PIPECONF_ENABLE) == 0) |
2190 | return; | |
2191 | ||
67adc644 VS |
2192 | /* |
2193 | * Double wide has implications for planes | |
2194 | * so best keep it disabled when not needed. | |
2195 | */ | |
6e3c9717 | 2196 | if (crtc->config->double_wide) |
67adc644 VS |
2197 | val &= ~PIPECONF_DOUBLE_WIDE; |
2198 | ||
2199 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2200 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2201 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2202 | val &= ~PIPECONF_ENABLE; |
2203 | ||
2204 | I915_WRITE(reg, val); | |
2205 | if ((val & PIPECONF_ENABLE) == 0) | |
2206 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2207 | } |
2208 | ||
693db184 CW |
2209 | static bool need_vtd_wa(struct drm_device *dev) |
2210 | { | |
2211 | #ifdef CONFIG_INTEL_IOMMU | |
2212 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2213 | return true; | |
2214 | #endif | |
2215 | return false; | |
2216 | } | |
2217 | ||
50470bb0 | 2218 | unsigned int |
6761dd31 | 2219 | intel_tile_height(struct drm_device *dev, uint32_t pixel_format, |
fe47ea0c | 2220 | uint64_t fb_format_modifier, unsigned int plane) |
a57ce0b2 | 2221 | { |
6761dd31 TU |
2222 | unsigned int tile_height; |
2223 | uint32_t pixel_bytes; | |
a57ce0b2 | 2224 | |
b5d0e9bf DL |
2225 | switch (fb_format_modifier) { |
2226 | case DRM_FORMAT_MOD_NONE: | |
2227 | tile_height = 1; | |
2228 | break; | |
2229 | case I915_FORMAT_MOD_X_TILED: | |
2230 | tile_height = IS_GEN2(dev) ? 16 : 8; | |
2231 | break; | |
2232 | case I915_FORMAT_MOD_Y_TILED: | |
2233 | tile_height = 32; | |
2234 | break; | |
2235 | case I915_FORMAT_MOD_Yf_TILED: | |
fe47ea0c | 2236 | pixel_bytes = drm_format_plane_cpp(pixel_format, plane); |
6761dd31 | 2237 | switch (pixel_bytes) { |
b5d0e9bf | 2238 | default: |
6761dd31 | 2239 | case 1: |
b5d0e9bf DL |
2240 | tile_height = 64; |
2241 | break; | |
6761dd31 TU |
2242 | case 2: |
2243 | case 4: | |
b5d0e9bf DL |
2244 | tile_height = 32; |
2245 | break; | |
6761dd31 | 2246 | case 8: |
b5d0e9bf DL |
2247 | tile_height = 16; |
2248 | break; | |
6761dd31 | 2249 | case 16: |
b5d0e9bf DL |
2250 | WARN_ONCE(1, |
2251 | "128-bit pixels are not supported for display!"); | |
2252 | tile_height = 16; | |
2253 | break; | |
2254 | } | |
2255 | break; | |
2256 | default: | |
2257 | MISSING_CASE(fb_format_modifier); | |
2258 | tile_height = 1; | |
2259 | break; | |
2260 | } | |
091df6cb | 2261 | |
6761dd31 TU |
2262 | return tile_height; |
2263 | } | |
2264 | ||
2265 | unsigned int | |
2266 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
2267 | uint32_t pixel_format, uint64_t fb_format_modifier) | |
2268 | { | |
2269 | return ALIGN(height, intel_tile_height(dev, pixel_format, | |
fe47ea0c | 2270 | fb_format_modifier, 0)); |
a57ce0b2 JB |
2271 | } |
2272 | ||
75c82a53 | 2273 | static void |
f64b98cd TU |
2274 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb, |
2275 | const struct drm_plane_state *plane_state) | |
2276 | { | |
a6d09186 | 2277 | struct intel_rotation_info *info = &view->params.rotation_info; |
84fe03f7 | 2278 | unsigned int tile_height, tile_pitch; |
50470bb0 | 2279 | |
f64b98cd TU |
2280 | *view = i915_ggtt_view_normal; |
2281 | ||
50470bb0 | 2282 | if (!plane_state) |
75c82a53 | 2283 | return; |
50470bb0 | 2284 | |
121920fa | 2285 | if (!intel_rotation_90_or_270(plane_state->rotation)) |
75c82a53 | 2286 | return; |
50470bb0 | 2287 | |
9abc4648 | 2288 | *view = i915_ggtt_view_rotated; |
50470bb0 TU |
2289 | |
2290 | info->height = fb->height; | |
2291 | info->pixel_format = fb->pixel_format; | |
2292 | info->pitch = fb->pitches[0]; | |
89e3e142 | 2293 | info->uv_offset = fb->offsets[1]; |
50470bb0 TU |
2294 | info->fb_modifier = fb->modifier[0]; |
2295 | ||
84fe03f7 | 2296 | tile_height = intel_tile_height(fb->dev, fb->pixel_format, |
fe47ea0c | 2297 | fb->modifier[0], 0); |
84fe03f7 TU |
2298 | tile_pitch = PAGE_SIZE / tile_height; |
2299 | info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch); | |
2300 | info->height_pages = DIV_ROUND_UP(fb->height, tile_height); | |
2301 | info->size = info->width_pages * info->height_pages * PAGE_SIZE; | |
2302 | ||
89e3e142 TU |
2303 | if (info->pixel_format == DRM_FORMAT_NV12) { |
2304 | tile_height = intel_tile_height(fb->dev, fb->pixel_format, | |
2305 | fb->modifier[0], 1); | |
2306 | tile_pitch = PAGE_SIZE / tile_height; | |
2307 | info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch); | |
2308 | info->height_pages_uv = DIV_ROUND_UP(fb->height / 2, | |
2309 | tile_height); | |
2310 | info->size_uv = info->width_pages_uv * info->height_pages_uv * | |
2311 | PAGE_SIZE; | |
2312 | } | |
f64b98cd TU |
2313 | } |
2314 | ||
4e9a86b6 VS |
2315 | static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv) |
2316 | { | |
2317 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2318 | return 256 * 1024; | |
985b8bb4 VS |
2319 | else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || |
2320 | IS_VALLEYVIEW(dev_priv)) | |
4e9a86b6 VS |
2321 | return 128 * 1024; |
2322 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2323 | return 4 * 1024; | |
2324 | else | |
44c5905e | 2325 | return 0; |
4e9a86b6 VS |
2326 | } |
2327 | ||
127bd2ac | 2328 | int |
850c4cdc TU |
2329 | intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
2330 | struct drm_framebuffer *fb, | |
7580d774 | 2331 | const struct drm_plane_state *plane_state) |
6b95a207 | 2332 | { |
850c4cdc | 2333 | struct drm_device *dev = fb->dev; |
ce453d81 | 2334 | struct drm_i915_private *dev_priv = dev->dev_private; |
850c4cdc | 2335 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2336 | struct i915_ggtt_view view; |
6b95a207 KH |
2337 | u32 alignment; |
2338 | int ret; | |
2339 | ||
ebcdd39e MR |
2340 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2341 | ||
7b911adc TU |
2342 | switch (fb->modifier[0]) { |
2343 | case DRM_FORMAT_MOD_NONE: | |
4e9a86b6 | 2344 | alignment = intel_linear_alignment(dev_priv); |
6b95a207 | 2345 | break; |
7b911adc | 2346 | case I915_FORMAT_MOD_X_TILED: |
1fada4cc DL |
2347 | if (INTEL_INFO(dev)->gen >= 9) |
2348 | alignment = 256 * 1024; | |
2349 | else { | |
2350 | /* pin() will align the object as required by fence */ | |
2351 | alignment = 0; | |
2352 | } | |
6b95a207 | 2353 | break; |
7b911adc | 2354 | case I915_FORMAT_MOD_Y_TILED: |
1327b9a1 DL |
2355 | case I915_FORMAT_MOD_Yf_TILED: |
2356 | if (WARN_ONCE(INTEL_INFO(dev)->gen < 9, | |
2357 | "Y tiling bo slipped through, driver bug!\n")) | |
2358 | return -EINVAL; | |
2359 | alignment = 1 * 1024 * 1024; | |
2360 | break; | |
6b95a207 | 2361 | default: |
7b911adc TU |
2362 | MISSING_CASE(fb->modifier[0]); |
2363 | return -EINVAL; | |
6b95a207 KH |
2364 | } |
2365 | ||
75c82a53 | 2366 | intel_fill_fb_ggtt_view(&view, fb, plane_state); |
f64b98cd | 2367 | |
693db184 CW |
2368 | /* Note that the w/a also requires 64 PTE of padding following the |
2369 | * bo. We currently fill all unused PTE with the shadow page and so | |
2370 | * we should always have valid PTE following the scanout preventing | |
2371 | * the VT-d warning. | |
2372 | */ | |
2373 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2374 | alignment = 256 * 1024; | |
2375 | ||
d6dd6843 PZ |
2376 | /* |
2377 | * Global gtt pte registers are special registers which actually forward | |
2378 | * writes to a chunk of system memory. Which means that there is no risk | |
2379 | * that the register values disappear as soon as we call | |
2380 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2381 | * pin/unpin/fence and not more. | |
2382 | */ | |
2383 | intel_runtime_pm_get(dev_priv); | |
2384 | ||
7580d774 ML |
2385 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, |
2386 | &view); | |
48b956c5 | 2387 | if (ret) |
b26a6b35 | 2388 | goto err_pm; |
6b95a207 KH |
2389 | |
2390 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2391 | * fence, whereas 965+ only requires a fence if using | |
2392 | * framebuffer compression. For simplicity, we always install | |
2393 | * a fence as the cost is not that onerous. | |
2394 | */ | |
9807216f VK |
2395 | if (view.type == I915_GGTT_VIEW_NORMAL) { |
2396 | ret = i915_gem_object_get_fence(obj); | |
2397 | if (ret == -EDEADLK) { | |
2398 | /* | |
2399 | * -EDEADLK means there are no free fences | |
2400 | * no pending flips. | |
2401 | * | |
2402 | * This is propagated to atomic, but it uses | |
2403 | * -EDEADLK to force a locking recovery, so | |
2404 | * change the returned error to -EBUSY. | |
2405 | */ | |
2406 | ret = -EBUSY; | |
2407 | goto err_unpin; | |
2408 | } else if (ret) | |
2409 | goto err_unpin; | |
1690e1eb | 2410 | |
9807216f VK |
2411 | i915_gem_object_pin_fence(obj); |
2412 | } | |
6b95a207 | 2413 | |
d6dd6843 | 2414 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2415 | return 0; |
48b956c5 CW |
2416 | |
2417 | err_unpin: | |
f64b98cd | 2418 | i915_gem_object_unpin_from_display_plane(obj, &view); |
b26a6b35 | 2419 | err_pm: |
d6dd6843 | 2420 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2421 | return ret; |
6b95a207 KH |
2422 | } |
2423 | ||
82bc3b2d TU |
2424 | static void intel_unpin_fb_obj(struct drm_framebuffer *fb, |
2425 | const struct drm_plane_state *plane_state) | |
1690e1eb | 2426 | { |
82bc3b2d | 2427 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2428 | struct i915_ggtt_view view; |
82bc3b2d | 2429 | |
ebcdd39e MR |
2430 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2431 | ||
75c82a53 | 2432 | intel_fill_fb_ggtt_view(&view, fb, plane_state); |
f64b98cd | 2433 | |
9807216f VK |
2434 | if (view.type == I915_GGTT_VIEW_NORMAL) |
2435 | i915_gem_object_unpin_fence(obj); | |
2436 | ||
f64b98cd | 2437 | i915_gem_object_unpin_from_display_plane(obj, &view); |
1690e1eb CW |
2438 | } |
2439 | ||
c2c75131 DV |
2440 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2441 | * is assumed to be a power-of-two. */ | |
4e9a86b6 VS |
2442 | unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv, |
2443 | int *x, int *y, | |
bc752862 CW |
2444 | unsigned int tiling_mode, |
2445 | unsigned int cpp, | |
2446 | unsigned int pitch) | |
c2c75131 | 2447 | { |
bc752862 CW |
2448 | if (tiling_mode != I915_TILING_NONE) { |
2449 | unsigned int tile_rows, tiles; | |
c2c75131 | 2450 | |
bc752862 CW |
2451 | tile_rows = *y / 8; |
2452 | *y %= 8; | |
c2c75131 | 2453 | |
bc752862 CW |
2454 | tiles = *x / (512/cpp); |
2455 | *x %= 512/cpp; | |
2456 | ||
2457 | return tile_rows * pitch * 8 + tiles * 4096; | |
2458 | } else { | |
4e9a86b6 | 2459 | unsigned int alignment = intel_linear_alignment(dev_priv) - 1; |
bc752862 CW |
2460 | unsigned int offset; |
2461 | ||
2462 | offset = *y * pitch + *x * cpp; | |
4e9a86b6 VS |
2463 | *y = (offset & alignment) / pitch; |
2464 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
2465 | return offset & ~alignment; | |
bc752862 | 2466 | } |
c2c75131 DV |
2467 | } |
2468 | ||
b35d63fa | 2469 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2470 | { |
2471 | switch (format) { | |
2472 | case DISPPLANE_8BPP: | |
2473 | return DRM_FORMAT_C8; | |
2474 | case DISPPLANE_BGRX555: | |
2475 | return DRM_FORMAT_XRGB1555; | |
2476 | case DISPPLANE_BGRX565: | |
2477 | return DRM_FORMAT_RGB565; | |
2478 | default: | |
2479 | case DISPPLANE_BGRX888: | |
2480 | return DRM_FORMAT_XRGB8888; | |
2481 | case DISPPLANE_RGBX888: | |
2482 | return DRM_FORMAT_XBGR8888; | |
2483 | case DISPPLANE_BGRX101010: | |
2484 | return DRM_FORMAT_XRGB2101010; | |
2485 | case DISPPLANE_RGBX101010: | |
2486 | return DRM_FORMAT_XBGR2101010; | |
2487 | } | |
2488 | } | |
2489 | ||
bc8d7dff DL |
2490 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2491 | { | |
2492 | switch (format) { | |
2493 | case PLANE_CTL_FORMAT_RGB_565: | |
2494 | return DRM_FORMAT_RGB565; | |
2495 | default: | |
2496 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2497 | if (rgb_order) { | |
2498 | if (alpha) | |
2499 | return DRM_FORMAT_ABGR8888; | |
2500 | else | |
2501 | return DRM_FORMAT_XBGR8888; | |
2502 | } else { | |
2503 | if (alpha) | |
2504 | return DRM_FORMAT_ARGB8888; | |
2505 | else | |
2506 | return DRM_FORMAT_XRGB8888; | |
2507 | } | |
2508 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2509 | if (rgb_order) | |
2510 | return DRM_FORMAT_XBGR2101010; | |
2511 | else | |
2512 | return DRM_FORMAT_XRGB2101010; | |
2513 | } | |
2514 | } | |
2515 | ||
5724dbd1 | 2516 | static bool |
f6936e29 DV |
2517 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2518 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2519 | { |
2520 | struct drm_device *dev = crtc->base.dev; | |
3badb49f | 2521 | struct drm_i915_private *dev_priv = to_i915(dev); |
46f297fb JB |
2522 | struct drm_i915_gem_object *obj = NULL; |
2523 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2524 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2525 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2526 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2527 | PAGE_SIZE); | |
2528 | ||
2529 | size_aligned -= base_aligned; | |
46f297fb | 2530 | |
ff2652ea CW |
2531 | if (plane_config->size == 0) |
2532 | return false; | |
2533 | ||
3badb49f PZ |
2534 | /* If the FB is too big, just don't use it since fbdev is not very |
2535 | * important and we should probably use that space with FBC or other | |
2536 | * features. */ | |
2537 | if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size) | |
2538 | return false; | |
2539 | ||
f37b5c2b DV |
2540 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2541 | base_aligned, | |
2542 | base_aligned, | |
2543 | size_aligned); | |
46f297fb | 2544 | if (!obj) |
484b41dd | 2545 | return false; |
46f297fb | 2546 | |
49af449b DL |
2547 | obj->tiling_mode = plane_config->tiling; |
2548 | if (obj->tiling_mode == I915_TILING_X) | |
6bf129df | 2549 | obj->stride = fb->pitches[0]; |
46f297fb | 2550 | |
6bf129df DL |
2551 | mode_cmd.pixel_format = fb->pixel_format; |
2552 | mode_cmd.width = fb->width; | |
2553 | mode_cmd.height = fb->height; | |
2554 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2555 | mode_cmd.modifier[0] = fb->modifier[0]; |
2556 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb JB |
2557 | |
2558 | mutex_lock(&dev->struct_mutex); | |
6bf129df | 2559 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2560 | &mode_cmd, obj)) { |
46f297fb JB |
2561 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2562 | goto out_unref_obj; | |
2563 | } | |
46f297fb | 2564 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2565 | |
f6936e29 | 2566 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2567 | return true; |
46f297fb JB |
2568 | |
2569 | out_unref_obj: | |
2570 | drm_gem_object_unreference(&obj->base); | |
2571 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2572 | return false; |
2573 | } | |
2574 | ||
afd65eb4 MR |
2575 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2576 | static void | |
2577 | update_state_fb(struct drm_plane *plane) | |
2578 | { | |
2579 | if (plane->fb == plane->state->fb) | |
2580 | return; | |
2581 | ||
2582 | if (plane->state->fb) | |
2583 | drm_framebuffer_unreference(plane->state->fb); | |
2584 | plane->state->fb = plane->fb; | |
2585 | if (plane->state->fb) | |
2586 | drm_framebuffer_reference(plane->state->fb); | |
2587 | } | |
2588 | ||
5724dbd1 | 2589 | static void |
f6936e29 DV |
2590 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2591 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2592 | { |
2593 | struct drm_device *dev = intel_crtc->base.dev; | |
d9ceb816 | 2594 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd JB |
2595 | struct drm_crtc *c; |
2596 | struct intel_crtc *i; | |
2ff8fde1 | 2597 | struct drm_i915_gem_object *obj; |
88595ac9 | 2598 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2599 | struct drm_plane_state *plane_state = primary->state; |
88595ac9 | 2600 | struct drm_framebuffer *fb; |
484b41dd | 2601 | |
2d14030b | 2602 | if (!plane_config->fb) |
484b41dd JB |
2603 | return; |
2604 | ||
f6936e29 | 2605 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2606 | fb = &plane_config->fb->base; |
2607 | goto valid_fb; | |
f55548b5 | 2608 | } |
484b41dd | 2609 | |
2d14030b | 2610 | kfree(plane_config->fb); |
484b41dd JB |
2611 | |
2612 | /* | |
2613 | * Failed to alloc the obj, check to see if we should share | |
2614 | * an fb with another CRTC instead | |
2615 | */ | |
70e1e0ec | 2616 | for_each_crtc(dev, c) { |
484b41dd JB |
2617 | i = to_intel_crtc(c); |
2618 | ||
2619 | if (c == &intel_crtc->base) | |
2620 | continue; | |
2621 | ||
2ff8fde1 MR |
2622 | if (!i->active) |
2623 | continue; | |
2624 | ||
88595ac9 DV |
2625 | fb = c->primary->fb; |
2626 | if (!fb) | |
484b41dd JB |
2627 | continue; |
2628 | ||
88595ac9 | 2629 | obj = intel_fb_obj(fb); |
2ff8fde1 | 2630 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
88595ac9 DV |
2631 | drm_framebuffer_reference(fb); |
2632 | goto valid_fb; | |
484b41dd JB |
2633 | } |
2634 | } | |
88595ac9 DV |
2635 | |
2636 | return; | |
2637 | ||
2638 | valid_fb: | |
f44e2659 VS |
2639 | plane_state->src_x = 0; |
2640 | plane_state->src_y = 0; | |
be5651f2 ML |
2641 | plane_state->src_w = fb->width << 16; |
2642 | plane_state->src_h = fb->height << 16; | |
2643 | ||
f44e2659 VS |
2644 | plane_state->crtc_x = 0; |
2645 | plane_state->crtc_y = 0; | |
be5651f2 ML |
2646 | plane_state->crtc_w = fb->width; |
2647 | plane_state->crtc_h = fb->height; | |
2648 | ||
88595ac9 DV |
2649 | obj = intel_fb_obj(fb); |
2650 | if (obj->tiling_mode != I915_TILING_NONE) | |
2651 | dev_priv->preserve_bios_swizzle = true; | |
2652 | ||
be5651f2 ML |
2653 | drm_framebuffer_reference(fb); |
2654 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2655 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
36750f28 | 2656 | intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); |
a9ff8714 | 2657 | obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit; |
46f297fb JB |
2658 | } |
2659 | ||
29b9bde6 DV |
2660 | static void i9xx_update_primary_plane(struct drm_crtc *crtc, |
2661 | struct drm_framebuffer *fb, | |
2662 | int x, int y) | |
81255565 JB |
2663 | { |
2664 | struct drm_device *dev = crtc->dev; | |
2665 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2666 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
2667 | struct drm_plane *primary = crtc->primary; |
2668 | bool visible = to_intel_plane_state(primary->state)->visible; | |
c9ba6fad | 2669 | struct drm_i915_gem_object *obj; |
81255565 | 2670 | int plane = intel_crtc->plane; |
e506a0c6 | 2671 | unsigned long linear_offset; |
81255565 | 2672 | u32 dspcntr; |
f0f59a00 | 2673 | i915_reg_t reg = DSPCNTR(plane); |
48404c1e | 2674 | int pixel_size; |
f45651ba | 2675 | |
b70709a6 | 2676 | if (!visible || !fb) { |
fdd508a6 VS |
2677 | I915_WRITE(reg, 0); |
2678 | if (INTEL_INFO(dev)->gen >= 4) | |
2679 | I915_WRITE(DSPSURF(plane), 0); | |
2680 | else | |
2681 | I915_WRITE(DSPADDR(plane), 0); | |
2682 | POSTING_READ(reg); | |
2683 | return; | |
2684 | } | |
2685 | ||
c9ba6fad VS |
2686 | obj = intel_fb_obj(fb); |
2687 | if (WARN_ON(obj == NULL)) | |
2688 | return; | |
2689 | ||
2690 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2691 | ||
f45651ba VS |
2692 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2693 | ||
fdd508a6 | 2694 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2695 | |
2696 | if (INTEL_INFO(dev)->gen < 4) { | |
2697 | if (intel_crtc->pipe == PIPE_B) | |
2698 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2699 | ||
2700 | /* pipesrc and dspsize control the size that is scaled from, | |
2701 | * which should always be the user's requested size. | |
2702 | */ | |
2703 | I915_WRITE(DSPSIZE(plane), | |
6e3c9717 ACO |
2704 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2705 | (intel_crtc->config->pipe_src_w - 1)); | |
f45651ba | 2706 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
2707 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2708 | I915_WRITE(PRIMSIZE(plane), | |
6e3c9717 ACO |
2709 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2710 | (intel_crtc->config->pipe_src_w - 1)); | |
c14b0485 VS |
2711 | I915_WRITE(PRIMPOS(plane), 0); |
2712 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2713 | } |
81255565 | 2714 | |
57779d06 VS |
2715 | switch (fb->pixel_format) { |
2716 | case DRM_FORMAT_C8: | |
81255565 JB |
2717 | dspcntr |= DISPPLANE_8BPP; |
2718 | break; | |
57779d06 | 2719 | case DRM_FORMAT_XRGB1555: |
57779d06 | 2720 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 2721 | break; |
57779d06 VS |
2722 | case DRM_FORMAT_RGB565: |
2723 | dspcntr |= DISPPLANE_BGRX565; | |
2724 | break; | |
2725 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
2726 | dspcntr |= DISPPLANE_BGRX888; |
2727 | break; | |
2728 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2729 | dspcntr |= DISPPLANE_RGBX888; |
2730 | break; | |
2731 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2732 | dspcntr |= DISPPLANE_BGRX101010; |
2733 | break; | |
2734 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2735 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
2736 | break; |
2737 | default: | |
baba133a | 2738 | BUG(); |
81255565 | 2739 | } |
57779d06 | 2740 | |
f45651ba VS |
2741 | if (INTEL_INFO(dev)->gen >= 4 && |
2742 | obj->tiling_mode != I915_TILING_NONE) | |
2743 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2744 | |
de1aa629 VS |
2745 | if (IS_G4X(dev)) |
2746 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2747 | ||
b9897127 | 2748 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
81255565 | 2749 | |
c2c75131 DV |
2750 | if (INTEL_INFO(dev)->gen >= 4) { |
2751 | intel_crtc->dspaddr_offset = | |
4e9a86b6 VS |
2752 | intel_gen4_compute_page_offset(dev_priv, |
2753 | &x, &y, obj->tiling_mode, | |
b9897127 | 2754 | pixel_size, |
bc752862 | 2755 | fb->pitches[0]); |
c2c75131 DV |
2756 | linear_offset -= intel_crtc->dspaddr_offset; |
2757 | } else { | |
e506a0c6 | 2758 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2759 | } |
e506a0c6 | 2760 | |
8e7d688b | 2761 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2762 | dspcntr |= DISPPLANE_ROTATE_180; |
2763 | ||
6e3c9717 ACO |
2764 | x += (intel_crtc->config->pipe_src_w - 1); |
2765 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2766 | |
2767 | /* Finding the last pixel of the last line of the display | |
2768 | data and adding to linear_offset*/ | |
2769 | linear_offset += | |
6e3c9717 ACO |
2770 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2771 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2772 | } |
2773 | ||
2db3366b PZ |
2774 | intel_crtc->adjusted_x = x; |
2775 | intel_crtc->adjusted_y = y; | |
2776 | ||
48404c1e SJ |
2777 | I915_WRITE(reg, dspcntr); |
2778 | ||
01f2c773 | 2779 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2780 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2781 | I915_WRITE(DSPSURF(plane), |
2782 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2783 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2784 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2785 | } else |
f343c5f6 | 2786 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2787 | POSTING_READ(reg); |
17638cd6 JB |
2788 | } |
2789 | ||
29b9bde6 DV |
2790 | static void ironlake_update_primary_plane(struct drm_crtc *crtc, |
2791 | struct drm_framebuffer *fb, | |
2792 | int x, int y) | |
17638cd6 JB |
2793 | { |
2794 | struct drm_device *dev = crtc->dev; | |
2795 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2796 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
2797 | struct drm_plane *primary = crtc->primary; |
2798 | bool visible = to_intel_plane_state(primary->state)->visible; | |
c9ba6fad | 2799 | struct drm_i915_gem_object *obj; |
17638cd6 | 2800 | int plane = intel_crtc->plane; |
e506a0c6 | 2801 | unsigned long linear_offset; |
17638cd6 | 2802 | u32 dspcntr; |
f0f59a00 | 2803 | i915_reg_t reg = DSPCNTR(plane); |
48404c1e | 2804 | int pixel_size; |
f45651ba | 2805 | |
b70709a6 | 2806 | if (!visible || !fb) { |
fdd508a6 VS |
2807 | I915_WRITE(reg, 0); |
2808 | I915_WRITE(DSPSURF(plane), 0); | |
2809 | POSTING_READ(reg); | |
2810 | return; | |
2811 | } | |
2812 | ||
c9ba6fad VS |
2813 | obj = intel_fb_obj(fb); |
2814 | if (WARN_ON(obj == NULL)) | |
2815 | return; | |
2816 | ||
2817 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2818 | ||
f45651ba VS |
2819 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2820 | ||
fdd508a6 | 2821 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2822 | |
2823 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2824 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2825 | |
57779d06 VS |
2826 | switch (fb->pixel_format) { |
2827 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2828 | dspcntr |= DISPPLANE_8BPP; |
2829 | break; | |
57779d06 VS |
2830 | case DRM_FORMAT_RGB565: |
2831 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2832 | break; |
57779d06 | 2833 | case DRM_FORMAT_XRGB8888: |
57779d06 VS |
2834 | dspcntr |= DISPPLANE_BGRX888; |
2835 | break; | |
2836 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2837 | dspcntr |= DISPPLANE_RGBX888; |
2838 | break; | |
2839 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2840 | dspcntr |= DISPPLANE_BGRX101010; |
2841 | break; | |
2842 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2843 | dspcntr |= DISPPLANE_RGBX101010; |
17638cd6 JB |
2844 | break; |
2845 | default: | |
baba133a | 2846 | BUG(); |
17638cd6 JB |
2847 | } |
2848 | ||
2849 | if (obj->tiling_mode != I915_TILING_NONE) | |
2850 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2851 | |
f45651ba | 2852 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2853 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2854 | |
b9897127 | 2855 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
c2c75131 | 2856 | intel_crtc->dspaddr_offset = |
4e9a86b6 VS |
2857 | intel_gen4_compute_page_offset(dev_priv, |
2858 | &x, &y, obj->tiling_mode, | |
b9897127 | 2859 | pixel_size, |
bc752862 | 2860 | fb->pitches[0]); |
c2c75131 | 2861 | linear_offset -= intel_crtc->dspaddr_offset; |
8e7d688b | 2862 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2863 | dspcntr |= DISPPLANE_ROTATE_180; |
2864 | ||
2865 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
6e3c9717 ACO |
2866 | x += (intel_crtc->config->pipe_src_w - 1); |
2867 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2868 | |
2869 | /* Finding the last pixel of the last line of the display | |
2870 | data and adding to linear_offset*/ | |
2871 | linear_offset += | |
6e3c9717 ACO |
2872 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2873 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2874 | } |
2875 | } | |
2876 | ||
2db3366b PZ |
2877 | intel_crtc->adjusted_x = x; |
2878 | intel_crtc->adjusted_y = y; | |
2879 | ||
48404c1e | 2880 | I915_WRITE(reg, dspcntr); |
17638cd6 | 2881 | |
01f2c773 | 2882 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2883 | I915_WRITE(DSPSURF(plane), |
2884 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2885 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2886 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2887 | } else { | |
2888 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2889 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2890 | } | |
17638cd6 | 2891 | POSTING_READ(reg); |
17638cd6 JB |
2892 | } |
2893 | ||
b321803d DL |
2894 | u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier, |
2895 | uint32_t pixel_format) | |
2896 | { | |
2897 | u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8; | |
2898 | ||
2899 | /* | |
2900 | * The stride is either expressed as a multiple of 64 bytes | |
2901 | * chunks for linear buffers or in number of tiles for tiled | |
2902 | * buffers. | |
2903 | */ | |
2904 | switch (fb_modifier) { | |
2905 | case DRM_FORMAT_MOD_NONE: | |
2906 | return 64; | |
2907 | case I915_FORMAT_MOD_X_TILED: | |
2908 | if (INTEL_INFO(dev)->gen == 2) | |
2909 | return 128; | |
2910 | return 512; | |
2911 | case I915_FORMAT_MOD_Y_TILED: | |
2912 | /* No need to check for old gens and Y tiling since this is | |
2913 | * about the display engine and those will be blocked before | |
2914 | * we get here. | |
2915 | */ | |
2916 | return 128; | |
2917 | case I915_FORMAT_MOD_Yf_TILED: | |
2918 | if (bits_per_pixel == 8) | |
2919 | return 64; | |
2920 | else | |
2921 | return 128; | |
2922 | default: | |
2923 | MISSING_CASE(fb_modifier); | |
2924 | return 64; | |
2925 | } | |
2926 | } | |
2927 | ||
44eb0cb9 MK |
2928 | u32 intel_plane_obj_offset(struct intel_plane *intel_plane, |
2929 | struct drm_i915_gem_object *obj, | |
2930 | unsigned int plane) | |
121920fa | 2931 | { |
ce7f1728 | 2932 | struct i915_ggtt_view view; |
dedf278c | 2933 | struct i915_vma *vma; |
44eb0cb9 | 2934 | u64 offset; |
121920fa | 2935 | |
ce7f1728 DV |
2936 | intel_fill_fb_ggtt_view(&view, intel_plane->base.fb, |
2937 | intel_plane->base.state); | |
121920fa | 2938 | |
ce7f1728 | 2939 | vma = i915_gem_obj_to_ggtt_view(obj, &view); |
dedf278c | 2940 | if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n", |
ce7f1728 | 2941 | view.type)) |
dedf278c TU |
2942 | return -1; |
2943 | ||
44eb0cb9 | 2944 | offset = vma->node.start; |
dedf278c TU |
2945 | |
2946 | if (plane == 1) { | |
a6d09186 | 2947 | offset += vma->ggtt_view.params.rotation_info.uv_start_page * |
dedf278c TU |
2948 | PAGE_SIZE; |
2949 | } | |
2950 | ||
44eb0cb9 MK |
2951 | WARN_ON(upper_32_bits(offset)); |
2952 | ||
2953 | return lower_32_bits(offset); | |
121920fa TU |
2954 | } |
2955 | ||
e435d6e5 ML |
2956 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
2957 | { | |
2958 | struct drm_device *dev = intel_crtc->base.dev; | |
2959 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2960 | ||
2961 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
2962 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
2963 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
2964 | } |
2965 | ||
a1b2278e CK |
2966 | /* |
2967 | * This function detaches (aka. unbinds) unused scalers in hardware | |
2968 | */ | |
0583236e | 2969 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 2970 | { |
a1b2278e CK |
2971 | struct intel_crtc_scaler_state *scaler_state; |
2972 | int i; | |
2973 | ||
a1b2278e CK |
2974 | scaler_state = &intel_crtc->config->scaler_state; |
2975 | ||
2976 | /* loop through and disable scalers that aren't in use */ | |
2977 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
2978 | if (!scaler_state->scalers[i].in_use) |
2979 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
2980 | } |
2981 | } | |
2982 | ||
6156a456 | 2983 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 2984 | { |
6156a456 | 2985 | switch (pixel_format) { |
d161cf7a | 2986 | case DRM_FORMAT_C8: |
c34ce3d1 | 2987 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 2988 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 2989 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 2990 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 2991 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 2992 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 2993 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
2994 | /* |
2995 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
2996 | * to be already pre-multiplied. We need to add a knob (or a different | |
2997 | * DRM_FORMAT) for user-space to configure that. | |
2998 | */ | |
f75fb42a | 2999 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 3000 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 3001 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 3002 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 3003 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 3004 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 3005 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 3006 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 3007 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 3008 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 3009 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 3010 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 3011 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 3012 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 3013 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 3014 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 3015 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 3016 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 3017 | default: |
4249eeef | 3018 | MISSING_CASE(pixel_format); |
70d21f0e | 3019 | } |
8cfcba41 | 3020 | |
c34ce3d1 | 3021 | return 0; |
6156a456 | 3022 | } |
70d21f0e | 3023 | |
6156a456 CK |
3024 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
3025 | { | |
6156a456 | 3026 | switch (fb_modifier) { |
30af77c4 | 3027 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 3028 | break; |
30af77c4 | 3029 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 3030 | return PLANE_CTL_TILED_X; |
b321803d | 3031 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 3032 | return PLANE_CTL_TILED_Y; |
b321803d | 3033 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 3034 | return PLANE_CTL_TILED_YF; |
70d21f0e | 3035 | default: |
6156a456 | 3036 | MISSING_CASE(fb_modifier); |
70d21f0e | 3037 | } |
8cfcba41 | 3038 | |
c34ce3d1 | 3039 | return 0; |
6156a456 | 3040 | } |
70d21f0e | 3041 | |
6156a456 CK |
3042 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
3043 | { | |
3b7a5119 | 3044 | switch (rotation) { |
6156a456 CK |
3045 | case BIT(DRM_ROTATE_0): |
3046 | break; | |
1e8df167 SJ |
3047 | /* |
3048 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
3049 | * while i915 HW rotation is clockwise, thats why this swapping. | |
3050 | */ | |
3b7a5119 | 3051 | case BIT(DRM_ROTATE_90): |
1e8df167 | 3052 | return PLANE_CTL_ROTATE_270; |
3b7a5119 | 3053 | case BIT(DRM_ROTATE_180): |
c34ce3d1 | 3054 | return PLANE_CTL_ROTATE_180; |
3b7a5119 | 3055 | case BIT(DRM_ROTATE_270): |
1e8df167 | 3056 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
3057 | default: |
3058 | MISSING_CASE(rotation); | |
3059 | } | |
3060 | ||
c34ce3d1 | 3061 | return 0; |
6156a456 CK |
3062 | } |
3063 | ||
3064 | static void skylake_update_primary_plane(struct drm_crtc *crtc, | |
3065 | struct drm_framebuffer *fb, | |
3066 | int x, int y) | |
3067 | { | |
3068 | struct drm_device *dev = crtc->dev; | |
3069 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3070 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
3071 | struct drm_plane *plane = crtc->primary; |
3072 | bool visible = to_intel_plane_state(plane->state)->visible; | |
6156a456 CK |
3073 | struct drm_i915_gem_object *obj; |
3074 | int pipe = intel_crtc->pipe; | |
3075 | u32 plane_ctl, stride_div, stride; | |
3076 | u32 tile_height, plane_offset, plane_size; | |
3077 | unsigned int rotation; | |
3078 | int x_offset, y_offset; | |
44eb0cb9 | 3079 | u32 surf_addr; |
6156a456 CK |
3080 | struct intel_crtc_state *crtc_state = intel_crtc->config; |
3081 | struct intel_plane_state *plane_state; | |
3082 | int src_x = 0, src_y = 0, src_w = 0, src_h = 0; | |
3083 | int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0; | |
3084 | int scaler_id = -1; | |
3085 | ||
6156a456 CK |
3086 | plane_state = to_intel_plane_state(plane->state); |
3087 | ||
b70709a6 | 3088 | if (!visible || !fb) { |
6156a456 CK |
3089 | I915_WRITE(PLANE_CTL(pipe, 0), 0); |
3090 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
3091 | POSTING_READ(PLANE_CTL(pipe, 0)); | |
3092 | return; | |
3b7a5119 | 3093 | } |
70d21f0e | 3094 | |
6156a456 CK |
3095 | plane_ctl = PLANE_CTL_ENABLE | |
3096 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3097 | PLANE_CTL_PIPE_CSC_ENABLE; | |
3098 | ||
3099 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); | |
3100 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
3101 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
3102 | ||
3103 | rotation = plane->state->rotation; | |
3104 | plane_ctl |= skl_plane_ctl_rotation(rotation); | |
3105 | ||
b321803d DL |
3106 | obj = intel_fb_obj(fb); |
3107 | stride_div = intel_fb_stride_alignment(dev, fb->modifier[0], | |
3108 | fb->pixel_format); | |
dedf278c | 3109 | surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0); |
3b7a5119 | 3110 | |
a42e5a23 PZ |
3111 | WARN_ON(drm_rect_width(&plane_state->src) == 0); |
3112 | ||
3113 | scaler_id = plane_state->scaler_id; | |
3114 | src_x = plane_state->src.x1 >> 16; | |
3115 | src_y = plane_state->src.y1 >> 16; | |
3116 | src_w = drm_rect_width(&plane_state->src) >> 16; | |
3117 | src_h = drm_rect_height(&plane_state->src) >> 16; | |
3118 | dst_x = plane_state->dst.x1; | |
3119 | dst_y = plane_state->dst.y1; | |
3120 | dst_w = drm_rect_width(&plane_state->dst); | |
3121 | dst_h = drm_rect_height(&plane_state->dst); | |
3122 | ||
3123 | WARN_ON(x != src_x || y != src_y); | |
6156a456 | 3124 | |
3b7a5119 SJ |
3125 | if (intel_rotation_90_or_270(rotation)) { |
3126 | /* stride = Surface height in tiles */ | |
2614f17d | 3127 | tile_height = intel_tile_height(dev, fb->pixel_format, |
fe47ea0c | 3128 | fb->modifier[0], 0); |
3b7a5119 | 3129 | stride = DIV_ROUND_UP(fb->height, tile_height); |
6156a456 | 3130 | x_offset = stride * tile_height - y - src_h; |
3b7a5119 | 3131 | y_offset = x; |
6156a456 | 3132 | plane_size = (src_w - 1) << 16 | (src_h - 1); |
3b7a5119 SJ |
3133 | } else { |
3134 | stride = fb->pitches[0] / stride_div; | |
3135 | x_offset = x; | |
3136 | y_offset = y; | |
6156a456 | 3137 | plane_size = (src_h - 1) << 16 | (src_w - 1); |
3b7a5119 SJ |
3138 | } |
3139 | plane_offset = y_offset << 16 | x_offset; | |
b321803d | 3140 | |
2db3366b PZ |
3141 | intel_crtc->adjusted_x = x_offset; |
3142 | intel_crtc->adjusted_y = y_offset; | |
3143 | ||
70d21f0e | 3144 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
3b7a5119 SJ |
3145 | I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); |
3146 | I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); | |
3147 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
6156a456 CK |
3148 | |
3149 | if (scaler_id >= 0) { | |
3150 | uint32_t ps_ctrl = 0; | |
3151 | ||
3152 | WARN_ON(!dst_w || !dst_h); | |
3153 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | | |
3154 | crtc_state->scaler_state.scalers[scaler_id].mode; | |
3155 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3156 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3157 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3158 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3159 | I915_WRITE(PLANE_POS(pipe, 0), 0); | |
3160 | } else { | |
3161 | I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); | |
3162 | } | |
3163 | ||
121920fa | 3164 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
70d21f0e DL |
3165 | |
3166 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3167 | } | |
3168 | ||
17638cd6 JB |
3169 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3170 | static int | |
3171 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3172 | int x, int y, enum mode_set_atomic state) | |
3173 | { | |
3174 | struct drm_device *dev = crtc->dev; | |
3175 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 3176 | |
ff2a3117 | 3177 | if (dev_priv->fbc.disable_fbc) |
7733b49b | 3178 | dev_priv->fbc.disable_fbc(dev_priv); |
81255565 | 3179 | |
29b9bde6 DV |
3180 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
3181 | ||
3182 | return 0; | |
81255565 JB |
3183 | } |
3184 | ||
7514747d | 3185 | static void intel_complete_page_flips(struct drm_device *dev) |
96a02917 | 3186 | { |
96a02917 VS |
3187 | struct drm_crtc *crtc; |
3188 | ||
70e1e0ec | 3189 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3190 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3191 | enum plane plane = intel_crtc->plane; | |
3192 | ||
3193 | intel_prepare_page_flip(dev, plane); | |
3194 | intel_finish_page_flip_plane(dev, plane); | |
3195 | } | |
7514747d VS |
3196 | } |
3197 | ||
3198 | static void intel_update_primary_planes(struct drm_device *dev) | |
3199 | { | |
7514747d | 3200 | struct drm_crtc *crtc; |
96a02917 | 3201 | |
70e1e0ec | 3202 | for_each_crtc(dev, crtc) { |
11c22da6 ML |
3203 | struct intel_plane *plane = to_intel_plane(crtc->primary); |
3204 | struct intel_plane_state *plane_state; | |
96a02917 | 3205 | |
11c22da6 | 3206 | drm_modeset_lock_crtc(crtc, &plane->base); |
11c22da6 ML |
3207 | plane_state = to_intel_plane_state(plane->base.state); |
3208 | ||
f029ee82 | 3209 | if (crtc->state->active && plane_state->base.fb) |
11c22da6 ML |
3210 | plane->commit_plane(&plane->base, plane_state); |
3211 | ||
3212 | drm_modeset_unlock_crtc(crtc); | |
96a02917 VS |
3213 | } |
3214 | } | |
3215 | ||
7514747d VS |
3216 | void intel_prepare_reset(struct drm_device *dev) |
3217 | { | |
3218 | /* no reset support for gen2 */ | |
3219 | if (IS_GEN2(dev)) | |
3220 | return; | |
3221 | ||
3222 | /* reset doesn't touch the display */ | |
3223 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
3224 | return; | |
3225 | ||
3226 | drm_modeset_lock_all(dev); | |
f98ce92f VS |
3227 | /* |
3228 | * Disabling the crtcs gracefully seems nicer. Also the | |
3229 | * g33 docs say we should at least disable all the planes. | |
3230 | */ | |
6b72d486 | 3231 | intel_display_suspend(dev); |
7514747d VS |
3232 | } |
3233 | ||
3234 | void intel_finish_reset(struct drm_device *dev) | |
3235 | { | |
3236 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3237 | ||
3238 | /* | |
3239 | * Flips in the rings will be nuked by the reset, | |
3240 | * so complete all pending flips so that user space | |
3241 | * will get its events and not get stuck. | |
3242 | */ | |
3243 | intel_complete_page_flips(dev); | |
3244 | ||
3245 | /* no reset support for gen2 */ | |
3246 | if (IS_GEN2(dev)) | |
3247 | return; | |
3248 | ||
3249 | /* reset doesn't touch the display */ | |
3250 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { | |
3251 | /* | |
3252 | * Flips in the rings have been nuked by the reset, | |
3253 | * so update the base address of all primary | |
3254 | * planes to the the last fb to make sure we're | |
3255 | * showing the correct fb after a reset. | |
11c22da6 ML |
3256 | * |
3257 | * FIXME: Atomic will make this obsolete since we won't schedule | |
3258 | * CS-based flips (which might get lost in gpu resets) any more. | |
7514747d VS |
3259 | */ |
3260 | intel_update_primary_planes(dev); | |
3261 | return; | |
3262 | } | |
3263 | ||
3264 | /* | |
3265 | * The display has been reset as well, | |
3266 | * so need a full re-initialization. | |
3267 | */ | |
3268 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3269 | intel_runtime_pm_enable_interrupts(dev_priv); | |
3270 | ||
3271 | intel_modeset_init_hw(dev); | |
3272 | ||
3273 | spin_lock_irq(&dev_priv->irq_lock); | |
3274 | if (dev_priv->display.hpd_irq_setup) | |
3275 | dev_priv->display.hpd_irq_setup(dev); | |
3276 | spin_unlock_irq(&dev_priv->irq_lock); | |
3277 | ||
043e9bda | 3278 | intel_display_resume(dev); |
7514747d VS |
3279 | |
3280 | intel_hpd_init(dev_priv); | |
3281 | ||
3282 | drm_modeset_unlock_all(dev); | |
3283 | } | |
3284 | ||
7d5e3799 CW |
3285 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3286 | { | |
3287 | struct drm_device *dev = crtc->dev; | |
3288 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3289 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7d5e3799 CW |
3290 | bool pending; |
3291 | ||
3292 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
3293 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
3294 | return false; | |
3295 | ||
5e2d7afc | 3296 | spin_lock_irq(&dev->event_lock); |
7d5e3799 | 3297 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
5e2d7afc | 3298 | spin_unlock_irq(&dev->event_lock); |
7d5e3799 CW |
3299 | |
3300 | return pending; | |
3301 | } | |
3302 | ||
bfd16b2a ML |
3303 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
3304 | struct intel_crtc_state *old_crtc_state) | |
e30e8f75 GP |
3305 | { |
3306 | struct drm_device *dev = crtc->base.dev; | |
3307 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bfd16b2a ML |
3308 | struct intel_crtc_state *pipe_config = |
3309 | to_intel_crtc_state(crtc->base.state); | |
e30e8f75 | 3310 | |
bfd16b2a ML |
3311 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
3312 | crtc->base.mode = crtc->base.state->mode; | |
3313 | ||
3314 | DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n", | |
3315 | old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h, | |
3316 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
e30e8f75 | 3317 | |
44522d85 ML |
3318 | if (HAS_DDI(dev)) |
3319 | intel_set_pipe_csc(&crtc->base); | |
3320 | ||
e30e8f75 GP |
3321 | /* |
3322 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3323 | * that in compute_mode_changes we check the native mode (not the pfit | |
3324 | * mode) to see if we can flip rather than do a full mode set. In the | |
3325 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3326 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3327 | * sized surface. | |
e30e8f75 GP |
3328 | */ |
3329 | ||
e30e8f75 | 3330 | I915_WRITE(PIPESRC(crtc->pipe), |
bfd16b2a ML |
3331 | ((pipe_config->pipe_src_w - 1) << 16) | |
3332 | (pipe_config->pipe_src_h - 1)); | |
3333 | ||
3334 | /* on skylake this is done by detaching scalers */ | |
3335 | if (INTEL_INFO(dev)->gen >= 9) { | |
3336 | skl_detach_scalers(crtc); | |
3337 | ||
3338 | if (pipe_config->pch_pfit.enabled) | |
3339 | skylake_pfit_enable(crtc); | |
3340 | } else if (HAS_PCH_SPLIT(dev)) { | |
3341 | if (pipe_config->pch_pfit.enabled) | |
3342 | ironlake_pfit_enable(crtc); | |
3343 | else if (old_crtc_state->pch_pfit.enabled) | |
3344 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3345 | } |
e30e8f75 GP |
3346 | } |
3347 | ||
5e84e1a4 ZW |
3348 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3349 | { | |
3350 | struct drm_device *dev = crtc->dev; | |
3351 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3352 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3353 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3354 | i915_reg_t reg; |
3355 | u32 temp; | |
5e84e1a4 ZW |
3356 | |
3357 | /* enable normal train */ | |
3358 | reg = FDI_TX_CTL(pipe); | |
3359 | temp = I915_READ(reg); | |
61e499bf | 3360 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3361 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3362 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3363 | } else { |
3364 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3365 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3366 | } |
5e84e1a4 ZW |
3367 | I915_WRITE(reg, temp); |
3368 | ||
3369 | reg = FDI_RX_CTL(pipe); | |
3370 | temp = I915_READ(reg); | |
3371 | if (HAS_PCH_CPT(dev)) { | |
3372 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3373 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3374 | } else { | |
3375 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3376 | temp |= FDI_LINK_TRAIN_NONE; | |
3377 | } | |
3378 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3379 | ||
3380 | /* wait one idle pattern time */ | |
3381 | POSTING_READ(reg); | |
3382 | udelay(1000); | |
357555c0 JB |
3383 | |
3384 | /* IVB wants error correction enabled */ | |
3385 | if (IS_IVYBRIDGE(dev)) | |
3386 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3387 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3388 | } |
3389 | ||
8db9d77b ZW |
3390 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3391 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3392 | { | |
3393 | struct drm_device *dev = crtc->dev; | |
3394 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3395 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3396 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3397 | i915_reg_t reg; |
3398 | u32 temp, tries; | |
8db9d77b | 3399 | |
1c8562f6 | 3400 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3401 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3402 | |
e1a44743 AJ |
3403 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3404 | for train result */ | |
5eddb70b CW |
3405 | reg = FDI_RX_IMR(pipe); |
3406 | temp = I915_READ(reg); | |
e1a44743 AJ |
3407 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3408 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3409 | I915_WRITE(reg, temp); |
3410 | I915_READ(reg); | |
e1a44743 AJ |
3411 | udelay(150); |
3412 | ||
8db9d77b | 3413 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3414 | reg = FDI_TX_CTL(pipe); |
3415 | temp = I915_READ(reg); | |
627eb5a3 | 3416 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3417 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3418 | temp &= ~FDI_LINK_TRAIN_NONE; |
3419 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3420 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3421 | |
5eddb70b CW |
3422 | reg = FDI_RX_CTL(pipe); |
3423 | temp = I915_READ(reg); | |
8db9d77b ZW |
3424 | temp &= ~FDI_LINK_TRAIN_NONE; |
3425 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3426 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3427 | ||
3428 | POSTING_READ(reg); | |
8db9d77b ZW |
3429 | udelay(150); |
3430 | ||
5b2adf89 | 3431 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3432 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3433 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3434 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3435 | |
5eddb70b | 3436 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3437 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3438 | temp = I915_READ(reg); |
8db9d77b ZW |
3439 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3440 | ||
3441 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3442 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3443 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3444 | break; |
3445 | } | |
8db9d77b | 3446 | } |
e1a44743 | 3447 | if (tries == 5) |
5eddb70b | 3448 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3449 | |
3450 | /* Train 2 */ | |
5eddb70b CW |
3451 | reg = FDI_TX_CTL(pipe); |
3452 | temp = I915_READ(reg); | |
8db9d77b ZW |
3453 | temp &= ~FDI_LINK_TRAIN_NONE; |
3454 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3455 | I915_WRITE(reg, temp); |
8db9d77b | 3456 | |
5eddb70b CW |
3457 | reg = FDI_RX_CTL(pipe); |
3458 | temp = I915_READ(reg); | |
8db9d77b ZW |
3459 | temp &= ~FDI_LINK_TRAIN_NONE; |
3460 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3461 | I915_WRITE(reg, temp); |
8db9d77b | 3462 | |
5eddb70b CW |
3463 | POSTING_READ(reg); |
3464 | udelay(150); | |
8db9d77b | 3465 | |
5eddb70b | 3466 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3467 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3468 | temp = I915_READ(reg); |
8db9d77b ZW |
3469 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3470 | ||
3471 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3472 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3473 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3474 | break; | |
3475 | } | |
8db9d77b | 3476 | } |
e1a44743 | 3477 | if (tries == 5) |
5eddb70b | 3478 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3479 | |
3480 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3481 | |
8db9d77b ZW |
3482 | } |
3483 | ||
0206e353 | 3484 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3485 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3486 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3487 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3488 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3489 | }; | |
3490 | ||
3491 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3492 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3493 | { | |
3494 | struct drm_device *dev = crtc->dev; | |
3495 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3496 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3497 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3498 | i915_reg_t reg; |
3499 | u32 temp, i, retry; | |
8db9d77b | 3500 | |
e1a44743 AJ |
3501 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3502 | for train result */ | |
5eddb70b CW |
3503 | reg = FDI_RX_IMR(pipe); |
3504 | temp = I915_READ(reg); | |
e1a44743 AJ |
3505 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3506 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3507 | I915_WRITE(reg, temp); |
3508 | ||
3509 | POSTING_READ(reg); | |
e1a44743 AJ |
3510 | udelay(150); |
3511 | ||
8db9d77b | 3512 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3513 | reg = FDI_TX_CTL(pipe); |
3514 | temp = I915_READ(reg); | |
627eb5a3 | 3515 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3516 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3517 | temp &= ~FDI_LINK_TRAIN_NONE; |
3518 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3519 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3520 | /* SNB-B */ | |
3521 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3522 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3523 | |
d74cf324 DV |
3524 | I915_WRITE(FDI_RX_MISC(pipe), |
3525 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3526 | ||
5eddb70b CW |
3527 | reg = FDI_RX_CTL(pipe); |
3528 | temp = I915_READ(reg); | |
8db9d77b ZW |
3529 | if (HAS_PCH_CPT(dev)) { |
3530 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3531 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3532 | } else { | |
3533 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3534 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3535 | } | |
5eddb70b CW |
3536 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3537 | ||
3538 | POSTING_READ(reg); | |
8db9d77b ZW |
3539 | udelay(150); |
3540 | ||
0206e353 | 3541 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3542 | reg = FDI_TX_CTL(pipe); |
3543 | temp = I915_READ(reg); | |
8db9d77b ZW |
3544 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3545 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3546 | I915_WRITE(reg, temp); |
3547 | ||
3548 | POSTING_READ(reg); | |
8db9d77b ZW |
3549 | udelay(500); |
3550 | ||
fa37d39e SP |
3551 | for (retry = 0; retry < 5; retry++) { |
3552 | reg = FDI_RX_IIR(pipe); | |
3553 | temp = I915_READ(reg); | |
3554 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3555 | if (temp & FDI_RX_BIT_LOCK) { | |
3556 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3557 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3558 | break; | |
3559 | } | |
3560 | udelay(50); | |
8db9d77b | 3561 | } |
fa37d39e SP |
3562 | if (retry < 5) |
3563 | break; | |
8db9d77b ZW |
3564 | } |
3565 | if (i == 4) | |
5eddb70b | 3566 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3567 | |
3568 | /* Train 2 */ | |
5eddb70b CW |
3569 | reg = FDI_TX_CTL(pipe); |
3570 | temp = I915_READ(reg); | |
8db9d77b ZW |
3571 | temp &= ~FDI_LINK_TRAIN_NONE; |
3572 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3573 | if (IS_GEN6(dev)) { | |
3574 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3575 | /* SNB-B */ | |
3576 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3577 | } | |
5eddb70b | 3578 | I915_WRITE(reg, temp); |
8db9d77b | 3579 | |
5eddb70b CW |
3580 | reg = FDI_RX_CTL(pipe); |
3581 | temp = I915_READ(reg); | |
8db9d77b ZW |
3582 | if (HAS_PCH_CPT(dev)) { |
3583 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3584 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3585 | } else { | |
3586 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3587 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3588 | } | |
5eddb70b CW |
3589 | I915_WRITE(reg, temp); |
3590 | ||
3591 | POSTING_READ(reg); | |
8db9d77b ZW |
3592 | udelay(150); |
3593 | ||
0206e353 | 3594 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3595 | reg = FDI_TX_CTL(pipe); |
3596 | temp = I915_READ(reg); | |
8db9d77b ZW |
3597 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3598 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3599 | I915_WRITE(reg, temp); |
3600 | ||
3601 | POSTING_READ(reg); | |
8db9d77b ZW |
3602 | udelay(500); |
3603 | ||
fa37d39e SP |
3604 | for (retry = 0; retry < 5; retry++) { |
3605 | reg = FDI_RX_IIR(pipe); | |
3606 | temp = I915_READ(reg); | |
3607 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3608 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3609 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3610 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3611 | break; | |
3612 | } | |
3613 | udelay(50); | |
8db9d77b | 3614 | } |
fa37d39e SP |
3615 | if (retry < 5) |
3616 | break; | |
8db9d77b ZW |
3617 | } |
3618 | if (i == 4) | |
5eddb70b | 3619 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3620 | |
3621 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3622 | } | |
3623 | ||
357555c0 JB |
3624 | /* Manual link training for Ivy Bridge A0 parts */ |
3625 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3626 | { | |
3627 | struct drm_device *dev = crtc->dev; | |
3628 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3629 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3630 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3631 | i915_reg_t reg; |
3632 | u32 temp, i, j; | |
357555c0 JB |
3633 | |
3634 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3635 | for train result */ | |
3636 | reg = FDI_RX_IMR(pipe); | |
3637 | temp = I915_READ(reg); | |
3638 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3639 | temp &= ~FDI_RX_BIT_LOCK; | |
3640 | I915_WRITE(reg, temp); | |
3641 | ||
3642 | POSTING_READ(reg); | |
3643 | udelay(150); | |
3644 | ||
01a415fd DV |
3645 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3646 | I915_READ(FDI_RX_IIR(pipe))); | |
3647 | ||
139ccd3f JB |
3648 | /* Try each vswing and preemphasis setting twice before moving on */ |
3649 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3650 | /* disable first in case we need to retry */ | |
3651 | reg = FDI_TX_CTL(pipe); | |
3652 | temp = I915_READ(reg); | |
3653 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3654 | temp &= ~FDI_TX_ENABLE; | |
3655 | I915_WRITE(reg, temp); | |
357555c0 | 3656 | |
139ccd3f JB |
3657 | reg = FDI_RX_CTL(pipe); |
3658 | temp = I915_READ(reg); | |
3659 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3660 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3661 | temp &= ~FDI_RX_ENABLE; | |
3662 | I915_WRITE(reg, temp); | |
357555c0 | 3663 | |
139ccd3f | 3664 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3665 | reg = FDI_TX_CTL(pipe); |
3666 | temp = I915_READ(reg); | |
139ccd3f | 3667 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3668 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 3669 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3670 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3671 | temp |= snb_b_fdi_train_param[j/2]; |
3672 | temp |= FDI_COMPOSITE_SYNC; | |
3673 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3674 | |
139ccd3f JB |
3675 | I915_WRITE(FDI_RX_MISC(pipe), |
3676 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3677 | |
139ccd3f | 3678 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3679 | temp = I915_READ(reg); |
139ccd3f JB |
3680 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3681 | temp |= FDI_COMPOSITE_SYNC; | |
3682 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3683 | |
139ccd3f JB |
3684 | POSTING_READ(reg); |
3685 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3686 | |
139ccd3f JB |
3687 | for (i = 0; i < 4; i++) { |
3688 | reg = FDI_RX_IIR(pipe); | |
3689 | temp = I915_READ(reg); | |
3690 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3691 | |
139ccd3f JB |
3692 | if (temp & FDI_RX_BIT_LOCK || |
3693 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3694 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3695 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3696 | i); | |
3697 | break; | |
3698 | } | |
3699 | udelay(1); /* should be 0.5us */ | |
3700 | } | |
3701 | if (i == 4) { | |
3702 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3703 | continue; | |
3704 | } | |
357555c0 | 3705 | |
139ccd3f | 3706 | /* Train 2 */ |
357555c0 JB |
3707 | reg = FDI_TX_CTL(pipe); |
3708 | temp = I915_READ(reg); | |
139ccd3f JB |
3709 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3710 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3711 | I915_WRITE(reg, temp); | |
3712 | ||
3713 | reg = FDI_RX_CTL(pipe); | |
3714 | temp = I915_READ(reg); | |
3715 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3716 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3717 | I915_WRITE(reg, temp); |
3718 | ||
3719 | POSTING_READ(reg); | |
139ccd3f | 3720 | udelay(2); /* should be 1.5us */ |
357555c0 | 3721 | |
139ccd3f JB |
3722 | for (i = 0; i < 4; i++) { |
3723 | reg = FDI_RX_IIR(pipe); | |
3724 | temp = I915_READ(reg); | |
3725 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3726 | |
139ccd3f JB |
3727 | if (temp & FDI_RX_SYMBOL_LOCK || |
3728 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3729 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3730 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3731 | i); | |
3732 | goto train_done; | |
3733 | } | |
3734 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3735 | } |
139ccd3f JB |
3736 | if (i == 4) |
3737 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3738 | } |
357555c0 | 3739 | |
139ccd3f | 3740 | train_done: |
357555c0 JB |
3741 | DRM_DEBUG_KMS("FDI train done.\n"); |
3742 | } | |
3743 | ||
88cefb6c | 3744 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3745 | { |
88cefb6c | 3746 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3747 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3748 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
3749 | i915_reg_t reg; |
3750 | u32 temp; | |
c64e311e | 3751 | |
c98e9dcf | 3752 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3753 | reg = FDI_RX_CTL(pipe); |
3754 | temp = I915_READ(reg); | |
627eb5a3 | 3755 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3756 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3757 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3758 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3759 | ||
3760 | POSTING_READ(reg); | |
c98e9dcf JB |
3761 | udelay(200); |
3762 | ||
3763 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3764 | temp = I915_READ(reg); |
3765 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3766 | ||
3767 | POSTING_READ(reg); | |
c98e9dcf JB |
3768 | udelay(200); |
3769 | ||
20749730 PZ |
3770 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3771 | reg = FDI_TX_CTL(pipe); | |
3772 | temp = I915_READ(reg); | |
3773 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3774 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3775 | |
20749730 PZ |
3776 | POSTING_READ(reg); |
3777 | udelay(100); | |
6be4a607 | 3778 | } |
0e23b99d JB |
3779 | } |
3780 | ||
88cefb6c DV |
3781 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3782 | { | |
3783 | struct drm_device *dev = intel_crtc->base.dev; | |
3784 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3785 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3786 | i915_reg_t reg; |
3787 | u32 temp; | |
88cefb6c DV |
3788 | |
3789 | /* Switch from PCDclk to Rawclk */ | |
3790 | reg = FDI_RX_CTL(pipe); | |
3791 | temp = I915_READ(reg); | |
3792 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3793 | ||
3794 | /* Disable CPU FDI TX PLL */ | |
3795 | reg = FDI_TX_CTL(pipe); | |
3796 | temp = I915_READ(reg); | |
3797 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3798 | ||
3799 | POSTING_READ(reg); | |
3800 | udelay(100); | |
3801 | ||
3802 | reg = FDI_RX_CTL(pipe); | |
3803 | temp = I915_READ(reg); | |
3804 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3805 | ||
3806 | /* Wait for the clocks to turn off. */ | |
3807 | POSTING_READ(reg); | |
3808 | udelay(100); | |
3809 | } | |
3810 | ||
0fc932b8 JB |
3811 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3812 | { | |
3813 | struct drm_device *dev = crtc->dev; | |
3814 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3815 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3816 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3817 | i915_reg_t reg; |
3818 | u32 temp; | |
0fc932b8 JB |
3819 | |
3820 | /* disable CPU FDI tx and PCH FDI rx */ | |
3821 | reg = FDI_TX_CTL(pipe); | |
3822 | temp = I915_READ(reg); | |
3823 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3824 | POSTING_READ(reg); | |
3825 | ||
3826 | reg = FDI_RX_CTL(pipe); | |
3827 | temp = I915_READ(reg); | |
3828 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3829 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3830 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3831 | ||
3832 | POSTING_READ(reg); | |
3833 | udelay(100); | |
3834 | ||
3835 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3836 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3837 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3838 | |
3839 | /* still set train pattern 1 */ | |
3840 | reg = FDI_TX_CTL(pipe); | |
3841 | temp = I915_READ(reg); | |
3842 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3843 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3844 | I915_WRITE(reg, temp); | |
3845 | ||
3846 | reg = FDI_RX_CTL(pipe); | |
3847 | temp = I915_READ(reg); | |
3848 | if (HAS_PCH_CPT(dev)) { | |
3849 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3850 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3851 | } else { | |
3852 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3853 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3854 | } | |
3855 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3856 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3857 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3858 | I915_WRITE(reg, temp); |
3859 | ||
3860 | POSTING_READ(reg); | |
3861 | udelay(100); | |
3862 | } | |
3863 | ||
5dce5b93 CW |
3864 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3865 | { | |
3866 | struct intel_crtc *crtc; | |
3867 | ||
3868 | /* Note that we don't need to be called with mode_config.lock here | |
3869 | * as our list of CRTC objects is static for the lifetime of the | |
3870 | * device and so cannot disappear as we iterate. Similarly, we can | |
3871 | * happily treat the predicates as racy, atomic checks as userspace | |
3872 | * cannot claim and pin a new fb without at least acquring the | |
3873 | * struct_mutex and so serialising with us. | |
3874 | */ | |
d3fcc808 | 3875 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3876 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3877 | continue; | |
3878 | ||
3879 | if (crtc->unpin_work) | |
3880 | intel_wait_for_vblank(dev, crtc->pipe); | |
3881 | ||
3882 | return true; | |
3883 | } | |
3884 | ||
3885 | return false; | |
3886 | } | |
3887 | ||
d6bbafa1 CW |
3888 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
3889 | { | |
3890 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
3891 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
3892 | ||
3893 | /* ensure that the unpin work is consistent wrt ->pending. */ | |
3894 | smp_rmb(); | |
3895 | intel_crtc->unpin_work = NULL; | |
3896 | ||
3897 | if (work->event) | |
3898 | drm_send_vblank_event(intel_crtc->base.dev, | |
3899 | intel_crtc->pipe, | |
3900 | work->event); | |
3901 | ||
3902 | drm_crtc_vblank_put(&intel_crtc->base); | |
3903 | ||
3904 | wake_up_all(&dev_priv->pending_flip_queue); | |
3905 | queue_work(dev_priv->wq, &work->work); | |
3906 | ||
3907 | trace_i915_flip_complete(intel_crtc->plane, | |
3908 | work->pending_flip_obj); | |
3909 | } | |
3910 | ||
5008e874 | 3911 | static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3912 | { |
0f91128d | 3913 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3914 | struct drm_i915_private *dev_priv = dev->dev_private; |
5008e874 | 3915 | long ret; |
e6c3a2a6 | 3916 | |
2c10d571 | 3917 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
5008e874 ML |
3918 | |
3919 | ret = wait_event_interruptible_timeout( | |
3920 | dev_priv->pending_flip_queue, | |
3921 | !intel_crtc_has_pending_flip(crtc), | |
3922 | 60*HZ); | |
3923 | ||
3924 | if (ret < 0) | |
3925 | return ret; | |
3926 | ||
3927 | if (ret == 0) { | |
9c787942 | 3928 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2c10d571 | 3929 | |
5e2d7afc | 3930 | spin_lock_irq(&dev->event_lock); |
9c787942 CW |
3931 | if (intel_crtc->unpin_work) { |
3932 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
3933 | page_flip_completed(intel_crtc); | |
3934 | } | |
5e2d7afc | 3935 | spin_unlock_irq(&dev->event_lock); |
9c787942 | 3936 | } |
5bb61643 | 3937 | |
5008e874 | 3938 | return 0; |
e6c3a2a6 CW |
3939 | } |
3940 | ||
e615efe4 ED |
3941 | /* Program iCLKIP clock to the desired frequency */ |
3942 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3943 | { | |
3944 | struct drm_device *dev = crtc->dev; | |
3945 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 3946 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
3947 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3948 | u32 temp; | |
3949 | ||
a580516d | 3950 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 3951 | |
e615efe4 ED |
3952 | /* It is necessary to ungate the pixclk gate prior to programming |
3953 | * the divisors, and gate it back when it is done. | |
3954 | */ | |
3955 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3956 | ||
3957 | /* Disable SSCCTL */ | |
3958 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
3959 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
3960 | SBI_SSCCTL_DISABLE, | |
3961 | SBI_ICLK); | |
e615efe4 ED |
3962 | |
3963 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3964 | if (clock == 20000) { |
e615efe4 ED |
3965 | auxdiv = 1; |
3966 | divsel = 0x41; | |
3967 | phaseinc = 0x20; | |
3968 | } else { | |
3969 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3970 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3971 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3972 | * convert the virtual clock precision to KHz here for higher |
3973 | * precision. | |
3974 | */ | |
3975 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3976 | u32 iclk_pi_range = 64; | |
3977 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3978 | ||
12d7ceed | 3979 | desired_divisor = (iclk_virtual_root_freq / clock); |
e615efe4 ED |
3980 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3981 | pi_value = desired_divisor % iclk_pi_range; | |
3982 | ||
3983 | auxdiv = 0; | |
3984 | divsel = msb_divisor_value - 2; | |
3985 | phaseinc = pi_value; | |
3986 | } | |
3987 | ||
3988 | /* This should not happen with any sane values */ | |
3989 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3990 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3991 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3992 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3993 | ||
3994 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3995 | clock, |
e615efe4 ED |
3996 | auxdiv, |
3997 | divsel, | |
3998 | phasedir, | |
3999 | phaseinc); | |
4000 | ||
4001 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 4002 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
4003 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
4004 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
4005 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
4006 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
4007 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
4008 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 4009 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
4010 | |
4011 | /* Program SSCAUXDIV */ | |
988d6ee8 | 4012 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
4013 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
4014 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 4015 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
4016 | |
4017 | /* Enable modulator and associated divider */ | |
988d6ee8 | 4018 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 4019 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 4020 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
4021 | |
4022 | /* Wait for initialization time */ | |
4023 | udelay(24); | |
4024 | ||
4025 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 | 4026 | |
a580516d | 4027 | mutex_unlock(&dev_priv->sb_lock); |
e615efe4 ED |
4028 | } |
4029 | ||
275f01b2 DV |
4030 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4031 | enum pipe pch_transcoder) | |
4032 | { | |
4033 | struct drm_device *dev = crtc->base.dev; | |
4034 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 4035 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4036 | |
4037 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4038 | I915_READ(HTOTAL(cpu_transcoder))); | |
4039 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4040 | I915_READ(HBLANK(cpu_transcoder))); | |
4041 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4042 | I915_READ(HSYNC(cpu_transcoder))); | |
4043 | ||
4044 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4045 | I915_READ(VTOTAL(cpu_transcoder))); | |
4046 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4047 | I915_READ(VBLANK(cpu_transcoder))); | |
4048 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4049 | I915_READ(VSYNC(cpu_transcoder))); | |
4050 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4051 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4052 | } | |
4053 | ||
003632d9 | 4054 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 DV |
4055 | { |
4056 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4057 | uint32_t temp; | |
4058 | ||
4059 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4060 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4061 | return; |
4062 | ||
4063 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4064 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4065 | ||
003632d9 ACO |
4066 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4067 | if (enable) | |
4068 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4069 | ||
4070 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4071 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4072 | POSTING_READ(SOUTH_CHICKEN1); | |
4073 | } | |
4074 | ||
4075 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4076 | { | |
4077 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4078 | |
4079 | switch (intel_crtc->pipe) { | |
4080 | case PIPE_A: | |
4081 | break; | |
4082 | case PIPE_B: | |
6e3c9717 | 4083 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4084 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4085 | else |
003632d9 | 4086 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4087 | |
4088 | break; | |
4089 | case PIPE_C: | |
003632d9 | 4090 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4091 | |
4092 | break; | |
4093 | default: | |
4094 | BUG(); | |
4095 | } | |
4096 | } | |
4097 | ||
c48b5305 VS |
4098 | /* Return which DP Port should be selected for Transcoder DP control */ |
4099 | static enum port | |
4100 | intel_trans_dp_port_sel(struct drm_crtc *crtc) | |
4101 | { | |
4102 | struct drm_device *dev = crtc->dev; | |
4103 | struct intel_encoder *encoder; | |
4104 | ||
4105 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
4106 | if (encoder->type == INTEL_OUTPUT_DISPLAYPORT || | |
4107 | encoder->type == INTEL_OUTPUT_EDP) | |
4108 | return enc_to_dig_port(&encoder->base)->port; | |
4109 | } | |
4110 | ||
4111 | return -1; | |
4112 | } | |
4113 | ||
f67a559d JB |
4114 | /* |
4115 | * Enable PCH resources required for PCH ports: | |
4116 | * - PCH PLLs | |
4117 | * - FDI training & RX/TX | |
4118 | * - update transcoder timings | |
4119 | * - DP transcoding bits | |
4120 | * - transcoder | |
4121 | */ | |
4122 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4123 | { |
4124 | struct drm_device *dev = crtc->dev; | |
4125 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4126 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4127 | int pipe = intel_crtc->pipe; | |
f0f59a00 | 4128 | u32 temp; |
2c07245f | 4129 | |
ab9412ba | 4130 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4131 | |
1fbc0d78 DV |
4132 | if (IS_IVYBRIDGE(dev)) |
4133 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
4134 | ||
cd986abb DV |
4135 | /* Write the TU size bits before fdi link training, so that error |
4136 | * detection works. */ | |
4137 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4138 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4139 | ||
3860b2ec VS |
4140 | /* |
4141 | * Sometimes spurious CPU pipe underruns happen during FDI | |
4142 | * training, at least with VGA+HDMI cloning. Suppress them. | |
4143 | */ | |
4144 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
4145 | ||
c98e9dcf | 4146 | /* For PCH output, training FDI link */ |
674cf967 | 4147 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4148 | |
3ad8a208 DV |
4149 | /* We need to program the right clock selection before writing the pixel |
4150 | * mutliplier into the DPLL. */ | |
303b81e0 | 4151 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 4152 | u32 sel; |
4b645f14 | 4153 | |
c98e9dcf | 4154 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4155 | temp |= TRANS_DPLL_ENABLE(pipe); |
4156 | sel = TRANS_DPLLB_SEL(pipe); | |
6e3c9717 | 4157 | if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
4158 | temp |= sel; |
4159 | else | |
4160 | temp &= ~sel; | |
c98e9dcf | 4161 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4162 | } |
5eddb70b | 4163 | |
3ad8a208 DV |
4164 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4165 | * transcoder, and we actually should do this to not upset any PCH | |
4166 | * transcoder that already use the clock when we share it. | |
4167 | * | |
4168 | * Note that enable_shared_dpll tries to do the right thing, but | |
4169 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4170 | * the right LVDS enable sequence. */ | |
85b3894f | 4171 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4172 | |
d9b6cb56 JB |
4173 | /* set transcoder timing, panel must allow it */ |
4174 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4175 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4176 | |
303b81e0 | 4177 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4178 | |
3860b2ec VS |
4179 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4180 | ||
c98e9dcf | 4181 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e3c9717 | 4182 | if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { |
9c4edaee VS |
4183 | const struct drm_display_mode *adjusted_mode = |
4184 | &intel_crtc->config->base.adjusted_mode; | |
dfd07d72 | 4185 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
f0f59a00 | 4186 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
5eddb70b CW |
4187 | temp = I915_READ(reg); |
4188 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4189 | TRANS_DP_SYNC_MASK | |
4190 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4191 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4192 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf | 4193 | |
9c4edaee | 4194 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
5eddb70b | 4195 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
9c4edaee | 4196 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4197 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4198 | |
4199 | switch (intel_trans_dp_port_sel(crtc)) { | |
c48b5305 | 4200 | case PORT_B: |
5eddb70b | 4201 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 4202 | break; |
c48b5305 | 4203 | case PORT_C: |
5eddb70b | 4204 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf | 4205 | break; |
c48b5305 | 4206 | case PORT_D: |
5eddb70b | 4207 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4208 | break; |
4209 | default: | |
e95d41e1 | 4210 | BUG(); |
32f9d658 | 4211 | } |
2c07245f | 4212 | |
5eddb70b | 4213 | I915_WRITE(reg, temp); |
6be4a607 | 4214 | } |
b52eb4dc | 4215 | |
b8a4f404 | 4216 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4217 | } |
4218 | ||
1507e5bd PZ |
4219 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4220 | { | |
4221 | struct drm_device *dev = crtc->dev; | |
4222 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4223 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6e3c9717 | 4224 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4225 | |
ab9412ba | 4226 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4227 | |
8c52b5e8 | 4228 | lpt_program_iclkip(crtc); |
1507e5bd | 4229 | |
0540e488 | 4230 | /* Set transcoder timing. */ |
275f01b2 | 4231 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4232 | |
937bb610 | 4233 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4234 | } |
4235 | ||
190f68c5 ACO |
4236 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, |
4237 | struct intel_crtc_state *crtc_state) | |
ee7b9f93 | 4238 | { |
e2b78267 | 4239 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
8bd31e67 | 4240 | struct intel_shared_dpll *pll; |
de419ab6 | 4241 | struct intel_shared_dpll_config *shared_dpll; |
e2b78267 | 4242 | enum intel_dpll_id i; |
00490c22 | 4243 | int max = dev_priv->num_shared_dpll; |
ee7b9f93 | 4244 | |
de419ab6 ML |
4245 | shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state); |
4246 | ||
98b6bd99 DV |
4247 | if (HAS_PCH_IBX(dev_priv->dev)) { |
4248 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 4249 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 4250 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 4251 | |
46edb027 DV |
4252 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
4253 | crtc->base.base.id, pll->name); | |
98b6bd99 | 4254 | |
de419ab6 | 4255 | WARN_ON(shared_dpll[i].crtc_mask); |
f2a69f44 | 4256 | |
98b6bd99 DV |
4257 | goto found; |
4258 | } | |
4259 | ||
bcddf610 S |
4260 | if (IS_BROXTON(dev_priv->dev)) { |
4261 | /* PLL is attached to port in bxt */ | |
4262 | struct intel_encoder *encoder; | |
4263 | struct intel_digital_port *intel_dig_port; | |
4264 | ||
4265 | encoder = intel_ddi_get_crtc_new_encoder(crtc_state); | |
4266 | if (WARN_ON(!encoder)) | |
4267 | return NULL; | |
4268 | ||
4269 | intel_dig_port = enc_to_dig_port(&encoder->base); | |
4270 | /* 1:1 mapping between ports and PLLs */ | |
4271 | i = (enum intel_dpll_id)intel_dig_port->port; | |
4272 | pll = &dev_priv->shared_dplls[i]; | |
4273 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", | |
4274 | crtc->base.base.id, pll->name); | |
de419ab6 | 4275 | WARN_ON(shared_dpll[i].crtc_mask); |
bcddf610 S |
4276 | |
4277 | goto found; | |
00490c22 ML |
4278 | } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv)) |
4279 | /* Do not consider SPLL */ | |
4280 | max = 2; | |
bcddf610 | 4281 | |
00490c22 | 4282 | for (i = 0; i < max; i++) { |
e72f9fbf | 4283 | pll = &dev_priv->shared_dplls[i]; |
ee7b9f93 JB |
4284 | |
4285 | /* Only want to check enabled timings first */ | |
de419ab6 | 4286 | if (shared_dpll[i].crtc_mask == 0) |
ee7b9f93 JB |
4287 | continue; |
4288 | ||
190f68c5 | 4289 | if (memcmp(&crtc_state->dpll_hw_state, |
de419ab6 ML |
4290 | &shared_dpll[i].hw_state, |
4291 | sizeof(crtc_state->dpll_hw_state)) == 0) { | |
8bd31e67 | 4292 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n", |
1e6f2ddc | 4293 | crtc->base.base.id, pll->name, |
de419ab6 | 4294 | shared_dpll[i].crtc_mask, |
8bd31e67 | 4295 | pll->active); |
ee7b9f93 JB |
4296 | goto found; |
4297 | } | |
4298 | } | |
4299 | ||
4300 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
4301 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4302 | pll = &dev_priv->shared_dplls[i]; | |
de419ab6 | 4303 | if (shared_dpll[i].crtc_mask == 0) { |
46edb027 DV |
4304 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
4305 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
4306 | goto found; |
4307 | } | |
4308 | } | |
4309 | ||
4310 | return NULL; | |
4311 | ||
4312 | found: | |
de419ab6 ML |
4313 | if (shared_dpll[i].crtc_mask == 0) |
4314 | shared_dpll[i].hw_state = | |
4315 | crtc_state->dpll_hw_state; | |
f2a69f44 | 4316 | |
190f68c5 | 4317 | crtc_state->shared_dpll = i; |
46edb027 DV |
4318 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
4319 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 4320 | |
de419ab6 | 4321 | shared_dpll[i].crtc_mask |= 1 << crtc->pipe; |
e04c7350 | 4322 | |
ee7b9f93 JB |
4323 | return pll; |
4324 | } | |
4325 | ||
de419ab6 | 4326 | static void intel_shared_dpll_commit(struct drm_atomic_state *state) |
8bd31e67 | 4327 | { |
de419ab6 ML |
4328 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
4329 | struct intel_shared_dpll_config *shared_dpll; | |
8bd31e67 ACO |
4330 | struct intel_shared_dpll *pll; |
4331 | enum intel_dpll_id i; | |
4332 | ||
de419ab6 ML |
4333 | if (!to_intel_atomic_state(state)->dpll_set) |
4334 | return; | |
8bd31e67 | 4335 | |
de419ab6 | 4336 | shared_dpll = to_intel_atomic_state(state)->shared_dpll; |
8bd31e67 ACO |
4337 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4338 | pll = &dev_priv->shared_dplls[i]; | |
de419ab6 | 4339 | pll->config = shared_dpll[i]; |
8bd31e67 ACO |
4340 | } |
4341 | } | |
4342 | ||
a1520318 | 4343 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
4344 | { |
4345 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 4346 | i915_reg_t dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4347 | u32 temp; |
4348 | ||
4349 | temp = I915_READ(dslreg); | |
4350 | udelay(500); | |
4351 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4352 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4353 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4354 | } |
4355 | } | |
4356 | ||
86adf9d7 ML |
4357 | static int |
4358 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
4359 | unsigned scaler_user, int *scaler_id, unsigned int rotation, | |
4360 | int src_w, int src_h, int dst_w, int dst_h) | |
a1b2278e | 4361 | { |
86adf9d7 ML |
4362 | struct intel_crtc_scaler_state *scaler_state = |
4363 | &crtc_state->scaler_state; | |
4364 | struct intel_crtc *intel_crtc = | |
4365 | to_intel_crtc(crtc_state->base.crtc); | |
a1b2278e | 4366 | int need_scaling; |
6156a456 CK |
4367 | |
4368 | need_scaling = intel_rotation_90_or_270(rotation) ? | |
4369 | (src_h != dst_w || src_w != dst_h): | |
4370 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4371 | |
4372 | /* | |
4373 | * if plane is being disabled or scaler is no more required or force detach | |
4374 | * - free scaler binded to this plane/crtc | |
4375 | * - in order to do this, update crtc->scaler_usage | |
4376 | * | |
4377 | * Here scaler state in crtc_state is set free so that | |
4378 | * scaler can be assigned to other user. Actual register | |
4379 | * update to free the scaler is done in plane/panel-fit programming. | |
4380 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4381 | */ | |
86adf9d7 | 4382 | if (force_detach || !need_scaling) { |
a1b2278e | 4383 | if (*scaler_id >= 0) { |
86adf9d7 | 4384 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4385 | scaler_state->scalers[*scaler_id].in_use = 0; |
4386 | ||
86adf9d7 ML |
4387 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4388 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4389 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4390 | scaler_state->scaler_users); |
4391 | *scaler_id = -1; | |
4392 | } | |
4393 | return 0; | |
4394 | } | |
4395 | ||
4396 | /* range checks */ | |
4397 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4398 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4399 | ||
4400 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4401 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4402 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4403 | "size is out of scaler range\n", |
86adf9d7 | 4404 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4405 | return -EINVAL; |
4406 | } | |
4407 | ||
86adf9d7 ML |
4408 | /* mark this plane as a scaler user in crtc_state */ |
4409 | scaler_state->scaler_users |= (1 << scaler_user); | |
4410 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4411 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4412 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4413 | scaler_state->scaler_users); | |
4414 | ||
4415 | return 0; | |
4416 | } | |
4417 | ||
4418 | /** | |
4419 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4420 | * | |
4421 | * @state: crtc's scaler state | |
86adf9d7 ML |
4422 | * |
4423 | * Return | |
4424 | * 0 - scaler_usage updated successfully | |
4425 | * error - requested scaling cannot be supported or other error condition | |
4426 | */ | |
e435d6e5 | 4427 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 ML |
4428 | { |
4429 | struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); | |
7c5f93b0 | 4430 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
86adf9d7 ML |
4431 | |
4432 | DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n", | |
4433 | intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX); | |
4434 | ||
e435d6e5 | 4435 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
86adf9d7 ML |
4436 | &state->scaler_state.scaler_id, DRM_ROTATE_0, |
4437 | state->pipe_src_w, state->pipe_src_h, | |
aad941d5 | 4438 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
86adf9d7 ML |
4439 | } |
4440 | ||
4441 | /** | |
4442 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4443 | * | |
4444 | * @state: crtc's scaler state | |
86adf9d7 ML |
4445 | * @plane_state: atomic plane state to update |
4446 | * | |
4447 | * Return | |
4448 | * 0 - scaler_usage updated successfully | |
4449 | * error - requested scaling cannot be supported or other error condition | |
4450 | */ | |
da20eabd ML |
4451 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4452 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4453 | { |
4454 | ||
4455 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
da20eabd ML |
4456 | struct intel_plane *intel_plane = |
4457 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4458 | struct drm_framebuffer *fb = plane_state->base.fb; |
4459 | int ret; | |
4460 | ||
4461 | bool force_detach = !fb || !plane_state->visible; | |
4462 | ||
4463 | DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n", | |
4464 | intel_plane->base.base.id, intel_crtc->pipe, | |
4465 | drm_plane_index(&intel_plane->base)); | |
4466 | ||
4467 | ret = skl_update_scaler(crtc_state, force_detach, | |
4468 | drm_plane_index(&intel_plane->base), | |
4469 | &plane_state->scaler_id, | |
4470 | plane_state->base.rotation, | |
4471 | drm_rect_width(&plane_state->src) >> 16, | |
4472 | drm_rect_height(&plane_state->src) >> 16, | |
4473 | drm_rect_width(&plane_state->dst), | |
4474 | drm_rect_height(&plane_state->dst)); | |
4475 | ||
4476 | if (ret || plane_state->scaler_id < 0) | |
4477 | return ret; | |
4478 | ||
a1b2278e | 4479 | /* check colorkey */ |
818ed961 | 4480 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
86adf9d7 | 4481 | DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed", |
818ed961 | 4482 | intel_plane->base.base.id); |
a1b2278e CK |
4483 | return -EINVAL; |
4484 | } | |
4485 | ||
4486 | /* Check src format */ | |
86adf9d7 ML |
4487 | switch (fb->pixel_format) { |
4488 | case DRM_FORMAT_RGB565: | |
4489 | case DRM_FORMAT_XBGR8888: | |
4490 | case DRM_FORMAT_XRGB8888: | |
4491 | case DRM_FORMAT_ABGR8888: | |
4492 | case DRM_FORMAT_ARGB8888: | |
4493 | case DRM_FORMAT_XRGB2101010: | |
4494 | case DRM_FORMAT_XBGR2101010: | |
4495 | case DRM_FORMAT_YUYV: | |
4496 | case DRM_FORMAT_YVYU: | |
4497 | case DRM_FORMAT_UYVY: | |
4498 | case DRM_FORMAT_VYUY: | |
4499 | break; | |
4500 | default: | |
4501 | DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n", | |
4502 | intel_plane->base.base.id, fb->base.id, fb->pixel_format); | |
4503 | return -EINVAL; | |
a1b2278e CK |
4504 | } |
4505 | ||
a1b2278e CK |
4506 | return 0; |
4507 | } | |
4508 | ||
e435d6e5 ML |
4509 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4510 | { | |
4511 | int i; | |
4512 | ||
4513 | for (i = 0; i < crtc->num_scalers; i++) | |
4514 | skl_detach_scaler(crtc, i); | |
4515 | } | |
4516 | ||
4517 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4518 | { |
4519 | struct drm_device *dev = crtc->base.dev; | |
4520 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4521 | int pipe = crtc->pipe; | |
a1b2278e CK |
4522 | struct intel_crtc_scaler_state *scaler_state = |
4523 | &crtc->config->scaler_state; | |
4524 | ||
4525 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4526 | ||
6e3c9717 | 4527 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4528 | int id; |
4529 | ||
4530 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4531 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4532 | return; | |
4533 | } | |
4534 | ||
4535 | id = scaler_state->scaler_id; | |
4536 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4537 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4538 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4539 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4540 | ||
4541 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4542 | } |
4543 | } | |
4544 | ||
b074cec8 JB |
4545 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4546 | { | |
4547 | struct drm_device *dev = crtc->base.dev; | |
4548 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4549 | int pipe = crtc->pipe; | |
4550 | ||
6e3c9717 | 4551 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4552 | /* Force use of hard-coded filter coefficients |
4553 | * as some pre-programmed values are broken, | |
4554 | * e.g. x201. | |
4555 | */ | |
4556 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4557 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4558 | PF_PIPE_SEL_IVB(pipe)); | |
4559 | else | |
4560 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4561 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4562 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4563 | } |
4564 | } | |
4565 | ||
20bc8673 | 4566 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4567 | { |
cea165c3 VS |
4568 | struct drm_device *dev = crtc->base.dev; |
4569 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 | 4570 | |
6e3c9717 | 4571 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4572 | return; |
4573 | ||
cea165c3 VS |
4574 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
4575 | intel_wait_for_vblank(dev, crtc->pipe); | |
4576 | ||
d77e4531 | 4577 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4578 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4579 | mutex_lock(&dev_priv->rps.hw_lock); |
4580 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4581 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4582 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4583 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4584 | * mailbox." Moreover, the mailbox may return a bogus state, |
4585 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4586 | */ |
4587 | } else { | |
4588 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4589 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4590 | * is essentially intel_wait_for_vblank. If we don't have this | |
4591 | * and don't wait for vblanks until the end of crtc_enable, then | |
4592 | * the HW state readout code will complain that the expected | |
4593 | * IPS_CTL value is not the one we read. */ | |
4594 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
4595 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
4596 | } | |
d77e4531 PZ |
4597 | } |
4598 | ||
20bc8673 | 4599 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4600 | { |
4601 | struct drm_device *dev = crtc->base.dev; | |
4602 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4603 | ||
6e3c9717 | 4604 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4605 | return; |
4606 | ||
4607 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4608 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4609 | mutex_lock(&dev_priv->rps.hw_lock); |
4610 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4611 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
4612 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
4613 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
4614 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 4615 | } else { |
2a114cc1 | 4616 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4617 | POSTING_READ(IPS_CTL); |
4618 | } | |
d77e4531 PZ |
4619 | |
4620 | /* We need to wait for a vblank before we can disable the plane. */ | |
4621 | intel_wait_for_vblank(dev, crtc->pipe); | |
4622 | } | |
4623 | ||
4624 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
4625 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
4626 | { | |
4627 | struct drm_device *dev = crtc->dev; | |
4628 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4629 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4630 | enum pipe pipe = intel_crtc->pipe; | |
d77e4531 PZ |
4631 | int i; |
4632 | bool reenable_ips = false; | |
4633 | ||
4634 | /* The clocks have to be on to load the palette. */ | |
53d9f4e9 | 4635 | if (!crtc->state->active) |
d77e4531 PZ |
4636 | return; |
4637 | ||
50360403 | 4638 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) { |
a65347ba | 4639 | if (intel_crtc->config->has_dsi_encoder) |
d77e4531 PZ |
4640 | assert_dsi_pll_enabled(dev_priv); |
4641 | else | |
4642 | assert_pll_enabled(dev_priv, pipe); | |
4643 | } | |
4644 | ||
d77e4531 PZ |
4645 | /* Workaround : Do not read or write the pipe palette/gamma data while |
4646 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
4647 | */ | |
6e3c9717 | 4648 | if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled && |
d77e4531 PZ |
4649 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
4650 | GAMMA_MODE_MODE_SPLIT)) { | |
4651 | hsw_disable_ips(intel_crtc); | |
4652 | reenable_ips = true; | |
4653 | } | |
4654 | ||
4655 | for (i = 0; i < 256; i++) { | |
f0f59a00 | 4656 | i915_reg_t palreg; |
f65a9c5b VS |
4657 | |
4658 | if (HAS_GMCH_DISPLAY(dev)) | |
4659 | palreg = PALETTE(pipe, i); | |
4660 | else | |
4661 | palreg = LGC_PALETTE(pipe, i); | |
4662 | ||
4663 | I915_WRITE(palreg, | |
d77e4531 PZ |
4664 | (intel_crtc->lut_r[i] << 16) | |
4665 | (intel_crtc->lut_g[i] << 8) | | |
4666 | intel_crtc->lut_b[i]); | |
4667 | } | |
4668 | ||
4669 | if (reenable_ips) | |
4670 | hsw_enable_ips(intel_crtc); | |
4671 | } | |
4672 | ||
7cac945f | 4673 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4674 | { |
7cac945f | 4675 | if (intel_crtc->overlay) { |
d3eedb1a VS |
4676 | struct drm_device *dev = intel_crtc->base.dev; |
4677 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4678 | ||
4679 | mutex_lock(&dev->struct_mutex); | |
4680 | dev_priv->mm.interruptible = false; | |
4681 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4682 | dev_priv->mm.interruptible = true; | |
4683 | mutex_unlock(&dev->struct_mutex); | |
4684 | } | |
4685 | ||
4686 | /* Let userspace switch the overlay on again. In most cases userspace | |
4687 | * has to recompute where to put it anyway. | |
4688 | */ | |
4689 | } | |
4690 | ||
87d4300a ML |
4691 | /** |
4692 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4693 | * @crtc: the CRTC whose primary plane was just enabled | |
4694 | * | |
4695 | * Performs potentially sleeping operations that must be done after the primary | |
4696 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4697 | * called due to an explicit primary plane update, or due to an implicit | |
4698 | * re-enable that is caused when a sprite plane is updated to no longer | |
4699 | * completely hide the primary plane. | |
4700 | */ | |
4701 | static void | |
4702 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4703 | { |
4704 | struct drm_device *dev = crtc->dev; | |
87d4300a | 4705 | struct drm_i915_private *dev_priv = dev->dev_private; |
a5c4d7bc VS |
4706 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4707 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4708 | |
87d4300a ML |
4709 | /* |
4710 | * BDW signals flip done immediately if the plane | |
4711 | * is disabled, even if the plane enable is already | |
4712 | * armed to occur at the next vblank :( | |
4713 | */ | |
4714 | if (IS_BROADWELL(dev)) | |
4715 | intel_wait_for_vblank(dev, pipe); | |
a5c4d7bc | 4716 | |
87d4300a ML |
4717 | /* |
4718 | * FIXME IPS should be fine as long as one plane is | |
4719 | * enabled, but in practice it seems to have problems | |
4720 | * when going from primary only to sprite only and vice | |
4721 | * versa. | |
4722 | */ | |
a5c4d7bc VS |
4723 | hsw_enable_ips(intel_crtc); |
4724 | ||
f99d7069 | 4725 | /* |
87d4300a ML |
4726 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4727 | * So don't enable underrun reporting before at least some planes | |
4728 | * are enabled. | |
4729 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4730 | * but leave the pipe running. | |
f99d7069 | 4731 | */ |
87d4300a ML |
4732 | if (IS_GEN2(dev)) |
4733 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4734 | ||
aca7b684 VS |
4735 | /* Underruns don't always raise interrupts, so check manually. */ |
4736 | intel_check_cpu_fifo_underruns(dev_priv); | |
4737 | intel_check_pch_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4738 | } |
4739 | ||
87d4300a ML |
4740 | /** |
4741 | * intel_pre_disable_primary - Perform operations before disabling primary plane | |
4742 | * @crtc: the CRTC whose primary plane is to be disabled | |
4743 | * | |
4744 | * Performs potentially sleeping operations that must be done before the | |
4745 | * primary plane is disabled, such as updating FBC and IPS. Note that this may | |
4746 | * be called due to an explicit primary plane update, or due to an implicit | |
4747 | * disable that is caused when a sprite plane completely hides the primary | |
4748 | * plane. | |
4749 | */ | |
4750 | static void | |
4751 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4752 | { |
4753 | struct drm_device *dev = crtc->dev; | |
4754 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4755 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4756 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4757 | |
87d4300a ML |
4758 | /* |
4759 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4760 | * So diasble underrun reporting before all the planes get disabled. | |
4761 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4762 | * but leave the pipe running. | |
4763 | */ | |
4764 | if (IS_GEN2(dev)) | |
4765 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
a5c4d7bc | 4766 | |
87d4300a ML |
4767 | /* |
4768 | * Vblank time updates from the shadow to live plane control register | |
4769 | * are blocked if the memory self-refresh mode is active at that | |
4770 | * moment. So to make sure the plane gets truly disabled, disable | |
4771 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4772 | * will be checked/applied by the HW only at the next frame start | |
4773 | * event which is after the vblank start event, so we need to have a | |
4774 | * wait-for-vblank between disabling the plane and the pipe. | |
4775 | */ | |
262cd2e1 | 4776 | if (HAS_GMCH_DISPLAY(dev)) { |
87d4300a | 4777 | intel_set_memory_cxsr(dev_priv, false); |
262cd2e1 VS |
4778 | dev_priv->wm.vlv.cxsr = false; |
4779 | intel_wait_for_vblank(dev, pipe); | |
4780 | } | |
87d4300a | 4781 | |
87d4300a ML |
4782 | /* |
4783 | * FIXME IPS should be fine as long as one plane is | |
4784 | * enabled, but in practice it seems to have problems | |
4785 | * when going from primary only to sprite only and vice | |
4786 | * versa. | |
4787 | */ | |
a5c4d7bc | 4788 | hsw_disable_ips(intel_crtc); |
87d4300a ML |
4789 | } |
4790 | ||
ac21b225 ML |
4791 | static void intel_post_plane_update(struct intel_crtc *crtc) |
4792 | { | |
4793 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; | |
4794 | struct drm_device *dev = crtc->base.dev; | |
7733b49b | 4795 | struct drm_i915_private *dev_priv = dev->dev_private; |
ac21b225 ML |
4796 | |
4797 | if (atomic->wait_vblank) | |
4798 | intel_wait_for_vblank(dev, crtc->pipe); | |
4799 | ||
4800 | intel_frontbuffer_flip(dev, atomic->fb_bits); | |
4801 | ||
852eb00d VS |
4802 | if (atomic->disable_cxsr) |
4803 | crtc->wm.cxsr_allowed = true; | |
4804 | ||
f015c551 VS |
4805 | if (crtc->atomic.update_wm_post) |
4806 | intel_update_watermarks(&crtc->base); | |
4807 | ||
c80ac854 | 4808 | if (atomic->update_fbc) |
7733b49b | 4809 | intel_fbc_update(dev_priv); |
ac21b225 ML |
4810 | |
4811 | if (atomic->post_enable_primary) | |
4812 | intel_post_enable_primary(&crtc->base); | |
4813 | ||
ac21b225 ML |
4814 | memset(atomic, 0, sizeof(*atomic)); |
4815 | } | |
4816 | ||
4817 | static void intel_pre_plane_update(struct intel_crtc *crtc) | |
4818 | { | |
4819 | struct drm_device *dev = crtc->base.dev; | |
eddfcbcd | 4820 | struct drm_i915_private *dev_priv = dev->dev_private; |
ac21b225 | 4821 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; |
ac21b225 | 4822 | |
c80ac854 | 4823 | if (atomic->disable_fbc) |
25ad93fd | 4824 | intel_fbc_disable_crtc(crtc); |
ac21b225 | 4825 | |
066cf55b RV |
4826 | if (crtc->atomic.disable_ips) |
4827 | hsw_disable_ips(crtc); | |
4828 | ||
ac21b225 ML |
4829 | if (atomic->pre_disable_primary) |
4830 | intel_pre_disable_primary(&crtc->base); | |
852eb00d VS |
4831 | |
4832 | if (atomic->disable_cxsr) { | |
4833 | crtc->wm.cxsr_allowed = false; | |
4834 | intel_set_memory_cxsr(dev_priv, false); | |
4835 | } | |
ac21b225 ML |
4836 | } |
4837 | ||
d032ffa0 | 4838 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
4839 | { |
4840 | struct drm_device *dev = crtc->dev; | |
4841 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 4842 | struct drm_plane *p; |
87d4300a ML |
4843 | int pipe = intel_crtc->pipe; |
4844 | ||
7cac945f | 4845 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 4846 | |
d032ffa0 ML |
4847 | drm_for_each_plane_mask(p, dev, plane_mask) |
4848 | to_intel_plane(p)->disable_plane(p, crtc); | |
f98551ae | 4849 | |
f99d7069 DV |
4850 | /* |
4851 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4852 | * to compute the mask of flip planes precisely. For the time being | |
4853 | * consider this a flip to a NULL plane. | |
4854 | */ | |
4855 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4856 | } |
4857 | ||
f67a559d JB |
4858 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4859 | { | |
4860 | struct drm_device *dev = crtc->dev; | |
4861 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4862 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4863 | struct intel_encoder *encoder; |
f67a559d | 4864 | int pipe = intel_crtc->pipe; |
f67a559d | 4865 | |
53d9f4e9 | 4866 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
4867 | return; |
4868 | ||
81b088ca VS |
4869 | if (intel_crtc->config->has_pch_encoder) |
4870 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
4871 | ||
6e3c9717 | 4872 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
4873 | intel_prepare_shared_dpll(intel_crtc); |
4874 | ||
6e3c9717 | 4875 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4876 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
4877 | |
4878 | intel_set_pipe_timings(intel_crtc); | |
4879 | ||
6e3c9717 | 4880 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 4881 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4882 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
4883 | } |
4884 | ||
4885 | ironlake_set_pipeconf(crtc); | |
4886 | ||
f67a559d | 4887 | intel_crtc->active = true; |
8664281b | 4888 | |
a72e4c9f | 4889 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
8664281b | 4890 | |
f6736a1a | 4891 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4892 | if (encoder->pre_enable) |
4893 | encoder->pre_enable(encoder); | |
f67a559d | 4894 | |
6e3c9717 | 4895 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
4896 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4897 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4898 | * enabling. */ | |
88cefb6c | 4899 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4900 | } else { |
4901 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4902 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4903 | } | |
f67a559d | 4904 | |
b074cec8 | 4905 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4906 | |
9c54c0dd JB |
4907 | /* |
4908 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4909 | * clocks enabled | |
4910 | */ | |
4911 | intel_crtc_load_lut(crtc); | |
4912 | ||
f37fcc2a | 4913 | intel_update_watermarks(crtc); |
e1fdc473 | 4914 | intel_enable_pipe(intel_crtc); |
f67a559d | 4915 | |
6e3c9717 | 4916 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 4917 | ironlake_pch_enable(crtc); |
c98e9dcf | 4918 | |
f9b61ff6 DV |
4919 | assert_vblank_disabled(crtc); |
4920 | drm_crtc_vblank_on(crtc); | |
4921 | ||
fa5c73b1 DV |
4922 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4923 | encoder->enable(encoder); | |
61b77ddd DV |
4924 | |
4925 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4926 | cpt_verify_modeset(dev, intel_crtc->pipe); |
37ca8d4c VS |
4927 | |
4928 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ | |
4929 | if (intel_crtc->config->has_pch_encoder) | |
4930 | intel_wait_for_vblank(dev, pipe); | |
4931 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
6be4a607 JB |
4932 | } |
4933 | ||
42db64ef PZ |
4934 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4935 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4936 | { | |
f5adf94e | 4937 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4938 | } |
4939 | ||
4f771f10 PZ |
4940 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4941 | { | |
4942 | struct drm_device *dev = crtc->dev; | |
4943 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4944 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4945 | struct intel_encoder *encoder; | |
99d736a2 ML |
4946 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4947 | struct intel_crtc_state *pipe_config = | |
4948 | to_intel_crtc_state(crtc->state); | |
4f771f10 | 4949 | |
53d9f4e9 | 4950 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
4951 | return; |
4952 | ||
81b088ca VS |
4953 | if (intel_crtc->config->has_pch_encoder) |
4954 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
4955 | false); | |
4956 | ||
df8ad70c DV |
4957 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
4958 | intel_enable_shared_dpll(intel_crtc); | |
4959 | ||
6e3c9717 | 4960 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4961 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 DV |
4962 | |
4963 | intel_set_pipe_timings(intel_crtc); | |
4964 | ||
6e3c9717 ACO |
4965 | if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) { |
4966 | I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder), | |
4967 | intel_crtc->config->pixel_multiplier - 1); | |
ebb69c95 CT |
4968 | } |
4969 | ||
6e3c9717 | 4970 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 4971 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4972 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
4973 | } |
4974 | ||
4975 | haswell_set_pipeconf(crtc); | |
4976 | ||
4977 | intel_set_pipe_csc(crtc); | |
4978 | ||
4f771f10 | 4979 | intel_crtc->active = true; |
8664281b | 4980 | |
a72e4c9f | 4981 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
7d4aefd0 | 4982 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 PZ |
4983 | if (encoder->pre_enable) |
4984 | encoder->pre_enable(encoder); | |
7d4aefd0 | 4985 | } |
4f771f10 | 4986 | |
d2d65408 | 4987 | if (intel_crtc->config->has_pch_encoder) |
4fe9467d | 4988 | dev_priv->display.fdi_link_train(crtc); |
4fe9467d | 4989 | |
a65347ba | 4990 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 4991 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 4992 | |
1c132b44 | 4993 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 4994 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 4995 | else |
1c132b44 | 4996 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
4997 | |
4998 | /* | |
4999 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5000 | * clocks enabled | |
5001 | */ | |
5002 | intel_crtc_load_lut(crtc); | |
5003 | ||
1f544388 | 5004 | intel_ddi_set_pipe_settings(crtc); |
a65347ba | 5005 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5006 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 5007 | |
f37fcc2a | 5008 | intel_update_watermarks(crtc); |
e1fdc473 | 5009 | intel_enable_pipe(intel_crtc); |
42db64ef | 5010 | |
6e3c9717 | 5011 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 5012 | lpt_pch_enable(crtc); |
4f771f10 | 5013 | |
a65347ba | 5014 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
5015 | intel_ddi_set_vc_payload_alloc(crtc, true); |
5016 | ||
f9b61ff6 DV |
5017 | assert_vblank_disabled(crtc); |
5018 | drm_crtc_vblank_on(crtc); | |
5019 | ||
8807e55b | 5020 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 5021 | encoder->enable(encoder); |
8807e55b JN |
5022 | intel_opregion_notify_encoder(encoder, true); |
5023 | } | |
4f771f10 | 5024 | |
d2d65408 VS |
5025 | if (intel_crtc->config->has_pch_encoder) |
5026 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5027 | true); | |
5028 | ||
e4916946 PZ |
5029 | /* If we change the relative order between pipe/planes enabling, we need |
5030 | * to change the workaround. */ | |
99d736a2 ML |
5031 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
5032 | if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) { | |
5033 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
5034 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
5035 | } | |
4f771f10 PZ |
5036 | } |
5037 | ||
bfd16b2a | 5038 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
5039 | { |
5040 | struct drm_device *dev = crtc->base.dev; | |
5041 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5042 | int pipe = crtc->pipe; | |
5043 | ||
5044 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
5045 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 5046 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
5047 | I915_WRITE(PF_CTL(pipe), 0); |
5048 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
5049 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
5050 | } | |
5051 | } | |
5052 | ||
6be4a607 JB |
5053 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
5054 | { | |
5055 | struct drm_device *dev = crtc->dev; | |
5056 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5057 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 5058 | struct intel_encoder *encoder; |
6be4a607 | 5059 | int pipe = intel_crtc->pipe; |
b52eb4dc | 5060 | |
37ca8d4c VS |
5061 | if (intel_crtc->config->has_pch_encoder) |
5062 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
5063 | ||
ea9d758d DV |
5064 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5065 | encoder->disable(encoder); | |
5066 | ||
f9b61ff6 DV |
5067 | drm_crtc_vblank_off(crtc); |
5068 | assert_vblank_disabled(crtc); | |
5069 | ||
3860b2ec VS |
5070 | /* |
5071 | * Sometimes spurious CPU pipe underruns happen when the | |
5072 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
5073 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
5074 | */ | |
5075 | if (intel_crtc->config->has_pch_encoder) | |
5076 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
5077 | ||
575f7ab7 | 5078 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5079 | |
bfd16b2a | 5080 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 5081 | |
3860b2ec | 5082 | if (intel_crtc->config->has_pch_encoder) { |
5a74f70a | 5083 | ironlake_fdi_disable(crtc); |
3860b2ec VS |
5084 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
5085 | } | |
5a74f70a | 5086 | |
bf49ec8c DV |
5087 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5088 | if (encoder->post_disable) | |
5089 | encoder->post_disable(encoder); | |
2c07245f | 5090 | |
6e3c9717 | 5091 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5092 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5093 | |
d925c59a | 5094 | if (HAS_PCH_CPT(dev)) { |
f0f59a00 VS |
5095 | i915_reg_t reg; |
5096 | u32 temp; | |
5097 | ||
d925c59a DV |
5098 | /* disable TRANS_DP_CTL */ |
5099 | reg = TRANS_DP_CTL(pipe); | |
5100 | temp = I915_READ(reg); | |
5101 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5102 | TRANS_DP_PORT_SEL_MASK); | |
5103 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5104 | I915_WRITE(reg, temp); | |
5105 | ||
5106 | /* disable DPLL_SEL */ | |
5107 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5108 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5109 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5110 | } |
e3421a18 | 5111 | |
d925c59a DV |
5112 | ironlake_fdi_pll_disable(intel_crtc); |
5113 | } | |
81b088ca VS |
5114 | |
5115 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
6be4a607 | 5116 | } |
1b3c7a47 | 5117 | |
4f771f10 | 5118 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 5119 | { |
4f771f10 PZ |
5120 | struct drm_device *dev = crtc->dev; |
5121 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 5122 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 5123 | struct intel_encoder *encoder; |
6e3c9717 | 5124 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5125 | |
d2d65408 VS |
5126 | if (intel_crtc->config->has_pch_encoder) |
5127 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5128 | false); | |
5129 | ||
8807e55b JN |
5130 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5131 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 5132 | encoder->disable(encoder); |
8807e55b | 5133 | } |
4f771f10 | 5134 | |
f9b61ff6 DV |
5135 | drm_crtc_vblank_off(crtc); |
5136 | assert_vblank_disabled(crtc); | |
5137 | ||
575f7ab7 | 5138 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5139 | |
6e3c9717 | 5140 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
5141 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5142 | ||
a65347ba | 5143 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5144 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5145 | |
1c132b44 | 5146 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5147 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5148 | else |
bfd16b2a | 5149 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 5150 | |
a65347ba | 5151 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5152 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 5153 | |
6e3c9717 | 5154 | if (intel_crtc->config->has_pch_encoder) { |
ab4d966c | 5155 | lpt_disable_pch_transcoder(dev_priv); |
1ad960f2 | 5156 | intel_ddi_fdi_disable(crtc); |
83616634 | 5157 | } |
4f771f10 | 5158 | |
97b040aa ID |
5159 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5160 | if (encoder->post_disable) | |
5161 | encoder->post_disable(encoder); | |
81b088ca VS |
5162 | |
5163 | if (intel_crtc->config->has_pch_encoder) | |
5164 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5165 | true); | |
4f771f10 PZ |
5166 | } |
5167 | ||
2dd24552 JB |
5168 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5169 | { | |
5170 | struct drm_device *dev = crtc->base.dev; | |
5171 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 5172 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5173 | |
681a8504 | 5174 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5175 | return; |
5176 | ||
2dd24552 | 5177 | /* |
c0b03411 DV |
5178 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5179 | * according to register description and PRM. | |
2dd24552 | 5180 | */ |
c0b03411 DV |
5181 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5182 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5183 | |
b074cec8 JB |
5184 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5185 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5186 | |
5187 | /* Border color in case we don't scale up to the full screen. Black by | |
5188 | * default, change to something else for debugging. */ | |
5189 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5190 | } |
5191 | ||
d05410f9 DA |
5192 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5193 | { | |
5194 | switch (port) { | |
5195 | case PORT_A: | |
6331a704 | 5196 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
d05410f9 | 5197 | case PORT_B: |
6331a704 | 5198 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
d05410f9 | 5199 | case PORT_C: |
6331a704 | 5200 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
d05410f9 | 5201 | case PORT_D: |
6331a704 | 5202 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
d8e19f99 | 5203 | case PORT_E: |
6331a704 | 5204 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
d05410f9 | 5205 | default: |
b9fec167 | 5206 | MISSING_CASE(port); |
d05410f9 DA |
5207 | return POWER_DOMAIN_PORT_OTHER; |
5208 | } | |
5209 | } | |
5210 | ||
25f78f58 VS |
5211 | static enum intel_display_power_domain port_to_aux_power_domain(enum port port) |
5212 | { | |
5213 | switch (port) { | |
5214 | case PORT_A: | |
5215 | return POWER_DOMAIN_AUX_A; | |
5216 | case PORT_B: | |
5217 | return POWER_DOMAIN_AUX_B; | |
5218 | case PORT_C: | |
5219 | return POWER_DOMAIN_AUX_C; | |
5220 | case PORT_D: | |
5221 | return POWER_DOMAIN_AUX_D; | |
5222 | case PORT_E: | |
5223 | /* FIXME: Check VBT for actual wiring of PORT E */ | |
5224 | return POWER_DOMAIN_AUX_D; | |
5225 | default: | |
b9fec167 | 5226 | MISSING_CASE(port); |
25f78f58 VS |
5227 | return POWER_DOMAIN_AUX_A; |
5228 | } | |
5229 | } | |
5230 | ||
319be8ae ID |
5231 | enum intel_display_power_domain |
5232 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5233 | { | |
5234 | struct drm_device *dev = intel_encoder->base.dev; | |
5235 | struct intel_digital_port *intel_dig_port; | |
5236 | ||
5237 | switch (intel_encoder->type) { | |
5238 | case INTEL_OUTPUT_UNKNOWN: | |
5239 | /* Only DDI platforms should ever use this output type */ | |
5240 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
5241 | case INTEL_OUTPUT_DISPLAYPORT: | |
5242 | case INTEL_OUTPUT_HDMI: | |
5243 | case INTEL_OUTPUT_EDP: | |
5244 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 5245 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
5246 | case INTEL_OUTPUT_DP_MST: |
5247 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5248 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
5249 | case INTEL_OUTPUT_ANALOG: |
5250 | return POWER_DOMAIN_PORT_CRT; | |
5251 | case INTEL_OUTPUT_DSI: | |
5252 | return POWER_DOMAIN_PORT_DSI; | |
5253 | default: | |
5254 | return POWER_DOMAIN_PORT_OTHER; | |
5255 | } | |
5256 | } | |
5257 | ||
25f78f58 VS |
5258 | enum intel_display_power_domain |
5259 | intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder) | |
5260 | { | |
5261 | struct drm_device *dev = intel_encoder->base.dev; | |
5262 | struct intel_digital_port *intel_dig_port; | |
5263 | ||
5264 | switch (intel_encoder->type) { | |
5265 | case INTEL_OUTPUT_UNKNOWN: | |
651174a4 ID |
5266 | case INTEL_OUTPUT_HDMI: |
5267 | /* | |
5268 | * Only DDI platforms should ever use these output types. | |
5269 | * We can get here after the HDMI detect code has already set | |
5270 | * the type of the shared encoder. Since we can't be sure | |
5271 | * what's the status of the given connectors, play safe and | |
5272 | * run the DP detection too. | |
5273 | */ | |
25f78f58 VS |
5274 | WARN_ON_ONCE(!HAS_DDI(dev)); |
5275 | case INTEL_OUTPUT_DISPLAYPORT: | |
5276 | case INTEL_OUTPUT_EDP: | |
5277 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
5278 | return port_to_aux_power_domain(intel_dig_port->port); | |
5279 | case INTEL_OUTPUT_DP_MST: | |
5280 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5281 | return port_to_aux_power_domain(intel_dig_port->port); | |
5282 | default: | |
b9fec167 | 5283 | MISSING_CASE(intel_encoder->type); |
25f78f58 VS |
5284 | return POWER_DOMAIN_AUX_A; |
5285 | } | |
5286 | } | |
5287 | ||
319be8ae | 5288 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) |
77d22dca | 5289 | { |
319be8ae ID |
5290 | struct drm_device *dev = crtc->dev; |
5291 | struct intel_encoder *intel_encoder; | |
5292 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5293 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca | 5294 | unsigned long mask; |
1a70a728 | 5295 | enum transcoder transcoder = intel_crtc->config->cpu_transcoder; |
77d22dca | 5296 | |
292b990e ML |
5297 | if (!crtc->state->active) |
5298 | return 0; | |
5299 | ||
77d22dca ID |
5300 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5301 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
6e3c9717 ACO |
5302 | if (intel_crtc->config->pch_pfit.enabled || |
5303 | intel_crtc->config->pch_pfit.force_thru) | |
77d22dca ID |
5304 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5305 | ||
319be8ae ID |
5306 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
5307 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); | |
5308 | ||
77d22dca ID |
5309 | return mask; |
5310 | } | |
5311 | ||
292b990e | 5312 | static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc) |
77d22dca | 5313 | { |
292b990e ML |
5314 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
5315 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5316 | enum intel_display_power_domain domain; | |
5317 | unsigned long domains, new_domains, old_domains; | |
77d22dca | 5318 | |
292b990e ML |
5319 | old_domains = intel_crtc->enabled_power_domains; |
5320 | intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc); | |
77d22dca | 5321 | |
292b990e ML |
5322 | domains = new_domains & ~old_domains; |
5323 | ||
5324 | for_each_power_domain(domain, domains) | |
5325 | intel_display_power_get(dev_priv, domain); | |
5326 | ||
5327 | return old_domains & ~new_domains; | |
5328 | } | |
5329 | ||
5330 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
5331 | unsigned long domains) | |
5332 | { | |
5333 | enum intel_display_power_domain domain; | |
5334 | ||
5335 | for_each_power_domain(domain, domains) | |
5336 | intel_display_power_put(dev_priv, domain); | |
5337 | } | |
77d22dca | 5338 | |
292b990e ML |
5339 | static void modeset_update_crtc_power_domains(struct drm_atomic_state *state) |
5340 | { | |
5341 | struct drm_device *dev = state->dev; | |
5342 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5343 | unsigned long put_domains[I915_MAX_PIPES] = {}; | |
5344 | struct drm_crtc_state *crtc_state; | |
5345 | struct drm_crtc *crtc; | |
5346 | int i; | |
77d22dca | 5347 | |
292b990e ML |
5348 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
5349 | if (needs_modeset(crtc->state)) | |
5350 | put_domains[to_intel_crtc(crtc)->pipe] = | |
5351 | modeset_get_crtc_power_domains(crtc); | |
77d22dca ID |
5352 | } |
5353 | ||
27c329ed ML |
5354 | if (dev_priv->display.modeset_commit_cdclk) { |
5355 | unsigned int cdclk = to_intel_atomic_state(state)->cdclk; | |
5356 | ||
5357 | if (cdclk != dev_priv->cdclk_freq && | |
5358 | !WARN_ON(!state->allow_modeset)) | |
5359 | dev_priv->display.modeset_commit_cdclk(state); | |
5360 | } | |
50f6e502 | 5361 | |
292b990e ML |
5362 | for (i = 0; i < I915_MAX_PIPES; i++) |
5363 | if (put_domains[i]) | |
5364 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
77d22dca ID |
5365 | } |
5366 | ||
adafdc6f MK |
5367 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
5368 | { | |
5369 | int max_cdclk_freq = dev_priv->max_cdclk_freq; | |
5370 | ||
5371 | if (INTEL_INFO(dev_priv)->gen >= 9 || | |
5372 | IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
5373 | return max_cdclk_freq; | |
5374 | else if (IS_CHERRYVIEW(dev_priv)) | |
5375 | return max_cdclk_freq*95/100; | |
5376 | else if (INTEL_INFO(dev_priv)->gen < 4) | |
5377 | return 2*max_cdclk_freq*90/100; | |
5378 | else | |
5379 | return max_cdclk_freq*90/100; | |
5380 | } | |
5381 | ||
560a7ae4 DL |
5382 | static void intel_update_max_cdclk(struct drm_device *dev) |
5383 | { | |
5384 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5385 | ||
ef11bdb3 | 5386 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
560a7ae4 DL |
5387 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; |
5388 | ||
5389 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) | |
5390 | dev_priv->max_cdclk_freq = 675000; | |
5391 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) | |
5392 | dev_priv->max_cdclk_freq = 540000; | |
5393 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) | |
5394 | dev_priv->max_cdclk_freq = 450000; | |
5395 | else | |
5396 | dev_priv->max_cdclk_freq = 337500; | |
5397 | } else if (IS_BROADWELL(dev)) { | |
5398 | /* | |
5399 | * FIXME with extra cooling we can allow | |
5400 | * 540 MHz for ULX and 675 Mhz for ULT. | |
5401 | * How can we know if extra cooling is | |
5402 | * available? PCI ID, VTB, something else? | |
5403 | */ | |
5404 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
5405 | dev_priv->max_cdclk_freq = 450000; | |
5406 | else if (IS_BDW_ULX(dev)) | |
5407 | dev_priv->max_cdclk_freq = 450000; | |
5408 | else if (IS_BDW_ULT(dev)) | |
5409 | dev_priv->max_cdclk_freq = 540000; | |
5410 | else | |
5411 | dev_priv->max_cdclk_freq = 675000; | |
0904deaf MK |
5412 | } else if (IS_CHERRYVIEW(dev)) { |
5413 | dev_priv->max_cdclk_freq = 320000; | |
560a7ae4 DL |
5414 | } else if (IS_VALLEYVIEW(dev)) { |
5415 | dev_priv->max_cdclk_freq = 400000; | |
5416 | } else { | |
5417 | /* otherwise assume cdclk is fixed */ | |
5418 | dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; | |
5419 | } | |
5420 | ||
adafdc6f MK |
5421 | dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); |
5422 | ||
560a7ae4 DL |
5423 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", |
5424 | dev_priv->max_cdclk_freq); | |
adafdc6f MK |
5425 | |
5426 | DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", | |
5427 | dev_priv->max_dotclk_freq); | |
560a7ae4 DL |
5428 | } |
5429 | ||
5430 | static void intel_update_cdclk(struct drm_device *dev) | |
5431 | { | |
5432 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5433 | ||
5434 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
5435 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", | |
5436 | dev_priv->cdclk_freq); | |
5437 | ||
5438 | /* | |
5439 | * Program the gmbus_freq based on the cdclk frequency. | |
5440 | * BSpec erroneously claims we should aim for 4MHz, but | |
5441 | * in fact 1MHz is the correct frequency. | |
5442 | */ | |
5443 | if (IS_VALLEYVIEW(dev)) { | |
5444 | /* | |
5445 | * Program the gmbus_freq based on the cdclk frequency. | |
5446 | * BSpec erroneously claims we should aim for 4MHz, but | |
5447 | * in fact 1MHz is the correct frequency. | |
5448 | */ | |
5449 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); | |
5450 | } | |
5451 | ||
5452 | if (dev_priv->max_cdclk_freq == 0) | |
5453 | intel_update_max_cdclk(dev); | |
5454 | } | |
5455 | ||
70d0c574 | 5456 | static void broxton_set_cdclk(struct drm_device *dev, int frequency) |
f8437dd1 VK |
5457 | { |
5458 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5459 | uint32_t divider; | |
5460 | uint32_t ratio; | |
5461 | uint32_t current_freq; | |
5462 | int ret; | |
5463 | ||
5464 | /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */ | |
5465 | switch (frequency) { | |
5466 | case 144000: | |
5467 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; | |
5468 | ratio = BXT_DE_PLL_RATIO(60); | |
5469 | break; | |
5470 | case 288000: | |
5471 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; | |
5472 | ratio = BXT_DE_PLL_RATIO(60); | |
5473 | break; | |
5474 | case 384000: | |
5475 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; | |
5476 | ratio = BXT_DE_PLL_RATIO(60); | |
5477 | break; | |
5478 | case 576000: | |
5479 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5480 | ratio = BXT_DE_PLL_RATIO(60); | |
5481 | break; | |
5482 | case 624000: | |
5483 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5484 | ratio = BXT_DE_PLL_RATIO(65); | |
5485 | break; | |
5486 | case 19200: | |
5487 | /* | |
5488 | * Bypass frequency with DE PLL disabled. Init ratio, divider | |
5489 | * to suppress GCC warning. | |
5490 | */ | |
5491 | ratio = 0; | |
5492 | divider = 0; | |
5493 | break; | |
5494 | default: | |
5495 | DRM_ERROR("unsupported CDCLK freq %d", frequency); | |
5496 | ||
5497 | return; | |
5498 | } | |
5499 | ||
5500 | mutex_lock(&dev_priv->rps.hw_lock); | |
5501 | /* Inform power controller of upcoming frequency change */ | |
5502 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5503 | 0x80000000); | |
5504 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5505 | ||
5506 | if (ret) { | |
5507 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
5508 | ret, frequency); | |
5509 | return; | |
5510 | } | |
5511 | ||
5512 | current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK; | |
5513 | /* convert from .1 fixpoint MHz with -1MHz offset to kHz */ | |
5514 | current_freq = current_freq * 500 + 1000; | |
5515 | ||
5516 | /* | |
5517 | * DE PLL has to be disabled when | |
5518 | * - setting to 19.2MHz (bypass, PLL isn't used) | |
5519 | * - before setting to 624MHz (PLL needs toggling) | |
5520 | * - before setting to any frequency from 624MHz (PLL needs toggling) | |
5521 | */ | |
5522 | if (frequency == 19200 || frequency == 624000 || | |
5523 | current_freq == 624000) { | |
5524 | I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE); | |
5525 | /* Timeout 200us */ | |
5526 | if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK), | |
5527 | 1)) | |
5528 | DRM_ERROR("timout waiting for DE PLL unlock\n"); | |
5529 | } | |
5530 | ||
5531 | if (frequency != 19200) { | |
5532 | uint32_t val; | |
5533 | ||
5534 | val = I915_READ(BXT_DE_PLL_CTL); | |
5535 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5536 | val |= ratio; | |
5537 | I915_WRITE(BXT_DE_PLL_CTL, val); | |
5538 | ||
5539 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5540 | /* Timeout 200us */ | |
5541 | if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1)) | |
5542 | DRM_ERROR("timeout waiting for DE PLL lock\n"); | |
5543 | ||
5544 | val = I915_READ(CDCLK_CTL); | |
5545 | val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK; | |
5546 | val |= divider; | |
5547 | /* | |
5548 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5549 | * enable otherwise. | |
5550 | */ | |
5551 | val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5552 | if (frequency >= 500000) | |
5553 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5554 | ||
5555 | val &= ~CDCLK_FREQ_DECIMAL_MASK; | |
5556 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ | |
5557 | val |= (frequency - 1000) / 500; | |
5558 | I915_WRITE(CDCLK_CTL, val); | |
5559 | } | |
5560 | ||
5561 | mutex_lock(&dev_priv->rps.hw_lock); | |
5562 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5563 | DIV_ROUND_UP(frequency, 25000)); | |
5564 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5565 | ||
5566 | if (ret) { | |
5567 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
5568 | ret, frequency); | |
5569 | return; | |
5570 | } | |
5571 | ||
a47871bd | 5572 | intel_update_cdclk(dev); |
f8437dd1 VK |
5573 | } |
5574 | ||
5575 | void broxton_init_cdclk(struct drm_device *dev) | |
5576 | { | |
5577 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5578 | uint32_t val; | |
5579 | ||
5580 | /* | |
5581 | * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT | |
5582 | * or else the reset will hang because there is no PCH to respond. | |
5583 | * Move the handshake programming to initialization sequence. | |
5584 | * Previously was left up to BIOS. | |
5585 | */ | |
5586 | val = I915_READ(HSW_NDE_RSTWRN_OPT); | |
5587 | val &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
5588 | I915_WRITE(HSW_NDE_RSTWRN_OPT, val); | |
5589 | ||
5590 | /* Enable PG1 for cdclk */ | |
5591 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); | |
5592 | ||
5593 | /* check if cd clock is enabled */ | |
5594 | if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) { | |
5595 | DRM_DEBUG_KMS("Display already initialized\n"); | |
5596 | return; | |
5597 | } | |
5598 | ||
5599 | /* | |
5600 | * FIXME: | |
5601 | * - The initial CDCLK needs to be read from VBT. | |
5602 | * Need to make this change after VBT has changes for BXT. | |
5603 | * - check if setting the max (or any) cdclk freq is really necessary | |
5604 | * here, it belongs to modeset time | |
5605 | */ | |
5606 | broxton_set_cdclk(dev, 624000); | |
5607 | ||
5608 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
22e02c0b VS |
5609 | POSTING_READ(DBUF_CTL); |
5610 | ||
f8437dd1 VK |
5611 | udelay(10); |
5612 | ||
5613 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5614 | DRM_ERROR("DBuf power enable timeout!\n"); | |
5615 | } | |
5616 | ||
5617 | void broxton_uninit_cdclk(struct drm_device *dev) | |
5618 | { | |
5619 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5620 | ||
5621 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
22e02c0b VS |
5622 | POSTING_READ(DBUF_CTL); |
5623 | ||
f8437dd1 VK |
5624 | udelay(10); |
5625 | ||
5626 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5627 | DRM_ERROR("DBuf power disable timeout!\n"); | |
5628 | ||
5629 | /* Set minimum (bypass) frequency, in effect turning off the DE PLL */ | |
5630 | broxton_set_cdclk(dev, 19200); | |
5631 | ||
5632 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
5633 | } | |
5634 | ||
5d96d8af DL |
5635 | static const struct skl_cdclk_entry { |
5636 | unsigned int freq; | |
5637 | unsigned int vco; | |
5638 | } skl_cdclk_frequencies[] = { | |
5639 | { .freq = 308570, .vco = 8640 }, | |
5640 | { .freq = 337500, .vco = 8100 }, | |
5641 | { .freq = 432000, .vco = 8640 }, | |
5642 | { .freq = 450000, .vco = 8100 }, | |
5643 | { .freq = 540000, .vco = 8100 }, | |
5644 | { .freq = 617140, .vco = 8640 }, | |
5645 | { .freq = 675000, .vco = 8100 }, | |
5646 | }; | |
5647 | ||
5648 | static unsigned int skl_cdclk_decimal(unsigned int freq) | |
5649 | { | |
5650 | return (freq - 1000) / 500; | |
5651 | } | |
5652 | ||
5653 | static unsigned int skl_cdclk_get_vco(unsigned int freq) | |
5654 | { | |
5655 | unsigned int i; | |
5656 | ||
5657 | for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) { | |
5658 | const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i]; | |
5659 | ||
5660 | if (e->freq == freq) | |
5661 | return e->vco; | |
5662 | } | |
5663 | ||
5664 | return 8100; | |
5665 | } | |
5666 | ||
5667 | static void | |
5668 | skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco) | |
5669 | { | |
5670 | unsigned int min_freq; | |
5671 | u32 val; | |
5672 | ||
5673 | /* select the minimum CDCLK before enabling DPLL 0 */ | |
5674 | val = I915_READ(CDCLK_CTL); | |
5675 | val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK; | |
5676 | val |= CDCLK_FREQ_337_308; | |
5677 | ||
5678 | if (required_vco == 8640) | |
5679 | min_freq = 308570; | |
5680 | else | |
5681 | min_freq = 337500; | |
5682 | ||
5683 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq); | |
5684 | ||
5685 | I915_WRITE(CDCLK_CTL, val); | |
5686 | POSTING_READ(CDCLK_CTL); | |
5687 | ||
5688 | /* | |
5689 | * We always enable DPLL0 with the lowest link rate possible, but still | |
5690 | * taking into account the VCO required to operate the eDP panel at the | |
5691 | * desired frequency. The usual DP link rates operate with a VCO of | |
5692 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. | |
5693 | * The modeset code is responsible for the selection of the exact link | |
5694 | * rate later on, with the constraint of choosing a frequency that | |
5695 | * works with required_vco. | |
5696 | */ | |
5697 | val = I915_READ(DPLL_CTRL1); | |
5698 | ||
5699 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
5700 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
5701 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
5702 | if (required_vco == 8640) | |
5703 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, | |
5704 | SKL_DPLL0); | |
5705 | else | |
5706 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, | |
5707 | SKL_DPLL0); | |
5708 | ||
5709 | I915_WRITE(DPLL_CTRL1, val); | |
5710 | POSTING_READ(DPLL_CTRL1); | |
5711 | ||
5712 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); | |
5713 | ||
5714 | if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5)) | |
5715 | DRM_ERROR("DPLL0 not locked\n"); | |
5716 | } | |
5717 | ||
5718 | static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) | |
5719 | { | |
5720 | int ret; | |
5721 | u32 val; | |
5722 | ||
5723 | /* inform PCU we want to change CDCLK */ | |
5724 | val = SKL_CDCLK_PREPARE_FOR_CHANGE; | |
5725 | mutex_lock(&dev_priv->rps.hw_lock); | |
5726 | ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); | |
5727 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5728 | ||
5729 | return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE); | |
5730 | } | |
5731 | ||
5732 | static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) | |
5733 | { | |
5734 | unsigned int i; | |
5735 | ||
5736 | for (i = 0; i < 15; i++) { | |
5737 | if (skl_cdclk_pcu_ready(dev_priv)) | |
5738 | return true; | |
5739 | udelay(10); | |
5740 | } | |
5741 | ||
5742 | return false; | |
5743 | } | |
5744 | ||
5745 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq) | |
5746 | { | |
560a7ae4 | 5747 | struct drm_device *dev = dev_priv->dev; |
5d96d8af DL |
5748 | u32 freq_select, pcu_ack; |
5749 | ||
5750 | DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq); | |
5751 | ||
5752 | if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { | |
5753 | DRM_ERROR("failed to inform PCU about cdclk change\n"); | |
5754 | return; | |
5755 | } | |
5756 | ||
5757 | /* set CDCLK_CTL */ | |
5758 | switch(freq) { | |
5759 | case 450000: | |
5760 | case 432000: | |
5761 | freq_select = CDCLK_FREQ_450_432; | |
5762 | pcu_ack = 1; | |
5763 | break; | |
5764 | case 540000: | |
5765 | freq_select = CDCLK_FREQ_540; | |
5766 | pcu_ack = 2; | |
5767 | break; | |
5768 | case 308570: | |
5769 | case 337500: | |
5770 | default: | |
5771 | freq_select = CDCLK_FREQ_337_308; | |
5772 | pcu_ack = 0; | |
5773 | break; | |
5774 | case 617140: | |
5775 | case 675000: | |
5776 | freq_select = CDCLK_FREQ_675_617; | |
5777 | pcu_ack = 3; | |
5778 | break; | |
5779 | } | |
5780 | ||
5781 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq)); | |
5782 | POSTING_READ(CDCLK_CTL); | |
5783 | ||
5784 | /* inform PCU of the change */ | |
5785 | mutex_lock(&dev_priv->rps.hw_lock); | |
5786 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); | |
5787 | mutex_unlock(&dev_priv->rps.hw_lock); | |
560a7ae4 DL |
5788 | |
5789 | intel_update_cdclk(dev); | |
5d96d8af DL |
5790 | } |
5791 | ||
5792 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) | |
5793 | { | |
5794 | /* disable DBUF power */ | |
5795 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
5796 | POSTING_READ(DBUF_CTL); | |
5797 | ||
5798 | udelay(10); | |
5799 | ||
5800 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5801 | DRM_ERROR("DBuf power disable timeout\n"); | |
5802 | ||
ab96c1ee ID |
5803 | /* disable DPLL0 */ |
5804 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); | |
5805 | if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) | |
5806 | DRM_ERROR("Couldn't disable DPLL0\n"); | |
5d96d8af DL |
5807 | } |
5808 | ||
5809 | void skl_init_cdclk(struct drm_i915_private *dev_priv) | |
5810 | { | |
5d96d8af DL |
5811 | unsigned int required_vco; |
5812 | ||
39d9b85a GW |
5813 | /* DPLL0 not enabled (happens on early BIOS versions) */ |
5814 | if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) { | |
5815 | /* enable DPLL0 */ | |
5816 | required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk); | |
5817 | skl_dpll0_enable(dev_priv, required_vco); | |
5d96d8af DL |
5818 | } |
5819 | ||
5d96d8af DL |
5820 | /* set CDCLK to the frequency the BIOS chose */ |
5821 | skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk); | |
5822 | ||
5823 | /* enable DBUF power */ | |
5824 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
5825 | POSTING_READ(DBUF_CTL); | |
5826 | ||
5827 | udelay(10); | |
5828 | ||
5829 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5830 | DRM_ERROR("DBuf power enable timeout\n"); | |
5831 | } | |
5832 | ||
c73666f3 SK |
5833 | int skl_sanitize_cdclk(struct drm_i915_private *dev_priv) |
5834 | { | |
5835 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
5836 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
5837 | int freq = dev_priv->skl_boot_cdclk; | |
5838 | ||
f1b391a5 SK |
5839 | /* |
5840 | * check if the pre-os intialized the display | |
5841 | * There is SWF18 scratchpad register defined which is set by the | |
5842 | * pre-os which can be used by the OS drivers to check the status | |
5843 | */ | |
5844 | if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) | |
5845 | goto sanitize; | |
5846 | ||
c73666f3 SK |
5847 | /* Is PLL enabled and locked ? */ |
5848 | if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK))) | |
5849 | goto sanitize; | |
5850 | ||
5851 | /* DPLL okay; verify the cdclock | |
5852 | * | |
5853 | * Noticed in some instances that the freq selection is correct but | |
5854 | * decimal part is programmed wrong from BIOS where pre-os does not | |
5855 | * enable display. Verify the same as well. | |
5856 | */ | |
5857 | if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq))) | |
5858 | /* All well; nothing to sanitize */ | |
5859 | return false; | |
5860 | sanitize: | |
5861 | /* | |
5862 | * As of now initialize with max cdclk till | |
5863 | * we get dynamic cdclk support | |
5864 | * */ | |
5865 | dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq; | |
5866 | skl_init_cdclk(dev_priv); | |
5867 | ||
5868 | /* we did have to sanitize */ | |
5869 | return true; | |
5870 | } | |
5871 | ||
30a970c6 JB |
5872 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
5873 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
5874 | { | |
5875 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5876 | u32 val, cmd; | |
5877 | ||
164dfd28 VK |
5878 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5879 | != dev_priv->cdclk_freq); | |
d60c4473 | 5880 | |
dfcab17e | 5881 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 5882 | cmd = 2; |
dfcab17e | 5883 | else if (cdclk == 266667) |
30a970c6 JB |
5884 | cmd = 1; |
5885 | else | |
5886 | cmd = 0; | |
5887 | ||
5888 | mutex_lock(&dev_priv->rps.hw_lock); | |
5889 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5890 | val &= ~DSPFREQGUAR_MASK; | |
5891 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
5892 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5893 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5894 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
5895 | 50)) { | |
5896 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5897 | } | |
5898 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5899 | ||
54433e91 VS |
5900 | mutex_lock(&dev_priv->sb_lock); |
5901 | ||
dfcab17e | 5902 | if (cdclk == 400000) { |
6bcda4f0 | 5903 | u32 divider; |
30a970c6 | 5904 | |
6bcda4f0 | 5905 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 | 5906 | |
30a970c6 JB |
5907 | /* adjust cdclk divider */ |
5908 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
87d5d259 | 5909 | val &= ~CCK_FREQUENCY_VALUES; |
30a970c6 JB |
5910 | val |= divider; |
5911 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
5912 | |
5913 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
87d5d259 | 5914 | CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), |
a877e801 VS |
5915 | 50)) |
5916 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
5917 | } |
5918 | ||
30a970c6 JB |
5919 | /* adjust self-refresh exit latency value */ |
5920 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
5921 | val &= ~0x7f; | |
5922 | ||
5923 | /* | |
5924 | * For high bandwidth configs, we set a higher latency in the bunit | |
5925 | * so that the core display fetch happens in time to avoid underruns. | |
5926 | */ | |
dfcab17e | 5927 | if (cdclk == 400000) |
30a970c6 JB |
5928 | val |= 4500 / 250; /* 4.5 usec */ |
5929 | else | |
5930 | val |= 3000 / 250; /* 3.0 usec */ | |
5931 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
54433e91 | 5932 | |
a580516d | 5933 | mutex_unlock(&dev_priv->sb_lock); |
30a970c6 | 5934 | |
b6283055 | 5935 | intel_update_cdclk(dev); |
30a970c6 JB |
5936 | } |
5937 | ||
383c5a6a VS |
5938 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
5939 | { | |
5940 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5941 | u32 val, cmd; | |
5942 | ||
164dfd28 VK |
5943 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5944 | != dev_priv->cdclk_freq); | |
383c5a6a VS |
5945 | |
5946 | switch (cdclk) { | |
383c5a6a VS |
5947 | case 333333: |
5948 | case 320000: | |
383c5a6a | 5949 | case 266667: |
383c5a6a | 5950 | case 200000: |
383c5a6a VS |
5951 | break; |
5952 | default: | |
5f77eeb0 | 5953 | MISSING_CASE(cdclk); |
383c5a6a VS |
5954 | return; |
5955 | } | |
5956 | ||
9d0d3fda VS |
5957 | /* |
5958 | * Specs are full of misinformation, but testing on actual | |
5959 | * hardware has shown that we just need to write the desired | |
5960 | * CCK divider into the Punit register. | |
5961 | */ | |
5962 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
5963 | ||
383c5a6a VS |
5964 | mutex_lock(&dev_priv->rps.hw_lock); |
5965 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5966 | val &= ~DSPFREQGUAR_MASK_CHV; | |
5967 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
5968 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5969 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5970 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
5971 | 50)) { | |
5972 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5973 | } | |
5974 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5975 | ||
b6283055 | 5976 | intel_update_cdclk(dev); |
383c5a6a VS |
5977 | } |
5978 | ||
30a970c6 JB |
5979 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
5980 | int max_pixclk) | |
5981 | { | |
6bcda4f0 | 5982 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 5983 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 5984 | |
30a970c6 JB |
5985 | /* |
5986 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
5987 | * 200MHz | |
5988 | * 267MHz | |
29dc7ef3 | 5989 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
5990 | * 400MHz (VLV only) |
5991 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
5992 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
5993 | * |
5994 | * We seem to get an unstable or solid color picture at 200MHz. | |
5995 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
5996 | * are off. | |
30a970c6 | 5997 | */ |
6cca3195 VS |
5998 | if (!IS_CHERRYVIEW(dev_priv) && |
5999 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 6000 | return 400000; |
6cca3195 | 6001 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 6002 | return freq_320; |
e37c67a1 | 6003 | else if (max_pixclk > 0) |
dfcab17e | 6004 | return 266667; |
e37c67a1 VS |
6005 | else |
6006 | return 200000; | |
30a970c6 JB |
6007 | } |
6008 | ||
f8437dd1 VK |
6009 | static int broxton_calc_cdclk(struct drm_i915_private *dev_priv, |
6010 | int max_pixclk) | |
6011 | { | |
6012 | /* | |
6013 | * FIXME: | |
6014 | * - remove the guardband, it's not needed on BXT | |
6015 | * - set 19.2MHz bypass frequency if there are no active pipes | |
6016 | */ | |
6017 | if (max_pixclk > 576000*9/10) | |
6018 | return 624000; | |
6019 | else if (max_pixclk > 384000*9/10) | |
6020 | return 576000; | |
6021 | else if (max_pixclk > 288000*9/10) | |
6022 | return 384000; | |
6023 | else if (max_pixclk > 144000*9/10) | |
6024 | return 288000; | |
6025 | else | |
6026 | return 144000; | |
6027 | } | |
6028 | ||
a821fc46 ACO |
6029 | /* Compute the max pixel clock for new configuration. Uses atomic state if |
6030 | * that's non-NULL, look at current state otherwise. */ | |
6031 | static int intel_mode_max_pixclk(struct drm_device *dev, | |
6032 | struct drm_atomic_state *state) | |
30a970c6 | 6033 | { |
30a970c6 | 6034 | struct intel_crtc *intel_crtc; |
304603f4 | 6035 | struct intel_crtc_state *crtc_state; |
30a970c6 JB |
6036 | int max_pixclk = 0; |
6037 | ||
d3fcc808 | 6038 | for_each_intel_crtc(dev, intel_crtc) { |
27c329ed | 6039 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
304603f4 ACO |
6040 | if (IS_ERR(crtc_state)) |
6041 | return PTR_ERR(crtc_state); | |
6042 | ||
6043 | if (!crtc_state->base.enable) | |
6044 | continue; | |
6045 | ||
6046 | max_pixclk = max(max_pixclk, | |
6047 | crtc_state->base.adjusted_mode.crtc_clock); | |
30a970c6 JB |
6048 | } |
6049 | ||
6050 | return max_pixclk; | |
6051 | } | |
6052 | ||
27c329ed | 6053 | static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) |
30a970c6 | 6054 | { |
27c329ed ML |
6055 | struct drm_device *dev = state->dev; |
6056 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6057 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
30a970c6 | 6058 | |
304603f4 ACO |
6059 | if (max_pixclk < 0) |
6060 | return max_pixclk; | |
30a970c6 | 6061 | |
27c329ed ML |
6062 | to_intel_atomic_state(state)->cdclk = |
6063 | valleyview_calc_cdclk(dev_priv, max_pixclk); | |
0a9ab303 | 6064 | |
27c329ed ML |
6065 | return 0; |
6066 | } | |
304603f4 | 6067 | |
27c329ed ML |
6068 | static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state) |
6069 | { | |
6070 | struct drm_device *dev = state->dev; | |
6071 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6072 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
85a96e7a | 6073 | |
27c329ed ML |
6074 | if (max_pixclk < 0) |
6075 | return max_pixclk; | |
85a96e7a | 6076 | |
27c329ed ML |
6077 | to_intel_atomic_state(state)->cdclk = |
6078 | broxton_calc_cdclk(dev_priv, max_pixclk); | |
85a96e7a | 6079 | |
27c329ed | 6080 | return 0; |
30a970c6 JB |
6081 | } |
6082 | ||
1e69cd74 VS |
6083 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
6084 | { | |
6085 | unsigned int credits, default_credits; | |
6086 | ||
6087 | if (IS_CHERRYVIEW(dev_priv)) | |
6088 | default_credits = PFI_CREDIT(12); | |
6089 | else | |
6090 | default_credits = PFI_CREDIT(8); | |
6091 | ||
bfa7df01 | 6092 | if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) { |
1e69cd74 VS |
6093 | /* CHV suggested value is 31 or 63 */ |
6094 | if (IS_CHERRYVIEW(dev_priv)) | |
fcc0008f | 6095 | credits = PFI_CREDIT_63; |
1e69cd74 VS |
6096 | else |
6097 | credits = PFI_CREDIT(15); | |
6098 | } else { | |
6099 | credits = default_credits; | |
6100 | } | |
6101 | ||
6102 | /* | |
6103 | * WA - write default credits before re-programming | |
6104 | * FIXME: should we also set the resend bit here? | |
6105 | */ | |
6106 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6107 | default_credits); | |
6108 | ||
6109 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6110 | credits | PFI_CREDIT_RESEND); | |
6111 | ||
6112 | /* | |
6113 | * FIXME is this guaranteed to clear | |
6114 | * immediately or should we poll for it? | |
6115 | */ | |
6116 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
6117 | } | |
6118 | ||
27c329ed | 6119 | static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
30a970c6 | 6120 | { |
a821fc46 | 6121 | struct drm_device *dev = old_state->dev; |
27c329ed | 6122 | unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk; |
30a970c6 | 6123 | struct drm_i915_private *dev_priv = dev->dev_private; |
30a970c6 | 6124 | |
27c329ed ML |
6125 | /* |
6126 | * FIXME: We can end up here with all power domains off, yet | |
6127 | * with a CDCLK frequency other than the minimum. To account | |
6128 | * for this take the PIPE-A power domain, which covers the HW | |
6129 | * blocks needed for the following programming. This can be | |
6130 | * removed once it's guaranteed that we get here either with | |
6131 | * the minimum CDCLK set, or the required power domains | |
6132 | * enabled. | |
6133 | */ | |
6134 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
738c05c0 | 6135 | |
27c329ed ML |
6136 | if (IS_CHERRYVIEW(dev)) |
6137 | cherryview_set_cdclk(dev, req_cdclk); | |
6138 | else | |
6139 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 6140 | |
27c329ed | 6141 | vlv_program_pfi_credits(dev_priv); |
1e69cd74 | 6142 | |
27c329ed | 6143 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
30a970c6 JB |
6144 | } |
6145 | ||
89b667f8 JB |
6146 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
6147 | { | |
6148 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6149 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
6150 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6151 | struct intel_encoder *encoder; | |
6152 | int pipe = intel_crtc->pipe; | |
89b667f8 | 6153 | |
53d9f4e9 | 6154 | if (WARN_ON(intel_crtc->active)) |
89b667f8 JB |
6155 | return; |
6156 | ||
6e3c9717 | 6157 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6158 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6159 | |
6160 | intel_set_pipe_timings(intel_crtc); | |
6161 | ||
c14b0485 VS |
6162 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
6163 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6164 | ||
6165 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
6166 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
6167 | } | |
6168 | ||
5b18e57c DV |
6169 | i9xx_set_pipeconf(intel_crtc); |
6170 | ||
89b667f8 | 6171 | intel_crtc->active = true; |
89b667f8 | 6172 | |
a72e4c9f | 6173 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6174 | |
89b667f8 JB |
6175 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6176 | if (encoder->pre_pll_enable) | |
6177 | encoder->pre_pll_enable(encoder); | |
6178 | ||
a65347ba | 6179 | if (!intel_crtc->config->has_dsi_encoder) { |
c0b4c660 VS |
6180 | if (IS_CHERRYVIEW(dev)) { |
6181 | chv_prepare_pll(intel_crtc, intel_crtc->config); | |
6e3c9717 | 6182 | chv_enable_pll(intel_crtc, intel_crtc->config); |
c0b4c660 VS |
6183 | } else { |
6184 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
6e3c9717 | 6185 | vlv_enable_pll(intel_crtc, intel_crtc->config); |
c0b4c660 | 6186 | } |
9d556c99 | 6187 | } |
89b667f8 JB |
6188 | |
6189 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
6190 | if (encoder->pre_enable) | |
6191 | encoder->pre_enable(encoder); | |
6192 | ||
2dd24552 JB |
6193 | i9xx_pfit_enable(intel_crtc); |
6194 | ||
63cbb074 VS |
6195 | intel_crtc_load_lut(crtc); |
6196 | ||
e1fdc473 | 6197 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6198 | |
4b3a9526 VS |
6199 | assert_vblank_disabled(crtc); |
6200 | drm_crtc_vblank_on(crtc); | |
6201 | ||
f9b61ff6 DV |
6202 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6203 | encoder->enable(encoder); | |
89b667f8 JB |
6204 | } |
6205 | ||
f13c2ef3 DV |
6206 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
6207 | { | |
6208 | struct drm_device *dev = crtc->base.dev; | |
6209 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6210 | ||
6e3c9717 ACO |
6211 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
6212 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
6213 | } |
6214 | ||
0b8765c6 | 6215 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
6216 | { |
6217 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6218 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 6219 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 6220 | struct intel_encoder *encoder; |
79e53945 | 6221 | int pipe = intel_crtc->pipe; |
79e53945 | 6222 | |
53d9f4e9 | 6223 | if (WARN_ON(intel_crtc->active)) |
f7abfe8b CW |
6224 | return; |
6225 | ||
f13c2ef3 DV |
6226 | i9xx_set_pll_dividers(intel_crtc); |
6227 | ||
6e3c9717 | 6228 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6229 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6230 | |
6231 | intel_set_pipe_timings(intel_crtc); | |
6232 | ||
5b18e57c DV |
6233 | i9xx_set_pipeconf(intel_crtc); |
6234 | ||
f7abfe8b | 6235 | intel_crtc->active = true; |
6b383a7f | 6236 | |
4a3436e8 | 6237 | if (!IS_GEN2(dev)) |
a72e4c9f | 6238 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6239 | |
9d6d9f19 MK |
6240 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6241 | if (encoder->pre_enable) | |
6242 | encoder->pre_enable(encoder); | |
6243 | ||
f6736a1a DV |
6244 | i9xx_enable_pll(intel_crtc); |
6245 | ||
2dd24552 JB |
6246 | i9xx_pfit_enable(intel_crtc); |
6247 | ||
63cbb074 VS |
6248 | intel_crtc_load_lut(crtc); |
6249 | ||
f37fcc2a | 6250 | intel_update_watermarks(crtc); |
e1fdc473 | 6251 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6252 | |
4b3a9526 VS |
6253 | assert_vblank_disabled(crtc); |
6254 | drm_crtc_vblank_on(crtc); | |
6255 | ||
f9b61ff6 DV |
6256 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6257 | encoder->enable(encoder); | |
0b8765c6 | 6258 | } |
79e53945 | 6259 | |
87476d63 DV |
6260 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
6261 | { | |
6262 | struct drm_device *dev = crtc->base.dev; | |
6263 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 6264 | |
6e3c9717 | 6265 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 6266 | return; |
87476d63 | 6267 | |
328d8e82 | 6268 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 6269 | |
328d8e82 DV |
6270 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
6271 | I915_READ(PFIT_CONTROL)); | |
6272 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
6273 | } |
6274 | ||
0b8765c6 JB |
6275 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
6276 | { | |
6277 | struct drm_device *dev = crtc->dev; | |
6278 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6279 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 6280 | struct intel_encoder *encoder; |
0b8765c6 | 6281 | int pipe = intel_crtc->pipe; |
ef9c3aee | 6282 | |
6304cd91 VS |
6283 | /* |
6284 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
6285 | * wait for planes to fully turn off before disabling the pipe. | |
564ed191 ID |
6286 | * We also need to wait on all gmch platforms because of the |
6287 | * self-refresh mode constraint explained above. | |
6304cd91 | 6288 | */ |
564ed191 | 6289 | intel_wait_for_vblank(dev, pipe); |
6304cd91 | 6290 | |
4b3a9526 VS |
6291 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6292 | encoder->disable(encoder); | |
6293 | ||
f9b61ff6 DV |
6294 | drm_crtc_vblank_off(crtc); |
6295 | assert_vblank_disabled(crtc); | |
6296 | ||
575f7ab7 | 6297 | intel_disable_pipe(intel_crtc); |
24a1f16d | 6298 | |
87476d63 | 6299 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 6300 | |
89b667f8 JB |
6301 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6302 | if (encoder->post_disable) | |
6303 | encoder->post_disable(encoder); | |
6304 | ||
a65347ba | 6305 | if (!intel_crtc->config->has_dsi_encoder) { |
076ed3b2 CML |
6306 | if (IS_CHERRYVIEW(dev)) |
6307 | chv_disable_pll(dev_priv, pipe); | |
6308 | else if (IS_VALLEYVIEW(dev)) | |
6309 | vlv_disable_pll(dev_priv, pipe); | |
6310 | else | |
1c4e0274 | 6311 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 6312 | } |
0b8765c6 | 6313 | |
d6db995f VS |
6314 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6315 | if (encoder->post_pll_disable) | |
6316 | encoder->post_pll_disable(encoder); | |
6317 | ||
4a3436e8 | 6318 | if (!IS_GEN2(dev)) |
a72e4c9f | 6319 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
0b8765c6 JB |
6320 | } |
6321 | ||
b17d48e2 ML |
6322 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
6323 | { | |
6324 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6325 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
6326 | enum intel_display_power_domain domain; | |
6327 | unsigned long domains; | |
6328 | ||
6329 | if (!intel_crtc->active) | |
6330 | return; | |
6331 | ||
a539205a | 6332 | if (to_intel_plane_state(crtc->primary->state)->visible) { |
fc32b1fd ML |
6333 | WARN_ON(intel_crtc->unpin_work); |
6334 | ||
a539205a ML |
6335 | intel_pre_disable_primary(crtc); |
6336 | } | |
6337 | ||
d032ffa0 | 6338 | intel_crtc_disable_planes(crtc, crtc->state->plane_mask); |
b17d48e2 | 6339 | dev_priv->display.crtc_disable(crtc); |
37d9078b MR |
6340 | intel_crtc->active = false; |
6341 | intel_update_watermarks(crtc); | |
1f7457b1 | 6342 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
6343 | |
6344 | domains = intel_crtc->enabled_power_domains; | |
6345 | for_each_power_domain(domain, domains) | |
6346 | intel_display_power_put(dev_priv, domain); | |
6347 | intel_crtc->enabled_power_domains = 0; | |
6348 | } | |
6349 | ||
6b72d486 ML |
6350 | /* |
6351 | * turn all crtc's off, but do not adjust state | |
6352 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
6353 | */ | |
70e0bd74 | 6354 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 6355 | { |
70e0bd74 ML |
6356 | struct drm_mode_config *config = &dev->mode_config; |
6357 | struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx; | |
6358 | struct drm_atomic_state *state; | |
6b72d486 | 6359 | struct drm_crtc *crtc; |
70e0bd74 ML |
6360 | unsigned crtc_mask = 0; |
6361 | int ret = 0; | |
6362 | ||
6363 | if (WARN_ON(!ctx)) | |
6364 | return 0; | |
6365 | ||
6366 | lockdep_assert_held(&ctx->ww_ctx); | |
6367 | state = drm_atomic_state_alloc(dev); | |
6368 | if (WARN_ON(!state)) | |
6369 | return -ENOMEM; | |
6370 | ||
6371 | state->acquire_ctx = ctx; | |
6372 | state->allow_modeset = true; | |
6373 | ||
6374 | for_each_crtc(dev, crtc) { | |
6375 | struct drm_crtc_state *crtc_state = | |
6376 | drm_atomic_get_crtc_state(state, crtc); | |
6b72d486 | 6377 | |
70e0bd74 ML |
6378 | ret = PTR_ERR_OR_ZERO(crtc_state); |
6379 | if (ret) | |
6380 | goto free; | |
6381 | ||
6382 | if (!crtc_state->active) | |
6383 | continue; | |
6384 | ||
6385 | crtc_state->active = false; | |
6386 | crtc_mask |= 1 << drm_crtc_index(crtc); | |
6387 | } | |
6388 | ||
6389 | if (crtc_mask) { | |
74c090b1 | 6390 | ret = drm_atomic_commit(state); |
70e0bd74 ML |
6391 | |
6392 | if (!ret) { | |
6393 | for_each_crtc(dev, crtc) | |
6394 | if (crtc_mask & (1 << drm_crtc_index(crtc))) | |
6395 | crtc->state->active = true; | |
6396 | ||
6397 | return ret; | |
6398 | } | |
6399 | } | |
6400 | ||
6401 | free: | |
6402 | if (ret) | |
6403 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
6404 | drm_atomic_state_free(state); | |
6405 | return ret; | |
ee7b9f93 JB |
6406 | } |
6407 | ||
ea5b213a | 6408 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6409 | { |
4ef69c7a | 6410 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6411 | |
ea5b213a CW |
6412 | drm_encoder_cleanup(encoder); |
6413 | kfree(intel_encoder); | |
7e7d76c3 JB |
6414 | } |
6415 | ||
0a91ca29 DV |
6416 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6417 | * internal consistency). */ | |
b980514c | 6418 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 6419 | { |
35dd3c64 ML |
6420 | struct drm_crtc *crtc = connector->base.state->crtc; |
6421 | ||
6422 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6423 | connector->base.base.id, | |
6424 | connector->base.name); | |
6425 | ||
0a91ca29 | 6426 | if (connector->get_hw_state(connector)) { |
e85376cb | 6427 | struct intel_encoder *encoder = connector->encoder; |
35dd3c64 | 6428 | struct drm_connector_state *conn_state = connector->base.state; |
0a91ca29 | 6429 | |
35dd3c64 ML |
6430 | I915_STATE_WARN(!crtc, |
6431 | "connector enabled without attached crtc\n"); | |
0a91ca29 | 6432 | |
35dd3c64 ML |
6433 | if (!crtc) |
6434 | return; | |
6435 | ||
6436 | I915_STATE_WARN(!crtc->state->active, | |
6437 | "connector is active, but attached crtc isn't\n"); | |
6438 | ||
e85376cb | 6439 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
6440 | return; |
6441 | ||
e85376cb | 6442 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
6443 | "atomic encoder doesn't match attached encoder\n"); |
6444 | ||
e85376cb | 6445 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
6446 | "attached encoder crtc differs from connector crtc\n"); |
6447 | } else { | |
4d688a2a ML |
6448 | I915_STATE_WARN(crtc && crtc->state->active, |
6449 | "attached crtc is active, but connector isn't\n"); | |
35dd3c64 ML |
6450 | I915_STATE_WARN(!crtc && connector->base.state->best_encoder, |
6451 | "best encoder set without crtc!\n"); | |
0a91ca29 | 6452 | } |
79e53945 JB |
6453 | } |
6454 | ||
08d9bc92 ACO |
6455 | int intel_connector_init(struct intel_connector *connector) |
6456 | { | |
6457 | struct drm_connector_state *connector_state; | |
6458 | ||
6459 | connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL); | |
6460 | if (!connector_state) | |
6461 | return -ENOMEM; | |
6462 | ||
6463 | connector->base.state = connector_state; | |
6464 | return 0; | |
6465 | } | |
6466 | ||
6467 | struct intel_connector *intel_connector_alloc(void) | |
6468 | { | |
6469 | struct intel_connector *connector; | |
6470 | ||
6471 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6472 | if (!connector) | |
6473 | return NULL; | |
6474 | ||
6475 | if (intel_connector_init(connector) < 0) { | |
6476 | kfree(connector); | |
6477 | return NULL; | |
6478 | } | |
6479 | ||
6480 | return connector; | |
6481 | } | |
6482 | ||
f0947c37 DV |
6483 | /* Simple connector->get_hw_state implementation for encoders that support only |
6484 | * one connector and no cloning and hence the encoder state determines the state | |
6485 | * of the connector. */ | |
6486 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6487 | { |
24929352 | 6488 | enum pipe pipe = 0; |
f0947c37 | 6489 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6490 | |
f0947c37 | 6491 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6492 | } |
6493 | ||
6d293983 | 6494 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6495 | { |
6d293983 ACO |
6496 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6497 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6498 | |
6499 | return 0; | |
6500 | } | |
6501 | ||
6d293983 | 6502 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6503 | struct intel_crtc_state *pipe_config) |
1857e1da | 6504 | { |
6d293983 ACO |
6505 | struct drm_atomic_state *state = pipe_config->base.state; |
6506 | struct intel_crtc *other_crtc; | |
6507 | struct intel_crtc_state *other_crtc_state; | |
6508 | ||
1857e1da DV |
6509 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6510 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6511 | if (pipe_config->fdi_lanes > 4) { | |
6512 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6513 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6514 | return -EINVAL; |
1857e1da DV |
6515 | } |
6516 | ||
bafb6553 | 6517 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
6518 | if (pipe_config->fdi_lanes > 2) { |
6519 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6520 | pipe_config->fdi_lanes); | |
6d293983 | 6521 | return -EINVAL; |
1857e1da | 6522 | } else { |
6d293983 | 6523 | return 0; |
1857e1da DV |
6524 | } |
6525 | } | |
6526 | ||
6527 | if (INTEL_INFO(dev)->num_pipes == 2) | |
6d293983 | 6528 | return 0; |
1857e1da DV |
6529 | |
6530 | /* Ivybridge 3 pipe is really complicated */ | |
6531 | switch (pipe) { | |
6532 | case PIPE_A: | |
6d293983 | 6533 | return 0; |
1857e1da | 6534 | case PIPE_B: |
6d293983 ACO |
6535 | if (pipe_config->fdi_lanes <= 2) |
6536 | return 0; | |
6537 | ||
6538 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); | |
6539 | other_crtc_state = | |
6540 | intel_atomic_get_crtc_state(state, other_crtc); | |
6541 | if (IS_ERR(other_crtc_state)) | |
6542 | return PTR_ERR(other_crtc_state); | |
6543 | ||
6544 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6545 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6546 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6547 | return -EINVAL; |
1857e1da | 6548 | } |
6d293983 | 6549 | return 0; |
1857e1da | 6550 | case PIPE_C: |
251cc67c VS |
6551 | if (pipe_config->fdi_lanes > 2) { |
6552 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6553 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6554 | return -EINVAL; |
251cc67c | 6555 | } |
6d293983 ACO |
6556 | |
6557 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); | |
6558 | other_crtc_state = | |
6559 | intel_atomic_get_crtc_state(state, other_crtc); | |
6560 | if (IS_ERR(other_crtc_state)) | |
6561 | return PTR_ERR(other_crtc_state); | |
6562 | ||
6563 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6564 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6565 | return -EINVAL; |
1857e1da | 6566 | } |
6d293983 | 6567 | return 0; |
1857e1da DV |
6568 | default: |
6569 | BUG(); | |
6570 | } | |
6571 | } | |
6572 | ||
e29c22c0 DV |
6573 | #define RETRY 1 |
6574 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6575 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6576 | { |
1857e1da | 6577 | struct drm_device *dev = intel_crtc->base.dev; |
7c5f93b0 | 6578 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6579 | int lane, link_bw, fdi_dotclock, ret; |
6580 | bool needs_recompute = false; | |
877d48d5 | 6581 | |
e29c22c0 | 6582 | retry: |
877d48d5 DV |
6583 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6584 | * each output octet as 10 bits. The actual frequency | |
6585 | * is stored as a divider into a 100MHz clock, and the | |
6586 | * mode pixel clock is stored in units of 1KHz. | |
6587 | * Hence the bw of each lane in terms of the mode signal | |
6588 | * is: | |
6589 | */ | |
6590 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
6591 | ||
241bfc38 | 6592 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6593 | |
2bd89a07 | 6594 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6595 | pipe_config->pipe_bpp); |
6596 | ||
6597 | pipe_config->fdi_lanes = lane; | |
6598 | ||
2bd89a07 | 6599 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 6600 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 6601 | |
6d293983 ACO |
6602 | ret = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
6603 | intel_crtc->pipe, pipe_config); | |
6604 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { | |
e29c22c0 DV |
6605 | pipe_config->pipe_bpp -= 2*3; |
6606 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
6607 | pipe_config->pipe_bpp); | |
6608 | needs_recompute = true; | |
6609 | pipe_config->bw_constrained = true; | |
6610 | ||
6611 | goto retry; | |
6612 | } | |
6613 | ||
6614 | if (needs_recompute) | |
6615 | return RETRY; | |
6616 | ||
6d293983 | 6617 | return ret; |
877d48d5 DV |
6618 | } |
6619 | ||
8cfb3407 VS |
6620 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
6621 | struct intel_crtc_state *pipe_config) | |
6622 | { | |
6623 | if (pipe_config->pipe_bpp > 24) | |
6624 | return false; | |
6625 | ||
6626 | /* HSW can handle pixel rate up to cdclk? */ | |
6627 | if (IS_HASWELL(dev_priv->dev)) | |
6628 | return true; | |
6629 | ||
6630 | /* | |
b432e5cf VS |
6631 | * We compare against max which means we must take |
6632 | * the increased cdclk requirement into account when | |
6633 | * calculating the new cdclk. | |
6634 | * | |
6635 | * Should measure whether using a lower cdclk w/o IPS | |
8cfb3407 VS |
6636 | */ |
6637 | return ilk_pipe_pixel_rate(pipe_config) <= | |
6638 | dev_priv->max_cdclk_freq * 95 / 100; | |
6639 | } | |
6640 | ||
42db64ef | 6641 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 6642 | struct intel_crtc_state *pipe_config) |
42db64ef | 6643 | { |
8cfb3407 VS |
6644 | struct drm_device *dev = crtc->base.dev; |
6645 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6646 | ||
d330a953 | 6647 | pipe_config->ips_enabled = i915.enable_ips && |
8cfb3407 VS |
6648 | hsw_crtc_supports_ips(crtc) && |
6649 | pipe_config_supports_ips(dev_priv, pipe_config); | |
42db64ef PZ |
6650 | } |
6651 | ||
39acb4aa VS |
6652 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
6653 | { | |
6654 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
6655 | ||
6656 | /* GDG double wide on either pipe, otherwise pipe A only */ | |
6657 | return INTEL_INFO(dev_priv)->gen < 4 && | |
6658 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); | |
6659 | } | |
6660 | ||
a43f6e0f | 6661 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 6662 | struct intel_crtc_state *pipe_config) |
79e53945 | 6663 | { |
a43f6e0f | 6664 | struct drm_device *dev = crtc->base.dev; |
8bd31e67 | 6665 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c5f93b0 | 6666 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
89749350 | 6667 | |
ad3a4479 | 6668 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 | 6669 | if (INTEL_INFO(dev)->gen < 4) { |
39acb4aa | 6670 | int clock_limit = dev_priv->max_cdclk_freq * 9 / 10; |
cf532bb2 VS |
6671 | |
6672 | /* | |
39acb4aa | 6673 | * Enable double wide mode when the dot clock |
cf532bb2 | 6674 | * is > 90% of the (display) core speed. |
cf532bb2 | 6675 | */ |
39acb4aa VS |
6676 | if (intel_crtc_supports_double_wide(crtc) && |
6677 | adjusted_mode->crtc_clock > clock_limit) { | |
ad3a4479 | 6678 | clock_limit *= 2; |
cf532bb2 | 6679 | pipe_config->double_wide = true; |
ad3a4479 VS |
6680 | } |
6681 | ||
39acb4aa VS |
6682 | if (adjusted_mode->crtc_clock > clock_limit) { |
6683 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
6684 | adjusted_mode->crtc_clock, clock_limit, | |
6685 | yesno(pipe_config->double_wide)); | |
e29c22c0 | 6686 | return -EINVAL; |
39acb4aa | 6687 | } |
2c07245f | 6688 | } |
89749350 | 6689 | |
1d1d0e27 VS |
6690 | /* |
6691 | * Pipe horizontal size must be even in: | |
6692 | * - DVO ganged mode | |
6693 | * - LVDS dual channel mode | |
6694 | * - Double wide pipe | |
6695 | */ | |
a93e255f | 6696 | if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
6697 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
6698 | pipe_config->pipe_src_w &= ~1; | |
6699 | ||
8693a824 DL |
6700 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6701 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
6702 | */ |
6703 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
aad941d5 | 6704 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) |
e29c22c0 | 6705 | return -EINVAL; |
44f46b42 | 6706 | |
f5adf94e | 6707 | if (HAS_IPS(dev)) |
a43f6e0f DV |
6708 | hsw_compute_ips_config(crtc, pipe_config); |
6709 | ||
877d48d5 | 6710 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 6711 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 6712 | |
cf5a15be | 6713 | return 0; |
79e53945 JB |
6714 | } |
6715 | ||
1652d19e VS |
6716 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
6717 | { | |
6718 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6719 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
6720 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6721 | uint32_t linkrate; | |
6722 | ||
414355a7 | 6723 | if (!(lcpll1 & LCPLL_PLL_ENABLE)) |
1652d19e | 6724 | return 24000; /* 24MHz is the cd freq with NSSC ref */ |
1652d19e VS |
6725 | |
6726 | if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) | |
6727 | return 540000; | |
6728 | ||
6729 | linkrate = (I915_READ(DPLL_CTRL1) & | |
71cd8423 | 6730 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; |
1652d19e | 6731 | |
71cd8423 DL |
6732 | if (linkrate == DPLL_CTRL1_LINK_RATE_2160 || |
6733 | linkrate == DPLL_CTRL1_LINK_RATE_1080) { | |
1652d19e VS |
6734 | /* vco 8640 */ |
6735 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6736 | case CDCLK_FREQ_450_432: | |
6737 | return 432000; | |
6738 | case CDCLK_FREQ_337_308: | |
6739 | return 308570; | |
6740 | case CDCLK_FREQ_675_617: | |
6741 | return 617140; | |
6742 | default: | |
6743 | WARN(1, "Unknown cd freq selection\n"); | |
6744 | } | |
6745 | } else { | |
6746 | /* vco 8100 */ | |
6747 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6748 | case CDCLK_FREQ_450_432: | |
6749 | return 450000; | |
6750 | case CDCLK_FREQ_337_308: | |
6751 | return 337500; | |
6752 | case CDCLK_FREQ_675_617: | |
6753 | return 675000; | |
6754 | default: | |
6755 | WARN(1, "Unknown cd freq selection\n"); | |
6756 | } | |
6757 | } | |
6758 | ||
6759 | /* error case, do as if DPLL0 isn't enabled */ | |
6760 | return 24000; | |
6761 | } | |
6762 | ||
acd3f3d3 BP |
6763 | static int broxton_get_display_clock_speed(struct drm_device *dev) |
6764 | { | |
6765 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6766 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6767 | uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; | |
6768 | uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE); | |
6769 | int cdclk; | |
6770 | ||
6771 | if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE)) | |
6772 | return 19200; | |
6773 | ||
6774 | cdclk = 19200 * pll_ratio / 2; | |
6775 | ||
6776 | switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) { | |
6777 | case BXT_CDCLK_CD2X_DIV_SEL_1: | |
6778 | return cdclk; /* 576MHz or 624MHz */ | |
6779 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: | |
6780 | return cdclk * 2 / 3; /* 384MHz */ | |
6781 | case BXT_CDCLK_CD2X_DIV_SEL_2: | |
6782 | return cdclk / 2; /* 288MHz */ | |
6783 | case BXT_CDCLK_CD2X_DIV_SEL_4: | |
6784 | return cdclk / 4; /* 144MHz */ | |
6785 | } | |
6786 | ||
6787 | /* error case, do as if DE PLL isn't enabled */ | |
6788 | return 19200; | |
6789 | } | |
6790 | ||
1652d19e VS |
6791 | static int broadwell_get_display_clock_speed(struct drm_device *dev) |
6792 | { | |
6793 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6794 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6795 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6796 | ||
6797 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6798 | return 800000; | |
6799 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6800 | return 450000; | |
6801 | else if (freq == LCPLL_CLK_FREQ_450) | |
6802 | return 450000; | |
6803 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
6804 | return 540000; | |
6805 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
6806 | return 337500; | |
6807 | else | |
6808 | return 675000; | |
6809 | } | |
6810 | ||
6811 | static int haswell_get_display_clock_speed(struct drm_device *dev) | |
6812 | { | |
6813 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6814 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6815 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6816 | ||
6817 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6818 | return 800000; | |
6819 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6820 | return 450000; | |
6821 | else if (freq == LCPLL_CLK_FREQ_450) | |
6822 | return 450000; | |
6823 | else if (IS_HSW_ULT(dev)) | |
6824 | return 337500; | |
6825 | else | |
6826 | return 540000; | |
79e53945 JB |
6827 | } |
6828 | ||
25eb05fc JB |
6829 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
6830 | { | |
bfa7df01 VS |
6831 | return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk", |
6832 | CCK_DISPLAY_CLOCK_CONTROL); | |
25eb05fc JB |
6833 | } |
6834 | ||
b37a6434 VS |
6835 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
6836 | { | |
6837 | return 450000; | |
6838 | } | |
6839 | ||
e70236a8 JB |
6840 | static int i945_get_display_clock_speed(struct drm_device *dev) |
6841 | { | |
6842 | return 400000; | |
6843 | } | |
79e53945 | 6844 | |
e70236a8 | 6845 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 6846 | { |
e907f170 | 6847 | return 333333; |
e70236a8 | 6848 | } |
79e53945 | 6849 | |
e70236a8 JB |
6850 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
6851 | { | |
6852 | return 200000; | |
6853 | } | |
79e53945 | 6854 | |
257a7ffc DV |
6855 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
6856 | { | |
6857 | u16 gcfgc = 0; | |
6858 | ||
6859 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
6860 | ||
6861 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6862 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 6863 | return 266667; |
257a7ffc | 6864 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 6865 | return 333333; |
257a7ffc | 6866 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 6867 | return 444444; |
257a7ffc DV |
6868 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
6869 | return 200000; | |
6870 | default: | |
6871 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
6872 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 6873 | return 133333; |
257a7ffc | 6874 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 6875 | return 166667; |
257a7ffc DV |
6876 | } |
6877 | } | |
6878 | ||
e70236a8 JB |
6879 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
6880 | { | |
6881 | u16 gcfgc = 0; | |
79e53945 | 6882 | |
e70236a8 JB |
6883 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
6884 | ||
6885 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 6886 | return 133333; |
e70236a8 JB |
6887 | else { |
6888 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6889 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 6890 | return 333333; |
e70236a8 JB |
6891 | default: |
6892 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
6893 | return 190000; | |
79e53945 | 6894 | } |
e70236a8 JB |
6895 | } |
6896 | } | |
6897 | ||
6898 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
6899 | { | |
e907f170 | 6900 | return 266667; |
e70236a8 JB |
6901 | } |
6902 | ||
1b1d2716 | 6903 | static int i85x_get_display_clock_speed(struct drm_device *dev) |
e70236a8 JB |
6904 | { |
6905 | u16 hpllcc = 0; | |
1b1d2716 | 6906 | |
65cd2b3f VS |
6907 | /* |
6908 | * 852GM/852GMV only supports 133 MHz and the HPLLCC | |
6909 | * encoding is different :( | |
6910 | * FIXME is this the right way to detect 852GM/852GMV? | |
6911 | */ | |
6912 | if (dev->pdev->revision == 0x1) | |
6913 | return 133333; | |
6914 | ||
1b1d2716 VS |
6915 | pci_bus_read_config_word(dev->pdev->bus, |
6916 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); | |
6917 | ||
e70236a8 JB |
6918 | /* Assume that the hardware is in the high speed state. This |
6919 | * should be the default. | |
6920 | */ | |
6921 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
6922 | case GC_CLOCK_133_200: | |
1b1d2716 | 6923 | case GC_CLOCK_133_200_2: |
e70236a8 JB |
6924 | case GC_CLOCK_100_200: |
6925 | return 200000; | |
6926 | case GC_CLOCK_166_250: | |
6927 | return 250000; | |
6928 | case GC_CLOCK_100_133: | |
e907f170 | 6929 | return 133333; |
1b1d2716 VS |
6930 | case GC_CLOCK_133_266: |
6931 | case GC_CLOCK_133_266_2: | |
6932 | case GC_CLOCK_166_266: | |
6933 | return 266667; | |
e70236a8 | 6934 | } |
79e53945 | 6935 | |
e70236a8 JB |
6936 | /* Shouldn't happen */ |
6937 | return 0; | |
6938 | } | |
79e53945 | 6939 | |
e70236a8 JB |
6940 | static int i830_get_display_clock_speed(struct drm_device *dev) |
6941 | { | |
e907f170 | 6942 | return 133333; |
79e53945 JB |
6943 | } |
6944 | ||
34edce2f VS |
6945 | static unsigned int intel_hpll_vco(struct drm_device *dev) |
6946 | { | |
6947 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6948 | static const unsigned int blb_vco[8] = { | |
6949 | [0] = 3200000, | |
6950 | [1] = 4000000, | |
6951 | [2] = 5333333, | |
6952 | [3] = 4800000, | |
6953 | [4] = 6400000, | |
6954 | }; | |
6955 | static const unsigned int pnv_vco[8] = { | |
6956 | [0] = 3200000, | |
6957 | [1] = 4000000, | |
6958 | [2] = 5333333, | |
6959 | [3] = 4800000, | |
6960 | [4] = 2666667, | |
6961 | }; | |
6962 | static const unsigned int cl_vco[8] = { | |
6963 | [0] = 3200000, | |
6964 | [1] = 4000000, | |
6965 | [2] = 5333333, | |
6966 | [3] = 6400000, | |
6967 | [4] = 3333333, | |
6968 | [5] = 3566667, | |
6969 | [6] = 4266667, | |
6970 | }; | |
6971 | static const unsigned int elk_vco[8] = { | |
6972 | [0] = 3200000, | |
6973 | [1] = 4000000, | |
6974 | [2] = 5333333, | |
6975 | [3] = 4800000, | |
6976 | }; | |
6977 | static const unsigned int ctg_vco[8] = { | |
6978 | [0] = 3200000, | |
6979 | [1] = 4000000, | |
6980 | [2] = 5333333, | |
6981 | [3] = 6400000, | |
6982 | [4] = 2666667, | |
6983 | [5] = 4266667, | |
6984 | }; | |
6985 | const unsigned int *vco_table; | |
6986 | unsigned int vco; | |
6987 | uint8_t tmp = 0; | |
6988 | ||
6989 | /* FIXME other chipsets? */ | |
6990 | if (IS_GM45(dev)) | |
6991 | vco_table = ctg_vco; | |
6992 | else if (IS_G4X(dev)) | |
6993 | vco_table = elk_vco; | |
6994 | else if (IS_CRESTLINE(dev)) | |
6995 | vco_table = cl_vco; | |
6996 | else if (IS_PINEVIEW(dev)) | |
6997 | vco_table = pnv_vco; | |
6998 | else if (IS_G33(dev)) | |
6999 | vco_table = blb_vco; | |
7000 | else | |
7001 | return 0; | |
7002 | ||
7003 | tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO); | |
7004 | ||
7005 | vco = vco_table[tmp & 0x7]; | |
7006 | if (vco == 0) | |
7007 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); | |
7008 | else | |
7009 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); | |
7010 | ||
7011 | return vco; | |
7012 | } | |
7013 | ||
7014 | static int gm45_get_display_clock_speed(struct drm_device *dev) | |
7015 | { | |
7016 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7017 | uint16_t tmp = 0; | |
7018 | ||
7019 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7020 | ||
7021 | cdclk_sel = (tmp >> 12) & 0x1; | |
7022 | ||
7023 | switch (vco) { | |
7024 | case 2666667: | |
7025 | case 4000000: | |
7026 | case 5333333: | |
7027 | return cdclk_sel ? 333333 : 222222; | |
7028 | case 3200000: | |
7029 | return cdclk_sel ? 320000 : 228571; | |
7030 | default: | |
7031 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); | |
7032 | return 222222; | |
7033 | } | |
7034 | } | |
7035 | ||
7036 | static int i965gm_get_display_clock_speed(struct drm_device *dev) | |
7037 | { | |
7038 | static const uint8_t div_3200[] = { 16, 10, 8 }; | |
7039 | static const uint8_t div_4000[] = { 20, 12, 10 }; | |
7040 | static const uint8_t div_5333[] = { 24, 16, 14 }; | |
7041 | const uint8_t *div_table; | |
7042 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7043 | uint16_t tmp = 0; | |
7044 | ||
7045 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7046 | ||
7047 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; | |
7048 | ||
7049 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7050 | goto fail; | |
7051 | ||
7052 | switch (vco) { | |
7053 | case 3200000: | |
7054 | div_table = div_3200; | |
7055 | break; | |
7056 | case 4000000: | |
7057 | div_table = div_4000; | |
7058 | break; | |
7059 | case 5333333: | |
7060 | div_table = div_5333; | |
7061 | break; | |
7062 | default: | |
7063 | goto fail; | |
7064 | } | |
7065 | ||
7066 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7067 | ||
caf4e252 | 7068 | fail: |
34edce2f VS |
7069 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); |
7070 | return 200000; | |
7071 | } | |
7072 | ||
7073 | static int g33_get_display_clock_speed(struct drm_device *dev) | |
7074 | { | |
7075 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; | |
7076 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; | |
7077 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; | |
7078 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; | |
7079 | const uint8_t *div_table; | |
7080 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7081 | uint16_t tmp = 0; | |
7082 | ||
7083 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7084 | ||
7085 | cdclk_sel = (tmp >> 4) & 0x7; | |
7086 | ||
7087 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7088 | goto fail; | |
7089 | ||
7090 | switch (vco) { | |
7091 | case 3200000: | |
7092 | div_table = div_3200; | |
7093 | break; | |
7094 | case 4000000: | |
7095 | div_table = div_4000; | |
7096 | break; | |
7097 | case 4800000: | |
7098 | div_table = div_4800; | |
7099 | break; | |
7100 | case 5333333: | |
7101 | div_table = div_5333; | |
7102 | break; | |
7103 | default: | |
7104 | goto fail; | |
7105 | } | |
7106 | ||
7107 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7108 | ||
caf4e252 | 7109 | fail: |
34edce2f VS |
7110 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); |
7111 | return 190476; | |
7112 | } | |
7113 | ||
2c07245f | 7114 | static void |
a65851af | 7115 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 7116 | { |
a65851af VS |
7117 | while (*num > DATA_LINK_M_N_MASK || |
7118 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
7119 | *num >>= 1; |
7120 | *den >>= 1; | |
7121 | } | |
7122 | } | |
7123 | ||
a65851af VS |
7124 | static void compute_m_n(unsigned int m, unsigned int n, |
7125 | uint32_t *ret_m, uint32_t *ret_n) | |
7126 | { | |
7127 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
7128 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
7129 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
7130 | } | |
7131 | ||
e69d0bc1 DV |
7132 | void |
7133 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
7134 | int pixel_clock, int link_clock, | |
7135 | struct intel_link_m_n *m_n) | |
2c07245f | 7136 | { |
e69d0bc1 | 7137 | m_n->tu = 64; |
a65851af VS |
7138 | |
7139 | compute_m_n(bits_per_pixel * pixel_clock, | |
7140 | link_clock * nlanes * 8, | |
7141 | &m_n->gmch_m, &m_n->gmch_n); | |
7142 | ||
7143 | compute_m_n(pixel_clock, link_clock, | |
7144 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
7145 | } |
7146 | ||
a7615030 CW |
7147 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
7148 | { | |
d330a953 JN |
7149 | if (i915.panel_use_ssc >= 0) |
7150 | return i915.panel_use_ssc != 0; | |
41aa3448 | 7151 | return dev_priv->vbt.lvds_use_ssc |
435793df | 7152 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
7153 | } |
7154 | ||
a93e255f ACO |
7155 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
7156 | int num_connectors) | |
c65d77d8 | 7157 | { |
a93e255f | 7158 | struct drm_device *dev = crtc_state->base.crtc->dev; |
c65d77d8 JB |
7159 | struct drm_i915_private *dev_priv = dev->dev_private; |
7160 | int refclk; | |
7161 | ||
a93e255f ACO |
7162 | WARN_ON(!crtc_state->base.state); |
7163 | ||
5ab7b0b7 | 7164 | if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) { |
9a0ea498 | 7165 | refclk = 100000; |
a93e255f | 7166 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 7167 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
7168 | refclk = dev_priv->vbt.lvds_ssc_freq; |
7169 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
7170 | } else if (!IS_GEN2(dev)) { |
7171 | refclk = 96000; | |
7172 | } else { | |
7173 | refclk = 48000; | |
7174 | } | |
7175 | ||
7176 | return refclk; | |
7177 | } | |
7178 | ||
7429e9d4 | 7179 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 7180 | { |
7df00d7a | 7181 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 7182 | } |
f47709a9 | 7183 | |
7429e9d4 DV |
7184 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
7185 | { | |
7186 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
7187 | } |
7188 | ||
f47709a9 | 7189 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 7190 | struct intel_crtc_state *crtc_state, |
a7516a05 JB |
7191 | intel_clock_t *reduced_clock) |
7192 | { | |
f47709a9 | 7193 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
7194 | u32 fp, fp2 = 0; |
7195 | ||
7196 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 7197 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7198 | if (reduced_clock) |
7429e9d4 | 7199 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 7200 | } else { |
190f68c5 | 7201 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7202 | if (reduced_clock) |
7429e9d4 | 7203 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
7204 | } |
7205 | ||
190f68c5 | 7206 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 7207 | |
f47709a9 | 7208 | crtc->lowfreq_avail = false; |
a93e255f | 7209 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 7210 | reduced_clock) { |
190f68c5 | 7211 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 7212 | crtc->lowfreq_avail = true; |
a7516a05 | 7213 | } else { |
190f68c5 | 7214 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
7215 | } |
7216 | } | |
7217 | ||
5e69f97f CML |
7218 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
7219 | pipe) | |
89b667f8 JB |
7220 | { |
7221 | u32 reg_val; | |
7222 | ||
7223 | /* | |
7224 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
7225 | * and set it to a reasonable value instead. | |
7226 | */ | |
ab3c759a | 7227 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
7228 | reg_val &= 0xffffff00; |
7229 | reg_val |= 0x00000030; | |
ab3c759a | 7230 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7231 | |
ab3c759a | 7232 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7233 | reg_val &= 0x8cffffff; |
7234 | reg_val = 0x8c000000; | |
ab3c759a | 7235 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 7236 | |
ab3c759a | 7237 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 7238 | reg_val &= 0xffffff00; |
ab3c759a | 7239 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7240 | |
ab3c759a | 7241 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7242 | reg_val &= 0x00ffffff; |
7243 | reg_val |= 0xb0000000; | |
ab3c759a | 7244 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
7245 | } |
7246 | ||
b551842d DV |
7247 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
7248 | struct intel_link_m_n *m_n) | |
7249 | { | |
7250 | struct drm_device *dev = crtc->base.dev; | |
7251 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7252 | int pipe = crtc->pipe; | |
7253 | ||
e3b95f1e DV |
7254 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7255 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
7256 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
7257 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
7258 | } |
7259 | ||
7260 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
7261 | struct intel_link_m_n *m_n, |
7262 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
7263 | { |
7264 | struct drm_device *dev = crtc->base.dev; | |
7265 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7266 | int pipe = crtc->pipe; | |
6e3c9717 | 7267 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
7268 | |
7269 | if (INTEL_INFO(dev)->gen >= 5) { | |
7270 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
7271 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
7272 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
7273 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
7274 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
7275 | * for gen < 8) and if DRRS is supported (to make sure the | |
7276 | * registers are not unnecessarily accessed). | |
7277 | */ | |
44395bfe | 7278 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 7279 | crtc->config->has_drrs) { |
f769cd24 VK |
7280 | I915_WRITE(PIPE_DATA_M2(transcoder), |
7281 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
7282 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
7283 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
7284 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
7285 | } | |
b551842d | 7286 | } else { |
e3b95f1e DV |
7287 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7288 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
7289 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
7290 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
7291 | } |
7292 | } | |
7293 | ||
fe3cd48d | 7294 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 7295 | { |
fe3cd48d R |
7296 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
7297 | ||
7298 | if (m_n == M1_N1) { | |
7299 | dp_m_n = &crtc->config->dp_m_n; | |
7300 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
7301 | } else if (m_n == M2_N2) { | |
7302 | ||
7303 | /* | |
7304 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
7305 | * needs to be programmed into M1_N1. | |
7306 | */ | |
7307 | dp_m_n = &crtc->config->dp_m2_n2; | |
7308 | } else { | |
7309 | DRM_ERROR("Unsupported divider value\n"); | |
7310 | return; | |
7311 | } | |
7312 | ||
6e3c9717 ACO |
7313 | if (crtc->config->has_pch_encoder) |
7314 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 7315 | else |
fe3cd48d | 7316 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
7317 | } |
7318 | ||
251ac862 DV |
7319 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
7320 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 DV |
7321 | { |
7322 | u32 dpll, dpll_md; | |
7323 | ||
7324 | /* | |
7325 | * Enable DPIO clock input. We should never disable the reference | |
7326 | * clock for pipe B, since VGA hotplug / manual detection depends | |
7327 | * on it. | |
7328 | */ | |
60bfe44f VS |
7329 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV | |
7330 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV; | |
bdd4b6a6 DV |
7331 | /* We should never disable this, set it here for state tracking */ |
7332 | if (crtc->pipe == PIPE_B) | |
7333 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
7334 | dpll |= DPLL_VCO_ENABLE; | |
d288f65f | 7335 | pipe_config->dpll_hw_state.dpll = dpll; |
bdd4b6a6 | 7336 | |
d288f65f | 7337 | dpll_md = (pipe_config->pixel_multiplier - 1) |
bdd4b6a6 | 7338 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
d288f65f | 7339 | pipe_config->dpll_hw_state.dpll_md = dpll_md; |
bdd4b6a6 DV |
7340 | } |
7341 | ||
d288f65f | 7342 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7343 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 7344 | { |
f47709a9 | 7345 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 7346 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 7347 | int pipe = crtc->pipe; |
bdd4b6a6 | 7348 | u32 mdiv; |
a0c4da24 | 7349 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 7350 | u32 coreclk, reg_val; |
a0c4da24 | 7351 | |
a580516d | 7352 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 7353 | |
d288f65f VS |
7354 | bestn = pipe_config->dpll.n; |
7355 | bestm1 = pipe_config->dpll.m1; | |
7356 | bestm2 = pipe_config->dpll.m2; | |
7357 | bestp1 = pipe_config->dpll.p1; | |
7358 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 7359 | |
89b667f8 JB |
7360 | /* See eDP HDMI DPIO driver vbios notes doc */ |
7361 | ||
7362 | /* PLL B needs special handling */ | |
bdd4b6a6 | 7363 | if (pipe == PIPE_B) |
5e69f97f | 7364 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
7365 | |
7366 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 7367 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
7368 | |
7369 | /* Disable target IRef on PLL */ | |
ab3c759a | 7370 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 7371 | reg_val &= 0x00ffffff; |
ab3c759a | 7372 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
7373 | |
7374 | /* Disable fast lock */ | |
ab3c759a | 7375 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
7376 | |
7377 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
7378 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
7379 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
7380 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 7381 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
7382 | |
7383 | /* | |
7384 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
7385 | * but we don't support that). | |
7386 | * Note: don't use the DAC post divider as it seems unstable. | |
7387 | */ | |
7388 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 7389 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7390 | |
a0c4da24 | 7391 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 7392 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7393 | |
89b667f8 | 7394 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 7395 | if (pipe_config->port_clock == 162000 || |
409ee761 ACO |
7396 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || |
7397 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 7398 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 7399 | 0x009f0003); |
89b667f8 | 7400 | else |
ab3c759a | 7401 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
7402 | 0x00d0000f); |
7403 | ||
681a8504 | 7404 | if (pipe_config->has_dp_encoder) { |
89b667f8 | 7405 | /* Use SSC source */ |
bdd4b6a6 | 7406 | if (pipe == PIPE_A) |
ab3c759a | 7407 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7408 | 0x0df40000); |
7409 | else | |
ab3c759a | 7410 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7411 | 0x0df70000); |
7412 | } else { /* HDMI or VGA */ | |
7413 | /* Use bend source */ | |
bdd4b6a6 | 7414 | if (pipe == PIPE_A) |
ab3c759a | 7415 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7416 | 0x0df70000); |
7417 | else | |
ab3c759a | 7418 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7419 | 0x0df40000); |
7420 | } | |
a0c4da24 | 7421 | |
ab3c759a | 7422 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 7423 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
409ee761 ACO |
7424 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
7425 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) | |
89b667f8 | 7426 | coreclk |= 0x01000000; |
ab3c759a | 7427 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 7428 | |
ab3c759a | 7429 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 7430 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
7431 | } |
7432 | ||
251ac862 DV |
7433 | static void chv_compute_dpll(struct intel_crtc *crtc, |
7434 | struct intel_crtc_state *pipe_config) | |
1ae0d137 | 7435 | { |
60bfe44f VS |
7436 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | |
7437 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | | |
1ae0d137 VS |
7438 | DPLL_VCO_ENABLE; |
7439 | if (crtc->pipe != PIPE_A) | |
d288f65f | 7440 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
1ae0d137 | 7441 | |
d288f65f VS |
7442 | pipe_config->dpll_hw_state.dpll_md = |
7443 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
1ae0d137 VS |
7444 | } |
7445 | ||
d288f65f | 7446 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7447 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
7448 | { |
7449 | struct drm_device *dev = crtc->base.dev; | |
7450 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7451 | int pipe = crtc->pipe; | |
f0f59a00 | 7452 | i915_reg_t dpll_reg = DPLL(crtc->pipe); |
9d556c99 | 7453 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9cbe40c1 | 7454 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 7455 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 7456 | u32 dpio_val; |
9cbe40c1 | 7457 | int vco; |
9d556c99 | 7458 | |
d288f65f VS |
7459 | bestn = pipe_config->dpll.n; |
7460 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
7461 | bestm1 = pipe_config->dpll.m1; | |
7462 | bestm2 = pipe_config->dpll.m2 >> 22; | |
7463 | bestp1 = pipe_config->dpll.p1; | |
7464 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 7465 | vco = pipe_config->dpll.vco; |
a945ce7e | 7466 | dpio_val = 0; |
9cbe40c1 | 7467 | loopfilter = 0; |
9d556c99 CML |
7468 | |
7469 | /* | |
7470 | * Enable Refclk and SSC | |
7471 | */ | |
a11b0703 | 7472 | I915_WRITE(dpll_reg, |
d288f65f | 7473 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
a11b0703 | 7474 | |
a580516d | 7475 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 7476 | |
9d556c99 CML |
7477 | /* p1 and p2 divider */ |
7478 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
7479 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
7480 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
7481 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
7482 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
7483 | ||
7484 | /* Feedback post-divider - m2 */ | |
7485 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
7486 | ||
7487 | /* Feedback refclk divider - n and m1 */ | |
7488 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
7489 | DPIO_CHV_M1_DIV_BY_2 | | |
7490 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
7491 | ||
7492 | /* M2 fraction division */ | |
25a25dfc | 7493 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
7494 | |
7495 | /* M2 fraction division enable */ | |
a945ce7e VP |
7496 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
7497 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
7498 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
7499 | if (bestm2_frac) | |
7500 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
7501 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 7502 | |
de3a0fde VP |
7503 | /* Program digital lock detect threshold */ |
7504 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
7505 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
7506 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
7507 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
7508 | if (!bestm2_frac) | |
7509 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
7510 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
7511 | ||
9d556c99 | 7512 | /* Loop filter */ |
9cbe40c1 VP |
7513 | if (vco == 5400000) { |
7514 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7515 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
7516 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7517 | tribuf_calcntr = 0x9; | |
7518 | } else if (vco <= 6200000) { | |
7519 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7520 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
7521 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7522 | tribuf_calcntr = 0x9; | |
7523 | } else if (vco <= 6480000) { | |
7524 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7525 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7526 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7527 | tribuf_calcntr = 0x8; | |
7528 | } else { | |
7529 | /* Not supported. Apply the same limits as in the max case */ | |
7530 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7531 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7532 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7533 | tribuf_calcntr = 0; | |
7534 | } | |
9d556c99 CML |
7535 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
7536 | ||
968040b2 | 7537 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
7538 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
7539 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
7540 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
7541 | ||
9d556c99 CML |
7542 | /* AFC Recal */ |
7543 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
7544 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
7545 | DPIO_AFC_RECAL); | |
7546 | ||
a580516d | 7547 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
7548 | } |
7549 | ||
d288f65f VS |
7550 | /** |
7551 | * vlv_force_pll_on - forcibly enable just the PLL | |
7552 | * @dev_priv: i915 private structure | |
7553 | * @pipe: pipe PLL to enable | |
7554 | * @dpll: PLL configuration | |
7555 | * | |
7556 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
7557 | * in cases where we need the PLL enabled even when @pipe is not going to | |
7558 | * be enabled. | |
7559 | */ | |
7560 | void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, | |
7561 | const struct dpll *dpll) | |
7562 | { | |
7563 | struct intel_crtc *crtc = | |
7564 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
5cec258b | 7565 | struct intel_crtc_state pipe_config = { |
a93e255f | 7566 | .base.crtc = &crtc->base, |
d288f65f VS |
7567 | .pixel_multiplier = 1, |
7568 | .dpll = *dpll, | |
7569 | }; | |
7570 | ||
7571 | if (IS_CHERRYVIEW(dev)) { | |
251ac862 | 7572 | chv_compute_dpll(crtc, &pipe_config); |
d288f65f VS |
7573 | chv_prepare_pll(crtc, &pipe_config); |
7574 | chv_enable_pll(crtc, &pipe_config); | |
7575 | } else { | |
251ac862 | 7576 | vlv_compute_dpll(crtc, &pipe_config); |
d288f65f VS |
7577 | vlv_prepare_pll(crtc, &pipe_config); |
7578 | vlv_enable_pll(crtc, &pipe_config); | |
7579 | } | |
7580 | } | |
7581 | ||
7582 | /** | |
7583 | * vlv_force_pll_off - forcibly disable just the PLL | |
7584 | * @dev_priv: i915 private structure | |
7585 | * @pipe: pipe PLL to disable | |
7586 | * | |
7587 | * Disable the PLL for @pipe. To be used in cases where we need | |
7588 | * the PLL enabled even when @pipe is not going to be enabled. | |
7589 | */ | |
7590 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
7591 | { | |
7592 | if (IS_CHERRYVIEW(dev)) | |
7593 | chv_disable_pll(to_i915(dev), pipe); | |
7594 | else | |
7595 | vlv_disable_pll(to_i915(dev), pipe); | |
7596 | } | |
7597 | ||
251ac862 DV |
7598 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
7599 | struct intel_crtc_state *crtc_state, | |
7600 | intel_clock_t *reduced_clock, | |
7601 | int num_connectors) | |
eb1cbe48 | 7602 | { |
f47709a9 | 7603 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7604 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
7605 | u32 dpll; |
7606 | bool is_sdvo; | |
190f68c5 | 7607 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7608 | |
190f68c5 | 7609 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7610 | |
a93e255f ACO |
7611 | is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) || |
7612 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
7613 | |
7614 | dpll = DPLL_VGA_MODE_DIS; | |
7615 | ||
a93e255f | 7616 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
7617 | dpll |= DPLLB_MODE_LVDS; |
7618 | else | |
7619 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 7620 | |
ef1b460d | 7621 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 7622 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 7623 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 7624 | } |
198a037f DV |
7625 | |
7626 | if (is_sdvo) | |
4a33e48d | 7627 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 7628 | |
190f68c5 | 7629 | if (crtc_state->has_dp_encoder) |
4a33e48d | 7630 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
7631 | |
7632 | /* compute bitmask from p1 value */ | |
7633 | if (IS_PINEVIEW(dev)) | |
7634 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
7635 | else { | |
7636 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7637 | if (IS_G4X(dev) && reduced_clock) | |
7638 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
7639 | } | |
7640 | switch (clock->p2) { | |
7641 | case 5: | |
7642 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7643 | break; | |
7644 | case 7: | |
7645 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7646 | break; | |
7647 | case 10: | |
7648 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7649 | break; | |
7650 | case 14: | |
7651 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7652 | break; | |
7653 | } | |
7654 | if (INTEL_INFO(dev)->gen >= 4) | |
7655 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
7656 | ||
190f68c5 | 7657 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 7658 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
a93e255f | 7659 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7660 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7661 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7662 | else | |
7663 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7664 | ||
7665 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7666 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 7667 | |
eb1cbe48 | 7668 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 7669 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7670 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 7671 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
7672 | } |
7673 | } | |
7674 | ||
251ac862 DV |
7675 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
7676 | struct intel_crtc_state *crtc_state, | |
7677 | intel_clock_t *reduced_clock, | |
7678 | int num_connectors) | |
eb1cbe48 | 7679 | { |
f47709a9 | 7680 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7681 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 7682 | u32 dpll; |
190f68c5 | 7683 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7684 | |
190f68c5 | 7685 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7686 | |
eb1cbe48 DV |
7687 | dpll = DPLL_VGA_MODE_DIS; |
7688 | ||
a93e255f | 7689 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
7690 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
7691 | } else { | |
7692 | if (clock->p1 == 2) | |
7693 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
7694 | else | |
7695 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7696 | if (clock->p2 == 4) | |
7697 | dpll |= PLL_P2_DIVIDE_BY_4; | |
7698 | } | |
7699 | ||
a93e255f | 7700 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
7701 | dpll |= DPLL_DVO_2X_MODE; |
7702 | ||
a93e255f | 7703 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7704 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7705 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7706 | else | |
7707 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7708 | ||
7709 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7710 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
7711 | } |
7712 | ||
8a654f3b | 7713 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
7714 | { |
7715 | struct drm_device *dev = intel_crtc->base.dev; | |
7716 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7717 | enum pipe pipe = intel_crtc->pipe; | |
6e3c9717 | 7718 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
7c5f93b0 | 7719 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
7720 | uint32_t crtc_vtotal, crtc_vblank_end; |
7721 | int vsyncshift = 0; | |
4d8a62ea DV |
7722 | |
7723 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
7724 | * the hw state checker will get angry at the mismatch. */ | |
7725 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
7726 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 7727 | |
609aeaca | 7728 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 7729 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
7730 | crtc_vtotal -= 1; |
7731 | crtc_vblank_end -= 1; | |
609aeaca | 7732 | |
409ee761 | 7733 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
7734 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
7735 | else | |
7736 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
7737 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
7738 | if (vsyncshift < 0) |
7739 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
7740 | } |
7741 | ||
7742 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 7743 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 7744 | |
fe2b8f9d | 7745 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
7746 | (adjusted_mode->crtc_hdisplay - 1) | |
7747 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 7748 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
7749 | (adjusted_mode->crtc_hblank_start - 1) | |
7750 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 7751 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
7752 | (adjusted_mode->crtc_hsync_start - 1) | |
7753 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
7754 | ||
fe2b8f9d | 7755 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 7756 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 7757 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 7758 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 7759 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 7760 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 7761 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
7762 | (adjusted_mode->crtc_vsync_start - 1) | |
7763 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
7764 | ||
b5e508d4 PZ |
7765 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
7766 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
7767 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
7768 | * bits. */ | |
7769 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
7770 | (pipe == PIPE_B || pipe == PIPE_C)) | |
7771 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
7772 | ||
b0e77b9c PZ |
7773 | /* pipesrc controls the size that is scaled from, which should |
7774 | * always be the user's requested size. | |
7775 | */ | |
7776 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
7777 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
7778 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
7779 | } |
7780 | ||
1bd1bd80 | 7781 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 7782 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
7783 | { |
7784 | struct drm_device *dev = crtc->base.dev; | |
7785 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7786 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
7787 | uint32_t tmp; | |
7788 | ||
7789 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7790 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
7791 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7792 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
7793 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
7794 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7795 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
7796 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
7797 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7798 | |
7799 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7800 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
7801 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7802 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
7803 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
7804 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7805 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
7806 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
7807 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7808 | |
7809 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
7810 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
7811 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
7812 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 DV |
7813 | } |
7814 | ||
7815 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
7816 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
7817 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
7818 | ||
2d112de7 ACO |
7819 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
7820 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
7821 | } |
7822 | ||
f6a83288 | 7823 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 7824 | struct intel_crtc_state *pipe_config) |
babea61d | 7825 | { |
2d112de7 ACO |
7826 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
7827 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
7828 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
7829 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 7830 | |
2d112de7 ACO |
7831 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
7832 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
7833 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7834 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 7835 | |
2d112de7 | 7836 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 7837 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 7838 | |
2d112de7 ACO |
7839 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
7840 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
cd13f5ab ML |
7841 | |
7842 | mode->hsync = drm_mode_hsync(mode); | |
7843 | mode->vrefresh = drm_mode_vrefresh(mode); | |
7844 | drm_mode_set_name(mode); | |
babea61d JB |
7845 | } |
7846 | ||
84b046f3 DV |
7847 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7848 | { | |
7849 | struct drm_device *dev = intel_crtc->base.dev; | |
7850 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7851 | uint32_t pipeconf; | |
7852 | ||
9f11a9e4 | 7853 | pipeconf = 0; |
84b046f3 | 7854 | |
b6b5d049 VS |
7855 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
7856 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
7857 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 7858 | |
6e3c9717 | 7859 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7860 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7861 | |
ff9ce46e DV |
7862 | /* only g4x and later have fancy bpc/dither controls */ |
7863 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
ff9ce46e | 7864 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 7865 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 7866 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 7867 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 7868 | |
6e3c9717 | 7869 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
7870 | case 18: |
7871 | pipeconf |= PIPECONF_6BPC; | |
7872 | break; | |
7873 | case 24: | |
7874 | pipeconf |= PIPECONF_8BPC; | |
7875 | break; | |
7876 | case 30: | |
7877 | pipeconf |= PIPECONF_10BPC; | |
7878 | break; | |
7879 | default: | |
7880 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7881 | BUG(); | |
84b046f3 DV |
7882 | } |
7883 | } | |
7884 | ||
7885 | if (HAS_PIPE_CXSR(dev)) { | |
7886 | if (intel_crtc->lowfreq_avail) { | |
7887 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
7888 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
7889 | } else { | |
7890 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
7891 | } |
7892 | } | |
7893 | ||
6e3c9717 | 7894 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 7895 | if (INTEL_INFO(dev)->gen < 4 || |
409ee761 | 7896 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
7897 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
7898 | else | |
7899 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7900 | } else | |
84b046f3 DV |
7901 | pipeconf |= PIPECONF_PROGRESSIVE; |
7902 | ||
6e3c9717 | 7903 | if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range) |
9f11a9e4 | 7904 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 7905 | |
84b046f3 DV |
7906 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7907 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7908 | } | |
7909 | ||
190f68c5 ACO |
7910 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
7911 | struct intel_crtc_state *crtc_state) | |
79e53945 | 7912 | { |
c7653199 | 7913 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 7914 | struct drm_i915_private *dev_priv = dev->dev_private; |
c751ce4f | 7915 | int refclk, num_connectors = 0; |
c329a4ec DV |
7916 | intel_clock_t clock; |
7917 | bool ok; | |
d4906093 | 7918 | const intel_limit_t *limit; |
55bb9992 | 7919 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 7920 | struct drm_connector *connector; |
55bb9992 ACO |
7921 | struct drm_connector_state *connector_state; |
7922 | int i; | |
79e53945 | 7923 | |
dd3cd74a ACO |
7924 | memset(&crtc_state->dpll_hw_state, 0, |
7925 | sizeof(crtc_state->dpll_hw_state)); | |
7926 | ||
a65347ba JN |
7927 | if (crtc_state->has_dsi_encoder) |
7928 | return 0; | |
43565a06 | 7929 | |
a65347ba JN |
7930 | for_each_connector_in_state(state, connector, connector_state, i) { |
7931 | if (connector_state->crtc == &crtc->base) | |
7932 | num_connectors++; | |
79e53945 JB |
7933 | } |
7934 | ||
190f68c5 | 7935 | if (!crtc_state->clock_set) { |
a93e255f | 7936 | refclk = i9xx_get_refclk(crtc_state, num_connectors); |
79e53945 | 7937 | |
e9fd1c02 JN |
7938 | /* |
7939 | * Returns a set of divisors for the desired target clock with | |
7940 | * the given refclk, or FALSE. The returned values represent | |
7941 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
7942 | * 2) / p1 / p2. | |
7943 | */ | |
a93e255f ACO |
7944 | limit = intel_limit(crtc_state, refclk); |
7945 | ok = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 7946 | crtc_state->port_clock, |
e9fd1c02 | 7947 | refclk, NULL, &clock); |
f2335330 | 7948 | if (!ok) { |
e9fd1c02 JN |
7949 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
7950 | return -EINVAL; | |
7951 | } | |
79e53945 | 7952 | |
f2335330 | 7953 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
7954 | crtc_state->dpll.n = clock.n; |
7955 | crtc_state->dpll.m1 = clock.m1; | |
7956 | crtc_state->dpll.m2 = clock.m2; | |
7957 | crtc_state->dpll.p1 = clock.p1; | |
7958 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 7959 | } |
7026d4ac | 7960 | |
e9fd1c02 | 7961 | if (IS_GEN2(dev)) { |
c329a4ec | 7962 | i8xx_compute_dpll(crtc, crtc_state, NULL, |
251ac862 | 7963 | num_connectors); |
9d556c99 | 7964 | } else if (IS_CHERRYVIEW(dev)) { |
251ac862 | 7965 | chv_compute_dpll(crtc, crtc_state); |
e9fd1c02 | 7966 | } else if (IS_VALLEYVIEW(dev)) { |
251ac862 | 7967 | vlv_compute_dpll(crtc, crtc_state); |
e9fd1c02 | 7968 | } else { |
c329a4ec | 7969 | i9xx_compute_dpll(crtc, crtc_state, NULL, |
251ac862 | 7970 | num_connectors); |
e9fd1c02 | 7971 | } |
79e53945 | 7972 | |
c8f7a0db | 7973 | return 0; |
f564048e EA |
7974 | } |
7975 | ||
2fa2fe9a | 7976 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 7977 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
7978 | { |
7979 | struct drm_device *dev = crtc->base.dev; | |
7980 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7981 | uint32_t tmp; | |
7982 | ||
dc9e7dec VS |
7983 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
7984 | return; | |
7985 | ||
2fa2fe9a | 7986 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
7987 | if (!(tmp & PFIT_ENABLE)) |
7988 | return; | |
2fa2fe9a | 7989 | |
06922821 | 7990 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
7991 | if (INTEL_INFO(dev)->gen < 4) { |
7992 | if (crtc->pipe != PIPE_B) | |
7993 | return; | |
2fa2fe9a DV |
7994 | } else { |
7995 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
7996 | return; | |
7997 | } | |
7998 | ||
06922821 | 7999 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
8000 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
8001 | if (INTEL_INFO(dev)->gen < 5) | |
8002 | pipe_config->gmch_pfit.lvds_border_bits = | |
8003 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
8004 | } | |
8005 | ||
acbec814 | 8006 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8007 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
8008 | { |
8009 | struct drm_device *dev = crtc->base.dev; | |
8010 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8011 | int pipe = pipe_config->cpu_transcoder; | |
8012 | intel_clock_t clock; | |
8013 | u32 mdiv; | |
662c6ecb | 8014 | int refclk = 100000; |
acbec814 | 8015 | |
f573de5a SK |
8016 | /* In case of MIPI DPLL will not even be used */ |
8017 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) | |
8018 | return; | |
8019 | ||
a580516d | 8020 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 8021 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 8022 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
8023 | |
8024 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
8025 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
8026 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
8027 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
8028 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
8029 | ||
dccbea3b | 8030 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
8031 | } |
8032 | ||
5724dbd1 DL |
8033 | static void |
8034 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
8035 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
8036 | { |
8037 | struct drm_device *dev = crtc->base.dev; | |
8038 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8039 | u32 val, base, offset; | |
8040 | int pipe = crtc->pipe, plane = crtc->plane; | |
8041 | int fourcc, pixel_format; | |
6761dd31 | 8042 | unsigned int aligned_height; |
b113d5ee | 8043 | struct drm_framebuffer *fb; |
1b842c89 | 8044 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 8045 | |
42a7b088 DL |
8046 | val = I915_READ(DSPCNTR(plane)); |
8047 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8048 | return; | |
8049 | ||
d9806c9f | 8050 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8051 | if (!intel_fb) { |
1ad292b5 JB |
8052 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8053 | return; | |
8054 | } | |
8055 | ||
1b842c89 DL |
8056 | fb = &intel_fb->base; |
8057 | ||
18c5247e DV |
8058 | if (INTEL_INFO(dev)->gen >= 4) { |
8059 | if (val & DISPPLANE_TILED) { | |
49af449b | 8060 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
8061 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
8062 | } | |
8063 | } | |
1ad292b5 JB |
8064 | |
8065 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8066 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
8067 | fb->pixel_format = fourcc; |
8068 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
8069 | |
8070 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 8071 | if (plane_config->tiling) |
1ad292b5 JB |
8072 | offset = I915_READ(DSPTILEOFF(plane)); |
8073 | else | |
8074 | offset = I915_READ(DSPLINOFF(plane)); | |
8075 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
8076 | } else { | |
8077 | base = I915_READ(DSPADDR(plane)); | |
8078 | } | |
8079 | plane_config->base = base; | |
8080 | ||
8081 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8082 | fb->width = ((val >> 16) & 0xfff) + 1; |
8083 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
8084 | |
8085 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8086 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 8087 | |
b113d5ee | 8088 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
8089 | fb->pixel_format, |
8090 | fb->modifier[0]); | |
1ad292b5 | 8091 | |
f37b5c2b | 8092 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 8093 | |
2844a921 DL |
8094 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8095 | pipe_name(pipe), plane, fb->width, fb->height, | |
8096 | fb->bits_per_pixel, base, fb->pitches[0], | |
8097 | plane_config->size); | |
1ad292b5 | 8098 | |
2d14030b | 8099 | plane_config->fb = intel_fb; |
1ad292b5 JB |
8100 | } |
8101 | ||
70b23a98 | 8102 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8103 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
8104 | { |
8105 | struct drm_device *dev = crtc->base.dev; | |
8106 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8107 | int pipe = pipe_config->cpu_transcoder; | |
8108 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
8109 | intel_clock_t clock; | |
0d7b6b11 | 8110 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
8111 | int refclk = 100000; |
8112 | ||
a580516d | 8113 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
8114 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
8115 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
8116 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
8117 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 8118 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 8119 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
8120 | |
8121 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
8122 | clock.m2 = (pll_dw0 & 0xff) << 22; |
8123 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
8124 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
8125 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
8126 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
8127 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
8128 | ||
dccbea3b | 8129 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
8130 | } |
8131 | ||
0e8ffe1b | 8132 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8133 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8134 | { |
8135 | struct drm_device *dev = crtc->base.dev; | |
8136 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8137 | uint32_t tmp; | |
8138 | ||
f458ebbc DV |
8139 | if (!intel_display_power_is_enabled(dev_priv, |
8140 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
b5482bd0 ID |
8141 | return false; |
8142 | ||
e143a21c | 8143 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 8144 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 8145 | |
0e8ffe1b DV |
8146 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8147 | if (!(tmp & PIPECONF_ENABLE)) | |
8148 | return false; | |
8149 | ||
42571aef VS |
8150 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
8151 | switch (tmp & PIPECONF_BPC_MASK) { | |
8152 | case PIPECONF_6BPC: | |
8153 | pipe_config->pipe_bpp = 18; | |
8154 | break; | |
8155 | case PIPECONF_8BPC: | |
8156 | pipe_config->pipe_bpp = 24; | |
8157 | break; | |
8158 | case PIPECONF_10BPC: | |
8159 | pipe_config->pipe_bpp = 30; | |
8160 | break; | |
8161 | default: | |
8162 | break; | |
8163 | } | |
8164 | } | |
8165 | ||
b5a9fa09 DV |
8166 | if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
8167 | pipe_config->limited_color_range = true; | |
8168 | ||
282740f7 VS |
8169 | if (INTEL_INFO(dev)->gen < 4) |
8170 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
8171 | ||
1bd1bd80 DV |
8172 | intel_get_pipe_timings(crtc, pipe_config); |
8173 | ||
2fa2fe9a DV |
8174 | i9xx_get_pfit_config(crtc, pipe_config); |
8175 | ||
6c49f241 DV |
8176 | if (INTEL_INFO(dev)->gen >= 4) { |
8177 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
8178 | pipe_config->pixel_multiplier = | |
8179 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
8180 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 8181 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
8182 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
8183 | tmp = I915_READ(DPLL(crtc->pipe)); | |
8184 | pipe_config->pixel_multiplier = | |
8185 | ((tmp & SDVO_MULTIPLIER_MASK) | |
8186 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
8187 | } else { | |
8188 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
8189 | * port and will be fixed up in the encoder->get_config | |
8190 | * function. */ | |
8191 | pipe_config->pixel_multiplier = 1; | |
8192 | } | |
8bcc2795 DV |
8193 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
8194 | if (!IS_VALLEYVIEW(dev)) { | |
1c4e0274 VS |
8195 | /* |
8196 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
8197 | * on 830. Filter it out here so that we don't | |
8198 | * report errors due to that. | |
8199 | */ | |
8200 | if (IS_I830(dev)) | |
8201 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
8202 | ||
8bcc2795 DV |
8203 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
8204 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
8205 | } else { |
8206 | /* Mask out read-only status bits. */ | |
8207 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
8208 | DPLL_PORTC_READY_MASK | | |
8209 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 8210 | } |
6c49f241 | 8211 | |
70b23a98 VS |
8212 | if (IS_CHERRYVIEW(dev)) |
8213 | chv_crtc_clock_get(crtc, pipe_config); | |
8214 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
8215 | vlv_crtc_clock_get(crtc, pipe_config); |
8216 | else | |
8217 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 8218 | |
0f64614d VS |
8219 | /* |
8220 | * Normally the dotclock is filled in by the encoder .get_config() | |
8221 | * but in case the pipe is enabled w/o any ports we need a sane | |
8222 | * default. | |
8223 | */ | |
8224 | pipe_config->base.adjusted_mode.crtc_clock = | |
8225 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
8226 | ||
0e8ffe1b DV |
8227 | return true; |
8228 | } | |
8229 | ||
dde86e2d | 8230 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
8231 | { |
8232 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 8233 | struct intel_encoder *encoder; |
74cfd7ac | 8234 | u32 val, final; |
13d83a67 | 8235 | bool has_lvds = false; |
199e5d79 | 8236 | bool has_cpu_edp = false; |
199e5d79 | 8237 | bool has_panel = false; |
99eb6a01 KP |
8238 | bool has_ck505 = false; |
8239 | bool can_ssc = false; | |
13d83a67 JB |
8240 | |
8241 | /* We need to take the global config into account */ | |
b2784e15 | 8242 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
8243 | switch (encoder->type) { |
8244 | case INTEL_OUTPUT_LVDS: | |
8245 | has_panel = true; | |
8246 | has_lvds = true; | |
8247 | break; | |
8248 | case INTEL_OUTPUT_EDP: | |
8249 | has_panel = true; | |
2de6905f | 8250 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
8251 | has_cpu_edp = true; |
8252 | break; | |
6847d71b PZ |
8253 | default: |
8254 | break; | |
13d83a67 JB |
8255 | } |
8256 | } | |
8257 | ||
99eb6a01 | 8258 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 8259 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
8260 | can_ssc = has_ck505; |
8261 | } else { | |
8262 | has_ck505 = false; | |
8263 | can_ssc = true; | |
8264 | } | |
8265 | ||
2de6905f ID |
8266 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
8267 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
8268 | |
8269 | /* Ironlake: try to setup display ref clock before DPLL | |
8270 | * enabling. This is only under driver's control after | |
8271 | * PCH B stepping, previous chipset stepping should be | |
8272 | * ignoring this setting. | |
8273 | */ | |
74cfd7ac CW |
8274 | val = I915_READ(PCH_DREF_CONTROL); |
8275 | ||
8276 | /* As we must carefully and slowly disable/enable each source in turn, | |
8277 | * compute the final state we want first and check if we need to | |
8278 | * make any changes at all. | |
8279 | */ | |
8280 | final = val; | |
8281 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
8282 | if (has_ck505) | |
8283 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
8284 | else | |
8285 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
8286 | ||
8287 | final &= ~DREF_SSC_SOURCE_MASK; | |
8288 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
8289 | final &= ~DREF_SSC1_ENABLE; | |
8290 | ||
8291 | if (has_panel) { | |
8292 | final |= DREF_SSC_SOURCE_ENABLE; | |
8293 | ||
8294 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8295 | final |= DREF_SSC1_ENABLE; | |
8296 | ||
8297 | if (has_cpu_edp) { | |
8298 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8299 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
8300 | else | |
8301 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
8302 | } else | |
8303 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8304 | } else { | |
8305 | final |= DREF_SSC_SOURCE_DISABLE; | |
8306 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8307 | } | |
8308 | ||
8309 | if (final == val) | |
8310 | return; | |
8311 | ||
13d83a67 | 8312 | /* Always enable nonspread source */ |
74cfd7ac | 8313 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 8314 | |
99eb6a01 | 8315 | if (has_ck505) |
74cfd7ac | 8316 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 8317 | else |
74cfd7ac | 8318 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 8319 | |
199e5d79 | 8320 | if (has_panel) { |
74cfd7ac CW |
8321 | val &= ~DREF_SSC_SOURCE_MASK; |
8322 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 8323 | |
199e5d79 | 8324 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 8325 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8326 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 8327 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 8328 | } else |
74cfd7ac | 8329 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
8330 | |
8331 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 8332 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8333 | POSTING_READ(PCH_DREF_CONTROL); |
8334 | udelay(200); | |
8335 | ||
74cfd7ac | 8336 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
8337 | |
8338 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 8339 | if (has_cpu_edp) { |
99eb6a01 | 8340 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8341 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 8342 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 8343 | } else |
74cfd7ac | 8344 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 8345 | } else |
74cfd7ac | 8346 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8347 | |
74cfd7ac | 8348 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8349 | POSTING_READ(PCH_DREF_CONTROL); |
8350 | udelay(200); | |
8351 | } else { | |
8352 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
8353 | ||
74cfd7ac | 8354 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
8355 | |
8356 | /* Turn off CPU output */ | |
74cfd7ac | 8357 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8358 | |
74cfd7ac | 8359 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8360 | POSTING_READ(PCH_DREF_CONTROL); |
8361 | udelay(200); | |
8362 | ||
8363 | /* Turn off the SSC source */ | |
74cfd7ac CW |
8364 | val &= ~DREF_SSC_SOURCE_MASK; |
8365 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
8366 | |
8367 | /* Turn off SSC1 */ | |
74cfd7ac | 8368 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 8369 | |
74cfd7ac | 8370 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
8371 | POSTING_READ(PCH_DREF_CONTROL); |
8372 | udelay(200); | |
8373 | } | |
74cfd7ac CW |
8374 | |
8375 | BUG_ON(val != final); | |
13d83a67 JB |
8376 | } |
8377 | ||
f31f2d55 | 8378 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 8379 | { |
f31f2d55 | 8380 | uint32_t tmp; |
dde86e2d | 8381 | |
0ff066a9 PZ |
8382 | tmp = I915_READ(SOUTH_CHICKEN2); |
8383 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
8384 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8385 | |
0ff066a9 PZ |
8386 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
8387 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
8388 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 8389 | |
0ff066a9 PZ |
8390 | tmp = I915_READ(SOUTH_CHICKEN2); |
8391 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
8392 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8393 | |
0ff066a9 PZ |
8394 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
8395 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
8396 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
8397 | } |
8398 | ||
8399 | /* WaMPhyProgramming:hsw */ | |
8400 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
8401 | { | |
8402 | uint32_t tmp; | |
dde86e2d PZ |
8403 | |
8404 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
8405 | tmp &= ~(0xFF << 24); | |
8406 | tmp |= (0x12 << 24); | |
8407 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
8408 | ||
dde86e2d PZ |
8409 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
8410 | tmp |= (1 << 11); | |
8411 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
8412 | ||
8413 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
8414 | tmp |= (1 << 11); | |
8415 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
8416 | ||
dde86e2d PZ |
8417 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
8418 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8419 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
8420 | ||
8421 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
8422 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8423 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
8424 | ||
0ff066a9 PZ |
8425 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
8426 | tmp &= ~(7 << 13); | |
8427 | tmp |= (5 << 13); | |
8428 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 8429 | |
0ff066a9 PZ |
8430 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
8431 | tmp &= ~(7 << 13); | |
8432 | tmp |= (5 << 13); | |
8433 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
8434 | |
8435 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
8436 | tmp &= ~0xFF; | |
8437 | tmp |= 0x1C; | |
8438 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
8439 | ||
8440 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
8441 | tmp &= ~0xFF; | |
8442 | tmp |= 0x1C; | |
8443 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
8444 | ||
8445 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
8446 | tmp &= ~(0xFF << 16); | |
8447 | tmp |= (0x1C << 16); | |
8448 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
8449 | ||
8450 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
8451 | tmp &= ~(0xFF << 16); | |
8452 | tmp |= (0x1C << 16); | |
8453 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
8454 | ||
0ff066a9 PZ |
8455 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
8456 | tmp |= (1 << 27); | |
8457 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 8458 | |
0ff066a9 PZ |
8459 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
8460 | tmp |= (1 << 27); | |
8461 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 8462 | |
0ff066a9 PZ |
8463 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
8464 | tmp &= ~(0xF << 28); | |
8465 | tmp |= (4 << 28); | |
8466 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 8467 | |
0ff066a9 PZ |
8468 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
8469 | tmp &= ~(0xF << 28); | |
8470 | tmp |= (4 << 28); | |
8471 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
8472 | } |
8473 | ||
2fa86a1f PZ |
8474 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
8475 | * Programming" based on the parameters passed: | |
8476 | * - Sequence to enable CLKOUT_DP | |
8477 | * - Sequence to enable CLKOUT_DP without spread | |
8478 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
8479 | */ | |
8480 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
8481 | bool with_fdi) | |
f31f2d55 PZ |
8482 | { |
8483 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
8484 | uint32_t reg, tmp; |
8485 | ||
8486 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
8487 | with_spread = true; | |
c2699524 | 8488 | if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n")) |
2fa86a1f | 8489 | with_fdi = false; |
f31f2d55 | 8490 | |
a580516d | 8491 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
8492 | |
8493 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8494 | tmp &= ~SBI_SSCCTL_DISABLE; | |
8495 | tmp |= SBI_SSCCTL_PATHALT; | |
8496 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8497 | ||
8498 | udelay(24); | |
8499 | ||
2fa86a1f PZ |
8500 | if (with_spread) { |
8501 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8502 | tmp &= ~SBI_SSCCTL_PATHALT; | |
8503 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 8504 | |
2fa86a1f PZ |
8505 | if (with_fdi) { |
8506 | lpt_reset_fdi_mphy(dev_priv); | |
8507 | lpt_program_fdi_mphy(dev_priv); | |
8508 | } | |
8509 | } | |
dde86e2d | 8510 | |
c2699524 | 8511 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
8512 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8513 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8514 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 8515 | |
a580516d | 8516 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
8517 | } |
8518 | ||
47701c3b PZ |
8519 | /* Sequence to disable CLKOUT_DP */ |
8520 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
8521 | { | |
8522 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8523 | uint32_t reg, tmp; | |
8524 | ||
a580516d | 8525 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 8526 | |
c2699524 | 8527 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
8528 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8529 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8530 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
8531 | ||
8532 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8533 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
8534 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
8535 | tmp |= SBI_SSCCTL_PATHALT; | |
8536 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8537 | udelay(32); | |
8538 | } | |
8539 | tmp |= SBI_SSCCTL_DISABLE; | |
8540 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8541 | } | |
8542 | ||
a580516d | 8543 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
8544 | } |
8545 | ||
bf8fa3d3 PZ |
8546 | static void lpt_init_pch_refclk(struct drm_device *dev) |
8547 | { | |
bf8fa3d3 PZ |
8548 | struct intel_encoder *encoder; |
8549 | bool has_vga = false; | |
8550 | ||
b2784e15 | 8551 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
8552 | switch (encoder->type) { |
8553 | case INTEL_OUTPUT_ANALOG: | |
8554 | has_vga = true; | |
8555 | break; | |
6847d71b PZ |
8556 | default: |
8557 | break; | |
bf8fa3d3 PZ |
8558 | } |
8559 | } | |
8560 | ||
47701c3b PZ |
8561 | if (has_vga) |
8562 | lpt_enable_clkout_dp(dev, true, true); | |
8563 | else | |
8564 | lpt_disable_clkout_dp(dev); | |
bf8fa3d3 PZ |
8565 | } |
8566 | ||
dde86e2d PZ |
8567 | /* |
8568 | * Initialize reference clocks when the driver loads | |
8569 | */ | |
8570 | void intel_init_pch_refclk(struct drm_device *dev) | |
8571 | { | |
8572 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
8573 | ironlake_init_pch_refclk(dev); | |
8574 | else if (HAS_PCH_LPT(dev)) | |
8575 | lpt_init_pch_refclk(dev); | |
8576 | } | |
8577 | ||
55bb9992 | 8578 | static int ironlake_get_refclk(struct intel_crtc_state *crtc_state) |
d9d444cb | 8579 | { |
55bb9992 | 8580 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d9d444cb | 8581 | struct drm_i915_private *dev_priv = dev->dev_private; |
55bb9992 | 8582 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8583 | struct drm_connector *connector; |
55bb9992 | 8584 | struct drm_connector_state *connector_state; |
d9d444cb | 8585 | struct intel_encoder *encoder; |
55bb9992 | 8586 | int num_connectors = 0, i; |
d9d444cb JB |
8587 | bool is_lvds = false; |
8588 | ||
da3ced29 | 8589 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8590 | if (connector_state->crtc != crtc_state->base.crtc) |
8591 | continue; | |
8592 | ||
8593 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8594 | ||
d9d444cb JB |
8595 | switch (encoder->type) { |
8596 | case INTEL_OUTPUT_LVDS: | |
8597 | is_lvds = true; | |
8598 | break; | |
6847d71b PZ |
8599 | default: |
8600 | break; | |
d9d444cb JB |
8601 | } |
8602 | num_connectors++; | |
8603 | } | |
8604 | ||
8605 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 8606 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 8607 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 8608 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
8609 | } |
8610 | ||
8611 | return 120000; | |
8612 | } | |
8613 | ||
6ff93609 | 8614 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 8615 | { |
c8203565 | 8616 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
8617 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8618 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
8619 | uint32_t val; |
8620 | ||
78114071 | 8621 | val = 0; |
c8203565 | 8622 | |
6e3c9717 | 8623 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 8624 | case 18: |
dfd07d72 | 8625 | val |= PIPECONF_6BPC; |
c8203565 PZ |
8626 | break; |
8627 | case 24: | |
dfd07d72 | 8628 | val |= PIPECONF_8BPC; |
c8203565 PZ |
8629 | break; |
8630 | case 30: | |
dfd07d72 | 8631 | val |= PIPECONF_10BPC; |
c8203565 PZ |
8632 | break; |
8633 | case 36: | |
dfd07d72 | 8634 | val |= PIPECONF_12BPC; |
c8203565 PZ |
8635 | break; |
8636 | default: | |
cc769b62 PZ |
8637 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
8638 | BUG(); | |
c8203565 PZ |
8639 | } |
8640 | ||
6e3c9717 | 8641 | if (intel_crtc->config->dither) |
c8203565 PZ |
8642 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8643 | ||
6e3c9717 | 8644 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
8645 | val |= PIPECONF_INTERLACED_ILK; |
8646 | else | |
8647 | val |= PIPECONF_PROGRESSIVE; | |
8648 | ||
6e3c9717 | 8649 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 8650 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 8651 | |
c8203565 PZ |
8652 | I915_WRITE(PIPECONF(pipe), val); |
8653 | POSTING_READ(PIPECONF(pipe)); | |
8654 | } | |
8655 | ||
86d3efce VS |
8656 | /* |
8657 | * Set up the pipe CSC unit. | |
8658 | * | |
8659 | * Currently only full range RGB to limited range RGB conversion | |
8660 | * is supported, but eventually this should handle various | |
8661 | * RGB<->YCbCr scenarios as well. | |
8662 | */ | |
50f3b016 | 8663 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
8664 | { |
8665 | struct drm_device *dev = crtc->dev; | |
8666 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8667 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8668 | int pipe = intel_crtc->pipe; | |
8669 | uint16_t coeff = 0x7800; /* 1.0 */ | |
8670 | ||
8671 | /* | |
8672 | * TODO: Check what kind of values actually come out of the pipe | |
8673 | * with these coeff/postoff values and adjust to get the best | |
8674 | * accuracy. Perhaps we even need to take the bpc value into | |
8675 | * consideration. | |
8676 | */ | |
8677 | ||
6e3c9717 | 8678 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8679 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
8680 | ||
8681 | /* | |
8682 | * GY/GU and RY/RU should be the other way around according | |
8683 | * to BSpec, but reality doesn't agree. Just set them up in | |
8684 | * a way that results in the correct picture. | |
8685 | */ | |
8686 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
8687 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
8688 | ||
8689 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
8690 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
8691 | ||
8692 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
8693 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
8694 | ||
8695 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
8696 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
8697 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
8698 | ||
8699 | if (INTEL_INFO(dev)->gen > 6) { | |
8700 | uint16_t postoff = 0; | |
8701 | ||
6e3c9717 | 8702 | if (intel_crtc->config->limited_color_range) |
32cf0cb0 | 8703 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
8704 | |
8705 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
8706 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
8707 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
8708 | ||
8709 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
8710 | } else { | |
8711 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
8712 | ||
6e3c9717 | 8713 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8714 | mode |= CSC_BLACK_SCREEN_OFFSET; |
8715 | ||
8716 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
8717 | } | |
8718 | } | |
8719 | ||
6ff93609 | 8720 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8721 | { |
756f85cf PZ |
8722 | struct drm_device *dev = crtc->dev; |
8723 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 8724 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 8725 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 8726 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee2b0b38 PZ |
8727 | uint32_t val; |
8728 | ||
3eff4faa | 8729 | val = 0; |
ee2b0b38 | 8730 | |
6e3c9717 | 8731 | if (IS_HASWELL(dev) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8732 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8733 | ||
6e3c9717 | 8734 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8735 | val |= PIPECONF_INTERLACED_ILK; |
8736 | else | |
8737 | val |= PIPECONF_PROGRESSIVE; | |
8738 | ||
702e7a56 PZ |
8739 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8740 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
8741 | |
8742 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
8743 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf | 8744 | |
3cdf122c | 8745 | if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { |
756f85cf PZ |
8746 | val = 0; |
8747 | ||
6e3c9717 | 8748 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8749 | case 18: |
8750 | val |= PIPEMISC_DITHER_6_BPC; | |
8751 | break; | |
8752 | case 24: | |
8753 | val |= PIPEMISC_DITHER_8_BPC; | |
8754 | break; | |
8755 | case 30: | |
8756 | val |= PIPEMISC_DITHER_10_BPC; | |
8757 | break; | |
8758 | case 36: | |
8759 | val |= PIPEMISC_DITHER_12_BPC; | |
8760 | break; | |
8761 | default: | |
8762 | /* Case prevented by pipe_config_set_bpp. */ | |
8763 | BUG(); | |
8764 | } | |
8765 | ||
6e3c9717 | 8766 | if (intel_crtc->config->dither) |
756f85cf PZ |
8767 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8768 | ||
8769 | I915_WRITE(PIPEMISC(pipe), val); | |
8770 | } | |
ee2b0b38 PZ |
8771 | } |
8772 | ||
6591c6e4 | 8773 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
190f68c5 | 8774 | struct intel_crtc_state *crtc_state, |
6591c6e4 PZ |
8775 | intel_clock_t *clock, |
8776 | bool *has_reduced_clock, | |
8777 | intel_clock_t *reduced_clock) | |
8778 | { | |
8779 | struct drm_device *dev = crtc->dev; | |
8780 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6591c6e4 | 8781 | int refclk; |
d4906093 | 8782 | const intel_limit_t *limit; |
c329a4ec | 8783 | bool ret; |
79e53945 | 8784 | |
55bb9992 | 8785 | refclk = ironlake_get_refclk(crtc_state); |
79e53945 | 8786 | |
d4906093 ML |
8787 | /* |
8788 | * Returns a set of divisors for the desired target clock with the given | |
8789 | * refclk, or FALSE. The returned values represent the clock equation: | |
8790 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
8791 | */ | |
a93e255f ACO |
8792 | limit = intel_limit(crtc_state, refclk); |
8793 | ret = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 8794 | crtc_state->port_clock, |
ee9300bb | 8795 | refclk, NULL, clock); |
6591c6e4 PZ |
8796 | if (!ret) |
8797 | return false; | |
cda4b7d3 | 8798 | |
6591c6e4 PZ |
8799 | return true; |
8800 | } | |
8801 | ||
d4b1931c PZ |
8802 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
8803 | { | |
8804 | /* | |
8805 | * Account for spread spectrum to avoid | |
8806 | * oversubscribing the link. Max center spread | |
8807 | * is 2.5%; use 5% for safety's sake. | |
8808 | */ | |
8809 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 8810 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
8811 | } |
8812 | ||
7429e9d4 | 8813 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 8814 | { |
7429e9d4 | 8815 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
8816 | } |
8817 | ||
de13a2e3 | 8818 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
190f68c5 | 8819 | struct intel_crtc_state *crtc_state, |
7429e9d4 | 8820 | u32 *fp, |
9a7c7890 | 8821 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 8822 | { |
de13a2e3 | 8823 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
8824 | struct drm_device *dev = crtc->dev; |
8825 | struct drm_i915_private *dev_priv = dev->dev_private; | |
55bb9992 | 8826 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8827 | struct drm_connector *connector; |
55bb9992 ACO |
8828 | struct drm_connector_state *connector_state; |
8829 | struct intel_encoder *encoder; | |
de13a2e3 | 8830 | uint32_t dpll; |
55bb9992 | 8831 | int factor, num_connectors = 0, i; |
09ede541 | 8832 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 8833 | |
da3ced29 | 8834 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8835 | if (connector_state->crtc != crtc_state->base.crtc) |
8836 | continue; | |
8837 | ||
8838 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8839 | ||
8840 | switch (encoder->type) { | |
79e53945 JB |
8841 | case INTEL_OUTPUT_LVDS: |
8842 | is_lvds = true; | |
8843 | break; | |
8844 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 8845 | case INTEL_OUTPUT_HDMI: |
79e53945 | 8846 | is_sdvo = true; |
79e53945 | 8847 | break; |
6847d71b PZ |
8848 | default: |
8849 | break; | |
79e53945 | 8850 | } |
43565a06 | 8851 | |
c751ce4f | 8852 | num_connectors++; |
79e53945 | 8853 | } |
79e53945 | 8854 | |
c1858123 | 8855 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
8856 | factor = 21; |
8857 | if (is_lvds) { | |
8858 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 8859 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 8860 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 8861 | factor = 25; |
190f68c5 | 8862 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 8863 | factor = 20; |
c1858123 | 8864 | |
190f68c5 | 8865 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
7d0ac5b7 | 8866 | *fp |= FP_CB_TUNE; |
2c07245f | 8867 | |
9a7c7890 DV |
8868 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
8869 | *fp2 |= FP_CB_TUNE; | |
8870 | ||
5eddb70b | 8871 | dpll = 0; |
2c07245f | 8872 | |
a07d6787 EA |
8873 | if (is_lvds) |
8874 | dpll |= DPLLB_MODE_LVDS; | |
8875 | else | |
8876 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 8877 | |
190f68c5 | 8878 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8879 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f DV |
8880 | |
8881 | if (is_sdvo) | |
4a33e48d | 8882 | dpll |= DPLL_SDVO_HIGH_SPEED; |
190f68c5 | 8883 | if (crtc_state->has_dp_encoder) |
4a33e48d | 8884 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 8885 | |
a07d6787 | 8886 | /* compute bitmask from p1 value */ |
190f68c5 | 8887 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 8888 | /* also FPA1 */ |
190f68c5 | 8889 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 8890 | |
190f68c5 | 8891 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
8892 | case 5: |
8893 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8894 | break; | |
8895 | case 7: | |
8896 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8897 | break; | |
8898 | case 10: | |
8899 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8900 | break; | |
8901 | case 14: | |
8902 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8903 | break; | |
79e53945 JB |
8904 | } |
8905 | ||
b4c09f3b | 8906 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 8907 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
8908 | else |
8909 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8910 | ||
959e16d6 | 8911 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
8912 | } |
8913 | ||
190f68c5 ACO |
8914 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
8915 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 8916 | { |
c7653199 | 8917 | struct drm_device *dev = crtc->base.dev; |
de13a2e3 | 8918 | intel_clock_t clock, reduced_clock; |
cbbab5bd | 8919 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 8920 | bool ok, has_reduced_clock = false; |
8b47047b | 8921 | bool is_lvds = false; |
e2b78267 | 8922 | struct intel_shared_dpll *pll; |
de13a2e3 | 8923 | |
dd3cd74a ACO |
8924 | memset(&crtc_state->dpll_hw_state, 0, |
8925 | sizeof(crtc_state->dpll_hw_state)); | |
8926 | ||
409ee761 | 8927 | is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS); |
79e53945 | 8928 | |
5dc5298b PZ |
8929 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
8930 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 8931 | |
190f68c5 | 8932 | ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock, |
de13a2e3 | 8933 | &has_reduced_clock, &reduced_clock); |
190f68c5 | 8934 | if (!ok && !crtc_state->clock_set) { |
de13a2e3 PZ |
8935 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
8936 | return -EINVAL; | |
79e53945 | 8937 | } |
f47709a9 | 8938 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
8939 | if (!crtc_state->clock_set) { |
8940 | crtc_state->dpll.n = clock.n; | |
8941 | crtc_state->dpll.m1 = clock.m1; | |
8942 | crtc_state->dpll.m2 = clock.m2; | |
8943 | crtc_state->dpll.p1 = clock.p1; | |
8944 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 8945 | } |
79e53945 | 8946 | |
5dc5298b | 8947 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
190f68c5 ACO |
8948 | if (crtc_state->has_pch_encoder) { |
8949 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); | |
cbbab5bd | 8950 | if (has_reduced_clock) |
7429e9d4 | 8951 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 8952 | |
190f68c5 | 8953 | dpll = ironlake_compute_dpll(crtc, crtc_state, |
cbbab5bd DV |
8954 | &fp, &reduced_clock, |
8955 | has_reduced_clock ? &fp2 : NULL); | |
8956 | ||
190f68c5 ACO |
8957 | crtc_state->dpll_hw_state.dpll = dpll; |
8958 | crtc_state->dpll_hw_state.fp0 = fp; | |
66e985c0 | 8959 | if (has_reduced_clock) |
190f68c5 | 8960 | crtc_state->dpll_hw_state.fp1 = fp2; |
66e985c0 | 8961 | else |
190f68c5 | 8962 | crtc_state->dpll_hw_state.fp1 = fp; |
66e985c0 | 8963 | |
190f68c5 | 8964 | pll = intel_get_shared_dpll(crtc, crtc_state); |
ee7b9f93 | 8965 | if (pll == NULL) { |
84f44ce7 | 8966 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
c7653199 | 8967 | pipe_name(crtc->pipe)); |
4b645f14 JB |
8968 | return -EINVAL; |
8969 | } | |
3fb37703 | 8970 | } |
79e53945 | 8971 | |
ab585dea | 8972 | if (is_lvds && has_reduced_clock) |
c7653199 | 8973 | crtc->lowfreq_avail = true; |
bcd644e0 | 8974 | else |
c7653199 | 8975 | crtc->lowfreq_avail = false; |
e2b78267 | 8976 | |
c8f7a0db | 8977 | return 0; |
79e53945 JB |
8978 | } |
8979 | ||
eb14cb74 VS |
8980 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
8981 | struct intel_link_m_n *m_n) | |
8982 | { | |
8983 | struct drm_device *dev = crtc->base.dev; | |
8984 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8985 | enum pipe pipe = crtc->pipe; | |
8986 | ||
8987 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
8988 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
8989 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8990 | & ~TU_SIZE_MASK; | |
8991 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
8992 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8993 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8994 | } | |
8995 | ||
8996 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
8997 | enum transcoder transcoder, | |
b95af8be VK |
8998 | struct intel_link_m_n *m_n, |
8999 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
9000 | { |
9001 | struct drm_device *dev = crtc->base.dev; | |
9002 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 9003 | enum pipe pipe = crtc->pipe; |
72419203 | 9004 | |
eb14cb74 VS |
9005 | if (INTEL_INFO(dev)->gen >= 5) { |
9006 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
9007 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
9008 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
9009 | & ~TU_SIZE_MASK; | |
9010 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
9011 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
9012 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
9013 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
9014 | * gen < 8) and if DRRS is supported (to make sure the | |
9015 | * registers are not unnecessarily read). | |
9016 | */ | |
9017 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 9018 | crtc->config->has_drrs) { |
b95af8be VK |
9019 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
9020 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
9021 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
9022 | & ~TU_SIZE_MASK; | |
9023 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
9024 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
9025 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9026 | } | |
eb14cb74 VS |
9027 | } else { |
9028 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
9029 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
9030 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9031 | & ~TU_SIZE_MASK; | |
9032 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
9033 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9034 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9035 | } | |
9036 | } | |
9037 | ||
9038 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 9039 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 9040 | { |
681a8504 | 9041 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
9042 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
9043 | else | |
9044 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
9045 | &pipe_config->dp_m_n, |
9046 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 9047 | } |
72419203 | 9048 | |
eb14cb74 | 9049 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 9050 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
9051 | { |
9052 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 9053 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
9054 | } |
9055 | ||
bd2e244f | 9056 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9057 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
9058 | { |
9059 | struct drm_device *dev = crtc->base.dev; | |
9060 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a1b2278e CK |
9061 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
9062 | uint32_t ps_ctrl = 0; | |
9063 | int id = -1; | |
9064 | int i; | |
bd2e244f | 9065 | |
a1b2278e CK |
9066 | /* find scaler attached to this pipe */ |
9067 | for (i = 0; i < crtc->num_scalers; i++) { | |
9068 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
9069 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
9070 | id = i; | |
9071 | pipe_config->pch_pfit.enabled = true; | |
9072 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
9073 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
9074 | break; | |
9075 | } | |
9076 | } | |
bd2e244f | 9077 | |
a1b2278e CK |
9078 | scaler_state->scaler_id = id; |
9079 | if (id >= 0) { | |
9080 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
9081 | } else { | |
9082 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
9083 | } |
9084 | } | |
9085 | ||
5724dbd1 DL |
9086 | static void |
9087 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
9088 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
9089 | { |
9090 | struct drm_device *dev = crtc->base.dev; | |
9091 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40f46283 | 9092 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
9093 | int pipe = crtc->pipe; |
9094 | int fourcc, pixel_format; | |
6761dd31 | 9095 | unsigned int aligned_height; |
bc8d7dff | 9096 | struct drm_framebuffer *fb; |
1b842c89 | 9097 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 9098 | |
d9806c9f | 9099 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9100 | if (!intel_fb) { |
bc8d7dff DL |
9101 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9102 | return; | |
9103 | } | |
9104 | ||
1b842c89 DL |
9105 | fb = &intel_fb->base; |
9106 | ||
bc8d7dff | 9107 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
9108 | if (!(val & PLANE_CTL_ENABLE)) |
9109 | goto error; | |
9110 | ||
bc8d7dff DL |
9111 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
9112 | fourcc = skl_format_to_fourcc(pixel_format, | |
9113 | val & PLANE_CTL_ORDER_RGBX, | |
9114 | val & PLANE_CTL_ALPHA_MASK); | |
9115 | fb->pixel_format = fourcc; | |
9116 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
9117 | ||
40f46283 DL |
9118 | tiling = val & PLANE_CTL_TILED_MASK; |
9119 | switch (tiling) { | |
9120 | case PLANE_CTL_TILED_LINEAR: | |
9121 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
9122 | break; | |
9123 | case PLANE_CTL_TILED_X: | |
9124 | plane_config->tiling = I915_TILING_X; | |
9125 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
9126 | break; | |
9127 | case PLANE_CTL_TILED_Y: | |
9128 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
9129 | break; | |
9130 | case PLANE_CTL_TILED_YF: | |
9131 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
9132 | break; | |
9133 | default: | |
9134 | MISSING_CASE(tiling); | |
9135 | goto error; | |
9136 | } | |
9137 | ||
bc8d7dff DL |
9138 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
9139 | plane_config->base = base; | |
9140 | ||
9141 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
9142 | ||
9143 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
9144 | fb->height = ((val >> 16) & 0xfff) + 1; | |
9145 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
9146 | ||
9147 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
40f46283 DL |
9148 | stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0], |
9149 | fb->pixel_format); | |
bc8d7dff DL |
9150 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
9151 | ||
9152 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
9153 | fb->pixel_format, |
9154 | fb->modifier[0]); | |
bc8d7dff | 9155 | |
f37b5c2b | 9156 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
9157 | |
9158 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
9159 | pipe_name(pipe), fb->width, fb->height, | |
9160 | fb->bits_per_pixel, base, fb->pitches[0], | |
9161 | plane_config->size); | |
9162 | ||
2d14030b | 9163 | plane_config->fb = intel_fb; |
bc8d7dff DL |
9164 | return; |
9165 | ||
9166 | error: | |
9167 | kfree(fb); | |
9168 | } | |
9169 | ||
2fa2fe9a | 9170 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9171 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
9172 | { |
9173 | struct drm_device *dev = crtc->base.dev; | |
9174 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9175 | uint32_t tmp; | |
9176 | ||
9177 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
9178 | ||
9179 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 9180 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
9181 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
9182 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
9183 | |
9184 | /* We currently do not free assignements of panel fitters on | |
9185 | * ivb/hsw (since we don't use the higher upscaling modes which | |
9186 | * differentiates them) so just WARN about this case for now. */ | |
9187 | if (IS_GEN7(dev)) { | |
9188 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
9189 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
9190 | } | |
2fa2fe9a | 9191 | } |
79e53945 JB |
9192 | } |
9193 | ||
5724dbd1 DL |
9194 | static void |
9195 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
9196 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
9197 | { |
9198 | struct drm_device *dev = crtc->base.dev; | |
9199 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9200 | u32 val, base, offset; | |
aeee5a49 | 9201 | int pipe = crtc->pipe; |
4c6baa59 | 9202 | int fourcc, pixel_format; |
6761dd31 | 9203 | unsigned int aligned_height; |
b113d5ee | 9204 | struct drm_framebuffer *fb; |
1b842c89 | 9205 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 9206 | |
42a7b088 DL |
9207 | val = I915_READ(DSPCNTR(pipe)); |
9208 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
9209 | return; | |
9210 | ||
d9806c9f | 9211 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9212 | if (!intel_fb) { |
4c6baa59 JB |
9213 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9214 | return; | |
9215 | } | |
9216 | ||
1b842c89 DL |
9217 | fb = &intel_fb->base; |
9218 | ||
18c5247e DV |
9219 | if (INTEL_INFO(dev)->gen >= 4) { |
9220 | if (val & DISPPLANE_TILED) { | |
49af449b | 9221 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
9222 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
9223 | } | |
9224 | } | |
4c6baa59 JB |
9225 | |
9226 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 9227 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
9228 | fb->pixel_format = fourcc; |
9229 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 9230 | |
aeee5a49 | 9231 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 9232 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 9233 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 9234 | } else { |
49af449b | 9235 | if (plane_config->tiling) |
aeee5a49 | 9236 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 9237 | else |
aeee5a49 | 9238 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
9239 | } |
9240 | plane_config->base = base; | |
9241 | ||
9242 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
9243 | fb->width = ((val >> 16) & 0xfff) + 1; |
9244 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
9245 | |
9246 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 9247 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 9248 | |
b113d5ee | 9249 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
9250 | fb->pixel_format, |
9251 | fb->modifier[0]); | |
4c6baa59 | 9252 | |
f37b5c2b | 9253 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 9254 | |
2844a921 DL |
9255 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
9256 | pipe_name(pipe), fb->width, fb->height, | |
9257 | fb->bits_per_pixel, base, fb->pitches[0], | |
9258 | plane_config->size); | |
b113d5ee | 9259 | |
2d14030b | 9260 | plane_config->fb = intel_fb; |
4c6baa59 JB |
9261 | } |
9262 | ||
0e8ffe1b | 9263 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9264 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9265 | { |
9266 | struct drm_device *dev = crtc->base.dev; | |
9267 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9268 | uint32_t tmp; | |
9269 | ||
f458ebbc DV |
9270 | if (!intel_display_power_is_enabled(dev_priv, |
9271 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
930e8c9e PZ |
9272 | return false; |
9273 | ||
e143a21c | 9274 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 9275 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 9276 | |
0e8ffe1b DV |
9277 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
9278 | if (!(tmp & PIPECONF_ENABLE)) | |
9279 | return false; | |
9280 | ||
42571aef VS |
9281 | switch (tmp & PIPECONF_BPC_MASK) { |
9282 | case PIPECONF_6BPC: | |
9283 | pipe_config->pipe_bpp = 18; | |
9284 | break; | |
9285 | case PIPECONF_8BPC: | |
9286 | pipe_config->pipe_bpp = 24; | |
9287 | break; | |
9288 | case PIPECONF_10BPC: | |
9289 | pipe_config->pipe_bpp = 30; | |
9290 | break; | |
9291 | case PIPECONF_12BPC: | |
9292 | pipe_config->pipe_bpp = 36; | |
9293 | break; | |
9294 | default: | |
9295 | break; | |
9296 | } | |
9297 | ||
b5a9fa09 DV |
9298 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
9299 | pipe_config->limited_color_range = true; | |
9300 | ||
ab9412ba | 9301 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
9302 | struct intel_shared_dpll *pll; |
9303 | ||
88adfff1 DV |
9304 | pipe_config->has_pch_encoder = true; |
9305 | ||
627eb5a3 DV |
9306 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
9307 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9308 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
9309 | |
9310 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 9311 | |
c0d43d62 | 9312 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
9313 | pipe_config->shared_dpll = |
9314 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
9315 | } else { |
9316 | tmp = I915_READ(PCH_DPLL_SEL); | |
9317 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
9318 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
9319 | else | |
9320 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
9321 | } | |
66e985c0 DV |
9322 | |
9323 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
9324 | ||
9325 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
9326 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
9327 | |
9328 | tmp = pipe_config->dpll_hw_state.dpll; | |
9329 | pipe_config->pixel_multiplier = | |
9330 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
9331 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
9332 | |
9333 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
9334 | } else { |
9335 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
9336 | } |
9337 | ||
1bd1bd80 DV |
9338 | intel_get_pipe_timings(crtc, pipe_config); |
9339 | ||
2fa2fe9a DV |
9340 | ironlake_get_pfit_config(crtc, pipe_config); |
9341 | ||
0e8ffe1b DV |
9342 | return true; |
9343 | } | |
9344 | ||
be256dc7 PZ |
9345 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
9346 | { | |
9347 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 9348 | struct intel_crtc *crtc; |
be256dc7 | 9349 | |
d3fcc808 | 9350 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 9351 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
9352 | pipe_name(crtc->pipe)); |
9353 | ||
e2c719b7 RC |
9354 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
9355 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
01403de3 VS |
9356 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
9357 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
e2c719b7 RC |
9358 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
9359 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
be256dc7 | 9360 | "CPU PWM1 enabled\n"); |
c5107b87 | 9361 | if (IS_HASWELL(dev)) |
e2c719b7 | 9362 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 9363 | "CPU PWM2 enabled\n"); |
e2c719b7 | 9364 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 9365 | "PCH PWM1 enabled\n"); |
e2c719b7 | 9366 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 9367 | "Utility pin enabled\n"); |
e2c719b7 | 9368 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 9369 | |
9926ada1 PZ |
9370 | /* |
9371 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
9372 | * interrupts remain enabled. We used to check for that, but since it's | |
9373 | * gen-specific and since we only disable LCPLL after we fully disable | |
9374 | * the interrupts, the check below should be enough. | |
9375 | */ | |
e2c719b7 | 9376 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
9377 | } |
9378 | ||
9ccd5aeb PZ |
9379 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
9380 | { | |
9381 | struct drm_device *dev = dev_priv->dev; | |
9382 | ||
9383 | if (IS_HASWELL(dev)) | |
9384 | return I915_READ(D_COMP_HSW); | |
9385 | else | |
9386 | return I915_READ(D_COMP_BDW); | |
9387 | } | |
9388 | ||
3c4c9b81 PZ |
9389 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
9390 | { | |
9391 | struct drm_device *dev = dev_priv->dev; | |
9392 | ||
9393 | if (IS_HASWELL(dev)) { | |
9394 | mutex_lock(&dev_priv->rps.hw_lock); | |
9395 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
9396 | val)) | |
f475dadf | 9397 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
9398 | mutex_unlock(&dev_priv->rps.hw_lock); |
9399 | } else { | |
9ccd5aeb PZ |
9400 | I915_WRITE(D_COMP_BDW, val); |
9401 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 9402 | } |
be256dc7 PZ |
9403 | } |
9404 | ||
9405 | /* | |
9406 | * This function implements pieces of two sequences from BSpec: | |
9407 | * - Sequence for display software to disable LCPLL | |
9408 | * - Sequence for display software to allow package C8+ | |
9409 | * The steps implemented here are just the steps that actually touch the LCPLL | |
9410 | * register. Callers should take care of disabling all the display engine | |
9411 | * functions, doing the mode unset, fixing interrupts, etc. | |
9412 | */ | |
6ff58d53 PZ |
9413 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
9414 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
9415 | { |
9416 | uint32_t val; | |
9417 | ||
9418 | assert_can_disable_lcpll(dev_priv); | |
9419 | ||
9420 | val = I915_READ(LCPLL_CTL); | |
9421 | ||
9422 | if (switch_to_fclk) { | |
9423 | val |= LCPLL_CD_SOURCE_FCLK; | |
9424 | I915_WRITE(LCPLL_CTL, val); | |
9425 | ||
9426 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9427 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9428 | DRM_ERROR("Switching to FCLK failed\n"); | |
9429 | ||
9430 | val = I915_READ(LCPLL_CTL); | |
9431 | } | |
9432 | ||
9433 | val |= LCPLL_PLL_DISABLE; | |
9434 | I915_WRITE(LCPLL_CTL, val); | |
9435 | POSTING_READ(LCPLL_CTL); | |
9436 | ||
9437 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
9438 | DRM_ERROR("LCPLL still locked\n"); | |
9439 | ||
9ccd5aeb | 9440 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 9441 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 9442 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9443 | ndelay(100); |
9444 | ||
9ccd5aeb PZ |
9445 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
9446 | 1)) | |
be256dc7 PZ |
9447 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
9448 | ||
9449 | if (allow_power_down) { | |
9450 | val = I915_READ(LCPLL_CTL); | |
9451 | val |= LCPLL_POWER_DOWN_ALLOW; | |
9452 | I915_WRITE(LCPLL_CTL, val); | |
9453 | POSTING_READ(LCPLL_CTL); | |
9454 | } | |
9455 | } | |
9456 | ||
9457 | /* | |
9458 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
9459 | * source. | |
9460 | */ | |
6ff58d53 | 9461 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
9462 | { |
9463 | uint32_t val; | |
9464 | ||
9465 | val = I915_READ(LCPLL_CTL); | |
9466 | ||
9467 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
9468 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
9469 | return; | |
9470 | ||
a8a8bd54 PZ |
9471 | /* |
9472 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
9473 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 9474 | */ |
59bad947 | 9475 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 9476 | |
be256dc7 PZ |
9477 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
9478 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
9479 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 9480 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
9481 | } |
9482 | ||
9ccd5aeb | 9483 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
9484 | val |= D_COMP_COMP_FORCE; |
9485 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 9486 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9487 | |
9488 | val = I915_READ(LCPLL_CTL); | |
9489 | val &= ~LCPLL_PLL_DISABLE; | |
9490 | I915_WRITE(LCPLL_CTL, val); | |
9491 | ||
9492 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
9493 | DRM_ERROR("LCPLL not locked yet\n"); | |
9494 | ||
9495 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
9496 | val = I915_READ(LCPLL_CTL); | |
9497 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9498 | I915_WRITE(LCPLL_CTL, val); | |
9499 | ||
9500 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9501 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9502 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9503 | } | |
215733fa | 9504 | |
59bad947 | 9505 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b6283055 | 9506 | intel_update_cdclk(dev_priv->dev); |
be256dc7 PZ |
9507 | } |
9508 | ||
765dab67 PZ |
9509 | /* |
9510 | * Package states C8 and deeper are really deep PC states that can only be | |
9511 | * reached when all the devices on the system allow it, so even if the graphics | |
9512 | * device allows PC8+, it doesn't mean the system will actually get to these | |
9513 | * states. Our driver only allows PC8+ when going into runtime PM. | |
9514 | * | |
9515 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
9516 | * well is disabled and most interrupts are disabled, and these are also | |
9517 | * requirements for runtime PM. When these conditions are met, we manually do | |
9518 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
9519 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
9520 | * hang the machine. | |
9521 | * | |
9522 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
9523 | * the state of some registers, so when we come back from PC8+ we need to | |
9524 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
9525 | * need to take care of the registers kept by RC6. Notice that this happens even | |
9526 | * if we don't put the device in PCI D3 state (which is what currently happens | |
9527 | * because of the runtime PM support). | |
9528 | * | |
9529 | * For more, read "Display Sequences for Package C8" on the hardware | |
9530 | * documentation. | |
9531 | */ | |
a14cb6fc | 9532 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 9533 | { |
c67a470b PZ |
9534 | struct drm_device *dev = dev_priv->dev; |
9535 | uint32_t val; | |
9536 | ||
c67a470b PZ |
9537 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
9538 | ||
c2699524 | 9539 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9540 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9541 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
9542 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9543 | } | |
9544 | ||
9545 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
9546 | hsw_disable_lcpll(dev_priv, true, true); |
9547 | } | |
9548 | ||
a14cb6fc | 9549 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
9550 | { |
9551 | struct drm_device *dev = dev_priv->dev; | |
9552 | uint32_t val; | |
9553 | ||
c67a470b PZ |
9554 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
9555 | ||
9556 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
9557 | lpt_init_pch_refclk(dev); |
9558 | ||
c2699524 | 9559 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9560 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9561 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
9562 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9563 | } | |
9564 | ||
9565 | intel_prepare_ddi(dev); | |
c67a470b PZ |
9566 | } |
9567 | ||
27c329ed | 9568 | static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
f8437dd1 | 9569 | { |
a821fc46 | 9570 | struct drm_device *dev = old_state->dev; |
27c329ed | 9571 | unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk; |
f8437dd1 | 9572 | |
27c329ed | 9573 | broxton_set_cdclk(dev, req_cdclk); |
f8437dd1 VK |
9574 | } |
9575 | ||
b432e5cf | 9576 | /* compute the max rate for new configuration */ |
27c329ed | 9577 | static int ilk_max_pixel_rate(struct drm_atomic_state *state) |
b432e5cf | 9578 | { |
b432e5cf | 9579 | struct intel_crtc *intel_crtc; |
27c329ed | 9580 | struct intel_crtc_state *crtc_state; |
b432e5cf | 9581 | int max_pixel_rate = 0; |
b432e5cf | 9582 | |
27c329ed ML |
9583 | for_each_intel_crtc(state->dev, intel_crtc) { |
9584 | int pixel_rate; | |
9585 | ||
9586 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); | |
9587 | if (IS_ERR(crtc_state)) | |
9588 | return PTR_ERR(crtc_state); | |
9589 | ||
9590 | if (!crtc_state->base.enable) | |
b432e5cf VS |
9591 | continue; |
9592 | ||
27c329ed | 9593 | pixel_rate = ilk_pipe_pixel_rate(crtc_state); |
b432e5cf VS |
9594 | |
9595 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
27c329ed | 9596 | if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled) |
b432e5cf VS |
9597 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); |
9598 | ||
9599 | max_pixel_rate = max(max_pixel_rate, pixel_rate); | |
9600 | } | |
9601 | ||
9602 | return max_pixel_rate; | |
9603 | } | |
9604 | ||
9605 | static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) | |
9606 | { | |
9607 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9608 | uint32_t val, data; | |
9609 | int ret; | |
9610 | ||
9611 | if (WARN((I915_READ(LCPLL_CTL) & | |
9612 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | | |
9613 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | | |
9614 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | | |
9615 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, | |
9616 | "trying to change cdclk frequency with cdclk not enabled\n")) | |
9617 | return; | |
9618 | ||
9619 | mutex_lock(&dev_priv->rps.hw_lock); | |
9620 | ret = sandybridge_pcode_write(dev_priv, | |
9621 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); | |
9622 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9623 | if (ret) { | |
9624 | DRM_ERROR("failed to inform pcode about cdclk change\n"); | |
9625 | return; | |
9626 | } | |
9627 | ||
9628 | val = I915_READ(LCPLL_CTL); | |
9629 | val |= LCPLL_CD_SOURCE_FCLK; | |
9630 | I915_WRITE(LCPLL_CTL, val); | |
9631 | ||
9632 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9633 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9634 | DRM_ERROR("Switching to FCLK failed\n"); | |
9635 | ||
9636 | val = I915_READ(LCPLL_CTL); | |
9637 | val &= ~LCPLL_CLK_FREQ_MASK; | |
9638 | ||
9639 | switch (cdclk) { | |
9640 | case 450000: | |
9641 | val |= LCPLL_CLK_FREQ_450; | |
9642 | data = 0; | |
9643 | break; | |
9644 | case 540000: | |
9645 | val |= LCPLL_CLK_FREQ_54O_BDW; | |
9646 | data = 1; | |
9647 | break; | |
9648 | case 337500: | |
9649 | val |= LCPLL_CLK_FREQ_337_5_BDW; | |
9650 | data = 2; | |
9651 | break; | |
9652 | case 675000: | |
9653 | val |= LCPLL_CLK_FREQ_675_BDW; | |
9654 | data = 3; | |
9655 | break; | |
9656 | default: | |
9657 | WARN(1, "invalid cdclk frequency\n"); | |
9658 | return; | |
9659 | } | |
9660 | ||
9661 | I915_WRITE(LCPLL_CTL, val); | |
9662 | ||
9663 | val = I915_READ(LCPLL_CTL); | |
9664 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9665 | I915_WRITE(LCPLL_CTL, val); | |
9666 | ||
9667 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9668 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9669 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9670 | ||
9671 | mutex_lock(&dev_priv->rps.hw_lock); | |
9672 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); | |
9673 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9674 | ||
9675 | intel_update_cdclk(dev); | |
9676 | ||
9677 | WARN(cdclk != dev_priv->cdclk_freq, | |
9678 | "cdclk requested %d kHz but got %d kHz\n", | |
9679 | cdclk, dev_priv->cdclk_freq); | |
9680 | } | |
9681 | ||
27c329ed | 9682 | static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state) |
b432e5cf | 9683 | { |
27c329ed ML |
9684 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
9685 | int max_pixclk = ilk_max_pixel_rate(state); | |
b432e5cf VS |
9686 | int cdclk; |
9687 | ||
9688 | /* | |
9689 | * FIXME should also account for plane ratio | |
9690 | * once 64bpp pixel formats are supported. | |
9691 | */ | |
27c329ed | 9692 | if (max_pixclk > 540000) |
b432e5cf | 9693 | cdclk = 675000; |
27c329ed | 9694 | else if (max_pixclk > 450000) |
b432e5cf | 9695 | cdclk = 540000; |
27c329ed | 9696 | else if (max_pixclk > 337500) |
b432e5cf VS |
9697 | cdclk = 450000; |
9698 | else | |
9699 | cdclk = 337500; | |
9700 | ||
9701 | /* | |
9702 | * FIXME move the cdclk caclulation to | |
9703 | * compute_config() so we can fail gracegully. | |
9704 | */ | |
9705 | if (cdclk > dev_priv->max_cdclk_freq) { | |
9706 | DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n", | |
9707 | cdclk, dev_priv->max_cdclk_freq); | |
9708 | cdclk = dev_priv->max_cdclk_freq; | |
9709 | } | |
9710 | ||
27c329ed | 9711 | to_intel_atomic_state(state)->cdclk = cdclk; |
b432e5cf VS |
9712 | |
9713 | return 0; | |
9714 | } | |
9715 | ||
27c329ed | 9716 | static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
b432e5cf | 9717 | { |
27c329ed ML |
9718 | struct drm_device *dev = old_state->dev; |
9719 | unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk; | |
b432e5cf | 9720 | |
27c329ed | 9721 | broadwell_set_cdclk(dev, req_cdclk); |
b432e5cf VS |
9722 | } |
9723 | ||
190f68c5 ACO |
9724 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
9725 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 9726 | { |
190f68c5 | 9727 | if (!intel_ddi_pll_select(crtc, crtc_state)) |
6441ab5f | 9728 | return -EINVAL; |
716c2e55 | 9729 | |
c7653199 | 9730 | crtc->lowfreq_avail = false; |
644cef34 | 9731 | |
c8f7a0db | 9732 | return 0; |
79e53945 JB |
9733 | } |
9734 | ||
3760b59c S |
9735 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
9736 | enum port port, | |
9737 | struct intel_crtc_state *pipe_config) | |
9738 | { | |
9739 | switch (port) { | |
9740 | case PORT_A: | |
9741 | pipe_config->ddi_pll_sel = SKL_DPLL0; | |
9742 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9743 | break; | |
9744 | case PORT_B: | |
9745 | pipe_config->ddi_pll_sel = SKL_DPLL1; | |
9746 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9747 | break; | |
9748 | case PORT_C: | |
9749 | pipe_config->ddi_pll_sel = SKL_DPLL2; | |
9750 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9751 | break; | |
9752 | default: | |
9753 | DRM_ERROR("Incorrect port type\n"); | |
9754 | } | |
9755 | } | |
9756 | ||
96b7dfb7 S |
9757 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
9758 | enum port port, | |
5cec258b | 9759 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 9760 | { |
3148ade7 | 9761 | u32 temp, dpll_ctl1; |
96b7dfb7 S |
9762 | |
9763 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
9764 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
9765 | ||
9766 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 DL |
9767 | case SKL_DPLL0: |
9768 | /* | |
9769 | * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part | |
9770 | * of the shared DPLL framework and thus needs to be read out | |
9771 | * separately | |
9772 | */ | |
9773 | dpll_ctl1 = I915_READ(DPLL_CTRL1); | |
9774 | pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f; | |
9775 | break; | |
96b7dfb7 S |
9776 | case SKL_DPLL1: |
9777 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9778 | break; | |
9779 | case SKL_DPLL2: | |
9780 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9781 | break; | |
9782 | case SKL_DPLL3: | |
9783 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9784 | break; | |
96b7dfb7 S |
9785 | } |
9786 | } | |
9787 | ||
7d2c8175 DL |
9788 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
9789 | enum port port, | |
5cec258b | 9790 | struct intel_crtc_state *pipe_config) |
7d2c8175 DL |
9791 | { |
9792 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); | |
9793 | ||
9794 | switch (pipe_config->ddi_pll_sel) { | |
9795 | case PORT_CLK_SEL_WRPLL1: | |
9796 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; | |
9797 | break; | |
9798 | case PORT_CLK_SEL_WRPLL2: | |
9799 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; | |
9800 | break; | |
00490c22 ML |
9801 | case PORT_CLK_SEL_SPLL: |
9802 | pipe_config->shared_dpll = DPLL_ID_SPLL; | |
7d2c8175 DL |
9803 | } |
9804 | } | |
9805 | ||
26804afd | 9806 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 9807 | struct intel_crtc_state *pipe_config) |
26804afd DV |
9808 | { |
9809 | struct drm_device *dev = crtc->base.dev; | |
9810 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 9811 | struct intel_shared_dpll *pll; |
26804afd DV |
9812 | enum port port; |
9813 | uint32_t tmp; | |
9814 | ||
9815 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
9816 | ||
9817 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
9818 | ||
ef11bdb3 | 9819 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
96b7dfb7 | 9820 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
3760b59c S |
9821 | else if (IS_BROXTON(dev)) |
9822 | bxt_get_ddi_pll(dev_priv, port, pipe_config); | |
96b7dfb7 S |
9823 | else |
9824 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 9825 | |
d452c5b6 DV |
9826 | if (pipe_config->shared_dpll >= 0) { |
9827 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
9828 | ||
9829 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
9830 | &pipe_config->dpll_hw_state)); | |
9831 | } | |
9832 | ||
26804afd DV |
9833 | /* |
9834 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
9835 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
9836 | * the PCH transcoder is on. | |
9837 | */ | |
ca370455 DL |
9838 | if (INTEL_INFO(dev)->gen < 9 && |
9839 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
9840 | pipe_config->has_pch_encoder = true; |
9841 | ||
9842 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
9843 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9844 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
9845 | ||
9846 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
9847 | } | |
9848 | } | |
9849 | ||
0e8ffe1b | 9850 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9851 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9852 | { |
9853 | struct drm_device *dev = crtc->base.dev; | |
9854 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 9855 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
9856 | uint32_t tmp; |
9857 | ||
f458ebbc | 9858 | if (!intel_display_power_is_enabled(dev_priv, |
b5482bd0 ID |
9859 | POWER_DOMAIN_PIPE(crtc->pipe))) |
9860 | return false; | |
9861 | ||
e143a21c | 9862 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
9863 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
9864 | ||
eccb140b DV |
9865 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
9866 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
9867 | enum pipe trans_edp_pipe; | |
9868 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
9869 | default: | |
9870 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
9871 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
9872 | case TRANS_DDI_EDP_INPUT_A_ON: | |
9873 | trans_edp_pipe = PIPE_A; | |
9874 | break; | |
9875 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
9876 | trans_edp_pipe = PIPE_B; | |
9877 | break; | |
9878 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
9879 | trans_edp_pipe = PIPE_C; | |
9880 | break; | |
9881 | } | |
9882 | ||
9883 | if (trans_edp_pipe == crtc->pipe) | |
9884 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
9885 | } | |
9886 | ||
f458ebbc | 9887 | if (!intel_display_power_is_enabled(dev_priv, |
eccb140b | 9888 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
9889 | return false; |
9890 | ||
eccb140b | 9891 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
9892 | if (!(tmp & PIPECONF_ENABLE)) |
9893 | return false; | |
9894 | ||
26804afd | 9895 | haswell_get_ddi_port_state(crtc, pipe_config); |
627eb5a3 | 9896 | |
1bd1bd80 DV |
9897 | intel_get_pipe_timings(crtc, pipe_config); |
9898 | ||
a1b2278e CK |
9899 | if (INTEL_INFO(dev)->gen >= 9) { |
9900 | skl_init_scalers(dev, crtc, pipe_config); | |
9901 | } | |
9902 | ||
2fa2fe9a | 9903 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
af99ceda CK |
9904 | |
9905 | if (INTEL_INFO(dev)->gen >= 9) { | |
9906 | pipe_config->scaler_state.scaler_id = -1; | |
9907 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
9908 | } | |
9909 | ||
bd2e244f | 9910 | if (intel_display_power_is_enabled(dev_priv, pfit_domain)) { |
1c132b44 | 9911 | if (INTEL_INFO(dev)->gen >= 9) |
bd2e244f | 9912 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 9913 | else |
1c132b44 | 9914 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 9915 | } |
88adfff1 | 9916 | |
e59150dc JB |
9917 | if (IS_HASWELL(dev)) |
9918 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
9919 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 9920 | |
ebb69c95 CT |
9921 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP) { |
9922 | pipe_config->pixel_multiplier = | |
9923 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
9924 | } else { | |
9925 | pipe_config->pixel_multiplier = 1; | |
9926 | } | |
6c49f241 | 9927 | |
0e8ffe1b DV |
9928 | return true; |
9929 | } | |
9930 | ||
560b85bb CW |
9931 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
9932 | { | |
9933 | struct drm_device *dev = crtc->dev; | |
9934 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9935 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 9936 | uint32_t cntl = 0, size = 0; |
560b85bb | 9937 | |
dc41c154 | 9938 | if (base) { |
3dd512fb MR |
9939 | unsigned int width = intel_crtc->base.cursor->state->crtc_w; |
9940 | unsigned int height = intel_crtc->base.cursor->state->crtc_h; | |
dc41c154 VS |
9941 | unsigned int stride = roundup_pow_of_two(width) * 4; |
9942 | ||
9943 | switch (stride) { | |
9944 | default: | |
9945 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
9946 | width, stride); | |
9947 | stride = 256; | |
9948 | /* fallthrough */ | |
9949 | case 256: | |
9950 | case 512: | |
9951 | case 1024: | |
9952 | case 2048: | |
9953 | break; | |
4b0e333e CW |
9954 | } |
9955 | ||
dc41c154 VS |
9956 | cntl |= CURSOR_ENABLE | |
9957 | CURSOR_GAMMA_ENABLE | | |
9958 | CURSOR_FORMAT_ARGB | | |
9959 | CURSOR_STRIDE(stride); | |
9960 | ||
9961 | size = (height << 12) | width; | |
4b0e333e | 9962 | } |
560b85bb | 9963 | |
dc41c154 VS |
9964 | if (intel_crtc->cursor_cntl != 0 && |
9965 | (intel_crtc->cursor_base != base || | |
9966 | intel_crtc->cursor_size != size || | |
9967 | intel_crtc->cursor_cntl != cntl)) { | |
9968 | /* On these chipsets we can only modify the base/size/stride | |
9969 | * whilst the cursor is disabled. | |
9970 | */ | |
0b87c24e VS |
9971 | I915_WRITE(CURCNTR(PIPE_A), 0); |
9972 | POSTING_READ(CURCNTR(PIPE_A)); | |
dc41c154 | 9973 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 9974 | } |
560b85bb | 9975 | |
99d1f387 | 9976 | if (intel_crtc->cursor_base != base) { |
0b87c24e | 9977 | I915_WRITE(CURBASE(PIPE_A), base); |
99d1f387 VS |
9978 | intel_crtc->cursor_base = base; |
9979 | } | |
4726e0b0 | 9980 | |
dc41c154 VS |
9981 | if (intel_crtc->cursor_size != size) { |
9982 | I915_WRITE(CURSIZE, size); | |
9983 | intel_crtc->cursor_size = size; | |
4b0e333e | 9984 | } |
560b85bb | 9985 | |
4b0e333e | 9986 | if (intel_crtc->cursor_cntl != cntl) { |
0b87c24e VS |
9987 | I915_WRITE(CURCNTR(PIPE_A), cntl); |
9988 | POSTING_READ(CURCNTR(PIPE_A)); | |
4b0e333e | 9989 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 9990 | } |
560b85bb CW |
9991 | } |
9992 | ||
560b85bb | 9993 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
65a21cd6 JB |
9994 | { |
9995 | struct drm_device *dev = crtc->dev; | |
9996 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9997 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9998 | int pipe = intel_crtc->pipe; | |
4b0e333e CW |
9999 | uint32_t cntl; |
10000 | ||
10001 | cntl = 0; | |
10002 | if (base) { | |
10003 | cntl = MCURSOR_GAMMA_ENABLE; | |
3dd512fb | 10004 | switch (intel_crtc->base.cursor->state->crtc_w) { |
4726e0b0 SK |
10005 | case 64: |
10006 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
10007 | break; | |
10008 | case 128: | |
10009 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
10010 | break; | |
10011 | case 256: | |
10012 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
10013 | break; | |
10014 | default: | |
3dd512fb | 10015 | MISSING_CASE(intel_crtc->base.cursor->state->crtc_w); |
4726e0b0 | 10016 | return; |
65a21cd6 | 10017 | } |
4b0e333e | 10018 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 | 10019 | |
fc6f93bc | 10020 | if (HAS_DDI(dev)) |
47bf17a7 | 10021 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
4b0e333e | 10022 | } |
65a21cd6 | 10023 | |
8e7d688b | 10024 | if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) |
4398ad45 VS |
10025 | cntl |= CURSOR_ROTATE_180; |
10026 | ||
4b0e333e CW |
10027 | if (intel_crtc->cursor_cntl != cntl) { |
10028 | I915_WRITE(CURCNTR(pipe), cntl); | |
10029 | POSTING_READ(CURCNTR(pipe)); | |
10030 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 10031 | } |
4b0e333e | 10032 | |
65a21cd6 | 10033 | /* and commit changes on next vblank */ |
5efb3e28 VS |
10034 | I915_WRITE(CURBASE(pipe), base); |
10035 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
10036 | |
10037 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
10038 | } |
10039 | ||
cda4b7d3 | 10040 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
10041 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
10042 | bool on) | |
cda4b7d3 CW |
10043 | { |
10044 | struct drm_device *dev = crtc->dev; | |
10045 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10046 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10047 | int pipe = intel_crtc->pipe; | |
9b4101be ML |
10048 | struct drm_plane_state *cursor_state = crtc->cursor->state; |
10049 | int x = cursor_state->crtc_x; | |
10050 | int y = cursor_state->crtc_y; | |
d6e4db15 | 10051 | u32 base = 0, pos = 0; |
cda4b7d3 | 10052 | |
d6e4db15 | 10053 | if (on) |
cda4b7d3 | 10054 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 10055 | |
6e3c9717 | 10056 | if (x >= intel_crtc->config->pipe_src_w) |
d6e4db15 VS |
10057 | base = 0; |
10058 | ||
6e3c9717 | 10059 | if (y >= intel_crtc->config->pipe_src_h) |
cda4b7d3 CW |
10060 | base = 0; |
10061 | ||
10062 | if (x < 0) { | |
9b4101be | 10063 | if (x + cursor_state->crtc_w <= 0) |
cda4b7d3 CW |
10064 | base = 0; |
10065 | ||
10066 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
10067 | x = -x; | |
10068 | } | |
10069 | pos |= x << CURSOR_X_SHIFT; | |
10070 | ||
10071 | if (y < 0) { | |
9b4101be | 10072 | if (y + cursor_state->crtc_h <= 0) |
cda4b7d3 CW |
10073 | base = 0; |
10074 | ||
10075 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
10076 | y = -y; | |
10077 | } | |
10078 | pos |= y << CURSOR_Y_SHIFT; | |
10079 | ||
4b0e333e | 10080 | if (base == 0 && intel_crtc->cursor_base == 0) |
cda4b7d3 CW |
10081 | return; |
10082 | ||
5efb3e28 VS |
10083 | I915_WRITE(CURPOS(pipe), pos); |
10084 | ||
4398ad45 VS |
10085 | /* ILK+ do this automagically */ |
10086 | if (HAS_GMCH_DISPLAY(dev) && | |
8e7d688b | 10087 | crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) { |
9b4101be ML |
10088 | base += (cursor_state->crtc_h * |
10089 | cursor_state->crtc_w - 1) * 4; | |
4398ad45 VS |
10090 | } |
10091 | ||
8ac54669 | 10092 | if (IS_845G(dev) || IS_I865G(dev)) |
5efb3e28 VS |
10093 | i845_update_cursor(crtc, base); |
10094 | else | |
10095 | i9xx_update_cursor(crtc, base); | |
cda4b7d3 CW |
10096 | } |
10097 | ||
dc41c154 VS |
10098 | static bool cursor_size_ok(struct drm_device *dev, |
10099 | uint32_t width, uint32_t height) | |
10100 | { | |
10101 | if (width == 0 || height == 0) | |
10102 | return false; | |
10103 | ||
10104 | /* | |
10105 | * 845g/865g are special in that they are only limited by | |
10106 | * the width of their cursors, the height is arbitrary up to | |
10107 | * the precision of the register. Everything else requires | |
10108 | * square cursors, limited to a few power-of-two sizes. | |
10109 | */ | |
10110 | if (IS_845G(dev) || IS_I865G(dev)) { | |
10111 | if ((width & 63) != 0) | |
10112 | return false; | |
10113 | ||
10114 | if (width > (IS_845G(dev) ? 64 : 512)) | |
10115 | return false; | |
10116 | ||
10117 | if (height > 1023) | |
10118 | return false; | |
10119 | } else { | |
10120 | switch (width | height) { | |
10121 | case 256: | |
10122 | case 128: | |
10123 | if (IS_GEN2(dev)) | |
10124 | return false; | |
10125 | case 64: | |
10126 | break; | |
10127 | default: | |
10128 | return false; | |
10129 | } | |
10130 | } | |
10131 | ||
10132 | return true; | |
10133 | } | |
10134 | ||
79e53945 | 10135 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 10136 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 10137 | { |
7203425a | 10138 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 10139 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 10140 | |
7203425a | 10141 | for (i = start; i < end; i++) { |
79e53945 JB |
10142 | intel_crtc->lut_r[i] = red[i] >> 8; |
10143 | intel_crtc->lut_g[i] = green[i] >> 8; | |
10144 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
10145 | } | |
10146 | ||
10147 | intel_crtc_load_lut(crtc); | |
10148 | } | |
10149 | ||
79e53945 JB |
10150 | /* VESA 640x480x72Hz mode to set on the pipe */ |
10151 | static struct drm_display_mode load_detect_mode = { | |
10152 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
10153 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
10154 | }; | |
10155 | ||
a8bb6818 DV |
10156 | struct drm_framebuffer * |
10157 | __intel_framebuffer_create(struct drm_device *dev, | |
10158 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10159 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
10160 | { |
10161 | struct intel_framebuffer *intel_fb; | |
10162 | int ret; | |
10163 | ||
10164 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
dcb1394e | 10165 | if (!intel_fb) |
d2dff872 | 10166 | return ERR_PTR(-ENOMEM); |
d2dff872 CW |
10167 | |
10168 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
10169 | if (ret) |
10170 | goto err; | |
d2dff872 CW |
10171 | |
10172 | return &intel_fb->base; | |
dcb1394e | 10173 | |
dd4916c5 | 10174 | err: |
dd4916c5 | 10175 | kfree(intel_fb); |
dd4916c5 | 10176 | return ERR_PTR(ret); |
d2dff872 CW |
10177 | } |
10178 | ||
b5ea642a | 10179 | static struct drm_framebuffer * |
a8bb6818 DV |
10180 | intel_framebuffer_create(struct drm_device *dev, |
10181 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10182 | struct drm_i915_gem_object *obj) | |
10183 | { | |
10184 | struct drm_framebuffer *fb; | |
10185 | int ret; | |
10186 | ||
10187 | ret = i915_mutex_lock_interruptible(dev); | |
10188 | if (ret) | |
10189 | return ERR_PTR(ret); | |
10190 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
10191 | mutex_unlock(&dev->struct_mutex); | |
10192 | ||
10193 | return fb; | |
10194 | } | |
10195 | ||
d2dff872 CW |
10196 | static u32 |
10197 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
10198 | { | |
10199 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
10200 | return ALIGN(pitch, 64); | |
10201 | } | |
10202 | ||
10203 | static u32 | |
10204 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
10205 | { | |
10206 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 10207 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
10208 | } |
10209 | ||
10210 | static struct drm_framebuffer * | |
10211 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
10212 | struct drm_display_mode *mode, | |
10213 | int depth, int bpp) | |
10214 | { | |
dcb1394e | 10215 | struct drm_framebuffer *fb; |
d2dff872 | 10216 | struct drm_i915_gem_object *obj; |
0fed39bd | 10217 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
10218 | |
10219 | obj = i915_gem_alloc_object(dev, | |
10220 | intel_framebuffer_size_for_mode(mode, bpp)); | |
10221 | if (obj == NULL) | |
10222 | return ERR_PTR(-ENOMEM); | |
10223 | ||
10224 | mode_cmd.width = mode->hdisplay; | |
10225 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
10226 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
10227 | bpp); | |
5ca0c34a | 10228 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 | 10229 | |
dcb1394e LW |
10230 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
10231 | if (IS_ERR(fb)) | |
10232 | drm_gem_object_unreference_unlocked(&obj->base); | |
10233 | ||
10234 | return fb; | |
d2dff872 CW |
10235 | } |
10236 | ||
10237 | static struct drm_framebuffer * | |
10238 | mode_fits_in_fbdev(struct drm_device *dev, | |
10239 | struct drm_display_mode *mode) | |
10240 | { | |
0695726e | 10241 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
d2dff872 CW |
10242 | struct drm_i915_private *dev_priv = dev->dev_private; |
10243 | struct drm_i915_gem_object *obj; | |
10244 | struct drm_framebuffer *fb; | |
10245 | ||
4c0e5528 | 10246 | if (!dev_priv->fbdev) |
d2dff872 CW |
10247 | return NULL; |
10248 | ||
4c0e5528 | 10249 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
10250 | return NULL; |
10251 | ||
4c0e5528 DV |
10252 | obj = dev_priv->fbdev->fb->obj; |
10253 | BUG_ON(!obj); | |
10254 | ||
8bcd4553 | 10255 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
10256 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
10257 | fb->bits_per_pixel)) | |
d2dff872 CW |
10258 | return NULL; |
10259 | ||
01f2c773 | 10260 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
10261 | return NULL; |
10262 | ||
10263 | return fb; | |
4520f53a DV |
10264 | #else |
10265 | return NULL; | |
10266 | #endif | |
d2dff872 CW |
10267 | } |
10268 | ||
d3a40d1b ACO |
10269 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
10270 | struct drm_crtc *crtc, | |
10271 | struct drm_display_mode *mode, | |
10272 | struct drm_framebuffer *fb, | |
10273 | int x, int y) | |
10274 | { | |
10275 | struct drm_plane_state *plane_state; | |
10276 | int hdisplay, vdisplay; | |
10277 | int ret; | |
10278 | ||
10279 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
10280 | if (IS_ERR(plane_state)) | |
10281 | return PTR_ERR(plane_state); | |
10282 | ||
10283 | if (mode) | |
10284 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); | |
10285 | else | |
10286 | hdisplay = vdisplay = 0; | |
10287 | ||
10288 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
10289 | if (ret) | |
10290 | return ret; | |
10291 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
10292 | plane_state->crtc_x = 0; | |
10293 | plane_state->crtc_y = 0; | |
10294 | plane_state->crtc_w = hdisplay; | |
10295 | plane_state->crtc_h = vdisplay; | |
10296 | plane_state->src_x = x << 16; | |
10297 | plane_state->src_y = y << 16; | |
10298 | plane_state->src_w = hdisplay << 16; | |
10299 | plane_state->src_h = vdisplay << 16; | |
10300 | ||
10301 | return 0; | |
10302 | } | |
10303 | ||
d2434ab7 | 10304 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 10305 | struct drm_display_mode *mode, |
51fd371b RC |
10306 | struct intel_load_detect_pipe *old, |
10307 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
10308 | { |
10309 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
10310 | struct intel_encoder *intel_encoder = |
10311 | intel_attached_encoder(connector); | |
79e53945 | 10312 | struct drm_crtc *possible_crtc; |
4ef69c7a | 10313 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
10314 | struct drm_crtc *crtc = NULL; |
10315 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 10316 | struct drm_framebuffer *fb; |
51fd371b | 10317 | struct drm_mode_config *config = &dev->mode_config; |
83a57153 | 10318 | struct drm_atomic_state *state = NULL; |
944b0c76 | 10319 | struct drm_connector_state *connector_state; |
4be07317 | 10320 | struct intel_crtc_state *crtc_state; |
51fd371b | 10321 | int ret, i = -1; |
79e53945 | 10322 | |
d2dff872 | 10323 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10324 | connector->base.id, connector->name, |
8e329a03 | 10325 | encoder->base.id, encoder->name); |
d2dff872 | 10326 | |
51fd371b RC |
10327 | retry: |
10328 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
10329 | if (ret) | |
ad3c558f | 10330 | goto fail; |
6e9f798d | 10331 | |
79e53945 JB |
10332 | /* |
10333 | * Algorithm gets a little messy: | |
7a5e4805 | 10334 | * |
79e53945 JB |
10335 | * - if the connector already has an assigned crtc, use it (but make |
10336 | * sure it's on first) | |
7a5e4805 | 10337 | * |
79e53945 JB |
10338 | * - try to find the first unused crtc that can drive this connector, |
10339 | * and use that if we find one | |
79e53945 JB |
10340 | */ |
10341 | ||
10342 | /* See if we already have a CRTC for this connector */ | |
10343 | if (encoder->crtc) { | |
10344 | crtc = encoder->crtc; | |
8261b191 | 10345 | |
51fd371b | 10346 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 10347 | if (ret) |
ad3c558f | 10348 | goto fail; |
4d02e2de | 10349 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
51fd371b | 10350 | if (ret) |
ad3c558f | 10351 | goto fail; |
7b24056b | 10352 | |
24218aac | 10353 | old->dpms_mode = connector->dpms; |
8261b191 CW |
10354 | old->load_detect_temp = false; |
10355 | ||
10356 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
10357 | if (connector->dpms != DRM_MODE_DPMS_ON) |
10358 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 10359 | |
7173188d | 10360 | return true; |
79e53945 JB |
10361 | } |
10362 | ||
10363 | /* Find an unused one (if possible) */ | |
70e1e0ec | 10364 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
10365 | i++; |
10366 | if (!(encoder->possible_crtcs & (1 << i))) | |
10367 | continue; | |
83d65738 | 10368 | if (possible_crtc->state->enable) |
a459249c | 10369 | continue; |
a459249c VS |
10370 | |
10371 | crtc = possible_crtc; | |
10372 | break; | |
79e53945 JB |
10373 | } |
10374 | ||
10375 | /* | |
10376 | * If we didn't find an unused CRTC, don't use any. | |
10377 | */ | |
10378 | if (!crtc) { | |
7173188d | 10379 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
ad3c558f | 10380 | goto fail; |
79e53945 JB |
10381 | } |
10382 | ||
51fd371b RC |
10383 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
10384 | if (ret) | |
ad3c558f | 10385 | goto fail; |
4d02e2de DV |
10386 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
10387 | if (ret) | |
ad3c558f | 10388 | goto fail; |
79e53945 JB |
10389 | |
10390 | intel_crtc = to_intel_crtc(crtc); | |
24218aac | 10391 | old->dpms_mode = connector->dpms; |
8261b191 | 10392 | old->load_detect_temp = true; |
d2dff872 | 10393 | old->release_fb = NULL; |
79e53945 | 10394 | |
83a57153 ACO |
10395 | state = drm_atomic_state_alloc(dev); |
10396 | if (!state) | |
10397 | return false; | |
10398 | ||
10399 | state->acquire_ctx = ctx; | |
10400 | ||
944b0c76 ACO |
10401 | connector_state = drm_atomic_get_connector_state(state, connector); |
10402 | if (IS_ERR(connector_state)) { | |
10403 | ret = PTR_ERR(connector_state); | |
10404 | goto fail; | |
10405 | } | |
10406 | ||
10407 | connector_state->crtc = crtc; | |
10408 | connector_state->best_encoder = &intel_encoder->base; | |
10409 | ||
4be07317 ACO |
10410 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10411 | if (IS_ERR(crtc_state)) { | |
10412 | ret = PTR_ERR(crtc_state); | |
10413 | goto fail; | |
10414 | } | |
10415 | ||
49d6fa21 | 10416 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 10417 | |
6492711d CW |
10418 | if (!mode) |
10419 | mode = &load_detect_mode; | |
79e53945 | 10420 | |
d2dff872 CW |
10421 | /* We need a framebuffer large enough to accommodate all accesses |
10422 | * that the plane may generate whilst we perform load detection. | |
10423 | * We can not rely on the fbcon either being present (we get called | |
10424 | * during its initialisation to detect all boot displays, or it may | |
10425 | * not even exist) or that it is large enough to satisfy the | |
10426 | * requested mode. | |
10427 | */ | |
94352cf9 DV |
10428 | fb = mode_fits_in_fbdev(dev, mode); |
10429 | if (fb == NULL) { | |
d2dff872 | 10430 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
10431 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
10432 | old->release_fb = fb; | |
d2dff872 CW |
10433 | } else |
10434 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 10435 | if (IS_ERR(fb)) { |
d2dff872 | 10436 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 10437 | goto fail; |
79e53945 | 10438 | } |
79e53945 | 10439 | |
d3a40d1b ACO |
10440 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
10441 | if (ret) | |
10442 | goto fail; | |
10443 | ||
8c7b5ccb ACO |
10444 | drm_mode_copy(&crtc_state->base.mode, mode); |
10445 | ||
74c090b1 | 10446 | if (drm_atomic_commit(state)) { |
6492711d | 10447 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
10448 | if (old->release_fb) |
10449 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 10450 | goto fail; |
79e53945 | 10451 | } |
9128b040 | 10452 | crtc->primary->crtc = crtc; |
7173188d | 10453 | |
79e53945 | 10454 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 10455 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 10456 | return true; |
412b61d8 | 10457 | |
ad3c558f | 10458 | fail: |
e5d958ef ACO |
10459 | drm_atomic_state_free(state); |
10460 | state = NULL; | |
83a57153 | 10461 | |
51fd371b RC |
10462 | if (ret == -EDEADLK) { |
10463 | drm_modeset_backoff(ctx); | |
10464 | goto retry; | |
10465 | } | |
10466 | ||
412b61d8 | 10467 | return false; |
79e53945 JB |
10468 | } |
10469 | ||
d2434ab7 | 10470 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
10471 | struct intel_load_detect_pipe *old, |
10472 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 10473 | { |
83a57153 | 10474 | struct drm_device *dev = connector->dev; |
d2434ab7 DV |
10475 | struct intel_encoder *intel_encoder = |
10476 | intel_attached_encoder(connector); | |
4ef69c7a | 10477 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 10478 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 10479 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
83a57153 | 10480 | struct drm_atomic_state *state; |
944b0c76 | 10481 | struct drm_connector_state *connector_state; |
4be07317 | 10482 | struct intel_crtc_state *crtc_state; |
d3a40d1b | 10483 | int ret; |
79e53945 | 10484 | |
d2dff872 | 10485 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10486 | connector->base.id, connector->name, |
8e329a03 | 10487 | encoder->base.id, encoder->name); |
d2dff872 | 10488 | |
8261b191 | 10489 | if (old->load_detect_temp) { |
83a57153 | 10490 | state = drm_atomic_state_alloc(dev); |
944b0c76 ACO |
10491 | if (!state) |
10492 | goto fail; | |
83a57153 ACO |
10493 | |
10494 | state->acquire_ctx = ctx; | |
10495 | ||
944b0c76 ACO |
10496 | connector_state = drm_atomic_get_connector_state(state, connector); |
10497 | if (IS_ERR(connector_state)) | |
10498 | goto fail; | |
10499 | ||
4be07317 ACO |
10500 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10501 | if (IS_ERR(crtc_state)) | |
10502 | goto fail; | |
10503 | ||
944b0c76 ACO |
10504 | connector_state->best_encoder = NULL; |
10505 | connector_state->crtc = NULL; | |
10506 | ||
49d6fa21 | 10507 | crtc_state->base.enable = crtc_state->base.active = false; |
4be07317 | 10508 | |
d3a40d1b ACO |
10509 | ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL, |
10510 | 0, 0); | |
10511 | if (ret) | |
10512 | goto fail; | |
10513 | ||
74c090b1 | 10514 | ret = drm_atomic_commit(state); |
2bfb4627 ACO |
10515 | if (ret) |
10516 | goto fail; | |
d2dff872 | 10517 | |
36206361 DV |
10518 | if (old->release_fb) { |
10519 | drm_framebuffer_unregister_private(old->release_fb); | |
10520 | drm_framebuffer_unreference(old->release_fb); | |
10521 | } | |
d2dff872 | 10522 | |
0622a53c | 10523 | return; |
79e53945 JB |
10524 | } |
10525 | ||
c751ce4f | 10526 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
10527 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
10528 | connector->funcs->dpms(connector, old->dpms_mode); | |
944b0c76 ACO |
10529 | |
10530 | return; | |
10531 | fail: | |
10532 | DRM_DEBUG_KMS("Couldn't release load detect pipe.\n"); | |
10533 | drm_atomic_state_free(state); | |
79e53945 JB |
10534 | } |
10535 | ||
da4a1efa | 10536 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 10537 | const struct intel_crtc_state *pipe_config) |
da4a1efa VS |
10538 | { |
10539 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10540 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
10541 | ||
10542 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 10543 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
10544 | else if (HAS_PCH_SPLIT(dev)) |
10545 | return 120000; | |
10546 | else if (!IS_GEN2(dev)) | |
10547 | return 96000; | |
10548 | else | |
10549 | return 48000; | |
10550 | } | |
10551 | ||
79e53945 | 10552 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 10553 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 10554 | struct intel_crtc_state *pipe_config) |
79e53945 | 10555 | { |
f1f644dc | 10556 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 10557 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 10558 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 10559 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
10560 | u32 fp; |
10561 | intel_clock_t clock; | |
dccbea3b | 10562 | int port_clock; |
da4a1efa | 10563 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
10564 | |
10565 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 10566 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 10567 | else |
293623f7 | 10568 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
10569 | |
10570 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
10571 | if (IS_PINEVIEW(dev)) { |
10572 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
10573 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
10574 | } else { |
10575 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
10576 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
10577 | } | |
10578 | ||
a6c45cf0 | 10579 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
10580 | if (IS_PINEVIEW(dev)) |
10581 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
10582 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
10583 | else |
10584 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
10585 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
10586 | ||
10587 | switch (dpll & DPLL_MODE_MASK) { | |
10588 | case DPLLB_MODE_DAC_SERIAL: | |
10589 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
10590 | 5 : 10; | |
10591 | break; | |
10592 | case DPLLB_MODE_LVDS: | |
10593 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
10594 | 7 : 14; | |
10595 | break; | |
10596 | default: | |
28c97730 | 10597 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 10598 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 10599 | return; |
79e53945 JB |
10600 | } |
10601 | ||
ac58c3f0 | 10602 | if (IS_PINEVIEW(dev)) |
dccbea3b | 10603 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 10604 | else |
dccbea3b | 10605 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 10606 | } else { |
0fb58223 | 10607 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 10608 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
10609 | |
10610 | if (is_lvds) { | |
10611 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
10612 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
10613 | |
10614 | if (lvds & LVDS_CLKB_POWER_UP) | |
10615 | clock.p2 = 7; | |
10616 | else | |
10617 | clock.p2 = 14; | |
79e53945 JB |
10618 | } else { |
10619 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
10620 | clock.p1 = 2; | |
10621 | else { | |
10622 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
10623 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
10624 | } | |
10625 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
10626 | clock.p2 = 4; | |
10627 | else | |
10628 | clock.p2 = 2; | |
79e53945 | 10629 | } |
da4a1efa | 10630 | |
dccbea3b | 10631 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
10632 | } |
10633 | ||
18442d08 VS |
10634 | /* |
10635 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 10636 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
10637 | * encoder's get_config() function. |
10638 | */ | |
dccbea3b | 10639 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
10640 | } |
10641 | ||
6878da05 VS |
10642 | int intel_dotclock_calculate(int link_freq, |
10643 | const struct intel_link_m_n *m_n) | |
f1f644dc | 10644 | { |
f1f644dc JB |
10645 | /* |
10646 | * The calculation for the data clock is: | |
1041a02f | 10647 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 10648 | * But we want to avoid losing precison if possible, so: |
1041a02f | 10649 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
10650 | * |
10651 | * and the link clock is simpler: | |
1041a02f | 10652 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
10653 | */ |
10654 | ||
6878da05 VS |
10655 | if (!m_n->link_n) |
10656 | return 0; | |
f1f644dc | 10657 | |
6878da05 VS |
10658 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
10659 | } | |
f1f644dc | 10660 | |
18442d08 | 10661 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 10662 | struct intel_crtc_state *pipe_config) |
6878da05 VS |
10663 | { |
10664 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 10665 | |
18442d08 VS |
10666 | /* read out port_clock from the DPLL */ |
10667 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 10668 | |
f1f644dc | 10669 | /* |
18442d08 | 10670 | * This value does not include pixel_multiplier. |
241bfc38 | 10671 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
10672 | * agree once we know their relationship in the encoder's |
10673 | * get_config() function. | |
79e53945 | 10674 | */ |
2d112de7 | 10675 | pipe_config->base.adjusted_mode.crtc_clock = |
18442d08 VS |
10676 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
10677 | &pipe_config->fdi_m_n); | |
79e53945 JB |
10678 | } |
10679 | ||
10680 | /** Returns the currently programmed mode of the given pipe. */ | |
10681 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
10682 | struct drm_crtc *crtc) | |
10683 | { | |
548f245b | 10684 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 10685 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 10686 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 10687 | struct drm_display_mode *mode; |
5cec258b | 10688 | struct intel_crtc_state pipe_config; |
fe2b8f9d PZ |
10689 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
10690 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
10691 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
10692 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 10693 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
10694 | |
10695 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
10696 | if (!mode) | |
10697 | return NULL; | |
10698 | ||
f1f644dc JB |
10699 | /* |
10700 | * Construct a pipe_config sufficient for getting the clock info | |
10701 | * back out of crtc_clock_get. | |
10702 | * | |
10703 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
10704 | * to use a real value here instead. | |
10705 | */ | |
293623f7 | 10706 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 10707 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
10708 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
10709 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
10710 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
10711 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
10712 | ||
773ae034 | 10713 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
10714 | mode->hdisplay = (htot & 0xffff) + 1; |
10715 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
10716 | mode->hsync_start = (hsync & 0xffff) + 1; | |
10717 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
10718 | mode->vdisplay = (vtot & 0xffff) + 1; | |
10719 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
10720 | mode->vsync_start = (vsync & 0xffff) + 1; | |
10721 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
10722 | ||
10723 | drm_mode_set_name(mode); | |
79e53945 JB |
10724 | |
10725 | return mode; | |
10726 | } | |
10727 | ||
f047e395 CW |
10728 | void intel_mark_busy(struct drm_device *dev) |
10729 | { | |
c67a470b PZ |
10730 | struct drm_i915_private *dev_priv = dev->dev_private; |
10731 | ||
f62a0076 CW |
10732 | if (dev_priv->mm.busy) |
10733 | return; | |
10734 | ||
43694d69 | 10735 | intel_runtime_pm_get(dev_priv); |
c67a470b | 10736 | i915_update_gfx_val(dev_priv); |
43cf3bf0 CW |
10737 | if (INTEL_INFO(dev)->gen >= 6) |
10738 | gen6_rps_busy(dev_priv); | |
f62a0076 | 10739 | dev_priv->mm.busy = true; |
f047e395 CW |
10740 | } |
10741 | ||
10742 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 10743 | { |
c67a470b | 10744 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 10745 | |
f62a0076 CW |
10746 | if (!dev_priv->mm.busy) |
10747 | return; | |
10748 | ||
10749 | dev_priv->mm.busy = false; | |
10750 | ||
3d13ef2e | 10751 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 10752 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 | 10753 | |
43694d69 | 10754 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
10755 | } |
10756 | ||
79e53945 JB |
10757 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
10758 | { | |
10759 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
10760 | struct drm_device *dev = crtc->dev; |
10761 | struct intel_unpin_work *work; | |
67e77c5a | 10762 | |
5e2d7afc | 10763 | spin_lock_irq(&dev->event_lock); |
67e77c5a DV |
10764 | work = intel_crtc->unpin_work; |
10765 | intel_crtc->unpin_work = NULL; | |
5e2d7afc | 10766 | spin_unlock_irq(&dev->event_lock); |
67e77c5a DV |
10767 | |
10768 | if (work) { | |
10769 | cancel_work_sync(&work->work); | |
10770 | kfree(work); | |
10771 | } | |
79e53945 JB |
10772 | |
10773 | drm_crtc_cleanup(crtc); | |
67e77c5a | 10774 | |
79e53945 JB |
10775 | kfree(intel_crtc); |
10776 | } | |
10777 | ||
6b95a207 KH |
10778 | static void intel_unpin_work_fn(struct work_struct *__work) |
10779 | { | |
10780 | struct intel_unpin_work *work = | |
10781 | container_of(__work, struct intel_unpin_work, work); | |
a9ff8714 VS |
10782 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); |
10783 | struct drm_device *dev = crtc->base.dev; | |
10784 | struct drm_plane *primary = crtc->base.primary; | |
6b95a207 | 10785 | |
b4a98e57 | 10786 | mutex_lock(&dev->struct_mutex); |
a9ff8714 | 10787 | intel_unpin_fb_obj(work->old_fb, primary->state); |
05394f39 | 10788 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
d9e86c0e | 10789 | |
f06cc1b9 | 10790 | if (work->flip_queued_req) |
146d84f0 | 10791 | i915_gem_request_assign(&work->flip_queued_req, NULL); |
b4a98e57 CW |
10792 | mutex_unlock(&dev->struct_mutex); |
10793 | ||
a9ff8714 | 10794 | intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit); |
89ed88ba | 10795 | drm_framebuffer_unreference(work->old_fb); |
f99d7069 | 10796 | |
a9ff8714 VS |
10797 | BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); |
10798 | atomic_dec(&crtc->unpin_work_count); | |
b4a98e57 | 10799 | |
6b95a207 KH |
10800 | kfree(work); |
10801 | } | |
10802 | ||
1afe3e9d | 10803 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 10804 | struct drm_crtc *crtc) |
6b95a207 | 10805 | { |
6b95a207 KH |
10806 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10807 | struct intel_unpin_work *work; | |
6b95a207 KH |
10808 | unsigned long flags; |
10809 | ||
10810 | /* Ignore early vblank irqs */ | |
10811 | if (intel_crtc == NULL) | |
10812 | return; | |
10813 | ||
f326038a DV |
10814 | /* |
10815 | * This is called both by irq handlers and the reset code (to complete | |
10816 | * lost pageflips) so needs the full irqsave spinlocks. | |
10817 | */ | |
6b95a207 KH |
10818 | spin_lock_irqsave(&dev->event_lock, flags); |
10819 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
10820 | |
10821 | /* Ensure we don't miss a work->pending update ... */ | |
10822 | smp_rmb(); | |
10823 | ||
10824 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
10825 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10826 | return; | |
10827 | } | |
10828 | ||
d6bbafa1 | 10829 | page_flip_completed(intel_crtc); |
0af7e4df | 10830 | |
6b95a207 | 10831 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6b95a207 KH |
10832 | } |
10833 | ||
1afe3e9d JB |
10834 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
10835 | { | |
fbee40df | 10836 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10837 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
10838 | ||
49b14a5c | 10839 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10840 | } |
10841 | ||
10842 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
10843 | { | |
fbee40df | 10844 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10845 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
10846 | ||
49b14a5c | 10847 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10848 | } |
10849 | ||
75f7f3ec VS |
10850 | /* Is 'a' after or equal to 'b'? */ |
10851 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
10852 | { | |
10853 | return !((a - b) & 0x80000000); | |
10854 | } | |
10855 | ||
10856 | static bool page_flip_finished(struct intel_crtc *crtc) | |
10857 | { | |
10858 | struct drm_device *dev = crtc->base.dev; | |
10859 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10860 | ||
bdfa7542 VS |
10861 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
10862 | crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
10863 | return true; | |
10864 | ||
75f7f3ec VS |
10865 | /* |
10866 | * The relevant registers doen't exist on pre-ctg. | |
10867 | * As the flip done interrupt doesn't trigger for mmio | |
10868 | * flips on gmch platforms, a flip count check isn't | |
10869 | * really needed there. But since ctg has the registers, | |
10870 | * include it in the check anyway. | |
10871 | */ | |
10872 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
10873 | return true; | |
10874 | ||
10875 | /* | |
10876 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
10877 | * used the same base address. In that case the mmio flip might | |
10878 | * have completed, but the CS hasn't even executed the flip yet. | |
10879 | * | |
10880 | * A flip count check isn't enough as the CS might have updated | |
10881 | * the base address just after start of vblank, but before we | |
10882 | * managed to process the interrupt. This means we'd complete the | |
10883 | * CS flip too soon. | |
10884 | * | |
10885 | * Combining both checks should get us a good enough result. It may | |
10886 | * still happen that the CS flip has been executed, but has not | |
10887 | * yet actually completed. But in case the base address is the same | |
10888 | * anyway, we don't really care. | |
10889 | */ | |
10890 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
10891 | crtc->unpin_work->gtt_offset && | |
fd8f507c | 10892 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), |
75f7f3ec VS |
10893 | crtc->unpin_work->flip_count); |
10894 | } | |
10895 | ||
6b95a207 KH |
10896 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
10897 | { | |
fbee40df | 10898 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
10899 | struct intel_crtc *intel_crtc = |
10900 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
10901 | unsigned long flags; | |
10902 | ||
f326038a DV |
10903 | |
10904 | /* | |
10905 | * This is called both by irq handlers and the reset code (to complete | |
10906 | * lost pageflips) so needs the full irqsave spinlocks. | |
10907 | * | |
10908 | * NB: An MMIO update of the plane base pointer will also | |
e7d841ca CW |
10909 | * generate a page-flip completion irq, i.e. every modeset |
10910 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
10911 | */ | |
6b95a207 | 10912 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 10913 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 10914 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
10915 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10916 | } | |
10917 | ||
6042639c | 10918 | static inline void intel_mark_page_flip_active(struct intel_unpin_work *work) |
e7d841ca CW |
10919 | { |
10920 | /* Ensure that the work item is consistent when activating it ... */ | |
10921 | smp_wmb(); | |
6042639c | 10922 | atomic_set(&work->pending, INTEL_FLIP_PENDING); |
e7d841ca CW |
10923 | /* and that it is marked active as soon as the irq could fire. */ |
10924 | smp_wmb(); | |
10925 | } | |
10926 | ||
8c9f3aaf JB |
10927 | static int intel_gen2_queue_flip(struct drm_device *dev, |
10928 | struct drm_crtc *crtc, | |
10929 | struct drm_framebuffer *fb, | |
ed8d1975 | 10930 | struct drm_i915_gem_object *obj, |
6258fbe2 | 10931 | struct drm_i915_gem_request *req, |
ed8d1975 | 10932 | uint32_t flags) |
8c9f3aaf | 10933 | { |
6258fbe2 | 10934 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf | 10935 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
10936 | u32 flip_mask; |
10937 | int ret; | |
10938 | ||
5fb9de1a | 10939 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 10940 | if (ret) |
4fa62c89 | 10941 | return ret; |
8c9f3aaf JB |
10942 | |
10943 | /* Can't queue multiple flips, so wait for the previous | |
10944 | * one to finish before executing the next. | |
10945 | */ | |
10946 | if (intel_crtc->plane) | |
10947 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
10948 | else | |
10949 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
10950 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
10951 | intel_ring_emit(ring, MI_NOOP); | |
10952 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
10953 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10954 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 10955 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 | 10956 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca | 10957 | |
6042639c | 10958 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 10959 | return 0; |
8c9f3aaf JB |
10960 | } |
10961 | ||
10962 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
10963 | struct drm_crtc *crtc, | |
10964 | struct drm_framebuffer *fb, | |
ed8d1975 | 10965 | struct drm_i915_gem_object *obj, |
6258fbe2 | 10966 | struct drm_i915_gem_request *req, |
ed8d1975 | 10967 | uint32_t flags) |
8c9f3aaf | 10968 | { |
6258fbe2 | 10969 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf | 10970 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
10971 | u32 flip_mask; |
10972 | int ret; | |
10973 | ||
5fb9de1a | 10974 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 10975 | if (ret) |
4fa62c89 | 10976 | return ret; |
8c9f3aaf JB |
10977 | |
10978 | if (intel_crtc->plane) | |
10979 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
10980 | else | |
10981 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
10982 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
10983 | intel_ring_emit(ring, MI_NOOP); | |
10984 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
10985 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10986 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 10987 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 DV |
10988 | intel_ring_emit(ring, MI_NOOP); |
10989 | ||
6042639c | 10990 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 10991 | return 0; |
8c9f3aaf JB |
10992 | } |
10993 | ||
10994 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
10995 | struct drm_crtc *crtc, | |
10996 | struct drm_framebuffer *fb, | |
ed8d1975 | 10997 | struct drm_i915_gem_object *obj, |
6258fbe2 | 10998 | struct drm_i915_gem_request *req, |
ed8d1975 | 10999 | uint32_t flags) |
8c9f3aaf | 11000 | { |
6258fbe2 | 11001 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf JB |
11002 | struct drm_i915_private *dev_priv = dev->dev_private; |
11003 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11004 | uint32_t pf, pipesrc; | |
11005 | int ret; | |
11006 | ||
5fb9de1a | 11007 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 11008 | if (ret) |
4fa62c89 | 11009 | return ret; |
8c9f3aaf JB |
11010 | |
11011 | /* i965+ uses the linear or tiled offsets from the | |
11012 | * Display Registers (which do not change across a page-flip) | |
11013 | * so we need only reprogram the base address. | |
11014 | */ | |
6d90c952 DV |
11015 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
11016 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11017 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 11018 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
c2c75131 | 11019 | obj->tiling_mode); |
8c9f3aaf JB |
11020 | |
11021 | /* XXX Enabling the panel-fitter across page-flip is so far | |
11022 | * untested on non-native modes, so ignore it for now. | |
11023 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
11024 | */ | |
11025 | pf = 0; | |
11026 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 11027 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca | 11028 | |
6042639c | 11029 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11030 | return 0; |
8c9f3aaf JB |
11031 | } |
11032 | ||
11033 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
11034 | struct drm_crtc *crtc, | |
11035 | struct drm_framebuffer *fb, | |
ed8d1975 | 11036 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11037 | struct drm_i915_gem_request *req, |
ed8d1975 | 11038 | uint32_t flags) |
8c9f3aaf | 11039 | { |
6258fbe2 | 11040 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf JB |
11041 | struct drm_i915_private *dev_priv = dev->dev_private; |
11042 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11043 | uint32_t pf, pipesrc; | |
11044 | int ret; | |
11045 | ||
5fb9de1a | 11046 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 11047 | if (ret) |
4fa62c89 | 11048 | return ret; |
8c9f3aaf | 11049 | |
6d90c952 DV |
11050 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
11051 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11052 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
75f7f3ec | 11053 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8c9f3aaf | 11054 | |
dc257cf1 DV |
11055 | /* Contrary to the suggestions in the documentation, |
11056 | * "Enable Panel Fitter" does not seem to be required when page | |
11057 | * flipping with a non-native mode, and worse causes a normal | |
11058 | * modeset to fail. | |
11059 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
11060 | */ | |
11061 | pf = 0; | |
8c9f3aaf | 11062 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 11063 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca | 11064 | |
6042639c | 11065 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11066 | return 0; |
8c9f3aaf JB |
11067 | } |
11068 | ||
7c9017e5 JB |
11069 | static int intel_gen7_queue_flip(struct drm_device *dev, |
11070 | struct drm_crtc *crtc, | |
11071 | struct drm_framebuffer *fb, | |
ed8d1975 | 11072 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11073 | struct drm_i915_gem_request *req, |
ed8d1975 | 11074 | uint32_t flags) |
7c9017e5 | 11075 | { |
6258fbe2 | 11076 | struct intel_engine_cs *ring = req->ring; |
7c9017e5 | 11077 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 11078 | uint32_t plane_bit = 0; |
ffe74d75 CW |
11079 | int len, ret; |
11080 | ||
eba905b2 | 11081 | switch (intel_crtc->plane) { |
cb05d8de DV |
11082 | case PLANE_A: |
11083 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
11084 | break; | |
11085 | case PLANE_B: | |
11086 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
11087 | break; | |
11088 | case PLANE_C: | |
11089 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
11090 | break; | |
11091 | default: | |
11092 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 11093 | return -ENODEV; |
cb05d8de DV |
11094 | } |
11095 | ||
ffe74d75 | 11096 | len = 4; |
f476828a | 11097 | if (ring->id == RCS) { |
ffe74d75 | 11098 | len += 6; |
f476828a DL |
11099 | /* |
11100 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
11101 | * 48bits addresses, and we need a NOOP for the batch size to | |
11102 | * stay even. | |
11103 | */ | |
11104 | if (IS_GEN8(dev)) | |
11105 | len += 2; | |
11106 | } | |
ffe74d75 | 11107 | |
f66fab8e VS |
11108 | /* |
11109 | * BSpec MI_DISPLAY_FLIP for IVB: | |
11110 | * "The full packet must be contained within the same cache line." | |
11111 | * | |
11112 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
11113 | * cacheline, if we ever start emitting more commands before | |
11114 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
11115 | * then do the cacheline alignment, and finally emit the | |
11116 | * MI_DISPLAY_FLIP. | |
11117 | */ | |
bba09b12 | 11118 | ret = intel_ring_cacheline_align(req); |
f66fab8e | 11119 | if (ret) |
4fa62c89 | 11120 | return ret; |
f66fab8e | 11121 | |
5fb9de1a | 11122 | ret = intel_ring_begin(req, len); |
7c9017e5 | 11123 | if (ret) |
4fa62c89 | 11124 | return ret; |
7c9017e5 | 11125 | |
ffe74d75 CW |
11126 | /* Unmask the flip-done completion message. Note that the bspec says that |
11127 | * we should do this for both the BCS and RCS, and that we must not unmask | |
11128 | * more than one flip event at any time (or ensure that one flip message | |
11129 | * can be sent by waiting for flip-done prior to queueing new flips). | |
11130 | * Experimentation says that BCS works despite DERRMR masking all | |
11131 | * flip-done completion events and that unmasking all planes at once | |
11132 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
11133 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
11134 | */ | |
11135 | if (ring->id == RCS) { | |
11136 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
f92a9162 | 11137 | intel_ring_emit_reg(ring, DERRMR); |
ffe74d75 CW |
11138 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | |
11139 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
11140 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a | 11141 | if (IS_GEN8(dev)) |
f1afe24f | 11142 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 | |
f476828a DL |
11143 | MI_SRM_LRM_GLOBAL_GTT); |
11144 | else | |
f1afe24f | 11145 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM | |
f476828a | 11146 | MI_SRM_LRM_GLOBAL_GTT); |
f92a9162 | 11147 | intel_ring_emit_reg(ring, DERRMR); |
ffe74d75 | 11148 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); |
f476828a DL |
11149 | if (IS_GEN8(dev)) { |
11150 | intel_ring_emit(ring, 0); | |
11151 | intel_ring_emit(ring, MI_NOOP); | |
11152 | } | |
ffe74d75 CW |
11153 | } |
11154 | ||
cb05d8de | 11155 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 11156 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
75f7f3ec | 11157 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
7c9017e5 | 11158 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca | 11159 | |
6042639c | 11160 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11161 | return 0; |
7c9017e5 JB |
11162 | } |
11163 | ||
84c33a64 SG |
11164 | static bool use_mmio_flip(struct intel_engine_cs *ring, |
11165 | struct drm_i915_gem_object *obj) | |
11166 | { | |
11167 | /* | |
11168 | * This is not being used for older platforms, because | |
11169 | * non-availability of flip done interrupt forces us to use | |
11170 | * CS flips. Older platforms derive flip done using some clever | |
11171 | * tricks involving the flip_pending status bits and vblank irqs. | |
11172 | * So using MMIO flips there would disrupt this mechanism. | |
11173 | */ | |
11174 | ||
8e09bf83 CW |
11175 | if (ring == NULL) |
11176 | return true; | |
11177 | ||
84c33a64 SG |
11178 | if (INTEL_INFO(ring->dev)->gen < 5) |
11179 | return false; | |
11180 | ||
11181 | if (i915.use_mmio_flip < 0) | |
11182 | return false; | |
11183 | else if (i915.use_mmio_flip > 0) | |
11184 | return true; | |
14bf993e OM |
11185 | else if (i915.enable_execlists) |
11186 | return true; | |
84c33a64 | 11187 | else |
b4716185 | 11188 | return ring != i915_gem_request_get_ring(obj->last_write_req); |
84c33a64 SG |
11189 | } |
11190 | ||
6042639c | 11191 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, |
86efe24a | 11192 | unsigned int rotation, |
6042639c | 11193 | struct intel_unpin_work *work) |
ff944564 DL |
11194 | { |
11195 | struct drm_device *dev = intel_crtc->base.dev; | |
11196 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11197 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; | |
ff944564 | 11198 | const enum pipe pipe = intel_crtc->pipe; |
86efe24a | 11199 | u32 ctl, stride, tile_height; |
ff944564 DL |
11200 | |
11201 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
11202 | ctl &= ~PLANE_CTL_TILED_MASK; | |
2ebef630 TU |
11203 | switch (fb->modifier[0]) { |
11204 | case DRM_FORMAT_MOD_NONE: | |
11205 | break; | |
11206 | case I915_FORMAT_MOD_X_TILED: | |
ff944564 | 11207 | ctl |= PLANE_CTL_TILED_X; |
2ebef630 TU |
11208 | break; |
11209 | case I915_FORMAT_MOD_Y_TILED: | |
11210 | ctl |= PLANE_CTL_TILED_Y; | |
11211 | break; | |
11212 | case I915_FORMAT_MOD_Yf_TILED: | |
11213 | ctl |= PLANE_CTL_TILED_YF; | |
11214 | break; | |
11215 | default: | |
11216 | MISSING_CASE(fb->modifier[0]); | |
11217 | } | |
ff944564 DL |
11218 | |
11219 | /* | |
11220 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
11221 | * linear buffers or in number of tiles for tiled buffers. | |
11222 | */ | |
86efe24a TU |
11223 | if (intel_rotation_90_or_270(rotation)) { |
11224 | /* stride = Surface height in tiles */ | |
11225 | tile_height = intel_tile_height(dev, fb->pixel_format, | |
11226 | fb->modifier[0], 0); | |
11227 | stride = DIV_ROUND_UP(fb->height, tile_height); | |
11228 | } else { | |
11229 | stride = fb->pitches[0] / | |
11230 | intel_fb_stride_alignment(dev, fb->modifier[0], | |
11231 | fb->pixel_format); | |
11232 | } | |
ff944564 DL |
11233 | |
11234 | /* | |
11235 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
11236 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
11237 | */ | |
11238 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
11239 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
11240 | ||
6042639c | 11241 | I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); |
ff944564 DL |
11242 | POSTING_READ(PLANE_SURF(pipe, 0)); |
11243 | } | |
11244 | ||
6042639c CW |
11245 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, |
11246 | struct intel_unpin_work *work) | |
84c33a64 SG |
11247 | { |
11248 | struct drm_device *dev = intel_crtc->base.dev; | |
11249 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11250 | struct intel_framebuffer *intel_fb = | |
11251 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
11252 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
f0f59a00 | 11253 | i915_reg_t reg = DSPCNTR(intel_crtc->plane); |
84c33a64 | 11254 | u32 dspcntr; |
84c33a64 | 11255 | |
84c33a64 SG |
11256 | dspcntr = I915_READ(reg); |
11257 | ||
c5d97472 DL |
11258 | if (obj->tiling_mode != I915_TILING_NONE) |
11259 | dspcntr |= DISPPLANE_TILED; | |
11260 | else | |
11261 | dspcntr &= ~DISPPLANE_TILED; | |
11262 | ||
84c33a64 SG |
11263 | I915_WRITE(reg, dspcntr); |
11264 | ||
6042639c | 11265 | I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); |
84c33a64 | 11266 | POSTING_READ(DSPSURF(intel_crtc->plane)); |
ff944564 DL |
11267 | } |
11268 | ||
11269 | /* | |
11270 | * XXX: This is the temporary way to update the plane registers until we get | |
11271 | * around to using the usual plane update functions for MMIO flips | |
11272 | */ | |
6042639c | 11273 | static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip) |
ff944564 | 11274 | { |
6042639c CW |
11275 | struct intel_crtc *crtc = mmio_flip->crtc; |
11276 | struct intel_unpin_work *work; | |
11277 | ||
11278 | spin_lock_irq(&crtc->base.dev->event_lock); | |
11279 | work = crtc->unpin_work; | |
11280 | spin_unlock_irq(&crtc->base.dev->event_lock); | |
11281 | if (work == NULL) | |
11282 | return; | |
ff944564 | 11283 | |
6042639c | 11284 | intel_mark_page_flip_active(work); |
ff944564 | 11285 | |
6042639c | 11286 | intel_pipe_update_start(crtc); |
ff944564 | 11287 | |
6042639c | 11288 | if (INTEL_INFO(mmio_flip->i915)->gen >= 9) |
86efe24a | 11289 | skl_do_mmio_flip(crtc, mmio_flip->rotation, work); |
ff944564 DL |
11290 | else |
11291 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
6042639c | 11292 | ilk_do_mmio_flip(crtc, work); |
ff944564 | 11293 | |
6042639c | 11294 | intel_pipe_update_end(crtc); |
84c33a64 SG |
11295 | } |
11296 | ||
9362c7c5 | 11297 | static void intel_mmio_flip_work_func(struct work_struct *work) |
84c33a64 | 11298 | { |
b2cfe0ab CW |
11299 | struct intel_mmio_flip *mmio_flip = |
11300 | container_of(work, struct intel_mmio_flip, work); | |
84c33a64 | 11301 | |
6042639c | 11302 | if (mmio_flip->req) { |
eed29a5b | 11303 | WARN_ON(__i915_wait_request(mmio_flip->req, |
b2cfe0ab | 11304 | mmio_flip->crtc->reset_counter, |
bcafc4e3 CW |
11305 | false, NULL, |
11306 | &mmio_flip->i915->rps.mmioflips)); | |
6042639c CW |
11307 | i915_gem_request_unreference__unlocked(mmio_flip->req); |
11308 | } | |
84c33a64 | 11309 | |
6042639c | 11310 | intel_do_mmio_flip(mmio_flip); |
b2cfe0ab | 11311 | kfree(mmio_flip); |
84c33a64 SG |
11312 | } |
11313 | ||
11314 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
11315 | struct drm_crtc *crtc, | |
86efe24a | 11316 | struct drm_i915_gem_object *obj) |
84c33a64 | 11317 | { |
b2cfe0ab CW |
11318 | struct intel_mmio_flip *mmio_flip; |
11319 | ||
11320 | mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL); | |
11321 | if (mmio_flip == NULL) | |
11322 | return -ENOMEM; | |
84c33a64 | 11323 | |
bcafc4e3 | 11324 | mmio_flip->i915 = to_i915(dev); |
eed29a5b | 11325 | mmio_flip->req = i915_gem_request_reference(obj->last_write_req); |
b2cfe0ab | 11326 | mmio_flip->crtc = to_intel_crtc(crtc); |
86efe24a | 11327 | mmio_flip->rotation = crtc->primary->state->rotation; |
536f5b5e | 11328 | |
b2cfe0ab CW |
11329 | INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func); |
11330 | schedule_work(&mmio_flip->work); | |
84c33a64 | 11331 | |
84c33a64 SG |
11332 | return 0; |
11333 | } | |
11334 | ||
8c9f3aaf JB |
11335 | static int intel_default_queue_flip(struct drm_device *dev, |
11336 | struct drm_crtc *crtc, | |
11337 | struct drm_framebuffer *fb, | |
ed8d1975 | 11338 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11339 | struct drm_i915_gem_request *req, |
ed8d1975 | 11340 | uint32_t flags) |
8c9f3aaf JB |
11341 | { |
11342 | return -ENODEV; | |
11343 | } | |
11344 | ||
d6bbafa1 CW |
11345 | static bool __intel_pageflip_stall_check(struct drm_device *dev, |
11346 | struct drm_crtc *crtc) | |
11347 | { | |
11348 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11349 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11350 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
11351 | u32 addr; | |
11352 | ||
11353 | if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) | |
11354 | return true; | |
11355 | ||
908565c2 CW |
11356 | if (atomic_read(&work->pending) < INTEL_FLIP_PENDING) |
11357 | return false; | |
11358 | ||
d6bbafa1 CW |
11359 | if (!work->enable_stall_check) |
11360 | return false; | |
11361 | ||
11362 | if (work->flip_ready_vblank == 0) { | |
3a8a946e DV |
11363 | if (work->flip_queued_req && |
11364 | !i915_gem_request_completed(work->flip_queued_req, true)) | |
d6bbafa1 CW |
11365 | return false; |
11366 | ||
1e3feefd | 11367 | work->flip_ready_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 CW |
11368 | } |
11369 | ||
1e3feefd | 11370 | if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) |
d6bbafa1 CW |
11371 | return false; |
11372 | ||
11373 | /* Potential stall - if we see that the flip has happened, | |
11374 | * assume a missed interrupt. */ | |
11375 | if (INTEL_INFO(dev)->gen >= 4) | |
11376 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
11377 | else | |
11378 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
11379 | ||
11380 | /* There is a potential issue here with a false positive after a flip | |
11381 | * to the same address. We could address this by checking for a | |
11382 | * non-incrementing frame counter. | |
11383 | */ | |
11384 | return addr == work->gtt_offset; | |
11385 | } | |
11386 | ||
11387 | void intel_check_page_flip(struct drm_device *dev, int pipe) | |
11388 | { | |
11389 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11390 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
11391 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6ad790c0 | 11392 | struct intel_unpin_work *work; |
f326038a | 11393 | |
6c51d46f | 11394 | WARN_ON(!in_interrupt()); |
d6bbafa1 CW |
11395 | |
11396 | if (crtc == NULL) | |
11397 | return; | |
11398 | ||
f326038a | 11399 | spin_lock(&dev->event_lock); |
6ad790c0 CW |
11400 | work = intel_crtc->unpin_work; |
11401 | if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) { | |
d6bbafa1 | 11402 | WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", |
6ad790c0 | 11403 | work->flip_queued_vblank, drm_vblank_count(dev, pipe)); |
d6bbafa1 | 11404 | page_flip_completed(intel_crtc); |
6ad790c0 | 11405 | work = NULL; |
d6bbafa1 | 11406 | } |
6ad790c0 CW |
11407 | if (work != NULL && |
11408 | drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1) | |
11409 | intel_queue_rps_boost_for_request(dev, work->flip_queued_req); | |
f326038a | 11410 | spin_unlock(&dev->event_lock); |
d6bbafa1 CW |
11411 | } |
11412 | ||
6b95a207 KH |
11413 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
11414 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
11415 | struct drm_pending_vblank_event *event, |
11416 | uint32_t page_flip_flags) | |
6b95a207 KH |
11417 | { |
11418 | struct drm_device *dev = crtc->dev; | |
11419 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 11420 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 11421 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 | 11422 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
455a6808 | 11423 | struct drm_plane *primary = crtc->primary; |
a071fa00 | 11424 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 11425 | struct intel_unpin_work *work; |
a4872ba6 | 11426 | struct intel_engine_cs *ring; |
cf5d8a46 | 11427 | bool mmio_flip; |
91af127f | 11428 | struct drm_i915_gem_request *request = NULL; |
52e68630 | 11429 | int ret; |
6b95a207 | 11430 | |
2ff8fde1 MR |
11431 | /* |
11432 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
11433 | * check to be safe. In the future we may enable pageflipping from | |
11434 | * a disabled primary plane. | |
11435 | */ | |
11436 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
11437 | return -EBUSY; | |
11438 | ||
e6a595d2 | 11439 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 11440 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
11441 | return -EINVAL; |
11442 | ||
11443 | /* | |
11444 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
11445 | * Note that pitch changes could also affect these register. | |
11446 | */ | |
11447 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
11448 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
11449 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
11450 | return -EINVAL; |
11451 | ||
f900db47 CW |
11452 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
11453 | goto out_hang; | |
11454 | ||
b14c5679 | 11455 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
11456 | if (work == NULL) |
11457 | return -ENOMEM; | |
11458 | ||
6b95a207 | 11459 | work->event = event; |
b4a98e57 | 11460 | work->crtc = crtc; |
ab8d6675 | 11461 | work->old_fb = old_fb; |
6b95a207 KH |
11462 | INIT_WORK(&work->work, intel_unpin_work_fn); |
11463 | ||
87b6b101 | 11464 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
11465 | if (ret) |
11466 | goto free_work; | |
11467 | ||
6b95a207 | 11468 | /* We borrow the event spin lock for protecting unpin_work */ |
5e2d7afc | 11469 | spin_lock_irq(&dev->event_lock); |
6b95a207 | 11470 | if (intel_crtc->unpin_work) { |
d6bbafa1 CW |
11471 | /* Before declaring the flip queue wedged, check if |
11472 | * the hardware completed the operation behind our backs. | |
11473 | */ | |
11474 | if (__intel_pageflip_stall_check(dev, crtc)) { | |
11475 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
11476 | page_flip_completed(intel_crtc); | |
11477 | } else { | |
11478 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
5e2d7afc | 11479 | spin_unlock_irq(&dev->event_lock); |
468f0b44 | 11480 | |
d6bbafa1 CW |
11481 | drm_crtc_vblank_put(crtc); |
11482 | kfree(work); | |
11483 | return -EBUSY; | |
11484 | } | |
6b95a207 KH |
11485 | } |
11486 | intel_crtc->unpin_work = work; | |
5e2d7afc | 11487 | spin_unlock_irq(&dev->event_lock); |
6b95a207 | 11488 | |
b4a98e57 CW |
11489 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
11490 | flush_workqueue(dev_priv->wq); | |
11491 | ||
75dfca80 | 11492 | /* Reference the objects for the scheduled work. */ |
ab8d6675 | 11493 | drm_framebuffer_reference(work->old_fb); |
05394f39 | 11494 | drm_gem_object_reference(&obj->base); |
6b95a207 | 11495 | |
f4510a27 | 11496 | crtc->primary->fb = fb; |
afd65eb4 | 11497 | update_state_fb(crtc->primary); |
1ed1f968 | 11498 | |
e1f99ce6 | 11499 | work->pending_flip_obj = obj; |
e1f99ce6 | 11500 | |
89ed88ba CW |
11501 | ret = i915_mutex_lock_interruptible(dev); |
11502 | if (ret) | |
11503 | goto cleanup; | |
11504 | ||
b4a98e57 | 11505 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 11506 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 11507 | |
75f7f3ec | 11508 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
fd8f507c | 11509 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; |
75f7f3ec | 11510 | |
4fa62c89 VS |
11511 | if (IS_VALLEYVIEW(dev)) { |
11512 | ring = &dev_priv->ring[BCS]; | |
ab8d6675 | 11513 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) |
8e09bf83 CW |
11514 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
11515 | ring = NULL; | |
48bf5b2d | 11516 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
2a92d5bc | 11517 | ring = &dev_priv->ring[BCS]; |
4fa62c89 | 11518 | } else if (INTEL_INFO(dev)->gen >= 7) { |
b4716185 | 11519 | ring = i915_gem_request_get_ring(obj->last_write_req); |
4fa62c89 VS |
11520 | if (ring == NULL || ring->id != RCS) |
11521 | ring = &dev_priv->ring[BCS]; | |
11522 | } else { | |
11523 | ring = &dev_priv->ring[RCS]; | |
11524 | } | |
11525 | ||
cf5d8a46 CW |
11526 | mmio_flip = use_mmio_flip(ring, obj); |
11527 | ||
11528 | /* When using CS flips, we want to emit semaphores between rings. | |
11529 | * However, when using mmio flips we will create a task to do the | |
11530 | * synchronisation, so all we want here is to pin the framebuffer | |
11531 | * into the display plane and skip any waits. | |
11532 | */ | |
7580d774 ML |
11533 | if (!mmio_flip) { |
11534 | ret = i915_gem_object_sync(obj, ring, &request); | |
11535 | if (ret) | |
11536 | goto cleanup_pending; | |
11537 | } | |
11538 | ||
82bc3b2d | 11539 | ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, |
7580d774 | 11540 | crtc->primary->state); |
8c9f3aaf JB |
11541 | if (ret) |
11542 | goto cleanup_pending; | |
6b95a207 | 11543 | |
dedf278c TU |
11544 | work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), |
11545 | obj, 0); | |
11546 | work->gtt_offset += intel_crtc->dspaddr_offset; | |
4fa62c89 | 11547 | |
cf5d8a46 | 11548 | if (mmio_flip) { |
86efe24a | 11549 | ret = intel_queue_mmio_flip(dev, crtc, obj); |
d6bbafa1 CW |
11550 | if (ret) |
11551 | goto cleanup_unpin; | |
11552 | ||
f06cc1b9 JH |
11553 | i915_gem_request_assign(&work->flip_queued_req, |
11554 | obj->last_write_req); | |
d6bbafa1 | 11555 | } else { |
6258fbe2 JH |
11556 | if (!request) { |
11557 | ret = i915_gem_request_alloc(ring, ring->default_context, &request); | |
11558 | if (ret) | |
11559 | goto cleanup_unpin; | |
11560 | } | |
11561 | ||
11562 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, | |
d6bbafa1 CW |
11563 | page_flip_flags); |
11564 | if (ret) | |
11565 | goto cleanup_unpin; | |
11566 | ||
6258fbe2 | 11567 | i915_gem_request_assign(&work->flip_queued_req, request); |
d6bbafa1 CW |
11568 | } |
11569 | ||
91af127f | 11570 | if (request) |
75289874 | 11571 | i915_add_request_no_flush(request); |
91af127f | 11572 | |
1e3feefd | 11573 | work->flip_queued_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 | 11574 | work->enable_stall_check = true; |
4fa62c89 | 11575 | |
ab8d6675 | 11576 | i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, |
a9ff8714 | 11577 | to_intel_plane(primary)->frontbuffer_bit); |
c80ac854 | 11578 | mutex_unlock(&dev->struct_mutex); |
a071fa00 | 11579 | |
4e1e26f1 | 11580 | intel_fbc_disable_crtc(intel_crtc); |
a9ff8714 VS |
11581 | intel_frontbuffer_flip_prepare(dev, |
11582 | to_intel_plane(primary)->frontbuffer_bit); | |
6b95a207 | 11583 | |
e5510fac JB |
11584 | trace_i915_flip_request(intel_crtc->plane, obj); |
11585 | ||
6b95a207 | 11586 | return 0; |
96b099fd | 11587 | |
4fa62c89 | 11588 | cleanup_unpin: |
82bc3b2d | 11589 | intel_unpin_fb_obj(fb, crtc->primary->state); |
8c9f3aaf | 11590 | cleanup_pending: |
91af127f JH |
11591 | if (request) |
11592 | i915_gem_request_cancel(request); | |
b4a98e57 | 11593 | atomic_dec(&intel_crtc->unpin_work_count); |
89ed88ba CW |
11594 | mutex_unlock(&dev->struct_mutex); |
11595 | cleanup: | |
f4510a27 | 11596 | crtc->primary->fb = old_fb; |
afd65eb4 | 11597 | update_state_fb(crtc->primary); |
89ed88ba CW |
11598 | |
11599 | drm_gem_object_unreference_unlocked(&obj->base); | |
ab8d6675 | 11600 | drm_framebuffer_unreference(work->old_fb); |
96b099fd | 11601 | |
5e2d7afc | 11602 | spin_lock_irq(&dev->event_lock); |
96b099fd | 11603 | intel_crtc->unpin_work = NULL; |
5e2d7afc | 11604 | spin_unlock_irq(&dev->event_lock); |
96b099fd | 11605 | |
87b6b101 | 11606 | drm_crtc_vblank_put(crtc); |
7317c75e | 11607 | free_work: |
96b099fd CW |
11608 | kfree(work); |
11609 | ||
f900db47 | 11610 | if (ret == -EIO) { |
02e0efb5 ML |
11611 | struct drm_atomic_state *state; |
11612 | struct drm_plane_state *plane_state; | |
11613 | ||
f900db47 | 11614 | out_hang: |
02e0efb5 ML |
11615 | state = drm_atomic_state_alloc(dev); |
11616 | if (!state) | |
11617 | return -ENOMEM; | |
11618 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); | |
11619 | ||
11620 | retry: | |
11621 | plane_state = drm_atomic_get_plane_state(state, primary); | |
11622 | ret = PTR_ERR_OR_ZERO(plane_state); | |
11623 | if (!ret) { | |
11624 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
11625 | ||
11626 | ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); | |
11627 | if (!ret) | |
11628 | ret = drm_atomic_commit(state); | |
11629 | } | |
11630 | ||
11631 | if (ret == -EDEADLK) { | |
11632 | drm_modeset_backoff(state->acquire_ctx); | |
11633 | drm_atomic_state_clear(state); | |
11634 | goto retry; | |
11635 | } | |
11636 | ||
11637 | if (ret) | |
11638 | drm_atomic_state_free(state); | |
11639 | ||
f0d3dad3 | 11640 | if (ret == 0 && event) { |
5e2d7afc | 11641 | spin_lock_irq(&dev->event_lock); |
a071fa00 | 11642 | drm_send_vblank_event(dev, pipe, event); |
5e2d7afc | 11643 | spin_unlock_irq(&dev->event_lock); |
f0d3dad3 | 11644 | } |
f900db47 | 11645 | } |
96b099fd | 11646 | return ret; |
6b95a207 KH |
11647 | } |
11648 | ||
da20eabd ML |
11649 | |
11650 | /** | |
11651 | * intel_wm_need_update - Check whether watermarks need updating | |
11652 | * @plane: drm plane | |
11653 | * @state: new plane state | |
11654 | * | |
11655 | * Check current plane state versus the new one to determine whether | |
11656 | * watermarks need to be recalculated. | |
11657 | * | |
11658 | * Returns true or false. | |
11659 | */ | |
11660 | static bool intel_wm_need_update(struct drm_plane *plane, | |
11661 | struct drm_plane_state *state) | |
11662 | { | |
d21fbe87 MR |
11663 | struct intel_plane_state *new = to_intel_plane_state(state); |
11664 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); | |
11665 | ||
11666 | /* Update watermarks on tiling or size changes. */ | |
da20eabd ML |
11667 | if (!plane->state->fb || !state->fb || |
11668 | plane->state->fb->modifier[0] != state->fb->modifier[0] || | |
d21fbe87 MR |
11669 | plane->state->rotation != state->rotation || |
11670 | drm_rect_width(&new->src) != drm_rect_width(&cur->src) || | |
11671 | drm_rect_height(&new->src) != drm_rect_height(&cur->src) || | |
11672 | drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) || | |
11673 | drm_rect_height(&new->dst) != drm_rect_height(&cur->dst)) | |
2791a16c | 11674 | return true; |
7809e5ae | 11675 | |
2791a16c | 11676 | return false; |
7809e5ae MR |
11677 | } |
11678 | ||
d21fbe87 MR |
11679 | static bool needs_scaling(struct intel_plane_state *state) |
11680 | { | |
11681 | int src_w = drm_rect_width(&state->src) >> 16; | |
11682 | int src_h = drm_rect_height(&state->src) >> 16; | |
11683 | int dst_w = drm_rect_width(&state->dst); | |
11684 | int dst_h = drm_rect_height(&state->dst); | |
11685 | ||
11686 | return (src_w != dst_w || src_h != dst_h); | |
11687 | } | |
11688 | ||
da20eabd ML |
11689 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
11690 | struct drm_plane_state *plane_state) | |
11691 | { | |
11692 | struct drm_crtc *crtc = crtc_state->crtc; | |
11693 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11694 | struct drm_plane *plane = plane_state->plane; | |
11695 | struct drm_device *dev = crtc->dev; | |
11696 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11697 | struct intel_plane_state *old_plane_state = | |
11698 | to_intel_plane_state(plane->state); | |
11699 | int idx = intel_crtc->base.base.id, ret; | |
11700 | int i = drm_plane_index(plane); | |
11701 | bool mode_changed = needs_modeset(crtc_state); | |
11702 | bool was_crtc_enabled = crtc->state->active; | |
11703 | bool is_crtc_enabled = crtc_state->active; | |
da20eabd ML |
11704 | bool turn_off, turn_on, visible, was_visible; |
11705 | struct drm_framebuffer *fb = plane_state->fb; | |
11706 | ||
11707 | if (crtc_state && INTEL_INFO(dev)->gen >= 9 && | |
11708 | plane->type != DRM_PLANE_TYPE_CURSOR) { | |
11709 | ret = skl_update_scaler_plane( | |
11710 | to_intel_crtc_state(crtc_state), | |
11711 | to_intel_plane_state(plane_state)); | |
11712 | if (ret) | |
11713 | return ret; | |
11714 | } | |
11715 | ||
da20eabd ML |
11716 | was_visible = old_plane_state->visible; |
11717 | visible = to_intel_plane_state(plane_state)->visible; | |
11718 | ||
11719 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
11720 | was_visible = false; | |
11721 | ||
11722 | if (!is_crtc_enabled && WARN_ON(visible)) | |
11723 | visible = false; | |
11724 | ||
11725 | if (!was_visible && !visible) | |
11726 | return 0; | |
11727 | ||
11728 | turn_off = was_visible && (!visible || mode_changed); | |
11729 | turn_on = visible && (!was_visible || mode_changed); | |
11730 | ||
11731 | DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx, | |
11732 | plane->base.id, fb ? fb->base.id : -1); | |
11733 | ||
11734 | DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n", | |
11735 | plane->base.id, was_visible, visible, | |
11736 | turn_off, turn_on, mode_changed); | |
11737 | ||
852eb00d | 11738 | if (turn_on) { |
f015c551 | 11739 | intel_crtc->atomic.update_wm_pre = true; |
852eb00d VS |
11740 | /* must disable cxsr around plane enable/disable */ |
11741 | if (plane->type != DRM_PLANE_TYPE_CURSOR) { | |
11742 | intel_crtc->atomic.disable_cxsr = true; | |
11743 | /* to potentially re-enable cxsr */ | |
11744 | intel_crtc->atomic.wait_vblank = true; | |
11745 | intel_crtc->atomic.update_wm_post = true; | |
11746 | } | |
11747 | } else if (turn_off) { | |
f015c551 | 11748 | intel_crtc->atomic.update_wm_post = true; |
852eb00d VS |
11749 | /* must disable cxsr around plane enable/disable */ |
11750 | if (plane->type != DRM_PLANE_TYPE_CURSOR) { | |
11751 | if (is_crtc_enabled) | |
11752 | intel_crtc->atomic.wait_vblank = true; | |
11753 | intel_crtc->atomic.disable_cxsr = true; | |
11754 | } | |
11755 | } else if (intel_wm_need_update(plane, plane_state)) { | |
f015c551 | 11756 | intel_crtc->atomic.update_wm_pre = true; |
852eb00d | 11757 | } |
da20eabd | 11758 | |
8be6ca85 | 11759 | if (visible || was_visible) |
a9ff8714 VS |
11760 | intel_crtc->atomic.fb_bits |= |
11761 | to_intel_plane(plane)->frontbuffer_bit; | |
11762 | ||
da20eabd ML |
11763 | switch (plane->type) { |
11764 | case DRM_PLANE_TYPE_PRIMARY: | |
da20eabd ML |
11765 | intel_crtc->atomic.pre_disable_primary = turn_off; |
11766 | intel_crtc->atomic.post_enable_primary = turn_on; | |
11767 | ||
066cf55b RV |
11768 | if (turn_off) { |
11769 | /* | |
11770 | * FIXME: Actually if we will still have any other | |
11771 | * plane enabled on the pipe we could let IPS enabled | |
11772 | * still, but for now lets consider that when we make | |
11773 | * primary invisible by setting DSPCNTR to 0 on | |
11774 | * update_primary_plane function IPS needs to be | |
11775 | * disable. | |
11776 | */ | |
11777 | intel_crtc->atomic.disable_ips = true; | |
11778 | ||
da20eabd | 11779 | intel_crtc->atomic.disable_fbc = true; |
066cf55b | 11780 | } |
da20eabd ML |
11781 | |
11782 | /* | |
11783 | * FBC does not work on some platforms for rotated | |
11784 | * planes, so disable it when rotation is not 0 and | |
11785 | * update it when rotation is set back to 0. | |
11786 | * | |
11787 | * FIXME: This is redundant with the fbc update done in | |
11788 | * the primary plane enable function except that that | |
11789 | * one is done too late. We eventually need to unify | |
11790 | * this. | |
11791 | */ | |
11792 | ||
11793 | if (visible && | |
11794 | INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && | |
11795 | dev_priv->fbc.crtc == intel_crtc && | |
11796 | plane_state->rotation != BIT(DRM_ROTATE_0)) | |
11797 | intel_crtc->atomic.disable_fbc = true; | |
11798 | ||
11799 | /* | |
11800 | * BDW signals flip done immediately if the plane | |
11801 | * is disabled, even if the plane enable is already | |
11802 | * armed to occur at the next vblank :( | |
11803 | */ | |
11804 | if (turn_on && IS_BROADWELL(dev)) | |
11805 | intel_crtc->atomic.wait_vblank = true; | |
11806 | ||
11807 | intel_crtc->atomic.update_fbc |= visible || mode_changed; | |
11808 | break; | |
11809 | case DRM_PLANE_TYPE_CURSOR: | |
da20eabd ML |
11810 | break; |
11811 | case DRM_PLANE_TYPE_OVERLAY: | |
d21fbe87 MR |
11812 | /* |
11813 | * WaCxSRDisabledForSpriteScaling:ivb | |
11814 | * | |
11815 | * cstate->update_wm was already set above, so this flag will | |
11816 | * take effect when we commit and program watermarks. | |
11817 | */ | |
11818 | if (IS_IVYBRIDGE(dev) && | |
11819 | needs_scaling(to_intel_plane_state(plane_state)) && | |
11820 | !needs_scaling(old_plane_state)) { | |
11821 | to_intel_crtc_state(crtc_state)->disable_lp_wm = true; | |
11822 | } else if (turn_off && !mode_changed) { | |
da20eabd ML |
11823 | intel_crtc->atomic.wait_vblank = true; |
11824 | intel_crtc->atomic.update_sprite_watermarks |= | |
11825 | 1 << i; | |
11826 | } | |
d21fbe87 MR |
11827 | |
11828 | break; | |
da20eabd ML |
11829 | } |
11830 | return 0; | |
11831 | } | |
11832 | ||
6d3a1ce7 ML |
11833 | static bool encoders_cloneable(const struct intel_encoder *a, |
11834 | const struct intel_encoder *b) | |
11835 | { | |
11836 | /* masks could be asymmetric, so check both ways */ | |
11837 | return a == b || (a->cloneable & (1 << b->type) && | |
11838 | b->cloneable & (1 << a->type)); | |
11839 | } | |
11840 | ||
11841 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
11842 | struct intel_crtc *crtc, | |
11843 | struct intel_encoder *encoder) | |
11844 | { | |
11845 | struct intel_encoder *source_encoder; | |
11846 | struct drm_connector *connector; | |
11847 | struct drm_connector_state *connector_state; | |
11848 | int i; | |
11849 | ||
11850 | for_each_connector_in_state(state, connector, connector_state, i) { | |
11851 | if (connector_state->crtc != &crtc->base) | |
11852 | continue; | |
11853 | ||
11854 | source_encoder = | |
11855 | to_intel_encoder(connector_state->best_encoder); | |
11856 | if (!encoders_cloneable(encoder, source_encoder)) | |
11857 | return false; | |
11858 | } | |
11859 | ||
11860 | return true; | |
11861 | } | |
11862 | ||
11863 | static bool check_encoder_cloning(struct drm_atomic_state *state, | |
11864 | struct intel_crtc *crtc) | |
11865 | { | |
11866 | struct intel_encoder *encoder; | |
11867 | struct drm_connector *connector; | |
11868 | struct drm_connector_state *connector_state; | |
11869 | int i; | |
11870 | ||
11871 | for_each_connector_in_state(state, connector, connector_state, i) { | |
11872 | if (connector_state->crtc != &crtc->base) | |
11873 | continue; | |
11874 | ||
11875 | encoder = to_intel_encoder(connector_state->best_encoder); | |
11876 | if (!check_single_encoder_cloning(state, crtc, encoder)) | |
11877 | return false; | |
11878 | } | |
11879 | ||
11880 | return true; | |
11881 | } | |
11882 | ||
11883 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, | |
11884 | struct drm_crtc_state *crtc_state) | |
11885 | { | |
cf5a15be | 11886 | struct drm_device *dev = crtc->dev; |
ad421372 | 11887 | struct drm_i915_private *dev_priv = dev->dev_private; |
6d3a1ce7 | 11888 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
11889 | struct intel_crtc_state *pipe_config = |
11890 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 11891 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 11892 | int ret; |
6d3a1ce7 ML |
11893 | bool mode_changed = needs_modeset(crtc_state); |
11894 | ||
11895 | if (mode_changed && !check_encoder_cloning(state, intel_crtc)) { | |
11896 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
11897 | return -EINVAL; | |
11898 | } | |
11899 | ||
852eb00d VS |
11900 | if (mode_changed && !crtc_state->active) |
11901 | intel_crtc->atomic.update_wm_post = true; | |
eddfcbcd | 11902 | |
ad421372 ML |
11903 | if (mode_changed && crtc_state->enable && |
11904 | dev_priv->display.crtc_compute_clock && | |
11905 | !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) { | |
11906 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, | |
11907 | pipe_config); | |
11908 | if (ret) | |
11909 | return ret; | |
11910 | } | |
11911 | ||
e435d6e5 | 11912 | ret = 0; |
86c8bbbe MR |
11913 | if (dev_priv->display.compute_pipe_wm) { |
11914 | ret = dev_priv->display.compute_pipe_wm(intel_crtc, state); | |
11915 | if (ret) | |
11916 | return ret; | |
11917 | } | |
11918 | ||
e435d6e5 ML |
11919 | if (INTEL_INFO(dev)->gen >= 9) { |
11920 | if (mode_changed) | |
11921 | ret = skl_update_scaler_crtc(pipe_config); | |
11922 | ||
11923 | if (!ret) | |
11924 | ret = intel_atomic_setup_scalers(dev, intel_crtc, | |
11925 | pipe_config); | |
11926 | } | |
11927 | ||
11928 | return ret; | |
6d3a1ce7 ML |
11929 | } |
11930 | ||
65b38e0d | 11931 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
11932 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
11933 | .load_lut = intel_crtc_load_lut, | |
ea2c67bb MR |
11934 | .atomic_begin = intel_begin_crtc_commit, |
11935 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 11936 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
11937 | }; |
11938 | ||
d29b2f9d ACO |
11939 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
11940 | { | |
11941 | struct intel_connector *connector; | |
11942 | ||
11943 | for_each_intel_connector(dev, connector) { | |
11944 | if (connector->base.encoder) { | |
11945 | connector->base.state->best_encoder = | |
11946 | connector->base.encoder; | |
11947 | connector->base.state->crtc = | |
11948 | connector->base.encoder->crtc; | |
11949 | } else { | |
11950 | connector->base.state->best_encoder = NULL; | |
11951 | connector->base.state->crtc = NULL; | |
11952 | } | |
11953 | } | |
11954 | } | |
11955 | ||
050f7aeb | 11956 | static void |
eba905b2 | 11957 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 11958 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
11959 | { |
11960 | int bpp = pipe_config->pipe_bpp; | |
11961 | ||
11962 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
11963 | connector->base.base.id, | |
c23cc417 | 11964 | connector->base.name); |
050f7aeb DV |
11965 | |
11966 | /* Don't use an invalid EDID bpc value */ | |
11967 | if (connector->base.display_info.bpc && | |
11968 | connector->base.display_info.bpc * 3 < bpp) { | |
11969 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
11970 | bpp, connector->base.display_info.bpc*3); | |
11971 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
11972 | } | |
11973 | ||
11974 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
11975 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
11976 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
11977 | bpp); | |
11978 | pipe_config->pipe_bpp = 24; | |
11979 | } | |
11980 | } | |
11981 | ||
4e53c2e0 | 11982 | static int |
050f7aeb | 11983 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 11984 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 11985 | { |
050f7aeb | 11986 | struct drm_device *dev = crtc->base.dev; |
1486017f | 11987 | struct drm_atomic_state *state; |
da3ced29 ACO |
11988 | struct drm_connector *connector; |
11989 | struct drm_connector_state *connector_state; | |
1486017f | 11990 | int bpp, i; |
4e53c2e0 | 11991 | |
d328c9d7 | 11992 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev))) |
4e53c2e0 | 11993 | bpp = 10*3; |
d328c9d7 DV |
11994 | else if (INTEL_INFO(dev)->gen >= 5) |
11995 | bpp = 12*3; | |
11996 | else | |
11997 | bpp = 8*3; | |
11998 | ||
4e53c2e0 | 11999 | |
4e53c2e0 DV |
12000 | pipe_config->pipe_bpp = bpp; |
12001 | ||
1486017f ACO |
12002 | state = pipe_config->base.state; |
12003 | ||
4e53c2e0 | 12004 | /* Clamp display bpp to EDID value */ |
da3ced29 ACO |
12005 | for_each_connector_in_state(state, connector, connector_state, i) { |
12006 | if (connector_state->crtc != &crtc->base) | |
4e53c2e0 DV |
12007 | continue; |
12008 | ||
da3ced29 ACO |
12009 | connected_sink_compute_bpp(to_intel_connector(connector), |
12010 | pipe_config); | |
4e53c2e0 DV |
12011 | } |
12012 | ||
12013 | return bpp; | |
12014 | } | |
12015 | ||
644db711 DV |
12016 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
12017 | { | |
12018 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
12019 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 12020 | mode->crtc_clock, |
644db711 DV |
12021 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
12022 | mode->crtc_hsync_end, mode->crtc_htotal, | |
12023 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
12024 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
12025 | } | |
12026 | ||
c0b03411 | 12027 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 12028 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
12029 | const char *context) |
12030 | { | |
6a60cd87 CK |
12031 | struct drm_device *dev = crtc->base.dev; |
12032 | struct drm_plane *plane; | |
12033 | struct intel_plane *intel_plane; | |
12034 | struct intel_plane_state *state; | |
12035 | struct drm_framebuffer *fb; | |
12036 | ||
12037 | DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id, | |
12038 | context, pipe_config, pipe_name(crtc->pipe)); | |
c0b03411 DV |
12039 | |
12040 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
12041 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
12042 | pipe_config->pipe_bpp, pipe_config->dither); | |
12043 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
12044 | pipe_config->has_pch_encoder, | |
12045 | pipe_config->fdi_lanes, | |
12046 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
12047 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
12048 | pipe_config->fdi_m_n.tu); | |
90a6b7b0 | 12049 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
eb14cb74 | 12050 | pipe_config->has_dp_encoder, |
90a6b7b0 | 12051 | pipe_config->lane_count, |
eb14cb74 VS |
12052 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, |
12053 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
12054 | pipe_config->dp_m_n.tu); | |
b95af8be | 12055 | |
90a6b7b0 | 12056 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", |
b95af8be | 12057 | pipe_config->has_dp_encoder, |
90a6b7b0 | 12058 | pipe_config->lane_count, |
b95af8be VK |
12059 | pipe_config->dp_m2_n2.gmch_m, |
12060 | pipe_config->dp_m2_n2.gmch_n, | |
12061 | pipe_config->dp_m2_n2.link_m, | |
12062 | pipe_config->dp_m2_n2.link_n, | |
12063 | pipe_config->dp_m2_n2.tu); | |
12064 | ||
55072d19 DV |
12065 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
12066 | pipe_config->has_audio, | |
12067 | pipe_config->has_infoframe); | |
12068 | ||
c0b03411 | 12069 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 12070 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 12071 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
12072 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
12073 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 12074 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
12075 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
12076 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
0ec463d3 TU |
12077 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", |
12078 | crtc->num_scalers, | |
12079 | pipe_config->scaler_state.scaler_users, | |
12080 | pipe_config->scaler_state.scaler_id); | |
c0b03411 DV |
12081 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
12082 | pipe_config->gmch_pfit.control, | |
12083 | pipe_config->gmch_pfit.pgm_ratios, | |
12084 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 12085 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 12086 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
12087 | pipe_config->pch_pfit.size, |
12088 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 12089 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 12090 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
6a60cd87 | 12091 | |
415ff0f6 | 12092 | if (IS_BROXTON(dev)) { |
05712c15 | 12093 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," |
415ff0f6 | 12094 | "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " |
c8453338 | 12095 | "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", |
415ff0f6 TU |
12096 | pipe_config->ddi_pll_sel, |
12097 | pipe_config->dpll_hw_state.ebb0, | |
05712c15 | 12098 | pipe_config->dpll_hw_state.ebb4, |
415ff0f6 TU |
12099 | pipe_config->dpll_hw_state.pll0, |
12100 | pipe_config->dpll_hw_state.pll1, | |
12101 | pipe_config->dpll_hw_state.pll2, | |
12102 | pipe_config->dpll_hw_state.pll3, | |
12103 | pipe_config->dpll_hw_state.pll6, | |
12104 | pipe_config->dpll_hw_state.pll8, | |
05712c15 | 12105 | pipe_config->dpll_hw_state.pll9, |
c8453338 | 12106 | pipe_config->dpll_hw_state.pll10, |
415ff0f6 | 12107 | pipe_config->dpll_hw_state.pcsdw12); |
ef11bdb3 | 12108 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
415ff0f6 TU |
12109 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " |
12110 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", | |
12111 | pipe_config->ddi_pll_sel, | |
12112 | pipe_config->dpll_hw_state.ctrl1, | |
12113 | pipe_config->dpll_hw_state.cfgcr1, | |
12114 | pipe_config->dpll_hw_state.cfgcr2); | |
12115 | } else if (HAS_DDI(dev)) { | |
00490c22 | 12116 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", |
415ff0f6 | 12117 | pipe_config->ddi_pll_sel, |
00490c22 ML |
12118 | pipe_config->dpll_hw_state.wrpll, |
12119 | pipe_config->dpll_hw_state.spll); | |
415ff0f6 TU |
12120 | } else { |
12121 | DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " | |
12122 | "fp0: 0x%x, fp1: 0x%x\n", | |
12123 | pipe_config->dpll_hw_state.dpll, | |
12124 | pipe_config->dpll_hw_state.dpll_md, | |
12125 | pipe_config->dpll_hw_state.fp0, | |
12126 | pipe_config->dpll_hw_state.fp1); | |
12127 | } | |
12128 | ||
6a60cd87 CK |
12129 | DRM_DEBUG_KMS("planes on this crtc\n"); |
12130 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
12131 | intel_plane = to_intel_plane(plane); | |
12132 | if (intel_plane->pipe != crtc->pipe) | |
12133 | continue; | |
12134 | ||
12135 | state = to_intel_plane_state(plane->state); | |
12136 | fb = state->base.fb; | |
12137 | if (!fb) { | |
12138 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d " | |
12139 | "disabled, scaler_id = %d\n", | |
12140 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12141 | plane->base.id, intel_plane->pipe, | |
12142 | (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1, | |
12143 | drm_plane_index(plane), state->scaler_id); | |
12144 | continue; | |
12145 | } | |
12146 | ||
12147 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled", | |
12148 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12149 | plane->base.id, intel_plane->pipe, | |
12150 | crtc->base.primary == plane ? 0 : intel_plane->plane + 1, | |
12151 | drm_plane_index(plane)); | |
12152 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x", | |
12153 | fb->base.id, fb->width, fb->height, fb->pixel_format); | |
12154 | DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n", | |
12155 | state->scaler_id, | |
12156 | state->src.x1 >> 16, state->src.y1 >> 16, | |
12157 | drm_rect_width(&state->src) >> 16, | |
12158 | drm_rect_height(&state->src) >> 16, | |
12159 | state->dst.x1, state->dst.y1, | |
12160 | drm_rect_width(&state->dst), drm_rect_height(&state->dst)); | |
12161 | } | |
c0b03411 DV |
12162 | } |
12163 | ||
5448a00d | 12164 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 12165 | { |
5448a00d ACO |
12166 | struct drm_device *dev = state->dev; |
12167 | struct intel_encoder *encoder; | |
da3ced29 | 12168 | struct drm_connector *connector; |
5448a00d | 12169 | struct drm_connector_state *connector_state; |
00f0b378 | 12170 | unsigned int used_ports = 0; |
5448a00d | 12171 | int i; |
00f0b378 VS |
12172 | |
12173 | /* | |
12174 | * Walk the connector list instead of the encoder | |
12175 | * list to detect the problem on ddi platforms | |
12176 | * where there's just one encoder per digital port. | |
12177 | */ | |
da3ced29 | 12178 | for_each_connector_in_state(state, connector, connector_state, i) { |
5448a00d | 12179 | if (!connector_state->best_encoder) |
00f0b378 VS |
12180 | continue; |
12181 | ||
5448a00d ACO |
12182 | encoder = to_intel_encoder(connector_state->best_encoder); |
12183 | ||
12184 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
12185 | |
12186 | switch (encoder->type) { | |
12187 | unsigned int port_mask; | |
12188 | case INTEL_OUTPUT_UNKNOWN: | |
12189 | if (WARN_ON(!HAS_DDI(dev))) | |
12190 | break; | |
12191 | case INTEL_OUTPUT_DISPLAYPORT: | |
12192 | case INTEL_OUTPUT_HDMI: | |
12193 | case INTEL_OUTPUT_EDP: | |
12194 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
12195 | ||
12196 | /* the same port mustn't appear more than once */ | |
12197 | if (used_ports & port_mask) | |
12198 | return false; | |
12199 | ||
12200 | used_ports |= port_mask; | |
12201 | default: | |
12202 | break; | |
12203 | } | |
12204 | } | |
12205 | ||
12206 | return true; | |
12207 | } | |
12208 | ||
83a57153 ACO |
12209 | static void |
12210 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
12211 | { | |
12212 | struct drm_crtc_state tmp_state; | |
663a3640 | 12213 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 ACO |
12214 | struct intel_dpll_hw_state dpll_hw_state; |
12215 | enum intel_dpll_id shared_dpll; | |
8504c74c | 12216 | uint32_t ddi_pll_sel; |
c4e2d043 | 12217 | bool force_thru; |
83a57153 | 12218 | |
7546a384 ACO |
12219 | /* FIXME: before the switch to atomic started, a new pipe_config was |
12220 | * kzalloc'd. Code that depends on any field being zero should be | |
12221 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
12222 | * only fields that are know to not cause problems are preserved. */ | |
12223 | ||
83a57153 | 12224 | tmp_state = crtc_state->base; |
663a3640 | 12225 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
12226 | shared_dpll = crtc_state->shared_dpll; |
12227 | dpll_hw_state = crtc_state->dpll_hw_state; | |
8504c74c | 12228 | ddi_pll_sel = crtc_state->ddi_pll_sel; |
c4e2d043 | 12229 | force_thru = crtc_state->pch_pfit.force_thru; |
4978cc93 | 12230 | |
83a57153 | 12231 | memset(crtc_state, 0, sizeof *crtc_state); |
4978cc93 | 12232 | |
83a57153 | 12233 | crtc_state->base = tmp_state; |
663a3640 | 12234 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
12235 | crtc_state->shared_dpll = shared_dpll; |
12236 | crtc_state->dpll_hw_state = dpll_hw_state; | |
8504c74c | 12237 | crtc_state->ddi_pll_sel = ddi_pll_sel; |
c4e2d043 | 12238 | crtc_state->pch_pfit.force_thru = force_thru; |
83a57153 ACO |
12239 | } |
12240 | ||
548ee15b | 12241 | static int |
b8cecdf5 | 12242 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 12243 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 12244 | { |
b359283a | 12245 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 12246 | struct intel_encoder *encoder; |
da3ced29 | 12247 | struct drm_connector *connector; |
0b901879 | 12248 | struct drm_connector_state *connector_state; |
d328c9d7 | 12249 | int base_bpp, ret = -EINVAL; |
0b901879 | 12250 | int i; |
e29c22c0 | 12251 | bool retry = true; |
ee7b9f93 | 12252 | |
83a57153 | 12253 | clear_intel_crtc_state(pipe_config); |
7758a113 | 12254 | |
e143a21c DV |
12255 | pipe_config->cpu_transcoder = |
12256 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 12257 | |
2960bc9c ID |
12258 | /* |
12259 | * Sanitize sync polarity flags based on requested ones. If neither | |
12260 | * positive or negative polarity is requested, treat this as meaning | |
12261 | * negative polarity. | |
12262 | */ | |
2d112de7 | 12263 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12264 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 12265 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 12266 | |
2d112de7 | 12267 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12268 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 12269 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 12270 | |
d328c9d7 DV |
12271 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
12272 | pipe_config); | |
12273 | if (base_bpp < 0) | |
4e53c2e0 DV |
12274 | goto fail; |
12275 | ||
e41a56be VS |
12276 | /* |
12277 | * Determine the real pipe dimensions. Note that stereo modes can | |
12278 | * increase the actual pipe size due to the frame doubling and | |
12279 | * insertion of additional space for blanks between the frame. This | |
12280 | * is stored in the crtc timings. We use the requested mode to do this | |
12281 | * computation to clearly distinguish it from the adjusted mode, which | |
12282 | * can be changed by the connectors in the below retry loop. | |
12283 | */ | |
2d112de7 | 12284 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
12285 | &pipe_config->pipe_src_w, |
12286 | &pipe_config->pipe_src_h); | |
e41a56be | 12287 | |
e29c22c0 | 12288 | encoder_retry: |
ef1b460d | 12289 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 12290 | pipe_config->port_clock = 0; |
ef1b460d | 12291 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 12292 | |
135c81b8 | 12293 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
12294 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
12295 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 12296 | |
7758a113 DV |
12297 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
12298 | * adjust it according to limitations or connector properties, and also | |
12299 | * a chance to reject the mode entirely. | |
47f1c6c9 | 12300 | */ |
da3ced29 | 12301 | for_each_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 12302 | if (connector_state->crtc != crtc) |
7758a113 | 12303 | continue; |
7ae89233 | 12304 | |
0b901879 ACO |
12305 | encoder = to_intel_encoder(connector_state->best_encoder); |
12306 | ||
efea6e8e DV |
12307 | if (!(encoder->compute_config(encoder, pipe_config))) { |
12308 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
12309 | goto fail; |
12310 | } | |
ee7b9f93 | 12311 | } |
47f1c6c9 | 12312 | |
ff9a6750 DV |
12313 | /* Set default port clock if not overwritten by the encoder. Needs to be |
12314 | * done afterwards in case the encoder adjusts the mode. */ | |
12315 | if (!pipe_config->port_clock) | |
2d112de7 | 12316 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 12317 | * pipe_config->pixel_multiplier; |
ff9a6750 | 12318 | |
a43f6e0f | 12319 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 12320 | if (ret < 0) { |
7758a113 DV |
12321 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
12322 | goto fail; | |
ee7b9f93 | 12323 | } |
e29c22c0 DV |
12324 | |
12325 | if (ret == RETRY) { | |
12326 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
12327 | ret = -EINVAL; | |
12328 | goto fail; | |
12329 | } | |
12330 | ||
12331 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
12332 | retry = false; | |
12333 | goto encoder_retry; | |
12334 | } | |
12335 | ||
e8fa4270 DV |
12336 | /* Dithering seems to not pass-through bits correctly when it should, so |
12337 | * only enable it on 6bpc panels. */ | |
12338 | pipe_config->dither = pipe_config->pipe_bpp == 6*3; | |
62f0ace5 | 12339 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 12340 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 12341 | |
7758a113 | 12342 | fail: |
548ee15b | 12343 | return ret; |
ee7b9f93 | 12344 | } |
47f1c6c9 | 12345 | |
ea9d758d | 12346 | static void |
4740b0f2 | 12347 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 12348 | { |
0a9ab303 ACO |
12349 | struct drm_crtc *crtc; |
12350 | struct drm_crtc_state *crtc_state; | |
8a75d157 | 12351 | int i; |
ea9d758d | 12352 | |
7668851f | 12353 | /* Double check state. */ |
8a75d157 | 12354 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
3cb480bc | 12355 | to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); |
fc467a22 ML |
12356 | |
12357 | /* Update hwmode for vblank functions */ | |
12358 | if (crtc->state->active) | |
12359 | crtc->hwmode = crtc->state->adjusted_mode; | |
12360 | else | |
12361 | crtc->hwmode.crtc_clock = 0; | |
61067a5e ML |
12362 | |
12363 | /* | |
12364 | * Update legacy state to satisfy fbc code. This can | |
12365 | * be removed when fbc uses the atomic state. | |
12366 | */ | |
12367 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
12368 | struct drm_plane_state *plane_state = crtc->primary->state; | |
12369 | ||
12370 | crtc->primary->fb = plane_state->fb; | |
12371 | crtc->x = plane_state->src_x >> 16; | |
12372 | crtc->y = plane_state->src_y >> 16; | |
12373 | } | |
ea9d758d | 12374 | } |
ea9d758d DV |
12375 | } |
12376 | ||
3bd26263 | 12377 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 12378 | { |
3bd26263 | 12379 | int diff; |
f1f644dc JB |
12380 | |
12381 | if (clock1 == clock2) | |
12382 | return true; | |
12383 | ||
12384 | if (!clock1 || !clock2) | |
12385 | return false; | |
12386 | ||
12387 | diff = abs(clock1 - clock2); | |
12388 | ||
12389 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
12390 | return true; | |
12391 | ||
12392 | return false; | |
12393 | } | |
12394 | ||
25c5b266 DV |
12395 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
12396 | list_for_each_entry((intel_crtc), \ | |
12397 | &(dev)->mode_config.crtc_list, \ | |
12398 | base.head) \ | |
0973f18f | 12399 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 12400 | |
cfb23ed6 ML |
12401 | static bool |
12402 | intel_compare_m_n(unsigned int m, unsigned int n, | |
12403 | unsigned int m2, unsigned int n2, | |
12404 | bool exact) | |
12405 | { | |
12406 | if (m == m2 && n == n2) | |
12407 | return true; | |
12408 | ||
12409 | if (exact || !m || !n || !m2 || !n2) | |
12410 | return false; | |
12411 | ||
12412 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
12413 | ||
12414 | if (m > m2) { | |
12415 | while (m > m2) { | |
12416 | m2 <<= 1; | |
12417 | n2 <<= 1; | |
12418 | } | |
12419 | } else if (m < m2) { | |
12420 | while (m < m2) { | |
12421 | m <<= 1; | |
12422 | n <<= 1; | |
12423 | } | |
12424 | } | |
12425 | ||
12426 | return m == m2 && n == n2; | |
12427 | } | |
12428 | ||
12429 | static bool | |
12430 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
12431 | struct intel_link_m_n *m2_n2, | |
12432 | bool adjust) | |
12433 | { | |
12434 | if (m_n->tu == m2_n2->tu && | |
12435 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
12436 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
12437 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
12438 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
12439 | if (adjust) | |
12440 | *m2_n2 = *m_n; | |
12441 | ||
12442 | return true; | |
12443 | } | |
12444 | ||
12445 | return false; | |
12446 | } | |
12447 | ||
0e8ffe1b | 12448 | static bool |
2fa2fe9a | 12449 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b | 12450 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
12451 | struct intel_crtc_state *pipe_config, |
12452 | bool adjust) | |
0e8ffe1b | 12453 | { |
cfb23ed6 ML |
12454 | bool ret = true; |
12455 | ||
12456 | #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \ | |
12457 | do { \ | |
12458 | if (!adjust) \ | |
12459 | DRM_ERROR(fmt, ##__VA_ARGS__); \ | |
12460 | else \ | |
12461 | DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \ | |
12462 | } while (0) | |
12463 | ||
66e985c0 DV |
12464 | #define PIPE_CONF_CHECK_X(name) \ |
12465 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12466 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
66e985c0 DV |
12467 | "(expected 0x%08x, found 0x%08x)\n", \ |
12468 | current_config->name, \ | |
12469 | pipe_config->name); \ | |
cfb23ed6 | 12470 | ret = false; \ |
66e985c0 DV |
12471 | } |
12472 | ||
08a24034 DV |
12473 | #define PIPE_CONF_CHECK_I(name) \ |
12474 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12475 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
08a24034 DV |
12476 | "(expected %i, found %i)\n", \ |
12477 | current_config->name, \ | |
12478 | pipe_config->name); \ | |
cfb23ed6 ML |
12479 | ret = false; \ |
12480 | } | |
12481 | ||
12482 | #define PIPE_CONF_CHECK_M_N(name) \ | |
12483 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12484 | &pipe_config->name,\ | |
12485 | adjust)) { \ | |
12486 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12487 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12488 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12489 | current_config->name.tu, \ | |
12490 | current_config->name.gmch_m, \ | |
12491 | current_config->name.gmch_n, \ | |
12492 | current_config->name.link_m, \ | |
12493 | current_config->name.link_n, \ | |
12494 | pipe_config->name.tu, \ | |
12495 | pipe_config->name.gmch_m, \ | |
12496 | pipe_config->name.gmch_n, \ | |
12497 | pipe_config->name.link_m, \ | |
12498 | pipe_config->name.link_n); \ | |
12499 | ret = false; \ | |
12500 | } | |
12501 | ||
12502 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ | |
12503 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12504 | &pipe_config->name, adjust) && \ | |
12505 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
12506 | &pipe_config->name, adjust)) { \ | |
12507 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12508 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12509 | "or tu %i gmch %i/%i link %i/%i, " \ | |
12510 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12511 | current_config->name.tu, \ | |
12512 | current_config->name.gmch_m, \ | |
12513 | current_config->name.gmch_n, \ | |
12514 | current_config->name.link_m, \ | |
12515 | current_config->name.link_n, \ | |
12516 | current_config->alt_name.tu, \ | |
12517 | current_config->alt_name.gmch_m, \ | |
12518 | current_config->alt_name.gmch_n, \ | |
12519 | current_config->alt_name.link_m, \ | |
12520 | current_config->alt_name.link_n, \ | |
12521 | pipe_config->name.tu, \ | |
12522 | pipe_config->name.gmch_m, \ | |
12523 | pipe_config->name.gmch_n, \ | |
12524 | pipe_config->name.link_m, \ | |
12525 | pipe_config->name.link_n); \ | |
12526 | ret = false; \ | |
88adfff1 DV |
12527 | } |
12528 | ||
b95af8be VK |
12529 | /* This is required for BDW+ where there is only one set of registers for |
12530 | * switching between high and low RR. | |
12531 | * This macro can be used whenever a comparison has to be made between one | |
12532 | * hw state and multiple sw state variables. | |
12533 | */ | |
12534 | #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ | |
12535 | if ((current_config->name != pipe_config->name) && \ | |
12536 | (current_config->alt_name != pipe_config->name)) { \ | |
cfb23ed6 | 12537 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
b95af8be VK |
12538 | "(expected %i or %i, found %i)\n", \ |
12539 | current_config->name, \ | |
12540 | current_config->alt_name, \ | |
12541 | pipe_config->name); \ | |
cfb23ed6 | 12542 | ret = false; \ |
b95af8be VK |
12543 | } |
12544 | ||
1bd1bd80 DV |
12545 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
12546 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
cfb23ed6 | 12547 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
12548 | "(expected %i, found %i)\n", \ |
12549 | current_config->name & (mask), \ | |
12550 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 12551 | ret = false; \ |
1bd1bd80 DV |
12552 | } |
12553 | ||
5e550656 VS |
12554 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
12555 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
cfb23ed6 | 12556 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
5e550656 VS |
12557 | "(expected %i, found %i)\n", \ |
12558 | current_config->name, \ | |
12559 | pipe_config->name); \ | |
cfb23ed6 | 12560 | ret = false; \ |
5e550656 VS |
12561 | } |
12562 | ||
bb760063 DV |
12563 | #define PIPE_CONF_QUIRK(quirk) \ |
12564 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
12565 | ||
eccb140b DV |
12566 | PIPE_CONF_CHECK_I(cpu_transcoder); |
12567 | ||
08a24034 DV |
12568 | PIPE_CONF_CHECK_I(has_pch_encoder); |
12569 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 12570 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 12571 | |
eb14cb74 | 12572 | PIPE_CONF_CHECK_I(has_dp_encoder); |
90a6b7b0 | 12573 | PIPE_CONF_CHECK_I(lane_count); |
b95af8be VK |
12574 | |
12575 | if (INTEL_INFO(dev)->gen < 8) { | |
cfb23ed6 ML |
12576 | PIPE_CONF_CHECK_M_N(dp_m_n); |
12577 | ||
12578 | PIPE_CONF_CHECK_I(has_drrs); | |
12579 | if (current_config->has_drrs) | |
12580 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
12581 | } else | |
12582 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 12583 | |
a65347ba JN |
12584 | PIPE_CONF_CHECK_I(has_dsi_encoder); |
12585 | ||
2d112de7 ACO |
12586 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
12587 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
12588 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
12589 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
12590 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
12591 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 12592 | |
2d112de7 ACO |
12593 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
12594 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
12595 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
12596 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
12597 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
12598 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 12599 | |
c93f54cf | 12600 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 12601 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 DV |
12602 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
12603 | IS_VALLEYVIEW(dev)) | |
12604 | PIPE_CONF_CHECK_I(limited_color_range); | |
e43823ec | 12605 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 12606 | |
9ed109a7 DV |
12607 | PIPE_CONF_CHECK_I(has_audio); |
12608 | ||
2d112de7 | 12609 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
12610 | DRM_MODE_FLAG_INTERLACE); |
12611 | ||
bb760063 | 12612 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 12613 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12614 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 12615 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12616 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 12617 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12618 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 12619 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
12620 | DRM_MODE_FLAG_NVSYNC); |
12621 | } | |
045ac3b5 | 12622 | |
333b8ca8 | 12623 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a DV |
12624 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
12625 | if (INTEL_INFO(dev)->gen < 4) | |
12626 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
333b8ca8 | 12627 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 12628 | |
bfd16b2a ML |
12629 | if (!adjust) { |
12630 | PIPE_CONF_CHECK_I(pipe_src_w); | |
12631 | PIPE_CONF_CHECK_I(pipe_src_h); | |
12632 | ||
12633 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
12634 | if (current_config->pch_pfit.enabled) { | |
12635 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
12636 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
12637 | } | |
2fa2fe9a | 12638 | |
7aefe2b5 ML |
12639 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
12640 | } | |
a1b2278e | 12641 | |
e59150dc JB |
12642 | /* BDW+ don't expose a synchronous way to read the state */ |
12643 | if (IS_HASWELL(dev)) | |
12644 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 12645 | |
282740f7 VS |
12646 | PIPE_CONF_CHECK_I(double_wide); |
12647 | ||
26804afd DV |
12648 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
12649 | ||
c0d43d62 | 12650 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 12651 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 12652 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
12653 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
12654 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 12655 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
00490c22 | 12656 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
3f4cd19f DL |
12657 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
12658 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
12659 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 12660 | |
42571aef VS |
12661 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
12662 | PIPE_CONF_CHECK_I(pipe_bpp); | |
12663 | ||
2d112de7 | 12664 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 12665 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 12666 | |
66e985c0 | 12667 | #undef PIPE_CONF_CHECK_X |
08a24034 | 12668 | #undef PIPE_CONF_CHECK_I |
b95af8be | 12669 | #undef PIPE_CONF_CHECK_I_ALT |
1bd1bd80 | 12670 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 12671 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 12672 | #undef PIPE_CONF_QUIRK |
cfb23ed6 | 12673 | #undef INTEL_ERR_OR_DBG_KMS |
88adfff1 | 12674 | |
cfb23ed6 | 12675 | return ret; |
0e8ffe1b DV |
12676 | } |
12677 | ||
08db6652 DL |
12678 | static void check_wm_state(struct drm_device *dev) |
12679 | { | |
12680 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12681 | struct skl_ddb_allocation hw_ddb, *sw_ddb; | |
12682 | struct intel_crtc *intel_crtc; | |
12683 | int plane; | |
12684 | ||
12685 | if (INTEL_INFO(dev)->gen < 9) | |
12686 | return; | |
12687 | ||
12688 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
12689 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
12690 | ||
12691 | for_each_intel_crtc(dev, intel_crtc) { | |
12692 | struct skl_ddb_entry *hw_entry, *sw_entry; | |
12693 | const enum pipe pipe = intel_crtc->pipe; | |
12694 | ||
12695 | if (!intel_crtc->active) | |
12696 | continue; | |
12697 | ||
12698 | /* planes */ | |
dd740780 | 12699 | for_each_plane(dev_priv, pipe, plane) { |
08db6652 DL |
12700 | hw_entry = &hw_ddb.plane[pipe][plane]; |
12701 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
12702 | ||
12703 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12704 | continue; | |
12705 | ||
12706 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " | |
12707 | "(expected (%u,%u), found (%u,%u))\n", | |
12708 | pipe_name(pipe), plane + 1, | |
12709 | sw_entry->start, sw_entry->end, | |
12710 | hw_entry->start, hw_entry->end); | |
12711 | } | |
12712 | ||
12713 | /* cursor */ | |
4969d33e MR |
12714 | hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; |
12715 | sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; | |
08db6652 DL |
12716 | |
12717 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12718 | continue; | |
12719 | ||
12720 | DRM_ERROR("mismatch in DDB state pipe %c cursor " | |
12721 | "(expected (%u,%u), found (%u,%u))\n", | |
12722 | pipe_name(pipe), | |
12723 | sw_entry->start, sw_entry->end, | |
12724 | hw_entry->start, hw_entry->end); | |
12725 | } | |
12726 | } | |
12727 | ||
91d1b4bd | 12728 | static void |
35dd3c64 ML |
12729 | check_connector_state(struct drm_device *dev, |
12730 | struct drm_atomic_state *old_state) | |
8af6cf88 | 12731 | { |
35dd3c64 ML |
12732 | struct drm_connector_state *old_conn_state; |
12733 | struct drm_connector *connector; | |
12734 | int i; | |
8af6cf88 | 12735 | |
35dd3c64 ML |
12736 | for_each_connector_in_state(old_state, connector, old_conn_state, i) { |
12737 | struct drm_encoder *encoder = connector->encoder; | |
12738 | struct drm_connector_state *state = connector->state; | |
ad3c558f | 12739 | |
8af6cf88 DV |
12740 | /* This also checks the encoder/connector hw state with the |
12741 | * ->get_hw_state callbacks. */ | |
35dd3c64 | 12742 | intel_connector_check_state(to_intel_connector(connector)); |
8af6cf88 | 12743 | |
ad3c558f | 12744 | I915_STATE_WARN(state->best_encoder != encoder, |
35dd3c64 | 12745 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 12746 | } |
91d1b4bd DV |
12747 | } |
12748 | ||
12749 | static void | |
12750 | check_encoder_state(struct drm_device *dev) | |
12751 | { | |
12752 | struct intel_encoder *encoder; | |
12753 | struct intel_connector *connector; | |
8af6cf88 | 12754 | |
b2784e15 | 12755 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 | 12756 | bool enabled = false; |
4d20cd86 | 12757 | enum pipe pipe; |
8af6cf88 DV |
12758 | |
12759 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
12760 | encoder->base.base.id, | |
8e329a03 | 12761 | encoder->base.name); |
8af6cf88 | 12762 | |
3a3371ff | 12763 | for_each_intel_connector(dev, connector) { |
4d20cd86 | 12764 | if (connector->base.state->best_encoder != &encoder->base) |
8af6cf88 DV |
12765 | continue; |
12766 | enabled = true; | |
ad3c558f ML |
12767 | |
12768 | I915_STATE_WARN(connector->base.state->crtc != | |
12769 | encoder->base.crtc, | |
12770 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 12771 | } |
0e32b39c | 12772 | |
e2c719b7 | 12773 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
12774 | "encoder's enabled state mismatch " |
12775 | "(expected %i, found %i)\n", | |
12776 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
12777 | |
12778 | if (!encoder->base.crtc) { | |
4d20cd86 | 12779 | bool active; |
7c60d198 | 12780 | |
4d20cd86 ML |
12781 | active = encoder->get_hw_state(encoder, &pipe); |
12782 | I915_STATE_WARN(active, | |
12783 | "encoder detached but still enabled on pipe %c.\n", | |
12784 | pipe_name(pipe)); | |
7c60d198 | 12785 | } |
8af6cf88 | 12786 | } |
91d1b4bd DV |
12787 | } |
12788 | ||
12789 | static void | |
4d20cd86 | 12790 | check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state) |
91d1b4bd | 12791 | { |
fbee40df | 12792 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd | 12793 | struct intel_encoder *encoder; |
4d20cd86 ML |
12794 | struct drm_crtc_state *old_crtc_state; |
12795 | struct drm_crtc *crtc; | |
12796 | int i; | |
8af6cf88 | 12797 | |
4d20cd86 ML |
12798 | for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) { |
12799 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12800 | struct intel_crtc_state *pipe_config, *sw_config; | |
7b89b8de | 12801 | bool active; |
8af6cf88 | 12802 | |
bfd16b2a ML |
12803 | if (!needs_modeset(crtc->state) && |
12804 | !to_intel_crtc_state(crtc->state)->update_pipe) | |
4d20cd86 | 12805 | continue; |
045ac3b5 | 12806 | |
4d20cd86 ML |
12807 | __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state); |
12808 | pipe_config = to_intel_crtc_state(old_crtc_state); | |
12809 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
12810 | pipe_config->base.crtc = crtc; | |
12811 | pipe_config->base.state = old_state; | |
8af6cf88 | 12812 | |
4d20cd86 ML |
12813 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
12814 | crtc->base.id); | |
8af6cf88 | 12815 | |
4d20cd86 ML |
12816 | active = dev_priv->display.get_pipe_config(intel_crtc, |
12817 | pipe_config); | |
d62cf62a | 12818 | |
b6b5d049 | 12819 | /* hw state is inconsistent with the pipe quirk */ |
4d20cd86 ML |
12820 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
12821 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
12822 | active = crtc->state->active; | |
6c49f241 | 12823 | |
4d20cd86 | 12824 | I915_STATE_WARN(crtc->state->active != active, |
0e8ffe1b | 12825 | "crtc active state doesn't match with hw state " |
4d20cd86 | 12826 | "(expected %i, found %i)\n", crtc->state->active, active); |
0e8ffe1b | 12827 | |
4d20cd86 | 12828 | I915_STATE_WARN(intel_crtc->active != crtc->state->active, |
53d9f4e9 | 12829 | "transitional active state does not match atomic hw state " |
4d20cd86 ML |
12830 | "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active); |
12831 | ||
12832 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
12833 | enum pipe pipe; | |
12834 | ||
12835 | active = encoder->get_hw_state(encoder, &pipe); | |
12836 | I915_STATE_WARN(active != crtc->state->active, | |
12837 | "[ENCODER:%i] active %i with crtc active %i\n", | |
12838 | encoder->base.base.id, active, crtc->state->active); | |
12839 | ||
12840 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, | |
12841 | "Encoder connected to wrong pipe %c\n", | |
12842 | pipe_name(pipe)); | |
12843 | ||
12844 | if (active) | |
12845 | encoder->get_config(encoder, pipe_config); | |
12846 | } | |
53d9f4e9 | 12847 | |
4d20cd86 | 12848 | if (!crtc->state->active) |
cfb23ed6 ML |
12849 | continue; |
12850 | ||
4d20cd86 ML |
12851 | sw_config = to_intel_crtc_state(crtc->state); |
12852 | if (!intel_pipe_config_compare(dev, sw_config, | |
12853 | pipe_config, false)) { | |
e2c719b7 | 12854 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); |
4d20cd86 | 12855 | intel_dump_pipe_config(intel_crtc, pipe_config, |
c0b03411 | 12856 | "[hw state]"); |
4d20cd86 | 12857 | intel_dump_pipe_config(intel_crtc, sw_config, |
c0b03411 DV |
12858 | "[sw state]"); |
12859 | } | |
8af6cf88 DV |
12860 | } |
12861 | } | |
12862 | ||
91d1b4bd DV |
12863 | static void |
12864 | check_shared_dpll_state(struct drm_device *dev) | |
12865 | { | |
fbee40df | 12866 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
12867 | struct intel_crtc *crtc; |
12868 | struct intel_dpll_hw_state dpll_hw_state; | |
12869 | int i; | |
5358901f DV |
12870 | |
12871 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
12872 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
12873 | int enabled_crtcs = 0, active_crtcs = 0; | |
12874 | bool active; | |
12875 | ||
12876 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
12877 | ||
12878 | DRM_DEBUG_KMS("%s\n", pll->name); | |
12879 | ||
12880 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
12881 | ||
e2c719b7 | 12882 | I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask), |
5358901f | 12883 | "more active pll users than references: %i vs %i\n", |
3e369b76 | 12884 | pll->active, hweight32(pll->config.crtc_mask)); |
e2c719b7 | 12885 | I915_STATE_WARN(pll->active && !pll->on, |
5358901f | 12886 | "pll in active use but not on in sw tracking\n"); |
e2c719b7 | 12887 | I915_STATE_WARN(pll->on && !pll->active, |
35c95375 | 12888 | "pll in on but not on in use in sw tracking\n"); |
e2c719b7 | 12889 | I915_STATE_WARN(pll->on != active, |
5358901f DV |
12890 | "pll on state mismatch (expected %i, found %i)\n", |
12891 | pll->on, active); | |
12892 | ||
d3fcc808 | 12893 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 12894 | if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll) |
5358901f DV |
12895 | enabled_crtcs++; |
12896 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
12897 | active_crtcs++; | |
12898 | } | |
e2c719b7 | 12899 | I915_STATE_WARN(pll->active != active_crtcs, |
5358901f DV |
12900 | "pll active crtcs mismatch (expected %i, found %i)\n", |
12901 | pll->active, active_crtcs); | |
e2c719b7 | 12902 | I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs, |
5358901f | 12903 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
3e369b76 | 12904 | hweight32(pll->config.crtc_mask), enabled_crtcs); |
66e985c0 | 12905 | |
e2c719b7 | 12906 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state, |
66e985c0 DV |
12907 | sizeof(dpll_hw_state)), |
12908 | "pll hw state mismatch\n"); | |
5358901f | 12909 | } |
8af6cf88 DV |
12910 | } |
12911 | ||
ee165b1a ML |
12912 | static void |
12913 | intel_modeset_check_state(struct drm_device *dev, | |
12914 | struct drm_atomic_state *old_state) | |
91d1b4bd | 12915 | { |
08db6652 | 12916 | check_wm_state(dev); |
35dd3c64 | 12917 | check_connector_state(dev, old_state); |
91d1b4bd | 12918 | check_encoder_state(dev); |
4d20cd86 | 12919 | check_crtc_state(dev, old_state); |
91d1b4bd DV |
12920 | check_shared_dpll_state(dev); |
12921 | } | |
12922 | ||
5cec258b | 12923 | void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config, |
18442d08 VS |
12924 | int dotclock) |
12925 | { | |
12926 | /* | |
12927 | * FDI already provided one idea for the dotclock. | |
12928 | * Yell if the encoder disagrees. | |
12929 | */ | |
2d112de7 | 12930 | WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock), |
18442d08 | 12931 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
2d112de7 | 12932 | pipe_config->base.adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
12933 | } |
12934 | ||
80715b2f VS |
12935 | static void update_scanline_offset(struct intel_crtc *crtc) |
12936 | { | |
12937 | struct drm_device *dev = crtc->base.dev; | |
12938 | ||
12939 | /* | |
12940 | * The scanline counter increments at the leading edge of hsync. | |
12941 | * | |
12942 | * On most platforms it starts counting from vtotal-1 on the | |
12943 | * first active line. That means the scanline counter value is | |
12944 | * always one less than what we would expect. Ie. just after | |
12945 | * start of vblank, which also occurs at start of hsync (on the | |
12946 | * last active line), the scanline counter will read vblank_start-1. | |
12947 | * | |
12948 | * On gen2 the scanline counter starts counting from 1 instead | |
12949 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
12950 | * to keep the value positive), instead of adding one. | |
12951 | * | |
12952 | * On HSW+ the behaviour of the scanline counter depends on the output | |
12953 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
12954 | * there's an extra 1 line difference. So we need to add two instead of | |
12955 | * one to the value. | |
12956 | */ | |
12957 | if (IS_GEN2(dev)) { | |
124abe07 | 12958 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
12959 | int vtotal; |
12960 | ||
124abe07 VS |
12961 | vtotal = adjusted_mode->crtc_vtotal; |
12962 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
12963 | vtotal /= 2; |
12964 | ||
12965 | crtc->scanline_offset = vtotal - 1; | |
12966 | } else if (HAS_DDI(dev) && | |
409ee761 | 12967 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
12968 | crtc->scanline_offset = 2; |
12969 | } else | |
12970 | crtc->scanline_offset = 1; | |
12971 | } | |
12972 | ||
ad421372 | 12973 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 12974 | { |
225da59b | 12975 | struct drm_device *dev = state->dev; |
ed6739ef | 12976 | struct drm_i915_private *dev_priv = to_i915(dev); |
ad421372 | 12977 | struct intel_shared_dpll_config *shared_dpll = NULL; |
ed6739ef | 12978 | struct intel_crtc *intel_crtc; |
0a9ab303 ACO |
12979 | struct intel_crtc_state *intel_crtc_state; |
12980 | struct drm_crtc *crtc; | |
12981 | struct drm_crtc_state *crtc_state; | |
0a9ab303 | 12982 | int i; |
ed6739ef ACO |
12983 | |
12984 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 12985 | return; |
ed6739ef | 12986 | |
0a9ab303 | 12987 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
ad421372 ML |
12988 | int dpll; |
12989 | ||
0a9ab303 | 12990 | intel_crtc = to_intel_crtc(crtc); |
4978cc93 | 12991 | intel_crtc_state = to_intel_crtc_state(crtc_state); |
ad421372 | 12992 | dpll = intel_crtc_state->shared_dpll; |
0a9ab303 | 12993 | |
ad421372 | 12994 | if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE) |
225da59b ACO |
12995 | continue; |
12996 | ||
ad421372 | 12997 | intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE; |
0a9ab303 | 12998 | |
ad421372 ML |
12999 | if (!shared_dpll) |
13000 | shared_dpll = intel_atomic_get_shared_dpll_state(state); | |
ed6739ef | 13001 | |
ad421372 ML |
13002 | shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe); |
13003 | } | |
ed6739ef ACO |
13004 | } |
13005 | ||
99d736a2 ML |
13006 | /* |
13007 | * This implements the workaround described in the "notes" section of the mode | |
13008 | * set sequence documentation. When going from no pipes or single pipe to | |
13009 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
13010 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
13011 | */ | |
13012 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
13013 | { | |
13014 | struct drm_crtc_state *crtc_state; | |
13015 | struct intel_crtc *intel_crtc; | |
13016 | struct drm_crtc *crtc; | |
13017 | struct intel_crtc_state *first_crtc_state = NULL; | |
13018 | struct intel_crtc_state *other_crtc_state = NULL; | |
13019 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
13020 | int i; | |
13021 | ||
13022 | /* look at all crtc's that are going to be enabled in during modeset */ | |
13023 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13024 | intel_crtc = to_intel_crtc(crtc); | |
13025 | ||
13026 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
13027 | continue; | |
13028 | ||
13029 | if (first_crtc_state) { | |
13030 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
13031 | break; | |
13032 | } else { | |
13033 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
13034 | first_pipe = intel_crtc->pipe; | |
13035 | } | |
13036 | } | |
13037 | ||
13038 | /* No workaround needed? */ | |
13039 | if (!first_crtc_state) | |
13040 | return 0; | |
13041 | ||
13042 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
13043 | for_each_intel_crtc(state->dev, intel_crtc) { | |
13044 | struct intel_crtc_state *pipe_config; | |
13045 | ||
13046 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
13047 | if (IS_ERR(pipe_config)) | |
13048 | return PTR_ERR(pipe_config); | |
13049 | ||
13050 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
13051 | ||
13052 | if (!pipe_config->base.active || | |
13053 | needs_modeset(&pipe_config->base)) | |
13054 | continue; | |
13055 | ||
13056 | /* 2 or more enabled crtcs means no need for w/a */ | |
13057 | if (enabled_pipe != INVALID_PIPE) | |
13058 | return 0; | |
13059 | ||
13060 | enabled_pipe = intel_crtc->pipe; | |
13061 | } | |
13062 | ||
13063 | if (enabled_pipe != INVALID_PIPE) | |
13064 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
13065 | else if (other_crtc_state) | |
13066 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
13067 | ||
13068 | return 0; | |
13069 | } | |
13070 | ||
27c329ed ML |
13071 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
13072 | { | |
13073 | struct drm_crtc *crtc; | |
13074 | struct drm_crtc_state *crtc_state; | |
13075 | int ret = 0; | |
13076 | ||
13077 | /* add all active pipes to the state */ | |
13078 | for_each_crtc(state->dev, crtc) { | |
13079 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13080 | if (IS_ERR(crtc_state)) | |
13081 | return PTR_ERR(crtc_state); | |
13082 | ||
13083 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
13084 | continue; | |
13085 | ||
13086 | crtc_state->mode_changed = true; | |
13087 | ||
13088 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
13089 | if (ret) | |
13090 | break; | |
13091 | ||
13092 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13093 | if (ret) | |
13094 | break; | |
13095 | } | |
13096 | ||
13097 | return ret; | |
13098 | } | |
13099 | ||
c347a676 | 13100 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd ACO |
13101 | { |
13102 | struct drm_device *dev = state->dev; | |
27c329ed | 13103 | struct drm_i915_private *dev_priv = dev->dev_private; |
054518dd ACO |
13104 | int ret; |
13105 | ||
b359283a ML |
13106 | if (!check_digital_port_conflicts(state)) { |
13107 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
13108 | return -EINVAL; | |
13109 | } | |
13110 | ||
054518dd ACO |
13111 | /* |
13112 | * See if the config requires any additional preparation, e.g. | |
13113 | * to adjust global state with pipes off. We need to do this | |
13114 | * here so we can get the modeset_pipe updated config for the new | |
13115 | * mode set on this crtc. For other crtcs we need to use the | |
13116 | * adjusted_mode bits in the crtc directly. | |
13117 | */ | |
27c329ed ML |
13118 | if (dev_priv->display.modeset_calc_cdclk) { |
13119 | unsigned int cdclk; | |
b432e5cf | 13120 | |
27c329ed ML |
13121 | ret = dev_priv->display.modeset_calc_cdclk(state); |
13122 | ||
13123 | cdclk = to_intel_atomic_state(state)->cdclk; | |
13124 | if (!ret && cdclk != dev_priv->cdclk_freq) | |
13125 | ret = intel_modeset_all_pipes(state); | |
13126 | ||
13127 | if (ret < 0) | |
054518dd | 13128 | return ret; |
27c329ed ML |
13129 | } else |
13130 | to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq; | |
054518dd | 13131 | |
ad421372 | 13132 | intel_modeset_clear_plls(state); |
054518dd | 13133 | |
99d736a2 | 13134 | if (IS_HASWELL(dev)) |
ad421372 | 13135 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 13136 | |
ad421372 | 13137 | return 0; |
c347a676 ACO |
13138 | } |
13139 | ||
aa363136 MR |
13140 | /* |
13141 | * Handle calculation of various watermark data at the end of the atomic check | |
13142 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
13143 | * handlers to ensure that all derived state has been updated. | |
13144 | */ | |
13145 | static void calc_watermark_data(struct drm_atomic_state *state) | |
13146 | { | |
13147 | struct drm_device *dev = state->dev; | |
13148 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
13149 | struct drm_crtc *crtc; | |
13150 | struct drm_crtc_state *cstate; | |
13151 | struct drm_plane *plane; | |
13152 | struct drm_plane_state *pstate; | |
13153 | ||
13154 | /* | |
13155 | * Calculate watermark configuration details now that derived | |
13156 | * plane/crtc state is all properly updated. | |
13157 | */ | |
13158 | drm_for_each_crtc(crtc, dev) { | |
13159 | cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?: | |
13160 | crtc->state; | |
13161 | ||
13162 | if (cstate->active) | |
13163 | intel_state->wm_config.num_pipes_active++; | |
13164 | } | |
13165 | drm_for_each_legacy_plane(plane, dev) { | |
13166 | pstate = drm_atomic_get_existing_plane_state(state, plane) ?: | |
13167 | plane->state; | |
13168 | ||
13169 | if (!to_intel_plane_state(pstate)->visible) | |
13170 | continue; | |
13171 | ||
13172 | intel_state->wm_config.sprites_enabled = true; | |
13173 | if (pstate->crtc_w != pstate->src_w >> 16 || | |
13174 | pstate->crtc_h != pstate->src_h >> 16) | |
13175 | intel_state->wm_config.sprites_scaled = true; | |
13176 | } | |
13177 | } | |
13178 | ||
74c090b1 ML |
13179 | /** |
13180 | * intel_atomic_check - validate state object | |
13181 | * @dev: drm device | |
13182 | * @state: state to validate | |
13183 | */ | |
13184 | static int intel_atomic_check(struct drm_device *dev, | |
13185 | struct drm_atomic_state *state) | |
c347a676 | 13186 | { |
aa363136 | 13187 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
c347a676 ACO |
13188 | struct drm_crtc *crtc; |
13189 | struct drm_crtc_state *crtc_state; | |
13190 | int ret, i; | |
61333b60 | 13191 | bool any_ms = false; |
c347a676 | 13192 | |
74c090b1 | 13193 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
13194 | if (ret) |
13195 | return ret; | |
13196 | ||
c347a676 | 13197 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
cfb23ed6 ML |
13198 | struct intel_crtc_state *pipe_config = |
13199 | to_intel_crtc_state(crtc_state); | |
1ed51de9 | 13200 | |
ba8af3e5 ML |
13201 | memset(&to_intel_crtc(crtc)->atomic, 0, |
13202 | sizeof(struct intel_crtc_atomic_commit)); | |
13203 | ||
1ed51de9 DV |
13204 | /* Catch I915_MODE_FLAG_INHERITED */ |
13205 | if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) | |
13206 | crtc_state->mode_changed = true; | |
cfb23ed6 | 13207 | |
61333b60 ML |
13208 | if (!crtc_state->enable) { |
13209 | if (needs_modeset(crtc_state)) | |
13210 | any_ms = true; | |
c347a676 | 13211 | continue; |
61333b60 | 13212 | } |
c347a676 | 13213 | |
26495481 | 13214 | if (!needs_modeset(crtc_state)) |
cfb23ed6 ML |
13215 | continue; |
13216 | ||
26495481 DV |
13217 | /* FIXME: For only active_changed we shouldn't need to do any |
13218 | * state recomputation at all. */ | |
13219 | ||
1ed51de9 DV |
13220 | ret = drm_atomic_add_affected_connectors(state, crtc); |
13221 | if (ret) | |
13222 | return ret; | |
b359283a | 13223 | |
cfb23ed6 | 13224 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
c347a676 ACO |
13225 | if (ret) |
13226 | return ret; | |
13227 | ||
73831236 JN |
13228 | if (i915.fastboot && |
13229 | intel_pipe_config_compare(state->dev, | |
cfb23ed6 | 13230 | to_intel_crtc_state(crtc->state), |
1ed51de9 | 13231 | pipe_config, true)) { |
26495481 | 13232 | crtc_state->mode_changed = false; |
bfd16b2a | 13233 | to_intel_crtc_state(crtc_state)->update_pipe = true; |
26495481 DV |
13234 | } |
13235 | ||
13236 | if (needs_modeset(crtc_state)) { | |
13237 | any_ms = true; | |
cfb23ed6 ML |
13238 | |
13239 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13240 | if (ret) | |
13241 | return ret; | |
13242 | } | |
61333b60 | 13243 | |
26495481 DV |
13244 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
13245 | needs_modeset(crtc_state) ? | |
13246 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
13247 | } |
13248 | ||
61333b60 ML |
13249 | if (any_ms) { |
13250 | ret = intel_modeset_checks(state); | |
13251 | ||
13252 | if (ret) | |
13253 | return ret; | |
27c329ed | 13254 | } else |
aa363136 | 13255 | intel_state->cdclk = to_i915(state->dev)->cdclk_freq; |
76305b1a | 13256 | |
aa363136 MR |
13257 | ret = drm_atomic_helper_check_planes(state->dev, state); |
13258 | if (ret) | |
13259 | return ret; | |
13260 | ||
13261 | calc_watermark_data(state); | |
13262 | ||
13263 | return 0; | |
054518dd ACO |
13264 | } |
13265 | ||
5008e874 ML |
13266 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
13267 | struct drm_atomic_state *state, | |
13268 | bool async) | |
13269 | { | |
7580d774 ML |
13270 | struct drm_i915_private *dev_priv = dev->dev_private; |
13271 | struct drm_plane_state *plane_state; | |
5008e874 | 13272 | struct drm_crtc_state *crtc_state; |
7580d774 | 13273 | struct drm_plane *plane; |
5008e874 ML |
13274 | struct drm_crtc *crtc; |
13275 | int i, ret; | |
13276 | ||
13277 | if (async) { | |
13278 | DRM_DEBUG_KMS("i915 does not yet support async commit\n"); | |
13279 | return -EINVAL; | |
13280 | } | |
13281 | ||
13282 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13283 | ret = intel_crtc_wait_for_pending_flips(crtc); | |
13284 | if (ret) | |
13285 | return ret; | |
7580d774 ML |
13286 | |
13287 | if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) | |
13288 | flush_workqueue(dev_priv->wq); | |
5008e874 ML |
13289 | } |
13290 | ||
f935675f ML |
13291 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
13292 | if (ret) | |
13293 | return ret; | |
13294 | ||
5008e874 | 13295 | ret = drm_atomic_helper_prepare_planes(dev, state); |
7580d774 ML |
13296 | if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) { |
13297 | u32 reset_counter; | |
13298 | ||
13299 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); | |
13300 | mutex_unlock(&dev->struct_mutex); | |
13301 | ||
13302 | for_each_plane_in_state(state, plane, plane_state, i) { | |
13303 | struct intel_plane_state *intel_plane_state = | |
13304 | to_intel_plane_state(plane_state); | |
13305 | ||
13306 | if (!intel_plane_state->wait_req) | |
13307 | continue; | |
13308 | ||
13309 | ret = __i915_wait_request(intel_plane_state->wait_req, | |
13310 | reset_counter, true, | |
13311 | NULL, NULL); | |
13312 | ||
13313 | /* Swallow -EIO errors to allow updates during hw lockup. */ | |
13314 | if (ret == -EIO) | |
13315 | ret = 0; | |
13316 | ||
13317 | if (ret) | |
13318 | break; | |
13319 | } | |
13320 | ||
13321 | if (!ret) | |
13322 | return 0; | |
13323 | ||
13324 | mutex_lock(&dev->struct_mutex); | |
13325 | drm_atomic_helper_cleanup_planes(dev, state); | |
13326 | } | |
5008e874 | 13327 | |
f935675f | 13328 | mutex_unlock(&dev->struct_mutex); |
5008e874 ML |
13329 | return ret; |
13330 | } | |
13331 | ||
74c090b1 ML |
13332 | /** |
13333 | * intel_atomic_commit - commit validated state object | |
13334 | * @dev: DRM device | |
13335 | * @state: the top-level driver state object | |
13336 | * @async: asynchronous commit | |
13337 | * | |
13338 | * This function commits a top-level state object that has been validated | |
13339 | * with drm_atomic_helper_check(). | |
13340 | * | |
13341 | * FIXME: Atomic modeset support for i915 is not yet complete. At the moment | |
13342 | * we can only handle plane-related operations and do not yet support | |
13343 | * asynchronous commit. | |
13344 | * | |
13345 | * RETURNS | |
13346 | * Zero for success or -errno. | |
13347 | */ | |
13348 | static int intel_atomic_commit(struct drm_device *dev, | |
13349 | struct drm_atomic_state *state, | |
13350 | bool async) | |
a6778b3c | 13351 | { |
fbee40df | 13352 | struct drm_i915_private *dev_priv = dev->dev_private; |
0a9ab303 | 13353 | struct drm_crtc_state *crtc_state; |
7580d774 | 13354 | struct drm_crtc *crtc; |
c0c36b94 | 13355 | int ret = 0; |
0a9ab303 | 13356 | int i; |
61333b60 | 13357 | bool any_ms = false; |
a6778b3c | 13358 | |
5008e874 | 13359 | ret = intel_atomic_prepare_commit(dev, state, async); |
7580d774 ML |
13360 | if (ret) { |
13361 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); | |
d4afb8cc | 13362 | return ret; |
7580d774 | 13363 | } |
d4afb8cc | 13364 | |
1c5e19f8 | 13365 | drm_atomic_helper_swap_state(dev, state); |
aa363136 | 13366 | dev_priv->wm.config = to_intel_atomic_state(state)->wm_config; |
1c5e19f8 | 13367 | |
0a9ab303 | 13368 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
a539205a ML |
13369 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13370 | ||
61333b60 ML |
13371 | if (!needs_modeset(crtc->state)) |
13372 | continue; | |
13373 | ||
13374 | any_ms = true; | |
a539205a | 13375 | intel_pre_plane_update(intel_crtc); |
460da916 | 13376 | |
a539205a ML |
13377 | if (crtc_state->active) { |
13378 | intel_crtc_disable_planes(crtc, crtc_state->plane_mask); | |
13379 | dev_priv->display.crtc_disable(crtc); | |
eddfcbcd ML |
13380 | intel_crtc->active = false; |
13381 | intel_disable_shared_dpll(intel_crtc); | |
9bbc8258 VS |
13382 | |
13383 | /* | |
13384 | * Underruns don't always raise | |
13385 | * interrupts, so check manually. | |
13386 | */ | |
13387 | intel_check_cpu_fifo_underruns(dev_priv); | |
13388 | intel_check_pch_fifo_underruns(dev_priv); | |
a539205a | 13389 | } |
b8cecdf5 | 13390 | } |
7758a113 | 13391 | |
ea9d758d DV |
13392 | /* Only after disabling all output pipelines that will be changed can we |
13393 | * update the the output configuration. */ | |
4740b0f2 | 13394 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 13395 | |
4740b0f2 ML |
13396 | if (any_ms) { |
13397 | intel_shared_dpll_commit(state); | |
13398 | ||
13399 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); | |
61333b60 | 13400 | modeset_update_crtc_power_domains(state); |
4740b0f2 | 13401 | } |
47fab737 | 13402 | |
a6778b3c | 13403 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
0a9ab303 | 13404 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
f6ac4b2a ML |
13405 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13406 | bool modeset = needs_modeset(crtc->state); | |
bfd16b2a ML |
13407 | bool update_pipe = !modeset && |
13408 | to_intel_crtc_state(crtc->state)->update_pipe; | |
13409 | unsigned long put_domains = 0; | |
f6ac4b2a | 13410 | |
9f836f90 PJ |
13411 | if (modeset) |
13412 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); | |
13413 | ||
f6ac4b2a | 13414 | if (modeset && crtc->state->active) { |
a539205a ML |
13415 | update_scanline_offset(to_intel_crtc(crtc)); |
13416 | dev_priv->display.crtc_enable(crtc); | |
13417 | } | |
80715b2f | 13418 | |
bfd16b2a ML |
13419 | if (update_pipe) { |
13420 | put_domains = modeset_get_crtc_power_domains(crtc); | |
13421 | ||
13422 | /* make sure intel_modeset_check_state runs */ | |
13423 | any_ms = true; | |
13424 | } | |
13425 | ||
f6ac4b2a ML |
13426 | if (!modeset) |
13427 | intel_pre_plane_update(intel_crtc); | |
13428 | ||
6173ee28 ML |
13429 | if (crtc->state->active && |
13430 | (crtc->state->planes_changed || update_pipe)) | |
62852622 | 13431 | drm_atomic_helper_commit_planes_on_crtc(crtc_state); |
bfd16b2a ML |
13432 | |
13433 | if (put_domains) | |
13434 | modeset_put_power_domains(dev_priv, put_domains); | |
13435 | ||
f6ac4b2a | 13436 | intel_post_plane_update(intel_crtc); |
9f836f90 PJ |
13437 | |
13438 | if (modeset) | |
13439 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); | |
80715b2f | 13440 | } |
a6778b3c | 13441 | |
a6778b3c | 13442 | /* FIXME: add subpixel order */ |
83a57153 | 13443 | |
74c090b1 | 13444 | drm_atomic_helper_wait_for_vblanks(dev, state); |
f935675f ML |
13445 | |
13446 | mutex_lock(&dev->struct_mutex); | |
d4afb8cc | 13447 | drm_atomic_helper_cleanup_planes(dev, state); |
f935675f | 13448 | mutex_unlock(&dev->struct_mutex); |
2bfb4627 | 13449 | |
74c090b1 | 13450 | if (any_ms) |
ee165b1a ML |
13451 | intel_modeset_check_state(dev, state); |
13452 | ||
13453 | drm_atomic_state_free(state); | |
f30da187 | 13454 | |
74c090b1 | 13455 | return 0; |
7f27126e JB |
13456 | } |
13457 | ||
c0c36b94 CW |
13458 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
13459 | { | |
83a57153 ACO |
13460 | struct drm_device *dev = crtc->dev; |
13461 | struct drm_atomic_state *state; | |
e694eb02 | 13462 | struct drm_crtc_state *crtc_state; |
2bfb4627 | 13463 | int ret; |
83a57153 ACO |
13464 | |
13465 | state = drm_atomic_state_alloc(dev); | |
13466 | if (!state) { | |
e694eb02 | 13467 | DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory", |
83a57153 ACO |
13468 | crtc->base.id); |
13469 | return; | |
13470 | } | |
13471 | ||
e694eb02 | 13472 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
83a57153 | 13473 | |
e694eb02 ML |
13474 | retry: |
13475 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13476 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
13477 | if (!ret) { | |
13478 | if (!crtc_state->active) | |
13479 | goto out; | |
83a57153 | 13480 | |
e694eb02 | 13481 | crtc_state->mode_changed = true; |
74c090b1 | 13482 | ret = drm_atomic_commit(state); |
83a57153 ACO |
13483 | } |
13484 | ||
e694eb02 ML |
13485 | if (ret == -EDEADLK) { |
13486 | drm_atomic_state_clear(state); | |
13487 | drm_modeset_backoff(state->acquire_ctx); | |
13488 | goto retry; | |
4ed9fb37 | 13489 | } |
4be07317 | 13490 | |
2bfb4627 | 13491 | if (ret) |
e694eb02 | 13492 | out: |
2bfb4627 | 13493 | drm_atomic_state_free(state); |
c0c36b94 CW |
13494 | } |
13495 | ||
25c5b266 DV |
13496 | #undef for_each_intel_crtc_masked |
13497 | ||
f6e5b160 | 13498 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
f6e5b160 | 13499 | .gamma_set = intel_crtc_gamma_set, |
74c090b1 | 13500 | .set_config = drm_atomic_helper_set_config, |
f6e5b160 CW |
13501 | .destroy = intel_crtc_destroy, |
13502 | .page_flip = intel_crtc_page_flip, | |
1356837e MR |
13503 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
13504 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
13505 | }; |
13506 | ||
5358901f DV |
13507 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
13508 | struct intel_shared_dpll *pll, | |
13509 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 13510 | { |
5358901f | 13511 | uint32_t val; |
ee7b9f93 | 13512 | |
f458ebbc | 13513 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
bd2bb1b9 PZ |
13514 | return false; |
13515 | ||
5358901f | 13516 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
13517 | hw_state->dpll = val; |
13518 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
13519 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
13520 | |
13521 | return val & DPLL_VCO_ENABLE; | |
13522 | } | |
13523 | ||
15bdd4cf DV |
13524 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
13525 | struct intel_shared_dpll *pll) | |
13526 | { | |
3e369b76 ACO |
13527 | I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0); |
13528 | I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1); | |
15bdd4cf DV |
13529 | } |
13530 | ||
e7b903d2 DV |
13531 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
13532 | struct intel_shared_dpll *pll) | |
13533 | { | |
e7b903d2 | 13534 | /* PCH refclock must be enabled first */ |
89eff4be | 13535 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 13536 | |
3e369b76 | 13537 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf DV |
13538 | |
13539 | /* Wait for the clocks to stabilize. */ | |
13540 | POSTING_READ(PCH_DPLL(pll->id)); | |
13541 | udelay(150); | |
13542 | ||
13543 | /* The pixel multiplier can only be updated once the | |
13544 | * DPLL is enabled and the clocks are stable. | |
13545 | * | |
13546 | * So write it again. | |
13547 | */ | |
3e369b76 | 13548 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf | 13549 | POSTING_READ(PCH_DPLL(pll->id)); |
e7b903d2 DV |
13550 | udelay(200); |
13551 | } | |
13552 | ||
13553 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
13554 | struct intel_shared_dpll *pll) | |
13555 | { | |
13556 | struct drm_device *dev = dev_priv->dev; | |
13557 | struct intel_crtc *crtc; | |
e7b903d2 DV |
13558 | |
13559 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 13560 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
13561 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
13562 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
13563 | } |
13564 | ||
15bdd4cf DV |
13565 | I915_WRITE(PCH_DPLL(pll->id), 0); |
13566 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
13567 | udelay(200); |
13568 | } | |
13569 | ||
46edb027 DV |
13570 | static char *ibx_pch_dpll_names[] = { |
13571 | "PCH DPLL A", | |
13572 | "PCH DPLL B", | |
13573 | }; | |
13574 | ||
7c74ade1 | 13575 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 13576 | { |
e7b903d2 | 13577 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
13578 | int i; |
13579 | ||
7c74ade1 | 13580 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 13581 | |
e72f9fbf | 13582 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
13583 | dev_priv->shared_dplls[i].id = i; |
13584 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 13585 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
13586 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
13587 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
13588 | dev_priv->shared_dplls[i].get_hw_state = |
13589 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
13590 | } |
13591 | } | |
13592 | ||
7c74ade1 DV |
13593 | static void intel_shared_dpll_init(struct drm_device *dev) |
13594 | { | |
e7b903d2 | 13595 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 | 13596 | |
9cd86933 DV |
13597 | if (HAS_DDI(dev)) |
13598 | intel_ddi_pll_init(dev); | |
13599 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7c74ade1 DV |
13600 | ibx_pch_dpll_init(dev); |
13601 | else | |
13602 | dev_priv->num_shared_dpll = 0; | |
13603 | ||
13604 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
13605 | } |
13606 | ||
6beb8c23 MR |
13607 | /** |
13608 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
13609 | * @plane: drm plane to prepare for | |
13610 | * @fb: framebuffer to prepare for presentation | |
13611 | * | |
13612 | * Prepares a framebuffer for usage on a display plane. Generally this | |
13613 | * involves pinning the underlying object and updating the frontbuffer tracking | |
13614 | * bits. Some older platforms need special physical address handling for | |
13615 | * cursor planes. | |
13616 | * | |
f935675f ML |
13617 | * Must be called with struct_mutex held. |
13618 | * | |
6beb8c23 MR |
13619 | * Returns 0 on success, negative error code on failure. |
13620 | */ | |
13621 | int | |
13622 | intel_prepare_plane_fb(struct drm_plane *plane, | |
d136dfee | 13623 | const struct drm_plane_state *new_state) |
465c120c MR |
13624 | { |
13625 | struct drm_device *dev = plane->dev; | |
844f9111 | 13626 | struct drm_framebuffer *fb = new_state->fb; |
6beb8c23 | 13627 | struct intel_plane *intel_plane = to_intel_plane(plane); |
6beb8c23 | 13628 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1ee49399 | 13629 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
6beb8c23 | 13630 | int ret = 0; |
465c120c | 13631 | |
1ee49399 | 13632 | if (!obj && !old_obj) |
465c120c MR |
13633 | return 0; |
13634 | ||
5008e874 ML |
13635 | if (old_obj) { |
13636 | struct drm_crtc_state *crtc_state = | |
13637 | drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc); | |
13638 | ||
13639 | /* Big Hammer, we also need to ensure that any pending | |
13640 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
13641 | * current scanout is retired before unpinning the old | |
13642 | * framebuffer. Note that we rely on userspace rendering | |
13643 | * into the buffer attached to the pipe they are waiting | |
13644 | * on. If not, userspace generates a GPU hang with IPEHR | |
13645 | * point to the MI_WAIT_FOR_EVENT. | |
13646 | * | |
13647 | * This should only fail upon a hung GPU, in which case we | |
13648 | * can safely continue. | |
13649 | */ | |
13650 | if (needs_modeset(crtc_state)) | |
13651 | ret = i915_gem_object_wait_rendering(old_obj, true); | |
13652 | ||
13653 | /* Swallow -EIO errors to allow updates during hw lockup. */ | |
13654 | if (ret && ret != -EIO) | |
f935675f | 13655 | return ret; |
5008e874 ML |
13656 | } |
13657 | ||
1ee49399 ML |
13658 | if (!obj) { |
13659 | ret = 0; | |
13660 | } else if (plane->type == DRM_PLANE_TYPE_CURSOR && | |
6beb8c23 MR |
13661 | INTEL_INFO(dev)->cursor_needs_physical) { |
13662 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
13663 | ret = i915_gem_object_attach_phys(obj, align); | |
13664 | if (ret) | |
13665 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
13666 | } else { | |
7580d774 | 13667 | ret = intel_pin_and_fence_fb_obj(plane, fb, new_state); |
6beb8c23 | 13668 | } |
465c120c | 13669 | |
7580d774 ML |
13670 | if (ret == 0) { |
13671 | if (obj) { | |
13672 | struct intel_plane_state *plane_state = | |
13673 | to_intel_plane_state(new_state); | |
13674 | ||
13675 | i915_gem_request_assign(&plane_state->wait_req, | |
13676 | obj->last_write_req); | |
13677 | } | |
13678 | ||
a9ff8714 | 13679 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); |
7580d774 | 13680 | } |
fdd508a6 | 13681 | |
6beb8c23 MR |
13682 | return ret; |
13683 | } | |
13684 | ||
38f3ce3a MR |
13685 | /** |
13686 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
13687 | * @plane: drm plane to clean up for | |
13688 | * @fb: old framebuffer that was on plane | |
13689 | * | |
13690 | * Cleans up a framebuffer that has just been removed from a plane. | |
f935675f ML |
13691 | * |
13692 | * Must be called with struct_mutex held. | |
38f3ce3a MR |
13693 | */ |
13694 | void | |
13695 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
d136dfee | 13696 | const struct drm_plane_state *old_state) |
38f3ce3a MR |
13697 | { |
13698 | struct drm_device *dev = plane->dev; | |
1ee49399 | 13699 | struct intel_plane *intel_plane = to_intel_plane(plane); |
7580d774 | 13700 | struct intel_plane_state *old_intel_state; |
1ee49399 ML |
13701 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb); |
13702 | struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb); | |
38f3ce3a | 13703 | |
7580d774 ML |
13704 | old_intel_state = to_intel_plane_state(old_state); |
13705 | ||
1ee49399 | 13706 | if (!obj && !old_obj) |
38f3ce3a MR |
13707 | return; |
13708 | ||
1ee49399 ML |
13709 | if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR || |
13710 | !INTEL_INFO(dev)->cursor_needs_physical)) | |
844f9111 | 13711 | intel_unpin_fb_obj(old_state->fb, old_state); |
1ee49399 ML |
13712 | |
13713 | /* prepare_fb aborted? */ | |
13714 | if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) || | |
13715 | (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit))) | |
13716 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); | |
7580d774 ML |
13717 | |
13718 | i915_gem_request_assign(&old_intel_state->wait_req, NULL); | |
13719 | ||
465c120c MR |
13720 | } |
13721 | ||
6156a456 CK |
13722 | int |
13723 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
13724 | { | |
13725 | int max_scale; | |
13726 | struct drm_device *dev; | |
13727 | struct drm_i915_private *dev_priv; | |
13728 | int crtc_clock, cdclk; | |
13729 | ||
13730 | if (!intel_crtc || !crtc_state) | |
13731 | return DRM_PLANE_HELPER_NO_SCALING; | |
13732 | ||
13733 | dev = intel_crtc->base.dev; | |
13734 | dev_priv = dev->dev_private; | |
13735 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; | |
27c329ed | 13736 | cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; |
6156a456 | 13737 | |
54bf1ce6 | 13738 | if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)) |
6156a456 CK |
13739 | return DRM_PLANE_HELPER_NO_SCALING; |
13740 | ||
13741 | /* | |
13742 | * skl max scale is lower of: | |
13743 | * close to 3 but not 3, -1 is for that purpose | |
13744 | * or | |
13745 | * cdclk/crtc_clock | |
13746 | */ | |
13747 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); | |
13748 | ||
13749 | return max_scale; | |
13750 | } | |
13751 | ||
465c120c | 13752 | static int |
3c692a41 | 13753 | intel_check_primary_plane(struct drm_plane *plane, |
061e4b8d | 13754 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
13755 | struct intel_plane_state *state) |
13756 | { | |
2b875c22 MR |
13757 | struct drm_crtc *crtc = state->base.crtc; |
13758 | struct drm_framebuffer *fb = state->base.fb; | |
6156a456 | 13759 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
13760 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
13761 | bool can_position = false; | |
465c120c | 13762 | |
061e4b8d ML |
13763 | /* use scaler when colorkey is not required */ |
13764 | if (INTEL_INFO(plane->dev)->gen >= 9 && | |
818ed961 | 13765 | state->ckey.flags == I915_SET_COLORKEY_NONE) { |
061e4b8d ML |
13766 | min_scale = 1; |
13767 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
d8106366 | 13768 | can_position = true; |
6156a456 | 13769 | } |
d8106366 | 13770 | |
061e4b8d ML |
13771 | return drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
13772 | &state->dst, &state->clip, | |
da20eabd ML |
13773 | min_scale, max_scale, |
13774 | can_position, true, | |
13775 | &state->visible); | |
14af293f GP |
13776 | } |
13777 | ||
13778 | static void | |
13779 | intel_commit_primary_plane(struct drm_plane *plane, | |
13780 | struct intel_plane_state *state) | |
13781 | { | |
2b875c22 MR |
13782 | struct drm_crtc *crtc = state->base.crtc; |
13783 | struct drm_framebuffer *fb = state->base.fb; | |
13784 | struct drm_device *dev = plane->dev; | |
14af293f | 13785 | struct drm_i915_private *dev_priv = dev->dev_private; |
14af293f | 13786 | |
ea2c67bb | 13787 | crtc = crtc ? crtc : plane->crtc; |
ccc759dc | 13788 | |
d4b08630 ML |
13789 | dev_priv->display.update_primary_plane(crtc, fb, |
13790 | state->src.x1 >> 16, | |
13791 | state->src.y1 >> 16); | |
465c120c MR |
13792 | } |
13793 | ||
a8ad0d8e ML |
13794 | static void |
13795 | intel_disable_primary_plane(struct drm_plane *plane, | |
7fabf5ef | 13796 | struct drm_crtc *crtc) |
a8ad0d8e ML |
13797 | { |
13798 | struct drm_device *dev = plane->dev; | |
13799 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13800 | ||
a8ad0d8e ML |
13801 | dev_priv->display.update_primary_plane(crtc, NULL, 0, 0); |
13802 | } | |
13803 | ||
613d2b27 ML |
13804 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
13805 | struct drm_crtc_state *old_crtc_state) | |
3c692a41 | 13806 | { |
32b7eeec | 13807 | struct drm_device *dev = crtc->dev; |
3c692a41 | 13808 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
bfd16b2a ML |
13809 | struct intel_crtc_state *old_intel_state = |
13810 | to_intel_crtc_state(old_crtc_state); | |
13811 | bool modeset = needs_modeset(crtc->state); | |
3c692a41 | 13812 | |
f015c551 | 13813 | if (intel_crtc->atomic.update_wm_pre) |
32b7eeec | 13814 | intel_update_watermarks(crtc); |
3c692a41 | 13815 | |
c34c9ee4 | 13816 | /* Perform vblank evasion around commit operation */ |
62852622 | 13817 | intel_pipe_update_start(intel_crtc); |
0583236e | 13818 | |
bfd16b2a ML |
13819 | if (modeset) |
13820 | return; | |
13821 | ||
13822 | if (to_intel_crtc_state(crtc->state)->update_pipe) | |
13823 | intel_update_pipe_config(intel_crtc, old_intel_state); | |
13824 | else if (INTEL_INFO(dev)->gen >= 9) | |
0583236e | 13825 | skl_detach_scalers(intel_crtc); |
32b7eeec MR |
13826 | } |
13827 | ||
613d2b27 ML |
13828 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, |
13829 | struct drm_crtc_state *old_crtc_state) | |
32b7eeec | 13830 | { |
32b7eeec | 13831 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
32b7eeec | 13832 | |
62852622 | 13833 | intel_pipe_update_end(intel_crtc); |
3c692a41 GP |
13834 | } |
13835 | ||
cf4c7c12 | 13836 | /** |
4a3b8769 MR |
13837 | * intel_plane_destroy - destroy a plane |
13838 | * @plane: plane to destroy | |
cf4c7c12 | 13839 | * |
4a3b8769 MR |
13840 | * Common destruction function for all types of planes (primary, cursor, |
13841 | * sprite). | |
cf4c7c12 | 13842 | */ |
4a3b8769 | 13843 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c MR |
13844 | { |
13845 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
13846 | drm_plane_cleanup(plane); | |
13847 | kfree(intel_plane); | |
13848 | } | |
13849 | ||
65a3fea0 | 13850 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
13851 | .update_plane = drm_atomic_helper_update_plane, |
13852 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 13853 | .destroy = intel_plane_destroy, |
c196e1d6 | 13854 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
13855 | .atomic_get_property = intel_plane_atomic_get_property, |
13856 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
13857 | .atomic_duplicate_state = intel_plane_duplicate_state, |
13858 | .atomic_destroy_state = intel_plane_destroy_state, | |
13859 | ||
465c120c MR |
13860 | }; |
13861 | ||
13862 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
13863 | int pipe) | |
13864 | { | |
13865 | struct intel_plane *primary; | |
8e7d688b | 13866 | struct intel_plane_state *state; |
465c120c | 13867 | const uint32_t *intel_primary_formats; |
45e3743a | 13868 | unsigned int num_formats; |
465c120c MR |
13869 | |
13870 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
13871 | if (primary == NULL) | |
13872 | return NULL; | |
13873 | ||
8e7d688b MR |
13874 | state = intel_create_plane_state(&primary->base); |
13875 | if (!state) { | |
ea2c67bb MR |
13876 | kfree(primary); |
13877 | return NULL; | |
13878 | } | |
8e7d688b | 13879 | primary->base.state = &state->base; |
ea2c67bb | 13880 | |
465c120c MR |
13881 | primary->can_scale = false; |
13882 | primary->max_downscale = 1; | |
6156a456 CK |
13883 | if (INTEL_INFO(dev)->gen >= 9) { |
13884 | primary->can_scale = true; | |
af99ceda | 13885 | state->scaler_id = -1; |
6156a456 | 13886 | } |
465c120c MR |
13887 | primary->pipe = pipe; |
13888 | primary->plane = pipe; | |
a9ff8714 | 13889 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 MR |
13890 | primary->check_plane = intel_check_primary_plane; |
13891 | primary->commit_plane = intel_commit_primary_plane; | |
a8ad0d8e | 13892 | primary->disable_plane = intel_disable_primary_plane; |
465c120c MR |
13893 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
13894 | primary->plane = !pipe; | |
13895 | ||
6c0fd451 DL |
13896 | if (INTEL_INFO(dev)->gen >= 9) { |
13897 | intel_primary_formats = skl_primary_formats; | |
13898 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
13899 | } else if (INTEL_INFO(dev)->gen >= 4) { | |
568db4f2 DL |
13900 | intel_primary_formats = i965_primary_formats; |
13901 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
6c0fd451 DL |
13902 | } else { |
13903 | intel_primary_formats = i8xx_primary_formats; | |
13904 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
465c120c MR |
13905 | } |
13906 | ||
13907 | drm_universal_plane_init(dev, &primary->base, 0, | |
65a3fea0 | 13908 | &intel_plane_funcs, |
465c120c MR |
13909 | intel_primary_formats, num_formats, |
13910 | DRM_PLANE_TYPE_PRIMARY); | |
48404c1e | 13911 | |
3b7a5119 SJ |
13912 | if (INTEL_INFO(dev)->gen >= 4) |
13913 | intel_create_rotation_property(dev, primary); | |
48404c1e | 13914 | |
ea2c67bb MR |
13915 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
13916 | ||
465c120c MR |
13917 | return &primary->base; |
13918 | } | |
13919 | ||
3b7a5119 SJ |
13920 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
13921 | { | |
13922 | if (!dev->mode_config.rotation_property) { | |
13923 | unsigned long flags = BIT(DRM_ROTATE_0) | | |
13924 | BIT(DRM_ROTATE_180); | |
13925 | ||
13926 | if (INTEL_INFO(dev)->gen >= 9) | |
13927 | flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); | |
13928 | ||
13929 | dev->mode_config.rotation_property = | |
13930 | drm_mode_create_rotation_property(dev, flags); | |
13931 | } | |
13932 | if (dev->mode_config.rotation_property) | |
13933 | drm_object_attach_property(&plane->base.base, | |
13934 | dev->mode_config.rotation_property, | |
13935 | plane->base.state->rotation); | |
13936 | } | |
13937 | ||
3d7d6510 | 13938 | static int |
852e787c | 13939 | intel_check_cursor_plane(struct drm_plane *plane, |
061e4b8d | 13940 | struct intel_crtc_state *crtc_state, |
852e787c | 13941 | struct intel_plane_state *state) |
3d7d6510 | 13942 | { |
061e4b8d | 13943 | struct drm_crtc *crtc = crtc_state->base.crtc; |
2b875c22 | 13944 | struct drm_framebuffer *fb = state->base.fb; |
757f9a3e | 13945 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
757f9a3e GP |
13946 | unsigned stride; |
13947 | int ret; | |
3d7d6510 | 13948 | |
061e4b8d ML |
13949 | ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
13950 | &state->dst, &state->clip, | |
3d7d6510 MR |
13951 | DRM_PLANE_HELPER_NO_SCALING, |
13952 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 13953 | true, true, &state->visible); |
757f9a3e GP |
13954 | if (ret) |
13955 | return ret; | |
13956 | ||
757f9a3e GP |
13957 | /* if we want to turn off the cursor ignore width and height */ |
13958 | if (!obj) | |
da20eabd | 13959 | return 0; |
757f9a3e | 13960 | |
757f9a3e | 13961 | /* Check for which cursor types we support */ |
061e4b8d | 13962 | if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) { |
ea2c67bb MR |
13963 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", |
13964 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
13965 | return -EINVAL; |
13966 | } | |
13967 | ||
ea2c67bb MR |
13968 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
13969 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
13970 | DRM_DEBUG_KMS("buffer is too small\n"); |
13971 | return -ENOMEM; | |
13972 | } | |
13973 | ||
3a656b54 | 13974 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e | 13975 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
da20eabd | 13976 | return -EINVAL; |
32b7eeec MR |
13977 | } |
13978 | ||
da20eabd | 13979 | return 0; |
852e787c | 13980 | } |
3d7d6510 | 13981 | |
a8ad0d8e ML |
13982 | static void |
13983 | intel_disable_cursor_plane(struct drm_plane *plane, | |
7fabf5ef | 13984 | struct drm_crtc *crtc) |
a8ad0d8e | 13985 | { |
a8ad0d8e ML |
13986 | intel_crtc_update_cursor(crtc, false); |
13987 | } | |
13988 | ||
f4a2cf29 | 13989 | static void |
852e787c GP |
13990 | intel_commit_cursor_plane(struct drm_plane *plane, |
13991 | struct intel_plane_state *state) | |
13992 | { | |
2b875c22 | 13993 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb MR |
13994 | struct drm_device *dev = plane->dev; |
13995 | struct intel_crtc *intel_crtc; | |
2b875c22 | 13996 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 13997 | uint32_t addr; |
852e787c | 13998 | |
ea2c67bb MR |
13999 | crtc = crtc ? crtc : plane->crtc; |
14000 | intel_crtc = to_intel_crtc(crtc); | |
14001 | ||
a912f12f GP |
14002 | if (intel_crtc->cursor_bo == obj) |
14003 | goto update; | |
4ed91096 | 14004 | |
f4a2cf29 | 14005 | if (!obj) |
a912f12f | 14006 | addr = 0; |
f4a2cf29 | 14007 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 14008 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 14009 | else |
a912f12f | 14010 | addr = obj->phys_handle->busaddr; |
852e787c | 14011 | |
a912f12f GP |
14012 | intel_crtc->cursor_addr = addr; |
14013 | intel_crtc->cursor_bo = obj; | |
852e787c | 14014 | |
302d19ac | 14015 | update: |
62852622 | 14016 | intel_crtc_update_cursor(crtc, state->visible); |
852e787c GP |
14017 | } |
14018 | ||
3d7d6510 MR |
14019 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
14020 | int pipe) | |
14021 | { | |
14022 | struct intel_plane *cursor; | |
8e7d688b | 14023 | struct intel_plane_state *state; |
3d7d6510 MR |
14024 | |
14025 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
14026 | if (cursor == NULL) | |
14027 | return NULL; | |
14028 | ||
8e7d688b MR |
14029 | state = intel_create_plane_state(&cursor->base); |
14030 | if (!state) { | |
ea2c67bb MR |
14031 | kfree(cursor); |
14032 | return NULL; | |
14033 | } | |
8e7d688b | 14034 | cursor->base.state = &state->base; |
ea2c67bb | 14035 | |
3d7d6510 MR |
14036 | cursor->can_scale = false; |
14037 | cursor->max_downscale = 1; | |
14038 | cursor->pipe = pipe; | |
14039 | cursor->plane = pipe; | |
a9ff8714 | 14040 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
c59cb179 MR |
14041 | cursor->check_plane = intel_check_cursor_plane; |
14042 | cursor->commit_plane = intel_commit_cursor_plane; | |
a8ad0d8e | 14043 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 MR |
14044 | |
14045 | drm_universal_plane_init(dev, &cursor->base, 0, | |
65a3fea0 | 14046 | &intel_plane_funcs, |
3d7d6510 MR |
14047 | intel_cursor_formats, |
14048 | ARRAY_SIZE(intel_cursor_formats), | |
14049 | DRM_PLANE_TYPE_CURSOR); | |
4398ad45 VS |
14050 | |
14051 | if (INTEL_INFO(dev)->gen >= 4) { | |
14052 | if (!dev->mode_config.rotation_property) | |
14053 | dev->mode_config.rotation_property = | |
14054 | drm_mode_create_rotation_property(dev, | |
14055 | BIT(DRM_ROTATE_0) | | |
14056 | BIT(DRM_ROTATE_180)); | |
14057 | if (dev->mode_config.rotation_property) | |
14058 | drm_object_attach_property(&cursor->base.base, | |
14059 | dev->mode_config.rotation_property, | |
8e7d688b | 14060 | state->base.rotation); |
4398ad45 VS |
14061 | } |
14062 | ||
af99ceda CK |
14063 | if (INTEL_INFO(dev)->gen >=9) |
14064 | state->scaler_id = -1; | |
14065 | ||
ea2c67bb MR |
14066 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
14067 | ||
3d7d6510 MR |
14068 | return &cursor->base; |
14069 | } | |
14070 | ||
549e2bfb CK |
14071 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
14072 | struct intel_crtc_state *crtc_state) | |
14073 | { | |
14074 | int i; | |
14075 | struct intel_scaler *intel_scaler; | |
14076 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; | |
14077 | ||
14078 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
14079 | intel_scaler = &scaler_state->scalers[i]; | |
14080 | intel_scaler->in_use = 0; | |
549e2bfb CK |
14081 | intel_scaler->mode = PS_SCALER_MODE_DYN; |
14082 | } | |
14083 | ||
14084 | scaler_state->scaler_id = -1; | |
14085 | } | |
14086 | ||
b358d0a6 | 14087 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 14088 | { |
fbee40df | 14089 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 14090 | struct intel_crtc *intel_crtc; |
f5de6e07 | 14091 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
14092 | struct drm_plane *primary = NULL; |
14093 | struct drm_plane *cursor = NULL; | |
465c120c | 14094 | int i, ret; |
79e53945 | 14095 | |
955382f3 | 14096 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
14097 | if (intel_crtc == NULL) |
14098 | return; | |
14099 | ||
f5de6e07 ACO |
14100 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
14101 | if (!crtc_state) | |
14102 | goto fail; | |
550acefd ACO |
14103 | intel_crtc->config = crtc_state; |
14104 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 14105 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 14106 | |
549e2bfb CK |
14107 | /* initialize shared scalers */ |
14108 | if (INTEL_INFO(dev)->gen >= 9) { | |
14109 | if (pipe == PIPE_C) | |
14110 | intel_crtc->num_scalers = 1; | |
14111 | else | |
14112 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
14113 | ||
14114 | skl_init_scalers(dev, intel_crtc, crtc_state); | |
14115 | } | |
14116 | ||
465c120c | 14117 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
14118 | if (!primary) |
14119 | goto fail; | |
14120 | ||
14121 | cursor = intel_cursor_plane_create(dev, pipe); | |
14122 | if (!cursor) | |
14123 | goto fail; | |
14124 | ||
465c120c | 14125 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
3d7d6510 MR |
14126 | cursor, &intel_crtc_funcs); |
14127 | if (ret) | |
14128 | goto fail; | |
79e53945 JB |
14129 | |
14130 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
14131 | for (i = 0; i < 256; i++) { |
14132 | intel_crtc->lut_r[i] = i; | |
14133 | intel_crtc->lut_g[i] = i; | |
14134 | intel_crtc->lut_b[i] = i; | |
14135 | } | |
14136 | ||
1f1c2e24 VS |
14137 | /* |
14138 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 14139 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 14140 | */ |
80824003 JB |
14141 | intel_crtc->pipe = pipe; |
14142 | intel_crtc->plane = pipe; | |
3a77c4c4 | 14143 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 14144 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 14145 | intel_crtc->plane = !pipe; |
80824003 JB |
14146 | } |
14147 | ||
4b0e333e CW |
14148 | intel_crtc->cursor_base = ~0; |
14149 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 14150 | intel_crtc->cursor_size = ~0; |
8d7849db | 14151 | |
852eb00d VS |
14152 | intel_crtc->wm.cxsr_allowed = true; |
14153 | ||
22fd0fab JB |
14154 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
14155 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
14156 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
14157 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
14158 | ||
79e53945 | 14159 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 DV |
14160 | |
14161 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); | |
3d7d6510 MR |
14162 | return; |
14163 | ||
14164 | fail: | |
14165 | if (primary) | |
14166 | drm_plane_cleanup(primary); | |
14167 | if (cursor) | |
14168 | drm_plane_cleanup(cursor); | |
f5de6e07 | 14169 | kfree(crtc_state); |
3d7d6510 | 14170 | kfree(intel_crtc); |
79e53945 JB |
14171 | } |
14172 | ||
752aa88a JB |
14173 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
14174 | { | |
14175 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 14176 | struct drm_device *dev = connector->base.dev; |
752aa88a | 14177 | |
51fd371b | 14178 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 14179 | |
d3babd3f | 14180 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
14181 | return INVALID_PIPE; |
14182 | ||
14183 | return to_intel_crtc(encoder->crtc)->pipe; | |
14184 | } | |
14185 | ||
08d7b3d1 | 14186 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 14187 | struct drm_file *file) |
08d7b3d1 | 14188 | { |
08d7b3d1 | 14189 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 14190 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 14191 | struct intel_crtc *crtc; |
08d7b3d1 | 14192 | |
7707e653 | 14193 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 14194 | |
7707e653 | 14195 | if (!drmmode_crtc) { |
08d7b3d1 | 14196 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 14197 | return -ENOENT; |
08d7b3d1 CW |
14198 | } |
14199 | ||
7707e653 | 14200 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 14201 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 14202 | |
c05422d5 | 14203 | return 0; |
08d7b3d1 CW |
14204 | } |
14205 | ||
66a9278e | 14206 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 14207 | { |
66a9278e DV |
14208 | struct drm_device *dev = encoder->base.dev; |
14209 | struct intel_encoder *source_encoder; | |
79e53945 | 14210 | int index_mask = 0; |
79e53945 JB |
14211 | int entry = 0; |
14212 | ||
b2784e15 | 14213 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 14214 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
14215 | index_mask |= (1 << entry); |
14216 | ||
79e53945 JB |
14217 | entry++; |
14218 | } | |
4ef69c7a | 14219 | |
79e53945 JB |
14220 | return index_mask; |
14221 | } | |
14222 | ||
4d302442 CW |
14223 | static bool has_edp_a(struct drm_device *dev) |
14224 | { | |
14225 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14226 | ||
14227 | if (!IS_MOBILE(dev)) | |
14228 | return false; | |
14229 | ||
14230 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
14231 | return false; | |
14232 | ||
e3589908 | 14233 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
14234 | return false; |
14235 | ||
14236 | return true; | |
14237 | } | |
14238 | ||
84b4e042 JB |
14239 | static bool intel_crt_present(struct drm_device *dev) |
14240 | { | |
14241 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14242 | ||
884497ed DL |
14243 | if (INTEL_INFO(dev)->gen >= 9) |
14244 | return false; | |
14245 | ||
cf404ce4 | 14246 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
14247 | return false; |
14248 | ||
14249 | if (IS_CHERRYVIEW(dev)) | |
14250 | return false; | |
14251 | ||
14252 | if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support) | |
14253 | return false; | |
14254 | ||
14255 | return true; | |
14256 | } | |
14257 | ||
79e53945 JB |
14258 | static void intel_setup_outputs(struct drm_device *dev) |
14259 | { | |
725e30ad | 14260 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 14261 | struct intel_encoder *encoder; |
cb0953d7 | 14262 | bool dpd_is_edp = false; |
79e53945 | 14263 | |
c9093354 | 14264 | intel_lvds_init(dev); |
79e53945 | 14265 | |
84b4e042 | 14266 | if (intel_crt_present(dev)) |
79935fca | 14267 | intel_crt_init(dev); |
cb0953d7 | 14268 | |
c776eb2e VK |
14269 | if (IS_BROXTON(dev)) { |
14270 | /* | |
14271 | * FIXME: Broxton doesn't support port detection via the | |
14272 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
14273 | * detect the ports. | |
14274 | */ | |
14275 | intel_ddi_init(dev, PORT_A); | |
14276 | intel_ddi_init(dev, PORT_B); | |
14277 | intel_ddi_init(dev, PORT_C); | |
14278 | } else if (HAS_DDI(dev)) { | |
0e72a5b5 ED |
14279 | int found; |
14280 | ||
de31facd JB |
14281 | /* |
14282 | * Haswell uses DDI functions to detect digital outputs. | |
14283 | * On SKL pre-D0 the strap isn't connected, so we assume | |
14284 | * it's there. | |
14285 | */ | |
77179400 | 14286 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 14287 | /* WaIgnoreDDIAStrap: skl */ |
ef11bdb3 | 14288 | if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
0e72a5b5 ED |
14289 | intel_ddi_init(dev, PORT_A); |
14290 | ||
14291 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
14292 | * register */ | |
14293 | found = I915_READ(SFUSE_STRAP); | |
14294 | ||
14295 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
14296 | intel_ddi_init(dev, PORT_B); | |
14297 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
14298 | intel_ddi_init(dev, PORT_C); | |
14299 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
14300 | intel_ddi_init(dev, PORT_D); | |
2800e4c2 RV |
14301 | /* |
14302 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
14303 | */ | |
ef11bdb3 | 14304 | if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && |
2800e4c2 RV |
14305 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
14306 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
14307 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
14308 | intel_ddi_init(dev, PORT_E); | |
14309 | ||
0e72a5b5 | 14310 | } else if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 14311 | int found; |
5d8a7752 | 14312 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
14313 | |
14314 | if (has_edp_a(dev)) | |
14315 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 14316 | |
dc0fa718 | 14317 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 14318 | /* PCH SDVOB multiplex with HDMIB */ |
2a5c0832 | 14319 | found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B); |
30ad48b7 | 14320 | if (!found) |
e2debe91 | 14321 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 14322 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 14323 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
14324 | } |
14325 | ||
dc0fa718 | 14326 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 14327 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 14328 | |
dc0fa718 | 14329 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 14330 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 14331 | |
5eb08b69 | 14332 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 14333 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 14334 | |
270b3042 | 14335 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 14336 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 14337 | } else if (IS_VALLEYVIEW(dev)) { |
e17ac6db VS |
14338 | /* |
14339 | * The DP_DETECTED bit is the latched state of the DDC | |
14340 | * SDA pin at boot. However since eDP doesn't require DDC | |
14341 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
14342 | * eDP ports may have been muxed to an alternate function. | |
14343 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
14344 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
14345 | * detect eDP ports. | |
14346 | */ | |
e66eb81d | 14347 | if (I915_READ(VLV_HDMIB) & SDVO_DETECTED && |
d2182a66 | 14348 | !intel_dp_is_edp(dev, PORT_B)) |
e66eb81d VS |
14349 | intel_hdmi_init(dev, VLV_HDMIB, PORT_B); |
14350 | if (I915_READ(VLV_DP_B) & DP_DETECTED || | |
e17ac6db | 14351 | intel_dp_is_edp(dev, PORT_B)) |
e66eb81d | 14352 | intel_dp_init(dev, VLV_DP_B, PORT_B); |
585a94b8 | 14353 | |
e66eb81d | 14354 | if (I915_READ(VLV_HDMIC) & SDVO_DETECTED && |
d2182a66 | 14355 | !intel_dp_is_edp(dev, PORT_C)) |
e66eb81d VS |
14356 | intel_hdmi_init(dev, VLV_HDMIC, PORT_C); |
14357 | if (I915_READ(VLV_DP_C) & DP_DETECTED || | |
e17ac6db | 14358 | intel_dp_is_edp(dev, PORT_C)) |
e66eb81d | 14359 | intel_dp_init(dev, VLV_DP_C, PORT_C); |
19c03924 | 14360 | |
9418c1f1 | 14361 | if (IS_CHERRYVIEW(dev)) { |
e17ac6db | 14362 | /* eDP not supported on port D, so don't check VBT */ |
e66eb81d VS |
14363 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED) |
14364 | intel_hdmi_init(dev, CHV_HDMID, PORT_D); | |
14365 | if (I915_READ(CHV_DP_D) & DP_DETECTED) | |
14366 | intel_dp_init(dev, CHV_DP_D, PORT_D); | |
9418c1f1 VS |
14367 | } |
14368 | ||
3cfca973 | 14369 | intel_dsi_init(dev); |
09da55dc | 14370 | } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) { |
27185ae1 | 14371 | bool found = false; |
7d57382e | 14372 | |
e2debe91 | 14373 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14374 | DRM_DEBUG_KMS("probing SDVOB\n"); |
2a5c0832 | 14375 | found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B); |
3fec3d2f | 14376 | if (!found && IS_G4X(dev)) { |
b01f2c3a | 14377 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
e2debe91 | 14378 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 14379 | } |
27185ae1 | 14380 | |
3fec3d2f | 14381 | if (!found && IS_G4X(dev)) |
ab9d7c30 | 14382 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 14383 | } |
13520b05 KH |
14384 | |
14385 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 14386 | |
e2debe91 | 14387 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14388 | DRM_DEBUG_KMS("probing SDVOC\n"); |
2a5c0832 | 14389 | found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C); |
b01f2c3a | 14390 | } |
27185ae1 | 14391 | |
e2debe91 | 14392 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 14393 | |
3fec3d2f | 14394 | if (IS_G4X(dev)) { |
b01f2c3a | 14395 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
e2debe91 | 14396 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 14397 | } |
3fec3d2f | 14398 | if (IS_G4X(dev)) |
ab9d7c30 | 14399 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 14400 | } |
27185ae1 | 14401 | |
3fec3d2f | 14402 | if (IS_G4X(dev) && |
e7281eab | 14403 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 14404 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 14405 | } else if (IS_GEN2(dev)) |
79e53945 JB |
14406 | intel_dvo_init(dev); |
14407 | ||
103a196f | 14408 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
14409 | intel_tv_init(dev); |
14410 | ||
0bc12bcb | 14411 | intel_psr_init(dev); |
7c8f8a70 | 14412 | |
b2784e15 | 14413 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
14414 | encoder->base.possible_crtcs = encoder->crtc_mask; |
14415 | encoder->base.possible_clones = | |
66a9278e | 14416 | intel_encoder_clones(encoder); |
79e53945 | 14417 | } |
47356eb6 | 14418 | |
dde86e2d | 14419 | intel_init_pch_refclk(dev); |
270b3042 DV |
14420 | |
14421 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
14422 | } |
14423 | ||
14424 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
14425 | { | |
60a5ca01 | 14426 | struct drm_device *dev = fb->dev; |
79e53945 | 14427 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 14428 | |
ef2d633e | 14429 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 14430 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 14431 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
14432 | drm_gem_object_unreference(&intel_fb->obj->base); |
14433 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
14434 | kfree(intel_fb); |
14435 | } | |
14436 | ||
14437 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 14438 | struct drm_file *file, |
79e53945 JB |
14439 | unsigned int *handle) |
14440 | { | |
14441 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 14442 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 14443 | |
cc917ab4 CW |
14444 | if (obj->userptr.mm) { |
14445 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); | |
14446 | return -EINVAL; | |
14447 | } | |
14448 | ||
05394f39 | 14449 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
14450 | } |
14451 | ||
86c98588 RV |
14452 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
14453 | struct drm_file *file, | |
14454 | unsigned flags, unsigned color, | |
14455 | struct drm_clip_rect *clips, | |
14456 | unsigned num_clips) | |
14457 | { | |
14458 | struct drm_device *dev = fb->dev; | |
14459 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
14460 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
14461 | ||
14462 | mutex_lock(&dev->struct_mutex); | |
74b4ea1e | 14463 | intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); |
86c98588 RV |
14464 | mutex_unlock(&dev->struct_mutex); |
14465 | ||
14466 | return 0; | |
14467 | } | |
14468 | ||
79e53945 JB |
14469 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
14470 | .destroy = intel_user_framebuffer_destroy, | |
14471 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 14472 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
14473 | }; |
14474 | ||
b321803d DL |
14475 | static |
14476 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
14477 | uint32_t pixel_format) | |
14478 | { | |
14479 | u32 gen = INTEL_INFO(dev)->gen; | |
14480 | ||
14481 | if (gen >= 9) { | |
14482 | /* "The stride in bytes must not exceed the of the size of 8K | |
14483 | * pixels and 32K bytes." | |
14484 | */ | |
14485 | return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768); | |
14486 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) { | |
14487 | return 32*1024; | |
14488 | } else if (gen >= 4) { | |
14489 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14490 | return 16*1024; | |
14491 | else | |
14492 | return 32*1024; | |
14493 | } else if (gen >= 3) { | |
14494 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14495 | return 8*1024; | |
14496 | else | |
14497 | return 16*1024; | |
14498 | } else { | |
14499 | /* XXX DSPC is limited to 4k tiled */ | |
14500 | return 8*1024; | |
14501 | } | |
14502 | } | |
14503 | ||
b5ea642a DV |
14504 | static int intel_framebuffer_init(struct drm_device *dev, |
14505 | struct intel_framebuffer *intel_fb, | |
14506 | struct drm_mode_fb_cmd2 *mode_cmd, | |
14507 | struct drm_i915_gem_object *obj) | |
79e53945 | 14508 | { |
6761dd31 | 14509 | unsigned int aligned_height; |
79e53945 | 14510 | int ret; |
b321803d | 14511 | u32 pitch_limit, stride_alignment; |
79e53945 | 14512 | |
dd4916c5 DV |
14513 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
14514 | ||
2a80eada DV |
14515 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
14516 | /* Enforce that fb modifier and tiling mode match, but only for | |
14517 | * X-tiled. This is needed for FBC. */ | |
14518 | if (!!(obj->tiling_mode == I915_TILING_X) != | |
14519 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { | |
14520 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
14521 | return -EINVAL; | |
14522 | } | |
14523 | } else { | |
14524 | if (obj->tiling_mode == I915_TILING_X) | |
14525 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
14526 | else if (obj->tiling_mode == I915_TILING_Y) { | |
14527 | DRM_DEBUG("No Y tiling for legacy addfb\n"); | |
14528 | return -EINVAL; | |
14529 | } | |
14530 | } | |
14531 | ||
9a8f0a12 TU |
14532 | /* Passed in modifier sanity checking. */ |
14533 | switch (mode_cmd->modifier[0]) { | |
14534 | case I915_FORMAT_MOD_Y_TILED: | |
14535 | case I915_FORMAT_MOD_Yf_TILED: | |
14536 | if (INTEL_INFO(dev)->gen < 9) { | |
14537 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
14538 | mode_cmd->modifier[0]); | |
14539 | return -EINVAL; | |
14540 | } | |
14541 | case DRM_FORMAT_MOD_NONE: | |
14542 | case I915_FORMAT_MOD_X_TILED: | |
14543 | break; | |
14544 | default: | |
c0f40428 JB |
14545 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
14546 | mode_cmd->modifier[0]); | |
57cd6508 | 14547 | return -EINVAL; |
c16ed4be | 14548 | } |
57cd6508 | 14549 | |
b321803d DL |
14550 | stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0], |
14551 | mode_cmd->pixel_format); | |
14552 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
14553 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
14554 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 14555 | return -EINVAL; |
c16ed4be | 14556 | } |
57cd6508 | 14557 | |
b321803d DL |
14558 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
14559 | mode_cmd->pixel_format); | |
a35cdaa0 | 14560 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
14561 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
14562 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 14563 | "tiled" : "linear", |
a35cdaa0 | 14564 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 14565 | return -EINVAL; |
c16ed4be | 14566 | } |
5d7bd705 | 14567 | |
2a80eada | 14568 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
c16ed4be CW |
14569 | mode_cmd->pitches[0] != obj->stride) { |
14570 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
14571 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 14572 | return -EINVAL; |
c16ed4be | 14573 | } |
5d7bd705 | 14574 | |
57779d06 | 14575 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 14576 | switch (mode_cmd->pixel_format) { |
57779d06 | 14577 | case DRM_FORMAT_C8: |
04b3924d VS |
14578 | case DRM_FORMAT_RGB565: |
14579 | case DRM_FORMAT_XRGB8888: | |
14580 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
14581 | break; |
14582 | case DRM_FORMAT_XRGB1555: | |
c16ed4be | 14583 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
14584 | DRM_DEBUG("unsupported pixel format: %s\n", |
14585 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14586 | return -EINVAL; |
c16ed4be | 14587 | } |
57779d06 | 14588 | break; |
57779d06 | 14589 | case DRM_FORMAT_ABGR8888: |
6c0fd451 DL |
14590 | if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) { |
14591 | DRM_DEBUG("unsupported pixel format: %s\n", | |
14592 | drm_get_format_name(mode_cmd->pixel_format)); | |
14593 | return -EINVAL; | |
14594 | } | |
14595 | break; | |
14596 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 14597 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 14598 | case DRM_FORMAT_XBGR2101010: |
c16ed4be | 14599 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
14600 | DRM_DEBUG("unsupported pixel format: %s\n", |
14601 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14602 | return -EINVAL; |
c16ed4be | 14603 | } |
b5626747 | 14604 | break; |
7531208b DL |
14605 | case DRM_FORMAT_ABGR2101010: |
14606 | if (!IS_VALLEYVIEW(dev)) { | |
14607 | DRM_DEBUG("unsupported pixel format: %s\n", | |
14608 | drm_get_format_name(mode_cmd->pixel_format)); | |
14609 | return -EINVAL; | |
14610 | } | |
14611 | break; | |
04b3924d VS |
14612 | case DRM_FORMAT_YUYV: |
14613 | case DRM_FORMAT_UYVY: | |
14614 | case DRM_FORMAT_YVYU: | |
14615 | case DRM_FORMAT_VYUY: | |
c16ed4be | 14616 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
14617 | DRM_DEBUG("unsupported pixel format: %s\n", |
14618 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14619 | return -EINVAL; |
c16ed4be | 14620 | } |
57cd6508 CW |
14621 | break; |
14622 | default: | |
4ee62c76 VS |
14623 | DRM_DEBUG("unsupported pixel format: %s\n", |
14624 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
14625 | return -EINVAL; |
14626 | } | |
14627 | ||
90f9a336 VS |
14628 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
14629 | if (mode_cmd->offsets[0] != 0) | |
14630 | return -EINVAL; | |
14631 | ||
ec2c981e | 14632 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
091df6cb DV |
14633 | mode_cmd->pixel_format, |
14634 | mode_cmd->modifier[0]); | |
53155c0a DV |
14635 | /* FIXME drm helper for size checks (especially planar formats)? */ |
14636 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
14637 | return -EINVAL; | |
14638 | ||
c7d73f6a DV |
14639 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
14640 | intel_fb->obj = obj; | |
80075d49 | 14641 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 14642 | |
79e53945 JB |
14643 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
14644 | if (ret) { | |
14645 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
14646 | return ret; | |
14647 | } | |
14648 | ||
79e53945 JB |
14649 | return 0; |
14650 | } | |
14651 | ||
79e53945 JB |
14652 | static struct drm_framebuffer * |
14653 | intel_user_framebuffer_create(struct drm_device *dev, | |
14654 | struct drm_file *filp, | |
76dc3769 | 14655 | struct drm_mode_fb_cmd2 *user_mode_cmd) |
79e53945 | 14656 | { |
dcb1394e | 14657 | struct drm_framebuffer *fb; |
05394f39 | 14658 | struct drm_i915_gem_object *obj; |
76dc3769 | 14659 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
79e53945 | 14660 | |
308e5bcb | 14661 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
76dc3769 | 14662 | mode_cmd.handles[0])); |
c8725226 | 14663 | if (&obj->base == NULL) |
cce13ff7 | 14664 | return ERR_PTR(-ENOENT); |
79e53945 | 14665 | |
92907cbb | 14666 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
dcb1394e LW |
14667 | if (IS_ERR(fb)) |
14668 | drm_gem_object_unreference_unlocked(&obj->base); | |
14669 | ||
14670 | return fb; | |
79e53945 JB |
14671 | } |
14672 | ||
0695726e | 14673 | #ifndef CONFIG_DRM_FBDEV_EMULATION |
0632fef6 | 14674 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
14675 | { |
14676 | } | |
14677 | #endif | |
14678 | ||
79e53945 | 14679 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 14680 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 14681 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
14682 | .atomic_check = intel_atomic_check, |
14683 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
14684 | .atomic_state_alloc = intel_atomic_state_alloc, |
14685 | .atomic_state_clear = intel_atomic_state_clear, | |
79e53945 JB |
14686 | }; |
14687 | ||
e70236a8 JB |
14688 | /* Set up chip specific display functions */ |
14689 | static void intel_init_display(struct drm_device *dev) | |
14690 | { | |
14691 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14692 | ||
ee9300bb DV |
14693 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
14694 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
14695 | else if (IS_CHERRYVIEW(dev)) |
14696 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
14697 | else if (IS_VALLEYVIEW(dev)) |
14698 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
14699 | else if (IS_PINEVIEW(dev)) | |
14700 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
14701 | else | |
14702 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
14703 | ||
bc8d7dff DL |
14704 | if (INTEL_INFO(dev)->gen >= 9) { |
14705 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; | |
5724dbd1 DL |
14706 | dev_priv->display.get_initial_plane_config = |
14707 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
14708 | dev_priv->display.crtc_compute_clock = |
14709 | haswell_crtc_compute_clock; | |
14710 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
14711 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
bc8d7dff DL |
14712 | dev_priv->display.update_primary_plane = |
14713 | skylake_update_primary_plane; | |
14714 | } else if (HAS_DDI(dev)) { | |
0e8ffe1b | 14715 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14716 | dev_priv->display.get_initial_plane_config = |
14717 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
14718 | dev_priv->display.crtc_compute_clock = |
14719 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
14720 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
14721 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
bc8d7dff DL |
14722 | dev_priv->display.update_primary_plane = |
14723 | ironlake_update_primary_plane; | |
09b4ddf9 | 14724 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 14725 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
14726 | dev_priv->display.get_initial_plane_config = |
14727 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
14728 | dev_priv->display.crtc_compute_clock = |
14729 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
14730 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
14731 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
262ca2b0 MR |
14732 | dev_priv->display.update_primary_plane = |
14733 | ironlake_update_primary_plane; | |
89b667f8 JB |
14734 | } else if (IS_VALLEYVIEW(dev)) { |
14735 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
5724dbd1 DL |
14736 | dev_priv->display.get_initial_plane_config = |
14737 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14738 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
89b667f8 JB |
14739 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
14740 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
262ca2b0 MR |
14741 | dev_priv->display.update_primary_plane = |
14742 | i9xx_update_primary_plane; | |
f564048e | 14743 | } else { |
0e8ffe1b | 14744 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14745 | dev_priv->display.get_initial_plane_config = |
14746 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14747 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
14748 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
14749 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
262ca2b0 MR |
14750 | dev_priv->display.update_primary_plane = |
14751 | i9xx_update_primary_plane; | |
f564048e | 14752 | } |
e70236a8 | 14753 | |
e70236a8 | 14754 | /* Returns the core display clock speed */ |
ef11bdb3 | 14755 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
1652d19e VS |
14756 | dev_priv->display.get_display_clock_speed = |
14757 | skylake_get_display_clock_speed; | |
acd3f3d3 BP |
14758 | else if (IS_BROXTON(dev)) |
14759 | dev_priv->display.get_display_clock_speed = | |
14760 | broxton_get_display_clock_speed; | |
1652d19e VS |
14761 | else if (IS_BROADWELL(dev)) |
14762 | dev_priv->display.get_display_clock_speed = | |
14763 | broadwell_get_display_clock_speed; | |
14764 | else if (IS_HASWELL(dev)) | |
14765 | dev_priv->display.get_display_clock_speed = | |
14766 | haswell_get_display_clock_speed; | |
14767 | else if (IS_VALLEYVIEW(dev)) | |
25eb05fc JB |
14768 | dev_priv->display.get_display_clock_speed = |
14769 | valleyview_get_display_clock_speed; | |
b37a6434 VS |
14770 | else if (IS_GEN5(dev)) |
14771 | dev_priv->display.get_display_clock_speed = | |
14772 | ilk_get_display_clock_speed; | |
a7c66cd8 | 14773 | else if (IS_I945G(dev) || IS_BROADWATER(dev) || |
34edce2f | 14774 | IS_GEN6(dev) || IS_IVYBRIDGE(dev)) |
e70236a8 JB |
14775 | dev_priv->display.get_display_clock_speed = |
14776 | i945_get_display_clock_speed; | |
34edce2f VS |
14777 | else if (IS_GM45(dev)) |
14778 | dev_priv->display.get_display_clock_speed = | |
14779 | gm45_get_display_clock_speed; | |
14780 | else if (IS_CRESTLINE(dev)) | |
14781 | dev_priv->display.get_display_clock_speed = | |
14782 | i965gm_get_display_clock_speed; | |
14783 | else if (IS_PINEVIEW(dev)) | |
14784 | dev_priv->display.get_display_clock_speed = | |
14785 | pnv_get_display_clock_speed; | |
14786 | else if (IS_G33(dev) || IS_G4X(dev)) | |
14787 | dev_priv->display.get_display_clock_speed = | |
14788 | g33_get_display_clock_speed; | |
e70236a8 JB |
14789 | else if (IS_I915G(dev)) |
14790 | dev_priv->display.get_display_clock_speed = | |
14791 | i915_get_display_clock_speed; | |
257a7ffc | 14792 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
14793 | dev_priv->display.get_display_clock_speed = |
14794 | i9xx_misc_get_display_clock_speed; | |
257a7ffc DV |
14795 | else if (IS_PINEVIEW(dev)) |
14796 | dev_priv->display.get_display_clock_speed = | |
14797 | pnv_get_display_clock_speed; | |
e70236a8 JB |
14798 | else if (IS_I915GM(dev)) |
14799 | dev_priv->display.get_display_clock_speed = | |
14800 | i915gm_get_display_clock_speed; | |
14801 | else if (IS_I865G(dev)) | |
14802 | dev_priv->display.get_display_clock_speed = | |
14803 | i865_get_display_clock_speed; | |
f0f8a9ce | 14804 | else if (IS_I85X(dev)) |
e70236a8 | 14805 | dev_priv->display.get_display_clock_speed = |
1b1d2716 | 14806 | i85x_get_display_clock_speed; |
623e01e5 VS |
14807 | else { /* 830 */ |
14808 | WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n"); | |
e70236a8 JB |
14809 | dev_priv->display.get_display_clock_speed = |
14810 | i830_get_display_clock_speed; | |
623e01e5 | 14811 | } |
e70236a8 | 14812 | |
7c10a2b5 | 14813 | if (IS_GEN5(dev)) { |
3bb11b53 | 14814 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
3bb11b53 SJ |
14815 | } else if (IS_GEN6(dev)) { |
14816 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; | |
3bb11b53 SJ |
14817 | } else if (IS_IVYBRIDGE(dev)) { |
14818 | /* FIXME: detect B0+ stepping and use auto training */ | |
14819 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
059b2fe9 | 14820 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
3bb11b53 | 14821 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
27c329ed ML |
14822 | if (IS_BROADWELL(dev)) { |
14823 | dev_priv->display.modeset_commit_cdclk = | |
14824 | broadwell_modeset_commit_cdclk; | |
14825 | dev_priv->display.modeset_calc_cdclk = | |
14826 | broadwell_modeset_calc_cdclk; | |
14827 | } | |
30a970c6 | 14828 | } else if (IS_VALLEYVIEW(dev)) { |
27c329ed ML |
14829 | dev_priv->display.modeset_commit_cdclk = |
14830 | valleyview_modeset_commit_cdclk; | |
14831 | dev_priv->display.modeset_calc_cdclk = | |
14832 | valleyview_modeset_calc_cdclk; | |
f8437dd1 | 14833 | } else if (IS_BROXTON(dev)) { |
27c329ed ML |
14834 | dev_priv->display.modeset_commit_cdclk = |
14835 | broxton_modeset_commit_cdclk; | |
14836 | dev_priv->display.modeset_calc_cdclk = | |
14837 | broxton_modeset_calc_cdclk; | |
e70236a8 | 14838 | } |
8c9f3aaf | 14839 | |
8c9f3aaf JB |
14840 | switch (INTEL_INFO(dev)->gen) { |
14841 | case 2: | |
14842 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
14843 | break; | |
14844 | ||
14845 | case 3: | |
14846 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
14847 | break; | |
14848 | ||
14849 | case 4: | |
14850 | case 5: | |
14851 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
14852 | break; | |
14853 | ||
14854 | case 6: | |
14855 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
14856 | break; | |
7c9017e5 | 14857 | case 7: |
4e0bbc31 | 14858 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
14859 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
14860 | break; | |
830c81db | 14861 | case 9: |
ba343e02 TU |
14862 | /* Drop through - unsupported since execlist only. */ |
14863 | default: | |
14864 | /* Default just returns -ENODEV to indicate unsupported */ | |
14865 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8c9f3aaf | 14866 | } |
7bd688cd | 14867 | |
e39b999a | 14868 | mutex_init(&dev_priv->pps_mutex); |
e70236a8 JB |
14869 | } |
14870 | ||
b690e96c JB |
14871 | /* |
14872 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
14873 | * resume, or other times. This quirk makes sure that's the case for | |
14874 | * affected systems. | |
14875 | */ | |
0206e353 | 14876 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
14877 | { |
14878 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14879 | ||
14880 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 14881 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
14882 | } |
14883 | ||
b6b5d049 VS |
14884 | static void quirk_pipeb_force(struct drm_device *dev) |
14885 | { | |
14886 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14887 | ||
14888 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
14889 | DRM_INFO("applying pipe b force quirk\n"); | |
14890 | } | |
14891 | ||
435793df KP |
14892 | /* |
14893 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
14894 | */ | |
14895 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
14896 | { | |
14897 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14898 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 14899 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
14900 | } |
14901 | ||
4dca20ef | 14902 | /* |
5a15ab5b CE |
14903 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
14904 | * brightness value | |
4dca20ef CE |
14905 | */ |
14906 | static void quirk_invert_brightness(struct drm_device *dev) | |
14907 | { | |
14908 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14909 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 14910 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
14911 | } |
14912 | ||
9c72cc6f SD |
14913 | /* Some VBT's incorrectly indicate no backlight is present */ |
14914 | static void quirk_backlight_present(struct drm_device *dev) | |
14915 | { | |
14916 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14917 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
14918 | DRM_INFO("applying backlight present quirk\n"); | |
14919 | } | |
14920 | ||
b690e96c JB |
14921 | struct intel_quirk { |
14922 | int device; | |
14923 | int subsystem_vendor; | |
14924 | int subsystem_device; | |
14925 | void (*hook)(struct drm_device *dev); | |
14926 | }; | |
14927 | ||
5f85f176 EE |
14928 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
14929 | struct intel_dmi_quirk { | |
14930 | void (*hook)(struct drm_device *dev); | |
14931 | const struct dmi_system_id (*dmi_id_list)[]; | |
14932 | }; | |
14933 | ||
14934 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
14935 | { | |
14936 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
14937 | return 1; | |
14938 | } | |
14939 | ||
14940 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
14941 | { | |
14942 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
14943 | { | |
14944 | .callback = intel_dmi_reverse_brightness, | |
14945 | .ident = "NCR Corporation", | |
14946 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
14947 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
14948 | }, | |
14949 | }, | |
14950 | { } /* terminating entry */ | |
14951 | }, | |
14952 | .hook = quirk_invert_brightness, | |
14953 | }, | |
14954 | }; | |
14955 | ||
c43b5634 | 14956 | static struct intel_quirk intel_quirks[] = { |
b690e96c JB |
14957 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
14958 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
14959 | ||
b690e96c JB |
14960 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
14961 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
14962 | ||
5f080c0f VS |
14963 | /* 830 needs to leave pipe A & dpll A up */ |
14964 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
14965 | ||
b6b5d049 VS |
14966 | /* 830 needs to leave pipe B & dpll B up */ |
14967 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
14968 | ||
435793df KP |
14969 | /* Lenovo U160 cannot use SSC on LVDS */ |
14970 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
14971 | |
14972 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
14973 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 14974 | |
be505f64 AH |
14975 | /* Acer Aspire 5734Z must invert backlight brightness */ |
14976 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
14977 | ||
14978 | /* Acer/eMachines G725 */ | |
14979 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
14980 | ||
14981 | /* Acer/eMachines e725 */ | |
14982 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
14983 | ||
14984 | /* Acer/Packard Bell NCL20 */ | |
14985 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
14986 | ||
14987 | /* Acer Aspire 4736Z */ | |
14988 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
14989 | |
14990 | /* Acer Aspire 5336 */ | |
14991 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
14992 | |
14993 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
14994 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 14995 | |
dfb3d47b SD |
14996 | /* Acer C720 Chromebook (Core i3 4005U) */ |
14997 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
14998 | ||
b2a9601c | 14999 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
15000 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
15001 | ||
1b9448b0 JN |
15002 | /* Apple Macbook 4,1 */ |
15003 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, | |
15004 | ||
d4967d8c SD |
15005 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
15006 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
15007 | |
15008 | /* HP Chromebook 14 (Celeron 2955U) */ | |
15009 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
15010 | |
15011 | /* Dell Chromebook 11 */ | |
15012 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
9be64eee JN |
15013 | |
15014 | /* Dell Chromebook 11 (2015 version) */ | |
15015 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
15016 | }; |
15017 | ||
15018 | static void intel_init_quirks(struct drm_device *dev) | |
15019 | { | |
15020 | struct pci_dev *d = dev->pdev; | |
15021 | int i; | |
15022 | ||
15023 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
15024 | struct intel_quirk *q = &intel_quirks[i]; | |
15025 | ||
15026 | if (d->device == q->device && | |
15027 | (d->subsystem_vendor == q->subsystem_vendor || | |
15028 | q->subsystem_vendor == PCI_ANY_ID) && | |
15029 | (d->subsystem_device == q->subsystem_device || | |
15030 | q->subsystem_device == PCI_ANY_ID)) | |
15031 | q->hook(dev); | |
15032 | } | |
5f85f176 EE |
15033 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
15034 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
15035 | intel_dmi_quirks[i].hook(dev); | |
15036 | } | |
b690e96c JB |
15037 | } |
15038 | ||
9cce37f4 JB |
15039 | /* Disable the VGA plane that we never use */ |
15040 | static void i915_disable_vga(struct drm_device *dev) | |
15041 | { | |
15042 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15043 | u8 sr1; | |
f0f59a00 | 15044 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 15045 | |
2b37c616 | 15046 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 15047 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 15048 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
15049 | sr1 = inb(VGA_SR_DATA); |
15050 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
15051 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
15052 | udelay(300); | |
15053 | ||
01f5a626 | 15054 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
15055 | POSTING_READ(vga_reg); |
15056 | } | |
15057 | ||
f817586c DV |
15058 | void intel_modeset_init_hw(struct drm_device *dev) |
15059 | { | |
b6283055 | 15060 | intel_update_cdclk(dev); |
a8f78b58 | 15061 | intel_prepare_ddi(dev); |
f817586c | 15062 | intel_init_clock_gating(dev); |
8090c6b9 | 15063 | intel_enable_gt_powersave(dev); |
f817586c DV |
15064 | } |
15065 | ||
79e53945 JB |
15066 | void intel_modeset_init(struct drm_device *dev) |
15067 | { | |
652c393a | 15068 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 15069 | int sprite, ret; |
8cc87b75 | 15070 | enum pipe pipe; |
46f297fb | 15071 | struct intel_crtc *crtc; |
79e53945 JB |
15072 | |
15073 | drm_mode_config_init(dev); | |
15074 | ||
15075 | dev->mode_config.min_width = 0; | |
15076 | dev->mode_config.min_height = 0; | |
15077 | ||
019d96cb DA |
15078 | dev->mode_config.preferred_depth = 24; |
15079 | dev->mode_config.prefer_shadow = 1; | |
15080 | ||
25bab385 TU |
15081 | dev->mode_config.allow_fb_modifiers = true; |
15082 | ||
e6ecefaa | 15083 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 15084 | |
b690e96c JB |
15085 | intel_init_quirks(dev); |
15086 | ||
1fa61106 ED |
15087 | intel_init_pm(dev); |
15088 | ||
e3c74757 BW |
15089 | if (INTEL_INFO(dev)->num_pipes == 0) |
15090 | return; | |
15091 | ||
69f92f67 LW |
15092 | /* |
15093 | * There may be no VBT; and if the BIOS enabled SSC we can | |
15094 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
15095 | * BIOS isn't using it, don't assume it will work even if the VBT | |
15096 | * indicates as much. | |
15097 | */ | |
15098 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { | |
15099 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
15100 | DREF_SSC1_ENABLE); | |
15101 | ||
15102 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
15103 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
15104 | bios_lvds_use_ssc ? "en" : "dis", | |
15105 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
15106 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
15107 | } | |
15108 | } | |
15109 | ||
e70236a8 | 15110 | intel_init_display(dev); |
7c10a2b5 | 15111 | intel_init_audio(dev); |
e70236a8 | 15112 | |
a6c45cf0 CW |
15113 | if (IS_GEN2(dev)) { |
15114 | dev->mode_config.max_width = 2048; | |
15115 | dev->mode_config.max_height = 2048; | |
15116 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
15117 | dev->mode_config.max_width = 4096; |
15118 | dev->mode_config.max_height = 4096; | |
79e53945 | 15119 | } else { |
a6c45cf0 CW |
15120 | dev->mode_config.max_width = 8192; |
15121 | dev->mode_config.max_height = 8192; | |
79e53945 | 15122 | } |
068be561 | 15123 | |
dc41c154 VS |
15124 | if (IS_845G(dev) || IS_I865G(dev)) { |
15125 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
15126 | dev->mode_config.cursor_height = 1023; | |
15127 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
15128 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
15129 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
15130 | } else { | |
15131 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
15132 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
15133 | } | |
15134 | ||
5d4545ae | 15135 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 15136 | |
28c97730 | 15137 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
15138 | INTEL_INFO(dev)->num_pipes, |
15139 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 15140 | |
055e393f | 15141 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 15142 | intel_crtc_init(dev, pipe); |
3bdcfc0c | 15143 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 15144 | ret = intel_plane_init(dev, pipe, sprite); |
7f1f3851 | 15145 | if (ret) |
06da8da2 | 15146 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 15147 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 15148 | } |
79e53945 JB |
15149 | } |
15150 | ||
bfa7df01 VS |
15151 | intel_update_czclk(dev_priv); |
15152 | intel_update_cdclk(dev); | |
15153 | ||
e72f9fbf | 15154 | intel_shared_dpll_init(dev); |
ee7b9f93 | 15155 | |
9cce37f4 JB |
15156 | /* Just disable it once at startup */ |
15157 | i915_disable_vga(dev); | |
79e53945 | 15158 | intel_setup_outputs(dev); |
11be49eb | 15159 | |
6e9f798d | 15160 | drm_modeset_lock_all(dev); |
043e9bda | 15161 | intel_modeset_setup_hw_state(dev); |
6e9f798d | 15162 | drm_modeset_unlock_all(dev); |
46f297fb | 15163 | |
d3fcc808 | 15164 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
15165 | struct intel_initial_plane_config plane_config = {}; |
15166 | ||
46f297fb JB |
15167 | if (!crtc->active) |
15168 | continue; | |
15169 | ||
46f297fb | 15170 | /* |
46f297fb JB |
15171 | * Note that reserving the BIOS fb up front prevents us |
15172 | * from stuffing other stolen allocations like the ring | |
15173 | * on top. This prevents some ugliness at boot time, and | |
15174 | * can even allow for smooth boot transitions if the BIOS | |
15175 | * fb is large enough for the active pipe configuration. | |
15176 | */ | |
eeebeac5 ML |
15177 | dev_priv->display.get_initial_plane_config(crtc, |
15178 | &plane_config); | |
15179 | ||
15180 | /* | |
15181 | * If the fb is shared between multiple heads, we'll | |
15182 | * just get the first one. | |
15183 | */ | |
15184 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 15185 | } |
2c7111db CW |
15186 | } |
15187 | ||
7fad798e DV |
15188 | static void intel_enable_pipe_a(struct drm_device *dev) |
15189 | { | |
15190 | struct intel_connector *connector; | |
15191 | struct drm_connector *crt = NULL; | |
15192 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 15193 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
15194 | |
15195 | /* We can't just switch on the pipe A, we need to set things up with a | |
15196 | * proper mode and output configuration. As a gross hack, enable pipe A | |
15197 | * by enabling the load detect pipe once. */ | |
3a3371ff | 15198 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
15199 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
15200 | crt = &connector->base; | |
15201 | break; | |
15202 | } | |
15203 | } | |
15204 | ||
15205 | if (!crt) | |
15206 | return; | |
15207 | ||
208bf9fd | 15208 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 15209 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
15210 | } |
15211 | ||
fa555837 DV |
15212 | static bool |
15213 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
15214 | { | |
7eb552ae BW |
15215 | struct drm_device *dev = crtc->base.dev; |
15216 | struct drm_i915_private *dev_priv = dev->dev_private; | |
649636ef | 15217 | u32 val; |
fa555837 | 15218 | |
7eb552ae | 15219 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
15220 | return true; |
15221 | ||
649636ef | 15222 | val = I915_READ(DSPCNTR(!crtc->plane)); |
fa555837 DV |
15223 | |
15224 | if ((val & DISPLAY_PLANE_ENABLE) && | |
15225 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
15226 | return false; | |
15227 | ||
15228 | return true; | |
15229 | } | |
15230 | ||
02e93c35 VS |
15231 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
15232 | { | |
15233 | struct drm_device *dev = crtc->base.dev; | |
15234 | struct intel_encoder *encoder; | |
15235 | ||
15236 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
15237 | return true; | |
15238 | ||
15239 | return false; | |
15240 | } | |
15241 | ||
24929352 DV |
15242 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
15243 | { | |
15244 | struct drm_device *dev = crtc->base.dev; | |
15245 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 15246 | i915_reg_t reg = PIPECONF(crtc->config->cpu_transcoder); |
24929352 | 15247 | |
24929352 | 15248 | /* Clear any frame start delays used for debugging left by the BIOS */ |
24929352 DV |
15249 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
15250 | ||
d3eaf884 | 15251 | /* restore vblank interrupts to correct state */ |
9625604c | 15252 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 15253 | if (crtc->active) { |
f9cd7b88 VS |
15254 | struct intel_plane *plane; |
15255 | ||
9625604c | 15256 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
15257 | |
15258 | /* Disable everything but the primary plane */ | |
15259 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
15260 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
15261 | continue; | |
15262 | ||
15263 | plane->disable_plane(&plane->base, &crtc->base); | |
15264 | } | |
9625604c | 15265 | } |
d3eaf884 | 15266 | |
24929352 | 15267 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
15268 | * disable the crtc (and hence change the state) if it is wrong. Note |
15269 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
15270 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
15271 | bool plane; |
15272 | ||
24929352 DV |
15273 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
15274 | crtc->base.base.id); | |
15275 | ||
15276 | /* Pipe has the wrong plane attached and the plane is active. | |
15277 | * Temporarily change the plane mapping and disable everything | |
15278 | * ... */ | |
15279 | plane = crtc->plane; | |
b70709a6 | 15280 | to_intel_plane_state(crtc->base.primary->state)->visible = true; |
24929352 | 15281 | crtc->plane = !plane; |
b17d48e2 | 15282 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15283 | crtc->plane = plane; |
24929352 | 15284 | } |
24929352 | 15285 | |
7fad798e DV |
15286 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
15287 | crtc->pipe == PIPE_A && !crtc->active) { | |
15288 | /* BIOS forgot to enable pipe A, this mostly happens after | |
15289 | * resume. Force-enable the pipe to fix this, the update_dpms | |
15290 | * call below we restore the pipe to the right state, but leave | |
15291 | * the required bits on. */ | |
15292 | intel_enable_pipe_a(dev); | |
15293 | } | |
15294 | ||
24929352 DV |
15295 | /* Adjust the state of the output pipe according to whether we |
15296 | * have active connectors/encoders. */ | |
02e93c35 | 15297 | if (!intel_crtc_has_encoders(crtc)) |
b17d48e2 | 15298 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15299 | |
53d9f4e9 | 15300 | if (crtc->active != crtc->base.state->active) { |
02e93c35 | 15301 | struct intel_encoder *encoder; |
24929352 DV |
15302 | |
15303 | /* This can happen either due to bugs in the get_hw_state | |
b17d48e2 ML |
15304 | * functions or because of calls to intel_crtc_disable_noatomic, |
15305 | * or because the pipe is force-enabled due to the | |
24929352 DV |
15306 | * pipe A quirk. */ |
15307 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
15308 | crtc->base.base.id, | |
83d65738 | 15309 | crtc->base.state->enable ? "enabled" : "disabled", |
24929352 DV |
15310 | crtc->active ? "enabled" : "disabled"); |
15311 | ||
4be40c98 | 15312 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0); |
49d6fa21 | 15313 | crtc->base.state->active = crtc->active; |
24929352 DV |
15314 | crtc->base.enabled = crtc->active; |
15315 | ||
15316 | /* Because we only establish the connector -> encoder -> | |
15317 | * crtc links if something is active, this means the | |
15318 | * crtc is now deactivated. Break the links. connector | |
15319 | * -> encoder links are only establish when things are | |
15320 | * actually up, hence no need to break them. */ | |
15321 | WARN_ON(crtc->active); | |
15322 | ||
2d406bb0 | 15323 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
24929352 | 15324 | encoder->base.crtc = NULL; |
24929352 | 15325 | } |
c5ab3bc0 | 15326 | |
a3ed6aad | 15327 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
15328 | /* |
15329 | * We start out with underrun reporting disabled to avoid races. | |
15330 | * For correct bookkeeping mark this on active crtcs. | |
15331 | * | |
c5ab3bc0 DV |
15332 | * Also on gmch platforms we dont have any hardware bits to |
15333 | * disable the underrun reporting. Which means we need to start | |
15334 | * out with underrun reporting disabled also on inactive pipes, | |
15335 | * since otherwise we'll complain about the garbage we read when | |
15336 | * e.g. coming up after runtime pm. | |
15337 | * | |
4cc31489 DV |
15338 | * No protection against concurrent access is required - at |
15339 | * worst a fifo underrun happens which also sets this to false. | |
15340 | */ | |
15341 | crtc->cpu_fifo_underrun_disabled = true; | |
15342 | crtc->pch_fifo_underrun_disabled = true; | |
15343 | } | |
24929352 DV |
15344 | } |
15345 | ||
15346 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
15347 | { | |
15348 | struct intel_connector *connector; | |
15349 | struct drm_device *dev = encoder->base.dev; | |
873ffe69 | 15350 | bool active = false; |
24929352 DV |
15351 | |
15352 | /* We need to check both for a crtc link (meaning that the | |
15353 | * encoder is active and trying to read from a pipe) and the | |
15354 | * pipe itself being active. */ | |
15355 | bool has_active_crtc = encoder->base.crtc && | |
15356 | to_intel_crtc(encoder->base.crtc)->active; | |
15357 | ||
873ffe69 ML |
15358 | for_each_intel_connector(dev, connector) { |
15359 | if (connector->base.encoder != &encoder->base) | |
15360 | continue; | |
15361 | ||
15362 | active = true; | |
15363 | break; | |
15364 | } | |
15365 | ||
15366 | if (active && !has_active_crtc) { | |
24929352 DV |
15367 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
15368 | encoder->base.base.id, | |
8e329a03 | 15369 | encoder->base.name); |
24929352 DV |
15370 | |
15371 | /* Connector is active, but has no active pipe. This is | |
15372 | * fallout from our resume register restoring. Disable | |
15373 | * the encoder manually again. */ | |
15374 | if (encoder->base.crtc) { | |
15375 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
15376 | encoder->base.base.id, | |
8e329a03 | 15377 | encoder->base.name); |
24929352 | 15378 | encoder->disable(encoder); |
a62d1497 VS |
15379 | if (encoder->post_disable) |
15380 | encoder->post_disable(encoder); | |
24929352 | 15381 | } |
7f1950fb | 15382 | encoder->base.crtc = NULL; |
24929352 DV |
15383 | |
15384 | /* Inconsistent output/port/pipe state happens presumably due to | |
15385 | * a bug in one of the get_hw_state functions. Or someplace else | |
15386 | * in our code, like the register restore mess on resume. Clamp | |
15387 | * things to off as a safer default. */ | |
3a3371ff | 15388 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15389 | if (connector->encoder != encoder) |
15390 | continue; | |
7f1950fb EE |
15391 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
15392 | connector->base.encoder = NULL; | |
24929352 DV |
15393 | } |
15394 | } | |
15395 | /* Enabled encoders without active connectors will be fixed in | |
15396 | * the crtc fixup. */ | |
15397 | } | |
15398 | ||
04098753 | 15399 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
15400 | { |
15401 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 15402 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 15403 | |
04098753 ID |
15404 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
15405 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
15406 | i915_disable_vga(dev); | |
15407 | } | |
15408 | } | |
15409 | ||
15410 | void i915_redisable_vga(struct drm_device *dev) | |
15411 | { | |
15412 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15413 | ||
8dc8a27c PZ |
15414 | /* This function can be called both from intel_modeset_setup_hw_state or |
15415 | * at a very early point in our resume sequence, where the power well | |
15416 | * structures are not yet restored. Since this function is at a very | |
15417 | * paranoid "someone might have enabled VGA while we were not looking" | |
15418 | * level, just check if the power well is enabled instead of trying to | |
15419 | * follow the "don't touch the power well if we don't need it" policy | |
15420 | * the rest of the driver uses. */ | |
f458ebbc | 15421 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
15422 | return; |
15423 | ||
04098753 | 15424 | i915_redisable_vga_power_on(dev); |
0fde901f KM |
15425 | } |
15426 | ||
f9cd7b88 | 15427 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 15428 | { |
f9cd7b88 | 15429 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 15430 | |
f9cd7b88 | 15431 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
15432 | } |
15433 | ||
f9cd7b88 VS |
15434 | /* FIXME read out full plane state for all planes */ |
15435 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 15436 | { |
b26d3ea3 | 15437 | struct drm_plane *primary = crtc->base.primary; |
f9cd7b88 | 15438 | struct intel_plane_state *plane_state = |
b26d3ea3 | 15439 | to_intel_plane_state(primary->state); |
d032ffa0 | 15440 | |
19b8d387 | 15441 | plane_state->visible = crtc->active && |
b26d3ea3 ML |
15442 | primary_get_hw_state(to_intel_plane(primary)); |
15443 | ||
15444 | if (plane_state->visible) | |
15445 | crtc->base.state->plane_mask |= 1 << drm_plane_index(primary); | |
98ec7739 VS |
15446 | } |
15447 | ||
30e984df | 15448 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
15449 | { |
15450 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15451 | enum pipe pipe; | |
24929352 DV |
15452 | struct intel_crtc *crtc; |
15453 | struct intel_encoder *encoder; | |
15454 | struct intel_connector *connector; | |
5358901f | 15455 | int i; |
24929352 | 15456 | |
d3fcc808 | 15457 | for_each_intel_crtc(dev, crtc) { |
b06f8b0d | 15458 | __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state); |
6e3c9717 | 15459 | memset(crtc->config, 0, sizeof(*crtc->config)); |
f7217905 | 15460 | crtc->config->base.crtc = &crtc->base; |
3b117c8f | 15461 | |
0e8ffe1b | 15462 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
6e3c9717 | 15463 | crtc->config); |
24929352 | 15464 | |
49d6fa21 | 15465 | crtc->base.state->active = crtc->active; |
24929352 | 15466 | crtc->base.enabled = crtc->active; |
b70709a6 | 15467 | |
f9cd7b88 | 15468 | readout_plane_state(crtc); |
24929352 DV |
15469 | |
15470 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
15471 | crtc->base.base.id, | |
15472 | crtc->active ? "enabled" : "disabled"); | |
15473 | } | |
15474 | ||
5358901f DV |
15475 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15476 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15477 | ||
3e369b76 ACO |
15478 | pll->on = pll->get_hw_state(dev_priv, pll, |
15479 | &pll->config.hw_state); | |
5358901f | 15480 | pll->active = 0; |
3e369b76 | 15481 | pll->config.crtc_mask = 0; |
d3fcc808 | 15482 | for_each_intel_crtc(dev, crtc) { |
1e6f2ddc | 15483 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) { |
5358901f | 15484 | pll->active++; |
3e369b76 | 15485 | pll->config.crtc_mask |= 1 << crtc->pipe; |
1e6f2ddc | 15486 | } |
5358901f | 15487 | } |
5358901f | 15488 | |
1e6f2ddc | 15489 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 15490 | pll->name, pll->config.crtc_mask, pll->on); |
bd2bb1b9 | 15491 | |
3e369b76 | 15492 | if (pll->config.crtc_mask) |
bd2bb1b9 | 15493 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
5358901f DV |
15494 | } |
15495 | ||
b2784e15 | 15496 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15497 | pipe = 0; |
15498 | ||
15499 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
15500 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15501 | encoder->base.crtc = &crtc->base; | |
6e3c9717 | 15502 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
15503 | } else { |
15504 | encoder->base.crtc = NULL; | |
15505 | } | |
15506 | ||
6f2bcceb | 15507 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 15508 | encoder->base.base.id, |
8e329a03 | 15509 | encoder->base.name, |
24929352 | 15510 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 15511 | pipe_name(pipe)); |
24929352 DV |
15512 | } |
15513 | ||
3a3371ff | 15514 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15515 | if (connector->get_hw_state(connector)) { |
15516 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
24929352 DV |
15517 | connector->base.encoder = &connector->encoder->base; |
15518 | } else { | |
15519 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
15520 | connector->base.encoder = NULL; | |
15521 | } | |
15522 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
15523 | connector->base.base.id, | |
c23cc417 | 15524 | connector->base.name, |
24929352 DV |
15525 | connector->base.encoder ? "enabled" : "disabled"); |
15526 | } | |
7f4c6284 VS |
15527 | |
15528 | for_each_intel_crtc(dev, crtc) { | |
15529 | crtc->base.hwmode = crtc->config->base.adjusted_mode; | |
15530 | ||
15531 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); | |
15532 | if (crtc->base.state->active) { | |
15533 | intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); | |
15534 | intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config); | |
15535 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); | |
15536 | ||
15537 | /* | |
15538 | * The initial mode needs to be set in order to keep | |
15539 | * the atomic core happy. It wants a valid mode if the | |
15540 | * crtc's enabled, so we do the above call. | |
15541 | * | |
15542 | * At this point some state updated by the connectors | |
15543 | * in their ->detect() callback has not run yet, so | |
15544 | * no recalculation can be done yet. | |
15545 | * | |
15546 | * Even if we could do a recalculation and modeset | |
15547 | * right now it would cause a double modeset if | |
15548 | * fbdev or userspace chooses a different initial mode. | |
15549 | * | |
15550 | * If that happens, someone indicated they wanted a | |
15551 | * mode change, which means it's safe to do a full | |
15552 | * recalculation. | |
15553 | */ | |
15554 | crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED; | |
9eca6832 VS |
15555 | |
15556 | drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); | |
15557 | update_scanline_offset(crtc); | |
7f4c6284 VS |
15558 | } |
15559 | } | |
30e984df DV |
15560 | } |
15561 | ||
043e9bda ML |
15562 | /* Scan out the current hw modeset state, |
15563 | * and sanitizes it to the current state | |
15564 | */ | |
15565 | static void | |
15566 | intel_modeset_setup_hw_state(struct drm_device *dev) | |
30e984df DV |
15567 | { |
15568 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15569 | enum pipe pipe; | |
30e984df DV |
15570 | struct intel_crtc *crtc; |
15571 | struct intel_encoder *encoder; | |
35c95375 | 15572 | int i; |
30e984df DV |
15573 | |
15574 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
15575 | |
15576 | /* HW state is read out, now we need to sanitize this mess. */ | |
b2784e15 | 15577 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15578 | intel_sanitize_encoder(encoder); |
15579 | } | |
15580 | ||
055e393f | 15581 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
15582 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15583 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
15584 | intel_dump_pipe_config(crtc, crtc->config, |
15585 | "[setup_hw_state]"); | |
24929352 | 15586 | } |
9a935856 | 15587 | |
d29b2f9d ACO |
15588 | intel_modeset_update_connector_atomic_state(dev); |
15589 | ||
35c95375 DV |
15590 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15591 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15592 | ||
15593 | if (!pll->on || pll->active) | |
15594 | continue; | |
15595 | ||
15596 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
15597 | ||
15598 | pll->disable(dev_priv, pll); | |
15599 | pll->on = false; | |
15600 | } | |
15601 | ||
26e1fe4f | 15602 | if (IS_VALLEYVIEW(dev)) |
6eb1a681 VS |
15603 | vlv_wm_get_hw_state(dev); |
15604 | else if (IS_GEN9(dev)) | |
3078999f PB |
15605 | skl_wm_get_hw_state(dev); |
15606 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 | 15607 | ilk_wm_get_hw_state(dev); |
292b990e ML |
15608 | |
15609 | for_each_intel_crtc(dev, crtc) { | |
15610 | unsigned long put_domains; | |
15611 | ||
15612 | put_domains = modeset_get_crtc_power_domains(&crtc->base); | |
15613 | if (WARN_ON(put_domains)) | |
15614 | modeset_put_power_domains(dev_priv, put_domains); | |
15615 | } | |
15616 | intel_display_set_init_power(dev_priv, false); | |
043e9bda | 15617 | } |
7d0bc1ea | 15618 | |
043e9bda ML |
15619 | void intel_display_resume(struct drm_device *dev) |
15620 | { | |
15621 | struct drm_atomic_state *state = drm_atomic_state_alloc(dev); | |
15622 | struct intel_connector *conn; | |
15623 | struct intel_plane *plane; | |
15624 | struct drm_crtc *crtc; | |
15625 | int ret; | |
f30da187 | 15626 | |
043e9bda ML |
15627 | if (!state) |
15628 | return; | |
15629 | ||
15630 | state->acquire_ctx = dev->mode_config.acquire_ctx; | |
15631 | ||
15632 | /* preserve complete old state, including dpll */ | |
15633 | intel_atomic_get_shared_dpll_state(state); | |
15634 | ||
15635 | for_each_crtc(dev, crtc) { | |
15636 | struct drm_crtc_state *crtc_state = | |
15637 | drm_atomic_get_crtc_state(state, crtc); | |
15638 | ||
15639 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
15640 | if (ret) | |
15641 | goto err; | |
15642 | ||
15643 | /* force a restore */ | |
15644 | crtc_state->mode_changed = true; | |
45e2b5f6 | 15645 | } |
8af6cf88 | 15646 | |
043e9bda ML |
15647 | for_each_intel_plane(dev, plane) { |
15648 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base)); | |
15649 | if (ret) | |
15650 | goto err; | |
15651 | } | |
15652 | ||
15653 | for_each_intel_connector(dev, conn) { | |
15654 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base)); | |
15655 | if (ret) | |
15656 | goto err; | |
15657 | } | |
15658 | ||
15659 | intel_modeset_setup_hw_state(dev); | |
15660 | ||
15661 | i915_redisable_vga(dev); | |
74c090b1 | 15662 | ret = drm_atomic_commit(state); |
043e9bda ML |
15663 | if (!ret) |
15664 | return; | |
15665 | ||
15666 | err: | |
15667 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
15668 | drm_atomic_state_free(state); | |
2c7111db CW |
15669 | } |
15670 | ||
15671 | void intel_modeset_gem_init(struct drm_device *dev) | |
15672 | { | |
484b41dd | 15673 | struct drm_crtc *c; |
2ff8fde1 | 15674 | struct drm_i915_gem_object *obj; |
e0d6149b | 15675 | int ret; |
484b41dd | 15676 | |
ae48434c ID |
15677 | mutex_lock(&dev->struct_mutex); |
15678 | intel_init_gt_powersave(dev); | |
15679 | mutex_unlock(&dev->struct_mutex); | |
15680 | ||
1833b134 | 15681 | intel_modeset_init_hw(dev); |
02e792fb DV |
15682 | |
15683 | intel_setup_overlay(dev); | |
484b41dd JB |
15684 | |
15685 | /* | |
15686 | * Make sure any fbs we allocated at startup are properly | |
15687 | * pinned & fenced. When we do the allocation it's too early | |
15688 | * for this. | |
15689 | */ | |
70e1e0ec | 15690 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
15691 | obj = intel_fb_obj(c->primary->fb); |
15692 | if (obj == NULL) | |
484b41dd JB |
15693 | continue; |
15694 | ||
e0d6149b TU |
15695 | mutex_lock(&dev->struct_mutex); |
15696 | ret = intel_pin_and_fence_fb_obj(c->primary, | |
15697 | c->primary->fb, | |
7580d774 | 15698 | c->primary->state); |
e0d6149b TU |
15699 | mutex_unlock(&dev->struct_mutex); |
15700 | if (ret) { | |
484b41dd JB |
15701 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
15702 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
15703 | drm_framebuffer_unreference(c->primary->fb); |
15704 | c->primary->fb = NULL; | |
36750f28 | 15705 | c->primary->crtc = c->primary->state->crtc = NULL; |
afd65eb4 | 15706 | update_state_fb(c->primary); |
36750f28 | 15707 | c->state->plane_mask &= ~(1 << drm_plane_index(c->primary)); |
484b41dd JB |
15708 | } |
15709 | } | |
0962c3c9 VS |
15710 | |
15711 | intel_backlight_register(dev); | |
79e53945 JB |
15712 | } |
15713 | ||
4932e2c3 ID |
15714 | void intel_connector_unregister(struct intel_connector *intel_connector) |
15715 | { | |
15716 | struct drm_connector *connector = &intel_connector->base; | |
15717 | ||
15718 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 15719 | drm_connector_unregister(connector); |
4932e2c3 ID |
15720 | } |
15721 | ||
79e53945 JB |
15722 | void intel_modeset_cleanup(struct drm_device *dev) |
15723 | { | |
652c393a | 15724 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9255d57 | 15725 | struct drm_connector *connector; |
652c393a | 15726 | |
2eb5252e ID |
15727 | intel_disable_gt_powersave(dev); |
15728 | ||
0962c3c9 VS |
15729 | intel_backlight_unregister(dev); |
15730 | ||
fd0c0642 DV |
15731 | /* |
15732 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 15733 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
15734 | * experience fancy races otherwise. |
15735 | */ | |
2aeb7d3a | 15736 | intel_irq_uninstall(dev_priv); |
eb21b92b | 15737 | |
fd0c0642 DV |
15738 | /* |
15739 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
15740 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
15741 | */ | |
f87ea761 | 15742 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 15743 | |
723bfd70 JB |
15744 | intel_unregister_dsm_handler(); |
15745 | ||
7733b49b | 15746 | intel_fbc_disable(dev_priv); |
69341a5e | 15747 | |
1630fe75 CW |
15748 | /* flush any delayed tasks or pending work */ |
15749 | flush_scheduled_work(); | |
15750 | ||
db31af1d JN |
15751 | /* destroy the backlight and sysfs files before encoders/connectors */ |
15752 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4932e2c3 ID |
15753 | struct intel_connector *intel_connector; |
15754 | ||
15755 | intel_connector = to_intel_connector(connector); | |
15756 | intel_connector->unregister(intel_connector); | |
db31af1d | 15757 | } |
d9255d57 | 15758 | |
79e53945 | 15759 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
15760 | |
15761 | intel_cleanup_overlay(dev); | |
ae48434c ID |
15762 | |
15763 | mutex_lock(&dev->struct_mutex); | |
15764 | intel_cleanup_gt_powersave(dev); | |
15765 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
15766 | } |
15767 | ||
f1c79df3 ZW |
15768 | /* |
15769 | * Return which encoder is currently attached for connector. | |
15770 | */ | |
df0e9248 | 15771 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 15772 | { |
df0e9248 CW |
15773 | return &intel_attached_encoder(connector)->base; |
15774 | } | |
f1c79df3 | 15775 | |
df0e9248 CW |
15776 | void intel_connector_attach_encoder(struct intel_connector *connector, |
15777 | struct intel_encoder *encoder) | |
15778 | { | |
15779 | connector->encoder = encoder; | |
15780 | drm_mode_connector_attach_encoder(&connector->base, | |
15781 | &encoder->base); | |
79e53945 | 15782 | } |
28d52043 DA |
15783 | |
15784 | /* | |
15785 | * set vga decode state - true == enable VGA decode | |
15786 | */ | |
15787 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
15788 | { | |
15789 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 15790 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
15791 | u16 gmch_ctrl; |
15792 | ||
75fa041d CW |
15793 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
15794 | DRM_ERROR("failed to read control word\n"); | |
15795 | return -EIO; | |
15796 | } | |
15797 | ||
c0cc8a55 CW |
15798 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
15799 | return 0; | |
15800 | ||
28d52043 DA |
15801 | if (state) |
15802 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
15803 | else | |
15804 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
15805 | |
15806 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
15807 | DRM_ERROR("failed to write control word\n"); | |
15808 | return -EIO; | |
15809 | } | |
15810 | ||
28d52043 DA |
15811 | return 0; |
15812 | } | |
c4a1d9e4 | 15813 | |
c4a1d9e4 | 15814 | struct intel_display_error_state { |
ff57f1b0 PZ |
15815 | |
15816 | u32 power_well_driver; | |
15817 | ||
63b66e5b CW |
15818 | int num_transcoders; |
15819 | ||
c4a1d9e4 CW |
15820 | struct intel_cursor_error_state { |
15821 | u32 control; | |
15822 | u32 position; | |
15823 | u32 base; | |
15824 | u32 size; | |
52331309 | 15825 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15826 | |
15827 | struct intel_pipe_error_state { | |
ddf9c536 | 15828 | bool power_domain_on; |
c4a1d9e4 | 15829 | u32 source; |
f301b1e1 | 15830 | u32 stat; |
52331309 | 15831 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15832 | |
15833 | struct intel_plane_error_state { | |
15834 | u32 control; | |
15835 | u32 stride; | |
15836 | u32 size; | |
15837 | u32 pos; | |
15838 | u32 addr; | |
15839 | u32 surface; | |
15840 | u32 tile_offset; | |
52331309 | 15841 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
15842 | |
15843 | struct intel_transcoder_error_state { | |
ddf9c536 | 15844 | bool power_domain_on; |
63b66e5b CW |
15845 | enum transcoder cpu_transcoder; |
15846 | ||
15847 | u32 conf; | |
15848 | ||
15849 | u32 htotal; | |
15850 | u32 hblank; | |
15851 | u32 hsync; | |
15852 | u32 vtotal; | |
15853 | u32 vblank; | |
15854 | u32 vsync; | |
15855 | } transcoder[4]; | |
c4a1d9e4 CW |
15856 | }; |
15857 | ||
15858 | struct intel_display_error_state * | |
15859 | intel_display_capture_error_state(struct drm_device *dev) | |
15860 | { | |
fbee40df | 15861 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 15862 | struct intel_display_error_state *error; |
63b66e5b CW |
15863 | int transcoders[] = { |
15864 | TRANSCODER_A, | |
15865 | TRANSCODER_B, | |
15866 | TRANSCODER_C, | |
15867 | TRANSCODER_EDP, | |
15868 | }; | |
c4a1d9e4 CW |
15869 | int i; |
15870 | ||
63b66e5b CW |
15871 | if (INTEL_INFO(dev)->num_pipes == 0) |
15872 | return NULL; | |
15873 | ||
9d1cb914 | 15874 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
15875 | if (error == NULL) |
15876 | return NULL; | |
15877 | ||
190be112 | 15878 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
15879 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
15880 | ||
055e393f | 15881 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 15882 | error->pipe[i].power_domain_on = |
f458ebbc DV |
15883 | __intel_display_power_is_enabled(dev_priv, |
15884 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 15885 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
15886 | continue; |
15887 | ||
5efb3e28 VS |
15888 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
15889 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
15890 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
15891 | |
15892 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
15893 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 15894 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 15895 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
15896 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
15897 | } | |
ca291363 PZ |
15898 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
15899 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
15900 | if (INTEL_INFO(dev)->gen >= 4) { |
15901 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
15902 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
15903 | } | |
15904 | ||
c4a1d9e4 | 15905 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 15906 | |
3abfce77 | 15907 | if (HAS_GMCH_DISPLAY(dev)) |
f301b1e1 | 15908 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
15909 | } |
15910 | ||
15911 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
15912 | if (HAS_DDI(dev_priv->dev)) | |
15913 | error->num_transcoders++; /* Account for eDP. */ | |
15914 | ||
15915 | for (i = 0; i < error->num_transcoders; i++) { | |
15916 | enum transcoder cpu_transcoder = transcoders[i]; | |
15917 | ||
ddf9c536 | 15918 | error->transcoder[i].power_domain_on = |
f458ebbc | 15919 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 15920 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 15921 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
15922 | continue; |
15923 | ||
63b66e5b CW |
15924 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
15925 | ||
15926 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
15927 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
15928 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
15929 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
15930 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
15931 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
15932 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
15933 | } |
15934 | ||
15935 | return error; | |
15936 | } | |
15937 | ||
edc3d884 MK |
15938 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
15939 | ||
c4a1d9e4 | 15940 | void |
edc3d884 | 15941 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
15942 | struct drm_device *dev, |
15943 | struct intel_display_error_state *error) | |
15944 | { | |
055e393f | 15945 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
15946 | int i; |
15947 | ||
63b66e5b CW |
15948 | if (!error) |
15949 | return; | |
15950 | ||
edc3d884 | 15951 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 15952 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 15953 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 15954 | error->power_well_driver); |
055e393f | 15955 | for_each_pipe(dev_priv, i) { |
edc3d884 | 15956 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 ID |
15957 | err_printf(m, " Power: %s\n", |
15958 | error->pipe[i].power_domain_on ? "on" : "off"); | |
edc3d884 | 15959 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 15960 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
15961 | |
15962 | err_printf(m, "Plane [%d]:\n", i); | |
15963 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
15964 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 15965 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
15966 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
15967 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 15968 | } |
4b71a570 | 15969 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 15970 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 15971 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
15972 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
15973 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
15974 | } |
15975 | ||
edc3d884 MK |
15976 | err_printf(m, "Cursor [%d]:\n", i); |
15977 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
15978 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
15979 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 15980 | } |
63b66e5b CW |
15981 | |
15982 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 15983 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 15984 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 ID |
15985 | err_printf(m, " Power: %s\n", |
15986 | error->transcoder[i].power_domain_on ? "on" : "off"); | |
63b66e5b CW |
15987 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
15988 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
15989 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
15990 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
15991 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
15992 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
15993 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
15994 | } | |
c4a1d9e4 | 15995 | } |
e2fcdaa9 VS |
15996 | |
15997 | void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file) | |
15998 | { | |
15999 | struct intel_crtc *crtc; | |
16000 | ||
16001 | for_each_intel_crtc(dev, crtc) { | |
16002 | struct intel_unpin_work *work; | |
e2fcdaa9 | 16003 | |
5e2d7afc | 16004 | spin_lock_irq(&dev->event_lock); |
e2fcdaa9 VS |
16005 | |
16006 | work = crtc->unpin_work; | |
16007 | ||
16008 | if (work && work->event && | |
16009 | work->event->base.file_priv == file) { | |
16010 | kfree(work->event); | |
16011 | work->event = NULL; | |
16012 | } | |
16013 | ||
5e2d7afc | 16014 | spin_unlock_irq(&dev->event_lock); |
e2fcdaa9 VS |
16015 | } |
16016 | } |