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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
319c1d42 | 40 | #include <drm/drm_atomic.h> |
c196e1d6 | 41 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
42 | #include <drm/drm_dp_helper.h> |
43 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
44 | #include <drm/drm_plane_helper.h> |
45 | #include <drm/drm_rect.h> | |
c0f372b3 | 46 | #include <linux/dma_remapping.h> |
79e53945 | 47 | |
465c120c | 48 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 49 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
50 | DRM_FORMAT_C8, |
51 | DRM_FORMAT_RGB565, | |
465c120c | 52 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 53 | DRM_FORMAT_XRGB8888, |
465c120c MR |
54 | }; |
55 | ||
56 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 57 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
58 | DRM_FORMAT_C8, |
59 | DRM_FORMAT_RGB565, | |
60 | DRM_FORMAT_XRGB8888, | |
61 | DRM_FORMAT_XBGR8888, | |
62 | DRM_FORMAT_XRGB2101010, | |
63 | DRM_FORMAT_XBGR2101010, | |
64 | }; | |
65 | ||
66 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
67 | DRM_FORMAT_C8, |
68 | DRM_FORMAT_RGB565, | |
69 | DRM_FORMAT_XRGB8888, | |
465c120c | 70 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 71 | DRM_FORMAT_ARGB8888, |
465c120c MR |
72 | DRM_FORMAT_ABGR8888, |
73 | DRM_FORMAT_XRGB2101010, | |
465c120c | 74 | DRM_FORMAT_XBGR2101010, |
465c120c MR |
75 | }; |
76 | ||
3d7d6510 MR |
77 | /* Cursor formats */ |
78 | static const uint32_t intel_cursor_formats[] = { | |
79 | DRM_FORMAT_ARGB8888, | |
80 | }; | |
81 | ||
6b383a7f | 82 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 83 | |
f1f644dc | 84 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 85 | struct intel_crtc_state *pipe_config); |
18442d08 | 86 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 87 | struct intel_crtc_state *pipe_config); |
f1f644dc | 88 | |
8c7b5ccb | 89 | static int intel_set_mode(struct drm_crtc *crtc, |
83a57153 | 90 | struct drm_atomic_state *state); |
eb1bfe80 JB |
91 | static int intel_framebuffer_init(struct drm_device *dev, |
92 | struct intel_framebuffer *ifb, | |
93 | struct drm_mode_fb_cmd2 *mode_cmd, | |
94 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
95 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
96 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
29407aab | 97 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
98 | struct intel_link_m_n *m_n, |
99 | struct intel_link_m_n *m2_n2); | |
29407aab | 100 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 DV |
101 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
102 | static void intel_set_pipe_csc(struct drm_crtc *crtc); | |
d288f65f | 103 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 104 | const struct intel_crtc_state *pipe_config); |
d288f65f | 105 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 106 | const struct intel_crtc_state *pipe_config); |
ea2c67bb MR |
107 | static void intel_begin_crtc_commit(struct drm_crtc *crtc); |
108 | static void intel_finish_crtc_commit(struct drm_crtc *crtc); | |
549e2bfb CK |
109 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
110 | struct intel_crtc_state *crtc_state); | |
5ab7b0b7 ID |
111 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
112 | int num_connectors); | |
ce22dba9 ML |
113 | static void intel_crtc_enable_planes(struct drm_crtc *crtc); |
114 | static void intel_crtc_disable_planes(struct drm_crtc *crtc); | |
e7457a9a | 115 | |
0e32b39c DA |
116 | static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe) |
117 | { | |
118 | if (!connector->mst_port) | |
119 | return connector->encoder; | |
120 | else | |
121 | return &connector->mst_port->mst_encoders[pipe]->base; | |
122 | } | |
123 | ||
79e53945 | 124 | typedef struct { |
0206e353 | 125 | int min, max; |
79e53945 JB |
126 | } intel_range_t; |
127 | ||
128 | typedef struct { | |
0206e353 AJ |
129 | int dot_limit; |
130 | int p2_slow, p2_fast; | |
79e53945 JB |
131 | } intel_p2_t; |
132 | ||
d4906093 ML |
133 | typedef struct intel_limit intel_limit_t; |
134 | struct intel_limit { | |
0206e353 AJ |
135 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
136 | intel_p2_t p2; | |
d4906093 | 137 | }; |
79e53945 | 138 | |
d2acd215 DV |
139 | int |
140 | intel_pch_rawclk(struct drm_device *dev) | |
141 | { | |
142 | struct drm_i915_private *dev_priv = dev->dev_private; | |
143 | ||
144 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
145 | ||
146 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
147 | } | |
148 | ||
021357ac CW |
149 | static inline u32 /* units of 100MHz */ |
150 | intel_fdi_link_freq(struct drm_device *dev) | |
151 | { | |
8b99e68c CW |
152 | if (IS_GEN5(dev)) { |
153 | struct drm_i915_private *dev_priv = dev->dev_private; | |
154 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
155 | } else | |
156 | return 27; | |
021357ac CW |
157 | } |
158 | ||
5d536e28 | 159 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 160 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 161 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 162 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
163 | .m = { .min = 96, .max = 140 }, |
164 | .m1 = { .min = 18, .max = 26 }, | |
165 | .m2 = { .min = 6, .max = 16 }, | |
166 | .p = { .min = 4, .max = 128 }, | |
167 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
168 | .p2 = { .dot_limit = 165000, |
169 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
170 | }; |
171 | ||
5d536e28 DV |
172 | static const intel_limit_t intel_limits_i8xx_dvo = { |
173 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 174 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 175 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
176 | .m = { .min = 96, .max = 140 }, |
177 | .m1 = { .min = 18, .max = 26 }, | |
178 | .m2 = { .min = 6, .max = 16 }, | |
179 | .p = { .min = 4, .max = 128 }, | |
180 | .p1 = { .min = 2, .max = 33 }, | |
181 | .p2 = { .dot_limit = 165000, | |
182 | .p2_slow = 4, .p2_fast = 4 }, | |
183 | }; | |
184 | ||
e4b36699 | 185 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 186 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 187 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 188 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
189 | .m = { .min = 96, .max = 140 }, |
190 | .m1 = { .min = 18, .max = 26 }, | |
191 | .m2 = { .min = 6, .max = 16 }, | |
192 | .p = { .min = 4, .max = 128 }, | |
193 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
194 | .p2 = { .dot_limit = 165000, |
195 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 196 | }; |
273e27ca | 197 | |
e4b36699 | 198 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
199 | .dot = { .min = 20000, .max = 400000 }, |
200 | .vco = { .min = 1400000, .max = 2800000 }, | |
201 | .n = { .min = 1, .max = 6 }, | |
202 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
203 | .m1 = { .min = 8, .max = 18 }, |
204 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
205 | .p = { .min = 5, .max = 80 }, |
206 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
207 | .p2 = { .dot_limit = 200000, |
208 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
209 | }; |
210 | ||
211 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
212 | .dot = { .min = 20000, .max = 400000 }, |
213 | .vco = { .min = 1400000, .max = 2800000 }, | |
214 | .n = { .min = 1, .max = 6 }, | |
215 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
216 | .m1 = { .min = 8, .max = 18 }, |
217 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
218 | .p = { .min = 7, .max = 98 }, |
219 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
220 | .p2 = { .dot_limit = 112000, |
221 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
222 | }; |
223 | ||
273e27ca | 224 | |
e4b36699 | 225 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
226 | .dot = { .min = 25000, .max = 270000 }, |
227 | .vco = { .min = 1750000, .max = 3500000}, | |
228 | .n = { .min = 1, .max = 4 }, | |
229 | .m = { .min = 104, .max = 138 }, | |
230 | .m1 = { .min = 17, .max = 23 }, | |
231 | .m2 = { .min = 5, .max = 11 }, | |
232 | .p = { .min = 10, .max = 30 }, | |
233 | .p1 = { .min = 1, .max = 3}, | |
234 | .p2 = { .dot_limit = 270000, | |
235 | .p2_slow = 10, | |
236 | .p2_fast = 10 | |
044c7c41 | 237 | }, |
e4b36699 KP |
238 | }; |
239 | ||
240 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
241 | .dot = { .min = 22000, .max = 400000 }, |
242 | .vco = { .min = 1750000, .max = 3500000}, | |
243 | .n = { .min = 1, .max = 4 }, | |
244 | .m = { .min = 104, .max = 138 }, | |
245 | .m1 = { .min = 16, .max = 23 }, | |
246 | .m2 = { .min = 5, .max = 11 }, | |
247 | .p = { .min = 5, .max = 80 }, | |
248 | .p1 = { .min = 1, .max = 8}, | |
249 | .p2 = { .dot_limit = 165000, | |
250 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
251 | }; |
252 | ||
253 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
254 | .dot = { .min = 20000, .max = 115000 }, |
255 | .vco = { .min = 1750000, .max = 3500000 }, | |
256 | .n = { .min = 1, .max = 3 }, | |
257 | .m = { .min = 104, .max = 138 }, | |
258 | .m1 = { .min = 17, .max = 23 }, | |
259 | .m2 = { .min = 5, .max = 11 }, | |
260 | .p = { .min = 28, .max = 112 }, | |
261 | .p1 = { .min = 2, .max = 8 }, | |
262 | .p2 = { .dot_limit = 0, | |
263 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 264 | }, |
e4b36699 KP |
265 | }; |
266 | ||
267 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
268 | .dot = { .min = 80000, .max = 224000 }, |
269 | .vco = { .min = 1750000, .max = 3500000 }, | |
270 | .n = { .min = 1, .max = 3 }, | |
271 | .m = { .min = 104, .max = 138 }, | |
272 | .m1 = { .min = 17, .max = 23 }, | |
273 | .m2 = { .min = 5, .max = 11 }, | |
274 | .p = { .min = 14, .max = 42 }, | |
275 | .p1 = { .min = 2, .max = 6 }, | |
276 | .p2 = { .dot_limit = 0, | |
277 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 278 | }, |
e4b36699 KP |
279 | }; |
280 | ||
f2b115e6 | 281 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
282 | .dot = { .min = 20000, .max = 400000}, |
283 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 284 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
285 | .n = { .min = 3, .max = 6 }, |
286 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 287 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
288 | .m1 = { .min = 0, .max = 0 }, |
289 | .m2 = { .min = 0, .max = 254 }, | |
290 | .p = { .min = 5, .max = 80 }, | |
291 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
292 | .p2 = { .dot_limit = 200000, |
293 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
294 | }; |
295 | ||
f2b115e6 | 296 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
297 | .dot = { .min = 20000, .max = 400000 }, |
298 | .vco = { .min = 1700000, .max = 3500000 }, | |
299 | .n = { .min = 3, .max = 6 }, | |
300 | .m = { .min = 2, .max = 256 }, | |
301 | .m1 = { .min = 0, .max = 0 }, | |
302 | .m2 = { .min = 0, .max = 254 }, | |
303 | .p = { .min = 7, .max = 112 }, | |
304 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
305 | .p2 = { .dot_limit = 112000, |
306 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
307 | }; |
308 | ||
273e27ca EA |
309 | /* Ironlake / Sandybridge |
310 | * | |
311 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
312 | * the range value for them is (actual_value - 2). | |
313 | */ | |
b91ad0ec | 314 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
315 | .dot = { .min = 25000, .max = 350000 }, |
316 | .vco = { .min = 1760000, .max = 3510000 }, | |
317 | .n = { .min = 1, .max = 5 }, | |
318 | .m = { .min = 79, .max = 127 }, | |
319 | .m1 = { .min = 12, .max = 22 }, | |
320 | .m2 = { .min = 5, .max = 9 }, | |
321 | .p = { .min = 5, .max = 80 }, | |
322 | .p1 = { .min = 1, .max = 8 }, | |
323 | .p2 = { .dot_limit = 225000, | |
324 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
325 | }; |
326 | ||
b91ad0ec | 327 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
328 | .dot = { .min = 25000, .max = 350000 }, |
329 | .vco = { .min = 1760000, .max = 3510000 }, | |
330 | .n = { .min = 1, .max = 3 }, | |
331 | .m = { .min = 79, .max = 118 }, | |
332 | .m1 = { .min = 12, .max = 22 }, | |
333 | .m2 = { .min = 5, .max = 9 }, | |
334 | .p = { .min = 28, .max = 112 }, | |
335 | .p1 = { .min = 2, .max = 8 }, | |
336 | .p2 = { .dot_limit = 225000, | |
337 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
338 | }; |
339 | ||
340 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
341 | .dot = { .min = 25000, .max = 350000 }, |
342 | .vco = { .min = 1760000, .max = 3510000 }, | |
343 | .n = { .min = 1, .max = 3 }, | |
344 | .m = { .min = 79, .max = 127 }, | |
345 | .m1 = { .min = 12, .max = 22 }, | |
346 | .m2 = { .min = 5, .max = 9 }, | |
347 | .p = { .min = 14, .max = 56 }, | |
348 | .p1 = { .min = 2, .max = 8 }, | |
349 | .p2 = { .dot_limit = 225000, | |
350 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
351 | }; |
352 | ||
273e27ca | 353 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 354 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
355 | .dot = { .min = 25000, .max = 350000 }, |
356 | .vco = { .min = 1760000, .max = 3510000 }, | |
357 | .n = { .min = 1, .max = 2 }, | |
358 | .m = { .min = 79, .max = 126 }, | |
359 | .m1 = { .min = 12, .max = 22 }, | |
360 | .m2 = { .min = 5, .max = 9 }, | |
361 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 362 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
363 | .p2 = { .dot_limit = 225000, |
364 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
365 | }; |
366 | ||
367 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
368 | .dot = { .min = 25000, .max = 350000 }, |
369 | .vco = { .min = 1760000, .max = 3510000 }, | |
370 | .n = { .min = 1, .max = 3 }, | |
371 | .m = { .min = 79, .max = 126 }, | |
372 | .m1 = { .min = 12, .max = 22 }, | |
373 | .m2 = { .min = 5, .max = 9 }, | |
374 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 375 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
376 | .p2 = { .dot_limit = 225000, |
377 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
378 | }; |
379 | ||
dc730512 | 380 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
381 | /* |
382 | * These are the data rate limits (measured in fast clocks) | |
383 | * since those are the strictest limits we have. The fast | |
384 | * clock and actual rate limits are more relaxed, so checking | |
385 | * them would make no difference. | |
386 | */ | |
387 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 388 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 389 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
390 | .m1 = { .min = 2, .max = 3 }, |
391 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 392 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 393 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
394 | }; |
395 | ||
ef9348c8 CML |
396 | static const intel_limit_t intel_limits_chv = { |
397 | /* | |
398 | * These are the data rate limits (measured in fast clocks) | |
399 | * since those are the strictest limits we have. The fast | |
400 | * clock and actual rate limits are more relaxed, so checking | |
401 | * them would make no difference. | |
402 | */ | |
403 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 404 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
405 | .n = { .min = 1, .max = 1 }, |
406 | .m1 = { .min = 2, .max = 2 }, | |
407 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
408 | .p1 = { .min = 2, .max = 4 }, | |
409 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
410 | }; | |
411 | ||
5ab7b0b7 ID |
412 | static const intel_limit_t intel_limits_bxt = { |
413 | /* FIXME: find real dot limits */ | |
414 | .dot = { .min = 0, .max = INT_MAX }, | |
415 | .vco = { .min = 4800000, .max = 6480000 }, | |
416 | .n = { .min = 1, .max = 1 }, | |
417 | .m1 = { .min = 2, .max = 2 }, | |
418 | /* FIXME: find real m2 limits */ | |
419 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
420 | .p1 = { .min = 2, .max = 4 }, | |
421 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
422 | }; | |
423 | ||
6b4bf1c4 VS |
424 | static void vlv_clock(int refclk, intel_clock_t *clock) |
425 | { | |
426 | clock->m = clock->m1 * clock->m2; | |
427 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
428 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
429 | return; | |
fb03ac01 VS |
430 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
431 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
6b4bf1c4 VS |
432 | } |
433 | ||
e0638cdf PZ |
434 | /** |
435 | * Returns whether any output on the specified pipe is of the specified type | |
436 | */ | |
4093561b | 437 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) |
e0638cdf | 438 | { |
409ee761 | 439 | struct drm_device *dev = crtc->base.dev; |
e0638cdf PZ |
440 | struct intel_encoder *encoder; |
441 | ||
409ee761 | 442 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
e0638cdf PZ |
443 | if (encoder->type == type) |
444 | return true; | |
445 | ||
446 | return false; | |
447 | } | |
448 | ||
d0737e1d ACO |
449 | /** |
450 | * Returns whether any output on the specified pipe will have the specified | |
451 | * type after a staged modeset is complete, i.e., the same as | |
452 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of | |
453 | * encoder->crtc. | |
454 | */ | |
a93e255f ACO |
455 | static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state, |
456 | int type) | |
d0737e1d | 457 | { |
a93e255f | 458 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 459 | struct drm_connector *connector; |
a93e255f | 460 | struct drm_connector_state *connector_state; |
d0737e1d | 461 | struct intel_encoder *encoder; |
a93e255f ACO |
462 | int i, num_connectors = 0; |
463 | ||
da3ced29 | 464 | for_each_connector_in_state(state, connector, connector_state, i) { |
a93e255f ACO |
465 | if (connector_state->crtc != crtc_state->base.crtc) |
466 | continue; | |
467 | ||
468 | num_connectors++; | |
d0737e1d | 469 | |
a93e255f ACO |
470 | encoder = to_intel_encoder(connector_state->best_encoder); |
471 | if (encoder->type == type) | |
d0737e1d | 472 | return true; |
a93e255f ACO |
473 | } |
474 | ||
475 | WARN_ON(num_connectors == 0); | |
d0737e1d ACO |
476 | |
477 | return false; | |
478 | } | |
479 | ||
a93e255f ACO |
480 | static const intel_limit_t * |
481 | intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk) | |
2c07245f | 482 | { |
a93e255f | 483 | struct drm_device *dev = crtc_state->base.crtc->dev; |
2c07245f | 484 | const intel_limit_t *limit; |
b91ad0ec | 485 | |
a93e255f | 486 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 487 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 488 | if (refclk == 100000) |
b91ad0ec ZW |
489 | limit = &intel_limits_ironlake_dual_lvds_100m; |
490 | else | |
491 | limit = &intel_limits_ironlake_dual_lvds; | |
492 | } else { | |
1b894b59 | 493 | if (refclk == 100000) |
b91ad0ec ZW |
494 | limit = &intel_limits_ironlake_single_lvds_100m; |
495 | else | |
496 | limit = &intel_limits_ironlake_single_lvds; | |
497 | } | |
c6bb3538 | 498 | } else |
b91ad0ec | 499 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
500 | |
501 | return limit; | |
502 | } | |
503 | ||
a93e255f ACO |
504 | static const intel_limit_t * |
505 | intel_g4x_limit(struct intel_crtc_state *crtc_state) | |
044c7c41 | 506 | { |
a93e255f | 507 | struct drm_device *dev = crtc_state->base.crtc->dev; |
044c7c41 ML |
508 | const intel_limit_t *limit; |
509 | ||
a93e255f | 510 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 511 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 512 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 513 | else |
e4b36699 | 514 | limit = &intel_limits_g4x_single_channel_lvds; |
a93e255f ACO |
515 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) || |
516 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 517 | limit = &intel_limits_g4x_hdmi; |
a93e255f | 518 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 519 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 520 | } else /* The option is for other outputs */ |
e4b36699 | 521 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
522 | |
523 | return limit; | |
524 | } | |
525 | ||
a93e255f ACO |
526 | static const intel_limit_t * |
527 | intel_limit(struct intel_crtc_state *crtc_state, int refclk) | |
79e53945 | 528 | { |
a93e255f | 529 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 JB |
530 | const intel_limit_t *limit; |
531 | ||
5ab7b0b7 ID |
532 | if (IS_BROXTON(dev)) |
533 | limit = &intel_limits_bxt; | |
534 | else if (HAS_PCH_SPLIT(dev)) | |
a93e255f | 535 | limit = intel_ironlake_limit(crtc_state, refclk); |
2c07245f | 536 | else if (IS_G4X(dev)) { |
a93e255f | 537 | limit = intel_g4x_limit(crtc_state); |
f2b115e6 | 538 | } else if (IS_PINEVIEW(dev)) { |
a93e255f | 539 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 540 | limit = &intel_limits_pineview_lvds; |
2177832f | 541 | else |
f2b115e6 | 542 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
543 | } else if (IS_CHERRYVIEW(dev)) { |
544 | limit = &intel_limits_chv; | |
a0c4da24 | 545 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 546 | limit = &intel_limits_vlv; |
a6c45cf0 | 547 | } else if (!IS_GEN2(dev)) { |
a93e255f | 548 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a6c45cf0 CW |
549 | limit = &intel_limits_i9xx_lvds; |
550 | else | |
551 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 | 552 | } else { |
a93e255f | 553 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
e4b36699 | 554 | limit = &intel_limits_i8xx_lvds; |
a93e255f | 555 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
e4b36699 | 556 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
557 | else |
558 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
559 | } |
560 | return limit; | |
561 | } | |
562 | ||
f2b115e6 AJ |
563 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
564 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 565 | { |
2177832f SL |
566 | clock->m = clock->m2 + 2; |
567 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
568 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
569 | return; | |
fb03ac01 VS |
570 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
571 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
2177832f SL |
572 | } |
573 | ||
7429e9d4 DV |
574 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
575 | { | |
576 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
577 | } | |
578 | ||
ac58c3f0 | 579 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
2177832f | 580 | { |
7429e9d4 | 581 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 582 | clock->p = clock->p1 * clock->p2; |
ed5ca77e VS |
583 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
584 | return; | |
fb03ac01 VS |
585 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
586 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
79e53945 JB |
587 | } |
588 | ||
ef9348c8 CML |
589 | static void chv_clock(int refclk, intel_clock_t *clock) |
590 | { | |
591 | clock->m = clock->m1 * clock->m2; | |
592 | clock->p = clock->p1 * clock->p2; | |
593 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
594 | return; | |
595 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, | |
596 | clock->n << 22); | |
597 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
598 | } | |
599 | ||
7c04d1d9 | 600 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
601 | /** |
602 | * Returns whether the given set of divisors are valid for a given refclk with | |
603 | * the given connectors. | |
604 | */ | |
605 | ||
1b894b59 CW |
606 | static bool intel_PLL_is_valid(struct drm_device *dev, |
607 | const intel_limit_t *limit, | |
608 | const intel_clock_t *clock) | |
79e53945 | 609 | { |
f01b7962 VS |
610 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
611 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 612 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 613 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 614 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 615 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 616 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 617 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 618 | |
5ab7b0b7 | 619 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) |
f01b7962 VS |
620 | if (clock->m1 <= clock->m2) |
621 | INTELPllInvalid("m1 <= m2\n"); | |
622 | ||
5ab7b0b7 | 623 | if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) { |
f01b7962 VS |
624 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
625 | INTELPllInvalid("p out of range\n"); | |
626 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
627 | INTELPllInvalid("m out of range\n"); | |
628 | } | |
629 | ||
79e53945 | 630 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 631 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
632 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
633 | * connector, etc., rather than just a single range. | |
634 | */ | |
635 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 636 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
637 | |
638 | return true; | |
639 | } | |
640 | ||
d4906093 | 641 | static bool |
a93e255f ACO |
642 | i9xx_find_best_dpll(const intel_limit_t *limit, |
643 | struct intel_crtc_state *crtc_state, | |
cec2f356 SP |
644 | int target, int refclk, intel_clock_t *match_clock, |
645 | intel_clock_t *best_clock) | |
79e53945 | 646 | { |
a93e255f | 647 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 648 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 649 | intel_clock_t clock; |
79e53945 JB |
650 | int err = target; |
651 | ||
a93e255f | 652 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 653 | /* |
a210b028 DV |
654 | * For LVDS just rely on its current settings for dual-channel. |
655 | * We haven't figured out how to reliably set up different | |
656 | * single/dual channel state, if we even can. | |
79e53945 | 657 | */ |
1974cad0 | 658 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
659 | clock.p2 = limit->p2.p2_fast; |
660 | else | |
661 | clock.p2 = limit->p2.p2_slow; | |
662 | } else { | |
663 | if (target < limit->p2.dot_limit) | |
664 | clock.p2 = limit->p2.p2_slow; | |
665 | else | |
666 | clock.p2 = limit->p2.p2_fast; | |
667 | } | |
668 | ||
0206e353 | 669 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 670 | |
42158660 ZY |
671 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
672 | clock.m1++) { | |
673 | for (clock.m2 = limit->m2.min; | |
674 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 675 | if (clock.m2 >= clock.m1) |
42158660 ZY |
676 | break; |
677 | for (clock.n = limit->n.min; | |
678 | clock.n <= limit->n.max; clock.n++) { | |
679 | for (clock.p1 = limit->p1.min; | |
680 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
681 | int this_err; |
682 | ||
ac58c3f0 DV |
683 | i9xx_clock(refclk, &clock); |
684 | if (!intel_PLL_is_valid(dev, limit, | |
685 | &clock)) | |
686 | continue; | |
687 | if (match_clock && | |
688 | clock.p != match_clock->p) | |
689 | continue; | |
690 | ||
691 | this_err = abs(clock.dot - target); | |
692 | if (this_err < err) { | |
693 | *best_clock = clock; | |
694 | err = this_err; | |
695 | } | |
696 | } | |
697 | } | |
698 | } | |
699 | } | |
700 | ||
701 | return (err != target); | |
702 | } | |
703 | ||
704 | static bool | |
a93e255f ACO |
705 | pnv_find_best_dpll(const intel_limit_t *limit, |
706 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
707 | int target, int refclk, intel_clock_t *match_clock, |
708 | intel_clock_t *best_clock) | |
79e53945 | 709 | { |
a93e255f | 710 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 711 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 712 | intel_clock_t clock; |
79e53945 JB |
713 | int err = target; |
714 | ||
a93e255f | 715 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 716 | /* |
a210b028 DV |
717 | * For LVDS just rely on its current settings for dual-channel. |
718 | * We haven't figured out how to reliably set up different | |
719 | * single/dual channel state, if we even can. | |
79e53945 | 720 | */ |
1974cad0 | 721 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
722 | clock.p2 = limit->p2.p2_fast; |
723 | else | |
724 | clock.p2 = limit->p2.p2_slow; | |
725 | } else { | |
726 | if (target < limit->p2.dot_limit) | |
727 | clock.p2 = limit->p2.p2_slow; | |
728 | else | |
729 | clock.p2 = limit->p2.p2_fast; | |
730 | } | |
731 | ||
0206e353 | 732 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 733 | |
42158660 ZY |
734 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
735 | clock.m1++) { | |
736 | for (clock.m2 = limit->m2.min; | |
737 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
738 | for (clock.n = limit->n.min; |
739 | clock.n <= limit->n.max; clock.n++) { | |
740 | for (clock.p1 = limit->p1.min; | |
741 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
742 | int this_err; |
743 | ||
ac58c3f0 | 744 | pineview_clock(refclk, &clock); |
1b894b59 CW |
745 | if (!intel_PLL_is_valid(dev, limit, |
746 | &clock)) | |
79e53945 | 747 | continue; |
cec2f356 SP |
748 | if (match_clock && |
749 | clock.p != match_clock->p) | |
750 | continue; | |
79e53945 JB |
751 | |
752 | this_err = abs(clock.dot - target); | |
753 | if (this_err < err) { | |
754 | *best_clock = clock; | |
755 | err = this_err; | |
756 | } | |
757 | } | |
758 | } | |
759 | } | |
760 | } | |
761 | ||
762 | return (err != target); | |
763 | } | |
764 | ||
d4906093 | 765 | static bool |
a93e255f ACO |
766 | g4x_find_best_dpll(const intel_limit_t *limit, |
767 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
768 | int target, int refclk, intel_clock_t *match_clock, |
769 | intel_clock_t *best_clock) | |
d4906093 | 770 | { |
a93e255f | 771 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 772 | struct drm_device *dev = crtc->base.dev; |
d4906093 ML |
773 | intel_clock_t clock; |
774 | int max_n; | |
775 | bool found; | |
6ba770dc AJ |
776 | /* approximately equals target * 0.00585 */ |
777 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
778 | found = false; |
779 | ||
a93e255f | 780 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 781 | if (intel_is_dual_link_lvds(dev)) |
d4906093 ML |
782 | clock.p2 = limit->p2.p2_fast; |
783 | else | |
784 | clock.p2 = limit->p2.p2_slow; | |
785 | } else { | |
786 | if (target < limit->p2.dot_limit) | |
787 | clock.p2 = limit->p2.p2_slow; | |
788 | else | |
789 | clock.p2 = limit->p2.p2_fast; | |
790 | } | |
791 | ||
792 | memset(best_clock, 0, sizeof(*best_clock)); | |
793 | max_n = limit->n.max; | |
f77f13e2 | 794 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 795 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 796 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
797 | for (clock.m1 = limit->m1.max; |
798 | clock.m1 >= limit->m1.min; clock.m1--) { | |
799 | for (clock.m2 = limit->m2.max; | |
800 | clock.m2 >= limit->m2.min; clock.m2--) { | |
801 | for (clock.p1 = limit->p1.max; | |
802 | clock.p1 >= limit->p1.min; clock.p1--) { | |
803 | int this_err; | |
804 | ||
ac58c3f0 | 805 | i9xx_clock(refclk, &clock); |
1b894b59 CW |
806 | if (!intel_PLL_is_valid(dev, limit, |
807 | &clock)) | |
d4906093 | 808 | continue; |
1b894b59 CW |
809 | |
810 | this_err = abs(clock.dot - target); | |
d4906093 ML |
811 | if (this_err < err_most) { |
812 | *best_clock = clock; | |
813 | err_most = this_err; | |
814 | max_n = clock.n; | |
815 | found = true; | |
816 | } | |
817 | } | |
818 | } | |
819 | } | |
820 | } | |
2c07245f ZW |
821 | return found; |
822 | } | |
823 | ||
d5dd62bd ID |
824 | /* |
825 | * Check if the calculated PLL configuration is more optimal compared to the | |
826 | * best configuration and error found so far. Return the calculated error. | |
827 | */ | |
828 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
829 | const intel_clock_t *calculated_clock, | |
830 | const intel_clock_t *best_clock, | |
831 | unsigned int best_error_ppm, | |
832 | unsigned int *error_ppm) | |
833 | { | |
9ca3ba01 ID |
834 | /* |
835 | * For CHV ignore the error and consider only the P value. | |
836 | * Prefer a bigger P value based on HW requirements. | |
837 | */ | |
838 | if (IS_CHERRYVIEW(dev)) { | |
839 | *error_ppm = 0; | |
840 | ||
841 | return calculated_clock->p > best_clock->p; | |
842 | } | |
843 | ||
24be4e46 ID |
844 | if (WARN_ON_ONCE(!target_freq)) |
845 | return false; | |
846 | ||
d5dd62bd ID |
847 | *error_ppm = div_u64(1000000ULL * |
848 | abs(target_freq - calculated_clock->dot), | |
849 | target_freq); | |
850 | /* | |
851 | * Prefer a better P value over a better (smaller) error if the error | |
852 | * is small. Ensure this preference for future configurations too by | |
853 | * setting the error to 0. | |
854 | */ | |
855 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
856 | *error_ppm = 0; | |
857 | ||
858 | return true; | |
859 | } | |
860 | ||
861 | return *error_ppm + 10 < best_error_ppm; | |
862 | } | |
863 | ||
a0c4da24 | 864 | static bool |
a93e255f ACO |
865 | vlv_find_best_dpll(const intel_limit_t *limit, |
866 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
867 | int target, int refclk, intel_clock_t *match_clock, |
868 | intel_clock_t *best_clock) | |
a0c4da24 | 869 | { |
a93e255f | 870 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 871 | struct drm_device *dev = crtc->base.dev; |
6b4bf1c4 | 872 | intel_clock_t clock; |
69e4f900 | 873 | unsigned int bestppm = 1000000; |
27e639bf VS |
874 | /* min update 19.2 MHz */ |
875 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 876 | bool found = false; |
a0c4da24 | 877 | |
6b4bf1c4 VS |
878 | target *= 5; /* fast clock */ |
879 | ||
880 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
881 | |
882 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 883 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 884 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 885 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 886 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 887 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 888 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 889 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 890 | unsigned int ppm; |
69e4f900 | 891 | |
6b4bf1c4 VS |
892 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
893 | refclk * clock.m1); | |
894 | ||
895 | vlv_clock(refclk, &clock); | |
43b0ac53 | 896 | |
f01b7962 VS |
897 | if (!intel_PLL_is_valid(dev, limit, |
898 | &clock)) | |
43b0ac53 VS |
899 | continue; |
900 | ||
d5dd62bd ID |
901 | if (!vlv_PLL_is_optimal(dev, target, |
902 | &clock, | |
903 | best_clock, | |
904 | bestppm, &ppm)) | |
905 | continue; | |
6b4bf1c4 | 906 | |
d5dd62bd ID |
907 | *best_clock = clock; |
908 | bestppm = ppm; | |
909 | found = true; | |
a0c4da24 JB |
910 | } |
911 | } | |
912 | } | |
913 | } | |
a0c4da24 | 914 | |
49e497ef | 915 | return found; |
a0c4da24 | 916 | } |
a4fc5ed6 | 917 | |
ef9348c8 | 918 | static bool |
a93e255f ACO |
919 | chv_find_best_dpll(const intel_limit_t *limit, |
920 | struct intel_crtc_state *crtc_state, | |
ef9348c8 CML |
921 | int target, int refclk, intel_clock_t *match_clock, |
922 | intel_clock_t *best_clock) | |
923 | { | |
a93e255f | 924 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 925 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 926 | unsigned int best_error_ppm; |
ef9348c8 CML |
927 | intel_clock_t clock; |
928 | uint64_t m2; | |
929 | int found = false; | |
930 | ||
931 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 932 | best_error_ppm = 1000000; |
ef9348c8 CML |
933 | |
934 | /* | |
935 | * Based on hardware doc, the n always set to 1, and m1 always | |
936 | * set to 2. If requires to support 200Mhz refclk, we need to | |
937 | * revisit this because n may not 1 anymore. | |
938 | */ | |
939 | clock.n = 1, clock.m1 = 2; | |
940 | target *= 5; /* fast clock */ | |
941 | ||
942 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
943 | for (clock.p2 = limit->p2.p2_fast; | |
944 | clock.p2 >= limit->p2.p2_slow; | |
945 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 946 | unsigned int error_ppm; |
ef9348c8 CML |
947 | |
948 | clock.p = clock.p1 * clock.p2; | |
949 | ||
950 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
951 | clock.n) << 22, refclk * clock.m1); | |
952 | ||
953 | if (m2 > INT_MAX/clock.m1) | |
954 | continue; | |
955 | ||
956 | clock.m2 = m2; | |
957 | ||
958 | chv_clock(refclk, &clock); | |
959 | ||
960 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
961 | continue; | |
962 | ||
9ca3ba01 ID |
963 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
964 | best_error_ppm, &error_ppm)) | |
965 | continue; | |
966 | ||
967 | *best_clock = clock; | |
968 | best_error_ppm = error_ppm; | |
969 | found = true; | |
ef9348c8 CML |
970 | } |
971 | } | |
972 | ||
973 | return found; | |
974 | } | |
975 | ||
5ab7b0b7 ID |
976 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
977 | intel_clock_t *best_clock) | |
978 | { | |
979 | int refclk = i9xx_get_refclk(crtc_state, 0); | |
980 | ||
981 | return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state, | |
982 | target_clock, refclk, NULL, best_clock); | |
983 | } | |
984 | ||
20ddf665 VS |
985 | bool intel_crtc_active(struct drm_crtc *crtc) |
986 | { | |
987 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
988 | ||
989 | /* Be paranoid as we can arrive here with only partial | |
990 | * state retrieved from the hardware during setup. | |
991 | * | |
241bfc38 | 992 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
993 | * as Haswell has gained clock readout/fastboot support. |
994 | * | |
66e514c1 | 995 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 996 | * properly reconstruct framebuffers. |
c3d1f436 MR |
997 | * |
998 | * FIXME: The intel_crtc->active here should be switched to | |
999 | * crtc->state->active once we have proper CRTC states wired up | |
1000 | * for atomic. | |
20ddf665 | 1001 | */ |
c3d1f436 | 1002 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 1003 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
1004 | } |
1005 | ||
a5c961d1 PZ |
1006 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1007 | enum pipe pipe) | |
1008 | { | |
1009 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1010 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1011 | ||
6e3c9717 | 1012 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1013 | } |
1014 | ||
fbf49ea2 VS |
1015 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
1016 | { | |
1017 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1018 | u32 reg = PIPEDSL(pipe); | |
1019 | u32 line1, line2; | |
1020 | u32 line_mask; | |
1021 | ||
1022 | if (IS_GEN2(dev)) | |
1023 | line_mask = DSL_LINEMASK_GEN2; | |
1024 | else | |
1025 | line_mask = DSL_LINEMASK_GEN3; | |
1026 | ||
1027 | line1 = I915_READ(reg) & line_mask; | |
1028 | mdelay(5); | |
1029 | line2 = I915_READ(reg) & line_mask; | |
1030 | ||
1031 | return line1 == line2; | |
1032 | } | |
1033 | ||
ab7ad7f6 KP |
1034 | /* |
1035 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1036 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1037 | * |
1038 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1039 | * spinning on the vblank interrupt status bit, since we won't actually | |
1040 | * see an interrupt when the pipe is disabled. | |
1041 | * | |
ab7ad7f6 KP |
1042 | * On Gen4 and above: |
1043 | * wait for the pipe register state bit to turn off | |
1044 | * | |
1045 | * Otherwise: | |
1046 | * wait for the display line value to settle (it usually | |
1047 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1048 | * |
9d0498a2 | 1049 | */ |
575f7ab7 | 1050 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1051 | { |
575f7ab7 | 1052 | struct drm_device *dev = crtc->base.dev; |
9d0498a2 | 1053 | struct drm_i915_private *dev_priv = dev->dev_private; |
6e3c9717 | 1054 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1055 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
1056 | |
1057 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 1058 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1059 | |
1060 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
1061 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1062 | 100)) | |
284637d9 | 1063 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1064 | } else { |
ab7ad7f6 | 1065 | /* Wait for the display line to settle */ |
fbf49ea2 | 1066 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1067 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1068 | } |
79e53945 JB |
1069 | } |
1070 | ||
b0ea7d37 DL |
1071 | /* |
1072 | * ibx_digital_port_connected - is the specified port connected? | |
1073 | * @dev_priv: i915 private structure | |
1074 | * @port: the port to test | |
1075 | * | |
1076 | * Returns true if @port is connected, false otherwise. | |
1077 | */ | |
1078 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, | |
1079 | struct intel_digital_port *port) | |
1080 | { | |
1081 | u32 bit; | |
1082 | ||
c36346e3 | 1083 | if (HAS_PCH_IBX(dev_priv->dev)) { |
eba905b2 | 1084 | switch (port->port) { |
c36346e3 DL |
1085 | case PORT_B: |
1086 | bit = SDE_PORTB_HOTPLUG; | |
1087 | break; | |
1088 | case PORT_C: | |
1089 | bit = SDE_PORTC_HOTPLUG; | |
1090 | break; | |
1091 | case PORT_D: | |
1092 | bit = SDE_PORTD_HOTPLUG; | |
1093 | break; | |
1094 | default: | |
1095 | return true; | |
1096 | } | |
1097 | } else { | |
eba905b2 | 1098 | switch (port->port) { |
c36346e3 DL |
1099 | case PORT_B: |
1100 | bit = SDE_PORTB_HOTPLUG_CPT; | |
1101 | break; | |
1102 | case PORT_C: | |
1103 | bit = SDE_PORTC_HOTPLUG_CPT; | |
1104 | break; | |
1105 | case PORT_D: | |
1106 | bit = SDE_PORTD_HOTPLUG_CPT; | |
1107 | break; | |
1108 | default: | |
1109 | return true; | |
1110 | } | |
b0ea7d37 DL |
1111 | } |
1112 | ||
1113 | return I915_READ(SDEISR) & bit; | |
1114 | } | |
1115 | ||
b24e7179 JB |
1116 | static const char *state_string(bool enabled) |
1117 | { | |
1118 | return enabled ? "on" : "off"; | |
1119 | } | |
1120 | ||
1121 | /* Only for pre-ILK configs */ | |
55607e8a DV |
1122 | void assert_pll(struct drm_i915_private *dev_priv, |
1123 | enum pipe pipe, bool state) | |
b24e7179 JB |
1124 | { |
1125 | int reg; | |
1126 | u32 val; | |
1127 | bool cur_state; | |
1128 | ||
1129 | reg = DPLL(pipe); | |
1130 | val = I915_READ(reg); | |
1131 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
e2c719b7 | 1132 | I915_STATE_WARN(cur_state != state, |
b24e7179 JB |
1133 | "PLL state assertion failure (expected %s, current %s)\n", |
1134 | state_string(state), state_string(cur_state)); | |
1135 | } | |
b24e7179 | 1136 | |
23538ef1 JN |
1137 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1138 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1139 | { | |
1140 | u32 val; | |
1141 | bool cur_state; | |
1142 | ||
a580516d | 1143 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1144 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1145 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1146 | |
1147 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1148 | I915_STATE_WARN(cur_state != state, |
23538ef1 JN |
1149 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
1150 | state_string(state), state_string(cur_state)); | |
1151 | } | |
1152 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1153 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1154 | ||
55607e8a | 1155 | struct intel_shared_dpll * |
e2b78267 DV |
1156 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1157 | { | |
1158 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1159 | ||
6e3c9717 | 1160 | if (crtc->config->shared_dpll < 0) |
e2b78267 DV |
1161 | return NULL; |
1162 | ||
6e3c9717 | 1163 | return &dev_priv->shared_dplls[crtc->config->shared_dpll]; |
e2b78267 DV |
1164 | } |
1165 | ||
040484af | 1166 | /* For ILK+ */ |
55607e8a DV |
1167 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1168 | struct intel_shared_dpll *pll, | |
1169 | bool state) | |
040484af | 1170 | { |
040484af | 1171 | bool cur_state; |
5358901f | 1172 | struct intel_dpll_hw_state hw_state; |
040484af | 1173 | |
92b27b08 | 1174 | if (WARN (!pll, |
46edb027 | 1175 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 1176 | return; |
ee7b9f93 | 1177 | |
5358901f | 1178 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
e2c719b7 | 1179 | I915_STATE_WARN(cur_state != state, |
5358901f DV |
1180 | "%s assertion failure (expected %s, current %s)\n", |
1181 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 1182 | } |
040484af JB |
1183 | |
1184 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1185 | enum pipe pipe, bool state) | |
1186 | { | |
1187 | int reg; | |
1188 | u32 val; | |
1189 | bool cur_state; | |
ad80a810 PZ |
1190 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1191 | pipe); | |
040484af | 1192 | |
affa9354 PZ |
1193 | if (HAS_DDI(dev_priv->dev)) { |
1194 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 1195 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 1196 | val = I915_READ(reg); |
ad80a810 | 1197 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
1198 | } else { |
1199 | reg = FDI_TX_CTL(pipe); | |
1200 | val = I915_READ(reg); | |
1201 | cur_state = !!(val & FDI_TX_ENABLE); | |
1202 | } | |
e2c719b7 | 1203 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1204 | "FDI TX state assertion failure (expected %s, current %s)\n", |
1205 | state_string(state), state_string(cur_state)); | |
1206 | } | |
1207 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1208 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1209 | ||
1210 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1211 | enum pipe pipe, bool state) | |
1212 | { | |
1213 | int reg; | |
1214 | u32 val; | |
1215 | bool cur_state; | |
1216 | ||
d63fa0dc PZ |
1217 | reg = FDI_RX_CTL(pipe); |
1218 | val = I915_READ(reg); | |
1219 | cur_state = !!(val & FDI_RX_ENABLE); | |
e2c719b7 | 1220 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1221 | "FDI RX state assertion failure (expected %s, current %s)\n", |
1222 | state_string(state), state_string(cur_state)); | |
1223 | } | |
1224 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1225 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1226 | ||
1227 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1228 | enum pipe pipe) | |
1229 | { | |
1230 | int reg; | |
1231 | u32 val; | |
1232 | ||
1233 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1234 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1235 | return; |
1236 | ||
bf507ef7 | 1237 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1238 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1239 | return; |
1240 | ||
040484af JB |
1241 | reg = FDI_TX_CTL(pipe); |
1242 | val = I915_READ(reg); | |
e2c719b7 | 1243 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1244 | } |
1245 | ||
55607e8a DV |
1246 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1247 | enum pipe pipe, bool state) | |
040484af JB |
1248 | { |
1249 | int reg; | |
1250 | u32 val; | |
55607e8a | 1251 | bool cur_state; |
040484af JB |
1252 | |
1253 | reg = FDI_RX_CTL(pipe); | |
1254 | val = I915_READ(reg); | |
55607e8a | 1255 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1256 | I915_STATE_WARN(cur_state != state, |
55607e8a DV |
1257 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
1258 | state_string(state), state_string(cur_state)); | |
040484af JB |
1259 | } |
1260 | ||
b680c37a DV |
1261 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1262 | enum pipe pipe) | |
ea0760cf | 1263 | { |
bedd4dba JN |
1264 | struct drm_device *dev = dev_priv->dev; |
1265 | int pp_reg; | |
ea0760cf JB |
1266 | u32 val; |
1267 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1268 | bool locked = true; |
ea0760cf | 1269 | |
bedd4dba JN |
1270 | if (WARN_ON(HAS_DDI(dev))) |
1271 | return; | |
1272 | ||
1273 | if (HAS_PCH_SPLIT(dev)) { | |
1274 | u32 port_sel; | |
1275 | ||
ea0760cf | 1276 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1277 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1278 | ||
1279 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1280 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1281 | panel_pipe = PIPE_B; | |
1282 | /* XXX: else fix for eDP */ | |
1283 | } else if (IS_VALLEYVIEW(dev)) { | |
1284 | /* presumably write lock depends on pipe, not port select */ | |
1285 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1286 | panel_pipe = pipe; | |
ea0760cf JB |
1287 | } else { |
1288 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1289 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1290 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1291 | } |
1292 | ||
1293 | val = I915_READ(pp_reg); | |
1294 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1295 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1296 | locked = false; |
1297 | ||
e2c719b7 | 1298 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1299 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1300 | pipe_name(pipe)); |
ea0760cf JB |
1301 | } |
1302 | ||
93ce0ba6 JN |
1303 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1304 | enum pipe pipe, bool state) | |
1305 | { | |
1306 | struct drm_device *dev = dev_priv->dev; | |
1307 | bool cur_state; | |
1308 | ||
d9d82081 | 1309 | if (IS_845G(dev) || IS_I865G(dev)) |
93ce0ba6 | 1310 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; |
d9d82081 | 1311 | else |
5efb3e28 | 1312 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1313 | |
e2c719b7 | 1314 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 JN |
1315 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
1316 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1317 | } | |
1318 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1319 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1320 | ||
b840d907 JB |
1321 | void assert_pipe(struct drm_i915_private *dev_priv, |
1322 | enum pipe pipe, bool state) | |
b24e7179 JB |
1323 | { |
1324 | int reg; | |
1325 | u32 val; | |
63d7bbe9 | 1326 | bool cur_state; |
702e7a56 PZ |
1327 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1328 | pipe); | |
b24e7179 | 1329 | |
b6b5d049 VS |
1330 | /* if we need the pipe quirk it must be always on */ |
1331 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1332 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1333 | state = true; |
1334 | ||
f458ebbc | 1335 | if (!intel_display_power_is_enabled(dev_priv, |
b97186f0 | 1336 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
69310161 PZ |
1337 | cur_state = false; |
1338 | } else { | |
1339 | reg = PIPECONF(cpu_transcoder); | |
1340 | val = I915_READ(reg); | |
1341 | cur_state = !!(val & PIPECONF_ENABLE); | |
1342 | } | |
1343 | ||
e2c719b7 | 1344 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1345 | "pipe %c assertion failure (expected %s, current %s)\n", |
9db4a9c7 | 1346 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1347 | } |
1348 | ||
931872fc CW |
1349 | static void assert_plane(struct drm_i915_private *dev_priv, |
1350 | enum plane plane, bool state) | |
b24e7179 JB |
1351 | { |
1352 | int reg; | |
1353 | u32 val; | |
931872fc | 1354 | bool cur_state; |
b24e7179 JB |
1355 | |
1356 | reg = DSPCNTR(plane); | |
1357 | val = I915_READ(reg); | |
931872fc | 1358 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1359 | I915_STATE_WARN(cur_state != state, |
931872fc CW |
1360 | "plane %c assertion failure (expected %s, current %s)\n", |
1361 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1362 | } |
1363 | ||
931872fc CW |
1364 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1365 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1366 | ||
b24e7179 JB |
1367 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1368 | enum pipe pipe) | |
1369 | { | |
653e1026 | 1370 | struct drm_device *dev = dev_priv->dev; |
b24e7179 JB |
1371 | int reg, i; |
1372 | u32 val; | |
1373 | int cur_pipe; | |
1374 | ||
653e1026 VS |
1375 | /* Primary planes are fixed to pipes on gen4+ */ |
1376 | if (INTEL_INFO(dev)->gen >= 4) { | |
28c05794 AJ |
1377 | reg = DSPCNTR(pipe); |
1378 | val = I915_READ(reg); | |
e2c719b7 | 1379 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1380 | "plane %c assertion failure, should be disabled but not\n", |
1381 | plane_name(pipe)); | |
19ec1358 | 1382 | return; |
28c05794 | 1383 | } |
19ec1358 | 1384 | |
b24e7179 | 1385 | /* Need to check both planes against the pipe */ |
055e393f | 1386 | for_each_pipe(dev_priv, i) { |
b24e7179 JB |
1387 | reg = DSPCNTR(i); |
1388 | val = I915_READ(reg); | |
1389 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1390 | DISPPLANE_SEL_PIPE_SHIFT; | |
e2c719b7 | 1391 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1392 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1393 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1394 | } |
1395 | } | |
1396 | ||
19332d7a JB |
1397 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1398 | enum pipe pipe) | |
1399 | { | |
20674eef | 1400 | struct drm_device *dev = dev_priv->dev; |
1fe47785 | 1401 | int reg, sprite; |
19332d7a JB |
1402 | u32 val; |
1403 | ||
7feb8b88 | 1404 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1405 | for_each_sprite(dev_priv, pipe, sprite) { |
7feb8b88 | 1406 | val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1407 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1408 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1409 | sprite, pipe_name(pipe)); | |
1410 | } | |
1411 | } else if (IS_VALLEYVIEW(dev)) { | |
3bdcfc0c | 1412 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 1413 | reg = SPCNTR(pipe, sprite); |
20674eef | 1414 | val = I915_READ(reg); |
e2c719b7 | 1415 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1416 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1417 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1418 | } |
1419 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
1420 | reg = SPRCTL(pipe); | |
19332d7a | 1421 | val = I915_READ(reg); |
e2c719b7 | 1422 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1423 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1424 | plane_name(pipe), pipe_name(pipe)); |
1425 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1426 | reg = DVSCNTR(pipe); | |
19332d7a | 1427 | val = I915_READ(reg); |
e2c719b7 | 1428 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1429 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1430 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1431 | } |
1432 | } | |
1433 | ||
08c71e5e VS |
1434 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1435 | { | |
e2c719b7 | 1436 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1437 | drm_crtc_vblank_put(crtc); |
1438 | } | |
1439 | ||
89eff4be | 1440 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1441 | { |
1442 | u32 val; | |
1443 | bool enabled; | |
1444 | ||
e2c719b7 | 1445 | I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1446 | |
92f2584a JB |
1447 | val = I915_READ(PCH_DREF_CONTROL); |
1448 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1449 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
e2c719b7 | 1450 | I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
92f2584a JB |
1451 | } |
1452 | ||
ab9412ba DV |
1453 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1454 | enum pipe pipe) | |
92f2584a JB |
1455 | { |
1456 | int reg; | |
1457 | u32 val; | |
1458 | bool enabled; | |
1459 | ||
ab9412ba | 1460 | reg = PCH_TRANSCONF(pipe); |
92f2584a JB |
1461 | val = I915_READ(reg); |
1462 | enabled = !!(val & TRANS_ENABLE); | |
e2c719b7 | 1463 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1464 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1465 | pipe_name(pipe)); | |
92f2584a JB |
1466 | } |
1467 | ||
4e634389 KP |
1468 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1469 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1470 | { |
1471 | if ((val & DP_PORT_EN) == 0) | |
1472 | return false; | |
1473 | ||
1474 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1475 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1476 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1477 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1478 | return false; | |
44f37d1f CML |
1479 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1480 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1481 | return false; | |
f0575e92 KP |
1482 | } else { |
1483 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1484 | return false; | |
1485 | } | |
1486 | return true; | |
1487 | } | |
1488 | ||
1519b995 KP |
1489 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1490 | enum pipe pipe, u32 val) | |
1491 | { | |
dc0fa718 | 1492 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1493 | return false; |
1494 | ||
1495 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1496 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1497 | return false; |
44f37d1f CML |
1498 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1499 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1500 | return false; | |
1519b995 | 1501 | } else { |
dc0fa718 | 1502 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1503 | return false; |
1504 | } | |
1505 | return true; | |
1506 | } | |
1507 | ||
1508 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1509 | enum pipe pipe, u32 val) | |
1510 | { | |
1511 | if ((val & LVDS_PORT_EN) == 0) | |
1512 | return false; | |
1513 | ||
1514 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1515 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1516 | return false; | |
1517 | } else { | |
1518 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1519 | return false; | |
1520 | } | |
1521 | return true; | |
1522 | } | |
1523 | ||
1524 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1525 | enum pipe pipe, u32 val) | |
1526 | { | |
1527 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1528 | return false; | |
1529 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1530 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1531 | return false; | |
1532 | } else { | |
1533 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1534 | return false; | |
1535 | } | |
1536 | return true; | |
1537 | } | |
1538 | ||
291906f1 | 1539 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1540 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1541 | { |
47a05eca | 1542 | u32 val = I915_READ(reg); |
e2c719b7 | 1543 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1544 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1545 | reg, pipe_name(pipe)); |
de9a35ab | 1546 | |
e2c719b7 | 1547 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1548 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1549 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1550 | } |
1551 | ||
1552 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1553 | enum pipe pipe, int reg) | |
1554 | { | |
47a05eca | 1555 | u32 val = I915_READ(reg); |
e2c719b7 | 1556 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1557 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1558 | reg, pipe_name(pipe)); |
de9a35ab | 1559 | |
e2c719b7 | 1560 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1561 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1562 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1563 | } |
1564 | ||
1565 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1566 | enum pipe pipe) | |
1567 | { | |
1568 | int reg; | |
1569 | u32 val; | |
291906f1 | 1570 | |
f0575e92 KP |
1571 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1572 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1573 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1574 | |
1575 | reg = PCH_ADPA; | |
1576 | val = I915_READ(reg); | |
e2c719b7 | 1577 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1578 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1579 | pipe_name(pipe)); |
291906f1 JB |
1580 | |
1581 | reg = PCH_LVDS; | |
1582 | val = I915_READ(reg); | |
e2c719b7 | 1583 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1584 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1585 | pipe_name(pipe)); |
291906f1 | 1586 | |
e2debe91 PZ |
1587 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1588 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1589 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1590 | } |
1591 | ||
40e9cf64 JB |
1592 | static void intel_init_dpio(struct drm_device *dev) |
1593 | { | |
1594 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1595 | ||
1596 | if (!IS_VALLEYVIEW(dev)) | |
1597 | return; | |
1598 | ||
a09caddd CML |
1599 | /* |
1600 | * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), | |
1601 | * CHV x1 PHY (DP/HDMI D) | |
1602 | * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) | |
1603 | */ | |
1604 | if (IS_CHERRYVIEW(dev)) { | |
1605 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; | |
1606 | DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO; | |
1607 | } else { | |
1608 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; | |
1609 | } | |
5382f5f3 JB |
1610 | } |
1611 | ||
d288f65f | 1612 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1613 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1614 | { |
426115cf DV |
1615 | struct drm_device *dev = crtc->base.dev; |
1616 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1617 | int reg = DPLL(crtc->pipe); | |
d288f65f | 1618 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
87442f73 | 1619 | |
426115cf | 1620 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 DV |
1621 | |
1622 | /* No really, not for ILK+ */ | |
1623 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
1624 | ||
1625 | /* PLL is protected by panel, make sure we can write it */ | |
6a9e7363 | 1626 | if (IS_MOBILE(dev_priv->dev)) |
426115cf | 1627 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1628 | |
426115cf DV |
1629 | I915_WRITE(reg, dpll); |
1630 | POSTING_READ(reg); | |
1631 | udelay(150); | |
1632 | ||
1633 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1634 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1635 | ||
d288f65f | 1636 | I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); |
426115cf | 1637 | POSTING_READ(DPLL_MD(crtc->pipe)); |
87442f73 DV |
1638 | |
1639 | /* We do this three times for luck */ | |
426115cf | 1640 | I915_WRITE(reg, dpll); |
87442f73 DV |
1641 | POSTING_READ(reg); |
1642 | udelay(150); /* wait for warmup */ | |
426115cf | 1643 | I915_WRITE(reg, dpll); |
87442f73 DV |
1644 | POSTING_READ(reg); |
1645 | udelay(150); /* wait for warmup */ | |
426115cf | 1646 | I915_WRITE(reg, dpll); |
87442f73 DV |
1647 | POSTING_READ(reg); |
1648 | udelay(150); /* wait for warmup */ | |
1649 | } | |
1650 | ||
d288f65f | 1651 | static void chv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1652 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
1653 | { |
1654 | struct drm_device *dev = crtc->base.dev; | |
1655 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1656 | int pipe = crtc->pipe; | |
1657 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1658 | u32 tmp; |
1659 | ||
1660 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1661 | ||
1662 | BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); | |
1663 | ||
a580516d | 1664 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1665 | |
1666 | /* Enable back the 10bit clock to display controller */ | |
1667 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1668 | tmp |= DPIO_DCLKP_EN; | |
1669 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1670 | ||
54433e91 VS |
1671 | mutex_unlock(&dev_priv->sb_lock); |
1672 | ||
9d556c99 CML |
1673 | /* |
1674 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1675 | */ | |
1676 | udelay(1); | |
1677 | ||
1678 | /* Enable PLL */ | |
d288f65f | 1679 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1680 | |
1681 | /* Check PLL is locked */ | |
a11b0703 | 1682 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1683 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1684 | ||
a11b0703 | 1685 | /* not sure when this should be written */ |
d288f65f | 1686 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
a11b0703 | 1687 | POSTING_READ(DPLL_MD(pipe)); |
9d556c99 CML |
1688 | } |
1689 | ||
1c4e0274 VS |
1690 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1691 | { | |
1692 | struct intel_crtc *crtc; | |
1693 | int count = 0; | |
1694 | ||
1695 | for_each_intel_crtc(dev, crtc) | |
1696 | count += crtc->active && | |
409ee761 | 1697 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
1c4e0274 VS |
1698 | |
1699 | return count; | |
1700 | } | |
1701 | ||
66e3d5c0 | 1702 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1703 | { |
66e3d5c0 DV |
1704 | struct drm_device *dev = crtc->base.dev; |
1705 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1706 | int reg = DPLL(crtc->pipe); | |
6e3c9717 | 1707 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1708 | |
66e3d5c0 | 1709 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1710 | |
63d7bbe9 | 1711 | /* No really, not for ILK+ */ |
3d13ef2e | 1712 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1713 | |
1714 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1715 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1716 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1717 | |
1c4e0274 VS |
1718 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1719 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1720 | /* | |
1721 | * It appears to be important that we don't enable this | |
1722 | * for the current pipe before otherwise configuring the | |
1723 | * PLL. No idea how this should be handled if multiple | |
1724 | * DVO outputs are enabled simultaneosly. | |
1725 | */ | |
1726 | dpll |= DPLL_DVO_2X_MODE; | |
1727 | I915_WRITE(DPLL(!crtc->pipe), | |
1728 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1729 | } | |
66e3d5c0 DV |
1730 | |
1731 | /* Wait for the clocks to stabilize. */ | |
1732 | POSTING_READ(reg); | |
1733 | udelay(150); | |
1734 | ||
1735 | if (INTEL_INFO(dev)->gen >= 4) { | |
1736 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1737 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1738 | } else { |
1739 | /* The pixel multiplier can only be updated once the | |
1740 | * DPLL is enabled and the clocks are stable. | |
1741 | * | |
1742 | * So write it again. | |
1743 | */ | |
1744 | I915_WRITE(reg, dpll); | |
1745 | } | |
63d7bbe9 JB |
1746 | |
1747 | /* We do this three times for luck */ | |
66e3d5c0 | 1748 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1749 | POSTING_READ(reg); |
1750 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1751 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1752 | POSTING_READ(reg); |
1753 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1754 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1755 | POSTING_READ(reg); |
1756 | udelay(150); /* wait for warmup */ | |
1757 | } | |
1758 | ||
1759 | /** | |
50b44a44 | 1760 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1761 | * @dev_priv: i915 private structure |
1762 | * @pipe: pipe PLL to disable | |
1763 | * | |
1764 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1765 | * | |
1766 | * Note! This is for pre-ILK only. | |
1767 | */ | |
1c4e0274 | 1768 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1769 | { |
1c4e0274 VS |
1770 | struct drm_device *dev = crtc->base.dev; |
1771 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1772 | enum pipe pipe = crtc->pipe; | |
1773 | ||
1774 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1775 | if (IS_I830(dev) && | |
409ee761 | 1776 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
1c4e0274 VS |
1777 | intel_num_dvo_pipes(dev) == 1) { |
1778 | I915_WRITE(DPLL(PIPE_B), | |
1779 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1780 | I915_WRITE(DPLL(PIPE_A), | |
1781 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1782 | } | |
1783 | ||
b6b5d049 VS |
1784 | /* Don't disable pipe or pipe PLLs if needed */ |
1785 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1786 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1787 | return; |
1788 | ||
1789 | /* Make sure the pipe isn't still relying on us */ | |
1790 | assert_pipe_disabled(dev_priv, pipe); | |
1791 | ||
50b44a44 DV |
1792 | I915_WRITE(DPLL(pipe), 0); |
1793 | POSTING_READ(DPLL(pipe)); | |
63d7bbe9 JB |
1794 | } |
1795 | ||
f6071166 JB |
1796 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1797 | { | |
1798 | u32 val = 0; | |
1799 | ||
1800 | /* Make sure the pipe isn't still relying on us */ | |
1801 | assert_pipe_disabled(dev_priv, pipe); | |
1802 | ||
e5cbfbfb ID |
1803 | /* |
1804 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1805 | * The latter is needed for VGA hotplug / manual detection. | |
1806 | */ | |
f6071166 | 1807 | if (pipe == PIPE_B) |
e5cbfbfb | 1808 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; |
f6071166 JB |
1809 | I915_WRITE(DPLL(pipe), val); |
1810 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1811 | |
1812 | } | |
1813 | ||
1814 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1815 | { | |
d752048d | 1816 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1817 | u32 val; |
1818 | ||
a11b0703 VS |
1819 | /* Make sure the pipe isn't still relying on us */ |
1820 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1821 | |
a11b0703 | 1822 | /* Set PLL en = 0 */ |
d17ec4ce | 1823 | val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV; |
a11b0703 VS |
1824 | if (pipe != PIPE_A) |
1825 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1826 | I915_WRITE(DPLL(pipe), val); | |
1827 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1828 | |
a580516d | 1829 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1830 | |
1831 | /* Disable 10bit clock to display controller */ | |
1832 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1833 | val &= ~DPIO_DCLKP_EN; | |
1834 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1835 | ||
61407f6d VS |
1836 | /* disable left/right clock distribution */ |
1837 | if (pipe != PIPE_B) { | |
1838 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
1839 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
1840 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
1841 | } else { | |
1842 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
1843 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
1844 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
1845 | } | |
1846 | ||
a580516d | 1847 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1848 | } |
1849 | ||
e4607fcf | 1850 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1851 | struct intel_digital_port *dport, |
1852 | unsigned int expected_mask) | |
89b667f8 JB |
1853 | { |
1854 | u32 port_mask; | |
00fc31b7 | 1855 | int dpll_reg; |
89b667f8 | 1856 | |
e4607fcf CML |
1857 | switch (dport->port) { |
1858 | case PORT_B: | |
89b667f8 | 1859 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1860 | dpll_reg = DPLL(0); |
e4607fcf CML |
1861 | break; |
1862 | case PORT_C: | |
89b667f8 | 1863 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1864 | dpll_reg = DPLL(0); |
9b6de0a1 | 1865 | expected_mask <<= 4; |
00fc31b7 CML |
1866 | break; |
1867 | case PORT_D: | |
1868 | port_mask = DPLL_PORTD_READY_MASK; | |
1869 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1870 | break; |
1871 | default: | |
1872 | BUG(); | |
1873 | } | |
89b667f8 | 1874 | |
9b6de0a1 VS |
1875 | if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000)) |
1876 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", | |
1877 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1878 | } |
1879 | ||
b14b1055 DV |
1880 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1881 | { | |
1882 | struct drm_device *dev = crtc->base.dev; | |
1883 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1884 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
1885 | ||
be19f0ff CW |
1886 | if (WARN_ON(pll == NULL)) |
1887 | return; | |
1888 | ||
3e369b76 | 1889 | WARN_ON(!pll->config.crtc_mask); |
b14b1055 DV |
1890 | if (pll->active == 0) { |
1891 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
1892 | WARN_ON(pll->on); | |
1893 | assert_shared_dpll_disabled(dev_priv, pll); | |
1894 | ||
1895 | pll->mode_set(dev_priv, pll); | |
1896 | } | |
1897 | } | |
1898 | ||
92f2584a | 1899 | /** |
85b3894f | 1900 | * intel_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1901 | * @dev_priv: i915 private structure |
1902 | * @pipe: pipe PLL to enable | |
1903 | * | |
1904 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1905 | * drives the transcoder clock. | |
1906 | */ | |
85b3894f | 1907 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1908 | { |
3d13ef2e DL |
1909 | struct drm_device *dev = crtc->base.dev; |
1910 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1911 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1912 | |
87a875bb | 1913 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1914 | return; |
1915 | ||
3e369b76 | 1916 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1917 | return; |
ee7b9f93 | 1918 | |
74dd6928 | 1919 | DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n", |
46edb027 | 1920 | pll->name, pll->active, pll->on, |
e2b78267 | 1921 | crtc->base.base.id); |
92f2584a | 1922 | |
cdbd2316 DV |
1923 | if (pll->active++) { |
1924 | WARN_ON(!pll->on); | |
e9d6944e | 1925 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1926 | return; |
1927 | } | |
f4a091c7 | 1928 | WARN_ON(pll->on); |
ee7b9f93 | 1929 | |
bd2bb1b9 PZ |
1930 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
1931 | ||
46edb027 | 1932 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1933 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1934 | pll->on = true; |
92f2584a JB |
1935 | } |
1936 | ||
f6daaec2 | 1937 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1938 | { |
3d13ef2e DL |
1939 | struct drm_device *dev = crtc->base.dev; |
1940 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1941 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1942 | |
92f2584a | 1943 | /* PCH only available on ILK+ */ |
3d13ef2e | 1944 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
87a875bb | 1945 | if (WARN_ON(pll == NULL)) |
ee7b9f93 | 1946 | return; |
92f2584a | 1947 | |
3e369b76 | 1948 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1949 | return; |
7a419866 | 1950 | |
46edb027 DV |
1951 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1952 | pll->name, pll->active, pll->on, | |
e2b78267 | 1953 | crtc->base.base.id); |
7a419866 | 1954 | |
48da64a8 | 1955 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1956 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1957 | return; |
1958 | } | |
1959 | ||
e9d6944e | 1960 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1961 | WARN_ON(!pll->on); |
cdbd2316 | 1962 | if (--pll->active) |
7a419866 | 1963 | return; |
ee7b9f93 | 1964 | |
46edb027 | 1965 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1966 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1967 | pll->on = false; |
bd2bb1b9 PZ |
1968 | |
1969 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
92f2584a JB |
1970 | } |
1971 | ||
b8a4f404 PZ |
1972 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1973 | enum pipe pipe) | |
040484af | 1974 | { |
23670b32 | 1975 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1976 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1977 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
23670b32 | 1978 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1979 | |
1980 | /* PCH only available on ILK+ */ | |
55522f37 | 1981 | BUG_ON(!HAS_PCH_SPLIT(dev)); |
040484af JB |
1982 | |
1983 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1984 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1985 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1986 | |
1987 | /* FDI must be feeding us bits for PCH ports */ | |
1988 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1989 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1990 | ||
23670b32 DV |
1991 | if (HAS_PCH_CPT(dev)) { |
1992 | /* Workaround: Set the timing override bit before enabling the | |
1993 | * pch transcoder. */ | |
1994 | reg = TRANS_CHICKEN2(pipe); | |
1995 | val = I915_READ(reg); | |
1996 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1997 | I915_WRITE(reg, val); | |
59c859d6 | 1998 | } |
23670b32 | 1999 | |
ab9412ba | 2000 | reg = PCH_TRANSCONF(pipe); |
040484af | 2001 | val = I915_READ(reg); |
5f7f726d | 2002 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
2003 | |
2004 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
2005 | /* | |
c5de7c6f VS |
2006 | * Make the BPC in transcoder be consistent with |
2007 | * that in pipeconf reg. For HDMI we must use 8bpc | |
2008 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 2009 | */ |
dfd07d72 | 2010 | val &= ~PIPECONF_BPC_MASK; |
c5de7c6f VS |
2011 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI)) |
2012 | val |= PIPECONF_8BPC; | |
2013 | else | |
2014 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 2015 | } |
5f7f726d PZ |
2016 | |
2017 | val &= ~TRANS_INTERLACE_MASK; | |
2018 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 | 2019 | if (HAS_PCH_IBX(dev_priv->dev) && |
409ee761 | 2020 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
2021 | val |= TRANS_LEGACY_INTERLACED_ILK; |
2022 | else | |
2023 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
2024 | else |
2025 | val |= TRANS_PROGRESSIVE; | |
2026 | ||
040484af JB |
2027 | I915_WRITE(reg, val | TRANS_ENABLE); |
2028 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 2029 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
2030 | } |
2031 | ||
8fb033d7 | 2032 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 2033 | enum transcoder cpu_transcoder) |
040484af | 2034 | { |
8fb033d7 | 2035 | u32 val, pipeconf_val; |
8fb033d7 PZ |
2036 | |
2037 | /* PCH only available on ILK+ */ | |
55522f37 | 2038 | BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev)); |
8fb033d7 | 2039 | |
8fb033d7 | 2040 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 2041 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 2042 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 2043 | |
223a6fdf PZ |
2044 | /* Workaround: set timing override bit. */ |
2045 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 2046 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
2047 | I915_WRITE(_TRANSA_CHICKEN2, val); |
2048 | ||
25f3ef11 | 2049 | val = TRANS_ENABLE; |
937bb610 | 2050 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 2051 | |
9a76b1c6 PZ |
2052 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
2053 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 2054 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
2055 | else |
2056 | val |= TRANS_PROGRESSIVE; | |
2057 | ||
ab9412ba DV |
2058 | I915_WRITE(LPT_TRANSCONF, val); |
2059 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 2060 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
2061 | } |
2062 | ||
b8a4f404 PZ |
2063 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
2064 | enum pipe pipe) | |
040484af | 2065 | { |
23670b32 DV |
2066 | struct drm_device *dev = dev_priv->dev; |
2067 | uint32_t reg, val; | |
040484af JB |
2068 | |
2069 | /* FDI relies on the transcoder */ | |
2070 | assert_fdi_tx_disabled(dev_priv, pipe); | |
2071 | assert_fdi_rx_disabled(dev_priv, pipe); | |
2072 | ||
291906f1 JB |
2073 | /* Ports must be off as well */ |
2074 | assert_pch_ports_disabled(dev_priv, pipe); | |
2075 | ||
ab9412ba | 2076 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
2077 | val = I915_READ(reg); |
2078 | val &= ~TRANS_ENABLE; | |
2079 | I915_WRITE(reg, val); | |
2080 | /* wait for PCH transcoder off, transcoder state */ | |
2081 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 2082 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 DV |
2083 | |
2084 | if (!HAS_PCH_IBX(dev)) { | |
2085 | /* Workaround: Clear the timing override chicken bit again. */ | |
2086 | reg = TRANS_CHICKEN2(pipe); | |
2087 | val = I915_READ(reg); | |
2088 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
2089 | I915_WRITE(reg, val); | |
2090 | } | |
040484af JB |
2091 | } |
2092 | ||
ab4d966c | 2093 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 2094 | { |
8fb033d7 PZ |
2095 | u32 val; |
2096 | ||
ab9412ba | 2097 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 2098 | val &= ~TRANS_ENABLE; |
ab9412ba | 2099 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 2100 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 2101 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 2102 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
2103 | |
2104 | /* Workaround: clear timing override bit. */ | |
2105 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 2106 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 2107 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
2108 | } |
2109 | ||
b24e7179 | 2110 | /** |
309cfea8 | 2111 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 2112 | * @crtc: crtc responsible for the pipe |
b24e7179 | 2113 | * |
0372264a | 2114 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 2115 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 2116 | */ |
e1fdc473 | 2117 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2118 | { |
0372264a PZ |
2119 | struct drm_device *dev = crtc->base.dev; |
2120 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2121 | enum pipe pipe = crtc->pipe; | |
702e7a56 PZ |
2122 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
2123 | pipe); | |
1a240d4d | 2124 | enum pipe pch_transcoder; |
b24e7179 JB |
2125 | int reg; |
2126 | u32 val; | |
2127 | ||
58c6eaa2 | 2128 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 2129 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
2130 | assert_sprites_disabled(dev_priv, pipe); |
2131 | ||
681e5811 | 2132 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
2133 | pch_transcoder = TRANSCODER_A; |
2134 | else | |
2135 | pch_transcoder = pipe; | |
2136 | ||
b24e7179 JB |
2137 | /* |
2138 | * A pipe without a PLL won't actually be able to drive bits from | |
2139 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
2140 | * need the check. | |
2141 | */ | |
50360403 | 2142 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) |
409ee761 | 2143 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
2144 | assert_dsi_pll_enabled(dev_priv); |
2145 | else | |
2146 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2147 | else { |
6e3c9717 | 2148 | if (crtc->config->has_pch_encoder) { |
040484af | 2149 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2150 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2151 | assert_fdi_tx_pll_enabled(dev_priv, |
2152 | (enum pipe) cpu_transcoder); | |
040484af JB |
2153 | } |
2154 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2155 | } | |
b24e7179 | 2156 | |
702e7a56 | 2157 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2158 | val = I915_READ(reg); |
7ad25d48 | 2159 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
2160 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
2161 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 2162 | return; |
7ad25d48 | 2163 | } |
00d70b15 CW |
2164 | |
2165 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2166 | POSTING_READ(reg); |
b24e7179 JB |
2167 | } |
2168 | ||
2169 | /** | |
309cfea8 | 2170 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2171 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2172 | * |
575f7ab7 VS |
2173 | * Disable the pipe of @crtc, making sure that various hardware |
2174 | * specific requirements are met, if applicable, e.g. plane | |
2175 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2176 | * |
2177 | * Will wait until the pipe has shut down before returning. | |
2178 | */ | |
575f7ab7 | 2179 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2180 | { |
575f7ab7 | 2181 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
6e3c9717 | 2182 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2183 | enum pipe pipe = crtc->pipe; |
b24e7179 JB |
2184 | int reg; |
2185 | u32 val; | |
2186 | ||
2187 | /* | |
2188 | * Make sure planes won't keep trying to pump pixels to us, | |
2189 | * or we might hang the display. | |
2190 | */ | |
2191 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2192 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2193 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2194 | |
702e7a56 | 2195 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2196 | val = I915_READ(reg); |
00d70b15 CW |
2197 | if ((val & PIPECONF_ENABLE) == 0) |
2198 | return; | |
2199 | ||
67adc644 VS |
2200 | /* |
2201 | * Double wide has implications for planes | |
2202 | * so best keep it disabled when not needed. | |
2203 | */ | |
6e3c9717 | 2204 | if (crtc->config->double_wide) |
67adc644 VS |
2205 | val &= ~PIPECONF_DOUBLE_WIDE; |
2206 | ||
2207 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2208 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2209 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2210 | val &= ~PIPECONF_ENABLE; |
2211 | ||
2212 | I915_WRITE(reg, val); | |
2213 | if ((val & PIPECONF_ENABLE) == 0) | |
2214 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2215 | } |
2216 | ||
2217 | /** | |
262ca2b0 | 2218 | * intel_enable_primary_hw_plane - enable the primary plane on a given pipe |
fdd508a6 VS |
2219 | * @plane: plane to be enabled |
2220 | * @crtc: crtc for the plane | |
b24e7179 | 2221 | * |
fdd508a6 | 2222 | * Enable @plane on @crtc, making sure that the pipe is running first. |
b24e7179 | 2223 | */ |
fdd508a6 VS |
2224 | static void intel_enable_primary_hw_plane(struct drm_plane *plane, |
2225 | struct drm_crtc *crtc) | |
b24e7179 | 2226 | { |
fdd508a6 VS |
2227 | struct drm_device *dev = plane->dev; |
2228 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2229 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b24e7179 JB |
2230 | |
2231 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
fdd508a6 | 2232 | assert_pipe_enabled(dev_priv, intel_crtc->pipe); |
b70709a6 | 2233 | to_intel_plane_state(plane->state)->visible = true; |
939c2fe8 | 2234 | |
fdd508a6 VS |
2235 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
2236 | crtc->x, crtc->y); | |
b24e7179 JB |
2237 | } |
2238 | ||
693db184 CW |
2239 | static bool need_vtd_wa(struct drm_device *dev) |
2240 | { | |
2241 | #ifdef CONFIG_INTEL_IOMMU | |
2242 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2243 | return true; | |
2244 | #endif | |
2245 | return false; | |
2246 | } | |
2247 | ||
50470bb0 | 2248 | unsigned int |
6761dd31 TU |
2249 | intel_tile_height(struct drm_device *dev, uint32_t pixel_format, |
2250 | uint64_t fb_format_modifier) | |
a57ce0b2 | 2251 | { |
6761dd31 TU |
2252 | unsigned int tile_height; |
2253 | uint32_t pixel_bytes; | |
a57ce0b2 | 2254 | |
b5d0e9bf DL |
2255 | switch (fb_format_modifier) { |
2256 | case DRM_FORMAT_MOD_NONE: | |
2257 | tile_height = 1; | |
2258 | break; | |
2259 | case I915_FORMAT_MOD_X_TILED: | |
2260 | tile_height = IS_GEN2(dev) ? 16 : 8; | |
2261 | break; | |
2262 | case I915_FORMAT_MOD_Y_TILED: | |
2263 | tile_height = 32; | |
2264 | break; | |
2265 | case I915_FORMAT_MOD_Yf_TILED: | |
6761dd31 TU |
2266 | pixel_bytes = drm_format_plane_cpp(pixel_format, 0); |
2267 | switch (pixel_bytes) { | |
b5d0e9bf | 2268 | default: |
6761dd31 | 2269 | case 1: |
b5d0e9bf DL |
2270 | tile_height = 64; |
2271 | break; | |
6761dd31 TU |
2272 | case 2: |
2273 | case 4: | |
b5d0e9bf DL |
2274 | tile_height = 32; |
2275 | break; | |
6761dd31 | 2276 | case 8: |
b5d0e9bf DL |
2277 | tile_height = 16; |
2278 | break; | |
6761dd31 | 2279 | case 16: |
b5d0e9bf DL |
2280 | WARN_ONCE(1, |
2281 | "128-bit pixels are not supported for display!"); | |
2282 | tile_height = 16; | |
2283 | break; | |
2284 | } | |
2285 | break; | |
2286 | default: | |
2287 | MISSING_CASE(fb_format_modifier); | |
2288 | tile_height = 1; | |
2289 | break; | |
2290 | } | |
091df6cb | 2291 | |
6761dd31 TU |
2292 | return tile_height; |
2293 | } | |
2294 | ||
2295 | unsigned int | |
2296 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
2297 | uint32_t pixel_format, uint64_t fb_format_modifier) | |
2298 | { | |
2299 | return ALIGN(height, intel_tile_height(dev, pixel_format, | |
2300 | fb_format_modifier)); | |
a57ce0b2 JB |
2301 | } |
2302 | ||
f64b98cd TU |
2303 | static int |
2304 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb, | |
2305 | const struct drm_plane_state *plane_state) | |
2306 | { | |
50470bb0 | 2307 | struct intel_rotation_info *info = &view->rotation_info; |
50470bb0 | 2308 | |
f64b98cd TU |
2309 | *view = i915_ggtt_view_normal; |
2310 | ||
50470bb0 TU |
2311 | if (!plane_state) |
2312 | return 0; | |
2313 | ||
121920fa | 2314 | if (!intel_rotation_90_or_270(plane_state->rotation)) |
50470bb0 TU |
2315 | return 0; |
2316 | ||
9abc4648 | 2317 | *view = i915_ggtt_view_rotated; |
50470bb0 TU |
2318 | |
2319 | info->height = fb->height; | |
2320 | info->pixel_format = fb->pixel_format; | |
2321 | info->pitch = fb->pitches[0]; | |
2322 | info->fb_modifier = fb->modifier[0]; | |
2323 | ||
f64b98cd TU |
2324 | return 0; |
2325 | } | |
2326 | ||
127bd2ac | 2327 | int |
850c4cdc TU |
2328 | intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
2329 | struct drm_framebuffer *fb, | |
82bc3b2d | 2330 | const struct drm_plane_state *plane_state, |
a4872ba6 | 2331 | struct intel_engine_cs *pipelined) |
6b95a207 | 2332 | { |
850c4cdc | 2333 | struct drm_device *dev = fb->dev; |
ce453d81 | 2334 | struct drm_i915_private *dev_priv = dev->dev_private; |
850c4cdc | 2335 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2336 | struct i915_ggtt_view view; |
6b95a207 KH |
2337 | u32 alignment; |
2338 | int ret; | |
2339 | ||
ebcdd39e MR |
2340 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2341 | ||
7b911adc TU |
2342 | switch (fb->modifier[0]) { |
2343 | case DRM_FORMAT_MOD_NONE: | |
1fada4cc DL |
2344 | if (INTEL_INFO(dev)->gen >= 9) |
2345 | alignment = 256 * 1024; | |
2346 | else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) | |
534843da | 2347 | alignment = 128 * 1024; |
a6c45cf0 | 2348 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
2349 | alignment = 4 * 1024; |
2350 | else | |
2351 | alignment = 64 * 1024; | |
6b95a207 | 2352 | break; |
7b911adc | 2353 | case I915_FORMAT_MOD_X_TILED: |
1fada4cc DL |
2354 | if (INTEL_INFO(dev)->gen >= 9) |
2355 | alignment = 256 * 1024; | |
2356 | else { | |
2357 | /* pin() will align the object as required by fence */ | |
2358 | alignment = 0; | |
2359 | } | |
6b95a207 | 2360 | break; |
7b911adc | 2361 | case I915_FORMAT_MOD_Y_TILED: |
1327b9a1 DL |
2362 | case I915_FORMAT_MOD_Yf_TILED: |
2363 | if (WARN_ONCE(INTEL_INFO(dev)->gen < 9, | |
2364 | "Y tiling bo slipped through, driver bug!\n")) | |
2365 | return -EINVAL; | |
2366 | alignment = 1 * 1024 * 1024; | |
2367 | break; | |
6b95a207 | 2368 | default: |
7b911adc TU |
2369 | MISSING_CASE(fb->modifier[0]); |
2370 | return -EINVAL; | |
6b95a207 KH |
2371 | } |
2372 | ||
f64b98cd TU |
2373 | ret = intel_fill_fb_ggtt_view(&view, fb, plane_state); |
2374 | if (ret) | |
2375 | return ret; | |
2376 | ||
693db184 CW |
2377 | /* Note that the w/a also requires 64 PTE of padding following the |
2378 | * bo. We currently fill all unused PTE with the shadow page and so | |
2379 | * we should always have valid PTE following the scanout preventing | |
2380 | * the VT-d warning. | |
2381 | */ | |
2382 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2383 | alignment = 256 * 1024; | |
2384 | ||
d6dd6843 PZ |
2385 | /* |
2386 | * Global gtt pte registers are special registers which actually forward | |
2387 | * writes to a chunk of system memory. Which means that there is no risk | |
2388 | * that the register values disappear as soon as we call | |
2389 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2390 | * pin/unpin/fence and not more. | |
2391 | */ | |
2392 | intel_runtime_pm_get(dev_priv); | |
2393 | ||
ce453d81 | 2394 | dev_priv->mm.interruptible = false; |
e6617330 | 2395 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined, |
f64b98cd | 2396 | &view); |
48b956c5 | 2397 | if (ret) |
ce453d81 | 2398 | goto err_interruptible; |
6b95a207 KH |
2399 | |
2400 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2401 | * fence, whereas 965+ only requires a fence if using | |
2402 | * framebuffer compression. For simplicity, we always install | |
2403 | * a fence as the cost is not that onerous. | |
2404 | */ | |
06d98131 | 2405 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
2406 | if (ret) |
2407 | goto err_unpin; | |
1690e1eb | 2408 | |
9a5a53b3 | 2409 | i915_gem_object_pin_fence(obj); |
6b95a207 | 2410 | |
ce453d81 | 2411 | dev_priv->mm.interruptible = true; |
d6dd6843 | 2412 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2413 | return 0; |
48b956c5 CW |
2414 | |
2415 | err_unpin: | |
f64b98cd | 2416 | i915_gem_object_unpin_from_display_plane(obj, &view); |
ce453d81 CW |
2417 | err_interruptible: |
2418 | dev_priv->mm.interruptible = true; | |
d6dd6843 | 2419 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2420 | return ret; |
6b95a207 KH |
2421 | } |
2422 | ||
82bc3b2d TU |
2423 | static void intel_unpin_fb_obj(struct drm_framebuffer *fb, |
2424 | const struct drm_plane_state *plane_state) | |
1690e1eb | 2425 | { |
82bc3b2d | 2426 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd TU |
2427 | struct i915_ggtt_view view; |
2428 | int ret; | |
82bc3b2d | 2429 | |
ebcdd39e MR |
2430 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2431 | ||
f64b98cd TU |
2432 | ret = intel_fill_fb_ggtt_view(&view, fb, plane_state); |
2433 | WARN_ONCE(ret, "Couldn't get view from plane state!"); | |
2434 | ||
1690e1eb | 2435 | i915_gem_object_unpin_fence(obj); |
f64b98cd | 2436 | i915_gem_object_unpin_from_display_plane(obj, &view); |
1690e1eb CW |
2437 | } |
2438 | ||
c2c75131 DV |
2439 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2440 | * is assumed to be a power-of-two. */ | |
bc752862 CW |
2441 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
2442 | unsigned int tiling_mode, | |
2443 | unsigned int cpp, | |
2444 | unsigned int pitch) | |
c2c75131 | 2445 | { |
bc752862 CW |
2446 | if (tiling_mode != I915_TILING_NONE) { |
2447 | unsigned int tile_rows, tiles; | |
c2c75131 | 2448 | |
bc752862 CW |
2449 | tile_rows = *y / 8; |
2450 | *y %= 8; | |
c2c75131 | 2451 | |
bc752862 CW |
2452 | tiles = *x / (512/cpp); |
2453 | *x %= 512/cpp; | |
2454 | ||
2455 | return tile_rows * pitch * 8 + tiles * 4096; | |
2456 | } else { | |
2457 | unsigned int offset; | |
2458 | ||
2459 | offset = *y * pitch + *x * cpp; | |
2460 | *y = 0; | |
2461 | *x = (offset & 4095) / cpp; | |
2462 | return offset & -4096; | |
2463 | } | |
c2c75131 DV |
2464 | } |
2465 | ||
b35d63fa | 2466 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2467 | { |
2468 | switch (format) { | |
2469 | case DISPPLANE_8BPP: | |
2470 | return DRM_FORMAT_C8; | |
2471 | case DISPPLANE_BGRX555: | |
2472 | return DRM_FORMAT_XRGB1555; | |
2473 | case DISPPLANE_BGRX565: | |
2474 | return DRM_FORMAT_RGB565; | |
2475 | default: | |
2476 | case DISPPLANE_BGRX888: | |
2477 | return DRM_FORMAT_XRGB8888; | |
2478 | case DISPPLANE_RGBX888: | |
2479 | return DRM_FORMAT_XBGR8888; | |
2480 | case DISPPLANE_BGRX101010: | |
2481 | return DRM_FORMAT_XRGB2101010; | |
2482 | case DISPPLANE_RGBX101010: | |
2483 | return DRM_FORMAT_XBGR2101010; | |
2484 | } | |
2485 | } | |
2486 | ||
bc8d7dff DL |
2487 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2488 | { | |
2489 | switch (format) { | |
2490 | case PLANE_CTL_FORMAT_RGB_565: | |
2491 | return DRM_FORMAT_RGB565; | |
2492 | default: | |
2493 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2494 | if (rgb_order) { | |
2495 | if (alpha) | |
2496 | return DRM_FORMAT_ABGR8888; | |
2497 | else | |
2498 | return DRM_FORMAT_XBGR8888; | |
2499 | } else { | |
2500 | if (alpha) | |
2501 | return DRM_FORMAT_ARGB8888; | |
2502 | else | |
2503 | return DRM_FORMAT_XRGB8888; | |
2504 | } | |
2505 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2506 | if (rgb_order) | |
2507 | return DRM_FORMAT_XBGR2101010; | |
2508 | else | |
2509 | return DRM_FORMAT_XRGB2101010; | |
2510 | } | |
2511 | } | |
2512 | ||
5724dbd1 | 2513 | static bool |
f6936e29 DV |
2514 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2515 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2516 | { |
2517 | struct drm_device *dev = crtc->base.dev; | |
2518 | struct drm_i915_gem_object *obj = NULL; | |
2519 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2520 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2521 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2522 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2523 | PAGE_SIZE); | |
2524 | ||
2525 | size_aligned -= base_aligned; | |
46f297fb | 2526 | |
ff2652ea CW |
2527 | if (plane_config->size == 0) |
2528 | return false; | |
2529 | ||
f37b5c2b DV |
2530 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2531 | base_aligned, | |
2532 | base_aligned, | |
2533 | size_aligned); | |
46f297fb | 2534 | if (!obj) |
484b41dd | 2535 | return false; |
46f297fb | 2536 | |
49af449b DL |
2537 | obj->tiling_mode = plane_config->tiling; |
2538 | if (obj->tiling_mode == I915_TILING_X) | |
6bf129df | 2539 | obj->stride = fb->pitches[0]; |
46f297fb | 2540 | |
6bf129df DL |
2541 | mode_cmd.pixel_format = fb->pixel_format; |
2542 | mode_cmd.width = fb->width; | |
2543 | mode_cmd.height = fb->height; | |
2544 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2545 | mode_cmd.modifier[0] = fb->modifier[0]; |
2546 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb JB |
2547 | |
2548 | mutex_lock(&dev->struct_mutex); | |
6bf129df | 2549 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2550 | &mode_cmd, obj)) { |
46f297fb JB |
2551 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2552 | goto out_unref_obj; | |
2553 | } | |
46f297fb | 2554 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2555 | |
f6936e29 | 2556 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2557 | return true; |
46f297fb JB |
2558 | |
2559 | out_unref_obj: | |
2560 | drm_gem_object_unreference(&obj->base); | |
2561 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2562 | return false; |
2563 | } | |
2564 | ||
afd65eb4 MR |
2565 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2566 | static void | |
2567 | update_state_fb(struct drm_plane *plane) | |
2568 | { | |
2569 | if (plane->fb == plane->state->fb) | |
2570 | return; | |
2571 | ||
2572 | if (plane->state->fb) | |
2573 | drm_framebuffer_unreference(plane->state->fb); | |
2574 | plane->state->fb = plane->fb; | |
2575 | if (plane->state->fb) | |
2576 | drm_framebuffer_reference(plane->state->fb); | |
2577 | } | |
2578 | ||
5724dbd1 | 2579 | static void |
f6936e29 DV |
2580 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2581 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2582 | { |
2583 | struct drm_device *dev = intel_crtc->base.dev; | |
d9ceb816 | 2584 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd JB |
2585 | struct drm_crtc *c; |
2586 | struct intel_crtc *i; | |
2ff8fde1 | 2587 | struct drm_i915_gem_object *obj; |
88595ac9 DV |
2588 | struct drm_plane *primary = intel_crtc->base.primary; |
2589 | struct drm_framebuffer *fb; | |
484b41dd | 2590 | |
2d14030b | 2591 | if (!plane_config->fb) |
484b41dd JB |
2592 | return; |
2593 | ||
f6936e29 | 2594 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2595 | fb = &plane_config->fb->base; |
2596 | goto valid_fb; | |
f55548b5 | 2597 | } |
484b41dd | 2598 | |
2d14030b | 2599 | kfree(plane_config->fb); |
484b41dd JB |
2600 | |
2601 | /* | |
2602 | * Failed to alloc the obj, check to see if we should share | |
2603 | * an fb with another CRTC instead | |
2604 | */ | |
70e1e0ec | 2605 | for_each_crtc(dev, c) { |
484b41dd JB |
2606 | i = to_intel_crtc(c); |
2607 | ||
2608 | if (c == &intel_crtc->base) | |
2609 | continue; | |
2610 | ||
2ff8fde1 MR |
2611 | if (!i->active) |
2612 | continue; | |
2613 | ||
88595ac9 DV |
2614 | fb = c->primary->fb; |
2615 | if (!fb) | |
484b41dd JB |
2616 | continue; |
2617 | ||
88595ac9 | 2618 | obj = intel_fb_obj(fb); |
2ff8fde1 | 2619 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
88595ac9 DV |
2620 | drm_framebuffer_reference(fb); |
2621 | goto valid_fb; | |
484b41dd JB |
2622 | } |
2623 | } | |
88595ac9 DV |
2624 | |
2625 | return; | |
2626 | ||
2627 | valid_fb: | |
2628 | obj = intel_fb_obj(fb); | |
2629 | if (obj->tiling_mode != I915_TILING_NONE) | |
2630 | dev_priv->preserve_bios_swizzle = true; | |
2631 | ||
2632 | primary->fb = fb; | |
2633 | primary->state->crtc = &intel_crtc->base; | |
2634 | primary->crtc = &intel_crtc->base; | |
2635 | update_state_fb(primary); | |
2636 | obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); | |
46f297fb JB |
2637 | } |
2638 | ||
29b9bde6 DV |
2639 | static void i9xx_update_primary_plane(struct drm_crtc *crtc, |
2640 | struct drm_framebuffer *fb, | |
2641 | int x, int y) | |
81255565 JB |
2642 | { |
2643 | struct drm_device *dev = crtc->dev; | |
2644 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2645 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
2646 | struct drm_plane *primary = crtc->primary; |
2647 | bool visible = to_intel_plane_state(primary->state)->visible; | |
c9ba6fad | 2648 | struct drm_i915_gem_object *obj; |
81255565 | 2649 | int plane = intel_crtc->plane; |
e506a0c6 | 2650 | unsigned long linear_offset; |
81255565 | 2651 | u32 dspcntr; |
f45651ba | 2652 | u32 reg = DSPCNTR(plane); |
48404c1e | 2653 | int pixel_size; |
f45651ba | 2654 | |
b70709a6 | 2655 | if (!visible || !fb) { |
fdd508a6 VS |
2656 | I915_WRITE(reg, 0); |
2657 | if (INTEL_INFO(dev)->gen >= 4) | |
2658 | I915_WRITE(DSPSURF(plane), 0); | |
2659 | else | |
2660 | I915_WRITE(DSPADDR(plane), 0); | |
2661 | POSTING_READ(reg); | |
2662 | return; | |
2663 | } | |
2664 | ||
c9ba6fad VS |
2665 | obj = intel_fb_obj(fb); |
2666 | if (WARN_ON(obj == NULL)) | |
2667 | return; | |
2668 | ||
2669 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2670 | ||
f45651ba VS |
2671 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2672 | ||
fdd508a6 | 2673 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2674 | |
2675 | if (INTEL_INFO(dev)->gen < 4) { | |
2676 | if (intel_crtc->pipe == PIPE_B) | |
2677 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2678 | ||
2679 | /* pipesrc and dspsize control the size that is scaled from, | |
2680 | * which should always be the user's requested size. | |
2681 | */ | |
2682 | I915_WRITE(DSPSIZE(plane), | |
6e3c9717 ACO |
2683 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2684 | (intel_crtc->config->pipe_src_w - 1)); | |
f45651ba | 2685 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
2686 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2687 | I915_WRITE(PRIMSIZE(plane), | |
6e3c9717 ACO |
2688 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2689 | (intel_crtc->config->pipe_src_w - 1)); | |
c14b0485 VS |
2690 | I915_WRITE(PRIMPOS(plane), 0); |
2691 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2692 | } |
81255565 | 2693 | |
57779d06 VS |
2694 | switch (fb->pixel_format) { |
2695 | case DRM_FORMAT_C8: | |
81255565 JB |
2696 | dspcntr |= DISPPLANE_8BPP; |
2697 | break; | |
57779d06 | 2698 | case DRM_FORMAT_XRGB1555: |
57779d06 | 2699 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 2700 | break; |
57779d06 VS |
2701 | case DRM_FORMAT_RGB565: |
2702 | dspcntr |= DISPPLANE_BGRX565; | |
2703 | break; | |
2704 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
2705 | dspcntr |= DISPPLANE_BGRX888; |
2706 | break; | |
2707 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2708 | dspcntr |= DISPPLANE_RGBX888; |
2709 | break; | |
2710 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2711 | dspcntr |= DISPPLANE_BGRX101010; |
2712 | break; | |
2713 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2714 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
2715 | break; |
2716 | default: | |
baba133a | 2717 | BUG(); |
81255565 | 2718 | } |
57779d06 | 2719 | |
f45651ba VS |
2720 | if (INTEL_INFO(dev)->gen >= 4 && |
2721 | obj->tiling_mode != I915_TILING_NONE) | |
2722 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2723 | |
de1aa629 VS |
2724 | if (IS_G4X(dev)) |
2725 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2726 | ||
b9897127 | 2727 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
81255565 | 2728 | |
c2c75131 DV |
2729 | if (INTEL_INFO(dev)->gen >= 4) { |
2730 | intel_crtc->dspaddr_offset = | |
bc752862 | 2731 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
b9897127 | 2732 | pixel_size, |
bc752862 | 2733 | fb->pitches[0]); |
c2c75131 DV |
2734 | linear_offset -= intel_crtc->dspaddr_offset; |
2735 | } else { | |
e506a0c6 | 2736 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2737 | } |
e506a0c6 | 2738 | |
8e7d688b | 2739 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2740 | dspcntr |= DISPPLANE_ROTATE_180; |
2741 | ||
6e3c9717 ACO |
2742 | x += (intel_crtc->config->pipe_src_w - 1); |
2743 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2744 | |
2745 | /* Finding the last pixel of the last line of the display | |
2746 | data and adding to linear_offset*/ | |
2747 | linear_offset += | |
6e3c9717 ACO |
2748 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2749 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2750 | } |
2751 | ||
2752 | I915_WRITE(reg, dspcntr); | |
2753 | ||
01f2c773 | 2754 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2755 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2756 | I915_WRITE(DSPSURF(plane), |
2757 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2758 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2759 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2760 | } else |
f343c5f6 | 2761 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2762 | POSTING_READ(reg); |
17638cd6 JB |
2763 | } |
2764 | ||
29b9bde6 DV |
2765 | static void ironlake_update_primary_plane(struct drm_crtc *crtc, |
2766 | struct drm_framebuffer *fb, | |
2767 | int x, int y) | |
17638cd6 JB |
2768 | { |
2769 | struct drm_device *dev = crtc->dev; | |
2770 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2771 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
2772 | struct drm_plane *primary = crtc->primary; |
2773 | bool visible = to_intel_plane_state(primary->state)->visible; | |
c9ba6fad | 2774 | struct drm_i915_gem_object *obj; |
17638cd6 | 2775 | int plane = intel_crtc->plane; |
e506a0c6 | 2776 | unsigned long linear_offset; |
17638cd6 | 2777 | u32 dspcntr; |
f45651ba | 2778 | u32 reg = DSPCNTR(plane); |
48404c1e | 2779 | int pixel_size; |
f45651ba | 2780 | |
b70709a6 | 2781 | if (!visible || !fb) { |
fdd508a6 VS |
2782 | I915_WRITE(reg, 0); |
2783 | I915_WRITE(DSPSURF(plane), 0); | |
2784 | POSTING_READ(reg); | |
2785 | return; | |
2786 | } | |
2787 | ||
c9ba6fad VS |
2788 | obj = intel_fb_obj(fb); |
2789 | if (WARN_ON(obj == NULL)) | |
2790 | return; | |
2791 | ||
2792 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2793 | ||
f45651ba VS |
2794 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2795 | ||
fdd508a6 | 2796 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2797 | |
2798 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2799 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2800 | |
57779d06 VS |
2801 | switch (fb->pixel_format) { |
2802 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2803 | dspcntr |= DISPPLANE_8BPP; |
2804 | break; | |
57779d06 VS |
2805 | case DRM_FORMAT_RGB565: |
2806 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2807 | break; |
57779d06 | 2808 | case DRM_FORMAT_XRGB8888: |
57779d06 VS |
2809 | dspcntr |= DISPPLANE_BGRX888; |
2810 | break; | |
2811 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2812 | dspcntr |= DISPPLANE_RGBX888; |
2813 | break; | |
2814 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2815 | dspcntr |= DISPPLANE_BGRX101010; |
2816 | break; | |
2817 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2818 | dspcntr |= DISPPLANE_RGBX101010; |
17638cd6 JB |
2819 | break; |
2820 | default: | |
baba133a | 2821 | BUG(); |
17638cd6 JB |
2822 | } |
2823 | ||
2824 | if (obj->tiling_mode != I915_TILING_NONE) | |
2825 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2826 | |
f45651ba | 2827 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2828 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2829 | |
b9897127 | 2830 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
c2c75131 | 2831 | intel_crtc->dspaddr_offset = |
bc752862 | 2832 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
b9897127 | 2833 | pixel_size, |
bc752862 | 2834 | fb->pitches[0]); |
c2c75131 | 2835 | linear_offset -= intel_crtc->dspaddr_offset; |
8e7d688b | 2836 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2837 | dspcntr |= DISPPLANE_ROTATE_180; |
2838 | ||
2839 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
6e3c9717 ACO |
2840 | x += (intel_crtc->config->pipe_src_w - 1); |
2841 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2842 | |
2843 | /* Finding the last pixel of the last line of the display | |
2844 | data and adding to linear_offset*/ | |
2845 | linear_offset += | |
6e3c9717 ACO |
2846 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2847 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2848 | } |
2849 | } | |
2850 | ||
2851 | I915_WRITE(reg, dspcntr); | |
17638cd6 | 2852 | |
01f2c773 | 2853 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2854 | I915_WRITE(DSPSURF(plane), |
2855 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2856 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2857 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2858 | } else { | |
2859 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2860 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2861 | } | |
17638cd6 | 2862 | POSTING_READ(reg); |
17638cd6 JB |
2863 | } |
2864 | ||
b321803d DL |
2865 | u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier, |
2866 | uint32_t pixel_format) | |
2867 | { | |
2868 | u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8; | |
2869 | ||
2870 | /* | |
2871 | * The stride is either expressed as a multiple of 64 bytes | |
2872 | * chunks for linear buffers or in number of tiles for tiled | |
2873 | * buffers. | |
2874 | */ | |
2875 | switch (fb_modifier) { | |
2876 | case DRM_FORMAT_MOD_NONE: | |
2877 | return 64; | |
2878 | case I915_FORMAT_MOD_X_TILED: | |
2879 | if (INTEL_INFO(dev)->gen == 2) | |
2880 | return 128; | |
2881 | return 512; | |
2882 | case I915_FORMAT_MOD_Y_TILED: | |
2883 | /* No need to check for old gens and Y tiling since this is | |
2884 | * about the display engine and those will be blocked before | |
2885 | * we get here. | |
2886 | */ | |
2887 | return 128; | |
2888 | case I915_FORMAT_MOD_Yf_TILED: | |
2889 | if (bits_per_pixel == 8) | |
2890 | return 64; | |
2891 | else | |
2892 | return 128; | |
2893 | default: | |
2894 | MISSING_CASE(fb_modifier); | |
2895 | return 64; | |
2896 | } | |
2897 | } | |
2898 | ||
121920fa TU |
2899 | unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane, |
2900 | struct drm_i915_gem_object *obj) | |
2901 | { | |
9abc4648 | 2902 | const struct i915_ggtt_view *view = &i915_ggtt_view_normal; |
121920fa TU |
2903 | |
2904 | if (intel_rotation_90_or_270(intel_plane->base.state->rotation)) | |
9abc4648 | 2905 | view = &i915_ggtt_view_rotated; |
121920fa TU |
2906 | |
2907 | return i915_gem_obj_ggtt_offset_view(obj, view); | |
2908 | } | |
2909 | ||
a1b2278e CK |
2910 | /* |
2911 | * This function detaches (aka. unbinds) unused scalers in hardware | |
2912 | */ | |
2913 | void skl_detach_scalers(struct intel_crtc *intel_crtc) | |
2914 | { | |
2915 | struct drm_device *dev; | |
2916 | struct drm_i915_private *dev_priv; | |
2917 | struct intel_crtc_scaler_state *scaler_state; | |
2918 | int i; | |
2919 | ||
2920 | if (!intel_crtc || !intel_crtc->config) | |
2921 | return; | |
2922 | ||
2923 | dev = intel_crtc->base.dev; | |
2924 | dev_priv = dev->dev_private; | |
2925 | scaler_state = &intel_crtc->config->scaler_state; | |
2926 | ||
2927 | /* loop through and disable scalers that aren't in use */ | |
2928 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
2929 | if (!scaler_state->scalers[i].in_use) { | |
2930 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0); | |
2931 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0); | |
2932 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0); | |
2933 | DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n", | |
2934 | intel_crtc->base.base.id, intel_crtc->pipe, i); | |
2935 | } | |
2936 | } | |
2937 | } | |
2938 | ||
6156a456 | 2939 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 2940 | { |
6156a456 | 2941 | switch (pixel_format) { |
d161cf7a | 2942 | case DRM_FORMAT_C8: |
c34ce3d1 | 2943 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 2944 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 2945 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 2946 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 2947 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 2948 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 2949 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
2950 | /* |
2951 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
2952 | * to be already pre-multiplied. We need to add a knob (or a different | |
2953 | * DRM_FORMAT) for user-space to configure that. | |
2954 | */ | |
f75fb42a | 2955 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 2956 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 2957 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 2958 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 2959 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 2960 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 2961 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 2962 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 2963 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 2964 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 2965 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 2966 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 2967 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 2968 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 2969 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 2970 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 2971 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 2972 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 2973 | default: |
4249eeef | 2974 | MISSING_CASE(pixel_format); |
70d21f0e | 2975 | } |
8cfcba41 | 2976 | |
c34ce3d1 | 2977 | return 0; |
6156a456 | 2978 | } |
70d21f0e | 2979 | |
6156a456 CK |
2980 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
2981 | { | |
6156a456 | 2982 | switch (fb_modifier) { |
30af77c4 | 2983 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 2984 | break; |
30af77c4 | 2985 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 2986 | return PLANE_CTL_TILED_X; |
b321803d | 2987 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 2988 | return PLANE_CTL_TILED_Y; |
b321803d | 2989 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 2990 | return PLANE_CTL_TILED_YF; |
70d21f0e | 2991 | default: |
6156a456 | 2992 | MISSING_CASE(fb_modifier); |
70d21f0e | 2993 | } |
8cfcba41 | 2994 | |
c34ce3d1 | 2995 | return 0; |
6156a456 | 2996 | } |
70d21f0e | 2997 | |
6156a456 CK |
2998 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
2999 | { | |
3b7a5119 | 3000 | switch (rotation) { |
6156a456 CK |
3001 | case BIT(DRM_ROTATE_0): |
3002 | break; | |
1e8df167 SJ |
3003 | /* |
3004 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
3005 | * while i915 HW rotation is clockwise, thats why this swapping. | |
3006 | */ | |
3b7a5119 | 3007 | case BIT(DRM_ROTATE_90): |
1e8df167 | 3008 | return PLANE_CTL_ROTATE_270; |
3b7a5119 | 3009 | case BIT(DRM_ROTATE_180): |
c34ce3d1 | 3010 | return PLANE_CTL_ROTATE_180; |
3b7a5119 | 3011 | case BIT(DRM_ROTATE_270): |
1e8df167 | 3012 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
3013 | default: |
3014 | MISSING_CASE(rotation); | |
3015 | } | |
3016 | ||
c34ce3d1 | 3017 | return 0; |
6156a456 CK |
3018 | } |
3019 | ||
3020 | static void skylake_update_primary_plane(struct drm_crtc *crtc, | |
3021 | struct drm_framebuffer *fb, | |
3022 | int x, int y) | |
3023 | { | |
3024 | struct drm_device *dev = crtc->dev; | |
3025 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3026 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
3027 | struct drm_plane *plane = crtc->primary; |
3028 | bool visible = to_intel_plane_state(plane->state)->visible; | |
6156a456 CK |
3029 | struct drm_i915_gem_object *obj; |
3030 | int pipe = intel_crtc->pipe; | |
3031 | u32 plane_ctl, stride_div, stride; | |
3032 | u32 tile_height, plane_offset, plane_size; | |
3033 | unsigned int rotation; | |
3034 | int x_offset, y_offset; | |
3035 | unsigned long surf_addr; | |
6156a456 CK |
3036 | struct intel_crtc_state *crtc_state = intel_crtc->config; |
3037 | struct intel_plane_state *plane_state; | |
3038 | int src_x = 0, src_y = 0, src_w = 0, src_h = 0; | |
3039 | int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0; | |
3040 | int scaler_id = -1; | |
3041 | ||
6156a456 CK |
3042 | plane_state = to_intel_plane_state(plane->state); |
3043 | ||
b70709a6 | 3044 | if (!visible || !fb) { |
6156a456 CK |
3045 | I915_WRITE(PLANE_CTL(pipe, 0), 0); |
3046 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
3047 | POSTING_READ(PLANE_CTL(pipe, 0)); | |
3048 | return; | |
3b7a5119 | 3049 | } |
70d21f0e | 3050 | |
6156a456 CK |
3051 | plane_ctl = PLANE_CTL_ENABLE | |
3052 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3053 | PLANE_CTL_PIPE_CSC_ENABLE; | |
3054 | ||
3055 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); | |
3056 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
3057 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
3058 | ||
3059 | rotation = plane->state->rotation; | |
3060 | plane_ctl |= skl_plane_ctl_rotation(rotation); | |
3061 | ||
b321803d DL |
3062 | obj = intel_fb_obj(fb); |
3063 | stride_div = intel_fb_stride_alignment(dev, fb->modifier[0], | |
3064 | fb->pixel_format); | |
3b7a5119 SJ |
3065 | surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj); |
3066 | ||
6156a456 CK |
3067 | /* |
3068 | * FIXME: intel_plane_state->src, dst aren't set when transitional | |
3069 | * update_plane helpers are called from legacy paths. | |
3070 | * Once full atomic crtc is available, below check can be avoided. | |
3071 | */ | |
3072 | if (drm_rect_width(&plane_state->src)) { | |
3073 | scaler_id = plane_state->scaler_id; | |
3074 | src_x = plane_state->src.x1 >> 16; | |
3075 | src_y = plane_state->src.y1 >> 16; | |
3076 | src_w = drm_rect_width(&plane_state->src) >> 16; | |
3077 | src_h = drm_rect_height(&plane_state->src) >> 16; | |
3078 | dst_x = plane_state->dst.x1; | |
3079 | dst_y = plane_state->dst.y1; | |
3080 | dst_w = drm_rect_width(&plane_state->dst); | |
3081 | dst_h = drm_rect_height(&plane_state->dst); | |
3082 | ||
3083 | WARN_ON(x != src_x || y != src_y); | |
3084 | } else { | |
3085 | src_w = intel_crtc->config->pipe_src_w; | |
3086 | src_h = intel_crtc->config->pipe_src_h; | |
3087 | } | |
3088 | ||
3b7a5119 SJ |
3089 | if (intel_rotation_90_or_270(rotation)) { |
3090 | /* stride = Surface height in tiles */ | |
2614f17d | 3091 | tile_height = intel_tile_height(dev, fb->pixel_format, |
3b7a5119 SJ |
3092 | fb->modifier[0]); |
3093 | stride = DIV_ROUND_UP(fb->height, tile_height); | |
6156a456 | 3094 | x_offset = stride * tile_height - y - src_h; |
3b7a5119 | 3095 | y_offset = x; |
6156a456 | 3096 | plane_size = (src_w - 1) << 16 | (src_h - 1); |
3b7a5119 SJ |
3097 | } else { |
3098 | stride = fb->pitches[0] / stride_div; | |
3099 | x_offset = x; | |
3100 | y_offset = y; | |
6156a456 | 3101 | plane_size = (src_h - 1) << 16 | (src_w - 1); |
3b7a5119 SJ |
3102 | } |
3103 | plane_offset = y_offset << 16 | x_offset; | |
b321803d | 3104 | |
70d21f0e | 3105 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
3b7a5119 SJ |
3106 | I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); |
3107 | I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); | |
3108 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
6156a456 CK |
3109 | |
3110 | if (scaler_id >= 0) { | |
3111 | uint32_t ps_ctrl = 0; | |
3112 | ||
3113 | WARN_ON(!dst_w || !dst_h); | |
3114 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | | |
3115 | crtc_state->scaler_state.scalers[scaler_id].mode; | |
3116 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3117 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3118 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3119 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3120 | I915_WRITE(PLANE_POS(pipe, 0), 0); | |
3121 | } else { | |
3122 | I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); | |
3123 | } | |
3124 | ||
121920fa | 3125 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
70d21f0e DL |
3126 | |
3127 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3128 | } | |
3129 | ||
17638cd6 JB |
3130 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3131 | static int | |
3132 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3133 | int x, int y, enum mode_set_atomic state) | |
3134 | { | |
3135 | struct drm_device *dev = crtc->dev; | |
3136 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 3137 | |
6b8e6ed0 CW |
3138 | if (dev_priv->display.disable_fbc) |
3139 | dev_priv->display.disable_fbc(dev); | |
81255565 | 3140 | |
29b9bde6 DV |
3141 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
3142 | ||
3143 | return 0; | |
81255565 JB |
3144 | } |
3145 | ||
7514747d | 3146 | static void intel_complete_page_flips(struct drm_device *dev) |
96a02917 | 3147 | { |
96a02917 VS |
3148 | struct drm_crtc *crtc; |
3149 | ||
70e1e0ec | 3150 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3151 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3152 | enum plane plane = intel_crtc->plane; | |
3153 | ||
3154 | intel_prepare_page_flip(dev, plane); | |
3155 | intel_finish_page_flip_plane(dev, plane); | |
3156 | } | |
7514747d VS |
3157 | } |
3158 | ||
3159 | static void intel_update_primary_planes(struct drm_device *dev) | |
3160 | { | |
3161 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3162 | struct drm_crtc *crtc; | |
96a02917 | 3163 | |
70e1e0ec | 3164 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3165 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3166 | ||
51fd371b | 3167 | drm_modeset_lock(&crtc->mutex, NULL); |
947fdaad CW |
3168 | /* |
3169 | * FIXME: Once we have proper support for primary planes (and | |
3170 | * disabling them without disabling the entire crtc) allow again | |
66e514c1 | 3171 | * a NULL crtc->primary->fb. |
947fdaad | 3172 | */ |
f4510a27 | 3173 | if (intel_crtc->active && crtc->primary->fb) |
262ca2b0 | 3174 | dev_priv->display.update_primary_plane(crtc, |
66e514c1 | 3175 | crtc->primary->fb, |
262ca2b0 MR |
3176 | crtc->x, |
3177 | crtc->y); | |
51fd371b | 3178 | drm_modeset_unlock(&crtc->mutex); |
96a02917 VS |
3179 | } |
3180 | } | |
3181 | ||
ce22dba9 ML |
3182 | void intel_crtc_reset(struct intel_crtc *crtc) |
3183 | { | |
3184 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
3185 | ||
3186 | if (!crtc->active) | |
3187 | return; | |
3188 | ||
3189 | intel_crtc_disable_planes(&crtc->base); | |
3190 | dev_priv->display.crtc_disable(&crtc->base); | |
3191 | dev_priv->display.crtc_enable(&crtc->base); | |
3192 | intel_crtc_enable_planes(&crtc->base); | |
3193 | } | |
3194 | ||
7514747d VS |
3195 | void intel_prepare_reset(struct drm_device *dev) |
3196 | { | |
f98ce92f VS |
3197 | struct drm_i915_private *dev_priv = to_i915(dev); |
3198 | struct intel_crtc *crtc; | |
3199 | ||
7514747d VS |
3200 | /* no reset support for gen2 */ |
3201 | if (IS_GEN2(dev)) | |
3202 | return; | |
3203 | ||
3204 | /* reset doesn't touch the display */ | |
3205 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
3206 | return; | |
3207 | ||
3208 | drm_modeset_lock_all(dev); | |
f98ce92f VS |
3209 | |
3210 | /* | |
3211 | * Disabling the crtcs gracefully seems nicer. Also the | |
3212 | * g33 docs say we should at least disable all the planes. | |
3213 | */ | |
3214 | for_each_intel_crtc(dev, crtc) { | |
ce22dba9 ML |
3215 | if (!crtc->active) |
3216 | continue; | |
3217 | ||
3218 | intel_crtc_disable_planes(&crtc->base); | |
3219 | dev_priv->display.crtc_disable(&crtc->base); | |
f98ce92f | 3220 | } |
7514747d VS |
3221 | } |
3222 | ||
3223 | void intel_finish_reset(struct drm_device *dev) | |
3224 | { | |
3225 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3226 | ||
3227 | /* | |
3228 | * Flips in the rings will be nuked by the reset, | |
3229 | * so complete all pending flips so that user space | |
3230 | * will get its events and not get stuck. | |
3231 | */ | |
3232 | intel_complete_page_flips(dev); | |
3233 | ||
3234 | /* no reset support for gen2 */ | |
3235 | if (IS_GEN2(dev)) | |
3236 | return; | |
3237 | ||
3238 | /* reset doesn't touch the display */ | |
3239 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { | |
3240 | /* | |
3241 | * Flips in the rings have been nuked by the reset, | |
3242 | * so update the base address of all primary | |
3243 | * planes to the the last fb to make sure we're | |
3244 | * showing the correct fb after a reset. | |
3245 | */ | |
3246 | intel_update_primary_planes(dev); | |
3247 | return; | |
3248 | } | |
3249 | ||
3250 | /* | |
3251 | * The display has been reset as well, | |
3252 | * so need a full re-initialization. | |
3253 | */ | |
3254 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3255 | intel_runtime_pm_enable_interrupts(dev_priv); | |
3256 | ||
3257 | intel_modeset_init_hw(dev); | |
3258 | ||
3259 | spin_lock_irq(&dev_priv->irq_lock); | |
3260 | if (dev_priv->display.hpd_irq_setup) | |
3261 | dev_priv->display.hpd_irq_setup(dev); | |
3262 | spin_unlock_irq(&dev_priv->irq_lock); | |
3263 | ||
3264 | intel_modeset_setup_hw_state(dev, true); | |
3265 | ||
3266 | intel_hpd_init(dev_priv); | |
3267 | ||
3268 | drm_modeset_unlock_all(dev); | |
3269 | } | |
3270 | ||
2e2f351d | 3271 | static void |
14667a4b CW |
3272 | intel_finish_fb(struct drm_framebuffer *old_fb) |
3273 | { | |
2ff8fde1 | 3274 | struct drm_i915_gem_object *obj = intel_fb_obj(old_fb); |
2e2f351d | 3275 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
14667a4b CW |
3276 | bool was_interruptible = dev_priv->mm.interruptible; |
3277 | int ret; | |
3278 | ||
14667a4b CW |
3279 | /* Big Hammer, we also need to ensure that any pending |
3280 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
3281 | * current scanout is retired before unpinning the old | |
2e2f351d CW |
3282 | * framebuffer. Note that we rely on userspace rendering |
3283 | * into the buffer attached to the pipe they are waiting | |
3284 | * on. If not, userspace generates a GPU hang with IPEHR | |
3285 | * point to the MI_WAIT_FOR_EVENT. | |
14667a4b CW |
3286 | * |
3287 | * This should only fail upon a hung GPU, in which case we | |
3288 | * can safely continue. | |
3289 | */ | |
3290 | dev_priv->mm.interruptible = false; | |
2e2f351d | 3291 | ret = i915_gem_object_wait_rendering(obj, true); |
14667a4b CW |
3292 | dev_priv->mm.interruptible = was_interruptible; |
3293 | ||
2e2f351d | 3294 | WARN_ON(ret); |
14667a4b CW |
3295 | } |
3296 | ||
7d5e3799 CW |
3297 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3298 | { | |
3299 | struct drm_device *dev = crtc->dev; | |
3300 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3301 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7d5e3799 CW |
3302 | bool pending; |
3303 | ||
3304 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
3305 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
3306 | return false; | |
3307 | ||
5e2d7afc | 3308 | spin_lock_irq(&dev->event_lock); |
7d5e3799 | 3309 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
5e2d7afc | 3310 | spin_unlock_irq(&dev->event_lock); |
7d5e3799 CW |
3311 | |
3312 | return pending; | |
3313 | } | |
3314 | ||
e30e8f75 GP |
3315 | static void intel_update_pipe_size(struct intel_crtc *crtc) |
3316 | { | |
3317 | struct drm_device *dev = crtc->base.dev; | |
3318 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3319 | const struct drm_display_mode *adjusted_mode; | |
3320 | ||
3321 | if (!i915.fastboot) | |
3322 | return; | |
3323 | ||
3324 | /* | |
3325 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3326 | * that in compute_mode_changes we check the native mode (not the pfit | |
3327 | * mode) to see if we can flip rather than do a full mode set. In the | |
3328 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3329 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3330 | * sized surface. | |
3331 | * | |
3332 | * To fix this properly, we need to hoist the checks up into | |
3333 | * compute_mode_changes (or above), check the actual pfit state and | |
3334 | * whether the platform allows pfit disable with pipe active, and only | |
3335 | * then update the pipesrc and pfit state, even on the flip path. | |
3336 | */ | |
3337 | ||
6e3c9717 | 3338 | adjusted_mode = &crtc->config->base.adjusted_mode; |
e30e8f75 GP |
3339 | |
3340 | I915_WRITE(PIPESRC(crtc->pipe), | |
3341 | ((adjusted_mode->crtc_hdisplay - 1) << 16) | | |
3342 | (adjusted_mode->crtc_vdisplay - 1)); | |
6e3c9717 | 3343 | if (!crtc->config->pch_pfit.enabled && |
409ee761 ACO |
3344 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
3345 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
e30e8f75 GP |
3346 | I915_WRITE(PF_CTL(crtc->pipe), 0); |
3347 | I915_WRITE(PF_WIN_POS(crtc->pipe), 0); | |
3348 | I915_WRITE(PF_WIN_SZ(crtc->pipe), 0); | |
3349 | } | |
6e3c9717 ACO |
3350 | crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay; |
3351 | crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay; | |
e30e8f75 GP |
3352 | } |
3353 | ||
5e84e1a4 ZW |
3354 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3355 | { | |
3356 | struct drm_device *dev = crtc->dev; | |
3357 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3358 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3359 | int pipe = intel_crtc->pipe; | |
3360 | u32 reg, temp; | |
3361 | ||
3362 | /* enable normal train */ | |
3363 | reg = FDI_TX_CTL(pipe); | |
3364 | temp = I915_READ(reg); | |
61e499bf | 3365 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3366 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3367 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3368 | } else { |
3369 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3370 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3371 | } |
5e84e1a4 ZW |
3372 | I915_WRITE(reg, temp); |
3373 | ||
3374 | reg = FDI_RX_CTL(pipe); | |
3375 | temp = I915_READ(reg); | |
3376 | if (HAS_PCH_CPT(dev)) { | |
3377 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3378 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3379 | } else { | |
3380 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3381 | temp |= FDI_LINK_TRAIN_NONE; | |
3382 | } | |
3383 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3384 | ||
3385 | /* wait one idle pattern time */ | |
3386 | POSTING_READ(reg); | |
3387 | udelay(1000); | |
357555c0 JB |
3388 | |
3389 | /* IVB wants error correction enabled */ | |
3390 | if (IS_IVYBRIDGE(dev)) | |
3391 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3392 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3393 | } |
3394 | ||
8db9d77b ZW |
3395 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3396 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3397 | { | |
3398 | struct drm_device *dev = crtc->dev; | |
3399 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3400 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3401 | int pipe = intel_crtc->pipe; | |
5eddb70b | 3402 | u32 reg, temp, tries; |
8db9d77b | 3403 | |
1c8562f6 | 3404 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3405 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3406 | |
e1a44743 AJ |
3407 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3408 | for train result */ | |
5eddb70b CW |
3409 | reg = FDI_RX_IMR(pipe); |
3410 | temp = I915_READ(reg); | |
e1a44743 AJ |
3411 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3412 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3413 | I915_WRITE(reg, temp); |
3414 | I915_READ(reg); | |
e1a44743 AJ |
3415 | udelay(150); |
3416 | ||
8db9d77b | 3417 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3418 | reg = FDI_TX_CTL(pipe); |
3419 | temp = I915_READ(reg); | |
627eb5a3 | 3420 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3421 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3422 | temp &= ~FDI_LINK_TRAIN_NONE; |
3423 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3424 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3425 | |
5eddb70b CW |
3426 | reg = FDI_RX_CTL(pipe); |
3427 | temp = I915_READ(reg); | |
8db9d77b ZW |
3428 | temp &= ~FDI_LINK_TRAIN_NONE; |
3429 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3430 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3431 | ||
3432 | POSTING_READ(reg); | |
8db9d77b ZW |
3433 | udelay(150); |
3434 | ||
5b2adf89 | 3435 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3436 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3437 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3438 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3439 | |
5eddb70b | 3440 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3441 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3442 | temp = I915_READ(reg); |
8db9d77b ZW |
3443 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3444 | ||
3445 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3446 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3447 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3448 | break; |
3449 | } | |
8db9d77b | 3450 | } |
e1a44743 | 3451 | if (tries == 5) |
5eddb70b | 3452 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3453 | |
3454 | /* Train 2 */ | |
5eddb70b CW |
3455 | reg = FDI_TX_CTL(pipe); |
3456 | temp = I915_READ(reg); | |
8db9d77b ZW |
3457 | temp &= ~FDI_LINK_TRAIN_NONE; |
3458 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3459 | I915_WRITE(reg, temp); |
8db9d77b | 3460 | |
5eddb70b CW |
3461 | reg = FDI_RX_CTL(pipe); |
3462 | temp = I915_READ(reg); | |
8db9d77b ZW |
3463 | temp &= ~FDI_LINK_TRAIN_NONE; |
3464 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3465 | I915_WRITE(reg, temp); |
8db9d77b | 3466 | |
5eddb70b CW |
3467 | POSTING_READ(reg); |
3468 | udelay(150); | |
8db9d77b | 3469 | |
5eddb70b | 3470 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3471 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3472 | temp = I915_READ(reg); |
8db9d77b ZW |
3473 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3474 | ||
3475 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3476 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3477 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3478 | break; | |
3479 | } | |
8db9d77b | 3480 | } |
e1a44743 | 3481 | if (tries == 5) |
5eddb70b | 3482 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3483 | |
3484 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3485 | |
8db9d77b ZW |
3486 | } |
3487 | ||
0206e353 | 3488 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3489 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3490 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3491 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3492 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3493 | }; | |
3494 | ||
3495 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3496 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3497 | { | |
3498 | struct drm_device *dev = crtc->dev; | |
3499 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3500 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3501 | int pipe = intel_crtc->pipe; | |
fa37d39e | 3502 | u32 reg, temp, i, retry; |
8db9d77b | 3503 | |
e1a44743 AJ |
3504 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3505 | for train result */ | |
5eddb70b CW |
3506 | reg = FDI_RX_IMR(pipe); |
3507 | temp = I915_READ(reg); | |
e1a44743 AJ |
3508 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3509 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3510 | I915_WRITE(reg, temp); |
3511 | ||
3512 | POSTING_READ(reg); | |
e1a44743 AJ |
3513 | udelay(150); |
3514 | ||
8db9d77b | 3515 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3516 | reg = FDI_TX_CTL(pipe); |
3517 | temp = I915_READ(reg); | |
627eb5a3 | 3518 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3519 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3520 | temp &= ~FDI_LINK_TRAIN_NONE; |
3521 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3522 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3523 | /* SNB-B */ | |
3524 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3525 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3526 | |
d74cf324 DV |
3527 | I915_WRITE(FDI_RX_MISC(pipe), |
3528 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3529 | ||
5eddb70b CW |
3530 | reg = FDI_RX_CTL(pipe); |
3531 | temp = I915_READ(reg); | |
8db9d77b ZW |
3532 | if (HAS_PCH_CPT(dev)) { |
3533 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3534 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3535 | } else { | |
3536 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3537 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3538 | } | |
5eddb70b CW |
3539 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3540 | ||
3541 | POSTING_READ(reg); | |
8db9d77b ZW |
3542 | udelay(150); |
3543 | ||
0206e353 | 3544 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3545 | reg = FDI_TX_CTL(pipe); |
3546 | temp = I915_READ(reg); | |
8db9d77b ZW |
3547 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3548 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3549 | I915_WRITE(reg, temp); |
3550 | ||
3551 | POSTING_READ(reg); | |
8db9d77b ZW |
3552 | udelay(500); |
3553 | ||
fa37d39e SP |
3554 | for (retry = 0; retry < 5; retry++) { |
3555 | reg = FDI_RX_IIR(pipe); | |
3556 | temp = I915_READ(reg); | |
3557 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3558 | if (temp & FDI_RX_BIT_LOCK) { | |
3559 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3560 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3561 | break; | |
3562 | } | |
3563 | udelay(50); | |
8db9d77b | 3564 | } |
fa37d39e SP |
3565 | if (retry < 5) |
3566 | break; | |
8db9d77b ZW |
3567 | } |
3568 | if (i == 4) | |
5eddb70b | 3569 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3570 | |
3571 | /* Train 2 */ | |
5eddb70b CW |
3572 | reg = FDI_TX_CTL(pipe); |
3573 | temp = I915_READ(reg); | |
8db9d77b ZW |
3574 | temp &= ~FDI_LINK_TRAIN_NONE; |
3575 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3576 | if (IS_GEN6(dev)) { | |
3577 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3578 | /* SNB-B */ | |
3579 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3580 | } | |
5eddb70b | 3581 | I915_WRITE(reg, temp); |
8db9d77b | 3582 | |
5eddb70b CW |
3583 | reg = FDI_RX_CTL(pipe); |
3584 | temp = I915_READ(reg); | |
8db9d77b ZW |
3585 | if (HAS_PCH_CPT(dev)) { |
3586 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3587 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3588 | } else { | |
3589 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3590 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3591 | } | |
5eddb70b CW |
3592 | I915_WRITE(reg, temp); |
3593 | ||
3594 | POSTING_READ(reg); | |
8db9d77b ZW |
3595 | udelay(150); |
3596 | ||
0206e353 | 3597 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3598 | reg = FDI_TX_CTL(pipe); |
3599 | temp = I915_READ(reg); | |
8db9d77b ZW |
3600 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3601 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3602 | I915_WRITE(reg, temp); |
3603 | ||
3604 | POSTING_READ(reg); | |
8db9d77b ZW |
3605 | udelay(500); |
3606 | ||
fa37d39e SP |
3607 | for (retry = 0; retry < 5; retry++) { |
3608 | reg = FDI_RX_IIR(pipe); | |
3609 | temp = I915_READ(reg); | |
3610 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3611 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3612 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3613 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3614 | break; | |
3615 | } | |
3616 | udelay(50); | |
8db9d77b | 3617 | } |
fa37d39e SP |
3618 | if (retry < 5) |
3619 | break; | |
8db9d77b ZW |
3620 | } |
3621 | if (i == 4) | |
5eddb70b | 3622 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3623 | |
3624 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3625 | } | |
3626 | ||
357555c0 JB |
3627 | /* Manual link training for Ivy Bridge A0 parts */ |
3628 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3629 | { | |
3630 | struct drm_device *dev = crtc->dev; | |
3631 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3632 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3633 | int pipe = intel_crtc->pipe; | |
139ccd3f | 3634 | u32 reg, temp, i, j; |
357555c0 JB |
3635 | |
3636 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3637 | for train result */ | |
3638 | reg = FDI_RX_IMR(pipe); | |
3639 | temp = I915_READ(reg); | |
3640 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3641 | temp &= ~FDI_RX_BIT_LOCK; | |
3642 | I915_WRITE(reg, temp); | |
3643 | ||
3644 | POSTING_READ(reg); | |
3645 | udelay(150); | |
3646 | ||
01a415fd DV |
3647 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3648 | I915_READ(FDI_RX_IIR(pipe))); | |
3649 | ||
139ccd3f JB |
3650 | /* Try each vswing and preemphasis setting twice before moving on */ |
3651 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3652 | /* disable first in case we need to retry */ | |
3653 | reg = FDI_TX_CTL(pipe); | |
3654 | temp = I915_READ(reg); | |
3655 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3656 | temp &= ~FDI_TX_ENABLE; | |
3657 | I915_WRITE(reg, temp); | |
357555c0 | 3658 | |
139ccd3f JB |
3659 | reg = FDI_RX_CTL(pipe); |
3660 | temp = I915_READ(reg); | |
3661 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3662 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3663 | temp &= ~FDI_RX_ENABLE; | |
3664 | I915_WRITE(reg, temp); | |
357555c0 | 3665 | |
139ccd3f | 3666 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3667 | reg = FDI_TX_CTL(pipe); |
3668 | temp = I915_READ(reg); | |
139ccd3f | 3669 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3670 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 3671 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3672 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3673 | temp |= snb_b_fdi_train_param[j/2]; |
3674 | temp |= FDI_COMPOSITE_SYNC; | |
3675 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3676 | |
139ccd3f JB |
3677 | I915_WRITE(FDI_RX_MISC(pipe), |
3678 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3679 | |
139ccd3f | 3680 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3681 | temp = I915_READ(reg); |
139ccd3f JB |
3682 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3683 | temp |= FDI_COMPOSITE_SYNC; | |
3684 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3685 | |
139ccd3f JB |
3686 | POSTING_READ(reg); |
3687 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3688 | |
139ccd3f JB |
3689 | for (i = 0; i < 4; i++) { |
3690 | reg = FDI_RX_IIR(pipe); | |
3691 | temp = I915_READ(reg); | |
3692 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3693 | |
139ccd3f JB |
3694 | if (temp & FDI_RX_BIT_LOCK || |
3695 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3696 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3697 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3698 | i); | |
3699 | break; | |
3700 | } | |
3701 | udelay(1); /* should be 0.5us */ | |
3702 | } | |
3703 | if (i == 4) { | |
3704 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3705 | continue; | |
3706 | } | |
357555c0 | 3707 | |
139ccd3f | 3708 | /* Train 2 */ |
357555c0 JB |
3709 | reg = FDI_TX_CTL(pipe); |
3710 | temp = I915_READ(reg); | |
139ccd3f JB |
3711 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3712 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3713 | I915_WRITE(reg, temp); | |
3714 | ||
3715 | reg = FDI_RX_CTL(pipe); | |
3716 | temp = I915_READ(reg); | |
3717 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3718 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3719 | I915_WRITE(reg, temp); |
3720 | ||
3721 | POSTING_READ(reg); | |
139ccd3f | 3722 | udelay(2); /* should be 1.5us */ |
357555c0 | 3723 | |
139ccd3f JB |
3724 | for (i = 0; i < 4; i++) { |
3725 | reg = FDI_RX_IIR(pipe); | |
3726 | temp = I915_READ(reg); | |
3727 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3728 | |
139ccd3f JB |
3729 | if (temp & FDI_RX_SYMBOL_LOCK || |
3730 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3731 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3732 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3733 | i); | |
3734 | goto train_done; | |
3735 | } | |
3736 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3737 | } |
139ccd3f JB |
3738 | if (i == 4) |
3739 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3740 | } |
357555c0 | 3741 | |
139ccd3f | 3742 | train_done: |
357555c0 JB |
3743 | DRM_DEBUG_KMS("FDI train done.\n"); |
3744 | } | |
3745 | ||
88cefb6c | 3746 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3747 | { |
88cefb6c | 3748 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3749 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3750 | int pipe = intel_crtc->pipe; |
5eddb70b | 3751 | u32 reg, temp; |
79e53945 | 3752 | |
c64e311e | 3753 | |
c98e9dcf | 3754 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3755 | reg = FDI_RX_CTL(pipe); |
3756 | temp = I915_READ(reg); | |
627eb5a3 | 3757 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3758 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3759 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3760 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3761 | ||
3762 | POSTING_READ(reg); | |
c98e9dcf JB |
3763 | udelay(200); |
3764 | ||
3765 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3766 | temp = I915_READ(reg); |
3767 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3768 | ||
3769 | POSTING_READ(reg); | |
c98e9dcf JB |
3770 | udelay(200); |
3771 | ||
20749730 PZ |
3772 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3773 | reg = FDI_TX_CTL(pipe); | |
3774 | temp = I915_READ(reg); | |
3775 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3776 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3777 | |
20749730 PZ |
3778 | POSTING_READ(reg); |
3779 | udelay(100); | |
6be4a607 | 3780 | } |
0e23b99d JB |
3781 | } |
3782 | ||
88cefb6c DV |
3783 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3784 | { | |
3785 | struct drm_device *dev = intel_crtc->base.dev; | |
3786 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3787 | int pipe = intel_crtc->pipe; | |
3788 | u32 reg, temp; | |
3789 | ||
3790 | /* Switch from PCDclk to Rawclk */ | |
3791 | reg = FDI_RX_CTL(pipe); | |
3792 | temp = I915_READ(reg); | |
3793 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3794 | ||
3795 | /* Disable CPU FDI TX PLL */ | |
3796 | reg = FDI_TX_CTL(pipe); | |
3797 | temp = I915_READ(reg); | |
3798 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3799 | ||
3800 | POSTING_READ(reg); | |
3801 | udelay(100); | |
3802 | ||
3803 | reg = FDI_RX_CTL(pipe); | |
3804 | temp = I915_READ(reg); | |
3805 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3806 | ||
3807 | /* Wait for the clocks to turn off. */ | |
3808 | POSTING_READ(reg); | |
3809 | udelay(100); | |
3810 | } | |
3811 | ||
0fc932b8 JB |
3812 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3813 | { | |
3814 | struct drm_device *dev = crtc->dev; | |
3815 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3816 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3817 | int pipe = intel_crtc->pipe; | |
3818 | u32 reg, temp; | |
3819 | ||
3820 | /* disable CPU FDI tx and PCH FDI rx */ | |
3821 | reg = FDI_TX_CTL(pipe); | |
3822 | temp = I915_READ(reg); | |
3823 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3824 | POSTING_READ(reg); | |
3825 | ||
3826 | reg = FDI_RX_CTL(pipe); | |
3827 | temp = I915_READ(reg); | |
3828 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3829 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3830 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3831 | ||
3832 | POSTING_READ(reg); | |
3833 | udelay(100); | |
3834 | ||
3835 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3836 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3837 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3838 | |
3839 | /* still set train pattern 1 */ | |
3840 | reg = FDI_TX_CTL(pipe); | |
3841 | temp = I915_READ(reg); | |
3842 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3843 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3844 | I915_WRITE(reg, temp); | |
3845 | ||
3846 | reg = FDI_RX_CTL(pipe); | |
3847 | temp = I915_READ(reg); | |
3848 | if (HAS_PCH_CPT(dev)) { | |
3849 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3850 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3851 | } else { | |
3852 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3853 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3854 | } | |
3855 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3856 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3857 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3858 | I915_WRITE(reg, temp); |
3859 | ||
3860 | POSTING_READ(reg); | |
3861 | udelay(100); | |
3862 | } | |
3863 | ||
5dce5b93 CW |
3864 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3865 | { | |
3866 | struct intel_crtc *crtc; | |
3867 | ||
3868 | /* Note that we don't need to be called with mode_config.lock here | |
3869 | * as our list of CRTC objects is static for the lifetime of the | |
3870 | * device and so cannot disappear as we iterate. Similarly, we can | |
3871 | * happily treat the predicates as racy, atomic checks as userspace | |
3872 | * cannot claim and pin a new fb without at least acquring the | |
3873 | * struct_mutex and so serialising with us. | |
3874 | */ | |
d3fcc808 | 3875 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3876 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3877 | continue; | |
3878 | ||
3879 | if (crtc->unpin_work) | |
3880 | intel_wait_for_vblank(dev, crtc->pipe); | |
3881 | ||
3882 | return true; | |
3883 | } | |
3884 | ||
3885 | return false; | |
3886 | } | |
3887 | ||
d6bbafa1 CW |
3888 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
3889 | { | |
3890 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
3891 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
3892 | ||
3893 | /* ensure that the unpin work is consistent wrt ->pending. */ | |
3894 | smp_rmb(); | |
3895 | intel_crtc->unpin_work = NULL; | |
3896 | ||
3897 | if (work->event) | |
3898 | drm_send_vblank_event(intel_crtc->base.dev, | |
3899 | intel_crtc->pipe, | |
3900 | work->event); | |
3901 | ||
3902 | drm_crtc_vblank_put(&intel_crtc->base); | |
3903 | ||
3904 | wake_up_all(&dev_priv->pending_flip_queue); | |
3905 | queue_work(dev_priv->wq, &work->work); | |
3906 | ||
3907 | trace_i915_flip_complete(intel_crtc->plane, | |
3908 | work->pending_flip_obj); | |
3909 | } | |
3910 | ||
46a55d30 | 3911 | void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3912 | { |
0f91128d | 3913 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3914 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 | 3915 | |
2c10d571 | 3916 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
9c787942 CW |
3917 | if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue, |
3918 | !intel_crtc_has_pending_flip(crtc), | |
3919 | 60*HZ) == 0)) { | |
3920 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2c10d571 | 3921 | |
5e2d7afc | 3922 | spin_lock_irq(&dev->event_lock); |
9c787942 CW |
3923 | if (intel_crtc->unpin_work) { |
3924 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
3925 | page_flip_completed(intel_crtc); | |
3926 | } | |
5e2d7afc | 3927 | spin_unlock_irq(&dev->event_lock); |
9c787942 | 3928 | } |
5bb61643 | 3929 | |
975d568a CW |
3930 | if (crtc->primary->fb) { |
3931 | mutex_lock(&dev->struct_mutex); | |
3932 | intel_finish_fb(crtc->primary->fb); | |
3933 | mutex_unlock(&dev->struct_mutex); | |
3934 | } | |
e6c3a2a6 CW |
3935 | } |
3936 | ||
e615efe4 ED |
3937 | /* Program iCLKIP clock to the desired frequency */ |
3938 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3939 | { | |
3940 | struct drm_device *dev = crtc->dev; | |
3941 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 3942 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
3943 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3944 | u32 temp; | |
3945 | ||
a580516d | 3946 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 3947 | |
e615efe4 ED |
3948 | /* It is necessary to ungate the pixclk gate prior to programming |
3949 | * the divisors, and gate it back when it is done. | |
3950 | */ | |
3951 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3952 | ||
3953 | /* Disable SSCCTL */ | |
3954 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
3955 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
3956 | SBI_SSCCTL_DISABLE, | |
3957 | SBI_ICLK); | |
e615efe4 ED |
3958 | |
3959 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3960 | if (clock == 20000) { |
e615efe4 ED |
3961 | auxdiv = 1; |
3962 | divsel = 0x41; | |
3963 | phaseinc = 0x20; | |
3964 | } else { | |
3965 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3966 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3967 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3968 | * convert the virtual clock precision to KHz here for higher |
3969 | * precision. | |
3970 | */ | |
3971 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3972 | u32 iclk_pi_range = 64; | |
3973 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3974 | ||
12d7ceed | 3975 | desired_divisor = (iclk_virtual_root_freq / clock); |
e615efe4 ED |
3976 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3977 | pi_value = desired_divisor % iclk_pi_range; | |
3978 | ||
3979 | auxdiv = 0; | |
3980 | divsel = msb_divisor_value - 2; | |
3981 | phaseinc = pi_value; | |
3982 | } | |
3983 | ||
3984 | /* This should not happen with any sane values */ | |
3985 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3986 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3987 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3988 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3989 | ||
3990 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3991 | clock, |
e615efe4 ED |
3992 | auxdiv, |
3993 | divsel, | |
3994 | phasedir, | |
3995 | phaseinc); | |
3996 | ||
3997 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 3998 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3999 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
4000 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
4001 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
4002 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
4003 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
4004 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 4005 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
4006 | |
4007 | /* Program SSCAUXDIV */ | |
988d6ee8 | 4008 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
4009 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
4010 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 4011 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
4012 | |
4013 | /* Enable modulator and associated divider */ | |
988d6ee8 | 4014 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 4015 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 4016 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
4017 | |
4018 | /* Wait for initialization time */ | |
4019 | udelay(24); | |
4020 | ||
4021 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 | 4022 | |
a580516d | 4023 | mutex_unlock(&dev_priv->sb_lock); |
e615efe4 ED |
4024 | } |
4025 | ||
275f01b2 DV |
4026 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4027 | enum pipe pch_transcoder) | |
4028 | { | |
4029 | struct drm_device *dev = crtc->base.dev; | |
4030 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 4031 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4032 | |
4033 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4034 | I915_READ(HTOTAL(cpu_transcoder))); | |
4035 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4036 | I915_READ(HBLANK(cpu_transcoder))); | |
4037 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4038 | I915_READ(HSYNC(cpu_transcoder))); | |
4039 | ||
4040 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4041 | I915_READ(VTOTAL(cpu_transcoder))); | |
4042 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4043 | I915_READ(VBLANK(cpu_transcoder))); | |
4044 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4045 | I915_READ(VSYNC(cpu_transcoder))); | |
4046 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4047 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4048 | } | |
4049 | ||
003632d9 | 4050 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 DV |
4051 | { |
4052 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4053 | uint32_t temp; | |
4054 | ||
4055 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4056 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4057 | return; |
4058 | ||
4059 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4060 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4061 | ||
003632d9 ACO |
4062 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4063 | if (enable) | |
4064 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4065 | ||
4066 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4067 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4068 | POSTING_READ(SOUTH_CHICKEN1); | |
4069 | } | |
4070 | ||
4071 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4072 | { | |
4073 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4074 | |
4075 | switch (intel_crtc->pipe) { | |
4076 | case PIPE_A: | |
4077 | break; | |
4078 | case PIPE_B: | |
6e3c9717 | 4079 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4080 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4081 | else |
003632d9 | 4082 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4083 | |
4084 | break; | |
4085 | case PIPE_C: | |
003632d9 | 4086 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4087 | |
4088 | break; | |
4089 | default: | |
4090 | BUG(); | |
4091 | } | |
4092 | } | |
4093 | ||
f67a559d JB |
4094 | /* |
4095 | * Enable PCH resources required for PCH ports: | |
4096 | * - PCH PLLs | |
4097 | * - FDI training & RX/TX | |
4098 | * - update transcoder timings | |
4099 | * - DP transcoding bits | |
4100 | * - transcoder | |
4101 | */ | |
4102 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4103 | { |
4104 | struct drm_device *dev = crtc->dev; | |
4105 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4106 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4107 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 4108 | u32 reg, temp; |
2c07245f | 4109 | |
ab9412ba | 4110 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4111 | |
1fbc0d78 DV |
4112 | if (IS_IVYBRIDGE(dev)) |
4113 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
4114 | ||
cd986abb DV |
4115 | /* Write the TU size bits before fdi link training, so that error |
4116 | * detection works. */ | |
4117 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4118 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4119 | ||
c98e9dcf | 4120 | /* For PCH output, training FDI link */ |
674cf967 | 4121 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4122 | |
3ad8a208 DV |
4123 | /* We need to program the right clock selection before writing the pixel |
4124 | * mutliplier into the DPLL. */ | |
303b81e0 | 4125 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 4126 | u32 sel; |
4b645f14 | 4127 | |
c98e9dcf | 4128 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4129 | temp |= TRANS_DPLL_ENABLE(pipe); |
4130 | sel = TRANS_DPLLB_SEL(pipe); | |
6e3c9717 | 4131 | if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
4132 | temp |= sel; |
4133 | else | |
4134 | temp &= ~sel; | |
c98e9dcf | 4135 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4136 | } |
5eddb70b | 4137 | |
3ad8a208 DV |
4138 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4139 | * transcoder, and we actually should do this to not upset any PCH | |
4140 | * transcoder that already use the clock when we share it. | |
4141 | * | |
4142 | * Note that enable_shared_dpll tries to do the right thing, but | |
4143 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4144 | * the right LVDS enable sequence. */ | |
85b3894f | 4145 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4146 | |
d9b6cb56 JB |
4147 | /* set transcoder timing, panel must allow it */ |
4148 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4149 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4150 | |
303b81e0 | 4151 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4152 | |
c98e9dcf | 4153 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e3c9717 | 4154 | if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { |
dfd07d72 | 4155 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
4156 | reg = TRANS_DP_CTL(pipe); |
4157 | temp = I915_READ(reg); | |
4158 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4159 | TRANS_DP_SYNC_MASK | |
4160 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4161 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4162 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
4163 | |
4164 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 4165 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 4166 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4167 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4168 | |
4169 | switch (intel_trans_dp_port_sel(crtc)) { | |
4170 | case PCH_DP_B: | |
5eddb70b | 4171 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
4172 | break; |
4173 | case PCH_DP_C: | |
5eddb70b | 4174 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
4175 | break; |
4176 | case PCH_DP_D: | |
5eddb70b | 4177 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4178 | break; |
4179 | default: | |
e95d41e1 | 4180 | BUG(); |
32f9d658 | 4181 | } |
2c07245f | 4182 | |
5eddb70b | 4183 | I915_WRITE(reg, temp); |
6be4a607 | 4184 | } |
b52eb4dc | 4185 | |
b8a4f404 | 4186 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4187 | } |
4188 | ||
1507e5bd PZ |
4189 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4190 | { | |
4191 | struct drm_device *dev = crtc->dev; | |
4192 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4193 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6e3c9717 | 4194 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4195 | |
ab9412ba | 4196 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4197 | |
8c52b5e8 | 4198 | lpt_program_iclkip(crtc); |
1507e5bd | 4199 | |
0540e488 | 4200 | /* Set transcoder timing. */ |
275f01b2 | 4201 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4202 | |
937bb610 | 4203 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4204 | } |
4205 | ||
716c2e55 | 4206 | void intel_put_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 4207 | { |
e2b78267 | 4208 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
ee7b9f93 JB |
4209 | |
4210 | if (pll == NULL) | |
4211 | return; | |
4212 | ||
3e369b76 | 4213 | if (!(pll->config.crtc_mask & (1 << crtc->pipe))) { |
1e6f2ddc | 4214 | WARN(1, "bad %s crtc mask\n", pll->name); |
ee7b9f93 JB |
4215 | return; |
4216 | } | |
4217 | ||
3e369b76 ACO |
4218 | pll->config.crtc_mask &= ~(1 << crtc->pipe); |
4219 | if (pll->config.crtc_mask == 0) { | |
f4a091c7 DV |
4220 | WARN_ON(pll->on); |
4221 | WARN_ON(pll->active); | |
4222 | } | |
4223 | ||
6e3c9717 | 4224 | crtc->config->shared_dpll = DPLL_ID_PRIVATE; |
ee7b9f93 JB |
4225 | } |
4226 | ||
190f68c5 ACO |
4227 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, |
4228 | struct intel_crtc_state *crtc_state) | |
ee7b9f93 | 4229 | { |
e2b78267 | 4230 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
8bd31e67 | 4231 | struct intel_shared_dpll *pll; |
e2b78267 | 4232 | enum intel_dpll_id i; |
ee7b9f93 | 4233 | |
98b6bd99 DV |
4234 | if (HAS_PCH_IBX(dev_priv->dev)) { |
4235 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 4236 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 4237 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 4238 | |
46edb027 DV |
4239 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
4240 | crtc->base.base.id, pll->name); | |
98b6bd99 | 4241 | |
8bd31e67 | 4242 | WARN_ON(pll->new_config->crtc_mask); |
f2a69f44 | 4243 | |
98b6bd99 DV |
4244 | goto found; |
4245 | } | |
4246 | ||
bcddf610 S |
4247 | if (IS_BROXTON(dev_priv->dev)) { |
4248 | /* PLL is attached to port in bxt */ | |
4249 | struct intel_encoder *encoder; | |
4250 | struct intel_digital_port *intel_dig_port; | |
4251 | ||
4252 | encoder = intel_ddi_get_crtc_new_encoder(crtc_state); | |
4253 | if (WARN_ON(!encoder)) | |
4254 | return NULL; | |
4255 | ||
4256 | intel_dig_port = enc_to_dig_port(&encoder->base); | |
4257 | /* 1:1 mapping between ports and PLLs */ | |
4258 | i = (enum intel_dpll_id)intel_dig_port->port; | |
4259 | pll = &dev_priv->shared_dplls[i]; | |
4260 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", | |
4261 | crtc->base.base.id, pll->name); | |
4262 | WARN_ON(pll->new_config->crtc_mask); | |
4263 | ||
4264 | goto found; | |
4265 | } | |
4266 | ||
e72f9fbf DV |
4267 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4268 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 JB |
4269 | |
4270 | /* Only want to check enabled timings first */ | |
8bd31e67 | 4271 | if (pll->new_config->crtc_mask == 0) |
ee7b9f93 JB |
4272 | continue; |
4273 | ||
190f68c5 | 4274 | if (memcmp(&crtc_state->dpll_hw_state, |
8bd31e67 ACO |
4275 | &pll->new_config->hw_state, |
4276 | sizeof(pll->new_config->hw_state)) == 0) { | |
4277 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n", | |
1e6f2ddc | 4278 | crtc->base.base.id, pll->name, |
8bd31e67 ACO |
4279 | pll->new_config->crtc_mask, |
4280 | pll->active); | |
ee7b9f93 JB |
4281 | goto found; |
4282 | } | |
4283 | } | |
4284 | ||
4285 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
4286 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4287 | pll = &dev_priv->shared_dplls[i]; | |
8bd31e67 | 4288 | if (pll->new_config->crtc_mask == 0) { |
46edb027 DV |
4289 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
4290 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
4291 | goto found; |
4292 | } | |
4293 | } | |
4294 | ||
4295 | return NULL; | |
4296 | ||
4297 | found: | |
8bd31e67 | 4298 | if (pll->new_config->crtc_mask == 0) |
190f68c5 | 4299 | pll->new_config->hw_state = crtc_state->dpll_hw_state; |
f2a69f44 | 4300 | |
190f68c5 | 4301 | crtc_state->shared_dpll = i; |
46edb027 DV |
4302 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
4303 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 4304 | |
8bd31e67 | 4305 | pll->new_config->crtc_mask |= 1 << crtc->pipe; |
e04c7350 | 4306 | |
ee7b9f93 JB |
4307 | return pll; |
4308 | } | |
4309 | ||
8bd31e67 ACO |
4310 | /** |
4311 | * intel_shared_dpll_start_config - start a new PLL staged config | |
4312 | * @dev_priv: DRM device | |
4313 | * @clear_pipes: mask of pipes that will have their PLLs freed | |
4314 | * | |
4315 | * Starts a new PLL staged config, copying the current config but | |
4316 | * releasing the references of pipes specified in clear_pipes. | |
4317 | */ | |
4318 | static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv, | |
4319 | unsigned clear_pipes) | |
4320 | { | |
4321 | struct intel_shared_dpll *pll; | |
4322 | enum intel_dpll_id i; | |
4323 | ||
4324 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
4325 | pll = &dev_priv->shared_dplls[i]; | |
4326 | ||
4327 | pll->new_config = kmemdup(&pll->config, sizeof pll->config, | |
4328 | GFP_KERNEL); | |
4329 | if (!pll->new_config) | |
4330 | goto cleanup; | |
4331 | ||
4332 | pll->new_config->crtc_mask &= ~clear_pipes; | |
4333 | } | |
4334 | ||
4335 | return 0; | |
4336 | ||
4337 | cleanup: | |
4338 | while (--i >= 0) { | |
4339 | pll = &dev_priv->shared_dplls[i]; | |
f354d733 | 4340 | kfree(pll->new_config); |
8bd31e67 ACO |
4341 | pll->new_config = NULL; |
4342 | } | |
4343 | ||
4344 | return -ENOMEM; | |
4345 | } | |
4346 | ||
4347 | static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv) | |
4348 | { | |
4349 | struct intel_shared_dpll *pll; | |
4350 | enum intel_dpll_id i; | |
4351 | ||
4352 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
4353 | pll = &dev_priv->shared_dplls[i]; | |
4354 | ||
4355 | WARN_ON(pll->new_config == &pll->config); | |
4356 | ||
4357 | pll->config = *pll->new_config; | |
4358 | kfree(pll->new_config); | |
4359 | pll->new_config = NULL; | |
4360 | } | |
4361 | } | |
4362 | ||
4363 | static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv) | |
4364 | { | |
4365 | struct intel_shared_dpll *pll; | |
4366 | enum intel_dpll_id i; | |
4367 | ||
4368 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
4369 | pll = &dev_priv->shared_dplls[i]; | |
4370 | ||
4371 | WARN_ON(pll->new_config == &pll->config); | |
4372 | ||
4373 | kfree(pll->new_config); | |
4374 | pll->new_config = NULL; | |
4375 | } | |
4376 | } | |
4377 | ||
a1520318 | 4378 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
4379 | { |
4380 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 4381 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4382 | u32 temp; |
4383 | ||
4384 | temp = I915_READ(dslreg); | |
4385 | udelay(500); | |
4386 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4387 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4388 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4389 | } |
4390 | } | |
4391 | ||
a1b2278e CK |
4392 | /** |
4393 | * skl_update_scaler_users - Stages update to crtc's scaler state | |
4394 | * @intel_crtc: crtc | |
4395 | * @crtc_state: crtc_state | |
4396 | * @plane: plane (NULL indicates crtc is requesting update) | |
4397 | * @plane_state: plane's state | |
4398 | * @force_detach: request unconditional detachment of scaler | |
4399 | * | |
4400 | * This function updates scaler state for requested plane or crtc. | |
4401 | * To request scaler usage update for a plane, caller shall pass plane pointer. | |
4402 | * To request scaler usage update for crtc, caller shall pass plane pointer | |
4403 | * as NULL. | |
4404 | * | |
4405 | * Return | |
4406 | * 0 - scaler_usage updated successfully | |
4407 | * error - requested scaling cannot be supported or other error condition | |
4408 | */ | |
4409 | int | |
4410 | skl_update_scaler_users( | |
4411 | struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state, | |
4412 | struct intel_plane *intel_plane, struct intel_plane_state *plane_state, | |
4413 | int force_detach) | |
4414 | { | |
4415 | int need_scaling; | |
4416 | int idx; | |
4417 | int src_w, src_h, dst_w, dst_h; | |
4418 | int *scaler_id; | |
4419 | struct drm_framebuffer *fb; | |
4420 | struct intel_crtc_scaler_state *scaler_state; | |
6156a456 | 4421 | unsigned int rotation; |
a1b2278e CK |
4422 | |
4423 | if (!intel_crtc || !crtc_state) | |
4424 | return 0; | |
4425 | ||
4426 | scaler_state = &crtc_state->scaler_state; | |
4427 | ||
4428 | idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX; | |
4429 | fb = intel_plane ? plane_state->base.fb : NULL; | |
4430 | ||
4431 | if (intel_plane) { | |
4432 | src_w = drm_rect_width(&plane_state->src) >> 16; | |
4433 | src_h = drm_rect_height(&plane_state->src) >> 16; | |
4434 | dst_w = drm_rect_width(&plane_state->dst); | |
4435 | dst_h = drm_rect_height(&plane_state->dst); | |
4436 | scaler_id = &plane_state->scaler_id; | |
6156a456 | 4437 | rotation = plane_state->base.rotation; |
a1b2278e CK |
4438 | } else { |
4439 | struct drm_display_mode *adjusted_mode = | |
4440 | &crtc_state->base.adjusted_mode; | |
4441 | src_w = crtc_state->pipe_src_w; | |
4442 | src_h = crtc_state->pipe_src_h; | |
4443 | dst_w = adjusted_mode->hdisplay; | |
4444 | dst_h = adjusted_mode->vdisplay; | |
4445 | scaler_id = &scaler_state->scaler_id; | |
6156a456 | 4446 | rotation = DRM_ROTATE_0; |
a1b2278e | 4447 | } |
6156a456 CK |
4448 | |
4449 | need_scaling = intel_rotation_90_or_270(rotation) ? | |
4450 | (src_h != dst_w || src_w != dst_h): | |
4451 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4452 | |
4453 | /* | |
4454 | * if plane is being disabled or scaler is no more required or force detach | |
4455 | * - free scaler binded to this plane/crtc | |
4456 | * - in order to do this, update crtc->scaler_usage | |
4457 | * | |
4458 | * Here scaler state in crtc_state is set free so that | |
4459 | * scaler can be assigned to other user. Actual register | |
4460 | * update to free the scaler is done in plane/panel-fit programming. | |
4461 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4462 | */ | |
4463 | if (force_detach || !need_scaling || (intel_plane && | |
4464 | (!fb || !plane_state->visible))) { | |
4465 | if (*scaler_id >= 0) { | |
4466 | scaler_state->scaler_users &= ~(1 << idx); | |
4467 | scaler_state->scalers[*scaler_id].in_use = 0; | |
4468 | ||
4469 | DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d " | |
4470 | "crtc_state = %p scaler_users = 0x%x\n", | |
4471 | intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC", | |
4472 | intel_plane ? intel_plane->base.base.id : | |
4473 | intel_crtc->base.base.id, crtc_state, | |
4474 | scaler_state->scaler_users); | |
4475 | *scaler_id = -1; | |
4476 | } | |
4477 | return 0; | |
4478 | } | |
4479 | ||
4480 | /* range checks */ | |
4481 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4482 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4483 | ||
4484 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4485 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
4486 | DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u " | |
4487 | "size is out of scaler range\n", | |
4488 | intel_plane ? "PLANE" : "CRTC", | |
4489 | intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id, | |
4490 | intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h); | |
4491 | return -EINVAL; | |
4492 | } | |
4493 | ||
4494 | /* check colorkey */ | |
225c228a CK |
4495 | if (WARN_ON(intel_plane && |
4496 | intel_plane->ckey.flags != I915_SET_COLORKEY_NONE)) { | |
4497 | DRM_DEBUG_KMS("PLANE:%d scaling %ux%u->%ux%u not allowed with colorkey", | |
4498 | intel_plane->base.base.id, src_w, src_h, dst_w, dst_h); | |
a1b2278e CK |
4499 | return -EINVAL; |
4500 | } | |
4501 | ||
4502 | /* Check src format */ | |
4503 | if (intel_plane) { | |
4504 | switch (fb->pixel_format) { | |
4505 | case DRM_FORMAT_RGB565: | |
4506 | case DRM_FORMAT_XBGR8888: | |
4507 | case DRM_FORMAT_XRGB8888: | |
4508 | case DRM_FORMAT_ABGR8888: | |
4509 | case DRM_FORMAT_ARGB8888: | |
4510 | case DRM_FORMAT_XRGB2101010: | |
a1b2278e | 4511 | case DRM_FORMAT_XBGR2101010: |
a1b2278e CK |
4512 | case DRM_FORMAT_YUYV: |
4513 | case DRM_FORMAT_YVYU: | |
4514 | case DRM_FORMAT_UYVY: | |
4515 | case DRM_FORMAT_VYUY: | |
4516 | break; | |
4517 | default: | |
4518 | DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n", | |
4519 | intel_plane->base.base.id, fb->base.id, fb->pixel_format); | |
4520 | return -EINVAL; | |
4521 | } | |
4522 | } | |
4523 | ||
4524 | /* mark this plane as a scaler user in crtc_state */ | |
4525 | scaler_state->scaler_users |= (1 << idx); | |
4526 | DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u " | |
4527 | "crtc_state = %p scaler_users = 0x%x\n", | |
4528 | intel_plane ? "PLANE" : "CRTC", | |
4529 | intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id, | |
4530 | src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users); | |
4531 | return 0; | |
4532 | } | |
4533 | ||
4534 | static void skylake_pfit_update(struct intel_crtc *crtc, int enable) | |
bd2e244f JB |
4535 | { |
4536 | struct drm_device *dev = crtc->base.dev; | |
4537 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4538 | int pipe = crtc->pipe; | |
a1b2278e CK |
4539 | struct intel_crtc_scaler_state *scaler_state = |
4540 | &crtc->config->scaler_state; | |
4541 | ||
4542 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4543 | ||
4544 | /* To update pfit, first update scaler state */ | |
4545 | skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable); | |
4546 | intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config); | |
4547 | skl_detach_scalers(crtc); | |
4548 | if (!enable) | |
4549 | return; | |
bd2e244f | 4550 | |
6e3c9717 | 4551 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4552 | int id; |
4553 | ||
4554 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4555 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4556 | return; | |
4557 | } | |
4558 | ||
4559 | id = scaler_state->scaler_id; | |
4560 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4561 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4562 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4563 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4564 | ||
4565 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4566 | } |
4567 | } | |
4568 | ||
b074cec8 JB |
4569 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4570 | { | |
4571 | struct drm_device *dev = crtc->base.dev; | |
4572 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4573 | int pipe = crtc->pipe; | |
4574 | ||
6e3c9717 | 4575 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4576 | /* Force use of hard-coded filter coefficients |
4577 | * as some pre-programmed values are broken, | |
4578 | * e.g. x201. | |
4579 | */ | |
4580 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4581 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4582 | PF_PIPE_SEL_IVB(pipe)); | |
4583 | else | |
4584 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4585 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4586 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4587 | } |
4588 | } | |
4589 | ||
4a3b8769 | 4590 | static void intel_enable_sprite_planes(struct drm_crtc *crtc) |
bb53d4ae VS |
4591 | { |
4592 | struct drm_device *dev = crtc->dev; | |
4593 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 4594 | struct drm_plane *plane; |
bb53d4ae VS |
4595 | struct intel_plane *intel_plane; |
4596 | ||
af2b653b MR |
4597 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
4598 | intel_plane = to_intel_plane(plane); | |
bb53d4ae VS |
4599 | if (intel_plane->pipe == pipe) |
4600 | intel_plane_restore(&intel_plane->base); | |
af2b653b | 4601 | } |
bb53d4ae VS |
4602 | } |
4603 | ||
20bc8673 | 4604 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4605 | { |
cea165c3 VS |
4606 | struct drm_device *dev = crtc->base.dev; |
4607 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 | 4608 | |
6e3c9717 | 4609 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4610 | return; |
4611 | ||
cea165c3 VS |
4612 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
4613 | intel_wait_for_vblank(dev, crtc->pipe); | |
4614 | ||
d77e4531 | 4615 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4616 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4617 | mutex_lock(&dev_priv->rps.hw_lock); |
4618 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4619 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4620 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4621 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4622 | * mailbox." Moreover, the mailbox may return a bogus state, |
4623 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4624 | */ |
4625 | } else { | |
4626 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4627 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4628 | * is essentially intel_wait_for_vblank. If we don't have this | |
4629 | * and don't wait for vblanks until the end of crtc_enable, then | |
4630 | * the HW state readout code will complain that the expected | |
4631 | * IPS_CTL value is not the one we read. */ | |
4632 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
4633 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
4634 | } | |
d77e4531 PZ |
4635 | } |
4636 | ||
20bc8673 | 4637 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4638 | { |
4639 | struct drm_device *dev = crtc->base.dev; | |
4640 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4641 | ||
6e3c9717 | 4642 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4643 | return; |
4644 | ||
4645 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4646 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4647 | mutex_lock(&dev_priv->rps.hw_lock); |
4648 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4649 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
4650 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
4651 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
4652 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 4653 | } else { |
2a114cc1 | 4654 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4655 | POSTING_READ(IPS_CTL); |
4656 | } | |
d77e4531 PZ |
4657 | |
4658 | /* We need to wait for a vblank before we can disable the plane. */ | |
4659 | intel_wait_for_vblank(dev, crtc->pipe); | |
4660 | } | |
4661 | ||
4662 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
4663 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
4664 | { | |
4665 | struct drm_device *dev = crtc->dev; | |
4666 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4667 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4668 | enum pipe pipe = intel_crtc->pipe; | |
4669 | int palreg = PALETTE(pipe); | |
4670 | int i; | |
4671 | bool reenable_ips = false; | |
4672 | ||
4673 | /* The clocks have to be on to load the palette. */ | |
83d65738 | 4674 | if (!crtc->state->enable || !intel_crtc->active) |
d77e4531 PZ |
4675 | return; |
4676 | ||
50360403 | 4677 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) { |
409ee761 | 4678 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) |
d77e4531 PZ |
4679 | assert_dsi_pll_enabled(dev_priv); |
4680 | else | |
4681 | assert_pll_enabled(dev_priv, pipe); | |
4682 | } | |
4683 | ||
4684 | /* use legacy palette for Ironlake */ | |
7a1db49a | 4685 | if (!HAS_GMCH_DISPLAY(dev)) |
d77e4531 PZ |
4686 | palreg = LGC_PALETTE(pipe); |
4687 | ||
4688 | /* Workaround : Do not read or write the pipe palette/gamma data while | |
4689 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
4690 | */ | |
6e3c9717 | 4691 | if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled && |
d77e4531 PZ |
4692 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
4693 | GAMMA_MODE_MODE_SPLIT)) { | |
4694 | hsw_disable_ips(intel_crtc); | |
4695 | reenable_ips = true; | |
4696 | } | |
4697 | ||
4698 | for (i = 0; i < 256; i++) { | |
4699 | I915_WRITE(palreg + 4 * i, | |
4700 | (intel_crtc->lut_r[i] << 16) | | |
4701 | (intel_crtc->lut_g[i] << 8) | | |
4702 | intel_crtc->lut_b[i]); | |
4703 | } | |
4704 | ||
4705 | if (reenable_ips) | |
4706 | hsw_enable_ips(intel_crtc); | |
4707 | } | |
4708 | ||
7cac945f | 4709 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4710 | { |
7cac945f | 4711 | if (intel_crtc->overlay) { |
d3eedb1a VS |
4712 | struct drm_device *dev = intel_crtc->base.dev; |
4713 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4714 | ||
4715 | mutex_lock(&dev->struct_mutex); | |
4716 | dev_priv->mm.interruptible = false; | |
4717 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4718 | dev_priv->mm.interruptible = true; | |
4719 | mutex_unlock(&dev->struct_mutex); | |
4720 | } | |
4721 | ||
4722 | /* Let userspace switch the overlay on again. In most cases userspace | |
4723 | * has to recompute where to put it anyway. | |
4724 | */ | |
4725 | } | |
4726 | ||
87d4300a ML |
4727 | /** |
4728 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4729 | * @crtc: the CRTC whose primary plane was just enabled | |
4730 | * | |
4731 | * Performs potentially sleeping operations that must be done after the primary | |
4732 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4733 | * called due to an explicit primary plane update, or due to an implicit | |
4734 | * re-enable that is caused when a sprite plane is updated to no longer | |
4735 | * completely hide the primary plane. | |
4736 | */ | |
4737 | static void | |
4738 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4739 | { |
4740 | struct drm_device *dev = crtc->dev; | |
87d4300a | 4741 | struct drm_i915_private *dev_priv = dev->dev_private; |
a5c4d7bc VS |
4742 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4743 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4744 | |
87d4300a ML |
4745 | /* |
4746 | * BDW signals flip done immediately if the plane | |
4747 | * is disabled, even if the plane enable is already | |
4748 | * armed to occur at the next vblank :( | |
4749 | */ | |
4750 | if (IS_BROADWELL(dev)) | |
4751 | intel_wait_for_vblank(dev, pipe); | |
a5c4d7bc | 4752 | |
87d4300a ML |
4753 | /* |
4754 | * FIXME IPS should be fine as long as one plane is | |
4755 | * enabled, but in practice it seems to have problems | |
4756 | * when going from primary only to sprite only and vice | |
4757 | * versa. | |
4758 | */ | |
a5c4d7bc VS |
4759 | hsw_enable_ips(intel_crtc); |
4760 | ||
4761 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 4762 | intel_fbc_update(dev); |
a5c4d7bc | 4763 | mutex_unlock(&dev->struct_mutex); |
f99d7069 DV |
4764 | |
4765 | /* | |
87d4300a ML |
4766 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4767 | * So don't enable underrun reporting before at least some planes | |
4768 | * are enabled. | |
4769 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4770 | * but leave the pipe running. | |
f99d7069 | 4771 | */ |
87d4300a ML |
4772 | if (IS_GEN2(dev)) |
4773 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4774 | ||
4775 | /* Underruns don't raise interrupts, so check manually. */ | |
4776 | if (HAS_GMCH_DISPLAY(dev)) | |
4777 | i9xx_check_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4778 | } |
4779 | ||
87d4300a ML |
4780 | /** |
4781 | * intel_pre_disable_primary - Perform operations before disabling primary plane | |
4782 | * @crtc: the CRTC whose primary plane is to be disabled | |
4783 | * | |
4784 | * Performs potentially sleeping operations that must be done before the | |
4785 | * primary plane is disabled, such as updating FBC and IPS. Note that this may | |
4786 | * be called due to an explicit primary plane update, or due to an implicit | |
4787 | * disable that is caused when a sprite plane completely hides the primary | |
4788 | * plane. | |
4789 | */ | |
4790 | static void | |
4791 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4792 | { |
4793 | struct drm_device *dev = crtc->dev; | |
4794 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4795 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4796 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4797 | |
87d4300a ML |
4798 | /* |
4799 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4800 | * So diasble underrun reporting before all the planes get disabled. | |
4801 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4802 | * but leave the pipe running. | |
4803 | */ | |
4804 | if (IS_GEN2(dev)) | |
4805 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
a5c4d7bc | 4806 | |
87d4300a ML |
4807 | /* |
4808 | * Vblank time updates from the shadow to live plane control register | |
4809 | * are blocked if the memory self-refresh mode is active at that | |
4810 | * moment. So to make sure the plane gets truly disabled, disable | |
4811 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4812 | * will be checked/applied by the HW only at the next frame start | |
4813 | * event which is after the vblank start event, so we need to have a | |
4814 | * wait-for-vblank between disabling the plane and the pipe. | |
4815 | */ | |
4816 | if (HAS_GMCH_DISPLAY(dev)) | |
4817 | intel_set_memory_cxsr(dev_priv, false); | |
4818 | ||
4819 | mutex_lock(&dev->struct_mutex); | |
e35fef21 | 4820 | if (dev_priv->fbc.crtc == intel_crtc) |
7ff0ebcc | 4821 | intel_fbc_disable(dev); |
87d4300a | 4822 | mutex_unlock(&dev->struct_mutex); |
a5c4d7bc | 4823 | |
87d4300a ML |
4824 | /* |
4825 | * FIXME IPS should be fine as long as one plane is | |
4826 | * enabled, but in practice it seems to have problems | |
4827 | * when going from primary only to sprite only and vice | |
4828 | * versa. | |
4829 | */ | |
a5c4d7bc | 4830 | hsw_disable_ips(intel_crtc); |
87d4300a ML |
4831 | } |
4832 | ||
4833 | static void intel_crtc_enable_planes(struct drm_crtc *crtc) | |
4834 | { | |
2d847d45 RV |
4835 | struct drm_device *dev = crtc->dev; |
4836 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4837 | int pipe = intel_crtc->pipe; | |
4838 | ||
87d4300a ML |
4839 | intel_enable_primary_hw_plane(crtc->primary, crtc); |
4840 | intel_enable_sprite_planes(crtc); | |
4841 | intel_crtc_update_cursor(crtc, true); | |
87d4300a ML |
4842 | |
4843 | intel_post_enable_primary(crtc); | |
2d847d45 RV |
4844 | |
4845 | /* | |
4846 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4847 | * to compute the mask of flip planes precisely. For the time being | |
4848 | * consider this a flip to a NULL plane. | |
4849 | */ | |
4850 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
87d4300a ML |
4851 | } |
4852 | ||
4853 | static void intel_crtc_disable_planes(struct drm_crtc *crtc) | |
4854 | { | |
4855 | struct drm_device *dev = crtc->dev; | |
4856 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4857 | struct intel_plane *intel_plane; | |
4858 | int pipe = intel_crtc->pipe; | |
4859 | ||
4860 | intel_crtc_wait_for_pending_flips(crtc); | |
4861 | ||
4862 | intel_pre_disable_primary(crtc); | |
a5c4d7bc | 4863 | |
7cac945f | 4864 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 ML |
4865 | for_each_intel_plane(dev, intel_plane) { |
4866 | if (intel_plane->pipe == pipe) { | |
4867 | struct drm_crtc *from = intel_plane->base.crtc; | |
4868 | ||
4869 | intel_plane->disable_plane(&intel_plane->base, | |
4870 | from ?: crtc, true); | |
4871 | } | |
4872 | } | |
f98551ae | 4873 | |
f99d7069 DV |
4874 | /* |
4875 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4876 | * to compute the mask of flip planes precisely. For the time being | |
4877 | * consider this a flip to a NULL plane. | |
4878 | */ | |
4879 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4880 | } |
4881 | ||
f67a559d JB |
4882 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4883 | { | |
4884 | struct drm_device *dev = crtc->dev; | |
4885 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4886 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4887 | struct intel_encoder *encoder; |
f67a559d | 4888 | int pipe = intel_crtc->pipe; |
f67a559d | 4889 | |
83d65738 | 4890 | WARN_ON(!crtc->state->enable); |
08a48469 | 4891 | |
f67a559d JB |
4892 | if (intel_crtc->active) |
4893 | return; | |
4894 | ||
6e3c9717 | 4895 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
4896 | intel_prepare_shared_dpll(intel_crtc); |
4897 | ||
6e3c9717 | 4898 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4899 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
4900 | |
4901 | intel_set_pipe_timings(intel_crtc); | |
4902 | ||
6e3c9717 | 4903 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 4904 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4905 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
4906 | } |
4907 | ||
4908 | ironlake_set_pipeconf(crtc); | |
4909 | ||
f67a559d | 4910 | intel_crtc->active = true; |
8664281b | 4911 | |
a72e4c9f DV |
4912 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4913 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
8664281b | 4914 | |
f6736a1a | 4915 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4916 | if (encoder->pre_enable) |
4917 | encoder->pre_enable(encoder); | |
f67a559d | 4918 | |
6e3c9717 | 4919 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
4920 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4921 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4922 | * enabling. */ | |
88cefb6c | 4923 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4924 | } else { |
4925 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4926 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4927 | } | |
f67a559d | 4928 | |
b074cec8 | 4929 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4930 | |
9c54c0dd JB |
4931 | /* |
4932 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4933 | * clocks enabled | |
4934 | */ | |
4935 | intel_crtc_load_lut(crtc); | |
4936 | ||
f37fcc2a | 4937 | intel_update_watermarks(crtc); |
e1fdc473 | 4938 | intel_enable_pipe(intel_crtc); |
f67a559d | 4939 | |
6e3c9717 | 4940 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 4941 | ironlake_pch_enable(crtc); |
c98e9dcf | 4942 | |
f9b61ff6 DV |
4943 | assert_vblank_disabled(crtc); |
4944 | drm_crtc_vblank_on(crtc); | |
4945 | ||
fa5c73b1 DV |
4946 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4947 | encoder->enable(encoder); | |
61b77ddd DV |
4948 | |
4949 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4950 | cpt_verify_modeset(dev, intel_crtc->pipe); |
6be4a607 JB |
4951 | } |
4952 | ||
42db64ef PZ |
4953 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4954 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4955 | { | |
f5adf94e | 4956 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4957 | } |
4958 | ||
e4916946 PZ |
4959 | /* |
4960 | * This implements the workaround described in the "notes" section of the mode | |
4961 | * set sequence documentation. When going from no pipes or single pipe to | |
4962 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
4963 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
4964 | */ | |
4965 | static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) | |
4966 | { | |
4967 | struct drm_device *dev = crtc->base.dev; | |
4968 | struct intel_crtc *crtc_it, *other_active_crtc = NULL; | |
4969 | ||
4970 | /* We want to get the other_active_crtc only if there's only 1 other | |
4971 | * active crtc. */ | |
d3fcc808 | 4972 | for_each_intel_crtc(dev, crtc_it) { |
e4916946 PZ |
4973 | if (!crtc_it->active || crtc_it == crtc) |
4974 | continue; | |
4975 | ||
4976 | if (other_active_crtc) | |
4977 | return; | |
4978 | ||
4979 | other_active_crtc = crtc_it; | |
4980 | } | |
4981 | if (!other_active_crtc) | |
4982 | return; | |
4983 | ||
4984 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4985 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4986 | } | |
4987 | ||
4f771f10 PZ |
4988 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4989 | { | |
4990 | struct drm_device *dev = crtc->dev; | |
4991 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4992 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4993 | struct intel_encoder *encoder; | |
4994 | int pipe = intel_crtc->pipe; | |
4f771f10 | 4995 | |
83d65738 | 4996 | WARN_ON(!crtc->state->enable); |
4f771f10 PZ |
4997 | |
4998 | if (intel_crtc->active) | |
4999 | return; | |
5000 | ||
df8ad70c DV |
5001 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
5002 | intel_enable_shared_dpll(intel_crtc); | |
5003 | ||
6e3c9717 | 5004 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 5005 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 DV |
5006 | |
5007 | intel_set_pipe_timings(intel_crtc); | |
5008 | ||
6e3c9717 ACO |
5009 | if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) { |
5010 | I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder), | |
5011 | intel_crtc->config->pixel_multiplier - 1); | |
ebb69c95 CT |
5012 | } |
5013 | ||
6e3c9717 | 5014 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 5015 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5016 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
5017 | } |
5018 | ||
5019 | haswell_set_pipeconf(crtc); | |
5020 | ||
5021 | intel_set_pipe_csc(crtc); | |
5022 | ||
4f771f10 | 5023 | intel_crtc->active = true; |
8664281b | 5024 | |
a72e4c9f | 5025 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4f771f10 PZ |
5026 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5027 | if (encoder->pre_enable) | |
5028 | encoder->pre_enable(encoder); | |
5029 | ||
6e3c9717 | 5030 | if (intel_crtc->config->has_pch_encoder) { |
a72e4c9f DV |
5031 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5032 | true); | |
4fe9467d ID |
5033 | dev_priv->display.fdi_link_train(crtc); |
5034 | } | |
5035 | ||
1f544388 | 5036 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 5037 | |
ff6d9f55 | 5038 | if (INTEL_INFO(dev)->gen == 9) |
a1b2278e | 5039 | skylake_pfit_update(intel_crtc, 1); |
ff6d9f55 | 5040 | else if (INTEL_INFO(dev)->gen < 9) |
bd2e244f | 5041 | ironlake_pfit_enable(intel_crtc); |
ff6d9f55 JB |
5042 | else |
5043 | MISSING_CASE(INTEL_INFO(dev)->gen); | |
4f771f10 PZ |
5044 | |
5045 | /* | |
5046 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5047 | * clocks enabled | |
5048 | */ | |
5049 | intel_crtc_load_lut(crtc); | |
5050 | ||
1f544388 | 5051 | intel_ddi_set_pipe_settings(crtc); |
8228c251 | 5052 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 5053 | |
f37fcc2a | 5054 | intel_update_watermarks(crtc); |
e1fdc473 | 5055 | intel_enable_pipe(intel_crtc); |
42db64ef | 5056 | |
6e3c9717 | 5057 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 5058 | lpt_pch_enable(crtc); |
4f771f10 | 5059 | |
6e3c9717 | 5060 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
5061 | intel_ddi_set_vc_payload_alloc(crtc, true); |
5062 | ||
f9b61ff6 DV |
5063 | assert_vblank_disabled(crtc); |
5064 | drm_crtc_vblank_on(crtc); | |
5065 | ||
8807e55b | 5066 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 5067 | encoder->enable(encoder); |
8807e55b JN |
5068 | intel_opregion_notify_encoder(encoder, true); |
5069 | } | |
4f771f10 | 5070 | |
e4916946 PZ |
5071 | /* If we change the relative order between pipe/planes enabling, we need |
5072 | * to change the workaround. */ | |
5073 | haswell_mode_set_planes_workaround(intel_crtc); | |
4f771f10 PZ |
5074 | } |
5075 | ||
3f8dce3a DV |
5076 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
5077 | { | |
5078 | struct drm_device *dev = crtc->base.dev; | |
5079 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5080 | int pipe = crtc->pipe; | |
5081 | ||
5082 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
5083 | * it's in use. The hw state code will make sure we get this right. */ | |
6e3c9717 | 5084 | if (crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
5085 | I915_WRITE(PF_CTL(pipe), 0); |
5086 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
5087 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
5088 | } | |
5089 | } | |
5090 | ||
6be4a607 JB |
5091 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
5092 | { | |
5093 | struct drm_device *dev = crtc->dev; | |
5094 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5095 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 5096 | struct intel_encoder *encoder; |
6be4a607 | 5097 | int pipe = intel_crtc->pipe; |
5eddb70b | 5098 | u32 reg, temp; |
b52eb4dc | 5099 | |
f7abfe8b CW |
5100 | if (!intel_crtc->active) |
5101 | return; | |
5102 | ||
ea9d758d DV |
5103 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5104 | encoder->disable(encoder); | |
5105 | ||
f9b61ff6 DV |
5106 | drm_crtc_vblank_off(crtc); |
5107 | assert_vblank_disabled(crtc); | |
5108 | ||
6e3c9717 | 5109 | if (intel_crtc->config->has_pch_encoder) |
a72e4c9f | 5110 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
d925c59a | 5111 | |
575f7ab7 | 5112 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5113 | |
3f8dce3a | 5114 | ironlake_pfit_disable(intel_crtc); |
2c07245f | 5115 | |
5a74f70a VS |
5116 | if (intel_crtc->config->has_pch_encoder) |
5117 | ironlake_fdi_disable(crtc); | |
5118 | ||
bf49ec8c DV |
5119 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5120 | if (encoder->post_disable) | |
5121 | encoder->post_disable(encoder); | |
2c07245f | 5122 | |
6e3c9717 | 5123 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5124 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5125 | |
d925c59a DV |
5126 | if (HAS_PCH_CPT(dev)) { |
5127 | /* disable TRANS_DP_CTL */ | |
5128 | reg = TRANS_DP_CTL(pipe); | |
5129 | temp = I915_READ(reg); | |
5130 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5131 | TRANS_DP_PORT_SEL_MASK); | |
5132 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5133 | I915_WRITE(reg, temp); | |
5134 | ||
5135 | /* disable DPLL_SEL */ | |
5136 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5137 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5138 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5139 | } |
e3421a18 | 5140 | |
d925c59a | 5141 | /* disable PCH DPLL */ |
e72f9fbf | 5142 | intel_disable_shared_dpll(intel_crtc); |
8db9d77b | 5143 | |
d925c59a DV |
5144 | ironlake_fdi_pll_disable(intel_crtc); |
5145 | } | |
6b383a7f | 5146 | |
f7abfe8b | 5147 | intel_crtc->active = false; |
46ba614c | 5148 | intel_update_watermarks(crtc); |
d1ebd816 BW |
5149 | |
5150 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 5151 | intel_fbc_update(dev); |
d1ebd816 | 5152 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 5153 | } |
1b3c7a47 | 5154 | |
4f771f10 | 5155 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 5156 | { |
4f771f10 PZ |
5157 | struct drm_device *dev = crtc->dev; |
5158 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 5159 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 5160 | struct intel_encoder *encoder; |
6e3c9717 | 5161 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5162 | |
4f771f10 PZ |
5163 | if (!intel_crtc->active) |
5164 | return; | |
5165 | ||
8807e55b JN |
5166 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5167 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 5168 | encoder->disable(encoder); |
8807e55b | 5169 | } |
4f771f10 | 5170 | |
f9b61ff6 DV |
5171 | drm_crtc_vblank_off(crtc); |
5172 | assert_vblank_disabled(crtc); | |
5173 | ||
6e3c9717 | 5174 | if (intel_crtc->config->has_pch_encoder) |
a72e4c9f DV |
5175 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5176 | false); | |
575f7ab7 | 5177 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5178 | |
6e3c9717 | 5179 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
5180 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5181 | ||
ad80a810 | 5182 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5183 | |
ff6d9f55 | 5184 | if (INTEL_INFO(dev)->gen == 9) |
a1b2278e | 5185 | skylake_pfit_update(intel_crtc, 0); |
ff6d9f55 | 5186 | else if (INTEL_INFO(dev)->gen < 9) |
bd2e244f | 5187 | ironlake_pfit_disable(intel_crtc); |
ff6d9f55 JB |
5188 | else |
5189 | MISSING_CASE(INTEL_INFO(dev)->gen); | |
4f771f10 | 5190 | |
1f544388 | 5191 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 5192 | |
6e3c9717 | 5193 | if (intel_crtc->config->has_pch_encoder) { |
ab4d966c | 5194 | lpt_disable_pch_transcoder(dev_priv); |
1ad960f2 | 5195 | intel_ddi_fdi_disable(crtc); |
83616634 | 5196 | } |
4f771f10 | 5197 | |
97b040aa ID |
5198 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5199 | if (encoder->post_disable) | |
5200 | encoder->post_disable(encoder); | |
5201 | ||
4f771f10 | 5202 | intel_crtc->active = false; |
46ba614c | 5203 | intel_update_watermarks(crtc); |
4f771f10 PZ |
5204 | |
5205 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 5206 | intel_fbc_update(dev); |
4f771f10 | 5207 | mutex_unlock(&dev->struct_mutex); |
df8ad70c DV |
5208 | |
5209 | if (intel_crtc_to_shared_dpll(intel_crtc)) | |
5210 | intel_disable_shared_dpll(intel_crtc); | |
4f771f10 PZ |
5211 | } |
5212 | ||
ee7b9f93 JB |
5213 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
5214 | { | |
5215 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e72f9fbf | 5216 | intel_put_shared_dpll(intel_crtc); |
ee7b9f93 JB |
5217 | } |
5218 | ||
6441ab5f | 5219 | |
2dd24552 JB |
5220 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5221 | { | |
5222 | struct drm_device *dev = crtc->base.dev; | |
5223 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 5224 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5225 | |
681a8504 | 5226 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5227 | return; |
5228 | ||
2dd24552 | 5229 | /* |
c0b03411 DV |
5230 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5231 | * according to register description and PRM. | |
2dd24552 | 5232 | */ |
c0b03411 DV |
5233 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5234 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5235 | |
b074cec8 JB |
5236 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5237 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5238 | |
5239 | /* Border color in case we don't scale up to the full screen. Black by | |
5240 | * default, change to something else for debugging. */ | |
5241 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5242 | } |
5243 | ||
d05410f9 DA |
5244 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5245 | { | |
5246 | switch (port) { | |
5247 | case PORT_A: | |
5248 | return POWER_DOMAIN_PORT_DDI_A_4_LANES; | |
5249 | case PORT_B: | |
5250 | return POWER_DOMAIN_PORT_DDI_B_4_LANES; | |
5251 | case PORT_C: | |
5252 | return POWER_DOMAIN_PORT_DDI_C_4_LANES; | |
5253 | case PORT_D: | |
5254 | return POWER_DOMAIN_PORT_DDI_D_4_LANES; | |
5255 | default: | |
5256 | WARN_ON_ONCE(1); | |
5257 | return POWER_DOMAIN_PORT_OTHER; | |
5258 | } | |
5259 | } | |
5260 | ||
77d22dca ID |
5261 | #define for_each_power_domain(domain, mask) \ |
5262 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
5263 | if ((1 << (domain)) & (mask)) | |
5264 | ||
319be8ae ID |
5265 | enum intel_display_power_domain |
5266 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5267 | { | |
5268 | struct drm_device *dev = intel_encoder->base.dev; | |
5269 | struct intel_digital_port *intel_dig_port; | |
5270 | ||
5271 | switch (intel_encoder->type) { | |
5272 | case INTEL_OUTPUT_UNKNOWN: | |
5273 | /* Only DDI platforms should ever use this output type */ | |
5274 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
5275 | case INTEL_OUTPUT_DISPLAYPORT: | |
5276 | case INTEL_OUTPUT_HDMI: | |
5277 | case INTEL_OUTPUT_EDP: | |
5278 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 5279 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
5280 | case INTEL_OUTPUT_DP_MST: |
5281 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5282 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
5283 | case INTEL_OUTPUT_ANALOG: |
5284 | return POWER_DOMAIN_PORT_CRT; | |
5285 | case INTEL_OUTPUT_DSI: | |
5286 | return POWER_DOMAIN_PORT_DSI; | |
5287 | default: | |
5288 | return POWER_DOMAIN_PORT_OTHER; | |
5289 | } | |
5290 | } | |
5291 | ||
5292 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) | |
77d22dca | 5293 | { |
319be8ae ID |
5294 | struct drm_device *dev = crtc->dev; |
5295 | struct intel_encoder *intel_encoder; | |
5296 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5297 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca ID |
5298 | unsigned long mask; |
5299 | enum transcoder transcoder; | |
5300 | ||
5301 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); | |
5302 | ||
5303 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); | |
5304 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
6e3c9717 ACO |
5305 | if (intel_crtc->config->pch_pfit.enabled || |
5306 | intel_crtc->config->pch_pfit.force_thru) | |
77d22dca ID |
5307 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5308 | ||
319be8ae ID |
5309 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
5310 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); | |
5311 | ||
77d22dca ID |
5312 | return mask; |
5313 | } | |
5314 | ||
679dacd4 | 5315 | static void modeset_update_crtc_power_domains(struct drm_atomic_state *state) |
77d22dca | 5316 | { |
679dacd4 | 5317 | struct drm_device *dev = state->dev; |
77d22dca ID |
5318 | struct drm_i915_private *dev_priv = dev->dev_private; |
5319 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; | |
5320 | struct intel_crtc *crtc; | |
5321 | ||
5322 | /* | |
5323 | * First get all needed power domains, then put all unneeded, to avoid | |
5324 | * any unnecessary toggling of the power wells. | |
5325 | */ | |
d3fcc808 | 5326 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
5327 | enum intel_display_power_domain domain; |
5328 | ||
83d65738 | 5329 | if (!crtc->base.state->enable) |
77d22dca ID |
5330 | continue; |
5331 | ||
319be8ae | 5332 | pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base); |
77d22dca ID |
5333 | |
5334 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) | |
5335 | intel_display_power_get(dev_priv, domain); | |
5336 | } | |
5337 | ||
50f6e502 | 5338 | if (dev_priv->display.modeset_global_resources) |
679dacd4 | 5339 | dev_priv->display.modeset_global_resources(state); |
50f6e502 | 5340 | |
d3fcc808 | 5341 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
5342 | enum intel_display_power_domain domain; |
5343 | ||
5344 | for_each_power_domain(domain, crtc->enabled_power_domains) | |
5345 | intel_display_power_put(dev_priv, domain); | |
5346 | ||
5347 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; | |
5348 | } | |
5349 | ||
5350 | intel_display_set_init_power(dev_priv, false); | |
5351 | } | |
5352 | ||
560a7ae4 DL |
5353 | static void intel_update_max_cdclk(struct drm_device *dev) |
5354 | { | |
5355 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5356 | ||
5357 | if (IS_SKYLAKE(dev)) { | |
5358 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; | |
5359 | ||
5360 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) | |
5361 | dev_priv->max_cdclk_freq = 675000; | |
5362 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) | |
5363 | dev_priv->max_cdclk_freq = 540000; | |
5364 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) | |
5365 | dev_priv->max_cdclk_freq = 450000; | |
5366 | else | |
5367 | dev_priv->max_cdclk_freq = 337500; | |
5368 | } else if (IS_BROADWELL(dev)) { | |
5369 | /* | |
5370 | * FIXME with extra cooling we can allow | |
5371 | * 540 MHz for ULX and 675 Mhz for ULT. | |
5372 | * How can we know if extra cooling is | |
5373 | * available? PCI ID, VTB, something else? | |
5374 | */ | |
5375 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
5376 | dev_priv->max_cdclk_freq = 450000; | |
5377 | else if (IS_BDW_ULX(dev)) | |
5378 | dev_priv->max_cdclk_freq = 450000; | |
5379 | else if (IS_BDW_ULT(dev)) | |
5380 | dev_priv->max_cdclk_freq = 540000; | |
5381 | else | |
5382 | dev_priv->max_cdclk_freq = 675000; | |
5383 | } else if (IS_VALLEYVIEW(dev)) { | |
5384 | dev_priv->max_cdclk_freq = 400000; | |
5385 | } else { | |
5386 | /* otherwise assume cdclk is fixed */ | |
5387 | dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; | |
5388 | } | |
5389 | ||
5390 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", | |
5391 | dev_priv->max_cdclk_freq); | |
5392 | } | |
5393 | ||
5394 | static void intel_update_cdclk(struct drm_device *dev) | |
5395 | { | |
5396 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5397 | ||
5398 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
5399 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", | |
5400 | dev_priv->cdclk_freq); | |
5401 | ||
5402 | /* | |
5403 | * Program the gmbus_freq based on the cdclk frequency. | |
5404 | * BSpec erroneously claims we should aim for 4MHz, but | |
5405 | * in fact 1MHz is the correct frequency. | |
5406 | */ | |
5407 | if (IS_VALLEYVIEW(dev)) { | |
5408 | /* | |
5409 | * Program the gmbus_freq based on the cdclk frequency. | |
5410 | * BSpec erroneously claims we should aim for 4MHz, but | |
5411 | * in fact 1MHz is the correct frequency. | |
5412 | */ | |
5413 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); | |
5414 | } | |
5415 | ||
5416 | if (dev_priv->max_cdclk_freq == 0) | |
5417 | intel_update_max_cdclk(dev); | |
5418 | } | |
5419 | ||
70d0c574 | 5420 | static void broxton_set_cdclk(struct drm_device *dev, int frequency) |
f8437dd1 VK |
5421 | { |
5422 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5423 | uint32_t divider; | |
5424 | uint32_t ratio; | |
5425 | uint32_t current_freq; | |
5426 | int ret; | |
5427 | ||
5428 | /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */ | |
5429 | switch (frequency) { | |
5430 | case 144000: | |
5431 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; | |
5432 | ratio = BXT_DE_PLL_RATIO(60); | |
5433 | break; | |
5434 | case 288000: | |
5435 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; | |
5436 | ratio = BXT_DE_PLL_RATIO(60); | |
5437 | break; | |
5438 | case 384000: | |
5439 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; | |
5440 | ratio = BXT_DE_PLL_RATIO(60); | |
5441 | break; | |
5442 | case 576000: | |
5443 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5444 | ratio = BXT_DE_PLL_RATIO(60); | |
5445 | break; | |
5446 | case 624000: | |
5447 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5448 | ratio = BXT_DE_PLL_RATIO(65); | |
5449 | break; | |
5450 | case 19200: | |
5451 | /* | |
5452 | * Bypass frequency with DE PLL disabled. Init ratio, divider | |
5453 | * to suppress GCC warning. | |
5454 | */ | |
5455 | ratio = 0; | |
5456 | divider = 0; | |
5457 | break; | |
5458 | default: | |
5459 | DRM_ERROR("unsupported CDCLK freq %d", frequency); | |
5460 | ||
5461 | return; | |
5462 | } | |
5463 | ||
5464 | mutex_lock(&dev_priv->rps.hw_lock); | |
5465 | /* Inform power controller of upcoming frequency change */ | |
5466 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5467 | 0x80000000); | |
5468 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5469 | ||
5470 | if (ret) { | |
5471 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
5472 | ret, frequency); | |
5473 | return; | |
5474 | } | |
5475 | ||
5476 | current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK; | |
5477 | /* convert from .1 fixpoint MHz with -1MHz offset to kHz */ | |
5478 | current_freq = current_freq * 500 + 1000; | |
5479 | ||
5480 | /* | |
5481 | * DE PLL has to be disabled when | |
5482 | * - setting to 19.2MHz (bypass, PLL isn't used) | |
5483 | * - before setting to 624MHz (PLL needs toggling) | |
5484 | * - before setting to any frequency from 624MHz (PLL needs toggling) | |
5485 | */ | |
5486 | if (frequency == 19200 || frequency == 624000 || | |
5487 | current_freq == 624000) { | |
5488 | I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE); | |
5489 | /* Timeout 200us */ | |
5490 | if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK), | |
5491 | 1)) | |
5492 | DRM_ERROR("timout waiting for DE PLL unlock\n"); | |
5493 | } | |
5494 | ||
5495 | if (frequency != 19200) { | |
5496 | uint32_t val; | |
5497 | ||
5498 | val = I915_READ(BXT_DE_PLL_CTL); | |
5499 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5500 | val |= ratio; | |
5501 | I915_WRITE(BXT_DE_PLL_CTL, val); | |
5502 | ||
5503 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5504 | /* Timeout 200us */ | |
5505 | if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1)) | |
5506 | DRM_ERROR("timeout waiting for DE PLL lock\n"); | |
5507 | ||
5508 | val = I915_READ(CDCLK_CTL); | |
5509 | val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK; | |
5510 | val |= divider; | |
5511 | /* | |
5512 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5513 | * enable otherwise. | |
5514 | */ | |
5515 | val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5516 | if (frequency >= 500000) | |
5517 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5518 | ||
5519 | val &= ~CDCLK_FREQ_DECIMAL_MASK; | |
5520 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ | |
5521 | val |= (frequency - 1000) / 500; | |
5522 | I915_WRITE(CDCLK_CTL, val); | |
5523 | } | |
5524 | ||
5525 | mutex_lock(&dev_priv->rps.hw_lock); | |
5526 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5527 | DIV_ROUND_UP(frequency, 25000)); | |
5528 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5529 | ||
5530 | if (ret) { | |
5531 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
5532 | ret, frequency); | |
5533 | return; | |
5534 | } | |
5535 | ||
a47871bd | 5536 | intel_update_cdclk(dev); |
f8437dd1 VK |
5537 | } |
5538 | ||
5539 | void broxton_init_cdclk(struct drm_device *dev) | |
5540 | { | |
5541 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5542 | uint32_t val; | |
5543 | ||
5544 | /* | |
5545 | * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT | |
5546 | * or else the reset will hang because there is no PCH to respond. | |
5547 | * Move the handshake programming to initialization sequence. | |
5548 | * Previously was left up to BIOS. | |
5549 | */ | |
5550 | val = I915_READ(HSW_NDE_RSTWRN_OPT); | |
5551 | val &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
5552 | I915_WRITE(HSW_NDE_RSTWRN_OPT, val); | |
5553 | ||
5554 | /* Enable PG1 for cdclk */ | |
5555 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); | |
5556 | ||
5557 | /* check if cd clock is enabled */ | |
5558 | if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) { | |
5559 | DRM_DEBUG_KMS("Display already initialized\n"); | |
5560 | return; | |
5561 | } | |
5562 | ||
5563 | /* | |
5564 | * FIXME: | |
5565 | * - The initial CDCLK needs to be read from VBT. | |
5566 | * Need to make this change after VBT has changes for BXT. | |
5567 | * - check if setting the max (or any) cdclk freq is really necessary | |
5568 | * here, it belongs to modeset time | |
5569 | */ | |
5570 | broxton_set_cdclk(dev, 624000); | |
5571 | ||
5572 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
22e02c0b VS |
5573 | POSTING_READ(DBUF_CTL); |
5574 | ||
f8437dd1 VK |
5575 | udelay(10); |
5576 | ||
5577 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5578 | DRM_ERROR("DBuf power enable timeout!\n"); | |
5579 | } | |
5580 | ||
5581 | void broxton_uninit_cdclk(struct drm_device *dev) | |
5582 | { | |
5583 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5584 | ||
5585 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
22e02c0b VS |
5586 | POSTING_READ(DBUF_CTL); |
5587 | ||
f8437dd1 VK |
5588 | udelay(10); |
5589 | ||
5590 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5591 | DRM_ERROR("DBuf power disable timeout!\n"); | |
5592 | ||
5593 | /* Set minimum (bypass) frequency, in effect turning off the DE PLL */ | |
5594 | broxton_set_cdclk(dev, 19200); | |
5595 | ||
5596 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
5597 | } | |
5598 | ||
5d96d8af DL |
5599 | static const struct skl_cdclk_entry { |
5600 | unsigned int freq; | |
5601 | unsigned int vco; | |
5602 | } skl_cdclk_frequencies[] = { | |
5603 | { .freq = 308570, .vco = 8640 }, | |
5604 | { .freq = 337500, .vco = 8100 }, | |
5605 | { .freq = 432000, .vco = 8640 }, | |
5606 | { .freq = 450000, .vco = 8100 }, | |
5607 | { .freq = 540000, .vco = 8100 }, | |
5608 | { .freq = 617140, .vco = 8640 }, | |
5609 | { .freq = 675000, .vco = 8100 }, | |
5610 | }; | |
5611 | ||
5612 | static unsigned int skl_cdclk_decimal(unsigned int freq) | |
5613 | { | |
5614 | return (freq - 1000) / 500; | |
5615 | } | |
5616 | ||
5617 | static unsigned int skl_cdclk_get_vco(unsigned int freq) | |
5618 | { | |
5619 | unsigned int i; | |
5620 | ||
5621 | for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) { | |
5622 | const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i]; | |
5623 | ||
5624 | if (e->freq == freq) | |
5625 | return e->vco; | |
5626 | } | |
5627 | ||
5628 | return 8100; | |
5629 | } | |
5630 | ||
5631 | static void | |
5632 | skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco) | |
5633 | { | |
5634 | unsigned int min_freq; | |
5635 | u32 val; | |
5636 | ||
5637 | /* select the minimum CDCLK before enabling DPLL 0 */ | |
5638 | val = I915_READ(CDCLK_CTL); | |
5639 | val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK; | |
5640 | val |= CDCLK_FREQ_337_308; | |
5641 | ||
5642 | if (required_vco == 8640) | |
5643 | min_freq = 308570; | |
5644 | else | |
5645 | min_freq = 337500; | |
5646 | ||
5647 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq); | |
5648 | ||
5649 | I915_WRITE(CDCLK_CTL, val); | |
5650 | POSTING_READ(CDCLK_CTL); | |
5651 | ||
5652 | /* | |
5653 | * We always enable DPLL0 with the lowest link rate possible, but still | |
5654 | * taking into account the VCO required to operate the eDP panel at the | |
5655 | * desired frequency. The usual DP link rates operate with a VCO of | |
5656 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. | |
5657 | * The modeset code is responsible for the selection of the exact link | |
5658 | * rate later on, with the constraint of choosing a frequency that | |
5659 | * works with required_vco. | |
5660 | */ | |
5661 | val = I915_READ(DPLL_CTRL1); | |
5662 | ||
5663 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
5664 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
5665 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
5666 | if (required_vco == 8640) | |
5667 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, | |
5668 | SKL_DPLL0); | |
5669 | else | |
5670 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, | |
5671 | SKL_DPLL0); | |
5672 | ||
5673 | I915_WRITE(DPLL_CTRL1, val); | |
5674 | POSTING_READ(DPLL_CTRL1); | |
5675 | ||
5676 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); | |
5677 | ||
5678 | if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5)) | |
5679 | DRM_ERROR("DPLL0 not locked\n"); | |
5680 | } | |
5681 | ||
5682 | static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) | |
5683 | { | |
5684 | int ret; | |
5685 | u32 val; | |
5686 | ||
5687 | /* inform PCU we want to change CDCLK */ | |
5688 | val = SKL_CDCLK_PREPARE_FOR_CHANGE; | |
5689 | mutex_lock(&dev_priv->rps.hw_lock); | |
5690 | ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); | |
5691 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5692 | ||
5693 | return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE); | |
5694 | } | |
5695 | ||
5696 | static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) | |
5697 | { | |
5698 | unsigned int i; | |
5699 | ||
5700 | for (i = 0; i < 15; i++) { | |
5701 | if (skl_cdclk_pcu_ready(dev_priv)) | |
5702 | return true; | |
5703 | udelay(10); | |
5704 | } | |
5705 | ||
5706 | return false; | |
5707 | } | |
5708 | ||
5709 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq) | |
5710 | { | |
560a7ae4 | 5711 | struct drm_device *dev = dev_priv->dev; |
5d96d8af DL |
5712 | u32 freq_select, pcu_ack; |
5713 | ||
5714 | DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq); | |
5715 | ||
5716 | if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { | |
5717 | DRM_ERROR("failed to inform PCU about cdclk change\n"); | |
5718 | return; | |
5719 | } | |
5720 | ||
5721 | /* set CDCLK_CTL */ | |
5722 | switch(freq) { | |
5723 | case 450000: | |
5724 | case 432000: | |
5725 | freq_select = CDCLK_FREQ_450_432; | |
5726 | pcu_ack = 1; | |
5727 | break; | |
5728 | case 540000: | |
5729 | freq_select = CDCLK_FREQ_540; | |
5730 | pcu_ack = 2; | |
5731 | break; | |
5732 | case 308570: | |
5733 | case 337500: | |
5734 | default: | |
5735 | freq_select = CDCLK_FREQ_337_308; | |
5736 | pcu_ack = 0; | |
5737 | break; | |
5738 | case 617140: | |
5739 | case 675000: | |
5740 | freq_select = CDCLK_FREQ_675_617; | |
5741 | pcu_ack = 3; | |
5742 | break; | |
5743 | } | |
5744 | ||
5745 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq)); | |
5746 | POSTING_READ(CDCLK_CTL); | |
5747 | ||
5748 | /* inform PCU of the change */ | |
5749 | mutex_lock(&dev_priv->rps.hw_lock); | |
5750 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); | |
5751 | mutex_unlock(&dev_priv->rps.hw_lock); | |
560a7ae4 DL |
5752 | |
5753 | intel_update_cdclk(dev); | |
5d96d8af DL |
5754 | } |
5755 | ||
5756 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) | |
5757 | { | |
5758 | /* disable DBUF power */ | |
5759 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
5760 | POSTING_READ(DBUF_CTL); | |
5761 | ||
5762 | udelay(10); | |
5763 | ||
5764 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5765 | DRM_ERROR("DBuf power disable timeout\n"); | |
5766 | ||
5767 | /* disable DPLL0 */ | |
5768 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); | |
5769 | if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) | |
5770 | DRM_ERROR("Couldn't disable DPLL0\n"); | |
5771 | ||
5772 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
5773 | } | |
5774 | ||
5775 | void skl_init_cdclk(struct drm_i915_private *dev_priv) | |
5776 | { | |
5777 | u32 val; | |
5778 | unsigned int required_vco; | |
5779 | ||
5780 | /* enable PCH reset handshake */ | |
5781 | val = I915_READ(HSW_NDE_RSTWRN_OPT); | |
5782 | I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE); | |
5783 | ||
5784 | /* enable PG1 and Misc I/O */ | |
5785 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); | |
5786 | ||
5787 | /* DPLL0 already enabed !? */ | |
5788 | if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) { | |
5789 | DRM_DEBUG_DRIVER("DPLL0 already running\n"); | |
5790 | return; | |
5791 | } | |
5792 | ||
5793 | /* enable DPLL0 */ | |
5794 | required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk); | |
5795 | skl_dpll0_enable(dev_priv, required_vco); | |
5796 | ||
5797 | /* set CDCLK to the frequency the BIOS chose */ | |
5798 | skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk); | |
5799 | ||
5800 | /* enable DBUF power */ | |
5801 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
5802 | POSTING_READ(DBUF_CTL); | |
5803 | ||
5804 | udelay(10); | |
5805 | ||
5806 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5807 | DRM_ERROR("DBuf power enable timeout\n"); | |
5808 | } | |
5809 | ||
dfcab17e | 5810 | /* returns HPLL frequency in kHz */ |
f8bf63fd | 5811 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) |
30a970c6 | 5812 | { |
586f49dc | 5813 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
30a970c6 | 5814 | |
586f49dc | 5815 | /* Obtain SKU information */ |
a580516d | 5816 | mutex_lock(&dev_priv->sb_lock); |
586f49dc JB |
5817 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & |
5818 | CCK_FUSE_HPLL_FREQ_MASK; | |
a580516d | 5819 | mutex_unlock(&dev_priv->sb_lock); |
30a970c6 | 5820 | |
dfcab17e | 5821 | return vco_freq[hpll_freq] * 1000; |
30a970c6 JB |
5822 | } |
5823 | ||
5824 | /* Adjust CDclk dividers to allow high res or save power if possible */ | |
5825 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
5826 | { | |
5827 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5828 | u32 val, cmd; | |
5829 | ||
164dfd28 VK |
5830 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5831 | != dev_priv->cdclk_freq); | |
d60c4473 | 5832 | |
dfcab17e | 5833 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 5834 | cmd = 2; |
dfcab17e | 5835 | else if (cdclk == 266667) |
30a970c6 JB |
5836 | cmd = 1; |
5837 | else | |
5838 | cmd = 0; | |
5839 | ||
5840 | mutex_lock(&dev_priv->rps.hw_lock); | |
5841 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5842 | val &= ~DSPFREQGUAR_MASK; | |
5843 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
5844 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5845 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5846 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
5847 | 50)) { | |
5848 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5849 | } | |
5850 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5851 | ||
54433e91 VS |
5852 | mutex_lock(&dev_priv->sb_lock); |
5853 | ||
dfcab17e | 5854 | if (cdclk == 400000) { |
6bcda4f0 | 5855 | u32 divider; |
30a970c6 | 5856 | |
6bcda4f0 | 5857 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 | 5858 | |
30a970c6 JB |
5859 | /* adjust cdclk divider */ |
5860 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
9cf33db5 | 5861 | val &= ~DISPLAY_FREQUENCY_VALUES; |
30a970c6 JB |
5862 | val |= divider; |
5863 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
5864 | |
5865 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
5866 | DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
5867 | 50)) | |
5868 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
5869 | } |
5870 | ||
30a970c6 JB |
5871 | /* adjust self-refresh exit latency value */ |
5872 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
5873 | val &= ~0x7f; | |
5874 | ||
5875 | /* | |
5876 | * For high bandwidth configs, we set a higher latency in the bunit | |
5877 | * so that the core display fetch happens in time to avoid underruns. | |
5878 | */ | |
dfcab17e | 5879 | if (cdclk == 400000) |
30a970c6 JB |
5880 | val |= 4500 / 250; /* 4.5 usec */ |
5881 | else | |
5882 | val |= 3000 / 250; /* 3.0 usec */ | |
5883 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
54433e91 | 5884 | |
a580516d | 5885 | mutex_unlock(&dev_priv->sb_lock); |
30a970c6 | 5886 | |
b6283055 | 5887 | intel_update_cdclk(dev); |
30a970c6 JB |
5888 | } |
5889 | ||
383c5a6a VS |
5890 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
5891 | { | |
5892 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5893 | u32 val, cmd; | |
5894 | ||
164dfd28 VK |
5895 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5896 | != dev_priv->cdclk_freq); | |
383c5a6a VS |
5897 | |
5898 | switch (cdclk) { | |
383c5a6a VS |
5899 | case 333333: |
5900 | case 320000: | |
383c5a6a | 5901 | case 266667: |
383c5a6a | 5902 | case 200000: |
383c5a6a VS |
5903 | break; |
5904 | default: | |
5f77eeb0 | 5905 | MISSING_CASE(cdclk); |
383c5a6a VS |
5906 | return; |
5907 | } | |
5908 | ||
9d0d3fda VS |
5909 | /* |
5910 | * Specs are full of misinformation, but testing on actual | |
5911 | * hardware has shown that we just need to write the desired | |
5912 | * CCK divider into the Punit register. | |
5913 | */ | |
5914 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
5915 | ||
383c5a6a VS |
5916 | mutex_lock(&dev_priv->rps.hw_lock); |
5917 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5918 | val &= ~DSPFREQGUAR_MASK_CHV; | |
5919 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
5920 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5921 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5922 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
5923 | 50)) { | |
5924 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5925 | } | |
5926 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5927 | ||
b6283055 | 5928 | intel_update_cdclk(dev); |
383c5a6a VS |
5929 | } |
5930 | ||
30a970c6 JB |
5931 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
5932 | int max_pixclk) | |
5933 | { | |
6bcda4f0 | 5934 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 5935 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 5936 | |
30a970c6 JB |
5937 | /* |
5938 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
5939 | * 200MHz | |
5940 | * 267MHz | |
29dc7ef3 | 5941 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
5942 | * 400MHz (VLV only) |
5943 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
5944 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
5945 | * |
5946 | * We seem to get an unstable or solid color picture at 200MHz. | |
5947 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
5948 | * are off. | |
30a970c6 | 5949 | */ |
6cca3195 VS |
5950 | if (!IS_CHERRYVIEW(dev_priv) && |
5951 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 5952 | return 400000; |
6cca3195 | 5953 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 5954 | return freq_320; |
e37c67a1 | 5955 | else if (max_pixclk > 0) |
dfcab17e | 5956 | return 266667; |
e37c67a1 VS |
5957 | else |
5958 | return 200000; | |
30a970c6 JB |
5959 | } |
5960 | ||
f8437dd1 VK |
5961 | static int broxton_calc_cdclk(struct drm_i915_private *dev_priv, |
5962 | int max_pixclk) | |
5963 | { | |
5964 | /* | |
5965 | * FIXME: | |
5966 | * - remove the guardband, it's not needed on BXT | |
5967 | * - set 19.2MHz bypass frequency if there are no active pipes | |
5968 | */ | |
5969 | if (max_pixclk > 576000*9/10) | |
5970 | return 624000; | |
5971 | else if (max_pixclk > 384000*9/10) | |
5972 | return 576000; | |
5973 | else if (max_pixclk > 288000*9/10) | |
5974 | return 384000; | |
5975 | else if (max_pixclk > 144000*9/10) | |
5976 | return 288000; | |
5977 | else | |
5978 | return 144000; | |
5979 | } | |
5980 | ||
a821fc46 ACO |
5981 | /* Compute the max pixel clock for new configuration. Uses atomic state if |
5982 | * that's non-NULL, look at current state otherwise. */ | |
5983 | static int intel_mode_max_pixclk(struct drm_device *dev, | |
5984 | struct drm_atomic_state *state) | |
30a970c6 | 5985 | { |
30a970c6 | 5986 | struct intel_crtc *intel_crtc; |
304603f4 | 5987 | struct intel_crtc_state *crtc_state; |
30a970c6 JB |
5988 | int max_pixclk = 0; |
5989 | ||
d3fcc808 | 5990 | for_each_intel_crtc(dev, intel_crtc) { |
a821fc46 ACO |
5991 | if (state) |
5992 | crtc_state = | |
5993 | intel_atomic_get_crtc_state(state, intel_crtc); | |
5994 | else | |
5995 | crtc_state = intel_crtc->config; | |
304603f4 ACO |
5996 | if (IS_ERR(crtc_state)) |
5997 | return PTR_ERR(crtc_state); | |
5998 | ||
5999 | if (!crtc_state->base.enable) | |
6000 | continue; | |
6001 | ||
6002 | max_pixclk = max(max_pixclk, | |
6003 | crtc_state->base.adjusted_mode.crtc_clock); | |
30a970c6 JB |
6004 | } |
6005 | ||
6006 | return max_pixclk; | |
6007 | } | |
6008 | ||
0a9ab303 | 6009 | static int valleyview_modeset_global_pipes(struct drm_atomic_state *state) |
30a970c6 | 6010 | { |
304603f4 | 6011 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
0a9ab303 ACO |
6012 | struct drm_crtc *crtc; |
6013 | struct drm_crtc_state *crtc_state; | |
a821fc46 | 6014 | int max_pixclk = intel_mode_max_pixclk(state->dev, state); |
0a9ab303 | 6015 | int cdclk, i; |
30a970c6 | 6016 | |
304603f4 ACO |
6017 | if (max_pixclk < 0) |
6018 | return max_pixclk; | |
30a970c6 | 6019 | |
f8437dd1 VK |
6020 | if (IS_VALLEYVIEW(dev_priv)) |
6021 | cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); | |
6022 | else | |
6023 | cdclk = broxton_calc_cdclk(dev_priv, max_pixclk); | |
6024 | ||
6025 | if (cdclk == dev_priv->cdclk_freq) | |
304603f4 | 6026 | return 0; |
30a970c6 | 6027 | |
0a9ab303 ACO |
6028 | /* add all active pipes to the state */ |
6029 | for_each_crtc(state->dev, crtc) { | |
6030 | if (!crtc->state->enable) | |
6031 | continue; | |
6032 | ||
6033 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
6034 | if (IS_ERR(crtc_state)) | |
6035 | return PTR_ERR(crtc_state); | |
6036 | } | |
6037 | ||
2f2d7aa1 | 6038 | /* disable/enable all currently active pipes while we change cdclk */ |
0a9ab303 ACO |
6039 | for_each_crtc_in_state(state, crtc, crtc_state, i) |
6040 | if (crtc_state->enable) | |
6041 | crtc_state->mode_changed = true; | |
304603f4 ACO |
6042 | |
6043 | return 0; | |
30a970c6 JB |
6044 | } |
6045 | ||
1e69cd74 VS |
6046 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
6047 | { | |
6048 | unsigned int credits, default_credits; | |
6049 | ||
6050 | if (IS_CHERRYVIEW(dev_priv)) | |
6051 | default_credits = PFI_CREDIT(12); | |
6052 | else | |
6053 | default_credits = PFI_CREDIT(8); | |
6054 | ||
164dfd28 | 6055 | if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) { |
1e69cd74 VS |
6056 | /* CHV suggested value is 31 or 63 */ |
6057 | if (IS_CHERRYVIEW(dev_priv)) | |
6058 | credits = PFI_CREDIT_31; | |
6059 | else | |
6060 | credits = PFI_CREDIT(15); | |
6061 | } else { | |
6062 | credits = default_credits; | |
6063 | } | |
6064 | ||
6065 | /* | |
6066 | * WA - write default credits before re-programming | |
6067 | * FIXME: should we also set the resend bit here? | |
6068 | */ | |
6069 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6070 | default_credits); | |
6071 | ||
6072 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6073 | credits | PFI_CREDIT_RESEND); | |
6074 | ||
6075 | /* | |
6076 | * FIXME is this guaranteed to clear | |
6077 | * immediately or should we poll for it? | |
6078 | */ | |
6079 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
6080 | } | |
6081 | ||
a821fc46 | 6082 | static void valleyview_modeset_global_resources(struct drm_atomic_state *old_state) |
30a970c6 | 6083 | { |
a821fc46 | 6084 | struct drm_device *dev = old_state->dev; |
30a970c6 | 6085 | struct drm_i915_private *dev_priv = dev->dev_private; |
a821fc46 | 6086 | int max_pixclk = intel_mode_max_pixclk(dev, NULL); |
304603f4 ACO |
6087 | int req_cdclk; |
6088 | ||
a821fc46 ACO |
6089 | /* The path in intel_mode_max_pixclk() with a NULL atomic state should |
6090 | * never fail. */ | |
304603f4 ACO |
6091 | if (WARN_ON(max_pixclk < 0)) |
6092 | return; | |
30a970c6 | 6093 | |
304603f4 | 6094 | req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); |
30a970c6 | 6095 | |
164dfd28 | 6096 | if (req_cdclk != dev_priv->cdclk_freq) { |
738c05c0 ID |
6097 | /* |
6098 | * FIXME: We can end up here with all power domains off, yet | |
6099 | * with a CDCLK frequency other than the minimum. To account | |
6100 | * for this take the PIPE-A power domain, which covers the HW | |
6101 | * blocks needed for the following programming. This can be | |
6102 | * removed once it's guaranteed that we get here either with | |
6103 | * the minimum CDCLK set, or the required power domains | |
6104 | * enabled. | |
6105 | */ | |
6106 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
6107 | ||
383c5a6a VS |
6108 | if (IS_CHERRYVIEW(dev)) |
6109 | cherryview_set_cdclk(dev, req_cdclk); | |
6110 | else | |
6111 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 6112 | |
1e69cd74 VS |
6113 | vlv_program_pfi_credits(dev_priv); |
6114 | ||
738c05c0 | 6115 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
383c5a6a | 6116 | } |
30a970c6 JB |
6117 | } |
6118 | ||
89b667f8 JB |
6119 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
6120 | { | |
6121 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6122 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
6123 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6124 | struct intel_encoder *encoder; | |
6125 | int pipe = intel_crtc->pipe; | |
23538ef1 | 6126 | bool is_dsi; |
89b667f8 | 6127 | |
83d65738 | 6128 | WARN_ON(!crtc->state->enable); |
89b667f8 JB |
6129 | |
6130 | if (intel_crtc->active) | |
6131 | return; | |
6132 | ||
409ee761 | 6133 | is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI); |
8525a235 | 6134 | |
1ae0d137 VS |
6135 | if (!is_dsi) { |
6136 | if (IS_CHERRYVIEW(dev)) | |
6e3c9717 | 6137 | chv_prepare_pll(intel_crtc, intel_crtc->config); |
1ae0d137 | 6138 | else |
6e3c9717 | 6139 | vlv_prepare_pll(intel_crtc, intel_crtc->config); |
1ae0d137 | 6140 | } |
5b18e57c | 6141 | |
6e3c9717 | 6142 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6143 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6144 | |
6145 | intel_set_pipe_timings(intel_crtc); | |
6146 | ||
c14b0485 VS |
6147 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
6148 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6149 | ||
6150 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
6151 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
6152 | } | |
6153 | ||
5b18e57c DV |
6154 | i9xx_set_pipeconf(intel_crtc); |
6155 | ||
89b667f8 | 6156 | intel_crtc->active = true; |
89b667f8 | 6157 | |
a72e4c9f | 6158 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6159 | |
89b667f8 JB |
6160 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6161 | if (encoder->pre_pll_enable) | |
6162 | encoder->pre_pll_enable(encoder); | |
6163 | ||
9d556c99 CML |
6164 | if (!is_dsi) { |
6165 | if (IS_CHERRYVIEW(dev)) | |
6e3c9717 | 6166 | chv_enable_pll(intel_crtc, intel_crtc->config); |
9d556c99 | 6167 | else |
6e3c9717 | 6168 | vlv_enable_pll(intel_crtc, intel_crtc->config); |
9d556c99 | 6169 | } |
89b667f8 JB |
6170 | |
6171 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
6172 | if (encoder->pre_enable) | |
6173 | encoder->pre_enable(encoder); | |
6174 | ||
2dd24552 JB |
6175 | i9xx_pfit_enable(intel_crtc); |
6176 | ||
63cbb074 VS |
6177 | intel_crtc_load_lut(crtc); |
6178 | ||
f37fcc2a | 6179 | intel_update_watermarks(crtc); |
e1fdc473 | 6180 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6181 | |
4b3a9526 VS |
6182 | assert_vblank_disabled(crtc); |
6183 | drm_crtc_vblank_on(crtc); | |
6184 | ||
f9b61ff6 DV |
6185 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6186 | encoder->enable(encoder); | |
89b667f8 JB |
6187 | } |
6188 | ||
f13c2ef3 DV |
6189 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
6190 | { | |
6191 | struct drm_device *dev = crtc->base.dev; | |
6192 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6193 | ||
6e3c9717 ACO |
6194 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
6195 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
6196 | } |
6197 | ||
0b8765c6 | 6198 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
6199 | { |
6200 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6201 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 6202 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 6203 | struct intel_encoder *encoder; |
79e53945 | 6204 | int pipe = intel_crtc->pipe; |
79e53945 | 6205 | |
83d65738 | 6206 | WARN_ON(!crtc->state->enable); |
08a48469 | 6207 | |
f7abfe8b CW |
6208 | if (intel_crtc->active) |
6209 | return; | |
6210 | ||
f13c2ef3 DV |
6211 | i9xx_set_pll_dividers(intel_crtc); |
6212 | ||
6e3c9717 | 6213 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6214 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6215 | |
6216 | intel_set_pipe_timings(intel_crtc); | |
6217 | ||
5b18e57c DV |
6218 | i9xx_set_pipeconf(intel_crtc); |
6219 | ||
f7abfe8b | 6220 | intel_crtc->active = true; |
6b383a7f | 6221 | |
4a3436e8 | 6222 | if (!IS_GEN2(dev)) |
a72e4c9f | 6223 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6224 | |
9d6d9f19 MK |
6225 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6226 | if (encoder->pre_enable) | |
6227 | encoder->pre_enable(encoder); | |
6228 | ||
f6736a1a DV |
6229 | i9xx_enable_pll(intel_crtc); |
6230 | ||
2dd24552 JB |
6231 | i9xx_pfit_enable(intel_crtc); |
6232 | ||
63cbb074 VS |
6233 | intel_crtc_load_lut(crtc); |
6234 | ||
f37fcc2a | 6235 | intel_update_watermarks(crtc); |
e1fdc473 | 6236 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6237 | |
4b3a9526 VS |
6238 | assert_vblank_disabled(crtc); |
6239 | drm_crtc_vblank_on(crtc); | |
6240 | ||
f9b61ff6 DV |
6241 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6242 | encoder->enable(encoder); | |
0b8765c6 | 6243 | } |
79e53945 | 6244 | |
87476d63 DV |
6245 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
6246 | { | |
6247 | struct drm_device *dev = crtc->base.dev; | |
6248 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 6249 | |
6e3c9717 | 6250 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 6251 | return; |
87476d63 | 6252 | |
328d8e82 | 6253 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 6254 | |
328d8e82 DV |
6255 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
6256 | I915_READ(PFIT_CONTROL)); | |
6257 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
6258 | } |
6259 | ||
0b8765c6 JB |
6260 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
6261 | { | |
6262 | struct drm_device *dev = crtc->dev; | |
6263 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6264 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 6265 | struct intel_encoder *encoder; |
0b8765c6 | 6266 | int pipe = intel_crtc->pipe; |
ef9c3aee | 6267 | |
f7abfe8b CW |
6268 | if (!intel_crtc->active) |
6269 | return; | |
6270 | ||
6304cd91 VS |
6271 | /* |
6272 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
6273 | * wait for planes to fully turn off before disabling the pipe. | |
564ed191 ID |
6274 | * We also need to wait on all gmch platforms because of the |
6275 | * self-refresh mode constraint explained above. | |
6304cd91 | 6276 | */ |
564ed191 | 6277 | intel_wait_for_vblank(dev, pipe); |
6304cd91 | 6278 | |
4b3a9526 VS |
6279 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6280 | encoder->disable(encoder); | |
6281 | ||
f9b61ff6 DV |
6282 | drm_crtc_vblank_off(crtc); |
6283 | assert_vblank_disabled(crtc); | |
6284 | ||
575f7ab7 | 6285 | intel_disable_pipe(intel_crtc); |
24a1f16d | 6286 | |
87476d63 | 6287 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 6288 | |
89b667f8 JB |
6289 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6290 | if (encoder->post_disable) | |
6291 | encoder->post_disable(encoder); | |
6292 | ||
409ee761 | 6293 | if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) { |
076ed3b2 CML |
6294 | if (IS_CHERRYVIEW(dev)) |
6295 | chv_disable_pll(dev_priv, pipe); | |
6296 | else if (IS_VALLEYVIEW(dev)) | |
6297 | vlv_disable_pll(dev_priv, pipe); | |
6298 | else | |
1c4e0274 | 6299 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 6300 | } |
0b8765c6 | 6301 | |
4a3436e8 | 6302 | if (!IS_GEN2(dev)) |
a72e4c9f | 6303 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
4a3436e8 | 6304 | |
f7abfe8b | 6305 | intel_crtc->active = false; |
46ba614c | 6306 | intel_update_watermarks(crtc); |
f37fcc2a | 6307 | |
efa9624e | 6308 | mutex_lock(&dev->struct_mutex); |
7ff0ebcc | 6309 | intel_fbc_update(dev); |
efa9624e | 6310 | mutex_unlock(&dev->struct_mutex); |
0b8765c6 JB |
6311 | } |
6312 | ||
ee7b9f93 JB |
6313 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
6314 | { | |
6315 | } | |
6316 | ||
b04c5bd6 BF |
6317 | /* Master function to enable/disable CRTC and corresponding power wells */ |
6318 | void intel_crtc_control(struct drm_crtc *crtc, bool enable) | |
976f8a20 DV |
6319 | { |
6320 | struct drm_device *dev = crtc->dev; | |
6321 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0e572fe7 | 6322 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
0e572fe7 DV |
6323 | enum intel_display_power_domain domain; |
6324 | unsigned long domains; | |
976f8a20 | 6325 | |
0e572fe7 DV |
6326 | if (enable) { |
6327 | if (!intel_crtc->active) { | |
e1e9fb84 DV |
6328 | domains = get_crtc_power_domains(crtc); |
6329 | for_each_power_domain(domain, domains) | |
6330 | intel_display_power_get(dev_priv, domain); | |
6331 | intel_crtc->enabled_power_domains = domains; | |
0e572fe7 DV |
6332 | |
6333 | dev_priv->display.crtc_enable(crtc); | |
ce22dba9 | 6334 | intel_crtc_enable_planes(crtc); |
0e572fe7 DV |
6335 | } |
6336 | } else { | |
6337 | if (intel_crtc->active) { | |
ce22dba9 | 6338 | intel_crtc_disable_planes(crtc); |
0e572fe7 DV |
6339 | dev_priv->display.crtc_disable(crtc); |
6340 | ||
e1e9fb84 DV |
6341 | domains = intel_crtc->enabled_power_domains; |
6342 | for_each_power_domain(domain, domains) | |
6343 | intel_display_power_put(dev_priv, domain); | |
6344 | intel_crtc->enabled_power_domains = 0; | |
0e572fe7 DV |
6345 | } |
6346 | } | |
b04c5bd6 BF |
6347 | } |
6348 | ||
6349 | /** | |
6350 | * Sets the power management mode of the pipe and plane. | |
6351 | */ | |
6352 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
6353 | { | |
6354 | struct drm_device *dev = crtc->dev; | |
6355 | struct intel_encoder *intel_encoder; | |
6356 | bool enable = false; | |
6357 | ||
6358 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
6359 | enable |= intel_encoder->connectors_active; | |
6360 | ||
6361 | intel_crtc_control(crtc, enable); | |
0f63cca2 ACO |
6362 | |
6363 | crtc->state->active = enable; | |
976f8a20 DV |
6364 | } |
6365 | ||
cdd59983 CW |
6366 | static void intel_crtc_disable(struct drm_crtc *crtc) |
6367 | { | |
cdd59983 | 6368 | struct drm_device *dev = crtc->dev; |
976f8a20 | 6369 | struct drm_connector *connector; |
ee7b9f93 | 6370 | struct drm_i915_private *dev_priv = dev->dev_private; |
cdd59983 | 6371 | |
976f8a20 | 6372 | /* crtc should still be enabled when we disable it. */ |
83d65738 | 6373 | WARN_ON(!crtc->state->enable); |
976f8a20 | 6374 | |
ce22dba9 | 6375 | intel_crtc_disable_planes(crtc); |
976f8a20 | 6376 | dev_priv->display.crtc_disable(crtc); |
ee7b9f93 JB |
6377 | dev_priv->display.off(crtc); |
6378 | ||
70a101f8 | 6379 | drm_plane_helper_disable(crtc->primary); |
976f8a20 DV |
6380 | |
6381 | /* Update computed state. */ | |
6382 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
6383 | if (!connector->encoder || !connector->encoder->crtc) | |
6384 | continue; | |
6385 | ||
6386 | if (connector->encoder->crtc != crtc) | |
6387 | continue; | |
6388 | ||
6389 | connector->dpms = DRM_MODE_DPMS_OFF; | |
6390 | to_intel_encoder(connector->encoder)->connectors_active = false; | |
cdd59983 CW |
6391 | } |
6392 | } | |
6393 | ||
ea5b213a | 6394 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6395 | { |
4ef69c7a | 6396 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6397 | |
ea5b213a CW |
6398 | drm_encoder_cleanup(encoder); |
6399 | kfree(intel_encoder); | |
7e7d76c3 JB |
6400 | } |
6401 | ||
9237329d | 6402 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
5ab432ef DV |
6403 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
6404 | * state of the entire output pipe. */ | |
9237329d | 6405 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
7e7d76c3 | 6406 | { |
5ab432ef DV |
6407 | if (mode == DRM_MODE_DPMS_ON) { |
6408 | encoder->connectors_active = true; | |
6409 | ||
b2cabb0e | 6410 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
6411 | } else { |
6412 | encoder->connectors_active = false; | |
6413 | ||
b2cabb0e | 6414 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 6415 | } |
79e53945 JB |
6416 | } |
6417 | ||
0a91ca29 DV |
6418 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6419 | * internal consistency). */ | |
b980514c | 6420 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 6421 | { |
0a91ca29 DV |
6422 | if (connector->get_hw_state(connector)) { |
6423 | struct intel_encoder *encoder = connector->encoder; | |
6424 | struct drm_crtc *crtc; | |
6425 | bool encoder_enabled; | |
6426 | enum pipe pipe; | |
6427 | ||
6428 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6429 | connector->base.base.id, | |
c23cc417 | 6430 | connector->base.name); |
0a91ca29 | 6431 | |
0e32b39c DA |
6432 | /* there is no real hw state for MST connectors */ |
6433 | if (connector->mst_port) | |
6434 | return; | |
6435 | ||
e2c719b7 | 6436 | I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, |
0a91ca29 | 6437 | "wrong connector dpms state\n"); |
e2c719b7 | 6438 | I915_STATE_WARN(connector->base.encoder != &encoder->base, |
0a91ca29 | 6439 | "active connector not linked to encoder\n"); |
0a91ca29 | 6440 | |
36cd7444 | 6441 | if (encoder) { |
e2c719b7 | 6442 | I915_STATE_WARN(!encoder->connectors_active, |
36cd7444 DA |
6443 | "encoder->connectors_active not set\n"); |
6444 | ||
6445 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
e2c719b7 RC |
6446 | I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n"); |
6447 | if (I915_STATE_WARN_ON(!encoder->base.crtc)) | |
36cd7444 | 6448 | return; |
0a91ca29 | 6449 | |
36cd7444 | 6450 | crtc = encoder->base.crtc; |
0a91ca29 | 6451 | |
83d65738 MR |
6452 | I915_STATE_WARN(!crtc->state->enable, |
6453 | "crtc not enabled\n"); | |
e2c719b7 RC |
6454 | I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); |
6455 | I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe, | |
36cd7444 DA |
6456 | "encoder active on the wrong pipe\n"); |
6457 | } | |
0a91ca29 | 6458 | } |
79e53945 JB |
6459 | } |
6460 | ||
08d9bc92 ACO |
6461 | int intel_connector_init(struct intel_connector *connector) |
6462 | { | |
6463 | struct drm_connector_state *connector_state; | |
6464 | ||
6465 | connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL); | |
6466 | if (!connector_state) | |
6467 | return -ENOMEM; | |
6468 | ||
6469 | connector->base.state = connector_state; | |
6470 | return 0; | |
6471 | } | |
6472 | ||
6473 | struct intel_connector *intel_connector_alloc(void) | |
6474 | { | |
6475 | struct intel_connector *connector; | |
6476 | ||
6477 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6478 | if (!connector) | |
6479 | return NULL; | |
6480 | ||
6481 | if (intel_connector_init(connector) < 0) { | |
6482 | kfree(connector); | |
6483 | return NULL; | |
6484 | } | |
6485 | ||
6486 | return connector; | |
6487 | } | |
6488 | ||
5ab432ef DV |
6489 | /* Even simpler default implementation, if there's really no special case to |
6490 | * consider. */ | |
6491 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 6492 | { |
5ab432ef DV |
6493 | /* All the simple cases only support two dpms states. */ |
6494 | if (mode != DRM_MODE_DPMS_ON) | |
6495 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 6496 | |
5ab432ef DV |
6497 | if (mode == connector->dpms) |
6498 | return; | |
6499 | ||
6500 | connector->dpms = mode; | |
6501 | ||
6502 | /* Only need to change hw state when actually enabled */ | |
c9976dcf CW |
6503 | if (connector->encoder) |
6504 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); | |
0a91ca29 | 6505 | |
b980514c | 6506 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
6507 | } |
6508 | ||
f0947c37 DV |
6509 | /* Simple connector->get_hw_state implementation for encoders that support only |
6510 | * one connector and no cloning and hence the encoder state determines the state | |
6511 | * of the connector. */ | |
6512 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6513 | { |
24929352 | 6514 | enum pipe pipe = 0; |
f0947c37 | 6515 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6516 | |
f0947c37 | 6517 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6518 | } |
6519 | ||
6d293983 | 6520 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6521 | { |
6d293983 ACO |
6522 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6523 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6524 | |
6525 | return 0; | |
6526 | } | |
6527 | ||
6d293983 | 6528 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6529 | struct intel_crtc_state *pipe_config) |
1857e1da | 6530 | { |
6d293983 ACO |
6531 | struct drm_atomic_state *state = pipe_config->base.state; |
6532 | struct intel_crtc *other_crtc; | |
6533 | struct intel_crtc_state *other_crtc_state; | |
6534 | ||
1857e1da DV |
6535 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6536 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6537 | if (pipe_config->fdi_lanes > 4) { | |
6538 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6539 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6540 | return -EINVAL; |
1857e1da DV |
6541 | } |
6542 | ||
bafb6553 | 6543 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
6544 | if (pipe_config->fdi_lanes > 2) { |
6545 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6546 | pipe_config->fdi_lanes); | |
6d293983 | 6547 | return -EINVAL; |
1857e1da | 6548 | } else { |
6d293983 | 6549 | return 0; |
1857e1da DV |
6550 | } |
6551 | } | |
6552 | ||
6553 | if (INTEL_INFO(dev)->num_pipes == 2) | |
6d293983 | 6554 | return 0; |
1857e1da DV |
6555 | |
6556 | /* Ivybridge 3 pipe is really complicated */ | |
6557 | switch (pipe) { | |
6558 | case PIPE_A: | |
6d293983 | 6559 | return 0; |
1857e1da | 6560 | case PIPE_B: |
6d293983 ACO |
6561 | if (pipe_config->fdi_lanes <= 2) |
6562 | return 0; | |
6563 | ||
6564 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); | |
6565 | other_crtc_state = | |
6566 | intel_atomic_get_crtc_state(state, other_crtc); | |
6567 | if (IS_ERR(other_crtc_state)) | |
6568 | return PTR_ERR(other_crtc_state); | |
6569 | ||
6570 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6571 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6572 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6573 | return -EINVAL; |
1857e1da | 6574 | } |
6d293983 | 6575 | return 0; |
1857e1da | 6576 | case PIPE_C: |
251cc67c VS |
6577 | if (pipe_config->fdi_lanes > 2) { |
6578 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6579 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6580 | return -EINVAL; |
251cc67c | 6581 | } |
6d293983 ACO |
6582 | |
6583 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); | |
6584 | other_crtc_state = | |
6585 | intel_atomic_get_crtc_state(state, other_crtc); | |
6586 | if (IS_ERR(other_crtc_state)) | |
6587 | return PTR_ERR(other_crtc_state); | |
6588 | ||
6589 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6590 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6591 | return -EINVAL; |
1857e1da | 6592 | } |
6d293983 | 6593 | return 0; |
1857e1da DV |
6594 | default: |
6595 | BUG(); | |
6596 | } | |
6597 | } | |
6598 | ||
e29c22c0 DV |
6599 | #define RETRY 1 |
6600 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6601 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6602 | { |
1857e1da | 6603 | struct drm_device *dev = intel_crtc->base.dev; |
2d112de7 | 6604 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6605 | int lane, link_bw, fdi_dotclock, ret; |
6606 | bool needs_recompute = false; | |
877d48d5 | 6607 | |
e29c22c0 | 6608 | retry: |
877d48d5 DV |
6609 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6610 | * each output octet as 10 bits. The actual frequency | |
6611 | * is stored as a divider into a 100MHz clock, and the | |
6612 | * mode pixel clock is stored in units of 1KHz. | |
6613 | * Hence the bw of each lane in terms of the mode signal | |
6614 | * is: | |
6615 | */ | |
6616 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
6617 | ||
241bfc38 | 6618 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6619 | |
2bd89a07 | 6620 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6621 | pipe_config->pipe_bpp); |
6622 | ||
6623 | pipe_config->fdi_lanes = lane; | |
6624 | ||
2bd89a07 | 6625 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 6626 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 6627 | |
6d293983 ACO |
6628 | ret = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
6629 | intel_crtc->pipe, pipe_config); | |
6630 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { | |
e29c22c0 DV |
6631 | pipe_config->pipe_bpp -= 2*3; |
6632 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
6633 | pipe_config->pipe_bpp); | |
6634 | needs_recompute = true; | |
6635 | pipe_config->bw_constrained = true; | |
6636 | ||
6637 | goto retry; | |
6638 | } | |
6639 | ||
6640 | if (needs_recompute) | |
6641 | return RETRY; | |
6642 | ||
6d293983 | 6643 | return ret; |
877d48d5 DV |
6644 | } |
6645 | ||
8cfb3407 VS |
6646 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
6647 | struct intel_crtc_state *pipe_config) | |
6648 | { | |
6649 | if (pipe_config->pipe_bpp > 24) | |
6650 | return false; | |
6651 | ||
6652 | /* HSW can handle pixel rate up to cdclk? */ | |
6653 | if (IS_HASWELL(dev_priv->dev)) | |
6654 | return true; | |
6655 | ||
6656 | /* | |
b432e5cf VS |
6657 | * We compare against max which means we must take |
6658 | * the increased cdclk requirement into account when | |
6659 | * calculating the new cdclk. | |
6660 | * | |
6661 | * Should measure whether using a lower cdclk w/o IPS | |
8cfb3407 VS |
6662 | */ |
6663 | return ilk_pipe_pixel_rate(pipe_config) <= | |
6664 | dev_priv->max_cdclk_freq * 95 / 100; | |
6665 | } | |
6666 | ||
42db64ef | 6667 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 6668 | struct intel_crtc_state *pipe_config) |
42db64ef | 6669 | { |
8cfb3407 VS |
6670 | struct drm_device *dev = crtc->base.dev; |
6671 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6672 | ||
d330a953 | 6673 | pipe_config->ips_enabled = i915.enable_ips && |
8cfb3407 VS |
6674 | hsw_crtc_supports_ips(crtc) && |
6675 | pipe_config_supports_ips(dev_priv, pipe_config); | |
42db64ef PZ |
6676 | } |
6677 | ||
a43f6e0f | 6678 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 6679 | struct intel_crtc_state *pipe_config) |
79e53945 | 6680 | { |
a43f6e0f | 6681 | struct drm_device *dev = crtc->base.dev; |
8bd31e67 | 6682 | struct drm_i915_private *dev_priv = dev->dev_private; |
2d112de7 | 6683 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
d03c93d4 | 6684 | int ret; |
89749350 | 6685 | |
ad3a4479 | 6686 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 | 6687 | if (INTEL_INFO(dev)->gen < 4) { |
44913155 | 6688 | int clock_limit = dev_priv->max_cdclk_freq; |
cf532bb2 VS |
6689 | |
6690 | /* | |
6691 | * Enable pixel doubling when the dot clock | |
6692 | * is > 90% of the (display) core speed. | |
6693 | * | |
b397c96b VS |
6694 | * GDG double wide on either pipe, |
6695 | * otherwise pipe A only. | |
cf532bb2 | 6696 | */ |
b397c96b | 6697 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
241bfc38 | 6698 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
ad3a4479 | 6699 | clock_limit *= 2; |
cf532bb2 | 6700 | pipe_config->double_wide = true; |
ad3a4479 VS |
6701 | } |
6702 | ||
241bfc38 | 6703 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
e29c22c0 | 6704 | return -EINVAL; |
2c07245f | 6705 | } |
89749350 | 6706 | |
1d1d0e27 VS |
6707 | /* |
6708 | * Pipe horizontal size must be even in: | |
6709 | * - DVO ganged mode | |
6710 | * - LVDS dual channel mode | |
6711 | * - Double wide pipe | |
6712 | */ | |
a93e255f | 6713 | if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
6714 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
6715 | pipe_config->pipe_src_w &= ~1; | |
6716 | ||
8693a824 DL |
6717 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6718 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
6719 | */ |
6720 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
6721 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
e29c22c0 | 6722 | return -EINVAL; |
44f46b42 | 6723 | |
f5adf94e | 6724 | if (HAS_IPS(dev)) |
a43f6e0f DV |
6725 | hsw_compute_ips_config(crtc, pipe_config); |
6726 | ||
877d48d5 | 6727 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 6728 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 6729 | |
d03c93d4 CK |
6730 | /* FIXME: remove below call once atomic mode set is place and all crtc |
6731 | * related checks called from atomic_crtc_check function */ | |
6732 | ret = 0; | |
6733 | DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n", | |
6734 | crtc, pipe_config->base.state); | |
6735 | ret = intel_atomic_setup_scalers(dev, crtc, pipe_config); | |
6736 | ||
6737 | return ret; | |
79e53945 JB |
6738 | } |
6739 | ||
1652d19e VS |
6740 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
6741 | { | |
6742 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6743 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
6744 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6745 | uint32_t linkrate; | |
6746 | ||
414355a7 | 6747 | if (!(lcpll1 & LCPLL_PLL_ENABLE)) |
1652d19e | 6748 | return 24000; /* 24MHz is the cd freq with NSSC ref */ |
1652d19e VS |
6749 | |
6750 | if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) | |
6751 | return 540000; | |
6752 | ||
6753 | linkrate = (I915_READ(DPLL_CTRL1) & | |
71cd8423 | 6754 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; |
1652d19e | 6755 | |
71cd8423 DL |
6756 | if (linkrate == DPLL_CTRL1_LINK_RATE_2160 || |
6757 | linkrate == DPLL_CTRL1_LINK_RATE_1080) { | |
1652d19e VS |
6758 | /* vco 8640 */ |
6759 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6760 | case CDCLK_FREQ_450_432: | |
6761 | return 432000; | |
6762 | case CDCLK_FREQ_337_308: | |
6763 | return 308570; | |
6764 | case CDCLK_FREQ_675_617: | |
6765 | return 617140; | |
6766 | default: | |
6767 | WARN(1, "Unknown cd freq selection\n"); | |
6768 | } | |
6769 | } else { | |
6770 | /* vco 8100 */ | |
6771 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6772 | case CDCLK_FREQ_450_432: | |
6773 | return 450000; | |
6774 | case CDCLK_FREQ_337_308: | |
6775 | return 337500; | |
6776 | case CDCLK_FREQ_675_617: | |
6777 | return 675000; | |
6778 | default: | |
6779 | WARN(1, "Unknown cd freq selection\n"); | |
6780 | } | |
6781 | } | |
6782 | ||
6783 | /* error case, do as if DPLL0 isn't enabled */ | |
6784 | return 24000; | |
6785 | } | |
6786 | ||
6787 | static int broadwell_get_display_clock_speed(struct drm_device *dev) | |
6788 | { | |
6789 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6790 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6791 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6792 | ||
6793 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6794 | return 800000; | |
6795 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6796 | return 450000; | |
6797 | else if (freq == LCPLL_CLK_FREQ_450) | |
6798 | return 450000; | |
6799 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
6800 | return 540000; | |
6801 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
6802 | return 337500; | |
6803 | else | |
6804 | return 675000; | |
6805 | } | |
6806 | ||
6807 | static int haswell_get_display_clock_speed(struct drm_device *dev) | |
6808 | { | |
6809 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6810 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6811 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6812 | ||
6813 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6814 | return 800000; | |
6815 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6816 | return 450000; | |
6817 | else if (freq == LCPLL_CLK_FREQ_450) | |
6818 | return 450000; | |
6819 | else if (IS_HSW_ULT(dev)) | |
6820 | return 337500; | |
6821 | else | |
6822 | return 540000; | |
79e53945 JB |
6823 | } |
6824 | ||
25eb05fc JB |
6825 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
6826 | { | |
d197b7d3 | 6827 | struct drm_i915_private *dev_priv = dev->dev_private; |
d197b7d3 VS |
6828 | u32 val; |
6829 | int divider; | |
6830 | ||
6bcda4f0 VS |
6831 | if (dev_priv->hpll_freq == 0) |
6832 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
6833 | ||
a580516d | 6834 | mutex_lock(&dev_priv->sb_lock); |
d197b7d3 | 6835 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); |
a580516d | 6836 | mutex_unlock(&dev_priv->sb_lock); |
d197b7d3 VS |
6837 | |
6838 | divider = val & DISPLAY_FREQUENCY_VALUES; | |
6839 | ||
7d007f40 VS |
6840 | WARN((val & DISPLAY_FREQUENCY_STATUS) != |
6841 | (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
6842 | "cdclk change in progress\n"); | |
6843 | ||
6bcda4f0 | 6844 | return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); |
25eb05fc JB |
6845 | } |
6846 | ||
b37a6434 VS |
6847 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
6848 | { | |
6849 | return 450000; | |
6850 | } | |
6851 | ||
e70236a8 JB |
6852 | static int i945_get_display_clock_speed(struct drm_device *dev) |
6853 | { | |
6854 | return 400000; | |
6855 | } | |
79e53945 | 6856 | |
e70236a8 | 6857 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 6858 | { |
e907f170 | 6859 | return 333333; |
e70236a8 | 6860 | } |
79e53945 | 6861 | |
e70236a8 JB |
6862 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
6863 | { | |
6864 | return 200000; | |
6865 | } | |
79e53945 | 6866 | |
257a7ffc DV |
6867 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
6868 | { | |
6869 | u16 gcfgc = 0; | |
6870 | ||
6871 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
6872 | ||
6873 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6874 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 6875 | return 266667; |
257a7ffc | 6876 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 6877 | return 333333; |
257a7ffc | 6878 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 6879 | return 444444; |
257a7ffc DV |
6880 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
6881 | return 200000; | |
6882 | default: | |
6883 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
6884 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 6885 | return 133333; |
257a7ffc | 6886 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 6887 | return 166667; |
257a7ffc DV |
6888 | } |
6889 | } | |
6890 | ||
e70236a8 JB |
6891 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
6892 | { | |
6893 | u16 gcfgc = 0; | |
79e53945 | 6894 | |
e70236a8 JB |
6895 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
6896 | ||
6897 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 6898 | return 133333; |
e70236a8 JB |
6899 | else { |
6900 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6901 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 6902 | return 333333; |
e70236a8 JB |
6903 | default: |
6904 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
6905 | return 190000; | |
79e53945 | 6906 | } |
e70236a8 JB |
6907 | } |
6908 | } | |
6909 | ||
6910 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
6911 | { | |
e907f170 | 6912 | return 266667; |
e70236a8 JB |
6913 | } |
6914 | ||
1b1d2716 | 6915 | static int i85x_get_display_clock_speed(struct drm_device *dev) |
e70236a8 JB |
6916 | { |
6917 | u16 hpllcc = 0; | |
1b1d2716 | 6918 | |
65cd2b3f VS |
6919 | /* |
6920 | * 852GM/852GMV only supports 133 MHz and the HPLLCC | |
6921 | * encoding is different :( | |
6922 | * FIXME is this the right way to detect 852GM/852GMV? | |
6923 | */ | |
6924 | if (dev->pdev->revision == 0x1) | |
6925 | return 133333; | |
6926 | ||
1b1d2716 VS |
6927 | pci_bus_read_config_word(dev->pdev->bus, |
6928 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); | |
6929 | ||
e70236a8 JB |
6930 | /* Assume that the hardware is in the high speed state. This |
6931 | * should be the default. | |
6932 | */ | |
6933 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
6934 | case GC_CLOCK_133_200: | |
1b1d2716 | 6935 | case GC_CLOCK_133_200_2: |
e70236a8 JB |
6936 | case GC_CLOCK_100_200: |
6937 | return 200000; | |
6938 | case GC_CLOCK_166_250: | |
6939 | return 250000; | |
6940 | case GC_CLOCK_100_133: | |
e907f170 | 6941 | return 133333; |
1b1d2716 VS |
6942 | case GC_CLOCK_133_266: |
6943 | case GC_CLOCK_133_266_2: | |
6944 | case GC_CLOCK_166_266: | |
6945 | return 266667; | |
e70236a8 | 6946 | } |
79e53945 | 6947 | |
e70236a8 JB |
6948 | /* Shouldn't happen */ |
6949 | return 0; | |
6950 | } | |
79e53945 | 6951 | |
e70236a8 JB |
6952 | static int i830_get_display_clock_speed(struct drm_device *dev) |
6953 | { | |
e907f170 | 6954 | return 133333; |
79e53945 JB |
6955 | } |
6956 | ||
34edce2f VS |
6957 | static unsigned int intel_hpll_vco(struct drm_device *dev) |
6958 | { | |
6959 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6960 | static const unsigned int blb_vco[8] = { | |
6961 | [0] = 3200000, | |
6962 | [1] = 4000000, | |
6963 | [2] = 5333333, | |
6964 | [3] = 4800000, | |
6965 | [4] = 6400000, | |
6966 | }; | |
6967 | static const unsigned int pnv_vco[8] = { | |
6968 | [0] = 3200000, | |
6969 | [1] = 4000000, | |
6970 | [2] = 5333333, | |
6971 | [3] = 4800000, | |
6972 | [4] = 2666667, | |
6973 | }; | |
6974 | static const unsigned int cl_vco[8] = { | |
6975 | [0] = 3200000, | |
6976 | [1] = 4000000, | |
6977 | [2] = 5333333, | |
6978 | [3] = 6400000, | |
6979 | [4] = 3333333, | |
6980 | [5] = 3566667, | |
6981 | [6] = 4266667, | |
6982 | }; | |
6983 | static const unsigned int elk_vco[8] = { | |
6984 | [0] = 3200000, | |
6985 | [1] = 4000000, | |
6986 | [2] = 5333333, | |
6987 | [3] = 4800000, | |
6988 | }; | |
6989 | static const unsigned int ctg_vco[8] = { | |
6990 | [0] = 3200000, | |
6991 | [1] = 4000000, | |
6992 | [2] = 5333333, | |
6993 | [3] = 6400000, | |
6994 | [4] = 2666667, | |
6995 | [5] = 4266667, | |
6996 | }; | |
6997 | const unsigned int *vco_table; | |
6998 | unsigned int vco; | |
6999 | uint8_t tmp = 0; | |
7000 | ||
7001 | /* FIXME other chipsets? */ | |
7002 | if (IS_GM45(dev)) | |
7003 | vco_table = ctg_vco; | |
7004 | else if (IS_G4X(dev)) | |
7005 | vco_table = elk_vco; | |
7006 | else if (IS_CRESTLINE(dev)) | |
7007 | vco_table = cl_vco; | |
7008 | else if (IS_PINEVIEW(dev)) | |
7009 | vco_table = pnv_vco; | |
7010 | else if (IS_G33(dev)) | |
7011 | vco_table = blb_vco; | |
7012 | else | |
7013 | return 0; | |
7014 | ||
7015 | tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO); | |
7016 | ||
7017 | vco = vco_table[tmp & 0x7]; | |
7018 | if (vco == 0) | |
7019 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); | |
7020 | else | |
7021 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); | |
7022 | ||
7023 | return vco; | |
7024 | } | |
7025 | ||
7026 | static int gm45_get_display_clock_speed(struct drm_device *dev) | |
7027 | { | |
7028 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7029 | uint16_t tmp = 0; | |
7030 | ||
7031 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7032 | ||
7033 | cdclk_sel = (tmp >> 12) & 0x1; | |
7034 | ||
7035 | switch (vco) { | |
7036 | case 2666667: | |
7037 | case 4000000: | |
7038 | case 5333333: | |
7039 | return cdclk_sel ? 333333 : 222222; | |
7040 | case 3200000: | |
7041 | return cdclk_sel ? 320000 : 228571; | |
7042 | default: | |
7043 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); | |
7044 | return 222222; | |
7045 | } | |
7046 | } | |
7047 | ||
7048 | static int i965gm_get_display_clock_speed(struct drm_device *dev) | |
7049 | { | |
7050 | static const uint8_t div_3200[] = { 16, 10, 8 }; | |
7051 | static const uint8_t div_4000[] = { 20, 12, 10 }; | |
7052 | static const uint8_t div_5333[] = { 24, 16, 14 }; | |
7053 | const uint8_t *div_table; | |
7054 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7055 | uint16_t tmp = 0; | |
7056 | ||
7057 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7058 | ||
7059 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; | |
7060 | ||
7061 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7062 | goto fail; | |
7063 | ||
7064 | switch (vco) { | |
7065 | case 3200000: | |
7066 | div_table = div_3200; | |
7067 | break; | |
7068 | case 4000000: | |
7069 | div_table = div_4000; | |
7070 | break; | |
7071 | case 5333333: | |
7072 | div_table = div_5333; | |
7073 | break; | |
7074 | default: | |
7075 | goto fail; | |
7076 | } | |
7077 | ||
7078 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7079 | ||
7080 | fail: | |
7081 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); | |
7082 | return 200000; | |
7083 | } | |
7084 | ||
7085 | static int g33_get_display_clock_speed(struct drm_device *dev) | |
7086 | { | |
7087 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; | |
7088 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; | |
7089 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; | |
7090 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; | |
7091 | const uint8_t *div_table; | |
7092 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7093 | uint16_t tmp = 0; | |
7094 | ||
7095 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7096 | ||
7097 | cdclk_sel = (tmp >> 4) & 0x7; | |
7098 | ||
7099 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7100 | goto fail; | |
7101 | ||
7102 | switch (vco) { | |
7103 | case 3200000: | |
7104 | div_table = div_3200; | |
7105 | break; | |
7106 | case 4000000: | |
7107 | div_table = div_4000; | |
7108 | break; | |
7109 | case 4800000: | |
7110 | div_table = div_4800; | |
7111 | break; | |
7112 | case 5333333: | |
7113 | div_table = div_5333; | |
7114 | break; | |
7115 | default: | |
7116 | goto fail; | |
7117 | } | |
7118 | ||
7119 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7120 | ||
7121 | fail: | |
7122 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); | |
7123 | return 190476; | |
7124 | } | |
7125 | ||
2c07245f | 7126 | static void |
a65851af | 7127 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 7128 | { |
a65851af VS |
7129 | while (*num > DATA_LINK_M_N_MASK || |
7130 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
7131 | *num >>= 1; |
7132 | *den >>= 1; | |
7133 | } | |
7134 | } | |
7135 | ||
a65851af VS |
7136 | static void compute_m_n(unsigned int m, unsigned int n, |
7137 | uint32_t *ret_m, uint32_t *ret_n) | |
7138 | { | |
7139 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
7140 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
7141 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
7142 | } | |
7143 | ||
e69d0bc1 DV |
7144 | void |
7145 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
7146 | int pixel_clock, int link_clock, | |
7147 | struct intel_link_m_n *m_n) | |
2c07245f | 7148 | { |
e69d0bc1 | 7149 | m_n->tu = 64; |
a65851af VS |
7150 | |
7151 | compute_m_n(bits_per_pixel * pixel_clock, | |
7152 | link_clock * nlanes * 8, | |
7153 | &m_n->gmch_m, &m_n->gmch_n); | |
7154 | ||
7155 | compute_m_n(pixel_clock, link_clock, | |
7156 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
7157 | } |
7158 | ||
a7615030 CW |
7159 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
7160 | { | |
d330a953 JN |
7161 | if (i915.panel_use_ssc >= 0) |
7162 | return i915.panel_use_ssc != 0; | |
41aa3448 | 7163 | return dev_priv->vbt.lvds_use_ssc |
435793df | 7164 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
7165 | } |
7166 | ||
a93e255f ACO |
7167 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
7168 | int num_connectors) | |
c65d77d8 | 7169 | { |
a93e255f | 7170 | struct drm_device *dev = crtc_state->base.crtc->dev; |
c65d77d8 JB |
7171 | struct drm_i915_private *dev_priv = dev->dev_private; |
7172 | int refclk; | |
7173 | ||
a93e255f ACO |
7174 | WARN_ON(!crtc_state->base.state); |
7175 | ||
5ab7b0b7 | 7176 | if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) { |
9a0ea498 | 7177 | refclk = 100000; |
a93e255f | 7178 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 7179 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
7180 | refclk = dev_priv->vbt.lvds_ssc_freq; |
7181 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
7182 | } else if (!IS_GEN2(dev)) { |
7183 | refclk = 96000; | |
7184 | } else { | |
7185 | refclk = 48000; | |
7186 | } | |
7187 | ||
7188 | return refclk; | |
7189 | } | |
7190 | ||
7429e9d4 | 7191 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 7192 | { |
7df00d7a | 7193 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 7194 | } |
f47709a9 | 7195 | |
7429e9d4 DV |
7196 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
7197 | { | |
7198 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
7199 | } |
7200 | ||
f47709a9 | 7201 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 7202 | struct intel_crtc_state *crtc_state, |
a7516a05 JB |
7203 | intel_clock_t *reduced_clock) |
7204 | { | |
f47709a9 | 7205 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
7206 | u32 fp, fp2 = 0; |
7207 | ||
7208 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 7209 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7210 | if (reduced_clock) |
7429e9d4 | 7211 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 7212 | } else { |
190f68c5 | 7213 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7214 | if (reduced_clock) |
7429e9d4 | 7215 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
7216 | } |
7217 | ||
190f68c5 | 7218 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 7219 | |
f47709a9 | 7220 | crtc->lowfreq_avail = false; |
a93e255f | 7221 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 7222 | reduced_clock) { |
190f68c5 | 7223 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 7224 | crtc->lowfreq_avail = true; |
a7516a05 | 7225 | } else { |
190f68c5 | 7226 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
7227 | } |
7228 | } | |
7229 | ||
5e69f97f CML |
7230 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
7231 | pipe) | |
89b667f8 JB |
7232 | { |
7233 | u32 reg_val; | |
7234 | ||
7235 | /* | |
7236 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
7237 | * and set it to a reasonable value instead. | |
7238 | */ | |
ab3c759a | 7239 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
7240 | reg_val &= 0xffffff00; |
7241 | reg_val |= 0x00000030; | |
ab3c759a | 7242 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7243 | |
ab3c759a | 7244 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7245 | reg_val &= 0x8cffffff; |
7246 | reg_val = 0x8c000000; | |
ab3c759a | 7247 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 7248 | |
ab3c759a | 7249 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 7250 | reg_val &= 0xffffff00; |
ab3c759a | 7251 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7252 | |
ab3c759a | 7253 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7254 | reg_val &= 0x00ffffff; |
7255 | reg_val |= 0xb0000000; | |
ab3c759a | 7256 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
7257 | } |
7258 | ||
b551842d DV |
7259 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
7260 | struct intel_link_m_n *m_n) | |
7261 | { | |
7262 | struct drm_device *dev = crtc->base.dev; | |
7263 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7264 | int pipe = crtc->pipe; | |
7265 | ||
e3b95f1e DV |
7266 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7267 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
7268 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
7269 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
7270 | } |
7271 | ||
7272 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
7273 | struct intel_link_m_n *m_n, |
7274 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
7275 | { |
7276 | struct drm_device *dev = crtc->base.dev; | |
7277 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7278 | int pipe = crtc->pipe; | |
6e3c9717 | 7279 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
7280 | |
7281 | if (INTEL_INFO(dev)->gen >= 5) { | |
7282 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
7283 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
7284 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
7285 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
7286 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
7287 | * for gen < 8) and if DRRS is supported (to make sure the | |
7288 | * registers are not unnecessarily accessed). | |
7289 | */ | |
44395bfe | 7290 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 7291 | crtc->config->has_drrs) { |
f769cd24 VK |
7292 | I915_WRITE(PIPE_DATA_M2(transcoder), |
7293 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
7294 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
7295 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
7296 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
7297 | } | |
b551842d | 7298 | } else { |
e3b95f1e DV |
7299 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7300 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
7301 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
7302 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
7303 | } |
7304 | } | |
7305 | ||
fe3cd48d | 7306 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 7307 | { |
fe3cd48d R |
7308 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
7309 | ||
7310 | if (m_n == M1_N1) { | |
7311 | dp_m_n = &crtc->config->dp_m_n; | |
7312 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
7313 | } else if (m_n == M2_N2) { | |
7314 | ||
7315 | /* | |
7316 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
7317 | * needs to be programmed into M1_N1. | |
7318 | */ | |
7319 | dp_m_n = &crtc->config->dp_m2_n2; | |
7320 | } else { | |
7321 | DRM_ERROR("Unsupported divider value\n"); | |
7322 | return; | |
7323 | } | |
7324 | ||
6e3c9717 ACO |
7325 | if (crtc->config->has_pch_encoder) |
7326 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 7327 | else |
fe3cd48d | 7328 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
7329 | } |
7330 | ||
d288f65f | 7331 | static void vlv_update_pll(struct intel_crtc *crtc, |
5cec258b | 7332 | struct intel_crtc_state *pipe_config) |
bdd4b6a6 DV |
7333 | { |
7334 | u32 dpll, dpll_md; | |
7335 | ||
7336 | /* | |
7337 | * Enable DPIO clock input. We should never disable the reference | |
7338 | * clock for pipe B, since VGA hotplug / manual detection depends | |
7339 | * on it. | |
7340 | */ | |
7341 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | | |
7342 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; | |
7343 | /* We should never disable this, set it here for state tracking */ | |
7344 | if (crtc->pipe == PIPE_B) | |
7345 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
7346 | dpll |= DPLL_VCO_ENABLE; | |
d288f65f | 7347 | pipe_config->dpll_hw_state.dpll = dpll; |
bdd4b6a6 | 7348 | |
d288f65f | 7349 | dpll_md = (pipe_config->pixel_multiplier - 1) |
bdd4b6a6 | 7350 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
d288f65f | 7351 | pipe_config->dpll_hw_state.dpll_md = dpll_md; |
bdd4b6a6 DV |
7352 | } |
7353 | ||
d288f65f | 7354 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7355 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 7356 | { |
f47709a9 | 7357 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 7358 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 7359 | int pipe = crtc->pipe; |
bdd4b6a6 | 7360 | u32 mdiv; |
a0c4da24 | 7361 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 7362 | u32 coreclk, reg_val; |
a0c4da24 | 7363 | |
a580516d | 7364 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 7365 | |
d288f65f VS |
7366 | bestn = pipe_config->dpll.n; |
7367 | bestm1 = pipe_config->dpll.m1; | |
7368 | bestm2 = pipe_config->dpll.m2; | |
7369 | bestp1 = pipe_config->dpll.p1; | |
7370 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 7371 | |
89b667f8 JB |
7372 | /* See eDP HDMI DPIO driver vbios notes doc */ |
7373 | ||
7374 | /* PLL B needs special handling */ | |
bdd4b6a6 | 7375 | if (pipe == PIPE_B) |
5e69f97f | 7376 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
7377 | |
7378 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 7379 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
7380 | |
7381 | /* Disable target IRef on PLL */ | |
ab3c759a | 7382 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 7383 | reg_val &= 0x00ffffff; |
ab3c759a | 7384 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
7385 | |
7386 | /* Disable fast lock */ | |
ab3c759a | 7387 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
7388 | |
7389 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
7390 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
7391 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
7392 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 7393 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
7394 | |
7395 | /* | |
7396 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
7397 | * but we don't support that). | |
7398 | * Note: don't use the DAC post divider as it seems unstable. | |
7399 | */ | |
7400 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 7401 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7402 | |
a0c4da24 | 7403 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 7404 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7405 | |
89b667f8 | 7406 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 7407 | if (pipe_config->port_clock == 162000 || |
409ee761 ACO |
7408 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || |
7409 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 7410 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 7411 | 0x009f0003); |
89b667f8 | 7412 | else |
ab3c759a | 7413 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
7414 | 0x00d0000f); |
7415 | ||
681a8504 | 7416 | if (pipe_config->has_dp_encoder) { |
89b667f8 | 7417 | /* Use SSC source */ |
bdd4b6a6 | 7418 | if (pipe == PIPE_A) |
ab3c759a | 7419 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7420 | 0x0df40000); |
7421 | else | |
ab3c759a | 7422 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7423 | 0x0df70000); |
7424 | } else { /* HDMI or VGA */ | |
7425 | /* Use bend source */ | |
bdd4b6a6 | 7426 | if (pipe == PIPE_A) |
ab3c759a | 7427 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7428 | 0x0df70000); |
7429 | else | |
ab3c759a | 7430 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7431 | 0x0df40000); |
7432 | } | |
a0c4da24 | 7433 | |
ab3c759a | 7434 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 7435 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
409ee761 ACO |
7436 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
7437 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) | |
89b667f8 | 7438 | coreclk |= 0x01000000; |
ab3c759a | 7439 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 7440 | |
ab3c759a | 7441 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 7442 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
7443 | } |
7444 | ||
d288f65f | 7445 | static void chv_update_pll(struct intel_crtc *crtc, |
5cec258b | 7446 | struct intel_crtc_state *pipe_config) |
1ae0d137 | 7447 | { |
d288f65f | 7448 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV | |
1ae0d137 VS |
7449 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | |
7450 | DPLL_VCO_ENABLE; | |
7451 | if (crtc->pipe != PIPE_A) | |
d288f65f | 7452 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
1ae0d137 | 7453 | |
d288f65f VS |
7454 | pipe_config->dpll_hw_state.dpll_md = |
7455 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
1ae0d137 VS |
7456 | } |
7457 | ||
d288f65f | 7458 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7459 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
7460 | { |
7461 | struct drm_device *dev = crtc->base.dev; | |
7462 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7463 | int pipe = crtc->pipe; | |
7464 | int dpll_reg = DPLL(crtc->pipe); | |
7465 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9cbe40c1 | 7466 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 7467 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 7468 | u32 dpio_val; |
9cbe40c1 | 7469 | int vco; |
9d556c99 | 7470 | |
d288f65f VS |
7471 | bestn = pipe_config->dpll.n; |
7472 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
7473 | bestm1 = pipe_config->dpll.m1; | |
7474 | bestm2 = pipe_config->dpll.m2 >> 22; | |
7475 | bestp1 = pipe_config->dpll.p1; | |
7476 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 7477 | vco = pipe_config->dpll.vco; |
a945ce7e | 7478 | dpio_val = 0; |
9cbe40c1 | 7479 | loopfilter = 0; |
9d556c99 CML |
7480 | |
7481 | /* | |
7482 | * Enable Refclk and SSC | |
7483 | */ | |
a11b0703 | 7484 | I915_WRITE(dpll_reg, |
d288f65f | 7485 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
a11b0703 | 7486 | |
a580516d | 7487 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 7488 | |
9d556c99 CML |
7489 | /* p1 and p2 divider */ |
7490 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
7491 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
7492 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
7493 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
7494 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
7495 | ||
7496 | /* Feedback post-divider - m2 */ | |
7497 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
7498 | ||
7499 | /* Feedback refclk divider - n and m1 */ | |
7500 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
7501 | DPIO_CHV_M1_DIV_BY_2 | | |
7502 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
7503 | ||
7504 | /* M2 fraction division */ | |
a945ce7e VP |
7505 | if (bestm2_frac) |
7506 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); | |
9d556c99 CML |
7507 | |
7508 | /* M2 fraction division enable */ | |
a945ce7e VP |
7509 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
7510 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
7511 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
7512 | if (bestm2_frac) | |
7513 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
7514 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 7515 | |
de3a0fde VP |
7516 | /* Program digital lock detect threshold */ |
7517 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
7518 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
7519 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
7520 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
7521 | if (!bestm2_frac) | |
7522 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
7523 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
7524 | ||
9d556c99 | 7525 | /* Loop filter */ |
9cbe40c1 VP |
7526 | if (vco == 5400000) { |
7527 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7528 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
7529 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7530 | tribuf_calcntr = 0x9; | |
7531 | } else if (vco <= 6200000) { | |
7532 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7533 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
7534 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7535 | tribuf_calcntr = 0x9; | |
7536 | } else if (vco <= 6480000) { | |
7537 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7538 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7539 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7540 | tribuf_calcntr = 0x8; | |
7541 | } else { | |
7542 | /* Not supported. Apply the same limits as in the max case */ | |
7543 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7544 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7545 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7546 | tribuf_calcntr = 0; | |
7547 | } | |
9d556c99 CML |
7548 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
7549 | ||
968040b2 | 7550 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
7551 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
7552 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
7553 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
7554 | ||
9d556c99 CML |
7555 | /* AFC Recal */ |
7556 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
7557 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
7558 | DPIO_AFC_RECAL); | |
7559 | ||
a580516d | 7560 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
7561 | } |
7562 | ||
d288f65f VS |
7563 | /** |
7564 | * vlv_force_pll_on - forcibly enable just the PLL | |
7565 | * @dev_priv: i915 private structure | |
7566 | * @pipe: pipe PLL to enable | |
7567 | * @dpll: PLL configuration | |
7568 | * | |
7569 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
7570 | * in cases where we need the PLL enabled even when @pipe is not going to | |
7571 | * be enabled. | |
7572 | */ | |
7573 | void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, | |
7574 | const struct dpll *dpll) | |
7575 | { | |
7576 | struct intel_crtc *crtc = | |
7577 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
5cec258b | 7578 | struct intel_crtc_state pipe_config = { |
a93e255f | 7579 | .base.crtc = &crtc->base, |
d288f65f VS |
7580 | .pixel_multiplier = 1, |
7581 | .dpll = *dpll, | |
7582 | }; | |
7583 | ||
7584 | if (IS_CHERRYVIEW(dev)) { | |
7585 | chv_update_pll(crtc, &pipe_config); | |
7586 | chv_prepare_pll(crtc, &pipe_config); | |
7587 | chv_enable_pll(crtc, &pipe_config); | |
7588 | } else { | |
7589 | vlv_update_pll(crtc, &pipe_config); | |
7590 | vlv_prepare_pll(crtc, &pipe_config); | |
7591 | vlv_enable_pll(crtc, &pipe_config); | |
7592 | } | |
7593 | } | |
7594 | ||
7595 | /** | |
7596 | * vlv_force_pll_off - forcibly disable just the PLL | |
7597 | * @dev_priv: i915 private structure | |
7598 | * @pipe: pipe PLL to disable | |
7599 | * | |
7600 | * Disable the PLL for @pipe. To be used in cases where we need | |
7601 | * the PLL enabled even when @pipe is not going to be enabled. | |
7602 | */ | |
7603 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
7604 | { | |
7605 | if (IS_CHERRYVIEW(dev)) | |
7606 | chv_disable_pll(to_i915(dev), pipe); | |
7607 | else | |
7608 | vlv_disable_pll(to_i915(dev), pipe); | |
7609 | } | |
7610 | ||
f47709a9 | 7611 | static void i9xx_update_pll(struct intel_crtc *crtc, |
190f68c5 | 7612 | struct intel_crtc_state *crtc_state, |
f47709a9 | 7613 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
7614 | int num_connectors) |
7615 | { | |
f47709a9 | 7616 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7617 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
7618 | u32 dpll; |
7619 | bool is_sdvo; | |
190f68c5 | 7620 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7621 | |
190f68c5 | 7622 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7623 | |
a93e255f ACO |
7624 | is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) || |
7625 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
7626 | |
7627 | dpll = DPLL_VGA_MODE_DIS; | |
7628 | ||
a93e255f | 7629 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
7630 | dpll |= DPLLB_MODE_LVDS; |
7631 | else | |
7632 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 7633 | |
ef1b460d | 7634 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 7635 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 7636 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 7637 | } |
198a037f DV |
7638 | |
7639 | if (is_sdvo) | |
4a33e48d | 7640 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 7641 | |
190f68c5 | 7642 | if (crtc_state->has_dp_encoder) |
4a33e48d | 7643 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
7644 | |
7645 | /* compute bitmask from p1 value */ | |
7646 | if (IS_PINEVIEW(dev)) | |
7647 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
7648 | else { | |
7649 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7650 | if (IS_G4X(dev) && reduced_clock) | |
7651 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
7652 | } | |
7653 | switch (clock->p2) { | |
7654 | case 5: | |
7655 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7656 | break; | |
7657 | case 7: | |
7658 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7659 | break; | |
7660 | case 10: | |
7661 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7662 | break; | |
7663 | case 14: | |
7664 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7665 | break; | |
7666 | } | |
7667 | if (INTEL_INFO(dev)->gen >= 4) | |
7668 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
7669 | ||
190f68c5 | 7670 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 7671 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
a93e255f | 7672 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7673 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7674 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7675 | else | |
7676 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7677 | ||
7678 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7679 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 7680 | |
eb1cbe48 | 7681 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 7682 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7683 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 7684 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
7685 | } |
7686 | } | |
7687 | ||
f47709a9 | 7688 | static void i8xx_update_pll(struct intel_crtc *crtc, |
190f68c5 | 7689 | struct intel_crtc_state *crtc_state, |
f47709a9 | 7690 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
7691 | int num_connectors) |
7692 | { | |
f47709a9 | 7693 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7694 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 7695 | u32 dpll; |
190f68c5 | 7696 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7697 | |
190f68c5 | 7698 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7699 | |
eb1cbe48 DV |
7700 | dpll = DPLL_VGA_MODE_DIS; |
7701 | ||
a93e255f | 7702 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
7703 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
7704 | } else { | |
7705 | if (clock->p1 == 2) | |
7706 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
7707 | else | |
7708 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7709 | if (clock->p2 == 4) | |
7710 | dpll |= PLL_P2_DIVIDE_BY_4; | |
7711 | } | |
7712 | ||
a93e255f | 7713 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
7714 | dpll |= DPLL_DVO_2X_MODE; |
7715 | ||
a93e255f | 7716 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7717 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7718 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7719 | else | |
7720 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7721 | ||
7722 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7723 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
7724 | } |
7725 | ||
8a654f3b | 7726 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
7727 | { |
7728 | struct drm_device *dev = intel_crtc->base.dev; | |
7729 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7730 | enum pipe pipe = intel_crtc->pipe; | |
6e3c9717 | 7731 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
8a654f3b | 7732 | struct drm_display_mode *adjusted_mode = |
6e3c9717 | 7733 | &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
7734 | uint32_t crtc_vtotal, crtc_vblank_end; |
7735 | int vsyncshift = 0; | |
4d8a62ea DV |
7736 | |
7737 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
7738 | * the hw state checker will get angry at the mismatch. */ | |
7739 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
7740 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 7741 | |
609aeaca | 7742 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 7743 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
7744 | crtc_vtotal -= 1; |
7745 | crtc_vblank_end -= 1; | |
609aeaca | 7746 | |
409ee761 | 7747 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
7748 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
7749 | else | |
7750 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
7751 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
7752 | if (vsyncshift < 0) |
7753 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
7754 | } |
7755 | ||
7756 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 7757 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 7758 | |
fe2b8f9d | 7759 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
7760 | (adjusted_mode->crtc_hdisplay - 1) | |
7761 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 7762 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
7763 | (adjusted_mode->crtc_hblank_start - 1) | |
7764 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 7765 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
7766 | (adjusted_mode->crtc_hsync_start - 1) | |
7767 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
7768 | ||
fe2b8f9d | 7769 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 7770 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 7771 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 7772 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 7773 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 7774 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 7775 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
7776 | (adjusted_mode->crtc_vsync_start - 1) | |
7777 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
7778 | ||
b5e508d4 PZ |
7779 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
7780 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
7781 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
7782 | * bits. */ | |
7783 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
7784 | (pipe == PIPE_B || pipe == PIPE_C)) | |
7785 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
7786 | ||
b0e77b9c PZ |
7787 | /* pipesrc controls the size that is scaled from, which should |
7788 | * always be the user's requested size. | |
7789 | */ | |
7790 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
7791 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
7792 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
7793 | } |
7794 | ||
1bd1bd80 | 7795 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 7796 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
7797 | { |
7798 | struct drm_device *dev = crtc->base.dev; | |
7799 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7800 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
7801 | uint32_t tmp; | |
7802 | ||
7803 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7804 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
7805 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7806 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
7807 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
7808 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7809 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
7810 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
7811 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7812 | |
7813 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7814 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
7815 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7816 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
7817 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
7818 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7819 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
7820 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
7821 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7822 | |
7823 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
7824 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
7825 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
7826 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 DV |
7827 | } |
7828 | ||
7829 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
7830 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
7831 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
7832 | ||
2d112de7 ACO |
7833 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
7834 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
7835 | } |
7836 | ||
f6a83288 | 7837 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 7838 | struct intel_crtc_state *pipe_config) |
babea61d | 7839 | { |
2d112de7 ACO |
7840 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
7841 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
7842 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
7843 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 7844 | |
2d112de7 ACO |
7845 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
7846 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
7847 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7848 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 7849 | |
2d112de7 | 7850 | mode->flags = pipe_config->base.adjusted_mode.flags; |
babea61d | 7851 | |
2d112de7 ACO |
7852 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
7853 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
babea61d JB |
7854 | } |
7855 | ||
84b046f3 DV |
7856 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7857 | { | |
7858 | struct drm_device *dev = intel_crtc->base.dev; | |
7859 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7860 | uint32_t pipeconf; | |
7861 | ||
9f11a9e4 | 7862 | pipeconf = 0; |
84b046f3 | 7863 | |
b6b5d049 VS |
7864 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
7865 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
7866 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 7867 | |
6e3c9717 | 7868 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7869 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7870 | |
ff9ce46e DV |
7871 | /* only g4x and later have fancy bpc/dither controls */ |
7872 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
ff9ce46e | 7873 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 7874 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 7875 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 7876 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 7877 | |
6e3c9717 | 7878 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
7879 | case 18: |
7880 | pipeconf |= PIPECONF_6BPC; | |
7881 | break; | |
7882 | case 24: | |
7883 | pipeconf |= PIPECONF_8BPC; | |
7884 | break; | |
7885 | case 30: | |
7886 | pipeconf |= PIPECONF_10BPC; | |
7887 | break; | |
7888 | default: | |
7889 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7890 | BUG(); | |
84b046f3 DV |
7891 | } |
7892 | } | |
7893 | ||
7894 | if (HAS_PIPE_CXSR(dev)) { | |
7895 | if (intel_crtc->lowfreq_avail) { | |
7896 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
7897 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
7898 | } else { | |
7899 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
7900 | } |
7901 | } | |
7902 | ||
6e3c9717 | 7903 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 7904 | if (INTEL_INFO(dev)->gen < 4 || |
409ee761 | 7905 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
7906 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
7907 | else | |
7908 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7909 | } else | |
84b046f3 DV |
7910 | pipeconf |= PIPECONF_PROGRESSIVE; |
7911 | ||
6e3c9717 | 7912 | if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range) |
9f11a9e4 | 7913 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 7914 | |
84b046f3 DV |
7915 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7916 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7917 | } | |
7918 | ||
190f68c5 ACO |
7919 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
7920 | struct intel_crtc_state *crtc_state) | |
79e53945 | 7921 | { |
c7653199 | 7922 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 7923 | struct drm_i915_private *dev_priv = dev->dev_private; |
c751ce4f | 7924 | int refclk, num_connectors = 0; |
652c393a | 7925 | intel_clock_t clock, reduced_clock; |
a16af721 | 7926 | bool ok, has_reduced_clock = false; |
e9fd1c02 | 7927 | bool is_lvds = false, is_dsi = false; |
5eddb70b | 7928 | struct intel_encoder *encoder; |
d4906093 | 7929 | const intel_limit_t *limit; |
55bb9992 | 7930 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 7931 | struct drm_connector *connector; |
55bb9992 ACO |
7932 | struct drm_connector_state *connector_state; |
7933 | int i; | |
79e53945 | 7934 | |
dd3cd74a ACO |
7935 | memset(&crtc_state->dpll_hw_state, 0, |
7936 | sizeof(crtc_state->dpll_hw_state)); | |
7937 | ||
da3ced29 | 7938 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
7939 | if (connector_state->crtc != &crtc->base) |
7940 | continue; | |
7941 | ||
7942 | encoder = to_intel_encoder(connector_state->best_encoder); | |
7943 | ||
5eddb70b | 7944 | switch (encoder->type) { |
79e53945 JB |
7945 | case INTEL_OUTPUT_LVDS: |
7946 | is_lvds = true; | |
7947 | break; | |
e9fd1c02 JN |
7948 | case INTEL_OUTPUT_DSI: |
7949 | is_dsi = true; | |
7950 | break; | |
6847d71b PZ |
7951 | default: |
7952 | break; | |
79e53945 | 7953 | } |
43565a06 | 7954 | |
c751ce4f | 7955 | num_connectors++; |
79e53945 JB |
7956 | } |
7957 | ||
f2335330 | 7958 | if (is_dsi) |
5b18e57c | 7959 | return 0; |
f2335330 | 7960 | |
190f68c5 | 7961 | if (!crtc_state->clock_set) { |
a93e255f | 7962 | refclk = i9xx_get_refclk(crtc_state, num_connectors); |
79e53945 | 7963 | |
e9fd1c02 JN |
7964 | /* |
7965 | * Returns a set of divisors for the desired target clock with | |
7966 | * the given refclk, or FALSE. The returned values represent | |
7967 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
7968 | * 2) / p1 / p2. | |
7969 | */ | |
a93e255f ACO |
7970 | limit = intel_limit(crtc_state, refclk); |
7971 | ok = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 7972 | crtc_state->port_clock, |
e9fd1c02 | 7973 | refclk, NULL, &clock); |
f2335330 | 7974 | if (!ok) { |
e9fd1c02 JN |
7975 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
7976 | return -EINVAL; | |
7977 | } | |
79e53945 | 7978 | |
f2335330 JN |
7979 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
7980 | /* | |
7981 | * Ensure we match the reduced clock's P to the target | |
7982 | * clock. If the clocks don't match, we can't switch | |
7983 | * the display clock by using the FP0/FP1. In such case | |
7984 | * we will disable the LVDS downclock feature. | |
7985 | */ | |
7986 | has_reduced_clock = | |
a93e255f | 7987 | dev_priv->display.find_dpll(limit, crtc_state, |
f2335330 JN |
7988 | dev_priv->lvds_downclock, |
7989 | refclk, &clock, | |
7990 | &reduced_clock); | |
7991 | } | |
7992 | /* Compat-code for transition, will disappear. */ | |
190f68c5 ACO |
7993 | crtc_state->dpll.n = clock.n; |
7994 | crtc_state->dpll.m1 = clock.m1; | |
7995 | crtc_state->dpll.m2 = clock.m2; | |
7996 | crtc_state->dpll.p1 = clock.p1; | |
7997 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 7998 | } |
7026d4ac | 7999 | |
e9fd1c02 | 8000 | if (IS_GEN2(dev)) { |
190f68c5 | 8001 | i8xx_update_pll(crtc, crtc_state, |
2a8f64ca VP |
8002 | has_reduced_clock ? &reduced_clock : NULL, |
8003 | num_connectors); | |
9d556c99 | 8004 | } else if (IS_CHERRYVIEW(dev)) { |
190f68c5 | 8005 | chv_update_pll(crtc, crtc_state); |
e9fd1c02 | 8006 | } else if (IS_VALLEYVIEW(dev)) { |
190f68c5 | 8007 | vlv_update_pll(crtc, crtc_state); |
e9fd1c02 | 8008 | } else { |
190f68c5 | 8009 | i9xx_update_pll(crtc, crtc_state, |
eb1cbe48 | 8010 | has_reduced_clock ? &reduced_clock : NULL, |
eba905b2 | 8011 | num_connectors); |
e9fd1c02 | 8012 | } |
79e53945 | 8013 | |
c8f7a0db | 8014 | return 0; |
f564048e EA |
8015 | } |
8016 | ||
2fa2fe9a | 8017 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8018 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
8019 | { |
8020 | struct drm_device *dev = crtc->base.dev; | |
8021 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8022 | uint32_t tmp; | |
8023 | ||
dc9e7dec VS |
8024 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
8025 | return; | |
8026 | ||
2fa2fe9a | 8027 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
8028 | if (!(tmp & PFIT_ENABLE)) |
8029 | return; | |
2fa2fe9a | 8030 | |
06922821 | 8031 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
8032 | if (INTEL_INFO(dev)->gen < 4) { |
8033 | if (crtc->pipe != PIPE_B) | |
8034 | return; | |
2fa2fe9a DV |
8035 | } else { |
8036 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
8037 | return; | |
8038 | } | |
8039 | ||
06922821 | 8040 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
8041 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
8042 | if (INTEL_INFO(dev)->gen < 5) | |
8043 | pipe_config->gmch_pfit.lvds_border_bits = | |
8044 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
8045 | } | |
8046 | ||
acbec814 | 8047 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8048 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
8049 | { |
8050 | struct drm_device *dev = crtc->base.dev; | |
8051 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8052 | int pipe = pipe_config->cpu_transcoder; | |
8053 | intel_clock_t clock; | |
8054 | u32 mdiv; | |
662c6ecb | 8055 | int refclk = 100000; |
acbec814 | 8056 | |
f573de5a SK |
8057 | /* In case of MIPI DPLL will not even be used */ |
8058 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) | |
8059 | return; | |
8060 | ||
a580516d | 8061 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 8062 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 8063 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
8064 | |
8065 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
8066 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
8067 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
8068 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
8069 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
8070 | ||
f646628b | 8071 | vlv_clock(refclk, &clock); |
acbec814 | 8072 | |
f646628b VS |
8073 | /* clock.dot is the fast clock */ |
8074 | pipe_config->port_clock = clock.dot / 5; | |
acbec814 JB |
8075 | } |
8076 | ||
5724dbd1 DL |
8077 | static void |
8078 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
8079 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
8080 | { |
8081 | struct drm_device *dev = crtc->base.dev; | |
8082 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8083 | u32 val, base, offset; | |
8084 | int pipe = crtc->pipe, plane = crtc->plane; | |
8085 | int fourcc, pixel_format; | |
6761dd31 | 8086 | unsigned int aligned_height; |
b113d5ee | 8087 | struct drm_framebuffer *fb; |
1b842c89 | 8088 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 8089 | |
42a7b088 DL |
8090 | val = I915_READ(DSPCNTR(plane)); |
8091 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8092 | return; | |
8093 | ||
d9806c9f | 8094 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8095 | if (!intel_fb) { |
1ad292b5 JB |
8096 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8097 | return; | |
8098 | } | |
8099 | ||
1b842c89 DL |
8100 | fb = &intel_fb->base; |
8101 | ||
18c5247e DV |
8102 | if (INTEL_INFO(dev)->gen >= 4) { |
8103 | if (val & DISPPLANE_TILED) { | |
49af449b | 8104 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
8105 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
8106 | } | |
8107 | } | |
1ad292b5 JB |
8108 | |
8109 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8110 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
8111 | fb->pixel_format = fourcc; |
8112 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
8113 | |
8114 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 8115 | if (plane_config->tiling) |
1ad292b5 JB |
8116 | offset = I915_READ(DSPTILEOFF(plane)); |
8117 | else | |
8118 | offset = I915_READ(DSPLINOFF(plane)); | |
8119 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
8120 | } else { | |
8121 | base = I915_READ(DSPADDR(plane)); | |
8122 | } | |
8123 | plane_config->base = base; | |
8124 | ||
8125 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8126 | fb->width = ((val >> 16) & 0xfff) + 1; |
8127 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
8128 | |
8129 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8130 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 8131 | |
b113d5ee | 8132 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
8133 | fb->pixel_format, |
8134 | fb->modifier[0]); | |
1ad292b5 | 8135 | |
f37b5c2b | 8136 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 8137 | |
2844a921 DL |
8138 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8139 | pipe_name(pipe), plane, fb->width, fb->height, | |
8140 | fb->bits_per_pixel, base, fb->pitches[0], | |
8141 | plane_config->size); | |
1ad292b5 | 8142 | |
2d14030b | 8143 | plane_config->fb = intel_fb; |
1ad292b5 JB |
8144 | } |
8145 | ||
70b23a98 | 8146 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8147 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
8148 | { |
8149 | struct drm_device *dev = crtc->base.dev; | |
8150 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8151 | int pipe = pipe_config->cpu_transcoder; | |
8152 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
8153 | intel_clock_t clock; | |
8154 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2; | |
8155 | int refclk = 100000; | |
8156 | ||
a580516d | 8157 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
8158 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
8159 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
8160 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
8161 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
a580516d | 8162 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
8163 | |
8164 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
8165 | clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff); | |
8166 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; | |
8167 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
8168 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
8169 | ||
8170 | chv_clock(refclk, &clock); | |
8171 | ||
8172 | /* clock.dot is the fast clock */ | |
8173 | pipe_config->port_clock = clock.dot / 5; | |
8174 | } | |
8175 | ||
0e8ffe1b | 8176 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8177 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8178 | { |
8179 | struct drm_device *dev = crtc->base.dev; | |
8180 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8181 | uint32_t tmp; | |
8182 | ||
f458ebbc DV |
8183 | if (!intel_display_power_is_enabled(dev_priv, |
8184 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
b5482bd0 ID |
8185 | return false; |
8186 | ||
e143a21c | 8187 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 8188 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 8189 | |
0e8ffe1b DV |
8190 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8191 | if (!(tmp & PIPECONF_ENABLE)) | |
8192 | return false; | |
8193 | ||
42571aef VS |
8194 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
8195 | switch (tmp & PIPECONF_BPC_MASK) { | |
8196 | case PIPECONF_6BPC: | |
8197 | pipe_config->pipe_bpp = 18; | |
8198 | break; | |
8199 | case PIPECONF_8BPC: | |
8200 | pipe_config->pipe_bpp = 24; | |
8201 | break; | |
8202 | case PIPECONF_10BPC: | |
8203 | pipe_config->pipe_bpp = 30; | |
8204 | break; | |
8205 | default: | |
8206 | break; | |
8207 | } | |
8208 | } | |
8209 | ||
b5a9fa09 DV |
8210 | if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
8211 | pipe_config->limited_color_range = true; | |
8212 | ||
282740f7 VS |
8213 | if (INTEL_INFO(dev)->gen < 4) |
8214 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
8215 | ||
1bd1bd80 DV |
8216 | intel_get_pipe_timings(crtc, pipe_config); |
8217 | ||
2fa2fe9a DV |
8218 | i9xx_get_pfit_config(crtc, pipe_config); |
8219 | ||
6c49f241 DV |
8220 | if (INTEL_INFO(dev)->gen >= 4) { |
8221 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
8222 | pipe_config->pixel_multiplier = | |
8223 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
8224 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 8225 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
8226 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
8227 | tmp = I915_READ(DPLL(crtc->pipe)); | |
8228 | pipe_config->pixel_multiplier = | |
8229 | ((tmp & SDVO_MULTIPLIER_MASK) | |
8230 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
8231 | } else { | |
8232 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
8233 | * port and will be fixed up in the encoder->get_config | |
8234 | * function. */ | |
8235 | pipe_config->pixel_multiplier = 1; | |
8236 | } | |
8bcc2795 DV |
8237 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
8238 | if (!IS_VALLEYVIEW(dev)) { | |
1c4e0274 VS |
8239 | /* |
8240 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
8241 | * on 830. Filter it out here so that we don't | |
8242 | * report errors due to that. | |
8243 | */ | |
8244 | if (IS_I830(dev)) | |
8245 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
8246 | ||
8bcc2795 DV |
8247 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
8248 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
8249 | } else { |
8250 | /* Mask out read-only status bits. */ | |
8251 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
8252 | DPLL_PORTC_READY_MASK | | |
8253 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 8254 | } |
6c49f241 | 8255 | |
70b23a98 VS |
8256 | if (IS_CHERRYVIEW(dev)) |
8257 | chv_crtc_clock_get(crtc, pipe_config); | |
8258 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
8259 | vlv_crtc_clock_get(crtc, pipe_config); |
8260 | else | |
8261 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 8262 | |
0e8ffe1b DV |
8263 | return true; |
8264 | } | |
8265 | ||
dde86e2d | 8266 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
8267 | { |
8268 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 8269 | struct intel_encoder *encoder; |
74cfd7ac | 8270 | u32 val, final; |
13d83a67 | 8271 | bool has_lvds = false; |
199e5d79 | 8272 | bool has_cpu_edp = false; |
199e5d79 | 8273 | bool has_panel = false; |
99eb6a01 KP |
8274 | bool has_ck505 = false; |
8275 | bool can_ssc = false; | |
13d83a67 JB |
8276 | |
8277 | /* We need to take the global config into account */ | |
b2784e15 | 8278 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
8279 | switch (encoder->type) { |
8280 | case INTEL_OUTPUT_LVDS: | |
8281 | has_panel = true; | |
8282 | has_lvds = true; | |
8283 | break; | |
8284 | case INTEL_OUTPUT_EDP: | |
8285 | has_panel = true; | |
2de6905f | 8286 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
8287 | has_cpu_edp = true; |
8288 | break; | |
6847d71b PZ |
8289 | default: |
8290 | break; | |
13d83a67 JB |
8291 | } |
8292 | } | |
8293 | ||
99eb6a01 | 8294 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 8295 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
8296 | can_ssc = has_ck505; |
8297 | } else { | |
8298 | has_ck505 = false; | |
8299 | can_ssc = true; | |
8300 | } | |
8301 | ||
2de6905f ID |
8302 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
8303 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
8304 | |
8305 | /* Ironlake: try to setup display ref clock before DPLL | |
8306 | * enabling. This is only under driver's control after | |
8307 | * PCH B stepping, previous chipset stepping should be | |
8308 | * ignoring this setting. | |
8309 | */ | |
74cfd7ac CW |
8310 | val = I915_READ(PCH_DREF_CONTROL); |
8311 | ||
8312 | /* As we must carefully and slowly disable/enable each source in turn, | |
8313 | * compute the final state we want first and check if we need to | |
8314 | * make any changes at all. | |
8315 | */ | |
8316 | final = val; | |
8317 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
8318 | if (has_ck505) | |
8319 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
8320 | else | |
8321 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
8322 | ||
8323 | final &= ~DREF_SSC_SOURCE_MASK; | |
8324 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
8325 | final &= ~DREF_SSC1_ENABLE; | |
8326 | ||
8327 | if (has_panel) { | |
8328 | final |= DREF_SSC_SOURCE_ENABLE; | |
8329 | ||
8330 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8331 | final |= DREF_SSC1_ENABLE; | |
8332 | ||
8333 | if (has_cpu_edp) { | |
8334 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8335 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
8336 | else | |
8337 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
8338 | } else | |
8339 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8340 | } else { | |
8341 | final |= DREF_SSC_SOURCE_DISABLE; | |
8342 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8343 | } | |
8344 | ||
8345 | if (final == val) | |
8346 | return; | |
8347 | ||
13d83a67 | 8348 | /* Always enable nonspread source */ |
74cfd7ac | 8349 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 8350 | |
99eb6a01 | 8351 | if (has_ck505) |
74cfd7ac | 8352 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 8353 | else |
74cfd7ac | 8354 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 8355 | |
199e5d79 | 8356 | if (has_panel) { |
74cfd7ac CW |
8357 | val &= ~DREF_SSC_SOURCE_MASK; |
8358 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 8359 | |
199e5d79 | 8360 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 8361 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8362 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 8363 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 8364 | } else |
74cfd7ac | 8365 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
8366 | |
8367 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 8368 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8369 | POSTING_READ(PCH_DREF_CONTROL); |
8370 | udelay(200); | |
8371 | ||
74cfd7ac | 8372 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
8373 | |
8374 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 8375 | if (has_cpu_edp) { |
99eb6a01 | 8376 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8377 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 8378 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 8379 | } else |
74cfd7ac | 8380 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 8381 | } else |
74cfd7ac | 8382 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8383 | |
74cfd7ac | 8384 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8385 | POSTING_READ(PCH_DREF_CONTROL); |
8386 | udelay(200); | |
8387 | } else { | |
8388 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
8389 | ||
74cfd7ac | 8390 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
8391 | |
8392 | /* Turn off CPU output */ | |
74cfd7ac | 8393 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8394 | |
74cfd7ac | 8395 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8396 | POSTING_READ(PCH_DREF_CONTROL); |
8397 | udelay(200); | |
8398 | ||
8399 | /* Turn off the SSC source */ | |
74cfd7ac CW |
8400 | val &= ~DREF_SSC_SOURCE_MASK; |
8401 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
8402 | |
8403 | /* Turn off SSC1 */ | |
74cfd7ac | 8404 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 8405 | |
74cfd7ac | 8406 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
8407 | POSTING_READ(PCH_DREF_CONTROL); |
8408 | udelay(200); | |
8409 | } | |
74cfd7ac CW |
8410 | |
8411 | BUG_ON(val != final); | |
13d83a67 JB |
8412 | } |
8413 | ||
f31f2d55 | 8414 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 8415 | { |
f31f2d55 | 8416 | uint32_t tmp; |
dde86e2d | 8417 | |
0ff066a9 PZ |
8418 | tmp = I915_READ(SOUTH_CHICKEN2); |
8419 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
8420 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8421 | |
0ff066a9 PZ |
8422 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
8423 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
8424 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 8425 | |
0ff066a9 PZ |
8426 | tmp = I915_READ(SOUTH_CHICKEN2); |
8427 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
8428 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8429 | |
0ff066a9 PZ |
8430 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
8431 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
8432 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
8433 | } |
8434 | ||
8435 | /* WaMPhyProgramming:hsw */ | |
8436 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
8437 | { | |
8438 | uint32_t tmp; | |
dde86e2d PZ |
8439 | |
8440 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
8441 | tmp &= ~(0xFF << 24); | |
8442 | tmp |= (0x12 << 24); | |
8443 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
8444 | ||
dde86e2d PZ |
8445 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
8446 | tmp |= (1 << 11); | |
8447 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
8448 | ||
8449 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
8450 | tmp |= (1 << 11); | |
8451 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
8452 | ||
dde86e2d PZ |
8453 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
8454 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8455 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
8456 | ||
8457 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
8458 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8459 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
8460 | ||
0ff066a9 PZ |
8461 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
8462 | tmp &= ~(7 << 13); | |
8463 | tmp |= (5 << 13); | |
8464 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 8465 | |
0ff066a9 PZ |
8466 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
8467 | tmp &= ~(7 << 13); | |
8468 | tmp |= (5 << 13); | |
8469 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
8470 | |
8471 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
8472 | tmp &= ~0xFF; | |
8473 | tmp |= 0x1C; | |
8474 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
8475 | ||
8476 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
8477 | tmp &= ~0xFF; | |
8478 | tmp |= 0x1C; | |
8479 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
8480 | ||
8481 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
8482 | tmp &= ~(0xFF << 16); | |
8483 | tmp |= (0x1C << 16); | |
8484 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
8485 | ||
8486 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
8487 | tmp &= ~(0xFF << 16); | |
8488 | tmp |= (0x1C << 16); | |
8489 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
8490 | ||
0ff066a9 PZ |
8491 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
8492 | tmp |= (1 << 27); | |
8493 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 8494 | |
0ff066a9 PZ |
8495 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
8496 | tmp |= (1 << 27); | |
8497 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 8498 | |
0ff066a9 PZ |
8499 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
8500 | tmp &= ~(0xF << 28); | |
8501 | tmp |= (4 << 28); | |
8502 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 8503 | |
0ff066a9 PZ |
8504 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
8505 | tmp &= ~(0xF << 28); | |
8506 | tmp |= (4 << 28); | |
8507 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
8508 | } |
8509 | ||
2fa86a1f PZ |
8510 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
8511 | * Programming" based on the parameters passed: | |
8512 | * - Sequence to enable CLKOUT_DP | |
8513 | * - Sequence to enable CLKOUT_DP without spread | |
8514 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
8515 | */ | |
8516 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
8517 | bool with_fdi) | |
f31f2d55 PZ |
8518 | { |
8519 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
8520 | uint32_t reg, tmp; |
8521 | ||
8522 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
8523 | with_spread = true; | |
8524 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && | |
8525 | with_fdi, "LP PCH doesn't have FDI\n")) | |
8526 | with_fdi = false; | |
f31f2d55 | 8527 | |
a580516d | 8528 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
8529 | |
8530 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8531 | tmp &= ~SBI_SSCCTL_DISABLE; | |
8532 | tmp |= SBI_SSCCTL_PATHALT; | |
8533 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8534 | ||
8535 | udelay(24); | |
8536 | ||
2fa86a1f PZ |
8537 | if (with_spread) { |
8538 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8539 | tmp &= ~SBI_SSCCTL_PATHALT; | |
8540 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 8541 | |
2fa86a1f PZ |
8542 | if (with_fdi) { |
8543 | lpt_reset_fdi_mphy(dev_priv); | |
8544 | lpt_program_fdi_mphy(dev_priv); | |
8545 | } | |
8546 | } | |
dde86e2d | 8547 | |
2fa86a1f PZ |
8548 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
8549 | SBI_GEN0 : SBI_DBUFF0; | |
8550 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
8551 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8552 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 8553 | |
a580516d | 8554 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
8555 | } |
8556 | ||
47701c3b PZ |
8557 | /* Sequence to disable CLKOUT_DP */ |
8558 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
8559 | { | |
8560 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8561 | uint32_t reg, tmp; | |
8562 | ||
a580516d | 8563 | mutex_lock(&dev_priv->sb_lock); |
47701c3b PZ |
8564 | |
8565 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? | |
8566 | SBI_GEN0 : SBI_DBUFF0; | |
8567 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
8568 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8569 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
8570 | ||
8571 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8572 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
8573 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
8574 | tmp |= SBI_SSCCTL_PATHALT; | |
8575 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8576 | udelay(32); | |
8577 | } | |
8578 | tmp |= SBI_SSCCTL_DISABLE; | |
8579 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8580 | } | |
8581 | ||
a580516d | 8582 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
8583 | } |
8584 | ||
bf8fa3d3 PZ |
8585 | static void lpt_init_pch_refclk(struct drm_device *dev) |
8586 | { | |
bf8fa3d3 PZ |
8587 | struct intel_encoder *encoder; |
8588 | bool has_vga = false; | |
8589 | ||
b2784e15 | 8590 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
8591 | switch (encoder->type) { |
8592 | case INTEL_OUTPUT_ANALOG: | |
8593 | has_vga = true; | |
8594 | break; | |
6847d71b PZ |
8595 | default: |
8596 | break; | |
bf8fa3d3 PZ |
8597 | } |
8598 | } | |
8599 | ||
47701c3b PZ |
8600 | if (has_vga) |
8601 | lpt_enable_clkout_dp(dev, true, true); | |
8602 | else | |
8603 | lpt_disable_clkout_dp(dev); | |
bf8fa3d3 PZ |
8604 | } |
8605 | ||
dde86e2d PZ |
8606 | /* |
8607 | * Initialize reference clocks when the driver loads | |
8608 | */ | |
8609 | void intel_init_pch_refclk(struct drm_device *dev) | |
8610 | { | |
8611 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
8612 | ironlake_init_pch_refclk(dev); | |
8613 | else if (HAS_PCH_LPT(dev)) | |
8614 | lpt_init_pch_refclk(dev); | |
8615 | } | |
8616 | ||
55bb9992 | 8617 | static int ironlake_get_refclk(struct intel_crtc_state *crtc_state) |
d9d444cb | 8618 | { |
55bb9992 | 8619 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d9d444cb | 8620 | struct drm_i915_private *dev_priv = dev->dev_private; |
55bb9992 | 8621 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8622 | struct drm_connector *connector; |
55bb9992 | 8623 | struct drm_connector_state *connector_state; |
d9d444cb | 8624 | struct intel_encoder *encoder; |
55bb9992 | 8625 | int num_connectors = 0, i; |
d9d444cb JB |
8626 | bool is_lvds = false; |
8627 | ||
da3ced29 | 8628 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8629 | if (connector_state->crtc != crtc_state->base.crtc) |
8630 | continue; | |
8631 | ||
8632 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8633 | ||
d9d444cb JB |
8634 | switch (encoder->type) { |
8635 | case INTEL_OUTPUT_LVDS: | |
8636 | is_lvds = true; | |
8637 | break; | |
6847d71b PZ |
8638 | default: |
8639 | break; | |
d9d444cb JB |
8640 | } |
8641 | num_connectors++; | |
8642 | } | |
8643 | ||
8644 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 8645 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 8646 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 8647 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
8648 | } |
8649 | ||
8650 | return 120000; | |
8651 | } | |
8652 | ||
6ff93609 | 8653 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 8654 | { |
c8203565 | 8655 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
8656 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8657 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
8658 | uint32_t val; |
8659 | ||
78114071 | 8660 | val = 0; |
c8203565 | 8661 | |
6e3c9717 | 8662 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 8663 | case 18: |
dfd07d72 | 8664 | val |= PIPECONF_6BPC; |
c8203565 PZ |
8665 | break; |
8666 | case 24: | |
dfd07d72 | 8667 | val |= PIPECONF_8BPC; |
c8203565 PZ |
8668 | break; |
8669 | case 30: | |
dfd07d72 | 8670 | val |= PIPECONF_10BPC; |
c8203565 PZ |
8671 | break; |
8672 | case 36: | |
dfd07d72 | 8673 | val |= PIPECONF_12BPC; |
c8203565 PZ |
8674 | break; |
8675 | default: | |
cc769b62 PZ |
8676 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
8677 | BUG(); | |
c8203565 PZ |
8678 | } |
8679 | ||
6e3c9717 | 8680 | if (intel_crtc->config->dither) |
c8203565 PZ |
8681 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8682 | ||
6e3c9717 | 8683 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
8684 | val |= PIPECONF_INTERLACED_ILK; |
8685 | else | |
8686 | val |= PIPECONF_PROGRESSIVE; | |
8687 | ||
6e3c9717 | 8688 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 8689 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 8690 | |
c8203565 PZ |
8691 | I915_WRITE(PIPECONF(pipe), val); |
8692 | POSTING_READ(PIPECONF(pipe)); | |
8693 | } | |
8694 | ||
86d3efce VS |
8695 | /* |
8696 | * Set up the pipe CSC unit. | |
8697 | * | |
8698 | * Currently only full range RGB to limited range RGB conversion | |
8699 | * is supported, but eventually this should handle various | |
8700 | * RGB<->YCbCr scenarios as well. | |
8701 | */ | |
50f3b016 | 8702 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
8703 | { |
8704 | struct drm_device *dev = crtc->dev; | |
8705 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8706 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8707 | int pipe = intel_crtc->pipe; | |
8708 | uint16_t coeff = 0x7800; /* 1.0 */ | |
8709 | ||
8710 | /* | |
8711 | * TODO: Check what kind of values actually come out of the pipe | |
8712 | * with these coeff/postoff values and adjust to get the best | |
8713 | * accuracy. Perhaps we even need to take the bpc value into | |
8714 | * consideration. | |
8715 | */ | |
8716 | ||
6e3c9717 | 8717 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8718 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
8719 | ||
8720 | /* | |
8721 | * GY/GU and RY/RU should be the other way around according | |
8722 | * to BSpec, but reality doesn't agree. Just set them up in | |
8723 | * a way that results in the correct picture. | |
8724 | */ | |
8725 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
8726 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
8727 | ||
8728 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
8729 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
8730 | ||
8731 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
8732 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
8733 | ||
8734 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
8735 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
8736 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
8737 | ||
8738 | if (INTEL_INFO(dev)->gen > 6) { | |
8739 | uint16_t postoff = 0; | |
8740 | ||
6e3c9717 | 8741 | if (intel_crtc->config->limited_color_range) |
32cf0cb0 | 8742 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
8743 | |
8744 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
8745 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
8746 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
8747 | ||
8748 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
8749 | } else { | |
8750 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
8751 | ||
6e3c9717 | 8752 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8753 | mode |= CSC_BLACK_SCREEN_OFFSET; |
8754 | ||
8755 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
8756 | } | |
8757 | } | |
8758 | ||
6ff93609 | 8759 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8760 | { |
756f85cf PZ |
8761 | struct drm_device *dev = crtc->dev; |
8762 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 8763 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 8764 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 8765 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee2b0b38 PZ |
8766 | uint32_t val; |
8767 | ||
3eff4faa | 8768 | val = 0; |
ee2b0b38 | 8769 | |
6e3c9717 | 8770 | if (IS_HASWELL(dev) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8771 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8772 | ||
6e3c9717 | 8773 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8774 | val |= PIPECONF_INTERLACED_ILK; |
8775 | else | |
8776 | val |= PIPECONF_PROGRESSIVE; | |
8777 | ||
702e7a56 PZ |
8778 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8779 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
8780 | |
8781 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
8782 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf | 8783 | |
3cdf122c | 8784 | if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { |
756f85cf PZ |
8785 | val = 0; |
8786 | ||
6e3c9717 | 8787 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8788 | case 18: |
8789 | val |= PIPEMISC_DITHER_6_BPC; | |
8790 | break; | |
8791 | case 24: | |
8792 | val |= PIPEMISC_DITHER_8_BPC; | |
8793 | break; | |
8794 | case 30: | |
8795 | val |= PIPEMISC_DITHER_10_BPC; | |
8796 | break; | |
8797 | case 36: | |
8798 | val |= PIPEMISC_DITHER_12_BPC; | |
8799 | break; | |
8800 | default: | |
8801 | /* Case prevented by pipe_config_set_bpp. */ | |
8802 | BUG(); | |
8803 | } | |
8804 | ||
6e3c9717 | 8805 | if (intel_crtc->config->dither) |
756f85cf PZ |
8806 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8807 | ||
8808 | I915_WRITE(PIPEMISC(pipe), val); | |
8809 | } | |
ee2b0b38 PZ |
8810 | } |
8811 | ||
6591c6e4 | 8812 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
190f68c5 | 8813 | struct intel_crtc_state *crtc_state, |
6591c6e4 PZ |
8814 | intel_clock_t *clock, |
8815 | bool *has_reduced_clock, | |
8816 | intel_clock_t *reduced_clock) | |
8817 | { | |
8818 | struct drm_device *dev = crtc->dev; | |
8819 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6591c6e4 | 8820 | int refclk; |
d4906093 | 8821 | const intel_limit_t *limit; |
a16af721 | 8822 | bool ret, is_lvds = false; |
79e53945 | 8823 | |
a93e255f | 8824 | is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS); |
79e53945 | 8825 | |
55bb9992 | 8826 | refclk = ironlake_get_refclk(crtc_state); |
79e53945 | 8827 | |
d4906093 ML |
8828 | /* |
8829 | * Returns a set of divisors for the desired target clock with the given | |
8830 | * refclk, or FALSE. The returned values represent the clock equation: | |
8831 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
8832 | */ | |
a93e255f ACO |
8833 | limit = intel_limit(crtc_state, refclk); |
8834 | ret = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 8835 | crtc_state->port_clock, |
ee9300bb | 8836 | refclk, NULL, clock); |
6591c6e4 PZ |
8837 | if (!ret) |
8838 | return false; | |
cda4b7d3 | 8839 | |
ddc9003c | 8840 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
8841 | /* |
8842 | * Ensure we match the reduced clock's P to the target clock. | |
8843 | * If the clocks don't match, we can't switch the display clock | |
8844 | * by using the FP0/FP1. In such case we will disable the LVDS | |
8845 | * downclock feature. | |
8846 | */ | |
ee9300bb | 8847 | *has_reduced_clock = |
a93e255f | 8848 | dev_priv->display.find_dpll(limit, crtc_state, |
ee9300bb DV |
8849 | dev_priv->lvds_downclock, |
8850 | refclk, clock, | |
8851 | reduced_clock); | |
652c393a | 8852 | } |
61e9653f | 8853 | |
6591c6e4 PZ |
8854 | return true; |
8855 | } | |
8856 | ||
d4b1931c PZ |
8857 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
8858 | { | |
8859 | /* | |
8860 | * Account for spread spectrum to avoid | |
8861 | * oversubscribing the link. Max center spread | |
8862 | * is 2.5%; use 5% for safety's sake. | |
8863 | */ | |
8864 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 8865 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
8866 | } |
8867 | ||
7429e9d4 | 8868 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 8869 | { |
7429e9d4 | 8870 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
8871 | } |
8872 | ||
de13a2e3 | 8873 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
190f68c5 | 8874 | struct intel_crtc_state *crtc_state, |
7429e9d4 | 8875 | u32 *fp, |
9a7c7890 | 8876 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 8877 | { |
de13a2e3 | 8878 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
8879 | struct drm_device *dev = crtc->dev; |
8880 | struct drm_i915_private *dev_priv = dev->dev_private; | |
55bb9992 | 8881 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8882 | struct drm_connector *connector; |
55bb9992 ACO |
8883 | struct drm_connector_state *connector_state; |
8884 | struct intel_encoder *encoder; | |
de13a2e3 | 8885 | uint32_t dpll; |
55bb9992 | 8886 | int factor, num_connectors = 0, i; |
09ede541 | 8887 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 8888 | |
da3ced29 | 8889 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8890 | if (connector_state->crtc != crtc_state->base.crtc) |
8891 | continue; | |
8892 | ||
8893 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8894 | ||
8895 | switch (encoder->type) { | |
79e53945 JB |
8896 | case INTEL_OUTPUT_LVDS: |
8897 | is_lvds = true; | |
8898 | break; | |
8899 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 8900 | case INTEL_OUTPUT_HDMI: |
79e53945 | 8901 | is_sdvo = true; |
79e53945 | 8902 | break; |
6847d71b PZ |
8903 | default: |
8904 | break; | |
79e53945 | 8905 | } |
43565a06 | 8906 | |
c751ce4f | 8907 | num_connectors++; |
79e53945 | 8908 | } |
79e53945 | 8909 | |
c1858123 | 8910 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
8911 | factor = 21; |
8912 | if (is_lvds) { | |
8913 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 8914 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 8915 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 8916 | factor = 25; |
190f68c5 | 8917 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 8918 | factor = 20; |
c1858123 | 8919 | |
190f68c5 | 8920 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
7d0ac5b7 | 8921 | *fp |= FP_CB_TUNE; |
2c07245f | 8922 | |
9a7c7890 DV |
8923 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
8924 | *fp2 |= FP_CB_TUNE; | |
8925 | ||
5eddb70b | 8926 | dpll = 0; |
2c07245f | 8927 | |
a07d6787 EA |
8928 | if (is_lvds) |
8929 | dpll |= DPLLB_MODE_LVDS; | |
8930 | else | |
8931 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 8932 | |
190f68c5 | 8933 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8934 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f DV |
8935 | |
8936 | if (is_sdvo) | |
4a33e48d | 8937 | dpll |= DPLL_SDVO_HIGH_SPEED; |
190f68c5 | 8938 | if (crtc_state->has_dp_encoder) |
4a33e48d | 8939 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 8940 | |
a07d6787 | 8941 | /* compute bitmask from p1 value */ |
190f68c5 | 8942 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 8943 | /* also FPA1 */ |
190f68c5 | 8944 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 8945 | |
190f68c5 | 8946 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
8947 | case 5: |
8948 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8949 | break; | |
8950 | case 7: | |
8951 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8952 | break; | |
8953 | case 10: | |
8954 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8955 | break; | |
8956 | case 14: | |
8957 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8958 | break; | |
79e53945 JB |
8959 | } |
8960 | ||
b4c09f3b | 8961 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 8962 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
8963 | else |
8964 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8965 | ||
959e16d6 | 8966 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
8967 | } |
8968 | ||
190f68c5 ACO |
8969 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
8970 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 8971 | { |
c7653199 | 8972 | struct drm_device *dev = crtc->base.dev; |
de13a2e3 | 8973 | intel_clock_t clock, reduced_clock; |
cbbab5bd | 8974 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 8975 | bool ok, has_reduced_clock = false; |
8b47047b | 8976 | bool is_lvds = false; |
e2b78267 | 8977 | struct intel_shared_dpll *pll; |
de13a2e3 | 8978 | |
dd3cd74a ACO |
8979 | memset(&crtc_state->dpll_hw_state, 0, |
8980 | sizeof(crtc_state->dpll_hw_state)); | |
8981 | ||
409ee761 | 8982 | is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS); |
79e53945 | 8983 | |
5dc5298b PZ |
8984 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
8985 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 8986 | |
190f68c5 | 8987 | ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock, |
de13a2e3 | 8988 | &has_reduced_clock, &reduced_clock); |
190f68c5 | 8989 | if (!ok && !crtc_state->clock_set) { |
de13a2e3 PZ |
8990 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
8991 | return -EINVAL; | |
79e53945 | 8992 | } |
f47709a9 | 8993 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
8994 | if (!crtc_state->clock_set) { |
8995 | crtc_state->dpll.n = clock.n; | |
8996 | crtc_state->dpll.m1 = clock.m1; | |
8997 | crtc_state->dpll.m2 = clock.m2; | |
8998 | crtc_state->dpll.p1 = clock.p1; | |
8999 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 9000 | } |
79e53945 | 9001 | |
5dc5298b | 9002 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
190f68c5 ACO |
9003 | if (crtc_state->has_pch_encoder) { |
9004 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); | |
cbbab5bd | 9005 | if (has_reduced_clock) |
7429e9d4 | 9006 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 9007 | |
190f68c5 | 9008 | dpll = ironlake_compute_dpll(crtc, crtc_state, |
cbbab5bd DV |
9009 | &fp, &reduced_clock, |
9010 | has_reduced_clock ? &fp2 : NULL); | |
9011 | ||
190f68c5 ACO |
9012 | crtc_state->dpll_hw_state.dpll = dpll; |
9013 | crtc_state->dpll_hw_state.fp0 = fp; | |
66e985c0 | 9014 | if (has_reduced_clock) |
190f68c5 | 9015 | crtc_state->dpll_hw_state.fp1 = fp2; |
66e985c0 | 9016 | else |
190f68c5 | 9017 | crtc_state->dpll_hw_state.fp1 = fp; |
66e985c0 | 9018 | |
190f68c5 | 9019 | pll = intel_get_shared_dpll(crtc, crtc_state); |
ee7b9f93 | 9020 | if (pll == NULL) { |
84f44ce7 | 9021 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
c7653199 | 9022 | pipe_name(crtc->pipe)); |
4b645f14 JB |
9023 | return -EINVAL; |
9024 | } | |
3fb37703 | 9025 | } |
79e53945 | 9026 | |
ab585dea | 9027 | if (is_lvds && has_reduced_clock) |
c7653199 | 9028 | crtc->lowfreq_avail = true; |
bcd644e0 | 9029 | else |
c7653199 | 9030 | crtc->lowfreq_avail = false; |
e2b78267 | 9031 | |
c8f7a0db | 9032 | return 0; |
79e53945 JB |
9033 | } |
9034 | ||
eb14cb74 VS |
9035 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
9036 | struct intel_link_m_n *m_n) | |
9037 | { | |
9038 | struct drm_device *dev = crtc->base.dev; | |
9039 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9040 | enum pipe pipe = crtc->pipe; | |
9041 | ||
9042 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
9043 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
9044 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9045 | & ~TU_SIZE_MASK; | |
9046 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
9047 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9048 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9049 | } | |
9050 | ||
9051 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
9052 | enum transcoder transcoder, | |
b95af8be VK |
9053 | struct intel_link_m_n *m_n, |
9054 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
9055 | { |
9056 | struct drm_device *dev = crtc->base.dev; | |
9057 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 9058 | enum pipe pipe = crtc->pipe; |
72419203 | 9059 | |
eb14cb74 VS |
9060 | if (INTEL_INFO(dev)->gen >= 5) { |
9061 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
9062 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
9063 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
9064 | & ~TU_SIZE_MASK; | |
9065 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
9066 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
9067 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
9068 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
9069 | * gen < 8) and if DRRS is supported (to make sure the | |
9070 | * registers are not unnecessarily read). | |
9071 | */ | |
9072 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 9073 | crtc->config->has_drrs) { |
b95af8be VK |
9074 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
9075 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
9076 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
9077 | & ~TU_SIZE_MASK; | |
9078 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
9079 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
9080 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9081 | } | |
eb14cb74 VS |
9082 | } else { |
9083 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
9084 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
9085 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9086 | & ~TU_SIZE_MASK; | |
9087 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
9088 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9089 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9090 | } | |
9091 | } | |
9092 | ||
9093 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 9094 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 9095 | { |
681a8504 | 9096 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
9097 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
9098 | else | |
9099 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
9100 | &pipe_config->dp_m_n, |
9101 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 9102 | } |
72419203 | 9103 | |
eb14cb74 | 9104 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 9105 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
9106 | { |
9107 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 9108 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
9109 | } |
9110 | ||
bd2e244f | 9111 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9112 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
9113 | { |
9114 | struct drm_device *dev = crtc->base.dev; | |
9115 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a1b2278e CK |
9116 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
9117 | uint32_t ps_ctrl = 0; | |
9118 | int id = -1; | |
9119 | int i; | |
bd2e244f | 9120 | |
a1b2278e CK |
9121 | /* find scaler attached to this pipe */ |
9122 | for (i = 0; i < crtc->num_scalers; i++) { | |
9123 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
9124 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
9125 | id = i; | |
9126 | pipe_config->pch_pfit.enabled = true; | |
9127 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
9128 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
9129 | break; | |
9130 | } | |
9131 | } | |
bd2e244f | 9132 | |
a1b2278e CK |
9133 | scaler_state->scaler_id = id; |
9134 | if (id >= 0) { | |
9135 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
9136 | } else { | |
9137 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
9138 | } |
9139 | } | |
9140 | ||
5724dbd1 DL |
9141 | static void |
9142 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
9143 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
9144 | { |
9145 | struct drm_device *dev = crtc->base.dev; | |
9146 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40f46283 | 9147 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
9148 | int pipe = crtc->pipe; |
9149 | int fourcc, pixel_format; | |
6761dd31 | 9150 | unsigned int aligned_height; |
bc8d7dff | 9151 | struct drm_framebuffer *fb; |
1b842c89 | 9152 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 9153 | |
d9806c9f | 9154 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9155 | if (!intel_fb) { |
bc8d7dff DL |
9156 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9157 | return; | |
9158 | } | |
9159 | ||
1b842c89 DL |
9160 | fb = &intel_fb->base; |
9161 | ||
bc8d7dff | 9162 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
9163 | if (!(val & PLANE_CTL_ENABLE)) |
9164 | goto error; | |
9165 | ||
bc8d7dff DL |
9166 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
9167 | fourcc = skl_format_to_fourcc(pixel_format, | |
9168 | val & PLANE_CTL_ORDER_RGBX, | |
9169 | val & PLANE_CTL_ALPHA_MASK); | |
9170 | fb->pixel_format = fourcc; | |
9171 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
9172 | ||
40f46283 DL |
9173 | tiling = val & PLANE_CTL_TILED_MASK; |
9174 | switch (tiling) { | |
9175 | case PLANE_CTL_TILED_LINEAR: | |
9176 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
9177 | break; | |
9178 | case PLANE_CTL_TILED_X: | |
9179 | plane_config->tiling = I915_TILING_X; | |
9180 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
9181 | break; | |
9182 | case PLANE_CTL_TILED_Y: | |
9183 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
9184 | break; | |
9185 | case PLANE_CTL_TILED_YF: | |
9186 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
9187 | break; | |
9188 | default: | |
9189 | MISSING_CASE(tiling); | |
9190 | goto error; | |
9191 | } | |
9192 | ||
bc8d7dff DL |
9193 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
9194 | plane_config->base = base; | |
9195 | ||
9196 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
9197 | ||
9198 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
9199 | fb->height = ((val >> 16) & 0xfff) + 1; | |
9200 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
9201 | ||
9202 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
40f46283 DL |
9203 | stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0], |
9204 | fb->pixel_format); | |
bc8d7dff DL |
9205 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
9206 | ||
9207 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
9208 | fb->pixel_format, |
9209 | fb->modifier[0]); | |
bc8d7dff | 9210 | |
f37b5c2b | 9211 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
9212 | |
9213 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
9214 | pipe_name(pipe), fb->width, fb->height, | |
9215 | fb->bits_per_pixel, base, fb->pitches[0], | |
9216 | plane_config->size); | |
9217 | ||
2d14030b | 9218 | plane_config->fb = intel_fb; |
bc8d7dff DL |
9219 | return; |
9220 | ||
9221 | error: | |
9222 | kfree(fb); | |
9223 | } | |
9224 | ||
2fa2fe9a | 9225 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9226 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
9227 | { |
9228 | struct drm_device *dev = crtc->base.dev; | |
9229 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9230 | uint32_t tmp; | |
9231 | ||
9232 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
9233 | ||
9234 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 9235 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
9236 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
9237 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
9238 | |
9239 | /* We currently do not free assignements of panel fitters on | |
9240 | * ivb/hsw (since we don't use the higher upscaling modes which | |
9241 | * differentiates them) so just WARN about this case for now. */ | |
9242 | if (IS_GEN7(dev)) { | |
9243 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
9244 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
9245 | } | |
2fa2fe9a | 9246 | } |
79e53945 JB |
9247 | } |
9248 | ||
5724dbd1 DL |
9249 | static void |
9250 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
9251 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
9252 | { |
9253 | struct drm_device *dev = crtc->base.dev; | |
9254 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9255 | u32 val, base, offset; | |
aeee5a49 | 9256 | int pipe = crtc->pipe; |
4c6baa59 | 9257 | int fourcc, pixel_format; |
6761dd31 | 9258 | unsigned int aligned_height; |
b113d5ee | 9259 | struct drm_framebuffer *fb; |
1b842c89 | 9260 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 9261 | |
42a7b088 DL |
9262 | val = I915_READ(DSPCNTR(pipe)); |
9263 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
9264 | return; | |
9265 | ||
d9806c9f | 9266 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9267 | if (!intel_fb) { |
4c6baa59 JB |
9268 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9269 | return; | |
9270 | } | |
9271 | ||
1b842c89 DL |
9272 | fb = &intel_fb->base; |
9273 | ||
18c5247e DV |
9274 | if (INTEL_INFO(dev)->gen >= 4) { |
9275 | if (val & DISPPLANE_TILED) { | |
49af449b | 9276 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
9277 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
9278 | } | |
9279 | } | |
4c6baa59 JB |
9280 | |
9281 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 9282 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
9283 | fb->pixel_format = fourcc; |
9284 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 9285 | |
aeee5a49 | 9286 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 9287 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 9288 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 9289 | } else { |
49af449b | 9290 | if (plane_config->tiling) |
aeee5a49 | 9291 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 9292 | else |
aeee5a49 | 9293 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
9294 | } |
9295 | plane_config->base = base; | |
9296 | ||
9297 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
9298 | fb->width = ((val >> 16) & 0xfff) + 1; |
9299 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
9300 | |
9301 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 9302 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 9303 | |
b113d5ee | 9304 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
9305 | fb->pixel_format, |
9306 | fb->modifier[0]); | |
4c6baa59 | 9307 | |
f37b5c2b | 9308 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 9309 | |
2844a921 DL |
9310 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
9311 | pipe_name(pipe), fb->width, fb->height, | |
9312 | fb->bits_per_pixel, base, fb->pitches[0], | |
9313 | plane_config->size); | |
b113d5ee | 9314 | |
2d14030b | 9315 | plane_config->fb = intel_fb; |
4c6baa59 JB |
9316 | } |
9317 | ||
0e8ffe1b | 9318 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9319 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9320 | { |
9321 | struct drm_device *dev = crtc->base.dev; | |
9322 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9323 | uint32_t tmp; | |
9324 | ||
f458ebbc DV |
9325 | if (!intel_display_power_is_enabled(dev_priv, |
9326 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
930e8c9e PZ |
9327 | return false; |
9328 | ||
e143a21c | 9329 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 9330 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 9331 | |
0e8ffe1b DV |
9332 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
9333 | if (!(tmp & PIPECONF_ENABLE)) | |
9334 | return false; | |
9335 | ||
42571aef VS |
9336 | switch (tmp & PIPECONF_BPC_MASK) { |
9337 | case PIPECONF_6BPC: | |
9338 | pipe_config->pipe_bpp = 18; | |
9339 | break; | |
9340 | case PIPECONF_8BPC: | |
9341 | pipe_config->pipe_bpp = 24; | |
9342 | break; | |
9343 | case PIPECONF_10BPC: | |
9344 | pipe_config->pipe_bpp = 30; | |
9345 | break; | |
9346 | case PIPECONF_12BPC: | |
9347 | pipe_config->pipe_bpp = 36; | |
9348 | break; | |
9349 | default: | |
9350 | break; | |
9351 | } | |
9352 | ||
b5a9fa09 DV |
9353 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
9354 | pipe_config->limited_color_range = true; | |
9355 | ||
ab9412ba | 9356 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
9357 | struct intel_shared_dpll *pll; |
9358 | ||
88adfff1 DV |
9359 | pipe_config->has_pch_encoder = true; |
9360 | ||
627eb5a3 DV |
9361 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
9362 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9363 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
9364 | |
9365 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 9366 | |
c0d43d62 | 9367 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
9368 | pipe_config->shared_dpll = |
9369 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
9370 | } else { |
9371 | tmp = I915_READ(PCH_DPLL_SEL); | |
9372 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
9373 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
9374 | else | |
9375 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
9376 | } | |
66e985c0 DV |
9377 | |
9378 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
9379 | ||
9380 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
9381 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
9382 | |
9383 | tmp = pipe_config->dpll_hw_state.dpll; | |
9384 | pipe_config->pixel_multiplier = | |
9385 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
9386 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
9387 | |
9388 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
9389 | } else { |
9390 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
9391 | } |
9392 | ||
1bd1bd80 DV |
9393 | intel_get_pipe_timings(crtc, pipe_config); |
9394 | ||
2fa2fe9a DV |
9395 | ironlake_get_pfit_config(crtc, pipe_config); |
9396 | ||
0e8ffe1b DV |
9397 | return true; |
9398 | } | |
9399 | ||
be256dc7 PZ |
9400 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
9401 | { | |
9402 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 9403 | struct intel_crtc *crtc; |
be256dc7 | 9404 | |
d3fcc808 | 9405 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 9406 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
9407 | pipe_name(crtc->pipe)); |
9408 | ||
e2c719b7 RC |
9409 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
9410 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
9411 | I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); | |
9412 | I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
9413 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); | |
9414 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
be256dc7 | 9415 | "CPU PWM1 enabled\n"); |
c5107b87 | 9416 | if (IS_HASWELL(dev)) |
e2c719b7 | 9417 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 9418 | "CPU PWM2 enabled\n"); |
e2c719b7 | 9419 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 9420 | "PCH PWM1 enabled\n"); |
e2c719b7 | 9421 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 9422 | "Utility pin enabled\n"); |
e2c719b7 | 9423 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 9424 | |
9926ada1 PZ |
9425 | /* |
9426 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
9427 | * interrupts remain enabled. We used to check for that, but since it's | |
9428 | * gen-specific and since we only disable LCPLL after we fully disable | |
9429 | * the interrupts, the check below should be enough. | |
9430 | */ | |
e2c719b7 | 9431 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
9432 | } |
9433 | ||
9ccd5aeb PZ |
9434 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
9435 | { | |
9436 | struct drm_device *dev = dev_priv->dev; | |
9437 | ||
9438 | if (IS_HASWELL(dev)) | |
9439 | return I915_READ(D_COMP_HSW); | |
9440 | else | |
9441 | return I915_READ(D_COMP_BDW); | |
9442 | } | |
9443 | ||
3c4c9b81 PZ |
9444 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
9445 | { | |
9446 | struct drm_device *dev = dev_priv->dev; | |
9447 | ||
9448 | if (IS_HASWELL(dev)) { | |
9449 | mutex_lock(&dev_priv->rps.hw_lock); | |
9450 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
9451 | val)) | |
f475dadf | 9452 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
9453 | mutex_unlock(&dev_priv->rps.hw_lock); |
9454 | } else { | |
9ccd5aeb PZ |
9455 | I915_WRITE(D_COMP_BDW, val); |
9456 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 9457 | } |
be256dc7 PZ |
9458 | } |
9459 | ||
9460 | /* | |
9461 | * This function implements pieces of two sequences from BSpec: | |
9462 | * - Sequence for display software to disable LCPLL | |
9463 | * - Sequence for display software to allow package C8+ | |
9464 | * The steps implemented here are just the steps that actually touch the LCPLL | |
9465 | * register. Callers should take care of disabling all the display engine | |
9466 | * functions, doing the mode unset, fixing interrupts, etc. | |
9467 | */ | |
6ff58d53 PZ |
9468 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
9469 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
9470 | { |
9471 | uint32_t val; | |
9472 | ||
9473 | assert_can_disable_lcpll(dev_priv); | |
9474 | ||
9475 | val = I915_READ(LCPLL_CTL); | |
9476 | ||
9477 | if (switch_to_fclk) { | |
9478 | val |= LCPLL_CD_SOURCE_FCLK; | |
9479 | I915_WRITE(LCPLL_CTL, val); | |
9480 | ||
9481 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9482 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9483 | DRM_ERROR("Switching to FCLK failed\n"); | |
9484 | ||
9485 | val = I915_READ(LCPLL_CTL); | |
9486 | } | |
9487 | ||
9488 | val |= LCPLL_PLL_DISABLE; | |
9489 | I915_WRITE(LCPLL_CTL, val); | |
9490 | POSTING_READ(LCPLL_CTL); | |
9491 | ||
9492 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
9493 | DRM_ERROR("LCPLL still locked\n"); | |
9494 | ||
9ccd5aeb | 9495 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 9496 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 9497 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9498 | ndelay(100); |
9499 | ||
9ccd5aeb PZ |
9500 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
9501 | 1)) | |
be256dc7 PZ |
9502 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
9503 | ||
9504 | if (allow_power_down) { | |
9505 | val = I915_READ(LCPLL_CTL); | |
9506 | val |= LCPLL_POWER_DOWN_ALLOW; | |
9507 | I915_WRITE(LCPLL_CTL, val); | |
9508 | POSTING_READ(LCPLL_CTL); | |
9509 | } | |
9510 | } | |
9511 | ||
9512 | /* | |
9513 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
9514 | * source. | |
9515 | */ | |
6ff58d53 | 9516 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
9517 | { |
9518 | uint32_t val; | |
9519 | ||
9520 | val = I915_READ(LCPLL_CTL); | |
9521 | ||
9522 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
9523 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
9524 | return; | |
9525 | ||
a8a8bd54 PZ |
9526 | /* |
9527 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
9528 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 9529 | */ |
59bad947 | 9530 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 9531 | |
be256dc7 PZ |
9532 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
9533 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
9534 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 9535 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
9536 | } |
9537 | ||
9ccd5aeb | 9538 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
9539 | val |= D_COMP_COMP_FORCE; |
9540 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 9541 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9542 | |
9543 | val = I915_READ(LCPLL_CTL); | |
9544 | val &= ~LCPLL_PLL_DISABLE; | |
9545 | I915_WRITE(LCPLL_CTL, val); | |
9546 | ||
9547 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
9548 | DRM_ERROR("LCPLL not locked yet\n"); | |
9549 | ||
9550 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
9551 | val = I915_READ(LCPLL_CTL); | |
9552 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9553 | I915_WRITE(LCPLL_CTL, val); | |
9554 | ||
9555 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9556 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9557 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9558 | } | |
215733fa | 9559 | |
59bad947 | 9560 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b6283055 | 9561 | intel_update_cdclk(dev_priv->dev); |
be256dc7 PZ |
9562 | } |
9563 | ||
765dab67 PZ |
9564 | /* |
9565 | * Package states C8 and deeper are really deep PC states that can only be | |
9566 | * reached when all the devices on the system allow it, so even if the graphics | |
9567 | * device allows PC8+, it doesn't mean the system will actually get to these | |
9568 | * states. Our driver only allows PC8+ when going into runtime PM. | |
9569 | * | |
9570 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
9571 | * well is disabled and most interrupts are disabled, and these are also | |
9572 | * requirements for runtime PM. When these conditions are met, we manually do | |
9573 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
9574 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
9575 | * hang the machine. | |
9576 | * | |
9577 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
9578 | * the state of some registers, so when we come back from PC8+ we need to | |
9579 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
9580 | * need to take care of the registers kept by RC6. Notice that this happens even | |
9581 | * if we don't put the device in PCI D3 state (which is what currently happens | |
9582 | * because of the runtime PM support). | |
9583 | * | |
9584 | * For more, read "Display Sequences for Package C8" on the hardware | |
9585 | * documentation. | |
9586 | */ | |
a14cb6fc | 9587 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 9588 | { |
c67a470b PZ |
9589 | struct drm_device *dev = dev_priv->dev; |
9590 | uint32_t val; | |
9591 | ||
c67a470b PZ |
9592 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
9593 | ||
c67a470b PZ |
9594 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
9595 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
9596 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
9597 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9598 | } | |
9599 | ||
9600 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
9601 | hsw_disable_lcpll(dev_priv, true, true); |
9602 | } | |
9603 | ||
a14cb6fc | 9604 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
9605 | { |
9606 | struct drm_device *dev = dev_priv->dev; | |
9607 | uint32_t val; | |
9608 | ||
c67a470b PZ |
9609 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
9610 | ||
9611 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
9612 | lpt_init_pch_refclk(dev); |
9613 | ||
9614 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
9615 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
9616 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
9617 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9618 | } | |
9619 | ||
9620 | intel_prepare_ddi(dev); | |
c67a470b PZ |
9621 | } |
9622 | ||
a821fc46 | 9623 | static void broxton_modeset_global_resources(struct drm_atomic_state *old_state) |
f8437dd1 | 9624 | { |
a821fc46 | 9625 | struct drm_device *dev = old_state->dev; |
f8437dd1 | 9626 | struct drm_i915_private *dev_priv = dev->dev_private; |
a821fc46 | 9627 | int max_pixclk = intel_mode_max_pixclk(dev, NULL); |
f8437dd1 VK |
9628 | int req_cdclk; |
9629 | ||
9630 | /* see the comment in valleyview_modeset_global_resources */ | |
9631 | if (WARN_ON(max_pixclk < 0)) | |
9632 | return; | |
9633 | ||
9634 | req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk); | |
9635 | ||
9636 | if (req_cdclk != dev_priv->cdclk_freq) | |
9637 | broxton_set_cdclk(dev, req_cdclk); | |
9638 | } | |
9639 | ||
b432e5cf VS |
9640 | /* compute the max rate for new configuration */ |
9641 | static int ilk_max_pixel_rate(struct drm_i915_private *dev_priv) | |
9642 | { | |
9643 | struct drm_device *dev = dev_priv->dev; | |
9644 | struct intel_crtc *intel_crtc; | |
9645 | struct drm_crtc *crtc; | |
9646 | int max_pixel_rate = 0; | |
9647 | int pixel_rate; | |
9648 | ||
9649 | for_each_crtc(dev, crtc) { | |
9650 | if (!crtc->state->enable) | |
9651 | continue; | |
9652 | ||
9653 | intel_crtc = to_intel_crtc(crtc); | |
9654 | pixel_rate = ilk_pipe_pixel_rate(intel_crtc->config); | |
9655 | ||
9656 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
9657 | if (IS_BROADWELL(dev) && intel_crtc->config->ips_enabled) | |
9658 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); | |
9659 | ||
9660 | max_pixel_rate = max(max_pixel_rate, pixel_rate); | |
9661 | } | |
9662 | ||
9663 | return max_pixel_rate; | |
9664 | } | |
9665 | ||
9666 | static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) | |
9667 | { | |
9668 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9669 | uint32_t val, data; | |
9670 | int ret; | |
9671 | ||
9672 | if (WARN((I915_READ(LCPLL_CTL) & | |
9673 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | | |
9674 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | | |
9675 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | | |
9676 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, | |
9677 | "trying to change cdclk frequency with cdclk not enabled\n")) | |
9678 | return; | |
9679 | ||
9680 | mutex_lock(&dev_priv->rps.hw_lock); | |
9681 | ret = sandybridge_pcode_write(dev_priv, | |
9682 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); | |
9683 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9684 | if (ret) { | |
9685 | DRM_ERROR("failed to inform pcode about cdclk change\n"); | |
9686 | return; | |
9687 | } | |
9688 | ||
9689 | val = I915_READ(LCPLL_CTL); | |
9690 | val |= LCPLL_CD_SOURCE_FCLK; | |
9691 | I915_WRITE(LCPLL_CTL, val); | |
9692 | ||
9693 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9694 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9695 | DRM_ERROR("Switching to FCLK failed\n"); | |
9696 | ||
9697 | val = I915_READ(LCPLL_CTL); | |
9698 | val &= ~LCPLL_CLK_FREQ_MASK; | |
9699 | ||
9700 | switch (cdclk) { | |
9701 | case 450000: | |
9702 | val |= LCPLL_CLK_FREQ_450; | |
9703 | data = 0; | |
9704 | break; | |
9705 | case 540000: | |
9706 | val |= LCPLL_CLK_FREQ_54O_BDW; | |
9707 | data = 1; | |
9708 | break; | |
9709 | case 337500: | |
9710 | val |= LCPLL_CLK_FREQ_337_5_BDW; | |
9711 | data = 2; | |
9712 | break; | |
9713 | case 675000: | |
9714 | val |= LCPLL_CLK_FREQ_675_BDW; | |
9715 | data = 3; | |
9716 | break; | |
9717 | default: | |
9718 | WARN(1, "invalid cdclk frequency\n"); | |
9719 | return; | |
9720 | } | |
9721 | ||
9722 | I915_WRITE(LCPLL_CTL, val); | |
9723 | ||
9724 | val = I915_READ(LCPLL_CTL); | |
9725 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9726 | I915_WRITE(LCPLL_CTL, val); | |
9727 | ||
9728 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9729 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9730 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9731 | ||
9732 | mutex_lock(&dev_priv->rps.hw_lock); | |
9733 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); | |
9734 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9735 | ||
9736 | intel_update_cdclk(dev); | |
9737 | ||
9738 | WARN(cdclk != dev_priv->cdclk_freq, | |
9739 | "cdclk requested %d kHz but got %d kHz\n", | |
9740 | cdclk, dev_priv->cdclk_freq); | |
9741 | } | |
9742 | ||
9743 | static int broadwell_calc_cdclk(struct drm_i915_private *dev_priv, | |
9744 | int max_pixel_rate) | |
9745 | { | |
9746 | int cdclk; | |
9747 | ||
9748 | /* | |
9749 | * FIXME should also account for plane ratio | |
9750 | * once 64bpp pixel formats are supported. | |
9751 | */ | |
9752 | if (max_pixel_rate > 540000) | |
9753 | cdclk = 675000; | |
9754 | else if (max_pixel_rate > 450000) | |
9755 | cdclk = 540000; | |
9756 | else if (max_pixel_rate > 337500) | |
9757 | cdclk = 450000; | |
9758 | else | |
9759 | cdclk = 337500; | |
9760 | ||
9761 | /* | |
9762 | * FIXME move the cdclk caclulation to | |
9763 | * compute_config() so we can fail gracegully. | |
9764 | */ | |
9765 | if (cdclk > dev_priv->max_cdclk_freq) { | |
9766 | DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n", | |
9767 | cdclk, dev_priv->max_cdclk_freq); | |
9768 | cdclk = dev_priv->max_cdclk_freq; | |
9769 | } | |
9770 | ||
9771 | return cdclk; | |
9772 | } | |
9773 | ||
9774 | static int broadwell_modeset_global_pipes(struct drm_atomic_state *state) | |
9775 | { | |
9776 | struct drm_i915_private *dev_priv = to_i915(state->dev); | |
9777 | struct drm_crtc *crtc; | |
9778 | struct drm_crtc_state *crtc_state; | |
9779 | int max_pixclk = ilk_max_pixel_rate(dev_priv); | |
9780 | int cdclk, i; | |
9781 | ||
9782 | cdclk = broadwell_calc_cdclk(dev_priv, max_pixclk); | |
9783 | ||
9784 | if (cdclk == dev_priv->cdclk_freq) | |
9785 | return 0; | |
9786 | ||
9787 | /* add all active pipes to the state */ | |
9788 | for_each_crtc(state->dev, crtc) { | |
9789 | if (!crtc->state->enable) | |
9790 | continue; | |
9791 | ||
9792 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
9793 | if (IS_ERR(crtc_state)) | |
9794 | return PTR_ERR(crtc_state); | |
9795 | } | |
9796 | ||
9797 | /* disable/enable all currently active pipes while we change cdclk */ | |
9798 | for_each_crtc_in_state(state, crtc, crtc_state, i) | |
9799 | if (crtc_state->enable) | |
9800 | crtc_state->mode_changed = true; | |
9801 | ||
9802 | return 0; | |
9803 | } | |
9804 | ||
9805 | static void broadwell_modeset_global_resources(struct drm_atomic_state *state) | |
9806 | { | |
9807 | struct drm_device *dev = state->dev; | |
9808 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9809 | int max_pixel_rate = ilk_max_pixel_rate(dev_priv); | |
9810 | int req_cdclk = broadwell_calc_cdclk(dev_priv, max_pixel_rate); | |
9811 | ||
9812 | if (req_cdclk != dev_priv->cdclk_freq) | |
9813 | broadwell_set_cdclk(dev, req_cdclk); | |
9814 | } | |
9815 | ||
190f68c5 ACO |
9816 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
9817 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 9818 | { |
190f68c5 | 9819 | if (!intel_ddi_pll_select(crtc, crtc_state)) |
6441ab5f | 9820 | return -EINVAL; |
716c2e55 | 9821 | |
c7653199 | 9822 | crtc->lowfreq_avail = false; |
644cef34 | 9823 | |
c8f7a0db | 9824 | return 0; |
79e53945 JB |
9825 | } |
9826 | ||
3760b59c S |
9827 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
9828 | enum port port, | |
9829 | struct intel_crtc_state *pipe_config) | |
9830 | { | |
9831 | switch (port) { | |
9832 | case PORT_A: | |
9833 | pipe_config->ddi_pll_sel = SKL_DPLL0; | |
9834 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9835 | break; | |
9836 | case PORT_B: | |
9837 | pipe_config->ddi_pll_sel = SKL_DPLL1; | |
9838 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9839 | break; | |
9840 | case PORT_C: | |
9841 | pipe_config->ddi_pll_sel = SKL_DPLL2; | |
9842 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9843 | break; | |
9844 | default: | |
9845 | DRM_ERROR("Incorrect port type\n"); | |
9846 | } | |
9847 | } | |
9848 | ||
96b7dfb7 S |
9849 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
9850 | enum port port, | |
5cec258b | 9851 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 9852 | { |
3148ade7 | 9853 | u32 temp, dpll_ctl1; |
96b7dfb7 S |
9854 | |
9855 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
9856 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
9857 | ||
9858 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 DL |
9859 | case SKL_DPLL0: |
9860 | /* | |
9861 | * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part | |
9862 | * of the shared DPLL framework and thus needs to be read out | |
9863 | * separately | |
9864 | */ | |
9865 | dpll_ctl1 = I915_READ(DPLL_CTRL1); | |
9866 | pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f; | |
9867 | break; | |
96b7dfb7 S |
9868 | case SKL_DPLL1: |
9869 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9870 | break; | |
9871 | case SKL_DPLL2: | |
9872 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9873 | break; | |
9874 | case SKL_DPLL3: | |
9875 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9876 | break; | |
96b7dfb7 S |
9877 | } |
9878 | } | |
9879 | ||
7d2c8175 DL |
9880 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
9881 | enum port port, | |
5cec258b | 9882 | struct intel_crtc_state *pipe_config) |
7d2c8175 DL |
9883 | { |
9884 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); | |
9885 | ||
9886 | switch (pipe_config->ddi_pll_sel) { | |
9887 | case PORT_CLK_SEL_WRPLL1: | |
9888 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; | |
9889 | break; | |
9890 | case PORT_CLK_SEL_WRPLL2: | |
9891 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; | |
9892 | break; | |
9893 | } | |
9894 | } | |
9895 | ||
26804afd | 9896 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 9897 | struct intel_crtc_state *pipe_config) |
26804afd DV |
9898 | { |
9899 | struct drm_device *dev = crtc->base.dev; | |
9900 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 9901 | struct intel_shared_dpll *pll; |
26804afd DV |
9902 | enum port port; |
9903 | uint32_t tmp; | |
9904 | ||
9905 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
9906 | ||
9907 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
9908 | ||
96b7dfb7 S |
9909 | if (IS_SKYLAKE(dev)) |
9910 | skylake_get_ddi_pll(dev_priv, port, pipe_config); | |
3760b59c S |
9911 | else if (IS_BROXTON(dev)) |
9912 | bxt_get_ddi_pll(dev_priv, port, pipe_config); | |
96b7dfb7 S |
9913 | else |
9914 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 9915 | |
d452c5b6 DV |
9916 | if (pipe_config->shared_dpll >= 0) { |
9917 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
9918 | ||
9919 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
9920 | &pipe_config->dpll_hw_state)); | |
9921 | } | |
9922 | ||
26804afd DV |
9923 | /* |
9924 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
9925 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
9926 | * the PCH transcoder is on. | |
9927 | */ | |
ca370455 DL |
9928 | if (INTEL_INFO(dev)->gen < 9 && |
9929 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
9930 | pipe_config->has_pch_encoder = true; |
9931 | ||
9932 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
9933 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9934 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
9935 | ||
9936 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
9937 | } | |
9938 | } | |
9939 | ||
0e8ffe1b | 9940 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9941 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9942 | { |
9943 | struct drm_device *dev = crtc->base.dev; | |
9944 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 9945 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
9946 | uint32_t tmp; |
9947 | ||
f458ebbc | 9948 | if (!intel_display_power_is_enabled(dev_priv, |
b5482bd0 ID |
9949 | POWER_DOMAIN_PIPE(crtc->pipe))) |
9950 | return false; | |
9951 | ||
e143a21c | 9952 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
9953 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
9954 | ||
eccb140b DV |
9955 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
9956 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
9957 | enum pipe trans_edp_pipe; | |
9958 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
9959 | default: | |
9960 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
9961 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
9962 | case TRANS_DDI_EDP_INPUT_A_ON: | |
9963 | trans_edp_pipe = PIPE_A; | |
9964 | break; | |
9965 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
9966 | trans_edp_pipe = PIPE_B; | |
9967 | break; | |
9968 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
9969 | trans_edp_pipe = PIPE_C; | |
9970 | break; | |
9971 | } | |
9972 | ||
9973 | if (trans_edp_pipe == crtc->pipe) | |
9974 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
9975 | } | |
9976 | ||
f458ebbc | 9977 | if (!intel_display_power_is_enabled(dev_priv, |
eccb140b | 9978 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
9979 | return false; |
9980 | ||
eccb140b | 9981 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
9982 | if (!(tmp & PIPECONF_ENABLE)) |
9983 | return false; | |
9984 | ||
26804afd | 9985 | haswell_get_ddi_port_state(crtc, pipe_config); |
627eb5a3 | 9986 | |
1bd1bd80 DV |
9987 | intel_get_pipe_timings(crtc, pipe_config); |
9988 | ||
a1b2278e CK |
9989 | if (INTEL_INFO(dev)->gen >= 9) { |
9990 | skl_init_scalers(dev, crtc, pipe_config); | |
9991 | } | |
9992 | ||
2fa2fe9a | 9993 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
af99ceda CK |
9994 | |
9995 | if (INTEL_INFO(dev)->gen >= 9) { | |
9996 | pipe_config->scaler_state.scaler_id = -1; | |
9997 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
9998 | } | |
9999 | ||
bd2e244f | 10000 | if (intel_display_power_is_enabled(dev_priv, pfit_domain)) { |
ff6d9f55 | 10001 | if (INTEL_INFO(dev)->gen == 9) |
bd2e244f | 10002 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 10003 | else if (INTEL_INFO(dev)->gen < 9) |
bd2e244f | 10004 | ironlake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 JB |
10005 | else |
10006 | MISSING_CASE(INTEL_INFO(dev)->gen); | |
bd2e244f | 10007 | } |
88adfff1 | 10008 | |
e59150dc JB |
10009 | if (IS_HASWELL(dev)) |
10010 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
10011 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 10012 | |
ebb69c95 CT |
10013 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP) { |
10014 | pipe_config->pixel_multiplier = | |
10015 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
10016 | } else { | |
10017 | pipe_config->pixel_multiplier = 1; | |
10018 | } | |
6c49f241 | 10019 | |
0e8ffe1b DV |
10020 | return true; |
10021 | } | |
10022 | ||
560b85bb CW |
10023 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
10024 | { | |
10025 | struct drm_device *dev = crtc->dev; | |
10026 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10027 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 10028 | uint32_t cntl = 0, size = 0; |
560b85bb | 10029 | |
dc41c154 | 10030 | if (base) { |
3dd512fb MR |
10031 | unsigned int width = intel_crtc->base.cursor->state->crtc_w; |
10032 | unsigned int height = intel_crtc->base.cursor->state->crtc_h; | |
dc41c154 VS |
10033 | unsigned int stride = roundup_pow_of_two(width) * 4; |
10034 | ||
10035 | switch (stride) { | |
10036 | default: | |
10037 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
10038 | width, stride); | |
10039 | stride = 256; | |
10040 | /* fallthrough */ | |
10041 | case 256: | |
10042 | case 512: | |
10043 | case 1024: | |
10044 | case 2048: | |
10045 | break; | |
4b0e333e CW |
10046 | } |
10047 | ||
dc41c154 VS |
10048 | cntl |= CURSOR_ENABLE | |
10049 | CURSOR_GAMMA_ENABLE | | |
10050 | CURSOR_FORMAT_ARGB | | |
10051 | CURSOR_STRIDE(stride); | |
10052 | ||
10053 | size = (height << 12) | width; | |
4b0e333e | 10054 | } |
560b85bb | 10055 | |
dc41c154 VS |
10056 | if (intel_crtc->cursor_cntl != 0 && |
10057 | (intel_crtc->cursor_base != base || | |
10058 | intel_crtc->cursor_size != size || | |
10059 | intel_crtc->cursor_cntl != cntl)) { | |
10060 | /* On these chipsets we can only modify the base/size/stride | |
10061 | * whilst the cursor is disabled. | |
10062 | */ | |
10063 | I915_WRITE(_CURACNTR, 0); | |
4b0e333e | 10064 | POSTING_READ(_CURACNTR); |
dc41c154 | 10065 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 10066 | } |
560b85bb | 10067 | |
99d1f387 | 10068 | if (intel_crtc->cursor_base != base) { |
9db4a9c7 | 10069 | I915_WRITE(_CURABASE, base); |
99d1f387 VS |
10070 | intel_crtc->cursor_base = base; |
10071 | } | |
4726e0b0 | 10072 | |
dc41c154 VS |
10073 | if (intel_crtc->cursor_size != size) { |
10074 | I915_WRITE(CURSIZE, size); | |
10075 | intel_crtc->cursor_size = size; | |
4b0e333e | 10076 | } |
560b85bb | 10077 | |
4b0e333e | 10078 | if (intel_crtc->cursor_cntl != cntl) { |
4b0e333e CW |
10079 | I915_WRITE(_CURACNTR, cntl); |
10080 | POSTING_READ(_CURACNTR); | |
4b0e333e | 10081 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 10082 | } |
560b85bb CW |
10083 | } |
10084 | ||
560b85bb | 10085 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
65a21cd6 JB |
10086 | { |
10087 | struct drm_device *dev = crtc->dev; | |
10088 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10089 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10090 | int pipe = intel_crtc->pipe; | |
4b0e333e CW |
10091 | uint32_t cntl; |
10092 | ||
10093 | cntl = 0; | |
10094 | if (base) { | |
10095 | cntl = MCURSOR_GAMMA_ENABLE; | |
3dd512fb | 10096 | switch (intel_crtc->base.cursor->state->crtc_w) { |
4726e0b0 SK |
10097 | case 64: |
10098 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
10099 | break; | |
10100 | case 128: | |
10101 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
10102 | break; | |
10103 | case 256: | |
10104 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
10105 | break; | |
10106 | default: | |
3dd512fb | 10107 | MISSING_CASE(intel_crtc->base.cursor->state->crtc_w); |
4726e0b0 | 10108 | return; |
65a21cd6 | 10109 | } |
4b0e333e | 10110 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 VS |
10111 | |
10112 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
10113 | cntl |= CURSOR_PIPE_CSC_ENABLE; | |
4b0e333e | 10114 | } |
65a21cd6 | 10115 | |
8e7d688b | 10116 | if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) |
4398ad45 VS |
10117 | cntl |= CURSOR_ROTATE_180; |
10118 | ||
4b0e333e CW |
10119 | if (intel_crtc->cursor_cntl != cntl) { |
10120 | I915_WRITE(CURCNTR(pipe), cntl); | |
10121 | POSTING_READ(CURCNTR(pipe)); | |
10122 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 10123 | } |
4b0e333e | 10124 | |
65a21cd6 | 10125 | /* and commit changes on next vblank */ |
5efb3e28 VS |
10126 | I915_WRITE(CURBASE(pipe), base); |
10127 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
10128 | |
10129 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
10130 | } |
10131 | ||
cda4b7d3 | 10132 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
10133 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
10134 | bool on) | |
cda4b7d3 CW |
10135 | { |
10136 | struct drm_device *dev = crtc->dev; | |
10137 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10138 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10139 | int pipe = intel_crtc->pipe; | |
3d7d6510 MR |
10140 | int x = crtc->cursor_x; |
10141 | int y = crtc->cursor_y; | |
d6e4db15 | 10142 | u32 base = 0, pos = 0; |
cda4b7d3 | 10143 | |
d6e4db15 | 10144 | if (on) |
cda4b7d3 | 10145 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 10146 | |
6e3c9717 | 10147 | if (x >= intel_crtc->config->pipe_src_w) |
d6e4db15 VS |
10148 | base = 0; |
10149 | ||
6e3c9717 | 10150 | if (y >= intel_crtc->config->pipe_src_h) |
cda4b7d3 CW |
10151 | base = 0; |
10152 | ||
10153 | if (x < 0) { | |
3dd512fb | 10154 | if (x + intel_crtc->base.cursor->state->crtc_w <= 0) |
cda4b7d3 CW |
10155 | base = 0; |
10156 | ||
10157 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
10158 | x = -x; | |
10159 | } | |
10160 | pos |= x << CURSOR_X_SHIFT; | |
10161 | ||
10162 | if (y < 0) { | |
3dd512fb | 10163 | if (y + intel_crtc->base.cursor->state->crtc_h <= 0) |
cda4b7d3 CW |
10164 | base = 0; |
10165 | ||
10166 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
10167 | y = -y; | |
10168 | } | |
10169 | pos |= y << CURSOR_Y_SHIFT; | |
10170 | ||
4b0e333e | 10171 | if (base == 0 && intel_crtc->cursor_base == 0) |
cda4b7d3 CW |
10172 | return; |
10173 | ||
5efb3e28 VS |
10174 | I915_WRITE(CURPOS(pipe), pos); |
10175 | ||
4398ad45 VS |
10176 | /* ILK+ do this automagically */ |
10177 | if (HAS_GMCH_DISPLAY(dev) && | |
8e7d688b | 10178 | crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) { |
3dd512fb MR |
10179 | base += (intel_crtc->base.cursor->state->crtc_h * |
10180 | intel_crtc->base.cursor->state->crtc_w - 1) * 4; | |
4398ad45 VS |
10181 | } |
10182 | ||
8ac54669 | 10183 | if (IS_845G(dev) || IS_I865G(dev)) |
5efb3e28 VS |
10184 | i845_update_cursor(crtc, base); |
10185 | else | |
10186 | i9xx_update_cursor(crtc, base); | |
cda4b7d3 CW |
10187 | } |
10188 | ||
dc41c154 VS |
10189 | static bool cursor_size_ok(struct drm_device *dev, |
10190 | uint32_t width, uint32_t height) | |
10191 | { | |
10192 | if (width == 0 || height == 0) | |
10193 | return false; | |
10194 | ||
10195 | /* | |
10196 | * 845g/865g are special in that they are only limited by | |
10197 | * the width of their cursors, the height is arbitrary up to | |
10198 | * the precision of the register. Everything else requires | |
10199 | * square cursors, limited to a few power-of-two sizes. | |
10200 | */ | |
10201 | if (IS_845G(dev) || IS_I865G(dev)) { | |
10202 | if ((width & 63) != 0) | |
10203 | return false; | |
10204 | ||
10205 | if (width > (IS_845G(dev) ? 64 : 512)) | |
10206 | return false; | |
10207 | ||
10208 | if (height > 1023) | |
10209 | return false; | |
10210 | } else { | |
10211 | switch (width | height) { | |
10212 | case 256: | |
10213 | case 128: | |
10214 | if (IS_GEN2(dev)) | |
10215 | return false; | |
10216 | case 64: | |
10217 | break; | |
10218 | default: | |
10219 | return false; | |
10220 | } | |
10221 | } | |
10222 | ||
10223 | return true; | |
10224 | } | |
10225 | ||
79e53945 | 10226 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 10227 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 10228 | { |
7203425a | 10229 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 10230 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 10231 | |
7203425a | 10232 | for (i = start; i < end; i++) { |
79e53945 JB |
10233 | intel_crtc->lut_r[i] = red[i] >> 8; |
10234 | intel_crtc->lut_g[i] = green[i] >> 8; | |
10235 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
10236 | } | |
10237 | ||
10238 | intel_crtc_load_lut(crtc); | |
10239 | } | |
10240 | ||
79e53945 JB |
10241 | /* VESA 640x480x72Hz mode to set on the pipe */ |
10242 | static struct drm_display_mode load_detect_mode = { | |
10243 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
10244 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
10245 | }; | |
10246 | ||
a8bb6818 DV |
10247 | struct drm_framebuffer * |
10248 | __intel_framebuffer_create(struct drm_device *dev, | |
10249 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10250 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
10251 | { |
10252 | struct intel_framebuffer *intel_fb; | |
10253 | int ret; | |
10254 | ||
10255 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
10256 | if (!intel_fb) { | |
6ccb81f2 | 10257 | drm_gem_object_unreference(&obj->base); |
d2dff872 CW |
10258 | return ERR_PTR(-ENOMEM); |
10259 | } | |
10260 | ||
10261 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
10262 | if (ret) |
10263 | goto err; | |
d2dff872 CW |
10264 | |
10265 | return &intel_fb->base; | |
dd4916c5 | 10266 | err: |
6ccb81f2 | 10267 | drm_gem_object_unreference(&obj->base); |
dd4916c5 DV |
10268 | kfree(intel_fb); |
10269 | ||
10270 | return ERR_PTR(ret); | |
d2dff872 CW |
10271 | } |
10272 | ||
b5ea642a | 10273 | static struct drm_framebuffer * |
a8bb6818 DV |
10274 | intel_framebuffer_create(struct drm_device *dev, |
10275 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10276 | struct drm_i915_gem_object *obj) | |
10277 | { | |
10278 | struct drm_framebuffer *fb; | |
10279 | int ret; | |
10280 | ||
10281 | ret = i915_mutex_lock_interruptible(dev); | |
10282 | if (ret) | |
10283 | return ERR_PTR(ret); | |
10284 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
10285 | mutex_unlock(&dev->struct_mutex); | |
10286 | ||
10287 | return fb; | |
10288 | } | |
10289 | ||
d2dff872 CW |
10290 | static u32 |
10291 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
10292 | { | |
10293 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
10294 | return ALIGN(pitch, 64); | |
10295 | } | |
10296 | ||
10297 | static u32 | |
10298 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
10299 | { | |
10300 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 10301 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
10302 | } |
10303 | ||
10304 | static struct drm_framebuffer * | |
10305 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
10306 | struct drm_display_mode *mode, | |
10307 | int depth, int bpp) | |
10308 | { | |
10309 | struct drm_i915_gem_object *obj; | |
0fed39bd | 10310 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
10311 | |
10312 | obj = i915_gem_alloc_object(dev, | |
10313 | intel_framebuffer_size_for_mode(mode, bpp)); | |
10314 | if (obj == NULL) | |
10315 | return ERR_PTR(-ENOMEM); | |
10316 | ||
10317 | mode_cmd.width = mode->hdisplay; | |
10318 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
10319 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
10320 | bpp); | |
5ca0c34a | 10321 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
10322 | |
10323 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
10324 | } | |
10325 | ||
10326 | static struct drm_framebuffer * | |
10327 | mode_fits_in_fbdev(struct drm_device *dev, | |
10328 | struct drm_display_mode *mode) | |
10329 | { | |
4520f53a | 10330 | #ifdef CONFIG_DRM_I915_FBDEV |
d2dff872 CW |
10331 | struct drm_i915_private *dev_priv = dev->dev_private; |
10332 | struct drm_i915_gem_object *obj; | |
10333 | struct drm_framebuffer *fb; | |
10334 | ||
4c0e5528 | 10335 | if (!dev_priv->fbdev) |
d2dff872 CW |
10336 | return NULL; |
10337 | ||
4c0e5528 | 10338 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
10339 | return NULL; |
10340 | ||
4c0e5528 DV |
10341 | obj = dev_priv->fbdev->fb->obj; |
10342 | BUG_ON(!obj); | |
10343 | ||
8bcd4553 | 10344 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
10345 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
10346 | fb->bits_per_pixel)) | |
d2dff872 CW |
10347 | return NULL; |
10348 | ||
01f2c773 | 10349 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
10350 | return NULL; |
10351 | ||
10352 | return fb; | |
4520f53a DV |
10353 | #else |
10354 | return NULL; | |
10355 | #endif | |
d2dff872 CW |
10356 | } |
10357 | ||
d3a40d1b ACO |
10358 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
10359 | struct drm_crtc *crtc, | |
10360 | struct drm_display_mode *mode, | |
10361 | struct drm_framebuffer *fb, | |
10362 | int x, int y) | |
10363 | { | |
10364 | struct drm_plane_state *plane_state; | |
10365 | int hdisplay, vdisplay; | |
10366 | int ret; | |
10367 | ||
10368 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
10369 | if (IS_ERR(plane_state)) | |
10370 | return PTR_ERR(plane_state); | |
10371 | ||
10372 | if (mode) | |
10373 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); | |
10374 | else | |
10375 | hdisplay = vdisplay = 0; | |
10376 | ||
10377 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
10378 | if (ret) | |
10379 | return ret; | |
10380 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
10381 | plane_state->crtc_x = 0; | |
10382 | plane_state->crtc_y = 0; | |
10383 | plane_state->crtc_w = hdisplay; | |
10384 | plane_state->crtc_h = vdisplay; | |
10385 | plane_state->src_x = x << 16; | |
10386 | plane_state->src_y = y << 16; | |
10387 | plane_state->src_w = hdisplay << 16; | |
10388 | plane_state->src_h = vdisplay << 16; | |
10389 | ||
10390 | return 0; | |
10391 | } | |
10392 | ||
d2434ab7 | 10393 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 10394 | struct drm_display_mode *mode, |
51fd371b RC |
10395 | struct intel_load_detect_pipe *old, |
10396 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
10397 | { |
10398 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
10399 | struct intel_encoder *intel_encoder = |
10400 | intel_attached_encoder(connector); | |
79e53945 | 10401 | struct drm_crtc *possible_crtc; |
4ef69c7a | 10402 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
10403 | struct drm_crtc *crtc = NULL; |
10404 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 10405 | struct drm_framebuffer *fb; |
51fd371b | 10406 | struct drm_mode_config *config = &dev->mode_config; |
83a57153 | 10407 | struct drm_atomic_state *state = NULL; |
944b0c76 | 10408 | struct drm_connector_state *connector_state; |
4be07317 | 10409 | struct intel_crtc_state *crtc_state; |
51fd371b | 10410 | int ret, i = -1; |
79e53945 | 10411 | |
d2dff872 | 10412 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10413 | connector->base.id, connector->name, |
8e329a03 | 10414 | encoder->base.id, encoder->name); |
d2dff872 | 10415 | |
51fd371b RC |
10416 | retry: |
10417 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
10418 | if (ret) | |
10419 | goto fail_unlock; | |
6e9f798d | 10420 | |
79e53945 JB |
10421 | /* |
10422 | * Algorithm gets a little messy: | |
7a5e4805 | 10423 | * |
79e53945 JB |
10424 | * - if the connector already has an assigned crtc, use it (but make |
10425 | * sure it's on first) | |
7a5e4805 | 10426 | * |
79e53945 JB |
10427 | * - try to find the first unused crtc that can drive this connector, |
10428 | * and use that if we find one | |
79e53945 JB |
10429 | */ |
10430 | ||
10431 | /* See if we already have a CRTC for this connector */ | |
10432 | if (encoder->crtc) { | |
10433 | crtc = encoder->crtc; | |
8261b191 | 10434 | |
51fd371b | 10435 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de DV |
10436 | if (ret) |
10437 | goto fail_unlock; | |
10438 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); | |
51fd371b RC |
10439 | if (ret) |
10440 | goto fail_unlock; | |
7b24056b | 10441 | |
24218aac | 10442 | old->dpms_mode = connector->dpms; |
8261b191 CW |
10443 | old->load_detect_temp = false; |
10444 | ||
10445 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
10446 | if (connector->dpms != DRM_MODE_DPMS_ON) |
10447 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 10448 | |
7173188d | 10449 | return true; |
79e53945 JB |
10450 | } |
10451 | ||
10452 | /* Find an unused one (if possible) */ | |
70e1e0ec | 10453 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
10454 | i++; |
10455 | if (!(encoder->possible_crtcs & (1 << i))) | |
10456 | continue; | |
83d65738 | 10457 | if (possible_crtc->state->enable) |
a459249c VS |
10458 | continue; |
10459 | /* This can occur when applying the pipe A quirk on resume. */ | |
10460 | if (to_intel_crtc(possible_crtc)->new_enabled) | |
10461 | continue; | |
10462 | ||
10463 | crtc = possible_crtc; | |
10464 | break; | |
79e53945 JB |
10465 | } |
10466 | ||
10467 | /* | |
10468 | * If we didn't find an unused CRTC, don't use any. | |
10469 | */ | |
10470 | if (!crtc) { | |
7173188d | 10471 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
51fd371b | 10472 | goto fail_unlock; |
79e53945 JB |
10473 | } |
10474 | ||
51fd371b RC |
10475 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
10476 | if (ret) | |
4d02e2de DV |
10477 | goto fail_unlock; |
10478 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); | |
10479 | if (ret) | |
51fd371b | 10480 | goto fail_unlock; |
fc303101 DV |
10481 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
10482 | to_intel_connector(connector)->new_encoder = intel_encoder; | |
79e53945 JB |
10483 | |
10484 | intel_crtc = to_intel_crtc(crtc); | |
412b61d8 | 10485 | intel_crtc->new_enabled = true; |
24218aac | 10486 | old->dpms_mode = connector->dpms; |
8261b191 | 10487 | old->load_detect_temp = true; |
d2dff872 | 10488 | old->release_fb = NULL; |
79e53945 | 10489 | |
83a57153 ACO |
10490 | state = drm_atomic_state_alloc(dev); |
10491 | if (!state) | |
10492 | return false; | |
10493 | ||
10494 | state->acquire_ctx = ctx; | |
10495 | ||
944b0c76 ACO |
10496 | connector_state = drm_atomic_get_connector_state(state, connector); |
10497 | if (IS_ERR(connector_state)) { | |
10498 | ret = PTR_ERR(connector_state); | |
10499 | goto fail; | |
10500 | } | |
10501 | ||
10502 | connector_state->crtc = crtc; | |
10503 | connector_state->best_encoder = &intel_encoder->base; | |
10504 | ||
4be07317 ACO |
10505 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10506 | if (IS_ERR(crtc_state)) { | |
10507 | ret = PTR_ERR(crtc_state); | |
10508 | goto fail; | |
10509 | } | |
10510 | ||
49d6fa21 | 10511 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 10512 | |
6492711d CW |
10513 | if (!mode) |
10514 | mode = &load_detect_mode; | |
79e53945 | 10515 | |
d2dff872 CW |
10516 | /* We need a framebuffer large enough to accommodate all accesses |
10517 | * that the plane may generate whilst we perform load detection. | |
10518 | * We can not rely on the fbcon either being present (we get called | |
10519 | * during its initialisation to detect all boot displays, or it may | |
10520 | * not even exist) or that it is large enough to satisfy the | |
10521 | * requested mode. | |
10522 | */ | |
94352cf9 DV |
10523 | fb = mode_fits_in_fbdev(dev, mode); |
10524 | if (fb == NULL) { | |
d2dff872 | 10525 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
10526 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
10527 | old->release_fb = fb; | |
d2dff872 CW |
10528 | } else |
10529 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 10530 | if (IS_ERR(fb)) { |
d2dff872 | 10531 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 10532 | goto fail; |
79e53945 | 10533 | } |
79e53945 | 10534 | |
d3a40d1b ACO |
10535 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
10536 | if (ret) | |
10537 | goto fail; | |
10538 | ||
8c7b5ccb ACO |
10539 | drm_mode_copy(&crtc_state->base.mode, mode); |
10540 | ||
10541 | if (intel_set_mode(crtc, state)) { | |
6492711d | 10542 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
10543 | if (old->release_fb) |
10544 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 10545 | goto fail; |
79e53945 | 10546 | } |
9128b040 | 10547 | crtc->primary->crtc = crtc; |
7173188d | 10548 | |
79e53945 | 10549 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 10550 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 10551 | return true; |
412b61d8 VS |
10552 | |
10553 | fail: | |
83d65738 | 10554 | intel_crtc->new_enabled = crtc->state->enable; |
51fd371b | 10555 | fail_unlock: |
e5d958ef ACO |
10556 | drm_atomic_state_free(state); |
10557 | state = NULL; | |
83a57153 | 10558 | |
51fd371b RC |
10559 | if (ret == -EDEADLK) { |
10560 | drm_modeset_backoff(ctx); | |
10561 | goto retry; | |
10562 | } | |
10563 | ||
412b61d8 | 10564 | return false; |
79e53945 JB |
10565 | } |
10566 | ||
d2434ab7 | 10567 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
10568 | struct intel_load_detect_pipe *old, |
10569 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 10570 | { |
83a57153 | 10571 | struct drm_device *dev = connector->dev; |
d2434ab7 DV |
10572 | struct intel_encoder *intel_encoder = |
10573 | intel_attached_encoder(connector); | |
4ef69c7a | 10574 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 10575 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 10576 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
83a57153 | 10577 | struct drm_atomic_state *state; |
944b0c76 | 10578 | struct drm_connector_state *connector_state; |
4be07317 | 10579 | struct intel_crtc_state *crtc_state; |
d3a40d1b | 10580 | int ret; |
79e53945 | 10581 | |
d2dff872 | 10582 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10583 | connector->base.id, connector->name, |
8e329a03 | 10584 | encoder->base.id, encoder->name); |
d2dff872 | 10585 | |
8261b191 | 10586 | if (old->load_detect_temp) { |
83a57153 | 10587 | state = drm_atomic_state_alloc(dev); |
944b0c76 ACO |
10588 | if (!state) |
10589 | goto fail; | |
83a57153 ACO |
10590 | |
10591 | state->acquire_ctx = ctx; | |
10592 | ||
944b0c76 ACO |
10593 | connector_state = drm_atomic_get_connector_state(state, connector); |
10594 | if (IS_ERR(connector_state)) | |
10595 | goto fail; | |
10596 | ||
4be07317 ACO |
10597 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10598 | if (IS_ERR(crtc_state)) | |
10599 | goto fail; | |
10600 | ||
fc303101 DV |
10601 | to_intel_connector(connector)->new_encoder = NULL; |
10602 | intel_encoder->new_crtc = NULL; | |
412b61d8 | 10603 | intel_crtc->new_enabled = false; |
944b0c76 ACO |
10604 | |
10605 | connector_state->best_encoder = NULL; | |
10606 | connector_state->crtc = NULL; | |
10607 | ||
49d6fa21 | 10608 | crtc_state->base.enable = crtc_state->base.active = false; |
4be07317 | 10609 | |
d3a40d1b ACO |
10610 | ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL, |
10611 | 0, 0); | |
10612 | if (ret) | |
10613 | goto fail; | |
10614 | ||
2bfb4627 ACO |
10615 | ret = intel_set_mode(crtc, state); |
10616 | if (ret) | |
10617 | goto fail; | |
d2dff872 | 10618 | |
36206361 DV |
10619 | if (old->release_fb) { |
10620 | drm_framebuffer_unregister_private(old->release_fb); | |
10621 | drm_framebuffer_unreference(old->release_fb); | |
10622 | } | |
d2dff872 | 10623 | |
0622a53c | 10624 | return; |
79e53945 JB |
10625 | } |
10626 | ||
c751ce4f | 10627 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
10628 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
10629 | connector->funcs->dpms(connector, old->dpms_mode); | |
944b0c76 ACO |
10630 | |
10631 | return; | |
10632 | fail: | |
10633 | DRM_DEBUG_KMS("Couldn't release load detect pipe.\n"); | |
10634 | drm_atomic_state_free(state); | |
79e53945 JB |
10635 | } |
10636 | ||
da4a1efa | 10637 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 10638 | const struct intel_crtc_state *pipe_config) |
da4a1efa VS |
10639 | { |
10640 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10641 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
10642 | ||
10643 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 10644 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
10645 | else if (HAS_PCH_SPLIT(dev)) |
10646 | return 120000; | |
10647 | else if (!IS_GEN2(dev)) | |
10648 | return 96000; | |
10649 | else | |
10650 | return 48000; | |
10651 | } | |
10652 | ||
79e53945 | 10653 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 10654 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 10655 | struct intel_crtc_state *pipe_config) |
79e53945 | 10656 | { |
f1f644dc | 10657 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 10658 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 10659 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 10660 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
10661 | u32 fp; |
10662 | intel_clock_t clock; | |
da4a1efa | 10663 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
10664 | |
10665 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 10666 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 10667 | else |
293623f7 | 10668 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
10669 | |
10670 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
10671 | if (IS_PINEVIEW(dev)) { |
10672 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
10673 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
10674 | } else { |
10675 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
10676 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
10677 | } | |
10678 | ||
a6c45cf0 | 10679 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
10680 | if (IS_PINEVIEW(dev)) |
10681 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
10682 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
10683 | else |
10684 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
10685 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
10686 | ||
10687 | switch (dpll & DPLL_MODE_MASK) { | |
10688 | case DPLLB_MODE_DAC_SERIAL: | |
10689 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
10690 | 5 : 10; | |
10691 | break; | |
10692 | case DPLLB_MODE_LVDS: | |
10693 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
10694 | 7 : 14; | |
10695 | break; | |
10696 | default: | |
28c97730 | 10697 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 10698 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 10699 | return; |
79e53945 JB |
10700 | } |
10701 | ||
ac58c3f0 | 10702 | if (IS_PINEVIEW(dev)) |
da4a1efa | 10703 | pineview_clock(refclk, &clock); |
ac58c3f0 | 10704 | else |
da4a1efa | 10705 | i9xx_clock(refclk, &clock); |
79e53945 | 10706 | } else { |
0fb58223 | 10707 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 10708 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
10709 | |
10710 | if (is_lvds) { | |
10711 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
10712 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
10713 | |
10714 | if (lvds & LVDS_CLKB_POWER_UP) | |
10715 | clock.p2 = 7; | |
10716 | else | |
10717 | clock.p2 = 14; | |
79e53945 JB |
10718 | } else { |
10719 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
10720 | clock.p1 = 2; | |
10721 | else { | |
10722 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
10723 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
10724 | } | |
10725 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
10726 | clock.p2 = 4; | |
10727 | else | |
10728 | clock.p2 = 2; | |
79e53945 | 10729 | } |
da4a1efa VS |
10730 | |
10731 | i9xx_clock(refclk, &clock); | |
79e53945 JB |
10732 | } |
10733 | ||
18442d08 VS |
10734 | /* |
10735 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 10736 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
10737 | * encoder's get_config() function. |
10738 | */ | |
10739 | pipe_config->port_clock = clock.dot; | |
f1f644dc JB |
10740 | } |
10741 | ||
6878da05 VS |
10742 | int intel_dotclock_calculate(int link_freq, |
10743 | const struct intel_link_m_n *m_n) | |
f1f644dc | 10744 | { |
f1f644dc JB |
10745 | /* |
10746 | * The calculation for the data clock is: | |
1041a02f | 10747 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 10748 | * But we want to avoid losing precison if possible, so: |
1041a02f | 10749 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
10750 | * |
10751 | * and the link clock is simpler: | |
1041a02f | 10752 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
10753 | */ |
10754 | ||
6878da05 VS |
10755 | if (!m_n->link_n) |
10756 | return 0; | |
f1f644dc | 10757 | |
6878da05 VS |
10758 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
10759 | } | |
f1f644dc | 10760 | |
18442d08 | 10761 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 10762 | struct intel_crtc_state *pipe_config) |
6878da05 VS |
10763 | { |
10764 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 10765 | |
18442d08 VS |
10766 | /* read out port_clock from the DPLL */ |
10767 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 10768 | |
f1f644dc | 10769 | /* |
18442d08 | 10770 | * This value does not include pixel_multiplier. |
241bfc38 | 10771 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
10772 | * agree once we know their relationship in the encoder's |
10773 | * get_config() function. | |
79e53945 | 10774 | */ |
2d112de7 | 10775 | pipe_config->base.adjusted_mode.crtc_clock = |
18442d08 VS |
10776 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
10777 | &pipe_config->fdi_m_n); | |
79e53945 JB |
10778 | } |
10779 | ||
10780 | /** Returns the currently programmed mode of the given pipe. */ | |
10781 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
10782 | struct drm_crtc *crtc) | |
10783 | { | |
548f245b | 10784 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 10785 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 10786 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 10787 | struct drm_display_mode *mode; |
5cec258b | 10788 | struct intel_crtc_state pipe_config; |
fe2b8f9d PZ |
10789 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
10790 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
10791 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
10792 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 10793 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
10794 | |
10795 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
10796 | if (!mode) | |
10797 | return NULL; | |
10798 | ||
f1f644dc JB |
10799 | /* |
10800 | * Construct a pipe_config sufficient for getting the clock info | |
10801 | * back out of crtc_clock_get. | |
10802 | * | |
10803 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
10804 | * to use a real value here instead. | |
10805 | */ | |
293623f7 | 10806 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 10807 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
10808 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
10809 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
10810 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
10811 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
10812 | ||
773ae034 | 10813 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
10814 | mode->hdisplay = (htot & 0xffff) + 1; |
10815 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
10816 | mode->hsync_start = (hsync & 0xffff) + 1; | |
10817 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
10818 | mode->vdisplay = (vtot & 0xffff) + 1; | |
10819 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
10820 | mode->vsync_start = (vsync & 0xffff) + 1; | |
10821 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
10822 | ||
10823 | drm_mode_set_name(mode); | |
79e53945 JB |
10824 | |
10825 | return mode; | |
10826 | } | |
10827 | ||
652c393a JB |
10828 | static void intel_decrease_pllclock(struct drm_crtc *crtc) |
10829 | { | |
10830 | struct drm_device *dev = crtc->dev; | |
fbee40df | 10831 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 10832 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
652c393a | 10833 | |
baff296c | 10834 | if (!HAS_GMCH_DISPLAY(dev)) |
652c393a JB |
10835 | return; |
10836 | ||
10837 | if (!dev_priv->lvds_downclock_avail) | |
10838 | return; | |
10839 | ||
10840 | /* | |
10841 | * Since this is called by a timer, we should never get here in | |
10842 | * the manual case. | |
10843 | */ | |
10844 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
10845 | int pipe = intel_crtc->pipe; |
10846 | int dpll_reg = DPLL(pipe); | |
10847 | int dpll; | |
f6e5b160 | 10848 | |
44d98a61 | 10849 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 10850 | |
8ac5a6d5 | 10851 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 10852 | |
dc257cf1 | 10853 | dpll = I915_READ(dpll_reg); |
652c393a JB |
10854 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
10855 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 10856 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
10857 | dpll = I915_READ(dpll_reg); |
10858 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 10859 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
10860 | } |
10861 | ||
10862 | } | |
10863 | ||
f047e395 CW |
10864 | void intel_mark_busy(struct drm_device *dev) |
10865 | { | |
c67a470b PZ |
10866 | struct drm_i915_private *dev_priv = dev->dev_private; |
10867 | ||
f62a0076 CW |
10868 | if (dev_priv->mm.busy) |
10869 | return; | |
10870 | ||
43694d69 | 10871 | intel_runtime_pm_get(dev_priv); |
c67a470b | 10872 | i915_update_gfx_val(dev_priv); |
43cf3bf0 CW |
10873 | if (INTEL_INFO(dev)->gen >= 6) |
10874 | gen6_rps_busy(dev_priv); | |
f62a0076 | 10875 | dev_priv->mm.busy = true; |
f047e395 CW |
10876 | } |
10877 | ||
10878 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 10879 | { |
c67a470b | 10880 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 10881 | struct drm_crtc *crtc; |
652c393a | 10882 | |
f62a0076 CW |
10883 | if (!dev_priv->mm.busy) |
10884 | return; | |
10885 | ||
10886 | dev_priv->mm.busy = false; | |
10887 | ||
70e1e0ec | 10888 | for_each_crtc(dev, crtc) { |
f4510a27 | 10889 | if (!crtc->primary->fb) |
652c393a JB |
10890 | continue; |
10891 | ||
725a5b54 | 10892 | intel_decrease_pllclock(crtc); |
652c393a | 10893 | } |
b29c19b6 | 10894 | |
3d13ef2e | 10895 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 10896 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 | 10897 | |
43694d69 | 10898 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
10899 | } |
10900 | ||
79e53945 JB |
10901 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
10902 | { | |
10903 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
10904 | struct drm_device *dev = crtc->dev; |
10905 | struct intel_unpin_work *work; | |
67e77c5a | 10906 | |
5e2d7afc | 10907 | spin_lock_irq(&dev->event_lock); |
67e77c5a DV |
10908 | work = intel_crtc->unpin_work; |
10909 | intel_crtc->unpin_work = NULL; | |
5e2d7afc | 10910 | spin_unlock_irq(&dev->event_lock); |
67e77c5a DV |
10911 | |
10912 | if (work) { | |
10913 | cancel_work_sync(&work->work); | |
10914 | kfree(work); | |
10915 | } | |
79e53945 JB |
10916 | |
10917 | drm_crtc_cleanup(crtc); | |
67e77c5a | 10918 | |
79e53945 JB |
10919 | kfree(intel_crtc); |
10920 | } | |
10921 | ||
6b95a207 KH |
10922 | static void intel_unpin_work_fn(struct work_struct *__work) |
10923 | { | |
10924 | struct intel_unpin_work *work = | |
10925 | container_of(__work, struct intel_unpin_work, work); | |
b4a98e57 | 10926 | struct drm_device *dev = work->crtc->dev; |
f99d7069 | 10927 | enum pipe pipe = to_intel_crtc(work->crtc)->pipe; |
6b95a207 | 10928 | |
b4a98e57 | 10929 | mutex_lock(&dev->struct_mutex); |
82bc3b2d | 10930 | intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state); |
05394f39 | 10931 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
d9e86c0e | 10932 | |
7ff0ebcc | 10933 | intel_fbc_update(dev); |
f06cc1b9 JH |
10934 | |
10935 | if (work->flip_queued_req) | |
146d84f0 | 10936 | i915_gem_request_assign(&work->flip_queued_req, NULL); |
b4a98e57 CW |
10937 | mutex_unlock(&dev->struct_mutex); |
10938 | ||
f99d7069 | 10939 | intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
89ed88ba | 10940 | drm_framebuffer_unreference(work->old_fb); |
f99d7069 | 10941 | |
b4a98e57 CW |
10942 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); |
10943 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); | |
10944 | ||
6b95a207 KH |
10945 | kfree(work); |
10946 | } | |
10947 | ||
1afe3e9d | 10948 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 10949 | struct drm_crtc *crtc) |
6b95a207 | 10950 | { |
6b95a207 KH |
10951 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10952 | struct intel_unpin_work *work; | |
6b95a207 KH |
10953 | unsigned long flags; |
10954 | ||
10955 | /* Ignore early vblank irqs */ | |
10956 | if (intel_crtc == NULL) | |
10957 | return; | |
10958 | ||
f326038a DV |
10959 | /* |
10960 | * This is called both by irq handlers and the reset code (to complete | |
10961 | * lost pageflips) so needs the full irqsave spinlocks. | |
10962 | */ | |
6b95a207 KH |
10963 | spin_lock_irqsave(&dev->event_lock, flags); |
10964 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
10965 | |
10966 | /* Ensure we don't miss a work->pending update ... */ | |
10967 | smp_rmb(); | |
10968 | ||
10969 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
10970 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10971 | return; | |
10972 | } | |
10973 | ||
d6bbafa1 | 10974 | page_flip_completed(intel_crtc); |
0af7e4df | 10975 | |
6b95a207 | 10976 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6b95a207 KH |
10977 | } |
10978 | ||
1afe3e9d JB |
10979 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
10980 | { | |
fbee40df | 10981 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10982 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
10983 | ||
49b14a5c | 10984 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10985 | } |
10986 | ||
10987 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
10988 | { | |
fbee40df | 10989 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10990 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
10991 | ||
49b14a5c | 10992 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10993 | } |
10994 | ||
75f7f3ec VS |
10995 | /* Is 'a' after or equal to 'b'? */ |
10996 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
10997 | { | |
10998 | return !((a - b) & 0x80000000); | |
10999 | } | |
11000 | ||
11001 | static bool page_flip_finished(struct intel_crtc *crtc) | |
11002 | { | |
11003 | struct drm_device *dev = crtc->base.dev; | |
11004 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11005 | ||
bdfa7542 VS |
11006 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
11007 | crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
11008 | return true; | |
11009 | ||
75f7f3ec VS |
11010 | /* |
11011 | * The relevant registers doen't exist on pre-ctg. | |
11012 | * As the flip done interrupt doesn't trigger for mmio | |
11013 | * flips on gmch platforms, a flip count check isn't | |
11014 | * really needed there. But since ctg has the registers, | |
11015 | * include it in the check anyway. | |
11016 | */ | |
11017 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
11018 | return true; | |
11019 | ||
11020 | /* | |
11021 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
11022 | * used the same base address. In that case the mmio flip might | |
11023 | * have completed, but the CS hasn't even executed the flip yet. | |
11024 | * | |
11025 | * A flip count check isn't enough as the CS might have updated | |
11026 | * the base address just after start of vblank, but before we | |
11027 | * managed to process the interrupt. This means we'd complete the | |
11028 | * CS flip too soon. | |
11029 | * | |
11030 | * Combining both checks should get us a good enough result. It may | |
11031 | * still happen that the CS flip has been executed, but has not | |
11032 | * yet actually completed. But in case the base address is the same | |
11033 | * anyway, we don't really care. | |
11034 | */ | |
11035 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
11036 | crtc->unpin_work->gtt_offset && | |
11037 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)), | |
11038 | crtc->unpin_work->flip_count); | |
11039 | } | |
11040 | ||
6b95a207 KH |
11041 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
11042 | { | |
fbee40df | 11043 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
11044 | struct intel_crtc *intel_crtc = |
11045 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
11046 | unsigned long flags; | |
11047 | ||
f326038a DV |
11048 | |
11049 | /* | |
11050 | * This is called both by irq handlers and the reset code (to complete | |
11051 | * lost pageflips) so needs the full irqsave spinlocks. | |
11052 | * | |
11053 | * NB: An MMIO update of the plane base pointer will also | |
e7d841ca CW |
11054 | * generate a page-flip completion irq, i.e. every modeset |
11055 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
11056 | */ | |
6b95a207 | 11057 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 11058 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 11059 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
11060 | spin_unlock_irqrestore(&dev->event_lock, flags); |
11061 | } | |
11062 | ||
eba905b2 | 11063 | static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
e7d841ca CW |
11064 | { |
11065 | /* Ensure that the work item is consistent when activating it ... */ | |
11066 | smp_wmb(); | |
11067 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
11068 | /* and that it is marked active as soon as the irq could fire. */ | |
11069 | smp_wmb(); | |
11070 | } | |
11071 | ||
8c9f3aaf JB |
11072 | static int intel_gen2_queue_flip(struct drm_device *dev, |
11073 | struct drm_crtc *crtc, | |
11074 | struct drm_framebuffer *fb, | |
ed8d1975 | 11075 | struct drm_i915_gem_object *obj, |
a4872ba6 | 11076 | struct intel_engine_cs *ring, |
ed8d1975 | 11077 | uint32_t flags) |
8c9f3aaf | 11078 | { |
8c9f3aaf | 11079 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
11080 | u32 flip_mask; |
11081 | int ret; | |
11082 | ||
6d90c952 | 11083 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 11084 | if (ret) |
4fa62c89 | 11085 | return ret; |
8c9f3aaf JB |
11086 | |
11087 | /* Can't queue multiple flips, so wait for the previous | |
11088 | * one to finish before executing the next. | |
11089 | */ | |
11090 | if (intel_crtc->plane) | |
11091 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11092 | else | |
11093 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
11094 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
11095 | intel_ring_emit(ring, MI_NOOP); | |
11096 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
11097 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11098 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 11099 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 | 11100 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
11101 | |
11102 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 11103 | __intel_ring_advance(ring); |
83d4092b | 11104 | return 0; |
8c9f3aaf JB |
11105 | } |
11106 | ||
11107 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
11108 | struct drm_crtc *crtc, | |
11109 | struct drm_framebuffer *fb, | |
ed8d1975 | 11110 | struct drm_i915_gem_object *obj, |
a4872ba6 | 11111 | struct intel_engine_cs *ring, |
ed8d1975 | 11112 | uint32_t flags) |
8c9f3aaf | 11113 | { |
8c9f3aaf | 11114 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
11115 | u32 flip_mask; |
11116 | int ret; | |
11117 | ||
6d90c952 | 11118 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 11119 | if (ret) |
4fa62c89 | 11120 | return ret; |
8c9f3aaf JB |
11121 | |
11122 | if (intel_crtc->plane) | |
11123 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11124 | else | |
11125 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
11126 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
11127 | intel_ring_emit(ring, MI_NOOP); | |
11128 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
11129 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11130 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 11131 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 DV |
11132 | intel_ring_emit(ring, MI_NOOP); |
11133 | ||
e7d841ca | 11134 | intel_mark_page_flip_active(intel_crtc); |
09246732 | 11135 | __intel_ring_advance(ring); |
83d4092b | 11136 | return 0; |
8c9f3aaf JB |
11137 | } |
11138 | ||
11139 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
11140 | struct drm_crtc *crtc, | |
11141 | struct drm_framebuffer *fb, | |
ed8d1975 | 11142 | struct drm_i915_gem_object *obj, |
a4872ba6 | 11143 | struct intel_engine_cs *ring, |
ed8d1975 | 11144 | uint32_t flags) |
8c9f3aaf JB |
11145 | { |
11146 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11147 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11148 | uint32_t pf, pipesrc; | |
11149 | int ret; | |
11150 | ||
6d90c952 | 11151 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 11152 | if (ret) |
4fa62c89 | 11153 | return ret; |
8c9f3aaf JB |
11154 | |
11155 | /* i965+ uses the linear or tiled offsets from the | |
11156 | * Display Registers (which do not change across a page-flip) | |
11157 | * so we need only reprogram the base address. | |
11158 | */ | |
6d90c952 DV |
11159 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
11160 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11161 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 11162 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
c2c75131 | 11163 | obj->tiling_mode); |
8c9f3aaf JB |
11164 | |
11165 | /* XXX Enabling the panel-fitter across page-flip is so far | |
11166 | * untested on non-native modes, so ignore it for now. | |
11167 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
11168 | */ | |
11169 | pf = 0; | |
11170 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 11171 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
11172 | |
11173 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 11174 | __intel_ring_advance(ring); |
83d4092b | 11175 | return 0; |
8c9f3aaf JB |
11176 | } |
11177 | ||
11178 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
11179 | struct drm_crtc *crtc, | |
11180 | struct drm_framebuffer *fb, | |
ed8d1975 | 11181 | struct drm_i915_gem_object *obj, |
a4872ba6 | 11182 | struct intel_engine_cs *ring, |
ed8d1975 | 11183 | uint32_t flags) |
8c9f3aaf JB |
11184 | { |
11185 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11186 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11187 | uint32_t pf, pipesrc; | |
11188 | int ret; | |
11189 | ||
6d90c952 | 11190 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 11191 | if (ret) |
4fa62c89 | 11192 | return ret; |
8c9f3aaf | 11193 | |
6d90c952 DV |
11194 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
11195 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11196 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
75f7f3ec | 11197 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8c9f3aaf | 11198 | |
dc257cf1 DV |
11199 | /* Contrary to the suggestions in the documentation, |
11200 | * "Enable Panel Fitter" does not seem to be required when page | |
11201 | * flipping with a non-native mode, and worse causes a normal | |
11202 | * modeset to fail. | |
11203 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
11204 | */ | |
11205 | pf = 0; | |
8c9f3aaf | 11206 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 11207 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
11208 | |
11209 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 11210 | __intel_ring_advance(ring); |
83d4092b | 11211 | return 0; |
8c9f3aaf JB |
11212 | } |
11213 | ||
7c9017e5 JB |
11214 | static int intel_gen7_queue_flip(struct drm_device *dev, |
11215 | struct drm_crtc *crtc, | |
11216 | struct drm_framebuffer *fb, | |
ed8d1975 | 11217 | struct drm_i915_gem_object *obj, |
a4872ba6 | 11218 | struct intel_engine_cs *ring, |
ed8d1975 | 11219 | uint32_t flags) |
7c9017e5 | 11220 | { |
7c9017e5 | 11221 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 11222 | uint32_t plane_bit = 0; |
ffe74d75 CW |
11223 | int len, ret; |
11224 | ||
eba905b2 | 11225 | switch (intel_crtc->plane) { |
cb05d8de DV |
11226 | case PLANE_A: |
11227 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
11228 | break; | |
11229 | case PLANE_B: | |
11230 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
11231 | break; | |
11232 | case PLANE_C: | |
11233 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
11234 | break; | |
11235 | default: | |
11236 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 11237 | return -ENODEV; |
cb05d8de DV |
11238 | } |
11239 | ||
ffe74d75 | 11240 | len = 4; |
f476828a | 11241 | if (ring->id == RCS) { |
ffe74d75 | 11242 | len += 6; |
f476828a DL |
11243 | /* |
11244 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
11245 | * 48bits addresses, and we need a NOOP for the batch size to | |
11246 | * stay even. | |
11247 | */ | |
11248 | if (IS_GEN8(dev)) | |
11249 | len += 2; | |
11250 | } | |
ffe74d75 | 11251 | |
f66fab8e VS |
11252 | /* |
11253 | * BSpec MI_DISPLAY_FLIP for IVB: | |
11254 | * "The full packet must be contained within the same cache line." | |
11255 | * | |
11256 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
11257 | * cacheline, if we ever start emitting more commands before | |
11258 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
11259 | * then do the cacheline alignment, and finally emit the | |
11260 | * MI_DISPLAY_FLIP. | |
11261 | */ | |
11262 | ret = intel_ring_cacheline_align(ring); | |
11263 | if (ret) | |
4fa62c89 | 11264 | return ret; |
f66fab8e | 11265 | |
ffe74d75 | 11266 | ret = intel_ring_begin(ring, len); |
7c9017e5 | 11267 | if (ret) |
4fa62c89 | 11268 | return ret; |
7c9017e5 | 11269 | |
ffe74d75 CW |
11270 | /* Unmask the flip-done completion message. Note that the bspec says that |
11271 | * we should do this for both the BCS and RCS, and that we must not unmask | |
11272 | * more than one flip event at any time (or ensure that one flip message | |
11273 | * can be sent by waiting for flip-done prior to queueing new flips). | |
11274 | * Experimentation says that BCS works despite DERRMR masking all | |
11275 | * flip-done completion events and that unmasking all planes at once | |
11276 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
11277 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
11278 | */ | |
11279 | if (ring->id == RCS) { | |
11280 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
11281 | intel_ring_emit(ring, DERRMR); | |
11282 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
11283 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
11284 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a DL |
11285 | if (IS_GEN8(dev)) |
11286 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) | | |
11287 | MI_SRM_LRM_GLOBAL_GTT); | |
11288 | else | |
11289 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | | |
11290 | MI_SRM_LRM_GLOBAL_GTT); | |
ffe74d75 CW |
11291 | intel_ring_emit(ring, DERRMR); |
11292 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
f476828a DL |
11293 | if (IS_GEN8(dev)) { |
11294 | intel_ring_emit(ring, 0); | |
11295 | intel_ring_emit(ring, MI_NOOP); | |
11296 | } | |
ffe74d75 CW |
11297 | } |
11298 | ||
cb05d8de | 11299 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 11300 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
75f7f3ec | 11301 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
7c9017e5 | 11302 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
11303 | |
11304 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 11305 | __intel_ring_advance(ring); |
83d4092b | 11306 | return 0; |
7c9017e5 JB |
11307 | } |
11308 | ||
84c33a64 SG |
11309 | static bool use_mmio_flip(struct intel_engine_cs *ring, |
11310 | struct drm_i915_gem_object *obj) | |
11311 | { | |
11312 | /* | |
11313 | * This is not being used for older platforms, because | |
11314 | * non-availability of flip done interrupt forces us to use | |
11315 | * CS flips. Older platforms derive flip done using some clever | |
11316 | * tricks involving the flip_pending status bits and vblank irqs. | |
11317 | * So using MMIO flips there would disrupt this mechanism. | |
11318 | */ | |
11319 | ||
8e09bf83 CW |
11320 | if (ring == NULL) |
11321 | return true; | |
11322 | ||
84c33a64 SG |
11323 | if (INTEL_INFO(ring->dev)->gen < 5) |
11324 | return false; | |
11325 | ||
11326 | if (i915.use_mmio_flip < 0) | |
11327 | return false; | |
11328 | else if (i915.use_mmio_flip > 0) | |
11329 | return true; | |
14bf993e OM |
11330 | else if (i915.enable_execlists) |
11331 | return true; | |
84c33a64 | 11332 | else |
b4716185 | 11333 | return ring != i915_gem_request_get_ring(obj->last_write_req); |
84c33a64 SG |
11334 | } |
11335 | ||
ff944564 DL |
11336 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc) |
11337 | { | |
11338 | struct drm_device *dev = intel_crtc->base.dev; | |
11339 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11340 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; | |
ff944564 DL |
11341 | const enum pipe pipe = intel_crtc->pipe; |
11342 | u32 ctl, stride; | |
11343 | ||
11344 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
11345 | ctl &= ~PLANE_CTL_TILED_MASK; | |
2ebef630 TU |
11346 | switch (fb->modifier[0]) { |
11347 | case DRM_FORMAT_MOD_NONE: | |
11348 | break; | |
11349 | case I915_FORMAT_MOD_X_TILED: | |
ff944564 | 11350 | ctl |= PLANE_CTL_TILED_X; |
2ebef630 TU |
11351 | break; |
11352 | case I915_FORMAT_MOD_Y_TILED: | |
11353 | ctl |= PLANE_CTL_TILED_Y; | |
11354 | break; | |
11355 | case I915_FORMAT_MOD_Yf_TILED: | |
11356 | ctl |= PLANE_CTL_TILED_YF; | |
11357 | break; | |
11358 | default: | |
11359 | MISSING_CASE(fb->modifier[0]); | |
11360 | } | |
ff944564 DL |
11361 | |
11362 | /* | |
11363 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
11364 | * linear buffers or in number of tiles for tiled buffers. | |
11365 | */ | |
2ebef630 TU |
11366 | stride = fb->pitches[0] / |
11367 | intel_fb_stride_alignment(dev, fb->modifier[0], | |
11368 | fb->pixel_format); | |
ff944564 DL |
11369 | |
11370 | /* | |
11371 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
11372 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
11373 | */ | |
11374 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
11375 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
11376 | ||
11377 | I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset); | |
11378 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
11379 | } | |
11380 | ||
11381 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc) | |
84c33a64 SG |
11382 | { |
11383 | struct drm_device *dev = intel_crtc->base.dev; | |
11384 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11385 | struct intel_framebuffer *intel_fb = | |
11386 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
11387 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
11388 | u32 dspcntr; | |
11389 | u32 reg; | |
11390 | ||
84c33a64 SG |
11391 | reg = DSPCNTR(intel_crtc->plane); |
11392 | dspcntr = I915_READ(reg); | |
11393 | ||
c5d97472 DL |
11394 | if (obj->tiling_mode != I915_TILING_NONE) |
11395 | dspcntr |= DISPPLANE_TILED; | |
11396 | else | |
11397 | dspcntr &= ~DISPPLANE_TILED; | |
11398 | ||
84c33a64 SG |
11399 | I915_WRITE(reg, dspcntr); |
11400 | ||
11401 | I915_WRITE(DSPSURF(intel_crtc->plane), | |
11402 | intel_crtc->unpin_work->gtt_offset); | |
11403 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
84c33a64 | 11404 | |
ff944564 DL |
11405 | } |
11406 | ||
11407 | /* | |
11408 | * XXX: This is the temporary way to update the plane registers until we get | |
11409 | * around to using the usual plane update functions for MMIO flips | |
11410 | */ | |
11411 | static void intel_do_mmio_flip(struct intel_crtc *intel_crtc) | |
11412 | { | |
11413 | struct drm_device *dev = intel_crtc->base.dev; | |
11414 | bool atomic_update; | |
11415 | u32 start_vbl_count; | |
11416 | ||
11417 | intel_mark_page_flip_active(intel_crtc); | |
11418 | ||
11419 | atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count); | |
11420 | ||
11421 | if (INTEL_INFO(dev)->gen >= 9) | |
11422 | skl_do_mmio_flip(intel_crtc); | |
11423 | else | |
11424 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
11425 | ilk_do_mmio_flip(intel_crtc); | |
11426 | ||
9362c7c5 ACO |
11427 | if (atomic_update) |
11428 | intel_pipe_update_end(intel_crtc, start_vbl_count); | |
84c33a64 SG |
11429 | } |
11430 | ||
9362c7c5 | 11431 | static void intel_mmio_flip_work_func(struct work_struct *work) |
84c33a64 | 11432 | { |
b2cfe0ab CW |
11433 | struct intel_mmio_flip *mmio_flip = |
11434 | container_of(work, struct intel_mmio_flip, work); | |
84c33a64 | 11435 | |
eed29a5b DV |
11436 | if (mmio_flip->req) |
11437 | WARN_ON(__i915_wait_request(mmio_flip->req, | |
b2cfe0ab | 11438 | mmio_flip->crtc->reset_counter, |
bcafc4e3 CW |
11439 | false, NULL, |
11440 | &mmio_flip->i915->rps.mmioflips)); | |
84c33a64 | 11441 | |
b2cfe0ab CW |
11442 | intel_do_mmio_flip(mmio_flip->crtc); |
11443 | ||
eed29a5b | 11444 | i915_gem_request_unreference__unlocked(mmio_flip->req); |
b2cfe0ab | 11445 | kfree(mmio_flip); |
84c33a64 SG |
11446 | } |
11447 | ||
11448 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
11449 | struct drm_crtc *crtc, | |
11450 | struct drm_framebuffer *fb, | |
11451 | struct drm_i915_gem_object *obj, | |
11452 | struct intel_engine_cs *ring, | |
11453 | uint32_t flags) | |
11454 | { | |
b2cfe0ab CW |
11455 | struct intel_mmio_flip *mmio_flip; |
11456 | ||
11457 | mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL); | |
11458 | if (mmio_flip == NULL) | |
11459 | return -ENOMEM; | |
84c33a64 | 11460 | |
bcafc4e3 | 11461 | mmio_flip->i915 = to_i915(dev); |
eed29a5b | 11462 | mmio_flip->req = i915_gem_request_reference(obj->last_write_req); |
b2cfe0ab | 11463 | mmio_flip->crtc = to_intel_crtc(crtc); |
536f5b5e | 11464 | |
b2cfe0ab CW |
11465 | INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func); |
11466 | schedule_work(&mmio_flip->work); | |
84c33a64 | 11467 | |
84c33a64 SG |
11468 | return 0; |
11469 | } | |
11470 | ||
8c9f3aaf JB |
11471 | static int intel_default_queue_flip(struct drm_device *dev, |
11472 | struct drm_crtc *crtc, | |
11473 | struct drm_framebuffer *fb, | |
ed8d1975 | 11474 | struct drm_i915_gem_object *obj, |
a4872ba6 | 11475 | struct intel_engine_cs *ring, |
ed8d1975 | 11476 | uint32_t flags) |
8c9f3aaf JB |
11477 | { |
11478 | return -ENODEV; | |
11479 | } | |
11480 | ||
d6bbafa1 CW |
11481 | static bool __intel_pageflip_stall_check(struct drm_device *dev, |
11482 | struct drm_crtc *crtc) | |
11483 | { | |
11484 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11485 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11486 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
11487 | u32 addr; | |
11488 | ||
11489 | if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) | |
11490 | return true; | |
11491 | ||
11492 | if (!work->enable_stall_check) | |
11493 | return false; | |
11494 | ||
11495 | if (work->flip_ready_vblank == 0) { | |
3a8a946e DV |
11496 | if (work->flip_queued_req && |
11497 | !i915_gem_request_completed(work->flip_queued_req, true)) | |
d6bbafa1 CW |
11498 | return false; |
11499 | ||
1e3feefd | 11500 | work->flip_ready_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 CW |
11501 | } |
11502 | ||
1e3feefd | 11503 | if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) |
d6bbafa1 CW |
11504 | return false; |
11505 | ||
11506 | /* Potential stall - if we see that the flip has happened, | |
11507 | * assume a missed interrupt. */ | |
11508 | if (INTEL_INFO(dev)->gen >= 4) | |
11509 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
11510 | else | |
11511 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
11512 | ||
11513 | /* There is a potential issue here with a false positive after a flip | |
11514 | * to the same address. We could address this by checking for a | |
11515 | * non-incrementing frame counter. | |
11516 | */ | |
11517 | return addr == work->gtt_offset; | |
11518 | } | |
11519 | ||
11520 | void intel_check_page_flip(struct drm_device *dev, int pipe) | |
11521 | { | |
11522 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11523 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
11524 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6ad790c0 | 11525 | struct intel_unpin_work *work; |
f326038a | 11526 | |
6c51d46f | 11527 | WARN_ON(!in_interrupt()); |
d6bbafa1 CW |
11528 | |
11529 | if (crtc == NULL) | |
11530 | return; | |
11531 | ||
f326038a | 11532 | spin_lock(&dev->event_lock); |
6ad790c0 CW |
11533 | work = intel_crtc->unpin_work; |
11534 | if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) { | |
d6bbafa1 | 11535 | WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", |
6ad790c0 | 11536 | work->flip_queued_vblank, drm_vblank_count(dev, pipe)); |
d6bbafa1 | 11537 | page_flip_completed(intel_crtc); |
6ad790c0 | 11538 | work = NULL; |
d6bbafa1 | 11539 | } |
6ad790c0 CW |
11540 | if (work != NULL && |
11541 | drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1) | |
11542 | intel_queue_rps_boost_for_request(dev, work->flip_queued_req); | |
f326038a | 11543 | spin_unlock(&dev->event_lock); |
d6bbafa1 CW |
11544 | } |
11545 | ||
6b95a207 KH |
11546 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
11547 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
11548 | struct drm_pending_vblank_event *event, |
11549 | uint32_t page_flip_flags) | |
6b95a207 KH |
11550 | { |
11551 | struct drm_device *dev = crtc->dev; | |
11552 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 11553 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 11554 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 | 11555 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
455a6808 | 11556 | struct drm_plane *primary = crtc->primary; |
a071fa00 | 11557 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 11558 | struct intel_unpin_work *work; |
a4872ba6 | 11559 | struct intel_engine_cs *ring; |
cf5d8a46 | 11560 | bool mmio_flip; |
52e68630 | 11561 | int ret; |
6b95a207 | 11562 | |
2ff8fde1 MR |
11563 | /* |
11564 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
11565 | * check to be safe. In the future we may enable pageflipping from | |
11566 | * a disabled primary plane. | |
11567 | */ | |
11568 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
11569 | return -EBUSY; | |
11570 | ||
e6a595d2 | 11571 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 11572 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
11573 | return -EINVAL; |
11574 | ||
11575 | /* | |
11576 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
11577 | * Note that pitch changes could also affect these register. | |
11578 | */ | |
11579 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
11580 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
11581 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
11582 | return -EINVAL; |
11583 | ||
f900db47 CW |
11584 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
11585 | goto out_hang; | |
11586 | ||
b14c5679 | 11587 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
11588 | if (work == NULL) |
11589 | return -ENOMEM; | |
11590 | ||
6b95a207 | 11591 | work->event = event; |
b4a98e57 | 11592 | work->crtc = crtc; |
ab8d6675 | 11593 | work->old_fb = old_fb; |
6b95a207 KH |
11594 | INIT_WORK(&work->work, intel_unpin_work_fn); |
11595 | ||
87b6b101 | 11596 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
11597 | if (ret) |
11598 | goto free_work; | |
11599 | ||
6b95a207 | 11600 | /* We borrow the event spin lock for protecting unpin_work */ |
5e2d7afc | 11601 | spin_lock_irq(&dev->event_lock); |
6b95a207 | 11602 | if (intel_crtc->unpin_work) { |
d6bbafa1 CW |
11603 | /* Before declaring the flip queue wedged, check if |
11604 | * the hardware completed the operation behind our backs. | |
11605 | */ | |
11606 | if (__intel_pageflip_stall_check(dev, crtc)) { | |
11607 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
11608 | page_flip_completed(intel_crtc); | |
11609 | } else { | |
11610 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
5e2d7afc | 11611 | spin_unlock_irq(&dev->event_lock); |
468f0b44 | 11612 | |
d6bbafa1 CW |
11613 | drm_crtc_vblank_put(crtc); |
11614 | kfree(work); | |
11615 | return -EBUSY; | |
11616 | } | |
6b95a207 KH |
11617 | } |
11618 | intel_crtc->unpin_work = work; | |
5e2d7afc | 11619 | spin_unlock_irq(&dev->event_lock); |
6b95a207 | 11620 | |
b4a98e57 CW |
11621 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
11622 | flush_workqueue(dev_priv->wq); | |
11623 | ||
75dfca80 | 11624 | /* Reference the objects for the scheduled work. */ |
ab8d6675 | 11625 | drm_framebuffer_reference(work->old_fb); |
05394f39 | 11626 | drm_gem_object_reference(&obj->base); |
6b95a207 | 11627 | |
f4510a27 | 11628 | crtc->primary->fb = fb; |
afd65eb4 | 11629 | update_state_fb(crtc->primary); |
1ed1f968 | 11630 | |
e1f99ce6 | 11631 | work->pending_flip_obj = obj; |
e1f99ce6 | 11632 | |
89ed88ba CW |
11633 | ret = i915_mutex_lock_interruptible(dev); |
11634 | if (ret) | |
11635 | goto cleanup; | |
11636 | ||
b4a98e57 | 11637 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 11638 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 11639 | |
75f7f3ec | 11640 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
a071fa00 | 11641 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1; |
75f7f3ec | 11642 | |
4fa62c89 VS |
11643 | if (IS_VALLEYVIEW(dev)) { |
11644 | ring = &dev_priv->ring[BCS]; | |
ab8d6675 | 11645 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) |
8e09bf83 CW |
11646 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
11647 | ring = NULL; | |
48bf5b2d | 11648 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
2a92d5bc | 11649 | ring = &dev_priv->ring[BCS]; |
4fa62c89 | 11650 | } else if (INTEL_INFO(dev)->gen >= 7) { |
b4716185 | 11651 | ring = i915_gem_request_get_ring(obj->last_write_req); |
4fa62c89 VS |
11652 | if (ring == NULL || ring->id != RCS) |
11653 | ring = &dev_priv->ring[BCS]; | |
11654 | } else { | |
11655 | ring = &dev_priv->ring[RCS]; | |
11656 | } | |
11657 | ||
cf5d8a46 CW |
11658 | mmio_flip = use_mmio_flip(ring, obj); |
11659 | ||
11660 | /* When using CS flips, we want to emit semaphores between rings. | |
11661 | * However, when using mmio flips we will create a task to do the | |
11662 | * synchronisation, so all we want here is to pin the framebuffer | |
11663 | * into the display plane and skip any waits. | |
11664 | */ | |
82bc3b2d | 11665 | ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, |
cf5d8a46 | 11666 | crtc->primary->state, |
b4716185 | 11667 | mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring); |
8c9f3aaf JB |
11668 | if (ret) |
11669 | goto cleanup_pending; | |
6b95a207 | 11670 | |
121920fa TU |
11671 | work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj) |
11672 | + intel_crtc->dspaddr_offset; | |
4fa62c89 | 11673 | |
cf5d8a46 | 11674 | if (mmio_flip) { |
84c33a64 SG |
11675 | ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring, |
11676 | page_flip_flags); | |
d6bbafa1 CW |
11677 | if (ret) |
11678 | goto cleanup_unpin; | |
11679 | ||
f06cc1b9 JH |
11680 | i915_gem_request_assign(&work->flip_queued_req, |
11681 | obj->last_write_req); | |
d6bbafa1 | 11682 | } else { |
d94b5030 CW |
11683 | if (obj->last_write_req) { |
11684 | ret = i915_gem_check_olr(obj->last_write_req); | |
11685 | if (ret) | |
11686 | goto cleanup_unpin; | |
11687 | } | |
11688 | ||
84c33a64 | 11689 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, |
d6bbafa1 CW |
11690 | page_flip_flags); |
11691 | if (ret) | |
11692 | goto cleanup_unpin; | |
11693 | ||
f06cc1b9 JH |
11694 | i915_gem_request_assign(&work->flip_queued_req, |
11695 | intel_ring_get_request(ring)); | |
d6bbafa1 CW |
11696 | } |
11697 | ||
1e3feefd | 11698 | work->flip_queued_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 | 11699 | work->enable_stall_check = true; |
4fa62c89 | 11700 | |
ab8d6675 | 11701 | i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, |
a071fa00 DV |
11702 | INTEL_FRONTBUFFER_PRIMARY(pipe)); |
11703 | ||
7ff0ebcc | 11704 | intel_fbc_disable(dev); |
f99d7069 | 11705 | intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
6b95a207 KH |
11706 | mutex_unlock(&dev->struct_mutex); |
11707 | ||
e5510fac JB |
11708 | trace_i915_flip_request(intel_crtc->plane, obj); |
11709 | ||
6b95a207 | 11710 | return 0; |
96b099fd | 11711 | |
4fa62c89 | 11712 | cleanup_unpin: |
82bc3b2d | 11713 | intel_unpin_fb_obj(fb, crtc->primary->state); |
8c9f3aaf | 11714 | cleanup_pending: |
b4a98e57 | 11715 | atomic_dec(&intel_crtc->unpin_work_count); |
89ed88ba CW |
11716 | mutex_unlock(&dev->struct_mutex); |
11717 | cleanup: | |
f4510a27 | 11718 | crtc->primary->fb = old_fb; |
afd65eb4 | 11719 | update_state_fb(crtc->primary); |
89ed88ba CW |
11720 | |
11721 | drm_gem_object_unreference_unlocked(&obj->base); | |
ab8d6675 | 11722 | drm_framebuffer_unreference(work->old_fb); |
96b099fd | 11723 | |
5e2d7afc | 11724 | spin_lock_irq(&dev->event_lock); |
96b099fd | 11725 | intel_crtc->unpin_work = NULL; |
5e2d7afc | 11726 | spin_unlock_irq(&dev->event_lock); |
96b099fd | 11727 | |
87b6b101 | 11728 | drm_crtc_vblank_put(crtc); |
7317c75e | 11729 | free_work: |
96b099fd CW |
11730 | kfree(work); |
11731 | ||
f900db47 CW |
11732 | if (ret == -EIO) { |
11733 | out_hang: | |
53a366b9 | 11734 | ret = intel_plane_restore(primary); |
f0d3dad3 | 11735 | if (ret == 0 && event) { |
5e2d7afc | 11736 | spin_lock_irq(&dev->event_lock); |
a071fa00 | 11737 | drm_send_vblank_event(dev, pipe, event); |
5e2d7afc | 11738 | spin_unlock_irq(&dev->event_lock); |
f0d3dad3 | 11739 | } |
f900db47 | 11740 | } |
96b099fd | 11741 | return ret; |
6b95a207 KH |
11742 | } |
11743 | ||
65b38e0d | 11744 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
11745 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
11746 | .load_lut = intel_crtc_load_lut, | |
ea2c67bb MR |
11747 | .atomic_begin = intel_begin_crtc_commit, |
11748 | .atomic_flush = intel_finish_crtc_commit, | |
f6e5b160 CW |
11749 | }; |
11750 | ||
9a935856 DV |
11751 | /** |
11752 | * intel_modeset_update_staged_output_state | |
11753 | * | |
11754 | * Updates the staged output configuration state, e.g. after we've read out the | |
11755 | * current hw state. | |
11756 | */ | |
11757 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) | |
f6e5b160 | 11758 | { |
7668851f | 11759 | struct intel_crtc *crtc; |
9a935856 DV |
11760 | struct intel_encoder *encoder; |
11761 | struct intel_connector *connector; | |
f6e5b160 | 11762 | |
3a3371ff | 11763 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
11764 | connector->new_encoder = |
11765 | to_intel_encoder(connector->base.encoder); | |
11766 | } | |
f6e5b160 | 11767 | |
b2784e15 | 11768 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
11769 | encoder->new_crtc = |
11770 | to_intel_crtc(encoder->base.crtc); | |
11771 | } | |
7668851f | 11772 | |
d3fcc808 | 11773 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 11774 | crtc->new_enabled = crtc->base.state->enable; |
7668851f | 11775 | } |
f6e5b160 CW |
11776 | } |
11777 | ||
d29b2f9d ACO |
11778 | /* Transitional helper to copy current connector/encoder state to |
11779 | * connector->state. This is needed so that code that is partially | |
11780 | * converted to atomic does the right thing. | |
11781 | */ | |
11782 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) | |
11783 | { | |
11784 | struct intel_connector *connector; | |
11785 | ||
11786 | for_each_intel_connector(dev, connector) { | |
11787 | if (connector->base.encoder) { | |
11788 | connector->base.state->best_encoder = | |
11789 | connector->base.encoder; | |
11790 | connector->base.state->crtc = | |
11791 | connector->base.encoder->crtc; | |
11792 | } else { | |
11793 | connector->base.state->best_encoder = NULL; | |
11794 | connector->base.state->crtc = NULL; | |
11795 | } | |
11796 | } | |
11797 | } | |
11798 | ||
a821fc46 | 11799 | /* Fixup legacy state after an atomic state swap. |
9a935856 | 11800 | */ |
a821fc46 | 11801 | static void intel_modeset_fixup_state(struct drm_atomic_state *state) |
9a935856 | 11802 | { |
a821fc46 | 11803 | struct intel_crtc *crtc; |
9a935856 | 11804 | struct intel_encoder *encoder; |
a821fc46 | 11805 | struct intel_connector *connector; |
d5432a9d | 11806 | |
a821fc46 ACO |
11807 | for_each_intel_connector(state->dev, connector) { |
11808 | connector->base.encoder = connector->base.state->best_encoder; | |
11809 | if (connector->base.encoder) | |
11810 | connector->base.encoder->crtc = | |
11811 | connector->base.state->crtc; | |
9a935856 | 11812 | } |
f6e5b160 | 11813 | |
d5432a9d ACO |
11814 | /* Update crtc of disabled encoders */ |
11815 | for_each_intel_encoder(state->dev, encoder) { | |
11816 | int num_connectors = 0; | |
11817 | ||
a821fc46 ACO |
11818 | for_each_intel_connector(state->dev, connector) |
11819 | if (connector->base.encoder == &encoder->base) | |
d5432a9d ACO |
11820 | num_connectors++; |
11821 | ||
11822 | if (num_connectors == 0) | |
11823 | encoder->base.crtc = NULL; | |
9a935856 | 11824 | } |
7668851f | 11825 | |
a821fc46 ACO |
11826 | for_each_intel_crtc(state->dev, crtc) { |
11827 | crtc->base.enabled = crtc->base.state->enable; | |
11828 | crtc->config = to_intel_crtc_state(crtc->base.state); | |
7668851f | 11829 | } |
d29b2f9d | 11830 | |
d5432a9d ACO |
11831 | /* Copy the new configuration to the staged state, to keep the few |
11832 | * pieces of code that haven't been converted yet happy */ | |
11833 | intel_modeset_update_staged_output_state(state->dev); | |
9a935856 DV |
11834 | } |
11835 | ||
050f7aeb | 11836 | static void |
eba905b2 | 11837 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 11838 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
11839 | { |
11840 | int bpp = pipe_config->pipe_bpp; | |
11841 | ||
11842 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
11843 | connector->base.base.id, | |
c23cc417 | 11844 | connector->base.name); |
050f7aeb DV |
11845 | |
11846 | /* Don't use an invalid EDID bpc value */ | |
11847 | if (connector->base.display_info.bpc && | |
11848 | connector->base.display_info.bpc * 3 < bpp) { | |
11849 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
11850 | bpp, connector->base.display_info.bpc*3); | |
11851 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
11852 | } | |
11853 | ||
11854 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
11855 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
11856 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
11857 | bpp); | |
11858 | pipe_config->pipe_bpp = 24; | |
11859 | } | |
11860 | } | |
11861 | ||
4e53c2e0 | 11862 | static int |
050f7aeb | 11863 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 11864 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 11865 | { |
050f7aeb | 11866 | struct drm_device *dev = crtc->base.dev; |
1486017f | 11867 | struct drm_atomic_state *state; |
da3ced29 ACO |
11868 | struct drm_connector *connector; |
11869 | struct drm_connector_state *connector_state; | |
1486017f | 11870 | int bpp, i; |
4e53c2e0 | 11871 | |
d328c9d7 | 11872 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev))) |
4e53c2e0 | 11873 | bpp = 10*3; |
d328c9d7 DV |
11874 | else if (INTEL_INFO(dev)->gen >= 5) |
11875 | bpp = 12*3; | |
11876 | else | |
11877 | bpp = 8*3; | |
11878 | ||
4e53c2e0 | 11879 | |
4e53c2e0 DV |
11880 | pipe_config->pipe_bpp = bpp; |
11881 | ||
1486017f ACO |
11882 | state = pipe_config->base.state; |
11883 | ||
4e53c2e0 | 11884 | /* Clamp display bpp to EDID value */ |
da3ced29 ACO |
11885 | for_each_connector_in_state(state, connector, connector_state, i) { |
11886 | if (connector_state->crtc != &crtc->base) | |
4e53c2e0 DV |
11887 | continue; |
11888 | ||
da3ced29 ACO |
11889 | connected_sink_compute_bpp(to_intel_connector(connector), |
11890 | pipe_config); | |
4e53c2e0 DV |
11891 | } |
11892 | ||
11893 | return bpp; | |
11894 | } | |
11895 | ||
644db711 DV |
11896 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
11897 | { | |
11898 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
11899 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 11900 | mode->crtc_clock, |
644db711 DV |
11901 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
11902 | mode->crtc_hsync_end, mode->crtc_htotal, | |
11903 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
11904 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
11905 | } | |
11906 | ||
c0b03411 | 11907 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 11908 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
11909 | const char *context) |
11910 | { | |
6a60cd87 CK |
11911 | struct drm_device *dev = crtc->base.dev; |
11912 | struct drm_plane *plane; | |
11913 | struct intel_plane *intel_plane; | |
11914 | struct intel_plane_state *state; | |
11915 | struct drm_framebuffer *fb; | |
11916 | ||
11917 | DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id, | |
11918 | context, pipe_config, pipe_name(crtc->pipe)); | |
c0b03411 DV |
11919 | |
11920 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
11921 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
11922 | pipe_config->pipe_bpp, pipe_config->dither); | |
11923 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
11924 | pipe_config->has_pch_encoder, | |
11925 | pipe_config->fdi_lanes, | |
11926 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
11927 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
11928 | pipe_config->fdi_m_n.tu); | |
eb14cb74 VS |
11929 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
11930 | pipe_config->has_dp_encoder, | |
11931 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, | |
11932 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
11933 | pipe_config->dp_m_n.tu); | |
b95af8be VK |
11934 | |
11935 | DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", | |
11936 | pipe_config->has_dp_encoder, | |
11937 | pipe_config->dp_m2_n2.gmch_m, | |
11938 | pipe_config->dp_m2_n2.gmch_n, | |
11939 | pipe_config->dp_m2_n2.link_m, | |
11940 | pipe_config->dp_m2_n2.link_n, | |
11941 | pipe_config->dp_m2_n2.tu); | |
11942 | ||
55072d19 DV |
11943 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
11944 | pipe_config->has_audio, | |
11945 | pipe_config->has_infoframe); | |
11946 | ||
c0b03411 | 11947 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 11948 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 11949 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
11950 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
11951 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 11952 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
11953 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
11954 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
0ec463d3 TU |
11955 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", |
11956 | crtc->num_scalers, | |
11957 | pipe_config->scaler_state.scaler_users, | |
11958 | pipe_config->scaler_state.scaler_id); | |
c0b03411 DV |
11959 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
11960 | pipe_config->gmch_pfit.control, | |
11961 | pipe_config->gmch_pfit.pgm_ratios, | |
11962 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 11963 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 11964 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
11965 | pipe_config->pch_pfit.size, |
11966 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 11967 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 11968 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
6a60cd87 | 11969 | |
415ff0f6 TU |
11970 | if (IS_BROXTON(dev)) { |
11971 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, " | |
11972 | "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " | |
11973 | "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n", | |
11974 | pipe_config->ddi_pll_sel, | |
11975 | pipe_config->dpll_hw_state.ebb0, | |
11976 | pipe_config->dpll_hw_state.pll0, | |
11977 | pipe_config->dpll_hw_state.pll1, | |
11978 | pipe_config->dpll_hw_state.pll2, | |
11979 | pipe_config->dpll_hw_state.pll3, | |
11980 | pipe_config->dpll_hw_state.pll6, | |
11981 | pipe_config->dpll_hw_state.pll8, | |
11982 | pipe_config->dpll_hw_state.pcsdw12); | |
11983 | } else if (IS_SKYLAKE(dev)) { | |
11984 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " | |
11985 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", | |
11986 | pipe_config->ddi_pll_sel, | |
11987 | pipe_config->dpll_hw_state.ctrl1, | |
11988 | pipe_config->dpll_hw_state.cfgcr1, | |
11989 | pipe_config->dpll_hw_state.cfgcr2); | |
11990 | } else if (HAS_DDI(dev)) { | |
11991 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n", | |
11992 | pipe_config->ddi_pll_sel, | |
11993 | pipe_config->dpll_hw_state.wrpll); | |
11994 | } else { | |
11995 | DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " | |
11996 | "fp0: 0x%x, fp1: 0x%x\n", | |
11997 | pipe_config->dpll_hw_state.dpll, | |
11998 | pipe_config->dpll_hw_state.dpll_md, | |
11999 | pipe_config->dpll_hw_state.fp0, | |
12000 | pipe_config->dpll_hw_state.fp1); | |
12001 | } | |
12002 | ||
6a60cd87 CK |
12003 | DRM_DEBUG_KMS("planes on this crtc\n"); |
12004 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
12005 | intel_plane = to_intel_plane(plane); | |
12006 | if (intel_plane->pipe != crtc->pipe) | |
12007 | continue; | |
12008 | ||
12009 | state = to_intel_plane_state(plane->state); | |
12010 | fb = state->base.fb; | |
12011 | if (!fb) { | |
12012 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d " | |
12013 | "disabled, scaler_id = %d\n", | |
12014 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12015 | plane->base.id, intel_plane->pipe, | |
12016 | (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1, | |
12017 | drm_plane_index(plane), state->scaler_id); | |
12018 | continue; | |
12019 | } | |
12020 | ||
12021 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled", | |
12022 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12023 | plane->base.id, intel_plane->pipe, | |
12024 | crtc->base.primary == plane ? 0 : intel_plane->plane + 1, | |
12025 | drm_plane_index(plane)); | |
12026 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x", | |
12027 | fb->base.id, fb->width, fb->height, fb->pixel_format); | |
12028 | DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n", | |
12029 | state->scaler_id, | |
12030 | state->src.x1 >> 16, state->src.y1 >> 16, | |
12031 | drm_rect_width(&state->src) >> 16, | |
12032 | drm_rect_height(&state->src) >> 16, | |
12033 | state->dst.x1, state->dst.y1, | |
12034 | drm_rect_width(&state->dst), drm_rect_height(&state->dst)); | |
12035 | } | |
c0b03411 DV |
12036 | } |
12037 | ||
bc079e8b VS |
12038 | static bool encoders_cloneable(const struct intel_encoder *a, |
12039 | const struct intel_encoder *b) | |
accfc0c5 | 12040 | { |
bc079e8b VS |
12041 | /* masks could be asymmetric, so check both ways */ |
12042 | return a == b || (a->cloneable & (1 << b->type) && | |
12043 | b->cloneable & (1 << a->type)); | |
12044 | } | |
12045 | ||
98a221da ACO |
12046 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, |
12047 | struct intel_crtc *crtc, | |
bc079e8b VS |
12048 | struct intel_encoder *encoder) |
12049 | { | |
bc079e8b | 12050 | struct intel_encoder *source_encoder; |
da3ced29 | 12051 | struct drm_connector *connector; |
98a221da ACO |
12052 | struct drm_connector_state *connector_state; |
12053 | int i; | |
bc079e8b | 12054 | |
da3ced29 | 12055 | for_each_connector_in_state(state, connector, connector_state, i) { |
98a221da | 12056 | if (connector_state->crtc != &crtc->base) |
bc079e8b VS |
12057 | continue; |
12058 | ||
98a221da ACO |
12059 | source_encoder = |
12060 | to_intel_encoder(connector_state->best_encoder); | |
bc079e8b VS |
12061 | if (!encoders_cloneable(encoder, source_encoder)) |
12062 | return false; | |
12063 | } | |
12064 | ||
12065 | return true; | |
12066 | } | |
12067 | ||
98a221da ACO |
12068 | static bool check_encoder_cloning(struct drm_atomic_state *state, |
12069 | struct intel_crtc *crtc) | |
bc079e8b | 12070 | { |
accfc0c5 | 12071 | struct intel_encoder *encoder; |
da3ced29 | 12072 | struct drm_connector *connector; |
98a221da ACO |
12073 | struct drm_connector_state *connector_state; |
12074 | int i; | |
accfc0c5 | 12075 | |
da3ced29 | 12076 | for_each_connector_in_state(state, connector, connector_state, i) { |
98a221da ACO |
12077 | if (connector_state->crtc != &crtc->base) |
12078 | continue; | |
12079 | ||
12080 | encoder = to_intel_encoder(connector_state->best_encoder); | |
12081 | if (!check_single_encoder_cloning(state, crtc, encoder)) | |
bc079e8b | 12082 | return false; |
accfc0c5 DV |
12083 | } |
12084 | ||
bc079e8b | 12085 | return true; |
accfc0c5 DV |
12086 | } |
12087 | ||
5448a00d | 12088 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 12089 | { |
5448a00d ACO |
12090 | struct drm_device *dev = state->dev; |
12091 | struct intel_encoder *encoder; | |
da3ced29 | 12092 | struct drm_connector *connector; |
5448a00d | 12093 | struct drm_connector_state *connector_state; |
00f0b378 | 12094 | unsigned int used_ports = 0; |
5448a00d | 12095 | int i; |
00f0b378 VS |
12096 | |
12097 | /* | |
12098 | * Walk the connector list instead of the encoder | |
12099 | * list to detect the problem on ddi platforms | |
12100 | * where there's just one encoder per digital port. | |
12101 | */ | |
da3ced29 | 12102 | for_each_connector_in_state(state, connector, connector_state, i) { |
5448a00d | 12103 | if (!connector_state->best_encoder) |
00f0b378 VS |
12104 | continue; |
12105 | ||
5448a00d ACO |
12106 | encoder = to_intel_encoder(connector_state->best_encoder); |
12107 | ||
12108 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
12109 | |
12110 | switch (encoder->type) { | |
12111 | unsigned int port_mask; | |
12112 | case INTEL_OUTPUT_UNKNOWN: | |
12113 | if (WARN_ON(!HAS_DDI(dev))) | |
12114 | break; | |
12115 | case INTEL_OUTPUT_DISPLAYPORT: | |
12116 | case INTEL_OUTPUT_HDMI: | |
12117 | case INTEL_OUTPUT_EDP: | |
12118 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
12119 | ||
12120 | /* the same port mustn't appear more than once */ | |
12121 | if (used_ports & port_mask) | |
12122 | return false; | |
12123 | ||
12124 | used_ports |= port_mask; | |
12125 | default: | |
12126 | break; | |
12127 | } | |
12128 | } | |
12129 | ||
12130 | return true; | |
12131 | } | |
12132 | ||
83a57153 ACO |
12133 | static void |
12134 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
12135 | { | |
12136 | struct drm_crtc_state tmp_state; | |
663a3640 | 12137 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 ACO |
12138 | struct intel_dpll_hw_state dpll_hw_state; |
12139 | enum intel_dpll_id shared_dpll; | |
8504c74c | 12140 | uint32_t ddi_pll_sel; |
83a57153 | 12141 | |
7546a384 ACO |
12142 | /* FIXME: before the switch to atomic started, a new pipe_config was |
12143 | * kzalloc'd. Code that depends on any field being zero should be | |
12144 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
12145 | * only fields that are know to not cause problems are preserved. */ | |
12146 | ||
83a57153 | 12147 | tmp_state = crtc_state->base; |
663a3640 | 12148 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
12149 | shared_dpll = crtc_state->shared_dpll; |
12150 | dpll_hw_state = crtc_state->dpll_hw_state; | |
8504c74c | 12151 | ddi_pll_sel = crtc_state->ddi_pll_sel; |
4978cc93 | 12152 | |
83a57153 | 12153 | memset(crtc_state, 0, sizeof *crtc_state); |
4978cc93 | 12154 | |
83a57153 | 12155 | crtc_state->base = tmp_state; |
663a3640 | 12156 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
12157 | crtc_state->shared_dpll = shared_dpll; |
12158 | crtc_state->dpll_hw_state = dpll_hw_state; | |
8504c74c | 12159 | crtc_state->ddi_pll_sel = ddi_pll_sel; |
83a57153 ACO |
12160 | } |
12161 | ||
548ee15b | 12162 | static int |
b8cecdf5 | 12163 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
548ee15b ACO |
12164 | struct drm_atomic_state *state, |
12165 | struct intel_crtc_state *pipe_config) | |
ee7b9f93 | 12166 | { |
7758a113 | 12167 | struct intel_encoder *encoder; |
da3ced29 | 12168 | struct drm_connector *connector; |
0b901879 | 12169 | struct drm_connector_state *connector_state; |
d328c9d7 | 12170 | int base_bpp, ret = -EINVAL; |
0b901879 | 12171 | int i; |
e29c22c0 | 12172 | bool retry = true; |
ee7b9f93 | 12173 | |
98a221da | 12174 | if (!check_encoder_cloning(state, to_intel_crtc(crtc))) { |
accfc0c5 | 12175 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
548ee15b | 12176 | return -EINVAL; |
accfc0c5 DV |
12177 | } |
12178 | ||
5448a00d | 12179 | if (!check_digital_port_conflicts(state)) { |
00f0b378 | 12180 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); |
548ee15b | 12181 | return -EINVAL; |
00f0b378 VS |
12182 | } |
12183 | ||
83a57153 | 12184 | clear_intel_crtc_state(pipe_config); |
7758a113 | 12185 | |
e143a21c DV |
12186 | pipe_config->cpu_transcoder = |
12187 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 12188 | |
2960bc9c ID |
12189 | /* |
12190 | * Sanitize sync polarity flags based on requested ones. If neither | |
12191 | * positive or negative polarity is requested, treat this as meaning | |
12192 | * negative polarity. | |
12193 | */ | |
2d112de7 | 12194 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12195 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 12196 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 12197 | |
2d112de7 | 12198 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12199 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 12200 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 12201 | |
050f7aeb DV |
12202 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
12203 | * plane pixel format and any sink constraints into account. Returns the | |
12204 | * source plane bpp so that dithering can be selected on mismatches | |
12205 | * after encoders and crtc also have had their say. */ | |
d328c9d7 DV |
12206 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
12207 | pipe_config); | |
12208 | if (base_bpp < 0) | |
4e53c2e0 DV |
12209 | goto fail; |
12210 | ||
e41a56be VS |
12211 | /* |
12212 | * Determine the real pipe dimensions. Note that stereo modes can | |
12213 | * increase the actual pipe size due to the frame doubling and | |
12214 | * insertion of additional space for blanks between the frame. This | |
12215 | * is stored in the crtc timings. We use the requested mode to do this | |
12216 | * computation to clearly distinguish it from the adjusted mode, which | |
12217 | * can be changed by the connectors in the below retry loop. | |
12218 | */ | |
2d112de7 | 12219 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
12220 | &pipe_config->pipe_src_w, |
12221 | &pipe_config->pipe_src_h); | |
e41a56be | 12222 | |
e29c22c0 | 12223 | encoder_retry: |
ef1b460d | 12224 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 12225 | pipe_config->port_clock = 0; |
ef1b460d | 12226 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 12227 | |
135c81b8 | 12228 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
12229 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
12230 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 12231 | |
7758a113 DV |
12232 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
12233 | * adjust it according to limitations or connector properties, and also | |
12234 | * a chance to reject the mode entirely. | |
47f1c6c9 | 12235 | */ |
da3ced29 | 12236 | for_each_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 12237 | if (connector_state->crtc != crtc) |
7758a113 | 12238 | continue; |
7ae89233 | 12239 | |
0b901879 ACO |
12240 | encoder = to_intel_encoder(connector_state->best_encoder); |
12241 | ||
efea6e8e DV |
12242 | if (!(encoder->compute_config(encoder, pipe_config))) { |
12243 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
12244 | goto fail; |
12245 | } | |
ee7b9f93 | 12246 | } |
47f1c6c9 | 12247 | |
ff9a6750 DV |
12248 | /* Set default port clock if not overwritten by the encoder. Needs to be |
12249 | * done afterwards in case the encoder adjusts the mode. */ | |
12250 | if (!pipe_config->port_clock) | |
2d112de7 | 12251 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 12252 | * pipe_config->pixel_multiplier; |
ff9a6750 | 12253 | |
a43f6e0f | 12254 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 12255 | if (ret < 0) { |
7758a113 DV |
12256 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
12257 | goto fail; | |
ee7b9f93 | 12258 | } |
e29c22c0 DV |
12259 | |
12260 | if (ret == RETRY) { | |
12261 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
12262 | ret = -EINVAL; | |
12263 | goto fail; | |
12264 | } | |
12265 | ||
12266 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
12267 | retry = false; | |
12268 | goto encoder_retry; | |
12269 | } | |
12270 | ||
d328c9d7 | 12271 | pipe_config->dither = pipe_config->pipe_bpp != base_bpp; |
4e53c2e0 | 12272 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 12273 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 12274 | |
548ee15b | 12275 | return 0; |
7758a113 | 12276 | fail: |
548ee15b | 12277 | return ret; |
ee7b9f93 | 12278 | } |
47f1c6c9 | 12279 | |
ea9d758d | 12280 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 12281 | { |
ea9d758d | 12282 | struct drm_encoder *encoder; |
f6e5b160 | 12283 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 12284 | |
ea9d758d DV |
12285 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
12286 | if (encoder->crtc == crtc) | |
12287 | return true; | |
12288 | ||
12289 | return false; | |
12290 | } | |
12291 | ||
0a9ab303 ACO |
12292 | static bool |
12293 | needs_modeset(struct drm_crtc_state *state) | |
12294 | { | |
12295 | return state->mode_changed || state->active_changed; | |
12296 | } | |
12297 | ||
ea9d758d | 12298 | static void |
0a9ab303 | 12299 | intel_modeset_update_state(struct drm_atomic_state *state) |
ea9d758d | 12300 | { |
0a9ab303 | 12301 | struct drm_device *dev = state->dev; |
ba41c0de | 12302 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea9d758d | 12303 | struct intel_encoder *intel_encoder; |
0a9ab303 ACO |
12304 | struct drm_crtc *crtc; |
12305 | struct drm_crtc_state *crtc_state; | |
ea9d758d | 12306 | struct drm_connector *connector; |
0a9ab303 | 12307 | int i; |
ea9d758d | 12308 | |
ba41c0de DV |
12309 | intel_shared_dpll_commit(dev_priv); |
12310 | ||
b2784e15 | 12311 | for_each_intel_encoder(dev, intel_encoder) { |
ea9d758d DV |
12312 | if (!intel_encoder->base.crtc) |
12313 | continue; | |
12314 | ||
bd4b4827 ACO |
12315 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
12316 | if (crtc != intel_encoder->base.crtc) | |
12317 | continue; | |
0a9ab303 | 12318 | |
bd4b4827 ACO |
12319 | if (crtc_state->enable && needs_modeset(crtc_state)) |
12320 | intel_encoder->connectors_active = false; | |
ea9d758d | 12321 | |
bd4b4827 ACO |
12322 | break; |
12323 | } | |
ea9d758d DV |
12324 | } |
12325 | ||
a821fc46 ACO |
12326 | drm_atomic_helper_swap_state(state->dev, state); |
12327 | intel_modeset_fixup_state(state); | |
ea9d758d | 12328 | |
7668851f | 12329 | /* Double check state. */ |
0a9ab303 ACO |
12330 | for_each_crtc(dev, crtc) { |
12331 | WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc)); | |
ea9d758d DV |
12332 | } |
12333 | ||
12334 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
12335 | if (!connector->encoder || !connector->encoder->crtc) | |
12336 | continue; | |
12337 | ||
bd4b4827 ACO |
12338 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
12339 | if (crtc != connector->encoder->crtc) | |
12340 | continue; | |
0a9ab303 | 12341 | |
bd4b4827 ACO |
12342 | if (crtc->state->enable && needs_modeset(crtc->state)) { |
12343 | struct drm_property *dpms_property = | |
12344 | dev->mode_config.dpms_property; | |
ea9d758d | 12345 | |
bd4b4827 ACO |
12346 | connector->dpms = DRM_MODE_DPMS_ON; |
12347 | drm_object_property_set_value(&connector->base, | |
12348 | dpms_property, | |
12349 | DRM_MODE_DPMS_ON); | |
68d34720 | 12350 | |
bd4b4827 ACO |
12351 | intel_encoder = to_intel_encoder(connector->encoder); |
12352 | intel_encoder->connectors_active = true; | |
12353 | } | |
ea9d758d | 12354 | |
bd4b4827 | 12355 | break; |
ea9d758d DV |
12356 | } |
12357 | } | |
12358 | ||
12359 | } | |
12360 | ||
3bd26263 | 12361 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 12362 | { |
3bd26263 | 12363 | int diff; |
f1f644dc JB |
12364 | |
12365 | if (clock1 == clock2) | |
12366 | return true; | |
12367 | ||
12368 | if (!clock1 || !clock2) | |
12369 | return false; | |
12370 | ||
12371 | diff = abs(clock1 - clock2); | |
12372 | ||
12373 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
12374 | return true; | |
12375 | ||
12376 | return false; | |
12377 | } | |
12378 | ||
25c5b266 DV |
12379 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
12380 | list_for_each_entry((intel_crtc), \ | |
12381 | &(dev)->mode_config.crtc_list, \ | |
12382 | base.head) \ | |
0973f18f | 12383 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 12384 | |
0e8ffe1b | 12385 | static bool |
2fa2fe9a | 12386 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b ACO |
12387 | struct intel_crtc_state *current_config, |
12388 | struct intel_crtc_state *pipe_config) | |
0e8ffe1b | 12389 | { |
66e985c0 DV |
12390 | #define PIPE_CONF_CHECK_X(name) \ |
12391 | if (current_config->name != pipe_config->name) { \ | |
12392 | DRM_ERROR("mismatch in " #name " " \ | |
12393 | "(expected 0x%08x, found 0x%08x)\n", \ | |
12394 | current_config->name, \ | |
12395 | pipe_config->name); \ | |
12396 | return false; \ | |
12397 | } | |
12398 | ||
08a24034 DV |
12399 | #define PIPE_CONF_CHECK_I(name) \ |
12400 | if (current_config->name != pipe_config->name) { \ | |
12401 | DRM_ERROR("mismatch in " #name " " \ | |
12402 | "(expected %i, found %i)\n", \ | |
12403 | current_config->name, \ | |
12404 | pipe_config->name); \ | |
12405 | return false; \ | |
88adfff1 DV |
12406 | } |
12407 | ||
b95af8be VK |
12408 | /* This is required for BDW+ where there is only one set of registers for |
12409 | * switching between high and low RR. | |
12410 | * This macro can be used whenever a comparison has to be made between one | |
12411 | * hw state and multiple sw state variables. | |
12412 | */ | |
12413 | #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ | |
12414 | if ((current_config->name != pipe_config->name) && \ | |
12415 | (current_config->alt_name != pipe_config->name)) { \ | |
12416 | DRM_ERROR("mismatch in " #name " " \ | |
12417 | "(expected %i or %i, found %i)\n", \ | |
12418 | current_config->name, \ | |
12419 | current_config->alt_name, \ | |
12420 | pipe_config->name); \ | |
12421 | return false; \ | |
12422 | } | |
12423 | ||
1bd1bd80 DV |
12424 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
12425 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
6f02488e | 12426 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
12427 | "(expected %i, found %i)\n", \ |
12428 | current_config->name & (mask), \ | |
12429 | pipe_config->name & (mask)); \ | |
12430 | return false; \ | |
12431 | } | |
12432 | ||
5e550656 VS |
12433 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
12434 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
12435 | DRM_ERROR("mismatch in " #name " " \ | |
12436 | "(expected %i, found %i)\n", \ | |
12437 | current_config->name, \ | |
12438 | pipe_config->name); \ | |
12439 | return false; \ | |
12440 | } | |
12441 | ||
bb760063 DV |
12442 | #define PIPE_CONF_QUIRK(quirk) \ |
12443 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
12444 | ||
eccb140b DV |
12445 | PIPE_CONF_CHECK_I(cpu_transcoder); |
12446 | ||
08a24034 DV |
12447 | PIPE_CONF_CHECK_I(has_pch_encoder); |
12448 | PIPE_CONF_CHECK_I(fdi_lanes); | |
72419203 DV |
12449 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
12450 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); | |
12451 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); | |
12452 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); | |
12453 | PIPE_CONF_CHECK_I(fdi_m_n.tu); | |
08a24034 | 12454 | |
eb14cb74 | 12455 | PIPE_CONF_CHECK_I(has_dp_encoder); |
b95af8be VK |
12456 | |
12457 | if (INTEL_INFO(dev)->gen < 8) { | |
12458 | PIPE_CONF_CHECK_I(dp_m_n.gmch_m); | |
12459 | PIPE_CONF_CHECK_I(dp_m_n.gmch_n); | |
12460 | PIPE_CONF_CHECK_I(dp_m_n.link_m); | |
12461 | PIPE_CONF_CHECK_I(dp_m_n.link_n); | |
12462 | PIPE_CONF_CHECK_I(dp_m_n.tu); | |
12463 | ||
12464 | if (current_config->has_drrs) { | |
12465 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m); | |
12466 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n); | |
12467 | PIPE_CONF_CHECK_I(dp_m2_n2.link_m); | |
12468 | PIPE_CONF_CHECK_I(dp_m2_n2.link_n); | |
12469 | PIPE_CONF_CHECK_I(dp_m2_n2.tu); | |
12470 | } | |
12471 | } else { | |
12472 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m); | |
12473 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n); | |
12474 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m); | |
12475 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n); | |
12476 | PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu); | |
12477 | } | |
eb14cb74 | 12478 | |
2d112de7 ACO |
12479 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
12480 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
12481 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
12482 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
12483 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
12484 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 12485 | |
2d112de7 ACO |
12486 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
12487 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
12488 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
12489 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
12490 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
12491 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 12492 | |
c93f54cf | 12493 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 12494 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 DV |
12495 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
12496 | IS_VALLEYVIEW(dev)) | |
12497 | PIPE_CONF_CHECK_I(limited_color_range); | |
e43823ec | 12498 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 12499 | |
9ed109a7 DV |
12500 | PIPE_CONF_CHECK_I(has_audio); |
12501 | ||
2d112de7 | 12502 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
12503 | DRM_MODE_FLAG_INTERLACE); |
12504 | ||
bb760063 | 12505 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 12506 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12507 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 12508 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12509 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 12510 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12511 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 12512 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
12513 | DRM_MODE_FLAG_NVSYNC); |
12514 | } | |
045ac3b5 | 12515 | |
37327abd VS |
12516 | PIPE_CONF_CHECK_I(pipe_src_w); |
12517 | PIPE_CONF_CHECK_I(pipe_src_h); | |
1bd1bd80 | 12518 | |
9953599b DV |
12519 | /* |
12520 | * FIXME: BIOS likes to set up a cloned config with lvds+external | |
12521 | * screen. Since we don't yet re-compute the pipe config when moving | |
12522 | * just the lvds port away to another pipe the sw tracking won't match. | |
12523 | * | |
12524 | * Proper atomic modesets with recomputed global state will fix this. | |
12525 | * Until then just don't check gmch state for inherited modes. | |
12526 | */ | |
12527 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) { | |
12528 | PIPE_CONF_CHECK_I(gmch_pfit.control); | |
12529 | /* pfit ratios are autocomputed by the hw on gen4+ */ | |
12530 | if (INTEL_INFO(dev)->gen < 4) | |
12531 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
12532 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); | |
12533 | } | |
12534 | ||
fd4daa9c CW |
12535 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
12536 | if (current_config->pch_pfit.enabled) { | |
12537 | PIPE_CONF_CHECK_I(pch_pfit.pos); | |
12538 | PIPE_CONF_CHECK_I(pch_pfit.size); | |
12539 | } | |
2fa2fe9a | 12540 | |
a1b2278e CK |
12541 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
12542 | ||
e59150dc JB |
12543 | /* BDW+ don't expose a synchronous way to read the state */ |
12544 | if (IS_HASWELL(dev)) | |
12545 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 12546 | |
282740f7 VS |
12547 | PIPE_CONF_CHECK_I(double_wide); |
12548 | ||
26804afd DV |
12549 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
12550 | ||
c0d43d62 | 12551 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 12552 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 12553 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
12554 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
12555 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 12556 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
3f4cd19f DL |
12557 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
12558 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
12559 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 12560 | |
42571aef VS |
12561 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
12562 | PIPE_CONF_CHECK_I(pipe_bpp); | |
12563 | ||
2d112de7 | 12564 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 12565 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 12566 | |
66e985c0 | 12567 | #undef PIPE_CONF_CHECK_X |
08a24034 | 12568 | #undef PIPE_CONF_CHECK_I |
b95af8be | 12569 | #undef PIPE_CONF_CHECK_I_ALT |
1bd1bd80 | 12570 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 12571 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 12572 | #undef PIPE_CONF_QUIRK |
88adfff1 | 12573 | |
0e8ffe1b DV |
12574 | return true; |
12575 | } | |
12576 | ||
08db6652 DL |
12577 | static void check_wm_state(struct drm_device *dev) |
12578 | { | |
12579 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12580 | struct skl_ddb_allocation hw_ddb, *sw_ddb; | |
12581 | struct intel_crtc *intel_crtc; | |
12582 | int plane; | |
12583 | ||
12584 | if (INTEL_INFO(dev)->gen < 9) | |
12585 | return; | |
12586 | ||
12587 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
12588 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
12589 | ||
12590 | for_each_intel_crtc(dev, intel_crtc) { | |
12591 | struct skl_ddb_entry *hw_entry, *sw_entry; | |
12592 | const enum pipe pipe = intel_crtc->pipe; | |
12593 | ||
12594 | if (!intel_crtc->active) | |
12595 | continue; | |
12596 | ||
12597 | /* planes */ | |
dd740780 | 12598 | for_each_plane(dev_priv, pipe, plane) { |
08db6652 DL |
12599 | hw_entry = &hw_ddb.plane[pipe][plane]; |
12600 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
12601 | ||
12602 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12603 | continue; | |
12604 | ||
12605 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " | |
12606 | "(expected (%u,%u), found (%u,%u))\n", | |
12607 | pipe_name(pipe), plane + 1, | |
12608 | sw_entry->start, sw_entry->end, | |
12609 | hw_entry->start, hw_entry->end); | |
12610 | } | |
12611 | ||
12612 | /* cursor */ | |
12613 | hw_entry = &hw_ddb.cursor[pipe]; | |
12614 | sw_entry = &sw_ddb->cursor[pipe]; | |
12615 | ||
12616 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12617 | continue; | |
12618 | ||
12619 | DRM_ERROR("mismatch in DDB state pipe %c cursor " | |
12620 | "(expected (%u,%u), found (%u,%u))\n", | |
12621 | pipe_name(pipe), | |
12622 | sw_entry->start, sw_entry->end, | |
12623 | hw_entry->start, hw_entry->end); | |
12624 | } | |
12625 | } | |
12626 | ||
91d1b4bd DV |
12627 | static void |
12628 | check_connector_state(struct drm_device *dev) | |
8af6cf88 | 12629 | { |
8af6cf88 DV |
12630 | struct intel_connector *connector; |
12631 | ||
3a3371ff | 12632 | for_each_intel_connector(dev, connector) { |
8af6cf88 DV |
12633 | /* This also checks the encoder/connector hw state with the |
12634 | * ->get_hw_state callbacks. */ | |
12635 | intel_connector_check_state(connector); | |
12636 | ||
e2c719b7 | 12637 | I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder, |
8af6cf88 DV |
12638 | "connector's staged encoder doesn't match current encoder\n"); |
12639 | } | |
91d1b4bd DV |
12640 | } |
12641 | ||
12642 | static void | |
12643 | check_encoder_state(struct drm_device *dev) | |
12644 | { | |
12645 | struct intel_encoder *encoder; | |
12646 | struct intel_connector *connector; | |
8af6cf88 | 12647 | |
b2784e15 | 12648 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 DV |
12649 | bool enabled = false; |
12650 | bool active = false; | |
12651 | enum pipe pipe, tracked_pipe; | |
12652 | ||
12653 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
12654 | encoder->base.base.id, | |
8e329a03 | 12655 | encoder->base.name); |
8af6cf88 | 12656 | |
e2c719b7 | 12657 | I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc, |
8af6cf88 | 12658 | "encoder's stage crtc doesn't match current crtc\n"); |
e2c719b7 | 12659 | I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc, |
8af6cf88 DV |
12660 | "encoder's active_connectors set, but no crtc\n"); |
12661 | ||
3a3371ff | 12662 | for_each_intel_connector(dev, connector) { |
8af6cf88 DV |
12663 | if (connector->base.encoder != &encoder->base) |
12664 | continue; | |
12665 | enabled = true; | |
12666 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
12667 | active = true; | |
12668 | } | |
0e32b39c DA |
12669 | /* |
12670 | * for MST connectors if we unplug the connector is gone | |
12671 | * away but the encoder is still connected to a crtc | |
12672 | * until a modeset happens in response to the hotplug. | |
12673 | */ | |
12674 | if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST) | |
12675 | continue; | |
12676 | ||
e2c719b7 | 12677 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
12678 | "encoder's enabled state mismatch " |
12679 | "(expected %i, found %i)\n", | |
12680 | !!encoder->base.crtc, enabled); | |
e2c719b7 | 12681 | I915_STATE_WARN(active && !encoder->base.crtc, |
8af6cf88 DV |
12682 | "active encoder with no crtc\n"); |
12683 | ||
e2c719b7 | 12684 | I915_STATE_WARN(encoder->connectors_active != active, |
8af6cf88 DV |
12685 | "encoder's computed active state doesn't match tracked active state " |
12686 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
12687 | ||
12688 | active = encoder->get_hw_state(encoder, &pipe); | |
e2c719b7 | 12689 | I915_STATE_WARN(active != encoder->connectors_active, |
8af6cf88 DV |
12690 | "encoder's hw state doesn't match sw tracking " |
12691 | "(expected %i, found %i)\n", | |
12692 | encoder->connectors_active, active); | |
12693 | ||
12694 | if (!encoder->base.crtc) | |
12695 | continue; | |
12696 | ||
12697 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
e2c719b7 | 12698 | I915_STATE_WARN(active && pipe != tracked_pipe, |
8af6cf88 DV |
12699 | "active encoder's pipe doesn't match" |
12700 | "(expected %i, found %i)\n", | |
12701 | tracked_pipe, pipe); | |
12702 | ||
12703 | } | |
91d1b4bd DV |
12704 | } |
12705 | ||
12706 | static void | |
12707 | check_crtc_state(struct drm_device *dev) | |
12708 | { | |
fbee40df | 12709 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
12710 | struct intel_crtc *crtc; |
12711 | struct intel_encoder *encoder; | |
5cec258b | 12712 | struct intel_crtc_state pipe_config; |
8af6cf88 | 12713 | |
d3fcc808 | 12714 | for_each_intel_crtc(dev, crtc) { |
8af6cf88 DV |
12715 | bool enabled = false; |
12716 | bool active = false; | |
12717 | ||
045ac3b5 JB |
12718 | memset(&pipe_config, 0, sizeof(pipe_config)); |
12719 | ||
8af6cf88 DV |
12720 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
12721 | crtc->base.base.id); | |
12722 | ||
83d65738 | 12723 | I915_STATE_WARN(crtc->active && !crtc->base.state->enable, |
8af6cf88 DV |
12724 | "active crtc, but not enabled in sw tracking\n"); |
12725 | ||
b2784e15 | 12726 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 DV |
12727 | if (encoder->base.crtc != &crtc->base) |
12728 | continue; | |
12729 | enabled = true; | |
12730 | if (encoder->connectors_active) | |
12731 | active = true; | |
12732 | } | |
6c49f241 | 12733 | |
e2c719b7 | 12734 | I915_STATE_WARN(active != crtc->active, |
8af6cf88 DV |
12735 | "crtc's computed active state doesn't match tracked active state " |
12736 | "(expected %i, found %i)\n", active, crtc->active); | |
83d65738 | 12737 | I915_STATE_WARN(enabled != crtc->base.state->enable, |
8af6cf88 | 12738 | "crtc's computed enabled state doesn't match tracked enabled state " |
83d65738 MR |
12739 | "(expected %i, found %i)\n", enabled, |
12740 | crtc->base.state->enable); | |
8af6cf88 | 12741 | |
0e8ffe1b DV |
12742 | active = dev_priv->display.get_pipe_config(crtc, |
12743 | &pipe_config); | |
d62cf62a | 12744 | |
b6b5d049 VS |
12745 | /* hw state is inconsistent with the pipe quirk */ |
12746 | if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
12747 | (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
d62cf62a DV |
12748 | active = crtc->active; |
12749 | ||
b2784e15 | 12750 | for_each_intel_encoder(dev, encoder) { |
3eaba51c | 12751 | enum pipe pipe; |
6c49f241 DV |
12752 | if (encoder->base.crtc != &crtc->base) |
12753 | continue; | |
1d37b689 | 12754 | if (encoder->get_hw_state(encoder, &pipe)) |
6c49f241 DV |
12755 | encoder->get_config(encoder, &pipe_config); |
12756 | } | |
12757 | ||
e2c719b7 | 12758 | I915_STATE_WARN(crtc->active != active, |
0e8ffe1b DV |
12759 | "crtc active state doesn't match with hw state " |
12760 | "(expected %i, found %i)\n", crtc->active, active); | |
12761 | ||
c0b03411 | 12762 | if (active && |
6e3c9717 | 12763 | !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) { |
e2c719b7 | 12764 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); |
c0b03411 DV |
12765 | intel_dump_pipe_config(crtc, &pipe_config, |
12766 | "[hw state]"); | |
6e3c9717 | 12767 | intel_dump_pipe_config(crtc, crtc->config, |
c0b03411 DV |
12768 | "[sw state]"); |
12769 | } | |
8af6cf88 DV |
12770 | } |
12771 | } | |
12772 | ||
91d1b4bd DV |
12773 | static void |
12774 | check_shared_dpll_state(struct drm_device *dev) | |
12775 | { | |
fbee40df | 12776 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
12777 | struct intel_crtc *crtc; |
12778 | struct intel_dpll_hw_state dpll_hw_state; | |
12779 | int i; | |
5358901f DV |
12780 | |
12781 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
12782 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
12783 | int enabled_crtcs = 0, active_crtcs = 0; | |
12784 | bool active; | |
12785 | ||
12786 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
12787 | ||
12788 | DRM_DEBUG_KMS("%s\n", pll->name); | |
12789 | ||
12790 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
12791 | ||
e2c719b7 | 12792 | I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask), |
5358901f | 12793 | "more active pll users than references: %i vs %i\n", |
3e369b76 | 12794 | pll->active, hweight32(pll->config.crtc_mask)); |
e2c719b7 | 12795 | I915_STATE_WARN(pll->active && !pll->on, |
5358901f | 12796 | "pll in active use but not on in sw tracking\n"); |
e2c719b7 | 12797 | I915_STATE_WARN(pll->on && !pll->active, |
35c95375 | 12798 | "pll in on but not on in use in sw tracking\n"); |
e2c719b7 | 12799 | I915_STATE_WARN(pll->on != active, |
5358901f DV |
12800 | "pll on state mismatch (expected %i, found %i)\n", |
12801 | pll->on, active); | |
12802 | ||
d3fcc808 | 12803 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 12804 | if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll) |
5358901f DV |
12805 | enabled_crtcs++; |
12806 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
12807 | active_crtcs++; | |
12808 | } | |
e2c719b7 | 12809 | I915_STATE_WARN(pll->active != active_crtcs, |
5358901f DV |
12810 | "pll active crtcs mismatch (expected %i, found %i)\n", |
12811 | pll->active, active_crtcs); | |
e2c719b7 | 12812 | I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs, |
5358901f | 12813 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
3e369b76 | 12814 | hweight32(pll->config.crtc_mask), enabled_crtcs); |
66e985c0 | 12815 | |
e2c719b7 | 12816 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state, |
66e985c0 DV |
12817 | sizeof(dpll_hw_state)), |
12818 | "pll hw state mismatch\n"); | |
5358901f | 12819 | } |
8af6cf88 DV |
12820 | } |
12821 | ||
91d1b4bd DV |
12822 | void |
12823 | intel_modeset_check_state(struct drm_device *dev) | |
12824 | { | |
08db6652 | 12825 | check_wm_state(dev); |
91d1b4bd DV |
12826 | check_connector_state(dev); |
12827 | check_encoder_state(dev); | |
12828 | check_crtc_state(dev); | |
12829 | check_shared_dpll_state(dev); | |
12830 | } | |
12831 | ||
5cec258b | 12832 | void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config, |
18442d08 VS |
12833 | int dotclock) |
12834 | { | |
12835 | /* | |
12836 | * FDI already provided one idea for the dotclock. | |
12837 | * Yell if the encoder disagrees. | |
12838 | */ | |
2d112de7 | 12839 | WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock), |
18442d08 | 12840 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
2d112de7 | 12841 | pipe_config->base.adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
12842 | } |
12843 | ||
80715b2f VS |
12844 | static void update_scanline_offset(struct intel_crtc *crtc) |
12845 | { | |
12846 | struct drm_device *dev = crtc->base.dev; | |
12847 | ||
12848 | /* | |
12849 | * The scanline counter increments at the leading edge of hsync. | |
12850 | * | |
12851 | * On most platforms it starts counting from vtotal-1 on the | |
12852 | * first active line. That means the scanline counter value is | |
12853 | * always one less than what we would expect. Ie. just after | |
12854 | * start of vblank, which also occurs at start of hsync (on the | |
12855 | * last active line), the scanline counter will read vblank_start-1. | |
12856 | * | |
12857 | * On gen2 the scanline counter starts counting from 1 instead | |
12858 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
12859 | * to keep the value positive), instead of adding one. | |
12860 | * | |
12861 | * On HSW+ the behaviour of the scanline counter depends on the output | |
12862 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
12863 | * there's an extra 1 line difference. So we need to add two instead of | |
12864 | * one to the value. | |
12865 | */ | |
12866 | if (IS_GEN2(dev)) { | |
6e3c9717 | 12867 | const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
12868 | int vtotal; |
12869 | ||
12870 | vtotal = mode->crtc_vtotal; | |
12871 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
12872 | vtotal /= 2; | |
12873 | ||
12874 | crtc->scanline_offset = vtotal - 1; | |
12875 | } else if (HAS_DDI(dev) && | |
409ee761 | 12876 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
12877 | crtc->scanline_offset = 2; |
12878 | } else | |
12879 | crtc->scanline_offset = 1; | |
12880 | } | |
12881 | ||
5cec258b | 12882 | static struct intel_crtc_state * |
7f27126e | 12883 | intel_modeset_compute_config(struct drm_crtc *crtc, |
0a9ab303 | 12884 | struct drm_atomic_state *state) |
7f27126e | 12885 | { |
548ee15b | 12886 | struct intel_crtc_state *pipe_config; |
0b901879 ACO |
12887 | int ret = 0; |
12888 | ||
12889 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
12890 | if (ret) | |
12891 | return ERR_PTR(ret); | |
7f27126e | 12892 | |
8c7b5ccb ACO |
12893 | ret = drm_atomic_helper_check_modeset(state->dev, state); |
12894 | if (ret) | |
12895 | return ERR_PTR(ret); | |
7f27126e | 12896 | |
7f27126e JB |
12897 | /* |
12898 | * Note this needs changes when we start tracking multiple modes | |
12899 | * and crtcs. At that point we'll need to compute the whole config | |
12900 | * (i.e. one pipe_config for each crtc) rather than just the one | |
12901 | * for this crtc. | |
12902 | */ | |
548ee15b ACO |
12903 | pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc)); |
12904 | if (IS_ERR(pipe_config)) | |
12905 | return pipe_config; | |
83a57153 | 12906 | |
4fed33f6 | 12907 | if (!pipe_config->base.enable) |
548ee15b | 12908 | return pipe_config; |
7f27126e | 12909 | |
8c7b5ccb | 12910 | ret = intel_modeset_pipe_config(crtc, state, pipe_config); |
548ee15b ACO |
12911 | if (ret) |
12912 | return ERR_PTR(ret); | |
12913 | ||
8d8c9b51 ACO |
12914 | /* Check things that can only be changed through modeset */ |
12915 | if (pipe_config->has_audio != | |
12916 | to_intel_crtc(crtc)->config->has_audio) | |
12917 | pipe_config->base.mode_changed = true; | |
12918 | ||
12919 | /* | |
12920 | * Note we have an issue here with infoframes: current code | |
12921 | * only updates them on the full mode set path per hw | |
12922 | * requirements. So here we should be checking for any | |
12923 | * required changes and forcing a mode set. | |
12924 | */ | |
12925 | ||
548ee15b | 12926 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,"[modeset]"); |
db7542dd | 12927 | |
8c7b5ccb ACO |
12928 | ret = drm_atomic_helper_check_planes(state->dev, state); |
12929 | if (ret) | |
12930 | return ERR_PTR(ret); | |
12931 | ||
548ee15b | 12932 | return pipe_config; |
7f27126e JB |
12933 | } |
12934 | ||
0a9ab303 | 12935 | static int __intel_set_mode_setup_plls(struct drm_atomic_state *state) |
ed6739ef | 12936 | { |
225da59b | 12937 | struct drm_device *dev = state->dev; |
ed6739ef | 12938 | struct drm_i915_private *dev_priv = to_i915(dev); |
0a9ab303 | 12939 | unsigned clear_pipes = 0; |
ed6739ef | 12940 | struct intel_crtc *intel_crtc; |
0a9ab303 ACO |
12941 | struct intel_crtc_state *intel_crtc_state; |
12942 | struct drm_crtc *crtc; | |
12943 | struct drm_crtc_state *crtc_state; | |
ed6739ef | 12944 | int ret = 0; |
0a9ab303 | 12945 | int i; |
ed6739ef ACO |
12946 | |
12947 | if (!dev_priv->display.crtc_compute_clock) | |
12948 | return 0; | |
12949 | ||
0a9ab303 ACO |
12950 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
12951 | intel_crtc = to_intel_crtc(crtc); | |
4978cc93 | 12952 | intel_crtc_state = to_intel_crtc_state(crtc_state); |
0a9ab303 | 12953 | |
4978cc93 | 12954 | if (needs_modeset(crtc_state)) { |
0a9ab303 | 12955 | clear_pipes |= 1 << intel_crtc->pipe; |
4978cc93 | 12956 | intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE; |
4978cc93 | 12957 | } |
0a9ab303 ACO |
12958 | } |
12959 | ||
ed6739ef ACO |
12960 | ret = intel_shared_dpll_start_config(dev_priv, clear_pipes); |
12961 | if (ret) | |
12962 | goto done; | |
12963 | ||
0a9ab303 ACO |
12964 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
12965 | if (!needs_modeset(crtc_state) || !crtc_state->enable) | |
225da59b ACO |
12966 | continue; |
12967 | ||
0a9ab303 ACO |
12968 | intel_crtc = to_intel_crtc(crtc); |
12969 | intel_crtc_state = to_intel_crtc_state(crtc_state); | |
12970 | ||
ed6739ef | 12971 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, |
0a9ab303 | 12972 | intel_crtc_state); |
ed6739ef ACO |
12973 | if (ret) { |
12974 | intel_shared_dpll_abort_config(dev_priv); | |
12975 | goto done; | |
12976 | } | |
12977 | } | |
12978 | ||
12979 | done: | |
12980 | return ret; | |
12981 | } | |
12982 | ||
054518dd ACO |
12983 | /* Code that should eventually be part of atomic_check() */ |
12984 | static int __intel_set_mode_checks(struct drm_atomic_state *state) | |
12985 | { | |
12986 | struct drm_device *dev = state->dev; | |
12987 | int ret; | |
12988 | ||
12989 | /* | |
12990 | * See if the config requires any additional preparation, e.g. | |
12991 | * to adjust global state with pipes off. We need to do this | |
12992 | * here so we can get the modeset_pipe updated config for the new | |
12993 | * mode set on this crtc. For other crtcs we need to use the | |
12994 | * adjusted_mode bits in the crtc directly. | |
12995 | */ | |
b432e5cf VS |
12996 | if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev) || IS_BROADWELL(dev)) { |
12997 | if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) | |
12998 | ret = valleyview_modeset_global_pipes(state); | |
12999 | else | |
13000 | ret = broadwell_modeset_global_pipes(state); | |
13001 | ||
054518dd ACO |
13002 | if (ret) |
13003 | return ret; | |
13004 | } | |
13005 | ||
13006 | ret = __intel_set_mode_setup_plls(state); | |
13007 | if (ret) | |
13008 | return ret; | |
13009 | ||
13010 | return 0; | |
13011 | } | |
13012 | ||
0a9ab303 | 13013 | static int __intel_set_mode(struct drm_crtc *modeset_crtc, |
0a9ab303 | 13014 | struct intel_crtc_state *pipe_config) |
a6778b3c | 13015 | { |
0a9ab303 | 13016 | struct drm_device *dev = modeset_crtc->dev; |
fbee40df | 13017 | struct drm_i915_private *dev_priv = dev->dev_private; |
304603f4 | 13018 | struct drm_atomic_state *state = pipe_config->base.state; |
0a9ab303 ACO |
13019 | struct drm_crtc *crtc; |
13020 | struct drm_crtc_state *crtc_state; | |
c0c36b94 | 13021 | int ret = 0; |
0a9ab303 | 13022 | int i; |
a6778b3c | 13023 | |
054518dd ACO |
13024 | ret = __intel_set_mode_checks(state); |
13025 | if (ret < 0) | |
13026 | return ret; | |
13027 | ||
d4afb8cc ACO |
13028 | ret = drm_atomic_helper_prepare_planes(dev, state); |
13029 | if (ret) | |
13030 | return ret; | |
13031 | ||
0a9ab303 ACO |
13032 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
13033 | if (!needs_modeset(crtc_state)) | |
13034 | continue; | |
460da916 | 13035 | |
0a9ab303 ACO |
13036 | if (!crtc_state->enable) { |
13037 | intel_crtc_disable(crtc); | |
13038 | } else if (crtc->state->enable) { | |
13039 | intel_crtc_disable_planes(crtc); | |
13040 | dev_priv->display.crtc_disable(crtc); | |
ce22dba9 | 13041 | } |
ea9d758d | 13042 | } |
a6778b3c | 13043 | |
6c4c86f5 DV |
13044 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
13045 | * to set it here already despite that we pass it down the callchain. | |
7f27126e JB |
13046 | * |
13047 | * Note we'll need to fix this up when we start tracking multiple | |
13048 | * pipes; here we assume a single modeset_pipe and only track the | |
13049 | * single crtc and mode. | |
f6e5b160 | 13050 | */ |
0a9ab303 | 13051 | if (pipe_config->base.enable && needs_modeset(&pipe_config->base)) { |
8c7b5ccb | 13052 | modeset_crtc->mode = pipe_config->base.mode; |
c326c0a9 VS |
13053 | |
13054 | /* | |
13055 | * Calculate and store various constants which | |
13056 | * are later needed by vblank and swap-completion | |
13057 | * timestamping. They are derived from true hwmode. | |
13058 | */ | |
0a9ab303 | 13059 | drm_calc_timestamping_constants(modeset_crtc, |
2d112de7 | 13060 | &pipe_config->base.adjusted_mode); |
b8cecdf5 | 13061 | } |
7758a113 | 13062 | |
ea9d758d DV |
13063 | /* Only after disabling all output pipelines that will be changed can we |
13064 | * update the the output configuration. */ | |
0a9ab303 | 13065 | intel_modeset_update_state(state); |
f6e5b160 | 13066 | |
a821fc46 ACO |
13067 | /* The state has been swaped above, so state actually contains the |
13068 | * old state now. */ | |
13069 | ||
304603f4 | 13070 | modeset_update_crtc_power_domains(state); |
47fab737 | 13071 | |
d4afb8cc | 13072 | drm_atomic_helper_commit_planes(dev, state); |
a6778b3c DV |
13073 | |
13074 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
0a9ab303 | 13075 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
a821fc46 | 13076 | if (!needs_modeset(crtc->state) || !crtc->state->enable) |
0a9ab303 ACO |
13077 | continue; |
13078 | ||
13079 | update_scanline_offset(to_intel_crtc(crtc)); | |
80715b2f | 13080 | |
0a9ab303 ACO |
13081 | dev_priv->display.crtc_enable(crtc); |
13082 | intel_crtc_enable_planes(crtc); | |
80715b2f | 13083 | } |
a6778b3c | 13084 | |
a6778b3c | 13085 | /* FIXME: add subpixel order */ |
83a57153 | 13086 | |
d4afb8cc ACO |
13087 | drm_atomic_helper_cleanup_planes(dev, state); |
13088 | ||
2bfb4627 ACO |
13089 | drm_atomic_state_free(state); |
13090 | ||
9eb45f22 | 13091 | return 0; |
f6e5b160 CW |
13092 | } |
13093 | ||
0a9ab303 | 13094 | static int intel_set_mode_with_config(struct drm_crtc *crtc, |
0a9ab303 | 13095 | struct intel_crtc_state *pipe_config) |
f30da187 DV |
13096 | { |
13097 | int ret; | |
13098 | ||
8c7b5ccb | 13099 | ret = __intel_set_mode(crtc, pipe_config); |
f30da187 DV |
13100 | |
13101 | if (ret == 0) | |
13102 | intel_modeset_check_state(crtc->dev); | |
13103 | ||
13104 | return ret; | |
13105 | } | |
13106 | ||
7f27126e | 13107 | static int intel_set_mode(struct drm_crtc *crtc, |
83a57153 | 13108 | struct drm_atomic_state *state) |
7f27126e | 13109 | { |
5cec258b | 13110 | struct intel_crtc_state *pipe_config; |
83a57153 | 13111 | int ret = 0; |
7f27126e | 13112 | |
8c7b5ccb | 13113 | pipe_config = intel_modeset_compute_config(crtc, state); |
83a57153 ACO |
13114 | if (IS_ERR(pipe_config)) { |
13115 | ret = PTR_ERR(pipe_config); | |
13116 | goto out; | |
13117 | } | |
13118 | ||
8c7b5ccb | 13119 | ret = intel_set_mode_with_config(crtc, pipe_config); |
83a57153 ACO |
13120 | if (ret) |
13121 | goto out; | |
7f27126e | 13122 | |
83a57153 ACO |
13123 | out: |
13124 | return ret; | |
7f27126e JB |
13125 | } |
13126 | ||
c0c36b94 CW |
13127 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
13128 | { | |
83a57153 ACO |
13129 | struct drm_device *dev = crtc->dev; |
13130 | struct drm_atomic_state *state; | |
4be07317 | 13131 | struct intel_crtc *intel_crtc; |
83a57153 ACO |
13132 | struct intel_encoder *encoder; |
13133 | struct intel_connector *connector; | |
13134 | struct drm_connector_state *connector_state; | |
4be07317 | 13135 | struct intel_crtc_state *crtc_state; |
2bfb4627 | 13136 | int ret; |
83a57153 ACO |
13137 | |
13138 | state = drm_atomic_state_alloc(dev); | |
13139 | if (!state) { | |
13140 | DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory", | |
13141 | crtc->base.id); | |
13142 | return; | |
13143 | } | |
13144 | ||
13145 | state->acquire_ctx = dev->mode_config.acquire_ctx; | |
13146 | ||
13147 | /* The force restore path in the HW readout code relies on the staged | |
13148 | * config still keeping the user requested config while the actual | |
13149 | * state has been overwritten by the configuration read from HW. We | |
13150 | * need to copy the staged config to the atomic state, otherwise the | |
13151 | * mode set will just reapply the state the HW is already in. */ | |
13152 | for_each_intel_encoder(dev, encoder) { | |
13153 | if (&encoder->new_crtc->base != crtc) | |
13154 | continue; | |
13155 | ||
13156 | for_each_intel_connector(dev, connector) { | |
13157 | if (connector->new_encoder != encoder) | |
13158 | continue; | |
13159 | ||
13160 | connector_state = drm_atomic_get_connector_state(state, &connector->base); | |
13161 | if (IS_ERR(connector_state)) { | |
13162 | DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n", | |
13163 | connector->base.base.id, | |
13164 | connector->base.name, | |
13165 | PTR_ERR(connector_state)); | |
13166 | continue; | |
13167 | } | |
13168 | ||
13169 | connector_state->crtc = crtc; | |
13170 | connector_state->best_encoder = &encoder->base; | |
13171 | } | |
13172 | } | |
13173 | ||
4be07317 ACO |
13174 | for_each_intel_crtc(dev, intel_crtc) { |
13175 | if (intel_crtc->new_enabled == intel_crtc->base.enabled) | |
13176 | continue; | |
13177 | ||
13178 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); | |
13179 | if (IS_ERR(crtc_state)) { | |
13180 | DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n", | |
13181 | intel_crtc->base.base.id, | |
13182 | PTR_ERR(crtc_state)); | |
13183 | continue; | |
13184 | } | |
13185 | ||
49d6fa21 ML |
13186 | crtc_state->base.active = crtc_state->base.enable = |
13187 | intel_crtc->new_enabled; | |
8c7b5ccb ACO |
13188 | |
13189 | if (&intel_crtc->base == crtc) | |
13190 | drm_mode_copy(&crtc_state->base.mode, &crtc->mode); | |
4be07317 ACO |
13191 | } |
13192 | ||
d3a40d1b ACO |
13193 | intel_modeset_setup_plane_state(state, crtc, &crtc->mode, |
13194 | crtc->primary->fb, crtc->x, crtc->y); | |
13195 | ||
2bfb4627 ACO |
13196 | ret = intel_set_mode(crtc, state); |
13197 | if (ret) | |
13198 | drm_atomic_state_free(state); | |
c0c36b94 CW |
13199 | } |
13200 | ||
25c5b266 DV |
13201 | #undef for_each_intel_crtc_masked |
13202 | ||
b7885264 ACO |
13203 | static bool intel_connector_in_mode_set(struct intel_connector *connector, |
13204 | struct drm_mode_set *set) | |
13205 | { | |
13206 | int ro; | |
13207 | ||
13208 | for (ro = 0; ro < set->num_connectors; ro++) | |
13209 | if (set->connectors[ro] == &connector->base) | |
13210 | return true; | |
13211 | ||
13212 | return false; | |
13213 | } | |
13214 | ||
2e431051 | 13215 | static int |
9a935856 DV |
13216 | intel_modeset_stage_output_state(struct drm_device *dev, |
13217 | struct drm_mode_set *set, | |
944b0c76 | 13218 | struct drm_atomic_state *state) |
50f56119 | 13219 | { |
9a935856 | 13220 | struct intel_connector *connector; |
d5432a9d | 13221 | struct drm_connector *drm_connector; |
944b0c76 | 13222 | struct drm_connector_state *connector_state; |
d5432a9d ACO |
13223 | struct drm_crtc *crtc; |
13224 | struct drm_crtc_state *crtc_state; | |
13225 | int i, ret; | |
50f56119 | 13226 | |
9abdda74 | 13227 | /* The upper layers ensure that we either disable a crtc or have a list |
9a935856 DV |
13228 | * of connectors. For paranoia, double-check this. */ |
13229 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
13230 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
13231 | ||
3a3371ff | 13232 | for_each_intel_connector(dev, connector) { |
b7885264 ACO |
13233 | bool in_mode_set = intel_connector_in_mode_set(connector, set); |
13234 | ||
d5432a9d ACO |
13235 | if (!in_mode_set && connector->base.state->crtc != set->crtc) |
13236 | continue; | |
13237 | ||
13238 | connector_state = | |
13239 | drm_atomic_get_connector_state(state, &connector->base); | |
13240 | if (IS_ERR(connector_state)) | |
13241 | return PTR_ERR(connector_state); | |
13242 | ||
b7885264 ACO |
13243 | if (in_mode_set) { |
13244 | int pipe = to_intel_crtc(set->crtc)->pipe; | |
d5432a9d ACO |
13245 | connector_state->best_encoder = |
13246 | &intel_find_encoder(connector, pipe)->base; | |
50f56119 DV |
13247 | } |
13248 | ||
d5432a9d | 13249 | if (connector->base.state->crtc != set->crtc) |
b7885264 ACO |
13250 | continue; |
13251 | ||
9a935856 DV |
13252 | /* If we disable the crtc, disable all its connectors. Also, if |
13253 | * the connector is on the changing crtc but not on the new | |
13254 | * connector list, disable it. */ | |
b7885264 | 13255 | if (!set->fb || !in_mode_set) { |
d5432a9d | 13256 | connector_state->best_encoder = NULL; |
9a935856 DV |
13257 | |
13258 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
13259 | connector->base.base.id, | |
c23cc417 | 13260 | connector->base.name); |
9a935856 | 13261 | } |
50f56119 | 13262 | } |
9a935856 | 13263 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 13264 | |
d5432a9d ACO |
13265 | for_each_connector_in_state(state, drm_connector, connector_state, i) { |
13266 | connector = to_intel_connector(drm_connector); | |
13267 | ||
13268 | if (!connector_state->best_encoder) { | |
13269 | ret = drm_atomic_set_crtc_for_connector(connector_state, | |
13270 | NULL); | |
13271 | if (ret) | |
13272 | return ret; | |
7668851f | 13273 | |
50f56119 | 13274 | continue; |
d5432a9d | 13275 | } |
50f56119 | 13276 | |
d5432a9d ACO |
13277 | if (intel_connector_in_mode_set(connector, set)) { |
13278 | struct drm_crtc *crtc = connector->base.state->crtc; | |
13279 | ||
13280 | /* If this connector was in a previous crtc, add it | |
13281 | * to the state. We might need to disable it. */ | |
13282 | if (crtc) { | |
13283 | crtc_state = | |
13284 | drm_atomic_get_crtc_state(state, crtc); | |
13285 | if (IS_ERR(crtc_state)) | |
13286 | return PTR_ERR(crtc_state); | |
13287 | } | |
13288 | ||
13289 | ret = drm_atomic_set_crtc_for_connector(connector_state, | |
13290 | set->crtc); | |
13291 | if (ret) | |
13292 | return ret; | |
13293 | } | |
50f56119 DV |
13294 | |
13295 | /* Make sure the new CRTC will work with the encoder */ | |
d5432a9d ACO |
13296 | if (!drm_encoder_crtc_ok(connector_state->best_encoder, |
13297 | connector_state->crtc)) { | |
5e2b584e | 13298 | return -EINVAL; |
50f56119 | 13299 | } |
944b0c76 | 13300 | |
9a935856 DV |
13301 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", |
13302 | connector->base.base.id, | |
c23cc417 | 13303 | connector->base.name, |
d5432a9d | 13304 | connector_state->crtc->base.id); |
944b0c76 | 13305 | |
d5432a9d ACO |
13306 | if (connector_state->best_encoder != &connector->encoder->base) |
13307 | connector->encoder = | |
13308 | to_intel_encoder(connector_state->best_encoder); | |
0e32b39c | 13309 | } |
7668851f | 13310 | |
d5432a9d | 13311 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
49d6fa21 ML |
13312 | bool has_connectors; |
13313 | ||
d5432a9d ACO |
13314 | ret = drm_atomic_add_affected_connectors(state, crtc); |
13315 | if (ret) | |
13316 | return ret; | |
4be07317 | 13317 | |
49d6fa21 ML |
13318 | has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc); |
13319 | if (has_connectors != crtc_state->enable) | |
13320 | crtc_state->enable = | |
13321 | crtc_state->active = has_connectors; | |
7668851f VS |
13322 | } |
13323 | ||
8c7b5ccb ACO |
13324 | ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode, |
13325 | set->fb, set->x, set->y); | |
13326 | if (ret) | |
13327 | return ret; | |
13328 | ||
13329 | crtc_state = drm_atomic_get_crtc_state(state, set->crtc); | |
13330 | if (IS_ERR(crtc_state)) | |
13331 | return PTR_ERR(crtc_state); | |
13332 | ||
13333 | if (set->mode) | |
13334 | drm_mode_copy(&crtc_state->mode, set->mode); | |
13335 | ||
13336 | if (set->num_connectors) | |
13337 | crtc_state->active = true; | |
13338 | ||
2e431051 DV |
13339 | return 0; |
13340 | } | |
13341 | ||
bb546623 ACO |
13342 | static bool primary_plane_visible(struct drm_crtc *crtc) |
13343 | { | |
13344 | struct intel_plane_state *plane_state = | |
13345 | to_intel_plane_state(crtc->primary->state); | |
13346 | ||
13347 | return plane_state->visible; | |
13348 | } | |
13349 | ||
2e431051 DV |
13350 | static int intel_crtc_set_config(struct drm_mode_set *set) |
13351 | { | |
13352 | struct drm_device *dev; | |
83a57153 | 13353 | struct drm_atomic_state *state = NULL; |
5cec258b | 13354 | struct intel_crtc_state *pipe_config; |
bb546623 | 13355 | bool primary_plane_was_visible; |
2e431051 | 13356 | int ret; |
2e431051 | 13357 | |
8d3e375e DV |
13358 | BUG_ON(!set); |
13359 | BUG_ON(!set->crtc); | |
13360 | BUG_ON(!set->crtc->helper_private); | |
2e431051 | 13361 | |
7e53f3a4 DV |
13362 | /* Enforce sane interface api - has been abused by the fb helper. */ |
13363 | BUG_ON(!set->mode && set->fb); | |
13364 | BUG_ON(set->fb && set->num_connectors == 0); | |
431e50f7 | 13365 | |
2e431051 DV |
13366 | if (set->fb) { |
13367 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
13368 | set->crtc->base.id, set->fb->base.id, | |
13369 | (int)set->num_connectors, set->x, set->y); | |
13370 | } else { | |
13371 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
13372 | } |
13373 | ||
13374 | dev = set->crtc->dev; | |
13375 | ||
83a57153 | 13376 | state = drm_atomic_state_alloc(dev); |
7cbf41d6 ACO |
13377 | if (!state) |
13378 | return -ENOMEM; | |
83a57153 ACO |
13379 | |
13380 | state->acquire_ctx = dev->mode_config.acquire_ctx; | |
13381 | ||
462a425a | 13382 | ret = intel_modeset_stage_output_state(dev, set, state); |
2e431051 | 13383 | if (ret) |
7cbf41d6 | 13384 | goto out; |
2e431051 | 13385 | |
8c7b5ccb | 13386 | pipe_config = intel_modeset_compute_config(set->crtc, state); |
20664591 | 13387 | if (IS_ERR(pipe_config)) { |
6ac0483b | 13388 | ret = PTR_ERR(pipe_config); |
7cbf41d6 | 13389 | goto out; |
20664591 | 13390 | } |
50f52756 | 13391 | |
1f9954d0 JB |
13392 | intel_update_pipe_size(to_intel_crtc(set->crtc)); |
13393 | ||
bb546623 ACO |
13394 | primary_plane_was_visible = primary_plane_visible(set->crtc); |
13395 | ||
8c7b5ccb | 13396 | ret = intel_set_mode_with_config(set->crtc, pipe_config); |
bb546623 ACO |
13397 | |
13398 | if (ret == 0 && | |
13399 | pipe_config->base.enable && | |
13400 | pipe_config->base.planes_changed && | |
13401 | !needs_modeset(&pipe_config->base)) { | |
3b150f08 | 13402 | struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc); |
3b150f08 MR |
13403 | |
13404 | /* | |
13405 | * We need to make sure the primary plane is re-enabled if it | |
13406 | * has previously been turned off. | |
13407 | */ | |
bb546623 ACO |
13408 | if (ret == 0 && !primary_plane_was_visible && |
13409 | primary_plane_visible(set->crtc)) { | |
3b150f08 | 13410 | WARN_ON(!intel_crtc->active); |
87d4300a | 13411 | intel_post_enable_primary(set->crtc); |
3b150f08 MR |
13412 | } |
13413 | ||
7ca51a3a JB |
13414 | /* |
13415 | * In the fastboot case this may be our only check of the | |
13416 | * state after boot. It would be better to only do it on | |
13417 | * the first update, but we don't have a nice way of doing that | |
13418 | * (and really, set_config isn't used much for high freq page | |
13419 | * flipping, so increasing its cost here shouldn't be a big | |
13420 | * deal). | |
13421 | */ | |
d330a953 | 13422 | if (i915.fastboot && ret == 0) |
7ca51a3a | 13423 | intel_modeset_check_state(set->crtc->dev); |
50f56119 DV |
13424 | } |
13425 | ||
2d05eae1 | 13426 | if (ret) { |
bf67dfeb DV |
13427 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
13428 | set->crtc->base.id, ret); | |
2d05eae1 | 13429 | } |
50f56119 | 13430 | |
7cbf41d6 | 13431 | out: |
2bfb4627 ACO |
13432 | if (ret) |
13433 | drm_atomic_state_free(state); | |
50f56119 DV |
13434 | return ret; |
13435 | } | |
f6e5b160 CW |
13436 | |
13437 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 | 13438 | .gamma_set = intel_crtc_gamma_set, |
50f56119 | 13439 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
13440 | .destroy = intel_crtc_destroy, |
13441 | .page_flip = intel_crtc_page_flip, | |
1356837e MR |
13442 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
13443 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
13444 | }; |
13445 | ||
5358901f DV |
13446 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
13447 | struct intel_shared_dpll *pll, | |
13448 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 13449 | { |
5358901f | 13450 | uint32_t val; |
ee7b9f93 | 13451 | |
f458ebbc | 13452 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
bd2bb1b9 PZ |
13453 | return false; |
13454 | ||
5358901f | 13455 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
13456 | hw_state->dpll = val; |
13457 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
13458 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
13459 | |
13460 | return val & DPLL_VCO_ENABLE; | |
13461 | } | |
13462 | ||
15bdd4cf DV |
13463 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
13464 | struct intel_shared_dpll *pll) | |
13465 | { | |
3e369b76 ACO |
13466 | I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0); |
13467 | I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1); | |
15bdd4cf DV |
13468 | } |
13469 | ||
e7b903d2 DV |
13470 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
13471 | struct intel_shared_dpll *pll) | |
13472 | { | |
e7b903d2 | 13473 | /* PCH refclock must be enabled first */ |
89eff4be | 13474 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 13475 | |
3e369b76 | 13476 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf DV |
13477 | |
13478 | /* Wait for the clocks to stabilize. */ | |
13479 | POSTING_READ(PCH_DPLL(pll->id)); | |
13480 | udelay(150); | |
13481 | ||
13482 | /* The pixel multiplier can only be updated once the | |
13483 | * DPLL is enabled and the clocks are stable. | |
13484 | * | |
13485 | * So write it again. | |
13486 | */ | |
3e369b76 | 13487 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf | 13488 | POSTING_READ(PCH_DPLL(pll->id)); |
e7b903d2 DV |
13489 | udelay(200); |
13490 | } | |
13491 | ||
13492 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
13493 | struct intel_shared_dpll *pll) | |
13494 | { | |
13495 | struct drm_device *dev = dev_priv->dev; | |
13496 | struct intel_crtc *crtc; | |
e7b903d2 DV |
13497 | |
13498 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 13499 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
13500 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
13501 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
13502 | } |
13503 | ||
15bdd4cf DV |
13504 | I915_WRITE(PCH_DPLL(pll->id), 0); |
13505 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
13506 | udelay(200); |
13507 | } | |
13508 | ||
46edb027 DV |
13509 | static char *ibx_pch_dpll_names[] = { |
13510 | "PCH DPLL A", | |
13511 | "PCH DPLL B", | |
13512 | }; | |
13513 | ||
7c74ade1 | 13514 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 13515 | { |
e7b903d2 | 13516 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
13517 | int i; |
13518 | ||
7c74ade1 | 13519 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 13520 | |
e72f9fbf | 13521 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
13522 | dev_priv->shared_dplls[i].id = i; |
13523 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 13524 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
13525 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
13526 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
13527 | dev_priv->shared_dplls[i].get_hw_state = |
13528 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
13529 | } |
13530 | } | |
13531 | ||
7c74ade1 DV |
13532 | static void intel_shared_dpll_init(struct drm_device *dev) |
13533 | { | |
e7b903d2 | 13534 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 | 13535 | |
b6283055 VS |
13536 | intel_update_cdclk(dev); |
13537 | ||
9cd86933 DV |
13538 | if (HAS_DDI(dev)) |
13539 | intel_ddi_pll_init(dev); | |
13540 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7c74ade1 DV |
13541 | ibx_pch_dpll_init(dev); |
13542 | else | |
13543 | dev_priv->num_shared_dpll = 0; | |
13544 | ||
13545 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
13546 | } |
13547 | ||
1fc0a8f7 TU |
13548 | /** |
13549 | * intel_wm_need_update - Check whether watermarks need updating | |
13550 | * @plane: drm plane | |
13551 | * @state: new plane state | |
13552 | * | |
13553 | * Check current plane state versus the new one to determine whether | |
13554 | * watermarks need to be recalculated. | |
13555 | * | |
13556 | * Returns true or false. | |
13557 | */ | |
13558 | bool intel_wm_need_update(struct drm_plane *plane, | |
13559 | struct drm_plane_state *state) | |
13560 | { | |
13561 | /* Update watermarks on tiling changes. */ | |
13562 | if (!plane->state->fb || !state->fb || | |
13563 | plane->state->fb->modifier[0] != state->fb->modifier[0] || | |
13564 | plane->state->rotation != state->rotation) | |
13565 | return true; | |
13566 | ||
13567 | return false; | |
13568 | } | |
13569 | ||
6beb8c23 MR |
13570 | /** |
13571 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
13572 | * @plane: drm plane to prepare for | |
13573 | * @fb: framebuffer to prepare for presentation | |
13574 | * | |
13575 | * Prepares a framebuffer for usage on a display plane. Generally this | |
13576 | * involves pinning the underlying object and updating the frontbuffer tracking | |
13577 | * bits. Some older platforms need special physical address handling for | |
13578 | * cursor planes. | |
13579 | * | |
13580 | * Returns 0 on success, negative error code on failure. | |
13581 | */ | |
13582 | int | |
13583 | intel_prepare_plane_fb(struct drm_plane *plane, | |
d136dfee TU |
13584 | struct drm_framebuffer *fb, |
13585 | const struct drm_plane_state *new_state) | |
465c120c MR |
13586 | { |
13587 | struct drm_device *dev = plane->dev; | |
6beb8c23 MR |
13588 | struct intel_plane *intel_plane = to_intel_plane(plane); |
13589 | enum pipe pipe = intel_plane->pipe; | |
13590 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
13591 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); | |
13592 | unsigned frontbuffer_bits = 0; | |
13593 | int ret = 0; | |
465c120c | 13594 | |
ea2c67bb | 13595 | if (!obj) |
465c120c MR |
13596 | return 0; |
13597 | ||
6beb8c23 MR |
13598 | switch (plane->type) { |
13599 | case DRM_PLANE_TYPE_PRIMARY: | |
13600 | frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe); | |
13601 | break; | |
13602 | case DRM_PLANE_TYPE_CURSOR: | |
13603 | frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe); | |
13604 | break; | |
13605 | case DRM_PLANE_TYPE_OVERLAY: | |
13606 | frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe); | |
13607 | break; | |
13608 | } | |
465c120c | 13609 | |
6beb8c23 | 13610 | mutex_lock(&dev->struct_mutex); |
465c120c | 13611 | |
6beb8c23 MR |
13612 | if (plane->type == DRM_PLANE_TYPE_CURSOR && |
13613 | INTEL_INFO(dev)->cursor_needs_physical) { | |
13614 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
13615 | ret = i915_gem_object_attach_phys(obj, align); | |
13616 | if (ret) | |
13617 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
13618 | } else { | |
82bc3b2d | 13619 | ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL); |
6beb8c23 | 13620 | } |
465c120c | 13621 | |
6beb8c23 MR |
13622 | if (ret == 0) |
13623 | i915_gem_track_fb(old_obj, obj, frontbuffer_bits); | |
fdd508a6 | 13624 | |
4c34574f | 13625 | mutex_unlock(&dev->struct_mutex); |
465c120c | 13626 | |
6beb8c23 MR |
13627 | return ret; |
13628 | } | |
13629 | ||
38f3ce3a MR |
13630 | /** |
13631 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
13632 | * @plane: drm plane to clean up for | |
13633 | * @fb: old framebuffer that was on plane | |
13634 | * | |
13635 | * Cleans up a framebuffer that has just been removed from a plane. | |
13636 | */ | |
13637 | void | |
13638 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
d136dfee TU |
13639 | struct drm_framebuffer *fb, |
13640 | const struct drm_plane_state *old_state) | |
38f3ce3a MR |
13641 | { |
13642 | struct drm_device *dev = plane->dev; | |
13643 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
13644 | ||
13645 | if (WARN_ON(!obj)) | |
13646 | return; | |
13647 | ||
13648 | if (plane->type != DRM_PLANE_TYPE_CURSOR || | |
13649 | !INTEL_INFO(dev)->cursor_needs_physical) { | |
13650 | mutex_lock(&dev->struct_mutex); | |
82bc3b2d | 13651 | intel_unpin_fb_obj(fb, old_state); |
38f3ce3a MR |
13652 | mutex_unlock(&dev->struct_mutex); |
13653 | } | |
465c120c MR |
13654 | } |
13655 | ||
6156a456 CK |
13656 | int |
13657 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
13658 | { | |
13659 | int max_scale; | |
13660 | struct drm_device *dev; | |
13661 | struct drm_i915_private *dev_priv; | |
13662 | int crtc_clock, cdclk; | |
13663 | ||
13664 | if (!intel_crtc || !crtc_state) | |
13665 | return DRM_PLANE_HELPER_NO_SCALING; | |
13666 | ||
13667 | dev = intel_crtc->base.dev; | |
13668 | dev_priv = dev->dev_private; | |
13669 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; | |
13670 | cdclk = dev_priv->display.get_display_clock_speed(dev); | |
13671 | ||
13672 | if (!crtc_clock || !cdclk) | |
13673 | return DRM_PLANE_HELPER_NO_SCALING; | |
13674 | ||
13675 | /* | |
13676 | * skl max scale is lower of: | |
13677 | * close to 3 but not 3, -1 is for that purpose | |
13678 | * or | |
13679 | * cdclk/crtc_clock | |
13680 | */ | |
13681 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); | |
13682 | ||
13683 | return max_scale; | |
13684 | } | |
13685 | ||
465c120c | 13686 | static int |
3c692a41 GP |
13687 | intel_check_primary_plane(struct drm_plane *plane, |
13688 | struct intel_plane_state *state) | |
13689 | { | |
32b7eeec MR |
13690 | struct drm_device *dev = plane->dev; |
13691 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2b875c22 | 13692 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb | 13693 | struct intel_crtc *intel_crtc; |
6156a456 | 13694 | struct intel_crtc_state *crtc_state; |
2b875c22 | 13695 | struct drm_framebuffer *fb = state->base.fb; |
3c692a41 GP |
13696 | struct drm_rect *dest = &state->dst; |
13697 | struct drm_rect *src = &state->src; | |
13698 | const struct drm_rect *clip = &state->clip; | |
d8106366 | 13699 | bool can_position = false; |
6156a456 CK |
13700 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
13701 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; | |
465c120c MR |
13702 | int ret; |
13703 | ||
ea2c67bb MR |
13704 | crtc = crtc ? crtc : plane->crtc; |
13705 | intel_crtc = to_intel_crtc(crtc); | |
6156a456 CK |
13706 | crtc_state = state->base.state ? |
13707 | intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL; | |
ea2c67bb | 13708 | |
6156a456 | 13709 | if (INTEL_INFO(dev)->gen >= 9) { |
225c228a CK |
13710 | /* use scaler when colorkey is not required */ |
13711 | if (to_intel_plane(plane)->ckey.flags == I915_SET_COLORKEY_NONE) { | |
13712 | min_scale = 1; | |
13713 | max_scale = skl_max_scale(intel_crtc, crtc_state); | |
13714 | } | |
d8106366 | 13715 | can_position = true; |
6156a456 | 13716 | } |
d8106366 | 13717 | |
c59cb179 MR |
13718 | ret = drm_plane_helper_check_update(plane, crtc, fb, |
13719 | src, dest, clip, | |
6156a456 CK |
13720 | min_scale, |
13721 | max_scale, | |
d8106366 SJ |
13722 | can_position, true, |
13723 | &state->visible); | |
c59cb179 MR |
13724 | if (ret) |
13725 | return ret; | |
465c120c | 13726 | |
32b7eeec | 13727 | if (intel_crtc->active) { |
b70709a6 ML |
13728 | struct intel_plane_state *old_state = |
13729 | to_intel_plane_state(plane->state); | |
13730 | ||
32b7eeec MR |
13731 | intel_crtc->atomic.wait_for_flips = true; |
13732 | ||
13733 | /* | |
13734 | * FBC does not work on some platforms for rotated | |
13735 | * planes, so disable it when rotation is not 0 and | |
13736 | * update it when rotation is set back to 0. | |
13737 | * | |
13738 | * FIXME: This is redundant with the fbc update done in | |
13739 | * the primary plane enable function except that that | |
13740 | * one is done too late. We eventually need to unify | |
13741 | * this. | |
13742 | */ | |
b70709a6 | 13743 | if (state->visible && |
32b7eeec | 13744 | INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && |
e35fef21 | 13745 | dev_priv->fbc.crtc == intel_crtc && |
8e7d688b | 13746 | state->base.rotation != BIT(DRM_ROTATE_0)) { |
32b7eeec MR |
13747 | intel_crtc->atomic.disable_fbc = true; |
13748 | } | |
13749 | ||
b70709a6 | 13750 | if (state->visible && !old_state->visible) { |
32b7eeec MR |
13751 | /* |
13752 | * BDW signals flip done immediately if the plane | |
13753 | * is disabled, even if the plane enable is already | |
13754 | * armed to occur at the next vblank :( | |
13755 | */ | |
b70709a6 | 13756 | if (IS_BROADWELL(dev)) |
32b7eeec MR |
13757 | intel_crtc->atomic.wait_vblank = true; |
13758 | } | |
13759 | ||
13760 | intel_crtc->atomic.fb_bits |= | |
13761 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); | |
13762 | ||
13763 | intel_crtc->atomic.update_fbc = true; | |
0fda6568 | 13764 | |
1fc0a8f7 | 13765 | if (intel_wm_need_update(plane, &state->base)) |
0fda6568 | 13766 | intel_crtc->atomic.update_wm = true; |
ccc759dc GP |
13767 | } |
13768 | ||
6156a456 CK |
13769 | if (INTEL_INFO(dev)->gen >= 9) { |
13770 | ret = skl_update_scaler_users(intel_crtc, crtc_state, | |
13771 | to_intel_plane(plane), state, 0); | |
13772 | if (ret) | |
13773 | return ret; | |
13774 | } | |
13775 | ||
14af293f GP |
13776 | return 0; |
13777 | } | |
13778 | ||
13779 | static void | |
13780 | intel_commit_primary_plane(struct drm_plane *plane, | |
13781 | struct intel_plane_state *state) | |
13782 | { | |
2b875c22 MR |
13783 | struct drm_crtc *crtc = state->base.crtc; |
13784 | struct drm_framebuffer *fb = state->base.fb; | |
13785 | struct drm_device *dev = plane->dev; | |
14af293f | 13786 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea2c67bb | 13787 | struct intel_crtc *intel_crtc; |
14af293f GP |
13788 | struct drm_rect *src = &state->src; |
13789 | ||
ea2c67bb MR |
13790 | crtc = crtc ? crtc : plane->crtc; |
13791 | intel_crtc = to_intel_crtc(crtc); | |
cf4c7c12 MR |
13792 | |
13793 | plane->fb = fb; | |
9dc806fc MR |
13794 | crtc->x = src->x1 >> 16; |
13795 | crtc->y = src->y1 >> 16; | |
ccc759dc | 13796 | |
ccc759dc | 13797 | if (intel_crtc->active) { |
27321ae8 | 13798 | if (state->visible) |
ccc759dc GP |
13799 | /* FIXME: kill this fastboot hack */ |
13800 | intel_update_pipe_size(intel_crtc); | |
465c120c | 13801 | |
27321ae8 ML |
13802 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
13803 | crtc->x, crtc->y); | |
ccc759dc | 13804 | } |
465c120c MR |
13805 | } |
13806 | ||
a8ad0d8e ML |
13807 | static void |
13808 | intel_disable_primary_plane(struct drm_plane *plane, | |
13809 | struct drm_crtc *crtc, | |
13810 | bool force) | |
13811 | { | |
13812 | struct drm_device *dev = plane->dev; | |
13813 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13814 | ||
a8ad0d8e ML |
13815 | dev_priv->display.update_primary_plane(crtc, NULL, 0, 0); |
13816 | } | |
13817 | ||
32b7eeec | 13818 | static void intel_begin_crtc_commit(struct drm_crtc *crtc) |
3c692a41 | 13819 | { |
32b7eeec | 13820 | struct drm_device *dev = crtc->dev; |
140fd38d | 13821 | struct drm_i915_private *dev_priv = dev->dev_private; |
3c692a41 | 13822 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ea2c67bb MR |
13823 | struct intel_plane *intel_plane; |
13824 | struct drm_plane *p; | |
13825 | unsigned fb_bits = 0; | |
13826 | ||
13827 | /* Track fb's for any planes being disabled */ | |
13828 | list_for_each_entry(p, &dev->mode_config.plane_list, head) { | |
13829 | intel_plane = to_intel_plane(p); | |
13830 | ||
13831 | if (intel_crtc->atomic.disabled_planes & | |
13832 | (1 << drm_plane_index(p))) { | |
13833 | switch (p->type) { | |
13834 | case DRM_PLANE_TYPE_PRIMARY: | |
13835 | fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe); | |
13836 | break; | |
13837 | case DRM_PLANE_TYPE_CURSOR: | |
13838 | fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe); | |
13839 | break; | |
13840 | case DRM_PLANE_TYPE_OVERLAY: | |
13841 | fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe); | |
13842 | break; | |
13843 | } | |
3c692a41 | 13844 | |
ea2c67bb MR |
13845 | mutex_lock(&dev->struct_mutex); |
13846 | i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits); | |
13847 | mutex_unlock(&dev->struct_mutex); | |
13848 | } | |
13849 | } | |
3c692a41 | 13850 | |
32b7eeec MR |
13851 | if (intel_crtc->atomic.wait_for_flips) |
13852 | intel_crtc_wait_for_pending_flips(crtc); | |
3c692a41 | 13853 | |
32b7eeec MR |
13854 | if (intel_crtc->atomic.disable_fbc) |
13855 | intel_fbc_disable(dev); | |
3c692a41 | 13856 | |
32b7eeec MR |
13857 | if (intel_crtc->atomic.pre_disable_primary) |
13858 | intel_pre_disable_primary(crtc); | |
3c692a41 | 13859 | |
32b7eeec MR |
13860 | if (intel_crtc->atomic.update_wm) |
13861 | intel_update_watermarks(crtc); | |
3c692a41 | 13862 | |
32b7eeec | 13863 | intel_runtime_pm_get(dev_priv); |
3c692a41 | 13864 | |
c34c9ee4 MR |
13865 | /* Perform vblank evasion around commit operation */ |
13866 | if (intel_crtc->active) | |
13867 | intel_crtc->atomic.evade = | |
13868 | intel_pipe_update_start(intel_crtc, | |
13869 | &intel_crtc->atomic.start_vbl_count); | |
32b7eeec MR |
13870 | } |
13871 | ||
13872 | static void intel_finish_crtc_commit(struct drm_crtc *crtc) | |
13873 | { | |
13874 | struct drm_device *dev = crtc->dev; | |
13875 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13876 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
13877 | struct drm_plane *p; | |
13878 | ||
c34c9ee4 MR |
13879 | if (intel_crtc->atomic.evade) |
13880 | intel_pipe_update_end(intel_crtc, | |
13881 | intel_crtc->atomic.start_vbl_count); | |
3c692a41 | 13882 | |
140fd38d | 13883 | intel_runtime_pm_put(dev_priv); |
3c692a41 | 13884 | |
32b7eeec MR |
13885 | if (intel_crtc->atomic.wait_vblank) |
13886 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
13887 | ||
13888 | intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits); | |
13889 | ||
13890 | if (intel_crtc->atomic.update_fbc) { | |
ccc759dc | 13891 | mutex_lock(&dev->struct_mutex); |
7ff0ebcc | 13892 | intel_fbc_update(dev); |
ccc759dc | 13893 | mutex_unlock(&dev->struct_mutex); |
38f3ce3a | 13894 | } |
3c692a41 | 13895 | |
32b7eeec MR |
13896 | if (intel_crtc->atomic.post_enable_primary) |
13897 | intel_post_enable_primary(crtc); | |
3c692a41 | 13898 | |
32b7eeec MR |
13899 | drm_for_each_legacy_plane(p, &dev->mode_config.plane_list) |
13900 | if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p)) | |
13901 | intel_update_sprite_watermarks(p, crtc, 0, 0, 0, | |
13902 | false, false); | |
13903 | ||
13904 | memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic)); | |
3c692a41 GP |
13905 | } |
13906 | ||
cf4c7c12 | 13907 | /** |
4a3b8769 MR |
13908 | * intel_plane_destroy - destroy a plane |
13909 | * @plane: plane to destroy | |
cf4c7c12 | 13910 | * |
4a3b8769 MR |
13911 | * Common destruction function for all types of planes (primary, cursor, |
13912 | * sprite). | |
cf4c7c12 | 13913 | */ |
4a3b8769 | 13914 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c MR |
13915 | { |
13916 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
13917 | drm_plane_cleanup(plane); | |
13918 | kfree(intel_plane); | |
13919 | } | |
13920 | ||
65a3fea0 | 13921 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
13922 | .update_plane = drm_atomic_helper_update_plane, |
13923 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 13924 | .destroy = intel_plane_destroy, |
c196e1d6 | 13925 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
13926 | .atomic_get_property = intel_plane_atomic_get_property, |
13927 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
13928 | .atomic_duplicate_state = intel_plane_duplicate_state, |
13929 | .atomic_destroy_state = intel_plane_destroy_state, | |
13930 | ||
465c120c MR |
13931 | }; |
13932 | ||
13933 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
13934 | int pipe) | |
13935 | { | |
13936 | struct intel_plane *primary; | |
8e7d688b | 13937 | struct intel_plane_state *state; |
465c120c MR |
13938 | const uint32_t *intel_primary_formats; |
13939 | int num_formats; | |
13940 | ||
13941 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
13942 | if (primary == NULL) | |
13943 | return NULL; | |
13944 | ||
8e7d688b MR |
13945 | state = intel_create_plane_state(&primary->base); |
13946 | if (!state) { | |
ea2c67bb MR |
13947 | kfree(primary); |
13948 | return NULL; | |
13949 | } | |
8e7d688b | 13950 | primary->base.state = &state->base; |
ea2c67bb | 13951 | |
465c120c MR |
13952 | primary->can_scale = false; |
13953 | primary->max_downscale = 1; | |
6156a456 CK |
13954 | if (INTEL_INFO(dev)->gen >= 9) { |
13955 | primary->can_scale = true; | |
af99ceda | 13956 | state->scaler_id = -1; |
6156a456 | 13957 | } |
465c120c MR |
13958 | primary->pipe = pipe; |
13959 | primary->plane = pipe; | |
c59cb179 MR |
13960 | primary->check_plane = intel_check_primary_plane; |
13961 | primary->commit_plane = intel_commit_primary_plane; | |
a8ad0d8e | 13962 | primary->disable_plane = intel_disable_primary_plane; |
08e221fb | 13963 | primary->ckey.flags = I915_SET_COLORKEY_NONE; |
465c120c MR |
13964 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
13965 | primary->plane = !pipe; | |
13966 | ||
6c0fd451 DL |
13967 | if (INTEL_INFO(dev)->gen >= 9) { |
13968 | intel_primary_formats = skl_primary_formats; | |
13969 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
13970 | } else if (INTEL_INFO(dev)->gen >= 4) { | |
568db4f2 DL |
13971 | intel_primary_formats = i965_primary_formats; |
13972 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
6c0fd451 DL |
13973 | } else { |
13974 | intel_primary_formats = i8xx_primary_formats; | |
13975 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
465c120c MR |
13976 | } |
13977 | ||
13978 | drm_universal_plane_init(dev, &primary->base, 0, | |
65a3fea0 | 13979 | &intel_plane_funcs, |
465c120c MR |
13980 | intel_primary_formats, num_formats, |
13981 | DRM_PLANE_TYPE_PRIMARY); | |
48404c1e | 13982 | |
3b7a5119 SJ |
13983 | if (INTEL_INFO(dev)->gen >= 4) |
13984 | intel_create_rotation_property(dev, primary); | |
48404c1e | 13985 | |
ea2c67bb MR |
13986 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
13987 | ||
465c120c MR |
13988 | return &primary->base; |
13989 | } | |
13990 | ||
3b7a5119 SJ |
13991 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
13992 | { | |
13993 | if (!dev->mode_config.rotation_property) { | |
13994 | unsigned long flags = BIT(DRM_ROTATE_0) | | |
13995 | BIT(DRM_ROTATE_180); | |
13996 | ||
13997 | if (INTEL_INFO(dev)->gen >= 9) | |
13998 | flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); | |
13999 | ||
14000 | dev->mode_config.rotation_property = | |
14001 | drm_mode_create_rotation_property(dev, flags); | |
14002 | } | |
14003 | if (dev->mode_config.rotation_property) | |
14004 | drm_object_attach_property(&plane->base.base, | |
14005 | dev->mode_config.rotation_property, | |
14006 | plane->base.state->rotation); | |
14007 | } | |
14008 | ||
3d7d6510 | 14009 | static int |
852e787c GP |
14010 | intel_check_cursor_plane(struct drm_plane *plane, |
14011 | struct intel_plane_state *state) | |
3d7d6510 | 14012 | { |
2b875c22 | 14013 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb | 14014 | struct drm_device *dev = plane->dev; |
2b875c22 | 14015 | struct drm_framebuffer *fb = state->base.fb; |
852e787c GP |
14016 | struct drm_rect *dest = &state->dst; |
14017 | struct drm_rect *src = &state->src; | |
14018 | const struct drm_rect *clip = &state->clip; | |
757f9a3e | 14019 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
ea2c67bb | 14020 | struct intel_crtc *intel_crtc; |
757f9a3e GP |
14021 | unsigned stride; |
14022 | int ret; | |
3d7d6510 | 14023 | |
ea2c67bb MR |
14024 | crtc = crtc ? crtc : plane->crtc; |
14025 | intel_crtc = to_intel_crtc(crtc); | |
14026 | ||
757f9a3e | 14027 | ret = drm_plane_helper_check_update(plane, crtc, fb, |
852e787c | 14028 | src, dest, clip, |
3d7d6510 MR |
14029 | DRM_PLANE_HELPER_NO_SCALING, |
14030 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 14031 | true, true, &state->visible); |
757f9a3e GP |
14032 | if (ret) |
14033 | return ret; | |
14034 | ||
14035 | ||
14036 | /* if we want to turn off the cursor ignore width and height */ | |
14037 | if (!obj) | |
32b7eeec | 14038 | goto finish; |
757f9a3e | 14039 | |
757f9a3e | 14040 | /* Check for which cursor types we support */ |
ea2c67bb MR |
14041 | if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) { |
14042 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", | |
14043 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
14044 | return -EINVAL; |
14045 | } | |
14046 | ||
ea2c67bb MR |
14047 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
14048 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
14049 | DRM_DEBUG_KMS("buffer is too small\n"); |
14050 | return -ENOMEM; | |
14051 | } | |
14052 | ||
3a656b54 | 14053 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e GP |
14054 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
14055 | ret = -EINVAL; | |
14056 | } | |
757f9a3e | 14057 | |
32b7eeec MR |
14058 | finish: |
14059 | if (intel_crtc->active) { | |
3749f463 | 14060 | if (plane->state->crtc_w != state->base.crtc_w) |
32b7eeec MR |
14061 | intel_crtc->atomic.update_wm = true; |
14062 | ||
14063 | intel_crtc->atomic.fb_bits |= | |
14064 | INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe); | |
14065 | } | |
14066 | ||
757f9a3e | 14067 | return ret; |
852e787c | 14068 | } |
3d7d6510 | 14069 | |
a8ad0d8e ML |
14070 | static void |
14071 | intel_disable_cursor_plane(struct drm_plane *plane, | |
14072 | struct drm_crtc *crtc, | |
14073 | bool force) | |
14074 | { | |
14075 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
14076 | ||
14077 | if (!force) { | |
14078 | plane->fb = NULL; | |
14079 | intel_crtc->cursor_bo = NULL; | |
14080 | intel_crtc->cursor_addr = 0; | |
14081 | } | |
14082 | ||
14083 | intel_crtc_update_cursor(crtc, false); | |
14084 | } | |
14085 | ||
f4a2cf29 | 14086 | static void |
852e787c GP |
14087 | intel_commit_cursor_plane(struct drm_plane *plane, |
14088 | struct intel_plane_state *state) | |
14089 | { | |
2b875c22 | 14090 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb MR |
14091 | struct drm_device *dev = plane->dev; |
14092 | struct intel_crtc *intel_crtc; | |
2b875c22 | 14093 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 14094 | uint32_t addr; |
852e787c | 14095 | |
ea2c67bb MR |
14096 | crtc = crtc ? crtc : plane->crtc; |
14097 | intel_crtc = to_intel_crtc(crtc); | |
14098 | ||
2b875c22 | 14099 | plane->fb = state->base.fb; |
ea2c67bb MR |
14100 | crtc->cursor_x = state->base.crtc_x; |
14101 | crtc->cursor_y = state->base.crtc_y; | |
14102 | ||
a912f12f GP |
14103 | if (intel_crtc->cursor_bo == obj) |
14104 | goto update; | |
4ed91096 | 14105 | |
f4a2cf29 | 14106 | if (!obj) |
a912f12f | 14107 | addr = 0; |
f4a2cf29 | 14108 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 14109 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 14110 | else |
a912f12f | 14111 | addr = obj->phys_handle->busaddr; |
852e787c | 14112 | |
a912f12f GP |
14113 | intel_crtc->cursor_addr = addr; |
14114 | intel_crtc->cursor_bo = obj; | |
14115 | update: | |
852e787c | 14116 | |
32b7eeec | 14117 | if (intel_crtc->active) |
a912f12f | 14118 | intel_crtc_update_cursor(crtc, state->visible); |
852e787c GP |
14119 | } |
14120 | ||
3d7d6510 MR |
14121 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
14122 | int pipe) | |
14123 | { | |
14124 | struct intel_plane *cursor; | |
8e7d688b | 14125 | struct intel_plane_state *state; |
3d7d6510 MR |
14126 | |
14127 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
14128 | if (cursor == NULL) | |
14129 | return NULL; | |
14130 | ||
8e7d688b MR |
14131 | state = intel_create_plane_state(&cursor->base); |
14132 | if (!state) { | |
ea2c67bb MR |
14133 | kfree(cursor); |
14134 | return NULL; | |
14135 | } | |
8e7d688b | 14136 | cursor->base.state = &state->base; |
ea2c67bb | 14137 | |
3d7d6510 MR |
14138 | cursor->can_scale = false; |
14139 | cursor->max_downscale = 1; | |
14140 | cursor->pipe = pipe; | |
14141 | cursor->plane = pipe; | |
c59cb179 MR |
14142 | cursor->check_plane = intel_check_cursor_plane; |
14143 | cursor->commit_plane = intel_commit_cursor_plane; | |
a8ad0d8e | 14144 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 MR |
14145 | |
14146 | drm_universal_plane_init(dev, &cursor->base, 0, | |
65a3fea0 | 14147 | &intel_plane_funcs, |
3d7d6510 MR |
14148 | intel_cursor_formats, |
14149 | ARRAY_SIZE(intel_cursor_formats), | |
14150 | DRM_PLANE_TYPE_CURSOR); | |
4398ad45 VS |
14151 | |
14152 | if (INTEL_INFO(dev)->gen >= 4) { | |
14153 | if (!dev->mode_config.rotation_property) | |
14154 | dev->mode_config.rotation_property = | |
14155 | drm_mode_create_rotation_property(dev, | |
14156 | BIT(DRM_ROTATE_0) | | |
14157 | BIT(DRM_ROTATE_180)); | |
14158 | if (dev->mode_config.rotation_property) | |
14159 | drm_object_attach_property(&cursor->base.base, | |
14160 | dev->mode_config.rotation_property, | |
8e7d688b | 14161 | state->base.rotation); |
4398ad45 VS |
14162 | } |
14163 | ||
af99ceda CK |
14164 | if (INTEL_INFO(dev)->gen >=9) |
14165 | state->scaler_id = -1; | |
14166 | ||
ea2c67bb MR |
14167 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
14168 | ||
3d7d6510 MR |
14169 | return &cursor->base; |
14170 | } | |
14171 | ||
549e2bfb CK |
14172 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
14173 | struct intel_crtc_state *crtc_state) | |
14174 | { | |
14175 | int i; | |
14176 | struct intel_scaler *intel_scaler; | |
14177 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; | |
14178 | ||
14179 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
14180 | intel_scaler = &scaler_state->scalers[i]; | |
14181 | intel_scaler->in_use = 0; | |
14182 | intel_scaler->id = i; | |
14183 | ||
14184 | intel_scaler->mode = PS_SCALER_MODE_DYN; | |
14185 | } | |
14186 | ||
14187 | scaler_state->scaler_id = -1; | |
14188 | } | |
14189 | ||
b358d0a6 | 14190 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 14191 | { |
fbee40df | 14192 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 14193 | struct intel_crtc *intel_crtc; |
f5de6e07 | 14194 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
14195 | struct drm_plane *primary = NULL; |
14196 | struct drm_plane *cursor = NULL; | |
465c120c | 14197 | int i, ret; |
79e53945 | 14198 | |
955382f3 | 14199 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
14200 | if (intel_crtc == NULL) |
14201 | return; | |
14202 | ||
f5de6e07 ACO |
14203 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
14204 | if (!crtc_state) | |
14205 | goto fail; | |
550acefd ACO |
14206 | intel_crtc->config = crtc_state; |
14207 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 14208 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 14209 | |
549e2bfb CK |
14210 | /* initialize shared scalers */ |
14211 | if (INTEL_INFO(dev)->gen >= 9) { | |
14212 | if (pipe == PIPE_C) | |
14213 | intel_crtc->num_scalers = 1; | |
14214 | else | |
14215 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
14216 | ||
14217 | skl_init_scalers(dev, intel_crtc, crtc_state); | |
14218 | } | |
14219 | ||
465c120c | 14220 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
14221 | if (!primary) |
14222 | goto fail; | |
14223 | ||
14224 | cursor = intel_cursor_plane_create(dev, pipe); | |
14225 | if (!cursor) | |
14226 | goto fail; | |
14227 | ||
465c120c | 14228 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
3d7d6510 MR |
14229 | cursor, &intel_crtc_funcs); |
14230 | if (ret) | |
14231 | goto fail; | |
79e53945 JB |
14232 | |
14233 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
14234 | for (i = 0; i < 256; i++) { |
14235 | intel_crtc->lut_r[i] = i; | |
14236 | intel_crtc->lut_g[i] = i; | |
14237 | intel_crtc->lut_b[i] = i; | |
14238 | } | |
14239 | ||
1f1c2e24 VS |
14240 | /* |
14241 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 14242 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 14243 | */ |
80824003 JB |
14244 | intel_crtc->pipe = pipe; |
14245 | intel_crtc->plane = pipe; | |
3a77c4c4 | 14246 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 14247 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 14248 | intel_crtc->plane = !pipe; |
80824003 JB |
14249 | } |
14250 | ||
4b0e333e CW |
14251 | intel_crtc->cursor_base = ~0; |
14252 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 14253 | intel_crtc->cursor_size = ~0; |
8d7849db | 14254 | |
22fd0fab JB |
14255 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
14256 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
14257 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
14258 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
14259 | ||
79e53945 | 14260 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 DV |
14261 | |
14262 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); | |
3d7d6510 MR |
14263 | return; |
14264 | ||
14265 | fail: | |
14266 | if (primary) | |
14267 | drm_plane_cleanup(primary); | |
14268 | if (cursor) | |
14269 | drm_plane_cleanup(cursor); | |
f5de6e07 | 14270 | kfree(crtc_state); |
3d7d6510 | 14271 | kfree(intel_crtc); |
79e53945 JB |
14272 | } |
14273 | ||
752aa88a JB |
14274 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
14275 | { | |
14276 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 14277 | struct drm_device *dev = connector->base.dev; |
752aa88a | 14278 | |
51fd371b | 14279 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 14280 | |
d3babd3f | 14281 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
14282 | return INVALID_PIPE; |
14283 | ||
14284 | return to_intel_crtc(encoder->crtc)->pipe; | |
14285 | } | |
14286 | ||
08d7b3d1 | 14287 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 14288 | struct drm_file *file) |
08d7b3d1 | 14289 | { |
08d7b3d1 | 14290 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 14291 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 14292 | struct intel_crtc *crtc; |
08d7b3d1 | 14293 | |
7707e653 | 14294 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 14295 | |
7707e653 | 14296 | if (!drmmode_crtc) { |
08d7b3d1 | 14297 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 14298 | return -ENOENT; |
08d7b3d1 CW |
14299 | } |
14300 | ||
7707e653 | 14301 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 14302 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 14303 | |
c05422d5 | 14304 | return 0; |
08d7b3d1 CW |
14305 | } |
14306 | ||
66a9278e | 14307 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 14308 | { |
66a9278e DV |
14309 | struct drm_device *dev = encoder->base.dev; |
14310 | struct intel_encoder *source_encoder; | |
79e53945 | 14311 | int index_mask = 0; |
79e53945 JB |
14312 | int entry = 0; |
14313 | ||
b2784e15 | 14314 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 14315 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
14316 | index_mask |= (1 << entry); |
14317 | ||
79e53945 JB |
14318 | entry++; |
14319 | } | |
4ef69c7a | 14320 | |
79e53945 JB |
14321 | return index_mask; |
14322 | } | |
14323 | ||
4d302442 CW |
14324 | static bool has_edp_a(struct drm_device *dev) |
14325 | { | |
14326 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14327 | ||
14328 | if (!IS_MOBILE(dev)) | |
14329 | return false; | |
14330 | ||
14331 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
14332 | return false; | |
14333 | ||
e3589908 | 14334 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
14335 | return false; |
14336 | ||
14337 | return true; | |
14338 | } | |
14339 | ||
84b4e042 JB |
14340 | static bool intel_crt_present(struct drm_device *dev) |
14341 | { | |
14342 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14343 | ||
884497ed DL |
14344 | if (INTEL_INFO(dev)->gen >= 9) |
14345 | return false; | |
14346 | ||
cf404ce4 | 14347 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
14348 | return false; |
14349 | ||
14350 | if (IS_CHERRYVIEW(dev)) | |
14351 | return false; | |
14352 | ||
14353 | if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support) | |
14354 | return false; | |
14355 | ||
14356 | return true; | |
14357 | } | |
14358 | ||
79e53945 JB |
14359 | static void intel_setup_outputs(struct drm_device *dev) |
14360 | { | |
725e30ad | 14361 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 14362 | struct intel_encoder *encoder; |
cb0953d7 | 14363 | bool dpd_is_edp = false; |
79e53945 | 14364 | |
c9093354 | 14365 | intel_lvds_init(dev); |
79e53945 | 14366 | |
84b4e042 | 14367 | if (intel_crt_present(dev)) |
79935fca | 14368 | intel_crt_init(dev); |
cb0953d7 | 14369 | |
c776eb2e VK |
14370 | if (IS_BROXTON(dev)) { |
14371 | /* | |
14372 | * FIXME: Broxton doesn't support port detection via the | |
14373 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
14374 | * detect the ports. | |
14375 | */ | |
14376 | intel_ddi_init(dev, PORT_A); | |
14377 | intel_ddi_init(dev, PORT_B); | |
14378 | intel_ddi_init(dev, PORT_C); | |
14379 | } else if (HAS_DDI(dev)) { | |
0e72a5b5 ED |
14380 | int found; |
14381 | ||
de31facd JB |
14382 | /* |
14383 | * Haswell uses DDI functions to detect digital outputs. | |
14384 | * On SKL pre-D0 the strap isn't connected, so we assume | |
14385 | * it's there. | |
14386 | */ | |
0e72a5b5 | 14387 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; |
de31facd JB |
14388 | /* WaIgnoreDDIAStrap: skl */ |
14389 | if (found || | |
14390 | (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0)) | |
0e72a5b5 ED |
14391 | intel_ddi_init(dev, PORT_A); |
14392 | ||
14393 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
14394 | * register */ | |
14395 | found = I915_READ(SFUSE_STRAP); | |
14396 | ||
14397 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
14398 | intel_ddi_init(dev, PORT_B); | |
14399 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
14400 | intel_ddi_init(dev, PORT_C); | |
14401 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
14402 | intel_ddi_init(dev, PORT_D); | |
14403 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 14404 | int found; |
5d8a7752 | 14405 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
14406 | |
14407 | if (has_edp_a(dev)) | |
14408 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 14409 | |
dc0fa718 | 14410 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 14411 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 14412 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 14413 | if (!found) |
e2debe91 | 14414 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 14415 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 14416 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
14417 | } |
14418 | ||
dc0fa718 | 14419 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 14420 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 14421 | |
dc0fa718 | 14422 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 14423 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 14424 | |
5eb08b69 | 14425 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 14426 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 14427 | |
270b3042 | 14428 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 14429 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 14430 | } else if (IS_VALLEYVIEW(dev)) { |
e17ac6db VS |
14431 | /* |
14432 | * The DP_DETECTED bit is the latched state of the DDC | |
14433 | * SDA pin at boot. However since eDP doesn't require DDC | |
14434 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
14435 | * eDP ports may have been muxed to an alternate function. | |
14436 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
14437 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
14438 | * detect eDP ports. | |
14439 | */ | |
d2182a66 VS |
14440 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED && |
14441 | !intel_dp_is_edp(dev, PORT_B)) | |
585a94b8 AB |
14442 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, |
14443 | PORT_B); | |
e17ac6db VS |
14444 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED || |
14445 | intel_dp_is_edp(dev, PORT_B)) | |
14446 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
585a94b8 | 14447 | |
d2182a66 VS |
14448 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED && |
14449 | !intel_dp_is_edp(dev, PORT_C)) | |
6f6005a5 JB |
14450 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, |
14451 | PORT_C); | |
e17ac6db VS |
14452 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED || |
14453 | intel_dp_is_edp(dev, PORT_C)) | |
14454 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); | |
19c03924 | 14455 | |
9418c1f1 | 14456 | if (IS_CHERRYVIEW(dev)) { |
e17ac6db | 14457 | if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) |
9418c1f1 VS |
14458 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID, |
14459 | PORT_D); | |
e17ac6db VS |
14460 | /* eDP not supported on port D, so don't check VBT */ |
14461 | if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED) | |
14462 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D); | |
9418c1f1 VS |
14463 | } |
14464 | ||
3cfca973 | 14465 | intel_dsi_init(dev); |
103a196f | 14466 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 14467 | bool found = false; |
7d57382e | 14468 | |
e2debe91 | 14469 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14470 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 14471 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
b01f2c3a JB |
14472 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
14473 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
e2debe91 | 14474 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 14475 | } |
27185ae1 | 14476 | |
e7281eab | 14477 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 14478 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 14479 | } |
13520b05 KH |
14480 | |
14481 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 14482 | |
e2debe91 | 14483 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14484 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 14485 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 14486 | } |
27185ae1 | 14487 | |
e2debe91 | 14488 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 14489 | |
b01f2c3a JB |
14490 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
14491 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
e2debe91 | 14492 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 14493 | } |
e7281eab | 14494 | if (SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 14495 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 14496 | } |
27185ae1 | 14497 | |
b01f2c3a | 14498 | if (SUPPORTS_INTEGRATED_DP(dev) && |
e7281eab | 14499 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 14500 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 14501 | } else if (IS_GEN2(dev)) |
79e53945 JB |
14502 | intel_dvo_init(dev); |
14503 | ||
103a196f | 14504 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
14505 | intel_tv_init(dev); |
14506 | ||
0bc12bcb | 14507 | intel_psr_init(dev); |
7c8f8a70 | 14508 | |
b2784e15 | 14509 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
14510 | encoder->base.possible_crtcs = encoder->crtc_mask; |
14511 | encoder->base.possible_clones = | |
66a9278e | 14512 | intel_encoder_clones(encoder); |
79e53945 | 14513 | } |
47356eb6 | 14514 | |
dde86e2d | 14515 | intel_init_pch_refclk(dev); |
270b3042 DV |
14516 | |
14517 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
14518 | } |
14519 | ||
14520 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
14521 | { | |
60a5ca01 | 14522 | struct drm_device *dev = fb->dev; |
79e53945 | 14523 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 14524 | |
ef2d633e | 14525 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 14526 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 14527 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
14528 | drm_gem_object_unreference(&intel_fb->obj->base); |
14529 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
14530 | kfree(intel_fb); |
14531 | } | |
14532 | ||
14533 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 14534 | struct drm_file *file, |
79e53945 JB |
14535 | unsigned int *handle) |
14536 | { | |
14537 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 14538 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 14539 | |
05394f39 | 14540 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
14541 | } |
14542 | ||
14543 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
14544 | .destroy = intel_user_framebuffer_destroy, | |
14545 | .create_handle = intel_user_framebuffer_create_handle, | |
14546 | }; | |
14547 | ||
b321803d DL |
14548 | static |
14549 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
14550 | uint32_t pixel_format) | |
14551 | { | |
14552 | u32 gen = INTEL_INFO(dev)->gen; | |
14553 | ||
14554 | if (gen >= 9) { | |
14555 | /* "The stride in bytes must not exceed the of the size of 8K | |
14556 | * pixels and 32K bytes." | |
14557 | */ | |
14558 | return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768); | |
14559 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) { | |
14560 | return 32*1024; | |
14561 | } else if (gen >= 4) { | |
14562 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14563 | return 16*1024; | |
14564 | else | |
14565 | return 32*1024; | |
14566 | } else if (gen >= 3) { | |
14567 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14568 | return 8*1024; | |
14569 | else | |
14570 | return 16*1024; | |
14571 | } else { | |
14572 | /* XXX DSPC is limited to 4k tiled */ | |
14573 | return 8*1024; | |
14574 | } | |
14575 | } | |
14576 | ||
b5ea642a DV |
14577 | static int intel_framebuffer_init(struct drm_device *dev, |
14578 | struct intel_framebuffer *intel_fb, | |
14579 | struct drm_mode_fb_cmd2 *mode_cmd, | |
14580 | struct drm_i915_gem_object *obj) | |
79e53945 | 14581 | { |
6761dd31 | 14582 | unsigned int aligned_height; |
79e53945 | 14583 | int ret; |
b321803d | 14584 | u32 pitch_limit, stride_alignment; |
79e53945 | 14585 | |
dd4916c5 DV |
14586 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
14587 | ||
2a80eada DV |
14588 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
14589 | /* Enforce that fb modifier and tiling mode match, but only for | |
14590 | * X-tiled. This is needed for FBC. */ | |
14591 | if (!!(obj->tiling_mode == I915_TILING_X) != | |
14592 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { | |
14593 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
14594 | return -EINVAL; | |
14595 | } | |
14596 | } else { | |
14597 | if (obj->tiling_mode == I915_TILING_X) | |
14598 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
14599 | else if (obj->tiling_mode == I915_TILING_Y) { | |
14600 | DRM_DEBUG("No Y tiling for legacy addfb\n"); | |
14601 | return -EINVAL; | |
14602 | } | |
14603 | } | |
14604 | ||
9a8f0a12 TU |
14605 | /* Passed in modifier sanity checking. */ |
14606 | switch (mode_cmd->modifier[0]) { | |
14607 | case I915_FORMAT_MOD_Y_TILED: | |
14608 | case I915_FORMAT_MOD_Yf_TILED: | |
14609 | if (INTEL_INFO(dev)->gen < 9) { | |
14610 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
14611 | mode_cmd->modifier[0]); | |
14612 | return -EINVAL; | |
14613 | } | |
14614 | case DRM_FORMAT_MOD_NONE: | |
14615 | case I915_FORMAT_MOD_X_TILED: | |
14616 | break; | |
14617 | default: | |
c0f40428 JB |
14618 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
14619 | mode_cmd->modifier[0]); | |
57cd6508 | 14620 | return -EINVAL; |
c16ed4be | 14621 | } |
57cd6508 | 14622 | |
b321803d DL |
14623 | stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0], |
14624 | mode_cmd->pixel_format); | |
14625 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
14626 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
14627 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 14628 | return -EINVAL; |
c16ed4be | 14629 | } |
57cd6508 | 14630 | |
b321803d DL |
14631 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
14632 | mode_cmd->pixel_format); | |
a35cdaa0 | 14633 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
14634 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
14635 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 14636 | "tiled" : "linear", |
a35cdaa0 | 14637 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 14638 | return -EINVAL; |
c16ed4be | 14639 | } |
5d7bd705 | 14640 | |
2a80eada | 14641 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
c16ed4be CW |
14642 | mode_cmd->pitches[0] != obj->stride) { |
14643 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
14644 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 14645 | return -EINVAL; |
c16ed4be | 14646 | } |
5d7bd705 | 14647 | |
57779d06 | 14648 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 14649 | switch (mode_cmd->pixel_format) { |
57779d06 | 14650 | case DRM_FORMAT_C8: |
04b3924d VS |
14651 | case DRM_FORMAT_RGB565: |
14652 | case DRM_FORMAT_XRGB8888: | |
14653 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
14654 | break; |
14655 | case DRM_FORMAT_XRGB1555: | |
c16ed4be | 14656 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
14657 | DRM_DEBUG("unsupported pixel format: %s\n", |
14658 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14659 | return -EINVAL; |
c16ed4be | 14660 | } |
57779d06 | 14661 | break; |
57779d06 | 14662 | case DRM_FORMAT_ABGR8888: |
6c0fd451 DL |
14663 | if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) { |
14664 | DRM_DEBUG("unsupported pixel format: %s\n", | |
14665 | drm_get_format_name(mode_cmd->pixel_format)); | |
14666 | return -EINVAL; | |
14667 | } | |
14668 | break; | |
14669 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 14670 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 14671 | case DRM_FORMAT_XBGR2101010: |
c16ed4be | 14672 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
14673 | DRM_DEBUG("unsupported pixel format: %s\n", |
14674 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14675 | return -EINVAL; |
c16ed4be | 14676 | } |
b5626747 | 14677 | break; |
7531208b DL |
14678 | case DRM_FORMAT_ABGR2101010: |
14679 | if (!IS_VALLEYVIEW(dev)) { | |
14680 | DRM_DEBUG("unsupported pixel format: %s\n", | |
14681 | drm_get_format_name(mode_cmd->pixel_format)); | |
14682 | return -EINVAL; | |
14683 | } | |
14684 | break; | |
04b3924d VS |
14685 | case DRM_FORMAT_YUYV: |
14686 | case DRM_FORMAT_UYVY: | |
14687 | case DRM_FORMAT_YVYU: | |
14688 | case DRM_FORMAT_VYUY: | |
c16ed4be | 14689 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
14690 | DRM_DEBUG("unsupported pixel format: %s\n", |
14691 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14692 | return -EINVAL; |
c16ed4be | 14693 | } |
57cd6508 CW |
14694 | break; |
14695 | default: | |
4ee62c76 VS |
14696 | DRM_DEBUG("unsupported pixel format: %s\n", |
14697 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
14698 | return -EINVAL; |
14699 | } | |
14700 | ||
90f9a336 VS |
14701 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
14702 | if (mode_cmd->offsets[0] != 0) | |
14703 | return -EINVAL; | |
14704 | ||
ec2c981e | 14705 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
091df6cb DV |
14706 | mode_cmd->pixel_format, |
14707 | mode_cmd->modifier[0]); | |
53155c0a DV |
14708 | /* FIXME drm helper for size checks (especially planar formats)? */ |
14709 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
14710 | return -EINVAL; | |
14711 | ||
c7d73f6a DV |
14712 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
14713 | intel_fb->obj = obj; | |
80075d49 | 14714 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 14715 | |
79e53945 JB |
14716 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
14717 | if (ret) { | |
14718 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
14719 | return ret; | |
14720 | } | |
14721 | ||
79e53945 JB |
14722 | return 0; |
14723 | } | |
14724 | ||
79e53945 JB |
14725 | static struct drm_framebuffer * |
14726 | intel_user_framebuffer_create(struct drm_device *dev, | |
14727 | struct drm_file *filp, | |
308e5bcb | 14728 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 14729 | { |
05394f39 | 14730 | struct drm_i915_gem_object *obj; |
79e53945 | 14731 | |
308e5bcb JB |
14732 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
14733 | mode_cmd->handles[0])); | |
c8725226 | 14734 | if (&obj->base == NULL) |
cce13ff7 | 14735 | return ERR_PTR(-ENOENT); |
79e53945 | 14736 | |
d2dff872 | 14737 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
14738 | } |
14739 | ||
4520f53a | 14740 | #ifndef CONFIG_DRM_I915_FBDEV |
0632fef6 | 14741 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
14742 | { |
14743 | } | |
14744 | #endif | |
14745 | ||
79e53945 | 14746 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 14747 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 14748 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
14749 | .atomic_check = intel_atomic_check, |
14750 | .atomic_commit = intel_atomic_commit, | |
79e53945 JB |
14751 | }; |
14752 | ||
e70236a8 JB |
14753 | /* Set up chip specific display functions */ |
14754 | static void intel_init_display(struct drm_device *dev) | |
14755 | { | |
14756 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14757 | ||
ee9300bb DV |
14758 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
14759 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
14760 | else if (IS_CHERRYVIEW(dev)) |
14761 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
14762 | else if (IS_VALLEYVIEW(dev)) |
14763 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
14764 | else if (IS_PINEVIEW(dev)) | |
14765 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
14766 | else | |
14767 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
14768 | ||
bc8d7dff DL |
14769 | if (INTEL_INFO(dev)->gen >= 9) { |
14770 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; | |
5724dbd1 DL |
14771 | dev_priv->display.get_initial_plane_config = |
14772 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
14773 | dev_priv->display.crtc_compute_clock = |
14774 | haswell_crtc_compute_clock; | |
14775 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
14776 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
14777 | dev_priv->display.off = ironlake_crtc_off; | |
14778 | dev_priv->display.update_primary_plane = | |
14779 | skylake_update_primary_plane; | |
14780 | } else if (HAS_DDI(dev)) { | |
0e8ffe1b | 14781 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14782 | dev_priv->display.get_initial_plane_config = |
14783 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
14784 | dev_priv->display.crtc_compute_clock = |
14785 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
14786 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
14787 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
df8ad70c | 14788 | dev_priv->display.off = ironlake_crtc_off; |
bc8d7dff DL |
14789 | dev_priv->display.update_primary_plane = |
14790 | ironlake_update_primary_plane; | |
09b4ddf9 | 14791 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 14792 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
14793 | dev_priv->display.get_initial_plane_config = |
14794 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
14795 | dev_priv->display.crtc_compute_clock = |
14796 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
14797 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
14798 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
ee7b9f93 | 14799 | dev_priv->display.off = ironlake_crtc_off; |
262ca2b0 MR |
14800 | dev_priv->display.update_primary_plane = |
14801 | ironlake_update_primary_plane; | |
89b667f8 JB |
14802 | } else if (IS_VALLEYVIEW(dev)) { |
14803 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
5724dbd1 DL |
14804 | dev_priv->display.get_initial_plane_config = |
14805 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14806 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
89b667f8 JB |
14807 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
14808 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
14809 | dev_priv->display.off = i9xx_crtc_off; | |
262ca2b0 MR |
14810 | dev_priv->display.update_primary_plane = |
14811 | i9xx_update_primary_plane; | |
f564048e | 14812 | } else { |
0e8ffe1b | 14813 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14814 | dev_priv->display.get_initial_plane_config = |
14815 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14816 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
14817 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
14818 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
ee7b9f93 | 14819 | dev_priv->display.off = i9xx_crtc_off; |
262ca2b0 MR |
14820 | dev_priv->display.update_primary_plane = |
14821 | i9xx_update_primary_plane; | |
f564048e | 14822 | } |
e70236a8 | 14823 | |
e70236a8 | 14824 | /* Returns the core display clock speed */ |
1652d19e VS |
14825 | if (IS_SKYLAKE(dev)) |
14826 | dev_priv->display.get_display_clock_speed = | |
14827 | skylake_get_display_clock_speed; | |
14828 | else if (IS_BROADWELL(dev)) | |
14829 | dev_priv->display.get_display_clock_speed = | |
14830 | broadwell_get_display_clock_speed; | |
14831 | else if (IS_HASWELL(dev)) | |
14832 | dev_priv->display.get_display_clock_speed = | |
14833 | haswell_get_display_clock_speed; | |
14834 | else if (IS_VALLEYVIEW(dev)) | |
25eb05fc JB |
14835 | dev_priv->display.get_display_clock_speed = |
14836 | valleyview_get_display_clock_speed; | |
b37a6434 VS |
14837 | else if (IS_GEN5(dev)) |
14838 | dev_priv->display.get_display_clock_speed = | |
14839 | ilk_get_display_clock_speed; | |
a7c66cd8 | 14840 | else if (IS_I945G(dev) || IS_BROADWATER(dev) || |
34edce2f | 14841 | IS_GEN6(dev) || IS_IVYBRIDGE(dev)) |
e70236a8 JB |
14842 | dev_priv->display.get_display_clock_speed = |
14843 | i945_get_display_clock_speed; | |
34edce2f VS |
14844 | else if (IS_GM45(dev)) |
14845 | dev_priv->display.get_display_clock_speed = | |
14846 | gm45_get_display_clock_speed; | |
14847 | else if (IS_CRESTLINE(dev)) | |
14848 | dev_priv->display.get_display_clock_speed = | |
14849 | i965gm_get_display_clock_speed; | |
14850 | else if (IS_PINEVIEW(dev)) | |
14851 | dev_priv->display.get_display_clock_speed = | |
14852 | pnv_get_display_clock_speed; | |
14853 | else if (IS_G33(dev) || IS_G4X(dev)) | |
14854 | dev_priv->display.get_display_clock_speed = | |
14855 | g33_get_display_clock_speed; | |
e70236a8 JB |
14856 | else if (IS_I915G(dev)) |
14857 | dev_priv->display.get_display_clock_speed = | |
14858 | i915_get_display_clock_speed; | |
257a7ffc | 14859 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
14860 | dev_priv->display.get_display_clock_speed = |
14861 | i9xx_misc_get_display_clock_speed; | |
257a7ffc DV |
14862 | else if (IS_PINEVIEW(dev)) |
14863 | dev_priv->display.get_display_clock_speed = | |
14864 | pnv_get_display_clock_speed; | |
e70236a8 JB |
14865 | else if (IS_I915GM(dev)) |
14866 | dev_priv->display.get_display_clock_speed = | |
14867 | i915gm_get_display_clock_speed; | |
14868 | else if (IS_I865G(dev)) | |
14869 | dev_priv->display.get_display_clock_speed = | |
14870 | i865_get_display_clock_speed; | |
f0f8a9ce | 14871 | else if (IS_I85X(dev)) |
e70236a8 | 14872 | dev_priv->display.get_display_clock_speed = |
1b1d2716 | 14873 | i85x_get_display_clock_speed; |
623e01e5 VS |
14874 | else { /* 830 */ |
14875 | WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n"); | |
e70236a8 JB |
14876 | dev_priv->display.get_display_clock_speed = |
14877 | i830_get_display_clock_speed; | |
623e01e5 | 14878 | } |
e70236a8 | 14879 | |
7c10a2b5 | 14880 | if (IS_GEN5(dev)) { |
3bb11b53 | 14881 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
3bb11b53 SJ |
14882 | } else if (IS_GEN6(dev)) { |
14883 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; | |
3bb11b53 SJ |
14884 | } else if (IS_IVYBRIDGE(dev)) { |
14885 | /* FIXME: detect B0+ stepping and use auto training */ | |
14886 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
059b2fe9 | 14887 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
3bb11b53 | 14888 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
b432e5cf VS |
14889 | if (IS_BROADWELL(dev)) |
14890 | dev_priv->display.modeset_global_resources = | |
14891 | broadwell_modeset_global_resources; | |
30a970c6 JB |
14892 | } else if (IS_VALLEYVIEW(dev)) { |
14893 | dev_priv->display.modeset_global_resources = | |
14894 | valleyview_modeset_global_resources; | |
f8437dd1 VK |
14895 | } else if (IS_BROXTON(dev)) { |
14896 | dev_priv->display.modeset_global_resources = | |
14897 | broxton_modeset_global_resources; | |
e70236a8 | 14898 | } |
8c9f3aaf | 14899 | |
8c9f3aaf JB |
14900 | switch (INTEL_INFO(dev)->gen) { |
14901 | case 2: | |
14902 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
14903 | break; | |
14904 | ||
14905 | case 3: | |
14906 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
14907 | break; | |
14908 | ||
14909 | case 4: | |
14910 | case 5: | |
14911 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
14912 | break; | |
14913 | ||
14914 | case 6: | |
14915 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
14916 | break; | |
7c9017e5 | 14917 | case 7: |
4e0bbc31 | 14918 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
14919 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
14920 | break; | |
830c81db | 14921 | case 9: |
ba343e02 TU |
14922 | /* Drop through - unsupported since execlist only. */ |
14923 | default: | |
14924 | /* Default just returns -ENODEV to indicate unsupported */ | |
14925 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8c9f3aaf | 14926 | } |
7bd688cd JN |
14927 | |
14928 | intel_panel_init_backlight_funcs(dev); | |
e39b999a VS |
14929 | |
14930 | mutex_init(&dev_priv->pps_mutex); | |
e70236a8 JB |
14931 | } |
14932 | ||
b690e96c JB |
14933 | /* |
14934 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
14935 | * resume, or other times. This quirk makes sure that's the case for | |
14936 | * affected systems. | |
14937 | */ | |
0206e353 | 14938 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
14939 | { |
14940 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14941 | ||
14942 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 14943 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
14944 | } |
14945 | ||
b6b5d049 VS |
14946 | static void quirk_pipeb_force(struct drm_device *dev) |
14947 | { | |
14948 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14949 | ||
14950 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
14951 | DRM_INFO("applying pipe b force quirk\n"); | |
14952 | } | |
14953 | ||
435793df KP |
14954 | /* |
14955 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
14956 | */ | |
14957 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
14958 | { | |
14959 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14960 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 14961 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
14962 | } |
14963 | ||
4dca20ef | 14964 | /* |
5a15ab5b CE |
14965 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
14966 | * brightness value | |
4dca20ef CE |
14967 | */ |
14968 | static void quirk_invert_brightness(struct drm_device *dev) | |
14969 | { | |
14970 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14971 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 14972 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
14973 | } |
14974 | ||
9c72cc6f SD |
14975 | /* Some VBT's incorrectly indicate no backlight is present */ |
14976 | static void quirk_backlight_present(struct drm_device *dev) | |
14977 | { | |
14978 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14979 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
14980 | DRM_INFO("applying backlight present quirk\n"); | |
14981 | } | |
14982 | ||
b690e96c JB |
14983 | struct intel_quirk { |
14984 | int device; | |
14985 | int subsystem_vendor; | |
14986 | int subsystem_device; | |
14987 | void (*hook)(struct drm_device *dev); | |
14988 | }; | |
14989 | ||
5f85f176 EE |
14990 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
14991 | struct intel_dmi_quirk { | |
14992 | void (*hook)(struct drm_device *dev); | |
14993 | const struct dmi_system_id (*dmi_id_list)[]; | |
14994 | }; | |
14995 | ||
14996 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
14997 | { | |
14998 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
14999 | return 1; | |
15000 | } | |
15001 | ||
15002 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
15003 | { | |
15004 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
15005 | { | |
15006 | .callback = intel_dmi_reverse_brightness, | |
15007 | .ident = "NCR Corporation", | |
15008 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
15009 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
15010 | }, | |
15011 | }, | |
15012 | { } /* terminating entry */ | |
15013 | }, | |
15014 | .hook = quirk_invert_brightness, | |
15015 | }, | |
15016 | }; | |
15017 | ||
c43b5634 | 15018 | static struct intel_quirk intel_quirks[] = { |
b690e96c JB |
15019 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
15020 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
15021 | ||
b690e96c JB |
15022 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
15023 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
15024 | ||
5f080c0f VS |
15025 | /* 830 needs to leave pipe A & dpll A up */ |
15026 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
15027 | ||
b6b5d049 VS |
15028 | /* 830 needs to leave pipe B & dpll B up */ |
15029 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
15030 | ||
435793df KP |
15031 | /* Lenovo U160 cannot use SSC on LVDS */ |
15032 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
15033 | |
15034 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
15035 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 15036 | |
be505f64 AH |
15037 | /* Acer Aspire 5734Z must invert backlight brightness */ |
15038 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
15039 | ||
15040 | /* Acer/eMachines G725 */ | |
15041 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
15042 | ||
15043 | /* Acer/eMachines e725 */ | |
15044 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
15045 | ||
15046 | /* Acer/Packard Bell NCL20 */ | |
15047 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
15048 | ||
15049 | /* Acer Aspire 4736Z */ | |
15050 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
15051 | |
15052 | /* Acer Aspire 5336 */ | |
15053 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
15054 | |
15055 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
15056 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 15057 | |
dfb3d47b SD |
15058 | /* Acer C720 Chromebook (Core i3 4005U) */ |
15059 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
15060 | ||
b2a9601c | 15061 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
15062 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
15063 | ||
d4967d8c SD |
15064 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
15065 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
15066 | |
15067 | /* HP Chromebook 14 (Celeron 2955U) */ | |
15068 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
15069 | |
15070 | /* Dell Chromebook 11 */ | |
15071 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
15072 | }; |
15073 | ||
15074 | static void intel_init_quirks(struct drm_device *dev) | |
15075 | { | |
15076 | struct pci_dev *d = dev->pdev; | |
15077 | int i; | |
15078 | ||
15079 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
15080 | struct intel_quirk *q = &intel_quirks[i]; | |
15081 | ||
15082 | if (d->device == q->device && | |
15083 | (d->subsystem_vendor == q->subsystem_vendor || | |
15084 | q->subsystem_vendor == PCI_ANY_ID) && | |
15085 | (d->subsystem_device == q->subsystem_device || | |
15086 | q->subsystem_device == PCI_ANY_ID)) | |
15087 | q->hook(dev); | |
15088 | } | |
5f85f176 EE |
15089 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
15090 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
15091 | intel_dmi_quirks[i].hook(dev); | |
15092 | } | |
b690e96c JB |
15093 | } |
15094 | ||
9cce37f4 JB |
15095 | /* Disable the VGA plane that we never use */ |
15096 | static void i915_disable_vga(struct drm_device *dev) | |
15097 | { | |
15098 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15099 | u8 sr1; | |
766aa1c4 | 15100 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 15101 | |
2b37c616 | 15102 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 15103 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 15104 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
15105 | sr1 = inb(VGA_SR_DATA); |
15106 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
15107 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
15108 | udelay(300); | |
15109 | ||
01f5a626 | 15110 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
15111 | POSTING_READ(vga_reg); |
15112 | } | |
15113 | ||
f817586c DV |
15114 | void intel_modeset_init_hw(struct drm_device *dev) |
15115 | { | |
b6283055 | 15116 | intel_update_cdclk(dev); |
a8f78b58 | 15117 | intel_prepare_ddi(dev); |
f817586c | 15118 | intel_init_clock_gating(dev); |
8090c6b9 | 15119 | intel_enable_gt_powersave(dev); |
f817586c DV |
15120 | } |
15121 | ||
79e53945 JB |
15122 | void intel_modeset_init(struct drm_device *dev) |
15123 | { | |
652c393a | 15124 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 15125 | int sprite, ret; |
8cc87b75 | 15126 | enum pipe pipe; |
46f297fb | 15127 | struct intel_crtc *crtc; |
79e53945 JB |
15128 | |
15129 | drm_mode_config_init(dev); | |
15130 | ||
15131 | dev->mode_config.min_width = 0; | |
15132 | dev->mode_config.min_height = 0; | |
15133 | ||
019d96cb DA |
15134 | dev->mode_config.preferred_depth = 24; |
15135 | dev->mode_config.prefer_shadow = 1; | |
15136 | ||
25bab385 TU |
15137 | dev->mode_config.allow_fb_modifiers = true; |
15138 | ||
e6ecefaa | 15139 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 15140 | |
b690e96c JB |
15141 | intel_init_quirks(dev); |
15142 | ||
1fa61106 ED |
15143 | intel_init_pm(dev); |
15144 | ||
e3c74757 BW |
15145 | if (INTEL_INFO(dev)->num_pipes == 0) |
15146 | return; | |
15147 | ||
e70236a8 | 15148 | intel_init_display(dev); |
7c10a2b5 | 15149 | intel_init_audio(dev); |
e70236a8 | 15150 | |
a6c45cf0 CW |
15151 | if (IS_GEN2(dev)) { |
15152 | dev->mode_config.max_width = 2048; | |
15153 | dev->mode_config.max_height = 2048; | |
15154 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
15155 | dev->mode_config.max_width = 4096; |
15156 | dev->mode_config.max_height = 4096; | |
79e53945 | 15157 | } else { |
a6c45cf0 CW |
15158 | dev->mode_config.max_width = 8192; |
15159 | dev->mode_config.max_height = 8192; | |
79e53945 | 15160 | } |
068be561 | 15161 | |
dc41c154 VS |
15162 | if (IS_845G(dev) || IS_I865G(dev)) { |
15163 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
15164 | dev->mode_config.cursor_height = 1023; | |
15165 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
15166 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
15167 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
15168 | } else { | |
15169 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
15170 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
15171 | } | |
15172 | ||
5d4545ae | 15173 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 15174 | |
28c97730 | 15175 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
15176 | INTEL_INFO(dev)->num_pipes, |
15177 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 15178 | |
055e393f | 15179 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 15180 | intel_crtc_init(dev, pipe); |
3bdcfc0c | 15181 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 15182 | ret = intel_plane_init(dev, pipe, sprite); |
7f1f3851 | 15183 | if (ret) |
06da8da2 | 15184 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 15185 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 15186 | } |
79e53945 JB |
15187 | } |
15188 | ||
f42bb70d JB |
15189 | intel_init_dpio(dev); |
15190 | ||
e72f9fbf | 15191 | intel_shared_dpll_init(dev); |
ee7b9f93 | 15192 | |
9cce37f4 JB |
15193 | /* Just disable it once at startup */ |
15194 | i915_disable_vga(dev); | |
79e53945 | 15195 | intel_setup_outputs(dev); |
11be49eb CW |
15196 | |
15197 | /* Just in case the BIOS is doing something questionable. */ | |
7ff0ebcc | 15198 | intel_fbc_disable(dev); |
fa9fa083 | 15199 | |
6e9f798d | 15200 | drm_modeset_lock_all(dev); |
fa9fa083 | 15201 | intel_modeset_setup_hw_state(dev, false); |
6e9f798d | 15202 | drm_modeset_unlock_all(dev); |
46f297fb | 15203 | |
d3fcc808 | 15204 | for_each_intel_crtc(dev, crtc) { |
46f297fb JB |
15205 | if (!crtc->active) |
15206 | continue; | |
15207 | ||
46f297fb | 15208 | /* |
46f297fb JB |
15209 | * Note that reserving the BIOS fb up front prevents us |
15210 | * from stuffing other stolen allocations like the ring | |
15211 | * on top. This prevents some ugliness at boot time, and | |
15212 | * can even allow for smooth boot transitions if the BIOS | |
15213 | * fb is large enough for the active pipe configuration. | |
15214 | */ | |
5724dbd1 DL |
15215 | if (dev_priv->display.get_initial_plane_config) { |
15216 | dev_priv->display.get_initial_plane_config(crtc, | |
46f297fb JB |
15217 | &crtc->plane_config); |
15218 | /* | |
15219 | * If the fb is shared between multiple heads, we'll | |
15220 | * just get the first one. | |
15221 | */ | |
f6936e29 | 15222 | intel_find_initial_plane_obj(crtc, &crtc->plane_config); |
46f297fb | 15223 | } |
46f297fb | 15224 | } |
2c7111db CW |
15225 | } |
15226 | ||
7fad798e DV |
15227 | static void intel_enable_pipe_a(struct drm_device *dev) |
15228 | { | |
15229 | struct intel_connector *connector; | |
15230 | struct drm_connector *crt = NULL; | |
15231 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 15232 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
15233 | |
15234 | /* We can't just switch on the pipe A, we need to set things up with a | |
15235 | * proper mode and output configuration. As a gross hack, enable pipe A | |
15236 | * by enabling the load detect pipe once. */ | |
3a3371ff | 15237 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
15238 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
15239 | crt = &connector->base; | |
15240 | break; | |
15241 | } | |
15242 | } | |
15243 | ||
15244 | if (!crt) | |
15245 | return; | |
15246 | ||
208bf9fd | 15247 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 15248 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
15249 | } |
15250 | ||
fa555837 DV |
15251 | static bool |
15252 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
15253 | { | |
7eb552ae BW |
15254 | struct drm_device *dev = crtc->base.dev; |
15255 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
15256 | u32 reg, val; |
15257 | ||
7eb552ae | 15258 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
15259 | return true; |
15260 | ||
15261 | reg = DSPCNTR(!crtc->plane); | |
15262 | val = I915_READ(reg); | |
15263 | ||
15264 | if ((val & DISPLAY_PLANE_ENABLE) && | |
15265 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
15266 | return false; | |
15267 | ||
15268 | return true; | |
15269 | } | |
15270 | ||
24929352 DV |
15271 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
15272 | { | |
15273 | struct drm_device *dev = crtc->base.dev; | |
15274 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 15275 | u32 reg; |
24929352 | 15276 | |
24929352 | 15277 | /* Clear any frame start delays used for debugging left by the BIOS */ |
6e3c9717 | 15278 | reg = PIPECONF(crtc->config->cpu_transcoder); |
24929352 DV |
15279 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
15280 | ||
d3eaf884 | 15281 | /* restore vblank interrupts to correct state */ |
9625604c | 15282 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 VS |
15283 | if (crtc->active) { |
15284 | update_scanline_offset(crtc); | |
9625604c DV |
15285 | drm_crtc_vblank_on(&crtc->base); |
15286 | } | |
d3eaf884 | 15287 | |
24929352 | 15288 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
15289 | * disable the crtc (and hence change the state) if it is wrong. Note |
15290 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
15291 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
15292 | struct intel_connector *connector; |
15293 | bool plane; | |
15294 | ||
24929352 DV |
15295 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
15296 | crtc->base.base.id); | |
15297 | ||
15298 | /* Pipe has the wrong plane attached and the plane is active. | |
15299 | * Temporarily change the plane mapping and disable everything | |
15300 | * ... */ | |
15301 | plane = crtc->plane; | |
b70709a6 | 15302 | to_intel_plane_state(crtc->base.primary->state)->visible = true; |
24929352 | 15303 | crtc->plane = !plane; |
ce22dba9 | 15304 | intel_crtc_disable_planes(&crtc->base); |
24929352 DV |
15305 | dev_priv->display.crtc_disable(&crtc->base); |
15306 | crtc->plane = plane; | |
15307 | ||
15308 | /* ... and break all links. */ | |
3a3371ff | 15309 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15310 | if (connector->encoder->base.crtc != &crtc->base) |
15311 | continue; | |
15312 | ||
7f1950fb EE |
15313 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
15314 | connector->base.encoder = NULL; | |
24929352 | 15315 | } |
7f1950fb EE |
15316 | /* multiple connectors may have the same encoder: |
15317 | * handle them and break crtc link separately */ | |
3a3371ff | 15318 | for_each_intel_connector(dev, connector) |
7f1950fb EE |
15319 | if (connector->encoder->base.crtc == &crtc->base) { |
15320 | connector->encoder->base.crtc = NULL; | |
15321 | connector->encoder->connectors_active = false; | |
15322 | } | |
24929352 DV |
15323 | |
15324 | WARN_ON(crtc->active); | |
83d65738 | 15325 | crtc->base.state->enable = false; |
49d6fa21 | 15326 | crtc->base.state->active = false; |
24929352 DV |
15327 | crtc->base.enabled = false; |
15328 | } | |
24929352 | 15329 | |
7fad798e DV |
15330 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
15331 | crtc->pipe == PIPE_A && !crtc->active) { | |
15332 | /* BIOS forgot to enable pipe A, this mostly happens after | |
15333 | * resume. Force-enable the pipe to fix this, the update_dpms | |
15334 | * call below we restore the pipe to the right state, but leave | |
15335 | * the required bits on. */ | |
15336 | intel_enable_pipe_a(dev); | |
15337 | } | |
15338 | ||
24929352 DV |
15339 | /* Adjust the state of the output pipe according to whether we |
15340 | * have active connectors/encoders. */ | |
15341 | intel_crtc_update_dpms(&crtc->base); | |
15342 | ||
83d65738 | 15343 | if (crtc->active != crtc->base.state->enable) { |
24929352 DV |
15344 | struct intel_encoder *encoder; |
15345 | ||
15346 | /* This can happen either due to bugs in the get_hw_state | |
15347 | * functions or because the pipe is force-enabled due to the | |
15348 | * pipe A quirk. */ | |
15349 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
15350 | crtc->base.base.id, | |
83d65738 | 15351 | crtc->base.state->enable ? "enabled" : "disabled", |
24929352 DV |
15352 | crtc->active ? "enabled" : "disabled"); |
15353 | ||
83d65738 | 15354 | crtc->base.state->enable = crtc->active; |
49d6fa21 | 15355 | crtc->base.state->active = crtc->active; |
24929352 DV |
15356 | crtc->base.enabled = crtc->active; |
15357 | ||
15358 | /* Because we only establish the connector -> encoder -> | |
15359 | * crtc links if something is active, this means the | |
15360 | * crtc is now deactivated. Break the links. connector | |
15361 | * -> encoder links are only establish when things are | |
15362 | * actually up, hence no need to break them. */ | |
15363 | WARN_ON(crtc->active); | |
15364 | ||
15365 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
15366 | WARN_ON(encoder->connectors_active); | |
15367 | encoder->base.crtc = NULL; | |
15368 | } | |
15369 | } | |
c5ab3bc0 | 15370 | |
a3ed6aad | 15371 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
15372 | /* |
15373 | * We start out with underrun reporting disabled to avoid races. | |
15374 | * For correct bookkeeping mark this on active crtcs. | |
15375 | * | |
c5ab3bc0 DV |
15376 | * Also on gmch platforms we dont have any hardware bits to |
15377 | * disable the underrun reporting. Which means we need to start | |
15378 | * out with underrun reporting disabled also on inactive pipes, | |
15379 | * since otherwise we'll complain about the garbage we read when | |
15380 | * e.g. coming up after runtime pm. | |
15381 | * | |
4cc31489 DV |
15382 | * No protection against concurrent access is required - at |
15383 | * worst a fifo underrun happens which also sets this to false. | |
15384 | */ | |
15385 | crtc->cpu_fifo_underrun_disabled = true; | |
15386 | crtc->pch_fifo_underrun_disabled = true; | |
15387 | } | |
24929352 DV |
15388 | } |
15389 | ||
15390 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
15391 | { | |
15392 | struct intel_connector *connector; | |
15393 | struct drm_device *dev = encoder->base.dev; | |
15394 | ||
15395 | /* We need to check both for a crtc link (meaning that the | |
15396 | * encoder is active and trying to read from a pipe) and the | |
15397 | * pipe itself being active. */ | |
15398 | bool has_active_crtc = encoder->base.crtc && | |
15399 | to_intel_crtc(encoder->base.crtc)->active; | |
15400 | ||
15401 | if (encoder->connectors_active && !has_active_crtc) { | |
15402 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
15403 | encoder->base.base.id, | |
8e329a03 | 15404 | encoder->base.name); |
24929352 DV |
15405 | |
15406 | /* Connector is active, but has no active pipe. This is | |
15407 | * fallout from our resume register restoring. Disable | |
15408 | * the encoder manually again. */ | |
15409 | if (encoder->base.crtc) { | |
15410 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
15411 | encoder->base.base.id, | |
8e329a03 | 15412 | encoder->base.name); |
24929352 | 15413 | encoder->disable(encoder); |
a62d1497 VS |
15414 | if (encoder->post_disable) |
15415 | encoder->post_disable(encoder); | |
24929352 | 15416 | } |
7f1950fb EE |
15417 | encoder->base.crtc = NULL; |
15418 | encoder->connectors_active = false; | |
24929352 DV |
15419 | |
15420 | /* Inconsistent output/port/pipe state happens presumably due to | |
15421 | * a bug in one of the get_hw_state functions. Or someplace else | |
15422 | * in our code, like the register restore mess on resume. Clamp | |
15423 | * things to off as a safer default. */ | |
3a3371ff | 15424 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15425 | if (connector->encoder != encoder) |
15426 | continue; | |
7f1950fb EE |
15427 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
15428 | connector->base.encoder = NULL; | |
24929352 DV |
15429 | } |
15430 | } | |
15431 | /* Enabled encoders without active connectors will be fixed in | |
15432 | * the crtc fixup. */ | |
15433 | } | |
15434 | ||
04098753 | 15435 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
15436 | { |
15437 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 15438 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 15439 | |
04098753 ID |
15440 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
15441 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
15442 | i915_disable_vga(dev); | |
15443 | } | |
15444 | } | |
15445 | ||
15446 | void i915_redisable_vga(struct drm_device *dev) | |
15447 | { | |
15448 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15449 | ||
8dc8a27c PZ |
15450 | /* This function can be called both from intel_modeset_setup_hw_state or |
15451 | * at a very early point in our resume sequence, where the power well | |
15452 | * structures are not yet restored. Since this function is at a very | |
15453 | * paranoid "someone might have enabled VGA while we were not looking" | |
15454 | * level, just check if the power well is enabled instead of trying to | |
15455 | * follow the "don't touch the power well if we don't need it" policy | |
15456 | * the rest of the driver uses. */ | |
f458ebbc | 15457 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
15458 | return; |
15459 | ||
04098753 | 15460 | i915_redisable_vga_power_on(dev); |
0fde901f KM |
15461 | } |
15462 | ||
98ec7739 VS |
15463 | static bool primary_get_hw_state(struct intel_crtc *crtc) |
15464 | { | |
15465 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
15466 | ||
15467 | if (!crtc->active) | |
15468 | return false; | |
15469 | ||
15470 | return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE; | |
15471 | } | |
15472 | ||
30e984df | 15473 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
15474 | { |
15475 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15476 | enum pipe pipe; | |
24929352 DV |
15477 | struct intel_crtc *crtc; |
15478 | struct intel_encoder *encoder; | |
15479 | struct intel_connector *connector; | |
5358901f | 15480 | int i; |
24929352 | 15481 | |
d3fcc808 | 15482 | for_each_intel_crtc(dev, crtc) { |
b70709a6 ML |
15483 | struct drm_plane *primary = crtc->base.primary; |
15484 | struct intel_plane_state *plane_state; | |
15485 | ||
6e3c9717 | 15486 | memset(crtc->config, 0, sizeof(*crtc->config)); |
3b117c8f | 15487 | |
6e3c9717 | 15488 | crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE; |
9953599b | 15489 | |
0e8ffe1b | 15490 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
6e3c9717 | 15491 | crtc->config); |
24929352 | 15492 | |
83d65738 | 15493 | crtc->base.state->enable = crtc->active; |
49d6fa21 | 15494 | crtc->base.state->active = crtc->active; |
24929352 | 15495 | crtc->base.enabled = crtc->active; |
b70709a6 ML |
15496 | |
15497 | plane_state = to_intel_plane_state(primary->state); | |
15498 | plane_state->visible = primary_get_hw_state(crtc); | |
24929352 DV |
15499 | |
15500 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
15501 | crtc->base.base.id, | |
15502 | crtc->active ? "enabled" : "disabled"); | |
15503 | } | |
15504 | ||
5358901f DV |
15505 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15506 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15507 | ||
3e369b76 ACO |
15508 | pll->on = pll->get_hw_state(dev_priv, pll, |
15509 | &pll->config.hw_state); | |
5358901f | 15510 | pll->active = 0; |
3e369b76 | 15511 | pll->config.crtc_mask = 0; |
d3fcc808 | 15512 | for_each_intel_crtc(dev, crtc) { |
1e6f2ddc | 15513 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) { |
5358901f | 15514 | pll->active++; |
3e369b76 | 15515 | pll->config.crtc_mask |= 1 << crtc->pipe; |
1e6f2ddc | 15516 | } |
5358901f | 15517 | } |
5358901f | 15518 | |
1e6f2ddc | 15519 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 15520 | pll->name, pll->config.crtc_mask, pll->on); |
bd2bb1b9 | 15521 | |
3e369b76 | 15522 | if (pll->config.crtc_mask) |
bd2bb1b9 | 15523 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
5358901f DV |
15524 | } |
15525 | ||
b2784e15 | 15526 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15527 | pipe = 0; |
15528 | ||
15529 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
15530 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15531 | encoder->base.crtc = &crtc->base; | |
6e3c9717 | 15532 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
15533 | } else { |
15534 | encoder->base.crtc = NULL; | |
15535 | } | |
15536 | ||
15537 | encoder->connectors_active = false; | |
6f2bcceb | 15538 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 15539 | encoder->base.base.id, |
8e329a03 | 15540 | encoder->base.name, |
24929352 | 15541 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 15542 | pipe_name(pipe)); |
24929352 DV |
15543 | } |
15544 | ||
3a3371ff | 15545 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15546 | if (connector->get_hw_state(connector)) { |
15547 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
15548 | connector->encoder->connectors_active = true; | |
15549 | connector->base.encoder = &connector->encoder->base; | |
15550 | } else { | |
15551 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
15552 | connector->base.encoder = NULL; | |
15553 | } | |
15554 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
15555 | connector->base.base.id, | |
c23cc417 | 15556 | connector->base.name, |
24929352 DV |
15557 | connector->base.encoder ? "enabled" : "disabled"); |
15558 | } | |
30e984df DV |
15559 | } |
15560 | ||
15561 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm | |
15562 | * and i915 state tracking structures. */ | |
15563 | void intel_modeset_setup_hw_state(struct drm_device *dev, | |
15564 | bool force_restore) | |
15565 | { | |
15566 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15567 | enum pipe pipe; | |
30e984df DV |
15568 | struct intel_crtc *crtc; |
15569 | struct intel_encoder *encoder; | |
35c95375 | 15570 | int i; |
30e984df DV |
15571 | |
15572 | intel_modeset_readout_hw_state(dev); | |
24929352 | 15573 | |
babea61d JB |
15574 | /* |
15575 | * Now that we have the config, copy it to each CRTC struct | |
15576 | * Note that this could go away if we move to using crtc_config | |
15577 | * checking everywhere. | |
15578 | */ | |
d3fcc808 | 15579 | for_each_intel_crtc(dev, crtc) { |
d330a953 | 15580 | if (crtc->active && i915.fastboot) { |
6e3c9717 ACO |
15581 | intel_mode_from_pipe_config(&crtc->base.mode, |
15582 | crtc->config); | |
babea61d JB |
15583 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", |
15584 | crtc->base.base.id); | |
15585 | drm_mode_debug_printmodeline(&crtc->base.mode); | |
15586 | } | |
15587 | } | |
15588 | ||
24929352 | 15589 | /* HW state is read out, now we need to sanitize this mess. */ |
b2784e15 | 15590 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15591 | intel_sanitize_encoder(encoder); |
15592 | } | |
15593 | ||
055e393f | 15594 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
15595 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15596 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
15597 | intel_dump_pipe_config(crtc, crtc->config, |
15598 | "[setup_hw_state]"); | |
24929352 | 15599 | } |
9a935856 | 15600 | |
d29b2f9d ACO |
15601 | intel_modeset_update_connector_atomic_state(dev); |
15602 | ||
35c95375 DV |
15603 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15604 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15605 | ||
15606 | if (!pll->on || pll->active) | |
15607 | continue; | |
15608 | ||
15609 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
15610 | ||
15611 | pll->disable(dev_priv, pll); | |
15612 | pll->on = false; | |
15613 | } | |
15614 | ||
3078999f PB |
15615 | if (IS_GEN9(dev)) |
15616 | skl_wm_get_hw_state(dev); | |
15617 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 VS |
15618 | ilk_wm_get_hw_state(dev); |
15619 | ||
45e2b5f6 | 15620 | if (force_restore) { |
7d0bc1ea VS |
15621 | i915_redisable_vga(dev); |
15622 | ||
f30da187 DV |
15623 | /* |
15624 | * We need to use raw interfaces for restoring state to avoid | |
15625 | * checking (bogus) intermediate states. | |
15626 | */ | |
055e393f | 15627 | for_each_pipe(dev_priv, pipe) { |
b5644d05 JB |
15628 | struct drm_crtc *crtc = |
15629 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
f30da187 | 15630 | |
83a57153 | 15631 | intel_crtc_restore_mode(crtc); |
45e2b5f6 DV |
15632 | } |
15633 | } else { | |
15634 | intel_modeset_update_staged_output_state(dev); | |
15635 | } | |
8af6cf88 DV |
15636 | |
15637 | intel_modeset_check_state(dev); | |
2c7111db CW |
15638 | } |
15639 | ||
15640 | void intel_modeset_gem_init(struct drm_device *dev) | |
15641 | { | |
92122789 | 15642 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd | 15643 | struct drm_crtc *c; |
2ff8fde1 | 15644 | struct drm_i915_gem_object *obj; |
e0d6149b | 15645 | int ret; |
484b41dd | 15646 | |
ae48434c ID |
15647 | mutex_lock(&dev->struct_mutex); |
15648 | intel_init_gt_powersave(dev); | |
15649 | mutex_unlock(&dev->struct_mutex); | |
15650 | ||
92122789 JB |
15651 | /* |
15652 | * There may be no VBT; and if the BIOS enabled SSC we can | |
15653 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
15654 | * BIOS isn't using it, don't assume it will work even if the VBT | |
15655 | * indicates as much. | |
15656 | */ | |
15657 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
15658 | dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
15659 | DREF_SSC1_ENABLE); | |
15660 | ||
1833b134 | 15661 | intel_modeset_init_hw(dev); |
02e792fb DV |
15662 | |
15663 | intel_setup_overlay(dev); | |
484b41dd JB |
15664 | |
15665 | /* | |
15666 | * Make sure any fbs we allocated at startup are properly | |
15667 | * pinned & fenced. When we do the allocation it's too early | |
15668 | * for this. | |
15669 | */ | |
70e1e0ec | 15670 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
15671 | obj = intel_fb_obj(c->primary->fb); |
15672 | if (obj == NULL) | |
484b41dd JB |
15673 | continue; |
15674 | ||
e0d6149b TU |
15675 | mutex_lock(&dev->struct_mutex); |
15676 | ret = intel_pin_and_fence_fb_obj(c->primary, | |
15677 | c->primary->fb, | |
15678 | c->primary->state, | |
15679 | NULL); | |
15680 | mutex_unlock(&dev->struct_mutex); | |
15681 | if (ret) { | |
484b41dd JB |
15682 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
15683 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
15684 | drm_framebuffer_unreference(c->primary->fb); |
15685 | c->primary->fb = NULL; | |
afd65eb4 | 15686 | update_state_fb(c->primary); |
484b41dd JB |
15687 | } |
15688 | } | |
0962c3c9 VS |
15689 | |
15690 | intel_backlight_register(dev); | |
79e53945 JB |
15691 | } |
15692 | ||
4932e2c3 ID |
15693 | void intel_connector_unregister(struct intel_connector *intel_connector) |
15694 | { | |
15695 | struct drm_connector *connector = &intel_connector->base; | |
15696 | ||
15697 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 15698 | drm_connector_unregister(connector); |
4932e2c3 ID |
15699 | } |
15700 | ||
79e53945 JB |
15701 | void intel_modeset_cleanup(struct drm_device *dev) |
15702 | { | |
652c393a | 15703 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9255d57 | 15704 | struct drm_connector *connector; |
652c393a | 15705 | |
2eb5252e ID |
15706 | intel_disable_gt_powersave(dev); |
15707 | ||
0962c3c9 VS |
15708 | intel_backlight_unregister(dev); |
15709 | ||
fd0c0642 DV |
15710 | /* |
15711 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 15712 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
15713 | * experience fancy races otherwise. |
15714 | */ | |
2aeb7d3a | 15715 | intel_irq_uninstall(dev_priv); |
eb21b92b | 15716 | |
fd0c0642 DV |
15717 | /* |
15718 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
15719 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
15720 | */ | |
f87ea761 | 15721 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 15722 | |
652c393a JB |
15723 | mutex_lock(&dev->struct_mutex); |
15724 | ||
723bfd70 JB |
15725 | intel_unregister_dsm_handler(); |
15726 | ||
7ff0ebcc | 15727 | intel_fbc_disable(dev); |
e70236a8 | 15728 | |
69341a5e KH |
15729 | mutex_unlock(&dev->struct_mutex); |
15730 | ||
1630fe75 CW |
15731 | /* flush any delayed tasks or pending work */ |
15732 | flush_scheduled_work(); | |
15733 | ||
db31af1d JN |
15734 | /* destroy the backlight and sysfs files before encoders/connectors */ |
15735 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4932e2c3 ID |
15736 | struct intel_connector *intel_connector; |
15737 | ||
15738 | intel_connector = to_intel_connector(connector); | |
15739 | intel_connector->unregister(intel_connector); | |
db31af1d | 15740 | } |
d9255d57 | 15741 | |
79e53945 | 15742 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
15743 | |
15744 | intel_cleanup_overlay(dev); | |
ae48434c ID |
15745 | |
15746 | mutex_lock(&dev->struct_mutex); | |
15747 | intel_cleanup_gt_powersave(dev); | |
15748 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
15749 | } |
15750 | ||
f1c79df3 ZW |
15751 | /* |
15752 | * Return which encoder is currently attached for connector. | |
15753 | */ | |
df0e9248 | 15754 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 15755 | { |
df0e9248 CW |
15756 | return &intel_attached_encoder(connector)->base; |
15757 | } | |
f1c79df3 | 15758 | |
df0e9248 CW |
15759 | void intel_connector_attach_encoder(struct intel_connector *connector, |
15760 | struct intel_encoder *encoder) | |
15761 | { | |
15762 | connector->encoder = encoder; | |
15763 | drm_mode_connector_attach_encoder(&connector->base, | |
15764 | &encoder->base); | |
79e53945 | 15765 | } |
28d52043 DA |
15766 | |
15767 | /* | |
15768 | * set vga decode state - true == enable VGA decode | |
15769 | */ | |
15770 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
15771 | { | |
15772 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 15773 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
15774 | u16 gmch_ctrl; |
15775 | ||
75fa041d CW |
15776 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
15777 | DRM_ERROR("failed to read control word\n"); | |
15778 | return -EIO; | |
15779 | } | |
15780 | ||
c0cc8a55 CW |
15781 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
15782 | return 0; | |
15783 | ||
28d52043 DA |
15784 | if (state) |
15785 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
15786 | else | |
15787 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
15788 | |
15789 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
15790 | DRM_ERROR("failed to write control word\n"); | |
15791 | return -EIO; | |
15792 | } | |
15793 | ||
28d52043 DA |
15794 | return 0; |
15795 | } | |
c4a1d9e4 | 15796 | |
c4a1d9e4 | 15797 | struct intel_display_error_state { |
ff57f1b0 PZ |
15798 | |
15799 | u32 power_well_driver; | |
15800 | ||
63b66e5b CW |
15801 | int num_transcoders; |
15802 | ||
c4a1d9e4 CW |
15803 | struct intel_cursor_error_state { |
15804 | u32 control; | |
15805 | u32 position; | |
15806 | u32 base; | |
15807 | u32 size; | |
52331309 | 15808 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15809 | |
15810 | struct intel_pipe_error_state { | |
ddf9c536 | 15811 | bool power_domain_on; |
c4a1d9e4 | 15812 | u32 source; |
f301b1e1 | 15813 | u32 stat; |
52331309 | 15814 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15815 | |
15816 | struct intel_plane_error_state { | |
15817 | u32 control; | |
15818 | u32 stride; | |
15819 | u32 size; | |
15820 | u32 pos; | |
15821 | u32 addr; | |
15822 | u32 surface; | |
15823 | u32 tile_offset; | |
52331309 | 15824 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
15825 | |
15826 | struct intel_transcoder_error_state { | |
ddf9c536 | 15827 | bool power_domain_on; |
63b66e5b CW |
15828 | enum transcoder cpu_transcoder; |
15829 | ||
15830 | u32 conf; | |
15831 | ||
15832 | u32 htotal; | |
15833 | u32 hblank; | |
15834 | u32 hsync; | |
15835 | u32 vtotal; | |
15836 | u32 vblank; | |
15837 | u32 vsync; | |
15838 | } transcoder[4]; | |
c4a1d9e4 CW |
15839 | }; |
15840 | ||
15841 | struct intel_display_error_state * | |
15842 | intel_display_capture_error_state(struct drm_device *dev) | |
15843 | { | |
fbee40df | 15844 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 15845 | struct intel_display_error_state *error; |
63b66e5b CW |
15846 | int transcoders[] = { |
15847 | TRANSCODER_A, | |
15848 | TRANSCODER_B, | |
15849 | TRANSCODER_C, | |
15850 | TRANSCODER_EDP, | |
15851 | }; | |
c4a1d9e4 CW |
15852 | int i; |
15853 | ||
63b66e5b CW |
15854 | if (INTEL_INFO(dev)->num_pipes == 0) |
15855 | return NULL; | |
15856 | ||
9d1cb914 | 15857 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
15858 | if (error == NULL) |
15859 | return NULL; | |
15860 | ||
190be112 | 15861 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
15862 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
15863 | ||
055e393f | 15864 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 15865 | error->pipe[i].power_domain_on = |
f458ebbc DV |
15866 | __intel_display_power_is_enabled(dev_priv, |
15867 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 15868 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
15869 | continue; |
15870 | ||
5efb3e28 VS |
15871 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
15872 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
15873 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
15874 | |
15875 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
15876 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 15877 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 15878 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
15879 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
15880 | } | |
ca291363 PZ |
15881 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
15882 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
15883 | if (INTEL_INFO(dev)->gen >= 4) { |
15884 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
15885 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
15886 | } | |
15887 | ||
c4a1d9e4 | 15888 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 15889 | |
3abfce77 | 15890 | if (HAS_GMCH_DISPLAY(dev)) |
f301b1e1 | 15891 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
15892 | } |
15893 | ||
15894 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
15895 | if (HAS_DDI(dev_priv->dev)) | |
15896 | error->num_transcoders++; /* Account for eDP. */ | |
15897 | ||
15898 | for (i = 0; i < error->num_transcoders; i++) { | |
15899 | enum transcoder cpu_transcoder = transcoders[i]; | |
15900 | ||
ddf9c536 | 15901 | error->transcoder[i].power_domain_on = |
f458ebbc | 15902 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 15903 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 15904 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
15905 | continue; |
15906 | ||
63b66e5b CW |
15907 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
15908 | ||
15909 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
15910 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
15911 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
15912 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
15913 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
15914 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
15915 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
15916 | } |
15917 | ||
15918 | return error; | |
15919 | } | |
15920 | ||
edc3d884 MK |
15921 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
15922 | ||
c4a1d9e4 | 15923 | void |
edc3d884 | 15924 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
15925 | struct drm_device *dev, |
15926 | struct intel_display_error_state *error) | |
15927 | { | |
055e393f | 15928 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
15929 | int i; |
15930 | ||
63b66e5b CW |
15931 | if (!error) |
15932 | return; | |
15933 | ||
edc3d884 | 15934 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 15935 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 15936 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 15937 | error->power_well_driver); |
055e393f | 15938 | for_each_pipe(dev_priv, i) { |
edc3d884 | 15939 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 ID |
15940 | err_printf(m, " Power: %s\n", |
15941 | error->pipe[i].power_domain_on ? "on" : "off"); | |
edc3d884 | 15942 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 15943 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
15944 | |
15945 | err_printf(m, "Plane [%d]:\n", i); | |
15946 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
15947 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 15948 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
15949 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
15950 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 15951 | } |
4b71a570 | 15952 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 15953 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 15954 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
15955 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
15956 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
15957 | } |
15958 | ||
edc3d884 MK |
15959 | err_printf(m, "Cursor [%d]:\n", i); |
15960 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
15961 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
15962 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 15963 | } |
63b66e5b CW |
15964 | |
15965 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 15966 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 15967 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 ID |
15968 | err_printf(m, " Power: %s\n", |
15969 | error->transcoder[i].power_domain_on ? "on" : "off"); | |
63b66e5b CW |
15970 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
15971 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
15972 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
15973 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
15974 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
15975 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
15976 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
15977 | } | |
c4a1d9e4 | 15978 | } |
e2fcdaa9 VS |
15979 | |
15980 | void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file) | |
15981 | { | |
15982 | struct intel_crtc *crtc; | |
15983 | ||
15984 | for_each_intel_crtc(dev, crtc) { | |
15985 | struct intel_unpin_work *work; | |
e2fcdaa9 | 15986 | |
5e2d7afc | 15987 | spin_lock_irq(&dev->event_lock); |
e2fcdaa9 VS |
15988 | |
15989 | work = crtc->unpin_work; | |
15990 | ||
15991 | if (work && work->event && | |
15992 | work->event->base.file_priv == file) { | |
15993 | kfree(work->event); | |
15994 | work->event = NULL; | |
15995 | } | |
15996 | ||
5e2d7afc | 15997 | spin_unlock_irq(&dev->event_lock); |
e2fcdaa9 VS |
15998 | } |
15999 | } |