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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
319c1d42 | 40 | #include <drm/drm_atomic.h> |
c196e1d6 | 41 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
42 | #include <drm/drm_dp_helper.h> |
43 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
44 | #include <drm/drm_plane_helper.h> |
45 | #include <drm/drm_rect.h> | |
c0f372b3 | 46 | #include <linux/dma_remapping.h> |
fd8e058a AG |
47 | #include <linux/reservation.h> |
48 | #include <linux/dma-buf.h> | |
79e53945 | 49 | |
465c120c | 50 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 51 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
52 | DRM_FORMAT_C8, |
53 | DRM_FORMAT_RGB565, | |
465c120c | 54 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 55 | DRM_FORMAT_XRGB8888, |
465c120c MR |
56 | }; |
57 | ||
58 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 59 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
60 | DRM_FORMAT_C8, |
61 | DRM_FORMAT_RGB565, | |
62 | DRM_FORMAT_XRGB8888, | |
63 | DRM_FORMAT_XBGR8888, | |
64 | DRM_FORMAT_XRGB2101010, | |
65 | DRM_FORMAT_XBGR2101010, | |
66 | }; | |
67 | ||
68 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
69 | DRM_FORMAT_C8, |
70 | DRM_FORMAT_RGB565, | |
71 | DRM_FORMAT_XRGB8888, | |
465c120c | 72 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 73 | DRM_FORMAT_ARGB8888, |
465c120c MR |
74 | DRM_FORMAT_ABGR8888, |
75 | DRM_FORMAT_XRGB2101010, | |
465c120c | 76 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
77 | DRM_FORMAT_YUYV, |
78 | DRM_FORMAT_YVYU, | |
79 | DRM_FORMAT_UYVY, | |
80 | DRM_FORMAT_VYUY, | |
465c120c MR |
81 | }; |
82 | ||
3d7d6510 MR |
83 | /* Cursor formats */ |
84 | static const uint32_t intel_cursor_formats[] = { | |
85 | DRM_FORMAT_ARGB8888, | |
86 | }; | |
87 | ||
f1f644dc | 88 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 89 | struct intel_crtc_state *pipe_config); |
18442d08 | 90 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 91 | struct intel_crtc_state *pipe_config); |
f1f644dc | 92 | |
eb1bfe80 JB |
93 | static int intel_framebuffer_init(struct drm_device *dev, |
94 | struct intel_framebuffer *ifb, | |
95 | struct drm_mode_fb_cmd2 *mode_cmd, | |
96 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
97 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
98 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
bc58be60 | 99 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc); |
29407aab | 100 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
101 | struct intel_link_m_n *m_n, |
102 | struct intel_link_m_n *m2_n2); | |
29407aab | 103 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 | 104 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
391bf048 | 105 | static void haswell_set_pipemisc(struct drm_crtc *crtc); |
d288f65f | 106 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 107 | const struct intel_crtc_state *pipe_config); |
d288f65f | 108 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 109 | const struct intel_crtc_state *pipe_config); |
613d2b27 ML |
110 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
111 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
549e2bfb CK |
112 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
113 | struct intel_crtc_state *crtc_state); | |
5ab7b0b7 ID |
114 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
115 | int num_connectors); | |
bfd16b2a ML |
116 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
117 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
118 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
043e9bda | 119 | static void intel_modeset_setup_hw_state(struct drm_device *dev); |
2622a081 | 120 | static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc); |
e7457a9a | 121 | |
79e53945 | 122 | typedef struct { |
0206e353 | 123 | int min, max; |
79e53945 JB |
124 | } intel_range_t; |
125 | ||
126 | typedef struct { | |
0206e353 AJ |
127 | int dot_limit; |
128 | int p2_slow, p2_fast; | |
79e53945 JB |
129 | } intel_p2_t; |
130 | ||
d4906093 ML |
131 | typedef struct intel_limit intel_limit_t; |
132 | struct intel_limit { | |
0206e353 AJ |
133 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
134 | intel_p2_t p2; | |
d4906093 | 135 | }; |
79e53945 | 136 | |
bfa7df01 VS |
137 | /* returns HPLL frequency in kHz */ |
138 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) | |
139 | { | |
140 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
141 | ||
142 | /* Obtain SKU information */ | |
143 | mutex_lock(&dev_priv->sb_lock); | |
144 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
145 | CCK_FUSE_HPLL_FREQ_MASK; | |
146 | mutex_unlock(&dev_priv->sb_lock); | |
147 | ||
148 | return vco_freq[hpll_freq] * 1000; | |
149 | } | |
150 | ||
151 | static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, | |
152 | const char *name, u32 reg) | |
153 | { | |
154 | u32 val; | |
155 | int divider; | |
156 | ||
157 | if (dev_priv->hpll_freq == 0) | |
158 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
159 | ||
160 | mutex_lock(&dev_priv->sb_lock); | |
161 | val = vlv_cck_read(dev_priv, reg); | |
162 | mutex_unlock(&dev_priv->sb_lock); | |
163 | ||
164 | divider = val & CCK_FREQUENCY_VALUES; | |
165 | ||
166 | WARN((val & CCK_FREQUENCY_STATUS) != | |
167 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
168 | "%s change in progress\n", name); | |
169 | ||
170 | return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); | |
171 | } | |
172 | ||
e7dc33f3 VS |
173 | static int |
174 | intel_pch_rawclk(struct drm_i915_private *dev_priv) | |
d2acd215 | 175 | { |
e7dc33f3 VS |
176 | return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; |
177 | } | |
d2acd215 | 178 | |
e7dc33f3 VS |
179 | static int |
180 | intel_vlv_hrawclk(struct drm_i915_private *dev_priv) | |
181 | { | |
35d38d1f VS |
182 | return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", |
183 | CCK_DISPLAY_REF_CLOCK_CONTROL); | |
d2acd215 DV |
184 | } |
185 | ||
e7dc33f3 VS |
186 | static int |
187 | intel_g4x_hrawclk(struct drm_i915_private *dev_priv) | |
79e50a4f | 188 | { |
79e50a4f JN |
189 | uint32_t clkcfg; |
190 | ||
e7dc33f3 | 191 | /* hrawclock is 1/4 the FSB frequency */ |
79e50a4f JN |
192 | clkcfg = I915_READ(CLKCFG); |
193 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
194 | case CLKCFG_FSB_400: | |
e7dc33f3 | 195 | return 100000; |
79e50a4f | 196 | case CLKCFG_FSB_533: |
e7dc33f3 | 197 | return 133333; |
79e50a4f | 198 | case CLKCFG_FSB_667: |
e7dc33f3 | 199 | return 166667; |
79e50a4f | 200 | case CLKCFG_FSB_800: |
e7dc33f3 | 201 | return 200000; |
79e50a4f | 202 | case CLKCFG_FSB_1067: |
e7dc33f3 | 203 | return 266667; |
79e50a4f | 204 | case CLKCFG_FSB_1333: |
e7dc33f3 | 205 | return 333333; |
79e50a4f JN |
206 | /* these two are just a guess; one of them might be right */ |
207 | case CLKCFG_FSB_1600: | |
208 | case CLKCFG_FSB_1600_ALT: | |
e7dc33f3 | 209 | return 400000; |
79e50a4f | 210 | default: |
e7dc33f3 | 211 | return 133333; |
79e50a4f JN |
212 | } |
213 | } | |
214 | ||
e7dc33f3 VS |
215 | static void intel_update_rawclk(struct drm_i915_private *dev_priv) |
216 | { | |
217 | if (HAS_PCH_SPLIT(dev_priv)) | |
218 | dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv); | |
219 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
220 | dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv); | |
221 | else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv)) | |
222 | dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv); | |
223 | else | |
224 | return; /* no rawclk on other platforms, or no need to know it */ | |
225 | ||
226 | DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq); | |
227 | } | |
228 | ||
bfa7df01 VS |
229 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
230 | { | |
666a4537 | 231 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
bfa7df01 VS |
232 | return; |
233 | ||
234 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
235 | CCK_CZ_CLOCK_CONTROL); | |
236 | ||
237 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); | |
238 | } | |
239 | ||
021357ac | 240 | static inline u32 /* units of 100MHz */ |
21a727b3 VS |
241 | intel_fdi_link_freq(struct drm_i915_private *dev_priv, |
242 | const struct intel_crtc_state *pipe_config) | |
021357ac | 243 | { |
21a727b3 VS |
244 | if (HAS_DDI(dev_priv)) |
245 | return pipe_config->port_clock; /* SPLL */ | |
246 | else if (IS_GEN5(dev_priv)) | |
247 | return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000; | |
e3b247da | 248 | else |
21a727b3 | 249 | return 270000; |
021357ac CW |
250 | } |
251 | ||
5d536e28 | 252 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 253 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 254 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 255 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
256 | .m = { .min = 96, .max = 140 }, |
257 | .m1 = { .min = 18, .max = 26 }, | |
258 | .m2 = { .min = 6, .max = 16 }, | |
259 | .p = { .min = 4, .max = 128 }, | |
260 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
261 | .p2 = { .dot_limit = 165000, |
262 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
263 | }; |
264 | ||
5d536e28 DV |
265 | static const intel_limit_t intel_limits_i8xx_dvo = { |
266 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 267 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 268 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
269 | .m = { .min = 96, .max = 140 }, |
270 | .m1 = { .min = 18, .max = 26 }, | |
271 | .m2 = { .min = 6, .max = 16 }, | |
272 | .p = { .min = 4, .max = 128 }, | |
273 | .p1 = { .min = 2, .max = 33 }, | |
274 | .p2 = { .dot_limit = 165000, | |
275 | .p2_slow = 4, .p2_fast = 4 }, | |
276 | }; | |
277 | ||
e4b36699 | 278 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 279 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 280 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 281 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
282 | .m = { .min = 96, .max = 140 }, |
283 | .m1 = { .min = 18, .max = 26 }, | |
284 | .m2 = { .min = 6, .max = 16 }, | |
285 | .p = { .min = 4, .max = 128 }, | |
286 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
287 | .p2 = { .dot_limit = 165000, |
288 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 289 | }; |
273e27ca | 290 | |
e4b36699 | 291 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
292 | .dot = { .min = 20000, .max = 400000 }, |
293 | .vco = { .min = 1400000, .max = 2800000 }, | |
294 | .n = { .min = 1, .max = 6 }, | |
295 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
296 | .m1 = { .min = 8, .max = 18 }, |
297 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
298 | .p = { .min = 5, .max = 80 }, |
299 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
300 | .p2 = { .dot_limit = 200000, |
301 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
302 | }; |
303 | ||
304 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
305 | .dot = { .min = 20000, .max = 400000 }, |
306 | .vco = { .min = 1400000, .max = 2800000 }, | |
307 | .n = { .min = 1, .max = 6 }, | |
308 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
309 | .m1 = { .min = 8, .max = 18 }, |
310 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
311 | .p = { .min = 7, .max = 98 }, |
312 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
313 | .p2 = { .dot_limit = 112000, |
314 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
315 | }; |
316 | ||
273e27ca | 317 | |
e4b36699 | 318 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
319 | .dot = { .min = 25000, .max = 270000 }, |
320 | .vco = { .min = 1750000, .max = 3500000}, | |
321 | .n = { .min = 1, .max = 4 }, | |
322 | .m = { .min = 104, .max = 138 }, | |
323 | .m1 = { .min = 17, .max = 23 }, | |
324 | .m2 = { .min = 5, .max = 11 }, | |
325 | .p = { .min = 10, .max = 30 }, | |
326 | .p1 = { .min = 1, .max = 3}, | |
327 | .p2 = { .dot_limit = 270000, | |
328 | .p2_slow = 10, | |
329 | .p2_fast = 10 | |
044c7c41 | 330 | }, |
e4b36699 KP |
331 | }; |
332 | ||
333 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
334 | .dot = { .min = 22000, .max = 400000 }, |
335 | .vco = { .min = 1750000, .max = 3500000}, | |
336 | .n = { .min = 1, .max = 4 }, | |
337 | .m = { .min = 104, .max = 138 }, | |
338 | .m1 = { .min = 16, .max = 23 }, | |
339 | .m2 = { .min = 5, .max = 11 }, | |
340 | .p = { .min = 5, .max = 80 }, | |
341 | .p1 = { .min = 1, .max = 8}, | |
342 | .p2 = { .dot_limit = 165000, | |
343 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
344 | }; |
345 | ||
346 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
347 | .dot = { .min = 20000, .max = 115000 }, |
348 | .vco = { .min = 1750000, .max = 3500000 }, | |
349 | .n = { .min = 1, .max = 3 }, | |
350 | .m = { .min = 104, .max = 138 }, | |
351 | .m1 = { .min = 17, .max = 23 }, | |
352 | .m2 = { .min = 5, .max = 11 }, | |
353 | .p = { .min = 28, .max = 112 }, | |
354 | .p1 = { .min = 2, .max = 8 }, | |
355 | .p2 = { .dot_limit = 0, | |
356 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 357 | }, |
e4b36699 KP |
358 | }; |
359 | ||
360 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
361 | .dot = { .min = 80000, .max = 224000 }, |
362 | .vco = { .min = 1750000, .max = 3500000 }, | |
363 | .n = { .min = 1, .max = 3 }, | |
364 | .m = { .min = 104, .max = 138 }, | |
365 | .m1 = { .min = 17, .max = 23 }, | |
366 | .m2 = { .min = 5, .max = 11 }, | |
367 | .p = { .min = 14, .max = 42 }, | |
368 | .p1 = { .min = 2, .max = 6 }, | |
369 | .p2 = { .dot_limit = 0, | |
370 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 371 | }, |
e4b36699 KP |
372 | }; |
373 | ||
f2b115e6 | 374 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
375 | .dot = { .min = 20000, .max = 400000}, |
376 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 377 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
378 | .n = { .min = 3, .max = 6 }, |
379 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 380 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
381 | .m1 = { .min = 0, .max = 0 }, |
382 | .m2 = { .min = 0, .max = 254 }, | |
383 | .p = { .min = 5, .max = 80 }, | |
384 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
385 | .p2 = { .dot_limit = 200000, |
386 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
387 | }; |
388 | ||
f2b115e6 | 389 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
390 | .dot = { .min = 20000, .max = 400000 }, |
391 | .vco = { .min = 1700000, .max = 3500000 }, | |
392 | .n = { .min = 3, .max = 6 }, | |
393 | .m = { .min = 2, .max = 256 }, | |
394 | .m1 = { .min = 0, .max = 0 }, | |
395 | .m2 = { .min = 0, .max = 254 }, | |
396 | .p = { .min = 7, .max = 112 }, | |
397 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
398 | .p2 = { .dot_limit = 112000, |
399 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
400 | }; |
401 | ||
273e27ca EA |
402 | /* Ironlake / Sandybridge |
403 | * | |
404 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
405 | * the range value for them is (actual_value - 2). | |
406 | */ | |
b91ad0ec | 407 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
408 | .dot = { .min = 25000, .max = 350000 }, |
409 | .vco = { .min = 1760000, .max = 3510000 }, | |
410 | .n = { .min = 1, .max = 5 }, | |
411 | .m = { .min = 79, .max = 127 }, | |
412 | .m1 = { .min = 12, .max = 22 }, | |
413 | .m2 = { .min = 5, .max = 9 }, | |
414 | .p = { .min = 5, .max = 80 }, | |
415 | .p1 = { .min = 1, .max = 8 }, | |
416 | .p2 = { .dot_limit = 225000, | |
417 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
418 | }; |
419 | ||
b91ad0ec | 420 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
421 | .dot = { .min = 25000, .max = 350000 }, |
422 | .vco = { .min = 1760000, .max = 3510000 }, | |
423 | .n = { .min = 1, .max = 3 }, | |
424 | .m = { .min = 79, .max = 118 }, | |
425 | .m1 = { .min = 12, .max = 22 }, | |
426 | .m2 = { .min = 5, .max = 9 }, | |
427 | .p = { .min = 28, .max = 112 }, | |
428 | .p1 = { .min = 2, .max = 8 }, | |
429 | .p2 = { .dot_limit = 225000, | |
430 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
431 | }; |
432 | ||
433 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
434 | .dot = { .min = 25000, .max = 350000 }, |
435 | .vco = { .min = 1760000, .max = 3510000 }, | |
436 | .n = { .min = 1, .max = 3 }, | |
437 | .m = { .min = 79, .max = 127 }, | |
438 | .m1 = { .min = 12, .max = 22 }, | |
439 | .m2 = { .min = 5, .max = 9 }, | |
440 | .p = { .min = 14, .max = 56 }, | |
441 | .p1 = { .min = 2, .max = 8 }, | |
442 | .p2 = { .dot_limit = 225000, | |
443 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
444 | }; |
445 | ||
273e27ca | 446 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 447 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
448 | .dot = { .min = 25000, .max = 350000 }, |
449 | .vco = { .min = 1760000, .max = 3510000 }, | |
450 | .n = { .min = 1, .max = 2 }, | |
451 | .m = { .min = 79, .max = 126 }, | |
452 | .m1 = { .min = 12, .max = 22 }, | |
453 | .m2 = { .min = 5, .max = 9 }, | |
454 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 455 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
456 | .p2 = { .dot_limit = 225000, |
457 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
458 | }; |
459 | ||
460 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
461 | .dot = { .min = 25000, .max = 350000 }, |
462 | .vco = { .min = 1760000, .max = 3510000 }, | |
463 | .n = { .min = 1, .max = 3 }, | |
464 | .m = { .min = 79, .max = 126 }, | |
465 | .m1 = { .min = 12, .max = 22 }, | |
466 | .m2 = { .min = 5, .max = 9 }, | |
467 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 468 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
469 | .p2 = { .dot_limit = 225000, |
470 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
471 | }; |
472 | ||
dc730512 | 473 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
474 | /* |
475 | * These are the data rate limits (measured in fast clocks) | |
476 | * since those are the strictest limits we have. The fast | |
477 | * clock and actual rate limits are more relaxed, so checking | |
478 | * them would make no difference. | |
479 | */ | |
480 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 481 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 482 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
483 | .m1 = { .min = 2, .max = 3 }, |
484 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 485 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 486 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
487 | }; |
488 | ||
ef9348c8 CML |
489 | static const intel_limit_t intel_limits_chv = { |
490 | /* | |
491 | * These are the data rate limits (measured in fast clocks) | |
492 | * since those are the strictest limits we have. The fast | |
493 | * clock and actual rate limits are more relaxed, so checking | |
494 | * them would make no difference. | |
495 | */ | |
496 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 497 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
498 | .n = { .min = 1, .max = 1 }, |
499 | .m1 = { .min = 2, .max = 2 }, | |
500 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
501 | .p1 = { .min = 2, .max = 4 }, | |
502 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
503 | }; | |
504 | ||
5ab7b0b7 ID |
505 | static const intel_limit_t intel_limits_bxt = { |
506 | /* FIXME: find real dot limits */ | |
507 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 508 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
509 | .n = { .min = 1, .max = 1 }, |
510 | .m1 = { .min = 2, .max = 2 }, | |
511 | /* FIXME: find real m2 limits */ | |
512 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
513 | .p1 = { .min = 2, .max = 4 }, | |
514 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
515 | }; | |
516 | ||
cdba954e ACO |
517 | static bool |
518 | needs_modeset(struct drm_crtc_state *state) | |
519 | { | |
fc596660 | 520 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
521 | } |
522 | ||
e0638cdf PZ |
523 | /** |
524 | * Returns whether any output on the specified pipe is of the specified type | |
525 | */ | |
4093561b | 526 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) |
e0638cdf | 527 | { |
409ee761 | 528 | struct drm_device *dev = crtc->base.dev; |
e0638cdf PZ |
529 | struct intel_encoder *encoder; |
530 | ||
409ee761 | 531 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
e0638cdf PZ |
532 | if (encoder->type == type) |
533 | return true; | |
534 | ||
535 | return false; | |
536 | } | |
537 | ||
d0737e1d ACO |
538 | /** |
539 | * Returns whether any output on the specified pipe will have the specified | |
540 | * type after a staged modeset is complete, i.e., the same as | |
541 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of | |
542 | * encoder->crtc. | |
543 | */ | |
a93e255f ACO |
544 | static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state, |
545 | int type) | |
d0737e1d | 546 | { |
a93e255f | 547 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 548 | struct drm_connector *connector; |
a93e255f | 549 | struct drm_connector_state *connector_state; |
d0737e1d | 550 | struct intel_encoder *encoder; |
a93e255f ACO |
551 | int i, num_connectors = 0; |
552 | ||
da3ced29 | 553 | for_each_connector_in_state(state, connector, connector_state, i) { |
a93e255f ACO |
554 | if (connector_state->crtc != crtc_state->base.crtc) |
555 | continue; | |
556 | ||
557 | num_connectors++; | |
d0737e1d | 558 | |
a93e255f ACO |
559 | encoder = to_intel_encoder(connector_state->best_encoder); |
560 | if (encoder->type == type) | |
d0737e1d | 561 | return true; |
a93e255f ACO |
562 | } |
563 | ||
564 | WARN_ON(num_connectors == 0); | |
d0737e1d ACO |
565 | |
566 | return false; | |
567 | } | |
568 | ||
a93e255f ACO |
569 | static const intel_limit_t * |
570 | intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk) | |
2c07245f | 571 | { |
a93e255f | 572 | struct drm_device *dev = crtc_state->base.crtc->dev; |
2c07245f | 573 | const intel_limit_t *limit; |
b91ad0ec | 574 | |
a93e255f | 575 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 576 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 577 | if (refclk == 100000) |
b91ad0ec ZW |
578 | limit = &intel_limits_ironlake_dual_lvds_100m; |
579 | else | |
580 | limit = &intel_limits_ironlake_dual_lvds; | |
581 | } else { | |
1b894b59 | 582 | if (refclk == 100000) |
b91ad0ec ZW |
583 | limit = &intel_limits_ironlake_single_lvds_100m; |
584 | else | |
585 | limit = &intel_limits_ironlake_single_lvds; | |
586 | } | |
c6bb3538 | 587 | } else |
b91ad0ec | 588 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
589 | |
590 | return limit; | |
591 | } | |
592 | ||
a93e255f ACO |
593 | static const intel_limit_t * |
594 | intel_g4x_limit(struct intel_crtc_state *crtc_state) | |
044c7c41 | 595 | { |
a93e255f | 596 | struct drm_device *dev = crtc_state->base.crtc->dev; |
044c7c41 ML |
597 | const intel_limit_t *limit; |
598 | ||
a93e255f | 599 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 600 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 601 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 602 | else |
e4b36699 | 603 | limit = &intel_limits_g4x_single_channel_lvds; |
a93e255f ACO |
604 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) || |
605 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 606 | limit = &intel_limits_g4x_hdmi; |
a93e255f | 607 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 608 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 609 | } else /* The option is for other outputs */ |
e4b36699 | 610 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
611 | |
612 | return limit; | |
613 | } | |
614 | ||
a93e255f ACO |
615 | static const intel_limit_t * |
616 | intel_limit(struct intel_crtc_state *crtc_state, int refclk) | |
79e53945 | 617 | { |
a93e255f | 618 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 JB |
619 | const intel_limit_t *limit; |
620 | ||
5ab7b0b7 ID |
621 | if (IS_BROXTON(dev)) |
622 | limit = &intel_limits_bxt; | |
623 | else if (HAS_PCH_SPLIT(dev)) | |
a93e255f | 624 | limit = intel_ironlake_limit(crtc_state, refclk); |
2c07245f | 625 | else if (IS_G4X(dev)) { |
a93e255f | 626 | limit = intel_g4x_limit(crtc_state); |
f2b115e6 | 627 | } else if (IS_PINEVIEW(dev)) { |
a93e255f | 628 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 629 | limit = &intel_limits_pineview_lvds; |
2177832f | 630 | else |
f2b115e6 | 631 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
632 | } else if (IS_CHERRYVIEW(dev)) { |
633 | limit = &intel_limits_chv; | |
a0c4da24 | 634 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 635 | limit = &intel_limits_vlv; |
a6c45cf0 | 636 | } else if (!IS_GEN2(dev)) { |
a93e255f | 637 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a6c45cf0 CW |
638 | limit = &intel_limits_i9xx_lvds; |
639 | else | |
640 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 | 641 | } else { |
a93e255f | 642 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
e4b36699 | 643 | limit = &intel_limits_i8xx_lvds; |
a93e255f | 644 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
e4b36699 | 645 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
646 | else |
647 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
648 | } |
649 | return limit; | |
650 | } | |
651 | ||
dccbea3b ID |
652 | /* |
653 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
654 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
655 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
656 | * The helpers' return value is the rate of the clock that is fed to the | |
657 | * display engine's pipe which can be the above fast dot clock rate or a | |
658 | * divided-down version of it. | |
659 | */ | |
f2b115e6 | 660 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
dccbea3b | 661 | static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock) |
79e53945 | 662 | { |
2177832f SL |
663 | clock->m = clock->m2 + 2; |
664 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 665 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 666 | return 0; |
fb03ac01 VS |
667 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
668 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
669 | |
670 | return clock->dot; | |
2177832f SL |
671 | } |
672 | ||
7429e9d4 DV |
673 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
674 | { | |
675 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
676 | } | |
677 | ||
dccbea3b | 678 | static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock) |
2177832f | 679 | { |
7429e9d4 | 680 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 681 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 682 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 683 | return 0; |
fb03ac01 VS |
684 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
685 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
686 | |
687 | return clock->dot; | |
79e53945 JB |
688 | } |
689 | ||
dccbea3b | 690 | static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock) |
589eca67 ID |
691 | { |
692 | clock->m = clock->m1 * clock->m2; | |
693 | clock->p = clock->p1 * clock->p2; | |
694 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 695 | return 0; |
589eca67 ID |
696 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
697 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
698 | |
699 | return clock->dot / 5; | |
589eca67 ID |
700 | } |
701 | ||
dccbea3b | 702 | int chv_calc_dpll_params(int refclk, intel_clock_t *clock) |
ef9348c8 CML |
703 | { |
704 | clock->m = clock->m1 * clock->m2; | |
705 | clock->p = clock->p1 * clock->p2; | |
706 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 707 | return 0; |
ef9348c8 CML |
708 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
709 | clock->n << 22); | |
710 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
711 | |
712 | return clock->dot / 5; | |
ef9348c8 CML |
713 | } |
714 | ||
7c04d1d9 | 715 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
716 | /** |
717 | * Returns whether the given set of divisors are valid for a given refclk with | |
718 | * the given connectors. | |
719 | */ | |
720 | ||
1b894b59 CW |
721 | static bool intel_PLL_is_valid(struct drm_device *dev, |
722 | const intel_limit_t *limit, | |
723 | const intel_clock_t *clock) | |
79e53945 | 724 | { |
f01b7962 VS |
725 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
726 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 727 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 728 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 729 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 730 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 731 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 732 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 733 | |
666a4537 WB |
734 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && |
735 | !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) | |
f01b7962 VS |
736 | if (clock->m1 <= clock->m2) |
737 | INTELPllInvalid("m1 <= m2\n"); | |
738 | ||
666a4537 | 739 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) { |
f01b7962 VS |
740 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
741 | INTELPllInvalid("p out of range\n"); | |
742 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
743 | INTELPllInvalid("m out of range\n"); | |
744 | } | |
745 | ||
79e53945 | 746 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 747 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
748 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
749 | * connector, etc., rather than just a single range. | |
750 | */ | |
751 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 752 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
753 | |
754 | return true; | |
755 | } | |
756 | ||
3b1429d9 VS |
757 | static int |
758 | i9xx_select_p2_div(const intel_limit_t *limit, | |
759 | const struct intel_crtc_state *crtc_state, | |
760 | int target) | |
79e53945 | 761 | { |
3b1429d9 | 762 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 763 | |
a93e255f | 764 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 765 | /* |
a210b028 DV |
766 | * For LVDS just rely on its current settings for dual-channel. |
767 | * We haven't figured out how to reliably set up different | |
768 | * single/dual channel state, if we even can. | |
79e53945 | 769 | */ |
1974cad0 | 770 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 771 | return limit->p2.p2_fast; |
79e53945 | 772 | else |
3b1429d9 | 773 | return limit->p2.p2_slow; |
79e53945 JB |
774 | } else { |
775 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 776 | return limit->p2.p2_slow; |
79e53945 | 777 | else |
3b1429d9 | 778 | return limit->p2.p2_fast; |
79e53945 | 779 | } |
3b1429d9 VS |
780 | } |
781 | ||
782 | static bool | |
783 | i9xx_find_best_dpll(const intel_limit_t *limit, | |
784 | struct intel_crtc_state *crtc_state, | |
785 | int target, int refclk, intel_clock_t *match_clock, | |
786 | intel_clock_t *best_clock) | |
787 | { | |
788 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
789 | intel_clock_t clock; | |
790 | int err = target; | |
79e53945 | 791 | |
0206e353 | 792 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 793 | |
3b1429d9 VS |
794 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
795 | ||
42158660 ZY |
796 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
797 | clock.m1++) { | |
798 | for (clock.m2 = limit->m2.min; | |
799 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 800 | if (clock.m2 >= clock.m1) |
42158660 ZY |
801 | break; |
802 | for (clock.n = limit->n.min; | |
803 | clock.n <= limit->n.max; clock.n++) { | |
804 | for (clock.p1 = limit->p1.min; | |
805 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
806 | int this_err; |
807 | ||
dccbea3b | 808 | i9xx_calc_dpll_params(refclk, &clock); |
ac58c3f0 DV |
809 | if (!intel_PLL_is_valid(dev, limit, |
810 | &clock)) | |
811 | continue; | |
812 | if (match_clock && | |
813 | clock.p != match_clock->p) | |
814 | continue; | |
815 | ||
816 | this_err = abs(clock.dot - target); | |
817 | if (this_err < err) { | |
818 | *best_clock = clock; | |
819 | err = this_err; | |
820 | } | |
821 | } | |
822 | } | |
823 | } | |
824 | } | |
825 | ||
826 | return (err != target); | |
827 | } | |
828 | ||
829 | static bool | |
a93e255f ACO |
830 | pnv_find_best_dpll(const intel_limit_t *limit, |
831 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
832 | int target, int refclk, intel_clock_t *match_clock, |
833 | intel_clock_t *best_clock) | |
79e53945 | 834 | { |
3b1429d9 | 835 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 836 | intel_clock_t clock; |
79e53945 JB |
837 | int err = target; |
838 | ||
0206e353 | 839 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 840 | |
3b1429d9 VS |
841 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
842 | ||
42158660 ZY |
843 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
844 | clock.m1++) { | |
845 | for (clock.m2 = limit->m2.min; | |
846 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
847 | for (clock.n = limit->n.min; |
848 | clock.n <= limit->n.max; clock.n++) { | |
849 | for (clock.p1 = limit->p1.min; | |
850 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
851 | int this_err; |
852 | ||
dccbea3b | 853 | pnv_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
854 | if (!intel_PLL_is_valid(dev, limit, |
855 | &clock)) | |
79e53945 | 856 | continue; |
cec2f356 SP |
857 | if (match_clock && |
858 | clock.p != match_clock->p) | |
859 | continue; | |
79e53945 JB |
860 | |
861 | this_err = abs(clock.dot - target); | |
862 | if (this_err < err) { | |
863 | *best_clock = clock; | |
864 | err = this_err; | |
865 | } | |
866 | } | |
867 | } | |
868 | } | |
869 | } | |
870 | ||
871 | return (err != target); | |
872 | } | |
873 | ||
d4906093 | 874 | static bool |
a93e255f ACO |
875 | g4x_find_best_dpll(const intel_limit_t *limit, |
876 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
877 | int target, int refclk, intel_clock_t *match_clock, |
878 | intel_clock_t *best_clock) | |
d4906093 | 879 | { |
3b1429d9 | 880 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d4906093 ML |
881 | intel_clock_t clock; |
882 | int max_n; | |
3b1429d9 | 883 | bool found = false; |
6ba770dc AJ |
884 | /* approximately equals target * 0.00585 */ |
885 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
886 | |
887 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
888 | |
889 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
890 | ||
d4906093 | 891 | max_n = limit->n.max; |
f77f13e2 | 892 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 893 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 894 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
895 | for (clock.m1 = limit->m1.max; |
896 | clock.m1 >= limit->m1.min; clock.m1--) { | |
897 | for (clock.m2 = limit->m2.max; | |
898 | clock.m2 >= limit->m2.min; clock.m2--) { | |
899 | for (clock.p1 = limit->p1.max; | |
900 | clock.p1 >= limit->p1.min; clock.p1--) { | |
901 | int this_err; | |
902 | ||
dccbea3b | 903 | i9xx_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
904 | if (!intel_PLL_is_valid(dev, limit, |
905 | &clock)) | |
d4906093 | 906 | continue; |
1b894b59 CW |
907 | |
908 | this_err = abs(clock.dot - target); | |
d4906093 ML |
909 | if (this_err < err_most) { |
910 | *best_clock = clock; | |
911 | err_most = this_err; | |
912 | max_n = clock.n; | |
913 | found = true; | |
914 | } | |
915 | } | |
916 | } | |
917 | } | |
918 | } | |
2c07245f ZW |
919 | return found; |
920 | } | |
921 | ||
d5dd62bd ID |
922 | /* |
923 | * Check if the calculated PLL configuration is more optimal compared to the | |
924 | * best configuration and error found so far. Return the calculated error. | |
925 | */ | |
926 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
927 | const intel_clock_t *calculated_clock, | |
928 | const intel_clock_t *best_clock, | |
929 | unsigned int best_error_ppm, | |
930 | unsigned int *error_ppm) | |
931 | { | |
9ca3ba01 ID |
932 | /* |
933 | * For CHV ignore the error and consider only the P value. | |
934 | * Prefer a bigger P value based on HW requirements. | |
935 | */ | |
936 | if (IS_CHERRYVIEW(dev)) { | |
937 | *error_ppm = 0; | |
938 | ||
939 | return calculated_clock->p > best_clock->p; | |
940 | } | |
941 | ||
24be4e46 ID |
942 | if (WARN_ON_ONCE(!target_freq)) |
943 | return false; | |
944 | ||
d5dd62bd ID |
945 | *error_ppm = div_u64(1000000ULL * |
946 | abs(target_freq - calculated_clock->dot), | |
947 | target_freq); | |
948 | /* | |
949 | * Prefer a better P value over a better (smaller) error if the error | |
950 | * is small. Ensure this preference for future configurations too by | |
951 | * setting the error to 0. | |
952 | */ | |
953 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
954 | *error_ppm = 0; | |
955 | ||
956 | return true; | |
957 | } | |
958 | ||
959 | return *error_ppm + 10 < best_error_ppm; | |
960 | } | |
961 | ||
a0c4da24 | 962 | static bool |
a93e255f ACO |
963 | vlv_find_best_dpll(const intel_limit_t *limit, |
964 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
965 | int target, int refclk, intel_clock_t *match_clock, |
966 | intel_clock_t *best_clock) | |
a0c4da24 | 967 | { |
a93e255f | 968 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 969 | struct drm_device *dev = crtc->base.dev; |
6b4bf1c4 | 970 | intel_clock_t clock; |
69e4f900 | 971 | unsigned int bestppm = 1000000; |
27e639bf VS |
972 | /* min update 19.2 MHz */ |
973 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 974 | bool found = false; |
a0c4da24 | 975 | |
6b4bf1c4 VS |
976 | target *= 5; /* fast clock */ |
977 | ||
978 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
979 | |
980 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 981 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 982 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 983 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 984 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 985 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 986 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 987 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 988 | unsigned int ppm; |
69e4f900 | 989 | |
6b4bf1c4 VS |
990 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
991 | refclk * clock.m1); | |
992 | ||
dccbea3b | 993 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 994 | |
f01b7962 VS |
995 | if (!intel_PLL_is_valid(dev, limit, |
996 | &clock)) | |
43b0ac53 VS |
997 | continue; |
998 | ||
d5dd62bd ID |
999 | if (!vlv_PLL_is_optimal(dev, target, |
1000 | &clock, | |
1001 | best_clock, | |
1002 | bestppm, &ppm)) | |
1003 | continue; | |
6b4bf1c4 | 1004 | |
d5dd62bd ID |
1005 | *best_clock = clock; |
1006 | bestppm = ppm; | |
1007 | found = true; | |
a0c4da24 JB |
1008 | } |
1009 | } | |
1010 | } | |
1011 | } | |
a0c4da24 | 1012 | |
49e497ef | 1013 | return found; |
a0c4da24 | 1014 | } |
a4fc5ed6 | 1015 | |
ef9348c8 | 1016 | static bool |
a93e255f ACO |
1017 | chv_find_best_dpll(const intel_limit_t *limit, |
1018 | struct intel_crtc_state *crtc_state, | |
ef9348c8 CML |
1019 | int target, int refclk, intel_clock_t *match_clock, |
1020 | intel_clock_t *best_clock) | |
1021 | { | |
a93e255f | 1022 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 1023 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 1024 | unsigned int best_error_ppm; |
ef9348c8 CML |
1025 | intel_clock_t clock; |
1026 | uint64_t m2; | |
1027 | int found = false; | |
1028 | ||
1029 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 1030 | best_error_ppm = 1000000; |
ef9348c8 CML |
1031 | |
1032 | /* | |
1033 | * Based on hardware doc, the n always set to 1, and m1 always | |
1034 | * set to 2. If requires to support 200Mhz refclk, we need to | |
1035 | * revisit this because n may not 1 anymore. | |
1036 | */ | |
1037 | clock.n = 1, clock.m1 = 2; | |
1038 | target *= 5; /* fast clock */ | |
1039 | ||
1040 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
1041 | for (clock.p2 = limit->p2.p2_fast; | |
1042 | clock.p2 >= limit->p2.p2_slow; | |
1043 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 1044 | unsigned int error_ppm; |
ef9348c8 CML |
1045 | |
1046 | clock.p = clock.p1 * clock.p2; | |
1047 | ||
1048 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
1049 | clock.n) << 22, refclk * clock.m1); | |
1050 | ||
1051 | if (m2 > INT_MAX/clock.m1) | |
1052 | continue; | |
1053 | ||
1054 | clock.m2 = m2; | |
1055 | ||
dccbea3b | 1056 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 CML |
1057 | |
1058 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
1059 | continue; | |
1060 | ||
9ca3ba01 ID |
1061 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
1062 | best_error_ppm, &error_ppm)) | |
1063 | continue; | |
1064 | ||
1065 | *best_clock = clock; | |
1066 | best_error_ppm = error_ppm; | |
1067 | found = true; | |
ef9348c8 CML |
1068 | } |
1069 | } | |
1070 | ||
1071 | return found; | |
1072 | } | |
1073 | ||
5ab7b0b7 ID |
1074 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
1075 | intel_clock_t *best_clock) | |
1076 | { | |
1077 | int refclk = i9xx_get_refclk(crtc_state, 0); | |
1078 | ||
1079 | return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state, | |
1080 | target_clock, refclk, NULL, best_clock); | |
1081 | } | |
1082 | ||
20ddf665 VS |
1083 | bool intel_crtc_active(struct drm_crtc *crtc) |
1084 | { | |
1085 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1086 | ||
1087 | /* Be paranoid as we can arrive here with only partial | |
1088 | * state retrieved from the hardware during setup. | |
1089 | * | |
241bfc38 | 1090 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
1091 | * as Haswell has gained clock readout/fastboot support. |
1092 | * | |
66e514c1 | 1093 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 1094 | * properly reconstruct framebuffers. |
c3d1f436 MR |
1095 | * |
1096 | * FIXME: The intel_crtc->active here should be switched to | |
1097 | * crtc->state->active once we have proper CRTC states wired up | |
1098 | * for atomic. | |
20ddf665 | 1099 | */ |
c3d1f436 | 1100 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 1101 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
1102 | } |
1103 | ||
a5c961d1 PZ |
1104 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1105 | enum pipe pipe) | |
1106 | { | |
1107 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1108 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1109 | ||
6e3c9717 | 1110 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1111 | } |
1112 | ||
fbf49ea2 VS |
1113 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
1114 | { | |
1115 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1116 | i915_reg_t reg = PIPEDSL(pipe); |
fbf49ea2 VS |
1117 | u32 line1, line2; |
1118 | u32 line_mask; | |
1119 | ||
1120 | if (IS_GEN2(dev)) | |
1121 | line_mask = DSL_LINEMASK_GEN2; | |
1122 | else | |
1123 | line_mask = DSL_LINEMASK_GEN3; | |
1124 | ||
1125 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 1126 | msleep(5); |
fbf49ea2 VS |
1127 | line2 = I915_READ(reg) & line_mask; |
1128 | ||
1129 | return line1 == line2; | |
1130 | } | |
1131 | ||
ab7ad7f6 KP |
1132 | /* |
1133 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1134 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1135 | * |
1136 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1137 | * spinning on the vblank interrupt status bit, since we won't actually | |
1138 | * see an interrupt when the pipe is disabled. | |
1139 | * | |
ab7ad7f6 KP |
1140 | * On Gen4 and above: |
1141 | * wait for the pipe register state bit to turn off | |
1142 | * | |
1143 | * Otherwise: | |
1144 | * wait for the display line value to settle (it usually | |
1145 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1146 | * |
9d0498a2 | 1147 | */ |
575f7ab7 | 1148 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1149 | { |
575f7ab7 | 1150 | struct drm_device *dev = crtc->base.dev; |
9d0498a2 | 1151 | struct drm_i915_private *dev_priv = dev->dev_private; |
6e3c9717 | 1152 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1153 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
1154 | |
1155 | if (INTEL_INFO(dev)->gen >= 4) { | |
f0f59a00 | 1156 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1157 | |
1158 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
1159 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1160 | 100)) | |
284637d9 | 1161 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1162 | } else { |
ab7ad7f6 | 1163 | /* Wait for the display line to settle */ |
fbf49ea2 | 1164 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1165 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1166 | } |
79e53945 JB |
1167 | } |
1168 | ||
b24e7179 | 1169 | /* Only for pre-ILK configs */ |
55607e8a DV |
1170 | void assert_pll(struct drm_i915_private *dev_priv, |
1171 | enum pipe pipe, bool state) | |
b24e7179 | 1172 | { |
b24e7179 JB |
1173 | u32 val; |
1174 | bool cur_state; | |
1175 | ||
649636ef | 1176 | val = I915_READ(DPLL(pipe)); |
b24e7179 | 1177 | cur_state = !!(val & DPLL_VCO_ENABLE); |
e2c719b7 | 1178 | I915_STATE_WARN(cur_state != state, |
b24e7179 | 1179 | "PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1180 | onoff(state), onoff(cur_state)); |
b24e7179 | 1181 | } |
b24e7179 | 1182 | |
23538ef1 | 1183 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
8563b1e8 | 1184 | void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) |
23538ef1 JN |
1185 | { |
1186 | u32 val; | |
1187 | bool cur_state; | |
1188 | ||
a580516d | 1189 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1190 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1191 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1192 | |
1193 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1194 | I915_STATE_WARN(cur_state != state, |
23538ef1 | 1195 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1196 | onoff(state), onoff(cur_state)); |
23538ef1 | 1197 | } |
23538ef1 | 1198 | |
040484af JB |
1199 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
1200 | enum pipe pipe, bool state) | |
1201 | { | |
040484af | 1202 | bool cur_state; |
ad80a810 PZ |
1203 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1204 | pipe); | |
040484af | 1205 | |
affa9354 PZ |
1206 | if (HAS_DDI(dev_priv->dev)) { |
1207 | /* DDI does not have a specific FDI_TX register */ | |
649636ef | 1208 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
ad80a810 | 1209 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 | 1210 | } else { |
649636ef | 1211 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
bf507ef7 ED |
1212 | cur_state = !!(val & FDI_TX_ENABLE); |
1213 | } | |
e2c719b7 | 1214 | I915_STATE_WARN(cur_state != state, |
040484af | 1215 | "FDI TX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1216 | onoff(state), onoff(cur_state)); |
040484af JB |
1217 | } |
1218 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1219 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1220 | ||
1221 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1222 | enum pipe pipe, bool state) | |
1223 | { | |
040484af JB |
1224 | u32 val; |
1225 | bool cur_state; | |
1226 | ||
649636ef | 1227 | val = I915_READ(FDI_RX_CTL(pipe)); |
d63fa0dc | 1228 | cur_state = !!(val & FDI_RX_ENABLE); |
e2c719b7 | 1229 | I915_STATE_WARN(cur_state != state, |
040484af | 1230 | "FDI RX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1231 | onoff(state), onoff(cur_state)); |
040484af JB |
1232 | } |
1233 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1234 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1235 | ||
1236 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1237 | enum pipe pipe) | |
1238 | { | |
040484af JB |
1239 | u32 val; |
1240 | ||
1241 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1242 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1243 | return; |
1244 | ||
bf507ef7 | 1245 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1246 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1247 | return; |
1248 | ||
649636ef | 1249 | val = I915_READ(FDI_TX_CTL(pipe)); |
e2c719b7 | 1250 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1251 | } |
1252 | ||
55607e8a DV |
1253 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1254 | enum pipe pipe, bool state) | |
040484af | 1255 | { |
040484af | 1256 | u32 val; |
55607e8a | 1257 | bool cur_state; |
040484af | 1258 | |
649636ef | 1259 | val = I915_READ(FDI_RX_CTL(pipe)); |
55607e8a | 1260 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1261 | I915_STATE_WARN(cur_state != state, |
55607e8a | 1262 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
87ad3212 | 1263 | onoff(state), onoff(cur_state)); |
040484af JB |
1264 | } |
1265 | ||
b680c37a DV |
1266 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1267 | enum pipe pipe) | |
ea0760cf | 1268 | { |
bedd4dba | 1269 | struct drm_device *dev = dev_priv->dev; |
f0f59a00 | 1270 | i915_reg_t pp_reg; |
ea0760cf JB |
1271 | u32 val; |
1272 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1273 | bool locked = true; |
ea0760cf | 1274 | |
bedd4dba JN |
1275 | if (WARN_ON(HAS_DDI(dev))) |
1276 | return; | |
1277 | ||
1278 | if (HAS_PCH_SPLIT(dev)) { | |
1279 | u32 port_sel; | |
1280 | ||
ea0760cf | 1281 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1282 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1283 | ||
1284 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1285 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1286 | panel_pipe = PIPE_B; | |
1287 | /* XXX: else fix for eDP */ | |
666a4537 | 1288 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
bedd4dba JN |
1289 | /* presumably write lock depends on pipe, not port select */ |
1290 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1291 | panel_pipe = pipe; | |
ea0760cf JB |
1292 | } else { |
1293 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1294 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1295 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1296 | } |
1297 | ||
1298 | val = I915_READ(pp_reg); | |
1299 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1300 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1301 | locked = false; |
1302 | ||
e2c719b7 | 1303 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1304 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1305 | pipe_name(pipe)); |
ea0760cf JB |
1306 | } |
1307 | ||
93ce0ba6 JN |
1308 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1309 | enum pipe pipe, bool state) | |
1310 | { | |
1311 | struct drm_device *dev = dev_priv->dev; | |
1312 | bool cur_state; | |
1313 | ||
d9d82081 | 1314 | if (IS_845G(dev) || IS_I865G(dev)) |
0b87c24e | 1315 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
d9d82081 | 1316 | else |
5efb3e28 | 1317 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1318 | |
e2c719b7 | 1319 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 | 1320 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1321 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
93ce0ba6 JN |
1322 | } |
1323 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1324 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1325 | ||
b840d907 JB |
1326 | void assert_pipe(struct drm_i915_private *dev_priv, |
1327 | enum pipe pipe, bool state) | |
b24e7179 | 1328 | { |
63d7bbe9 | 1329 | bool cur_state; |
702e7a56 PZ |
1330 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1331 | pipe); | |
4feed0eb | 1332 | enum intel_display_power_domain power_domain; |
b24e7179 | 1333 | |
b6b5d049 VS |
1334 | /* if we need the pipe quirk it must be always on */ |
1335 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1336 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1337 | state = true; |
1338 | ||
4feed0eb ID |
1339 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); |
1340 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
649636ef | 1341 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
69310161 | 1342 | cur_state = !!(val & PIPECONF_ENABLE); |
4feed0eb ID |
1343 | |
1344 | intel_display_power_put(dev_priv, power_domain); | |
1345 | } else { | |
1346 | cur_state = false; | |
69310161 PZ |
1347 | } |
1348 | ||
e2c719b7 | 1349 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1350 | "pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1351 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1352 | } |
1353 | ||
931872fc CW |
1354 | static void assert_plane(struct drm_i915_private *dev_priv, |
1355 | enum plane plane, bool state) | |
b24e7179 | 1356 | { |
b24e7179 | 1357 | u32 val; |
931872fc | 1358 | bool cur_state; |
b24e7179 | 1359 | |
649636ef | 1360 | val = I915_READ(DSPCNTR(plane)); |
931872fc | 1361 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1362 | I915_STATE_WARN(cur_state != state, |
931872fc | 1363 | "plane %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1364 | plane_name(plane), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1365 | } |
1366 | ||
931872fc CW |
1367 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1368 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1369 | ||
b24e7179 JB |
1370 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1371 | enum pipe pipe) | |
1372 | { | |
653e1026 | 1373 | struct drm_device *dev = dev_priv->dev; |
649636ef | 1374 | int i; |
b24e7179 | 1375 | |
653e1026 VS |
1376 | /* Primary planes are fixed to pipes on gen4+ */ |
1377 | if (INTEL_INFO(dev)->gen >= 4) { | |
649636ef | 1378 | u32 val = I915_READ(DSPCNTR(pipe)); |
e2c719b7 | 1379 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1380 | "plane %c assertion failure, should be disabled but not\n", |
1381 | plane_name(pipe)); | |
19ec1358 | 1382 | return; |
28c05794 | 1383 | } |
19ec1358 | 1384 | |
b24e7179 | 1385 | /* Need to check both planes against the pipe */ |
055e393f | 1386 | for_each_pipe(dev_priv, i) { |
649636ef VS |
1387 | u32 val = I915_READ(DSPCNTR(i)); |
1388 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
b24e7179 | 1389 | DISPPLANE_SEL_PIPE_SHIFT; |
e2c719b7 | 1390 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1391 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1392 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1393 | } |
1394 | } | |
1395 | ||
19332d7a JB |
1396 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1397 | enum pipe pipe) | |
1398 | { | |
20674eef | 1399 | struct drm_device *dev = dev_priv->dev; |
649636ef | 1400 | int sprite; |
19332d7a | 1401 | |
7feb8b88 | 1402 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1403 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1404 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1405 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1406 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1407 | sprite, pipe_name(pipe)); | |
1408 | } | |
666a4537 | 1409 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
3bdcfc0c | 1410 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1411 | u32 val = I915_READ(SPCNTR(pipe, sprite)); |
e2c719b7 | 1412 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1413 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1414 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1415 | } |
1416 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
649636ef | 1417 | u32 val = I915_READ(SPRCTL(pipe)); |
e2c719b7 | 1418 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1419 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1420 | plane_name(pipe), pipe_name(pipe)); |
1421 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
649636ef | 1422 | u32 val = I915_READ(DVSCNTR(pipe)); |
e2c719b7 | 1423 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1424 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1425 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1426 | } |
1427 | } | |
1428 | ||
08c71e5e VS |
1429 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1430 | { | |
e2c719b7 | 1431 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1432 | drm_crtc_vblank_put(crtc); |
1433 | } | |
1434 | ||
7abd4b35 ACO |
1435 | void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1436 | enum pipe pipe) | |
92f2584a | 1437 | { |
92f2584a JB |
1438 | u32 val; |
1439 | bool enabled; | |
1440 | ||
649636ef | 1441 | val = I915_READ(PCH_TRANSCONF(pipe)); |
92f2584a | 1442 | enabled = !!(val & TRANS_ENABLE); |
e2c719b7 | 1443 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1444 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1445 | pipe_name(pipe)); | |
92f2584a JB |
1446 | } |
1447 | ||
4e634389 KP |
1448 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1449 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1450 | { |
1451 | if ((val & DP_PORT_EN) == 0) | |
1452 | return false; | |
1453 | ||
1454 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
f0f59a00 | 1455 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
f0575e92 KP |
1456 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1457 | return false; | |
44f37d1f CML |
1458 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1459 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1460 | return false; | |
f0575e92 KP |
1461 | } else { |
1462 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1463 | return false; | |
1464 | } | |
1465 | return true; | |
1466 | } | |
1467 | ||
1519b995 KP |
1468 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1469 | enum pipe pipe, u32 val) | |
1470 | { | |
dc0fa718 | 1471 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1472 | return false; |
1473 | ||
1474 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1475 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1476 | return false; |
44f37d1f CML |
1477 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1478 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1479 | return false; | |
1519b995 | 1480 | } else { |
dc0fa718 | 1481 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1482 | return false; |
1483 | } | |
1484 | return true; | |
1485 | } | |
1486 | ||
1487 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1488 | enum pipe pipe, u32 val) | |
1489 | { | |
1490 | if ((val & LVDS_PORT_EN) == 0) | |
1491 | return false; | |
1492 | ||
1493 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1494 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1495 | return false; | |
1496 | } else { | |
1497 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1498 | return false; | |
1499 | } | |
1500 | return true; | |
1501 | } | |
1502 | ||
1503 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1504 | enum pipe pipe, u32 val) | |
1505 | { | |
1506 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1507 | return false; | |
1508 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1509 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1510 | return false; | |
1511 | } else { | |
1512 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1513 | return false; | |
1514 | } | |
1515 | return true; | |
1516 | } | |
1517 | ||
291906f1 | 1518 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
1519 | enum pipe pipe, i915_reg_t reg, |
1520 | u32 port_sel) | |
291906f1 | 1521 | { |
47a05eca | 1522 | u32 val = I915_READ(reg); |
e2c719b7 | 1523 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1524 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1525 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1526 | |
e2c719b7 | 1527 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1528 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1529 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1530 | } |
1531 | ||
1532 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
f0f59a00 | 1533 | enum pipe pipe, i915_reg_t reg) |
291906f1 | 1534 | { |
47a05eca | 1535 | u32 val = I915_READ(reg); |
e2c719b7 | 1536 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1537 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1538 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1539 | |
e2c719b7 | 1540 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1541 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1542 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1543 | } |
1544 | ||
1545 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1546 | enum pipe pipe) | |
1547 | { | |
291906f1 | 1548 | u32 val; |
291906f1 | 1549 | |
f0575e92 KP |
1550 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1551 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1552 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 | 1553 | |
649636ef | 1554 | val = I915_READ(PCH_ADPA); |
e2c719b7 | 1555 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1556 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1557 | pipe_name(pipe)); |
291906f1 | 1558 | |
649636ef | 1559 | val = I915_READ(PCH_LVDS); |
e2c719b7 | 1560 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1561 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1562 | pipe_name(pipe)); |
291906f1 | 1563 | |
e2debe91 PZ |
1564 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1565 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1566 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1567 | } |
1568 | ||
d288f65f | 1569 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1570 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1571 | { |
426115cf DV |
1572 | struct drm_device *dev = crtc->base.dev; |
1573 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1574 | i915_reg_t reg = DPLL(crtc->pipe); |
d288f65f | 1575 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
87442f73 | 1576 | |
426115cf | 1577 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 | 1578 | |
87442f73 | 1579 | /* PLL is protected by panel, make sure we can write it */ |
6a9e7363 | 1580 | if (IS_MOBILE(dev_priv->dev)) |
426115cf | 1581 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1582 | |
426115cf DV |
1583 | I915_WRITE(reg, dpll); |
1584 | POSTING_READ(reg); | |
1585 | udelay(150); | |
1586 | ||
1587 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1588 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1589 | ||
d288f65f | 1590 | I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); |
426115cf | 1591 | POSTING_READ(DPLL_MD(crtc->pipe)); |
87442f73 DV |
1592 | |
1593 | /* We do this three times for luck */ | |
426115cf | 1594 | I915_WRITE(reg, dpll); |
87442f73 DV |
1595 | POSTING_READ(reg); |
1596 | udelay(150); /* wait for warmup */ | |
426115cf | 1597 | I915_WRITE(reg, dpll); |
87442f73 DV |
1598 | POSTING_READ(reg); |
1599 | udelay(150); /* wait for warmup */ | |
426115cf | 1600 | I915_WRITE(reg, dpll); |
87442f73 DV |
1601 | POSTING_READ(reg); |
1602 | udelay(150); /* wait for warmup */ | |
1603 | } | |
1604 | ||
d288f65f | 1605 | static void chv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1606 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
1607 | { |
1608 | struct drm_device *dev = crtc->base.dev; | |
1609 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1610 | int pipe = crtc->pipe; | |
1611 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1612 | u32 tmp; |
1613 | ||
1614 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1615 | ||
a580516d | 1616 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1617 | |
1618 | /* Enable back the 10bit clock to display controller */ | |
1619 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1620 | tmp |= DPIO_DCLKP_EN; | |
1621 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1622 | ||
54433e91 VS |
1623 | mutex_unlock(&dev_priv->sb_lock); |
1624 | ||
9d556c99 CML |
1625 | /* |
1626 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1627 | */ | |
1628 | udelay(1); | |
1629 | ||
1630 | /* Enable PLL */ | |
d288f65f | 1631 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1632 | |
1633 | /* Check PLL is locked */ | |
a11b0703 | 1634 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1635 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1636 | ||
a11b0703 | 1637 | /* not sure when this should be written */ |
d288f65f | 1638 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
a11b0703 | 1639 | POSTING_READ(DPLL_MD(pipe)); |
9d556c99 CML |
1640 | } |
1641 | ||
1c4e0274 VS |
1642 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1643 | { | |
1644 | struct intel_crtc *crtc; | |
1645 | int count = 0; | |
1646 | ||
1647 | for_each_intel_crtc(dev, crtc) | |
3538b9df | 1648 | count += crtc->base.state->active && |
409ee761 | 1649 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
1c4e0274 VS |
1650 | |
1651 | return count; | |
1652 | } | |
1653 | ||
66e3d5c0 | 1654 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1655 | { |
66e3d5c0 DV |
1656 | struct drm_device *dev = crtc->base.dev; |
1657 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1658 | i915_reg_t reg = DPLL(crtc->pipe); |
6e3c9717 | 1659 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1660 | |
66e3d5c0 | 1661 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1662 | |
63d7bbe9 | 1663 | /* No really, not for ILK+ */ |
3d13ef2e | 1664 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1665 | |
1666 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1667 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1668 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1669 | |
1c4e0274 VS |
1670 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1671 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1672 | /* | |
1673 | * It appears to be important that we don't enable this | |
1674 | * for the current pipe before otherwise configuring the | |
1675 | * PLL. No idea how this should be handled if multiple | |
1676 | * DVO outputs are enabled simultaneosly. | |
1677 | */ | |
1678 | dpll |= DPLL_DVO_2X_MODE; | |
1679 | I915_WRITE(DPLL(!crtc->pipe), | |
1680 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1681 | } | |
66e3d5c0 | 1682 | |
c2b63374 VS |
1683 | /* |
1684 | * Apparently we need to have VGA mode enabled prior to changing | |
1685 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1686 | * dividers, even though the register value does change. | |
1687 | */ | |
1688 | I915_WRITE(reg, 0); | |
1689 | ||
8e7a65aa VS |
1690 | I915_WRITE(reg, dpll); |
1691 | ||
66e3d5c0 DV |
1692 | /* Wait for the clocks to stabilize. */ |
1693 | POSTING_READ(reg); | |
1694 | udelay(150); | |
1695 | ||
1696 | if (INTEL_INFO(dev)->gen >= 4) { | |
1697 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1698 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1699 | } else { |
1700 | /* The pixel multiplier can only be updated once the | |
1701 | * DPLL is enabled and the clocks are stable. | |
1702 | * | |
1703 | * So write it again. | |
1704 | */ | |
1705 | I915_WRITE(reg, dpll); | |
1706 | } | |
63d7bbe9 JB |
1707 | |
1708 | /* We do this three times for luck */ | |
66e3d5c0 | 1709 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1710 | POSTING_READ(reg); |
1711 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1712 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1713 | POSTING_READ(reg); |
1714 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1715 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1716 | POSTING_READ(reg); |
1717 | udelay(150); /* wait for warmup */ | |
1718 | } | |
1719 | ||
1720 | /** | |
50b44a44 | 1721 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1722 | * @dev_priv: i915 private structure |
1723 | * @pipe: pipe PLL to disable | |
1724 | * | |
1725 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1726 | * | |
1727 | * Note! This is for pre-ILK only. | |
1728 | */ | |
1c4e0274 | 1729 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1730 | { |
1c4e0274 VS |
1731 | struct drm_device *dev = crtc->base.dev; |
1732 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1733 | enum pipe pipe = crtc->pipe; | |
1734 | ||
1735 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1736 | if (IS_I830(dev) && | |
409ee761 | 1737 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
3538b9df | 1738 | !intel_num_dvo_pipes(dev)) { |
1c4e0274 VS |
1739 | I915_WRITE(DPLL(PIPE_B), |
1740 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1741 | I915_WRITE(DPLL(PIPE_A), | |
1742 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1743 | } | |
1744 | ||
b6b5d049 VS |
1745 | /* Don't disable pipe or pipe PLLs if needed */ |
1746 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1747 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1748 | return; |
1749 | ||
1750 | /* Make sure the pipe isn't still relying on us */ | |
1751 | assert_pipe_disabled(dev_priv, pipe); | |
1752 | ||
b8afb911 | 1753 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1754 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1755 | } |
1756 | ||
f6071166 JB |
1757 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1758 | { | |
b8afb911 | 1759 | u32 val; |
f6071166 JB |
1760 | |
1761 | /* Make sure the pipe isn't still relying on us */ | |
1762 | assert_pipe_disabled(dev_priv, pipe); | |
1763 | ||
e5cbfbfb ID |
1764 | /* |
1765 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1766 | * The latter is needed for VGA hotplug / manual detection. | |
1767 | */ | |
b8afb911 | 1768 | val = DPLL_VGA_MODE_DIS; |
f6071166 | 1769 | if (pipe == PIPE_B) |
60bfe44f | 1770 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV; |
f6071166 JB |
1771 | I915_WRITE(DPLL(pipe), val); |
1772 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1773 | |
1774 | } | |
1775 | ||
1776 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1777 | { | |
d752048d | 1778 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1779 | u32 val; |
1780 | ||
a11b0703 VS |
1781 | /* Make sure the pipe isn't still relying on us */ |
1782 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1783 | |
a11b0703 | 1784 | /* Set PLL en = 0 */ |
60bfe44f VS |
1785 | val = DPLL_SSC_REF_CLK_CHV | |
1786 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1787 | if (pipe != PIPE_A) |
1788 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1789 | I915_WRITE(DPLL(pipe), val); | |
1790 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1791 | |
a580516d | 1792 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1793 | |
1794 | /* Disable 10bit clock to display controller */ | |
1795 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1796 | val &= ~DPIO_DCLKP_EN; | |
1797 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1798 | ||
a580516d | 1799 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1800 | } |
1801 | ||
e4607fcf | 1802 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1803 | struct intel_digital_port *dport, |
1804 | unsigned int expected_mask) | |
89b667f8 JB |
1805 | { |
1806 | u32 port_mask; | |
f0f59a00 | 1807 | i915_reg_t dpll_reg; |
89b667f8 | 1808 | |
e4607fcf CML |
1809 | switch (dport->port) { |
1810 | case PORT_B: | |
89b667f8 | 1811 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1812 | dpll_reg = DPLL(0); |
e4607fcf CML |
1813 | break; |
1814 | case PORT_C: | |
89b667f8 | 1815 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1816 | dpll_reg = DPLL(0); |
9b6de0a1 | 1817 | expected_mask <<= 4; |
00fc31b7 CML |
1818 | break; |
1819 | case PORT_D: | |
1820 | port_mask = DPLL_PORTD_READY_MASK; | |
1821 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1822 | break; |
1823 | default: | |
1824 | BUG(); | |
1825 | } | |
89b667f8 | 1826 | |
9b6de0a1 VS |
1827 | if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000)) |
1828 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", | |
1829 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1830 | } |
1831 | ||
b8a4f404 PZ |
1832 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1833 | enum pipe pipe) | |
040484af | 1834 | { |
23670b32 | 1835 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1836 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1837 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
f0f59a00 VS |
1838 | i915_reg_t reg; |
1839 | uint32_t val, pipeconf_val; | |
040484af JB |
1840 | |
1841 | /* PCH only available on ILK+ */ | |
55522f37 | 1842 | BUG_ON(!HAS_PCH_SPLIT(dev)); |
040484af JB |
1843 | |
1844 | /* Make sure PCH DPLL is enabled */ | |
8106ddbd | 1845 | assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll); |
040484af JB |
1846 | |
1847 | /* FDI must be feeding us bits for PCH ports */ | |
1848 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1849 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1850 | ||
23670b32 DV |
1851 | if (HAS_PCH_CPT(dev)) { |
1852 | /* Workaround: Set the timing override bit before enabling the | |
1853 | * pch transcoder. */ | |
1854 | reg = TRANS_CHICKEN2(pipe); | |
1855 | val = I915_READ(reg); | |
1856 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1857 | I915_WRITE(reg, val); | |
59c859d6 | 1858 | } |
23670b32 | 1859 | |
ab9412ba | 1860 | reg = PCH_TRANSCONF(pipe); |
040484af | 1861 | val = I915_READ(reg); |
5f7f726d | 1862 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1863 | |
1864 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1865 | /* | |
c5de7c6f VS |
1866 | * Make the BPC in transcoder be consistent with |
1867 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1868 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1869 | */ |
dfd07d72 | 1870 | val &= ~PIPECONF_BPC_MASK; |
c5de7c6f VS |
1871 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI)) |
1872 | val |= PIPECONF_8BPC; | |
1873 | else | |
1874 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1875 | } |
5f7f726d PZ |
1876 | |
1877 | val &= ~TRANS_INTERLACE_MASK; | |
1878 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 | 1879 | if (HAS_PCH_IBX(dev_priv->dev) && |
409ee761 | 1880 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
1881 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1882 | else | |
1883 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1884 | else |
1885 | val |= TRANS_PROGRESSIVE; | |
1886 | ||
040484af JB |
1887 | I915_WRITE(reg, val | TRANS_ENABLE); |
1888 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 1889 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1890 | } |
1891 | ||
8fb033d7 | 1892 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1893 | enum transcoder cpu_transcoder) |
040484af | 1894 | { |
8fb033d7 | 1895 | u32 val, pipeconf_val; |
8fb033d7 PZ |
1896 | |
1897 | /* PCH only available on ILK+ */ | |
55522f37 | 1898 | BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev)); |
8fb033d7 | 1899 | |
8fb033d7 | 1900 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1901 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1902 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1903 | |
223a6fdf | 1904 | /* Workaround: set timing override bit. */ |
36c0d0cf | 1905 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1906 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1907 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 1908 | |
25f3ef11 | 1909 | val = TRANS_ENABLE; |
937bb610 | 1910 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1911 | |
9a76b1c6 PZ |
1912 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1913 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1914 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1915 | else |
1916 | val |= TRANS_PROGRESSIVE; | |
1917 | ||
ab9412ba DV |
1918 | I915_WRITE(LPT_TRANSCONF, val); |
1919 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 1920 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1921 | } |
1922 | ||
b8a4f404 PZ |
1923 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1924 | enum pipe pipe) | |
040484af | 1925 | { |
23670b32 | 1926 | struct drm_device *dev = dev_priv->dev; |
f0f59a00 VS |
1927 | i915_reg_t reg; |
1928 | uint32_t val; | |
040484af JB |
1929 | |
1930 | /* FDI relies on the transcoder */ | |
1931 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1932 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1933 | ||
291906f1 JB |
1934 | /* Ports must be off as well */ |
1935 | assert_pch_ports_disabled(dev_priv, pipe); | |
1936 | ||
ab9412ba | 1937 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1938 | val = I915_READ(reg); |
1939 | val &= ~TRANS_ENABLE; | |
1940 | I915_WRITE(reg, val); | |
1941 | /* wait for PCH transcoder off, transcoder state */ | |
1942 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 1943 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 | 1944 | |
c465613b | 1945 | if (HAS_PCH_CPT(dev)) { |
23670b32 DV |
1946 | /* Workaround: Clear the timing override chicken bit again. */ |
1947 | reg = TRANS_CHICKEN2(pipe); | |
1948 | val = I915_READ(reg); | |
1949 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1950 | I915_WRITE(reg, val); | |
1951 | } | |
040484af JB |
1952 | } |
1953 | ||
ab4d966c | 1954 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1955 | { |
8fb033d7 PZ |
1956 | u32 val; |
1957 | ||
ab9412ba | 1958 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1959 | val &= ~TRANS_ENABLE; |
ab9412ba | 1960 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1961 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 1962 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 1963 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1964 | |
1965 | /* Workaround: clear timing override bit. */ | |
36c0d0cf | 1966 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1967 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1968 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
1969 | } |
1970 | ||
b24e7179 | 1971 | /** |
309cfea8 | 1972 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 1973 | * @crtc: crtc responsible for the pipe |
b24e7179 | 1974 | * |
0372264a | 1975 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 1976 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 1977 | */ |
e1fdc473 | 1978 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1979 | { |
0372264a PZ |
1980 | struct drm_device *dev = crtc->base.dev; |
1981 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1982 | enum pipe pipe = crtc->pipe; | |
1a70a728 | 1983 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
1a240d4d | 1984 | enum pipe pch_transcoder; |
f0f59a00 | 1985 | i915_reg_t reg; |
b24e7179 JB |
1986 | u32 val; |
1987 | ||
9e2ee2dd VS |
1988 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
1989 | ||
58c6eaa2 | 1990 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 1991 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
1992 | assert_sprites_disabled(dev_priv, pipe); |
1993 | ||
681e5811 | 1994 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
1995 | pch_transcoder = TRANSCODER_A; |
1996 | else | |
1997 | pch_transcoder = pipe; | |
1998 | ||
b24e7179 JB |
1999 | /* |
2000 | * A pipe without a PLL won't actually be able to drive bits from | |
2001 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
2002 | * need the check. | |
2003 | */ | |
50360403 | 2004 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) |
a65347ba | 2005 | if (crtc->config->has_dsi_encoder) |
23538ef1 JN |
2006 | assert_dsi_pll_enabled(dev_priv); |
2007 | else | |
2008 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2009 | else { |
6e3c9717 | 2010 | if (crtc->config->has_pch_encoder) { |
040484af | 2011 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2012 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2013 | assert_fdi_tx_pll_enabled(dev_priv, |
2014 | (enum pipe) cpu_transcoder); | |
040484af JB |
2015 | } |
2016 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2017 | } | |
b24e7179 | 2018 | |
702e7a56 | 2019 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2020 | val = I915_READ(reg); |
7ad25d48 | 2021 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
2022 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
2023 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 2024 | return; |
7ad25d48 | 2025 | } |
00d70b15 CW |
2026 | |
2027 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2028 | POSTING_READ(reg); |
b7792d8b VS |
2029 | |
2030 | /* | |
2031 | * Until the pipe starts DSL will read as 0, which would cause | |
2032 | * an apparent vblank timestamp jump, which messes up also the | |
2033 | * frame count when it's derived from the timestamps. So let's | |
2034 | * wait for the pipe to start properly before we call | |
2035 | * drm_crtc_vblank_on() | |
2036 | */ | |
2037 | if (dev->max_vblank_count == 0 && | |
2038 | wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50)) | |
2039 | DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe)); | |
b24e7179 JB |
2040 | } |
2041 | ||
2042 | /** | |
309cfea8 | 2043 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2044 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2045 | * |
575f7ab7 VS |
2046 | * Disable the pipe of @crtc, making sure that various hardware |
2047 | * specific requirements are met, if applicable, e.g. plane | |
2048 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2049 | * |
2050 | * Will wait until the pipe has shut down before returning. | |
2051 | */ | |
575f7ab7 | 2052 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2053 | { |
575f7ab7 | 2054 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
6e3c9717 | 2055 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2056 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 2057 | i915_reg_t reg; |
b24e7179 JB |
2058 | u32 val; |
2059 | ||
9e2ee2dd VS |
2060 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
2061 | ||
b24e7179 JB |
2062 | /* |
2063 | * Make sure planes won't keep trying to pump pixels to us, | |
2064 | * or we might hang the display. | |
2065 | */ | |
2066 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2067 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2068 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2069 | |
702e7a56 | 2070 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2071 | val = I915_READ(reg); |
00d70b15 CW |
2072 | if ((val & PIPECONF_ENABLE) == 0) |
2073 | return; | |
2074 | ||
67adc644 VS |
2075 | /* |
2076 | * Double wide has implications for planes | |
2077 | * so best keep it disabled when not needed. | |
2078 | */ | |
6e3c9717 | 2079 | if (crtc->config->double_wide) |
67adc644 VS |
2080 | val &= ~PIPECONF_DOUBLE_WIDE; |
2081 | ||
2082 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2083 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2084 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2085 | val &= ~PIPECONF_ENABLE; |
2086 | ||
2087 | I915_WRITE(reg, val); | |
2088 | if ((val & PIPECONF_ENABLE) == 0) | |
2089 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2090 | } |
2091 | ||
693db184 CW |
2092 | static bool need_vtd_wa(struct drm_device *dev) |
2093 | { | |
2094 | #ifdef CONFIG_INTEL_IOMMU | |
2095 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2096 | return true; | |
2097 | #endif | |
2098 | return false; | |
2099 | } | |
2100 | ||
832be82f VS |
2101 | static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) |
2102 | { | |
2103 | return IS_GEN2(dev_priv) ? 2048 : 4096; | |
2104 | } | |
2105 | ||
27ba3910 VS |
2106 | static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv, |
2107 | uint64_t fb_modifier, unsigned int cpp) | |
7b49f948 VS |
2108 | { |
2109 | switch (fb_modifier) { | |
2110 | case DRM_FORMAT_MOD_NONE: | |
2111 | return cpp; | |
2112 | case I915_FORMAT_MOD_X_TILED: | |
2113 | if (IS_GEN2(dev_priv)) | |
2114 | return 128; | |
2115 | else | |
2116 | return 512; | |
2117 | case I915_FORMAT_MOD_Y_TILED: | |
2118 | if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) | |
2119 | return 128; | |
2120 | else | |
2121 | return 512; | |
2122 | case I915_FORMAT_MOD_Yf_TILED: | |
2123 | switch (cpp) { | |
2124 | case 1: | |
2125 | return 64; | |
2126 | case 2: | |
2127 | case 4: | |
2128 | return 128; | |
2129 | case 8: | |
2130 | case 16: | |
2131 | return 256; | |
2132 | default: | |
2133 | MISSING_CASE(cpp); | |
2134 | return cpp; | |
2135 | } | |
2136 | break; | |
2137 | default: | |
2138 | MISSING_CASE(fb_modifier); | |
2139 | return cpp; | |
2140 | } | |
2141 | } | |
2142 | ||
832be82f VS |
2143 | unsigned int intel_tile_height(const struct drm_i915_private *dev_priv, |
2144 | uint64_t fb_modifier, unsigned int cpp) | |
a57ce0b2 | 2145 | { |
832be82f VS |
2146 | if (fb_modifier == DRM_FORMAT_MOD_NONE) |
2147 | return 1; | |
2148 | else | |
2149 | return intel_tile_size(dev_priv) / | |
27ba3910 | 2150 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
6761dd31 TU |
2151 | } |
2152 | ||
8d0deca8 VS |
2153 | /* Return the tile dimensions in pixel units */ |
2154 | static void intel_tile_dims(const struct drm_i915_private *dev_priv, | |
2155 | unsigned int *tile_width, | |
2156 | unsigned int *tile_height, | |
2157 | uint64_t fb_modifier, | |
2158 | unsigned int cpp) | |
2159 | { | |
2160 | unsigned int tile_width_bytes = | |
2161 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); | |
2162 | ||
2163 | *tile_width = tile_width_bytes / cpp; | |
2164 | *tile_height = intel_tile_size(dev_priv) / tile_width_bytes; | |
2165 | } | |
2166 | ||
6761dd31 TU |
2167 | unsigned int |
2168 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
832be82f | 2169 | uint32_t pixel_format, uint64_t fb_modifier) |
6761dd31 | 2170 | { |
832be82f VS |
2171 | unsigned int cpp = drm_format_plane_cpp(pixel_format, 0); |
2172 | unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp); | |
2173 | ||
2174 | return ALIGN(height, tile_height); | |
a57ce0b2 JB |
2175 | } |
2176 | ||
1663b9d6 VS |
2177 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) |
2178 | { | |
2179 | unsigned int size = 0; | |
2180 | int i; | |
2181 | ||
2182 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) | |
2183 | size += rot_info->plane[i].width * rot_info->plane[i].height; | |
2184 | ||
2185 | return size; | |
2186 | } | |
2187 | ||
75c82a53 | 2188 | static void |
3465c580 VS |
2189 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, |
2190 | const struct drm_framebuffer *fb, | |
2191 | unsigned int rotation) | |
f64b98cd | 2192 | { |
2d7a215f VS |
2193 | if (intel_rotation_90_or_270(rotation)) { |
2194 | *view = i915_ggtt_view_rotated; | |
2195 | view->params.rotated = to_intel_framebuffer(fb)->rot_info; | |
2196 | } else { | |
2197 | *view = i915_ggtt_view_normal; | |
2198 | } | |
2199 | } | |
50470bb0 | 2200 | |
2d7a215f VS |
2201 | static void |
2202 | intel_fill_fb_info(struct drm_i915_private *dev_priv, | |
2203 | struct drm_framebuffer *fb) | |
2204 | { | |
2205 | struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info; | |
2206 | unsigned int tile_size, tile_width, tile_height, cpp; | |
50470bb0 | 2207 | |
d9b3288e VS |
2208 | tile_size = intel_tile_size(dev_priv); |
2209 | ||
2210 | cpp = drm_format_plane_cpp(fb->pixel_format, 0); | |
8d0deca8 VS |
2211 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2212 | fb->modifier[0], cpp); | |
d9b3288e | 2213 | |
1663b9d6 VS |
2214 | info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp); |
2215 | info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height); | |
84fe03f7 | 2216 | |
89e3e142 | 2217 | if (info->pixel_format == DRM_FORMAT_NV12) { |
832be82f | 2218 | cpp = drm_format_plane_cpp(fb->pixel_format, 1); |
8d0deca8 VS |
2219 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2220 | fb->modifier[1], cpp); | |
d9b3288e | 2221 | |
2d7a215f | 2222 | info->uv_offset = fb->offsets[1]; |
1663b9d6 VS |
2223 | info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp); |
2224 | info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height); | |
89e3e142 | 2225 | } |
f64b98cd TU |
2226 | } |
2227 | ||
603525d7 | 2228 | static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) |
4e9a86b6 VS |
2229 | { |
2230 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2231 | return 256 * 1024; | |
985b8bb4 | 2232 | else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || |
666a4537 | 2233 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
4e9a86b6 VS |
2234 | return 128 * 1024; |
2235 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2236 | return 4 * 1024; | |
2237 | else | |
44c5905e | 2238 | return 0; |
4e9a86b6 VS |
2239 | } |
2240 | ||
603525d7 VS |
2241 | static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv, |
2242 | uint64_t fb_modifier) | |
2243 | { | |
2244 | switch (fb_modifier) { | |
2245 | case DRM_FORMAT_MOD_NONE: | |
2246 | return intel_linear_alignment(dev_priv); | |
2247 | case I915_FORMAT_MOD_X_TILED: | |
2248 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2249 | return 256 * 1024; | |
2250 | return 0; | |
2251 | case I915_FORMAT_MOD_Y_TILED: | |
2252 | case I915_FORMAT_MOD_Yf_TILED: | |
2253 | return 1 * 1024 * 1024; | |
2254 | default: | |
2255 | MISSING_CASE(fb_modifier); | |
2256 | return 0; | |
2257 | } | |
2258 | } | |
2259 | ||
127bd2ac | 2260 | int |
3465c580 VS |
2261 | intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, |
2262 | unsigned int rotation) | |
6b95a207 | 2263 | { |
850c4cdc | 2264 | struct drm_device *dev = fb->dev; |
ce453d81 | 2265 | struct drm_i915_private *dev_priv = dev->dev_private; |
850c4cdc | 2266 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2267 | struct i915_ggtt_view view; |
6b95a207 KH |
2268 | u32 alignment; |
2269 | int ret; | |
2270 | ||
ebcdd39e MR |
2271 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2272 | ||
603525d7 | 2273 | alignment = intel_surf_alignment(dev_priv, fb->modifier[0]); |
6b95a207 | 2274 | |
3465c580 | 2275 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2276 | |
693db184 CW |
2277 | /* Note that the w/a also requires 64 PTE of padding following the |
2278 | * bo. We currently fill all unused PTE with the shadow page and so | |
2279 | * we should always have valid PTE following the scanout preventing | |
2280 | * the VT-d warning. | |
2281 | */ | |
2282 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2283 | alignment = 256 * 1024; | |
2284 | ||
d6dd6843 PZ |
2285 | /* |
2286 | * Global gtt pte registers are special registers which actually forward | |
2287 | * writes to a chunk of system memory. Which means that there is no risk | |
2288 | * that the register values disappear as soon as we call | |
2289 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2290 | * pin/unpin/fence and not more. | |
2291 | */ | |
2292 | intel_runtime_pm_get(dev_priv); | |
2293 | ||
7580d774 ML |
2294 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, |
2295 | &view); | |
48b956c5 | 2296 | if (ret) |
b26a6b35 | 2297 | goto err_pm; |
6b95a207 KH |
2298 | |
2299 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2300 | * fence, whereas 965+ only requires a fence if using | |
2301 | * framebuffer compression. For simplicity, we always install | |
2302 | * a fence as the cost is not that onerous. | |
2303 | */ | |
9807216f VK |
2304 | if (view.type == I915_GGTT_VIEW_NORMAL) { |
2305 | ret = i915_gem_object_get_fence(obj); | |
2306 | if (ret == -EDEADLK) { | |
2307 | /* | |
2308 | * -EDEADLK means there are no free fences | |
2309 | * no pending flips. | |
2310 | * | |
2311 | * This is propagated to atomic, but it uses | |
2312 | * -EDEADLK to force a locking recovery, so | |
2313 | * change the returned error to -EBUSY. | |
2314 | */ | |
2315 | ret = -EBUSY; | |
2316 | goto err_unpin; | |
2317 | } else if (ret) | |
2318 | goto err_unpin; | |
1690e1eb | 2319 | |
9807216f VK |
2320 | i915_gem_object_pin_fence(obj); |
2321 | } | |
6b95a207 | 2322 | |
d6dd6843 | 2323 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2324 | return 0; |
48b956c5 CW |
2325 | |
2326 | err_unpin: | |
f64b98cd | 2327 | i915_gem_object_unpin_from_display_plane(obj, &view); |
b26a6b35 | 2328 | err_pm: |
d6dd6843 | 2329 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2330 | return ret; |
6b95a207 KH |
2331 | } |
2332 | ||
3465c580 | 2333 | static void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) |
1690e1eb | 2334 | { |
82bc3b2d | 2335 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2336 | struct i915_ggtt_view view; |
82bc3b2d | 2337 | |
ebcdd39e MR |
2338 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2339 | ||
3465c580 | 2340 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2341 | |
9807216f VK |
2342 | if (view.type == I915_GGTT_VIEW_NORMAL) |
2343 | i915_gem_object_unpin_fence(obj); | |
2344 | ||
f64b98cd | 2345 | i915_gem_object_unpin_from_display_plane(obj, &view); |
1690e1eb CW |
2346 | } |
2347 | ||
29cf9491 VS |
2348 | /* |
2349 | * Adjust the tile offset by moving the difference into | |
2350 | * the x/y offsets. | |
2351 | * | |
2352 | * Input tile dimensions and pitch must already be | |
2353 | * rotated to match x and y, and in pixel units. | |
2354 | */ | |
2355 | static u32 intel_adjust_tile_offset(int *x, int *y, | |
2356 | unsigned int tile_width, | |
2357 | unsigned int tile_height, | |
2358 | unsigned int tile_size, | |
2359 | unsigned int pitch_tiles, | |
2360 | u32 old_offset, | |
2361 | u32 new_offset) | |
2362 | { | |
2363 | unsigned int tiles; | |
2364 | ||
2365 | WARN_ON(old_offset & (tile_size - 1)); | |
2366 | WARN_ON(new_offset & (tile_size - 1)); | |
2367 | WARN_ON(new_offset > old_offset); | |
2368 | ||
2369 | tiles = (old_offset - new_offset) / tile_size; | |
2370 | ||
2371 | *y += tiles / pitch_tiles * tile_height; | |
2372 | *x += tiles % pitch_tiles * tile_width; | |
2373 | ||
2374 | return new_offset; | |
2375 | } | |
2376 | ||
8d0deca8 VS |
2377 | /* |
2378 | * Computes the linear offset to the base tile and adjusts | |
2379 | * x, y. bytes per pixel is assumed to be a power-of-two. | |
2380 | * | |
2381 | * In the 90/270 rotated case, x and y are assumed | |
2382 | * to be already rotated to match the rotated GTT view, and | |
2383 | * pitch is the tile_height aligned framebuffer height. | |
2384 | */ | |
4f2d9934 VS |
2385 | u32 intel_compute_tile_offset(int *x, int *y, |
2386 | const struct drm_framebuffer *fb, int plane, | |
8d0deca8 VS |
2387 | unsigned int pitch, |
2388 | unsigned int rotation) | |
c2c75131 | 2389 | { |
4f2d9934 VS |
2390 | const struct drm_i915_private *dev_priv = to_i915(fb->dev); |
2391 | uint64_t fb_modifier = fb->modifier[plane]; | |
2392 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); | |
29cf9491 VS |
2393 | u32 offset, offset_aligned, alignment; |
2394 | ||
2395 | alignment = intel_surf_alignment(dev_priv, fb_modifier); | |
2396 | if (alignment) | |
2397 | alignment--; | |
2398 | ||
b5c65338 | 2399 | if (fb_modifier != DRM_FORMAT_MOD_NONE) { |
8d0deca8 VS |
2400 | unsigned int tile_size, tile_width, tile_height; |
2401 | unsigned int tile_rows, tiles, pitch_tiles; | |
c2c75131 | 2402 | |
d843310d | 2403 | tile_size = intel_tile_size(dev_priv); |
8d0deca8 VS |
2404 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2405 | fb_modifier, cpp); | |
2406 | ||
2407 | if (intel_rotation_90_or_270(rotation)) { | |
2408 | pitch_tiles = pitch / tile_height; | |
2409 | swap(tile_width, tile_height); | |
2410 | } else { | |
2411 | pitch_tiles = pitch / (tile_width * cpp); | |
2412 | } | |
d843310d VS |
2413 | |
2414 | tile_rows = *y / tile_height; | |
2415 | *y %= tile_height; | |
c2c75131 | 2416 | |
8d0deca8 VS |
2417 | tiles = *x / tile_width; |
2418 | *x %= tile_width; | |
bc752862 | 2419 | |
29cf9491 VS |
2420 | offset = (tile_rows * pitch_tiles + tiles) * tile_size; |
2421 | offset_aligned = offset & ~alignment; | |
bc752862 | 2422 | |
29cf9491 VS |
2423 | intel_adjust_tile_offset(x, y, tile_width, tile_height, |
2424 | tile_size, pitch_tiles, | |
2425 | offset, offset_aligned); | |
2426 | } else { | |
bc752862 | 2427 | offset = *y * pitch + *x * cpp; |
29cf9491 VS |
2428 | offset_aligned = offset & ~alignment; |
2429 | ||
4e9a86b6 VS |
2430 | *y = (offset & alignment) / pitch; |
2431 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
bc752862 | 2432 | } |
29cf9491 VS |
2433 | |
2434 | return offset_aligned; | |
c2c75131 DV |
2435 | } |
2436 | ||
b35d63fa | 2437 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2438 | { |
2439 | switch (format) { | |
2440 | case DISPPLANE_8BPP: | |
2441 | return DRM_FORMAT_C8; | |
2442 | case DISPPLANE_BGRX555: | |
2443 | return DRM_FORMAT_XRGB1555; | |
2444 | case DISPPLANE_BGRX565: | |
2445 | return DRM_FORMAT_RGB565; | |
2446 | default: | |
2447 | case DISPPLANE_BGRX888: | |
2448 | return DRM_FORMAT_XRGB8888; | |
2449 | case DISPPLANE_RGBX888: | |
2450 | return DRM_FORMAT_XBGR8888; | |
2451 | case DISPPLANE_BGRX101010: | |
2452 | return DRM_FORMAT_XRGB2101010; | |
2453 | case DISPPLANE_RGBX101010: | |
2454 | return DRM_FORMAT_XBGR2101010; | |
2455 | } | |
2456 | } | |
2457 | ||
bc8d7dff DL |
2458 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2459 | { | |
2460 | switch (format) { | |
2461 | case PLANE_CTL_FORMAT_RGB_565: | |
2462 | return DRM_FORMAT_RGB565; | |
2463 | default: | |
2464 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2465 | if (rgb_order) { | |
2466 | if (alpha) | |
2467 | return DRM_FORMAT_ABGR8888; | |
2468 | else | |
2469 | return DRM_FORMAT_XBGR8888; | |
2470 | } else { | |
2471 | if (alpha) | |
2472 | return DRM_FORMAT_ARGB8888; | |
2473 | else | |
2474 | return DRM_FORMAT_XRGB8888; | |
2475 | } | |
2476 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2477 | if (rgb_order) | |
2478 | return DRM_FORMAT_XBGR2101010; | |
2479 | else | |
2480 | return DRM_FORMAT_XRGB2101010; | |
2481 | } | |
2482 | } | |
2483 | ||
5724dbd1 | 2484 | static bool |
f6936e29 DV |
2485 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2486 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2487 | { |
2488 | struct drm_device *dev = crtc->base.dev; | |
3badb49f | 2489 | struct drm_i915_private *dev_priv = to_i915(dev); |
46f297fb JB |
2490 | struct drm_i915_gem_object *obj = NULL; |
2491 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2492 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2493 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2494 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2495 | PAGE_SIZE); | |
2496 | ||
2497 | size_aligned -= base_aligned; | |
46f297fb | 2498 | |
ff2652ea CW |
2499 | if (plane_config->size == 0) |
2500 | return false; | |
2501 | ||
3badb49f PZ |
2502 | /* If the FB is too big, just don't use it since fbdev is not very |
2503 | * important and we should probably use that space with FBC or other | |
2504 | * features. */ | |
62106b4f | 2505 | if (size_aligned * 2 > dev_priv->ggtt.stolen_usable_size) |
3badb49f PZ |
2506 | return false; |
2507 | ||
12c83d99 TU |
2508 | mutex_lock(&dev->struct_mutex); |
2509 | ||
f37b5c2b DV |
2510 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2511 | base_aligned, | |
2512 | base_aligned, | |
2513 | size_aligned); | |
12c83d99 TU |
2514 | if (!obj) { |
2515 | mutex_unlock(&dev->struct_mutex); | |
484b41dd | 2516 | return false; |
12c83d99 | 2517 | } |
46f297fb | 2518 | |
49af449b DL |
2519 | obj->tiling_mode = plane_config->tiling; |
2520 | if (obj->tiling_mode == I915_TILING_X) | |
6bf129df | 2521 | obj->stride = fb->pitches[0]; |
46f297fb | 2522 | |
6bf129df DL |
2523 | mode_cmd.pixel_format = fb->pixel_format; |
2524 | mode_cmd.width = fb->width; | |
2525 | mode_cmd.height = fb->height; | |
2526 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2527 | mode_cmd.modifier[0] = fb->modifier[0]; |
2528 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb | 2529 | |
6bf129df | 2530 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2531 | &mode_cmd, obj)) { |
46f297fb JB |
2532 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2533 | goto out_unref_obj; | |
2534 | } | |
12c83d99 | 2535 | |
46f297fb | 2536 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2537 | |
f6936e29 | 2538 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2539 | return true; |
46f297fb JB |
2540 | |
2541 | out_unref_obj: | |
2542 | drm_gem_object_unreference(&obj->base); | |
2543 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2544 | return false; |
2545 | } | |
2546 | ||
afd65eb4 MR |
2547 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2548 | static void | |
2549 | update_state_fb(struct drm_plane *plane) | |
2550 | { | |
2551 | if (plane->fb == plane->state->fb) | |
2552 | return; | |
2553 | ||
2554 | if (plane->state->fb) | |
2555 | drm_framebuffer_unreference(plane->state->fb); | |
2556 | plane->state->fb = plane->fb; | |
2557 | if (plane->state->fb) | |
2558 | drm_framebuffer_reference(plane->state->fb); | |
2559 | } | |
2560 | ||
5724dbd1 | 2561 | static void |
f6936e29 DV |
2562 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2563 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2564 | { |
2565 | struct drm_device *dev = intel_crtc->base.dev; | |
d9ceb816 | 2566 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd JB |
2567 | struct drm_crtc *c; |
2568 | struct intel_crtc *i; | |
2ff8fde1 | 2569 | struct drm_i915_gem_object *obj; |
88595ac9 | 2570 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2571 | struct drm_plane_state *plane_state = primary->state; |
200757f5 MR |
2572 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
2573 | struct intel_plane *intel_plane = to_intel_plane(primary); | |
0a8d8a86 MR |
2574 | struct intel_plane_state *intel_state = |
2575 | to_intel_plane_state(plane_state); | |
88595ac9 | 2576 | struct drm_framebuffer *fb; |
484b41dd | 2577 | |
2d14030b | 2578 | if (!plane_config->fb) |
484b41dd JB |
2579 | return; |
2580 | ||
f6936e29 | 2581 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2582 | fb = &plane_config->fb->base; |
2583 | goto valid_fb; | |
f55548b5 | 2584 | } |
484b41dd | 2585 | |
2d14030b | 2586 | kfree(plane_config->fb); |
484b41dd JB |
2587 | |
2588 | /* | |
2589 | * Failed to alloc the obj, check to see if we should share | |
2590 | * an fb with another CRTC instead | |
2591 | */ | |
70e1e0ec | 2592 | for_each_crtc(dev, c) { |
484b41dd JB |
2593 | i = to_intel_crtc(c); |
2594 | ||
2595 | if (c == &intel_crtc->base) | |
2596 | continue; | |
2597 | ||
2ff8fde1 MR |
2598 | if (!i->active) |
2599 | continue; | |
2600 | ||
88595ac9 DV |
2601 | fb = c->primary->fb; |
2602 | if (!fb) | |
484b41dd JB |
2603 | continue; |
2604 | ||
88595ac9 | 2605 | obj = intel_fb_obj(fb); |
2ff8fde1 | 2606 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
88595ac9 DV |
2607 | drm_framebuffer_reference(fb); |
2608 | goto valid_fb; | |
484b41dd JB |
2609 | } |
2610 | } | |
88595ac9 | 2611 | |
200757f5 MR |
2612 | /* |
2613 | * We've failed to reconstruct the BIOS FB. Current display state | |
2614 | * indicates that the primary plane is visible, but has a NULL FB, | |
2615 | * which will lead to problems later if we don't fix it up. The | |
2616 | * simplest solution is to just disable the primary plane now and | |
2617 | * pretend the BIOS never had it enabled. | |
2618 | */ | |
2619 | to_intel_plane_state(plane_state)->visible = false; | |
2620 | crtc_state->plane_mask &= ~(1 << drm_plane_index(primary)); | |
2622a081 | 2621 | intel_pre_disable_primary_noatomic(&intel_crtc->base); |
200757f5 MR |
2622 | intel_plane->disable_plane(primary, &intel_crtc->base); |
2623 | ||
88595ac9 DV |
2624 | return; |
2625 | ||
2626 | valid_fb: | |
f44e2659 VS |
2627 | plane_state->src_x = 0; |
2628 | plane_state->src_y = 0; | |
be5651f2 ML |
2629 | plane_state->src_w = fb->width << 16; |
2630 | plane_state->src_h = fb->height << 16; | |
2631 | ||
f44e2659 VS |
2632 | plane_state->crtc_x = 0; |
2633 | plane_state->crtc_y = 0; | |
be5651f2 ML |
2634 | plane_state->crtc_w = fb->width; |
2635 | plane_state->crtc_h = fb->height; | |
2636 | ||
0a8d8a86 MR |
2637 | intel_state->src.x1 = plane_state->src_x; |
2638 | intel_state->src.y1 = plane_state->src_y; | |
2639 | intel_state->src.x2 = plane_state->src_x + plane_state->src_w; | |
2640 | intel_state->src.y2 = plane_state->src_y + plane_state->src_h; | |
2641 | intel_state->dst.x1 = plane_state->crtc_x; | |
2642 | intel_state->dst.y1 = plane_state->crtc_y; | |
2643 | intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w; | |
2644 | intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h; | |
2645 | ||
88595ac9 DV |
2646 | obj = intel_fb_obj(fb); |
2647 | if (obj->tiling_mode != I915_TILING_NONE) | |
2648 | dev_priv->preserve_bios_swizzle = true; | |
2649 | ||
be5651f2 ML |
2650 | drm_framebuffer_reference(fb); |
2651 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2652 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
36750f28 | 2653 | intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); |
a9ff8714 | 2654 | obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit; |
46f297fb JB |
2655 | } |
2656 | ||
a8d201af ML |
2657 | static void i9xx_update_primary_plane(struct drm_plane *primary, |
2658 | const struct intel_crtc_state *crtc_state, | |
2659 | const struct intel_plane_state *plane_state) | |
81255565 | 2660 | { |
a8d201af | 2661 | struct drm_device *dev = primary->dev; |
81255565 | 2662 | struct drm_i915_private *dev_priv = dev->dev_private; |
a8d201af ML |
2663 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
2664 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2665 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
81255565 | 2666 | int plane = intel_crtc->plane; |
54ea9da8 | 2667 | u32 linear_offset; |
81255565 | 2668 | u32 dspcntr; |
f0f59a00 | 2669 | i915_reg_t reg = DSPCNTR(plane); |
8d0deca8 | 2670 | unsigned int rotation = plane_state->base.rotation; |
ac484963 | 2671 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
54ea9da8 VS |
2672 | int x = plane_state->src.x1 >> 16; |
2673 | int y = plane_state->src.y1 >> 16; | |
c9ba6fad | 2674 | |
f45651ba VS |
2675 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2676 | ||
fdd508a6 | 2677 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2678 | |
2679 | if (INTEL_INFO(dev)->gen < 4) { | |
2680 | if (intel_crtc->pipe == PIPE_B) | |
2681 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2682 | ||
2683 | /* pipesrc and dspsize control the size that is scaled from, | |
2684 | * which should always be the user's requested size. | |
2685 | */ | |
2686 | I915_WRITE(DSPSIZE(plane), | |
a8d201af ML |
2687 | ((crtc_state->pipe_src_h - 1) << 16) | |
2688 | (crtc_state->pipe_src_w - 1)); | |
f45651ba | 2689 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
2690 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2691 | I915_WRITE(PRIMSIZE(plane), | |
a8d201af ML |
2692 | ((crtc_state->pipe_src_h - 1) << 16) | |
2693 | (crtc_state->pipe_src_w - 1)); | |
c14b0485 VS |
2694 | I915_WRITE(PRIMPOS(plane), 0); |
2695 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2696 | } |
81255565 | 2697 | |
57779d06 VS |
2698 | switch (fb->pixel_format) { |
2699 | case DRM_FORMAT_C8: | |
81255565 JB |
2700 | dspcntr |= DISPPLANE_8BPP; |
2701 | break; | |
57779d06 | 2702 | case DRM_FORMAT_XRGB1555: |
57779d06 | 2703 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 2704 | break; |
57779d06 VS |
2705 | case DRM_FORMAT_RGB565: |
2706 | dspcntr |= DISPPLANE_BGRX565; | |
2707 | break; | |
2708 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
2709 | dspcntr |= DISPPLANE_BGRX888; |
2710 | break; | |
2711 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2712 | dspcntr |= DISPPLANE_RGBX888; |
2713 | break; | |
2714 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2715 | dspcntr |= DISPPLANE_BGRX101010; |
2716 | break; | |
2717 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2718 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
2719 | break; |
2720 | default: | |
baba133a | 2721 | BUG(); |
81255565 | 2722 | } |
57779d06 | 2723 | |
f45651ba VS |
2724 | if (INTEL_INFO(dev)->gen >= 4 && |
2725 | obj->tiling_mode != I915_TILING_NONE) | |
2726 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2727 | |
de1aa629 VS |
2728 | if (IS_G4X(dev)) |
2729 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2730 | ||
ac484963 | 2731 | linear_offset = y * fb->pitches[0] + x * cpp; |
81255565 | 2732 | |
c2c75131 DV |
2733 | if (INTEL_INFO(dev)->gen >= 4) { |
2734 | intel_crtc->dspaddr_offset = | |
4f2d9934 | 2735 | intel_compute_tile_offset(&x, &y, fb, 0, |
8d0deca8 | 2736 | fb->pitches[0], rotation); |
c2c75131 DV |
2737 | linear_offset -= intel_crtc->dspaddr_offset; |
2738 | } else { | |
e506a0c6 | 2739 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2740 | } |
e506a0c6 | 2741 | |
8d0deca8 | 2742 | if (rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2743 | dspcntr |= DISPPLANE_ROTATE_180; |
2744 | ||
a8d201af ML |
2745 | x += (crtc_state->pipe_src_w - 1); |
2746 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
2747 | |
2748 | /* Finding the last pixel of the last line of the display | |
2749 | data and adding to linear_offset*/ | |
2750 | linear_offset += | |
a8d201af | 2751 | (crtc_state->pipe_src_h - 1) * fb->pitches[0] + |
ac484963 | 2752 | (crtc_state->pipe_src_w - 1) * cpp; |
48404c1e SJ |
2753 | } |
2754 | ||
2db3366b PZ |
2755 | intel_crtc->adjusted_x = x; |
2756 | intel_crtc->adjusted_y = y; | |
2757 | ||
48404c1e SJ |
2758 | I915_WRITE(reg, dspcntr); |
2759 | ||
01f2c773 | 2760 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2761 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2762 | I915_WRITE(DSPSURF(plane), |
2763 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2764 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2765 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2766 | } else |
f343c5f6 | 2767 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2768 | POSTING_READ(reg); |
17638cd6 JB |
2769 | } |
2770 | ||
a8d201af ML |
2771 | static void i9xx_disable_primary_plane(struct drm_plane *primary, |
2772 | struct drm_crtc *crtc) | |
17638cd6 JB |
2773 | { |
2774 | struct drm_device *dev = crtc->dev; | |
2775 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2776 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
17638cd6 | 2777 | int plane = intel_crtc->plane; |
f45651ba | 2778 | |
a8d201af ML |
2779 | I915_WRITE(DSPCNTR(plane), 0); |
2780 | if (INTEL_INFO(dev_priv)->gen >= 4) | |
fdd508a6 | 2781 | I915_WRITE(DSPSURF(plane), 0); |
a8d201af ML |
2782 | else |
2783 | I915_WRITE(DSPADDR(plane), 0); | |
2784 | POSTING_READ(DSPCNTR(plane)); | |
2785 | } | |
c9ba6fad | 2786 | |
a8d201af ML |
2787 | static void ironlake_update_primary_plane(struct drm_plane *primary, |
2788 | const struct intel_crtc_state *crtc_state, | |
2789 | const struct intel_plane_state *plane_state) | |
2790 | { | |
2791 | struct drm_device *dev = primary->dev; | |
2792 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2793 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
2794 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2795 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
2796 | int plane = intel_crtc->plane; | |
54ea9da8 | 2797 | u32 linear_offset; |
a8d201af ML |
2798 | u32 dspcntr; |
2799 | i915_reg_t reg = DSPCNTR(plane); | |
8d0deca8 | 2800 | unsigned int rotation = plane_state->base.rotation; |
ac484963 | 2801 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
a8d201af ML |
2802 | int x = plane_state->src.x1 >> 16; |
2803 | int y = plane_state->src.y1 >> 16; | |
c9ba6fad | 2804 | |
f45651ba | 2805 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
fdd508a6 | 2806 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2807 | |
2808 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2809 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2810 | |
57779d06 VS |
2811 | switch (fb->pixel_format) { |
2812 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2813 | dspcntr |= DISPPLANE_8BPP; |
2814 | break; | |
57779d06 VS |
2815 | case DRM_FORMAT_RGB565: |
2816 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2817 | break; |
57779d06 | 2818 | case DRM_FORMAT_XRGB8888: |
57779d06 VS |
2819 | dspcntr |= DISPPLANE_BGRX888; |
2820 | break; | |
2821 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2822 | dspcntr |= DISPPLANE_RGBX888; |
2823 | break; | |
2824 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2825 | dspcntr |= DISPPLANE_BGRX101010; |
2826 | break; | |
2827 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2828 | dspcntr |= DISPPLANE_RGBX101010; |
17638cd6 JB |
2829 | break; |
2830 | default: | |
baba133a | 2831 | BUG(); |
17638cd6 JB |
2832 | } |
2833 | ||
2834 | if (obj->tiling_mode != I915_TILING_NONE) | |
2835 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2836 | |
f45651ba | 2837 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2838 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2839 | |
ac484963 | 2840 | linear_offset = y * fb->pitches[0] + x * cpp; |
c2c75131 | 2841 | intel_crtc->dspaddr_offset = |
4f2d9934 | 2842 | intel_compute_tile_offset(&x, &y, fb, 0, |
8d0deca8 | 2843 | fb->pitches[0], rotation); |
c2c75131 | 2844 | linear_offset -= intel_crtc->dspaddr_offset; |
8d0deca8 | 2845 | if (rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2846 | dspcntr |= DISPPLANE_ROTATE_180; |
2847 | ||
2848 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
a8d201af ML |
2849 | x += (crtc_state->pipe_src_w - 1); |
2850 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
2851 | |
2852 | /* Finding the last pixel of the last line of the display | |
2853 | data and adding to linear_offset*/ | |
2854 | linear_offset += | |
a8d201af | 2855 | (crtc_state->pipe_src_h - 1) * fb->pitches[0] + |
ac484963 | 2856 | (crtc_state->pipe_src_w - 1) * cpp; |
48404c1e SJ |
2857 | } |
2858 | } | |
2859 | ||
2db3366b PZ |
2860 | intel_crtc->adjusted_x = x; |
2861 | intel_crtc->adjusted_y = y; | |
2862 | ||
48404c1e | 2863 | I915_WRITE(reg, dspcntr); |
17638cd6 | 2864 | |
01f2c773 | 2865 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2866 | I915_WRITE(DSPSURF(plane), |
2867 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2868 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2869 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2870 | } else { | |
2871 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2872 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2873 | } | |
17638cd6 | 2874 | POSTING_READ(reg); |
17638cd6 JB |
2875 | } |
2876 | ||
7b49f948 VS |
2877 | u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv, |
2878 | uint64_t fb_modifier, uint32_t pixel_format) | |
b321803d | 2879 | { |
7b49f948 | 2880 | if (fb_modifier == DRM_FORMAT_MOD_NONE) { |
b321803d | 2881 | return 64; |
7b49f948 VS |
2882 | } else { |
2883 | int cpp = drm_format_plane_cpp(pixel_format, 0); | |
2884 | ||
27ba3910 | 2885 | return intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
b321803d DL |
2886 | } |
2887 | } | |
2888 | ||
44eb0cb9 MK |
2889 | u32 intel_plane_obj_offset(struct intel_plane *intel_plane, |
2890 | struct drm_i915_gem_object *obj, | |
2891 | unsigned int plane) | |
121920fa | 2892 | { |
ce7f1728 | 2893 | struct i915_ggtt_view view; |
dedf278c | 2894 | struct i915_vma *vma; |
44eb0cb9 | 2895 | u64 offset; |
121920fa | 2896 | |
e7941294 | 2897 | intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb, |
3465c580 | 2898 | intel_plane->base.state->rotation); |
121920fa | 2899 | |
ce7f1728 | 2900 | vma = i915_gem_obj_to_ggtt_view(obj, &view); |
dedf278c | 2901 | if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n", |
ce7f1728 | 2902 | view.type)) |
dedf278c TU |
2903 | return -1; |
2904 | ||
44eb0cb9 | 2905 | offset = vma->node.start; |
dedf278c TU |
2906 | |
2907 | if (plane == 1) { | |
7723f47d | 2908 | offset += vma->ggtt_view.params.rotated.uv_start_page * |
dedf278c TU |
2909 | PAGE_SIZE; |
2910 | } | |
2911 | ||
44eb0cb9 MK |
2912 | WARN_ON(upper_32_bits(offset)); |
2913 | ||
2914 | return lower_32_bits(offset); | |
121920fa TU |
2915 | } |
2916 | ||
e435d6e5 ML |
2917 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
2918 | { | |
2919 | struct drm_device *dev = intel_crtc->base.dev; | |
2920 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2921 | ||
2922 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
2923 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
2924 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
2925 | } |
2926 | ||
a1b2278e CK |
2927 | /* |
2928 | * This function detaches (aka. unbinds) unused scalers in hardware | |
2929 | */ | |
0583236e | 2930 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 2931 | { |
a1b2278e CK |
2932 | struct intel_crtc_scaler_state *scaler_state; |
2933 | int i; | |
2934 | ||
a1b2278e CK |
2935 | scaler_state = &intel_crtc->config->scaler_state; |
2936 | ||
2937 | /* loop through and disable scalers that aren't in use */ | |
2938 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
2939 | if (!scaler_state->scalers[i].in_use) |
2940 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
2941 | } |
2942 | } | |
2943 | ||
6156a456 | 2944 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 2945 | { |
6156a456 | 2946 | switch (pixel_format) { |
d161cf7a | 2947 | case DRM_FORMAT_C8: |
c34ce3d1 | 2948 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 2949 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 2950 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 2951 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 2952 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 2953 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 2954 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
2955 | /* |
2956 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
2957 | * to be already pre-multiplied. We need to add a knob (or a different | |
2958 | * DRM_FORMAT) for user-space to configure that. | |
2959 | */ | |
f75fb42a | 2960 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 2961 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 2962 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 2963 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 2964 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 2965 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 2966 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 2967 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 2968 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 2969 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 2970 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 2971 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 2972 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 2973 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 2974 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 2975 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 2976 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 2977 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 2978 | default: |
4249eeef | 2979 | MISSING_CASE(pixel_format); |
70d21f0e | 2980 | } |
8cfcba41 | 2981 | |
c34ce3d1 | 2982 | return 0; |
6156a456 | 2983 | } |
70d21f0e | 2984 | |
6156a456 CK |
2985 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
2986 | { | |
6156a456 | 2987 | switch (fb_modifier) { |
30af77c4 | 2988 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 2989 | break; |
30af77c4 | 2990 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 2991 | return PLANE_CTL_TILED_X; |
b321803d | 2992 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 2993 | return PLANE_CTL_TILED_Y; |
b321803d | 2994 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 2995 | return PLANE_CTL_TILED_YF; |
70d21f0e | 2996 | default: |
6156a456 | 2997 | MISSING_CASE(fb_modifier); |
70d21f0e | 2998 | } |
8cfcba41 | 2999 | |
c34ce3d1 | 3000 | return 0; |
6156a456 | 3001 | } |
70d21f0e | 3002 | |
6156a456 CK |
3003 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
3004 | { | |
3b7a5119 | 3005 | switch (rotation) { |
6156a456 CK |
3006 | case BIT(DRM_ROTATE_0): |
3007 | break; | |
1e8df167 SJ |
3008 | /* |
3009 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
3010 | * while i915 HW rotation is clockwise, thats why this swapping. | |
3011 | */ | |
3b7a5119 | 3012 | case BIT(DRM_ROTATE_90): |
1e8df167 | 3013 | return PLANE_CTL_ROTATE_270; |
3b7a5119 | 3014 | case BIT(DRM_ROTATE_180): |
c34ce3d1 | 3015 | return PLANE_CTL_ROTATE_180; |
3b7a5119 | 3016 | case BIT(DRM_ROTATE_270): |
1e8df167 | 3017 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
3018 | default: |
3019 | MISSING_CASE(rotation); | |
3020 | } | |
3021 | ||
c34ce3d1 | 3022 | return 0; |
6156a456 CK |
3023 | } |
3024 | ||
a8d201af ML |
3025 | static void skylake_update_primary_plane(struct drm_plane *plane, |
3026 | const struct intel_crtc_state *crtc_state, | |
3027 | const struct intel_plane_state *plane_state) | |
6156a456 | 3028 | { |
a8d201af | 3029 | struct drm_device *dev = plane->dev; |
6156a456 | 3030 | struct drm_i915_private *dev_priv = dev->dev_private; |
a8d201af ML |
3031 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
3032 | struct drm_framebuffer *fb = plane_state->base.fb; | |
3033 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
6156a456 CK |
3034 | int pipe = intel_crtc->pipe; |
3035 | u32 plane_ctl, stride_div, stride; | |
3036 | u32 tile_height, plane_offset, plane_size; | |
a8d201af | 3037 | unsigned int rotation = plane_state->base.rotation; |
6156a456 | 3038 | int x_offset, y_offset; |
44eb0cb9 | 3039 | u32 surf_addr; |
a8d201af ML |
3040 | int scaler_id = plane_state->scaler_id; |
3041 | int src_x = plane_state->src.x1 >> 16; | |
3042 | int src_y = plane_state->src.y1 >> 16; | |
3043 | int src_w = drm_rect_width(&plane_state->src) >> 16; | |
3044 | int src_h = drm_rect_height(&plane_state->src) >> 16; | |
3045 | int dst_x = plane_state->dst.x1; | |
3046 | int dst_y = plane_state->dst.y1; | |
3047 | int dst_w = drm_rect_width(&plane_state->dst); | |
3048 | int dst_h = drm_rect_height(&plane_state->dst); | |
70d21f0e | 3049 | |
6156a456 CK |
3050 | plane_ctl = PLANE_CTL_ENABLE | |
3051 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3052 | PLANE_CTL_PIPE_CSC_ENABLE; | |
3053 | ||
3054 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); | |
3055 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
3056 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
6156a456 CK |
3057 | plane_ctl |= skl_plane_ctl_rotation(rotation); |
3058 | ||
7b49f948 | 3059 | stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
b321803d | 3060 | fb->pixel_format); |
dedf278c | 3061 | surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0); |
3b7a5119 | 3062 | |
a42e5a23 PZ |
3063 | WARN_ON(drm_rect_width(&plane_state->src) == 0); |
3064 | ||
3b7a5119 | 3065 | if (intel_rotation_90_or_270(rotation)) { |
832be82f VS |
3066 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
3067 | ||
3b7a5119 | 3068 | /* stride = Surface height in tiles */ |
832be82f | 3069 | tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp); |
3b7a5119 | 3070 | stride = DIV_ROUND_UP(fb->height, tile_height); |
a8d201af ML |
3071 | x_offset = stride * tile_height - src_y - src_h; |
3072 | y_offset = src_x; | |
6156a456 | 3073 | plane_size = (src_w - 1) << 16 | (src_h - 1); |
3b7a5119 SJ |
3074 | } else { |
3075 | stride = fb->pitches[0] / stride_div; | |
a8d201af ML |
3076 | x_offset = src_x; |
3077 | y_offset = src_y; | |
6156a456 | 3078 | plane_size = (src_h - 1) << 16 | (src_w - 1); |
3b7a5119 SJ |
3079 | } |
3080 | plane_offset = y_offset << 16 | x_offset; | |
b321803d | 3081 | |
2db3366b PZ |
3082 | intel_crtc->adjusted_x = x_offset; |
3083 | intel_crtc->adjusted_y = y_offset; | |
3084 | ||
70d21f0e | 3085 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
3b7a5119 SJ |
3086 | I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); |
3087 | I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); | |
3088 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
6156a456 CK |
3089 | |
3090 | if (scaler_id >= 0) { | |
3091 | uint32_t ps_ctrl = 0; | |
3092 | ||
3093 | WARN_ON(!dst_w || !dst_h); | |
3094 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | | |
3095 | crtc_state->scaler_state.scalers[scaler_id].mode; | |
3096 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3097 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3098 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3099 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3100 | I915_WRITE(PLANE_POS(pipe, 0), 0); | |
3101 | } else { | |
3102 | I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); | |
3103 | } | |
3104 | ||
121920fa | 3105 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
70d21f0e DL |
3106 | |
3107 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3108 | } | |
3109 | ||
a8d201af ML |
3110 | static void skylake_disable_primary_plane(struct drm_plane *primary, |
3111 | struct drm_crtc *crtc) | |
17638cd6 JB |
3112 | { |
3113 | struct drm_device *dev = crtc->dev; | |
3114 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a8d201af | 3115 | int pipe = to_intel_crtc(crtc)->pipe; |
17638cd6 | 3116 | |
a8d201af ML |
3117 | I915_WRITE(PLANE_CTL(pipe, 0), 0); |
3118 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
3119 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3120 | } | |
29b9bde6 | 3121 | |
a8d201af ML |
3122 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3123 | static int | |
3124 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3125 | int x, int y, enum mode_set_atomic state) | |
3126 | { | |
3127 | /* Support for kgdboc is disabled, this needs a major rework. */ | |
3128 | DRM_ERROR("legacy panic handler not supported any more.\n"); | |
3129 | ||
3130 | return -ENODEV; | |
81255565 JB |
3131 | } |
3132 | ||
7514747d | 3133 | static void intel_complete_page_flips(struct drm_device *dev) |
96a02917 | 3134 | { |
96a02917 VS |
3135 | struct drm_crtc *crtc; |
3136 | ||
70e1e0ec | 3137 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3138 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3139 | enum plane plane = intel_crtc->plane; | |
3140 | ||
3141 | intel_prepare_page_flip(dev, plane); | |
3142 | intel_finish_page_flip_plane(dev, plane); | |
3143 | } | |
7514747d VS |
3144 | } |
3145 | ||
3146 | static void intel_update_primary_planes(struct drm_device *dev) | |
3147 | { | |
7514747d | 3148 | struct drm_crtc *crtc; |
96a02917 | 3149 | |
70e1e0ec | 3150 | for_each_crtc(dev, crtc) { |
11c22da6 ML |
3151 | struct intel_plane *plane = to_intel_plane(crtc->primary); |
3152 | struct intel_plane_state *plane_state; | |
96a02917 | 3153 | |
11c22da6 | 3154 | drm_modeset_lock_crtc(crtc, &plane->base); |
11c22da6 ML |
3155 | plane_state = to_intel_plane_state(plane->base.state); |
3156 | ||
a8d201af ML |
3157 | if (plane_state->visible) |
3158 | plane->update_plane(&plane->base, | |
3159 | to_intel_crtc_state(crtc->state), | |
3160 | plane_state); | |
11c22da6 ML |
3161 | |
3162 | drm_modeset_unlock_crtc(crtc); | |
96a02917 VS |
3163 | } |
3164 | } | |
3165 | ||
7514747d VS |
3166 | void intel_prepare_reset(struct drm_device *dev) |
3167 | { | |
3168 | /* no reset support for gen2 */ | |
3169 | if (IS_GEN2(dev)) | |
3170 | return; | |
3171 | ||
3172 | /* reset doesn't touch the display */ | |
3173 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
3174 | return; | |
3175 | ||
3176 | drm_modeset_lock_all(dev); | |
f98ce92f VS |
3177 | /* |
3178 | * Disabling the crtcs gracefully seems nicer. Also the | |
3179 | * g33 docs say we should at least disable all the planes. | |
3180 | */ | |
6b72d486 | 3181 | intel_display_suspend(dev); |
7514747d VS |
3182 | } |
3183 | ||
3184 | void intel_finish_reset(struct drm_device *dev) | |
3185 | { | |
3186 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3187 | ||
3188 | /* | |
3189 | * Flips in the rings will be nuked by the reset, | |
3190 | * so complete all pending flips so that user space | |
3191 | * will get its events and not get stuck. | |
3192 | */ | |
3193 | intel_complete_page_flips(dev); | |
3194 | ||
3195 | /* no reset support for gen2 */ | |
3196 | if (IS_GEN2(dev)) | |
3197 | return; | |
3198 | ||
3199 | /* reset doesn't touch the display */ | |
3200 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { | |
3201 | /* | |
3202 | * Flips in the rings have been nuked by the reset, | |
3203 | * so update the base address of all primary | |
3204 | * planes to the the last fb to make sure we're | |
3205 | * showing the correct fb after a reset. | |
11c22da6 ML |
3206 | * |
3207 | * FIXME: Atomic will make this obsolete since we won't schedule | |
3208 | * CS-based flips (which might get lost in gpu resets) any more. | |
7514747d VS |
3209 | */ |
3210 | intel_update_primary_planes(dev); | |
3211 | return; | |
3212 | } | |
3213 | ||
3214 | /* | |
3215 | * The display has been reset as well, | |
3216 | * so need a full re-initialization. | |
3217 | */ | |
3218 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3219 | intel_runtime_pm_enable_interrupts(dev_priv); | |
3220 | ||
3221 | intel_modeset_init_hw(dev); | |
3222 | ||
3223 | spin_lock_irq(&dev_priv->irq_lock); | |
3224 | if (dev_priv->display.hpd_irq_setup) | |
3225 | dev_priv->display.hpd_irq_setup(dev); | |
3226 | spin_unlock_irq(&dev_priv->irq_lock); | |
3227 | ||
043e9bda | 3228 | intel_display_resume(dev); |
7514747d VS |
3229 | |
3230 | intel_hpd_init(dev_priv); | |
3231 | ||
3232 | drm_modeset_unlock_all(dev); | |
3233 | } | |
3234 | ||
7d5e3799 CW |
3235 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3236 | { | |
3237 | struct drm_device *dev = crtc->dev; | |
3238 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3239 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7d5e3799 CW |
3240 | bool pending; |
3241 | ||
3242 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
3243 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
3244 | return false; | |
3245 | ||
5e2d7afc | 3246 | spin_lock_irq(&dev->event_lock); |
7d5e3799 | 3247 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
5e2d7afc | 3248 | spin_unlock_irq(&dev->event_lock); |
7d5e3799 CW |
3249 | |
3250 | return pending; | |
3251 | } | |
3252 | ||
bfd16b2a ML |
3253 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
3254 | struct intel_crtc_state *old_crtc_state) | |
e30e8f75 GP |
3255 | { |
3256 | struct drm_device *dev = crtc->base.dev; | |
3257 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bfd16b2a ML |
3258 | struct intel_crtc_state *pipe_config = |
3259 | to_intel_crtc_state(crtc->base.state); | |
e30e8f75 | 3260 | |
bfd16b2a ML |
3261 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
3262 | crtc->base.mode = crtc->base.state->mode; | |
3263 | ||
3264 | DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n", | |
3265 | old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h, | |
3266 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
e30e8f75 | 3267 | |
44522d85 | 3268 | if (HAS_DDI(dev)) |
8563b1e8 | 3269 | intel_color_set_csc(&crtc->base); |
44522d85 | 3270 | |
e30e8f75 GP |
3271 | /* |
3272 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3273 | * that in compute_mode_changes we check the native mode (not the pfit | |
3274 | * mode) to see if we can flip rather than do a full mode set. In the | |
3275 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3276 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3277 | * sized surface. | |
e30e8f75 GP |
3278 | */ |
3279 | ||
e30e8f75 | 3280 | I915_WRITE(PIPESRC(crtc->pipe), |
bfd16b2a ML |
3281 | ((pipe_config->pipe_src_w - 1) << 16) | |
3282 | (pipe_config->pipe_src_h - 1)); | |
3283 | ||
3284 | /* on skylake this is done by detaching scalers */ | |
3285 | if (INTEL_INFO(dev)->gen >= 9) { | |
3286 | skl_detach_scalers(crtc); | |
3287 | ||
3288 | if (pipe_config->pch_pfit.enabled) | |
3289 | skylake_pfit_enable(crtc); | |
3290 | } else if (HAS_PCH_SPLIT(dev)) { | |
3291 | if (pipe_config->pch_pfit.enabled) | |
3292 | ironlake_pfit_enable(crtc); | |
3293 | else if (old_crtc_state->pch_pfit.enabled) | |
3294 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3295 | } |
e30e8f75 GP |
3296 | } |
3297 | ||
5e84e1a4 ZW |
3298 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3299 | { | |
3300 | struct drm_device *dev = crtc->dev; | |
3301 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3302 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3303 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3304 | i915_reg_t reg; |
3305 | u32 temp; | |
5e84e1a4 ZW |
3306 | |
3307 | /* enable normal train */ | |
3308 | reg = FDI_TX_CTL(pipe); | |
3309 | temp = I915_READ(reg); | |
61e499bf | 3310 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3311 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3312 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3313 | } else { |
3314 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3315 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3316 | } |
5e84e1a4 ZW |
3317 | I915_WRITE(reg, temp); |
3318 | ||
3319 | reg = FDI_RX_CTL(pipe); | |
3320 | temp = I915_READ(reg); | |
3321 | if (HAS_PCH_CPT(dev)) { | |
3322 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3323 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3324 | } else { | |
3325 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3326 | temp |= FDI_LINK_TRAIN_NONE; | |
3327 | } | |
3328 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3329 | ||
3330 | /* wait one idle pattern time */ | |
3331 | POSTING_READ(reg); | |
3332 | udelay(1000); | |
357555c0 JB |
3333 | |
3334 | /* IVB wants error correction enabled */ | |
3335 | if (IS_IVYBRIDGE(dev)) | |
3336 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3337 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3338 | } |
3339 | ||
8db9d77b ZW |
3340 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3341 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3342 | { | |
3343 | struct drm_device *dev = crtc->dev; | |
3344 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3345 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3346 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3347 | i915_reg_t reg; |
3348 | u32 temp, tries; | |
8db9d77b | 3349 | |
1c8562f6 | 3350 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3351 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3352 | |
e1a44743 AJ |
3353 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3354 | for train result */ | |
5eddb70b CW |
3355 | reg = FDI_RX_IMR(pipe); |
3356 | temp = I915_READ(reg); | |
e1a44743 AJ |
3357 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3358 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3359 | I915_WRITE(reg, temp); |
3360 | I915_READ(reg); | |
e1a44743 AJ |
3361 | udelay(150); |
3362 | ||
8db9d77b | 3363 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3364 | reg = FDI_TX_CTL(pipe); |
3365 | temp = I915_READ(reg); | |
627eb5a3 | 3366 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3367 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3368 | temp &= ~FDI_LINK_TRAIN_NONE; |
3369 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3370 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3371 | |
5eddb70b CW |
3372 | reg = FDI_RX_CTL(pipe); |
3373 | temp = I915_READ(reg); | |
8db9d77b ZW |
3374 | temp &= ~FDI_LINK_TRAIN_NONE; |
3375 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3376 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3377 | ||
3378 | POSTING_READ(reg); | |
8db9d77b ZW |
3379 | udelay(150); |
3380 | ||
5b2adf89 | 3381 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3382 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3383 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3384 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3385 | |
5eddb70b | 3386 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3387 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3388 | temp = I915_READ(reg); |
8db9d77b ZW |
3389 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3390 | ||
3391 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3392 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3393 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3394 | break; |
3395 | } | |
8db9d77b | 3396 | } |
e1a44743 | 3397 | if (tries == 5) |
5eddb70b | 3398 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3399 | |
3400 | /* Train 2 */ | |
5eddb70b CW |
3401 | reg = FDI_TX_CTL(pipe); |
3402 | temp = I915_READ(reg); | |
8db9d77b ZW |
3403 | temp &= ~FDI_LINK_TRAIN_NONE; |
3404 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3405 | I915_WRITE(reg, temp); |
8db9d77b | 3406 | |
5eddb70b CW |
3407 | reg = FDI_RX_CTL(pipe); |
3408 | temp = I915_READ(reg); | |
8db9d77b ZW |
3409 | temp &= ~FDI_LINK_TRAIN_NONE; |
3410 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3411 | I915_WRITE(reg, temp); |
8db9d77b | 3412 | |
5eddb70b CW |
3413 | POSTING_READ(reg); |
3414 | udelay(150); | |
8db9d77b | 3415 | |
5eddb70b | 3416 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3417 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3418 | temp = I915_READ(reg); |
8db9d77b ZW |
3419 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3420 | ||
3421 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3422 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3423 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3424 | break; | |
3425 | } | |
8db9d77b | 3426 | } |
e1a44743 | 3427 | if (tries == 5) |
5eddb70b | 3428 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3429 | |
3430 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3431 | |
8db9d77b ZW |
3432 | } |
3433 | ||
0206e353 | 3434 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3435 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3436 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3437 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3438 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3439 | }; | |
3440 | ||
3441 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3442 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3443 | { | |
3444 | struct drm_device *dev = crtc->dev; | |
3445 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3446 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3447 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3448 | i915_reg_t reg; |
3449 | u32 temp, i, retry; | |
8db9d77b | 3450 | |
e1a44743 AJ |
3451 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3452 | for train result */ | |
5eddb70b CW |
3453 | reg = FDI_RX_IMR(pipe); |
3454 | temp = I915_READ(reg); | |
e1a44743 AJ |
3455 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3456 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3457 | I915_WRITE(reg, temp); |
3458 | ||
3459 | POSTING_READ(reg); | |
e1a44743 AJ |
3460 | udelay(150); |
3461 | ||
8db9d77b | 3462 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3463 | reg = FDI_TX_CTL(pipe); |
3464 | temp = I915_READ(reg); | |
627eb5a3 | 3465 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3466 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3467 | temp &= ~FDI_LINK_TRAIN_NONE; |
3468 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3469 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3470 | /* SNB-B */ | |
3471 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3472 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3473 | |
d74cf324 DV |
3474 | I915_WRITE(FDI_RX_MISC(pipe), |
3475 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3476 | ||
5eddb70b CW |
3477 | reg = FDI_RX_CTL(pipe); |
3478 | temp = I915_READ(reg); | |
8db9d77b ZW |
3479 | if (HAS_PCH_CPT(dev)) { |
3480 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3481 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3482 | } else { | |
3483 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3484 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3485 | } | |
5eddb70b CW |
3486 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3487 | ||
3488 | POSTING_READ(reg); | |
8db9d77b ZW |
3489 | udelay(150); |
3490 | ||
0206e353 | 3491 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3492 | reg = FDI_TX_CTL(pipe); |
3493 | temp = I915_READ(reg); | |
8db9d77b ZW |
3494 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3495 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3496 | I915_WRITE(reg, temp); |
3497 | ||
3498 | POSTING_READ(reg); | |
8db9d77b ZW |
3499 | udelay(500); |
3500 | ||
fa37d39e SP |
3501 | for (retry = 0; retry < 5; retry++) { |
3502 | reg = FDI_RX_IIR(pipe); | |
3503 | temp = I915_READ(reg); | |
3504 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3505 | if (temp & FDI_RX_BIT_LOCK) { | |
3506 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3507 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3508 | break; | |
3509 | } | |
3510 | udelay(50); | |
8db9d77b | 3511 | } |
fa37d39e SP |
3512 | if (retry < 5) |
3513 | break; | |
8db9d77b ZW |
3514 | } |
3515 | if (i == 4) | |
5eddb70b | 3516 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3517 | |
3518 | /* Train 2 */ | |
5eddb70b CW |
3519 | reg = FDI_TX_CTL(pipe); |
3520 | temp = I915_READ(reg); | |
8db9d77b ZW |
3521 | temp &= ~FDI_LINK_TRAIN_NONE; |
3522 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3523 | if (IS_GEN6(dev)) { | |
3524 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3525 | /* SNB-B */ | |
3526 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3527 | } | |
5eddb70b | 3528 | I915_WRITE(reg, temp); |
8db9d77b | 3529 | |
5eddb70b CW |
3530 | reg = FDI_RX_CTL(pipe); |
3531 | temp = I915_READ(reg); | |
8db9d77b ZW |
3532 | if (HAS_PCH_CPT(dev)) { |
3533 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3534 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3535 | } else { | |
3536 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3537 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3538 | } | |
5eddb70b CW |
3539 | I915_WRITE(reg, temp); |
3540 | ||
3541 | POSTING_READ(reg); | |
8db9d77b ZW |
3542 | udelay(150); |
3543 | ||
0206e353 | 3544 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3545 | reg = FDI_TX_CTL(pipe); |
3546 | temp = I915_READ(reg); | |
8db9d77b ZW |
3547 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3548 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3549 | I915_WRITE(reg, temp); |
3550 | ||
3551 | POSTING_READ(reg); | |
8db9d77b ZW |
3552 | udelay(500); |
3553 | ||
fa37d39e SP |
3554 | for (retry = 0; retry < 5; retry++) { |
3555 | reg = FDI_RX_IIR(pipe); | |
3556 | temp = I915_READ(reg); | |
3557 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3558 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3559 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3560 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3561 | break; | |
3562 | } | |
3563 | udelay(50); | |
8db9d77b | 3564 | } |
fa37d39e SP |
3565 | if (retry < 5) |
3566 | break; | |
8db9d77b ZW |
3567 | } |
3568 | if (i == 4) | |
5eddb70b | 3569 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3570 | |
3571 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3572 | } | |
3573 | ||
357555c0 JB |
3574 | /* Manual link training for Ivy Bridge A0 parts */ |
3575 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3576 | { | |
3577 | struct drm_device *dev = crtc->dev; | |
3578 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3579 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3580 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3581 | i915_reg_t reg; |
3582 | u32 temp, i, j; | |
357555c0 JB |
3583 | |
3584 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3585 | for train result */ | |
3586 | reg = FDI_RX_IMR(pipe); | |
3587 | temp = I915_READ(reg); | |
3588 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3589 | temp &= ~FDI_RX_BIT_LOCK; | |
3590 | I915_WRITE(reg, temp); | |
3591 | ||
3592 | POSTING_READ(reg); | |
3593 | udelay(150); | |
3594 | ||
01a415fd DV |
3595 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3596 | I915_READ(FDI_RX_IIR(pipe))); | |
3597 | ||
139ccd3f JB |
3598 | /* Try each vswing and preemphasis setting twice before moving on */ |
3599 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3600 | /* disable first in case we need to retry */ | |
3601 | reg = FDI_TX_CTL(pipe); | |
3602 | temp = I915_READ(reg); | |
3603 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3604 | temp &= ~FDI_TX_ENABLE; | |
3605 | I915_WRITE(reg, temp); | |
357555c0 | 3606 | |
139ccd3f JB |
3607 | reg = FDI_RX_CTL(pipe); |
3608 | temp = I915_READ(reg); | |
3609 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3610 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3611 | temp &= ~FDI_RX_ENABLE; | |
3612 | I915_WRITE(reg, temp); | |
357555c0 | 3613 | |
139ccd3f | 3614 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3615 | reg = FDI_TX_CTL(pipe); |
3616 | temp = I915_READ(reg); | |
139ccd3f | 3617 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3618 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 3619 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3620 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3621 | temp |= snb_b_fdi_train_param[j/2]; |
3622 | temp |= FDI_COMPOSITE_SYNC; | |
3623 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3624 | |
139ccd3f JB |
3625 | I915_WRITE(FDI_RX_MISC(pipe), |
3626 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3627 | |
139ccd3f | 3628 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3629 | temp = I915_READ(reg); |
139ccd3f JB |
3630 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3631 | temp |= FDI_COMPOSITE_SYNC; | |
3632 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3633 | |
139ccd3f JB |
3634 | POSTING_READ(reg); |
3635 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3636 | |
139ccd3f JB |
3637 | for (i = 0; i < 4; i++) { |
3638 | reg = FDI_RX_IIR(pipe); | |
3639 | temp = I915_READ(reg); | |
3640 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3641 | |
139ccd3f JB |
3642 | if (temp & FDI_RX_BIT_LOCK || |
3643 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3644 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3645 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3646 | i); | |
3647 | break; | |
3648 | } | |
3649 | udelay(1); /* should be 0.5us */ | |
3650 | } | |
3651 | if (i == 4) { | |
3652 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3653 | continue; | |
3654 | } | |
357555c0 | 3655 | |
139ccd3f | 3656 | /* Train 2 */ |
357555c0 JB |
3657 | reg = FDI_TX_CTL(pipe); |
3658 | temp = I915_READ(reg); | |
139ccd3f JB |
3659 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3660 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3661 | I915_WRITE(reg, temp); | |
3662 | ||
3663 | reg = FDI_RX_CTL(pipe); | |
3664 | temp = I915_READ(reg); | |
3665 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3666 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3667 | I915_WRITE(reg, temp); |
3668 | ||
3669 | POSTING_READ(reg); | |
139ccd3f | 3670 | udelay(2); /* should be 1.5us */ |
357555c0 | 3671 | |
139ccd3f JB |
3672 | for (i = 0; i < 4; i++) { |
3673 | reg = FDI_RX_IIR(pipe); | |
3674 | temp = I915_READ(reg); | |
3675 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3676 | |
139ccd3f JB |
3677 | if (temp & FDI_RX_SYMBOL_LOCK || |
3678 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3679 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3680 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3681 | i); | |
3682 | goto train_done; | |
3683 | } | |
3684 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3685 | } |
139ccd3f JB |
3686 | if (i == 4) |
3687 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3688 | } |
357555c0 | 3689 | |
139ccd3f | 3690 | train_done: |
357555c0 JB |
3691 | DRM_DEBUG_KMS("FDI train done.\n"); |
3692 | } | |
3693 | ||
88cefb6c | 3694 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3695 | { |
88cefb6c | 3696 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3697 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3698 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
3699 | i915_reg_t reg; |
3700 | u32 temp; | |
c64e311e | 3701 | |
c98e9dcf | 3702 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3703 | reg = FDI_RX_CTL(pipe); |
3704 | temp = I915_READ(reg); | |
627eb5a3 | 3705 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3706 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3707 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3708 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3709 | ||
3710 | POSTING_READ(reg); | |
c98e9dcf JB |
3711 | udelay(200); |
3712 | ||
3713 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3714 | temp = I915_READ(reg); |
3715 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3716 | ||
3717 | POSTING_READ(reg); | |
c98e9dcf JB |
3718 | udelay(200); |
3719 | ||
20749730 PZ |
3720 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3721 | reg = FDI_TX_CTL(pipe); | |
3722 | temp = I915_READ(reg); | |
3723 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3724 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3725 | |
20749730 PZ |
3726 | POSTING_READ(reg); |
3727 | udelay(100); | |
6be4a607 | 3728 | } |
0e23b99d JB |
3729 | } |
3730 | ||
88cefb6c DV |
3731 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3732 | { | |
3733 | struct drm_device *dev = intel_crtc->base.dev; | |
3734 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3735 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3736 | i915_reg_t reg; |
3737 | u32 temp; | |
88cefb6c DV |
3738 | |
3739 | /* Switch from PCDclk to Rawclk */ | |
3740 | reg = FDI_RX_CTL(pipe); | |
3741 | temp = I915_READ(reg); | |
3742 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3743 | ||
3744 | /* Disable CPU FDI TX PLL */ | |
3745 | reg = FDI_TX_CTL(pipe); | |
3746 | temp = I915_READ(reg); | |
3747 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3748 | ||
3749 | POSTING_READ(reg); | |
3750 | udelay(100); | |
3751 | ||
3752 | reg = FDI_RX_CTL(pipe); | |
3753 | temp = I915_READ(reg); | |
3754 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3755 | ||
3756 | /* Wait for the clocks to turn off. */ | |
3757 | POSTING_READ(reg); | |
3758 | udelay(100); | |
3759 | } | |
3760 | ||
0fc932b8 JB |
3761 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3762 | { | |
3763 | struct drm_device *dev = crtc->dev; | |
3764 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3765 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3766 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3767 | i915_reg_t reg; |
3768 | u32 temp; | |
0fc932b8 JB |
3769 | |
3770 | /* disable CPU FDI tx and PCH FDI rx */ | |
3771 | reg = FDI_TX_CTL(pipe); | |
3772 | temp = I915_READ(reg); | |
3773 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3774 | POSTING_READ(reg); | |
3775 | ||
3776 | reg = FDI_RX_CTL(pipe); | |
3777 | temp = I915_READ(reg); | |
3778 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3779 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3780 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3781 | ||
3782 | POSTING_READ(reg); | |
3783 | udelay(100); | |
3784 | ||
3785 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3786 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3787 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3788 | |
3789 | /* still set train pattern 1 */ | |
3790 | reg = FDI_TX_CTL(pipe); | |
3791 | temp = I915_READ(reg); | |
3792 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3793 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3794 | I915_WRITE(reg, temp); | |
3795 | ||
3796 | reg = FDI_RX_CTL(pipe); | |
3797 | temp = I915_READ(reg); | |
3798 | if (HAS_PCH_CPT(dev)) { | |
3799 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3800 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3801 | } else { | |
3802 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3803 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3804 | } | |
3805 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3806 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3807 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3808 | I915_WRITE(reg, temp); |
3809 | ||
3810 | POSTING_READ(reg); | |
3811 | udelay(100); | |
3812 | } | |
3813 | ||
5dce5b93 CW |
3814 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3815 | { | |
3816 | struct intel_crtc *crtc; | |
3817 | ||
3818 | /* Note that we don't need to be called with mode_config.lock here | |
3819 | * as our list of CRTC objects is static for the lifetime of the | |
3820 | * device and so cannot disappear as we iterate. Similarly, we can | |
3821 | * happily treat the predicates as racy, atomic checks as userspace | |
3822 | * cannot claim and pin a new fb without at least acquring the | |
3823 | * struct_mutex and so serialising with us. | |
3824 | */ | |
d3fcc808 | 3825 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3826 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3827 | continue; | |
3828 | ||
3829 | if (crtc->unpin_work) | |
3830 | intel_wait_for_vblank(dev, crtc->pipe); | |
3831 | ||
3832 | return true; | |
3833 | } | |
3834 | ||
3835 | return false; | |
3836 | } | |
3837 | ||
d6bbafa1 CW |
3838 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
3839 | { | |
3840 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
3841 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
3842 | ||
3843 | /* ensure that the unpin work is consistent wrt ->pending. */ | |
3844 | smp_rmb(); | |
3845 | intel_crtc->unpin_work = NULL; | |
3846 | ||
3847 | if (work->event) | |
3848 | drm_send_vblank_event(intel_crtc->base.dev, | |
3849 | intel_crtc->pipe, | |
3850 | work->event); | |
3851 | ||
3852 | drm_crtc_vblank_put(&intel_crtc->base); | |
3853 | ||
3854 | wake_up_all(&dev_priv->pending_flip_queue); | |
3855 | queue_work(dev_priv->wq, &work->work); | |
3856 | ||
3857 | trace_i915_flip_complete(intel_crtc->plane, | |
3858 | work->pending_flip_obj); | |
3859 | } | |
3860 | ||
5008e874 | 3861 | static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3862 | { |
0f91128d | 3863 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3864 | struct drm_i915_private *dev_priv = dev->dev_private; |
5008e874 | 3865 | long ret; |
e6c3a2a6 | 3866 | |
2c10d571 | 3867 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
5008e874 ML |
3868 | |
3869 | ret = wait_event_interruptible_timeout( | |
3870 | dev_priv->pending_flip_queue, | |
3871 | !intel_crtc_has_pending_flip(crtc), | |
3872 | 60*HZ); | |
3873 | ||
3874 | if (ret < 0) | |
3875 | return ret; | |
3876 | ||
3877 | if (ret == 0) { | |
9c787942 | 3878 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2c10d571 | 3879 | |
5e2d7afc | 3880 | spin_lock_irq(&dev->event_lock); |
9c787942 CW |
3881 | if (intel_crtc->unpin_work) { |
3882 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
3883 | page_flip_completed(intel_crtc); | |
3884 | } | |
5e2d7afc | 3885 | spin_unlock_irq(&dev->event_lock); |
9c787942 | 3886 | } |
5bb61643 | 3887 | |
5008e874 | 3888 | return 0; |
e6c3a2a6 CW |
3889 | } |
3890 | ||
060f02d8 VS |
3891 | static void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
3892 | { | |
3893 | u32 temp; | |
3894 | ||
3895 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3896 | ||
3897 | mutex_lock(&dev_priv->sb_lock); | |
3898 | ||
3899 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
3900 | temp |= SBI_SSCCTL_DISABLE; | |
3901 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
3902 | ||
3903 | mutex_unlock(&dev_priv->sb_lock); | |
3904 | } | |
3905 | ||
e615efe4 ED |
3906 | /* Program iCLKIP clock to the desired frequency */ |
3907 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3908 | { | |
64b46a06 | 3909 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
6e3c9717 | 3910 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
3911 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3912 | u32 temp; | |
3913 | ||
060f02d8 | 3914 | lpt_disable_iclkip(dev_priv); |
e615efe4 | 3915 | |
64b46a06 VS |
3916 | /* The iCLK virtual clock root frequency is in MHz, |
3917 | * but the adjusted_mode->crtc_clock in in KHz. To get the | |
3918 | * divisors, it is necessary to divide one by another, so we | |
3919 | * convert the virtual clock precision to KHz here for higher | |
3920 | * precision. | |
3921 | */ | |
3922 | for (auxdiv = 0; auxdiv < 2; auxdiv++) { | |
e615efe4 ED |
3923 | u32 iclk_virtual_root_freq = 172800 * 1000; |
3924 | u32 iclk_pi_range = 64; | |
64b46a06 | 3925 | u32 desired_divisor; |
e615efe4 | 3926 | |
64b46a06 VS |
3927 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, |
3928 | clock << auxdiv); | |
3929 | divsel = (desired_divisor / iclk_pi_range) - 2; | |
3930 | phaseinc = desired_divisor % iclk_pi_range; | |
e615efe4 | 3931 | |
64b46a06 VS |
3932 | /* |
3933 | * Near 20MHz is a corner case which is | |
3934 | * out of range for the 7-bit divisor | |
3935 | */ | |
3936 | if (divsel <= 0x7f) | |
3937 | break; | |
e615efe4 ED |
3938 | } |
3939 | ||
3940 | /* This should not happen with any sane values */ | |
3941 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3942 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3943 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3944 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3945 | ||
3946 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3947 | clock, |
e615efe4 ED |
3948 | auxdiv, |
3949 | divsel, | |
3950 | phasedir, | |
3951 | phaseinc); | |
3952 | ||
060f02d8 VS |
3953 | mutex_lock(&dev_priv->sb_lock); |
3954 | ||
e615efe4 | 3955 | /* Program SSCDIVINTPHASE6 */ |
988d6ee8 | 3956 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3957 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3958 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3959 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3960 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3961 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3962 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3963 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3964 | |
3965 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3966 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3967 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3968 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3969 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3970 | |
3971 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3972 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3973 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3974 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 | 3975 | |
060f02d8 VS |
3976 | mutex_unlock(&dev_priv->sb_lock); |
3977 | ||
e615efe4 ED |
3978 | /* Wait for initialization time */ |
3979 | udelay(24); | |
3980 | ||
3981 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
3982 | } | |
3983 | ||
8802e5b6 VS |
3984 | int lpt_get_iclkip(struct drm_i915_private *dev_priv) |
3985 | { | |
3986 | u32 divsel, phaseinc, auxdiv; | |
3987 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3988 | u32 iclk_pi_range = 64; | |
3989 | u32 desired_divisor; | |
3990 | u32 temp; | |
3991 | ||
3992 | if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) | |
3993 | return 0; | |
3994 | ||
3995 | mutex_lock(&dev_priv->sb_lock); | |
3996 | ||
3997 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
3998 | if (temp & SBI_SSCCTL_DISABLE) { | |
3999 | mutex_unlock(&dev_priv->sb_lock); | |
4000 | return 0; | |
4001 | } | |
4002 | ||
4003 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); | |
4004 | divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >> | |
4005 | SBI_SSCDIVINTPHASE_DIVSEL_SHIFT; | |
4006 | phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >> | |
4007 | SBI_SSCDIVINTPHASE_INCVAL_SHIFT; | |
4008 | ||
4009 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); | |
4010 | auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >> | |
4011 | SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT; | |
4012 | ||
4013 | mutex_unlock(&dev_priv->sb_lock); | |
4014 | ||
4015 | desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc; | |
4016 | ||
4017 | return DIV_ROUND_CLOSEST(iclk_virtual_root_freq, | |
4018 | desired_divisor << auxdiv); | |
4019 | } | |
4020 | ||
275f01b2 DV |
4021 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4022 | enum pipe pch_transcoder) | |
4023 | { | |
4024 | struct drm_device *dev = crtc->base.dev; | |
4025 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 4026 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4027 | |
4028 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4029 | I915_READ(HTOTAL(cpu_transcoder))); | |
4030 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4031 | I915_READ(HBLANK(cpu_transcoder))); | |
4032 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4033 | I915_READ(HSYNC(cpu_transcoder))); | |
4034 | ||
4035 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4036 | I915_READ(VTOTAL(cpu_transcoder))); | |
4037 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4038 | I915_READ(VBLANK(cpu_transcoder))); | |
4039 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4040 | I915_READ(VSYNC(cpu_transcoder))); | |
4041 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4042 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4043 | } | |
4044 | ||
003632d9 | 4045 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 DV |
4046 | { |
4047 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4048 | uint32_t temp; | |
4049 | ||
4050 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4051 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4052 | return; |
4053 | ||
4054 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4055 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4056 | ||
003632d9 ACO |
4057 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4058 | if (enable) | |
4059 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4060 | ||
4061 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4062 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4063 | POSTING_READ(SOUTH_CHICKEN1); | |
4064 | } | |
4065 | ||
4066 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4067 | { | |
4068 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4069 | |
4070 | switch (intel_crtc->pipe) { | |
4071 | case PIPE_A: | |
4072 | break; | |
4073 | case PIPE_B: | |
6e3c9717 | 4074 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4075 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4076 | else |
003632d9 | 4077 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4078 | |
4079 | break; | |
4080 | case PIPE_C: | |
003632d9 | 4081 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4082 | |
4083 | break; | |
4084 | default: | |
4085 | BUG(); | |
4086 | } | |
4087 | } | |
4088 | ||
c48b5305 VS |
4089 | /* Return which DP Port should be selected for Transcoder DP control */ |
4090 | static enum port | |
4091 | intel_trans_dp_port_sel(struct drm_crtc *crtc) | |
4092 | { | |
4093 | struct drm_device *dev = crtc->dev; | |
4094 | struct intel_encoder *encoder; | |
4095 | ||
4096 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
4097 | if (encoder->type == INTEL_OUTPUT_DISPLAYPORT || | |
4098 | encoder->type == INTEL_OUTPUT_EDP) | |
4099 | return enc_to_dig_port(&encoder->base)->port; | |
4100 | } | |
4101 | ||
4102 | return -1; | |
4103 | } | |
4104 | ||
f67a559d JB |
4105 | /* |
4106 | * Enable PCH resources required for PCH ports: | |
4107 | * - PCH PLLs | |
4108 | * - FDI training & RX/TX | |
4109 | * - update transcoder timings | |
4110 | * - DP transcoding bits | |
4111 | * - transcoder | |
4112 | */ | |
4113 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4114 | { |
4115 | struct drm_device *dev = crtc->dev; | |
4116 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4117 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4118 | int pipe = intel_crtc->pipe; | |
f0f59a00 | 4119 | u32 temp; |
2c07245f | 4120 | |
ab9412ba | 4121 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4122 | |
1fbc0d78 DV |
4123 | if (IS_IVYBRIDGE(dev)) |
4124 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
4125 | ||
cd986abb DV |
4126 | /* Write the TU size bits before fdi link training, so that error |
4127 | * detection works. */ | |
4128 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4129 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4130 | ||
3860b2ec VS |
4131 | /* |
4132 | * Sometimes spurious CPU pipe underruns happen during FDI | |
4133 | * training, at least with VGA+HDMI cloning. Suppress them. | |
4134 | */ | |
4135 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
4136 | ||
c98e9dcf | 4137 | /* For PCH output, training FDI link */ |
674cf967 | 4138 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4139 | |
3ad8a208 DV |
4140 | /* We need to program the right clock selection before writing the pixel |
4141 | * mutliplier into the DPLL. */ | |
303b81e0 | 4142 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 4143 | u32 sel; |
4b645f14 | 4144 | |
c98e9dcf | 4145 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4146 | temp |= TRANS_DPLL_ENABLE(pipe); |
4147 | sel = TRANS_DPLLB_SEL(pipe); | |
8106ddbd ACO |
4148 | if (intel_crtc->config->shared_dpll == |
4149 | intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B)) | |
ee7b9f93 JB |
4150 | temp |= sel; |
4151 | else | |
4152 | temp &= ~sel; | |
c98e9dcf | 4153 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4154 | } |
5eddb70b | 4155 | |
3ad8a208 DV |
4156 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4157 | * transcoder, and we actually should do this to not upset any PCH | |
4158 | * transcoder that already use the clock when we share it. | |
4159 | * | |
4160 | * Note that enable_shared_dpll tries to do the right thing, but | |
4161 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4162 | * the right LVDS enable sequence. */ | |
85b3894f | 4163 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4164 | |
d9b6cb56 JB |
4165 | /* set transcoder timing, panel must allow it */ |
4166 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4167 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4168 | |
303b81e0 | 4169 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4170 | |
3860b2ec VS |
4171 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4172 | ||
c98e9dcf | 4173 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e3c9717 | 4174 | if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { |
9c4edaee VS |
4175 | const struct drm_display_mode *adjusted_mode = |
4176 | &intel_crtc->config->base.adjusted_mode; | |
dfd07d72 | 4177 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
f0f59a00 | 4178 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
5eddb70b CW |
4179 | temp = I915_READ(reg); |
4180 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4181 | TRANS_DP_SYNC_MASK | |
4182 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4183 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4184 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf | 4185 | |
9c4edaee | 4186 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
5eddb70b | 4187 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
9c4edaee | 4188 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4189 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4190 | |
4191 | switch (intel_trans_dp_port_sel(crtc)) { | |
c48b5305 | 4192 | case PORT_B: |
5eddb70b | 4193 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 4194 | break; |
c48b5305 | 4195 | case PORT_C: |
5eddb70b | 4196 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf | 4197 | break; |
c48b5305 | 4198 | case PORT_D: |
5eddb70b | 4199 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4200 | break; |
4201 | default: | |
e95d41e1 | 4202 | BUG(); |
32f9d658 | 4203 | } |
2c07245f | 4204 | |
5eddb70b | 4205 | I915_WRITE(reg, temp); |
6be4a607 | 4206 | } |
b52eb4dc | 4207 | |
b8a4f404 | 4208 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4209 | } |
4210 | ||
1507e5bd PZ |
4211 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4212 | { | |
4213 | struct drm_device *dev = crtc->dev; | |
4214 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4215 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6e3c9717 | 4216 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4217 | |
ab9412ba | 4218 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4219 | |
8c52b5e8 | 4220 | lpt_program_iclkip(crtc); |
1507e5bd | 4221 | |
0540e488 | 4222 | /* Set transcoder timing. */ |
275f01b2 | 4223 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4224 | |
937bb610 | 4225 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4226 | } |
4227 | ||
a1520318 | 4228 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
4229 | { |
4230 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 4231 | i915_reg_t dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4232 | u32 temp; |
4233 | ||
4234 | temp = I915_READ(dslreg); | |
4235 | udelay(500); | |
4236 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4237 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4238 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4239 | } |
4240 | } | |
4241 | ||
86adf9d7 ML |
4242 | static int |
4243 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
4244 | unsigned scaler_user, int *scaler_id, unsigned int rotation, | |
4245 | int src_w, int src_h, int dst_w, int dst_h) | |
a1b2278e | 4246 | { |
86adf9d7 ML |
4247 | struct intel_crtc_scaler_state *scaler_state = |
4248 | &crtc_state->scaler_state; | |
4249 | struct intel_crtc *intel_crtc = | |
4250 | to_intel_crtc(crtc_state->base.crtc); | |
a1b2278e | 4251 | int need_scaling; |
6156a456 CK |
4252 | |
4253 | need_scaling = intel_rotation_90_or_270(rotation) ? | |
4254 | (src_h != dst_w || src_w != dst_h): | |
4255 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4256 | |
4257 | /* | |
4258 | * if plane is being disabled or scaler is no more required or force detach | |
4259 | * - free scaler binded to this plane/crtc | |
4260 | * - in order to do this, update crtc->scaler_usage | |
4261 | * | |
4262 | * Here scaler state in crtc_state is set free so that | |
4263 | * scaler can be assigned to other user. Actual register | |
4264 | * update to free the scaler is done in plane/panel-fit programming. | |
4265 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4266 | */ | |
86adf9d7 | 4267 | if (force_detach || !need_scaling) { |
a1b2278e | 4268 | if (*scaler_id >= 0) { |
86adf9d7 | 4269 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4270 | scaler_state->scalers[*scaler_id].in_use = 0; |
4271 | ||
86adf9d7 ML |
4272 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4273 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4274 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4275 | scaler_state->scaler_users); |
4276 | *scaler_id = -1; | |
4277 | } | |
4278 | return 0; | |
4279 | } | |
4280 | ||
4281 | /* range checks */ | |
4282 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4283 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4284 | ||
4285 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4286 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4287 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4288 | "size is out of scaler range\n", |
86adf9d7 | 4289 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4290 | return -EINVAL; |
4291 | } | |
4292 | ||
86adf9d7 ML |
4293 | /* mark this plane as a scaler user in crtc_state */ |
4294 | scaler_state->scaler_users |= (1 << scaler_user); | |
4295 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4296 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4297 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4298 | scaler_state->scaler_users); | |
4299 | ||
4300 | return 0; | |
4301 | } | |
4302 | ||
4303 | /** | |
4304 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4305 | * | |
4306 | * @state: crtc's scaler state | |
86adf9d7 ML |
4307 | * |
4308 | * Return | |
4309 | * 0 - scaler_usage updated successfully | |
4310 | * error - requested scaling cannot be supported or other error condition | |
4311 | */ | |
e435d6e5 | 4312 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 ML |
4313 | { |
4314 | struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); | |
7c5f93b0 | 4315 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
86adf9d7 ML |
4316 | |
4317 | DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n", | |
4318 | intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX); | |
4319 | ||
e435d6e5 | 4320 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
fa5a7970 | 4321 | &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0), |
86adf9d7 | 4322 | state->pipe_src_w, state->pipe_src_h, |
aad941d5 | 4323 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
86adf9d7 ML |
4324 | } |
4325 | ||
4326 | /** | |
4327 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4328 | * | |
4329 | * @state: crtc's scaler state | |
86adf9d7 ML |
4330 | * @plane_state: atomic plane state to update |
4331 | * | |
4332 | * Return | |
4333 | * 0 - scaler_usage updated successfully | |
4334 | * error - requested scaling cannot be supported or other error condition | |
4335 | */ | |
da20eabd ML |
4336 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4337 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4338 | { |
4339 | ||
4340 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
da20eabd ML |
4341 | struct intel_plane *intel_plane = |
4342 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4343 | struct drm_framebuffer *fb = plane_state->base.fb; |
4344 | int ret; | |
4345 | ||
4346 | bool force_detach = !fb || !plane_state->visible; | |
4347 | ||
4348 | DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n", | |
4349 | intel_plane->base.base.id, intel_crtc->pipe, | |
4350 | drm_plane_index(&intel_plane->base)); | |
4351 | ||
4352 | ret = skl_update_scaler(crtc_state, force_detach, | |
4353 | drm_plane_index(&intel_plane->base), | |
4354 | &plane_state->scaler_id, | |
4355 | plane_state->base.rotation, | |
4356 | drm_rect_width(&plane_state->src) >> 16, | |
4357 | drm_rect_height(&plane_state->src) >> 16, | |
4358 | drm_rect_width(&plane_state->dst), | |
4359 | drm_rect_height(&plane_state->dst)); | |
4360 | ||
4361 | if (ret || plane_state->scaler_id < 0) | |
4362 | return ret; | |
4363 | ||
a1b2278e | 4364 | /* check colorkey */ |
818ed961 | 4365 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
86adf9d7 | 4366 | DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed", |
818ed961 | 4367 | intel_plane->base.base.id); |
a1b2278e CK |
4368 | return -EINVAL; |
4369 | } | |
4370 | ||
4371 | /* Check src format */ | |
86adf9d7 ML |
4372 | switch (fb->pixel_format) { |
4373 | case DRM_FORMAT_RGB565: | |
4374 | case DRM_FORMAT_XBGR8888: | |
4375 | case DRM_FORMAT_XRGB8888: | |
4376 | case DRM_FORMAT_ABGR8888: | |
4377 | case DRM_FORMAT_ARGB8888: | |
4378 | case DRM_FORMAT_XRGB2101010: | |
4379 | case DRM_FORMAT_XBGR2101010: | |
4380 | case DRM_FORMAT_YUYV: | |
4381 | case DRM_FORMAT_YVYU: | |
4382 | case DRM_FORMAT_UYVY: | |
4383 | case DRM_FORMAT_VYUY: | |
4384 | break; | |
4385 | default: | |
4386 | DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n", | |
4387 | intel_plane->base.base.id, fb->base.id, fb->pixel_format); | |
4388 | return -EINVAL; | |
a1b2278e CK |
4389 | } |
4390 | ||
a1b2278e CK |
4391 | return 0; |
4392 | } | |
4393 | ||
e435d6e5 ML |
4394 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4395 | { | |
4396 | int i; | |
4397 | ||
4398 | for (i = 0; i < crtc->num_scalers; i++) | |
4399 | skl_detach_scaler(crtc, i); | |
4400 | } | |
4401 | ||
4402 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4403 | { |
4404 | struct drm_device *dev = crtc->base.dev; | |
4405 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4406 | int pipe = crtc->pipe; | |
a1b2278e CK |
4407 | struct intel_crtc_scaler_state *scaler_state = |
4408 | &crtc->config->scaler_state; | |
4409 | ||
4410 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4411 | ||
6e3c9717 | 4412 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4413 | int id; |
4414 | ||
4415 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4416 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4417 | return; | |
4418 | } | |
4419 | ||
4420 | id = scaler_state->scaler_id; | |
4421 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4422 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4423 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4424 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4425 | ||
4426 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4427 | } |
4428 | } | |
4429 | ||
b074cec8 JB |
4430 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4431 | { | |
4432 | struct drm_device *dev = crtc->base.dev; | |
4433 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4434 | int pipe = crtc->pipe; | |
4435 | ||
6e3c9717 | 4436 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4437 | /* Force use of hard-coded filter coefficients |
4438 | * as some pre-programmed values are broken, | |
4439 | * e.g. x201. | |
4440 | */ | |
4441 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4442 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4443 | PF_PIPE_SEL_IVB(pipe)); | |
4444 | else | |
4445 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4446 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4447 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4448 | } |
4449 | } | |
4450 | ||
20bc8673 | 4451 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4452 | { |
cea165c3 VS |
4453 | struct drm_device *dev = crtc->base.dev; |
4454 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 | 4455 | |
6e3c9717 | 4456 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4457 | return; |
4458 | ||
cea165c3 VS |
4459 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
4460 | intel_wait_for_vblank(dev, crtc->pipe); | |
4461 | ||
d77e4531 | 4462 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4463 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4464 | mutex_lock(&dev_priv->rps.hw_lock); |
4465 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4466 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4467 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4468 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4469 | * mailbox." Moreover, the mailbox may return a bogus state, |
4470 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4471 | */ |
4472 | } else { | |
4473 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4474 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4475 | * is essentially intel_wait_for_vblank. If we don't have this | |
4476 | * and don't wait for vblanks until the end of crtc_enable, then | |
4477 | * the HW state readout code will complain that the expected | |
4478 | * IPS_CTL value is not the one we read. */ | |
4479 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
4480 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
4481 | } | |
d77e4531 PZ |
4482 | } |
4483 | ||
20bc8673 | 4484 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4485 | { |
4486 | struct drm_device *dev = crtc->base.dev; | |
4487 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4488 | ||
6e3c9717 | 4489 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4490 | return; |
4491 | ||
4492 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4493 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4494 | mutex_lock(&dev_priv->rps.hw_lock); |
4495 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4496 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
4497 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
4498 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
4499 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 4500 | } else { |
2a114cc1 | 4501 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4502 | POSTING_READ(IPS_CTL); |
4503 | } | |
d77e4531 PZ |
4504 | |
4505 | /* We need to wait for a vblank before we can disable the plane. */ | |
4506 | intel_wait_for_vblank(dev, crtc->pipe); | |
4507 | } | |
4508 | ||
7cac945f | 4509 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4510 | { |
7cac945f | 4511 | if (intel_crtc->overlay) { |
d3eedb1a VS |
4512 | struct drm_device *dev = intel_crtc->base.dev; |
4513 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4514 | ||
4515 | mutex_lock(&dev->struct_mutex); | |
4516 | dev_priv->mm.interruptible = false; | |
4517 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4518 | dev_priv->mm.interruptible = true; | |
4519 | mutex_unlock(&dev->struct_mutex); | |
4520 | } | |
4521 | ||
4522 | /* Let userspace switch the overlay on again. In most cases userspace | |
4523 | * has to recompute where to put it anyway. | |
4524 | */ | |
4525 | } | |
4526 | ||
87d4300a ML |
4527 | /** |
4528 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4529 | * @crtc: the CRTC whose primary plane was just enabled | |
4530 | * | |
4531 | * Performs potentially sleeping operations that must be done after the primary | |
4532 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4533 | * called due to an explicit primary plane update, or due to an implicit | |
4534 | * re-enable that is caused when a sprite plane is updated to no longer | |
4535 | * completely hide the primary plane. | |
4536 | */ | |
4537 | static void | |
4538 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4539 | { |
4540 | struct drm_device *dev = crtc->dev; | |
87d4300a | 4541 | struct drm_i915_private *dev_priv = dev->dev_private; |
a5c4d7bc VS |
4542 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4543 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4544 | |
87d4300a ML |
4545 | /* |
4546 | * FIXME IPS should be fine as long as one plane is | |
4547 | * enabled, but in practice it seems to have problems | |
4548 | * when going from primary only to sprite only and vice | |
4549 | * versa. | |
4550 | */ | |
a5c4d7bc VS |
4551 | hsw_enable_ips(intel_crtc); |
4552 | ||
f99d7069 | 4553 | /* |
87d4300a ML |
4554 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4555 | * So don't enable underrun reporting before at least some planes | |
4556 | * are enabled. | |
4557 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4558 | * but leave the pipe running. | |
f99d7069 | 4559 | */ |
87d4300a ML |
4560 | if (IS_GEN2(dev)) |
4561 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4562 | ||
aca7b684 VS |
4563 | /* Underruns don't always raise interrupts, so check manually. */ |
4564 | intel_check_cpu_fifo_underruns(dev_priv); | |
4565 | intel_check_pch_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4566 | } |
4567 | ||
2622a081 | 4568 | /* FIXME move all this to pre_plane_update() with proper state tracking */ |
87d4300a ML |
4569 | static void |
4570 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4571 | { |
4572 | struct drm_device *dev = crtc->dev; | |
4573 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4574 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4575 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4576 | |
87d4300a ML |
4577 | /* |
4578 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4579 | * So diasble underrun reporting before all the planes get disabled. | |
4580 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4581 | * but leave the pipe running. | |
4582 | */ | |
4583 | if (IS_GEN2(dev)) | |
4584 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
a5c4d7bc | 4585 | |
2622a081 VS |
4586 | /* |
4587 | * FIXME IPS should be fine as long as one plane is | |
4588 | * enabled, but in practice it seems to have problems | |
4589 | * when going from primary only to sprite only and vice | |
4590 | * versa. | |
4591 | */ | |
4592 | hsw_disable_ips(intel_crtc); | |
4593 | } | |
4594 | ||
4595 | /* FIXME get rid of this and use pre_plane_update */ | |
4596 | static void | |
4597 | intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) | |
4598 | { | |
4599 | struct drm_device *dev = crtc->dev; | |
4600 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4601 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4602 | int pipe = intel_crtc->pipe; | |
4603 | ||
4604 | intel_pre_disable_primary(crtc); | |
4605 | ||
87d4300a ML |
4606 | /* |
4607 | * Vblank time updates from the shadow to live plane control register | |
4608 | * are blocked if the memory self-refresh mode is active at that | |
4609 | * moment. So to make sure the plane gets truly disabled, disable | |
4610 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4611 | * will be checked/applied by the HW only at the next frame start | |
4612 | * event which is after the vblank start event, so we need to have a | |
4613 | * wait-for-vblank between disabling the plane and the pipe. | |
4614 | */ | |
262cd2e1 | 4615 | if (HAS_GMCH_DISPLAY(dev)) { |
87d4300a | 4616 | intel_set_memory_cxsr(dev_priv, false); |
262cd2e1 VS |
4617 | dev_priv->wm.vlv.cxsr = false; |
4618 | intel_wait_for_vblank(dev, pipe); | |
4619 | } | |
87d4300a ML |
4620 | } |
4621 | ||
cd202f69 | 4622 | static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) |
ac21b225 | 4623 | { |
cd202f69 ML |
4624 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
4625 | struct drm_atomic_state *old_state = old_crtc_state->base.state; | |
92826fcd ML |
4626 | struct intel_crtc_state *pipe_config = |
4627 | to_intel_crtc_state(crtc->base.state); | |
ac21b225 | 4628 | struct drm_device *dev = crtc->base.dev; |
cd202f69 ML |
4629 | struct drm_plane *primary = crtc->base.primary; |
4630 | struct drm_plane_state *old_pri_state = | |
4631 | drm_atomic_get_existing_plane_state(old_state, primary); | |
ac21b225 | 4632 | |
cd202f69 | 4633 | intel_frontbuffer_flip(dev, pipe_config->fb_bits); |
ac21b225 | 4634 | |
ab1d3a0e | 4635 | crtc->wm.cxsr_allowed = true; |
852eb00d | 4636 | |
caed361d | 4637 | if (pipe_config->update_wm_post && pipe_config->base.active) |
f015c551 VS |
4638 | intel_update_watermarks(&crtc->base); |
4639 | ||
cd202f69 ML |
4640 | if (old_pri_state) { |
4641 | struct intel_plane_state *primary_state = | |
4642 | to_intel_plane_state(primary->state); | |
4643 | struct intel_plane_state *old_primary_state = | |
4644 | to_intel_plane_state(old_pri_state); | |
4645 | ||
31ae71fc ML |
4646 | intel_fbc_post_update(crtc); |
4647 | ||
cd202f69 ML |
4648 | if (primary_state->visible && |
4649 | (needs_modeset(&pipe_config->base) || | |
4650 | !old_primary_state->visible)) | |
4651 | intel_post_enable_primary(&crtc->base); | |
4652 | } | |
ac21b225 ML |
4653 | } |
4654 | ||
5c74cd73 | 4655 | static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state) |
ac21b225 | 4656 | { |
5c74cd73 | 4657 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
ac21b225 | 4658 | struct drm_device *dev = crtc->base.dev; |
eddfcbcd | 4659 | struct drm_i915_private *dev_priv = dev->dev_private; |
ab1d3a0e ML |
4660 | struct intel_crtc_state *pipe_config = |
4661 | to_intel_crtc_state(crtc->base.state); | |
5c74cd73 ML |
4662 | struct drm_atomic_state *old_state = old_crtc_state->base.state; |
4663 | struct drm_plane *primary = crtc->base.primary; | |
4664 | struct drm_plane_state *old_pri_state = | |
4665 | drm_atomic_get_existing_plane_state(old_state, primary); | |
4666 | bool modeset = needs_modeset(&pipe_config->base); | |
ac21b225 | 4667 | |
5c74cd73 ML |
4668 | if (old_pri_state) { |
4669 | struct intel_plane_state *primary_state = | |
4670 | to_intel_plane_state(primary->state); | |
4671 | struct intel_plane_state *old_primary_state = | |
4672 | to_intel_plane_state(old_pri_state); | |
4673 | ||
31ae71fc ML |
4674 | intel_fbc_pre_update(crtc); |
4675 | ||
5c74cd73 ML |
4676 | if (old_primary_state->visible && |
4677 | (modeset || !primary_state->visible)) | |
4678 | intel_pre_disable_primary(&crtc->base); | |
4679 | } | |
852eb00d | 4680 | |
ab1d3a0e | 4681 | if (pipe_config->disable_cxsr) { |
852eb00d | 4682 | crtc->wm.cxsr_allowed = false; |
2dfd178d | 4683 | |
2622a081 VS |
4684 | /* |
4685 | * Vblank time updates from the shadow to live plane control register | |
4686 | * are blocked if the memory self-refresh mode is active at that | |
4687 | * moment. So to make sure the plane gets truly disabled, disable | |
4688 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4689 | * will be checked/applied by the HW only at the next frame start | |
4690 | * event which is after the vblank start event, so we need to have a | |
4691 | * wait-for-vblank between disabling the plane and the pipe. | |
4692 | */ | |
4693 | if (old_crtc_state->base.active) { | |
2dfd178d | 4694 | intel_set_memory_cxsr(dev_priv, false); |
2622a081 VS |
4695 | dev_priv->wm.vlv.cxsr = false; |
4696 | intel_wait_for_vblank(dev, crtc->pipe); | |
4697 | } | |
852eb00d | 4698 | } |
92826fcd | 4699 | |
ed4a6a7c MR |
4700 | /* |
4701 | * IVB workaround: must disable low power watermarks for at least | |
4702 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
4703 | * when scaling is disabled. | |
4704 | * | |
4705 | * WaCxSRDisabledForSpriteScaling:ivb | |
4706 | */ | |
4707 | if (pipe_config->disable_lp_wm) { | |
4708 | ilk_disable_lp_wm(dev); | |
4709 | intel_wait_for_vblank(dev, crtc->pipe); | |
4710 | } | |
4711 | ||
4712 | /* | |
4713 | * If we're doing a modeset, we're done. No need to do any pre-vblank | |
4714 | * watermark programming here. | |
4715 | */ | |
4716 | if (needs_modeset(&pipe_config->base)) | |
4717 | return; | |
4718 | ||
4719 | /* | |
4720 | * For platforms that support atomic watermarks, program the | |
4721 | * 'intermediate' watermarks immediately. On pre-gen9 platforms, these | |
4722 | * will be the intermediate values that are safe for both pre- and | |
4723 | * post- vblank; when vblank happens, the 'active' values will be set | |
4724 | * to the final 'target' values and we'll do this again to get the | |
4725 | * optimal watermarks. For gen9+ platforms, the values we program here | |
4726 | * will be the final target values which will get automatically latched | |
4727 | * at vblank time; no further programming will be necessary. | |
4728 | * | |
4729 | * If a platform hasn't been transitioned to atomic watermarks yet, | |
4730 | * we'll continue to update watermarks the old way, if flags tell | |
4731 | * us to. | |
4732 | */ | |
4733 | if (dev_priv->display.initial_watermarks != NULL) | |
4734 | dev_priv->display.initial_watermarks(pipe_config); | |
caed361d | 4735 | else if (pipe_config->update_wm_pre) |
92826fcd | 4736 | intel_update_watermarks(&crtc->base); |
ac21b225 ML |
4737 | } |
4738 | ||
d032ffa0 | 4739 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
4740 | { |
4741 | struct drm_device *dev = crtc->dev; | |
4742 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 4743 | struct drm_plane *p; |
87d4300a ML |
4744 | int pipe = intel_crtc->pipe; |
4745 | ||
7cac945f | 4746 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 4747 | |
d032ffa0 ML |
4748 | drm_for_each_plane_mask(p, dev, plane_mask) |
4749 | to_intel_plane(p)->disable_plane(p, crtc); | |
f98551ae | 4750 | |
f99d7069 DV |
4751 | /* |
4752 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4753 | * to compute the mask of flip planes precisely. For the time being | |
4754 | * consider this a flip to a NULL plane. | |
4755 | */ | |
4756 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4757 | } |
4758 | ||
f67a559d JB |
4759 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4760 | { | |
4761 | struct drm_device *dev = crtc->dev; | |
4762 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4763 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4764 | struct intel_encoder *encoder; |
f67a559d | 4765 | int pipe = intel_crtc->pipe; |
f67a559d | 4766 | |
53d9f4e9 | 4767 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
4768 | return; |
4769 | ||
81b088ca VS |
4770 | if (intel_crtc->config->has_pch_encoder) |
4771 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
4772 | ||
6e3c9717 | 4773 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
4774 | intel_prepare_shared_dpll(intel_crtc); |
4775 | ||
6e3c9717 | 4776 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4777 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
4778 | |
4779 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 4780 | intel_set_pipe_src_size(intel_crtc); |
29407aab | 4781 | |
6e3c9717 | 4782 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 4783 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4784 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
4785 | } |
4786 | ||
4787 | ironlake_set_pipeconf(crtc); | |
4788 | ||
f67a559d | 4789 | intel_crtc->active = true; |
8664281b | 4790 | |
a72e4c9f | 4791 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
8664281b | 4792 | |
f6736a1a | 4793 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4794 | if (encoder->pre_enable) |
4795 | encoder->pre_enable(encoder); | |
f67a559d | 4796 | |
6e3c9717 | 4797 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
4798 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4799 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4800 | * enabling. */ | |
88cefb6c | 4801 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4802 | } else { |
4803 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4804 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4805 | } | |
f67a559d | 4806 | |
b074cec8 | 4807 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4808 | |
9c54c0dd JB |
4809 | /* |
4810 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4811 | * clocks enabled | |
4812 | */ | |
8563b1e8 | 4813 | intel_color_load_luts(crtc); |
9c54c0dd | 4814 | |
1d5bf5d9 ID |
4815 | if (dev_priv->display.initial_watermarks != NULL) |
4816 | dev_priv->display.initial_watermarks(intel_crtc->config); | |
e1fdc473 | 4817 | intel_enable_pipe(intel_crtc); |
f67a559d | 4818 | |
6e3c9717 | 4819 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 4820 | ironlake_pch_enable(crtc); |
c98e9dcf | 4821 | |
f9b61ff6 DV |
4822 | assert_vblank_disabled(crtc); |
4823 | drm_crtc_vblank_on(crtc); | |
4824 | ||
fa5c73b1 DV |
4825 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4826 | encoder->enable(encoder); | |
61b77ddd DV |
4827 | |
4828 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4829 | cpt_verify_modeset(dev, intel_crtc->pipe); |
37ca8d4c VS |
4830 | |
4831 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ | |
4832 | if (intel_crtc->config->has_pch_encoder) | |
4833 | intel_wait_for_vblank(dev, pipe); | |
4834 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
6be4a607 JB |
4835 | } |
4836 | ||
42db64ef PZ |
4837 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4838 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4839 | { | |
f5adf94e | 4840 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4841 | } |
4842 | ||
4f771f10 PZ |
4843 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4844 | { | |
4845 | struct drm_device *dev = crtc->dev; | |
4846 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4847 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4848 | struct intel_encoder *encoder; | |
99d736a2 | 4849 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4d1de975 | 4850 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
99d736a2 ML |
4851 | struct intel_crtc_state *pipe_config = |
4852 | to_intel_crtc_state(crtc->state); | |
4f771f10 | 4853 | |
53d9f4e9 | 4854 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
4855 | return; |
4856 | ||
81b088ca VS |
4857 | if (intel_crtc->config->has_pch_encoder) |
4858 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
4859 | false); | |
4860 | ||
8106ddbd | 4861 | if (intel_crtc->config->shared_dpll) |
df8ad70c DV |
4862 | intel_enable_shared_dpll(intel_crtc); |
4863 | ||
6e3c9717 | 4864 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4865 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 | 4866 | |
4d1de975 JN |
4867 | if (!intel_crtc->config->has_dsi_encoder) |
4868 | intel_set_pipe_timings(intel_crtc); | |
4869 | ||
bc58be60 | 4870 | intel_set_pipe_src_size(intel_crtc); |
229fca97 | 4871 | |
4d1de975 JN |
4872 | if (cpu_transcoder != TRANSCODER_EDP && |
4873 | !transcoder_is_dsi(cpu_transcoder)) { | |
4874 | I915_WRITE(PIPE_MULT(cpu_transcoder), | |
6e3c9717 | 4875 | intel_crtc->config->pixel_multiplier - 1); |
ebb69c95 CT |
4876 | } |
4877 | ||
6e3c9717 | 4878 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 4879 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4880 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
4881 | } |
4882 | ||
4d1de975 JN |
4883 | if (!intel_crtc->config->has_dsi_encoder) |
4884 | haswell_set_pipeconf(crtc); | |
4885 | ||
391bf048 | 4886 | haswell_set_pipemisc(crtc); |
229fca97 | 4887 | |
8563b1e8 | 4888 | intel_color_set_csc(crtc); |
229fca97 | 4889 | |
4f771f10 | 4890 | intel_crtc->active = true; |
8664281b | 4891 | |
6b698516 DV |
4892 | if (intel_crtc->config->has_pch_encoder) |
4893 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
4894 | else | |
4895 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4896 | ||
7d4aefd0 | 4897 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 PZ |
4898 | if (encoder->pre_enable) |
4899 | encoder->pre_enable(encoder); | |
7d4aefd0 | 4900 | } |
4f771f10 | 4901 | |
d2d65408 | 4902 | if (intel_crtc->config->has_pch_encoder) |
4fe9467d | 4903 | dev_priv->display.fdi_link_train(crtc); |
4fe9467d | 4904 | |
a65347ba | 4905 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 4906 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 4907 | |
1c132b44 | 4908 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 4909 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 4910 | else |
1c132b44 | 4911 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
4912 | |
4913 | /* | |
4914 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4915 | * clocks enabled | |
4916 | */ | |
8563b1e8 | 4917 | intel_color_load_luts(crtc); |
4f771f10 | 4918 | |
1f544388 | 4919 | intel_ddi_set_pipe_settings(crtc); |
a65347ba | 4920 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 4921 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 4922 | |
1d5bf5d9 ID |
4923 | if (dev_priv->display.initial_watermarks != NULL) |
4924 | dev_priv->display.initial_watermarks(pipe_config); | |
4925 | else | |
4926 | intel_update_watermarks(crtc); | |
4d1de975 JN |
4927 | |
4928 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ | |
4929 | if (!intel_crtc->config->has_dsi_encoder) | |
4930 | intel_enable_pipe(intel_crtc); | |
42db64ef | 4931 | |
6e3c9717 | 4932 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 4933 | lpt_pch_enable(crtc); |
4f771f10 | 4934 | |
a65347ba | 4935 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
4936 | intel_ddi_set_vc_payload_alloc(crtc, true); |
4937 | ||
f9b61ff6 DV |
4938 | assert_vblank_disabled(crtc); |
4939 | drm_crtc_vblank_on(crtc); | |
4940 | ||
8807e55b | 4941 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 4942 | encoder->enable(encoder); |
8807e55b JN |
4943 | intel_opregion_notify_encoder(encoder, true); |
4944 | } | |
4f771f10 | 4945 | |
6b698516 DV |
4946 | if (intel_crtc->config->has_pch_encoder) { |
4947 | intel_wait_for_vblank(dev, pipe); | |
4948 | intel_wait_for_vblank(dev, pipe); | |
4949 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
d2d65408 VS |
4950 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
4951 | true); | |
6b698516 | 4952 | } |
d2d65408 | 4953 | |
e4916946 PZ |
4954 | /* If we change the relative order between pipe/planes enabling, we need |
4955 | * to change the workaround. */ | |
99d736a2 ML |
4956 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
4957 | if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) { | |
4958 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
4959 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
4960 | } | |
4f771f10 PZ |
4961 | } |
4962 | ||
bfd16b2a | 4963 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
4964 | { |
4965 | struct drm_device *dev = crtc->base.dev; | |
4966 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4967 | int pipe = crtc->pipe; | |
4968 | ||
4969 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
4970 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 4971 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
4972 | I915_WRITE(PF_CTL(pipe), 0); |
4973 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
4974 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
4975 | } | |
4976 | } | |
4977 | ||
6be4a607 JB |
4978 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
4979 | { | |
4980 | struct drm_device *dev = crtc->dev; | |
4981 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4982 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4983 | struct intel_encoder *encoder; |
6be4a607 | 4984 | int pipe = intel_crtc->pipe; |
b52eb4dc | 4985 | |
37ca8d4c VS |
4986 | if (intel_crtc->config->has_pch_encoder) |
4987 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
4988 | ||
ea9d758d DV |
4989 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4990 | encoder->disable(encoder); | |
4991 | ||
f9b61ff6 DV |
4992 | drm_crtc_vblank_off(crtc); |
4993 | assert_vblank_disabled(crtc); | |
4994 | ||
3860b2ec VS |
4995 | /* |
4996 | * Sometimes spurious CPU pipe underruns happen when the | |
4997 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
4998 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
4999 | */ | |
5000 | if (intel_crtc->config->has_pch_encoder) | |
5001 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
5002 | ||
575f7ab7 | 5003 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5004 | |
bfd16b2a | 5005 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 5006 | |
3860b2ec | 5007 | if (intel_crtc->config->has_pch_encoder) { |
5a74f70a | 5008 | ironlake_fdi_disable(crtc); |
3860b2ec VS |
5009 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
5010 | } | |
5a74f70a | 5011 | |
bf49ec8c DV |
5012 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5013 | if (encoder->post_disable) | |
5014 | encoder->post_disable(encoder); | |
2c07245f | 5015 | |
6e3c9717 | 5016 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5017 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5018 | |
d925c59a | 5019 | if (HAS_PCH_CPT(dev)) { |
f0f59a00 VS |
5020 | i915_reg_t reg; |
5021 | u32 temp; | |
5022 | ||
d925c59a DV |
5023 | /* disable TRANS_DP_CTL */ |
5024 | reg = TRANS_DP_CTL(pipe); | |
5025 | temp = I915_READ(reg); | |
5026 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5027 | TRANS_DP_PORT_SEL_MASK); | |
5028 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5029 | I915_WRITE(reg, temp); | |
5030 | ||
5031 | /* disable DPLL_SEL */ | |
5032 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5033 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5034 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5035 | } |
e3421a18 | 5036 | |
d925c59a DV |
5037 | ironlake_fdi_pll_disable(intel_crtc); |
5038 | } | |
81b088ca VS |
5039 | |
5040 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
6be4a607 | 5041 | } |
1b3c7a47 | 5042 | |
4f771f10 | 5043 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 5044 | { |
4f771f10 PZ |
5045 | struct drm_device *dev = crtc->dev; |
5046 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 5047 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 5048 | struct intel_encoder *encoder; |
6e3c9717 | 5049 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5050 | |
d2d65408 VS |
5051 | if (intel_crtc->config->has_pch_encoder) |
5052 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5053 | false); | |
5054 | ||
8807e55b JN |
5055 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5056 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 5057 | encoder->disable(encoder); |
8807e55b | 5058 | } |
4f771f10 | 5059 | |
f9b61ff6 DV |
5060 | drm_crtc_vblank_off(crtc); |
5061 | assert_vblank_disabled(crtc); | |
5062 | ||
4d1de975 JN |
5063 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ |
5064 | if (!intel_crtc->config->has_dsi_encoder) | |
5065 | intel_disable_pipe(intel_crtc); | |
4f771f10 | 5066 | |
6e3c9717 | 5067 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
5068 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5069 | ||
a65347ba | 5070 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5071 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5072 | |
1c132b44 | 5073 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5074 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5075 | else |
bfd16b2a | 5076 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 5077 | |
a65347ba | 5078 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5079 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 5080 | |
97b040aa ID |
5081 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5082 | if (encoder->post_disable) | |
5083 | encoder->post_disable(encoder); | |
81b088ca | 5084 | |
92966a37 VS |
5085 | if (intel_crtc->config->has_pch_encoder) { |
5086 | lpt_disable_pch_transcoder(dev_priv); | |
503a74e9 | 5087 | lpt_disable_iclkip(dev_priv); |
92966a37 VS |
5088 | intel_ddi_fdi_disable(crtc); |
5089 | ||
81b088ca VS |
5090 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5091 | true); | |
92966a37 | 5092 | } |
4f771f10 PZ |
5093 | } |
5094 | ||
2dd24552 JB |
5095 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5096 | { | |
5097 | struct drm_device *dev = crtc->base.dev; | |
5098 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 5099 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5100 | |
681a8504 | 5101 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5102 | return; |
5103 | ||
2dd24552 | 5104 | /* |
c0b03411 DV |
5105 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5106 | * according to register description and PRM. | |
2dd24552 | 5107 | */ |
c0b03411 DV |
5108 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5109 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5110 | |
b074cec8 JB |
5111 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5112 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5113 | |
5114 | /* Border color in case we don't scale up to the full screen. Black by | |
5115 | * default, change to something else for debugging. */ | |
5116 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5117 | } |
5118 | ||
d05410f9 DA |
5119 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5120 | { | |
5121 | switch (port) { | |
5122 | case PORT_A: | |
6331a704 | 5123 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
d05410f9 | 5124 | case PORT_B: |
6331a704 | 5125 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
d05410f9 | 5126 | case PORT_C: |
6331a704 | 5127 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
d05410f9 | 5128 | case PORT_D: |
6331a704 | 5129 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
d8e19f99 | 5130 | case PORT_E: |
6331a704 | 5131 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
d05410f9 | 5132 | default: |
b9fec167 | 5133 | MISSING_CASE(port); |
d05410f9 DA |
5134 | return POWER_DOMAIN_PORT_OTHER; |
5135 | } | |
5136 | } | |
5137 | ||
25f78f58 VS |
5138 | static enum intel_display_power_domain port_to_aux_power_domain(enum port port) |
5139 | { | |
5140 | switch (port) { | |
5141 | case PORT_A: | |
5142 | return POWER_DOMAIN_AUX_A; | |
5143 | case PORT_B: | |
5144 | return POWER_DOMAIN_AUX_B; | |
5145 | case PORT_C: | |
5146 | return POWER_DOMAIN_AUX_C; | |
5147 | case PORT_D: | |
5148 | return POWER_DOMAIN_AUX_D; | |
5149 | case PORT_E: | |
5150 | /* FIXME: Check VBT for actual wiring of PORT E */ | |
5151 | return POWER_DOMAIN_AUX_D; | |
5152 | default: | |
b9fec167 | 5153 | MISSING_CASE(port); |
25f78f58 VS |
5154 | return POWER_DOMAIN_AUX_A; |
5155 | } | |
5156 | } | |
5157 | ||
319be8ae ID |
5158 | enum intel_display_power_domain |
5159 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5160 | { | |
5161 | struct drm_device *dev = intel_encoder->base.dev; | |
5162 | struct intel_digital_port *intel_dig_port; | |
5163 | ||
5164 | switch (intel_encoder->type) { | |
5165 | case INTEL_OUTPUT_UNKNOWN: | |
5166 | /* Only DDI platforms should ever use this output type */ | |
5167 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
5168 | case INTEL_OUTPUT_DISPLAYPORT: | |
5169 | case INTEL_OUTPUT_HDMI: | |
5170 | case INTEL_OUTPUT_EDP: | |
5171 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 5172 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
5173 | case INTEL_OUTPUT_DP_MST: |
5174 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5175 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
5176 | case INTEL_OUTPUT_ANALOG: |
5177 | return POWER_DOMAIN_PORT_CRT; | |
5178 | case INTEL_OUTPUT_DSI: | |
5179 | return POWER_DOMAIN_PORT_DSI; | |
5180 | default: | |
5181 | return POWER_DOMAIN_PORT_OTHER; | |
5182 | } | |
5183 | } | |
5184 | ||
25f78f58 VS |
5185 | enum intel_display_power_domain |
5186 | intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder) | |
5187 | { | |
5188 | struct drm_device *dev = intel_encoder->base.dev; | |
5189 | struct intel_digital_port *intel_dig_port; | |
5190 | ||
5191 | switch (intel_encoder->type) { | |
5192 | case INTEL_OUTPUT_UNKNOWN: | |
651174a4 ID |
5193 | case INTEL_OUTPUT_HDMI: |
5194 | /* | |
5195 | * Only DDI platforms should ever use these output types. | |
5196 | * We can get here after the HDMI detect code has already set | |
5197 | * the type of the shared encoder. Since we can't be sure | |
5198 | * what's the status of the given connectors, play safe and | |
5199 | * run the DP detection too. | |
5200 | */ | |
25f78f58 VS |
5201 | WARN_ON_ONCE(!HAS_DDI(dev)); |
5202 | case INTEL_OUTPUT_DISPLAYPORT: | |
5203 | case INTEL_OUTPUT_EDP: | |
5204 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
5205 | return port_to_aux_power_domain(intel_dig_port->port); | |
5206 | case INTEL_OUTPUT_DP_MST: | |
5207 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5208 | return port_to_aux_power_domain(intel_dig_port->port); | |
5209 | default: | |
b9fec167 | 5210 | MISSING_CASE(intel_encoder->type); |
25f78f58 VS |
5211 | return POWER_DOMAIN_AUX_A; |
5212 | } | |
5213 | } | |
5214 | ||
74bff5f9 ML |
5215 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc, |
5216 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5217 | { |
319be8ae | 5218 | struct drm_device *dev = crtc->dev; |
74bff5f9 | 5219 | struct drm_encoder *encoder; |
319be8ae ID |
5220 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5221 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca | 5222 | unsigned long mask; |
74bff5f9 | 5223 | enum transcoder transcoder = crtc_state->cpu_transcoder; |
77d22dca | 5224 | |
74bff5f9 | 5225 | if (!crtc_state->base.active) |
292b990e ML |
5226 | return 0; |
5227 | ||
77d22dca ID |
5228 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5229 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
74bff5f9 ML |
5230 | if (crtc_state->pch_pfit.enabled || |
5231 | crtc_state->pch_pfit.force_thru) | |
77d22dca ID |
5232 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5233 | ||
74bff5f9 ML |
5234 | drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) { |
5235 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
5236 | ||
319be8ae | 5237 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); |
74bff5f9 | 5238 | } |
319be8ae | 5239 | |
15e7ec29 ML |
5240 | if (crtc_state->shared_dpll) |
5241 | mask |= BIT(POWER_DOMAIN_PLLS); | |
5242 | ||
77d22dca ID |
5243 | return mask; |
5244 | } | |
5245 | ||
74bff5f9 ML |
5246 | static unsigned long |
5247 | modeset_get_crtc_power_domains(struct drm_crtc *crtc, | |
5248 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5249 | { |
292b990e ML |
5250 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
5251 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5252 | enum intel_display_power_domain domain; | |
5253 | unsigned long domains, new_domains, old_domains; | |
77d22dca | 5254 | |
292b990e | 5255 | old_domains = intel_crtc->enabled_power_domains; |
74bff5f9 ML |
5256 | intel_crtc->enabled_power_domains = new_domains = |
5257 | get_crtc_power_domains(crtc, crtc_state); | |
77d22dca | 5258 | |
292b990e ML |
5259 | domains = new_domains & ~old_domains; |
5260 | ||
5261 | for_each_power_domain(domain, domains) | |
5262 | intel_display_power_get(dev_priv, domain); | |
5263 | ||
5264 | return old_domains & ~new_domains; | |
5265 | } | |
5266 | ||
5267 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
5268 | unsigned long domains) | |
5269 | { | |
5270 | enum intel_display_power_domain domain; | |
5271 | ||
5272 | for_each_power_domain(domain, domains) | |
5273 | intel_display_power_put(dev_priv, domain); | |
5274 | } | |
77d22dca | 5275 | |
adafdc6f MK |
5276 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
5277 | { | |
5278 | int max_cdclk_freq = dev_priv->max_cdclk_freq; | |
5279 | ||
5280 | if (INTEL_INFO(dev_priv)->gen >= 9 || | |
5281 | IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
5282 | return max_cdclk_freq; | |
5283 | else if (IS_CHERRYVIEW(dev_priv)) | |
5284 | return max_cdclk_freq*95/100; | |
5285 | else if (INTEL_INFO(dev_priv)->gen < 4) | |
5286 | return 2*max_cdclk_freq*90/100; | |
5287 | else | |
5288 | return max_cdclk_freq*90/100; | |
5289 | } | |
5290 | ||
560a7ae4 DL |
5291 | static void intel_update_max_cdclk(struct drm_device *dev) |
5292 | { | |
5293 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5294 | ||
ef11bdb3 | 5295 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
560a7ae4 DL |
5296 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; |
5297 | ||
5298 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) | |
5299 | dev_priv->max_cdclk_freq = 675000; | |
5300 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) | |
5301 | dev_priv->max_cdclk_freq = 540000; | |
5302 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) | |
5303 | dev_priv->max_cdclk_freq = 450000; | |
5304 | else | |
5305 | dev_priv->max_cdclk_freq = 337500; | |
5306 | } else if (IS_BROADWELL(dev)) { | |
5307 | /* | |
5308 | * FIXME with extra cooling we can allow | |
5309 | * 540 MHz for ULX and 675 Mhz for ULT. | |
5310 | * How can we know if extra cooling is | |
5311 | * available? PCI ID, VTB, something else? | |
5312 | */ | |
5313 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
5314 | dev_priv->max_cdclk_freq = 450000; | |
5315 | else if (IS_BDW_ULX(dev)) | |
5316 | dev_priv->max_cdclk_freq = 450000; | |
5317 | else if (IS_BDW_ULT(dev)) | |
5318 | dev_priv->max_cdclk_freq = 540000; | |
5319 | else | |
5320 | dev_priv->max_cdclk_freq = 675000; | |
0904deaf MK |
5321 | } else if (IS_CHERRYVIEW(dev)) { |
5322 | dev_priv->max_cdclk_freq = 320000; | |
560a7ae4 DL |
5323 | } else if (IS_VALLEYVIEW(dev)) { |
5324 | dev_priv->max_cdclk_freq = 400000; | |
5325 | } else { | |
5326 | /* otherwise assume cdclk is fixed */ | |
5327 | dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; | |
5328 | } | |
5329 | ||
adafdc6f MK |
5330 | dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); |
5331 | ||
560a7ae4 DL |
5332 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", |
5333 | dev_priv->max_cdclk_freq); | |
adafdc6f MK |
5334 | |
5335 | DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", | |
5336 | dev_priv->max_dotclk_freq); | |
560a7ae4 DL |
5337 | } |
5338 | ||
5339 | static void intel_update_cdclk(struct drm_device *dev) | |
5340 | { | |
5341 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5342 | ||
5343 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
5344 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", | |
5345 | dev_priv->cdclk_freq); | |
5346 | ||
5347 | /* | |
5348 | * Program the gmbus_freq based on the cdclk frequency. | |
5349 | * BSpec erroneously claims we should aim for 4MHz, but | |
5350 | * in fact 1MHz is the correct frequency. | |
5351 | */ | |
666a4537 | 5352 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
560a7ae4 DL |
5353 | /* |
5354 | * Program the gmbus_freq based on the cdclk frequency. | |
5355 | * BSpec erroneously claims we should aim for 4MHz, but | |
5356 | * in fact 1MHz is the correct frequency. | |
5357 | */ | |
5358 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); | |
5359 | } | |
5360 | ||
5361 | if (dev_priv->max_cdclk_freq == 0) | |
5362 | intel_update_max_cdclk(dev); | |
5363 | } | |
5364 | ||
70d0c574 | 5365 | static void broxton_set_cdclk(struct drm_device *dev, int frequency) |
f8437dd1 VK |
5366 | { |
5367 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5368 | uint32_t divider; | |
5369 | uint32_t ratio; | |
5370 | uint32_t current_freq; | |
5371 | int ret; | |
5372 | ||
5373 | /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */ | |
5374 | switch (frequency) { | |
5375 | case 144000: | |
5376 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; | |
5377 | ratio = BXT_DE_PLL_RATIO(60); | |
5378 | break; | |
5379 | case 288000: | |
5380 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; | |
5381 | ratio = BXT_DE_PLL_RATIO(60); | |
5382 | break; | |
5383 | case 384000: | |
5384 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; | |
5385 | ratio = BXT_DE_PLL_RATIO(60); | |
5386 | break; | |
5387 | case 576000: | |
5388 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5389 | ratio = BXT_DE_PLL_RATIO(60); | |
5390 | break; | |
5391 | case 624000: | |
5392 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5393 | ratio = BXT_DE_PLL_RATIO(65); | |
5394 | break; | |
5395 | case 19200: | |
5396 | /* | |
5397 | * Bypass frequency with DE PLL disabled. Init ratio, divider | |
5398 | * to suppress GCC warning. | |
5399 | */ | |
5400 | ratio = 0; | |
5401 | divider = 0; | |
5402 | break; | |
5403 | default: | |
5404 | DRM_ERROR("unsupported CDCLK freq %d", frequency); | |
5405 | ||
5406 | return; | |
5407 | } | |
5408 | ||
5409 | mutex_lock(&dev_priv->rps.hw_lock); | |
5410 | /* Inform power controller of upcoming frequency change */ | |
5411 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5412 | 0x80000000); | |
5413 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5414 | ||
5415 | if (ret) { | |
5416 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
5417 | ret, frequency); | |
5418 | return; | |
5419 | } | |
5420 | ||
5421 | current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK; | |
5422 | /* convert from .1 fixpoint MHz with -1MHz offset to kHz */ | |
5423 | current_freq = current_freq * 500 + 1000; | |
5424 | ||
5425 | /* | |
5426 | * DE PLL has to be disabled when | |
5427 | * - setting to 19.2MHz (bypass, PLL isn't used) | |
5428 | * - before setting to 624MHz (PLL needs toggling) | |
5429 | * - before setting to any frequency from 624MHz (PLL needs toggling) | |
5430 | */ | |
5431 | if (frequency == 19200 || frequency == 624000 || | |
5432 | current_freq == 624000) { | |
5433 | I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE); | |
5434 | /* Timeout 200us */ | |
5435 | if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK), | |
5436 | 1)) | |
5437 | DRM_ERROR("timout waiting for DE PLL unlock\n"); | |
5438 | } | |
5439 | ||
5440 | if (frequency != 19200) { | |
5441 | uint32_t val; | |
5442 | ||
5443 | val = I915_READ(BXT_DE_PLL_CTL); | |
5444 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5445 | val |= ratio; | |
5446 | I915_WRITE(BXT_DE_PLL_CTL, val); | |
5447 | ||
5448 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5449 | /* Timeout 200us */ | |
5450 | if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1)) | |
5451 | DRM_ERROR("timeout waiting for DE PLL lock\n"); | |
5452 | ||
5453 | val = I915_READ(CDCLK_CTL); | |
5454 | val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK; | |
5455 | val |= divider; | |
5456 | /* | |
5457 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5458 | * enable otherwise. | |
5459 | */ | |
5460 | val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5461 | if (frequency >= 500000) | |
5462 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5463 | ||
5464 | val &= ~CDCLK_FREQ_DECIMAL_MASK; | |
5465 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ | |
5466 | val |= (frequency - 1000) / 500; | |
5467 | I915_WRITE(CDCLK_CTL, val); | |
5468 | } | |
5469 | ||
5470 | mutex_lock(&dev_priv->rps.hw_lock); | |
5471 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5472 | DIV_ROUND_UP(frequency, 25000)); | |
5473 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5474 | ||
5475 | if (ret) { | |
5476 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
5477 | ret, frequency); | |
5478 | return; | |
5479 | } | |
5480 | ||
a47871bd | 5481 | intel_update_cdclk(dev); |
f8437dd1 VK |
5482 | } |
5483 | ||
5484 | void broxton_init_cdclk(struct drm_device *dev) | |
5485 | { | |
5486 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5487 | uint32_t val; | |
5488 | ||
5489 | /* | |
5490 | * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT | |
5491 | * or else the reset will hang because there is no PCH to respond. | |
5492 | * Move the handshake programming to initialization sequence. | |
5493 | * Previously was left up to BIOS. | |
5494 | */ | |
5495 | val = I915_READ(HSW_NDE_RSTWRN_OPT); | |
5496 | val &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
5497 | I915_WRITE(HSW_NDE_RSTWRN_OPT, val); | |
5498 | ||
5499 | /* Enable PG1 for cdclk */ | |
5500 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); | |
5501 | ||
5502 | /* check if cd clock is enabled */ | |
5503 | if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) { | |
5504 | DRM_DEBUG_KMS("Display already initialized\n"); | |
5505 | return; | |
5506 | } | |
5507 | ||
5508 | /* | |
5509 | * FIXME: | |
5510 | * - The initial CDCLK needs to be read from VBT. | |
5511 | * Need to make this change after VBT has changes for BXT. | |
5512 | * - check if setting the max (or any) cdclk freq is really necessary | |
5513 | * here, it belongs to modeset time | |
5514 | */ | |
5515 | broxton_set_cdclk(dev, 624000); | |
5516 | ||
5517 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
22e02c0b VS |
5518 | POSTING_READ(DBUF_CTL); |
5519 | ||
f8437dd1 VK |
5520 | udelay(10); |
5521 | ||
5522 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5523 | DRM_ERROR("DBuf power enable timeout!\n"); | |
5524 | } | |
5525 | ||
5526 | void broxton_uninit_cdclk(struct drm_device *dev) | |
5527 | { | |
5528 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5529 | ||
5530 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
22e02c0b VS |
5531 | POSTING_READ(DBUF_CTL); |
5532 | ||
f8437dd1 VK |
5533 | udelay(10); |
5534 | ||
5535 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5536 | DRM_ERROR("DBuf power disable timeout!\n"); | |
5537 | ||
5538 | /* Set minimum (bypass) frequency, in effect turning off the DE PLL */ | |
5539 | broxton_set_cdclk(dev, 19200); | |
5540 | ||
5541 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
5542 | } | |
5543 | ||
5d96d8af DL |
5544 | static const struct skl_cdclk_entry { |
5545 | unsigned int freq; | |
5546 | unsigned int vco; | |
5547 | } skl_cdclk_frequencies[] = { | |
5548 | { .freq = 308570, .vco = 8640 }, | |
5549 | { .freq = 337500, .vco = 8100 }, | |
5550 | { .freq = 432000, .vco = 8640 }, | |
5551 | { .freq = 450000, .vco = 8100 }, | |
5552 | { .freq = 540000, .vco = 8100 }, | |
5553 | { .freq = 617140, .vco = 8640 }, | |
5554 | { .freq = 675000, .vco = 8100 }, | |
5555 | }; | |
5556 | ||
5557 | static unsigned int skl_cdclk_decimal(unsigned int freq) | |
5558 | { | |
5559 | return (freq - 1000) / 500; | |
5560 | } | |
5561 | ||
5562 | static unsigned int skl_cdclk_get_vco(unsigned int freq) | |
5563 | { | |
5564 | unsigned int i; | |
5565 | ||
5566 | for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) { | |
5567 | const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i]; | |
5568 | ||
5569 | if (e->freq == freq) | |
5570 | return e->vco; | |
5571 | } | |
5572 | ||
5573 | return 8100; | |
5574 | } | |
5575 | ||
5576 | static void | |
5577 | skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco) | |
5578 | { | |
5579 | unsigned int min_freq; | |
5580 | u32 val; | |
5581 | ||
5582 | /* select the minimum CDCLK before enabling DPLL 0 */ | |
5583 | val = I915_READ(CDCLK_CTL); | |
5584 | val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK; | |
5585 | val |= CDCLK_FREQ_337_308; | |
5586 | ||
5587 | if (required_vco == 8640) | |
5588 | min_freq = 308570; | |
5589 | else | |
5590 | min_freq = 337500; | |
5591 | ||
5592 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq); | |
5593 | ||
5594 | I915_WRITE(CDCLK_CTL, val); | |
5595 | POSTING_READ(CDCLK_CTL); | |
5596 | ||
5597 | /* | |
5598 | * We always enable DPLL0 with the lowest link rate possible, but still | |
5599 | * taking into account the VCO required to operate the eDP panel at the | |
5600 | * desired frequency. The usual DP link rates operate with a VCO of | |
5601 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. | |
5602 | * The modeset code is responsible for the selection of the exact link | |
5603 | * rate later on, with the constraint of choosing a frequency that | |
5604 | * works with required_vco. | |
5605 | */ | |
5606 | val = I915_READ(DPLL_CTRL1); | |
5607 | ||
5608 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
5609 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
5610 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
5611 | if (required_vco == 8640) | |
5612 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, | |
5613 | SKL_DPLL0); | |
5614 | else | |
5615 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, | |
5616 | SKL_DPLL0); | |
5617 | ||
5618 | I915_WRITE(DPLL_CTRL1, val); | |
5619 | POSTING_READ(DPLL_CTRL1); | |
5620 | ||
5621 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); | |
5622 | ||
5623 | if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5)) | |
5624 | DRM_ERROR("DPLL0 not locked\n"); | |
5625 | } | |
5626 | ||
5627 | static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) | |
5628 | { | |
5629 | int ret; | |
5630 | u32 val; | |
5631 | ||
5632 | /* inform PCU we want to change CDCLK */ | |
5633 | val = SKL_CDCLK_PREPARE_FOR_CHANGE; | |
5634 | mutex_lock(&dev_priv->rps.hw_lock); | |
5635 | ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); | |
5636 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5637 | ||
5638 | return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE); | |
5639 | } | |
5640 | ||
5641 | static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) | |
5642 | { | |
5643 | unsigned int i; | |
5644 | ||
5645 | for (i = 0; i < 15; i++) { | |
5646 | if (skl_cdclk_pcu_ready(dev_priv)) | |
5647 | return true; | |
5648 | udelay(10); | |
5649 | } | |
5650 | ||
5651 | return false; | |
5652 | } | |
5653 | ||
5654 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq) | |
5655 | { | |
560a7ae4 | 5656 | struct drm_device *dev = dev_priv->dev; |
5d96d8af DL |
5657 | u32 freq_select, pcu_ack; |
5658 | ||
5659 | DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq); | |
5660 | ||
5661 | if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { | |
5662 | DRM_ERROR("failed to inform PCU about cdclk change\n"); | |
5663 | return; | |
5664 | } | |
5665 | ||
5666 | /* set CDCLK_CTL */ | |
5667 | switch(freq) { | |
5668 | case 450000: | |
5669 | case 432000: | |
5670 | freq_select = CDCLK_FREQ_450_432; | |
5671 | pcu_ack = 1; | |
5672 | break; | |
5673 | case 540000: | |
5674 | freq_select = CDCLK_FREQ_540; | |
5675 | pcu_ack = 2; | |
5676 | break; | |
5677 | case 308570: | |
5678 | case 337500: | |
5679 | default: | |
5680 | freq_select = CDCLK_FREQ_337_308; | |
5681 | pcu_ack = 0; | |
5682 | break; | |
5683 | case 617140: | |
5684 | case 675000: | |
5685 | freq_select = CDCLK_FREQ_675_617; | |
5686 | pcu_ack = 3; | |
5687 | break; | |
5688 | } | |
5689 | ||
5690 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq)); | |
5691 | POSTING_READ(CDCLK_CTL); | |
5692 | ||
5693 | /* inform PCU of the change */ | |
5694 | mutex_lock(&dev_priv->rps.hw_lock); | |
5695 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); | |
5696 | mutex_unlock(&dev_priv->rps.hw_lock); | |
560a7ae4 DL |
5697 | |
5698 | intel_update_cdclk(dev); | |
5d96d8af DL |
5699 | } |
5700 | ||
5701 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) | |
5702 | { | |
5703 | /* disable DBUF power */ | |
5704 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
5705 | POSTING_READ(DBUF_CTL); | |
5706 | ||
5707 | udelay(10); | |
5708 | ||
5709 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5710 | DRM_ERROR("DBuf power disable timeout\n"); | |
5711 | ||
ab96c1ee ID |
5712 | /* disable DPLL0 */ |
5713 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); | |
5714 | if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) | |
5715 | DRM_ERROR("Couldn't disable DPLL0\n"); | |
5d96d8af DL |
5716 | } |
5717 | ||
5718 | void skl_init_cdclk(struct drm_i915_private *dev_priv) | |
5719 | { | |
5d96d8af DL |
5720 | unsigned int required_vco; |
5721 | ||
39d9b85a GW |
5722 | /* DPLL0 not enabled (happens on early BIOS versions) */ |
5723 | if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) { | |
5724 | /* enable DPLL0 */ | |
5725 | required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk); | |
5726 | skl_dpll0_enable(dev_priv, required_vco); | |
5d96d8af DL |
5727 | } |
5728 | ||
5d96d8af DL |
5729 | /* set CDCLK to the frequency the BIOS chose */ |
5730 | skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk); | |
5731 | ||
5732 | /* enable DBUF power */ | |
5733 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
5734 | POSTING_READ(DBUF_CTL); | |
5735 | ||
5736 | udelay(10); | |
5737 | ||
5738 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5739 | DRM_ERROR("DBuf power enable timeout\n"); | |
5740 | } | |
5741 | ||
c73666f3 SK |
5742 | int skl_sanitize_cdclk(struct drm_i915_private *dev_priv) |
5743 | { | |
5744 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
5745 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
5746 | int freq = dev_priv->skl_boot_cdclk; | |
5747 | ||
f1b391a5 SK |
5748 | /* |
5749 | * check if the pre-os intialized the display | |
5750 | * There is SWF18 scratchpad register defined which is set by the | |
5751 | * pre-os which can be used by the OS drivers to check the status | |
5752 | */ | |
5753 | if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) | |
5754 | goto sanitize; | |
5755 | ||
c73666f3 SK |
5756 | /* Is PLL enabled and locked ? */ |
5757 | if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK))) | |
5758 | goto sanitize; | |
5759 | ||
5760 | /* DPLL okay; verify the cdclock | |
5761 | * | |
5762 | * Noticed in some instances that the freq selection is correct but | |
5763 | * decimal part is programmed wrong from BIOS where pre-os does not | |
5764 | * enable display. Verify the same as well. | |
5765 | */ | |
5766 | if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq))) | |
5767 | /* All well; nothing to sanitize */ | |
5768 | return false; | |
5769 | sanitize: | |
5770 | /* | |
5771 | * As of now initialize with max cdclk till | |
5772 | * we get dynamic cdclk support | |
5773 | * */ | |
5774 | dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq; | |
5775 | skl_init_cdclk(dev_priv); | |
5776 | ||
5777 | /* we did have to sanitize */ | |
5778 | return true; | |
5779 | } | |
5780 | ||
30a970c6 JB |
5781 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
5782 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
5783 | { | |
5784 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5785 | u32 val, cmd; | |
5786 | ||
164dfd28 VK |
5787 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5788 | != dev_priv->cdclk_freq); | |
d60c4473 | 5789 | |
dfcab17e | 5790 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 5791 | cmd = 2; |
dfcab17e | 5792 | else if (cdclk == 266667) |
30a970c6 JB |
5793 | cmd = 1; |
5794 | else | |
5795 | cmd = 0; | |
5796 | ||
5797 | mutex_lock(&dev_priv->rps.hw_lock); | |
5798 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5799 | val &= ~DSPFREQGUAR_MASK; | |
5800 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
5801 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5802 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5803 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
5804 | 50)) { | |
5805 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5806 | } | |
5807 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5808 | ||
54433e91 VS |
5809 | mutex_lock(&dev_priv->sb_lock); |
5810 | ||
dfcab17e | 5811 | if (cdclk == 400000) { |
6bcda4f0 | 5812 | u32 divider; |
30a970c6 | 5813 | |
6bcda4f0 | 5814 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 | 5815 | |
30a970c6 JB |
5816 | /* adjust cdclk divider */ |
5817 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
87d5d259 | 5818 | val &= ~CCK_FREQUENCY_VALUES; |
30a970c6 JB |
5819 | val |= divider; |
5820 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
5821 | |
5822 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
87d5d259 | 5823 | CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), |
a877e801 VS |
5824 | 50)) |
5825 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
5826 | } |
5827 | ||
30a970c6 JB |
5828 | /* adjust self-refresh exit latency value */ |
5829 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
5830 | val &= ~0x7f; | |
5831 | ||
5832 | /* | |
5833 | * For high bandwidth configs, we set a higher latency in the bunit | |
5834 | * so that the core display fetch happens in time to avoid underruns. | |
5835 | */ | |
dfcab17e | 5836 | if (cdclk == 400000) |
30a970c6 JB |
5837 | val |= 4500 / 250; /* 4.5 usec */ |
5838 | else | |
5839 | val |= 3000 / 250; /* 3.0 usec */ | |
5840 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
54433e91 | 5841 | |
a580516d | 5842 | mutex_unlock(&dev_priv->sb_lock); |
30a970c6 | 5843 | |
b6283055 | 5844 | intel_update_cdclk(dev); |
30a970c6 JB |
5845 | } |
5846 | ||
383c5a6a VS |
5847 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
5848 | { | |
5849 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5850 | u32 val, cmd; | |
5851 | ||
164dfd28 VK |
5852 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5853 | != dev_priv->cdclk_freq); | |
383c5a6a VS |
5854 | |
5855 | switch (cdclk) { | |
383c5a6a VS |
5856 | case 333333: |
5857 | case 320000: | |
383c5a6a | 5858 | case 266667: |
383c5a6a | 5859 | case 200000: |
383c5a6a VS |
5860 | break; |
5861 | default: | |
5f77eeb0 | 5862 | MISSING_CASE(cdclk); |
383c5a6a VS |
5863 | return; |
5864 | } | |
5865 | ||
9d0d3fda VS |
5866 | /* |
5867 | * Specs are full of misinformation, but testing on actual | |
5868 | * hardware has shown that we just need to write the desired | |
5869 | * CCK divider into the Punit register. | |
5870 | */ | |
5871 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
5872 | ||
383c5a6a VS |
5873 | mutex_lock(&dev_priv->rps.hw_lock); |
5874 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5875 | val &= ~DSPFREQGUAR_MASK_CHV; | |
5876 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
5877 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5878 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5879 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
5880 | 50)) { | |
5881 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5882 | } | |
5883 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5884 | ||
b6283055 | 5885 | intel_update_cdclk(dev); |
383c5a6a VS |
5886 | } |
5887 | ||
30a970c6 JB |
5888 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
5889 | int max_pixclk) | |
5890 | { | |
6bcda4f0 | 5891 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 5892 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 5893 | |
30a970c6 JB |
5894 | /* |
5895 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
5896 | * 200MHz | |
5897 | * 267MHz | |
29dc7ef3 | 5898 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
5899 | * 400MHz (VLV only) |
5900 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
5901 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
5902 | * |
5903 | * We seem to get an unstable or solid color picture at 200MHz. | |
5904 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
5905 | * are off. | |
30a970c6 | 5906 | */ |
6cca3195 VS |
5907 | if (!IS_CHERRYVIEW(dev_priv) && |
5908 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 5909 | return 400000; |
6cca3195 | 5910 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 5911 | return freq_320; |
e37c67a1 | 5912 | else if (max_pixclk > 0) |
dfcab17e | 5913 | return 266667; |
e37c67a1 VS |
5914 | else |
5915 | return 200000; | |
30a970c6 JB |
5916 | } |
5917 | ||
f8437dd1 VK |
5918 | static int broxton_calc_cdclk(struct drm_i915_private *dev_priv, |
5919 | int max_pixclk) | |
5920 | { | |
5921 | /* | |
5922 | * FIXME: | |
5923 | * - remove the guardband, it's not needed on BXT | |
5924 | * - set 19.2MHz bypass frequency if there are no active pipes | |
5925 | */ | |
5926 | if (max_pixclk > 576000*9/10) | |
5927 | return 624000; | |
5928 | else if (max_pixclk > 384000*9/10) | |
5929 | return 576000; | |
5930 | else if (max_pixclk > 288000*9/10) | |
5931 | return 384000; | |
5932 | else if (max_pixclk > 144000*9/10) | |
5933 | return 288000; | |
5934 | else | |
5935 | return 144000; | |
5936 | } | |
5937 | ||
e8788cbc | 5938 | /* Compute the max pixel clock for new configuration. */ |
a821fc46 ACO |
5939 | static int intel_mode_max_pixclk(struct drm_device *dev, |
5940 | struct drm_atomic_state *state) | |
30a970c6 | 5941 | { |
565602d7 ML |
5942 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
5943 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5944 | struct drm_crtc *crtc; | |
5945 | struct drm_crtc_state *crtc_state; | |
5946 | unsigned max_pixclk = 0, i; | |
5947 | enum pipe pipe; | |
30a970c6 | 5948 | |
565602d7 ML |
5949 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
5950 | sizeof(intel_state->min_pixclk)); | |
304603f4 | 5951 | |
565602d7 ML |
5952 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
5953 | int pixclk = 0; | |
5954 | ||
5955 | if (crtc_state->enable) | |
5956 | pixclk = crtc_state->adjusted_mode.crtc_clock; | |
304603f4 | 5957 | |
565602d7 | 5958 | intel_state->min_pixclk[i] = pixclk; |
30a970c6 JB |
5959 | } |
5960 | ||
565602d7 ML |
5961 | for_each_pipe(dev_priv, pipe) |
5962 | max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk); | |
5963 | ||
30a970c6 JB |
5964 | return max_pixclk; |
5965 | } | |
5966 | ||
27c329ed | 5967 | static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) |
30a970c6 | 5968 | { |
27c329ed ML |
5969 | struct drm_device *dev = state->dev; |
5970 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5971 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
1a617b77 ML |
5972 | struct intel_atomic_state *intel_state = |
5973 | to_intel_atomic_state(state); | |
30a970c6 | 5974 | |
304603f4 ACO |
5975 | if (max_pixclk < 0) |
5976 | return max_pixclk; | |
30a970c6 | 5977 | |
1a617b77 | 5978 | intel_state->cdclk = intel_state->dev_cdclk = |
27c329ed | 5979 | valleyview_calc_cdclk(dev_priv, max_pixclk); |
0a9ab303 | 5980 | |
1a617b77 ML |
5981 | if (!intel_state->active_crtcs) |
5982 | intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0); | |
5983 | ||
27c329ed ML |
5984 | return 0; |
5985 | } | |
304603f4 | 5986 | |
27c329ed ML |
5987 | static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state) |
5988 | { | |
5989 | struct drm_device *dev = state->dev; | |
5990 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5991 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
1a617b77 ML |
5992 | struct intel_atomic_state *intel_state = |
5993 | to_intel_atomic_state(state); | |
85a96e7a | 5994 | |
27c329ed ML |
5995 | if (max_pixclk < 0) |
5996 | return max_pixclk; | |
85a96e7a | 5997 | |
1a617b77 | 5998 | intel_state->cdclk = intel_state->dev_cdclk = |
27c329ed | 5999 | broxton_calc_cdclk(dev_priv, max_pixclk); |
85a96e7a | 6000 | |
1a617b77 ML |
6001 | if (!intel_state->active_crtcs) |
6002 | intel_state->dev_cdclk = broxton_calc_cdclk(dev_priv, 0); | |
6003 | ||
27c329ed | 6004 | return 0; |
30a970c6 JB |
6005 | } |
6006 | ||
1e69cd74 VS |
6007 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
6008 | { | |
6009 | unsigned int credits, default_credits; | |
6010 | ||
6011 | if (IS_CHERRYVIEW(dev_priv)) | |
6012 | default_credits = PFI_CREDIT(12); | |
6013 | else | |
6014 | default_credits = PFI_CREDIT(8); | |
6015 | ||
bfa7df01 | 6016 | if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) { |
1e69cd74 VS |
6017 | /* CHV suggested value is 31 or 63 */ |
6018 | if (IS_CHERRYVIEW(dev_priv)) | |
fcc0008f | 6019 | credits = PFI_CREDIT_63; |
1e69cd74 VS |
6020 | else |
6021 | credits = PFI_CREDIT(15); | |
6022 | } else { | |
6023 | credits = default_credits; | |
6024 | } | |
6025 | ||
6026 | /* | |
6027 | * WA - write default credits before re-programming | |
6028 | * FIXME: should we also set the resend bit here? | |
6029 | */ | |
6030 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6031 | default_credits); | |
6032 | ||
6033 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6034 | credits | PFI_CREDIT_RESEND); | |
6035 | ||
6036 | /* | |
6037 | * FIXME is this guaranteed to clear | |
6038 | * immediately or should we poll for it? | |
6039 | */ | |
6040 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
6041 | } | |
6042 | ||
27c329ed | 6043 | static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
30a970c6 | 6044 | { |
a821fc46 | 6045 | struct drm_device *dev = old_state->dev; |
30a970c6 | 6046 | struct drm_i915_private *dev_priv = dev->dev_private; |
1a617b77 ML |
6047 | struct intel_atomic_state *old_intel_state = |
6048 | to_intel_atomic_state(old_state); | |
6049 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
30a970c6 | 6050 | |
27c329ed ML |
6051 | /* |
6052 | * FIXME: We can end up here with all power domains off, yet | |
6053 | * with a CDCLK frequency other than the minimum. To account | |
6054 | * for this take the PIPE-A power domain, which covers the HW | |
6055 | * blocks needed for the following programming. This can be | |
6056 | * removed once it's guaranteed that we get here either with | |
6057 | * the minimum CDCLK set, or the required power domains | |
6058 | * enabled. | |
6059 | */ | |
6060 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
738c05c0 | 6061 | |
27c329ed ML |
6062 | if (IS_CHERRYVIEW(dev)) |
6063 | cherryview_set_cdclk(dev, req_cdclk); | |
6064 | else | |
6065 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 6066 | |
27c329ed | 6067 | vlv_program_pfi_credits(dev_priv); |
1e69cd74 | 6068 | |
27c329ed | 6069 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
30a970c6 JB |
6070 | } |
6071 | ||
89b667f8 JB |
6072 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
6073 | { | |
6074 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6075 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
6076 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6077 | struct intel_encoder *encoder; | |
6078 | int pipe = intel_crtc->pipe; | |
89b667f8 | 6079 | |
53d9f4e9 | 6080 | if (WARN_ON(intel_crtc->active)) |
89b667f8 JB |
6081 | return; |
6082 | ||
6e3c9717 | 6083 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6084 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6085 | |
6086 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 6087 | intel_set_pipe_src_size(intel_crtc); |
5b18e57c | 6088 | |
c14b0485 VS |
6089 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
6090 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6091 | ||
6092 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
6093 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
6094 | } | |
6095 | ||
5b18e57c DV |
6096 | i9xx_set_pipeconf(intel_crtc); |
6097 | ||
89b667f8 | 6098 | intel_crtc->active = true; |
89b667f8 | 6099 | |
a72e4c9f | 6100 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6101 | |
89b667f8 JB |
6102 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6103 | if (encoder->pre_pll_enable) | |
6104 | encoder->pre_pll_enable(encoder); | |
6105 | ||
a65347ba | 6106 | if (!intel_crtc->config->has_dsi_encoder) { |
c0b4c660 VS |
6107 | if (IS_CHERRYVIEW(dev)) { |
6108 | chv_prepare_pll(intel_crtc, intel_crtc->config); | |
6e3c9717 | 6109 | chv_enable_pll(intel_crtc, intel_crtc->config); |
c0b4c660 VS |
6110 | } else { |
6111 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
6e3c9717 | 6112 | vlv_enable_pll(intel_crtc, intel_crtc->config); |
c0b4c660 | 6113 | } |
9d556c99 | 6114 | } |
89b667f8 JB |
6115 | |
6116 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
6117 | if (encoder->pre_enable) | |
6118 | encoder->pre_enable(encoder); | |
6119 | ||
2dd24552 JB |
6120 | i9xx_pfit_enable(intel_crtc); |
6121 | ||
8563b1e8 | 6122 | intel_color_load_luts(crtc); |
63cbb074 | 6123 | |
caed361d | 6124 | intel_update_watermarks(crtc); |
e1fdc473 | 6125 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6126 | |
4b3a9526 VS |
6127 | assert_vblank_disabled(crtc); |
6128 | drm_crtc_vblank_on(crtc); | |
6129 | ||
f9b61ff6 DV |
6130 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6131 | encoder->enable(encoder); | |
89b667f8 JB |
6132 | } |
6133 | ||
f13c2ef3 DV |
6134 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
6135 | { | |
6136 | struct drm_device *dev = crtc->base.dev; | |
6137 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6138 | ||
6e3c9717 ACO |
6139 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
6140 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
6141 | } |
6142 | ||
0b8765c6 | 6143 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
6144 | { |
6145 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6146 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 6147 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 6148 | struct intel_encoder *encoder; |
79e53945 | 6149 | int pipe = intel_crtc->pipe; |
79e53945 | 6150 | |
53d9f4e9 | 6151 | if (WARN_ON(intel_crtc->active)) |
f7abfe8b CW |
6152 | return; |
6153 | ||
f13c2ef3 DV |
6154 | i9xx_set_pll_dividers(intel_crtc); |
6155 | ||
6e3c9717 | 6156 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6157 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6158 | |
6159 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 6160 | intel_set_pipe_src_size(intel_crtc); |
5b18e57c | 6161 | |
5b18e57c DV |
6162 | i9xx_set_pipeconf(intel_crtc); |
6163 | ||
f7abfe8b | 6164 | intel_crtc->active = true; |
6b383a7f | 6165 | |
4a3436e8 | 6166 | if (!IS_GEN2(dev)) |
a72e4c9f | 6167 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6168 | |
9d6d9f19 MK |
6169 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6170 | if (encoder->pre_enable) | |
6171 | encoder->pre_enable(encoder); | |
6172 | ||
f6736a1a DV |
6173 | i9xx_enable_pll(intel_crtc); |
6174 | ||
2dd24552 JB |
6175 | i9xx_pfit_enable(intel_crtc); |
6176 | ||
8563b1e8 | 6177 | intel_color_load_luts(crtc); |
63cbb074 | 6178 | |
f37fcc2a | 6179 | intel_update_watermarks(crtc); |
e1fdc473 | 6180 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6181 | |
4b3a9526 VS |
6182 | assert_vblank_disabled(crtc); |
6183 | drm_crtc_vblank_on(crtc); | |
6184 | ||
f9b61ff6 DV |
6185 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6186 | encoder->enable(encoder); | |
0b8765c6 | 6187 | } |
79e53945 | 6188 | |
87476d63 DV |
6189 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
6190 | { | |
6191 | struct drm_device *dev = crtc->base.dev; | |
6192 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 6193 | |
6e3c9717 | 6194 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 6195 | return; |
87476d63 | 6196 | |
328d8e82 | 6197 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 6198 | |
328d8e82 DV |
6199 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
6200 | I915_READ(PFIT_CONTROL)); | |
6201 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
6202 | } |
6203 | ||
0b8765c6 JB |
6204 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
6205 | { | |
6206 | struct drm_device *dev = crtc->dev; | |
6207 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6208 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 6209 | struct intel_encoder *encoder; |
0b8765c6 | 6210 | int pipe = intel_crtc->pipe; |
ef9c3aee | 6211 | |
6304cd91 VS |
6212 | /* |
6213 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
6214 | * wait for planes to fully turn off before disabling the pipe. | |
564ed191 ID |
6215 | * We also need to wait on all gmch platforms because of the |
6216 | * self-refresh mode constraint explained above. | |
6304cd91 | 6217 | */ |
564ed191 | 6218 | intel_wait_for_vblank(dev, pipe); |
6304cd91 | 6219 | |
4b3a9526 VS |
6220 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6221 | encoder->disable(encoder); | |
6222 | ||
f9b61ff6 DV |
6223 | drm_crtc_vblank_off(crtc); |
6224 | assert_vblank_disabled(crtc); | |
6225 | ||
575f7ab7 | 6226 | intel_disable_pipe(intel_crtc); |
24a1f16d | 6227 | |
87476d63 | 6228 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 6229 | |
89b667f8 JB |
6230 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6231 | if (encoder->post_disable) | |
6232 | encoder->post_disable(encoder); | |
6233 | ||
a65347ba | 6234 | if (!intel_crtc->config->has_dsi_encoder) { |
076ed3b2 CML |
6235 | if (IS_CHERRYVIEW(dev)) |
6236 | chv_disable_pll(dev_priv, pipe); | |
6237 | else if (IS_VALLEYVIEW(dev)) | |
6238 | vlv_disable_pll(dev_priv, pipe); | |
6239 | else | |
1c4e0274 | 6240 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 6241 | } |
0b8765c6 | 6242 | |
d6db995f VS |
6243 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6244 | if (encoder->post_pll_disable) | |
6245 | encoder->post_pll_disable(encoder); | |
6246 | ||
4a3436e8 | 6247 | if (!IS_GEN2(dev)) |
a72e4c9f | 6248 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
0b8765c6 JB |
6249 | } |
6250 | ||
b17d48e2 ML |
6251 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
6252 | { | |
842e0307 | 6253 | struct intel_encoder *encoder; |
b17d48e2 ML |
6254 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6255 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
6256 | enum intel_display_power_domain domain; | |
6257 | unsigned long domains; | |
6258 | ||
6259 | if (!intel_crtc->active) | |
6260 | return; | |
6261 | ||
a539205a | 6262 | if (to_intel_plane_state(crtc->primary->state)->visible) { |
fc32b1fd ML |
6263 | WARN_ON(intel_crtc->unpin_work); |
6264 | ||
2622a081 | 6265 | intel_pre_disable_primary_noatomic(crtc); |
54a41961 ML |
6266 | |
6267 | intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); | |
6268 | to_intel_plane_state(crtc->primary->state)->visible = false; | |
a539205a ML |
6269 | } |
6270 | ||
b17d48e2 | 6271 | dev_priv->display.crtc_disable(crtc); |
842e0307 ML |
6272 | |
6273 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was enabled, now disabled\n", | |
6274 | crtc->base.id); | |
6275 | ||
6276 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0); | |
6277 | crtc->state->active = false; | |
37d9078b | 6278 | intel_crtc->active = false; |
842e0307 ML |
6279 | crtc->enabled = false; |
6280 | crtc->state->connector_mask = 0; | |
6281 | crtc->state->encoder_mask = 0; | |
6282 | ||
6283 | for_each_encoder_on_crtc(crtc->dev, crtc, encoder) | |
6284 | encoder->base.crtc = NULL; | |
6285 | ||
58f9c0bc | 6286 | intel_fbc_disable(intel_crtc); |
37d9078b | 6287 | intel_update_watermarks(crtc); |
1f7457b1 | 6288 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
6289 | |
6290 | domains = intel_crtc->enabled_power_domains; | |
6291 | for_each_power_domain(domain, domains) | |
6292 | intel_display_power_put(dev_priv, domain); | |
6293 | intel_crtc->enabled_power_domains = 0; | |
565602d7 ML |
6294 | |
6295 | dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); | |
6296 | dev_priv->min_pixclk[intel_crtc->pipe] = 0; | |
b17d48e2 ML |
6297 | } |
6298 | ||
6b72d486 ML |
6299 | /* |
6300 | * turn all crtc's off, but do not adjust state | |
6301 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
6302 | */ | |
70e0bd74 | 6303 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 6304 | { |
e2c8b870 | 6305 | struct drm_i915_private *dev_priv = to_i915(dev); |
70e0bd74 | 6306 | struct drm_atomic_state *state; |
e2c8b870 | 6307 | int ret; |
70e0bd74 | 6308 | |
e2c8b870 ML |
6309 | state = drm_atomic_helper_suspend(dev); |
6310 | ret = PTR_ERR_OR_ZERO(state); | |
70e0bd74 ML |
6311 | if (ret) |
6312 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
e2c8b870 ML |
6313 | else |
6314 | dev_priv->modeset_restore_state = state; | |
70e0bd74 | 6315 | return ret; |
ee7b9f93 JB |
6316 | } |
6317 | ||
ea5b213a | 6318 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6319 | { |
4ef69c7a | 6320 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6321 | |
ea5b213a CW |
6322 | drm_encoder_cleanup(encoder); |
6323 | kfree(intel_encoder); | |
7e7d76c3 JB |
6324 | } |
6325 | ||
0a91ca29 DV |
6326 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6327 | * internal consistency). */ | |
b980514c | 6328 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 6329 | { |
35dd3c64 ML |
6330 | struct drm_crtc *crtc = connector->base.state->crtc; |
6331 | ||
6332 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6333 | connector->base.base.id, | |
6334 | connector->base.name); | |
6335 | ||
0a91ca29 | 6336 | if (connector->get_hw_state(connector)) { |
e85376cb | 6337 | struct intel_encoder *encoder = connector->encoder; |
35dd3c64 | 6338 | struct drm_connector_state *conn_state = connector->base.state; |
0a91ca29 | 6339 | |
35dd3c64 ML |
6340 | I915_STATE_WARN(!crtc, |
6341 | "connector enabled without attached crtc\n"); | |
0a91ca29 | 6342 | |
35dd3c64 ML |
6343 | if (!crtc) |
6344 | return; | |
6345 | ||
6346 | I915_STATE_WARN(!crtc->state->active, | |
6347 | "connector is active, but attached crtc isn't\n"); | |
6348 | ||
e85376cb | 6349 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
6350 | return; |
6351 | ||
e85376cb | 6352 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
6353 | "atomic encoder doesn't match attached encoder\n"); |
6354 | ||
e85376cb | 6355 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
6356 | "attached encoder crtc differs from connector crtc\n"); |
6357 | } else { | |
4d688a2a ML |
6358 | I915_STATE_WARN(crtc && crtc->state->active, |
6359 | "attached crtc is active, but connector isn't\n"); | |
35dd3c64 ML |
6360 | I915_STATE_WARN(!crtc && connector->base.state->best_encoder, |
6361 | "best encoder set without crtc!\n"); | |
0a91ca29 | 6362 | } |
79e53945 JB |
6363 | } |
6364 | ||
08d9bc92 ACO |
6365 | int intel_connector_init(struct intel_connector *connector) |
6366 | { | |
5350a031 | 6367 | drm_atomic_helper_connector_reset(&connector->base); |
08d9bc92 | 6368 | |
5350a031 | 6369 | if (!connector->base.state) |
08d9bc92 ACO |
6370 | return -ENOMEM; |
6371 | ||
08d9bc92 ACO |
6372 | return 0; |
6373 | } | |
6374 | ||
6375 | struct intel_connector *intel_connector_alloc(void) | |
6376 | { | |
6377 | struct intel_connector *connector; | |
6378 | ||
6379 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6380 | if (!connector) | |
6381 | return NULL; | |
6382 | ||
6383 | if (intel_connector_init(connector) < 0) { | |
6384 | kfree(connector); | |
6385 | return NULL; | |
6386 | } | |
6387 | ||
6388 | return connector; | |
6389 | } | |
6390 | ||
f0947c37 DV |
6391 | /* Simple connector->get_hw_state implementation for encoders that support only |
6392 | * one connector and no cloning and hence the encoder state determines the state | |
6393 | * of the connector. */ | |
6394 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6395 | { |
24929352 | 6396 | enum pipe pipe = 0; |
f0947c37 | 6397 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6398 | |
f0947c37 | 6399 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6400 | } |
6401 | ||
6d293983 | 6402 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6403 | { |
6d293983 ACO |
6404 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6405 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6406 | |
6407 | return 0; | |
6408 | } | |
6409 | ||
6d293983 | 6410 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6411 | struct intel_crtc_state *pipe_config) |
1857e1da | 6412 | { |
6d293983 ACO |
6413 | struct drm_atomic_state *state = pipe_config->base.state; |
6414 | struct intel_crtc *other_crtc; | |
6415 | struct intel_crtc_state *other_crtc_state; | |
6416 | ||
1857e1da DV |
6417 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6418 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6419 | if (pipe_config->fdi_lanes > 4) { | |
6420 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6421 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6422 | return -EINVAL; |
1857e1da DV |
6423 | } |
6424 | ||
bafb6553 | 6425 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
6426 | if (pipe_config->fdi_lanes > 2) { |
6427 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6428 | pipe_config->fdi_lanes); | |
6d293983 | 6429 | return -EINVAL; |
1857e1da | 6430 | } else { |
6d293983 | 6431 | return 0; |
1857e1da DV |
6432 | } |
6433 | } | |
6434 | ||
6435 | if (INTEL_INFO(dev)->num_pipes == 2) | |
6d293983 | 6436 | return 0; |
1857e1da DV |
6437 | |
6438 | /* Ivybridge 3 pipe is really complicated */ | |
6439 | switch (pipe) { | |
6440 | case PIPE_A: | |
6d293983 | 6441 | return 0; |
1857e1da | 6442 | case PIPE_B: |
6d293983 ACO |
6443 | if (pipe_config->fdi_lanes <= 2) |
6444 | return 0; | |
6445 | ||
6446 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); | |
6447 | other_crtc_state = | |
6448 | intel_atomic_get_crtc_state(state, other_crtc); | |
6449 | if (IS_ERR(other_crtc_state)) | |
6450 | return PTR_ERR(other_crtc_state); | |
6451 | ||
6452 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6453 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6454 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6455 | return -EINVAL; |
1857e1da | 6456 | } |
6d293983 | 6457 | return 0; |
1857e1da | 6458 | case PIPE_C: |
251cc67c VS |
6459 | if (pipe_config->fdi_lanes > 2) { |
6460 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6461 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6462 | return -EINVAL; |
251cc67c | 6463 | } |
6d293983 ACO |
6464 | |
6465 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); | |
6466 | other_crtc_state = | |
6467 | intel_atomic_get_crtc_state(state, other_crtc); | |
6468 | if (IS_ERR(other_crtc_state)) | |
6469 | return PTR_ERR(other_crtc_state); | |
6470 | ||
6471 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6472 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6473 | return -EINVAL; |
1857e1da | 6474 | } |
6d293983 | 6475 | return 0; |
1857e1da DV |
6476 | default: |
6477 | BUG(); | |
6478 | } | |
6479 | } | |
6480 | ||
e29c22c0 DV |
6481 | #define RETRY 1 |
6482 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6483 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6484 | { |
1857e1da | 6485 | struct drm_device *dev = intel_crtc->base.dev; |
7c5f93b0 | 6486 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6487 | int lane, link_bw, fdi_dotclock, ret; |
6488 | bool needs_recompute = false; | |
877d48d5 | 6489 | |
e29c22c0 | 6490 | retry: |
877d48d5 DV |
6491 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6492 | * each output octet as 10 bits. The actual frequency | |
6493 | * is stored as a divider into a 100MHz clock, and the | |
6494 | * mode pixel clock is stored in units of 1KHz. | |
6495 | * Hence the bw of each lane in terms of the mode signal | |
6496 | * is: | |
6497 | */ | |
21a727b3 | 6498 | link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config); |
877d48d5 | 6499 | |
241bfc38 | 6500 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6501 | |
2bd89a07 | 6502 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6503 | pipe_config->pipe_bpp); |
6504 | ||
6505 | pipe_config->fdi_lanes = lane; | |
6506 | ||
2bd89a07 | 6507 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 6508 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 6509 | |
e3b247da | 6510 | ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); |
6d293983 | 6511 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { |
e29c22c0 DV |
6512 | pipe_config->pipe_bpp -= 2*3; |
6513 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
6514 | pipe_config->pipe_bpp); | |
6515 | needs_recompute = true; | |
6516 | pipe_config->bw_constrained = true; | |
6517 | ||
6518 | goto retry; | |
6519 | } | |
6520 | ||
6521 | if (needs_recompute) | |
6522 | return RETRY; | |
6523 | ||
6d293983 | 6524 | return ret; |
877d48d5 DV |
6525 | } |
6526 | ||
8cfb3407 VS |
6527 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
6528 | struct intel_crtc_state *pipe_config) | |
6529 | { | |
6530 | if (pipe_config->pipe_bpp > 24) | |
6531 | return false; | |
6532 | ||
6533 | /* HSW can handle pixel rate up to cdclk? */ | |
6534 | if (IS_HASWELL(dev_priv->dev)) | |
6535 | return true; | |
6536 | ||
6537 | /* | |
b432e5cf VS |
6538 | * We compare against max which means we must take |
6539 | * the increased cdclk requirement into account when | |
6540 | * calculating the new cdclk. | |
6541 | * | |
6542 | * Should measure whether using a lower cdclk w/o IPS | |
8cfb3407 VS |
6543 | */ |
6544 | return ilk_pipe_pixel_rate(pipe_config) <= | |
6545 | dev_priv->max_cdclk_freq * 95 / 100; | |
6546 | } | |
6547 | ||
42db64ef | 6548 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 6549 | struct intel_crtc_state *pipe_config) |
42db64ef | 6550 | { |
8cfb3407 VS |
6551 | struct drm_device *dev = crtc->base.dev; |
6552 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6553 | ||
d330a953 | 6554 | pipe_config->ips_enabled = i915.enable_ips && |
8cfb3407 VS |
6555 | hsw_crtc_supports_ips(crtc) && |
6556 | pipe_config_supports_ips(dev_priv, pipe_config); | |
42db64ef PZ |
6557 | } |
6558 | ||
39acb4aa VS |
6559 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
6560 | { | |
6561 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
6562 | ||
6563 | /* GDG double wide on either pipe, otherwise pipe A only */ | |
6564 | return INTEL_INFO(dev_priv)->gen < 4 && | |
6565 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); | |
6566 | } | |
6567 | ||
a43f6e0f | 6568 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 6569 | struct intel_crtc_state *pipe_config) |
79e53945 | 6570 | { |
a43f6e0f | 6571 | struct drm_device *dev = crtc->base.dev; |
8bd31e67 | 6572 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c5f93b0 | 6573 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
89749350 | 6574 | |
ad3a4479 | 6575 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 | 6576 | if (INTEL_INFO(dev)->gen < 4) { |
39acb4aa | 6577 | int clock_limit = dev_priv->max_cdclk_freq * 9 / 10; |
cf532bb2 VS |
6578 | |
6579 | /* | |
39acb4aa | 6580 | * Enable double wide mode when the dot clock |
cf532bb2 | 6581 | * is > 90% of the (display) core speed. |
cf532bb2 | 6582 | */ |
39acb4aa VS |
6583 | if (intel_crtc_supports_double_wide(crtc) && |
6584 | adjusted_mode->crtc_clock > clock_limit) { | |
ad3a4479 | 6585 | clock_limit *= 2; |
cf532bb2 | 6586 | pipe_config->double_wide = true; |
ad3a4479 VS |
6587 | } |
6588 | ||
39acb4aa VS |
6589 | if (adjusted_mode->crtc_clock > clock_limit) { |
6590 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
6591 | adjusted_mode->crtc_clock, clock_limit, | |
6592 | yesno(pipe_config->double_wide)); | |
e29c22c0 | 6593 | return -EINVAL; |
39acb4aa | 6594 | } |
2c07245f | 6595 | } |
89749350 | 6596 | |
1d1d0e27 VS |
6597 | /* |
6598 | * Pipe horizontal size must be even in: | |
6599 | * - DVO ganged mode | |
6600 | * - LVDS dual channel mode | |
6601 | * - Double wide pipe | |
6602 | */ | |
a93e255f | 6603 | if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
6604 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
6605 | pipe_config->pipe_src_w &= ~1; | |
6606 | ||
8693a824 DL |
6607 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6608 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
6609 | */ |
6610 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
aad941d5 | 6611 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) |
e29c22c0 | 6612 | return -EINVAL; |
44f46b42 | 6613 | |
f5adf94e | 6614 | if (HAS_IPS(dev)) |
a43f6e0f DV |
6615 | hsw_compute_ips_config(crtc, pipe_config); |
6616 | ||
877d48d5 | 6617 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 6618 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 6619 | |
cf5a15be | 6620 | return 0; |
79e53945 JB |
6621 | } |
6622 | ||
1652d19e VS |
6623 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
6624 | { | |
6625 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6626 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
6627 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6628 | uint32_t linkrate; | |
6629 | ||
414355a7 | 6630 | if (!(lcpll1 & LCPLL_PLL_ENABLE)) |
1652d19e | 6631 | return 24000; /* 24MHz is the cd freq with NSSC ref */ |
1652d19e VS |
6632 | |
6633 | if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) | |
6634 | return 540000; | |
6635 | ||
6636 | linkrate = (I915_READ(DPLL_CTRL1) & | |
71cd8423 | 6637 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; |
1652d19e | 6638 | |
71cd8423 DL |
6639 | if (linkrate == DPLL_CTRL1_LINK_RATE_2160 || |
6640 | linkrate == DPLL_CTRL1_LINK_RATE_1080) { | |
1652d19e VS |
6641 | /* vco 8640 */ |
6642 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6643 | case CDCLK_FREQ_450_432: | |
6644 | return 432000; | |
6645 | case CDCLK_FREQ_337_308: | |
6646 | return 308570; | |
6647 | case CDCLK_FREQ_675_617: | |
6648 | return 617140; | |
6649 | default: | |
6650 | WARN(1, "Unknown cd freq selection\n"); | |
6651 | } | |
6652 | } else { | |
6653 | /* vco 8100 */ | |
6654 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6655 | case CDCLK_FREQ_450_432: | |
6656 | return 450000; | |
6657 | case CDCLK_FREQ_337_308: | |
6658 | return 337500; | |
6659 | case CDCLK_FREQ_675_617: | |
6660 | return 675000; | |
6661 | default: | |
6662 | WARN(1, "Unknown cd freq selection\n"); | |
6663 | } | |
6664 | } | |
6665 | ||
6666 | /* error case, do as if DPLL0 isn't enabled */ | |
6667 | return 24000; | |
6668 | } | |
6669 | ||
acd3f3d3 BP |
6670 | static int broxton_get_display_clock_speed(struct drm_device *dev) |
6671 | { | |
6672 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6673 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6674 | uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; | |
6675 | uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE); | |
6676 | int cdclk; | |
6677 | ||
6678 | if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE)) | |
6679 | return 19200; | |
6680 | ||
6681 | cdclk = 19200 * pll_ratio / 2; | |
6682 | ||
6683 | switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) { | |
6684 | case BXT_CDCLK_CD2X_DIV_SEL_1: | |
6685 | return cdclk; /* 576MHz or 624MHz */ | |
6686 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: | |
6687 | return cdclk * 2 / 3; /* 384MHz */ | |
6688 | case BXT_CDCLK_CD2X_DIV_SEL_2: | |
6689 | return cdclk / 2; /* 288MHz */ | |
6690 | case BXT_CDCLK_CD2X_DIV_SEL_4: | |
6691 | return cdclk / 4; /* 144MHz */ | |
6692 | } | |
6693 | ||
6694 | /* error case, do as if DE PLL isn't enabled */ | |
6695 | return 19200; | |
6696 | } | |
6697 | ||
1652d19e VS |
6698 | static int broadwell_get_display_clock_speed(struct drm_device *dev) |
6699 | { | |
6700 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6701 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6702 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6703 | ||
6704 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6705 | return 800000; | |
6706 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6707 | return 450000; | |
6708 | else if (freq == LCPLL_CLK_FREQ_450) | |
6709 | return 450000; | |
6710 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
6711 | return 540000; | |
6712 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
6713 | return 337500; | |
6714 | else | |
6715 | return 675000; | |
6716 | } | |
6717 | ||
6718 | static int haswell_get_display_clock_speed(struct drm_device *dev) | |
6719 | { | |
6720 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6721 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6722 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6723 | ||
6724 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6725 | return 800000; | |
6726 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6727 | return 450000; | |
6728 | else if (freq == LCPLL_CLK_FREQ_450) | |
6729 | return 450000; | |
6730 | else if (IS_HSW_ULT(dev)) | |
6731 | return 337500; | |
6732 | else | |
6733 | return 540000; | |
79e53945 JB |
6734 | } |
6735 | ||
25eb05fc JB |
6736 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
6737 | { | |
bfa7df01 VS |
6738 | return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk", |
6739 | CCK_DISPLAY_CLOCK_CONTROL); | |
25eb05fc JB |
6740 | } |
6741 | ||
b37a6434 VS |
6742 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
6743 | { | |
6744 | return 450000; | |
6745 | } | |
6746 | ||
e70236a8 JB |
6747 | static int i945_get_display_clock_speed(struct drm_device *dev) |
6748 | { | |
6749 | return 400000; | |
6750 | } | |
79e53945 | 6751 | |
e70236a8 | 6752 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 6753 | { |
e907f170 | 6754 | return 333333; |
e70236a8 | 6755 | } |
79e53945 | 6756 | |
e70236a8 JB |
6757 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
6758 | { | |
6759 | return 200000; | |
6760 | } | |
79e53945 | 6761 | |
257a7ffc DV |
6762 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
6763 | { | |
6764 | u16 gcfgc = 0; | |
6765 | ||
6766 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
6767 | ||
6768 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6769 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 6770 | return 266667; |
257a7ffc | 6771 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 6772 | return 333333; |
257a7ffc | 6773 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 6774 | return 444444; |
257a7ffc DV |
6775 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
6776 | return 200000; | |
6777 | default: | |
6778 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
6779 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 6780 | return 133333; |
257a7ffc | 6781 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 6782 | return 166667; |
257a7ffc DV |
6783 | } |
6784 | } | |
6785 | ||
e70236a8 JB |
6786 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
6787 | { | |
6788 | u16 gcfgc = 0; | |
79e53945 | 6789 | |
e70236a8 JB |
6790 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
6791 | ||
6792 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 6793 | return 133333; |
e70236a8 JB |
6794 | else { |
6795 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6796 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 6797 | return 333333; |
e70236a8 JB |
6798 | default: |
6799 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
6800 | return 190000; | |
79e53945 | 6801 | } |
e70236a8 JB |
6802 | } |
6803 | } | |
6804 | ||
6805 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
6806 | { | |
e907f170 | 6807 | return 266667; |
e70236a8 JB |
6808 | } |
6809 | ||
1b1d2716 | 6810 | static int i85x_get_display_clock_speed(struct drm_device *dev) |
e70236a8 JB |
6811 | { |
6812 | u16 hpllcc = 0; | |
1b1d2716 | 6813 | |
65cd2b3f VS |
6814 | /* |
6815 | * 852GM/852GMV only supports 133 MHz and the HPLLCC | |
6816 | * encoding is different :( | |
6817 | * FIXME is this the right way to detect 852GM/852GMV? | |
6818 | */ | |
6819 | if (dev->pdev->revision == 0x1) | |
6820 | return 133333; | |
6821 | ||
1b1d2716 VS |
6822 | pci_bus_read_config_word(dev->pdev->bus, |
6823 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); | |
6824 | ||
e70236a8 JB |
6825 | /* Assume that the hardware is in the high speed state. This |
6826 | * should be the default. | |
6827 | */ | |
6828 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
6829 | case GC_CLOCK_133_200: | |
1b1d2716 | 6830 | case GC_CLOCK_133_200_2: |
e70236a8 JB |
6831 | case GC_CLOCK_100_200: |
6832 | return 200000; | |
6833 | case GC_CLOCK_166_250: | |
6834 | return 250000; | |
6835 | case GC_CLOCK_100_133: | |
e907f170 | 6836 | return 133333; |
1b1d2716 VS |
6837 | case GC_CLOCK_133_266: |
6838 | case GC_CLOCK_133_266_2: | |
6839 | case GC_CLOCK_166_266: | |
6840 | return 266667; | |
e70236a8 | 6841 | } |
79e53945 | 6842 | |
e70236a8 JB |
6843 | /* Shouldn't happen */ |
6844 | return 0; | |
6845 | } | |
79e53945 | 6846 | |
e70236a8 JB |
6847 | static int i830_get_display_clock_speed(struct drm_device *dev) |
6848 | { | |
e907f170 | 6849 | return 133333; |
79e53945 JB |
6850 | } |
6851 | ||
34edce2f VS |
6852 | static unsigned int intel_hpll_vco(struct drm_device *dev) |
6853 | { | |
6854 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6855 | static const unsigned int blb_vco[8] = { | |
6856 | [0] = 3200000, | |
6857 | [1] = 4000000, | |
6858 | [2] = 5333333, | |
6859 | [3] = 4800000, | |
6860 | [4] = 6400000, | |
6861 | }; | |
6862 | static const unsigned int pnv_vco[8] = { | |
6863 | [0] = 3200000, | |
6864 | [1] = 4000000, | |
6865 | [2] = 5333333, | |
6866 | [3] = 4800000, | |
6867 | [4] = 2666667, | |
6868 | }; | |
6869 | static const unsigned int cl_vco[8] = { | |
6870 | [0] = 3200000, | |
6871 | [1] = 4000000, | |
6872 | [2] = 5333333, | |
6873 | [3] = 6400000, | |
6874 | [4] = 3333333, | |
6875 | [5] = 3566667, | |
6876 | [6] = 4266667, | |
6877 | }; | |
6878 | static const unsigned int elk_vco[8] = { | |
6879 | [0] = 3200000, | |
6880 | [1] = 4000000, | |
6881 | [2] = 5333333, | |
6882 | [3] = 4800000, | |
6883 | }; | |
6884 | static const unsigned int ctg_vco[8] = { | |
6885 | [0] = 3200000, | |
6886 | [1] = 4000000, | |
6887 | [2] = 5333333, | |
6888 | [3] = 6400000, | |
6889 | [4] = 2666667, | |
6890 | [5] = 4266667, | |
6891 | }; | |
6892 | const unsigned int *vco_table; | |
6893 | unsigned int vco; | |
6894 | uint8_t tmp = 0; | |
6895 | ||
6896 | /* FIXME other chipsets? */ | |
6897 | if (IS_GM45(dev)) | |
6898 | vco_table = ctg_vco; | |
6899 | else if (IS_G4X(dev)) | |
6900 | vco_table = elk_vco; | |
6901 | else if (IS_CRESTLINE(dev)) | |
6902 | vco_table = cl_vco; | |
6903 | else if (IS_PINEVIEW(dev)) | |
6904 | vco_table = pnv_vco; | |
6905 | else if (IS_G33(dev)) | |
6906 | vco_table = blb_vco; | |
6907 | else | |
6908 | return 0; | |
6909 | ||
6910 | tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO); | |
6911 | ||
6912 | vco = vco_table[tmp & 0x7]; | |
6913 | if (vco == 0) | |
6914 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); | |
6915 | else | |
6916 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); | |
6917 | ||
6918 | return vco; | |
6919 | } | |
6920 | ||
6921 | static int gm45_get_display_clock_speed(struct drm_device *dev) | |
6922 | { | |
6923 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
6924 | uint16_t tmp = 0; | |
6925 | ||
6926 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
6927 | ||
6928 | cdclk_sel = (tmp >> 12) & 0x1; | |
6929 | ||
6930 | switch (vco) { | |
6931 | case 2666667: | |
6932 | case 4000000: | |
6933 | case 5333333: | |
6934 | return cdclk_sel ? 333333 : 222222; | |
6935 | case 3200000: | |
6936 | return cdclk_sel ? 320000 : 228571; | |
6937 | default: | |
6938 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); | |
6939 | return 222222; | |
6940 | } | |
6941 | } | |
6942 | ||
6943 | static int i965gm_get_display_clock_speed(struct drm_device *dev) | |
6944 | { | |
6945 | static const uint8_t div_3200[] = { 16, 10, 8 }; | |
6946 | static const uint8_t div_4000[] = { 20, 12, 10 }; | |
6947 | static const uint8_t div_5333[] = { 24, 16, 14 }; | |
6948 | const uint8_t *div_table; | |
6949 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
6950 | uint16_t tmp = 0; | |
6951 | ||
6952 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
6953 | ||
6954 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; | |
6955 | ||
6956 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
6957 | goto fail; | |
6958 | ||
6959 | switch (vco) { | |
6960 | case 3200000: | |
6961 | div_table = div_3200; | |
6962 | break; | |
6963 | case 4000000: | |
6964 | div_table = div_4000; | |
6965 | break; | |
6966 | case 5333333: | |
6967 | div_table = div_5333; | |
6968 | break; | |
6969 | default: | |
6970 | goto fail; | |
6971 | } | |
6972 | ||
6973 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
6974 | ||
caf4e252 | 6975 | fail: |
34edce2f VS |
6976 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); |
6977 | return 200000; | |
6978 | } | |
6979 | ||
6980 | static int g33_get_display_clock_speed(struct drm_device *dev) | |
6981 | { | |
6982 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; | |
6983 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; | |
6984 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; | |
6985 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; | |
6986 | const uint8_t *div_table; | |
6987 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
6988 | uint16_t tmp = 0; | |
6989 | ||
6990 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
6991 | ||
6992 | cdclk_sel = (tmp >> 4) & 0x7; | |
6993 | ||
6994 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
6995 | goto fail; | |
6996 | ||
6997 | switch (vco) { | |
6998 | case 3200000: | |
6999 | div_table = div_3200; | |
7000 | break; | |
7001 | case 4000000: | |
7002 | div_table = div_4000; | |
7003 | break; | |
7004 | case 4800000: | |
7005 | div_table = div_4800; | |
7006 | break; | |
7007 | case 5333333: | |
7008 | div_table = div_5333; | |
7009 | break; | |
7010 | default: | |
7011 | goto fail; | |
7012 | } | |
7013 | ||
7014 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7015 | ||
caf4e252 | 7016 | fail: |
34edce2f VS |
7017 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); |
7018 | return 190476; | |
7019 | } | |
7020 | ||
2c07245f | 7021 | static void |
a65851af | 7022 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 7023 | { |
a65851af VS |
7024 | while (*num > DATA_LINK_M_N_MASK || |
7025 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
7026 | *num >>= 1; |
7027 | *den >>= 1; | |
7028 | } | |
7029 | } | |
7030 | ||
a65851af VS |
7031 | static void compute_m_n(unsigned int m, unsigned int n, |
7032 | uint32_t *ret_m, uint32_t *ret_n) | |
7033 | { | |
7034 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
7035 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
7036 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
7037 | } | |
7038 | ||
e69d0bc1 DV |
7039 | void |
7040 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
7041 | int pixel_clock, int link_clock, | |
7042 | struct intel_link_m_n *m_n) | |
2c07245f | 7043 | { |
e69d0bc1 | 7044 | m_n->tu = 64; |
a65851af VS |
7045 | |
7046 | compute_m_n(bits_per_pixel * pixel_clock, | |
7047 | link_clock * nlanes * 8, | |
7048 | &m_n->gmch_m, &m_n->gmch_n); | |
7049 | ||
7050 | compute_m_n(pixel_clock, link_clock, | |
7051 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
7052 | } |
7053 | ||
a7615030 CW |
7054 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
7055 | { | |
d330a953 JN |
7056 | if (i915.panel_use_ssc >= 0) |
7057 | return i915.panel_use_ssc != 0; | |
41aa3448 | 7058 | return dev_priv->vbt.lvds_use_ssc |
435793df | 7059 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
7060 | } |
7061 | ||
a93e255f ACO |
7062 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
7063 | int num_connectors) | |
c65d77d8 | 7064 | { |
a93e255f | 7065 | struct drm_device *dev = crtc_state->base.crtc->dev; |
c65d77d8 JB |
7066 | struct drm_i915_private *dev_priv = dev->dev_private; |
7067 | int refclk; | |
7068 | ||
a93e255f ACO |
7069 | WARN_ON(!crtc_state->base.state); |
7070 | ||
666a4537 | 7071 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) { |
9a0ea498 | 7072 | refclk = 100000; |
a93e255f | 7073 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 7074 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
7075 | refclk = dev_priv->vbt.lvds_ssc_freq; |
7076 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
7077 | } else if (!IS_GEN2(dev)) { |
7078 | refclk = 96000; | |
7079 | } else { | |
7080 | refclk = 48000; | |
7081 | } | |
7082 | ||
7083 | return refclk; | |
7084 | } | |
7085 | ||
7429e9d4 | 7086 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 7087 | { |
7df00d7a | 7088 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 7089 | } |
f47709a9 | 7090 | |
7429e9d4 DV |
7091 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
7092 | { | |
7093 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
7094 | } |
7095 | ||
f47709a9 | 7096 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 7097 | struct intel_crtc_state *crtc_state, |
a7516a05 JB |
7098 | intel_clock_t *reduced_clock) |
7099 | { | |
f47709a9 | 7100 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
7101 | u32 fp, fp2 = 0; |
7102 | ||
7103 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 7104 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7105 | if (reduced_clock) |
7429e9d4 | 7106 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 7107 | } else { |
190f68c5 | 7108 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7109 | if (reduced_clock) |
7429e9d4 | 7110 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
7111 | } |
7112 | ||
190f68c5 | 7113 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 7114 | |
f47709a9 | 7115 | crtc->lowfreq_avail = false; |
a93e255f | 7116 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 7117 | reduced_clock) { |
190f68c5 | 7118 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 7119 | crtc->lowfreq_avail = true; |
a7516a05 | 7120 | } else { |
190f68c5 | 7121 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
7122 | } |
7123 | } | |
7124 | ||
5e69f97f CML |
7125 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
7126 | pipe) | |
89b667f8 JB |
7127 | { |
7128 | u32 reg_val; | |
7129 | ||
7130 | /* | |
7131 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
7132 | * and set it to a reasonable value instead. | |
7133 | */ | |
ab3c759a | 7134 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
7135 | reg_val &= 0xffffff00; |
7136 | reg_val |= 0x00000030; | |
ab3c759a | 7137 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7138 | |
ab3c759a | 7139 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7140 | reg_val &= 0x8cffffff; |
7141 | reg_val = 0x8c000000; | |
ab3c759a | 7142 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 7143 | |
ab3c759a | 7144 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 7145 | reg_val &= 0xffffff00; |
ab3c759a | 7146 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7147 | |
ab3c759a | 7148 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7149 | reg_val &= 0x00ffffff; |
7150 | reg_val |= 0xb0000000; | |
ab3c759a | 7151 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
7152 | } |
7153 | ||
b551842d DV |
7154 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
7155 | struct intel_link_m_n *m_n) | |
7156 | { | |
7157 | struct drm_device *dev = crtc->base.dev; | |
7158 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7159 | int pipe = crtc->pipe; | |
7160 | ||
e3b95f1e DV |
7161 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7162 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
7163 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
7164 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
7165 | } |
7166 | ||
7167 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
7168 | struct intel_link_m_n *m_n, |
7169 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
7170 | { |
7171 | struct drm_device *dev = crtc->base.dev; | |
7172 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7173 | int pipe = crtc->pipe; | |
6e3c9717 | 7174 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
7175 | |
7176 | if (INTEL_INFO(dev)->gen >= 5) { | |
7177 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
7178 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
7179 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
7180 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
7181 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
7182 | * for gen < 8) and if DRRS is supported (to make sure the | |
7183 | * registers are not unnecessarily accessed). | |
7184 | */ | |
44395bfe | 7185 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 7186 | crtc->config->has_drrs) { |
f769cd24 VK |
7187 | I915_WRITE(PIPE_DATA_M2(transcoder), |
7188 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
7189 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
7190 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
7191 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
7192 | } | |
b551842d | 7193 | } else { |
e3b95f1e DV |
7194 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7195 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
7196 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
7197 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
7198 | } |
7199 | } | |
7200 | ||
fe3cd48d | 7201 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 7202 | { |
fe3cd48d R |
7203 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
7204 | ||
7205 | if (m_n == M1_N1) { | |
7206 | dp_m_n = &crtc->config->dp_m_n; | |
7207 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
7208 | } else if (m_n == M2_N2) { | |
7209 | ||
7210 | /* | |
7211 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
7212 | * needs to be programmed into M1_N1. | |
7213 | */ | |
7214 | dp_m_n = &crtc->config->dp_m2_n2; | |
7215 | } else { | |
7216 | DRM_ERROR("Unsupported divider value\n"); | |
7217 | return; | |
7218 | } | |
7219 | ||
6e3c9717 ACO |
7220 | if (crtc->config->has_pch_encoder) |
7221 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 7222 | else |
fe3cd48d | 7223 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
7224 | } |
7225 | ||
251ac862 DV |
7226 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
7227 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 DV |
7228 | { |
7229 | u32 dpll, dpll_md; | |
7230 | ||
7231 | /* | |
7232 | * Enable DPIO clock input. We should never disable the reference | |
7233 | * clock for pipe B, since VGA hotplug / manual detection depends | |
7234 | * on it. | |
7235 | */ | |
60bfe44f VS |
7236 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV | |
7237 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV; | |
bdd4b6a6 DV |
7238 | /* We should never disable this, set it here for state tracking */ |
7239 | if (crtc->pipe == PIPE_B) | |
7240 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
7241 | dpll |= DPLL_VCO_ENABLE; | |
d288f65f | 7242 | pipe_config->dpll_hw_state.dpll = dpll; |
bdd4b6a6 | 7243 | |
d288f65f | 7244 | dpll_md = (pipe_config->pixel_multiplier - 1) |
bdd4b6a6 | 7245 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
d288f65f | 7246 | pipe_config->dpll_hw_state.dpll_md = dpll_md; |
bdd4b6a6 DV |
7247 | } |
7248 | ||
d288f65f | 7249 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7250 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 7251 | { |
f47709a9 | 7252 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 7253 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 7254 | int pipe = crtc->pipe; |
bdd4b6a6 | 7255 | u32 mdiv; |
a0c4da24 | 7256 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 7257 | u32 coreclk, reg_val; |
a0c4da24 | 7258 | |
a580516d | 7259 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 7260 | |
d288f65f VS |
7261 | bestn = pipe_config->dpll.n; |
7262 | bestm1 = pipe_config->dpll.m1; | |
7263 | bestm2 = pipe_config->dpll.m2; | |
7264 | bestp1 = pipe_config->dpll.p1; | |
7265 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 7266 | |
89b667f8 JB |
7267 | /* See eDP HDMI DPIO driver vbios notes doc */ |
7268 | ||
7269 | /* PLL B needs special handling */ | |
bdd4b6a6 | 7270 | if (pipe == PIPE_B) |
5e69f97f | 7271 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
7272 | |
7273 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 7274 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
7275 | |
7276 | /* Disable target IRef on PLL */ | |
ab3c759a | 7277 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 7278 | reg_val &= 0x00ffffff; |
ab3c759a | 7279 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
7280 | |
7281 | /* Disable fast lock */ | |
ab3c759a | 7282 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
7283 | |
7284 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
7285 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
7286 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
7287 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 7288 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
7289 | |
7290 | /* | |
7291 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
7292 | * but we don't support that). | |
7293 | * Note: don't use the DAC post divider as it seems unstable. | |
7294 | */ | |
7295 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 7296 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7297 | |
a0c4da24 | 7298 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 7299 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7300 | |
89b667f8 | 7301 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 7302 | if (pipe_config->port_clock == 162000 || |
409ee761 ACO |
7303 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || |
7304 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 7305 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 7306 | 0x009f0003); |
89b667f8 | 7307 | else |
ab3c759a | 7308 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
7309 | 0x00d0000f); |
7310 | ||
681a8504 | 7311 | if (pipe_config->has_dp_encoder) { |
89b667f8 | 7312 | /* Use SSC source */ |
bdd4b6a6 | 7313 | if (pipe == PIPE_A) |
ab3c759a | 7314 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7315 | 0x0df40000); |
7316 | else | |
ab3c759a | 7317 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7318 | 0x0df70000); |
7319 | } else { /* HDMI or VGA */ | |
7320 | /* Use bend source */ | |
bdd4b6a6 | 7321 | if (pipe == PIPE_A) |
ab3c759a | 7322 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7323 | 0x0df70000); |
7324 | else | |
ab3c759a | 7325 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7326 | 0x0df40000); |
7327 | } | |
a0c4da24 | 7328 | |
ab3c759a | 7329 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 7330 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
409ee761 ACO |
7331 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
7332 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) | |
89b667f8 | 7333 | coreclk |= 0x01000000; |
ab3c759a | 7334 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 7335 | |
ab3c759a | 7336 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 7337 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
7338 | } |
7339 | ||
251ac862 DV |
7340 | static void chv_compute_dpll(struct intel_crtc *crtc, |
7341 | struct intel_crtc_state *pipe_config) | |
1ae0d137 | 7342 | { |
60bfe44f VS |
7343 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | |
7344 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | | |
1ae0d137 VS |
7345 | DPLL_VCO_ENABLE; |
7346 | if (crtc->pipe != PIPE_A) | |
d288f65f | 7347 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
1ae0d137 | 7348 | |
d288f65f VS |
7349 | pipe_config->dpll_hw_state.dpll_md = |
7350 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
1ae0d137 VS |
7351 | } |
7352 | ||
d288f65f | 7353 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7354 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
7355 | { |
7356 | struct drm_device *dev = crtc->base.dev; | |
7357 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7358 | int pipe = crtc->pipe; | |
f0f59a00 | 7359 | i915_reg_t dpll_reg = DPLL(crtc->pipe); |
9d556c99 | 7360 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9cbe40c1 | 7361 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 7362 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 7363 | u32 dpio_val; |
9cbe40c1 | 7364 | int vco; |
9d556c99 | 7365 | |
d288f65f VS |
7366 | bestn = pipe_config->dpll.n; |
7367 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
7368 | bestm1 = pipe_config->dpll.m1; | |
7369 | bestm2 = pipe_config->dpll.m2 >> 22; | |
7370 | bestp1 = pipe_config->dpll.p1; | |
7371 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 7372 | vco = pipe_config->dpll.vco; |
a945ce7e | 7373 | dpio_val = 0; |
9cbe40c1 | 7374 | loopfilter = 0; |
9d556c99 CML |
7375 | |
7376 | /* | |
7377 | * Enable Refclk and SSC | |
7378 | */ | |
a11b0703 | 7379 | I915_WRITE(dpll_reg, |
d288f65f | 7380 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
a11b0703 | 7381 | |
a580516d | 7382 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 7383 | |
9d556c99 CML |
7384 | /* p1 and p2 divider */ |
7385 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
7386 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
7387 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
7388 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
7389 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
7390 | ||
7391 | /* Feedback post-divider - m2 */ | |
7392 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
7393 | ||
7394 | /* Feedback refclk divider - n and m1 */ | |
7395 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
7396 | DPIO_CHV_M1_DIV_BY_2 | | |
7397 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
7398 | ||
7399 | /* M2 fraction division */ | |
25a25dfc | 7400 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
7401 | |
7402 | /* M2 fraction division enable */ | |
a945ce7e VP |
7403 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
7404 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
7405 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
7406 | if (bestm2_frac) | |
7407 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
7408 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 7409 | |
de3a0fde VP |
7410 | /* Program digital lock detect threshold */ |
7411 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
7412 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
7413 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
7414 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
7415 | if (!bestm2_frac) | |
7416 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
7417 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
7418 | ||
9d556c99 | 7419 | /* Loop filter */ |
9cbe40c1 VP |
7420 | if (vco == 5400000) { |
7421 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7422 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
7423 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7424 | tribuf_calcntr = 0x9; | |
7425 | } else if (vco <= 6200000) { | |
7426 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7427 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
7428 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7429 | tribuf_calcntr = 0x9; | |
7430 | } else if (vco <= 6480000) { | |
7431 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7432 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7433 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7434 | tribuf_calcntr = 0x8; | |
7435 | } else { | |
7436 | /* Not supported. Apply the same limits as in the max case */ | |
7437 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7438 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7439 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7440 | tribuf_calcntr = 0; | |
7441 | } | |
9d556c99 CML |
7442 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
7443 | ||
968040b2 | 7444 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
7445 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
7446 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
7447 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
7448 | ||
9d556c99 CML |
7449 | /* AFC Recal */ |
7450 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
7451 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
7452 | DPIO_AFC_RECAL); | |
7453 | ||
a580516d | 7454 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
7455 | } |
7456 | ||
d288f65f VS |
7457 | /** |
7458 | * vlv_force_pll_on - forcibly enable just the PLL | |
7459 | * @dev_priv: i915 private structure | |
7460 | * @pipe: pipe PLL to enable | |
7461 | * @dpll: PLL configuration | |
7462 | * | |
7463 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
7464 | * in cases where we need the PLL enabled even when @pipe is not going to | |
7465 | * be enabled. | |
7466 | */ | |
3f36b937 TU |
7467 | int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, |
7468 | const struct dpll *dpll) | |
d288f65f VS |
7469 | { |
7470 | struct intel_crtc *crtc = | |
7471 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
3f36b937 TU |
7472 | struct intel_crtc_state *pipe_config; |
7473 | ||
7474 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); | |
7475 | if (!pipe_config) | |
7476 | return -ENOMEM; | |
7477 | ||
7478 | pipe_config->base.crtc = &crtc->base; | |
7479 | pipe_config->pixel_multiplier = 1; | |
7480 | pipe_config->dpll = *dpll; | |
d288f65f VS |
7481 | |
7482 | if (IS_CHERRYVIEW(dev)) { | |
3f36b937 TU |
7483 | chv_compute_dpll(crtc, pipe_config); |
7484 | chv_prepare_pll(crtc, pipe_config); | |
7485 | chv_enable_pll(crtc, pipe_config); | |
d288f65f | 7486 | } else { |
3f36b937 TU |
7487 | vlv_compute_dpll(crtc, pipe_config); |
7488 | vlv_prepare_pll(crtc, pipe_config); | |
7489 | vlv_enable_pll(crtc, pipe_config); | |
d288f65f | 7490 | } |
3f36b937 TU |
7491 | |
7492 | kfree(pipe_config); | |
7493 | ||
7494 | return 0; | |
d288f65f VS |
7495 | } |
7496 | ||
7497 | /** | |
7498 | * vlv_force_pll_off - forcibly disable just the PLL | |
7499 | * @dev_priv: i915 private structure | |
7500 | * @pipe: pipe PLL to disable | |
7501 | * | |
7502 | * Disable the PLL for @pipe. To be used in cases where we need | |
7503 | * the PLL enabled even when @pipe is not going to be enabled. | |
7504 | */ | |
7505 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
7506 | { | |
7507 | if (IS_CHERRYVIEW(dev)) | |
7508 | chv_disable_pll(to_i915(dev), pipe); | |
7509 | else | |
7510 | vlv_disable_pll(to_i915(dev), pipe); | |
7511 | } | |
7512 | ||
251ac862 DV |
7513 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
7514 | struct intel_crtc_state *crtc_state, | |
7515 | intel_clock_t *reduced_clock, | |
7516 | int num_connectors) | |
eb1cbe48 | 7517 | { |
f47709a9 | 7518 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7519 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
7520 | u32 dpll; |
7521 | bool is_sdvo; | |
190f68c5 | 7522 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7523 | |
190f68c5 | 7524 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7525 | |
a93e255f ACO |
7526 | is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) || |
7527 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
7528 | |
7529 | dpll = DPLL_VGA_MODE_DIS; | |
7530 | ||
a93e255f | 7531 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
7532 | dpll |= DPLLB_MODE_LVDS; |
7533 | else | |
7534 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 7535 | |
ef1b460d | 7536 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 7537 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 7538 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 7539 | } |
198a037f DV |
7540 | |
7541 | if (is_sdvo) | |
4a33e48d | 7542 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 7543 | |
190f68c5 | 7544 | if (crtc_state->has_dp_encoder) |
4a33e48d | 7545 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
7546 | |
7547 | /* compute bitmask from p1 value */ | |
7548 | if (IS_PINEVIEW(dev)) | |
7549 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
7550 | else { | |
7551 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7552 | if (IS_G4X(dev) && reduced_clock) | |
7553 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
7554 | } | |
7555 | switch (clock->p2) { | |
7556 | case 5: | |
7557 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7558 | break; | |
7559 | case 7: | |
7560 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7561 | break; | |
7562 | case 10: | |
7563 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7564 | break; | |
7565 | case 14: | |
7566 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7567 | break; | |
7568 | } | |
7569 | if (INTEL_INFO(dev)->gen >= 4) | |
7570 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
7571 | ||
190f68c5 | 7572 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 7573 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
a93e255f | 7574 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7575 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7576 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7577 | else | |
7578 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7579 | ||
7580 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7581 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 7582 | |
eb1cbe48 | 7583 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 7584 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7585 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 7586 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
7587 | } |
7588 | } | |
7589 | ||
251ac862 DV |
7590 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
7591 | struct intel_crtc_state *crtc_state, | |
7592 | intel_clock_t *reduced_clock, | |
7593 | int num_connectors) | |
eb1cbe48 | 7594 | { |
f47709a9 | 7595 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7596 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 7597 | u32 dpll; |
190f68c5 | 7598 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7599 | |
190f68c5 | 7600 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7601 | |
eb1cbe48 DV |
7602 | dpll = DPLL_VGA_MODE_DIS; |
7603 | ||
a93e255f | 7604 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
7605 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
7606 | } else { | |
7607 | if (clock->p1 == 2) | |
7608 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
7609 | else | |
7610 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7611 | if (clock->p2 == 4) | |
7612 | dpll |= PLL_P2_DIVIDE_BY_4; | |
7613 | } | |
7614 | ||
a93e255f | 7615 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
7616 | dpll |= DPLL_DVO_2X_MODE; |
7617 | ||
a93e255f | 7618 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7619 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7620 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7621 | else | |
7622 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7623 | ||
7624 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7625 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
7626 | } |
7627 | ||
8a654f3b | 7628 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
7629 | { |
7630 | struct drm_device *dev = intel_crtc->base.dev; | |
7631 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7632 | enum pipe pipe = intel_crtc->pipe; | |
6e3c9717 | 7633 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
7c5f93b0 | 7634 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
7635 | uint32_t crtc_vtotal, crtc_vblank_end; |
7636 | int vsyncshift = 0; | |
4d8a62ea DV |
7637 | |
7638 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
7639 | * the hw state checker will get angry at the mismatch. */ | |
7640 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
7641 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 7642 | |
609aeaca | 7643 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 7644 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
7645 | crtc_vtotal -= 1; |
7646 | crtc_vblank_end -= 1; | |
609aeaca | 7647 | |
409ee761 | 7648 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
7649 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
7650 | else | |
7651 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
7652 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
7653 | if (vsyncshift < 0) |
7654 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
7655 | } |
7656 | ||
7657 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 7658 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 7659 | |
fe2b8f9d | 7660 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
7661 | (adjusted_mode->crtc_hdisplay - 1) | |
7662 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 7663 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
7664 | (adjusted_mode->crtc_hblank_start - 1) | |
7665 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 7666 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
7667 | (adjusted_mode->crtc_hsync_start - 1) | |
7668 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
7669 | ||
fe2b8f9d | 7670 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 7671 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 7672 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 7673 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 7674 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 7675 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 7676 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
7677 | (adjusted_mode->crtc_vsync_start - 1) | |
7678 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
7679 | ||
b5e508d4 PZ |
7680 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
7681 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
7682 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
7683 | * bits. */ | |
7684 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
7685 | (pipe == PIPE_B || pipe == PIPE_C)) | |
7686 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
7687 | ||
bc58be60 JN |
7688 | } |
7689 | ||
7690 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc) | |
7691 | { | |
7692 | struct drm_device *dev = intel_crtc->base.dev; | |
7693 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7694 | enum pipe pipe = intel_crtc->pipe; | |
7695 | ||
b0e77b9c PZ |
7696 | /* pipesrc controls the size that is scaled from, which should |
7697 | * always be the user's requested size. | |
7698 | */ | |
7699 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
7700 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
7701 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
7702 | } |
7703 | ||
1bd1bd80 | 7704 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 7705 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
7706 | { |
7707 | struct drm_device *dev = crtc->base.dev; | |
7708 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7709 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
7710 | uint32_t tmp; | |
7711 | ||
7712 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7713 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
7714 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7715 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
7716 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
7717 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7718 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
7719 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
7720 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7721 | |
7722 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7723 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
7724 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7725 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
7726 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
7727 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7728 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
7729 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
7730 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7731 | |
7732 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
7733 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
7734 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
7735 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 | 7736 | } |
bc58be60 JN |
7737 | } |
7738 | ||
7739 | static void intel_get_pipe_src_size(struct intel_crtc *crtc, | |
7740 | struct intel_crtc_state *pipe_config) | |
7741 | { | |
7742 | struct drm_device *dev = crtc->base.dev; | |
7743 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7744 | u32 tmp; | |
1bd1bd80 DV |
7745 | |
7746 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
7747 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
7748 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
7749 | ||
2d112de7 ACO |
7750 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
7751 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
7752 | } |
7753 | ||
f6a83288 | 7754 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 7755 | struct intel_crtc_state *pipe_config) |
babea61d | 7756 | { |
2d112de7 ACO |
7757 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
7758 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
7759 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
7760 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 7761 | |
2d112de7 ACO |
7762 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
7763 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
7764 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7765 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 7766 | |
2d112de7 | 7767 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 7768 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 7769 | |
2d112de7 ACO |
7770 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
7771 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
cd13f5ab ML |
7772 | |
7773 | mode->hsync = drm_mode_hsync(mode); | |
7774 | mode->vrefresh = drm_mode_vrefresh(mode); | |
7775 | drm_mode_set_name(mode); | |
babea61d JB |
7776 | } |
7777 | ||
84b046f3 DV |
7778 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7779 | { | |
7780 | struct drm_device *dev = intel_crtc->base.dev; | |
7781 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7782 | uint32_t pipeconf; | |
7783 | ||
9f11a9e4 | 7784 | pipeconf = 0; |
84b046f3 | 7785 | |
b6b5d049 VS |
7786 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
7787 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
7788 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 7789 | |
6e3c9717 | 7790 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7791 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7792 | |
ff9ce46e | 7793 | /* only g4x and later have fancy bpc/dither controls */ |
666a4537 | 7794 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
ff9ce46e | 7795 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 7796 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 7797 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 7798 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 7799 | |
6e3c9717 | 7800 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
7801 | case 18: |
7802 | pipeconf |= PIPECONF_6BPC; | |
7803 | break; | |
7804 | case 24: | |
7805 | pipeconf |= PIPECONF_8BPC; | |
7806 | break; | |
7807 | case 30: | |
7808 | pipeconf |= PIPECONF_10BPC; | |
7809 | break; | |
7810 | default: | |
7811 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7812 | BUG(); | |
84b046f3 DV |
7813 | } |
7814 | } | |
7815 | ||
7816 | if (HAS_PIPE_CXSR(dev)) { | |
7817 | if (intel_crtc->lowfreq_avail) { | |
7818 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
7819 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
7820 | } else { | |
7821 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
7822 | } |
7823 | } | |
7824 | ||
6e3c9717 | 7825 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 7826 | if (INTEL_INFO(dev)->gen < 4 || |
409ee761 | 7827 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
7828 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
7829 | else | |
7830 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7831 | } else | |
84b046f3 DV |
7832 | pipeconf |= PIPECONF_PROGRESSIVE; |
7833 | ||
666a4537 WB |
7834 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
7835 | intel_crtc->config->limited_color_range) | |
9f11a9e4 | 7836 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 7837 | |
84b046f3 DV |
7838 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7839 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7840 | } | |
7841 | ||
190f68c5 ACO |
7842 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
7843 | struct intel_crtc_state *crtc_state) | |
79e53945 | 7844 | { |
c7653199 | 7845 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 7846 | struct drm_i915_private *dev_priv = dev->dev_private; |
c751ce4f | 7847 | int refclk, num_connectors = 0; |
c329a4ec DV |
7848 | intel_clock_t clock; |
7849 | bool ok; | |
d4906093 | 7850 | const intel_limit_t *limit; |
55bb9992 | 7851 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 7852 | struct drm_connector *connector; |
55bb9992 ACO |
7853 | struct drm_connector_state *connector_state; |
7854 | int i; | |
79e53945 | 7855 | |
dd3cd74a ACO |
7856 | memset(&crtc_state->dpll_hw_state, 0, |
7857 | sizeof(crtc_state->dpll_hw_state)); | |
7858 | ||
a65347ba JN |
7859 | if (crtc_state->has_dsi_encoder) |
7860 | return 0; | |
43565a06 | 7861 | |
a65347ba JN |
7862 | for_each_connector_in_state(state, connector, connector_state, i) { |
7863 | if (connector_state->crtc == &crtc->base) | |
7864 | num_connectors++; | |
79e53945 JB |
7865 | } |
7866 | ||
190f68c5 | 7867 | if (!crtc_state->clock_set) { |
a93e255f | 7868 | refclk = i9xx_get_refclk(crtc_state, num_connectors); |
79e53945 | 7869 | |
e9fd1c02 JN |
7870 | /* |
7871 | * Returns a set of divisors for the desired target clock with | |
7872 | * the given refclk, or FALSE. The returned values represent | |
7873 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
7874 | * 2) / p1 / p2. | |
7875 | */ | |
a93e255f ACO |
7876 | limit = intel_limit(crtc_state, refclk); |
7877 | ok = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 7878 | crtc_state->port_clock, |
e9fd1c02 | 7879 | refclk, NULL, &clock); |
f2335330 | 7880 | if (!ok) { |
e9fd1c02 JN |
7881 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
7882 | return -EINVAL; | |
7883 | } | |
79e53945 | 7884 | |
f2335330 | 7885 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
7886 | crtc_state->dpll.n = clock.n; |
7887 | crtc_state->dpll.m1 = clock.m1; | |
7888 | crtc_state->dpll.m2 = clock.m2; | |
7889 | crtc_state->dpll.p1 = clock.p1; | |
7890 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 7891 | } |
7026d4ac | 7892 | |
e9fd1c02 | 7893 | if (IS_GEN2(dev)) { |
c329a4ec | 7894 | i8xx_compute_dpll(crtc, crtc_state, NULL, |
251ac862 | 7895 | num_connectors); |
9d556c99 | 7896 | } else if (IS_CHERRYVIEW(dev)) { |
251ac862 | 7897 | chv_compute_dpll(crtc, crtc_state); |
e9fd1c02 | 7898 | } else if (IS_VALLEYVIEW(dev)) { |
251ac862 | 7899 | vlv_compute_dpll(crtc, crtc_state); |
e9fd1c02 | 7900 | } else { |
c329a4ec | 7901 | i9xx_compute_dpll(crtc, crtc_state, NULL, |
251ac862 | 7902 | num_connectors); |
e9fd1c02 | 7903 | } |
79e53945 | 7904 | |
c8f7a0db | 7905 | return 0; |
f564048e EA |
7906 | } |
7907 | ||
2fa2fe9a | 7908 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 7909 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
7910 | { |
7911 | struct drm_device *dev = crtc->base.dev; | |
7912 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7913 | uint32_t tmp; | |
7914 | ||
dc9e7dec VS |
7915 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
7916 | return; | |
7917 | ||
2fa2fe9a | 7918 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
7919 | if (!(tmp & PFIT_ENABLE)) |
7920 | return; | |
2fa2fe9a | 7921 | |
06922821 | 7922 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
7923 | if (INTEL_INFO(dev)->gen < 4) { |
7924 | if (crtc->pipe != PIPE_B) | |
7925 | return; | |
2fa2fe9a DV |
7926 | } else { |
7927 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
7928 | return; | |
7929 | } | |
7930 | ||
06922821 | 7931 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
7932 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
7933 | if (INTEL_INFO(dev)->gen < 5) | |
7934 | pipe_config->gmch_pfit.lvds_border_bits = | |
7935 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
7936 | } | |
7937 | ||
acbec814 | 7938 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7939 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
7940 | { |
7941 | struct drm_device *dev = crtc->base.dev; | |
7942 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7943 | int pipe = pipe_config->cpu_transcoder; | |
7944 | intel_clock_t clock; | |
7945 | u32 mdiv; | |
662c6ecb | 7946 | int refclk = 100000; |
acbec814 | 7947 | |
f573de5a SK |
7948 | /* In case of MIPI DPLL will not even be used */ |
7949 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) | |
7950 | return; | |
7951 | ||
a580516d | 7952 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 7953 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 7954 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
7955 | |
7956 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
7957 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
7958 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
7959 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
7960 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
7961 | ||
dccbea3b | 7962 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
7963 | } |
7964 | ||
5724dbd1 DL |
7965 | static void |
7966 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
7967 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
7968 | { |
7969 | struct drm_device *dev = crtc->base.dev; | |
7970 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7971 | u32 val, base, offset; | |
7972 | int pipe = crtc->pipe, plane = crtc->plane; | |
7973 | int fourcc, pixel_format; | |
6761dd31 | 7974 | unsigned int aligned_height; |
b113d5ee | 7975 | struct drm_framebuffer *fb; |
1b842c89 | 7976 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 7977 | |
42a7b088 DL |
7978 | val = I915_READ(DSPCNTR(plane)); |
7979 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
7980 | return; | |
7981 | ||
d9806c9f | 7982 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 7983 | if (!intel_fb) { |
1ad292b5 JB |
7984 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7985 | return; | |
7986 | } | |
7987 | ||
1b842c89 DL |
7988 | fb = &intel_fb->base; |
7989 | ||
18c5247e DV |
7990 | if (INTEL_INFO(dev)->gen >= 4) { |
7991 | if (val & DISPPLANE_TILED) { | |
49af449b | 7992 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
7993 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
7994 | } | |
7995 | } | |
1ad292b5 JB |
7996 | |
7997 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 7998 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
7999 | fb->pixel_format = fourcc; |
8000 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
8001 | |
8002 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 8003 | if (plane_config->tiling) |
1ad292b5 JB |
8004 | offset = I915_READ(DSPTILEOFF(plane)); |
8005 | else | |
8006 | offset = I915_READ(DSPLINOFF(plane)); | |
8007 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
8008 | } else { | |
8009 | base = I915_READ(DSPADDR(plane)); | |
8010 | } | |
8011 | plane_config->base = base; | |
8012 | ||
8013 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8014 | fb->width = ((val >> 16) & 0xfff) + 1; |
8015 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
8016 | |
8017 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8018 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 8019 | |
b113d5ee | 8020 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
8021 | fb->pixel_format, |
8022 | fb->modifier[0]); | |
1ad292b5 | 8023 | |
f37b5c2b | 8024 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 8025 | |
2844a921 DL |
8026 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8027 | pipe_name(pipe), plane, fb->width, fb->height, | |
8028 | fb->bits_per_pixel, base, fb->pitches[0], | |
8029 | plane_config->size); | |
1ad292b5 | 8030 | |
2d14030b | 8031 | plane_config->fb = intel_fb; |
1ad292b5 JB |
8032 | } |
8033 | ||
70b23a98 | 8034 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8035 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
8036 | { |
8037 | struct drm_device *dev = crtc->base.dev; | |
8038 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8039 | int pipe = pipe_config->cpu_transcoder; | |
8040 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
8041 | intel_clock_t clock; | |
0d7b6b11 | 8042 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
8043 | int refclk = 100000; |
8044 | ||
a580516d | 8045 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
8046 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
8047 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
8048 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
8049 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 8050 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 8051 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
8052 | |
8053 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
8054 | clock.m2 = (pll_dw0 & 0xff) << 22; |
8055 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
8056 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
8057 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
8058 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
8059 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
8060 | ||
dccbea3b | 8061 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
8062 | } |
8063 | ||
0e8ffe1b | 8064 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8065 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8066 | { |
8067 | struct drm_device *dev = crtc->base.dev; | |
8068 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1729050e | 8069 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 8070 | uint32_t tmp; |
1729050e | 8071 | bool ret; |
0e8ffe1b | 8072 | |
1729050e ID |
8073 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
8074 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 ID |
8075 | return false; |
8076 | ||
e143a21c | 8077 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 8078 | pipe_config->shared_dpll = NULL; |
eccb140b | 8079 | |
1729050e ID |
8080 | ret = false; |
8081 | ||
0e8ffe1b DV |
8082 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8083 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 8084 | goto out; |
0e8ffe1b | 8085 | |
666a4537 | 8086 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
42571aef VS |
8087 | switch (tmp & PIPECONF_BPC_MASK) { |
8088 | case PIPECONF_6BPC: | |
8089 | pipe_config->pipe_bpp = 18; | |
8090 | break; | |
8091 | case PIPECONF_8BPC: | |
8092 | pipe_config->pipe_bpp = 24; | |
8093 | break; | |
8094 | case PIPECONF_10BPC: | |
8095 | pipe_config->pipe_bpp = 30; | |
8096 | break; | |
8097 | default: | |
8098 | break; | |
8099 | } | |
8100 | } | |
8101 | ||
666a4537 WB |
8102 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
8103 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) | |
b5a9fa09 DV |
8104 | pipe_config->limited_color_range = true; |
8105 | ||
282740f7 VS |
8106 | if (INTEL_INFO(dev)->gen < 4) |
8107 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
8108 | ||
1bd1bd80 | 8109 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 8110 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 8111 | |
2fa2fe9a DV |
8112 | i9xx_get_pfit_config(crtc, pipe_config); |
8113 | ||
6c49f241 DV |
8114 | if (INTEL_INFO(dev)->gen >= 4) { |
8115 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
8116 | pipe_config->pixel_multiplier = | |
8117 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
8118 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 8119 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
8120 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
8121 | tmp = I915_READ(DPLL(crtc->pipe)); | |
8122 | pipe_config->pixel_multiplier = | |
8123 | ((tmp & SDVO_MULTIPLIER_MASK) | |
8124 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
8125 | } else { | |
8126 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
8127 | * port and will be fixed up in the encoder->get_config | |
8128 | * function. */ | |
8129 | pipe_config->pixel_multiplier = 1; | |
8130 | } | |
8bcc2795 | 8131 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
666a4537 | 8132 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
1c4e0274 VS |
8133 | /* |
8134 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
8135 | * on 830. Filter it out here so that we don't | |
8136 | * report errors due to that. | |
8137 | */ | |
8138 | if (IS_I830(dev)) | |
8139 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
8140 | ||
8bcc2795 DV |
8141 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
8142 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
8143 | } else { |
8144 | /* Mask out read-only status bits. */ | |
8145 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
8146 | DPLL_PORTC_READY_MASK | | |
8147 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 8148 | } |
6c49f241 | 8149 | |
70b23a98 VS |
8150 | if (IS_CHERRYVIEW(dev)) |
8151 | chv_crtc_clock_get(crtc, pipe_config); | |
8152 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
8153 | vlv_crtc_clock_get(crtc, pipe_config); |
8154 | else | |
8155 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 8156 | |
0f64614d VS |
8157 | /* |
8158 | * Normally the dotclock is filled in by the encoder .get_config() | |
8159 | * but in case the pipe is enabled w/o any ports we need a sane | |
8160 | * default. | |
8161 | */ | |
8162 | pipe_config->base.adjusted_mode.crtc_clock = | |
8163 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
8164 | ||
1729050e ID |
8165 | ret = true; |
8166 | ||
8167 | out: | |
8168 | intel_display_power_put(dev_priv, power_domain); | |
8169 | ||
8170 | return ret; | |
0e8ffe1b DV |
8171 | } |
8172 | ||
dde86e2d | 8173 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
8174 | { |
8175 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 8176 | struct intel_encoder *encoder; |
74cfd7ac | 8177 | u32 val, final; |
13d83a67 | 8178 | bool has_lvds = false; |
199e5d79 | 8179 | bool has_cpu_edp = false; |
199e5d79 | 8180 | bool has_panel = false; |
99eb6a01 KP |
8181 | bool has_ck505 = false; |
8182 | bool can_ssc = false; | |
13d83a67 JB |
8183 | |
8184 | /* We need to take the global config into account */ | |
b2784e15 | 8185 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
8186 | switch (encoder->type) { |
8187 | case INTEL_OUTPUT_LVDS: | |
8188 | has_panel = true; | |
8189 | has_lvds = true; | |
8190 | break; | |
8191 | case INTEL_OUTPUT_EDP: | |
8192 | has_panel = true; | |
2de6905f | 8193 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
8194 | has_cpu_edp = true; |
8195 | break; | |
6847d71b PZ |
8196 | default: |
8197 | break; | |
13d83a67 JB |
8198 | } |
8199 | } | |
8200 | ||
99eb6a01 | 8201 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 8202 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
8203 | can_ssc = has_ck505; |
8204 | } else { | |
8205 | has_ck505 = false; | |
8206 | can_ssc = true; | |
8207 | } | |
8208 | ||
2de6905f ID |
8209 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
8210 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
8211 | |
8212 | /* Ironlake: try to setup display ref clock before DPLL | |
8213 | * enabling. This is only under driver's control after | |
8214 | * PCH B stepping, previous chipset stepping should be | |
8215 | * ignoring this setting. | |
8216 | */ | |
74cfd7ac CW |
8217 | val = I915_READ(PCH_DREF_CONTROL); |
8218 | ||
8219 | /* As we must carefully and slowly disable/enable each source in turn, | |
8220 | * compute the final state we want first and check if we need to | |
8221 | * make any changes at all. | |
8222 | */ | |
8223 | final = val; | |
8224 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
8225 | if (has_ck505) | |
8226 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
8227 | else | |
8228 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
8229 | ||
8230 | final &= ~DREF_SSC_SOURCE_MASK; | |
8231 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
8232 | final &= ~DREF_SSC1_ENABLE; | |
8233 | ||
8234 | if (has_panel) { | |
8235 | final |= DREF_SSC_SOURCE_ENABLE; | |
8236 | ||
8237 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8238 | final |= DREF_SSC1_ENABLE; | |
8239 | ||
8240 | if (has_cpu_edp) { | |
8241 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8242 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
8243 | else | |
8244 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
8245 | } else | |
8246 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8247 | } else { | |
8248 | final |= DREF_SSC_SOURCE_DISABLE; | |
8249 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8250 | } | |
8251 | ||
8252 | if (final == val) | |
8253 | return; | |
8254 | ||
13d83a67 | 8255 | /* Always enable nonspread source */ |
74cfd7ac | 8256 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 8257 | |
99eb6a01 | 8258 | if (has_ck505) |
74cfd7ac | 8259 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 8260 | else |
74cfd7ac | 8261 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 8262 | |
199e5d79 | 8263 | if (has_panel) { |
74cfd7ac CW |
8264 | val &= ~DREF_SSC_SOURCE_MASK; |
8265 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 8266 | |
199e5d79 | 8267 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 8268 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8269 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 8270 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 8271 | } else |
74cfd7ac | 8272 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
8273 | |
8274 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 8275 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8276 | POSTING_READ(PCH_DREF_CONTROL); |
8277 | udelay(200); | |
8278 | ||
74cfd7ac | 8279 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
8280 | |
8281 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 8282 | if (has_cpu_edp) { |
99eb6a01 | 8283 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8284 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 8285 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 8286 | } else |
74cfd7ac | 8287 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 8288 | } else |
74cfd7ac | 8289 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8290 | |
74cfd7ac | 8291 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8292 | POSTING_READ(PCH_DREF_CONTROL); |
8293 | udelay(200); | |
8294 | } else { | |
8295 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
8296 | ||
74cfd7ac | 8297 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
8298 | |
8299 | /* Turn off CPU output */ | |
74cfd7ac | 8300 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8301 | |
74cfd7ac | 8302 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8303 | POSTING_READ(PCH_DREF_CONTROL); |
8304 | udelay(200); | |
8305 | ||
8306 | /* Turn off the SSC source */ | |
74cfd7ac CW |
8307 | val &= ~DREF_SSC_SOURCE_MASK; |
8308 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
8309 | |
8310 | /* Turn off SSC1 */ | |
74cfd7ac | 8311 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 8312 | |
74cfd7ac | 8313 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
8314 | POSTING_READ(PCH_DREF_CONTROL); |
8315 | udelay(200); | |
8316 | } | |
74cfd7ac CW |
8317 | |
8318 | BUG_ON(val != final); | |
13d83a67 JB |
8319 | } |
8320 | ||
f31f2d55 | 8321 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 8322 | { |
f31f2d55 | 8323 | uint32_t tmp; |
dde86e2d | 8324 | |
0ff066a9 PZ |
8325 | tmp = I915_READ(SOUTH_CHICKEN2); |
8326 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
8327 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8328 | |
0ff066a9 PZ |
8329 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
8330 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
8331 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 8332 | |
0ff066a9 PZ |
8333 | tmp = I915_READ(SOUTH_CHICKEN2); |
8334 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
8335 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8336 | |
0ff066a9 PZ |
8337 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
8338 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
8339 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
8340 | } |
8341 | ||
8342 | /* WaMPhyProgramming:hsw */ | |
8343 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
8344 | { | |
8345 | uint32_t tmp; | |
dde86e2d PZ |
8346 | |
8347 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
8348 | tmp &= ~(0xFF << 24); | |
8349 | tmp |= (0x12 << 24); | |
8350 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
8351 | ||
dde86e2d PZ |
8352 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
8353 | tmp |= (1 << 11); | |
8354 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
8355 | ||
8356 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
8357 | tmp |= (1 << 11); | |
8358 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
8359 | ||
dde86e2d PZ |
8360 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
8361 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8362 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
8363 | ||
8364 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
8365 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8366 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
8367 | ||
0ff066a9 PZ |
8368 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
8369 | tmp &= ~(7 << 13); | |
8370 | tmp |= (5 << 13); | |
8371 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 8372 | |
0ff066a9 PZ |
8373 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
8374 | tmp &= ~(7 << 13); | |
8375 | tmp |= (5 << 13); | |
8376 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
8377 | |
8378 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
8379 | tmp &= ~0xFF; | |
8380 | tmp |= 0x1C; | |
8381 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
8382 | ||
8383 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
8384 | tmp &= ~0xFF; | |
8385 | tmp |= 0x1C; | |
8386 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
8387 | ||
8388 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
8389 | tmp &= ~(0xFF << 16); | |
8390 | tmp |= (0x1C << 16); | |
8391 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
8392 | ||
8393 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
8394 | tmp &= ~(0xFF << 16); | |
8395 | tmp |= (0x1C << 16); | |
8396 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
8397 | ||
0ff066a9 PZ |
8398 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
8399 | tmp |= (1 << 27); | |
8400 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 8401 | |
0ff066a9 PZ |
8402 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
8403 | tmp |= (1 << 27); | |
8404 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 8405 | |
0ff066a9 PZ |
8406 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
8407 | tmp &= ~(0xF << 28); | |
8408 | tmp |= (4 << 28); | |
8409 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 8410 | |
0ff066a9 PZ |
8411 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
8412 | tmp &= ~(0xF << 28); | |
8413 | tmp |= (4 << 28); | |
8414 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
8415 | } |
8416 | ||
2fa86a1f PZ |
8417 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
8418 | * Programming" based on the parameters passed: | |
8419 | * - Sequence to enable CLKOUT_DP | |
8420 | * - Sequence to enable CLKOUT_DP without spread | |
8421 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
8422 | */ | |
8423 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
8424 | bool with_fdi) | |
f31f2d55 PZ |
8425 | { |
8426 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
8427 | uint32_t reg, tmp; |
8428 | ||
8429 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
8430 | with_spread = true; | |
c2699524 | 8431 | if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n")) |
2fa86a1f | 8432 | with_fdi = false; |
f31f2d55 | 8433 | |
a580516d | 8434 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
8435 | |
8436 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8437 | tmp &= ~SBI_SSCCTL_DISABLE; | |
8438 | tmp |= SBI_SSCCTL_PATHALT; | |
8439 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8440 | ||
8441 | udelay(24); | |
8442 | ||
2fa86a1f PZ |
8443 | if (with_spread) { |
8444 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8445 | tmp &= ~SBI_SSCCTL_PATHALT; | |
8446 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 8447 | |
2fa86a1f PZ |
8448 | if (with_fdi) { |
8449 | lpt_reset_fdi_mphy(dev_priv); | |
8450 | lpt_program_fdi_mphy(dev_priv); | |
8451 | } | |
8452 | } | |
dde86e2d | 8453 | |
c2699524 | 8454 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
8455 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8456 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8457 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 8458 | |
a580516d | 8459 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
8460 | } |
8461 | ||
47701c3b PZ |
8462 | /* Sequence to disable CLKOUT_DP */ |
8463 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
8464 | { | |
8465 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8466 | uint32_t reg, tmp; | |
8467 | ||
a580516d | 8468 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 8469 | |
c2699524 | 8470 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
8471 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8472 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8473 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
8474 | ||
8475 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8476 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
8477 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
8478 | tmp |= SBI_SSCCTL_PATHALT; | |
8479 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8480 | udelay(32); | |
8481 | } | |
8482 | tmp |= SBI_SSCCTL_DISABLE; | |
8483 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8484 | } | |
8485 | ||
a580516d | 8486 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
8487 | } |
8488 | ||
f7be2c21 VS |
8489 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
8490 | ||
8491 | static const uint16_t sscdivintphase[] = { | |
8492 | [BEND_IDX( 50)] = 0x3B23, | |
8493 | [BEND_IDX( 45)] = 0x3B23, | |
8494 | [BEND_IDX( 40)] = 0x3C23, | |
8495 | [BEND_IDX( 35)] = 0x3C23, | |
8496 | [BEND_IDX( 30)] = 0x3D23, | |
8497 | [BEND_IDX( 25)] = 0x3D23, | |
8498 | [BEND_IDX( 20)] = 0x3E23, | |
8499 | [BEND_IDX( 15)] = 0x3E23, | |
8500 | [BEND_IDX( 10)] = 0x3F23, | |
8501 | [BEND_IDX( 5)] = 0x3F23, | |
8502 | [BEND_IDX( 0)] = 0x0025, | |
8503 | [BEND_IDX( -5)] = 0x0025, | |
8504 | [BEND_IDX(-10)] = 0x0125, | |
8505 | [BEND_IDX(-15)] = 0x0125, | |
8506 | [BEND_IDX(-20)] = 0x0225, | |
8507 | [BEND_IDX(-25)] = 0x0225, | |
8508 | [BEND_IDX(-30)] = 0x0325, | |
8509 | [BEND_IDX(-35)] = 0x0325, | |
8510 | [BEND_IDX(-40)] = 0x0425, | |
8511 | [BEND_IDX(-45)] = 0x0425, | |
8512 | [BEND_IDX(-50)] = 0x0525, | |
8513 | }; | |
8514 | ||
8515 | /* | |
8516 | * Bend CLKOUT_DP | |
8517 | * steps -50 to 50 inclusive, in steps of 5 | |
8518 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) | |
8519 | * change in clock period = -(steps / 10) * 5.787 ps | |
8520 | */ | |
8521 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) | |
8522 | { | |
8523 | uint32_t tmp; | |
8524 | int idx = BEND_IDX(steps); | |
8525 | ||
8526 | if (WARN_ON(steps % 5 != 0)) | |
8527 | return; | |
8528 | ||
8529 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) | |
8530 | return; | |
8531 | ||
8532 | mutex_lock(&dev_priv->sb_lock); | |
8533 | ||
8534 | if (steps % 10 != 0) | |
8535 | tmp = 0xAAAAAAAB; | |
8536 | else | |
8537 | tmp = 0x00000000; | |
8538 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); | |
8539 | ||
8540 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); | |
8541 | tmp &= 0xffff0000; | |
8542 | tmp |= sscdivintphase[idx]; | |
8543 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); | |
8544 | ||
8545 | mutex_unlock(&dev_priv->sb_lock); | |
8546 | } | |
8547 | ||
8548 | #undef BEND_IDX | |
8549 | ||
bf8fa3d3 PZ |
8550 | static void lpt_init_pch_refclk(struct drm_device *dev) |
8551 | { | |
bf8fa3d3 PZ |
8552 | struct intel_encoder *encoder; |
8553 | bool has_vga = false; | |
8554 | ||
b2784e15 | 8555 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
8556 | switch (encoder->type) { |
8557 | case INTEL_OUTPUT_ANALOG: | |
8558 | has_vga = true; | |
8559 | break; | |
6847d71b PZ |
8560 | default: |
8561 | break; | |
bf8fa3d3 PZ |
8562 | } |
8563 | } | |
8564 | ||
f7be2c21 VS |
8565 | if (has_vga) { |
8566 | lpt_bend_clkout_dp(to_i915(dev), 0); | |
47701c3b | 8567 | lpt_enable_clkout_dp(dev, true, true); |
f7be2c21 | 8568 | } else { |
47701c3b | 8569 | lpt_disable_clkout_dp(dev); |
f7be2c21 | 8570 | } |
bf8fa3d3 PZ |
8571 | } |
8572 | ||
dde86e2d PZ |
8573 | /* |
8574 | * Initialize reference clocks when the driver loads | |
8575 | */ | |
8576 | void intel_init_pch_refclk(struct drm_device *dev) | |
8577 | { | |
8578 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
8579 | ironlake_init_pch_refclk(dev); | |
8580 | else if (HAS_PCH_LPT(dev)) | |
8581 | lpt_init_pch_refclk(dev); | |
8582 | } | |
8583 | ||
55bb9992 | 8584 | static int ironlake_get_refclk(struct intel_crtc_state *crtc_state) |
d9d444cb | 8585 | { |
55bb9992 | 8586 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d9d444cb | 8587 | struct drm_i915_private *dev_priv = dev->dev_private; |
55bb9992 | 8588 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8589 | struct drm_connector *connector; |
55bb9992 | 8590 | struct drm_connector_state *connector_state; |
d9d444cb | 8591 | struct intel_encoder *encoder; |
55bb9992 | 8592 | int num_connectors = 0, i; |
d9d444cb JB |
8593 | bool is_lvds = false; |
8594 | ||
da3ced29 | 8595 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8596 | if (connector_state->crtc != crtc_state->base.crtc) |
8597 | continue; | |
8598 | ||
8599 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8600 | ||
d9d444cb JB |
8601 | switch (encoder->type) { |
8602 | case INTEL_OUTPUT_LVDS: | |
8603 | is_lvds = true; | |
8604 | break; | |
6847d71b PZ |
8605 | default: |
8606 | break; | |
d9d444cb JB |
8607 | } |
8608 | num_connectors++; | |
8609 | } | |
8610 | ||
8611 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 8612 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 8613 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 8614 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
8615 | } |
8616 | ||
8617 | return 120000; | |
8618 | } | |
8619 | ||
6ff93609 | 8620 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 8621 | { |
c8203565 | 8622 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
8623 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8624 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
8625 | uint32_t val; |
8626 | ||
78114071 | 8627 | val = 0; |
c8203565 | 8628 | |
6e3c9717 | 8629 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 8630 | case 18: |
dfd07d72 | 8631 | val |= PIPECONF_6BPC; |
c8203565 PZ |
8632 | break; |
8633 | case 24: | |
dfd07d72 | 8634 | val |= PIPECONF_8BPC; |
c8203565 PZ |
8635 | break; |
8636 | case 30: | |
dfd07d72 | 8637 | val |= PIPECONF_10BPC; |
c8203565 PZ |
8638 | break; |
8639 | case 36: | |
dfd07d72 | 8640 | val |= PIPECONF_12BPC; |
c8203565 PZ |
8641 | break; |
8642 | default: | |
cc769b62 PZ |
8643 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
8644 | BUG(); | |
c8203565 PZ |
8645 | } |
8646 | ||
6e3c9717 | 8647 | if (intel_crtc->config->dither) |
c8203565 PZ |
8648 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8649 | ||
6e3c9717 | 8650 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
8651 | val |= PIPECONF_INTERLACED_ILK; |
8652 | else | |
8653 | val |= PIPECONF_PROGRESSIVE; | |
8654 | ||
6e3c9717 | 8655 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 8656 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 8657 | |
c8203565 PZ |
8658 | I915_WRITE(PIPECONF(pipe), val); |
8659 | POSTING_READ(PIPECONF(pipe)); | |
8660 | } | |
8661 | ||
6ff93609 | 8662 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8663 | { |
391bf048 | 8664 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
ee2b0b38 | 8665 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 8666 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
391bf048 | 8667 | u32 val = 0; |
ee2b0b38 | 8668 | |
391bf048 | 8669 | if (IS_HASWELL(dev_priv) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8670 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8671 | ||
6e3c9717 | 8672 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8673 | val |= PIPECONF_INTERLACED_ILK; |
8674 | else | |
8675 | val |= PIPECONF_PROGRESSIVE; | |
8676 | ||
702e7a56 PZ |
8677 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8678 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
391bf048 JN |
8679 | } |
8680 | ||
391bf048 JN |
8681 | static void haswell_set_pipemisc(struct drm_crtc *crtc) |
8682 | { | |
8683 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
8684 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
756f85cf | 8685 | |
391bf048 JN |
8686 | if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) { |
8687 | u32 val = 0; | |
756f85cf | 8688 | |
6e3c9717 | 8689 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8690 | case 18: |
8691 | val |= PIPEMISC_DITHER_6_BPC; | |
8692 | break; | |
8693 | case 24: | |
8694 | val |= PIPEMISC_DITHER_8_BPC; | |
8695 | break; | |
8696 | case 30: | |
8697 | val |= PIPEMISC_DITHER_10_BPC; | |
8698 | break; | |
8699 | case 36: | |
8700 | val |= PIPEMISC_DITHER_12_BPC; | |
8701 | break; | |
8702 | default: | |
8703 | /* Case prevented by pipe_config_set_bpp. */ | |
8704 | BUG(); | |
8705 | } | |
8706 | ||
6e3c9717 | 8707 | if (intel_crtc->config->dither) |
756f85cf PZ |
8708 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8709 | ||
391bf048 | 8710 | I915_WRITE(PIPEMISC(intel_crtc->pipe), val); |
756f85cf | 8711 | } |
ee2b0b38 PZ |
8712 | } |
8713 | ||
6591c6e4 | 8714 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
190f68c5 | 8715 | struct intel_crtc_state *crtc_state, |
6591c6e4 PZ |
8716 | intel_clock_t *clock, |
8717 | bool *has_reduced_clock, | |
8718 | intel_clock_t *reduced_clock) | |
8719 | { | |
8720 | struct drm_device *dev = crtc->dev; | |
8721 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6591c6e4 | 8722 | int refclk; |
d4906093 | 8723 | const intel_limit_t *limit; |
c329a4ec | 8724 | bool ret; |
79e53945 | 8725 | |
55bb9992 | 8726 | refclk = ironlake_get_refclk(crtc_state); |
79e53945 | 8727 | |
d4906093 ML |
8728 | /* |
8729 | * Returns a set of divisors for the desired target clock with the given | |
8730 | * refclk, or FALSE. The returned values represent the clock equation: | |
8731 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
8732 | */ | |
a93e255f ACO |
8733 | limit = intel_limit(crtc_state, refclk); |
8734 | ret = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 8735 | crtc_state->port_clock, |
ee9300bb | 8736 | refclk, NULL, clock); |
6591c6e4 PZ |
8737 | if (!ret) |
8738 | return false; | |
cda4b7d3 | 8739 | |
6591c6e4 PZ |
8740 | return true; |
8741 | } | |
8742 | ||
d4b1931c PZ |
8743 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
8744 | { | |
8745 | /* | |
8746 | * Account for spread spectrum to avoid | |
8747 | * oversubscribing the link. Max center spread | |
8748 | * is 2.5%; use 5% for safety's sake. | |
8749 | */ | |
8750 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 8751 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
8752 | } |
8753 | ||
7429e9d4 | 8754 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 8755 | { |
7429e9d4 | 8756 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
8757 | } |
8758 | ||
de13a2e3 | 8759 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
190f68c5 | 8760 | struct intel_crtc_state *crtc_state, |
7429e9d4 | 8761 | u32 *fp, |
9a7c7890 | 8762 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 8763 | { |
de13a2e3 | 8764 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
8765 | struct drm_device *dev = crtc->dev; |
8766 | struct drm_i915_private *dev_priv = dev->dev_private; | |
55bb9992 | 8767 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8768 | struct drm_connector *connector; |
55bb9992 ACO |
8769 | struct drm_connector_state *connector_state; |
8770 | struct intel_encoder *encoder; | |
de13a2e3 | 8771 | uint32_t dpll; |
55bb9992 | 8772 | int factor, num_connectors = 0, i; |
09ede541 | 8773 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 8774 | |
da3ced29 | 8775 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8776 | if (connector_state->crtc != crtc_state->base.crtc) |
8777 | continue; | |
8778 | ||
8779 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8780 | ||
8781 | switch (encoder->type) { | |
79e53945 JB |
8782 | case INTEL_OUTPUT_LVDS: |
8783 | is_lvds = true; | |
8784 | break; | |
8785 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 8786 | case INTEL_OUTPUT_HDMI: |
79e53945 | 8787 | is_sdvo = true; |
79e53945 | 8788 | break; |
6847d71b PZ |
8789 | default: |
8790 | break; | |
79e53945 | 8791 | } |
43565a06 | 8792 | |
c751ce4f | 8793 | num_connectors++; |
79e53945 | 8794 | } |
79e53945 | 8795 | |
c1858123 | 8796 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
8797 | factor = 21; |
8798 | if (is_lvds) { | |
8799 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 8800 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 8801 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 8802 | factor = 25; |
190f68c5 | 8803 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 8804 | factor = 20; |
c1858123 | 8805 | |
190f68c5 | 8806 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
7d0ac5b7 | 8807 | *fp |= FP_CB_TUNE; |
2c07245f | 8808 | |
9a7c7890 DV |
8809 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
8810 | *fp2 |= FP_CB_TUNE; | |
8811 | ||
5eddb70b | 8812 | dpll = 0; |
2c07245f | 8813 | |
a07d6787 EA |
8814 | if (is_lvds) |
8815 | dpll |= DPLLB_MODE_LVDS; | |
8816 | else | |
8817 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 8818 | |
190f68c5 | 8819 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8820 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f DV |
8821 | |
8822 | if (is_sdvo) | |
4a33e48d | 8823 | dpll |= DPLL_SDVO_HIGH_SPEED; |
190f68c5 | 8824 | if (crtc_state->has_dp_encoder) |
4a33e48d | 8825 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 8826 | |
a07d6787 | 8827 | /* compute bitmask from p1 value */ |
190f68c5 | 8828 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 8829 | /* also FPA1 */ |
190f68c5 | 8830 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 8831 | |
190f68c5 | 8832 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
8833 | case 5: |
8834 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8835 | break; | |
8836 | case 7: | |
8837 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8838 | break; | |
8839 | case 10: | |
8840 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8841 | break; | |
8842 | case 14: | |
8843 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8844 | break; | |
79e53945 JB |
8845 | } |
8846 | ||
b4c09f3b | 8847 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 8848 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
8849 | else |
8850 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8851 | ||
959e16d6 | 8852 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
8853 | } |
8854 | ||
190f68c5 ACO |
8855 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
8856 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 8857 | { |
c7653199 | 8858 | struct drm_device *dev = crtc->base.dev; |
de13a2e3 | 8859 | intel_clock_t clock, reduced_clock; |
cbbab5bd | 8860 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 8861 | bool ok, has_reduced_clock = false; |
8b47047b | 8862 | bool is_lvds = false; |
e2b78267 | 8863 | struct intel_shared_dpll *pll; |
de13a2e3 | 8864 | |
dd3cd74a ACO |
8865 | memset(&crtc_state->dpll_hw_state, 0, |
8866 | sizeof(crtc_state->dpll_hw_state)); | |
8867 | ||
7905df29 | 8868 | is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS); |
79e53945 | 8869 | |
5dc5298b PZ |
8870 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
8871 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 8872 | |
190f68c5 | 8873 | ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock, |
de13a2e3 | 8874 | &has_reduced_clock, &reduced_clock); |
190f68c5 | 8875 | if (!ok && !crtc_state->clock_set) { |
de13a2e3 PZ |
8876 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
8877 | return -EINVAL; | |
79e53945 | 8878 | } |
f47709a9 | 8879 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
8880 | if (!crtc_state->clock_set) { |
8881 | crtc_state->dpll.n = clock.n; | |
8882 | crtc_state->dpll.m1 = clock.m1; | |
8883 | crtc_state->dpll.m2 = clock.m2; | |
8884 | crtc_state->dpll.p1 = clock.p1; | |
8885 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 8886 | } |
79e53945 | 8887 | |
5dc5298b | 8888 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
190f68c5 ACO |
8889 | if (crtc_state->has_pch_encoder) { |
8890 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); | |
cbbab5bd | 8891 | if (has_reduced_clock) |
7429e9d4 | 8892 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 8893 | |
190f68c5 | 8894 | dpll = ironlake_compute_dpll(crtc, crtc_state, |
cbbab5bd DV |
8895 | &fp, &reduced_clock, |
8896 | has_reduced_clock ? &fp2 : NULL); | |
8897 | ||
190f68c5 ACO |
8898 | crtc_state->dpll_hw_state.dpll = dpll; |
8899 | crtc_state->dpll_hw_state.fp0 = fp; | |
66e985c0 | 8900 | if (has_reduced_clock) |
190f68c5 | 8901 | crtc_state->dpll_hw_state.fp1 = fp2; |
66e985c0 | 8902 | else |
190f68c5 | 8903 | crtc_state->dpll_hw_state.fp1 = fp; |
66e985c0 | 8904 | |
daedf20a | 8905 | pll = intel_get_shared_dpll(crtc, crtc_state, NULL); |
ee7b9f93 | 8906 | if (pll == NULL) { |
84f44ce7 | 8907 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
c7653199 | 8908 | pipe_name(crtc->pipe)); |
4b645f14 JB |
8909 | return -EINVAL; |
8910 | } | |
3fb37703 | 8911 | } |
79e53945 | 8912 | |
ab585dea | 8913 | if (is_lvds && has_reduced_clock) |
c7653199 | 8914 | crtc->lowfreq_avail = true; |
bcd644e0 | 8915 | else |
c7653199 | 8916 | crtc->lowfreq_avail = false; |
e2b78267 | 8917 | |
c8f7a0db | 8918 | return 0; |
79e53945 JB |
8919 | } |
8920 | ||
eb14cb74 VS |
8921 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
8922 | struct intel_link_m_n *m_n) | |
8923 | { | |
8924 | struct drm_device *dev = crtc->base.dev; | |
8925 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8926 | enum pipe pipe = crtc->pipe; | |
8927 | ||
8928 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
8929 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
8930 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8931 | & ~TU_SIZE_MASK; | |
8932 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
8933 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8934 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8935 | } | |
8936 | ||
8937 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
8938 | enum transcoder transcoder, | |
b95af8be VK |
8939 | struct intel_link_m_n *m_n, |
8940 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
8941 | { |
8942 | struct drm_device *dev = crtc->base.dev; | |
8943 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 8944 | enum pipe pipe = crtc->pipe; |
72419203 | 8945 | |
eb14cb74 VS |
8946 | if (INTEL_INFO(dev)->gen >= 5) { |
8947 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
8948 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
8949 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
8950 | & ~TU_SIZE_MASK; | |
8951 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
8952 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
8953 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
8954 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
8955 | * gen < 8) and if DRRS is supported (to make sure the | |
8956 | * registers are not unnecessarily read). | |
8957 | */ | |
8958 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 8959 | crtc->config->has_drrs) { |
b95af8be VK |
8960 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
8961 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
8962 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
8963 | & ~TU_SIZE_MASK; | |
8964 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
8965 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
8966 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8967 | } | |
eb14cb74 VS |
8968 | } else { |
8969 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
8970 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
8971 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8972 | & ~TU_SIZE_MASK; | |
8973 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
8974 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8975 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8976 | } | |
8977 | } | |
8978 | ||
8979 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 8980 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 8981 | { |
681a8504 | 8982 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
8983 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
8984 | else | |
8985 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
8986 | &pipe_config->dp_m_n, |
8987 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 8988 | } |
72419203 | 8989 | |
eb14cb74 | 8990 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 8991 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
8992 | { |
8993 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 8994 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
8995 | } |
8996 | ||
bd2e244f | 8997 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8998 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
8999 | { |
9000 | struct drm_device *dev = crtc->base.dev; | |
9001 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a1b2278e CK |
9002 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
9003 | uint32_t ps_ctrl = 0; | |
9004 | int id = -1; | |
9005 | int i; | |
bd2e244f | 9006 | |
a1b2278e CK |
9007 | /* find scaler attached to this pipe */ |
9008 | for (i = 0; i < crtc->num_scalers; i++) { | |
9009 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
9010 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
9011 | id = i; | |
9012 | pipe_config->pch_pfit.enabled = true; | |
9013 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
9014 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
9015 | break; | |
9016 | } | |
9017 | } | |
bd2e244f | 9018 | |
a1b2278e CK |
9019 | scaler_state->scaler_id = id; |
9020 | if (id >= 0) { | |
9021 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
9022 | } else { | |
9023 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
9024 | } |
9025 | } | |
9026 | ||
5724dbd1 DL |
9027 | static void |
9028 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
9029 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
9030 | { |
9031 | struct drm_device *dev = crtc->base.dev; | |
9032 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40f46283 | 9033 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
9034 | int pipe = crtc->pipe; |
9035 | int fourcc, pixel_format; | |
6761dd31 | 9036 | unsigned int aligned_height; |
bc8d7dff | 9037 | struct drm_framebuffer *fb; |
1b842c89 | 9038 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 9039 | |
d9806c9f | 9040 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9041 | if (!intel_fb) { |
bc8d7dff DL |
9042 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9043 | return; | |
9044 | } | |
9045 | ||
1b842c89 DL |
9046 | fb = &intel_fb->base; |
9047 | ||
bc8d7dff | 9048 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
9049 | if (!(val & PLANE_CTL_ENABLE)) |
9050 | goto error; | |
9051 | ||
bc8d7dff DL |
9052 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
9053 | fourcc = skl_format_to_fourcc(pixel_format, | |
9054 | val & PLANE_CTL_ORDER_RGBX, | |
9055 | val & PLANE_CTL_ALPHA_MASK); | |
9056 | fb->pixel_format = fourcc; | |
9057 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
9058 | ||
40f46283 DL |
9059 | tiling = val & PLANE_CTL_TILED_MASK; |
9060 | switch (tiling) { | |
9061 | case PLANE_CTL_TILED_LINEAR: | |
9062 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
9063 | break; | |
9064 | case PLANE_CTL_TILED_X: | |
9065 | plane_config->tiling = I915_TILING_X; | |
9066 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
9067 | break; | |
9068 | case PLANE_CTL_TILED_Y: | |
9069 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
9070 | break; | |
9071 | case PLANE_CTL_TILED_YF: | |
9072 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
9073 | break; | |
9074 | default: | |
9075 | MISSING_CASE(tiling); | |
9076 | goto error; | |
9077 | } | |
9078 | ||
bc8d7dff DL |
9079 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
9080 | plane_config->base = base; | |
9081 | ||
9082 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
9083 | ||
9084 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
9085 | fb->height = ((val >> 16) & 0xfff) + 1; | |
9086 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
9087 | ||
9088 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
7b49f948 | 9089 | stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
40f46283 | 9090 | fb->pixel_format); |
bc8d7dff DL |
9091 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
9092 | ||
9093 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
9094 | fb->pixel_format, |
9095 | fb->modifier[0]); | |
bc8d7dff | 9096 | |
f37b5c2b | 9097 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
9098 | |
9099 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
9100 | pipe_name(pipe), fb->width, fb->height, | |
9101 | fb->bits_per_pixel, base, fb->pitches[0], | |
9102 | plane_config->size); | |
9103 | ||
2d14030b | 9104 | plane_config->fb = intel_fb; |
bc8d7dff DL |
9105 | return; |
9106 | ||
9107 | error: | |
9108 | kfree(fb); | |
9109 | } | |
9110 | ||
2fa2fe9a | 9111 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9112 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
9113 | { |
9114 | struct drm_device *dev = crtc->base.dev; | |
9115 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9116 | uint32_t tmp; | |
9117 | ||
9118 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
9119 | ||
9120 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 9121 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
9122 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
9123 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
9124 | |
9125 | /* We currently do not free assignements of panel fitters on | |
9126 | * ivb/hsw (since we don't use the higher upscaling modes which | |
9127 | * differentiates them) so just WARN about this case for now. */ | |
9128 | if (IS_GEN7(dev)) { | |
9129 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
9130 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
9131 | } | |
2fa2fe9a | 9132 | } |
79e53945 JB |
9133 | } |
9134 | ||
5724dbd1 DL |
9135 | static void |
9136 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
9137 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
9138 | { |
9139 | struct drm_device *dev = crtc->base.dev; | |
9140 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9141 | u32 val, base, offset; | |
aeee5a49 | 9142 | int pipe = crtc->pipe; |
4c6baa59 | 9143 | int fourcc, pixel_format; |
6761dd31 | 9144 | unsigned int aligned_height; |
b113d5ee | 9145 | struct drm_framebuffer *fb; |
1b842c89 | 9146 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 9147 | |
42a7b088 DL |
9148 | val = I915_READ(DSPCNTR(pipe)); |
9149 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
9150 | return; | |
9151 | ||
d9806c9f | 9152 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9153 | if (!intel_fb) { |
4c6baa59 JB |
9154 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9155 | return; | |
9156 | } | |
9157 | ||
1b842c89 DL |
9158 | fb = &intel_fb->base; |
9159 | ||
18c5247e DV |
9160 | if (INTEL_INFO(dev)->gen >= 4) { |
9161 | if (val & DISPPLANE_TILED) { | |
49af449b | 9162 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
9163 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
9164 | } | |
9165 | } | |
4c6baa59 JB |
9166 | |
9167 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 9168 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
9169 | fb->pixel_format = fourcc; |
9170 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 9171 | |
aeee5a49 | 9172 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 9173 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 9174 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 9175 | } else { |
49af449b | 9176 | if (plane_config->tiling) |
aeee5a49 | 9177 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 9178 | else |
aeee5a49 | 9179 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
9180 | } |
9181 | plane_config->base = base; | |
9182 | ||
9183 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
9184 | fb->width = ((val >> 16) & 0xfff) + 1; |
9185 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
9186 | |
9187 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 9188 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 9189 | |
b113d5ee | 9190 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
9191 | fb->pixel_format, |
9192 | fb->modifier[0]); | |
4c6baa59 | 9193 | |
f37b5c2b | 9194 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 9195 | |
2844a921 DL |
9196 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
9197 | pipe_name(pipe), fb->width, fb->height, | |
9198 | fb->bits_per_pixel, base, fb->pitches[0], | |
9199 | plane_config->size); | |
b113d5ee | 9200 | |
2d14030b | 9201 | plane_config->fb = intel_fb; |
4c6baa59 JB |
9202 | } |
9203 | ||
0e8ffe1b | 9204 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9205 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9206 | { |
9207 | struct drm_device *dev = crtc->base.dev; | |
9208 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1729050e | 9209 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 9210 | uint32_t tmp; |
1729050e | 9211 | bool ret; |
0e8ffe1b | 9212 | |
1729050e ID |
9213 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
9214 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
930e8c9e PZ |
9215 | return false; |
9216 | ||
e143a21c | 9217 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 9218 | pipe_config->shared_dpll = NULL; |
eccb140b | 9219 | |
1729050e | 9220 | ret = false; |
0e8ffe1b DV |
9221 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
9222 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 9223 | goto out; |
0e8ffe1b | 9224 | |
42571aef VS |
9225 | switch (tmp & PIPECONF_BPC_MASK) { |
9226 | case PIPECONF_6BPC: | |
9227 | pipe_config->pipe_bpp = 18; | |
9228 | break; | |
9229 | case PIPECONF_8BPC: | |
9230 | pipe_config->pipe_bpp = 24; | |
9231 | break; | |
9232 | case PIPECONF_10BPC: | |
9233 | pipe_config->pipe_bpp = 30; | |
9234 | break; | |
9235 | case PIPECONF_12BPC: | |
9236 | pipe_config->pipe_bpp = 36; | |
9237 | break; | |
9238 | default: | |
9239 | break; | |
9240 | } | |
9241 | ||
b5a9fa09 DV |
9242 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
9243 | pipe_config->limited_color_range = true; | |
9244 | ||
ab9412ba | 9245 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 | 9246 | struct intel_shared_dpll *pll; |
8106ddbd | 9247 | enum intel_dpll_id pll_id; |
66e985c0 | 9248 | |
88adfff1 DV |
9249 | pipe_config->has_pch_encoder = true; |
9250 | ||
627eb5a3 DV |
9251 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
9252 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9253 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
9254 | |
9255 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 9256 | |
c0d43d62 | 9257 | if (HAS_PCH_IBX(dev_priv->dev)) { |
8106ddbd | 9258 | pll_id = (enum intel_dpll_id) crtc->pipe; |
c0d43d62 DV |
9259 | } else { |
9260 | tmp = I915_READ(PCH_DPLL_SEL); | |
9261 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
8106ddbd | 9262 | pll_id = DPLL_ID_PCH_PLL_B; |
c0d43d62 | 9263 | else |
8106ddbd | 9264 | pll_id= DPLL_ID_PCH_PLL_A; |
c0d43d62 | 9265 | } |
66e985c0 | 9266 | |
8106ddbd ACO |
9267 | pipe_config->shared_dpll = |
9268 | intel_get_shared_dpll_by_id(dev_priv, pll_id); | |
9269 | pll = pipe_config->shared_dpll; | |
66e985c0 | 9270 | |
2edd6443 ACO |
9271 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
9272 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
9273 | |
9274 | tmp = pipe_config->dpll_hw_state.dpll; | |
9275 | pipe_config->pixel_multiplier = | |
9276 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
9277 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
9278 | |
9279 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
9280 | } else { |
9281 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
9282 | } |
9283 | ||
1bd1bd80 | 9284 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 9285 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 9286 | |
2fa2fe9a DV |
9287 | ironlake_get_pfit_config(crtc, pipe_config); |
9288 | ||
1729050e ID |
9289 | ret = true; |
9290 | ||
9291 | out: | |
9292 | intel_display_power_put(dev_priv, power_domain); | |
9293 | ||
9294 | return ret; | |
0e8ffe1b DV |
9295 | } |
9296 | ||
be256dc7 PZ |
9297 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
9298 | { | |
9299 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 9300 | struct intel_crtc *crtc; |
be256dc7 | 9301 | |
d3fcc808 | 9302 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 9303 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
9304 | pipe_name(crtc->pipe)); |
9305 | ||
e2c719b7 RC |
9306 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
9307 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
01403de3 VS |
9308 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
9309 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
e2c719b7 RC |
9310 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
9311 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
be256dc7 | 9312 | "CPU PWM1 enabled\n"); |
c5107b87 | 9313 | if (IS_HASWELL(dev)) |
e2c719b7 | 9314 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 9315 | "CPU PWM2 enabled\n"); |
e2c719b7 | 9316 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 9317 | "PCH PWM1 enabled\n"); |
e2c719b7 | 9318 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 9319 | "Utility pin enabled\n"); |
e2c719b7 | 9320 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 9321 | |
9926ada1 PZ |
9322 | /* |
9323 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
9324 | * interrupts remain enabled. We used to check for that, but since it's | |
9325 | * gen-specific and since we only disable LCPLL after we fully disable | |
9326 | * the interrupts, the check below should be enough. | |
9327 | */ | |
e2c719b7 | 9328 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
9329 | } |
9330 | ||
9ccd5aeb PZ |
9331 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
9332 | { | |
9333 | struct drm_device *dev = dev_priv->dev; | |
9334 | ||
9335 | if (IS_HASWELL(dev)) | |
9336 | return I915_READ(D_COMP_HSW); | |
9337 | else | |
9338 | return I915_READ(D_COMP_BDW); | |
9339 | } | |
9340 | ||
3c4c9b81 PZ |
9341 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
9342 | { | |
9343 | struct drm_device *dev = dev_priv->dev; | |
9344 | ||
9345 | if (IS_HASWELL(dev)) { | |
9346 | mutex_lock(&dev_priv->rps.hw_lock); | |
9347 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
9348 | val)) | |
f475dadf | 9349 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
9350 | mutex_unlock(&dev_priv->rps.hw_lock); |
9351 | } else { | |
9ccd5aeb PZ |
9352 | I915_WRITE(D_COMP_BDW, val); |
9353 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 9354 | } |
be256dc7 PZ |
9355 | } |
9356 | ||
9357 | /* | |
9358 | * This function implements pieces of two sequences from BSpec: | |
9359 | * - Sequence for display software to disable LCPLL | |
9360 | * - Sequence for display software to allow package C8+ | |
9361 | * The steps implemented here are just the steps that actually touch the LCPLL | |
9362 | * register. Callers should take care of disabling all the display engine | |
9363 | * functions, doing the mode unset, fixing interrupts, etc. | |
9364 | */ | |
6ff58d53 PZ |
9365 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
9366 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
9367 | { |
9368 | uint32_t val; | |
9369 | ||
9370 | assert_can_disable_lcpll(dev_priv); | |
9371 | ||
9372 | val = I915_READ(LCPLL_CTL); | |
9373 | ||
9374 | if (switch_to_fclk) { | |
9375 | val |= LCPLL_CD_SOURCE_FCLK; | |
9376 | I915_WRITE(LCPLL_CTL, val); | |
9377 | ||
9378 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9379 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9380 | DRM_ERROR("Switching to FCLK failed\n"); | |
9381 | ||
9382 | val = I915_READ(LCPLL_CTL); | |
9383 | } | |
9384 | ||
9385 | val |= LCPLL_PLL_DISABLE; | |
9386 | I915_WRITE(LCPLL_CTL, val); | |
9387 | POSTING_READ(LCPLL_CTL); | |
9388 | ||
9389 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
9390 | DRM_ERROR("LCPLL still locked\n"); | |
9391 | ||
9ccd5aeb | 9392 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 9393 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 9394 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9395 | ndelay(100); |
9396 | ||
9ccd5aeb PZ |
9397 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
9398 | 1)) | |
be256dc7 PZ |
9399 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
9400 | ||
9401 | if (allow_power_down) { | |
9402 | val = I915_READ(LCPLL_CTL); | |
9403 | val |= LCPLL_POWER_DOWN_ALLOW; | |
9404 | I915_WRITE(LCPLL_CTL, val); | |
9405 | POSTING_READ(LCPLL_CTL); | |
9406 | } | |
9407 | } | |
9408 | ||
9409 | /* | |
9410 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
9411 | * source. | |
9412 | */ | |
6ff58d53 | 9413 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
9414 | { |
9415 | uint32_t val; | |
9416 | ||
9417 | val = I915_READ(LCPLL_CTL); | |
9418 | ||
9419 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
9420 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
9421 | return; | |
9422 | ||
a8a8bd54 PZ |
9423 | /* |
9424 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
9425 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 9426 | */ |
59bad947 | 9427 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 9428 | |
be256dc7 PZ |
9429 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
9430 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
9431 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 9432 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
9433 | } |
9434 | ||
9ccd5aeb | 9435 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
9436 | val |= D_COMP_COMP_FORCE; |
9437 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 9438 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9439 | |
9440 | val = I915_READ(LCPLL_CTL); | |
9441 | val &= ~LCPLL_PLL_DISABLE; | |
9442 | I915_WRITE(LCPLL_CTL, val); | |
9443 | ||
9444 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
9445 | DRM_ERROR("LCPLL not locked yet\n"); | |
9446 | ||
9447 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
9448 | val = I915_READ(LCPLL_CTL); | |
9449 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9450 | I915_WRITE(LCPLL_CTL, val); | |
9451 | ||
9452 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9453 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9454 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9455 | } | |
215733fa | 9456 | |
59bad947 | 9457 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b6283055 | 9458 | intel_update_cdclk(dev_priv->dev); |
be256dc7 PZ |
9459 | } |
9460 | ||
765dab67 PZ |
9461 | /* |
9462 | * Package states C8 and deeper are really deep PC states that can only be | |
9463 | * reached when all the devices on the system allow it, so even if the graphics | |
9464 | * device allows PC8+, it doesn't mean the system will actually get to these | |
9465 | * states. Our driver only allows PC8+ when going into runtime PM. | |
9466 | * | |
9467 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
9468 | * well is disabled and most interrupts are disabled, and these are also | |
9469 | * requirements for runtime PM. When these conditions are met, we manually do | |
9470 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
9471 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
9472 | * hang the machine. | |
9473 | * | |
9474 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
9475 | * the state of some registers, so when we come back from PC8+ we need to | |
9476 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
9477 | * need to take care of the registers kept by RC6. Notice that this happens even | |
9478 | * if we don't put the device in PCI D3 state (which is what currently happens | |
9479 | * because of the runtime PM support). | |
9480 | * | |
9481 | * For more, read "Display Sequences for Package C8" on the hardware | |
9482 | * documentation. | |
9483 | */ | |
a14cb6fc | 9484 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 9485 | { |
c67a470b PZ |
9486 | struct drm_device *dev = dev_priv->dev; |
9487 | uint32_t val; | |
9488 | ||
c67a470b PZ |
9489 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
9490 | ||
c2699524 | 9491 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9492 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9493 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
9494 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9495 | } | |
9496 | ||
9497 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
9498 | hsw_disable_lcpll(dev_priv, true, true); |
9499 | } | |
9500 | ||
a14cb6fc | 9501 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
9502 | { |
9503 | struct drm_device *dev = dev_priv->dev; | |
9504 | uint32_t val; | |
9505 | ||
c67a470b PZ |
9506 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
9507 | ||
9508 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
9509 | lpt_init_pch_refclk(dev); |
9510 | ||
c2699524 | 9511 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9512 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9513 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
9514 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9515 | } | |
c67a470b PZ |
9516 | } |
9517 | ||
27c329ed | 9518 | static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
f8437dd1 | 9519 | { |
a821fc46 | 9520 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
9521 | struct intel_atomic_state *old_intel_state = |
9522 | to_intel_atomic_state(old_state); | |
9523 | unsigned int req_cdclk = old_intel_state->dev_cdclk; | |
f8437dd1 | 9524 | |
27c329ed | 9525 | broxton_set_cdclk(dev, req_cdclk); |
f8437dd1 VK |
9526 | } |
9527 | ||
b432e5cf | 9528 | /* compute the max rate for new configuration */ |
27c329ed | 9529 | static int ilk_max_pixel_rate(struct drm_atomic_state *state) |
b432e5cf | 9530 | { |
565602d7 ML |
9531 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
9532 | struct drm_i915_private *dev_priv = state->dev->dev_private; | |
9533 | struct drm_crtc *crtc; | |
9534 | struct drm_crtc_state *cstate; | |
27c329ed | 9535 | struct intel_crtc_state *crtc_state; |
565602d7 ML |
9536 | unsigned max_pixel_rate = 0, i; |
9537 | enum pipe pipe; | |
b432e5cf | 9538 | |
565602d7 ML |
9539 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
9540 | sizeof(intel_state->min_pixclk)); | |
27c329ed | 9541 | |
565602d7 ML |
9542 | for_each_crtc_in_state(state, crtc, cstate, i) { |
9543 | int pixel_rate; | |
27c329ed | 9544 | |
565602d7 ML |
9545 | crtc_state = to_intel_crtc_state(cstate); |
9546 | if (!crtc_state->base.enable) { | |
9547 | intel_state->min_pixclk[i] = 0; | |
b432e5cf | 9548 | continue; |
565602d7 | 9549 | } |
b432e5cf | 9550 | |
27c329ed | 9551 | pixel_rate = ilk_pipe_pixel_rate(crtc_state); |
b432e5cf VS |
9552 | |
9553 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
565602d7 | 9554 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) |
b432e5cf VS |
9555 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); |
9556 | ||
565602d7 | 9557 | intel_state->min_pixclk[i] = pixel_rate; |
b432e5cf VS |
9558 | } |
9559 | ||
565602d7 ML |
9560 | for_each_pipe(dev_priv, pipe) |
9561 | max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate); | |
9562 | ||
b432e5cf VS |
9563 | return max_pixel_rate; |
9564 | } | |
9565 | ||
9566 | static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) | |
9567 | { | |
9568 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9569 | uint32_t val, data; | |
9570 | int ret; | |
9571 | ||
9572 | if (WARN((I915_READ(LCPLL_CTL) & | |
9573 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | | |
9574 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | | |
9575 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | | |
9576 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, | |
9577 | "trying to change cdclk frequency with cdclk not enabled\n")) | |
9578 | return; | |
9579 | ||
9580 | mutex_lock(&dev_priv->rps.hw_lock); | |
9581 | ret = sandybridge_pcode_write(dev_priv, | |
9582 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); | |
9583 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9584 | if (ret) { | |
9585 | DRM_ERROR("failed to inform pcode about cdclk change\n"); | |
9586 | return; | |
9587 | } | |
9588 | ||
9589 | val = I915_READ(LCPLL_CTL); | |
9590 | val |= LCPLL_CD_SOURCE_FCLK; | |
9591 | I915_WRITE(LCPLL_CTL, val); | |
9592 | ||
5ba00178 TU |
9593 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
9594 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
b432e5cf VS |
9595 | DRM_ERROR("Switching to FCLK failed\n"); |
9596 | ||
9597 | val = I915_READ(LCPLL_CTL); | |
9598 | val &= ~LCPLL_CLK_FREQ_MASK; | |
9599 | ||
9600 | switch (cdclk) { | |
9601 | case 450000: | |
9602 | val |= LCPLL_CLK_FREQ_450; | |
9603 | data = 0; | |
9604 | break; | |
9605 | case 540000: | |
9606 | val |= LCPLL_CLK_FREQ_54O_BDW; | |
9607 | data = 1; | |
9608 | break; | |
9609 | case 337500: | |
9610 | val |= LCPLL_CLK_FREQ_337_5_BDW; | |
9611 | data = 2; | |
9612 | break; | |
9613 | case 675000: | |
9614 | val |= LCPLL_CLK_FREQ_675_BDW; | |
9615 | data = 3; | |
9616 | break; | |
9617 | default: | |
9618 | WARN(1, "invalid cdclk frequency\n"); | |
9619 | return; | |
9620 | } | |
9621 | ||
9622 | I915_WRITE(LCPLL_CTL, val); | |
9623 | ||
9624 | val = I915_READ(LCPLL_CTL); | |
9625 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9626 | I915_WRITE(LCPLL_CTL, val); | |
9627 | ||
5ba00178 TU |
9628 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
9629 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
b432e5cf VS |
9630 | DRM_ERROR("Switching back to LCPLL failed\n"); |
9631 | ||
9632 | mutex_lock(&dev_priv->rps.hw_lock); | |
9633 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); | |
9634 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9635 | ||
9636 | intel_update_cdclk(dev); | |
9637 | ||
9638 | WARN(cdclk != dev_priv->cdclk_freq, | |
9639 | "cdclk requested %d kHz but got %d kHz\n", | |
9640 | cdclk, dev_priv->cdclk_freq); | |
9641 | } | |
9642 | ||
27c329ed | 9643 | static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state) |
b432e5cf | 9644 | { |
27c329ed | 9645 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
1a617b77 | 9646 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
27c329ed | 9647 | int max_pixclk = ilk_max_pixel_rate(state); |
b432e5cf VS |
9648 | int cdclk; |
9649 | ||
9650 | /* | |
9651 | * FIXME should also account for plane ratio | |
9652 | * once 64bpp pixel formats are supported. | |
9653 | */ | |
27c329ed | 9654 | if (max_pixclk > 540000) |
b432e5cf | 9655 | cdclk = 675000; |
27c329ed | 9656 | else if (max_pixclk > 450000) |
b432e5cf | 9657 | cdclk = 540000; |
27c329ed | 9658 | else if (max_pixclk > 337500) |
b432e5cf VS |
9659 | cdclk = 450000; |
9660 | else | |
9661 | cdclk = 337500; | |
9662 | ||
b432e5cf | 9663 | if (cdclk > dev_priv->max_cdclk_freq) { |
63ba534e ML |
9664 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", |
9665 | cdclk, dev_priv->max_cdclk_freq); | |
9666 | return -EINVAL; | |
b432e5cf VS |
9667 | } |
9668 | ||
1a617b77 ML |
9669 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; |
9670 | if (!intel_state->active_crtcs) | |
9671 | intel_state->dev_cdclk = 337500; | |
b432e5cf VS |
9672 | |
9673 | return 0; | |
9674 | } | |
9675 | ||
27c329ed | 9676 | static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
b432e5cf | 9677 | { |
27c329ed | 9678 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
9679 | struct intel_atomic_state *old_intel_state = |
9680 | to_intel_atomic_state(old_state); | |
9681 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
b432e5cf | 9682 | |
27c329ed | 9683 | broadwell_set_cdclk(dev, req_cdclk); |
b432e5cf VS |
9684 | } |
9685 | ||
190f68c5 ACO |
9686 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
9687 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 9688 | { |
af3997b5 MK |
9689 | struct intel_encoder *intel_encoder = |
9690 | intel_ddi_get_crtc_new_encoder(crtc_state); | |
9691 | ||
9692 | if (intel_encoder->type != INTEL_OUTPUT_DSI) { | |
9693 | if (!intel_ddi_pll_select(crtc, crtc_state)) | |
9694 | return -EINVAL; | |
9695 | } | |
716c2e55 | 9696 | |
c7653199 | 9697 | crtc->lowfreq_avail = false; |
644cef34 | 9698 | |
c8f7a0db | 9699 | return 0; |
79e53945 JB |
9700 | } |
9701 | ||
3760b59c S |
9702 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
9703 | enum port port, | |
9704 | struct intel_crtc_state *pipe_config) | |
9705 | { | |
8106ddbd ACO |
9706 | enum intel_dpll_id id; |
9707 | ||
3760b59c S |
9708 | switch (port) { |
9709 | case PORT_A: | |
9710 | pipe_config->ddi_pll_sel = SKL_DPLL0; | |
08250c4b | 9711 | id = DPLL_ID_SKL_DPLL0; |
3760b59c S |
9712 | break; |
9713 | case PORT_B: | |
9714 | pipe_config->ddi_pll_sel = SKL_DPLL1; | |
08250c4b | 9715 | id = DPLL_ID_SKL_DPLL1; |
3760b59c S |
9716 | break; |
9717 | case PORT_C: | |
9718 | pipe_config->ddi_pll_sel = SKL_DPLL2; | |
08250c4b | 9719 | id = DPLL_ID_SKL_DPLL2; |
3760b59c S |
9720 | break; |
9721 | default: | |
9722 | DRM_ERROR("Incorrect port type\n"); | |
8106ddbd | 9723 | return; |
3760b59c | 9724 | } |
8106ddbd ACO |
9725 | |
9726 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
3760b59c S |
9727 | } |
9728 | ||
96b7dfb7 S |
9729 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
9730 | enum port port, | |
5cec258b | 9731 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 9732 | { |
8106ddbd | 9733 | enum intel_dpll_id id; |
a3c988ea | 9734 | u32 temp; |
96b7dfb7 S |
9735 | |
9736 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
9737 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
9738 | ||
9739 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 | 9740 | case SKL_DPLL0: |
a3c988ea ACO |
9741 | id = DPLL_ID_SKL_DPLL0; |
9742 | break; | |
96b7dfb7 | 9743 | case SKL_DPLL1: |
8106ddbd | 9744 | id = DPLL_ID_SKL_DPLL1; |
96b7dfb7 S |
9745 | break; |
9746 | case SKL_DPLL2: | |
8106ddbd | 9747 | id = DPLL_ID_SKL_DPLL2; |
96b7dfb7 S |
9748 | break; |
9749 | case SKL_DPLL3: | |
8106ddbd | 9750 | id = DPLL_ID_SKL_DPLL3; |
96b7dfb7 | 9751 | break; |
8106ddbd ACO |
9752 | default: |
9753 | MISSING_CASE(pipe_config->ddi_pll_sel); | |
9754 | return; | |
96b7dfb7 | 9755 | } |
8106ddbd ACO |
9756 | |
9757 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
96b7dfb7 S |
9758 | } |
9759 | ||
7d2c8175 DL |
9760 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
9761 | enum port port, | |
5cec258b | 9762 | struct intel_crtc_state *pipe_config) |
7d2c8175 | 9763 | { |
8106ddbd ACO |
9764 | enum intel_dpll_id id; |
9765 | ||
7d2c8175 DL |
9766 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); |
9767 | ||
9768 | switch (pipe_config->ddi_pll_sel) { | |
9769 | case PORT_CLK_SEL_WRPLL1: | |
8106ddbd | 9770 | id = DPLL_ID_WRPLL1; |
7d2c8175 DL |
9771 | break; |
9772 | case PORT_CLK_SEL_WRPLL2: | |
8106ddbd | 9773 | id = DPLL_ID_WRPLL2; |
7d2c8175 | 9774 | break; |
00490c22 | 9775 | case PORT_CLK_SEL_SPLL: |
8106ddbd | 9776 | id = DPLL_ID_SPLL; |
79bd23da | 9777 | break; |
9d16da65 ACO |
9778 | case PORT_CLK_SEL_LCPLL_810: |
9779 | id = DPLL_ID_LCPLL_810; | |
9780 | break; | |
9781 | case PORT_CLK_SEL_LCPLL_1350: | |
9782 | id = DPLL_ID_LCPLL_1350; | |
9783 | break; | |
9784 | case PORT_CLK_SEL_LCPLL_2700: | |
9785 | id = DPLL_ID_LCPLL_2700; | |
9786 | break; | |
8106ddbd ACO |
9787 | default: |
9788 | MISSING_CASE(pipe_config->ddi_pll_sel); | |
9789 | /* fall through */ | |
9790 | case PORT_CLK_SEL_NONE: | |
8106ddbd | 9791 | return; |
7d2c8175 | 9792 | } |
8106ddbd ACO |
9793 | |
9794 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
7d2c8175 DL |
9795 | } |
9796 | ||
cf30429e JN |
9797 | static bool hsw_get_transcoder_state(struct intel_crtc *crtc, |
9798 | struct intel_crtc_state *pipe_config, | |
9799 | unsigned long *power_domain_mask) | |
9800 | { | |
9801 | struct drm_device *dev = crtc->base.dev; | |
9802 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9803 | enum intel_display_power_domain power_domain; | |
9804 | u32 tmp; | |
9805 | ||
9806 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; | |
9807 | ||
9808 | /* | |
9809 | * XXX: Do intel_display_power_get_if_enabled before reading this (for | |
9810 | * consistency and less surprising code; it's in always on power). | |
9811 | */ | |
9812 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
9813 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
9814 | enum pipe trans_edp_pipe; | |
9815 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
9816 | default: | |
9817 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
9818 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
9819 | case TRANS_DDI_EDP_INPUT_A_ON: | |
9820 | trans_edp_pipe = PIPE_A; | |
9821 | break; | |
9822 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
9823 | trans_edp_pipe = PIPE_B; | |
9824 | break; | |
9825 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
9826 | trans_edp_pipe = PIPE_C; | |
9827 | break; | |
9828 | } | |
9829 | ||
9830 | if (trans_edp_pipe == crtc->pipe) | |
9831 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
9832 | } | |
9833 | ||
9834 | power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); | |
9835 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
9836 | return false; | |
9837 | *power_domain_mask |= BIT(power_domain); | |
9838 | ||
9839 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); | |
9840 | ||
9841 | return tmp & PIPECONF_ENABLE; | |
9842 | } | |
9843 | ||
4d1de975 JN |
9844 | static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, |
9845 | struct intel_crtc_state *pipe_config, | |
9846 | unsigned long *power_domain_mask) | |
9847 | { | |
9848 | struct drm_device *dev = crtc->base.dev; | |
9849 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9850 | enum intel_display_power_domain power_domain; | |
9851 | enum port port; | |
9852 | enum transcoder cpu_transcoder; | |
9853 | u32 tmp; | |
9854 | ||
9855 | pipe_config->has_dsi_encoder = false; | |
9856 | ||
9857 | for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { | |
9858 | if (port == PORT_A) | |
9859 | cpu_transcoder = TRANSCODER_DSI_A; | |
9860 | else | |
9861 | cpu_transcoder = TRANSCODER_DSI_C; | |
9862 | ||
9863 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
9864 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
9865 | continue; | |
9866 | *power_domain_mask |= BIT(power_domain); | |
9867 | ||
9868 | /* XXX: this works for video mode only */ | |
9869 | tmp = I915_READ(BXT_MIPI_PORT_CTRL(port)); | |
9870 | if (!(tmp & DPI_ENABLE)) | |
9871 | continue; | |
9872 | ||
9873 | tmp = I915_READ(MIPI_CTRL(port)); | |
9874 | if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) | |
9875 | continue; | |
9876 | ||
9877 | pipe_config->cpu_transcoder = cpu_transcoder; | |
9878 | pipe_config->has_dsi_encoder = true; | |
9879 | break; | |
9880 | } | |
9881 | ||
9882 | return pipe_config->has_dsi_encoder; | |
9883 | } | |
9884 | ||
26804afd | 9885 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 9886 | struct intel_crtc_state *pipe_config) |
26804afd DV |
9887 | { |
9888 | struct drm_device *dev = crtc->base.dev; | |
9889 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 9890 | struct intel_shared_dpll *pll; |
26804afd DV |
9891 | enum port port; |
9892 | uint32_t tmp; | |
9893 | ||
9894 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
9895 | ||
9896 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
9897 | ||
ef11bdb3 | 9898 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
96b7dfb7 | 9899 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
3760b59c S |
9900 | else if (IS_BROXTON(dev)) |
9901 | bxt_get_ddi_pll(dev_priv, port, pipe_config); | |
96b7dfb7 S |
9902 | else |
9903 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 9904 | |
8106ddbd ACO |
9905 | pll = pipe_config->shared_dpll; |
9906 | if (pll) { | |
2edd6443 ACO |
9907 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
9908 | &pipe_config->dpll_hw_state)); | |
d452c5b6 DV |
9909 | } |
9910 | ||
26804afd DV |
9911 | /* |
9912 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
9913 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
9914 | * the PCH transcoder is on. | |
9915 | */ | |
ca370455 DL |
9916 | if (INTEL_INFO(dev)->gen < 9 && |
9917 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
9918 | pipe_config->has_pch_encoder = true; |
9919 | ||
9920 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
9921 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9922 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
9923 | ||
9924 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
9925 | } | |
9926 | } | |
9927 | ||
0e8ffe1b | 9928 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9929 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9930 | { |
9931 | struct drm_device *dev = crtc->base.dev; | |
9932 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1729050e ID |
9933 | enum intel_display_power_domain power_domain; |
9934 | unsigned long power_domain_mask; | |
cf30429e | 9935 | bool active; |
0e8ffe1b | 9936 | |
1729050e ID |
9937 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
9938 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 | 9939 | return false; |
1729050e ID |
9940 | power_domain_mask = BIT(power_domain); |
9941 | ||
8106ddbd | 9942 | pipe_config->shared_dpll = NULL; |
c0d43d62 | 9943 | |
cf30429e | 9944 | active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask); |
eccb140b | 9945 | |
4d1de975 JN |
9946 | if (IS_BROXTON(dev_priv)) { |
9947 | bxt_get_dsi_transcoder_state(crtc, pipe_config, | |
9948 | &power_domain_mask); | |
9949 | WARN_ON(active && pipe_config->has_dsi_encoder); | |
9950 | if (pipe_config->has_dsi_encoder) | |
9951 | active = true; | |
9952 | } | |
9953 | ||
cf30429e | 9954 | if (!active) |
1729050e | 9955 | goto out; |
0e8ffe1b | 9956 | |
4d1de975 JN |
9957 | if (!pipe_config->has_dsi_encoder) { |
9958 | haswell_get_ddi_port_state(crtc, pipe_config); | |
9959 | intel_get_pipe_timings(crtc, pipe_config); | |
9960 | } | |
627eb5a3 | 9961 | |
bc58be60 | 9962 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 9963 | |
05dc698c LL |
9964 | pipe_config->gamma_mode = |
9965 | I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; | |
9966 | ||
a1b2278e CK |
9967 | if (INTEL_INFO(dev)->gen >= 9) { |
9968 | skl_init_scalers(dev, crtc, pipe_config); | |
9969 | } | |
9970 | ||
af99ceda CK |
9971 | if (INTEL_INFO(dev)->gen >= 9) { |
9972 | pipe_config->scaler_state.scaler_id = -1; | |
9973 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
9974 | } | |
9975 | ||
1729050e ID |
9976 | power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
9977 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
9978 | power_domain_mask |= BIT(power_domain); | |
1c132b44 | 9979 | if (INTEL_INFO(dev)->gen >= 9) |
bd2e244f | 9980 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 9981 | else |
1c132b44 | 9982 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 9983 | } |
88adfff1 | 9984 | |
e59150dc JB |
9985 | if (IS_HASWELL(dev)) |
9986 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
9987 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 9988 | |
4d1de975 JN |
9989 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP && |
9990 | !transcoder_is_dsi(pipe_config->cpu_transcoder)) { | |
ebb69c95 CT |
9991 | pipe_config->pixel_multiplier = |
9992 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
9993 | } else { | |
9994 | pipe_config->pixel_multiplier = 1; | |
9995 | } | |
6c49f241 | 9996 | |
1729050e ID |
9997 | out: |
9998 | for_each_power_domain(power_domain, power_domain_mask) | |
9999 | intel_display_power_put(dev_priv, power_domain); | |
10000 | ||
cf30429e | 10001 | return active; |
0e8ffe1b DV |
10002 | } |
10003 | ||
55a08b3f ML |
10004 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base, |
10005 | const struct intel_plane_state *plane_state) | |
560b85bb CW |
10006 | { |
10007 | struct drm_device *dev = crtc->dev; | |
10008 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10009 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 10010 | uint32_t cntl = 0, size = 0; |
560b85bb | 10011 | |
55a08b3f ML |
10012 | if (plane_state && plane_state->visible) { |
10013 | unsigned int width = plane_state->base.crtc_w; | |
10014 | unsigned int height = plane_state->base.crtc_h; | |
dc41c154 VS |
10015 | unsigned int stride = roundup_pow_of_two(width) * 4; |
10016 | ||
10017 | switch (stride) { | |
10018 | default: | |
10019 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
10020 | width, stride); | |
10021 | stride = 256; | |
10022 | /* fallthrough */ | |
10023 | case 256: | |
10024 | case 512: | |
10025 | case 1024: | |
10026 | case 2048: | |
10027 | break; | |
4b0e333e CW |
10028 | } |
10029 | ||
dc41c154 VS |
10030 | cntl |= CURSOR_ENABLE | |
10031 | CURSOR_GAMMA_ENABLE | | |
10032 | CURSOR_FORMAT_ARGB | | |
10033 | CURSOR_STRIDE(stride); | |
10034 | ||
10035 | size = (height << 12) | width; | |
4b0e333e | 10036 | } |
560b85bb | 10037 | |
dc41c154 VS |
10038 | if (intel_crtc->cursor_cntl != 0 && |
10039 | (intel_crtc->cursor_base != base || | |
10040 | intel_crtc->cursor_size != size || | |
10041 | intel_crtc->cursor_cntl != cntl)) { | |
10042 | /* On these chipsets we can only modify the base/size/stride | |
10043 | * whilst the cursor is disabled. | |
10044 | */ | |
0b87c24e VS |
10045 | I915_WRITE(CURCNTR(PIPE_A), 0); |
10046 | POSTING_READ(CURCNTR(PIPE_A)); | |
dc41c154 | 10047 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 10048 | } |
560b85bb | 10049 | |
99d1f387 | 10050 | if (intel_crtc->cursor_base != base) { |
0b87c24e | 10051 | I915_WRITE(CURBASE(PIPE_A), base); |
99d1f387 VS |
10052 | intel_crtc->cursor_base = base; |
10053 | } | |
4726e0b0 | 10054 | |
dc41c154 VS |
10055 | if (intel_crtc->cursor_size != size) { |
10056 | I915_WRITE(CURSIZE, size); | |
10057 | intel_crtc->cursor_size = size; | |
4b0e333e | 10058 | } |
560b85bb | 10059 | |
4b0e333e | 10060 | if (intel_crtc->cursor_cntl != cntl) { |
0b87c24e VS |
10061 | I915_WRITE(CURCNTR(PIPE_A), cntl); |
10062 | POSTING_READ(CURCNTR(PIPE_A)); | |
4b0e333e | 10063 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 10064 | } |
560b85bb CW |
10065 | } |
10066 | ||
55a08b3f ML |
10067 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, |
10068 | const struct intel_plane_state *plane_state) | |
65a21cd6 JB |
10069 | { |
10070 | struct drm_device *dev = crtc->dev; | |
10071 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10072 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10073 | int pipe = intel_crtc->pipe; | |
663f3122 | 10074 | uint32_t cntl = 0; |
4b0e333e | 10075 | |
55a08b3f | 10076 | if (plane_state && plane_state->visible) { |
4b0e333e | 10077 | cntl = MCURSOR_GAMMA_ENABLE; |
55a08b3f | 10078 | switch (plane_state->base.crtc_w) { |
4726e0b0 SK |
10079 | case 64: |
10080 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
10081 | break; | |
10082 | case 128: | |
10083 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
10084 | break; | |
10085 | case 256: | |
10086 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
10087 | break; | |
10088 | default: | |
55a08b3f | 10089 | MISSING_CASE(plane_state->base.crtc_w); |
4726e0b0 | 10090 | return; |
65a21cd6 | 10091 | } |
4b0e333e | 10092 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 | 10093 | |
fc6f93bc | 10094 | if (HAS_DDI(dev)) |
47bf17a7 | 10095 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
65a21cd6 | 10096 | |
55a08b3f ML |
10097 | if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) |
10098 | cntl |= CURSOR_ROTATE_180; | |
10099 | } | |
4398ad45 | 10100 | |
4b0e333e CW |
10101 | if (intel_crtc->cursor_cntl != cntl) { |
10102 | I915_WRITE(CURCNTR(pipe), cntl); | |
10103 | POSTING_READ(CURCNTR(pipe)); | |
10104 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 10105 | } |
4b0e333e | 10106 | |
65a21cd6 | 10107 | /* and commit changes on next vblank */ |
5efb3e28 VS |
10108 | I915_WRITE(CURBASE(pipe), base); |
10109 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
10110 | |
10111 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
10112 | } |
10113 | ||
cda4b7d3 | 10114 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f | 10115 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
55a08b3f | 10116 | const struct intel_plane_state *plane_state) |
cda4b7d3 CW |
10117 | { |
10118 | struct drm_device *dev = crtc->dev; | |
10119 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10120 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10121 | int pipe = intel_crtc->pipe; | |
55a08b3f ML |
10122 | u32 base = intel_crtc->cursor_addr; |
10123 | u32 pos = 0; | |
cda4b7d3 | 10124 | |
55a08b3f ML |
10125 | if (plane_state) { |
10126 | int x = plane_state->base.crtc_x; | |
10127 | int y = plane_state->base.crtc_y; | |
cda4b7d3 | 10128 | |
55a08b3f ML |
10129 | if (x < 0) { |
10130 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
10131 | x = -x; | |
10132 | } | |
10133 | pos |= x << CURSOR_X_SHIFT; | |
cda4b7d3 | 10134 | |
55a08b3f ML |
10135 | if (y < 0) { |
10136 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
10137 | y = -y; | |
10138 | } | |
10139 | pos |= y << CURSOR_Y_SHIFT; | |
10140 | ||
10141 | /* ILK+ do this automagically */ | |
10142 | if (HAS_GMCH_DISPLAY(dev) && | |
10143 | plane_state->base.rotation == BIT(DRM_ROTATE_180)) { | |
10144 | base += (plane_state->base.crtc_h * | |
10145 | plane_state->base.crtc_w - 1) * 4; | |
10146 | } | |
cda4b7d3 | 10147 | } |
cda4b7d3 | 10148 | |
5efb3e28 VS |
10149 | I915_WRITE(CURPOS(pipe), pos); |
10150 | ||
8ac54669 | 10151 | if (IS_845G(dev) || IS_I865G(dev)) |
55a08b3f | 10152 | i845_update_cursor(crtc, base, plane_state); |
5efb3e28 | 10153 | else |
55a08b3f | 10154 | i9xx_update_cursor(crtc, base, plane_state); |
cda4b7d3 CW |
10155 | } |
10156 | ||
dc41c154 VS |
10157 | static bool cursor_size_ok(struct drm_device *dev, |
10158 | uint32_t width, uint32_t height) | |
10159 | { | |
10160 | if (width == 0 || height == 0) | |
10161 | return false; | |
10162 | ||
10163 | /* | |
10164 | * 845g/865g are special in that they are only limited by | |
10165 | * the width of their cursors, the height is arbitrary up to | |
10166 | * the precision of the register. Everything else requires | |
10167 | * square cursors, limited to a few power-of-two sizes. | |
10168 | */ | |
10169 | if (IS_845G(dev) || IS_I865G(dev)) { | |
10170 | if ((width & 63) != 0) | |
10171 | return false; | |
10172 | ||
10173 | if (width > (IS_845G(dev) ? 64 : 512)) | |
10174 | return false; | |
10175 | ||
10176 | if (height > 1023) | |
10177 | return false; | |
10178 | } else { | |
10179 | switch (width | height) { | |
10180 | case 256: | |
10181 | case 128: | |
10182 | if (IS_GEN2(dev)) | |
10183 | return false; | |
10184 | case 64: | |
10185 | break; | |
10186 | default: | |
10187 | return false; | |
10188 | } | |
10189 | } | |
10190 | ||
10191 | return true; | |
10192 | } | |
10193 | ||
79e53945 JB |
10194 | /* VESA 640x480x72Hz mode to set on the pipe */ |
10195 | static struct drm_display_mode load_detect_mode = { | |
10196 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
10197 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
10198 | }; | |
10199 | ||
a8bb6818 DV |
10200 | struct drm_framebuffer * |
10201 | __intel_framebuffer_create(struct drm_device *dev, | |
10202 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10203 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
10204 | { |
10205 | struct intel_framebuffer *intel_fb; | |
10206 | int ret; | |
10207 | ||
10208 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
dcb1394e | 10209 | if (!intel_fb) |
d2dff872 | 10210 | return ERR_PTR(-ENOMEM); |
d2dff872 CW |
10211 | |
10212 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
10213 | if (ret) |
10214 | goto err; | |
d2dff872 CW |
10215 | |
10216 | return &intel_fb->base; | |
dcb1394e | 10217 | |
dd4916c5 | 10218 | err: |
dd4916c5 | 10219 | kfree(intel_fb); |
dd4916c5 | 10220 | return ERR_PTR(ret); |
d2dff872 CW |
10221 | } |
10222 | ||
b5ea642a | 10223 | static struct drm_framebuffer * |
a8bb6818 DV |
10224 | intel_framebuffer_create(struct drm_device *dev, |
10225 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10226 | struct drm_i915_gem_object *obj) | |
10227 | { | |
10228 | struct drm_framebuffer *fb; | |
10229 | int ret; | |
10230 | ||
10231 | ret = i915_mutex_lock_interruptible(dev); | |
10232 | if (ret) | |
10233 | return ERR_PTR(ret); | |
10234 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
10235 | mutex_unlock(&dev->struct_mutex); | |
10236 | ||
10237 | return fb; | |
10238 | } | |
10239 | ||
d2dff872 CW |
10240 | static u32 |
10241 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
10242 | { | |
10243 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
10244 | return ALIGN(pitch, 64); | |
10245 | } | |
10246 | ||
10247 | static u32 | |
10248 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
10249 | { | |
10250 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 10251 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
10252 | } |
10253 | ||
10254 | static struct drm_framebuffer * | |
10255 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
10256 | struct drm_display_mode *mode, | |
10257 | int depth, int bpp) | |
10258 | { | |
dcb1394e | 10259 | struct drm_framebuffer *fb; |
d2dff872 | 10260 | struct drm_i915_gem_object *obj; |
0fed39bd | 10261 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
10262 | |
10263 | obj = i915_gem_alloc_object(dev, | |
10264 | intel_framebuffer_size_for_mode(mode, bpp)); | |
10265 | if (obj == NULL) | |
10266 | return ERR_PTR(-ENOMEM); | |
10267 | ||
10268 | mode_cmd.width = mode->hdisplay; | |
10269 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
10270 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
10271 | bpp); | |
5ca0c34a | 10272 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 | 10273 | |
dcb1394e LW |
10274 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
10275 | if (IS_ERR(fb)) | |
10276 | drm_gem_object_unreference_unlocked(&obj->base); | |
10277 | ||
10278 | return fb; | |
d2dff872 CW |
10279 | } |
10280 | ||
10281 | static struct drm_framebuffer * | |
10282 | mode_fits_in_fbdev(struct drm_device *dev, | |
10283 | struct drm_display_mode *mode) | |
10284 | { | |
0695726e | 10285 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
d2dff872 CW |
10286 | struct drm_i915_private *dev_priv = dev->dev_private; |
10287 | struct drm_i915_gem_object *obj; | |
10288 | struct drm_framebuffer *fb; | |
10289 | ||
4c0e5528 | 10290 | if (!dev_priv->fbdev) |
d2dff872 CW |
10291 | return NULL; |
10292 | ||
4c0e5528 | 10293 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
10294 | return NULL; |
10295 | ||
4c0e5528 DV |
10296 | obj = dev_priv->fbdev->fb->obj; |
10297 | BUG_ON(!obj); | |
10298 | ||
8bcd4553 | 10299 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
10300 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
10301 | fb->bits_per_pixel)) | |
d2dff872 CW |
10302 | return NULL; |
10303 | ||
01f2c773 | 10304 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
10305 | return NULL; |
10306 | ||
edde3617 | 10307 | drm_framebuffer_reference(fb); |
d2dff872 | 10308 | return fb; |
4520f53a DV |
10309 | #else |
10310 | return NULL; | |
10311 | #endif | |
d2dff872 CW |
10312 | } |
10313 | ||
d3a40d1b ACO |
10314 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
10315 | struct drm_crtc *crtc, | |
10316 | struct drm_display_mode *mode, | |
10317 | struct drm_framebuffer *fb, | |
10318 | int x, int y) | |
10319 | { | |
10320 | struct drm_plane_state *plane_state; | |
10321 | int hdisplay, vdisplay; | |
10322 | int ret; | |
10323 | ||
10324 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
10325 | if (IS_ERR(plane_state)) | |
10326 | return PTR_ERR(plane_state); | |
10327 | ||
10328 | if (mode) | |
10329 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); | |
10330 | else | |
10331 | hdisplay = vdisplay = 0; | |
10332 | ||
10333 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
10334 | if (ret) | |
10335 | return ret; | |
10336 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
10337 | plane_state->crtc_x = 0; | |
10338 | plane_state->crtc_y = 0; | |
10339 | plane_state->crtc_w = hdisplay; | |
10340 | plane_state->crtc_h = vdisplay; | |
10341 | plane_state->src_x = x << 16; | |
10342 | plane_state->src_y = y << 16; | |
10343 | plane_state->src_w = hdisplay << 16; | |
10344 | plane_state->src_h = vdisplay << 16; | |
10345 | ||
10346 | return 0; | |
10347 | } | |
10348 | ||
d2434ab7 | 10349 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 10350 | struct drm_display_mode *mode, |
51fd371b RC |
10351 | struct intel_load_detect_pipe *old, |
10352 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
10353 | { |
10354 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
10355 | struct intel_encoder *intel_encoder = |
10356 | intel_attached_encoder(connector); | |
79e53945 | 10357 | struct drm_crtc *possible_crtc; |
4ef69c7a | 10358 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
10359 | struct drm_crtc *crtc = NULL; |
10360 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 10361 | struct drm_framebuffer *fb; |
51fd371b | 10362 | struct drm_mode_config *config = &dev->mode_config; |
edde3617 | 10363 | struct drm_atomic_state *state = NULL, *restore_state = NULL; |
944b0c76 | 10364 | struct drm_connector_state *connector_state; |
4be07317 | 10365 | struct intel_crtc_state *crtc_state; |
51fd371b | 10366 | int ret, i = -1; |
79e53945 | 10367 | |
d2dff872 | 10368 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10369 | connector->base.id, connector->name, |
8e329a03 | 10370 | encoder->base.id, encoder->name); |
d2dff872 | 10371 | |
edde3617 ML |
10372 | old->restore_state = NULL; |
10373 | ||
51fd371b RC |
10374 | retry: |
10375 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
10376 | if (ret) | |
ad3c558f | 10377 | goto fail; |
6e9f798d | 10378 | |
79e53945 JB |
10379 | /* |
10380 | * Algorithm gets a little messy: | |
7a5e4805 | 10381 | * |
79e53945 JB |
10382 | * - if the connector already has an assigned crtc, use it (but make |
10383 | * sure it's on first) | |
7a5e4805 | 10384 | * |
79e53945 JB |
10385 | * - try to find the first unused crtc that can drive this connector, |
10386 | * and use that if we find one | |
79e53945 JB |
10387 | */ |
10388 | ||
10389 | /* See if we already have a CRTC for this connector */ | |
edde3617 ML |
10390 | if (connector->state->crtc) { |
10391 | crtc = connector->state->crtc; | |
8261b191 | 10392 | |
51fd371b | 10393 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 10394 | if (ret) |
ad3c558f | 10395 | goto fail; |
8261b191 CW |
10396 | |
10397 | /* Make sure the crtc and connector are running */ | |
edde3617 | 10398 | goto found; |
79e53945 JB |
10399 | } |
10400 | ||
10401 | /* Find an unused one (if possible) */ | |
70e1e0ec | 10402 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
10403 | i++; |
10404 | if (!(encoder->possible_crtcs & (1 << i))) | |
10405 | continue; | |
edde3617 ML |
10406 | |
10407 | ret = drm_modeset_lock(&possible_crtc->mutex, ctx); | |
10408 | if (ret) | |
10409 | goto fail; | |
10410 | ||
10411 | if (possible_crtc->state->enable) { | |
10412 | drm_modeset_unlock(&possible_crtc->mutex); | |
a459249c | 10413 | continue; |
edde3617 | 10414 | } |
a459249c VS |
10415 | |
10416 | crtc = possible_crtc; | |
10417 | break; | |
79e53945 JB |
10418 | } |
10419 | ||
10420 | /* | |
10421 | * If we didn't find an unused CRTC, don't use any. | |
10422 | */ | |
10423 | if (!crtc) { | |
7173188d | 10424 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
ad3c558f | 10425 | goto fail; |
79e53945 JB |
10426 | } |
10427 | ||
edde3617 ML |
10428 | found: |
10429 | intel_crtc = to_intel_crtc(crtc); | |
10430 | ||
4d02e2de DV |
10431 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
10432 | if (ret) | |
ad3c558f | 10433 | goto fail; |
79e53945 | 10434 | |
83a57153 | 10435 | state = drm_atomic_state_alloc(dev); |
edde3617 ML |
10436 | restore_state = drm_atomic_state_alloc(dev); |
10437 | if (!state || !restore_state) { | |
10438 | ret = -ENOMEM; | |
10439 | goto fail; | |
10440 | } | |
83a57153 ACO |
10441 | |
10442 | state->acquire_ctx = ctx; | |
edde3617 | 10443 | restore_state->acquire_ctx = ctx; |
83a57153 | 10444 | |
944b0c76 ACO |
10445 | connector_state = drm_atomic_get_connector_state(state, connector); |
10446 | if (IS_ERR(connector_state)) { | |
10447 | ret = PTR_ERR(connector_state); | |
10448 | goto fail; | |
10449 | } | |
10450 | ||
edde3617 ML |
10451 | ret = drm_atomic_set_crtc_for_connector(connector_state, crtc); |
10452 | if (ret) | |
10453 | goto fail; | |
944b0c76 | 10454 | |
4be07317 ACO |
10455 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10456 | if (IS_ERR(crtc_state)) { | |
10457 | ret = PTR_ERR(crtc_state); | |
10458 | goto fail; | |
10459 | } | |
10460 | ||
49d6fa21 | 10461 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 10462 | |
6492711d CW |
10463 | if (!mode) |
10464 | mode = &load_detect_mode; | |
79e53945 | 10465 | |
d2dff872 CW |
10466 | /* We need a framebuffer large enough to accommodate all accesses |
10467 | * that the plane may generate whilst we perform load detection. | |
10468 | * We can not rely on the fbcon either being present (we get called | |
10469 | * during its initialisation to detect all boot displays, or it may | |
10470 | * not even exist) or that it is large enough to satisfy the | |
10471 | * requested mode. | |
10472 | */ | |
94352cf9 DV |
10473 | fb = mode_fits_in_fbdev(dev, mode); |
10474 | if (fb == NULL) { | |
d2dff872 | 10475 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 | 10476 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
d2dff872 CW |
10477 | } else |
10478 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 10479 | if (IS_ERR(fb)) { |
d2dff872 | 10480 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 10481 | goto fail; |
79e53945 | 10482 | } |
79e53945 | 10483 | |
d3a40d1b ACO |
10484 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
10485 | if (ret) | |
10486 | goto fail; | |
10487 | ||
edde3617 ML |
10488 | drm_framebuffer_unreference(fb); |
10489 | ||
10490 | ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode); | |
10491 | if (ret) | |
10492 | goto fail; | |
10493 | ||
10494 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); | |
10495 | if (!ret) | |
10496 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc)); | |
10497 | if (!ret) | |
10498 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary)); | |
10499 | if (ret) { | |
10500 | DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret); | |
10501 | goto fail; | |
10502 | } | |
8c7b5ccb | 10503 | |
3ba86073 ML |
10504 | ret = drm_atomic_commit(state); |
10505 | if (ret) { | |
6492711d | 10506 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
412b61d8 | 10507 | goto fail; |
79e53945 | 10508 | } |
edde3617 ML |
10509 | |
10510 | old->restore_state = restore_state; | |
7173188d | 10511 | |
79e53945 | 10512 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 10513 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 10514 | return true; |
412b61d8 | 10515 | |
ad3c558f | 10516 | fail: |
e5d958ef | 10517 | drm_atomic_state_free(state); |
edde3617 ML |
10518 | drm_atomic_state_free(restore_state); |
10519 | restore_state = state = NULL; | |
83a57153 | 10520 | |
51fd371b RC |
10521 | if (ret == -EDEADLK) { |
10522 | drm_modeset_backoff(ctx); | |
10523 | goto retry; | |
10524 | } | |
10525 | ||
412b61d8 | 10526 | return false; |
79e53945 JB |
10527 | } |
10528 | ||
d2434ab7 | 10529 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
10530 | struct intel_load_detect_pipe *old, |
10531 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 10532 | { |
d2434ab7 DV |
10533 | struct intel_encoder *intel_encoder = |
10534 | intel_attached_encoder(connector); | |
4ef69c7a | 10535 | struct drm_encoder *encoder = &intel_encoder->base; |
edde3617 | 10536 | struct drm_atomic_state *state = old->restore_state; |
d3a40d1b | 10537 | int ret; |
79e53945 | 10538 | |
d2dff872 | 10539 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10540 | connector->base.id, connector->name, |
8e329a03 | 10541 | encoder->base.id, encoder->name); |
d2dff872 | 10542 | |
edde3617 | 10543 | if (!state) |
0622a53c | 10544 | return; |
79e53945 | 10545 | |
edde3617 ML |
10546 | ret = drm_atomic_commit(state); |
10547 | if (ret) { | |
10548 | DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret); | |
10549 | drm_atomic_state_free(state); | |
10550 | } | |
79e53945 JB |
10551 | } |
10552 | ||
da4a1efa | 10553 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 10554 | const struct intel_crtc_state *pipe_config) |
da4a1efa VS |
10555 | { |
10556 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10557 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
10558 | ||
10559 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 10560 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
10561 | else if (HAS_PCH_SPLIT(dev)) |
10562 | return 120000; | |
10563 | else if (!IS_GEN2(dev)) | |
10564 | return 96000; | |
10565 | else | |
10566 | return 48000; | |
10567 | } | |
10568 | ||
79e53945 | 10569 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 10570 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 10571 | struct intel_crtc_state *pipe_config) |
79e53945 | 10572 | { |
f1f644dc | 10573 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 10574 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 10575 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 10576 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
10577 | u32 fp; |
10578 | intel_clock_t clock; | |
dccbea3b | 10579 | int port_clock; |
da4a1efa | 10580 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
10581 | |
10582 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 10583 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 10584 | else |
293623f7 | 10585 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
10586 | |
10587 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
10588 | if (IS_PINEVIEW(dev)) { |
10589 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
10590 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
10591 | } else { |
10592 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
10593 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
10594 | } | |
10595 | ||
a6c45cf0 | 10596 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
10597 | if (IS_PINEVIEW(dev)) |
10598 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
10599 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
10600 | else |
10601 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
10602 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
10603 | ||
10604 | switch (dpll & DPLL_MODE_MASK) { | |
10605 | case DPLLB_MODE_DAC_SERIAL: | |
10606 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
10607 | 5 : 10; | |
10608 | break; | |
10609 | case DPLLB_MODE_LVDS: | |
10610 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
10611 | 7 : 14; | |
10612 | break; | |
10613 | default: | |
28c97730 | 10614 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 10615 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 10616 | return; |
79e53945 JB |
10617 | } |
10618 | ||
ac58c3f0 | 10619 | if (IS_PINEVIEW(dev)) |
dccbea3b | 10620 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 10621 | else |
dccbea3b | 10622 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 10623 | } else { |
0fb58223 | 10624 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 10625 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
10626 | |
10627 | if (is_lvds) { | |
10628 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
10629 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
10630 | |
10631 | if (lvds & LVDS_CLKB_POWER_UP) | |
10632 | clock.p2 = 7; | |
10633 | else | |
10634 | clock.p2 = 14; | |
79e53945 JB |
10635 | } else { |
10636 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
10637 | clock.p1 = 2; | |
10638 | else { | |
10639 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
10640 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
10641 | } | |
10642 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
10643 | clock.p2 = 4; | |
10644 | else | |
10645 | clock.p2 = 2; | |
79e53945 | 10646 | } |
da4a1efa | 10647 | |
dccbea3b | 10648 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
10649 | } |
10650 | ||
18442d08 VS |
10651 | /* |
10652 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 10653 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
10654 | * encoder's get_config() function. |
10655 | */ | |
dccbea3b | 10656 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
10657 | } |
10658 | ||
6878da05 VS |
10659 | int intel_dotclock_calculate(int link_freq, |
10660 | const struct intel_link_m_n *m_n) | |
f1f644dc | 10661 | { |
f1f644dc JB |
10662 | /* |
10663 | * The calculation for the data clock is: | |
1041a02f | 10664 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 10665 | * But we want to avoid losing precison if possible, so: |
1041a02f | 10666 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
10667 | * |
10668 | * and the link clock is simpler: | |
1041a02f | 10669 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
10670 | */ |
10671 | ||
6878da05 VS |
10672 | if (!m_n->link_n) |
10673 | return 0; | |
f1f644dc | 10674 | |
6878da05 VS |
10675 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
10676 | } | |
f1f644dc | 10677 | |
18442d08 | 10678 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 10679 | struct intel_crtc_state *pipe_config) |
6878da05 | 10680 | { |
e3b247da | 10681 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
79e53945 | 10682 | |
18442d08 VS |
10683 | /* read out port_clock from the DPLL */ |
10684 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 10685 | |
f1f644dc | 10686 | /* |
e3b247da VS |
10687 | * In case there is an active pipe without active ports, |
10688 | * we may need some idea for the dotclock anyway. | |
10689 | * Calculate one based on the FDI configuration. | |
79e53945 | 10690 | */ |
2d112de7 | 10691 | pipe_config->base.adjusted_mode.crtc_clock = |
21a727b3 | 10692 | intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
18442d08 | 10693 | &pipe_config->fdi_m_n); |
79e53945 JB |
10694 | } |
10695 | ||
10696 | /** Returns the currently programmed mode of the given pipe. */ | |
10697 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
10698 | struct drm_crtc *crtc) | |
10699 | { | |
548f245b | 10700 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 10701 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 10702 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 10703 | struct drm_display_mode *mode; |
3f36b937 | 10704 | struct intel_crtc_state *pipe_config; |
fe2b8f9d PZ |
10705 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
10706 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
10707 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
10708 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 10709 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
10710 | |
10711 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
10712 | if (!mode) | |
10713 | return NULL; | |
10714 | ||
3f36b937 TU |
10715 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
10716 | if (!pipe_config) { | |
10717 | kfree(mode); | |
10718 | return NULL; | |
10719 | } | |
10720 | ||
f1f644dc JB |
10721 | /* |
10722 | * Construct a pipe_config sufficient for getting the clock info | |
10723 | * back out of crtc_clock_get. | |
10724 | * | |
10725 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
10726 | * to use a real value here instead. | |
10727 | */ | |
3f36b937 TU |
10728 | pipe_config->cpu_transcoder = (enum transcoder) pipe; |
10729 | pipe_config->pixel_multiplier = 1; | |
10730 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe)); | |
10731 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
10732 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
10733 | i9xx_crtc_clock_get(intel_crtc, pipe_config); | |
10734 | ||
10735 | mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier; | |
79e53945 JB |
10736 | mode->hdisplay = (htot & 0xffff) + 1; |
10737 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
10738 | mode->hsync_start = (hsync & 0xffff) + 1; | |
10739 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
10740 | mode->vdisplay = (vtot & 0xffff) + 1; | |
10741 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
10742 | mode->vsync_start = (vsync & 0xffff) + 1; | |
10743 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
10744 | ||
10745 | drm_mode_set_name(mode); | |
79e53945 | 10746 | |
3f36b937 TU |
10747 | kfree(pipe_config); |
10748 | ||
79e53945 JB |
10749 | return mode; |
10750 | } | |
10751 | ||
f047e395 CW |
10752 | void intel_mark_busy(struct drm_device *dev) |
10753 | { | |
c67a470b PZ |
10754 | struct drm_i915_private *dev_priv = dev->dev_private; |
10755 | ||
f62a0076 CW |
10756 | if (dev_priv->mm.busy) |
10757 | return; | |
10758 | ||
43694d69 | 10759 | intel_runtime_pm_get(dev_priv); |
c67a470b | 10760 | i915_update_gfx_val(dev_priv); |
43cf3bf0 CW |
10761 | if (INTEL_INFO(dev)->gen >= 6) |
10762 | gen6_rps_busy(dev_priv); | |
f62a0076 | 10763 | dev_priv->mm.busy = true; |
f047e395 CW |
10764 | } |
10765 | ||
10766 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 10767 | { |
c67a470b | 10768 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 10769 | |
f62a0076 CW |
10770 | if (!dev_priv->mm.busy) |
10771 | return; | |
10772 | ||
10773 | dev_priv->mm.busy = false; | |
10774 | ||
3d13ef2e | 10775 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 10776 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 | 10777 | |
43694d69 | 10778 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
10779 | } |
10780 | ||
79e53945 JB |
10781 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
10782 | { | |
10783 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
10784 | struct drm_device *dev = crtc->dev; |
10785 | struct intel_unpin_work *work; | |
67e77c5a | 10786 | |
5e2d7afc | 10787 | spin_lock_irq(&dev->event_lock); |
67e77c5a DV |
10788 | work = intel_crtc->unpin_work; |
10789 | intel_crtc->unpin_work = NULL; | |
5e2d7afc | 10790 | spin_unlock_irq(&dev->event_lock); |
67e77c5a DV |
10791 | |
10792 | if (work) { | |
10793 | cancel_work_sync(&work->work); | |
10794 | kfree(work); | |
10795 | } | |
79e53945 JB |
10796 | |
10797 | drm_crtc_cleanup(crtc); | |
67e77c5a | 10798 | |
79e53945 JB |
10799 | kfree(intel_crtc); |
10800 | } | |
10801 | ||
6b95a207 KH |
10802 | static void intel_unpin_work_fn(struct work_struct *__work) |
10803 | { | |
10804 | struct intel_unpin_work *work = | |
10805 | container_of(__work, struct intel_unpin_work, work); | |
a9ff8714 VS |
10806 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); |
10807 | struct drm_device *dev = crtc->base.dev; | |
10808 | struct drm_plane *primary = crtc->base.primary; | |
6b95a207 | 10809 | |
b4a98e57 | 10810 | mutex_lock(&dev->struct_mutex); |
3465c580 | 10811 | intel_unpin_fb_obj(work->old_fb, primary->state->rotation); |
05394f39 | 10812 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
d9e86c0e | 10813 | |
f06cc1b9 | 10814 | if (work->flip_queued_req) |
146d84f0 | 10815 | i915_gem_request_assign(&work->flip_queued_req, NULL); |
b4a98e57 CW |
10816 | mutex_unlock(&dev->struct_mutex); |
10817 | ||
a9ff8714 | 10818 | intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit); |
1eb52238 | 10819 | intel_fbc_post_update(crtc); |
89ed88ba | 10820 | drm_framebuffer_unreference(work->old_fb); |
f99d7069 | 10821 | |
a9ff8714 VS |
10822 | BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); |
10823 | atomic_dec(&crtc->unpin_work_count); | |
b4a98e57 | 10824 | |
6b95a207 KH |
10825 | kfree(work); |
10826 | } | |
10827 | ||
1afe3e9d | 10828 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 10829 | struct drm_crtc *crtc) |
6b95a207 | 10830 | { |
6b95a207 KH |
10831 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10832 | struct intel_unpin_work *work; | |
6b95a207 KH |
10833 | unsigned long flags; |
10834 | ||
10835 | /* Ignore early vblank irqs */ | |
10836 | if (intel_crtc == NULL) | |
10837 | return; | |
10838 | ||
f326038a DV |
10839 | /* |
10840 | * This is called both by irq handlers and the reset code (to complete | |
10841 | * lost pageflips) so needs the full irqsave spinlocks. | |
10842 | */ | |
6b95a207 KH |
10843 | spin_lock_irqsave(&dev->event_lock, flags); |
10844 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
10845 | |
10846 | /* Ensure we don't miss a work->pending update ... */ | |
10847 | smp_rmb(); | |
10848 | ||
10849 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
10850 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10851 | return; | |
10852 | } | |
10853 | ||
d6bbafa1 | 10854 | page_flip_completed(intel_crtc); |
0af7e4df | 10855 | |
6b95a207 | 10856 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6b95a207 KH |
10857 | } |
10858 | ||
1afe3e9d JB |
10859 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
10860 | { | |
fbee40df | 10861 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10862 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
10863 | ||
49b14a5c | 10864 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10865 | } |
10866 | ||
10867 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
10868 | { | |
fbee40df | 10869 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10870 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
10871 | ||
49b14a5c | 10872 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10873 | } |
10874 | ||
75f7f3ec VS |
10875 | /* Is 'a' after or equal to 'b'? */ |
10876 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
10877 | { | |
10878 | return !((a - b) & 0x80000000); | |
10879 | } | |
10880 | ||
10881 | static bool page_flip_finished(struct intel_crtc *crtc) | |
10882 | { | |
10883 | struct drm_device *dev = crtc->base.dev; | |
10884 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10885 | ||
bdfa7542 VS |
10886 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
10887 | crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
10888 | return true; | |
10889 | ||
75f7f3ec VS |
10890 | /* |
10891 | * The relevant registers doen't exist on pre-ctg. | |
10892 | * As the flip done interrupt doesn't trigger for mmio | |
10893 | * flips on gmch platforms, a flip count check isn't | |
10894 | * really needed there. But since ctg has the registers, | |
10895 | * include it in the check anyway. | |
10896 | */ | |
10897 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
10898 | return true; | |
10899 | ||
e8861675 ML |
10900 | /* |
10901 | * BDW signals flip done immediately if the plane | |
10902 | * is disabled, even if the plane enable is already | |
10903 | * armed to occur at the next vblank :( | |
10904 | */ | |
10905 | ||
75f7f3ec VS |
10906 | /* |
10907 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
10908 | * used the same base address. In that case the mmio flip might | |
10909 | * have completed, but the CS hasn't even executed the flip yet. | |
10910 | * | |
10911 | * A flip count check isn't enough as the CS might have updated | |
10912 | * the base address just after start of vblank, but before we | |
10913 | * managed to process the interrupt. This means we'd complete the | |
10914 | * CS flip too soon. | |
10915 | * | |
10916 | * Combining both checks should get us a good enough result. It may | |
10917 | * still happen that the CS flip has been executed, but has not | |
10918 | * yet actually completed. But in case the base address is the same | |
10919 | * anyway, we don't really care. | |
10920 | */ | |
10921 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
10922 | crtc->unpin_work->gtt_offset && | |
fd8f507c | 10923 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), |
75f7f3ec VS |
10924 | crtc->unpin_work->flip_count); |
10925 | } | |
10926 | ||
6b95a207 KH |
10927 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
10928 | { | |
fbee40df | 10929 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
10930 | struct intel_crtc *intel_crtc = |
10931 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
10932 | unsigned long flags; | |
10933 | ||
f326038a DV |
10934 | |
10935 | /* | |
10936 | * This is called both by irq handlers and the reset code (to complete | |
10937 | * lost pageflips) so needs the full irqsave spinlocks. | |
10938 | * | |
10939 | * NB: An MMIO update of the plane base pointer will also | |
e7d841ca CW |
10940 | * generate a page-flip completion irq, i.e. every modeset |
10941 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
10942 | */ | |
6b95a207 | 10943 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 10944 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 10945 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
10946 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10947 | } | |
10948 | ||
6042639c | 10949 | static inline void intel_mark_page_flip_active(struct intel_unpin_work *work) |
e7d841ca CW |
10950 | { |
10951 | /* Ensure that the work item is consistent when activating it ... */ | |
10952 | smp_wmb(); | |
6042639c | 10953 | atomic_set(&work->pending, INTEL_FLIP_PENDING); |
e7d841ca CW |
10954 | /* and that it is marked active as soon as the irq could fire. */ |
10955 | smp_wmb(); | |
10956 | } | |
10957 | ||
8c9f3aaf JB |
10958 | static int intel_gen2_queue_flip(struct drm_device *dev, |
10959 | struct drm_crtc *crtc, | |
10960 | struct drm_framebuffer *fb, | |
ed8d1975 | 10961 | struct drm_i915_gem_object *obj, |
6258fbe2 | 10962 | struct drm_i915_gem_request *req, |
ed8d1975 | 10963 | uint32_t flags) |
8c9f3aaf | 10964 | { |
4a570db5 | 10965 | struct intel_engine_cs *engine = req->engine; |
8c9f3aaf | 10966 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
10967 | u32 flip_mask; |
10968 | int ret; | |
10969 | ||
5fb9de1a | 10970 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 10971 | if (ret) |
4fa62c89 | 10972 | return ret; |
8c9f3aaf JB |
10973 | |
10974 | /* Can't queue multiple flips, so wait for the previous | |
10975 | * one to finish before executing the next. | |
10976 | */ | |
10977 | if (intel_crtc->plane) | |
10978 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
10979 | else | |
10980 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
e2f80391 TU |
10981 | intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask); |
10982 | intel_ring_emit(engine, MI_NOOP); | |
10983 | intel_ring_emit(engine, MI_DISPLAY_FLIP | | |
6d90c952 | 10984 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
e2f80391 TU |
10985 | intel_ring_emit(engine, fb->pitches[0]); |
10986 | intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset); | |
10987 | intel_ring_emit(engine, 0); /* aux display base address, unused */ | |
e7d841ca | 10988 | |
6042639c | 10989 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 10990 | return 0; |
8c9f3aaf JB |
10991 | } |
10992 | ||
10993 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
10994 | struct drm_crtc *crtc, | |
10995 | struct drm_framebuffer *fb, | |
ed8d1975 | 10996 | struct drm_i915_gem_object *obj, |
6258fbe2 | 10997 | struct drm_i915_gem_request *req, |
ed8d1975 | 10998 | uint32_t flags) |
8c9f3aaf | 10999 | { |
4a570db5 | 11000 | struct intel_engine_cs *engine = req->engine; |
8c9f3aaf | 11001 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
11002 | u32 flip_mask; |
11003 | int ret; | |
11004 | ||
5fb9de1a | 11005 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 11006 | if (ret) |
4fa62c89 | 11007 | return ret; |
8c9f3aaf JB |
11008 | |
11009 | if (intel_crtc->plane) | |
11010 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11011 | else | |
11012 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
e2f80391 TU |
11013 | intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask); |
11014 | intel_ring_emit(engine, MI_NOOP); | |
11015 | intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | | |
6d90c952 | 11016 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
e2f80391 TU |
11017 | intel_ring_emit(engine, fb->pitches[0]); |
11018 | intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset); | |
11019 | intel_ring_emit(engine, MI_NOOP); | |
6d90c952 | 11020 | |
6042639c | 11021 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11022 | return 0; |
8c9f3aaf JB |
11023 | } |
11024 | ||
11025 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
11026 | struct drm_crtc *crtc, | |
11027 | struct drm_framebuffer *fb, | |
ed8d1975 | 11028 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11029 | struct drm_i915_gem_request *req, |
ed8d1975 | 11030 | uint32_t flags) |
8c9f3aaf | 11031 | { |
4a570db5 | 11032 | struct intel_engine_cs *engine = req->engine; |
8c9f3aaf JB |
11033 | struct drm_i915_private *dev_priv = dev->dev_private; |
11034 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11035 | uint32_t pf, pipesrc; | |
11036 | int ret; | |
11037 | ||
5fb9de1a | 11038 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 11039 | if (ret) |
4fa62c89 | 11040 | return ret; |
8c9f3aaf JB |
11041 | |
11042 | /* i965+ uses the linear or tiled offsets from the | |
11043 | * Display Registers (which do not change across a page-flip) | |
11044 | * so we need only reprogram the base address. | |
11045 | */ | |
e2f80391 | 11046 | intel_ring_emit(engine, MI_DISPLAY_FLIP | |
6d90c952 | 11047 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
e2f80391 TU |
11048 | intel_ring_emit(engine, fb->pitches[0]); |
11049 | intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset | | |
c2c75131 | 11050 | obj->tiling_mode); |
8c9f3aaf JB |
11051 | |
11052 | /* XXX Enabling the panel-fitter across page-flip is so far | |
11053 | * untested on non-native modes, so ignore it for now. | |
11054 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
11055 | */ | |
11056 | pf = 0; | |
11057 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
e2f80391 | 11058 | intel_ring_emit(engine, pf | pipesrc); |
e7d841ca | 11059 | |
6042639c | 11060 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11061 | return 0; |
8c9f3aaf JB |
11062 | } |
11063 | ||
11064 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
11065 | struct drm_crtc *crtc, | |
11066 | struct drm_framebuffer *fb, | |
ed8d1975 | 11067 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11068 | struct drm_i915_gem_request *req, |
ed8d1975 | 11069 | uint32_t flags) |
8c9f3aaf | 11070 | { |
4a570db5 | 11071 | struct intel_engine_cs *engine = req->engine; |
8c9f3aaf JB |
11072 | struct drm_i915_private *dev_priv = dev->dev_private; |
11073 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11074 | uint32_t pf, pipesrc; | |
11075 | int ret; | |
11076 | ||
5fb9de1a | 11077 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 11078 | if (ret) |
4fa62c89 | 11079 | return ret; |
8c9f3aaf | 11080 | |
e2f80391 | 11081 | intel_ring_emit(engine, MI_DISPLAY_FLIP | |
6d90c952 | 11082 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
e2f80391 TU |
11083 | intel_ring_emit(engine, fb->pitches[0] | obj->tiling_mode); |
11084 | intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset); | |
8c9f3aaf | 11085 | |
dc257cf1 DV |
11086 | /* Contrary to the suggestions in the documentation, |
11087 | * "Enable Panel Fitter" does not seem to be required when page | |
11088 | * flipping with a non-native mode, and worse causes a normal | |
11089 | * modeset to fail. | |
11090 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
11091 | */ | |
11092 | pf = 0; | |
8c9f3aaf | 11093 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
e2f80391 | 11094 | intel_ring_emit(engine, pf | pipesrc); |
e7d841ca | 11095 | |
6042639c | 11096 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11097 | return 0; |
8c9f3aaf JB |
11098 | } |
11099 | ||
7c9017e5 JB |
11100 | static int intel_gen7_queue_flip(struct drm_device *dev, |
11101 | struct drm_crtc *crtc, | |
11102 | struct drm_framebuffer *fb, | |
ed8d1975 | 11103 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11104 | struct drm_i915_gem_request *req, |
ed8d1975 | 11105 | uint32_t flags) |
7c9017e5 | 11106 | { |
4a570db5 | 11107 | struct intel_engine_cs *engine = req->engine; |
7c9017e5 | 11108 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 11109 | uint32_t plane_bit = 0; |
ffe74d75 CW |
11110 | int len, ret; |
11111 | ||
eba905b2 | 11112 | switch (intel_crtc->plane) { |
cb05d8de DV |
11113 | case PLANE_A: |
11114 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
11115 | break; | |
11116 | case PLANE_B: | |
11117 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
11118 | break; | |
11119 | case PLANE_C: | |
11120 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
11121 | break; | |
11122 | default: | |
11123 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 11124 | return -ENODEV; |
cb05d8de DV |
11125 | } |
11126 | ||
ffe74d75 | 11127 | len = 4; |
e2f80391 | 11128 | if (engine->id == RCS) { |
ffe74d75 | 11129 | len += 6; |
f476828a DL |
11130 | /* |
11131 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
11132 | * 48bits addresses, and we need a NOOP for the batch size to | |
11133 | * stay even. | |
11134 | */ | |
11135 | if (IS_GEN8(dev)) | |
11136 | len += 2; | |
11137 | } | |
ffe74d75 | 11138 | |
f66fab8e VS |
11139 | /* |
11140 | * BSpec MI_DISPLAY_FLIP for IVB: | |
11141 | * "The full packet must be contained within the same cache line." | |
11142 | * | |
11143 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
11144 | * cacheline, if we ever start emitting more commands before | |
11145 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
11146 | * then do the cacheline alignment, and finally emit the | |
11147 | * MI_DISPLAY_FLIP. | |
11148 | */ | |
bba09b12 | 11149 | ret = intel_ring_cacheline_align(req); |
f66fab8e | 11150 | if (ret) |
4fa62c89 | 11151 | return ret; |
f66fab8e | 11152 | |
5fb9de1a | 11153 | ret = intel_ring_begin(req, len); |
7c9017e5 | 11154 | if (ret) |
4fa62c89 | 11155 | return ret; |
7c9017e5 | 11156 | |
ffe74d75 CW |
11157 | /* Unmask the flip-done completion message. Note that the bspec says that |
11158 | * we should do this for both the BCS and RCS, and that we must not unmask | |
11159 | * more than one flip event at any time (or ensure that one flip message | |
11160 | * can be sent by waiting for flip-done prior to queueing new flips). | |
11161 | * Experimentation says that BCS works despite DERRMR masking all | |
11162 | * flip-done completion events and that unmasking all planes at once | |
11163 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
11164 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
11165 | */ | |
e2f80391 TU |
11166 | if (engine->id == RCS) { |
11167 | intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1)); | |
11168 | intel_ring_emit_reg(engine, DERRMR); | |
11169 | intel_ring_emit(engine, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
11170 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
11171 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a | 11172 | if (IS_GEN8(dev)) |
e2f80391 | 11173 | intel_ring_emit(engine, MI_STORE_REGISTER_MEM_GEN8 | |
f476828a DL |
11174 | MI_SRM_LRM_GLOBAL_GTT); |
11175 | else | |
e2f80391 | 11176 | intel_ring_emit(engine, MI_STORE_REGISTER_MEM | |
f476828a | 11177 | MI_SRM_LRM_GLOBAL_GTT); |
e2f80391 TU |
11178 | intel_ring_emit_reg(engine, DERRMR); |
11179 | intel_ring_emit(engine, engine->scratch.gtt_offset + 256); | |
f476828a | 11180 | if (IS_GEN8(dev)) { |
e2f80391 TU |
11181 | intel_ring_emit(engine, 0); |
11182 | intel_ring_emit(engine, MI_NOOP); | |
f476828a | 11183 | } |
ffe74d75 CW |
11184 | } |
11185 | ||
e2f80391 TU |
11186 | intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | plane_bit); |
11187 | intel_ring_emit(engine, (fb->pitches[0] | obj->tiling_mode)); | |
11188 | intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset); | |
11189 | intel_ring_emit(engine, (MI_NOOP)); | |
e7d841ca | 11190 | |
6042639c | 11191 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11192 | return 0; |
7c9017e5 JB |
11193 | } |
11194 | ||
0bc40be8 | 11195 | static bool use_mmio_flip(struct intel_engine_cs *engine, |
84c33a64 SG |
11196 | struct drm_i915_gem_object *obj) |
11197 | { | |
11198 | /* | |
11199 | * This is not being used for older platforms, because | |
11200 | * non-availability of flip done interrupt forces us to use | |
11201 | * CS flips. Older platforms derive flip done using some clever | |
11202 | * tricks involving the flip_pending status bits and vblank irqs. | |
11203 | * So using MMIO flips there would disrupt this mechanism. | |
11204 | */ | |
11205 | ||
0bc40be8 | 11206 | if (engine == NULL) |
8e09bf83 CW |
11207 | return true; |
11208 | ||
0bc40be8 | 11209 | if (INTEL_INFO(engine->dev)->gen < 5) |
84c33a64 SG |
11210 | return false; |
11211 | ||
11212 | if (i915.use_mmio_flip < 0) | |
11213 | return false; | |
11214 | else if (i915.use_mmio_flip > 0) | |
11215 | return true; | |
14bf993e OM |
11216 | else if (i915.enable_execlists) |
11217 | return true; | |
fd8e058a AG |
11218 | else if (obj->base.dma_buf && |
11219 | !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv, | |
11220 | false)) | |
11221 | return true; | |
84c33a64 | 11222 | else |
666796da | 11223 | return engine != i915_gem_request_get_engine(obj->last_write_req); |
84c33a64 SG |
11224 | } |
11225 | ||
6042639c | 11226 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, |
86efe24a | 11227 | unsigned int rotation, |
6042639c | 11228 | struct intel_unpin_work *work) |
ff944564 DL |
11229 | { |
11230 | struct drm_device *dev = intel_crtc->base.dev; | |
11231 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11232 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; | |
ff944564 | 11233 | const enum pipe pipe = intel_crtc->pipe; |
86efe24a | 11234 | u32 ctl, stride, tile_height; |
ff944564 DL |
11235 | |
11236 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
11237 | ctl &= ~PLANE_CTL_TILED_MASK; | |
2ebef630 TU |
11238 | switch (fb->modifier[0]) { |
11239 | case DRM_FORMAT_MOD_NONE: | |
11240 | break; | |
11241 | case I915_FORMAT_MOD_X_TILED: | |
ff944564 | 11242 | ctl |= PLANE_CTL_TILED_X; |
2ebef630 TU |
11243 | break; |
11244 | case I915_FORMAT_MOD_Y_TILED: | |
11245 | ctl |= PLANE_CTL_TILED_Y; | |
11246 | break; | |
11247 | case I915_FORMAT_MOD_Yf_TILED: | |
11248 | ctl |= PLANE_CTL_TILED_YF; | |
11249 | break; | |
11250 | default: | |
11251 | MISSING_CASE(fb->modifier[0]); | |
11252 | } | |
ff944564 DL |
11253 | |
11254 | /* | |
11255 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
11256 | * linear buffers or in number of tiles for tiled buffers. | |
11257 | */ | |
86efe24a TU |
11258 | if (intel_rotation_90_or_270(rotation)) { |
11259 | /* stride = Surface height in tiles */ | |
832be82f | 11260 | tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0); |
86efe24a TU |
11261 | stride = DIV_ROUND_UP(fb->height, tile_height); |
11262 | } else { | |
11263 | stride = fb->pitches[0] / | |
7b49f948 VS |
11264 | intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
11265 | fb->pixel_format); | |
86efe24a | 11266 | } |
ff944564 DL |
11267 | |
11268 | /* | |
11269 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
11270 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
11271 | */ | |
11272 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
11273 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
11274 | ||
6042639c | 11275 | I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); |
ff944564 DL |
11276 | POSTING_READ(PLANE_SURF(pipe, 0)); |
11277 | } | |
11278 | ||
6042639c CW |
11279 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, |
11280 | struct intel_unpin_work *work) | |
84c33a64 SG |
11281 | { |
11282 | struct drm_device *dev = intel_crtc->base.dev; | |
11283 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11284 | struct intel_framebuffer *intel_fb = | |
11285 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
11286 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
f0f59a00 | 11287 | i915_reg_t reg = DSPCNTR(intel_crtc->plane); |
84c33a64 | 11288 | u32 dspcntr; |
84c33a64 | 11289 | |
84c33a64 SG |
11290 | dspcntr = I915_READ(reg); |
11291 | ||
c5d97472 DL |
11292 | if (obj->tiling_mode != I915_TILING_NONE) |
11293 | dspcntr |= DISPPLANE_TILED; | |
11294 | else | |
11295 | dspcntr &= ~DISPPLANE_TILED; | |
11296 | ||
84c33a64 SG |
11297 | I915_WRITE(reg, dspcntr); |
11298 | ||
6042639c | 11299 | I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); |
84c33a64 | 11300 | POSTING_READ(DSPSURF(intel_crtc->plane)); |
ff944564 DL |
11301 | } |
11302 | ||
11303 | /* | |
11304 | * XXX: This is the temporary way to update the plane registers until we get | |
11305 | * around to using the usual plane update functions for MMIO flips | |
11306 | */ | |
6042639c | 11307 | static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip) |
ff944564 | 11308 | { |
6042639c CW |
11309 | struct intel_crtc *crtc = mmio_flip->crtc; |
11310 | struct intel_unpin_work *work; | |
11311 | ||
11312 | spin_lock_irq(&crtc->base.dev->event_lock); | |
11313 | work = crtc->unpin_work; | |
11314 | spin_unlock_irq(&crtc->base.dev->event_lock); | |
11315 | if (work == NULL) | |
11316 | return; | |
ff944564 | 11317 | |
6042639c | 11318 | intel_mark_page_flip_active(work); |
ff944564 | 11319 | |
6042639c | 11320 | intel_pipe_update_start(crtc); |
ff944564 | 11321 | |
6042639c | 11322 | if (INTEL_INFO(mmio_flip->i915)->gen >= 9) |
86efe24a | 11323 | skl_do_mmio_flip(crtc, mmio_flip->rotation, work); |
ff944564 DL |
11324 | else |
11325 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
6042639c | 11326 | ilk_do_mmio_flip(crtc, work); |
ff944564 | 11327 | |
6042639c | 11328 | intel_pipe_update_end(crtc); |
84c33a64 SG |
11329 | } |
11330 | ||
9362c7c5 | 11331 | static void intel_mmio_flip_work_func(struct work_struct *work) |
84c33a64 | 11332 | { |
b2cfe0ab CW |
11333 | struct intel_mmio_flip *mmio_flip = |
11334 | container_of(work, struct intel_mmio_flip, work); | |
fd8e058a AG |
11335 | struct intel_framebuffer *intel_fb = |
11336 | to_intel_framebuffer(mmio_flip->crtc->base.primary->fb); | |
11337 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
84c33a64 | 11338 | |
6042639c | 11339 | if (mmio_flip->req) { |
eed29a5b | 11340 | WARN_ON(__i915_wait_request(mmio_flip->req, |
b2cfe0ab | 11341 | mmio_flip->crtc->reset_counter, |
bcafc4e3 CW |
11342 | false, NULL, |
11343 | &mmio_flip->i915->rps.mmioflips)); | |
6042639c CW |
11344 | i915_gem_request_unreference__unlocked(mmio_flip->req); |
11345 | } | |
84c33a64 | 11346 | |
fd8e058a AG |
11347 | /* For framebuffer backed by dmabuf, wait for fence */ |
11348 | if (obj->base.dma_buf) | |
11349 | WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv, | |
11350 | false, false, | |
11351 | MAX_SCHEDULE_TIMEOUT) < 0); | |
11352 | ||
6042639c | 11353 | intel_do_mmio_flip(mmio_flip); |
b2cfe0ab | 11354 | kfree(mmio_flip); |
84c33a64 SG |
11355 | } |
11356 | ||
11357 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
11358 | struct drm_crtc *crtc, | |
86efe24a | 11359 | struct drm_i915_gem_object *obj) |
84c33a64 | 11360 | { |
b2cfe0ab CW |
11361 | struct intel_mmio_flip *mmio_flip; |
11362 | ||
11363 | mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL); | |
11364 | if (mmio_flip == NULL) | |
11365 | return -ENOMEM; | |
84c33a64 | 11366 | |
bcafc4e3 | 11367 | mmio_flip->i915 = to_i915(dev); |
eed29a5b | 11368 | mmio_flip->req = i915_gem_request_reference(obj->last_write_req); |
b2cfe0ab | 11369 | mmio_flip->crtc = to_intel_crtc(crtc); |
86efe24a | 11370 | mmio_flip->rotation = crtc->primary->state->rotation; |
536f5b5e | 11371 | |
b2cfe0ab CW |
11372 | INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func); |
11373 | schedule_work(&mmio_flip->work); | |
84c33a64 | 11374 | |
84c33a64 SG |
11375 | return 0; |
11376 | } | |
11377 | ||
8c9f3aaf JB |
11378 | static int intel_default_queue_flip(struct drm_device *dev, |
11379 | struct drm_crtc *crtc, | |
11380 | struct drm_framebuffer *fb, | |
ed8d1975 | 11381 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11382 | struct drm_i915_gem_request *req, |
ed8d1975 | 11383 | uint32_t flags) |
8c9f3aaf JB |
11384 | { |
11385 | return -ENODEV; | |
11386 | } | |
11387 | ||
d6bbafa1 CW |
11388 | static bool __intel_pageflip_stall_check(struct drm_device *dev, |
11389 | struct drm_crtc *crtc) | |
11390 | { | |
11391 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11392 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11393 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
11394 | u32 addr; | |
11395 | ||
11396 | if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) | |
11397 | return true; | |
11398 | ||
908565c2 CW |
11399 | if (atomic_read(&work->pending) < INTEL_FLIP_PENDING) |
11400 | return false; | |
11401 | ||
d6bbafa1 CW |
11402 | if (!work->enable_stall_check) |
11403 | return false; | |
11404 | ||
11405 | if (work->flip_ready_vblank == 0) { | |
3a8a946e DV |
11406 | if (work->flip_queued_req && |
11407 | !i915_gem_request_completed(work->flip_queued_req, true)) | |
d6bbafa1 CW |
11408 | return false; |
11409 | ||
1e3feefd | 11410 | work->flip_ready_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 CW |
11411 | } |
11412 | ||
1e3feefd | 11413 | if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) |
d6bbafa1 CW |
11414 | return false; |
11415 | ||
11416 | /* Potential stall - if we see that the flip has happened, | |
11417 | * assume a missed interrupt. */ | |
11418 | if (INTEL_INFO(dev)->gen >= 4) | |
11419 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
11420 | else | |
11421 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
11422 | ||
11423 | /* There is a potential issue here with a false positive after a flip | |
11424 | * to the same address. We could address this by checking for a | |
11425 | * non-incrementing frame counter. | |
11426 | */ | |
11427 | return addr == work->gtt_offset; | |
11428 | } | |
11429 | ||
11430 | void intel_check_page_flip(struct drm_device *dev, int pipe) | |
11431 | { | |
11432 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11433 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
11434 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6ad790c0 | 11435 | struct intel_unpin_work *work; |
f326038a | 11436 | |
6c51d46f | 11437 | WARN_ON(!in_interrupt()); |
d6bbafa1 CW |
11438 | |
11439 | if (crtc == NULL) | |
11440 | return; | |
11441 | ||
f326038a | 11442 | spin_lock(&dev->event_lock); |
6ad790c0 CW |
11443 | work = intel_crtc->unpin_work; |
11444 | if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) { | |
d6bbafa1 | 11445 | WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", |
6ad790c0 | 11446 | work->flip_queued_vblank, drm_vblank_count(dev, pipe)); |
d6bbafa1 | 11447 | page_flip_completed(intel_crtc); |
6ad790c0 | 11448 | work = NULL; |
d6bbafa1 | 11449 | } |
6ad790c0 CW |
11450 | if (work != NULL && |
11451 | drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1) | |
11452 | intel_queue_rps_boost_for_request(dev, work->flip_queued_req); | |
f326038a | 11453 | spin_unlock(&dev->event_lock); |
d6bbafa1 CW |
11454 | } |
11455 | ||
6b95a207 KH |
11456 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
11457 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
11458 | struct drm_pending_vblank_event *event, |
11459 | uint32_t page_flip_flags) | |
6b95a207 KH |
11460 | { |
11461 | struct drm_device *dev = crtc->dev; | |
11462 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 11463 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 11464 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 | 11465 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
455a6808 | 11466 | struct drm_plane *primary = crtc->primary; |
a071fa00 | 11467 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 11468 | struct intel_unpin_work *work; |
e2f80391 | 11469 | struct intel_engine_cs *engine; |
cf5d8a46 | 11470 | bool mmio_flip; |
91af127f | 11471 | struct drm_i915_gem_request *request = NULL; |
52e68630 | 11472 | int ret; |
6b95a207 | 11473 | |
2ff8fde1 MR |
11474 | /* |
11475 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
11476 | * check to be safe. In the future we may enable pageflipping from | |
11477 | * a disabled primary plane. | |
11478 | */ | |
11479 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
11480 | return -EBUSY; | |
11481 | ||
e6a595d2 | 11482 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 11483 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
11484 | return -EINVAL; |
11485 | ||
11486 | /* | |
11487 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
11488 | * Note that pitch changes could also affect these register. | |
11489 | */ | |
11490 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
11491 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
11492 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
11493 | return -EINVAL; |
11494 | ||
f900db47 CW |
11495 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
11496 | goto out_hang; | |
11497 | ||
b14c5679 | 11498 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
11499 | if (work == NULL) |
11500 | return -ENOMEM; | |
11501 | ||
6b95a207 | 11502 | work->event = event; |
b4a98e57 | 11503 | work->crtc = crtc; |
ab8d6675 | 11504 | work->old_fb = old_fb; |
6b95a207 KH |
11505 | INIT_WORK(&work->work, intel_unpin_work_fn); |
11506 | ||
87b6b101 | 11507 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
11508 | if (ret) |
11509 | goto free_work; | |
11510 | ||
6b95a207 | 11511 | /* We borrow the event spin lock for protecting unpin_work */ |
5e2d7afc | 11512 | spin_lock_irq(&dev->event_lock); |
6b95a207 | 11513 | if (intel_crtc->unpin_work) { |
d6bbafa1 CW |
11514 | /* Before declaring the flip queue wedged, check if |
11515 | * the hardware completed the operation behind our backs. | |
11516 | */ | |
11517 | if (__intel_pageflip_stall_check(dev, crtc)) { | |
11518 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
11519 | page_flip_completed(intel_crtc); | |
11520 | } else { | |
11521 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
5e2d7afc | 11522 | spin_unlock_irq(&dev->event_lock); |
468f0b44 | 11523 | |
d6bbafa1 CW |
11524 | drm_crtc_vblank_put(crtc); |
11525 | kfree(work); | |
11526 | return -EBUSY; | |
11527 | } | |
6b95a207 KH |
11528 | } |
11529 | intel_crtc->unpin_work = work; | |
5e2d7afc | 11530 | spin_unlock_irq(&dev->event_lock); |
6b95a207 | 11531 | |
b4a98e57 CW |
11532 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
11533 | flush_workqueue(dev_priv->wq); | |
11534 | ||
75dfca80 | 11535 | /* Reference the objects for the scheduled work. */ |
ab8d6675 | 11536 | drm_framebuffer_reference(work->old_fb); |
05394f39 | 11537 | drm_gem_object_reference(&obj->base); |
6b95a207 | 11538 | |
f4510a27 | 11539 | crtc->primary->fb = fb; |
afd65eb4 | 11540 | update_state_fb(crtc->primary); |
e8216e50 | 11541 | intel_fbc_pre_update(intel_crtc); |
1ed1f968 | 11542 | |
e1f99ce6 | 11543 | work->pending_flip_obj = obj; |
e1f99ce6 | 11544 | |
89ed88ba CW |
11545 | ret = i915_mutex_lock_interruptible(dev); |
11546 | if (ret) | |
11547 | goto cleanup; | |
11548 | ||
b4a98e57 | 11549 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 11550 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 11551 | |
75f7f3ec | 11552 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
fd8f507c | 11553 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; |
75f7f3ec | 11554 | |
666a4537 | 11555 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
4a570db5 | 11556 | engine = &dev_priv->engine[BCS]; |
ab8d6675 | 11557 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) |
8e09bf83 | 11558 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
e2f80391 | 11559 | engine = NULL; |
48bf5b2d | 11560 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
4a570db5 | 11561 | engine = &dev_priv->engine[BCS]; |
4fa62c89 | 11562 | } else if (INTEL_INFO(dev)->gen >= 7) { |
666796da | 11563 | engine = i915_gem_request_get_engine(obj->last_write_req); |
e2f80391 | 11564 | if (engine == NULL || engine->id != RCS) |
4a570db5 | 11565 | engine = &dev_priv->engine[BCS]; |
4fa62c89 | 11566 | } else { |
4a570db5 | 11567 | engine = &dev_priv->engine[RCS]; |
4fa62c89 VS |
11568 | } |
11569 | ||
e2f80391 | 11570 | mmio_flip = use_mmio_flip(engine, obj); |
cf5d8a46 CW |
11571 | |
11572 | /* When using CS flips, we want to emit semaphores between rings. | |
11573 | * However, when using mmio flips we will create a task to do the | |
11574 | * synchronisation, so all we want here is to pin the framebuffer | |
11575 | * into the display plane and skip any waits. | |
11576 | */ | |
7580d774 | 11577 | if (!mmio_flip) { |
e2f80391 | 11578 | ret = i915_gem_object_sync(obj, engine, &request); |
7580d774 ML |
11579 | if (ret) |
11580 | goto cleanup_pending; | |
11581 | } | |
11582 | ||
3465c580 | 11583 | ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation); |
8c9f3aaf JB |
11584 | if (ret) |
11585 | goto cleanup_pending; | |
6b95a207 | 11586 | |
dedf278c TU |
11587 | work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), |
11588 | obj, 0); | |
11589 | work->gtt_offset += intel_crtc->dspaddr_offset; | |
4fa62c89 | 11590 | |
cf5d8a46 | 11591 | if (mmio_flip) { |
86efe24a | 11592 | ret = intel_queue_mmio_flip(dev, crtc, obj); |
d6bbafa1 CW |
11593 | if (ret) |
11594 | goto cleanup_unpin; | |
11595 | ||
f06cc1b9 JH |
11596 | i915_gem_request_assign(&work->flip_queued_req, |
11597 | obj->last_write_req); | |
d6bbafa1 | 11598 | } else { |
6258fbe2 | 11599 | if (!request) { |
e2f80391 | 11600 | request = i915_gem_request_alloc(engine, NULL); |
26827088 DG |
11601 | if (IS_ERR(request)) { |
11602 | ret = PTR_ERR(request); | |
6258fbe2 | 11603 | goto cleanup_unpin; |
26827088 | 11604 | } |
6258fbe2 JH |
11605 | } |
11606 | ||
11607 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, | |
d6bbafa1 CW |
11608 | page_flip_flags); |
11609 | if (ret) | |
11610 | goto cleanup_unpin; | |
11611 | ||
6258fbe2 | 11612 | i915_gem_request_assign(&work->flip_queued_req, request); |
d6bbafa1 CW |
11613 | } |
11614 | ||
91af127f | 11615 | if (request) |
75289874 | 11616 | i915_add_request_no_flush(request); |
91af127f | 11617 | |
1e3feefd | 11618 | work->flip_queued_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 | 11619 | work->enable_stall_check = true; |
4fa62c89 | 11620 | |
ab8d6675 | 11621 | i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, |
a9ff8714 | 11622 | to_intel_plane(primary)->frontbuffer_bit); |
c80ac854 | 11623 | mutex_unlock(&dev->struct_mutex); |
a071fa00 | 11624 | |
a9ff8714 VS |
11625 | intel_frontbuffer_flip_prepare(dev, |
11626 | to_intel_plane(primary)->frontbuffer_bit); | |
6b95a207 | 11627 | |
e5510fac JB |
11628 | trace_i915_flip_request(intel_crtc->plane, obj); |
11629 | ||
6b95a207 | 11630 | return 0; |
96b099fd | 11631 | |
4fa62c89 | 11632 | cleanup_unpin: |
3465c580 | 11633 | intel_unpin_fb_obj(fb, crtc->primary->state->rotation); |
8c9f3aaf | 11634 | cleanup_pending: |
0aa498d5 | 11635 | if (!IS_ERR_OR_NULL(request)) |
91af127f | 11636 | i915_gem_request_cancel(request); |
b4a98e57 | 11637 | atomic_dec(&intel_crtc->unpin_work_count); |
89ed88ba CW |
11638 | mutex_unlock(&dev->struct_mutex); |
11639 | cleanup: | |
f4510a27 | 11640 | crtc->primary->fb = old_fb; |
afd65eb4 | 11641 | update_state_fb(crtc->primary); |
89ed88ba CW |
11642 | |
11643 | drm_gem_object_unreference_unlocked(&obj->base); | |
ab8d6675 | 11644 | drm_framebuffer_unreference(work->old_fb); |
96b099fd | 11645 | |
5e2d7afc | 11646 | spin_lock_irq(&dev->event_lock); |
96b099fd | 11647 | intel_crtc->unpin_work = NULL; |
5e2d7afc | 11648 | spin_unlock_irq(&dev->event_lock); |
96b099fd | 11649 | |
87b6b101 | 11650 | drm_crtc_vblank_put(crtc); |
7317c75e | 11651 | free_work: |
96b099fd CW |
11652 | kfree(work); |
11653 | ||
f900db47 | 11654 | if (ret == -EIO) { |
02e0efb5 ML |
11655 | struct drm_atomic_state *state; |
11656 | struct drm_plane_state *plane_state; | |
11657 | ||
f900db47 | 11658 | out_hang: |
02e0efb5 ML |
11659 | state = drm_atomic_state_alloc(dev); |
11660 | if (!state) | |
11661 | return -ENOMEM; | |
11662 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); | |
11663 | ||
11664 | retry: | |
11665 | plane_state = drm_atomic_get_plane_state(state, primary); | |
11666 | ret = PTR_ERR_OR_ZERO(plane_state); | |
11667 | if (!ret) { | |
11668 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
11669 | ||
11670 | ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); | |
11671 | if (!ret) | |
11672 | ret = drm_atomic_commit(state); | |
11673 | } | |
11674 | ||
11675 | if (ret == -EDEADLK) { | |
11676 | drm_modeset_backoff(state->acquire_ctx); | |
11677 | drm_atomic_state_clear(state); | |
11678 | goto retry; | |
11679 | } | |
11680 | ||
11681 | if (ret) | |
11682 | drm_atomic_state_free(state); | |
11683 | ||
f0d3dad3 | 11684 | if (ret == 0 && event) { |
5e2d7afc | 11685 | spin_lock_irq(&dev->event_lock); |
a071fa00 | 11686 | drm_send_vblank_event(dev, pipe, event); |
5e2d7afc | 11687 | spin_unlock_irq(&dev->event_lock); |
f0d3dad3 | 11688 | } |
f900db47 | 11689 | } |
96b099fd | 11690 | return ret; |
6b95a207 KH |
11691 | } |
11692 | ||
da20eabd ML |
11693 | |
11694 | /** | |
11695 | * intel_wm_need_update - Check whether watermarks need updating | |
11696 | * @plane: drm plane | |
11697 | * @state: new plane state | |
11698 | * | |
11699 | * Check current plane state versus the new one to determine whether | |
11700 | * watermarks need to be recalculated. | |
11701 | * | |
11702 | * Returns true or false. | |
11703 | */ | |
11704 | static bool intel_wm_need_update(struct drm_plane *plane, | |
11705 | struct drm_plane_state *state) | |
11706 | { | |
d21fbe87 MR |
11707 | struct intel_plane_state *new = to_intel_plane_state(state); |
11708 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); | |
11709 | ||
11710 | /* Update watermarks on tiling or size changes. */ | |
92826fcd ML |
11711 | if (new->visible != cur->visible) |
11712 | return true; | |
11713 | ||
11714 | if (!cur->base.fb || !new->base.fb) | |
11715 | return false; | |
11716 | ||
11717 | if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] || | |
11718 | cur->base.rotation != new->base.rotation || | |
d21fbe87 MR |
11719 | drm_rect_width(&new->src) != drm_rect_width(&cur->src) || |
11720 | drm_rect_height(&new->src) != drm_rect_height(&cur->src) || | |
11721 | drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) || | |
11722 | drm_rect_height(&new->dst) != drm_rect_height(&cur->dst)) | |
2791a16c | 11723 | return true; |
7809e5ae | 11724 | |
2791a16c | 11725 | return false; |
7809e5ae MR |
11726 | } |
11727 | ||
d21fbe87 MR |
11728 | static bool needs_scaling(struct intel_plane_state *state) |
11729 | { | |
11730 | int src_w = drm_rect_width(&state->src) >> 16; | |
11731 | int src_h = drm_rect_height(&state->src) >> 16; | |
11732 | int dst_w = drm_rect_width(&state->dst); | |
11733 | int dst_h = drm_rect_height(&state->dst); | |
11734 | ||
11735 | return (src_w != dst_w || src_h != dst_h); | |
11736 | } | |
11737 | ||
da20eabd ML |
11738 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
11739 | struct drm_plane_state *plane_state) | |
11740 | { | |
ab1d3a0e | 11741 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
da20eabd ML |
11742 | struct drm_crtc *crtc = crtc_state->crtc; |
11743 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11744 | struct drm_plane *plane = plane_state->plane; | |
11745 | struct drm_device *dev = crtc->dev; | |
ed4a6a7c | 11746 | struct drm_i915_private *dev_priv = to_i915(dev); |
da20eabd ML |
11747 | struct intel_plane_state *old_plane_state = |
11748 | to_intel_plane_state(plane->state); | |
11749 | int idx = intel_crtc->base.base.id, ret; | |
da20eabd ML |
11750 | bool mode_changed = needs_modeset(crtc_state); |
11751 | bool was_crtc_enabled = crtc->state->active; | |
11752 | bool is_crtc_enabled = crtc_state->active; | |
da20eabd ML |
11753 | bool turn_off, turn_on, visible, was_visible; |
11754 | struct drm_framebuffer *fb = plane_state->fb; | |
11755 | ||
11756 | if (crtc_state && INTEL_INFO(dev)->gen >= 9 && | |
11757 | plane->type != DRM_PLANE_TYPE_CURSOR) { | |
11758 | ret = skl_update_scaler_plane( | |
11759 | to_intel_crtc_state(crtc_state), | |
11760 | to_intel_plane_state(plane_state)); | |
11761 | if (ret) | |
11762 | return ret; | |
11763 | } | |
11764 | ||
da20eabd ML |
11765 | was_visible = old_plane_state->visible; |
11766 | visible = to_intel_plane_state(plane_state)->visible; | |
11767 | ||
11768 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
11769 | was_visible = false; | |
11770 | ||
35c08f43 ML |
11771 | /* |
11772 | * Visibility is calculated as if the crtc was on, but | |
11773 | * after scaler setup everything depends on it being off | |
11774 | * when the crtc isn't active. | |
11775 | */ | |
11776 | if (!is_crtc_enabled) | |
11777 | to_intel_plane_state(plane_state)->visible = visible = false; | |
da20eabd ML |
11778 | |
11779 | if (!was_visible && !visible) | |
11780 | return 0; | |
11781 | ||
e8861675 ML |
11782 | if (fb != old_plane_state->base.fb) |
11783 | pipe_config->fb_changed = true; | |
11784 | ||
da20eabd ML |
11785 | turn_off = was_visible && (!visible || mode_changed); |
11786 | turn_on = visible && (!was_visible || mode_changed); | |
11787 | ||
11788 | DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx, | |
11789 | plane->base.id, fb ? fb->base.id : -1); | |
11790 | ||
11791 | DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n", | |
11792 | plane->base.id, was_visible, visible, | |
11793 | turn_off, turn_on, mode_changed); | |
11794 | ||
caed361d VS |
11795 | if (turn_on) { |
11796 | pipe_config->update_wm_pre = true; | |
11797 | ||
11798 | /* must disable cxsr around plane enable/disable */ | |
11799 | if (plane->type != DRM_PLANE_TYPE_CURSOR) | |
11800 | pipe_config->disable_cxsr = true; | |
11801 | } else if (turn_off) { | |
11802 | pipe_config->update_wm_post = true; | |
92826fcd | 11803 | |
852eb00d | 11804 | /* must disable cxsr around plane enable/disable */ |
e8861675 | 11805 | if (plane->type != DRM_PLANE_TYPE_CURSOR) |
ab1d3a0e | 11806 | pipe_config->disable_cxsr = true; |
852eb00d | 11807 | } else if (intel_wm_need_update(plane, plane_state)) { |
caed361d VS |
11808 | /* FIXME bollocks */ |
11809 | pipe_config->update_wm_pre = true; | |
11810 | pipe_config->update_wm_post = true; | |
852eb00d | 11811 | } |
da20eabd | 11812 | |
ed4a6a7c | 11813 | /* Pre-gen9 platforms need two-step watermark updates */ |
caed361d VS |
11814 | if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) && |
11815 | INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks) | |
ed4a6a7c MR |
11816 | to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true; |
11817 | ||
8be6ca85 | 11818 | if (visible || was_visible) |
cd202f69 | 11819 | pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit; |
a9ff8714 | 11820 | |
31ae71fc ML |
11821 | /* |
11822 | * WaCxSRDisabledForSpriteScaling:ivb | |
11823 | * | |
11824 | * cstate->update_wm was already set above, so this flag will | |
11825 | * take effect when we commit and program watermarks. | |
11826 | */ | |
11827 | if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) && | |
11828 | needs_scaling(to_intel_plane_state(plane_state)) && | |
11829 | !needs_scaling(old_plane_state)) | |
11830 | pipe_config->disable_lp_wm = true; | |
d21fbe87 | 11831 | |
da20eabd ML |
11832 | return 0; |
11833 | } | |
11834 | ||
6d3a1ce7 ML |
11835 | static bool encoders_cloneable(const struct intel_encoder *a, |
11836 | const struct intel_encoder *b) | |
11837 | { | |
11838 | /* masks could be asymmetric, so check both ways */ | |
11839 | return a == b || (a->cloneable & (1 << b->type) && | |
11840 | b->cloneable & (1 << a->type)); | |
11841 | } | |
11842 | ||
11843 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
11844 | struct intel_crtc *crtc, | |
11845 | struct intel_encoder *encoder) | |
11846 | { | |
11847 | struct intel_encoder *source_encoder; | |
11848 | struct drm_connector *connector; | |
11849 | struct drm_connector_state *connector_state; | |
11850 | int i; | |
11851 | ||
11852 | for_each_connector_in_state(state, connector, connector_state, i) { | |
11853 | if (connector_state->crtc != &crtc->base) | |
11854 | continue; | |
11855 | ||
11856 | source_encoder = | |
11857 | to_intel_encoder(connector_state->best_encoder); | |
11858 | if (!encoders_cloneable(encoder, source_encoder)) | |
11859 | return false; | |
11860 | } | |
11861 | ||
11862 | return true; | |
11863 | } | |
11864 | ||
11865 | static bool check_encoder_cloning(struct drm_atomic_state *state, | |
11866 | struct intel_crtc *crtc) | |
11867 | { | |
11868 | struct intel_encoder *encoder; | |
11869 | struct drm_connector *connector; | |
11870 | struct drm_connector_state *connector_state; | |
11871 | int i; | |
11872 | ||
11873 | for_each_connector_in_state(state, connector, connector_state, i) { | |
11874 | if (connector_state->crtc != &crtc->base) | |
11875 | continue; | |
11876 | ||
11877 | encoder = to_intel_encoder(connector_state->best_encoder); | |
11878 | if (!check_single_encoder_cloning(state, crtc, encoder)) | |
11879 | return false; | |
11880 | } | |
11881 | ||
11882 | return true; | |
11883 | } | |
11884 | ||
11885 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, | |
11886 | struct drm_crtc_state *crtc_state) | |
11887 | { | |
cf5a15be | 11888 | struct drm_device *dev = crtc->dev; |
ad421372 | 11889 | struct drm_i915_private *dev_priv = dev->dev_private; |
6d3a1ce7 | 11890 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
11891 | struct intel_crtc_state *pipe_config = |
11892 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 11893 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 11894 | int ret; |
6d3a1ce7 ML |
11895 | bool mode_changed = needs_modeset(crtc_state); |
11896 | ||
11897 | if (mode_changed && !check_encoder_cloning(state, intel_crtc)) { | |
11898 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
11899 | return -EINVAL; | |
11900 | } | |
11901 | ||
852eb00d | 11902 | if (mode_changed && !crtc_state->active) |
caed361d | 11903 | pipe_config->update_wm_post = true; |
eddfcbcd | 11904 | |
ad421372 ML |
11905 | if (mode_changed && crtc_state->enable && |
11906 | dev_priv->display.crtc_compute_clock && | |
8106ddbd | 11907 | !WARN_ON(pipe_config->shared_dpll)) { |
ad421372 ML |
11908 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, |
11909 | pipe_config); | |
11910 | if (ret) | |
11911 | return ret; | |
11912 | } | |
11913 | ||
82cf435b LL |
11914 | if (crtc_state->color_mgmt_changed) { |
11915 | ret = intel_color_check(crtc, crtc_state); | |
11916 | if (ret) | |
11917 | return ret; | |
11918 | } | |
11919 | ||
e435d6e5 | 11920 | ret = 0; |
86c8bbbe | 11921 | if (dev_priv->display.compute_pipe_wm) { |
e3bddded | 11922 | ret = dev_priv->display.compute_pipe_wm(pipe_config); |
ed4a6a7c MR |
11923 | if (ret) { |
11924 | DRM_DEBUG_KMS("Target pipe watermarks are invalid\n"); | |
11925 | return ret; | |
11926 | } | |
11927 | } | |
11928 | ||
11929 | if (dev_priv->display.compute_intermediate_wm && | |
11930 | !to_intel_atomic_state(state)->skip_intermediate_wm) { | |
11931 | if (WARN_ON(!dev_priv->display.compute_pipe_wm)) | |
11932 | return 0; | |
11933 | ||
11934 | /* | |
11935 | * Calculate 'intermediate' watermarks that satisfy both the | |
11936 | * old state and the new state. We can program these | |
11937 | * immediately. | |
11938 | */ | |
11939 | ret = dev_priv->display.compute_intermediate_wm(crtc->dev, | |
11940 | intel_crtc, | |
11941 | pipe_config); | |
11942 | if (ret) { | |
11943 | DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n"); | |
86c8bbbe | 11944 | return ret; |
ed4a6a7c | 11945 | } |
86c8bbbe MR |
11946 | } |
11947 | ||
e435d6e5 ML |
11948 | if (INTEL_INFO(dev)->gen >= 9) { |
11949 | if (mode_changed) | |
11950 | ret = skl_update_scaler_crtc(pipe_config); | |
11951 | ||
11952 | if (!ret) | |
11953 | ret = intel_atomic_setup_scalers(dev, intel_crtc, | |
11954 | pipe_config); | |
11955 | } | |
11956 | ||
11957 | return ret; | |
6d3a1ce7 ML |
11958 | } |
11959 | ||
65b38e0d | 11960 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 | 11961 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
ea2c67bb MR |
11962 | .atomic_begin = intel_begin_crtc_commit, |
11963 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 11964 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
11965 | }; |
11966 | ||
d29b2f9d ACO |
11967 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
11968 | { | |
11969 | struct intel_connector *connector; | |
11970 | ||
11971 | for_each_intel_connector(dev, connector) { | |
11972 | if (connector->base.encoder) { | |
11973 | connector->base.state->best_encoder = | |
11974 | connector->base.encoder; | |
11975 | connector->base.state->crtc = | |
11976 | connector->base.encoder->crtc; | |
11977 | } else { | |
11978 | connector->base.state->best_encoder = NULL; | |
11979 | connector->base.state->crtc = NULL; | |
11980 | } | |
11981 | } | |
11982 | } | |
11983 | ||
050f7aeb | 11984 | static void |
eba905b2 | 11985 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 11986 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
11987 | { |
11988 | int bpp = pipe_config->pipe_bpp; | |
11989 | ||
11990 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
11991 | connector->base.base.id, | |
c23cc417 | 11992 | connector->base.name); |
050f7aeb DV |
11993 | |
11994 | /* Don't use an invalid EDID bpc value */ | |
11995 | if (connector->base.display_info.bpc && | |
11996 | connector->base.display_info.bpc * 3 < bpp) { | |
11997 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
11998 | bpp, connector->base.display_info.bpc*3); | |
11999 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
12000 | } | |
12001 | ||
013dd9e0 JN |
12002 | /* Clamp bpp to default limit on screens without EDID 1.4 */ |
12003 | if (connector->base.display_info.bpc == 0) { | |
12004 | int type = connector->base.connector_type; | |
12005 | int clamp_bpp = 24; | |
12006 | ||
12007 | /* Fall back to 18 bpp when DP sink capability is unknown. */ | |
12008 | if (type == DRM_MODE_CONNECTOR_DisplayPort || | |
12009 | type == DRM_MODE_CONNECTOR_eDP) | |
12010 | clamp_bpp = 18; | |
12011 | ||
12012 | if (bpp > clamp_bpp) { | |
12013 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n", | |
12014 | bpp, clamp_bpp); | |
12015 | pipe_config->pipe_bpp = clamp_bpp; | |
12016 | } | |
050f7aeb DV |
12017 | } |
12018 | } | |
12019 | ||
4e53c2e0 | 12020 | static int |
050f7aeb | 12021 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 12022 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 12023 | { |
050f7aeb | 12024 | struct drm_device *dev = crtc->base.dev; |
1486017f | 12025 | struct drm_atomic_state *state; |
da3ced29 ACO |
12026 | struct drm_connector *connector; |
12027 | struct drm_connector_state *connector_state; | |
1486017f | 12028 | int bpp, i; |
4e53c2e0 | 12029 | |
666a4537 | 12030 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) |
4e53c2e0 | 12031 | bpp = 10*3; |
d328c9d7 DV |
12032 | else if (INTEL_INFO(dev)->gen >= 5) |
12033 | bpp = 12*3; | |
12034 | else | |
12035 | bpp = 8*3; | |
12036 | ||
4e53c2e0 | 12037 | |
4e53c2e0 DV |
12038 | pipe_config->pipe_bpp = bpp; |
12039 | ||
1486017f ACO |
12040 | state = pipe_config->base.state; |
12041 | ||
4e53c2e0 | 12042 | /* Clamp display bpp to EDID value */ |
da3ced29 ACO |
12043 | for_each_connector_in_state(state, connector, connector_state, i) { |
12044 | if (connector_state->crtc != &crtc->base) | |
4e53c2e0 DV |
12045 | continue; |
12046 | ||
da3ced29 ACO |
12047 | connected_sink_compute_bpp(to_intel_connector(connector), |
12048 | pipe_config); | |
4e53c2e0 DV |
12049 | } |
12050 | ||
12051 | return bpp; | |
12052 | } | |
12053 | ||
644db711 DV |
12054 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
12055 | { | |
12056 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
12057 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 12058 | mode->crtc_clock, |
644db711 DV |
12059 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
12060 | mode->crtc_hsync_end, mode->crtc_htotal, | |
12061 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
12062 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
12063 | } | |
12064 | ||
c0b03411 | 12065 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 12066 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
12067 | const char *context) |
12068 | { | |
6a60cd87 CK |
12069 | struct drm_device *dev = crtc->base.dev; |
12070 | struct drm_plane *plane; | |
12071 | struct intel_plane *intel_plane; | |
12072 | struct intel_plane_state *state; | |
12073 | struct drm_framebuffer *fb; | |
12074 | ||
12075 | DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id, | |
12076 | context, pipe_config, pipe_name(crtc->pipe)); | |
c0b03411 | 12077 | |
da205630 | 12078 | DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder)); |
c0b03411 DV |
12079 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", |
12080 | pipe_config->pipe_bpp, pipe_config->dither); | |
12081 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
12082 | pipe_config->has_pch_encoder, | |
12083 | pipe_config->fdi_lanes, | |
12084 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
12085 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
12086 | pipe_config->fdi_m_n.tu); | |
90a6b7b0 | 12087 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
eb14cb74 | 12088 | pipe_config->has_dp_encoder, |
90a6b7b0 | 12089 | pipe_config->lane_count, |
eb14cb74 VS |
12090 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, |
12091 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
12092 | pipe_config->dp_m_n.tu); | |
b95af8be | 12093 | |
90a6b7b0 | 12094 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", |
b95af8be | 12095 | pipe_config->has_dp_encoder, |
90a6b7b0 | 12096 | pipe_config->lane_count, |
b95af8be VK |
12097 | pipe_config->dp_m2_n2.gmch_m, |
12098 | pipe_config->dp_m2_n2.gmch_n, | |
12099 | pipe_config->dp_m2_n2.link_m, | |
12100 | pipe_config->dp_m2_n2.link_n, | |
12101 | pipe_config->dp_m2_n2.tu); | |
12102 | ||
55072d19 DV |
12103 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
12104 | pipe_config->has_audio, | |
12105 | pipe_config->has_infoframe); | |
12106 | ||
c0b03411 | 12107 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 12108 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 12109 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
12110 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
12111 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 12112 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
12113 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
12114 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
0ec463d3 TU |
12115 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", |
12116 | crtc->num_scalers, | |
12117 | pipe_config->scaler_state.scaler_users, | |
12118 | pipe_config->scaler_state.scaler_id); | |
c0b03411 DV |
12119 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
12120 | pipe_config->gmch_pfit.control, | |
12121 | pipe_config->gmch_pfit.pgm_ratios, | |
12122 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 12123 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 12124 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
12125 | pipe_config->pch_pfit.size, |
12126 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 12127 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 12128 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
6a60cd87 | 12129 | |
415ff0f6 | 12130 | if (IS_BROXTON(dev)) { |
05712c15 | 12131 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," |
415ff0f6 | 12132 | "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " |
c8453338 | 12133 | "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", |
415ff0f6 TU |
12134 | pipe_config->ddi_pll_sel, |
12135 | pipe_config->dpll_hw_state.ebb0, | |
05712c15 | 12136 | pipe_config->dpll_hw_state.ebb4, |
415ff0f6 TU |
12137 | pipe_config->dpll_hw_state.pll0, |
12138 | pipe_config->dpll_hw_state.pll1, | |
12139 | pipe_config->dpll_hw_state.pll2, | |
12140 | pipe_config->dpll_hw_state.pll3, | |
12141 | pipe_config->dpll_hw_state.pll6, | |
12142 | pipe_config->dpll_hw_state.pll8, | |
05712c15 | 12143 | pipe_config->dpll_hw_state.pll9, |
c8453338 | 12144 | pipe_config->dpll_hw_state.pll10, |
415ff0f6 | 12145 | pipe_config->dpll_hw_state.pcsdw12); |
ef11bdb3 | 12146 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
415ff0f6 TU |
12147 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " |
12148 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", | |
12149 | pipe_config->ddi_pll_sel, | |
12150 | pipe_config->dpll_hw_state.ctrl1, | |
12151 | pipe_config->dpll_hw_state.cfgcr1, | |
12152 | pipe_config->dpll_hw_state.cfgcr2); | |
12153 | } else if (HAS_DDI(dev)) { | |
1260f07e | 12154 | DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", |
415ff0f6 | 12155 | pipe_config->ddi_pll_sel, |
00490c22 ML |
12156 | pipe_config->dpll_hw_state.wrpll, |
12157 | pipe_config->dpll_hw_state.spll); | |
415ff0f6 TU |
12158 | } else { |
12159 | DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " | |
12160 | "fp0: 0x%x, fp1: 0x%x\n", | |
12161 | pipe_config->dpll_hw_state.dpll, | |
12162 | pipe_config->dpll_hw_state.dpll_md, | |
12163 | pipe_config->dpll_hw_state.fp0, | |
12164 | pipe_config->dpll_hw_state.fp1); | |
12165 | } | |
12166 | ||
6a60cd87 CK |
12167 | DRM_DEBUG_KMS("planes on this crtc\n"); |
12168 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
12169 | intel_plane = to_intel_plane(plane); | |
12170 | if (intel_plane->pipe != crtc->pipe) | |
12171 | continue; | |
12172 | ||
12173 | state = to_intel_plane_state(plane->state); | |
12174 | fb = state->base.fb; | |
12175 | if (!fb) { | |
12176 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d " | |
12177 | "disabled, scaler_id = %d\n", | |
12178 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12179 | plane->base.id, intel_plane->pipe, | |
12180 | (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1, | |
12181 | drm_plane_index(plane), state->scaler_id); | |
12182 | continue; | |
12183 | } | |
12184 | ||
12185 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled", | |
12186 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12187 | plane->base.id, intel_plane->pipe, | |
12188 | crtc->base.primary == plane ? 0 : intel_plane->plane + 1, | |
12189 | drm_plane_index(plane)); | |
12190 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x", | |
12191 | fb->base.id, fb->width, fb->height, fb->pixel_format); | |
12192 | DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n", | |
12193 | state->scaler_id, | |
12194 | state->src.x1 >> 16, state->src.y1 >> 16, | |
12195 | drm_rect_width(&state->src) >> 16, | |
12196 | drm_rect_height(&state->src) >> 16, | |
12197 | state->dst.x1, state->dst.y1, | |
12198 | drm_rect_width(&state->dst), drm_rect_height(&state->dst)); | |
12199 | } | |
c0b03411 DV |
12200 | } |
12201 | ||
5448a00d | 12202 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 12203 | { |
5448a00d | 12204 | struct drm_device *dev = state->dev; |
da3ced29 | 12205 | struct drm_connector *connector; |
00f0b378 VS |
12206 | unsigned int used_ports = 0; |
12207 | ||
12208 | /* | |
12209 | * Walk the connector list instead of the encoder | |
12210 | * list to detect the problem on ddi platforms | |
12211 | * where there's just one encoder per digital port. | |
12212 | */ | |
0bff4858 VS |
12213 | drm_for_each_connector(connector, dev) { |
12214 | struct drm_connector_state *connector_state; | |
12215 | struct intel_encoder *encoder; | |
12216 | ||
12217 | connector_state = drm_atomic_get_existing_connector_state(state, connector); | |
12218 | if (!connector_state) | |
12219 | connector_state = connector->state; | |
12220 | ||
5448a00d | 12221 | if (!connector_state->best_encoder) |
00f0b378 VS |
12222 | continue; |
12223 | ||
5448a00d ACO |
12224 | encoder = to_intel_encoder(connector_state->best_encoder); |
12225 | ||
12226 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
12227 | |
12228 | switch (encoder->type) { | |
12229 | unsigned int port_mask; | |
12230 | case INTEL_OUTPUT_UNKNOWN: | |
12231 | if (WARN_ON(!HAS_DDI(dev))) | |
12232 | break; | |
12233 | case INTEL_OUTPUT_DISPLAYPORT: | |
12234 | case INTEL_OUTPUT_HDMI: | |
12235 | case INTEL_OUTPUT_EDP: | |
12236 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
12237 | ||
12238 | /* the same port mustn't appear more than once */ | |
12239 | if (used_ports & port_mask) | |
12240 | return false; | |
12241 | ||
12242 | used_ports |= port_mask; | |
12243 | default: | |
12244 | break; | |
12245 | } | |
12246 | } | |
12247 | ||
12248 | return true; | |
12249 | } | |
12250 | ||
83a57153 ACO |
12251 | static void |
12252 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
12253 | { | |
12254 | struct drm_crtc_state tmp_state; | |
663a3640 | 12255 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 | 12256 | struct intel_dpll_hw_state dpll_hw_state; |
8106ddbd | 12257 | struct intel_shared_dpll *shared_dpll; |
8504c74c | 12258 | uint32_t ddi_pll_sel; |
c4e2d043 | 12259 | bool force_thru; |
83a57153 | 12260 | |
7546a384 ACO |
12261 | /* FIXME: before the switch to atomic started, a new pipe_config was |
12262 | * kzalloc'd. Code that depends on any field being zero should be | |
12263 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
12264 | * only fields that are know to not cause problems are preserved. */ | |
12265 | ||
83a57153 | 12266 | tmp_state = crtc_state->base; |
663a3640 | 12267 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
12268 | shared_dpll = crtc_state->shared_dpll; |
12269 | dpll_hw_state = crtc_state->dpll_hw_state; | |
8504c74c | 12270 | ddi_pll_sel = crtc_state->ddi_pll_sel; |
c4e2d043 | 12271 | force_thru = crtc_state->pch_pfit.force_thru; |
4978cc93 | 12272 | |
83a57153 | 12273 | memset(crtc_state, 0, sizeof *crtc_state); |
4978cc93 | 12274 | |
83a57153 | 12275 | crtc_state->base = tmp_state; |
663a3640 | 12276 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
12277 | crtc_state->shared_dpll = shared_dpll; |
12278 | crtc_state->dpll_hw_state = dpll_hw_state; | |
8504c74c | 12279 | crtc_state->ddi_pll_sel = ddi_pll_sel; |
c4e2d043 | 12280 | crtc_state->pch_pfit.force_thru = force_thru; |
83a57153 ACO |
12281 | } |
12282 | ||
548ee15b | 12283 | static int |
b8cecdf5 | 12284 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 12285 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 12286 | { |
b359283a | 12287 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 12288 | struct intel_encoder *encoder; |
da3ced29 | 12289 | struct drm_connector *connector; |
0b901879 | 12290 | struct drm_connector_state *connector_state; |
d328c9d7 | 12291 | int base_bpp, ret = -EINVAL; |
0b901879 | 12292 | int i; |
e29c22c0 | 12293 | bool retry = true; |
ee7b9f93 | 12294 | |
83a57153 | 12295 | clear_intel_crtc_state(pipe_config); |
7758a113 | 12296 | |
e143a21c DV |
12297 | pipe_config->cpu_transcoder = |
12298 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 12299 | |
2960bc9c ID |
12300 | /* |
12301 | * Sanitize sync polarity flags based on requested ones. If neither | |
12302 | * positive or negative polarity is requested, treat this as meaning | |
12303 | * negative polarity. | |
12304 | */ | |
2d112de7 | 12305 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12306 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 12307 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 12308 | |
2d112de7 | 12309 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12310 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 12311 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 12312 | |
d328c9d7 DV |
12313 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
12314 | pipe_config); | |
12315 | if (base_bpp < 0) | |
4e53c2e0 DV |
12316 | goto fail; |
12317 | ||
e41a56be VS |
12318 | /* |
12319 | * Determine the real pipe dimensions. Note that stereo modes can | |
12320 | * increase the actual pipe size due to the frame doubling and | |
12321 | * insertion of additional space for blanks between the frame. This | |
12322 | * is stored in the crtc timings. We use the requested mode to do this | |
12323 | * computation to clearly distinguish it from the adjusted mode, which | |
12324 | * can be changed by the connectors in the below retry loop. | |
12325 | */ | |
2d112de7 | 12326 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
12327 | &pipe_config->pipe_src_w, |
12328 | &pipe_config->pipe_src_h); | |
e41a56be | 12329 | |
e29c22c0 | 12330 | encoder_retry: |
ef1b460d | 12331 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 12332 | pipe_config->port_clock = 0; |
ef1b460d | 12333 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 12334 | |
135c81b8 | 12335 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
12336 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
12337 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 12338 | |
7758a113 DV |
12339 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
12340 | * adjust it according to limitations or connector properties, and also | |
12341 | * a chance to reject the mode entirely. | |
47f1c6c9 | 12342 | */ |
da3ced29 | 12343 | for_each_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 12344 | if (connector_state->crtc != crtc) |
7758a113 | 12345 | continue; |
7ae89233 | 12346 | |
0b901879 ACO |
12347 | encoder = to_intel_encoder(connector_state->best_encoder); |
12348 | ||
efea6e8e DV |
12349 | if (!(encoder->compute_config(encoder, pipe_config))) { |
12350 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
12351 | goto fail; |
12352 | } | |
ee7b9f93 | 12353 | } |
47f1c6c9 | 12354 | |
ff9a6750 DV |
12355 | /* Set default port clock if not overwritten by the encoder. Needs to be |
12356 | * done afterwards in case the encoder adjusts the mode. */ | |
12357 | if (!pipe_config->port_clock) | |
2d112de7 | 12358 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 12359 | * pipe_config->pixel_multiplier; |
ff9a6750 | 12360 | |
a43f6e0f | 12361 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 12362 | if (ret < 0) { |
7758a113 DV |
12363 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
12364 | goto fail; | |
ee7b9f93 | 12365 | } |
e29c22c0 DV |
12366 | |
12367 | if (ret == RETRY) { | |
12368 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
12369 | ret = -EINVAL; | |
12370 | goto fail; | |
12371 | } | |
12372 | ||
12373 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
12374 | retry = false; | |
12375 | goto encoder_retry; | |
12376 | } | |
12377 | ||
e8fa4270 DV |
12378 | /* Dithering seems to not pass-through bits correctly when it should, so |
12379 | * only enable it on 6bpc panels. */ | |
12380 | pipe_config->dither = pipe_config->pipe_bpp == 6*3; | |
62f0ace5 | 12381 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 12382 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 12383 | |
7758a113 | 12384 | fail: |
548ee15b | 12385 | return ret; |
ee7b9f93 | 12386 | } |
47f1c6c9 | 12387 | |
ea9d758d | 12388 | static void |
4740b0f2 | 12389 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 12390 | { |
0a9ab303 ACO |
12391 | struct drm_crtc *crtc; |
12392 | struct drm_crtc_state *crtc_state; | |
8a75d157 | 12393 | int i; |
ea9d758d | 12394 | |
7668851f | 12395 | /* Double check state. */ |
8a75d157 | 12396 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
3cb480bc | 12397 | to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); |
fc467a22 ML |
12398 | |
12399 | /* Update hwmode for vblank functions */ | |
12400 | if (crtc->state->active) | |
12401 | crtc->hwmode = crtc->state->adjusted_mode; | |
12402 | else | |
12403 | crtc->hwmode.crtc_clock = 0; | |
61067a5e ML |
12404 | |
12405 | /* | |
12406 | * Update legacy state to satisfy fbc code. This can | |
12407 | * be removed when fbc uses the atomic state. | |
12408 | */ | |
12409 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
12410 | struct drm_plane_state *plane_state = crtc->primary->state; | |
12411 | ||
12412 | crtc->primary->fb = plane_state->fb; | |
12413 | crtc->x = plane_state->src_x >> 16; | |
12414 | crtc->y = plane_state->src_y >> 16; | |
12415 | } | |
ea9d758d | 12416 | } |
ea9d758d DV |
12417 | } |
12418 | ||
3bd26263 | 12419 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 12420 | { |
3bd26263 | 12421 | int diff; |
f1f644dc JB |
12422 | |
12423 | if (clock1 == clock2) | |
12424 | return true; | |
12425 | ||
12426 | if (!clock1 || !clock2) | |
12427 | return false; | |
12428 | ||
12429 | diff = abs(clock1 - clock2); | |
12430 | ||
12431 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
12432 | return true; | |
12433 | ||
12434 | return false; | |
12435 | } | |
12436 | ||
25c5b266 DV |
12437 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
12438 | list_for_each_entry((intel_crtc), \ | |
12439 | &(dev)->mode_config.crtc_list, \ | |
12440 | base.head) \ | |
95150bdf | 12441 | for_each_if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 12442 | |
cfb23ed6 ML |
12443 | static bool |
12444 | intel_compare_m_n(unsigned int m, unsigned int n, | |
12445 | unsigned int m2, unsigned int n2, | |
12446 | bool exact) | |
12447 | { | |
12448 | if (m == m2 && n == n2) | |
12449 | return true; | |
12450 | ||
12451 | if (exact || !m || !n || !m2 || !n2) | |
12452 | return false; | |
12453 | ||
12454 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
12455 | ||
31d10b57 ML |
12456 | if (n > n2) { |
12457 | while (n > n2) { | |
cfb23ed6 ML |
12458 | m2 <<= 1; |
12459 | n2 <<= 1; | |
12460 | } | |
31d10b57 ML |
12461 | } else if (n < n2) { |
12462 | while (n < n2) { | |
cfb23ed6 ML |
12463 | m <<= 1; |
12464 | n <<= 1; | |
12465 | } | |
12466 | } | |
12467 | ||
31d10b57 ML |
12468 | if (n != n2) |
12469 | return false; | |
12470 | ||
12471 | return intel_fuzzy_clock_check(m, m2); | |
cfb23ed6 ML |
12472 | } |
12473 | ||
12474 | static bool | |
12475 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
12476 | struct intel_link_m_n *m2_n2, | |
12477 | bool adjust) | |
12478 | { | |
12479 | if (m_n->tu == m2_n2->tu && | |
12480 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
12481 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
12482 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
12483 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
12484 | if (adjust) | |
12485 | *m2_n2 = *m_n; | |
12486 | ||
12487 | return true; | |
12488 | } | |
12489 | ||
12490 | return false; | |
12491 | } | |
12492 | ||
0e8ffe1b | 12493 | static bool |
2fa2fe9a | 12494 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b | 12495 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
12496 | struct intel_crtc_state *pipe_config, |
12497 | bool adjust) | |
0e8ffe1b | 12498 | { |
cfb23ed6 ML |
12499 | bool ret = true; |
12500 | ||
12501 | #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \ | |
12502 | do { \ | |
12503 | if (!adjust) \ | |
12504 | DRM_ERROR(fmt, ##__VA_ARGS__); \ | |
12505 | else \ | |
12506 | DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \ | |
12507 | } while (0) | |
12508 | ||
66e985c0 DV |
12509 | #define PIPE_CONF_CHECK_X(name) \ |
12510 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12511 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
66e985c0 DV |
12512 | "(expected 0x%08x, found 0x%08x)\n", \ |
12513 | current_config->name, \ | |
12514 | pipe_config->name); \ | |
cfb23ed6 | 12515 | ret = false; \ |
66e985c0 DV |
12516 | } |
12517 | ||
08a24034 DV |
12518 | #define PIPE_CONF_CHECK_I(name) \ |
12519 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12520 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
08a24034 DV |
12521 | "(expected %i, found %i)\n", \ |
12522 | current_config->name, \ | |
12523 | pipe_config->name); \ | |
cfb23ed6 ML |
12524 | ret = false; \ |
12525 | } | |
12526 | ||
8106ddbd ACO |
12527 | #define PIPE_CONF_CHECK_P(name) \ |
12528 | if (current_config->name != pipe_config->name) { \ | |
12529 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12530 | "(expected %p, found %p)\n", \ | |
12531 | current_config->name, \ | |
12532 | pipe_config->name); \ | |
12533 | ret = false; \ | |
12534 | } | |
12535 | ||
cfb23ed6 ML |
12536 | #define PIPE_CONF_CHECK_M_N(name) \ |
12537 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12538 | &pipe_config->name,\ | |
12539 | adjust)) { \ | |
12540 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12541 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12542 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12543 | current_config->name.tu, \ | |
12544 | current_config->name.gmch_m, \ | |
12545 | current_config->name.gmch_n, \ | |
12546 | current_config->name.link_m, \ | |
12547 | current_config->name.link_n, \ | |
12548 | pipe_config->name.tu, \ | |
12549 | pipe_config->name.gmch_m, \ | |
12550 | pipe_config->name.gmch_n, \ | |
12551 | pipe_config->name.link_m, \ | |
12552 | pipe_config->name.link_n); \ | |
12553 | ret = false; \ | |
12554 | } | |
12555 | ||
12556 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ | |
12557 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12558 | &pipe_config->name, adjust) && \ | |
12559 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
12560 | &pipe_config->name, adjust)) { \ | |
12561 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12562 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12563 | "or tu %i gmch %i/%i link %i/%i, " \ | |
12564 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12565 | current_config->name.tu, \ | |
12566 | current_config->name.gmch_m, \ | |
12567 | current_config->name.gmch_n, \ | |
12568 | current_config->name.link_m, \ | |
12569 | current_config->name.link_n, \ | |
12570 | current_config->alt_name.tu, \ | |
12571 | current_config->alt_name.gmch_m, \ | |
12572 | current_config->alt_name.gmch_n, \ | |
12573 | current_config->alt_name.link_m, \ | |
12574 | current_config->alt_name.link_n, \ | |
12575 | pipe_config->name.tu, \ | |
12576 | pipe_config->name.gmch_m, \ | |
12577 | pipe_config->name.gmch_n, \ | |
12578 | pipe_config->name.link_m, \ | |
12579 | pipe_config->name.link_n); \ | |
12580 | ret = false; \ | |
88adfff1 DV |
12581 | } |
12582 | ||
b95af8be VK |
12583 | /* This is required for BDW+ where there is only one set of registers for |
12584 | * switching between high and low RR. | |
12585 | * This macro can be used whenever a comparison has to be made between one | |
12586 | * hw state and multiple sw state variables. | |
12587 | */ | |
12588 | #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ | |
12589 | if ((current_config->name != pipe_config->name) && \ | |
12590 | (current_config->alt_name != pipe_config->name)) { \ | |
cfb23ed6 | 12591 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
b95af8be VK |
12592 | "(expected %i or %i, found %i)\n", \ |
12593 | current_config->name, \ | |
12594 | current_config->alt_name, \ | |
12595 | pipe_config->name); \ | |
cfb23ed6 | 12596 | ret = false; \ |
b95af8be VK |
12597 | } |
12598 | ||
1bd1bd80 DV |
12599 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
12600 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
cfb23ed6 | 12601 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
12602 | "(expected %i, found %i)\n", \ |
12603 | current_config->name & (mask), \ | |
12604 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 12605 | ret = false; \ |
1bd1bd80 DV |
12606 | } |
12607 | ||
5e550656 VS |
12608 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
12609 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
cfb23ed6 | 12610 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
5e550656 VS |
12611 | "(expected %i, found %i)\n", \ |
12612 | current_config->name, \ | |
12613 | pipe_config->name); \ | |
cfb23ed6 | 12614 | ret = false; \ |
5e550656 VS |
12615 | } |
12616 | ||
bb760063 DV |
12617 | #define PIPE_CONF_QUIRK(quirk) \ |
12618 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
12619 | ||
eccb140b DV |
12620 | PIPE_CONF_CHECK_I(cpu_transcoder); |
12621 | ||
08a24034 DV |
12622 | PIPE_CONF_CHECK_I(has_pch_encoder); |
12623 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 12624 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 12625 | |
eb14cb74 | 12626 | PIPE_CONF_CHECK_I(has_dp_encoder); |
90a6b7b0 | 12627 | PIPE_CONF_CHECK_I(lane_count); |
b95af8be VK |
12628 | |
12629 | if (INTEL_INFO(dev)->gen < 8) { | |
cfb23ed6 ML |
12630 | PIPE_CONF_CHECK_M_N(dp_m_n); |
12631 | ||
cfb23ed6 ML |
12632 | if (current_config->has_drrs) |
12633 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
12634 | } else | |
12635 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 12636 | |
a65347ba JN |
12637 | PIPE_CONF_CHECK_I(has_dsi_encoder); |
12638 | ||
2d112de7 ACO |
12639 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
12640 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
12641 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
12642 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
12643 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
12644 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 12645 | |
2d112de7 ACO |
12646 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
12647 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
12648 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
12649 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
12650 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
12651 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 12652 | |
c93f54cf | 12653 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 12654 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 | 12655 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
666a4537 | 12656 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
b5a9fa09 | 12657 | PIPE_CONF_CHECK_I(limited_color_range); |
e43823ec | 12658 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 12659 | |
9ed109a7 DV |
12660 | PIPE_CONF_CHECK_I(has_audio); |
12661 | ||
2d112de7 | 12662 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
12663 | DRM_MODE_FLAG_INTERLACE); |
12664 | ||
bb760063 | 12665 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 12666 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12667 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 12668 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12669 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 12670 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12671 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 12672 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
12673 | DRM_MODE_FLAG_NVSYNC); |
12674 | } | |
045ac3b5 | 12675 | |
333b8ca8 | 12676 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a DV |
12677 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
12678 | if (INTEL_INFO(dev)->gen < 4) | |
12679 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
333b8ca8 | 12680 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 12681 | |
bfd16b2a ML |
12682 | if (!adjust) { |
12683 | PIPE_CONF_CHECK_I(pipe_src_w); | |
12684 | PIPE_CONF_CHECK_I(pipe_src_h); | |
12685 | ||
12686 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
12687 | if (current_config->pch_pfit.enabled) { | |
12688 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
12689 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
12690 | } | |
2fa2fe9a | 12691 | |
7aefe2b5 ML |
12692 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
12693 | } | |
a1b2278e | 12694 | |
e59150dc JB |
12695 | /* BDW+ don't expose a synchronous way to read the state */ |
12696 | if (IS_HASWELL(dev)) | |
12697 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 12698 | |
282740f7 VS |
12699 | PIPE_CONF_CHECK_I(double_wide); |
12700 | ||
26804afd DV |
12701 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
12702 | ||
8106ddbd | 12703 | PIPE_CONF_CHECK_P(shared_dpll); |
66e985c0 | 12704 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 12705 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
12706 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
12707 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 12708 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
00490c22 | 12709 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
3f4cd19f DL |
12710 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
12711 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
12712 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 12713 | |
42571aef VS |
12714 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
12715 | PIPE_CONF_CHECK_I(pipe_bpp); | |
12716 | ||
2d112de7 | 12717 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 12718 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 12719 | |
66e985c0 | 12720 | #undef PIPE_CONF_CHECK_X |
08a24034 | 12721 | #undef PIPE_CONF_CHECK_I |
8106ddbd | 12722 | #undef PIPE_CONF_CHECK_P |
b95af8be | 12723 | #undef PIPE_CONF_CHECK_I_ALT |
1bd1bd80 | 12724 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 12725 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 12726 | #undef PIPE_CONF_QUIRK |
cfb23ed6 | 12727 | #undef INTEL_ERR_OR_DBG_KMS |
88adfff1 | 12728 | |
cfb23ed6 | 12729 | return ret; |
0e8ffe1b DV |
12730 | } |
12731 | ||
e3b247da VS |
12732 | static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, |
12733 | const struct intel_crtc_state *pipe_config) | |
12734 | { | |
12735 | if (pipe_config->has_pch_encoder) { | |
21a727b3 | 12736 | int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
e3b247da VS |
12737 | &pipe_config->fdi_m_n); |
12738 | int dotclock = pipe_config->base.adjusted_mode.crtc_clock; | |
12739 | ||
12740 | /* | |
12741 | * FDI already provided one idea for the dotclock. | |
12742 | * Yell if the encoder disagrees. | |
12743 | */ | |
12744 | WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock), | |
12745 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", | |
12746 | fdi_dotclock, dotclock); | |
12747 | } | |
12748 | } | |
12749 | ||
08db6652 DL |
12750 | static void check_wm_state(struct drm_device *dev) |
12751 | { | |
12752 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12753 | struct skl_ddb_allocation hw_ddb, *sw_ddb; | |
12754 | struct intel_crtc *intel_crtc; | |
12755 | int plane; | |
12756 | ||
12757 | if (INTEL_INFO(dev)->gen < 9) | |
12758 | return; | |
12759 | ||
12760 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
12761 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
12762 | ||
12763 | for_each_intel_crtc(dev, intel_crtc) { | |
12764 | struct skl_ddb_entry *hw_entry, *sw_entry; | |
12765 | const enum pipe pipe = intel_crtc->pipe; | |
12766 | ||
12767 | if (!intel_crtc->active) | |
12768 | continue; | |
12769 | ||
12770 | /* planes */ | |
dd740780 | 12771 | for_each_plane(dev_priv, pipe, plane) { |
08db6652 DL |
12772 | hw_entry = &hw_ddb.plane[pipe][plane]; |
12773 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
12774 | ||
12775 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12776 | continue; | |
12777 | ||
12778 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " | |
12779 | "(expected (%u,%u), found (%u,%u))\n", | |
12780 | pipe_name(pipe), plane + 1, | |
12781 | sw_entry->start, sw_entry->end, | |
12782 | hw_entry->start, hw_entry->end); | |
12783 | } | |
12784 | ||
12785 | /* cursor */ | |
4969d33e MR |
12786 | hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; |
12787 | sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; | |
08db6652 DL |
12788 | |
12789 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12790 | continue; | |
12791 | ||
12792 | DRM_ERROR("mismatch in DDB state pipe %c cursor " | |
12793 | "(expected (%u,%u), found (%u,%u))\n", | |
12794 | pipe_name(pipe), | |
12795 | sw_entry->start, sw_entry->end, | |
12796 | hw_entry->start, hw_entry->end); | |
12797 | } | |
12798 | } | |
12799 | ||
91d1b4bd | 12800 | static void |
35dd3c64 ML |
12801 | check_connector_state(struct drm_device *dev, |
12802 | struct drm_atomic_state *old_state) | |
8af6cf88 | 12803 | { |
35dd3c64 ML |
12804 | struct drm_connector_state *old_conn_state; |
12805 | struct drm_connector *connector; | |
12806 | int i; | |
8af6cf88 | 12807 | |
35dd3c64 ML |
12808 | for_each_connector_in_state(old_state, connector, old_conn_state, i) { |
12809 | struct drm_encoder *encoder = connector->encoder; | |
12810 | struct drm_connector_state *state = connector->state; | |
ad3c558f | 12811 | |
8af6cf88 DV |
12812 | /* This also checks the encoder/connector hw state with the |
12813 | * ->get_hw_state callbacks. */ | |
35dd3c64 | 12814 | intel_connector_check_state(to_intel_connector(connector)); |
8af6cf88 | 12815 | |
ad3c558f | 12816 | I915_STATE_WARN(state->best_encoder != encoder, |
35dd3c64 | 12817 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 12818 | } |
91d1b4bd DV |
12819 | } |
12820 | ||
12821 | static void | |
12822 | check_encoder_state(struct drm_device *dev) | |
12823 | { | |
12824 | struct intel_encoder *encoder; | |
12825 | struct intel_connector *connector; | |
8af6cf88 | 12826 | |
b2784e15 | 12827 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 | 12828 | bool enabled = false; |
4d20cd86 | 12829 | enum pipe pipe; |
8af6cf88 DV |
12830 | |
12831 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
12832 | encoder->base.base.id, | |
8e329a03 | 12833 | encoder->base.name); |
8af6cf88 | 12834 | |
3a3371ff | 12835 | for_each_intel_connector(dev, connector) { |
4d20cd86 | 12836 | if (connector->base.state->best_encoder != &encoder->base) |
8af6cf88 DV |
12837 | continue; |
12838 | enabled = true; | |
ad3c558f ML |
12839 | |
12840 | I915_STATE_WARN(connector->base.state->crtc != | |
12841 | encoder->base.crtc, | |
12842 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 12843 | } |
0e32b39c | 12844 | |
e2c719b7 | 12845 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
12846 | "encoder's enabled state mismatch " |
12847 | "(expected %i, found %i)\n", | |
12848 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
12849 | |
12850 | if (!encoder->base.crtc) { | |
4d20cd86 | 12851 | bool active; |
7c60d198 | 12852 | |
4d20cd86 ML |
12853 | active = encoder->get_hw_state(encoder, &pipe); |
12854 | I915_STATE_WARN(active, | |
12855 | "encoder detached but still enabled on pipe %c.\n", | |
12856 | pipe_name(pipe)); | |
7c60d198 | 12857 | } |
8af6cf88 | 12858 | } |
91d1b4bd DV |
12859 | } |
12860 | ||
12861 | static void | |
4d20cd86 | 12862 | check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state) |
91d1b4bd | 12863 | { |
fbee40df | 12864 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd | 12865 | struct intel_encoder *encoder; |
4d20cd86 ML |
12866 | struct drm_crtc_state *old_crtc_state; |
12867 | struct drm_crtc *crtc; | |
12868 | int i; | |
8af6cf88 | 12869 | |
4d20cd86 ML |
12870 | for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) { |
12871 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12872 | struct intel_crtc_state *pipe_config, *sw_config; | |
7b89b8de | 12873 | bool active; |
8af6cf88 | 12874 | |
bfd16b2a ML |
12875 | if (!needs_modeset(crtc->state) && |
12876 | !to_intel_crtc_state(crtc->state)->update_pipe) | |
4d20cd86 | 12877 | continue; |
045ac3b5 | 12878 | |
4d20cd86 ML |
12879 | __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state); |
12880 | pipe_config = to_intel_crtc_state(old_crtc_state); | |
12881 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
12882 | pipe_config->base.crtc = crtc; | |
12883 | pipe_config->base.state = old_state; | |
8af6cf88 | 12884 | |
4d20cd86 ML |
12885 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
12886 | crtc->base.id); | |
8af6cf88 | 12887 | |
4d20cd86 ML |
12888 | active = dev_priv->display.get_pipe_config(intel_crtc, |
12889 | pipe_config); | |
d62cf62a | 12890 | |
b6b5d049 | 12891 | /* hw state is inconsistent with the pipe quirk */ |
4d20cd86 ML |
12892 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
12893 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
12894 | active = crtc->state->active; | |
6c49f241 | 12895 | |
4d20cd86 | 12896 | I915_STATE_WARN(crtc->state->active != active, |
0e8ffe1b | 12897 | "crtc active state doesn't match with hw state " |
4d20cd86 | 12898 | "(expected %i, found %i)\n", crtc->state->active, active); |
0e8ffe1b | 12899 | |
4d20cd86 | 12900 | I915_STATE_WARN(intel_crtc->active != crtc->state->active, |
53d9f4e9 | 12901 | "transitional active state does not match atomic hw state " |
4d20cd86 ML |
12902 | "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active); |
12903 | ||
12904 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
12905 | enum pipe pipe; | |
12906 | ||
12907 | active = encoder->get_hw_state(encoder, &pipe); | |
12908 | I915_STATE_WARN(active != crtc->state->active, | |
12909 | "[ENCODER:%i] active %i with crtc active %i\n", | |
12910 | encoder->base.base.id, active, crtc->state->active); | |
12911 | ||
12912 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, | |
12913 | "Encoder connected to wrong pipe %c\n", | |
12914 | pipe_name(pipe)); | |
12915 | ||
12916 | if (active) | |
12917 | encoder->get_config(encoder, pipe_config); | |
12918 | } | |
53d9f4e9 | 12919 | |
4d20cd86 | 12920 | if (!crtc->state->active) |
cfb23ed6 ML |
12921 | continue; |
12922 | ||
e3b247da VS |
12923 | intel_pipe_config_sanity_check(dev_priv, pipe_config); |
12924 | ||
4d20cd86 ML |
12925 | sw_config = to_intel_crtc_state(crtc->state); |
12926 | if (!intel_pipe_config_compare(dev, sw_config, | |
12927 | pipe_config, false)) { | |
e2c719b7 | 12928 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); |
4d20cd86 | 12929 | intel_dump_pipe_config(intel_crtc, pipe_config, |
c0b03411 | 12930 | "[hw state]"); |
4d20cd86 | 12931 | intel_dump_pipe_config(intel_crtc, sw_config, |
c0b03411 DV |
12932 | "[sw state]"); |
12933 | } | |
8af6cf88 DV |
12934 | } |
12935 | } | |
12936 | ||
91d1b4bd DV |
12937 | static void |
12938 | check_shared_dpll_state(struct drm_device *dev) | |
12939 | { | |
fbee40df | 12940 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
12941 | struct intel_crtc *crtc; |
12942 | struct intel_dpll_hw_state dpll_hw_state; | |
12943 | int i; | |
5358901f DV |
12944 | |
12945 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
8106ddbd ACO |
12946 | struct intel_shared_dpll *pll = |
12947 | intel_get_shared_dpll_by_id(dev_priv, i); | |
2dd66ebd | 12948 | unsigned enabled_crtcs = 0, active_crtcs = 0; |
5358901f DV |
12949 | bool active; |
12950 | ||
12951 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
12952 | ||
12953 | DRM_DEBUG_KMS("%s\n", pll->name); | |
12954 | ||
2edd6443 | 12955 | active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state); |
5358901f | 12956 | |
2dd66ebd ML |
12957 | I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask, |
12958 | "more active pll users than references: %x vs %x\n", | |
12959 | pll->active_mask, pll->config.crtc_mask); | |
9d16da65 ACO |
12960 | |
12961 | if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) { | |
2dd66ebd ML |
12962 | I915_STATE_WARN(!pll->on && pll->active_mask, |
12963 | "pll in active use but not on in sw tracking\n"); | |
12964 | I915_STATE_WARN(pll->on && !pll->active_mask, | |
12965 | "pll is on but not used by any active crtc\n"); | |
9d16da65 ACO |
12966 | I915_STATE_WARN(pll->on != active, |
12967 | "pll on state mismatch (expected %i, found %i)\n", | |
12968 | pll->on, active); | |
12969 | } | |
5358901f | 12970 | |
d3fcc808 | 12971 | for_each_intel_crtc(dev, crtc) { |
8106ddbd | 12972 | if (crtc->base.state->enable && crtc->config->shared_dpll == pll) |
2dd66ebd ML |
12973 | enabled_crtcs |= 1 << drm_crtc_index(&crtc->base); |
12974 | if (crtc->base.state->active && crtc->config->shared_dpll == pll) | |
12975 | active_crtcs |= 1 << drm_crtc_index(&crtc->base); | |
5358901f | 12976 | } |
2dd66ebd ML |
12977 | |
12978 | I915_STATE_WARN(pll->active_mask != active_crtcs, | |
12979 | "pll active crtcs mismatch (expected %x, found %x)\n", | |
12980 | pll->active_mask, active_crtcs); | |
12981 | I915_STATE_WARN(pll->config.crtc_mask != enabled_crtcs, | |
12982 | "pll enabled crtcs mismatch (expected %x, found %x)\n", | |
12983 | pll->config.crtc_mask, enabled_crtcs); | |
66e985c0 | 12984 | |
e2c719b7 | 12985 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state, |
66e985c0 DV |
12986 | sizeof(dpll_hw_state)), |
12987 | "pll hw state mismatch\n"); | |
5358901f | 12988 | } |
8af6cf88 DV |
12989 | } |
12990 | ||
ee165b1a ML |
12991 | static void |
12992 | intel_modeset_check_state(struct drm_device *dev, | |
12993 | struct drm_atomic_state *old_state) | |
91d1b4bd | 12994 | { |
08db6652 | 12995 | check_wm_state(dev); |
35dd3c64 | 12996 | check_connector_state(dev, old_state); |
91d1b4bd | 12997 | check_encoder_state(dev); |
4d20cd86 | 12998 | check_crtc_state(dev, old_state); |
91d1b4bd DV |
12999 | check_shared_dpll_state(dev); |
13000 | } | |
13001 | ||
80715b2f VS |
13002 | static void update_scanline_offset(struct intel_crtc *crtc) |
13003 | { | |
13004 | struct drm_device *dev = crtc->base.dev; | |
13005 | ||
13006 | /* | |
13007 | * The scanline counter increments at the leading edge of hsync. | |
13008 | * | |
13009 | * On most platforms it starts counting from vtotal-1 on the | |
13010 | * first active line. That means the scanline counter value is | |
13011 | * always one less than what we would expect. Ie. just after | |
13012 | * start of vblank, which also occurs at start of hsync (on the | |
13013 | * last active line), the scanline counter will read vblank_start-1. | |
13014 | * | |
13015 | * On gen2 the scanline counter starts counting from 1 instead | |
13016 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
13017 | * to keep the value positive), instead of adding one. | |
13018 | * | |
13019 | * On HSW+ the behaviour of the scanline counter depends on the output | |
13020 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
13021 | * there's an extra 1 line difference. So we need to add two instead of | |
13022 | * one to the value. | |
13023 | */ | |
13024 | if (IS_GEN2(dev)) { | |
124abe07 | 13025 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
13026 | int vtotal; |
13027 | ||
124abe07 VS |
13028 | vtotal = adjusted_mode->crtc_vtotal; |
13029 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
13030 | vtotal /= 2; |
13031 | ||
13032 | crtc->scanline_offset = vtotal - 1; | |
13033 | } else if (HAS_DDI(dev) && | |
409ee761 | 13034 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
13035 | crtc->scanline_offset = 2; |
13036 | } else | |
13037 | crtc->scanline_offset = 1; | |
13038 | } | |
13039 | ||
ad421372 | 13040 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 13041 | { |
225da59b | 13042 | struct drm_device *dev = state->dev; |
ed6739ef | 13043 | struct drm_i915_private *dev_priv = to_i915(dev); |
ad421372 | 13044 | struct intel_shared_dpll_config *shared_dpll = NULL; |
0a9ab303 ACO |
13045 | struct drm_crtc *crtc; |
13046 | struct drm_crtc_state *crtc_state; | |
0a9ab303 | 13047 | int i; |
ed6739ef ACO |
13048 | |
13049 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 13050 | return; |
ed6739ef | 13051 | |
0a9ab303 | 13052 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
fb1a38a9 | 13053 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8106ddbd ACO |
13054 | struct intel_shared_dpll *old_dpll = |
13055 | to_intel_crtc_state(crtc->state)->shared_dpll; | |
0a9ab303 | 13056 | |
fb1a38a9 | 13057 | if (!needs_modeset(crtc_state)) |
225da59b ACO |
13058 | continue; |
13059 | ||
8106ddbd | 13060 | to_intel_crtc_state(crtc_state)->shared_dpll = NULL; |
fb1a38a9 | 13061 | |
8106ddbd | 13062 | if (!old_dpll) |
fb1a38a9 | 13063 | continue; |
0a9ab303 | 13064 | |
ad421372 ML |
13065 | if (!shared_dpll) |
13066 | shared_dpll = intel_atomic_get_shared_dpll_state(state); | |
ed6739ef | 13067 | |
8106ddbd | 13068 | intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc); |
ad421372 | 13069 | } |
ed6739ef ACO |
13070 | } |
13071 | ||
99d736a2 ML |
13072 | /* |
13073 | * This implements the workaround described in the "notes" section of the mode | |
13074 | * set sequence documentation. When going from no pipes or single pipe to | |
13075 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
13076 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
13077 | */ | |
13078 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
13079 | { | |
13080 | struct drm_crtc_state *crtc_state; | |
13081 | struct intel_crtc *intel_crtc; | |
13082 | struct drm_crtc *crtc; | |
13083 | struct intel_crtc_state *first_crtc_state = NULL; | |
13084 | struct intel_crtc_state *other_crtc_state = NULL; | |
13085 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
13086 | int i; | |
13087 | ||
13088 | /* look at all crtc's that are going to be enabled in during modeset */ | |
13089 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13090 | intel_crtc = to_intel_crtc(crtc); | |
13091 | ||
13092 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
13093 | continue; | |
13094 | ||
13095 | if (first_crtc_state) { | |
13096 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
13097 | break; | |
13098 | } else { | |
13099 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
13100 | first_pipe = intel_crtc->pipe; | |
13101 | } | |
13102 | } | |
13103 | ||
13104 | /* No workaround needed? */ | |
13105 | if (!first_crtc_state) | |
13106 | return 0; | |
13107 | ||
13108 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
13109 | for_each_intel_crtc(state->dev, intel_crtc) { | |
13110 | struct intel_crtc_state *pipe_config; | |
13111 | ||
13112 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
13113 | if (IS_ERR(pipe_config)) | |
13114 | return PTR_ERR(pipe_config); | |
13115 | ||
13116 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
13117 | ||
13118 | if (!pipe_config->base.active || | |
13119 | needs_modeset(&pipe_config->base)) | |
13120 | continue; | |
13121 | ||
13122 | /* 2 or more enabled crtcs means no need for w/a */ | |
13123 | if (enabled_pipe != INVALID_PIPE) | |
13124 | return 0; | |
13125 | ||
13126 | enabled_pipe = intel_crtc->pipe; | |
13127 | } | |
13128 | ||
13129 | if (enabled_pipe != INVALID_PIPE) | |
13130 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
13131 | else if (other_crtc_state) | |
13132 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
13133 | ||
13134 | return 0; | |
13135 | } | |
13136 | ||
27c329ed ML |
13137 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
13138 | { | |
13139 | struct drm_crtc *crtc; | |
13140 | struct drm_crtc_state *crtc_state; | |
13141 | int ret = 0; | |
13142 | ||
13143 | /* add all active pipes to the state */ | |
13144 | for_each_crtc(state->dev, crtc) { | |
13145 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13146 | if (IS_ERR(crtc_state)) | |
13147 | return PTR_ERR(crtc_state); | |
13148 | ||
13149 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
13150 | continue; | |
13151 | ||
13152 | crtc_state->mode_changed = true; | |
13153 | ||
13154 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
13155 | if (ret) | |
13156 | break; | |
13157 | ||
13158 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13159 | if (ret) | |
13160 | break; | |
13161 | } | |
13162 | ||
13163 | return ret; | |
13164 | } | |
13165 | ||
c347a676 | 13166 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd | 13167 | { |
565602d7 ML |
13168 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
13169 | struct drm_i915_private *dev_priv = state->dev->dev_private; | |
13170 | struct drm_crtc *crtc; | |
13171 | struct drm_crtc_state *crtc_state; | |
13172 | int ret = 0, i; | |
054518dd | 13173 | |
b359283a ML |
13174 | if (!check_digital_port_conflicts(state)) { |
13175 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
13176 | return -EINVAL; | |
13177 | } | |
13178 | ||
565602d7 ML |
13179 | intel_state->modeset = true; |
13180 | intel_state->active_crtcs = dev_priv->active_crtcs; | |
13181 | ||
13182 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13183 | if (crtc_state->active) | |
13184 | intel_state->active_crtcs |= 1 << i; | |
13185 | else | |
13186 | intel_state->active_crtcs &= ~(1 << i); | |
13187 | } | |
13188 | ||
054518dd ACO |
13189 | /* |
13190 | * See if the config requires any additional preparation, e.g. | |
13191 | * to adjust global state with pipes off. We need to do this | |
13192 | * here so we can get the modeset_pipe updated config for the new | |
13193 | * mode set on this crtc. For other crtcs we need to use the | |
13194 | * adjusted_mode bits in the crtc directly. | |
13195 | */ | |
27c329ed | 13196 | if (dev_priv->display.modeset_calc_cdclk) { |
27c329ed ML |
13197 | ret = dev_priv->display.modeset_calc_cdclk(state); |
13198 | ||
1a617b77 | 13199 | if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq) |
27c329ed ML |
13200 | ret = intel_modeset_all_pipes(state); |
13201 | ||
13202 | if (ret < 0) | |
054518dd | 13203 | return ret; |
e8788cbc ML |
13204 | |
13205 | DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n", | |
13206 | intel_state->cdclk, intel_state->dev_cdclk); | |
27c329ed | 13207 | } else |
1a617b77 | 13208 | to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq; |
054518dd | 13209 | |
ad421372 | 13210 | intel_modeset_clear_plls(state); |
054518dd | 13211 | |
565602d7 | 13212 | if (IS_HASWELL(dev_priv)) |
ad421372 | 13213 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 13214 | |
ad421372 | 13215 | return 0; |
c347a676 ACO |
13216 | } |
13217 | ||
aa363136 MR |
13218 | /* |
13219 | * Handle calculation of various watermark data at the end of the atomic check | |
13220 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
13221 | * handlers to ensure that all derived state has been updated. | |
13222 | */ | |
13223 | static void calc_watermark_data(struct drm_atomic_state *state) | |
13224 | { | |
13225 | struct drm_device *dev = state->dev; | |
13226 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
13227 | struct drm_crtc *crtc; | |
13228 | struct drm_crtc_state *cstate; | |
13229 | struct drm_plane *plane; | |
13230 | struct drm_plane_state *pstate; | |
13231 | ||
13232 | /* | |
13233 | * Calculate watermark configuration details now that derived | |
13234 | * plane/crtc state is all properly updated. | |
13235 | */ | |
13236 | drm_for_each_crtc(crtc, dev) { | |
13237 | cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?: | |
13238 | crtc->state; | |
13239 | ||
13240 | if (cstate->active) | |
13241 | intel_state->wm_config.num_pipes_active++; | |
13242 | } | |
13243 | drm_for_each_legacy_plane(plane, dev) { | |
13244 | pstate = drm_atomic_get_existing_plane_state(state, plane) ?: | |
13245 | plane->state; | |
13246 | ||
13247 | if (!to_intel_plane_state(pstate)->visible) | |
13248 | continue; | |
13249 | ||
13250 | intel_state->wm_config.sprites_enabled = true; | |
13251 | if (pstate->crtc_w != pstate->src_w >> 16 || | |
13252 | pstate->crtc_h != pstate->src_h >> 16) | |
13253 | intel_state->wm_config.sprites_scaled = true; | |
13254 | } | |
13255 | } | |
13256 | ||
74c090b1 ML |
13257 | /** |
13258 | * intel_atomic_check - validate state object | |
13259 | * @dev: drm device | |
13260 | * @state: state to validate | |
13261 | */ | |
13262 | static int intel_atomic_check(struct drm_device *dev, | |
13263 | struct drm_atomic_state *state) | |
c347a676 | 13264 | { |
dd8b3bdb | 13265 | struct drm_i915_private *dev_priv = to_i915(dev); |
aa363136 | 13266 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
c347a676 ACO |
13267 | struct drm_crtc *crtc; |
13268 | struct drm_crtc_state *crtc_state; | |
13269 | int ret, i; | |
61333b60 | 13270 | bool any_ms = false; |
c347a676 | 13271 | |
74c090b1 | 13272 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
13273 | if (ret) |
13274 | return ret; | |
13275 | ||
c347a676 | 13276 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
cfb23ed6 ML |
13277 | struct intel_crtc_state *pipe_config = |
13278 | to_intel_crtc_state(crtc_state); | |
1ed51de9 DV |
13279 | |
13280 | /* Catch I915_MODE_FLAG_INHERITED */ | |
13281 | if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) | |
13282 | crtc_state->mode_changed = true; | |
cfb23ed6 | 13283 | |
61333b60 ML |
13284 | if (!crtc_state->enable) { |
13285 | if (needs_modeset(crtc_state)) | |
13286 | any_ms = true; | |
c347a676 | 13287 | continue; |
61333b60 | 13288 | } |
c347a676 | 13289 | |
26495481 | 13290 | if (!needs_modeset(crtc_state)) |
cfb23ed6 ML |
13291 | continue; |
13292 | ||
26495481 DV |
13293 | /* FIXME: For only active_changed we shouldn't need to do any |
13294 | * state recomputation at all. */ | |
13295 | ||
1ed51de9 DV |
13296 | ret = drm_atomic_add_affected_connectors(state, crtc); |
13297 | if (ret) | |
13298 | return ret; | |
b359283a | 13299 | |
cfb23ed6 | 13300 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
c347a676 ACO |
13301 | if (ret) |
13302 | return ret; | |
13303 | ||
73831236 | 13304 | if (i915.fastboot && |
dd8b3bdb | 13305 | intel_pipe_config_compare(dev, |
cfb23ed6 | 13306 | to_intel_crtc_state(crtc->state), |
1ed51de9 | 13307 | pipe_config, true)) { |
26495481 | 13308 | crtc_state->mode_changed = false; |
bfd16b2a | 13309 | to_intel_crtc_state(crtc_state)->update_pipe = true; |
26495481 DV |
13310 | } |
13311 | ||
13312 | if (needs_modeset(crtc_state)) { | |
13313 | any_ms = true; | |
cfb23ed6 ML |
13314 | |
13315 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13316 | if (ret) | |
13317 | return ret; | |
13318 | } | |
61333b60 | 13319 | |
26495481 DV |
13320 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
13321 | needs_modeset(crtc_state) ? | |
13322 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
13323 | } |
13324 | ||
61333b60 ML |
13325 | if (any_ms) { |
13326 | ret = intel_modeset_checks(state); | |
13327 | ||
13328 | if (ret) | |
13329 | return ret; | |
27c329ed | 13330 | } else |
dd8b3bdb | 13331 | intel_state->cdclk = dev_priv->cdclk_freq; |
76305b1a | 13332 | |
dd8b3bdb | 13333 | ret = drm_atomic_helper_check_planes(dev, state); |
aa363136 MR |
13334 | if (ret) |
13335 | return ret; | |
13336 | ||
f51be2e0 | 13337 | intel_fbc_choose_crtc(dev_priv, state); |
aa363136 MR |
13338 | calc_watermark_data(state); |
13339 | ||
13340 | return 0; | |
054518dd ACO |
13341 | } |
13342 | ||
5008e874 ML |
13343 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
13344 | struct drm_atomic_state *state, | |
13345 | bool async) | |
13346 | { | |
7580d774 ML |
13347 | struct drm_i915_private *dev_priv = dev->dev_private; |
13348 | struct drm_plane_state *plane_state; | |
5008e874 | 13349 | struct drm_crtc_state *crtc_state; |
7580d774 | 13350 | struct drm_plane *plane; |
5008e874 ML |
13351 | struct drm_crtc *crtc; |
13352 | int i, ret; | |
13353 | ||
13354 | if (async) { | |
13355 | DRM_DEBUG_KMS("i915 does not yet support async commit\n"); | |
13356 | return -EINVAL; | |
13357 | } | |
13358 | ||
13359 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13360 | ret = intel_crtc_wait_for_pending_flips(crtc); | |
13361 | if (ret) | |
13362 | return ret; | |
7580d774 ML |
13363 | |
13364 | if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) | |
13365 | flush_workqueue(dev_priv->wq); | |
5008e874 ML |
13366 | } |
13367 | ||
f935675f ML |
13368 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
13369 | if (ret) | |
13370 | return ret; | |
13371 | ||
5008e874 | 13372 | ret = drm_atomic_helper_prepare_planes(dev, state); |
7580d774 ML |
13373 | if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) { |
13374 | u32 reset_counter; | |
13375 | ||
13376 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); | |
13377 | mutex_unlock(&dev->struct_mutex); | |
13378 | ||
13379 | for_each_plane_in_state(state, plane, plane_state, i) { | |
13380 | struct intel_plane_state *intel_plane_state = | |
13381 | to_intel_plane_state(plane_state); | |
13382 | ||
13383 | if (!intel_plane_state->wait_req) | |
13384 | continue; | |
13385 | ||
13386 | ret = __i915_wait_request(intel_plane_state->wait_req, | |
13387 | reset_counter, true, | |
13388 | NULL, NULL); | |
13389 | ||
13390 | /* Swallow -EIO errors to allow updates during hw lockup. */ | |
13391 | if (ret == -EIO) | |
13392 | ret = 0; | |
13393 | ||
13394 | if (ret) | |
13395 | break; | |
13396 | } | |
13397 | ||
13398 | if (!ret) | |
13399 | return 0; | |
13400 | ||
13401 | mutex_lock(&dev->struct_mutex); | |
13402 | drm_atomic_helper_cleanup_planes(dev, state); | |
13403 | } | |
5008e874 | 13404 | |
f935675f | 13405 | mutex_unlock(&dev->struct_mutex); |
5008e874 ML |
13406 | return ret; |
13407 | } | |
13408 | ||
e8861675 ML |
13409 | static void intel_atomic_wait_for_vblanks(struct drm_device *dev, |
13410 | struct drm_i915_private *dev_priv, | |
13411 | unsigned crtc_mask) | |
13412 | { | |
13413 | unsigned last_vblank_count[I915_MAX_PIPES]; | |
13414 | enum pipe pipe; | |
13415 | int ret; | |
13416 | ||
13417 | if (!crtc_mask) | |
13418 | return; | |
13419 | ||
13420 | for_each_pipe(dev_priv, pipe) { | |
13421 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
13422 | ||
13423 | if (!((1 << pipe) & crtc_mask)) | |
13424 | continue; | |
13425 | ||
13426 | ret = drm_crtc_vblank_get(crtc); | |
13427 | if (WARN_ON(ret != 0)) { | |
13428 | crtc_mask &= ~(1 << pipe); | |
13429 | continue; | |
13430 | } | |
13431 | ||
13432 | last_vblank_count[pipe] = drm_crtc_vblank_count(crtc); | |
13433 | } | |
13434 | ||
13435 | for_each_pipe(dev_priv, pipe) { | |
13436 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
13437 | long lret; | |
13438 | ||
13439 | if (!((1 << pipe) & crtc_mask)) | |
13440 | continue; | |
13441 | ||
13442 | lret = wait_event_timeout(dev->vblank[pipe].queue, | |
13443 | last_vblank_count[pipe] != | |
13444 | drm_crtc_vblank_count(crtc), | |
13445 | msecs_to_jiffies(50)); | |
13446 | ||
13447 | WARN_ON(!lret); | |
13448 | ||
13449 | drm_crtc_vblank_put(crtc); | |
13450 | } | |
13451 | } | |
13452 | ||
13453 | static bool needs_vblank_wait(struct intel_crtc_state *crtc_state) | |
13454 | { | |
13455 | /* fb updated, need to unpin old fb */ | |
13456 | if (crtc_state->fb_changed) | |
13457 | return true; | |
13458 | ||
13459 | /* wm changes, need vblank before final wm's */ | |
caed361d | 13460 | if (crtc_state->update_wm_post) |
e8861675 ML |
13461 | return true; |
13462 | ||
13463 | /* | |
13464 | * cxsr is re-enabled after vblank. | |
caed361d | 13465 | * This is already handled by crtc_state->update_wm_post, |
e8861675 ML |
13466 | * but added for clarity. |
13467 | */ | |
13468 | if (crtc_state->disable_cxsr) | |
13469 | return true; | |
13470 | ||
13471 | return false; | |
13472 | } | |
13473 | ||
74c090b1 ML |
13474 | /** |
13475 | * intel_atomic_commit - commit validated state object | |
13476 | * @dev: DRM device | |
13477 | * @state: the top-level driver state object | |
13478 | * @async: asynchronous commit | |
13479 | * | |
13480 | * This function commits a top-level state object that has been validated | |
13481 | * with drm_atomic_helper_check(). | |
13482 | * | |
13483 | * FIXME: Atomic modeset support for i915 is not yet complete. At the moment | |
13484 | * we can only handle plane-related operations and do not yet support | |
13485 | * asynchronous commit. | |
13486 | * | |
13487 | * RETURNS | |
13488 | * Zero for success or -errno. | |
13489 | */ | |
13490 | static int intel_atomic_commit(struct drm_device *dev, | |
13491 | struct drm_atomic_state *state, | |
13492 | bool async) | |
a6778b3c | 13493 | { |
565602d7 | 13494 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fbee40df | 13495 | struct drm_i915_private *dev_priv = dev->dev_private; |
29ceb0e6 | 13496 | struct drm_crtc_state *old_crtc_state; |
7580d774 | 13497 | struct drm_crtc *crtc; |
ed4a6a7c | 13498 | struct intel_crtc_state *intel_cstate; |
565602d7 ML |
13499 | int ret = 0, i; |
13500 | bool hw_check = intel_state->modeset; | |
33c8df89 | 13501 | unsigned long put_domains[I915_MAX_PIPES] = {}; |
e8861675 | 13502 | unsigned crtc_vblank_mask = 0; |
a6778b3c | 13503 | |
5008e874 | 13504 | ret = intel_atomic_prepare_commit(dev, state, async); |
7580d774 ML |
13505 | if (ret) { |
13506 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); | |
d4afb8cc | 13507 | return ret; |
7580d774 | 13508 | } |
d4afb8cc | 13509 | |
1c5e19f8 | 13510 | drm_atomic_helper_swap_state(dev, state); |
a1475e77 ML |
13511 | dev_priv->wm.config = intel_state->wm_config; |
13512 | intel_shared_dpll_commit(state); | |
1c5e19f8 | 13513 | |
565602d7 ML |
13514 | if (intel_state->modeset) { |
13515 | memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, | |
13516 | sizeof(intel_state->min_pixclk)); | |
13517 | dev_priv->active_crtcs = intel_state->active_crtcs; | |
1a617b77 | 13518 | dev_priv->atomic_cdclk_freq = intel_state->cdclk; |
33c8df89 ML |
13519 | |
13520 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); | |
565602d7 ML |
13521 | } |
13522 | ||
29ceb0e6 | 13523 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
a539205a ML |
13524 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13525 | ||
33c8df89 ML |
13526 | if (needs_modeset(crtc->state) || |
13527 | to_intel_crtc_state(crtc->state)->update_pipe) { | |
13528 | hw_check = true; | |
13529 | ||
13530 | put_domains[to_intel_crtc(crtc)->pipe] = | |
13531 | modeset_get_crtc_power_domains(crtc, | |
13532 | to_intel_crtc_state(crtc->state)); | |
13533 | } | |
13534 | ||
61333b60 ML |
13535 | if (!needs_modeset(crtc->state)) |
13536 | continue; | |
13537 | ||
29ceb0e6 | 13538 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); |
460da916 | 13539 | |
29ceb0e6 VS |
13540 | if (old_crtc_state->active) { |
13541 | intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask); | |
a539205a | 13542 | dev_priv->display.crtc_disable(crtc); |
eddfcbcd | 13543 | intel_crtc->active = false; |
58f9c0bc | 13544 | intel_fbc_disable(intel_crtc); |
eddfcbcd | 13545 | intel_disable_shared_dpll(intel_crtc); |
9bbc8258 VS |
13546 | |
13547 | /* | |
13548 | * Underruns don't always raise | |
13549 | * interrupts, so check manually. | |
13550 | */ | |
13551 | intel_check_cpu_fifo_underruns(dev_priv); | |
13552 | intel_check_pch_fifo_underruns(dev_priv); | |
b9001114 ML |
13553 | |
13554 | if (!crtc->state->active) | |
13555 | intel_update_watermarks(crtc); | |
a539205a | 13556 | } |
b8cecdf5 | 13557 | } |
7758a113 | 13558 | |
ea9d758d DV |
13559 | /* Only after disabling all output pipelines that will be changed can we |
13560 | * update the the output configuration. */ | |
4740b0f2 | 13561 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 13562 | |
565602d7 | 13563 | if (intel_state->modeset) { |
4740b0f2 | 13564 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); |
33c8df89 ML |
13565 | |
13566 | if (dev_priv->display.modeset_commit_cdclk && | |
13567 | intel_state->dev_cdclk != dev_priv->cdclk_freq) | |
13568 | dev_priv->display.modeset_commit_cdclk(state); | |
4740b0f2 | 13569 | } |
47fab737 | 13570 | |
a6778b3c | 13571 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
29ceb0e6 | 13572 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
f6ac4b2a ML |
13573 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13574 | bool modeset = needs_modeset(crtc->state); | |
e8861675 ML |
13575 | struct intel_crtc_state *pipe_config = |
13576 | to_intel_crtc_state(crtc->state); | |
13577 | bool update_pipe = !modeset && pipe_config->update_pipe; | |
9f836f90 | 13578 | |
f6ac4b2a | 13579 | if (modeset && crtc->state->active) { |
a539205a ML |
13580 | update_scanline_offset(to_intel_crtc(crtc)); |
13581 | dev_priv->display.crtc_enable(crtc); | |
13582 | } | |
80715b2f | 13583 | |
82cf435b LL |
13584 | if (!modeset && |
13585 | crtc->state->active && | |
13586 | crtc->state->color_mgmt_changed) { | |
13587 | /* | |
13588 | * Only update color management when not doing | |
13589 | * a modeset as this will be done by | |
13590 | * crtc_enable already. | |
13591 | */ | |
13592 | intel_color_set_csc(crtc); | |
13593 | intel_color_load_luts(crtc); | |
13594 | } | |
13595 | ||
f6ac4b2a | 13596 | if (!modeset) |
29ceb0e6 | 13597 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); |
f6ac4b2a | 13598 | |
31ae71fc ML |
13599 | if (crtc->state->active && |
13600 | drm_atomic_get_existing_plane_state(state, crtc->primary)) | |
49227c4a PZ |
13601 | intel_fbc_enable(intel_crtc); |
13602 | ||
6173ee28 ML |
13603 | if (crtc->state->active && |
13604 | (crtc->state->planes_changed || update_pipe)) | |
29ceb0e6 | 13605 | drm_atomic_helper_commit_planes_on_crtc(old_crtc_state); |
bfd16b2a | 13606 | |
e8861675 ML |
13607 | if (pipe_config->base.active && needs_vblank_wait(pipe_config)) |
13608 | crtc_vblank_mask |= 1 << i; | |
80715b2f | 13609 | } |
a6778b3c | 13610 | |
a6778b3c | 13611 | /* FIXME: add subpixel order */ |
83a57153 | 13612 | |
e8861675 ML |
13613 | if (!state->legacy_cursor_update) |
13614 | intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask); | |
f935675f | 13615 | |
ed4a6a7c MR |
13616 | /* |
13617 | * Now that the vblank has passed, we can go ahead and program the | |
13618 | * optimal watermarks on platforms that need two-step watermark | |
13619 | * programming. | |
13620 | * | |
13621 | * TODO: Move this (and other cleanup) to an async worker eventually. | |
13622 | */ | |
29ceb0e6 | 13623 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
ed4a6a7c MR |
13624 | intel_cstate = to_intel_crtc_state(crtc->state); |
13625 | ||
13626 | if (dev_priv->display.optimize_watermarks) | |
13627 | dev_priv->display.optimize_watermarks(intel_cstate); | |
13628 | } | |
13629 | ||
177246a8 MR |
13630 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
13631 | intel_post_plane_update(to_intel_crtc_state(old_crtc_state)); | |
13632 | ||
13633 | if (put_domains[i]) | |
13634 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
13635 | } | |
13636 | ||
13637 | if (intel_state->modeset) | |
13638 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); | |
13639 | ||
f935675f | 13640 | mutex_lock(&dev->struct_mutex); |
d4afb8cc | 13641 | drm_atomic_helper_cleanup_planes(dev, state); |
f935675f | 13642 | mutex_unlock(&dev->struct_mutex); |
2bfb4627 | 13643 | |
565602d7 | 13644 | if (hw_check) |
ee165b1a ML |
13645 | intel_modeset_check_state(dev, state); |
13646 | ||
13647 | drm_atomic_state_free(state); | |
f30da187 | 13648 | |
75714940 MK |
13649 | /* As one of the primary mmio accessors, KMS has a high likelihood |
13650 | * of triggering bugs in unclaimed access. After we finish | |
13651 | * modesetting, see if an error has been flagged, and if so | |
13652 | * enable debugging for the next modeset - and hope we catch | |
13653 | * the culprit. | |
13654 | * | |
13655 | * XXX note that we assume display power is on at this point. | |
13656 | * This might hold true now but we need to add pm helper to check | |
13657 | * unclaimed only when the hardware is on, as atomic commits | |
13658 | * can happen also when the device is completely off. | |
13659 | */ | |
13660 | intel_uncore_arm_unclaimed_mmio_detection(dev_priv); | |
13661 | ||
74c090b1 | 13662 | return 0; |
7f27126e JB |
13663 | } |
13664 | ||
c0c36b94 CW |
13665 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
13666 | { | |
83a57153 ACO |
13667 | struct drm_device *dev = crtc->dev; |
13668 | struct drm_atomic_state *state; | |
e694eb02 | 13669 | struct drm_crtc_state *crtc_state; |
2bfb4627 | 13670 | int ret; |
83a57153 ACO |
13671 | |
13672 | state = drm_atomic_state_alloc(dev); | |
13673 | if (!state) { | |
e694eb02 | 13674 | DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory", |
83a57153 ACO |
13675 | crtc->base.id); |
13676 | return; | |
13677 | } | |
13678 | ||
e694eb02 | 13679 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
83a57153 | 13680 | |
e694eb02 ML |
13681 | retry: |
13682 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13683 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
13684 | if (!ret) { | |
13685 | if (!crtc_state->active) | |
13686 | goto out; | |
83a57153 | 13687 | |
e694eb02 | 13688 | crtc_state->mode_changed = true; |
74c090b1 | 13689 | ret = drm_atomic_commit(state); |
83a57153 ACO |
13690 | } |
13691 | ||
e694eb02 ML |
13692 | if (ret == -EDEADLK) { |
13693 | drm_atomic_state_clear(state); | |
13694 | drm_modeset_backoff(state->acquire_ctx); | |
13695 | goto retry; | |
4ed9fb37 | 13696 | } |
4be07317 | 13697 | |
2bfb4627 | 13698 | if (ret) |
e694eb02 | 13699 | out: |
2bfb4627 | 13700 | drm_atomic_state_free(state); |
c0c36b94 CW |
13701 | } |
13702 | ||
25c5b266 DV |
13703 | #undef for_each_intel_crtc_masked |
13704 | ||
f6e5b160 | 13705 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
82cf435b | 13706 | .gamma_set = drm_atomic_helper_legacy_gamma_set, |
74c090b1 | 13707 | .set_config = drm_atomic_helper_set_config, |
82cf435b | 13708 | .set_property = drm_atomic_helper_crtc_set_property, |
f6e5b160 CW |
13709 | .destroy = intel_crtc_destroy, |
13710 | .page_flip = intel_crtc_page_flip, | |
1356837e MR |
13711 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
13712 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
13713 | }; |
13714 | ||
6beb8c23 MR |
13715 | /** |
13716 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
13717 | * @plane: drm plane to prepare for | |
13718 | * @fb: framebuffer to prepare for presentation | |
13719 | * | |
13720 | * Prepares a framebuffer for usage on a display plane. Generally this | |
13721 | * involves pinning the underlying object and updating the frontbuffer tracking | |
13722 | * bits. Some older platforms need special physical address handling for | |
13723 | * cursor planes. | |
13724 | * | |
f935675f ML |
13725 | * Must be called with struct_mutex held. |
13726 | * | |
6beb8c23 MR |
13727 | * Returns 0 on success, negative error code on failure. |
13728 | */ | |
13729 | int | |
13730 | intel_prepare_plane_fb(struct drm_plane *plane, | |
d136dfee | 13731 | const struct drm_plane_state *new_state) |
465c120c MR |
13732 | { |
13733 | struct drm_device *dev = plane->dev; | |
844f9111 | 13734 | struct drm_framebuffer *fb = new_state->fb; |
6beb8c23 | 13735 | struct intel_plane *intel_plane = to_intel_plane(plane); |
6beb8c23 | 13736 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1ee49399 | 13737 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
6beb8c23 | 13738 | int ret = 0; |
465c120c | 13739 | |
1ee49399 | 13740 | if (!obj && !old_obj) |
465c120c MR |
13741 | return 0; |
13742 | ||
5008e874 ML |
13743 | if (old_obj) { |
13744 | struct drm_crtc_state *crtc_state = | |
13745 | drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc); | |
13746 | ||
13747 | /* Big Hammer, we also need to ensure that any pending | |
13748 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
13749 | * current scanout is retired before unpinning the old | |
13750 | * framebuffer. Note that we rely on userspace rendering | |
13751 | * into the buffer attached to the pipe they are waiting | |
13752 | * on. If not, userspace generates a GPU hang with IPEHR | |
13753 | * point to the MI_WAIT_FOR_EVENT. | |
13754 | * | |
13755 | * This should only fail upon a hung GPU, in which case we | |
13756 | * can safely continue. | |
13757 | */ | |
13758 | if (needs_modeset(crtc_state)) | |
13759 | ret = i915_gem_object_wait_rendering(old_obj, true); | |
13760 | ||
13761 | /* Swallow -EIO errors to allow updates during hw lockup. */ | |
13762 | if (ret && ret != -EIO) | |
f935675f | 13763 | return ret; |
5008e874 ML |
13764 | } |
13765 | ||
3c28ff22 AG |
13766 | /* For framebuffer backed by dmabuf, wait for fence */ |
13767 | if (obj && obj->base.dma_buf) { | |
bcf8be27 ML |
13768 | long lret; |
13769 | ||
13770 | lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv, | |
13771 | false, true, | |
13772 | MAX_SCHEDULE_TIMEOUT); | |
13773 | if (lret == -ERESTARTSYS) | |
13774 | return lret; | |
3c28ff22 | 13775 | |
bcf8be27 | 13776 | WARN(lret < 0, "waiting returns %li\n", lret); |
3c28ff22 AG |
13777 | } |
13778 | ||
1ee49399 ML |
13779 | if (!obj) { |
13780 | ret = 0; | |
13781 | } else if (plane->type == DRM_PLANE_TYPE_CURSOR && | |
6beb8c23 MR |
13782 | INTEL_INFO(dev)->cursor_needs_physical) { |
13783 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
13784 | ret = i915_gem_object_attach_phys(obj, align); | |
13785 | if (ret) | |
13786 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
13787 | } else { | |
3465c580 | 13788 | ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation); |
6beb8c23 | 13789 | } |
465c120c | 13790 | |
7580d774 ML |
13791 | if (ret == 0) { |
13792 | if (obj) { | |
13793 | struct intel_plane_state *plane_state = | |
13794 | to_intel_plane_state(new_state); | |
13795 | ||
13796 | i915_gem_request_assign(&plane_state->wait_req, | |
13797 | obj->last_write_req); | |
13798 | } | |
13799 | ||
a9ff8714 | 13800 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); |
7580d774 | 13801 | } |
fdd508a6 | 13802 | |
6beb8c23 MR |
13803 | return ret; |
13804 | } | |
13805 | ||
38f3ce3a MR |
13806 | /** |
13807 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
13808 | * @plane: drm plane to clean up for | |
13809 | * @fb: old framebuffer that was on plane | |
13810 | * | |
13811 | * Cleans up a framebuffer that has just been removed from a plane. | |
f935675f ML |
13812 | * |
13813 | * Must be called with struct_mutex held. | |
38f3ce3a MR |
13814 | */ |
13815 | void | |
13816 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
d136dfee | 13817 | const struct drm_plane_state *old_state) |
38f3ce3a MR |
13818 | { |
13819 | struct drm_device *dev = plane->dev; | |
1ee49399 | 13820 | struct intel_plane *intel_plane = to_intel_plane(plane); |
7580d774 | 13821 | struct intel_plane_state *old_intel_state; |
1ee49399 ML |
13822 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb); |
13823 | struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb); | |
38f3ce3a | 13824 | |
7580d774 ML |
13825 | old_intel_state = to_intel_plane_state(old_state); |
13826 | ||
1ee49399 | 13827 | if (!obj && !old_obj) |
38f3ce3a MR |
13828 | return; |
13829 | ||
1ee49399 ML |
13830 | if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR || |
13831 | !INTEL_INFO(dev)->cursor_needs_physical)) | |
3465c580 | 13832 | intel_unpin_fb_obj(old_state->fb, old_state->rotation); |
1ee49399 ML |
13833 | |
13834 | /* prepare_fb aborted? */ | |
13835 | if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) || | |
13836 | (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit))) | |
13837 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); | |
7580d774 ML |
13838 | |
13839 | i915_gem_request_assign(&old_intel_state->wait_req, NULL); | |
465c120c MR |
13840 | } |
13841 | ||
6156a456 CK |
13842 | int |
13843 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
13844 | { | |
13845 | int max_scale; | |
13846 | struct drm_device *dev; | |
13847 | struct drm_i915_private *dev_priv; | |
13848 | int crtc_clock, cdclk; | |
13849 | ||
bf8a0af0 | 13850 | if (!intel_crtc || !crtc_state->base.enable) |
6156a456 CK |
13851 | return DRM_PLANE_HELPER_NO_SCALING; |
13852 | ||
13853 | dev = intel_crtc->base.dev; | |
13854 | dev_priv = dev->dev_private; | |
13855 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; | |
27c329ed | 13856 | cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; |
6156a456 | 13857 | |
54bf1ce6 | 13858 | if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)) |
6156a456 CK |
13859 | return DRM_PLANE_HELPER_NO_SCALING; |
13860 | ||
13861 | /* | |
13862 | * skl max scale is lower of: | |
13863 | * close to 3 but not 3, -1 is for that purpose | |
13864 | * or | |
13865 | * cdclk/crtc_clock | |
13866 | */ | |
13867 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); | |
13868 | ||
13869 | return max_scale; | |
13870 | } | |
13871 | ||
465c120c | 13872 | static int |
3c692a41 | 13873 | intel_check_primary_plane(struct drm_plane *plane, |
061e4b8d | 13874 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
13875 | struct intel_plane_state *state) |
13876 | { | |
2b875c22 MR |
13877 | struct drm_crtc *crtc = state->base.crtc; |
13878 | struct drm_framebuffer *fb = state->base.fb; | |
6156a456 | 13879 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
13880 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
13881 | bool can_position = false; | |
465c120c | 13882 | |
693bdc28 VS |
13883 | if (INTEL_INFO(plane->dev)->gen >= 9) { |
13884 | /* use scaler when colorkey is not required */ | |
13885 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { | |
13886 | min_scale = 1; | |
13887 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
13888 | } | |
d8106366 | 13889 | can_position = true; |
6156a456 | 13890 | } |
d8106366 | 13891 | |
061e4b8d ML |
13892 | return drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
13893 | &state->dst, &state->clip, | |
da20eabd ML |
13894 | min_scale, max_scale, |
13895 | can_position, true, | |
13896 | &state->visible); | |
14af293f GP |
13897 | } |
13898 | ||
613d2b27 ML |
13899 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
13900 | struct drm_crtc_state *old_crtc_state) | |
3c692a41 | 13901 | { |
32b7eeec | 13902 | struct drm_device *dev = crtc->dev; |
3c692a41 | 13903 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
bfd16b2a ML |
13904 | struct intel_crtc_state *old_intel_state = |
13905 | to_intel_crtc_state(old_crtc_state); | |
13906 | bool modeset = needs_modeset(crtc->state); | |
3c692a41 | 13907 | |
c34c9ee4 | 13908 | /* Perform vblank evasion around commit operation */ |
62852622 | 13909 | intel_pipe_update_start(intel_crtc); |
0583236e | 13910 | |
bfd16b2a ML |
13911 | if (modeset) |
13912 | return; | |
13913 | ||
13914 | if (to_intel_crtc_state(crtc->state)->update_pipe) | |
13915 | intel_update_pipe_config(intel_crtc, old_intel_state); | |
13916 | else if (INTEL_INFO(dev)->gen >= 9) | |
0583236e | 13917 | skl_detach_scalers(intel_crtc); |
32b7eeec MR |
13918 | } |
13919 | ||
613d2b27 ML |
13920 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, |
13921 | struct drm_crtc_state *old_crtc_state) | |
32b7eeec | 13922 | { |
32b7eeec | 13923 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
32b7eeec | 13924 | |
62852622 | 13925 | intel_pipe_update_end(intel_crtc); |
3c692a41 GP |
13926 | } |
13927 | ||
cf4c7c12 | 13928 | /** |
4a3b8769 MR |
13929 | * intel_plane_destroy - destroy a plane |
13930 | * @plane: plane to destroy | |
cf4c7c12 | 13931 | * |
4a3b8769 MR |
13932 | * Common destruction function for all types of planes (primary, cursor, |
13933 | * sprite). | |
cf4c7c12 | 13934 | */ |
4a3b8769 | 13935 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c MR |
13936 | { |
13937 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
13938 | drm_plane_cleanup(plane); | |
13939 | kfree(intel_plane); | |
13940 | } | |
13941 | ||
65a3fea0 | 13942 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
13943 | .update_plane = drm_atomic_helper_update_plane, |
13944 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 13945 | .destroy = intel_plane_destroy, |
c196e1d6 | 13946 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
13947 | .atomic_get_property = intel_plane_atomic_get_property, |
13948 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
13949 | .atomic_duplicate_state = intel_plane_duplicate_state, |
13950 | .atomic_destroy_state = intel_plane_destroy_state, | |
13951 | ||
465c120c MR |
13952 | }; |
13953 | ||
13954 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
13955 | int pipe) | |
13956 | { | |
13957 | struct intel_plane *primary; | |
8e7d688b | 13958 | struct intel_plane_state *state; |
465c120c | 13959 | const uint32_t *intel_primary_formats; |
45e3743a | 13960 | unsigned int num_formats; |
465c120c MR |
13961 | |
13962 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
13963 | if (primary == NULL) | |
13964 | return NULL; | |
13965 | ||
8e7d688b MR |
13966 | state = intel_create_plane_state(&primary->base); |
13967 | if (!state) { | |
ea2c67bb MR |
13968 | kfree(primary); |
13969 | return NULL; | |
13970 | } | |
8e7d688b | 13971 | primary->base.state = &state->base; |
ea2c67bb | 13972 | |
465c120c MR |
13973 | primary->can_scale = false; |
13974 | primary->max_downscale = 1; | |
6156a456 CK |
13975 | if (INTEL_INFO(dev)->gen >= 9) { |
13976 | primary->can_scale = true; | |
af99ceda | 13977 | state->scaler_id = -1; |
6156a456 | 13978 | } |
465c120c MR |
13979 | primary->pipe = pipe; |
13980 | primary->plane = pipe; | |
a9ff8714 | 13981 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 | 13982 | primary->check_plane = intel_check_primary_plane; |
465c120c MR |
13983 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
13984 | primary->plane = !pipe; | |
13985 | ||
6c0fd451 DL |
13986 | if (INTEL_INFO(dev)->gen >= 9) { |
13987 | intel_primary_formats = skl_primary_formats; | |
13988 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
a8d201af ML |
13989 | |
13990 | primary->update_plane = skylake_update_primary_plane; | |
13991 | primary->disable_plane = skylake_disable_primary_plane; | |
13992 | } else if (HAS_PCH_SPLIT(dev)) { | |
13993 | intel_primary_formats = i965_primary_formats; | |
13994 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
13995 | ||
13996 | primary->update_plane = ironlake_update_primary_plane; | |
13997 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 | 13998 | } else if (INTEL_INFO(dev)->gen >= 4) { |
568db4f2 DL |
13999 | intel_primary_formats = i965_primary_formats; |
14000 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
a8d201af ML |
14001 | |
14002 | primary->update_plane = i9xx_update_primary_plane; | |
14003 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 DL |
14004 | } else { |
14005 | intel_primary_formats = i8xx_primary_formats; | |
14006 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
a8d201af ML |
14007 | |
14008 | primary->update_plane = i9xx_update_primary_plane; | |
14009 | primary->disable_plane = i9xx_disable_primary_plane; | |
465c120c MR |
14010 | } |
14011 | ||
14012 | drm_universal_plane_init(dev, &primary->base, 0, | |
65a3fea0 | 14013 | &intel_plane_funcs, |
465c120c | 14014 | intel_primary_formats, num_formats, |
b0b3b795 | 14015 | DRM_PLANE_TYPE_PRIMARY, NULL); |
48404c1e | 14016 | |
3b7a5119 SJ |
14017 | if (INTEL_INFO(dev)->gen >= 4) |
14018 | intel_create_rotation_property(dev, primary); | |
48404c1e | 14019 | |
ea2c67bb MR |
14020 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
14021 | ||
465c120c MR |
14022 | return &primary->base; |
14023 | } | |
14024 | ||
3b7a5119 SJ |
14025 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
14026 | { | |
14027 | if (!dev->mode_config.rotation_property) { | |
14028 | unsigned long flags = BIT(DRM_ROTATE_0) | | |
14029 | BIT(DRM_ROTATE_180); | |
14030 | ||
14031 | if (INTEL_INFO(dev)->gen >= 9) | |
14032 | flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); | |
14033 | ||
14034 | dev->mode_config.rotation_property = | |
14035 | drm_mode_create_rotation_property(dev, flags); | |
14036 | } | |
14037 | if (dev->mode_config.rotation_property) | |
14038 | drm_object_attach_property(&plane->base.base, | |
14039 | dev->mode_config.rotation_property, | |
14040 | plane->base.state->rotation); | |
14041 | } | |
14042 | ||
3d7d6510 | 14043 | static int |
852e787c | 14044 | intel_check_cursor_plane(struct drm_plane *plane, |
061e4b8d | 14045 | struct intel_crtc_state *crtc_state, |
852e787c | 14046 | struct intel_plane_state *state) |
3d7d6510 | 14047 | { |
061e4b8d | 14048 | struct drm_crtc *crtc = crtc_state->base.crtc; |
2b875c22 | 14049 | struct drm_framebuffer *fb = state->base.fb; |
757f9a3e | 14050 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
b29ec92c | 14051 | enum pipe pipe = to_intel_plane(plane)->pipe; |
757f9a3e GP |
14052 | unsigned stride; |
14053 | int ret; | |
3d7d6510 | 14054 | |
061e4b8d ML |
14055 | ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
14056 | &state->dst, &state->clip, | |
3d7d6510 MR |
14057 | DRM_PLANE_HELPER_NO_SCALING, |
14058 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 14059 | true, true, &state->visible); |
757f9a3e GP |
14060 | if (ret) |
14061 | return ret; | |
14062 | ||
757f9a3e GP |
14063 | /* if we want to turn off the cursor ignore width and height */ |
14064 | if (!obj) | |
da20eabd | 14065 | return 0; |
757f9a3e | 14066 | |
757f9a3e | 14067 | /* Check for which cursor types we support */ |
061e4b8d | 14068 | if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) { |
ea2c67bb MR |
14069 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", |
14070 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
14071 | return -EINVAL; |
14072 | } | |
14073 | ||
ea2c67bb MR |
14074 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
14075 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
14076 | DRM_DEBUG_KMS("buffer is too small\n"); |
14077 | return -ENOMEM; | |
14078 | } | |
14079 | ||
3a656b54 | 14080 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e | 14081 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
da20eabd | 14082 | return -EINVAL; |
32b7eeec MR |
14083 | } |
14084 | ||
b29ec92c VS |
14085 | /* |
14086 | * There's something wrong with the cursor on CHV pipe C. | |
14087 | * If it straddles the left edge of the screen then | |
14088 | * moving it away from the edge or disabling it often | |
14089 | * results in a pipe underrun, and often that can lead to | |
14090 | * dead pipe (constant underrun reported, and it scans | |
14091 | * out just a solid color). To recover from that, the | |
14092 | * display power well must be turned off and on again. | |
14093 | * Refuse the put the cursor into that compromised position. | |
14094 | */ | |
14095 | if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C && | |
14096 | state->visible && state->base.crtc_x < 0) { | |
14097 | DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); | |
14098 | return -EINVAL; | |
14099 | } | |
14100 | ||
da20eabd | 14101 | return 0; |
852e787c | 14102 | } |
3d7d6510 | 14103 | |
a8ad0d8e ML |
14104 | static void |
14105 | intel_disable_cursor_plane(struct drm_plane *plane, | |
7fabf5ef | 14106 | struct drm_crtc *crtc) |
a8ad0d8e | 14107 | { |
f2858021 ML |
14108 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
14109 | ||
14110 | intel_crtc->cursor_addr = 0; | |
55a08b3f | 14111 | intel_crtc_update_cursor(crtc, NULL); |
a8ad0d8e ML |
14112 | } |
14113 | ||
f4a2cf29 | 14114 | static void |
55a08b3f ML |
14115 | intel_update_cursor_plane(struct drm_plane *plane, |
14116 | const struct intel_crtc_state *crtc_state, | |
14117 | const struct intel_plane_state *state) | |
852e787c | 14118 | { |
55a08b3f ML |
14119 | struct drm_crtc *crtc = crtc_state->base.crtc; |
14120 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ea2c67bb | 14121 | struct drm_device *dev = plane->dev; |
2b875c22 | 14122 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 14123 | uint32_t addr; |
852e787c | 14124 | |
f4a2cf29 | 14125 | if (!obj) |
a912f12f | 14126 | addr = 0; |
f4a2cf29 | 14127 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 14128 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 14129 | else |
a912f12f | 14130 | addr = obj->phys_handle->busaddr; |
852e787c | 14131 | |
a912f12f | 14132 | intel_crtc->cursor_addr = addr; |
55a08b3f | 14133 | intel_crtc_update_cursor(crtc, state); |
852e787c GP |
14134 | } |
14135 | ||
3d7d6510 MR |
14136 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
14137 | int pipe) | |
14138 | { | |
14139 | struct intel_plane *cursor; | |
8e7d688b | 14140 | struct intel_plane_state *state; |
3d7d6510 MR |
14141 | |
14142 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
14143 | if (cursor == NULL) | |
14144 | return NULL; | |
14145 | ||
8e7d688b MR |
14146 | state = intel_create_plane_state(&cursor->base); |
14147 | if (!state) { | |
ea2c67bb MR |
14148 | kfree(cursor); |
14149 | return NULL; | |
14150 | } | |
8e7d688b | 14151 | cursor->base.state = &state->base; |
ea2c67bb | 14152 | |
3d7d6510 MR |
14153 | cursor->can_scale = false; |
14154 | cursor->max_downscale = 1; | |
14155 | cursor->pipe = pipe; | |
14156 | cursor->plane = pipe; | |
a9ff8714 | 14157 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
c59cb179 | 14158 | cursor->check_plane = intel_check_cursor_plane; |
55a08b3f | 14159 | cursor->update_plane = intel_update_cursor_plane; |
a8ad0d8e | 14160 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 MR |
14161 | |
14162 | drm_universal_plane_init(dev, &cursor->base, 0, | |
65a3fea0 | 14163 | &intel_plane_funcs, |
3d7d6510 MR |
14164 | intel_cursor_formats, |
14165 | ARRAY_SIZE(intel_cursor_formats), | |
b0b3b795 | 14166 | DRM_PLANE_TYPE_CURSOR, NULL); |
4398ad45 VS |
14167 | |
14168 | if (INTEL_INFO(dev)->gen >= 4) { | |
14169 | if (!dev->mode_config.rotation_property) | |
14170 | dev->mode_config.rotation_property = | |
14171 | drm_mode_create_rotation_property(dev, | |
14172 | BIT(DRM_ROTATE_0) | | |
14173 | BIT(DRM_ROTATE_180)); | |
14174 | if (dev->mode_config.rotation_property) | |
14175 | drm_object_attach_property(&cursor->base.base, | |
14176 | dev->mode_config.rotation_property, | |
8e7d688b | 14177 | state->base.rotation); |
4398ad45 VS |
14178 | } |
14179 | ||
af99ceda CK |
14180 | if (INTEL_INFO(dev)->gen >=9) |
14181 | state->scaler_id = -1; | |
14182 | ||
ea2c67bb MR |
14183 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
14184 | ||
3d7d6510 MR |
14185 | return &cursor->base; |
14186 | } | |
14187 | ||
549e2bfb CK |
14188 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
14189 | struct intel_crtc_state *crtc_state) | |
14190 | { | |
14191 | int i; | |
14192 | struct intel_scaler *intel_scaler; | |
14193 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; | |
14194 | ||
14195 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
14196 | intel_scaler = &scaler_state->scalers[i]; | |
14197 | intel_scaler->in_use = 0; | |
549e2bfb CK |
14198 | intel_scaler->mode = PS_SCALER_MODE_DYN; |
14199 | } | |
14200 | ||
14201 | scaler_state->scaler_id = -1; | |
14202 | } | |
14203 | ||
b358d0a6 | 14204 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 14205 | { |
fbee40df | 14206 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 14207 | struct intel_crtc *intel_crtc; |
f5de6e07 | 14208 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
14209 | struct drm_plane *primary = NULL; |
14210 | struct drm_plane *cursor = NULL; | |
8563b1e8 | 14211 | int ret; |
79e53945 | 14212 | |
955382f3 | 14213 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
14214 | if (intel_crtc == NULL) |
14215 | return; | |
14216 | ||
f5de6e07 ACO |
14217 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
14218 | if (!crtc_state) | |
14219 | goto fail; | |
550acefd ACO |
14220 | intel_crtc->config = crtc_state; |
14221 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 14222 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 14223 | |
549e2bfb CK |
14224 | /* initialize shared scalers */ |
14225 | if (INTEL_INFO(dev)->gen >= 9) { | |
14226 | if (pipe == PIPE_C) | |
14227 | intel_crtc->num_scalers = 1; | |
14228 | else | |
14229 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
14230 | ||
14231 | skl_init_scalers(dev, intel_crtc, crtc_state); | |
14232 | } | |
14233 | ||
465c120c | 14234 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
14235 | if (!primary) |
14236 | goto fail; | |
14237 | ||
14238 | cursor = intel_cursor_plane_create(dev, pipe); | |
14239 | if (!cursor) | |
14240 | goto fail; | |
14241 | ||
465c120c | 14242 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
f9882876 | 14243 | cursor, &intel_crtc_funcs, NULL); |
3d7d6510 MR |
14244 | if (ret) |
14245 | goto fail; | |
79e53945 | 14246 | |
1f1c2e24 VS |
14247 | /* |
14248 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 14249 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 14250 | */ |
80824003 JB |
14251 | intel_crtc->pipe = pipe; |
14252 | intel_crtc->plane = pipe; | |
3a77c4c4 | 14253 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 14254 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 14255 | intel_crtc->plane = !pipe; |
80824003 JB |
14256 | } |
14257 | ||
4b0e333e CW |
14258 | intel_crtc->cursor_base = ~0; |
14259 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 14260 | intel_crtc->cursor_size = ~0; |
8d7849db | 14261 | |
852eb00d VS |
14262 | intel_crtc->wm.cxsr_allowed = true; |
14263 | ||
22fd0fab JB |
14264 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
14265 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
14266 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
14267 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
14268 | ||
79e53945 | 14269 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 | 14270 | |
8563b1e8 LL |
14271 | intel_color_init(&intel_crtc->base); |
14272 | ||
87b6b101 | 14273 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); |
3d7d6510 MR |
14274 | return; |
14275 | ||
14276 | fail: | |
14277 | if (primary) | |
14278 | drm_plane_cleanup(primary); | |
14279 | if (cursor) | |
14280 | drm_plane_cleanup(cursor); | |
f5de6e07 | 14281 | kfree(crtc_state); |
3d7d6510 | 14282 | kfree(intel_crtc); |
79e53945 JB |
14283 | } |
14284 | ||
752aa88a JB |
14285 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
14286 | { | |
14287 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 14288 | struct drm_device *dev = connector->base.dev; |
752aa88a | 14289 | |
51fd371b | 14290 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 14291 | |
d3babd3f | 14292 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
14293 | return INVALID_PIPE; |
14294 | ||
14295 | return to_intel_crtc(encoder->crtc)->pipe; | |
14296 | } | |
14297 | ||
08d7b3d1 | 14298 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 14299 | struct drm_file *file) |
08d7b3d1 | 14300 | { |
08d7b3d1 | 14301 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 14302 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 14303 | struct intel_crtc *crtc; |
08d7b3d1 | 14304 | |
7707e653 | 14305 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 14306 | |
7707e653 | 14307 | if (!drmmode_crtc) { |
08d7b3d1 | 14308 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 14309 | return -ENOENT; |
08d7b3d1 CW |
14310 | } |
14311 | ||
7707e653 | 14312 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 14313 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 14314 | |
c05422d5 | 14315 | return 0; |
08d7b3d1 CW |
14316 | } |
14317 | ||
66a9278e | 14318 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 14319 | { |
66a9278e DV |
14320 | struct drm_device *dev = encoder->base.dev; |
14321 | struct intel_encoder *source_encoder; | |
79e53945 | 14322 | int index_mask = 0; |
79e53945 JB |
14323 | int entry = 0; |
14324 | ||
b2784e15 | 14325 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 14326 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
14327 | index_mask |= (1 << entry); |
14328 | ||
79e53945 JB |
14329 | entry++; |
14330 | } | |
4ef69c7a | 14331 | |
79e53945 JB |
14332 | return index_mask; |
14333 | } | |
14334 | ||
4d302442 CW |
14335 | static bool has_edp_a(struct drm_device *dev) |
14336 | { | |
14337 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14338 | ||
14339 | if (!IS_MOBILE(dev)) | |
14340 | return false; | |
14341 | ||
14342 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
14343 | return false; | |
14344 | ||
e3589908 | 14345 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
14346 | return false; |
14347 | ||
14348 | return true; | |
14349 | } | |
14350 | ||
84b4e042 JB |
14351 | static bool intel_crt_present(struct drm_device *dev) |
14352 | { | |
14353 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14354 | ||
884497ed DL |
14355 | if (INTEL_INFO(dev)->gen >= 9) |
14356 | return false; | |
14357 | ||
cf404ce4 | 14358 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
14359 | return false; |
14360 | ||
14361 | if (IS_CHERRYVIEW(dev)) | |
14362 | return false; | |
14363 | ||
65e472e4 VS |
14364 | if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) |
14365 | return false; | |
14366 | ||
70ac54d0 VS |
14367 | /* DDI E can't be used if DDI A requires 4 lanes */ |
14368 | if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) | |
14369 | return false; | |
14370 | ||
e4abb733 | 14371 | if (!dev_priv->vbt.int_crt_support) |
84b4e042 JB |
14372 | return false; |
14373 | ||
14374 | return true; | |
14375 | } | |
14376 | ||
79e53945 JB |
14377 | static void intel_setup_outputs(struct drm_device *dev) |
14378 | { | |
725e30ad | 14379 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 14380 | struct intel_encoder *encoder; |
cb0953d7 | 14381 | bool dpd_is_edp = false; |
79e53945 | 14382 | |
c9093354 | 14383 | intel_lvds_init(dev); |
79e53945 | 14384 | |
84b4e042 | 14385 | if (intel_crt_present(dev)) |
79935fca | 14386 | intel_crt_init(dev); |
cb0953d7 | 14387 | |
c776eb2e VK |
14388 | if (IS_BROXTON(dev)) { |
14389 | /* | |
14390 | * FIXME: Broxton doesn't support port detection via the | |
14391 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
14392 | * detect the ports. | |
14393 | */ | |
14394 | intel_ddi_init(dev, PORT_A); | |
14395 | intel_ddi_init(dev, PORT_B); | |
14396 | intel_ddi_init(dev, PORT_C); | |
14397 | } else if (HAS_DDI(dev)) { | |
0e72a5b5 ED |
14398 | int found; |
14399 | ||
de31facd JB |
14400 | /* |
14401 | * Haswell uses DDI functions to detect digital outputs. | |
14402 | * On SKL pre-D0 the strap isn't connected, so we assume | |
14403 | * it's there. | |
14404 | */ | |
77179400 | 14405 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 14406 | /* WaIgnoreDDIAStrap: skl */ |
ef11bdb3 | 14407 | if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
0e72a5b5 ED |
14408 | intel_ddi_init(dev, PORT_A); |
14409 | ||
14410 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
14411 | * register */ | |
14412 | found = I915_READ(SFUSE_STRAP); | |
14413 | ||
14414 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
14415 | intel_ddi_init(dev, PORT_B); | |
14416 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
14417 | intel_ddi_init(dev, PORT_C); | |
14418 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
14419 | intel_ddi_init(dev, PORT_D); | |
2800e4c2 RV |
14420 | /* |
14421 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
14422 | */ | |
ef11bdb3 | 14423 | if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && |
2800e4c2 RV |
14424 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
14425 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
14426 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
14427 | intel_ddi_init(dev, PORT_E); | |
14428 | ||
0e72a5b5 | 14429 | } else if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 14430 | int found; |
5d8a7752 | 14431 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
14432 | |
14433 | if (has_edp_a(dev)) | |
14434 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 14435 | |
dc0fa718 | 14436 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 14437 | /* PCH SDVOB multiplex with HDMIB */ |
2a5c0832 | 14438 | found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B); |
30ad48b7 | 14439 | if (!found) |
e2debe91 | 14440 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 14441 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 14442 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
14443 | } |
14444 | ||
dc0fa718 | 14445 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 14446 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 14447 | |
dc0fa718 | 14448 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 14449 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 14450 | |
5eb08b69 | 14451 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 14452 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 14453 | |
270b3042 | 14454 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 14455 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
666a4537 | 14456 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
e17ac6db VS |
14457 | /* |
14458 | * The DP_DETECTED bit is the latched state of the DDC | |
14459 | * SDA pin at boot. However since eDP doesn't require DDC | |
14460 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
14461 | * eDP ports may have been muxed to an alternate function. | |
14462 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
14463 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
14464 | * detect eDP ports. | |
14465 | */ | |
e66eb81d | 14466 | if (I915_READ(VLV_HDMIB) & SDVO_DETECTED && |
d2182a66 | 14467 | !intel_dp_is_edp(dev, PORT_B)) |
e66eb81d VS |
14468 | intel_hdmi_init(dev, VLV_HDMIB, PORT_B); |
14469 | if (I915_READ(VLV_DP_B) & DP_DETECTED || | |
e17ac6db | 14470 | intel_dp_is_edp(dev, PORT_B)) |
e66eb81d | 14471 | intel_dp_init(dev, VLV_DP_B, PORT_B); |
585a94b8 | 14472 | |
e66eb81d | 14473 | if (I915_READ(VLV_HDMIC) & SDVO_DETECTED && |
d2182a66 | 14474 | !intel_dp_is_edp(dev, PORT_C)) |
e66eb81d VS |
14475 | intel_hdmi_init(dev, VLV_HDMIC, PORT_C); |
14476 | if (I915_READ(VLV_DP_C) & DP_DETECTED || | |
e17ac6db | 14477 | intel_dp_is_edp(dev, PORT_C)) |
e66eb81d | 14478 | intel_dp_init(dev, VLV_DP_C, PORT_C); |
19c03924 | 14479 | |
9418c1f1 | 14480 | if (IS_CHERRYVIEW(dev)) { |
e17ac6db | 14481 | /* eDP not supported on port D, so don't check VBT */ |
e66eb81d VS |
14482 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED) |
14483 | intel_hdmi_init(dev, CHV_HDMID, PORT_D); | |
14484 | if (I915_READ(CHV_DP_D) & DP_DETECTED) | |
14485 | intel_dp_init(dev, CHV_DP_D, PORT_D); | |
9418c1f1 VS |
14486 | } |
14487 | ||
3cfca973 | 14488 | intel_dsi_init(dev); |
09da55dc | 14489 | } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) { |
27185ae1 | 14490 | bool found = false; |
7d57382e | 14491 | |
e2debe91 | 14492 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14493 | DRM_DEBUG_KMS("probing SDVOB\n"); |
2a5c0832 | 14494 | found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B); |
3fec3d2f | 14495 | if (!found && IS_G4X(dev)) { |
b01f2c3a | 14496 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
e2debe91 | 14497 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 14498 | } |
27185ae1 | 14499 | |
3fec3d2f | 14500 | if (!found && IS_G4X(dev)) |
ab9d7c30 | 14501 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 14502 | } |
13520b05 KH |
14503 | |
14504 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 14505 | |
e2debe91 | 14506 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14507 | DRM_DEBUG_KMS("probing SDVOC\n"); |
2a5c0832 | 14508 | found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C); |
b01f2c3a | 14509 | } |
27185ae1 | 14510 | |
e2debe91 | 14511 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 14512 | |
3fec3d2f | 14513 | if (IS_G4X(dev)) { |
b01f2c3a | 14514 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
e2debe91 | 14515 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 14516 | } |
3fec3d2f | 14517 | if (IS_G4X(dev)) |
ab9d7c30 | 14518 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 14519 | } |
27185ae1 | 14520 | |
3fec3d2f | 14521 | if (IS_G4X(dev) && |
e7281eab | 14522 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 14523 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 14524 | } else if (IS_GEN2(dev)) |
79e53945 JB |
14525 | intel_dvo_init(dev); |
14526 | ||
103a196f | 14527 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
14528 | intel_tv_init(dev); |
14529 | ||
0bc12bcb | 14530 | intel_psr_init(dev); |
7c8f8a70 | 14531 | |
b2784e15 | 14532 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
14533 | encoder->base.possible_crtcs = encoder->crtc_mask; |
14534 | encoder->base.possible_clones = | |
66a9278e | 14535 | intel_encoder_clones(encoder); |
79e53945 | 14536 | } |
47356eb6 | 14537 | |
dde86e2d | 14538 | intel_init_pch_refclk(dev); |
270b3042 DV |
14539 | |
14540 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
14541 | } |
14542 | ||
14543 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
14544 | { | |
60a5ca01 | 14545 | struct drm_device *dev = fb->dev; |
79e53945 | 14546 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 14547 | |
ef2d633e | 14548 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 14549 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 14550 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
14551 | drm_gem_object_unreference(&intel_fb->obj->base); |
14552 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
14553 | kfree(intel_fb); |
14554 | } | |
14555 | ||
14556 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 14557 | struct drm_file *file, |
79e53945 JB |
14558 | unsigned int *handle) |
14559 | { | |
14560 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 14561 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 14562 | |
cc917ab4 CW |
14563 | if (obj->userptr.mm) { |
14564 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); | |
14565 | return -EINVAL; | |
14566 | } | |
14567 | ||
05394f39 | 14568 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
14569 | } |
14570 | ||
86c98588 RV |
14571 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
14572 | struct drm_file *file, | |
14573 | unsigned flags, unsigned color, | |
14574 | struct drm_clip_rect *clips, | |
14575 | unsigned num_clips) | |
14576 | { | |
14577 | struct drm_device *dev = fb->dev; | |
14578 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
14579 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
14580 | ||
14581 | mutex_lock(&dev->struct_mutex); | |
74b4ea1e | 14582 | intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); |
86c98588 RV |
14583 | mutex_unlock(&dev->struct_mutex); |
14584 | ||
14585 | return 0; | |
14586 | } | |
14587 | ||
79e53945 JB |
14588 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
14589 | .destroy = intel_user_framebuffer_destroy, | |
14590 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 14591 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
14592 | }; |
14593 | ||
b321803d DL |
14594 | static |
14595 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
14596 | uint32_t pixel_format) | |
14597 | { | |
14598 | u32 gen = INTEL_INFO(dev)->gen; | |
14599 | ||
14600 | if (gen >= 9) { | |
ac484963 VS |
14601 | int cpp = drm_format_plane_cpp(pixel_format, 0); |
14602 | ||
b321803d DL |
14603 | /* "The stride in bytes must not exceed the of the size of 8K |
14604 | * pixels and 32K bytes." | |
14605 | */ | |
ac484963 | 14606 | return min(8192 * cpp, 32768); |
666a4537 | 14607 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
b321803d DL |
14608 | return 32*1024; |
14609 | } else if (gen >= 4) { | |
14610 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14611 | return 16*1024; | |
14612 | else | |
14613 | return 32*1024; | |
14614 | } else if (gen >= 3) { | |
14615 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14616 | return 8*1024; | |
14617 | else | |
14618 | return 16*1024; | |
14619 | } else { | |
14620 | /* XXX DSPC is limited to 4k tiled */ | |
14621 | return 8*1024; | |
14622 | } | |
14623 | } | |
14624 | ||
b5ea642a DV |
14625 | static int intel_framebuffer_init(struct drm_device *dev, |
14626 | struct intel_framebuffer *intel_fb, | |
14627 | struct drm_mode_fb_cmd2 *mode_cmd, | |
14628 | struct drm_i915_gem_object *obj) | |
79e53945 | 14629 | { |
7b49f948 | 14630 | struct drm_i915_private *dev_priv = to_i915(dev); |
6761dd31 | 14631 | unsigned int aligned_height; |
79e53945 | 14632 | int ret; |
b321803d | 14633 | u32 pitch_limit, stride_alignment; |
79e53945 | 14634 | |
dd4916c5 DV |
14635 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
14636 | ||
2a80eada DV |
14637 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
14638 | /* Enforce that fb modifier and tiling mode match, but only for | |
14639 | * X-tiled. This is needed for FBC. */ | |
14640 | if (!!(obj->tiling_mode == I915_TILING_X) != | |
14641 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { | |
14642 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
14643 | return -EINVAL; | |
14644 | } | |
14645 | } else { | |
14646 | if (obj->tiling_mode == I915_TILING_X) | |
14647 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
14648 | else if (obj->tiling_mode == I915_TILING_Y) { | |
14649 | DRM_DEBUG("No Y tiling for legacy addfb\n"); | |
14650 | return -EINVAL; | |
14651 | } | |
14652 | } | |
14653 | ||
9a8f0a12 TU |
14654 | /* Passed in modifier sanity checking. */ |
14655 | switch (mode_cmd->modifier[0]) { | |
14656 | case I915_FORMAT_MOD_Y_TILED: | |
14657 | case I915_FORMAT_MOD_Yf_TILED: | |
14658 | if (INTEL_INFO(dev)->gen < 9) { | |
14659 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
14660 | mode_cmd->modifier[0]); | |
14661 | return -EINVAL; | |
14662 | } | |
14663 | case DRM_FORMAT_MOD_NONE: | |
14664 | case I915_FORMAT_MOD_X_TILED: | |
14665 | break; | |
14666 | default: | |
c0f40428 JB |
14667 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
14668 | mode_cmd->modifier[0]); | |
57cd6508 | 14669 | return -EINVAL; |
c16ed4be | 14670 | } |
57cd6508 | 14671 | |
7b49f948 VS |
14672 | stride_alignment = intel_fb_stride_alignment(dev_priv, |
14673 | mode_cmd->modifier[0], | |
b321803d DL |
14674 | mode_cmd->pixel_format); |
14675 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
14676 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
14677 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 14678 | return -EINVAL; |
c16ed4be | 14679 | } |
57cd6508 | 14680 | |
b321803d DL |
14681 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
14682 | mode_cmd->pixel_format); | |
a35cdaa0 | 14683 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
14684 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
14685 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 14686 | "tiled" : "linear", |
a35cdaa0 | 14687 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 14688 | return -EINVAL; |
c16ed4be | 14689 | } |
5d7bd705 | 14690 | |
2a80eada | 14691 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
c16ed4be CW |
14692 | mode_cmd->pitches[0] != obj->stride) { |
14693 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
14694 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 14695 | return -EINVAL; |
c16ed4be | 14696 | } |
5d7bd705 | 14697 | |
57779d06 | 14698 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 14699 | switch (mode_cmd->pixel_format) { |
57779d06 | 14700 | case DRM_FORMAT_C8: |
04b3924d VS |
14701 | case DRM_FORMAT_RGB565: |
14702 | case DRM_FORMAT_XRGB8888: | |
14703 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
14704 | break; |
14705 | case DRM_FORMAT_XRGB1555: | |
c16ed4be | 14706 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
14707 | DRM_DEBUG("unsupported pixel format: %s\n", |
14708 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14709 | return -EINVAL; |
c16ed4be | 14710 | } |
57779d06 | 14711 | break; |
57779d06 | 14712 | case DRM_FORMAT_ABGR8888: |
666a4537 WB |
14713 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
14714 | INTEL_INFO(dev)->gen < 9) { | |
6c0fd451 DL |
14715 | DRM_DEBUG("unsupported pixel format: %s\n", |
14716 | drm_get_format_name(mode_cmd->pixel_format)); | |
14717 | return -EINVAL; | |
14718 | } | |
14719 | break; | |
14720 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 14721 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 14722 | case DRM_FORMAT_XBGR2101010: |
c16ed4be | 14723 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
14724 | DRM_DEBUG("unsupported pixel format: %s\n", |
14725 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14726 | return -EINVAL; |
c16ed4be | 14727 | } |
b5626747 | 14728 | break; |
7531208b | 14729 | case DRM_FORMAT_ABGR2101010: |
666a4537 | 14730 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
7531208b DL |
14731 | DRM_DEBUG("unsupported pixel format: %s\n", |
14732 | drm_get_format_name(mode_cmd->pixel_format)); | |
14733 | return -EINVAL; | |
14734 | } | |
14735 | break; | |
04b3924d VS |
14736 | case DRM_FORMAT_YUYV: |
14737 | case DRM_FORMAT_UYVY: | |
14738 | case DRM_FORMAT_YVYU: | |
14739 | case DRM_FORMAT_VYUY: | |
c16ed4be | 14740 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
14741 | DRM_DEBUG("unsupported pixel format: %s\n", |
14742 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14743 | return -EINVAL; |
c16ed4be | 14744 | } |
57cd6508 CW |
14745 | break; |
14746 | default: | |
4ee62c76 VS |
14747 | DRM_DEBUG("unsupported pixel format: %s\n", |
14748 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
14749 | return -EINVAL; |
14750 | } | |
14751 | ||
90f9a336 VS |
14752 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
14753 | if (mode_cmd->offsets[0] != 0) | |
14754 | return -EINVAL; | |
14755 | ||
ec2c981e | 14756 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
091df6cb DV |
14757 | mode_cmd->pixel_format, |
14758 | mode_cmd->modifier[0]); | |
53155c0a DV |
14759 | /* FIXME drm helper for size checks (especially planar formats)? */ |
14760 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
14761 | return -EINVAL; | |
14762 | ||
c7d73f6a DV |
14763 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
14764 | intel_fb->obj = obj; | |
14765 | ||
2d7a215f VS |
14766 | intel_fill_fb_info(dev_priv, &intel_fb->base); |
14767 | ||
79e53945 JB |
14768 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
14769 | if (ret) { | |
14770 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
14771 | return ret; | |
14772 | } | |
14773 | ||
0b05e1e0 VS |
14774 | intel_fb->obj->framebuffer_references++; |
14775 | ||
79e53945 JB |
14776 | return 0; |
14777 | } | |
14778 | ||
79e53945 JB |
14779 | static struct drm_framebuffer * |
14780 | intel_user_framebuffer_create(struct drm_device *dev, | |
14781 | struct drm_file *filp, | |
1eb83451 | 14782 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
79e53945 | 14783 | { |
dcb1394e | 14784 | struct drm_framebuffer *fb; |
05394f39 | 14785 | struct drm_i915_gem_object *obj; |
76dc3769 | 14786 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
79e53945 | 14787 | |
308e5bcb | 14788 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
76dc3769 | 14789 | mode_cmd.handles[0])); |
c8725226 | 14790 | if (&obj->base == NULL) |
cce13ff7 | 14791 | return ERR_PTR(-ENOENT); |
79e53945 | 14792 | |
92907cbb | 14793 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
dcb1394e LW |
14794 | if (IS_ERR(fb)) |
14795 | drm_gem_object_unreference_unlocked(&obj->base); | |
14796 | ||
14797 | return fb; | |
79e53945 JB |
14798 | } |
14799 | ||
0695726e | 14800 | #ifndef CONFIG_DRM_FBDEV_EMULATION |
0632fef6 | 14801 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
14802 | { |
14803 | } | |
14804 | #endif | |
14805 | ||
79e53945 | 14806 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 14807 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 14808 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
14809 | .atomic_check = intel_atomic_check, |
14810 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
14811 | .atomic_state_alloc = intel_atomic_state_alloc, |
14812 | .atomic_state_clear = intel_atomic_state_clear, | |
79e53945 JB |
14813 | }; |
14814 | ||
88212941 ID |
14815 | /** |
14816 | * intel_init_display_hooks - initialize the display modesetting hooks | |
14817 | * @dev_priv: device private | |
14818 | */ | |
14819 | void intel_init_display_hooks(struct drm_i915_private *dev_priv) | |
e70236a8 | 14820 | { |
88212941 | 14821 | if (HAS_PCH_SPLIT(dev_priv) || IS_G4X(dev_priv)) |
ee9300bb | 14822 | dev_priv->display.find_dpll = g4x_find_best_dpll; |
88212941 | 14823 | else if (IS_CHERRYVIEW(dev_priv)) |
ef9348c8 | 14824 | dev_priv->display.find_dpll = chv_find_best_dpll; |
88212941 | 14825 | else if (IS_VALLEYVIEW(dev_priv)) |
ee9300bb | 14826 | dev_priv->display.find_dpll = vlv_find_best_dpll; |
88212941 | 14827 | else if (IS_PINEVIEW(dev_priv)) |
ee9300bb DV |
14828 | dev_priv->display.find_dpll = pnv_find_best_dpll; |
14829 | else | |
14830 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
14831 | ||
88212941 | 14832 | if (INTEL_INFO(dev_priv)->gen >= 9) { |
bc8d7dff | 14833 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14834 | dev_priv->display.get_initial_plane_config = |
14835 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
14836 | dev_priv->display.crtc_compute_clock = |
14837 | haswell_crtc_compute_clock; | |
14838 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
14839 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 14840 | } else if (HAS_DDI(dev_priv)) { |
0e8ffe1b | 14841 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14842 | dev_priv->display.get_initial_plane_config = |
14843 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
14844 | dev_priv->display.crtc_compute_clock = |
14845 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
14846 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
14847 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 14848 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
0e8ffe1b | 14849 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
14850 | dev_priv->display.get_initial_plane_config = |
14851 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
14852 | dev_priv->display.crtc_compute_clock = |
14853 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
14854 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
14855 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
88212941 | 14856 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
89b667f8 | 14857 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14858 | dev_priv->display.get_initial_plane_config = |
14859 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14860 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
89b667f8 JB |
14861 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
14862 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 14863 | } else { |
0e8ffe1b | 14864 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14865 | dev_priv->display.get_initial_plane_config = |
14866 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14867 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
14868 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
14869 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 14870 | } |
e70236a8 | 14871 | |
e70236a8 | 14872 | /* Returns the core display clock speed */ |
88212941 | 14873 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
1652d19e VS |
14874 | dev_priv->display.get_display_clock_speed = |
14875 | skylake_get_display_clock_speed; | |
88212941 | 14876 | else if (IS_BROXTON(dev_priv)) |
acd3f3d3 BP |
14877 | dev_priv->display.get_display_clock_speed = |
14878 | broxton_get_display_clock_speed; | |
88212941 | 14879 | else if (IS_BROADWELL(dev_priv)) |
1652d19e VS |
14880 | dev_priv->display.get_display_clock_speed = |
14881 | broadwell_get_display_clock_speed; | |
88212941 | 14882 | else if (IS_HASWELL(dev_priv)) |
1652d19e VS |
14883 | dev_priv->display.get_display_clock_speed = |
14884 | haswell_get_display_clock_speed; | |
88212941 | 14885 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
25eb05fc JB |
14886 | dev_priv->display.get_display_clock_speed = |
14887 | valleyview_get_display_clock_speed; | |
88212941 | 14888 | else if (IS_GEN5(dev_priv)) |
b37a6434 VS |
14889 | dev_priv->display.get_display_clock_speed = |
14890 | ilk_get_display_clock_speed; | |
88212941 ID |
14891 | else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) || |
14892 | IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) | |
e70236a8 JB |
14893 | dev_priv->display.get_display_clock_speed = |
14894 | i945_get_display_clock_speed; | |
88212941 | 14895 | else if (IS_GM45(dev_priv)) |
34edce2f VS |
14896 | dev_priv->display.get_display_clock_speed = |
14897 | gm45_get_display_clock_speed; | |
88212941 | 14898 | else if (IS_CRESTLINE(dev_priv)) |
34edce2f VS |
14899 | dev_priv->display.get_display_clock_speed = |
14900 | i965gm_get_display_clock_speed; | |
88212941 | 14901 | else if (IS_PINEVIEW(dev_priv)) |
34edce2f VS |
14902 | dev_priv->display.get_display_clock_speed = |
14903 | pnv_get_display_clock_speed; | |
88212941 | 14904 | else if (IS_G33(dev_priv) || IS_G4X(dev_priv)) |
34edce2f VS |
14905 | dev_priv->display.get_display_clock_speed = |
14906 | g33_get_display_clock_speed; | |
88212941 | 14907 | else if (IS_I915G(dev_priv)) |
e70236a8 JB |
14908 | dev_priv->display.get_display_clock_speed = |
14909 | i915_get_display_clock_speed; | |
88212941 | 14910 | else if (IS_I945GM(dev_priv) || IS_845G(dev_priv)) |
e70236a8 JB |
14911 | dev_priv->display.get_display_clock_speed = |
14912 | i9xx_misc_get_display_clock_speed; | |
88212941 | 14913 | else if (IS_I915GM(dev_priv)) |
e70236a8 JB |
14914 | dev_priv->display.get_display_clock_speed = |
14915 | i915gm_get_display_clock_speed; | |
88212941 | 14916 | else if (IS_I865G(dev_priv)) |
e70236a8 JB |
14917 | dev_priv->display.get_display_clock_speed = |
14918 | i865_get_display_clock_speed; | |
88212941 | 14919 | else if (IS_I85X(dev_priv)) |
e70236a8 | 14920 | dev_priv->display.get_display_clock_speed = |
1b1d2716 | 14921 | i85x_get_display_clock_speed; |
623e01e5 | 14922 | else { /* 830 */ |
88212941 | 14923 | WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n"); |
e70236a8 JB |
14924 | dev_priv->display.get_display_clock_speed = |
14925 | i830_get_display_clock_speed; | |
623e01e5 | 14926 | } |
e70236a8 | 14927 | |
88212941 | 14928 | if (IS_GEN5(dev_priv)) { |
3bb11b53 | 14929 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
88212941 | 14930 | } else if (IS_GEN6(dev_priv)) { |
3bb11b53 | 14931 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
88212941 | 14932 | } else if (IS_IVYBRIDGE(dev_priv)) { |
3bb11b53 SJ |
14933 | /* FIXME: detect B0+ stepping and use auto training */ |
14934 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
88212941 | 14935 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
3bb11b53 | 14936 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
88212941 | 14937 | if (IS_BROADWELL(dev_priv)) { |
27c329ed ML |
14938 | dev_priv->display.modeset_commit_cdclk = |
14939 | broadwell_modeset_commit_cdclk; | |
14940 | dev_priv->display.modeset_calc_cdclk = | |
14941 | broadwell_modeset_calc_cdclk; | |
14942 | } | |
88212941 | 14943 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
27c329ed ML |
14944 | dev_priv->display.modeset_commit_cdclk = |
14945 | valleyview_modeset_commit_cdclk; | |
14946 | dev_priv->display.modeset_calc_cdclk = | |
14947 | valleyview_modeset_calc_cdclk; | |
88212941 | 14948 | } else if (IS_BROXTON(dev_priv)) { |
27c329ed ML |
14949 | dev_priv->display.modeset_commit_cdclk = |
14950 | broxton_modeset_commit_cdclk; | |
14951 | dev_priv->display.modeset_calc_cdclk = | |
14952 | broxton_modeset_calc_cdclk; | |
e70236a8 | 14953 | } |
8c9f3aaf | 14954 | |
88212941 | 14955 | switch (INTEL_INFO(dev_priv)->gen) { |
8c9f3aaf JB |
14956 | case 2: |
14957 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
14958 | break; | |
14959 | ||
14960 | case 3: | |
14961 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
14962 | break; | |
14963 | ||
14964 | case 4: | |
14965 | case 5: | |
14966 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
14967 | break; | |
14968 | ||
14969 | case 6: | |
14970 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
14971 | break; | |
7c9017e5 | 14972 | case 7: |
4e0bbc31 | 14973 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
14974 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
14975 | break; | |
830c81db | 14976 | case 9: |
ba343e02 TU |
14977 | /* Drop through - unsupported since execlist only. */ |
14978 | default: | |
14979 | /* Default just returns -ENODEV to indicate unsupported */ | |
14980 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8c9f3aaf | 14981 | } |
e70236a8 JB |
14982 | } |
14983 | ||
b690e96c JB |
14984 | /* |
14985 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
14986 | * resume, or other times. This quirk makes sure that's the case for | |
14987 | * affected systems. | |
14988 | */ | |
0206e353 | 14989 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
14990 | { |
14991 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14992 | ||
14993 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 14994 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
14995 | } |
14996 | ||
b6b5d049 VS |
14997 | static void quirk_pipeb_force(struct drm_device *dev) |
14998 | { | |
14999 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15000 | ||
15001 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
15002 | DRM_INFO("applying pipe b force quirk\n"); | |
15003 | } | |
15004 | ||
435793df KP |
15005 | /* |
15006 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
15007 | */ | |
15008 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
15009 | { | |
15010 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15011 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 15012 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
15013 | } |
15014 | ||
4dca20ef | 15015 | /* |
5a15ab5b CE |
15016 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
15017 | * brightness value | |
4dca20ef CE |
15018 | */ |
15019 | static void quirk_invert_brightness(struct drm_device *dev) | |
15020 | { | |
15021 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15022 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 15023 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
15024 | } |
15025 | ||
9c72cc6f SD |
15026 | /* Some VBT's incorrectly indicate no backlight is present */ |
15027 | static void quirk_backlight_present(struct drm_device *dev) | |
15028 | { | |
15029 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15030 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
15031 | DRM_INFO("applying backlight present quirk\n"); | |
15032 | } | |
15033 | ||
b690e96c JB |
15034 | struct intel_quirk { |
15035 | int device; | |
15036 | int subsystem_vendor; | |
15037 | int subsystem_device; | |
15038 | void (*hook)(struct drm_device *dev); | |
15039 | }; | |
15040 | ||
5f85f176 EE |
15041 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
15042 | struct intel_dmi_quirk { | |
15043 | void (*hook)(struct drm_device *dev); | |
15044 | const struct dmi_system_id (*dmi_id_list)[]; | |
15045 | }; | |
15046 | ||
15047 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
15048 | { | |
15049 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
15050 | return 1; | |
15051 | } | |
15052 | ||
15053 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
15054 | { | |
15055 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
15056 | { | |
15057 | .callback = intel_dmi_reverse_brightness, | |
15058 | .ident = "NCR Corporation", | |
15059 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
15060 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
15061 | }, | |
15062 | }, | |
15063 | { } /* terminating entry */ | |
15064 | }, | |
15065 | .hook = quirk_invert_brightness, | |
15066 | }, | |
15067 | }; | |
15068 | ||
c43b5634 | 15069 | static struct intel_quirk intel_quirks[] = { |
b690e96c JB |
15070 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
15071 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
15072 | ||
b690e96c JB |
15073 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
15074 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
15075 | ||
5f080c0f VS |
15076 | /* 830 needs to leave pipe A & dpll A up */ |
15077 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
15078 | ||
b6b5d049 VS |
15079 | /* 830 needs to leave pipe B & dpll B up */ |
15080 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
15081 | ||
435793df KP |
15082 | /* Lenovo U160 cannot use SSC on LVDS */ |
15083 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
15084 | |
15085 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
15086 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 15087 | |
be505f64 AH |
15088 | /* Acer Aspire 5734Z must invert backlight brightness */ |
15089 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
15090 | ||
15091 | /* Acer/eMachines G725 */ | |
15092 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
15093 | ||
15094 | /* Acer/eMachines e725 */ | |
15095 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
15096 | ||
15097 | /* Acer/Packard Bell NCL20 */ | |
15098 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
15099 | ||
15100 | /* Acer Aspire 4736Z */ | |
15101 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
15102 | |
15103 | /* Acer Aspire 5336 */ | |
15104 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
15105 | |
15106 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
15107 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 15108 | |
dfb3d47b SD |
15109 | /* Acer C720 Chromebook (Core i3 4005U) */ |
15110 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
15111 | ||
b2a9601c | 15112 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
15113 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
15114 | ||
1b9448b0 JN |
15115 | /* Apple Macbook 4,1 */ |
15116 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, | |
15117 | ||
d4967d8c SD |
15118 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
15119 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
15120 | |
15121 | /* HP Chromebook 14 (Celeron 2955U) */ | |
15122 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
15123 | |
15124 | /* Dell Chromebook 11 */ | |
15125 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
9be64eee JN |
15126 | |
15127 | /* Dell Chromebook 11 (2015 version) */ | |
15128 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
15129 | }; |
15130 | ||
15131 | static void intel_init_quirks(struct drm_device *dev) | |
15132 | { | |
15133 | struct pci_dev *d = dev->pdev; | |
15134 | int i; | |
15135 | ||
15136 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
15137 | struct intel_quirk *q = &intel_quirks[i]; | |
15138 | ||
15139 | if (d->device == q->device && | |
15140 | (d->subsystem_vendor == q->subsystem_vendor || | |
15141 | q->subsystem_vendor == PCI_ANY_ID) && | |
15142 | (d->subsystem_device == q->subsystem_device || | |
15143 | q->subsystem_device == PCI_ANY_ID)) | |
15144 | q->hook(dev); | |
15145 | } | |
5f85f176 EE |
15146 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
15147 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
15148 | intel_dmi_quirks[i].hook(dev); | |
15149 | } | |
b690e96c JB |
15150 | } |
15151 | ||
9cce37f4 JB |
15152 | /* Disable the VGA plane that we never use */ |
15153 | static void i915_disable_vga(struct drm_device *dev) | |
15154 | { | |
15155 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15156 | u8 sr1; | |
f0f59a00 | 15157 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 15158 | |
2b37c616 | 15159 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 15160 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 15161 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
15162 | sr1 = inb(VGA_SR_DATA); |
15163 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
15164 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
15165 | udelay(300); | |
15166 | ||
01f5a626 | 15167 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
15168 | POSTING_READ(vga_reg); |
15169 | } | |
15170 | ||
f817586c DV |
15171 | void intel_modeset_init_hw(struct drm_device *dev) |
15172 | { | |
1a617b77 ML |
15173 | struct drm_i915_private *dev_priv = dev->dev_private; |
15174 | ||
b6283055 | 15175 | intel_update_cdclk(dev); |
1a617b77 ML |
15176 | |
15177 | dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq; | |
15178 | ||
f817586c | 15179 | intel_init_clock_gating(dev); |
8090c6b9 | 15180 | intel_enable_gt_powersave(dev); |
f817586c DV |
15181 | } |
15182 | ||
d93c0372 MR |
15183 | /* |
15184 | * Calculate what we think the watermarks should be for the state we've read | |
15185 | * out of the hardware and then immediately program those watermarks so that | |
15186 | * we ensure the hardware settings match our internal state. | |
15187 | * | |
15188 | * We can calculate what we think WM's should be by creating a duplicate of the | |
15189 | * current state (which was constructed during hardware readout) and running it | |
15190 | * through the atomic check code to calculate new watermark values in the | |
15191 | * state object. | |
15192 | */ | |
15193 | static void sanitize_watermarks(struct drm_device *dev) | |
15194 | { | |
15195 | struct drm_i915_private *dev_priv = to_i915(dev); | |
15196 | struct drm_atomic_state *state; | |
15197 | struct drm_crtc *crtc; | |
15198 | struct drm_crtc_state *cstate; | |
15199 | struct drm_modeset_acquire_ctx ctx; | |
15200 | int ret; | |
15201 | int i; | |
15202 | ||
15203 | /* Only supported on platforms that use atomic watermark design */ | |
ed4a6a7c | 15204 | if (!dev_priv->display.optimize_watermarks) |
d93c0372 MR |
15205 | return; |
15206 | ||
15207 | /* | |
15208 | * We need to hold connection_mutex before calling duplicate_state so | |
15209 | * that the connector loop is protected. | |
15210 | */ | |
15211 | drm_modeset_acquire_init(&ctx, 0); | |
15212 | retry: | |
0cd1262d | 15213 | ret = drm_modeset_lock_all_ctx(dev, &ctx); |
d93c0372 MR |
15214 | if (ret == -EDEADLK) { |
15215 | drm_modeset_backoff(&ctx); | |
15216 | goto retry; | |
15217 | } else if (WARN_ON(ret)) { | |
0cd1262d | 15218 | goto fail; |
d93c0372 MR |
15219 | } |
15220 | ||
15221 | state = drm_atomic_helper_duplicate_state(dev, &ctx); | |
15222 | if (WARN_ON(IS_ERR(state))) | |
0cd1262d | 15223 | goto fail; |
d93c0372 | 15224 | |
ed4a6a7c MR |
15225 | /* |
15226 | * Hardware readout is the only time we don't want to calculate | |
15227 | * intermediate watermarks (since we don't trust the current | |
15228 | * watermarks). | |
15229 | */ | |
15230 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
15231 | ||
d93c0372 MR |
15232 | ret = intel_atomic_check(dev, state); |
15233 | if (ret) { | |
15234 | /* | |
15235 | * If we fail here, it means that the hardware appears to be | |
15236 | * programmed in a way that shouldn't be possible, given our | |
15237 | * understanding of watermark requirements. This might mean a | |
15238 | * mistake in the hardware readout code or a mistake in the | |
15239 | * watermark calculations for a given platform. Raise a WARN | |
15240 | * so that this is noticeable. | |
15241 | * | |
15242 | * If this actually happens, we'll have to just leave the | |
15243 | * BIOS-programmed watermarks untouched and hope for the best. | |
15244 | */ | |
15245 | WARN(true, "Could not determine valid watermarks for inherited state\n"); | |
0cd1262d | 15246 | goto fail; |
d93c0372 MR |
15247 | } |
15248 | ||
15249 | /* Write calculated watermark values back */ | |
15250 | to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config; | |
15251 | for_each_crtc_in_state(state, crtc, cstate, i) { | |
15252 | struct intel_crtc_state *cs = to_intel_crtc_state(cstate); | |
15253 | ||
ed4a6a7c MR |
15254 | cs->wm.need_postvbl_update = true; |
15255 | dev_priv->display.optimize_watermarks(cs); | |
d93c0372 MR |
15256 | } |
15257 | ||
15258 | drm_atomic_state_free(state); | |
0cd1262d | 15259 | fail: |
d93c0372 MR |
15260 | drm_modeset_drop_locks(&ctx); |
15261 | drm_modeset_acquire_fini(&ctx); | |
15262 | } | |
15263 | ||
79e53945 JB |
15264 | void intel_modeset_init(struct drm_device *dev) |
15265 | { | |
652c393a | 15266 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 15267 | int sprite, ret; |
8cc87b75 | 15268 | enum pipe pipe; |
46f297fb | 15269 | struct intel_crtc *crtc; |
79e53945 JB |
15270 | |
15271 | drm_mode_config_init(dev); | |
15272 | ||
15273 | dev->mode_config.min_width = 0; | |
15274 | dev->mode_config.min_height = 0; | |
15275 | ||
019d96cb DA |
15276 | dev->mode_config.preferred_depth = 24; |
15277 | dev->mode_config.prefer_shadow = 1; | |
15278 | ||
25bab385 TU |
15279 | dev->mode_config.allow_fb_modifiers = true; |
15280 | ||
e6ecefaa | 15281 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 15282 | |
b690e96c JB |
15283 | intel_init_quirks(dev); |
15284 | ||
1fa61106 ED |
15285 | intel_init_pm(dev); |
15286 | ||
e3c74757 BW |
15287 | if (INTEL_INFO(dev)->num_pipes == 0) |
15288 | return; | |
15289 | ||
69f92f67 LW |
15290 | /* |
15291 | * There may be no VBT; and if the BIOS enabled SSC we can | |
15292 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
15293 | * BIOS isn't using it, don't assume it will work even if the VBT | |
15294 | * indicates as much. | |
15295 | */ | |
15296 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { | |
15297 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
15298 | DREF_SSC1_ENABLE); | |
15299 | ||
15300 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
15301 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
15302 | bios_lvds_use_ssc ? "en" : "dis", | |
15303 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
15304 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
15305 | } | |
15306 | } | |
15307 | ||
a6c45cf0 CW |
15308 | if (IS_GEN2(dev)) { |
15309 | dev->mode_config.max_width = 2048; | |
15310 | dev->mode_config.max_height = 2048; | |
15311 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
15312 | dev->mode_config.max_width = 4096; |
15313 | dev->mode_config.max_height = 4096; | |
79e53945 | 15314 | } else { |
a6c45cf0 CW |
15315 | dev->mode_config.max_width = 8192; |
15316 | dev->mode_config.max_height = 8192; | |
79e53945 | 15317 | } |
068be561 | 15318 | |
dc41c154 VS |
15319 | if (IS_845G(dev) || IS_I865G(dev)) { |
15320 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
15321 | dev->mode_config.cursor_height = 1023; | |
15322 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
15323 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
15324 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
15325 | } else { | |
15326 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
15327 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
15328 | } | |
15329 | ||
62106b4f | 15330 | dev->mode_config.fb_base = dev_priv->ggtt.mappable_base; |
79e53945 | 15331 | |
28c97730 | 15332 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
15333 | INTEL_INFO(dev)->num_pipes, |
15334 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 15335 | |
055e393f | 15336 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 15337 | intel_crtc_init(dev, pipe); |
3bdcfc0c | 15338 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 15339 | ret = intel_plane_init(dev, pipe, sprite); |
7f1f3851 | 15340 | if (ret) |
06da8da2 | 15341 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 15342 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 15343 | } |
79e53945 JB |
15344 | } |
15345 | ||
bfa7df01 | 15346 | intel_update_czclk(dev_priv); |
e7dc33f3 | 15347 | intel_update_rawclk(dev_priv); |
bfa7df01 VS |
15348 | intel_update_cdclk(dev); |
15349 | ||
e72f9fbf | 15350 | intel_shared_dpll_init(dev); |
ee7b9f93 | 15351 | |
9cce37f4 JB |
15352 | /* Just disable it once at startup */ |
15353 | i915_disable_vga(dev); | |
79e53945 | 15354 | intel_setup_outputs(dev); |
11be49eb | 15355 | |
6e9f798d | 15356 | drm_modeset_lock_all(dev); |
043e9bda | 15357 | intel_modeset_setup_hw_state(dev); |
6e9f798d | 15358 | drm_modeset_unlock_all(dev); |
46f297fb | 15359 | |
d3fcc808 | 15360 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
15361 | struct intel_initial_plane_config plane_config = {}; |
15362 | ||
46f297fb JB |
15363 | if (!crtc->active) |
15364 | continue; | |
15365 | ||
46f297fb | 15366 | /* |
46f297fb JB |
15367 | * Note that reserving the BIOS fb up front prevents us |
15368 | * from stuffing other stolen allocations like the ring | |
15369 | * on top. This prevents some ugliness at boot time, and | |
15370 | * can even allow for smooth boot transitions if the BIOS | |
15371 | * fb is large enough for the active pipe configuration. | |
15372 | */ | |
eeebeac5 ML |
15373 | dev_priv->display.get_initial_plane_config(crtc, |
15374 | &plane_config); | |
15375 | ||
15376 | /* | |
15377 | * If the fb is shared between multiple heads, we'll | |
15378 | * just get the first one. | |
15379 | */ | |
15380 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 15381 | } |
d93c0372 MR |
15382 | |
15383 | /* | |
15384 | * Make sure hardware watermarks really match the state we read out. | |
15385 | * Note that we need to do this after reconstructing the BIOS fb's | |
15386 | * since the watermark calculation done here will use pstate->fb. | |
15387 | */ | |
15388 | sanitize_watermarks(dev); | |
2c7111db CW |
15389 | } |
15390 | ||
7fad798e DV |
15391 | static void intel_enable_pipe_a(struct drm_device *dev) |
15392 | { | |
15393 | struct intel_connector *connector; | |
15394 | struct drm_connector *crt = NULL; | |
15395 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 15396 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
15397 | |
15398 | /* We can't just switch on the pipe A, we need to set things up with a | |
15399 | * proper mode and output configuration. As a gross hack, enable pipe A | |
15400 | * by enabling the load detect pipe once. */ | |
3a3371ff | 15401 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
15402 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
15403 | crt = &connector->base; | |
15404 | break; | |
15405 | } | |
15406 | } | |
15407 | ||
15408 | if (!crt) | |
15409 | return; | |
15410 | ||
208bf9fd | 15411 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 15412 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
15413 | } |
15414 | ||
fa555837 DV |
15415 | static bool |
15416 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
15417 | { | |
7eb552ae BW |
15418 | struct drm_device *dev = crtc->base.dev; |
15419 | struct drm_i915_private *dev_priv = dev->dev_private; | |
649636ef | 15420 | u32 val; |
fa555837 | 15421 | |
7eb552ae | 15422 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
15423 | return true; |
15424 | ||
649636ef | 15425 | val = I915_READ(DSPCNTR(!crtc->plane)); |
fa555837 DV |
15426 | |
15427 | if ((val & DISPLAY_PLANE_ENABLE) && | |
15428 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
15429 | return false; | |
15430 | ||
15431 | return true; | |
15432 | } | |
15433 | ||
02e93c35 VS |
15434 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
15435 | { | |
15436 | struct drm_device *dev = crtc->base.dev; | |
15437 | struct intel_encoder *encoder; | |
15438 | ||
15439 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
15440 | return true; | |
15441 | ||
15442 | return false; | |
15443 | } | |
15444 | ||
dd756198 VS |
15445 | static bool intel_encoder_has_connectors(struct intel_encoder *encoder) |
15446 | { | |
15447 | struct drm_device *dev = encoder->base.dev; | |
15448 | struct intel_connector *connector; | |
15449 | ||
15450 | for_each_connector_on_encoder(dev, &encoder->base, connector) | |
15451 | return true; | |
15452 | ||
15453 | return false; | |
15454 | } | |
15455 | ||
24929352 DV |
15456 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
15457 | { | |
15458 | struct drm_device *dev = crtc->base.dev; | |
15459 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4d1de975 | 15460 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
24929352 | 15461 | |
24929352 | 15462 | /* Clear any frame start delays used for debugging left by the BIOS */ |
4d1de975 JN |
15463 | if (!transcoder_is_dsi(cpu_transcoder)) { |
15464 | i915_reg_t reg = PIPECONF(cpu_transcoder); | |
15465 | ||
15466 | I915_WRITE(reg, | |
15467 | I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); | |
15468 | } | |
24929352 | 15469 | |
d3eaf884 | 15470 | /* restore vblank interrupts to correct state */ |
9625604c | 15471 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 15472 | if (crtc->active) { |
f9cd7b88 VS |
15473 | struct intel_plane *plane; |
15474 | ||
9625604c | 15475 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
15476 | |
15477 | /* Disable everything but the primary plane */ | |
15478 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
15479 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
15480 | continue; | |
15481 | ||
15482 | plane->disable_plane(&plane->base, &crtc->base); | |
15483 | } | |
9625604c | 15484 | } |
d3eaf884 | 15485 | |
24929352 | 15486 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
15487 | * disable the crtc (and hence change the state) if it is wrong. Note |
15488 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
15489 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
15490 | bool plane; |
15491 | ||
24929352 DV |
15492 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
15493 | crtc->base.base.id); | |
15494 | ||
15495 | /* Pipe has the wrong plane attached and the plane is active. | |
15496 | * Temporarily change the plane mapping and disable everything | |
15497 | * ... */ | |
15498 | plane = crtc->plane; | |
b70709a6 | 15499 | to_intel_plane_state(crtc->base.primary->state)->visible = true; |
24929352 | 15500 | crtc->plane = !plane; |
b17d48e2 | 15501 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15502 | crtc->plane = plane; |
24929352 | 15503 | } |
24929352 | 15504 | |
7fad798e DV |
15505 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
15506 | crtc->pipe == PIPE_A && !crtc->active) { | |
15507 | /* BIOS forgot to enable pipe A, this mostly happens after | |
15508 | * resume. Force-enable the pipe to fix this, the update_dpms | |
15509 | * call below we restore the pipe to the right state, but leave | |
15510 | * the required bits on. */ | |
15511 | intel_enable_pipe_a(dev); | |
15512 | } | |
15513 | ||
24929352 DV |
15514 | /* Adjust the state of the output pipe according to whether we |
15515 | * have active connectors/encoders. */ | |
842e0307 | 15516 | if (crtc->active && !intel_crtc_has_encoders(crtc)) |
b17d48e2 | 15517 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15518 | |
a3ed6aad | 15519 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
15520 | /* |
15521 | * We start out with underrun reporting disabled to avoid races. | |
15522 | * For correct bookkeeping mark this on active crtcs. | |
15523 | * | |
c5ab3bc0 DV |
15524 | * Also on gmch platforms we dont have any hardware bits to |
15525 | * disable the underrun reporting. Which means we need to start | |
15526 | * out with underrun reporting disabled also on inactive pipes, | |
15527 | * since otherwise we'll complain about the garbage we read when | |
15528 | * e.g. coming up after runtime pm. | |
15529 | * | |
4cc31489 DV |
15530 | * No protection against concurrent access is required - at |
15531 | * worst a fifo underrun happens which also sets this to false. | |
15532 | */ | |
15533 | crtc->cpu_fifo_underrun_disabled = true; | |
15534 | crtc->pch_fifo_underrun_disabled = true; | |
15535 | } | |
24929352 DV |
15536 | } |
15537 | ||
15538 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
15539 | { | |
15540 | struct intel_connector *connector; | |
15541 | struct drm_device *dev = encoder->base.dev; | |
15542 | ||
15543 | /* We need to check both for a crtc link (meaning that the | |
15544 | * encoder is active and trying to read from a pipe) and the | |
15545 | * pipe itself being active. */ | |
15546 | bool has_active_crtc = encoder->base.crtc && | |
15547 | to_intel_crtc(encoder->base.crtc)->active; | |
15548 | ||
dd756198 | 15549 | if (intel_encoder_has_connectors(encoder) && !has_active_crtc) { |
24929352 DV |
15550 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
15551 | encoder->base.base.id, | |
8e329a03 | 15552 | encoder->base.name); |
24929352 DV |
15553 | |
15554 | /* Connector is active, but has no active pipe. This is | |
15555 | * fallout from our resume register restoring. Disable | |
15556 | * the encoder manually again. */ | |
15557 | if (encoder->base.crtc) { | |
15558 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
15559 | encoder->base.base.id, | |
8e329a03 | 15560 | encoder->base.name); |
24929352 | 15561 | encoder->disable(encoder); |
a62d1497 VS |
15562 | if (encoder->post_disable) |
15563 | encoder->post_disable(encoder); | |
24929352 | 15564 | } |
7f1950fb | 15565 | encoder->base.crtc = NULL; |
24929352 DV |
15566 | |
15567 | /* Inconsistent output/port/pipe state happens presumably due to | |
15568 | * a bug in one of the get_hw_state functions. Or someplace else | |
15569 | * in our code, like the register restore mess on resume. Clamp | |
15570 | * things to off as a safer default. */ | |
3a3371ff | 15571 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15572 | if (connector->encoder != encoder) |
15573 | continue; | |
7f1950fb EE |
15574 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
15575 | connector->base.encoder = NULL; | |
24929352 DV |
15576 | } |
15577 | } | |
15578 | /* Enabled encoders without active connectors will be fixed in | |
15579 | * the crtc fixup. */ | |
15580 | } | |
15581 | ||
04098753 | 15582 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
15583 | { |
15584 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 15585 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 15586 | |
04098753 ID |
15587 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
15588 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
15589 | i915_disable_vga(dev); | |
15590 | } | |
15591 | } | |
15592 | ||
15593 | void i915_redisable_vga(struct drm_device *dev) | |
15594 | { | |
15595 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15596 | ||
8dc8a27c PZ |
15597 | /* This function can be called both from intel_modeset_setup_hw_state or |
15598 | * at a very early point in our resume sequence, where the power well | |
15599 | * structures are not yet restored. Since this function is at a very | |
15600 | * paranoid "someone might have enabled VGA while we were not looking" | |
15601 | * level, just check if the power well is enabled instead of trying to | |
15602 | * follow the "don't touch the power well if we don't need it" policy | |
15603 | * the rest of the driver uses. */ | |
6392f847 | 15604 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
15605 | return; |
15606 | ||
04098753 | 15607 | i915_redisable_vga_power_on(dev); |
6392f847 ID |
15608 | |
15609 | intel_display_power_put(dev_priv, POWER_DOMAIN_VGA); | |
0fde901f KM |
15610 | } |
15611 | ||
f9cd7b88 | 15612 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 15613 | { |
f9cd7b88 | 15614 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 15615 | |
f9cd7b88 | 15616 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
15617 | } |
15618 | ||
f9cd7b88 VS |
15619 | /* FIXME read out full plane state for all planes */ |
15620 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 15621 | { |
b26d3ea3 | 15622 | struct drm_plane *primary = crtc->base.primary; |
f9cd7b88 | 15623 | struct intel_plane_state *plane_state = |
b26d3ea3 | 15624 | to_intel_plane_state(primary->state); |
d032ffa0 | 15625 | |
19b8d387 | 15626 | plane_state->visible = crtc->active && |
b26d3ea3 ML |
15627 | primary_get_hw_state(to_intel_plane(primary)); |
15628 | ||
15629 | if (plane_state->visible) | |
15630 | crtc->base.state->plane_mask |= 1 << drm_plane_index(primary); | |
98ec7739 VS |
15631 | } |
15632 | ||
30e984df | 15633 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
15634 | { |
15635 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15636 | enum pipe pipe; | |
24929352 DV |
15637 | struct intel_crtc *crtc; |
15638 | struct intel_encoder *encoder; | |
15639 | struct intel_connector *connector; | |
5358901f | 15640 | int i; |
24929352 | 15641 | |
565602d7 ML |
15642 | dev_priv->active_crtcs = 0; |
15643 | ||
d3fcc808 | 15644 | for_each_intel_crtc(dev, crtc) { |
565602d7 ML |
15645 | struct intel_crtc_state *crtc_state = crtc->config; |
15646 | int pixclk = 0; | |
3b117c8f | 15647 | |
565602d7 ML |
15648 | __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base); |
15649 | memset(crtc_state, 0, sizeof(*crtc_state)); | |
15650 | crtc_state->base.crtc = &crtc->base; | |
24929352 | 15651 | |
565602d7 ML |
15652 | crtc_state->base.active = crtc_state->base.enable = |
15653 | dev_priv->display.get_pipe_config(crtc, crtc_state); | |
15654 | ||
15655 | crtc->base.enabled = crtc_state->base.enable; | |
15656 | crtc->active = crtc_state->base.active; | |
15657 | ||
15658 | if (crtc_state->base.active) { | |
15659 | dev_priv->active_crtcs |= 1 << crtc->pipe; | |
15660 | ||
15661 | if (IS_BROADWELL(dev_priv)) { | |
15662 | pixclk = ilk_pipe_pixel_rate(crtc_state); | |
15663 | ||
15664 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
15665 | if (crtc_state->ips_enabled) | |
15666 | pixclk = DIV_ROUND_UP(pixclk * 100, 95); | |
15667 | } else if (IS_VALLEYVIEW(dev_priv) || | |
15668 | IS_CHERRYVIEW(dev_priv) || | |
15669 | IS_BROXTON(dev_priv)) | |
15670 | pixclk = crtc_state->base.adjusted_mode.crtc_clock; | |
15671 | else | |
15672 | WARN_ON(dev_priv->display.modeset_calc_cdclk); | |
15673 | } | |
15674 | ||
15675 | dev_priv->min_pixclk[crtc->pipe] = pixclk; | |
b70709a6 | 15676 | |
f9cd7b88 | 15677 | readout_plane_state(crtc); |
24929352 DV |
15678 | |
15679 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
15680 | crtc->base.base.id, | |
15681 | crtc->active ? "enabled" : "disabled"); | |
15682 | } | |
15683 | ||
5358901f DV |
15684 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15685 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15686 | ||
2edd6443 ACO |
15687 | pll->on = pll->funcs.get_hw_state(dev_priv, pll, |
15688 | &pll->config.hw_state); | |
3e369b76 | 15689 | pll->config.crtc_mask = 0; |
d3fcc808 | 15690 | for_each_intel_crtc(dev, crtc) { |
2dd66ebd | 15691 | if (crtc->active && crtc->config->shared_dpll == pll) |
3e369b76 | 15692 | pll->config.crtc_mask |= 1 << crtc->pipe; |
5358901f | 15693 | } |
2dd66ebd | 15694 | pll->active_mask = pll->config.crtc_mask; |
5358901f | 15695 | |
1e6f2ddc | 15696 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 15697 | pll->name, pll->config.crtc_mask, pll->on); |
5358901f DV |
15698 | } |
15699 | ||
b2784e15 | 15700 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15701 | pipe = 0; |
15702 | ||
15703 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
15704 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15705 | encoder->base.crtc = &crtc->base; | |
6e3c9717 | 15706 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
15707 | } else { |
15708 | encoder->base.crtc = NULL; | |
15709 | } | |
15710 | ||
6f2bcceb | 15711 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 15712 | encoder->base.base.id, |
8e329a03 | 15713 | encoder->base.name, |
24929352 | 15714 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 15715 | pipe_name(pipe)); |
24929352 DV |
15716 | } |
15717 | ||
3a3371ff | 15718 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15719 | if (connector->get_hw_state(connector)) { |
15720 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
2aa974c9 ML |
15721 | |
15722 | encoder = connector->encoder; | |
15723 | connector->base.encoder = &encoder->base; | |
15724 | ||
15725 | if (encoder->base.crtc && | |
15726 | encoder->base.crtc->state->active) { | |
15727 | /* | |
15728 | * This has to be done during hardware readout | |
15729 | * because anything calling .crtc_disable may | |
15730 | * rely on the connector_mask being accurate. | |
15731 | */ | |
15732 | encoder->base.crtc->state->connector_mask |= | |
15733 | 1 << drm_connector_index(&connector->base); | |
e87a52b3 ML |
15734 | encoder->base.crtc->state->encoder_mask |= |
15735 | 1 << drm_encoder_index(&encoder->base); | |
2aa974c9 ML |
15736 | } |
15737 | ||
24929352 DV |
15738 | } else { |
15739 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
15740 | connector->base.encoder = NULL; | |
15741 | } | |
15742 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
15743 | connector->base.base.id, | |
c23cc417 | 15744 | connector->base.name, |
24929352 DV |
15745 | connector->base.encoder ? "enabled" : "disabled"); |
15746 | } | |
7f4c6284 VS |
15747 | |
15748 | for_each_intel_crtc(dev, crtc) { | |
15749 | crtc->base.hwmode = crtc->config->base.adjusted_mode; | |
15750 | ||
15751 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); | |
15752 | if (crtc->base.state->active) { | |
15753 | intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); | |
15754 | intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config); | |
15755 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); | |
15756 | ||
15757 | /* | |
15758 | * The initial mode needs to be set in order to keep | |
15759 | * the atomic core happy. It wants a valid mode if the | |
15760 | * crtc's enabled, so we do the above call. | |
15761 | * | |
15762 | * At this point some state updated by the connectors | |
15763 | * in their ->detect() callback has not run yet, so | |
15764 | * no recalculation can be done yet. | |
15765 | * | |
15766 | * Even if we could do a recalculation and modeset | |
15767 | * right now it would cause a double modeset if | |
15768 | * fbdev or userspace chooses a different initial mode. | |
15769 | * | |
15770 | * If that happens, someone indicated they wanted a | |
15771 | * mode change, which means it's safe to do a full | |
15772 | * recalculation. | |
15773 | */ | |
15774 | crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED; | |
9eca6832 VS |
15775 | |
15776 | drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); | |
15777 | update_scanline_offset(crtc); | |
7f4c6284 | 15778 | } |
e3b247da VS |
15779 | |
15780 | intel_pipe_config_sanity_check(dev_priv, crtc->config); | |
7f4c6284 | 15781 | } |
30e984df DV |
15782 | } |
15783 | ||
043e9bda ML |
15784 | /* Scan out the current hw modeset state, |
15785 | * and sanitizes it to the current state | |
15786 | */ | |
15787 | static void | |
15788 | intel_modeset_setup_hw_state(struct drm_device *dev) | |
30e984df DV |
15789 | { |
15790 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15791 | enum pipe pipe; | |
30e984df DV |
15792 | struct intel_crtc *crtc; |
15793 | struct intel_encoder *encoder; | |
35c95375 | 15794 | int i; |
30e984df DV |
15795 | |
15796 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
15797 | |
15798 | /* HW state is read out, now we need to sanitize this mess. */ | |
b2784e15 | 15799 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15800 | intel_sanitize_encoder(encoder); |
15801 | } | |
15802 | ||
055e393f | 15803 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
15804 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15805 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
15806 | intel_dump_pipe_config(crtc, crtc->config, |
15807 | "[setup_hw_state]"); | |
24929352 | 15808 | } |
9a935856 | 15809 | |
d29b2f9d ACO |
15810 | intel_modeset_update_connector_atomic_state(dev); |
15811 | ||
35c95375 DV |
15812 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15813 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15814 | ||
2dd66ebd | 15815 | if (!pll->on || pll->active_mask) |
35c95375 DV |
15816 | continue; |
15817 | ||
15818 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
15819 | ||
2edd6443 | 15820 | pll->funcs.disable(dev_priv, pll); |
35c95375 DV |
15821 | pll->on = false; |
15822 | } | |
15823 | ||
666a4537 | 15824 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
6eb1a681 VS |
15825 | vlv_wm_get_hw_state(dev); |
15826 | else if (IS_GEN9(dev)) | |
3078999f PB |
15827 | skl_wm_get_hw_state(dev); |
15828 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 | 15829 | ilk_wm_get_hw_state(dev); |
292b990e ML |
15830 | |
15831 | for_each_intel_crtc(dev, crtc) { | |
15832 | unsigned long put_domains; | |
15833 | ||
74bff5f9 | 15834 | put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config); |
292b990e ML |
15835 | if (WARN_ON(put_domains)) |
15836 | modeset_put_power_domains(dev_priv, put_domains); | |
15837 | } | |
15838 | intel_display_set_init_power(dev_priv, false); | |
010cf73d PZ |
15839 | |
15840 | intel_fbc_init_pipe_state(dev_priv); | |
043e9bda | 15841 | } |
7d0bc1ea | 15842 | |
043e9bda ML |
15843 | void intel_display_resume(struct drm_device *dev) |
15844 | { | |
e2c8b870 ML |
15845 | struct drm_i915_private *dev_priv = to_i915(dev); |
15846 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
15847 | struct drm_modeset_acquire_ctx ctx; | |
043e9bda | 15848 | int ret; |
e2c8b870 | 15849 | bool setup = false; |
f30da187 | 15850 | |
e2c8b870 | 15851 | dev_priv->modeset_restore_state = NULL; |
043e9bda | 15852 | |
ea49c9ac ML |
15853 | /* |
15854 | * This is a cludge because with real atomic modeset mode_config.mutex | |
15855 | * won't be taken. Unfortunately some probed state like | |
15856 | * audio_codec_enable is still protected by mode_config.mutex, so lock | |
15857 | * it here for now. | |
15858 | */ | |
15859 | mutex_lock(&dev->mode_config.mutex); | |
e2c8b870 | 15860 | drm_modeset_acquire_init(&ctx, 0); |
043e9bda | 15861 | |
e2c8b870 ML |
15862 | retry: |
15863 | ret = drm_modeset_lock_all_ctx(dev, &ctx); | |
043e9bda | 15864 | |
e2c8b870 ML |
15865 | if (ret == 0 && !setup) { |
15866 | setup = true; | |
043e9bda | 15867 | |
e2c8b870 ML |
15868 | intel_modeset_setup_hw_state(dev); |
15869 | i915_redisable_vga(dev); | |
45e2b5f6 | 15870 | } |
8af6cf88 | 15871 | |
e2c8b870 ML |
15872 | if (ret == 0 && state) { |
15873 | struct drm_crtc_state *crtc_state; | |
15874 | struct drm_crtc *crtc; | |
15875 | int i; | |
043e9bda | 15876 | |
e2c8b870 ML |
15877 | state->acquire_ctx = &ctx; |
15878 | ||
15879 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
15880 | /* | |
15881 | * Force recalculation even if we restore | |
15882 | * current state. With fast modeset this may not result | |
15883 | * in a modeset when the state is compatible. | |
15884 | */ | |
15885 | crtc_state->mode_changed = true; | |
15886 | } | |
15887 | ||
15888 | ret = drm_atomic_commit(state); | |
043e9bda ML |
15889 | } |
15890 | ||
e2c8b870 ML |
15891 | if (ret == -EDEADLK) { |
15892 | drm_modeset_backoff(&ctx); | |
15893 | goto retry; | |
15894 | } | |
043e9bda | 15895 | |
e2c8b870 ML |
15896 | drm_modeset_drop_locks(&ctx); |
15897 | drm_modeset_acquire_fini(&ctx); | |
ea49c9ac | 15898 | mutex_unlock(&dev->mode_config.mutex); |
043e9bda | 15899 | |
e2c8b870 ML |
15900 | if (ret) { |
15901 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
15902 | drm_atomic_state_free(state); | |
15903 | } | |
2c7111db CW |
15904 | } |
15905 | ||
15906 | void intel_modeset_gem_init(struct drm_device *dev) | |
15907 | { | |
484b41dd | 15908 | struct drm_crtc *c; |
2ff8fde1 | 15909 | struct drm_i915_gem_object *obj; |
e0d6149b | 15910 | int ret; |
484b41dd | 15911 | |
ae48434c | 15912 | intel_init_gt_powersave(dev); |
ae48434c | 15913 | |
1833b134 | 15914 | intel_modeset_init_hw(dev); |
02e792fb DV |
15915 | |
15916 | intel_setup_overlay(dev); | |
484b41dd JB |
15917 | |
15918 | /* | |
15919 | * Make sure any fbs we allocated at startup are properly | |
15920 | * pinned & fenced. When we do the allocation it's too early | |
15921 | * for this. | |
15922 | */ | |
70e1e0ec | 15923 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
15924 | obj = intel_fb_obj(c->primary->fb); |
15925 | if (obj == NULL) | |
484b41dd JB |
15926 | continue; |
15927 | ||
e0d6149b | 15928 | mutex_lock(&dev->struct_mutex); |
3465c580 VS |
15929 | ret = intel_pin_and_fence_fb_obj(c->primary->fb, |
15930 | c->primary->state->rotation); | |
e0d6149b TU |
15931 | mutex_unlock(&dev->struct_mutex); |
15932 | if (ret) { | |
484b41dd JB |
15933 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
15934 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
15935 | drm_framebuffer_unreference(c->primary->fb); |
15936 | c->primary->fb = NULL; | |
36750f28 | 15937 | c->primary->crtc = c->primary->state->crtc = NULL; |
afd65eb4 | 15938 | update_state_fb(c->primary); |
36750f28 | 15939 | c->state->plane_mask &= ~(1 << drm_plane_index(c->primary)); |
484b41dd JB |
15940 | } |
15941 | } | |
0962c3c9 VS |
15942 | |
15943 | intel_backlight_register(dev); | |
79e53945 JB |
15944 | } |
15945 | ||
4932e2c3 ID |
15946 | void intel_connector_unregister(struct intel_connector *intel_connector) |
15947 | { | |
15948 | struct drm_connector *connector = &intel_connector->base; | |
15949 | ||
15950 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 15951 | drm_connector_unregister(connector); |
4932e2c3 ID |
15952 | } |
15953 | ||
79e53945 JB |
15954 | void intel_modeset_cleanup(struct drm_device *dev) |
15955 | { | |
652c393a | 15956 | struct drm_i915_private *dev_priv = dev->dev_private; |
19c8054c | 15957 | struct intel_connector *connector; |
652c393a | 15958 | |
2eb5252e ID |
15959 | intel_disable_gt_powersave(dev); |
15960 | ||
0962c3c9 VS |
15961 | intel_backlight_unregister(dev); |
15962 | ||
fd0c0642 DV |
15963 | /* |
15964 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 15965 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
15966 | * experience fancy races otherwise. |
15967 | */ | |
2aeb7d3a | 15968 | intel_irq_uninstall(dev_priv); |
eb21b92b | 15969 | |
fd0c0642 DV |
15970 | /* |
15971 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
15972 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
15973 | */ | |
f87ea761 | 15974 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 15975 | |
723bfd70 JB |
15976 | intel_unregister_dsm_handler(); |
15977 | ||
c937ab3e | 15978 | intel_fbc_global_disable(dev_priv); |
69341a5e | 15979 | |
1630fe75 CW |
15980 | /* flush any delayed tasks or pending work */ |
15981 | flush_scheduled_work(); | |
15982 | ||
db31af1d | 15983 | /* destroy the backlight and sysfs files before encoders/connectors */ |
19c8054c JN |
15984 | for_each_intel_connector(dev, connector) |
15985 | connector->unregister(connector); | |
d9255d57 | 15986 | |
79e53945 | 15987 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
15988 | |
15989 | intel_cleanup_overlay(dev); | |
ae48434c | 15990 | |
ae48434c | 15991 | intel_cleanup_gt_powersave(dev); |
f5949141 DV |
15992 | |
15993 | intel_teardown_gmbus(dev); | |
79e53945 JB |
15994 | } |
15995 | ||
f1c79df3 ZW |
15996 | /* |
15997 | * Return which encoder is currently attached for connector. | |
15998 | */ | |
df0e9248 | 15999 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 16000 | { |
df0e9248 CW |
16001 | return &intel_attached_encoder(connector)->base; |
16002 | } | |
f1c79df3 | 16003 | |
df0e9248 CW |
16004 | void intel_connector_attach_encoder(struct intel_connector *connector, |
16005 | struct intel_encoder *encoder) | |
16006 | { | |
16007 | connector->encoder = encoder; | |
16008 | drm_mode_connector_attach_encoder(&connector->base, | |
16009 | &encoder->base); | |
79e53945 | 16010 | } |
28d52043 DA |
16011 | |
16012 | /* | |
16013 | * set vga decode state - true == enable VGA decode | |
16014 | */ | |
16015 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
16016 | { | |
16017 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 16018 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
16019 | u16 gmch_ctrl; |
16020 | ||
75fa041d CW |
16021 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
16022 | DRM_ERROR("failed to read control word\n"); | |
16023 | return -EIO; | |
16024 | } | |
16025 | ||
c0cc8a55 CW |
16026 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
16027 | return 0; | |
16028 | ||
28d52043 DA |
16029 | if (state) |
16030 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
16031 | else | |
16032 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
16033 | |
16034 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
16035 | DRM_ERROR("failed to write control word\n"); | |
16036 | return -EIO; | |
16037 | } | |
16038 | ||
28d52043 DA |
16039 | return 0; |
16040 | } | |
c4a1d9e4 | 16041 | |
c4a1d9e4 | 16042 | struct intel_display_error_state { |
ff57f1b0 PZ |
16043 | |
16044 | u32 power_well_driver; | |
16045 | ||
63b66e5b CW |
16046 | int num_transcoders; |
16047 | ||
c4a1d9e4 CW |
16048 | struct intel_cursor_error_state { |
16049 | u32 control; | |
16050 | u32 position; | |
16051 | u32 base; | |
16052 | u32 size; | |
52331309 | 16053 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
16054 | |
16055 | struct intel_pipe_error_state { | |
ddf9c536 | 16056 | bool power_domain_on; |
c4a1d9e4 | 16057 | u32 source; |
f301b1e1 | 16058 | u32 stat; |
52331309 | 16059 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
16060 | |
16061 | struct intel_plane_error_state { | |
16062 | u32 control; | |
16063 | u32 stride; | |
16064 | u32 size; | |
16065 | u32 pos; | |
16066 | u32 addr; | |
16067 | u32 surface; | |
16068 | u32 tile_offset; | |
52331309 | 16069 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
16070 | |
16071 | struct intel_transcoder_error_state { | |
ddf9c536 | 16072 | bool power_domain_on; |
63b66e5b CW |
16073 | enum transcoder cpu_transcoder; |
16074 | ||
16075 | u32 conf; | |
16076 | ||
16077 | u32 htotal; | |
16078 | u32 hblank; | |
16079 | u32 hsync; | |
16080 | u32 vtotal; | |
16081 | u32 vblank; | |
16082 | u32 vsync; | |
16083 | } transcoder[4]; | |
c4a1d9e4 CW |
16084 | }; |
16085 | ||
16086 | struct intel_display_error_state * | |
16087 | intel_display_capture_error_state(struct drm_device *dev) | |
16088 | { | |
fbee40df | 16089 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 16090 | struct intel_display_error_state *error; |
63b66e5b CW |
16091 | int transcoders[] = { |
16092 | TRANSCODER_A, | |
16093 | TRANSCODER_B, | |
16094 | TRANSCODER_C, | |
16095 | TRANSCODER_EDP, | |
16096 | }; | |
c4a1d9e4 CW |
16097 | int i; |
16098 | ||
63b66e5b CW |
16099 | if (INTEL_INFO(dev)->num_pipes == 0) |
16100 | return NULL; | |
16101 | ||
9d1cb914 | 16102 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
16103 | if (error == NULL) |
16104 | return NULL; | |
16105 | ||
190be112 | 16106 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
16107 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
16108 | ||
055e393f | 16109 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 16110 | error->pipe[i].power_domain_on = |
f458ebbc DV |
16111 | __intel_display_power_is_enabled(dev_priv, |
16112 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 16113 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
16114 | continue; |
16115 | ||
5efb3e28 VS |
16116 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
16117 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
16118 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
16119 | |
16120 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
16121 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 16122 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 16123 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
16124 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
16125 | } | |
ca291363 PZ |
16126 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
16127 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
16128 | if (INTEL_INFO(dev)->gen >= 4) { |
16129 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
16130 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
16131 | } | |
16132 | ||
c4a1d9e4 | 16133 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 16134 | |
3abfce77 | 16135 | if (HAS_GMCH_DISPLAY(dev)) |
f301b1e1 | 16136 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
16137 | } |
16138 | ||
4d1de975 | 16139 | /* Note: this does not include DSI transcoders. */ |
63b66e5b CW |
16140 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; |
16141 | if (HAS_DDI(dev_priv->dev)) | |
16142 | error->num_transcoders++; /* Account for eDP. */ | |
16143 | ||
16144 | for (i = 0; i < error->num_transcoders; i++) { | |
16145 | enum transcoder cpu_transcoder = transcoders[i]; | |
16146 | ||
ddf9c536 | 16147 | error->transcoder[i].power_domain_on = |
f458ebbc | 16148 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 16149 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 16150 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
16151 | continue; |
16152 | ||
63b66e5b CW |
16153 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
16154 | ||
16155 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
16156 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
16157 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
16158 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
16159 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
16160 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
16161 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
16162 | } |
16163 | ||
16164 | return error; | |
16165 | } | |
16166 | ||
edc3d884 MK |
16167 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
16168 | ||
c4a1d9e4 | 16169 | void |
edc3d884 | 16170 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
16171 | struct drm_device *dev, |
16172 | struct intel_display_error_state *error) | |
16173 | { | |
055e393f | 16174 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
16175 | int i; |
16176 | ||
63b66e5b CW |
16177 | if (!error) |
16178 | return; | |
16179 | ||
edc3d884 | 16180 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 16181 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 16182 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 16183 | error->power_well_driver); |
055e393f | 16184 | for_each_pipe(dev_priv, i) { |
edc3d884 | 16185 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 | 16186 | err_printf(m, " Power: %s\n", |
87ad3212 | 16187 | onoff(error->pipe[i].power_domain_on)); |
edc3d884 | 16188 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 16189 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
16190 | |
16191 | err_printf(m, "Plane [%d]:\n", i); | |
16192 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
16193 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 16194 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
16195 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
16196 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 16197 | } |
4b71a570 | 16198 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 16199 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 16200 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
16201 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
16202 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
16203 | } |
16204 | ||
edc3d884 MK |
16205 | err_printf(m, "Cursor [%d]:\n", i); |
16206 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
16207 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
16208 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 16209 | } |
63b66e5b CW |
16210 | |
16211 | for (i = 0; i < error->num_transcoders; i++) { | |
da205630 | 16212 | err_printf(m, "CPU transcoder: %s\n", |
63b66e5b | 16213 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 | 16214 | err_printf(m, " Power: %s\n", |
87ad3212 | 16215 | onoff(error->transcoder[i].power_domain_on)); |
63b66e5b CW |
16216 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
16217 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
16218 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
16219 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
16220 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
16221 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
16222 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
16223 | } | |
c4a1d9e4 | 16224 | } |