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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
5d723d7a | 37 | #include "intel_frontbuffer.h" |
760285e7 | 38 | #include <drm/i915_drm.h> |
79e53945 | 39 | #include "i915_drv.h" |
57822dc6 | 40 | #include "i915_gem_clflush.h" |
db18b6a6 | 41 | #include "intel_dsi.h" |
e5510fac | 42 | #include "i915_trace.h" |
319c1d42 | 43 | #include <drm/drm_atomic.h> |
c196e1d6 | 44 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
45 | #include <drm/drm_dp_helper.h> |
46 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
47 | #include <drm/drm_plane_helper.h> |
48 | #include <drm/drm_rect.h> | |
c0f372b3 | 49 | #include <linux/dma_remapping.h> |
fd8e058a | 50 | #include <linux/reservation.h> |
79e53945 | 51 | |
465c120c | 52 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 53 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
54 | DRM_FORMAT_C8, |
55 | DRM_FORMAT_RGB565, | |
465c120c | 56 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 57 | DRM_FORMAT_XRGB8888, |
465c120c MR |
58 | }; |
59 | ||
60 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 61 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
62 | DRM_FORMAT_C8, |
63 | DRM_FORMAT_RGB565, | |
64 | DRM_FORMAT_XRGB8888, | |
65 | DRM_FORMAT_XBGR8888, | |
66 | DRM_FORMAT_XRGB2101010, | |
67 | DRM_FORMAT_XBGR2101010, | |
68 | }; | |
69 | ||
714244e2 BW |
70 | static const uint64_t i9xx_format_modifiers[] = { |
71 | I915_FORMAT_MOD_X_TILED, | |
72 | DRM_FORMAT_MOD_LINEAR, | |
73 | DRM_FORMAT_MOD_INVALID | |
74 | }; | |
75 | ||
6c0fd451 | 76 | static const uint32_t skl_primary_formats[] = { |
67fe7dc5 DL |
77 | DRM_FORMAT_C8, |
78 | DRM_FORMAT_RGB565, | |
79 | DRM_FORMAT_XRGB8888, | |
465c120c | 80 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 81 | DRM_FORMAT_ARGB8888, |
465c120c MR |
82 | DRM_FORMAT_ABGR8888, |
83 | DRM_FORMAT_XRGB2101010, | |
465c120c | 84 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
85 | DRM_FORMAT_YUYV, |
86 | DRM_FORMAT_YVYU, | |
87 | DRM_FORMAT_UYVY, | |
88 | DRM_FORMAT_VYUY, | |
465c120c MR |
89 | }; |
90 | ||
714244e2 BW |
91 | static const uint64_t skl_format_modifiers_noccs[] = { |
92 | I915_FORMAT_MOD_Yf_TILED, | |
93 | I915_FORMAT_MOD_Y_TILED, | |
94 | I915_FORMAT_MOD_X_TILED, | |
95 | DRM_FORMAT_MOD_LINEAR, | |
96 | DRM_FORMAT_MOD_INVALID | |
97 | }; | |
98 | ||
99 | static const uint64_t skl_format_modifiers_ccs[] = { | |
100 | I915_FORMAT_MOD_Yf_TILED_CCS, | |
101 | I915_FORMAT_MOD_Y_TILED_CCS, | |
102 | I915_FORMAT_MOD_Yf_TILED, | |
103 | I915_FORMAT_MOD_Y_TILED, | |
104 | I915_FORMAT_MOD_X_TILED, | |
105 | DRM_FORMAT_MOD_LINEAR, | |
106 | DRM_FORMAT_MOD_INVALID | |
107 | }; | |
108 | ||
3d7d6510 MR |
109 | /* Cursor formats */ |
110 | static const uint32_t intel_cursor_formats[] = { | |
111 | DRM_FORMAT_ARGB8888, | |
112 | }; | |
113 | ||
714244e2 BW |
114 | static const uint64_t cursor_format_modifiers[] = { |
115 | DRM_FORMAT_MOD_LINEAR, | |
116 | DRM_FORMAT_MOD_INVALID | |
117 | }; | |
118 | ||
f1f644dc | 119 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 120 | struct intel_crtc_state *pipe_config); |
18442d08 | 121 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 122 | struct intel_crtc_state *pipe_config); |
f1f644dc | 123 | |
24dbf51a CW |
124 | static int intel_framebuffer_init(struct intel_framebuffer *ifb, |
125 | struct drm_i915_gem_object *obj, | |
126 | struct drm_mode_fb_cmd2 *mode_cmd); | |
5b18e57c DV |
127 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
128 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
bc58be60 | 129 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc); |
29407aab | 130 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
131 | struct intel_link_m_n *m_n, |
132 | struct intel_link_m_n *m2_n2); | |
29407aab | 133 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 | 134 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
391bf048 | 135 | static void haswell_set_pipemisc(struct drm_crtc *crtc); |
d288f65f | 136 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 137 | const struct intel_crtc_state *pipe_config); |
d288f65f | 138 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 139 | const struct intel_crtc_state *pipe_config); |
5a21b665 DV |
140 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
141 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
1c74eeaf NM |
142 | static void intel_crtc_init_scalers(struct intel_crtc *crtc, |
143 | struct intel_crtc_state *crtc_state); | |
bfd16b2a ML |
144 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
145 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
146 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
aecd36b8 VS |
147 | static void intel_modeset_setup_hw_state(struct drm_device *dev, |
148 | struct drm_modeset_acquire_ctx *ctx); | |
2622a081 | 149 | static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc); |
e7457a9a | 150 | |
d4906093 | 151 | struct intel_limit { |
4c5def93 ACO |
152 | struct { |
153 | int min, max; | |
154 | } dot, vco, n, m, m1, m2, p, p1; | |
155 | ||
156 | struct { | |
157 | int dot_limit; | |
158 | int p2_slow, p2_fast; | |
159 | } p2; | |
d4906093 | 160 | }; |
79e53945 | 161 | |
bfa7df01 | 162 | /* returns HPLL frequency in kHz */ |
49cd97a3 | 163 | int vlv_get_hpll_vco(struct drm_i915_private *dev_priv) |
bfa7df01 VS |
164 | { |
165 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
166 | ||
167 | /* Obtain SKU information */ | |
168 | mutex_lock(&dev_priv->sb_lock); | |
169 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
170 | CCK_FUSE_HPLL_FREQ_MASK; | |
171 | mutex_unlock(&dev_priv->sb_lock); | |
172 | ||
173 | return vco_freq[hpll_freq] * 1000; | |
174 | } | |
175 | ||
c30fec65 VS |
176 | int vlv_get_cck_clock(struct drm_i915_private *dev_priv, |
177 | const char *name, u32 reg, int ref_freq) | |
bfa7df01 VS |
178 | { |
179 | u32 val; | |
180 | int divider; | |
181 | ||
bfa7df01 VS |
182 | mutex_lock(&dev_priv->sb_lock); |
183 | val = vlv_cck_read(dev_priv, reg); | |
184 | mutex_unlock(&dev_priv->sb_lock); | |
185 | ||
186 | divider = val & CCK_FREQUENCY_VALUES; | |
187 | ||
188 | WARN((val & CCK_FREQUENCY_STATUS) != | |
189 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
190 | "%s change in progress\n", name); | |
191 | ||
c30fec65 VS |
192 | return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); |
193 | } | |
194 | ||
7ff89ca2 VS |
195 | int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, |
196 | const char *name, u32 reg) | |
c30fec65 VS |
197 | { |
198 | if (dev_priv->hpll_freq == 0) | |
49cd97a3 | 199 | dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); |
c30fec65 VS |
200 | |
201 | return vlv_get_cck_clock(dev_priv, name, reg, | |
202 | dev_priv->hpll_freq); | |
bfa7df01 VS |
203 | } |
204 | ||
bfa7df01 VS |
205 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
206 | { | |
666a4537 | 207 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
bfa7df01 VS |
208 | return; |
209 | ||
210 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
211 | CCK_CZ_CLOCK_CONTROL); | |
212 | ||
213 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); | |
214 | } | |
215 | ||
021357ac | 216 | static inline u32 /* units of 100MHz */ |
21a727b3 VS |
217 | intel_fdi_link_freq(struct drm_i915_private *dev_priv, |
218 | const struct intel_crtc_state *pipe_config) | |
021357ac | 219 | { |
21a727b3 VS |
220 | if (HAS_DDI(dev_priv)) |
221 | return pipe_config->port_clock; /* SPLL */ | |
222 | else if (IS_GEN5(dev_priv)) | |
223 | return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000; | |
e3b247da | 224 | else |
21a727b3 | 225 | return 270000; |
021357ac CW |
226 | } |
227 | ||
1b6f4958 | 228 | static const struct intel_limit intel_limits_i8xx_dac = { |
0206e353 | 229 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 230 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 231 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
232 | .m = { .min = 96, .max = 140 }, |
233 | .m1 = { .min = 18, .max = 26 }, | |
234 | .m2 = { .min = 6, .max = 16 }, | |
235 | .p = { .min = 4, .max = 128 }, | |
236 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
237 | .p2 = { .dot_limit = 165000, |
238 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
239 | }; |
240 | ||
1b6f4958 | 241 | static const struct intel_limit intel_limits_i8xx_dvo = { |
5d536e28 | 242 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 243 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 244 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
245 | .m = { .min = 96, .max = 140 }, |
246 | .m1 = { .min = 18, .max = 26 }, | |
247 | .m2 = { .min = 6, .max = 16 }, | |
248 | .p = { .min = 4, .max = 128 }, | |
249 | .p1 = { .min = 2, .max = 33 }, | |
250 | .p2 = { .dot_limit = 165000, | |
251 | .p2_slow = 4, .p2_fast = 4 }, | |
252 | }; | |
253 | ||
1b6f4958 | 254 | static const struct intel_limit intel_limits_i8xx_lvds = { |
0206e353 | 255 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 256 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 257 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
258 | .m = { .min = 96, .max = 140 }, |
259 | .m1 = { .min = 18, .max = 26 }, | |
260 | .m2 = { .min = 6, .max = 16 }, | |
261 | .p = { .min = 4, .max = 128 }, | |
262 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
263 | .p2 = { .dot_limit = 165000, |
264 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 265 | }; |
273e27ca | 266 | |
1b6f4958 | 267 | static const struct intel_limit intel_limits_i9xx_sdvo = { |
0206e353 AJ |
268 | .dot = { .min = 20000, .max = 400000 }, |
269 | .vco = { .min = 1400000, .max = 2800000 }, | |
270 | .n = { .min = 1, .max = 6 }, | |
271 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
272 | .m1 = { .min = 8, .max = 18 }, |
273 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
274 | .p = { .min = 5, .max = 80 }, |
275 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
276 | .p2 = { .dot_limit = 200000, |
277 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
278 | }; |
279 | ||
1b6f4958 | 280 | static const struct intel_limit intel_limits_i9xx_lvds = { |
0206e353 AJ |
281 | .dot = { .min = 20000, .max = 400000 }, |
282 | .vco = { .min = 1400000, .max = 2800000 }, | |
283 | .n = { .min = 1, .max = 6 }, | |
284 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
285 | .m1 = { .min = 8, .max = 18 }, |
286 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
287 | .p = { .min = 7, .max = 98 }, |
288 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
289 | .p2 = { .dot_limit = 112000, |
290 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
291 | }; |
292 | ||
273e27ca | 293 | |
1b6f4958 | 294 | static const struct intel_limit intel_limits_g4x_sdvo = { |
273e27ca EA |
295 | .dot = { .min = 25000, .max = 270000 }, |
296 | .vco = { .min = 1750000, .max = 3500000}, | |
297 | .n = { .min = 1, .max = 4 }, | |
298 | .m = { .min = 104, .max = 138 }, | |
299 | .m1 = { .min = 17, .max = 23 }, | |
300 | .m2 = { .min = 5, .max = 11 }, | |
301 | .p = { .min = 10, .max = 30 }, | |
302 | .p1 = { .min = 1, .max = 3}, | |
303 | .p2 = { .dot_limit = 270000, | |
304 | .p2_slow = 10, | |
305 | .p2_fast = 10 | |
044c7c41 | 306 | }, |
e4b36699 KP |
307 | }; |
308 | ||
1b6f4958 | 309 | static const struct intel_limit intel_limits_g4x_hdmi = { |
273e27ca EA |
310 | .dot = { .min = 22000, .max = 400000 }, |
311 | .vco = { .min = 1750000, .max = 3500000}, | |
312 | .n = { .min = 1, .max = 4 }, | |
313 | .m = { .min = 104, .max = 138 }, | |
314 | .m1 = { .min = 16, .max = 23 }, | |
315 | .m2 = { .min = 5, .max = 11 }, | |
316 | .p = { .min = 5, .max = 80 }, | |
317 | .p1 = { .min = 1, .max = 8}, | |
318 | .p2 = { .dot_limit = 165000, | |
319 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
320 | }; |
321 | ||
1b6f4958 | 322 | static const struct intel_limit intel_limits_g4x_single_channel_lvds = { |
273e27ca EA |
323 | .dot = { .min = 20000, .max = 115000 }, |
324 | .vco = { .min = 1750000, .max = 3500000 }, | |
325 | .n = { .min = 1, .max = 3 }, | |
326 | .m = { .min = 104, .max = 138 }, | |
327 | .m1 = { .min = 17, .max = 23 }, | |
328 | .m2 = { .min = 5, .max = 11 }, | |
329 | .p = { .min = 28, .max = 112 }, | |
330 | .p1 = { .min = 2, .max = 8 }, | |
331 | .p2 = { .dot_limit = 0, | |
332 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 333 | }, |
e4b36699 KP |
334 | }; |
335 | ||
1b6f4958 | 336 | static const struct intel_limit intel_limits_g4x_dual_channel_lvds = { |
273e27ca EA |
337 | .dot = { .min = 80000, .max = 224000 }, |
338 | .vco = { .min = 1750000, .max = 3500000 }, | |
339 | .n = { .min = 1, .max = 3 }, | |
340 | .m = { .min = 104, .max = 138 }, | |
341 | .m1 = { .min = 17, .max = 23 }, | |
342 | .m2 = { .min = 5, .max = 11 }, | |
343 | .p = { .min = 14, .max = 42 }, | |
344 | .p1 = { .min = 2, .max = 6 }, | |
345 | .p2 = { .dot_limit = 0, | |
346 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 347 | }, |
e4b36699 KP |
348 | }; |
349 | ||
1b6f4958 | 350 | static const struct intel_limit intel_limits_pineview_sdvo = { |
0206e353 AJ |
351 | .dot = { .min = 20000, .max = 400000}, |
352 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 353 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
354 | .n = { .min = 3, .max = 6 }, |
355 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 356 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
357 | .m1 = { .min = 0, .max = 0 }, |
358 | .m2 = { .min = 0, .max = 254 }, | |
359 | .p = { .min = 5, .max = 80 }, | |
360 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
361 | .p2 = { .dot_limit = 200000, |
362 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
363 | }; |
364 | ||
1b6f4958 | 365 | static const struct intel_limit intel_limits_pineview_lvds = { |
0206e353 AJ |
366 | .dot = { .min = 20000, .max = 400000 }, |
367 | .vco = { .min = 1700000, .max = 3500000 }, | |
368 | .n = { .min = 3, .max = 6 }, | |
369 | .m = { .min = 2, .max = 256 }, | |
370 | .m1 = { .min = 0, .max = 0 }, | |
371 | .m2 = { .min = 0, .max = 254 }, | |
372 | .p = { .min = 7, .max = 112 }, | |
373 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
374 | .p2 = { .dot_limit = 112000, |
375 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
376 | }; |
377 | ||
273e27ca EA |
378 | /* Ironlake / Sandybridge |
379 | * | |
380 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
381 | * the range value for them is (actual_value - 2). | |
382 | */ | |
1b6f4958 | 383 | static const struct intel_limit intel_limits_ironlake_dac = { |
273e27ca EA |
384 | .dot = { .min = 25000, .max = 350000 }, |
385 | .vco = { .min = 1760000, .max = 3510000 }, | |
386 | .n = { .min = 1, .max = 5 }, | |
387 | .m = { .min = 79, .max = 127 }, | |
388 | .m1 = { .min = 12, .max = 22 }, | |
389 | .m2 = { .min = 5, .max = 9 }, | |
390 | .p = { .min = 5, .max = 80 }, | |
391 | .p1 = { .min = 1, .max = 8 }, | |
392 | .p2 = { .dot_limit = 225000, | |
393 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
394 | }; |
395 | ||
1b6f4958 | 396 | static const struct intel_limit intel_limits_ironlake_single_lvds = { |
273e27ca EA |
397 | .dot = { .min = 25000, .max = 350000 }, |
398 | .vco = { .min = 1760000, .max = 3510000 }, | |
399 | .n = { .min = 1, .max = 3 }, | |
400 | .m = { .min = 79, .max = 118 }, | |
401 | .m1 = { .min = 12, .max = 22 }, | |
402 | .m2 = { .min = 5, .max = 9 }, | |
403 | .p = { .min = 28, .max = 112 }, | |
404 | .p1 = { .min = 2, .max = 8 }, | |
405 | .p2 = { .dot_limit = 225000, | |
406 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
407 | }; |
408 | ||
1b6f4958 | 409 | static const struct intel_limit intel_limits_ironlake_dual_lvds = { |
273e27ca EA |
410 | .dot = { .min = 25000, .max = 350000 }, |
411 | .vco = { .min = 1760000, .max = 3510000 }, | |
412 | .n = { .min = 1, .max = 3 }, | |
413 | .m = { .min = 79, .max = 127 }, | |
414 | .m1 = { .min = 12, .max = 22 }, | |
415 | .m2 = { .min = 5, .max = 9 }, | |
416 | .p = { .min = 14, .max = 56 }, | |
417 | .p1 = { .min = 2, .max = 8 }, | |
418 | .p2 = { .dot_limit = 225000, | |
419 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
420 | }; |
421 | ||
273e27ca | 422 | /* LVDS 100mhz refclk limits. */ |
1b6f4958 | 423 | static const struct intel_limit intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
424 | .dot = { .min = 25000, .max = 350000 }, |
425 | .vco = { .min = 1760000, .max = 3510000 }, | |
426 | .n = { .min = 1, .max = 2 }, | |
427 | .m = { .min = 79, .max = 126 }, | |
428 | .m1 = { .min = 12, .max = 22 }, | |
429 | .m2 = { .min = 5, .max = 9 }, | |
430 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 431 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
432 | .p2 = { .dot_limit = 225000, |
433 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
434 | }; |
435 | ||
1b6f4958 | 436 | static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = { |
273e27ca EA |
437 | .dot = { .min = 25000, .max = 350000 }, |
438 | .vco = { .min = 1760000, .max = 3510000 }, | |
439 | .n = { .min = 1, .max = 3 }, | |
440 | .m = { .min = 79, .max = 126 }, | |
441 | .m1 = { .min = 12, .max = 22 }, | |
442 | .m2 = { .min = 5, .max = 9 }, | |
443 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 444 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
445 | .p2 = { .dot_limit = 225000, |
446 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
447 | }; |
448 | ||
1b6f4958 | 449 | static const struct intel_limit intel_limits_vlv = { |
f01b7962 VS |
450 | /* |
451 | * These are the data rate limits (measured in fast clocks) | |
452 | * since those are the strictest limits we have. The fast | |
453 | * clock and actual rate limits are more relaxed, so checking | |
454 | * them would make no difference. | |
455 | */ | |
456 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 457 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 458 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
459 | .m1 = { .min = 2, .max = 3 }, |
460 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 461 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 462 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
463 | }; |
464 | ||
1b6f4958 | 465 | static const struct intel_limit intel_limits_chv = { |
ef9348c8 CML |
466 | /* |
467 | * These are the data rate limits (measured in fast clocks) | |
468 | * since those are the strictest limits we have. The fast | |
469 | * clock and actual rate limits are more relaxed, so checking | |
470 | * them would make no difference. | |
471 | */ | |
472 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 473 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
474 | .n = { .min = 1, .max = 1 }, |
475 | .m1 = { .min = 2, .max = 2 }, | |
476 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
477 | .p1 = { .min = 2, .max = 4 }, | |
478 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
479 | }; | |
480 | ||
1b6f4958 | 481 | static const struct intel_limit intel_limits_bxt = { |
5ab7b0b7 ID |
482 | /* FIXME: find real dot limits */ |
483 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 484 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
485 | .n = { .min = 1, .max = 1 }, |
486 | .m1 = { .min = 2, .max = 2 }, | |
487 | /* FIXME: find real m2 limits */ | |
488 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
489 | .p1 = { .min = 2, .max = 4 }, | |
490 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
491 | }; | |
492 | ||
cdba954e ACO |
493 | static bool |
494 | needs_modeset(struct drm_crtc_state *state) | |
495 | { | |
fc596660 | 496 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
497 | } |
498 | ||
dccbea3b ID |
499 | /* |
500 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
501 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
502 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
503 | * The helpers' return value is the rate of the clock that is fed to the | |
504 | * display engine's pipe which can be the above fast dot clock rate or a | |
505 | * divided-down version of it. | |
506 | */ | |
f2b115e6 | 507 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
9e2c8475 | 508 | static int pnv_calc_dpll_params(int refclk, struct dpll *clock) |
79e53945 | 509 | { |
2177832f SL |
510 | clock->m = clock->m2 + 2; |
511 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 512 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 513 | return 0; |
fb03ac01 VS |
514 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
515 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
516 | |
517 | return clock->dot; | |
2177832f SL |
518 | } |
519 | ||
7429e9d4 DV |
520 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
521 | { | |
522 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
523 | } | |
524 | ||
9e2c8475 | 525 | static int i9xx_calc_dpll_params(int refclk, struct dpll *clock) |
2177832f | 526 | { |
7429e9d4 | 527 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 528 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 529 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 530 | return 0; |
fb03ac01 VS |
531 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
532 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
533 | |
534 | return clock->dot; | |
79e53945 JB |
535 | } |
536 | ||
9e2c8475 | 537 | static int vlv_calc_dpll_params(int refclk, struct dpll *clock) |
589eca67 ID |
538 | { |
539 | clock->m = clock->m1 * clock->m2; | |
540 | clock->p = clock->p1 * clock->p2; | |
541 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 542 | return 0; |
589eca67 ID |
543 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
544 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
545 | |
546 | return clock->dot / 5; | |
589eca67 ID |
547 | } |
548 | ||
9e2c8475 | 549 | int chv_calc_dpll_params(int refclk, struct dpll *clock) |
ef9348c8 CML |
550 | { |
551 | clock->m = clock->m1 * clock->m2; | |
552 | clock->p = clock->p1 * clock->p2; | |
553 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 554 | return 0; |
ef9348c8 CML |
555 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
556 | clock->n << 22); | |
557 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
558 | |
559 | return clock->dot / 5; | |
ef9348c8 CML |
560 | } |
561 | ||
7c04d1d9 | 562 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
563 | /** |
564 | * Returns whether the given set of divisors are valid for a given refclk with | |
565 | * the given connectors. | |
566 | */ | |
567 | ||
e2d214ae | 568 | static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv, |
1b6f4958 | 569 | const struct intel_limit *limit, |
9e2c8475 | 570 | const struct dpll *clock) |
79e53945 | 571 | { |
f01b7962 VS |
572 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
573 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 574 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 575 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 576 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 577 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 578 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 579 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 580 | |
e2d214ae | 581 | if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) && |
cc3f90f0 | 582 | !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv)) |
f01b7962 VS |
583 | if (clock->m1 <= clock->m2) |
584 | INTELPllInvalid("m1 <= m2\n"); | |
585 | ||
e2d214ae | 586 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
cc3f90f0 | 587 | !IS_GEN9_LP(dev_priv)) { |
f01b7962 VS |
588 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
589 | INTELPllInvalid("p out of range\n"); | |
590 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
591 | INTELPllInvalid("m out of range\n"); | |
592 | } | |
593 | ||
79e53945 | 594 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 595 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
596 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
597 | * connector, etc., rather than just a single range. | |
598 | */ | |
599 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 600 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
601 | |
602 | return true; | |
603 | } | |
604 | ||
3b1429d9 | 605 | static int |
1b6f4958 | 606 | i9xx_select_p2_div(const struct intel_limit *limit, |
3b1429d9 VS |
607 | const struct intel_crtc_state *crtc_state, |
608 | int target) | |
79e53945 | 609 | { |
3b1429d9 | 610 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 611 | |
2d84d2b3 | 612 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 613 | /* |
a210b028 DV |
614 | * For LVDS just rely on its current settings for dual-channel. |
615 | * We haven't figured out how to reliably set up different | |
616 | * single/dual channel state, if we even can. | |
79e53945 | 617 | */ |
1974cad0 | 618 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 619 | return limit->p2.p2_fast; |
79e53945 | 620 | else |
3b1429d9 | 621 | return limit->p2.p2_slow; |
79e53945 JB |
622 | } else { |
623 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 624 | return limit->p2.p2_slow; |
79e53945 | 625 | else |
3b1429d9 | 626 | return limit->p2.p2_fast; |
79e53945 | 627 | } |
3b1429d9 VS |
628 | } |
629 | ||
70e8aa21 ACO |
630 | /* |
631 | * Returns a set of divisors for the desired target clock with the given | |
632 | * refclk, or FALSE. The returned values represent the clock equation: | |
633 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
634 | * | |
635 | * Target and reference clocks are specified in kHz. | |
636 | * | |
637 | * If match_clock is provided, then best_clock P divider must match the P | |
638 | * divider from @match_clock used for LVDS downclocking. | |
639 | */ | |
3b1429d9 | 640 | static bool |
1b6f4958 | 641 | i9xx_find_best_dpll(const struct intel_limit *limit, |
3b1429d9 | 642 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
643 | int target, int refclk, struct dpll *match_clock, |
644 | struct dpll *best_clock) | |
3b1429d9 VS |
645 | { |
646 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
9e2c8475 | 647 | struct dpll clock; |
3b1429d9 | 648 | int err = target; |
79e53945 | 649 | |
0206e353 | 650 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 651 | |
3b1429d9 VS |
652 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
653 | ||
42158660 ZY |
654 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
655 | clock.m1++) { | |
656 | for (clock.m2 = limit->m2.min; | |
657 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 658 | if (clock.m2 >= clock.m1) |
42158660 ZY |
659 | break; |
660 | for (clock.n = limit->n.min; | |
661 | clock.n <= limit->n.max; clock.n++) { | |
662 | for (clock.p1 = limit->p1.min; | |
663 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
664 | int this_err; |
665 | ||
dccbea3b | 666 | i9xx_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
667 | if (!intel_PLL_is_valid(to_i915(dev), |
668 | limit, | |
ac58c3f0 DV |
669 | &clock)) |
670 | continue; | |
671 | if (match_clock && | |
672 | clock.p != match_clock->p) | |
673 | continue; | |
674 | ||
675 | this_err = abs(clock.dot - target); | |
676 | if (this_err < err) { | |
677 | *best_clock = clock; | |
678 | err = this_err; | |
679 | } | |
680 | } | |
681 | } | |
682 | } | |
683 | } | |
684 | ||
685 | return (err != target); | |
686 | } | |
687 | ||
70e8aa21 ACO |
688 | /* |
689 | * Returns a set of divisors for the desired target clock with the given | |
690 | * refclk, or FALSE. The returned values represent the clock equation: | |
691 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
692 | * | |
693 | * Target and reference clocks are specified in kHz. | |
694 | * | |
695 | * If match_clock is provided, then best_clock P divider must match the P | |
696 | * divider from @match_clock used for LVDS downclocking. | |
697 | */ | |
ac58c3f0 | 698 | static bool |
1b6f4958 | 699 | pnv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 700 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
701 | int target, int refclk, struct dpll *match_clock, |
702 | struct dpll *best_clock) | |
79e53945 | 703 | { |
3b1429d9 | 704 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 705 | struct dpll clock; |
79e53945 JB |
706 | int err = target; |
707 | ||
0206e353 | 708 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 709 | |
3b1429d9 VS |
710 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
711 | ||
42158660 ZY |
712 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
713 | clock.m1++) { | |
714 | for (clock.m2 = limit->m2.min; | |
715 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
716 | for (clock.n = limit->n.min; |
717 | clock.n <= limit->n.max; clock.n++) { | |
718 | for (clock.p1 = limit->p1.min; | |
719 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
720 | int this_err; |
721 | ||
dccbea3b | 722 | pnv_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
723 | if (!intel_PLL_is_valid(to_i915(dev), |
724 | limit, | |
1b894b59 | 725 | &clock)) |
79e53945 | 726 | continue; |
cec2f356 SP |
727 | if (match_clock && |
728 | clock.p != match_clock->p) | |
729 | continue; | |
79e53945 JB |
730 | |
731 | this_err = abs(clock.dot - target); | |
732 | if (this_err < err) { | |
733 | *best_clock = clock; | |
734 | err = this_err; | |
735 | } | |
736 | } | |
737 | } | |
738 | } | |
739 | } | |
740 | ||
741 | return (err != target); | |
742 | } | |
743 | ||
997c030c ACO |
744 | /* |
745 | * Returns a set of divisors for the desired target clock with the given | |
746 | * refclk, or FALSE. The returned values represent the clock equation: | |
747 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
70e8aa21 ACO |
748 | * |
749 | * Target and reference clocks are specified in kHz. | |
750 | * | |
751 | * If match_clock is provided, then best_clock P divider must match the P | |
752 | * divider from @match_clock used for LVDS downclocking. | |
997c030c | 753 | */ |
d4906093 | 754 | static bool |
1b6f4958 | 755 | g4x_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 756 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
757 | int target, int refclk, struct dpll *match_clock, |
758 | struct dpll *best_clock) | |
d4906093 | 759 | { |
3b1429d9 | 760 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 761 | struct dpll clock; |
d4906093 | 762 | int max_n; |
3b1429d9 | 763 | bool found = false; |
6ba770dc AJ |
764 | /* approximately equals target * 0.00585 */ |
765 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
766 | |
767 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
768 | |
769 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
770 | ||
d4906093 | 771 | max_n = limit->n.max; |
f77f13e2 | 772 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 773 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 774 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
775 | for (clock.m1 = limit->m1.max; |
776 | clock.m1 >= limit->m1.min; clock.m1--) { | |
777 | for (clock.m2 = limit->m2.max; | |
778 | clock.m2 >= limit->m2.min; clock.m2--) { | |
779 | for (clock.p1 = limit->p1.max; | |
780 | clock.p1 >= limit->p1.min; clock.p1--) { | |
781 | int this_err; | |
782 | ||
dccbea3b | 783 | i9xx_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
784 | if (!intel_PLL_is_valid(to_i915(dev), |
785 | limit, | |
1b894b59 | 786 | &clock)) |
d4906093 | 787 | continue; |
1b894b59 CW |
788 | |
789 | this_err = abs(clock.dot - target); | |
d4906093 ML |
790 | if (this_err < err_most) { |
791 | *best_clock = clock; | |
792 | err_most = this_err; | |
793 | max_n = clock.n; | |
794 | found = true; | |
795 | } | |
796 | } | |
797 | } | |
798 | } | |
799 | } | |
2c07245f ZW |
800 | return found; |
801 | } | |
802 | ||
d5dd62bd ID |
803 | /* |
804 | * Check if the calculated PLL configuration is more optimal compared to the | |
805 | * best configuration and error found so far. Return the calculated error. | |
806 | */ | |
807 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
9e2c8475 ACO |
808 | const struct dpll *calculated_clock, |
809 | const struct dpll *best_clock, | |
d5dd62bd ID |
810 | unsigned int best_error_ppm, |
811 | unsigned int *error_ppm) | |
812 | { | |
9ca3ba01 ID |
813 | /* |
814 | * For CHV ignore the error and consider only the P value. | |
815 | * Prefer a bigger P value based on HW requirements. | |
816 | */ | |
920a14b2 | 817 | if (IS_CHERRYVIEW(to_i915(dev))) { |
9ca3ba01 ID |
818 | *error_ppm = 0; |
819 | ||
820 | return calculated_clock->p > best_clock->p; | |
821 | } | |
822 | ||
24be4e46 ID |
823 | if (WARN_ON_ONCE(!target_freq)) |
824 | return false; | |
825 | ||
d5dd62bd ID |
826 | *error_ppm = div_u64(1000000ULL * |
827 | abs(target_freq - calculated_clock->dot), | |
828 | target_freq); | |
829 | /* | |
830 | * Prefer a better P value over a better (smaller) error if the error | |
831 | * is small. Ensure this preference for future configurations too by | |
832 | * setting the error to 0. | |
833 | */ | |
834 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
835 | *error_ppm = 0; | |
836 | ||
837 | return true; | |
838 | } | |
839 | ||
840 | return *error_ppm + 10 < best_error_ppm; | |
841 | } | |
842 | ||
65b3d6a9 ACO |
843 | /* |
844 | * Returns a set of divisors for the desired target clock with the given | |
845 | * refclk, or FALSE. The returned values represent the clock equation: | |
846 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
847 | */ | |
a0c4da24 | 848 | static bool |
1b6f4958 | 849 | vlv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 850 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
851 | int target, int refclk, struct dpll *match_clock, |
852 | struct dpll *best_clock) | |
a0c4da24 | 853 | { |
a93e255f | 854 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 855 | struct drm_device *dev = crtc->base.dev; |
9e2c8475 | 856 | struct dpll clock; |
69e4f900 | 857 | unsigned int bestppm = 1000000; |
27e639bf VS |
858 | /* min update 19.2 MHz */ |
859 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 860 | bool found = false; |
a0c4da24 | 861 | |
6b4bf1c4 VS |
862 | target *= 5; /* fast clock */ |
863 | ||
864 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
865 | |
866 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 867 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 868 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 869 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 870 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 871 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 872 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 873 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 874 | unsigned int ppm; |
69e4f900 | 875 | |
6b4bf1c4 VS |
876 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
877 | refclk * clock.m1); | |
878 | ||
dccbea3b | 879 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 880 | |
e2d214ae TU |
881 | if (!intel_PLL_is_valid(to_i915(dev), |
882 | limit, | |
f01b7962 | 883 | &clock)) |
43b0ac53 VS |
884 | continue; |
885 | ||
d5dd62bd ID |
886 | if (!vlv_PLL_is_optimal(dev, target, |
887 | &clock, | |
888 | best_clock, | |
889 | bestppm, &ppm)) | |
890 | continue; | |
6b4bf1c4 | 891 | |
d5dd62bd ID |
892 | *best_clock = clock; |
893 | bestppm = ppm; | |
894 | found = true; | |
a0c4da24 JB |
895 | } |
896 | } | |
897 | } | |
898 | } | |
a0c4da24 | 899 | |
49e497ef | 900 | return found; |
a0c4da24 | 901 | } |
a4fc5ed6 | 902 | |
65b3d6a9 ACO |
903 | /* |
904 | * Returns a set of divisors for the desired target clock with the given | |
905 | * refclk, or FALSE. The returned values represent the clock equation: | |
906 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
907 | */ | |
ef9348c8 | 908 | static bool |
1b6f4958 | 909 | chv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 910 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
911 | int target, int refclk, struct dpll *match_clock, |
912 | struct dpll *best_clock) | |
ef9348c8 | 913 | { |
a93e255f | 914 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 915 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 916 | unsigned int best_error_ppm; |
9e2c8475 | 917 | struct dpll clock; |
ef9348c8 CML |
918 | uint64_t m2; |
919 | int found = false; | |
920 | ||
921 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 922 | best_error_ppm = 1000000; |
ef9348c8 CML |
923 | |
924 | /* | |
925 | * Based on hardware doc, the n always set to 1, and m1 always | |
926 | * set to 2. If requires to support 200Mhz refclk, we need to | |
927 | * revisit this because n may not 1 anymore. | |
928 | */ | |
929 | clock.n = 1, clock.m1 = 2; | |
930 | target *= 5; /* fast clock */ | |
931 | ||
932 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
933 | for (clock.p2 = limit->p2.p2_fast; | |
934 | clock.p2 >= limit->p2.p2_slow; | |
935 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 936 | unsigned int error_ppm; |
ef9348c8 CML |
937 | |
938 | clock.p = clock.p1 * clock.p2; | |
939 | ||
940 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
941 | clock.n) << 22, refclk * clock.m1); | |
942 | ||
943 | if (m2 > INT_MAX/clock.m1) | |
944 | continue; | |
945 | ||
946 | clock.m2 = m2; | |
947 | ||
dccbea3b | 948 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 | 949 | |
e2d214ae | 950 | if (!intel_PLL_is_valid(to_i915(dev), limit, &clock)) |
ef9348c8 CML |
951 | continue; |
952 | ||
9ca3ba01 ID |
953 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
954 | best_error_ppm, &error_ppm)) | |
955 | continue; | |
956 | ||
957 | *best_clock = clock; | |
958 | best_error_ppm = error_ppm; | |
959 | found = true; | |
ef9348c8 CML |
960 | } |
961 | } | |
962 | ||
963 | return found; | |
964 | } | |
965 | ||
5ab7b0b7 | 966 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
9e2c8475 | 967 | struct dpll *best_clock) |
5ab7b0b7 | 968 | { |
65b3d6a9 | 969 | int refclk = 100000; |
1b6f4958 | 970 | const struct intel_limit *limit = &intel_limits_bxt; |
5ab7b0b7 | 971 | |
65b3d6a9 | 972 | return chv_find_best_dpll(limit, crtc_state, |
5ab7b0b7 ID |
973 | target_clock, refclk, NULL, best_clock); |
974 | } | |
975 | ||
525b9311 | 976 | bool intel_crtc_active(struct intel_crtc *crtc) |
20ddf665 | 977 | { |
20ddf665 VS |
978 | /* Be paranoid as we can arrive here with only partial |
979 | * state retrieved from the hardware during setup. | |
980 | * | |
241bfc38 | 981 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
982 | * as Haswell has gained clock readout/fastboot support. |
983 | * | |
66e514c1 | 984 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 985 | * properly reconstruct framebuffers. |
c3d1f436 MR |
986 | * |
987 | * FIXME: The intel_crtc->active here should be switched to | |
988 | * crtc->state->active once we have proper CRTC states wired up | |
989 | * for atomic. | |
20ddf665 | 990 | */ |
525b9311 VS |
991 | return crtc->active && crtc->base.primary->state->fb && |
992 | crtc->config->base.adjusted_mode.crtc_clock; | |
20ddf665 VS |
993 | } |
994 | ||
a5c961d1 PZ |
995 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
996 | enum pipe pipe) | |
997 | { | |
98187836 | 998 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
a5c961d1 | 999 | |
e2af48c6 | 1000 | return crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1001 | } |
1002 | ||
6315b5d3 | 1003 | static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe) |
fbf49ea2 | 1004 | { |
f0f59a00 | 1005 | i915_reg_t reg = PIPEDSL(pipe); |
fbf49ea2 VS |
1006 | u32 line1, line2; |
1007 | u32 line_mask; | |
1008 | ||
5db94019 | 1009 | if (IS_GEN2(dev_priv)) |
fbf49ea2 VS |
1010 | line_mask = DSL_LINEMASK_GEN2; |
1011 | else | |
1012 | line_mask = DSL_LINEMASK_GEN3; | |
1013 | ||
1014 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 1015 | msleep(5); |
fbf49ea2 VS |
1016 | line2 = I915_READ(reg) & line_mask; |
1017 | ||
1018 | return line1 == line2; | |
1019 | } | |
1020 | ||
ab7ad7f6 KP |
1021 | /* |
1022 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1023 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1024 | * |
1025 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1026 | * spinning on the vblank interrupt status bit, since we won't actually | |
1027 | * see an interrupt when the pipe is disabled. | |
1028 | * | |
ab7ad7f6 KP |
1029 | * On Gen4 and above: |
1030 | * wait for the pipe register state bit to turn off | |
1031 | * | |
1032 | * Otherwise: | |
1033 | * wait for the display line value to settle (it usually | |
1034 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1035 | * |
9d0498a2 | 1036 | */ |
575f7ab7 | 1037 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1038 | { |
6315b5d3 | 1039 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6e3c9717 | 1040 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1041 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 | 1042 | |
6315b5d3 | 1043 | if (INTEL_GEN(dev_priv) >= 4) { |
f0f59a00 | 1044 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1045 | |
1046 | /* Wait for the Pipe State to go off */ | |
b8511f53 CW |
1047 | if (intel_wait_for_register(dev_priv, |
1048 | reg, I965_PIPECONF_ACTIVE, 0, | |
1049 | 100)) | |
284637d9 | 1050 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1051 | } else { |
ab7ad7f6 | 1052 | /* Wait for the display line to settle */ |
6315b5d3 | 1053 | if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100)) |
284637d9 | 1054 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1055 | } |
79e53945 JB |
1056 | } |
1057 | ||
b24e7179 | 1058 | /* Only for pre-ILK configs */ |
55607e8a DV |
1059 | void assert_pll(struct drm_i915_private *dev_priv, |
1060 | enum pipe pipe, bool state) | |
b24e7179 | 1061 | { |
b24e7179 JB |
1062 | u32 val; |
1063 | bool cur_state; | |
1064 | ||
649636ef | 1065 | val = I915_READ(DPLL(pipe)); |
b24e7179 | 1066 | cur_state = !!(val & DPLL_VCO_ENABLE); |
e2c719b7 | 1067 | I915_STATE_WARN(cur_state != state, |
b24e7179 | 1068 | "PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1069 | onoff(state), onoff(cur_state)); |
b24e7179 | 1070 | } |
b24e7179 | 1071 | |
23538ef1 | 1072 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
8563b1e8 | 1073 | void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) |
23538ef1 JN |
1074 | { |
1075 | u32 val; | |
1076 | bool cur_state; | |
1077 | ||
a580516d | 1078 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1079 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1080 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1081 | |
1082 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1083 | I915_STATE_WARN(cur_state != state, |
23538ef1 | 1084 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1085 | onoff(state), onoff(cur_state)); |
23538ef1 | 1086 | } |
23538ef1 | 1087 | |
040484af JB |
1088 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
1089 | enum pipe pipe, bool state) | |
1090 | { | |
040484af | 1091 | bool cur_state; |
ad80a810 PZ |
1092 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1093 | pipe); | |
040484af | 1094 | |
2d1fe073 | 1095 | if (HAS_DDI(dev_priv)) { |
affa9354 | 1096 | /* DDI does not have a specific FDI_TX register */ |
649636ef | 1097 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
ad80a810 | 1098 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 | 1099 | } else { |
649636ef | 1100 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
bf507ef7 ED |
1101 | cur_state = !!(val & FDI_TX_ENABLE); |
1102 | } | |
e2c719b7 | 1103 | I915_STATE_WARN(cur_state != state, |
040484af | 1104 | "FDI TX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1105 | onoff(state), onoff(cur_state)); |
040484af JB |
1106 | } |
1107 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1108 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1109 | ||
1110 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1111 | enum pipe pipe, bool state) | |
1112 | { | |
040484af JB |
1113 | u32 val; |
1114 | bool cur_state; | |
1115 | ||
649636ef | 1116 | val = I915_READ(FDI_RX_CTL(pipe)); |
d63fa0dc | 1117 | cur_state = !!(val & FDI_RX_ENABLE); |
e2c719b7 | 1118 | I915_STATE_WARN(cur_state != state, |
040484af | 1119 | "FDI RX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1120 | onoff(state), onoff(cur_state)); |
040484af JB |
1121 | } |
1122 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1123 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1124 | ||
1125 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1126 | enum pipe pipe) | |
1127 | { | |
040484af JB |
1128 | u32 val; |
1129 | ||
1130 | /* ILK FDI PLL is always enabled */ | |
7e22dbbb | 1131 | if (IS_GEN5(dev_priv)) |
040484af JB |
1132 | return; |
1133 | ||
bf507ef7 | 1134 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
2d1fe073 | 1135 | if (HAS_DDI(dev_priv)) |
bf507ef7 ED |
1136 | return; |
1137 | ||
649636ef | 1138 | val = I915_READ(FDI_TX_CTL(pipe)); |
e2c719b7 | 1139 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1140 | } |
1141 | ||
55607e8a DV |
1142 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1143 | enum pipe pipe, bool state) | |
040484af | 1144 | { |
040484af | 1145 | u32 val; |
55607e8a | 1146 | bool cur_state; |
040484af | 1147 | |
649636ef | 1148 | val = I915_READ(FDI_RX_CTL(pipe)); |
55607e8a | 1149 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1150 | I915_STATE_WARN(cur_state != state, |
55607e8a | 1151 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
87ad3212 | 1152 | onoff(state), onoff(cur_state)); |
040484af JB |
1153 | } |
1154 | ||
4f8036a2 | 1155 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe) |
ea0760cf | 1156 | { |
f0f59a00 | 1157 | i915_reg_t pp_reg; |
ea0760cf JB |
1158 | u32 val; |
1159 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1160 | bool locked = true; |
ea0760cf | 1161 | |
4f8036a2 | 1162 | if (WARN_ON(HAS_DDI(dev_priv))) |
bedd4dba JN |
1163 | return; |
1164 | ||
4f8036a2 | 1165 | if (HAS_PCH_SPLIT(dev_priv)) { |
bedd4dba JN |
1166 | u32 port_sel; |
1167 | ||
44cb734c ID |
1168 | pp_reg = PP_CONTROL(0); |
1169 | port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; | |
bedd4dba JN |
1170 | |
1171 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1172 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1173 | panel_pipe = PIPE_B; | |
1174 | /* XXX: else fix for eDP */ | |
4f8036a2 | 1175 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
bedd4dba | 1176 | /* presumably write lock depends on pipe, not port select */ |
44cb734c | 1177 | pp_reg = PP_CONTROL(pipe); |
bedd4dba | 1178 | panel_pipe = pipe; |
ea0760cf | 1179 | } else { |
44cb734c | 1180 | pp_reg = PP_CONTROL(0); |
bedd4dba JN |
1181 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1182 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1183 | } |
1184 | ||
1185 | val = I915_READ(pp_reg); | |
1186 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1187 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1188 | locked = false; |
1189 | ||
e2c719b7 | 1190 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1191 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1192 | pipe_name(pipe)); |
ea0760cf JB |
1193 | } |
1194 | ||
93ce0ba6 JN |
1195 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1196 | enum pipe pipe, bool state) | |
1197 | { | |
93ce0ba6 JN |
1198 | bool cur_state; |
1199 | ||
2a307c2e | 1200 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) |
0b87c24e | 1201 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
d9d82081 | 1202 | else |
5efb3e28 | 1203 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1204 | |
e2c719b7 | 1205 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 | 1206 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1207 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
93ce0ba6 JN |
1208 | } |
1209 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1210 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1211 | ||
b840d907 JB |
1212 | void assert_pipe(struct drm_i915_private *dev_priv, |
1213 | enum pipe pipe, bool state) | |
b24e7179 | 1214 | { |
63d7bbe9 | 1215 | bool cur_state; |
702e7a56 PZ |
1216 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1217 | pipe); | |
4feed0eb | 1218 | enum intel_display_power_domain power_domain; |
b24e7179 | 1219 | |
e56134bc VS |
1220 | /* we keep both pipes enabled on 830 */ |
1221 | if (IS_I830(dev_priv)) | |
8e636784 DV |
1222 | state = true; |
1223 | ||
4feed0eb ID |
1224 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); |
1225 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
649636ef | 1226 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
69310161 | 1227 | cur_state = !!(val & PIPECONF_ENABLE); |
4feed0eb ID |
1228 | |
1229 | intel_display_power_put(dev_priv, power_domain); | |
1230 | } else { | |
1231 | cur_state = false; | |
69310161 PZ |
1232 | } |
1233 | ||
e2c719b7 | 1234 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1235 | "pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1236 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1237 | } |
1238 | ||
931872fc CW |
1239 | static void assert_plane(struct drm_i915_private *dev_priv, |
1240 | enum plane plane, bool state) | |
b24e7179 | 1241 | { |
b24e7179 | 1242 | u32 val; |
931872fc | 1243 | bool cur_state; |
b24e7179 | 1244 | |
649636ef | 1245 | val = I915_READ(DSPCNTR(plane)); |
931872fc | 1246 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1247 | I915_STATE_WARN(cur_state != state, |
931872fc | 1248 | "plane %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1249 | plane_name(plane), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1250 | } |
1251 | ||
931872fc CW |
1252 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1253 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1254 | ||
b24e7179 JB |
1255 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1256 | enum pipe pipe) | |
1257 | { | |
649636ef | 1258 | int i; |
b24e7179 | 1259 | |
653e1026 | 1260 | /* Primary planes are fixed to pipes on gen4+ */ |
6315b5d3 | 1261 | if (INTEL_GEN(dev_priv) >= 4) { |
649636ef | 1262 | u32 val = I915_READ(DSPCNTR(pipe)); |
e2c719b7 | 1263 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1264 | "plane %c assertion failure, should be disabled but not\n", |
1265 | plane_name(pipe)); | |
19ec1358 | 1266 | return; |
28c05794 | 1267 | } |
19ec1358 | 1268 | |
b24e7179 | 1269 | /* Need to check both planes against the pipe */ |
055e393f | 1270 | for_each_pipe(dev_priv, i) { |
649636ef VS |
1271 | u32 val = I915_READ(DSPCNTR(i)); |
1272 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
b24e7179 | 1273 | DISPPLANE_SEL_PIPE_SHIFT; |
e2c719b7 | 1274 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1275 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1276 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1277 | } |
1278 | } | |
1279 | ||
19332d7a JB |
1280 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1281 | enum pipe pipe) | |
1282 | { | |
649636ef | 1283 | int sprite; |
19332d7a | 1284 | |
6315b5d3 | 1285 | if (INTEL_GEN(dev_priv) >= 9) { |
3bdcfc0c | 1286 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1287 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1288 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1289 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1290 | sprite, pipe_name(pipe)); | |
1291 | } | |
920a14b2 | 1292 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
3bdcfc0c | 1293 | for_each_sprite(dev_priv, pipe, sprite) { |
83c04a62 | 1294 | u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite)); |
e2c719b7 | 1295 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1296 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1297 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef | 1298 | } |
6315b5d3 | 1299 | } else if (INTEL_GEN(dev_priv) >= 7) { |
649636ef | 1300 | u32 val = I915_READ(SPRCTL(pipe)); |
e2c719b7 | 1301 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1302 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1303 | plane_name(pipe), pipe_name(pipe)); |
ab33081a | 1304 | } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) { |
649636ef | 1305 | u32 val = I915_READ(DVSCNTR(pipe)); |
e2c719b7 | 1306 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1307 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1308 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1309 | } |
1310 | } | |
1311 | ||
08c71e5e VS |
1312 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1313 | { | |
e2c719b7 | 1314 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1315 | drm_crtc_vblank_put(crtc); |
1316 | } | |
1317 | ||
7abd4b35 ACO |
1318 | void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1319 | enum pipe pipe) | |
92f2584a | 1320 | { |
92f2584a JB |
1321 | u32 val; |
1322 | bool enabled; | |
1323 | ||
649636ef | 1324 | val = I915_READ(PCH_TRANSCONF(pipe)); |
92f2584a | 1325 | enabled = !!(val & TRANS_ENABLE); |
e2c719b7 | 1326 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1327 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1328 | pipe_name(pipe)); | |
92f2584a JB |
1329 | } |
1330 | ||
4e634389 KP |
1331 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1332 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1333 | { |
1334 | if ((val & DP_PORT_EN) == 0) | |
1335 | return false; | |
1336 | ||
2d1fe073 | 1337 | if (HAS_PCH_CPT(dev_priv)) { |
f0f59a00 | 1338 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
f0575e92 KP |
1339 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1340 | return false; | |
2d1fe073 | 1341 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1342 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) |
1343 | return false; | |
f0575e92 KP |
1344 | } else { |
1345 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1346 | return false; | |
1347 | } | |
1348 | return true; | |
1349 | } | |
1350 | ||
1519b995 KP |
1351 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1352 | enum pipe pipe, u32 val) | |
1353 | { | |
dc0fa718 | 1354 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1355 | return false; |
1356 | ||
2d1fe073 | 1357 | if (HAS_PCH_CPT(dev_priv)) { |
dc0fa718 | 1358 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1359 | return false; |
2d1fe073 | 1360 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1361 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) |
1362 | return false; | |
1519b995 | 1363 | } else { |
dc0fa718 | 1364 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1365 | return false; |
1366 | } | |
1367 | return true; | |
1368 | } | |
1369 | ||
1370 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1371 | enum pipe pipe, u32 val) | |
1372 | { | |
1373 | if ((val & LVDS_PORT_EN) == 0) | |
1374 | return false; | |
1375 | ||
2d1fe073 | 1376 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1377 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1378 | return false; | |
1379 | } else { | |
1380 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1381 | return false; | |
1382 | } | |
1383 | return true; | |
1384 | } | |
1385 | ||
1386 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1387 | enum pipe pipe, u32 val) | |
1388 | { | |
1389 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1390 | return false; | |
2d1fe073 | 1391 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1392 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1393 | return false; | |
1394 | } else { | |
1395 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1396 | return false; | |
1397 | } | |
1398 | return true; | |
1399 | } | |
1400 | ||
291906f1 | 1401 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
1402 | enum pipe pipe, i915_reg_t reg, |
1403 | u32 port_sel) | |
291906f1 | 1404 | { |
47a05eca | 1405 | u32 val = I915_READ(reg); |
e2c719b7 | 1406 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1407 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1408 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1409 | |
2d1fe073 | 1410 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1411 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1412 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1413 | } |
1414 | ||
1415 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
f0f59a00 | 1416 | enum pipe pipe, i915_reg_t reg) |
291906f1 | 1417 | { |
47a05eca | 1418 | u32 val = I915_READ(reg); |
e2c719b7 | 1419 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1420 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1421 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1422 | |
2d1fe073 | 1423 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1424 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1425 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1426 | } |
1427 | ||
1428 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1429 | enum pipe pipe) | |
1430 | { | |
291906f1 | 1431 | u32 val; |
291906f1 | 1432 | |
f0575e92 KP |
1433 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1434 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1435 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 | 1436 | |
649636ef | 1437 | val = I915_READ(PCH_ADPA); |
e2c719b7 | 1438 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1439 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1440 | pipe_name(pipe)); |
291906f1 | 1441 | |
649636ef | 1442 | val = I915_READ(PCH_LVDS); |
e2c719b7 | 1443 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1444 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1445 | pipe_name(pipe)); |
291906f1 | 1446 | |
e2debe91 PZ |
1447 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1448 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1449 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1450 | } |
1451 | ||
cd2d34d9 VS |
1452 | static void _vlv_enable_pll(struct intel_crtc *crtc, |
1453 | const struct intel_crtc_state *pipe_config) | |
1454 | { | |
1455 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1456 | enum pipe pipe = crtc->pipe; | |
1457 | ||
1458 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); | |
1459 | POSTING_READ(DPLL(pipe)); | |
1460 | udelay(150); | |
1461 | ||
2c30b43b CW |
1462 | if (intel_wait_for_register(dev_priv, |
1463 | DPLL(pipe), | |
1464 | DPLL_LOCK_VLV, | |
1465 | DPLL_LOCK_VLV, | |
1466 | 1)) | |
cd2d34d9 VS |
1467 | DRM_ERROR("DPLL %d failed to lock\n", pipe); |
1468 | } | |
1469 | ||
d288f65f | 1470 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1471 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1472 | { |
cd2d34d9 | 1473 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1474 | enum pipe pipe = crtc->pipe; |
87442f73 | 1475 | |
8bd3f301 | 1476 | assert_pipe_disabled(dev_priv, pipe); |
87442f73 | 1477 | |
87442f73 | 1478 | /* PLL is protected by panel, make sure we can write it */ |
7d1a83cb | 1479 | assert_panel_unlocked(dev_priv, pipe); |
87442f73 | 1480 | |
cd2d34d9 VS |
1481 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) |
1482 | _vlv_enable_pll(crtc, pipe_config); | |
426115cf | 1483 | |
8bd3f301 VS |
1484 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
1485 | POSTING_READ(DPLL_MD(pipe)); | |
87442f73 DV |
1486 | } |
1487 | ||
cd2d34d9 VS |
1488 | |
1489 | static void _chv_enable_pll(struct intel_crtc *crtc, | |
1490 | const struct intel_crtc_state *pipe_config) | |
9d556c99 | 1491 | { |
cd2d34d9 | 1492 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1493 | enum pipe pipe = crtc->pipe; |
9d556c99 | 1494 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9d556c99 CML |
1495 | u32 tmp; |
1496 | ||
a580516d | 1497 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1498 | |
1499 | /* Enable back the 10bit clock to display controller */ | |
1500 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1501 | tmp |= DPIO_DCLKP_EN; | |
1502 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1503 | ||
54433e91 VS |
1504 | mutex_unlock(&dev_priv->sb_lock); |
1505 | ||
9d556c99 CML |
1506 | /* |
1507 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1508 | */ | |
1509 | udelay(1); | |
1510 | ||
1511 | /* Enable PLL */ | |
d288f65f | 1512 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1513 | |
1514 | /* Check PLL is locked */ | |
6b18826a CW |
1515 | if (intel_wait_for_register(dev_priv, |
1516 | DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV, | |
1517 | 1)) | |
9d556c99 | 1518 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
cd2d34d9 VS |
1519 | } |
1520 | ||
1521 | static void chv_enable_pll(struct intel_crtc *crtc, | |
1522 | const struct intel_crtc_state *pipe_config) | |
1523 | { | |
1524 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1525 | enum pipe pipe = crtc->pipe; | |
1526 | ||
1527 | assert_pipe_disabled(dev_priv, pipe); | |
1528 | ||
1529 | /* PLL is protected by panel, make sure we can write it */ | |
1530 | assert_panel_unlocked(dev_priv, pipe); | |
1531 | ||
1532 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) | |
1533 | _chv_enable_pll(crtc, pipe_config); | |
9d556c99 | 1534 | |
c231775c VS |
1535 | if (pipe != PIPE_A) { |
1536 | /* | |
1537 | * WaPixelRepeatModeFixForC0:chv | |
1538 | * | |
1539 | * DPLLCMD is AWOL. Use chicken bits to propagate | |
1540 | * the value from DPLLBMD to either pipe B or C. | |
1541 | */ | |
1542 | I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C); | |
1543 | I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md); | |
1544 | I915_WRITE(CBR4_VLV, 0); | |
1545 | dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; | |
1546 | ||
1547 | /* | |
1548 | * DPLLB VGA mode also seems to cause problems. | |
1549 | * We should always have it disabled. | |
1550 | */ | |
1551 | WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); | |
1552 | } else { | |
1553 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); | |
1554 | POSTING_READ(DPLL_MD(pipe)); | |
1555 | } | |
9d556c99 CML |
1556 | } |
1557 | ||
6315b5d3 | 1558 | static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv) |
1c4e0274 VS |
1559 | { |
1560 | struct intel_crtc *crtc; | |
1561 | int count = 0; | |
1562 | ||
6315b5d3 | 1563 | for_each_intel_crtc(&dev_priv->drm, crtc) { |
3538b9df | 1564 | count += crtc->base.state->active && |
2d84d2b3 VS |
1565 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO); |
1566 | } | |
1c4e0274 VS |
1567 | |
1568 | return count; | |
1569 | } | |
1570 | ||
66e3d5c0 | 1571 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1572 | { |
6315b5d3 | 1573 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
f0f59a00 | 1574 | i915_reg_t reg = DPLL(crtc->pipe); |
6e3c9717 | 1575 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
bb408dd2 | 1576 | int i; |
63d7bbe9 | 1577 | |
66e3d5c0 | 1578 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1579 | |
63d7bbe9 | 1580 | /* PLL is protected by panel, make sure we can write it */ |
50a0bc90 | 1581 | if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv)) |
66e3d5c0 | 1582 | assert_panel_unlocked(dev_priv, crtc->pipe); |
63d7bbe9 | 1583 | |
1c4e0274 | 1584 | /* Enable DVO 2x clock on both PLLs if necessary */ |
6315b5d3 | 1585 | if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) { |
1c4e0274 VS |
1586 | /* |
1587 | * It appears to be important that we don't enable this | |
1588 | * for the current pipe before otherwise configuring the | |
1589 | * PLL. No idea how this should be handled if multiple | |
1590 | * DVO outputs are enabled simultaneosly. | |
1591 | */ | |
1592 | dpll |= DPLL_DVO_2X_MODE; | |
1593 | I915_WRITE(DPLL(!crtc->pipe), | |
1594 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1595 | } | |
66e3d5c0 | 1596 | |
c2b63374 VS |
1597 | /* |
1598 | * Apparently we need to have VGA mode enabled prior to changing | |
1599 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1600 | * dividers, even though the register value does change. | |
1601 | */ | |
1602 | I915_WRITE(reg, 0); | |
1603 | ||
8e7a65aa VS |
1604 | I915_WRITE(reg, dpll); |
1605 | ||
66e3d5c0 DV |
1606 | /* Wait for the clocks to stabilize. */ |
1607 | POSTING_READ(reg); | |
1608 | udelay(150); | |
1609 | ||
6315b5d3 | 1610 | if (INTEL_GEN(dev_priv) >= 4) { |
66e3d5c0 | 1611 | I915_WRITE(DPLL_MD(crtc->pipe), |
6e3c9717 | 1612 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1613 | } else { |
1614 | /* The pixel multiplier can only be updated once the | |
1615 | * DPLL is enabled and the clocks are stable. | |
1616 | * | |
1617 | * So write it again. | |
1618 | */ | |
1619 | I915_WRITE(reg, dpll); | |
1620 | } | |
63d7bbe9 JB |
1621 | |
1622 | /* We do this three times for luck */ | |
bb408dd2 VS |
1623 | for (i = 0; i < 3; i++) { |
1624 | I915_WRITE(reg, dpll); | |
1625 | POSTING_READ(reg); | |
1626 | udelay(150); /* wait for warmup */ | |
1627 | } | |
63d7bbe9 JB |
1628 | } |
1629 | ||
1630 | /** | |
50b44a44 | 1631 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1632 | * @dev_priv: i915 private structure |
1633 | * @pipe: pipe PLL to disable | |
1634 | * | |
1635 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1636 | * | |
1637 | * Note! This is for pre-ILK only. | |
1638 | */ | |
1c4e0274 | 1639 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1640 | { |
6315b5d3 | 1641 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1c4e0274 VS |
1642 | enum pipe pipe = crtc->pipe; |
1643 | ||
1644 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
50a0bc90 | 1645 | if (IS_I830(dev_priv) && |
2d84d2b3 | 1646 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) && |
6315b5d3 | 1647 | !intel_num_dvo_pipes(dev_priv)) { |
1c4e0274 VS |
1648 | I915_WRITE(DPLL(PIPE_B), |
1649 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1650 | I915_WRITE(DPLL(PIPE_A), | |
1651 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1652 | } | |
1653 | ||
b6b5d049 | 1654 | /* Don't disable pipe or pipe PLLs if needed */ |
e56134bc | 1655 | if (IS_I830(dev_priv)) |
63d7bbe9 JB |
1656 | return; |
1657 | ||
1658 | /* Make sure the pipe isn't still relying on us */ | |
1659 | assert_pipe_disabled(dev_priv, pipe); | |
1660 | ||
b8afb911 | 1661 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1662 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1663 | } |
1664 | ||
f6071166 JB |
1665 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1666 | { | |
b8afb911 | 1667 | u32 val; |
f6071166 JB |
1668 | |
1669 | /* Make sure the pipe isn't still relying on us */ | |
1670 | assert_pipe_disabled(dev_priv, pipe); | |
1671 | ||
03ed5cbf VS |
1672 | val = DPLL_INTEGRATED_REF_CLK_VLV | |
1673 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
1674 | if (pipe != PIPE_A) | |
1675 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1676 | ||
f6071166 JB |
1677 | I915_WRITE(DPLL(pipe), val); |
1678 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1679 | } |
1680 | ||
1681 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1682 | { | |
d752048d | 1683 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1684 | u32 val; |
1685 | ||
a11b0703 VS |
1686 | /* Make sure the pipe isn't still relying on us */ |
1687 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1688 | |
60bfe44f VS |
1689 | val = DPLL_SSC_REF_CLK_CHV | |
1690 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1691 | if (pipe != PIPE_A) |
1692 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
03ed5cbf | 1693 | |
a11b0703 VS |
1694 | I915_WRITE(DPLL(pipe), val); |
1695 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1696 | |
a580516d | 1697 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1698 | |
1699 | /* Disable 10bit clock to display controller */ | |
1700 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1701 | val &= ~DPIO_DCLKP_EN; | |
1702 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1703 | ||
a580516d | 1704 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1705 | } |
1706 | ||
e4607fcf | 1707 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1708 | struct intel_digital_port *dport, |
1709 | unsigned int expected_mask) | |
89b667f8 JB |
1710 | { |
1711 | u32 port_mask; | |
f0f59a00 | 1712 | i915_reg_t dpll_reg; |
89b667f8 | 1713 | |
e4607fcf CML |
1714 | switch (dport->port) { |
1715 | case PORT_B: | |
89b667f8 | 1716 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1717 | dpll_reg = DPLL(0); |
e4607fcf CML |
1718 | break; |
1719 | case PORT_C: | |
89b667f8 | 1720 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1721 | dpll_reg = DPLL(0); |
9b6de0a1 | 1722 | expected_mask <<= 4; |
00fc31b7 CML |
1723 | break; |
1724 | case PORT_D: | |
1725 | port_mask = DPLL_PORTD_READY_MASK; | |
1726 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1727 | break; |
1728 | default: | |
1729 | BUG(); | |
1730 | } | |
89b667f8 | 1731 | |
370004d3 CW |
1732 | if (intel_wait_for_register(dev_priv, |
1733 | dpll_reg, port_mask, expected_mask, | |
1734 | 1000)) | |
9b6de0a1 VS |
1735 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", |
1736 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1737 | } |
1738 | ||
b8a4f404 PZ |
1739 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1740 | enum pipe pipe) | |
040484af | 1741 | { |
98187836 VS |
1742 | struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv, |
1743 | pipe); | |
f0f59a00 VS |
1744 | i915_reg_t reg; |
1745 | uint32_t val, pipeconf_val; | |
040484af | 1746 | |
040484af | 1747 | /* Make sure PCH DPLL is enabled */ |
8106ddbd | 1748 | assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll); |
040484af JB |
1749 | |
1750 | /* FDI must be feeding us bits for PCH ports */ | |
1751 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1752 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1753 | ||
6e266956 | 1754 | if (HAS_PCH_CPT(dev_priv)) { |
23670b32 DV |
1755 | /* Workaround: Set the timing override bit before enabling the |
1756 | * pch transcoder. */ | |
1757 | reg = TRANS_CHICKEN2(pipe); | |
1758 | val = I915_READ(reg); | |
1759 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1760 | I915_WRITE(reg, val); | |
59c859d6 | 1761 | } |
23670b32 | 1762 | |
ab9412ba | 1763 | reg = PCH_TRANSCONF(pipe); |
040484af | 1764 | val = I915_READ(reg); |
5f7f726d | 1765 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c | 1766 | |
2d1fe073 | 1767 | if (HAS_PCH_IBX(dev_priv)) { |
e9bcff5c | 1768 | /* |
c5de7c6f VS |
1769 | * Make the BPC in transcoder be consistent with |
1770 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1771 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1772 | */ |
dfd07d72 | 1773 | val &= ~PIPECONF_BPC_MASK; |
2d84d2b3 | 1774 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI)) |
c5de7c6f VS |
1775 | val |= PIPECONF_8BPC; |
1776 | else | |
1777 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1778 | } |
5f7f726d PZ |
1779 | |
1780 | val &= ~TRANS_INTERLACE_MASK; | |
1781 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
2d1fe073 | 1782 | if (HAS_PCH_IBX(dev_priv) && |
2d84d2b3 | 1783 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
1784 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1785 | else | |
1786 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1787 | else |
1788 | val |= TRANS_PROGRESSIVE; | |
1789 | ||
040484af | 1790 | I915_WRITE(reg, val | TRANS_ENABLE); |
650fbd84 CW |
1791 | if (intel_wait_for_register(dev_priv, |
1792 | reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE, | |
1793 | 100)) | |
4bb6f1f3 | 1794 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1795 | } |
1796 | ||
8fb033d7 | 1797 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1798 | enum transcoder cpu_transcoder) |
040484af | 1799 | { |
8fb033d7 | 1800 | u32 val, pipeconf_val; |
8fb033d7 | 1801 | |
8fb033d7 | 1802 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1803 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
a2196033 | 1804 | assert_fdi_rx_enabled(dev_priv, PIPE_A); |
8fb033d7 | 1805 | |
223a6fdf | 1806 | /* Workaround: set timing override bit. */ |
36c0d0cf | 1807 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1808 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1809 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 1810 | |
25f3ef11 | 1811 | val = TRANS_ENABLE; |
937bb610 | 1812 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1813 | |
9a76b1c6 PZ |
1814 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1815 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1816 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1817 | else |
1818 | val |= TRANS_PROGRESSIVE; | |
1819 | ||
ab9412ba | 1820 | I915_WRITE(LPT_TRANSCONF, val); |
d9f96244 CW |
1821 | if (intel_wait_for_register(dev_priv, |
1822 | LPT_TRANSCONF, | |
1823 | TRANS_STATE_ENABLE, | |
1824 | TRANS_STATE_ENABLE, | |
1825 | 100)) | |
937bb610 | 1826 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1827 | } |
1828 | ||
b8a4f404 PZ |
1829 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1830 | enum pipe pipe) | |
040484af | 1831 | { |
f0f59a00 VS |
1832 | i915_reg_t reg; |
1833 | uint32_t val; | |
040484af JB |
1834 | |
1835 | /* FDI relies on the transcoder */ | |
1836 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1837 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1838 | ||
291906f1 JB |
1839 | /* Ports must be off as well */ |
1840 | assert_pch_ports_disabled(dev_priv, pipe); | |
1841 | ||
ab9412ba | 1842 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1843 | val = I915_READ(reg); |
1844 | val &= ~TRANS_ENABLE; | |
1845 | I915_WRITE(reg, val); | |
1846 | /* wait for PCH transcoder off, transcoder state */ | |
a7d04662 CW |
1847 | if (intel_wait_for_register(dev_priv, |
1848 | reg, TRANS_STATE_ENABLE, 0, | |
1849 | 50)) | |
4bb6f1f3 | 1850 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 | 1851 | |
6e266956 | 1852 | if (HAS_PCH_CPT(dev_priv)) { |
23670b32 DV |
1853 | /* Workaround: Clear the timing override chicken bit again. */ |
1854 | reg = TRANS_CHICKEN2(pipe); | |
1855 | val = I915_READ(reg); | |
1856 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1857 | I915_WRITE(reg, val); | |
1858 | } | |
040484af JB |
1859 | } |
1860 | ||
b7076546 | 1861 | void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1862 | { |
8fb033d7 PZ |
1863 | u32 val; |
1864 | ||
ab9412ba | 1865 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1866 | val &= ~TRANS_ENABLE; |
ab9412ba | 1867 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1868 | /* wait for PCH transcoder off, transcoder state */ |
dfdb4749 CW |
1869 | if (intel_wait_for_register(dev_priv, |
1870 | LPT_TRANSCONF, TRANS_STATE_ENABLE, 0, | |
1871 | 50)) | |
8a52fd9f | 1872 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1873 | |
1874 | /* Workaround: clear timing override bit. */ | |
36c0d0cf | 1875 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1876 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1877 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
1878 | } |
1879 | ||
a2196033 | 1880 | enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc) |
65f2130c VS |
1881 | { |
1882 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1883 | ||
1884 | WARN_ON(!crtc->config->has_pch_encoder); | |
1885 | ||
1886 | if (HAS_PCH_LPT(dev_priv)) | |
a2196033 | 1887 | return PIPE_A; |
65f2130c | 1888 | else |
a2196033 | 1889 | return crtc->pipe; |
65f2130c VS |
1890 | } |
1891 | ||
b24e7179 | 1892 | /** |
309cfea8 | 1893 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 1894 | * @crtc: crtc responsible for the pipe |
b24e7179 | 1895 | * |
0372264a | 1896 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 1897 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 1898 | */ |
e1fdc473 | 1899 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1900 | { |
0372264a | 1901 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1902 | struct drm_i915_private *dev_priv = to_i915(dev); |
0372264a | 1903 | enum pipe pipe = crtc->pipe; |
1a70a728 | 1904 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
f0f59a00 | 1905 | i915_reg_t reg; |
b24e7179 JB |
1906 | u32 val; |
1907 | ||
9e2ee2dd VS |
1908 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
1909 | ||
58c6eaa2 | 1910 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 1911 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
1912 | assert_sprites_disabled(dev_priv, pipe); |
1913 | ||
b24e7179 JB |
1914 | /* |
1915 | * A pipe without a PLL won't actually be able to drive bits from | |
1916 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1917 | * need the check. | |
1918 | */ | |
09fa8bb9 | 1919 | if (HAS_GMCH_DISPLAY(dev_priv)) { |
d7edc4e5 | 1920 | if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
1921 | assert_dsi_pll_enabled(dev_priv); |
1922 | else | |
1923 | assert_pll_enabled(dev_priv, pipe); | |
09fa8bb9 | 1924 | } else { |
6e3c9717 | 1925 | if (crtc->config->has_pch_encoder) { |
040484af | 1926 | /* if driving the PCH, we need FDI enabled */ |
65f2130c | 1927 | assert_fdi_rx_pll_enabled(dev_priv, |
a2196033 | 1928 | intel_crtc_pch_transcoder(crtc)); |
1a240d4d DV |
1929 | assert_fdi_tx_pll_enabled(dev_priv, |
1930 | (enum pipe) cpu_transcoder); | |
040484af JB |
1931 | } |
1932 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1933 | } | |
b24e7179 | 1934 | |
702e7a56 | 1935 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1936 | val = I915_READ(reg); |
7ad25d48 | 1937 | if (val & PIPECONF_ENABLE) { |
e56134bc VS |
1938 | /* we keep both pipes enabled on 830 */ |
1939 | WARN_ON(!IS_I830(dev_priv)); | |
00d70b15 | 1940 | return; |
7ad25d48 | 1941 | } |
00d70b15 CW |
1942 | |
1943 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 1944 | POSTING_READ(reg); |
b7792d8b VS |
1945 | |
1946 | /* | |
1947 | * Until the pipe starts DSL will read as 0, which would cause | |
1948 | * an apparent vblank timestamp jump, which messes up also the | |
1949 | * frame count when it's derived from the timestamps. So let's | |
1950 | * wait for the pipe to start properly before we call | |
1951 | * drm_crtc_vblank_on() | |
1952 | */ | |
1953 | if (dev->max_vblank_count == 0 && | |
1954 | wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50)) | |
1955 | DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe)); | |
b24e7179 JB |
1956 | } |
1957 | ||
1958 | /** | |
309cfea8 | 1959 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 1960 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 1961 | * |
575f7ab7 VS |
1962 | * Disable the pipe of @crtc, making sure that various hardware |
1963 | * specific requirements are met, if applicable, e.g. plane | |
1964 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
1965 | * |
1966 | * Will wait until the pipe has shut down before returning. | |
1967 | */ | |
575f7ab7 | 1968 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1969 | { |
fac5e23e | 1970 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6e3c9717 | 1971 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1972 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 1973 | i915_reg_t reg; |
b24e7179 JB |
1974 | u32 val; |
1975 | ||
9e2ee2dd VS |
1976 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
1977 | ||
b24e7179 JB |
1978 | /* |
1979 | * Make sure planes won't keep trying to pump pixels to us, | |
1980 | * or we might hang the display. | |
1981 | */ | |
1982 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 1983 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 1984 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 1985 | |
702e7a56 | 1986 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1987 | val = I915_READ(reg); |
00d70b15 CW |
1988 | if ((val & PIPECONF_ENABLE) == 0) |
1989 | return; | |
1990 | ||
67adc644 VS |
1991 | /* |
1992 | * Double wide has implications for planes | |
1993 | * so best keep it disabled when not needed. | |
1994 | */ | |
6e3c9717 | 1995 | if (crtc->config->double_wide) |
67adc644 VS |
1996 | val &= ~PIPECONF_DOUBLE_WIDE; |
1997 | ||
1998 | /* Don't disable pipe or pipe PLLs if needed */ | |
e56134bc | 1999 | if (!IS_I830(dev_priv)) |
67adc644 VS |
2000 | val &= ~PIPECONF_ENABLE; |
2001 | ||
2002 | I915_WRITE(reg, val); | |
2003 | if ((val & PIPECONF_ENABLE) == 0) | |
2004 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2005 | } |
2006 | ||
832be82f VS |
2007 | static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) |
2008 | { | |
2009 | return IS_GEN2(dev_priv) ? 2048 : 4096; | |
2010 | } | |
2011 | ||
d88c4afd VS |
2012 | static unsigned int |
2013 | intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane) | |
7b49f948 | 2014 | { |
d88c4afd VS |
2015 | struct drm_i915_private *dev_priv = to_i915(fb->dev); |
2016 | unsigned int cpp = fb->format->cpp[plane]; | |
2017 | ||
2018 | switch (fb->modifier) { | |
2f075565 | 2019 | case DRM_FORMAT_MOD_LINEAR: |
7b49f948 VS |
2020 | return cpp; |
2021 | case I915_FORMAT_MOD_X_TILED: | |
2022 | if (IS_GEN2(dev_priv)) | |
2023 | return 128; | |
2024 | else | |
2025 | return 512; | |
2e2adb05 VS |
2026 | case I915_FORMAT_MOD_Y_TILED_CCS: |
2027 | if (plane == 1) | |
2028 | return 128; | |
2029 | /* fall through */ | |
7b49f948 VS |
2030 | case I915_FORMAT_MOD_Y_TILED: |
2031 | if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) | |
2032 | return 128; | |
2033 | else | |
2034 | return 512; | |
2e2adb05 VS |
2035 | case I915_FORMAT_MOD_Yf_TILED_CCS: |
2036 | if (plane == 1) | |
2037 | return 128; | |
2038 | /* fall through */ | |
7b49f948 VS |
2039 | case I915_FORMAT_MOD_Yf_TILED: |
2040 | switch (cpp) { | |
2041 | case 1: | |
2042 | return 64; | |
2043 | case 2: | |
2044 | case 4: | |
2045 | return 128; | |
2046 | case 8: | |
2047 | case 16: | |
2048 | return 256; | |
2049 | default: | |
2050 | MISSING_CASE(cpp); | |
2051 | return cpp; | |
2052 | } | |
2053 | break; | |
2054 | default: | |
d88c4afd | 2055 | MISSING_CASE(fb->modifier); |
7b49f948 VS |
2056 | return cpp; |
2057 | } | |
2058 | } | |
2059 | ||
d88c4afd VS |
2060 | static unsigned int |
2061 | intel_tile_height(const struct drm_framebuffer *fb, int plane) | |
a57ce0b2 | 2062 | { |
2f075565 | 2063 | if (fb->modifier == DRM_FORMAT_MOD_LINEAR) |
832be82f VS |
2064 | return 1; |
2065 | else | |
d88c4afd VS |
2066 | return intel_tile_size(to_i915(fb->dev)) / |
2067 | intel_tile_width_bytes(fb, plane); | |
6761dd31 TU |
2068 | } |
2069 | ||
8d0deca8 | 2070 | /* Return the tile dimensions in pixel units */ |
d88c4afd | 2071 | static void intel_tile_dims(const struct drm_framebuffer *fb, int plane, |
8d0deca8 | 2072 | unsigned int *tile_width, |
d88c4afd | 2073 | unsigned int *tile_height) |
8d0deca8 | 2074 | { |
d88c4afd VS |
2075 | unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane); |
2076 | unsigned int cpp = fb->format->cpp[plane]; | |
8d0deca8 VS |
2077 | |
2078 | *tile_width = tile_width_bytes / cpp; | |
d88c4afd | 2079 | *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes; |
8d0deca8 VS |
2080 | } |
2081 | ||
6761dd31 | 2082 | unsigned int |
d88c4afd VS |
2083 | intel_fb_align_height(const struct drm_framebuffer *fb, |
2084 | int plane, unsigned int height) | |
6761dd31 | 2085 | { |
d88c4afd | 2086 | unsigned int tile_height = intel_tile_height(fb, plane); |
832be82f VS |
2087 | |
2088 | return ALIGN(height, tile_height); | |
a57ce0b2 JB |
2089 | } |
2090 | ||
1663b9d6 VS |
2091 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) |
2092 | { | |
2093 | unsigned int size = 0; | |
2094 | int i; | |
2095 | ||
2096 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) | |
2097 | size += rot_info->plane[i].width * rot_info->plane[i].height; | |
2098 | ||
2099 | return size; | |
2100 | } | |
2101 | ||
75c82a53 | 2102 | static void |
3465c580 VS |
2103 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, |
2104 | const struct drm_framebuffer *fb, | |
2105 | unsigned int rotation) | |
f64b98cd | 2106 | { |
7b92c047 | 2107 | view->type = I915_GGTT_VIEW_NORMAL; |
bd2ef25d | 2108 | if (drm_rotation_90_or_270(rotation)) { |
7b92c047 | 2109 | view->type = I915_GGTT_VIEW_ROTATED; |
8bab1193 | 2110 | view->rotated = to_intel_framebuffer(fb)->rot_info; |
2d7a215f VS |
2111 | } |
2112 | } | |
50470bb0 | 2113 | |
fabac484 VS |
2114 | static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv) |
2115 | { | |
2116 | if (IS_I830(dev_priv)) | |
2117 | return 16 * 1024; | |
2118 | else if (IS_I85X(dev_priv)) | |
2119 | return 256; | |
d9e1551e VS |
2120 | else if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) |
2121 | return 32; | |
fabac484 VS |
2122 | else |
2123 | return 4 * 1024; | |
2124 | } | |
2125 | ||
603525d7 | 2126 | static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) |
4e9a86b6 VS |
2127 | { |
2128 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2129 | return 256 * 1024; | |
c0f86832 | 2130 | else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) || |
666a4537 | 2131 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
4e9a86b6 VS |
2132 | return 128 * 1024; |
2133 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2134 | return 4 * 1024; | |
2135 | else | |
44c5905e | 2136 | return 0; |
4e9a86b6 VS |
2137 | } |
2138 | ||
d88c4afd VS |
2139 | static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb, |
2140 | int plane) | |
603525d7 | 2141 | { |
d88c4afd VS |
2142 | struct drm_i915_private *dev_priv = to_i915(fb->dev); |
2143 | ||
b90c1ee1 | 2144 | /* AUX_DIST needs only 4K alignment */ |
2e2adb05 | 2145 | if (plane == 1) |
b90c1ee1 VS |
2146 | return 4096; |
2147 | ||
d88c4afd | 2148 | switch (fb->modifier) { |
2f075565 | 2149 | case DRM_FORMAT_MOD_LINEAR: |
603525d7 VS |
2150 | return intel_linear_alignment(dev_priv); |
2151 | case I915_FORMAT_MOD_X_TILED: | |
d88c4afd | 2152 | if (INTEL_GEN(dev_priv) >= 9) |
603525d7 VS |
2153 | return 256 * 1024; |
2154 | return 0; | |
2e2adb05 VS |
2155 | case I915_FORMAT_MOD_Y_TILED_CCS: |
2156 | case I915_FORMAT_MOD_Yf_TILED_CCS: | |
603525d7 VS |
2157 | case I915_FORMAT_MOD_Y_TILED: |
2158 | case I915_FORMAT_MOD_Yf_TILED: | |
2159 | return 1 * 1024 * 1024; | |
2160 | default: | |
d88c4afd | 2161 | MISSING_CASE(fb->modifier); |
603525d7 VS |
2162 | return 0; |
2163 | } | |
2164 | } | |
2165 | ||
058d88c4 CW |
2166 | struct i915_vma * |
2167 | intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) | |
6b95a207 | 2168 | { |
850c4cdc | 2169 | struct drm_device *dev = fb->dev; |
fac5e23e | 2170 | struct drm_i915_private *dev_priv = to_i915(dev); |
850c4cdc | 2171 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2172 | struct i915_ggtt_view view; |
058d88c4 | 2173 | struct i915_vma *vma; |
6b95a207 | 2174 | u32 alignment; |
6b95a207 | 2175 | |
ebcdd39e MR |
2176 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2177 | ||
d88c4afd | 2178 | alignment = intel_surf_alignment(fb, 0); |
6b95a207 | 2179 | |
3465c580 | 2180 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2181 | |
693db184 CW |
2182 | /* Note that the w/a also requires 64 PTE of padding following the |
2183 | * bo. We currently fill all unused PTE with the shadow page and so | |
2184 | * we should always have valid PTE following the scanout preventing | |
2185 | * the VT-d warning. | |
2186 | */ | |
48f112fe | 2187 | if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024) |
693db184 CW |
2188 | alignment = 256 * 1024; |
2189 | ||
d6dd6843 PZ |
2190 | /* |
2191 | * Global gtt pte registers are special registers which actually forward | |
2192 | * writes to a chunk of system memory. Which means that there is no risk | |
2193 | * that the register values disappear as soon as we call | |
2194 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2195 | * pin/unpin/fence and not more. | |
2196 | */ | |
2197 | intel_runtime_pm_get(dev_priv); | |
2198 | ||
9db529aa DV |
2199 | atomic_inc(&dev_priv->gpu_error.pending_fb_pin); |
2200 | ||
058d88c4 | 2201 | vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view); |
49ef5294 CW |
2202 | if (IS_ERR(vma)) |
2203 | goto err; | |
6b95a207 | 2204 | |
05a20d09 | 2205 | if (i915_vma_is_map_and_fenceable(vma)) { |
49ef5294 CW |
2206 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
2207 | * fence, whereas 965+ only requires a fence if using | |
2208 | * framebuffer compression. For simplicity, we always, when | |
2209 | * possible, install a fence as the cost is not that onerous. | |
2210 | * | |
2211 | * If we fail to fence the tiled scanout, then either the | |
2212 | * modeset will reject the change (which is highly unlikely as | |
2213 | * the affected systems, all but one, do not have unmappable | |
2214 | * space) or we will not be able to enable full powersaving | |
2215 | * techniques (also likely not to apply due to various limits | |
2216 | * FBC and the like impose on the size of the buffer, which | |
2217 | * presumably we violated anyway with this unmappable buffer). | |
2218 | * Anyway, it is presumably better to stumble onwards with | |
2219 | * something and try to run the system in a "less than optimal" | |
2220 | * mode that matches the user configuration. | |
2221 | */ | |
2222 | if (i915_vma_get_fence(vma) == 0) | |
2223 | i915_vma_pin_fence(vma); | |
9807216f | 2224 | } |
6b95a207 | 2225 | |
be1e3415 | 2226 | i915_vma_get(vma); |
49ef5294 | 2227 | err: |
9db529aa DV |
2228 | atomic_dec(&dev_priv->gpu_error.pending_fb_pin); |
2229 | ||
d6dd6843 | 2230 | intel_runtime_pm_put(dev_priv); |
058d88c4 | 2231 | return vma; |
6b95a207 KH |
2232 | } |
2233 | ||
be1e3415 | 2234 | void intel_unpin_fb_vma(struct i915_vma *vma) |
1690e1eb | 2235 | { |
be1e3415 | 2236 | lockdep_assert_held(&vma->vm->i915->drm.struct_mutex); |
f64b98cd | 2237 | |
49ef5294 | 2238 | i915_vma_unpin_fence(vma); |
058d88c4 | 2239 | i915_gem_object_unpin_from_display_plane(vma); |
be1e3415 | 2240 | i915_vma_put(vma); |
1690e1eb CW |
2241 | } |
2242 | ||
ef78ec94 VS |
2243 | static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane, |
2244 | unsigned int rotation) | |
2245 | { | |
bd2ef25d | 2246 | if (drm_rotation_90_or_270(rotation)) |
ef78ec94 VS |
2247 | return to_intel_framebuffer(fb)->rotated[plane].pitch; |
2248 | else | |
2249 | return fb->pitches[plane]; | |
2250 | } | |
2251 | ||
6687c906 VS |
2252 | /* |
2253 | * Convert the x/y offsets into a linear offset. | |
2254 | * Only valid with 0/180 degree rotation, which is fine since linear | |
2255 | * offset is only used with linear buffers on pre-hsw and tiled buffers | |
2256 | * with gen2/3, and 90/270 degree rotations isn't supported on any of them. | |
2257 | */ | |
2258 | u32 intel_fb_xy_to_linear(int x, int y, | |
2949056c VS |
2259 | const struct intel_plane_state *state, |
2260 | int plane) | |
6687c906 | 2261 | { |
2949056c | 2262 | const struct drm_framebuffer *fb = state->base.fb; |
353c8598 | 2263 | unsigned int cpp = fb->format->cpp[plane]; |
6687c906 VS |
2264 | unsigned int pitch = fb->pitches[plane]; |
2265 | ||
2266 | return y * pitch + x * cpp; | |
2267 | } | |
2268 | ||
2269 | /* | |
2270 | * Add the x/y offsets derived from fb->offsets[] to the user | |
2271 | * specified plane src x/y offsets. The resulting x/y offsets | |
2272 | * specify the start of scanout from the beginning of the gtt mapping. | |
2273 | */ | |
2274 | void intel_add_fb_offsets(int *x, int *y, | |
2949056c VS |
2275 | const struct intel_plane_state *state, |
2276 | int plane) | |
6687c906 VS |
2277 | |
2278 | { | |
2949056c VS |
2279 | const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb); |
2280 | unsigned int rotation = state->base.rotation; | |
6687c906 | 2281 | |
bd2ef25d | 2282 | if (drm_rotation_90_or_270(rotation)) { |
6687c906 VS |
2283 | *x += intel_fb->rotated[plane].x; |
2284 | *y += intel_fb->rotated[plane].y; | |
2285 | } else { | |
2286 | *x += intel_fb->normal[plane].x; | |
2287 | *y += intel_fb->normal[plane].y; | |
2288 | } | |
2289 | } | |
2290 | ||
29cf9491 | 2291 | /* |
29cf9491 VS |
2292 | * Input tile dimensions and pitch must already be |
2293 | * rotated to match x and y, and in pixel units. | |
2294 | */ | |
66a2d927 VS |
2295 | static u32 _intel_adjust_tile_offset(int *x, int *y, |
2296 | unsigned int tile_width, | |
2297 | unsigned int tile_height, | |
2298 | unsigned int tile_size, | |
2299 | unsigned int pitch_tiles, | |
2300 | u32 old_offset, | |
2301 | u32 new_offset) | |
29cf9491 | 2302 | { |
b9b24038 | 2303 | unsigned int pitch_pixels = pitch_tiles * tile_width; |
29cf9491 VS |
2304 | unsigned int tiles; |
2305 | ||
2306 | WARN_ON(old_offset & (tile_size - 1)); | |
2307 | WARN_ON(new_offset & (tile_size - 1)); | |
2308 | WARN_ON(new_offset > old_offset); | |
2309 | ||
2310 | tiles = (old_offset - new_offset) / tile_size; | |
2311 | ||
2312 | *y += tiles / pitch_tiles * tile_height; | |
2313 | *x += tiles % pitch_tiles * tile_width; | |
2314 | ||
b9b24038 VS |
2315 | /* minimize x in case it got needlessly big */ |
2316 | *y += *x / pitch_pixels * tile_height; | |
2317 | *x %= pitch_pixels; | |
2318 | ||
29cf9491 VS |
2319 | return new_offset; |
2320 | } | |
2321 | ||
66a2d927 VS |
2322 | /* |
2323 | * Adjust the tile offset by moving the difference into | |
2324 | * the x/y offsets. | |
2325 | */ | |
2326 | static u32 intel_adjust_tile_offset(int *x, int *y, | |
2327 | const struct intel_plane_state *state, int plane, | |
2328 | u32 old_offset, u32 new_offset) | |
2329 | { | |
2330 | const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev); | |
2331 | const struct drm_framebuffer *fb = state->base.fb; | |
353c8598 | 2332 | unsigned int cpp = fb->format->cpp[plane]; |
66a2d927 VS |
2333 | unsigned int rotation = state->base.rotation; |
2334 | unsigned int pitch = intel_fb_pitch(fb, plane, rotation); | |
2335 | ||
2336 | WARN_ON(new_offset > old_offset); | |
2337 | ||
2f075565 | 2338 | if (fb->modifier != DRM_FORMAT_MOD_LINEAR) { |
66a2d927 VS |
2339 | unsigned int tile_size, tile_width, tile_height; |
2340 | unsigned int pitch_tiles; | |
2341 | ||
2342 | tile_size = intel_tile_size(dev_priv); | |
d88c4afd | 2343 | intel_tile_dims(fb, plane, &tile_width, &tile_height); |
66a2d927 | 2344 | |
bd2ef25d | 2345 | if (drm_rotation_90_or_270(rotation)) { |
66a2d927 VS |
2346 | pitch_tiles = pitch / tile_height; |
2347 | swap(tile_width, tile_height); | |
2348 | } else { | |
2349 | pitch_tiles = pitch / (tile_width * cpp); | |
2350 | } | |
2351 | ||
2352 | _intel_adjust_tile_offset(x, y, tile_width, tile_height, | |
2353 | tile_size, pitch_tiles, | |
2354 | old_offset, new_offset); | |
2355 | } else { | |
2356 | old_offset += *y * pitch + *x * cpp; | |
2357 | ||
2358 | *y = (old_offset - new_offset) / pitch; | |
2359 | *x = ((old_offset - new_offset) - *y * pitch) / cpp; | |
2360 | } | |
2361 | ||
2362 | return new_offset; | |
2363 | } | |
2364 | ||
8d0deca8 VS |
2365 | /* |
2366 | * Computes the linear offset to the base tile and adjusts | |
2367 | * x, y. bytes per pixel is assumed to be a power-of-two. | |
2368 | * | |
2369 | * In the 90/270 rotated case, x and y are assumed | |
2370 | * to be already rotated to match the rotated GTT view, and | |
2371 | * pitch is the tile_height aligned framebuffer height. | |
6687c906 VS |
2372 | * |
2373 | * This function is used when computing the derived information | |
2374 | * under intel_framebuffer, so using any of that information | |
2375 | * here is not allowed. Anything under drm_framebuffer can be | |
2376 | * used. This is why the user has to pass in the pitch since it | |
2377 | * is specified in the rotated orientation. | |
8d0deca8 | 2378 | */ |
6687c906 VS |
2379 | static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv, |
2380 | int *x, int *y, | |
2381 | const struct drm_framebuffer *fb, int plane, | |
2382 | unsigned int pitch, | |
2383 | unsigned int rotation, | |
2384 | u32 alignment) | |
c2c75131 | 2385 | { |
bae781b2 | 2386 | uint64_t fb_modifier = fb->modifier; |
353c8598 | 2387 | unsigned int cpp = fb->format->cpp[plane]; |
6687c906 | 2388 | u32 offset, offset_aligned; |
29cf9491 | 2389 | |
29cf9491 VS |
2390 | if (alignment) |
2391 | alignment--; | |
2392 | ||
2f075565 | 2393 | if (fb_modifier != DRM_FORMAT_MOD_LINEAR) { |
8d0deca8 VS |
2394 | unsigned int tile_size, tile_width, tile_height; |
2395 | unsigned int tile_rows, tiles, pitch_tiles; | |
c2c75131 | 2396 | |
d843310d | 2397 | tile_size = intel_tile_size(dev_priv); |
d88c4afd | 2398 | intel_tile_dims(fb, plane, &tile_width, &tile_height); |
8d0deca8 | 2399 | |
bd2ef25d | 2400 | if (drm_rotation_90_or_270(rotation)) { |
8d0deca8 VS |
2401 | pitch_tiles = pitch / tile_height; |
2402 | swap(tile_width, tile_height); | |
2403 | } else { | |
2404 | pitch_tiles = pitch / (tile_width * cpp); | |
2405 | } | |
d843310d VS |
2406 | |
2407 | tile_rows = *y / tile_height; | |
2408 | *y %= tile_height; | |
c2c75131 | 2409 | |
8d0deca8 VS |
2410 | tiles = *x / tile_width; |
2411 | *x %= tile_width; | |
bc752862 | 2412 | |
29cf9491 VS |
2413 | offset = (tile_rows * pitch_tiles + tiles) * tile_size; |
2414 | offset_aligned = offset & ~alignment; | |
bc752862 | 2415 | |
66a2d927 VS |
2416 | _intel_adjust_tile_offset(x, y, tile_width, tile_height, |
2417 | tile_size, pitch_tiles, | |
2418 | offset, offset_aligned); | |
29cf9491 | 2419 | } else { |
bc752862 | 2420 | offset = *y * pitch + *x * cpp; |
29cf9491 VS |
2421 | offset_aligned = offset & ~alignment; |
2422 | ||
4e9a86b6 VS |
2423 | *y = (offset & alignment) / pitch; |
2424 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
bc752862 | 2425 | } |
29cf9491 VS |
2426 | |
2427 | return offset_aligned; | |
c2c75131 DV |
2428 | } |
2429 | ||
6687c906 | 2430 | u32 intel_compute_tile_offset(int *x, int *y, |
2949056c VS |
2431 | const struct intel_plane_state *state, |
2432 | int plane) | |
6687c906 | 2433 | { |
1e7b4fd8 VS |
2434 | struct intel_plane *intel_plane = to_intel_plane(state->base.plane); |
2435 | struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev); | |
2949056c VS |
2436 | const struct drm_framebuffer *fb = state->base.fb; |
2437 | unsigned int rotation = state->base.rotation; | |
ef78ec94 | 2438 | int pitch = intel_fb_pitch(fb, plane, rotation); |
1e7b4fd8 VS |
2439 | u32 alignment; |
2440 | ||
2441 | if (intel_plane->id == PLANE_CURSOR) | |
2442 | alignment = intel_cursor_alignment(dev_priv); | |
2443 | else | |
2444 | alignment = intel_surf_alignment(fb, plane); | |
6687c906 VS |
2445 | |
2446 | return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch, | |
2447 | rotation, alignment); | |
2448 | } | |
2449 | ||
2450 | /* Convert the fb->offset[] linear offset into x/y offsets */ | |
2451 | static void intel_fb_offset_to_xy(int *x, int *y, | |
2452 | const struct drm_framebuffer *fb, int plane) | |
2453 | { | |
353c8598 | 2454 | unsigned int cpp = fb->format->cpp[plane]; |
6687c906 VS |
2455 | unsigned int pitch = fb->pitches[plane]; |
2456 | u32 linear_offset = fb->offsets[plane]; | |
2457 | ||
2458 | *y = linear_offset / pitch; | |
2459 | *x = linear_offset % pitch / cpp; | |
2460 | } | |
2461 | ||
72618ebf VS |
2462 | static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier) |
2463 | { | |
2464 | switch (fb_modifier) { | |
2465 | case I915_FORMAT_MOD_X_TILED: | |
2466 | return I915_TILING_X; | |
2467 | case I915_FORMAT_MOD_Y_TILED: | |
2e2adb05 | 2468 | case I915_FORMAT_MOD_Y_TILED_CCS: |
72618ebf VS |
2469 | return I915_TILING_Y; |
2470 | default: | |
2471 | return I915_TILING_NONE; | |
2472 | } | |
2473 | } | |
2474 | ||
bbfb6ce8 VS |
2475 | static const struct drm_format_info ccs_formats[] = { |
2476 | { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, | |
2477 | { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, | |
2478 | { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, | |
2479 | { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, | |
2480 | }; | |
2481 | ||
2482 | static const struct drm_format_info * | |
2483 | lookup_format_info(const struct drm_format_info formats[], | |
2484 | int num_formats, u32 format) | |
2485 | { | |
2486 | int i; | |
2487 | ||
2488 | for (i = 0; i < num_formats; i++) { | |
2489 | if (formats[i].format == format) | |
2490 | return &formats[i]; | |
2491 | } | |
2492 | ||
2493 | return NULL; | |
2494 | } | |
2495 | ||
2496 | static const struct drm_format_info * | |
2497 | intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd) | |
2498 | { | |
2499 | switch (cmd->modifier[0]) { | |
2500 | case I915_FORMAT_MOD_Y_TILED_CCS: | |
2501 | case I915_FORMAT_MOD_Yf_TILED_CCS: | |
2502 | return lookup_format_info(ccs_formats, | |
2503 | ARRAY_SIZE(ccs_formats), | |
2504 | cmd->pixel_format); | |
2505 | default: | |
2506 | return NULL; | |
2507 | } | |
2508 | } | |
2509 | ||
6687c906 VS |
2510 | static int |
2511 | intel_fill_fb_info(struct drm_i915_private *dev_priv, | |
2512 | struct drm_framebuffer *fb) | |
2513 | { | |
2514 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
2515 | struct intel_rotation_info *rot_info = &intel_fb->rot_info; | |
2516 | u32 gtt_offset_rotated = 0; | |
2517 | unsigned int max_size = 0; | |
bcb0b461 | 2518 | int i, num_planes = fb->format->num_planes; |
6687c906 VS |
2519 | unsigned int tile_size = intel_tile_size(dev_priv); |
2520 | ||
2521 | for (i = 0; i < num_planes; i++) { | |
2522 | unsigned int width, height; | |
2523 | unsigned int cpp, size; | |
2524 | u32 offset; | |
2525 | int x, y; | |
2526 | ||
353c8598 | 2527 | cpp = fb->format->cpp[i]; |
145fcb11 VS |
2528 | width = drm_framebuffer_plane_width(fb->width, fb, i); |
2529 | height = drm_framebuffer_plane_height(fb->height, fb, i); | |
6687c906 VS |
2530 | |
2531 | intel_fb_offset_to_xy(&x, &y, fb, i); | |
2532 | ||
2e2adb05 VS |
2533 | if ((fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || |
2534 | fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) && i == 1) { | |
2535 | int hsub = fb->format->hsub; | |
2536 | int vsub = fb->format->vsub; | |
2537 | int tile_width, tile_height; | |
2538 | int main_x, main_y; | |
2539 | int ccs_x, ccs_y; | |
2540 | ||
2541 | intel_tile_dims(fb, i, &tile_width, &tile_height); | |
2542 | ||
2543 | ccs_x = (x * hsub) % (tile_width * hsub); | |
2544 | ccs_y = (y * vsub) % (tile_height * vsub); | |
2545 | main_x = intel_fb->normal[0].x % (tile_width * hsub); | |
2546 | main_y = intel_fb->normal[0].y % (tile_height * vsub); | |
2547 | ||
2548 | /* | |
2549 | * CCS doesn't have its own x/y offset register, so the intra CCS tile | |
2550 | * x/y offsets must match between CCS and the main surface. | |
2551 | */ | |
2552 | if (main_x != ccs_x || main_y != ccs_y) { | |
2553 | DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n", | |
2554 | main_x, main_y, | |
2555 | ccs_x, ccs_y, | |
2556 | intel_fb->normal[0].x, | |
2557 | intel_fb->normal[0].y, | |
2558 | x, y); | |
2559 | return -EINVAL; | |
2560 | } | |
2561 | } | |
2562 | ||
60d5f2a4 VS |
2563 | /* |
2564 | * The fence (if used) is aligned to the start of the object | |
2565 | * so having the framebuffer wrap around across the edge of the | |
2566 | * fenced region doesn't really work. We have no API to configure | |
2567 | * the fence start offset within the object (nor could we probably | |
2568 | * on gen2/3). So it's just easier if we just require that the | |
2569 | * fb layout agrees with the fence layout. We already check that the | |
2570 | * fb stride matches the fence stride elsewhere. | |
2571 | */ | |
2572 | if (i915_gem_object_is_tiled(intel_fb->obj) && | |
2573 | (x + width) * cpp > fb->pitches[i]) { | |
144cc143 VS |
2574 | DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n", |
2575 | i, fb->offsets[i]); | |
60d5f2a4 VS |
2576 | return -EINVAL; |
2577 | } | |
2578 | ||
6687c906 VS |
2579 | /* |
2580 | * First pixel of the framebuffer from | |
2581 | * the start of the normal gtt mapping. | |
2582 | */ | |
2583 | intel_fb->normal[i].x = x; | |
2584 | intel_fb->normal[i].y = y; | |
2585 | ||
2586 | offset = _intel_compute_tile_offset(dev_priv, &x, &y, | |
3ca46c0a | 2587 | fb, i, fb->pitches[i], |
c2c446ad | 2588 | DRM_MODE_ROTATE_0, tile_size); |
6687c906 VS |
2589 | offset /= tile_size; |
2590 | ||
2f075565 | 2591 | if (fb->modifier != DRM_FORMAT_MOD_LINEAR) { |
6687c906 VS |
2592 | unsigned int tile_width, tile_height; |
2593 | unsigned int pitch_tiles; | |
2594 | struct drm_rect r; | |
2595 | ||
d88c4afd | 2596 | intel_tile_dims(fb, i, &tile_width, &tile_height); |
6687c906 VS |
2597 | |
2598 | rot_info->plane[i].offset = offset; | |
2599 | rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp); | |
2600 | rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width); | |
2601 | rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height); | |
2602 | ||
2603 | intel_fb->rotated[i].pitch = | |
2604 | rot_info->plane[i].height * tile_height; | |
2605 | ||
2606 | /* how many tiles does this plane need */ | |
2607 | size = rot_info->plane[i].stride * rot_info->plane[i].height; | |
2608 | /* | |
2609 | * If the plane isn't horizontally tile aligned, | |
2610 | * we need one more tile. | |
2611 | */ | |
2612 | if (x != 0) | |
2613 | size++; | |
2614 | ||
2615 | /* rotate the x/y offsets to match the GTT view */ | |
2616 | r.x1 = x; | |
2617 | r.y1 = y; | |
2618 | r.x2 = x + width; | |
2619 | r.y2 = y + height; | |
2620 | drm_rect_rotate(&r, | |
2621 | rot_info->plane[i].width * tile_width, | |
2622 | rot_info->plane[i].height * tile_height, | |
c2c446ad | 2623 | DRM_MODE_ROTATE_270); |
6687c906 VS |
2624 | x = r.x1; |
2625 | y = r.y1; | |
2626 | ||
2627 | /* rotate the tile dimensions to match the GTT view */ | |
2628 | pitch_tiles = intel_fb->rotated[i].pitch / tile_height; | |
2629 | swap(tile_width, tile_height); | |
2630 | ||
2631 | /* | |
2632 | * We only keep the x/y offsets, so push all of the | |
2633 | * gtt offset into the x/y offsets. | |
2634 | */ | |
46a1bd28 ACO |
2635 | _intel_adjust_tile_offset(&x, &y, |
2636 | tile_width, tile_height, | |
2637 | tile_size, pitch_tiles, | |
66a2d927 | 2638 | gtt_offset_rotated * tile_size, 0); |
6687c906 VS |
2639 | |
2640 | gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height; | |
2641 | ||
2642 | /* | |
2643 | * First pixel of the framebuffer from | |
2644 | * the start of the rotated gtt mapping. | |
2645 | */ | |
2646 | intel_fb->rotated[i].x = x; | |
2647 | intel_fb->rotated[i].y = y; | |
2648 | } else { | |
2649 | size = DIV_ROUND_UP((y + height) * fb->pitches[i] + | |
2650 | x * cpp, tile_size); | |
2651 | } | |
2652 | ||
2653 | /* how many tiles in total needed in the bo */ | |
2654 | max_size = max(max_size, offset + size); | |
2655 | } | |
2656 | ||
144cc143 VS |
2657 | if (max_size * tile_size > intel_fb->obj->base.size) { |
2658 | DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n", | |
2659 | max_size * tile_size, intel_fb->obj->base.size); | |
6687c906 VS |
2660 | return -EINVAL; |
2661 | } | |
2662 | ||
2663 | return 0; | |
2664 | } | |
2665 | ||
b35d63fa | 2666 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2667 | { |
2668 | switch (format) { | |
2669 | case DISPPLANE_8BPP: | |
2670 | return DRM_FORMAT_C8; | |
2671 | case DISPPLANE_BGRX555: | |
2672 | return DRM_FORMAT_XRGB1555; | |
2673 | case DISPPLANE_BGRX565: | |
2674 | return DRM_FORMAT_RGB565; | |
2675 | default: | |
2676 | case DISPPLANE_BGRX888: | |
2677 | return DRM_FORMAT_XRGB8888; | |
2678 | case DISPPLANE_RGBX888: | |
2679 | return DRM_FORMAT_XBGR8888; | |
2680 | case DISPPLANE_BGRX101010: | |
2681 | return DRM_FORMAT_XRGB2101010; | |
2682 | case DISPPLANE_RGBX101010: | |
2683 | return DRM_FORMAT_XBGR2101010; | |
2684 | } | |
2685 | } | |
2686 | ||
bc8d7dff DL |
2687 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2688 | { | |
2689 | switch (format) { | |
2690 | case PLANE_CTL_FORMAT_RGB_565: | |
2691 | return DRM_FORMAT_RGB565; | |
2692 | default: | |
2693 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2694 | if (rgb_order) { | |
2695 | if (alpha) | |
2696 | return DRM_FORMAT_ABGR8888; | |
2697 | else | |
2698 | return DRM_FORMAT_XBGR8888; | |
2699 | } else { | |
2700 | if (alpha) | |
2701 | return DRM_FORMAT_ARGB8888; | |
2702 | else | |
2703 | return DRM_FORMAT_XRGB8888; | |
2704 | } | |
2705 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2706 | if (rgb_order) | |
2707 | return DRM_FORMAT_XBGR2101010; | |
2708 | else | |
2709 | return DRM_FORMAT_XRGB2101010; | |
2710 | } | |
2711 | } | |
2712 | ||
5724dbd1 | 2713 | static bool |
f6936e29 DV |
2714 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2715 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2716 | { |
2717 | struct drm_device *dev = crtc->base.dev; | |
3badb49f | 2718 | struct drm_i915_private *dev_priv = to_i915(dev); |
72e96d64 | 2719 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
46f297fb JB |
2720 | struct drm_i915_gem_object *obj = NULL; |
2721 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2722 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2723 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2724 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2725 | PAGE_SIZE); | |
2726 | ||
2727 | size_aligned -= base_aligned; | |
46f297fb | 2728 | |
ff2652ea CW |
2729 | if (plane_config->size == 0) |
2730 | return false; | |
2731 | ||
3badb49f PZ |
2732 | /* If the FB is too big, just don't use it since fbdev is not very |
2733 | * important and we should probably use that space with FBC or other | |
2734 | * features. */ | |
72e96d64 | 2735 | if (size_aligned * 2 > ggtt->stolen_usable_size) |
3badb49f PZ |
2736 | return false; |
2737 | ||
12c83d99 | 2738 | mutex_lock(&dev->struct_mutex); |
187685cb | 2739 | obj = i915_gem_object_create_stolen_for_preallocated(dev_priv, |
f37b5c2b DV |
2740 | base_aligned, |
2741 | base_aligned, | |
2742 | size_aligned); | |
24dbf51a CW |
2743 | mutex_unlock(&dev->struct_mutex); |
2744 | if (!obj) | |
484b41dd | 2745 | return false; |
46f297fb | 2746 | |
3e510a8e CW |
2747 | if (plane_config->tiling == I915_TILING_X) |
2748 | obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X; | |
46f297fb | 2749 | |
438b74a5 | 2750 | mode_cmd.pixel_format = fb->format->format; |
6bf129df DL |
2751 | mode_cmd.width = fb->width; |
2752 | mode_cmd.height = fb->height; | |
2753 | mode_cmd.pitches[0] = fb->pitches[0]; | |
bae781b2 | 2754 | mode_cmd.modifier[0] = fb->modifier; |
18c5247e | 2755 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; |
46f297fb | 2756 | |
24dbf51a | 2757 | if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) { |
46f297fb JB |
2758 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2759 | goto out_unref_obj; | |
2760 | } | |
12c83d99 | 2761 | |
484b41dd | 2762 | |
f6936e29 | 2763 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2764 | return true; |
46f297fb JB |
2765 | |
2766 | out_unref_obj: | |
f8c417cd | 2767 | i915_gem_object_put(obj); |
484b41dd JB |
2768 | return false; |
2769 | } | |
2770 | ||
e9728bd8 VS |
2771 | static void |
2772 | intel_set_plane_visible(struct intel_crtc_state *crtc_state, | |
2773 | struct intel_plane_state *plane_state, | |
2774 | bool visible) | |
2775 | { | |
2776 | struct intel_plane *plane = to_intel_plane(plane_state->base.plane); | |
2777 | ||
2778 | plane_state->base.visible = visible; | |
2779 | ||
2780 | /* FIXME pre-g4x don't work like this */ | |
2781 | if (visible) { | |
2782 | crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base)); | |
2783 | crtc_state->active_planes |= BIT(plane->id); | |
2784 | } else { | |
2785 | crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base)); | |
2786 | crtc_state->active_planes &= ~BIT(plane->id); | |
2787 | } | |
2788 | ||
2789 | DRM_DEBUG_KMS("%s active planes 0x%x\n", | |
2790 | crtc_state->base.crtc->name, | |
2791 | crtc_state->active_planes); | |
2792 | } | |
2793 | ||
5724dbd1 | 2794 | static void |
f6936e29 DV |
2795 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2796 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2797 | { |
2798 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 2799 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd | 2800 | struct drm_crtc *c; |
2ff8fde1 | 2801 | struct drm_i915_gem_object *obj; |
88595ac9 | 2802 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2803 | struct drm_plane_state *plane_state = primary->state; |
200757f5 MR |
2804 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
2805 | struct intel_plane *intel_plane = to_intel_plane(primary); | |
0a8d8a86 MR |
2806 | struct intel_plane_state *intel_state = |
2807 | to_intel_plane_state(plane_state); | |
88595ac9 | 2808 | struct drm_framebuffer *fb; |
484b41dd | 2809 | |
2d14030b | 2810 | if (!plane_config->fb) |
484b41dd JB |
2811 | return; |
2812 | ||
f6936e29 | 2813 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2814 | fb = &plane_config->fb->base; |
2815 | goto valid_fb; | |
f55548b5 | 2816 | } |
484b41dd | 2817 | |
2d14030b | 2818 | kfree(plane_config->fb); |
484b41dd JB |
2819 | |
2820 | /* | |
2821 | * Failed to alloc the obj, check to see if we should share | |
2822 | * an fb with another CRTC instead | |
2823 | */ | |
70e1e0ec | 2824 | for_each_crtc(dev, c) { |
be1e3415 | 2825 | struct intel_plane_state *state; |
484b41dd JB |
2826 | |
2827 | if (c == &intel_crtc->base) | |
2828 | continue; | |
2829 | ||
be1e3415 | 2830 | if (!to_intel_crtc(c)->active) |
2ff8fde1 MR |
2831 | continue; |
2832 | ||
be1e3415 CW |
2833 | state = to_intel_plane_state(c->primary->state); |
2834 | if (!state->vma) | |
484b41dd JB |
2835 | continue; |
2836 | ||
be1e3415 CW |
2837 | if (intel_plane_ggtt_offset(state) == plane_config->base) { |
2838 | fb = c->primary->fb; | |
88595ac9 DV |
2839 | drm_framebuffer_reference(fb); |
2840 | goto valid_fb; | |
484b41dd JB |
2841 | } |
2842 | } | |
88595ac9 | 2843 | |
200757f5 MR |
2844 | /* |
2845 | * We've failed to reconstruct the BIOS FB. Current display state | |
2846 | * indicates that the primary plane is visible, but has a NULL FB, | |
2847 | * which will lead to problems later if we don't fix it up. The | |
2848 | * simplest solution is to just disable the primary plane now and | |
2849 | * pretend the BIOS never had it enabled. | |
2850 | */ | |
e9728bd8 VS |
2851 | intel_set_plane_visible(to_intel_crtc_state(crtc_state), |
2852 | to_intel_plane_state(plane_state), | |
2853 | false); | |
2622a081 | 2854 | intel_pre_disable_primary_noatomic(&intel_crtc->base); |
72259536 | 2855 | trace_intel_disable_plane(primary, intel_crtc); |
282dbf9b | 2856 | intel_plane->disable_plane(intel_plane, intel_crtc); |
200757f5 | 2857 | |
88595ac9 DV |
2858 | return; |
2859 | ||
2860 | valid_fb: | |
be1e3415 CW |
2861 | mutex_lock(&dev->struct_mutex); |
2862 | intel_state->vma = | |
2863 | intel_pin_and_fence_fb_obj(fb, primary->state->rotation); | |
2864 | mutex_unlock(&dev->struct_mutex); | |
2865 | if (IS_ERR(intel_state->vma)) { | |
2866 | DRM_ERROR("failed to pin boot fb on pipe %d: %li\n", | |
2867 | intel_crtc->pipe, PTR_ERR(intel_state->vma)); | |
2868 | ||
2869 | intel_state->vma = NULL; | |
2870 | drm_framebuffer_unreference(fb); | |
2871 | return; | |
2872 | } | |
2873 | ||
f44e2659 VS |
2874 | plane_state->src_x = 0; |
2875 | plane_state->src_y = 0; | |
be5651f2 ML |
2876 | plane_state->src_w = fb->width << 16; |
2877 | plane_state->src_h = fb->height << 16; | |
2878 | ||
f44e2659 VS |
2879 | plane_state->crtc_x = 0; |
2880 | plane_state->crtc_y = 0; | |
be5651f2 ML |
2881 | plane_state->crtc_w = fb->width; |
2882 | plane_state->crtc_h = fb->height; | |
2883 | ||
1638d30c RC |
2884 | intel_state->base.src = drm_plane_state_src(plane_state); |
2885 | intel_state->base.dst = drm_plane_state_dest(plane_state); | |
0a8d8a86 | 2886 | |
88595ac9 | 2887 | obj = intel_fb_obj(fb); |
3e510a8e | 2888 | if (i915_gem_object_is_tiled(obj)) |
88595ac9 DV |
2889 | dev_priv->preserve_bios_swizzle = true; |
2890 | ||
be5651f2 ML |
2891 | drm_framebuffer_reference(fb); |
2892 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2893 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
e9728bd8 VS |
2894 | |
2895 | intel_set_plane_visible(to_intel_crtc_state(crtc_state), | |
2896 | to_intel_plane_state(plane_state), | |
2897 | true); | |
2898 | ||
faf5bf0a CW |
2899 | atomic_or(to_intel_plane(primary)->frontbuffer_bit, |
2900 | &obj->frontbuffer_bits); | |
46f297fb JB |
2901 | } |
2902 | ||
b63a16f6 VS |
2903 | static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane, |
2904 | unsigned int rotation) | |
2905 | { | |
353c8598 | 2906 | int cpp = fb->format->cpp[plane]; |
b63a16f6 | 2907 | |
bae781b2 | 2908 | switch (fb->modifier) { |
2f075565 | 2909 | case DRM_FORMAT_MOD_LINEAR: |
b63a16f6 VS |
2910 | case I915_FORMAT_MOD_X_TILED: |
2911 | switch (cpp) { | |
2912 | case 8: | |
2913 | return 4096; | |
2914 | case 4: | |
2915 | case 2: | |
2916 | case 1: | |
2917 | return 8192; | |
2918 | default: | |
2919 | MISSING_CASE(cpp); | |
2920 | break; | |
2921 | } | |
2922 | break; | |
2e2adb05 VS |
2923 | case I915_FORMAT_MOD_Y_TILED_CCS: |
2924 | case I915_FORMAT_MOD_Yf_TILED_CCS: | |
2925 | /* FIXME AUX plane? */ | |
b63a16f6 VS |
2926 | case I915_FORMAT_MOD_Y_TILED: |
2927 | case I915_FORMAT_MOD_Yf_TILED: | |
2928 | switch (cpp) { | |
2929 | case 8: | |
2930 | return 2048; | |
2931 | case 4: | |
2932 | return 4096; | |
2933 | case 2: | |
2934 | case 1: | |
2935 | return 8192; | |
2936 | default: | |
2937 | MISSING_CASE(cpp); | |
2938 | break; | |
2939 | } | |
2940 | break; | |
2941 | default: | |
bae781b2 | 2942 | MISSING_CASE(fb->modifier); |
b63a16f6 VS |
2943 | } |
2944 | ||
2945 | return 2048; | |
2946 | } | |
2947 | ||
2e2adb05 VS |
2948 | static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state, |
2949 | int main_x, int main_y, u32 main_offset) | |
2950 | { | |
2951 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
2952 | int hsub = fb->format->hsub; | |
2953 | int vsub = fb->format->vsub; | |
2954 | int aux_x = plane_state->aux.x; | |
2955 | int aux_y = plane_state->aux.y; | |
2956 | u32 aux_offset = plane_state->aux.offset; | |
2957 | u32 alignment = intel_surf_alignment(fb, 1); | |
2958 | ||
2959 | while (aux_offset >= main_offset && aux_y <= main_y) { | |
2960 | int x, y; | |
2961 | ||
2962 | if (aux_x == main_x && aux_y == main_y) | |
2963 | break; | |
2964 | ||
2965 | if (aux_offset == 0) | |
2966 | break; | |
2967 | ||
2968 | x = aux_x / hsub; | |
2969 | y = aux_y / vsub; | |
2970 | aux_offset = intel_adjust_tile_offset(&x, &y, plane_state, 1, | |
2971 | aux_offset, aux_offset - alignment); | |
2972 | aux_x = x * hsub + aux_x % hsub; | |
2973 | aux_y = y * vsub + aux_y % vsub; | |
2974 | } | |
2975 | ||
2976 | if (aux_x != main_x || aux_y != main_y) | |
2977 | return false; | |
2978 | ||
2979 | plane_state->aux.offset = aux_offset; | |
2980 | plane_state->aux.x = aux_x; | |
2981 | plane_state->aux.y = aux_y; | |
2982 | ||
2983 | return true; | |
2984 | } | |
2985 | ||
b63a16f6 VS |
2986 | static int skl_check_main_surface(struct intel_plane_state *plane_state) |
2987 | { | |
b63a16f6 VS |
2988 | const struct drm_framebuffer *fb = plane_state->base.fb; |
2989 | unsigned int rotation = plane_state->base.rotation; | |
cc926387 DV |
2990 | int x = plane_state->base.src.x1 >> 16; |
2991 | int y = plane_state->base.src.y1 >> 16; | |
2992 | int w = drm_rect_width(&plane_state->base.src) >> 16; | |
2993 | int h = drm_rect_height(&plane_state->base.src) >> 16; | |
b63a16f6 VS |
2994 | int max_width = skl_max_plane_width(fb, 0, rotation); |
2995 | int max_height = 4096; | |
8d970654 | 2996 | u32 alignment, offset, aux_offset = plane_state->aux.offset; |
b63a16f6 VS |
2997 | |
2998 | if (w > max_width || h > max_height) { | |
2999 | DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n", | |
3000 | w, h, max_width, max_height); | |
3001 | return -EINVAL; | |
3002 | } | |
3003 | ||
3004 | intel_add_fb_offsets(&x, &y, plane_state, 0); | |
3005 | offset = intel_compute_tile_offset(&x, &y, plane_state, 0); | |
d88c4afd | 3006 | alignment = intel_surf_alignment(fb, 0); |
b63a16f6 | 3007 | |
8d970654 VS |
3008 | /* |
3009 | * AUX surface offset is specified as the distance from the | |
3010 | * main surface offset, and it must be non-negative. Make | |
3011 | * sure that is what we will get. | |
3012 | */ | |
3013 | if (offset > aux_offset) | |
3014 | offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, | |
3015 | offset, aux_offset & ~(alignment - 1)); | |
3016 | ||
b63a16f6 VS |
3017 | /* |
3018 | * When using an X-tiled surface, the plane blows up | |
3019 | * if the x offset + width exceed the stride. | |
3020 | * | |
3021 | * TODO: linear and Y-tiled seem fine, Yf untested, | |
3022 | */ | |
bae781b2 | 3023 | if (fb->modifier == I915_FORMAT_MOD_X_TILED) { |
353c8598 | 3024 | int cpp = fb->format->cpp[0]; |
b63a16f6 VS |
3025 | |
3026 | while ((x + w) * cpp > fb->pitches[0]) { | |
3027 | if (offset == 0) { | |
2e2adb05 | 3028 | DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n"); |
b63a16f6 VS |
3029 | return -EINVAL; |
3030 | } | |
3031 | ||
3032 | offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, | |
3033 | offset, offset - alignment); | |
3034 | } | |
3035 | } | |
3036 | ||
2e2adb05 VS |
3037 | /* |
3038 | * CCS AUX surface doesn't have its own x/y offsets, we must make sure | |
3039 | * they match with the main surface x/y offsets. | |
3040 | */ | |
3041 | if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || | |
3042 | fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) { | |
3043 | while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) { | |
3044 | if (offset == 0) | |
3045 | break; | |
3046 | ||
3047 | offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, | |
3048 | offset, offset - alignment); | |
3049 | } | |
3050 | ||
3051 | if (x != plane_state->aux.x || y != plane_state->aux.y) { | |
3052 | DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n"); | |
3053 | return -EINVAL; | |
3054 | } | |
3055 | } | |
3056 | ||
b63a16f6 VS |
3057 | plane_state->main.offset = offset; |
3058 | plane_state->main.x = x; | |
3059 | plane_state->main.y = y; | |
3060 | ||
3061 | return 0; | |
3062 | } | |
3063 | ||
8d970654 VS |
3064 | static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) |
3065 | { | |
3066 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
3067 | unsigned int rotation = plane_state->base.rotation; | |
3068 | int max_width = skl_max_plane_width(fb, 1, rotation); | |
3069 | int max_height = 4096; | |
cc926387 DV |
3070 | int x = plane_state->base.src.x1 >> 17; |
3071 | int y = plane_state->base.src.y1 >> 17; | |
3072 | int w = drm_rect_width(&plane_state->base.src) >> 17; | |
3073 | int h = drm_rect_height(&plane_state->base.src) >> 17; | |
8d970654 VS |
3074 | u32 offset; |
3075 | ||
3076 | intel_add_fb_offsets(&x, &y, plane_state, 1); | |
3077 | offset = intel_compute_tile_offset(&x, &y, plane_state, 1); | |
3078 | ||
3079 | /* FIXME not quite sure how/if these apply to the chroma plane */ | |
3080 | if (w > max_width || h > max_height) { | |
3081 | DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n", | |
3082 | w, h, max_width, max_height); | |
3083 | return -EINVAL; | |
3084 | } | |
3085 | ||
3086 | plane_state->aux.offset = offset; | |
3087 | plane_state->aux.x = x; | |
3088 | plane_state->aux.y = y; | |
3089 | ||
3090 | return 0; | |
3091 | } | |
3092 | ||
2e2adb05 VS |
3093 | static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state) |
3094 | { | |
3095 | struct intel_plane *plane = to_intel_plane(plane_state->base.plane); | |
3096 | struct intel_crtc *crtc = to_intel_crtc(plane_state->base.crtc); | |
3097 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
3098 | int src_x = plane_state->base.src.x1 >> 16; | |
3099 | int src_y = plane_state->base.src.y1 >> 16; | |
3100 | int hsub = fb->format->hsub; | |
3101 | int vsub = fb->format->vsub; | |
3102 | int x = src_x / hsub; | |
3103 | int y = src_y / vsub; | |
3104 | u32 offset; | |
3105 | ||
3106 | switch (plane->id) { | |
3107 | case PLANE_PRIMARY: | |
3108 | case PLANE_SPRITE0: | |
3109 | break; | |
3110 | default: | |
3111 | DRM_DEBUG_KMS("RC support only on plane 1 and 2\n"); | |
3112 | return -EINVAL; | |
3113 | } | |
3114 | ||
3115 | if (crtc->pipe == PIPE_C) { | |
3116 | DRM_DEBUG_KMS("No RC support on pipe C\n"); | |
3117 | return -EINVAL; | |
3118 | } | |
3119 | ||
3120 | if (plane_state->base.rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180)) { | |
3121 | DRM_DEBUG_KMS("RC support only with 0/180 degree rotation %x\n", | |
3122 | plane_state->base.rotation); | |
3123 | return -EINVAL; | |
3124 | } | |
3125 | ||
3126 | intel_add_fb_offsets(&x, &y, plane_state, 1); | |
3127 | offset = intel_compute_tile_offset(&x, &y, plane_state, 1); | |
3128 | ||
3129 | plane_state->aux.offset = offset; | |
3130 | plane_state->aux.x = x * hsub + src_x % hsub; | |
3131 | plane_state->aux.y = y * vsub + src_y % vsub; | |
3132 | ||
3133 | return 0; | |
3134 | } | |
3135 | ||
b63a16f6 VS |
3136 | int skl_check_plane_surface(struct intel_plane_state *plane_state) |
3137 | { | |
3138 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
3139 | unsigned int rotation = plane_state->base.rotation; | |
3140 | int ret; | |
3141 | ||
a5e4c7d0 VS |
3142 | if (!plane_state->base.visible) |
3143 | return 0; | |
3144 | ||
b63a16f6 | 3145 | /* Rotate src coordinates to match rotated GTT view */ |
bd2ef25d | 3146 | if (drm_rotation_90_or_270(rotation)) |
cc926387 | 3147 | drm_rect_rotate(&plane_state->base.src, |
da064b47 | 3148 | fb->width << 16, fb->height << 16, |
c2c446ad | 3149 | DRM_MODE_ROTATE_270); |
b63a16f6 | 3150 | |
8d970654 VS |
3151 | /* |
3152 | * Handle the AUX surface first since | |
3153 | * the main surface setup depends on it. | |
3154 | */ | |
438b74a5 | 3155 | if (fb->format->format == DRM_FORMAT_NV12) { |
8d970654 VS |
3156 | ret = skl_check_nv12_aux_surface(plane_state); |
3157 | if (ret) | |
3158 | return ret; | |
2e2adb05 VS |
3159 | } else if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || |
3160 | fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) { | |
3161 | ret = skl_check_ccs_aux_surface(plane_state); | |
3162 | if (ret) | |
3163 | return ret; | |
8d970654 VS |
3164 | } else { |
3165 | plane_state->aux.offset = ~0xfff; | |
3166 | plane_state->aux.x = 0; | |
3167 | plane_state->aux.y = 0; | |
3168 | } | |
3169 | ||
b63a16f6 VS |
3170 | ret = skl_check_main_surface(plane_state); |
3171 | if (ret) | |
3172 | return ret; | |
3173 | ||
3174 | return 0; | |
3175 | } | |
3176 | ||
7145f60a VS |
3177 | static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state, |
3178 | const struct intel_plane_state *plane_state) | |
81255565 | 3179 | { |
7145f60a VS |
3180 | struct drm_i915_private *dev_priv = |
3181 | to_i915(plane_state->base.plane->dev); | |
3182 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
3183 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
8d0deca8 | 3184 | unsigned int rotation = plane_state->base.rotation; |
7145f60a | 3185 | u32 dspcntr; |
c9ba6fad | 3186 | |
7145f60a | 3187 | dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE; |
f45651ba | 3188 | |
6a4407a6 VS |
3189 | if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) || |
3190 | IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) | |
7145f60a | 3191 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
f45651ba | 3192 | |
6a4407a6 VS |
3193 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
3194 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
f45651ba | 3195 | |
d509e28b VS |
3196 | if (INTEL_GEN(dev_priv) < 4) |
3197 | dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe); | |
81255565 | 3198 | |
438b74a5 | 3199 | switch (fb->format->format) { |
57779d06 | 3200 | case DRM_FORMAT_C8: |
81255565 JB |
3201 | dspcntr |= DISPPLANE_8BPP; |
3202 | break; | |
57779d06 | 3203 | case DRM_FORMAT_XRGB1555: |
57779d06 | 3204 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 3205 | break; |
57779d06 VS |
3206 | case DRM_FORMAT_RGB565: |
3207 | dspcntr |= DISPPLANE_BGRX565; | |
3208 | break; | |
3209 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
3210 | dspcntr |= DISPPLANE_BGRX888; |
3211 | break; | |
3212 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
3213 | dspcntr |= DISPPLANE_RGBX888; |
3214 | break; | |
3215 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
3216 | dspcntr |= DISPPLANE_BGRX101010; |
3217 | break; | |
3218 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 3219 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
3220 | break; |
3221 | default: | |
7145f60a VS |
3222 | MISSING_CASE(fb->format->format); |
3223 | return 0; | |
81255565 | 3224 | } |
57779d06 | 3225 | |
72618ebf | 3226 | if (INTEL_GEN(dev_priv) >= 4 && |
bae781b2 | 3227 | fb->modifier == I915_FORMAT_MOD_X_TILED) |
f45651ba | 3228 | dspcntr |= DISPPLANE_TILED; |
81255565 | 3229 | |
c2c446ad | 3230 | if (rotation & DRM_MODE_ROTATE_180) |
df0cd455 VS |
3231 | dspcntr |= DISPPLANE_ROTATE_180; |
3232 | ||
c2c446ad | 3233 | if (rotation & DRM_MODE_REFLECT_X) |
4ea7be2b VS |
3234 | dspcntr |= DISPPLANE_MIRROR; |
3235 | ||
7145f60a VS |
3236 | return dspcntr; |
3237 | } | |
de1aa629 | 3238 | |
f9407ae1 | 3239 | int i9xx_check_plane_surface(struct intel_plane_state *plane_state) |
5b7fcc44 VS |
3240 | { |
3241 | struct drm_i915_private *dev_priv = | |
3242 | to_i915(plane_state->base.plane->dev); | |
3243 | int src_x = plane_state->base.src.x1 >> 16; | |
3244 | int src_y = plane_state->base.src.y1 >> 16; | |
3245 | u32 offset; | |
81255565 | 3246 | |
5b7fcc44 | 3247 | intel_add_fb_offsets(&src_x, &src_y, plane_state, 0); |
e506a0c6 | 3248 | |
5b7fcc44 VS |
3249 | if (INTEL_GEN(dev_priv) >= 4) |
3250 | offset = intel_compute_tile_offset(&src_x, &src_y, | |
3251 | plane_state, 0); | |
3252 | else | |
3253 | offset = 0; | |
3254 | ||
3255 | /* HSW/BDW do this automagically in hardware */ | |
3256 | if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) { | |
3257 | unsigned int rotation = plane_state->base.rotation; | |
3258 | int src_w = drm_rect_width(&plane_state->base.src) >> 16; | |
3259 | int src_h = drm_rect_height(&plane_state->base.src) >> 16; | |
3260 | ||
c2c446ad | 3261 | if (rotation & DRM_MODE_ROTATE_180) { |
5b7fcc44 VS |
3262 | src_x += src_w - 1; |
3263 | src_y += src_h - 1; | |
c2c446ad | 3264 | } else if (rotation & DRM_MODE_REFLECT_X) { |
5b7fcc44 VS |
3265 | src_x += src_w - 1; |
3266 | } | |
48404c1e SJ |
3267 | } |
3268 | ||
5b7fcc44 VS |
3269 | plane_state->main.offset = offset; |
3270 | plane_state->main.x = src_x; | |
3271 | plane_state->main.y = src_y; | |
3272 | ||
3273 | return 0; | |
3274 | } | |
3275 | ||
282dbf9b | 3276 | static void i9xx_update_primary_plane(struct intel_plane *primary, |
7145f60a VS |
3277 | const struct intel_crtc_state *crtc_state, |
3278 | const struct intel_plane_state *plane_state) | |
3279 | { | |
282dbf9b VS |
3280 | struct drm_i915_private *dev_priv = to_i915(primary->base.dev); |
3281 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
3282 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
3283 | enum plane plane = primary->plane; | |
7145f60a | 3284 | u32 linear_offset; |
a0864d59 | 3285 | u32 dspcntr = plane_state->ctl; |
7145f60a | 3286 | i915_reg_t reg = DSPCNTR(plane); |
5b7fcc44 VS |
3287 | int x = plane_state->main.x; |
3288 | int y = plane_state->main.y; | |
7145f60a VS |
3289 | unsigned long irqflags; |
3290 | ||
2949056c | 3291 | linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); |
6687c906 | 3292 | |
5b7fcc44 | 3293 | if (INTEL_GEN(dev_priv) >= 4) |
282dbf9b | 3294 | crtc->dspaddr_offset = plane_state->main.offset; |
5b7fcc44 | 3295 | else |
282dbf9b | 3296 | crtc->dspaddr_offset = linear_offset; |
6687c906 | 3297 | |
282dbf9b VS |
3298 | crtc->adjusted_x = x; |
3299 | crtc->adjusted_y = y; | |
2db3366b | 3300 | |
dd584fc0 VS |
3301 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
3302 | ||
78587de2 VS |
3303 | if (INTEL_GEN(dev_priv) < 4) { |
3304 | /* pipesrc and dspsize control the size that is scaled from, | |
3305 | * which should always be the user's requested size. | |
3306 | */ | |
dd584fc0 VS |
3307 | I915_WRITE_FW(DSPSIZE(plane), |
3308 | ((crtc_state->pipe_src_h - 1) << 16) | | |
3309 | (crtc_state->pipe_src_w - 1)); | |
3310 | I915_WRITE_FW(DSPPOS(plane), 0); | |
78587de2 | 3311 | } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) { |
dd584fc0 VS |
3312 | I915_WRITE_FW(PRIMSIZE(plane), |
3313 | ((crtc_state->pipe_src_h - 1) << 16) | | |
3314 | (crtc_state->pipe_src_w - 1)); | |
3315 | I915_WRITE_FW(PRIMPOS(plane), 0); | |
3316 | I915_WRITE_FW(PRIMCNSTALPHA(plane), 0); | |
78587de2 VS |
3317 | } |
3318 | ||
dd584fc0 | 3319 | I915_WRITE_FW(reg, dspcntr); |
48404c1e | 3320 | |
dd584fc0 | 3321 | I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]); |
3ba35e53 VS |
3322 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
3323 | I915_WRITE_FW(DSPSURF(plane), | |
3324 | intel_plane_ggtt_offset(plane_state) + | |
282dbf9b | 3325 | crtc->dspaddr_offset); |
3ba35e53 VS |
3326 | I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x); |
3327 | } else if (INTEL_GEN(dev_priv) >= 4) { | |
dd584fc0 VS |
3328 | I915_WRITE_FW(DSPSURF(plane), |
3329 | intel_plane_ggtt_offset(plane_state) + | |
282dbf9b | 3330 | crtc->dspaddr_offset); |
dd584fc0 VS |
3331 | I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x); |
3332 | I915_WRITE_FW(DSPLINOFF(plane), linear_offset); | |
bfb81049 | 3333 | } else { |
dd584fc0 VS |
3334 | I915_WRITE_FW(DSPADDR(plane), |
3335 | intel_plane_ggtt_offset(plane_state) + | |
282dbf9b | 3336 | crtc->dspaddr_offset); |
bfb81049 | 3337 | } |
dd584fc0 VS |
3338 | POSTING_READ_FW(reg); |
3339 | ||
3340 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
17638cd6 JB |
3341 | } |
3342 | ||
282dbf9b VS |
3343 | static void i9xx_disable_primary_plane(struct intel_plane *primary, |
3344 | struct intel_crtc *crtc) | |
17638cd6 | 3345 | { |
282dbf9b VS |
3346 | struct drm_i915_private *dev_priv = to_i915(primary->base.dev); |
3347 | enum plane plane = primary->plane; | |
dd584fc0 VS |
3348 | unsigned long irqflags; |
3349 | ||
3350 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
f45651ba | 3351 | |
dd584fc0 | 3352 | I915_WRITE_FW(DSPCNTR(plane), 0); |
a8d201af | 3353 | if (INTEL_INFO(dev_priv)->gen >= 4) |
dd584fc0 | 3354 | I915_WRITE_FW(DSPSURF(plane), 0); |
a8d201af | 3355 | else |
dd584fc0 VS |
3356 | I915_WRITE_FW(DSPADDR(plane), 0); |
3357 | POSTING_READ_FW(DSPCNTR(plane)); | |
3358 | ||
3359 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
a8d201af | 3360 | } |
c9ba6fad | 3361 | |
d88c4afd VS |
3362 | static u32 |
3363 | intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane) | |
b321803d | 3364 | { |
2f075565 | 3365 | if (fb->modifier == DRM_FORMAT_MOD_LINEAR) |
b321803d | 3366 | return 64; |
d88c4afd VS |
3367 | else |
3368 | return intel_tile_width_bytes(fb, plane); | |
b321803d DL |
3369 | } |
3370 | ||
e435d6e5 ML |
3371 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
3372 | { | |
3373 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 3374 | struct drm_i915_private *dev_priv = to_i915(dev); |
e435d6e5 ML |
3375 | |
3376 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
3377 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
3378 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
3379 | } |
3380 | ||
a1b2278e CK |
3381 | /* |
3382 | * This function detaches (aka. unbinds) unused scalers in hardware | |
3383 | */ | |
0583236e | 3384 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 3385 | { |
a1b2278e CK |
3386 | struct intel_crtc_scaler_state *scaler_state; |
3387 | int i; | |
3388 | ||
a1b2278e CK |
3389 | scaler_state = &intel_crtc->config->scaler_state; |
3390 | ||
3391 | /* loop through and disable scalers that aren't in use */ | |
3392 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
3393 | if (!scaler_state->scalers[i].in_use) |
3394 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
3395 | } |
3396 | } | |
3397 | ||
d2196774 VS |
3398 | u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane, |
3399 | unsigned int rotation) | |
3400 | { | |
1b500535 VS |
3401 | u32 stride; |
3402 | ||
3403 | if (plane >= fb->format->num_planes) | |
3404 | return 0; | |
3405 | ||
3406 | stride = intel_fb_pitch(fb, plane, rotation); | |
d2196774 VS |
3407 | |
3408 | /* | |
3409 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
3410 | * linear buffers or in number of tiles for tiled buffers. | |
3411 | */ | |
d88c4afd VS |
3412 | if (drm_rotation_90_or_270(rotation)) |
3413 | stride /= intel_tile_height(fb, plane); | |
3414 | else | |
3415 | stride /= intel_fb_stride_alignment(fb, plane); | |
d2196774 VS |
3416 | |
3417 | return stride; | |
3418 | } | |
3419 | ||
2e881264 | 3420 | static u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 3421 | { |
6156a456 | 3422 | switch (pixel_format) { |
d161cf7a | 3423 | case DRM_FORMAT_C8: |
c34ce3d1 | 3424 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 3425 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 3426 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 3427 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 3428 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 3429 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 3430 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
3431 | /* |
3432 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
3433 | * to be already pre-multiplied. We need to add a knob (or a different | |
3434 | * DRM_FORMAT) for user-space to configure that. | |
3435 | */ | |
f75fb42a | 3436 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 3437 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 3438 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 3439 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 3440 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 3441 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 3442 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 3443 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 3444 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 3445 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 3446 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 3447 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 3448 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 3449 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 3450 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 3451 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 3452 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 3453 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 3454 | default: |
4249eeef | 3455 | MISSING_CASE(pixel_format); |
70d21f0e | 3456 | } |
8cfcba41 | 3457 | |
c34ce3d1 | 3458 | return 0; |
6156a456 | 3459 | } |
70d21f0e | 3460 | |
2e881264 | 3461 | static u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
6156a456 | 3462 | { |
6156a456 | 3463 | switch (fb_modifier) { |
2f075565 | 3464 | case DRM_FORMAT_MOD_LINEAR: |
70d21f0e | 3465 | break; |
30af77c4 | 3466 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 3467 | return PLANE_CTL_TILED_X; |
b321803d | 3468 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 3469 | return PLANE_CTL_TILED_Y; |
2e2adb05 VS |
3470 | case I915_FORMAT_MOD_Y_TILED_CCS: |
3471 | return PLANE_CTL_TILED_Y | PLANE_CTL_DECOMPRESSION_ENABLE; | |
b321803d | 3472 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 3473 | return PLANE_CTL_TILED_YF; |
2e2adb05 VS |
3474 | case I915_FORMAT_MOD_Yf_TILED_CCS: |
3475 | return PLANE_CTL_TILED_YF | PLANE_CTL_DECOMPRESSION_ENABLE; | |
70d21f0e | 3476 | default: |
6156a456 | 3477 | MISSING_CASE(fb_modifier); |
70d21f0e | 3478 | } |
8cfcba41 | 3479 | |
c34ce3d1 | 3480 | return 0; |
6156a456 | 3481 | } |
70d21f0e | 3482 | |
2e881264 | 3483 | static u32 skl_plane_ctl_rotation(unsigned int rotation) |
6156a456 | 3484 | { |
3b7a5119 | 3485 | switch (rotation) { |
c2c446ad | 3486 | case DRM_MODE_ROTATE_0: |
6156a456 | 3487 | break; |
1e8df167 | 3488 | /* |
c2c446ad | 3489 | * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr |
1e8df167 SJ |
3490 | * while i915 HW rotation is clockwise, thats why this swapping. |
3491 | */ | |
c2c446ad | 3492 | case DRM_MODE_ROTATE_90: |
1e8df167 | 3493 | return PLANE_CTL_ROTATE_270; |
c2c446ad | 3494 | case DRM_MODE_ROTATE_180: |
c34ce3d1 | 3495 | return PLANE_CTL_ROTATE_180; |
c2c446ad | 3496 | case DRM_MODE_ROTATE_270: |
1e8df167 | 3497 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
3498 | default: |
3499 | MISSING_CASE(rotation); | |
3500 | } | |
3501 | ||
c34ce3d1 | 3502 | return 0; |
6156a456 CK |
3503 | } |
3504 | ||
2e881264 VS |
3505 | u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, |
3506 | const struct intel_plane_state *plane_state) | |
46f788ba VS |
3507 | { |
3508 | struct drm_i915_private *dev_priv = | |
3509 | to_i915(plane_state->base.plane->dev); | |
3510 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
3511 | unsigned int rotation = plane_state->base.rotation; | |
2e881264 | 3512 | const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; |
46f788ba VS |
3513 | u32 plane_ctl; |
3514 | ||
3515 | plane_ctl = PLANE_CTL_ENABLE; | |
3516 | ||
6602be0e | 3517 | if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) { |
46f788ba VS |
3518 | plane_ctl |= |
3519 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3520 | PLANE_CTL_PIPE_CSC_ENABLE | | |
3521 | PLANE_CTL_PLANE_GAMMA_DISABLE; | |
3522 | } | |
3523 | ||
3524 | plane_ctl |= skl_plane_ctl_format(fb->format->format); | |
3525 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier); | |
3526 | plane_ctl |= skl_plane_ctl_rotation(rotation); | |
3527 | ||
2e881264 VS |
3528 | if (key->flags & I915_SET_COLORKEY_DESTINATION) |
3529 | plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION; | |
3530 | else if (key->flags & I915_SET_COLORKEY_SOURCE) | |
3531 | plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE; | |
3532 | ||
46f788ba VS |
3533 | return plane_ctl; |
3534 | } | |
3535 | ||
282dbf9b | 3536 | static void skylake_update_primary_plane(struct intel_plane *plane, |
a8d201af ML |
3537 | const struct intel_crtc_state *crtc_state, |
3538 | const struct intel_plane_state *plane_state) | |
6156a456 | 3539 | { |
282dbf9b VS |
3540 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
3541 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
3542 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
3543 | enum plane_id plane_id = plane->id; | |
3544 | enum pipe pipe = plane->pipe; | |
a0864d59 | 3545 | u32 plane_ctl = plane_state->ctl; |
a8d201af | 3546 | unsigned int rotation = plane_state->base.rotation; |
d2196774 | 3547 | u32 stride = skl_plane_stride(fb, 0, rotation); |
2e2adb05 | 3548 | u32 aux_stride = skl_plane_stride(fb, 1, rotation); |
b63a16f6 | 3549 | u32 surf_addr = plane_state->main.offset; |
a8d201af | 3550 | int scaler_id = plane_state->scaler_id; |
b63a16f6 VS |
3551 | int src_x = plane_state->main.x; |
3552 | int src_y = plane_state->main.y; | |
936e71e3 VS |
3553 | int src_w = drm_rect_width(&plane_state->base.src) >> 16; |
3554 | int src_h = drm_rect_height(&plane_state->base.src) >> 16; | |
3555 | int dst_x = plane_state->base.dst.x1; | |
3556 | int dst_y = plane_state->base.dst.y1; | |
3557 | int dst_w = drm_rect_width(&plane_state->base.dst); | |
3558 | int dst_h = drm_rect_height(&plane_state->base.dst); | |
dd584fc0 | 3559 | unsigned long irqflags; |
70d21f0e | 3560 | |
6687c906 VS |
3561 | /* Sizes are 0 based */ |
3562 | src_w--; | |
3563 | src_h--; | |
3564 | dst_w--; | |
3565 | dst_h--; | |
3566 | ||
282dbf9b | 3567 | crtc->dspaddr_offset = surf_addr; |
4c0b8a8b | 3568 | |
282dbf9b VS |
3569 | crtc->adjusted_x = src_x; |
3570 | crtc->adjusted_y = src_y; | |
2db3366b | 3571 | |
dd584fc0 VS |
3572 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
3573 | ||
6602be0e | 3574 | if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) { |
dd584fc0 VS |
3575 | I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id), |
3576 | PLANE_COLOR_PIPE_GAMMA_ENABLE | | |
3577 | PLANE_COLOR_PIPE_CSC_ENABLE | | |
3578 | PLANE_COLOR_PLANE_GAMMA_DISABLE); | |
78587de2 VS |
3579 | } |
3580 | ||
dd584fc0 VS |
3581 | I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl); |
3582 | I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x); | |
3583 | I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride); | |
3584 | I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w); | |
2e2adb05 VS |
3585 | I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id), |
3586 | (plane_state->aux.offset - surf_addr) | aux_stride); | |
3587 | I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id), | |
3588 | (plane_state->aux.y << 16) | plane_state->aux.x); | |
6156a456 CK |
3589 | |
3590 | if (scaler_id >= 0) { | |
3591 | uint32_t ps_ctrl = 0; | |
3592 | ||
3593 | WARN_ON(!dst_w || !dst_h); | |
8e816bb4 | 3594 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) | |
6156a456 | 3595 | crtc_state->scaler_state.scalers[scaler_id].mode; |
dd584fc0 VS |
3596 | I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); |
3597 | I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3598 | I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3599 | I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3600 | I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0); | |
6156a456 | 3601 | } else { |
dd584fc0 | 3602 | I915_WRITE_FW(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x); |
6156a456 CK |
3603 | } |
3604 | ||
dd584fc0 VS |
3605 | I915_WRITE_FW(PLANE_SURF(pipe, plane_id), |
3606 | intel_plane_ggtt_offset(plane_state) + surf_addr); | |
70d21f0e | 3607 | |
dd584fc0 VS |
3608 | POSTING_READ_FW(PLANE_SURF(pipe, plane_id)); |
3609 | ||
3610 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
70d21f0e DL |
3611 | } |
3612 | ||
282dbf9b VS |
3613 | static void skylake_disable_primary_plane(struct intel_plane *primary, |
3614 | struct intel_crtc *crtc) | |
17638cd6 | 3615 | { |
282dbf9b VS |
3616 | struct drm_i915_private *dev_priv = to_i915(primary->base.dev); |
3617 | enum plane_id plane_id = primary->id; | |
3618 | enum pipe pipe = primary->pipe; | |
dd584fc0 VS |
3619 | unsigned long irqflags; |
3620 | ||
3621 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
62e0fb88 | 3622 | |
dd584fc0 VS |
3623 | I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0); |
3624 | I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0); | |
3625 | POSTING_READ_FW(PLANE_SURF(pipe, plane_id)); | |
3626 | ||
3627 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
a8d201af | 3628 | } |
29b9bde6 | 3629 | |
73974893 ML |
3630 | static int |
3631 | __intel_display_resume(struct drm_device *dev, | |
581e49fe ML |
3632 | struct drm_atomic_state *state, |
3633 | struct drm_modeset_acquire_ctx *ctx) | |
73974893 ML |
3634 | { |
3635 | struct drm_crtc_state *crtc_state; | |
3636 | struct drm_crtc *crtc; | |
3637 | int i, ret; | |
11c22da6 | 3638 | |
aecd36b8 | 3639 | intel_modeset_setup_hw_state(dev, ctx); |
29b74b7f | 3640 | i915_redisable_vga(to_i915(dev)); |
73974893 ML |
3641 | |
3642 | if (!state) | |
3643 | return 0; | |
3644 | ||
aa5e9b47 ML |
3645 | /* |
3646 | * We've duplicated the state, pointers to the old state are invalid. | |
3647 | * | |
3648 | * Don't attempt to use the old state until we commit the duplicated state. | |
3649 | */ | |
3650 | for_each_new_crtc_in_state(state, crtc, crtc_state, i) { | |
73974893 ML |
3651 | /* |
3652 | * Force recalculation even if we restore | |
3653 | * current state. With fast modeset this may not result | |
3654 | * in a modeset when the state is compatible. | |
3655 | */ | |
3656 | crtc_state->mode_changed = true; | |
96a02917 | 3657 | } |
73974893 ML |
3658 | |
3659 | /* ignore any reset values/BIOS leftovers in the WM registers */ | |
602ae835 VS |
3660 | if (!HAS_GMCH_DISPLAY(to_i915(dev))) |
3661 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
73974893 | 3662 | |
581e49fe | 3663 | ret = drm_atomic_helper_commit_duplicated_state(state, ctx); |
73974893 ML |
3664 | |
3665 | WARN_ON(ret == -EDEADLK); | |
3666 | return ret; | |
96a02917 VS |
3667 | } |
3668 | ||
4ac2ba2f VS |
3669 | static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv) |
3670 | { | |
ae98104b VS |
3671 | return intel_has_gpu_reset(dev_priv) && |
3672 | INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv); | |
4ac2ba2f VS |
3673 | } |
3674 | ||
c033666a | 3675 | void intel_prepare_reset(struct drm_i915_private *dev_priv) |
7514747d | 3676 | { |
73974893 ML |
3677 | struct drm_device *dev = &dev_priv->drm; |
3678 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; | |
3679 | struct drm_atomic_state *state; | |
3680 | int ret; | |
3681 | ||
ce87ea15 DV |
3682 | |
3683 | /* reset doesn't touch the display */ | |
3684 | if (!i915.force_reset_modeset_test && | |
3685 | !gpu_reset_clobbers_display(dev_priv)) | |
3686 | return; | |
3687 | ||
9db529aa DV |
3688 | /* We have a modeset vs reset deadlock, defensively unbreak it. */ |
3689 | set_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags); | |
3690 | wake_up_all(&dev_priv->gpu_error.wait_queue); | |
3691 | ||
3692 | if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) { | |
3693 | DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n"); | |
3694 | i915_gem_set_wedged(dev_priv); | |
3695 | } | |
97154ec2 | 3696 | |
73974893 ML |
3697 | /* |
3698 | * Need mode_config.mutex so that we don't | |
3699 | * trample ongoing ->detect() and whatnot. | |
3700 | */ | |
3701 | mutex_lock(&dev->mode_config.mutex); | |
3702 | drm_modeset_acquire_init(ctx, 0); | |
3703 | while (1) { | |
3704 | ret = drm_modeset_lock_all_ctx(dev, ctx); | |
3705 | if (ret != -EDEADLK) | |
3706 | break; | |
3707 | ||
3708 | drm_modeset_backoff(ctx); | |
3709 | } | |
f98ce92f VS |
3710 | /* |
3711 | * Disabling the crtcs gracefully seems nicer. Also the | |
3712 | * g33 docs say we should at least disable all the planes. | |
3713 | */ | |
73974893 ML |
3714 | state = drm_atomic_helper_duplicate_state(dev, ctx); |
3715 | if (IS_ERR(state)) { | |
3716 | ret = PTR_ERR(state); | |
73974893 | 3717 | DRM_ERROR("Duplicating state failed with %i\n", ret); |
1e5a15d6 | 3718 | return; |
73974893 ML |
3719 | } |
3720 | ||
3721 | ret = drm_atomic_helper_disable_all(dev, ctx); | |
3722 | if (ret) { | |
3723 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
1e5a15d6 ACO |
3724 | drm_atomic_state_put(state); |
3725 | return; | |
73974893 ML |
3726 | } |
3727 | ||
3728 | dev_priv->modeset_restore_state = state; | |
3729 | state->acquire_ctx = ctx; | |
7514747d VS |
3730 | } |
3731 | ||
c033666a | 3732 | void intel_finish_reset(struct drm_i915_private *dev_priv) |
7514747d | 3733 | { |
73974893 ML |
3734 | struct drm_device *dev = &dev_priv->drm; |
3735 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; | |
3736 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
3737 | int ret; | |
3738 | ||
ce87ea15 DV |
3739 | /* reset doesn't touch the display */ |
3740 | if (!i915.force_reset_modeset_test && | |
3741 | !gpu_reset_clobbers_display(dev_priv)) | |
3742 | return; | |
3743 | ||
3744 | if (!state) | |
3745 | goto unlock; | |
3746 | ||
73974893 ML |
3747 | dev_priv->modeset_restore_state = NULL; |
3748 | ||
7514747d | 3749 | /* reset doesn't touch the display */ |
4ac2ba2f | 3750 | if (!gpu_reset_clobbers_display(dev_priv)) { |
ce87ea15 DV |
3751 | /* for testing only restore the display */ |
3752 | ret = __intel_display_resume(dev, state, ctx); | |
942d5d0d CW |
3753 | if (ret) |
3754 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
73974893 ML |
3755 | } else { |
3756 | /* | |
3757 | * The display has been reset as well, | |
3758 | * so need a full re-initialization. | |
3759 | */ | |
3760 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3761 | intel_runtime_pm_enable_interrupts(dev_priv); | |
7514747d | 3762 | |
51f59205 | 3763 | intel_pps_unlock_regs_wa(dev_priv); |
73974893 | 3764 | intel_modeset_init_hw(dev); |
7514747d | 3765 | |
73974893 ML |
3766 | spin_lock_irq(&dev_priv->irq_lock); |
3767 | if (dev_priv->display.hpd_irq_setup) | |
3768 | dev_priv->display.hpd_irq_setup(dev_priv); | |
3769 | spin_unlock_irq(&dev_priv->irq_lock); | |
7514747d | 3770 | |
581e49fe | 3771 | ret = __intel_display_resume(dev, state, ctx); |
73974893 ML |
3772 | if (ret) |
3773 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
7514747d | 3774 | |
73974893 ML |
3775 | intel_hpd_init(dev_priv); |
3776 | } | |
7514747d | 3777 | |
ce87ea15 DV |
3778 | drm_atomic_state_put(state); |
3779 | unlock: | |
73974893 ML |
3780 | drm_modeset_drop_locks(ctx); |
3781 | drm_modeset_acquire_fini(ctx); | |
3782 | mutex_unlock(&dev->mode_config.mutex); | |
9db529aa DV |
3783 | |
3784 | clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags); | |
7514747d VS |
3785 | } |
3786 | ||
bfd16b2a ML |
3787 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
3788 | struct intel_crtc_state *old_crtc_state) | |
e30e8f75 | 3789 | { |
6315b5d3 | 3790 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
bfd16b2a ML |
3791 | struct intel_crtc_state *pipe_config = |
3792 | to_intel_crtc_state(crtc->base.state); | |
e30e8f75 | 3793 | |
bfd16b2a ML |
3794 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
3795 | crtc->base.mode = crtc->base.state->mode; | |
3796 | ||
e30e8f75 GP |
3797 | /* |
3798 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3799 | * that in compute_mode_changes we check the native mode (not the pfit | |
3800 | * mode) to see if we can flip rather than do a full mode set. In the | |
3801 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3802 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3803 | * sized surface. | |
e30e8f75 GP |
3804 | */ |
3805 | ||
e30e8f75 | 3806 | I915_WRITE(PIPESRC(crtc->pipe), |
bfd16b2a ML |
3807 | ((pipe_config->pipe_src_w - 1) << 16) | |
3808 | (pipe_config->pipe_src_h - 1)); | |
3809 | ||
3810 | /* on skylake this is done by detaching scalers */ | |
6315b5d3 | 3811 | if (INTEL_GEN(dev_priv) >= 9) { |
bfd16b2a ML |
3812 | skl_detach_scalers(crtc); |
3813 | ||
3814 | if (pipe_config->pch_pfit.enabled) | |
3815 | skylake_pfit_enable(crtc); | |
6e266956 | 3816 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
bfd16b2a ML |
3817 | if (pipe_config->pch_pfit.enabled) |
3818 | ironlake_pfit_enable(crtc); | |
3819 | else if (old_crtc_state->pch_pfit.enabled) | |
3820 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3821 | } |
e30e8f75 GP |
3822 | } |
3823 | ||
4cbe4b2b | 3824 | static void intel_fdi_normal_train(struct intel_crtc *crtc) |
5e84e1a4 | 3825 | { |
4cbe4b2b | 3826 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 3827 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 3828 | int pipe = crtc->pipe; |
f0f59a00 VS |
3829 | i915_reg_t reg; |
3830 | u32 temp; | |
5e84e1a4 ZW |
3831 | |
3832 | /* enable normal train */ | |
3833 | reg = FDI_TX_CTL(pipe); | |
3834 | temp = I915_READ(reg); | |
fd6b8f43 | 3835 | if (IS_IVYBRIDGE(dev_priv)) { |
357555c0 JB |
3836 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3837 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3838 | } else { |
3839 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3840 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3841 | } |
5e84e1a4 ZW |
3842 | I915_WRITE(reg, temp); |
3843 | ||
3844 | reg = FDI_RX_CTL(pipe); | |
3845 | temp = I915_READ(reg); | |
6e266956 | 3846 | if (HAS_PCH_CPT(dev_priv)) { |
5e84e1a4 ZW |
3847 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3848 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3849 | } else { | |
3850 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3851 | temp |= FDI_LINK_TRAIN_NONE; | |
3852 | } | |
3853 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3854 | ||
3855 | /* wait one idle pattern time */ | |
3856 | POSTING_READ(reg); | |
3857 | udelay(1000); | |
357555c0 JB |
3858 | |
3859 | /* IVB wants error correction enabled */ | |
fd6b8f43 | 3860 | if (IS_IVYBRIDGE(dev_priv)) |
357555c0 JB |
3861 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | |
3862 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3863 | } |
3864 | ||
8db9d77b | 3865 | /* The FDI link training functions for ILK/Ibexpeak. */ |
dc4a1094 ACO |
3866 | static void ironlake_fdi_link_train(struct intel_crtc *crtc, |
3867 | const struct intel_crtc_state *crtc_state) | |
8db9d77b | 3868 | { |
4cbe4b2b | 3869 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 3870 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 3871 | int pipe = crtc->pipe; |
f0f59a00 VS |
3872 | i915_reg_t reg; |
3873 | u32 temp, tries; | |
8db9d77b | 3874 | |
1c8562f6 | 3875 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3876 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3877 | |
e1a44743 AJ |
3878 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3879 | for train result */ | |
5eddb70b CW |
3880 | reg = FDI_RX_IMR(pipe); |
3881 | temp = I915_READ(reg); | |
e1a44743 AJ |
3882 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3883 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3884 | I915_WRITE(reg, temp); |
3885 | I915_READ(reg); | |
e1a44743 AJ |
3886 | udelay(150); |
3887 | ||
8db9d77b | 3888 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3889 | reg = FDI_TX_CTL(pipe); |
3890 | temp = I915_READ(reg); | |
627eb5a3 | 3891 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
dc4a1094 | 3892 | temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); |
8db9d77b ZW |
3893 | temp &= ~FDI_LINK_TRAIN_NONE; |
3894 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3895 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3896 | |
5eddb70b CW |
3897 | reg = FDI_RX_CTL(pipe); |
3898 | temp = I915_READ(reg); | |
8db9d77b ZW |
3899 | temp &= ~FDI_LINK_TRAIN_NONE; |
3900 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3901 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3902 | ||
3903 | POSTING_READ(reg); | |
8db9d77b ZW |
3904 | udelay(150); |
3905 | ||
5b2adf89 | 3906 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3907 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3908 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3909 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3910 | |
5eddb70b | 3911 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3912 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3913 | temp = I915_READ(reg); |
8db9d77b ZW |
3914 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3915 | ||
3916 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3917 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3918 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3919 | break; |
3920 | } | |
8db9d77b | 3921 | } |
e1a44743 | 3922 | if (tries == 5) |
5eddb70b | 3923 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3924 | |
3925 | /* Train 2 */ | |
5eddb70b CW |
3926 | reg = FDI_TX_CTL(pipe); |
3927 | temp = I915_READ(reg); | |
8db9d77b ZW |
3928 | temp &= ~FDI_LINK_TRAIN_NONE; |
3929 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3930 | I915_WRITE(reg, temp); |
8db9d77b | 3931 | |
5eddb70b CW |
3932 | reg = FDI_RX_CTL(pipe); |
3933 | temp = I915_READ(reg); | |
8db9d77b ZW |
3934 | temp &= ~FDI_LINK_TRAIN_NONE; |
3935 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3936 | I915_WRITE(reg, temp); |
8db9d77b | 3937 | |
5eddb70b CW |
3938 | POSTING_READ(reg); |
3939 | udelay(150); | |
8db9d77b | 3940 | |
5eddb70b | 3941 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3942 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3943 | temp = I915_READ(reg); |
8db9d77b ZW |
3944 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3945 | ||
3946 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3947 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3948 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3949 | break; | |
3950 | } | |
8db9d77b | 3951 | } |
e1a44743 | 3952 | if (tries == 5) |
5eddb70b | 3953 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3954 | |
3955 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3956 | |
8db9d77b ZW |
3957 | } |
3958 | ||
0206e353 | 3959 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3960 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3961 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3962 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3963 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3964 | }; | |
3965 | ||
3966 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
dc4a1094 ACO |
3967 | static void gen6_fdi_link_train(struct intel_crtc *crtc, |
3968 | const struct intel_crtc_state *crtc_state) | |
8db9d77b | 3969 | { |
4cbe4b2b | 3970 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 3971 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 3972 | int pipe = crtc->pipe; |
f0f59a00 VS |
3973 | i915_reg_t reg; |
3974 | u32 temp, i, retry; | |
8db9d77b | 3975 | |
e1a44743 AJ |
3976 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3977 | for train result */ | |
5eddb70b CW |
3978 | reg = FDI_RX_IMR(pipe); |
3979 | temp = I915_READ(reg); | |
e1a44743 AJ |
3980 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3981 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3982 | I915_WRITE(reg, temp); |
3983 | ||
3984 | POSTING_READ(reg); | |
e1a44743 AJ |
3985 | udelay(150); |
3986 | ||
8db9d77b | 3987 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3988 | reg = FDI_TX_CTL(pipe); |
3989 | temp = I915_READ(reg); | |
627eb5a3 | 3990 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
dc4a1094 | 3991 | temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); |
8db9d77b ZW |
3992 | temp &= ~FDI_LINK_TRAIN_NONE; |
3993 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3994 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3995 | /* SNB-B */ | |
3996 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3997 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3998 | |
d74cf324 DV |
3999 | I915_WRITE(FDI_RX_MISC(pipe), |
4000 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
4001 | ||
5eddb70b CW |
4002 | reg = FDI_RX_CTL(pipe); |
4003 | temp = I915_READ(reg); | |
6e266956 | 4004 | if (HAS_PCH_CPT(dev_priv)) { |
8db9d77b ZW |
4005 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
4006 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
4007 | } else { | |
4008 | temp &= ~FDI_LINK_TRAIN_NONE; | |
4009 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
4010 | } | |
5eddb70b CW |
4011 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
4012 | ||
4013 | POSTING_READ(reg); | |
8db9d77b ZW |
4014 | udelay(150); |
4015 | ||
0206e353 | 4016 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
4017 | reg = FDI_TX_CTL(pipe); |
4018 | temp = I915_READ(reg); | |
8db9d77b ZW |
4019 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
4020 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
4021 | I915_WRITE(reg, temp); |
4022 | ||
4023 | POSTING_READ(reg); | |
8db9d77b ZW |
4024 | udelay(500); |
4025 | ||
fa37d39e SP |
4026 | for (retry = 0; retry < 5; retry++) { |
4027 | reg = FDI_RX_IIR(pipe); | |
4028 | temp = I915_READ(reg); | |
4029 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
4030 | if (temp & FDI_RX_BIT_LOCK) { | |
4031 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
4032 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
4033 | break; | |
4034 | } | |
4035 | udelay(50); | |
8db9d77b | 4036 | } |
fa37d39e SP |
4037 | if (retry < 5) |
4038 | break; | |
8db9d77b ZW |
4039 | } |
4040 | if (i == 4) | |
5eddb70b | 4041 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
4042 | |
4043 | /* Train 2 */ | |
5eddb70b CW |
4044 | reg = FDI_TX_CTL(pipe); |
4045 | temp = I915_READ(reg); | |
8db9d77b ZW |
4046 | temp &= ~FDI_LINK_TRAIN_NONE; |
4047 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5db94019 | 4048 | if (IS_GEN6(dev_priv)) { |
8db9d77b ZW |
4049 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
4050 | /* SNB-B */ | |
4051 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
4052 | } | |
5eddb70b | 4053 | I915_WRITE(reg, temp); |
8db9d77b | 4054 | |
5eddb70b CW |
4055 | reg = FDI_RX_CTL(pipe); |
4056 | temp = I915_READ(reg); | |
6e266956 | 4057 | if (HAS_PCH_CPT(dev_priv)) { |
8db9d77b ZW |
4058 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
4059 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
4060 | } else { | |
4061 | temp &= ~FDI_LINK_TRAIN_NONE; | |
4062 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
4063 | } | |
5eddb70b CW |
4064 | I915_WRITE(reg, temp); |
4065 | ||
4066 | POSTING_READ(reg); | |
8db9d77b ZW |
4067 | udelay(150); |
4068 | ||
0206e353 | 4069 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
4070 | reg = FDI_TX_CTL(pipe); |
4071 | temp = I915_READ(reg); | |
8db9d77b ZW |
4072 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
4073 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
4074 | I915_WRITE(reg, temp); |
4075 | ||
4076 | POSTING_READ(reg); | |
8db9d77b ZW |
4077 | udelay(500); |
4078 | ||
fa37d39e SP |
4079 | for (retry = 0; retry < 5; retry++) { |
4080 | reg = FDI_RX_IIR(pipe); | |
4081 | temp = I915_READ(reg); | |
4082 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
4083 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
4084 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
4085 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
4086 | break; | |
4087 | } | |
4088 | udelay(50); | |
8db9d77b | 4089 | } |
fa37d39e SP |
4090 | if (retry < 5) |
4091 | break; | |
8db9d77b ZW |
4092 | } |
4093 | if (i == 4) | |
5eddb70b | 4094 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
4095 | |
4096 | DRM_DEBUG_KMS("FDI train done.\n"); | |
4097 | } | |
4098 | ||
357555c0 | 4099 | /* Manual link training for Ivy Bridge A0 parts */ |
dc4a1094 ACO |
4100 | static void ivb_manual_fdi_link_train(struct intel_crtc *crtc, |
4101 | const struct intel_crtc_state *crtc_state) | |
357555c0 | 4102 | { |
4cbe4b2b | 4103 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4104 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 4105 | int pipe = crtc->pipe; |
f0f59a00 VS |
4106 | i915_reg_t reg; |
4107 | u32 temp, i, j; | |
357555c0 JB |
4108 | |
4109 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
4110 | for train result */ | |
4111 | reg = FDI_RX_IMR(pipe); | |
4112 | temp = I915_READ(reg); | |
4113 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
4114 | temp &= ~FDI_RX_BIT_LOCK; | |
4115 | I915_WRITE(reg, temp); | |
4116 | ||
4117 | POSTING_READ(reg); | |
4118 | udelay(150); | |
4119 | ||
01a415fd DV |
4120 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
4121 | I915_READ(FDI_RX_IIR(pipe))); | |
4122 | ||
139ccd3f JB |
4123 | /* Try each vswing and preemphasis setting twice before moving on */ |
4124 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
4125 | /* disable first in case we need to retry */ | |
4126 | reg = FDI_TX_CTL(pipe); | |
4127 | temp = I915_READ(reg); | |
4128 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
4129 | temp &= ~FDI_TX_ENABLE; | |
4130 | I915_WRITE(reg, temp); | |
357555c0 | 4131 | |
139ccd3f JB |
4132 | reg = FDI_RX_CTL(pipe); |
4133 | temp = I915_READ(reg); | |
4134 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
4135 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
4136 | temp &= ~FDI_RX_ENABLE; | |
4137 | I915_WRITE(reg, temp); | |
357555c0 | 4138 | |
139ccd3f | 4139 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
4140 | reg = FDI_TX_CTL(pipe); |
4141 | temp = I915_READ(reg); | |
139ccd3f | 4142 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
dc4a1094 | 4143 | temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); |
139ccd3f | 4144 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 4145 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
4146 | temp |= snb_b_fdi_train_param[j/2]; |
4147 | temp |= FDI_COMPOSITE_SYNC; | |
4148 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 4149 | |
139ccd3f JB |
4150 | I915_WRITE(FDI_RX_MISC(pipe), |
4151 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 4152 | |
139ccd3f | 4153 | reg = FDI_RX_CTL(pipe); |
357555c0 | 4154 | temp = I915_READ(reg); |
139ccd3f JB |
4155 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
4156 | temp |= FDI_COMPOSITE_SYNC; | |
4157 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 4158 | |
139ccd3f JB |
4159 | POSTING_READ(reg); |
4160 | udelay(1); /* should be 0.5us */ | |
357555c0 | 4161 | |
139ccd3f JB |
4162 | for (i = 0; i < 4; i++) { |
4163 | reg = FDI_RX_IIR(pipe); | |
4164 | temp = I915_READ(reg); | |
4165 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 4166 | |
139ccd3f JB |
4167 | if (temp & FDI_RX_BIT_LOCK || |
4168 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
4169 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
4170 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
4171 | i); | |
4172 | break; | |
4173 | } | |
4174 | udelay(1); /* should be 0.5us */ | |
4175 | } | |
4176 | if (i == 4) { | |
4177 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
4178 | continue; | |
4179 | } | |
357555c0 | 4180 | |
139ccd3f | 4181 | /* Train 2 */ |
357555c0 JB |
4182 | reg = FDI_TX_CTL(pipe); |
4183 | temp = I915_READ(reg); | |
139ccd3f JB |
4184 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
4185 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
4186 | I915_WRITE(reg, temp); | |
4187 | ||
4188 | reg = FDI_RX_CTL(pipe); | |
4189 | temp = I915_READ(reg); | |
4190 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
4191 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
4192 | I915_WRITE(reg, temp); |
4193 | ||
4194 | POSTING_READ(reg); | |
139ccd3f | 4195 | udelay(2); /* should be 1.5us */ |
357555c0 | 4196 | |
139ccd3f JB |
4197 | for (i = 0; i < 4; i++) { |
4198 | reg = FDI_RX_IIR(pipe); | |
4199 | temp = I915_READ(reg); | |
4200 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 4201 | |
139ccd3f JB |
4202 | if (temp & FDI_RX_SYMBOL_LOCK || |
4203 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
4204 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
4205 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
4206 | i); | |
4207 | goto train_done; | |
4208 | } | |
4209 | udelay(2); /* should be 1.5us */ | |
357555c0 | 4210 | } |
139ccd3f JB |
4211 | if (i == 4) |
4212 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 4213 | } |
357555c0 | 4214 | |
139ccd3f | 4215 | train_done: |
357555c0 JB |
4216 | DRM_DEBUG_KMS("FDI train done.\n"); |
4217 | } | |
4218 | ||
88cefb6c | 4219 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 4220 | { |
88cefb6c | 4221 | struct drm_device *dev = intel_crtc->base.dev; |
fac5e23e | 4222 | struct drm_i915_private *dev_priv = to_i915(dev); |
2c07245f | 4223 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
4224 | i915_reg_t reg; |
4225 | u32 temp; | |
c64e311e | 4226 | |
c98e9dcf | 4227 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
4228 | reg = FDI_RX_CTL(pipe); |
4229 | temp = I915_READ(reg); | |
627eb5a3 | 4230 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 4231 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 4232 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
4233 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
4234 | ||
4235 | POSTING_READ(reg); | |
c98e9dcf JB |
4236 | udelay(200); |
4237 | ||
4238 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
4239 | temp = I915_READ(reg); |
4240 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
4241 | ||
4242 | POSTING_READ(reg); | |
c98e9dcf JB |
4243 | udelay(200); |
4244 | ||
20749730 PZ |
4245 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
4246 | reg = FDI_TX_CTL(pipe); | |
4247 | temp = I915_READ(reg); | |
4248 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
4249 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 4250 | |
20749730 PZ |
4251 | POSTING_READ(reg); |
4252 | udelay(100); | |
6be4a607 | 4253 | } |
0e23b99d JB |
4254 | } |
4255 | ||
88cefb6c DV |
4256 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
4257 | { | |
4258 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 4259 | struct drm_i915_private *dev_priv = to_i915(dev); |
88cefb6c | 4260 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
4261 | i915_reg_t reg; |
4262 | u32 temp; | |
88cefb6c DV |
4263 | |
4264 | /* Switch from PCDclk to Rawclk */ | |
4265 | reg = FDI_RX_CTL(pipe); | |
4266 | temp = I915_READ(reg); | |
4267 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
4268 | ||
4269 | /* Disable CPU FDI TX PLL */ | |
4270 | reg = FDI_TX_CTL(pipe); | |
4271 | temp = I915_READ(reg); | |
4272 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
4273 | ||
4274 | POSTING_READ(reg); | |
4275 | udelay(100); | |
4276 | ||
4277 | reg = FDI_RX_CTL(pipe); | |
4278 | temp = I915_READ(reg); | |
4279 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
4280 | ||
4281 | /* Wait for the clocks to turn off. */ | |
4282 | POSTING_READ(reg); | |
4283 | udelay(100); | |
4284 | } | |
4285 | ||
0fc932b8 JB |
4286 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
4287 | { | |
4288 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4289 | struct drm_i915_private *dev_priv = to_i915(dev); |
0fc932b8 JB |
4290 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4291 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
4292 | i915_reg_t reg; |
4293 | u32 temp; | |
0fc932b8 JB |
4294 | |
4295 | /* disable CPU FDI tx and PCH FDI rx */ | |
4296 | reg = FDI_TX_CTL(pipe); | |
4297 | temp = I915_READ(reg); | |
4298 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
4299 | POSTING_READ(reg); | |
4300 | ||
4301 | reg = FDI_RX_CTL(pipe); | |
4302 | temp = I915_READ(reg); | |
4303 | temp &= ~(0x7 << 16); | |
dfd07d72 | 4304 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
4305 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
4306 | ||
4307 | POSTING_READ(reg); | |
4308 | udelay(100); | |
4309 | ||
4310 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
6e266956 | 4311 | if (HAS_PCH_IBX(dev_priv)) |
6f06ce18 | 4312 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
4313 | |
4314 | /* still set train pattern 1 */ | |
4315 | reg = FDI_TX_CTL(pipe); | |
4316 | temp = I915_READ(reg); | |
4317 | temp &= ~FDI_LINK_TRAIN_NONE; | |
4318 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
4319 | I915_WRITE(reg, temp); | |
4320 | ||
4321 | reg = FDI_RX_CTL(pipe); | |
4322 | temp = I915_READ(reg); | |
6e266956 | 4323 | if (HAS_PCH_CPT(dev_priv)) { |
0fc932b8 JB |
4324 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
4325 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
4326 | } else { | |
4327 | temp &= ~FDI_LINK_TRAIN_NONE; | |
4328 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
4329 | } | |
4330 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
4331 | temp &= ~(0x07 << 16); | |
dfd07d72 | 4332 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
4333 | I915_WRITE(reg, temp); |
4334 | ||
4335 | POSTING_READ(reg); | |
4336 | udelay(100); | |
4337 | } | |
4338 | ||
49d73912 | 4339 | bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) |
5dce5b93 | 4340 | { |
fa05887a DV |
4341 | struct drm_crtc *crtc; |
4342 | bool cleanup_done; | |
4343 | ||
4344 | drm_for_each_crtc(crtc, &dev_priv->drm) { | |
4345 | struct drm_crtc_commit *commit; | |
4346 | spin_lock(&crtc->commit_lock); | |
4347 | commit = list_first_entry_or_null(&crtc->commit_list, | |
4348 | struct drm_crtc_commit, commit_entry); | |
4349 | cleanup_done = commit ? | |
4350 | try_wait_for_completion(&commit->cleanup_done) : true; | |
4351 | spin_unlock(&crtc->commit_lock); | |
4352 | ||
4353 | if (cleanup_done) | |
5dce5b93 CW |
4354 | continue; |
4355 | ||
fa05887a | 4356 | drm_crtc_wait_one_vblank(crtc); |
5dce5b93 CW |
4357 | |
4358 | return true; | |
4359 | } | |
4360 | ||
4361 | return false; | |
4362 | } | |
4363 | ||
b7076546 | 4364 | void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
060f02d8 VS |
4365 | { |
4366 | u32 temp; | |
4367 | ||
4368 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
4369 | ||
4370 | mutex_lock(&dev_priv->sb_lock); | |
4371 | ||
4372 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
4373 | temp |= SBI_SSCCTL_DISABLE; | |
4374 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
4375 | ||
4376 | mutex_unlock(&dev_priv->sb_lock); | |
4377 | } | |
4378 | ||
e615efe4 | 4379 | /* Program iCLKIP clock to the desired frequency */ |
0dcdc382 | 4380 | static void lpt_program_iclkip(struct intel_crtc *crtc) |
e615efe4 | 4381 | { |
0dcdc382 ACO |
4382 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
4383 | int clock = crtc->config->base.adjusted_mode.crtc_clock; | |
e615efe4 ED |
4384 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
4385 | u32 temp; | |
4386 | ||
060f02d8 | 4387 | lpt_disable_iclkip(dev_priv); |
e615efe4 | 4388 | |
64b46a06 VS |
4389 | /* The iCLK virtual clock root frequency is in MHz, |
4390 | * but the adjusted_mode->crtc_clock in in KHz. To get the | |
4391 | * divisors, it is necessary to divide one by another, so we | |
4392 | * convert the virtual clock precision to KHz here for higher | |
4393 | * precision. | |
4394 | */ | |
4395 | for (auxdiv = 0; auxdiv < 2; auxdiv++) { | |
e615efe4 ED |
4396 | u32 iclk_virtual_root_freq = 172800 * 1000; |
4397 | u32 iclk_pi_range = 64; | |
64b46a06 | 4398 | u32 desired_divisor; |
e615efe4 | 4399 | |
64b46a06 VS |
4400 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, |
4401 | clock << auxdiv); | |
4402 | divsel = (desired_divisor / iclk_pi_range) - 2; | |
4403 | phaseinc = desired_divisor % iclk_pi_range; | |
e615efe4 | 4404 | |
64b46a06 VS |
4405 | /* |
4406 | * Near 20MHz is a corner case which is | |
4407 | * out of range for the 7-bit divisor | |
4408 | */ | |
4409 | if (divsel <= 0x7f) | |
4410 | break; | |
e615efe4 ED |
4411 | } |
4412 | ||
4413 | /* This should not happen with any sane values */ | |
4414 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
4415 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
4416 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
4417 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
4418 | ||
4419 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 4420 | clock, |
e615efe4 ED |
4421 | auxdiv, |
4422 | divsel, | |
4423 | phasedir, | |
4424 | phaseinc); | |
4425 | ||
060f02d8 VS |
4426 | mutex_lock(&dev_priv->sb_lock); |
4427 | ||
e615efe4 | 4428 | /* Program SSCDIVINTPHASE6 */ |
988d6ee8 | 4429 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
4430 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
4431 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
4432 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
4433 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
4434 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
4435 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 4436 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
4437 | |
4438 | /* Program SSCAUXDIV */ | |
988d6ee8 | 4439 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
4440 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
4441 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 4442 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
4443 | |
4444 | /* Enable modulator and associated divider */ | |
988d6ee8 | 4445 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 4446 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 4447 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 | 4448 | |
060f02d8 VS |
4449 | mutex_unlock(&dev_priv->sb_lock); |
4450 | ||
e615efe4 ED |
4451 | /* Wait for initialization time */ |
4452 | udelay(24); | |
4453 | ||
4454 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
4455 | } | |
4456 | ||
8802e5b6 VS |
4457 | int lpt_get_iclkip(struct drm_i915_private *dev_priv) |
4458 | { | |
4459 | u32 divsel, phaseinc, auxdiv; | |
4460 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
4461 | u32 iclk_pi_range = 64; | |
4462 | u32 desired_divisor; | |
4463 | u32 temp; | |
4464 | ||
4465 | if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) | |
4466 | return 0; | |
4467 | ||
4468 | mutex_lock(&dev_priv->sb_lock); | |
4469 | ||
4470 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
4471 | if (temp & SBI_SSCCTL_DISABLE) { | |
4472 | mutex_unlock(&dev_priv->sb_lock); | |
4473 | return 0; | |
4474 | } | |
4475 | ||
4476 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); | |
4477 | divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >> | |
4478 | SBI_SSCDIVINTPHASE_DIVSEL_SHIFT; | |
4479 | phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >> | |
4480 | SBI_SSCDIVINTPHASE_INCVAL_SHIFT; | |
4481 | ||
4482 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); | |
4483 | auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >> | |
4484 | SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT; | |
4485 | ||
4486 | mutex_unlock(&dev_priv->sb_lock); | |
4487 | ||
4488 | desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc; | |
4489 | ||
4490 | return DIV_ROUND_CLOSEST(iclk_virtual_root_freq, | |
4491 | desired_divisor << auxdiv); | |
4492 | } | |
4493 | ||
275f01b2 DV |
4494 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4495 | enum pipe pch_transcoder) | |
4496 | { | |
4497 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4498 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 4499 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4500 | |
4501 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4502 | I915_READ(HTOTAL(cpu_transcoder))); | |
4503 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4504 | I915_READ(HBLANK(cpu_transcoder))); | |
4505 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4506 | I915_READ(HSYNC(cpu_transcoder))); | |
4507 | ||
4508 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4509 | I915_READ(VTOTAL(cpu_transcoder))); | |
4510 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4511 | I915_READ(VBLANK(cpu_transcoder))); | |
4512 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4513 | I915_READ(VSYNC(cpu_transcoder))); | |
4514 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4515 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4516 | } | |
4517 | ||
003632d9 | 4518 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 | 4519 | { |
fac5e23e | 4520 | struct drm_i915_private *dev_priv = to_i915(dev); |
1fbc0d78 DV |
4521 | uint32_t temp; |
4522 | ||
4523 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4524 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4525 | return; |
4526 | ||
4527 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4528 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4529 | ||
003632d9 ACO |
4530 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4531 | if (enable) | |
4532 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4533 | ||
4534 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4535 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4536 | POSTING_READ(SOUTH_CHICKEN1); | |
4537 | } | |
4538 | ||
4539 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4540 | { | |
4541 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4542 | |
4543 | switch (intel_crtc->pipe) { | |
4544 | case PIPE_A: | |
4545 | break; | |
4546 | case PIPE_B: | |
6e3c9717 | 4547 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4548 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4549 | else |
003632d9 | 4550 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4551 | |
4552 | break; | |
4553 | case PIPE_C: | |
003632d9 | 4554 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4555 | |
4556 | break; | |
4557 | default: | |
4558 | BUG(); | |
4559 | } | |
4560 | } | |
4561 | ||
c48b5305 VS |
4562 | /* Return which DP Port should be selected for Transcoder DP control */ |
4563 | static enum port | |
4cbe4b2b | 4564 | intel_trans_dp_port_sel(struct intel_crtc *crtc) |
c48b5305 | 4565 | { |
4cbe4b2b | 4566 | struct drm_device *dev = crtc->base.dev; |
c48b5305 VS |
4567 | struct intel_encoder *encoder; |
4568 | ||
4cbe4b2b | 4569 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { |
cca0502b | 4570 | if (encoder->type == INTEL_OUTPUT_DP || |
c48b5305 VS |
4571 | encoder->type == INTEL_OUTPUT_EDP) |
4572 | return enc_to_dig_port(&encoder->base)->port; | |
4573 | } | |
4574 | ||
4575 | return -1; | |
4576 | } | |
4577 | ||
f67a559d JB |
4578 | /* |
4579 | * Enable PCH resources required for PCH ports: | |
4580 | * - PCH PLLs | |
4581 | * - FDI training & RX/TX | |
4582 | * - update transcoder timings | |
4583 | * - DP transcoding bits | |
4584 | * - transcoder | |
4585 | */ | |
2ce42273 | 4586 | static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state) |
0e23b99d | 4587 | { |
2ce42273 | 4588 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
4cbe4b2b | 4589 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4590 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 4591 | int pipe = crtc->pipe; |
f0f59a00 | 4592 | u32 temp; |
2c07245f | 4593 | |
ab9412ba | 4594 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4595 | |
fd6b8f43 | 4596 | if (IS_IVYBRIDGE(dev_priv)) |
4cbe4b2b | 4597 | ivybridge_update_fdi_bc_bifurcation(crtc); |
1fbc0d78 | 4598 | |
cd986abb DV |
4599 | /* Write the TU size bits before fdi link training, so that error |
4600 | * detection works. */ | |
4601 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4602 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4603 | ||
c98e9dcf | 4604 | /* For PCH output, training FDI link */ |
dc4a1094 | 4605 | dev_priv->display.fdi_link_train(crtc, crtc_state); |
2c07245f | 4606 | |
3ad8a208 DV |
4607 | /* We need to program the right clock selection before writing the pixel |
4608 | * mutliplier into the DPLL. */ | |
6e266956 | 4609 | if (HAS_PCH_CPT(dev_priv)) { |
ee7b9f93 | 4610 | u32 sel; |
4b645f14 | 4611 | |
c98e9dcf | 4612 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4613 | temp |= TRANS_DPLL_ENABLE(pipe); |
4614 | sel = TRANS_DPLLB_SEL(pipe); | |
2ce42273 | 4615 | if (crtc_state->shared_dpll == |
8106ddbd | 4616 | intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B)) |
ee7b9f93 JB |
4617 | temp |= sel; |
4618 | else | |
4619 | temp &= ~sel; | |
c98e9dcf | 4620 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4621 | } |
5eddb70b | 4622 | |
3ad8a208 DV |
4623 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4624 | * transcoder, and we actually should do this to not upset any PCH | |
4625 | * transcoder that already use the clock when we share it. | |
4626 | * | |
4627 | * Note that enable_shared_dpll tries to do the right thing, but | |
4628 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4629 | * the right LVDS enable sequence. */ | |
4cbe4b2b | 4630 | intel_enable_shared_dpll(crtc); |
3ad8a208 | 4631 | |
d9b6cb56 JB |
4632 | /* set transcoder timing, panel must allow it */ |
4633 | assert_panel_unlocked(dev_priv, pipe); | |
4cbe4b2b | 4634 | ironlake_pch_transcoder_set_timings(crtc, pipe); |
8db9d77b | 4635 | |
303b81e0 | 4636 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4637 | |
c98e9dcf | 4638 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e266956 | 4639 | if (HAS_PCH_CPT(dev_priv) && |
2ce42273 | 4640 | intel_crtc_has_dp_encoder(crtc_state)) { |
9c4edaee | 4641 | const struct drm_display_mode *adjusted_mode = |
2ce42273 | 4642 | &crtc_state->base.adjusted_mode; |
dfd07d72 | 4643 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
f0f59a00 | 4644 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
5eddb70b CW |
4645 | temp = I915_READ(reg); |
4646 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4647 | TRANS_DP_SYNC_MASK | |
4648 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4649 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4650 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf | 4651 | |
9c4edaee | 4652 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
5eddb70b | 4653 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
9c4edaee | 4654 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4655 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4656 | |
4657 | switch (intel_trans_dp_port_sel(crtc)) { | |
c48b5305 | 4658 | case PORT_B: |
5eddb70b | 4659 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 4660 | break; |
c48b5305 | 4661 | case PORT_C: |
5eddb70b | 4662 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf | 4663 | break; |
c48b5305 | 4664 | case PORT_D: |
5eddb70b | 4665 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4666 | break; |
4667 | default: | |
e95d41e1 | 4668 | BUG(); |
32f9d658 | 4669 | } |
2c07245f | 4670 | |
5eddb70b | 4671 | I915_WRITE(reg, temp); |
6be4a607 | 4672 | } |
b52eb4dc | 4673 | |
b8a4f404 | 4674 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4675 | } |
4676 | ||
2ce42273 | 4677 | static void lpt_pch_enable(const struct intel_crtc_state *crtc_state) |
1507e5bd | 4678 | { |
2ce42273 | 4679 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
0dcdc382 | 4680 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
2ce42273 | 4681 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
1507e5bd | 4682 | |
a2196033 | 4683 | assert_pch_transcoder_disabled(dev_priv, PIPE_A); |
1507e5bd | 4684 | |
8c52b5e8 | 4685 | lpt_program_iclkip(crtc); |
1507e5bd | 4686 | |
0540e488 | 4687 | /* Set transcoder timing. */ |
0dcdc382 | 4688 | ironlake_pch_transcoder_set_timings(crtc, PIPE_A); |
1507e5bd | 4689 | |
937bb610 | 4690 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4691 | } |
4692 | ||
a1520318 | 4693 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 | 4694 | { |
fac5e23e | 4695 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 4696 | i915_reg_t dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4697 | u32 temp; |
4698 | ||
4699 | temp = I915_READ(dslreg); | |
4700 | udelay(500); | |
4701 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4702 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4703 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4704 | } |
4705 | } | |
4706 | ||
86adf9d7 ML |
4707 | static int |
4708 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
d96a7d2a | 4709 | unsigned int scaler_user, int *scaler_id, |
86adf9d7 | 4710 | int src_w, int src_h, int dst_w, int dst_h) |
a1b2278e | 4711 | { |
86adf9d7 ML |
4712 | struct intel_crtc_scaler_state *scaler_state = |
4713 | &crtc_state->scaler_state; | |
4714 | struct intel_crtc *intel_crtc = | |
4715 | to_intel_crtc(crtc_state->base.crtc); | |
7f58cbb1 MK |
4716 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
4717 | const struct drm_display_mode *adjusted_mode = | |
4718 | &crtc_state->base.adjusted_mode; | |
a1b2278e | 4719 | int need_scaling; |
6156a456 | 4720 | |
d96a7d2a VS |
4721 | /* |
4722 | * Src coordinates are already rotated by 270 degrees for | |
4723 | * the 90/270 degree plane rotation cases (to match the | |
4724 | * GTT mapping), hence no need to account for rotation here. | |
4725 | */ | |
4726 | need_scaling = src_w != dst_w || src_h != dst_h; | |
a1b2278e | 4727 | |
e5c05931 SS |
4728 | if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX) |
4729 | need_scaling = true; | |
4730 | ||
7f58cbb1 MK |
4731 | /* |
4732 | * Scaling/fitting not supported in IF-ID mode in GEN9+ | |
4733 | * TODO: Interlace fetch mode doesn't support YUV420 planar formats. | |
4734 | * Once NV12 is enabled, handle it here while allocating scaler | |
4735 | * for NV12. | |
4736 | */ | |
4737 | if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable && | |
4738 | need_scaling && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
4739 | DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n"); | |
4740 | return -EINVAL; | |
4741 | } | |
4742 | ||
a1b2278e CK |
4743 | /* |
4744 | * if plane is being disabled or scaler is no more required or force detach | |
4745 | * - free scaler binded to this plane/crtc | |
4746 | * - in order to do this, update crtc->scaler_usage | |
4747 | * | |
4748 | * Here scaler state in crtc_state is set free so that | |
4749 | * scaler can be assigned to other user. Actual register | |
4750 | * update to free the scaler is done in plane/panel-fit programming. | |
4751 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4752 | */ | |
86adf9d7 | 4753 | if (force_detach || !need_scaling) { |
a1b2278e | 4754 | if (*scaler_id >= 0) { |
86adf9d7 | 4755 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4756 | scaler_state->scalers[*scaler_id].in_use = 0; |
4757 | ||
86adf9d7 ML |
4758 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4759 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4760 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4761 | scaler_state->scaler_users); |
4762 | *scaler_id = -1; | |
4763 | } | |
4764 | return 0; | |
4765 | } | |
4766 | ||
4767 | /* range checks */ | |
4768 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4769 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4770 | ||
4771 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4772 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4773 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4774 | "size is out of scaler range\n", |
86adf9d7 | 4775 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4776 | return -EINVAL; |
4777 | } | |
4778 | ||
86adf9d7 ML |
4779 | /* mark this plane as a scaler user in crtc_state */ |
4780 | scaler_state->scaler_users |= (1 << scaler_user); | |
4781 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4782 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4783 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4784 | scaler_state->scaler_users); | |
4785 | ||
4786 | return 0; | |
4787 | } | |
4788 | ||
4789 | /** | |
4790 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4791 | * | |
4792 | * @state: crtc's scaler state | |
86adf9d7 ML |
4793 | * |
4794 | * Return | |
4795 | * 0 - scaler_usage updated successfully | |
4796 | * error - requested scaling cannot be supported or other error condition | |
4797 | */ | |
e435d6e5 | 4798 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 | 4799 | { |
7c5f93b0 | 4800 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
86adf9d7 | 4801 | |
e435d6e5 | 4802 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
d96a7d2a | 4803 | &state->scaler_state.scaler_id, |
86adf9d7 | 4804 | state->pipe_src_w, state->pipe_src_h, |
aad941d5 | 4805 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
86adf9d7 ML |
4806 | } |
4807 | ||
4808 | /** | |
4809 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4810 | * | |
4811 | * @state: crtc's scaler state | |
86adf9d7 ML |
4812 | * @plane_state: atomic plane state to update |
4813 | * | |
4814 | * Return | |
4815 | * 0 - scaler_usage updated successfully | |
4816 | * error - requested scaling cannot be supported or other error condition | |
4817 | */ | |
da20eabd ML |
4818 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4819 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4820 | { |
4821 | ||
da20eabd ML |
4822 | struct intel_plane *intel_plane = |
4823 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4824 | struct drm_framebuffer *fb = plane_state->base.fb; |
4825 | int ret; | |
4826 | ||
936e71e3 | 4827 | bool force_detach = !fb || !plane_state->base.visible; |
86adf9d7 | 4828 | |
86adf9d7 ML |
4829 | ret = skl_update_scaler(crtc_state, force_detach, |
4830 | drm_plane_index(&intel_plane->base), | |
4831 | &plane_state->scaler_id, | |
936e71e3 VS |
4832 | drm_rect_width(&plane_state->base.src) >> 16, |
4833 | drm_rect_height(&plane_state->base.src) >> 16, | |
4834 | drm_rect_width(&plane_state->base.dst), | |
4835 | drm_rect_height(&plane_state->base.dst)); | |
86adf9d7 ML |
4836 | |
4837 | if (ret || plane_state->scaler_id < 0) | |
4838 | return ret; | |
4839 | ||
a1b2278e | 4840 | /* check colorkey */ |
818ed961 | 4841 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
72660ce0 VS |
4842 | DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed", |
4843 | intel_plane->base.base.id, | |
4844 | intel_plane->base.name); | |
a1b2278e CK |
4845 | return -EINVAL; |
4846 | } | |
4847 | ||
4848 | /* Check src format */ | |
438b74a5 | 4849 | switch (fb->format->format) { |
86adf9d7 ML |
4850 | case DRM_FORMAT_RGB565: |
4851 | case DRM_FORMAT_XBGR8888: | |
4852 | case DRM_FORMAT_XRGB8888: | |
4853 | case DRM_FORMAT_ABGR8888: | |
4854 | case DRM_FORMAT_ARGB8888: | |
4855 | case DRM_FORMAT_XRGB2101010: | |
4856 | case DRM_FORMAT_XBGR2101010: | |
4857 | case DRM_FORMAT_YUYV: | |
4858 | case DRM_FORMAT_YVYU: | |
4859 | case DRM_FORMAT_UYVY: | |
4860 | case DRM_FORMAT_VYUY: | |
4861 | break; | |
4862 | default: | |
72660ce0 VS |
4863 | DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n", |
4864 | intel_plane->base.base.id, intel_plane->base.name, | |
438b74a5 | 4865 | fb->base.id, fb->format->format); |
86adf9d7 | 4866 | return -EINVAL; |
a1b2278e CK |
4867 | } |
4868 | ||
a1b2278e CK |
4869 | return 0; |
4870 | } | |
4871 | ||
e435d6e5 ML |
4872 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4873 | { | |
4874 | int i; | |
4875 | ||
4876 | for (i = 0; i < crtc->num_scalers; i++) | |
4877 | skl_detach_scaler(crtc, i); | |
4878 | } | |
4879 | ||
4880 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4881 | { |
4882 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4883 | struct drm_i915_private *dev_priv = to_i915(dev); |
bd2e244f | 4884 | int pipe = crtc->pipe; |
a1b2278e CK |
4885 | struct intel_crtc_scaler_state *scaler_state = |
4886 | &crtc->config->scaler_state; | |
4887 | ||
6e3c9717 | 4888 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4889 | int id; |
4890 | ||
c3f8ad57 | 4891 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) |
a1b2278e | 4892 | return; |
a1b2278e CK |
4893 | |
4894 | id = scaler_state->scaler_id; | |
4895 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4896 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4897 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4898 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
bd2e244f JB |
4899 | } |
4900 | } | |
4901 | ||
b074cec8 JB |
4902 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4903 | { | |
4904 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4905 | struct drm_i915_private *dev_priv = to_i915(dev); |
b074cec8 JB |
4906 | int pipe = crtc->pipe; |
4907 | ||
6e3c9717 | 4908 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4909 | /* Force use of hard-coded filter coefficients |
4910 | * as some pre-programmed values are broken, | |
4911 | * e.g. x201. | |
4912 | */ | |
fd6b8f43 | 4913 | if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) |
b074cec8 JB |
4914 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | |
4915 | PF_PIPE_SEL_IVB(pipe)); | |
4916 | else | |
4917 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4918 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4919 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4920 | } |
4921 | } | |
4922 | ||
20bc8673 | 4923 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4924 | { |
cea165c3 | 4925 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4926 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 4927 | |
6e3c9717 | 4928 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4929 | return; |
4930 | ||
307e4498 ML |
4931 | /* |
4932 | * We can only enable IPS after we enable a plane and wait for a vblank | |
4933 | * This function is called from post_plane_update, which is run after | |
4934 | * a vblank wait. | |
4935 | */ | |
cea165c3 | 4936 | |
d77e4531 | 4937 | assert_plane_enabled(dev_priv, crtc->plane); |
8652744b | 4938 | if (IS_BROADWELL(dev_priv)) { |
2a114cc1 BW |
4939 | mutex_lock(&dev_priv->rps.hw_lock); |
4940 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4941 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4942 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4943 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4944 | * mailbox." Moreover, the mailbox may return a bogus state, |
4945 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4946 | */ |
4947 | } else { | |
4948 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4949 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4950 | * is essentially intel_wait_for_vblank. If we don't have this | |
4951 | * and don't wait for vblanks until the end of crtc_enable, then | |
4952 | * the HW state readout code will complain that the expected | |
4953 | * IPS_CTL value is not the one we read. */ | |
2ec9ba3c CW |
4954 | if (intel_wait_for_register(dev_priv, |
4955 | IPS_CTL, IPS_ENABLE, IPS_ENABLE, | |
4956 | 50)) | |
2a114cc1 BW |
4957 | DRM_ERROR("Timed out waiting for IPS enable\n"); |
4958 | } | |
d77e4531 PZ |
4959 | } |
4960 | ||
20bc8673 | 4961 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4962 | { |
4963 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4964 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 4965 | |
6e3c9717 | 4966 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4967 | return; |
4968 | ||
4969 | assert_plane_enabled(dev_priv, crtc->plane); | |
8652744b | 4970 | if (IS_BROADWELL(dev_priv)) { |
2a114cc1 BW |
4971 | mutex_lock(&dev_priv->rps.hw_lock); |
4972 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4973 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 | 4974 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
b85c1ecf CW |
4975 | if (intel_wait_for_register(dev_priv, |
4976 | IPS_CTL, IPS_ENABLE, 0, | |
4977 | 42)) | |
23d0b130 | 4978 | DRM_ERROR("Timed out waiting for IPS disable\n"); |
e59150dc | 4979 | } else { |
2a114cc1 | 4980 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4981 | POSTING_READ(IPS_CTL); |
4982 | } | |
d77e4531 PZ |
4983 | |
4984 | /* We need to wait for a vblank before we can disable the plane. */ | |
0f0f74bc | 4985 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
d77e4531 PZ |
4986 | } |
4987 | ||
7cac945f | 4988 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4989 | { |
7cac945f | 4990 | if (intel_crtc->overlay) { |
d3eedb1a | 4991 | struct drm_device *dev = intel_crtc->base.dev; |
d3eedb1a VS |
4992 | |
4993 | mutex_lock(&dev->struct_mutex); | |
d3eedb1a | 4994 | (void) intel_overlay_switch_off(intel_crtc->overlay); |
d3eedb1a VS |
4995 | mutex_unlock(&dev->struct_mutex); |
4996 | } | |
4997 | ||
4998 | /* Let userspace switch the overlay on again. In most cases userspace | |
4999 | * has to recompute where to put it anyway. | |
5000 | */ | |
5001 | } | |
5002 | ||
87d4300a ML |
5003 | /** |
5004 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
5005 | * @crtc: the CRTC whose primary plane was just enabled | |
5006 | * | |
5007 | * Performs potentially sleeping operations that must be done after the primary | |
5008 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
5009 | * called due to an explicit primary plane update, or due to an implicit | |
5010 | * re-enable that is caused when a sprite plane is updated to no longer | |
5011 | * completely hide the primary plane. | |
5012 | */ | |
5013 | static void | |
5014 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
5015 | { |
5016 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 5017 | struct drm_i915_private *dev_priv = to_i915(dev); |
a5c4d7bc VS |
5018 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5019 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 5020 | |
87d4300a ML |
5021 | /* |
5022 | * FIXME IPS should be fine as long as one plane is | |
5023 | * enabled, but in practice it seems to have problems | |
5024 | * when going from primary only to sprite only and vice | |
5025 | * versa. | |
5026 | */ | |
a5c4d7bc VS |
5027 | hsw_enable_ips(intel_crtc); |
5028 | ||
f99d7069 | 5029 | /* |
87d4300a ML |
5030 | * Gen2 reports pipe underruns whenever all planes are disabled. |
5031 | * So don't enable underrun reporting before at least some planes | |
5032 | * are enabled. | |
5033 | * FIXME: Need to fix the logic to work when we turn off all planes | |
5034 | * but leave the pipe running. | |
f99d7069 | 5035 | */ |
5db94019 | 5036 | if (IS_GEN2(dev_priv)) |
87d4300a ML |
5037 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
5038 | ||
aca7b684 VS |
5039 | /* Underruns don't always raise interrupts, so check manually. */ |
5040 | intel_check_cpu_fifo_underruns(dev_priv); | |
5041 | intel_check_pch_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
5042 | } |
5043 | ||
2622a081 | 5044 | /* FIXME move all this to pre_plane_update() with proper state tracking */ |
87d4300a ML |
5045 | static void |
5046 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
5047 | { |
5048 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 5049 | struct drm_i915_private *dev_priv = to_i915(dev); |
a5c4d7bc VS |
5050 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5051 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 5052 | |
87d4300a ML |
5053 | /* |
5054 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
5055 | * So diasble underrun reporting before all the planes get disabled. | |
5056 | * FIXME: Need to fix the logic to work when we turn off all planes | |
5057 | * but leave the pipe running. | |
5058 | */ | |
5db94019 | 5059 | if (IS_GEN2(dev_priv)) |
87d4300a | 5060 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
a5c4d7bc | 5061 | |
2622a081 VS |
5062 | /* |
5063 | * FIXME IPS should be fine as long as one plane is | |
5064 | * enabled, but in practice it seems to have problems | |
5065 | * when going from primary only to sprite only and vice | |
5066 | * versa. | |
5067 | */ | |
5068 | hsw_disable_ips(intel_crtc); | |
5069 | } | |
5070 | ||
5071 | /* FIXME get rid of this and use pre_plane_update */ | |
5072 | static void | |
5073 | intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) | |
5074 | { | |
5075 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 5076 | struct drm_i915_private *dev_priv = to_i915(dev); |
2622a081 VS |
5077 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5078 | int pipe = intel_crtc->pipe; | |
5079 | ||
5080 | intel_pre_disable_primary(crtc); | |
5081 | ||
87d4300a ML |
5082 | /* |
5083 | * Vblank time updates from the shadow to live plane control register | |
5084 | * are blocked if the memory self-refresh mode is active at that | |
5085 | * moment. So to make sure the plane gets truly disabled, disable | |
5086 | * first the self-refresh mode. The self-refresh enable bit in turn | |
5087 | * will be checked/applied by the HW only at the next frame start | |
5088 | * event which is after the vblank start event, so we need to have a | |
5089 | * wait-for-vblank between disabling the plane and the pipe. | |
5090 | */ | |
11a85d6a VS |
5091 | if (HAS_GMCH_DISPLAY(dev_priv) && |
5092 | intel_set_memory_cxsr(dev_priv, false)) | |
0f0f74bc | 5093 | intel_wait_for_vblank(dev_priv, pipe); |
87d4300a ML |
5094 | } |
5095 | ||
5a21b665 DV |
5096 | static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) |
5097 | { | |
5098 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); | |
5099 | struct drm_atomic_state *old_state = old_crtc_state->base.state; | |
5100 | struct intel_crtc_state *pipe_config = | |
5101 | to_intel_crtc_state(crtc->base.state); | |
5a21b665 DV |
5102 | struct drm_plane *primary = crtc->base.primary; |
5103 | struct drm_plane_state *old_pri_state = | |
5104 | drm_atomic_get_existing_plane_state(old_state, primary); | |
5105 | ||
5748b6a1 | 5106 | intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits); |
5a21b665 | 5107 | |
5a21b665 | 5108 | if (pipe_config->update_wm_post && pipe_config->base.active) |
432081bc | 5109 | intel_update_watermarks(crtc); |
5a21b665 DV |
5110 | |
5111 | if (old_pri_state) { | |
5112 | struct intel_plane_state *primary_state = | |
5113 | to_intel_plane_state(primary->state); | |
5114 | struct intel_plane_state *old_primary_state = | |
5115 | to_intel_plane_state(old_pri_state); | |
5116 | ||
5117 | intel_fbc_post_update(crtc); | |
5118 | ||
936e71e3 | 5119 | if (primary_state->base.visible && |
5a21b665 | 5120 | (needs_modeset(&pipe_config->base) || |
936e71e3 | 5121 | !old_primary_state->base.visible)) |
5a21b665 DV |
5122 | intel_post_enable_primary(&crtc->base); |
5123 | } | |
5124 | } | |
5125 | ||
aa5e9b47 ML |
5126 | static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state, |
5127 | struct intel_crtc_state *pipe_config) | |
ac21b225 | 5128 | { |
5c74cd73 | 5129 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
ac21b225 | 5130 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 5131 | struct drm_i915_private *dev_priv = to_i915(dev); |
5c74cd73 ML |
5132 | struct drm_atomic_state *old_state = old_crtc_state->base.state; |
5133 | struct drm_plane *primary = crtc->base.primary; | |
5134 | struct drm_plane_state *old_pri_state = | |
5135 | drm_atomic_get_existing_plane_state(old_state, primary); | |
5136 | bool modeset = needs_modeset(&pipe_config->base); | |
ccf010fb ML |
5137 | struct intel_atomic_state *old_intel_state = |
5138 | to_intel_atomic_state(old_state); | |
ac21b225 | 5139 | |
5c74cd73 ML |
5140 | if (old_pri_state) { |
5141 | struct intel_plane_state *primary_state = | |
5142 | to_intel_plane_state(primary->state); | |
5143 | struct intel_plane_state *old_primary_state = | |
5144 | to_intel_plane_state(old_pri_state); | |
5145 | ||
faf68d92 | 5146 | intel_fbc_pre_update(crtc, pipe_config, primary_state); |
31ae71fc | 5147 | |
936e71e3 VS |
5148 | if (old_primary_state->base.visible && |
5149 | (modeset || !primary_state->base.visible)) | |
5c74cd73 ML |
5150 | intel_pre_disable_primary(&crtc->base); |
5151 | } | |
852eb00d | 5152 | |
5eeb798b VS |
5153 | /* |
5154 | * Vblank time updates from the shadow to live plane control register | |
5155 | * are blocked if the memory self-refresh mode is active at that | |
5156 | * moment. So to make sure the plane gets truly disabled, disable | |
5157 | * first the self-refresh mode. The self-refresh enable bit in turn | |
5158 | * will be checked/applied by the HW only at the next frame start | |
5159 | * event which is after the vblank start event, so we need to have a | |
5160 | * wait-for-vblank between disabling the plane and the pipe. | |
5161 | */ | |
5162 | if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active && | |
5163 | pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false)) | |
5164 | intel_wait_for_vblank(dev_priv, crtc->pipe); | |
92826fcd | 5165 | |
ed4a6a7c MR |
5166 | /* |
5167 | * IVB workaround: must disable low power watermarks for at least | |
5168 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
5169 | * when scaling is disabled. | |
5170 | * | |
5171 | * WaCxSRDisabledForSpriteScaling:ivb | |
5172 | */ | |
ddd2b792 | 5173 | if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev)) |
0f0f74bc | 5174 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
ed4a6a7c MR |
5175 | |
5176 | /* | |
5177 | * If we're doing a modeset, we're done. No need to do any pre-vblank | |
5178 | * watermark programming here. | |
5179 | */ | |
5180 | if (needs_modeset(&pipe_config->base)) | |
5181 | return; | |
5182 | ||
5183 | /* | |
5184 | * For platforms that support atomic watermarks, program the | |
5185 | * 'intermediate' watermarks immediately. On pre-gen9 platforms, these | |
5186 | * will be the intermediate values that are safe for both pre- and | |
5187 | * post- vblank; when vblank happens, the 'active' values will be set | |
5188 | * to the final 'target' values and we'll do this again to get the | |
5189 | * optimal watermarks. For gen9+ platforms, the values we program here | |
5190 | * will be the final target values which will get automatically latched | |
5191 | * at vblank time; no further programming will be necessary. | |
5192 | * | |
5193 | * If a platform hasn't been transitioned to atomic watermarks yet, | |
5194 | * we'll continue to update watermarks the old way, if flags tell | |
5195 | * us to. | |
5196 | */ | |
5197 | if (dev_priv->display.initial_watermarks != NULL) | |
ccf010fb ML |
5198 | dev_priv->display.initial_watermarks(old_intel_state, |
5199 | pipe_config); | |
caed361d | 5200 | else if (pipe_config->update_wm_pre) |
432081bc | 5201 | intel_update_watermarks(crtc); |
ac21b225 ML |
5202 | } |
5203 | ||
d032ffa0 | 5204 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
5205 | { |
5206 | struct drm_device *dev = crtc->dev; | |
5207 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 5208 | struct drm_plane *p; |
87d4300a ML |
5209 | int pipe = intel_crtc->pipe; |
5210 | ||
7cac945f | 5211 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 5212 | |
d032ffa0 | 5213 | drm_for_each_plane_mask(p, dev, plane_mask) |
282dbf9b | 5214 | to_intel_plane(p)->disable_plane(to_intel_plane(p), intel_crtc); |
f98551ae | 5215 | |
f99d7069 DV |
5216 | /* |
5217 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
5218 | * to compute the mask of flip planes precisely. For the time being | |
5219 | * consider this a flip to a NULL plane. | |
5220 | */ | |
5748b6a1 | 5221 | intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe)); |
a5c4d7bc VS |
5222 | } |
5223 | ||
fb1c98b1 | 5224 | static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc, |
fd6bbda9 | 5225 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5226 | struct drm_atomic_state *old_state) |
5227 | { | |
aa5e9b47 | 5228 | struct drm_connector_state *conn_state; |
fb1c98b1 ML |
5229 | struct drm_connector *conn; |
5230 | int i; | |
5231 | ||
aa5e9b47 | 5232 | for_each_new_connector_in_state(old_state, conn, conn_state, i) { |
fb1c98b1 ML |
5233 | struct intel_encoder *encoder = |
5234 | to_intel_encoder(conn_state->best_encoder); | |
5235 | ||
5236 | if (conn_state->crtc != crtc) | |
5237 | continue; | |
5238 | ||
5239 | if (encoder->pre_pll_enable) | |
fd6bbda9 | 5240 | encoder->pre_pll_enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5241 | } |
5242 | } | |
5243 | ||
5244 | static void intel_encoders_pre_enable(struct drm_crtc *crtc, | |
fd6bbda9 | 5245 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5246 | struct drm_atomic_state *old_state) |
5247 | { | |
aa5e9b47 | 5248 | struct drm_connector_state *conn_state; |
fb1c98b1 ML |
5249 | struct drm_connector *conn; |
5250 | int i; | |
5251 | ||
aa5e9b47 | 5252 | for_each_new_connector_in_state(old_state, conn, conn_state, i) { |
fb1c98b1 ML |
5253 | struct intel_encoder *encoder = |
5254 | to_intel_encoder(conn_state->best_encoder); | |
5255 | ||
5256 | if (conn_state->crtc != crtc) | |
5257 | continue; | |
5258 | ||
5259 | if (encoder->pre_enable) | |
fd6bbda9 | 5260 | encoder->pre_enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5261 | } |
5262 | } | |
5263 | ||
5264 | static void intel_encoders_enable(struct drm_crtc *crtc, | |
fd6bbda9 | 5265 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5266 | struct drm_atomic_state *old_state) |
5267 | { | |
aa5e9b47 | 5268 | struct drm_connector_state *conn_state; |
fb1c98b1 ML |
5269 | struct drm_connector *conn; |
5270 | int i; | |
5271 | ||
aa5e9b47 | 5272 | for_each_new_connector_in_state(old_state, conn, conn_state, i) { |
fb1c98b1 ML |
5273 | struct intel_encoder *encoder = |
5274 | to_intel_encoder(conn_state->best_encoder); | |
5275 | ||
5276 | if (conn_state->crtc != crtc) | |
5277 | continue; | |
5278 | ||
fd6bbda9 | 5279 | encoder->enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5280 | intel_opregion_notify_encoder(encoder, true); |
5281 | } | |
5282 | } | |
5283 | ||
5284 | static void intel_encoders_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5285 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5286 | struct drm_atomic_state *old_state) |
5287 | { | |
5288 | struct drm_connector_state *old_conn_state; | |
5289 | struct drm_connector *conn; | |
5290 | int i; | |
5291 | ||
aa5e9b47 | 5292 | for_each_old_connector_in_state(old_state, conn, old_conn_state, i) { |
fb1c98b1 ML |
5293 | struct intel_encoder *encoder = |
5294 | to_intel_encoder(old_conn_state->best_encoder); | |
5295 | ||
5296 | if (old_conn_state->crtc != crtc) | |
5297 | continue; | |
5298 | ||
5299 | intel_opregion_notify_encoder(encoder, false); | |
fd6bbda9 | 5300 | encoder->disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5301 | } |
5302 | } | |
5303 | ||
5304 | static void intel_encoders_post_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5305 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5306 | struct drm_atomic_state *old_state) |
5307 | { | |
5308 | struct drm_connector_state *old_conn_state; | |
5309 | struct drm_connector *conn; | |
5310 | int i; | |
5311 | ||
aa5e9b47 | 5312 | for_each_old_connector_in_state(old_state, conn, old_conn_state, i) { |
fb1c98b1 ML |
5313 | struct intel_encoder *encoder = |
5314 | to_intel_encoder(old_conn_state->best_encoder); | |
5315 | ||
5316 | if (old_conn_state->crtc != crtc) | |
5317 | continue; | |
5318 | ||
5319 | if (encoder->post_disable) | |
fd6bbda9 | 5320 | encoder->post_disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5321 | } |
5322 | } | |
5323 | ||
5324 | static void intel_encoders_post_pll_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5325 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5326 | struct drm_atomic_state *old_state) |
5327 | { | |
5328 | struct drm_connector_state *old_conn_state; | |
5329 | struct drm_connector *conn; | |
5330 | int i; | |
5331 | ||
aa5e9b47 | 5332 | for_each_old_connector_in_state(old_state, conn, old_conn_state, i) { |
fb1c98b1 ML |
5333 | struct intel_encoder *encoder = |
5334 | to_intel_encoder(old_conn_state->best_encoder); | |
5335 | ||
5336 | if (old_conn_state->crtc != crtc) | |
5337 | continue; | |
5338 | ||
5339 | if (encoder->post_pll_disable) | |
fd6bbda9 | 5340 | encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5341 | } |
5342 | } | |
5343 | ||
4a806558 ML |
5344 | static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config, |
5345 | struct drm_atomic_state *old_state) | |
f67a559d | 5346 | { |
4a806558 | 5347 | struct drm_crtc *crtc = pipe_config->base.crtc; |
f67a559d | 5348 | struct drm_device *dev = crtc->dev; |
fac5e23e | 5349 | struct drm_i915_private *dev_priv = to_i915(dev); |
f67a559d JB |
5350 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5351 | int pipe = intel_crtc->pipe; | |
ccf010fb ML |
5352 | struct intel_atomic_state *old_intel_state = |
5353 | to_intel_atomic_state(old_state); | |
f67a559d | 5354 | |
53d9f4e9 | 5355 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
5356 | return; |
5357 | ||
b2c0593a VS |
5358 | /* |
5359 | * Sometimes spurious CPU pipe underruns happen during FDI | |
5360 | * training, at least with VGA+HDMI cloning. Suppress them. | |
5361 | * | |
5362 | * On ILK we get an occasional spurious CPU pipe underruns | |
5363 | * between eDP port A enable and vdd enable. Also PCH port | |
5364 | * enable seems to result in the occasional CPU pipe underrun. | |
5365 | * | |
5366 | * Spurious PCH underruns also occur during PCH enabling. | |
5367 | */ | |
5368 | if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv)) | |
5369 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
81b088ca VS |
5370 | if (intel_crtc->config->has_pch_encoder) |
5371 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
5372 | ||
6e3c9717 | 5373 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
5374 | intel_prepare_shared_dpll(intel_crtc); |
5375 | ||
37a5650b | 5376 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 5377 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
5378 | |
5379 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 5380 | intel_set_pipe_src_size(intel_crtc); |
29407aab | 5381 | |
6e3c9717 | 5382 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 5383 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5384 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
5385 | } |
5386 | ||
5387 | ironlake_set_pipeconf(crtc); | |
5388 | ||
f67a559d | 5389 | intel_crtc->active = true; |
8664281b | 5390 | |
fd6bbda9 | 5391 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
f67a559d | 5392 | |
6e3c9717 | 5393 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
5394 | /* Note: FDI PLL enabling _must_ be done before we enable the |
5395 | * cpu pipes, hence this is separate from all the other fdi/pch | |
5396 | * enabling. */ | |
88cefb6c | 5397 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
5398 | } else { |
5399 | assert_fdi_tx_disabled(dev_priv, pipe); | |
5400 | assert_fdi_rx_disabled(dev_priv, pipe); | |
5401 | } | |
f67a559d | 5402 | |
b074cec8 | 5403 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 5404 | |
9c54c0dd JB |
5405 | /* |
5406 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5407 | * clocks enabled | |
5408 | */ | |
b95c5321 | 5409 | intel_color_load_luts(&pipe_config->base); |
9c54c0dd | 5410 | |
1d5bf5d9 | 5411 | if (dev_priv->display.initial_watermarks != NULL) |
ccf010fb | 5412 | dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config); |
e1fdc473 | 5413 | intel_enable_pipe(intel_crtc); |
f67a559d | 5414 | |
6e3c9717 | 5415 | if (intel_crtc->config->has_pch_encoder) |
2ce42273 | 5416 | ironlake_pch_enable(pipe_config); |
c98e9dcf | 5417 | |
f9b61ff6 DV |
5418 | assert_vblank_disabled(crtc); |
5419 | drm_crtc_vblank_on(crtc); | |
5420 | ||
fd6bbda9 | 5421 | intel_encoders_enable(crtc, pipe_config, old_state); |
61b77ddd | 5422 | |
6e266956 | 5423 | if (HAS_PCH_CPT(dev_priv)) |
a1520318 | 5424 | cpt_verify_modeset(dev, intel_crtc->pipe); |
37ca8d4c VS |
5425 | |
5426 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ | |
5427 | if (intel_crtc->config->has_pch_encoder) | |
0f0f74bc | 5428 | intel_wait_for_vblank(dev_priv, pipe); |
b2c0593a | 5429 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
37ca8d4c | 5430 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 JB |
5431 | } |
5432 | ||
42db64ef PZ |
5433 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
5434 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
5435 | { | |
50a0bc90 | 5436 | return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A; |
42db64ef PZ |
5437 | } |
5438 | ||
4a806558 ML |
5439 | static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, |
5440 | struct drm_atomic_state *old_state) | |
4f771f10 | 5441 | { |
4a806558 | 5442 | struct drm_crtc *crtc = pipe_config->base.crtc; |
6315b5d3 | 5443 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
4f771f10 | 5444 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
99d736a2 | 5445 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4d1de975 | 5446 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ccf010fb ML |
5447 | struct intel_atomic_state *old_intel_state = |
5448 | to_intel_atomic_state(old_state); | |
4f771f10 | 5449 | |
53d9f4e9 | 5450 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
5451 | return; |
5452 | ||
81b088ca | 5453 | if (intel_crtc->config->has_pch_encoder) |
29012159 | 5454 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); |
81b088ca | 5455 | |
fd6bbda9 | 5456 | intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); |
95a7a2ae | 5457 | |
8106ddbd | 5458 | if (intel_crtc->config->shared_dpll) |
df8ad70c DV |
5459 | intel_enable_shared_dpll(intel_crtc); |
5460 | ||
37a5650b | 5461 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 5462 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 | 5463 | |
d7edc4e5 | 5464 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 JN |
5465 | intel_set_pipe_timings(intel_crtc); |
5466 | ||
bc58be60 | 5467 | intel_set_pipe_src_size(intel_crtc); |
229fca97 | 5468 | |
4d1de975 JN |
5469 | if (cpu_transcoder != TRANSCODER_EDP && |
5470 | !transcoder_is_dsi(cpu_transcoder)) { | |
5471 | I915_WRITE(PIPE_MULT(cpu_transcoder), | |
6e3c9717 | 5472 | intel_crtc->config->pixel_multiplier - 1); |
ebb69c95 CT |
5473 | } |
5474 | ||
6e3c9717 | 5475 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 5476 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5477 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
5478 | } |
5479 | ||
d7edc4e5 | 5480 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 JN |
5481 | haswell_set_pipeconf(crtc); |
5482 | ||
391bf048 | 5483 | haswell_set_pipemisc(crtc); |
229fca97 | 5484 | |
b95c5321 | 5485 | intel_color_set_csc(&pipe_config->base); |
229fca97 | 5486 | |
4f771f10 | 5487 | intel_crtc->active = true; |
8664281b | 5488 | |
6b698516 DV |
5489 | if (intel_crtc->config->has_pch_encoder) |
5490 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
5491 | else | |
5492 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
5493 | ||
fd6bbda9 | 5494 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
4f771f10 | 5495 | |
d2d65408 | 5496 | if (intel_crtc->config->has_pch_encoder) |
dc4a1094 | 5497 | dev_priv->display.fdi_link_train(intel_crtc, pipe_config); |
4fe9467d | 5498 | |
d7edc4e5 | 5499 | if (!transcoder_is_dsi(cpu_transcoder)) |
3dc38eea | 5500 | intel_ddi_enable_pipe_clock(pipe_config); |
4f771f10 | 5501 | |
6315b5d3 | 5502 | if (INTEL_GEN(dev_priv) >= 9) |
e435d6e5 | 5503 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 5504 | else |
1c132b44 | 5505 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
5506 | |
5507 | /* | |
5508 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5509 | * clocks enabled | |
5510 | */ | |
b95c5321 | 5511 | intel_color_load_luts(&pipe_config->base); |
4f771f10 | 5512 | |
3dc38eea | 5513 | intel_ddi_set_pipe_settings(pipe_config); |
d7edc4e5 | 5514 | if (!transcoder_is_dsi(cpu_transcoder)) |
3dc38eea | 5515 | intel_ddi_enable_transcoder_func(pipe_config); |
4f771f10 | 5516 | |
1d5bf5d9 | 5517 | if (dev_priv->display.initial_watermarks != NULL) |
3125d39f | 5518 | dev_priv->display.initial_watermarks(old_intel_state, pipe_config); |
4d1de975 JN |
5519 | |
5520 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ | |
d7edc4e5 | 5521 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 | 5522 | intel_enable_pipe(intel_crtc); |
42db64ef | 5523 | |
6e3c9717 | 5524 | if (intel_crtc->config->has_pch_encoder) |
2ce42273 | 5525 | lpt_pch_enable(pipe_config); |
4f771f10 | 5526 | |
0037071d | 5527 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST)) |
3dc38eea | 5528 | intel_ddi_set_vc_payload_alloc(pipe_config, true); |
0e32b39c | 5529 | |
f9b61ff6 DV |
5530 | assert_vblank_disabled(crtc); |
5531 | drm_crtc_vblank_on(crtc); | |
5532 | ||
fd6bbda9 | 5533 | intel_encoders_enable(crtc, pipe_config, old_state); |
4f771f10 | 5534 | |
6b698516 | 5535 | if (intel_crtc->config->has_pch_encoder) { |
0f0f74bc VS |
5536 | intel_wait_for_vblank(dev_priv, pipe); |
5537 | intel_wait_for_vblank(dev_priv, pipe); | |
6b698516 | 5538 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
29012159 | 5539 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
6b698516 | 5540 | } |
d2d65408 | 5541 | |
e4916946 PZ |
5542 | /* If we change the relative order between pipe/planes enabling, we need |
5543 | * to change the workaround. */ | |
99d736a2 | 5544 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
772c2a51 | 5545 | if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { |
0f0f74bc VS |
5546 | intel_wait_for_vblank(dev_priv, hsw_workaround_pipe); |
5547 | intel_wait_for_vblank(dev_priv, hsw_workaround_pipe); | |
99d736a2 | 5548 | } |
4f771f10 PZ |
5549 | } |
5550 | ||
bfd16b2a | 5551 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
5552 | { |
5553 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 5554 | struct drm_i915_private *dev_priv = to_i915(dev); |
3f8dce3a DV |
5555 | int pipe = crtc->pipe; |
5556 | ||
5557 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
5558 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 5559 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
5560 | I915_WRITE(PF_CTL(pipe), 0); |
5561 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
5562 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
5563 | } | |
5564 | } | |
5565 | ||
4a806558 ML |
5566 | static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state, |
5567 | struct drm_atomic_state *old_state) | |
6be4a607 | 5568 | { |
4a806558 | 5569 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
6be4a607 | 5570 | struct drm_device *dev = crtc->dev; |
fac5e23e | 5571 | struct drm_i915_private *dev_priv = to_i915(dev); |
6be4a607 JB |
5572 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5573 | int pipe = intel_crtc->pipe; | |
b52eb4dc | 5574 | |
b2c0593a VS |
5575 | /* |
5576 | * Sometimes spurious CPU pipe underruns happen when the | |
5577 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
5578 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
5579 | */ | |
5580 | if (intel_crtc->config->has_pch_encoder) { | |
5581 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
37ca8d4c | 5582 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
b2c0593a | 5583 | } |
37ca8d4c | 5584 | |
fd6bbda9 | 5585 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
ea9d758d | 5586 | |
f9b61ff6 DV |
5587 | drm_crtc_vblank_off(crtc); |
5588 | assert_vblank_disabled(crtc); | |
5589 | ||
575f7ab7 | 5590 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5591 | |
bfd16b2a | 5592 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 5593 | |
b2c0593a | 5594 | if (intel_crtc->config->has_pch_encoder) |
5a74f70a VS |
5595 | ironlake_fdi_disable(crtc); |
5596 | ||
fd6bbda9 | 5597 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
2c07245f | 5598 | |
6e3c9717 | 5599 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5600 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5601 | |
6e266956 | 5602 | if (HAS_PCH_CPT(dev_priv)) { |
f0f59a00 VS |
5603 | i915_reg_t reg; |
5604 | u32 temp; | |
5605 | ||
d925c59a DV |
5606 | /* disable TRANS_DP_CTL */ |
5607 | reg = TRANS_DP_CTL(pipe); | |
5608 | temp = I915_READ(reg); | |
5609 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5610 | TRANS_DP_PORT_SEL_MASK); | |
5611 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5612 | I915_WRITE(reg, temp); | |
5613 | ||
5614 | /* disable DPLL_SEL */ | |
5615 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5616 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5617 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5618 | } |
e3421a18 | 5619 | |
d925c59a DV |
5620 | ironlake_fdi_pll_disable(intel_crtc); |
5621 | } | |
81b088ca | 5622 | |
b2c0593a | 5623 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
81b088ca | 5624 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 | 5625 | } |
1b3c7a47 | 5626 | |
4a806558 ML |
5627 | static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state, |
5628 | struct drm_atomic_state *old_state) | |
ee7b9f93 | 5629 | { |
4a806558 | 5630 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
6315b5d3 | 5631 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
ee7b9f93 | 5632 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 5633 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5634 | |
d2d65408 | 5635 | if (intel_crtc->config->has_pch_encoder) |
29012159 | 5636 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); |
d2d65408 | 5637 | |
fd6bbda9 | 5638 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
4f771f10 | 5639 | |
f9b61ff6 DV |
5640 | drm_crtc_vblank_off(crtc); |
5641 | assert_vblank_disabled(crtc); | |
5642 | ||
4d1de975 | 5643 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ |
d7edc4e5 | 5644 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 | 5645 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5646 | |
0037071d | 5647 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST)) |
3dc38eea | 5648 | intel_ddi_set_vc_payload_alloc(intel_crtc->config, false); |
a4bf214f | 5649 | |
d7edc4e5 | 5650 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5651 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5652 | |
6315b5d3 | 5653 | if (INTEL_GEN(dev_priv) >= 9) |
e435d6e5 | 5654 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5655 | else |
bfd16b2a | 5656 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 5657 | |
d7edc4e5 | 5658 | if (!transcoder_is_dsi(cpu_transcoder)) |
3dc38eea | 5659 | intel_ddi_disable_pipe_clock(intel_crtc->config); |
4f771f10 | 5660 | |
fd6bbda9 | 5661 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
81b088ca | 5662 | |
b7076546 | 5663 | if (old_crtc_state->has_pch_encoder) |
29012159 | 5664 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
4f771f10 PZ |
5665 | } |
5666 | ||
2dd24552 JB |
5667 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5668 | { | |
5669 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 5670 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 5671 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5672 | |
681a8504 | 5673 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5674 | return; |
5675 | ||
2dd24552 | 5676 | /* |
c0b03411 DV |
5677 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5678 | * according to register description and PRM. | |
2dd24552 | 5679 | */ |
c0b03411 DV |
5680 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5681 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5682 | |
b074cec8 JB |
5683 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5684 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5685 | |
5686 | /* Border color in case we don't scale up to the full screen. Black by | |
5687 | * default, change to something else for debugging. */ | |
5688 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5689 | } |
5690 | ||
79f255a0 | 5691 | enum intel_display_power_domain intel_port_to_power_domain(enum port port) |
d05410f9 DA |
5692 | { |
5693 | switch (port) { | |
5694 | case PORT_A: | |
6331a704 | 5695 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
d05410f9 | 5696 | case PORT_B: |
6331a704 | 5697 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
d05410f9 | 5698 | case PORT_C: |
6331a704 | 5699 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
d05410f9 | 5700 | case PORT_D: |
6331a704 | 5701 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
d8e19f99 | 5702 | case PORT_E: |
6331a704 | 5703 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
d05410f9 | 5704 | default: |
b9fec167 | 5705 | MISSING_CASE(port); |
d05410f9 DA |
5706 | return POWER_DOMAIN_PORT_OTHER; |
5707 | } | |
5708 | } | |
5709 | ||
d8fc70b7 ACO |
5710 | static u64 get_crtc_power_domains(struct drm_crtc *crtc, |
5711 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5712 | { |
319be8ae | 5713 | struct drm_device *dev = crtc->dev; |
37255d8d | 5714 | struct drm_i915_private *dev_priv = to_i915(dev); |
74bff5f9 | 5715 | struct drm_encoder *encoder; |
319be8ae ID |
5716 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5717 | enum pipe pipe = intel_crtc->pipe; | |
d8fc70b7 | 5718 | u64 mask; |
74bff5f9 | 5719 | enum transcoder transcoder = crtc_state->cpu_transcoder; |
77d22dca | 5720 | |
74bff5f9 | 5721 | if (!crtc_state->base.active) |
292b990e ML |
5722 | return 0; |
5723 | ||
77d22dca ID |
5724 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5725 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
74bff5f9 ML |
5726 | if (crtc_state->pch_pfit.enabled || |
5727 | crtc_state->pch_pfit.force_thru) | |
d8fc70b7 | 5728 | mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
77d22dca | 5729 | |
74bff5f9 ML |
5730 | drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) { |
5731 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
5732 | ||
79f255a0 | 5733 | mask |= BIT_ULL(intel_encoder->power_domain); |
74bff5f9 | 5734 | } |
319be8ae | 5735 | |
37255d8d ML |
5736 | if (HAS_DDI(dev_priv) && crtc_state->has_audio) |
5737 | mask |= BIT(POWER_DOMAIN_AUDIO); | |
5738 | ||
15e7ec29 | 5739 | if (crtc_state->shared_dpll) |
d8fc70b7 | 5740 | mask |= BIT_ULL(POWER_DOMAIN_PLLS); |
15e7ec29 | 5741 | |
77d22dca ID |
5742 | return mask; |
5743 | } | |
5744 | ||
d2d15016 | 5745 | static u64 |
74bff5f9 ML |
5746 | modeset_get_crtc_power_domains(struct drm_crtc *crtc, |
5747 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5748 | { |
fac5e23e | 5749 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
292b990e ML |
5750 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5751 | enum intel_display_power_domain domain; | |
d8fc70b7 | 5752 | u64 domains, new_domains, old_domains; |
77d22dca | 5753 | |
292b990e | 5754 | old_domains = intel_crtc->enabled_power_domains; |
74bff5f9 ML |
5755 | intel_crtc->enabled_power_domains = new_domains = |
5756 | get_crtc_power_domains(crtc, crtc_state); | |
77d22dca | 5757 | |
5a21b665 | 5758 | domains = new_domains & ~old_domains; |
292b990e ML |
5759 | |
5760 | for_each_power_domain(domain, domains) | |
5761 | intel_display_power_get(dev_priv, domain); | |
5762 | ||
5a21b665 | 5763 | return old_domains & ~new_domains; |
292b990e ML |
5764 | } |
5765 | ||
5766 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
d8fc70b7 | 5767 | u64 domains) |
292b990e ML |
5768 | { |
5769 | enum intel_display_power_domain domain; | |
5770 | ||
5771 | for_each_power_domain(domain, domains) | |
5772 | intel_display_power_put(dev_priv, domain); | |
5773 | } | |
77d22dca | 5774 | |
7ff89ca2 VS |
5775 | static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config, |
5776 | struct drm_atomic_state *old_state) | |
adafdc6f | 5777 | { |
ff32c54e VS |
5778 | struct intel_atomic_state *old_intel_state = |
5779 | to_intel_atomic_state(old_state); | |
7ff89ca2 VS |
5780 | struct drm_crtc *crtc = pipe_config->base.crtc; |
5781 | struct drm_device *dev = crtc->dev; | |
5782 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5783 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5784 | int pipe = intel_crtc->pipe; | |
adafdc6f | 5785 | |
7ff89ca2 VS |
5786 | if (WARN_ON(intel_crtc->active)) |
5787 | return; | |
adafdc6f | 5788 | |
7ff89ca2 VS |
5789 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
5790 | intel_dp_set_m_n(intel_crtc, M1_N1); | |
b2045352 | 5791 | |
7ff89ca2 VS |
5792 | intel_set_pipe_timings(intel_crtc); |
5793 | intel_set_pipe_src_size(intel_crtc); | |
b2045352 | 5794 | |
7ff89ca2 VS |
5795 | if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { |
5796 | struct drm_i915_private *dev_priv = to_i915(dev); | |
560a7ae4 | 5797 | |
7ff89ca2 VS |
5798 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); |
5799 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
560a7ae4 DL |
5800 | } |
5801 | ||
7ff89ca2 | 5802 | i9xx_set_pipeconf(intel_crtc); |
560a7ae4 | 5803 | |
7ff89ca2 | 5804 | intel_crtc->active = true; |
92891e45 | 5805 | |
7ff89ca2 | 5806 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
5f199dfa | 5807 | |
7ff89ca2 | 5808 | intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); |
5f199dfa | 5809 | |
7ff89ca2 VS |
5810 | if (IS_CHERRYVIEW(dev_priv)) { |
5811 | chv_prepare_pll(intel_crtc, intel_crtc->config); | |
5812 | chv_enable_pll(intel_crtc, intel_crtc->config); | |
5813 | } else { | |
5814 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
5815 | vlv_enable_pll(intel_crtc, intel_crtc->config); | |
5f199dfa VS |
5816 | } |
5817 | ||
7ff89ca2 | 5818 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
5f199dfa | 5819 | |
7ff89ca2 | 5820 | i9xx_pfit_enable(intel_crtc); |
89b3c3c7 | 5821 | |
7ff89ca2 | 5822 | intel_color_load_luts(&pipe_config->base); |
89b3c3c7 | 5823 | |
ff32c54e VS |
5824 | dev_priv->display.initial_watermarks(old_intel_state, |
5825 | pipe_config); | |
7ff89ca2 VS |
5826 | intel_enable_pipe(intel_crtc); |
5827 | ||
5828 | assert_vblank_disabled(crtc); | |
5829 | drm_crtc_vblank_on(crtc); | |
89b3c3c7 | 5830 | |
7ff89ca2 | 5831 | intel_encoders_enable(crtc, pipe_config, old_state); |
89b3c3c7 ACO |
5832 | } |
5833 | ||
7ff89ca2 | 5834 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
2b73001e | 5835 | { |
7ff89ca2 VS |
5836 | struct drm_device *dev = crtc->base.dev; |
5837 | struct drm_i915_private *dev_priv = to_i915(dev); | |
83d7c81f | 5838 | |
7ff89ca2 VS |
5839 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
5840 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
2b73001e VS |
5841 | } |
5842 | ||
7ff89ca2 VS |
5843 | static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config, |
5844 | struct drm_atomic_state *old_state) | |
2b73001e | 5845 | { |
04548cba VS |
5846 | struct intel_atomic_state *old_intel_state = |
5847 | to_intel_atomic_state(old_state); | |
7ff89ca2 VS |
5848 | struct drm_crtc *crtc = pipe_config->base.crtc; |
5849 | struct drm_device *dev = crtc->dev; | |
5850 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5851 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5852 | enum pipe pipe = intel_crtc->pipe; | |
2b73001e | 5853 | |
7ff89ca2 VS |
5854 | if (WARN_ON(intel_crtc->active)) |
5855 | return; | |
2b73001e | 5856 | |
7ff89ca2 | 5857 | i9xx_set_pll_dividers(intel_crtc); |
2b73001e | 5858 | |
7ff89ca2 VS |
5859 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
5860 | intel_dp_set_m_n(intel_crtc, M1_N1); | |
83d7c81f | 5861 | |
7ff89ca2 VS |
5862 | intel_set_pipe_timings(intel_crtc); |
5863 | intel_set_pipe_src_size(intel_crtc); | |
2b73001e | 5864 | |
7ff89ca2 | 5865 | i9xx_set_pipeconf(intel_crtc); |
f8437dd1 | 5866 | |
7ff89ca2 | 5867 | intel_crtc->active = true; |
5f199dfa | 5868 | |
7ff89ca2 VS |
5869 | if (!IS_GEN2(dev_priv)) |
5870 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
5f199dfa | 5871 | |
7ff89ca2 | 5872 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
f8437dd1 | 5873 | |
7ff89ca2 | 5874 | i9xx_enable_pll(intel_crtc); |
f8437dd1 | 5875 | |
7ff89ca2 | 5876 | i9xx_pfit_enable(intel_crtc); |
f8437dd1 | 5877 | |
7ff89ca2 | 5878 | intel_color_load_luts(&pipe_config->base); |
f8437dd1 | 5879 | |
04548cba VS |
5880 | if (dev_priv->display.initial_watermarks != NULL) |
5881 | dev_priv->display.initial_watermarks(old_intel_state, | |
5882 | intel_crtc->config); | |
5883 | else | |
5884 | intel_update_watermarks(intel_crtc); | |
7ff89ca2 | 5885 | intel_enable_pipe(intel_crtc); |
f8437dd1 | 5886 | |
7ff89ca2 VS |
5887 | assert_vblank_disabled(crtc); |
5888 | drm_crtc_vblank_on(crtc); | |
f8437dd1 | 5889 | |
7ff89ca2 VS |
5890 | intel_encoders_enable(crtc, pipe_config, old_state); |
5891 | } | |
f8437dd1 | 5892 | |
7ff89ca2 VS |
5893 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
5894 | { | |
5895 | struct drm_device *dev = crtc->base.dev; | |
5896 | struct drm_i915_private *dev_priv = to_i915(dev); | |
f8437dd1 | 5897 | |
7ff89ca2 | 5898 | if (!crtc->config->gmch_pfit.control) |
f8437dd1 | 5899 | return; |
f8437dd1 | 5900 | |
7ff89ca2 VS |
5901 | assert_pipe_disabled(dev_priv, crtc->pipe); |
5902 | ||
5903 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", | |
5904 | I915_READ(PFIT_CONTROL)); | |
5905 | I915_WRITE(PFIT_CONTROL, 0); | |
f8437dd1 VK |
5906 | } |
5907 | ||
7ff89ca2 VS |
5908 | static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state, |
5909 | struct drm_atomic_state *old_state) | |
f8437dd1 | 5910 | { |
7ff89ca2 VS |
5911 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
5912 | struct drm_device *dev = crtc->dev; | |
5913 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5914 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5915 | int pipe = intel_crtc->pipe; | |
d66a2194 | 5916 | |
d66a2194 | 5917 | /* |
7ff89ca2 VS |
5918 | * On gen2 planes are double buffered but the pipe isn't, so we must |
5919 | * wait for planes to fully turn off before disabling the pipe. | |
d66a2194 | 5920 | */ |
7ff89ca2 VS |
5921 | if (IS_GEN2(dev_priv)) |
5922 | intel_wait_for_vblank(dev_priv, pipe); | |
d66a2194 | 5923 | |
7ff89ca2 | 5924 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
d66a2194 | 5925 | |
7ff89ca2 VS |
5926 | drm_crtc_vblank_off(crtc); |
5927 | assert_vblank_disabled(crtc); | |
d66a2194 | 5928 | |
7ff89ca2 | 5929 | intel_disable_pipe(intel_crtc); |
d66a2194 | 5930 | |
7ff89ca2 | 5931 | i9xx_pfit_disable(intel_crtc); |
89b3c3c7 | 5932 | |
7ff89ca2 | 5933 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
d66a2194 | 5934 | |
7ff89ca2 VS |
5935 | if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) { |
5936 | if (IS_CHERRYVIEW(dev_priv)) | |
5937 | chv_disable_pll(dev_priv, pipe); | |
5938 | else if (IS_VALLEYVIEW(dev_priv)) | |
5939 | vlv_disable_pll(dev_priv, pipe); | |
5940 | else | |
5941 | i9xx_disable_pll(intel_crtc); | |
5942 | } | |
c2e001ef | 5943 | |
7ff89ca2 | 5944 | intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state); |
89b3c3c7 | 5945 | |
7ff89ca2 VS |
5946 | if (!IS_GEN2(dev_priv)) |
5947 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
ff32c54e VS |
5948 | |
5949 | if (!dev_priv->display.initial_watermarks) | |
5950 | intel_update_watermarks(intel_crtc); | |
2ee0da16 VS |
5951 | |
5952 | /* clock the pipe down to 640x480@60 to potentially save power */ | |
5953 | if (IS_I830(dev_priv)) | |
5954 | i830_enable_pipe(dev_priv, pipe); | |
f8437dd1 VK |
5955 | } |
5956 | ||
da1d0e26 VS |
5957 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc, |
5958 | struct drm_modeset_acquire_ctx *ctx) | |
f8437dd1 | 5959 | { |
7ff89ca2 VS |
5960 | struct intel_encoder *encoder; |
5961 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5962 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
5963 | enum intel_display_power_domain domain; | |
d2d15016 | 5964 | u64 domains; |
7ff89ca2 VS |
5965 | struct drm_atomic_state *state; |
5966 | struct intel_crtc_state *crtc_state; | |
5967 | int ret; | |
f8437dd1 | 5968 | |
7ff89ca2 VS |
5969 | if (!intel_crtc->active) |
5970 | return; | |
a8ca4934 | 5971 | |
7ff89ca2 | 5972 | if (crtc->primary->state->visible) { |
7ff89ca2 | 5973 | intel_pre_disable_primary_noatomic(crtc); |
709e05c3 | 5974 | |
7ff89ca2 VS |
5975 | intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); |
5976 | crtc->primary->state->visible = false; | |
5977 | } | |
5d96d8af | 5978 | |
7ff89ca2 VS |
5979 | state = drm_atomic_state_alloc(crtc->dev); |
5980 | if (!state) { | |
5981 | DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory", | |
5982 | crtc->base.id, crtc->name); | |
1c3f7700 | 5983 | return; |
7ff89ca2 | 5984 | } |
9f7eb31a | 5985 | |
da1d0e26 | 5986 | state->acquire_ctx = ctx; |
ea61791e | 5987 | |
7ff89ca2 VS |
5988 | /* Everything's already locked, -EDEADLK can't happen. */ |
5989 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); | |
5990 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
9f7eb31a | 5991 | |
7ff89ca2 | 5992 | WARN_ON(IS_ERR(crtc_state) || ret); |
5d96d8af | 5993 | |
7ff89ca2 | 5994 | dev_priv->display.crtc_disable(crtc_state, state); |
4a806558 | 5995 | |
0853695c | 5996 | drm_atomic_state_put(state); |
842e0307 | 5997 | |
78108b7c VS |
5998 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", |
5999 | crtc->base.id, crtc->name); | |
842e0307 ML |
6000 | |
6001 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0); | |
6002 | crtc->state->active = false; | |
37d9078b | 6003 | intel_crtc->active = false; |
842e0307 ML |
6004 | crtc->enabled = false; |
6005 | crtc->state->connector_mask = 0; | |
6006 | crtc->state->encoder_mask = 0; | |
6007 | ||
6008 | for_each_encoder_on_crtc(crtc->dev, crtc, encoder) | |
6009 | encoder->base.crtc = NULL; | |
6010 | ||
58f9c0bc | 6011 | intel_fbc_disable(intel_crtc); |
432081bc | 6012 | intel_update_watermarks(intel_crtc); |
1f7457b1 | 6013 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
6014 | |
6015 | domains = intel_crtc->enabled_power_domains; | |
6016 | for_each_power_domain(domain, domains) | |
6017 | intel_display_power_put(dev_priv, domain); | |
6018 | intel_crtc->enabled_power_domains = 0; | |
565602d7 ML |
6019 | |
6020 | dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); | |
6021 | dev_priv->min_pixclk[intel_crtc->pipe] = 0; | |
b17d48e2 ML |
6022 | } |
6023 | ||
6b72d486 ML |
6024 | /* |
6025 | * turn all crtc's off, but do not adjust state | |
6026 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
6027 | */ | |
70e0bd74 | 6028 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 6029 | { |
e2c8b870 | 6030 | struct drm_i915_private *dev_priv = to_i915(dev); |
70e0bd74 | 6031 | struct drm_atomic_state *state; |
e2c8b870 | 6032 | int ret; |
70e0bd74 | 6033 | |
e2c8b870 ML |
6034 | state = drm_atomic_helper_suspend(dev); |
6035 | ret = PTR_ERR_OR_ZERO(state); | |
70e0bd74 ML |
6036 | if (ret) |
6037 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
e2c8b870 ML |
6038 | else |
6039 | dev_priv->modeset_restore_state = state; | |
70e0bd74 | 6040 | return ret; |
ee7b9f93 JB |
6041 | } |
6042 | ||
ea5b213a | 6043 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6044 | { |
4ef69c7a | 6045 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6046 | |
ea5b213a CW |
6047 | drm_encoder_cleanup(encoder); |
6048 | kfree(intel_encoder); | |
7e7d76c3 JB |
6049 | } |
6050 | ||
0a91ca29 DV |
6051 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6052 | * internal consistency). */ | |
749d98b8 ML |
6053 | static void intel_connector_verify_state(struct drm_crtc_state *crtc_state, |
6054 | struct drm_connector_state *conn_state) | |
79e53945 | 6055 | { |
749d98b8 | 6056 | struct intel_connector *connector = to_intel_connector(conn_state->connector); |
35dd3c64 ML |
6057 | |
6058 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6059 | connector->base.base.id, | |
6060 | connector->base.name); | |
6061 | ||
0a91ca29 | 6062 | if (connector->get_hw_state(connector)) { |
e85376cb | 6063 | struct intel_encoder *encoder = connector->encoder; |
0a91ca29 | 6064 | |
749d98b8 | 6065 | I915_STATE_WARN(!crtc_state, |
35dd3c64 | 6066 | "connector enabled without attached crtc\n"); |
0a91ca29 | 6067 | |
749d98b8 | 6068 | if (!crtc_state) |
35dd3c64 ML |
6069 | return; |
6070 | ||
749d98b8 | 6071 | I915_STATE_WARN(!crtc_state->active, |
35dd3c64 ML |
6072 | "connector is active, but attached crtc isn't\n"); |
6073 | ||
e85376cb | 6074 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
6075 | return; |
6076 | ||
e85376cb | 6077 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
6078 | "atomic encoder doesn't match attached encoder\n"); |
6079 | ||
e85376cb | 6080 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
6081 | "attached encoder crtc differs from connector crtc\n"); |
6082 | } else { | |
749d98b8 | 6083 | I915_STATE_WARN(crtc_state && crtc_state->active, |
4d688a2a | 6084 | "attached crtc is active, but connector isn't\n"); |
749d98b8 | 6085 | I915_STATE_WARN(!crtc_state && conn_state->best_encoder, |
35dd3c64 | 6086 | "best encoder set without crtc!\n"); |
0a91ca29 | 6087 | } |
79e53945 JB |
6088 | } |
6089 | ||
08d9bc92 ACO |
6090 | int intel_connector_init(struct intel_connector *connector) |
6091 | { | |
11c1a9ec | 6092 | struct intel_digital_connector_state *conn_state; |
08d9bc92 | 6093 | |
11c1a9ec ML |
6094 | /* |
6095 | * Allocate enough memory to hold intel_digital_connector_state, | |
6096 | * This might be a few bytes too many, but for connectors that don't | |
6097 | * need it we'll free the state and allocate a smaller one on the first | |
6098 | * succesful commit anyway. | |
6099 | */ | |
6100 | conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL); | |
6101 | if (!conn_state) | |
08d9bc92 ACO |
6102 | return -ENOMEM; |
6103 | ||
11c1a9ec ML |
6104 | __drm_atomic_helper_connector_reset(&connector->base, |
6105 | &conn_state->base); | |
6106 | ||
08d9bc92 ACO |
6107 | return 0; |
6108 | } | |
6109 | ||
6110 | struct intel_connector *intel_connector_alloc(void) | |
6111 | { | |
6112 | struct intel_connector *connector; | |
6113 | ||
6114 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6115 | if (!connector) | |
6116 | return NULL; | |
6117 | ||
6118 | if (intel_connector_init(connector) < 0) { | |
6119 | kfree(connector); | |
6120 | return NULL; | |
6121 | } | |
6122 | ||
6123 | return connector; | |
6124 | } | |
6125 | ||
f0947c37 DV |
6126 | /* Simple connector->get_hw_state implementation for encoders that support only |
6127 | * one connector and no cloning and hence the encoder state determines the state | |
6128 | * of the connector. */ | |
6129 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6130 | { |
24929352 | 6131 | enum pipe pipe = 0; |
f0947c37 | 6132 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6133 | |
f0947c37 | 6134 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6135 | } |
6136 | ||
6d293983 | 6137 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6138 | { |
6d293983 ACO |
6139 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6140 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6141 | |
6142 | return 0; | |
6143 | } | |
6144 | ||
6d293983 | 6145 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6146 | struct intel_crtc_state *pipe_config) |
1857e1da | 6147 | { |
8652744b | 6148 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d293983 ACO |
6149 | struct drm_atomic_state *state = pipe_config->base.state; |
6150 | struct intel_crtc *other_crtc; | |
6151 | struct intel_crtc_state *other_crtc_state; | |
6152 | ||
1857e1da DV |
6153 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6154 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6155 | if (pipe_config->fdi_lanes > 4) { | |
6156 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6157 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6158 | return -EINVAL; |
1857e1da DV |
6159 | } |
6160 | ||
8652744b | 6161 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
1857e1da DV |
6162 | if (pipe_config->fdi_lanes > 2) { |
6163 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6164 | pipe_config->fdi_lanes); | |
6d293983 | 6165 | return -EINVAL; |
1857e1da | 6166 | } else { |
6d293983 | 6167 | return 0; |
1857e1da DV |
6168 | } |
6169 | } | |
6170 | ||
b7f05d4a | 6171 | if (INTEL_INFO(dev_priv)->num_pipes == 2) |
6d293983 | 6172 | return 0; |
1857e1da DV |
6173 | |
6174 | /* Ivybridge 3 pipe is really complicated */ | |
6175 | switch (pipe) { | |
6176 | case PIPE_A: | |
6d293983 | 6177 | return 0; |
1857e1da | 6178 | case PIPE_B: |
6d293983 ACO |
6179 | if (pipe_config->fdi_lanes <= 2) |
6180 | return 0; | |
6181 | ||
b91eb5cc | 6182 | other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C); |
6d293983 ACO |
6183 | other_crtc_state = |
6184 | intel_atomic_get_crtc_state(state, other_crtc); | |
6185 | if (IS_ERR(other_crtc_state)) | |
6186 | return PTR_ERR(other_crtc_state); | |
6187 | ||
6188 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6189 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6190 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6191 | return -EINVAL; |
1857e1da | 6192 | } |
6d293983 | 6193 | return 0; |
1857e1da | 6194 | case PIPE_C: |
251cc67c VS |
6195 | if (pipe_config->fdi_lanes > 2) { |
6196 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6197 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6198 | return -EINVAL; |
251cc67c | 6199 | } |
6d293983 | 6200 | |
b91eb5cc | 6201 | other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B); |
6d293983 ACO |
6202 | other_crtc_state = |
6203 | intel_atomic_get_crtc_state(state, other_crtc); | |
6204 | if (IS_ERR(other_crtc_state)) | |
6205 | return PTR_ERR(other_crtc_state); | |
6206 | ||
6207 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6208 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6209 | return -EINVAL; |
1857e1da | 6210 | } |
6d293983 | 6211 | return 0; |
1857e1da DV |
6212 | default: |
6213 | BUG(); | |
6214 | } | |
6215 | } | |
6216 | ||
e29c22c0 DV |
6217 | #define RETRY 1 |
6218 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6219 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6220 | { |
1857e1da | 6221 | struct drm_device *dev = intel_crtc->base.dev; |
7c5f93b0 | 6222 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6223 | int lane, link_bw, fdi_dotclock, ret; |
6224 | bool needs_recompute = false; | |
877d48d5 | 6225 | |
e29c22c0 | 6226 | retry: |
877d48d5 DV |
6227 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6228 | * each output octet as 10 bits. The actual frequency | |
6229 | * is stored as a divider into a 100MHz clock, and the | |
6230 | * mode pixel clock is stored in units of 1KHz. | |
6231 | * Hence the bw of each lane in terms of the mode signal | |
6232 | * is: | |
6233 | */ | |
21a727b3 | 6234 | link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config); |
877d48d5 | 6235 | |
241bfc38 | 6236 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6237 | |
2bd89a07 | 6238 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6239 | pipe_config->pipe_bpp); |
6240 | ||
6241 | pipe_config->fdi_lanes = lane; | |
6242 | ||
2bd89a07 | 6243 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
b31e85ed | 6244 | link_bw, &pipe_config->fdi_m_n, false); |
1857e1da | 6245 | |
e3b247da | 6246 | ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); |
6d293983 | 6247 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { |
e29c22c0 | 6248 | pipe_config->pipe_bpp -= 2*3; |
7ff89ca2 VS |
6249 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", |
6250 | pipe_config->pipe_bpp); | |
6251 | needs_recompute = true; | |
6252 | pipe_config->bw_constrained = true; | |
257a7ffc | 6253 | |
7ff89ca2 | 6254 | goto retry; |
257a7ffc | 6255 | } |
79e53945 | 6256 | |
7ff89ca2 VS |
6257 | if (needs_recompute) |
6258 | return RETRY; | |
e70236a8 | 6259 | |
7ff89ca2 | 6260 | return ret; |
e70236a8 JB |
6261 | } |
6262 | ||
7ff89ca2 VS |
6263 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
6264 | struct intel_crtc_state *pipe_config) | |
e70236a8 | 6265 | { |
6e644626 VS |
6266 | if (pipe_config->ips_force_disable) |
6267 | return false; | |
6268 | ||
7ff89ca2 VS |
6269 | if (pipe_config->pipe_bpp > 24) |
6270 | return false; | |
e70236a8 | 6271 | |
7ff89ca2 VS |
6272 | /* HSW can handle pixel rate up to cdclk? */ |
6273 | if (IS_HASWELL(dev_priv)) | |
6274 | return true; | |
1b1d2716 | 6275 | |
65cd2b3f | 6276 | /* |
7ff89ca2 VS |
6277 | * We compare against max which means we must take |
6278 | * the increased cdclk requirement into account when | |
6279 | * calculating the new cdclk. | |
6280 | * | |
6281 | * Should measure whether using a lower cdclk w/o IPS | |
e70236a8 | 6282 | */ |
7ff89ca2 VS |
6283 | return pipe_config->pixel_rate <= |
6284 | dev_priv->max_cdclk_freq * 95 / 100; | |
e70236a8 | 6285 | } |
79e53945 | 6286 | |
7ff89ca2 VS |
6287 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
6288 | struct intel_crtc_state *pipe_config) | |
6289 | { | |
6290 | struct drm_device *dev = crtc->base.dev; | |
6291 | struct drm_i915_private *dev_priv = to_i915(dev); | |
34edce2f | 6292 | |
7ff89ca2 VS |
6293 | pipe_config->ips_enabled = i915.enable_ips && |
6294 | hsw_crtc_supports_ips(crtc) && | |
6295 | pipe_config_supports_ips(dev_priv, pipe_config); | |
34edce2f VS |
6296 | } |
6297 | ||
7ff89ca2 | 6298 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
34edce2f | 6299 | { |
7ff89ca2 | 6300 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
34edce2f | 6301 | |
7ff89ca2 VS |
6302 | /* GDG double wide on either pipe, otherwise pipe A only */ |
6303 | return INTEL_INFO(dev_priv)->gen < 4 && | |
6304 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); | |
34edce2f VS |
6305 | } |
6306 | ||
ceb99320 VS |
6307 | static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config) |
6308 | { | |
6309 | uint32_t pixel_rate; | |
6310 | ||
6311 | pixel_rate = pipe_config->base.adjusted_mode.crtc_clock; | |
6312 | ||
6313 | /* | |
6314 | * We only use IF-ID interlacing. If we ever use | |
6315 | * PF-ID we'll need to adjust the pixel_rate here. | |
6316 | */ | |
6317 | ||
6318 | if (pipe_config->pch_pfit.enabled) { | |
6319 | uint64_t pipe_w, pipe_h, pfit_w, pfit_h; | |
6320 | uint32_t pfit_size = pipe_config->pch_pfit.size; | |
6321 | ||
6322 | pipe_w = pipe_config->pipe_src_w; | |
6323 | pipe_h = pipe_config->pipe_src_h; | |
6324 | ||
6325 | pfit_w = (pfit_size >> 16) & 0xFFFF; | |
6326 | pfit_h = pfit_size & 0xFFFF; | |
6327 | if (pipe_w < pfit_w) | |
6328 | pipe_w = pfit_w; | |
6329 | if (pipe_h < pfit_h) | |
6330 | pipe_h = pfit_h; | |
6331 | ||
6332 | if (WARN_ON(!pfit_w || !pfit_h)) | |
6333 | return pixel_rate; | |
6334 | ||
6335 | pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h, | |
6336 | pfit_w * pfit_h); | |
6337 | } | |
6338 | ||
6339 | return pixel_rate; | |
6340 | } | |
6341 | ||
7ff89ca2 | 6342 | static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) |
34edce2f | 6343 | { |
7ff89ca2 | 6344 | struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); |
34edce2f | 6345 | |
7ff89ca2 VS |
6346 | if (HAS_GMCH_DISPLAY(dev_priv)) |
6347 | /* FIXME calculate proper pipe pixel rate for GMCH pfit */ | |
6348 | crtc_state->pixel_rate = | |
6349 | crtc_state->base.adjusted_mode.crtc_clock; | |
6350 | else | |
6351 | crtc_state->pixel_rate = | |
6352 | ilk_pipe_pixel_rate(crtc_state); | |
6353 | } | |
34edce2f | 6354 | |
7ff89ca2 VS |
6355 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
6356 | struct intel_crtc_state *pipe_config) | |
6357 | { | |
6358 | struct drm_device *dev = crtc->base.dev; | |
6359 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6360 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; | |
6361 | int clock_limit = dev_priv->max_dotclk_freq; | |
34edce2f | 6362 | |
7ff89ca2 VS |
6363 | if (INTEL_GEN(dev_priv) < 4) { |
6364 | clock_limit = dev_priv->max_cdclk_freq * 9 / 10; | |
34edce2f | 6365 | |
7ff89ca2 VS |
6366 | /* |
6367 | * Enable double wide mode when the dot clock | |
6368 | * is > 90% of the (display) core speed. | |
6369 | */ | |
6370 | if (intel_crtc_supports_double_wide(crtc) && | |
6371 | adjusted_mode->crtc_clock > clock_limit) { | |
6372 | clock_limit = dev_priv->max_dotclk_freq; | |
6373 | pipe_config->double_wide = true; | |
6374 | } | |
34edce2f VS |
6375 | } |
6376 | ||
7ff89ca2 VS |
6377 | if (adjusted_mode->crtc_clock > clock_limit) { |
6378 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
6379 | adjusted_mode->crtc_clock, clock_limit, | |
6380 | yesno(pipe_config->double_wide)); | |
6381 | return -EINVAL; | |
6382 | } | |
34edce2f | 6383 | |
25edf915 SS |
6384 | if (pipe_config->ycbcr420 && pipe_config->base.ctm) { |
6385 | /* | |
6386 | * There is only one pipe CSC unit per pipe, and we need that | |
6387 | * for output conversion from RGB->YCBCR. So if CTM is already | |
6388 | * applied we can't support YCBCR420 output. | |
6389 | */ | |
6390 | DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n"); | |
6391 | return -EINVAL; | |
6392 | } | |
6393 | ||
7ff89ca2 VS |
6394 | /* |
6395 | * Pipe horizontal size must be even in: | |
6396 | * - DVO ganged mode | |
6397 | * - LVDS dual channel mode | |
6398 | * - Double wide pipe | |
6399 | */ | |
6400 | if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) && | |
6401 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) | |
6402 | pipe_config->pipe_src_w &= ~1; | |
34edce2f | 6403 | |
7ff89ca2 VS |
6404 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6405 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
6406 | */ | |
6407 | if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) && | |
6408 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) | |
6409 | return -EINVAL; | |
34edce2f | 6410 | |
7ff89ca2 | 6411 | intel_crtc_compute_pixel_rate(pipe_config); |
34edce2f | 6412 | |
7ff89ca2 VS |
6413 | if (HAS_IPS(dev_priv)) |
6414 | hsw_compute_ips_config(crtc, pipe_config); | |
34edce2f | 6415 | |
7ff89ca2 VS |
6416 | if (pipe_config->has_pch_encoder) |
6417 | return ironlake_fdi_compute_config(crtc, pipe_config); | |
34edce2f | 6418 | |
7ff89ca2 | 6419 | return 0; |
34edce2f VS |
6420 | } |
6421 | ||
2c07245f | 6422 | static void |
a65851af | 6423 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 6424 | { |
a65851af VS |
6425 | while (*num > DATA_LINK_M_N_MASK || |
6426 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
6427 | *num >>= 1; |
6428 | *den >>= 1; | |
6429 | } | |
6430 | } | |
6431 | ||
a65851af | 6432 | static void compute_m_n(unsigned int m, unsigned int n, |
b31e85ed JN |
6433 | uint32_t *ret_m, uint32_t *ret_n, |
6434 | bool reduce_m_n) | |
a65851af | 6435 | { |
9a86cda0 JN |
6436 | /* |
6437 | * Reduce M/N as much as possible without loss in precision. Several DP | |
6438 | * dongles in particular seem to be fussy about too large *link* M/N | |
6439 | * values. The passed in values are more likely to have the least | |
6440 | * significant bits zero than M after rounding below, so do this first. | |
6441 | */ | |
b31e85ed JN |
6442 | if (reduce_m_n) { |
6443 | while ((m & 1) == 0 && (n & 1) == 0) { | |
6444 | m >>= 1; | |
6445 | n >>= 1; | |
6446 | } | |
9a86cda0 JN |
6447 | } |
6448 | ||
a65851af VS |
6449 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); |
6450 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
6451 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
6452 | } | |
6453 | ||
e69d0bc1 DV |
6454 | void |
6455 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
6456 | int pixel_clock, int link_clock, | |
b31e85ed JN |
6457 | struct intel_link_m_n *m_n, |
6458 | bool reduce_m_n) | |
2c07245f | 6459 | { |
e69d0bc1 | 6460 | m_n->tu = 64; |
a65851af VS |
6461 | |
6462 | compute_m_n(bits_per_pixel * pixel_clock, | |
6463 | link_clock * nlanes * 8, | |
b31e85ed JN |
6464 | &m_n->gmch_m, &m_n->gmch_n, |
6465 | reduce_m_n); | |
a65851af VS |
6466 | |
6467 | compute_m_n(pixel_clock, link_clock, | |
b31e85ed JN |
6468 | &m_n->link_m, &m_n->link_n, |
6469 | reduce_m_n); | |
2c07245f ZW |
6470 | } |
6471 | ||
a7615030 CW |
6472 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
6473 | { | |
d330a953 JN |
6474 | if (i915.panel_use_ssc >= 0) |
6475 | return i915.panel_use_ssc != 0; | |
41aa3448 | 6476 | return dev_priv->vbt.lvds_use_ssc |
435793df | 6477 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
6478 | } |
6479 | ||
7429e9d4 | 6480 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 6481 | { |
7df00d7a | 6482 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 6483 | } |
f47709a9 | 6484 | |
7429e9d4 DV |
6485 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
6486 | { | |
6487 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
6488 | } |
6489 | ||
f47709a9 | 6490 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 6491 | struct intel_crtc_state *crtc_state, |
9e2c8475 | 6492 | struct dpll *reduced_clock) |
a7516a05 | 6493 | { |
9b1e14f4 | 6494 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
a7516a05 JB |
6495 | u32 fp, fp2 = 0; |
6496 | ||
9b1e14f4 | 6497 | if (IS_PINEVIEW(dev_priv)) { |
190f68c5 | 6498 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 6499 | if (reduced_clock) |
7429e9d4 | 6500 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 6501 | } else { |
190f68c5 | 6502 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 6503 | if (reduced_clock) |
7429e9d4 | 6504 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
6505 | } |
6506 | ||
190f68c5 | 6507 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 6508 | |
f47709a9 | 6509 | crtc->lowfreq_avail = false; |
2d84d2b3 | 6510 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 6511 | reduced_clock) { |
190f68c5 | 6512 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 6513 | crtc->lowfreq_avail = true; |
a7516a05 | 6514 | } else { |
190f68c5 | 6515 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
6516 | } |
6517 | } | |
6518 | ||
5e69f97f CML |
6519 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
6520 | pipe) | |
89b667f8 JB |
6521 | { |
6522 | u32 reg_val; | |
6523 | ||
6524 | /* | |
6525 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
6526 | * and set it to a reasonable value instead. | |
6527 | */ | |
ab3c759a | 6528 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
6529 | reg_val &= 0xffffff00; |
6530 | reg_val |= 0x00000030; | |
ab3c759a | 6531 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 6532 | |
ab3c759a | 6533 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
ed58570f ID |
6534 | reg_val &= 0x00ffffff; |
6535 | reg_val |= 0x8c000000; | |
ab3c759a | 6536 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 6537 | |
ab3c759a | 6538 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 6539 | reg_val &= 0xffffff00; |
ab3c759a | 6540 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 6541 | |
ab3c759a | 6542 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
6543 | reg_val &= 0x00ffffff; |
6544 | reg_val |= 0xb0000000; | |
ab3c759a | 6545 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
6546 | } |
6547 | ||
b551842d DV |
6548 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
6549 | struct intel_link_m_n *m_n) | |
6550 | { | |
6551 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6552 | struct drm_i915_private *dev_priv = to_i915(dev); |
b551842d DV |
6553 | int pipe = crtc->pipe; |
6554 | ||
e3b95f1e DV |
6555 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6556 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
6557 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
6558 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
6559 | } |
6560 | ||
6561 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
6562 | struct intel_link_m_n *m_n, |
6563 | struct intel_link_m_n *m2_n2) | |
b551842d | 6564 | { |
6315b5d3 | 6565 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
b551842d | 6566 | int pipe = crtc->pipe; |
6e3c9717 | 6567 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d | 6568 | |
6315b5d3 | 6569 | if (INTEL_GEN(dev_priv) >= 5) { |
b551842d DV |
6570 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6571 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
6572 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
6573 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
6574 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
6575 | * for gen < 8) and if DRRS is supported (to make sure the | |
6576 | * registers are not unnecessarily accessed). | |
6577 | */ | |
920a14b2 TU |
6578 | if (m2_n2 && (IS_CHERRYVIEW(dev_priv) || |
6579 | INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) { | |
f769cd24 VK |
6580 | I915_WRITE(PIPE_DATA_M2(transcoder), |
6581 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
6582 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
6583 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
6584 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
6585 | } | |
b551842d | 6586 | } else { |
e3b95f1e DV |
6587 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6588 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
6589 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
6590 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
6591 | } |
6592 | } | |
6593 | ||
fe3cd48d | 6594 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 6595 | { |
fe3cd48d R |
6596 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
6597 | ||
6598 | if (m_n == M1_N1) { | |
6599 | dp_m_n = &crtc->config->dp_m_n; | |
6600 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
6601 | } else if (m_n == M2_N2) { | |
6602 | ||
6603 | /* | |
6604 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
6605 | * needs to be programmed into M1_N1. | |
6606 | */ | |
6607 | dp_m_n = &crtc->config->dp_m2_n2; | |
6608 | } else { | |
6609 | DRM_ERROR("Unsupported divider value\n"); | |
6610 | return; | |
6611 | } | |
6612 | ||
6e3c9717 ACO |
6613 | if (crtc->config->has_pch_encoder) |
6614 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 6615 | else |
fe3cd48d | 6616 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
6617 | } |
6618 | ||
251ac862 DV |
6619 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
6620 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 | 6621 | { |
03ed5cbf | 6622 | pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | |
cd2d34d9 | 6623 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
6624 | if (crtc->pipe != PIPE_A) |
6625 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
bdd4b6a6 | 6626 | |
cd2d34d9 | 6627 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 6628 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
6629 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | |
6630 | DPLL_EXT_BUFFER_ENABLE_VLV; | |
6631 | ||
03ed5cbf VS |
6632 | pipe_config->dpll_hw_state.dpll_md = |
6633 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
6634 | } | |
bdd4b6a6 | 6635 | |
03ed5cbf VS |
6636 | static void chv_compute_dpll(struct intel_crtc *crtc, |
6637 | struct intel_crtc_state *pipe_config) | |
6638 | { | |
6639 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | | |
cd2d34d9 | 6640 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
6641 | if (crtc->pipe != PIPE_A) |
6642 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
6643 | ||
cd2d34d9 | 6644 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 6645 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
6646 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; |
6647 | ||
03ed5cbf VS |
6648 | pipe_config->dpll_hw_state.dpll_md = |
6649 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
bdd4b6a6 DV |
6650 | } |
6651 | ||
d288f65f | 6652 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 6653 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 6654 | { |
f47709a9 | 6655 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 6656 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 6657 | enum pipe pipe = crtc->pipe; |
bdd4b6a6 | 6658 | u32 mdiv; |
a0c4da24 | 6659 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 6660 | u32 coreclk, reg_val; |
a0c4da24 | 6661 | |
cd2d34d9 VS |
6662 | /* Enable Refclk */ |
6663 | I915_WRITE(DPLL(pipe), | |
6664 | pipe_config->dpll_hw_state.dpll & | |
6665 | ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); | |
6666 | ||
6667 | /* No need to actually set up the DPLL with DSI */ | |
6668 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
6669 | return; | |
6670 | ||
a580516d | 6671 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 6672 | |
d288f65f VS |
6673 | bestn = pipe_config->dpll.n; |
6674 | bestm1 = pipe_config->dpll.m1; | |
6675 | bestm2 = pipe_config->dpll.m2; | |
6676 | bestp1 = pipe_config->dpll.p1; | |
6677 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 6678 | |
89b667f8 JB |
6679 | /* See eDP HDMI DPIO driver vbios notes doc */ |
6680 | ||
6681 | /* PLL B needs special handling */ | |
bdd4b6a6 | 6682 | if (pipe == PIPE_B) |
5e69f97f | 6683 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
6684 | |
6685 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 6686 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
6687 | |
6688 | /* Disable target IRef on PLL */ | |
ab3c759a | 6689 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 6690 | reg_val &= 0x00ffffff; |
ab3c759a | 6691 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
6692 | |
6693 | /* Disable fast lock */ | |
ab3c759a | 6694 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
6695 | |
6696 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
6697 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
6698 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
6699 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 6700 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
6701 | |
6702 | /* | |
6703 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
6704 | * but we don't support that). | |
6705 | * Note: don't use the DAC post divider as it seems unstable. | |
6706 | */ | |
6707 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 6708 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6709 | |
a0c4da24 | 6710 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 6711 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6712 | |
89b667f8 | 6713 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 6714 | if (pipe_config->port_clock == 162000 || |
2d84d2b3 VS |
6715 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) || |
6716 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 6717 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 6718 | 0x009f0003); |
89b667f8 | 6719 | else |
ab3c759a | 6720 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
6721 | 0x00d0000f); |
6722 | ||
37a5650b | 6723 | if (intel_crtc_has_dp_encoder(pipe_config)) { |
89b667f8 | 6724 | /* Use SSC source */ |
bdd4b6a6 | 6725 | if (pipe == PIPE_A) |
ab3c759a | 6726 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6727 | 0x0df40000); |
6728 | else | |
ab3c759a | 6729 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6730 | 0x0df70000); |
6731 | } else { /* HDMI or VGA */ | |
6732 | /* Use bend source */ | |
bdd4b6a6 | 6733 | if (pipe == PIPE_A) |
ab3c759a | 6734 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6735 | 0x0df70000); |
6736 | else | |
ab3c759a | 6737 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6738 | 0x0df40000); |
6739 | } | |
a0c4da24 | 6740 | |
ab3c759a | 6741 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 6742 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
2210ce7f | 6743 | if (intel_crtc_has_dp_encoder(crtc->config)) |
89b667f8 | 6744 | coreclk |= 0x01000000; |
ab3c759a | 6745 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 6746 | |
ab3c759a | 6747 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 6748 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
6749 | } |
6750 | ||
d288f65f | 6751 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 6752 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
6753 | { |
6754 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6755 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 6756 | enum pipe pipe = crtc->pipe; |
9d556c99 | 6757 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9cbe40c1 | 6758 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 6759 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 6760 | u32 dpio_val; |
9cbe40c1 | 6761 | int vco; |
9d556c99 | 6762 | |
cd2d34d9 VS |
6763 | /* Enable Refclk and SSC */ |
6764 | I915_WRITE(DPLL(pipe), | |
6765 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); | |
6766 | ||
6767 | /* No need to actually set up the DPLL with DSI */ | |
6768 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
6769 | return; | |
6770 | ||
d288f65f VS |
6771 | bestn = pipe_config->dpll.n; |
6772 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
6773 | bestm1 = pipe_config->dpll.m1; | |
6774 | bestm2 = pipe_config->dpll.m2 >> 22; | |
6775 | bestp1 = pipe_config->dpll.p1; | |
6776 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 6777 | vco = pipe_config->dpll.vco; |
a945ce7e | 6778 | dpio_val = 0; |
9cbe40c1 | 6779 | loopfilter = 0; |
9d556c99 | 6780 | |
a580516d | 6781 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 6782 | |
9d556c99 CML |
6783 | /* p1 and p2 divider */ |
6784 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
6785 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
6786 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
6787 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
6788 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
6789 | ||
6790 | /* Feedback post-divider - m2 */ | |
6791 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
6792 | ||
6793 | /* Feedback refclk divider - n and m1 */ | |
6794 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
6795 | DPIO_CHV_M1_DIV_BY_2 | | |
6796 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
6797 | ||
6798 | /* M2 fraction division */ | |
25a25dfc | 6799 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
6800 | |
6801 | /* M2 fraction division enable */ | |
a945ce7e VP |
6802 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
6803 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
6804 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
6805 | if (bestm2_frac) | |
6806 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
6807 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 6808 | |
de3a0fde VP |
6809 | /* Program digital lock detect threshold */ |
6810 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
6811 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
6812 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
6813 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
6814 | if (!bestm2_frac) | |
6815 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
6816 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
6817 | ||
9d556c99 | 6818 | /* Loop filter */ |
9cbe40c1 VP |
6819 | if (vco == 5400000) { |
6820 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6821 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
6822 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6823 | tribuf_calcntr = 0x9; | |
6824 | } else if (vco <= 6200000) { | |
6825 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6826 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
6827 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6828 | tribuf_calcntr = 0x9; | |
6829 | } else if (vco <= 6480000) { | |
6830 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6831 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
6832 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6833 | tribuf_calcntr = 0x8; | |
6834 | } else { | |
6835 | /* Not supported. Apply the same limits as in the max case */ | |
6836 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6837 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
6838 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6839 | tribuf_calcntr = 0; | |
6840 | } | |
9d556c99 CML |
6841 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
6842 | ||
968040b2 | 6843 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
6844 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
6845 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
6846 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
6847 | ||
9d556c99 CML |
6848 | /* AFC Recal */ |
6849 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
6850 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
6851 | DPIO_AFC_RECAL); | |
6852 | ||
a580516d | 6853 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
6854 | } |
6855 | ||
d288f65f VS |
6856 | /** |
6857 | * vlv_force_pll_on - forcibly enable just the PLL | |
6858 | * @dev_priv: i915 private structure | |
6859 | * @pipe: pipe PLL to enable | |
6860 | * @dpll: PLL configuration | |
6861 | * | |
6862 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
6863 | * in cases where we need the PLL enabled even when @pipe is not going to | |
6864 | * be enabled. | |
6865 | */ | |
30ad9814 | 6866 | int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, |
3f36b937 | 6867 | const struct dpll *dpll) |
d288f65f | 6868 | { |
b91eb5cc | 6869 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
3f36b937 TU |
6870 | struct intel_crtc_state *pipe_config; |
6871 | ||
6872 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); | |
6873 | if (!pipe_config) | |
6874 | return -ENOMEM; | |
6875 | ||
6876 | pipe_config->base.crtc = &crtc->base; | |
6877 | pipe_config->pixel_multiplier = 1; | |
6878 | pipe_config->dpll = *dpll; | |
d288f65f | 6879 | |
30ad9814 | 6880 | if (IS_CHERRYVIEW(dev_priv)) { |
3f36b937 TU |
6881 | chv_compute_dpll(crtc, pipe_config); |
6882 | chv_prepare_pll(crtc, pipe_config); | |
6883 | chv_enable_pll(crtc, pipe_config); | |
d288f65f | 6884 | } else { |
3f36b937 TU |
6885 | vlv_compute_dpll(crtc, pipe_config); |
6886 | vlv_prepare_pll(crtc, pipe_config); | |
6887 | vlv_enable_pll(crtc, pipe_config); | |
d288f65f | 6888 | } |
3f36b937 TU |
6889 | |
6890 | kfree(pipe_config); | |
6891 | ||
6892 | return 0; | |
d288f65f VS |
6893 | } |
6894 | ||
6895 | /** | |
6896 | * vlv_force_pll_off - forcibly disable just the PLL | |
6897 | * @dev_priv: i915 private structure | |
6898 | * @pipe: pipe PLL to disable | |
6899 | * | |
6900 | * Disable the PLL for @pipe. To be used in cases where we need | |
6901 | * the PLL enabled even when @pipe is not going to be enabled. | |
6902 | */ | |
30ad9814 | 6903 | void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe) |
d288f65f | 6904 | { |
30ad9814 VS |
6905 | if (IS_CHERRYVIEW(dev_priv)) |
6906 | chv_disable_pll(dev_priv, pipe); | |
d288f65f | 6907 | else |
30ad9814 | 6908 | vlv_disable_pll(dev_priv, pipe); |
d288f65f VS |
6909 | } |
6910 | ||
251ac862 DV |
6911 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
6912 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 6913 | struct dpll *reduced_clock) |
eb1cbe48 | 6914 | { |
9b1e14f4 | 6915 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
eb1cbe48 | 6916 | u32 dpll; |
190f68c5 | 6917 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 6918 | |
190f68c5 | 6919 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 6920 | |
eb1cbe48 DV |
6921 | dpll = DPLL_VGA_MODE_DIS; |
6922 | ||
2d84d2b3 | 6923 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
6924 | dpll |= DPLLB_MODE_LVDS; |
6925 | else | |
6926 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 6927 | |
73f67aa8 JN |
6928 | if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || |
6929 | IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { | |
190f68c5 | 6930 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 6931 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 6932 | } |
198a037f | 6933 | |
3d6e9ee0 VS |
6934 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
6935 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 6936 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 6937 | |
37a5650b | 6938 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 6939 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
6940 | |
6941 | /* compute bitmask from p1 value */ | |
9b1e14f4 | 6942 | if (IS_PINEVIEW(dev_priv)) |
eb1cbe48 DV |
6943 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; |
6944 | else { | |
6945 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
9beb5fea | 6946 | if (IS_G4X(dev_priv) && reduced_clock) |
eb1cbe48 DV |
6947 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
6948 | } | |
6949 | switch (clock->p2) { | |
6950 | case 5: | |
6951 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
6952 | break; | |
6953 | case 7: | |
6954 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
6955 | break; | |
6956 | case 10: | |
6957 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
6958 | break; | |
6959 | case 14: | |
6960 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
6961 | break; | |
6962 | } | |
9b1e14f4 | 6963 | if (INTEL_GEN(dev_priv) >= 4) |
eb1cbe48 DV |
6964 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
6965 | ||
190f68c5 | 6966 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 6967 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
2d84d2b3 | 6968 | else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 6969 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
6970 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
6971 | else | |
6972 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6973 | ||
6974 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 6975 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 6976 | |
9b1e14f4 | 6977 | if (INTEL_GEN(dev_priv) >= 4) { |
190f68c5 | 6978 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 6979 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 6980 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
6981 | } |
6982 | } | |
6983 | ||
251ac862 DV |
6984 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
6985 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 6986 | struct dpll *reduced_clock) |
eb1cbe48 | 6987 | { |
f47709a9 | 6988 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 6989 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb1cbe48 | 6990 | u32 dpll; |
190f68c5 | 6991 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 6992 | |
190f68c5 | 6993 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 6994 | |
eb1cbe48 DV |
6995 | dpll = DPLL_VGA_MODE_DIS; |
6996 | ||
2d84d2b3 | 6997 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
6998 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
6999 | } else { | |
7000 | if (clock->p1 == 2) | |
7001 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
7002 | else | |
7003 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7004 | if (clock->p2 == 4) | |
7005 | dpll |= PLL_P2_DIVIDE_BY_4; | |
7006 | } | |
7007 | ||
50a0bc90 TU |
7008 | if (!IS_I830(dev_priv) && |
7009 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) | |
4a33e48d DV |
7010 | dpll |= DPLL_DVO_2X_MODE; |
7011 | ||
2d84d2b3 | 7012 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 7013 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
7014 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
7015 | else | |
7016 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7017 | ||
7018 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7019 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
7020 | } |
7021 | ||
8a654f3b | 7022 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c | 7023 | { |
6315b5d3 | 7024 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
b0e77b9c | 7025 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 7026 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
7c5f93b0 | 7027 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
7028 | uint32_t crtc_vtotal, crtc_vblank_end; |
7029 | int vsyncshift = 0; | |
4d8a62ea DV |
7030 | |
7031 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
7032 | * the hw state checker will get angry at the mismatch. */ | |
7033 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
7034 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 7035 | |
609aeaca | 7036 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 7037 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
7038 | crtc_vtotal -= 1; |
7039 | crtc_vblank_end -= 1; | |
609aeaca | 7040 | |
2d84d2b3 | 7041 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
7042 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
7043 | else | |
7044 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
7045 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
7046 | if (vsyncshift < 0) |
7047 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
7048 | } |
7049 | ||
6315b5d3 | 7050 | if (INTEL_GEN(dev_priv) > 3) |
fe2b8f9d | 7051 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 7052 | |
fe2b8f9d | 7053 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
7054 | (adjusted_mode->crtc_hdisplay - 1) | |
7055 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 7056 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
7057 | (adjusted_mode->crtc_hblank_start - 1) | |
7058 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 7059 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
7060 | (adjusted_mode->crtc_hsync_start - 1) | |
7061 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
7062 | ||
fe2b8f9d | 7063 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 7064 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 7065 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 7066 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 7067 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 7068 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 7069 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
7070 | (adjusted_mode->crtc_vsync_start - 1) | |
7071 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
7072 | ||
b5e508d4 PZ |
7073 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
7074 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
7075 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
7076 | * bits. */ | |
772c2a51 | 7077 | if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && |
b5e508d4 PZ |
7078 | (pipe == PIPE_B || pipe == PIPE_C)) |
7079 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
7080 | ||
bc58be60 JN |
7081 | } |
7082 | ||
7083 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc) | |
7084 | { | |
7085 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 7086 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 JN |
7087 | enum pipe pipe = intel_crtc->pipe; |
7088 | ||
b0e77b9c PZ |
7089 | /* pipesrc controls the size that is scaled from, which should |
7090 | * always be the user's requested size. | |
7091 | */ | |
7092 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
7093 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
7094 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
7095 | } |
7096 | ||
1bd1bd80 | 7097 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 7098 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
7099 | { |
7100 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7101 | struct drm_i915_private *dev_priv = to_i915(dev); |
1bd1bd80 DV |
7102 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
7103 | uint32_t tmp; | |
7104 | ||
7105 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7106 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
7107 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7108 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
7109 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
7110 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7111 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
7112 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
7113 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7114 | |
7115 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7116 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
7117 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7118 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
7119 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
7120 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7121 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
7122 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
7123 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7124 | |
7125 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
7126 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
7127 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
7128 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 | 7129 | } |
bc58be60 JN |
7130 | } |
7131 | ||
7132 | static void intel_get_pipe_src_size(struct intel_crtc *crtc, | |
7133 | struct intel_crtc_state *pipe_config) | |
7134 | { | |
7135 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7136 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 | 7137 | u32 tmp; |
1bd1bd80 DV |
7138 | |
7139 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
7140 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
7141 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
7142 | ||
2d112de7 ACO |
7143 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
7144 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
7145 | } |
7146 | ||
f6a83288 | 7147 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 7148 | struct intel_crtc_state *pipe_config) |
babea61d | 7149 | { |
2d112de7 ACO |
7150 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
7151 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
7152 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
7153 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 7154 | |
2d112de7 ACO |
7155 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
7156 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
7157 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7158 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 7159 | |
2d112de7 | 7160 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 7161 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 7162 | |
2d112de7 | 7163 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
cd13f5ab ML |
7164 | |
7165 | mode->hsync = drm_mode_hsync(mode); | |
7166 | mode->vrefresh = drm_mode_vrefresh(mode); | |
7167 | drm_mode_set_name(mode); | |
babea61d JB |
7168 | } |
7169 | ||
84b046f3 DV |
7170 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7171 | { | |
6315b5d3 | 7172 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
84b046f3 DV |
7173 | uint32_t pipeconf; |
7174 | ||
9f11a9e4 | 7175 | pipeconf = 0; |
84b046f3 | 7176 | |
e56134bc VS |
7177 | /* we keep both pipes enabled on 830 */ |
7178 | if (IS_I830(dev_priv)) | |
b6b5d049 | 7179 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; |
67c72a12 | 7180 | |
6e3c9717 | 7181 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7182 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7183 | |
ff9ce46e | 7184 | /* only g4x and later have fancy bpc/dither controls */ |
9beb5fea TU |
7185 | if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
7186 | IS_CHERRYVIEW(dev_priv)) { | |
ff9ce46e | 7187 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 7188 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 7189 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 7190 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 7191 | |
6e3c9717 | 7192 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
7193 | case 18: |
7194 | pipeconf |= PIPECONF_6BPC; | |
7195 | break; | |
7196 | case 24: | |
7197 | pipeconf |= PIPECONF_8BPC; | |
7198 | break; | |
7199 | case 30: | |
7200 | pipeconf |= PIPECONF_10BPC; | |
7201 | break; | |
7202 | default: | |
7203 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7204 | BUG(); | |
84b046f3 DV |
7205 | } |
7206 | } | |
7207 | ||
56b857a5 | 7208 | if (HAS_PIPE_CXSR(dev_priv)) { |
84b046f3 DV |
7209 | if (intel_crtc->lowfreq_avail) { |
7210 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
7211 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
7212 | } else { | |
7213 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
7214 | } |
7215 | } | |
7216 | ||
6e3c9717 | 7217 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
6315b5d3 | 7218 | if (INTEL_GEN(dev_priv) < 4 || |
2d84d2b3 | 7219 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
7220 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
7221 | else | |
7222 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7223 | } else | |
84b046f3 DV |
7224 | pipeconf |= PIPECONF_PROGRESSIVE; |
7225 | ||
920a14b2 | 7226 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
666a4537 | 7227 | intel_crtc->config->limited_color_range) |
9f11a9e4 | 7228 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 7229 | |
84b046f3 DV |
7230 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7231 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7232 | } | |
7233 | ||
81c97f52 ACO |
7234 | static int i8xx_crtc_compute_clock(struct intel_crtc *crtc, |
7235 | struct intel_crtc_state *crtc_state) | |
7236 | { | |
7237 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7238 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7239 | const struct intel_limit *limit; |
81c97f52 ACO |
7240 | int refclk = 48000; |
7241 | ||
7242 | memset(&crtc_state->dpll_hw_state, 0, | |
7243 | sizeof(crtc_state->dpll_hw_state)); | |
7244 | ||
2d84d2b3 | 7245 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
81c97f52 ACO |
7246 | if (intel_panel_use_ssc(dev_priv)) { |
7247 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7248 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7249 | } | |
7250 | ||
7251 | limit = &intel_limits_i8xx_lvds; | |
2d84d2b3 | 7252 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) { |
81c97f52 ACO |
7253 | limit = &intel_limits_i8xx_dvo; |
7254 | } else { | |
7255 | limit = &intel_limits_i8xx_dac; | |
7256 | } | |
7257 | ||
7258 | if (!crtc_state->clock_set && | |
7259 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7260 | refclk, NULL, &crtc_state->dpll)) { | |
7261 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7262 | return -EINVAL; | |
7263 | } | |
7264 | ||
7265 | i8xx_compute_dpll(crtc, crtc_state, NULL); | |
7266 | ||
7267 | return 0; | |
7268 | } | |
7269 | ||
19ec6693 ACO |
7270 | static int g4x_crtc_compute_clock(struct intel_crtc *crtc, |
7271 | struct intel_crtc_state *crtc_state) | |
7272 | { | |
7273 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7274 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7275 | const struct intel_limit *limit; |
19ec6693 ACO |
7276 | int refclk = 96000; |
7277 | ||
7278 | memset(&crtc_state->dpll_hw_state, 0, | |
7279 | sizeof(crtc_state->dpll_hw_state)); | |
7280 | ||
2d84d2b3 | 7281 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
19ec6693 ACO |
7282 | if (intel_panel_use_ssc(dev_priv)) { |
7283 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7284 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7285 | } | |
7286 | ||
7287 | if (intel_is_dual_link_lvds(dev)) | |
7288 | limit = &intel_limits_g4x_dual_channel_lvds; | |
7289 | else | |
7290 | limit = &intel_limits_g4x_single_channel_lvds; | |
2d84d2b3 VS |
7291 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) || |
7292 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
19ec6693 | 7293 | limit = &intel_limits_g4x_hdmi; |
2d84d2b3 | 7294 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
19ec6693 ACO |
7295 | limit = &intel_limits_g4x_sdvo; |
7296 | } else { | |
7297 | /* The option is for other outputs */ | |
7298 | limit = &intel_limits_i9xx_sdvo; | |
7299 | } | |
7300 | ||
7301 | if (!crtc_state->clock_set && | |
7302 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7303 | refclk, NULL, &crtc_state->dpll)) { | |
7304 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7305 | return -EINVAL; | |
7306 | } | |
7307 | ||
7308 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
7309 | ||
7310 | return 0; | |
7311 | } | |
7312 | ||
70e8aa21 ACO |
7313 | static int pnv_crtc_compute_clock(struct intel_crtc *crtc, |
7314 | struct intel_crtc_state *crtc_state) | |
7315 | { | |
7316 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7317 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7318 | const struct intel_limit *limit; |
70e8aa21 ACO |
7319 | int refclk = 96000; |
7320 | ||
7321 | memset(&crtc_state->dpll_hw_state, 0, | |
7322 | sizeof(crtc_state->dpll_hw_state)); | |
7323 | ||
2d84d2b3 | 7324 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
7325 | if (intel_panel_use_ssc(dev_priv)) { |
7326 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7327 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7328 | } | |
7329 | ||
7330 | limit = &intel_limits_pineview_lvds; | |
7331 | } else { | |
7332 | limit = &intel_limits_pineview_sdvo; | |
7333 | } | |
7334 | ||
7335 | if (!crtc_state->clock_set && | |
7336 | !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7337 | refclk, NULL, &crtc_state->dpll)) { | |
7338 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7339 | return -EINVAL; | |
7340 | } | |
7341 | ||
7342 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
7343 | ||
7344 | return 0; | |
7345 | } | |
7346 | ||
190f68c5 ACO |
7347 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
7348 | struct intel_crtc_state *crtc_state) | |
79e53945 | 7349 | { |
c7653199 | 7350 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7351 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7352 | const struct intel_limit *limit; |
81c97f52 | 7353 | int refclk = 96000; |
79e53945 | 7354 | |
dd3cd74a ACO |
7355 | memset(&crtc_state->dpll_hw_state, 0, |
7356 | sizeof(crtc_state->dpll_hw_state)); | |
7357 | ||
2d84d2b3 | 7358 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
7359 | if (intel_panel_use_ssc(dev_priv)) { |
7360 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7361 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7362 | } | |
43565a06 | 7363 | |
70e8aa21 ACO |
7364 | limit = &intel_limits_i9xx_lvds; |
7365 | } else { | |
7366 | limit = &intel_limits_i9xx_sdvo; | |
81c97f52 | 7367 | } |
79e53945 | 7368 | |
70e8aa21 ACO |
7369 | if (!crtc_state->clock_set && |
7370 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7371 | refclk, NULL, &crtc_state->dpll)) { | |
7372 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7373 | return -EINVAL; | |
f47709a9 | 7374 | } |
7026d4ac | 7375 | |
81c97f52 | 7376 | i9xx_compute_dpll(crtc, crtc_state, NULL); |
79e53945 | 7377 | |
c8f7a0db | 7378 | return 0; |
f564048e EA |
7379 | } |
7380 | ||
65b3d6a9 ACO |
7381 | static int chv_crtc_compute_clock(struct intel_crtc *crtc, |
7382 | struct intel_crtc_state *crtc_state) | |
7383 | { | |
7384 | int refclk = 100000; | |
1b6f4958 | 7385 | const struct intel_limit *limit = &intel_limits_chv; |
65b3d6a9 ACO |
7386 | |
7387 | memset(&crtc_state->dpll_hw_state, 0, | |
7388 | sizeof(crtc_state->dpll_hw_state)); | |
7389 | ||
65b3d6a9 ACO |
7390 | if (!crtc_state->clock_set && |
7391 | !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7392 | refclk, NULL, &crtc_state->dpll)) { | |
7393 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7394 | return -EINVAL; | |
7395 | } | |
7396 | ||
7397 | chv_compute_dpll(crtc, crtc_state); | |
7398 | ||
7399 | return 0; | |
7400 | } | |
7401 | ||
7402 | static int vlv_crtc_compute_clock(struct intel_crtc *crtc, | |
7403 | struct intel_crtc_state *crtc_state) | |
7404 | { | |
7405 | int refclk = 100000; | |
1b6f4958 | 7406 | const struct intel_limit *limit = &intel_limits_vlv; |
65b3d6a9 ACO |
7407 | |
7408 | memset(&crtc_state->dpll_hw_state, 0, | |
7409 | sizeof(crtc_state->dpll_hw_state)); | |
7410 | ||
65b3d6a9 ACO |
7411 | if (!crtc_state->clock_set && |
7412 | !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7413 | refclk, NULL, &crtc_state->dpll)) { | |
7414 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7415 | return -EINVAL; | |
7416 | } | |
7417 | ||
7418 | vlv_compute_dpll(crtc, crtc_state); | |
7419 | ||
7420 | return 0; | |
7421 | } | |
7422 | ||
2fa2fe9a | 7423 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 7424 | struct intel_crtc_state *pipe_config) |
2fa2fe9a | 7425 | { |
6315b5d3 | 7426 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
2fa2fe9a DV |
7427 | uint32_t tmp; |
7428 | ||
50a0bc90 TU |
7429 | if (INTEL_GEN(dev_priv) <= 3 && |
7430 | (IS_I830(dev_priv) || !IS_MOBILE(dev_priv))) | |
dc9e7dec VS |
7431 | return; |
7432 | ||
2fa2fe9a | 7433 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
7434 | if (!(tmp & PFIT_ENABLE)) |
7435 | return; | |
2fa2fe9a | 7436 | |
06922821 | 7437 | /* Check whether the pfit is attached to our pipe. */ |
6315b5d3 | 7438 | if (INTEL_GEN(dev_priv) < 4) { |
2fa2fe9a DV |
7439 | if (crtc->pipe != PIPE_B) |
7440 | return; | |
2fa2fe9a DV |
7441 | } else { |
7442 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
7443 | return; | |
7444 | } | |
7445 | ||
06922821 | 7446 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a | 7447 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
2fa2fe9a DV |
7448 | } |
7449 | ||
acbec814 | 7450 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7451 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
7452 | { |
7453 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7454 | struct drm_i915_private *dev_priv = to_i915(dev); |
acbec814 | 7455 | int pipe = pipe_config->cpu_transcoder; |
9e2c8475 | 7456 | struct dpll clock; |
acbec814 | 7457 | u32 mdiv; |
662c6ecb | 7458 | int refclk = 100000; |
acbec814 | 7459 | |
b521973b VS |
7460 | /* In case of DSI, DPLL will not be used */ |
7461 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
f573de5a SK |
7462 | return; |
7463 | ||
a580516d | 7464 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 7465 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 7466 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
7467 | |
7468 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
7469 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
7470 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
7471 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
7472 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
7473 | ||
dccbea3b | 7474 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
7475 | } |
7476 | ||
5724dbd1 DL |
7477 | static void |
7478 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
7479 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
7480 | { |
7481 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7482 | struct drm_i915_private *dev_priv = to_i915(dev); |
1ad292b5 JB |
7483 | u32 val, base, offset; |
7484 | int pipe = crtc->pipe, plane = crtc->plane; | |
7485 | int fourcc, pixel_format; | |
6761dd31 | 7486 | unsigned int aligned_height; |
b113d5ee | 7487 | struct drm_framebuffer *fb; |
1b842c89 | 7488 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 7489 | |
42a7b088 DL |
7490 | val = I915_READ(DSPCNTR(plane)); |
7491 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
7492 | return; | |
7493 | ||
d9806c9f | 7494 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 7495 | if (!intel_fb) { |
1ad292b5 JB |
7496 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7497 | return; | |
7498 | } | |
7499 | ||
1b842c89 DL |
7500 | fb = &intel_fb->base; |
7501 | ||
d2e9f5fc VS |
7502 | fb->dev = dev; |
7503 | ||
6315b5d3 | 7504 | if (INTEL_GEN(dev_priv) >= 4) { |
18c5247e | 7505 | if (val & DISPPLANE_TILED) { |
49af449b | 7506 | plane_config->tiling = I915_TILING_X; |
bae781b2 | 7507 | fb->modifier = I915_FORMAT_MOD_X_TILED; |
18c5247e DV |
7508 | } |
7509 | } | |
1ad292b5 JB |
7510 | |
7511 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 7512 | fourcc = i9xx_format_to_fourcc(pixel_format); |
2f3f4763 | 7513 | fb->format = drm_format_info(fourcc); |
1ad292b5 | 7514 | |
6315b5d3 | 7515 | if (INTEL_GEN(dev_priv) >= 4) { |
49af449b | 7516 | if (plane_config->tiling) |
1ad292b5 JB |
7517 | offset = I915_READ(DSPTILEOFF(plane)); |
7518 | else | |
7519 | offset = I915_READ(DSPLINOFF(plane)); | |
7520 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
7521 | } else { | |
7522 | base = I915_READ(DSPADDR(plane)); | |
7523 | } | |
7524 | plane_config->base = base; | |
7525 | ||
7526 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
7527 | fb->width = ((val >> 16) & 0xfff) + 1; |
7528 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
7529 | |
7530 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 7531 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 7532 | |
d88c4afd | 7533 | aligned_height = intel_fb_align_height(fb, 0, fb->height); |
1ad292b5 | 7534 | |
f37b5c2b | 7535 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 7536 | |
2844a921 DL |
7537 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
7538 | pipe_name(pipe), plane, fb->width, fb->height, | |
272725c7 | 7539 | fb->format->cpp[0] * 8, base, fb->pitches[0], |
2844a921 | 7540 | plane_config->size); |
1ad292b5 | 7541 | |
2d14030b | 7542 | plane_config->fb = intel_fb; |
1ad292b5 JB |
7543 | } |
7544 | ||
70b23a98 | 7545 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7546 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
7547 | { |
7548 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7549 | struct drm_i915_private *dev_priv = to_i915(dev); |
70b23a98 VS |
7550 | int pipe = pipe_config->cpu_transcoder; |
7551 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9e2c8475 | 7552 | struct dpll clock; |
0d7b6b11 | 7553 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
7554 | int refclk = 100000; |
7555 | ||
b521973b VS |
7556 | /* In case of DSI, DPLL will not be used */ |
7557 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
7558 | return; | |
7559 | ||
a580516d | 7560 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
7561 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
7562 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
7563 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
7564 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 7565 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 7566 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
7567 | |
7568 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
7569 | clock.m2 = (pll_dw0 & 0xff) << 22; |
7570 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
7571 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
7572 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
7573 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
7574 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
7575 | ||
dccbea3b | 7576 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
7577 | } |
7578 | ||
0e8ffe1b | 7579 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 7580 | struct intel_crtc_state *pipe_config) |
0e8ffe1b | 7581 | { |
6315b5d3 | 7582 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1729050e | 7583 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 7584 | uint32_t tmp; |
1729050e | 7585 | bool ret; |
0e8ffe1b | 7586 | |
1729050e ID |
7587 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
7588 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 ID |
7589 | return false; |
7590 | ||
e143a21c | 7591 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 7592 | pipe_config->shared_dpll = NULL; |
eccb140b | 7593 | |
1729050e ID |
7594 | ret = false; |
7595 | ||
0e8ffe1b DV |
7596 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
7597 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 7598 | goto out; |
0e8ffe1b | 7599 | |
9beb5fea TU |
7600 | if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
7601 | IS_CHERRYVIEW(dev_priv)) { | |
42571aef VS |
7602 | switch (tmp & PIPECONF_BPC_MASK) { |
7603 | case PIPECONF_6BPC: | |
7604 | pipe_config->pipe_bpp = 18; | |
7605 | break; | |
7606 | case PIPECONF_8BPC: | |
7607 | pipe_config->pipe_bpp = 24; | |
7608 | break; | |
7609 | case PIPECONF_10BPC: | |
7610 | pipe_config->pipe_bpp = 30; | |
7611 | break; | |
7612 | default: | |
7613 | break; | |
7614 | } | |
7615 | } | |
7616 | ||
920a14b2 | 7617 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
666a4537 | 7618 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
b5a9fa09 DV |
7619 | pipe_config->limited_color_range = true; |
7620 | ||
6315b5d3 | 7621 | if (INTEL_GEN(dev_priv) < 4) |
282740f7 VS |
7622 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; |
7623 | ||
1bd1bd80 | 7624 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 7625 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 7626 | |
2fa2fe9a DV |
7627 | i9xx_get_pfit_config(crtc, pipe_config); |
7628 | ||
6315b5d3 | 7629 | if (INTEL_GEN(dev_priv) >= 4) { |
c231775c | 7630 | /* No way to read it out on pipes B and C */ |
920a14b2 | 7631 | if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) |
c231775c VS |
7632 | tmp = dev_priv->chv_dpll_md[crtc->pipe]; |
7633 | else | |
7634 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
6c49f241 DV |
7635 | pipe_config->pixel_multiplier = |
7636 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
7637 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 7638 | pipe_config->dpll_hw_state.dpll_md = tmp; |
50a0bc90 | 7639 | } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || |
73f67aa8 | 7640 | IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { |
6c49f241 DV |
7641 | tmp = I915_READ(DPLL(crtc->pipe)); |
7642 | pipe_config->pixel_multiplier = | |
7643 | ((tmp & SDVO_MULTIPLIER_MASK) | |
7644 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
7645 | } else { | |
7646 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
7647 | * port and will be fixed up in the encoder->get_config | |
7648 | * function. */ | |
7649 | pipe_config->pixel_multiplier = 1; | |
7650 | } | |
8bcc2795 | 7651 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
920a14b2 | 7652 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { |
1c4e0274 VS |
7653 | /* |
7654 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
7655 | * on 830. Filter it out here so that we don't | |
7656 | * report errors due to that. | |
7657 | */ | |
50a0bc90 | 7658 | if (IS_I830(dev_priv)) |
1c4e0274 VS |
7659 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; |
7660 | ||
8bcc2795 DV |
7661 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
7662 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
7663 | } else { |
7664 | /* Mask out read-only status bits. */ | |
7665 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
7666 | DPLL_PORTC_READY_MASK | | |
7667 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 7668 | } |
6c49f241 | 7669 | |
920a14b2 | 7670 | if (IS_CHERRYVIEW(dev_priv)) |
70b23a98 | 7671 | chv_crtc_clock_get(crtc, pipe_config); |
11a914c2 | 7672 | else if (IS_VALLEYVIEW(dev_priv)) |
acbec814 JB |
7673 | vlv_crtc_clock_get(crtc, pipe_config); |
7674 | else | |
7675 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 7676 | |
0f64614d VS |
7677 | /* |
7678 | * Normally the dotclock is filled in by the encoder .get_config() | |
7679 | * but in case the pipe is enabled w/o any ports we need a sane | |
7680 | * default. | |
7681 | */ | |
7682 | pipe_config->base.adjusted_mode.crtc_clock = | |
7683 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
7684 | ||
1729050e ID |
7685 | ret = true; |
7686 | ||
7687 | out: | |
7688 | intel_display_power_put(dev_priv, power_domain); | |
7689 | ||
7690 | return ret; | |
0e8ffe1b DV |
7691 | } |
7692 | ||
c39055b0 | 7693 | static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv) |
13d83a67 | 7694 | { |
13d83a67 | 7695 | struct intel_encoder *encoder; |
1c1a24d2 | 7696 | int i; |
74cfd7ac | 7697 | u32 val, final; |
13d83a67 | 7698 | bool has_lvds = false; |
199e5d79 | 7699 | bool has_cpu_edp = false; |
199e5d79 | 7700 | bool has_panel = false; |
99eb6a01 KP |
7701 | bool has_ck505 = false; |
7702 | bool can_ssc = false; | |
1c1a24d2 | 7703 | bool using_ssc_source = false; |
13d83a67 JB |
7704 | |
7705 | /* We need to take the global config into account */ | |
c39055b0 | 7706 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
199e5d79 KP |
7707 | switch (encoder->type) { |
7708 | case INTEL_OUTPUT_LVDS: | |
7709 | has_panel = true; | |
7710 | has_lvds = true; | |
7711 | break; | |
7712 | case INTEL_OUTPUT_EDP: | |
7713 | has_panel = true; | |
2de6905f | 7714 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
7715 | has_cpu_edp = true; |
7716 | break; | |
6847d71b PZ |
7717 | default: |
7718 | break; | |
13d83a67 JB |
7719 | } |
7720 | } | |
7721 | ||
6e266956 | 7722 | if (HAS_PCH_IBX(dev_priv)) { |
41aa3448 | 7723 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
7724 | can_ssc = has_ck505; |
7725 | } else { | |
7726 | has_ck505 = false; | |
7727 | can_ssc = true; | |
7728 | } | |
7729 | ||
1c1a24d2 L |
7730 | /* Check if any DPLLs are using the SSC source */ |
7731 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
7732 | u32 temp = I915_READ(PCH_DPLL(i)); | |
7733 | ||
7734 | if (!(temp & DPLL_VCO_ENABLE)) | |
7735 | continue; | |
7736 | ||
7737 | if ((temp & PLL_REF_INPUT_MASK) == | |
7738 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
7739 | using_ssc_source = true; | |
7740 | break; | |
7741 | } | |
7742 | } | |
7743 | ||
7744 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n", | |
7745 | has_panel, has_lvds, has_ck505, using_ssc_source); | |
13d83a67 JB |
7746 | |
7747 | /* Ironlake: try to setup display ref clock before DPLL | |
7748 | * enabling. This is only under driver's control after | |
7749 | * PCH B stepping, previous chipset stepping should be | |
7750 | * ignoring this setting. | |
7751 | */ | |
74cfd7ac CW |
7752 | val = I915_READ(PCH_DREF_CONTROL); |
7753 | ||
7754 | /* As we must carefully and slowly disable/enable each source in turn, | |
7755 | * compute the final state we want first and check if we need to | |
7756 | * make any changes at all. | |
7757 | */ | |
7758 | final = val; | |
7759 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
7760 | if (has_ck505) | |
7761 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
7762 | else | |
7763 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
7764 | ||
8c07eb68 | 7765 | final &= ~DREF_SSC_SOURCE_MASK; |
74cfd7ac | 7766 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
8c07eb68 | 7767 | final &= ~DREF_SSC1_ENABLE; |
74cfd7ac CW |
7768 | |
7769 | if (has_panel) { | |
7770 | final |= DREF_SSC_SOURCE_ENABLE; | |
7771 | ||
7772 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
7773 | final |= DREF_SSC1_ENABLE; | |
7774 | ||
7775 | if (has_cpu_edp) { | |
7776 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
7777 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
7778 | else | |
7779 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
7780 | } else | |
7781 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
1c1a24d2 L |
7782 | } else if (using_ssc_source) { |
7783 | final |= DREF_SSC_SOURCE_ENABLE; | |
7784 | final |= DREF_SSC1_ENABLE; | |
74cfd7ac CW |
7785 | } |
7786 | ||
7787 | if (final == val) | |
7788 | return; | |
7789 | ||
13d83a67 | 7790 | /* Always enable nonspread source */ |
74cfd7ac | 7791 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 7792 | |
99eb6a01 | 7793 | if (has_ck505) |
74cfd7ac | 7794 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 7795 | else |
74cfd7ac | 7796 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 7797 | |
199e5d79 | 7798 | if (has_panel) { |
74cfd7ac CW |
7799 | val &= ~DREF_SSC_SOURCE_MASK; |
7800 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 7801 | |
199e5d79 | 7802 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 7803 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 7804 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 7805 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 7806 | } else |
74cfd7ac | 7807 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
7808 | |
7809 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 7810 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7811 | POSTING_READ(PCH_DREF_CONTROL); |
7812 | udelay(200); | |
7813 | ||
74cfd7ac | 7814 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
7815 | |
7816 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 7817 | if (has_cpu_edp) { |
99eb6a01 | 7818 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 7819 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 7820 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 7821 | } else |
74cfd7ac | 7822 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 7823 | } else |
74cfd7ac | 7824 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7825 | |
74cfd7ac | 7826 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7827 | POSTING_READ(PCH_DREF_CONTROL); |
7828 | udelay(200); | |
7829 | } else { | |
1c1a24d2 | 7830 | DRM_DEBUG_KMS("Disabling CPU source output\n"); |
199e5d79 | 7831 | |
74cfd7ac | 7832 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
7833 | |
7834 | /* Turn off CPU output */ | |
74cfd7ac | 7835 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7836 | |
74cfd7ac | 7837 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7838 | POSTING_READ(PCH_DREF_CONTROL); |
7839 | udelay(200); | |
7840 | ||
1c1a24d2 L |
7841 | if (!using_ssc_source) { |
7842 | DRM_DEBUG_KMS("Disabling SSC source\n"); | |
199e5d79 | 7843 | |
1c1a24d2 L |
7844 | /* Turn off the SSC source */ |
7845 | val &= ~DREF_SSC_SOURCE_MASK; | |
7846 | val |= DREF_SSC_SOURCE_DISABLE; | |
f165d283 | 7847 | |
1c1a24d2 L |
7848 | /* Turn off SSC1 */ |
7849 | val &= ~DREF_SSC1_ENABLE; | |
7850 | ||
7851 | I915_WRITE(PCH_DREF_CONTROL, val); | |
7852 | POSTING_READ(PCH_DREF_CONTROL); | |
7853 | udelay(200); | |
7854 | } | |
13d83a67 | 7855 | } |
74cfd7ac CW |
7856 | |
7857 | BUG_ON(val != final); | |
13d83a67 JB |
7858 | } |
7859 | ||
f31f2d55 | 7860 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 7861 | { |
f31f2d55 | 7862 | uint32_t tmp; |
dde86e2d | 7863 | |
0ff066a9 PZ |
7864 | tmp = I915_READ(SOUTH_CHICKEN2); |
7865 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
7866 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7867 | |
cf3598c2 ID |
7868 | if (wait_for_us(I915_READ(SOUTH_CHICKEN2) & |
7869 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
0ff066a9 | 7870 | DRM_ERROR("FDI mPHY reset assert timeout\n"); |
dde86e2d | 7871 | |
0ff066a9 PZ |
7872 | tmp = I915_READ(SOUTH_CHICKEN2); |
7873 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
7874 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7875 | |
cf3598c2 ID |
7876 | if (wait_for_us((I915_READ(SOUTH_CHICKEN2) & |
7877 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
0ff066a9 | 7878 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); |
f31f2d55 PZ |
7879 | } |
7880 | ||
7881 | /* WaMPhyProgramming:hsw */ | |
7882 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
7883 | { | |
7884 | uint32_t tmp; | |
dde86e2d PZ |
7885 | |
7886 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
7887 | tmp &= ~(0xFF << 24); | |
7888 | tmp |= (0x12 << 24); | |
7889 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
7890 | ||
dde86e2d PZ |
7891 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
7892 | tmp |= (1 << 11); | |
7893 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
7894 | ||
7895 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
7896 | tmp |= (1 << 11); | |
7897 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
7898 | ||
dde86e2d PZ |
7899 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
7900 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7901 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
7902 | ||
7903 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
7904 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7905 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
7906 | ||
0ff066a9 PZ |
7907 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
7908 | tmp &= ~(7 << 13); | |
7909 | tmp |= (5 << 13); | |
7910 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 7911 | |
0ff066a9 PZ |
7912 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
7913 | tmp &= ~(7 << 13); | |
7914 | tmp |= (5 << 13); | |
7915 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
7916 | |
7917 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
7918 | tmp &= ~0xFF; | |
7919 | tmp |= 0x1C; | |
7920 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
7921 | ||
7922 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
7923 | tmp &= ~0xFF; | |
7924 | tmp |= 0x1C; | |
7925 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
7926 | ||
7927 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
7928 | tmp &= ~(0xFF << 16); | |
7929 | tmp |= (0x1C << 16); | |
7930 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
7931 | ||
7932 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
7933 | tmp &= ~(0xFF << 16); | |
7934 | tmp |= (0x1C << 16); | |
7935 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
7936 | ||
0ff066a9 PZ |
7937 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
7938 | tmp |= (1 << 27); | |
7939 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 7940 | |
0ff066a9 PZ |
7941 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
7942 | tmp |= (1 << 27); | |
7943 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 7944 | |
0ff066a9 PZ |
7945 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
7946 | tmp &= ~(0xF << 28); | |
7947 | tmp |= (4 << 28); | |
7948 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 7949 | |
0ff066a9 PZ |
7950 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
7951 | tmp &= ~(0xF << 28); | |
7952 | tmp |= (4 << 28); | |
7953 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
7954 | } |
7955 | ||
2fa86a1f PZ |
7956 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
7957 | * Programming" based on the parameters passed: | |
7958 | * - Sequence to enable CLKOUT_DP | |
7959 | * - Sequence to enable CLKOUT_DP without spread | |
7960 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
7961 | */ | |
c39055b0 ACO |
7962 | static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv, |
7963 | bool with_spread, bool with_fdi) | |
f31f2d55 | 7964 | { |
2fa86a1f PZ |
7965 | uint32_t reg, tmp; |
7966 | ||
7967 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
7968 | with_spread = true; | |
4f8036a2 TU |
7969 | if (WARN(HAS_PCH_LPT_LP(dev_priv) && |
7970 | with_fdi, "LP PCH doesn't have FDI\n")) | |
2fa86a1f | 7971 | with_fdi = false; |
f31f2d55 | 7972 | |
a580516d | 7973 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
7974 | |
7975 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7976 | tmp &= ~SBI_SSCCTL_DISABLE; | |
7977 | tmp |= SBI_SSCCTL_PATHALT; | |
7978 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7979 | ||
7980 | udelay(24); | |
7981 | ||
2fa86a1f PZ |
7982 | if (with_spread) { |
7983 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7984 | tmp &= ~SBI_SSCCTL_PATHALT; | |
7985 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 7986 | |
2fa86a1f PZ |
7987 | if (with_fdi) { |
7988 | lpt_reset_fdi_mphy(dev_priv); | |
7989 | lpt_program_fdi_mphy(dev_priv); | |
7990 | } | |
7991 | } | |
dde86e2d | 7992 | |
4f8036a2 | 7993 | reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
7994 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
7995 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
7996 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 7997 | |
a580516d | 7998 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
7999 | } |
8000 | ||
47701c3b | 8001 | /* Sequence to disable CLKOUT_DP */ |
c39055b0 | 8002 | static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv) |
47701c3b | 8003 | { |
47701c3b PZ |
8004 | uint32_t reg, tmp; |
8005 | ||
a580516d | 8006 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 8007 | |
4f8036a2 | 8008 | reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
8009 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8010 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8011 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
8012 | ||
8013 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8014 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
8015 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
8016 | tmp |= SBI_SSCCTL_PATHALT; | |
8017 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8018 | udelay(32); | |
8019 | } | |
8020 | tmp |= SBI_SSCCTL_DISABLE; | |
8021 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8022 | } | |
8023 | ||
a580516d | 8024 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
8025 | } |
8026 | ||
f7be2c21 VS |
8027 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
8028 | ||
8029 | static const uint16_t sscdivintphase[] = { | |
8030 | [BEND_IDX( 50)] = 0x3B23, | |
8031 | [BEND_IDX( 45)] = 0x3B23, | |
8032 | [BEND_IDX( 40)] = 0x3C23, | |
8033 | [BEND_IDX( 35)] = 0x3C23, | |
8034 | [BEND_IDX( 30)] = 0x3D23, | |
8035 | [BEND_IDX( 25)] = 0x3D23, | |
8036 | [BEND_IDX( 20)] = 0x3E23, | |
8037 | [BEND_IDX( 15)] = 0x3E23, | |
8038 | [BEND_IDX( 10)] = 0x3F23, | |
8039 | [BEND_IDX( 5)] = 0x3F23, | |
8040 | [BEND_IDX( 0)] = 0x0025, | |
8041 | [BEND_IDX( -5)] = 0x0025, | |
8042 | [BEND_IDX(-10)] = 0x0125, | |
8043 | [BEND_IDX(-15)] = 0x0125, | |
8044 | [BEND_IDX(-20)] = 0x0225, | |
8045 | [BEND_IDX(-25)] = 0x0225, | |
8046 | [BEND_IDX(-30)] = 0x0325, | |
8047 | [BEND_IDX(-35)] = 0x0325, | |
8048 | [BEND_IDX(-40)] = 0x0425, | |
8049 | [BEND_IDX(-45)] = 0x0425, | |
8050 | [BEND_IDX(-50)] = 0x0525, | |
8051 | }; | |
8052 | ||
8053 | /* | |
8054 | * Bend CLKOUT_DP | |
8055 | * steps -50 to 50 inclusive, in steps of 5 | |
8056 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) | |
8057 | * change in clock period = -(steps / 10) * 5.787 ps | |
8058 | */ | |
8059 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) | |
8060 | { | |
8061 | uint32_t tmp; | |
8062 | int idx = BEND_IDX(steps); | |
8063 | ||
8064 | if (WARN_ON(steps % 5 != 0)) | |
8065 | return; | |
8066 | ||
8067 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) | |
8068 | return; | |
8069 | ||
8070 | mutex_lock(&dev_priv->sb_lock); | |
8071 | ||
8072 | if (steps % 10 != 0) | |
8073 | tmp = 0xAAAAAAAB; | |
8074 | else | |
8075 | tmp = 0x00000000; | |
8076 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); | |
8077 | ||
8078 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); | |
8079 | tmp &= 0xffff0000; | |
8080 | tmp |= sscdivintphase[idx]; | |
8081 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); | |
8082 | ||
8083 | mutex_unlock(&dev_priv->sb_lock); | |
8084 | } | |
8085 | ||
8086 | #undef BEND_IDX | |
8087 | ||
c39055b0 | 8088 | static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv) |
bf8fa3d3 | 8089 | { |
bf8fa3d3 PZ |
8090 | struct intel_encoder *encoder; |
8091 | bool has_vga = false; | |
8092 | ||
c39055b0 | 8093 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
bf8fa3d3 PZ |
8094 | switch (encoder->type) { |
8095 | case INTEL_OUTPUT_ANALOG: | |
8096 | has_vga = true; | |
8097 | break; | |
6847d71b PZ |
8098 | default: |
8099 | break; | |
bf8fa3d3 PZ |
8100 | } |
8101 | } | |
8102 | ||
f7be2c21 | 8103 | if (has_vga) { |
c39055b0 ACO |
8104 | lpt_bend_clkout_dp(dev_priv, 0); |
8105 | lpt_enable_clkout_dp(dev_priv, true, true); | |
f7be2c21 | 8106 | } else { |
c39055b0 | 8107 | lpt_disable_clkout_dp(dev_priv); |
f7be2c21 | 8108 | } |
bf8fa3d3 PZ |
8109 | } |
8110 | ||
dde86e2d PZ |
8111 | /* |
8112 | * Initialize reference clocks when the driver loads | |
8113 | */ | |
c39055b0 | 8114 | void intel_init_pch_refclk(struct drm_i915_private *dev_priv) |
dde86e2d | 8115 | { |
6e266956 | 8116 | if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) |
c39055b0 | 8117 | ironlake_init_pch_refclk(dev_priv); |
6e266956 | 8118 | else if (HAS_PCH_LPT(dev_priv)) |
c39055b0 | 8119 | lpt_init_pch_refclk(dev_priv); |
dde86e2d PZ |
8120 | } |
8121 | ||
6ff93609 | 8122 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 8123 | { |
fac5e23e | 8124 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
79e53945 JB |
8125 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8126 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
8127 | uint32_t val; |
8128 | ||
78114071 | 8129 | val = 0; |
c8203565 | 8130 | |
6e3c9717 | 8131 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 8132 | case 18: |
dfd07d72 | 8133 | val |= PIPECONF_6BPC; |
c8203565 PZ |
8134 | break; |
8135 | case 24: | |
dfd07d72 | 8136 | val |= PIPECONF_8BPC; |
c8203565 PZ |
8137 | break; |
8138 | case 30: | |
dfd07d72 | 8139 | val |= PIPECONF_10BPC; |
c8203565 PZ |
8140 | break; |
8141 | case 36: | |
dfd07d72 | 8142 | val |= PIPECONF_12BPC; |
c8203565 PZ |
8143 | break; |
8144 | default: | |
cc769b62 PZ |
8145 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
8146 | BUG(); | |
c8203565 PZ |
8147 | } |
8148 | ||
6e3c9717 | 8149 | if (intel_crtc->config->dither) |
c8203565 PZ |
8150 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8151 | ||
6e3c9717 | 8152 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
8153 | val |= PIPECONF_INTERLACED_ILK; |
8154 | else | |
8155 | val |= PIPECONF_PROGRESSIVE; | |
8156 | ||
6e3c9717 | 8157 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 8158 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 8159 | |
c8203565 PZ |
8160 | I915_WRITE(PIPECONF(pipe), val); |
8161 | POSTING_READ(PIPECONF(pipe)); | |
8162 | } | |
8163 | ||
6ff93609 | 8164 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8165 | { |
fac5e23e | 8166 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
ee2b0b38 | 8167 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 8168 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
391bf048 | 8169 | u32 val = 0; |
ee2b0b38 | 8170 | |
391bf048 | 8171 | if (IS_HASWELL(dev_priv) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8172 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8173 | ||
6e3c9717 | 8174 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8175 | val |= PIPECONF_INTERLACED_ILK; |
8176 | else | |
8177 | val |= PIPECONF_PROGRESSIVE; | |
8178 | ||
702e7a56 PZ |
8179 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8180 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
391bf048 JN |
8181 | } |
8182 | ||
391bf048 JN |
8183 | static void haswell_set_pipemisc(struct drm_crtc *crtc) |
8184 | { | |
fac5e23e | 8185 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
391bf048 | 8186 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
b22ca995 | 8187 | struct intel_crtc_state *config = intel_crtc->config; |
756f85cf | 8188 | |
391bf048 JN |
8189 | if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) { |
8190 | u32 val = 0; | |
756f85cf | 8191 | |
6e3c9717 | 8192 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8193 | case 18: |
8194 | val |= PIPEMISC_DITHER_6_BPC; | |
8195 | break; | |
8196 | case 24: | |
8197 | val |= PIPEMISC_DITHER_8_BPC; | |
8198 | break; | |
8199 | case 30: | |
8200 | val |= PIPEMISC_DITHER_10_BPC; | |
8201 | break; | |
8202 | case 36: | |
8203 | val |= PIPEMISC_DITHER_12_BPC; | |
8204 | break; | |
8205 | default: | |
8206 | /* Case prevented by pipe_config_set_bpp. */ | |
8207 | BUG(); | |
8208 | } | |
8209 | ||
6e3c9717 | 8210 | if (intel_crtc->config->dither) |
756f85cf PZ |
8211 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8212 | ||
b22ca995 SS |
8213 | if (config->ycbcr420) { |
8214 | val |= PIPEMISC_OUTPUT_COLORSPACE_YUV | | |
8215 | PIPEMISC_YUV420_ENABLE | | |
8216 | PIPEMISC_YUV420_MODE_FULL_BLEND; | |
8217 | } | |
8218 | ||
391bf048 | 8219 | I915_WRITE(PIPEMISC(intel_crtc->pipe), val); |
756f85cf | 8220 | } |
ee2b0b38 PZ |
8221 | } |
8222 | ||
d4b1931c PZ |
8223 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
8224 | { | |
8225 | /* | |
8226 | * Account for spread spectrum to avoid | |
8227 | * oversubscribing the link. Max center spread | |
8228 | * is 2.5%; use 5% for safety's sake. | |
8229 | */ | |
8230 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 8231 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
8232 | } |
8233 | ||
7429e9d4 | 8234 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 8235 | { |
7429e9d4 | 8236 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
8237 | } |
8238 | ||
b75ca6f6 ACO |
8239 | static void ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
8240 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 8241 | struct dpll *reduced_clock) |
79e53945 | 8242 | { |
de13a2e3 | 8243 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 | 8244 | struct drm_device *dev = crtc->dev; |
fac5e23e | 8245 | struct drm_i915_private *dev_priv = to_i915(dev); |
b75ca6f6 | 8246 | u32 dpll, fp, fp2; |
3d6e9ee0 | 8247 | int factor; |
79e53945 | 8248 | |
c1858123 | 8249 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 | 8250 | factor = 21; |
3d6e9ee0 | 8251 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
8febb297 | 8252 | if ((intel_panel_use_ssc(dev_priv) && |
e91e941b | 8253 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
6e266956 | 8254 | (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev))) |
8febb297 | 8255 | factor = 25; |
190f68c5 | 8256 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 8257 | factor = 20; |
c1858123 | 8258 | |
b75ca6f6 ACO |
8259 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
8260 | ||
190f68c5 | 8261 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
b75ca6f6 ACO |
8262 | fp |= FP_CB_TUNE; |
8263 | ||
8264 | if (reduced_clock) { | |
8265 | fp2 = i9xx_dpll_compute_fp(reduced_clock); | |
2c07245f | 8266 | |
b75ca6f6 ACO |
8267 | if (reduced_clock->m < factor * reduced_clock->n) |
8268 | fp2 |= FP_CB_TUNE; | |
8269 | } else { | |
8270 | fp2 = fp; | |
8271 | } | |
9a7c7890 | 8272 | |
5eddb70b | 8273 | dpll = 0; |
2c07245f | 8274 | |
3d6e9ee0 | 8275 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a07d6787 EA |
8276 | dpll |= DPLLB_MODE_LVDS; |
8277 | else | |
8278 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 8279 | |
190f68c5 | 8280 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8281 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f | 8282 | |
3d6e9ee0 VS |
8283 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
8284 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 8285 | dpll |= DPLL_SDVO_HIGH_SPEED; |
3d6e9ee0 | 8286 | |
37a5650b | 8287 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 8288 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 8289 | |
7d7f8633 VS |
8290 | /* |
8291 | * The high speed IO clock is only really required for | |
8292 | * SDVO/HDMI/DP, but we also enable it for CRT to make it | |
8293 | * possible to share the DPLL between CRT and HDMI. Enabling | |
8294 | * the clock needlessly does no real harm, except use up a | |
8295 | * bit of power potentially. | |
8296 | * | |
8297 | * We'll limit this to IVB with 3 pipes, since it has only two | |
8298 | * DPLLs and so DPLL sharing is the only way to get three pipes | |
8299 | * driving PCH ports at the same time. On SNB we could do this, | |
8300 | * and potentially avoid enabling the second DPLL, but it's not | |
8301 | * clear if it''s a win or loss power wise. No point in doing | |
8302 | * this on ILK at all since it has a fixed DPLL<->pipe mapping. | |
8303 | */ | |
8304 | if (INTEL_INFO(dev_priv)->num_pipes == 3 && | |
8305 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) | |
8306 | dpll |= DPLL_SDVO_HIGH_SPEED; | |
8307 | ||
a07d6787 | 8308 | /* compute bitmask from p1 value */ |
190f68c5 | 8309 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 8310 | /* also FPA1 */ |
190f68c5 | 8311 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 8312 | |
190f68c5 | 8313 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
8314 | case 5: |
8315 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8316 | break; | |
8317 | case 7: | |
8318 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8319 | break; | |
8320 | case 10: | |
8321 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8322 | break; | |
8323 | case 14: | |
8324 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8325 | break; | |
79e53945 JB |
8326 | } |
8327 | ||
3d6e9ee0 VS |
8328 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
8329 | intel_panel_use_ssc(dev_priv)) | |
43565a06 | 8330 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
8331 | else |
8332 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8333 | ||
b75ca6f6 ACO |
8334 | dpll |= DPLL_VCO_ENABLE; |
8335 | ||
8336 | crtc_state->dpll_hw_state.dpll = dpll; | |
8337 | crtc_state->dpll_hw_state.fp0 = fp; | |
8338 | crtc_state->dpll_hw_state.fp1 = fp2; | |
de13a2e3 PZ |
8339 | } |
8340 | ||
190f68c5 ACO |
8341 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
8342 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 8343 | { |
997c030c | 8344 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 8345 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 8346 | const struct intel_limit *limit; |
997c030c | 8347 | int refclk = 120000; |
de13a2e3 | 8348 | |
dd3cd74a ACO |
8349 | memset(&crtc_state->dpll_hw_state, 0, |
8350 | sizeof(crtc_state->dpll_hw_state)); | |
8351 | ||
ded220e2 ACO |
8352 | crtc->lowfreq_avail = false; |
8353 | ||
8354 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ | |
8355 | if (!crtc_state->has_pch_encoder) | |
8356 | return 0; | |
79e53945 | 8357 | |
2d84d2b3 | 8358 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
997c030c ACO |
8359 | if (intel_panel_use_ssc(dev_priv)) { |
8360 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", | |
8361 | dev_priv->vbt.lvds_ssc_freq); | |
8362 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8363 | } | |
8364 | ||
8365 | if (intel_is_dual_link_lvds(dev)) { | |
8366 | if (refclk == 100000) | |
8367 | limit = &intel_limits_ironlake_dual_lvds_100m; | |
8368 | else | |
8369 | limit = &intel_limits_ironlake_dual_lvds; | |
8370 | } else { | |
8371 | if (refclk == 100000) | |
8372 | limit = &intel_limits_ironlake_single_lvds_100m; | |
8373 | else | |
8374 | limit = &intel_limits_ironlake_single_lvds; | |
8375 | } | |
8376 | } else { | |
8377 | limit = &intel_limits_ironlake_dac; | |
8378 | } | |
8379 | ||
364ee29d | 8380 | if (!crtc_state->clock_set && |
997c030c ACO |
8381 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
8382 | refclk, NULL, &crtc_state->dpll)) { | |
364ee29d ACO |
8383 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
8384 | return -EINVAL; | |
f47709a9 | 8385 | } |
79e53945 | 8386 | |
cbaa3315 | 8387 | ironlake_compute_dpll(crtc, crtc_state, NULL); |
66e985c0 | 8388 | |
efd38b68 | 8389 | if (!intel_get_shared_dpll(crtc, crtc_state, NULL)) { |
ded220e2 ACO |
8390 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
8391 | pipe_name(crtc->pipe)); | |
8392 | return -EINVAL; | |
3fb37703 | 8393 | } |
79e53945 | 8394 | |
c8f7a0db | 8395 | return 0; |
79e53945 JB |
8396 | } |
8397 | ||
eb14cb74 VS |
8398 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
8399 | struct intel_link_m_n *m_n) | |
8400 | { | |
8401 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8402 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb14cb74 VS |
8403 | enum pipe pipe = crtc->pipe; |
8404 | ||
8405 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
8406 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
8407 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8408 | & ~TU_SIZE_MASK; | |
8409 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
8410 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8411 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8412 | } | |
8413 | ||
8414 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
8415 | enum transcoder transcoder, | |
b95af8be VK |
8416 | struct intel_link_m_n *m_n, |
8417 | struct intel_link_m_n *m2_n2) | |
72419203 | 8418 | { |
6315b5d3 | 8419 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
eb14cb74 | 8420 | enum pipe pipe = crtc->pipe; |
72419203 | 8421 | |
6315b5d3 | 8422 | if (INTEL_GEN(dev_priv) >= 5) { |
eb14cb74 VS |
8423 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); |
8424 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
8425 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
8426 | & ~TU_SIZE_MASK; | |
8427 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
8428 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
8429 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
8430 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
8431 | * gen < 8) and if DRRS is supported (to make sure the | |
8432 | * registers are not unnecessarily read). | |
8433 | */ | |
6315b5d3 | 8434 | if (m2_n2 && INTEL_GEN(dev_priv) < 8 && |
6e3c9717 | 8435 | crtc->config->has_drrs) { |
b95af8be VK |
8436 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
8437 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
8438 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
8439 | & ~TU_SIZE_MASK; | |
8440 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
8441 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
8442 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8443 | } | |
eb14cb74 VS |
8444 | } else { |
8445 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
8446 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
8447 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8448 | & ~TU_SIZE_MASK; | |
8449 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
8450 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8451 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8452 | } | |
8453 | } | |
8454 | ||
8455 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 8456 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 8457 | { |
681a8504 | 8458 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
8459 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
8460 | else | |
8461 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
8462 | &pipe_config->dp_m_n, |
8463 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 8464 | } |
72419203 | 8465 | |
eb14cb74 | 8466 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 8467 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
8468 | { |
8469 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 8470 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
8471 | } |
8472 | ||
bd2e244f | 8473 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8474 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
8475 | { |
8476 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8477 | struct drm_i915_private *dev_priv = to_i915(dev); |
a1b2278e CK |
8478 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
8479 | uint32_t ps_ctrl = 0; | |
8480 | int id = -1; | |
8481 | int i; | |
bd2e244f | 8482 | |
a1b2278e CK |
8483 | /* find scaler attached to this pipe */ |
8484 | for (i = 0; i < crtc->num_scalers; i++) { | |
8485 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
8486 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
8487 | id = i; | |
8488 | pipe_config->pch_pfit.enabled = true; | |
8489 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
8490 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
8491 | break; | |
8492 | } | |
8493 | } | |
bd2e244f | 8494 | |
a1b2278e CK |
8495 | scaler_state->scaler_id = id; |
8496 | if (id >= 0) { | |
8497 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
8498 | } else { | |
8499 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
8500 | } |
8501 | } | |
8502 | ||
5724dbd1 DL |
8503 | static void |
8504 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
8505 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
8506 | { |
8507 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8508 | struct drm_i915_private *dev_priv = to_i915(dev); |
40f46283 | 8509 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
8510 | int pipe = crtc->pipe; |
8511 | int fourcc, pixel_format; | |
6761dd31 | 8512 | unsigned int aligned_height; |
bc8d7dff | 8513 | struct drm_framebuffer *fb; |
1b842c89 | 8514 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 8515 | |
d9806c9f | 8516 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8517 | if (!intel_fb) { |
bc8d7dff DL |
8518 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8519 | return; | |
8520 | } | |
8521 | ||
1b842c89 DL |
8522 | fb = &intel_fb->base; |
8523 | ||
d2e9f5fc VS |
8524 | fb->dev = dev; |
8525 | ||
bc8d7dff | 8526 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
8527 | if (!(val & PLANE_CTL_ENABLE)) |
8528 | goto error; | |
8529 | ||
bc8d7dff DL |
8530 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
8531 | fourcc = skl_format_to_fourcc(pixel_format, | |
8532 | val & PLANE_CTL_ORDER_RGBX, | |
8533 | val & PLANE_CTL_ALPHA_MASK); | |
2f3f4763 | 8534 | fb->format = drm_format_info(fourcc); |
bc8d7dff | 8535 | |
40f46283 DL |
8536 | tiling = val & PLANE_CTL_TILED_MASK; |
8537 | switch (tiling) { | |
8538 | case PLANE_CTL_TILED_LINEAR: | |
2f075565 | 8539 | fb->modifier = DRM_FORMAT_MOD_LINEAR; |
40f46283 DL |
8540 | break; |
8541 | case PLANE_CTL_TILED_X: | |
8542 | plane_config->tiling = I915_TILING_X; | |
bae781b2 | 8543 | fb->modifier = I915_FORMAT_MOD_X_TILED; |
40f46283 DL |
8544 | break; |
8545 | case PLANE_CTL_TILED_Y: | |
2e2adb05 VS |
8546 | if (val & PLANE_CTL_DECOMPRESSION_ENABLE) |
8547 | fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS; | |
8548 | else | |
8549 | fb->modifier = I915_FORMAT_MOD_Y_TILED; | |
40f46283 DL |
8550 | break; |
8551 | case PLANE_CTL_TILED_YF: | |
2e2adb05 VS |
8552 | if (val & PLANE_CTL_DECOMPRESSION_ENABLE) |
8553 | fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS; | |
8554 | else | |
8555 | fb->modifier = I915_FORMAT_MOD_Yf_TILED; | |
40f46283 DL |
8556 | break; |
8557 | default: | |
8558 | MISSING_CASE(tiling); | |
8559 | goto error; | |
8560 | } | |
8561 | ||
bc8d7dff DL |
8562 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
8563 | plane_config->base = base; | |
8564 | ||
8565 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
8566 | ||
8567 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
8568 | fb->height = ((val >> 16) & 0xfff) + 1; | |
8569 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
8570 | ||
8571 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
d88c4afd | 8572 | stride_mult = intel_fb_stride_alignment(fb, 0); |
bc8d7dff DL |
8573 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
8574 | ||
d88c4afd | 8575 | aligned_height = intel_fb_align_height(fb, 0, fb->height); |
bc8d7dff | 8576 | |
f37b5c2b | 8577 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
8578 | |
8579 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
8580 | pipe_name(pipe), fb->width, fb->height, | |
272725c7 | 8581 | fb->format->cpp[0] * 8, base, fb->pitches[0], |
bc8d7dff DL |
8582 | plane_config->size); |
8583 | ||
2d14030b | 8584 | plane_config->fb = intel_fb; |
bc8d7dff DL |
8585 | return; |
8586 | ||
8587 | error: | |
d1a3a036 | 8588 | kfree(intel_fb); |
bc8d7dff DL |
8589 | } |
8590 | ||
2fa2fe9a | 8591 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8592 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
8593 | { |
8594 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8595 | struct drm_i915_private *dev_priv = to_i915(dev); |
2fa2fe9a DV |
8596 | uint32_t tmp; |
8597 | ||
8598 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
8599 | ||
8600 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 8601 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
8602 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
8603 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
8604 | |
8605 | /* We currently do not free assignements of panel fitters on | |
8606 | * ivb/hsw (since we don't use the higher upscaling modes which | |
8607 | * differentiates them) so just WARN about this case for now. */ | |
5db94019 | 8608 | if (IS_GEN7(dev_priv)) { |
cb8b2a30 DV |
8609 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != |
8610 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
8611 | } | |
2fa2fe9a | 8612 | } |
79e53945 JB |
8613 | } |
8614 | ||
5724dbd1 DL |
8615 | static void |
8616 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
8617 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
8618 | { |
8619 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8620 | struct drm_i915_private *dev_priv = to_i915(dev); |
4c6baa59 | 8621 | u32 val, base, offset; |
aeee5a49 | 8622 | int pipe = crtc->pipe; |
4c6baa59 | 8623 | int fourcc, pixel_format; |
6761dd31 | 8624 | unsigned int aligned_height; |
b113d5ee | 8625 | struct drm_framebuffer *fb; |
1b842c89 | 8626 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 8627 | |
42a7b088 DL |
8628 | val = I915_READ(DSPCNTR(pipe)); |
8629 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8630 | return; | |
8631 | ||
d9806c9f | 8632 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8633 | if (!intel_fb) { |
4c6baa59 JB |
8634 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8635 | return; | |
8636 | } | |
8637 | ||
1b842c89 DL |
8638 | fb = &intel_fb->base; |
8639 | ||
d2e9f5fc VS |
8640 | fb->dev = dev; |
8641 | ||
6315b5d3 | 8642 | if (INTEL_GEN(dev_priv) >= 4) { |
18c5247e | 8643 | if (val & DISPPLANE_TILED) { |
49af449b | 8644 | plane_config->tiling = I915_TILING_X; |
bae781b2 | 8645 | fb->modifier = I915_FORMAT_MOD_X_TILED; |
18c5247e DV |
8646 | } |
8647 | } | |
4c6baa59 JB |
8648 | |
8649 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8650 | fourcc = i9xx_format_to_fourcc(pixel_format); |
2f3f4763 | 8651 | fb->format = drm_format_info(fourcc); |
4c6baa59 | 8652 | |
aeee5a49 | 8653 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
8652744b | 8654 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
aeee5a49 | 8655 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 8656 | } else { |
49af449b | 8657 | if (plane_config->tiling) |
aeee5a49 | 8658 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 8659 | else |
aeee5a49 | 8660 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
8661 | } |
8662 | plane_config->base = base; | |
8663 | ||
8664 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8665 | fb->width = ((val >> 16) & 0xfff) + 1; |
8666 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
8667 | |
8668 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8669 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 8670 | |
d88c4afd | 8671 | aligned_height = intel_fb_align_height(fb, 0, fb->height); |
4c6baa59 | 8672 | |
f37b5c2b | 8673 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 8674 | |
2844a921 DL |
8675 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8676 | pipe_name(pipe), fb->width, fb->height, | |
272725c7 | 8677 | fb->format->cpp[0] * 8, base, fb->pitches[0], |
2844a921 | 8678 | plane_config->size); |
b113d5ee | 8679 | |
2d14030b | 8680 | plane_config->fb = intel_fb; |
4c6baa59 JB |
8681 | } |
8682 | ||
0e8ffe1b | 8683 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8684 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8685 | { |
8686 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8687 | struct drm_i915_private *dev_priv = to_i915(dev); |
1729050e | 8688 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 8689 | uint32_t tmp; |
1729050e | 8690 | bool ret; |
0e8ffe1b | 8691 | |
1729050e ID |
8692 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
8693 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
930e8c9e PZ |
8694 | return false; |
8695 | ||
e143a21c | 8696 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 8697 | pipe_config->shared_dpll = NULL; |
eccb140b | 8698 | |
1729050e | 8699 | ret = false; |
0e8ffe1b DV |
8700 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8701 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 8702 | goto out; |
0e8ffe1b | 8703 | |
42571aef VS |
8704 | switch (tmp & PIPECONF_BPC_MASK) { |
8705 | case PIPECONF_6BPC: | |
8706 | pipe_config->pipe_bpp = 18; | |
8707 | break; | |
8708 | case PIPECONF_8BPC: | |
8709 | pipe_config->pipe_bpp = 24; | |
8710 | break; | |
8711 | case PIPECONF_10BPC: | |
8712 | pipe_config->pipe_bpp = 30; | |
8713 | break; | |
8714 | case PIPECONF_12BPC: | |
8715 | pipe_config->pipe_bpp = 36; | |
8716 | break; | |
8717 | default: | |
8718 | break; | |
8719 | } | |
8720 | ||
b5a9fa09 DV |
8721 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
8722 | pipe_config->limited_color_range = true; | |
8723 | ||
ab9412ba | 8724 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 | 8725 | struct intel_shared_dpll *pll; |
8106ddbd | 8726 | enum intel_dpll_id pll_id; |
66e985c0 | 8727 | |
88adfff1 DV |
8728 | pipe_config->has_pch_encoder = true; |
8729 | ||
627eb5a3 DV |
8730 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
8731 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
8732 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
8733 | |
8734 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 8735 | |
2d1fe073 | 8736 | if (HAS_PCH_IBX(dev_priv)) { |
d9a7bc67 ID |
8737 | /* |
8738 | * The pipe->pch transcoder and pch transcoder->pll | |
8739 | * mapping is fixed. | |
8740 | */ | |
8106ddbd | 8741 | pll_id = (enum intel_dpll_id) crtc->pipe; |
c0d43d62 DV |
8742 | } else { |
8743 | tmp = I915_READ(PCH_DPLL_SEL); | |
8744 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
8106ddbd | 8745 | pll_id = DPLL_ID_PCH_PLL_B; |
c0d43d62 | 8746 | else |
8106ddbd | 8747 | pll_id= DPLL_ID_PCH_PLL_A; |
c0d43d62 | 8748 | } |
66e985c0 | 8749 | |
8106ddbd ACO |
8750 | pipe_config->shared_dpll = |
8751 | intel_get_shared_dpll_by_id(dev_priv, pll_id); | |
8752 | pll = pipe_config->shared_dpll; | |
66e985c0 | 8753 | |
2edd6443 ACO |
8754 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
8755 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
8756 | |
8757 | tmp = pipe_config->dpll_hw_state.dpll; | |
8758 | pipe_config->pixel_multiplier = | |
8759 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
8760 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
8761 | |
8762 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
8763 | } else { |
8764 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
8765 | } |
8766 | ||
1bd1bd80 | 8767 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 8768 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 8769 | |
2fa2fe9a DV |
8770 | ironlake_get_pfit_config(crtc, pipe_config); |
8771 | ||
1729050e ID |
8772 | ret = true; |
8773 | ||
8774 | out: | |
8775 | intel_display_power_put(dev_priv, power_domain); | |
8776 | ||
8777 | return ret; | |
0e8ffe1b DV |
8778 | } |
8779 | ||
be256dc7 PZ |
8780 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
8781 | { | |
91c8a326 | 8782 | struct drm_device *dev = &dev_priv->drm; |
be256dc7 | 8783 | struct intel_crtc *crtc; |
be256dc7 | 8784 | |
d3fcc808 | 8785 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 8786 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
8787 | pipe_name(crtc->pipe)); |
8788 | ||
9c3a16c8 ID |
8789 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL)), |
8790 | "Display power well on\n"); | |
e2c719b7 | 8791 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); |
01403de3 VS |
8792 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
8793 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
44cb734c | 8794 | I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n"); |
e2c719b7 | 8795 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, |
be256dc7 | 8796 | "CPU PWM1 enabled\n"); |
772c2a51 | 8797 | if (IS_HASWELL(dev_priv)) |
e2c719b7 | 8798 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 8799 | "CPU PWM2 enabled\n"); |
e2c719b7 | 8800 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 8801 | "PCH PWM1 enabled\n"); |
e2c719b7 | 8802 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 8803 | "Utility pin enabled\n"); |
e2c719b7 | 8804 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 8805 | |
9926ada1 PZ |
8806 | /* |
8807 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
8808 | * interrupts remain enabled. We used to check for that, but since it's | |
8809 | * gen-specific and since we only disable LCPLL after we fully disable | |
8810 | * the interrupts, the check below should be enough. | |
8811 | */ | |
e2c719b7 | 8812 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
8813 | } |
8814 | ||
9ccd5aeb PZ |
8815 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
8816 | { | |
772c2a51 | 8817 | if (IS_HASWELL(dev_priv)) |
9ccd5aeb PZ |
8818 | return I915_READ(D_COMP_HSW); |
8819 | else | |
8820 | return I915_READ(D_COMP_BDW); | |
8821 | } | |
8822 | ||
3c4c9b81 PZ |
8823 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
8824 | { | |
772c2a51 | 8825 | if (IS_HASWELL(dev_priv)) { |
3c4c9b81 PZ |
8826 | mutex_lock(&dev_priv->rps.hw_lock); |
8827 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
8828 | val)) | |
79cf219a | 8829 | DRM_DEBUG_KMS("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
8830 | mutex_unlock(&dev_priv->rps.hw_lock); |
8831 | } else { | |
9ccd5aeb PZ |
8832 | I915_WRITE(D_COMP_BDW, val); |
8833 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 8834 | } |
be256dc7 PZ |
8835 | } |
8836 | ||
8837 | /* | |
8838 | * This function implements pieces of two sequences from BSpec: | |
8839 | * - Sequence for display software to disable LCPLL | |
8840 | * - Sequence for display software to allow package C8+ | |
8841 | * The steps implemented here are just the steps that actually touch the LCPLL | |
8842 | * register. Callers should take care of disabling all the display engine | |
8843 | * functions, doing the mode unset, fixing interrupts, etc. | |
8844 | */ | |
6ff58d53 PZ |
8845 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
8846 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
8847 | { |
8848 | uint32_t val; | |
8849 | ||
8850 | assert_can_disable_lcpll(dev_priv); | |
8851 | ||
8852 | val = I915_READ(LCPLL_CTL); | |
8853 | ||
8854 | if (switch_to_fclk) { | |
8855 | val |= LCPLL_CD_SOURCE_FCLK; | |
8856 | I915_WRITE(LCPLL_CTL, val); | |
8857 | ||
f53dd63f ID |
8858 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
8859 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
be256dc7 PZ |
8860 | DRM_ERROR("Switching to FCLK failed\n"); |
8861 | ||
8862 | val = I915_READ(LCPLL_CTL); | |
8863 | } | |
8864 | ||
8865 | val |= LCPLL_PLL_DISABLE; | |
8866 | I915_WRITE(LCPLL_CTL, val); | |
8867 | POSTING_READ(LCPLL_CTL); | |
8868 | ||
24d8441d | 8869 | if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1)) |
be256dc7 PZ |
8870 | DRM_ERROR("LCPLL still locked\n"); |
8871 | ||
9ccd5aeb | 8872 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 8873 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 8874 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
8875 | ndelay(100); |
8876 | ||
9ccd5aeb PZ |
8877 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
8878 | 1)) | |
be256dc7 PZ |
8879 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
8880 | ||
8881 | if (allow_power_down) { | |
8882 | val = I915_READ(LCPLL_CTL); | |
8883 | val |= LCPLL_POWER_DOWN_ALLOW; | |
8884 | I915_WRITE(LCPLL_CTL, val); | |
8885 | POSTING_READ(LCPLL_CTL); | |
8886 | } | |
8887 | } | |
8888 | ||
8889 | /* | |
8890 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
8891 | * source. | |
8892 | */ | |
6ff58d53 | 8893 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
8894 | { |
8895 | uint32_t val; | |
8896 | ||
8897 | val = I915_READ(LCPLL_CTL); | |
8898 | ||
8899 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
8900 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
8901 | return; | |
8902 | ||
a8a8bd54 PZ |
8903 | /* |
8904 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
8905 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 8906 | */ |
59bad947 | 8907 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 8908 | |
be256dc7 PZ |
8909 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
8910 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
8911 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 8912 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
8913 | } |
8914 | ||
9ccd5aeb | 8915 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
8916 | val |= D_COMP_COMP_FORCE; |
8917 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 8918 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
8919 | |
8920 | val = I915_READ(LCPLL_CTL); | |
8921 | val &= ~LCPLL_PLL_DISABLE; | |
8922 | I915_WRITE(LCPLL_CTL, val); | |
8923 | ||
93220c08 CW |
8924 | if (intel_wait_for_register(dev_priv, |
8925 | LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, | |
8926 | 5)) | |
be256dc7 PZ |
8927 | DRM_ERROR("LCPLL not locked yet\n"); |
8928 | ||
8929 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
8930 | val = I915_READ(LCPLL_CTL); | |
8931 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
8932 | I915_WRITE(LCPLL_CTL, val); | |
8933 | ||
f53dd63f ID |
8934 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
8935 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
be256dc7 PZ |
8936 | DRM_ERROR("Switching back to LCPLL failed\n"); |
8937 | } | |
215733fa | 8938 | |
59bad947 | 8939 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
4c75b940 | 8940 | intel_update_cdclk(dev_priv); |
be256dc7 PZ |
8941 | } |
8942 | ||
765dab67 PZ |
8943 | /* |
8944 | * Package states C8 and deeper are really deep PC states that can only be | |
8945 | * reached when all the devices on the system allow it, so even if the graphics | |
8946 | * device allows PC8+, it doesn't mean the system will actually get to these | |
8947 | * states. Our driver only allows PC8+ when going into runtime PM. | |
8948 | * | |
8949 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
8950 | * well is disabled and most interrupts are disabled, and these are also | |
8951 | * requirements for runtime PM. When these conditions are met, we manually do | |
8952 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
8953 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
8954 | * hang the machine. | |
8955 | * | |
8956 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
8957 | * the state of some registers, so when we come back from PC8+ we need to | |
8958 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
8959 | * need to take care of the registers kept by RC6. Notice that this happens even | |
8960 | * if we don't put the device in PCI D3 state (which is what currently happens | |
8961 | * because of the runtime PM support). | |
8962 | * | |
8963 | * For more, read "Display Sequences for Package C8" on the hardware | |
8964 | * documentation. | |
8965 | */ | |
a14cb6fc | 8966 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 8967 | { |
c67a470b PZ |
8968 | uint32_t val; |
8969 | ||
c67a470b PZ |
8970 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
8971 | ||
4f8036a2 | 8972 | if (HAS_PCH_LPT_LP(dev_priv)) { |
c67a470b PZ |
8973 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
8974 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
8975 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
8976 | } | |
8977 | ||
c39055b0 | 8978 | lpt_disable_clkout_dp(dev_priv); |
c67a470b PZ |
8979 | hsw_disable_lcpll(dev_priv, true, true); |
8980 | } | |
8981 | ||
a14cb6fc | 8982 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 8983 | { |
c67a470b PZ |
8984 | uint32_t val; |
8985 | ||
c67a470b PZ |
8986 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
8987 | ||
8988 | hsw_restore_lcpll(dev_priv); | |
c39055b0 | 8989 | lpt_init_pch_refclk(dev_priv); |
c67a470b | 8990 | |
4f8036a2 | 8991 | if (HAS_PCH_LPT_LP(dev_priv)) { |
c67a470b PZ |
8992 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
8993 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
8994 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
8995 | } | |
c67a470b PZ |
8996 | } |
8997 | ||
190f68c5 ACO |
8998 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
8999 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 9000 | { |
d7edc4e5 | 9001 | if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) { |
44a126ba PZ |
9002 | struct intel_encoder *encoder = |
9003 | intel_ddi_get_crtc_new_encoder(crtc_state); | |
9004 | ||
9005 | if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) { | |
9006 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
9007 | pipe_name(crtc->pipe)); | |
af3997b5 | 9008 | return -EINVAL; |
44a126ba | 9009 | } |
af3997b5 | 9010 | } |
716c2e55 | 9011 | |
c7653199 | 9012 | crtc->lowfreq_avail = false; |
644cef34 | 9013 | |
c8f7a0db | 9014 | return 0; |
79e53945 JB |
9015 | } |
9016 | ||
8b0f7e06 KM |
9017 | static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv, |
9018 | enum port port, | |
9019 | struct intel_crtc_state *pipe_config) | |
9020 | { | |
9021 | enum intel_dpll_id id; | |
9022 | u32 temp; | |
9023 | ||
9024 | temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); | |
dfbd4508 | 9025 | id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port); |
8b0f7e06 KM |
9026 | |
9027 | if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2)) | |
9028 | return; | |
9029 | ||
9030 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
9031 | } | |
9032 | ||
3760b59c S |
9033 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
9034 | enum port port, | |
9035 | struct intel_crtc_state *pipe_config) | |
9036 | { | |
8106ddbd ACO |
9037 | enum intel_dpll_id id; |
9038 | ||
3760b59c S |
9039 | switch (port) { |
9040 | case PORT_A: | |
08250c4b | 9041 | id = DPLL_ID_SKL_DPLL0; |
3760b59c S |
9042 | break; |
9043 | case PORT_B: | |
08250c4b | 9044 | id = DPLL_ID_SKL_DPLL1; |
3760b59c S |
9045 | break; |
9046 | case PORT_C: | |
08250c4b | 9047 | id = DPLL_ID_SKL_DPLL2; |
3760b59c S |
9048 | break; |
9049 | default: | |
9050 | DRM_ERROR("Incorrect port type\n"); | |
8106ddbd | 9051 | return; |
3760b59c | 9052 | } |
8106ddbd ACO |
9053 | |
9054 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
3760b59c S |
9055 | } |
9056 | ||
96b7dfb7 S |
9057 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
9058 | enum port port, | |
5cec258b | 9059 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 9060 | { |
8106ddbd | 9061 | enum intel_dpll_id id; |
a3c988ea | 9062 | u32 temp; |
96b7dfb7 S |
9063 | |
9064 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
c856052a | 9065 | id = temp >> (port * 3 + 1); |
96b7dfb7 | 9066 | |
c856052a | 9067 | if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3)) |
8106ddbd | 9068 | return; |
8106ddbd ACO |
9069 | |
9070 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
96b7dfb7 S |
9071 | } |
9072 | ||
7d2c8175 DL |
9073 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
9074 | enum port port, | |
5cec258b | 9075 | struct intel_crtc_state *pipe_config) |
7d2c8175 | 9076 | { |
8106ddbd | 9077 | enum intel_dpll_id id; |
c856052a | 9078 | uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); |
8106ddbd | 9079 | |
c856052a | 9080 | switch (ddi_pll_sel) { |
7d2c8175 | 9081 | case PORT_CLK_SEL_WRPLL1: |
8106ddbd | 9082 | id = DPLL_ID_WRPLL1; |
7d2c8175 DL |
9083 | break; |
9084 | case PORT_CLK_SEL_WRPLL2: | |
8106ddbd | 9085 | id = DPLL_ID_WRPLL2; |
7d2c8175 | 9086 | break; |
00490c22 | 9087 | case PORT_CLK_SEL_SPLL: |
8106ddbd | 9088 | id = DPLL_ID_SPLL; |
79bd23da | 9089 | break; |
9d16da65 ACO |
9090 | case PORT_CLK_SEL_LCPLL_810: |
9091 | id = DPLL_ID_LCPLL_810; | |
9092 | break; | |
9093 | case PORT_CLK_SEL_LCPLL_1350: | |
9094 | id = DPLL_ID_LCPLL_1350; | |
9095 | break; | |
9096 | case PORT_CLK_SEL_LCPLL_2700: | |
9097 | id = DPLL_ID_LCPLL_2700; | |
9098 | break; | |
8106ddbd | 9099 | default: |
c856052a | 9100 | MISSING_CASE(ddi_pll_sel); |
8106ddbd ACO |
9101 | /* fall through */ |
9102 | case PORT_CLK_SEL_NONE: | |
8106ddbd | 9103 | return; |
7d2c8175 | 9104 | } |
8106ddbd ACO |
9105 | |
9106 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
7d2c8175 DL |
9107 | } |
9108 | ||
cf30429e JN |
9109 | static bool hsw_get_transcoder_state(struct intel_crtc *crtc, |
9110 | struct intel_crtc_state *pipe_config, | |
d8fc70b7 | 9111 | u64 *power_domain_mask) |
cf30429e JN |
9112 | { |
9113 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9114 | struct drm_i915_private *dev_priv = to_i915(dev); |
cf30429e JN |
9115 | enum intel_display_power_domain power_domain; |
9116 | u32 tmp; | |
9117 | ||
d9a7bc67 ID |
9118 | /* |
9119 | * The pipe->transcoder mapping is fixed with the exception of the eDP | |
9120 | * transcoder handled below. | |
9121 | */ | |
cf30429e JN |
9122 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
9123 | ||
9124 | /* | |
9125 | * XXX: Do intel_display_power_get_if_enabled before reading this (for | |
9126 | * consistency and less surprising code; it's in always on power). | |
9127 | */ | |
9128 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
9129 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
9130 | enum pipe trans_edp_pipe; | |
9131 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
9132 | default: | |
9133 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
9134 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
9135 | case TRANS_DDI_EDP_INPUT_A_ON: | |
9136 | trans_edp_pipe = PIPE_A; | |
9137 | break; | |
9138 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
9139 | trans_edp_pipe = PIPE_B; | |
9140 | break; | |
9141 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
9142 | trans_edp_pipe = PIPE_C; | |
9143 | break; | |
9144 | } | |
9145 | ||
9146 | if (trans_edp_pipe == crtc->pipe) | |
9147 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
9148 | } | |
9149 | ||
9150 | power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); | |
9151 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
9152 | return false; | |
d8fc70b7 | 9153 | *power_domain_mask |= BIT_ULL(power_domain); |
cf30429e JN |
9154 | |
9155 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); | |
9156 | ||
9157 | return tmp & PIPECONF_ENABLE; | |
9158 | } | |
9159 | ||
4d1de975 JN |
9160 | static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, |
9161 | struct intel_crtc_state *pipe_config, | |
d8fc70b7 | 9162 | u64 *power_domain_mask) |
4d1de975 JN |
9163 | { |
9164 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9165 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 JN |
9166 | enum intel_display_power_domain power_domain; |
9167 | enum port port; | |
9168 | enum transcoder cpu_transcoder; | |
9169 | u32 tmp; | |
9170 | ||
4d1de975 JN |
9171 | for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { |
9172 | if (port == PORT_A) | |
9173 | cpu_transcoder = TRANSCODER_DSI_A; | |
9174 | else | |
9175 | cpu_transcoder = TRANSCODER_DSI_C; | |
9176 | ||
9177 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
9178 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
9179 | continue; | |
d8fc70b7 | 9180 | *power_domain_mask |= BIT_ULL(power_domain); |
4d1de975 | 9181 | |
db18b6a6 ID |
9182 | /* |
9183 | * The PLL needs to be enabled with a valid divider | |
9184 | * configuration, otherwise accessing DSI registers will hang | |
9185 | * the machine. See BSpec North Display Engine | |
9186 | * registers/MIPI[BXT]. We can break out here early, since we | |
9187 | * need the same DSI PLL to be enabled for both DSI ports. | |
9188 | */ | |
9189 | if (!intel_dsi_pll_is_enabled(dev_priv)) | |
9190 | break; | |
9191 | ||
4d1de975 JN |
9192 | /* XXX: this works for video mode only */ |
9193 | tmp = I915_READ(BXT_MIPI_PORT_CTRL(port)); | |
9194 | if (!(tmp & DPI_ENABLE)) | |
9195 | continue; | |
9196 | ||
9197 | tmp = I915_READ(MIPI_CTRL(port)); | |
9198 | if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) | |
9199 | continue; | |
9200 | ||
9201 | pipe_config->cpu_transcoder = cpu_transcoder; | |
4d1de975 JN |
9202 | break; |
9203 | } | |
9204 | ||
d7edc4e5 | 9205 | return transcoder_is_dsi(pipe_config->cpu_transcoder); |
4d1de975 JN |
9206 | } |
9207 | ||
26804afd | 9208 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 9209 | struct intel_crtc_state *pipe_config) |
26804afd | 9210 | { |
6315b5d3 | 9211 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
d452c5b6 | 9212 | struct intel_shared_dpll *pll; |
26804afd DV |
9213 | enum port port; |
9214 | uint32_t tmp; | |
9215 | ||
9216 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
9217 | ||
9218 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
9219 | ||
8b0f7e06 KM |
9220 | if (IS_CANNONLAKE(dev_priv)) |
9221 | cannonlake_get_ddi_pll(dev_priv, port, pipe_config); | |
9222 | else if (IS_GEN9_BC(dev_priv)) | |
96b7dfb7 | 9223 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
cc3f90f0 | 9224 | else if (IS_GEN9_LP(dev_priv)) |
3760b59c | 9225 | bxt_get_ddi_pll(dev_priv, port, pipe_config); |
96b7dfb7 S |
9226 | else |
9227 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 9228 | |
8106ddbd ACO |
9229 | pll = pipe_config->shared_dpll; |
9230 | if (pll) { | |
2edd6443 ACO |
9231 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
9232 | &pipe_config->dpll_hw_state)); | |
d452c5b6 DV |
9233 | } |
9234 | ||
26804afd DV |
9235 | /* |
9236 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
9237 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
9238 | * the PCH transcoder is on. | |
9239 | */ | |
6315b5d3 | 9240 | if (INTEL_GEN(dev_priv) < 9 && |
ca370455 | 9241 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
26804afd DV |
9242 | pipe_config->has_pch_encoder = true; |
9243 | ||
9244 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
9245 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9246 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
9247 | ||
9248 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
9249 | } | |
9250 | } | |
9251 | ||
0e8ffe1b | 9252 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9253 | struct intel_crtc_state *pipe_config) |
0e8ffe1b | 9254 | { |
6315b5d3 | 9255 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1729050e | 9256 | enum intel_display_power_domain power_domain; |
d8fc70b7 | 9257 | u64 power_domain_mask; |
cf30429e | 9258 | bool active; |
0e8ffe1b | 9259 | |
e79dfb51 | 9260 | intel_crtc_init_scalers(crtc, pipe_config); |
5fb9dadf | 9261 | |
1729050e ID |
9262 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
9263 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 | 9264 | return false; |
d8fc70b7 | 9265 | power_domain_mask = BIT_ULL(power_domain); |
1729050e | 9266 | |
8106ddbd | 9267 | pipe_config->shared_dpll = NULL; |
c0d43d62 | 9268 | |
cf30429e | 9269 | active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask); |
eccb140b | 9270 | |
cc3f90f0 | 9271 | if (IS_GEN9_LP(dev_priv) && |
d7edc4e5 VS |
9272 | bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) { |
9273 | WARN_ON(active); | |
9274 | active = true; | |
4d1de975 JN |
9275 | } |
9276 | ||
cf30429e | 9277 | if (!active) |
1729050e | 9278 | goto out; |
0e8ffe1b | 9279 | |
d7edc4e5 | 9280 | if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { |
4d1de975 JN |
9281 | haswell_get_ddi_port_state(crtc, pipe_config); |
9282 | intel_get_pipe_timings(crtc, pipe_config); | |
9283 | } | |
627eb5a3 | 9284 | |
bc58be60 | 9285 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 9286 | |
05dc698c LL |
9287 | pipe_config->gamma_mode = |
9288 | I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; | |
9289 | ||
b22ca995 SS |
9290 | if (IS_BROADWELL(dev_priv) || dev_priv->info.gen >= 9) { |
9291 | u32 tmp = I915_READ(PIPEMISC(crtc->pipe)); | |
9292 | bool clrspace_yuv = tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV; | |
9293 | ||
9294 | if (IS_GEMINILAKE(dev_priv) || dev_priv->info.gen >= 10) { | |
9295 | bool blend_mode_420 = tmp & | |
9296 | PIPEMISC_YUV420_MODE_FULL_BLEND; | |
9297 | ||
9298 | pipe_config->ycbcr420 = tmp & PIPEMISC_YUV420_ENABLE; | |
9299 | if (pipe_config->ycbcr420 != clrspace_yuv || | |
9300 | pipe_config->ycbcr420 != blend_mode_420) | |
9301 | DRM_DEBUG_KMS("Bad 4:2:0 mode (%08x)\n", tmp); | |
9302 | } else if (clrspace_yuv) { | |
9303 | DRM_DEBUG_KMS("YCbCr 4:2:0 Unsupported\n"); | |
9304 | } | |
9305 | } | |
9306 | ||
1729050e ID |
9307 | power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
9308 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
d8fc70b7 | 9309 | power_domain_mask |= BIT_ULL(power_domain); |
6315b5d3 | 9310 | if (INTEL_GEN(dev_priv) >= 9) |
bd2e244f | 9311 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 9312 | else |
1c132b44 | 9313 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 9314 | } |
88adfff1 | 9315 | |
772c2a51 | 9316 | if (IS_HASWELL(dev_priv)) |
e59150dc JB |
9317 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && |
9318 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 9319 | |
4d1de975 JN |
9320 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP && |
9321 | !transcoder_is_dsi(pipe_config->cpu_transcoder)) { | |
ebb69c95 CT |
9322 | pipe_config->pixel_multiplier = |
9323 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
9324 | } else { | |
9325 | pipe_config->pixel_multiplier = 1; | |
9326 | } | |
6c49f241 | 9327 | |
1729050e ID |
9328 | out: |
9329 | for_each_power_domain(power_domain, power_domain_mask) | |
9330 | intel_display_power_put(dev_priv, power_domain); | |
9331 | ||
cf30429e | 9332 | return active; |
0e8ffe1b DV |
9333 | } |
9334 | ||
cd5dcbf1 | 9335 | static u32 intel_cursor_base(const struct intel_plane_state *plane_state) |
1cecc830 VS |
9336 | { |
9337 | struct drm_i915_private *dev_priv = | |
9338 | to_i915(plane_state->base.plane->dev); | |
9339 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
9340 | const struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
9341 | u32 base; | |
9342 | ||
9343 | if (INTEL_INFO(dev_priv)->cursor_needs_physical) | |
9344 | base = obj->phys_handle->busaddr; | |
9345 | else | |
9346 | base = intel_plane_ggtt_offset(plane_state); | |
9347 | ||
1e7b4fd8 VS |
9348 | base += plane_state->main.offset; |
9349 | ||
1cecc830 VS |
9350 | /* ILK+ do this automagically */ |
9351 | if (HAS_GMCH_DISPLAY(dev_priv) && | |
a82256bc | 9352 | plane_state->base.rotation & DRM_MODE_ROTATE_180) |
1cecc830 VS |
9353 | base += (plane_state->base.crtc_h * |
9354 | plane_state->base.crtc_w - 1) * fb->format->cpp[0]; | |
9355 | ||
9356 | return base; | |
9357 | } | |
9358 | ||
ed270223 VS |
9359 | static u32 intel_cursor_position(const struct intel_plane_state *plane_state) |
9360 | { | |
9361 | int x = plane_state->base.crtc_x; | |
9362 | int y = plane_state->base.crtc_y; | |
9363 | u32 pos = 0; | |
9364 | ||
9365 | if (x < 0) { | |
9366 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
9367 | x = -x; | |
9368 | } | |
9369 | pos |= x << CURSOR_X_SHIFT; | |
9370 | ||
9371 | if (y < 0) { | |
9372 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
9373 | y = -y; | |
9374 | } | |
9375 | pos |= y << CURSOR_Y_SHIFT; | |
9376 | ||
9377 | return pos; | |
9378 | } | |
9379 | ||
3637ecf0 VS |
9380 | static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state) |
9381 | { | |
9382 | const struct drm_mode_config *config = | |
9383 | &plane_state->base.plane->dev->mode_config; | |
9384 | int width = plane_state->base.crtc_w; | |
9385 | int height = plane_state->base.crtc_h; | |
9386 | ||
9387 | return width > 0 && width <= config->cursor_width && | |
9388 | height > 0 && height <= config->cursor_height; | |
9389 | } | |
9390 | ||
659056f2 VS |
9391 | static int intel_check_cursor(struct intel_crtc_state *crtc_state, |
9392 | struct intel_plane_state *plane_state) | |
9393 | { | |
9394 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
1e7b4fd8 VS |
9395 | int src_x, src_y; |
9396 | u32 offset; | |
659056f2 VS |
9397 | int ret; |
9398 | ||
9399 | ret = drm_plane_helper_check_state(&plane_state->base, | |
9400 | &plane_state->clip, | |
9401 | DRM_PLANE_HELPER_NO_SCALING, | |
9402 | DRM_PLANE_HELPER_NO_SCALING, | |
9403 | true, true); | |
9404 | if (ret) | |
9405 | return ret; | |
9406 | ||
9407 | if (!fb) | |
9408 | return 0; | |
9409 | ||
9410 | if (fb->modifier != DRM_FORMAT_MOD_LINEAR) { | |
9411 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); | |
9412 | return -EINVAL; | |
9413 | } | |
9414 | ||
1e7b4fd8 VS |
9415 | src_x = plane_state->base.src_x >> 16; |
9416 | src_y = plane_state->base.src_y >> 16; | |
9417 | ||
9418 | intel_add_fb_offsets(&src_x, &src_y, plane_state, 0); | |
9419 | offset = intel_compute_tile_offset(&src_x, &src_y, plane_state, 0); | |
9420 | ||
9421 | if (src_x != 0 || src_y != 0) { | |
9422 | DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n"); | |
9423 | return -EINVAL; | |
9424 | } | |
9425 | ||
9426 | plane_state->main.offset = offset; | |
9427 | ||
659056f2 VS |
9428 | return 0; |
9429 | } | |
9430 | ||
292889e1 VS |
9431 | static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state, |
9432 | const struct intel_plane_state *plane_state) | |
9433 | { | |
1e1bb871 | 9434 | const struct drm_framebuffer *fb = plane_state->base.fb; |
292889e1 | 9435 | |
292889e1 VS |
9436 | return CURSOR_ENABLE | |
9437 | CURSOR_GAMMA_ENABLE | | |
9438 | CURSOR_FORMAT_ARGB | | |
1e1bb871 | 9439 | CURSOR_STRIDE(fb->pitches[0]); |
292889e1 VS |
9440 | } |
9441 | ||
659056f2 VS |
9442 | static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state) |
9443 | { | |
659056f2 | 9444 | int width = plane_state->base.crtc_w; |
659056f2 VS |
9445 | |
9446 | /* | |
9447 | * 845g/865g are only limited by the width of their cursors, | |
9448 | * the height is arbitrary up to the precision of the register. | |
9449 | */ | |
3637ecf0 | 9450 | return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64); |
659056f2 VS |
9451 | } |
9452 | ||
9453 | static int i845_check_cursor(struct intel_plane *plane, | |
9454 | struct intel_crtc_state *crtc_state, | |
9455 | struct intel_plane_state *plane_state) | |
9456 | { | |
9457 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
659056f2 VS |
9458 | int ret; |
9459 | ||
9460 | ret = intel_check_cursor(crtc_state, plane_state); | |
9461 | if (ret) | |
9462 | return ret; | |
9463 | ||
9464 | /* if we want to turn off the cursor ignore width and height */ | |
1e1bb871 | 9465 | if (!fb) |
659056f2 VS |
9466 | return 0; |
9467 | ||
9468 | /* Check for which cursor types we support */ | |
9469 | if (!i845_cursor_size_ok(plane_state)) { | |
9470 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", | |
9471 | plane_state->base.crtc_w, | |
9472 | plane_state->base.crtc_h); | |
9473 | return -EINVAL; | |
9474 | } | |
9475 | ||
1e1bb871 | 9476 | switch (fb->pitches[0]) { |
292889e1 VS |
9477 | case 256: |
9478 | case 512: | |
9479 | case 1024: | |
9480 | case 2048: | |
9481 | break; | |
1e1bb871 VS |
9482 | default: |
9483 | DRM_DEBUG_KMS("Invalid cursor stride (%u)\n", | |
9484 | fb->pitches[0]); | |
9485 | return -EINVAL; | |
292889e1 VS |
9486 | } |
9487 | ||
659056f2 VS |
9488 | plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state); |
9489 | ||
9490 | return 0; | |
292889e1 VS |
9491 | } |
9492 | ||
b2d03b0d VS |
9493 | static void i845_update_cursor(struct intel_plane *plane, |
9494 | const struct intel_crtc_state *crtc_state, | |
55a08b3f | 9495 | const struct intel_plane_state *plane_state) |
560b85bb | 9496 | { |
cd5dcbf1 | 9497 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
b2d03b0d VS |
9498 | u32 cntl = 0, base = 0, pos = 0, size = 0; |
9499 | unsigned long irqflags; | |
560b85bb | 9500 | |
936e71e3 | 9501 | if (plane_state && plane_state->base.visible) { |
55a08b3f ML |
9502 | unsigned int width = plane_state->base.crtc_w; |
9503 | unsigned int height = plane_state->base.crtc_h; | |
dc41c154 | 9504 | |
a0864d59 | 9505 | cntl = plane_state->ctl; |
dc41c154 | 9506 | size = (height << 12) | width; |
560b85bb | 9507 | |
b2d03b0d VS |
9508 | base = intel_cursor_base(plane_state); |
9509 | pos = intel_cursor_position(plane_state); | |
4b0e333e | 9510 | } |
560b85bb | 9511 | |
b2d03b0d | 9512 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
4726e0b0 | 9513 | |
e11ffddb VS |
9514 | /* On these chipsets we can only modify the base/size/stride |
9515 | * whilst the cursor is disabled. | |
9516 | */ | |
9517 | if (plane->cursor.base != base || | |
9518 | plane->cursor.size != size || | |
9519 | plane->cursor.cntl != cntl) { | |
dd584fc0 | 9520 | I915_WRITE_FW(CURCNTR(PIPE_A), 0); |
dd584fc0 | 9521 | I915_WRITE_FW(CURBASE(PIPE_A), base); |
dd584fc0 | 9522 | I915_WRITE_FW(CURSIZE, size); |
b2d03b0d | 9523 | I915_WRITE_FW(CURPOS(PIPE_A), pos); |
dd584fc0 | 9524 | I915_WRITE_FW(CURCNTR(PIPE_A), cntl); |
75343a44 | 9525 | |
e11ffddb VS |
9526 | plane->cursor.base = base; |
9527 | plane->cursor.size = size; | |
9528 | plane->cursor.cntl = cntl; | |
9529 | } else { | |
9530 | I915_WRITE_FW(CURPOS(PIPE_A), pos); | |
560b85bb | 9531 | } |
e11ffddb | 9532 | |
75343a44 | 9533 | POSTING_READ_FW(CURCNTR(PIPE_A)); |
b2d03b0d VS |
9534 | |
9535 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
9536 | } | |
9537 | ||
9538 | static void i845_disable_cursor(struct intel_plane *plane, | |
9539 | struct intel_crtc *crtc) | |
9540 | { | |
9541 | i845_update_cursor(plane, NULL, NULL); | |
560b85bb CW |
9542 | } |
9543 | ||
292889e1 VS |
9544 | static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state, |
9545 | const struct intel_plane_state *plane_state) | |
9546 | { | |
9547 | struct drm_i915_private *dev_priv = | |
9548 | to_i915(plane_state->base.plane->dev); | |
9549 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
292889e1 VS |
9550 | u32 cntl; |
9551 | ||
9552 | cntl = MCURSOR_GAMMA_ENABLE; | |
9553 | ||
9554 | if (HAS_DDI(dev_priv)) | |
9555 | cntl |= CURSOR_PIPE_CSC_ENABLE; | |
9556 | ||
d509e28b | 9557 | cntl |= MCURSOR_PIPE_SELECT(crtc->pipe); |
292889e1 VS |
9558 | |
9559 | switch (plane_state->base.crtc_w) { | |
9560 | case 64: | |
9561 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
9562 | break; | |
9563 | case 128: | |
9564 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
9565 | break; | |
9566 | case 256: | |
9567 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
9568 | break; | |
9569 | default: | |
9570 | MISSING_CASE(plane_state->base.crtc_w); | |
9571 | return 0; | |
9572 | } | |
9573 | ||
c2c446ad | 9574 | if (plane_state->base.rotation & DRM_MODE_ROTATE_180) |
292889e1 VS |
9575 | cntl |= CURSOR_ROTATE_180; |
9576 | ||
9577 | return cntl; | |
9578 | } | |
9579 | ||
659056f2 | 9580 | static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state) |
65a21cd6 | 9581 | { |
024faac7 VS |
9582 | struct drm_i915_private *dev_priv = |
9583 | to_i915(plane_state->base.plane->dev); | |
659056f2 VS |
9584 | int width = plane_state->base.crtc_w; |
9585 | int height = plane_state->base.crtc_h; | |
4b0e333e | 9586 | |
3637ecf0 | 9587 | if (!intel_cursor_size_ok(plane_state)) |
659056f2 | 9588 | return false; |
4398ad45 | 9589 | |
024faac7 VS |
9590 | /* Cursor width is limited to a few power-of-two sizes */ |
9591 | switch (width) { | |
659056f2 VS |
9592 | case 256: |
9593 | case 128: | |
659056f2 VS |
9594 | case 64: |
9595 | break; | |
9596 | default: | |
9597 | return false; | |
65a21cd6 | 9598 | } |
4b0e333e | 9599 | |
024faac7 VS |
9600 | /* |
9601 | * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor | |
9602 | * height from 8 lines up to the cursor width, when the | |
9603 | * cursor is not rotated. Everything else requires square | |
9604 | * cursors. | |
9605 | */ | |
9606 | if (HAS_CUR_FBC(dev_priv) && | |
a82256bc | 9607 | plane_state->base.rotation & DRM_MODE_ROTATE_0) { |
024faac7 VS |
9608 | if (height < 8 || height > width) |
9609 | return false; | |
9610 | } else { | |
9611 | if (height != width) | |
9612 | return false; | |
9613 | } | |
99d1f387 | 9614 | |
659056f2 | 9615 | return true; |
65a21cd6 JB |
9616 | } |
9617 | ||
659056f2 VS |
9618 | static int i9xx_check_cursor(struct intel_plane *plane, |
9619 | struct intel_crtc_state *crtc_state, | |
9620 | struct intel_plane_state *plane_state) | |
cda4b7d3 | 9621 | { |
659056f2 VS |
9622 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
9623 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
659056f2 | 9624 | enum pipe pipe = plane->pipe; |
659056f2 | 9625 | int ret; |
cda4b7d3 | 9626 | |
659056f2 VS |
9627 | ret = intel_check_cursor(crtc_state, plane_state); |
9628 | if (ret) | |
9629 | return ret; | |
cda4b7d3 | 9630 | |
659056f2 | 9631 | /* if we want to turn off the cursor ignore width and height */ |
1e1bb871 | 9632 | if (!fb) |
659056f2 | 9633 | return 0; |
55a08b3f | 9634 | |
659056f2 VS |
9635 | /* Check for which cursor types we support */ |
9636 | if (!i9xx_cursor_size_ok(plane_state)) { | |
9637 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", | |
9638 | plane_state->base.crtc_w, | |
9639 | plane_state->base.crtc_h); | |
9640 | return -EINVAL; | |
cda4b7d3 | 9641 | } |
cda4b7d3 | 9642 | |
1e1bb871 VS |
9643 | if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) { |
9644 | DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n", | |
9645 | fb->pitches[0], plane_state->base.crtc_w); | |
9646 | return -EINVAL; | |
659056f2 | 9647 | } |
dd584fc0 | 9648 | |
659056f2 VS |
9649 | /* |
9650 | * There's something wrong with the cursor on CHV pipe C. | |
9651 | * If it straddles the left edge of the screen then | |
9652 | * moving it away from the edge or disabling it often | |
9653 | * results in a pipe underrun, and often that can lead to | |
9654 | * dead pipe (constant underrun reported, and it scans | |
9655 | * out just a solid color). To recover from that, the | |
9656 | * display power well must be turned off and on again. | |
9657 | * Refuse the put the cursor into that compromised position. | |
9658 | */ | |
9659 | if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C && | |
9660 | plane_state->base.visible && plane_state->base.crtc_x < 0) { | |
9661 | DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); | |
9662 | return -EINVAL; | |
9663 | } | |
5efb3e28 | 9664 | |
659056f2 | 9665 | plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state); |
dd584fc0 | 9666 | |
659056f2 | 9667 | return 0; |
cda4b7d3 CW |
9668 | } |
9669 | ||
b2d03b0d VS |
9670 | static void i9xx_update_cursor(struct intel_plane *plane, |
9671 | const struct intel_crtc_state *crtc_state, | |
55a08b3f | 9672 | const struct intel_plane_state *plane_state) |
dc41c154 | 9673 | { |
cd5dcbf1 VS |
9674 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
9675 | enum pipe pipe = plane->pipe; | |
024faac7 | 9676 | u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0; |
b2d03b0d | 9677 | unsigned long irqflags; |
dc41c154 | 9678 | |
b2d03b0d | 9679 | if (plane_state && plane_state->base.visible) { |
a0864d59 | 9680 | cntl = plane_state->ctl; |
dc41c154 | 9681 | |
024faac7 VS |
9682 | if (plane_state->base.crtc_h != plane_state->base.crtc_w) |
9683 | fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1); | |
dc41c154 | 9684 | |
b2d03b0d VS |
9685 | base = intel_cursor_base(plane_state); |
9686 | pos = intel_cursor_position(plane_state); | |
9687 | } | |
9688 | ||
9689 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
9690 | ||
e11ffddb VS |
9691 | /* |
9692 | * On some platforms writing CURCNTR first will also | |
9693 | * cause CURPOS to be armed by the CURBASE write. | |
9694 | * Without the CURCNTR write the CURPOS write would | |
8753d2bc VS |
9695 | * arm itself. Thus we always start the full update |
9696 | * with a CURCNTR write. | |
9697 | * | |
9698 | * On other platforms CURPOS always requires the | |
9699 | * CURBASE write to arm the update. Additonally | |
9700 | * a write to any of the cursor register will cancel | |
9701 | * an already armed cursor update. Thus leaving out | |
9702 | * the CURBASE write after CURPOS could lead to a | |
9703 | * cursor that doesn't appear to move, or even change | |
9704 | * shape. Thus we always write CURBASE. | |
e11ffddb VS |
9705 | * |
9706 | * CURCNTR and CUR_FBC_CTL are always | |
9707 | * armed by the CURBASE write only. | |
9708 | */ | |
9709 | if (plane->cursor.base != base || | |
9710 | plane->cursor.size != fbc_ctl || | |
9711 | plane->cursor.cntl != cntl) { | |
dd584fc0 | 9712 | I915_WRITE_FW(CURCNTR(pipe), cntl); |
e11ffddb VS |
9713 | if (HAS_CUR_FBC(dev_priv)) |
9714 | I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl); | |
b2d03b0d | 9715 | I915_WRITE_FW(CURPOS(pipe), pos); |
75343a44 VS |
9716 | I915_WRITE_FW(CURBASE(pipe), base); |
9717 | ||
e11ffddb VS |
9718 | plane->cursor.base = base; |
9719 | plane->cursor.size = fbc_ctl; | |
9720 | plane->cursor.cntl = cntl; | |
dc41c154 | 9721 | } else { |
e11ffddb | 9722 | I915_WRITE_FW(CURPOS(pipe), pos); |
8753d2bc | 9723 | I915_WRITE_FW(CURBASE(pipe), base); |
dc41c154 VS |
9724 | } |
9725 | ||
dd584fc0 | 9726 | POSTING_READ_FW(CURBASE(pipe)); |
99d1f387 | 9727 | |
b2d03b0d | 9728 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
65a21cd6 JB |
9729 | } |
9730 | ||
b2d03b0d VS |
9731 | static void i9xx_disable_cursor(struct intel_plane *plane, |
9732 | struct intel_crtc *crtc) | |
cda4b7d3 | 9733 | { |
b2d03b0d | 9734 | i9xx_update_cursor(plane, NULL, NULL); |
dc41c154 VS |
9735 | } |
9736 | ||
dc41c154 | 9737 | |
79e53945 JB |
9738 | /* VESA 640x480x72Hz mode to set on the pipe */ |
9739 | static struct drm_display_mode load_detect_mode = { | |
9740 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
9741 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
9742 | }; | |
9743 | ||
a8bb6818 | 9744 | struct drm_framebuffer * |
24dbf51a CW |
9745 | intel_framebuffer_create(struct drm_i915_gem_object *obj, |
9746 | struct drm_mode_fb_cmd2 *mode_cmd) | |
d2dff872 CW |
9747 | { |
9748 | struct intel_framebuffer *intel_fb; | |
9749 | int ret; | |
9750 | ||
9751 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
dcb1394e | 9752 | if (!intel_fb) |
d2dff872 | 9753 | return ERR_PTR(-ENOMEM); |
d2dff872 | 9754 | |
24dbf51a | 9755 | ret = intel_framebuffer_init(intel_fb, obj, mode_cmd); |
dd4916c5 DV |
9756 | if (ret) |
9757 | goto err; | |
d2dff872 CW |
9758 | |
9759 | return &intel_fb->base; | |
dcb1394e | 9760 | |
dd4916c5 | 9761 | err: |
dd4916c5 | 9762 | kfree(intel_fb); |
dd4916c5 | 9763 | return ERR_PTR(ret); |
d2dff872 CW |
9764 | } |
9765 | ||
9766 | static u32 | |
9767 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
9768 | { | |
9769 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
9770 | return ALIGN(pitch, 64); | |
9771 | } | |
9772 | ||
9773 | static u32 | |
9774 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
9775 | { | |
9776 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 9777 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
9778 | } |
9779 | ||
9780 | static struct drm_framebuffer * | |
9781 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
9782 | struct drm_display_mode *mode, | |
9783 | int depth, int bpp) | |
9784 | { | |
dcb1394e | 9785 | struct drm_framebuffer *fb; |
d2dff872 | 9786 | struct drm_i915_gem_object *obj; |
0fed39bd | 9787 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 | 9788 | |
12d79d78 | 9789 | obj = i915_gem_object_create(to_i915(dev), |
d2dff872 | 9790 | intel_framebuffer_size_for_mode(mode, bpp)); |
fe3db79b CW |
9791 | if (IS_ERR(obj)) |
9792 | return ERR_CAST(obj); | |
d2dff872 CW |
9793 | |
9794 | mode_cmd.width = mode->hdisplay; | |
9795 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
9796 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
9797 | bpp); | |
5ca0c34a | 9798 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 | 9799 | |
24dbf51a | 9800 | fb = intel_framebuffer_create(obj, &mode_cmd); |
dcb1394e | 9801 | if (IS_ERR(fb)) |
f0cd5182 | 9802 | i915_gem_object_put(obj); |
dcb1394e LW |
9803 | |
9804 | return fb; | |
d2dff872 CW |
9805 | } |
9806 | ||
9807 | static struct drm_framebuffer * | |
9808 | mode_fits_in_fbdev(struct drm_device *dev, | |
9809 | struct drm_display_mode *mode) | |
9810 | { | |
0695726e | 9811 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
fac5e23e | 9812 | struct drm_i915_private *dev_priv = to_i915(dev); |
d2dff872 CW |
9813 | struct drm_i915_gem_object *obj; |
9814 | struct drm_framebuffer *fb; | |
9815 | ||
4c0e5528 | 9816 | if (!dev_priv->fbdev) |
d2dff872 CW |
9817 | return NULL; |
9818 | ||
4c0e5528 | 9819 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
9820 | return NULL; |
9821 | ||
4c0e5528 DV |
9822 | obj = dev_priv->fbdev->fb->obj; |
9823 | BUG_ON(!obj); | |
9824 | ||
8bcd4553 | 9825 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 | 9826 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
272725c7 | 9827 | fb->format->cpp[0] * 8)) |
d2dff872 CW |
9828 | return NULL; |
9829 | ||
01f2c773 | 9830 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
9831 | return NULL; |
9832 | ||
edde3617 | 9833 | drm_framebuffer_reference(fb); |
d2dff872 | 9834 | return fb; |
4520f53a DV |
9835 | #else |
9836 | return NULL; | |
9837 | #endif | |
d2dff872 CW |
9838 | } |
9839 | ||
d3a40d1b ACO |
9840 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
9841 | struct drm_crtc *crtc, | |
9842 | struct drm_display_mode *mode, | |
9843 | struct drm_framebuffer *fb, | |
9844 | int x, int y) | |
9845 | { | |
9846 | struct drm_plane_state *plane_state; | |
9847 | int hdisplay, vdisplay; | |
9848 | int ret; | |
9849 | ||
9850 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
9851 | if (IS_ERR(plane_state)) | |
9852 | return PTR_ERR(plane_state); | |
9853 | ||
9854 | if (mode) | |
196cd5d3 | 9855 | drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay); |
d3a40d1b ACO |
9856 | else |
9857 | hdisplay = vdisplay = 0; | |
9858 | ||
9859 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
9860 | if (ret) | |
9861 | return ret; | |
9862 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
9863 | plane_state->crtc_x = 0; | |
9864 | plane_state->crtc_y = 0; | |
9865 | plane_state->crtc_w = hdisplay; | |
9866 | plane_state->crtc_h = vdisplay; | |
9867 | plane_state->src_x = x << 16; | |
9868 | plane_state->src_y = y << 16; | |
9869 | plane_state->src_w = hdisplay << 16; | |
9870 | plane_state->src_h = vdisplay << 16; | |
9871 | ||
9872 | return 0; | |
9873 | } | |
9874 | ||
6c5ed5ae ML |
9875 | int intel_get_load_detect_pipe(struct drm_connector *connector, |
9876 | struct drm_display_mode *mode, | |
9877 | struct intel_load_detect_pipe *old, | |
9878 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
9879 | { |
9880 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
9881 | struct intel_encoder *intel_encoder = |
9882 | intel_attached_encoder(connector); | |
79e53945 | 9883 | struct drm_crtc *possible_crtc; |
4ef69c7a | 9884 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
9885 | struct drm_crtc *crtc = NULL; |
9886 | struct drm_device *dev = encoder->dev; | |
0f0f74bc | 9887 | struct drm_i915_private *dev_priv = to_i915(dev); |
94352cf9 | 9888 | struct drm_framebuffer *fb; |
51fd371b | 9889 | struct drm_mode_config *config = &dev->mode_config; |
edde3617 | 9890 | struct drm_atomic_state *state = NULL, *restore_state = NULL; |
944b0c76 | 9891 | struct drm_connector_state *connector_state; |
4be07317 | 9892 | struct intel_crtc_state *crtc_state; |
51fd371b | 9893 | int ret, i = -1; |
79e53945 | 9894 | |
d2dff872 | 9895 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 9896 | connector->base.id, connector->name, |
8e329a03 | 9897 | encoder->base.id, encoder->name); |
d2dff872 | 9898 | |
edde3617 ML |
9899 | old->restore_state = NULL; |
9900 | ||
6c5ed5ae | 9901 | WARN_ON(!drm_modeset_is_locked(&config->connection_mutex)); |
6e9f798d | 9902 | |
79e53945 JB |
9903 | /* |
9904 | * Algorithm gets a little messy: | |
7a5e4805 | 9905 | * |
79e53945 JB |
9906 | * - if the connector already has an assigned crtc, use it (but make |
9907 | * sure it's on first) | |
7a5e4805 | 9908 | * |
79e53945 JB |
9909 | * - try to find the first unused crtc that can drive this connector, |
9910 | * and use that if we find one | |
79e53945 JB |
9911 | */ |
9912 | ||
9913 | /* See if we already have a CRTC for this connector */ | |
edde3617 ML |
9914 | if (connector->state->crtc) { |
9915 | crtc = connector->state->crtc; | |
8261b191 | 9916 | |
51fd371b | 9917 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 9918 | if (ret) |
ad3c558f | 9919 | goto fail; |
8261b191 CW |
9920 | |
9921 | /* Make sure the crtc and connector are running */ | |
edde3617 | 9922 | goto found; |
79e53945 JB |
9923 | } |
9924 | ||
9925 | /* Find an unused one (if possible) */ | |
70e1e0ec | 9926 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
9927 | i++; |
9928 | if (!(encoder->possible_crtcs & (1 << i))) | |
9929 | continue; | |
edde3617 ML |
9930 | |
9931 | ret = drm_modeset_lock(&possible_crtc->mutex, ctx); | |
9932 | if (ret) | |
9933 | goto fail; | |
9934 | ||
9935 | if (possible_crtc->state->enable) { | |
9936 | drm_modeset_unlock(&possible_crtc->mutex); | |
a459249c | 9937 | continue; |
edde3617 | 9938 | } |
a459249c VS |
9939 | |
9940 | crtc = possible_crtc; | |
9941 | break; | |
79e53945 JB |
9942 | } |
9943 | ||
9944 | /* | |
9945 | * If we didn't find an unused CRTC, don't use any. | |
9946 | */ | |
9947 | if (!crtc) { | |
7173188d | 9948 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
f4bf77b4 | 9949 | ret = -ENODEV; |
ad3c558f | 9950 | goto fail; |
79e53945 JB |
9951 | } |
9952 | ||
edde3617 ML |
9953 | found: |
9954 | intel_crtc = to_intel_crtc(crtc); | |
9955 | ||
4d02e2de DV |
9956 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
9957 | if (ret) | |
ad3c558f | 9958 | goto fail; |
79e53945 | 9959 | |
83a57153 | 9960 | state = drm_atomic_state_alloc(dev); |
edde3617 ML |
9961 | restore_state = drm_atomic_state_alloc(dev); |
9962 | if (!state || !restore_state) { | |
9963 | ret = -ENOMEM; | |
9964 | goto fail; | |
9965 | } | |
83a57153 ACO |
9966 | |
9967 | state->acquire_ctx = ctx; | |
edde3617 | 9968 | restore_state->acquire_ctx = ctx; |
83a57153 | 9969 | |
944b0c76 ACO |
9970 | connector_state = drm_atomic_get_connector_state(state, connector); |
9971 | if (IS_ERR(connector_state)) { | |
9972 | ret = PTR_ERR(connector_state); | |
9973 | goto fail; | |
9974 | } | |
9975 | ||
edde3617 ML |
9976 | ret = drm_atomic_set_crtc_for_connector(connector_state, crtc); |
9977 | if (ret) | |
9978 | goto fail; | |
944b0c76 | 9979 | |
4be07317 ACO |
9980 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
9981 | if (IS_ERR(crtc_state)) { | |
9982 | ret = PTR_ERR(crtc_state); | |
9983 | goto fail; | |
9984 | } | |
9985 | ||
49d6fa21 | 9986 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 9987 | |
6492711d CW |
9988 | if (!mode) |
9989 | mode = &load_detect_mode; | |
79e53945 | 9990 | |
d2dff872 CW |
9991 | /* We need a framebuffer large enough to accommodate all accesses |
9992 | * that the plane may generate whilst we perform load detection. | |
9993 | * We can not rely on the fbcon either being present (we get called | |
9994 | * during its initialisation to detect all boot displays, or it may | |
9995 | * not even exist) or that it is large enough to satisfy the | |
9996 | * requested mode. | |
9997 | */ | |
94352cf9 DV |
9998 | fb = mode_fits_in_fbdev(dev, mode); |
9999 | if (fb == NULL) { | |
d2dff872 | 10000 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 | 10001 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
d2dff872 CW |
10002 | } else |
10003 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 10004 | if (IS_ERR(fb)) { |
d2dff872 | 10005 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
f4bf77b4 | 10006 | ret = PTR_ERR(fb); |
412b61d8 | 10007 | goto fail; |
79e53945 | 10008 | } |
79e53945 | 10009 | |
d3a40d1b ACO |
10010 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
10011 | if (ret) | |
10012 | goto fail; | |
10013 | ||
edde3617 ML |
10014 | drm_framebuffer_unreference(fb); |
10015 | ||
10016 | ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode); | |
10017 | if (ret) | |
10018 | goto fail; | |
10019 | ||
10020 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); | |
10021 | if (!ret) | |
10022 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc)); | |
10023 | if (!ret) | |
10024 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary)); | |
10025 | if (ret) { | |
10026 | DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret); | |
10027 | goto fail; | |
10028 | } | |
8c7b5ccb | 10029 | |
3ba86073 ML |
10030 | ret = drm_atomic_commit(state); |
10031 | if (ret) { | |
6492711d | 10032 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
412b61d8 | 10033 | goto fail; |
79e53945 | 10034 | } |
edde3617 ML |
10035 | |
10036 | old->restore_state = restore_state; | |
7abbd11f | 10037 | drm_atomic_state_put(state); |
7173188d | 10038 | |
79e53945 | 10039 | /* let the connector get through one full cycle before testing */ |
0f0f74bc | 10040 | intel_wait_for_vblank(dev_priv, intel_crtc->pipe); |
7173188d | 10041 | return true; |
412b61d8 | 10042 | |
ad3c558f | 10043 | fail: |
7fb71c8f CW |
10044 | if (state) { |
10045 | drm_atomic_state_put(state); | |
10046 | state = NULL; | |
10047 | } | |
10048 | if (restore_state) { | |
10049 | drm_atomic_state_put(restore_state); | |
10050 | restore_state = NULL; | |
10051 | } | |
83a57153 | 10052 | |
6c5ed5ae ML |
10053 | if (ret == -EDEADLK) |
10054 | return ret; | |
51fd371b | 10055 | |
412b61d8 | 10056 | return false; |
79e53945 JB |
10057 | } |
10058 | ||
d2434ab7 | 10059 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
10060 | struct intel_load_detect_pipe *old, |
10061 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 10062 | { |
d2434ab7 DV |
10063 | struct intel_encoder *intel_encoder = |
10064 | intel_attached_encoder(connector); | |
4ef69c7a | 10065 | struct drm_encoder *encoder = &intel_encoder->base; |
edde3617 | 10066 | struct drm_atomic_state *state = old->restore_state; |
d3a40d1b | 10067 | int ret; |
79e53945 | 10068 | |
d2dff872 | 10069 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10070 | connector->base.id, connector->name, |
8e329a03 | 10071 | encoder->base.id, encoder->name); |
d2dff872 | 10072 | |
edde3617 | 10073 | if (!state) |
0622a53c | 10074 | return; |
79e53945 | 10075 | |
581e49fe | 10076 | ret = drm_atomic_helper_commit_duplicated_state(state, ctx); |
0853695c | 10077 | if (ret) |
edde3617 | 10078 | DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret); |
0853695c | 10079 | drm_atomic_state_put(state); |
79e53945 JB |
10080 | } |
10081 | ||
da4a1efa | 10082 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 10083 | const struct intel_crtc_state *pipe_config) |
da4a1efa | 10084 | { |
fac5e23e | 10085 | struct drm_i915_private *dev_priv = to_i915(dev); |
da4a1efa VS |
10086 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
10087 | ||
10088 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 10089 | return dev_priv->vbt.lvds_ssc_freq; |
6e266956 | 10090 | else if (HAS_PCH_SPLIT(dev_priv)) |
da4a1efa | 10091 | return 120000; |
5db94019 | 10092 | else if (!IS_GEN2(dev_priv)) |
da4a1efa VS |
10093 | return 96000; |
10094 | else | |
10095 | return 48000; | |
10096 | } | |
10097 | ||
79e53945 | 10098 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 10099 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 10100 | struct intel_crtc_state *pipe_config) |
79e53945 | 10101 | { |
f1f644dc | 10102 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 10103 | struct drm_i915_private *dev_priv = to_i915(dev); |
f1f644dc | 10104 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 10105 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 | 10106 | u32 fp; |
9e2c8475 | 10107 | struct dpll clock; |
dccbea3b | 10108 | int port_clock; |
da4a1efa | 10109 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
10110 | |
10111 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 10112 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 10113 | else |
293623f7 | 10114 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
10115 | |
10116 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
9b1e14f4 | 10117 | if (IS_PINEVIEW(dev_priv)) { |
f2b115e6 AJ |
10118 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; |
10119 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
10120 | } else { |
10121 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
10122 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
10123 | } | |
10124 | ||
5db94019 | 10125 | if (!IS_GEN2(dev_priv)) { |
9b1e14f4 | 10126 | if (IS_PINEVIEW(dev_priv)) |
f2b115e6 AJ |
10127 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> |
10128 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
10129 | else |
10130 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
10131 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
10132 | ||
10133 | switch (dpll & DPLL_MODE_MASK) { | |
10134 | case DPLLB_MODE_DAC_SERIAL: | |
10135 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
10136 | 5 : 10; | |
10137 | break; | |
10138 | case DPLLB_MODE_LVDS: | |
10139 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
10140 | 7 : 14; | |
10141 | break; | |
10142 | default: | |
28c97730 | 10143 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 10144 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 10145 | return; |
79e53945 JB |
10146 | } |
10147 | ||
9b1e14f4 | 10148 | if (IS_PINEVIEW(dev_priv)) |
dccbea3b | 10149 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 10150 | else |
dccbea3b | 10151 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 10152 | } else { |
50a0bc90 | 10153 | u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS); |
b1c560d1 | 10154 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
10155 | |
10156 | if (is_lvds) { | |
10157 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
10158 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
10159 | |
10160 | if (lvds & LVDS_CLKB_POWER_UP) | |
10161 | clock.p2 = 7; | |
10162 | else | |
10163 | clock.p2 = 14; | |
79e53945 JB |
10164 | } else { |
10165 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
10166 | clock.p1 = 2; | |
10167 | else { | |
10168 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
10169 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
10170 | } | |
10171 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
10172 | clock.p2 = 4; | |
10173 | else | |
10174 | clock.p2 = 2; | |
79e53945 | 10175 | } |
da4a1efa | 10176 | |
dccbea3b | 10177 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
10178 | } |
10179 | ||
18442d08 VS |
10180 | /* |
10181 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 10182 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
10183 | * encoder's get_config() function. |
10184 | */ | |
dccbea3b | 10185 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
10186 | } |
10187 | ||
6878da05 VS |
10188 | int intel_dotclock_calculate(int link_freq, |
10189 | const struct intel_link_m_n *m_n) | |
f1f644dc | 10190 | { |
f1f644dc JB |
10191 | /* |
10192 | * The calculation for the data clock is: | |
1041a02f | 10193 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 10194 | * But we want to avoid losing precison if possible, so: |
1041a02f | 10195 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
10196 | * |
10197 | * and the link clock is simpler: | |
1041a02f | 10198 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
10199 | */ |
10200 | ||
6878da05 VS |
10201 | if (!m_n->link_n) |
10202 | return 0; | |
f1f644dc | 10203 | |
6878da05 VS |
10204 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
10205 | } | |
f1f644dc | 10206 | |
18442d08 | 10207 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 10208 | struct intel_crtc_state *pipe_config) |
6878da05 | 10209 | { |
e3b247da | 10210 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
79e53945 | 10211 | |
18442d08 VS |
10212 | /* read out port_clock from the DPLL */ |
10213 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 10214 | |
f1f644dc | 10215 | /* |
e3b247da VS |
10216 | * In case there is an active pipe without active ports, |
10217 | * we may need some idea for the dotclock anyway. | |
10218 | * Calculate one based on the FDI configuration. | |
79e53945 | 10219 | */ |
2d112de7 | 10220 | pipe_config->base.adjusted_mode.crtc_clock = |
21a727b3 | 10221 | intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
18442d08 | 10222 | &pipe_config->fdi_m_n); |
79e53945 JB |
10223 | } |
10224 | ||
10225 | /** Returns the currently programmed mode of the given pipe. */ | |
10226 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
10227 | struct drm_crtc *crtc) | |
10228 | { | |
fac5e23e | 10229 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 10230 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 10231 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 10232 | struct drm_display_mode *mode; |
3f36b937 | 10233 | struct intel_crtc_state *pipe_config; |
fe2b8f9d PZ |
10234 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
10235 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
10236 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
10237 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 10238 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
10239 | |
10240 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
10241 | if (!mode) | |
10242 | return NULL; | |
10243 | ||
3f36b937 TU |
10244 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
10245 | if (!pipe_config) { | |
10246 | kfree(mode); | |
10247 | return NULL; | |
10248 | } | |
10249 | ||
f1f644dc JB |
10250 | /* |
10251 | * Construct a pipe_config sufficient for getting the clock info | |
10252 | * back out of crtc_clock_get. | |
10253 | * | |
10254 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
10255 | * to use a real value here instead. | |
10256 | */ | |
3f36b937 TU |
10257 | pipe_config->cpu_transcoder = (enum transcoder) pipe; |
10258 | pipe_config->pixel_multiplier = 1; | |
10259 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe)); | |
10260 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
10261 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
10262 | i9xx_crtc_clock_get(intel_crtc, pipe_config); | |
10263 | ||
10264 | mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier; | |
79e53945 JB |
10265 | mode->hdisplay = (htot & 0xffff) + 1; |
10266 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
10267 | mode->hsync_start = (hsync & 0xffff) + 1; | |
10268 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
10269 | mode->vdisplay = (vtot & 0xffff) + 1; | |
10270 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
10271 | mode->vsync_start = (vsync & 0xffff) + 1; | |
10272 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
10273 | ||
10274 | drm_mode_set_name(mode); | |
79e53945 | 10275 | |
3f36b937 TU |
10276 | kfree(pipe_config); |
10277 | ||
79e53945 JB |
10278 | return mode; |
10279 | } | |
10280 | ||
10281 | static void intel_crtc_destroy(struct drm_crtc *crtc) | |
10282 | { | |
10283 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10284 | ||
10285 | drm_crtc_cleanup(crtc); | |
10286 | kfree(intel_crtc); | |
10287 | } | |
10288 | ||
5a21b665 DV |
10289 | /** |
10290 | * intel_wm_need_update - Check whether watermarks need updating | |
10291 | * @plane: drm plane | |
10292 | * @state: new plane state | |
10293 | * | |
10294 | * Check current plane state versus the new one to determine whether | |
10295 | * watermarks need to be recalculated. | |
10296 | * | |
10297 | * Returns true or false. | |
10298 | */ | |
10299 | static bool intel_wm_need_update(struct drm_plane *plane, | |
10300 | struct drm_plane_state *state) | |
10301 | { | |
10302 | struct intel_plane_state *new = to_intel_plane_state(state); | |
10303 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); | |
10304 | ||
10305 | /* Update watermarks on tiling or size changes. */ | |
936e71e3 | 10306 | if (new->base.visible != cur->base.visible) |
5a21b665 DV |
10307 | return true; |
10308 | ||
10309 | if (!cur->base.fb || !new->base.fb) | |
10310 | return false; | |
10311 | ||
bae781b2 | 10312 | if (cur->base.fb->modifier != new->base.fb->modifier || |
5a21b665 | 10313 | cur->base.rotation != new->base.rotation || |
936e71e3 VS |
10314 | drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) || |
10315 | drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) || | |
10316 | drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) || | |
10317 | drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst)) | |
5a21b665 DV |
10318 | return true; |
10319 | ||
10320 | return false; | |
10321 | } | |
10322 | ||
10323 | static bool needs_scaling(struct intel_plane_state *state) | |
10324 | { | |
936e71e3 VS |
10325 | int src_w = drm_rect_width(&state->base.src) >> 16; |
10326 | int src_h = drm_rect_height(&state->base.src) >> 16; | |
10327 | int dst_w = drm_rect_width(&state->base.dst); | |
10328 | int dst_h = drm_rect_height(&state->base.dst); | |
5a21b665 DV |
10329 | |
10330 | return (src_w != dst_w || src_h != dst_h); | |
10331 | } | |
d21fbe87 | 10332 | |
da20eabd ML |
10333 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
10334 | struct drm_plane_state *plane_state) | |
10335 | { | |
ab1d3a0e | 10336 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
da20eabd ML |
10337 | struct drm_crtc *crtc = crtc_state->crtc; |
10338 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e9728bd8 | 10339 | struct intel_plane *plane = to_intel_plane(plane_state->plane); |
da20eabd | 10340 | struct drm_device *dev = crtc->dev; |
ed4a6a7c | 10341 | struct drm_i915_private *dev_priv = to_i915(dev); |
da20eabd | 10342 | struct intel_plane_state *old_plane_state = |
e9728bd8 | 10343 | to_intel_plane_state(plane->base.state); |
da20eabd ML |
10344 | bool mode_changed = needs_modeset(crtc_state); |
10345 | bool was_crtc_enabled = crtc->state->active; | |
10346 | bool is_crtc_enabled = crtc_state->active; | |
da20eabd ML |
10347 | bool turn_off, turn_on, visible, was_visible; |
10348 | struct drm_framebuffer *fb = plane_state->fb; | |
78108b7c | 10349 | int ret; |
da20eabd | 10350 | |
e9728bd8 | 10351 | if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) { |
da20eabd ML |
10352 | ret = skl_update_scaler_plane( |
10353 | to_intel_crtc_state(crtc_state), | |
10354 | to_intel_plane_state(plane_state)); | |
10355 | if (ret) | |
10356 | return ret; | |
10357 | } | |
10358 | ||
936e71e3 | 10359 | was_visible = old_plane_state->base.visible; |
1d4258db | 10360 | visible = plane_state->visible; |
da20eabd ML |
10361 | |
10362 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
10363 | was_visible = false; | |
10364 | ||
35c08f43 ML |
10365 | /* |
10366 | * Visibility is calculated as if the crtc was on, but | |
10367 | * after scaler setup everything depends on it being off | |
10368 | * when the crtc isn't active. | |
f818ffea VS |
10369 | * |
10370 | * FIXME this is wrong for watermarks. Watermarks should also | |
10371 | * be computed as if the pipe would be active. Perhaps move | |
10372 | * per-plane wm computation to the .check_plane() hook, and | |
10373 | * only combine the results from all planes in the current place? | |
35c08f43 | 10374 | */ |
e9728bd8 | 10375 | if (!is_crtc_enabled) { |
1d4258db | 10376 | plane_state->visible = visible = false; |
e9728bd8 VS |
10377 | to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id); |
10378 | } | |
da20eabd ML |
10379 | |
10380 | if (!was_visible && !visible) | |
10381 | return 0; | |
10382 | ||
e8861675 ML |
10383 | if (fb != old_plane_state->base.fb) |
10384 | pipe_config->fb_changed = true; | |
10385 | ||
da20eabd ML |
10386 | turn_off = was_visible && (!visible || mode_changed); |
10387 | turn_on = visible && (!was_visible || mode_changed); | |
10388 | ||
72660ce0 | 10389 | DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n", |
e9728bd8 VS |
10390 | intel_crtc->base.base.id, intel_crtc->base.name, |
10391 | plane->base.base.id, plane->base.name, | |
72660ce0 | 10392 | fb ? fb->base.id : -1); |
da20eabd | 10393 | |
72660ce0 | 10394 | DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n", |
e9728bd8 | 10395 | plane->base.base.id, plane->base.name, |
72660ce0 | 10396 | was_visible, visible, |
da20eabd ML |
10397 | turn_off, turn_on, mode_changed); |
10398 | ||
caed361d | 10399 | if (turn_on) { |
04548cba | 10400 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) |
b4ede6df | 10401 | pipe_config->update_wm_pre = true; |
caed361d VS |
10402 | |
10403 | /* must disable cxsr around plane enable/disable */ | |
e9728bd8 | 10404 | if (plane->id != PLANE_CURSOR) |
caed361d VS |
10405 | pipe_config->disable_cxsr = true; |
10406 | } else if (turn_off) { | |
04548cba | 10407 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) |
b4ede6df | 10408 | pipe_config->update_wm_post = true; |
92826fcd | 10409 | |
852eb00d | 10410 | /* must disable cxsr around plane enable/disable */ |
e9728bd8 | 10411 | if (plane->id != PLANE_CURSOR) |
ab1d3a0e | 10412 | pipe_config->disable_cxsr = true; |
e9728bd8 | 10413 | } else if (intel_wm_need_update(&plane->base, plane_state)) { |
04548cba | 10414 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) { |
b4ede6df VS |
10415 | /* FIXME bollocks */ |
10416 | pipe_config->update_wm_pre = true; | |
10417 | pipe_config->update_wm_post = true; | |
10418 | } | |
852eb00d | 10419 | } |
da20eabd | 10420 | |
8be6ca85 | 10421 | if (visible || was_visible) |
e9728bd8 | 10422 | pipe_config->fb_bits |= plane->frontbuffer_bit; |
a9ff8714 | 10423 | |
31ae71fc ML |
10424 | /* |
10425 | * WaCxSRDisabledForSpriteScaling:ivb | |
10426 | * | |
10427 | * cstate->update_wm was already set above, so this flag will | |
10428 | * take effect when we commit and program watermarks. | |
10429 | */ | |
e9728bd8 | 10430 | if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) && |
31ae71fc ML |
10431 | needs_scaling(to_intel_plane_state(plane_state)) && |
10432 | !needs_scaling(old_plane_state)) | |
10433 | pipe_config->disable_lp_wm = true; | |
d21fbe87 | 10434 | |
da20eabd ML |
10435 | return 0; |
10436 | } | |
10437 | ||
6d3a1ce7 ML |
10438 | static bool encoders_cloneable(const struct intel_encoder *a, |
10439 | const struct intel_encoder *b) | |
10440 | { | |
10441 | /* masks could be asymmetric, so check both ways */ | |
10442 | return a == b || (a->cloneable & (1 << b->type) && | |
10443 | b->cloneable & (1 << a->type)); | |
10444 | } | |
10445 | ||
10446 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
10447 | struct intel_crtc *crtc, | |
10448 | struct intel_encoder *encoder) | |
10449 | { | |
10450 | struct intel_encoder *source_encoder; | |
10451 | struct drm_connector *connector; | |
10452 | struct drm_connector_state *connector_state; | |
10453 | int i; | |
10454 | ||
aa5e9b47 | 10455 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
6d3a1ce7 ML |
10456 | if (connector_state->crtc != &crtc->base) |
10457 | continue; | |
10458 | ||
10459 | source_encoder = | |
10460 | to_intel_encoder(connector_state->best_encoder); | |
10461 | if (!encoders_cloneable(encoder, source_encoder)) | |
10462 | return false; | |
10463 | } | |
10464 | ||
10465 | return true; | |
10466 | } | |
10467 | ||
6d3a1ce7 ML |
10468 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, |
10469 | struct drm_crtc_state *crtc_state) | |
10470 | { | |
cf5a15be | 10471 | struct drm_device *dev = crtc->dev; |
fac5e23e | 10472 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d3a1ce7 | 10473 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
10474 | struct intel_crtc_state *pipe_config = |
10475 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 10476 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 10477 | int ret; |
6d3a1ce7 ML |
10478 | bool mode_changed = needs_modeset(crtc_state); |
10479 | ||
852eb00d | 10480 | if (mode_changed && !crtc_state->active) |
caed361d | 10481 | pipe_config->update_wm_post = true; |
eddfcbcd | 10482 | |
ad421372 ML |
10483 | if (mode_changed && crtc_state->enable && |
10484 | dev_priv->display.crtc_compute_clock && | |
8106ddbd | 10485 | !WARN_ON(pipe_config->shared_dpll)) { |
ad421372 ML |
10486 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, |
10487 | pipe_config); | |
10488 | if (ret) | |
10489 | return ret; | |
10490 | } | |
10491 | ||
82cf435b LL |
10492 | if (crtc_state->color_mgmt_changed) { |
10493 | ret = intel_color_check(crtc, crtc_state); | |
10494 | if (ret) | |
10495 | return ret; | |
e7852a4b LL |
10496 | |
10497 | /* | |
10498 | * Changing color management on Intel hardware is | |
10499 | * handled as part of planes update. | |
10500 | */ | |
10501 | crtc_state->planes_changed = true; | |
82cf435b LL |
10502 | } |
10503 | ||
e435d6e5 | 10504 | ret = 0; |
86c8bbbe | 10505 | if (dev_priv->display.compute_pipe_wm) { |
e3bddded | 10506 | ret = dev_priv->display.compute_pipe_wm(pipe_config); |
ed4a6a7c MR |
10507 | if (ret) { |
10508 | DRM_DEBUG_KMS("Target pipe watermarks are invalid\n"); | |
10509 | return ret; | |
10510 | } | |
10511 | } | |
10512 | ||
10513 | if (dev_priv->display.compute_intermediate_wm && | |
10514 | !to_intel_atomic_state(state)->skip_intermediate_wm) { | |
10515 | if (WARN_ON(!dev_priv->display.compute_pipe_wm)) | |
10516 | return 0; | |
10517 | ||
10518 | /* | |
10519 | * Calculate 'intermediate' watermarks that satisfy both the | |
10520 | * old state and the new state. We can program these | |
10521 | * immediately. | |
10522 | */ | |
6315b5d3 | 10523 | ret = dev_priv->display.compute_intermediate_wm(dev, |
ed4a6a7c MR |
10524 | intel_crtc, |
10525 | pipe_config); | |
10526 | if (ret) { | |
10527 | DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n"); | |
86c8bbbe | 10528 | return ret; |
ed4a6a7c | 10529 | } |
e3d5457c VS |
10530 | } else if (dev_priv->display.compute_intermediate_wm) { |
10531 | if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9) | |
10532 | pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal; | |
86c8bbbe MR |
10533 | } |
10534 | ||
6315b5d3 | 10535 | if (INTEL_GEN(dev_priv) >= 9) { |
e435d6e5 ML |
10536 | if (mode_changed) |
10537 | ret = skl_update_scaler_crtc(pipe_config); | |
10538 | ||
73b0ca8e MK |
10539 | if (!ret) |
10540 | ret = skl_check_pipe_max_pixel_rate(intel_crtc, | |
10541 | pipe_config); | |
e435d6e5 | 10542 | if (!ret) |
6ebc6923 | 10543 | ret = intel_atomic_setup_scalers(dev_priv, intel_crtc, |
e435d6e5 ML |
10544 | pipe_config); |
10545 | } | |
10546 | ||
10547 | return ret; | |
6d3a1ce7 ML |
10548 | } |
10549 | ||
65b38e0d | 10550 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
5a21b665 DV |
10551 | .atomic_begin = intel_begin_crtc_commit, |
10552 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 10553 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
10554 | }; |
10555 | ||
d29b2f9d ACO |
10556 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
10557 | { | |
10558 | struct intel_connector *connector; | |
f9e905ca | 10559 | struct drm_connector_list_iter conn_iter; |
d29b2f9d | 10560 | |
f9e905ca DV |
10561 | drm_connector_list_iter_begin(dev, &conn_iter); |
10562 | for_each_intel_connector_iter(connector, &conn_iter) { | |
8863dc7f DV |
10563 | if (connector->base.state->crtc) |
10564 | drm_connector_unreference(&connector->base); | |
10565 | ||
d29b2f9d ACO |
10566 | if (connector->base.encoder) { |
10567 | connector->base.state->best_encoder = | |
10568 | connector->base.encoder; | |
10569 | connector->base.state->crtc = | |
10570 | connector->base.encoder->crtc; | |
8863dc7f DV |
10571 | |
10572 | drm_connector_reference(&connector->base); | |
d29b2f9d ACO |
10573 | } else { |
10574 | connector->base.state->best_encoder = NULL; | |
10575 | connector->base.state->crtc = NULL; | |
10576 | } | |
10577 | } | |
f9e905ca | 10578 | drm_connector_list_iter_end(&conn_iter); |
d29b2f9d ACO |
10579 | } |
10580 | ||
050f7aeb | 10581 | static void |
eba905b2 | 10582 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 10583 | struct intel_crtc_state *pipe_config) |
050f7aeb | 10584 | { |
6a2a5c5d | 10585 | const struct drm_display_info *info = &connector->base.display_info; |
050f7aeb DV |
10586 | int bpp = pipe_config->pipe_bpp; |
10587 | ||
10588 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
6a2a5c5d VS |
10589 | connector->base.base.id, |
10590 | connector->base.name); | |
050f7aeb DV |
10591 | |
10592 | /* Don't use an invalid EDID bpc value */ | |
6a2a5c5d | 10593 | if (info->bpc != 0 && info->bpc * 3 < bpp) { |
050f7aeb | 10594 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", |
6a2a5c5d VS |
10595 | bpp, info->bpc * 3); |
10596 | pipe_config->pipe_bpp = info->bpc * 3; | |
050f7aeb DV |
10597 | } |
10598 | ||
196f954e | 10599 | /* Clamp bpp to 8 on screens without EDID 1.4 */ |
6a2a5c5d | 10600 | if (info->bpc == 0 && bpp > 24) { |
196f954e MK |
10601 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", |
10602 | bpp); | |
10603 | pipe_config->pipe_bpp = 24; | |
050f7aeb DV |
10604 | } |
10605 | } | |
10606 | ||
4e53c2e0 | 10607 | static int |
050f7aeb | 10608 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 10609 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 10610 | { |
9beb5fea | 10611 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1486017f | 10612 | struct drm_atomic_state *state; |
da3ced29 ACO |
10613 | struct drm_connector *connector; |
10614 | struct drm_connector_state *connector_state; | |
1486017f | 10615 | int bpp, i; |
4e53c2e0 | 10616 | |
9beb5fea TU |
10617 | if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
10618 | IS_CHERRYVIEW(dev_priv))) | |
4e53c2e0 | 10619 | bpp = 10*3; |
9beb5fea | 10620 | else if (INTEL_GEN(dev_priv) >= 5) |
d328c9d7 DV |
10621 | bpp = 12*3; |
10622 | else | |
10623 | bpp = 8*3; | |
10624 | ||
4e53c2e0 | 10625 | |
4e53c2e0 DV |
10626 | pipe_config->pipe_bpp = bpp; |
10627 | ||
1486017f ACO |
10628 | state = pipe_config->base.state; |
10629 | ||
4e53c2e0 | 10630 | /* Clamp display bpp to EDID value */ |
aa5e9b47 | 10631 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
da3ced29 | 10632 | if (connector_state->crtc != &crtc->base) |
4e53c2e0 DV |
10633 | continue; |
10634 | ||
da3ced29 ACO |
10635 | connected_sink_compute_bpp(to_intel_connector(connector), |
10636 | pipe_config); | |
4e53c2e0 DV |
10637 | } |
10638 | ||
10639 | return bpp; | |
10640 | } | |
10641 | ||
644db711 DV |
10642 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
10643 | { | |
10644 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
10645 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 10646 | mode->crtc_clock, |
644db711 DV |
10647 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
10648 | mode->crtc_hsync_end, mode->crtc_htotal, | |
10649 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
10650 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
10651 | } | |
10652 | ||
f6982332 TU |
10653 | static inline void |
10654 | intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id, | |
a4309657 | 10655 | unsigned int lane_count, struct intel_link_m_n *m_n) |
f6982332 | 10656 | { |
a4309657 TU |
10657 | DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
10658 | id, lane_count, | |
f6982332 TU |
10659 | m_n->gmch_m, m_n->gmch_n, |
10660 | m_n->link_m, m_n->link_n, m_n->tu); | |
10661 | } | |
10662 | ||
c0b03411 | 10663 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 10664 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
10665 | const char *context) |
10666 | { | |
6a60cd87 | 10667 | struct drm_device *dev = crtc->base.dev; |
4f8036a2 | 10668 | struct drm_i915_private *dev_priv = to_i915(dev); |
6a60cd87 CK |
10669 | struct drm_plane *plane; |
10670 | struct intel_plane *intel_plane; | |
10671 | struct intel_plane_state *state; | |
10672 | struct drm_framebuffer *fb; | |
10673 | ||
66766e4f TU |
10674 | DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n", |
10675 | crtc->base.base.id, crtc->base.name, context); | |
c0b03411 | 10676 | |
2c89429e TU |
10677 | DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n", |
10678 | transcoder_name(pipe_config->cpu_transcoder), | |
c0b03411 | 10679 | pipe_config->pipe_bpp, pipe_config->dither); |
a4309657 TU |
10680 | |
10681 | if (pipe_config->has_pch_encoder) | |
10682 | intel_dump_m_n_config(pipe_config, "fdi", | |
10683 | pipe_config->fdi_lanes, | |
10684 | &pipe_config->fdi_m_n); | |
f6982332 | 10685 | |
b22ca995 SS |
10686 | if (pipe_config->ycbcr420) |
10687 | DRM_DEBUG_KMS("YCbCr 4:2:0 output enabled\n"); | |
10688 | ||
f6982332 | 10689 | if (intel_crtc_has_dp_encoder(pipe_config)) { |
a4309657 TU |
10690 | intel_dump_m_n_config(pipe_config, "dp m_n", |
10691 | pipe_config->lane_count, &pipe_config->dp_m_n); | |
d806e682 TU |
10692 | if (pipe_config->has_drrs) |
10693 | intel_dump_m_n_config(pipe_config, "dp m2_n2", | |
10694 | pipe_config->lane_count, | |
10695 | &pipe_config->dp_m2_n2); | |
f6982332 | 10696 | } |
b95af8be | 10697 | |
55072d19 | 10698 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
2c89429e | 10699 | pipe_config->has_audio, pipe_config->has_infoframe); |
55072d19 | 10700 | |
c0b03411 | 10701 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 10702 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 10703 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
10704 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
10705 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
a7d1b3f4 | 10706 | DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n", |
2c89429e | 10707 | pipe_config->port_clock, |
a7d1b3f4 VS |
10708 | pipe_config->pipe_src_w, pipe_config->pipe_src_h, |
10709 | pipe_config->pixel_rate); | |
dd2f616d TU |
10710 | |
10711 | if (INTEL_GEN(dev_priv) >= 9) | |
10712 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", | |
10713 | crtc->num_scalers, | |
10714 | pipe_config->scaler_state.scaler_users, | |
10715 | pipe_config->scaler_state.scaler_id); | |
a74f8375 TU |
10716 | |
10717 | if (HAS_GMCH_DISPLAY(dev_priv)) | |
10718 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", | |
10719 | pipe_config->gmch_pfit.control, | |
10720 | pipe_config->gmch_pfit.pgm_ratios, | |
10721 | pipe_config->gmch_pfit.lvds_border_bits); | |
10722 | else | |
10723 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", | |
10724 | pipe_config->pch_pfit.pos, | |
10725 | pipe_config->pch_pfit.size, | |
08c4d7fc | 10726 | enableddisabled(pipe_config->pch_pfit.enabled)); |
a74f8375 | 10727 | |
2c89429e TU |
10728 | DRM_DEBUG_KMS("ips: %i, double wide: %i\n", |
10729 | pipe_config->ips_enabled, pipe_config->double_wide); | |
6a60cd87 | 10730 | |
f50b79f0 | 10731 | intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state); |
415ff0f6 | 10732 | |
6a60cd87 CK |
10733 | DRM_DEBUG_KMS("planes on this crtc\n"); |
10734 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
b3c11ac2 | 10735 | struct drm_format_name_buf format_name; |
6a60cd87 CK |
10736 | intel_plane = to_intel_plane(plane); |
10737 | if (intel_plane->pipe != crtc->pipe) | |
10738 | continue; | |
10739 | ||
10740 | state = to_intel_plane_state(plane->state); | |
10741 | fb = state->base.fb; | |
10742 | if (!fb) { | |
1d577e02 VS |
10743 | DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n", |
10744 | plane->base.id, plane->name, state->scaler_id); | |
6a60cd87 CK |
10745 | continue; |
10746 | } | |
10747 | ||
dd2f616d TU |
10748 | DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n", |
10749 | plane->base.id, plane->name, | |
b3c11ac2 | 10750 | fb->base.id, fb->width, fb->height, |
438b74a5 | 10751 | drm_get_format_name(fb->format->format, &format_name)); |
dd2f616d TU |
10752 | if (INTEL_GEN(dev_priv) >= 9) |
10753 | DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n", | |
10754 | state->scaler_id, | |
10755 | state->base.src.x1 >> 16, | |
10756 | state->base.src.y1 >> 16, | |
10757 | drm_rect_width(&state->base.src) >> 16, | |
10758 | drm_rect_height(&state->base.src) >> 16, | |
10759 | state->base.dst.x1, state->base.dst.y1, | |
10760 | drm_rect_width(&state->base.dst), | |
10761 | drm_rect_height(&state->base.dst)); | |
6a60cd87 | 10762 | } |
c0b03411 DV |
10763 | } |
10764 | ||
5448a00d | 10765 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 10766 | { |
5448a00d | 10767 | struct drm_device *dev = state->dev; |
da3ced29 | 10768 | struct drm_connector *connector; |
2fd96b41 | 10769 | struct drm_connector_list_iter conn_iter; |
00f0b378 | 10770 | unsigned int used_ports = 0; |
477321e0 | 10771 | unsigned int used_mst_ports = 0; |
00f0b378 VS |
10772 | |
10773 | /* | |
10774 | * Walk the connector list instead of the encoder | |
10775 | * list to detect the problem on ddi platforms | |
10776 | * where there's just one encoder per digital port. | |
10777 | */ | |
2fd96b41 GP |
10778 | drm_connector_list_iter_begin(dev, &conn_iter); |
10779 | drm_for_each_connector_iter(connector, &conn_iter) { | |
0bff4858 VS |
10780 | struct drm_connector_state *connector_state; |
10781 | struct intel_encoder *encoder; | |
10782 | ||
10783 | connector_state = drm_atomic_get_existing_connector_state(state, connector); | |
10784 | if (!connector_state) | |
10785 | connector_state = connector->state; | |
10786 | ||
5448a00d | 10787 | if (!connector_state->best_encoder) |
00f0b378 VS |
10788 | continue; |
10789 | ||
5448a00d ACO |
10790 | encoder = to_intel_encoder(connector_state->best_encoder); |
10791 | ||
10792 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
10793 | |
10794 | switch (encoder->type) { | |
10795 | unsigned int port_mask; | |
10796 | case INTEL_OUTPUT_UNKNOWN: | |
4f8036a2 | 10797 | if (WARN_ON(!HAS_DDI(to_i915(dev)))) |
00f0b378 | 10798 | break; |
cca0502b | 10799 | case INTEL_OUTPUT_DP: |
00f0b378 VS |
10800 | case INTEL_OUTPUT_HDMI: |
10801 | case INTEL_OUTPUT_EDP: | |
10802 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
10803 | ||
10804 | /* the same port mustn't appear more than once */ | |
10805 | if (used_ports & port_mask) | |
10806 | return false; | |
10807 | ||
10808 | used_ports |= port_mask; | |
477321e0 VS |
10809 | break; |
10810 | case INTEL_OUTPUT_DP_MST: | |
10811 | used_mst_ports |= | |
10812 | 1 << enc_to_mst(&encoder->base)->primary->port; | |
10813 | break; | |
00f0b378 VS |
10814 | default: |
10815 | break; | |
10816 | } | |
10817 | } | |
2fd96b41 | 10818 | drm_connector_list_iter_end(&conn_iter); |
00f0b378 | 10819 | |
477321e0 VS |
10820 | /* can't mix MST and SST/HDMI on the same port */ |
10821 | if (used_ports & used_mst_ports) | |
10822 | return false; | |
10823 | ||
00f0b378 VS |
10824 | return true; |
10825 | } | |
10826 | ||
83a57153 ACO |
10827 | static void |
10828 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
10829 | { | |
ff32c54e VS |
10830 | struct drm_i915_private *dev_priv = |
10831 | to_i915(crtc_state->base.crtc->dev); | |
663a3640 | 10832 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 | 10833 | struct intel_dpll_hw_state dpll_hw_state; |
8106ddbd | 10834 | struct intel_shared_dpll *shared_dpll; |
ff32c54e | 10835 | struct intel_crtc_wm_state wm_state; |
6e644626 | 10836 | bool force_thru, ips_force_disable; |
83a57153 | 10837 | |
7546a384 ACO |
10838 | /* FIXME: before the switch to atomic started, a new pipe_config was |
10839 | * kzalloc'd. Code that depends on any field being zero should be | |
10840 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
10841 | * only fields that are know to not cause problems are preserved. */ | |
10842 | ||
663a3640 | 10843 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
10844 | shared_dpll = crtc_state->shared_dpll; |
10845 | dpll_hw_state = crtc_state->dpll_hw_state; | |
c4e2d043 | 10846 | force_thru = crtc_state->pch_pfit.force_thru; |
6e644626 | 10847 | ips_force_disable = crtc_state->ips_force_disable; |
04548cba VS |
10848 | if (IS_G4X(dev_priv) || |
10849 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
ff32c54e | 10850 | wm_state = crtc_state->wm; |
4978cc93 | 10851 | |
d2fa80a5 CW |
10852 | /* Keep base drm_crtc_state intact, only clear our extended struct */ |
10853 | BUILD_BUG_ON(offsetof(struct intel_crtc_state, base)); | |
10854 | memset(&crtc_state->base + 1, 0, | |
10855 | sizeof(*crtc_state) - sizeof(crtc_state->base)); | |
4978cc93 | 10856 | |
663a3640 | 10857 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
10858 | crtc_state->shared_dpll = shared_dpll; |
10859 | crtc_state->dpll_hw_state = dpll_hw_state; | |
c4e2d043 | 10860 | crtc_state->pch_pfit.force_thru = force_thru; |
6e644626 | 10861 | crtc_state->ips_force_disable = ips_force_disable; |
04548cba VS |
10862 | if (IS_G4X(dev_priv) || |
10863 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
ff32c54e | 10864 | crtc_state->wm = wm_state; |
83a57153 ACO |
10865 | } |
10866 | ||
548ee15b | 10867 | static int |
b8cecdf5 | 10868 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 10869 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 10870 | { |
b359283a | 10871 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 10872 | struct intel_encoder *encoder; |
da3ced29 | 10873 | struct drm_connector *connector; |
0b901879 | 10874 | struct drm_connector_state *connector_state; |
d328c9d7 | 10875 | int base_bpp, ret = -EINVAL; |
0b901879 | 10876 | int i; |
e29c22c0 | 10877 | bool retry = true; |
ee7b9f93 | 10878 | |
83a57153 | 10879 | clear_intel_crtc_state(pipe_config); |
7758a113 | 10880 | |
e143a21c DV |
10881 | pipe_config->cpu_transcoder = |
10882 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 10883 | |
2960bc9c ID |
10884 | /* |
10885 | * Sanitize sync polarity flags based on requested ones. If neither | |
10886 | * positive or negative polarity is requested, treat this as meaning | |
10887 | * negative polarity. | |
10888 | */ | |
2d112de7 | 10889 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 10890 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 10891 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 10892 | |
2d112de7 | 10893 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 10894 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 10895 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 10896 | |
d328c9d7 DV |
10897 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
10898 | pipe_config); | |
10899 | if (base_bpp < 0) | |
4e53c2e0 DV |
10900 | goto fail; |
10901 | ||
e41a56be VS |
10902 | /* |
10903 | * Determine the real pipe dimensions. Note that stereo modes can | |
10904 | * increase the actual pipe size due to the frame doubling and | |
10905 | * insertion of additional space for blanks between the frame. This | |
10906 | * is stored in the crtc timings. We use the requested mode to do this | |
10907 | * computation to clearly distinguish it from the adjusted mode, which | |
10908 | * can be changed by the connectors in the below retry loop. | |
10909 | */ | |
196cd5d3 | 10910 | drm_mode_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
10911 | &pipe_config->pipe_src_w, |
10912 | &pipe_config->pipe_src_h); | |
e41a56be | 10913 | |
aa5e9b47 | 10914 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
253c84c8 VS |
10915 | if (connector_state->crtc != crtc) |
10916 | continue; | |
10917 | ||
10918 | encoder = to_intel_encoder(connector_state->best_encoder); | |
10919 | ||
e25148d0 VS |
10920 | if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) { |
10921 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
10922 | goto fail; | |
10923 | } | |
10924 | ||
253c84c8 VS |
10925 | /* |
10926 | * Determine output_types before calling the .compute_config() | |
10927 | * hooks so that the hooks can use this information safely. | |
10928 | */ | |
10929 | pipe_config->output_types |= 1 << encoder->type; | |
10930 | } | |
10931 | ||
e29c22c0 | 10932 | encoder_retry: |
ef1b460d | 10933 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 10934 | pipe_config->port_clock = 0; |
ef1b460d | 10935 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 10936 | |
135c81b8 | 10937 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
10938 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
10939 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 10940 | |
7758a113 DV |
10941 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
10942 | * adjust it according to limitations or connector properties, and also | |
10943 | * a chance to reject the mode entirely. | |
47f1c6c9 | 10944 | */ |
aa5e9b47 | 10945 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 10946 | if (connector_state->crtc != crtc) |
7758a113 | 10947 | continue; |
7ae89233 | 10948 | |
0b901879 ACO |
10949 | encoder = to_intel_encoder(connector_state->best_encoder); |
10950 | ||
0a478c27 | 10951 | if (!(encoder->compute_config(encoder, pipe_config, connector_state))) { |
efea6e8e | 10952 | DRM_DEBUG_KMS("Encoder config failure\n"); |
7758a113 DV |
10953 | goto fail; |
10954 | } | |
ee7b9f93 | 10955 | } |
47f1c6c9 | 10956 | |
ff9a6750 DV |
10957 | /* Set default port clock if not overwritten by the encoder. Needs to be |
10958 | * done afterwards in case the encoder adjusts the mode. */ | |
10959 | if (!pipe_config->port_clock) | |
2d112de7 | 10960 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 10961 | * pipe_config->pixel_multiplier; |
ff9a6750 | 10962 | |
a43f6e0f | 10963 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 10964 | if (ret < 0) { |
7758a113 DV |
10965 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
10966 | goto fail; | |
ee7b9f93 | 10967 | } |
e29c22c0 DV |
10968 | |
10969 | if (ret == RETRY) { | |
10970 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
10971 | ret = -EINVAL; | |
10972 | goto fail; | |
10973 | } | |
10974 | ||
10975 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
10976 | retry = false; | |
10977 | goto encoder_retry; | |
10978 | } | |
10979 | ||
e8fa4270 | 10980 | /* Dithering seems to not pass-through bits correctly when it should, so |
611032bf MN |
10981 | * only enable it on 6bpc panels and when its not a compliance |
10982 | * test requesting 6bpc video pattern. | |
10983 | */ | |
10984 | pipe_config->dither = (pipe_config->pipe_bpp == 6*3) && | |
10985 | !pipe_config->dither_force_disable; | |
62f0ace5 | 10986 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 10987 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 10988 | |
7758a113 | 10989 | fail: |
548ee15b | 10990 | return ret; |
ee7b9f93 | 10991 | } |
47f1c6c9 | 10992 | |
ea9d758d | 10993 | static void |
4740b0f2 | 10994 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 10995 | { |
0a9ab303 | 10996 | struct drm_crtc *crtc; |
aa5e9b47 | 10997 | struct drm_crtc_state *new_crtc_state; |
8a75d157 | 10998 | int i; |
ea9d758d | 10999 | |
7668851f | 11000 | /* Double check state. */ |
aa5e9b47 ML |
11001 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
11002 | to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state); | |
fc467a22 | 11003 | |
61067a5e ML |
11004 | /* |
11005 | * Update legacy state to satisfy fbc code. This can | |
11006 | * be removed when fbc uses the atomic state. | |
11007 | */ | |
11008 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
11009 | struct drm_plane_state *plane_state = crtc->primary->state; | |
11010 | ||
11011 | crtc->primary->fb = plane_state->fb; | |
11012 | crtc->x = plane_state->src_x >> 16; | |
11013 | crtc->y = plane_state->src_y >> 16; | |
11014 | } | |
ea9d758d | 11015 | } |
ea9d758d DV |
11016 | } |
11017 | ||
3bd26263 | 11018 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 11019 | { |
3bd26263 | 11020 | int diff; |
f1f644dc JB |
11021 | |
11022 | if (clock1 == clock2) | |
11023 | return true; | |
11024 | ||
11025 | if (!clock1 || !clock2) | |
11026 | return false; | |
11027 | ||
11028 | diff = abs(clock1 - clock2); | |
11029 | ||
11030 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
11031 | return true; | |
11032 | ||
11033 | return false; | |
11034 | } | |
11035 | ||
cfb23ed6 ML |
11036 | static bool |
11037 | intel_compare_m_n(unsigned int m, unsigned int n, | |
11038 | unsigned int m2, unsigned int n2, | |
11039 | bool exact) | |
11040 | { | |
11041 | if (m == m2 && n == n2) | |
11042 | return true; | |
11043 | ||
11044 | if (exact || !m || !n || !m2 || !n2) | |
11045 | return false; | |
11046 | ||
11047 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
11048 | ||
31d10b57 ML |
11049 | if (n > n2) { |
11050 | while (n > n2) { | |
cfb23ed6 ML |
11051 | m2 <<= 1; |
11052 | n2 <<= 1; | |
11053 | } | |
31d10b57 ML |
11054 | } else if (n < n2) { |
11055 | while (n < n2) { | |
cfb23ed6 ML |
11056 | m <<= 1; |
11057 | n <<= 1; | |
11058 | } | |
11059 | } | |
11060 | ||
31d10b57 ML |
11061 | if (n != n2) |
11062 | return false; | |
11063 | ||
11064 | return intel_fuzzy_clock_check(m, m2); | |
cfb23ed6 ML |
11065 | } |
11066 | ||
11067 | static bool | |
11068 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
11069 | struct intel_link_m_n *m2_n2, | |
11070 | bool adjust) | |
11071 | { | |
11072 | if (m_n->tu == m2_n2->tu && | |
11073 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
11074 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
11075 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
11076 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
11077 | if (adjust) | |
11078 | *m2_n2 = *m_n; | |
11079 | ||
11080 | return true; | |
11081 | } | |
11082 | ||
11083 | return false; | |
11084 | } | |
11085 | ||
4e8048f8 TU |
11086 | static void __printf(3, 4) |
11087 | pipe_config_err(bool adjust, const char *name, const char *format, ...) | |
11088 | { | |
11089 | char *level; | |
11090 | unsigned int category; | |
11091 | struct va_format vaf; | |
11092 | va_list args; | |
11093 | ||
11094 | if (adjust) { | |
11095 | level = KERN_DEBUG; | |
11096 | category = DRM_UT_KMS; | |
11097 | } else { | |
11098 | level = KERN_ERR; | |
11099 | category = DRM_UT_NONE; | |
11100 | } | |
11101 | ||
11102 | va_start(args, format); | |
11103 | vaf.fmt = format; | |
11104 | vaf.va = &args; | |
11105 | ||
11106 | drm_printk(level, category, "mismatch in %s %pV", name, &vaf); | |
11107 | ||
11108 | va_end(args); | |
11109 | } | |
11110 | ||
0e8ffe1b | 11111 | static bool |
6315b5d3 | 11112 | intel_pipe_config_compare(struct drm_i915_private *dev_priv, |
5cec258b | 11113 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
11114 | struct intel_crtc_state *pipe_config, |
11115 | bool adjust) | |
0e8ffe1b | 11116 | { |
cfb23ed6 ML |
11117 | bool ret = true; |
11118 | ||
66e985c0 DV |
11119 | #define PIPE_CONF_CHECK_X(name) \ |
11120 | if (current_config->name != pipe_config->name) { \ | |
4e8048f8 | 11121 | pipe_config_err(adjust, __stringify(name), \ |
66e985c0 DV |
11122 | "(expected 0x%08x, found 0x%08x)\n", \ |
11123 | current_config->name, \ | |
11124 | pipe_config->name); \ | |
cfb23ed6 | 11125 | ret = false; \ |
66e985c0 DV |
11126 | } |
11127 | ||
08a24034 DV |
11128 | #define PIPE_CONF_CHECK_I(name) \ |
11129 | if (current_config->name != pipe_config->name) { \ | |
4e8048f8 | 11130 | pipe_config_err(adjust, __stringify(name), \ |
08a24034 DV |
11131 | "(expected %i, found %i)\n", \ |
11132 | current_config->name, \ | |
11133 | pipe_config->name); \ | |
cfb23ed6 ML |
11134 | ret = false; \ |
11135 | } | |
11136 | ||
8106ddbd ACO |
11137 | #define PIPE_CONF_CHECK_P(name) \ |
11138 | if (current_config->name != pipe_config->name) { \ | |
4e8048f8 | 11139 | pipe_config_err(adjust, __stringify(name), \ |
8106ddbd ACO |
11140 | "(expected %p, found %p)\n", \ |
11141 | current_config->name, \ | |
11142 | pipe_config->name); \ | |
11143 | ret = false; \ | |
11144 | } | |
11145 | ||
cfb23ed6 ML |
11146 | #define PIPE_CONF_CHECK_M_N(name) \ |
11147 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
11148 | &pipe_config->name,\ | |
11149 | adjust)) { \ | |
4e8048f8 | 11150 | pipe_config_err(adjust, __stringify(name), \ |
cfb23ed6 ML |
11151 | "(expected tu %i gmch %i/%i link %i/%i, " \ |
11152 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
11153 | current_config->name.tu, \ | |
11154 | current_config->name.gmch_m, \ | |
11155 | current_config->name.gmch_n, \ | |
11156 | current_config->name.link_m, \ | |
11157 | current_config->name.link_n, \ | |
11158 | pipe_config->name.tu, \ | |
11159 | pipe_config->name.gmch_m, \ | |
11160 | pipe_config->name.gmch_n, \ | |
11161 | pipe_config->name.link_m, \ | |
11162 | pipe_config->name.link_n); \ | |
11163 | ret = false; \ | |
11164 | } | |
11165 | ||
55c561a7 DV |
11166 | /* This is required for BDW+ where there is only one set of registers for |
11167 | * switching between high and low RR. | |
11168 | * This macro can be used whenever a comparison has to be made between one | |
11169 | * hw state and multiple sw state variables. | |
11170 | */ | |
cfb23ed6 ML |
11171 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ |
11172 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
11173 | &pipe_config->name, adjust) && \ | |
11174 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
11175 | &pipe_config->name, adjust)) { \ | |
4e8048f8 | 11176 | pipe_config_err(adjust, __stringify(name), \ |
cfb23ed6 ML |
11177 | "(expected tu %i gmch %i/%i link %i/%i, " \ |
11178 | "or tu %i gmch %i/%i link %i/%i, " \ | |
11179 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
11180 | current_config->name.tu, \ | |
11181 | current_config->name.gmch_m, \ | |
11182 | current_config->name.gmch_n, \ | |
11183 | current_config->name.link_m, \ | |
11184 | current_config->name.link_n, \ | |
11185 | current_config->alt_name.tu, \ | |
11186 | current_config->alt_name.gmch_m, \ | |
11187 | current_config->alt_name.gmch_n, \ | |
11188 | current_config->alt_name.link_m, \ | |
11189 | current_config->alt_name.link_n, \ | |
11190 | pipe_config->name.tu, \ | |
11191 | pipe_config->name.gmch_m, \ | |
11192 | pipe_config->name.gmch_n, \ | |
11193 | pipe_config->name.link_m, \ | |
11194 | pipe_config->name.link_n); \ | |
11195 | ret = false; \ | |
88adfff1 DV |
11196 | } |
11197 | ||
1bd1bd80 DV |
11198 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
11199 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
4e8048f8 TU |
11200 | pipe_config_err(adjust, __stringify(name), \ |
11201 | "(%x) (expected %i, found %i)\n", \ | |
11202 | (mask), \ | |
1bd1bd80 DV |
11203 | current_config->name & (mask), \ |
11204 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 11205 | ret = false; \ |
1bd1bd80 DV |
11206 | } |
11207 | ||
5e550656 VS |
11208 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
11209 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
4e8048f8 | 11210 | pipe_config_err(adjust, __stringify(name), \ |
5e550656 VS |
11211 | "(expected %i, found %i)\n", \ |
11212 | current_config->name, \ | |
11213 | pipe_config->name); \ | |
cfb23ed6 | 11214 | ret = false; \ |
5e550656 VS |
11215 | } |
11216 | ||
bb760063 DV |
11217 | #define PIPE_CONF_QUIRK(quirk) \ |
11218 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
11219 | ||
eccb140b DV |
11220 | PIPE_CONF_CHECK_I(cpu_transcoder); |
11221 | ||
08a24034 DV |
11222 | PIPE_CONF_CHECK_I(has_pch_encoder); |
11223 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 11224 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 11225 | |
90a6b7b0 | 11226 | PIPE_CONF_CHECK_I(lane_count); |
95a7a2ae | 11227 | PIPE_CONF_CHECK_X(lane_lat_optim_mask); |
b95af8be | 11228 | |
6315b5d3 | 11229 | if (INTEL_GEN(dev_priv) < 8) { |
cfb23ed6 ML |
11230 | PIPE_CONF_CHECK_M_N(dp_m_n); |
11231 | ||
cfb23ed6 ML |
11232 | if (current_config->has_drrs) |
11233 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
11234 | } else | |
11235 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 11236 | |
253c84c8 | 11237 | PIPE_CONF_CHECK_X(output_types); |
a65347ba | 11238 | |
2d112de7 ACO |
11239 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
11240 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
11241 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
11242 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
11243 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
11244 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 11245 | |
2d112de7 ACO |
11246 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
11247 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
11248 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
11249 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
11250 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
11251 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 11252 | |
c93f54cf | 11253 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 11254 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
772c2a51 | 11255 | if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || |
920a14b2 | 11256 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
b5a9fa09 | 11257 | PIPE_CONF_CHECK_I(limited_color_range); |
15953637 SS |
11258 | |
11259 | PIPE_CONF_CHECK_I(hdmi_scrambling); | |
11260 | PIPE_CONF_CHECK_I(hdmi_high_tmds_clock_ratio); | |
e43823ec | 11261 | PIPE_CONF_CHECK_I(has_infoframe); |
60436fd4 | 11262 | PIPE_CONF_CHECK_I(ycbcr420); |
6c49f241 | 11263 | |
9ed109a7 DV |
11264 | PIPE_CONF_CHECK_I(has_audio); |
11265 | ||
2d112de7 | 11266 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
11267 | DRM_MODE_FLAG_INTERLACE); |
11268 | ||
bb760063 | 11269 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 11270 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11271 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 11272 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11273 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 11274 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11275 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 11276 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
11277 | DRM_MODE_FLAG_NVSYNC); |
11278 | } | |
045ac3b5 | 11279 | |
333b8ca8 | 11280 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a | 11281 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
6315b5d3 | 11282 | if (INTEL_GEN(dev_priv) < 4) |
7f7d8dd6 | 11283 | PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); |
333b8ca8 | 11284 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 11285 | |
bfd16b2a ML |
11286 | if (!adjust) { |
11287 | PIPE_CONF_CHECK_I(pipe_src_w); | |
11288 | PIPE_CONF_CHECK_I(pipe_src_h); | |
11289 | ||
11290 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
11291 | if (current_config->pch_pfit.enabled) { | |
11292 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
11293 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
11294 | } | |
2fa2fe9a | 11295 | |
7aefe2b5 | 11296 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
a7d1b3f4 | 11297 | PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate); |
7aefe2b5 | 11298 | } |
a1b2278e | 11299 | |
e59150dc | 11300 | /* BDW+ don't expose a synchronous way to read the state */ |
772c2a51 | 11301 | if (IS_HASWELL(dev_priv)) |
e59150dc | 11302 | PIPE_CONF_CHECK_I(ips_enabled); |
42db64ef | 11303 | |
282740f7 VS |
11304 | PIPE_CONF_CHECK_I(double_wide); |
11305 | ||
8106ddbd | 11306 | PIPE_CONF_CHECK_P(shared_dpll); |
66e985c0 | 11307 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 11308 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
11309 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
11310 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 11311 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
00490c22 | 11312 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
3f4cd19f DL |
11313 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
11314 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
11315 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 11316 | |
47eacbab VS |
11317 | PIPE_CONF_CHECK_X(dsi_pll.ctrl); |
11318 | PIPE_CONF_CHECK_X(dsi_pll.div); | |
11319 | ||
9beb5fea | 11320 | if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) |
42571aef VS |
11321 | PIPE_CONF_CHECK_I(pipe_bpp); |
11322 | ||
2d112de7 | 11323 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 11324 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 11325 | |
66e985c0 | 11326 | #undef PIPE_CONF_CHECK_X |
08a24034 | 11327 | #undef PIPE_CONF_CHECK_I |
8106ddbd | 11328 | #undef PIPE_CONF_CHECK_P |
1bd1bd80 | 11329 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 11330 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 11331 | #undef PIPE_CONF_QUIRK |
88adfff1 | 11332 | |
cfb23ed6 | 11333 | return ret; |
0e8ffe1b DV |
11334 | } |
11335 | ||
e3b247da VS |
11336 | static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, |
11337 | const struct intel_crtc_state *pipe_config) | |
11338 | { | |
11339 | if (pipe_config->has_pch_encoder) { | |
21a727b3 | 11340 | int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
e3b247da VS |
11341 | &pipe_config->fdi_m_n); |
11342 | int dotclock = pipe_config->base.adjusted_mode.crtc_clock; | |
11343 | ||
11344 | /* | |
11345 | * FDI already provided one idea for the dotclock. | |
11346 | * Yell if the encoder disagrees. | |
11347 | */ | |
11348 | WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock), | |
11349 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", | |
11350 | fdi_dotclock, dotclock); | |
11351 | } | |
11352 | } | |
11353 | ||
c0ead703 ML |
11354 | static void verify_wm_state(struct drm_crtc *crtc, |
11355 | struct drm_crtc_state *new_state) | |
08db6652 | 11356 | { |
6315b5d3 | 11357 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
08db6652 | 11358 | struct skl_ddb_allocation hw_ddb, *sw_ddb; |
3de8a14c | 11359 | struct skl_pipe_wm hw_wm, *sw_wm; |
11360 | struct skl_plane_wm *hw_plane_wm, *sw_plane_wm; | |
11361 | struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry; | |
e7c84544 ML |
11362 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11363 | const enum pipe pipe = intel_crtc->pipe; | |
3de8a14c | 11364 | int plane, level, max_level = ilk_wm_max_level(dev_priv); |
08db6652 | 11365 | |
6315b5d3 | 11366 | if (INTEL_GEN(dev_priv) < 9 || !new_state->active) |
08db6652 DL |
11367 | return; |
11368 | ||
3de8a14c | 11369 | skl_pipe_wm_get_hw_state(crtc, &hw_wm); |
03af79e0 | 11370 | sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal; |
3de8a14c | 11371 | |
08db6652 DL |
11372 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); |
11373 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
11374 | ||
e7c84544 | 11375 | /* planes */ |
8b364b41 | 11376 | for_each_universal_plane(dev_priv, pipe, plane) { |
3de8a14c | 11377 | hw_plane_wm = &hw_wm.planes[plane]; |
11378 | sw_plane_wm = &sw_wm->planes[plane]; | |
08db6652 | 11379 | |
3de8a14c | 11380 | /* Watermarks */ |
11381 | for (level = 0; level <= max_level; level++) { | |
11382 | if (skl_wm_level_equals(&hw_plane_wm->wm[level], | |
11383 | &sw_plane_wm->wm[level])) | |
11384 | continue; | |
11385 | ||
11386 | DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
11387 | pipe_name(pipe), plane + 1, level, | |
11388 | sw_plane_wm->wm[level].plane_en, | |
11389 | sw_plane_wm->wm[level].plane_res_b, | |
11390 | sw_plane_wm->wm[level].plane_res_l, | |
11391 | hw_plane_wm->wm[level].plane_en, | |
11392 | hw_plane_wm->wm[level].plane_res_b, | |
11393 | hw_plane_wm->wm[level].plane_res_l); | |
11394 | } | |
08db6652 | 11395 | |
3de8a14c | 11396 | if (!skl_wm_level_equals(&hw_plane_wm->trans_wm, |
11397 | &sw_plane_wm->trans_wm)) { | |
11398 | DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
11399 | pipe_name(pipe), plane + 1, | |
11400 | sw_plane_wm->trans_wm.plane_en, | |
11401 | sw_plane_wm->trans_wm.plane_res_b, | |
11402 | sw_plane_wm->trans_wm.plane_res_l, | |
11403 | hw_plane_wm->trans_wm.plane_en, | |
11404 | hw_plane_wm->trans_wm.plane_res_b, | |
11405 | hw_plane_wm->trans_wm.plane_res_l); | |
11406 | } | |
11407 | ||
11408 | /* DDB */ | |
11409 | hw_ddb_entry = &hw_ddb.plane[pipe][plane]; | |
11410 | sw_ddb_entry = &sw_ddb->plane[pipe][plane]; | |
11411 | ||
11412 | if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { | |
faccd994 | 11413 | DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n", |
3de8a14c | 11414 | pipe_name(pipe), plane + 1, |
11415 | sw_ddb_entry->start, sw_ddb_entry->end, | |
11416 | hw_ddb_entry->start, hw_ddb_entry->end); | |
11417 | } | |
e7c84544 | 11418 | } |
08db6652 | 11419 | |
27082493 L |
11420 | /* |
11421 | * cursor | |
11422 | * If the cursor plane isn't active, we may not have updated it's ddb | |
11423 | * allocation. In that case since the ddb allocation will be updated | |
11424 | * once the plane becomes visible, we can skip this check | |
11425 | */ | |
cd5dcbf1 | 11426 | if (1) { |
3de8a14c | 11427 | hw_plane_wm = &hw_wm.planes[PLANE_CURSOR]; |
11428 | sw_plane_wm = &sw_wm->planes[PLANE_CURSOR]; | |
11429 | ||
11430 | /* Watermarks */ | |
11431 | for (level = 0; level <= max_level; level++) { | |
11432 | if (skl_wm_level_equals(&hw_plane_wm->wm[level], | |
11433 | &sw_plane_wm->wm[level])) | |
11434 | continue; | |
11435 | ||
11436 | DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
11437 | pipe_name(pipe), level, | |
11438 | sw_plane_wm->wm[level].plane_en, | |
11439 | sw_plane_wm->wm[level].plane_res_b, | |
11440 | sw_plane_wm->wm[level].plane_res_l, | |
11441 | hw_plane_wm->wm[level].plane_en, | |
11442 | hw_plane_wm->wm[level].plane_res_b, | |
11443 | hw_plane_wm->wm[level].plane_res_l); | |
11444 | } | |
11445 | ||
11446 | if (!skl_wm_level_equals(&hw_plane_wm->trans_wm, | |
11447 | &sw_plane_wm->trans_wm)) { | |
11448 | DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
11449 | pipe_name(pipe), | |
11450 | sw_plane_wm->trans_wm.plane_en, | |
11451 | sw_plane_wm->trans_wm.plane_res_b, | |
11452 | sw_plane_wm->trans_wm.plane_res_l, | |
11453 | hw_plane_wm->trans_wm.plane_en, | |
11454 | hw_plane_wm->trans_wm.plane_res_b, | |
11455 | hw_plane_wm->trans_wm.plane_res_l); | |
11456 | } | |
11457 | ||
11458 | /* DDB */ | |
11459 | hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; | |
11460 | sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; | |
27082493 | 11461 | |
3de8a14c | 11462 | if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { |
faccd994 | 11463 | DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n", |
27082493 | 11464 | pipe_name(pipe), |
3de8a14c | 11465 | sw_ddb_entry->start, sw_ddb_entry->end, |
11466 | hw_ddb_entry->start, hw_ddb_entry->end); | |
27082493 | 11467 | } |
08db6652 DL |
11468 | } |
11469 | } | |
11470 | ||
91d1b4bd | 11471 | static void |
677100ce ML |
11472 | verify_connector_state(struct drm_device *dev, |
11473 | struct drm_atomic_state *state, | |
11474 | struct drm_crtc *crtc) | |
8af6cf88 | 11475 | { |
35dd3c64 | 11476 | struct drm_connector *connector; |
aa5e9b47 | 11477 | struct drm_connector_state *new_conn_state; |
677100ce | 11478 | int i; |
8af6cf88 | 11479 | |
aa5e9b47 | 11480 | for_each_new_connector_in_state(state, connector, new_conn_state, i) { |
35dd3c64 | 11481 | struct drm_encoder *encoder = connector->encoder; |
749d98b8 | 11482 | struct drm_crtc_state *crtc_state = NULL; |
ad3c558f | 11483 | |
aa5e9b47 | 11484 | if (new_conn_state->crtc != crtc) |
e7c84544 ML |
11485 | continue; |
11486 | ||
749d98b8 ML |
11487 | if (crtc) |
11488 | crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc); | |
11489 | ||
11490 | intel_connector_verify_state(crtc_state, new_conn_state); | |
8af6cf88 | 11491 | |
aa5e9b47 | 11492 | I915_STATE_WARN(new_conn_state->best_encoder != encoder, |
35dd3c64 | 11493 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 11494 | } |
91d1b4bd DV |
11495 | } |
11496 | ||
11497 | static void | |
86b04268 | 11498 | verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state) |
91d1b4bd DV |
11499 | { |
11500 | struct intel_encoder *encoder; | |
86b04268 DV |
11501 | struct drm_connector *connector; |
11502 | struct drm_connector_state *old_conn_state, *new_conn_state; | |
11503 | int i; | |
8af6cf88 | 11504 | |
b2784e15 | 11505 | for_each_intel_encoder(dev, encoder) { |
86b04268 | 11506 | bool enabled = false, found = false; |
4d20cd86 | 11507 | enum pipe pipe; |
8af6cf88 DV |
11508 | |
11509 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
11510 | encoder->base.base.id, | |
8e329a03 | 11511 | encoder->base.name); |
8af6cf88 | 11512 | |
86b04268 DV |
11513 | for_each_oldnew_connector_in_state(state, connector, old_conn_state, |
11514 | new_conn_state, i) { | |
11515 | if (old_conn_state->best_encoder == &encoder->base) | |
11516 | found = true; | |
11517 | ||
11518 | if (new_conn_state->best_encoder != &encoder->base) | |
8af6cf88 | 11519 | continue; |
86b04268 | 11520 | found = enabled = true; |
ad3c558f | 11521 | |
86b04268 | 11522 | I915_STATE_WARN(new_conn_state->crtc != |
ad3c558f ML |
11523 | encoder->base.crtc, |
11524 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 11525 | } |
86b04268 DV |
11526 | |
11527 | if (!found) | |
11528 | continue; | |
0e32b39c | 11529 | |
e2c719b7 | 11530 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
11531 | "encoder's enabled state mismatch " |
11532 | "(expected %i, found %i)\n", | |
11533 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
11534 | |
11535 | if (!encoder->base.crtc) { | |
4d20cd86 | 11536 | bool active; |
7c60d198 | 11537 | |
4d20cd86 ML |
11538 | active = encoder->get_hw_state(encoder, &pipe); |
11539 | I915_STATE_WARN(active, | |
11540 | "encoder detached but still enabled on pipe %c.\n", | |
11541 | pipe_name(pipe)); | |
7c60d198 | 11542 | } |
8af6cf88 | 11543 | } |
91d1b4bd DV |
11544 | } |
11545 | ||
11546 | static void | |
c0ead703 ML |
11547 | verify_crtc_state(struct drm_crtc *crtc, |
11548 | struct drm_crtc_state *old_crtc_state, | |
11549 | struct drm_crtc_state *new_crtc_state) | |
91d1b4bd | 11550 | { |
e7c84544 | 11551 | struct drm_device *dev = crtc->dev; |
fac5e23e | 11552 | struct drm_i915_private *dev_priv = to_i915(dev); |
91d1b4bd | 11553 | struct intel_encoder *encoder; |
e7c84544 ML |
11554 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11555 | struct intel_crtc_state *pipe_config, *sw_config; | |
11556 | struct drm_atomic_state *old_state; | |
11557 | bool active; | |
045ac3b5 | 11558 | |
e7c84544 | 11559 | old_state = old_crtc_state->state; |
ec2dc6a0 | 11560 | __drm_atomic_helper_crtc_destroy_state(old_crtc_state); |
e7c84544 ML |
11561 | pipe_config = to_intel_crtc_state(old_crtc_state); |
11562 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
11563 | pipe_config->base.crtc = crtc; | |
11564 | pipe_config->base.state = old_state; | |
8af6cf88 | 11565 | |
78108b7c | 11566 | DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name); |
8af6cf88 | 11567 | |
e7c84544 | 11568 | active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config); |
d62cf62a | 11569 | |
e56134bc VS |
11570 | /* we keep both pipes enabled on 830 */ |
11571 | if (IS_I830(dev_priv)) | |
e7c84544 | 11572 | active = new_crtc_state->active; |
6c49f241 | 11573 | |
e7c84544 ML |
11574 | I915_STATE_WARN(new_crtc_state->active != active, |
11575 | "crtc active state doesn't match with hw state " | |
11576 | "(expected %i, found %i)\n", new_crtc_state->active, active); | |
0e8ffe1b | 11577 | |
e7c84544 ML |
11578 | I915_STATE_WARN(intel_crtc->active != new_crtc_state->active, |
11579 | "transitional active state does not match atomic hw state " | |
11580 | "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active); | |
4d20cd86 | 11581 | |
e7c84544 ML |
11582 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
11583 | enum pipe pipe; | |
4d20cd86 | 11584 | |
e7c84544 ML |
11585 | active = encoder->get_hw_state(encoder, &pipe); |
11586 | I915_STATE_WARN(active != new_crtc_state->active, | |
11587 | "[ENCODER:%i] active %i with crtc active %i\n", | |
11588 | encoder->base.base.id, active, new_crtc_state->active); | |
4d20cd86 | 11589 | |
e7c84544 ML |
11590 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, |
11591 | "Encoder connected to wrong pipe %c\n", | |
11592 | pipe_name(pipe)); | |
4d20cd86 | 11593 | |
253c84c8 VS |
11594 | if (active) { |
11595 | pipe_config->output_types |= 1 << encoder->type; | |
e7c84544 | 11596 | encoder->get_config(encoder, pipe_config); |
253c84c8 | 11597 | } |
e7c84544 | 11598 | } |
53d9f4e9 | 11599 | |
a7d1b3f4 VS |
11600 | intel_crtc_compute_pixel_rate(pipe_config); |
11601 | ||
e7c84544 ML |
11602 | if (!new_crtc_state->active) |
11603 | return; | |
cfb23ed6 | 11604 | |
e7c84544 | 11605 | intel_pipe_config_sanity_check(dev_priv, pipe_config); |
e3b247da | 11606 | |
749d98b8 | 11607 | sw_config = to_intel_crtc_state(new_crtc_state); |
6315b5d3 | 11608 | if (!intel_pipe_config_compare(dev_priv, sw_config, |
e7c84544 ML |
11609 | pipe_config, false)) { |
11610 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); | |
11611 | intel_dump_pipe_config(intel_crtc, pipe_config, | |
11612 | "[hw state]"); | |
11613 | intel_dump_pipe_config(intel_crtc, sw_config, | |
11614 | "[sw state]"); | |
8af6cf88 DV |
11615 | } |
11616 | } | |
11617 | ||
91d1b4bd | 11618 | static void |
c0ead703 ML |
11619 | verify_single_dpll_state(struct drm_i915_private *dev_priv, |
11620 | struct intel_shared_dpll *pll, | |
11621 | struct drm_crtc *crtc, | |
11622 | struct drm_crtc_state *new_state) | |
91d1b4bd | 11623 | { |
91d1b4bd | 11624 | struct intel_dpll_hw_state dpll_hw_state; |
e7c84544 ML |
11625 | unsigned crtc_mask; |
11626 | bool active; | |
5358901f | 11627 | |
e7c84544 | 11628 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); |
5358901f | 11629 | |
e7c84544 | 11630 | DRM_DEBUG_KMS("%s\n", pll->name); |
5358901f | 11631 | |
e7c84544 | 11632 | active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state); |
5358901f | 11633 | |
e7c84544 ML |
11634 | if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) { |
11635 | I915_STATE_WARN(!pll->on && pll->active_mask, | |
11636 | "pll in active use but not on in sw tracking\n"); | |
11637 | I915_STATE_WARN(pll->on && !pll->active_mask, | |
11638 | "pll is on but not used by any active crtc\n"); | |
11639 | I915_STATE_WARN(pll->on != active, | |
11640 | "pll on state mismatch (expected %i, found %i)\n", | |
11641 | pll->on, active); | |
11642 | } | |
5358901f | 11643 | |
e7c84544 | 11644 | if (!crtc) { |
2c42e535 | 11645 | I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask, |
e7c84544 | 11646 | "more active pll users than references: %x vs %x\n", |
2c42e535 | 11647 | pll->active_mask, pll->state.crtc_mask); |
5358901f | 11648 | |
e7c84544 ML |
11649 | return; |
11650 | } | |
11651 | ||
11652 | crtc_mask = 1 << drm_crtc_index(crtc); | |
11653 | ||
11654 | if (new_state->active) | |
11655 | I915_STATE_WARN(!(pll->active_mask & crtc_mask), | |
11656 | "pll active mismatch (expected pipe %c in active mask 0x%02x)\n", | |
11657 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
11658 | else | |
11659 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
11660 | "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n", | |
11661 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
2dd66ebd | 11662 | |
2c42e535 | 11663 | I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask), |
e7c84544 | 11664 | "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n", |
2c42e535 | 11665 | crtc_mask, pll->state.crtc_mask); |
66e985c0 | 11666 | |
2c42e535 | 11667 | I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state, |
e7c84544 ML |
11668 | &dpll_hw_state, |
11669 | sizeof(dpll_hw_state)), | |
11670 | "pll hw state mismatch\n"); | |
11671 | } | |
11672 | ||
11673 | static void | |
c0ead703 ML |
11674 | verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc, |
11675 | struct drm_crtc_state *old_crtc_state, | |
11676 | struct drm_crtc_state *new_crtc_state) | |
e7c84544 | 11677 | { |
fac5e23e | 11678 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7c84544 ML |
11679 | struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state); |
11680 | struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state); | |
11681 | ||
11682 | if (new_state->shared_dpll) | |
c0ead703 | 11683 | verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state); |
e7c84544 ML |
11684 | |
11685 | if (old_state->shared_dpll && | |
11686 | old_state->shared_dpll != new_state->shared_dpll) { | |
11687 | unsigned crtc_mask = 1 << drm_crtc_index(crtc); | |
11688 | struct intel_shared_dpll *pll = old_state->shared_dpll; | |
11689 | ||
11690 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
11691 | "pll active mismatch (didn't expect pipe %c in active mask)\n", | |
11692 | pipe_name(drm_crtc_index(crtc))); | |
2c42e535 | 11693 | I915_STATE_WARN(pll->state.crtc_mask & crtc_mask, |
e7c84544 ML |
11694 | "pll enabled crtcs mismatch (found %x in enabled mask)\n", |
11695 | pipe_name(drm_crtc_index(crtc))); | |
5358901f | 11696 | } |
8af6cf88 DV |
11697 | } |
11698 | ||
e7c84544 | 11699 | static void |
c0ead703 | 11700 | intel_modeset_verify_crtc(struct drm_crtc *crtc, |
677100ce ML |
11701 | struct drm_atomic_state *state, |
11702 | struct drm_crtc_state *old_state, | |
11703 | struct drm_crtc_state *new_state) | |
e7c84544 | 11704 | { |
5a21b665 DV |
11705 | if (!needs_modeset(new_state) && |
11706 | !to_intel_crtc_state(new_state)->update_pipe) | |
11707 | return; | |
11708 | ||
c0ead703 | 11709 | verify_wm_state(crtc, new_state); |
677100ce | 11710 | verify_connector_state(crtc->dev, state, crtc); |
c0ead703 ML |
11711 | verify_crtc_state(crtc, old_state, new_state); |
11712 | verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state); | |
e7c84544 ML |
11713 | } |
11714 | ||
11715 | static void | |
c0ead703 | 11716 | verify_disabled_dpll_state(struct drm_device *dev) |
e7c84544 | 11717 | { |
fac5e23e | 11718 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7c84544 ML |
11719 | int i; |
11720 | ||
11721 | for (i = 0; i < dev_priv->num_shared_dpll; i++) | |
c0ead703 | 11722 | verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL); |
e7c84544 ML |
11723 | } |
11724 | ||
11725 | static void | |
677100ce ML |
11726 | intel_modeset_verify_disabled(struct drm_device *dev, |
11727 | struct drm_atomic_state *state) | |
e7c84544 | 11728 | { |
86b04268 | 11729 | verify_encoder_state(dev, state); |
677100ce | 11730 | verify_connector_state(dev, state, NULL); |
c0ead703 | 11731 | verify_disabled_dpll_state(dev); |
e7c84544 ML |
11732 | } |
11733 | ||
80715b2f VS |
11734 | static void update_scanline_offset(struct intel_crtc *crtc) |
11735 | { | |
4f8036a2 | 11736 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
80715b2f VS |
11737 | |
11738 | /* | |
11739 | * The scanline counter increments at the leading edge of hsync. | |
11740 | * | |
11741 | * On most platforms it starts counting from vtotal-1 on the | |
11742 | * first active line. That means the scanline counter value is | |
11743 | * always one less than what we would expect. Ie. just after | |
11744 | * start of vblank, which also occurs at start of hsync (on the | |
11745 | * last active line), the scanline counter will read vblank_start-1. | |
11746 | * | |
11747 | * On gen2 the scanline counter starts counting from 1 instead | |
11748 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
11749 | * to keep the value positive), instead of adding one. | |
11750 | * | |
11751 | * On HSW+ the behaviour of the scanline counter depends on the output | |
11752 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
11753 | * there's an extra 1 line difference. So we need to add two instead of | |
11754 | * one to the value. | |
ec1b4ee2 VS |
11755 | * |
11756 | * On VLV/CHV DSI the scanline counter would appear to increment | |
11757 | * approx. 1/3 of a scanline before start of vblank. Unfortunately | |
11758 | * that means we can't tell whether we're in vblank or not while | |
11759 | * we're on that particular line. We must still set scanline_offset | |
11760 | * to 1 so that the vblank timestamps come out correct when we query | |
11761 | * the scanline counter from within the vblank interrupt handler. | |
11762 | * However if queried just before the start of vblank we'll get an | |
11763 | * answer that's slightly in the future. | |
80715b2f | 11764 | */ |
4f8036a2 | 11765 | if (IS_GEN2(dev_priv)) { |
124abe07 | 11766 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
11767 | int vtotal; |
11768 | ||
124abe07 VS |
11769 | vtotal = adjusted_mode->crtc_vtotal; |
11770 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
11771 | vtotal /= 2; |
11772 | ||
11773 | crtc->scanline_offset = vtotal - 1; | |
4f8036a2 | 11774 | } else if (HAS_DDI(dev_priv) && |
2d84d2b3 | 11775 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
11776 | crtc->scanline_offset = 2; |
11777 | } else | |
11778 | crtc->scanline_offset = 1; | |
11779 | } | |
11780 | ||
ad421372 | 11781 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 11782 | { |
225da59b | 11783 | struct drm_device *dev = state->dev; |
ed6739ef | 11784 | struct drm_i915_private *dev_priv = to_i915(dev); |
0a9ab303 | 11785 | struct drm_crtc *crtc; |
aa5e9b47 | 11786 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
0a9ab303 | 11787 | int i; |
ed6739ef ACO |
11788 | |
11789 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 11790 | return; |
ed6739ef | 11791 | |
aa5e9b47 | 11792 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
fb1a38a9 | 11793 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8106ddbd | 11794 | struct intel_shared_dpll *old_dpll = |
aa5e9b47 | 11795 | to_intel_crtc_state(old_crtc_state)->shared_dpll; |
0a9ab303 | 11796 | |
aa5e9b47 | 11797 | if (!needs_modeset(new_crtc_state)) |
225da59b ACO |
11798 | continue; |
11799 | ||
aa5e9b47 | 11800 | to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL; |
fb1a38a9 | 11801 | |
8106ddbd | 11802 | if (!old_dpll) |
fb1a38a9 | 11803 | continue; |
0a9ab303 | 11804 | |
a1c414ee | 11805 | intel_release_shared_dpll(old_dpll, intel_crtc, state); |
ad421372 | 11806 | } |
ed6739ef ACO |
11807 | } |
11808 | ||
99d736a2 ML |
11809 | /* |
11810 | * This implements the workaround described in the "notes" section of the mode | |
11811 | * set sequence documentation. When going from no pipes or single pipe to | |
11812 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
11813 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
11814 | */ | |
11815 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
11816 | { | |
11817 | struct drm_crtc_state *crtc_state; | |
11818 | struct intel_crtc *intel_crtc; | |
11819 | struct drm_crtc *crtc; | |
11820 | struct intel_crtc_state *first_crtc_state = NULL; | |
11821 | struct intel_crtc_state *other_crtc_state = NULL; | |
11822 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
11823 | int i; | |
11824 | ||
11825 | /* look at all crtc's that are going to be enabled in during modeset */ | |
aa5e9b47 | 11826 | for_each_new_crtc_in_state(state, crtc, crtc_state, i) { |
99d736a2 ML |
11827 | intel_crtc = to_intel_crtc(crtc); |
11828 | ||
11829 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
11830 | continue; | |
11831 | ||
11832 | if (first_crtc_state) { | |
11833 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
11834 | break; | |
11835 | } else { | |
11836 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
11837 | first_pipe = intel_crtc->pipe; | |
11838 | } | |
11839 | } | |
11840 | ||
11841 | /* No workaround needed? */ | |
11842 | if (!first_crtc_state) | |
11843 | return 0; | |
11844 | ||
11845 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
11846 | for_each_intel_crtc(state->dev, intel_crtc) { | |
11847 | struct intel_crtc_state *pipe_config; | |
11848 | ||
11849 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
11850 | if (IS_ERR(pipe_config)) | |
11851 | return PTR_ERR(pipe_config); | |
11852 | ||
11853 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
11854 | ||
11855 | if (!pipe_config->base.active || | |
11856 | needs_modeset(&pipe_config->base)) | |
11857 | continue; | |
11858 | ||
11859 | /* 2 or more enabled crtcs means no need for w/a */ | |
11860 | if (enabled_pipe != INVALID_PIPE) | |
11861 | return 0; | |
11862 | ||
11863 | enabled_pipe = intel_crtc->pipe; | |
11864 | } | |
11865 | ||
11866 | if (enabled_pipe != INVALID_PIPE) | |
11867 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
11868 | else if (other_crtc_state) | |
11869 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
11870 | ||
11871 | return 0; | |
11872 | } | |
11873 | ||
8d96561a VS |
11874 | static int intel_lock_all_pipes(struct drm_atomic_state *state) |
11875 | { | |
11876 | struct drm_crtc *crtc; | |
11877 | ||
11878 | /* Add all pipes to the state */ | |
11879 | for_each_crtc(state->dev, crtc) { | |
11880 | struct drm_crtc_state *crtc_state; | |
11881 | ||
11882 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
11883 | if (IS_ERR(crtc_state)) | |
11884 | return PTR_ERR(crtc_state); | |
11885 | } | |
11886 | ||
11887 | return 0; | |
11888 | } | |
11889 | ||
27c329ed ML |
11890 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
11891 | { | |
11892 | struct drm_crtc *crtc; | |
27c329ed | 11893 | |
8d96561a VS |
11894 | /* |
11895 | * Add all pipes to the state, and force | |
11896 | * a modeset on all the active ones. | |
11897 | */ | |
27c329ed | 11898 | for_each_crtc(state->dev, crtc) { |
9780aad5 VS |
11899 | struct drm_crtc_state *crtc_state; |
11900 | int ret; | |
11901 | ||
27c329ed ML |
11902 | crtc_state = drm_atomic_get_crtc_state(state, crtc); |
11903 | if (IS_ERR(crtc_state)) | |
11904 | return PTR_ERR(crtc_state); | |
11905 | ||
11906 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
11907 | continue; | |
11908 | ||
11909 | crtc_state->mode_changed = true; | |
11910 | ||
11911 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
11912 | if (ret) | |
9780aad5 | 11913 | return ret; |
27c329ed ML |
11914 | |
11915 | ret = drm_atomic_add_affected_planes(state, crtc); | |
11916 | if (ret) | |
9780aad5 | 11917 | return ret; |
27c329ed ML |
11918 | } |
11919 | ||
9780aad5 | 11920 | return 0; |
27c329ed ML |
11921 | } |
11922 | ||
c347a676 | 11923 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd | 11924 | { |
565602d7 | 11925 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 11926 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
565602d7 | 11927 | struct drm_crtc *crtc; |
aa5e9b47 | 11928 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
565602d7 | 11929 | int ret = 0, i; |
054518dd | 11930 | |
b359283a ML |
11931 | if (!check_digital_port_conflicts(state)) { |
11932 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
11933 | return -EINVAL; | |
11934 | } | |
11935 | ||
565602d7 ML |
11936 | intel_state->modeset = true; |
11937 | intel_state->active_crtcs = dev_priv->active_crtcs; | |
bb0f4aab VS |
11938 | intel_state->cdclk.logical = dev_priv->cdclk.logical; |
11939 | intel_state->cdclk.actual = dev_priv->cdclk.actual; | |
565602d7 | 11940 | |
aa5e9b47 ML |
11941 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
11942 | if (new_crtc_state->active) | |
565602d7 ML |
11943 | intel_state->active_crtcs |= 1 << i; |
11944 | else | |
11945 | intel_state->active_crtcs &= ~(1 << i); | |
8b4a7d05 | 11946 | |
aa5e9b47 | 11947 | if (old_crtc_state->active != new_crtc_state->active) |
8b4a7d05 | 11948 | intel_state->active_pipe_changes |= drm_crtc_mask(crtc); |
565602d7 ML |
11949 | } |
11950 | ||
054518dd ACO |
11951 | /* |
11952 | * See if the config requires any additional preparation, e.g. | |
11953 | * to adjust global state with pipes off. We need to do this | |
11954 | * here so we can get the modeset_pipe updated config for the new | |
11955 | * mode set on this crtc. For other crtcs we need to use the | |
11956 | * adjusted_mode bits in the crtc directly. | |
11957 | */ | |
27c329ed | 11958 | if (dev_priv->display.modeset_calc_cdclk) { |
27c329ed | 11959 | ret = dev_priv->display.modeset_calc_cdclk(state); |
c89e39f3 CT |
11960 | if (ret < 0) |
11961 | return ret; | |
27c329ed | 11962 | |
8d96561a | 11963 | /* |
bb0f4aab | 11964 | * Writes to dev_priv->cdclk.logical must protected by |
8d96561a VS |
11965 | * holding all the crtc locks, even if we don't end up |
11966 | * touching the hardware | |
11967 | */ | |
bb0f4aab VS |
11968 | if (!intel_cdclk_state_compare(&dev_priv->cdclk.logical, |
11969 | &intel_state->cdclk.logical)) { | |
8d96561a VS |
11970 | ret = intel_lock_all_pipes(state); |
11971 | if (ret < 0) | |
11972 | return ret; | |
11973 | } | |
11974 | ||
11975 | /* All pipes must be switched off while we change the cdclk. */ | |
bb0f4aab VS |
11976 | if (!intel_cdclk_state_compare(&dev_priv->cdclk.actual, |
11977 | &intel_state->cdclk.actual)) { | |
27c329ed | 11978 | ret = intel_modeset_all_pipes(state); |
8d96561a VS |
11979 | if (ret < 0) |
11980 | return ret; | |
11981 | } | |
e8788cbc | 11982 | |
bb0f4aab VS |
11983 | DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n", |
11984 | intel_state->cdclk.logical.cdclk, | |
11985 | intel_state->cdclk.actual.cdclk); | |
e0ca7a6b | 11986 | } else { |
bb0f4aab | 11987 | to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical; |
e0ca7a6b | 11988 | } |
054518dd | 11989 | |
ad421372 | 11990 | intel_modeset_clear_plls(state); |
054518dd | 11991 | |
565602d7 | 11992 | if (IS_HASWELL(dev_priv)) |
ad421372 | 11993 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 11994 | |
ad421372 | 11995 | return 0; |
c347a676 ACO |
11996 | } |
11997 | ||
aa363136 MR |
11998 | /* |
11999 | * Handle calculation of various watermark data at the end of the atomic check | |
12000 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
12001 | * handlers to ensure that all derived state has been updated. | |
12002 | */ | |
55994c2c | 12003 | static int calc_watermark_data(struct drm_atomic_state *state) |
aa363136 MR |
12004 | { |
12005 | struct drm_device *dev = state->dev; | |
98d39494 | 12006 | struct drm_i915_private *dev_priv = to_i915(dev); |
98d39494 MR |
12007 | |
12008 | /* Is there platform-specific watermark information to calculate? */ | |
12009 | if (dev_priv->display.compute_global_watermarks) | |
55994c2c MR |
12010 | return dev_priv->display.compute_global_watermarks(state); |
12011 | ||
12012 | return 0; | |
aa363136 MR |
12013 | } |
12014 | ||
74c090b1 ML |
12015 | /** |
12016 | * intel_atomic_check - validate state object | |
12017 | * @dev: drm device | |
12018 | * @state: state to validate | |
12019 | */ | |
12020 | static int intel_atomic_check(struct drm_device *dev, | |
12021 | struct drm_atomic_state *state) | |
c347a676 | 12022 | { |
dd8b3bdb | 12023 | struct drm_i915_private *dev_priv = to_i915(dev); |
aa363136 | 12024 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
c347a676 | 12025 | struct drm_crtc *crtc; |
aa5e9b47 | 12026 | struct drm_crtc_state *old_crtc_state, *crtc_state; |
c347a676 | 12027 | int ret, i; |
61333b60 | 12028 | bool any_ms = false; |
c347a676 | 12029 | |
74c090b1 | 12030 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
12031 | if (ret) |
12032 | return ret; | |
12033 | ||
aa5e9b47 | 12034 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) { |
cfb23ed6 ML |
12035 | struct intel_crtc_state *pipe_config = |
12036 | to_intel_crtc_state(crtc_state); | |
1ed51de9 DV |
12037 | |
12038 | /* Catch I915_MODE_FLAG_INHERITED */ | |
aa5e9b47 | 12039 | if (crtc_state->mode.private_flags != old_crtc_state->mode.private_flags) |
1ed51de9 | 12040 | crtc_state->mode_changed = true; |
cfb23ed6 | 12041 | |
af4a879e | 12042 | if (!needs_modeset(crtc_state)) |
c347a676 ACO |
12043 | continue; |
12044 | ||
af4a879e DV |
12045 | if (!crtc_state->enable) { |
12046 | any_ms = true; | |
cfb23ed6 | 12047 | continue; |
af4a879e | 12048 | } |
cfb23ed6 | 12049 | |
26495481 DV |
12050 | /* FIXME: For only active_changed we shouldn't need to do any |
12051 | * state recomputation at all. */ | |
12052 | ||
1ed51de9 DV |
12053 | ret = drm_atomic_add_affected_connectors(state, crtc); |
12054 | if (ret) | |
12055 | return ret; | |
b359283a | 12056 | |
cfb23ed6 | 12057 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
25aa1c39 ML |
12058 | if (ret) { |
12059 | intel_dump_pipe_config(to_intel_crtc(crtc), | |
12060 | pipe_config, "[failed]"); | |
c347a676 | 12061 | return ret; |
25aa1c39 | 12062 | } |
c347a676 | 12063 | |
73831236 | 12064 | if (i915.fastboot && |
6315b5d3 | 12065 | intel_pipe_config_compare(dev_priv, |
aa5e9b47 | 12066 | to_intel_crtc_state(old_crtc_state), |
1ed51de9 | 12067 | pipe_config, true)) { |
26495481 | 12068 | crtc_state->mode_changed = false; |
aa5e9b47 | 12069 | pipe_config->update_pipe = true; |
26495481 DV |
12070 | } |
12071 | ||
af4a879e | 12072 | if (needs_modeset(crtc_state)) |
26495481 | 12073 | any_ms = true; |
cfb23ed6 | 12074 | |
af4a879e DV |
12075 | ret = drm_atomic_add_affected_planes(state, crtc); |
12076 | if (ret) | |
12077 | return ret; | |
61333b60 | 12078 | |
26495481 DV |
12079 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
12080 | needs_modeset(crtc_state) ? | |
12081 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
12082 | } |
12083 | ||
61333b60 ML |
12084 | if (any_ms) { |
12085 | ret = intel_modeset_checks(state); | |
12086 | ||
12087 | if (ret) | |
12088 | return ret; | |
e0ca7a6b | 12089 | } else { |
bb0f4aab | 12090 | intel_state->cdclk.logical = dev_priv->cdclk.logical; |
e0ca7a6b | 12091 | } |
76305b1a | 12092 | |
dd8b3bdb | 12093 | ret = drm_atomic_helper_check_planes(dev, state); |
aa363136 MR |
12094 | if (ret) |
12095 | return ret; | |
12096 | ||
f51be2e0 | 12097 | intel_fbc_choose_crtc(dev_priv, state); |
55994c2c | 12098 | return calc_watermark_data(state); |
054518dd ACO |
12099 | } |
12100 | ||
5008e874 | 12101 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
d07f0e59 | 12102 | struct drm_atomic_state *state) |
5008e874 | 12103 | { |
fd70075f | 12104 | return drm_atomic_helper_prepare_planes(dev, state); |
5008e874 ML |
12105 | } |
12106 | ||
a2991414 ML |
12107 | u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc) |
12108 | { | |
12109 | struct drm_device *dev = crtc->base.dev; | |
12110 | ||
12111 | if (!dev->max_vblank_count) | |
ca814b25 | 12112 | return drm_crtc_accurate_vblank_count(&crtc->base); |
a2991414 ML |
12113 | |
12114 | return dev->driver->get_vblank_counter(dev, crtc->pipe); | |
12115 | } | |
12116 | ||
5a21b665 DV |
12117 | static void intel_atomic_wait_for_vblanks(struct drm_device *dev, |
12118 | struct drm_i915_private *dev_priv, | |
12119 | unsigned crtc_mask) | |
e8861675 | 12120 | { |
5a21b665 DV |
12121 | unsigned last_vblank_count[I915_MAX_PIPES]; |
12122 | enum pipe pipe; | |
12123 | int ret; | |
e8861675 | 12124 | |
5a21b665 DV |
12125 | if (!crtc_mask) |
12126 | return; | |
e8861675 | 12127 | |
5a21b665 | 12128 | for_each_pipe(dev_priv, pipe) { |
98187836 VS |
12129 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, |
12130 | pipe); | |
e8861675 | 12131 | |
5a21b665 | 12132 | if (!((1 << pipe) & crtc_mask)) |
e8861675 ML |
12133 | continue; |
12134 | ||
e2af48c6 | 12135 | ret = drm_crtc_vblank_get(&crtc->base); |
5a21b665 DV |
12136 | if (WARN_ON(ret != 0)) { |
12137 | crtc_mask &= ~(1 << pipe); | |
12138 | continue; | |
e8861675 ML |
12139 | } |
12140 | ||
e2af48c6 | 12141 | last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base); |
e8861675 ML |
12142 | } |
12143 | ||
5a21b665 | 12144 | for_each_pipe(dev_priv, pipe) { |
98187836 VS |
12145 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, |
12146 | pipe); | |
5a21b665 | 12147 | long lret; |
e8861675 | 12148 | |
5a21b665 DV |
12149 | if (!((1 << pipe) & crtc_mask)) |
12150 | continue; | |
d55dbd06 | 12151 | |
5a21b665 DV |
12152 | lret = wait_event_timeout(dev->vblank[pipe].queue, |
12153 | last_vblank_count[pipe] != | |
e2af48c6 | 12154 | drm_crtc_vblank_count(&crtc->base), |
5a21b665 | 12155 | msecs_to_jiffies(50)); |
d55dbd06 | 12156 | |
5a21b665 | 12157 | WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe)); |
d55dbd06 | 12158 | |
e2af48c6 | 12159 | drm_crtc_vblank_put(&crtc->base); |
d55dbd06 ML |
12160 | } |
12161 | } | |
12162 | ||
5a21b665 | 12163 | static bool needs_vblank_wait(struct intel_crtc_state *crtc_state) |
a6747b73 | 12164 | { |
5a21b665 DV |
12165 | /* fb updated, need to unpin old fb */ |
12166 | if (crtc_state->fb_changed) | |
12167 | return true; | |
a6747b73 | 12168 | |
5a21b665 DV |
12169 | /* wm changes, need vblank before final wm's */ |
12170 | if (crtc_state->update_wm_post) | |
12171 | return true; | |
a6747b73 | 12172 | |
5eeb798b | 12173 | if (crtc_state->wm.need_postvbl_update) |
5a21b665 | 12174 | return true; |
a6747b73 | 12175 | |
5a21b665 | 12176 | return false; |
e8861675 ML |
12177 | } |
12178 | ||
896e5bb0 L |
12179 | static void intel_update_crtc(struct drm_crtc *crtc, |
12180 | struct drm_atomic_state *state, | |
12181 | struct drm_crtc_state *old_crtc_state, | |
aa5e9b47 | 12182 | struct drm_crtc_state *new_crtc_state, |
896e5bb0 L |
12183 | unsigned int *crtc_vblank_mask) |
12184 | { | |
12185 | struct drm_device *dev = crtc->dev; | |
12186 | struct drm_i915_private *dev_priv = to_i915(dev); | |
12187 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
aa5e9b47 ML |
12188 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state); |
12189 | bool modeset = needs_modeset(new_crtc_state); | |
896e5bb0 L |
12190 | |
12191 | if (modeset) { | |
12192 | update_scanline_offset(intel_crtc); | |
12193 | dev_priv->display.crtc_enable(pipe_config, state); | |
12194 | } else { | |
aa5e9b47 ML |
12195 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state), |
12196 | pipe_config); | |
896e5bb0 L |
12197 | } |
12198 | ||
12199 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
12200 | intel_fbc_enable( | |
12201 | intel_crtc, pipe_config, | |
12202 | to_intel_plane_state(crtc->primary->state)); | |
12203 | } | |
12204 | ||
12205 | drm_atomic_helper_commit_planes_on_crtc(old_crtc_state); | |
12206 | ||
12207 | if (needs_vblank_wait(pipe_config)) | |
12208 | *crtc_vblank_mask |= drm_crtc_mask(crtc); | |
12209 | } | |
12210 | ||
12211 | static void intel_update_crtcs(struct drm_atomic_state *state, | |
12212 | unsigned int *crtc_vblank_mask) | |
12213 | { | |
12214 | struct drm_crtc *crtc; | |
aa5e9b47 | 12215 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
896e5bb0 L |
12216 | int i; |
12217 | ||
aa5e9b47 ML |
12218 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
12219 | if (!new_crtc_state->active) | |
896e5bb0 L |
12220 | continue; |
12221 | ||
12222 | intel_update_crtc(crtc, state, old_crtc_state, | |
aa5e9b47 | 12223 | new_crtc_state, crtc_vblank_mask); |
896e5bb0 L |
12224 | } |
12225 | } | |
12226 | ||
27082493 L |
12227 | static void skl_update_crtcs(struct drm_atomic_state *state, |
12228 | unsigned int *crtc_vblank_mask) | |
12229 | { | |
0f0f74bc | 12230 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
27082493 L |
12231 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
12232 | struct drm_crtc *crtc; | |
ce0ba283 | 12233 | struct intel_crtc *intel_crtc; |
aa5e9b47 | 12234 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
ce0ba283 | 12235 | struct intel_crtc_state *cstate; |
27082493 L |
12236 | unsigned int updated = 0; |
12237 | bool progress; | |
12238 | enum pipe pipe; | |
5eff503b ML |
12239 | int i; |
12240 | ||
12241 | const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {}; | |
12242 | ||
aa5e9b47 | 12243 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) |
5eff503b | 12244 | /* ignore allocations for crtc's that have been turned off. */ |
aa5e9b47 | 12245 | if (new_crtc_state->active) |
5eff503b | 12246 | entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb; |
27082493 L |
12247 | |
12248 | /* | |
12249 | * Whenever the number of active pipes changes, we need to make sure we | |
12250 | * update the pipes in the right order so that their ddb allocations | |
12251 | * never overlap with eachother inbetween CRTC updates. Otherwise we'll | |
12252 | * cause pipe underruns and other bad stuff. | |
12253 | */ | |
12254 | do { | |
27082493 L |
12255 | progress = false; |
12256 | ||
aa5e9b47 | 12257 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
27082493 L |
12258 | bool vbl_wait = false; |
12259 | unsigned int cmask = drm_crtc_mask(crtc); | |
ce0ba283 L |
12260 | |
12261 | intel_crtc = to_intel_crtc(crtc); | |
12262 | cstate = to_intel_crtc_state(crtc->state); | |
12263 | pipe = intel_crtc->pipe; | |
27082493 | 12264 | |
5eff503b | 12265 | if (updated & cmask || !cstate->base.active) |
27082493 | 12266 | continue; |
5eff503b ML |
12267 | |
12268 | if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i)) | |
27082493 L |
12269 | continue; |
12270 | ||
12271 | updated |= cmask; | |
5eff503b | 12272 | entries[i] = &cstate->wm.skl.ddb; |
27082493 L |
12273 | |
12274 | /* | |
12275 | * If this is an already active pipe, it's DDB changed, | |
12276 | * and this isn't the last pipe that needs updating | |
12277 | * then we need to wait for a vblank to pass for the | |
12278 | * new ddb allocation to take effect. | |
12279 | */ | |
ce0ba283 | 12280 | if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb, |
512b5527 | 12281 | &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) && |
aa5e9b47 | 12282 | !new_crtc_state->active_changed && |
27082493 L |
12283 | intel_state->wm_results.dirty_pipes != updated) |
12284 | vbl_wait = true; | |
12285 | ||
12286 | intel_update_crtc(crtc, state, old_crtc_state, | |
aa5e9b47 | 12287 | new_crtc_state, crtc_vblank_mask); |
27082493 L |
12288 | |
12289 | if (vbl_wait) | |
0f0f74bc | 12290 | intel_wait_for_vblank(dev_priv, pipe); |
27082493 L |
12291 | |
12292 | progress = true; | |
12293 | } | |
12294 | } while (progress); | |
12295 | } | |
12296 | ||
ba318c61 CW |
12297 | static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv) |
12298 | { | |
12299 | struct intel_atomic_state *state, *next; | |
12300 | struct llist_node *freed; | |
12301 | ||
12302 | freed = llist_del_all(&dev_priv->atomic_helper.free_list); | |
12303 | llist_for_each_entry_safe(state, next, freed, freed) | |
12304 | drm_atomic_state_put(&state->base); | |
12305 | } | |
12306 | ||
12307 | static void intel_atomic_helper_free_state_worker(struct work_struct *work) | |
12308 | { | |
12309 | struct drm_i915_private *dev_priv = | |
12310 | container_of(work, typeof(*dev_priv), atomic_helper.free_work); | |
12311 | ||
12312 | intel_atomic_helper_free_state(dev_priv); | |
12313 | } | |
12314 | ||
9db529aa DV |
12315 | static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state) |
12316 | { | |
12317 | struct wait_queue_entry wait_fence, wait_reset; | |
12318 | struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev); | |
12319 | ||
12320 | init_wait_entry(&wait_fence, 0); | |
12321 | init_wait_entry(&wait_reset, 0); | |
12322 | for (;;) { | |
12323 | prepare_to_wait(&intel_state->commit_ready.wait, | |
12324 | &wait_fence, TASK_UNINTERRUPTIBLE); | |
12325 | prepare_to_wait(&dev_priv->gpu_error.wait_queue, | |
12326 | &wait_reset, TASK_UNINTERRUPTIBLE); | |
12327 | ||
12328 | ||
12329 | if (i915_sw_fence_done(&intel_state->commit_ready) | |
12330 | || test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags)) | |
12331 | break; | |
12332 | ||
12333 | schedule(); | |
12334 | } | |
12335 | finish_wait(&intel_state->commit_ready.wait, &wait_fence); | |
12336 | finish_wait(&dev_priv->gpu_error.wait_queue, &wait_reset); | |
12337 | } | |
12338 | ||
94f05024 | 12339 | static void intel_atomic_commit_tail(struct drm_atomic_state *state) |
a6778b3c | 12340 | { |
94f05024 | 12341 | struct drm_device *dev = state->dev; |
565602d7 | 12342 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 12343 | struct drm_i915_private *dev_priv = to_i915(dev); |
aa5e9b47 | 12344 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
7580d774 | 12345 | struct drm_crtc *crtc; |
5a21b665 | 12346 | struct intel_crtc_state *intel_cstate; |
5a21b665 | 12347 | bool hw_check = intel_state->modeset; |
d8fc70b7 | 12348 | u64 put_domains[I915_MAX_PIPES] = {}; |
5a21b665 | 12349 | unsigned crtc_vblank_mask = 0; |
e95433c7 | 12350 | int i; |
a6778b3c | 12351 | |
9db529aa | 12352 | intel_atomic_commit_fence_wait(intel_state); |
42b062b0 | 12353 | |
ea0000f0 DV |
12354 | drm_atomic_helper_wait_for_dependencies(state); |
12355 | ||
c3b32658 | 12356 | if (intel_state->modeset) |
5a21b665 | 12357 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); |
565602d7 | 12358 | |
aa5e9b47 | 12359 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
a539205a ML |
12360 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
12361 | ||
aa5e9b47 ML |
12362 | if (needs_modeset(new_crtc_state) || |
12363 | to_intel_crtc_state(new_crtc_state)->update_pipe) { | |
5a21b665 DV |
12364 | hw_check = true; |
12365 | ||
12366 | put_domains[to_intel_crtc(crtc)->pipe] = | |
12367 | modeset_get_crtc_power_domains(crtc, | |
aa5e9b47 | 12368 | to_intel_crtc_state(new_crtc_state)); |
5a21b665 DV |
12369 | } |
12370 | ||
aa5e9b47 | 12371 | if (!needs_modeset(new_crtc_state)) |
61333b60 ML |
12372 | continue; |
12373 | ||
aa5e9b47 ML |
12374 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state), |
12375 | to_intel_crtc_state(new_crtc_state)); | |
460da916 | 12376 | |
29ceb0e6 VS |
12377 | if (old_crtc_state->active) { |
12378 | intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask); | |
4a806558 | 12379 | dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state); |
eddfcbcd | 12380 | intel_crtc->active = false; |
58f9c0bc | 12381 | intel_fbc_disable(intel_crtc); |
eddfcbcd | 12382 | intel_disable_shared_dpll(intel_crtc); |
9bbc8258 VS |
12383 | |
12384 | /* | |
12385 | * Underruns don't always raise | |
12386 | * interrupts, so check manually. | |
12387 | */ | |
12388 | intel_check_cpu_fifo_underruns(dev_priv); | |
12389 | intel_check_pch_fifo_underruns(dev_priv); | |
b9001114 | 12390 | |
e62929b3 ML |
12391 | if (!crtc->state->active) { |
12392 | /* | |
12393 | * Make sure we don't call initial_watermarks | |
12394 | * for ILK-style watermark updates. | |
ff32c54e VS |
12395 | * |
12396 | * No clue what this is supposed to achieve. | |
e62929b3 | 12397 | */ |
ff32c54e | 12398 | if (INTEL_GEN(dev_priv) >= 9) |
e62929b3 ML |
12399 | dev_priv->display.initial_watermarks(intel_state, |
12400 | to_intel_crtc_state(crtc->state)); | |
e62929b3 | 12401 | } |
a539205a | 12402 | } |
b8cecdf5 | 12403 | } |
7758a113 | 12404 | |
ea9d758d DV |
12405 | /* Only after disabling all output pipelines that will be changed can we |
12406 | * update the the output configuration. */ | |
4740b0f2 | 12407 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 12408 | |
565602d7 | 12409 | if (intel_state->modeset) { |
4740b0f2 | 12410 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); |
33c8df89 | 12411 | |
b0587e4d | 12412 | intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual); |
f6d1973d | 12413 | |
656d1b89 L |
12414 | /* |
12415 | * SKL workaround: bspec recommends we disable the SAGV when we | |
12416 | * have more then one pipe enabled | |
12417 | */ | |
56feca91 | 12418 | if (!intel_can_enable_sagv(state)) |
16dcdc4e | 12419 | intel_disable_sagv(dev_priv); |
656d1b89 | 12420 | |
677100ce | 12421 | intel_modeset_verify_disabled(dev, state); |
4740b0f2 | 12422 | } |
47fab737 | 12423 | |
896e5bb0 | 12424 | /* Complete the events for pipes that have now been disabled */ |
aa5e9b47 ML |
12425 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
12426 | bool modeset = needs_modeset(new_crtc_state); | |
80715b2f | 12427 | |
1f7528c4 | 12428 | /* Complete events for now disable pipes here. */ |
aa5e9b47 | 12429 | if (modeset && !new_crtc_state->active && new_crtc_state->event) { |
1f7528c4 | 12430 | spin_lock_irq(&dev->event_lock); |
aa5e9b47 | 12431 | drm_crtc_send_vblank_event(crtc, new_crtc_state->event); |
1f7528c4 DV |
12432 | spin_unlock_irq(&dev->event_lock); |
12433 | ||
aa5e9b47 | 12434 | new_crtc_state->event = NULL; |
1f7528c4 | 12435 | } |
177246a8 MR |
12436 | } |
12437 | ||
896e5bb0 L |
12438 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
12439 | dev_priv->display.update_crtcs(state, &crtc_vblank_mask); | |
12440 | ||
94f05024 DV |
12441 | /* FIXME: We should call drm_atomic_helper_commit_hw_done() here |
12442 | * already, but still need the state for the delayed optimization. To | |
12443 | * fix this: | |
12444 | * - wrap the optimization/post_plane_update stuff into a per-crtc work. | |
12445 | * - schedule that vblank worker _before_ calling hw_done | |
12446 | * - at the start of commit_tail, cancel it _synchrously | |
12447 | * - switch over to the vblank wait helper in the core after that since | |
12448 | * we don't need out special handling any more. | |
12449 | */ | |
5a21b665 DV |
12450 | if (!state->legacy_cursor_update) |
12451 | intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask); | |
12452 | ||
12453 | /* | |
12454 | * Now that the vblank has passed, we can go ahead and program the | |
12455 | * optimal watermarks on platforms that need two-step watermark | |
12456 | * programming. | |
12457 | * | |
12458 | * TODO: Move this (and other cleanup) to an async worker eventually. | |
12459 | */ | |
aa5e9b47 ML |
12460 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
12461 | intel_cstate = to_intel_crtc_state(new_crtc_state); | |
5a21b665 DV |
12462 | |
12463 | if (dev_priv->display.optimize_watermarks) | |
ccf010fb ML |
12464 | dev_priv->display.optimize_watermarks(intel_state, |
12465 | intel_cstate); | |
5a21b665 DV |
12466 | } |
12467 | ||
aa5e9b47 | 12468 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
5a21b665 DV |
12469 | intel_post_plane_update(to_intel_crtc_state(old_crtc_state)); |
12470 | ||
12471 | if (put_domains[i]) | |
12472 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
12473 | ||
aa5e9b47 | 12474 | intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state); |
5a21b665 DV |
12475 | } |
12476 | ||
56feca91 | 12477 | if (intel_state->modeset && intel_can_enable_sagv(state)) |
16dcdc4e | 12478 | intel_enable_sagv(dev_priv); |
656d1b89 | 12479 | |
94f05024 DV |
12480 | drm_atomic_helper_commit_hw_done(state); |
12481 | ||
d5553c09 CW |
12482 | if (intel_state->modeset) { |
12483 | /* As one of the primary mmio accessors, KMS has a high | |
12484 | * likelihood of triggering bugs in unclaimed access. After we | |
12485 | * finish modesetting, see if an error has been flagged, and if | |
12486 | * so enable debugging for the next modeset - and hope we catch | |
12487 | * the culprit. | |
12488 | */ | |
12489 | intel_uncore_arm_unclaimed_mmio_detection(dev_priv); | |
5a21b665 | 12490 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); |
d5553c09 | 12491 | } |
5a21b665 | 12492 | |
5a21b665 | 12493 | drm_atomic_helper_cleanup_planes(dev, state); |
5a21b665 | 12494 | |
ea0000f0 DV |
12495 | drm_atomic_helper_commit_cleanup_done(state); |
12496 | ||
0853695c | 12497 | drm_atomic_state_put(state); |
f30da187 | 12498 | |
ba318c61 | 12499 | intel_atomic_helper_free_state(dev_priv); |
94f05024 DV |
12500 | } |
12501 | ||
12502 | static void intel_atomic_commit_work(struct work_struct *work) | |
12503 | { | |
c004a90b CW |
12504 | struct drm_atomic_state *state = |
12505 | container_of(work, struct drm_atomic_state, commit_work); | |
12506 | ||
94f05024 DV |
12507 | intel_atomic_commit_tail(state); |
12508 | } | |
12509 | ||
c004a90b CW |
12510 | static int __i915_sw_fence_call |
12511 | intel_atomic_commit_ready(struct i915_sw_fence *fence, | |
12512 | enum i915_sw_fence_notify notify) | |
12513 | { | |
12514 | struct intel_atomic_state *state = | |
12515 | container_of(fence, struct intel_atomic_state, commit_ready); | |
12516 | ||
12517 | switch (notify) { | |
12518 | case FENCE_COMPLETE: | |
42b062b0 | 12519 | /* we do blocking waits in the worker, nothing to do here */ |
c004a90b | 12520 | break; |
c004a90b | 12521 | case FENCE_FREE: |
eb955eee CW |
12522 | { |
12523 | struct intel_atomic_helper *helper = | |
12524 | &to_i915(state->base.dev)->atomic_helper; | |
12525 | ||
12526 | if (llist_add(&state->freed, &helper->free_list)) | |
12527 | schedule_work(&helper->free_work); | |
12528 | break; | |
12529 | } | |
c004a90b CW |
12530 | } |
12531 | ||
12532 | return NOTIFY_DONE; | |
12533 | } | |
12534 | ||
6c9c1b38 DV |
12535 | static void intel_atomic_track_fbs(struct drm_atomic_state *state) |
12536 | { | |
aa5e9b47 | 12537 | struct drm_plane_state *old_plane_state, *new_plane_state; |
6c9c1b38 | 12538 | struct drm_plane *plane; |
6c9c1b38 DV |
12539 | int i; |
12540 | ||
aa5e9b47 | 12541 | for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) |
faf5bf0a | 12542 | i915_gem_track_fb(intel_fb_obj(old_plane_state->fb), |
aa5e9b47 | 12543 | intel_fb_obj(new_plane_state->fb), |
faf5bf0a | 12544 | to_intel_plane(plane)->frontbuffer_bit); |
6c9c1b38 DV |
12545 | } |
12546 | ||
94f05024 DV |
12547 | /** |
12548 | * intel_atomic_commit - commit validated state object | |
12549 | * @dev: DRM device | |
12550 | * @state: the top-level driver state object | |
12551 | * @nonblock: nonblocking commit | |
12552 | * | |
12553 | * This function commits a top-level state object that has been validated | |
12554 | * with drm_atomic_helper_check(). | |
12555 | * | |
94f05024 DV |
12556 | * RETURNS |
12557 | * Zero for success or -errno. | |
12558 | */ | |
12559 | static int intel_atomic_commit(struct drm_device *dev, | |
12560 | struct drm_atomic_state *state, | |
12561 | bool nonblock) | |
12562 | { | |
12563 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
fac5e23e | 12564 | struct drm_i915_private *dev_priv = to_i915(dev); |
94f05024 DV |
12565 | int ret = 0; |
12566 | ||
94f05024 DV |
12567 | ret = drm_atomic_helper_setup_commit(state, nonblock); |
12568 | if (ret) | |
12569 | return ret; | |
12570 | ||
c004a90b CW |
12571 | drm_atomic_state_get(state); |
12572 | i915_sw_fence_init(&intel_state->commit_ready, | |
12573 | intel_atomic_commit_ready); | |
94f05024 | 12574 | |
d07f0e59 | 12575 | ret = intel_atomic_prepare_commit(dev, state); |
94f05024 DV |
12576 | if (ret) { |
12577 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); | |
c004a90b | 12578 | i915_sw_fence_commit(&intel_state->commit_ready); |
94f05024 DV |
12579 | return ret; |
12580 | } | |
12581 | ||
440df938 VS |
12582 | /* |
12583 | * The intel_legacy_cursor_update() fast path takes care | |
12584 | * of avoiding the vblank waits for simple cursor | |
12585 | * movement and flips. For cursor on/off and size changes, | |
12586 | * we want to perform the vblank waits so that watermark | |
12587 | * updates happen during the correct frames. Gen9+ have | |
12588 | * double buffered watermarks and so shouldn't need this. | |
12589 | * | |
12590 | * Do this after drm_atomic_helper_setup_commit() and | |
12591 | * intel_atomic_prepare_commit() because we still want | |
12592 | * to skip the flip and fb cleanup waits. Although that | |
12593 | * does risk yanking the mapping from under the display | |
12594 | * engine. | |
12595 | * | |
12596 | * FIXME doing watermarks and fb cleanup from a vblank worker | |
12597 | * (assuming we had any) would solve these problems. | |
12598 | */ | |
12599 | if (INTEL_GEN(dev_priv) < 9) | |
12600 | state->legacy_cursor_update = false; | |
12601 | ||
0806f4ee ML |
12602 | ret = drm_atomic_helper_swap_state(state, true); |
12603 | if (ret) { | |
12604 | i915_sw_fence_commit(&intel_state->commit_ready); | |
12605 | ||
0806f4ee | 12606 | drm_atomic_helper_cleanup_planes(dev, state); |
0806f4ee ML |
12607 | return ret; |
12608 | } | |
94f05024 | 12609 | dev_priv->wm.distrust_bios_wm = false; |
3c0fb588 | 12610 | intel_shared_dpll_swap_state(state); |
6c9c1b38 | 12611 | intel_atomic_track_fbs(state); |
94f05024 | 12612 | |
c3b32658 ML |
12613 | if (intel_state->modeset) { |
12614 | memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, | |
12615 | sizeof(intel_state->min_pixclk)); | |
12616 | dev_priv->active_crtcs = intel_state->active_crtcs; | |
bb0f4aab VS |
12617 | dev_priv->cdclk.logical = intel_state->cdclk.logical; |
12618 | dev_priv->cdclk.actual = intel_state->cdclk.actual; | |
c3b32658 ML |
12619 | } |
12620 | ||
0853695c | 12621 | drm_atomic_state_get(state); |
42b062b0 | 12622 | INIT_WORK(&state->commit_work, intel_atomic_commit_work); |
c004a90b CW |
12623 | |
12624 | i915_sw_fence_commit(&intel_state->commit_ready); | |
42b062b0 DV |
12625 | if (nonblock) |
12626 | queue_work(system_unbound_wq, &state->commit_work); | |
12627 | else | |
94f05024 | 12628 | intel_atomic_commit_tail(state); |
42b062b0 | 12629 | |
75714940 | 12630 | |
74c090b1 | 12631 | return 0; |
7f27126e JB |
12632 | } |
12633 | ||
f6e5b160 | 12634 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
3fab2f09 | 12635 | .gamma_set = drm_atomic_helper_legacy_gamma_set, |
74c090b1 | 12636 | .set_config = drm_atomic_helper_set_config, |
f6e5b160 | 12637 | .destroy = intel_crtc_destroy, |
4c01ded5 | 12638 | .page_flip = drm_atomic_helper_page_flip, |
1356837e MR |
12639 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
12640 | .atomic_destroy_state = intel_crtc_destroy_state, | |
8c6b709d | 12641 | .set_crc_source = intel_crtc_set_crc_source, |
f6e5b160 CW |
12642 | }; |
12643 | ||
74d290f8 CW |
12644 | struct wait_rps_boost { |
12645 | struct wait_queue_entry wait; | |
12646 | ||
12647 | struct drm_crtc *crtc; | |
12648 | struct drm_i915_gem_request *request; | |
12649 | }; | |
12650 | ||
12651 | static int do_rps_boost(struct wait_queue_entry *_wait, | |
12652 | unsigned mode, int sync, void *key) | |
12653 | { | |
12654 | struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait); | |
12655 | struct drm_i915_gem_request *rq = wait->request; | |
12656 | ||
12657 | gen6_rps_boost(rq, NULL); | |
12658 | i915_gem_request_put(rq); | |
12659 | ||
12660 | drm_crtc_vblank_put(wait->crtc); | |
12661 | ||
12662 | list_del(&wait->wait.entry); | |
12663 | kfree(wait); | |
12664 | return 1; | |
12665 | } | |
12666 | ||
12667 | static void add_rps_boost_after_vblank(struct drm_crtc *crtc, | |
12668 | struct dma_fence *fence) | |
12669 | { | |
12670 | struct wait_rps_boost *wait; | |
12671 | ||
12672 | if (!dma_fence_is_i915(fence)) | |
12673 | return; | |
12674 | ||
12675 | if (INTEL_GEN(to_i915(crtc->dev)) < 6) | |
12676 | return; | |
12677 | ||
12678 | if (drm_crtc_vblank_get(crtc)) | |
12679 | return; | |
12680 | ||
12681 | wait = kmalloc(sizeof(*wait), GFP_KERNEL); | |
12682 | if (!wait) { | |
12683 | drm_crtc_vblank_put(crtc); | |
12684 | return; | |
12685 | } | |
12686 | ||
12687 | wait->request = to_request(dma_fence_get(fence)); | |
12688 | wait->crtc = crtc; | |
12689 | ||
12690 | wait->wait.func = do_rps_boost; | |
12691 | wait->wait.flags = 0; | |
12692 | ||
12693 | add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait); | |
12694 | } | |
12695 | ||
6beb8c23 MR |
12696 | /** |
12697 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
12698 | * @plane: drm plane to prepare for | |
12699 | * @fb: framebuffer to prepare for presentation | |
12700 | * | |
12701 | * Prepares a framebuffer for usage on a display plane. Generally this | |
12702 | * involves pinning the underlying object and updating the frontbuffer tracking | |
12703 | * bits. Some older platforms need special physical address handling for | |
12704 | * cursor planes. | |
12705 | * | |
f935675f ML |
12706 | * Must be called with struct_mutex held. |
12707 | * | |
6beb8c23 MR |
12708 | * Returns 0 on success, negative error code on failure. |
12709 | */ | |
12710 | int | |
12711 | intel_prepare_plane_fb(struct drm_plane *plane, | |
1832040d | 12712 | struct drm_plane_state *new_state) |
465c120c | 12713 | { |
c004a90b CW |
12714 | struct intel_atomic_state *intel_state = |
12715 | to_intel_atomic_state(new_state->state); | |
b7f05d4a | 12716 | struct drm_i915_private *dev_priv = to_i915(plane->dev); |
844f9111 | 12717 | struct drm_framebuffer *fb = new_state->fb; |
6beb8c23 | 12718 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1ee49399 | 12719 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
c004a90b | 12720 | int ret; |
465c120c | 12721 | |
5008e874 ML |
12722 | if (old_obj) { |
12723 | struct drm_crtc_state *crtc_state = | |
c004a90b CW |
12724 | drm_atomic_get_existing_crtc_state(new_state->state, |
12725 | plane->state->crtc); | |
5008e874 ML |
12726 | |
12727 | /* Big Hammer, we also need to ensure that any pending | |
12728 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
12729 | * current scanout is retired before unpinning the old | |
12730 | * framebuffer. Note that we rely on userspace rendering | |
12731 | * into the buffer attached to the pipe they are waiting | |
12732 | * on. If not, userspace generates a GPU hang with IPEHR | |
12733 | * point to the MI_WAIT_FOR_EVENT. | |
12734 | * | |
12735 | * This should only fail upon a hung GPU, in which case we | |
12736 | * can safely continue. | |
12737 | */ | |
c004a90b CW |
12738 | if (needs_modeset(crtc_state)) { |
12739 | ret = i915_sw_fence_await_reservation(&intel_state->commit_ready, | |
12740 | old_obj->resv, NULL, | |
12741 | false, 0, | |
12742 | GFP_KERNEL); | |
12743 | if (ret < 0) | |
12744 | return ret; | |
f4457ae7 | 12745 | } |
5008e874 ML |
12746 | } |
12747 | ||
c004a90b CW |
12748 | if (new_state->fence) { /* explicit fencing */ |
12749 | ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready, | |
12750 | new_state->fence, | |
12751 | I915_FENCE_TIMEOUT, | |
12752 | GFP_KERNEL); | |
12753 | if (ret < 0) | |
12754 | return ret; | |
12755 | } | |
12756 | ||
c37efb99 CW |
12757 | if (!obj) |
12758 | return 0; | |
12759 | ||
4d3088c7 | 12760 | ret = i915_gem_object_pin_pages(obj); |
fd70075f CW |
12761 | if (ret) |
12762 | return ret; | |
12763 | ||
4d3088c7 CW |
12764 | ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex); |
12765 | if (ret) { | |
12766 | i915_gem_object_unpin_pages(obj); | |
12767 | return ret; | |
12768 | } | |
12769 | ||
fd70075f CW |
12770 | if (plane->type == DRM_PLANE_TYPE_CURSOR && |
12771 | INTEL_INFO(dev_priv)->cursor_needs_physical) { | |
12772 | const int align = intel_cursor_alignment(dev_priv); | |
12773 | ||
12774 | ret = i915_gem_object_attach_phys(obj, align); | |
12775 | } else { | |
12776 | struct i915_vma *vma; | |
12777 | ||
12778 | vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation); | |
12779 | if (!IS_ERR(vma)) | |
12780 | to_intel_plane_state(new_state)->vma = vma; | |
12781 | else | |
12782 | ret = PTR_ERR(vma); | |
12783 | } | |
12784 | ||
12785 | i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY); | |
12786 | ||
12787 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
4d3088c7 | 12788 | i915_gem_object_unpin_pages(obj); |
fd70075f CW |
12789 | if (ret) |
12790 | return ret; | |
12791 | ||
c004a90b | 12792 | if (!new_state->fence) { /* implicit fencing */ |
74d290f8 CW |
12793 | struct dma_fence *fence; |
12794 | ||
c004a90b CW |
12795 | ret = i915_sw_fence_await_reservation(&intel_state->commit_ready, |
12796 | obj->resv, NULL, | |
12797 | false, I915_FENCE_TIMEOUT, | |
12798 | GFP_KERNEL); | |
12799 | if (ret < 0) | |
12800 | return ret; | |
74d290f8 CW |
12801 | |
12802 | fence = reservation_object_get_excl_rcu(obj->resv); | |
12803 | if (fence) { | |
12804 | add_rps_boost_after_vblank(new_state->crtc, fence); | |
12805 | dma_fence_put(fence); | |
12806 | } | |
12807 | } else { | |
12808 | add_rps_boost_after_vblank(new_state->crtc, new_state->fence); | |
c004a90b | 12809 | } |
5a21b665 | 12810 | |
d07f0e59 | 12811 | return 0; |
6beb8c23 MR |
12812 | } |
12813 | ||
38f3ce3a MR |
12814 | /** |
12815 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
12816 | * @plane: drm plane to clean up for | |
12817 | * @fb: old framebuffer that was on plane | |
12818 | * | |
12819 | * Cleans up a framebuffer that has just been removed from a plane. | |
f935675f ML |
12820 | * |
12821 | * Must be called with struct_mutex held. | |
38f3ce3a MR |
12822 | */ |
12823 | void | |
12824 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
1832040d | 12825 | struct drm_plane_state *old_state) |
38f3ce3a | 12826 | { |
be1e3415 | 12827 | struct i915_vma *vma; |
38f3ce3a | 12828 | |
be1e3415 CW |
12829 | /* Should only be called after a successful intel_prepare_plane_fb()! */ |
12830 | vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma); | |
fd70075f CW |
12831 | if (vma) { |
12832 | mutex_lock(&plane->dev->struct_mutex); | |
be1e3415 | 12833 | intel_unpin_fb_vma(vma); |
fd70075f CW |
12834 | mutex_unlock(&plane->dev->struct_mutex); |
12835 | } | |
465c120c MR |
12836 | } |
12837 | ||
6156a456 CK |
12838 | int |
12839 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
12840 | { | |
5b7280f0 | 12841 | struct drm_i915_private *dev_priv; |
6156a456 | 12842 | int max_scale; |
5b7280f0 | 12843 | int crtc_clock, max_dotclk; |
6156a456 | 12844 | |
bf8a0af0 | 12845 | if (!intel_crtc || !crtc_state->base.enable) |
6156a456 CK |
12846 | return DRM_PLANE_HELPER_NO_SCALING; |
12847 | ||
5b7280f0 ACO |
12848 | dev_priv = to_i915(intel_crtc->base.dev); |
12849 | ||
6156a456 | 12850 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; |
5b7280f0 ACO |
12851 | max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk; |
12852 | ||
12853 | if (IS_GEMINILAKE(dev_priv)) | |
12854 | max_dotclk *= 2; | |
6156a456 | 12855 | |
5b7280f0 | 12856 | if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock)) |
6156a456 CK |
12857 | return DRM_PLANE_HELPER_NO_SCALING; |
12858 | ||
12859 | /* | |
12860 | * skl max scale is lower of: | |
12861 | * close to 3 but not 3, -1 is for that purpose | |
12862 | * or | |
12863 | * cdclk/crtc_clock | |
12864 | */ | |
5b7280f0 ACO |
12865 | max_scale = min((1 << 16) * 3 - 1, |
12866 | (1 << 8) * ((max_dotclk << 8) / crtc_clock)); | |
6156a456 CK |
12867 | |
12868 | return max_scale; | |
12869 | } | |
12870 | ||
465c120c | 12871 | static int |
282dbf9b | 12872 | intel_check_primary_plane(struct intel_plane *plane, |
061e4b8d | 12873 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
12874 | struct intel_plane_state *state) |
12875 | { | |
282dbf9b | 12876 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
2b875c22 | 12877 | struct drm_crtc *crtc = state->base.crtc; |
6156a456 | 12878 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
12879 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
12880 | bool can_position = false; | |
b63a16f6 | 12881 | int ret; |
465c120c | 12882 | |
b63a16f6 | 12883 | if (INTEL_GEN(dev_priv) >= 9) { |
693bdc28 VS |
12884 | /* use scaler when colorkey is not required */ |
12885 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { | |
12886 | min_scale = 1; | |
12887 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
12888 | } | |
d8106366 | 12889 | can_position = true; |
6156a456 | 12890 | } |
d8106366 | 12891 | |
cc926387 DV |
12892 | ret = drm_plane_helper_check_state(&state->base, |
12893 | &state->clip, | |
12894 | min_scale, max_scale, | |
12895 | can_position, true); | |
b63a16f6 VS |
12896 | if (ret) |
12897 | return ret; | |
12898 | ||
cc926387 | 12899 | if (!state->base.fb) |
b63a16f6 VS |
12900 | return 0; |
12901 | ||
12902 | if (INTEL_GEN(dev_priv) >= 9) { | |
12903 | ret = skl_check_plane_surface(state); | |
12904 | if (ret) | |
12905 | return ret; | |
a0864d59 VS |
12906 | |
12907 | state->ctl = skl_plane_ctl(crtc_state, state); | |
12908 | } else { | |
5b7fcc44 VS |
12909 | ret = i9xx_check_plane_surface(state); |
12910 | if (ret) | |
12911 | return ret; | |
12912 | ||
a0864d59 | 12913 | state->ctl = i9xx_plane_ctl(crtc_state, state); |
b63a16f6 VS |
12914 | } |
12915 | ||
12916 | return 0; | |
14af293f GP |
12917 | } |
12918 | ||
5a21b665 DV |
12919 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
12920 | struct drm_crtc_state *old_crtc_state) | |
12921 | { | |
12922 | struct drm_device *dev = crtc->dev; | |
62e0fb88 | 12923 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 | 12924 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
b707aa50 L |
12925 | struct intel_crtc_state *intel_cstate = |
12926 | to_intel_crtc_state(crtc->state); | |
ccf010fb | 12927 | struct intel_crtc_state *old_intel_cstate = |
5a21b665 | 12928 | to_intel_crtc_state(old_crtc_state); |
ccf010fb ML |
12929 | struct intel_atomic_state *old_intel_state = |
12930 | to_intel_atomic_state(old_crtc_state->state); | |
5a21b665 DV |
12931 | bool modeset = needs_modeset(crtc->state); |
12932 | ||
567f0792 ML |
12933 | if (!modeset && |
12934 | (intel_cstate->base.color_mgmt_changed || | |
12935 | intel_cstate->update_pipe)) { | |
12936 | intel_color_set_csc(crtc->state); | |
12937 | intel_color_load_luts(crtc->state); | |
12938 | } | |
12939 | ||
5a21b665 DV |
12940 | /* Perform vblank evasion around commit operation */ |
12941 | intel_pipe_update_start(intel_crtc); | |
12942 | ||
12943 | if (modeset) | |
e62929b3 | 12944 | goto out; |
5a21b665 | 12945 | |
ccf010fb ML |
12946 | if (intel_cstate->update_pipe) |
12947 | intel_update_pipe_config(intel_crtc, old_intel_cstate); | |
12948 | else if (INTEL_GEN(dev_priv) >= 9) | |
5a21b665 | 12949 | skl_detach_scalers(intel_crtc); |
62e0fb88 | 12950 | |
e62929b3 | 12951 | out: |
ccf010fb ML |
12952 | if (dev_priv->display.atomic_update_watermarks) |
12953 | dev_priv->display.atomic_update_watermarks(old_intel_state, | |
12954 | intel_cstate); | |
5a21b665 DV |
12955 | } |
12956 | ||
12957 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, | |
12958 | struct drm_crtc_state *old_crtc_state) | |
12959 | { | |
12960 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12961 | ||
8b5d27b9 | 12962 | intel_pipe_update_end(intel_crtc); |
5a21b665 DV |
12963 | } |
12964 | ||
cf4c7c12 | 12965 | /** |
4a3b8769 MR |
12966 | * intel_plane_destroy - destroy a plane |
12967 | * @plane: plane to destroy | |
cf4c7c12 | 12968 | * |
4a3b8769 MR |
12969 | * Common destruction function for all types of planes (primary, cursor, |
12970 | * sprite). | |
cf4c7c12 | 12971 | */ |
4a3b8769 | 12972 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c | 12973 | { |
465c120c | 12974 | drm_plane_cleanup(plane); |
69ae561f | 12975 | kfree(to_intel_plane(plane)); |
465c120c MR |
12976 | } |
12977 | ||
714244e2 BW |
12978 | static bool i8xx_mod_supported(uint32_t format, uint64_t modifier) |
12979 | { | |
12980 | switch (format) { | |
12981 | case DRM_FORMAT_C8: | |
12982 | case DRM_FORMAT_RGB565: | |
12983 | case DRM_FORMAT_XRGB1555: | |
12984 | case DRM_FORMAT_XRGB8888: | |
12985 | return modifier == DRM_FORMAT_MOD_LINEAR || | |
12986 | modifier == I915_FORMAT_MOD_X_TILED; | |
12987 | default: | |
12988 | return false; | |
12989 | } | |
12990 | } | |
12991 | ||
12992 | static bool i965_mod_supported(uint32_t format, uint64_t modifier) | |
12993 | { | |
12994 | switch (format) { | |
12995 | case DRM_FORMAT_C8: | |
12996 | case DRM_FORMAT_RGB565: | |
12997 | case DRM_FORMAT_XRGB8888: | |
12998 | case DRM_FORMAT_XBGR8888: | |
12999 | case DRM_FORMAT_XRGB2101010: | |
13000 | case DRM_FORMAT_XBGR2101010: | |
13001 | return modifier == DRM_FORMAT_MOD_LINEAR || | |
13002 | modifier == I915_FORMAT_MOD_X_TILED; | |
13003 | default: | |
13004 | return false; | |
13005 | } | |
13006 | } | |
13007 | ||
13008 | static bool skl_mod_supported(uint32_t format, uint64_t modifier) | |
13009 | { | |
13010 | switch (format) { | |
13011 | case DRM_FORMAT_XRGB8888: | |
13012 | case DRM_FORMAT_XBGR8888: | |
13013 | case DRM_FORMAT_ARGB8888: | |
13014 | case DRM_FORMAT_ABGR8888: | |
13015 | if (modifier == I915_FORMAT_MOD_Yf_TILED_CCS || | |
13016 | modifier == I915_FORMAT_MOD_Y_TILED_CCS) | |
13017 | return true; | |
13018 | /* fall through */ | |
13019 | case DRM_FORMAT_RGB565: | |
13020 | case DRM_FORMAT_XRGB2101010: | |
13021 | case DRM_FORMAT_XBGR2101010: | |
13022 | case DRM_FORMAT_YUYV: | |
13023 | case DRM_FORMAT_YVYU: | |
13024 | case DRM_FORMAT_UYVY: | |
13025 | case DRM_FORMAT_VYUY: | |
13026 | if (modifier == I915_FORMAT_MOD_Yf_TILED) | |
13027 | return true; | |
13028 | /* fall through */ | |
13029 | case DRM_FORMAT_C8: | |
13030 | if (modifier == DRM_FORMAT_MOD_LINEAR || | |
13031 | modifier == I915_FORMAT_MOD_X_TILED || | |
13032 | modifier == I915_FORMAT_MOD_Y_TILED) | |
13033 | return true; | |
13034 | /* fall through */ | |
13035 | default: | |
13036 | return false; | |
13037 | } | |
13038 | } | |
13039 | ||
13040 | static bool intel_primary_plane_format_mod_supported(struct drm_plane *plane, | |
13041 | uint32_t format, | |
13042 | uint64_t modifier) | |
13043 | { | |
13044 | struct drm_i915_private *dev_priv = to_i915(plane->dev); | |
13045 | ||
13046 | if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID)) | |
13047 | return false; | |
13048 | ||
13049 | if ((modifier >> 56) != DRM_FORMAT_MOD_VENDOR_INTEL && | |
13050 | modifier != DRM_FORMAT_MOD_LINEAR) | |
13051 | return false; | |
13052 | ||
13053 | if (INTEL_GEN(dev_priv) >= 9) | |
13054 | return skl_mod_supported(format, modifier); | |
13055 | else if (INTEL_GEN(dev_priv) >= 4) | |
13056 | return i965_mod_supported(format, modifier); | |
13057 | else | |
13058 | return i8xx_mod_supported(format, modifier); | |
13059 | ||
13060 | unreachable(); | |
13061 | } | |
13062 | ||
13063 | static bool intel_cursor_plane_format_mod_supported(struct drm_plane *plane, | |
13064 | uint32_t format, | |
13065 | uint64_t modifier) | |
13066 | { | |
13067 | if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID)) | |
13068 | return false; | |
13069 | ||
13070 | return modifier == DRM_FORMAT_MOD_LINEAR && format == DRM_FORMAT_ARGB8888; | |
13071 | } | |
13072 | ||
13073 | static struct drm_plane_funcs intel_plane_funcs = { | |
70a101f8 MR |
13074 | .update_plane = drm_atomic_helper_update_plane, |
13075 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 13076 | .destroy = intel_plane_destroy, |
a98b3431 MR |
13077 | .atomic_get_property = intel_plane_atomic_get_property, |
13078 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
13079 | .atomic_duplicate_state = intel_plane_duplicate_state, |
13080 | .atomic_destroy_state = intel_plane_destroy_state, | |
714244e2 | 13081 | .format_mod_supported = intel_primary_plane_format_mod_supported, |
465c120c MR |
13082 | }; |
13083 | ||
f79f2692 ML |
13084 | static int |
13085 | intel_legacy_cursor_update(struct drm_plane *plane, | |
13086 | struct drm_crtc *crtc, | |
13087 | struct drm_framebuffer *fb, | |
13088 | int crtc_x, int crtc_y, | |
13089 | unsigned int crtc_w, unsigned int crtc_h, | |
13090 | uint32_t src_x, uint32_t src_y, | |
34a2ab5e DV |
13091 | uint32_t src_w, uint32_t src_h, |
13092 | struct drm_modeset_acquire_ctx *ctx) | |
f79f2692 ML |
13093 | { |
13094 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
13095 | int ret; | |
13096 | struct drm_plane_state *old_plane_state, *new_plane_state; | |
13097 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
13098 | struct drm_framebuffer *old_fb; | |
13099 | struct drm_crtc_state *crtc_state = crtc->state; | |
fd70075f | 13100 | struct i915_vma *old_vma, *vma; |
f79f2692 ML |
13101 | |
13102 | /* | |
13103 | * When crtc is inactive or there is a modeset pending, | |
13104 | * wait for it to complete in the slowpath | |
13105 | */ | |
13106 | if (!crtc_state->active || needs_modeset(crtc_state) || | |
13107 | to_intel_crtc_state(crtc_state)->update_pipe) | |
13108 | goto slow; | |
13109 | ||
13110 | old_plane_state = plane->state; | |
13111 | ||
13112 | /* | |
13113 | * If any parameters change that may affect watermarks, | |
13114 | * take the slowpath. Only changing fb or position should be | |
13115 | * in the fastpath. | |
13116 | */ | |
13117 | if (old_plane_state->crtc != crtc || | |
13118 | old_plane_state->src_w != src_w || | |
13119 | old_plane_state->src_h != src_h || | |
13120 | old_plane_state->crtc_w != crtc_w || | |
13121 | old_plane_state->crtc_h != crtc_h || | |
a5509abd | 13122 | !old_plane_state->fb != !fb) |
f79f2692 ML |
13123 | goto slow; |
13124 | ||
13125 | new_plane_state = intel_plane_duplicate_state(plane); | |
13126 | if (!new_plane_state) | |
13127 | return -ENOMEM; | |
13128 | ||
13129 | drm_atomic_set_fb_for_plane(new_plane_state, fb); | |
13130 | ||
13131 | new_plane_state->src_x = src_x; | |
13132 | new_plane_state->src_y = src_y; | |
13133 | new_plane_state->src_w = src_w; | |
13134 | new_plane_state->src_h = src_h; | |
13135 | new_plane_state->crtc_x = crtc_x; | |
13136 | new_plane_state->crtc_y = crtc_y; | |
13137 | new_plane_state->crtc_w = crtc_w; | |
13138 | new_plane_state->crtc_h = crtc_h; | |
13139 | ||
13140 | ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state), | |
13141 | to_intel_plane_state(new_plane_state)); | |
13142 | if (ret) | |
13143 | goto out_free; | |
13144 | ||
f79f2692 ML |
13145 | ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex); |
13146 | if (ret) | |
13147 | goto out_free; | |
13148 | ||
13149 | if (INTEL_INFO(dev_priv)->cursor_needs_physical) { | |
fabac484 | 13150 | int align = intel_cursor_alignment(dev_priv); |
f79f2692 ML |
13151 | |
13152 | ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align); | |
13153 | if (ret) { | |
13154 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
13155 | goto out_unlock; | |
13156 | } | |
13157 | } else { | |
f79f2692 ML |
13158 | vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation); |
13159 | if (IS_ERR(vma)) { | |
13160 | DRM_DEBUG_KMS("failed to pin object\n"); | |
13161 | ||
13162 | ret = PTR_ERR(vma); | |
13163 | goto out_unlock; | |
13164 | } | |
be1e3415 CW |
13165 | |
13166 | to_intel_plane_state(new_plane_state)->vma = vma; | |
f79f2692 ML |
13167 | } |
13168 | ||
13169 | old_fb = old_plane_state->fb; | |
be1e3415 | 13170 | old_vma = to_intel_plane_state(old_plane_state)->vma; |
f79f2692 ML |
13171 | |
13172 | i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb), | |
13173 | intel_plane->frontbuffer_bit); | |
13174 | ||
13175 | /* Swap plane state */ | |
13176 | new_plane_state->fence = old_plane_state->fence; | |
13177 | *to_intel_plane_state(old_plane_state) = *to_intel_plane_state(new_plane_state); | |
13178 | new_plane_state->fence = NULL; | |
13179 | new_plane_state->fb = old_fb; | |
fd70075f | 13180 | to_intel_plane_state(new_plane_state)->vma = NULL; |
f79f2692 | 13181 | |
72259536 VS |
13182 | if (plane->state->visible) { |
13183 | trace_intel_update_plane(plane, to_intel_crtc(crtc)); | |
282dbf9b | 13184 | intel_plane->update_plane(intel_plane, |
a5509abd VS |
13185 | to_intel_crtc_state(crtc->state), |
13186 | to_intel_plane_state(plane->state)); | |
72259536 VS |
13187 | } else { |
13188 | trace_intel_disable_plane(plane, to_intel_crtc(crtc)); | |
282dbf9b | 13189 | intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc)); |
72259536 | 13190 | } |
f79f2692 | 13191 | |
fd70075f CW |
13192 | if (old_vma) |
13193 | intel_unpin_fb_vma(old_vma); | |
f79f2692 ML |
13194 | |
13195 | out_unlock: | |
13196 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
13197 | out_free: | |
13198 | intel_plane_destroy_state(plane, new_plane_state); | |
13199 | return ret; | |
13200 | ||
f79f2692 ML |
13201 | slow: |
13202 | return drm_atomic_helper_update_plane(plane, crtc, fb, | |
13203 | crtc_x, crtc_y, crtc_w, crtc_h, | |
34a2ab5e | 13204 | src_x, src_y, src_w, src_h, ctx); |
f79f2692 ML |
13205 | } |
13206 | ||
13207 | static const struct drm_plane_funcs intel_cursor_plane_funcs = { | |
13208 | .update_plane = intel_legacy_cursor_update, | |
13209 | .disable_plane = drm_atomic_helper_disable_plane, | |
13210 | .destroy = intel_plane_destroy, | |
f79f2692 ML |
13211 | .atomic_get_property = intel_plane_atomic_get_property, |
13212 | .atomic_set_property = intel_plane_atomic_set_property, | |
13213 | .atomic_duplicate_state = intel_plane_duplicate_state, | |
13214 | .atomic_destroy_state = intel_plane_destroy_state, | |
714244e2 | 13215 | .format_mod_supported = intel_cursor_plane_format_mod_supported, |
f79f2692 ML |
13216 | }; |
13217 | ||
b079bd17 | 13218 | static struct intel_plane * |
580503c7 | 13219 | intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) |
465c120c | 13220 | { |
fca0ce2a VS |
13221 | struct intel_plane *primary = NULL; |
13222 | struct intel_plane_state *state = NULL; | |
465c120c | 13223 | const uint32_t *intel_primary_formats; |
93ca7e00 | 13224 | unsigned int supported_rotations; |
45e3743a | 13225 | unsigned int num_formats; |
714244e2 | 13226 | const uint64_t *modifiers; |
fca0ce2a | 13227 | int ret; |
465c120c MR |
13228 | |
13229 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
b079bd17 VS |
13230 | if (!primary) { |
13231 | ret = -ENOMEM; | |
fca0ce2a | 13232 | goto fail; |
b079bd17 | 13233 | } |
465c120c | 13234 | |
8e7d688b | 13235 | state = intel_create_plane_state(&primary->base); |
b079bd17 VS |
13236 | if (!state) { |
13237 | ret = -ENOMEM; | |
fca0ce2a | 13238 | goto fail; |
b079bd17 VS |
13239 | } |
13240 | ||
8e7d688b | 13241 | primary->base.state = &state->base; |
ea2c67bb | 13242 | |
465c120c MR |
13243 | primary->can_scale = false; |
13244 | primary->max_downscale = 1; | |
580503c7 | 13245 | if (INTEL_GEN(dev_priv) >= 9) { |
6156a456 | 13246 | primary->can_scale = true; |
af99ceda | 13247 | state->scaler_id = -1; |
6156a456 | 13248 | } |
465c120c | 13249 | primary->pipe = pipe; |
e3c566df VS |
13250 | /* |
13251 | * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS | |
13252 | * port is hooked to pipe B. Hence we want plane A feeding pipe B. | |
13253 | */ | |
13254 | if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4) | |
13255 | primary->plane = (enum plane) !pipe; | |
13256 | else | |
13257 | primary->plane = (enum plane) pipe; | |
b14e5848 | 13258 | primary->id = PLANE_PRIMARY; |
a9ff8714 | 13259 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 | 13260 | primary->check_plane = intel_check_primary_plane; |
465c120c | 13261 | |
714244e2 | 13262 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { |
6c0fd451 DL |
13263 | intel_primary_formats = skl_primary_formats; |
13264 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
714244e2 BW |
13265 | modifiers = skl_format_modifiers_ccs; |
13266 | ||
13267 | primary->update_plane = skylake_update_primary_plane; | |
13268 | primary->disable_plane = skylake_disable_primary_plane; | |
13269 | } else if (INTEL_GEN(dev_priv) >= 9) { | |
13270 | intel_primary_formats = skl_primary_formats; | |
13271 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
13272 | if (pipe < PIPE_C) | |
13273 | modifiers = skl_format_modifiers_ccs; | |
13274 | else | |
13275 | modifiers = skl_format_modifiers_noccs; | |
a8d201af ML |
13276 | |
13277 | primary->update_plane = skylake_update_primary_plane; | |
13278 | primary->disable_plane = skylake_disable_primary_plane; | |
580503c7 | 13279 | } else if (INTEL_GEN(dev_priv) >= 4) { |
568db4f2 DL |
13280 | intel_primary_formats = i965_primary_formats; |
13281 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
714244e2 | 13282 | modifiers = i9xx_format_modifiers; |
a8d201af ML |
13283 | |
13284 | primary->update_plane = i9xx_update_primary_plane; | |
13285 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 DL |
13286 | } else { |
13287 | intel_primary_formats = i8xx_primary_formats; | |
13288 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
714244e2 | 13289 | modifiers = i9xx_format_modifiers; |
a8d201af ML |
13290 | |
13291 | primary->update_plane = i9xx_update_primary_plane; | |
13292 | primary->disable_plane = i9xx_disable_primary_plane; | |
465c120c MR |
13293 | } |
13294 | ||
580503c7 VS |
13295 | if (INTEL_GEN(dev_priv) >= 9) |
13296 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, | |
13297 | 0, &intel_plane_funcs, | |
38573dc1 | 13298 | intel_primary_formats, num_formats, |
714244e2 | 13299 | modifiers, |
38573dc1 VS |
13300 | DRM_PLANE_TYPE_PRIMARY, |
13301 | "plane 1%c", pipe_name(pipe)); | |
9beb5fea | 13302 | else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) |
580503c7 VS |
13303 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, |
13304 | 0, &intel_plane_funcs, | |
38573dc1 | 13305 | intel_primary_formats, num_formats, |
714244e2 | 13306 | modifiers, |
38573dc1 VS |
13307 | DRM_PLANE_TYPE_PRIMARY, |
13308 | "primary %c", pipe_name(pipe)); | |
13309 | else | |
580503c7 VS |
13310 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, |
13311 | 0, &intel_plane_funcs, | |
38573dc1 | 13312 | intel_primary_formats, num_formats, |
714244e2 | 13313 | modifiers, |
38573dc1 VS |
13314 | DRM_PLANE_TYPE_PRIMARY, |
13315 | "plane %c", plane_name(primary->plane)); | |
fca0ce2a VS |
13316 | if (ret) |
13317 | goto fail; | |
48404c1e | 13318 | |
5481e27f | 13319 | if (INTEL_GEN(dev_priv) >= 9) { |
93ca7e00 | 13320 | supported_rotations = |
c2c446ad RF |
13321 | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | |
13322 | DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270; | |
4ea7be2b VS |
13323 | } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { |
13324 | supported_rotations = | |
c2c446ad RF |
13325 | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 | |
13326 | DRM_MODE_REFLECT_X; | |
5481e27f | 13327 | } else if (INTEL_GEN(dev_priv) >= 4) { |
93ca7e00 | 13328 | supported_rotations = |
c2c446ad | 13329 | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; |
93ca7e00 | 13330 | } else { |
c2c446ad | 13331 | supported_rotations = DRM_MODE_ROTATE_0; |
93ca7e00 VS |
13332 | } |
13333 | ||
5481e27f | 13334 | if (INTEL_GEN(dev_priv) >= 4) |
93ca7e00 | 13335 | drm_plane_create_rotation_property(&primary->base, |
c2c446ad | 13336 | DRM_MODE_ROTATE_0, |
93ca7e00 | 13337 | supported_rotations); |
48404c1e | 13338 | |
ea2c67bb MR |
13339 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
13340 | ||
b079bd17 | 13341 | return primary; |
fca0ce2a VS |
13342 | |
13343 | fail: | |
13344 | kfree(state); | |
13345 | kfree(primary); | |
13346 | ||
b079bd17 | 13347 | return ERR_PTR(ret); |
465c120c MR |
13348 | } |
13349 | ||
b079bd17 | 13350 | static struct intel_plane * |
b2d03b0d VS |
13351 | intel_cursor_plane_create(struct drm_i915_private *dev_priv, |
13352 | enum pipe pipe) | |
3d7d6510 | 13353 | { |
fca0ce2a VS |
13354 | struct intel_plane *cursor = NULL; |
13355 | struct intel_plane_state *state = NULL; | |
13356 | int ret; | |
3d7d6510 MR |
13357 | |
13358 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
b079bd17 VS |
13359 | if (!cursor) { |
13360 | ret = -ENOMEM; | |
fca0ce2a | 13361 | goto fail; |
b079bd17 | 13362 | } |
3d7d6510 | 13363 | |
8e7d688b | 13364 | state = intel_create_plane_state(&cursor->base); |
b079bd17 VS |
13365 | if (!state) { |
13366 | ret = -ENOMEM; | |
fca0ce2a | 13367 | goto fail; |
b079bd17 VS |
13368 | } |
13369 | ||
8e7d688b | 13370 | cursor->base.state = &state->base; |
ea2c67bb | 13371 | |
3d7d6510 MR |
13372 | cursor->can_scale = false; |
13373 | cursor->max_downscale = 1; | |
13374 | cursor->pipe = pipe; | |
13375 | cursor->plane = pipe; | |
b14e5848 | 13376 | cursor->id = PLANE_CURSOR; |
a9ff8714 | 13377 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
b2d03b0d VS |
13378 | |
13379 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { | |
13380 | cursor->update_plane = i845_update_cursor; | |
13381 | cursor->disable_plane = i845_disable_cursor; | |
659056f2 | 13382 | cursor->check_plane = i845_check_cursor; |
b2d03b0d VS |
13383 | } else { |
13384 | cursor->update_plane = i9xx_update_cursor; | |
13385 | cursor->disable_plane = i9xx_disable_cursor; | |
659056f2 | 13386 | cursor->check_plane = i9xx_check_cursor; |
b2d03b0d | 13387 | } |
3d7d6510 | 13388 | |
cd5dcbf1 VS |
13389 | cursor->cursor.base = ~0; |
13390 | cursor->cursor.cntl = ~0; | |
024faac7 VS |
13391 | |
13392 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv)) | |
13393 | cursor->cursor.size = ~0; | |
3d7d6510 | 13394 | |
580503c7 | 13395 | ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base, |
f79f2692 | 13396 | 0, &intel_cursor_plane_funcs, |
fca0ce2a VS |
13397 | intel_cursor_formats, |
13398 | ARRAY_SIZE(intel_cursor_formats), | |
714244e2 BW |
13399 | cursor_format_modifiers, |
13400 | DRM_PLANE_TYPE_CURSOR, | |
38573dc1 | 13401 | "cursor %c", pipe_name(pipe)); |
fca0ce2a VS |
13402 | if (ret) |
13403 | goto fail; | |
4398ad45 | 13404 | |
5481e27f | 13405 | if (INTEL_GEN(dev_priv) >= 4) |
93ca7e00 | 13406 | drm_plane_create_rotation_property(&cursor->base, |
c2c446ad RF |
13407 | DRM_MODE_ROTATE_0, |
13408 | DRM_MODE_ROTATE_0 | | |
13409 | DRM_MODE_ROTATE_180); | |
4398ad45 | 13410 | |
580503c7 | 13411 | if (INTEL_GEN(dev_priv) >= 9) |
af99ceda CK |
13412 | state->scaler_id = -1; |
13413 | ||
ea2c67bb MR |
13414 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
13415 | ||
b079bd17 | 13416 | return cursor; |
fca0ce2a VS |
13417 | |
13418 | fail: | |
13419 | kfree(state); | |
13420 | kfree(cursor); | |
13421 | ||
b079bd17 | 13422 | return ERR_PTR(ret); |
3d7d6510 MR |
13423 | } |
13424 | ||
1c74eeaf NM |
13425 | static void intel_crtc_init_scalers(struct intel_crtc *crtc, |
13426 | struct intel_crtc_state *crtc_state) | |
549e2bfb | 13427 | { |
65edccce VS |
13428 | struct intel_crtc_scaler_state *scaler_state = |
13429 | &crtc_state->scaler_state; | |
1c74eeaf | 13430 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
549e2bfb | 13431 | int i; |
549e2bfb | 13432 | |
1c74eeaf NM |
13433 | crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe]; |
13434 | if (!crtc->num_scalers) | |
13435 | return; | |
13436 | ||
65edccce VS |
13437 | for (i = 0; i < crtc->num_scalers; i++) { |
13438 | struct intel_scaler *scaler = &scaler_state->scalers[i]; | |
13439 | ||
13440 | scaler->in_use = 0; | |
13441 | scaler->mode = PS_SCALER_MODE_DYN; | |
549e2bfb CK |
13442 | } |
13443 | ||
13444 | scaler_state->scaler_id = -1; | |
13445 | } | |
13446 | ||
5ab0d85b | 13447 | static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) |
79e53945 JB |
13448 | { |
13449 | struct intel_crtc *intel_crtc; | |
f5de6e07 | 13450 | struct intel_crtc_state *crtc_state = NULL; |
b079bd17 VS |
13451 | struct intel_plane *primary = NULL; |
13452 | struct intel_plane *cursor = NULL; | |
a81d6fa0 | 13453 | int sprite, ret; |
79e53945 | 13454 | |
955382f3 | 13455 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
b079bd17 VS |
13456 | if (!intel_crtc) |
13457 | return -ENOMEM; | |
79e53945 | 13458 | |
f5de6e07 | 13459 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
b079bd17 VS |
13460 | if (!crtc_state) { |
13461 | ret = -ENOMEM; | |
f5de6e07 | 13462 | goto fail; |
b079bd17 | 13463 | } |
550acefd ACO |
13464 | intel_crtc->config = crtc_state; |
13465 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 13466 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 13467 | |
580503c7 | 13468 | primary = intel_primary_plane_create(dev_priv, pipe); |
b079bd17 VS |
13469 | if (IS_ERR(primary)) { |
13470 | ret = PTR_ERR(primary); | |
3d7d6510 | 13471 | goto fail; |
b079bd17 | 13472 | } |
d97d7b48 | 13473 | intel_crtc->plane_ids_mask |= BIT(primary->id); |
3d7d6510 | 13474 | |
a81d6fa0 | 13475 | for_each_sprite(dev_priv, pipe, sprite) { |
b079bd17 VS |
13476 | struct intel_plane *plane; |
13477 | ||
580503c7 | 13478 | plane = intel_sprite_plane_create(dev_priv, pipe, sprite); |
d2b2cbce | 13479 | if (IS_ERR(plane)) { |
b079bd17 VS |
13480 | ret = PTR_ERR(plane); |
13481 | goto fail; | |
13482 | } | |
d97d7b48 | 13483 | intel_crtc->plane_ids_mask |= BIT(plane->id); |
a81d6fa0 VS |
13484 | } |
13485 | ||
580503c7 | 13486 | cursor = intel_cursor_plane_create(dev_priv, pipe); |
d2b2cbce | 13487 | if (IS_ERR(cursor)) { |
b079bd17 | 13488 | ret = PTR_ERR(cursor); |
3d7d6510 | 13489 | goto fail; |
b079bd17 | 13490 | } |
d97d7b48 | 13491 | intel_crtc->plane_ids_mask |= BIT(cursor->id); |
3d7d6510 | 13492 | |
5ab0d85b | 13493 | ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base, |
b079bd17 VS |
13494 | &primary->base, &cursor->base, |
13495 | &intel_crtc_funcs, | |
4d5d72b7 | 13496 | "pipe %c", pipe_name(pipe)); |
3d7d6510 MR |
13497 | if (ret) |
13498 | goto fail; | |
79e53945 | 13499 | |
80824003 | 13500 | intel_crtc->pipe = pipe; |
e3c566df | 13501 | intel_crtc->plane = primary->plane; |
80824003 | 13502 | |
1c74eeaf NM |
13503 | /* initialize shared scalers */ |
13504 | intel_crtc_init_scalers(intel_crtc, crtc_state); | |
13505 | ||
22fd0fab JB |
13506 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
13507 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
e2af48c6 VS |
13508 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc; |
13509 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc; | |
22fd0fab | 13510 | |
79e53945 | 13511 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 | 13512 | |
8563b1e8 LL |
13513 | intel_color_init(&intel_crtc->base); |
13514 | ||
87b6b101 | 13515 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); |
b079bd17 VS |
13516 | |
13517 | return 0; | |
3d7d6510 MR |
13518 | |
13519 | fail: | |
b079bd17 VS |
13520 | /* |
13521 | * drm_mode_config_cleanup() will free up any | |
13522 | * crtcs/planes already initialized. | |
13523 | */ | |
f5de6e07 | 13524 | kfree(crtc_state); |
3d7d6510 | 13525 | kfree(intel_crtc); |
b079bd17 VS |
13526 | |
13527 | return ret; | |
79e53945 JB |
13528 | } |
13529 | ||
752aa88a JB |
13530 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
13531 | { | |
6e9f798d | 13532 | struct drm_device *dev = connector->base.dev; |
752aa88a | 13533 | |
51fd371b | 13534 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 13535 | |
51ec53da | 13536 | if (!connector->base.state->crtc) |
752aa88a JB |
13537 | return INVALID_PIPE; |
13538 | ||
51ec53da | 13539 | return to_intel_crtc(connector->base.state->crtc)->pipe; |
752aa88a JB |
13540 | } |
13541 | ||
08d7b3d1 | 13542 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 13543 | struct drm_file *file) |
08d7b3d1 | 13544 | { |
08d7b3d1 | 13545 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 13546 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 13547 | struct intel_crtc *crtc; |
08d7b3d1 | 13548 | |
7707e653 | 13549 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
71240ed2 | 13550 | if (!drmmode_crtc) |
3f2c2057 | 13551 | return -ENOENT; |
08d7b3d1 | 13552 | |
7707e653 | 13553 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 13554 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 13555 | |
c05422d5 | 13556 | return 0; |
08d7b3d1 CW |
13557 | } |
13558 | ||
66a9278e | 13559 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 13560 | { |
66a9278e DV |
13561 | struct drm_device *dev = encoder->base.dev; |
13562 | struct intel_encoder *source_encoder; | |
79e53945 | 13563 | int index_mask = 0; |
79e53945 JB |
13564 | int entry = 0; |
13565 | ||
b2784e15 | 13566 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 13567 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
13568 | index_mask |= (1 << entry); |
13569 | ||
79e53945 JB |
13570 | entry++; |
13571 | } | |
4ef69c7a | 13572 | |
79e53945 JB |
13573 | return index_mask; |
13574 | } | |
13575 | ||
646d5772 | 13576 | static bool has_edp_a(struct drm_i915_private *dev_priv) |
4d302442 | 13577 | { |
646d5772 | 13578 | if (!IS_MOBILE(dev_priv)) |
4d302442 CW |
13579 | return false; |
13580 | ||
13581 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
13582 | return false; | |
13583 | ||
5db94019 | 13584 | if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
13585 | return false; |
13586 | ||
13587 | return true; | |
13588 | } | |
13589 | ||
6315b5d3 | 13590 | static bool intel_crt_present(struct drm_i915_private *dev_priv) |
84b4e042 | 13591 | { |
6315b5d3 | 13592 | if (INTEL_GEN(dev_priv) >= 9) |
884497ed DL |
13593 | return false; |
13594 | ||
50a0bc90 | 13595 | if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) |
84b4e042 JB |
13596 | return false; |
13597 | ||
920a14b2 | 13598 | if (IS_CHERRYVIEW(dev_priv)) |
84b4e042 JB |
13599 | return false; |
13600 | ||
4f8036a2 TU |
13601 | if (HAS_PCH_LPT_H(dev_priv) && |
13602 | I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) | |
65e472e4 VS |
13603 | return false; |
13604 | ||
70ac54d0 | 13605 | /* DDI E can't be used if DDI A requires 4 lanes */ |
4f8036a2 | 13606 | if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) |
70ac54d0 VS |
13607 | return false; |
13608 | ||
e4abb733 | 13609 | if (!dev_priv->vbt.int_crt_support) |
84b4e042 JB |
13610 | return false; |
13611 | ||
13612 | return true; | |
13613 | } | |
13614 | ||
8090ba8c ID |
13615 | void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv) |
13616 | { | |
13617 | int pps_num; | |
13618 | int pps_idx; | |
13619 | ||
13620 | if (HAS_DDI(dev_priv)) | |
13621 | return; | |
13622 | /* | |
13623 | * This w/a is needed at least on CPT/PPT, but to be sure apply it | |
13624 | * everywhere where registers can be write protected. | |
13625 | */ | |
13626 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
13627 | pps_num = 2; | |
13628 | else | |
13629 | pps_num = 1; | |
13630 | ||
13631 | for (pps_idx = 0; pps_idx < pps_num; pps_idx++) { | |
13632 | u32 val = I915_READ(PP_CONTROL(pps_idx)); | |
13633 | ||
13634 | val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS; | |
13635 | I915_WRITE(PP_CONTROL(pps_idx), val); | |
13636 | } | |
13637 | } | |
13638 | ||
44cb734c ID |
13639 | static void intel_pps_init(struct drm_i915_private *dev_priv) |
13640 | { | |
cc3f90f0 | 13641 | if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv)) |
44cb734c ID |
13642 | dev_priv->pps_mmio_base = PCH_PPS_BASE; |
13643 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
13644 | dev_priv->pps_mmio_base = VLV_PPS_BASE; | |
13645 | else | |
13646 | dev_priv->pps_mmio_base = PPS_BASE; | |
8090ba8c ID |
13647 | |
13648 | intel_pps_unlock_regs_wa(dev_priv); | |
44cb734c ID |
13649 | } |
13650 | ||
c39055b0 | 13651 | static void intel_setup_outputs(struct drm_i915_private *dev_priv) |
79e53945 | 13652 | { |
4ef69c7a | 13653 | struct intel_encoder *encoder; |
cb0953d7 | 13654 | bool dpd_is_edp = false; |
79e53945 | 13655 | |
44cb734c ID |
13656 | intel_pps_init(dev_priv); |
13657 | ||
97a824e1 ID |
13658 | /* |
13659 | * intel_edp_init_connector() depends on this completing first, to | |
13660 | * prevent the registeration of both eDP and LVDS and the incorrect | |
13661 | * sharing of the PPS. | |
13662 | */ | |
c39055b0 | 13663 | intel_lvds_init(dev_priv); |
79e53945 | 13664 | |
6315b5d3 | 13665 | if (intel_crt_present(dev_priv)) |
c39055b0 | 13666 | intel_crt_init(dev_priv); |
cb0953d7 | 13667 | |
cc3f90f0 | 13668 | if (IS_GEN9_LP(dev_priv)) { |
c776eb2e VK |
13669 | /* |
13670 | * FIXME: Broxton doesn't support port detection via the | |
13671 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
13672 | * detect the ports. | |
13673 | */ | |
c39055b0 ACO |
13674 | intel_ddi_init(dev_priv, PORT_A); |
13675 | intel_ddi_init(dev_priv, PORT_B); | |
13676 | intel_ddi_init(dev_priv, PORT_C); | |
c6c794a2 | 13677 | |
c39055b0 | 13678 | intel_dsi_init(dev_priv); |
4f8036a2 | 13679 | } else if (HAS_DDI(dev_priv)) { |
0e72a5b5 ED |
13680 | int found; |
13681 | ||
de31facd JB |
13682 | /* |
13683 | * Haswell uses DDI functions to detect digital outputs. | |
13684 | * On SKL pre-D0 the strap isn't connected, so we assume | |
13685 | * it's there. | |
13686 | */ | |
77179400 | 13687 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 13688 | /* WaIgnoreDDIAStrap: skl */ |
b976dc53 | 13689 | if (found || IS_GEN9_BC(dev_priv)) |
c39055b0 | 13690 | intel_ddi_init(dev_priv, PORT_A); |
0e72a5b5 ED |
13691 | |
13692 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
13693 | * register */ | |
13694 | found = I915_READ(SFUSE_STRAP); | |
13695 | ||
13696 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
c39055b0 | 13697 | intel_ddi_init(dev_priv, PORT_B); |
0e72a5b5 | 13698 | if (found & SFUSE_STRAP_DDIC_DETECTED) |
c39055b0 | 13699 | intel_ddi_init(dev_priv, PORT_C); |
0e72a5b5 | 13700 | if (found & SFUSE_STRAP_DDID_DETECTED) |
c39055b0 | 13701 | intel_ddi_init(dev_priv, PORT_D); |
2800e4c2 RV |
13702 | /* |
13703 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
13704 | */ | |
b976dc53 | 13705 | if (IS_GEN9_BC(dev_priv) && |
2800e4c2 RV |
13706 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
13707 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
13708 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
c39055b0 | 13709 | intel_ddi_init(dev_priv, PORT_E); |
2800e4c2 | 13710 | |
6e266956 | 13711 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
cb0953d7 | 13712 | int found; |
7b91bf7f | 13713 | dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D); |
270b3042 | 13714 | |
646d5772 | 13715 | if (has_edp_a(dev_priv)) |
c39055b0 | 13716 | intel_dp_init(dev_priv, DP_A, PORT_A); |
cb0953d7 | 13717 | |
dc0fa718 | 13718 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 13719 | /* PCH SDVOB multiplex with HDMIB */ |
c39055b0 | 13720 | found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B); |
30ad48b7 | 13721 | if (!found) |
c39055b0 | 13722 | intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B); |
5eb08b69 | 13723 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
c39055b0 | 13724 | intel_dp_init(dev_priv, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
13725 | } |
13726 | ||
dc0fa718 | 13727 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
c39055b0 | 13728 | intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C); |
30ad48b7 | 13729 | |
dc0fa718 | 13730 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
c39055b0 | 13731 | intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D); |
30ad48b7 | 13732 | |
5eb08b69 | 13733 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
c39055b0 | 13734 | intel_dp_init(dev_priv, PCH_DP_C, PORT_C); |
5eb08b69 | 13735 | |
270b3042 | 13736 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
c39055b0 | 13737 | intel_dp_init(dev_priv, PCH_DP_D, PORT_D); |
920a14b2 | 13738 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
22f35042 | 13739 | bool has_edp, has_port; |
457c52d8 | 13740 | |
e17ac6db VS |
13741 | /* |
13742 | * The DP_DETECTED bit is the latched state of the DDC | |
13743 | * SDA pin at boot. However since eDP doesn't require DDC | |
13744 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
13745 | * eDP ports may have been muxed to an alternate function. | |
13746 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
13747 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
13748 | * detect eDP ports. | |
22f35042 VS |
13749 | * |
13750 | * Sadly the straps seem to be missing sometimes even for HDMI | |
13751 | * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap | |
13752 | * and VBT for the presence of the port. Additionally we can't | |
13753 | * trust the port type the VBT declares as we've seen at least | |
13754 | * HDMI ports that the VBT claim are DP or eDP. | |
e17ac6db | 13755 | */ |
7b91bf7f | 13756 | has_edp = intel_dp_is_port_edp(dev_priv, PORT_B); |
22f35042 VS |
13757 | has_port = intel_bios_is_port_present(dev_priv, PORT_B); |
13758 | if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port) | |
c39055b0 | 13759 | has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B); |
22f35042 | 13760 | if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) |
c39055b0 | 13761 | intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); |
585a94b8 | 13762 | |
7b91bf7f | 13763 | has_edp = intel_dp_is_port_edp(dev_priv, PORT_C); |
22f35042 VS |
13764 | has_port = intel_bios_is_port_present(dev_priv, PORT_C); |
13765 | if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port) | |
c39055b0 | 13766 | has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C); |
22f35042 | 13767 | if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) |
c39055b0 | 13768 | intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C); |
19c03924 | 13769 | |
920a14b2 | 13770 | if (IS_CHERRYVIEW(dev_priv)) { |
22f35042 VS |
13771 | /* |
13772 | * eDP not supported on port D, | |
13773 | * so no need to worry about it | |
13774 | */ | |
13775 | has_port = intel_bios_is_port_present(dev_priv, PORT_D); | |
13776 | if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port) | |
c39055b0 | 13777 | intel_dp_init(dev_priv, CHV_DP_D, PORT_D); |
22f35042 | 13778 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port) |
c39055b0 | 13779 | intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D); |
9418c1f1 VS |
13780 | } |
13781 | ||
c39055b0 | 13782 | intel_dsi_init(dev_priv); |
5db94019 | 13783 | } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) { |
27185ae1 | 13784 | bool found = false; |
7d57382e | 13785 | |
e2debe91 | 13786 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 13787 | DRM_DEBUG_KMS("probing SDVOB\n"); |
c39055b0 | 13788 | found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B); |
9beb5fea | 13789 | if (!found && IS_G4X(dev_priv)) { |
b01f2c3a | 13790 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
c39055b0 | 13791 | intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B); |
b01f2c3a | 13792 | } |
27185ae1 | 13793 | |
9beb5fea | 13794 | if (!found && IS_G4X(dev_priv)) |
c39055b0 | 13795 | intel_dp_init(dev_priv, DP_B, PORT_B); |
725e30ad | 13796 | } |
13520b05 KH |
13797 | |
13798 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 13799 | |
e2debe91 | 13800 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 13801 | DRM_DEBUG_KMS("probing SDVOC\n"); |
c39055b0 | 13802 | found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C); |
b01f2c3a | 13803 | } |
27185ae1 | 13804 | |
e2debe91 | 13805 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 13806 | |
9beb5fea | 13807 | if (IS_G4X(dev_priv)) { |
b01f2c3a | 13808 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
c39055b0 | 13809 | intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C); |
b01f2c3a | 13810 | } |
9beb5fea | 13811 | if (IS_G4X(dev_priv)) |
c39055b0 | 13812 | intel_dp_init(dev_priv, DP_C, PORT_C); |
725e30ad | 13813 | } |
27185ae1 | 13814 | |
9beb5fea | 13815 | if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED)) |
c39055b0 | 13816 | intel_dp_init(dev_priv, DP_D, PORT_D); |
5db94019 | 13817 | } else if (IS_GEN2(dev_priv)) |
c39055b0 | 13818 | intel_dvo_init(dev_priv); |
79e53945 | 13819 | |
56b857a5 | 13820 | if (SUPPORTS_TV(dev_priv)) |
c39055b0 | 13821 | intel_tv_init(dev_priv); |
79e53945 | 13822 | |
c39055b0 | 13823 | intel_psr_init(dev_priv); |
7c8f8a70 | 13824 | |
c39055b0 | 13825 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
4ef69c7a CW |
13826 | encoder->base.possible_crtcs = encoder->crtc_mask; |
13827 | encoder->base.possible_clones = | |
66a9278e | 13828 | intel_encoder_clones(encoder); |
79e53945 | 13829 | } |
47356eb6 | 13830 | |
c39055b0 | 13831 | intel_init_pch_refclk(dev_priv); |
270b3042 | 13832 | |
c39055b0 | 13833 | drm_helper_move_panel_connectors_to_head(&dev_priv->drm); |
79e53945 JB |
13834 | } |
13835 | ||
13836 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
13837 | { | |
13838 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 | 13839 | |
ef2d633e | 13840 | drm_framebuffer_cleanup(fb); |
70001cd2 | 13841 | |
dd689287 CW |
13842 | i915_gem_object_lock(intel_fb->obj); |
13843 | WARN_ON(!intel_fb->obj->framebuffer_references--); | |
13844 | i915_gem_object_unlock(intel_fb->obj); | |
13845 | ||
f8c417cd | 13846 | i915_gem_object_put(intel_fb->obj); |
70001cd2 | 13847 | |
79e53945 JB |
13848 | kfree(intel_fb); |
13849 | } | |
13850 | ||
13851 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 13852 | struct drm_file *file, |
79e53945 JB |
13853 | unsigned int *handle) |
13854 | { | |
13855 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 13856 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 13857 | |
cc917ab4 CW |
13858 | if (obj->userptr.mm) { |
13859 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); | |
13860 | return -EINVAL; | |
13861 | } | |
13862 | ||
05394f39 | 13863 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
13864 | } |
13865 | ||
86c98588 RV |
13866 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
13867 | struct drm_file *file, | |
13868 | unsigned flags, unsigned color, | |
13869 | struct drm_clip_rect *clips, | |
13870 | unsigned num_clips) | |
13871 | { | |
5a97bcc6 | 13872 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
86c98588 | 13873 | |
5a97bcc6 | 13874 | i915_gem_object_flush_if_display(obj); |
d59b21ec | 13875 | intel_fb_obj_flush(obj, ORIGIN_DIRTYFB); |
86c98588 RV |
13876 | |
13877 | return 0; | |
13878 | } | |
13879 | ||
79e53945 JB |
13880 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
13881 | .destroy = intel_user_framebuffer_destroy, | |
13882 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 13883 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
13884 | }; |
13885 | ||
b321803d | 13886 | static |
920a14b2 TU |
13887 | u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv, |
13888 | uint64_t fb_modifier, uint32_t pixel_format) | |
b321803d | 13889 | { |
24dbf51a | 13890 | u32 gen = INTEL_GEN(dev_priv); |
b321803d DL |
13891 | |
13892 | if (gen >= 9) { | |
ac484963 VS |
13893 | int cpp = drm_format_plane_cpp(pixel_format, 0); |
13894 | ||
b321803d DL |
13895 | /* "The stride in bytes must not exceed the of the size of 8K |
13896 | * pixels and 32K bytes." | |
13897 | */ | |
ac484963 | 13898 | return min(8192 * cpp, 32768); |
6401c37d | 13899 | } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) { |
b321803d DL |
13900 | return 32*1024; |
13901 | } else if (gen >= 4) { | |
13902 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
13903 | return 16*1024; | |
13904 | else | |
13905 | return 32*1024; | |
13906 | } else if (gen >= 3) { | |
13907 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
13908 | return 8*1024; | |
13909 | else | |
13910 | return 16*1024; | |
13911 | } else { | |
13912 | /* XXX DSPC is limited to 4k tiled */ | |
13913 | return 8*1024; | |
13914 | } | |
13915 | } | |
13916 | ||
24dbf51a CW |
13917 | static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, |
13918 | struct drm_i915_gem_object *obj, | |
13919 | struct drm_mode_fb_cmd2 *mode_cmd) | |
79e53945 | 13920 | { |
24dbf51a | 13921 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
2e2adb05 | 13922 | struct drm_framebuffer *fb = &intel_fb->base; |
b3c11ac2 | 13923 | struct drm_format_name_buf format_name; |
2e2adb05 | 13924 | u32 pitch_limit; |
dd689287 | 13925 | unsigned int tiling, stride; |
24dbf51a | 13926 | int ret = -EINVAL; |
2e2adb05 | 13927 | int i; |
79e53945 | 13928 | |
dd689287 CW |
13929 | i915_gem_object_lock(obj); |
13930 | obj->framebuffer_references++; | |
13931 | tiling = i915_gem_object_get_tiling(obj); | |
13932 | stride = i915_gem_object_get_stride(obj); | |
13933 | i915_gem_object_unlock(obj); | |
dd4916c5 | 13934 | |
2a80eada | 13935 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
c2ff7370 VS |
13936 | /* |
13937 | * If there's a fence, enforce that | |
13938 | * the fb modifier and tiling mode match. | |
13939 | */ | |
13940 | if (tiling != I915_TILING_NONE && | |
13941 | tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { | |
144cc143 | 13942 | DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n"); |
24dbf51a | 13943 | goto err; |
2a80eada DV |
13944 | } |
13945 | } else { | |
c2ff7370 | 13946 | if (tiling == I915_TILING_X) { |
2a80eada | 13947 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; |
c2ff7370 | 13948 | } else if (tiling == I915_TILING_Y) { |
144cc143 | 13949 | DRM_DEBUG_KMS("No Y tiling for legacy addfb\n"); |
24dbf51a | 13950 | goto err; |
2a80eada DV |
13951 | } |
13952 | } | |
13953 | ||
9a8f0a12 TU |
13954 | /* Passed in modifier sanity checking. */ |
13955 | switch (mode_cmd->modifier[0]) { | |
2e2adb05 VS |
13956 | case I915_FORMAT_MOD_Y_TILED_CCS: |
13957 | case I915_FORMAT_MOD_Yf_TILED_CCS: | |
13958 | switch (mode_cmd->pixel_format) { | |
13959 | case DRM_FORMAT_XBGR8888: | |
13960 | case DRM_FORMAT_ABGR8888: | |
13961 | case DRM_FORMAT_XRGB8888: | |
13962 | case DRM_FORMAT_ARGB8888: | |
13963 | break; | |
13964 | default: | |
13965 | DRM_DEBUG_KMS("RC supported only with RGB8888 formats\n"); | |
13966 | goto err; | |
13967 | } | |
13968 | /* fall through */ | |
9a8f0a12 TU |
13969 | case I915_FORMAT_MOD_Y_TILED: |
13970 | case I915_FORMAT_MOD_Yf_TILED: | |
6315b5d3 | 13971 | if (INTEL_GEN(dev_priv) < 9) { |
144cc143 VS |
13972 | DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n", |
13973 | mode_cmd->modifier[0]); | |
24dbf51a | 13974 | goto err; |
9a8f0a12 | 13975 | } |
2f075565 | 13976 | case DRM_FORMAT_MOD_LINEAR: |
9a8f0a12 TU |
13977 | case I915_FORMAT_MOD_X_TILED: |
13978 | break; | |
13979 | default: | |
144cc143 VS |
13980 | DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n", |
13981 | mode_cmd->modifier[0]); | |
24dbf51a | 13982 | goto err; |
c16ed4be | 13983 | } |
57cd6508 | 13984 | |
c2ff7370 VS |
13985 | /* |
13986 | * gen2/3 display engine uses the fence if present, | |
13987 | * so the tiling mode must match the fb modifier exactly. | |
13988 | */ | |
13989 | if (INTEL_INFO(dev_priv)->gen < 4 && | |
13990 | tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { | |
144cc143 | 13991 | DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n"); |
9aceb5c1 | 13992 | goto err; |
c2ff7370 VS |
13993 | } |
13994 | ||
920a14b2 | 13995 | pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0], |
b321803d | 13996 | mode_cmd->pixel_format); |
a35cdaa0 | 13997 | if (mode_cmd->pitches[0] > pitch_limit) { |
144cc143 | 13998 | DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n", |
2f075565 | 13999 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ? |
144cc143 VS |
14000 | "tiled" : "linear", |
14001 | mode_cmd->pitches[0], pitch_limit); | |
24dbf51a | 14002 | goto err; |
c16ed4be | 14003 | } |
5d7bd705 | 14004 | |
c2ff7370 VS |
14005 | /* |
14006 | * If there's a fence, enforce that | |
14007 | * the fb pitch and fence stride match. | |
14008 | */ | |
144cc143 VS |
14009 | if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) { |
14010 | DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n", | |
14011 | mode_cmd->pitches[0], stride); | |
24dbf51a | 14012 | goto err; |
c16ed4be | 14013 | } |
5d7bd705 | 14014 | |
57779d06 | 14015 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 14016 | switch (mode_cmd->pixel_format) { |
57779d06 | 14017 | case DRM_FORMAT_C8: |
04b3924d VS |
14018 | case DRM_FORMAT_RGB565: |
14019 | case DRM_FORMAT_XRGB8888: | |
14020 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
14021 | break; |
14022 | case DRM_FORMAT_XRGB1555: | |
6315b5d3 | 14023 | if (INTEL_GEN(dev_priv) > 3) { |
144cc143 VS |
14024 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
14025 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 14026 | goto err; |
c16ed4be | 14027 | } |
57779d06 | 14028 | break; |
57779d06 | 14029 | case DRM_FORMAT_ABGR8888: |
920a14b2 | 14030 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
6315b5d3 | 14031 | INTEL_GEN(dev_priv) < 9) { |
144cc143 VS |
14032 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
14033 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 14034 | goto err; |
6c0fd451 DL |
14035 | } |
14036 | break; | |
14037 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 14038 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 14039 | case DRM_FORMAT_XBGR2101010: |
6315b5d3 | 14040 | if (INTEL_GEN(dev_priv) < 4) { |
144cc143 VS |
14041 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
14042 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 14043 | goto err; |
c16ed4be | 14044 | } |
b5626747 | 14045 | break; |
7531208b | 14046 | case DRM_FORMAT_ABGR2101010: |
920a14b2 | 14047 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { |
144cc143 VS |
14048 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
14049 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 14050 | goto err; |
7531208b DL |
14051 | } |
14052 | break; | |
04b3924d VS |
14053 | case DRM_FORMAT_YUYV: |
14054 | case DRM_FORMAT_UYVY: | |
14055 | case DRM_FORMAT_YVYU: | |
14056 | case DRM_FORMAT_VYUY: | |
ab33081a | 14057 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) { |
144cc143 VS |
14058 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
14059 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 14060 | goto err; |
c16ed4be | 14061 | } |
57cd6508 CW |
14062 | break; |
14063 | default: | |
144cc143 VS |
14064 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
14065 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 14066 | goto err; |
57cd6508 CW |
14067 | } |
14068 | ||
90f9a336 VS |
14069 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
14070 | if (mode_cmd->offsets[0] != 0) | |
24dbf51a | 14071 | goto err; |
90f9a336 | 14072 | |
2e2adb05 | 14073 | drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd); |
d88c4afd | 14074 | |
2e2adb05 VS |
14075 | for (i = 0; i < fb->format->num_planes; i++) { |
14076 | u32 stride_alignment; | |
14077 | ||
14078 | if (mode_cmd->handles[i] != mode_cmd->handles[0]) { | |
14079 | DRM_DEBUG_KMS("bad plane %d handle\n", i); | |
14080 | return -EINVAL; | |
14081 | } | |
14082 | ||
14083 | stride_alignment = intel_fb_stride_alignment(fb, i); | |
14084 | ||
14085 | /* | |
14086 | * Display WA #0531: skl,bxt,kbl,glk | |
14087 | * | |
14088 | * Render decompression and plane width > 3840 | |
14089 | * combined with horizontal panning requires the | |
14090 | * plane stride to be a multiple of 4. We'll just | |
14091 | * require the entire fb to accommodate that to avoid | |
14092 | * potential runtime errors at plane configuration time. | |
14093 | */ | |
14094 | if (IS_GEN9(dev_priv) && i == 0 && fb->width > 3840 && | |
14095 | (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || | |
14096 | fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) | |
14097 | stride_alignment *= 4; | |
14098 | ||
14099 | if (fb->pitches[i] & (stride_alignment - 1)) { | |
14100 | DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n", | |
14101 | i, fb->pitches[i], stride_alignment); | |
14102 | goto err; | |
14103 | } | |
d88c4afd VS |
14104 | } |
14105 | ||
c7d73f6a DV |
14106 | intel_fb->obj = obj; |
14107 | ||
2e2adb05 | 14108 | ret = intel_fill_fb_info(dev_priv, fb); |
6687c906 | 14109 | if (ret) |
9aceb5c1 | 14110 | goto err; |
2d7a215f | 14111 | |
2e2adb05 | 14112 | ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs); |
79e53945 JB |
14113 | if (ret) { |
14114 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
24dbf51a | 14115 | goto err; |
79e53945 JB |
14116 | } |
14117 | ||
79e53945 | 14118 | return 0; |
24dbf51a CW |
14119 | |
14120 | err: | |
dd689287 CW |
14121 | i915_gem_object_lock(obj); |
14122 | obj->framebuffer_references--; | |
14123 | i915_gem_object_unlock(obj); | |
24dbf51a | 14124 | return ret; |
79e53945 JB |
14125 | } |
14126 | ||
79e53945 JB |
14127 | static struct drm_framebuffer * |
14128 | intel_user_framebuffer_create(struct drm_device *dev, | |
14129 | struct drm_file *filp, | |
1eb83451 | 14130 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
79e53945 | 14131 | { |
dcb1394e | 14132 | struct drm_framebuffer *fb; |
05394f39 | 14133 | struct drm_i915_gem_object *obj; |
76dc3769 | 14134 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
79e53945 | 14135 | |
03ac0642 CW |
14136 | obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]); |
14137 | if (!obj) | |
cce13ff7 | 14138 | return ERR_PTR(-ENOENT); |
79e53945 | 14139 | |
24dbf51a | 14140 | fb = intel_framebuffer_create(obj, &mode_cmd); |
dcb1394e | 14141 | if (IS_ERR(fb)) |
f0cd5182 | 14142 | i915_gem_object_put(obj); |
dcb1394e LW |
14143 | |
14144 | return fb; | |
79e53945 JB |
14145 | } |
14146 | ||
778e23a9 CW |
14147 | static void intel_atomic_state_free(struct drm_atomic_state *state) |
14148 | { | |
14149 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
14150 | ||
14151 | drm_atomic_state_default_release(state); | |
14152 | ||
14153 | i915_sw_fence_fini(&intel_state->commit_ready); | |
14154 | ||
14155 | kfree(state); | |
14156 | } | |
14157 | ||
79e53945 | 14158 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 14159 | .fb_create = intel_user_framebuffer_create, |
bbfb6ce8 | 14160 | .get_format_info = intel_get_format_info, |
0632fef6 | 14161 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
14162 | .atomic_check = intel_atomic_check, |
14163 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
14164 | .atomic_state_alloc = intel_atomic_state_alloc, |
14165 | .atomic_state_clear = intel_atomic_state_clear, | |
778e23a9 | 14166 | .atomic_state_free = intel_atomic_state_free, |
79e53945 JB |
14167 | }; |
14168 | ||
88212941 ID |
14169 | /** |
14170 | * intel_init_display_hooks - initialize the display modesetting hooks | |
14171 | * @dev_priv: device private | |
14172 | */ | |
14173 | void intel_init_display_hooks(struct drm_i915_private *dev_priv) | |
e70236a8 | 14174 | { |
7ff89ca2 VS |
14175 | intel_init_cdclk_hooks(dev_priv); |
14176 | ||
88212941 | 14177 | if (INTEL_INFO(dev_priv)->gen >= 9) { |
bc8d7dff | 14178 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14179 | dev_priv->display.get_initial_plane_config = |
14180 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
14181 | dev_priv->display.crtc_compute_clock = |
14182 | haswell_crtc_compute_clock; | |
14183 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
14184 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 14185 | } else if (HAS_DDI(dev_priv)) { |
0e8ffe1b | 14186 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14187 | dev_priv->display.get_initial_plane_config = |
14188 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
14189 | dev_priv->display.crtc_compute_clock = |
14190 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
14191 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
14192 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 14193 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
0e8ffe1b | 14194 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
14195 | dev_priv->display.get_initial_plane_config = |
14196 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
14197 | dev_priv->display.crtc_compute_clock = |
14198 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
14199 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
14200 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
65b3d6a9 | 14201 | } else if (IS_CHERRYVIEW(dev_priv)) { |
89b667f8 | 14202 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14203 | dev_priv->display.get_initial_plane_config = |
14204 | i9xx_get_initial_plane_config; | |
65b3d6a9 ACO |
14205 | dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock; |
14206 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
14207 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
14208 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
14209 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14210 | dev_priv->display.get_initial_plane_config = | |
14211 | i9xx_get_initial_plane_config; | |
14212 | dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock; | |
89b667f8 JB |
14213 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
14214 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
19ec6693 ACO |
14215 | } else if (IS_G4X(dev_priv)) { |
14216 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14217 | dev_priv->display.get_initial_plane_config = | |
14218 | i9xx_get_initial_plane_config; | |
14219 | dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock; | |
14220 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
14221 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
70e8aa21 ACO |
14222 | } else if (IS_PINEVIEW(dev_priv)) { |
14223 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14224 | dev_priv->display.get_initial_plane_config = | |
14225 | i9xx_get_initial_plane_config; | |
14226 | dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock; | |
14227 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
14228 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 | 14229 | } else if (!IS_GEN2(dev_priv)) { |
0e8ffe1b | 14230 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14231 | dev_priv->display.get_initial_plane_config = |
14232 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14233 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
14234 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
14235 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 ACO |
14236 | } else { |
14237 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14238 | dev_priv->display.get_initial_plane_config = | |
14239 | i9xx_get_initial_plane_config; | |
14240 | dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock; | |
14241 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
14242 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 14243 | } |
e70236a8 | 14244 | |
88212941 | 14245 | if (IS_GEN5(dev_priv)) { |
3bb11b53 | 14246 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
88212941 | 14247 | } else if (IS_GEN6(dev_priv)) { |
3bb11b53 | 14248 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
88212941 | 14249 | } else if (IS_IVYBRIDGE(dev_priv)) { |
3bb11b53 SJ |
14250 | /* FIXME: detect B0+ stepping and use auto training */ |
14251 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
88212941 | 14252 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
3bb11b53 | 14253 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
445e780b VS |
14254 | } |
14255 | ||
27082493 L |
14256 | if (dev_priv->info.gen >= 9) |
14257 | dev_priv->display.update_crtcs = skl_update_crtcs; | |
14258 | else | |
14259 | dev_priv->display.update_crtcs = intel_update_crtcs; | |
e70236a8 JB |
14260 | } |
14261 | ||
435793df KP |
14262 | /* |
14263 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
14264 | */ | |
14265 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
14266 | { | |
fac5e23e | 14267 | struct drm_i915_private *dev_priv = to_i915(dev); |
435793df | 14268 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; |
bc0daf48 | 14269 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
14270 | } |
14271 | ||
4dca20ef | 14272 | /* |
5a15ab5b CE |
14273 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
14274 | * brightness value | |
4dca20ef CE |
14275 | */ |
14276 | static void quirk_invert_brightness(struct drm_device *dev) | |
14277 | { | |
fac5e23e | 14278 | struct drm_i915_private *dev_priv = to_i915(dev); |
4dca20ef | 14279 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; |
bc0daf48 | 14280 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
14281 | } |
14282 | ||
9c72cc6f SD |
14283 | /* Some VBT's incorrectly indicate no backlight is present */ |
14284 | static void quirk_backlight_present(struct drm_device *dev) | |
14285 | { | |
fac5e23e | 14286 | struct drm_i915_private *dev_priv = to_i915(dev); |
9c72cc6f SD |
14287 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; |
14288 | DRM_INFO("applying backlight present quirk\n"); | |
14289 | } | |
14290 | ||
c99a259b MN |
14291 | /* Toshiba Satellite P50-C-18C requires T12 delay to be min 800ms |
14292 | * which is 300 ms greater than eDP spec T12 min. | |
14293 | */ | |
14294 | static void quirk_increase_t12_delay(struct drm_device *dev) | |
14295 | { | |
14296 | struct drm_i915_private *dev_priv = to_i915(dev); | |
14297 | ||
14298 | dev_priv->quirks |= QUIRK_INCREASE_T12_DELAY; | |
14299 | DRM_INFO("Applying T12 delay quirk\n"); | |
14300 | } | |
14301 | ||
b690e96c JB |
14302 | struct intel_quirk { |
14303 | int device; | |
14304 | int subsystem_vendor; | |
14305 | int subsystem_device; | |
14306 | void (*hook)(struct drm_device *dev); | |
14307 | }; | |
14308 | ||
5f85f176 EE |
14309 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
14310 | struct intel_dmi_quirk { | |
14311 | void (*hook)(struct drm_device *dev); | |
14312 | const struct dmi_system_id (*dmi_id_list)[]; | |
14313 | }; | |
14314 | ||
14315 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
14316 | { | |
14317 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
14318 | return 1; | |
14319 | } | |
14320 | ||
14321 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
14322 | { | |
14323 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
14324 | { | |
14325 | .callback = intel_dmi_reverse_brightness, | |
14326 | .ident = "NCR Corporation", | |
14327 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
14328 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
14329 | }, | |
14330 | }, | |
14331 | { } /* terminating entry */ | |
14332 | }, | |
14333 | .hook = quirk_invert_brightness, | |
14334 | }, | |
14335 | }; | |
14336 | ||
c43b5634 | 14337 | static struct intel_quirk intel_quirks[] = { |
435793df KP |
14338 | /* Lenovo U160 cannot use SSC on LVDS */ |
14339 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
14340 | |
14341 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
14342 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 14343 | |
be505f64 AH |
14344 | /* Acer Aspire 5734Z must invert backlight brightness */ |
14345 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
14346 | ||
14347 | /* Acer/eMachines G725 */ | |
14348 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
14349 | ||
14350 | /* Acer/eMachines e725 */ | |
14351 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
14352 | ||
14353 | /* Acer/Packard Bell NCL20 */ | |
14354 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
14355 | ||
14356 | /* Acer Aspire 4736Z */ | |
14357 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
14358 | |
14359 | /* Acer Aspire 5336 */ | |
14360 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
14361 | |
14362 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
14363 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 14364 | |
dfb3d47b SD |
14365 | /* Acer C720 Chromebook (Core i3 4005U) */ |
14366 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
14367 | ||
b2a9601c | 14368 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
14369 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
14370 | ||
1b9448b0 JN |
14371 | /* Apple Macbook 4,1 */ |
14372 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, | |
14373 | ||
d4967d8c SD |
14374 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
14375 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
14376 | |
14377 | /* HP Chromebook 14 (Celeron 2955U) */ | |
14378 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
14379 | |
14380 | /* Dell Chromebook 11 */ | |
14381 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
9be64eee JN |
14382 | |
14383 | /* Dell Chromebook 11 (2015 version) */ | |
14384 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, | |
c99a259b MN |
14385 | |
14386 | /* Toshiba Satellite P50-C-18C */ | |
14387 | { 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay }, | |
b690e96c JB |
14388 | }; |
14389 | ||
14390 | static void intel_init_quirks(struct drm_device *dev) | |
14391 | { | |
14392 | struct pci_dev *d = dev->pdev; | |
14393 | int i; | |
14394 | ||
14395 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
14396 | struct intel_quirk *q = &intel_quirks[i]; | |
14397 | ||
14398 | if (d->device == q->device && | |
14399 | (d->subsystem_vendor == q->subsystem_vendor || | |
14400 | q->subsystem_vendor == PCI_ANY_ID) && | |
14401 | (d->subsystem_device == q->subsystem_device || | |
14402 | q->subsystem_device == PCI_ANY_ID)) | |
14403 | q->hook(dev); | |
14404 | } | |
5f85f176 EE |
14405 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
14406 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
14407 | intel_dmi_quirks[i].hook(dev); | |
14408 | } | |
b690e96c JB |
14409 | } |
14410 | ||
9cce37f4 | 14411 | /* Disable the VGA plane that we never use */ |
29b74b7f | 14412 | static void i915_disable_vga(struct drm_i915_private *dev_priv) |
9cce37f4 | 14413 | { |
52a05c30 | 14414 | struct pci_dev *pdev = dev_priv->drm.pdev; |
9cce37f4 | 14415 | u8 sr1; |
920a14b2 | 14416 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv); |
9cce37f4 | 14417 | |
2b37c616 | 14418 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
52a05c30 | 14419 | vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 14420 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
14421 | sr1 = inb(VGA_SR_DATA); |
14422 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
52a05c30 | 14423 | vga_put(pdev, VGA_RSRC_LEGACY_IO); |
9cce37f4 JB |
14424 | udelay(300); |
14425 | ||
01f5a626 | 14426 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
14427 | POSTING_READ(vga_reg); |
14428 | } | |
14429 | ||
f817586c DV |
14430 | void intel_modeset_init_hw(struct drm_device *dev) |
14431 | { | |
fac5e23e | 14432 | struct drm_i915_private *dev_priv = to_i915(dev); |
1a617b77 | 14433 | |
4c75b940 | 14434 | intel_update_cdclk(dev_priv); |
bb0f4aab | 14435 | dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw; |
1a617b77 | 14436 | |
46f16e63 | 14437 | intel_init_clock_gating(dev_priv); |
f817586c DV |
14438 | } |
14439 | ||
d93c0372 MR |
14440 | /* |
14441 | * Calculate what we think the watermarks should be for the state we've read | |
14442 | * out of the hardware and then immediately program those watermarks so that | |
14443 | * we ensure the hardware settings match our internal state. | |
14444 | * | |
14445 | * We can calculate what we think WM's should be by creating a duplicate of the | |
14446 | * current state (which was constructed during hardware readout) and running it | |
14447 | * through the atomic check code to calculate new watermark values in the | |
14448 | * state object. | |
14449 | */ | |
14450 | static void sanitize_watermarks(struct drm_device *dev) | |
14451 | { | |
14452 | struct drm_i915_private *dev_priv = to_i915(dev); | |
14453 | struct drm_atomic_state *state; | |
ccf010fb | 14454 | struct intel_atomic_state *intel_state; |
d93c0372 MR |
14455 | struct drm_crtc *crtc; |
14456 | struct drm_crtc_state *cstate; | |
14457 | struct drm_modeset_acquire_ctx ctx; | |
14458 | int ret; | |
14459 | int i; | |
14460 | ||
14461 | /* Only supported on platforms that use atomic watermark design */ | |
ed4a6a7c | 14462 | if (!dev_priv->display.optimize_watermarks) |
d93c0372 MR |
14463 | return; |
14464 | ||
14465 | /* | |
14466 | * We need to hold connection_mutex before calling duplicate_state so | |
14467 | * that the connector loop is protected. | |
14468 | */ | |
14469 | drm_modeset_acquire_init(&ctx, 0); | |
14470 | retry: | |
0cd1262d | 14471 | ret = drm_modeset_lock_all_ctx(dev, &ctx); |
d93c0372 MR |
14472 | if (ret == -EDEADLK) { |
14473 | drm_modeset_backoff(&ctx); | |
14474 | goto retry; | |
14475 | } else if (WARN_ON(ret)) { | |
0cd1262d | 14476 | goto fail; |
d93c0372 MR |
14477 | } |
14478 | ||
14479 | state = drm_atomic_helper_duplicate_state(dev, &ctx); | |
14480 | if (WARN_ON(IS_ERR(state))) | |
0cd1262d | 14481 | goto fail; |
d93c0372 | 14482 | |
ccf010fb ML |
14483 | intel_state = to_intel_atomic_state(state); |
14484 | ||
ed4a6a7c MR |
14485 | /* |
14486 | * Hardware readout is the only time we don't want to calculate | |
14487 | * intermediate watermarks (since we don't trust the current | |
14488 | * watermarks). | |
14489 | */ | |
602ae835 VS |
14490 | if (!HAS_GMCH_DISPLAY(dev_priv)) |
14491 | intel_state->skip_intermediate_wm = true; | |
ed4a6a7c | 14492 | |
d93c0372 MR |
14493 | ret = intel_atomic_check(dev, state); |
14494 | if (ret) { | |
14495 | /* | |
14496 | * If we fail here, it means that the hardware appears to be | |
14497 | * programmed in a way that shouldn't be possible, given our | |
14498 | * understanding of watermark requirements. This might mean a | |
14499 | * mistake in the hardware readout code or a mistake in the | |
14500 | * watermark calculations for a given platform. Raise a WARN | |
14501 | * so that this is noticeable. | |
14502 | * | |
14503 | * If this actually happens, we'll have to just leave the | |
14504 | * BIOS-programmed watermarks untouched and hope for the best. | |
14505 | */ | |
14506 | WARN(true, "Could not determine valid watermarks for inherited state\n"); | |
b9a1b717 | 14507 | goto put_state; |
d93c0372 MR |
14508 | } |
14509 | ||
14510 | /* Write calculated watermark values back */ | |
aa5e9b47 | 14511 | for_each_new_crtc_in_state(state, crtc, cstate, i) { |
d93c0372 MR |
14512 | struct intel_crtc_state *cs = to_intel_crtc_state(cstate); |
14513 | ||
ed4a6a7c | 14514 | cs->wm.need_postvbl_update = true; |
ccf010fb | 14515 | dev_priv->display.optimize_watermarks(intel_state, cs); |
d93c0372 MR |
14516 | } |
14517 | ||
b9a1b717 | 14518 | put_state: |
0853695c | 14519 | drm_atomic_state_put(state); |
0cd1262d | 14520 | fail: |
d93c0372 MR |
14521 | drm_modeset_drop_locks(&ctx); |
14522 | drm_modeset_acquire_fini(&ctx); | |
14523 | } | |
14524 | ||
b079bd17 | 14525 | int intel_modeset_init(struct drm_device *dev) |
79e53945 | 14526 | { |
72e96d64 JL |
14527 | struct drm_i915_private *dev_priv = to_i915(dev); |
14528 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
8cc87b75 | 14529 | enum pipe pipe; |
46f297fb | 14530 | struct intel_crtc *crtc; |
79e53945 JB |
14531 | |
14532 | drm_mode_config_init(dev); | |
14533 | ||
14534 | dev->mode_config.min_width = 0; | |
14535 | dev->mode_config.min_height = 0; | |
14536 | ||
019d96cb DA |
14537 | dev->mode_config.preferred_depth = 24; |
14538 | dev->mode_config.prefer_shadow = 1; | |
14539 | ||
25bab385 TU |
14540 | dev->mode_config.allow_fb_modifiers = true; |
14541 | ||
e6ecefaa | 14542 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 14543 | |
400c19d9 | 14544 | init_llist_head(&dev_priv->atomic_helper.free_list); |
eb955eee | 14545 | INIT_WORK(&dev_priv->atomic_helper.free_work, |
ba318c61 | 14546 | intel_atomic_helper_free_state_worker); |
eb955eee | 14547 | |
b690e96c JB |
14548 | intel_init_quirks(dev); |
14549 | ||
62d75df7 | 14550 | intel_init_pm(dev_priv); |
1fa61106 | 14551 | |
b7f05d4a | 14552 | if (INTEL_INFO(dev_priv)->num_pipes == 0) |
b079bd17 | 14553 | return 0; |
e3c74757 | 14554 | |
69f92f67 LW |
14555 | /* |
14556 | * There may be no VBT; and if the BIOS enabled SSC we can | |
14557 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
14558 | * BIOS isn't using it, don't assume it will work even if the VBT | |
14559 | * indicates as much. | |
14560 | */ | |
6e266956 | 14561 | if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { |
69f92f67 LW |
14562 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & |
14563 | DREF_SSC1_ENABLE); | |
14564 | ||
14565 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
14566 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
14567 | bios_lvds_use_ssc ? "en" : "dis", | |
14568 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
14569 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
14570 | } | |
14571 | } | |
14572 | ||
5db94019 | 14573 | if (IS_GEN2(dev_priv)) { |
a6c45cf0 CW |
14574 | dev->mode_config.max_width = 2048; |
14575 | dev->mode_config.max_height = 2048; | |
5db94019 | 14576 | } else if (IS_GEN3(dev_priv)) { |
5e4d6fa7 KP |
14577 | dev->mode_config.max_width = 4096; |
14578 | dev->mode_config.max_height = 4096; | |
79e53945 | 14579 | } else { |
a6c45cf0 CW |
14580 | dev->mode_config.max_width = 8192; |
14581 | dev->mode_config.max_height = 8192; | |
79e53945 | 14582 | } |
068be561 | 14583 | |
2a307c2e JN |
14584 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { |
14585 | dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512; | |
dc41c154 | 14586 | dev->mode_config.cursor_height = 1023; |
5db94019 | 14587 | } else if (IS_GEN2(dev_priv)) { |
068be561 DL |
14588 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
14589 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
14590 | } else { | |
14591 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
14592 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
14593 | } | |
14594 | ||
72e96d64 | 14595 | dev->mode_config.fb_base = ggtt->mappable_base; |
79e53945 | 14596 | |
28c97730 | 14597 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
b7f05d4a TU |
14598 | INTEL_INFO(dev_priv)->num_pipes, |
14599 | INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 14600 | |
055e393f | 14601 | for_each_pipe(dev_priv, pipe) { |
b079bd17 VS |
14602 | int ret; |
14603 | ||
5ab0d85b | 14604 | ret = intel_crtc_init(dev_priv, pipe); |
b079bd17 VS |
14605 | if (ret) { |
14606 | drm_mode_config_cleanup(dev); | |
14607 | return ret; | |
14608 | } | |
79e53945 JB |
14609 | } |
14610 | ||
e72f9fbf | 14611 | intel_shared_dpll_init(dev); |
ee7b9f93 | 14612 | |
5be6e334 VS |
14613 | intel_update_czclk(dev_priv); |
14614 | intel_modeset_init_hw(dev); | |
14615 | ||
b2045352 | 14616 | if (dev_priv->max_cdclk_freq == 0) |
4c75b940 | 14617 | intel_update_max_cdclk(dev_priv); |
b2045352 | 14618 | |
9cce37f4 | 14619 | /* Just disable it once at startup */ |
29b74b7f | 14620 | i915_disable_vga(dev_priv); |
c39055b0 | 14621 | intel_setup_outputs(dev_priv); |
11be49eb | 14622 | |
6e9f798d | 14623 | drm_modeset_lock_all(dev); |
aecd36b8 | 14624 | intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx); |
6e9f798d | 14625 | drm_modeset_unlock_all(dev); |
46f297fb | 14626 | |
d3fcc808 | 14627 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
14628 | struct intel_initial_plane_config plane_config = {}; |
14629 | ||
46f297fb JB |
14630 | if (!crtc->active) |
14631 | continue; | |
14632 | ||
46f297fb | 14633 | /* |
46f297fb JB |
14634 | * Note that reserving the BIOS fb up front prevents us |
14635 | * from stuffing other stolen allocations like the ring | |
14636 | * on top. This prevents some ugliness at boot time, and | |
14637 | * can even allow for smooth boot transitions if the BIOS | |
14638 | * fb is large enough for the active pipe configuration. | |
14639 | */ | |
eeebeac5 ML |
14640 | dev_priv->display.get_initial_plane_config(crtc, |
14641 | &plane_config); | |
14642 | ||
14643 | /* | |
14644 | * If the fb is shared between multiple heads, we'll | |
14645 | * just get the first one. | |
14646 | */ | |
14647 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 14648 | } |
d93c0372 MR |
14649 | |
14650 | /* | |
14651 | * Make sure hardware watermarks really match the state we read out. | |
14652 | * Note that we need to do this after reconstructing the BIOS fb's | |
14653 | * since the watermark calculation done here will use pstate->fb. | |
14654 | */ | |
602ae835 VS |
14655 | if (!HAS_GMCH_DISPLAY(dev_priv)) |
14656 | sanitize_watermarks(dev); | |
b079bd17 VS |
14657 | |
14658 | return 0; | |
2c7111db CW |
14659 | } |
14660 | ||
2ee0da16 VS |
14661 | void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) |
14662 | { | |
14663 | /* 640x480@60Hz, ~25175 kHz */ | |
14664 | struct dpll clock = { | |
14665 | .m1 = 18, | |
14666 | .m2 = 7, | |
14667 | .p1 = 13, | |
14668 | .p2 = 4, | |
14669 | .n = 2, | |
14670 | }; | |
14671 | u32 dpll, fp; | |
14672 | int i; | |
14673 | ||
14674 | WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154); | |
14675 | ||
14676 | DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n", | |
14677 | pipe_name(pipe), clock.vco, clock.dot); | |
14678 | ||
14679 | fp = i9xx_dpll_compute_fp(&clock); | |
14680 | dpll = (I915_READ(DPLL(pipe)) & DPLL_DVO_2X_MODE) | | |
14681 | DPLL_VGA_MODE_DIS | | |
14682 | ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) | | |
14683 | PLL_P2_DIVIDE_BY_4 | | |
14684 | PLL_REF_INPUT_DREFCLK | | |
14685 | DPLL_VCO_ENABLE; | |
14686 | ||
14687 | I915_WRITE(FP0(pipe), fp); | |
14688 | I915_WRITE(FP1(pipe), fp); | |
14689 | ||
14690 | I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16)); | |
14691 | I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16)); | |
14692 | I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16)); | |
14693 | I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16)); | |
14694 | I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16)); | |
14695 | I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16)); | |
14696 | I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1)); | |
14697 | ||
14698 | /* | |
14699 | * Apparently we need to have VGA mode enabled prior to changing | |
14700 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
14701 | * dividers, even though the register value does change. | |
14702 | */ | |
14703 | I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); | |
14704 | I915_WRITE(DPLL(pipe), dpll); | |
14705 | ||
14706 | /* Wait for the clocks to stabilize. */ | |
14707 | POSTING_READ(DPLL(pipe)); | |
14708 | udelay(150); | |
14709 | ||
14710 | /* The pixel multiplier can only be updated once the | |
14711 | * DPLL is enabled and the clocks are stable. | |
14712 | * | |
14713 | * So write it again. | |
14714 | */ | |
14715 | I915_WRITE(DPLL(pipe), dpll); | |
14716 | ||
14717 | /* We do this three times for luck */ | |
14718 | for (i = 0; i < 3 ; i++) { | |
14719 | I915_WRITE(DPLL(pipe), dpll); | |
14720 | POSTING_READ(DPLL(pipe)); | |
14721 | udelay(150); /* wait for warmup */ | |
14722 | } | |
14723 | ||
14724 | I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE); | |
14725 | POSTING_READ(PIPECONF(pipe)); | |
14726 | } | |
14727 | ||
14728 | void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) | |
14729 | { | |
14730 | DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n", | |
14731 | pipe_name(pipe)); | |
14732 | ||
14733 | assert_plane_disabled(dev_priv, PLANE_A); | |
14734 | assert_plane_disabled(dev_priv, PLANE_B); | |
14735 | ||
14736 | I915_WRITE(PIPECONF(pipe), 0); | |
14737 | POSTING_READ(PIPECONF(pipe)); | |
14738 | ||
14739 | if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100)) | |
14740 | DRM_ERROR("pipe %c off wait timed out\n", pipe_name(pipe)); | |
14741 | ||
14742 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); | |
14743 | POSTING_READ(DPLL(pipe)); | |
14744 | } | |
14745 | ||
fa555837 DV |
14746 | static bool |
14747 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
14748 | { | |
b7f05d4a | 14749 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
649636ef | 14750 | u32 val; |
fa555837 | 14751 | |
b7f05d4a | 14752 | if (INTEL_INFO(dev_priv)->num_pipes == 1) |
fa555837 DV |
14753 | return true; |
14754 | ||
649636ef | 14755 | val = I915_READ(DSPCNTR(!crtc->plane)); |
fa555837 DV |
14756 | |
14757 | if ((val & DISPLAY_PLANE_ENABLE) && | |
14758 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
14759 | return false; | |
14760 | ||
14761 | return true; | |
14762 | } | |
14763 | ||
02e93c35 VS |
14764 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
14765 | { | |
14766 | struct drm_device *dev = crtc->base.dev; | |
14767 | struct intel_encoder *encoder; | |
14768 | ||
14769 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
14770 | return true; | |
14771 | ||
14772 | return false; | |
14773 | } | |
14774 | ||
496b0fc3 ML |
14775 | static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder) |
14776 | { | |
14777 | struct drm_device *dev = encoder->base.dev; | |
14778 | struct intel_connector *connector; | |
14779 | ||
14780 | for_each_connector_on_encoder(dev, &encoder->base, connector) | |
14781 | return connector; | |
14782 | ||
14783 | return NULL; | |
14784 | } | |
14785 | ||
a168f5b3 VS |
14786 | static bool has_pch_trancoder(struct drm_i915_private *dev_priv, |
14787 | enum transcoder pch_transcoder) | |
14788 | { | |
14789 | return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) || | |
14790 | (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A); | |
14791 | } | |
14792 | ||
aecd36b8 VS |
14793 | static void intel_sanitize_crtc(struct intel_crtc *crtc, |
14794 | struct drm_modeset_acquire_ctx *ctx) | |
24929352 DV |
14795 | { |
14796 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 14797 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 | 14798 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
24929352 | 14799 | |
24929352 | 14800 | /* Clear any frame start delays used for debugging left by the BIOS */ |
4d1de975 JN |
14801 | if (!transcoder_is_dsi(cpu_transcoder)) { |
14802 | i915_reg_t reg = PIPECONF(cpu_transcoder); | |
14803 | ||
14804 | I915_WRITE(reg, | |
14805 | I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); | |
14806 | } | |
24929352 | 14807 | |
d3eaf884 | 14808 | /* restore vblank interrupts to correct state */ |
9625604c | 14809 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 14810 | if (crtc->active) { |
f9cd7b88 VS |
14811 | struct intel_plane *plane; |
14812 | ||
9625604c | 14813 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
14814 | |
14815 | /* Disable everything but the primary plane */ | |
14816 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
14817 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
14818 | continue; | |
14819 | ||
72259536 | 14820 | trace_intel_disable_plane(&plane->base, crtc); |
282dbf9b | 14821 | plane->disable_plane(plane, crtc); |
f9cd7b88 | 14822 | } |
9625604c | 14823 | } |
d3eaf884 | 14824 | |
24929352 | 14825 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
14826 | * disable the crtc (and hence change the state) if it is wrong. Note |
14827 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
6315b5d3 | 14828 | if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) { |
24929352 DV |
14829 | bool plane; |
14830 | ||
78108b7c VS |
14831 | DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n", |
14832 | crtc->base.base.id, crtc->base.name); | |
24929352 DV |
14833 | |
14834 | /* Pipe has the wrong plane attached and the plane is active. | |
14835 | * Temporarily change the plane mapping and disable everything | |
14836 | * ... */ | |
14837 | plane = crtc->plane; | |
1d4258db | 14838 | crtc->base.primary->state->visible = true; |
24929352 | 14839 | crtc->plane = !plane; |
da1d0e26 | 14840 | intel_crtc_disable_noatomic(&crtc->base, ctx); |
24929352 | 14841 | crtc->plane = plane; |
24929352 | 14842 | } |
24929352 DV |
14843 | |
14844 | /* Adjust the state of the output pipe according to whether we | |
14845 | * have active connectors/encoders. */ | |
842e0307 | 14846 | if (crtc->active && !intel_crtc_has_encoders(crtc)) |
da1d0e26 | 14847 | intel_crtc_disable_noatomic(&crtc->base, ctx); |
24929352 | 14848 | |
49cff963 | 14849 | if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) { |
4cc31489 DV |
14850 | /* |
14851 | * We start out with underrun reporting disabled to avoid races. | |
14852 | * For correct bookkeeping mark this on active crtcs. | |
14853 | * | |
c5ab3bc0 DV |
14854 | * Also on gmch platforms we dont have any hardware bits to |
14855 | * disable the underrun reporting. Which means we need to start | |
14856 | * out with underrun reporting disabled also on inactive pipes, | |
14857 | * since otherwise we'll complain about the garbage we read when | |
14858 | * e.g. coming up after runtime pm. | |
14859 | * | |
4cc31489 DV |
14860 | * No protection against concurrent access is required - at |
14861 | * worst a fifo underrun happens which also sets this to false. | |
14862 | */ | |
14863 | crtc->cpu_fifo_underrun_disabled = true; | |
a168f5b3 VS |
14864 | /* |
14865 | * We track the PCH trancoder underrun reporting state | |
14866 | * within the crtc. With crtc for pipe A housing the underrun | |
14867 | * reporting state for PCH transcoder A, crtc for pipe B housing | |
14868 | * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A, | |
14869 | * and marking underrun reporting as disabled for the non-existing | |
14870 | * PCH transcoders B and C would prevent enabling the south | |
14871 | * error interrupt (see cpt_can_enable_serr_int()). | |
14872 | */ | |
14873 | if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe)) | |
14874 | crtc->pch_fifo_underrun_disabled = true; | |
4cc31489 | 14875 | } |
24929352 DV |
14876 | } |
14877 | ||
14878 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
14879 | { | |
14880 | struct intel_connector *connector; | |
24929352 DV |
14881 | |
14882 | /* We need to check both for a crtc link (meaning that the | |
14883 | * encoder is active and trying to read from a pipe) and the | |
14884 | * pipe itself being active. */ | |
14885 | bool has_active_crtc = encoder->base.crtc && | |
14886 | to_intel_crtc(encoder->base.crtc)->active; | |
14887 | ||
496b0fc3 ML |
14888 | connector = intel_encoder_find_connector(encoder); |
14889 | if (connector && !has_active_crtc) { | |
24929352 DV |
14890 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
14891 | encoder->base.base.id, | |
8e329a03 | 14892 | encoder->base.name); |
24929352 DV |
14893 | |
14894 | /* Connector is active, but has no active pipe. This is | |
14895 | * fallout from our resume register restoring. Disable | |
14896 | * the encoder manually again. */ | |
14897 | if (encoder->base.crtc) { | |
fd6bbda9 ML |
14898 | struct drm_crtc_state *crtc_state = encoder->base.crtc->state; |
14899 | ||
24929352 DV |
14900 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", |
14901 | encoder->base.base.id, | |
8e329a03 | 14902 | encoder->base.name); |
fd6bbda9 | 14903 | encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state); |
a62d1497 | 14904 | if (encoder->post_disable) |
fd6bbda9 | 14905 | encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state); |
24929352 | 14906 | } |
7f1950fb | 14907 | encoder->base.crtc = NULL; |
24929352 DV |
14908 | |
14909 | /* Inconsistent output/port/pipe state happens presumably due to | |
14910 | * a bug in one of the get_hw_state functions. Or someplace else | |
14911 | * in our code, like the register restore mess on resume. Clamp | |
14912 | * things to off as a safer default. */ | |
fd6bbda9 ML |
14913 | |
14914 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
14915 | connector->base.encoder = NULL; | |
24929352 DV |
14916 | } |
14917 | /* Enabled encoders without active connectors will be fixed in | |
14918 | * the crtc fixup. */ | |
14919 | } | |
14920 | ||
29b74b7f | 14921 | void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv) |
0fde901f | 14922 | { |
920a14b2 | 14923 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv); |
0fde901f | 14924 | |
04098753 ID |
14925 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
14926 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
29b74b7f | 14927 | i915_disable_vga(dev_priv); |
04098753 ID |
14928 | } |
14929 | } | |
14930 | ||
29b74b7f | 14931 | void i915_redisable_vga(struct drm_i915_private *dev_priv) |
04098753 | 14932 | { |
8dc8a27c PZ |
14933 | /* This function can be called both from intel_modeset_setup_hw_state or |
14934 | * at a very early point in our resume sequence, where the power well | |
14935 | * structures are not yet restored. Since this function is at a very | |
14936 | * paranoid "someone might have enabled VGA while we were not looking" | |
14937 | * level, just check if the power well is enabled instead of trying to | |
14938 | * follow the "don't touch the power well if we don't need it" policy | |
14939 | * the rest of the driver uses. */ | |
6392f847 | 14940 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
14941 | return; |
14942 | ||
29b74b7f | 14943 | i915_redisable_vga_power_on(dev_priv); |
6392f847 ID |
14944 | |
14945 | intel_display_power_put(dev_priv, POWER_DOMAIN_VGA); | |
0fde901f KM |
14946 | } |
14947 | ||
f9cd7b88 | 14948 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 14949 | { |
f9cd7b88 | 14950 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 14951 | |
f9cd7b88 | 14952 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
14953 | } |
14954 | ||
f9cd7b88 VS |
14955 | /* FIXME read out full plane state for all planes */ |
14956 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 14957 | { |
e9728bd8 VS |
14958 | struct intel_plane *primary = to_intel_plane(crtc->base.primary); |
14959 | bool visible; | |
d032ffa0 | 14960 | |
e9728bd8 | 14961 | visible = crtc->active && primary_get_hw_state(primary); |
b26d3ea3 | 14962 | |
e9728bd8 VS |
14963 | intel_set_plane_visible(to_intel_crtc_state(crtc->base.state), |
14964 | to_intel_plane_state(primary->base.state), | |
14965 | visible); | |
98ec7739 VS |
14966 | } |
14967 | ||
30e984df | 14968 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 | 14969 | { |
fac5e23e | 14970 | struct drm_i915_private *dev_priv = to_i915(dev); |
24929352 | 14971 | enum pipe pipe; |
24929352 DV |
14972 | struct intel_crtc *crtc; |
14973 | struct intel_encoder *encoder; | |
14974 | struct intel_connector *connector; | |
f9e905ca | 14975 | struct drm_connector_list_iter conn_iter; |
5358901f | 14976 | int i; |
24929352 | 14977 | |
565602d7 ML |
14978 | dev_priv->active_crtcs = 0; |
14979 | ||
d3fcc808 | 14980 | for_each_intel_crtc(dev, crtc) { |
a8cd6da0 VS |
14981 | struct intel_crtc_state *crtc_state = |
14982 | to_intel_crtc_state(crtc->base.state); | |
3b117c8f | 14983 | |
ec2dc6a0 | 14984 | __drm_atomic_helper_crtc_destroy_state(&crtc_state->base); |
565602d7 ML |
14985 | memset(crtc_state, 0, sizeof(*crtc_state)); |
14986 | crtc_state->base.crtc = &crtc->base; | |
24929352 | 14987 | |
565602d7 ML |
14988 | crtc_state->base.active = crtc_state->base.enable = |
14989 | dev_priv->display.get_pipe_config(crtc, crtc_state); | |
14990 | ||
14991 | crtc->base.enabled = crtc_state->base.enable; | |
14992 | crtc->active = crtc_state->base.active; | |
14993 | ||
aca1ebf4 | 14994 | if (crtc_state->base.active) |
565602d7 ML |
14995 | dev_priv->active_crtcs |= 1 << crtc->pipe; |
14996 | ||
f9cd7b88 | 14997 | readout_plane_state(crtc); |
24929352 | 14998 | |
78108b7c VS |
14999 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n", |
15000 | crtc->base.base.id, crtc->base.name, | |
a8cd6da0 | 15001 | enableddisabled(crtc_state->base.active)); |
24929352 DV |
15002 | } |
15003 | ||
5358901f DV |
15004 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15005 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15006 | ||
2edd6443 | 15007 | pll->on = pll->funcs.get_hw_state(dev_priv, pll, |
2c42e535 ACO |
15008 | &pll->state.hw_state); |
15009 | pll->state.crtc_mask = 0; | |
d3fcc808 | 15010 | for_each_intel_crtc(dev, crtc) { |
a8cd6da0 VS |
15011 | struct intel_crtc_state *crtc_state = |
15012 | to_intel_crtc_state(crtc->base.state); | |
15013 | ||
15014 | if (crtc_state->base.active && | |
15015 | crtc_state->shared_dpll == pll) | |
2c42e535 | 15016 | pll->state.crtc_mask |= 1 << crtc->pipe; |
5358901f | 15017 | } |
2c42e535 | 15018 | pll->active_mask = pll->state.crtc_mask; |
5358901f | 15019 | |
1e6f2ddc | 15020 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
2c42e535 | 15021 | pll->name, pll->state.crtc_mask, pll->on); |
5358901f DV |
15022 | } |
15023 | ||
b2784e15 | 15024 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15025 | pipe = 0; |
15026 | ||
15027 | if (encoder->get_hw_state(encoder, &pipe)) { | |
a8cd6da0 VS |
15028 | struct intel_crtc_state *crtc_state; |
15029 | ||
98187836 | 15030 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
a8cd6da0 | 15031 | crtc_state = to_intel_crtc_state(crtc->base.state); |
e2af48c6 | 15032 | |
045ac3b5 | 15033 | encoder->base.crtc = &crtc->base; |
a8cd6da0 VS |
15034 | crtc_state->output_types |= 1 << encoder->type; |
15035 | encoder->get_config(encoder, crtc_state); | |
24929352 DV |
15036 | } else { |
15037 | encoder->base.crtc = NULL; | |
15038 | } | |
15039 | ||
6f2bcceb | 15040 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
08c4d7fc TU |
15041 | encoder->base.base.id, encoder->base.name, |
15042 | enableddisabled(encoder->base.crtc), | |
6f2bcceb | 15043 | pipe_name(pipe)); |
24929352 DV |
15044 | } |
15045 | ||
f9e905ca DV |
15046 | drm_connector_list_iter_begin(dev, &conn_iter); |
15047 | for_each_intel_connector_iter(connector, &conn_iter) { | |
24929352 DV |
15048 | if (connector->get_hw_state(connector)) { |
15049 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
2aa974c9 ML |
15050 | |
15051 | encoder = connector->encoder; | |
15052 | connector->base.encoder = &encoder->base; | |
15053 | ||
15054 | if (encoder->base.crtc && | |
15055 | encoder->base.crtc->state->active) { | |
15056 | /* | |
15057 | * This has to be done during hardware readout | |
15058 | * because anything calling .crtc_disable may | |
15059 | * rely on the connector_mask being accurate. | |
15060 | */ | |
15061 | encoder->base.crtc->state->connector_mask |= | |
15062 | 1 << drm_connector_index(&connector->base); | |
e87a52b3 ML |
15063 | encoder->base.crtc->state->encoder_mask |= |
15064 | 1 << drm_encoder_index(&encoder->base); | |
2aa974c9 ML |
15065 | } |
15066 | ||
24929352 DV |
15067 | } else { |
15068 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
15069 | connector->base.encoder = NULL; | |
15070 | } | |
15071 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
08c4d7fc TU |
15072 | connector->base.base.id, connector->base.name, |
15073 | enableddisabled(connector->base.encoder)); | |
24929352 | 15074 | } |
f9e905ca | 15075 | drm_connector_list_iter_end(&conn_iter); |
7f4c6284 VS |
15076 | |
15077 | for_each_intel_crtc(dev, crtc) { | |
a8cd6da0 VS |
15078 | struct intel_crtc_state *crtc_state = |
15079 | to_intel_crtc_state(crtc->base.state); | |
aca1ebf4 VS |
15080 | int pixclk = 0; |
15081 | ||
7f4c6284 | 15082 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); |
a8cd6da0 VS |
15083 | if (crtc_state->base.active) { |
15084 | intel_mode_from_pipe_config(&crtc->base.mode, crtc_state); | |
15085 | intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state); | |
7f4c6284 VS |
15086 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); |
15087 | ||
15088 | /* | |
15089 | * The initial mode needs to be set in order to keep | |
15090 | * the atomic core happy. It wants a valid mode if the | |
15091 | * crtc's enabled, so we do the above call. | |
15092 | * | |
7800fb69 DV |
15093 | * But we don't set all the derived state fully, hence |
15094 | * set a flag to indicate that a full recalculation is | |
15095 | * needed on the next commit. | |
7f4c6284 | 15096 | */ |
a8cd6da0 | 15097 | crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED; |
9eca6832 | 15098 | |
a7d1b3f4 VS |
15099 | intel_crtc_compute_pixel_rate(crtc_state); |
15100 | ||
15101 | if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv) || | |
15102 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
15103 | pixclk = crtc_state->pixel_rate; | |
aca1ebf4 VS |
15104 | else |
15105 | WARN_ON(dev_priv->display.modeset_calc_cdclk); | |
15106 | ||
15107 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
a8cd6da0 | 15108 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) |
aca1ebf4 VS |
15109 | pixclk = DIV_ROUND_UP(pixclk * 100, 95); |
15110 | ||
5caa0fea DV |
15111 | drm_calc_timestamping_constants(&crtc->base, |
15112 | &crtc_state->base.adjusted_mode); | |
9eca6832 | 15113 | update_scanline_offset(crtc); |
7f4c6284 | 15114 | } |
e3b247da | 15115 | |
aca1ebf4 VS |
15116 | dev_priv->min_pixclk[crtc->pipe] = pixclk; |
15117 | ||
a8cd6da0 | 15118 | intel_pipe_config_sanity_check(dev_priv, crtc_state); |
7f4c6284 | 15119 | } |
30e984df DV |
15120 | } |
15121 | ||
62b69566 ACO |
15122 | static void |
15123 | get_encoder_power_domains(struct drm_i915_private *dev_priv) | |
15124 | { | |
15125 | struct intel_encoder *encoder; | |
15126 | ||
15127 | for_each_intel_encoder(&dev_priv->drm, encoder) { | |
15128 | u64 get_domains; | |
15129 | enum intel_display_power_domain domain; | |
15130 | ||
15131 | if (!encoder->get_power_domains) | |
15132 | continue; | |
15133 | ||
15134 | get_domains = encoder->get_power_domains(encoder); | |
15135 | for_each_power_domain(domain, get_domains) | |
15136 | intel_display_power_get(dev_priv, domain); | |
15137 | } | |
15138 | } | |
15139 | ||
043e9bda ML |
15140 | /* Scan out the current hw modeset state, |
15141 | * and sanitizes it to the current state | |
15142 | */ | |
15143 | static void | |
aecd36b8 VS |
15144 | intel_modeset_setup_hw_state(struct drm_device *dev, |
15145 | struct drm_modeset_acquire_ctx *ctx) | |
30e984df | 15146 | { |
fac5e23e | 15147 | struct drm_i915_private *dev_priv = to_i915(dev); |
30e984df | 15148 | enum pipe pipe; |
30e984df DV |
15149 | struct intel_crtc *crtc; |
15150 | struct intel_encoder *encoder; | |
35c95375 | 15151 | int i; |
30e984df DV |
15152 | |
15153 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
15154 | |
15155 | /* HW state is read out, now we need to sanitize this mess. */ | |
62b69566 ACO |
15156 | get_encoder_power_domains(dev_priv); |
15157 | ||
b2784e15 | 15158 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15159 | intel_sanitize_encoder(encoder); |
15160 | } | |
15161 | ||
055e393f | 15162 | for_each_pipe(dev_priv, pipe) { |
98187836 | 15163 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
e2af48c6 | 15164 | |
aecd36b8 | 15165 | intel_sanitize_crtc(crtc, ctx); |
6e3c9717 ACO |
15166 | intel_dump_pipe_config(crtc, crtc->config, |
15167 | "[setup_hw_state]"); | |
24929352 | 15168 | } |
9a935856 | 15169 | |
d29b2f9d ACO |
15170 | intel_modeset_update_connector_atomic_state(dev); |
15171 | ||
35c95375 DV |
15172 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15173 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15174 | ||
2dd66ebd | 15175 | if (!pll->on || pll->active_mask) |
35c95375 DV |
15176 | continue; |
15177 | ||
15178 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
15179 | ||
2edd6443 | 15180 | pll->funcs.disable(dev_priv, pll); |
35c95375 DV |
15181 | pll->on = false; |
15182 | } | |
15183 | ||
04548cba VS |
15184 | if (IS_G4X(dev_priv)) { |
15185 | g4x_wm_get_hw_state(dev); | |
15186 | g4x_wm_sanitize(dev_priv); | |
15187 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
6eb1a681 | 15188 | vlv_wm_get_hw_state(dev); |
602ae835 | 15189 | vlv_wm_sanitize(dev_priv); |
a029fa4d | 15190 | } else if (INTEL_GEN(dev_priv) >= 9) { |
3078999f | 15191 | skl_wm_get_hw_state(dev); |
602ae835 | 15192 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
243e6a44 | 15193 | ilk_wm_get_hw_state(dev); |
602ae835 | 15194 | } |
292b990e ML |
15195 | |
15196 | for_each_intel_crtc(dev, crtc) { | |
d8fc70b7 | 15197 | u64 put_domains; |
292b990e | 15198 | |
74bff5f9 | 15199 | put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config); |
292b990e ML |
15200 | if (WARN_ON(put_domains)) |
15201 | modeset_put_power_domains(dev_priv, put_domains); | |
15202 | } | |
15203 | intel_display_set_init_power(dev_priv, false); | |
010cf73d | 15204 | |
8d8c386c ID |
15205 | intel_power_domains_verify_state(dev_priv); |
15206 | ||
010cf73d | 15207 | intel_fbc_init_pipe_state(dev_priv); |
043e9bda | 15208 | } |
7d0bc1ea | 15209 | |
043e9bda ML |
15210 | void intel_display_resume(struct drm_device *dev) |
15211 | { | |
e2c8b870 ML |
15212 | struct drm_i915_private *dev_priv = to_i915(dev); |
15213 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
15214 | struct drm_modeset_acquire_ctx ctx; | |
043e9bda | 15215 | int ret; |
f30da187 | 15216 | |
e2c8b870 | 15217 | dev_priv->modeset_restore_state = NULL; |
73974893 ML |
15218 | if (state) |
15219 | state->acquire_ctx = &ctx; | |
043e9bda | 15220 | |
e2c8b870 | 15221 | drm_modeset_acquire_init(&ctx, 0); |
043e9bda | 15222 | |
73974893 ML |
15223 | while (1) { |
15224 | ret = drm_modeset_lock_all_ctx(dev, &ctx); | |
15225 | if (ret != -EDEADLK) | |
15226 | break; | |
043e9bda | 15227 | |
e2c8b870 | 15228 | drm_modeset_backoff(&ctx); |
e2c8b870 | 15229 | } |
043e9bda | 15230 | |
73974893 | 15231 | if (!ret) |
581e49fe | 15232 | ret = __intel_display_resume(dev, state, &ctx); |
73974893 | 15233 | |
e2c8b870 ML |
15234 | drm_modeset_drop_locks(&ctx); |
15235 | drm_modeset_acquire_fini(&ctx); | |
043e9bda | 15236 | |
0853695c | 15237 | if (ret) |
e2c8b870 | 15238 | DRM_ERROR("Restoring old state failed with %i\n", ret); |
3c5e37f1 CW |
15239 | if (state) |
15240 | drm_atomic_state_put(state); | |
2c7111db CW |
15241 | } |
15242 | ||
15243 | void intel_modeset_gem_init(struct drm_device *dev) | |
15244 | { | |
dc97997a | 15245 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd | 15246 | |
dc97997a | 15247 | intel_init_gt_powersave(dev_priv); |
ae48434c | 15248 | |
1ee8da6d | 15249 | intel_setup_overlay(dev_priv); |
1ebaa0b9 CW |
15250 | } |
15251 | ||
15252 | int intel_connector_register(struct drm_connector *connector) | |
15253 | { | |
15254 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
15255 | int ret; | |
15256 | ||
15257 | ret = intel_backlight_device_register(intel_connector); | |
15258 | if (ret) | |
15259 | goto err; | |
15260 | ||
15261 | return 0; | |
0962c3c9 | 15262 | |
1ebaa0b9 CW |
15263 | err: |
15264 | return ret; | |
79e53945 JB |
15265 | } |
15266 | ||
c191eca1 | 15267 | void intel_connector_unregister(struct drm_connector *connector) |
4932e2c3 | 15268 | { |
e63d87c0 | 15269 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4932e2c3 | 15270 | |
e63d87c0 | 15271 | intel_backlight_device_unregister(intel_connector); |
4932e2c3 | 15272 | intel_panel_destroy_backlight(connector); |
4932e2c3 ID |
15273 | } |
15274 | ||
79e53945 JB |
15275 | void intel_modeset_cleanup(struct drm_device *dev) |
15276 | { | |
fac5e23e | 15277 | struct drm_i915_private *dev_priv = to_i915(dev); |
652c393a | 15278 | |
eb955eee CW |
15279 | flush_work(&dev_priv->atomic_helper.free_work); |
15280 | WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list)); | |
15281 | ||
dc97997a | 15282 | intel_disable_gt_powersave(dev_priv); |
2eb5252e | 15283 | |
fd0c0642 DV |
15284 | /* |
15285 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 15286 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
15287 | * experience fancy races otherwise. |
15288 | */ | |
2aeb7d3a | 15289 | intel_irq_uninstall(dev_priv); |
eb21b92b | 15290 | |
fd0c0642 DV |
15291 | /* |
15292 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
15293 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
15294 | */ | |
f87ea761 | 15295 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 15296 | |
4f256d82 DV |
15297 | /* poll work can call into fbdev, hence clean that up afterwards */ |
15298 | intel_fbdev_fini(dev_priv); | |
15299 | ||
723bfd70 JB |
15300 | intel_unregister_dsm_handler(); |
15301 | ||
c937ab3e | 15302 | intel_fbc_global_disable(dev_priv); |
69341a5e | 15303 | |
1630fe75 CW |
15304 | /* flush any delayed tasks or pending work */ |
15305 | flush_scheduled_work(); | |
15306 | ||
79e53945 | 15307 | drm_mode_config_cleanup(dev); |
4d7bb011 | 15308 | |
1ee8da6d | 15309 | intel_cleanup_overlay(dev_priv); |
ae48434c | 15310 | |
dc97997a | 15311 | intel_cleanup_gt_powersave(dev_priv); |
f5949141 | 15312 | |
40196446 | 15313 | intel_teardown_gmbus(dev_priv); |
79e53945 JB |
15314 | } |
15315 | ||
df0e9248 CW |
15316 | void intel_connector_attach_encoder(struct intel_connector *connector, |
15317 | struct intel_encoder *encoder) | |
15318 | { | |
15319 | connector->encoder = encoder; | |
15320 | drm_mode_connector_attach_encoder(&connector->base, | |
15321 | &encoder->base); | |
79e53945 | 15322 | } |
28d52043 DA |
15323 | |
15324 | /* | |
15325 | * set vga decode state - true == enable VGA decode | |
15326 | */ | |
6315b5d3 | 15327 | int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state) |
28d52043 | 15328 | { |
6315b5d3 | 15329 | unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
15330 | u16 gmch_ctrl; |
15331 | ||
75fa041d CW |
15332 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
15333 | DRM_ERROR("failed to read control word\n"); | |
15334 | return -EIO; | |
15335 | } | |
15336 | ||
c0cc8a55 CW |
15337 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
15338 | return 0; | |
15339 | ||
28d52043 DA |
15340 | if (state) |
15341 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
15342 | else | |
15343 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
15344 | |
15345 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
15346 | DRM_ERROR("failed to write control word\n"); | |
15347 | return -EIO; | |
15348 | } | |
15349 | ||
28d52043 DA |
15350 | return 0; |
15351 | } | |
c4a1d9e4 | 15352 | |
98a2f411 CW |
15353 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
15354 | ||
c4a1d9e4 | 15355 | struct intel_display_error_state { |
ff57f1b0 PZ |
15356 | |
15357 | u32 power_well_driver; | |
15358 | ||
63b66e5b CW |
15359 | int num_transcoders; |
15360 | ||
c4a1d9e4 CW |
15361 | struct intel_cursor_error_state { |
15362 | u32 control; | |
15363 | u32 position; | |
15364 | u32 base; | |
15365 | u32 size; | |
52331309 | 15366 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15367 | |
15368 | struct intel_pipe_error_state { | |
ddf9c536 | 15369 | bool power_domain_on; |
c4a1d9e4 | 15370 | u32 source; |
f301b1e1 | 15371 | u32 stat; |
52331309 | 15372 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15373 | |
15374 | struct intel_plane_error_state { | |
15375 | u32 control; | |
15376 | u32 stride; | |
15377 | u32 size; | |
15378 | u32 pos; | |
15379 | u32 addr; | |
15380 | u32 surface; | |
15381 | u32 tile_offset; | |
52331309 | 15382 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
15383 | |
15384 | struct intel_transcoder_error_state { | |
ddf9c536 | 15385 | bool power_domain_on; |
63b66e5b CW |
15386 | enum transcoder cpu_transcoder; |
15387 | ||
15388 | u32 conf; | |
15389 | ||
15390 | u32 htotal; | |
15391 | u32 hblank; | |
15392 | u32 hsync; | |
15393 | u32 vtotal; | |
15394 | u32 vblank; | |
15395 | u32 vsync; | |
15396 | } transcoder[4]; | |
c4a1d9e4 CW |
15397 | }; |
15398 | ||
15399 | struct intel_display_error_state * | |
c033666a | 15400 | intel_display_capture_error_state(struct drm_i915_private *dev_priv) |
c4a1d9e4 | 15401 | { |
c4a1d9e4 | 15402 | struct intel_display_error_state *error; |
63b66e5b CW |
15403 | int transcoders[] = { |
15404 | TRANSCODER_A, | |
15405 | TRANSCODER_B, | |
15406 | TRANSCODER_C, | |
15407 | TRANSCODER_EDP, | |
15408 | }; | |
c4a1d9e4 CW |
15409 | int i; |
15410 | ||
c033666a | 15411 | if (INTEL_INFO(dev_priv)->num_pipes == 0) |
63b66e5b CW |
15412 | return NULL; |
15413 | ||
9d1cb914 | 15414 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
15415 | if (error == NULL) |
15416 | return NULL; | |
15417 | ||
c033666a | 15418 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
9c3a16c8 ID |
15419 | error->power_well_driver = |
15420 | I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL)); | |
ff57f1b0 | 15421 | |
055e393f | 15422 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 15423 | error->pipe[i].power_domain_on = |
f458ebbc DV |
15424 | __intel_display_power_is_enabled(dev_priv, |
15425 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 15426 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
15427 | continue; |
15428 | ||
5efb3e28 VS |
15429 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
15430 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
15431 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
15432 | |
15433 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
15434 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
c033666a | 15435 | if (INTEL_GEN(dev_priv) <= 3) { |
51889b35 | 15436 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
15437 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
15438 | } | |
c033666a | 15439 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
ca291363 | 15440 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
c033666a | 15441 | if (INTEL_GEN(dev_priv) >= 4) { |
c4a1d9e4 CW |
15442 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
15443 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
15444 | } | |
15445 | ||
c4a1d9e4 | 15446 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 15447 | |
c033666a | 15448 | if (HAS_GMCH_DISPLAY(dev_priv)) |
f301b1e1 | 15449 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
15450 | } |
15451 | ||
4d1de975 | 15452 | /* Note: this does not include DSI transcoders. */ |
c033666a | 15453 | error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes; |
2d1fe073 | 15454 | if (HAS_DDI(dev_priv)) |
63b66e5b CW |
15455 | error->num_transcoders++; /* Account for eDP. */ |
15456 | ||
15457 | for (i = 0; i < error->num_transcoders; i++) { | |
15458 | enum transcoder cpu_transcoder = transcoders[i]; | |
15459 | ||
ddf9c536 | 15460 | error->transcoder[i].power_domain_on = |
f458ebbc | 15461 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 15462 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 15463 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
15464 | continue; |
15465 | ||
63b66e5b CW |
15466 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
15467 | ||
15468 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
15469 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
15470 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
15471 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
15472 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
15473 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
15474 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
15475 | } |
15476 | ||
15477 | return error; | |
15478 | } | |
15479 | ||
edc3d884 MK |
15480 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
15481 | ||
c4a1d9e4 | 15482 | void |
edc3d884 | 15483 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
15484 | struct intel_display_error_state *error) |
15485 | { | |
5a4c6f1b | 15486 | struct drm_i915_private *dev_priv = m->i915; |
c4a1d9e4 CW |
15487 | int i; |
15488 | ||
63b66e5b CW |
15489 | if (!error) |
15490 | return; | |
15491 | ||
b7f05d4a | 15492 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes); |
8652744b | 15493 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
edc3d884 | 15494 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 15495 | error->power_well_driver); |
055e393f | 15496 | for_each_pipe(dev_priv, i) { |
edc3d884 | 15497 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 | 15498 | err_printf(m, " Power: %s\n", |
87ad3212 | 15499 | onoff(error->pipe[i].power_domain_on)); |
edc3d884 | 15500 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 15501 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
15502 | |
15503 | err_printf(m, "Plane [%d]:\n", i); | |
15504 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
15505 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
5f56d5f9 | 15506 | if (INTEL_GEN(dev_priv) <= 3) { |
edc3d884 MK |
15507 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
15508 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 15509 | } |
772c2a51 | 15510 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
edc3d884 | 15511 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
5f56d5f9 | 15512 | if (INTEL_GEN(dev_priv) >= 4) { |
edc3d884 MK |
15513 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
15514 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
15515 | } |
15516 | ||
edc3d884 MK |
15517 | err_printf(m, "Cursor [%d]:\n", i); |
15518 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
15519 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
15520 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 15521 | } |
63b66e5b CW |
15522 | |
15523 | for (i = 0; i < error->num_transcoders; i++) { | |
da205630 | 15524 | err_printf(m, "CPU transcoder: %s\n", |
63b66e5b | 15525 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 | 15526 | err_printf(m, " Power: %s\n", |
87ad3212 | 15527 | onoff(error->transcoder[i].power_domain_on)); |
63b66e5b CW |
15528 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
15529 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
15530 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
15531 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
15532 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
15533 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
15534 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
15535 | } | |
c4a1d9e4 | 15536 | } |
98a2f411 CW |
15537 | |
15538 | #endif |